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author | Michael Sevakis <jethead71@rockbox.org> | 2010-04-09 01:21:53 +0000 |
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committer | Michael Sevakis <jethead71@rockbox.org> | 2010-04-09 01:21:53 +0000 |
commit | 7abf2b53a462612808d46d6d77a7f35261a0e5a3 (patch) | |
tree | 241304f7cd2b5d1c2a9e091fe56a33d2d2f8e816 /firmware/target/arm/imx31/gigabeat-s/i2s-gigabeat-s.c | |
parent | 43304b87b0662d1619ac60e5297a1694aa580310 (diff) | |
download | rockbox-7abf2b53a462612808d46d6d77a7f35261a0e5a3.tar.gz rockbox-7abf2b53a462612808d46d6d77a7f35261a0e5a3.zip |
Gigabeat S/i.MX31: Sort files in the /target tree into things that are SoC-generic (into /imx31) and player-specific (into /gigabeat-s, based upon current appearances). Move i2s clock init into the appropriate file. Housekeeping only-- no functional changes.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25547 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/imx31/gigabeat-s/i2s-gigabeat-s.c')
-rw-r--r-- | firmware/target/arm/imx31/gigabeat-s/i2s-gigabeat-s.c | 45 |
1 files changed, 45 insertions, 0 deletions
diff --git a/firmware/target/arm/imx31/gigabeat-s/i2s-gigabeat-s.c b/firmware/target/arm/imx31/gigabeat-s/i2s-gigabeat-s.c new file mode 100644 index 0000000000..c2ec0d6cab --- /dev/null +++ b/firmware/target/arm/imx31/gigabeat-s/i2s-gigabeat-s.c | |||
@@ -0,0 +1,45 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2007 by Michael Sevakis | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | #include "config.h" | ||
22 | #include "system.h" | ||
23 | #include "i2s.h" | ||
24 | |||
25 | void i2s_reset(void) | ||
26 | { | ||
27 | /* How SYSCLK for codec is derived (USBPLL=338.688MHz). | ||
28 | * | ||
29 | * SSI post dividers (SSI2 PODF=4, SSI2 PRE PODF=0): | ||
30 | * 338688000Hz / 5 = 67737600Hz = ssi1_clk | ||
31 | * | ||
32 | * SSI bit clock dividers (DIV2=1, PSR=0, PM=0): | ||
33 | * ssi1_clk / 4 = 16934400Hz = INT_BIT_CLK (MCLK) | ||
34 | * | ||
35 | * WM Codec post divider (MCLKDIV=1.5): | ||
36 | * INT_BIT_CLK (MCLK) / 1.5 = 11289600Hz = 256*fs = SYSCLK | ||
37 | */ | ||
38 | imx31_regmod32(&CCM_PDR1, | ||
39 | ((1-1) << CCM_PDR1_SSI1_PRE_PODF_POS) | | ||
40 | ((5-1) << CCM_PDR1_SSI1_PODF_POS) | | ||
41 | ((8-1) << CCM_PDR1_SSI2_PRE_PODF_POS) | | ||
42 | ((64-1) << CCM_PDR1_SSI2_PODF_POS), | ||
43 | CCM_PDR1_SSI1_PODF | CCM_PDR1_SSI2_PODF | | ||
44 | CCM_PDR1_SSI1_PRE_PODF | CCM_PDR1_SSI2_PRE_PODF); | ||
45 | } | ||