From 7abf2b53a462612808d46d6d77a7f35261a0e5a3 Mon Sep 17 00:00:00 2001 From: Michael Sevakis Date: Fri, 9 Apr 2010 01:21:53 +0000 Subject: Gigabeat S/i.MX31: Sort files in the /target tree into things that are SoC-generic (into /imx31) and player-specific (into /gigabeat-s, based upon current appearances). Move i2s clock init into the appropriate file. Housekeeping only-- no functional changes. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25547 a1c6a512-1295-4272-9138-f99709370657 --- .../target/arm/imx31/gigabeat-s/i2s-gigabeat-s.c | 45 ++++++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 firmware/target/arm/imx31/gigabeat-s/i2s-gigabeat-s.c (limited to 'firmware/target/arm/imx31/gigabeat-s/i2s-gigabeat-s.c') diff --git a/firmware/target/arm/imx31/gigabeat-s/i2s-gigabeat-s.c b/firmware/target/arm/imx31/gigabeat-s/i2s-gigabeat-s.c new file mode 100644 index 0000000000..c2ec0d6cab --- /dev/null +++ b/firmware/target/arm/imx31/gigabeat-s/i2s-gigabeat-s.c @@ -0,0 +1,45 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * $Id$ + * + * Copyright (C) 2007 by Michael Sevakis + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ +#include "config.h" +#include "system.h" +#include "i2s.h" + +void i2s_reset(void) +{ + /* How SYSCLK for codec is derived (USBPLL=338.688MHz). + * + * SSI post dividers (SSI2 PODF=4, SSI2 PRE PODF=0): + * 338688000Hz / 5 = 67737600Hz = ssi1_clk + * + * SSI bit clock dividers (DIV2=1, PSR=0, PM=0): + * ssi1_clk / 4 = 16934400Hz = INT_BIT_CLK (MCLK) + * + * WM Codec post divider (MCLKDIV=1.5): + * INT_BIT_CLK (MCLK) / 1.5 = 11289600Hz = 256*fs = SYSCLK + */ + imx31_regmod32(&CCM_PDR1, + ((1-1) << CCM_PDR1_SSI1_PRE_PODF_POS) | + ((5-1) << CCM_PDR1_SSI1_PODF_POS) | + ((8-1) << CCM_PDR1_SSI2_PRE_PODF_POS) | + ((64-1) << CCM_PDR1_SSI2_PODF_POS), + CCM_PDR1_SSI1_PODF | CCM_PDR1_SSI2_PODF | + CCM_PDR1_SSI1_PRE_PODF | CCM_PDR1_SSI2_PRE_PODF); +} -- cgit v1.2.3