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author | Michael Sevakis <jethead71@rockbox.org> | 2010-04-23 15:32:50 +0000 |
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committer | Michael Sevakis <jethead71@rockbox.org> | 2010-04-23 15:32:50 +0000 |
commit | 11cca264ff57ad0b234bd1cd2c9a2366b967feb7 (patch) | |
tree | 7693e7150d5abc9687966cc248bfbd550d356964 /firmware/target/arm/imx31/dvfs_dptc-imx31.h | |
parent | 6cee7579dbdc4d41c4df08c9395cf96c952ebab1 (diff) | |
download | rockbox-11cca264ff57ad0b234bd1cd2c9a2366b967feb7.tar.gz rockbox-11cca264ff57ad0b234bd1cd2c9a2366b967feb7.zip |
i.MX31/Gigabeat S: Implement frequency and voltage scaling-- 1.6V for 528MHz, and 1.35V for 264MHz and 132MHz. Keep DPTC overdrive ( > 400MHz) voltage scaling off for now because of uncertainties. Simplify the (working) mess later.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25699 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/imx31/dvfs_dptc-imx31.h')
-rw-r--r-- | firmware/target/arm/imx31/dvfs_dptc-imx31.h | 99 |
1 files changed, 99 insertions, 0 deletions
diff --git a/firmware/target/arm/imx31/dvfs_dptc-imx31.h b/firmware/target/arm/imx31/dvfs_dptc-imx31.h index 8f6f5da98d..2bf6114a11 100644 --- a/firmware/target/arm/imx31/dvfs_dptc-imx31.h +++ b/firmware/target/arm/imx31/dvfs_dptc-imx31.h | |||
@@ -24,7 +24,106 @@ | |||
24 | #ifndef _DVFS_DPTC_IMX31_H_ | 24 | #ifndef _DVFS_DPTC_IMX31_H_ |
25 | #define _DVFS_DPTC_IMX31_H_ | 25 | #define _DVFS_DPTC_IMX31_H_ |
26 | 26 | ||
27 | /* DVFS load tracking signals */ | ||
28 | enum DVFS_LT_SIGS | ||
29 | { | ||
30 | DVFS_LT_SIG_M3IF_M0_BUF = 0, /* Hready signal of M3IF's master #0 | ||
31 | (L2 Cache) */ | ||
32 | DVFS_LT_SIG_M3IF_M1 = 1, /* Hready signal of M3IF's master #1 | ||
33 | (L2 Cache) */ | ||
34 | DVFS_LT_SIG_MBX_MBXCLKGATE = 2, /* Hready signal of M3IF's master #2 | ||
35 | (MBX) */ | ||
36 | DVFS_LT_SIG_M3IF_M3 = 3, /* Hready signal of M3IF's master #3 | ||
37 | (MAX) */ | ||
38 | DVFS_LT_SIG_M3IF_M4 = 4, /* Hready signal of M3IF's master #4 | ||
39 | (SDMA) */ | ||
40 | DVFS_LT_SIG_M3IF_M5 = 5, /* Hready signal of M3IF's master #5 | ||
41 | (mpeg4_vga_encoder) */ | ||
42 | DVFS_LT_SIG_M3IF_M6 = 6, /* Hready signal of M3IF's master #6 | ||
43 | (IPU) */ | ||
44 | DVFS_LT_SIG_M3IF_M7 = 7, /* Hready signal of M3IF's master #7 | ||
45 | (IPU) */ | ||
46 | DVFS_LT_SIG_ARM11_P_IRQ_B_RBT_GATE = 8, /* ARM normal interrupt */ | ||
47 | DVFS_LT_SIG_ARM11_P_FIQ_B_RBT_GATE = 9, /* ARM fast interrupt */ | ||
48 | DVFS_LT_SIG_IPI_GPIO1_INT0 = 10, /* Interrupt line from GPIO */ | ||
49 | DVFS_LT_SIG_IPI_INT_IPU_FUNC = 11, /* Interrupt line from IPU */ | ||
50 | DVFS_LT_SIG_DVGP0 = 12, /* Software-controllable general-purpose | ||
51 | bits from the CCM */ | ||
52 | DVFS_LT_SIG_DVGP1 = 13, /* Software-controllable general-purpose | ||
53 | bits from the CCM */ | ||
54 | DVFS_LT_SIG_DVGP2 = 14, /* Software-controllable general-purpose | ||
55 | bits from the CCM */ | ||
56 | DVFS_LT_SIG_DVGP3 = 15, /* Software-controllable general-purpose | ||
57 | bits from the CCM */ | ||
58 | }; | ||
59 | |||
60 | |||
61 | enum DVFS_DVGPS | ||
62 | { | ||
63 | DVFS_DVGP_0 = 0, | ||
64 | DVFS_DVGP_1, | ||
65 | DVFS_DVGP_2, | ||
66 | DVFS_DVGP_3, | ||
67 | }; | ||
68 | |||
69 | union dvfs_dptc_voltage_table_entry | ||
70 | { | ||
71 | uint8_t sw[4]; /* Access as array */ | ||
72 | |||
73 | struct | ||
74 | { | ||
75 | /* Chosen by PMIC pin states */ | ||
76 | /* when SWxABDVS bit is 1: */ | ||
77 | /* DVSSWxA DVSSWxB */ | ||
78 | uint8_t sw1a; /* 0 0 */ | ||
79 | uint8_t sw1advs; /* 1 0 */ | ||
80 | uint8_t sw1bdvs; /* 0 1 */ | ||
81 | uint8_t sw1bstby; /* 1 1 */ | ||
82 | }; | ||
83 | }; | ||
84 | |||
85 | |||
86 | struct dptc_dcvr_table_entry | ||
87 | { | ||
88 | uint32_t dcvr0; /* DCVR register values for working point */ | ||
89 | uint32_t dcvr1; | ||
90 | uint32_t dcvr2; | ||
91 | uint32_t dcvr3; | ||
92 | }; | ||
93 | |||
94 | |||
95 | struct dvfs_clock_table_entry | ||
96 | { | ||
97 | uint32_t pll_val; /* Setting for target PLL */ | ||
98 | uint32_t pdr_val; /* Post-divider for target setting */ | ||
99 | uint32_t pll_num : 1; /* 1 = MCU PLL, 0 = Serial PLL */ | ||
100 | uint32_t vscnt : 3; /* Voltage scaling counter, CKIL delay */ | ||
101 | }; | ||
102 | |||
103 | |||
104 | struct dvfs_lt_signal_descriptor | ||
105 | { | ||
106 | uint8_t weight : 3; /* Signal weight = 0-7 */ | ||
107 | uint8_t detect : 1; /* 1 = edge-detected */ | ||
108 | }; | ||
109 | |||
110 | |||
111 | extern long cpu_voltage_setting; | ||
112 | |||
113 | void dvfs_dptc_init(void); | ||
27 | void dvfs_dptc_start(void); | 114 | void dvfs_dptc_start(void); |
28 | void dvfs_dptc_stop(void); | 115 | void dvfs_dptc_stop(void); |
29 | 116 | ||
117 | void dvfs_wfi_monitor(bool on); | ||
118 | void dvfs_set_lt_weight(enum DVFS_LT_SIGS index, unsigned long value); | ||
119 | void dvfs_set_lt_detect(enum DVFS_LT_SIGS index, bool edge); | ||
120 | void dvfs_set_gp_bit(enum DVFS_DVGPS dvgp, bool assert); | ||
121 | |||
122 | unsigned int dvfs_dptc_get_voltage(void); | ||
123 | unsigned int dvfs_get_level(void); | ||
124 | void dvfs_set_level(unsigned int level); | ||
125 | |||
126 | unsigned int dptc_get_wp(void); | ||
127 | void dptc_set_wp(unsigned int wp); | ||
128 | |||
30 | #endif /* _DVFS_DPTC_IMX31_H_ */ | 129 | #endif /* _DVFS_DPTC_IMX31_H_ */ |