From 11cca264ff57ad0b234bd1cd2c9a2366b967feb7 Mon Sep 17 00:00:00 2001 From: Michael Sevakis Date: Fri, 23 Apr 2010 15:32:50 +0000 Subject: i.MX31/Gigabeat S: Implement frequency and voltage scaling-- 1.6V for 528MHz, and 1.35V for 264MHz and 132MHz. Keep DPTC overdrive ( > 400MHz) voltage scaling off for now because of uncertainties. Simplify the (working) mess later. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25699 a1c6a512-1295-4272-9138-f99709370657 --- firmware/target/arm/imx31/dvfs_dptc-imx31.h | 99 +++++++++++++++++++++++++++++ 1 file changed, 99 insertions(+) (limited to 'firmware/target/arm/imx31/dvfs_dptc-imx31.h') diff --git a/firmware/target/arm/imx31/dvfs_dptc-imx31.h b/firmware/target/arm/imx31/dvfs_dptc-imx31.h index 8f6f5da98d..2bf6114a11 100644 --- a/firmware/target/arm/imx31/dvfs_dptc-imx31.h +++ b/firmware/target/arm/imx31/dvfs_dptc-imx31.h @@ -24,7 +24,106 @@ #ifndef _DVFS_DPTC_IMX31_H_ #define _DVFS_DPTC_IMX31_H_ +/* DVFS load tracking signals */ +enum DVFS_LT_SIGS +{ + DVFS_LT_SIG_M3IF_M0_BUF = 0, /* Hready signal of M3IF's master #0 + (L2 Cache) */ + DVFS_LT_SIG_M3IF_M1 = 1, /* Hready signal of M3IF's master #1 + (L2 Cache) */ + DVFS_LT_SIG_MBX_MBXCLKGATE = 2, /* Hready signal of M3IF's master #2 + (MBX) */ + DVFS_LT_SIG_M3IF_M3 = 3, /* Hready signal of M3IF's master #3 + (MAX) */ + DVFS_LT_SIG_M3IF_M4 = 4, /* Hready signal of M3IF's master #4 + (SDMA) */ + DVFS_LT_SIG_M3IF_M5 = 5, /* Hready signal of M3IF's master #5 + (mpeg4_vga_encoder) */ + DVFS_LT_SIG_M3IF_M6 = 6, /* Hready signal of M3IF's master #6 + (IPU) */ + DVFS_LT_SIG_M3IF_M7 = 7, /* Hready signal of M3IF's master #7 + (IPU) */ + DVFS_LT_SIG_ARM11_P_IRQ_B_RBT_GATE = 8, /* ARM normal interrupt */ + DVFS_LT_SIG_ARM11_P_FIQ_B_RBT_GATE = 9, /* ARM fast interrupt */ + DVFS_LT_SIG_IPI_GPIO1_INT0 = 10, /* Interrupt line from GPIO */ + DVFS_LT_SIG_IPI_INT_IPU_FUNC = 11, /* Interrupt line from IPU */ + DVFS_LT_SIG_DVGP0 = 12, /* Software-controllable general-purpose + bits from the CCM */ + DVFS_LT_SIG_DVGP1 = 13, /* Software-controllable general-purpose + bits from the CCM */ + DVFS_LT_SIG_DVGP2 = 14, /* Software-controllable general-purpose + bits from the CCM */ + DVFS_LT_SIG_DVGP3 = 15, /* Software-controllable general-purpose + bits from the CCM */ +}; + + +enum DVFS_DVGPS +{ + DVFS_DVGP_0 = 0, + DVFS_DVGP_1, + DVFS_DVGP_2, + DVFS_DVGP_3, +}; + +union dvfs_dptc_voltage_table_entry +{ + uint8_t sw[4]; /* Access as array */ + + struct + { + /* Chosen by PMIC pin states */ + /* when SWxABDVS bit is 1: */ + /* DVSSWxA DVSSWxB */ + uint8_t sw1a; /* 0 0 */ + uint8_t sw1advs; /* 1 0 */ + uint8_t sw1bdvs; /* 0 1 */ + uint8_t sw1bstby; /* 1 1 */ + }; +}; + + +struct dptc_dcvr_table_entry +{ + uint32_t dcvr0; /* DCVR register values for working point */ + uint32_t dcvr1; + uint32_t dcvr2; + uint32_t dcvr3; +}; + + +struct dvfs_clock_table_entry +{ + uint32_t pll_val; /* Setting for target PLL */ + uint32_t pdr_val; /* Post-divider for target setting */ + uint32_t pll_num : 1; /* 1 = MCU PLL, 0 = Serial PLL */ + uint32_t vscnt : 3; /* Voltage scaling counter, CKIL delay */ +}; + + +struct dvfs_lt_signal_descriptor +{ + uint8_t weight : 3; /* Signal weight = 0-7 */ + uint8_t detect : 1; /* 1 = edge-detected */ +}; + + +extern long cpu_voltage_setting; + +void dvfs_dptc_init(void); void dvfs_dptc_start(void); void dvfs_dptc_stop(void); +void dvfs_wfi_monitor(bool on); +void dvfs_set_lt_weight(enum DVFS_LT_SIGS index, unsigned long value); +void dvfs_set_lt_detect(enum DVFS_LT_SIGS index, bool edge); +void dvfs_set_gp_bit(enum DVFS_DVGPS dvgp, bool assert); + +unsigned int dvfs_dptc_get_voltage(void); +unsigned int dvfs_get_level(void); +void dvfs_set_level(unsigned int level); + +unsigned int dptc_get_wp(void); +void dptc_set_wp(unsigned int wp); + #endif /* _DVFS_DPTC_IMX31_H_ */ -- cgit v1.2.3