imx233: modify arm cache timings on frequency switch

The manual recommands to tweak the arm cache settings on frequency
changes. The meaning of these values is undocumented but 0 seems
to be a safe value for all frequencies whereas 3 seems to be valid
only for low frequencies (<=64MHz ?)

Change-Id: Iaa8db4af8191010789cf986b1139ff259d73e2ed

1 files changed, 12 insertions, 0 deletions

diff --git a/firmware/target/arm/imx233/system-imx233.c b/firmware/target/arm/imx233/system-imx233.c
index 68f063512d..dfa6b569a8 100644
--- a/firmware/target/arm/imx233/system-imx233.c
+++ b/firmware/target/arm/imx233/system-imx233.c
@@ -163,6 +163,16 @@ void udelay(unsigned us)
     while(!imx233_us_elapsed(ref, us));
 }
 
+void imx233_digctl_set_arm_cache_timings(unsigned timings)
+{
+    HW_DIGCTL_ARMCACHE =
+        timings << HW_DIGCTL_ARMCACHE__ITAG_SS_BP |
+        timings << HW_DIGCTL_ARMCACHE__DTAG_SS_BP |
+        timings << HW_DIGCTL_ARMCACHE__CACHE_SS_BP |
+        timings << HW_DIGCTL_ARMCACHE__DRTY_SS_BP |
+        timings << HW_DIGCTL_ARMCACHE__VALID_SS_BP;
+}
+
 #ifdef HAVE_ADJUSTABLE_CPU_FREQ
 void set_cpu_frequency(long frequency)
 {
@@ -185,6 +195,7 @@ void set_cpu_frequency(long frequency)
      * changes are safe too */
     imx233_clkctrl_set_clock_divisor(CLK_HBUS, 4);
     imx233_clkctrl_set_bypass_pll(CLK_CPU, true);
+    imx233_digctl_set_arm_cache_timings(0);
 
     switch(frequency)
     {
@@ -233,6 +244,7 @@ void set_cpu_frequency(long frequency)
             imx233_clkctrl_set_bypass_pll(CLK_CPU, false);
 
             imx233_emi_set_frequency(IMX233_EMIFREQ_64_MHz);
+            imx233_digctl_set_arm_cache_timings(3);
             /* ref_cpu@480 MHz
              * ref_emi@480 MHz
              * clk_emi@64 MHz