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author | Amaury Pouly <amaury.pouly@gmail.com> | 2013-01-10 01:02:12 +0000 |
---|---|---|
committer | Amaury Pouly <amaury.pouly@gmail.com> | 2013-01-10 01:02:12 +0000 |
commit | 1fa406dc216cbbabd9f17df6312abf205976276f (patch) | |
tree | 576960251e968e706cc978d6f11c94baf5c62fef /firmware | |
parent | 5aa19f3eeb4e401b2d1ac57131a87b87b6ce55d5 (diff) | |
download | rockbox-1fa406dc216cbbabd9f17df6312abf205976276f.tar.gz rockbox-1fa406dc216cbbabd9f17df6312abf205976276f.zip |
imx233: modify arm cache timings on frequency switch
The manual recommands to tweak the arm cache settings on frequency
changes. The meaning of these values is undocumented but 0 seems
to be a safe value for all frequencies whereas 3 seems to be valid
only for low frequencies (<=64MHz ?)
Change-Id: Iaa8db4af8191010789cf986b1139ff259d73e2ed
Diffstat (limited to 'firmware')
-rw-r--r-- | firmware/target/arm/imx233/system-imx233.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/firmware/target/arm/imx233/system-imx233.c b/firmware/target/arm/imx233/system-imx233.c index 68f063512d..dfa6b569a8 100644 --- a/firmware/target/arm/imx233/system-imx233.c +++ b/firmware/target/arm/imx233/system-imx233.c | |||
@@ -163,6 +163,16 @@ void udelay(unsigned us) | |||
163 | while(!imx233_us_elapsed(ref, us)); | 163 | while(!imx233_us_elapsed(ref, us)); |
164 | } | 164 | } |
165 | 165 | ||
166 | void imx233_digctl_set_arm_cache_timings(unsigned timings) | ||
167 | { | ||
168 | HW_DIGCTL_ARMCACHE = | ||
169 | timings << HW_DIGCTL_ARMCACHE__ITAG_SS_BP | | ||
170 | timings << HW_DIGCTL_ARMCACHE__DTAG_SS_BP | | ||
171 | timings << HW_DIGCTL_ARMCACHE__CACHE_SS_BP | | ||
172 | timings << HW_DIGCTL_ARMCACHE__DRTY_SS_BP | | ||
173 | timings << HW_DIGCTL_ARMCACHE__VALID_SS_BP; | ||
174 | } | ||
175 | |||
166 | #ifdef HAVE_ADJUSTABLE_CPU_FREQ | 176 | #ifdef HAVE_ADJUSTABLE_CPU_FREQ |
167 | void set_cpu_frequency(long frequency) | 177 | void set_cpu_frequency(long frequency) |
168 | { | 178 | { |
@@ -185,6 +195,7 @@ void set_cpu_frequency(long frequency) | |||
185 | * changes are safe too */ | 195 | * changes are safe too */ |
186 | imx233_clkctrl_set_clock_divisor(CLK_HBUS, 4); | 196 | imx233_clkctrl_set_clock_divisor(CLK_HBUS, 4); |
187 | imx233_clkctrl_set_bypass_pll(CLK_CPU, true); | 197 | imx233_clkctrl_set_bypass_pll(CLK_CPU, true); |
198 | imx233_digctl_set_arm_cache_timings(0); | ||
188 | 199 | ||
189 | switch(frequency) | 200 | switch(frequency) |
190 | { | 201 | { |
@@ -233,6 +244,7 @@ void set_cpu_frequency(long frequency) | |||
233 | imx233_clkctrl_set_bypass_pll(CLK_CPU, false); | 244 | imx233_clkctrl_set_bypass_pll(CLK_CPU, false); |
234 | 245 | ||
235 | imx233_emi_set_frequency(IMX233_EMIFREQ_64_MHz); | 246 | imx233_emi_set_frequency(IMX233_EMIFREQ_64_MHz); |
247 | imx233_digctl_set_arm_cache_timings(3); | ||
236 | /* ref_cpu@480 MHz | 248 | /* ref_cpu@480 MHz |
237 | * ref_emi@480 MHz | 249 | * ref_emi@480 MHz |
238 | * clk_emi@64 MHz | 250 | * clk_emi@64 MHz |