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author | Amaury Pouly <amaury.pouly@gmail.com> | 2013-06-16 20:08:49 +0200 |
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committer | Amaury Pouly <amaury.pouly@gmail.com> | 2013-06-17 00:29:24 +0200 |
commit | f5ac658d160d11880c2affa9c5b669404c4fe207 (patch) | |
tree | 120f5e132430ea032d12d765fc6f407c020a908e /firmware/target/arm/imx233/ssp-imx233.c | |
parent | 84fc327aeb7be91e611520bb058a6c8d318401c3 (diff) | |
download | rockbox-f5ac658d160d11880c2affa9c5b669404c4fe207.tar.gz rockbox-f5ac658d160d11880c2affa9c5b669404c4fe207.zip |
imx233: normalise clkctrl
The clkctrl functions were becoming a mess. Normalise the names,
get rid of the xtal derived as special case and use the same
interface.
Change-Id: Ib954a8d30a6bd691914b5e0d97774ec9fc560c50
Diffstat (limited to 'firmware/target/arm/imx233/ssp-imx233.c')
-rw-r--r-- | firmware/target/arm/imx233/ssp-imx233.c | 19 |
1 files changed, 8 insertions, 11 deletions
diff --git a/firmware/target/arm/imx233/ssp-imx233.c b/firmware/target/arm/imx233/ssp-imx233.c index 5f0880c2e9..295e64d810 100644 --- a/firmware/target/arm/imx233/ssp-imx233.c +++ b/firmware/target/arm/imx233/ssp-imx233.c | |||
@@ -114,7 +114,7 @@ void imx233_ssp_start(int ssp) | |||
114 | return; | 114 | return; |
115 | ssp_in_use[ssp - 1] = true; | 115 | ssp_in_use[ssp - 1] = true; |
116 | /* Gate block */ | 116 | /* Gate block */ |
117 | imx233_reset_block(&SSP_REGn(SSP_CTRL0, ssp)); | 117 | imx233_ssp_softreset(ssp); |
118 | /* Gate dma channel */ | 118 | /* Gate dma channel */ |
119 | imx233_dma_clkgate_channel(APB_SSP(ssp), true); | 119 | imx233_dma_clkgate_channel(APB_SSP(ssp), true); |
120 | /* If first block to start, start SSP clock */ | 120 | /* If first block to start, start SSP clock */ |
@@ -123,11 +123,11 @@ void imx233_ssp_start(int ssp) | |||
123 | /** 2.3.1: the clk_ssp maximum frequency is 102.858 MHz */ | 123 | /** 2.3.1: the clk_ssp maximum frequency is 102.858 MHz */ |
124 | /* fracdiv = 18 => clk_io = pll = 480Mhz | 124 | /* fracdiv = 18 => clk_io = pll = 480Mhz |
125 | * intdiv = 5 => clk_ssp = 96Mhz */ | 125 | * intdiv = 5 => clk_ssp = 96Mhz */ |
126 | imx233_clkctrl_set_fractional_divisor(CLK_IO, 18); | 126 | imx233_clkctrl_set_frac_div(CLK_IO, 18); |
127 | imx233_clkctrl_enable_clock(CLK_SSP, false); | 127 | imx233_clkctrl_enable(CLK_SSP, false); |
128 | imx233_clkctrl_set_clock_divisor(CLK_SSP, 5); | 128 | imx233_clkctrl_set_div(CLK_SSP, 5); |
129 | imx233_clkctrl_set_bypass_pll(CLK_SSP, false); /* use IO */ | 129 | imx233_clkctrl_set_bypass(CLK_SSP, false); /* use IO */ |
130 | imx233_clkctrl_enable_clock(CLK_SSP, true); | 130 | imx233_clkctrl_enable(CLK_SSP, true); |
131 | } | 131 | } |
132 | ssp_nr_in_use++; | 132 | ssp_nr_in_use++; |
133 | } | 133 | } |
@@ -145,16 +145,13 @@ void imx233_ssp_stop(int ssp) | |||
145 | /* If last block to stop, stop SSP clock */ | 145 | /* If last block to stop, stop SSP clock */ |
146 | ssp_nr_in_use--; | 146 | ssp_nr_in_use--; |
147 | if(ssp_nr_in_use == 0) | 147 | if(ssp_nr_in_use == 0) |
148 | { | 148 | imx233_clkctrl_enable(CLK_SSP, false); |
149 | imx233_clkctrl_enable_clock(CLK_SSP, false); | ||
150 | imx233_clkctrl_set_fractional_divisor(CLK_IO, 0); | ||
151 | } | ||
152 | } | 149 | } |
153 | 150 | ||
154 | void imx233_ssp_softreset(int ssp) | 151 | void imx233_ssp_softreset(int ssp) |
155 | { | 152 | { |
156 | ASSERT_SSP(ssp) | 153 | ASSERT_SSP(ssp) |
157 | imx233_reset_block(&HW_SSP_CTRL0(ssp)); | 154 | imx233_reset_block(&SSP_REGn(SSP_CTRL0, ssp)); |
158 | } | 155 | } |
159 | 156 | ||
160 | void imx233_ssp_set_timings(int ssp, int divide, int rate, int timeout) | 157 | void imx233_ssp_set_timings(int ssp, int divide, int rate, int timeout) |