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author | Amaury Pouly <amaury.pouly@gmail.com> | 2013-06-16 17:16:48 +0200 |
---|---|---|
committer | Amaury Pouly <amaury.pouly@gmail.com> | 2013-06-16 18:21:43 +0200 |
commit | 7c5b65b9d234f819447195e3f852d9b59a225813 (patch) | |
tree | b49f4741fe792b07456bfc7ad4e71a7edbb01c0d /firmware/target/arm/imx233/power-imx233.c | |
parent | b73fda3a05f78a3ce78708e319f2eb719fd55719 (diff) | |
download | rockbox-7c5b65b9d234f819447195e3f852d9b59a225813.tar.gz rockbox-7c5b65b9d234f819447195e3f852d9b59a225813.zip |
imx233: rewrite power using new registers
Change-Id: Ifbee91161220419f4d1750672b5c4ae3537cefca
Diffstat (limited to 'firmware/target/arm/imx233/power-imx233.c')
-rw-r--r-- | firmware/target/arm/imx233/power-imx233.c | 162 |
1 files changed, 82 insertions, 80 deletions
diff --git a/firmware/target/arm/imx233/power-imx233.c b/firmware/target/arm/imx233/power-imx233.c index 49323f6ffd..9c00178f1a 100644 --- a/firmware/target/arm/imx233/power-imx233.c +++ b/firmware/target/arm/imx233/power-imx233.c | |||
@@ -38,76 +38,76 @@ struct current_step_bit_t | |||
38 | /* in decreasing order */ | 38 | /* in decreasing order */ |
39 | static struct current_step_bit_t g_charger_current_bits[] = | 39 | static struct current_step_bit_t g_charger_current_bits[] = |
40 | { | 40 | { |
41 | { 400, HW_POWER_CHARGE__BATTCHRG_I__400mA }, | 41 | { 400, BV_POWER_CHARGE_BATTCHRG_I__400mA }, |
42 | { 200, HW_POWER_CHARGE__BATTCHRG_I__200mA }, | 42 | { 200, BV_POWER_CHARGE_BATTCHRG_I__200mA }, |
43 | { 100, HW_POWER_CHARGE__BATTCHRG_I__100mA }, | 43 | { 100, BV_POWER_CHARGE_BATTCHRG_I__100mA }, |
44 | { 50, HW_POWER_CHARGE__BATTCHRG_I__50mA }, | 44 | { 50, BV_POWER_CHARGE_BATTCHRG_I__50mA }, |
45 | { 20, HW_POWER_CHARGE__BATTCHRG_I__20mA }, | 45 | { 20, BV_POWER_CHARGE_BATTCHRG_I__20mA }, |
46 | { 10, HW_POWER_CHARGE__BATTCHRG_I__10mA } | 46 | { 10, BV_POWER_CHARGE_BATTCHRG_I__10mA } |
47 | }; | 47 | }; |
48 | 48 | ||
49 | /* in decreasing order */ | 49 | /* in decreasing order */ |
50 | static struct current_step_bit_t g_charger_stop_current_bits[] = | 50 | static struct current_step_bit_t g_charger_stop_current_bits[] = |
51 | { | 51 | { |
52 | { 100, HW_POWER_CHARGE__STOP_ILIMIT__100mA }, | 52 | { 100, BV_POWER_CHARGE_STOP_ILIMIT__100mA }, |
53 | { 50, HW_POWER_CHARGE__STOP_ILIMIT__50mA }, | 53 | { 50, BV_POWER_CHARGE_STOP_ILIMIT__50mA }, |
54 | { 20, HW_POWER_CHARGE__STOP_ILIMIT__20mA }, | 54 | { 20, BV_POWER_CHARGE_STOP_ILIMIT__20mA }, |
55 | { 10, HW_POWER_CHARGE__STOP_ILIMIT__10mA } | 55 | { 10, BV_POWER_CHARGE_STOP_ILIMIT__10mA } |
56 | }; | 56 | }; |
57 | 57 | ||
58 | /* in decreasing order */ | 58 | /* in decreasing order */ |
59 | static struct current_step_bit_t g_4p2_charge_limit_bits[] = | 59 | static struct current_step_bit_t g_4p2_charge_limit_bits[] = |
60 | { | 60 | { |
61 | { 400, HW_POWER_5VCTRL__CHARGE_4P2_ILIMIT__400mA }, | 61 | { 400, BV_POWER_5VCTRL_CHARGE_4P2_ILIMIT__400mA }, |
62 | { 200, HW_POWER_5VCTRL__CHARGE_4P2_ILIMIT__200mA }, | 62 | { 200, BV_POWER_5VCTRL_CHARGE_4P2_ILIMIT__200mA }, |
63 | { 100, HW_POWER_5VCTRL__CHARGE_4P2_ILIMIT__100mA }, | 63 | { 100, BV_POWER_5VCTRL_CHARGE_4P2_ILIMIT__100mA }, |
64 | { 50, HW_POWER_5VCTRL__CHARGE_4P2_ILIMIT__50mA }, | 64 | { 50, BV_POWER_5VCTRL_CHARGE_4P2_ILIMIT__50mA }, |
65 | { 20, HW_POWER_5VCTRL__CHARGE_4P2_ILIMIT__20mA }, | 65 | { 20, BV_POWER_5VCTRL_CHARGE_4P2_ILIMIT__20mA }, |
66 | { 10, HW_POWER_5VCTRL__CHARGE_4P2_ILIMIT__10mA } | 66 | { 10, BV_POWER_5VCTRL_CHARGE_4P2_ILIMIT__10mA } |
67 | }; | 67 | }; |
68 | 68 | ||
69 | void INT_VDD5V(void) | 69 | void INT_VDD5V(void) |
70 | { | 70 | { |
71 | if(HW_POWER_CTRL & HW_POWER_CTRL__VBUSVALID_IRQ) | 71 | if(BF_RD(POWER_CTRL, VBUSVALID_IRQ)) |
72 | { | 72 | { |
73 | if(HW_POWER_STS & HW_POWER_STS__VBUSVALID) | 73 | if(BF_RD(POWER_STS, VBUSVALID)) |
74 | usb_insert_int(); | 74 | usb_insert_int(); |
75 | else | 75 | else |
76 | usb_remove_int(); | 76 | usb_remove_int(); |
77 | /* reverse polarity */ | 77 | /* reverse polarity */ |
78 | __REG_TOG(HW_POWER_CTRL) = HW_POWER_CTRL__POLARITY_VBUSVALID; | 78 | BF_TOG(POWER_CTRL, POLARITY_VBUSVALID); |
79 | /* enable int */ | 79 | /* enable int */ |
80 | __REG_CLR(HW_POWER_CTRL) = HW_POWER_CTRL__VBUSVALID_IRQ; | 80 | BF_CLR(POWER_CTRL, VBUSVALID_IRQ); |
81 | } | 81 | } |
82 | } | 82 | } |
83 | 83 | ||
84 | void imx233_power_init(void) | 84 | void imx233_power_init(void) |
85 | { | 85 | { |
86 | /* setup vbusvalid parameters: set threshold to 4v and power up comparators */ | 86 | /* setup vbusvalid parameters: set threshold to 4v and power up comparators */ |
87 | __REG_CLR(HW_POWER_5VCTRL) = HW_POWER_5VCTRL__VBUSVALID_TRSH_BM; | 87 | BF_CLR(POWER_5VCTRL, VBUSVALID_TRSH); |
88 | __REG_SET(HW_POWER_5VCTRL) = HW_POWER_5VCTRL__VBUSVALID_TRSH_4V | | 88 | BF_SETV(POWER_5VCTRL, VBUSVALID_TRSH, 1); |
89 | HW_POWER_5VCTRL__PWRUP_VBUS_CMPS; | 89 | BF_SET(POWER_5VCTRL, PWRUP_VBUS_CMPS); |
90 | /* enable vbusvalid detection method for the dcdc (improves efficiency) */ | 90 | /* enable vbusvalid detection method for the dcdc (improves efficiency) */ |
91 | __REG_SET(HW_POWER_5VCTRL) = HW_POWER_5VCTRL__VBUSVALID_5VDETECT; | 91 | BF_SET(POWER_5VCTRL, VBUSVALID_5VDETECT); |
92 | /* clear vbusvalid irq and set correct polarity */ | 92 | BF_CLR(POWER_CTRL, VBUSVALID_IRQ); |
93 | __REG_CLR(HW_POWER_CTRL) = HW_POWER_CTRL__VBUSVALID_IRQ; | 93 | if(BF_RD(POWER_STS, VBUSVALID)) |
94 | if(HW_POWER_STS & HW_POWER_STS__VBUSVALID) | 94 | BF_CLR(POWER_CTRL, POLARITY_VBUSVALID); |
95 | __REG_CLR(HW_POWER_CTRL) = HW_POWER_CTRL__POLARITY_VBUSVALID; | ||
96 | else | 95 | else |
97 | __REG_SET(HW_POWER_CTRL) = HW_POWER_CTRL__POLARITY_VBUSVALID; | 96 | BF_SET(POWER_CTRL, POLARITY_VBUSVALID); |
98 | __REG_SET(HW_POWER_CTRL) = HW_POWER_CTRL__ENIRQ_VBUS_VALID; | 97 | BF_SET(POWER_CTRL, ENIRQ_VBUS_VALID); |
99 | imx233_icoll_enable_interrupt(INT_SRC_VDD5V, true); | 98 | imx233_icoll_enable_interrupt(INT_SRC_VDD5V, true); |
100 | /* setup linear regulator offsets to 25 mV below to prevent contention between | 99 | /* setup linear regulator offsets to 25 mV below to prevent contention between |
101 | * linear regulators and DCDC */ | 100 | * linear regulators and DCDC */ |
102 | __FIELD_SET(HW_POWER_VDDDCTRL, LINREG_OFFSET, 2); | 101 | BF_WR(POWER_VDDDCTRL, LINREG_OFFSET, 2); |
103 | __FIELD_SET(HW_POWER_VDDACTRL, LINREG_OFFSET, 2); | 102 | BF_WR(POWER_VDDACTRL, LINREG_OFFSET, 2); |
104 | __FIELD_SET(HW_POWER_VDDIOCTRL, LINREG_OFFSET, 2); | 103 | BF_WR(POWER_VDDIOCTRL, LINREG_OFFSET, 2); |
105 | /* enable DCDC (more efficient) */ | 104 | /* enable DCDC (more efficient) */ |
106 | __REG_SET(HW_POWER_5VCTRL) = HW_POWER_5VCTRL__ENABLE_DCDC; | 105 | BF_SET(POWER_5VCTRL, ENABLE_DCDC); |
107 | /* enable a few bits controlling the DC-DC as recommended by Freescale */ | 106 | /* enable a few bits controlling the DC-DC as recommended by Freescale */ |
108 | __REG_SET(HW_POWER_LOOPCTRL) = HW_POWER_LOOPCTRL__TOGGLE_DIF | | 107 | BF_SET(POWER_LOOPCTRL, TOGGLE_DIF); |
109 | HW_POWER_LOOPCTRL__EN_CM_HYST; | 108 | BF_SET(POWER_LOOPCTRL, EN_CM_HYST); |
110 | __FIELD_SET(HW_POWER_LOOPCTRL, EN_RCSCALE, HW_POWER_LOOPCTRL__EN_RCSCALE__2X); | 109 | BF_CLR(POWER_LOOPCTRL, EN_RCSCALE); |
110 | BF_SETV(POWER_LOOPCTRL, EN_RCSCALE, 1); | ||
111 | } | 111 | } |
112 | 112 | ||
113 | void power_init(void) | 113 | void power_init(void) |
@@ -126,7 +126,7 @@ void power_off(void) | |||
126 | imx233_set_gpio_output(0, 9, true); | 126 | imx233_set_gpio_output(0, 9, true); |
127 | #endif | 127 | #endif |
128 | /* power down */ | 128 | /* power down */ |
129 | HW_POWER_RESET = HW_POWER_RESET__UNLOCK | HW_POWER_RESET__PWD; | 129 | HW_POWER_RESET = BM_OR2(POWER_RESET, UNLOCK, PWD); |
130 | while(1); | 130 | while(1); |
131 | } | 131 | } |
132 | 132 | ||
@@ -138,24 +138,24 @@ unsigned int power_input_status(void) | |||
138 | 138 | ||
139 | bool charging_state(void) | 139 | bool charging_state(void) |
140 | { | 140 | { |
141 | return HW_POWER_STS & HW_POWER_STS__CHRGSTS; | 141 | return BF_RD(POWER_STS, CHRGSTS); |
142 | } | 142 | } |
143 | 143 | ||
144 | void imx233_power_set_charge_current(unsigned current) | 144 | void imx233_power_set_charge_current(unsigned current) |
145 | { | 145 | { |
146 | __REG_CLR(HW_POWER_CHARGE) = HW_POWER_CHARGE__BATTCHRG_I_BM; | 146 | BF_CLR(POWER_CHARGE, BATTCHRG_I); |
147 | /* find closest current LOWER THAN OR EQUAL TO the expected current */ | 147 | /* find closest current LOWER THAN OR EQUAL TO the expected current */ |
148 | for(unsigned i = 0; i < ARRAYLEN(g_charger_current_bits); i++) | 148 | for(unsigned i = 0; i < ARRAYLEN(g_charger_current_bits); i++) |
149 | if(current >= g_charger_current_bits[i].current) | 149 | if(current >= g_charger_current_bits[i].current) |
150 | { | 150 | { |
151 | current -= g_charger_current_bits[i].current; | 151 | current -= g_charger_current_bits[i].current; |
152 | __REG_SET(HW_POWER_CHARGE) = g_charger_current_bits[i].bit; | 152 | BF_SETV(POWER_CHARGE, BATTCHRG_I, g_charger_current_bits[i].bit); |
153 | } | 153 | } |
154 | } | 154 | } |
155 | 155 | ||
156 | void imx233_power_set_stop_current(unsigned current) | 156 | void imx233_power_set_stop_current(unsigned current) |
157 | { | 157 | { |
158 | __REG_CLR(HW_POWER_CHARGE) = HW_POWER_CHARGE__STOP_ILIMIT_BM; | 158 | BF_CLR(POWER_CHARGE, STOP_ILIMIT); |
159 | /* find closest current GREATHER THAN OR EQUAL TO the expected current */ | 159 | /* find closest current GREATHER THAN OR EQUAL TO the expected current */ |
160 | unsigned sum = 0; | 160 | unsigned sum = 0; |
161 | for(unsigned i = 0; i < ARRAYLEN(g_charger_stop_current_bits); i++) | 161 | for(unsigned i = 0; i < ARRAYLEN(g_charger_stop_current_bits); i++) |
@@ -166,7 +166,7 @@ void imx233_power_set_stop_current(unsigned current) | |||
166 | if(current > sum) | 166 | if(current > sum) |
167 | { | 167 | { |
168 | current -= g_charger_stop_current_bits[i].current; | 168 | current -= g_charger_stop_current_bits[i].current; |
169 | __REG_SET(HW_POWER_CHARGE) = g_charger_stop_current_bits[i].bit; | 169 | BF_SETV(POWER_CHARGE, STOP_ILIMIT, g_charger_stop_current_bits[i].bit); |
170 | } | 170 | } |
171 | } | 171 | } |
172 | } | 172 | } |
@@ -191,17 +191,17 @@ static struct | |||
191 | .min = HW_POWER_##name##CTRL__TRG_MIN, \ | 191 | .min = HW_POWER_##name##CTRL__TRG_MIN, \ |
192 | .step = HW_POWER_##name##CTRL__TRG_STEP, \ | 192 | .step = HW_POWER_##name##CTRL__TRG_STEP, \ |
193 | .reg = &HW_POWER_##name##CTRL, \ | 193 | .reg = &HW_POWER_##name##CTRL, \ |
194 | .trg_bm = HW_POWER_##name##CTRL__TRG_BM, \ | 194 | .trg_bm = BM_POWER_##name##CTRL_TRG, \ |
195 | .trg_bp = HW_POWER_##name##CTRL__TRG_BP, \ | 195 | .trg_bp = BP_POWER_##name##CTRL_TRG, \ |
196 | .flags = mask | 196 | .flags = mask |
197 | #define ADD_REGULATOR_BO(name) \ | 197 | #define ADD_REGULATOR_BO(name) \ |
198 | .bo_bm = HW_POWER_##name##CTRL__BO_OFFSET_BM, \ | 198 | .bo_bm = BM_POWER_##name##CTRL_BO_OFFSET, \ |
199 | .bo_bp = HW_POWER_##name##CTRL__BO_OFFSET_BP | 199 | .bo_bp = BP_POWER_##name##CTRL_BO_OFFSET |
200 | #define ADD_REGULATOR_LINREG(name) \ | 200 | #define ADD_REGULATOR_LINREG(name) \ |
201 | .linreg_bm = HW_POWER_##name##CTRL__ENABLE_LINREG | 201 | .linreg_bm = BM_POWER_##name##CTRL_ENABLE_LINREG |
202 | #define ADD_REGULATOR_LINREG_OFFSET(name) \ | 202 | #define ADD_REGULATOR_LINREG_OFFSET(name) \ |
203 | .linreg_offset_bm = HW_POWER_##name##CTRL__LINREG_OFFSET_BM, \ | 203 | .linreg_offset_bm = BM_POWER_##name##CTRL_LINREG_OFFSET, \ |
204 | .linreg_offset_bp = HW_POWER_##name##CTRL__LINREG_OFFSET_BP | 204 | .linreg_offset_bp = BP_POWER_##name##CTRL_LINREG_OFFSET |
205 | [REGULATOR_VDDD] = | 205 | [REGULATOR_VDDD] = |
206 | { | 206 | { |
207 | ADD_REGULATOR(VDDD, HAS_BO|HAS_LINREG|HAS_LINREG_OFFSET), | 207 | ADD_REGULATOR(VDDD, HAS_BO|HAS_LINREG|HAS_LINREG_OFFSET), |
@@ -257,7 +257,7 @@ void imx233_power_set_regulator(enum imx233_regulator_t reg, unsigned value_mv, | |||
257 | unsigned raw_val = (value_mv - regulator_info[reg].min) / regulator_info[reg].step; | 257 | unsigned raw_val = (value_mv - regulator_info[reg].min) / regulator_info[reg].step; |
258 | unsigned raw_bo_offset = (value_mv - brownout_mv) / regulator_info[reg].step; | 258 | unsigned raw_bo_offset = (value_mv - brownout_mv) / regulator_info[reg].step; |
259 | // clear dc-dc ok flag | 259 | // clear dc-dc ok flag |
260 | __REG_SET(HW_POWER_CTRL) = HW_POWER_CTRL__DC_OK_IRQ; | 260 | BF_SET(POWER_CTRL, DC_OK_IRQ); |
261 | // update | 261 | // update |
262 | uint32_t reg_val = (*regulator_info[reg].reg) & ~regulator_info[reg].trg_bm; | 262 | uint32_t reg_val = (*regulator_info[reg].reg) & ~regulator_info[reg].trg_bm; |
263 | reg_val |= raw_val << regulator_info[reg].trg_bp; | 263 | reg_val |= raw_val << regulator_info[reg].trg_bp; |
@@ -271,12 +271,12 @@ void imx233_power_set_regulator(enum imx233_regulator_t reg, unsigned value_mv, | |||
271 | * If DC-DC is used, we can use the DCDC_OK irq | 271 | * If DC-DC is used, we can use the DCDC_OK irq |
272 | * Otherwise it is unreliable (doesn't work when lowering voltage on linregs) | 272 | * Otherwise it is unreliable (doesn't work when lowering voltage on linregs) |
273 | * It usually takes between 0.5ms and 2.5ms */ | 273 | * It usually takes between 0.5ms and 2.5ms */ |
274 | if(!(HW_POWER_5VCTRL & HW_POWER_5VCTRL__ENABLE_DCDC)) | 274 | if(!BF_RD(POWER_5VCTRL, ENABLE_DCDC)) |
275 | panicf("regulator %d: wait for voltage stabilize in linreg mode !", reg); | 275 | panicf("regulator %d: wait for voltage stabilize in linreg mode !", reg); |
276 | unsigned timeout = current_tick + (HZ * 20) / 1000; | 276 | unsigned timeout = current_tick + (HZ * 20) / 1000; |
277 | while(!(HW_POWER_CTRL & HW_POWER_CTRL__DC_OK_IRQ) || !TIME_AFTER(current_tick, timeout)) | 277 | while(!BF_RD(POWER_CTRL, DC_OK_IRQ) || !TIME_AFTER(current_tick, timeout)) |
278 | yield(); | 278 | yield(); |
279 | if(!(HW_POWER_CTRL & HW_POWER_CTRL__DC_OK_IRQ)) | 279 | if(!BF_RD(POWER_CTRL, DC_OK_IRQ)) |
280 | panicf("regulator %d: failed to stabilize", reg); | 280 | panicf("regulator %d: failed to stabilize", reg); |
281 | } | 281 | } |
282 | 282 | ||
@@ -311,55 +311,57 @@ void imx233_power_set_regulator_linreg(enum imx233_regulator_t reg, | |||
311 | struct imx233_power_info_t imx233_power_get_info(unsigned flags) | 311 | struct imx233_power_info_t imx233_power_get_info(unsigned flags) |
312 | { | 312 | { |
313 | static int dcdc_freqsel[8] = { | 313 | static int dcdc_freqsel[8] = { |
314 | [HW_POWER_MISC__FREQSEL__RES] = 0, | 314 | [BV_POWER_MISC_FREQSEL__RES] = 0, |
315 | [HW_POWER_MISC__FREQSEL__20MHz] = 20000, | 315 | [BV_POWER_MISC_FREQSEL__20MHz] = 20000, |
316 | [HW_POWER_MISC__FREQSEL__24MHz] = 24000, | 316 | [BV_POWER_MISC_FREQSEL__24MHz] = 24000, |
317 | [HW_POWER_MISC__FREQSEL__19p2MHz] = 19200, | 317 | [BV_POWER_MISC_FREQSEL__19p2MHz] = 19200, |
318 | [HW_POWER_MISC__FREQSEL__14p4MHz] = 14200, | 318 | [BV_POWER_MISC_FREQSEL__14p4MHz] = 14200, |
319 | [HW_POWER_MISC__FREQSEL__18MHz] = 18000, | 319 | [BV_POWER_MISC_FREQSEL__18MHz] = 18000, |
320 | [HW_POWER_MISC__FREQSEL__21p6MHz] = 21600, | 320 | [BV_POWER_MISC_FREQSEL__21p6MHz] = 21600, |
321 | [HW_POWER_MISC__FREQSEL__17p28MHz] = 17280, | 321 | [BV_POWER_MISC_FREQSEL__17p28MHz] = 17280, |
322 | }; | 322 | }; |
323 | 323 | ||
324 | struct imx233_power_info_t s; | 324 | struct imx233_power_info_t s; |
325 | memset(&s, 0, sizeof(s)); | 325 | memset(&s, 0, sizeof(s)); |
326 | if(flags & POWER_INFO_DCDC) | 326 | if(flags & POWER_INFO_DCDC) |
327 | { | 327 | { |
328 | s.dcdc_sel_pllclk = HW_POWER_MISC & HW_POWER_MISC__SEL_PLLCLK; | 328 | s.dcdc_sel_pllclk = BF_RD(POWER_MISC, SEL_PLLCLK); |
329 | s.dcdc_freqsel = dcdc_freqsel[__XTRACT(HW_POWER_MISC, FREQSEL)]; | 329 | s.dcdc_freqsel = dcdc_freqsel[BF_RD(POWER_MISC, FREQSEL)]; |
330 | } | 330 | } |
331 | if(flags & POWER_INFO_CHARGE) | 331 | if(flags & POWER_INFO_CHARGE) |
332 | { | 332 | { |
333 | uint32_t current = BF_RD(POWER_CHARGE, BATTCHRG_I); | ||
334 | uint32_t stop_current = BF_RD(POWER_CHARGE, STOP_ILIMIT); | ||
333 | for(unsigned i = 0; i < ARRAYLEN(g_charger_current_bits); i++) | 335 | for(unsigned i = 0; i < ARRAYLEN(g_charger_current_bits); i++) |
334 | if(HW_POWER_CHARGE & g_charger_current_bits[i].bit) | 336 | if(current & g_charger_current_bits[i].bit) |
335 | s.charge_current += g_charger_current_bits[i].current; | 337 | s.charge_current += g_charger_current_bits[i].current; |
336 | for(unsigned i = 0; i < ARRAYLEN(g_charger_stop_current_bits); i++) | 338 | for(unsigned i = 0; i < ARRAYLEN(g_charger_stop_current_bits); i++) |
337 | if(HW_POWER_CHARGE & g_charger_stop_current_bits[i].bit) | 339 | if(stop_current & g_charger_stop_current_bits[i].bit) |
338 | s.stop_current += g_charger_stop_current_bits[i].current; | 340 | s.stop_current += g_charger_stop_current_bits[i].current; |
339 | s.charging = HW_POWER_STS & HW_POWER_STS__CHRGSTS; | 341 | s.charging = BF_RD(POWER_STS, CHRGSTS); |
340 | s.batt_adj = HW_POWER_BATTMONITOR & HW_POWER_BATTMONITOR__ENBATADJ; | 342 | s.batt_adj = BF_RD(POWER_BATTMONITOR, EN_BATADJ); |
341 | } | 343 | } |
342 | if(flags & POWER_INFO_4P2) | 344 | if(flags & POWER_INFO_4P2) |
343 | { | 345 | { |
344 | s._4p2_enable = HW_POWER_DCDC4P2 & HW_POWER_DCDC4P2__ENABLE_4P2; | 346 | s._4p2_enable = BF_RD(POWER_DCDC4P2, ENABLE_4P2); |
345 | s._4p2_dcdc = HW_POWER_DCDC4P2 & HW_POWER_DCDC4P2__ENABLE_DCDC; | 347 | s._4p2_dcdc = BF_RD(POWER_DCDC4P2, ENABLE_DCDC); |
346 | s._4p2_cmptrip = __XTRACT(HW_POWER_DCDC4P2, CMPTRIP); | 348 | s._4p2_cmptrip = BF_RD(POWER_DCDC4P2, CMPTRIP); |
347 | s._4p2_dropout = __XTRACT(HW_POWER_DCDC4P2, DROPOUT_CTRL); | 349 | s._4p2_dropout = BF_RD(POWER_DCDC4P2, DROPOUT_CTRL); |
348 | } | 350 | } |
349 | if(flags & POWER_INFO_5V) | 351 | if(flags & POWER_INFO_5V) |
350 | { | 352 | { |
351 | s._5v_pwd_charge_4p2 = HW_POWER_5VCTRL & HW_POWER_5VCTRL__PWD_CHARGE_4P2; | 353 | s._5v_pwd_charge_4p2 = BF_RD(POWER_5VCTRL, PWD_CHARGE_4P2); |
352 | s._5v_dcdc_xfer = HW_POWER_5VCTRL & HW_POWER_5VCTRL__DCDC_XFER; | 354 | s._5v_enable_dcdc = BF_RD(POWER_5VCTRL, ENABLE_DCDC); |
353 | s._5v_enable_dcdc = HW_POWER_5VCTRL & HW_POWER_5VCTRL__ENABLE_DCDC; | 355 | uint32_t charge_4p2_ilimit = BF_RD(POWER_5VCTRL, CHARGE_4P2_ILIMIT); |
354 | for(unsigned i = 0; i < ARRAYLEN(g_4p2_charge_limit_bits); i++) | 356 | for(unsigned i = 0; i < ARRAYLEN(g_4p2_charge_limit_bits); i++) |
355 | if(HW_POWER_5VCTRL & g_4p2_charge_limit_bits[i].bit) | 357 | if(charge_4p2_ilimit & g_4p2_charge_limit_bits[i].bit) |
356 | s._5v_charge_4p2_limit += g_4p2_charge_limit_bits[i].current; | 358 | s._5v_charge_4p2_limit += g_4p2_charge_limit_bits[i].current; |
357 | s._5v_vbusvalid_detect = HW_POWER_5VCTRL & HW_POWER_5VCTRL__VBUSVALID_5VDETECT; | 359 | s._5v_vbusvalid_detect = BF_RD(POWER_5VCTRL, VBUSVALID_5VDETECT); |
358 | s._5v_vbus_cmps = HW_POWER_5VCTRL & HW_POWER_5VCTRL__PWRUP_VBUS_CMPS; | 360 | s._5v_vbus_cmps = BF_RD(POWER_5VCTRL, PWRUP_VBUS_CMPS); |
359 | s._5v_vbusvalid_thr = | 361 | s._5v_vbusvalid_thr = |
360 | __XTRACT(HW_POWER_5VCTRL, VBUSVALID_TRSH) == 0 ? | 362 | BF_RD(POWER_5VCTRL, VBUSVALID_TRSH) == 0 ? |
361 | 2900 | 363 | 2900 |
362 | : 3900 + __XTRACT(HW_POWER_5VCTRL, VBUSVALID_TRSH) * 100; | 364 | : 3900 + BF_RD(POWER_5VCTRL, VBUSVALID_TRSH) * 100; |
363 | } | 365 | } |
364 | return s; | 366 | return s; |
365 | } | 367 | } |