diff options
-rw-r--r-- | bootloader/imx233.c | 2 | ||||
-rw-r--r-- | firmware/target/arm/imx233/creative-zenxfi3/button-zenxfi3.c | 2 | ||||
-rw-r--r-- | firmware/target/arm/imx233/power-imx233.c | 162 | ||||
-rw-r--r-- | firmware/target/arm/imx233/power-imx233.h | 182 | ||||
-rw-r--r-- | firmware/target/arm/imx233/powermgmt-imx233.c | 50 | ||||
-rw-r--r-- | firmware/target/arm/imx233/sansa-fuzeplus/button-fuzeplus.c | 2 | ||||
-rw-r--r-- | firmware/target/arm/imx233/usb-imx233.c | 2 |
7 files changed, 145 insertions, 257 deletions
diff --git a/bootloader/imx233.c b/bootloader/imx233.c index 9f6525e735..c9e968ee66 100644 --- a/bootloader/imx233.c +++ b/bootloader/imx233.c | |||
@@ -150,7 +150,7 @@ void main(uint32_t arg, uint32_t addr) | |||
150 | 150 | ||
151 | printf("Boot version: %s", RBVERSION); | 151 | printf("Boot version: %s", RBVERSION); |
152 | printf("arg=%x addr=%x", arg, addr); | 152 | printf("arg=%x addr=%x", arg, addr); |
153 | printf("power up source: %x", __XTRACT(HW_POWER_STS, PWRUP_SOURCE)); | 153 | printf("power up source: %x", BF_RD(POWER_STS, PWRUP_SOURCE)); |
154 | 154 | ||
155 | if(arg == 0xfee1dead) | 155 | if(arg == 0xfee1dead) |
156 | { | 156 | { |
diff --git a/firmware/target/arm/imx233/creative-zenxfi3/button-zenxfi3.c b/firmware/target/arm/imx233/creative-zenxfi3/button-zenxfi3.c index f2e0bb20bc..70355bc24c 100644 --- a/firmware/target/arm/imx233/creative-zenxfi3/button-zenxfi3.c +++ b/firmware/target/arm/imx233/creative-zenxfi3/button-zenxfi3.c | |||
@@ -176,7 +176,7 @@ int button_read_device(void) | |||
176 | res |= BUTTON_VOL_DOWN; | 176 | res |= BUTTON_VOL_DOWN; |
177 | if(!(mask & 0x100)) | 177 | if(!(mask & 0x100)) |
178 | res |= BUTTON_VOL_UP; | 178 | res |= BUTTON_VOL_UP; |
179 | if(__XTRACT(HW_POWER_STS, PSWITCH) != 0 && power_ignore_counter == 0) | 179 | if(BF_RD(POWER_STS, PSWITCH) != 0 && power_ignore_counter == 0) |
180 | res |= BUTTON_POWER; | 180 | res |= BUTTON_POWER; |
181 | return res | touchpad_btns; | 181 | return res | touchpad_btns; |
182 | } | 182 | } |
diff --git a/firmware/target/arm/imx233/power-imx233.c b/firmware/target/arm/imx233/power-imx233.c index 49323f6ffd..9c00178f1a 100644 --- a/firmware/target/arm/imx233/power-imx233.c +++ b/firmware/target/arm/imx233/power-imx233.c | |||
@@ -38,76 +38,76 @@ struct current_step_bit_t | |||
38 | /* in decreasing order */ | 38 | /* in decreasing order */ |
39 | static struct current_step_bit_t g_charger_current_bits[] = | 39 | static struct current_step_bit_t g_charger_current_bits[] = |
40 | { | 40 | { |
41 | { 400, HW_POWER_CHARGE__BATTCHRG_I__400mA }, | 41 | { 400, BV_POWER_CHARGE_BATTCHRG_I__400mA }, |
42 | { 200, HW_POWER_CHARGE__BATTCHRG_I__200mA }, | 42 | { 200, BV_POWER_CHARGE_BATTCHRG_I__200mA }, |
43 | { 100, HW_POWER_CHARGE__BATTCHRG_I__100mA }, | 43 | { 100, BV_POWER_CHARGE_BATTCHRG_I__100mA }, |
44 | { 50, HW_POWER_CHARGE__BATTCHRG_I__50mA }, | 44 | { 50, BV_POWER_CHARGE_BATTCHRG_I__50mA }, |
45 | { 20, HW_POWER_CHARGE__BATTCHRG_I__20mA }, | 45 | { 20, BV_POWER_CHARGE_BATTCHRG_I__20mA }, |
46 | { 10, HW_POWER_CHARGE__BATTCHRG_I__10mA } | 46 | { 10, BV_POWER_CHARGE_BATTCHRG_I__10mA } |
47 | }; | 47 | }; |
48 | 48 | ||
49 | /* in decreasing order */ | 49 | /* in decreasing order */ |
50 | static struct current_step_bit_t g_charger_stop_current_bits[] = | 50 | static struct current_step_bit_t g_charger_stop_current_bits[] = |
51 | { | 51 | { |
52 | { 100, HW_POWER_CHARGE__STOP_ILIMIT__100mA }, | 52 | { 100, BV_POWER_CHARGE_STOP_ILIMIT__100mA }, |
53 | { 50, HW_POWER_CHARGE__STOP_ILIMIT__50mA }, | 53 | { 50, BV_POWER_CHARGE_STOP_ILIMIT__50mA }, |
54 | { 20, HW_POWER_CHARGE__STOP_ILIMIT__20mA }, | 54 | { 20, BV_POWER_CHARGE_STOP_ILIMIT__20mA }, |
55 | { 10, HW_POWER_CHARGE__STOP_ILIMIT__10mA } | 55 | { 10, BV_POWER_CHARGE_STOP_ILIMIT__10mA } |
56 | }; | 56 | }; |
57 | 57 | ||
58 | /* in decreasing order */ | 58 | /* in decreasing order */ |
59 | static struct current_step_bit_t g_4p2_charge_limit_bits[] = | 59 | static struct current_step_bit_t g_4p2_charge_limit_bits[] = |
60 | { | 60 | { |
61 | { 400, HW_POWER_5VCTRL__CHARGE_4P2_ILIMIT__400mA }, | 61 | { 400, BV_POWER_5VCTRL_CHARGE_4P2_ILIMIT__400mA }, |
62 | { 200, HW_POWER_5VCTRL__CHARGE_4P2_ILIMIT__200mA }, | 62 | { 200, BV_POWER_5VCTRL_CHARGE_4P2_ILIMIT__200mA }, |
63 | { 100, HW_POWER_5VCTRL__CHARGE_4P2_ILIMIT__100mA }, | 63 | { 100, BV_POWER_5VCTRL_CHARGE_4P2_ILIMIT__100mA }, |
64 | { 50, HW_POWER_5VCTRL__CHARGE_4P2_ILIMIT__50mA }, | 64 | { 50, BV_POWER_5VCTRL_CHARGE_4P2_ILIMIT__50mA }, |
65 | { 20, HW_POWER_5VCTRL__CHARGE_4P2_ILIMIT__20mA }, | 65 | { 20, BV_POWER_5VCTRL_CHARGE_4P2_ILIMIT__20mA }, |
66 | { 10, HW_POWER_5VCTRL__CHARGE_4P2_ILIMIT__10mA } | 66 | { 10, BV_POWER_5VCTRL_CHARGE_4P2_ILIMIT__10mA } |
67 | }; | 67 | }; |
68 | 68 | ||
69 | void INT_VDD5V(void) | 69 | void INT_VDD5V(void) |
70 | { | 70 | { |
71 | if(HW_POWER_CTRL & HW_POWER_CTRL__VBUSVALID_IRQ) | 71 | if(BF_RD(POWER_CTRL, VBUSVALID_IRQ)) |
72 | { | 72 | { |
73 | if(HW_POWER_STS & HW_POWER_STS__VBUSVALID) | 73 | if(BF_RD(POWER_STS, VBUSVALID)) |
74 | usb_insert_int(); | 74 | usb_insert_int(); |
75 | else | 75 | else |
76 | usb_remove_int(); | 76 | usb_remove_int(); |
77 | /* reverse polarity */ | 77 | /* reverse polarity */ |
78 | __REG_TOG(HW_POWER_CTRL) = HW_POWER_CTRL__POLARITY_VBUSVALID; | 78 | BF_TOG(POWER_CTRL, POLARITY_VBUSVALID); |
79 | /* enable int */ | 79 | /* enable int */ |
80 | __REG_CLR(HW_POWER_CTRL) = HW_POWER_CTRL__VBUSVALID_IRQ; | 80 | BF_CLR(POWER_CTRL, VBUSVALID_IRQ); |
81 | } | 81 | } |
82 | } | 82 | } |
83 | 83 | ||
84 | void imx233_power_init(void) | 84 | void imx233_power_init(void) |
85 | { | 85 | { |
86 | /* setup vbusvalid parameters: set threshold to 4v and power up comparators */ | 86 | /* setup vbusvalid parameters: set threshold to 4v and power up comparators */ |
87 | __REG_CLR(HW_POWER_5VCTRL) = HW_POWER_5VCTRL__VBUSVALID_TRSH_BM; | 87 | BF_CLR(POWER_5VCTRL, VBUSVALID_TRSH); |
88 | __REG_SET(HW_POWER_5VCTRL) = HW_POWER_5VCTRL__VBUSVALID_TRSH_4V | | 88 | BF_SETV(POWER_5VCTRL, VBUSVALID_TRSH, 1); |
89 | HW_POWER_5VCTRL__PWRUP_VBUS_CMPS; | 89 | BF_SET(POWER_5VCTRL, PWRUP_VBUS_CMPS); |
90 | /* enable vbusvalid detection method for the dcdc (improves efficiency) */ | 90 | /* enable vbusvalid detection method for the dcdc (improves efficiency) */ |
91 | __REG_SET(HW_POWER_5VCTRL) = HW_POWER_5VCTRL__VBUSVALID_5VDETECT; | 91 | BF_SET(POWER_5VCTRL, VBUSVALID_5VDETECT); |
92 | /* clear vbusvalid irq and set correct polarity */ | 92 | BF_CLR(POWER_CTRL, VBUSVALID_IRQ); |
93 | __REG_CLR(HW_POWER_CTRL) = HW_POWER_CTRL__VBUSVALID_IRQ; | 93 | if(BF_RD(POWER_STS, VBUSVALID)) |
94 | if(HW_POWER_STS & HW_POWER_STS__VBUSVALID) | 94 | BF_CLR(POWER_CTRL, POLARITY_VBUSVALID); |
95 | __REG_CLR(HW_POWER_CTRL) = HW_POWER_CTRL__POLARITY_VBUSVALID; | ||
96 | else | 95 | else |
97 | __REG_SET(HW_POWER_CTRL) = HW_POWER_CTRL__POLARITY_VBUSVALID; | 96 | BF_SET(POWER_CTRL, POLARITY_VBUSVALID); |
98 | __REG_SET(HW_POWER_CTRL) = HW_POWER_CTRL__ENIRQ_VBUS_VALID; | 97 | BF_SET(POWER_CTRL, ENIRQ_VBUS_VALID); |
99 | imx233_icoll_enable_interrupt(INT_SRC_VDD5V, true); | 98 | imx233_icoll_enable_interrupt(INT_SRC_VDD5V, true); |
100 | /* setup linear regulator offsets to 25 mV below to prevent contention between | 99 | /* setup linear regulator offsets to 25 mV below to prevent contention between |
101 | * linear regulators and DCDC */ | 100 | * linear regulators and DCDC */ |
102 | __FIELD_SET(HW_POWER_VDDDCTRL, LINREG_OFFSET, 2); | 101 | BF_WR(POWER_VDDDCTRL, LINREG_OFFSET, 2); |
103 | __FIELD_SET(HW_POWER_VDDACTRL, LINREG_OFFSET, 2); | 102 | BF_WR(POWER_VDDACTRL, LINREG_OFFSET, 2); |
104 | __FIELD_SET(HW_POWER_VDDIOCTRL, LINREG_OFFSET, 2); | 103 | BF_WR(POWER_VDDIOCTRL, LINREG_OFFSET, 2); |
105 | /* enable DCDC (more efficient) */ | 104 | /* enable DCDC (more efficient) */ |
106 | __REG_SET(HW_POWER_5VCTRL) = HW_POWER_5VCTRL__ENABLE_DCDC; | 105 | BF_SET(POWER_5VCTRL, ENABLE_DCDC); |
107 | /* enable a few bits controlling the DC-DC as recommended by Freescale */ | 106 | /* enable a few bits controlling the DC-DC as recommended by Freescale */ |
108 | __REG_SET(HW_POWER_LOOPCTRL) = HW_POWER_LOOPCTRL__TOGGLE_DIF | | 107 | BF_SET(POWER_LOOPCTRL, TOGGLE_DIF); |
109 | HW_POWER_LOOPCTRL__EN_CM_HYST; | 108 | BF_SET(POWER_LOOPCTRL, EN_CM_HYST); |
110 | __FIELD_SET(HW_POWER_LOOPCTRL, EN_RCSCALE, HW_POWER_LOOPCTRL__EN_RCSCALE__2X); | 109 | BF_CLR(POWER_LOOPCTRL, EN_RCSCALE); |
110 | BF_SETV(POWER_LOOPCTRL, EN_RCSCALE, 1); | ||
111 | } | 111 | } |
112 | 112 | ||
113 | void power_init(void) | 113 | void power_init(void) |
@@ -126,7 +126,7 @@ void power_off(void) | |||
126 | imx233_set_gpio_output(0, 9, true); | 126 | imx233_set_gpio_output(0, 9, true); |
127 | #endif | 127 | #endif |
128 | /* power down */ | 128 | /* power down */ |
129 | HW_POWER_RESET = HW_POWER_RESET__UNLOCK | HW_POWER_RESET__PWD; | 129 | HW_POWER_RESET = BM_OR2(POWER_RESET, UNLOCK, PWD); |
130 | while(1); | 130 | while(1); |
131 | } | 131 | } |
132 | 132 | ||
@@ -138,24 +138,24 @@ unsigned int power_input_status(void) | |||
138 | 138 | ||
139 | bool charging_state(void) | 139 | bool charging_state(void) |
140 | { | 140 | { |
141 | return HW_POWER_STS & HW_POWER_STS__CHRGSTS; | 141 | return BF_RD(POWER_STS, CHRGSTS); |
142 | } | 142 | } |
143 | 143 | ||
144 | void imx233_power_set_charge_current(unsigned current) | 144 | void imx233_power_set_charge_current(unsigned current) |
145 | { | 145 | { |
146 | __REG_CLR(HW_POWER_CHARGE) = HW_POWER_CHARGE__BATTCHRG_I_BM; | 146 | BF_CLR(POWER_CHARGE, BATTCHRG_I); |
147 | /* find closest current LOWER THAN OR EQUAL TO the expected current */ | 147 | /* find closest current LOWER THAN OR EQUAL TO the expected current */ |
148 | for(unsigned i = 0; i < ARRAYLEN(g_charger_current_bits); i++) | 148 | for(unsigned i = 0; i < ARRAYLEN(g_charger_current_bits); i++) |
149 | if(current >= g_charger_current_bits[i].current) | 149 | if(current >= g_charger_current_bits[i].current) |
150 | { | 150 | { |
151 | current -= g_charger_current_bits[i].current; | 151 | current -= g_charger_current_bits[i].current; |
152 | __REG_SET(HW_POWER_CHARGE) = g_charger_current_bits[i].bit; | 152 | BF_SETV(POWER_CHARGE, BATTCHRG_I, g_charger_current_bits[i].bit); |
153 | } | 153 | } |
154 | } | 154 | } |
155 | 155 | ||
156 | void imx233_power_set_stop_current(unsigned current) | 156 | void imx233_power_set_stop_current(unsigned current) |
157 | { | 157 | { |
158 | __REG_CLR(HW_POWER_CHARGE) = HW_POWER_CHARGE__STOP_ILIMIT_BM; | 158 | BF_CLR(POWER_CHARGE, STOP_ILIMIT); |
159 | /* find closest current GREATHER THAN OR EQUAL TO the expected current */ | 159 | /* find closest current GREATHER THAN OR EQUAL TO the expected current */ |
160 | unsigned sum = 0; | 160 | unsigned sum = 0; |
161 | for(unsigned i = 0; i < ARRAYLEN(g_charger_stop_current_bits); i++) | 161 | for(unsigned i = 0; i < ARRAYLEN(g_charger_stop_current_bits); i++) |
@@ -166,7 +166,7 @@ void imx233_power_set_stop_current(unsigned current) | |||
166 | if(current > sum) | 166 | if(current > sum) |
167 | { | 167 | { |
168 | current -= g_charger_stop_current_bits[i].current; | 168 | current -= g_charger_stop_current_bits[i].current; |
169 | __REG_SET(HW_POWER_CHARGE) = g_charger_stop_current_bits[i].bit; | 169 | BF_SETV(POWER_CHARGE, STOP_ILIMIT, g_charger_stop_current_bits[i].bit); |
170 | } | 170 | } |
171 | } | 171 | } |
172 | } | 172 | } |
@@ -191,17 +191,17 @@ static struct | |||
191 | .min = HW_POWER_##name##CTRL__TRG_MIN, \ | 191 | .min = HW_POWER_##name##CTRL__TRG_MIN, \ |
192 | .step = HW_POWER_##name##CTRL__TRG_STEP, \ | 192 | .step = HW_POWER_##name##CTRL__TRG_STEP, \ |
193 | .reg = &HW_POWER_##name##CTRL, \ | 193 | .reg = &HW_POWER_##name##CTRL, \ |
194 | .trg_bm = HW_POWER_##name##CTRL__TRG_BM, \ | 194 | .trg_bm = BM_POWER_##name##CTRL_TRG, \ |
195 | .trg_bp = HW_POWER_##name##CTRL__TRG_BP, \ | 195 | .trg_bp = BP_POWER_##name##CTRL_TRG, \ |
196 | .flags = mask | 196 | .flags = mask |
197 | #define ADD_REGULATOR_BO(name) \ | 197 | #define ADD_REGULATOR_BO(name) \ |
198 | .bo_bm = HW_POWER_##name##CTRL__BO_OFFSET_BM, \ | 198 | .bo_bm = BM_POWER_##name##CTRL_BO_OFFSET, \ |
199 | .bo_bp = HW_POWER_##name##CTRL__BO_OFFSET_BP | 199 | .bo_bp = BP_POWER_##name##CTRL_BO_OFFSET |
200 | #define ADD_REGULATOR_LINREG(name) \ | 200 | #define ADD_REGULATOR_LINREG(name) \ |
201 | .linreg_bm = HW_POWER_##name##CTRL__ENABLE_LINREG | 201 | .linreg_bm = BM_POWER_##name##CTRL_ENABLE_LINREG |
202 | #define ADD_REGULATOR_LINREG_OFFSET(name) \ | 202 | #define ADD_REGULATOR_LINREG_OFFSET(name) \ |
203 | .linreg_offset_bm = HW_POWER_##name##CTRL__LINREG_OFFSET_BM, \ | 203 | .linreg_offset_bm = BM_POWER_##name##CTRL_LINREG_OFFSET, \ |
204 | .linreg_offset_bp = HW_POWER_##name##CTRL__LINREG_OFFSET_BP | 204 | .linreg_offset_bp = BP_POWER_##name##CTRL_LINREG_OFFSET |
205 | [REGULATOR_VDDD] = | 205 | [REGULATOR_VDDD] = |
206 | { | 206 | { |
207 | ADD_REGULATOR(VDDD, HAS_BO|HAS_LINREG|HAS_LINREG_OFFSET), | 207 | ADD_REGULATOR(VDDD, HAS_BO|HAS_LINREG|HAS_LINREG_OFFSET), |
@@ -257,7 +257,7 @@ void imx233_power_set_regulator(enum imx233_regulator_t reg, unsigned value_mv, | |||
257 | unsigned raw_val = (value_mv - regulator_info[reg].min) / regulator_info[reg].step; | 257 | unsigned raw_val = (value_mv - regulator_info[reg].min) / regulator_info[reg].step; |
258 | unsigned raw_bo_offset = (value_mv - brownout_mv) / regulator_info[reg].step; | 258 | unsigned raw_bo_offset = (value_mv - brownout_mv) / regulator_info[reg].step; |
259 | // clear dc-dc ok flag | 259 | // clear dc-dc ok flag |
260 | __REG_SET(HW_POWER_CTRL) = HW_POWER_CTRL__DC_OK_IRQ; | 260 | BF_SET(POWER_CTRL, DC_OK_IRQ); |
261 | // update | 261 | // update |
262 | uint32_t reg_val = (*regulator_info[reg].reg) & ~regulator_info[reg].trg_bm; | 262 | uint32_t reg_val = (*regulator_info[reg].reg) & ~regulator_info[reg].trg_bm; |
263 | reg_val |= raw_val << regulator_info[reg].trg_bp; | 263 | reg_val |= raw_val << regulator_info[reg].trg_bp; |
@@ -271,12 +271,12 @@ void imx233_power_set_regulator(enum imx233_regulator_t reg, unsigned value_mv, | |||
271 | * If DC-DC is used, we can use the DCDC_OK irq | 271 | * If DC-DC is used, we can use the DCDC_OK irq |
272 | * Otherwise it is unreliable (doesn't work when lowering voltage on linregs) | 272 | * Otherwise it is unreliable (doesn't work when lowering voltage on linregs) |
273 | * It usually takes between 0.5ms and 2.5ms */ | 273 | * It usually takes between 0.5ms and 2.5ms */ |
274 | if(!(HW_POWER_5VCTRL & HW_POWER_5VCTRL__ENABLE_DCDC)) | 274 | if(!BF_RD(POWER_5VCTRL, ENABLE_DCDC)) |
275 | panicf("regulator %d: wait for voltage stabilize in linreg mode !", reg); | 275 | panicf("regulator %d: wait for voltage stabilize in linreg mode !", reg); |
276 | unsigned timeout = current_tick + (HZ * 20) / 1000; | 276 | unsigned timeout = current_tick + (HZ * 20) / 1000; |
277 | while(!(HW_POWER_CTRL & HW_POWER_CTRL__DC_OK_IRQ) || !TIME_AFTER(current_tick, timeout)) | 277 | while(!BF_RD(POWER_CTRL, DC_OK_IRQ) || !TIME_AFTER(current_tick, timeout)) |
278 | yield(); | 278 | yield(); |
279 | if(!(HW_POWER_CTRL & HW_POWER_CTRL__DC_OK_IRQ)) | 279 | if(!BF_RD(POWER_CTRL, DC_OK_IRQ)) |
280 | panicf("regulator %d: failed to stabilize", reg); | 280 | panicf("regulator %d: failed to stabilize", reg); |
281 | } | 281 | } |
282 | 282 | ||
@@ -311,55 +311,57 @@ void imx233_power_set_regulator_linreg(enum imx233_regulator_t reg, | |||
311 | struct imx233_power_info_t imx233_power_get_info(unsigned flags) | 311 | struct imx233_power_info_t imx233_power_get_info(unsigned flags) |
312 | { | 312 | { |
313 | static int dcdc_freqsel[8] = { | 313 | static int dcdc_freqsel[8] = { |
314 | [HW_POWER_MISC__FREQSEL__RES] = 0, | 314 | [BV_POWER_MISC_FREQSEL__RES] = 0, |
315 | [HW_POWER_MISC__FREQSEL__20MHz] = 20000, | 315 | [BV_POWER_MISC_FREQSEL__20MHz] = 20000, |
316 | [HW_POWER_MISC__FREQSEL__24MHz] = 24000, | 316 | [BV_POWER_MISC_FREQSEL__24MHz] = 24000, |
317 | [HW_POWER_MISC__FREQSEL__19p2MHz] = 19200, | 317 | [BV_POWER_MISC_FREQSEL__19p2MHz] = 19200, |
318 | [HW_POWER_MISC__FREQSEL__14p4MHz] = 14200, | 318 | [BV_POWER_MISC_FREQSEL__14p4MHz] = 14200, |
319 | [HW_POWER_MISC__FREQSEL__18MHz] = 18000, | 319 | [BV_POWER_MISC_FREQSEL__18MHz] = 18000, |
320 | [HW_POWER_MISC__FREQSEL__21p6MHz] = 21600, | 320 | [BV_POWER_MISC_FREQSEL__21p6MHz] = 21600, |
321 | [HW_POWER_MISC__FREQSEL__17p28MHz] = 17280, | 321 | [BV_POWER_MISC_FREQSEL__17p28MHz] = 17280, |
322 | }; | 322 | }; |
323 | 323 | ||
324 | struct imx233_power_info_t s; | 324 | struct imx233_power_info_t s; |
325 | memset(&s, 0, sizeof(s)); | 325 | memset(&s, 0, sizeof(s)); |
326 | if(flags & POWER_INFO_DCDC) | 326 | if(flags & POWER_INFO_DCDC) |
327 | { | 327 | { |
328 | s.dcdc_sel_pllclk = HW_POWER_MISC & HW_POWER_MISC__SEL_PLLCLK; | 328 | s.dcdc_sel_pllclk = BF_RD(POWER_MISC, SEL_PLLCLK); |
329 | s.dcdc_freqsel = dcdc_freqsel[__XTRACT(HW_POWER_MISC, FREQSEL)]; | 329 | s.dcdc_freqsel = dcdc_freqsel[BF_RD(POWER_MISC, FREQSEL)]; |
330 | } | 330 | } |
331 | if(flags & POWER_INFO_CHARGE) | 331 | if(flags & POWER_INFO_CHARGE) |
332 | { | 332 | { |
333 | uint32_t current = BF_RD(POWER_CHARGE, BATTCHRG_I); | ||
334 | uint32_t stop_current = BF_RD(POWER_CHARGE, STOP_ILIMIT); | ||
333 | for(unsigned i = 0; i < ARRAYLEN(g_charger_current_bits); i++) | 335 | for(unsigned i = 0; i < ARRAYLEN(g_charger_current_bits); i++) |
334 | if(HW_POWER_CHARGE & g_charger_current_bits[i].bit) | 336 | if(current & g_charger_current_bits[i].bit) |
335 | s.charge_current += g_charger_current_bits[i].current; | 337 | s.charge_current += g_charger_current_bits[i].current; |
336 | for(unsigned i = 0; i < ARRAYLEN(g_charger_stop_current_bits); i++) | 338 | for(unsigned i = 0; i < ARRAYLEN(g_charger_stop_current_bits); i++) |
337 | if(HW_POWER_CHARGE & g_charger_stop_current_bits[i].bit) | 339 | if(stop_current & g_charger_stop_current_bits[i].bit) |
338 | s.stop_current += g_charger_stop_current_bits[i].current; | 340 | s.stop_current += g_charger_stop_current_bits[i].current; |
339 | s.charging = HW_POWER_STS & HW_POWER_STS__CHRGSTS; | 341 | s.charging = BF_RD(POWER_STS, CHRGSTS); |
340 | s.batt_adj = HW_POWER_BATTMONITOR & HW_POWER_BATTMONITOR__ENBATADJ; | 342 | s.batt_adj = BF_RD(POWER_BATTMONITOR, EN_BATADJ); |
341 | } | 343 | } |
342 | if(flags & POWER_INFO_4P2) | 344 | if(flags & POWER_INFO_4P2) |
343 | { | 345 | { |
344 | s._4p2_enable = HW_POWER_DCDC4P2 & HW_POWER_DCDC4P2__ENABLE_4P2; | 346 | s._4p2_enable = BF_RD(POWER_DCDC4P2, ENABLE_4P2); |
345 | s._4p2_dcdc = HW_POWER_DCDC4P2 & HW_POWER_DCDC4P2__ENABLE_DCDC; | 347 | s._4p2_dcdc = BF_RD(POWER_DCDC4P2, ENABLE_DCDC); |
346 | s._4p2_cmptrip = __XTRACT(HW_POWER_DCDC4P2, CMPTRIP); | 348 | s._4p2_cmptrip = BF_RD(POWER_DCDC4P2, CMPTRIP); |
347 | s._4p2_dropout = __XTRACT(HW_POWER_DCDC4P2, DROPOUT_CTRL); | 349 | s._4p2_dropout = BF_RD(POWER_DCDC4P2, DROPOUT_CTRL); |
348 | } | 350 | } |
349 | if(flags & POWER_INFO_5V) | 351 | if(flags & POWER_INFO_5V) |
350 | { | 352 | { |
351 | s._5v_pwd_charge_4p2 = HW_POWER_5VCTRL & HW_POWER_5VCTRL__PWD_CHARGE_4P2; | 353 | s._5v_pwd_charge_4p2 = BF_RD(POWER_5VCTRL, PWD_CHARGE_4P2); |
352 | s._5v_dcdc_xfer = HW_POWER_5VCTRL & HW_POWER_5VCTRL__DCDC_XFER; | 354 | s._5v_enable_dcdc = BF_RD(POWER_5VCTRL, ENABLE_DCDC); |
353 | s._5v_enable_dcdc = HW_POWER_5VCTRL & HW_POWER_5VCTRL__ENABLE_DCDC; | 355 | uint32_t charge_4p2_ilimit = BF_RD(POWER_5VCTRL, CHARGE_4P2_ILIMIT); |
354 | for(unsigned i = 0; i < ARRAYLEN(g_4p2_charge_limit_bits); i++) | 356 | for(unsigned i = 0; i < ARRAYLEN(g_4p2_charge_limit_bits); i++) |
355 | if(HW_POWER_5VCTRL & g_4p2_charge_limit_bits[i].bit) | 357 | if(charge_4p2_ilimit & g_4p2_charge_limit_bits[i].bit) |
356 | s._5v_charge_4p2_limit += g_4p2_charge_limit_bits[i].current; | 358 | s._5v_charge_4p2_limit += g_4p2_charge_limit_bits[i].current; |
357 | s._5v_vbusvalid_detect = HW_POWER_5VCTRL & HW_POWER_5VCTRL__VBUSVALID_5VDETECT; | 359 | s._5v_vbusvalid_detect = BF_RD(POWER_5VCTRL, VBUSVALID_5VDETECT); |
358 | s._5v_vbus_cmps = HW_POWER_5VCTRL & HW_POWER_5VCTRL__PWRUP_VBUS_CMPS; | 360 | s._5v_vbus_cmps = BF_RD(POWER_5VCTRL, PWRUP_VBUS_CMPS); |
359 | s._5v_vbusvalid_thr = | 361 | s._5v_vbusvalid_thr = |
360 | __XTRACT(HW_POWER_5VCTRL, VBUSVALID_TRSH) == 0 ? | 362 | BF_RD(POWER_5VCTRL, VBUSVALID_TRSH) == 0 ? |
361 | 2900 | 363 | 2900 |
362 | : 3900 + __XTRACT(HW_POWER_5VCTRL, VBUSVALID_TRSH) * 100; | 364 | : 3900 + BF_RD(POWER_5VCTRL, VBUSVALID_TRSH) * 100; |
363 | } | 365 | } |
364 | return s; | 366 | return s; |
365 | } | 367 | } |
diff --git a/firmware/target/arm/imx233/power-imx233.h b/firmware/target/arm/imx233/power-imx233.h index 5379326969..e6bd02525b 100644 --- a/firmware/target/arm/imx233/power-imx233.h +++ b/firmware/target/arm/imx233/power-imx233.h | |||
@@ -25,157 +25,47 @@ | |||
25 | #include "system-target.h" | 25 | #include "system-target.h" |
26 | #include "cpu.h" | 26 | #include "cpu.h" |
27 | 27 | ||
28 | #define HW_POWER_BASE 0x80044000 | 28 | #include "regs/regs-power.h" |
29 | 29 | ||
30 | #define HW_POWER_CTRL (*(volatile uint32_t *)(HW_POWER_BASE + 0x0)) | 30 | #define BV_POWER_5VCTRL_CHARGE_4P2_ILIMIT__10mA (1 << 0) |
31 | #define HW_POWER_CTRL__ENIRQ_VBUS_VALID (1 << 3) | 31 | #define BV_POWER_5VCTRL_CHARGE_4P2_ILIMIT__20mA (1 << 1) |
32 | #define HW_POWER_CTRL__VBUSVALID_IRQ (1 << 4) | 32 | #define BV_POWER_5VCTRL_CHARGE_4P2_ILIMIT__50mA (1 << 2) |
33 | #define HW_POWER_CTRL__POLARITY_VBUSVALID (1 << 5) | 33 | #define BV_POWER_5VCTRL_CHARGE_4P2_ILIMIT__100mA (1 << 3) |
34 | #define HW_POWER_CTRL__ENIRQ_DC_OK (1 << 14) | 34 | #define BV_POWER_5VCTRL_CHARGE_4P2_ILIMIT__200mA (1 << 4) |
35 | #define HW_POWER_CTRL__DC_OK_IRQ (1 << 15) | 35 | #define BV_POWER_5VCTRL_CHARGE_4P2_ILIMIT__400mA (1 << 5) |
36 | 36 | ||
37 | #define HW_POWER_5VCTRL (*(volatile uint32_t *)(HW_POWER_BASE + 0x10)) | 37 | #define BV_POWER_CHARGE_BATTCHRG_I__10mA (1 << 0) |
38 | #define HW_POWER_5VCTRL__ENABLE_DCDC (1 << 0) | 38 | #define BV_POWER_CHARGE_BATTCHRG_I__20mA (1 << 1) |
39 | #define HW_POWER_5VCTRL__PWRUP_VBUS_CMPS (1 << 1) | 39 | #define BV_POWER_CHARGE_BATTCHRG_I__50mA (1 << 2) |
40 | #define HW_POWER_5VCTRL__VBUSVALID_5VDETECT (1 << 4) | 40 | #define BV_POWER_CHARGE_BATTCHRG_I__100mA (1 << 3) |
41 | #define HW_POWER_5VCTRL__DCDC_XFER (1 << 5) | 41 | #define BV_POWER_CHARGE_BATTCHRG_I__200mA (1 << 4) |
42 | #define HW_POWER_5VCTRL__VBUSVALID_TRSH_BP 8 | 42 | #define BV_POWER_CHARGE_BATTCHRG_I__400mA (1 << 5) |
43 | #define HW_POWER_5VCTRL__VBUSVALID_TRSH_BM (0x7 << 8) | 43 | |
44 | #define HW_POWER_5VCTRL__VBUSVALID_TRSH_2p9 (0 << 8) | 44 | #define BV_POWER_CHARGE_STOP_ILIMIT__10mA (1 << 0) |
45 | #define HW_POWER_5VCTRL__VBUSVALID_TRSH_4V (1 << 8) | 45 | #define BV_POWER_CHARGE_STOP_ILIMIT__20mA (1 << 1) |
46 | #define HW_POWER_5VCTRL__CHARGE_4P2_ILIMIT_BP 12 | 46 | #define BV_POWER_CHARGE_STOP_ILIMIT__50mA (1 << 2) |
47 | #define HW_POWER_5VCTRL__CHARGE_4P2_ILIMIT_BM (0x3f << 12) | 47 | #define BV_POWER_CHARGE_STOP_ILIMIT__100mA (1 << 3) |
48 | #define HW_POWER_5VCTRL__CHARGE_4P2_ILIMIT__10mA (1 << 12) | 48 | |
49 | #define HW_POWER_5VCTRL__CHARGE_4P2_ILIMIT__20mA (1 << 13) | ||
50 | #define HW_POWER_5VCTRL__CHARGE_4P2_ILIMIT__50mA (1 << 14) | ||
51 | #define HW_POWER_5VCTRL__CHARGE_4P2_ILIMIT__100mA (1 << 15) | ||
52 | #define HW_POWER_5VCTRL__CHARGE_4P2_ILIMIT__200mA (1 << 16) | ||
53 | #define HW_POWER_5VCTRL__CHARGE_4P2_ILIMIT__400mA (1 << 17) | ||
54 | #define HW_POWER_5VCTRL__PWD_CHARGE_4P2 (1 << 20) | ||
55 | |||
56 | #define HW_POWER_MINPWR (*(volatile uint32_t *)(HW_POWER_BASE + 0x20)) | ||
57 | #define HW_POWER_MINPWR__HALF_FETS (1 << 5) | ||
58 | #define HW_POWER_MINPWR__DOUBLE_FETS (1 << 6) | ||
59 | |||
60 | #define HW_POWER_CHARGE (*(volatile uint32_t *)(HW_POWER_BASE + 0x30)) | ||
61 | #define HW_POWER_CHARGE__BATTCHRG_I_BP 0 | ||
62 | #define HW_POWER_CHARGE__BATTCHRG_I_BM 0x3f | ||
63 | #define HW_POWER_CHARGE__BATTCHRG_I__10mA (1 << 0) | ||
64 | #define HW_POWER_CHARGE__BATTCHRG_I__20mA (1 << 1) | ||
65 | #define HW_POWER_CHARGE__BATTCHRG_I__50mA (1 << 2) | ||
66 | #define HW_POWER_CHARGE__BATTCHRG_I__100mA (1 << 3) | ||
67 | #define HW_POWER_CHARGE__BATTCHRG_I__200mA (1 << 4) | ||
68 | #define HW_POWER_CHARGE__BATTCHRG_I__400mA (1 << 5) | ||
69 | #define HW_POWER_CHARGE__STOP_ILIMIT_BP 8 | ||
70 | #define HW_POWER_CHARGE__STOP_ILIMIT_BM 0xf00 | ||
71 | #define HW_POWER_CHARGE__STOP_ILIMIT__10mA (1 << 8) | ||
72 | #define HW_POWER_CHARGE__STOP_ILIMIT__20mA (1 << 9) | ||
73 | #define HW_POWER_CHARGE__STOP_ILIMIT__50mA (1 << 10) | ||
74 | #define HW_POWER_CHARGE__STOP_ILIMIT__100mA (1 << 11) | ||
75 | #define HW_POWER_CHARGE__PWD_BATTCHRG (1 << 16) | ||
76 | #define HW_POWER_CHARGE__CHRG_STS_OFF (1 << 19) | ||
77 | #define HW_POWER_CHARGE__ENABLE_LOAD (1 << 22) | ||
78 | |||
79 | #define HW_POWER_VDDDCTRL (*(volatile uint32_t *)(HW_POWER_BASE + 0x40)) | ||
80 | #define HW_POWER_VDDDCTRL__TRG_BP 0 | ||
81 | #define HW_POWER_VDDDCTRL__TRG_BM 0x1f | ||
82 | #define HW_POWER_VDDDCTRL__BO_OFFSET_BP 8 | ||
83 | #define HW_POWER_VDDDCTRL__BO_OFFSET_BM (0x7 << 8) | ||
84 | #define HW_POWER_VDDDCTRL__TRG_STEP 25 /* mV */ | 49 | #define HW_POWER_VDDDCTRL__TRG_STEP 25 /* mV */ |
85 | #define HW_POWER_VDDDCTRL__TRG_MIN 800 /* mV */ | 50 | #define HW_POWER_VDDDCTRL__TRG_MIN 800 /* mV */ |
86 | #define HW_POWER_VDDDCTRL__LINREG_OFFSET_BP 16 | 51 | |
87 | #define HW_POWER_VDDDCTRL__LINREG_OFFSET_BM (0x3 << 16) | ||
88 | #define HW_POWER_VDDDCTRL__ENABLE_LINREG (1 << 21) | ||
89 | |||
90 | #define HW_POWER_VDDACTRL (*(volatile uint32_t *)(HW_POWER_BASE + 0x50)) | ||
91 | #define HW_POWER_VDDACTRL__TRG_BP 0 | ||
92 | #define HW_POWER_VDDACTRL__TRG_BM 0x1f | ||
93 | #define HW_POWER_VDDACTRL__BO_OFFSET_BP 8 | ||
94 | #define HW_POWER_VDDACTRL__BO_OFFSET_BM (0x7 << 8) | ||
95 | #define HW_POWER_VDDACTRL__TRG_STEP 25 /* mV */ | 52 | #define HW_POWER_VDDACTRL__TRG_STEP 25 /* mV */ |
96 | #define HW_POWER_VDDACTRL__TRG_MIN 1500 /* mV */ | 53 | #define HW_POWER_VDDACTRL__TRG_MIN 1500 /* mV */ |
97 | #define HW_POWER_VDDACTRL__LINREG_OFFSET_BP 12 | 54 | |
98 | #define HW_POWER_VDDACTRL__LINREG_OFFSET_BM (0x3 << 12) | ||
99 | #define HW_POWER_VDDACTRL__ENABLE_LINREG (1 << 17) | ||
100 | |||
101 | #define HW_POWER_VDDIOCTRL (*(volatile uint32_t *)(HW_POWER_BASE + 0x60)) | ||
102 | #define HW_POWER_VDDIOCTRL__TRG_BP 0 | ||
103 | #define HW_POWER_VDDIOCTRL__TRG_BM 0x1f | ||
104 | #define HW_POWER_VDDIOCTRL__BO_OFFSET_BP 8 | ||
105 | #define HW_POWER_VDDIOCTRL__BO_OFFSET_BM (0x7 << 8) | ||
106 | #define HW_POWER_VDDIOCTRL__TRG_STEP 25 /* mV */ | 55 | #define HW_POWER_VDDIOCTRL__TRG_STEP 25 /* mV */ |
107 | #define HW_POWER_VDDIOCTRL__TRG_MIN 2800 /* mV */ | 56 | #define HW_POWER_VDDIOCTRL__TRG_MIN 2800 /* mV */ |
108 | #define HW_POWER_VDDIOCTRL__LINREG_OFFSET_BP 12 | ||
109 | #define HW_POWER_VDDIOCTRL__LINREG_OFFSET_BM (0x3 << 12) | ||
110 | 57 | ||
111 | #define HW_POWER_VDDMEMCTRL (*(volatile uint32_t *)(HW_POWER_BASE + 0x70)) | ||
112 | #define HW_POWER_VDDMEMCTRL__TRG_BP 0 | ||
113 | #define HW_POWER_VDDMEMCTRL__TRG_BM 0x1f | ||
114 | #define HW_POWER_VDDMEMCTRL__TRG_STEP 50 /* mV */ | 58 | #define HW_POWER_VDDMEMCTRL__TRG_STEP 50 /* mV */ |
115 | #define HW_POWER_VDDMEMCTRL__TRG_MIN 1700 /* mV */ | 59 | #define HW_POWER_VDDMEMCTRL__TRG_MIN 1700 /* mV */ |
116 | #define HW_POWER_VDDMEMCTRL__ENABLE_LINREG (1 << 8) | 60 | |
117 | 61 | #define BV_POWER_MISC_FREQSEL__RES 0 | |
118 | #define HW_POWER_DCDC4P2 (*(volatile uint32_t *)(HW_POWER_BASE + 0x80)) | 62 | #define BV_POWER_MISC_FREQSEL__20MHz 1 |
119 | #define HW_POWER_DCDC4P2__CMPTRIP_BP 0 | 63 | #define BV_POWER_MISC_FREQSEL__24MHz 2 |
120 | #define HW_POWER_DCDC4P2__CMPTRIP_BM 0x1f | 64 | #define BV_POWER_MISC_FREQSEL__19p2MHz 3 |
121 | #define HW_POWER_DCDC4P2__CMPTRIP__0p85 0 | 65 | #define BV_POWER_MISC_FREQSEL__14p4MHz 4 |
122 | #define HW_POWER_DCDC4P2__ENABLE_DCDC (1 << 22) | 66 | #define BV_POWER_MISC_FREQSEL__18MHz 5 |
123 | #define HW_POWER_DCDC4P2__ENABLE_4P2 (1 << 23) | 67 | #define BV_POWER_MISC_FREQSEL__21p6MHz 6 |
124 | #define HW_POWER_DCDC4P2__DROPOUT_CTRL_BP 28 | 68 | #define BV_POWER_MISC_FREQSEL__17p28MHz 7 |
125 | #define HW_POWER_DCDC4P2__DROPOUT_CTRL_BM (0xf << 28) | ||
126 | #define HW_POWER_DCDC4P2__DROPOUT_CTRL__200mV (3 << 30) | ||
127 | #define HW_POWER_DCDC4P2__DROPOUT_CTRL__HIGHER (2 << 28) | ||
128 | |||
129 | #define HW_POWER_MISC (*(volatile uint32_t *)(HW_POWER_BASE + 0x90)) | ||
130 | #define HW_POWER_MISC__SEL_PLLCLK 1 | ||
131 | #define HW_POWER_MISC__FREQSEL_BP 4 | ||
132 | #define HW_POWER_MISC__FREQSEL_BM (0x7 << 4) | ||
133 | #define HW_POWER_MISC__FREQSEL__RES 0 | ||
134 | #define HW_POWER_MISC__FREQSEL__20MHz 1 | ||
135 | #define HW_POWER_MISC__FREQSEL__24MHz 2 | ||
136 | #define HW_POWER_MISC__FREQSEL__19p2MHz 3 | ||
137 | #define HW_POWER_MISC__FREQSEL__14p4MHz 4 | ||
138 | #define HW_POWER_MISC__FREQSEL__18MHz 5 | ||
139 | #define HW_POWER_MISC__FREQSEL__21p6MHz 6 | ||
140 | #define HW_POWER_MISC__FREQSEL__17p28MHz 7 | ||
141 | |||
142 | #define HW_POWER_LOOPCTRL (*(volatile uint32_t *)(HW_POWER_BASE + 0xb0)) | ||
143 | #define HW_POWER_LOOPCTRL__DC_C_BP 0 | ||
144 | #define HW_POWER_LOOPCTRL__DC_C_BM 0x3 | ||
145 | #define HW_POWER_LOOPCTRL__DC_R_BP 4 | ||
146 | #define HW_POWER_LOOPCTRL__DC_R_BM 0xf0 | ||
147 | #define HW_POWER_LOOPCTRL__DC_FF_BP 8 | ||
148 | #define HW_POWER_LOOPCTRL__DC_FF_BM (0x7 << 8) | ||
149 | #define HW_POWER_LOOPCTRL__EN_RCSCALE_BP 12 | ||
150 | #define HW_POWER_LOOPCTRL__EN_RCSCALE_BM (0x3 << 12) | ||
151 | #define HW_POWER_LOOPCTRL__EN_RCSCALE__DISABLED 0 | ||
152 | #define HW_POWER_LOOPCTRL__EN_RCSCALE__2X 1 | ||
153 | #define HW_POWER_LOOPCTRL__EN_RCSCALE__4X 2 | ||
154 | #define HW_POWER_LOOPCTRL__EN_RCSCALE__8X 3 | ||
155 | #define HW_POWER_LOOPCTRL__RCSCALE_THRESH (1 << 14) | ||
156 | #define HW_POWER_LOOPCTRL__DF_HYST_THRESH (1 << 15) | ||
157 | #define HW_POWER_LOOPCTRL__CM_HYST_THRESH (1 << 16) | ||
158 | #define HW_POWER_LOOPCTRL__EN_DF_HYST (1 << 17) | ||
159 | #define HW_POWER_LOOPCTRL__EN_CM_HYST (1 << 18) | ||
160 | #define HW_POWER_LOOPCTRL__HYST_SIGN (1 << 19) | ||
161 | #define HW_POWER_LOOPCTRL__TOGGLE_DIF (1 << 20) | ||
162 | |||
163 | #define HW_POWER_STS (*(volatile uint32_t *)(HW_POWER_BASE + 0xc0)) | ||
164 | #define HW_POWER_STS__VBUSVALID (1 << 1) | ||
165 | #define HW_POWER_STS__CHRGSTS (1 << 11) | ||
166 | #define HW_POWER_STS__PSWITCH_BP 20 | ||
167 | #define HW_POWER_STS__PSWITCH_BM (3 << 20) | ||
168 | #define HW_POWER_STS__PWRUP_SOURCE_BP 24 | ||
169 | #define HW_POWER_STS__PWRUP_SOURCE_BM (0x3f << 24) | ||
170 | |||
171 | #define HW_POWER_BATTMONITOR (*(volatile uint32_t *)(HW_POWER_BASE + 0xe0)) | ||
172 | #define HW_POWER_BATTMONITOR__ENBATADJ (1 << 10) | ||
173 | #define HW_POWER_BATTMONITOR__BATT_VAL_BP 16 | ||
174 | #define HW_POWER_BATTMONITOR__BATT_VAL_BM (0x3ff << 16) | ||
175 | |||
176 | #define HW_POWER_RESET (*(volatile uint32_t *)(HW_POWER_BASE + 0x100)) | ||
177 | #define HW_POWER_RESET__UNLOCK 0x3E770000 | ||
178 | #define HW_POWER_RESET__PWD 0x1 | ||
179 | 69 | ||
180 | void imx233_power_init(void); | 70 | void imx233_power_init(void); |
181 | 71 | ||
@@ -209,13 +99,9 @@ void imx233_power_set_regulator_linreg(enum imx233_regulator_t reg, | |||
209 | 99 | ||
210 | static inline void imx233_power_set_dcdc_freq(bool pll, unsigned freq) | 100 | static inline void imx233_power_set_dcdc_freq(bool pll, unsigned freq) |
211 | { | 101 | { |
212 | HW_POWER_MISC &= ~(HW_POWER_MISC__SEL_PLLCLK | HW_POWER_MISC__FREQSEL_BM); | ||
213 | /* WARNING: HW_POWER_MISC does not have a SET/CLR variant ! */ | ||
214 | if(pll) | 102 | if(pll) |
215 | { | 103 | BF_WR(POWER_MISC, FREQSEL, freq); |
216 | HW_POWER_MISC |= freq << HW_POWER_MISC__FREQSEL_BP; | 104 | BF_WR(POWER_MISC, SEL_PLLCLK, pll); |
217 | HW_POWER_MISC |= HW_POWER_MISC__SEL_PLLCLK; | ||
218 | } | ||
219 | } | 105 | } |
220 | 106 | ||
221 | struct imx233_power_info_t | 107 | struct imx233_power_info_t |
diff --git a/firmware/target/arm/imx233/powermgmt-imx233.c b/firmware/target/arm/imx233/powermgmt-imx233.c index 31f9ac7659..b155b5fcb8 100644 --- a/firmware/target/arm/imx233/powermgmt-imx233.c +++ b/firmware/target/arm/imx233/powermgmt-imx233.c | |||
@@ -41,7 +41,7 @@ static int timeout_4p2_ilimit_increase; /* timeout before increasing 4p2 ilimit | |||
41 | int _battery_voltage(void) | 41 | int _battery_voltage(void) |
42 | { | 42 | { |
43 | /* battery value is in 8mV LSB */ | 43 | /* battery value is in 8mV LSB */ |
44 | return __XTRACT(HW_POWER_BATTMONITOR, BATT_VAL) * 8; | 44 | return BF_RD(POWER_BATTMONITOR, BATT_VAL) * 8; |
45 | } | 45 | } |
46 | 46 | ||
47 | void powermgmt_init_target(void) | 47 | void powermgmt_init_target(void) |
@@ -49,12 +49,12 @@ void powermgmt_init_target(void) | |||
49 | imx233_power_set_charge_current(IMX233_CHARGE_CURRENT); | 49 | imx233_power_set_charge_current(IMX233_CHARGE_CURRENT); |
50 | imx233_power_set_stop_current(IMX233_STOP_CURRENT); | 50 | imx233_power_set_stop_current(IMX233_STOP_CURRENT); |
51 | /* assume that adc_init was called and battery monitoring via LRADC setup */ | 51 | /* assume that adc_init was called and battery monitoring via LRADC setup */ |
52 | __REG_SET(HW_POWER_BATTMONITOR) = HW_POWER_BATTMONITOR__ENBATADJ; | 52 | BF_WR(POWER_BATTMONITOR, EN_BATADJ, 1); |
53 | /* make sure we are in a known state: disable charger and 4p2 */ | 53 | /* make sure we are in a known state: disable charger and 4p2 */ |
54 | __REG_SET(HW_POWER_CHARGE) = HW_POWER_CHARGE__PWD_BATTCHRG; | 54 | BF_SET(POWER_CHARGE, PWD_BATTCHRG); |
55 | __REG_CLR(HW_POWER_DCDC4P2) = HW_POWER_DCDC4P2__ENABLE_DCDC | | 55 | BF_WR(POWER_DCDC4P2, ENABLE_DCDC, 0); |
56 | HW_POWER_DCDC4P2__ENABLE_4P2; | 56 | BF_WR(POWER_DCDC4P2, ENABLE_4P2, 0); |
57 | __REG_SET(HW_POWER_5VCTRL) = HW_POWER_5VCTRL__PWD_CHARGE_4P2; | 57 | BF_SET(POWER_5VCTRL, PWD_CHARGE_4P2); |
58 | charge_state = DISCHARGING; | 58 | charge_state = DISCHARGING; |
59 | } | 59 | } |
60 | 60 | ||
@@ -68,10 +68,10 @@ void charging_algorithm_step(void) | |||
68 | logf("pwrmgmt: * -> discharging"); | 68 | logf("pwrmgmt: * -> discharging"); |
69 | logf("pwrmgmt: disable charger and 4p2"); | 69 | logf("pwrmgmt: disable charger and 4p2"); |
70 | /* 5V has been lost: disable 4p2 power rail */ | 70 | /* 5V has been lost: disable 4p2 power rail */ |
71 | __REG_SET(HW_POWER_CHARGE) = HW_POWER_CHARGE__PWD_BATTCHRG; | 71 | BF_SET(POWER_CHARGE, PWD_BATTCHRG); |
72 | __REG_CLR(HW_POWER_DCDC4P2) = HW_POWER_DCDC4P2__ENABLE_DCDC | | 72 | BF_WR(POWER_DCDC4P2, ENABLE_DCDC, 0); |
73 | HW_POWER_DCDC4P2__ENABLE_4P2; | 73 | BF_WR(POWER_DCDC4P2, ENABLE_4P2, 0); |
74 | __REG_SET(HW_POWER_5VCTRL) = HW_POWER_5VCTRL__PWD_CHARGE_4P2; | 74 | BF_SET(POWER_5VCTRL, PWD_CHARGE_4P2); |
75 | charge_state = DISCHARGING; | 75 | charge_state = DISCHARGING; |
76 | } | 76 | } |
77 | /* battery -> 5v transition */ | 77 | /* battery -> 5v transition */ |
@@ -80,11 +80,11 @@ void charging_algorithm_step(void) | |||
80 | logf("pwrmgmt: discharging -> trickle"); | 80 | logf("pwrmgmt: discharging -> trickle"); |
81 | logf("pwrmgmt: begin charging 4p2"); | 81 | logf("pwrmgmt: begin charging 4p2"); |
82 | /* 5V has been detected: prepare 4.2V power rail for activation */ | 82 | /* 5V has been detected: prepare 4.2V power rail for activation */ |
83 | __REG_SET(HW_POWER_DCDC4P2) = HW_POWER_DCDC4P2__ENABLE_4P2; | 83 | BF_WR(POWER_DCDC4P2, ENABLE_4P2, 1); |
84 | __REG_SET(HW_POWER_CHARGE) = HW_POWER_CHARGE__ENABLE_LOAD; | 84 | BF_SET(POWER_CHARGE, ENABLE_LOAD); |
85 | __FIELD_SET(HW_POWER_5VCTRL, CHARGE_4P2_ILIMIT, 1); | 85 | BF_WR(POWER_5VCTRL, CHARGE_4P2_ILIMIT, 1); |
86 | __REG_CLR(HW_POWER_5VCTRL) = HW_POWER_5VCTRL__PWD_CHARGE_4P2;// FIXME: manual error ? | 86 | BF_CLR(POWER_5VCTRL, PWD_CHARGE_4P2);// FIXME: manual error ? |
87 | __REG_SET(HW_POWER_DCDC4P2) = HW_POWER_DCDC4P2__ENABLE_DCDC; | 87 | BF_WR(POWER_DCDC4P2, ENABLE_DCDC, 1); |
88 | timeout_4p2_ilimit_increase = current_tick + HZ / 100; | 88 | timeout_4p2_ilimit_increase = current_tick + HZ / 100; |
89 | charge_state = TRICKLE; | 89 | charge_state = TRICKLE; |
90 | } | 90 | } |
@@ -92,10 +92,10 @@ void charging_algorithm_step(void) | |||
92 | { | 92 | { |
93 | /* if 4.2V current limit has not reached 780mA, increase it slowly to | 93 | /* if 4.2V current limit has not reached 780mA, increase it slowly to |
94 | * charge the 4.2V capacitance */ | 94 | * charge the 4.2V capacitance */ |
95 | if(__XTRACT(HW_POWER_5VCTRL, CHARGE_4P2_ILIMIT) != 0x3f) | 95 | if(BF_RD(POWER_5VCTRL, CHARGE_4P2_ILIMIT) != 0x3f) |
96 | { | 96 | { |
97 | //logf("pwrmgmt: incr 4.2 ilimit"); | 97 | //logf("pwrmgmt: incr 4.2 ilimit"); |
98 | HW_POWER_5VCTRL += 1 << HW_POWER_5VCTRL__CHARGE_4P2_ILIMIT_BP; | 98 | HW_POWER_5VCTRL += BF_POWER_5VCTRL_CHARGE_4P2_ILIMIT(1); |
99 | timeout_4p2_ilimit_increase = current_tick + HZ / 100; | 99 | timeout_4p2_ilimit_increase = current_tick + HZ / 100; |
100 | } | 100 | } |
101 | /* we've reached the maximum, take action */ | 101 | /* we've reached the maximum, take action */ |
@@ -104,12 +104,12 @@ void charging_algorithm_step(void) | |||
104 | logf("pwrmgmt: enable dcdc and charger"); | 104 | logf("pwrmgmt: enable dcdc and charger"); |
105 | logf("pwrmgmt: trickle -> charging"); | 105 | logf("pwrmgmt: trickle -> charging"); |
106 | /* adjust arbitration between 4.2 and battery */ | 106 | /* adjust arbitration between 4.2 and battery */ |
107 | __FIELD_SET(HW_POWER_DCDC4P2, CMPTRIP, 0); /* 85% */ | 107 | BF_WR(POWER_DCDC4P2, CMPTRIP, 0); /* 85% */ |
108 | __FIELD_SET(HW_POWER_DCDC4P2, DROPOUT_CTRL, 0xe); /* select greater, 200 mV drop */ | 108 | BF_WR(POWER_DCDC4P2, DROPOUT_CTRL, 0xe); /* select greater, 200 mV drop */ |
109 | __REG_CLR(HW_POWER_5VCTRL) = HW_POWER_5VCTRL__DCDC_XFER; | 109 | BF_CLR(POWER_5VCTRL, DCDC_XFER); |
110 | __REG_SET(HW_POWER_5VCTRL) = HW_POWER_5VCTRL__ENABLE_DCDC; | 110 | BF_SET(POWER_5VCTRL, ENABLE_DCDC); |
111 | /* enable battery charging */ | 111 | /* enable battery charging */ |
112 | __REG_CLR(HW_POWER_CHARGE) = HW_POWER_CHARGE__PWD_BATTCHRG; | 112 | BF_CLR(POWER_CHARGE, PWD_BATTCHRG); |
113 | charge_state = CHARGING; | 113 | charge_state = CHARGING; |
114 | timeout_charging = current_tick + IMX233_CHARGING_TIMEOUT; | 114 | timeout_charging = current_tick + IMX233_CHARGING_TIMEOUT; |
115 | } | 115 | } |
@@ -120,11 +120,11 @@ void charging_algorithm_step(void) | |||
120 | logf("pwrmgmt: charging timeout exceeded!"); | 120 | logf("pwrmgmt: charging timeout exceeded!"); |
121 | logf("pwrmgmt: charging -> error"); | 121 | logf("pwrmgmt: charging -> error"); |
122 | /* stop charging */ | 122 | /* stop charging */ |
123 | __REG_SET(HW_POWER_5VCTRL) = HW_POWER_5VCTRL__PWD_CHARGE_4P2; | 123 | BF_SET(POWER_5VCTRL, PWD_CHARGE_4P2); |
124 | /* goto error state */ | 124 | /* goto error state */ |
125 | charge_state = CHARGE_STATE_ERROR; | 125 | charge_state = CHARGE_STATE_ERROR; |
126 | } | 126 | } |
127 | else if(charge_state == CHARGING && !(HW_POWER_STS & HW_POWER_STS__CHRGSTS)) | 127 | else if(charge_state == CHARGING && !BF_RD(POWER_STS, CHRGSTS)) |
128 | { | 128 | { |
129 | logf("pwrmgmt: topping off"); | 129 | logf("pwrmgmt: topping off"); |
130 | logf("pwrmgmt: charging -> topoff"); | 130 | logf("pwrmgmt: charging -> topoff"); |
@@ -136,7 +136,7 @@ void charging_algorithm_step(void) | |||
136 | logf("pwrmgmt: charging finished"); | 136 | logf("pwrmgmt: charging finished"); |
137 | logf("pwrmgmt: topoff -> disabled"); | 137 | logf("pwrmgmt: topoff -> disabled"); |
138 | /* stop charging */ | 138 | /* stop charging */ |
139 | __REG_SET(HW_POWER_CHARGE) = HW_POWER_CHARGE__PWD_BATTCHRG; | 139 | BF_SET(POWER_CHARGE, PWD_BATTCHRG); |
140 | charge_state = CHARGE_STATE_DISABLED; | 140 | charge_state = CHARGE_STATE_DISABLED; |
141 | } | 141 | } |
142 | } | 142 | } |
diff --git a/firmware/target/arm/imx233/sansa-fuzeplus/button-fuzeplus.c b/firmware/target/arm/imx233/sansa-fuzeplus/button-fuzeplus.c index 86bb00f4a5..703e87fc42 100644 --- a/firmware/target/arm/imx233/sansa-fuzeplus/button-fuzeplus.c +++ b/firmware/target/arm/imx233/sansa-fuzeplus/button-fuzeplus.c | |||
@@ -369,7 +369,7 @@ int button_read_device(void) | |||
369 | static int volume_power_lock = 0; | 369 | static int volume_power_lock = 0; |
370 | if(volume_power_lock > 0) | 370 | if(volume_power_lock > 0) |
371 | volume_power_lock--; | 371 | volume_power_lock--; |
372 | switch(__XTRACT(HW_POWER_STS, PSWITCH)) | 372 | switch(BF_RD(POWER_STS, PSWITCH)) |
373 | { | 373 | { |
374 | case 1: | 374 | case 1: |
375 | if(volume_power_lock == 0) | 375 | if(volume_power_lock == 0) |
diff --git a/firmware/target/arm/imx233/usb-imx233.c b/firmware/target/arm/imx233/usb-imx233.c index d27f3ee55c..4e7656f7ab 100644 --- a/firmware/target/arm/imx233/usb-imx233.c +++ b/firmware/target/arm/imx233/usb-imx233.c | |||
@@ -61,7 +61,7 @@ void usb_init_device(void) | |||
61 | 61 | ||
62 | int usb_detect(void) | 62 | int usb_detect(void) |
63 | { | 63 | { |
64 | return (HW_POWER_STS & HW_POWER_STS__VBUSVALID) ? USB_INSERTED : USB_EXTRACTED; | 64 | return BF_RD(POWER_STS, VBUSVALID) ? USB_INSERTED : USB_EXTRACTED; |
65 | } | 65 | } |
66 | 66 | ||
67 | void usb_enable(bool on) | 67 | void usb_enable(bool on) |