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author | Daniel Ankers <dan@weirdo.org.uk> | 2006-11-22 00:49:16 +0000 |
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committer | Daniel Ankers <dan@weirdo.org.uk> | 2006-11-22 00:49:16 +0000 |
commit | 43e2c01065df95bac37e2efd15d61c86b736e1c0 (patch) | |
tree | 29683fdac7b6d11fd8d57f56c585707a8ed1e241 /firmware/target/arm/crt0-pp.S | |
parent | 242cbd5cd73542c79020a4ce9a8e83ee0391bc72 (diff) | |
download | rockbox-43e2c01065df95bac37e2efd15d61c86b736e1c0.tar.gz rockbox-43e2c01065df95bac37e2efd15d61c86b736e1c0.zip |
Sansa doesn't use a Wolfson codec. Various other changes to allow Sansa to compile correctly with a normal build. Based on FS#6336 by Pavel Gnelitsa
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@11570 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/crt0-pp.S')
-rw-r--r-- | firmware/target/arm/crt0-pp.S | 18 |
1 files changed, 16 insertions, 2 deletions
diff --git a/firmware/target/arm/crt0-pp.S b/firmware/target/arm/crt0-pp.S index d847d9d943..17b1e8a4a3 100644 --- a/firmware/target/arm/crt0-pp.S +++ b/firmware/target/arm/crt0-pp.S | |||
@@ -47,14 +47,28 @@ start: | |||
47 | .equ SLEEP, 0x80000000 | 47 | .equ SLEEP, 0x80000000 |
48 | .equ WAKE, 0x0 | 48 | .equ WAKE, 0x0 |
49 | .equ SLEEPING, 0x80000000 | 49 | .equ SLEEPING, 0x80000000 |
50 | .equ CACHE_CTRL, 0x6000c000 | ||
50 | #endif | 51 | #endif |
51 | 52 | ||
52 | msr cpsr_c, #0xd3 /* enter supervisor mode, disable IRQ */ | 53 | msr cpsr_c, #0xd3 /* enter supervisor mode, disable IRQ */ |
53 | 54 | ||
54 | #ifndef BOOTLOADER | 55 | #ifndef BOOTLOADER |
55 | b pad_skip | 56 | b pad_skip |
56 | .space 50*4 /* (more than enough) space for exception vectors */ | 57 | |
58 | #if defined(SANSA_E200) | ||
59 | /* mi4tool writes junk between 0xe0 and 0xeb. Avoid this. */ | ||
60 | .space 60*4 /* (more than enough) space for exception vectors */ | ||
61 | #else | ||
62 | .space 50*4 | ||
63 | #endif | ||
64 | |||
57 | pad_skip: | 65 | pad_skip: |
66 | #ifdef SANSA_E200 | ||
67 | /* On the Sansa, copying the vectors fails if the cache is initialised */ | ||
68 | ldr r1, =CACHE_CTRL | ||
69 | mov r2, #0x0 | ||
70 | str r2, [r1] | ||
71 | #endif | ||
58 | /* We need to remap memory from wherever SDRAM is mapped natively, to | 72 | /* We need to remap memory from wherever SDRAM is mapped natively, to |
59 | base address 0, so we can put our exception vectors there. We don't | 73 | base address 0, so we can put our exception vectors there. We don't |
60 | want to do this remapping while executing from SDRAM, so we copy the | 74 | want to do this remapping while executing from SDRAM, so we copy the |
@@ -126,7 +140,7 @@ remap_end: | |||
126 | ldr r0, =fiq_handler | 140 | ldr r0, =fiq_handler |
127 | str r0, [r1, #28] | 141 | str r0, [r1, #28] |
128 | #endif | 142 | #endif |
129 | 143 | ||
130 | #ifndef STUB | 144 | #ifndef STUB |
131 | /* Zero out IBSS */ | 145 | /* Zero out IBSS */ |
132 | ldr r2, =_iedata | 146 | ldr r2, =_iedata |