From 43e2c01065df95bac37e2efd15d61c86b736e1c0 Mon Sep 17 00:00:00 2001 From: Daniel Ankers Date: Wed, 22 Nov 2006 00:49:16 +0000 Subject: Sansa doesn't use a Wolfson codec. Various other changes to allow Sansa to compile correctly with a normal build. Based on FS#6336 by Pavel Gnelitsa git-svn-id: svn://svn.rockbox.org/rockbox/trunk@11570 a1c6a512-1295-4272-9138-f99709370657 --- firmware/target/arm/crt0-pp.S | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) (limited to 'firmware/target/arm/crt0-pp.S') diff --git a/firmware/target/arm/crt0-pp.S b/firmware/target/arm/crt0-pp.S index d847d9d943..17b1e8a4a3 100644 --- a/firmware/target/arm/crt0-pp.S +++ b/firmware/target/arm/crt0-pp.S @@ -47,14 +47,28 @@ start: .equ SLEEP, 0x80000000 .equ WAKE, 0x0 .equ SLEEPING, 0x80000000 + .equ CACHE_CTRL, 0x6000c000 #endif msr cpsr_c, #0xd3 /* enter supervisor mode, disable IRQ */ #ifndef BOOTLOADER b pad_skip -.space 50*4 /* (more than enough) space for exception vectors */ + +#if defined(SANSA_E200) +/* mi4tool writes junk between 0xe0 and 0xeb. Avoid this. */ +.space 60*4 /* (more than enough) space for exception vectors */ +#else +.space 50*4 +#endif + pad_skip: +#ifdef SANSA_E200 + /* On the Sansa, copying the vectors fails if the cache is initialised */ + ldr r1, =CACHE_CTRL + mov r2, #0x0 + str r2, [r1] +#endif /* We need to remap memory from wherever SDRAM is mapped natively, to base address 0, so we can put our exception vectors there. We don't want to do this remapping while executing from SDRAM, so we copy the @@ -126,7 +140,7 @@ remap_end: ldr r0, =fiq_handler str r0, [r1, #28] #endif - + #ifndef STUB /* Zero out IBSS */ ldr r2, =_iedata -- cgit v1.2.3