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author | Michael Sevakis <jethead71@rockbox.org> | 2010-06-30 02:02:46 +0000 |
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committer | Michael Sevakis <jethead71@rockbox.org> | 2010-06-30 02:02:46 +0000 |
commit | e286b0bbc04a34c181978efce19c6d0814e228c0 (patch) | |
tree | 841288761e20dc9a7a25e5ba83306adf52547d65 /firmware/target/arm/bits-armv4.S | |
parent | f4a00174b50c209f2a23b7a73fe7cb544ef59d02 (diff) | |
download | rockbox-e286b0bbc04a34c181978efce19c6d0814e228c0.tar.gz rockbox-e286b0bbc04a34c181978efce19c6d0814e228c0.zip |
Remove atomic register bit manipulation functions from i.MX and s3c target code and introduce generic functions for ARM (bitmod32, bitset32, and bitclr32). Multiprocessor support is possible but just not implemented at the moment, only interrupt lockout.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@27188 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/bits-armv4.S')
-rw-r--r-- | firmware/target/arm/bits-armv4.S | 77 |
1 files changed, 77 insertions, 0 deletions
diff --git a/firmware/target/arm/bits-armv4.S b/firmware/target/arm/bits-armv4.S new file mode 100644 index 0000000000..05d61b8b7e --- /dev/null +++ b/firmware/target/arm/bits-armv4.S | |||
@@ -0,0 +1,77 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2010 by Michael Sevakis | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | |||
22 | /*************************************************************************** | ||
23 | * void bitmod32(volatile uint32_t *addr, uint32_t bits, uint32_t mask) | ||
24 | */ | ||
25 | .section .text, "ax", %progbits | ||
26 | .align 2 | ||
27 | .global bitmod32 | ||
28 | .type bitmod32, %function | ||
29 | bitmod32: | ||
30 | mrs r12, cpsr | ||
31 | orr r3, r12, #0xc0 | ||
32 | msr cpsr_c, r3 | ||
33 | ldr r3, [r0] | ||
34 | and r1, r1, r2 @ Only allow mod of bits in 'mask' | ||
35 | bic r3, r3, r2 @ Clear mask bits | ||
36 | orr r3, r3, r1 @ Set according to 'bits' | ||
37 | str r3, [r0] | ||
38 | msr cpsr_c, r12 | ||
39 | bx lr | ||
40 | .size bitmod32, .-bitmod32 | ||
41 | |||
42 | /*************************************************************************** | ||
43 | * void bitset32(volatile uint32_t *addr, uint32_t mask) | ||
44 | */ | ||
45 | .section .text, "ax", %progbits | ||
46 | .align 2 | ||
47 | .global bitset32 | ||
48 | .type bitset32, %function | ||
49 | bitset32: | ||
50 | mrs r12, cpsr | ||
51 | orr r2, r12, #0xc0 | ||
52 | msr cpsr_c, r2 | ||
53 | ldr r2, [r0] | ||
54 | orr r2, r2, r1 | ||
55 | str r2, [r0] | ||
56 | msr cpsr_c, r12 | ||
57 | bx lr | ||
58 | .size bitset32, .-bitset32 | ||
59 | |||
60 | |||
61 | /*************************************************************************** | ||
62 | * void bitclr32(volatile uint32_t *addr, uint32_t mask) | ||
63 | */ | ||
64 | .section .text, "ax", %progbits | ||
65 | .align 2 | ||
66 | .global bitclr32 | ||
67 | .type bitclr32, %function | ||
68 | bitclr32: | ||
69 | mrs r12, cpsr | ||
70 | orr r2, r12, #0xc0 | ||
71 | msr cpsr_c, r2 | ||
72 | ldr r2, [r0] | ||
73 | bic r2, r2, r1 | ||
74 | str r2, [r0] | ||
75 | msr cpsr_c, r12 | ||
76 | bx lr | ||
77 | .size bitclr32, .-bitclr32 | ||