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author | Jack Halpin <jack.halpin@gmail.com> | 2010-03-23 17:00:59 +0000 |
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committer | Jack Halpin <jack.halpin@gmail.com> | 2010-03-23 17:00:59 +0000 |
commit | 19fc7297bae8225bfaab51bd8b1f2f8c3aa67858 (patch) | |
tree | 29cd8b2c40bb0f8f442f68db959838776ef097a9 /firmware/target/arm/as3525/sd-as3525v2.c | |
parent | 2d174af4433aae8cf407c7c42e1f7b90e363c5b5 (diff) | |
download | rockbox-19fc7297bae8225bfaab51bd8b1f2f8c3aa67858.tar.gz rockbox-19fc7297bae8225bfaab51bd8b1f2f8c3aa67858.zip |
SansaAMSv2: Give register CGU_BASE + 0x3C the name CGU_SDSLOT.
Move CLKDIV macros into clock-target.h.
Only enable the necessary interfaces for the 3 clock registers used for SD.
Add MEMSTICK and SDSLOT registers to bottom of register display in View HW info debug page.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25309 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/as3525/sd-as3525v2.c')
-rw-r--r-- | firmware/target/arm/as3525/sd-as3525v2.c | 18 |
1 files changed, 10 insertions, 8 deletions
diff --git a/firmware/target/arm/as3525/sd-as3525v2.c b/firmware/target/arm/as3525/sd-as3525v2.c index 945d6e5302..250dfca784 100644 --- a/firmware/target/arm/as3525/sd-as3525v2.c +++ b/firmware/target/arm/as3525/sd-as3525v2.c | |||
@@ -641,18 +641,20 @@ static void init_controller(void) | |||
641 | int sd_init(void) | 641 | int sd_init(void) |
642 | { | 642 | { |
643 | int ret; | 643 | int ret; |
644 | |||
644 | CGU_PERI |= CGU_MCI_CLOCK_ENABLE; | 645 | CGU_PERI |= CGU_MCI_CLOCK_ENABLE; |
645 | 646 | ||
646 | CGU_IDE = (1<<7) /* AHB interface enable */ | | 647 | CGU_IDE = (1<<7) /* AHB interface enable */ |
647 | (1<<6) /* interface enable */ | | 648 | | (AS3525_IDE_DIV << 2) |
648 | ((CLK_DIV(AS3525_PLLA_FREQ, AS3525_IDE_FREQ) - 1) << 2) | | 649 | | 1; /* clock source = PLLA */ |
649 | 1; /* clock source = PLLA */ | ||
650 | 650 | ||
651 | CGU_MEMSTICK = (1<<8) | (1<<7) | | 651 | CGU_MEMSTICK = (1<<7) /* interface enable */ |
652 | ((CLK_DIV(AS3525_PLLA_FREQ, AS3525_MS_FREQ) -1) << 2) | 1; | 652 | | (AS3525_MS_DIV << 2) |
653 | | 1; /* clock source = PLLA */ | ||
653 | 654 | ||
654 | *(volatile int*)(CGU_BASE+0x3C) = (1<<7) | | 655 | CGU_SDSLOT = (1<<7) /* interface enable */ |
655 | (CLK_DIV(AS3525_PLLA_FREQ, 24000000) -1)<<2 | 1; | 656 | | (AS3525_SDSLOT_DIV << 2) |
657 | | 1; /* clock source = PLLA */ | ||
656 | 658 | ||
657 | wakeup_init(&transfer_completion_signal); | 659 | wakeup_init(&transfer_completion_signal); |
658 | 660 | ||