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author | Rafaël Carré <rafael.carre@gmail.com> | 2008-12-04 20:04:31 +0000 |
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committer | Rafaël Carré <rafael.carre@gmail.com> | 2008-12-04 20:04:31 +0000 |
commit | 45711ac2869f955c40be96d8dcbc7201c718dba4 (patch) | |
tree | ef022bec4b6e8bcc11005de34d300e073c60770d /firmware/target/arm/as3525/sansa-e200v2/lcd-e200v2.c | |
parent | 7ea9e31658da4fce9c4a3e30838b82fda8eda287 (diff) | |
download | rockbox-45711ac2869f955c40be96d8dcbc7201c718dba4.tar.gz rockbox-45711ac2869f955c40be96d8dcbc7201c718dba4.zip |
Sansa AMS: centralize clock settings in clock-target.h
Reorder system_init() to initialize peripherals not only in bootloader
Use a 65MHz PCLK (and memclk) which will be needed for realtime decoding
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@19330 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/as3525/sansa-e200v2/lcd-e200v2.c')
-rw-r--r-- | firmware/target/arm/as3525/sansa-e200v2/lcd-e200v2.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/firmware/target/arm/as3525/sansa-e200v2/lcd-e200v2.c b/firmware/target/arm/as3525/sansa-e200v2/lcd-e200v2.c index 6bdee395c0..f157b552e4 100644 --- a/firmware/target/arm/as3525/sansa-e200v2/lcd-e200v2.c +++ b/firmware/target/arm/as3525/sansa-e200v2/lcd-e200v2.c | |||
@@ -31,6 +31,7 @@ | |||
31 | #include "system.h" | 31 | #include "system.h" |
32 | #include "font.h" | 32 | #include "font.h" |
33 | #include "bidi.h" | 33 | #include "bidi.h" |
34 | #include "clock-target.h" | ||
34 | 35 | ||
35 | static bool display_on = false; /* is the display turned on? */ | 36 | static bool display_on = false; /* is the display turned on? */ |
36 | static bool display_flipped = false; | 37 | static bool display_flipped = false; |
@@ -94,7 +95,7 @@ static void lcd_delay(int x) | |||
94 | /* DBOP initialisation, do what OF does */ | 95 | /* DBOP initialisation, do what OF does */ |
95 | static void ams3525_dbop_init(void) | 96 | static void ams3525_dbop_init(void) |
96 | { | 97 | { |
97 | CGU_DBOP = (1<<3) | (3-1); | 98 | CGU_DBOP = (1<<3) | CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ); |
98 | 99 | ||
99 | DBOP_TIMPOL_01 = 0xe167e167; | 100 | DBOP_TIMPOL_01 = 0xe167e167; |
100 | DBOP_TIMPOL_23 = 0xe167006e; | 101 | DBOP_TIMPOL_23 = 0xe167006e; |