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authorRafaël Carré <rafael.carre@gmail.com>2010-05-27 23:32:38 +0000
committerRafaël Carré <rafael.carre@gmail.com>2010-05-27 23:32:38 +0000
commit6921a2b6b988e40fed1c2c3c5182381c26ef3d75 (patch)
treedd3ca9554ecf0a24d704d84b976b745955545b3e /firmware/target/arm/as3525/lcd-fuze.h
parent9d583f2b0b52919d961ed1853babebd6ec377c1d (diff)
downloadrockbox-6921a2b6b988e40fed1c2c3c5182381c26ef3d75.tar.gz
rockbox-6921a2b6b988e40fed1c2c3c5182381c26ef3d75.zip
Merge common LCD code between fuzev1 & fuzev2
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@26344 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/as3525/lcd-fuze.h')
-rw-r--r--firmware/target/arm/as3525/lcd-fuze.h56
1 files changed, 56 insertions, 0 deletions
diff --git a/firmware/target/arm/as3525/lcd-fuze.h b/firmware/target/arm/as3525/lcd-fuze.h
new file mode 100644
index 0000000000..00bb960ef1
--- /dev/null
+++ b/firmware/target/arm/as3525/lcd-fuze.h
@@ -0,0 +1,56 @@
1/* register defines */
2#define R_START_OSC 0x00
3#define R_DRV_OUTPUT_CONTROL 0x01
4#define R_DRV_WAVEFORM_CONTROL 0x02
5#define R_ENTRY_MODE 0x03
6#define R_COMPARE_REG1 0x04
7#define R_COMPARE_REG2 0x05
8
9#define R_DISP_CONTROL1 0x07
10#define R_DISP_CONTROL2 0x08
11#define R_DISP_CONTROL3 0x09
12
13#define R_FRAME_CYCLE_CONTROL 0x0b
14#define R_EXT_DISP_IF_CONTROL 0x0c
15
16#define R_POWER_CONTROL1 0x10
17#define R_POWER_CONTROL2 0x11
18#define R_POWER_CONTROL3 0x12
19#define R_POWER_CONTROL4 0x13
20
21#define R_RAM_ADDR_SET 0x21
22#define R_WRITE_DATA_2_GRAM 0x22
23
24#define R_GAMMA_FINE_ADJ_POS1 0x30
25#define R_GAMMA_FINE_ADJ_POS2 0x31
26#define R_GAMMA_FINE_ADJ_POS3 0x32
27#define R_GAMMA_GRAD_ADJ_POS 0x33
28
29#define R_GAMMA_FINE_ADJ_NEG1 0x34
30#define R_GAMMA_FINE_ADJ_NEG2 0x35
31#define R_GAMMA_FINE_ADJ_NEG3 0x36
32#define R_GAMMA_GRAD_ADJ_NEG 0x37
33
34#define R_GAMMA_AMP_ADJ_RES_POS 0x38
35#define R_GAMMA_AMP_AVG_ADJ_RES_NEG 0x39
36
37#define R_GATE_SCAN_POS 0x40
38#define R_VERT_SCROLL_CONTROL 0x41
39#define R_1ST_SCR_DRV_POS 0x42
40#define R_2ND_SCR_DRV_POS 0x43
41#define R_HORIZ_RAM_ADDR_POS 0x44
42#define R_VERT_RAM_ADDR_POS 0x45
43
44/* Flip Flag */
45#define R_ENTRY_MODE_HORZ_NORMAL 0x1030
46#define R_ENTRY_MODE_HORZ_FLIPPED 0x1000
47#define R_ENTRY_MODE_VIDEO_NORMAL 0x1038
48#define R_ENTRY_MODE_VIDEO_FLIPPED 0x1018
49
50/* Reverse Flag */
51#define R_DISP_CONTROL_NORMAL 0x0004
52#define R_DISP_CONTROL_REV 0x0000
53
54void lcd_write_cmd(int16_t cmd);
55void lcd_write_reg(int reg, int value);
56void fuze_display_on(void);