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author | Rafaël Carré <rafael.carre@gmail.com> | 2009-11-01 23:35:34 +0000 |
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committer | Rafaël Carré <rafael.carre@gmail.com> | 2009-11-01 23:35:34 +0000 |
commit | f64a3fe149830e54e75a9847337b08c73e827b2a (patch) | |
tree | 84cf903a64ab4749985bceb79d1044e522447ce6 /firmware/target/arm/as3525/clock-target.h | |
parent | e28bfd1349ca813cf34d8b327e21e128a6badba1 (diff) | |
download | rockbox-f64a3fe149830e54e75a9847337b08c73e827b2a.tar.gz rockbox-f64a3fe149830e54e75a9847337b08c73e827b2a.zip |
Sansa AMS PCM: remove runtime sanity checks
Unaligned memory ops will cause a data abort anyway
Make the check for samplerate at buildtime
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23480 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/as3525/clock-target.h')
-rw-r--r-- | firmware/target/arm/as3525/clock-target.h | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/firmware/target/arm/as3525/clock-target.h b/firmware/target/arm/as3525/clock-target.h index 560e067510..81926c1884 100644 --- a/firmware/target/arm/as3525/clock-target.h +++ b/firmware/target/arm/as3525/clock-target.h | |||
@@ -132,21 +132,35 @@ | |||
132 | #if (CLK_DIV(AS3525_PLLA_FREQ, AS3525_PCLK_FREQ) - 1) >= (1<<4) /* 4 bits */ | 132 | #if (CLK_DIV(AS3525_PLLA_FREQ, AS3525_PCLK_FREQ) - 1) >= (1<<4) /* 4 bits */ |
133 | #error PCLK frequency is too low : clock divider will not fit ! | 133 | #error PCLK frequency is too low : clock divider will not fit ! |
134 | #endif | 134 | #endif |
135 | |||
135 | /* AS3525_DBOP_FREQ */ | 136 | /* AS3525_DBOP_FREQ */ |
136 | #if (CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ) - 1) >= (1<<3) /* 3 bits */ | 137 | #if (CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ) - 1) >= (1<<3) /* 3 bits */ |
137 | #error DBOP frequency is too low : clock divider will not fit ! | 138 | #error DBOP frequency is too low : clock divider will not fit ! |
138 | #endif | 139 | #endif |
140 | |||
139 | /* AS3525_IDE_FREQ */ | 141 | /* AS3525_IDE_FREQ */ |
140 | #if (CLK_DIV(AS3525_PLLA_FREQ, AS3525_IDE_FREQ) - 1) >= (1<<4) /* 4 bits */ | 142 | #if (CLK_DIV(AS3525_PLLA_FREQ, AS3525_IDE_FREQ) - 1) >= (1<<4) /* 4 bits */ |
141 | #error IDE frequency is too low : clock divider will not fit ! | 143 | #error IDE frequency is too low : clock divider will not fit ! |
142 | #endif | 144 | #endif |
145 | |||
143 | /* AS3525_I2C_FREQ */ | 146 | /* AS3525_I2C_FREQ */ |
144 | #if (CLK_DIV(AS3525_PCLK_FREQ, AS3525_I2C_FREQ)) >= (1<<10) /* 2+8 bits */ | 147 | #if (CLK_DIV(AS3525_PCLK_FREQ, AS3525_I2C_FREQ)) >= (1<<10) /* 2+8 bits */ |
145 | #error I2C frequency is too low : clock divider will not fit ! | 148 | #error I2C frequency is too low : clock divider will not fit ! |
146 | #endif | 149 | #endif |
150 | |||
147 | /* AS3525_SD_IDENT_FREQ */ | 151 | /* AS3525_SD_IDENT_FREQ */ |
148 | #if ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SD_IDENT_FREQ) / 2) - 1) >= (1<<8) /* 8 bits */ | 152 | #if ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SD_IDENT_FREQ) / 2) - 1) >= (1<<8) /* 8 bits */ |
149 | #error SD IDENTIFICATION frequency is too low : clock divider will not fit ! | 153 | #error SD IDENTIFICATION frequency is too low : clock divider will not fit ! |
150 | #endif | 154 | #endif |
151 | 155 | ||
156 | /* I2SIN / I2SOUT frequencies */ | ||
157 | /* low samplerate */ | ||
158 | #if ((AS3525_PLLA_FREQ/(128*8000))) > 512 /* 8kHz = lowest frequency */ | ||
159 | #error PLLA frequency is too low for 8kHz samplerate ! | ||
160 | #endif | ||
161 | /* high samplerate */ | ||
162 | #if ((AS3525_PLLA_FREQ/(128*96000))) < 1 /* 96kHz = highest frequency */ | ||
163 | #error PLLA frequency is too high for 96kHz samplerate ! | ||
164 | #endif | ||
165 | |||
152 | #endif /* CLOCK_TARGET_H */ | 166 | #endif /* CLOCK_TARGET_H */ |