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author | Rafaël Carré <rafael.carre@gmail.com> | 2009-11-01 23:35:34 +0000 |
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committer | Rafaël Carré <rafael.carre@gmail.com> | 2009-11-01 23:35:34 +0000 |
commit | f64a3fe149830e54e75a9847337b08c73e827b2a (patch) | |
tree | 84cf903a64ab4749985bceb79d1044e522447ce6 | |
parent | e28bfd1349ca813cf34d8b327e21e128a6badba1 (diff) | |
download | rockbox-f64a3fe149830e54e75a9847337b08c73e827b2a.tar.gz rockbox-f64a3fe149830e54e75a9847337b08c73e827b2a.zip |
Sansa AMS PCM: remove runtime sanity checks
Unaligned memory ops will cause a data abort anyway
Make the check for samplerate at buildtime
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23480 a1c6a512-1295-4272-9138-f99709370657
-rw-r--r-- | firmware/target/arm/as3525/clock-target.h | 14 | ||||
-rw-r--r-- | firmware/target/arm/as3525/pcm-as3525.c | 9 |
2 files changed, 15 insertions, 8 deletions
diff --git a/firmware/target/arm/as3525/clock-target.h b/firmware/target/arm/as3525/clock-target.h index 560e067510..81926c1884 100644 --- a/firmware/target/arm/as3525/clock-target.h +++ b/firmware/target/arm/as3525/clock-target.h | |||
@@ -132,21 +132,35 @@ | |||
132 | #if (CLK_DIV(AS3525_PLLA_FREQ, AS3525_PCLK_FREQ) - 1) >= (1<<4) /* 4 bits */ | 132 | #if (CLK_DIV(AS3525_PLLA_FREQ, AS3525_PCLK_FREQ) - 1) >= (1<<4) /* 4 bits */ |
133 | #error PCLK frequency is too low : clock divider will not fit ! | 133 | #error PCLK frequency is too low : clock divider will not fit ! |
134 | #endif | 134 | #endif |
135 | |||
135 | /* AS3525_DBOP_FREQ */ | 136 | /* AS3525_DBOP_FREQ */ |
136 | #if (CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ) - 1) >= (1<<3) /* 3 bits */ | 137 | #if (CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ) - 1) >= (1<<3) /* 3 bits */ |
137 | #error DBOP frequency is too low : clock divider will not fit ! | 138 | #error DBOP frequency is too low : clock divider will not fit ! |
138 | #endif | 139 | #endif |
140 | |||
139 | /* AS3525_IDE_FREQ */ | 141 | /* AS3525_IDE_FREQ */ |
140 | #if (CLK_DIV(AS3525_PLLA_FREQ, AS3525_IDE_FREQ) - 1) >= (1<<4) /* 4 bits */ | 142 | #if (CLK_DIV(AS3525_PLLA_FREQ, AS3525_IDE_FREQ) - 1) >= (1<<4) /* 4 bits */ |
141 | #error IDE frequency is too low : clock divider will not fit ! | 143 | #error IDE frequency is too low : clock divider will not fit ! |
142 | #endif | 144 | #endif |
145 | |||
143 | /* AS3525_I2C_FREQ */ | 146 | /* AS3525_I2C_FREQ */ |
144 | #if (CLK_DIV(AS3525_PCLK_FREQ, AS3525_I2C_FREQ)) >= (1<<10) /* 2+8 bits */ | 147 | #if (CLK_DIV(AS3525_PCLK_FREQ, AS3525_I2C_FREQ)) >= (1<<10) /* 2+8 bits */ |
145 | #error I2C frequency is too low : clock divider will not fit ! | 148 | #error I2C frequency is too low : clock divider will not fit ! |
146 | #endif | 149 | #endif |
150 | |||
147 | /* AS3525_SD_IDENT_FREQ */ | 151 | /* AS3525_SD_IDENT_FREQ */ |
148 | #if ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SD_IDENT_FREQ) / 2) - 1) >= (1<<8) /* 8 bits */ | 152 | #if ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SD_IDENT_FREQ) / 2) - 1) >= (1<<8) /* 8 bits */ |
149 | #error SD IDENTIFICATION frequency is too low : clock divider will not fit ! | 153 | #error SD IDENTIFICATION frequency is too low : clock divider will not fit ! |
150 | #endif | 154 | #endif |
151 | 155 | ||
156 | /* I2SIN / I2SOUT frequencies */ | ||
157 | /* low samplerate */ | ||
158 | #if ((AS3525_PLLA_FREQ/(128*8000))) > 512 /* 8kHz = lowest frequency */ | ||
159 | #error PLLA frequency is too low for 8kHz samplerate ! | ||
160 | #endif | ||
161 | /* high samplerate */ | ||
162 | #if ((AS3525_PLLA_FREQ/(128*96000))) < 1 /* 96kHz = highest frequency */ | ||
163 | #error PLLA frequency is too high for 96kHz samplerate ! | ||
164 | #endif | ||
165 | |||
152 | #endif /* CLOCK_TARGET_H */ | 166 | #endif /* CLOCK_TARGET_H */ |
diff --git a/firmware/target/arm/as3525/pcm-as3525.c b/firmware/target/arm/as3525/pcm-as3525.c index f648908474..26e018c82f 100644 --- a/firmware/target/arm/as3525/pcm-as3525.c +++ b/firmware/target/arm/as3525/pcm-as3525.c | |||
@@ -61,9 +61,6 @@ static void play_start_pcm(void) | |||
61 | if(size > MAX_TRANSFER) | 61 | if(size > MAX_TRANSFER) |
62 | size = MAX_TRANSFER; | 62 | size = MAX_TRANSFER; |
63 | 63 | ||
64 | if((unsigned int)dma_start_addr & 3) | ||
65 | panicf("unaligned pointer!"); | ||
66 | |||
67 | dma_size -= size; | 64 | dma_size -= size; |
68 | dma_start_addr += size; | 65 | dma_start_addr += size; |
69 | 66 | ||
@@ -148,9 +145,8 @@ void pcm_dma_apply_settings(void) | |||
148 | { | 145 | { |
149 | unsigned long frequency = pcm_sampr; | 146 | unsigned long frequency = pcm_sampr; |
150 | 147 | ||
148 | /* TODO : use a table ? */ | ||
151 | const int divider = (((AS3525_PLLA_FREQ/128) + (frequency/2)) / frequency) - 1; | 149 | const int divider = (((AS3525_PLLA_FREQ/128) + (frequency/2)) / frequency) - 1; |
152 | if(divider < 0 || divider > 511) | ||
153 | panicf("unsupported frequency %ld", frequency); | ||
154 | 150 | ||
155 | int cgu_audio = CGU_AUDIO; /* read register */ | 151 | int cgu_audio = CGU_AUDIO; /* read register */ |
156 | cgu_audio &= ~(511 << 2); /* clear i2sout divider */ | 152 | cgu_audio &= ~(511 << 2); /* clear i2sout divider */ |
@@ -266,9 +262,6 @@ void pcm_rec_dma_start(void *addr, size_t size) | |||
266 | rec_start_addr = addr; | 262 | rec_start_addr = addr; |
267 | rec_size = size; | 263 | rec_size = size; |
268 | 264 | ||
269 | if((unsigned int)addr & 3) | ||
270 | panicf("unaligned pointer!"); | ||
271 | |||
272 | CGU_PERI |= CGU_I2SIN_APB_CLOCK_ENABLE|CGU_I2SOUT_APB_CLOCK_ENABLE; | 265 | CGU_PERI |= CGU_I2SIN_APB_CLOCK_ENABLE|CGU_I2SOUT_APB_CLOCK_ENABLE; |
273 | CGU_AUDIO |= ((1<<23)|(1<<11)); | 266 | CGU_AUDIO |= ((1<<23)|(1<<11)); |
274 | 267 | ||