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author | Bertrik Sikken <bertrik@sikken.nl> | 2010-01-10 14:24:45 +0000 |
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committer | Bertrik Sikken <bertrik@sikken.nl> | 2010-01-10 14:24:45 +0000 |
commit | ba9040a82b15c18b242134474a6e1d571ed686a3 (patch) | |
tree | 244e940c6000ede86271f94406a344bfeaeb899f /firmware/target/arm/as3525/clock-target.h | |
parent | 25972b63e63fcf42b5f0d17814272385daa96c2f (diff) | |
download | rockbox-ba9040a82b15c18b242134474a6e1d571ed686a3.tar.gz rockbox-ba9040a82b15c18b242134474a6e1d571ed686a3.zip |
Sansa AMS: allow use of PLL B for more accurate audio sample rate (0.04% instead 0.15% error)
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@24211 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/as3525/clock-target.h')
-rw-r--r-- | firmware/target/arm/as3525/clock-target.h | 24 |
1 files changed, 19 insertions, 5 deletions
diff --git a/firmware/target/arm/as3525/clock-target.h b/firmware/target/arm/as3525/clock-target.h index 08c385c7cd..fd3a1c7bf4 100644 --- a/firmware/target/arm/as3525/clock-target.h +++ b/firmware/target/arm/as3525/clock-target.h | |||
@@ -52,7 +52,7 @@ | |||
52 | /* Clock Sources */ | 52 | /* Clock Sources */ |
53 | #define AS3525_CLK_MAIN 0 | 53 | #define AS3525_CLK_MAIN 0 |
54 | #define AS3525_CLK_PLLA 1 | 54 | #define AS3525_CLK_PLLA 1 |
55 | //#define AS3525_CLK_PLLB 2 | 55 | #define AS3525_CLK_PLLB 2 |
56 | #define AS3525_CLK_FCLK 3 /* Available as PCLK input only */ | 56 | #define AS3525_CLK_FCLK 3 /* Available as PCLK input only */ |
57 | 57 | ||
58 | /** ************ Change these to reconfigure clocking scheme *******************/ | 58 | /** ************ Change these to reconfigure clocking scheme *******************/ |
@@ -70,6 +70,10 @@ | |||
70 | /* *5/8 = 155MHz 77.5, 51.67, 38.75 */ | 70 | /* *5/8 = 155MHz 77.5, 51.67, 38.75 */ |
71 | #define AS3525_PLLA_SETTING 0x261F | 71 | #define AS3525_PLLA_SETTING 0x261F |
72 | 72 | ||
73 | /* PLLB frequencies and settings (audio and USB) */ | ||
74 | #define AS3525_PLLB_FREQ 384000000 /* allows 44.1kHz with 0.04% error*/ | ||
75 | #define AS3525_PLLB_SETTING 0x2630 | ||
76 | |||
73 | #endif /* SANSA_CLIPV2 */ | 77 | #endif /* SANSA_CLIPV2 */ |
74 | 78 | ||
75 | //#define AS3525_PLLA_FREQ 384000000 /*192,128,96,76.8,64,54.9,48,42.7,38.4*/ | 79 | //#define AS3525_PLLA_FREQ 384000000 /*192,128,96,76.8,64,54.9,48,42.7,38.4*/ |
@@ -107,6 +111,16 @@ | |||
107 | #define AS3525_FCLK_SEL AS3525_CLK_PLLA | 111 | #define AS3525_FCLK_SEL AS3525_CLK_PLLA |
108 | #define AS3525_FCLK_POSTDIV (CLK_DIV((AS3525_PLLA_FREQ*(8-AS3525_FCLK_PREDIV)/8), AS3525_FCLK_FREQ) - 1) /*div=1/(n+1)*/ | 112 | #define AS3525_FCLK_POSTDIV (CLK_DIV((AS3525_PLLA_FREQ*(8-AS3525_FCLK_PREDIV)/8), AS3525_FCLK_FREQ) - 1) /*div=1/(n+1)*/ |
109 | 113 | ||
114 | /* MCLK */ | ||
115 | #define AS3525_MCLK_SEL AS3525_CLK_PLLA | ||
116 | #if (AS3525_MCLK_SEL==AS3525_CLK_PLLA) | ||
117 | #define AS3525_MCLK_FREQ AS3525_PLLA_FREQ | ||
118 | #elif (AS3525_MCLK_SEL==AS3525_CLK_PLLB) | ||
119 | #define AS3525_MCLK_FREQ AS3525_PLLB_FREQ | ||
120 | #else | ||
121 | #error Choose either PLLA or PLLB for MCLK! | ||
122 | #endif | ||
123 | |||
110 | /* PCLK */ | 124 | /* PCLK */ |
111 | #ifdef ASYNCHRONOUS_BUS | 125 | #ifdef ASYNCHRONOUS_BUS |
112 | #define AS3525_PCLK_SEL AS3525_CLK_PLLA /* PLLA input for asynchronous */ | 126 | #define AS3525_PCLK_SEL AS3525_CLK_PLLA /* PLLA input for asynchronous */ |
@@ -169,12 +183,12 @@ | |||
169 | 183 | ||
170 | /* I2SIN / I2SOUT frequencies */ | 184 | /* I2SIN / I2SOUT frequencies */ |
171 | /* low samplerate */ | 185 | /* low samplerate */ |
172 | #if ((AS3525_PLLA_FREQ/(128*8000))) > 512 /* 8kHz = lowest frequency */ | 186 | #if ((AS3525_MCLK_FREQ/(128*8000))) > 512 /* 8kHz = lowest frequency */ |
173 | #error PLLA frequency is too low for 8kHz samplerate ! | 187 | #error AS3525_MCLK_FREQ is too high for 8kHz samplerate ! |
174 | #endif | 188 | #endif |
175 | /* high samplerate */ | 189 | /* high samplerate */ |
176 | #if ((AS3525_PLLA_FREQ/(128*96000))) < 1 /* 96kHz = highest frequency */ | 190 | #if ((AS3525_MCLK_FREQ/(128*96000))) < 1 /* 96kHz = highest frequency */ |
177 | #error PLLA frequency is too high for 96kHz samplerate ! | 191 | #error AS3525_MCLK_FREQ is too low for 96kHz samplerate ! |
178 | #endif | 192 | #endif |
179 | 193 | ||
180 | #endif /* CLOCK_TARGET_H */ | 194 | #endif /* CLOCK_TARGET_H */ |