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authorBertrik Sikken <bertrik@sikken.nl>2010-01-10 14:24:45 +0000
committerBertrik Sikken <bertrik@sikken.nl>2010-01-10 14:24:45 +0000
commitba9040a82b15c18b242134474a6e1d571ed686a3 (patch)
tree244e940c6000ede86271f94406a344bfeaeb899f
parent25972b63e63fcf42b5f0d17814272385daa96c2f (diff)
downloadrockbox-ba9040a82b15c18b242134474a6e1d571ed686a3.tar.gz
rockbox-ba9040a82b15c18b242134474a6e1d571ed686a3.zip
Sansa AMS: allow use of PLL B for more accurate audio sample rate (0.04% instead 0.15% error)
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@24211 a1c6a512-1295-4272-9138-f99709370657
-rw-r--r--firmware/target/arm/as3525/clock-target.h24
-rw-r--r--firmware/target/arm/as3525/pcm-as3525.c14
-rw-r--r--firmware/target/arm/as3525/system-as3525.c7
3 files changed, 34 insertions, 11 deletions
diff --git a/firmware/target/arm/as3525/clock-target.h b/firmware/target/arm/as3525/clock-target.h
index 08c385c7cd..fd3a1c7bf4 100644
--- a/firmware/target/arm/as3525/clock-target.h
+++ b/firmware/target/arm/as3525/clock-target.h
@@ -52,7 +52,7 @@
52/* Clock Sources */ 52/* Clock Sources */
53#define AS3525_CLK_MAIN 0 53#define AS3525_CLK_MAIN 0
54#define AS3525_CLK_PLLA 1 54#define AS3525_CLK_PLLA 1
55//#define AS3525_CLK_PLLB 2 55#define AS3525_CLK_PLLB 2
56#define AS3525_CLK_FCLK 3 /* Available as PCLK input only */ 56#define AS3525_CLK_FCLK 3 /* Available as PCLK input only */
57 57
58/** ************ Change these to reconfigure clocking scheme *******************/ 58/** ************ Change these to reconfigure clocking scheme *******************/
@@ -70,6 +70,10 @@
70 /* *5/8 = 155MHz 77.5, 51.67, 38.75 */ 70 /* *5/8 = 155MHz 77.5, 51.67, 38.75 */
71#define AS3525_PLLA_SETTING 0x261F 71#define AS3525_PLLA_SETTING 0x261F
72 72
73/* PLLB frequencies and settings (audio and USB) */
74#define AS3525_PLLB_FREQ 384000000 /* allows 44.1kHz with 0.04% error*/
75#define AS3525_PLLB_SETTING 0x2630
76
73#endif /* SANSA_CLIPV2 */ 77#endif /* SANSA_CLIPV2 */
74 78
75//#define AS3525_PLLA_FREQ 384000000 /*192,128,96,76.8,64,54.9,48,42.7,38.4*/ 79//#define AS3525_PLLA_FREQ 384000000 /*192,128,96,76.8,64,54.9,48,42.7,38.4*/
@@ -107,6 +111,16 @@
107#define AS3525_FCLK_SEL AS3525_CLK_PLLA 111#define AS3525_FCLK_SEL AS3525_CLK_PLLA
108#define AS3525_FCLK_POSTDIV (CLK_DIV((AS3525_PLLA_FREQ*(8-AS3525_FCLK_PREDIV)/8), AS3525_FCLK_FREQ) - 1) /*div=1/(n+1)*/ 112#define AS3525_FCLK_POSTDIV (CLK_DIV((AS3525_PLLA_FREQ*(8-AS3525_FCLK_PREDIV)/8), AS3525_FCLK_FREQ) - 1) /*div=1/(n+1)*/
109 113
114/* MCLK */
115#define AS3525_MCLK_SEL AS3525_CLK_PLLA
116#if (AS3525_MCLK_SEL==AS3525_CLK_PLLA)
117#define AS3525_MCLK_FREQ AS3525_PLLA_FREQ
118#elif (AS3525_MCLK_SEL==AS3525_CLK_PLLB)
119#define AS3525_MCLK_FREQ AS3525_PLLB_FREQ
120#else
121#error Choose either PLLA or PLLB for MCLK!
122#endif
123
110/* PCLK */ 124/* PCLK */
111#ifdef ASYNCHRONOUS_BUS 125#ifdef ASYNCHRONOUS_BUS
112#define AS3525_PCLK_SEL AS3525_CLK_PLLA /* PLLA input for asynchronous */ 126#define AS3525_PCLK_SEL AS3525_CLK_PLLA /* PLLA input for asynchronous */
@@ -169,12 +183,12 @@
169 183
170/* I2SIN / I2SOUT frequencies */ 184/* I2SIN / I2SOUT frequencies */
171/* low samplerate */ 185/* low samplerate */
172#if ((AS3525_PLLA_FREQ/(128*8000))) > 512 /* 8kHz = lowest frequency */ 186#if ((AS3525_MCLK_FREQ/(128*8000))) > 512 /* 8kHz = lowest frequency */
173#error PLLA frequency is too low for 8kHz samplerate ! 187#error AS3525_MCLK_FREQ is too high for 8kHz samplerate !
174#endif 188#endif
175/* high samplerate */ 189/* high samplerate */
176#if ((AS3525_PLLA_FREQ/(128*96000))) < 1 /* 96kHz = highest frequency */ 190#if ((AS3525_MCLK_FREQ/(128*96000))) < 1 /* 96kHz = highest frequency */
177#error PLLA frequency is too high for 96kHz samplerate ! 191#error AS3525_MCLK_FREQ is too low for 96kHz samplerate !
178#endif 192#endif
179 193
180#endif /* CLOCK_TARGET_H */ 194#endif /* CLOCK_TARGET_H */
diff --git a/firmware/target/arm/as3525/pcm-as3525.c b/firmware/target/arm/as3525/pcm-as3525.c
index 88aaaf9220..53a3f0c9a3 100644
--- a/firmware/target/arm/as3525/pcm-as3525.c
+++ b/firmware/target/arm/as3525/pcm-as3525.c
@@ -139,11 +139,13 @@ void pcm_dma_apply_settings(void)
139 unsigned long frequency = pcm_sampr; 139 unsigned long frequency = pcm_sampr;
140 140
141 /* TODO : use a table ? */ 141 /* TODO : use a table ? */
142 const int divider = (((AS3525_PLLA_FREQ/128) + (frequency/2)) / frequency) - 1; 142 const int divider = ((AS3525_MCLK_FREQ/128) + (frequency/2)) / frequency;
143 143
144 int cgu_audio = CGU_AUDIO; /* read register */ 144 int cgu_audio = CGU_AUDIO; /* read register */
145 cgu_audio &= ~(3 << 0); /* clear i2sout MCLK_SEL */
146 cgu_audio |= (AS3525_MCLK_SEL << 0); /* set i2sout MCLK_SEL */
145 cgu_audio &= ~(511 << 2); /* clear i2sout divider */ 147 cgu_audio &= ~(511 << 2); /* clear i2sout divider */
146 cgu_audio |= divider << 2; /* set new i2sout divider */ 148 cgu_audio |= (divider - 1) << 2; /* set new i2sout divider */
147 CGU_AUDIO = cgu_audio; /* write back register */ 149 CGU_AUDIO = cgu_audio; /* write back register */
148} 150}
149 151
@@ -318,13 +320,13 @@ void pcm_rec_dma_init(void)
318 unsigned long frequency = pcm_sampr; 320 unsigned long frequency = pcm_sampr;
319 321
320 /* TODO : use a table ? */ 322 /* TODO : use a table ? */
321 const int divider = (((AS3525_PLLA_FREQ/128) + (frequency/2)) / frequency) - 1; 323 const int divider = ((AS3525_MCLK_FREQ/128) + (frequency/2)) / frequency;
322 324
323 int cgu_audio = CGU_AUDIO; /* read register */ 325 int cgu_audio = CGU_AUDIO; /* read register */
324 cgu_audio &= ~(3 << 12); /* clear i2sin clocksource */ 326 cgu_audio &= ~(3 << 12); /* clear i2sin MCLK_SEL */
325 cgu_audio |= (1 << 12); /* set to PLLA */ 327 cgu_audio |= (AS3525_MCLK_SEL << 12); /* set i2sin MCLK_SEL */
326 cgu_audio &= ~(511 << 14); /* clear i2sin divider */ 328 cgu_audio &= ~(511 << 14); /* clear i2sin divider */
327 cgu_audio |= divider << 14; /* set new i2sin divider */ 329 cgu_audio |= (divider - 1) << 14; /* set new i2sin divider */
328 CGU_AUDIO = cgu_audio; /* write back register */ 330 CGU_AUDIO = cgu_audio; /* write back register */
329} 331}
330 332
diff --git a/firmware/target/arm/as3525/system-as3525.c b/firmware/target/arm/as3525/system-as3525.c
index 75539ba8d7..13b406a6b8 100644
--- a/firmware/target/arm/as3525/system-as3525.c
+++ b/firmware/target/arm/as3525/system-as3525.c
@@ -285,8 +285,15 @@ void system_init(void)
285 CGU_PROC = 0; /* fclk 24 MHz */ 285 CGU_PROC = 0; /* fclk 24 MHz */
286 CGU_PERI &= ~0x7f; /* pclk 24 MHz */ 286 CGU_PERI &= ~0x7f; /* pclk 24 MHz */
287 287
288 CGU_PLLASUP = 0; /* enable PLLA */
288 CGU_PLLA = AS3525_PLLA_SETTING; 289 CGU_PLLA = AS3525_PLLA_SETTING;
289 while(!(CGU_INTCTRL & (1<<0))); /* wait until PLLA is locked */ 290 while(!(CGU_INTCTRL & (1<<0))); /* wait until PLLA is locked */
291
292#if (AS3525_MCLK_SEL == AS3525_CLK_PLLB)
293 CGU_PLLBSUP = 0; /* enable PLLB */
294 CGU_PLLB = AS3525_PLLB_SETTING;
295 while(!(CGU_INTCTRL & (1<<1))); /* wait until PLLB is locked */
296#endif
290 297
291 /* Set FCLK frequency */ 298 /* Set FCLK frequency */
292 CGU_PROC = ((AS3525_FCLK_POSTDIV << 4) | 299 CGU_PROC = ((AS3525_FCLK_POSTDIV << 4) |