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author | Rafaël Carré <rafael.carre@gmail.com> | 2010-02-08 03:36:53 +0000 |
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committer | Rafaël Carré <rafael.carre@gmail.com> | 2010-02-08 03:36:53 +0000 |
commit | 71e77aaff8cbfcb95205171d413d572a14304f94 (patch) | |
tree | 29e30fd33f074937aa19a10a325a63e3c25e9c38 /firmware/target/arm/as3525/clock-target.h | |
parent | fbc59e2e2859d7e1d93b3416dad5199cb9def536 (diff) | |
download | rockbox-71e77aaff8cbfcb95205171d413d572a14304f94.tar.gz rockbox-71e77aaff8cbfcb95205171d413d572a14304f94.zip |
Sansa Clip+: use correct SSP settings
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@24559 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/as3525/clock-target.h')
-rw-r--r-- | firmware/target/arm/as3525/clock-target.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/firmware/target/arm/as3525/clock-target.h b/firmware/target/arm/as3525/clock-target.h index 2c3632c8be..9f436f742a 100644 --- a/firmware/target/arm/as3525/clock-target.h +++ b/firmware/target/arm/as3525/clock-target.h | |||
@@ -141,6 +141,8 @@ | |||
141 | #define AS3525_I2C_FREQ 400000 | 141 | #define AS3525_I2C_FREQ 400000 |
142 | #define AS3525_SD_IDENT_DIV ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SD_IDENT_FREQ) / 2) - 1) | 142 | #define AS3525_SD_IDENT_DIV ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SD_IDENT_FREQ) / 2) - 1) |
143 | #define AS3525_SD_IDENT_FREQ 400000 /* must be between 100 & 400 kHz */ | 143 | #define AS3525_SD_IDENT_FREQ 400000 /* must be between 100 & 400 kHz */ |
144 | #define AS3525_SSP_PRESCALER ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SSP_FREQ) + 1) & ~1) /* must be an even number */ | ||
145 | #define AS3525_SSP_FREQ 12000000 | ||
144 | 146 | ||
145 | #define AS3525_IDE_SEL AS3525_CLK_PLLA /* Input Source */ | 147 | #define AS3525_IDE_SEL AS3525_CLK_PLLA /* Input Source */ |
146 | #define AS3525_IDE_DIV (CLK_DIV(AS3525_PLLA_FREQ, AS3525_IDE_FREQ) - 1)/*div=1/(n+1)*/ | 148 | #define AS3525_IDE_DIV (CLK_DIV(AS3525_PLLA_FREQ, AS3525_IDE_FREQ) - 1)/*div=1/(n+1)*/ |
@@ -179,6 +181,11 @@ | |||
179 | #error I2C frequency is too low : clock divider will not fit ! | 181 | #error I2C frequency is too low : clock divider will not fit ! |
180 | #endif | 182 | #endif |
181 | 183 | ||
184 | /* AS3525_SSP_FREQ */ | ||
185 | #if (((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SSP_FREQ)) + 1 ) & ~1) >= (1<<8) /* 8 bits */ | ||
186 | #error SSP frequency is too low : clock divider will not fit ! | ||
187 | #endif | ||
188 | |||
182 | /* AS3525_SD_IDENT_FREQ */ | 189 | /* AS3525_SD_IDENT_FREQ */ |
183 | #if ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SD_IDENT_FREQ) / 2) - 1) >= (1<<8) /* 8 bits */ | 190 | #if ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SD_IDENT_FREQ) / 2) - 1) >= (1<<8) /* 8 bits */ |
184 | #error SD IDENTIFICATION frequency is too low : clock divider will not fit ! | 191 | #error SD IDENTIFICATION frequency is too low : clock divider will not fit ! |