From 71e77aaff8cbfcb95205171d413d572a14304f94 Mon Sep 17 00:00:00 2001 From: Rafaël Carré Date: Mon, 8 Feb 2010 03:36:53 +0000 Subject: Sansa Clip+: use correct SSP settings git-svn-id: svn://svn.rockbox.org/rockbox/trunk@24559 a1c6a512-1295-4272-9138-f99709370657 --- firmware/target/arm/as3525/clock-target.h | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'firmware/target/arm/as3525/clock-target.h') diff --git a/firmware/target/arm/as3525/clock-target.h b/firmware/target/arm/as3525/clock-target.h index 2c3632c8be..9f436f742a 100644 --- a/firmware/target/arm/as3525/clock-target.h +++ b/firmware/target/arm/as3525/clock-target.h @@ -141,6 +141,8 @@ #define AS3525_I2C_FREQ 400000 #define AS3525_SD_IDENT_DIV ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SD_IDENT_FREQ) / 2) - 1) #define AS3525_SD_IDENT_FREQ 400000 /* must be between 100 & 400 kHz */ + #define AS3525_SSP_PRESCALER ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SSP_FREQ) + 1) & ~1) /* must be an even number */ + #define AS3525_SSP_FREQ 12000000 #define AS3525_IDE_SEL AS3525_CLK_PLLA /* Input Source */ #define AS3525_IDE_DIV (CLK_DIV(AS3525_PLLA_FREQ, AS3525_IDE_FREQ) - 1)/*div=1/(n+1)*/ @@ -179,6 +181,11 @@ #error I2C frequency is too low : clock divider will not fit ! #endif +/* AS3525_SSP_FREQ */ +#if (((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SSP_FREQ)) + 1 ) & ~1) >= (1<<8) /* 8 bits */ +#error SSP frequency is too low : clock divider will not fit ! +#endif + /* AS3525_SD_IDENT_FREQ */ #if ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SD_IDENT_FREQ) / 2) - 1) >= (1<<8) /* 8 bits */ #error SD IDENTIFICATION frequency is too low : clock divider will not fit ! -- cgit v1.2.3