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author | Rafaël Carré <rafael.carre@gmail.com> | 2008-12-04 20:04:31 +0000 |
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committer | Rafaël Carré <rafael.carre@gmail.com> | 2008-12-04 20:04:31 +0000 |
commit | 45711ac2869f955c40be96d8dcbc7201c718dba4 (patch) | |
tree | ef022bec4b6e8bcc11005de34d300e073c60770d /firmware/target/arm/as3525/ata_sd_as3525.c | |
parent | 7ea9e31658da4fce9c4a3e30838b82fda8eda287 (diff) | |
download | rockbox-45711ac2869f955c40be96d8dcbc7201c718dba4.tar.gz rockbox-45711ac2869f955c40be96d8dcbc7201c718dba4.zip |
Sansa AMS: centralize clock settings in clock-target.h
Reorder system_init() to initialize peripherals not only in bootloader
Use a 65MHz PCLK (and memclk) which will be needed for realtime decoding
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@19330 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/as3525/ata_sd_as3525.c')
-rw-r--r-- | firmware/target/arm/as3525/ata_sd_as3525.c | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/firmware/target/arm/as3525/ata_sd_as3525.c b/firmware/target/arm/as3525/ata_sd_as3525.c index cb1666c029..b2d8e3c1f3 100644 --- a/firmware/target/arm/as3525/ata_sd_as3525.c +++ b/firmware/target/arm/as3525/ata_sd_as3525.c | |||
@@ -35,6 +35,7 @@ | |||
35 | #include "pl180.h" /* SD controller */ | 35 | #include "pl180.h" /* SD controller */ |
36 | #include "pl081.h" /* DMA controller */ | 36 | #include "pl081.h" /* DMA controller */ |
37 | #include "dma-target.h" /* DMA request lines */ | 37 | #include "dma-target.h" /* DMA request lines */ |
38 | #include "clock-target.h" | ||
38 | #include "panic.h" | 39 | #include "panic.h" |
39 | #include "stdbool.h" | 40 | #include "stdbool.h" |
40 | #include "ata_idle_notify.h" | 41 | #include "ata_idle_notify.h" |
@@ -375,7 +376,9 @@ static void init_pl180_controller(const int drive) | |||
375 | MCI_CLOCK(drive) &= ~MCI_CLOCK_POWERSAVE; | 376 | MCI_CLOCK(drive) &= ~MCI_CLOCK_POWERSAVE; |
376 | 377 | ||
377 | /* set MCLK divider */ | 378 | /* set MCLK divider */ |
378 | mci_set_clock_divider(drive, 200); | 379 | mci_set_clock_divider(drive, |
380 | CLK_DIV(AS3525_PCLK_FREQ, AS3525_SD_IDENT_FREQ)); | ||
381 | |||
379 | } | 382 | } |
380 | 383 | ||
381 | int sd_init(void) | 384 | int sd_init(void) |
@@ -384,7 +387,7 @@ int sd_init(void) | |||
384 | 387 | ||
385 | CGU_IDE = (1<<7) /* AHB interface enable */ | | 388 | CGU_IDE = (1<<7) /* AHB interface enable */ | |
386 | (1<<6) /* interface enable */ | | 389 | (1<<6) /* interface enable */ | |
387 | (2<<2) /* clock didiver = 2+1 */ | | 390 | ((CLK_DIV(AS3525_PLLA_FREQ, AS3525_IDE_FREQ) - 1) << 2) | |
388 | 1 /* clock source = PLLA */; | 391 | 1 /* clock source = PLLA */; |
389 | 392 | ||
390 | CGU_PERI |= CGU_NAF_CLOCK_ENABLE; | 393 | CGU_PERI |= CGU_NAF_CLOCK_ENABLE; |