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authorMichael Sevakis <jethead71@rockbox.org>2008-06-03 05:08:24 +0000
committerMichael Sevakis <jethead71@rockbox.org>2008-06-03 05:08:24 +0000
commit191320cd0f39a1dd831273f6ad57602d1b2e6cf9 (patch)
treeceedf028763a7855bf1b2caeb11765e7c6dd79af /firmware/rolo.c
parent606d9d0c83f8396fa418fa16a23da68aa2e4d784 (diff)
downloadrockbox-191320cd0f39a1dd831273f6ad57602d1b2e6cf9.tar.gz
rockbox-191320cd0f39a1dd831273f6ad57602d1b2e6cf9.zip
Rename CPU/COP_INT_CLR to CPU/COP_INT_DIS since it's really a 'write one to disable' register and hasn't anything to do with acknowledging interrupts-- that's handled at the module level.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@17683 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/rolo.c')
-rw-r--r--firmware/rolo.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/firmware/rolo.c b/firmware/rolo.c
index 06ae9e1380..6bb0bb13a1 100644
--- a/firmware/rolo.c
+++ b/firmware/rolo.c
@@ -142,7 +142,7 @@ void rolo_restart(const unsigned char* source, unsigned char* dest,
142 : : "a"(dest) 142 : : "a"(dest)
143 ); 143 );
144#elif defined(CPU_PP502x) 144#elif defined(CPU_PP502x)
145 CPU_INT_CLR = -1; 145 CPU_INT_DIS = -1;
146 146
147 /* Flush cache */ 147 /* Flush cache */
148 flush_icache(); 148 flush_icache();