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-rw-r--r--firmware/export/pp5002.h4
-rw-r--r--firmware/export/pp5020.h4
-rw-r--r--firmware/rolo.c2
-rw-r--r--firmware/target/arm/ipod/button-1g-3g.c2
-rw-r--r--firmware/target/arm/olympus/mrobe-100/power-mr100.c4
-rw-r--r--firmware/target/arm/philips/sa9200/power-sa9200.c4
-rw-r--r--firmware/target/arm/sandisk/power-c200_e200.c4
-rw-r--r--firmware/target/arm/system-pp5002.c4
-rw-r--r--firmware/target/arm/system-pp502x.c8
-rw-r--r--firmware/target/arm/usb-drv-arc.c2
-rw-r--r--firmware/timer.c8
11 files changed, 23 insertions, 23 deletions
diff --git a/firmware/export/pp5002.h b/firmware/export/pp5002.h
index bbd7003c63..03bab42fb5 100644
--- a/firmware/export/pp5002.h
+++ b/firmware/export/pp5002.h
@@ -105,12 +105,12 @@
105 105
106#define CPU_INT_EN_STAT (*(volatile unsigned long *)(0xcf001020)) 106#define CPU_INT_EN_STAT (*(volatile unsigned long *)(0xcf001020))
107#define CPU_INT_EN (*(volatile unsigned long *)(0xcf001024)) 107#define CPU_INT_EN (*(volatile unsigned long *)(0xcf001024))
108#define CPU_INT_CLR (*(volatile unsigned long *)(0xcf001028)) 108#define CPU_INT_DIS (*(volatile unsigned long *)(0xcf001028))
109#define CPU_INT_PRIORITY (*(volatile unsigned long *)(0xcf00102c)) 109#define CPU_INT_PRIORITY (*(volatile unsigned long *)(0xcf00102c))
110 110
111#define COP_INT_EN_STAT (*(volatile unsigned long *)(0xcf001030)) 111#define COP_INT_EN_STAT (*(volatile unsigned long *)(0xcf001030))
112#define COP_INT_EN (*(volatile unsigned long *)(0xcf001034)) 112#define COP_INT_EN (*(volatile unsigned long *)(0xcf001034))
113#define COP_INT_CLR (*(volatile unsigned long *)(0xcf001038)) 113#define COP_INT_DIS (*(volatile unsigned long *)(0xcf001038))
114#define COP_INT_PRIORITY (*(volatile unsigned long *)(0xcf00103c)) 114#define COP_INT_PRIORITY (*(volatile unsigned long *)(0xcf00103c))
115 115
116#define IDE_IRQ 1 116#define IDE_IRQ 1
diff --git a/firmware/export/pp5020.h b/firmware/export/pp5020.h
index 52acb2f21b..caae5a7e00 100644
--- a/firmware/export/pp5020.h
+++ b/firmware/export/pp5020.h
@@ -62,12 +62,12 @@
62 62
63#define CPU_INT_EN_STAT (*(volatile unsigned long*)(0x60004020)) 63#define CPU_INT_EN_STAT (*(volatile unsigned long*)(0x60004020))
64#define CPU_INT_EN (*(volatile unsigned long*)(0x60004024)) 64#define CPU_INT_EN (*(volatile unsigned long*)(0x60004024))
65#define CPU_INT_CLR (*(volatile unsigned long*)(0x60004028)) 65#define CPU_INT_DIS (*(volatile unsigned long*)(0x60004028))
66#define CPU_INT_PRIORITY (*(volatile unsigned long*)(0x6000402c)) 66#define CPU_INT_PRIORITY (*(volatile unsigned long*)(0x6000402c))
67 67
68#define COP_INT_EN_STAT (*(volatile unsigned long*)(0x60004030)) 68#define COP_INT_EN_STAT (*(volatile unsigned long*)(0x60004030))
69#define COP_INT_EN (*(volatile unsigned long*)(0x60004034)) 69#define COP_INT_EN (*(volatile unsigned long*)(0x60004034))
70#define COP_INT_CLR (*(volatile unsigned long*)(0x60004038)) 70#define COP_INT_DIS (*(volatile unsigned long*)(0x60004038))
71#define COP_INT_PRIORITY (*(volatile unsigned long*)(0x6000403c)) 71#define COP_INT_PRIORITY (*(volatile unsigned long*)(0x6000403c))
72 72
73#define CPU_HI_INT_STAT (*(volatile unsigned long*)(0x60004100)) 73#define CPU_HI_INT_STAT (*(volatile unsigned long*)(0x60004100))
diff --git a/firmware/rolo.c b/firmware/rolo.c
index 06ae9e1380..6bb0bb13a1 100644
--- a/firmware/rolo.c
+++ b/firmware/rolo.c
@@ -142,7 +142,7 @@ void rolo_restart(const unsigned char* source, unsigned char* dest,
142 : : "a"(dest) 142 : : "a"(dest)
143 ); 143 );
144#elif defined(CPU_PP502x) 144#elif defined(CPU_PP502x)
145 CPU_INT_CLR = -1; 145 CPU_INT_DIS = -1;
146 146
147 /* Flush cache */ 147 /* Flush cache */
148 flush_icache(); 148 flush_icache();
diff --git a/firmware/target/arm/ipod/button-1g-3g.c b/firmware/target/arm/ipod/button-1g-3g.c
index c91051e78b..c869f6f271 100644
--- a/firmware/target/arm/ipod/button-1g-3g.c
+++ b/firmware/target/arm/ipod/button-1g-3g.c
@@ -167,7 +167,7 @@ static int ipod_3g_button_read(void)
167 167
168void ipod_3g_button_int(void) 168void ipod_3g_button_int(void)
169{ 169{
170 CPU_INT_CLR = GPIO_MASK; 170 CPU_INT_DIS = GPIO_MASK;
171 int_btn = ipod_3g_button_read(); 171 int_btn = ipod_3g_button_read();
172 CPU_INT_EN = GPIO_MASK; 172 CPU_INT_EN = GPIO_MASK;
173} 173}
diff --git a/firmware/target/arm/olympus/mrobe-100/power-mr100.c b/firmware/target/arm/olympus/mrobe-100/power-mr100.c
index c6f7d65844..dff8bb97f2 100644
--- a/firmware/target/arm/olympus/mrobe-100/power-mr100.c
+++ b/firmware/target/arm/olympus/mrobe-100/power-mr100.c
@@ -63,8 +63,8 @@ void power_off(void)
63 disable_interrupt(IRQ_FIQ_STATUS); 63 disable_interrupt(IRQ_FIQ_STATUS);
64 64
65 /* Mask them on both cores */ 65 /* Mask them on both cores */
66 CPU_INT_CLR = -1; 66 CPU_INT_DIS = -1;
67 COP_INT_CLR = -1; 67 COP_INT_DIS = -1;
68 68
69 while (1) 69 while (1)
70 GPIOB_OUTPUT_VAL |= 0x80; 70 GPIOB_OUTPUT_VAL |= 0x80;
diff --git a/firmware/target/arm/philips/sa9200/power-sa9200.c b/firmware/target/arm/philips/sa9200/power-sa9200.c
index 8c8214a7ce..ddb782e107 100644
--- a/firmware/target/arm/philips/sa9200/power-sa9200.c
+++ b/firmware/target/arm/philips/sa9200/power-sa9200.c
@@ -40,8 +40,8 @@ void power_off(void)
40 40
41 /* Stop interrupts on both cores */ 41 /* Stop interrupts on both cores */
42 disable_interrupt(IRQ_FIQ_STATUS); 42 disable_interrupt(IRQ_FIQ_STATUS);
43 COP_INT_CLR = -1; 43 COP_INT_DIS = -1;
44 CPU_INT_CLR = -1; 44 CPU_INT_DIS = -1;
45 45
46 /* Halt everything and wait for device to power off */ 46 /* Halt everything and wait for device to power off */
47 while (1) 47 while (1)
diff --git a/firmware/target/arm/sandisk/power-c200_e200.c b/firmware/target/arm/sandisk/power-c200_e200.c
index 8c8214a7ce..ddb782e107 100644
--- a/firmware/target/arm/sandisk/power-c200_e200.c
+++ b/firmware/target/arm/sandisk/power-c200_e200.c
@@ -40,8 +40,8 @@ void power_off(void)
40 40
41 /* Stop interrupts on both cores */ 41 /* Stop interrupts on both cores */
42 disable_interrupt(IRQ_FIQ_STATUS); 42 disable_interrupt(IRQ_FIQ_STATUS);
43 COP_INT_CLR = -1; 43 COP_INT_DIS = -1;
44 CPU_INT_CLR = -1; 44 CPU_INT_DIS = -1;
45 45
46 /* Halt everything and wait for device to power off */ 46 /* Halt everything and wait for device to power off */
47 while (1) 47 while (1)
diff --git a/firmware/target/arm/system-pp5002.c b/firmware/target/arm/system-pp5002.c
index 164913f0f6..e4d3913651 100644
--- a/firmware/target/arm/system-pp5002.c
+++ b/firmware/target/arm/system-pp5002.c
@@ -177,8 +177,8 @@ void system_init(void)
177#endif 177#endif
178 178
179 INT_FORCED_CLR = -1; 179 INT_FORCED_CLR = -1;
180 CPU_INT_CLR = -1; 180 CPU_INT_DIS = -1;
181 COP_INT_CLR = -1; 181 COP_INT_DIS = -1;
182 182
183 GPIOA_INT_EN = 0; 183 GPIOA_INT_EN = 0;
184 GPIOB_INT_EN = 0; 184 GPIOB_INT_EN = 0;
diff --git a/firmware/target/arm/system-pp502x.c b/firmware/target/arm/system-pp502x.c
index f74b0484ab..fb292b5edf 100644
--- a/firmware/target/arm/system-pp502x.c
+++ b/firmware/target/arm/system-pp502x.c
@@ -384,12 +384,12 @@ void system_init(void)
384#endif 384#endif
385 385
386 /* disable all irqs */ 386 /* disable all irqs */
387 COP_HI_INT_CLR = -1; 387 COP_HI_INT_DIS = -1;
388 CPU_HI_INT_CLR = -1; 388 CPU_HI_INT_DIS = -1;
389 HI_INT_FORCED_CLR = -1; 389 HI_INT_FORCED_CLR = -1;
390 390
391 COP_INT_CLR = -1; 391 COP_INT_DIS = -1;
392 CPU_INT_CLR = -1; 392 CPU_INT_DIS = -1;
393 INT_FORCED_CLR = -1; 393 INT_FORCED_CLR = -1;
394 394
395 GPIOA_INT_EN = 0; 395 GPIOA_INT_EN = 0;
diff --git a/firmware/target/arm/usb-drv-arc.c b/firmware/target/arm/usb-drv-arc.c
index f785535100..31a6acb71b 100644
--- a/firmware/target/arm/usb-drv-arc.c
+++ b/firmware/target/arm/usb-drv-arc.c
@@ -475,7 +475,7 @@ void usb_drv_exit(void)
475#if CONFIG_CPU == IMX31L 475#if CONFIG_CPU == IMX31L
476 avic_disable_int(USB_OTG); 476 avic_disable_int(USB_OTG);
477#else 477#else
478 CPU_INT_CLR = USB_MASK; 478 CPU_INT_DIS = USB_MASK;
479#endif 479#endif
480 480
481 cancel_cpu_boost(); 481 cancel_cpu_boost();
diff --git a/firmware/timer.c b/firmware/timer.c
index bd9050f872..eefebb38f8 100644
--- a/firmware/timer.c
+++ b/firmware/timer.c
@@ -201,8 +201,8 @@ static bool timer_set(long cycles, bool start)
201 pfn_unregister(); 201 pfn_unregister();
202 pfn_unregister = NULL; 202 pfn_unregister = NULL;
203 } 203 }
204 CPU_INT_CLR = TIMER2_MASK; 204 CPU_INT_DIS = TIMER2_MASK;
205 COP_INT_CLR = TIMER2_MASK; 205 COP_INT_DIS = TIMER2_MASK;
206 } 206 }
207 if (start || (cycles_new == -1)) /* within isr, cycles_new is "locked" */ 207 if (start || (cycles_new == -1)) /* within isr, cycles_new is "locked" */
208 TIMER2_CFG = 0xc0000000 | (cycles - 1); /* enable timer */ 208 TIMER2_CFG = 0xc0000000 | (cycles - 1); /* enable timer */
@@ -311,8 +311,8 @@ void timer_unregister(void)
311 or_l((1<<10), &IMR); /* disable interrupt */ 311 or_l((1<<10), &IMR); /* disable interrupt */
312#elif defined(CPU_PP) 312#elif defined(CPU_PP)
313 TIMER2_CFG = 0; /* stop timer 2 */ 313 TIMER2_CFG = 0; /* stop timer 2 */
314 CPU_INT_CLR = TIMER2_MASK; 314 CPU_INT_DIS = TIMER2_MASK;
315 COP_INT_CLR = TIMER2_MASK; 315 COP_INT_DIS = TIMER2_MASK;
316#elif CONFIG_CPU == PNX0101 316#elif CONFIG_CPU == PNX0101
317 TIMER1.ctrl &= ~0x80; /* disable timer 1 */ 317 TIMER1.ctrl &= ~0x80; /* disable timer 1 */
318 irq_disable_int(IRQ_TIMER1); 318 irq_disable_int(IRQ_TIMER1);