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author | Rafaël Carré <rafael.carre@gmail.com> | 2008-10-28 11:24:29 +0000 |
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committer | Rafaël Carré <rafael.carre@gmail.com> | 2008-10-28 11:24:29 +0000 |
commit | b3ee07c22e1886c4cb1557dbaa4fd65d25cd1be3 (patch) | |
tree | 666598d06ac756ba58dedab7c53ea4bd667e0b0d /firmware/export | |
parent | a5a2f12f0a07df1f58732e1d6cb08a5d730fc79c (diff) | |
download | rockbox-b3ee07c22e1886c4cb1557dbaa4fd65d25cd1be3.tar.gz rockbox-b3ee07c22e1886c4cb1557dbaa4fd65d25cd1be3.zip |
Sansav2 : initializes SDRAM
The AS3525 SoC ships with an ARM PL172 MPMC controller
Also correct the memory sizes in tools/configure
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@18899 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/export')
-rw-r--r-- | firmware/export/as3525.h | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/firmware/export/as3525.h b/firmware/export/as3525.h index 2453c33ec0..91d0155234 100644 --- a/firmware/export/as3525.h +++ b/firmware/export/as3525.h | |||
@@ -312,4 +312,39 @@ interface */ | |||
312 | #define GPIOD_AFSEL (*(volatile unsigned char*)(GPIOD_BASE+0x420)) | 312 | #define GPIOD_AFSEL (*(volatile unsigned char*)(GPIOD_BASE+0x420)) |
313 | #define GPIOD_PIN(a) (*(volatile unsigned char*)(GPIOD_BASE+4*(1<<(a)))) | 313 | #define GPIOD_PIN(a) (*(volatile unsigned char*)(GPIOD_BASE+4*(1<<(a)))) |
314 | 314 | ||
315 | /* ARM PL172 Memory Controller registers */ | ||
316 | |||
317 | #define MPMC_CONTROL (*(volatile unsigned long*)(MPMC_BASE+0x000)) | ||
318 | #define MPMC_STATUS (*(volatile unsigned long*)(MPMC_BASE+0x004)) | ||
319 | #define MPMC_CONFIG (*(volatile unsigned long*)(MPMC_BASE+0x008)) | ||
320 | |||
321 | #define MPMC_DYNAMIC_CONTROL (*(volatile unsigned long*)(MPMC_BASE+0x020)) | ||
322 | #define MPMC_DYNAMIC_REFRESH (*(volatile unsigned long*)(MPMC_BASE+0x024)) | ||
323 | #define MPMC_DYNAMIC_READ_CONFIG (*(volatile unsigned long*)(MPMC_BASE+0x028)) | ||
324 | #define MPMC_DYNAMIC_tRP (*(volatile unsigned long*)(MPMC_BASE+0x030)) | ||
325 | #define MPMC_DYNAMIC_tRAS (*(volatile unsigned long*)(MPMC_BASE+0x034)) | ||
326 | #define MPMC_DYNAMIC_tSREX (*(volatile unsigned long*)(MPMC_BASE+0x038)) | ||
327 | #define MPMC_DYNAMIC_tAPR (*(volatile unsigned long*)(MPMC_BASE+0x03C)) | ||
328 | #define MPMC_DYNAMIC_tDAL (*(volatile unsigned long*)(MPMC_BASE+0x040)) | ||
329 | #define MPMC_DYNAMIC_tWR (*(volatile unsigned long*)(MPMC_BASE+0x044)) | ||
330 | #define MPMC_DYNAMIC_tRC (*(volatile unsigned long*)(MPMC_BASE+0x048)) | ||
331 | #define MPMC_DYNAMIC_tRFC (*(volatile unsigned long*)(MPMC_BASE+0x04C)) | ||
332 | #define MPMC_DYNAMIC_tXSR (*(volatile unsigned long*)(MPMC_BASE+0x050)) | ||
333 | #define MPMC_DYNAMIC_tRRD (*(volatile unsigned long*)(MPMC_BASE+0x054)) | ||
334 | #define MPMC_DYNAMIC_tMRD (*(volatile unsigned long*)(MPMC_BASE+0x058)) | ||
335 | |||
336 | #define MPMC_STATIC_EXTENDED_WAIT (*(volatile unsigned long*)(MPMC_BASE+0x080)) | ||
337 | |||
338 | #define MPMC_DYNAMIC_CONFIG_0 (*(volatile unsigned long*)(MPMC_BASE+0x100)) | ||
339 | #define MPMC_DYNAMIC_CONFIG_1 (*(volatile unsigned long*)(MPMC_BASE+0x120)) | ||
340 | #define MPMC_DYNAMIC_CONFIG_2 (*(volatile unsigned long*)(MPMC_BASE+0x140)) | ||
341 | #define MPMC_DYNAMIC_CONFIG_3 (*(volatile unsigned long*)(MPMC_BASE+0x160)) | ||
342 | |||
343 | #define MPMC_DYNAMIC_RASCAS_0 (*(volatile unsigned long*)(MPMC_BASE+0x104)) | ||
344 | #define MPMC_DYNAMIC_RASCAS_1 (*(volatile unsigned long*)(MPMC_BASE+0x124)) | ||
345 | #define MPMC_DYNAMIC_RASCAS_2 (*(volatile unsigned long*)(MPMC_BASE+0x144)) | ||
346 | #define MPMC_DYNAMIC_RASCAS_3 (*(volatile unsigned long*)(MPMC_BASE+0x164)) | ||
347 | |||
348 | #define MPMC_PERIPH_ID2 (*(volatile unsigned long*)(MPMC_BASE+0xFE8)) | ||
349 | |||
315 | #endif /*__AS3525_H__*/ | 350 | #endif /*__AS3525_H__*/ |