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| author | Jens Arnold <amiconn@rockbox.org> | 2007-07-31 10:56:50 +0000 |
|---|---|---|
| committer | Jens Arnold <amiconn@rockbox.org> | 2007-07-31 10:56:50 +0000 |
| commit | 1bc3b7feb2b0fc1014c41203ab82047ec94f69d4 (patch) | |
| tree | 2148dcd33c48b8da7f6d2619453af4367a6509dc /firmware/export | |
| parent | 1dc5435f8ebe067fcd88dea72ba65ea9c186a6a6 (diff) | |
| download | rockbox-1bc3b7feb2b0fc1014c41203ab82047ec94f69d4.tar.gz rockbox-1bc3b7feb2b0fc1014c41203ab82047ec94f69d4.zip | |
PP5002: Clock setup cleanup. * Switch to 80MHz when boosted like on the other PP targets. * Prepare sleep mode by adding CPUFREQ_SLEEP. This is already confirmed working, but a lot of functions in rockbox will probably hang because the microsecond timer isn't running in this mode.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@14096 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/export')
| -rw-r--r-- | firmware/export/pp5002.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/firmware/export/pp5002.h b/firmware/export/pp5002.h index f2a7630ef6..082fc1c9cc 100644 --- a/firmware/export/pp5002.h +++ b/firmware/export/pp5002.h | |||
| @@ -130,6 +130,7 @@ | |||
| 130 | #define PLL_CONTROL (*(volatile unsigned long *)(0xcf005010)) | 130 | #define PLL_CONTROL (*(volatile unsigned long *)(0xcf005010)) |
| 131 | #define PLL_DIV (*(volatile unsigned long *)(0xcf005018)) | 131 | #define PLL_DIV (*(volatile unsigned long *)(0xcf005018)) |
| 132 | #define PLL_MULT (*(volatile unsigned long *)(0xcf00501c)) | 132 | #define PLL_MULT (*(volatile unsigned long *)(0xcf00501c)) |
| 133 | #define PLL_UNLOCK (*(volatile unsigned long *)(0xcf005038)) | ||
| 133 | 134 | ||
| 134 | #define MMAP0_LOGICAL (*(volatile unsigned long *)(0xf000f000)) | 135 | #define MMAP0_LOGICAL (*(volatile unsigned long *)(0xf000f000)) |
| 135 | #define MMAP0_PHYSICAL (*(volatile unsigned long *)(0xf000f004)) | 136 | #define MMAP0_PHYSICAL (*(volatile unsigned long *)(0xf000f004)) |