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author | Michael Sevakis <jethead71@rockbox.org> | 2009-01-22 22:05:04 +0000 |
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committer | Michael Sevakis <jethead71@rockbox.org> | 2009-01-22 22:05:04 +0000 |
commit | da76a3469437261bd8857c6eddeaafcc601f373e (patch) | |
tree | 33e6c461aeb03d28575166c5ed5002aaf8ea9741 /firmware/export/pp5020.h | |
parent | 81df953da55e75632b5efbe676f2b348e11b2c4b (diff) | |
download | rockbox-da76a3469437261bd8857c6eddeaafcc601f373e.tar.gz rockbox-da76a3469437261bd8857c6eddeaafcc601f373e.zip |
Use bus reset detection for all ARC OTG devices. Remove conflict from LV24020LP driver with some GPIO-by-number macros for PP502x. Start monitoring for USB stack once all core threads and queues are created otherwise queues will likely be registered after USB acks. Putting PP502x system_reboot in IRAM (unmapped, uncached) memory seems to help it work more consistently. Hopefully I got all the PP USB connect handlers in the right spot in irq_handler. If device seems unresponsive to cable, check there first.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@19819 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/export/pp5020.h')
-rw-r--r-- | firmware/export/pp5020.h | 36 |
1 files changed, 34 insertions, 2 deletions
diff --git a/firmware/export/pp5020.h b/firmware/export/pp5020.h index 0f622a907d..36c88e00df 100644 --- a/firmware/export/pp5020.h +++ b/firmware/export/pp5020.h | |||
@@ -218,6 +218,7 @@ | |||
218 | #define CACHE_OP_INVALIDATE 0x0004 | 218 | #define CACHE_OP_INVALIDATE 0x0004 |
219 | 219 | ||
220 | /* GPIO Ports */ | 220 | /* GPIO Ports */ |
221 | #define GPIO_BASE_ADDR 0x6000d000 | ||
221 | #define GPIOA_ENABLE (*(volatile unsigned long *)(0x6000d000)) | 222 | #define GPIOA_ENABLE (*(volatile unsigned long *)(0x6000d000)) |
222 | #define GPIOB_ENABLE (*(volatile unsigned long *)(0x6000d004)) | 223 | #define GPIOB_ENABLE (*(volatile unsigned long *)(0x6000d004)) |
223 | #define GPIOC_ENABLE (*(volatile unsigned long *)(0x6000d008)) | 224 | #define GPIOC_ENABLE (*(volatile unsigned long *)(0x6000d008)) |
@@ -322,10 +323,41 @@ | |||
322 | * define the value of those bits. */ | 323 | * define the value of those bits. */ |
323 | 324 | ||
324 | #define GPIO_SET_BITWISE(port, mask) \ | 325 | #define GPIO_SET_BITWISE(port, mask) \ |
325 | do { *(&port + (0x800/sizeof(long))) = (mask << 8) | mask; } while(0) | 326 | do { *(&(port) + (0x800/sizeof(long))) = ((mask) << 8) | (mask); } while(0) |
326 | 327 | ||
327 | #define GPIO_CLEAR_BITWISE(port, mask) \ | 328 | #define GPIO_CLEAR_BITWISE(port, mask) \ |
328 | do { *(&port + (0x800/sizeof(long))) = mask << 8; } while(0) | 329 | do { *(&(port) + (0x800/sizeof(long))) = (mask) << 8; } while(0) |
330 | |||
331 | #define GPIO_WRITE_BITWISE(port, val, mask) \ | ||
332 | do { *(&(port) + (0x800/sizeof(long))) = ((mask) << 8) | (val); } while(0) | ||
333 | |||
334 | /* GPIO Module 0 */ | ||
335 | #define GPIOA 0 | ||
336 | #define GPIOB 1 | ||
337 | #define GPIOC 2 | ||
338 | #define GPIOD 3 | ||
339 | /* GPIO Module 1 */ | ||
340 | #define GPIOE 4 | ||
341 | #define GPIOF 5 | ||
342 | #define GPIOG 6 | ||
343 | #define GPIOH 7 | ||
344 | /* GPIO Module 2 */ | ||
345 | #define GPIOI 8 | ||
346 | #define GPIOJ 9 | ||
347 | #define GPIOK 10 | ||
348 | #define GPIOL 11 | ||
349 | |||
350 | #define GPIO_MODULE_NUM(gpio) ((gpio)>>2) | ||
351 | #define GPIO_MAP_ADDR(gpio) (GPIO_BASE_ADDR+(GPIO_MODULE_NUM(gpio)<<7)+(((gpio)&3)<<2)) | ||
352 | #define GPIO_ENABLE(gpio) (*(volatile unsigned long *)(GPIO_MAP_ADDR(gpio)+0x00)) | ||
353 | #define GPIO_OUTPUT_EN(gpio) (*(volatile unsigned long *)(GPIO_MAP_ADDR(gpio)+0x10)) | ||
354 | #define GPIO_OUTPUT_VAL(gpio) (*(volatile unsigned long *)(GPIO_MAP_ADDR(gpio)+0x20)) | ||
355 | #define GPIO_INPUT_VAL(gpio) (*(volatile unsigned long *)(GPIO_MAP_ADDR(gpio)+0x30)) | ||
356 | #define GPIO_INT_STAT(gpio) (*(volatile unsigned long *)(GPIO_MAP_ADDR(gpio)+0x40)) | ||
357 | #define GPIO_INT_EN(gpio) (*(volatile unsigned long *)(GPIO_MAP_ADDR(gpio)+0x50)) | ||
358 | #define GPIO_INT_LEV(gpio) (*(volatile unsigned long *)(GPIO_MAP_ADDR(gpio)+0x60)) | ||
359 | #define GPIO_INT_CLR(gpio) (*(volatile unsigned long *)(GPIO_MAP_ADDR(gpio)+0x70)) | ||
360 | #define GPIO_HI_INT_MASK(gpio) (1ul << GPIO_MODULE_NUM(gpio)) | ||
329 | 361 | ||
330 | /* Device initialization */ | 362 | /* Device initialization */ |
331 | #define PP_VER1 (*(volatile unsigned long *)(0x70000000)) | 363 | #define PP_VER1 (*(volatile unsigned long *)(0x70000000)) |