From da76a3469437261bd8857c6eddeaafcc601f373e Mon Sep 17 00:00:00 2001 From: Michael Sevakis Date: Thu, 22 Jan 2009 22:05:04 +0000 Subject: Use bus reset detection for all ARC OTG devices. Remove conflict from LV24020LP driver with some GPIO-by-number macros for PP502x. Start monitoring for USB stack once all core threads and queues are created otherwise queues will likely be registered after USB acks. Putting PP502x system_reboot in IRAM (unmapped, uncached) memory seems to help it work more consistently. Hopefully I got all the PP USB connect handlers in the right spot in irq_handler. If device seems unresponsive to cable, check there first. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@19819 a1c6a512-1295-4272-9138-f99709370657 --- firmware/export/pp5020.h | 36 ++++++++++++++++++++++++++++++++++-- 1 file changed, 34 insertions(+), 2 deletions(-) (limited to 'firmware/export/pp5020.h') diff --git a/firmware/export/pp5020.h b/firmware/export/pp5020.h index 0f622a907d..36c88e00df 100644 --- a/firmware/export/pp5020.h +++ b/firmware/export/pp5020.h @@ -218,6 +218,7 @@ #define CACHE_OP_INVALIDATE 0x0004 /* GPIO Ports */ +#define GPIO_BASE_ADDR 0x6000d000 #define GPIOA_ENABLE (*(volatile unsigned long *)(0x6000d000)) #define GPIOB_ENABLE (*(volatile unsigned long *)(0x6000d004)) #define GPIOC_ENABLE (*(volatile unsigned long *)(0x6000d008)) @@ -322,10 +323,41 @@ * define the value of those bits. */ #define GPIO_SET_BITWISE(port, mask) \ - do { *(&port + (0x800/sizeof(long))) = (mask << 8) | mask; } while(0) + do { *(&(port) + (0x800/sizeof(long))) = ((mask) << 8) | (mask); } while(0) #define GPIO_CLEAR_BITWISE(port, mask) \ - do { *(&port + (0x800/sizeof(long))) = mask << 8; } while(0) + do { *(&(port) + (0x800/sizeof(long))) = (mask) << 8; } while(0) + +#define GPIO_WRITE_BITWISE(port, val, mask) \ + do { *(&(port) + (0x800/sizeof(long))) = ((mask) << 8) | (val); } while(0) + +/* GPIO Module 0 */ +#define GPIOA 0 +#define GPIOB 1 +#define GPIOC 2 +#define GPIOD 3 +/* GPIO Module 1 */ +#define GPIOE 4 +#define GPIOF 5 +#define GPIOG 6 +#define GPIOH 7 +/* GPIO Module 2 */ +#define GPIOI 8 +#define GPIOJ 9 +#define GPIOK 10 +#define GPIOL 11 + +#define GPIO_MODULE_NUM(gpio) ((gpio)>>2) +#define GPIO_MAP_ADDR(gpio) (GPIO_BASE_ADDR+(GPIO_MODULE_NUM(gpio)<<7)+(((gpio)&3)<<2)) +#define GPIO_ENABLE(gpio) (*(volatile unsigned long *)(GPIO_MAP_ADDR(gpio)+0x00)) +#define GPIO_OUTPUT_EN(gpio) (*(volatile unsigned long *)(GPIO_MAP_ADDR(gpio)+0x10)) +#define GPIO_OUTPUT_VAL(gpio) (*(volatile unsigned long *)(GPIO_MAP_ADDR(gpio)+0x20)) +#define GPIO_INPUT_VAL(gpio) (*(volatile unsigned long *)(GPIO_MAP_ADDR(gpio)+0x30)) +#define GPIO_INT_STAT(gpio) (*(volatile unsigned long *)(GPIO_MAP_ADDR(gpio)+0x40)) +#define GPIO_INT_EN(gpio) (*(volatile unsigned long *)(GPIO_MAP_ADDR(gpio)+0x50)) +#define GPIO_INT_LEV(gpio) (*(volatile unsigned long *)(GPIO_MAP_ADDR(gpio)+0x60)) +#define GPIO_INT_CLR(gpio) (*(volatile unsigned long *)(GPIO_MAP_ADDR(gpio)+0x70)) +#define GPIO_HI_INT_MASK(gpio) (1ul << GPIO_MODULE_NUM(gpio)) /* Device initialization */ #define PP_VER1 (*(volatile unsigned long *)(0x70000000)) -- cgit v1.2.3