diff options
author | Maurus Cuelenaere <mcuelenaere@gmail.com> | 2009-02-16 22:49:58 +0000 |
---|---|---|
committer | Maurus Cuelenaere <mcuelenaere@gmail.com> | 2009-02-16 22:49:58 +0000 |
commit | 360d3d720b87f2029c399a468294838a71181f64 (patch) | |
tree | fec2a00b06d17c4fe8395757ab3df8399abf0972 /firmware/export/mipsregs.h | |
parent | 67a5c56103f5f57d778be90a6babdf5726295bfd (diff) | |
download | rockbox-360d3d720b87f2029c399a468294838a71181f64.tar.gz rockbox-360d3d720b87f2029c399a468294838a71181f64.zip |
Onda VX747:
* Rework battery reading
* Get power off back working
* Add time to debug view
* Convert TABs to spaces in firmware/export/mips*.h
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@20024 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/export/mipsregs.h')
-rw-r--r-- | firmware/export/mipsregs.h | 1068 |
1 files changed, 534 insertions, 534 deletions
diff --git a/firmware/export/mipsregs.h b/firmware/export/mipsregs.h index 0ae9bce4d7..197f8eb992 100644 --- a/firmware/export/mipsregs.h +++ b/firmware/export/mipsregs.h | |||
@@ -74,7 +74,7 @@ | |||
74 | /* | 74 | /* |
75 | * TX39 Series | 75 | * TX39 Series |
76 | */ | 76 | */ |
77 | #define CP0_TX39_CACHE $7 | 77 | #define CP0_TX39_CACHE $7 |
78 | 78 | ||
79 | /* | 79 | /* |
80 | * Coprocessor 1 (FPU) register names | 80 | * Coprocessor 1 (FPU) register names |
@@ -141,38 +141,38 @@ | |||
141 | 141 | ||
142 | /* Why doesn't stupidity hurt ... */ | 142 | /* Why doesn't stupidity hurt ... */ |
143 | 143 | ||
144 | #define PM_1K 0x00000000 | 144 | #define PM_1K 0x00000000 |
145 | #define PM_4K 0x00001800 | 145 | #define PM_4K 0x00001800 |
146 | #define PM_16K 0x00007800 | 146 | #define PM_16K 0x00007800 |
147 | #define PM_64K 0x0001f800 | 147 | #define PM_64K 0x0001f800 |
148 | #define PM_256K 0x0007f800 | 148 | #define PM_256K 0x0007f800 |
149 | 149 | ||
150 | #else | 150 | #else |
151 | 151 | ||
152 | #define PM_4K 0x00000000 | 152 | #define PM_4K 0x00000000 |
153 | #define PM_16K 0x00006000 | 153 | #define PM_16K 0x00006000 |
154 | #define PM_64K 0x0001e000 | 154 | #define PM_64K 0x0001e000 |
155 | #define PM_256K 0x0007e000 | 155 | #define PM_256K 0x0007e000 |
156 | #define PM_1M 0x001fe000 | 156 | #define PM_1M 0x001fe000 |
157 | #define PM_4M 0x007fe000 | 157 | #define PM_4M 0x007fe000 |
158 | #define PM_16M 0x01ffe000 | 158 | #define PM_16M 0x01ffe000 |
159 | #define PM_64M 0x07ffe000 | 159 | #define PM_64M 0x07ffe000 |
160 | #define PM_256M 0x1fffe000 | 160 | #define PM_256M 0x1fffe000 |
161 | 161 | ||
162 | #endif | 162 | #endif |
163 | 163 | ||
164 | /* | 164 | /* |
165 | * Values used for computation of new tlb entries | 165 | * Values used for computation of new tlb entries |
166 | */ | 166 | */ |
167 | #define PL_4K 12 | 167 | #define PL_4K 12 |
168 | #define PL_16K 14 | 168 | #define PL_16K 14 |
169 | #define PL_64K 16 | 169 | #define PL_64K 16 |
170 | #define PL_256K 18 | 170 | #define PL_256K 18 |
171 | #define PL_1M 20 | 171 | #define PL_1M 20 |
172 | #define PL_4M 22 | 172 | #define PL_4M 22 |
173 | #define PL_16M 24 | 173 | #define PL_16M 24 |
174 | #define PL_64M 26 | 174 | #define PL_64M 26 |
175 | #define PL_256M 28 | 175 | #define PL_256M 28 |
176 | 176 | ||
177 | /* | 177 | /* |
178 | * R4x00 interrupt enable / cause bits | 178 | * R4x00 interrupt enable / cause bits |
@@ -201,233 +201,233 @@ | |||
201 | /* | 201 | /* |
202 | * Bitfields in the R4xx0 cp0 status register | 202 | * Bitfields in the R4xx0 cp0 status register |
203 | */ | 203 | */ |
204 | #define ST0_IE 0x00000001 | 204 | #define ST0_IE 0x00000001 |
205 | #define ST0_EXL 0x00000002 | 205 | #define ST0_EXL 0x00000002 |
206 | #define ST0_ERL 0x00000004 | 206 | #define ST0_ERL 0x00000004 |
207 | #define ST0_KSU 0x00000018 | 207 | #define ST0_KSU 0x00000018 |
208 | # define KSU_USER 0x00000010 | 208 | # define KSU_USER 0x00000010 |
209 | # define KSU_SUPERVISOR 0x00000008 | 209 | # define KSU_SUPERVISOR 0x00000008 |
210 | # define KSU_KERNEL 0x00000000 | 210 | # define KSU_KERNEL 0x00000000 |
211 | #define ST0_UX 0x00000020 | 211 | #define ST0_UX 0x00000020 |
212 | #define ST0_SX 0x00000040 | 212 | #define ST0_SX 0x00000040 |
213 | #define ST0_KX 0x00000080 | 213 | #define ST0_KX 0x00000080 |
214 | #define ST0_DE 0x00010000 | 214 | #define ST0_DE 0x00010000 |
215 | #define ST0_CE 0x00020000 | 215 | #define ST0_CE 0x00020000 |
216 | 216 | ||
217 | /* | 217 | /* |
218 | * Bitfields in the R[23]000 cp0 status register. | 218 | * Bitfields in the R[23]000 cp0 status register. |
219 | */ | 219 | */ |
220 | #define ST0_IEC 0x00000001 | 220 | #define ST0_IEC 0x00000001 |
221 | #define ST0_KUC 0x00000002 | 221 | #define ST0_KUC 0x00000002 |
222 | #define ST0_IEP 0x00000004 | 222 | #define ST0_IEP 0x00000004 |
223 | #define ST0_KUP 0x00000008 | 223 | #define ST0_KUP 0x00000008 |
224 | #define ST0_IEO 0x00000010 | 224 | #define ST0_IEO 0x00000010 |
225 | #define ST0_KUO 0x00000020 | 225 | #define ST0_KUO 0x00000020 |
226 | /* bits 6 & 7 are reserved on R[23]000 */ | 226 | /* bits 6 & 7 are reserved on R[23]000 */ |
227 | #define ST0_ISC 0x00010000 | 227 | #define ST0_ISC 0x00010000 |
228 | #define ST0_SWC 0x00020000 | 228 | #define ST0_SWC 0x00020000 |
229 | #define ST0_CM 0x00080000 | 229 | #define ST0_CM 0x00080000 |
230 | 230 | ||
231 | /* | 231 | /* |
232 | * Bits specific to the R4640/R4650 | 232 | * Bits specific to the R4640/R4650 |
233 | */ | 233 | */ |
234 | #define ST0_UM (_ULCAST_(1) << 4) | 234 | #define ST0_UM (_ULCAST_(1) << 4) |
235 | #define ST0_IL (_ULCAST_(1) << 23) | 235 | #define ST0_IL (_ULCAST_(1) << 23) |
236 | #define ST0_DL (_ULCAST_(1) << 24) | 236 | #define ST0_DL (_ULCAST_(1) << 24) |
237 | 237 | ||
238 | /* | 238 | /* |
239 | * Bitfields in the TX39 family CP0 Configuration Register 3 | 239 | * Bitfields in the TX39 family CP0 Configuration Register 3 |
240 | */ | 240 | */ |
241 | #define TX39_CONF_ICS_SHIFT 19 | 241 | #define TX39_CONF_ICS_SHIFT 19 |
242 | #define TX39_CONF_ICS_MASK 0x00380000 | 242 | #define TX39_CONF_ICS_MASK 0x00380000 |
243 | #define TX39_CONF_ICS_1KB 0x00000000 | 243 | #define TX39_CONF_ICS_1KB 0x00000000 |
244 | #define TX39_CONF_ICS_2KB 0x00080000 | 244 | #define TX39_CONF_ICS_2KB 0x00080000 |
245 | #define TX39_CONF_ICS_4KB 0x00100000 | 245 | #define TX39_CONF_ICS_4KB 0x00100000 |
246 | #define TX39_CONF_ICS_8KB 0x00180000 | 246 | #define TX39_CONF_ICS_8KB 0x00180000 |
247 | #define TX39_CONF_ICS_16KB 0x00200000 | 247 | #define TX39_CONF_ICS_16KB 0x00200000 |
248 | 248 | ||
249 | #define TX39_CONF_DCS_SHIFT 16 | 249 | #define TX39_CONF_DCS_SHIFT 16 |
250 | #define TX39_CONF_DCS_MASK 0x00070000 | 250 | #define TX39_CONF_DCS_MASK 0x00070000 |
251 | #define TX39_CONF_DCS_1KB 0x00000000 | 251 | #define TX39_CONF_DCS_1KB 0x00000000 |
252 | #define TX39_CONF_DCS_2KB 0x00010000 | 252 | #define TX39_CONF_DCS_2KB 0x00010000 |
253 | #define TX39_CONF_DCS_4KB 0x00020000 | 253 | #define TX39_CONF_DCS_4KB 0x00020000 |
254 | #define TX39_CONF_DCS_8KB 0x00030000 | 254 | #define TX39_CONF_DCS_8KB 0x00030000 |
255 | #define TX39_CONF_DCS_16KB 0x00040000 | 255 | #define TX39_CONF_DCS_16KB 0x00040000 |
256 | 256 | ||
257 | #define TX39_CONF_CWFON 0x00004000 | 257 | #define TX39_CONF_CWFON 0x00004000 |
258 | #define TX39_CONF_WBON 0x00002000 | 258 | #define TX39_CONF_WBON 0x00002000 |
259 | #define TX39_CONF_RF_SHIFT 10 | 259 | #define TX39_CONF_RF_SHIFT 10 |
260 | #define TX39_CONF_RF_MASK 0x00000c00 | 260 | #define TX39_CONF_RF_MASK 0x00000c00 |
261 | #define TX39_CONF_DOZE 0x00000200 | 261 | #define TX39_CONF_DOZE 0x00000200 |
262 | #define TX39_CONF_HALT 0x00000100 | 262 | #define TX39_CONF_HALT 0x00000100 |
263 | #define TX39_CONF_LOCK 0x00000080 | 263 | #define TX39_CONF_LOCK 0x00000080 |
264 | #define TX39_CONF_ICE 0x00000020 | 264 | #define TX39_CONF_ICE 0x00000020 |
265 | #define TX39_CONF_DCE 0x00000010 | 265 | #define TX39_CONF_DCE 0x00000010 |
266 | #define TX39_CONF_IRSIZE_SHIFT 2 | 266 | #define TX39_CONF_IRSIZE_SHIFT 2 |
267 | #define TX39_CONF_IRSIZE_MASK 0x0000000c | 267 | #define TX39_CONF_IRSIZE_MASK 0x0000000c |
268 | #define TX39_CONF_DRSIZE_SHIFT 0 | 268 | #define TX39_CONF_DRSIZE_SHIFT 0 |
269 | #define TX39_CONF_DRSIZE_MASK 0x00000003 | 269 | #define TX39_CONF_DRSIZE_MASK 0x00000003 |
270 | 270 | ||
271 | /* | 271 | /* |
272 | * Status register bits available in all MIPS CPUs. | 272 | * Status register bits available in all MIPS CPUs. |
273 | */ | 273 | */ |
274 | #define ST0_IM 0x0000ff00 | 274 | #define ST0_IM 0x0000ff00 |
275 | #define STATUSB_IP0 8 | 275 | #define STATUSB_IP0 8 |
276 | #define STATUSF_IP0 (_ULCAST_(1) << 8) | 276 | #define STATUSF_IP0 (_ULCAST_(1) << 8) |
277 | #define STATUSB_IP1 9 | 277 | #define STATUSB_IP1 9 |
278 | #define STATUSF_IP1 (_ULCAST_(1) << 9) | 278 | #define STATUSF_IP1 (_ULCAST_(1) << 9) |
279 | #define STATUSB_IP2 10 | 279 | #define STATUSB_IP2 10 |
280 | #define STATUSF_IP2 (_ULCAST_(1) << 10) | 280 | #define STATUSF_IP2 (_ULCAST_(1) << 10) |
281 | #define STATUSB_IP3 11 | 281 | #define STATUSB_IP3 11 |
282 | #define STATUSF_IP3 (_ULCAST_(1) << 11) | 282 | #define STATUSF_IP3 (_ULCAST_(1) << 11) |
283 | #define STATUSB_IP4 12 | 283 | #define STATUSB_IP4 12 |
284 | #define STATUSF_IP4 (_ULCAST_(1) << 12) | 284 | #define STATUSF_IP4 (_ULCAST_(1) << 12) |
285 | #define STATUSB_IP5 13 | 285 | #define STATUSB_IP5 13 |
286 | #define STATUSF_IP5 (_ULCAST_(1) << 13) | 286 | #define STATUSF_IP5 (_ULCAST_(1) << 13) |
287 | #define STATUSB_IP6 14 | 287 | #define STATUSB_IP6 14 |
288 | #define STATUSF_IP6 (_ULCAST_(1) << 14) | 288 | #define STATUSF_IP6 (_ULCAST_(1) << 14) |
289 | #define STATUSB_IP7 15 | 289 | #define STATUSB_IP7 15 |
290 | #define STATUSF_IP7 (_ULCAST_(1) << 15) | 290 | #define STATUSF_IP7 (_ULCAST_(1) << 15) |
291 | #define STATUSB_IP8 0 | 291 | #define STATUSB_IP8 0 |
292 | #define STATUSF_IP8 (_ULCAST_(1) << 0) | 292 | #define STATUSF_IP8 (_ULCAST_(1) << 0) |
293 | #define STATUSB_IP9 1 | 293 | #define STATUSB_IP9 1 |
294 | #define STATUSF_IP9 (_ULCAST_(1) << 1) | 294 | #define STATUSF_IP9 (_ULCAST_(1) << 1) |
295 | #define STATUSB_IP10 2 | 295 | #define STATUSB_IP10 2 |
296 | #define STATUSF_IP10 (_ULCAST_(1) << 2) | 296 | #define STATUSF_IP10 (_ULCAST_(1) << 2) |
297 | #define STATUSB_IP11 3 | 297 | #define STATUSB_IP11 3 |
298 | #define STATUSF_IP11 (_ULCAST_(1) << 3) | 298 | #define STATUSF_IP11 (_ULCAST_(1) << 3) |
299 | #define STATUSB_IP12 4 | 299 | #define STATUSB_IP12 4 |
300 | #define STATUSF_IP12 (_ULCAST_(1) << 4) | 300 | #define STATUSF_IP12 (_ULCAST_(1) << 4) |
301 | #define STATUSB_IP13 5 | 301 | #define STATUSB_IP13 5 |
302 | #define STATUSF_IP13 (_ULCAST_(1) << 5) | 302 | #define STATUSF_IP13 (_ULCAST_(1) << 5) |
303 | #define STATUSB_IP14 6 | 303 | #define STATUSB_IP14 6 |
304 | #define STATUSF_IP14 (_ULCAST_(1) << 6) | 304 | #define STATUSF_IP14 (_ULCAST_(1) << 6) |
305 | #define STATUSB_IP15 7 | 305 | #define STATUSB_IP15 7 |
306 | #define STATUSF_IP15 (_ULCAST_(1) << 7) | 306 | #define STATUSF_IP15 (_ULCAST_(1) << 7) |
307 | #define ST0_CH 0x00040000 | 307 | #define ST0_CH 0x00040000 |
308 | #define ST0_SR 0x00100000 | 308 | #define ST0_SR 0x00100000 |
309 | #define ST0_TS 0x00200000 | 309 | #define ST0_TS 0x00200000 |
310 | #define ST0_BEV 0x00400000 | 310 | #define ST0_BEV 0x00400000 |
311 | #define ST0_RE 0x02000000 | 311 | #define ST0_RE 0x02000000 |
312 | #define ST0_FR 0x04000000 | 312 | #define ST0_FR 0x04000000 |
313 | #define ST0_CU 0xf0000000 | 313 | #define ST0_CU 0xf0000000 |
314 | #define ST0_CU0 0x10000000 | 314 | #define ST0_CU0 0x10000000 |
315 | #define ST0_CU1 0x20000000 | 315 | #define ST0_CU1 0x20000000 |
316 | #define ST0_CU2 0x40000000 | 316 | #define ST0_CU2 0x40000000 |
317 | #define ST0_CU3 0x80000000 | 317 | #define ST0_CU3 0x80000000 |
318 | #define ST0_XX 0x80000000 /* MIPS IV naming */ | 318 | #define ST0_XX 0x80000000 /* MIPS IV naming */ |
319 | 319 | ||
320 | /* | 320 | /* |
321 | * Bitfields and bit numbers in the coprocessor 0 cause register. | 321 | * Bitfields and bit numbers in the coprocessor 0 cause register. |
322 | * | 322 | * |
323 | * Refer to your MIPS R4xx0 manual, chapter 5 for explanation. | 323 | * Refer to your MIPS R4xx0 manual, chapter 5 for explanation. |
324 | */ | 324 | */ |
325 | #define CAUSEB_EXCCODE 2 | 325 | #define CAUSEB_EXCCODE 2 |
326 | #define CAUSEF_EXCCODE (_ULCAST_(31) << 2) | 326 | #define CAUSEF_EXCCODE (_ULCAST_(31) << 2) |
327 | #define CAUSEB_IP 8 | 327 | #define CAUSEB_IP 8 |
328 | #define CAUSEF_IP (_ULCAST_(255) << 8) | 328 | #define CAUSEF_IP (_ULCAST_(255) << 8) |
329 | #define CAUSEB_IP0 8 | 329 | #define CAUSEB_IP0 8 |
330 | #define CAUSEF_IP0 (_ULCAST_(1) << 8) | 330 | #define CAUSEF_IP0 (_ULCAST_(1) << 8) |
331 | #define CAUSEB_IP1 9 | 331 | #define CAUSEB_IP1 9 |
332 | #define CAUSEF_IP1 (_ULCAST_(1) << 9) | 332 | #define CAUSEF_IP1 (_ULCAST_(1) << 9) |
333 | #define CAUSEB_IP2 10 | 333 | #define CAUSEB_IP2 10 |
334 | #define CAUSEF_IP2 (_ULCAST_(1) << 10) | 334 | #define CAUSEF_IP2 (_ULCAST_(1) << 10) |
335 | #define CAUSEB_IP3 11 | 335 | #define CAUSEB_IP3 11 |
336 | #define CAUSEF_IP3 (_ULCAST_(1) << 11) | 336 | #define CAUSEF_IP3 (_ULCAST_(1) << 11) |
337 | #define CAUSEB_IP4 12 | 337 | #define CAUSEB_IP4 12 |
338 | #define CAUSEF_IP4 (_ULCAST_(1) << 12) | 338 | #define CAUSEF_IP4 (_ULCAST_(1) << 12) |
339 | #define CAUSEB_IP5 13 | 339 | #define CAUSEB_IP5 13 |
340 | #define CAUSEF_IP5 (_ULCAST_(1) << 13) | 340 | #define CAUSEF_IP5 (_ULCAST_(1) << 13) |
341 | #define CAUSEB_IP6 14 | 341 | #define CAUSEB_IP6 14 |
342 | #define CAUSEF_IP6 (_ULCAST_(1) << 14) | 342 | #define CAUSEF_IP6 (_ULCAST_(1) << 14) |
343 | #define CAUSEB_IP7 15 | 343 | #define CAUSEB_IP7 15 |
344 | #define CAUSEF_IP7 (_ULCAST_(1) << 15) | 344 | #define CAUSEF_IP7 (_ULCAST_(1) << 15) |
345 | #define CAUSEB_IV 23 | 345 | #define CAUSEB_IV 23 |
346 | #define CAUSEF_IV (_ULCAST_(1) << 23) | 346 | #define CAUSEF_IV (_ULCAST_(1) << 23) |
347 | #define CAUSEB_CE 28 | 347 | #define CAUSEB_CE 28 |
348 | #define CAUSEF_CE (_ULCAST_(3) << 28) | 348 | #define CAUSEF_CE (_ULCAST_(3) << 28) |
349 | #define CAUSEB_BD 31 | 349 | #define CAUSEB_BD 31 |
350 | #define CAUSEF_BD (_ULCAST_(1) << 31) | 350 | #define CAUSEF_BD (_ULCAST_(1) << 31) |
351 | 351 | ||
352 | /* | 352 | /* |
353 | * Bits in the coprocessor 0 config register. | 353 | * Bits in the coprocessor 0 config register. |
354 | */ | 354 | */ |
355 | /* Generic bits. */ | 355 | /* Generic bits. */ |
356 | #define CONF_CM_CACHABLE_NO_WA 0 | 356 | #define CONF_CM_CACHABLE_NO_WA 0 |
357 | #define CONF_CM_CACHABLE_WA 1 | 357 | #define CONF_CM_CACHABLE_WA 1 |
358 | #define CONF_CM_UNCACHED 2 | 358 | #define CONF_CM_UNCACHED 2 |
359 | #define CONF_CM_CACHABLE_NONCOHERENT 3 | 359 | #define CONF_CM_CACHABLE_NONCOHERENT 3 |
360 | #define CONF_CM_CACHABLE_CE 4 | 360 | #define CONF_CM_CACHABLE_CE 4 |
361 | #define CONF_CM_CACHABLE_COW 5 | 361 | #define CONF_CM_CACHABLE_COW 5 |
362 | #define CONF_CM_CACHABLE_CUW 6 | 362 | #define CONF_CM_CACHABLE_CUW 6 |
363 | #define CONF_CM_CACHABLE_ACCELERATED 7 | 363 | #define CONF_CM_CACHABLE_ACCELERATED 7 |
364 | #define CONF_CM_CMASK 7 | 364 | #define CONF_CM_CMASK 7 |
365 | #define CONF_BE (_ULCAST_(1) << 15) | 365 | #define CONF_BE (_ULCAST_(1) << 15) |
366 | 366 | ||
367 | /* Bits common to various processors. */ | 367 | /* Bits common to various processors. */ |
368 | #define CONF_CU (_ULCAST_(1) << 3) | 368 | #define CONF_CU (_ULCAST_(1) << 3) |
369 | #define CONF_DB (_ULCAST_(1) << 4) | 369 | #define CONF_DB (_ULCAST_(1) << 4) |
370 | #define CONF_IB (_ULCAST_(1) << 5) | 370 | #define CONF_IB (_ULCAST_(1) << 5) |
371 | #define CONF_DC (_ULCAST_(7) << 6) | 371 | #define CONF_DC (_ULCAST_(7) << 6) |
372 | #define CONF_IC (_ULCAST_(7) << 9) | 372 | #define CONF_IC (_ULCAST_(7) << 9) |
373 | #define CONF_EB (_ULCAST_(1) << 13) | 373 | #define CONF_EB (_ULCAST_(1) << 13) |
374 | #define CONF_EM (_ULCAST_(1) << 14) | 374 | #define CONF_EM (_ULCAST_(1) << 14) |
375 | #define CONF_SM (_ULCAST_(1) << 16) | 375 | #define CONF_SM (_ULCAST_(1) << 16) |
376 | #define CONF_SC (_ULCAST_(1) << 17) | 376 | #define CONF_SC (_ULCAST_(1) << 17) |
377 | #define CONF_EW (_ULCAST_(3) << 18) | 377 | #define CONF_EW (_ULCAST_(3) << 18) |
378 | #define CONF_EP (_ULCAST_(15)<< 24) | 378 | #define CONF_EP (_ULCAST_(15)<< 24) |
379 | #define CONF_EC (_ULCAST_(7) << 28) | 379 | #define CONF_EC (_ULCAST_(7) << 28) |
380 | #define CONF_CM (_ULCAST_(1) << 31) | 380 | #define CONF_CM (_ULCAST_(1) << 31) |
381 | 381 | ||
382 | /* Bits specific to the R4xx0. */ | 382 | /* Bits specific to the R4xx0. */ |
383 | #define R4K_CONF_SW (_ULCAST_(1) << 20) | 383 | #define R4K_CONF_SW (_ULCAST_(1) << 20) |
384 | #define R4K_CONF_SS (_ULCAST_(1) << 21) | 384 | #define R4K_CONF_SS (_ULCAST_(1) << 21) |
385 | #define R4K_CONF_SB (_ULCAST_(3) << 22) | 385 | #define R4K_CONF_SB (_ULCAST_(3) << 22) |
386 | 386 | ||
387 | /* Bits specific to the R5000. */ | 387 | /* Bits specific to the R5000. */ |
388 | #define R5K_CONF_SE (_ULCAST_(1) << 12) | 388 | #define R5K_CONF_SE (_ULCAST_(1) << 12) |
389 | #define R5K_CONF_SS (_ULCAST_(3) << 20) | 389 | #define R5K_CONF_SS (_ULCAST_(3) << 20) |
390 | 390 | ||
391 | /* Bits specific to the R10000. */ | 391 | /* Bits specific to the R10000. */ |
392 | #define R10K_CONF_DN (_ULCAST_(3) << 3) | 392 | #define R10K_CONF_DN (_ULCAST_(3) << 3) |
393 | #define R10K_CONF_CT (_ULCAST_(1) << 5) | 393 | #define R10K_CONF_CT (_ULCAST_(1) << 5) |
394 | #define R10K_CONF_PE (_ULCAST_(1) << 6) | 394 | #define R10K_CONF_PE (_ULCAST_(1) << 6) |
395 | #define R10K_CONF_PM (_ULCAST_(3) << 7) | 395 | #define R10K_CONF_PM (_ULCAST_(3) << 7) |
396 | #define R10K_CONF_EC (_ULCAST_(15)<< 9) | 396 | #define R10K_CONF_EC (_ULCAST_(15)<< 9) |
397 | #define R10K_CONF_SB (_ULCAST_(1) << 13) | 397 | #define R10K_CONF_SB (_ULCAST_(1) << 13) |
398 | #define R10K_CONF_SK (_ULCAST_(1) << 14) | 398 | #define R10K_CONF_SK (_ULCAST_(1) << 14) |
399 | #define R10K_CONF_SS (_ULCAST_(7) << 16) | 399 | #define R10K_CONF_SS (_ULCAST_(7) << 16) |
400 | #define R10K_CONF_SC (_ULCAST_(7) << 19) | 400 | #define R10K_CONF_SC (_ULCAST_(7) << 19) |
401 | #define R10K_CONF_DC (_ULCAST_(7) << 26) | 401 | #define R10K_CONF_DC (_ULCAST_(7) << 26) |
402 | #define R10K_CONF_IC (_ULCAST_(7) << 29) | 402 | #define R10K_CONF_IC (_ULCAST_(7) << 29) |
403 | 403 | ||
404 | /* Bits specific to the VR41xx. */ | 404 | /* Bits specific to the VR41xx. */ |
405 | #define VR41_CONF_CS (_ULCAST_(1) << 12) | 405 | #define VR41_CONF_CS (_ULCAST_(1) << 12) |
406 | #define VR41_CONF_M16 (_ULCAST_(1) << 20) | 406 | #define VR41_CONF_M16 (_ULCAST_(1) << 20) |
407 | #define VR41_CONF_AD (_ULCAST_(1) << 23) | 407 | #define VR41_CONF_AD (_ULCAST_(1) << 23) |
408 | 408 | ||
409 | /* Bits specific to the R30xx. */ | 409 | /* Bits specific to the R30xx. */ |
410 | #define R30XX_CONF_FDM (_ULCAST_(1) << 19) | 410 | #define R30XX_CONF_FDM (_ULCAST_(1) << 19) |
411 | #define R30XX_CONF_REV (_ULCAST_(1) << 22) | 411 | #define R30XX_CONF_REV (_ULCAST_(1) << 22) |
412 | #define R30XX_CONF_AC (_ULCAST_(1) << 23) | 412 | #define R30XX_CONF_AC (_ULCAST_(1) << 23) |
413 | #define R30XX_CONF_RF (_ULCAST_(1) << 24) | 413 | #define R30XX_CONF_RF (_ULCAST_(1) << 24) |
414 | #define R30XX_CONF_HALT (_ULCAST_(1) << 25) | 414 | #define R30XX_CONF_HALT (_ULCAST_(1) << 25) |
415 | #define R30XX_CONF_FPINT (_ULCAST_(7) << 26) | 415 | #define R30XX_CONF_FPINT (_ULCAST_(7) << 26) |
416 | #define R30XX_CONF_DBR (_ULCAST_(1) << 29) | 416 | #define R30XX_CONF_DBR (_ULCAST_(1) << 29) |
417 | #define R30XX_CONF_SB (_ULCAST_(1) << 30) | 417 | #define R30XX_CONF_SB (_ULCAST_(1) << 30) |
418 | #define R30XX_CONF_LOCK (_ULCAST_(1) << 31) | 418 | #define R30XX_CONF_LOCK (_ULCAST_(1) << 31) |
419 | 419 | ||
420 | /* Bits specific to the TX49. */ | 420 | /* Bits specific to the TX49. */ |
421 | #define TX49_CONF_DC (_ULCAST_(1) << 16) | 421 | #define TX49_CONF_DC (_ULCAST_(1) << 16) |
422 | #define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */ | 422 | #define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */ |
423 | #define TX49_CONF_HALT (_ULCAST_(1) << 18) | 423 | #define TX49_CONF_HALT (_ULCAST_(1) << 18) |
424 | #define TX49_CONF_CWFON (_ULCAST_(1) << 27) | 424 | #define TX49_CONF_CWFON (_ULCAST_(1) << 27) |
425 | 425 | ||
426 | /* Bits specific to the MIPS32/64 PRA. */ | 426 | /* Bits specific to the MIPS32/64 PRA. */ |
427 | #define MIPS_CONF_MT (_ULCAST_(7) << 7) | 427 | #define MIPS_CONF_MT (_ULCAST_(7) << 7) |
428 | #define MIPS_CONF_AR (_ULCAST_(7) << 10) | 428 | #define MIPS_CONF_AR (_ULCAST_(7) << 10) |
429 | #define MIPS_CONF_AT (_ULCAST_(3) << 13) | 429 | #define MIPS_CONF_AT (_ULCAST_(3) << 13) |
430 | #define MIPS_CONF_M (_ULCAST_(1) << 31) | 430 | #define MIPS_CONF_M (_ULCAST_(1) << 31) |
431 | 431 | ||
432 | /* | 432 | /* |
433 | * R10000 performance counter definitions. | 433 | * R10000 performance counter definitions. |
@@ -440,50 +440,50 @@ | |||
440 | /* | 440 | /* |
441 | * Events counted by counter #0 | 441 | * Events counted by counter #0 |
442 | */ | 442 | */ |
443 | #define CE0_CYCLES 0 | 443 | #define CE0_CYCLES 0 |
444 | #define CE0_INSN_ISSUED 1 | 444 | #define CE0_INSN_ISSUED 1 |
445 | #define CE0_LPSC_ISSUED 2 | 445 | #define CE0_LPSC_ISSUED 2 |
446 | #define CE0_S_ISSUED 3 | 446 | #define CE0_S_ISSUED 3 |
447 | #define CE0_SC_ISSUED 4 | 447 | #define CE0_SC_ISSUED 4 |
448 | #define CE0_SC_FAILED 5 | 448 | #define CE0_SC_FAILED 5 |
449 | #define CE0_BRANCH_DECODED 6 | 449 | #define CE0_BRANCH_DECODED 6 |
450 | #define CE0_QW_WB_SECONDARY 7 | 450 | #define CE0_QW_WB_SECONDARY 7 |
451 | #define CE0_CORRECTED_ECC_ERRORS 8 | 451 | #define CE0_CORRECTED_ECC_ERRORS 8 |
452 | #define CE0_ICACHE_MISSES 9 | 452 | #define CE0_ICACHE_MISSES 9 |
453 | #define CE0_SCACHE_I_MISSES 10 | 453 | #define CE0_SCACHE_I_MISSES 10 |
454 | #define CE0_SCACHE_I_WAY_MISSPREDICTED 11 | 454 | #define CE0_SCACHE_I_WAY_MISSPREDICTED 11 |
455 | #define CE0_EXT_INTERVENTIONS_REQ 12 | 455 | #define CE0_EXT_INTERVENTIONS_REQ 12 |
456 | #define CE0_EXT_INVALIDATE_REQ 13 | 456 | #define CE0_EXT_INVALIDATE_REQ 13 |
457 | #define CE0_VIRTUAL_COHERENCY_COND 14 | 457 | #define CE0_VIRTUAL_COHERENCY_COND 14 |
458 | #define CE0_INSN_GRADUATED 15 | 458 | #define CE0_INSN_GRADUATED 15 |
459 | 459 | ||
460 | /* | 460 | /* |
461 | * Events counted by counter #1 | 461 | * Events counted by counter #1 |
462 | */ | 462 | */ |
463 | #define CE1_CYCLES 0 | 463 | #define CE1_CYCLES 0 |
464 | #define CE1_INSN_GRADUATED 1 | 464 | #define CE1_INSN_GRADUATED 1 |
465 | #define CE1_LPSC_GRADUATED 2 | 465 | #define CE1_LPSC_GRADUATED 2 |
466 | #define CE1_S_GRADUATED 3 | 466 | #define CE1_S_GRADUATED 3 |
467 | #define CE1_SC_GRADUATED 4 | 467 | #define CE1_SC_GRADUATED 4 |
468 | #define CE1_FP_INSN_GRADUATED 5 | 468 | #define CE1_FP_INSN_GRADUATED 5 |
469 | #define CE1_QW_WB_PRIMARY 6 | 469 | #define CE1_QW_WB_PRIMARY 6 |
470 | #define CE1_TLB_REFILL 7 | 470 | #define CE1_TLB_REFILL 7 |
471 | #define CE1_BRANCH_MISSPREDICTED 8 | 471 | #define CE1_BRANCH_MISSPREDICTED 8 |
472 | #define CE1_DCACHE_MISS 9 | 472 | #define CE1_DCACHE_MISS 9 |
473 | #define CE1_SCACHE_D_MISSES 10 | 473 | #define CE1_SCACHE_D_MISSES 10 |
474 | #define CE1_SCACHE_D_WAY_MISSPREDICTED 11 | 474 | #define CE1_SCACHE_D_WAY_MISSPREDICTED 11 |
475 | #define CE1_EXT_INTERVENTION_HITS 12 | 475 | #define CE1_EXT_INTERVENTION_HITS 12 |
476 | #define CE1_EXT_INVALIDATE_REQ 13 | 476 | #define CE1_EXT_INVALIDATE_REQ 13 |
477 | #define CE1_SP_HINT_TO_CEXCL_SC_BLOCKS 14 | 477 | #define CE1_SP_HINT_TO_CEXCL_SC_BLOCKS 14 |
478 | #define CE1_SP_HINT_TO_SHARED_SC_BLOCKS 15 | 478 | #define CE1_SP_HINT_TO_SHARED_SC_BLOCKS 15 |
479 | 479 | ||
480 | /* | 480 | /* |
481 | * These flags define in which priviledge mode the counters count events | 481 | * These flags define in which priviledge mode the counters count events |
482 | */ | 482 | */ |
483 | #define CEB_USER 8 /* Count events in user mode, EXL = ERL = 0 */ | 483 | #define CEB_USER 8 /* Count events in user mode, EXL = ERL = 0 */ |
484 | #define CEB_SUPERVISOR 4 /* Count events in supvervisor mode EXL = ERL = 0 */ | 484 | #define CEB_SUPERVISOR 4 /* Count events in supvervisor mode EXL = ERL = 0 */ |
485 | #define CEB_KERNEL 2 /* Count events in kernel mode EXL = ERL = 0 */ | 485 | #define CEB_KERNEL 2 /* Count events in kernel mode EXL = ERL = 0 */ |
486 | #define CEB_EXL 1 /* Count events with EXL = 1, ERL = 0 */ | 486 | #define CEB_EXL 1 /* Count events with EXL = 1, ERL = 0 */ |
487 | 487 | ||
488 | #ifndef __ASSEMBLY__ | 488 | #ifndef __ASSEMBLY__ |
489 | 489 | ||
@@ -521,274 +521,274 @@ | |||
521 | * Macros to access the system control coprocessor | 521 | * Macros to access the system control coprocessor |
522 | */ | 522 | */ |
523 | 523 | ||
524 | #define __read_32bit_c0_register(source, sel) \ | 524 | #define __read_32bit_c0_register(source, sel) \ |
525 | ({ unsigned int __res; \ | 525 | ({ unsigned int __res; \ |
526 | if (sel == 0) \ | 526 | if (sel == 0) \ |
527 | __asm__ __volatile__( \ | 527 | __asm__ __volatile__( \ |
528 | "mfc0\t%0, " #source "\n\t" \ | 528 | "mfc0\t%0, " #source "\n\t" \ |
529 | : "=r" (__res)); \ | 529 | : "=r" (__res)); \ |
530 | else \ | 530 | else \ |
531 | __asm__ __volatile__( \ | 531 | __asm__ __volatile__( \ |
532 | ".set\tmips32\n\t" \ | 532 | ".set\tmips32\n\t" \ |
533 | "mfc0\t%0, " #source ", " #sel "\n\t" \ | 533 | "mfc0\t%0, " #source ", " #sel "\n\t" \ |
534 | ".set\tmips0\n\t" \ | 534 | ".set\tmips0\n\t" \ |
535 | : "=r" (__res)); \ | 535 | : "=r" (__res)); \ |
536 | __res; \ | 536 | __res; \ |
537 | }) | 537 | }) |
538 | 538 | ||
539 | #define __read_64bit_c0_register(source, sel) \ | 539 | #define __read_64bit_c0_register(source, sel) \ |
540 | ({ unsigned long __res; \ | 540 | ({ unsigned long __res; \ |
541 | if (sel == 0) \ | 541 | if (sel == 0) \ |
542 | __asm__ __volatile__( \ | 542 | __asm__ __volatile__( \ |
543 | ".set\tmips3\n\t" \ | 543 | ".set\tmips3\n\t" \ |
544 | "dmfc0\t%0, " #source "\n\t" \ | 544 | "dmfc0\t%0, " #source "\n\t" \ |
545 | ".set\tmips0" \ | 545 | ".set\tmips0" \ |
546 | : "=r" (__res)); \ | 546 | : "=r" (__res)); \ |
547 | else \ | 547 | else \ |
548 | __asm__ __volatile__( \ | 548 | __asm__ __volatile__( \ |
549 | ".set\tmips64\n\t" \ | 549 | ".set\tmips64\n\t" \ |
550 | "dmfc0\t%0, " #source ", " #sel "\n\t" \ | 550 | "dmfc0\t%0, " #source ", " #sel "\n\t" \ |
551 | ".set\tmips0" \ | 551 | ".set\tmips0" \ |
552 | : "=r" (__res)); \ | 552 | : "=r" (__res)); \ |
553 | __res; \ | 553 | __res; \ |
554 | }) | 554 | }) |
555 | 555 | ||
556 | #define __write_32bit_c0_register(register, sel, value) \ | 556 | #define __write_32bit_c0_register(register, sel, value) \ |
557 | do { \ | 557 | do { \ |
558 | if (sel == 0) \ | 558 | if (sel == 0) \ |
559 | __asm__ __volatile__( \ | 559 | __asm__ __volatile__( \ |
560 | "mtc0\t%z0, " #register "\n\t" \ | 560 | "mtc0\t%z0, " #register "\n\t" \ |
561 | : : "Jr" (value)); \ | 561 | : : "Jr" (value)); \ |
562 | else \ | 562 | else \ |
563 | __asm__ __volatile__( \ | 563 | __asm__ __volatile__( \ |
564 | ".set\tmips32\n\t" \ | 564 | ".set\tmips32\n\t" \ |
565 | "mtc0\t%z0, " #register ", " #sel "\n\t" \ | 565 | "mtc0\t%z0, " #register ", " #sel "\n\t" \ |
566 | ".set\tmips0" \ | 566 | ".set\tmips0" \ |
567 | : : "Jr" (value)); \ | 567 | : : "Jr" (value)); \ |
568 | } while (0) | 568 | } while (0) |
569 | 569 | ||
570 | #define __write_64bit_c0_register(register, sel, value) \ | 570 | #define __write_64bit_c0_register(register, sel, value) \ |
571 | do { \ | 571 | do { \ |
572 | if (sel == 0) \ | 572 | if (sel == 0) \ |
573 | __asm__ __volatile__( \ | 573 | __asm__ __volatile__( \ |
574 | ".set\tmips3\n\t" \ | 574 | ".set\tmips3\n\t" \ |
575 | "dmtc0\t%z0, " #register "\n\t" \ | 575 | "dmtc0\t%z0, " #register "\n\t" \ |
576 | ".set\tmips0" \ | 576 | ".set\tmips0" \ |
577 | : : "Jr" (value)); \ | 577 | : : "Jr" (value)); \ |
578 | else \ | 578 | else \ |
579 | __asm__ __volatile__( \ | 579 | __asm__ __volatile__( \ |
580 | ".set\tmips64\n\t" \ | 580 | ".set\tmips64\n\t" \ |
581 | "dmtc0\t%z0, " #register ", " #sel "\n\t" \ | 581 | "dmtc0\t%z0, " #register ", " #sel "\n\t" \ |
582 | ".set\tmips0" \ | 582 | ".set\tmips0" \ |
583 | : : "Jr" (value)); \ | 583 | : : "Jr" (value)); \ |
584 | } while (0) | 584 | } while (0) |
585 | 585 | ||
586 | #define __read_ulong_c0_register(reg, sel) \ | 586 | #define __read_ulong_c0_register(reg, sel) \ |
587 | ((sizeof(unsigned long) == 4) ? \ | 587 | ((sizeof(unsigned long) == 4) ? \ |
588 | __read_32bit_c0_register(reg, sel) : \ | 588 | __read_32bit_c0_register(reg, sel) : \ |
589 | __read_64bit_c0_register(reg, sel)) | 589 | __read_64bit_c0_register(reg, sel)) |
590 | 590 | ||
591 | #define __write_ulong_c0_register(reg, sel, val) \ | 591 | #define __write_ulong_c0_register(reg, sel, val) \ |
592 | do { \ | 592 | do { \ |
593 | if (sizeof(unsigned long) == 4) \ | 593 | if (sizeof(unsigned long) == 4) \ |
594 | __write_32bit_c0_register(reg, sel, val); \ | 594 | __write_32bit_c0_register(reg, sel, val); \ |
595 | else \ | 595 | else \ |
596 | __write_64bit_c0_register(reg, sel, val); \ | 596 | __write_64bit_c0_register(reg, sel, val); \ |
597 | } while (0) | 597 | } while (0) |
598 | 598 | ||
599 | /* | 599 | /* |
600 | * These versions are only needed for systems with more than 38 bits of | 600 | * These versions are only needed for systems with more than 38 bits of |
601 | * physical address space running the 32-bit kernel. That's none atm :-) | 601 | * physical address space running the 32-bit kernel. That's none atm :-) |
602 | */ | 602 | */ |
603 | #define __read_64bit_c0_split(source, sel) \ | 603 | #define __read_64bit_c0_split(source, sel) \ |
604 | ({ \ | 604 | ({ \ |
605 | unsigned long long val; \ | 605 | unsigned long long val; \ |
606 | unsigned long flags; \ | 606 | unsigned long flags; \ |
607 | \ | 607 | \ |
608 | local_irq_save(flags); \ | 608 | local_irq_save(flags); \ |
609 | if (sel == 0) \ | 609 | if (sel == 0) \ |
610 | __asm__ __volatile__( \ | 610 | __asm__ __volatile__( \ |
611 | ".set\tmips64\n\t" \ | 611 | ".set\tmips64\n\t" \ |
612 | "dmfc0\t%M0, " #source "\n\t" \ | 612 | "dmfc0\t%M0, " #source "\n\t" \ |
613 | "dsll\t%L0, %M0, 32\n\t" \ | 613 | "dsll\t%L0, %M0, 32\n\t" \ |
614 | "dsrl\t%M0, %M0, 32\n\t" \ | 614 | "dsrl\t%M0, %M0, 32\n\t" \ |
615 | "dsrl\t%L0, %L0, 32\n\t" \ | 615 | "dsrl\t%L0, %L0, 32\n\t" \ |
616 | ".set\tmips0" \ | 616 | ".set\tmips0" \ |
617 | : "=r" (val)); \ | 617 | : "=r" (val)); \ |
618 | else \ | 618 | else \ |
619 | __asm__ __volatile__( \ | 619 | __asm__ __volatile__( \ |
620 | ".set\tmips64\n\t" \ | 620 | ".set\tmips64\n\t" \ |
621 | "dmfc0\t%M0, " #source ", " #sel "\n\t" \ | 621 | "dmfc0\t%M0, " #source ", " #sel "\n\t" \ |
622 | "dsll\t%L0, %M0, 32\n\t" \ | 622 | "dsll\t%L0, %M0, 32\n\t" \ |
623 | "dsrl\t%M0, %M0, 32\n\t" \ | 623 | "dsrl\t%M0, %M0, 32\n\t" \ |
624 | "dsrl\t%L0, %L0, 32\n\t" \ | 624 | "dsrl\t%L0, %L0, 32\n\t" \ |
625 | ".set\tmips0" \ | 625 | ".set\tmips0" \ |
626 | : "=r" (val)); \ | 626 | : "=r" (val)); \ |
627 | local_irq_restore(flags); \ | 627 | local_irq_restore(flags); \ |
628 | \ | 628 | \ |
629 | val; \ | 629 | val; \ |
630 | }) | 630 | }) |
631 | 631 | ||
632 | #define __write_64bit_c0_split(source, sel, val) \ | 632 | #define __write_64bit_c0_split(source, sel, val) \ |
633 | do { \ | 633 | do { \ |
634 | unsigned long flags; \ | 634 | unsigned long flags; \ |
635 | \ | 635 | \ |
636 | local_irq_save(flags); \ | 636 | local_irq_save(flags); \ |
637 | if (sel == 0) \ | 637 | if (sel == 0) \ |
638 | __asm__ __volatile__( \ | 638 | __asm__ __volatile__( \ |
639 | ".set\tmips64\n\t" \ | 639 | ".set\tmips64\n\t" \ |
640 | "dsll\t%L0, %L0, 32\n\t" \ | 640 | "dsll\t%L0, %L0, 32\n\t" \ |
641 | "dsrl\t%L0, %L0, 32\n\t" \ | 641 | "dsrl\t%L0, %L0, 32\n\t" \ |
642 | "dsll\t%M0, %M0, 32\n\t" \ | 642 | "dsll\t%M0, %M0, 32\n\t" \ |
643 | "or\t%L0, %L0, %M0\n\t" \ | 643 | "or\t%L0, %L0, %M0\n\t" \ |
644 | "dmtc0\t%L0, " #source "\n\t" \ | 644 | "dmtc0\t%L0, " #source "\n\t" \ |
645 | ".set\tmips0" \ | 645 | ".set\tmips0" \ |
646 | : : "r" (val)); \ | 646 | : : "r" (val)); \ |
647 | else \ | 647 | else \ |
648 | __asm__ __volatile__( \ | 648 | __asm__ __volatile__( \ |
649 | ".set\tmips64\n\t" \ | 649 | ".set\tmips64\n\t" \ |
650 | "dsll\t%L0, %L0, 32\n\t" \ | 650 | "dsll\t%L0, %L0, 32\n\t" \ |
651 | "dsrl\t%L0, %L0, 32\n\t" \ | 651 | "dsrl\t%L0, %L0, 32\n\t" \ |
652 | "dsll\t%M0, %M0, 32\n\t" \ | 652 | "dsll\t%M0, %M0, 32\n\t" \ |
653 | "or\t%L0, %L0, %M0\n\t" \ | 653 | "or\t%L0, %L0, %M0\n\t" \ |
654 | "dmtc0\t%L0, " #source ", " #sel "\n\t" \ | 654 | "dmtc0\t%L0, " #source ", " #sel "\n\t" \ |
655 | ".set\tmips0" \ | 655 | ".set\tmips0" \ |
656 | : : "r" (val)); \ | 656 | : : "r" (val)); \ |
657 | local_irq_restore(flags); \ | 657 | local_irq_restore(flags); \ |
658 | } while (0) | 658 | } while (0) |
659 | 659 | ||
660 | #define read_c0_index() __read_32bit_c0_register($0, 0) | 660 | #define read_c0_index() __read_32bit_c0_register($0, 0) |
661 | #define write_c0_index(val) __write_32bit_c0_register($0, 0, val) | 661 | #define write_c0_index(val) __write_32bit_c0_register($0, 0, val) |
662 | 662 | ||
663 | #define read_c0_entrylo0() __read_ulong_c0_register($2, 0) | 663 | #define read_c0_entrylo0() __read_ulong_c0_register($2, 0) |
664 | #define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val) | 664 | #define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val) |
665 | 665 | ||
666 | #define read_c0_entrylo1() __read_ulong_c0_register($3, 0) | 666 | #define read_c0_entrylo1() __read_ulong_c0_register($3, 0) |
667 | #define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val) | 667 | #define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val) |
668 | 668 | ||
669 | #define read_c0_conf() __read_32bit_c0_register($3, 0) | 669 | #define read_c0_conf() __read_32bit_c0_register($3, 0) |
670 | #define write_c0_conf(val) __write_32bit_c0_register($3, 0, val) | 670 | #define write_c0_conf(val) __write_32bit_c0_register($3, 0, val) |
671 | 671 | ||
672 | #define read_c0_context() __read_ulong_c0_register($4, 0) | 672 | #define read_c0_context() __read_ulong_c0_register($4, 0) |
673 | #define write_c0_context(val) __write_ulong_c0_register($4, 0, val) | 673 | #define write_c0_context(val) __write_ulong_c0_register($4, 0, val) |
674 | 674 | ||
675 | #define read_c0_pagemask() __read_32bit_c0_register($5, 0) | 675 | #define read_c0_pagemask() __read_32bit_c0_register($5, 0) |
676 | #define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val) | 676 | #define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val) |
677 | 677 | ||
678 | #define read_c0_wired() __read_32bit_c0_register($6, 0) | 678 | #define read_c0_wired() __read_32bit_c0_register($6, 0) |
679 | #define write_c0_wired(val) __write_32bit_c0_register($6, 0, val) | 679 | #define write_c0_wired(val) __write_32bit_c0_register($6, 0, val) |
680 | 680 | ||
681 | #define read_c0_info() __read_32bit_c0_register($7, 0) | 681 | #define read_c0_info() __read_32bit_c0_register($7, 0) |
682 | 682 | ||
683 | #define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */ | 683 | #define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */ |
684 | #define write_c0_cache(val) __write_32bit_c0_register($7, 0, val) | 684 | #define write_c0_cache(val) __write_32bit_c0_register($7, 0, val) |
685 | 685 | ||
686 | #define read_c0_badvaddr() __read_32bit_c0_register($8, 0) | 686 | #define read_c0_badvaddr() __read_32bit_c0_register($8, 0) |
687 | 687 | ||
688 | #define read_c0_count() __read_32bit_c0_register($9, 0) | 688 | #define read_c0_count() __read_32bit_c0_register($9, 0) |
689 | #define write_c0_count(val) __write_32bit_c0_register($9, 0, val) | 689 | #define write_c0_count(val) __write_32bit_c0_register($9, 0, val) |
690 | 690 | ||
691 | #define read_c0_entryhi() __read_ulong_c0_register($10, 0) | 691 | #define read_c0_entryhi() __read_ulong_c0_register($10, 0) |
692 | #define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val) | 692 | #define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val) |
693 | 693 | ||
694 | #define read_c0_compare() __read_32bit_c0_register($11, 0) | 694 | #define read_c0_compare() __read_32bit_c0_register($11, 0) |
695 | #define write_c0_compare(val) __write_32bit_c0_register($11, 0, val) | 695 | #define write_c0_compare(val) __write_32bit_c0_register($11, 0, val) |
696 | 696 | ||
697 | #define read_c0_status() __read_32bit_c0_register($12, 0) | 697 | #define read_c0_status() __read_32bit_c0_register($12, 0) |
698 | #define write_c0_status(val) __write_32bit_c0_register($12, 0, val) | 698 | #define write_c0_status(val) __write_32bit_c0_register($12, 0, val) |
699 | 699 | ||
700 | #define read_c0_cause() __read_32bit_c0_register($13, 0) | 700 | #define read_c0_cause() __read_32bit_c0_register($13, 0) |
701 | #define write_c0_cause(val) __write_32bit_c0_register($13, 0, val) | 701 | #define write_c0_cause(val) __write_32bit_c0_register($13, 0, val) |
702 | 702 | ||
703 | #define read_c0_prid() __read_32bit_c0_register($15, 0) | 703 | #define read_c0_prid() __read_32bit_c0_register($15, 0) |
704 | 704 | ||
705 | #define read_c0_config() __read_32bit_c0_register($16, 0) | 705 | #define read_c0_config() __read_32bit_c0_register($16, 0) |
706 | #define read_c0_config1() __read_32bit_c0_register($16, 1) | 706 | #define read_c0_config1() __read_32bit_c0_register($16, 1) |
707 | #define read_c0_config2() __read_32bit_c0_register($16, 2) | 707 | #define read_c0_config2() __read_32bit_c0_register($16, 2) |
708 | #define read_c0_config3() __read_32bit_c0_register($16, 3) | 708 | #define read_c0_config3() __read_32bit_c0_register($16, 3) |
709 | #define write_c0_config(val) __write_32bit_c0_register($16, 0, val) | 709 | #define write_c0_config(val) __write_32bit_c0_register($16, 0, val) |
710 | #define write_c0_config1(val) __write_32bit_c0_register($16, 1, val) | 710 | #define write_c0_config1(val) __write_32bit_c0_register($16, 1, val) |
711 | #define write_c0_config2(val) __write_32bit_c0_register($16, 2, val) | 711 | #define write_c0_config2(val) __write_32bit_c0_register($16, 2, val) |
712 | #define write_c0_config3(val) __write_32bit_c0_register($16, 3, val) | 712 | #define write_c0_config3(val) __write_32bit_c0_register($16, 3, val) |
713 | 713 | ||
714 | /* | 714 | /* |
715 | * The WatchLo register. There may be upto 8 of them. | 715 | * The WatchLo register. There may be upto 8 of them. |
716 | */ | 716 | */ |
717 | #define read_c0_watchlo0() __read_ulong_c0_register($18, 0) | 717 | #define read_c0_watchlo0() __read_ulong_c0_register($18, 0) |
718 | #define read_c0_watchlo1() __read_ulong_c0_register($18, 1) | 718 | #define read_c0_watchlo1() __read_ulong_c0_register($18, 1) |
719 | #define read_c0_watchlo2() __read_ulong_c0_register($18, 2) | 719 | #define read_c0_watchlo2() __read_ulong_c0_register($18, 2) |
720 | #define read_c0_watchlo3() __read_ulong_c0_register($18, 3) | 720 | #define read_c0_watchlo3() __read_ulong_c0_register($18, 3) |
721 | #define read_c0_watchlo4() __read_ulong_c0_register($18, 4) | 721 | #define read_c0_watchlo4() __read_ulong_c0_register($18, 4) |
722 | #define read_c0_watchlo5() __read_ulong_c0_register($18, 5) | 722 | #define read_c0_watchlo5() __read_ulong_c0_register($18, 5) |
723 | #define read_c0_watchlo6() __read_ulong_c0_register($18, 6) | 723 | #define read_c0_watchlo6() __read_ulong_c0_register($18, 6) |
724 | #define read_c0_watchlo7() __read_ulong_c0_register($18, 7) | 724 | #define read_c0_watchlo7() __read_ulong_c0_register($18, 7) |
725 | #define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val) | 725 | #define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val) |
726 | #define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val) | 726 | #define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val) |
727 | #define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val) | 727 | #define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val) |
728 | #define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val) | 728 | #define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val) |
729 | #define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val) | 729 | #define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val) |
730 | #define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val) | 730 | #define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val) |
731 | #define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val) | 731 | #define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val) |
732 | #define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val) | 732 | #define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val) |
733 | 733 | ||
734 | /* | 734 | /* |
735 | * The WatchHi register. There may be upto 8 of them. | 735 | * The WatchHi register. There may be upto 8 of them. |
736 | */ | 736 | */ |
737 | #define read_c0_watchhi0() __read_32bit_c0_register($19, 0) | 737 | #define read_c0_watchhi0() __read_32bit_c0_register($19, 0) |
738 | #define read_c0_watchhi1() __read_32bit_c0_register($19, 1) | 738 | #define read_c0_watchhi1() __read_32bit_c0_register($19, 1) |
739 | #define read_c0_watchhi2() __read_32bit_c0_register($19, 2) | 739 | #define read_c0_watchhi2() __read_32bit_c0_register($19, 2) |
740 | #define read_c0_watchhi3() __read_32bit_c0_register($19, 3) | 740 | #define read_c0_watchhi3() __read_32bit_c0_register($19, 3) |
741 | #define read_c0_watchhi4() __read_32bit_c0_register($19, 4) | 741 | #define read_c0_watchhi4() __read_32bit_c0_register($19, 4) |
742 | #define read_c0_watchhi5() __read_32bit_c0_register($19, 5) | 742 | #define read_c0_watchhi5() __read_32bit_c0_register($19, 5) |
743 | #define read_c0_watchhi6() __read_32bit_c0_register($19, 6) | 743 | #define read_c0_watchhi6() __read_32bit_c0_register($19, 6) |
744 | #define read_c0_watchhi7() __read_32bit_c0_register($19, 7) | 744 | #define read_c0_watchhi7() __read_32bit_c0_register($19, 7) |
745 | 745 | ||
746 | #define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val) | 746 | #define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val) |
747 | #define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val) | 747 | #define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val) |
748 | #define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val) | 748 | #define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val) |
749 | #define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val) | 749 | #define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val) |
750 | #define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val) | 750 | #define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val) |
751 | #define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val) | 751 | #define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val) |
752 | #define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val) | 752 | #define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val) |
753 | #define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val) | 753 | #define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val) |
754 | 754 | ||
755 | #define read_c0_xcontext() __read_ulong_c0_register($20, 0) | 755 | #define read_c0_xcontext() __read_ulong_c0_register($20, 0) |
756 | #define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val) | 756 | #define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val) |
757 | 757 | ||
758 | #define read_c0_intcontrol() __read_32bit_c0_register($20, 1) | 758 | #define read_c0_intcontrol() __read_32bit_c0_register($20, 1) |
759 | #define write_c0_intcontrol(val) __write_32bit_c0_register($20, 1, val) | 759 | #define write_c0_intcontrol(val) __write_32bit_c0_register($20, 1, val) |
760 | 760 | ||
761 | #define read_c0_framemask() __read_32bit_c0_register($21, 0) | 761 | #define read_c0_framemask() __read_32bit_c0_register($21, 0) |
762 | #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val) | 762 | #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val) |
763 | 763 | ||
764 | #define read_c0_debug() __read_32bit_c0_register($23, 0) | 764 | #define read_c0_debug() __read_32bit_c0_register($23, 0) |
765 | #define write_c0_debug(val) __write_32bit_c0_register($23, 0, val) | 765 | #define write_c0_debug(val) __write_32bit_c0_register($23, 0, val) |
766 | 766 | ||
767 | #define read_c0_depc() __read_ulong_c0_register($24, 0) | 767 | #define read_c0_depc() __read_ulong_c0_register($24, 0) |
768 | #define write_c0_depc(val) __write_ulong_c0_register($24, 0, val) | 768 | #define write_c0_depc(val) __write_ulong_c0_register($24, 0, val) |
769 | 769 | ||
770 | #define read_c0_ecc() __read_32bit_c0_register($26, 0) | 770 | #define read_c0_ecc() __read_32bit_c0_register($26, 0) |
771 | #define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val) | 771 | #define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val) |
772 | 772 | ||
773 | #define read_c0_derraddr0() __read_ulong_c0_register($26, 1) | 773 | #define read_c0_derraddr0() __read_ulong_c0_register($26, 1) |
774 | #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val) | 774 | #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val) |
775 | 775 | ||
776 | #define read_c0_cacheerr() __read_32bit_c0_register($27, 0) | 776 | #define read_c0_cacheerr() __read_32bit_c0_register($27, 0) |
777 | 777 | ||
778 | #define read_c0_derraddr1() __read_ulong_c0_register($27, 1) | 778 | #define read_c0_derraddr1() __read_ulong_c0_register($27, 1) |
779 | #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val) | 779 | #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val) |
780 | 780 | ||
781 | #define read_c0_taglo() __read_32bit_c0_register($28, 0) | 781 | #define read_c0_taglo() __read_32bit_c0_register($28, 0) |
782 | #define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val) | 782 | #define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val) |
783 | 783 | ||
784 | #define read_c0_taghi() __read_32bit_c0_register($29, 0) | 784 | #define read_c0_taghi() __read_32bit_c0_register($29, 0) |
785 | #define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val) | 785 | #define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val) |
786 | 786 | ||
787 | #define read_c0_errorepc() __read_ulong_c0_register($30, 0) | 787 | #define read_c0_errorepc() __read_ulong_c0_register($30, 0) |
788 | #define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val) | 788 | #define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val) |
789 | 789 | ||
790 | #define read_c0_epc() __read_ulong_c0_register($14, 0) | 790 | #define read_c0_epc() __read_ulong_c0_register($14, 0) |
791 | #define write_c0_epc(val) __write_ulong_c0_register($14, 0, val) | 791 | #define write_c0_epc(val) __write_ulong_c0_register($14, 0, val) |
792 | 792 | ||
793 | #if 1 | 793 | #if 1 |
794 | /* | 794 | /* |
@@ -797,20 +797,20 @@ do { \ | |||
797 | #define read_32bit_cp0_register(source) \ | 797 | #define read_32bit_cp0_register(source) \ |
798 | ({ int __res; \ | 798 | ({ int __res; \ |
799 | __asm__ __volatile__( \ | 799 | __asm__ __volatile__( \ |
800 | ".set\tpush\n\t" \ | 800 | ".set\tpush\n\t" \ |
801 | ".set\treorder\n\t" \ | 801 | ".set\treorder\n\t" \ |
802 | "mfc0\t%0,"STR(source)"\n\t" \ | 802 | "mfc0\t%0,"STR(source)"\n\t" \ |
803 | ".set\tpop" \ | 803 | ".set\tpop" \ |
804 | : "=r" (__res)); \ | 804 | : "=r" (__res)); \ |
805 | __res;}) | 805 | __res;}) |
806 | 806 | ||
807 | #define read_32bit_cp0_set1_register(source) \ | 807 | #define read_32bit_cp0_set1_register(source) \ |
808 | ({ int __res; \ | 808 | ({ int __res; \ |
809 | __asm__ __volatile__( \ | 809 | __asm__ __volatile__( \ |
810 | ".set\tpush\n\t" \ | 810 | ".set\tpush\n\t" \ |
811 | ".set\treorder\n\t" \ | 811 | ".set\treorder\n\t" \ |
812 | "cfc0\t%0,"STR(source)"\n\t" \ | 812 | "cfc0\t%0,"STR(source)"\n\t" \ |
813 | ".set\tpop" \ | 813 | ".set\tpop" \ |
814 | : "=r" (__res)); \ | 814 | : "=r" (__res)); \ |
815 | __res;}) | 815 | __res;}) |
816 | 816 | ||
@@ -828,14 +828,14 @@ do { \ | |||
828 | 828 | ||
829 | #define write_32bit_cp0_register(register,value) \ | 829 | #define write_32bit_cp0_register(register,value) \ |
830 | __asm__ __volatile__( \ | 830 | __asm__ __volatile__( \ |
831 | "mtc0\t%0,"STR(register)"\n\t" \ | 831 | "mtc0\t%0,"STR(register)"\n\t" \ |
832 | "nop" \ | 832 | "nop" \ |
833 | : : "r" (value)); | 833 | : : "r" (value)); |
834 | 834 | ||
835 | #define write_32bit_cp0_set1_register(register,value) \ | 835 | #define write_32bit_cp0_set1_register(register,value) \ |
836 | __asm__ __volatile__( \ | 836 | __asm__ __volatile__( \ |
837 | "ctc0\t%0,"STR(register)"\n\t" \ | 837 | "ctc0\t%0,"STR(register)"\n\t" \ |
838 | "nop" \ | 838 | "nop" \ |
839 | : : "r" (value)); | 839 | : : "r" (value)); |
840 | 840 | ||
841 | #define write_64bit_cp0_register(register,value) \ | 841 | #define write_64bit_cp0_register(register,value) \ |
@@ -851,16 +851,16 @@ do { \ | |||
851 | #define read_mips32_cp0_config1() \ | 851 | #define read_mips32_cp0_config1() \ |
852 | ({ int __res; \ | 852 | ({ int __res; \ |
853 | __asm__ __volatile__( \ | 853 | __asm__ __volatile__( \ |
854 | ".set\tnoreorder\n\t" \ | 854 | ".set\tnoreorder\n\t" \ |
855 | ".set\tnoat\n\t" \ | 855 | ".set\tnoat\n\t" \ |
856 | "#.set\tmips64\n\t" \ | 856 | "#.set\tmips64\n\t" \ |
857 | "#mfc0\t$1, $16, 1\n\t" \ | 857 | "#mfc0\t$1, $16, 1\n\t" \ |
858 | "#.set\tmips0\n\t" \ | 858 | "#.set\tmips0\n\t" \ |
859 | ".word\t0x40018001\n\t" \ | 859 | ".word\t0x40018001\n\t" \ |
860 | "move\t%0,$1\n\t" \ | 860 | "move\t%0,$1\n\t" \ |
861 | ".set\tat\n\t" \ | 861 | ".set\tat\n\t" \ |
862 | ".set\treorder" \ | 862 | ".set\treorder" \ |
863 | :"=r" (__res)); \ | 863 | :"=r" (__res)); \ |
864 | __res;}) | 864 | __res;}) |
865 | 865 | ||
866 | #endif | 866 | #endif |
@@ -869,95 +869,95 @@ do { \ | |||
869 | */ | 869 | */ |
870 | #define read_32bit_cp1_register(source) \ | 870 | #define read_32bit_cp1_register(source) \ |
871 | ({ int __res; \ | 871 | ({ int __res; \ |
872 | __asm__ __volatile__( \ | 872 | __asm__ __volatile__( \ |
873 | ".set\tpush\n\t" \ | 873 | ".set\tpush\n\t" \ |
874 | ".set\treorder\n\t" \ | 874 | ".set\treorder\n\t" \ |
875 | "cfc1\t%0,"STR(source)"\n\t" \ | 875 | "cfc1\t%0,"STR(source)"\n\t" \ |
876 | ".set\tpop" \ | 876 | ".set\tpop" \ |
877 | : "=r" (__res)); \ | 877 | : "=r" (__res)); \ |
878 | __res;}) | 878 | __res;}) |
879 | 879 | ||
880 | /* TLB operations. */ | 880 | /* TLB operations. */ |
881 | static inline void tlb_probe(void) | 881 | static inline void tlb_probe(void) |
882 | { | 882 | { |
883 | __asm__ __volatile__( | 883 | __asm__ __volatile__( |
884 | ".set noreorder\n\t" | 884 | ".set noreorder\n\t" |
885 | "tlbp\n\t" | 885 | "tlbp\n\t" |
886 | ".set reorder"); | 886 | ".set reorder"); |
887 | } | 887 | } |
888 | 888 | ||
889 | static inline void tlb_read(void) | 889 | static inline void tlb_read(void) |
890 | { | 890 | { |
891 | __asm__ __volatile__( | 891 | __asm__ __volatile__( |
892 | ".set noreorder\n\t" | 892 | ".set noreorder\n\t" |
893 | "tlbr\n\t" | 893 | "tlbr\n\t" |
894 | ".set reorder"); | 894 | ".set reorder"); |
895 | } | 895 | } |
896 | 896 | ||
897 | static inline void tlb_write_indexed(void) | 897 | static inline void tlb_write_indexed(void) |
898 | { | 898 | { |
899 | __asm__ __volatile__( | 899 | __asm__ __volatile__( |
900 | ".set noreorder\n\t" | 900 | ".set noreorder\n\t" |
901 | "tlbwi\n\t" | 901 | "tlbwi\n\t" |
902 | ".set reorder"); | 902 | ".set reorder"); |
903 | } | 903 | } |
904 | 904 | ||
905 | static inline void tlb_write_random(void) | 905 | static inline void tlb_write_random(void) |
906 | { | 906 | { |
907 | __asm__ __volatile__( | 907 | __asm__ __volatile__( |
908 | ".set noreorder\n\t" | 908 | ".set noreorder\n\t" |
909 | "tlbwr\n\t" | 909 | "tlbwr\n\t" |
910 | ".set reorder"); | 910 | ".set reorder"); |
911 | } | 911 | } |
912 | 912 | ||
913 | /* | 913 | /* |
914 | * Manipulate bits in a c0 register. | 914 | * Manipulate bits in a c0 register. |
915 | */ | 915 | */ |
916 | #define __BUILD_SET_C0(name,register) \ | 916 | #define __BUILD_SET_C0(name,register) \ |
917 | static inline unsigned int \ | 917 | static inline unsigned int \ |
918 | set_c0_##name(unsigned int set) \ | 918 | set_c0_##name(unsigned int set) \ |
919 | { \ | 919 | { \ |
920 | unsigned int res; \ | 920 | unsigned int res; \ |
921 | \ | 921 | \ |
922 | res = read_c0_##name(); \ | 922 | res = read_c0_##name(); \ |
923 | res |= set; \ | 923 | res |= set; \ |
924 | write_c0_##name(res); \ | 924 | write_c0_##name(res); \ |
925 | \ | 925 | \ |
926 | return res; \ | 926 | return res; \ |
927 | } \ | 927 | } \ |
928 | \ | 928 | \ |
929 | static inline unsigned int \ | 929 | static inline unsigned int \ |
930 | clear_c0_##name(unsigned int clear) \ | 930 | clear_c0_##name(unsigned int clear) \ |
931 | { \ | 931 | { \ |
932 | unsigned int res; \ | 932 | unsigned int res; \ |
933 | \ | 933 | \ |
934 | res = read_c0_##name(); \ | 934 | res = read_c0_##name(); \ |
935 | res &= ~clear; \ | 935 | res &= ~clear; \ |
936 | write_c0_##name(res); \ | 936 | write_c0_##name(res); \ |
937 | \ | 937 | \ |
938 | return res; \ | 938 | return res; \ |
939 | } \ | 939 | } \ |
940 | \ | 940 | \ |
941 | static inline unsigned int \ | 941 | static inline unsigned int \ |
942 | change_c0_##name(unsigned int change, unsigned int new) \ | 942 | change_c0_##name(unsigned int change, unsigned int new) \ |
943 | { \ | 943 | { \ |
944 | unsigned int res; \ | 944 | unsigned int res; \ |
945 | \ | 945 | \ |
946 | res = read_c0_##name(); \ | 946 | res = read_c0_##name(); \ |
947 | res &= ~change; \ | 947 | res &= ~change; \ |
948 | res |= (new & change); \ | 948 | res |= (new & change); \ |
949 | write_c0_##name(res); \ | 949 | write_c0_##name(res); \ |
950 | \ | 950 | \ |
951 | return res; \ | 951 | return res; \ |
952 | } | 952 | } |
953 | 953 | ||
954 | __BUILD_SET_C0(status,CP0_STATUS) | 954 | __BUILD_SET_C0(status,CP0_STATUS) |
955 | __BUILD_SET_C0(cause,CP0_CAUSE) | 955 | __BUILD_SET_C0(cause,CP0_CAUSE) |
956 | __BUILD_SET_C0(config,CP0_CONFIG) | 956 | __BUILD_SET_C0(config,CP0_CONFIG) |
957 | 957 | ||
958 | #define set_cp0_status(x) set_c0_status(x) | 958 | #define set_cp0_status(x) set_c0_status(x) |
959 | #define set_cp0_cause(x) set_c0_cause(x) | 959 | #define set_cp0_cause(x) set_c0_cause(x) |
960 | #define set_cp0_config(x) set_c0_config(x) | 960 | #define set_cp0_config(x) set_c0_config(x) |
961 | 961 | ||
962 | #endif /* !__ASSEMBLY__ */ | 962 | #endif /* !__ASSEMBLY__ */ |
963 | 963 | ||