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authorMaurus Cuelenaere <mcuelenaere@gmail.com>2009-02-16 22:49:58 +0000
committerMaurus Cuelenaere <mcuelenaere@gmail.com>2009-02-16 22:49:58 +0000
commit360d3d720b87f2029c399a468294838a71181f64 (patch)
treefec2a00b06d17c4fe8395757ab3df8399abf0972
parent67a5c56103f5f57d778be90a6babdf5726295bfd (diff)
downloadrockbox-360d3d720b87f2029c399a468294838a71181f64.tar.gz
rockbox-360d3d720b87f2029c399a468294838a71181f64.zip
Onda VX747:
* Rework battery reading * Get power off back working * Add time to debug view * Convert TABs to spaces in firmware/export/mips*.h git-svn-id: svn://svn.rockbox.org/rockbox/trunk@20024 a1c6a512-1295-4272-9138-f99709370657
Diffstat
-rw-r--r--firmware/export/config-ondavx747.h14
-rw-r--r--firmware/export/mips-archdefs.h2322
-rw-r--r--firmware/export/mips.h990
-rw-r--r--firmware/export/mipsregs.h1068
-rw-r--r--firmware/target/mips/ingenic_jz47xx/debug-jz4740.c6
-rw-r--r--firmware/target/mips/ingenic_jz47xx/onda_vx747/sadc-onda_vx747.c27
-rw-r--r--firmware/target/mips/ingenic_jz47xx/system-jz4740.c3
7 files changed, 2216 insertions, 2214 deletions
diff --git a/firmware/export/config-ondavx747.h b/firmware/export/config-ondavx747.h
index a7df97068c..a5e22aaf26 100644
--- a/firmware/export/config-ondavx747.h
+++ b/firmware/export/config-ondavx747.h
@@ -85,9 +85,14 @@
85 85
86/* Define this for LCD backlight available */ 86/* Define this for LCD backlight available */
87#define HAVE_BACKLIGHT 87#define HAVE_BACKLIGHT
88
89#define HAVE_BACKLIGHT_BRIGHTNESS 88#define HAVE_BACKLIGHT_BRIGHTNESS
90 89
90/* define this if the backlight can be set to a brightness */
91#define __BACKLIGHT_INIT
92
93/* Which backlight fading type? */
94//#define CONFIG_BACKLIGHT_FADING BACKLIGHT_FADING_PWM
95
91/* Main LCD backlight brightness range and defaults */ 96/* Main LCD backlight brightness range and defaults */
92#define MIN_BRIGHTNESS_SETTING 100 97#define MIN_BRIGHTNESS_SETTING 100
93#define MAX_BRIGHTNESS_SETTING 300 98#define MAX_BRIGHTNESS_SETTING 300
@@ -95,7 +100,7 @@
95#define DEFAULT_DIMNESS_SETTING 100 /* "most dim" */ 100#define DEFAULT_DIMNESS_SETTING 100 /* "most dim" */
96 101
97/* Define this if you have a software controlled poweroff */ 102/* Define this if you have a software controlled poweroff */
98//#define HAVE_SW_POWEROFF 103#define HAVE_SW_POWEROFF
99 104
100/* The number of bytes reserved for loadable codecs */ 105/* The number of bytes reserved for loadable codecs */
101#define CODEC_SIZE 0x100000 106#define CODEC_SIZE 0x100000
@@ -108,7 +113,7 @@
108 113
109#define CONFIG_I2C I2C_JZ47XX 114#define CONFIG_I2C I2C_JZ47XX
110 115
111/* TLV320 has no tone controls, so we use the software ones */ 116/* has no tone controls, so we use the software ones */
112//#define HAVE_SW_TONE_CONTROLS 117//#define HAVE_SW_TONE_CONTROLS
113 118
114/*#define HW_SAMPR_CAPS (SAMPR_CAP_88 | SAMPR_CAP_44 | SAMPR_CAP_22 | \ 119/*#define HW_SAMPR_CAPS (SAMPR_CAP_88 | SAMPR_CAP_44 | SAMPR_CAP_22 | \
@@ -141,9 +146,6 @@
141/* Virtual LED (icon) */ 146/* Virtual LED (icon) */
142#define CONFIG_LED LED_VIRTUAL 147#define CONFIG_LED LED_VIRTUAL
143 148
144/* define this if the backlight can be set to a brightness */
145#define __BACKLIGHT_INIT
146
147/* Offset ( in the firmware file's header ) to the file CRC */ 149/* Offset ( in the firmware file's header ) to the file CRC */
148#define FIRMWARE_OFFSET_FILE_CRC 0 150#define FIRMWARE_OFFSET_FILE_CRC 0
149 151
diff --git a/firmware/export/mips-archdefs.h b/firmware/export/mips-archdefs.h
index 4bf39c81a9..5b13a81a46 100644
--- a/firmware/export/mips-archdefs.h
+++ b/firmware/export/mips-archdefs.h
@@ -89,24 +89,24 @@
89 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 89 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
90 */ 90 */
91 91
92#define S_InstnOpcode 26 92#define S_InstnOpcode 26
93#define M_InstnOpcode (0x3f << S_InstnOpcode) 93#define M_InstnOpcode (0x3f << S_InstnOpcode)
94#define S_InstnRS 21 94#define S_InstnRS 21
95#define M_InstnRS (0x1f << S_InstnRS) 95#define M_InstnRS (0x1f << S_InstnRS)
96#define S_InstnRT 16 96#define S_InstnRT 16
97#define M_InstnRT (0x1f << S_InstnRT) 97#define M_InstnRT (0x1f << S_InstnRT)
98#define S_InstnRD 11 98#define S_InstnRD 11
99#define M_InstnRD (0x1f << S_InstnRD) 99#define M_InstnRD (0x1f << S_InstnRD)
100#define S_InstnSA 6 100#define S_InstnSA 6
101#define M_InstnSA (0x1f << S_InstnSA) 101#define M_InstnSA (0x1f << S_InstnSA)
102#define S_InstnTcode 6 102#define S_InstnTcode 6
103#define M_InstnTcode (0x3ff << S_InstnTcode) 103#define M_InstnTcode (0x3ff << S_InstnTcode)
104#define S_InstnBcode 6 104#define S_InstnBcode 6
105#define M_InstnBcode (0xfffff << S_InstnBcode) 105#define M_InstnBcode (0xfffff << S_InstnBcode)
106#define S_InstnFunc 0 106#define S_InstnFunc 0
107#define M_InstnFunc (0x3f << S_InstnFunc) 107#define M_InstnFunc (0x3f << S_InstnFunc)
108#define S_InstnSel 0 108#define S_InstnSel 0
109#define M_InstnSel (0x7 << S_InstnSel) 109#define M_InstnSel (0x7 << S_InstnSel)
110 110
111/* 111/*
112 * I-Type (load, store, branch, immediate) 112 * I-Type (load, store, branch, immediate)
@@ -118,8 +118,8 @@
118 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 118 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
119 */ 119 */
120 120
121#define S_InstnOffset 0 121#define S_InstnOffset 0
122#define M_InstnOffset (0xffff << S_InstnOffset) 122#define M_InstnOffset (0xffff << S_InstnOffset)
123 123
124/* 124/*
125 * I-Type (pref) 125 * I-Type (pref)
@@ -131,8 +131,8 @@
131 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 131 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
132 */ 132 */
133 133
134#define S_InstnHint S_InstnRT 134#define S_InstnHint S_InstnRT
135#define M_InstnHint M_InstnRT 135#define M_InstnHint M_InstnRT
136 136
137/* 137/*
138 * J-Type (jump) 138 * J-Type (jump)
@@ -144,8 +144,8 @@
144 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 144 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
145 */ 145 */
146 146
147#define S_InstnJIndex 0 147#define S_InstnJIndex 0
148#define M_InstnJIndex (0x03ffffff << S_InstnJIndex) 148#define M_InstnJIndex (0x03ffffff << S_InstnJIndex)
149 149
150/* 150/*
151 * FP R-Type (operate) 151 * FP R-Type (operate)
@@ -157,14 +157,14 @@
157 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 157 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
158 */ 158 */
159 159
160#define S_InstnFmt S_InstnRS 160#define S_InstnFmt S_InstnRS
161#define M_InstnFmt M_InstnRS 161#define M_InstnFmt M_InstnRS
162#define S_InstnFT S_InstnRT 162#define S_InstnFT S_InstnRT
163#define M_InstnFT M_InstnRT 163#define M_InstnFT M_InstnRT
164#define S_InstnFS S_InstnRD 164#define S_InstnFS S_InstnRD
165#define M_InstnFS M_InstnRD 165#define M_InstnFS M_InstnRD
166#define S_InstnFD S_InstnSA 166#define S_InstnFD S_InstnSA
167#define M_InstnFD M_InstnSA 167#define M_InstnFD M_InstnSA
168 168
169/* 169/*
170 * FP R-Type (cpu <-> cpu data movement)) 170 * FP R-Type (cpu <-> cpu data movement))
@@ -176,8 +176,8 @@
176 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 176 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
177 */ 177 */
178 178
179#define S_InstnSub S_InstnRS 179#define S_InstnSub S_InstnRS
180#define M_InstnSub M_InstnRS 180#define M_InstnSub M_InstnRS
181 181
182/* 182/*
183 * FP R-Type (compare) 183 * FP R-Type (compare)
@@ -191,10 +191,10 @@
191 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 191 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
192 */ 192 */
193 193
194#define S_InstnCCcmp 8 194#define S_InstnCCcmp 8
195#define M_InstnCCcmp (0x7 << S_InstnCCcmp) 195#define M_InstnCCcmp (0x7 << S_InstnCCcmp)
196#define S_InstnCABS 6 196#define S_InstnCABS 6
197#define M_InstnCABS (0x1 << S_InstnCABS) 197#define M_InstnCABS (0x1 << S_InstnCABS)
198 198
199/* 199/*
200 * FP R-Type (FPR conditional move on FP cc) 200 * FP R-Type (FPR conditional move on FP cc)
@@ -207,12 +207,12 @@
207 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 207 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
208 */ 208 */
209 209
210#define S_InstnCC 18 210#define S_InstnCC 18
211#define M_InstnCC (0x7 << S_InstnCC) 211#define M_InstnCC (0x7 << S_InstnCC)
212#define S_InstnND 17 212#define S_InstnND 17
213#define M_InstnND (0x1 << S_InstnND) 213#define M_InstnND (0x1 << S_InstnND)
214#define S_InstnTF 16 214#define S_InstnTF 16
215#define M_InstnTF (0x1 << S_InstnTF) 215#define M_InstnTF (0x1 << S_InstnTF)
216 216
217/* 217/*
218 * FP R-Type (3-operand operate) 218 * FP R-Type (3-operand operate)
@@ -224,12 +224,12 @@
224 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 224 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
225 */ 225 */
226 226
227#define S_InstnFR S_InstnRS 227#define S_InstnFR S_InstnRS
228#define M_InstnFR M_InstnRS 228#define M_InstnFR M_InstnRS
229#define S_InstnOp4 3 229#define S_InstnOp4 3
230#define M_InstnOp4 (0x7 << S_InstnOp4) 230#define M_InstnOp4 (0x7 << S_InstnOp4)
231#define S_InstnFmt3 0 231#define S_InstnFmt3 0
232#define M_InstnFmt3 (0x7 << S_InstnFmt3) 232#define M_InstnFmt3 (0x7 << S_InstnFmt3)
233 233
234/* 234/*
235 * FP R-Type (Indexed load, store) 235 * FP R-Type (Indexed load, store)
@@ -250,8 +250,8 @@
250 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 250 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
251 */ 251 */
252 252
253#define S_InstnHintX S_InstnRD 253#define S_InstnHintX S_InstnRD
254#define M_InstnHintX M_InstnRD 254#define M_InstnHintX M_InstnRD
255 255
256/* 256/*
257 * FP R-Type (GPR conditional move on FP cc) 257 * FP R-Type (GPR conditional move on FP cc)
@@ -293,19 +293,19 @@
293 */ 293 */
294 294
295#ifdef MIPSADDR64 295#ifdef MIPSADDR64
296#define A_K0BASE UNS64Const(0xffffffff80000000) 296#define A_K0BASE UNS64Const(0xffffffff80000000)
297#define A_K1BASE UNS64Const(0xffffffffa0000000) 297#define A_K1BASE UNS64Const(0xffffffffa0000000)
298#define A_K2BASE UNS64Const(0xffffffffc0000000) 298#define A_K2BASE UNS64Const(0xffffffffc0000000)
299#define A_K3BASE UNS64Const(0xffffffffe0000000) 299#define A_K3BASE UNS64Const(0xffffffffe0000000)
300#define A_REGION UNS64Const(0xc000000000000000) 300#define A_REGION UNS64Const(0xc000000000000000)
301#define A_XKPHYS_ATTR UNS64Const(0x3800000000000000) 301#define A_XKPHYS_ATTR UNS64Const(0x3800000000000000)
302#else 302#else
303#define A_K0BASE 0x80000000 303#define A_K0BASE 0x80000000
304#define A_K1BASE 0xa0000000 304#define A_K1BASE 0xa0000000
305#define A_K2BASE 0xc0000000 305#define A_K2BASE 0xc0000000
306#define A_K3BASE 0xe0000000 306#define A_K3BASE 0xe0000000
307#endif 307#endif
308#define M_KMAPPED 0x40000000 /* KnSEG address is mapped if bit is one */ 308#define M_KMAPPED 0x40000000 /* KnSEG address is mapped if bit is one */
309 309
310 310
311#ifdef MIPS_Model64 311#ifdef MIPS_Model64
@@ -406,41 +406,41 @@
406/* 406/*
407 * Cache encodings 407 * Cache encodings
408 */ 408 */
409#define K_CachePriI 0 /* Primary Icache */ 409#define K_CachePriI 0 /* Primary Icache */
410#define K_CachePriD 1 /* Primary Dcache */ 410#define K_CachePriD 1 /* Primary Dcache */
411#define K_CachePriU 1 /* Unified primary */ 411#define K_CachePriU 1 /* Unified primary */
412#define K_CacheTerU 2 /* Unified Tertiary */ 412#define K_CacheTerU 2 /* Unified Tertiary */
413#define K_CacheSecU 3 /* Unified secondary */ 413#define K_CacheSecU 3 /* Unified secondary */
414 414
415 415
416/* 416/*
417 * Function encodings 417 * Function encodings
418 */ 418 */
419#define S_CacheFunc 2 /* Amount to shift function encoding within 5-bit field */ 419#define S_CacheFunc 2 /* Amount to shift function encoding within 5-bit field */
420#define K_CacheIndexInv 0 /* Index invalidate */ 420#define K_CacheIndexInv 0 /* Index invalidate */
421#define K_CacheIndexWBInv 0 /* Index writeback invalidate */ 421#define K_CacheIndexWBInv 0 /* Index writeback invalidate */
422#define K_CacheIndexLdTag 1 /* Index load tag */ 422#define K_CacheIndexLdTag 1 /* Index load tag */
423#define K_CacheIndexStTag 2 /* Index store tag */ 423#define K_CacheIndexStTag 2 /* Index store tag */
424#define K_CacheHitInv 4 /* Hit Invalidate */ 424#define K_CacheHitInv 4 /* Hit Invalidate */
425#define K_CacheFill 5 /* Fill (Icache only) */ 425#define K_CacheFill 5 /* Fill (Icache only) */
426#define K_CacheHitWBInv 5 /* Hit writeback invalidate */ 426#define K_CacheHitWBInv 5 /* Hit writeback invalidate */
427#define K_CacheHitWB 6 /* Hit writeback */ 427#define K_CacheHitWB 6 /* Hit writeback */
428#define K_CacheFetchLock 7 /* Fetch and lock */ 428#define K_CacheFetchLock 7 /* Fetch and lock */
429 429
430#define ICIndexInv ((K_CacheIndexInv << S_CacheFunc) | K_CachePriI) 430#define ICIndexInv ((K_CacheIndexInv << S_CacheFunc) | K_CachePriI)
431#define DCIndexWBInv ((K_CacheIndexWBInv << S_CacheFunc) | K_CachePriD) 431#define DCIndexWBInv ((K_CacheIndexWBInv << S_CacheFunc) | K_CachePriD)
432#define DCIndexInv DCIndexWBInv 432#define DCIndexInv DCIndexWBInv
433#define ICIndexLdTag ((K_CacheIndexLdTag << S_CacheFunc) | K_CachePriI) 433#define ICIndexLdTag ((K_CacheIndexLdTag << S_CacheFunc) | K_CachePriI)
434#define DCIndexLdTag ((K_CacheIndexLdTag << S_CacheFunc) | K_CachePriD) 434#define DCIndexLdTag ((K_CacheIndexLdTag << S_CacheFunc) | K_CachePriD)
435#define ICIndexStTag ((K_CacheIndexStTag << S_CacheFunc) | K_CachePriI) 435#define ICIndexStTag ((K_CacheIndexStTag << S_CacheFunc) | K_CachePriI)
436#define DCIndexStTag ((K_CacheIndexStTag << S_CacheFunc) | K_CachePriD) 436#define DCIndexStTag ((K_CacheIndexStTag << S_CacheFunc) | K_CachePriD)
437#define ICHitInv ((K_CacheHitInv << S_CacheFunc) | K_CachePriI) 437#define ICHitInv ((K_CacheHitInv << S_CacheFunc) | K_CachePriI)
438#define DCHitInv ((K_CacheHitInv << S_CacheFunc) | K_CachePriD) 438#define DCHitInv ((K_CacheHitInv << S_CacheFunc) | K_CachePriD)
439#define ICFill ((K_CacheFill << S_CacheFunc) | K_CachePriI) 439#define ICFill ((K_CacheFill << S_CacheFunc) | K_CachePriI)
440#define DCHitWBInv ((K_CacheHitWBInv << S_CacheFunc) | K_CachePriD) 440#define DCHitWBInv ((K_CacheHitWBInv << S_CacheFunc) | K_CachePriD)
441#define DCHitWB ((K_CacheHitWB << S_CacheFunc) | K_CachePriD) 441#define DCHitWB ((K_CacheHitWB << S_CacheFunc) | K_CachePriD)
442#define ICFetchLock ((K_CacheFetchLock << S_CacheFunc) | K_CachePriI) 442#define ICFetchLock ((K_CacheFetchLock << S_CacheFunc) | K_CachePriI)
443#define DCFetchLock ((K_CacheFetchLock << S_CacheFunc) | K_CachePriD) 443#define DCFetchLock ((K_CacheFetchLock << S_CacheFunc) | K_CachePriD)
444 444
445 445
446/* 446/*
@@ -449,14 +449,14 @@
449 ************************************************************************* 449 *************************************************************************
450 */ 450 */
451 451
452#define PrefLoad 0 452#define PrefLoad 0
453#define PrefStore 1 453#define PrefStore 1
454#define PrefLoadStreamed 4 454#define PrefLoadStreamed 4
455#define PrefStoreStreamed 5 455#define PrefStoreStreamed 5
456#define PrefLoadRetained 6 456#define PrefLoadRetained 6
457#define PrefStoreRetained 7 457#define PrefStoreRetained 7
458#define PrefWBInval 25 458#define PrefWBInval 25
459#define PrefNudge 25 459#define PrefNudge 25
460 460
461 461
462/* 462/*
@@ -472,38 +472,38 @@
472 ************************************************************************* 472 *************************************************************************
473 */ 473 */
474 474
475#define zero $0 475#define zero $0
476#define AT $1 476#define AT $1
477#define v0 $2 477#define v0 $2
478#define v1 $3 478#define v1 $3
479#define a0 $4 479#define a0 $4
480#define a1 $5 480#define a1 $5
481#define a2 $6 481#define a2 $6
482#define a3 $7 482#define a3 $7
483#define t0 $8 483#define t0 $8
484#define t1 $9 484#define t1 $9
485#define t2 $10 485#define t2 $10
486#define t3 $11 486#define t3 $11
487#define t4 $12 487#define t4 $12
488#define t5 $13 488#define t5 $13
489#define t6 $14 489#define t6 $14
490#define t7 $15 490#define t7 $15
491#define s0 $16 491#define s0 $16
492#define s1 $17 492#define s1 $17
493#define s2 $18 493#define s2 $18
494#define s3 $19 494#define s3 $19
495#define s4 $20 495#define s4 $20
496#define s5 $21 496#define s5 $21
497#define s6 $22 497#define s6 $22
498#define s7 $23 498#define s7 $23
499#define t8 $24 499#define t8 $24
500#define t9 $25 500#define t9 $25
501#define k0 $26 501#define k0 $26
502#define k1 $27 502#define k1 $27
503#define gp $28 503#define gp $28
504#define sp $29 504#define sp $29
505#define fp $30 505#define fp $30
506#define ra $31 506#define ra $31
507 507
508/* 508/*
509 * The following registers are used by the AVP environment and 509 * The following registers are used by the AVP environment and
@@ -511,8 +511,8 @@
511 */ 511 */
512 512
513#ifdef MIPSAVPENV 513#ifdef MIPSAVPENV
514#define repc $25 /* Expected exception PC */ 514#define repc $25 /* Expected exception PC */
515#define tid $30 /* Current test case address */ 515#define tid $30 /* Current test case address */
516#endif 516#endif
517 517
518 518
@@ -526,53 +526,53 @@
526 * Removing them causes assembly rather than runtime errors for tests that 526 * Removing them causes assembly rather than runtime errors for tests that
527 * use the `r' names. 527 * use the `r' names.
528 * 528 *
529 * - r25 (repc) is used as the expected PC on an exception 529 * - r25 (repc) is used as the expected PC on an exception
530 * - r26-r27 (k0, k1) are used in the exception handler 530 * - r26-r27 (k0, k1) are used in the exception handler
531 * - r30 (tid) is used as the current test address 531 * - r30 (tid) is used as the current test address
532 */ 532 */
533 533
534#define r0 $0 534#define r0 $0
535#define r1 $1 535#define r1 $1
536#define r2 $2 536#define r2 $2
537#define r3 $3 537#define r3 $3
538#define r4 $4 538#define r4 $4
539#define r5 $5 539#define r5 $5
540#define r6 $6 540#define r6 $6
541#define r7 $7 541#define r7 $7
542#define r8 $8 542#define r8 $8
543#define r9 $9 543#define r9 $9
544#define r10 $10 544#define r10 $10
545#define r11 $11 545#define r11 $11
546#define r12 $12 546#define r12 $12
547#define r13 $13 547#define r13 $13
548#define r14 $14 548#define r14 $14
549#define r15 $15 549#define r15 $15
550#define r16 $16 550#define r16 $16
551#define r17 $17 551#define r17 $17
552#define r18 $18 552#define r18 $18
553#define r19 $19 553#define r19 $19
554#define r20 $20 554#define r20 $20
555#define r21 $21 555#define r21 $21
556#define r22 $22 556#define r22 $22
557#define r23 $23 557#define r23 $23
558#define r24 $24 558#define r24 $24
559#ifdef MIPSAVPENV 559#ifdef MIPSAVPENV
560#define r25 r25_unknown 560#define r25 r25_unknown
561#define r26 r26_unknown 561#define r26 r26_unknown
562#define r27 r27_unknown 562#define r27 r27_unknown
563#else 563#else
564#define r25 $25 564#define r25 $25
565#define r26 $26 565#define r26 $26
566#define r27 $27 566#define r27 $27
567#endif 567#endif
568#define r28 $28 568#define r28 $28
569#define r29 $29 569#define r29 $29
570#ifdef MIPSAVPENV 570#ifdef MIPSAVPENV
571#define r30 r30_unknown 571#define r30 r30_unknown
572#else 572#else
573#define r30 $30 573#define r30 $30
574#endif 574#endif
575#define r31 $31 575#define r31 $31
576 576
577 577
578/* 578/*
@@ -584,40 +584,40 @@
584 * to the assembler register name ($n). 584 * to the assembler register name ($n).
585 */ 585 */
586 586
587#define R_r0 0 587#define R_r0 0
588#define R_r1 1 588#define R_r1 1
589#define R_r2 2 589#define R_r2 2
590#define R_r3 3 590#define R_r3 3
591#define R_r4 4 591#define R_r4 4
592#define R_r5 5 592#define R_r5 5
593#define R_r6 6 593#define R_r6 6
594#define R_r7 7 594#define R_r7 7
595#define R_r8 8 595#define R_r8 8
596#define R_r9 9 596#define R_r9 9
597#define R_r10 10 597#define R_r10 10
598#define R_r11 11 598#define R_r11 11
599#define R_r12 12 599#define R_r12 12
600#define R_r13 13 600#define R_r13 13
601#define R_r14 14 601#define R_r14 14
602#define R_r15 15 602#define R_r15 15
603#define R_r16 16 603#define R_r16 16
604#define R_r17 17 604#define R_r17 17
605#define R_r18 18 605#define R_r18 18
606#define R_r19 19 606#define R_r19 19
607#define R_r20 20 607#define R_r20 20
608#define R_r21 21 608#define R_r21 21
609#define R_r22 22 609#define R_r22 22
610#define R_r23 23 610#define R_r23 23
611#define R_r24 24 611#define R_r24 24
612#define R_r25 25 612#define R_r25 25
613#define R_r26 26 613#define R_r26 26
614#define R_r27 27 614#define R_r27 27
615#define R_r28 28 615#define R_r28 28
616#define R_r29 29 616#define R_r29 29
617#define R_r30 30 617#define R_r30 30
618#define R_r31 31 618#define R_r31 31
619#define R_hi 32 /* Hi register */ 619#define R_hi 32 /* Hi register */
620#define R_lo 33 /* Lo register */ 620#define R_lo 33 /* Lo register */
621 621
622 622
623/* 623/*
@@ -628,37 +628,37 @@
628 * These definitions provide the bit mask corresponding to the GPR number 628 * These definitions provide the bit mask corresponding to the GPR number
629 */ 629 */
630 630
631#define M_AT (1<<1) 631#define M_AT (1<<1)
632#define M_v0 (1<<2) 632#define M_v0 (1<<2)
633#define M_v1 (1<<3) 633#define M_v1 (1<<3)
634#define M_a0 (1<<4) 634#define M_a0 (1<<4)
635#define M_a1 (1<<5) 635#define M_a1 (1<<5)
636#define M_a2 (1<<6) 636#define M_a2 (1<<6)
637#define M_a3 (1<<7) 637#define M_a3 (1<<7)
638#define M_t0 (1<<8) 638#define M_t0 (1<<8)
639#define M_t1 (1<<9) 639#define M_t1 (1<<9)
640#define M_t2 (1<<10) 640#define M_t2 (1<<10)
641#define M_t3 (1<<11) 641#define M_t3 (1<<11)
642#define M_t4 (1<<12) 642#define M_t4 (1<<12)
643#define M_t5 (1<<13) 643#define M_t5 (1<<13)
644#define M_t6 (1<<14) 644#define M_t6 (1<<14)
645#define M_t7 (1<<15) 645#define M_t7 (1<<15)
646#define M_s0 (1<<16) 646#define M_s0 (1<<16)
647#define M_s1 (1<<17) 647#define M_s1 (1<<17)
648#define M_s2 (1<<18) 648#define M_s2 (1<<18)
649#define M_s3 (1<<19) 649#define M_s3 (1<<19)
650#define M_s4 (1<<20) 650#define M_s4 (1<<20)
651#define M_s5 (1<<21) 651#define M_s5 (1<<21)
652#define M_s6 (1<<22) 652#define M_s6 (1<<22)
653#define M_s7 (1<<23) 653#define M_s7 (1<<23)
654#define M_t8 (1<<24) 654#define M_t8 (1<<24)
655#define M_t9 (1<<25) 655#define M_t9 (1<<25)
656#define M_k0 (1<<26) 656#define M_k0 (1<<26)
657#define M_k1 (1<<27) 657#define M_k1 (1<<27)
658#define M_gp (1<<28) 658#define M_gp (1<<28)
659#define M_sp (1<<29) 659#define M_sp (1<<29)
660#define M_fp (1<<30) 660#define M_fp (1<<30)
661#define M_ra (1<<31) 661#define M_ra (1<<31)
662 662
663 663
664/* 664/*
@@ -667,16 +667,16 @@
667 ************************************************************************* 667 *************************************************************************
668 * Each register has the following definitions: 668 * Each register has the following definitions:
669 * 669 *
670 * C0_rrr The register number (as a $n value) 670 * C0_rrr The register number (as a $n value)
671 * R_C0_rrr The register index (as an integer corresponding 671 * R_C0_rrr The register index (as an integer corresponding
672 * to the register number) 672 * to the register number)
673 * 673 *
674 * Each field in a register has the following definitions: 674 * Each field in a register has the following definitions:
675 * 675 *
676 * S_rrrfff The shift count required to right-justify 676 * S_rrrfff The shift count required to right-justify
677 * the field. This corresponds to the bit 677 * the field. This corresponds to the bit
678 * number of the right-most bit in the field. 678 * number of the right-most bit in the field.
679 * M_rrrfff The Mask required to isolate the field. 679 * M_rrrfff The Mask required to isolate the field.
680 * 680 *
681 * Register diagrams included below as comments correspond to the 681 * Register diagrams included below as comments correspond to the
682 * MIPS32 and MIPS64 architecture specifications. Refer to other 682 * MIPS32 and MIPS64 architecture specifications. Refer to other
@@ -688,7 +688,7 @@
688 ************************************************************************ 688 ************************************************************************
689 * I N D E X R E G I S T E R ( 0 ) * 689 * I N D E X R E G I S T E R ( 0 ) *
690 ************************************************************************ 690 ************************************************************************
691 * 691 *
692 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 692 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
693 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 693 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
694 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 694 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
@@ -696,25 +696,25 @@
696 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 696 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
697 */ 697 */
698 698
699#define C0_Index $0 699#define C0_Index $0
700#define R_C0_Index 0 700#define R_C0_Index 0
701#define C0_INX C0_Index /* OBSOLETE - DO NOT USE IN NEW CODE */ 701#define C0_INX C0_Index /* OBSOLETE - DO NOT USE IN NEW CODE */
702 702
703#define S_IndexP 31 /* Probe failure (R)*/ 703#define S_IndexP 31 /* Probe failure (R)*/
704#define M_IndexP (0x1 << S_IndexP) 704#define M_IndexP (0x1 << S_IndexP)
705 705
706#define S_IndexIndex 0 /* TLB index (R/W)*/ 706#define S_IndexIndex 0 /* TLB index (R/W)*/
707#define M_IndexIndex (0x3f << S_IndexIndex) 707#define M_IndexIndex (0x3f << S_IndexIndex)
708 708
709#define M_Index0Fields 0x7fffffc0 709#define M_Index0Fields 0x7fffffc0
710#define M_IndexRFields 0x80000000 710#define M_IndexRFields 0x80000000
711 711
712 712
713/* 713/*
714 ************************************************************************ 714 ************************************************************************
715 * R A N D O M R E G I S T E R ( 1 ) * 715 * R A N D O M R E G I S T E R ( 1 ) *
716 ************************************************************************ 716 ************************************************************************
717 * 717 *
718 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 718 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
719 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 719 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
720 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 720 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
@@ -722,22 +722,22 @@
722 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 722 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
723 */ 723 */
724 724
725#define C0_Random $1 725#define C0_Random $1
726#define R_C0_Random 1 726#define R_C0_Random 1
727#define C0_RAND $1 /* OBSOLETE - DO NOT USE IN NEW CODE */ 727#define C0_RAND $1 /* OBSOLETE - DO NOT USE IN NEW CODE */
728 728
729#define S_RandomIndex 0 /* TLB random index (R)*/ 729#define S_RandomIndex 0 /* TLB random index (R)*/
730#define M_RandomIndex (0x3f << S_RandomIndex) 730#define M_RandomIndex (0x3f << S_RandomIndex)
731 731
732#define M_Random0Fields 0xffffffc0 732#define M_Random0Fields 0xffffffc0
733#define M_RandomRFields 0x0000003f 733#define M_RandomRFields 0x0000003f
734 734
735 735
736/* 736/*
737 ************************************************************************ 737 ************************************************************************
738 * E N T R Y L O 0 R E G I S T E R ( 2 ) * 738 * E N T R Y L O 0 R E G I S T E R ( 2 ) *
739 ************************************************************************ 739 ************************************************************************
740 * 740 *
741 * 6 6 6 6 5 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 741 * 6 6 6 6 5 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
742 * 3 2 1 0 9 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 742 * 3 2 1 0 9 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
743 * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 743 * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
@@ -745,49 +745,49 @@
745 * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 745 * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
746 */ 746 */
747 747
748#define C0_EntryLo0 $2 748#define C0_EntryLo0 $2
749#define R_C0_EntryLo0 2 749#define R_C0_EntryLo0 2
750#define C0_TLBLO_0 C0_EntryLo0 /* OBSOLETE - DO NOT USE IN NEW CODE */ 750#define C0_TLBLO_0 C0_EntryLo0 /* OBSOLETE - DO NOT USE IN NEW CODE */
751 751
752#define S_EntryLoPFN 6 /* PFN (R/W) */ 752#define S_EntryLoPFN 6 /* PFN (R/W) */
753#define M_EntryLoPFN (0xffffff << S_EntryLoPFN) 753#define M_EntryLoPFN (0xffffff << S_EntryLoPFN)
754#define S_EntryLoC 3 /* Coherency attribute (R/W) */ 754#define S_EntryLoC 3 /* Coherency attribute (R/W) */
755#define M_EntryLoC (0x7 << S_EntryLoC) 755#define M_EntryLoC (0x7 << S_EntryLoC)
756#define S_EntryLoD 2 /* Dirty (R/W) */ 756#define S_EntryLoD 2 /* Dirty (R/W) */
757#define M_EntryLoD (0x1 << S_EntryLoD) 757#define M_EntryLoD (0x1 << S_EntryLoD)
758#define S_EntryLoV 1 /* Valid (R/W) */ 758#define S_EntryLoV 1 /* Valid (R/W) */
759#define M_EntryLoV (0x1 << S_EntryLoV) 759#define M_EntryLoV (0x1 << S_EntryLoV)
760#define S_EntryLoG 0 /* Global (R/W) */ 760#define S_EntryLoG 0 /* Global (R/W) */
761#define M_EntryLoG (0x1 << S_EntryLoG) 761#define M_EntryLoG (0x1 << S_EntryLoG)
762#define M_EntryLoOddPFN (0x1 << S_EntryLoPFN) /* Odd PFN bit */ 762#define M_EntryLoOddPFN (0x1 << S_EntryLoPFN) /* Odd PFN bit */
763#define S_EntryLo_RS K_PageAlign /* Right-justify PFN */ 763#define S_EntryLo_RS K_PageAlign /* Right-justify PFN */
764#define S_EntryLo_LS S_EntryLoPFN /* Position PFN to appropriate position */ 764#define S_EntryLo_LS S_EntryLoPFN /* Position PFN to appropriate position */
765 765
766#define M_EntryLo0Fields 0x00000000 766#define M_EntryLo0Fields 0x00000000
767#define M_EntryLoRFields 0xc0000000 767#define M_EntryLoRFields 0xc0000000
768#define M_EntryLo0Fields64 UNS64Const(0x0000000000000000) 768#define M_EntryLo0Fields64 UNS64Const(0x0000000000000000)
769#define M_EntryLoRFields64 UNS64Const(0xffffffffc0000000) 769#define M_EntryLoRFields64 UNS64Const(0xffffffffc0000000)
770 770
771/* 771/*
772 * Cache attribute values in the C field of EntryLo and the 772 * Cache attribute values in the C field of EntryLo and the
773 * K0 field of Config 773 * K0 field of Config
774 */ 774 */
775#define K_CacheAttrCWTnWA 0 /* Cacheable, write-thru, no write allocate */ 775#define K_CacheAttrCWTnWA 0 /* Cacheable, write-thru, no write allocate */
776#define K_CacheAttrCWTWA 1 /* Cacheable, write-thru, write allocate */ 776#define K_CacheAttrCWTWA 1 /* Cacheable, write-thru, write allocate */
777#define K_CacheAttrU 2 /* Uncached */ 777#define K_CacheAttrU 2 /* Uncached */
778#define K_CacheAttrC 3 /* Cacheable */ 778#define K_CacheAttrC 3 /* Cacheable */
779#define K_CacheAttrCN 3 /* Cacheable, non-coherent */ 779#define K_CacheAttrCN 3 /* Cacheable, non-coherent */
780#define K_CacheAttrCCE 4 /* Cacheable, coherent, exclusive */ 780#define K_CacheAttrCCE 4 /* Cacheable, coherent, exclusive */
781#define K_CacheAttrCCS 5 /* Cacheable, coherent, shared */ 781#define K_CacheAttrCCS 5 /* Cacheable, coherent, shared */
782#define K_CacheAttrCCU 6 /* Cacheable, coherent, update */ 782#define K_CacheAttrCCU 6 /* Cacheable, coherent, update */
783#define K_CacheAttrUA 7 /* Uncached accelerated */ 783#define K_CacheAttrUA 7 /* Uncached accelerated */
784 784
785 785
786/* 786/*
787 ************************************************************************ 787 ************************************************************************
788 * E N T R Y L O 1 R E G I S T E R ( 3 ) * 788 * E N T R Y L O 1 R E G I S T E R ( 3 ) *
789 ************************************************************************ 789 ************************************************************************
790 * 790 *
791 * 6 6 6 6 5 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 791 * 6 6 6 6 5 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
792 * 3 2 1 0 9 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 792 * 3 2 1 0 9 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
793 * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 793 * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
@@ -795,9 +795,9 @@
795 * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 795 * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
796 */ 796 */
797 797
798#define C0_EntryLo1 $3 798#define C0_EntryLo1 $3
799#define R_C0_EntryLo1 3 799#define R_C0_EntryLo1 3
800#define C0_TLBLO_1 C0_EntryLo1 /* OBSOLETE - DO NOT USE IN NEW CODE */ 800#define C0_TLBLO_1 C0_EntryLo1 /* OBSOLETE - DO NOT USE IN NEW CODE */
801 801
802/* 802/*
803 * Field definitions are as given for EntryLo0 above 803 * Field definitions are as given for EntryLo0 above
@@ -808,7 +808,7 @@
808 ************************************************************************ 808 ************************************************************************
809 * C O N T E X T R E G I S T E R ( 4 ) * 809 * C O N T E X T R E G I S T E R ( 4 ) *
810 ************************************************************************ 810 ************************************************************************
811 * 811 *
812 * 6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 812 * 6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
813 * 3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 813 * 3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
814 * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 814 * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
@@ -816,28 +816,28 @@
816 * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 816 * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
817 */ 817 */
818 818
819#define C0_Context $4 819#define C0_Context $4
820#define R_C0_Context 4 820#define R_C0_Context 4
821#define C0_CTXT C0_Context /* OBSOLETE - DO NOT USE IN NEW CODE */ 821#define C0_CTXT C0_Context /* OBSOLETE - DO NOT USE IN NEW CODE */
822 822
823#define S_ContextPTEBase 23 /* PTE base (R/W) */ 823#define S_ContextPTEBase 23 /* PTE base (R/W) */
824#define M_ContextPTEBase (0x1ff << S_ContextPTEBase) 824#define M_ContextPTEBase (0x1ff << S_ContextPTEBase)
825#define S_ContextBadVPN 4 /* BadVPN2 (R) */ 825#define S_ContextBadVPN 4 /* BadVPN2 (R) */
826#define M_ContextBadVPN (0x7ffff << S_ContextBadVPN) 826#define M_ContextBadVPN (0x7ffff << S_ContextBadVPN)
827#define S_ContextBadVPN_LS 9 /* Position BadVPN to bit 31 */ 827#define S_ContextBadVPN_LS 9 /* Position BadVPN to bit 31 */
828#define S_ContextBadVPN_RS 13 /* Right-justify shifted BadVPN field */ 828#define S_ContextBadVPN_RS 13 /* Right-justify shifted BadVPN field */
829 829
830#define M_Context0Fields 0x0000000f 830#define M_Context0Fields 0x0000000f
831#define M_ContextRFields 0x007ffff0 831#define M_ContextRFields 0x007ffff0
832#define M_Context0Fields64 UNS64Const(0x000000000000000f) 832#define M_Context0Fields64 UNS64Const(0x000000000000000f)
833#define M_ContextRFields64 UNS64Const(0x00000000007ffff0) 833#define M_ContextRFields64 UNS64Const(0x00000000007ffff0)
834 834
835 835
836/* 836/*
837 ************************************************************************ 837 ************************************************************************
838 * P A G E M A S K R E G I S T E R ( 5 ) * 838 * P A G E M A S K R E G I S T E R ( 5 ) *
839 ************************************************************************ 839 ************************************************************************
840 * 840 *
841 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 841 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
842 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 842 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
843 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 843 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
@@ -845,41 +845,41 @@
845 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 845 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
846 */ 846 */
847 847
848#define C0_PageMask $5 848#define C0_PageMask $5
849#define R_C0_PageMask 5 /* Mask (R/W) */ 849#define R_C0_PageMask 5 /* Mask (R/W) */
850#define C0_PGMASK C0_PageMask /* OBSOLETE - DO NOT USE IN NEW CODE */ 850#define C0_PGMASK C0_PageMask /* OBSOLETE - DO NOT USE IN NEW CODE */
851 851
852#define S_PageMaskMask 13 852#define S_PageMaskMask 13
853#define M_PageMaskMask (0xfff << S_PageMaskMask) 853#define M_PageMaskMask (0xfff << S_PageMaskMask)
854 854
855#define M_PageMask0Fields 0xfe001fff 855#define M_PageMask0Fields 0xfe001fff
856#define M_PageMaskRFields 0x00000000 856#define M_PageMaskRFields 0x00000000
857 857
858/* 858/*
859 * Values in the Mask field 859 * Values in the Mask field
860 */ 860 */
861#define K_PageMask4K 0x000 /* K_PageMasknn values are values for use */ 861#define K_PageMask4K 0x000 /* K_PageMasknn values are values for use */
862#define K_PageMask16K 0x003 /* with KReqPageAttributes or KReqPageMask macros */ 862#define K_PageMask16K 0x003 /* with KReqPageAttributes or KReqPageMask macros */
863#define K_PageMask64K 0x00f 863#define K_PageMask64K 0x00f
864#define K_PageMask256K 0x03f 864#define K_PageMask256K 0x03f
865#define K_PageMask1M 0x0ff 865#define K_PageMask1M 0x0ff
866#define K_PageMask4M 0x3ff 866#define K_PageMask4M 0x3ff
867#define K_PageMask16M 0xfff 867#define K_PageMask16M 0xfff
868 868
869#define M_PageMask4K (K_PageMask4K << S_PageMaskMask) /* M_PageMasknn values are masks */ 869#define M_PageMask4K (K_PageMask4K << S_PageMaskMask) /* M_PageMasknn values are masks */
870#define M_PageMask16K (K_PageMask16K << S_PageMaskMask) /* in position in the PageMask register */ 870#define M_PageMask16K (K_PageMask16K << S_PageMaskMask) /* in position in the PageMask register */
871#define M_PageMask64K (K_PageMask64K << S_PageMaskMask) 871#define M_PageMask64K (K_PageMask64K << S_PageMaskMask)
872#define M_PageMask256K (K_PageMask256K << S_PageMaskMask) 872#define M_PageMask256K (K_PageMask256K << S_PageMaskMask)
873#define M_PageMask1M (K_PageMask1M << S_PageMaskMask) 873#define M_PageMask1M (K_PageMask1M << S_PageMaskMask)
874#define M_PageMask4M (K_PageMask4M << S_PageMaskMask) 874#define M_PageMask4M (K_PageMask4M << S_PageMaskMask)
875#define M_PageMask16M (K_PageMask16M << S_PageMaskMask) 875#define M_PageMask16M (K_PageMask16M << S_PageMaskMask)
876 876
877 877
878/* 878/*
879 ************************************************************************ 879 ************************************************************************
880 * W I R E D R E G I S T E R ( 6 ) * 880 * W I R E D R E G I S T E R ( 6 ) *
881 ************************************************************************ 881 ************************************************************************
882 * 882 *
883 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 883 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
884 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 884 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
885 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 885 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
@@ -887,22 +887,22 @@
887 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 887 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
888 */ 888 */
889 889
890#define C0_Wired $6 890#define C0_Wired $6
891#define R_C0_Wired 6 891#define R_C0_Wired 6
892#define C0_TLBWIRED C0_Wired /* OBSOLETE - DO NOT USE IN NEW CODE */ 892#define C0_TLBWIRED C0_Wired /* OBSOLETE - DO NOT USE IN NEW CODE */
893 893
894#define S_WiredIndex 0 /* TLB wired boundary (R/W) */ 894#define S_WiredIndex 0 /* TLB wired boundary (R/W) */
895#define M_WiredIndex (0x3f << S_WiredIndex) 895#define M_WiredIndex (0x3f << S_WiredIndex)
896 896
897#define M_Wired0Fields 0xffffffc0 897#define M_Wired0Fields 0xffffffc0
898#define M_WiredRFields 0x00000000 898#define M_WiredRFields 0x00000000
899 899
900 900
901/* 901/*
902 ************************************************************************ 902 ************************************************************************
903 * B A D V A D D R R E G I S T E R ( 8 ) * 903 * B A D V A D D R R E G I S T E R ( 8 ) *
904 ************************************************************************ 904 ************************************************************************
905 * 905 *
906 * 6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 906 * 6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
907 * 3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 907 * 3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
908 * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 908 * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
@@ -910,22 +910,22 @@
910 * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 910 * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
911 */ 911 */
912 912
913#define C0_BadVAddr $8 913#define C0_BadVAddr $8
914#define R_C0_BadVAddr 8 914#define R_C0_BadVAddr 8
915#define C0_BADVADDR C0_BadVAddr /* OBSOLETE - DO NOT USE IN NEW CODE */ 915#define C0_BADVADDR C0_BadVAddr /* OBSOLETE - DO NOT USE IN NEW CODE */
916 916
917#define M_BadVAddrOddPage K_PageSize /* Even/Odd VA bit for pair of PAs */ 917#define M_BadVAddrOddPage K_PageSize /* Even/Odd VA bit for pair of PAs */
918 918
919#define M_BadVAddr0Fields 0x00000000 919#define M_BadVAddr0Fields 0x00000000
920#define M_BadVAddrRFields 0xffffffff 920#define M_BadVAddrRFields 0xffffffff
921#define M_BadVAddr0Fields64 UNS64Const(0x0000000000000000) 921#define M_BadVAddr0Fields64 UNS64Const(0x0000000000000000)
922#define M_BadVAddrRFields64 UNS64Const(0xffffffffffffffff) 922#define M_BadVAddrRFields64 UNS64Const(0xffffffffffffffff)
923 923
924/* 924/*
925 ************************************************************************ 925 ************************************************************************
926 * C O U N T R E G I S T E R ( 9 ) * 926 * C O U N T R E G I S T E R ( 9 ) *
927 ************************************************************************ 927 ************************************************************************
928 * 928 *
929 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 929 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
930 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 930 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
931 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 931 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
@@ -933,19 +933,19 @@
933 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 933 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
934 */ 934 */
935 935
936#define C0_Count $9 936#define C0_Count $9
937#define R_C0_Count 9 937#define R_C0_Count 9
938#define C0_COUNT C0_Count /* OBSOLETE - DO NOT USE IN NEW CODE */ 938#define C0_COUNT C0_Count /* OBSOLETE - DO NOT USE IN NEW CODE */
939 939
940#define M_Count0Fields 0x00000000 940#define M_Count0Fields 0x00000000
941#define M_CountRFields 0x00000000 941#define M_CountRFields 0x00000000
942 942
943 943
944/* 944/*
945 ************************************************************************ 945 ************************************************************************
946 * E N T R Y H I R E G I S T E R ( 1 0 ) * 946 * E N T R Y H I R E G I S T E R ( 1 0 ) *
947 ************************************************************************ 947 ************************************************************************
948 * 948 *
949 * 6 6 6 6 5 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 949 * 6 6 6 6 5 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
950 * 3 2 1 0 9 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 950 * 3 2 1 0 9 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
951 * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 951 * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
@@ -953,30 +953,30 @@
953 * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 953 * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
954 */ 954 */
955 955
956#define C0_EntryHi $10 956#define C0_EntryHi $10
957#define R_C0_EntryHi 10 957#define R_C0_EntryHi 10
958#define C0_TLBHI C0_EntryHi /* OBSOLETE - DO NOT USE IN NEW CODE */ 958#define C0_TLBHI C0_EntryHi /* OBSOLETE - DO NOT USE IN NEW CODE */
959 959
960#define S_EntryHiR64 62 /* Region (R/W) */ 960#define S_EntryHiR64 62 /* Region (R/W) */
961#define M_EntryHiR64 UNS64Const(0xc000000000000000) 961#define M_EntryHiR64 UNS64Const(0xc000000000000000)
962#define S_EntryHiVPN2 13 /* VPN/2 (R/W) */ 962#define S_EntryHiVPN2 13 /* VPN/2 (R/W) */
963#define M_EntryHiVPN2 (0x7ffff << S_EntryHiVPN2) 963#define M_EntryHiVPN2 (0x7ffff << S_EntryHiVPN2)
964#define M_EntryHiVPN264 UNS64Const(0x000000ffffffe000) 964#define M_EntryHiVPN264 UNS64Const(0x000000ffffffe000)
965#define S_EntryHiASID 0 /* ASID (R/W) */ 965#define S_EntryHiASID 0 /* ASID (R/W) */
966#define M_EntryHiASID (0xff << S_EntryHiASID) 966#define M_EntryHiASID (0xff << S_EntryHiASID)
967#define S_EntryHiVPN_Shf S_EntryHiVPN2 967#define S_EntryHiVPN_Shf S_EntryHiVPN2
968 968
969#define M_EntryHi0Fields 0x00001f00 969#define M_EntryHi0Fields 0x00001f00
970#define M_EntryHiRFields 0x00000000 970#define M_EntryHiRFields 0x00000000
971#define M_EntryHi0Fields64 UNS64Const(0x0000000000001f00) 971#define M_EntryHi0Fields64 UNS64Const(0x0000000000001f00)
972#define M_EntryHiRFields64 UNS64Const(0x3fffff0000000000) 972#define M_EntryHiRFields64 UNS64Const(0x3fffff0000000000)
973 973
974 974
975/* 975/*
976 ************************************************************************ 976 ************************************************************************
977 * C O M P A R E R E G I S T E R ( 1 1 ) * 977 * C O M P A R E R E G I S T E R ( 1 1 ) *
978 ************************************************************************ 978 ************************************************************************
979 * 979 *
980 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 980 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
981 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 981 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
982 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 982 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
@@ -984,19 +984,19 @@
984 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 984 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
985 */ 985 */
986 986
987#define C0_Compare $11 987#define C0_Compare $11
988#define R_C0_Compare 11 988#define R_C0_Compare 11
989#define C0_COMPARE C0_Compare /* OBSOLETE - DO NOT USE IN NEW CODE */ 989#define C0_COMPARE C0_Compare /* OBSOLETE - DO NOT USE IN NEW CODE */
990 990
991#define M_Compare0Fields 0x00000000 991#define M_Compare0Fields 0x00000000
992#define M_CompareRFields 0x00000000 992#define M_CompareRFields 0x00000000
993 993
994 994
995/* 995/*
996 ************************************************************************ 996 ************************************************************************
997 * S T A T U S R E G I S T E R ( 1 2 ) * 997 * S T A T U S R E G I S T E R ( 1 2 ) *
998 ************************************************************************ 998 ************************************************************************
999 * 999 *
1000 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1000 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1001 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 1001 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
1002 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1002 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
@@ -1006,93 +1006,93 @@
1006 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1006 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1007 */ 1007 */
1008 1008
1009#define C0_Status $12 1009#define C0_Status $12
1010#define R_C0_Status 12 1010#define R_C0_Status 12
1011#define C0_SR C0_Status /* OBSOLETE - DO NOT USE IN NEW CODE */ 1011#define C0_SR C0_Status /* OBSOLETE - DO NOT USE IN NEW CODE */
1012 1012
1013#define S_StatusCU 28 /* Coprocessor enable (R/W) */ 1013#define S_StatusCU 28 /* Coprocessor enable (R/W) */
1014#define M_StatusCU (0xf << S_StatusCU) 1014#define M_StatusCU (0xf << S_StatusCU)
1015#define S_StatusCU3 31 1015#define S_StatusCU3 31
1016#define M_StatusCU3 (0x1 << S_StatusCU3) 1016#define M_StatusCU3 (0x1 << S_StatusCU3)
1017#define S_StatusCU2 30 1017#define S_StatusCU2 30
1018#define M_StatusCU2 (0x1 << S_StatusCU2) 1018#define M_StatusCU2 (0x1 << S_StatusCU2)
1019#define S_StatusCU1 29 1019#define S_StatusCU1 29
1020#define M_StatusCU1 (0x1 << S_StatusCU1) 1020#define M_StatusCU1 (0x1 << S_StatusCU1)
1021#define S_StatusCU0 28 1021#define S_StatusCU0 28
1022#define M_StatusCU0 (0x1 << S_StatusCU0) 1022#define M_StatusCU0 (0x1 << S_StatusCU0)
1023#define S_StatusRP 27 /* Enable reduced power mode (R/W) */ 1023#define S_StatusRP 27 /* Enable reduced power mode (R/W) */
1024#define M_StatusRP (0x1 << S_StatusRP) 1024#define M_StatusRP (0x1 << S_StatusRP)
1025#define S_StatusFR 26 /* Enable 64-bit FPRs (MIPS64 only) (R/W) */ 1025#define S_StatusFR 26 /* Enable 64-bit FPRs (MIPS64 only) (R/W) */
1026#define M_StatusFR (0x1 << S_StatusFR) 1026#define M_StatusFR (0x1 << S_StatusFR)
1027#define S_StatusRE 25 /* Enable reverse endian (R/W) */ 1027#define S_StatusRE 25 /* Enable reverse endian (R/W) */
1028#define M_StatusRE (0x1 << S_StatusRE) 1028#define M_StatusRE (0x1 << S_StatusRE)
1029#define S_StatusMX 24 /* Enable access to MDMX resources (MIPS64 only) (R/W) */ 1029#define S_StatusMX 24 /* Enable access to MDMX resources (MIPS64 only) (R/W) */
1030#define M_StatusMX (0x1 << S_StatusMX) 1030#define M_StatusMX (0x1 << S_StatusMX)
1031#define S_StatusPX 23 /* Enable access to 64-bit instructions/data (MIPS64 only) (R/W) */ 1031#define S_StatusPX 23 /* Enable access to 64-bit instructions/data (MIPS64 only) (R/W) */
1032#define M_StatusPX (0x1 << S_StatusPX) 1032#define M_StatusPX (0x1 << S_StatusPX)
1033#define S_StatusBEV 22 /* Enable Boot Exception Vectors (R/W) */ 1033#define S_StatusBEV 22 /* Enable Boot Exception Vectors (R/W) */
1034#define M_StatusBEV (0x1 << S_StatusBEV) 1034#define M_StatusBEV (0x1 << S_StatusBEV)
1035#define S_StatusTS 21 /* Denote TLB shutdown (R/W) */ 1035#define S_StatusTS 21 /* Denote TLB shutdown (R/W) */
1036#define M_StatusTS (0x1 << S_StatusTS) 1036#define M_StatusTS (0x1 << S_StatusTS)
1037#define S_StatusSR 20 /* Denote soft reset (R/W) */ 1037#define S_StatusSR 20 /* Denote soft reset (R/W) */
1038#define M_StatusSR (0x1 << S_StatusSR) 1038#define M_StatusSR (0x1 << S_StatusSR)
1039#define S_StatusNMI 19 1039#define S_StatusNMI 19
1040#define M_StatusNMI (0x1 << S_StatusNMI) /* Denote NMI (R/W) */ 1040#define M_StatusNMI (0x1 << S_StatusNMI) /* Denote NMI (R/W) */
1041#define S_StatusIM 8 /* Interrupt mask (R/W) */ 1041#define S_StatusIM 8 /* Interrupt mask (R/W) */
1042#define M_StatusIM (0xff << S_StatusIM) 1042#define M_StatusIM (0xff << S_StatusIM)
1043#define S_StatusIM7 15 1043#define S_StatusIM7 15
1044#define M_StatusIM7 (0x1 << S_StatusIM7) 1044#define M_StatusIM7 (0x1 << S_StatusIM7)
1045#define S_StatusIM6 14 1045#define S_StatusIM6 14
1046#define M_StatusIM6 (0x1 << S_StatusIM6) 1046#define M_StatusIM6 (0x1 << S_StatusIM6)
1047#define S_StatusIM5 13 1047#define S_StatusIM5 13
1048#define M_StatusIM5 (0x1 << S_StatusIM5) 1048#define M_StatusIM5 (0x1 << S_StatusIM5)
1049#define S_StatusIM4 12 1049#define S_StatusIM4 12
1050#define M_StatusIM4 (0x1 << S_StatusIM4) 1050#define M_StatusIM4 (0x1 << S_StatusIM4)
1051#define S_StatusIM3 11 1051#define S_StatusIM3 11
1052#define M_StatusIM3 (0x1 << S_StatusIM3) 1052#define M_StatusIM3 (0x1 << S_StatusIM3)
1053#define S_StatusIM2 10 1053#define S_StatusIM2 10
1054#define M_StatusIM2 (0x1 << S_StatusIM2) 1054#define M_StatusIM2 (0x1 << S_StatusIM2)
1055#define S_StatusIM1 9 1055#define S_StatusIM1 9
1056#define M_StatusIM1 (0x1 << S_StatusIM1) 1056#define M_StatusIM1 (0x1 << S_StatusIM1)
1057#define S_StatusIM0 8 1057#define S_StatusIM0 8
1058#define M_StatusIM0 (0x1 << S_StatusIM0) 1058#define M_StatusIM0 (0x1 << S_StatusIM0)
1059#define S_StatusKX 7 /* Enable access to extended kernel addresses (MIPS64 only) (R/W) */ 1059#define S_StatusKX 7 /* Enable access to extended kernel addresses (MIPS64 only) (R/W) */
1060#define M_StatusKX (0x1 << S_StatusKX) 1060#define M_StatusKX (0x1 << S_StatusKX)
1061#define S_StatusSX 6 /* Enable access to extended supervisor addresses (MIPS64 only) (R/W) */ 1061#define S_StatusSX 6 /* Enable access to extended supervisor addresses (MIPS64 only) (R/W) */
1062#define M_StatusSX (0x1 << S_StatusSX) 1062#define M_StatusSX (0x1 << S_StatusSX)
1063#define S_StatusUX 5 /* Enable access to extended user addresses (MIPS64 only) (R/W) */ 1063#define S_StatusUX 5 /* Enable access to extended user addresses (MIPS64 only) (R/W) */
1064#define M_StatusUX (0x1 << S_StatusUX) 1064#define M_StatusUX (0x1 << S_StatusUX)
1065#define S_StatusKSU 3 /* Two-bit current mode (R/W) */ 1065#define S_StatusKSU 3 /* Two-bit current mode (R/W) */
1066#define M_StatusKSU (0x3 << S_StatusKSU) 1066#define M_StatusKSU (0x3 << S_StatusKSU)
1067#define S_StatusUM 4 /* User mode if supervisor mode not implemented (R/W) */ 1067#define S_StatusUM 4 /* User mode if supervisor mode not implemented (R/W) */
1068#define M_StatusUM (0x1 << S_StatusUM) 1068#define M_StatusUM (0x1 << S_StatusUM)
1069#define S_StatusSM 3 /* Supervisor mode (R/W) */ 1069#define S_StatusSM 3 /* Supervisor mode (R/W) */
1070#define M_StatusSM (0x1 << S_StatusSM) 1070#define M_StatusSM (0x1 << S_StatusSM)
1071#define S_StatusERL 2 /* Denotes error level (R/W) */ 1071#define S_StatusERL 2 /* Denotes error level (R/W) */
1072#define M_StatusERL (0x1 << S_StatusERL) 1072#define M_StatusERL (0x1 << S_StatusERL)
1073#define S_StatusEXL 1 /* Denotes exception level (R/W) */ 1073#define S_StatusEXL 1 /* Denotes exception level (R/W) */
1074#define M_StatusEXL (0x1 << S_StatusEXL) 1074#define M_StatusEXL (0x1 << S_StatusEXL)
1075#define S_StatusIE 0 /* Enables interrupts (R/W) */ 1075#define S_StatusIE 0 /* Enables interrupts (R/W) */
1076#define M_StatusIE (0x1 << S_StatusIE) 1076#define M_StatusIE (0x1 << S_StatusIE)
1077 1077
1078#define M_Status0Fields 0x00040000 1078#define M_Status0Fields 0x00040000
1079#define M_StatusRFields 0x058000e0 /* FR, MX, PX, KX, SX, UX unused in MIPS32 */ 1079#define M_StatusRFields 0x058000e0 /* FR, MX, PX, KX, SX, UX unused in MIPS32 */
1080#define M_Status0Fields64 0x00040000 1080#define M_Status0Fields64 0x00040000
1081#define M_StatusRFields64 0x00000000 1081#define M_StatusRFields64 0x00000000
1082 1082
1083/* 1083/*
1084 * Values in the KSU field 1084 * Values in the KSU field
1085 */ 1085 */
1086#define K_StatusKSU_U 2 /* User mode in KSU field */ 1086#define K_StatusKSU_U 2 /* User mode in KSU field */
1087#define K_StatusKSU_S 1 /* Supervisor mode in KSU field */ 1087#define K_StatusKSU_S 1 /* Supervisor mode in KSU field */
1088#define K_StatusKSU_K 0 /* Kernel mode in KSU field */ 1088#define K_StatusKSU_K 0 /* Kernel mode in KSU field */
1089 1089
1090 1090
1091/* 1091/*
1092 ************************************************************************ 1092 ************************************************************************
1093 * C A U S E R E G I S T E R ( 1 3 ) * 1093 * C A U S E R E G I S T E R ( 1 3 ) *
1094 ************************************************************************ 1094 ************************************************************************
1095 * 1095 *
1096 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1096 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1097 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 1097 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
1098 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1098 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
@@ -1102,108 +1102,108 @@
1102 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1102 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1103 */ 1103 */
1104 1104
1105#define C0_Cause $13 1105#define C0_Cause $13
1106#define R_C0_Cause 13 1106#define R_C0_Cause 13
1107#define C0_CAUSE C0_Cause /* OBSOLETE - DO NOT USE IN NEW CODE */ 1107#define C0_CAUSE C0_Cause /* OBSOLETE - DO NOT USE IN NEW CODE */
1108 1108
1109#define S_CauseBD 31 1109#define S_CauseBD 31
1110#define M_CauseBD (0x1 << S_CauseBD) 1110#define M_CauseBD (0x1 << S_CauseBD)
1111#define S_CauseCE 28 1111#define S_CauseCE 28
1112#define M_CauseCE (0x3<< S_CauseCE) 1112#define M_CauseCE (0x3<< S_CauseCE)
1113#define S_CauseIV 23 1113#define S_CauseIV 23
1114#define M_CauseIV (0x1 << S_CauseIV) 1114#define M_CauseIV (0x1 << S_CauseIV)
1115#define S_CauseWP 22 1115#define S_CauseWP 22
1116#define M_CauseWP (0x1 << S_CauseWP) 1116#define M_CauseWP (0x1 << S_CauseWP)
1117#define S_CauseIP 8 1117#define S_CauseIP 8
1118#define M_CauseIP (0xff << S_CauseIP) 1118#define M_CauseIP (0xff << S_CauseIP)
1119#define S_CauseIPEXT 10 1119#define S_CauseIPEXT 10
1120#define M_CauseIPEXT (0x3f << S_CauseIPEXT) 1120#define M_CauseIPEXT (0x3f << S_CauseIPEXT)
1121#define S_CauseIP7 15 1121#define S_CauseIP7 15
1122#define M_CauseIP7 (0x1 << S_CauseIP7) 1122#define M_CauseIP7 (0x1 << S_CauseIP7)
1123#define S_CauseIP6 14 1123#define S_CauseIP6 14
1124#define M_CauseIP6 (0x1 << S_CauseIP6) 1124#define M_CauseIP6 (0x1 << S_CauseIP6)
1125#define S_CauseIP5 13 1125#define S_CauseIP5 13
1126#define M_CauseIP5 (0x1 << S_CauseIP5) 1126#define M_CauseIP5 (0x1 << S_CauseIP5)
1127#define S_CauseIP4 12 1127#define S_CauseIP4 12
1128#define M_CauseIP4 (0x1 << S_CauseIP4) 1128#define M_CauseIP4 (0x1 << S_CauseIP4)
1129#define S_CauseIP3 11 1129#define S_CauseIP3 11
1130#define M_CauseIP3 (0x1 << S_CauseIP3) 1130#define M_CauseIP3 (0x1 << S_CauseIP3)
1131#define S_CauseIP2 10 1131#define S_CauseIP2 10
1132#define M_CauseIP2 (0x1 << S_CauseIP2) 1132#define M_CauseIP2 (0x1 << S_CauseIP2)
1133#define S_CauseIP1 9 1133#define S_CauseIP1 9
1134#define M_CauseIP1 (0x1 << S_CauseIP1) 1134#define M_CauseIP1 (0x1 << S_CauseIP1)
1135#define S_CauseIP0 8 1135#define S_CauseIP0 8
1136#define M_CauseIP0 (0x1 << S_CauseIP0) 1136#define M_CauseIP0 (0x1 << S_CauseIP0)
1137#define S_CauseExcCode 2 1137#define S_CauseExcCode 2
1138#define M_CauseExcCode (0x1f << S_CauseExcCode) 1138#define M_CauseExcCode (0x1f << S_CauseExcCode)
1139 1139
1140#define M_Cause0Fields 0x4f3f0083 1140#define M_Cause0Fields 0x4f3f0083
1141#define M_CauseRFields 0xb000fc7c 1141#define M_CauseRFields 0xb000fc7c
1142 1142
1143/* 1143/*
1144 * Values in the CE field 1144 * Values in the CE field
1145 */ 1145 */
1146#define K_CauseCE0 0 /* Coprocessor 0 in the CE field */ 1146#define K_CauseCE0 0 /* Coprocessor 0 in the CE field */
1147#define K_CauseCE1 1 /* Coprocessor 1 in the CE field */ 1147#define K_CauseCE1 1 /* Coprocessor 1 in the CE field */
1148#define K_CauseCE2 2 /* Coprocessor 2 in the CE field */ 1148#define K_CauseCE2 2 /* Coprocessor 2 in the CE field */
1149#define K_CauseCE3 3 /* Coprocessor 3 in the CE field */ 1149#define K_CauseCE3 3 /* Coprocessor 3 in the CE field */
1150 1150
1151/* 1151/*
1152 * Values in the ExcCode field 1152 * Values in the ExcCode field
1153 */ 1153 */
1154#define EX_INT 0 /* Interrupt */ 1154#define EX_INT 0 /* Interrupt */
1155#define EXC_INT (EX_INT << S_CauseExcCode) 1155#define EXC_INT (EX_INT << S_CauseExcCode)
1156#define EX_MOD 1 /* TLB modified */ 1156#define EX_MOD 1 /* TLB modified */
1157#define EXC_MOD (EX_MOD << S_CauseExcCode) 1157#define EXC_MOD (EX_MOD << S_CauseExcCode)
1158#define EX_TLBL 2 /* TLB exception (load or ifetch) */ 1158#define EX_TLBL 2 /* TLB exception (load or ifetch) */
1159#define EXC_TLBL (EX_TLBL << S_CauseExcCode) 1159#define EXC_TLBL (EX_TLBL << S_CauseExcCode)
1160#define EX_TLBS 3 /* TLB exception (store) */ 1160#define EX_TLBS 3 /* TLB exception (store) */
1161#define EXC_TLBS (EX_TLBS << S_CauseExcCode) 1161#define EXC_TLBS (EX_TLBS << S_CauseExcCode)
1162#define EX_ADEL 4 /* Address error (load or ifetch) */ 1162#define EX_ADEL 4 /* Address error (load or ifetch) */
1163#define EXC_ADEL (EX_ADEL << S_CauseExcCode) 1163#define EXC_ADEL (EX_ADEL << S_CauseExcCode)
1164#define EX_ADES 5 /* Address error (store) */ 1164#define EX_ADES 5 /* Address error (store) */
1165#define EXC_ADES (EX_ADES << S_CauseExcCode) 1165#define EXC_ADES (EX_ADES << S_CauseExcCode)
1166#define EX_IBE 6 /* Instruction Bus Error */ 1166#define EX_IBE 6 /* Instruction Bus Error */
1167#define EXC_IBE (EX_IBE << S_CauseExcCode) 1167#define EXC_IBE (EX_IBE << S_CauseExcCode)
1168#define EX_DBE 7 /* Data Bus Error */ 1168#define EX_DBE 7 /* Data Bus Error */
1169#define EXC_DBE (EX_DBE << S_CauseExcCode) 1169#define EXC_DBE (EX_DBE << S_CauseExcCode)
1170#define EX_SYS 8 /* Syscall */ 1170#define EX_SYS 8 /* Syscall */
1171#define EXC_SYS (EX_SYS << S_CauseExcCode) 1171#define EXC_SYS (EX_SYS << S_CauseExcCode)
1172#define EX_SYSCALL EX_SYS 1172#define EX_SYSCALL EX_SYS
1173#define EXC_SYSCALL EXC_SYS 1173#define EXC_SYSCALL EXC_SYS
1174#define EX_BP 9 /* Breakpoint */ 1174#define EX_BP 9 /* Breakpoint */
1175#define EXC_BP (EX_BP << S_CauseExcCode) 1175#define EXC_BP (EX_BP << S_CauseExcCode)
1176#define EX_BREAK EX_BP 1176#define EX_BREAK EX_BP
1177#define EXC_BREAK EXC_BP 1177#define EXC_BREAK EXC_BP
1178#define EX_RI 10 /* Reserved instruction */ 1178#define EX_RI 10 /* Reserved instruction */
1179#define EXC_RI (EX_RI << S_CauseExcCode) 1179#define EXC_RI (EX_RI << S_CauseExcCode)
1180#define EX_CPU 11 /* CoProcessor Unusable */ 1180#define EX_CPU 11 /* CoProcessor Unusable */
1181#define EXC_CPU (EX_CPU << S_CauseExcCode) 1181#define EXC_CPU (EX_CPU << S_CauseExcCode)
1182#define EX_OV 12 /* OVerflow */ 1182#define EX_OV 12 /* OVerflow */
1183#define EXC_OV (EX_OV << S_CauseExcCode) 1183#define EXC_OV (EX_OV << S_CauseExcCode)
1184#define EX_TR 13 /* Trap instruction */ 1184#define EX_TR 13 /* Trap instruction */
1185#define EXC_TR (EX_TR << S_CauseExcCode) 1185#define EXC_TR (EX_TR << S_CauseExcCode)
1186#define EX_TRAP EX_TR 1186#define EX_TRAP EX_TR
1187#define EXC_TRAP EXC_TR 1187#define EXC_TRAP EXC_TR
1188#define EX_FPE 15 /* floating point exception */ 1188#define EX_FPE 15 /* floating point exception */
1189#define EXC_FPE (EX_FPE << S_CauseExcCode) 1189#define EXC_FPE (EX_FPE << S_CauseExcCode)
1190#define EX_C2E 18 /* COP2 exception */ 1190#define EX_C2E 18 /* COP2 exception */
1191#define EXC_C2E (EX_C2E << S_CauseExcCode) 1191#define EXC_C2E (EX_C2E << S_CauseExcCode)
1192#define EX_MDMX 22 /* MDMX exception */ 1192#define EX_MDMX 22 /* MDMX exception */
1193#define EXC_MDMX (EX_MDMX << S_CauseExcCode) 1193#define EXC_MDMX (EX_MDMX << S_CauseExcCode)
1194#define EX_WATCH 23 /* Watch exception */ 1194#define EX_WATCH 23 /* Watch exception */
1195#define EXC_WATCH (EX_WATCH << S_CauseExcCode) 1195#define EXC_WATCH (EX_WATCH << S_CauseExcCode)
1196#define EX_MCHECK 24 /* Machine check exception */ 1196#define EX_MCHECK 24 /* Machine check exception */
1197#define EXC_MCHECK (EX_MCHECK << S_CauseExcCode) 1197#define EXC_MCHECK (EX_MCHECK << S_CauseExcCode)
1198#define EX_CacheErr 30 /* Cache error caused re-entry to Debug Mode */ 1198#define EX_CacheErr 30 /* Cache error caused re-entry to Debug Mode */
1199#define EXC_CacheErr (EX_CacheErr << S_CauseExcCode) 1199#define EXC_CacheErr (EX_CacheErr << S_CauseExcCode)
1200 1200
1201 1201
1202/* 1202/*
1203 ************************************************************************ 1203 ************************************************************************
1204 * E P C R E G I S T E R ( 1 4 ) * 1204 * E P C R E G I S T E R ( 1 4 ) *
1205 ************************************************************************ 1205 ************************************************************************
1206 * 1206 *
1207 * 6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1207 * 6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1208 * 3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 1208 * 3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
1209 * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1209 * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
@@ -1211,19 +1211,19 @@
1211 * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1211 * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1212 */ 1212 */
1213 1213
1214#define C0_EPC $14 1214#define C0_EPC $14
1215#define R_C0_EPC 14 1215#define R_C0_EPC 14
1216 1216
1217#define M_EPC0Fields 0x00000000 1217#define M_EPC0Fields 0x00000000
1218#define M_EPCRFields 0x00000000 1218#define M_EPCRFields 0x00000000
1219#define M_EPC0Fields64 UNS64Const(0x0000000000000000) 1219#define M_EPC0Fields64 UNS64Const(0x0000000000000000)
1220#define M_EPCRFields64 UNS64Const(0x0000000000000000) 1220#define M_EPCRFields64 UNS64Const(0x0000000000000000)
1221 1221
1222/* 1222/*
1223 ************************************************************************ 1223 ************************************************************************
1224 * P R I D R E G I S T E R ( 1 5 ) * 1224 * P R I D R E G I S T E R ( 1 5 ) *
1225 ************************************************************************ 1225 ************************************************************************
1226 * 1226 *
1227 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1227 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1228 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 1228 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
1229 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1229 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
@@ -1231,25 +1231,25 @@
1231 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1231 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1232 */ 1232 */
1233 1233
1234#define C0_PRId $15 1234#define C0_PRId $15
1235#define R_C0_PRId 15 1235#define R_C0_PRId 15
1236#define C0_PRID C0_PRID /* OBSOLETE - DO NOT USE IN NEW CODE */ 1236#define C0_PRID C0_PRID /* OBSOLETE - DO NOT USE IN NEW CODE */
1237 1237
1238#define S_PRIdCoOpt 24 /* Company options (R) */ 1238#define S_PRIdCoOpt 24 /* Company options (R) */
1239#define M_PRIdCoOpt (0xff << S_PRIdCoOpt) 1239#define M_PRIdCoOpt (0xff << S_PRIdCoOpt)
1240#define S_PRIdCoID 16 /* Company ID (R) */ 1240#define S_PRIdCoID 16 /* Company ID (R) */
1241#define M_PRIdCoID (0xff << S_PRIdCoID) 1241#define M_PRIdCoID (0xff << S_PRIdCoID)
1242#define S_PRIdImp 8 /* Implementation ID (R) */ 1242#define S_PRIdImp 8 /* Implementation ID (R) */
1243#define M_PRIdImp (0xff << S_PRIdImp) 1243#define M_PRIdImp (0xff << S_PRIdImp)
1244#define S_PRIdRev 0 /* Revision (R) */ 1244#define S_PRIdRev 0 /* Revision (R) */
1245#define M_PRIdRev (0xff << S_PRIdRev) 1245#define M_PRIdRev (0xff << S_PRIdRev)
1246 1246
1247#define M_PRId0Fields 0x00000000 1247#define M_PRId0Fields 0x00000000
1248#define M_PRIdRFields 0xffffffff 1248#define M_PRIdRFields 0xffffffff
1249/* 1249/*
1250 * Values in the Company ID field 1250 * Values in the Company ID field
1251 */ 1251 */
1252#define K_PRIdCoID_MIPS 1 1252#define K_PRIdCoID_MIPS 1
1253#define K_PRIdCoID_Broadcom 2 1253#define K_PRIdCoID_Broadcom 2
1254#define K_PRIdCoID_Alchemy 3 1254#define K_PRIdCoID_Alchemy 3
1255#define K_PRIdCoID_SiByte 4 1255#define K_PRIdCoID_SiByte 4
@@ -1261,27 +1261,27 @@
1261/* 1261/*
1262 * Values in the implementation number field 1262 * Values in the implementation number field
1263 */ 1263 */
1264#define K_PRIdImp_Jade 0x80 1264#define K_PRIdImp_Jade 0x80
1265#define K_PRIdImp_Opal 0x81 1265#define K_PRIdImp_Opal 0x81
1266#define K_PRIdImp_Ruby 0x82 1266#define K_PRIdImp_Ruby 0x82
1267#define K_PRIdImp_JadeLite 0x83 1267#define K_PRIdImp_JadeLite 0x83
1268#define K_PRIdImp_4KEc 0x84 /* Emerald with TLB MMU */ 1268#define K_PRIdImp_4KEc 0x84 /* Emerald with TLB MMU */
1269#define K_PRIdImp_4KEmp 0x85 /* Emerald with FM MMU */ 1269#define K_PRIdImp_4KEmp 0x85 /* Emerald with FM MMU */
1270#define K_PRIdImp_4KSc 0x86 /* Coral */ 1270#define K_PRIdImp_4KSc 0x86 /* Coral */
1271 1271
1272#define K_PRIdImp_R3000 0x01 1272#define K_PRIdImp_R3000 0x01
1273#define K_PRIdImp_R4000 0x04 1273#define K_PRIdImp_R4000 0x04
1274#define K_PRIdImp_R10000 0x09 1274#define K_PRIdImp_R10000 0x09
1275#define K_PRIdImp_R4300 0x0b 1275#define K_PRIdImp_R4300 0x0b
1276#define K_PRIdImp_R5000 0x23 1276#define K_PRIdImp_R5000 0x23
1277#define K_PRIdImp_R5200 0x28 1277#define K_PRIdImp_R5200 0x28
1278#define K_PRIdImp_R5400 0x54 1278#define K_PRIdImp_R5400 0x54
1279 1279
1280/* 1280/*
1281 ************************************************************************ 1281 ************************************************************************
1282 * C O N F I G R E G I S T E R ( 1 6 ) * 1282 * C O N F I G R E G I S T E R ( 1 6 ) *
1283 ************************************************************************ 1283 ************************************************************************
1284 * 1284 *
1285 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1285 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1286 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 1286 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
1287 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1287 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
@@ -1290,24 +1290,24 @@
1290 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1290 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1291 */ 1291 */
1292 1292
1293#define C0_Config $16 1293#define C0_Config $16
1294#define R_C0_Config 16 1294#define R_C0_Config 16
1295#define C0_CONFIG C0_Config /* OBSOLETE - DO NOT USE IN NEW CODE */ 1295#define C0_CONFIG C0_Config /* OBSOLETE - DO NOT USE IN NEW CODE */
1296 1296
1297#define S_ConfigMore 31 /* Additional config registers present (R) */ 1297#define S_ConfigMore 31 /* Additional config registers present (R) */
1298#define M_ConfigMore (0x1 << S_ConfigMore) 1298#define M_ConfigMore (0x1 << S_ConfigMore)
1299#define S_ConfigImpl 16 /* Implementation-specific fields */ 1299#define S_ConfigImpl 16 /* Implementation-specific fields */
1300#define M_ConfigImpl (0x7fff << S_ConfigImpl) 1300#define M_ConfigImpl (0x7fff << S_ConfigImpl)
1301#define S_ConfigBE 15 /* Denotes big-endian operation (R) */ 1301#define S_ConfigBE 15 /* Denotes big-endian operation (R) */
1302#define M_ConfigBE (0x1 << S_ConfigBE) 1302#define M_ConfigBE (0x1 << S_ConfigBE)
1303#define S_ConfigAT 13 /* Architecture type (R) */ 1303#define S_ConfigAT 13 /* Architecture type (R) */
1304#define M_ConfigAT (0x3 << S_ConfigAT) 1304#define M_ConfigAT (0x3 << S_ConfigAT)
1305#define S_ConfigAR 10 /* Architecture revision (R) */ 1305#define S_ConfigAR 10 /* Architecture revision (R) */
1306#define M_ConfigAR (0x7 << S_ConfigAR) 1306#define M_ConfigAR (0x7 << S_ConfigAR)
1307#define S_ConfigMT 7 /* MMU Type (R) */ 1307#define S_ConfigMT 7 /* MMU Type (R) */
1308#define M_ConfigMT (0x7 << S_ConfigMT) 1308#define M_ConfigMT (0x7 << S_ConfigMT)
1309#define S_ConfigK0 0 /* Kseg0 coherency algorithm (R/W) */ 1309#define S_ConfigK0 0 /* Kseg0 coherency algorithm (R/W) */
1310#define M_ConfigK0 (0x7 << S_ConfigK0) 1310#define M_ConfigK0 (0x7 << S_ConfigK0)
1311 1311
1312/* 1312/*
1313 * The following definitions are technically part of the "reserved for 1313 * The following definitions are technically part of the "reserved for
@@ -1316,35 +1316,35 @@
1316 * references. For that reason, they are included here, but may be 1316 * references. For that reason, they are included here, but may be
1317 * overridden by true implementation-specific definitions 1317 * overridden by true implementation-specific definitions
1318 */ 1318 */
1319#define S_ConfigK23 28 /* Kseg2/3 coherency algorithm (FM MMU only) (R/W) */ 1319#define S_ConfigK23 28 /* Kseg2/3 coherency algorithm (FM MMU only) (R/W) */
1320#define M_ConfigK23 (0x7 << S_ConfigK23) 1320#define M_ConfigK23 (0x7 << S_ConfigK23)
1321#define S_ConfigKU 25 /* Kuseg coherency algorithm (FM MMU only) (R/W) */ 1321#define S_ConfigKU 25 /* Kuseg coherency algorithm (FM MMU only) (R/W) */
1322#define M_ConfigKU (0x7 << S_ConfigKU) 1322#define M_ConfigKU (0x7 << S_ConfigKU)
1323 1323
1324#define M_Config0Fields 0x00000078 1324#define M_Config0Fields 0x00000078
1325#define M_ConfigRFields 0x8000ff80 1325#define M_ConfigRFields 0x8000ff80
1326 1326
1327/* 1327/*
1328 * Values in the AT field 1328 * Values in the AT field
1329 */ 1329 */
1330#define K_ConfigAT_MIPS32 0 /* MIPS32 */ 1330#define K_ConfigAT_MIPS32 0 /* MIPS32 */
1331#define K_ConfigAT_MIPS64S 1 /* MIPS64 with 32-bit addresses */ 1331#define K_ConfigAT_MIPS64S 1 /* MIPS64 with 32-bit addresses */
1332#define K_ConfigAT_MIPS64 2 /* MIPS64 with 32/64-bit addresses */ 1332#define K_ConfigAT_MIPS64 2 /* MIPS64 with 32/64-bit addresses */
1333 1333
1334/* 1334/*
1335 * Values in the MT field 1335 * Values in the MT field
1336 */ 1336 */
1337#define K_ConfigMT_NoMMU 0 /* No MMU */ 1337#define K_ConfigMT_NoMMU 0 /* No MMU */
1338#define K_ConfigMT_TLBMMU 1 /* Standard TLB MMU */ 1338#define K_ConfigMT_TLBMMU 1 /* Standard TLB MMU */
1339#define K_ConfigMT_BATMMU 2 /* Standard BAT MMU */ 1339#define K_ConfigMT_BATMMU 2 /* Standard BAT MMU */
1340#define K_ConfigMT_FMMMU 3 /* Standard Fixed Mapping MMU */ 1340#define K_ConfigMT_FMMMU 3 /* Standard Fixed Mapping MMU */
1341 1341
1342 1342
1343/* 1343/*
1344 ************************************************************************ 1344 ************************************************************************
1345 * C O N F I G 1 R E G I S T E R ( 1 6, SELECT 1 ) * 1345 * C O N F I G 1 R E G I S T E R ( 1 6, SELECT 1 ) *
1346 ************************************************************************ 1346 ************************************************************************
1347 * 1347 *
1348 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1348 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1349 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 1349 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
1350 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1350 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
@@ -1353,79 +1353,79 @@
1353 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1353 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1354 */ 1354 */
1355 1355
1356#define C0_Config1 $16,1 1356#define C0_Config1 $16,1
1357#define R_C0_Config1 16 1357#define R_C0_Config1 16
1358 1358
1359#define S_Config1More 31 /* Additional Config registers present (R) */ 1359#define S_Config1More 31 /* Additional Config registers present (R) */
1360#define M_Config1More (0x1 << S_Config1More) 1360#define M_Config1More (0x1 << S_Config1More)
1361#define S_Config1MMUSize 25 /* Number of MMU entries - 1 (R) */ 1361#define S_Config1MMUSize 25 /* Number of MMU entries - 1 (R) */
1362#define M_Config1MMUSize (0x3f << S_Config1MMUSize) 1362#define M_Config1MMUSize (0x3f << S_Config1MMUSize)
1363#define S_Config1IS 22 /* Icache sets per way (R) */ 1363#define S_Config1IS 22 /* Icache sets per way (R) */
1364#define M_Config1IS (0x7 << S_Config1IS) 1364#define M_Config1IS (0x7 << S_Config1IS)
1365#define S_Config1IL 19 /* Icache line size (R) */ 1365#define S_Config1IL 19 /* Icache line size (R) */
1366#define M_Config1IL (0x7 << S_Config1IL) 1366#define M_Config1IL (0x7 << S_Config1IL)
1367#define S_Config1IA 16 /* Icache associativity - 1 (R) */ 1367#define S_Config1IA 16 /* Icache associativity - 1 (R) */
1368#define M_Config1IA (0x7 << S_Config1IA) 1368#define M_Config1IA (0x7 << S_Config1IA)
1369#define S_Config1DS 13 /* Dcache sets per way (R) */ 1369#define S_Config1DS 13 /* Dcache sets per way (R) */
1370#define M_Config1DS (0x7 << S_Config1DS) 1370#define M_Config1DS (0x7 << S_Config1DS)
1371#define S_Config1DL 10 /* Dcache line size (R) */ 1371#define S_Config1DL 10 /* Dcache line size (R) */
1372#define M_Config1DL (0x7 << S_Config1DL) 1372#define M_Config1DL (0x7 << S_Config1DL)
1373#define S_Config1DA 7 /* Dcache associativity (R) */ 1373#define S_Config1DA 7 /* Dcache associativity (R) */
1374#define M_Config1DA (0x7 << S_Config1DA) 1374#define M_Config1DA (0x7 << S_Config1DA)
1375#define S_Config1C2 6 /* Coprocessor 2 present (R) */ 1375#define S_Config1C2 6 /* Coprocessor 2 present (R) */
1376#define M_Config1C2 (0x1 << S_Config1C2) 1376#define M_Config1C2 (0x1 << S_Config1C2)
1377#define S_Config1MD 5 /* Denotes MDMX present (R) */ 1377#define S_Config1MD 5 /* Denotes MDMX present (R) */
1378#define M_Config1MD (0x1 << S_Config1MD) 1378#define M_Config1MD (0x1 << S_Config1MD)
1379#define S_Config1PC 4 /* Denotes performance counters present (R) */ 1379#define S_Config1PC 4 /* Denotes performance counters present (R) */
1380#define M_Config1PC (0x1 << S_Config1PC) 1380#define M_Config1PC (0x1 << S_Config1PC)
1381#define S_Config1WR 3 /* Denotes watch registers present (R) */ 1381#define S_Config1WR 3 /* Denotes watch registers present (R) */
1382#define M_Config1WR (0x1 << S_Config1WR) 1382#define M_Config1WR (0x1 << S_Config1WR)
1383#define S_Config1CA 2 /* Denotes MIPS-16 present (R) */ 1383#define S_Config1CA 2 /* Denotes MIPS-16 present (R) */
1384#define M_Config1CA (0x1 << S_Config1CA) 1384#define M_Config1CA (0x1 << S_Config1CA)
1385#define S_Config1EP 1 /* Denotes EJTAG present (R) */ 1385#define S_Config1EP 1 /* Denotes EJTAG present (R) */
1386#define M_Config1EP (0x1 << S_Config1EP) 1386#define M_Config1EP (0x1 << S_Config1EP)
1387#define S_Config1FP 0 /* Denotes floating point present (R) */ 1387#define S_Config1FP 0 /* Denotes floating point present (R) */
1388#define M_Config1FP (0x1 << S_Config1FP) 1388#define M_Config1FP (0x1 << S_Config1FP)
1389 1389
1390#define M_Config10Fields 0x00000060 1390#define M_Config10Fields 0x00000060
1391#define M_Config1RFields 0x7fffff9f 1391#define M_Config1RFields 0x7fffff9f
1392 1392
1393/* 1393/*
1394 * The following macro generates a table that is indexed 1394 * The following macro generates a table that is indexed
1395 * by the Icache or Dcache sets field in Config1 and 1395 * by the Icache or Dcache sets field in Config1 and
1396 * contains the decoded value of sets per way 1396 * contains the decoded value of sets per way
1397 */ 1397 */
1398#define Config1CacheSets() \ 1398#define Config1CacheSets() \
1399 HALF(64); \ 1399 HALF(64); \
1400 HALF(128); \ 1400 HALF(128); \
1401 HALF(256); \ 1401 HALF(256); \
1402 HALF(512); \ 1402 HALF(512); \
1403 HALF(1024); \ 1403 HALF(1024); \
1404 HALF(2048); \ 1404 HALF(2048); \
1405 HALF(4096); \ 1405 HALF(4096); \
1406 HALF(8192); 1406 HALF(8192);
1407 1407
1408/* 1408/*
1409 * The following macro generates a table that is indexed 1409 * The following macro generates a table that is indexed
1410 * by the Icache or Dcache line size field in Config1 and 1410 * by the Icache or Dcache line size field in Config1 and
1411 * contains the decoded value of the cache line size, in bytes 1411 * contains the decoded value of the cache line size, in bytes
1412 */ 1412 */
1413#define Config1CacheLineSize() \ 1413#define Config1CacheLineSize() \
1414 HALF(0); \ 1414 HALF(0); \
1415 HALF(4); \ 1415 HALF(4); \
1416 HALF(8); \ 1416 HALF(8); \
1417 HALF(16); \ 1417 HALF(16); \
1418 HALF(32); \ 1418 HALF(32); \
1419 HALF(64); \ 1419 HALF(64); \
1420 HALF(128); \ 1420 HALF(128); \
1421 HALF(256); 1421 HALF(256);
1422 1422
1423 1423
1424/* 1424/*
1425 ************************************************************************ 1425 ************************************************************************
1426 * C O N F I G 2 R E G I S T E R ( 1 6, SELECT 2 ) * 1426 * C O N F I G 2 R E G I S T E R ( 1 6, SELECT 2 ) *
1427 ************************************************************************ 1427 ************************************************************************
1428 * 1428 *
1429 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1429 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1430 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 1430 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
1431 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1431 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
@@ -1434,24 +1434,24 @@
1434 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1434 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1435 */ 1435 */
1436 1436
1437#define C0_Config2 $16,2 1437#define C0_Config2 $16,2
1438#define R_C0_Config2 16 1438#define R_C0_Config2 16
1439 1439
1440#define S_Config2More 31 /* Additional Config registers present (R) */ 1440#define S_Config2More 31 /* Additional Config registers present (R) */
1441#define M_Config2More (0x1 << S_Config2More) 1441#define M_Config2More (0x1 << S_Config2More)
1442#define S_Config2SM 1 /* Denotes SmartMIPS ASE present (R) */ 1442#define S_Config2SM 1 /* Denotes SmartMIPS ASE present (R) */
1443#define M_Config2SM (0x1 << S_Config2SM) 1443#define M_Config2SM (0x1 << S_Config2SM)
1444#define S_Config2TL 0 /* Denotes Tracing Logic present (R) */ 1444#define S_Config2TL 0 /* Denotes Tracing Logic present (R) */
1445#define M_Config2TL (0x1 << S_Config2TL) 1445#define M_Config2TL (0x1 << S_Config2TL)
1446 1446
1447#define M_Config20Fields 0xfffffffc 1447#define M_Config20Fields 0xfffffffc
1448#define M_Config2RFields 0x00000003 1448#define M_Config2RFields 0x00000003
1449 1449
1450/* 1450/*
1451 ************************************************************************ 1451 ************************************************************************
1452 * L L A D D R R E G I S T E R ( 1 7 ) * 1452 * L L A D D R R E G I S T E R ( 1 7 ) *
1453 ************************************************************************ 1453 ************************************************************************
1454 * 1454 *
1455 * 6 6 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1455 * 6 6 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1456 * 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 1456 * 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
1457 * +-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1457 * +-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
@@ -1459,21 +1459,21 @@
1459 * +-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1459 * +-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1460 */ 1460 */
1461 1461
1462#define C0_LLAddr $17 1462#define C0_LLAddr $17
1463#define R_C0_LLAddr 17 1463#define R_C0_LLAddr 17
1464#define C0_LLADDR C0_LLAddr /* OBSOLETE - DO NOT USE IN NEW CODE */ 1464#define C0_LLADDR C0_LLAddr /* OBSOLETE - DO NOT USE IN NEW CODE */
1465 1465
1466#define M_LLAddr0Fields 0x00000000 1466#define M_LLAddr0Fields 0x00000000
1467#define M_LLAddrRFields 0x00000000 1467#define M_LLAddrRFields 0x00000000
1468#define M_LLAddr0Fields64 UNS64Const(0x0000000000000000) 1468#define M_LLAddr0Fields64 UNS64Const(0x0000000000000000)
1469#define M_LLAddrRFields64 UNS64Const(0x0000000000000000) 1469#define M_LLAddrRFields64 UNS64Const(0x0000000000000000)
1470 1470
1471 1471
1472/* 1472/*
1473 ************************************************************************ 1473 ************************************************************************
1474 * W A T C H L O R E G I S T E R ( 1 8 ) * 1474 * W A T C H L O R E G I S T E R ( 1 8 ) *
1475 ************************************************************************ 1475 ************************************************************************
1476 * 1476 *
1477 * 6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1477 * 6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1478 * 3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 1478 * 3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
1479 * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1479 * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
@@ -1481,32 +1481,32 @@
1481 * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1481 * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1482 */ 1482 */
1483 1483
1484#define C0_WatchLo $18 1484#define C0_WatchLo $18
1485#define R_C0_WatchLo 18 1485#define R_C0_WatchLo 18
1486#define C0_WATCHLO C0_WatchLo /* OBSOLETE - DO NOT USE IN NEW CODE */ 1486#define C0_WATCHLO C0_WatchLo /* OBSOLETE - DO NOT USE IN NEW CODE */
1487 1487
1488#define S_WatchLoVAddr 3 /* Watch virtual address (R/W) */ 1488#define S_WatchLoVAddr 3 /* Watch virtual address (R/W) */
1489#define M_WatchLoVAddr (0x1fffffff << S_WatchLoVAddr) 1489#define M_WatchLoVAddr (0x1fffffff << S_WatchLoVAddr)
1490#define S_WatchLoI 2 /* Enable Istream watch (R/W) */ 1490#define S_WatchLoI 2 /* Enable Istream watch (R/W) */
1491#define M_WatchLoI (0x1 << S_WatchLoI) 1491#define M_WatchLoI (0x1 << S_WatchLoI)
1492#define S_WatchLoR 1 /* Enable data read watch (R/W) */ 1492#define S_WatchLoR 1 /* Enable data read watch (R/W) */
1493#define M_WatchLoR (0x1 << S_WatchLoR) 1493#define M_WatchLoR (0x1 << S_WatchLoR)
1494#define S_WatchLoW 0 /* Enable data write watch (R/W) */ 1494#define S_WatchLoW 0 /* Enable data write watch (R/W) */
1495#define M_WatchLoW (0x1 << S_WatchLoW) 1495#define M_WatchLoW (0x1 << S_WatchLoW)
1496 1496
1497#define M_WatchLo0Fields 0x00000000 1497#define M_WatchLo0Fields 0x00000000
1498#define M_WatchLoRFields 0x00000000 1498#define M_WatchLoRFields 0x00000000
1499#define M_WatchLo0Fields64 UNS64Const(0x0000000000000000) 1499#define M_WatchLo0Fields64 UNS64Const(0x0000000000000000)
1500#define M_WatchLoRFields64 UNS64Const(0x0000000000000000) 1500#define M_WatchLoRFields64 UNS64Const(0x0000000000000000)
1501 1501
1502#define M_WatchLoEnables (M_WatchLoI | M_WatchLoR | M_WatchLoW) 1502#define M_WatchLoEnables (M_WatchLoI | M_WatchLoR | M_WatchLoW)
1503 1503
1504 1504
1505/* 1505/*
1506 ************************************************************************ 1506 ************************************************************************
1507 * W A T C H H I R E G I S T E R ( 1 9 ) * 1507 * W A T C H H I R E G I S T E R ( 1 9 ) *
1508 ************************************************************************ 1508 ************************************************************************
1509 * 1509 *
1510 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1510 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1511 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 1511 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
1512 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1512 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
@@ -1514,28 +1514,28 @@
1514 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1514 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1515 */ 1515 */
1516 1516
1517#define C0_WatchHi $19 1517#define C0_WatchHi $19
1518#define R_C0_WatchHi 19 1518#define R_C0_WatchHi 19
1519#define C0_WATCHHI C0_WatchHi /* OBSOLETE - DO NOT USE IN NEW CODE */ 1519#define C0_WATCHHI C0_WatchHi /* OBSOLETE - DO NOT USE IN NEW CODE */
1520 1520
1521#define S_WatchHiM 31 /* Denotes additional Watch registers present (R) */ 1521#define S_WatchHiM 31 /* Denotes additional Watch registers present (R) */
1522#define M_WatchHiM (0x1 << S_WatchHiM) 1522#define M_WatchHiM (0x1 << S_WatchHiM)
1523#define S_WatchHiG 30 /* Enable ASID-independent Watch match (R/W) */ 1523#define S_WatchHiG 30 /* Enable ASID-independent Watch match (R/W) */
1524#define M_WatchHiG (0x1 << S_WatchHiG) 1524#define M_WatchHiG (0x1 << S_WatchHiG)
1525#define S_WatchHiASID 16 /* ASID value to match (R/W) */ 1525#define S_WatchHiASID 16 /* ASID value to match (R/W) */
1526#define M_WatchHiASID (0xff << S_WatchHiASID) 1526#define M_WatchHiASID (0xff << S_WatchHiASID)
1527#define S_WatchHiMask 3 /* Address inhibit mask (R/W) */ 1527#define S_WatchHiMask 3 /* Address inhibit mask (R/W) */
1528#define M_WatchHiMask (0x1ff << S_WatchHiMask) 1528#define M_WatchHiMask (0x1ff << S_WatchHiMask)
1529 1529
1530#define M_WatchHi0Fields 0x3f00f007 1530#define M_WatchHi0Fields 0x3f00f007
1531#define M_WatchHiRFields 0x80000000 1531#define M_WatchHiRFields 0x80000000
1532 1532
1533 1533
1534/* 1534/*
1535 ************************************************************************ 1535 ************************************************************************
1536 * X C O N T E X T R E G I S T E R ( 2 0 ) * 1536 * X C O N T E X T R E G I S T E R ( 2 0 ) *
1537 ************************************************************************ 1537 ************************************************************************
1538 * 1538 *
1539 * 6 // 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1539 * 6 // 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1540 * 3 // 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 1540 * 3 // 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
1541 * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1541 * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
@@ -1543,21 +1543,21 @@
1543 * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1543 * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1544 */ 1544 */
1545 1545
1546#define C0_XContext $20 1546#define C0_XContext $20
1547#define R_C0_XContext 20 1547#define R_C0_XContext 20
1548#define C0_EXTCTXT C0_XContext /* OBSOLETE - DO NOT USE IN NEW CODE */ 1548#define C0_EXTCTXT C0_XContext /* OBSOLETE - DO NOT USE IN NEW CODE */
1549 1549
1550#define S_XContextBadVPN2 4 /* BadVPN2 (R) */ 1550#define S_XContextBadVPN2 4 /* BadVPN2 (R) */
1551#define S_XContextBadVPN S_XContextBadVPN2 1551#define S_XContextBadVPN S_XContextBadVPN2
1552 1552
1553#define M_XContext0Fields 0x0000000f 1553#define M_XContext0Fields 0x0000000f
1554 1554
1555 1555
1556/* 1556/*
1557 ************************************************************************ 1557 ************************************************************************
1558 * D E B U G R E G I S T E R ( 2 3 ) * 1558 * D E B U G R E G I S T E R ( 2 3 ) *
1559 ************************************************************************ 1559 ************************************************************************
1560 * 1560 *
1561 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1561 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1562 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 1562 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
1563 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1563 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
@@ -1572,67 +1572,67 @@
1572 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1572 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1573 */ 1573 */
1574 1574
1575#define C0_Debug $23 /* EJTAG */ 1575#define C0_Debug $23 /* EJTAG */
1576#define R_C0_Debug 23 1576#define R_C0_Debug 23
1577 1577
1578#define S_DebugDBD 31 /* Debug branch delay (R) */ 1578#define S_DebugDBD 31 /* Debug branch delay (R) */
1579#define M_DebugDBD (0x1 << S_DebugDBD) 1579#define M_DebugDBD (0x1 << S_DebugDBD)
1580#define S_DebugDM 30 /* Debug mode (R) */ 1580#define S_DebugDM 30 /* Debug mode (R) */
1581#define M_DebugDM (0x1 << S_DebugDM) 1581#define M_DebugDM (0x1 << S_DebugDM)
1582#define S_DebugNoDCR 29 /* No debug control register present (R) */ 1582#define S_DebugNoDCR 29 /* No debug control register present (R) */
1583#define M_DebugNoDCR (0x1 << S_DebugNoDCR) 1583#define M_DebugNoDCR (0x1 << S_DebugNoDCR)
1584#define S_DebugLSNM 28 /* Load/Store Normal Memory (R/W) */ 1584#define S_DebugLSNM 28 /* Load/Store Normal Memory (R/W) */
1585#define M_DebugLSNM (0x1 << S_DebugLSNM) 1585#define M_DebugLSNM (0x1 << S_DebugLSNM)
1586#define S_DebugDoze 27 /* Doze (R) */ 1586#define S_DebugDoze 27 /* Doze (R) */
1587#define M_DebugDoze (0x1 << S_DebugDoze) 1587#define M_DebugDoze (0x1 << S_DebugDoze)
1588#define S_DebugHalt 26 /* Halt (R) */ 1588#define S_DebugHalt 26 /* Halt (R) */
1589#define M_DebugHalt (0x1 << S_DebugHalt) 1589#define M_DebugHalt (0x1 << S_DebugHalt)
1590#define S_DebugCountDM 25 /* Count register behavior in debug mode (R/W) */ 1590#define S_DebugCountDM 25 /* Count register behavior in debug mode (R/W) */
1591#define M_DebugCountDM (0x1 << S_DebugCountDM) 1591#define M_DebugCountDM (0x1 << S_DebugCountDM)
1592#define S_DebugIBusEP 24 /* Imprecise Instn Bus Error Pending (R/W) */ 1592#define S_DebugIBusEP 24 /* Imprecise Instn Bus Error Pending (R/W) */
1593#define M_DebugIBusEP (0x1 << S_DebugIBusEP) 1593#define M_DebugIBusEP (0x1 << S_DebugIBusEP)
1594#define S_DebugMCheckP 23 /* Imprecise Machine Check Pending (R/W) */ 1594#define S_DebugMCheckP 23 /* Imprecise Machine Check Pending (R/W) */
1595#define M_DebugMCheckP (0x1 << S_DebugMCheckP) 1595#define M_DebugMCheckP (0x1 << S_DebugMCheckP)
1596#define S_DebugCacheEP 22 /* Imprecise Cache Error Pending (R/W) */ 1596#define S_DebugCacheEP 22 /* Imprecise Cache Error Pending (R/W) */
1597#define M_DebugCacheEP (0x1 << S_DebugCacheEP) 1597#define M_DebugCacheEP (0x1 << S_DebugCacheEP)
1598#define S_DebugDBusEP 21 /* Imprecise Data Bus Error Pending (R/W) */ 1598#define S_DebugDBusEP 21 /* Imprecise Data Bus Error Pending (R/W) */
1599#define M_DebugDBusEP (0x1 << S_DebugDBusEP) 1599#define M_DebugDBusEP (0x1 << S_DebugDBusEP)
1600#define S_DebugIEXI 20 /* Imprecise Exception Inhibit (R/W) */ 1600#define S_DebugIEXI 20 /* Imprecise Exception Inhibit (R/W) */
1601#define M_DebugIEXI (0x1 << S_DebugIEXI) 1601#define M_DebugIEXI (0x1 << S_DebugIEXI)
1602#define S_DebugDDBSImpr 19 /* Debug data break store imprecise (R) */ 1602#define S_DebugDDBSImpr 19 /* Debug data break store imprecise (R) */
1603#define M_DebugDDBSImpr (0x1 << S_DebugDDBSImpr) 1603#define M_DebugDDBSImpr (0x1 << S_DebugDDBSImpr)
1604#define S_DebugDDBLImpr 18 /* Debug data break load imprecise (R) */ 1604#define S_DebugDDBLImpr 18 /* Debug data break load imprecise (R) */
1605#define M_DebugDDBLImpr (0x1 << S_DebugDDBLImpr) 1605#define M_DebugDDBLImpr (0x1 << S_DebugDDBLImpr)
1606#define S_DebugEJTAGver 15 /* EJTAG version number (R) */ 1606#define S_DebugEJTAGver 15 /* EJTAG version number (R) */
1607#define M_DebugEJTAGver (0x7 << S_DebugEJTAGver) 1607#define M_DebugEJTAGver (0x7 << S_DebugEJTAGver)
1608#define S_DebugDExcCode 10 /* Debug exception code (R) */ 1608#define S_DebugDExcCode 10 /* Debug exception code (R) */
1609#define M_DebugDExcCode (0x1f << S_DebugDExcCode) 1609#define M_DebugDExcCode (0x1f << S_DebugDExcCode)
1610#define S_DebugNoSSt 9 /* No single step implemented (R) */ 1610#define S_DebugNoSSt 9 /* No single step implemented (R) */
1611#define M_DebugNoSSt (0x1 << S_DebugNoSSt) 1611#define M_DebugNoSSt (0x1 << S_DebugNoSSt)
1612#define S_DebugSSt 8 /* Single step enable (R/W) */ 1612#define S_DebugSSt 8 /* Single step enable (R/W) */
1613#define M_DebugSSt (0x1 << S_DebugSSt) 1613#define M_DebugSSt (0x1 << S_DebugSSt)
1614#define S_DebugDINT 5 /* Debug interrupt (R) */ 1614#define S_DebugDINT 5 /* Debug interrupt (R) */
1615#define M_DebugDINT (0x1 << S_DebugDINT) 1615#define M_DebugDINT (0x1 << S_DebugDINT)
1616#define S_DebugDIB 4 /* Debug instruction break (R) */ 1616#define S_DebugDIB 4 /* Debug instruction break (R) */
1617#define M_DebugDIB (0x1 << S_DebugDIB) 1617#define M_DebugDIB (0x1 << S_DebugDIB)
1618#define S_DebugDDBS 3 /* Debug data break store (R) */ 1618#define S_DebugDDBS 3 /* Debug data break store (R) */
1619#define M_DebugDDBS (0x1 << S_DebugDDBS) 1619#define M_DebugDDBS (0x1 << S_DebugDDBS)
1620#define S_DebugDDBL 2 /* Debug data break load (R) */ 1620#define S_DebugDDBL 2 /* Debug data break load (R) */
1621#define M_DebugDDBL (0x1 << S_DebugDDBL) 1621#define M_DebugDDBL (0x1 << S_DebugDDBL)
1622#define S_DebugDBp 1 /* Debug breakpoint (R) */ 1622#define S_DebugDBp 1 /* Debug breakpoint (R) */
1623#define M_DebugDBp (0x1 << S_DebugDBp) 1623#define M_DebugDBp (0x1 << S_DebugDBp)
1624#define S_DebugDSS 0 /* Debug single step (R) */ 1624#define S_DebugDSS 0 /* Debug single step (R) */
1625#define M_DebugDSS (0x1 << S_DebugDSS) 1625#define M_DebugDSS (0x1 << S_DebugDSS)
1626 1626
1627#define M_Debug0Fields 0x01f000c0 1627#define M_Debug0Fields 0x01f000c0
1628#define M_DebugRFields 0xec0ffe3f 1628#define M_DebugRFields 0xec0ffe3f
1629 1629
1630 1630
1631/* 1631/*
1632 ************************************************************************ 1632 ************************************************************************
1633 * D E P C R E G I S T E R ( 2 4 ) * 1633 * D E P C R E G I S T E R ( 2 4 ) *
1634 ************************************************************************ 1634 ************************************************************************
1635 * 1635 *
1636 * 6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1636 * 6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1637 * 3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 1637 * 3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
1638 * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1638 * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
@@ -1641,20 +1641,20 @@
1641 */ 1641 */
1642 1642
1643 1643
1644#define C0_DEPC $24 1644#define C0_DEPC $24
1645#define R_C0_DEPC 24 1645#define R_C0_DEPC 24
1646 1646
1647#define M_DEEPC0Fields 0x00000000 1647#define M_DEEPC0Fields 0x00000000
1648#define M_DEEPCRFields 0x00000000 1648#define M_DEEPCRFields 0x00000000
1649#define M_DEEPC0Fields64 UNS64Const(0x0000000000000000) 1649#define M_DEEPC0Fields64 UNS64Const(0x0000000000000000)
1650#define M_DEEPCRFields64 UNS64Const(0x0000000000000000) 1650#define M_DEEPCRFields64 UNS64Const(0x0000000000000000)
1651 1651
1652 1652
1653/* 1653/*
1654 ************************************************************************ 1654 ************************************************************************
1655 * P E R F C N T R E G I S T E R ( 2 5 ) * 1655 * P E R F C N T R E G I S T E R ( 2 5 ) *
1656 ************************************************************************ 1656 ************************************************************************
1657 * 1657 *
1658 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1658 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1659 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 1659 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
1660 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1660 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
@@ -1671,35 +1671,35 @@
1671 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1671 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1672 */ 1672 */
1673 1673
1674#define C0_PerfCnt $25 1674#define C0_PerfCnt $25
1675#define R_C0_PerfCnt 25 1675#define R_C0_PerfCnt 25
1676#define C0_PRFCNT0 C0_PerfCnt /* OBSOLETE - DO NOT USE IN NEW CODE */ 1676#define C0_PRFCNT0 C0_PerfCnt /* OBSOLETE - DO NOT USE IN NEW CODE */
1677#define C0_PRFCNT1 C0_PerfCnt /* OBSOLETE - DO NOT USE IN NEW CODE */ 1677#define C0_PRFCNT1 C0_PerfCnt /* OBSOLETE - DO NOT USE IN NEW CODE */
1678 1678
1679#define S_PerfCntM 31 /* More performance counters exist (R) */ 1679#define S_PerfCntM 31 /* More performance counters exist (R) */
1680#define M_PerfCntM (1 << S_PerfCntM) 1680#define M_PerfCntM (1 << S_PerfCntM)
1681#define S_PerfCntEvent 5 /* Enabled event (R/W) */ 1681#define S_PerfCntEvent 5 /* Enabled event (R/W) */
1682#define M_PerfCntEvent (0x3f << S_PerfCntEvent) 1682#define M_PerfCntEvent (0x3f << S_PerfCntEvent)
1683#define S_PerfCntIE 4 /* Interrupt Enable (R/W) */ 1683#define S_PerfCntIE 4 /* Interrupt Enable (R/W) */
1684#define M_PerfCntIE (1 << S_PerfCntIE) 1684#define M_PerfCntIE (1 << S_PerfCntIE)
1685#define S_PerfCntU 3 /* Enable counting in User Mode (R/W) */ 1685#define S_PerfCntU 3 /* Enable counting in User Mode (R/W) */
1686#define M_PerfCntU (1 << S_PerfCntU) 1686#define M_PerfCntU (1 << S_PerfCntU)
1687#define S_PerfCntS 2 /* Enable counting in Supervisor Mode (R/W) */ 1687#define S_PerfCntS 2 /* Enable counting in Supervisor Mode (R/W) */
1688#define M_PerfCntS (1 << S_PerfCntS) 1688#define M_PerfCntS (1 << S_PerfCntS)
1689#define S_PerfCntK 1 /* Enable counting in Kernel Mode (R/W) */ 1689#define S_PerfCntK 1 /* Enable counting in Kernel Mode (R/W) */
1690#define M_PerfCntK (1 << S_PerfCntK) 1690#define M_PerfCntK (1 << S_PerfCntK)
1691#define S_PerfCntEXL 0 /* Enable counting while EXL==1 (R/W) */ 1691#define S_PerfCntEXL 0 /* Enable counting while EXL==1 (R/W) */
1692#define M_PerfCntEXL (1 << S_PerfCntEXL) 1692#define M_PerfCntEXL (1 << S_PerfCntEXL)
1693 1693
1694#define M_PerfCnt0Fields 0x7ffff800 1694#define M_PerfCnt0Fields 0x7ffff800
1695#define M_PerfCntRFields 0x80000000 1695#define M_PerfCntRFields 0x80000000
1696 1696
1697 1697
1698/* 1698/*
1699 ************************************************************************ 1699 ************************************************************************
1700 * E R R C T L R E G I S T E R ( 2 6 ) * 1700 * E R R C T L R E G I S T E R ( 2 6 ) *
1701 ************************************************************************ 1701 ************************************************************************
1702 * 1702 *
1703 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1703 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1704 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 1704 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
1705 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1705 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
@@ -1707,20 +1707,20 @@
1707 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1707 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1708 */ 1708 */
1709 1709
1710#define C0_ErrCtl $26 1710#define C0_ErrCtl $26
1711#define R_C0_ErrCtl 26 1711#define R_C0_ErrCtl 26
1712#define C0_ECC $26 /* OBSOLETE - DO NOT USE IN NEW CODE */ 1712#define C0_ECC $26 /* OBSOLETE - DO NOT USE IN NEW CODE */
1713#define R_C0_ECC 26 /* OBSOLETE - DO NOT USE IN NEW CODE */ 1713#define R_C0_ECC 26 /* OBSOLETE - DO NOT USE IN NEW CODE */
1714 1714
1715#define M_ErrCtl0Fields 0x00000000 1715#define M_ErrCtl0Fields 0x00000000
1716#define M_ErrCtlRFields 0x00000000 1716#define M_ErrCtlRFields 0x00000000
1717 1717
1718 1718
1719/* 1719/*
1720 ************************************************************************ 1720 ************************************************************************
1721 * C A C H E E R R R E G I S T E R ( 2 7 ) * CacheErr 1721 * C A C H E E R R R E G I S T E R ( 2 7 ) * CacheErr
1722 ************************************************************************ 1722 ************************************************************************
1723 * 1723 *
1724 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1724 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1725 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 1725 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
1726 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1726 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
@@ -1728,19 +1728,19 @@
1728 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1728 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1729 */ 1729 */
1730 1730
1731#define C0_CacheErr $27 1731#define C0_CacheErr $27
1732#define R_C0_CacheErr 27 1732#define R_C0_CacheErr 27
1733#define C0_CACHE_ERR C0_CacheErr /* OBSOLETE - DO NOT USE IN NEW CODE */ 1733#define C0_CACHE_ERR C0_CacheErr /* OBSOLETE - DO NOT USE IN NEW CODE */
1734 1734
1735#define M_CacheErr0Fields 0x00000000 1735#define M_CacheErr0Fields 0x00000000
1736#define M_CachErrRFields 0x00000000 1736#define M_CachErrRFields 0x00000000
1737 1737
1738 1738
1739/* 1739/*
1740 ************************************************************************ 1740 ************************************************************************
1741 * T A G L O R E G I S T E R ( 2 8 ) * TagLo 1741 * T A G L O R E G I S T E R ( 2 8 ) * TagLo
1742 ************************************************************************ 1742 ************************************************************************
1743 * 1743 *
1744 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1744 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1745 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 1745 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
1746 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1746 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
@@ -1748,9 +1748,9 @@
1748 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1748 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1749 */ 1749 */
1750 1750
1751#define C0_TagLo $28 1751#define C0_TagLo $28
1752#define R_C0_TagLo 28 1752#define R_C0_TagLo 28
1753#define C0_TAGLO C0_TagLo /* OBSOLETE - DO NOT USE IN NEW CODE */ 1753#define C0_TAGLO C0_TagLo /* OBSOLETE - DO NOT USE IN NEW CODE */
1754 1754
1755/* 1755/*
1756 * Some implementations use separate TagLo registers for the 1756 * Some implementations use separate TagLo registers for the
@@ -1758,18 +1758,18 @@
1758 * definitions can be used in relevant code 1758 * definitions can be used in relevant code
1759 */ 1759 */
1760 1760
1761#define C0_ITagLo $28,0 1761#define C0_ITagLo $28,0
1762#define C0_DTagLo $28,2 1762#define C0_DTagLo $28,2
1763 1763
1764#define M_TagLo0Fields 0x00000000 1764#define M_TagLo0Fields 0x00000000
1765#define M_TagLoRFields 0x00000000 1765#define M_TagLoRFields 0x00000000
1766 1766
1767 1767
1768/* 1768/*
1769 ************************************************************************ 1769 ************************************************************************
1770 * D A T A L O R E G I S T E R ( 2 8, SELECT 1 ) * DataLo 1770 * D A T A L O R E G I S T E R ( 2 8, SELECT 1 ) * DataLo
1771 ************************************************************************ 1771 ************************************************************************
1772 * 1772 *
1773 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1773 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1774 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 1774 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
1775 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1775 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
@@ -1777,8 +1777,8 @@
1777 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1777 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1778 */ 1778 */
1779 1779
1780#define C0_DataLo $28,1 1780#define C0_DataLo $28,1
1781#define R_C0_DataLo 28 1781#define R_C0_DataLo 28
1782 1782
1783/* 1783/*
1784 * Some implementations use separate DataLo registers for the 1784 * Some implementations use separate DataLo registers for the
@@ -1786,18 +1786,18 @@
1786 * definitions can be used in relevant code 1786 * definitions can be used in relevant code
1787 */ 1787 */
1788 1788
1789#define C0_IDataLo $28,1 1789#define C0_IDataLo $28,1
1790#define C0_DDataLo $28,3 1790#define C0_DDataLo $28,3
1791 1791
1792#define M_DataLo0Fields 0x00000000 1792#define M_DataLo0Fields 0x00000000
1793#define M_DataLoRFields 0xffffffff 1793#define M_DataLoRFields 0xffffffff
1794 1794
1795 1795
1796/* 1796/*
1797 ************************************************************************ 1797 ************************************************************************
1798 * T A G H I R E G I S T E R ( 2 9 ) * TagHi 1798 * T A G H I R E G I S T E R ( 2 9 ) * TagHi
1799 ************************************************************************ 1799 ************************************************************************
1800 * 1800 *
1801 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1801 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1802 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 1802 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
1803 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1803 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
@@ -1805,9 +1805,9 @@
1805 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1805 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1806 */ 1806 */
1807 1807
1808#define C0_TagHi $29 1808#define C0_TagHi $29
1809#define R_C0_TagHi 29 1809#define R_C0_TagHi 29
1810#define C0_TAGHI C0_TagHi /* OBSOLETE - DO NOT USE IN NEW CODE */ 1810#define C0_TAGHI C0_TagHi /* OBSOLETE - DO NOT USE IN NEW CODE */
1811 1811
1812/* 1812/*
1813 * Some implementations use separate TagHi registers for the 1813 * Some implementations use separate TagHi registers for the
@@ -1815,18 +1815,18 @@
1815 * definitions can be used in relevant code 1815 * definitions can be used in relevant code
1816 */ 1816 */
1817 1817
1818#define C0_ITagHi $29,0 1818#define C0_ITagHi $29,0
1819#define C0_DTagHi $29,2 1819#define C0_DTagHi $29,2
1820 1820
1821#define M_TagHi0Fields 0x00000000 1821#define M_TagHi0Fields 0x00000000
1822#define M_TagHiRFields 0x00000000 1822#define M_TagHiRFields 0x00000000
1823 1823
1824 1824
1825/* 1825/*
1826 ************************************************************************ 1826 ************************************************************************
1827 * D A T A H I R E G I S T E R ( 2 9, SELECT 1 ) * DataHi 1827 * D A T A H I R E G I S T E R ( 2 9, SELECT 1 ) * DataHi
1828 ************************************************************************ 1828 ************************************************************************
1829 * 1829 *
1830 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1830 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1831 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 1831 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
1832 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1832 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
@@ -1834,8 +1834,8 @@
1834 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1834 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1835 */ 1835 */
1836 1836
1837#define C0_DataHi $29,1 1837#define C0_DataHi $29,1
1838#define R_C0_DataHi 29 1838#define R_C0_DataHi 29
1839 1839
1840/* 1840/*
1841 * Some implementations use separate DataHi registers for the 1841 * Some implementations use separate DataHi registers for the
@@ -1843,18 +1843,18 @@
1843 * definitions can be used in relevant code 1843 * definitions can be used in relevant code
1844 */ 1844 */
1845 1845
1846#define C0_IDataHi $29,1 1846#define C0_IDataHi $29,1
1847#define C0_DDataHi $29,3 1847#define C0_DDataHi $29,3
1848 1848
1849#define M_DataHi0Fields 0x00000000 1849#define M_DataHi0Fields 0x00000000
1850#define M_DataHiRFields 0xffffffff 1850#define M_DataHiRFields 0xffffffff
1851 1851
1852 1852
1853/* 1853/*
1854 ************************************************************************ 1854 ************************************************************************
1855 * E R R O R E P C R E G I S T E R ( 3 0 ) * 1855 * E R R O R E P C R E G I S T E R ( 3 0 ) *
1856 ************************************************************************ 1856 ************************************************************************
1857 * 1857 *
1858 * 6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1858 * 6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1859 * 3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 1859 * 3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
1860 * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1860 * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
@@ -1862,21 +1862,21 @@
1862 * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1862 * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1863 */ 1863 */
1864 1864
1865#define C0_ErrorEPC $30 1865#define C0_ErrorEPC $30
1866#define R_C0_ErrorEPC 30 1866#define R_C0_ErrorEPC 30
1867#define C0_ERROR_EPC C0_ErrorEPC /* OBSOLETE - DO NOT USE IN NEW CODE */ 1867#define C0_ERROR_EPC C0_ErrorEPC /* OBSOLETE - DO NOT USE IN NEW CODE */
1868 1868
1869#define M_ErrorEPC0Fields 0x00000000 1869#define M_ErrorEPC0Fields 0x00000000
1870#define M_ErrorEPCRFields 0x00000000 1870#define M_ErrorEPCRFields 0x00000000
1871#define M_ErrorEPC0Fields64 UNS64Const(0x0000000000000000) 1871#define M_ErrorEPC0Fields64 UNS64Const(0x0000000000000000)
1872#define M_ErrorEPCRFields64 UNS64Const(0x0000000000000000) 1872#define M_ErrorEPCRFields64 UNS64Const(0x0000000000000000)
1873 1873
1874 1874
1875/* 1875/*
1876 ************************************************************************ 1876 ************************************************************************
1877 * D E S A V E R E G I S T E R ( 3 1 ) * 1877 * D E S A V E R E G I S T E R ( 3 1 ) *
1878 ************************************************************************ 1878 ************************************************************************
1879 * 1879 *
1880 * 6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1880 * 6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1881 * 3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 1881 * 3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
1882 * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1882 * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
@@ -1884,13 +1884,13 @@
1884 * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1884 * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1885 */ 1885 */
1886 1886
1887#define C0_DESAVE $31 1887#define C0_DESAVE $31
1888#define R_C0_DESAVE 31 1888#define R_C0_DESAVE 31
1889 1889
1890#define M_DESAVE0Fields 0x00000000 1890#define M_DESAVE0Fields 0x00000000
1891#define M_DESAVERFields 0x00000000 1891#define M_DESAVERFields 0x00000000
1892#define M_DESAVE0Fields64 UNS64Const(0x0000000000000000) 1892#define M_DESAVE0Fields64 UNS64Const(0x0000000000000000)
1893#define M_DESAVERFields64 UNS64Const(0x0000000000000000) 1893#define M_DESAVERFields64 UNS64Const(0x0000000000000000)
1894 1894
1895 1895
1896/* 1896/*
@@ -1906,38 +1906,38 @@
1906 ************************************************************************* 1906 *************************************************************************
1907 */ 1907 */
1908 1908
1909#define fp0 $f0 1909#define fp0 $f0
1910#define fp1 $f1 1910#define fp1 $f1
1911#define fp2 $f2 1911#define fp2 $f2
1912#define fp3 $f3 1912#define fp3 $f3
1913#define fp4 $f4 1913#define fp4 $f4
1914#define fp5 $f5 1914#define fp5 $f5
1915#define fp6 $f6 1915#define fp6 $f6
1916#define fp7 $f7 1916#define fp7 $f7
1917#define fp8 $f8 1917#define fp8 $f8
1918#define fp9 $f9 1918#define fp9 $f9
1919#define fp10 $f10 1919#define fp10 $f10
1920#define fp11 $f11 1920#define fp11 $f11
1921#define fp12 $f12 1921#define fp12 $f12
1922#define fp13 $f13 1922#define fp13 $f13
1923#define fp14 $f14 1923#define fp14 $f14
1924#define fp15 $f15 1924#define fp15 $f15
1925#define fp16 $f16 1925#define fp16 $f16
1926#define fp17 $f17 1926#define fp17 $f17
1927#define fp18 $f18 1927#define fp18 $f18
1928#define fp19 $f19 1928#define fp19 $f19
1929#define fp20 $f20 1929#define fp20 $f20
1930#define fp21 $f21 1930#define fp21 $f21
1931#define fp22 $f22 1931#define fp22 $f22
1932#define fp23 $f23 1932#define fp23 $f23
1933#define fp24 $f24 1933#define fp24 $f24
1934#define fp25 $f25 1934#define fp25 $f25
1935#define fp26 $f26 1935#define fp26 $f26
1936#define fp27 $f27 1936#define fp27 $f27
1937#define fp28 $f28 1937#define fp28 $f28
1938#define fp29 $f29 1938#define fp29 $f29
1939#define fp30 $f30 1939#define fp30 $f30
1940#define fp31 $f31 1940#define fp31 $f31
1941 1941
1942/* 1942/*
1943 * The following definitions are used to convert an FPR name 1943 * The following definitions are used to convert an FPR name
@@ -1945,39 +1945,39 @@
1945 * This is used in macro substitution in the AVPs. 1945 * This is used in macro substitution in the AVPs.
1946 */ 1946 */
1947 1947
1948#define fp1_even $f0 1948#define fp1_even $f0
1949#define fp3_even $f2 1949#define fp3_even $f2
1950#define fp5_even $f4 1950#define fp5_even $f4
1951#define fp7_even $f6 1951#define fp7_even $f6
1952#define fp9_even $f8 1952#define fp9_even $f8
1953#define fp11_even $f10 1953#define fp11_even $f10
1954#define fp13_even $f12 1954#define fp13_even $f12
1955#define fp15_even $f14 1955#define fp15_even $f14
1956#define fp17_even $f16 1956#define fp17_even $f16
1957#define fp19_even $f18 1957#define fp19_even $f18
1958#define fp21_even $f20 1958#define fp21_even $f20
1959#define fp23_even $f22 1959#define fp23_even $f22
1960#define fp25_even $f24 1960#define fp25_even $f24
1961#define fp27_even $f26 1961#define fp27_even $f26
1962#define fp29_even $f28 1962#define fp29_even $f28
1963#define fp31_even $f30 1963#define fp31_even $f30
1964 1964
1965#define fp0_odd $f1 1965#define fp0_odd $f1
1966#define fp2_odd $f3 1966#define fp2_odd $f3
1967#define fp4_odd $f5 1967#define fp4_odd $f5
1968#define fp6_odd $f7 1968#define fp6_odd $f7
1969#define fp8_odd $f9 1969#define fp8_odd $f9
1970#define fp10_odd $f11 1970#define fp10_odd $f11
1971#define fp12_odd $f13 1971#define fp12_odd $f13
1972#define fp14_odd $f15 1972#define fp14_odd $f15
1973#define fp16_odd $f17 1973#define fp16_odd $f17
1974#define fp18_odd $f19 1974#define fp18_odd $f19
1975#define fp20_odd $f21 1975#define fp20_odd $f21
1976#define fp22_odd $f23 1976#define fp22_odd $f23
1977#define fp24_odd $f25 1977#define fp24_odd $f25
1978#define fp26_odd $f27 1978#define fp26_odd $f27
1979#define fp28_odd $f29 1979#define fp28_odd $f29
1980#define fp30_odd $f31 1980#define fp30_odd $f31
1981 1981
1982 1982
1983/* 1983/*
@@ -1989,38 +1989,38 @@
1989 * to the assembler register name ($n). 1989 * to the assembler register name ($n).
1990 */ 1990 */
1991 1991
1992#define R_fp0 0 1992#define R_fp0 0
1993#define R_fp1 1 1993#define R_fp1 1
1994#define R_fp2 2 1994#define R_fp2 2
1995#define R_fp3 3 1995#define R_fp3 3
1996#define R_fp4 4 1996#define R_fp4 4
1997#define R_fp5 5 1997#define R_fp5 5
1998#define R_fp6 6 1998#define R_fp6 6
1999#define R_fp7 7 1999#define R_fp7 7
2000#define R_fp8 8 2000#define R_fp8 8
2001#define R_fp9 9 2001#define R_fp9 9
2002#define R_fp10 10 2002#define R_fp10 10
2003#define R_fp11 11 2003#define R_fp11 11
2004#define R_fp12 12 2004#define R_fp12 12
2005#define R_fp13 13 2005#define R_fp13 13
2006#define R_fp14 14 2006#define R_fp14 14
2007#define R_fp15 15 2007#define R_fp15 15
2008#define R_fp16 16 2008#define R_fp16 16
2009#define R_fp17 17 2009#define R_fp17 17
2010#define R_fp18 18 2010#define R_fp18 18
2011#define R_fp19 19 2011#define R_fp19 19
2012#define R_fp20 20 2012#define R_fp20 20
2013#define R_fp21 21 2013#define R_fp21 21
2014#define R_fp22 22 2014#define R_fp22 22
2015#define R_fp23 23 2015#define R_fp23 23
2016#define R_fp24 24 2016#define R_fp24 24
2017#define R_fp25 25 2017#define R_fp25 25
2018#define R_fp26 26 2018#define R_fp26 26
2019#define R_fp27 27 2019#define R_fp27 27
2020#define R_fp28 28 2020#define R_fp28 28
2021#define R_fp29 29 2021#define R_fp29 29
2022#define R_fp30 30 2022#define R_fp30 30
2023#define R_fp31 31 2023#define R_fp31 31
2024 2024
2025 2025
2026/* 2026/*
@@ -2029,11 +2029,11 @@
2029 ************************************************************************* 2029 *************************************************************************
2030 */ 2030 */
2031 2031
2032#define fc0 $0 2032#define fc0 $0
2033#define fc25 $25 2033#define fc25 $25
2034#define fc26 $26 2034#define fc26 $26
2035#define fc28 $28 2035#define fc28 $28
2036#define fc31 $31 2036#define fc31 $31
2037 2037
2038 2038
2039/* 2039/*
@@ -2045,11 +2045,11 @@
2045 * to the assembler register name ($n). 2045 * to the assembler register name ($n).
2046 */ 2046 */
2047 2047
2048#define R_fc0 0 2048#define R_fc0 0
2049#define R_fc25 25 2049#define R_fc25 25
2050#define R_fc26 26 2050#define R_fc26 26
2051#define R_fc28 28 2051#define R_fc28 28
2052#define R_fc31 31 2052#define R_fc31 31
2053 2053
2054 2054
2055/* 2055/*
@@ -2058,14 +2058,14 @@
2058 ************************************************************************* 2058 *************************************************************************
2059 */ 2059 */
2060 2060
2061#define cc0 $fcc0 2061#define cc0 $fcc0
2062#define cc1 $fcc1 2062#define cc1 $fcc1
2063#define cc2 $fcc2 2063#define cc2 $fcc2
2064#define cc3 $fcc3 2064#define cc3 $fcc3
2065#define cc4 $fcc4 2065#define cc4 $fcc4
2066#define cc5 $fcc5 2066#define cc5 $fcc5
2067#define cc6 $fcc6 2067#define cc6 $fcc6
2068#define cc7 $fcc7 2068#define cc7 $fcc7
2069 2069
2070 2070
2071/* 2071/*
@@ -2077,21 +2077,21 @@
2077 * to the assembler register name ($n). 2077 * to the assembler register name ($n).
2078 */ 2078 */
2079 2079
2080#define R_cc0 0 2080#define R_cc0 0
2081#define R_cc1 1 2081#define R_cc1 1
2082#define R_cc2 2 2082#define R_cc2 2
2083#define R_cc3 3 2083#define R_cc3 3
2084#define R_cc4 4 2084#define R_cc4 4
2085#define R_cc5 5 2085#define R_cc5 5
2086#define R_cc6 6 2086#define R_cc6 6
2087#define R_cc7 7 2087#define R_cc7 7
2088 2088
2089 2089
2090/* 2090/*
2091 ************************************************************************ 2091 ************************************************************************
2092 * I M P L E M E N T A T I O N R E G I S T E R * 2092 * I M P L E M E N T A T I O N R E G I S T E R *
2093 ************************************************************************ 2093 ************************************************************************
2094 * 2094 *
2095 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 2095 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
2096 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 2096 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
2097 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 2097 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
@@ -2100,33 +2100,33 @@
2100 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 2100 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
2101 */ 2101 */
2102 2102
2103#define C1_FIR $0 2103#define C1_FIR $0
2104#define R_C1_FIR 0 2104#define R_C1_FIR 0
2105 2105
2106#define S_FIRConfigS 16 2106#define S_FIRConfigS 16
2107#define M_FIRConfigS (0x1 << S_FIRConfigS) 2107#define M_FIRConfigS (0x1 << S_FIRConfigS)
2108#define S_FIRConfigD 17 2108#define S_FIRConfigD 17
2109#define M_FIRConfigD (0x1 << S_FIRConfigD) 2109#define M_FIRConfigD (0x1 << S_FIRConfigD)
2110#define S_FIRConfigPS 18 2110#define S_FIRConfigPS 18
2111#define M_FIRConfigPS (0x1 << S_FIRConfigPS) 2111#define M_FIRConfigPS (0x1 << S_FIRConfigPS)
2112#define S_FIRConfig3D 19 2112#define S_FIRConfig3D 19
2113#define M_FIRConfig3D (0x1 << S_FIRConfig3D) 2113#define M_FIRConfig3D (0x1 << S_FIRConfig3D)
2114#define M_FIRConfigAll (M_FIRConfigS|M_FIRConfigD|M_FIRConfigPS|M_FIRConfig3D) 2114#define M_FIRConfigAll (M_FIRConfigS|M_FIRConfigD|M_FIRConfigPS|M_FIRConfig3D)
2115 2115
2116#define S_FIRImp 8 2116#define S_FIRImp 8
2117#define M_FIRImp (0xff << S_FIRImp) 2117#define M_FIRImp (0xff << S_FIRImp)
2118 2118
2119#define S_FIRRev 0 2119#define S_FIRRev 0
2120#define M_FIRRev (0xff << S_FIRRev) 2120#define M_FIRRev (0xff << S_FIRRev)
2121 2121
2122#define M_FIR0Fields 0xfff00000 2122#define M_FIR0Fields 0xfff00000
2123#define M_FIRRFields 0x000fffff 2123#define M_FIRRFields 0x000fffff
2124 2124
2125/* 2125/*
2126 ************************************************************************ 2126 ************************************************************************
2127 * C O N D I T I O N C O D E S R E G I S T E R * 2127 * C O N D I T I O N C O D E S R E G I S T E R *
2128 ************************************************************************ 2128 ************************************************************************
2129 * 2129 *
2130 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 2130 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
2131 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 2131 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
2132 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 2132 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
@@ -2134,37 +2134,37 @@
2134 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 2134 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
2135 */ 2135 */
2136 2136
2137#define C1_FCCR $25 2137#define C1_FCCR $25
2138#define R_C1_FCCR 25 2138#define R_C1_FCCR 25
2139 2139
2140#define S_FCCRCC 0 2140#define S_FCCRCC 0
2141#define M_FCCRCC (0xff << S_FCCRCC) 2141#define M_FCCRCC (0xff << S_FCCRCC)
2142#define S_FCCRCC7 7 2142#define S_FCCRCC7 7
2143#define M_FCCRCC7 (0x1 << S_FCCRCC7) 2143#define M_FCCRCC7 (0x1 << S_FCCRCC7)
2144#define S_FCCRCC6 6 2144#define S_FCCRCC6 6
2145#define M_FCCRCC6 (0x1 << S_FCCRCC6) 2145#define M_FCCRCC6 (0x1 << S_FCCRCC6)
2146#define S_FCCRCC5 5 2146#define S_FCCRCC5 5
2147#define M_FCCRCC5 (0x1 << S_FCCRCC5) 2147#define M_FCCRCC5 (0x1 << S_FCCRCC5)
2148#define S_FCCRCC4 4 2148#define S_FCCRCC4 4
2149#define M_FCCRCC4 (0x1 << S_FCCRCC4) 2149#define M_FCCRCC4 (0x1 << S_FCCRCC4)
2150#define S_FCCRCC3 3 2150#define S_FCCRCC3 3
2151#define M_FCCRCC3 (0x1 << S_FCCRCC3) 2151#define M_FCCRCC3 (0x1 << S_FCCRCC3)
2152#define S_FCCRCC2 2 2152#define S_FCCRCC2 2
2153#define M_FCCRCC2 (0x1 << S_FCCRCC2) 2153#define M_FCCRCC2 (0x1 << S_FCCRCC2)
2154#define S_FCCRCC1 1 2154#define S_FCCRCC1 1
2155#define M_FCCRCC1 (0x1 << S_FCCRCC1) 2155#define M_FCCRCC1 (0x1 << S_FCCRCC1)
2156#define S_FCCRCC0 0 2156#define S_FCCRCC0 0
2157#define M_FCCRCC0 (0x1 << S_FCCRCC0) 2157#define M_FCCRCC0 (0x1 << S_FCCRCC0)
2158 2158
2159#define M_FCCR0Fields 0xffffff00 2159#define M_FCCR0Fields 0xffffff00
2160#define M_FCCRRFields 0x000000ff 2160#define M_FCCRRFields 0x000000ff
2161 2161
2162 2162
2163/* 2163/*
2164 ************************************************************************ 2164 ************************************************************************
2165 * E X C E P T I O N S R E G I S T E R * 2165 * E X C E P T I O N S R E G I S T E R *
2166 ************************************************************************ 2166 ************************************************************************
2167 * 2167 *
2168 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 2168 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
2169 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 2169 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
2170 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 2170 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
@@ -2173,46 +2173,46 @@
2173 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 2173 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
2174 */ 2174 */
2175 2175
2176#define C1_FEXR $26 2176#define C1_FEXR $26
2177#define R_C1_FEXR 26 2177#define R_C1_FEXR 26
2178 2178
2179#define S_FEXRExc 12 2179#define S_FEXRExc 12
2180#define M_FEXRExc (0x3f << S_FEXRExc) 2180#define M_FEXRExc (0x3f << S_FEXRExc)
2181#define S_FEXRExcE 17 2181#define S_FEXRExcE 17
2182#define M_FEXRExcE (0x1 << S_FEXRExcE) 2182#define M_FEXRExcE (0x1 << S_FEXRExcE)
2183#define S_FEXRExcV 16 2183#define S_FEXRExcV 16
2184#define M_FEXRExcV (0x1 << S_FEXRExcV) 2184#define M_FEXRExcV (0x1 << S_FEXRExcV)
2185#define S_FEXRExcZ 15 2185#define S_FEXRExcZ 15
2186#define M_FEXRExcZ (0x1 << S_FEXRExcZ) 2186#define M_FEXRExcZ (0x1 << S_FEXRExcZ)
2187#define S_FEXRExcO 14 2187#define S_FEXRExcO 14
2188#define M_FEXRExcO (0x1 << S_FEXRExcO) 2188#define M_FEXRExcO (0x1 << S_FEXRExcO)
2189#define S_FEXRExcU 13 2189#define S_FEXRExcU 13
2190#define M_FEXRExcU (0x1 << S_FEXRExcU) 2190#define M_FEXRExcU (0x1 << S_FEXRExcU)
2191#define S_FEXRExcI 12 2191#define S_FEXRExcI 12
2192#define M_FEXRExcI (0x1 << S_FEXRExcI) 2192#define M_FEXRExcI (0x1 << S_FEXRExcI)
2193 2193
2194#define S_FEXRFlg 2 2194#define S_FEXRFlg 2
2195#define M_FEXRFlg (0x1f << S_FEXRFlg) 2195#define M_FEXRFlg (0x1f << S_FEXRFlg)
2196#define S_FEXRFlgV 6 2196#define S_FEXRFlgV 6
2197#define M_FEXRFlgV (0x1 << S_FEXRFlgV) 2197#define M_FEXRFlgV (0x1 << S_FEXRFlgV)
2198#define S_FEXRFlgZ 5 2198#define S_FEXRFlgZ 5
2199#define M_FEXRFlgZ (0x1 << S_FEXRFlgZ) 2199#define M_FEXRFlgZ (0x1 << S_FEXRFlgZ)
2200#define S_FEXRFlgO 4 2200#define S_FEXRFlgO 4
2201#define M_FEXRFlgO (0x1 << S_FEXRFlgO) 2201#define M_FEXRFlgO (0x1 << S_FEXRFlgO)
2202#define S_FEXRFlgU 3 2202#define S_FEXRFlgU 3
2203#define M_FEXRFlgU (0x1 << S_FEXRFlgU) 2203#define M_FEXRFlgU (0x1 << S_FEXRFlgU)
2204#define S_FEXRFlgI 2 2204#define S_FEXRFlgI 2
2205#define M_FEXRFlgI (0x1 << S_FEXRFlgI) 2205#define M_FEXRFlgI (0x1 << S_FEXRFlgI)
2206 2206
2207#define M_FEXR0Fields 0xfffc0f83 2207#define M_FEXR0Fields 0xfffc0f83
2208#define M_FEXRRFields 0x00000000 2208#define M_FEXRRFields 0x00000000
2209 2209
2210 2210
2211/* 2211/*
2212 ************************************************************************ 2212 ************************************************************************
2213 * E N A B L E S R E G I S T E R * 2213 * E N A B L E S R E G I S T E R *
2214 ************************************************************************ 2214 ************************************************************************
2215 * 2215 *
2216 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 2216 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
2217 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 2217 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
2218 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 2218 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
@@ -2221,37 +2221,37 @@
2221 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 2221 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
2222 */ 2222 */
2223 2223
2224#define C1_FENR $28 2224#define C1_FENR $28
2225#define R_C1_FENR 28 2225#define R_C1_FENR 28
2226 2226
2227#define S_FENREna 7 2227#define S_FENREna 7
2228#define M_FENREna (0x1f << S_FENREna) 2228#define M_FENREna (0x1f << S_FENREna)
2229#define S_FENREnaV 11 2229#define S_FENREnaV 11
2230#define M_FENREnaV (0x1 << S_FENREnaV) 2230#define M_FENREnaV (0x1 << S_FENREnaV)
2231#define S_FENREnaZ 10 2231#define S_FENREnaZ 10
2232#define M_FENREnaZ (0x1 << S_FENREnaZ) 2232#define M_FENREnaZ (0x1 << S_FENREnaZ)
2233#define S_FENREnaO 9 2233#define S_FENREnaO 9
2234#define M_FENREnaO (0x1 << S_FENREnaO) 2234#define M_FENREnaO (0x1 << S_FENREnaO)
2235#define S_FENREnaU 8 2235#define S_FENREnaU 8
2236#define M_FENREnaU (0x1 << S_FENREnaU) 2236#define M_FENREnaU (0x1 << S_FENREnaU)
2237#define S_FENREnaI 7 2237#define S_FENREnaI 7
2238#define M_FENREnaI (0x1 << S_FENREnaI) 2238#define M_FENREnaI (0x1 << S_FENREnaI)
2239 2239
2240#define S_FENRFS 2 2240#define S_FENRFS 2
2241#define M_FENRFS (0x1 << S_FENRFS) 2241#define M_FENRFS (0x1 << S_FENRFS)
2242 2242
2243#define S_FENRRM 0 2243#define S_FENRRM 0
2244#define M_FENRRM (0x3 << S_FENRRM) 2244#define M_FENRRM (0x3 << S_FENRRM)
2245 2245
2246#define M_FENR0Fields 0xfffff078 2246#define M_FENR0Fields 0xfffff078
2247#define M_FENRRFields 0x00000000 2247#define M_FENRRFields 0x00000000
2248 2248
2249 2249
2250/* 2250/*
2251 ************************************************************************ 2251 ************************************************************************
2252 * C O N T R O L / S T A T U S R E G I S T E R * 2252 * C O N T R O L / S T A T U S R E G I S T E R *
2253 ************************************************************************ 2253 ************************************************************************
2254 * 2254 *
2255 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 2255 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
2256 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 2256 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
2257 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 2257 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
@@ -2260,91 +2260,91 @@
2260 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 2260 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
2261 */ 2261 */
2262 2262
2263#define C1_FCSR $31 2263#define C1_FCSR $31
2264#define R_C1_FCSR 31 2264#define R_C1_FCSR 31
2265 2265
2266#define S_FCSRFCC7_1 25 /* Floating point condition codes 7..1 (R/W) */ 2266#define S_FCSRFCC7_1 25 /* Floating point condition codes 7..1 (R/W) */
2267#define M_FCSRFCC7_1 (0x7f << S_FCSRFCC7_1) 2267#define M_FCSRFCC7_1 (0x7f << S_FCSRFCC7_1)
2268#define S_FCSRCC7 31 2268#define S_FCSRCC7 31
2269#define M_FCSRCC7 (0x1 << S_FCSRCC7) 2269#define M_FCSRCC7 (0x1 << S_FCSRCC7)
2270#define S_FCSRCC6 30 2270#define S_FCSRCC6 30
2271#define M_FCSRCC6 (0x1 << S_FCSRCC6) 2271#define M_FCSRCC6 (0x1 << S_FCSRCC6)
2272#define S_FCSRCC5 29 2272#define S_FCSRCC5 29
2273#define M_FCSRCC5 (0x1 << S_FCSRCC5) 2273#define M_FCSRCC5 (0x1 << S_FCSRCC5)
2274#define S_FCSRCC4 28 2274#define S_FCSRCC4 28
2275#define M_FCSRCC4 (0x1 << S_FCSRCC4) 2275#define M_FCSRCC4 (0x1 << S_FCSRCC4)
2276#define S_FCSRCC3 27 2276#define S_FCSRCC3 27
2277#define M_FCSRCC3 (0x1 << S_FCSRCC3) 2277#define M_FCSRCC3 (0x1 << S_FCSRCC3)
2278#define S_FCSRCC2 26 2278#define S_FCSRCC2 26
2279#define M_FCSRCC2 (0x1 << S_FCSRCC2) 2279#define M_FCSRCC2 (0x1 << S_FCSRCC2)
2280#define S_FCSRCC1 25 2280#define S_FCSRCC1 25
2281#define M_FCSRCC1 (0x1 << S_FCSRCC1) 2281#define M_FCSRCC1 (0x1 << S_FCSRCC1)
2282 2282
2283#define S_FCSRFS 24 /* Flush denorms to zero (R/W) */ 2283#define S_FCSRFS 24 /* Flush denorms to zero (R/W) */
2284#define M_FCSRFS (0x1 << S_FCSRFS) 2284#define M_FCSRFS (0x1 << S_FCSRFS)
2285 2285
2286#define S_FCSRCC0 23 /* Floating point condition code 0 (R/W) */ 2286#define S_FCSRCC0 23 /* Floating point condition code 0 (R/W) */
2287#define M_FCSRCC0 (0x1 << S_FCSRCC0) 2287#define M_FCSRCC0 (0x1 << S_FCSRCC0)
2288#define S_FCSRCC S_FCSRCC0 2288#define S_FCSRCC S_FCSRCC0
2289#define M_FCSRCC M_FCSRCC0 2289#define M_FCSRCC M_FCSRCC0
2290 2290
2291#define S_FCSRImpl 21 /* Implementation-specific control bits (R/W) */ 2291#define S_FCSRImpl 21 /* Implementation-specific control bits (R/W) */
2292#define M_FCSRImpl (0x3 << S_FCSRImpl) 2292#define M_FCSRImpl (0x3 << S_FCSRImpl)
2293 2293
2294#define S_FCSRExc 12 /* Exception cause (R/W) */ 2294#define S_FCSRExc 12 /* Exception cause (R/W) */
2295#define M_FCSRExc (0x3f << S_FCSRExc) 2295#define M_FCSRExc (0x3f << S_FCSRExc)
2296#define S_FCSRExcE 17 2296#define S_FCSRExcE 17
2297#define M_FCSRExcE (0x1 << S_FCSRExcE) 2297#define M_FCSRExcE (0x1 << S_FCSRExcE)
2298#define S_FCSRExcV 16 2298#define S_FCSRExcV 16
2299#define M_FCSRExcV (0x1 << S_FCSRExcV) 2299#define M_FCSRExcV (0x1 << S_FCSRExcV)
2300#define S_FCSRExcZ 15 2300#define S_FCSRExcZ 15
2301#define M_FCSRExcZ (0x1 << S_FCSRExcZ) 2301#define M_FCSRExcZ (0x1 << S_FCSRExcZ)
2302#define S_FCSRExcO 14 2302#define S_FCSRExcO 14
2303#define M_FCSRExcO (0x1 << S_FCSRExcO) 2303#define M_FCSRExcO (0x1 << S_FCSRExcO)
2304#define S_FCSRExcU 13 2304#define S_FCSRExcU 13
2305#define M_FCSRExcU (0x1 << S_FCSRExcU) 2305#define M_FCSRExcU (0x1 << S_FCSRExcU)
2306#define S_FCSRExcI 12 2306#define S_FCSRExcI 12
2307#define M_FCSRExcI (0x1 << S_FCSRExcI) 2307#define M_FCSRExcI (0x1 << S_FCSRExcI)
2308 2308
2309#define S_FCSREna 7 /* Exception enable (R/W) */ 2309#define S_FCSREna 7 /* Exception enable (R/W) */
2310#define M_FCSREna (0x1f << S_FCSREna) 2310#define M_FCSREna (0x1f << S_FCSREna)
2311#define S_FCSREnaV 11 2311#define S_FCSREnaV 11
2312#define M_FCSREnaV (0x1 << S_FCSREnaV) 2312#define M_FCSREnaV (0x1 << S_FCSREnaV)
2313#define S_FCSREnaZ 10 2313#define S_FCSREnaZ 10
2314#define M_FCSREnaZ (0x1 << S_FCSREnaZ) 2314#define M_FCSREnaZ (0x1 << S_FCSREnaZ)
2315#define S_FCSREnaO 9 2315#define S_FCSREnaO 9
2316#define M_FCSREnaO (0x1 << S_FCSREnaO) 2316#define M_FCSREnaO (0x1 << S_FCSREnaO)
2317#define S_FCSREnaU 8 2317#define S_FCSREnaU 8
2318#define M_FCSREnaU (0x1 << S_FCSREnaU) 2318#define M_FCSREnaU (0x1 << S_FCSREnaU)
2319#define S_FCSREnaI 7 2319#define S_FCSREnaI 7
2320#define M_FCSREnaI (0x1 << S_FCSREnaI) 2320#define M_FCSREnaI (0x1 << S_FCSREnaI)
2321 2321
2322#define S_FCSRFlg 2 /* Exception flags (R/W) */ 2322#define S_FCSRFlg 2 /* Exception flags (R/W) */
2323#define M_FCSRFlg (0x1f << S_FCSRFlg) 2323#define M_FCSRFlg (0x1f << S_FCSRFlg)
2324#define S_FCSRFlgV 6 2324#define S_FCSRFlgV 6
2325#define M_FCSRFlgV (0x1 << S_FCSRFlgV) 2325#define M_FCSRFlgV (0x1 << S_FCSRFlgV)
2326#define S_FCSRFlgZ 5 2326#define S_FCSRFlgZ 5
2327#define M_FCSRFlgZ (0x1 << S_FCSRFlgZ) 2327#define M_FCSRFlgZ (0x1 << S_FCSRFlgZ)
2328#define S_FCSRFlgO 4 2328#define S_FCSRFlgO 4
2329#define M_FCSRFlgO (0x1 << S_FCSRFlgO) 2329#define M_FCSRFlgO (0x1 << S_FCSRFlgO)
2330#define S_FCSRFlgU 3 2330#define S_FCSRFlgU 3
2331#define M_FCSRFlgU (0x1 << S_FCSRFlgU) 2331#define M_FCSRFlgU (0x1 << S_FCSRFlgU)
2332#define S_FCSRFlgI 2 2332#define S_FCSRFlgI 2
2333#define M_FCSRFlgI (0x1 << S_FCSRFlgI) 2333#define M_FCSRFlgI (0x1 << S_FCSRFlgI)
2334 2334
2335#define S_FCSRRM 0 /* Rounding mode (R/W) */ 2335#define S_FCSRRM 0 /* Rounding mode (R/W) */
2336#define M_FCSRRM (0x3 << S_FCSRRM) 2336#define M_FCSRRM (0x3 << S_FCSRRM)
2337 2337
2338#define M_FCSR0Fields 0x001c0000 2338#define M_FCSR0Fields 0x001c0000
2339#define M_FCSRRFields 0x00000000 2339#define M_FCSRRFields 0x00000000
2340 2340
2341/* 2341/*
2342 * Values in the rounding mode field (of both FCSR and FCCR) 2342 * Values in the rounding mode field (of both FCSR and FCCR)
2343 */ 2343 */
2344#define K_FCSRRM_RN 0 2344#define K_FCSRRM_RN 0
2345#define K_FCSRRM_RZ 1 2345#define K_FCSRRM_RZ 1
2346#define K_FCSRRM_RP 2 2346#define K_FCSRRM_RP 2
2347#define K_FCSRRM_RM 3 2347#define K_FCSRRM_RM 3
2348 2348
2349 2349
2350/* ********************************************************************* */ 2350/* ********************************************************************* */
diff --git a/firmware/export/mips.h b/firmware/export/mips.h
index 5fd3071e4e..aef7bc9dd2 100644
--- a/firmware/export/mips.h
+++ b/firmware/export/mips.h
@@ -37,161 +37,161 @@
37/* Interface macro & data definition */ 37/* Interface macro & data definition */
38 38
39#ifndef MSK 39#ifndef MSK
40#define MSK(n) ((1 << (n)) - 1) 40#define MSK(n) ((1 << (n)) - 1)
41#endif 41#endif
42 42
43/* CPU registers */ 43/* CPU registers */
44#define SYS_CPUREG_ZERO 0 44#define SYS_CPUREG_ZERO 0
45#define SYS_CPUREG_AT 1 45#define SYS_CPUREG_AT 1
46#define SYS_CPUREG_V0 2 46#define SYS_CPUREG_V0 2
47#define SYS_CPUREG_V1 3 47#define SYS_CPUREG_V1 3
48#define SYS_CPUREG_A0 4 48#define SYS_CPUREG_A0 4
49#define SYS_CPUREG_A1 5 49#define SYS_CPUREG_A1 5
50#define SYS_CPUREG_A2 6 50#define SYS_CPUREG_A2 6
51#define SYS_CPUREG_A3 7 51#define SYS_CPUREG_A3 7
52#define SYS_CPUREG_T0 8 52#define SYS_CPUREG_T0 8
53#define SYS_CPUREG_T1 9 53#define SYS_CPUREG_T1 9
54#define SYS_CPUREG_T2 10 54#define SYS_CPUREG_T2 10
55#define SYS_CPUREG_T3 11 55#define SYS_CPUREG_T3 11
56#define SYS_CPUREG_T4 12 56#define SYS_CPUREG_T4 12
57#define SYS_CPUREG_T5 13 57#define SYS_CPUREG_T5 13
58#define SYS_CPUREG_T6 14 58#define SYS_CPUREG_T6 14
59#define SYS_CPUREG_T7 15 59#define SYS_CPUREG_T7 15
60#define SYS_CPUREG_S0 16 60#define SYS_CPUREG_S0 16
61#define SYS_CPUREG_S1 17 61#define SYS_CPUREG_S1 17
62#define SYS_CPUREG_S2 18 62#define SYS_CPUREG_S2 18
63#define SYS_CPUREG_S3 19 63#define SYS_CPUREG_S3 19
64#define SYS_CPUREG_S4 20 64#define SYS_CPUREG_S4 20
65#define SYS_CPUREG_S5 21 65#define SYS_CPUREG_S5 21
66#define SYS_CPUREG_S6 22 66#define SYS_CPUREG_S6 22
67#define SYS_CPUREG_S7 23 67#define SYS_CPUREG_S7 23
68#define SYS_CPUREG_T8 24 68#define SYS_CPUREG_T8 24
69#define SYS_CPUREG_T9 25 69#define SYS_CPUREG_T9 25
70#define SYS_CPUREG_K0 26 70#define SYS_CPUREG_K0 26
71#define SYS_CPUREG_K1 27 71#define SYS_CPUREG_K1 27
72#define SYS_CPUREG_GP 28 72#define SYS_CPUREG_GP 28
73#define SYS_CPUREG_SP 29 73#define SYS_CPUREG_SP 29
74#define SYS_CPUREG_S8 30 74#define SYS_CPUREG_S8 30
75#define SYS_CPUREG_FP SYS_CPUREG_S8 75#define SYS_CPUREG_FP SYS_CPUREG_S8
76#define SYS_CPUREG_RA 31 76#define SYS_CPUREG_RA 31
77 77
78 78
79/* CPU register fp ($30) has an alias s8 */ 79/* CPU register fp ($30) has an alias s8 */
80#define s8 fp 80#define s8 fp
81 81
82 82
83/* Aliases for System Control Coprocessor (CP0) registers */ 83/* Aliases for System Control Coprocessor (CP0) registers */
84#define C0_INDEX C0_Index 84#define C0_INDEX C0_Index
85#define C0_RANDOM C0_Random 85#define C0_RANDOM C0_Random
86#define C0_ENTRYLO0 C0_EntryLo0 86#define C0_ENTRYLO0 C0_EntryLo0
87#define C0_ENTRYLO1 C0_EntryLo1 87#define C0_ENTRYLO1 C0_EntryLo1
88#define C0_CONTEXT C0_Context 88#define C0_CONTEXT C0_Context
89#define C0_PAGEMASK C0_PageMask 89#define C0_PAGEMASK C0_PageMask
90#define C0_WIRED C0_Wired 90#define C0_WIRED C0_Wired
91#define C0_BADVADDR C0_BadVAddr 91#define C0_BADVADDR C0_BadVAddr
92#define C0_COUNT C0_Count 92#define C0_COUNT C0_Count
93#define C0_ENTRYHI C0_EntryHi 93#define C0_ENTRYHI C0_EntryHi
94#define C0_COMPARE C0_Compare 94#define C0_COMPARE C0_Compare
95#define C0_STATUS C0_Status 95#define C0_STATUS C0_Status
96#define C0_CAUSE C0_Cause 96#define C0_CAUSE C0_Cause
97 97
98#ifdef C0_PRID /* ArchDefs has an obsolete def. of C0_PRID */ 98#ifdef C0_PRID /* ArchDefs has an obsolete def. of C0_PRID */
99#undef C0_PRID 99#undef C0_PRID
100#endif 100#endif
101#define C0_PRID C0_PRId 101#define C0_PRID C0_PRId
102 102
103#define C0_CONFIG C0_Config 103#define C0_CONFIG C0_Config
104#define C0_CONFIG1 C0_Config1 104#define C0_CONFIG1 C0_Config1
105#define C0_LLADDR C0_LLAddr 105#define C0_LLADDR C0_LLAddr
106#define C0_WATCHLO C0_WatchLo 106#define C0_WATCHLO C0_WatchLo
107#define C0_WATCHHI C0_WatchHi 107#define C0_WATCHHI C0_WatchHi
108#define C0_DEBUG C0_Debug 108#define C0_DEBUG C0_Debug
109#define C0_PERFCNT C0_PerfCnt 109#define C0_PERFCNT C0_PerfCnt
110#define C0_ERRCTL C0_ErrCtl 110#define C0_ERRCTL C0_ErrCtl
111#define C0_CACHEERR C0_CacheErr 111#define C0_CACHEERR C0_CacheErr
112#define C0_TAGLO C0_TagLo 112#define C0_TAGLO C0_TagLo
113#define C0_DATALO C0_DataLo 113#define C0_DATALO C0_DataLo
114#define C0_TAGHI C0_TagHi 114#define C0_TAGHI C0_TagHi
115#define C0_DATAHI C0_DataHi 115#define C0_DATAHI C0_DataHi
116#define C0_ERROREPC C0_ErrorEPC 116#define C0_ERROREPC C0_ErrorEPC
117#if 0 117#if 0
118#define C0_DESAVE C0_DESAVE 118#define C0_DESAVE C0_DESAVE
119#define C0_EPC C0_EPC 119#define C0_EPC C0_EPC
120#define C0_DEPC C0_DEPC 120#define C0_DEPC C0_DEPC
121#endif 121#endif
122 122
123/* System Control Coprocessor (CP0) registers select fields */ 123/* System Control Coprocessor (CP0) registers select fields */
124#define C0_INDEX_SEL 0 /* TLB Index */ 124#define C0_INDEX_SEL 0 /* TLB Index */
125#define C0_RANDOM_SEL 0 /* TLB Random */ 125#define C0_RANDOM_SEL 0 /* TLB Random */
126#define C0_TLBLO0_SEL 0 /* TLB EntryLo0 */ 126#define C0_TLBLO0_SEL 0 /* TLB EntryLo0 */
127#define C0_TLBLO1_SEL 0 /* TLB EntryLo1 */ 127#define C0_TLBLO1_SEL 0 /* TLB EntryLo1 */
128#define C0_CONTEXT_SEL 0 /* Context */ 128#define C0_CONTEXT_SEL 0 /* Context */
129#define C0_PAGEMASK_SEL 0 /* TLB PageMask */ 129#define C0_PAGEMASK_SEL 0 /* TLB PageMask */
130#define C0_WIRED_SEL 0 /* TLB Wired */ 130#define C0_WIRED_SEL 0 /* TLB Wired */
131#define C0_BADVADDR_SEL 0 /* Bad Virtual Address */ 131#define C0_BADVADDR_SEL 0 /* Bad Virtual Address */
132#define C0_COUNT_SEL 0 /* Count */ 132#define C0_COUNT_SEL 0 /* Count */
133#define C0_ENTRYHI_SEL 0 /* TLB EntryHi */ 133#define C0_ENTRYHI_SEL 0 /* TLB EntryHi */
134#define C0_COMPARE_SEL 0 /* Compare */ 134#define C0_COMPARE_SEL 0 /* Compare */
135#define C0_STATUS_SEL 0 /* Processor Status */ 135#define C0_STATUS_SEL 0 /* Processor Status */
136#define C0_CAUSE_SEL 0 /* Exception Cause */ 136#define C0_CAUSE_SEL 0 /* Exception Cause */
137#define C0_EPC_SEL 0 /* Exception PC */ 137#define C0_EPC_SEL 0 /* Exception PC */
138#define C0_PRID_SEL 0 /* Processor Revision Indentifier */ 138#define C0_PRID_SEL 0 /* Processor Revision Indentifier */
139#define C0_CONFIG_SEL 0 /* Config */ 139#define C0_CONFIG_SEL 0 /* Config */
140#define C0_CONFIG1_SEL 1 /* Config1 */ 140#define C0_CONFIG1_SEL 1 /* Config1 */
141#define C0_LLADDR_SEL 0 /* LLAddr */ 141#define C0_LLADDR_SEL 0 /* LLAddr */
142#define C0_WATCHLO_SEL 0 /* WatchpointLo */ 142#define C0_WATCHLO_SEL 0 /* WatchpointLo */
143#define C0_WATCHHI_SEL 0 /* WatchpointHi */ 143#define C0_WATCHHI_SEL 0 /* WatchpointHi */
144#define C0_DEBUG_SEL 0 /* EJTAG Debug Register */ 144#define C0_DEBUG_SEL 0 /* EJTAG Debug Register */
145#define C0_DEPC_SEL 0 /* Program counter at last EJTAG debug exception */ 145#define C0_DEPC_SEL 0 /* Program counter at last EJTAG debug exception */
146#define C0_PERFCNT_SEL 0 /* Performance counter interface */ 146#define C0_PERFCNT_SEL 0 /* Performance counter interface */
147#define C0_ERRCTL_SEL 0 /* ERRCTL */ 147#define C0_ERRCTL_SEL 0 /* ERRCTL */
148#define C0_CACHEERR_SEL 0 /* CacheErr */ 148#define C0_CACHEERR_SEL 0 /* CacheErr */
149#define C0_TAGLO_SEL 0 /* TagLo */ 149#define C0_TAGLO_SEL 0 /* TagLo */
150#define C0_DATALO_SEL 1 /* DataLo */ 150#define C0_DATALO_SEL 1 /* DataLo */
151#define C0_DTAGLO_SEL 2 /* DTagLo */ 151#define C0_DTAGLO_SEL 2 /* DTagLo */
152#define C0_TAGHI_SEL 0 /* TagHi */ 152#define C0_TAGHI_SEL 0 /* TagHi */
153#define C0_DATAHI_SEL 1 /* DataHi */ 153#define C0_DATAHI_SEL 1 /* DataHi */
154#define C0_DTAGHI_SEL 2 /* DTagHi */ 154#define C0_DTAGHI_SEL 2 /* DTagHi */
155#define C0_ERROREPC_SEL 0 /* ErrorEPC */ 155#define C0_ERROREPC_SEL 0 /* ErrorEPC */
156#define C0_DESAVE_SEL 0 /* EJTAG dbg exc. save register */ 156#define C0_DESAVE_SEL 0 /* EJTAG dbg exc. save register */
157 157
158 158
159/* C0_CONFIG register encoding */ 159/* C0_CONFIG register encoding */
160 160
161#define C0_CONFIG_M_SHF S_ConfigMore 161#define C0_CONFIG_M_SHF S_ConfigMore
162#define C0_CONFIG_M_MSK M_ConfigMore 162#define C0_CONFIG_M_MSK M_ConfigMore
163#define C0_CONFIG_M_BIT C0_CONFIG_M_MSK 163#define C0_CONFIG_M_BIT C0_CONFIG_M_MSK
164 164
165#define C0_CONFIG_BE_SHF S_ConfigBE 165#define C0_CONFIG_BE_SHF S_ConfigBE
166#define C0_CONFIG_BE_MSK M_ConfigBE 166#define C0_CONFIG_BE_MSK M_ConfigBE
167#define C0_CONFIG_BE_BIT C0_CONFIG_BE_MSK 167#define C0_CONFIG_BE_BIT C0_CONFIG_BE_MSK
168 168
169#define C0_CONFIG_AT_SHF S_ConfigAT 169#define C0_CONFIG_AT_SHF S_ConfigAT
170#define C0_CONFIG_AT_MSK M_ConfigAT 170#define C0_CONFIG_AT_MSK M_ConfigAT
171#define C0_CONFIG_AT_MIPS32 K_ConfigAT_MIPS32 171#define C0_CONFIG_AT_MIPS32 K_ConfigAT_MIPS32
172#define C0_CONFIG_AT_MIPS64_32ADDR K_ConfigAT_MIPS64S 172#define C0_CONFIG_AT_MIPS64_32ADDR K_ConfigAT_MIPS64S
173#define C0_CONFIG_AT_MIPS64 K_ConfigAT_MIPS64 173#define C0_CONFIG_AT_MIPS64 K_ConfigAT_MIPS64
174 174
175#define C0_CONFIG_AR_SHF S_ConfigAR 175#define C0_CONFIG_AR_SHF S_ConfigAR
176#define C0_CONFIG_AR_MSK M_ConfigAR 176#define C0_CONFIG_AR_MSK M_ConfigAR
177 177
178#define C0_CONFIG_MT_SHF S_ConfigMT 178#define C0_CONFIG_MT_SHF S_ConfigMT
179#define C0_CONFIG_MT_MSK M_ConfigMT 179#define C0_CONFIG_MT_MSK M_ConfigMT
180#define C0_CONFIG_MT_NONE K_ConfigMT_NoMMU 180#define C0_CONFIG_MT_NONE K_ConfigMT_NoMMU
181#define C0_CONFIG_MT_TLB K_ConfigMT_TLBMMU 181#define C0_CONFIG_MT_TLB K_ConfigMT_TLBMMU
182#define C0_CONFIG_MT_BAT K_ConfigMT_BATMMU 182#define C0_CONFIG_MT_BAT K_ConfigMT_BATMMU
183#define C0_CONFIG_MT_NON_STD K_ConfigMT_FMMMU 183#define C0_CONFIG_MT_NON_STD K_ConfigMT_FMMMU
184 184
185#define C0_CONFIG_K0_SHF S_ConfigK0 185#define C0_CONFIG_K0_SHF S_ConfigK0
186#define C0_CONFIG_K0_MSK M_ConfigK0 186#define C0_CONFIG_K0_MSK M_ConfigK0
187#define C0_CONFIG_K0_WTHRU_NOALLOC K_CacheAttrCWTnWA 187#define C0_CONFIG_K0_WTHRU_NOALLOC K_CacheAttrCWTnWA
188#define C0_CONFIG_K0_WTHRU_ALLOC K_CacheAttrCWTWA 188#define C0_CONFIG_K0_WTHRU_ALLOC K_CacheAttrCWTWA
189#define C0_CONFIG_K0_UNCACHED K_CacheAttrU 189#define C0_CONFIG_K0_UNCACHED K_CacheAttrU
190#define C0_CONFIG_K0_NONCOHERENT K_CacheAttrCN 190#define C0_CONFIG_K0_NONCOHERENT K_CacheAttrCN
191#define C0_CONFIG_K0_COHERENTXCL K_CacheAttrCCE 191#define C0_CONFIG_K0_COHERENTXCL K_CacheAttrCCE
192#define C0_CONFIG_K0_COHERENTXCLW K_CacheAttrCCS 192#define C0_CONFIG_K0_COHERENTXCLW K_CacheAttrCCS
193#define C0_CONFIG_K0_COHERENTUPD K_CacheAttrCCU 193#define C0_CONFIG_K0_COHERENTUPD K_CacheAttrCCU
194#define C0_CONFIG_K0_UNCACHED_ACCEL K_CacheAttrUA 194#define C0_CONFIG_K0_UNCACHED_ACCEL K_CacheAttrUA
195 195
196 196
197/* WC field. 197/* WC field.
@@ -203,379 +203,379 @@
203 * MIPS Architecture, and may cause unpredictable operation of 203 * MIPS Architecture, and may cause unpredictable operation of
204 * the processor. 204 * the processor.
205 */ 205 */
206#define C0_CONFIG_WC_SHF 19 206#define C0_CONFIG_WC_SHF 19
207#define C0_CONFIG_WC_MSK (MSK(1) << C0_CONFIG_WC_SHF) 207#define C0_CONFIG_WC_MSK (MSK(1) << C0_CONFIG_WC_SHF)
208#define C0_CONFIG_WC_BIT C0_CONFIG_WC_MSK 208#define C0_CONFIG_WC_BIT C0_CONFIG_WC_MSK
209 209
210 210
211/* C0_CONFIG1 register encoding */ 211/* C0_CONFIG1 register encoding */
212 212
213#define C0_CONFIG1_MMUSIZE_SHF S_Config1MMUSize 213#define C0_CONFIG1_MMUSIZE_SHF S_Config1MMUSize
214#define C0_CONFIG1_MMUSIZE_MSK M_Config1MMUSize 214#define C0_CONFIG1_MMUSIZE_MSK M_Config1MMUSize
215 215
216#define C0_CONFIG1_IS_SHF S_Config1IS 216#define C0_CONFIG1_IS_SHF S_Config1IS
217#define C0_CONFIG1_IS_MSK M_Config1IS 217#define C0_CONFIG1_IS_MSK M_Config1IS
218 218
219#define C0_CONFIG1_IL_SHF S_Config1IL 219#define C0_CONFIG1_IL_SHF S_Config1IL
220#define C0_CONFIG1_IL_MSK M_Config1IL 220#define C0_CONFIG1_IL_MSK M_Config1IL
221 221
222#define C0_CONFIG1_IA_SHF S_Config1IA 222#define C0_CONFIG1_IA_SHF S_Config1IA
223#define C0_CONFIG1_IA_MSK M_Config1IA 223#define C0_CONFIG1_IA_MSK M_Config1IA
224 224
225#define C0_CONFIG1_DS_SHF S_Config1DS 225#define C0_CONFIG1_DS_SHF S_Config1DS
226#define C0_CONFIG1_DS_MSK M_Config1DS 226#define C0_CONFIG1_DS_MSK M_Config1DS
227 227
228#define C0_CONFIG1_DL_SHF S_Config1DL 228#define C0_CONFIG1_DL_SHF S_Config1DL
229#define C0_CONFIG1_DL_MSK M_Config1DL 229#define C0_CONFIG1_DL_MSK M_Config1DL
230 230
231#define C0_CONFIG1_DA_SHF S_Config1DA 231#define C0_CONFIG1_DA_SHF S_Config1DA
232#define C0_CONFIG1_DA_MSK M_Config1DA 232#define C0_CONFIG1_DA_MSK M_Config1DA
233 233
234#define C0_CONFIG1_WR_SHF S_Config1WR 234#define C0_CONFIG1_WR_SHF S_Config1WR
235#define C0_CONFIG1_WR_MSK M_Config1WR 235#define C0_CONFIG1_WR_MSK M_Config1WR
236#define C0_CONFIG1_WR_BIT C0_CONFIG1_WR_MSK 236#define C0_CONFIG1_WR_BIT C0_CONFIG1_WR_MSK
237 237
238#define C0_CONFIG1_CA_SHF S_Config1CA 238#define C0_CONFIG1_CA_SHF S_Config1CA
239#define C0_CONFIG1_CA_MSK M_Config1CA 239#define C0_CONFIG1_CA_MSK M_Config1CA
240#define C0_CONFIG1_CA_BIT C0_CONFIG1_CA_MSK 240#define C0_CONFIG1_CA_BIT C0_CONFIG1_CA_MSK
241 241
242#define C0_CONFIG1_EP_SHF S_Config1EP 242#define C0_CONFIG1_EP_SHF S_Config1EP
243#define C0_CONFIG1_EP_MSK M_Config1EP 243#define C0_CONFIG1_EP_MSK M_Config1EP
244#define C0_CONFIG1_EP_BIT C0_CONFIG1_EP_MSK 244#define C0_CONFIG1_EP_BIT C0_CONFIG1_EP_MSK
245 245
246#define C0_CONFIG1_FP_SHF S_Config1FP 246#define C0_CONFIG1_FP_SHF S_Config1FP
247#define C0_CONFIG1_FP_MSK M_Config1FP 247#define C0_CONFIG1_FP_MSK M_Config1FP
248#define C0_CONFIG1_FP_BIT C0_CONFIG1_FP_MSK 248#define C0_CONFIG1_FP_BIT C0_CONFIG1_FP_MSK
249 249
250 250
251/* C0_STATUS register encoding */ 251/* C0_STATUS register encoding */
252 252
253#define C0_STATUS_CU3_SHF S_StatusCU3 253#define C0_STATUS_CU3_SHF S_StatusCU3
254#define C0_STATUS_CU3_MSK M_StatusCU3 254#define C0_STATUS_CU3_MSK M_StatusCU3
255#define C0_STATUS_CU3_BIT C0_STATUS_CU3_MSK 255#define C0_STATUS_CU3_BIT C0_STATUS_CU3_MSK
256 256
257#define C0_STATUS_CU2_SHF S_StatusCU2 257#define C0_STATUS_CU2_SHF S_StatusCU2
258#define C0_STATUS_CU2_MSK M_StatusCU2 258#define C0_STATUS_CU2_MSK M_StatusCU2
259#define C0_STATUS_CU2_BIT C0_STATUS_CU2_MSK 259#define C0_STATUS_CU2_BIT C0_STATUS_CU2_MSK
260 260
261#define C0_STATUS_CU1_SHF S_StatusCU1 261#define C0_STATUS_CU1_SHF S_StatusCU1
262#define C0_STATUS_CU1_MSK M_StatusCU1 262#define C0_STATUS_CU1_MSK M_StatusCU1
263#define C0_STATUS_CU1_BIT C0_STATUS_CU1_MSK 263#define C0_STATUS_CU1_BIT C0_STATUS_CU1_MSK
264 264
265#define C0_STATUS_CU0_SHF S_StatusCU1 265#define C0_STATUS_CU0_SHF S_StatusCU1
266#define C0_STATUS_CU0_MSK M_StatusCU1 266#define C0_STATUS_CU0_MSK M_StatusCU1
267#define C0_STATUS_CU0_BIT C0_STATUS_CU0_MSK 267#define C0_STATUS_CU0_BIT C0_STATUS_CU0_MSK
268 268
269#define C0_STATUS_RP_SHF S_StatusRP 269#define C0_STATUS_RP_SHF S_StatusRP
270#define C0_STATUS_RP_MSK M_StatusRP 270#define C0_STATUS_RP_MSK M_StatusRP
271#define C0_STATUS_RP_BIT C0_STATUS_RP_MSK 271#define C0_STATUS_RP_BIT C0_STATUS_RP_MSK
272 272
273#define C0_STATUS_FR_SHF S_StatusFR 273#define C0_STATUS_FR_SHF S_StatusFR
274#define C0_STATUS_FR_MSK M_StatusFR 274#define C0_STATUS_FR_MSK M_StatusFR
275#define C0_STATUS_FR_BIT C0_STATUS_FR_MSK 275#define C0_STATUS_FR_BIT C0_STATUS_FR_MSK
276 276
277#define C0_STATUS_RE_SHF S_StatusRE 277#define C0_STATUS_RE_SHF S_StatusRE
278#define C0_STATUS_RE_MSK M_StatusRE 278#define C0_STATUS_RE_MSK M_StatusRE
279#define C0_STATUS_RE_BIT C0_STATUS_RE_MSK 279#define C0_STATUS_RE_BIT C0_STATUS_RE_MSK
280 280
281#define C0_STATUS_BEV_SHF S_StatusBEV 281#define C0_STATUS_BEV_SHF S_StatusBEV
282#define C0_STATUS_BEV_MSK M_StatusBEV 282#define C0_STATUS_BEV_MSK M_StatusBEV
283#define C0_STATUS_BEV_BIT C0_STATUS_BEV_MSK 283#define C0_STATUS_BEV_BIT C0_STATUS_BEV_MSK
284 284
285#define C0_STATUS_TS_SHF S_StatusTS 285#define C0_STATUS_TS_SHF S_StatusTS
286#define C0_STATUS_TS_MSK M_StatusTS 286#define C0_STATUS_TS_MSK M_StatusTS
287#define C0_STATUS_TS_BIT C0_STATUS_TS_MSK 287#define C0_STATUS_TS_BIT C0_STATUS_TS_MSK
288 288
289#define C0_STATUS_SR_SHF S_StatusSR 289#define C0_STATUS_SR_SHF S_StatusSR
290#define C0_STATUS_SR_MSK M_StatusSR 290#define C0_STATUS_SR_MSK M_StatusSR
291#define C0_STATUS_SR_BIT C0_STATUS_SR_MSK 291#define C0_STATUS_SR_BIT C0_STATUS_SR_MSK
292 292
293#define C0_STATUS_NMI_SHF S_StatusNMI 293#define C0_STATUS_NMI_SHF S_StatusNMI
294#define C0_STATUS_NMI_MSK M_StatusNMI 294#define C0_STATUS_NMI_MSK M_StatusNMI
295#define C0_STATUS_NMI_BIT C0_STATUS_NMI_MSK 295#define C0_STATUS_NMI_BIT C0_STATUS_NMI_MSK
296 296
297#define C0_STATUS_IM_SHF S_StatusIM 297#define C0_STATUS_IM_SHF S_StatusIM
298#define C0_STATUS_IM_MSK M_StatusIM 298#define C0_STATUS_IM_MSK M_StatusIM
299/* Note that the the definitions below indicate the interrupt number 299/* Note that the the definitions below indicate the interrupt number
300 * rather than the mask. 300 * rather than the mask.
301 * (0..1 for SW interrupts and 2...7 for HW interrupts) 301 * (0..1 for SW interrupts and 2...7 for HW interrupts)
302 */ 302 */
303#define C0_STATUS_IM_SW0 (S_StatusIM0 - S_StatusIM) 303#define C0_STATUS_IM_SW0 (S_StatusIM0 - S_StatusIM)
304#define C0_STATUS_IM_SW1 (S_StatusIM1 - S_StatusIM) 304#define C0_STATUS_IM_SW1 (S_StatusIM1 - S_StatusIM)
305#define C0_STATUS_IM_HW0 (S_StatusIM2 - S_StatusIM) 305#define C0_STATUS_IM_HW0 (S_StatusIM2 - S_StatusIM)
306#define C0_STATUS_IM_HW1 (S_StatusIM3 - S_StatusIM) 306#define C0_STATUS_IM_HW1 (S_StatusIM3 - S_StatusIM)
307#define C0_STATUS_IM_HW2 (S_StatusIM4 - S_StatusIM) 307#define C0_STATUS_IM_HW2 (S_StatusIM4 - S_StatusIM)
308#define C0_STATUS_IM_HW3 (S_StatusIM5 - S_StatusIM) 308#define C0_STATUS_IM_HW3 (S_StatusIM5 - S_StatusIM)
309#define C0_STATUS_IM_HW4 (S_StatusIM6 - S_StatusIM) 309#define C0_STATUS_IM_HW4 (S_StatusIM6 - S_StatusIM)
310#define C0_STATUS_IM_HW5 (S_StatusIM7 - S_StatusIM) 310#define C0_STATUS_IM_HW5 (S_StatusIM7 - S_StatusIM)
311 311
312/* Max interrupt code */ 312/* Max interrupt code */
313#define C0_STATUS_IM_MAX C0_STATUS_IM_HW5 313#define C0_STATUS_IM_MAX C0_STATUS_IM_HW5
314 314
315#define C0_STATUS_KSU_SHF S_StatusKSU 315#define C0_STATUS_KSU_SHF S_StatusKSU
316#define C0_STATUS_KSU_MSK M_StatusKSU 316#define C0_STATUS_KSU_MSK M_StatusKSU
317 317
318#define C0_STATUS_UM_SHF S_StatusUM 318#define C0_STATUS_UM_SHF S_StatusUM
319#define C0_STATUS_UM_MSK M_StatusUM 319#define C0_STATUS_UM_MSK M_StatusUM
320#define C0_STATUS_UM_BIT C0_STATUS_UM_MSK 320#define C0_STATUS_UM_BIT C0_STATUS_UM_MSK
321 321
322#define C0_STATUS_ERL_SHF S_StatusERL 322#define C0_STATUS_ERL_SHF S_StatusERL
323#define C0_STATUS_ERL_MSK M_StatusERL 323#define C0_STATUS_ERL_MSK M_StatusERL
324#define C0_STATUS_ERL_BIT C0_STATUS_ERL_MSK 324#define C0_STATUS_ERL_BIT C0_STATUS_ERL_MSK
325 325
326#define C0_STATUS_EXL_SHF S_StatusEXL 326#define C0_STATUS_EXL_SHF S_StatusEXL
327#define C0_STATUS_EXL_MSK M_StatusEXL 327#define C0_STATUS_EXL_MSK M_StatusEXL
328#define C0_STATUS_EXL_BIT C0_STATUS_EXL_MSK 328#define C0_STATUS_EXL_BIT C0_STATUS_EXL_MSK
329 329
330#define C0_STATUS_IE_SHF S_StatusIE 330#define C0_STATUS_IE_SHF S_StatusIE
331#define C0_STATUS_IE_MSK M_StatusIE 331#define C0_STATUS_IE_MSK M_StatusIE
332#define C0_STATUS_IE_BIT C0_STATUS_IE_MSK 332#define C0_STATUS_IE_BIT C0_STATUS_IE_MSK
333 333
334 334
335/* C0_PRID register encoding */ 335/* C0_PRID register encoding */
336 336
337#define C0_PRID_OPT_SHF S_PRIdCoOpt 337#define C0_PRID_OPT_SHF S_PRIdCoOpt
338#define C0_PRID_OPT_MSK M_PRIdCoOpt 338#define C0_PRID_OPT_MSK M_PRIdCoOpt
339 339
340#define C0_PRID_COMP_SHF S_PRIdCoID 340#define C0_PRID_COMP_SHF S_PRIdCoID
341#define C0_PRID_COMP_MSK M_PRIdCoID 341#define C0_PRID_COMP_MSK M_PRIdCoID
342#define C0_PRID_COMP_MIPS K_PRIdCoID_MIPS 342#define C0_PRID_COMP_MIPS K_PRIdCoID_MIPS
343#define C0_PRID_COMP_NOT_MIPS32_64 0 343#define C0_PRID_COMP_NOT_MIPS32_64 0
344 344
345#define C0_PRID_PRID_SHF S_PRIdImp 345#define C0_PRID_PRID_SHF S_PRIdImp
346#define C0_PRID_PRID_MSK M_PRIdImp 346#define C0_PRID_PRID_MSK M_PRIdImp
347 347
348/* Jade */ 348/* Jade */
349#define C0_PRID_PRID_4Kc K_PRIdImp_Jade 349#define C0_PRID_PRID_4Kc K_PRIdImp_Jade
350#define C0_PRID_PRID_4Kmp K_PRIdImp_JadeLite /* 4Km/4Kp */ 350#define C0_PRID_PRID_4Kmp K_PRIdImp_JadeLite /* 4Km/4Kp */
351/* Emerald */ 351/* Emerald */
352#define C0_PRID_PRID_4KEc K_PRIdImp_4KEc 352#define C0_PRID_PRID_4KEc K_PRIdImp_4KEc
353#define C0_PRID_PRID_4KEmp K_PRIdImp_4KEmp 353#define C0_PRID_PRID_4KEmp K_PRIdImp_4KEmp
354/* Coral */ 354/* Coral */
355#define C0_PRID_PRID_4KSc K_PRIdImp_4KSc 355#define C0_PRID_PRID_4KSc K_PRIdImp_4KSc
356/* Opal */ 356/* Opal */
357#define C0_PRID_PRID_5K K_PRIdImp_Opal 357#define C0_PRID_PRID_5K K_PRIdImp_Opal
358/* Ruby */ 358/* Ruby */
359#define C0_PRID_PRID_20Kc K_PRIdImp_Ruby 359#define C0_PRID_PRID_20Kc K_PRIdImp_Ruby
360/* Other CPUs */ 360/* Other CPUs */
361#define C0_PRID_PRID_R4000 K_PRIdImp_R4000 361#define C0_PRID_PRID_R4000 K_PRIdImp_R4000
362#define C0_PRID_PRID_RM52XX K_PRIdImp_R5200 362#define C0_PRID_PRID_RM52XX K_PRIdImp_R5200
363#define C0_PRID_PRID_RM70XX 0x27 363#define C0_PRID_PRID_RM70XX 0x27
364 364
365#define C0_PRID_REV_SHF S_PRIdRev 365#define C0_PRID_REV_SHF S_PRIdRev
366#define C0_PRID_REV_MSK M_PRIdRev 366#define C0_PRID_REV_MSK M_PRIdRev
367 367
368 368
369#define MIPS_4Kc ( (C0_PRID_COMP_MIPS << \ 369#define MIPS_4Kc ( (C0_PRID_COMP_MIPS << \
370 C0_PRID_COMP_SHF) | \ 370 C0_PRID_COMP_SHF) | \
371 (C0_PRID_PRID_4Kc << \ 371 (C0_PRID_PRID_4Kc << \
372 C0_PRID_PRID_SHF) \ 372 C0_PRID_PRID_SHF) \
373 ) 373 )
374 374
375#define MIPS_4Kmp ( (C0_PRID_COMP_MIPS << \ 375#define MIPS_4Kmp ( (C0_PRID_COMP_MIPS << \
376 C0_PRID_COMP_SHF) | \ 376 C0_PRID_COMP_SHF) | \
377 (C0_PRID_PRID_4Kmp << \ 377 (C0_PRID_PRID_4Kmp << \
378 C0_PRID_PRID_SHF) \ 378 C0_PRID_PRID_SHF) \
379 ) 379 )
380 380
381#define MIPS_4KEc ( (C0_PRID_COMP_MIPS << \ 381#define MIPS_4KEc ( (C0_PRID_COMP_MIPS << \
382 C0_PRID_COMP_SHF) | \ 382 C0_PRID_COMP_SHF) | \
383 (C0_PRID_PRID_4KEc << \ 383 (C0_PRID_PRID_4KEc << \
384 C0_PRID_PRID_SHF) \ 384 C0_PRID_PRID_SHF) \
385 ) 385 )
386 386
387#define MIPS_4KEmp ( (C0_PRID_COMP_MIPS << \ 387#define MIPS_4KEmp ( (C0_PRID_COMP_MIPS << \
388 C0_PRID_COMP_SHF) | \ 388 C0_PRID_COMP_SHF) | \
389 (C0_PRID_PRID_4KEmp << \ 389 (C0_PRID_PRID_4KEmp << \
390 C0_PRID_PRID_SHF) \ 390 C0_PRID_PRID_SHF) \
391 ) 391 )
392 392
393#define MIPS_4KSc ( (C0_PRID_COMP_MIPS << \ 393#define MIPS_4KSc ( (C0_PRID_COMP_MIPS << \
394 C0_PRID_COMP_SHF) | \ 394 C0_PRID_COMP_SHF) | \
395 (C0_PRID_PRID_4KSc << \ 395 (C0_PRID_PRID_4KSc << \
396 C0_PRID_PRID_SHF) \ 396 C0_PRID_PRID_SHF) \
397 ) 397 )
398 398
399#define MIPS_5K ( (C0_PRID_COMP_MIPS << \ 399#define MIPS_5K ( (C0_PRID_COMP_MIPS << \
400 C0_PRID_COMP_SHF) | \ 400 C0_PRID_COMP_SHF) | \
401 (C0_PRID_PRID_5K << \ 401 (C0_PRID_PRID_5K << \
402 C0_PRID_PRID_SHF) \ 402 C0_PRID_PRID_SHF) \
403 ) 403 )
404 404
405#define MIPS_20Kc ( (C0_PRID_COMP_MIPS << \ 405#define MIPS_20Kc ( (C0_PRID_COMP_MIPS << \
406 C0_PRID_COMP_SHF) | \ 406 C0_PRID_COMP_SHF) | \
407 (C0_PRID_PRID_20Kc << \ 407 (C0_PRID_PRID_20Kc << \
408 C0_PRID_PRID_SHF) \ 408 C0_PRID_PRID_SHF) \
409 ) 409 )
410 410
411#define QED_RM52XX ( (C0_PRID_COMP_NOT_MIPS32_64 << \ 411#define QED_RM52XX ( (C0_PRID_COMP_NOT_MIPS32_64 << \
412 C0_PRID_COMP_SHF) | \ 412 C0_PRID_COMP_SHF) | \
413 (C0_PRID_PRID_RM52XX << \ 413 (C0_PRID_PRID_RM52XX << \
414 C0_PRID_PRID_SHF) \ 414 C0_PRID_PRID_SHF) \
415 ) 415 )
416 416
417#define QED_RM70XX ( (C0_PRID_COMP_NOT_MIPS32_64 << \ 417#define QED_RM70XX ( (C0_PRID_COMP_NOT_MIPS32_64 << \
418 C0_PRID_COMP_SHF) | \ 418 C0_PRID_COMP_SHF) | \
419 (C0_PRID_PRID_RM70XX << \ 419 (C0_PRID_PRID_RM70XX << \
420 C0_PRID_PRID_SHF) \ 420 C0_PRID_PRID_SHF) \
421 ) 421 )
422 422
423/* C0_ENTRYHI register encoding */ 423/* C0_ENTRYHI register encoding */
424 424
425#define C0_ENTRYHI_VPN2_SHF S_EntryHiVPN2 425#define C0_ENTRYHI_VPN2_SHF S_EntryHiVPN2
426#define C0_ENTRYHI_VPN2_MSK M_EntryHiVPN2 426#define C0_ENTRYHI_VPN2_MSK M_EntryHiVPN2
427 427
428#define C0_ENTRYHI_ASID_SHF S_EntryHiASID 428#define C0_ENTRYHI_ASID_SHF S_EntryHiASID
429#define C0_ENTRYHI_ASID_MSK M_EntryHiASID 429#define C0_ENTRYHI_ASID_MSK M_EntryHiASID
430 430
431 431
432/* C0_CAUSE register encoding */ 432/* C0_CAUSE register encoding */
433 433
434#define C0_CAUSE_BD_SHF S_CauseBD 434#define C0_CAUSE_BD_SHF S_CauseBD
435#define C0_CAUSE_BD_MSK M_CauseBD 435#define C0_CAUSE_BD_MSK M_CauseBD
436#define C0_CAUSE_BD_BIT C0_CAUSE_BD_MSK 436#define C0_CAUSE_BD_BIT C0_CAUSE_BD_MSK
437 437
438#define C0_CAUSE_CE_SHF S_CauseCE 438#define C0_CAUSE_CE_SHF S_CauseCE
439#define C0_CAUSE_CE_MSK M_CauseCE 439#define C0_CAUSE_CE_MSK M_CauseCE
440 440
441#define C0_CAUSE_IV_SHF S_CauseIV 441#define C0_CAUSE_IV_SHF S_CauseIV
442#define C0_CAUSE_IV_MSK M_CauseIV 442#define C0_CAUSE_IV_MSK M_CauseIV
443#define C0_CAUSE_IV_BIT C0_CAUSE_IV_MSK 443#define C0_CAUSE_IV_BIT C0_CAUSE_IV_MSK
444 444
445#define C0_CAUSE_WP_SHF S_CauseWP 445#define C0_CAUSE_WP_SHF S_CauseWP
446#define C0_CAUSE_WP_MSK M_CauseWP 446#define C0_CAUSE_WP_MSK M_CauseWP
447#define C0_CAUSE_WP_BIT C0_CAUSE_WP_MSK 447#define C0_CAUSE_WP_BIT C0_CAUSE_WP_MSK
448 448
449#define C0_CAUSE_IP_SHF S_CauseIP 449#define C0_CAUSE_IP_SHF S_CauseIP
450#define C0_CAUSE_IP_MSK M_CauseIP 450#define C0_CAUSE_IP_MSK M_CauseIP
451 451
452#define C0_CAUSE_CODE_SHF S_CauseExcCode 452#define C0_CAUSE_CODE_SHF S_CauseExcCode
453#define C0_CAUSE_CODE_MSK M_CauseExcCode 453#define C0_CAUSE_CODE_MSK M_CauseExcCode
454 454
455#define C0_CAUSE_CODE_INT EX_INT 455#define C0_CAUSE_CODE_INT EX_INT
456#define C0_CAUSE_CODE_MOD EX_MOD 456#define C0_CAUSE_CODE_MOD EX_MOD
457#define C0_CAUSE_CODE_TLBL EX_TLBL 457#define C0_CAUSE_CODE_TLBL EX_TLBL
458#define C0_CAUSE_CODE_TLBS EX_TLBS 458#define C0_CAUSE_CODE_TLBS EX_TLBS
459#define C0_CAUSE_CODE_ADEL EX_ADEL 459#define C0_CAUSE_CODE_ADEL EX_ADEL
460#define C0_CAUSE_CODE_ADES EX_ADES 460#define C0_CAUSE_CODE_ADES EX_ADES
461#define C0_CAUSE_CODE_IBE EX_IBE 461#define C0_CAUSE_CODE_IBE EX_IBE
462#define C0_CAUSE_CODE_DBE EX_DBE 462#define C0_CAUSE_CODE_DBE EX_DBE
463#define C0_CAUSE_CODE_SYS EX_SYS 463#define C0_CAUSE_CODE_SYS EX_SYS
464#define C0_CAUSE_CODE_BP EX_BP 464#define C0_CAUSE_CODE_BP EX_BP
465#define C0_CAUSE_CODE_RI EX_RI 465#define C0_CAUSE_CODE_RI EX_RI
466#define C0_CAUSE_CODE_CPU EX_CPU 466#define C0_CAUSE_CODE_CPU EX_CPU
467#define C0_CAUSE_CODE_OV EX_OV 467#define C0_CAUSE_CODE_OV EX_OV
468#define C0_CAUSE_CODE_TR EV_TR 468#define C0_CAUSE_CODE_TR EV_TR
469#define C0_CAUSE_CODE_FPE EX_FPE 469#define C0_CAUSE_CODE_FPE EX_FPE
470#define C0_CAUSE_CODE_WATCH EX_WATCH 470#define C0_CAUSE_CODE_WATCH EX_WATCH
471#define C0_CAUSE_CODE_MCHECK EX_MCHECK 471#define C0_CAUSE_CODE_MCHECK EX_MCHECK
472 472
473/* Max cause code */ 473/* Max cause code */
474#define C0_CAUSE_CODE_MAX EX_MCHECK 474#define C0_CAUSE_CODE_MAX EX_MCHECK
475 475
476 476
477/* C0_PAGEMASK register encoding */ 477/* C0_PAGEMASK register encoding */
478#define C0_PAGEMASK_MASK_SHF S_PageMaskMask 478#define C0_PAGEMASK_MASK_SHF S_PageMaskMask
479#define C0_PAGEMASK_MASK_MSK M_PageMaskMask 479#define C0_PAGEMASK_MASK_MSK M_PageMaskMask
480#define C0_PAGEMASK_MASK_4K K_PageMask4K 480#define C0_PAGEMASK_MASK_4K K_PageMask4K
481#define C0_PAGEMASK_MASK_16K K_PageMask16K 481#define C0_PAGEMASK_MASK_16K K_PageMask16K
482#define C0_PAGEMASK_MASK_64K K_PageMask64K 482#define C0_PAGEMASK_MASK_64K K_PageMask64K
483#define C0_PAGEMASK_MASK_256K K_PageMask256K 483#define C0_PAGEMASK_MASK_256K K_PageMask256K
484#define C0_PAGEMASK_MASK_1M K_PageMask1M 484#define C0_PAGEMASK_MASK_1M K_PageMask1M
485#define C0_PAGEMASK_MASK_4M K_PageMask4M 485#define C0_PAGEMASK_MASK_4M K_PageMask4M
486#define C0_PAGEMASK_MASK_16M K_PageMask16M 486#define C0_PAGEMASK_MASK_16M K_PageMask16M
487 487
488 488
489/* C0_ENTRYLO0 register encoding (equiv. to C0_ENTRYLO1) */ 489/* C0_ENTRYLO0 register encoding (equiv. to C0_ENTRYLO1) */
490#define C0_ENTRYLO0_PFN_SHF S_EntryLoPFN 490#define C0_ENTRYLO0_PFN_SHF S_EntryLoPFN
491#define C0_ENTRYLO0_PFN_MSK M_EntryLoPFN 491#define C0_ENTRYLO0_PFN_MSK M_EntryLoPFN
492 492
493#define C0_ENTRYLO0_C_SHF S_EntryLoC 493#define C0_ENTRYLO0_C_SHF S_EntryLoC
494#define C0_ENTRYLO0_C_MSK M_EntryLoC 494#define C0_ENTRYLO0_C_MSK M_EntryLoC
495 495
496#define C0_ENTRYLO0_D_SHF S_EntryLoD 496#define C0_ENTRYLO0_D_SHF S_EntryLoD
497#define C0_ENTRYLO0_D_MSK M_EntryLoD 497#define C0_ENTRYLO0_D_MSK M_EntryLoD
498 498
499#define C0_ENTRYLO0_V_SHF S_EntryLoV 499#define C0_ENTRYLO0_V_SHF S_EntryLoV
500#define C0_ENTRYLO0_V_MSK M_EntryLoV 500#define C0_ENTRYLO0_V_MSK M_EntryLoV
501 501
502#define C0_ENTRYLO0_G_SHF S_EntryLoG 502#define C0_ENTRYLO0_G_SHF S_EntryLoG
503#define C0_ENTRYLO0_G_MSK M_EntryLoG 503#define C0_ENTRYLO0_G_MSK M_EntryLoG
504 504
505 505
506/* FPU (CP1) FIR register encoding */ 506/* FPU (CP1) FIR register encoding */
507#define C1_FIR_3D_SHF S_FIRConfig3D 507#define C1_FIR_3D_SHF S_FIRConfig3D
508#define C1_FIR_3D_MSK M_FIRConfig3D 508#define C1_FIR_3D_MSK M_FIRConfig3D
509 509
510#define C1_FIR_PS_SHF S_FIRConfigPS 510#define C1_FIR_PS_SHF S_FIRConfigPS
511#define C1_FIR_PS_MSK M_FIRConfigPS 511#define C1_FIR_PS_MSK M_FIRConfigPS
512 512
513#define C1_FIR_D_SHF S_FIRConfigD 513#define C1_FIR_D_SHF S_FIRConfigD
514#define C1_FIR_D_MSK M_FIRConfigD 514#define C1_FIR_D_MSK M_FIRConfigD
515 515
516#define C1_FIR_S_SHF S_FIRConfigS 516#define C1_FIR_S_SHF S_FIRConfigS
517#define C1_FIR_S_MSK M_FIRConfigS 517#define C1_FIR_S_MSK M_FIRConfigS
518 518
519#define C1_FIR_PRID_SHF S_FIRImp 519#define C1_FIR_PRID_SHF S_FIRImp
520#define C1_FIR_PRID_MSK M_FIRImp 520#define C1_FIR_PRID_MSK M_FIRImp
521 521
522#define C1_FIR_REV_SHF S_FIRRev 522#define C1_FIR_REV_SHF S_FIRRev
523#define C1_FIR_REV_MSK M_FIRRev 523#define C1_FIR_REV_MSK M_FIRRev
524 524
525 525
526/* FPU (CP1) FCSR control/status register */ 526/* FPU (CP1) FCSR control/status register */
527#define C1_FCSR_FCC_SHF S_FCSRFCC7_1 527#define C1_FCSR_FCC_SHF S_FCSRFCC7_1
528#define C1_FCSR_FCC_MSK M_FCSRFCC7_1 528#define C1_FCSR_FCC_MSK M_FCSRFCC7_1
529 529
530#define C1_FCSR_FS_SHF S_FCSRFS 530#define C1_FCSR_FS_SHF S_FCSRFS
531#define C1_FCSR_FS_MSK M_FCSRFS 531#define C1_FCSR_FS_MSK M_FCSRFS
532#define C1_FCSR_FS_BIT C1_FCSR_FS_MSK 532#define C1_FCSR_FS_BIT C1_FCSR_FS_MSK
533 533
534#define C1_FCSR_CC_SHF S_FCSRCC 534#define C1_FCSR_CC_SHF S_FCSRCC
535#define C1_FCSR_CC_MSK M_FCSRCC 535#define C1_FCSR_CC_MSK M_FCSRCC
536 536
537#define C1_FCSR_IMPL_SHF S_FCSRImpl 537#define C1_FCSR_IMPL_SHF S_FCSRImpl
538#define C1_FCSR_IMPL_MSK M_FCSRImpl 538#define C1_FCSR_IMPL_MSK M_FCSRImpl
539 539
540#define C1_FCSR_EXC_SHF S_FCSRExc 540#define C1_FCSR_EXC_SHF S_FCSRExc
541#define C1_FCSR_EXC_MSK M_FCSRExc 541#define C1_FCSR_EXC_MSK M_FCSRExc
542 542
543#define C1_FCSR_ENA_SHF S_FCSREna 543#define C1_FCSR_ENA_SHF S_FCSREna
544#define C1_FCSR_ENA_MSK M_FCSREna 544#define C1_FCSR_ENA_MSK M_FCSREna
545 545
546#define C1_FCSR_FLG_SHF S_FCSRFlg 546#define C1_FCSR_FLG_SHF S_FCSRFlg
547#define C1_FCSR_FLG_MSK M_FCSRFlg 547#define C1_FCSR_FLG_MSK M_FCSRFlg
548 548
549#define C1_FCSR_RM_SHF S_FCSRRM 549#define C1_FCSR_RM_SHF S_FCSRRM
550#define C1_FCSR_RM_MSK M_FCSRRM 550#define C1_FCSR_RM_MSK M_FCSRRM
551#define C1_FCSR_RM_RN K_FCSRRM_RN 551#define C1_FCSR_RM_RN K_FCSRRM_RN
552#define C1_FCSR_RM_RZ K_FCSRRM_RZ 552#define C1_FCSR_RM_RZ K_FCSRRM_RZ
553#define C1_FCSR_RM_RP K_FCSRRM_RP 553#define C1_FCSR_RM_RP K_FCSRRM_RP
554#define C1_FCSR_RM_RM K_FCSRRM_RM 554#define C1_FCSR_RM_RM K_FCSRRM_RM
555 555
556 556
557 557
558/* cache operations */ 558/* cache operations */
559 559
560#define CACHE_OP( code, type ) ( ((code) << 2) | (type) ) 560#define CACHE_OP( code, type ) ( ((code) << 2) | (type) )
561 561
562#define ICACHE_INDEX_INVALIDATE CACHE_OP(0x0, 0) 562#define ICACHE_INDEX_INVALIDATE CACHE_OP(0x0, 0)
563#define ICACHE_INDEX_LOAD_TAG CACHE_OP(0x1, 0) 563#define ICACHE_INDEX_LOAD_TAG CACHE_OP(0x1, 0)
564#define ICACHE_INDEX_STORE_TAG CACHE_OP(0x2, 0) 564#define ICACHE_INDEX_STORE_TAG CACHE_OP(0x2, 0)
565#define DCACHE_INDEX_WRITEBACK_INVALIDATE CACHE_OP(0x0, 1) 565#define DCACHE_INDEX_WRITEBACK_INVALIDATE CACHE_OP(0x0, 1)
566#define DCACHE_INDEX_LOAD_TAG CACHE_OP(0x1, 1) 566#define DCACHE_INDEX_LOAD_TAG CACHE_OP(0x1, 1)
567#define DCACHE_INDEX_STORE_TAG CACHE_OP(0x2, 1) 567#define DCACHE_INDEX_STORE_TAG CACHE_OP(0x2, 1)
568#define SCACHE_INDEX_STORE_TAG CACHE_OP(0x2, 3) 568#define SCACHE_INDEX_STORE_TAG CACHE_OP(0x2, 3)
569 569
570#define ICACHE_ADDR_HIT_INVALIDATE CACHE_OP(0x4, 0) 570#define ICACHE_ADDR_HIT_INVALIDATE CACHE_OP(0x4, 0)
571#define ICACHE_ADDR_FILL CACHE_OP(0x5, 0) 571#define ICACHE_ADDR_FILL CACHE_OP(0x5, 0)
572#define ICACHE_ADDR_FETCH_LOCK CACHE_OP(0x7, 0) 572#define ICACHE_ADDR_FETCH_LOCK CACHE_OP(0x7, 0)
573#define DCACHE_ADDR_HIT_INVALIDATE CACHE_OP(0x4, 1) 573#define DCACHE_ADDR_HIT_INVALIDATE CACHE_OP(0x4, 1)
574#define DCACHE_ADDR_HIT_WRITEBACK_INVALIDATE CACHE_OP(0x5, 1) 574#define DCACHE_ADDR_HIT_WRITEBACK_INVALIDATE CACHE_OP(0x5, 1)
575#define DCACHE_ADDR_HIT_WRITEBACK CACHE_OP(0x6, 1) 575#define DCACHE_ADDR_HIT_WRITEBACK CACHE_OP(0x6, 1)
576#define DCACHE_ADDR_FETCH_LOCK CACHE_OP(0x7, 1) 576#define DCACHE_ADDR_FETCH_LOCK CACHE_OP(0x7, 1)
577 577
578#define SCACHE_ADDR_HIT_WRITEBACK_INVALIDATE CACHE_OP(0x5, 3) 578#define SCACHE_ADDR_HIT_WRITEBACK_INVALIDATE CACHE_OP(0x5, 3)
579 579
580/* Workaround for bug in early revisions of MIPS 4K family of 580/* Workaround for bug in early revisions of MIPS 4K family of
581 * processors. Only relevant in early engineering samples of test 581 * processors. Only relevant in early engineering samples of test
@@ -594,44 +594,44 @@
594#define SET_POP() 594#define SET_POP()
595#endif 595#endif
596#define ICACHE_INVALIDATE_WORKAROUND(reg) \ 596#define ICACHE_INVALIDATE_WORKAROUND(reg) \
597SET_PUSH(); \ 597SET_PUSH(); \
598SET_MIPS0(); \ 598SET_MIPS0(); \
599 la reg, 999f; \ 599 la reg, 999f; \
600SET_POP(); \ 600SET_POP(); \
601 cache ICACHE_ADDR_FILL, 0(reg); \ 601 cache ICACHE_ADDR_FILL, 0(reg); \
602 sync; \ 602 sync; \
603 nop; nop; nop; nop; \ 603 nop; nop; nop; nop; \
604999: 604999:
605 605
606/* EMPTY_PIPELINE is used for the below cache invalidation operations. 606/* EMPTY_PIPELINE is used for the below cache invalidation operations.
607 * When $I is invalidated, there will still be operations in the 607 * When $I is invalidated, there will still be operations in the
608 * pipeline. We make sure these are 'nop' operations. 608 * pipeline. We make sure these are 'nop' operations.
609 */ 609 */
610#define EMPTY_PIPELINE nop; nop; nop; nop 610#define EMPTY_PIPELINE nop; nop; nop; nop
611 611
612#define ICACHE_INDEX_INVALIDATE_OP(index,scratch) \ 612#define ICACHE_INDEX_INVALIDATE_OP(index,scratch) \
613 ICACHE_INVALIDATE_WORKAROUND(scratch); \ 613 ICACHE_INVALIDATE_WORKAROUND(scratch); \
614 cache ICACHE_INDEX_INVALIDATE, 0(index); \ 614 cache ICACHE_INDEX_INVALIDATE, 0(index); \
615 EMPTY_PIPELINE 615 EMPTY_PIPELINE
616 616
617#define ICACHE_ADDR_INVALIDATE_OP(addr,scratch) \ 617#define ICACHE_ADDR_INVALIDATE_OP(addr,scratch) \
618 ICACHE_INVALIDATE_WORKAROUND(scratch); \ 618 ICACHE_INVALIDATE_WORKAROUND(scratch); \
619 cache ICACHE_ADDR_HIT_INVALIDATE, 0(addr); \ 619 cache ICACHE_ADDR_HIT_INVALIDATE, 0(addr); \
620 EMPTY_PIPELINE 620 EMPTY_PIPELINE
621 621
622/* The sync used in the below macro is there in case we are installing 622/* The sync used in the below macro is there in case we are installing
623 * a new instruction (flush $D, sync, invalidate $I sequence). 623 * a new instruction (flush $D, sync, invalidate $I sequence).
624 */ 624 */
625#define SCACHE_ADDR_HIT_WB_INVALIDATE_OP(reg) \ 625#define SCACHE_ADDR_HIT_WB_INVALIDATE_OP(reg) \
626 cache SCACHE_ADDR_HIT_WRITEBACK_INVALIDATE, 0(reg); \ 626 cache SCACHE_ADDR_HIT_WRITEBACK_INVALIDATE, 0(reg); \
627 sync; \ 627 sync; \
628 EMPTY_PIPELINE 628 EMPTY_PIPELINE
629 629
630/* Config1 cache field decoding */ 630/* Config1 cache field decoding */
631#define CACHE_CALC_SPW(s) ( 64 << (s) ) 631#define CACHE_CALC_SPW(s) ( 64 << (s) )
632#define CACHE_CALC_LS(l) ( (l) ? 2 << (l) : 0 ) 632#define CACHE_CALC_LS(l) ( (l) ? 2 << (l) : 0 )
633#define CACHE_CALC_BPW(l,s) ( CACHE_CALC_LS(l) * CACHE_CALC_SPW(s) ) 633#define CACHE_CALC_BPW(l,s) ( CACHE_CALC_LS(l) * CACHE_CALC_SPW(s) )
634#define CACHE_CALC_ASSOC(a) ( (a) + 1 ) 634#define CACHE_CALC_ASSOC(a) ( (a) + 1 )
635 635
636 636
637/**** Move from/to Coprocessor operations ****/ 637/**** Move from/to Coprocessor operations ****/
@@ -641,11 +641,11 @@ SET_POP(); \
641 * The "sll zero,zero,1" notation is compiler backwards compatible. 641 * The "sll zero,zero,1" notation is compiler backwards compatible.
642 */ 642 */
643#define SSNOP sll zero,zero,1 643#define SSNOP sll zero,zero,1
644#define NOPS SSNOP; SSNOP; SSNOP; SSNOP 644#define NOPS SSNOP; SSNOP; SSNOP; SSNOP
645 645
646#define MFLO(dst) \ 646#define MFLO(dst) \
647 mflo dst;\ 647 mflo dst;\
648 NOPS 648 NOPS
649 649
650/* Workaround for bug in early revisions of MIPS 4K family of 650/* Workaround for bug in early revisions of MIPS 4K family of
651 * processors. 651 * processors.
@@ -662,45 +662,45 @@ SET_POP(); \
662 */ 662 */
663 663
664#define MTC0(src, dst) \ 664#define MTC0(src, dst) \
665 nop; \ 665 nop; \
666 mtc0 src,dst;\ 666 mtc0 src,dst;\
667 NOPS 667 NOPS
668 668
669#define DMTC0(src, dst) \ 669#define DMTC0(src, dst) \
670 nop; \ 670 nop; \
671 dmtc0 src,dst;\ 671 dmtc0 src,dst;\
672 NOPS 672 NOPS
673 673
674#define MFC0(dst, src) \ 674#define MFC0(dst, src) \
675 mfc0 dst,src;\ 675 mfc0 dst,src;\
676 NOPS 676 NOPS
677 677
678#define DMFC0(dst, src) \ 678#define DMFC0(dst, src) \
679 dmfc0 dst,src;\ 679 dmfc0 dst,src;\
680 NOPS 680 NOPS
681 681
682#define MFC0_SEL_OPCODE(dst, src, sel)\ 682#define MFC0_SEL_OPCODE(dst, src, sel)\
683 .##word (0x40000000 | ((dst)<<16) | ((src)<<11) | (sel));\ 683 .##word (0x40000000 | ((dst)<<16) | ((src)<<11) | (sel));\
684 NOPS 684 NOPS
685 685
686#define MTC0_SEL_OPCODE(dst, src, sel)\ 686#define MTC0_SEL_OPCODE(dst, src, sel)\
687 .##word (0x40800000 | ((dst)<<16) | ((src)<<11) | (sel));\ 687 .##word (0x40800000 | ((dst)<<16) | ((src)<<11) | (sel));\
688 NOPS 688 NOPS
689 689
690#define LDC1(dst, src, offs)\ 690#define LDC1(dst, src, offs)\
691 .##word (0xd4000000 | ((src)<<21) | ((dst)<<16) | (offs)) 691 .##word (0xd4000000 | ((src)<<21) | ((dst)<<16) | (offs))
692 692
693#define SDC1(src, dst, offs)\ 693#define SDC1(src, dst, offs)\
694 .##word (0xf4000000 | ((dst)<<21) | ((src)<<16) | (offs)) 694 .##word (0xf4000000 | ((dst)<<21) | ((src)<<16) | (offs))
695 695
696 696
697/* Instruction opcode fields */ 697/* Instruction opcode fields */
698#define OPC_SPECIAL 0x0 698#define OPC_SPECIAL 0x0
699#define OPC_REGIM 0x1 699#define OPC_REGIM 0x1
700#define OPC_J 0x2 700#define OPC_J 0x2
701#define OPC_JAL 0x3 701#define OPC_JAL 0x3
702#define OPC_BEQ 0x4 702#define OPC_BEQ 0x4
703#define OPC_BNE 0x5 703#define OPC_BNE 0x5
704#define OPC_BLEZ 0x6 704#define OPC_BLEZ 0x6
705#define OPC_BGTZ 0x7 705#define OPC_BGTZ 0x7
706#define OPC_COP1 0x11 706#define OPC_COP1 0x11
@@ -711,12 +711,12 @@ SET_POP(); \
711#define OPC_BGTZL 0x17 711#define OPC_BGTZL 0x17
712 712
713/* Instruction function fields */ 713/* Instruction function fields */
714#define FUNC_JR 0x8 714#define FUNC_JR 0x8
715#define FUNC_JALR 0x9 715#define FUNC_JALR 0x9
716 716
717/* Instruction rt fields */ 717/* Instruction rt fields */
718#define RT_BLTZ 0x0 718#define RT_BLTZ 0x0
719#define RT_BGEZ 0x1 719#define RT_BGEZ 0x1
720#define RT_BLTZL 0x2 720#define RT_BLTZL 0x2
721#define RT_BGEZL 0x3 721#define RT_BGEZL 0x3
722#define RT_BLTZAL 0x10 722#define RT_BLTZAL 0x10
@@ -725,59 +725,59 @@ SET_POP(); \
725#define RT_BGEZALL 0x13 725#define RT_BGEZALL 0x13
726 726
727/* Instruction rs fields */ 727/* Instruction rs fields */
728#define RS_BC1 0x08 728#define RS_BC1 0x08
729 729
730/* Access macros for instruction fields */ 730/* Access macros for instruction fields */
731#define MIPS_OPCODE( instr) ((instr) >> 26) 731#define MIPS_OPCODE( instr) ((instr) >> 26)
732#define MIPS_FUNCTION(instr) ((instr) & MSK(6)) 732#define MIPS_FUNCTION(instr) ((instr) & MSK(6))
733#define MIPS_RT(instr) (((instr) >> 16) & MSK(5)) 733#define MIPS_RT(instr) (((instr) >> 16) & MSK(5))
734#define MIPS_RS(instr) (((instr) >> 21) & MSK(5)) 734#define MIPS_RS(instr) (((instr) >> 21) & MSK(5))
735#define MIPS_OFFSET(instr) ((instr) & 0xFFFF) 735#define MIPS_OFFSET(instr) ((instr) & 0xFFFF)
736#define MIPS_TARGET(instr) ((instr) & MSK(26)) 736#define MIPS_TARGET(instr) ((instr) & MSK(26))
737 737
738/* Instructions */ 738/* Instructions */
739#define OPCODE_DERET 0x4200001f 739#define OPCODE_DERET 0x4200001f
740#define OPCODE_BREAK 0x0005000d 740#define OPCODE_BREAK 0x0005000d
741#define OPCODE_NOP 0 741#define OPCODE_NOP 0
742#define OPCODE_JUMP(addr) ( (OPC_J << 26) | (((addr) >> 2) & 0x3FFFFFF) ) 742#define OPCODE_JUMP(addr) ( (OPC_J << 26) | (((addr) >> 2) & 0x3FFFFFF) )
743 743
744#define DERET .##word OPCODE_DERET 744#define DERET .##word OPCODE_DERET
745 745
746/* MIPS16e opcodes and instruction field access macros */ 746/* MIPS16e opcodes and instruction field access macros */
747 747
748#define MIPS16E_OPCODE(inst) (((inst) >> 11) & 0x1f) 748#define MIPS16E_OPCODE(inst) (((inst) >> 11) & 0x1f)
749#define MIPS16E_I8_FUNCTION(inst) (((inst) >> 8) & 0x7) 749#define MIPS16E_I8_FUNCTION(inst) (((inst) >> 8) & 0x7)
750#define MIPS16E_X(inst) (((inst) >> 26) & 0x1) 750#define MIPS16E_X(inst) (((inst) >> 26) & 0x1)
751#define MIPS16E_RR_FUNCTION(inst) (((inst) >> 0) & 0x1f) 751#define MIPS16E_RR_FUNCTION(inst) (((inst) >> 0) & 0x1f)
752#define MIPS16E_RY(inst) (((inst) >> 5) & 0x3) 752#define MIPS16E_RY(inst) (((inst) >> 5) & 0x3)
753#define MIPS16E_OPC_EXTEND 0x1e 753#define MIPS16E_OPC_EXTEND 0x1e
754#define MIPS16E_OPC_JAL_X 0x03 754#define MIPS16E_OPC_JAL_X 0x03
755#define MIPS16E_OPC_B 0x02 755#define MIPS16E_OPC_B 0x02
756#define MIPS16E_OPC_BEQZ 0x04 756#define MIPS16E_OPC_BEQZ 0x04
757#define MIPS16E_OPC_BNEZ 0x05 757#define MIPS16E_OPC_BNEZ 0x05
758#define MIPS16E_OPC_I8 0x0c 758#define MIPS16E_OPC_I8 0x0c
759#define MIPS16E_I8_FUNC_BTEQZ 0x00 759#define MIPS16E_I8_FUNC_BTEQZ 0x00
760#define MIPS16E_I8_FUNC_BTNEZ 0x01 760#define MIPS16E_I8_FUNC_BTNEZ 0x01
761#define MIPS16E_X_JALX 0x01 761#define MIPS16E_X_JALX 0x01
762#define MIPS16E_OPC_RR 0x1d 762#define MIPS16E_OPC_RR 0x1d
763#define MIPS16E_RR_FUNC_JALRC 0x00 763#define MIPS16E_RR_FUNC_JALRC 0x00
764#define MIPS16E_RR_RY_JRRX 0x00 764#define MIPS16E_RR_RY_JRRX 0x00
765#define MIPS16E_RR_RY_JRRA 0x01 765#define MIPS16E_RR_RY_JRRA 0x01
766#define MIPS16E_RR_RY_JALR 0x02 766#define MIPS16E_RR_RY_JALR 0x02
767#define MIPS16E_RR_RY_JRCRX 0x04 767#define MIPS16E_RR_RY_JRCRX 0x04
768#define MIPS16E_RR_RY_JRCRA 0x05 768#define MIPS16E_RR_RY_JRCRA 0x05
769#define MIPS16E_RR_RY_JALRC 0x06 769#define MIPS16E_RR_RY_JALRC 0x06
770 770
771#define MIPS16E_OPCODE_BREAK 0xE805 771#define MIPS16E_OPCODE_BREAK 0xE805
772#define MIPS16E_OPCODE_NOP 0x6500 772#define MIPS16E_OPCODE_NOP 0x6500
773 773
774/* MIPS reset vector */ 774/* MIPS reset vector */
775#define MIPS_RESET_VECTOR 0x1fc00000 775#define MIPS_RESET_VECTOR 0x1fc00000
776 776
777/* Clock periods per count register increment */ 777/* Clock periods per count register increment */
778#define MIPS4K_COUNT_CLK_PER_CYCLE 2 778#define MIPS4K_COUNT_CLK_PER_CYCLE 2
779#define MIPS5K_COUNT_CLK_PER_CYCLE 2 779#define MIPS5K_COUNT_CLK_PER_CYCLE 2
780#define MIPS20Kc_COUNT_CLK_PER_CYCLE 1 780#define MIPS20Kc_COUNT_CLK_PER_CYCLE 1
781 781
782 782
783/**** MIPS 4K/5K families specific fields of CONFIG register ****/ 783/**** MIPS 4K/5K families specific fields of CONFIG register ****/
diff --git a/firmware/export/mipsregs.h b/firmware/export/mipsregs.h
index 0ae9bce4d7..197f8eb992 100644
--- a/firmware/export/mipsregs.h
+++ b/firmware/export/mipsregs.h
@@ -74,7 +74,7 @@
74/* 74/*
75 * TX39 Series 75 * TX39 Series
76 */ 76 */
77#define CP0_TX39_CACHE $7 77#define CP0_TX39_CACHE $7
78 78
79/* 79/*
80 * Coprocessor 1 (FPU) register names 80 * Coprocessor 1 (FPU) register names
@@ -141,38 +141,38 @@
141 141
142/* Why doesn't stupidity hurt ... */ 142/* Why doesn't stupidity hurt ... */
143 143
144#define PM_1K 0x00000000 144#define PM_1K 0x00000000
145#define PM_4K 0x00001800 145#define PM_4K 0x00001800
146#define PM_16K 0x00007800 146#define PM_16K 0x00007800
147#define PM_64K 0x0001f800 147#define PM_64K 0x0001f800
148#define PM_256K 0x0007f800 148#define PM_256K 0x0007f800
149 149
150#else 150#else
151 151
152#define PM_4K 0x00000000 152#define PM_4K 0x00000000
153#define PM_16K 0x00006000 153#define PM_16K 0x00006000
154#define PM_64K 0x0001e000 154#define PM_64K 0x0001e000
155#define PM_256K 0x0007e000 155#define PM_256K 0x0007e000
156#define PM_1M 0x001fe000 156#define PM_1M 0x001fe000
157#define PM_4M 0x007fe000 157#define PM_4M 0x007fe000
158#define PM_16M 0x01ffe000 158#define PM_16M 0x01ffe000
159#define PM_64M 0x07ffe000 159#define PM_64M 0x07ffe000
160#define PM_256M 0x1fffe000 160#define PM_256M 0x1fffe000
161 161
162#endif 162#endif
163 163
164/* 164/*
165 * Values used for computation of new tlb entries 165 * Values used for computation of new tlb entries
166 */ 166 */
167#define PL_4K 12 167#define PL_4K 12
168#define PL_16K 14 168#define PL_16K 14
169#define PL_64K 16 169#define PL_64K 16
170#define PL_256K 18 170#define PL_256K 18
171#define PL_1M 20 171#define PL_1M 20
172#define PL_4M 22 172#define PL_4M 22
173#define PL_16M 24 173#define PL_16M 24
174#define PL_64M 26 174#define PL_64M 26
175#define PL_256M 28 175#define PL_256M 28
176 176
177/* 177/*
178 * R4x00 interrupt enable / cause bits 178 * R4x00 interrupt enable / cause bits
@@ -201,233 +201,233 @@
201/* 201/*
202 * Bitfields in the R4xx0 cp0 status register 202 * Bitfields in the R4xx0 cp0 status register
203 */ 203 */
204#define ST0_IE 0x00000001 204#define ST0_IE 0x00000001
205#define ST0_EXL 0x00000002 205#define ST0_EXL 0x00000002
206#define ST0_ERL 0x00000004 206#define ST0_ERL 0x00000004
207#define ST0_KSU 0x00000018 207#define ST0_KSU 0x00000018
208# define KSU_USER 0x00000010 208# define KSU_USER 0x00000010
209# define KSU_SUPERVISOR 0x00000008 209# define KSU_SUPERVISOR 0x00000008
210# define KSU_KERNEL 0x00000000 210# define KSU_KERNEL 0x00000000
211#define ST0_UX 0x00000020 211#define ST0_UX 0x00000020
212#define ST0_SX 0x00000040 212#define ST0_SX 0x00000040
213#define ST0_KX 0x00000080 213#define ST0_KX 0x00000080
214#define ST0_DE 0x00010000 214#define ST0_DE 0x00010000
215#define ST0_CE 0x00020000 215#define ST0_CE 0x00020000
216 216
217/* 217/*
218 * Bitfields in the R[23]000 cp0 status register. 218 * Bitfields in the R[23]000 cp0 status register.
219 */ 219 */
220#define ST0_IEC 0x00000001 220#define ST0_IEC 0x00000001
221#define ST0_KUC 0x00000002 221#define ST0_KUC 0x00000002
222#define ST0_IEP 0x00000004 222#define ST0_IEP 0x00000004
223#define ST0_KUP 0x00000008 223#define ST0_KUP 0x00000008
224#define ST0_IEO 0x00000010 224#define ST0_IEO 0x00000010
225#define ST0_KUO 0x00000020 225#define ST0_KUO 0x00000020
226/* bits 6 & 7 are reserved on R[23]000 */ 226/* bits 6 & 7 are reserved on R[23]000 */
227#define ST0_ISC 0x00010000 227#define ST0_ISC 0x00010000
228#define ST0_SWC 0x00020000 228#define ST0_SWC 0x00020000
229#define ST0_CM 0x00080000 229#define ST0_CM 0x00080000
230 230
231/* 231/*
232 * Bits specific to the R4640/R4650 232 * Bits specific to the R4640/R4650
233 */ 233 */
234#define ST0_UM (_ULCAST_(1) << 4) 234#define ST0_UM (_ULCAST_(1) << 4)
235#define ST0_IL (_ULCAST_(1) << 23) 235#define ST0_IL (_ULCAST_(1) << 23)
236#define ST0_DL (_ULCAST_(1) << 24) 236#define ST0_DL (_ULCAST_(1) << 24)
237 237
238/* 238/*
239 * Bitfields in the TX39 family CP0 Configuration Register 3 239 * Bitfields in the TX39 family CP0 Configuration Register 3
240 */ 240 */
241#define TX39_CONF_ICS_SHIFT 19 241#define TX39_CONF_ICS_SHIFT 19
242#define TX39_CONF_ICS_MASK 0x00380000 242#define TX39_CONF_ICS_MASK 0x00380000
243#define TX39_CONF_ICS_1KB 0x00000000 243#define TX39_CONF_ICS_1KB 0x00000000
244#define TX39_CONF_ICS_2KB 0x00080000 244#define TX39_CONF_ICS_2KB 0x00080000
245#define TX39_CONF_ICS_4KB 0x00100000 245#define TX39_CONF_ICS_4KB 0x00100000
246#define TX39_CONF_ICS_8KB 0x00180000 246#define TX39_CONF_ICS_8KB 0x00180000
247#define TX39_CONF_ICS_16KB 0x00200000 247#define TX39_CONF_ICS_16KB 0x00200000
248 248
249#define TX39_CONF_DCS_SHIFT 16 249#define TX39_CONF_DCS_SHIFT 16
250#define TX39_CONF_DCS_MASK 0x00070000 250#define TX39_CONF_DCS_MASK 0x00070000
251#define TX39_CONF_DCS_1KB 0x00000000 251#define TX39_CONF_DCS_1KB 0x00000000
252#define TX39_CONF_DCS_2KB 0x00010000 252#define TX39_CONF_DCS_2KB 0x00010000
253#define TX39_CONF_DCS_4KB 0x00020000 253#define TX39_CONF_DCS_4KB 0x00020000
254#define TX39_CONF_DCS_8KB 0x00030000 254#define TX39_CONF_DCS_8KB 0x00030000
255#define TX39_CONF_DCS_16KB 0x00040000 255#define TX39_CONF_DCS_16KB 0x00040000
256 256
257#define TX39_CONF_CWFON 0x00004000 257#define TX39_CONF_CWFON 0x00004000
258#define TX39_CONF_WBON 0x00002000 258#define TX39_CONF_WBON 0x00002000
259#define TX39_CONF_RF_SHIFT 10 259#define TX39_CONF_RF_SHIFT 10
260#define TX39_CONF_RF_MASK 0x00000c00 260#define TX39_CONF_RF_MASK 0x00000c00
261#define TX39_CONF_DOZE 0x00000200 261#define TX39_CONF_DOZE 0x00000200
262#define TX39_CONF_HALT 0x00000100 262#define TX39_CONF_HALT 0x00000100
263#define TX39_CONF_LOCK 0x00000080 263#define TX39_CONF_LOCK 0x00000080
264#define TX39_CONF_ICE 0x00000020 264#define TX39_CONF_ICE 0x00000020
265#define TX39_CONF_DCE 0x00000010 265#define TX39_CONF_DCE 0x00000010
266#define TX39_CONF_IRSIZE_SHIFT 2 266#define TX39_CONF_IRSIZE_SHIFT 2
267#define TX39_CONF_IRSIZE_MASK 0x0000000c 267#define TX39_CONF_IRSIZE_MASK 0x0000000c
268#define TX39_CONF_DRSIZE_SHIFT 0 268#define TX39_CONF_DRSIZE_SHIFT 0
269#define TX39_CONF_DRSIZE_MASK 0x00000003 269#define TX39_CONF_DRSIZE_MASK 0x00000003
270 270
271/* 271/*
272 * Status register bits available in all MIPS CPUs. 272 * Status register bits available in all MIPS CPUs.
273 */ 273 */
274#define ST0_IM 0x0000ff00 274#define ST0_IM 0x0000ff00
275#define STATUSB_IP0 8 275#define STATUSB_IP0 8
276#define STATUSF_IP0 (_ULCAST_(1) << 8) 276#define STATUSF_IP0 (_ULCAST_(1) << 8)
277#define STATUSB_IP1 9 277#define STATUSB_IP1 9
278#define STATUSF_IP1 (_ULCAST_(1) << 9) 278#define STATUSF_IP1 (_ULCAST_(1) << 9)
279#define STATUSB_IP2 10 279#define STATUSB_IP2 10
280#define STATUSF_IP2 (_ULCAST_(1) << 10) 280#define STATUSF_IP2 (_ULCAST_(1) << 10)
281#define STATUSB_IP3 11 281#define STATUSB_IP3 11
282#define STATUSF_IP3 (_ULCAST_(1) << 11) 282#define STATUSF_IP3 (_ULCAST_(1) << 11)
283#define STATUSB_IP4 12 283#define STATUSB_IP4 12
284#define STATUSF_IP4 (_ULCAST_(1) << 12) 284#define STATUSF_IP4 (_ULCAST_(1) << 12)
285#define STATUSB_IP5 13 285#define STATUSB_IP5 13
286#define STATUSF_IP5 (_ULCAST_(1) << 13) 286#define STATUSF_IP5 (_ULCAST_(1) << 13)
287#define STATUSB_IP6 14 287#define STATUSB_IP6 14
288#define STATUSF_IP6 (_ULCAST_(1) << 14) 288#define STATUSF_IP6 (_ULCAST_(1) << 14)
289#define STATUSB_IP7 15 289#define STATUSB_IP7 15
290#define STATUSF_IP7 (_ULCAST_(1) << 15) 290#define STATUSF_IP7 (_ULCAST_(1) << 15)
291#define STATUSB_IP8 0 291#define STATUSB_IP8 0
292#define STATUSF_IP8 (_ULCAST_(1) << 0) 292#define STATUSF_IP8 (_ULCAST_(1) << 0)
293#define STATUSB_IP9 1 293#define STATUSB_IP9 1
294#define STATUSF_IP9 (_ULCAST_(1) << 1) 294#define STATUSF_IP9 (_ULCAST_(1) << 1)
295#define STATUSB_IP10 2 295#define STATUSB_IP10 2
296#define STATUSF_IP10 (_ULCAST_(1) << 2) 296#define STATUSF_IP10 (_ULCAST_(1) << 2)
297#define STATUSB_IP11 3 297#define STATUSB_IP11 3
298#define STATUSF_IP11 (_ULCAST_(1) << 3) 298#define STATUSF_IP11 (_ULCAST_(1) << 3)
299#define STATUSB_IP12 4 299#define STATUSB_IP12 4
300#define STATUSF_IP12 (_ULCAST_(1) << 4) 300#define STATUSF_IP12 (_ULCAST_(1) << 4)
301#define STATUSB_IP13 5 301#define STATUSB_IP13 5
302#define STATUSF_IP13 (_ULCAST_(1) << 5) 302#define STATUSF_IP13 (_ULCAST_(1) << 5)
303#define STATUSB_IP14 6 303#define STATUSB_IP14 6
304#define STATUSF_IP14 (_ULCAST_(1) << 6) 304#define STATUSF_IP14 (_ULCAST_(1) << 6)
305#define STATUSB_IP15 7 305#define STATUSB_IP15 7
306#define STATUSF_IP15 (_ULCAST_(1) << 7) 306#define STATUSF_IP15 (_ULCAST_(1) << 7)
307#define ST0_CH 0x00040000 307#define ST0_CH 0x00040000
308#define ST0_SR 0x00100000 308#define ST0_SR 0x00100000
309#define ST0_TS 0x00200000 309#define ST0_TS 0x00200000
310#define ST0_BEV 0x00400000 310#define ST0_BEV 0x00400000
311#define ST0_RE 0x02000000 311#define ST0_RE 0x02000000
312#define ST0_FR 0x04000000 312#define ST0_FR 0x04000000
313#define ST0_CU 0xf0000000 313#define ST0_CU 0xf0000000
314#define ST0_CU0 0x10000000 314#define ST0_CU0 0x10000000
315#define ST0_CU1 0x20000000 315#define ST0_CU1 0x20000000
316#define ST0_CU2 0x40000000 316#define ST0_CU2 0x40000000
317#define ST0_CU3 0x80000000 317#define ST0_CU3 0x80000000
318#define ST0_XX 0x80000000 /* MIPS IV naming */ 318#define ST0_XX 0x80000000 /* MIPS IV naming */
319 319
320/* 320/*
321 * Bitfields and bit numbers in the coprocessor 0 cause register. 321 * Bitfields and bit numbers in the coprocessor 0 cause register.
322 * 322 *
323 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation. 323 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
324 */ 324 */
325#define CAUSEB_EXCCODE 2 325#define CAUSEB_EXCCODE 2
326#define CAUSEF_EXCCODE (_ULCAST_(31) << 2) 326#define CAUSEF_EXCCODE (_ULCAST_(31) << 2)
327#define CAUSEB_IP 8 327#define CAUSEB_IP 8
328#define CAUSEF_IP (_ULCAST_(255) << 8) 328#define CAUSEF_IP (_ULCAST_(255) << 8)
329#define CAUSEB_IP0 8 329#define CAUSEB_IP0 8
330#define CAUSEF_IP0 (_ULCAST_(1) << 8) 330#define CAUSEF_IP0 (_ULCAST_(1) << 8)
331#define CAUSEB_IP1 9 331#define CAUSEB_IP1 9
332#define CAUSEF_IP1 (_ULCAST_(1) << 9) 332#define CAUSEF_IP1 (_ULCAST_(1) << 9)
333#define CAUSEB_IP2 10 333#define CAUSEB_IP2 10
334#define CAUSEF_IP2 (_ULCAST_(1) << 10) 334#define CAUSEF_IP2 (_ULCAST_(1) << 10)
335#define CAUSEB_IP3 11 335#define CAUSEB_IP3 11
336#define CAUSEF_IP3 (_ULCAST_(1) << 11) 336#define CAUSEF_IP3 (_ULCAST_(1) << 11)
337#define CAUSEB_IP4 12 337#define CAUSEB_IP4 12
338#define CAUSEF_IP4 (_ULCAST_(1) << 12) 338#define CAUSEF_IP4 (_ULCAST_(1) << 12)
339#define CAUSEB_IP5 13 339#define CAUSEB_IP5 13
340#define CAUSEF_IP5 (_ULCAST_(1) << 13) 340#define CAUSEF_IP5 (_ULCAST_(1) << 13)
341#define CAUSEB_IP6 14 341#define CAUSEB_IP6 14
342#define CAUSEF_IP6 (_ULCAST_(1) << 14) 342#define CAUSEF_IP6 (_ULCAST_(1) << 14)
343#define CAUSEB_IP7 15 343#define CAUSEB_IP7 15
344#define CAUSEF_IP7 (_ULCAST_(1) << 15) 344#define CAUSEF_IP7 (_ULCAST_(1) << 15)
345#define CAUSEB_IV 23 345#define CAUSEB_IV 23
346#define CAUSEF_IV (_ULCAST_(1) << 23) 346#define CAUSEF_IV (_ULCAST_(1) << 23)
347#define CAUSEB_CE 28 347#define CAUSEB_CE 28
348#define CAUSEF_CE (_ULCAST_(3) << 28) 348#define CAUSEF_CE (_ULCAST_(3) << 28)
349#define CAUSEB_BD 31 349#define CAUSEB_BD 31
350#define CAUSEF_BD (_ULCAST_(1) << 31) 350#define CAUSEF_BD (_ULCAST_(1) << 31)
351 351
352/* 352/*
353 * Bits in the coprocessor 0 config register. 353 * Bits in the coprocessor 0 config register.
354 */ 354 */
355/* Generic bits. */ 355/* Generic bits. */
356#define CONF_CM_CACHABLE_NO_WA 0 356#define CONF_CM_CACHABLE_NO_WA 0
357#define CONF_CM_CACHABLE_WA 1 357#define CONF_CM_CACHABLE_WA 1
358#define CONF_CM_UNCACHED 2 358#define CONF_CM_UNCACHED 2
359#define CONF_CM_CACHABLE_NONCOHERENT 3 359#define CONF_CM_CACHABLE_NONCOHERENT 3
360#define CONF_CM_CACHABLE_CE 4 360#define CONF_CM_CACHABLE_CE 4
361#define CONF_CM_CACHABLE_COW 5 361#define CONF_CM_CACHABLE_COW 5
362#define CONF_CM_CACHABLE_CUW 6 362#define CONF_CM_CACHABLE_CUW 6
363#define CONF_CM_CACHABLE_ACCELERATED 7 363#define CONF_CM_CACHABLE_ACCELERATED 7
364#define CONF_CM_CMASK 7 364#define CONF_CM_CMASK 7
365#define CONF_BE (_ULCAST_(1) << 15) 365#define CONF_BE (_ULCAST_(1) << 15)
366 366
367/* Bits common to various processors. */ 367/* Bits common to various processors. */
368#define CONF_CU (_ULCAST_(1) << 3) 368#define CONF_CU (_ULCAST_(1) << 3)
369#define CONF_DB (_ULCAST_(1) << 4) 369#define CONF_DB (_ULCAST_(1) << 4)
370#define CONF_IB (_ULCAST_(1) << 5) 370#define CONF_IB (_ULCAST_(1) << 5)
371#define CONF_DC (_ULCAST_(7) << 6) 371#define CONF_DC (_ULCAST_(7) << 6)
372#define CONF_IC (_ULCAST_(7) << 9) 372#define CONF_IC (_ULCAST_(7) << 9)
373#define CONF_EB (_ULCAST_(1) << 13) 373#define CONF_EB (_ULCAST_(1) << 13)
374#define CONF_EM (_ULCAST_(1) << 14) 374#define CONF_EM (_ULCAST_(1) << 14)
375#define CONF_SM (_ULCAST_(1) << 16) 375#define CONF_SM (_ULCAST_(1) << 16)
376#define CONF_SC (_ULCAST_(1) << 17) 376#define CONF_SC (_ULCAST_(1) << 17)
377#define CONF_EW (_ULCAST_(3) << 18) 377#define CONF_EW (_ULCAST_(3) << 18)
378#define CONF_EP (_ULCAST_(15)<< 24) 378#define CONF_EP (_ULCAST_(15)<< 24)
379#define CONF_EC (_ULCAST_(7) << 28) 379#define CONF_EC (_ULCAST_(7) << 28)
380#define CONF_CM (_ULCAST_(1) << 31) 380#define CONF_CM (_ULCAST_(1) << 31)
381 381
382/* Bits specific to the R4xx0. */ 382/* Bits specific to the R4xx0. */
383#define R4K_CONF_SW (_ULCAST_(1) << 20) 383#define R4K_CONF_SW (_ULCAST_(1) << 20)
384#define R4K_CONF_SS (_ULCAST_(1) << 21) 384#define R4K_CONF_SS (_ULCAST_(1) << 21)
385#define R4K_CONF_SB (_ULCAST_(3) << 22) 385#define R4K_CONF_SB (_ULCAST_(3) << 22)
386 386
387/* Bits specific to the R5000. */ 387/* Bits specific to the R5000. */
388#define R5K_CONF_SE (_ULCAST_(1) << 12) 388#define R5K_CONF_SE (_ULCAST_(1) << 12)
389#define R5K_CONF_SS (_ULCAST_(3) << 20) 389#define R5K_CONF_SS (_ULCAST_(3) << 20)
390 390
391/* Bits specific to the R10000. */ 391/* Bits specific to the R10000. */
392#define R10K_CONF_DN (_ULCAST_(3) << 3) 392#define R10K_CONF_DN (_ULCAST_(3) << 3)
393#define R10K_CONF_CT (_ULCAST_(1) << 5) 393#define R10K_CONF_CT (_ULCAST_(1) << 5)
394#define R10K_CONF_PE (_ULCAST_(1) << 6) 394#define R10K_CONF_PE (_ULCAST_(1) << 6)
395#define R10K_CONF_PM (_ULCAST_(3) << 7) 395#define R10K_CONF_PM (_ULCAST_(3) << 7)
396#define R10K_CONF_EC (_ULCAST_(15)<< 9) 396#define R10K_CONF_EC (_ULCAST_(15)<< 9)
397#define R10K_CONF_SB (_ULCAST_(1) << 13) 397#define R10K_CONF_SB (_ULCAST_(1) << 13)
398#define R10K_CONF_SK (_ULCAST_(1) << 14) 398#define R10K_CONF_SK (_ULCAST_(1) << 14)
399#define R10K_CONF_SS (_ULCAST_(7) << 16) 399#define R10K_CONF_SS (_ULCAST_(7) << 16)
400#define R10K_CONF_SC (_ULCAST_(7) << 19) 400#define R10K_CONF_SC (_ULCAST_(7) << 19)
401#define R10K_CONF_DC (_ULCAST_(7) << 26) 401#define R10K_CONF_DC (_ULCAST_(7) << 26)
402#define R10K_CONF_IC (_ULCAST_(7) << 29) 402#define R10K_CONF_IC (_ULCAST_(7) << 29)
403 403
404/* Bits specific to the VR41xx. */ 404/* Bits specific to the VR41xx. */
405#define VR41_CONF_CS (_ULCAST_(1) << 12) 405#define VR41_CONF_CS (_ULCAST_(1) << 12)
406#define VR41_CONF_M16 (_ULCAST_(1) << 20) 406#define VR41_CONF_M16 (_ULCAST_(1) << 20)
407#define VR41_CONF_AD (_ULCAST_(1) << 23) 407#define VR41_CONF_AD (_ULCAST_(1) << 23)
408 408
409/* Bits specific to the R30xx. */ 409/* Bits specific to the R30xx. */
410#define R30XX_CONF_FDM (_ULCAST_(1) << 19) 410#define R30XX_CONF_FDM (_ULCAST_(1) << 19)
411#define R30XX_CONF_REV (_ULCAST_(1) << 22) 411#define R30XX_CONF_REV (_ULCAST_(1) << 22)
412#define R30XX_CONF_AC (_ULCAST_(1) << 23) 412#define R30XX_CONF_AC (_ULCAST_(1) << 23)
413#define R30XX_CONF_RF (_ULCAST_(1) << 24) 413#define R30XX_CONF_RF (_ULCAST_(1) << 24)
414#define R30XX_CONF_HALT (_ULCAST_(1) << 25) 414#define R30XX_CONF_HALT (_ULCAST_(1) << 25)
415#define R30XX_CONF_FPINT (_ULCAST_(7) << 26) 415#define R30XX_CONF_FPINT (_ULCAST_(7) << 26)
416#define R30XX_CONF_DBR (_ULCAST_(1) << 29) 416#define R30XX_CONF_DBR (_ULCAST_(1) << 29)
417#define R30XX_CONF_SB (_ULCAST_(1) << 30) 417#define R30XX_CONF_SB (_ULCAST_(1) << 30)
418#define R30XX_CONF_LOCK (_ULCAST_(1) << 31) 418#define R30XX_CONF_LOCK (_ULCAST_(1) << 31)
419 419
420/* Bits specific to the TX49. */ 420/* Bits specific to the TX49. */
421#define TX49_CONF_DC (_ULCAST_(1) << 16) 421#define TX49_CONF_DC (_ULCAST_(1) << 16)
422#define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */ 422#define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */
423#define TX49_CONF_HALT (_ULCAST_(1) << 18) 423#define TX49_CONF_HALT (_ULCAST_(1) << 18)
424#define TX49_CONF_CWFON (_ULCAST_(1) << 27) 424#define TX49_CONF_CWFON (_ULCAST_(1) << 27)
425 425
426/* Bits specific to the MIPS32/64 PRA. */ 426/* Bits specific to the MIPS32/64 PRA. */
427#define MIPS_CONF_MT (_ULCAST_(7) << 7) 427#define MIPS_CONF_MT (_ULCAST_(7) << 7)
428#define MIPS_CONF_AR (_ULCAST_(7) << 10) 428#define MIPS_CONF_AR (_ULCAST_(7) << 10)
429#define MIPS_CONF_AT (_ULCAST_(3) << 13) 429#define MIPS_CONF_AT (_ULCAST_(3) << 13)
430#define MIPS_CONF_M (_ULCAST_(1) << 31) 430#define MIPS_CONF_M (_ULCAST_(1) << 31)
431 431
432/* 432/*
433 * R10000 performance counter definitions. 433 * R10000 performance counter definitions.
@@ -440,50 +440,50 @@
440/* 440/*
441 * Events counted by counter #0 441 * Events counted by counter #0
442 */ 442 */
443#define CE0_CYCLES 0 443#define CE0_CYCLES 0
444#define CE0_INSN_ISSUED 1 444#define CE0_INSN_ISSUED 1
445#define CE0_LPSC_ISSUED 2 445#define CE0_LPSC_ISSUED 2
446#define CE0_S_ISSUED 3 446#define CE0_S_ISSUED 3
447#define CE0_SC_ISSUED 4 447#define CE0_SC_ISSUED 4
448#define CE0_SC_FAILED 5 448#define CE0_SC_FAILED 5
449#define CE0_BRANCH_DECODED 6 449#define CE0_BRANCH_DECODED 6
450#define CE0_QW_WB_SECONDARY 7 450#define CE0_QW_WB_SECONDARY 7
451#define CE0_CORRECTED_ECC_ERRORS 8 451#define CE0_CORRECTED_ECC_ERRORS 8
452#define CE0_ICACHE_MISSES 9 452#define CE0_ICACHE_MISSES 9
453#define CE0_SCACHE_I_MISSES 10 453#define CE0_SCACHE_I_MISSES 10
454#define CE0_SCACHE_I_WAY_MISSPREDICTED 11 454#define CE0_SCACHE_I_WAY_MISSPREDICTED 11
455#define CE0_EXT_INTERVENTIONS_REQ 12 455#define CE0_EXT_INTERVENTIONS_REQ 12
456#define CE0_EXT_INVALIDATE_REQ 13 456#define CE0_EXT_INVALIDATE_REQ 13
457#define CE0_VIRTUAL_COHERENCY_COND 14 457#define CE0_VIRTUAL_COHERENCY_COND 14
458#define CE0_INSN_GRADUATED 15 458#define CE0_INSN_GRADUATED 15
459 459
460/* 460/*
461 * Events counted by counter #1 461 * Events counted by counter #1
462 */ 462 */
463#define CE1_CYCLES 0 463#define CE1_CYCLES 0
464#define CE1_INSN_GRADUATED 1 464#define CE1_INSN_GRADUATED 1
465#define CE1_LPSC_GRADUATED 2 465#define CE1_LPSC_GRADUATED 2
466#define CE1_S_GRADUATED 3 466#define CE1_S_GRADUATED 3
467#define CE1_SC_GRADUATED 4 467#define CE1_SC_GRADUATED 4
468#define CE1_FP_INSN_GRADUATED 5 468#define CE1_FP_INSN_GRADUATED 5
469#define CE1_QW_WB_PRIMARY 6 469#define CE1_QW_WB_PRIMARY 6
470#define CE1_TLB_REFILL 7 470#define CE1_TLB_REFILL 7
471#define CE1_BRANCH_MISSPREDICTED 8 471#define CE1_BRANCH_MISSPREDICTED 8
472#define CE1_DCACHE_MISS 9 472#define CE1_DCACHE_MISS 9
473#define CE1_SCACHE_D_MISSES 10 473#define CE1_SCACHE_D_MISSES 10
474#define CE1_SCACHE_D_WAY_MISSPREDICTED 11 474#define CE1_SCACHE_D_WAY_MISSPREDICTED 11
475#define CE1_EXT_INTERVENTION_HITS 12 475#define CE1_EXT_INTERVENTION_HITS 12
476#define CE1_EXT_INVALIDATE_REQ 13 476#define CE1_EXT_INVALIDATE_REQ 13
477#define CE1_SP_HINT_TO_CEXCL_SC_BLOCKS 14 477#define CE1_SP_HINT_TO_CEXCL_SC_BLOCKS 14
478#define CE1_SP_HINT_TO_SHARED_SC_BLOCKS 15 478#define CE1_SP_HINT_TO_SHARED_SC_BLOCKS 15
479 479
480/* 480/*
481 * These flags define in which priviledge mode the counters count events 481 * These flags define in which priviledge mode the counters count events
482 */ 482 */
483#define CEB_USER 8 /* Count events in user mode, EXL = ERL = 0 */ 483#define CEB_USER 8 /* Count events in user mode, EXL = ERL = 0 */
484#define CEB_SUPERVISOR 4 /* Count events in supvervisor mode EXL = ERL = 0 */ 484#define CEB_SUPERVISOR 4 /* Count events in supvervisor mode EXL = ERL = 0 */
485#define CEB_KERNEL 2 /* Count events in kernel mode EXL = ERL = 0 */ 485#define CEB_KERNEL 2 /* Count events in kernel mode EXL = ERL = 0 */
486#define CEB_EXL 1 /* Count events with EXL = 1, ERL = 0 */ 486#define CEB_EXL 1 /* Count events with EXL = 1, ERL = 0 */
487 487
488#ifndef __ASSEMBLY__ 488#ifndef __ASSEMBLY__
489 489
@@ -521,274 +521,274 @@
521 * Macros to access the system control coprocessor 521 * Macros to access the system control coprocessor
522 */ 522 */
523 523
524#define __read_32bit_c0_register(source, sel) \ 524#define __read_32bit_c0_register(source, sel) \
525({ unsigned int __res; \ 525({ unsigned int __res; \
526 if (sel == 0) \ 526 if (sel == 0) \
527 __asm__ __volatile__( \ 527 __asm__ __volatile__( \
528 "mfc0\t%0, " #source "\n\t" \ 528 "mfc0\t%0, " #source "\n\t" \
529 : "=r" (__res)); \ 529 : "=r" (__res)); \
530 else \ 530 else \
531 __asm__ __volatile__( \ 531 __asm__ __volatile__( \
532 ".set\tmips32\n\t" \ 532 ".set\tmips32\n\t" \
533 "mfc0\t%0, " #source ", " #sel "\n\t" \ 533 "mfc0\t%0, " #source ", " #sel "\n\t" \
534 ".set\tmips0\n\t" \ 534 ".set\tmips0\n\t" \
535 : "=r" (__res)); \ 535 : "=r" (__res)); \
536 __res; \ 536 __res; \
537}) 537})
538 538
539#define __read_64bit_c0_register(source, sel) \ 539#define __read_64bit_c0_register(source, sel) \
540({ unsigned long __res; \ 540({ unsigned long __res; \
541 if (sel == 0) \ 541 if (sel == 0) \
542 __asm__ __volatile__( \ 542 __asm__ __volatile__( \
543 ".set\tmips3\n\t" \ 543 ".set\tmips3\n\t" \
544 "dmfc0\t%0, " #source "\n\t" \ 544 "dmfc0\t%0, " #source "\n\t" \
545 ".set\tmips0" \ 545 ".set\tmips0" \
546 : "=r" (__res)); \ 546 : "=r" (__res)); \
547 else \ 547 else \
548 __asm__ __volatile__( \ 548 __asm__ __volatile__( \
549 ".set\tmips64\n\t" \ 549 ".set\tmips64\n\t" \
550 "dmfc0\t%0, " #source ", " #sel "\n\t" \ 550 "dmfc0\t%0, " #source ", " #sel "\n\t" \
551 ".set\tmips0" \ 551 ".set\tmips0" \
552 : "=r" (__res)); \ 552 : "=r" (__res)); \
553 __res; \ 553 __res; \
554}) 554})
555 555
556#define __write_32bit_c0_register(register, sel, value) \ 556#define __write_32bit_c0_register(register, sel, value) \
557do { \ 557do { \
558 if (sel == 0) \ 558 if (sel == 0) \
559 __asm__ __volatile__( \ 559 __asm__ __volatile__( \
560 "mtc0\t%z0, " #register "\n\t" \ 560 "mtc0\t%z0, " #register "\n\t" \
561 : : "Jr" (value)); \ 561 : : "Jr" (value)); \
562 else \ 562 else \
563 __asm__ __volatile__( \ 563 __asm__ __volatile__( \
564 ".set\tmips32\n\t" \ 564 ".set\tmips32\n\t" \
565 "mtc0\t%z0, " #register ", " #sel "\n\t" \ 565 "mtc0\t%z0, " #register ", " #sel "\n\t" \
566 ".set\tmips0" \ 566 ".set\tmips0" \
567 : : "Jr" (value)); \ 567 : : "Jr" (value)); \
568} while (0) 568} while (0)
569 569
570#define __write_64bit_c0_register(register, sel, value) \ 570#define __write_64bit_c0_register(register, sel, value) \
571do { \ 571do { \
572 if (sel == 0) \ 572 if (sel == 0) \
573 __asm__ __volatile__( \ 573 __asm__ __volatile__( \
574 ".set\tmips3\n\t" \ 574 ".set\tmips3\n\t" \
575 "dmtc0\t%z0, " #register "\n\t" \ 575 "dmtc0\t%z0, " #register "\n\t" \
576 ".set\tmips0" \ 576 ".set\tmips0" \
577 : : "Jr" (value)); \ 577 : : "Jr" (value)); \
578 else \ 578 else \
579 __asm__ __volatile__( \ 579 __asm__ __volatile__( \
580 ".set\tmips64\n\t" \ 580 ".set\tmips64\n\t" \
581 "dmtc0\t%z0, " #register ", " #sel "\n\t" \ 581 "dmtc0\t%z0, " #register ", " #sel "\n\t" \
582 ".set\tmips0" \ 582 ".set\tmips0" \
583 : : "Jr" (value)); \ 583 : : "Jr" (value)); \
584} while (0) 584} while (0)
585 585
586#define __read_ulong_c0_register(reg, sel) \ 586#define __read_ulong_c0_register(reg, sel) \
587 ((sizeof(unsigned long) == 4) ? \ 587 ((sizeof(unsigned long) == 4) ? \
588 __read_32bit_c0_register(reg, sel) : \ 588 __read_32bit_c0_register(reg, sel) : \
589 __read_64bit_c0_register(reg, sel)) 589 __read_64bit_c0_register(reg, sel))
590 590
591#define __write_ulong_c0_register(reg, sel, val) \ 591#define __write_ulong_c0_register(reg, sel, val) \
592do { \ 592do { \
593 if (sizeof(unsigned long) == 4) \ 593 if (sizeof(unsigned long) == 4) \
594 __write_32bit_c0_register(reg, sel, val); \ 594 __write_32bit_c0_register(reg, sel, val); \
595 else \ 595 else \
596 __write_64bit_c0_register(reg, sel, val); \ 596 __write_64bit_c0_register(reg, sel, val); \
597} while (0) 597} while (0)
598 598
599/* 599/*
600 * These versions are only needed for systems with more than 38 bits of 600 * These versions are only needed for systems with more than 38 bits of
601 * physical address space running the 32-bit kernel. That's none atm :-) 601 * physical address space running the 32-bit kernel. That's none atm :-)
602 */ 602 */
603#define __read_64bit_c0_split(source, sel) \ 603#define __read_64bit_c0_split(source, sel) \
604({ \ 604({ \
605 unsigned long long val; \ 605 unsigned long long val; \
606 unsigned long flags; \ 606 unsigned long flags; \
607 \ 607 \
608 local_irq_save(flags); \ 608 local_irq_save(flags); \
609 if (sel == 0) \ 609 if (sel == 0) \
610 __asm__ __volatile__( \ 610 __asm__ __volatile__( \
611 ".set\tmips64\n\t" \ 611 ".set\tmips64\n\t" \
612 "dmfc0\t%M0, " #source "\n\t" \ 612 "dmfc0\t%M0, " #source "\n\t" \
613 "dsll\t%L0, %M0, 32\n\t" \ 613 "dsll\t%L0, %M0, 32\n\t" \
614 "dsrl\t%M0, %M0, 32\n\t" \ 614 "dsrl\t%M0, %M0, 32\n\t" \
615 "dsrl\t%L0, %L0, 32\n\t" \ 615 "dsrl\t%L0, %L0, 32\n\t" \
616 ".set\tmips0" \ 616 ".set\tmips0" \
617 : "=r" (val)); \ 617 : "=r" (val)); \
618 else \ 618 else \
619 __asm__ __volatile__( \ 619 __asm__ __volatile__( \
620 ".set\tmips64\n\t" \ 620 ".set\tmips64\n\t" \
621 "dmfc0\t%M0, " #source ", " #sel "\n\t" \ 621 "dmfc0\t%M0, " #source ", " #sel "\n\t" \
622 "dsll\t%L0, %M0, 32\n\t" \ 622 "dsll\t%L0, %M0, 32\n\t" \
623 "dsrl\t%M0, %M0, 32\n\t" \ 623 "dsrl\t%M0, %M0, 32\n\t" \
624 "dsrl\t%L0, %L0, 32\n\t" \ 624 "dsrl\t%L0, %L0, 32\n\t" \
625 ".set\tmips0" \ 625 ".set\tmips0" \
626 : "=r" (val)); \ 626 : "=r" (val)); \
627 local_irq_restore(flags); \ 627 local_irq_restore(flags); \
628 \ 628 \
629 val; \ 629 val; \
630}) 630})
631 631
632#define __write_64bit_c0_split(source, sel, val) \ 632#define __write_64bit_c0_split(source, sel, val) \
633do { \ 633do { \
634 unsigned long flags; \ 634 unsigned long flags; \
635 \ 635 \
636 local_irq_save(flags); \ 636 local_irq_save(flags); \
637 if (sel == 0) \ 637 if (sel == 0) \
638 __asm__ __volatile__( \ 638 __asm__ __volatile__( \
639 ".set\tmips64\n\t" \ 639 ".set\tmips64\n\t" \
640 "dsll\t%L0, %L0, 32\n\t" \ 640 "dsll\t%L0, %L0, 32\n\t" \
641 "dsrl\t%L0, %L0, 32\n\t" \ 641 "dsrl\t%L0, %L0, 32\n\t" \
642 "dsll\t%M0, %M0, 32\n\t" \ 642 "dsll\t%M0, %M0, 32\n\t" \
643 "or\t%L0, %L0, %M0\n\t" \ 643 "or\t%L0, %L0, %M0\n\t" \
644 "dmtc0\t%L0, " #source "\n\t" \ 644 "dmtc0\t%L0, " #source "\n\t" \
645 ".set\tmips0" \ 645 ".set\tmips0" \
646 : : "r" (val)); \ 646 : : "r" (val)); \
647 else \ 647 else \
648 __asm__ __volatile__( \ 648 __asm__ __volatile__( \
649 ".set\tmips64\n\t" \ 649 ".set\tmips64\n\t" \
650 "dsll\t%L0, %L0, 32\n\t" \ 650 "dsll\t%L0, %L0, 32\n\t" \
651 "dsrl\t%L0, %L0, 32\n\t" \ 651 "dsrl\t%L0, %L0, 32\n\t" \
652 "dsll\t%M0, %M0, 32\n\t" \ 652 "dsll\t%M0, %M0, 32\n\t" \
653 "or\t%L0, %L0, %M0\n\t" \ 653 "or\t%L0, %L0, %M0\n\t" \
654 "dmtc0\t%L0, " #source ", " #sel "\n\t" \ 654 "dmtc0\t%L0, " #source ", " #sel "\n\t" \
655 ".set\tmips0" \ 655 ".set\tmips0" \
656 : : "r" (val)); \ 656 : : "r" (val)); \
657 local_irq_restore(flags); \ 657 local_irq_restore(flags); \
658} while (0) 658} while (0)
659 659
660#define read_c0_index() __read_32bit_c0_register($0, 0) 660#define read_c0_index() __read_32bit_c0_register($0, 0)
661#define write_c0_index(val) __write_32bit_c0_register($0, 0, val) 661#define write_c0_index(val) __write_32bit_c0_register($0, 0, val)
662 662
663#define read_c0_entrylo0() __read_ulong_c0_register($2, 0) 663#define read_c0_entrylo0() __read_ulong_c0_register($2, 0)
664#define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val) 664#define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val)
665 665
666#define read_c0_entrylo1() __read_ulong_c0_register($3, 0) 666#define read_c0_entrylo1() __read_ulong_c0_register($3, 0)
667#define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val) 667#define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val)
668 668
669#define read_c0_conf() __read_32bit_c0_register($3, 0) 669#define read_c0_conf() __read_32bit_c0_register($3, 0)
670#define write_c0_conf(val) __write_32bit_c0_register($3, 0, val) 670#define write_c0_conf(val) __write_32bit_c0_register($3, 0, val)
671 671
672#define read_c0_context() __read_ulong_c0_register($4, 0) 672#define read_c0_context() __read_ulong_c0_register($4, 0)
673#define write_c0_context(val) __write_ulong_c0_register($4, 0, val) 673#define write_c0_context(val) __write_ulong_c0_register($4, 0, val)
674 674
675#define read_c0_pagemask() __read_32bit_c0_register($5, 0) 675#define read_c0_pagemask() __read_32bit_c0_register($5, 0)
676#define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val) 676#define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val)
677 677
678#define read_c0_wired() __read_32bit_c0_register($6, 0) 678#define read_c0_wired() __read_32bit_c0_register($6, 0)
679#define write_c0_wired(val) __write_32bit_c0_register($6, 0, val) 679#define write_c0_wired(val) __write_32bit_c0_register($6, 0, val)
680 680
681#define read_c0_info() __read_32bit_c0_register($7, 0) 681#define read_c0_info() __read_32bit_c0_register($7, 0)
682 682
683#define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */ 683#define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */
684#define write_c0_cache(val) __write_32bit_c0_register($7, 0, val) 684#define write_c0_cache(val) __write_32bit_c0_register($7, 0, val)
685 685
686#define read_c0_badvaddr() __read_32bit_c0_register($8, 0) 686#define read_c0_badvaddr() __read_32bit_c0_register($8, 0)
687 687
688#define read_c0_count() __read_32bit_c0_register($9, 0) 688#define read_c0_count() __read_32bit_c0_register($9, 0)
689#define write_c0_count(val) __write_32bit_c0_register($9, 0, val) 689#define write_c0_count(val) __write_32bit_c0_register($9, 0, val)
690 690
691#define read_c0_entryhi() __read_ulong_c0_register($10, 0) 691#define read_c0_entryhi() __read_ulong_c0_register($10, 0)
692#define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val) 692#define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val)
693 693
694#define read_c0_compare() __read_32bit_c0_register($11, 0) 694#define read_c0_compare() __read_32bit_c0_register($11, 0)
695#define write_c0_compare(val) __write_32bit_c0_register($11, 0, val) 695#define write_c0_compare(val) __write_32bit_c0_register($11, 0, val)
696 696
697#define read_c0_status() __read_32bit_c0_register($12, 0) 697#define read_c0_status() __read_32bit_c0_register($12, 0)
698#define write_c0_status(val) __write_32bit_c0_register($12, 0, val) 698#define write_c0_status(val) __write_32bit_c0_register($12, 0, val)
699 699
700#define read_c0_cause() __read_32bit_c0_register($13, 0) 700#define read_c0_cause() __read_32bit_c0_register($13, 0)
701#define write_c0_cause(val) __write_32bit_c0_register($13, 0, val) 701#define write_c0_cause(val) __write_32bit_c0_register($13, 0, val)
702 702
703#define read_c0_prid() __read_32bit_c0_register($15, 0) 703#define read_c0_prid() __read_32bit_c0_register($15, 0)
704 704
705#define read_c0_config() __read_32bit_c0_register($16, 0) 705#define read_c0_config() __read_32bit_c0_register($16, 0)
706#define read_c0_config1() __read_32bit_c0_register($16, 1) 706#define read_c0_config1() __read_32bit_c0_register($16, 1)
707#define read_c0_config2() __read_32bit_c0_register($16, 2) 707#define read_c0_config2() __read_32bit_c0_register($16, 2)
708#define read_c0_config3() __read_32bit_c0_register($16, 3) 708#define read_c0_config3() __read_32bit_c0_register($16, 3)
709#define write_c0_config(val) __write_32bit_c0_register($16, 0, val) 709#define write_c0_config(val) __write_32bit_c0_register($16, 0, val)
710#define write_c0_config1(val) __write_32bit_c0_register($16, 1, val) 710#define write_c0_config1(val) __write_32bit_c0_register($16, 1, val)
711#define write_c0_config2(val) __write_32bit_c0_register($16, 2, val) 711#define write_c0_config2(val) __write_32bit_c0_register($16, 2, val)
712#define write_c0_config3(val) __write_32bit_c0_register($16, 3, val) 712#define write_c0_config3(val) __write_32bit_c0_register($16, 3, val)
713 713
714/* 714/*
715 * The WatchLo register. There may be upto 8 of them. 715 * The WatchLo register. There may be upto 8 of them.
716 */ 716 */
717#define read_c0_watchlo0() __read_ulong_c0_register($18, 0) 717#define read_c0_watchlo0() __read_ulong_c0_register($18, 0)
718#define read_c0_watchlo1() __read_ulong_c0_register($18, 1) 718#define read_c0_watchlo1() __read_ulong_c0_register($18, 1)
719#define read_c0_watchlo2() __read_ulong_c0_register($18, 2) 719#define read_c0_watchlo2() __read_ulong_c0_register($18, 2)
720#define read_c0_watchlo3() __read_ulong_c0_register($18, 3) 720#define read_c0_watchlo3() __read_ulong_c0_register($18, 3)
721#define read_c0_watchlo4() __read_ulong_c0_register($18, 4) 721#define read_c0_watchlo4() __read_ulong_c0_register($18, 4)
722#define read_c0_watchlo5() __read_ulong_c0_register($18, 5) 722#define read_c0_watchlo5() __read_ulong_c0_register($18, 5)
723#define read_c0_watchlo6() __read_ulong_c0_register($18, 6) 723#define read_c0_watchlo6() __read_ulong_c0_register($18, 6)
724#define read_c0_watchlo7() __read_ulong_c0_register($18, 7) 724#define read_c0_watchlo7() __read_ulong_c0_register($18, 7)
725#define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val) 725#define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val)
726#define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val) 726#define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val)
727#define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val) 727#define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val)
728#define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val) 728#define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val)
729#define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val) 729#define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val)
730#define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val) 730#define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val)
731#define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val) 731#define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val)
732#define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val) 732#define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val)
733 733
734/* 734/*
735 * The WatchHi register. There may be upto 8 of them. 735 * The WatchHi register. There may be upto 8 of them.
736 */ 736 */
737#define read_c0_watchhi0() __read_32bit_c0_register($19, 0) 737#define read_c0_watchhi0() __read_32bit_c0_register($19, 0)
738#define read_c0_watchhi1() __read_32bit_c0_register($19, 1) 738#define read_c0_watchhi1() __read_32bit_c0_register($19, 1)
739#define read_c0_watchhi2() __read_32bit_c0_register($19, 2) 739#define read_c0_watchhi2() __read_32bit_c0_register($19, 2)
740#define read_c0_watchhi3() __read_32bit_c0_register($19, 3) 740#define read_c0_watchhi3() __read_32bit_c0_register($19, 3)
741#define read_c0_watchhi4() __read_32bit_c0_register($19, 4) 741#define read_c0_watchhi4() __read_32bit_c0_register($19, 4)
742#define read_c0_watchhi5() __read_32bit_c0_register($19, 5) 742#define read_c0_watchhi5() __read_32bit_c0_register($19, 5)
743#define read_c0_watchhi6() __read_32bit_c0_register($19, 6) 743#define read_c0_watchhi6() __read_32bit_c0_register($19, 6)
744#define read_c0_watchhi7() __read_32bit_c0_register($19, 7) 744#define read_c0_watchhi7() __read_32bit_c0_register($19, 7)
745 745
746#define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val) 746#define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val)
747#define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val) 747#define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val)
748#define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val) 748#define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val)
749#define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val) 749#define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val)
750#define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val) 750#define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val)
751#define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val) 751#define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val)
752#define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val) 752#define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val)
753#define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val) 753#define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val)
754 754
755#define read_c0_xcontext() __read_ulong_c0_register($20, 0) 755#define read_c0_xcontext() __read_ulong_c0_register($20, 0)
756#define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val) 756#define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val)
757 757
758#define read_c0_intcontrol() __read_32bit_c0_register($20, 1) 758#define read_c0_intcontrol() __read_32bit_c0_register($20, 1)
759#define write_c0_intcontrol(val) __write_32bit_c0_register($20, 1, val) 759#define write_c0_intcontrol(val) __write_32bit_c0_register($20, 1, val)
760 760
761#define read_c0_framemask() __read_32bit_c0_register($21, 0) 761#define read_c0_framemask() __read_32bit_c0_register($21, 0)
762#define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val) 762#define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
763 763
764#define read_c0_debug() __read_32bit_c0_register($23, 0) 764#define read_c0_debug() __read_32bit_c0_register($23, 0)
765#define write_c0_debug(val) __write_32bit_c0_register($23, 0, val) 765#define write_c0_debug(val) __write_32bit_c0_register($23, 0, val)
766 766
767#define read_c0_depc() __read_ulong_c0_register($24, 0) 767#define read_c0_depc() __read_ulong_c0_register($24, 0)
768#define write_c0_depc(val) __write_ulong_c0_register($24, 0, val) 768#define write_c0_depc(val) __write_ulong_c0_register($24, 0, val)
769 769
770#define read_c0_ecc() __read_32bit_c0_register($26, 0) 770#define read_c0_ecc() __read_32bit_c0_register($26, 0)
771#define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val) 771#define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val)
772 772
773#define read_c0_derraddr0() __read_ulong_c0_register($26, 1) 773#define read_c0_derraddr0() __read_ulong_c0_register($26, 1)
774#define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val) 774#define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
775 775
776#define read_c0_cacheerr() __read_32bit_c0_register($27, 0) 776#define read_c0_cacheerr() __read_32bit_c0_register($27, 0)
777 777
778#define read_c0_derraddr1() __read_ulong_c0_register($27, 1) 778#define read_c0_derraddr1() __read_ulong_c0_register($27, 1)
779#define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val) 779#define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
780 780
781#define read_c0_taglo() __read_32bit_c0_register($28, 0) 781#define read_c0_taglo() __read_32bit_c0_register($28, 0)
782#define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val) 782#define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val)
783 783
784#define read_c0_taghi() __read_32bit_c0_register($29, 0) 784#define read_c0_taghi() __read_32bit_c0_register($29, 0)
785#define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val) 785#define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val)
786 786
787#define read_c0_errorepc() __read_ulong_c0_register($30, 0) 787#define read_c0_errorepc() __read_ulong_c0_register($30, 0)
788#define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val) 788#define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val)
789 789
790#define read_c0_epc() __read_ulong_c0_register($14, 0) 790#define read_c0_epc() __read_ulong_c0_register($14, 0)
791#define write_c0_epc(val) __write_ulong_c0_register($14, 0, val) 791#define write_c0_epc(val) __write_ulong_c0_register($14, 0, val)
792 792
793#if 1 793#if 1
794/* 794/*
@@ -797,20 +797,20 @@ do { \
797#define read_32bit_cp0_register(source) \ 797#define read_32bit_cp0_register(source) \
798({ int __res; \ 798({ int __res; \
799 __asm__ __volatile__( \ 799 __asm__ __volatile__( \
800 ".set\tpush\n\t" \ 800 ".set\tpush\n\t" \
801 ".set\treorder\n\t" \ 801 ".set\treorder\n\t" \
802 "mfc0\t%0,"STR(source)"\n\t" \ 802 "mfc0\t%0,"STR(source)"\n\t" \
803 ".set\tpop" \ 803 ".set\tpop" \
804 : "=r" (__res)); \ 804 : "=r" (__res)); \
805 __res;}) 805 __res;})
806 806
807#define read_32bit_cp0_set1_register(source) \ 807#define read_32bit_cp0_set1_register(source) \
808({ int __res; \ 808({ int __res; \
809 __asm__ __volatile__( \ 809 __asm__ __volatile__( \
810 ".set\tpush\n\t" \ 810 ".set\tpush\n\t" \
811 ".set\treorder\n\t" \ 811 ".set\treorder\n\t" \
812 "cfc0\t%0,"STR(source)"\n\t" \ 812 "cfc0\t%0,"STR(source)"\n\t" \
813 ".set\tpop" \ 813 ".set\tpop" \
814 : "=r" (__res)); \ 814 : "=r" (__res)); \
815 __res;}) 815 __res;})
816 816
@@ -828,14 +828,14 @@ do { \
828 828
829#define write_32bit_cp0_register(register,value) \ 829#define write_32bit_cp0_register(register,value) \
830 __asm__ __volatile__( \ 830 __asm__ __volatile__( \
831 "mtc0\t%0,"STR(register)"\n\t" \ 831 "mtc0\t%0,"STR(register)"\n\t" \
832 "nop" \ 832 "nop" \
833 : : "r" (value)); 833 : : "r" (value));
834 834
835#define write_32bit_cp0_set1_register(register,value) \ 835#define write_32bit_cp0_set1_register(register,value) \
836 __asm__ __volatile__( \ 836 __asm__ __volatile__( \
837 "ctc0\t%0,"STR(register)"\n\t" \ 837 "ctc0\t%0,"STR(register)"\n\t" \
838 "nop" \ 838 "nop" \
839 : : "r" (value)); 839 : : "r" (value));
840 840
841#define write_64bit_cp0_register(register,value) \ 841#define write_64bit_cp0_register(register,value) \
@@ -851,16 +851,16 @@ do { \
851#define read_mips32_cp0_config1() \ 851#define read_mips32_cp0_config1() \
852({ int __res; \ 852({ int __res; \
853 __asm__ __volatile__( \ 853 __asm__ __volatile__( \
854 ".set\tnoreorder\n\t" \ 854 ".set\tnoreorder\n\t" \
855 ".set\tnoat\n\t" \ 855 ".set\tnoat\n\t" \
856 "#.set\tmips64\n\t" \ 856 "#.set\tmips64\n\t" \
857 "#mfc0\t$1, $16, 1\n\t" \ 857 "#mfc0\t$1, $16, 1\n\t" \
858 "#.set\tmips0\n\t" \ 858 "#.set\tmips0\n\t" \
859 ".word\t0x40018001\n\t" \ 859 ".word\t0x40018001\n\t" \
860 "move\t%0,$1\n\t" \ 860 "move\t%0,$1\n\t" \
861 ".set\tat\n\t" \ 861 ".set\tat\n\t" \
862 ".set\treorder" \ 862 ".set\treorder" \
863 :"=r" (__res)); \ 863 :"=r" (__res)); \
864 __res;}) 864 __res;})
865 865
866#endif 866#endif
@@ -869,95 +869,95 @@ do { \
869 */ 869 */
870#define read_32bit_cp1_register(source) \ 870#define read_32bit_cp1_register(source) \
871({ int __res; \ 871({ int __res; \
872 __asm__ __volatile__( \ 872 __asm__ __volatile__( \
873 ".set\tpush\n\t" \ 873 ".set\tpush\n\t" \
874 ".set\treorder\n\t" \ 874 ".set\treorder\n\t" \
875 "cfc1\t%0,"STR(source)"\n\t" \ 875 "cfc1\t%0,"STR(source)"\n\t" \
876 ".set\tpop" \ 876 ".set\tpop" \
877 : "=r" (__res)); \ 877 : "=r" (__res)); \
878 __res;}) 878 __res;})
879 879
880/* TLB operations. */ 880/* TLB operations. */
881static inline void tlb_probe(void) 881static inline void tlb_probe(void)
882{ 882{
883 __asm__ __volatile__( 883 __asm__ __volatile__(
884 ".set noreorder\n\t" 884 ".set noreorder\n\t"
885 "tlbp\n\t" 885 "tlbp\n\t"
886 ".set reorder"); 886 ".set reorder");
887} 887}
888 888
889static inline void tlb_read(void) 889static inline void tlb_read(void)
890{ 890{
891 __asm__ __volatile__( 891 __asm__ __volatile__(
892 ".set noreorder\n\t" 892 ".set noreorder\n\t"
893 "tlbr\n\t" 893 "tlbr\n\t"
894 ".set reorder"); 894 ".set reorder");
895} 895}
896 896
897static inline void tlb_write_indexed(void) 897static inline void tlb_write_indexed(void)
898{ 898{
899 __asm__ __volatile__( 899 __asm__ __volatile__(
900 ".set noreorder\n\t" 900 ".set noreorder\n\t"
901 "tlbwi\n\t" 901 "tlbwi\n\t"
902 ".set reorder"); 902 ".set reorder");
903} 903}
904 904
905static inline void tlb_write_random(void) 905static inline void tlb_write_random(void)
906{ 906{
907 __asm__ __volatile__( 907 __asm__ __volatile__(
908 ".set noreorder\n\t" 908 ".set noreorder\n\t"
909 "tlbwr\n\t" 909 "tlbwr\n\t"
910 ".set reorder"); 910 ".set reorder");
911} 911}
912 912
913/* 913/*
914 * Manipulate bits in a c0 register. 914 * Manipulate bits in a c0 register.
915 */ 915 */
916#define __BUILD_SET_C0(name,register) \ 916#define __BUILD_SET_C0(name,register) \
917static inline unsigned int \ 917static inline unsigned int \
918set_c0_##name(unsigned int set) \ 918set_c0_##name(unsigned int set) \
919{ \ 919{ \
920 unsigned int res; \ 920 unsigned int res; \
921 \ 921 \
922 res = read_c0_##name(); \ 922 res = read_c0_##name(); \
923 res |= set; \ 923 res |= set; \
924 write_c0_##name(res); \ 924 write_c0_##name(res); \
925 \ 925 \
926 return res; \ 926 return res; \
927} \ 927} \
928 \ 928 \
929static inline unsigned int \ 929static inline unsigned int \
930clear_c0_##name(unsigned int clear) \ 930clear_c0_##name(unsigned int clear) \
931{ \ 931{ \
932 unsigned int res; \ 932 unsigned int res; \
933 \ 933 \
934 res = read_c0_##name(); \ 934 res = read_c0_##name(); \
935 res &= ~clear; \ 935 res &= ~clear; \
936 write_c0_##name(res); \ 936 write_c0_##name(res); \
937 \ 937 \
938 return res; \ 938 return res; \
939} \ 939} \
940 \ 940 \
941static inline unsigned int \ 941static inline unsigned int \
942change_c0_##name(unsigned int change, unsigned int new) \ 942change_c0_##name(unsigned int change, unsigned int new) \
943{ \ 943{ \
944 unsigned int res; \ 944 unsigned int res; \
945 \ 945 \
946 res = read_c0_##name(); \ 946 res = read_c0_##name(); \
947 res &= ~change; \ 947 res &= ~change; \
948 res |= (new & change); \ 948 res |= (new & change); \
949 write_c0_##name(res); \ 949 write_c0_##name(res); \
950 \ 950 \
951 return res; \ 951 return res; \
952} 952}
953 953
954__BUILD_SET_C0(status,CP0_STATUS) 954__BUILD_SET_C0(status,CP0_STATUS)
955__BUILD_SET_C0(cause,CP0_CAUSE) 955__BUILD_SET_C0(cause,CP0_CAUSE)
956__BUILD_SET_C0(config,CP0_CONFIG) 956__BUILD_SET_C0(config,CP0_CONFIG)
957 957
958#define set_cp0_status(x) set_c0_status(x) 958#define set_cp0_status(x) set_c0_status(x)
959#define set_cp0_cause(x) set_c0_cause(x) 959#define set_cp0_cause(x) set_c0_cause(x)
960#define set_cp0_config(x) set_c0_config(x) 960#define set_cp0_config(x) set_c0_config(x)
961 961
962#endif /* !__ASSEMBLY__ */ 962#endif /* !__ASSEMBLY__ */
963 963
diff --git a/firmware/target/mips/ingenic_jz47xx/debug-jz4740.c b/firmware/target/mips/ingenic_jz47xx/debug-jz4740.c
index 2164f1d323..7b0b74ed0d 100644
--- a/firmware/target/mips/ingenic_jz47xx/debug-jz4740.c
+++ b/firmware/target/mips/ingenic_jz47xx/debug-jz4740.c
@@ -28,6 +28,7 @@
28#include "kernel.h" 28#include "kernel.h"
29#include "font.h" 29#include "font.h"
30#include "button.h" 30#include "button.h"
31#include "timefuncs.h"
31 32
32static int line = 0; 33static int line = 0;
33static void printf(const char *format, ...) 34static void printf(const char *format, ...)
@@ -150,6 +151,7 @@ bool __dbg_ports(void)
150bool __dbg_hw_info(void) 151bool __dbg_hw_info(void)
151{ 152{
152 int btn = 0, touch; 153 int btn = 0, touch;
154 struct tm *cur_time;
153 155
154 lcd_setfont(FONT_SYSFIXED); 156 lcd_setfont(FONT_SYSFIXED);
155 while(btn ^ BUTTON_POWER) 157 while(btn ^ BUTTON_POWER)
@@ -159,7 +161,11 @@ bool __dbg_hw_info(void)
159 display_clocks(); 161 display_clocks();
160 display_enabled_clocks(); 162 display_enabled_clocks();
161 btn = button_read_device(&touch); 163 btn = button_read_device(&touch);
164 cur_time = get_time();
162 printf("X: %d Y: %d BTN: 0x%X", touch>>16, touch&0xFFFF, btn); 165 printf("X: %d Y: %d BTN: 0x%X", touch>>16, touch&0xFFFF, btn);
166 printf("%02d/%02d/%04d %02d:%02d:%02d", cur_time->tm_mday,
167 cur_time->tm_mon, cur_time->tm_year, cur_time->tm_hour,
168 cur_time->tm_min, cur_time->tm_sec);
163 lcd_update(); 169 lcd_update();
164 sleep(HZ/16); 170 sleep(HZ/16);
165 } 171 }
diff --git a/firmware/target/mips/ingenic_jz47xx/onda_vx747/sadc-onda_vx747.c b/firmware/target/mips/ingenic_jz47xx/onda_vx747/sadc-onda_vx747.c
index f750efdf57..c6fffdec42 100644
--- a/firmware/target/mips/ingenic_jz47xx/onda_vx747/sadc-onda_vx747.c
+++ b/firmware/target/mips/ingenic_jz47xx/onda_vx747/sadc-onda_vx747.c
@@ -108,34 +108,25 @@ const unsigned short percent_to_volt_charge[11] =
108/* Returns battery voltage from ADC [millivolts] */ 108/* Returns battery voltage from ADC [millivolts] */
109unsigned int battery_adc_voltage(void) 109unsigned int battery_adc_voltage(void)
110{ 110{
111 unsigned int val, i; 111 unsigned int dummy, timeout=1000;
112 112
113 mutex_lock(&battery_mtx); 113 mutex_lock(&battery_mtx);
114 114
115 val = REG_SADC_BATDAT; 115 dummy = REG_SADC_BATDAT;
116 val = REG_SADC_BATDAT; 116 dummy = REG_SADC_BATDAT;
117 117
118 REG_SADC_ENA |= SADC_ENA_PBATEN; 118 REG_SADC_ENA |= SADC_ENA_PBATEN;
119 for(i=0; i<4; i++) 119 bat_val = 0;
120 {
121 bat_val = 0;
122
123 /* primitive wakeup event */
124 while(bat_val == 0)
125 sleep(0);
126
127 val += bat_val;
128 }
129 REG_SADC_ENA &= ~SADC_ENA_PBATEN;
130 120
131 val /= 4; 121 /* primitive wakeup event */
122 while(bat_val == 0 && timeout--)
123 sleep(0);
132 124
133 logf("%d %d %d", val, (val*BATTERY_SCALE_FACTOR)>>12, 125 logf("%d %d", bat_val, (bat_val*BATTERY_SCALE_FACTOR)>>12);
134 (val*0xAAAAAAAB >> 32) >> 1);
135 126
136 mutex_unlock(&battery_mtx); 127 mutex_unlock(&battery_mtx);
137 128
138 return (val*BATTERY_SCALE_FACTOR)>>12; 129 return (bat_val*BATTERY_SCALE_FACTOR)>>12;
139} 130}
140 131
141void button_init_device(void) 132void button_init_device(void)
diff --git a/firmware/target/mips/ingenic_jz47xx/system-jz4740.c b/firmware/target/mips/ingenic_jz47xx/system-jz4740.c
index e37f17c73f..c029dd46bb 100644
--- a/firmware/target/mips/ingenic_jz47xx/system-jz4740.c
+++ b/firmware/target/mips/ingenic_jz47xx/system-jz4740.c
@@ -509,6 +509,9 @@ void system_exception_wait(void)
509 509
510void power_off(void) 510void power_off(void)
511{ 511{
512 /* Enable RTC clock */
513 __cpm_start_rtc();
514
512 /* Put system into hibernate mode */ 515 /* Put system into hibernate mode */
513 __rtc_clear_alarm_flag(); 516 __rtc_clear_alarm_flag();
514 __rtc_clear_hib_stat_all(); 517 __rtc_clear_hib_stat_all();
generated by cgit v1.2.3 (git 2.39.1) at 2024-09-17 21:36:43 +0000