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authorMichael Sevakis <jethead71@rockbox.org>2010-05-08 07:45:34 +0000
committerMichael Sevakis <jethead71@rockbox.org>2010-05-08 07:45:34 +0000
commita420561bf8315f60c290ea41aaa7e80f410c592d (patch)
tree4f8f2e5e8ad8f613d3647a0239e8c40ed8b3cf8c /firmware/export/imx31l.h
parent7f3b3494a6a4198c59e07d54ad979b7a764250b6 (diff)
downloadrockbox-a420561bf8315f60c290ea41aaa7e80f410c592d.tar.gz
rockbox-a420561bf8315f60c290ea41aaa7e80f410c592d.zip
Gigabeat S: Reclaim about 800K of memory that was laying unused. Get rid of DEVBSS_ATTR for this target and implement as NOCACHEBSS_ATTR. Plugin and codec buffers move so all that is now incompatible (do full update). No version increase for plugins/codecs because the loader will reject them.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25895 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/export/imx31l.h')
-rw-r--r--firmware/export/imx31l.h10
1 files changed, 7 insertions, 3 deletions
diff --git a/firmware/export/imx31l.h b/firmware/export/imx31l.h
index 66ae0acc4d..ea92d059cc 100644
--- a/firmware/export/imx31l.h
+++ b/firmware/export/imx31l.h
@@ -35,14 +35,18 @@
35#define FRAME_SIZE (240*320*2) 35#define FRAME_SIZE (240*320*2)
36/* Rockbox framebuffer address, not retail OS */ 36/* Rockbox framebuffer address, not retail OS */
37#define FRAME_PHYS_ADDR (TTB_BASE_ADDR - FRAME_SIZE) 37#define FRAME_PHYS_ADDR (TTB_BASE_ADDR - FRAME_SIZE)
38#define FRAME ((void *)(FRAME_PHYS_ADDR-CSD0_BASE_ADDR)) 38#define FRAME ((void *)(FRAME_PHYS_ADDR+0x100000-CSD0_BASE_ADDR))
39
40#define CACHEALIGN_SIZE 32
41#define NOCACHE_BASE CSD0_BASE_ADDR
39 42
40#define DEVBSS_ATTR __attribute__((section(".devbss"),nocommon))
41/* USBOTG */ 43/* USBOTG */
42#define USB_QHARRAY_ATTR __attribute__((section(".qharray"),nocommon,aligned(2048))) 44#define USB_QHARRAY_ATTR __attribute__((section(".qharray"),nocommon,aligned(2048)))
43#define USB_NUM_ENDPOINTS 8 45#define USB_NUM_ENDPOINTS 8
44#define USB_DEVBSS_ATTR DEVBSS_ATTR 46#define USB_DEVBSS_ATTR NOCACHEBSS_ATTR
45#define USB_BASE OTG_BASE_ADDR 47#define USB_BASE OTG_BASE_ADDR
48#define QHARRAY_SIZE ((64*USB_NUM_ENDPOINTS*2 + 2047) & (0xffffffff - 2047))
49#define QHARRAY_PHYS_ADDR ((FRAME_PHYS_ADDR - QHARRAY_SIZE) & (0xffffffff - 2047))
46 50
47/* 51/*
48 * AIPS 1 52 * AIPS 1