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authorTomasz Moń <desowin@gmail.com>2021-07-08 18:23:18 +0200
committerTomasz Moń <desowin@gmail.com>2021-07-09 09:24:38 +0000
commit60e2cd6de946c0c473c0e9bfde5b7b1d47a5b28f (patch)
tree07ebe2764bc37a0189da55a62312524769a5ecab /firmware/export/dm320.h
parent2e9b93dc5df5aff35a64c55493bc2d2d74b4aa0d (diff)
downloadrockbox-60e2cd6de946c0c473c0e9bfde5b7b1d47a5b28f.tar.gz
rockbox-60e2cd6de946c0c473c0e9bfde5b7b1d47a5b28f.zip
DM320: Regorganize LCD and TTB memory layout
Do not introduce any change for M:Robe 500 as it uses the two LCD frames in non-obvious way. Sansa Connect and Creative ZVM use only single front framebuffer. Place TTB at DRAM end to minimize memory loss due to alignment. Reserve as little as possible memory for the LCD frames. On Sansa Connect this change extends audio buffer by 858 KiB. Change-Id: I21bdeec4cfba86d71803a39acd651a87e73767e6
Diffstat (limited to 'firmware/export/dm320.h')
-rw-r--r--firmware/export/dm320.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/firmware/export/dm320.h b/firmware/export/dm320.h
index 01f206bfc9..bd6ca15407 100644
--- a/firmware/export/dm320.h
+++ b/firmware/export/dm320.h
@@ -30,13 +30,17 @@
30#if !defined(__ASSEMBLER__) && !defined(__LD__) 30#if !defined(__ASSEMBLER__) && !defined(__LD__)
31/* These variables are created during linking (app/boot.lds) */ 31/* These variables are created during linking (app/boot.lds) */
32extern unsigned long _lcdbuf; 32extern unsigned long _lcdbuf;
33#ifdef MROBE_500
33extern unsigned long _lcdbuf2; 34extern unsigned long _lcdbuf2;
35#endif
34extern unsigned long _ttbstart; 36extern unsigned long _ttbstart;
35#endif 37#endif
36 38
37#define TTB_BASE_ADDR (_ttbstart) /* End of memory */ 39#define TTB_BASE_ADDR (_ttbstart) /* End of memory */
38#define FRAME ((short *) (&_lcdbuf)) /* Right after TTB */ 40#define FRAME ((short *) (&_lcdbuf)) /* Right after TTB */
41#ifdef MROBE_500
39#define FRAME2 ((short *) (&_lcdbuf2)) /* Right after FRAME */ 42#define FRAME2 ((short *) (&_lcdbuf2)) /* Right after FRAME */
43#endif
40 44
41#define PHY_IO_BASE 0x00030000 45#define PHY_IO_BASE 0x00030000
42#define DM320_REG(addr) (*(volatile unsigned short *)(PHY_IO_BASE + (addr))) 46#define DM320_REG(addr) (*(volatile unsigned short *)(PHY_IO_BASE + (addr)))