From 60e2cd6de946c0c473c0e9bfde5b7b1d47a5b28f Mon Sep 17 00:00:00 2001 From: Tomasz Moń Date: Thu, 8 Jul 2021 18:23:18 +0200 Subject: DM320: Regorganize LCD and TTB memory layout Do not introduce any change for M:Robe 500 as it uses the two LCD frames in non-obvious way. Sansa Connect and Creative ZVM use only single front framebuffer. Place TTB at DRAM end to minimize memory loss due to alignment. Reserve as little as possible memory for the LCD frames. On Sansa Connect this change extends audio buffer by 858 KiB. Change-Id: I21bdeec4cfba86d71803a39acd651a87e73767e6 --- firmware/export/dm320.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'firmware/export/dm320.h') diff --git a/firmware/export/dm320.h b/firmware/export/dm320.h index 01f206bfc9..bd6ca15407 100644 --- a/firmware/export/dm320.h +++ b/firmware/export/dm320.h @@ -30,13 +30,17 @@ #if !defined(__ASSEMBLER__) && !defined(__LD__) /* These variables are created during linking (app/boot.lds) */ extern unsigned long _lcdbuf; +#ifdef MROBE_500 extern unsigned long _lcdbuf2; +#endif extern unsigned long _ttbstart; #endif #define TTB_BASE_ADDR (_ttbstart) /* End of memory */ #define FRAME ((short *) (&_lcdbuf)) /* Right after TTB */ +#ifdef MROBE_500 #define FRAME2 ((short *) (&_lcdbuf2)) /* Right after FRAME */ +#endif #define PHY_IO_BASE 0x00030000 #define DM320_REG(addr) (*(volatile unsigned short *)(PHY_IO_BASE + (addr))) -- cgit v1.2.3