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author | Will Robertson <aliask@rockbox.org> | 2007-09-22 02:17:08 +0000 |
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committer | Will Robertson <aliask@rockbox.org> | 2007-09-22 02:17:08 +0000 |
commit | 26a05afe10b123788c8a32fbc92c7d80b1206f08 (patch) | |
tree | 2c5e8971f2b620a026fbafc2bf23d0fc5bac3863 /firmware/drivers | |
parent | 729388f741ba4fa6ba947c863d93885e8205c41a (diff) | |
download | rockbox-26a05afe10b123788c8a32fbc92c7d80b1206f08.tar.gz rockbox-26a05afe10b123788c8a32fbc92c7d80b1206f08.zip |
A few minor cleanups for the Gigabeat S
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@14812 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/drivers')
-rw-r--r-- | firmware/drivers/serial.c | 72 |
1 files changed, 72 insertions, 0 deletions
diff --git a/firmware/drivers/serial.c b/firmware/drivers/serial.c index 142f67e609..6ed539b780 100644 --- a/firmware/drivers/serial.c +++ b/firmware/drivers/serial.c | |||
@@ -27,6 +27,9 @@ | |||
27 | #include "lcd.h" | 27 | #include "lcd.h" |
28 | #include "serial.h" | 28 | #include "serial.h" |
29 | 29 | ||
30 | #if CONFIG_CPU == IMX31L | ||
31 | #include "serial-imx31.h" | ||
32 | #endif | ||
30 | 33 | ||
31 | #if CONFIG_CPU == SH7034 | 34 | #if CONFIG_CPU == SH7034 |
32 | 35 | ||
@@ -166,6 +169,75 @@ void serial_setup (void) | |||
166 | UCR0 = 0x04; /* Tx enable */ | 169 | UCR0 = 0x04; /* Tx enable */ |
167 | } | 170 | } |
168 | 171 | ||
172 | #elif (CONFIG_CPU == IMX31L) | ||
173 | |||
174 | void serial_setup(void) | ||
175 | { | ||
176 | #ifdef UART_INT /*enable UART Interrupts */ | ||
177 | UCR1_1 |= (EUartUCR1_TRDYEN | EUartUCR1_RRDYEN | EUartUCR1_TXMPTYEN); | ||
178 | UCR4_1 |= (EUartUCR4_TCEN); | ||
179 | #else /*disable UART Interrupts*/ | ||
180 | UCR1_1 &= ~(EUartUCR1_TRDYEN | EUartUCR1_RRDYEN | EUartUCR1_TXMPTYEN); | ||
181 | UCR4_1 &= ~(EUartUCR4_TCEN); | ||
182 | #endif | ||
183 | UCR1_1 |= EUartUCR1_UARTEN; | ||
184 | UCR2_1 |= (EUartUCR2_TXEN | EUartUCR2_RXEN | EUartUCR2_IRTS); | ||
185 | |||
186 | /* Tx,Rx Interrupt Trigger levels, Disable for now*/ | ||
187 | /*UFCR1 |= (UFCR1_TXTL_32 | UFCR1_RXTL_32);*/ | ||
188 | } | ||
189 | |||
190 | int Tx_Rdy(void) | ||
191 | { | ||
192 | if((UTS1 & EUartUTS_TXEMPTY)) | ||
193 | return 1; | ||
194 | else return 0; | ||
195 | } | ||
196 | |||
197 | /*Not ready...After first Rx, UTS1 & UTS1_RXEMPTY | ||
198 | keeps returning true*/ | ||
199 | int Rx_Rdy(void) | ||
200 | { | ||
201 | if(!(UTS1 & EUartUTS_RXEMPTY)) | ||
202 | return 1; | ||
203 | else return 0; | ||
204 | } | ||
205 | |||
206 | void Tx_Writec(char c) | ||
207 | { | ||
208 | UTXD1=(int) c; | ||
209 | } | ||
210 | |||
211 | void dprintf(const char * str, ... ) | ||
212 | { | ||
213 | char dprintfbuff[256]; | ||
214 | unsigned char * ptr; | ||
215 | |||
216 | va_list ap; | ||
217 | va_start(ap, str); | ||
218 | |||
219 | ptr = dprintfbuff; | ||
220 | vsnprintf(ptr,sizeof(dprintfbuff),str,ap); | ||
221 | va_end(ap); | ||
222 | |||
223 | serial_tx(ptr); | ||
224 | } | ||
225 | |||
226 | void serial_tx(const unsigned char * buf) | ||
227 | { | ||
228 | /*Tx*/ | ||
229 | for(;;) { | ||
230 | if(Tx_Rdy()) { | ||
231 | if(*buf == '\0') | ||
232 | return; | ||
233 | if(*buf == '\n') | ||
234 | Tx_Writec('\r'); | ||
235 | Tx_Writec(*buf); | ||
236 | buf++; | ||
237 | } | ||
238 | } | ||
239 | } | ||
240 | |||
169 | #else /* Other targets */ | 241 | #else /* Other targets */ |
170 | void serial_setup (void) | 242 | void serial_setup (void) |
171 | { | 243 | { |