A few minor cleanups for the Gigabeat S

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@14812 a1c6a512-1295-4272-9138-f99709370657

4 files changed, 80 insertions, 3 deletions

diff --git a/firmware/SOURCES b/firmware/SOURCES
index 92e2c1d8c5..9dd617b5d5 100644
--- a/firmware/SOURCES
+++ b/firmware/SOURCES
@@ -208,7 +208,7 @@ drivers/mas.c
 drivers/audio/uda1380.c
 #elif defined(HAVE_WM8751)
 drivers/audio/wm8751.c
-#elif defined(HAVE_WM8975)
+#elif defined(HAVE_WM8975) || defined(HAVE_WM8978)
 drivers/audio/wm8975.c
 #elif defined(HAVE_WM8758)
 drivers/audio/wm8758.c
@@ -608,7 +608,7 @@ target/arm/imx31/gigabeat-s/mmu-imx31.c
 target/arm/imx31/gigabeat-s/avic-imx31.c
 target/arm/imx31/gigabeat-s/spi-imx31.c
 #ifndef BOOTLOADER
-target/arm/imx31/gigabeat-fx/pcm-imx31.c
+target/arm/imx31/gigabeat-s/pcm-imx31.c
 #endif
 #endif /* SIMULATOR */
 #endif /* GIGABEAT_S */
diff --git a/firmware/drivers/serial.c b/firmware/drivers/serial.c
index 142f67e609..6ed539b780 100644
--- a/firmware/drivers/serial.c
+++ b/firmware/drivers/serial.c
@@ -27,6 +27,9 @@
 #include "lcd.h"
 #include "serial.h"
 
+#if CONFIG_CPU == IMX31L
+#include "serial-imx31.h"
+#endif
 
 #if CONFIG_CPU == SH7034
 
@@ -166,6 +169,75 @@ void serial_setup (void)
     UCR0 = 0x04; /* Tx enable */
 }
 
+#elif (CONFIG_CPU == IMX31L)
+
+void serial_setup(void)
+{
+#ifdef UART_INT /*enable UART Interrupts */
+    UCR1_1 |= (EUartUCR1_TRDYEN | EUartUCR1_RRDYEN | EUartUCR1_TXMPTYEN);
+    UCR4_1 |= (EUartUCR4_TCEN);
+#else /*disable UART Interrupts*/
+    UCR1_1 &= ~(EUartUCR1_TRDYEN | EUartUCR1_RRDYEN | EUartUCR1_TXMPTYEN);
+    UCR4_1 &= ~(EUartUCR4_TCEN);
+#endif
+    UCR1_1 |= EUartUCR1_UARTEN;
+    UCR2_1 |= (EUartUCR2_TXEN  | EUartUCR2_RXEN | EUartUCR2_IRTS);
+
+    /* Tx,Rx Interrupt Trigger levels, Disable for now*/
+    /*UFCR1 |= (UFCR1_TXTL_32 | UFCR1_RXTL_32);*/
+}
+
+int Tx_Rdy(void)
+{
+    if((UTS1 & EUartUTS_TXEMPTY))
+        return 1;
+    else return 0;
+}
+
+/*Not ready...After first Rx, UTS1 & UTS1_RXEMPTY 
+  keeps returning true*/
+int Rx_Rdy(void) 
+{
+    if(!(UTS1 & EUartUTS_RXEMPTY))
+        return 1;
+    else return 0;
+}
+
+void Tx_Writec(char c)
+{
+    UTXD1=(int) c;
+}
+
+void dprintf(const char * str, ... )
+{
+    char dprintfbuff[256];
+    unsigned char * ptr;
+        
+    va_list ap;
+    va_start(ap, str);
+
+    ptr = dprintfbuff;
+    vsnprintf(ptr,sizeof(dprintfbuff),str,ap);
+    va_end(ap);
+
+    serial_tx(ptr);
+}
+
+void serial_tx(const unsigned char * buf)
+{
+    /*Tx*/
+    for(;;) {
+        if(Tx_Rdy()) {
+            if(*buf == '\0')
+                return;
+            if(*buf == '\n')
+                Tx_Writec('\r');
+            Tx_Writec(*buf);
+            buf++;
+        }
+    }
+}
+
 #else /* Other targets */
 void serial_setup (void) 
 {
diff --git a/firmware/pcm_playback.c b/firmware/pcm_playback.c
index 1b16eb47db..123b7e3505 100644
--- a/firmware/pcm_playback.c
+++ b/firmware/pcm_playback.c
@@ -70,7 +70,8 @@ void pcm_mute(bool mute)
 }
 #endif /* defined(CPU_COLDFIRE) || (CONFIG_CPU == S3C2440) */
 
-#if defined(CPU_COLDFIRE) || (CONFIG_CPU == S3C2440) || defined(CPU_PP)
+#if defined(CPU_COLDFIRE) || (CONFIG_CPU == S3C2440) || defined(CPU_PP) \
+    || (CONFIG_CPU == IMX31L)
 /* Implemented in target/... */
 #else
 static int pcm_freq = HW_SAMPR_DEFAULT; /* 44.1 is default */
diff --git a/firmware/timer.c b/firmware/timer.c
index b86d4493a3..c08e8348d9 100644
--- a/firmware/timer.c
+++ b/firmware/timer.c
@@ -208,6 +208,8 @@ static bool timer_set(long cycles, bool start)
         cycles_new = cycles;
 
     return true;
+#elif (CONFIG_CPU == IMX31L)
+    /* TODO */
 #else
     return __TIMER_SET(cycles, start);
 #endif /* CONFIG_CPU */
@@ -268,6 +270,8 @@ bool timer_register(int reg_prio, void (*unregister_callback)(void),
     irq_set_int_handler(IRQ_TIMER1, TIMER1_ISR);
     irq_enable_int(IRQ_TIMER1);
     return true;
+#elif CONFIG_CPU == IMX31L
+    /* TODO */
 #else
     return __TIMER_REGISTER(reg_prio, unregister_callback, cycles,
                             int_prio, timer_callback);