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author | Solomon Peachy <pizza@shaftnet.org> | 2020-07-15 19:40:55 -0400 |
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committer | Solomon Peachy <pizza@shaftnet.org> | 2020-07-24 21:20:13 +0000 |
commit | 092c340a2062fa98b7387fc5fd63578ddae7d0b6 (patch) | |
tree | 98ec96946eeb2ae709cb0528cc6998e21bb9b290 /firmware/drivers/rtc/rtc_m41st84w.c | |
parent | 17f7cc92c258bc456a27c3e7c5a19c9409851879 (diff) | |
download | rockbox-092c340a2062fa98b7387fc5fd63578ddae7d0b6.tar.gz rockbox-092c340a2062fa98b7387fc5fd63578ddae7d0b6.zip |
[1/4] Remove SH support and all archos targets
This removes all code specific to SH targets
Change-Id: I7980523785d2596e65c06430f4638eec74a06061
Diffstat (limited to 'firmware/drivers/rtc/rtc_m41st84w.c')
-rw-r--r-- | firmware/drivers/rtc/rtc_m41st84w.c | 296 |
1 files changed, 0 insertions, 296 deletions
diff --git a/firmware/drivers/rtc/rtc_m41st84w.c b/firmware/drivers/rtc/rtc_m41st84w.c deleted file mode 100644 index 621e650f68..0000000000 --- a/firmware/drivers/rtc/rtc_m41st84w.c +++ /dev/null | |||
@@ -1,296 +0,0 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2002 by Linus Nielsen Feltzing, Uwe Freese, Laurent Baum | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | #include "config.h" | ||
22 | #include "i2c.h" | ||
23 | #include "rtc.h" | ||
24 | #include "kernel.h" | ||
25 | #include "system.h" | ||
26 | #include "timefuncs.h" | ||
27 | |||
28 | #define RTC_ADR 0xd0 | ||
29 | #define RTC_DEV_WRITE (RTC_ADR | 0x00) | ||
30 | #define RTC_DEV_READ (RTC_ADR | 0x01) | ||
31 | |||
32 | void rtc_init(void) | ||
33 | { | ||
34 | unsigned char data; | ||
35 | |||
36 | #ifdef HAVE_RTC_ALARM | ||
37 | /* Check + save alarm bit first, before the power thread starts watching */ | ||
38 | rtc_check_alarm_started(false); | ||
39 | #endif | ||
40 | |||
41 | /* Clear the Stop bit if it is set */ | ||
42 | data = rtc_read(0x01); | ||
43 | if(data & 0x80) | ||
44 | rtc_write(0x01, 0x00); | ||
45 | |||
46 | /* Clear the HT bit if it is set */ | ||
47 | data = rtc_read(0x0c); | ||
48 | |||
49 | if(data & 0x40) | ||
50 | { | ||
51 | data &= ~0x40; | ||
52 | rtc_write(0x0c,data); | ||
53 | } | ||
54 | |||
55 | #ifdef HAVE_RTC_ALARM | ||
56 | |||
57 | /* Clear Trec bit, write-protecting the RTC for 200ms when shutting off */ | ||
58 | /* without this, the alarm won't work! */ | ||
59 | |||
60 | data = rtc_read(0x04); | ||
61 | if (data & 0x80) | ||
62 | { | ||
63 | data &= ~0x80; | ||
64 | rtc_write(0x04, data); | ||
65 | } | ||
66 | |||
67 | /* Also, make sure that the OUT bit in register 8 is 1, | ||
68 | otherwise the player can't be turned off. */ | ||
69 | rtc_write(8, rtc_read(8) | 0x80); | ||
70 | |||
71 | #endif | ||
72 | } | ||
73 | |||
74 | #ifdef HAVE_RTC_ALARM | ||
75 | |||
76 | /* check whether the unit has been started by the RTC alarm function */ | ||
77 | /* (check for AF, which => started using wakeup alarm) */ | ||
78 | bool rtc_check_alarm_started(bool release_alarm) | ||
79 | { | ||
80 | static bool alarm_state, run_before; | ||
81 | bool rc; | ||
82 | |||
83 | if (run_before) { | ||
84 | rc = alarm_state; | ||
85 | alarm_state &= ~release_alarm; | ||
86 | } else { | ||
87 | /* This call resets AF, so we store the state for later recall */ | ||
88 | rc = alarm_state = rtc_check_alarm_flag(); | ||
89 | run_before = true; | ||
90 | } | ||
91 | |||
92 | return rc; | ||
93 | } | ||
94 | /* | ||
95 | * Checks the AL register. This call resets AL once read. | ||
96 | * | ||
97 | * We're only interested if ABE is set. AL is still raised regardless | ||
98 | * even if the unit is off when the alarm occurs. | ||
99 | */ | ||
100 | bool rtc_check_alarm_flag(void) | ||
101 | { | ||
102 | return ( ( (rtc_read(0x0f) & 0x40) != 0) && | ||
103 | (rtc_read(0x0a) & 0x20) ); | ||
104 | } | ||
105 | |||
106 | /* set alarm time registers to the given time (repeat once per day) */ | ||
107 | void rtc_set_alarm(int h, int m) | ||
108 | { | ||
109 | unsigned char data; | ||
110 | |||
111 | /* for daily alarm, RPT5=RPT4=on, RPT1=RPT2=RPT3=off */ | ||
112 | |||
113 | rtc_write(0x0e, 0x00); /* seconds 0 and RTP1 */ | ||
114 | rtc_write(0x0d, DEC2BCD(m)); /* minutes and RPT2 */ | ||
115 | rtc_write(0x0c, DEC2BCD(h)); /* hour and RPT3 */ | ||
116 | rtc_write(0x0b, 0xc1); /* set date 01 and RPT4 and RTP5 */ | ||
117 | |||
118 | /* set month to 1, if it's invalid, the rtc does an alarm every second instead */ | ||
119 | data = rtc_read(0x0a); | ||
120 | data &= 0xe0; | ||
121 | data |= 0x01; | ||
122 | rtc_write(0x0a, data); | ||
123 | } | ||
124 | |||
125 | /* read out the current alarm time */ | ||
126 | void rtc_get_alarm(int *h, int *m) | ||
127 | { | ||
128 | unsigned char data; | ||
129 | |||
130 | data = rtc_read(0x0c); | ||
131 | *h = BCD2DEC(data & 0x3f); | ||
132 | |||
133 | data = rtc_read(0x0d); | ||
134 | *m = BCD2DEC(data & 0x7f); | ||
135 | } | ||
136 | |||
137 | /* turn alarm on or off by setting the alarm flag enable */ | ||
138 | /* the alarm is automatically disabled when the RTC gets Vcc power at startup */ | ||
139 | /* avoid that an alarm occurs when the device is on because this locks the ON key forever */ | ||
140 | void rtc_enable_alarm(bool enable) | ||
141 | { | ||
142 | unsigned char data = rtc_read(0x0a); | ||
143 | if (enable) | ||
144 | { | ||
145 | data |= 0xa0; /* turn bit d7=AFE and d5=ABE on */ | ||
146 | } | ||
147 | else | ||
148 | data &= 0x5f; /* turn bit d7=AFE and d5=ABE off */ | ||
149 | rtc_write(0x0a, data); | ||
150 | |||
151 | /* check if alarm flag AF is off (as it should be) */ | ||
152 | /* in some cases enabling the alarm results in an activated AF flag */ | ||
153 | /* this should not happen, but it does */ | ||
154 | /* if you know why, tell me! */ | ||
155 | /* for now, we try again forever in this case */ | ||
156 | while (rtc_check_alarm_flag()) /* on */ | ||
157 | { | ||
158 | data &= 0x5f; /* turn bit d7=AFE and d5=ABE off */ | ||
159 | rtc_write(0x0a, data); | ||
160 | sleep(HZ / 10); | ||
161 | rtc_check_alarm_flag(); | ||
162 | data |= 0xa0; /* turn bit d7=AFE and d5=ABE on */ | ||
163 | rtc_write(0x0a, data); | ||
164 | } | ||
165 | } | ||
166 | |||
167 | #endif /* HAVE_RTC_ALARM */ | ||
168 | |||
169 | int rtc_write(unsigned char address, unsigned char value) | ||
170 | { | ||
171 | int ret = 0; | ||
172 | unsigned char buf[2]; | ||
173 | |||
174 | i2c_begin(); | ||
175 | |||
176 | buf[0] = address; | ||
177 | buf[1] = value; | ||
178 | |||
179 | /* send run command */ | ||
180 | if (i2c_write(RTC_DEV_WRITE,buf,2)) | ||
181 | { | ||
182 | ret = -1; | ||
183 | } | ||
184 | |||
185 | i2c_end(); | ||
186 | return ret; | ||
187 | } | ||
188 | |||
189 | int rtc_read(unsigned char address) | ||
190 | { | ||
191 | int value = -1; | ||
192 | unsigned char buf[1]; | ||
193 | |||
194 | i2c_begin(); | ||
195 | |||
196 | buf[0] = address; | ||
197 | |||
198 | /* send read command */ | ||
199 | if (i2c_write(RTC_DEV_READ,buf,1) >= 0) | ||
200 | { | ||
201 | i2c_start(); | ||
202 | i2c_outb(RTC_DEV_READ); | ||
203 | if (i2c_getack()) | ||
204 | { | ||
205 | value = i2c_inb(1); | ||
206 | } | ||
207 | } | ||
208 | |||
209 | i2c_stop(); | ||
210 | |||
211 | i2c_end(); | ||
212 | return value; | ||
213 | } | ||
214 | |||
215 | int rtc_read_multiple(unsigned char address, unsigned char *buf, int numbytes) | ||
216 | { | ||
217 | int ret = 0; | ||
218 | unsigned char obuf[1]; | ||
219 | int i; | ||
220 | |||
221 | i2c_begin(); | ||
222 | |||
223 | obuf[0] = address; | ||
224 | |||
225 | /* send read command */ | ||
226 | if (i2c_write(RTC_DEV_READ, obuf, 1) >= 0) | ||
227 | { | ||
228 | i2c_start(); | ||
229 | i2c_outb(RTC_DEV_READ); | ||
230 | if (i2c_getack()) | ||
231 | { | ||
232 | for(i = 0;i < numbytes-1;i++) | ||
233 | buf[i] = i2c_inb(0); | ||
234 | |||
235 | buf[i] = i2c_inb(1); | ||
236 | } | ||
237 | else | ||
238 | { | ||
239 | ret = -1; | ||
240 | } | ||
241 | } | ||
242 | |||
243 | i2c_stop(); | ||
244 | |||
245 | i2c_end(); | ||
246 | return ret; | ||
247 | } | ||
248 | |||
249 | int rtc_read_datetime(struct tm *tm) | ||
250 | { | ||
251 | int rc; | ||
252 | unsigned char buf[7]; | ||
253 | |||
254 | rc = rtc_read_multiple(1, buf, sizeof(buf)); | ||
255 | |||
256 | /* convert from bcd, avoid getting extra bits */ | ||
257 | tm->tm_sec = BCD2DEC(buf[0] & 0x7f); | ||
258 | tm->tm_min = BCD2DEC(buf[1] & 0x7f); | ||
259 | tm->tm_hour = BCD2DEC(buf[2] & 0x3f); | ||
260 | tm->tm_mday = BCD2DEC(buf[4] & 0x3f); | ||
261 | tm->tm_mon = BCD2DEC(buf[5] & 0x1f) - 1; | ||
262 | tm->tm_year = BCD2DEC(buf[6]) + 100; | ||
263 | tm->tm_yday = 0; /* Not implemented for now */ | ||
264 | |||
265 | set_day_of_week(tm); | ||
266 | |||
267 | return rc; | ||
268 | } | ||
269 | |||
270 | int rtc_write_datetime(const struct tm *tm) | ||
271 | { | ||
272 | unsigned int i; | ||
273 | int rc = 0; | ||
274 | unsigned char buf[7]; | ||
275 | |||
276 | buf[0] = tm->tm_sec; | ||
277 | buf[1] = tm->tm_min; | ||
278 | buf[2] = tm->tm_hour; | ||
279 | buf[3] = tm->tm_wday; | ||
280 | buf[4] = tm->tm_mday; | ||
281 | buf[5] = tm->tm_mon + 1; | ||
282 | buf[6] = tm->tm_year - 100; | ||
283 | |||
284 | /* Adjust weekday */ | ||
285 | if (buf[3] == 0) | ||
286 | buf[3] = 7; | ||
287 | |||
288 | for (i = 0; i < sizeof(buf) ;i++) | ||
289 | { | ||
290 | rc |= rtc_write(i + 1, DEC2BCD(buf[i])); | ||
291 | } | ||
292 | rc |= rtc_write(8, 0x80); /* Out=1, calibration = 0 */ | ||
293 | |||
294 | return rc; | ||
295 | } | ||
296 | |||