diff options
author | Jens Arnold <amiconn@rockbox.org> | 2006-06-16 17:34:18 +0000 |
---|---|---|
committer | Jens Arnold <amiconn@rockbox.org> | 2006-06-16 17:34:18 +0000 |
commit | 977169ea7af37e8e4617a67a84874bb98d07b070 (patch) | |
tree | 2d6f28e11682b2788dde041fa03cd198ab44fcde /firmware/crt0.S | |
parent | cd69996450ab847fe3014c3a3c701173e36997fe (diff) | |
download | rockbox-977169ea7af37e8e4617a67a84874bb98d07b070.tar.gz rockbox-977169ea7af37e8e4617a67a84874bb98d07b070.zip |
H300: Rudimentary driver for the ISP1362 USB on-the-go controller. For now it just sends the chip to sleep, solving the poor battery runtime issue.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@10128 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/crt0.S')
-rw-r--r-- | firmware/crt0.S | 13 |
1 files changed, 11 insertions, 2 deletions
diff --git a/firmware/crt0.S b/firmware/crt0.S index e8ccede187..7594416c06 100644 --- a/firmware/crt0.S +++ b/firmware/crt0.S | |||
@@ -531,7 +531,7 @@ irq_handler: | |||
531 | /* Chip select 1 - LCD controller */ | 531 | /* Chip select 1 - LCD controller */ |
532 | move.l #0xf0000000,%d0 /* CSAR1 - Base = 0xf0000000 */ | 532 | move.l #0xf0000000,%d0 /* CSAR1 - Base = 0xf0000000 */ |
533 | move.l %d0,(0x08c,%a0) | 533 | move.l %d0,(0x08c,%a0) |
534 | moveq.l #0x1,%d0 /* CSMR1 - 64K */ | 534 | moveq.l #0x1,%d0 /* CSMR1 - 64K */ |
535 | move.l %d0,(0x090,%a0) | 535 | move.l %d0,(0x090,%a0) |
536 | move.l #0x00000180,%d0 /* CSCR1 - no wait states, 16 bits, no bursts */ | 536 | move.l #0x00000180,%d0 /* CSCR1 - no wait states, 16 bits, no bursts */ |
537 | move.l %d0,(0x094,%a0) | 537 | move.l %d0,(0x094,%a0) |
@@ -545,7 +545,16 @@ irq_handler: | |||
545 | move.l %d0,(0x0a0,%a0) /* NOTE: I'm not sure about the wait states. | 545 | move.l %d0,(0x0a0,%a0) /* NOTE: I'm not sure about the wait states. |
546 | We have to be careful with the access times, | 546 | We have to be careful with the access times, |
547 | since IORDY isn't connected to the HDD. */ | 547 | since IORDY isn't connected to the HDD. */ |
548 | 548 | ||
549 | #if CONFIG_USBOTG == USBOTG_ISP1362 | ||
550 | /* Chip select 3 - USBOTG controller */ | ||
551 | move.l #0xc0000000,%d0 /* CSAR3 - Base = 0xc0000000 */ | ||
552 | move.l %d0,(0x0a4,%a0) | ||
553 | moveq.l #0x1,%d0 /* CSMR3 - 64K */ | ||
554 | move.l %d0,(0x0a8,%a0) | ||
555 | move.l #0x00000180,%d0 /* CSCR3 - no wait states, 16 bits, no bursts */ | ||
556 | move.l %d0,(0x0ac,%a0) | ||
557 | #endif | ||
549 | 558 | ||
550 | #ifdef BOOTLOADER | 559 | #ifdef BOOTLOADER |
551 | /* The cookie is not reset. This must mean that the boot loader | 560 | /* The cookie is not reset. This must mean that the boot loader |