diff options
author | Jens Arnold <amiconn@rockbox.org> | 2006-06-16 17:34:18 +0000 |
---|---|---|
committer | Jens Arnold <amiconn@rockbox.org> | 2006-06-16 17:34:18 +0000 |
commit | 977169ea7af37e8e4617a67a84874bb98d07b070 (patch) | |
tree | 2d6f28e11682b2788dde041fa03cd198ab44fcde | |
parent | cd69996450ab847fe3014c3a3c701173e36997fe (diff) | |
download | rockbox-977169ea7af37e8e4617a67a84874bb98d07b070.tar.gz rockbox-977169ea7af37e8e4617a67a84874bb98d07b070.zip |
H300: Rudimentary driver for the ISP1362 USB on-the-go controller. For now it just sends the chip to sleep, solving the poor battery runtime issue.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@10128 a1c6a512-1295-4272-9138-f99709370657
-rw-r--r-- | apps/main.c | 7 | ||||
-rw-r--r-- | firmware/SOURCES | 4 | ||||
-rw-r--r-- | firmware/crt0.S | 13 | ||||
-rwxr-xr-x | firmware/drivers/isp1362.c | 177 | ||||
-rw-r--r-- | firmware/export/config-h300.h | 3 | ||||
-rw-r--r-- | firmware/export/config.h | 4 | ||||
-rwxr-xr-x | firmware/export/isp1362.h | 134 | ||||
-rw-r--r-- | firmware/system.c | 20 |
8 files changed, 355 insertions, 7 deletions
diff --git a/apps/main.c b/apps/main.c index 7bfc438cfd..d6e3c342c9 100644 --- a/apps/main.c +++ b/apps/main.c | |||
@@ -88,6 +88,10 @@ | |||
88 | #include "lcd-remote.h" | 88 | #include "lcd-remote.h" |
89 | #endif | 89 | #endif |
90 | 90 | ||
91 | #if CONFIG_USBOTG == USBOTG_ISP1362 | ||
92 | #include "isp1362.h" | ||
93 | #endif | ||
94 | |||
91 | /*#define AUTOROCK*/ /* define this to check for "autostart.rock" on boot */ | 95 | /*#define AUTOROCK*/ /* define this to check for "autostart.rock" on boot */ |
92 | 96 | ||
93 | const char appsversion[]=APPSVERSION; | 97 | const char appsversion[]=APPSVERSION; |
@@ -276,6 +280,9 @@ void init(void) | |||
276 | adc_init(); | 280 | adc_init(); |
277 | 281 | ||
278 | usb_init(); | 282 | usb_init(); |
283 | #if CONFIG_USBOTG == USBOTG_ISP1362 | ||
284 | isp1362_init(); | ||
285 | #endif | ||
279 | 286 | ||
280 | backlight_init(); | 287 | backlight_init(); |
281 | 288 | ||
diff --git a/firmware/SOURCES b/firmware/SOURCES index 07f4ffd796..d6765ef627 100644 --- a/firmware/SOURCES +++ b/firmware/SOURCES | |||
@@ -203,6 +203,10 @@ sound.c | |||
203 | common/sscanf.c | 203 | common/sscanf.c |
204 | usb_serial.c | 204 | usb_serial.c |
205 | #endif | 205 | #endif |
206 | #if CONFIG_USBOTG == USBOTG_ISP1362 | ||
207 | drivers/isp1362.c | ||
208 | #endif | ||
209 | |||
206 | 210 | ||
207 | #ifndef SIMULATOR | 211 | #ifndef SIMULATOR |
208 | #ifdef IAUDIO_X5 | 212 | #ifdef IAUDIO_X5 |
diff --git a/firmware/crt0.S b/firmware/crt0.S index e8ccede187..7594416c06 100644 --- a/firmware/crt0.S +++ b/firmware/crt0.S | |||
@@ -531,7 +531,7 @@ irq_handler: | |||
531 | /* Chip select 1 - LCD controller */ | 531 | /* Chip select 1 - LCD controller */ |
532 | move.l #0xf0000000,%d0 /* CSAR1 - Base = 0xf0000000 */ | 532 | move.l #0xf0000000,%d0 /* CSAR1 - Base = 0xf0000000 */ |
533 | move.l %d0,(0x08c,%a0) | 533 | move.l %d0,(0x08c,%a0) |
534 | moveq.l #0x1,%d0 /* CSMR1 - 64K */ | 534 | moveq.l #0x1,%d0 /* CSMR1 - 64K */ |
535 | move.l %d0,(0x090,%a0) | 535 | move.l %d0,(0x090,%a0) |
536 | move.l #0x00000180,%d0 /* CSCR1 - no wait states, 16 bits, no bursts */ | 536 | move.l #0x00000180,%d0 /* CSCR1 - no wait states, 16 bits, no bursts */ |
537 | move.l %d0,(0x094,%a0) | 537 | move.l %d0,(0x094,%a0) |
@@ -545,7 +545,16 @@ irq_handler: | |||
545 | move.l %d0,(0x0a0,%a0) /* NOTE: I'm not sure about the wait states. | 545 | move.l %d0,(0x0a0,%a0) /* NOTE: I'm not sure about the wait states. |
546 | We have to be careful with the access times, | 546 | We have to be careful with the access times, |
547 | since IORDY isn't connected to the HDD. */ | 547 | since IORDY isn't connected to the HDD. */ |
548 | 548 | ||
549 | #if CONFIG_USBOTG == USBOTG_ISP1362 | ||
550 | /* Chip select 3 - USBOTG controller */ | ||
551 | move.l #0xc0000000,%d0 /* CSAR3 - Base = 0xc0000000 */ | ||
552 | move.l %d0,(0x0a4,%a0) | ||
553 | moveq.l #0x1,%d0 /* CSMR3 - 64K */ | ||
554 | move.l %d0,(0x0a8,%a0) | ||
555 | move.l #0x00000180,%d0 /* CSCR3 - no wait states, 16 bits, no bursts */ | ||
556 | move.l %d0,(0x0ac,%a0) | ||
557 | #endif | ||
549 | 558 | ||
550 | #ifdef BOOTLOADER | 559 | #ifdef BOOTLOADER |
551 | /* The cookie is not reset. This must mean that the boot loader | 560 | /* The cookie is not reset. This must mean that the boot loader |
diff --git a/firmware/drivers/isp1362.c b/firmware/drivers/isp1362.c new file mode 100755 index 0000000000..473c9dc3db --- /dev/null +++ b/firmware/drivers/isp1362.c | |||
@@ -0,0 +1,177 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2006 Jens Arnold | ||
11 | * | ||
12 | * All files in this archive are subject to the GNU General Public License. | ||
13 | * See the file COPYING in the source tree root for full license agreement. | ||
14 | * | ||
15 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
16 | * KIND, either express or implied. | ||
17 | * | ||
18 | ****************************************************************************/ | ||
19 | |||
20 | #include "system.h" | ||
21 | #include "kernel.h" | ||
22 | #include "isp1362.h" | ||
23 | |||
24 | #define HC_DATA (*((volatile unsigned short*)0xc0000000)) | ||
25 | #define HC_CMD (*((volatile unsigned short*)0xc0000002)) | ||
26 | #define DC_DATA (*((volatile unsigned short*)0xc0000004)) | ||
27 | #define DC_CMD (*((volatile unsigned short*)0xc0000006)) | ||
28 | |||
29 | /* host controller access */ | ||
30 | |||
31 | unsigned isp1362_read_hc_reg16(unsigned reg) | ||
32 | { | ||
33 | HC_CMD = reg; | ||
34 | |||
35 | asm ("nop\n nop\n nop\n nop\n"); | ||
36 | asm ("nop\n nop\n nop\n nop\n"); | ||
37 | asm ("nop\n nop\n nop\n nop\n"); | ||
38 | |||
39 | return HC_DATA; | ||
40 | } | ||
41 | |||
42 | unsigned isp1362_read_hc_reg32(unsigned reg) | ||
43 | { | ||
44 | unsigned data; | ||
45 | |||
46 | HC_CMD = reg; | ||
47 | |||
48 | asm ("nop\n nop\n nop\n nop\n"); | ||
49 | asm ("nop\n nop\n nop\n nop\n"); | ||
50 | asm ("nop\n nop\n nop\n nop\n"); | ||
51 | |||
52 | data = HC_DATA; | ||
53 | data |= HC_DATA << 16; | ||
54 | return data; | ||
55 | } | ||
56 | |||
57 | void isp1362_write_hc_reg16(unsigned reg, unsigned data) | ||
58 | { | ||
59 | HC_CMD = reg | 0x80; | ||
60 | |||
61 | asm ("nop\n nop\n nop\n"); | ||
62 | |||
63 | HC_DATA = data; | ||
64 | } | ||
65 | |||
66 | void isp1362_write_hc_reg32(unsigned reg, unsigned data) | ||
67 | { | ||
68 | HC_CMD = reg | 0x80; | ||
69 | |||
70 | asm ("nop\n nop\n nop\n"); | ||
71 | |||
72 | HC_DATA = data; | ||
73 | HC_DATA = data >> 16; | ||
74 | } | ||
75 | |||
76 | /* device controller access */ | ||
77 | |||
78 | unsigned isp1362_read_dc_reg16(unsigned reg) | ||
79 | { | ||
80 | DC_CMD = reg; | ||
81 | |||
82 | asm ("nop\n nop\n nop\n nop\n"); | ||
83 | asm ("nop\n nop\n nop\n nop\n"); | ||
84 | asm ("nop\n nop\n nop\n nop\n"); | ||
85 | |||
86 | return DC_DATA; | ||
87 | } | ||
88 | |||
89 | unsigned isp1362_read_dc_reg32(unsigned reg) | ||
90 | { | ||
91 | unsigned data; | ||
92 | |||
93 | DC_CMD = reg; | ||
94 | |||
95 | asm ("nop\n nop\n nop\n nop\n"); | ||
96 | asm ("nop\n nop\n nop\n nop\n"); | ||
97 | asm ("nop\n nop\n nop\n nop\n"); | ||
98 | |||
99 | data = DC_DATA; | ||
100 | data |= DC_DATA << 16; | ||
101 | return data; | ||
102 | } | ||
103 | |||
104 | void isp1362_write_dc_reg16(unsigned reg, unsigned data) | ||
105 | { | ||
106 | DC_CMD = reg; | ||
107 | |||
108 | asm ("nop\n nop\n nop\n"); | ||
109 | |||
110 | DC_DATA = data; | ||
111 | } | ||
112 | |||
113 | void isp1362_write_dc_reg32(unsigned reg, unsigned data) | ||
114 | { | ||
115 | DC_CMD = reg; | ||
116 | |||
117 | asm ("nop\n nop\n nop\n"); | ||
118 | |||
119 | DC_DATA = data; | ||
120 | DC_DATA = data >> 16; | ||
121 | } | ||
122 | |||
123 | static void isp1362_suspend(void) | ||
124 | { | ||
125 | unsigned data; | ||
126 | |||
127 | data = isp1362_read_hc_reg16(ISP1362_OTG_CONTROL); | ||
128 | data &= ~0x0001; /* DRV_VBUS = 0 */ | ||
129 | isp1362_write_hc_reg16(ISP1362_OTG_CONTROL, data); | ||
130 | |||
131 | /* prepare the DC */ | ||
132 | data = isp1362_read_dc_reg16(ISP1362_DC_HARDWARE_CONFIG_R); | ||
133 | data &= ~0x1008; /* CLKRUN = WKUPCS = 0. Wakeup is still possible via /D_WAKEUP */ | ||
134 | isp1362_write_dc_reg16(ISP1362_DC_HARDWARE_CONFIG_W, data); | ||
135 | |||
136 | /* send the DC to sleep */ | ||
137 | data = isp1362_read_dc_reg16(ISP1362_DC_MODE_R); | ||
138 | data |= 0x20; /* GOSUSP = 1 */ | ||
139 | isp1362_write_dc_reg16(ISP1362_DC_MODE_W, data); | ||
140 | data &= ~0x20; /* GOSUSP = 0 */ | ||
141 | isp1362_write_dc_reg16(ISP1362_DC_MODE_W, data); | ||
142 | |||
143 | /* prepare the HC */ | ||
144 | data = isp1362_read_hc_reg16(ISP1362_HC_HARDWARE_CONFIG); | ||
145 | data &= ~0x0800; /* SuspendClkNotStop = 0 */ | ||
146 | data |= 0x4001; /* GlobalPowerDown = InterruptPinEnable = 1 */ | ||
147 | isp1362_write_hc_reg16(ISP1362_HC_HARDWARE_CONFIG, data); | ||
148 | |||
149 | /* TODO: OTG wake-up cfg */ | ||
150 | /* TODO: Interrupt setup */ | ||
151 | |||
152 | /* set the HC to operational */ | ||
153 | isp1362_write_hc_reg32(ISP1362_HC_CONTROL, 0x0680); | ||
154 | /* RWE = RWC = 1, HCFS = 0b10 (USBOperational) */ | ||
155 | /* ..then send it to sleep */ | ||
156 | isp1362_write_hc_reg32(ISP1362_HC_CONTROL, 0x06c0); | ||
157 | /* RWE = RWC = 1, HCFS = 0b11 (USBSuspend) */ | ||
158 | } | ||
159 | |||
160 | /* init */ | ||
161 | |||
162 | void isp1362_init(void) | ||
163 | { | ||
164 | and_l(~0x00200080, &GPIO1_OUT); /* disable 5V USB host power and ??? */ | ||
165 | or_l( 0x00200080, &GPIO1_ENABLE); | ||
166 | or_l( 0x00200080, &GPIO1_FUNCTION); | ||
167 | |||
168 | or_l( 0x20600000, &GPIO_OUT); /* ID = D_SUSPEND = /OTGMODE = 1 */ | ||
169 | and_l(~0x04000000, &GPIO_OUT); /* ?R26? = 0 */ | ||
170 | or_l( 0x24600000, &GPIO_ENABLE); /* ID, ?R26?, D_SUSPEND, /OTGMODE outputs */ | ||
171 | and_l(~0x000000a8, &GPIO_ENABLE); /* /INT2, /INT1, /RESET inputs */ | ||
172 | or_l( 0x246000a8, &GPIO_FUNCTION); /* GPIO for these pins */ | ||
173 | |||
174 | sleep(HZ/5); | ||
175 | |||
176 | isp1362_suspend(); | ||
177 | } | ||
diff --git a/firmware/export/config-h300.h b/firmware/export/config-h300.h index 7ed54958ca..30cca21253 100644 --- a/firmware/export/config-h300.h +++ b/firmware/export/config-h300.h | |||
@@ -110,6 +110,9 @@ | |||
110 | 110 | ||
111 | #define USB_IRIVERSTYLE | 111 | #define USB_IRIVERSTYLE |
112 | 112 | ||
113 | /* USB On-the-go */ | ||
114 | #define CONFIG_USBOTG USBOTG_ISP1362 | ||
115 | |||
113 | /* Define this if you have adjustable CPU frequency */ | 116 | /* Define this if you have adjustable CPU frequency */ |
114 | #define HAVE_ADJUSTABLE_CPU_FREQ | 117 | #define HAVE_ADJUSTABLE_CPU_FREQ |
115 | 118 | ||
diff --git a/firmware/export/config.h b/firmware/export/config.h index 910aeca4eb..a1327558ed 100644 --- a/firmware/export/config.h +++ b/firmware/export/config.h | |||
@@ -122,6 +122,7 @@ | |||
122 | /* CONFIG_LED */ | 122 | /* CONFIG_LED */ |
123 | #define LED_REAL 1 /* SW controlled LED (Archos recorders, player, Gmini) */ | 123 | #define LED_REAL 1 /* SW controlled LED (Archos recorders, player, Gmini) */ |
124 | #define LED_VIRTUAL 2 /* Virtual LED (icon) (Archos Ondio) */ | 124 | #define LED_VIRTUAL 2 /* Virtual LED (icon) (Archos Ondio) */ |
125 | /* else HW controlled LED (iRiver H1x0) */ | ||
125 | 126 | ||
126 | /* CONFIG_FLASH */ | 127 | /* CONFIG_FLASH */ |
127 | #define FLASH_IFP7XX 1 | 128 | #define FLASH_IFP7XX 1 |
@@ -132,7 +133,8 @@ | |||
132 | #define RTC_PCF50606 3 /* iriver H300 */ | 133 | #define RTC_PCF50606 3 /* iriver H300 */ |
133 | #define RTC_S3C2440 4 | 134 | #define RTC_S3C2440 4 |
134 | 135 | ||
135 | /* else HW controlled LED (iRiver H1x0) */ | 136 | /* USB On-the-go */ |
137 | #define USBOTG_ISP1362 1362 | ||
136 | 138 | ||
137 | /* now go and pick yours */ | 139 | /* now go and pick yours */ |
138 | #if defined(ARCHOS_PLAYER) | 140 | #if defined(ARCHOS_PLAYER) |
diff --git a/firmware/export/isp1362.h b/firmware/export/isp1362.h new file mode 100755 index 0000000000..cba693e4f0 --- /dev/null +++ b/firmware/export/isp1362.h | |||
@@ -0,0 +1,134 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2006 Jens Arnold | ||
11 | * | ||
12 | * All files in this archive are subject to the GNU General Public License. | ||
13 | * See the file COPYING in the source tree root for full license agreement. | ||
14 | * | ||
15 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
16 | * KIND, either express or implied. | ||
17 | * | ||
18 | ****************************************************************************/ | ||
19 | |||
20 | unsigned isp1362_read_hc_reg16(unsigned reg); | ||
21 | unsigned isp1362_read_hc_reg32(unsigned reg); | ||
22 | void isp1362_write_hc_reg16(unsigned reg, unsigned data); | ||
23 | void isp1362_write_hc_reg32(unsigned reg, unsigned data); | ||
24 | |||
25 | #define ISP1362_OTG_CONTROL 0x62 | ||
26 | #define ISP1362_OTG_STATUS 0x67 /* read only */ | ||
27 | #define ISP1362_OTG_INTERRUPT 0x68 | ||
28 | #define ISP1362_OTG_INT_ENABLE 0x69 | ||
29 | #define ISP1362_OTG_TIMER 0x6a | ||
30 | #define ISP1362_OTG_ALT_TIMER 0x6c | ||
31 | |||
32 | #define ISP1362_HC_REVISION 0x00 /* read only */ | ||
33 | #define ISP1362_HC_CONTROL 0x01 | ||
34 | #define ISP1362_HC_COMMAND_STATUS 0x02 | ||
35 | #define ISP1362_HC_INT_STATUS 0x03 | ||
36 | #define ISP1362_HC_INT_ENABLE 0x04 | ||
37 | #define ISP1362_HC_INT_DISABLE 0x05 | ||
38 | #define ISP1362_HC_FM_INTERVAL 0x0d | ||
39 | #define ISP1362_HC_FM_REMAINING 0x0e | ||
40 | #define ISP1362_HC_FM_NUMBER 0x0f | ||
41 | #define ISP1362_HC_LS_THRESHOLD 0x11 | ||
42 | #define ISP1362_HC_RH_DESCRIPTOR_A 0x12 | ||
43 | #define ISP1362_HC_RH_DESCRIPTOR_B 0x13 | ||
44 | #define ISP1362_HC_RH_STATUS 0x14 | ||
45 | #define ISP1362_HC_RH_PORT_STATUS1 0x15 | ||
46 | #define ISP1362_HC_RH_PORT_STATUS2 0x16 | ||
47 | #define ISP1362_HC_HARDWARE_CONFIG 0x20 | ||
48 | #define ISP1362_HC_DMA_CONFIG 0x21 | ||
49 | #define ISP1362_HC_TRANSFER_COUNTER 0x22 | ||
50 | #define ISP1362_HC_UP_INTERRUPT 0x24 | ||
51 | #define ISP1362_HC_UP_INT_ENABLE 0x25 | ||
52 | #define ISP1362_HC_CHIP_ID 0x27 /* read only */ | ||
53 | #define ISP1362_HC_SCRATCH 0x28 | ||
54 | #define ISP1362_HC_SOFTWARE_RESET 0x29 /* write only */ | ||
55 | #define ISP1362_HC_BUFFER_STATUS 0x2c | ||
56 | #define ISP1362_HC_DIRECT_ADDR_LEN 0x32 | ||
57 | #define ISP1362_HC_DIRECT_ADDR_DATA 0x45 | ||
58 | #define ISP1362_HC_ISTL_BUF_SIZE 0x30 | ||
59 | #define ISP1362_HC_ISTL0_BUF_PORT 0x40 | ||
60 | #define ISP1362_HC_ISTL1_BUF_PORT 0x42 | ||
61 | #define ISP1362_HC_ISTL_TOGGLE_RATE 0x47 | ||
62 | #define ISP1362_HC_INTL_BUF_SIZE 0x33 | ||
63 | #define ISP1362_HC_INTL_BUF_PORT 0x43 | ||
64 | #define ISP1362_HC_INTL_BLK_SIZE 0x53 | ||
65 | #define ISP1362_HC_INTL_PRD_DONE_MAP 0x17 /* read only */ | ||
66 | #define ISP1362_HC_INTL_PTD_SKIP_MAP 0x18 | ||
67 | #define ISP1362_HC_INTL_LAST_PTD 0x19 | ||
68 | #define ISP1362_HC_INTL_CUR_ACT_PTD 0x1a /* read only */ | ||
69 | #define ISP1362_HC_ATL_BUF_SIZE 0x34 | ||
70 | #define ISP1362_HC_ATL_BUF_PORT 0x44 | ||
71 | #define ISP1362_HC_ATL_BLK_SIZE 0x54 | ||
72 | #define ISP1362_HC_ATL_PTD_DONE_MAP 0x1b /* read only */ | ||
73 | #define ISP1362_HC_ATL_PTD_SKIP_MAP 0x1c | ||
74 | #define ISP1362_HC_ATL_LAST_PTD 0x1d | ||
75 | #define ISP1362_HC_ATL_CUR_ACT_PTD 0x1e /* read only */ | ||
76 | #define ISP1362_HC_ATL_PTD_DONE_THR_CNT 0x51 | ||
77 | #define ISP1362_HC_ATL_PTD_DONE_THR_TMO 0x52 | ||
78 | |||
79 | unsigned isp1362_read_dc_reg16(unsigned reg); | ||
80 | unsigned isp1362_read_dc_reg32(unsigned reg); | ||
81 | void isp1362_write_dc_reg16(unsigned reg, unsigned data); | ||
82 | void isp1362_write_dc_reg32(unsigned reg, unsigned data); | ||
83 | |||
84 | #define ISP1362_DC_CTRL_OUT_CFG_W 0x20 | ||
85 | #define ISP1362_DC_CTRL_IN_CFG_W 0x21 | ||
86 | #define ISP1362_DC_ENDPOINT_CFG_BASE_W 0x22 | ||
87 | #define ISP1362_DC_CTRL_OUT_CFG_R 0x30 | ||
88 | #define ISP1362_DC_CTRL_IN_CFG_R 0x31 | ||
89 | #define ISP1362_DC_ENDPOINT_CFG_BASE_R 0x32 | ||
90 | #define ISP1362_DC_ADDRESS_W 0xb6 | ||
91 | #define ISP1362_DC_ADDRESS_R 0xb7 | ||
92 | #define ISP1362_DC_MODE_W 0xb8 | ||
93 | #define ISP1362_DC_MODE_R 0xb9 | ||
94 | #define ISP1362_DC_HARDWARE_CONFIG_W 0xba | ||
95 | #define ISP1362_DC_HARDWARE_CONFIG_R 0xbb | ||
96 | #define ISP1362_DC_INT_ENABLE_W 0xc2 | ||
97 | #define ISP1362_DC_INT_ENABLE_R 0xc3 | ||
98 | #define ISP1362_DC_DMA_CONFIG_W 0xf0 | ||
99 | #define ISP1362_DC_DMA_CONFIG_R 0xf1 | ||
100 | #define ISP1362_DC_DMA_COUNTER_W 0xf2 | ||
101 | #define ISP1362_DC_DMA_COUNTER_R 0xf3 | ||
102 | #define ISP1362_DC_RESET 0xf6 | ||
103 | #define ISP1362_DC_CTRL_IN_BUF_W 0x01 | ||
104 | #define ISP1362_DC_ENDPOINT_BUF_BASE_W 0x02 | ||
105 | #define ISP1362_DC_CTRL_OUT_BUF_R 0x10 | ||
106 | #define ISP1362_DC_ENDPOINT_BUF_BASE_R 0x12 | ||
107 | #define ISP1362_DC_CTRL_OUT_STALL 0x40 | ||
108 | #define ISP1362_DC_CTRL_IN_STALL 0x41 | ||
109 | #define ISP1362_DC_ENDPOINT_STALL_BASE 0x42 | ||
110 | #define ISP1362_DC_CTRL_OUT_STATUS_R 0x50 | ||
111 | #define ISP1362_DC_CTRL_IN_STATUS_R 0x51 | ||
112 | #define ISP1362_DC_ENDPOINT_STATUS_BASE_R 0x52 | ||
113 | #define ISP1362_DC_CTRL_IN_VALIDATE 0x61 | ||
114 | #define ISP1362_DC_ENDPOINT_VALIDATE_BASE 0x62 | ||
115 | #define ISP1362_DC_CTRL_OUT_CLEAR 0x70 | ||
116 | #define ISP1362_DC_ENDPOINT_CLEAR_BASE 0x72 | ||
117 | #define ISP1362_DC_CTRL_OUT_UNSTALL 0x80 | ||
118 | #define ISP1362_DC_CTRL_IN_UNSTALL 0x81 | ||
119 | #define ISP1362_DC_ENDPOINT_UNSTALL_BASE 0x82 | ||
120 | #define ISP1362_DC_CTRL_OUT_STAT_IMG_R 0xd0 | ||
121 | #define ISP1362_DC_CTRL_IN_STAT_IMG_R 0xd1 | ||
122 | #define ISP1362_DC_ENDPOINT_STAT_IMG_BASE_R 0xd2 | ||
123 | #define ISP1362_DC_SETUP_ACK 0xf4 | ||
124 | #define ISP1362_DC_CTRL_OUT_ERROR_R 0xa0 | ||
125 | #define ISP1362_DC_CTRL_IN_ERROR_R 0xa1 | ||
126 | #define ISP1362_DC_ENDPOINT_ERROR_BASE_R 0xa2 | ||
127 | #define ISP1362_DC_UNLOCK_DEVICE 0xb0 | ||
128 | #define ISP1362_DC_SCRATCH_W 0xb2 | ||
129 | #define ISP1362_DC_SCRATCH_R 0xb3 | ||
130 | #define ISP1362_DC_FRAME_NUMBER_R 0xb4 | ||
131 | #define ISP1362_DC_CHIP_ID_R 0xb5 | ||
132 | #define ISP1362_DC_INTERRUPT_R 0xc0 | ||
133 | |||
134 | void isp1362_init(void); | ||
diff --git a/firmware/system.c b/firmware/system.c index 6e6408bf1b..af2b74a17a 100644 --- a/firmware/system.c +++ b/firmware/system.c | |||
@@ -616,13 +616,17 @@ void set_cpu_frequency(long frequency) | |||
616 | PLLCR = 0x11c56005; | 616 | PLLCR = 0x11c56005; |
617 | CSCR0 = 0x00001180; /* Flash: 4 wait states */ | 617 | CSCR0 = 0x00001180; /* Flash: 4 wait states */ |
618 | CSCR1 = 0x00000980; /* LCD: 2 wait states */ | 618 | CSCR1 = 0x00000980; /* LCD: 2 wait states */ |
619 | #if CONFIG_USBOTG == USBOTG_ISP1362 | ||
620 | CSCR3 = 0x00002180; /* USBOTG: 8 wait states */ | ||
621 | #endif | ||
619 | while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked. | 622 | while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked. |
620 | This may take up to 10ms! */ | 623 | This may take up to 10ms! */ |
621 | timers_adjust_prescale(CPUFREQ_MAX_MULT, true); | 624 | timers_adjust_prescale(CPUFREQ_MAX_MULT, true); |
622 | DCR = (0x8200 | MAX_REFRESH_TIMER); /* Refresh timer */ | 625 | DCR = (0x8200 | MAX_REFRESH_TIMER); /* Refresh timer */ |
623 | cpu_frequency = CPUFREQ_MAX; | 626 | cpu_frequency = CPUFREQ_MAX; |
624 | IDECONFIG1 = 0x106000 | (5 << 10); /* BUFEN2 enable + CS2Pre/CS2Post */ | 627 | IDECONFIG1 = 0x10100000 | (3 << 13) | (5 << 10); |
625 | IDECONFIG2 = 0x40000 | (1 << 8); /* TA enable + CS2wait */ | 628 | /* SRE active on write (H300 USBOTG) | BUFEN2 enable | CS2Post | CS2Pre */ |
629 | IDECONFIG2 = 0x40000 | (2 << 8); /* TA enable + CS2wait */ | ||
626 | break; | 630 | break; |
627 | 631 | ||
628 | case CPUFREQ_NORMAL: | 632 | case CPUFREQ_NORMAL: |
@@ -634,12 +638,16 @@ void set_cpu_frequency(long frequency) | |||
634 | PLLCR = 0x13c5e005; | 638 | PLLCR = 0x13c5e005; |
635 | CSCR0 = 0x00000580; /* Flash: 1 wait state */ | 639 | CSCR0 = 0x00000580; /* Flash: 1 wait state */ |
636 | CSCR1 = 0x00000180; /* LCD: 0 wait states */ | 640 | CSCR1 = 0x00000180; /* LCD: 0 wait states */ |
641 | #if CONFIG_USBOTG == USBOTG_ISP1362 | ||
642 | CSCR3 = 0x00000580; /* USBOTG: 1 wait state */ | ||
643 | #endif | ||
637 | while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked. | 644 | while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked. |
638 | This may take up to 10ms! */ | 645 | This may take up to 10ms! */ |
639 | timers_adjust_prescale(CPUFREQ_NORMAL_MULT, true); | 646 | timers_adjust_prescale(CPUFREQ_NORMAL_MULT, true); |
640 | DCR = (0x8000 | NORMAL_REFRESH_TIMER); /* Refresh timer */ | 647 | DCR = (0x8000 | NORMAL_REFRESH_TIMER); /* Refresh timer */ |
641 | cpu_frequency = CPUFREQ_NORMAL; | 648 | cpu_frequency = CPUFREQ_NORMAL; |
642 | IDECONFIG1 = 0x106000 | (5 << 10); /* BUFEN2 enable + CS2Pre/CS2Post */ | 649 | IDECONFIG1 = 0x10100000 | (3 << 13) | (5 << 10); |
650 | /* SRE active on write (H300 USBOTG) | BUFEN2 enable | CS2Post | CS2Pre */ | ||
643 | IDECONFIG2 = 0x40000 | (0 << 8); /* TA enable + CS2wait */ | 651 | IDECONFIG2 = 0x40000 | (0 << 8); /* TA enable + CS2wait */ |
644 | break; | 652 | break; |
645 | default: | 653 | default: |
@@ -651,9 +659,13 @@ void set_cpu_frequency(long frequency) | |||
651 | PLLCR = 0x10c00200; /* Power down PLL, but keep CLSEL and CRSEL */ | 659 | PLLCR = 0x10c00200; /* Power down PLL, but keep CLSEL and CRSEL */ |
652 | CSCR0 = 0x00000180; /* Flash: 0 wait states */ | 660 | CSCR0 = 0x00000180; /* Flash: 0 wait states */ |
653 | CSCR1 = 0x00000180; /* LCD: 0 wait states */ | 661 | CSCR1 = 0x00000180; /* LCD: 0 wait states */ |
662 | #if CONFIG_USBOTG == USBOTG_ISP1362 | ||
663 | CSCR3 = 0x00000180; /* USBOTG: 0 wait states */ | ||
664 | #endif | ||
654 | DCR = (0x8000 | DEFAULT_REFRESH_TIMER); /* Refresh timer */ | 665 | DCR = (0x8000 | DEFAULT_REFRESH_TIMER); /* Refresh timer */ |
655 | cpu_frequency = CPUFREQ_DEFAULT; | 666 | cpu_frequency = CPUFREQ_DEFAULT; |
656 | IDECONFIG1 = 0x106000 | (1 << 10); /* BUFEN2 enable + CS2Pre/CS2Post */ | 667 | IDECONFIG1 = 0x10100000 | (3 << 13) | (1 << 10); |
668 | /* SRE active on write (H300 USBOTG) | BUFEN2 enable | CS2Post | CS2Pre */ | ||
657 | IDECONFIG2 = 0x40000 | (0 << 8); /* TA enable + CS2wait */ | 669 | IDECONFIG2 = 0x40000 | (0 << 8); /* TA enable + CS2wait */ |
658 | break; | 670 | break; |
659 | } | 671 | } |