diff options
author | Marcin Bukat <marcin.bukat@gmail.com> | 2014-09-19 10:35:43 +0200 |
---|---|---|
committer | Marcin Bukat <marcin.bukat@gmail.com> | 2014-09-19 12:38:19 +0200 |
commit | f9be1ef021fe0b5b1e924474f51c4201e437738e (patch) | |
tree | 6147f8590ba69e8b3fe641e3f401a5c8c94e22eb | |
parent | b888743cac9c0af26632672796934fe9eaaa471d (diff) | |
download | rockbox-f9be1ef021fe0b5b1e924474f51c4201e437738e.tar.gz rockbox-f9be1ef021fe0b5b1e924474f51c4201e437738e.zip |
regtools: reg-rk27xx.xml description file rework and cleanup
Change-Id: I0a2e45eb1b4aa03122382cc93bbc0c292b3249be
-rw-r--r-- | utils/regtools/desc/regs-rk27xx.xml | 478 |
1 files changed, 381 insertions, 97 deletions
diff --git a/utils/regtools/desc/regs-rk27xx.xml b/utils/regtools/desc/regs-rk27xx.xml index fc866bc8bc..3fa87a518c 100644 --- a/utils/regtools/desc/regs-rk27xx.xml +++ b/utils/regtools/desc/regs-rk27xx.xml | |||
@@ -2,74 +2,167 @@ | |||
2 | <soc name="rk27xx" desc="Rockchip rk27xx"> | 2 | <soc name="rk27xx" desc="Rockchip rk27xx"> |
3 | <dev name="A2A_DMA" long_name="AHB-to-AHB bridge" desc="AHB-to-AHB bridge with DMA" version="1.0"> | 3 | <dev name="A2A_DMA" long_name="AHB-to-AHB bridge" desc="AHB-to-AHB bridge with DMA" version="1.0"> |
4 | <addr name="A2A_DMA" addr="0x18094000"/> | 4 | <addr name="A2A_DMA" addr="0x18094000"/> |
5 | <reg name="CON0" desc=""> | 5 | <reg name="CON" desc=""> |
6 | <addr name="CON0" addr="0x0"/> | 6 | <addr name="CON0" addr="0x0"/> |
7 | </reg> | ||
8 | <reg name="ISRC0" desc=""> | ||
9 | <addr name="ISRC0" addr="0x4"/> | ||
10 | </reg> | ||
11 | <reg name="IDST0" desc=""> | ||
12 | <addr name="IDST0" addr="0x8"/> | ||
13 | </reg> | ||
14 | <reg name="ICNT0" desc=""> | ||
15 | <addr name="ICNT0" addr="0xc"/> | ||
16 | </reg> | ||
17 | <reg name="CSRC0" desc=""> | ||
18 | <addr name="CSRC0" addr="0x10"/> | ||
19 | </reg> | ||
20 | <reg name="CDST0" desc=""> | ||
21 | <addr name="CDST0" addr="0x14"/> | ||
22 | </reg> | ||
23 | <reg name="CCNT0" desc=""> | ||
24 | <addr name="CCNT0" addr="0x18"/> | ||
25 | </reg> | ||
26 | <reg name="CON1" desc=""> | ||
27 | <addr name="CON1" addr="0x1c"/> | 7 | <addr name="CON1" addr="0x1c"/> |
8 | <field name="RESERVED31_15" desc="" bitrange="31:15"/> | ||
9 | <field name="AUTO_RELOAD" desc="" bitrange="14:14"> | ||
10 | <value name="DISABLE" value="0x0" desc=""/> | ||
11 | <value name="ENABLE" value="0x1" desc=""/> | ||
12 | </field> | ||
13 | <field name="DMA_HW_EN" desc="" bitrange="13:13"> | ||
14 | <value name="DISABLE" value="0x0" desc=""/> | ||
15 | <value name="ENABLE" value="0x1" desc=""/> | ||
16 | </field> | ||
17 | <field name="INT_EN" desc="" bitrange="12:12"> | ||
18 | <value name="DISABLE" value="0x0" desc=""/> | ||
19 | <value name="ENABLE" value="0x1" desc=""/> | ||
20 | </field> | ||
21 | <field name="ON_THE_FLY" desc="On the fly transfer can be applied on DMA which source and destination addresses are at the different bus domain. " bitrange="11:11"> | ||
22 | <value name="DISABLE" value="0x0" desc=""/> | ||
23 | <value name="ENABLE" value="0x1" desc=""/> | ||
24 | </field> | ||
25 | <field name="XFER_MODE" desc="Burst size" bitrange="10:9"> | ||
26 | <value name="SINGLE" value="0x0" desc=""/> | ||
27 | <value name="INCR4" value="0x1" desc=""/> | ||
28 | <value name="INCR8" value="0x2" desc=""/> | ||
29 | <value name="INCR16" value="0x3" desc=""/> | ||
30 | </field> | ||
31 | <field name="HDREQ_SRC" desc="" bitrange="8:7"> | ||
32 | <value name="SDMMC" value="0x0" desc=""/> | ||
33 | </field> | ||
34 | <field name="SRC_INC" desc="" bitrange="6:6"> | ||
35 | <value name="INCREMENT" value="0x0" desc=""/> | ||
36 | <value name="FIXED" value="0x1" desc=""/> | ||
37 | </field> | ||
38 | <field name="DST_INC" desc="" bitrange="5:5"> | ||
39 | <value name="INCREMENT" value="0x0" desc=""/> | ||
40 | <value name="FIXED" value="0x1" desc=""/> | ||
41 | </field> | ||
42 | <field name="DMA_SW_CMD" desc="" bitrange="4:3"> | ||
43 | <value name="NO_CMD" value="0x0" desc=""/> | ||
44 | <value name="START_SW_DMA" value="0x1" desc=""/> | ||
45 | <value name="PAUSE_SW_DMA" value="0x2" desc=""/> | ||
46 | <value name="CANCEL_SW_DMA" value="0x3" desc=""/> | ||
47 | </field> | ||
48 | <field name="XFER_WIDTH" desc="" bitrange="2:1"> | ||
49 | <value name="BYTE" value="0x0" desc=""/> | ||
50 | <value name="HALFWORD" value="0x1" desc=""/> | ||
51 | <value name="WORD" value="0x2" desc=""/> | ||
52 | <value name="RESERVED" value="0x3" desc=""/> | ||
53 | </field> | ||
54 | <field name="DMA_MODE" desc="" bitrange="0:0"> | ||
55 | <value name="HW_BLOCK_MODE" value="0x0" desc=""/> | ||
56 | <value name="SW_MODE" value="0x1" desc=""/> | ||
57 | </field> | ||
28 | </reg> | 58 | </reg> |
29 | <reg name="ISRC1" desc=""> | 59 | <reg name="ISRC" desc="A2A DMA initial source address register."> |
60 | <addr name="ISRC0" addr="0x4"/> | ||
30 | <addr name="ISRC1" addr="0x20"/> | 61 | <addr name="ISRC1" addr="0x20"/> |
31 | </reg> | 62 | </reg> |
32 | <reg name="IDST1" desc=""> | 63 | <reg name="IDST" desc="A2A DMA initial destination address register."> |
64 | <addr name="IDST0" addr="0x8"/> | ||
33 | <addr name="IDST1" addr="0x24"/> | 65 | <addr name="IDST1" addr="0x24"/> |
34 | </reg> | 66 | </reg> |
35 | <reg name="ICNT1" desc=""> | 67 | <reg name="ICNT" desc=""> |
68 | <addr name="ICNT0" addr="0xc"/> | ||
36 | <addr name="ICNT1" addr="0x28"/> | 69 | <addr name="ICNT1" addr="0x28"/> |
70 | <field name="RESERVED31_16" desc="" bitrange="31:16"/> | ||
71 | <field name="CNT" desc="DMA initial terminate count register for channel x." bitrange="15:0"/> | ||
37 | </reg> | 72 | </reg> |
38 | <reg name="CSRC1" desc=""> | 73 | <reg name="CSRC" desc="A2A DMA current source address register."> |
74 | <addr name="CSRC0" addr="0x10"/> | ||
39 | <addr name="CSRC1" addr="0x2c"/> | 75 | <addr name="CSRC1" addr="0x2c"/> |
40 | </reg> | 76 | </reg> |
41 | <reg name="CDST1" desc=""> | 77 | <reg name="CDST" desc="A2A DMA current destination address register."> |
78 | <addr name="CDST0" addr="0x14"/> | ||
42 | <addr name="CDST1" addr="0x30"/> | 79 | <addr name="CDST1" addr="0x30"/> |
43 | </reg> | 80 | </reg> |
44 | <reg name="CCNT1" desc=""> | 81 | <reg name="CCNT" desc=""> |
82 | <addr name="CCNT0" addr="0x18"/> | ||
45 | <addr name="CCNT1" addr="0x34"/> | 83 | <addr name="CCNT1" addr="0x34"/> |
84 | <field name="RESERVED31_16" desc="" bitrange="31:16"/> | ||
85 | <field name="CNT" desc="" bitrange="15:0"/> | ||
46 | </reg> | 86 | </reg> |
47 | <reg name="INT_STS" desc=""> | 87 | <reg name="INT_STS" desc=""> |
48 | <addr name="INT_STS" addr="0x38"/> | 88 | <addr name="INT_STS" addr="0x38"/> |
89 | <field name="RESERVED31_4" desc="" bitrange="31:4"/> | ||
90 | <field name="AHB2_ERR_INT" desc="" bitrange="3:3"> | ||
91 | <value name="NO_ERROR" value="0x0" desc=""/> | ||
92 | <value name="ERROR" value="0x1" desc=""/> | ||
93 | </field> | ||
94 | <field name="AHB1_ERR_INT" desc="" bitrange="2:2"> | ||
95 | <value name="NO_ERROR" value="0x0" desc=""/> | ||
96 | <value name="ERROR" value="0x1" desc=""/> | ||
97 | </field> | ||
98 | <field name="CHANNEL1_INT" desc="Channel 1 Interrupt active, clear interrupt after write." bitrange="1:1"> | ||
99 | <value name="NOT_ACTIVE" value="0x0" desc=""/> | ||
100 | <value name="ACTIVE" value="0x1" desc=""/> | ||
101 | </field> | ||
102 | <field name="CHANNEL0_INT" desc="Channel 0 Interrupt active, clear interrupt after write." bitrange="0:0"> | ||
103 | <value name="NOT_ACTIVE" value="0x0" desc=""/> | ||
104 | <value name="ACTIVE" value="0x1" desc=""/> | ||
105 | </field> | ||
49 | </reg> | 106 | </reg> |
50 | <reg name="DMA_STS" desc=""> | 107 | <reg name="DMA_STS" desc=""> |
51 | <addr name="DMA_STS" addr="0x3c"/> | 108 | <addr name="DMA_STS" addr="0x3c"/> |
109 | <field name="RESERVED31_2" desc="" bitrange="31:2"/> | ||
110 | <field name="CHANNEL1_BUSY" desc="" bitrange="1:1"> | ||
111 | <value name="FREE" value="0x0" desc=""/> | ||
112 | <value name="BUSY" value="0x1" desc=""/> | ||
113 | </field> | ||
114 | <field name="CHANNEL0_BUSY" desc="" bitrange="0:0"> | ||
115 | <value name="FREE" value="0x0" desc=""/> | ||
116 | <value name="BUSY" value="0x1" desc=""/> | ||
117 | </field> | ||
52 | </reg> | 118 | </reg> |
53 | <reg name="ERR_ADR0" desc=""> | 119 | <reg name="ERR_ADR" desc=""> |
54 | <addr name="ERR_ADR0" addr="0x40"/> | 120 | <addr name="ERR_ADR0" addr="0x40"/> |
55 | </reg> | ||
56 | <reg name="ERR_OP0" desc=""> | ||
57 | <addr name="ERR_OP0" addr="0x44"/> | ||
58 | </reg> | ||
59 | <reg name="ERR_ADR1" desc=""> | ||
60 | <addr name="ERR_ADR1" addr="0x48"/> | 121 | <addr name="ERR_ADR1" addr="0x48"/> |
61 | </reg> | 122 | </reg> |
62 | <reg name="ERR_OP1" desc=""> | 123 | <reg name="ERR_OP" desc=""> |
124 | <addr name="ERR_OP0" addr="0x44"/> | ||
63 | <addr name="ERR_OP1" addr="0x4c"/> | 125 | <addr name="ERR_OP1" addr="0x4c"/> |
126 | <field name="RESERVED31_1" desc="" bitrange="31:1"/> | ||
127 | <field name="DIR" desc="" bitrange="0:0"> | ||
128 | <value name="READ" value="0x0" desc=""/> | ||
129 | <value name="WRITE" value="0x1" desc=""/> | ||
130 | </field> | ||
64 | </reg> | 131 | </reg> |
65 | <reg name="LCNT0" desc=""> | 132 | <reg name="LCNT" desc=""> |
66 | <addr name="LCNT0" addr="0x50"/> | 133 | <addr name="LCNT0" addr="0x50"/> |
67 | </reg> | ||
68 | <reg name="LCNT1" desc=""> | ||
69 | <addr name="LCNT1" addr="0x54"/> | 134 | <addr name="LCNT1" addr="0x54"/> |
135 | <field name="RESERVED31_3" desc="" bitrange="31:3"/> | ||
136 | <field name="LOCK_CNT" desc="Bus lock counts at on-the-fly mode." bitrange="2:0"> | ||
137 | <value name="NEVER" value="0x0" desc=""/> | ||
138 | <value name="16BITS" value="0x1" desc=""/> | ||
139 | <value name="32BITS" value="0x2" desc=""/> | ||
140 | <value name="64BITS" value="0x3" desc=""/> | ||
141 | <value name="128BITS" value="0x4" desc=""/> | ||
142 | <value name="256BITS" value="0x5" desc=""/> | ||
143 | <value name="512BITS" value="0x6" desc=""/> | ||
144 | <value name="1024BITS" value="0x7" desc=""/> | ||
145 | </field> | ||
70 | </reg> | 146 | </reg> |
71 | <reg name="DOMAIN" desc=""> | 147 | <reg name="DOMAIN" desc=""> |
72 | <addr name="DOMAIN" addr="0x58"/> | 148 | <addr name="DOMAIN" addr="0x58"/> |
149 | <field name="RESERVED31_4" desc="" bitrange="31:4"/> | ||
150 | <field name="CH1_DST_DOMAIN" desc="" bitrange="3:3"> | ||
151 | <value name="AHB0" value="0x0" desc=""/> | ||
152 | <value name="AHB1" value="0x1" desc=""/> | ||
153 | </field> | ||
154 | <field name="CH1_SRC_DOMAIN" desc="" bitrange="2:2"> | ||
155 | <value name="AHB0" value="0x0" desc=""/> | ||
156 | <value name="AHB1" value="0x1" desc=""/> | ||
157 | </field> | ||
158 | <field name="CH0_DST_DOMAIN" desc="" bitrange="1:1"> | ||
159 | <value name="AHB0" value="0x0" desc=""/> | ||
160 | <value name="AHB1" value="0x1" desc=""/> | ||
161 | </field> | ||
162 | <field name="CH0_SRC_DOMAIN" desc="" bitrange="0:0"> | ||
163 | <value name="AHB0" value="0x0" desc=""/> | ||
164 | <value name="AHB1" value="0x1" desc=""/> | ||
165 | </field> | ||
73 | </reg> | 166 | </reg> |
74 | </dev> | 167 | </dev> |
75 | <dev name="ADC" long_name="ADC" desc="4 channels 10-bit SAR A/D converter" version="1.0"> | 168 | <dev name="ADC" long_name="ADC" desc="4 channels 10-bit SAR A/D converter" version="1.0"> |
@@ -183,21 +276,21 @@ | |||
183 | </dev> | 276 | </dev> |
184 | <dev name="DWDMA" long_name="DMA Controller" desc="DMA Controller" version="1.0"> | 277 | <dev name="DWDMA" long_name="DMA Controller" desc="DMA Controller" version="1.0"> |
185 | <addr name="DWDMA" addr="0x186f0000"/> | 278 | <addr name="DWDMA" addr="0x186f0000"/> |
186 | <reg name="DWDMA_SARn" desc=""> | 279 | <reg name="DWDMA_SARn" desc="Source address register"> |
187 | <formula string="n*0x58+0x00"/> | 280 | <formula string="n*0x58+0x00"/> |
188 | <addr name="SAR0" addr="0x0"/> | 281 | <addr name="SAR0" addr="0x0"/> |
189 | <addr name="SAR1" addr="0x58"/> | 282 | <addr name="SAR1" addr="0x58"/> |
190 | <addr name="SAR2" addr="0xb0"/> | 283 | <addr name="SAR2" addr="0xb0"/> |
191 | <addr name="SAR3" addr="0x108"/> | 284 | <addr name="SAR3" addr="0x108"/> |
192 | </reg> | 285 | </reg> |
193 | <reg name="DWDMA_DARn" desc=""> | 286 | <reg name="DWDMA_DARn" desc="Destination address register"> |
194 | <formula string="n*0x58+0x08"/> | 287 | <formula string="n*0x58+0x08"/> |
195 | <addr name="DAR0" addr="0x8"/> | 288 | <addr name="DAR0" addr="0x8"/> |
196 | <addr name="DAR1" addr="0x60"/> | 289 | <addr name="DAR1" addr="0x60"/> |
197 | <addr name="DAR2" addr="0xb8"/> | 290 | <addr name="DAR2" addr="0xb8"/> |
198 | <addr name="DAR3" addr="0x110"/> | 291 | <addr name="DAR3" addr="0x110"/> |
199 | </reg> | 292 | </reg> |
200 | <reg name="DWDMA_LLPn" desc=""> | 293 | <reg name="DWDMA_LLPn" desc="Linked List pointer register"> |
201 | <formula string="n*0x58+0x10"/> | 294 | <formula string="n*0x58+0x10"/> |
202 | <addr name="LLP0" addr="0x10"/> | 295 | <addr name="LLP0" addr="0x10"/> |
203 | <addr name="LLP1" addr="0x68"/> | 296 | <addr name="LLP1" addr="0x68"/> |
@@ -210,6 +303,61 @@ | |||
210 | <addr name="CTL_L1" addr="0x70"/> | 303 | <addr name="CTL_L1" addr="0x70"/> |
211 | <addr name="CTL_L2" addr="0xc8"/> | 304 | <addr name="CTL_L2" addr="0xc8"/> |
212 | <addr name="CTL_L3" addr="0x120"/> | 305 | <addr name="CTL_L3" addr="0x120"/> |
306 | <field name="RESERVED31_29" desc="" bitrange="31:29"/> | ||
307 | <field name="LLP_SRC_EN" desc="" bitrange="28:28"/> | ||
308 | <field name="LLP_DST_EN" desc="" bitrange="27:27"/> | ||
309 | <field name="SMS" desc="" bitrange="26:25"/> | ||
310 | <field name="DMS" desc="" bitrange="24:23"/> | ||
311 | <field name="TT_FC" desc="" bitrange="22:20"> | ||
312 | <value name="MEM2MEM" value="0x0" desc="flow controller DWDMA_AHB_DMAC"/> | ||
313 | <value name="MEM2PERI" value="0x1" desc="flow controller DWDMA_AHB_DMAC"/> | ||
314 | <value name="PERI2MEM" value="0x2" desc="flow controller DWDMA_AHB_DMAC"/> | ||
315 | <value name="PERI2PERI" value="0x3" desc="flow controller DWDMA_AHB_DMAC"/> | ||
316 | <value name="PERI2MEM" value="0x4" desc="flow controller Peripheral"/> | ||
317 | <value name="PERI2PERI" value="0x5" desc="flow controller Source Peripheral"/> | ||
318 | <value name="MEM2PERI" value="0x6" desc="flow controller Peripheral"/> | ||
319 | <value name="PERI2PERI" value="0x7" desc="flow controller Destination Peripheral"/> | ||
320 | </field> | ||
321 | <field name="RESERVED19" desc="" bitrange="19:19"/> | ||
322 | <field name="DST_SCATTER_EN" desc="" bitrange="18:18"/> | ||
323 | <field name="SRC_GATHER_EN" desc="" bitrange="17:17"/> | ||
324 | <field name="SRC_MSIZE" desc="Number of data items to be transferred (of width CTLx.SRC_TR_WIDTH or CTLx.DST_TR_WIDTH) " bitrange="16:14"> | ||
325 | <value name="1" value="0x0" desc=""/> | ||
326 | <value name="4" value="0x1" desc=""/> | ||
327 | <value name="8" value="0x2" desc=""/> | ||
328 | <value name="16" value="0x3" desc=""/> | ||
329 | <value name="32" value="0x4" desc=""/> | ||
330 | </field> | ||
331 | <field name="DST_MSIZE" desc="" bitrange="13:11"> | ||
332 | <value name="1" value="0x0" desc=""/> | ||
333 | <value name="4" value="0x1" desc=""/> | ||
334 | <value name="8" value="0x2" desc=""/> | ||
335 | <value name="16" value="0x3" desc=""/> | ||
336 | <value name="32" value="0x4" desc=""/> | ||
337 | </field> | ||
338 | <field name="SINC" desc="Source Address Increment." bitrange="10:9"> | ||
339 | <value name="INCREMENT" value="0x0" desc=""/> | ||
340 | <value name="DECREMENT" value="0x1" desc=""/> | ||
341 | <value name="FIXED" value="0x2" desc=""/> | ||
342 | <value name="FIXED" value="0x3" desc=""/> | ||
343 | </field> | ||
344 | <field name="DINC" desc="" bitrange="8:7"> | ||
345 | <value name="INCREMENT" value="0x0" desc=""/> | ||
346 | <value name="DECREMENT" value="0x1" desc=""/> | ||
347 | <value name="FIXED" value="0x2" desc=""/> | ||
348 | <value name="FIXED" value="0x3" desc=""/> | ||
349 | </field> | ||
350 | <field name="SRC_TR_WIDTH" desc="" bitrange="6:4"> | ||
351 | <value name="BYTE" value="0x0" desc=""/> | ||
352 | <value name="HALFWORD" value="0x1" desc=""/> | ||
353 | <value name="WORD" value="0x2" desc=""/> | ||
354 | </field> | ||
355 | <field name="DST_TR_WIDTH" desc="" bitrange="3:1"> | ||
356 | <value name="BYTE" value="0x0" desc=""/> | ||
357 | <value name="HALFWORD" value="0x1" desc=""/> | ||
358 | <value name="WORD" value="0x2" desc=""/> | ||
359 | </field> | ||
360 | <field name="INT_EN" desc="" bitrange="0:0"/> | ||
213 | </reg> | 361 | </reg> |
214 | <reg name="DWDMA_CTL_Hn" desc=""> | 362 | <reg name="DWDMA_CTL_Hn" desc=""> |
215 | <formula string="n*0x58+0x1c"/> | 363 | <formula string="n*0x58+0x1c"/> |
@@ -217,6 +365,9 @@ | |||
217 | <addr name="CTL_H1" addr="0x74"/> | 365 | <addr name="CTL_H1" addr="0x74"/> |
218 | <addr name="CTL_H2" addr="0xcc"/> | 366 | <addr name="CTL_H2" addr="0xcc"/> |
219 | <addr name="CTL_H3" addr="0x124"/> | 367 | <addr name="CTL_H3" addr="0x124"/> |
368 | <field name="RESERVED31_13" desc="" bitrange="31:13"/> | ||
369 | <field name="DONE" desc="" bitrange="12:12"/> | ||
370 | <field name="BLOCK_TS" desc="" bitrange="12:0"/> | ||
220 | </reg> | 371 | </reg> |
221 | <reg name="DWDMA_SSTATn" desc=""> | 372 | <reg name="DWDMA_SSTATn" desc=""> |
222 | <formula string="n*0x58+0x20"/> | 373 | <formula string="n*0x58+0x20"/> |
@@ -252,6 +403,38 @@ | |||
252 | <addr name="CFG_L1" addr="0x98"/> | 403 | <addr name="CFG_L1" addr="0x98"/> |
253 | <addr name="CFG_L2" addr="0xf0"/> | 404 | <addr name="CFG_L2" addr="0xf0"/> |
254 | <addr name="CFG_L3" addr="0x148"/> | 405 | <addr name="CFG_L3" addr="0x148"/> |
406 | <field name="RELOAD_DST" desc="" bitrange="31:31"/> | ||
407 | <field name="CH_SUSP" desc="" bitrange="31:0"> | ||
408 | <value name="SUSPEND" value="0x1" desc=""/> | ||
409 | </field> | ||
410 | <field name="RELOAD_SRC" desc="" bitrange="30:30"/> | ||
411 | <field name="MAX_ABRST" desc="" bitrange="29:20"/> | ||
412 | <field name="SRC_HS_POL" desc="Source Handshaking Interface Polarity." bitrange="19:19"> | ||
413 | <value name="ACTIVE_HIGH" value="0x0" desc=""/> | ||
414 | <value name="ACTIVE_LOW" value="0x1" desc=""/> | ||
415 | </field> | ||
416 | <field name="DST_HS_POL" desc="Destination Handshaking Interface Polarity." bitrange="18:18"> | ||
417 | <value name="ACTIVE_HIGH" value="0x0" desc=""/> | ||
418 | <value name="ACTIVE_LOW" value="0x1" desc=""/> | ||
419 | </field> | ||
420 | <field name="LOCK_B" desc="" bitrange="17:17"/> | ||
421 | <field name="LOCK_CH" desc="" bitrange="16:16"/> | ||
422 | <field name="LOCK_B_L" desc="" bitrange="15:14"/> | ||
423 | <field name="LOCK_CH_L" desc="" bitrange="13:12"/> | ||
424 | <field name="HS_SEL_SRC" desc="" bitrange="11:11"> | ||
425 | <value name="HW" value="0x0" desc=""/> | ||
426 | <value name="SW" value="0x1" desc=""/> | ||
427 | </field> | ||
428 | <field name="HS_SEL_DST" desc="" bitrange="10:10"> | ||
429 | <value name="HW" value="0x0" desc=""/> | ||
430 | <value name="SW" value="0x1" desc=""/> | ||
431 | </field> | ||
432 | <field name="FIFO_EMPTY" desc="Indicates if there is data left in the channel FIFO." bitrange="9:9"> | ||
433 | <value name="NOT_EMPTY" value="0x0" desc=""/> | ||
434 | <value name="EMPTY" value="0x1" desc=""/> | ||
435 | </field> | ||
436 | <field name="CH_PRIOR" desc="Channel priority. A priority of 7 is the highest priority, and 0 is the lowest. " bitrange="7:5"/> | ||
437 | <field name="RESERVED4_0" desc="" bitrange="4:0"/> | ||
255 | </reg> | 438 | </reg> |
256 | <reg name="DWDMA_CFG_Hn" desc=""> | 439 | <reg name="DWDMA_CFG_Hn" desc=""> |
257 | <formula string="n*0x58+0x44"/> | 440 | <formula string="n*0x58+0x44"/> |
@@ -260,7 +443,7 @@ | |||
260 | <addr name="CFG_H2" addr="0xf4"/> | 443 | <addr name="CFG_H2" addr="0xf4"/> |
261 | <addr name="CFG_H3" addr="0x14c"/> | 444 | <addr name="CFG_H3" addr="0x14c"/> |
262 | </reg> | 445 | </reg> |
263 | <reg name="DWDMA_SGRn" desc=""> | 446 | <reg name="DWDMA_SGRn" desc="Source Gather Register"> |
264 | <formula string="n*0x58+0x48"/> | 447 | <formula string="n*0x58+0x48"/> |
265 | <addr name="SGR0" addr="0x48"/> | 448 | <addr name="SGR0" addr="0x48"/> |
266 | <addr name="SGR1" addr="0xa0"/> | 449 | <addr name="SGR1" addr="0xa0"/> |
@@ -357,9 +540,28 @@ | |||
357 | </reg> | 540 | </reg> |
358 | <reg name="DMA_CFG" desc=""> | 541 | <reg name="DMA_CFG" desc=""> |
359 | <addr name="DMA_CFG" addr="0x398"/> | 542 | <addr name="DMA_CFG" addr="0x398"/> |
543 | <field name="RESERVED31_1" desc="" bitrange="31:1"/> | ||
544 | <field name="DMA_EN" desc="Global DMA enable." bitrange="0:0"> | ||
545 | <value name="DISABLE" value="0x0" desc=""/> | ||
546 | <value name="ENABLE" value="0x1" desc=""/> | ||
547 | </field> | ||
360 | </reg> | 548 | </reg> |
361 | <reg name="DMA_CHEN" desc=""> | 549 | <reg name="DMA_CHEN" desc="Channel enable register."> |
362 | <addr name="DMA_CHEN" addr="0x3a0"/> | 550 | <addr name="DMA_CHEN" addr="0x3a0"/> |
551 | <field name="RESERVED_31_12" desc="" bitrange="31:12"/> | ||
552 | <field name="CHANNEL_EN_WR_EN" desc="Channel enable write enable." bitrange="11:8"> | ||
553 | <value name="CH0_EN_WR_EN" value="0x1" desc=""/> | ||
554 | <value name="CH1_EN_WR_EN" value="0x2" desc=""/> | ||
555 | <value name="CH2_EN_WR_EN" value="0x4" desc=""/> | ||
556 | <value name="CH3_EN_WR_EN" value="0x8" desc=""/> | ||
557 | </field> | ||
558 | <field name="RESERVED7_4" desc="" bitrange="7:4"/> | ||
559 | <field name="CHANNEL_EN" desc="" bitrange="3:0"> | ||
560 | <value name="CH0_EN" value="0x1" desc=""/> | ||
561 | <value name="CH1_EN" value="0x2" desc=""/> | ||
562 | <value name="CH2_EN" value="0x4" desc=""/> | ||
563 | <value name="CH3_EN" value="0x8" desc=""/> | ||
564 | </field> | ||
363 | </reg> | 565 | </reg> |
364 | </dev> | 566 | </dev> |
365 | <dev name="GPIO" long_name="GPIO" desc="GPIO" version="1.0"> | 567 | <dev name="GPIO" long_name="GPIO" desc="GPIO" version="1.0"> |
@@ -508,46 +710,32 @@ | |||
508 | </dev> | 710 | </dev> |
509 | <dev name="HDMA" long_name="AHB DMA" desc="AHB DMA" version="1.0"> | 711 | <dev name="HDMA" long_name="AHB DMA" desc="AHB DMA" version="1.0"> |
510 | <addr name="HDMA" addr="0x18090000"/> | 712 | <addr name="HDMA" addr="0x18090000"/> |
511 | <reg name="CON0" desc=""> | 713 | <reg name="CON" desc=""> |
512 | <addr name="CON0" addr="0x0"/> | 714 | <addr name="CON0" addr="0x0"/> |
513 | </reg> | ||
514 | <reg name="CON1" desc=""> | ||
515 | <addr name="CON1" addr="0x4"/> | 715 | <addr name="CON1" addr="0x4"/> |
516 | </reg> | 716 | </reg> |
517 | <reg name="ISRC0" desc=""> | 717 | <reg name="ISRC" desc=""> |
518 | <addr name="ISRC0" addr="0x8"/> | 718 | <addr name="ISRC0" addr="0x8"/> |
519 | </reg> | ||
520 | <reg name="IDST0" desc=""> | ||
521 | <addr name="IDST0" addr="0xc"/> | ||
522 | </reg> | ||
523 | <reg name="ICNT0" desc=""> | ||
524 | <addr name="ICNT0" addr="0x10"/> | ||
525 | </reg> | ||
526 | <reg name="ISRC1" desc=""> | ||
527 | <addr name="ISRC1" addr="0x14"/> | 719 | <addr name="ISRC1" addr="0x14"/> |
528 | </reg> | 720 | </reg> |
529 | <reg name="IDST1" desc=""> | 721 | <reg name="IDST" desc=""> |
722 | <addr name="IDST0" addr="0xc"/> | ||
530 | <addr name="IDST1" addr="0x18"/> | 723 | <addr name="IDST1" addr="0x18"/> |
531 | </reg> | 724 | </reg> |
532 | <reg name="ICNT1" desc=""> | 725 | <reg name="ICNT" desc=""> |
726 | <addr name="ICNT0" addr="0x10"/> | ||
533 | <addr name="ICNT1" addr="0x1c"/> | 727 | <addr name="ICNT1" addr="0x1c"/> |
534 | </reg> | 728 | </reg> |
535 | <reg name="CSRC0" desc=""> | 729 | <reg name="CSRC" desc=""> |
536 | <addr name="CSRC0" addr="0x20"/> | 730 | <addr name="CSRC0" addr="0x20"/> |
537 | </reg> | ||
538 | <reg name="CDST0" desc=""> | ||
539 | <addr name="CDST0" addr="0x24"/> | ||
540 | </reg> | ||
541 | <reg name="CCNT0" desc=""> | ||
542 | <addr name="CCNT0" addr="0x28"/> | ||
543 | </reg> | ||
544 | <reg name="CSRC1" desc=""> | ||
545 | <addr name="CSRC1" addr="0x2c"/> | 731 | <addr name="CSRC1" addr="0x2c"/> |
546 | </reg> | 732 | </reg> |
547 | <reg name="CDST1" desc=""> | 733 | <reg name="CDST" desc=""> |
734 | <addr name="CDST0" addr="0x24"/> | ||
548 | <addr name="CDST1" addr="0x30"/> | 735 | <addr name="CDST1" addr="0x30"/> |
549 | </reg> | 736 | </reg> |
550 | <reg name="CCNT1" desc=""> | 737 | <reg name="CCNT" desc=""> |
738 | <addr name="CCNT0" addr="0x28"/> | ||
551 | <addr name="CCNT1" addr="0x34"/> | 739 | <addr name="CCNT1" addr="0x34"/> |
552 | </reg> | 740 | </reg> |
553 | <reg name="ISR" desc=""> | 741 | <reg name="ISR" desc=""> |
@@ -556,46 +744,32 @@ | |||
556 | <reg name="DSR" desc=""> | 744 | <reg name="DSR" desc=""> |
557 | <addr name="DSR" addr="0x3c"/> | 745 | <addr name="DSR" addr="0x3c"/> |
558 | </reg> | 746 | </reg> |
559 | <reg name="ISCNT0" desc=""> | 747 | <reg name="ISCNT" desc=""> |
560 | <addr name="ISCNT0" addr="0x40"/> | 748 | <addr name="ISCNT0" addr="0x40"/> |
561 | </reg> | ||
562 | <reg name="IPNCNTD0" desc=""> | ||
563 | <addr name="IPNCNTD0" addr="0x44"/> | ||
564 | </reg> | ||
565 | <reg name="IADDR_BS0" desc=""> | ||
566 | <addr name="IADDR_BS0" addr="0x48"/> | ||
567 | </reg> | ||
568 | <reg name="ISCNT1" desc=""> | ||
569 | <addr name="ISCNT1" addr="0x4c"/> | 749 | <addr name="ISCNT1" addr="0x4c"/> |
570 | </reg> | 750 | </reg> |
571 | <reg name="IPNCNTD1" desc=""> | 751 | <reg name="IPNCNTD" desc=""> |
752 | <addr name="IPNCNTD0" addr="0x44"/> | ||
572 | <addr name="IPNCNTD1" addr="0x50"/> | 753 | <addr name="IPNCNTD1" addr="0x50"/> |
573 | </reg> | 754 | </reg> |
574 | <reg name="IADDR_BS1" desc=""> | 755 | <reg name="IADDR_BS" desc=""> |
575 | <addr name="IADDR_BS1" addr="0x54"/> | 756 | <addr name="IADDR_BS0" addr="0x48"/> |
757 | <addr name="IADDR_BS0" addr="0x54"/> | ||
576 | </reg> | 758 | </reg> |
577 | <reg name="CSCNT0" desc=""> | 759 | <reg name="CSCNT" desc=""> |
578 | <addr name="CSCNT0" addr="0x58"/> | 760 | <addr name="CSCNT0" addr="0x58"/> |
761 | <addr name="CSCNT0" addr="0x64"/> | ||
579 | </reg> | 762 | </reg> |
580 | <reg name="CPNCNTD0" desc=""> | 763 | <reg name="CPNCNTD" desc=""> |
581 | <addr name="CPNCNTD0" addr="0x5c"/> | 764 | <addr name="CPNCNTD0" addr="0x5c"/> |
582 | </reg> | ||
583 | <reg name="CADDR_BS0" desc=""> | ||
584 | <addr name="CADDR_BS0" addr="0x60"/> | ||
585 | </reg> | ||
586 | <reg name="CSCNT1" desc=""> | ||
587 | <addr name="CSCNT1" addr="0x64"/> | ||
588 | </reg> | ||
589 | <reg name="CPNCNTD1" desc=""> | ||
590 | <addr name="CPNCNTD1" addr="0x68"/> | 765 | <addr name="CPNCNTD1" addr="0x68"/> |
591 | </reg> | 766 | </reg> |
592 | <reg name="CADDR_BS1" desc=""> | 767 | <reg name="CADDR_BS" desc=""> |
768 | <addr name="CADDR_BS0" addr="0x60"/> | ||
593 | <addr name="CADDR_BS1" addr="0x6c"/> | 769 | <addr name="CADDR_BS1" addr="0x6c"/> |
594 | </reg> | 770 | </reg> |
595 | <reg name="PACNT0" desc=""> | 771 | <reg name="PACNT" desc=""> |
596 | <addr name="PACNT0" addr="0x70"/> | 772 | <addr name="PACNT0" addr="0x70"/> |
597 | </reg> | ||
598 | <reg name="PACNT1" desc=""> | ||
599 | <addr name="PACNT1" addr="0x74"/> | 773 | <addr name="PACNT1" addr="0x74"/> |
600 | </reg> | 774 | </reg> |
601 | </dev> | 775 | </dev> |
@@ -654,27 +828,137 @@ | |||
654 | <addr name="I2S" addr="0x18028000"/> | 828 | <addr name="I2S" addr="0x18028000"/> |
655 | <reg name="OPR" desc=""> | 829 | <reg name="OPR" desc=""> |
656 | <addr name="OPR" addr="0x0"/> | 830 | <addr name="OPR" addr="0x0"/> |
831 | <field name="I2S_VERSION" desc="" bitrange="31:24"/> | ||
832 | <field name="RESERVED23_18" desc="" bitrange="23:18"/> | ||
833 | <field name="TX_RESET" desc="" bitrange="17:17"/> | ||
834 | <field name="RX_RESET" desc="" bitrange="16:16"/> | ||
835 | <field name="RESERVED15_7" desc="" bitrange="15:7"/> | ||
836 | <field name="HDMA_REQ1_DIS" desc="" bitrange="6:6"> | ||
837 | <value name="ENABLE" value="0x0" desc=""/> | ||
838 | <value name="DISABLE" value="0x1" desc="HDMA REQ1 Always 1 "/> | ||
839 | </field> | ||
840 | <field name="HDMA_REQ2_DIS" desc="" bitrange="5:5"> | ||
841 | <value name="ENABLE" value="0x0" desc=""/> | ||
842 | <value name="DISABLE" value="0x1" desc="HDMA REQ2 Always 1"/> | ||
843 | </field> | ||
844 | <field name="HDMA_REQ1_CH" desc="This bit is to indicate the Hardware DMA IF1 is used for which FIFO " bitrange="4:4"> | ||
845 | <value name="TX_FIFO" value="0x0" desc=""/> | ||
846 | <value name="RX_FIFO" value="0x1" desc=""/> | ||
847 | </field> | ||
848 | <field name="HDMA_REQ2_CH" desc="his bit is to indicate the Hardware DMA IF2 is used for which FIFO" bitrange="3:3"> | ||
849 | <value name="TX_FIFO" value="0x0" desc=""/> | ||
850 | <value name="RX_FIFO" value="0x1" desc=""/> | ||
851 | </field> | ||
852 | <field name="I2S_LOOPBACK" desc="" bitrange="2:2"> | ||
853 | <value name="NORMAL" value="0x0" desc=""/> | ||
854 | <value name="LOOPBACK" value="0x1" desc=""/> | ||
855 | </field> | ||
856 | <field name="I2S_TX_START" desc="" bitrange="1:1"/> | ||
857 | <field name="I2S_RX_START" desc="" bitrange="0:0"/> | ||
657 | </reg> | 858 | </reg> |
658 | <reg name="TXR" desc=""> | 859 | <reg name="TXR" desc="I2S transmit FIFO"> |
659 | <addr name="TXR" addr="0x4"/> | 860 | <addr name="TXR" addr="0x4"/> |
660 | </reg> | 861 | </reg> |
661 | <reg name="RXR" desc=""> | 862 | <reg name="RXR" desc="I2S receive FIFO"> |
662 | <addr name="RXR" addr="0x8"/> | 863 | <addr name="RXR" addr="0x8"/> |
663 | </reg> | 864 | </reg> |
664 | <reg name="TXCTL" desc=""> | 865 | <reg name="TXCTL" desc=""> |
665 | <addr name="TXCTL" addr="0xc"/> | 866 | <addr name="TXCTL" addr="0xc"/> |
867 | <field name="RESERVED31_18" desc="" bitrange="31:18"/> | ||
868 | <field name="OVERSAMPLING" desc="Oversampling rate = LRCK / SCLK" bitrange="17:16"> | ||
869 | <value name="32FS" value="0x0" desc=""/> | ||
870 | <value name="64FS" value="0x1" desc=""/> | ||
871 | <value name="128FS" value="0x2" desc=""/> | ||
872 | <value name="RESERVED" value="0x3" desc=""/> | ||
873 | </field> | ||
874 | <field name="MCLK_DIV" desc="" bitrange="15:8"/> | ||
875 | <field name="RESERVED7_6" desc="" bitrange="7:6"/> | ||
876 | <field name="SAMPLE_WIDTH" desc="" bitrange="5:4"> | ||
877 | <value name="8BITS" value="0x0" desc=""/> | ||
878 | <value name="16BITS" value="0x1" desc=""/> | ||
879 | </field> | ||
880 | <field name="MONO_STEREO" desc="When the bit is set to 1, transmitter is at Mono mode and data output from left channel. " bitrange="3:3"> | ||
881 | <value name="STEREO" value="0x0" desc=""/> | ||
882 | <value name="MONO" value="0x1" desc=""/> | ||
883 | </field> | ||
884 | <field name="IF_MODE" desc="" bitrange="2:1"> | ||
885 | <value name="I2S" value="0x0" desc=""/> | ||
886 | <value name="LEFT_JUSTIFIED" value="0x1" desc=""/> | ||
887 | <value name="RIGHT_JUSTIFIED" value="0x2" desc=""/> | ||
888 | </field> | ||
889 | <field name="MASTER_SLAVE" desc="This bit decides that transmitter acts as a master or slave. " bitrange="0:0"> | ||
890 | <value name="SLAVE" value="0x0" desc=""/> | ||
891 | <value name="MASTER" value="0x0" desc=""/> | ||
892 | </field> | ||
666 | </reg> | 893 | </reg> |
667 | <reg name="RXCTL" desc=""> | 894 | <reg name="RXCTL" desc=""> |
668 | <addr name="RXCTL" addr="0x10"/> | 895 | <addr name="RXCTL" addr="0x10"/> |
896 | <field name="RESERVED31_25" desc="" bitrange="31:25"/> | ||
897 | <field name="RX_FIFO_RESET" desc="" bitrange="24:24"/> | ||
898 | <field name="RESERVED23_18" desc="" bitrange="23:18"/> | ||
899 | <field name="OVERSAMPLING" desc="Oversampling rate = LRCK / SCLK" bitrange="17:16"> | ||
900 | <value name="32fs" value="0x0" desc=""/> | ||
901 | <value name="64fs" value="0x1" desc=""/> | ||
902 | <value name="128fs" value="0x2" desc=""/> | ||
903 | </field> | ||
904 | <field name="MCLK_DIV" desc="" bitrange="15:8"/> | ||
905 | <field name="RESERVED7_6" desc="" bitrange="7:6"/> | ||
906 | <field name="SAMPLE_WIDTH" desc="" bitrange="5:4"> | ||
907 | <value name="8BITS" value="0x0" desc=""/> | ||
908 | <value name="16BITS" value="0x1" desc=""/> | ||
909 | </field> | ||
910 | <field name="MONO_STEREO" desc="" bitrange="3:3"> | ||
911 | <value name="STEREO" value="0x0" desc=""/> | ||
912 | <value name="MONO" value="0x1" desc=""/> | ||
913 | </field> | ||
914 | <field name="IF_MODE" desc="" bitrange="2:1"> | ||
915 | <value name="I2S" value="0x0" desc=""/> | ||
916 | <value name="LEFT_JUSTIFIED" value="0x1" desc=""/> | ||
917 | <value name="RIGHT_JUSTIFIED" value="0x2" desc=""/> | ||
918 | </field> | ||
919 | <field name="MASTER_SLAVE" desc="" bitrange="0:0"> | ||
920 | <value name="MASTER" value="0x0" desc=""/> | ||
921 | <value name="SLAVE" value="0x1" desc=""/> | ||
922 | </field> | ||
669 | </reg> | 923 | </reg> |
670 | <reg name="FIFOSTS" desc=""> | 924 | <reg name="FIFOSTS" desc="his register shows FIFO status and interrupts trigger level."> |
671 | <addr name="FIFOSTS" addr="0x14"/> | 925 | <addr name="FIFOSTS" addr="0x14"/> |
926 | <field name="RESERVED" desc="" bitrange="31:20"/> | ||
927 | <field name="TX_INT_TRIG" desc="Tx interrupt trigger level." bitrange="19:18"> | ||
928 | <value name="ALMOST_EMPTY" value="0x0" desc=""/> | ||
929 | <value name="HALF_FULL" value="0x1" desc=""/> | ||
930 | <value name="ALMOST_FULL" value="0x2" desc=""/> | ||
931 | </field> | ||
932 | <field name="RX_INT_TRIG" desc="Rx interrupt trigger level." bitrange="17:16"> | ||
933 | <value name="ALMOST_EMPTY" value="0x0" desc=""/> | ||
934 | <value name="HALF_FULL" value="0x1" desc=""/> | ||
935 | <value name="ALMOST_FULL" value="0x2" desc=""/> | ||
936 | </field> | ||
937 | <field name="RESERVED15_10" desc="" bitrange="15:10"/> | ||
938 | <field name="TX_FIFO_HALF" desc="" bitrange="9:9"/> | ||
939 | <field name="RX_FIFO_HALF" desc="" bitrange="8:8"/> | ||
940 | <field name="TX_FIFO_ALMOST_FULL" desc="" bitrange="7:7"/> | ||
941 | <field name="TX_FIFO_ALMOST_EMPTY" desc="" bitrange="6:6"/> | ||
942 | <field name="RX_FIFO_ALMOST_FULL" desc="" bitrange="5:5"/> | ||
943 | <field name="RX_FIFO_ALMOST_EMPTY" desc="" bitrange="4:4"/> | ||
944 | <field name="TX_FIFO_FULL" desc="" bitrange="3:3"/> | ||
945 | <field name="TX_FIFO_EMPTY" desc="" bitrange="2:2"/> | ||
946 | <field name="RX_FIFO_FULL" desc="" bitrange="1:1"/> | ||
947 | <field name="RX_FIFO_EMPTY" desc="" bitrange="0:0"/> | ||
672 | </reg> | 948 | </reg> |
673 | <reg name="IER" desc=""> | 949 | <reg name="IER" desc=""> |
674 | <addr name="IER" addr="0x18"/> | 950 | <addr name="IER" addr="0x18"/> |
951 | <field name="RESERVED31_3" desc="" bitrange="31:3"/> | ||
952 | <field name="TX_FIFO_LEVEL_EN" desc="This bit enables the interrupt when Tx FIFO trigger level is reached." bitrange="2:2"/> | ||
953 | <field name="RX_FIFO_LEVEL_EN" desc="This bit enables the interrupt when Rx FIFO trigger level is reached." bitrange="1:1"/> | ||
954 | <field name="RX_FIFO_OVERRUN_EN" desc="This bit enables the interrupt when Rx FIFO overrun condition occurred." bitrange="0:0"/> | ||
675 | </reg> | 955 | </reg> |
676 | <reg name="ISR" desc=""> | 956 | <reg name="ISR" desc="I2S interrupt status register"> |
677 | <addr name="ISR" addr="0x1c"/> | 957 | <addr name="ISR" addr="0x1c"/> |
958 | <field name="RESERVED31_3" desc="" bitrange="31:3"/> | ||
959 | <field name="TX_FIFO_LEVEL_INT" desc="" bitrange="2:2"/> | ||
960 | <field name="RX_FIFO_LEVEL_INT" desc="" bitrange="1:1"/> | ||
961 | <field name="RX_FIFO_OVERRUN_INT" desc="" bitrange="0:0"/> | ||
678 | </reg> | 962 | </reg> |
679 | </dev> | 963 | </dev> |
680 | <dev name="INTC" long_name="Interrupt controller" desc="Interrupt controller" version="1.0"> | 964 | <dev name="INTC" long_name="Interrupt controller" desc="Interrupt controller" version="1.0"> |