Fix identations.

Change-Id: I98acabd5c8ab024d553726cfabe5654242a18b3b

3 files changed, 15 insertions, 15 deletions

diff --git a/firmware/target/arm/rk27xx/debug-rk27xx.c b/firmware/target/arm/rk27xx/debug-rk27xx.c
index d6be51595a..98ceaf634a 100644
--- a/firmware/target/arm/rk27xx/debug-rk27xx.c
+++ b/firmware/target/arm/rk27xx/debug-rk27xx.c
@@ -66,7 +66,7 @@ bool dbg_hw_info(void)
         _DEBUG_PRINTF("SCU_CHIPCFG: 0x%0x", SCU_CHIPCFG);
 
 #ifdef HM60X
-        _DEBUG_PRINTF("LCD type: %s", lcd_type == LCD_V1 ? "V1 (HX8340b)": "V2");
+        _DEBUG_PRINTF("LCD type: %s", lcd_type == LCD_V1 ? "V1 (HX8340b)": "V2");
 #endif
         line++;
         _DEBUG_PRINTF("sd_debug_time_rd: %d", sd_debug_time_rd);
diff --git a/firmware/target/arm/rk27xx/nand-rk27xx.c b/firmware/target/arm/rk27xx/nand-rk27xx.c
index 84e60a47e1..a4c28b9fb7 100644
--- a/firmware/target/arm/rk27xx/nand-rk27xx.c
+++ b/firmware/target/arm/rk27xx/nand-rk27xx.c
@@ -176,7 +176,7 @@ void flash_init(void)
         /* Redundat - we will use special macros
          * just for reference what OF does
          */
-        flash_spec[i].cmd = 0x180E8200 + (i<<9);
+        flash_spec[i].cmd = 0x180E8200 + (i<<9);
         flash_spec[i].addr = 0x180E204 + (i<<9);
         flash_spec[i].data = 0x180E208 + (i<<9);
 
diff --git a/firmware/target/arm/rk27xx/pcm-rk27xx.c b/firmware/target/arm/rk27xx/pcm-rk27xx.c
index a4ce568a83..4e6b8fe6b6 100644
--- a/firmware/target/arm/rk27xx/pcm-rk27xx.c
+++ b/firmware/target/arm/rk27xx/pcm-rk27xx.c
@@ -203,16 +203,16 @@ static void set_codec_freq(unsigned int freq)
     /* {CLKR, CLKF, CLKOD, CODECPLL_DIV} */
     static const unsigned int pcm_freq_params[HW_NUM_FREQ][4] = 
     {
-        [HW_FREQ_96] = {24, 255, 4, 1},
-        [HW_FREQ_48] = {24, 127, 4, 1},
-        [HW_FREQ_44] = {24, 293, 4, 4},
-        [HW_FREQ_32] = {24, 127, 4, 2},
-        [HW_FREQ_24] = {24, 127, 4, 3},
-        [HW_FREQ_22] = {24, 146, 4, 4},
-        [HW_FREQ_16] = {24, 127, 5, 4},
-        [HW_FREQ_12] = {24, 127, 4, 7},
-        [HW_FREQ_11] = {24, 146, 4, 9},
-        [HW_FREQ_8]  = {24, 127, 5, 9},
+        [HW_FREQ_96] = {24, 255, 4, 1},
+        [HW_FREQ_48] = {24, 127, 4, 1},
+        [HW_FREQ_44] = {24, 293, 4, 4},
+        [HW_FREQ_32] = {24, 127, 4, 2},
+        [HW_FREQ_24] = {24, 127, 4, 3},
+        [HW_FREQ_22] = {24, 146, 4, 4},
+        [HW_FREQ_16] = {24, 127, 5, 4},
+        [HW_FREQ_12] = {24, 127, 4, 7},
+        [HW_FREQ_11] = {24, 146, 4, 9},
+        [HW_FREQ_8]  = {24, 127, 5, 9},
     };
     /* select divider output from codec pll */
     SCU_DIVCON1 &= ~((1<<9) | (0xF<<5));
@@ -223,9 +223,9 @@ static void set_codec_freq(unsigned int freq)
 
     SCU_PLLCON3 = (1<<24) |    /* Saturation behavior enable */
                   (1<<23) |    /* Enable fast locking circuit */
-                  (pcm_freq_params[freq][0]<<16) | /* CLKR factor */
-                  (pcm_freq_params[freq][1]<<4)  | /* CLKF factor */
-                  (pcm_freq_params[freq][2]<<1) ; /* CLKOD factor */
+                  (pcm_freq_params[freq][0]<<16) | /* CLKR factor */
+                  (pcm_freq_params[freq][1]<<4)  | /* CLKF factor */
+                  (pcm_freq_params[freq][2]<<1) ; /* CLKOD factor */
 
 /* wait for CODEC PLL lock with 10 ms timeout
  * datasheet states that pll lock should take approx. 0.3 ms