diff options
Diffstat (limited to 'firmware/target/arm/rk27xx/pcm-rk27xx.c')
-rw-r--r-- | firmware/target/arm/rk27xx/pcm-rk27xx.c | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/firmware/target/arm/rk27xx/pcm-rk27xx.c b/firmware/target/arm/rk27xx/pcm-rk27xx.c index a4ce568a83..4e6b8fe6b6 100644 --- a/firmware/target/arm/rk27xx/pcm-rk27xx.c +++ b/firmware/target/arm/rk27xx/pcm-rk27xx.c | |||
@@ -203,16 +203,16 @@ static void set_codec_freq(unsigned int freq) | |||
203 | /* {CLKR, CLKF, CLKOD, CODECPLL_DIV} */ | 203 | /* {CLKR, CLKF, CLKOD, CODECPLL_DIV} */ |
204 | static const unsigned int pcm_freq_params[HW_NUM_FREQ][4] = | 204 | static const unsigned int pcm_freq_params[HW_NUM_FREQ][4] = |
205 | { | 205 | { |
206 | [HW_FREQ_96] = {24, 255, 4, 1}, | 206 | [HW_FREQ_96] = {24, 255, 4, 1}, |
207 | [HW_FREQ_48] = {24, 127, 4, 1}, | 207 | [HW_FREQ_48] = {24, 127, 4, 1}, |
208 | [HW_FREQ_44] = {24, 293, 4, 4}, | 208 | [HW_FREQ_44] = {24, 293, 4, 4}, |
209 | [HW_FREQ_32] = {24, 127, 4, 2}, | 209 | [HW_FREQ_32] = {24, 127, 4, 2}, |
210 | [HW_FREQ_24] = {24, 127, 4, 3}, | 210 | [HW_FREQ_24] = {24, 127, 4, 3}, |
211 | [HW_FREQ_22] = {24, 146, 4, 4}, | 211 | [HW_FREQ_22] = {24, 146, 4, 4}, |
212 | [HW_FREQ_16] = {24, 127, 5, 4}, | 212 | [HW_FREQ_16] = {24, 127, 5, 4}, |
213 | [HW_FREQ_12] = {24, 127, 4, 7}, | 213 | [HW_FREQ_12] = {24, 127, 4, 7}, |
214 | [HW_FREQ_11] = {24, 146, 4, 9}, | 214 | [HW_FREQ_11] = {24, 146, 4, 9}, |
215 | [HW_FREQ_8] = {24, 127, 5, 9}, | 215 | [HW_FREQ_8] = {24, 127, 5, 9}, |
216 | }; | 216 | }; |
217 | /* select divider output from codec pll */ | 217 | /* select divider output from codec pll */ |
218 | SCU_DIVCON1 &= ~((1<<9) | (0xF<<5)); | 218 | SCU_DIVCON1 &= ~((1<<9) | (0xF<<5)); |
@@ -223,9 +223,9 @@ static void set_codec_freq(unsigned int freq) | |||
223 | 223 | ||
224 | SCU_PLLCON3 = (1<<24) | /* Saturation behavior enable */ | 224 | SCU_PLLCON3 = (1<<24) | /* Saturation behavior enable */ |
225 | (1<<23) | /* Enable fast locking circuit */ | 225 | (1<<23) | /* Enable fast locking circuit */ |
226 | (pcm_freq_params[freq][0]<<16) | /* CLKR factor */ | 226 | (pcm_freq_params[freq][0]<<16) | /* CLKR factor */ |
227 | (pcm_freq_params[freq][1]<<4) | /* CLKF factor */ | 227 | (pcm_freq_params[freq][1]<<4) | /* CLKF factor */ |
228 | (pcm_freq_params[freq][2]<<1) ; /* CLKOD factor */ | 228 | (pcm_freq_params[freq][2]<<1) ; /* CLKOD factor */ |
229 | 229 | ||
230 | /* wait for CODEC PLL lock with 10 ms timeout | 230 | /* wait for CODEC PLL lock with 10 ms timeout |
231 | * datasheet states that pll lock should take approx. 0.3 ms | 231 | * datasheet states that pll lock should take approx. 0.3 ms |