diff options
author | Rafaël Carré <rafael.carre@gmail.com> | 2009-05-26 18:44:02 +0000 |
---|---|---|
committer | Rafaël Carré <rafael.carre@gmail.com> | 2009-05-26 18:44:02 +0000 |
commit | ef9aacb2e020726cc45a00aca00ad9230fcdb25e (patch) | |
tree | ce1c1a580dabf545af5f95e70dee11093cfe9e1d | |
parent | 29bbcebee4043ef09ca5c71fb36251a3073e94f2 (diff) | |
download | rockbox-ef9aacb2e020726cc45a00aca00ad9230fcdb25e.tar.gz rockbox-ef9aacb2e020726cc45a00aca00ad9230fcdb25e.zip |
FS#10245 by Jack Halpin : Adjust Clocking scheme on Sansa AMS
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@21088 a1c6a512-1295-4272-9138-f99709370657
-rw-r--r-- | firmware/target/arm/as3525/ascodec-as3525.c | 2 | ||||
-rw-r--r-- | firmware/target/arm/as3525/ata_sd_as3525.c | 7 | ||||
-rw-r--r-- | firmware/target/arm/as3525/clock-target.h | 117 | ||||
-rw-r--r-- | firmware/target/arm/as3525/debug-as3525.c | 22 | ||||
-rw-r--r-- | firmware/target/arm/as3525/sansa-c200v2/lcd-c200v2.c | 2 | ||||
-rw-r--r-- | firmware/target/arm/as3525/sansa-clip/lcd-ssd1303.c | 2 | ||||
-rw-r--r-- | firmware/target/arm/as3525/sansa-e200v2/lcd-e200v2.c | 2 | ||||
-rw-r--r-- | firmware/target/arm/as3525/sansa-fuze/lcd-fuze.c | 2 | ||||
-rw-r--r-- | firmware/target/arm/as3525/system-as3525.c | 72 |
9 files changed, 155 insertions, 73 deletions
diff --git a/firmware/target/arm/as3525/ascodec-as3525.c b/firmware/target/arm/as3525/ascodec-as3525.c index b9790217aa..668c001f9b 100644 --- a/firmware/target/arm/as3525/ascodec-as3525.c +++ b/firmware/target/arm/as3525/ascodec-as3525.c | |||
@@ -78,7 +78,7 @@ void ascodec_init(void) | |||
78 | CGU_PERI |= CGU_I2C_AUDIO_MASTER_CLOCK_ENABLE; | 78 | CGU_PERI |= CGU_I2C_AUDIO_MASTER_CLOCK_ENABLE; |
79 | 79 | ||
80 | /* prescaler for i2c clock */ | 80 | /* prescaler for i2c clock */ |
81 | prescaler = CLK_DIV(AS3525_PCLK_FREQ, AS3525_I2C_FREQ); | 81 | prescaler = AS3525_I2C_PRESCALER; |
82 | I2C2_CPSR0 = prescaler & 0xFF; /* 8 lsb */ | 82 | I2C2_CPSR0 = prescaler & 0xFF; /* 8 lsb */ |
83 | I2C2_CPSR1 = (prescaler >> 8) & 0x3; /* 2 msb */ | 83 | I2C2_CPSR1 = (prescaler >> 8) & 0x3; /* 2 msb */ |
84 | 84 | ||
diff --git a/firmware/target/arm/as3525/ata_sd_as3525.c b/firmware/target/arm/as3525/ata_sd_as3525.c index 6d6b275fba..03a6a8bd02 100644 --- a/firmware/target/arm/as3525/ata_sd_as3525.c +++ b/firmware/target/arm/as3525/ata_sd_as3525.c | |||
@@ -456,8 +456,7 @@ static void init_pl180_controller(const int drive) | |||
456 | 456 | ||
457 | MCI_SELECT(drive) = 0; | 457 | MCI_SELECT(drive) = 0; |
458 | 458 | ||
459 | MCI_CLOCK(drive) = MCI_CLOCK_ENABLE | | 459 | MCI_CLOCK(drive) = MCI_CLOCK_ENABLE | AS3525_SD_IDENT_DIV; |
460 | (((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SD_IDENT_FREQ)) / 2) - 1); | ||
461 | mci_delay(); | 460 | mci_delay(); |
462 | } | 461 | } |
463 | 462 | ||
@@ -466,8 +465,8 @@ int sd_init(void) | |||
466 | int ret; | 465 | int ret; |
467 | CGU_IDE = (1<<7) /* AHB interface enable */ | | 466 | CGU_IDE = (1<<7) /* AHB interface enable */ | |
468 | (1<<6) /* interface enable */ | | 467 | (1<<6) /* interface enable */ | |
469 | ((CLK_DIV(AS3525_PLLA_FREQ, AS3525_IDE_FREQ) - 1) << 2) | | 468 | (AS3525_IDE_DIV << 2) | |
470 | 1; /* clock source = PLLA */ | 469 | AS3525_CLK_PLLA; /* clock source = PLLA */ |
471 | 470 | ||
472 | 471 | ||
473 | CGU_PERI |= CGU_NAF_CLOCK_ENABLE; | 472 | CGU_PERI |= CGU_NAF_CLOCK_ENABLE; |
diff --git a/firmware/target/arm/as3525/clock-target.h b/firmware/target/arm/as3525/clock-target.h index 1928f1fbf2..a6e4927386 100644 --- a/firmware/target/arm/as3525/clock-target.h +++ b/firmware/target/arm/as3525/clock-target.h | |||
@@ -24,47 +24,120 @@ | |||
24 | /* returns clock divider, given maximal target frequency and clock reference */ | 24 | /* returns clock divider, given maximal target frequency and clock reference */ |
25 | #define CLK_DIV(ref, target) ((ref + target - 1) / target) | 25 | #define CLK_DIV(ref, target) ((ref + target - 1) / target) |
26 | 26 | ||
27 | /* PLL */ | ||
28 | 27 | ||
29 | #define AS3525_PLLA_FREQ 248000000 | 28 | /* Frequency and Bus Settings |
29 | * These bus settings work on the assumption that unboosted performance will be | ||
30 | * based on fastbus mode(FCLK == PCLK) at a frequency configured with this file. | ||
31 | * Boosted performance defaults to synchronous bus but will be changed to | ||
32 | * asynchronous bus if FCLK is not an integer multiple of PCLK. | ||
33 | * The player starts up in fastbus mode and synchronous or asynchronous mode is | ||
34 | * implemented in the set_cpu_frequency() function in system-as3525.c. There | ||
35 | * are limitations on both frequencies and frequency relationships listed in 7.3.14 | ||
36 | * of the as3525 datasheet that need to be observed. If you are determined to | ||
37 | * use a frequency that is not "legal" you can do that. There are no checks for | ||
38 | * legal frequency values, only some validity checks to make sure the divider | ||
39 | * value fits into the number of bits allotted to it. | ||
40 | * | ||
41 | * The CLOCK_DIV macro does a pretty good job at selecting divider values but | ||
42 | * you can always overide it by choosing your own value and commenting out the | ||
43 | * macro. If you are going to use AS3525_FCLK_PREDIV or AS3525_PCLK_DIV1 you | ||
44 | * will have to do a manual calculation. I have included USB & PLLB for future | ||
45 | * use but commented them out for now. | ||
46 | */ | ||
47 | |||
48 | /* Clock Sources */ | ||
49 | #define AS3525_CLK_MAIN 0 | ||
50 | #define AS3525_CLK_PLLA 1 | ||
51 | //#define AS3525_CLK_PLLB 2 | ||
52 | #define AS3525_CLK_FCLK 3 /* for synchronous bus only */ | ||
53 | |||
54 | /* PLL frequencies and settings*/ | ||
55 | |||
56 | #define AS3525_PLLA_FREQ 248000000 /*124,82.7,62,49.6,41.3,35.4 */ | ||
57 | /* FCLK_PREDIV-> *7/8 = 217MHz 108.5 ,72.3, 54.25, 43.4, 36.17 */ | ||
58 | /* *6/8 = 186MHz 93, 62, 46.5, 37.2 */ | ||
59 | /* *5/8 = 155MHz 77.5, 51.67, 38.75 */ | ||
30 | #define AS3525_PLLA_SETTING 0x261F | 60 | #define AS3525_PLLA_SETTING 0x261F |
31 | 61 | ||
32 | /* CPU */ | 62 | //#define AS3525_PLLA_FREQ 384000000 /*192,128,96,76.8,64,54.9,48,42.7,38.4*/ |
63 | /* FCLK_PREDIV-> *7/8 = 336MHz 168, 112, 84, 67.2, 56, 48, 42, 37.3*/ | ||
64 | /* *6/8 = 288MHz 144, 96, 72, 57.6, 48, 41.1, */ | ||
65 | /* *5/8 = 240MHz 120, 80, 60, 48, 40 */ | ||
66 | //#define AS3525_PLLA_SETTING 0x2630 | ||
33 | 67 | ||
34 | /* ensure that PLLA_FREQ * prediv == CPUFREQ_MAX */ | 68 | /* PLLB not used at this time! */ |
35 | #define AS3525_CPU_PREDIV 0 /* div = 1/1 */ | 69 | //#define AS3525_PLLB_FREQ |
70 | //#define AS3525_PLLB_SETTING | ||
36 | 71 | ||
37 | #define CPUFREQ_MAX 248000000 | 72 | /** ************ Change these to reconfigure clocking scheme *******************/ |
38 | 73 | ||
39 | #define CPUFREQ_DEFAULT 24800000 | 74 | #define AS3525_FCLK_FREQ 248000000 /* Boosted FCLK frequency */ |
75 | #define AS3525_PCLK_FREQ 62000000 /* Initial PCLK frequency */ | ||
76 | #define AS3525_DBOP_FREQ AS3525_PCLK_FREQ /* Initial DBOP frequency */ | ||
40 | 77 | ||
41 | #define CPUFREQ_NORMAL 31000000 | 78 | /** ****************************************************************************/ |
42 | 79 | ||
43 | /* peripherals */ | 80 | /* Figure out if we need to use asynchronous bus */ |
81 | #if (AS3525_FCLK_FREQ % AS3525_PCLK_FREQ) | ||
82 | #define ASYNCHRONOUS_BUS /* Boosted mode asynchronous */ | ||
83 | #endif | ||
44 | 84 | ||
45 | #define AS3525_PCLK_FREQ 62000000 | 85 | /* Tell the software what frequencies we're running */ |
46 | #if (CLK_DIV(AS3525_PLLA_FREQ, AS3525_PCLK_FREQ) - 1) >= (1<<4) /* 4 bits */ | 86 | #define CPUFREQ_MAX AS3525_FCLK_FREQ |
47 | #error PCLK frequency is too low : clock divider will not fit ! | 87 | #define CPUFREQ_DEFAULT AS3525_PCLK_FREQ |
88 | #define CPUFREQ_NORMAL AS3525_PCLK_FREQ | ||
89 | |||
90 | /* FCLK */ | ||
91 | #define AS3525_FCLK_SEL AS3525_CLK_PLLA | ||
92 | #define AS3525_FCLK_PREDIV 0 /* div = (8-n)/8 acts strange when used!*/ | ||
93 | #define AS3525_FCLK_POSTDIV (CLK_DIV(AS3525_PLLA_FREQ, AS3525_FCLK_FREQ) - 1) /*div=1/(n+1)*/ | ||
94 | |||
95 | /* PCLK */ | ||
96 | #ifdef ASYNCHRONOUS_BUS | ||
97 | #define AS3525_PCLK_SEL AS3525_CLK_PLLA /* PLLA input for asynchronous */ | ||
98 | #define AS3525_PCLK_DIV0 (CLK_DIV(AS3525_PLLA_FREQ, AS3525_PCLK_FREQ) - 1)/*div=1/(n+1)*/ | ||
99 | #else | ||
100 | #define AS3525_PCLK_SEL AS3525_CLK_FCLK /* Fclk input for synchronous */ | ||
101 | #define AS3525_PCLK_DIV0 (CLK_DIV(AS3525_FCLK_FREQ, AS3525_PCLK_FREQ) - 1) /*div=1/(n+1)*/ | ||
48 | #endif | 102 | #endif |
103 | #define AS3525_PCLK_DIV1 0 /* div = 1/(n+1) unable to use successfuly so far*/ | ||
104 | |||
105 | /* PCLK as Source */ | ||
106 | #define AS3525_DBOP_DIV (CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ) - 1) /*div=1/(n+1)*/ | ||
107 | #define AS3525_I2C_PRESCALER CLK_DIV(AS3525_PCLK_FREQ, AS3525_I2C_FREQ) | ||
108 | #define AS3525_I2C_FREQ 400000 | ||
109 | #define AS3525_SD_IDENT_DIV ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SD_IDENT_FREQ) / 2) - 1) | ||
110 | #define AS3525_SD_IDENT_FREQ 400000 /* must be between 100 & 400 kHz */ | ||
49 | 111 | ||
50 | #define AS3525_IDE_FREQ 90000000 /* The OF uses 66MHz maximal freq | 112 | #define AS3525_IDE_SEL AS3525_CLK_PLLA /* Input Source */ |
113 | #define AS3525_IDE_DIV (CLK_DIV(AS3525_PLLA_FREQ, AS3525_IDE_FREQ) - 1)/*div=1/(n+1)*/ | ||
114 | #define AS3525_IDE_FREQ 90000000 /* The OF uses 66MHz maximal freq | ||
51 | but sd transfers fail on some | 115 | but sd transfers fail on some |
52 | players with this limit */ | 116 | players with this limit */ |
117 | |||
118 | //#define AS3525_USB_SEL AS3525_CLK_PLLA /* Input Source */ | ||
119 | //#define AS3525_USB_DIV /* div = 1/(n=0?1:2n)*/ | ||
120 | |||
121 | |||
122 | /* Validity Checks */ | ||
123 | |||
124 | /* AS3525_PCLK_FREQ */ | ||
125 | #if (CLK_DIV(AS3525_PLLA_FREQ, AS3525_PCLK_FREQ) - 1) >= (1<<4) /* 4 bits */ | ||
126 | #error PCLK frequency is too low : clock divider will not fit ! | ||
127 | #endif | ||
128 | /* AS3525_DBOP_FREQ */ | ||
129 | #if (CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ) - 1) >= (1<<3) /* 3 bits */ | ||
130 | #error DBOP frequency is too low : clock divider will not fit ! | ||
131 | #endif | ||
132 | /* AS3525_IDE_FREQ */ | ||
53 | #if (CLK_DIV(AS3525_PLLA_FREQ, AS3525_IDE_FREQ) - 1) >= (1<<4) /* 4 bits */ | 133 | #if (CLK_DIV(AS3525_PLLA_FREQ, AS3525_IDE_FREQ) - 1) >= (1<<4) /* 4 bits */ |
54 | #error IDE frequency is too low : clock divider will not fit ! | 134 | #error IDE frequency is too low : clock divider will not fit ! |
55 | #endif | 135 | #endif |
56 | 136 | /* AS3525_I2C_FREQ */ | |
57 | #define AS3525_I2C_FREQ 400000 | ||
58 | #if (CLK_DIV(AS3525_PCLK_FREQ, AS3525_I2C_FREQ)) >= (1<<10) /* 2+8 bits */ | 137 | #if (CLK_DIV(AS3525_PCLK_FREQ, AS3525_I2C_FREQ)) >= (1<<10) /* 2+8 bits */ |
59 | #error I2C frequency is too low : clock divider will not fit ! | 138 | #error I2C frequency is too low : clock divider will not fit ! |
60 | #endif | 139 | #endif |
61 | 140 | /* AS3525_SD_IDENT_FREQ */ | |
62 | #define AS3525_DBOP_FREQ 32000000 | ||
63 | #if (CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ) - 1) >= (1<<3) /* 3 bits */ | ||
64 | #error DBOP frequency is too low : clock divider will not fit ! | ||
65 | #endif | ||
66 | |||
67 | #define AS3525_SD_IDENT_FREQ 400000 /* must be between 100 & 400 kHz */ | ||
68 | #if ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SD_IDENT_FREQ) / 2) - 1) >= (1<<8) /* 8 bits */ | 141 | #if ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SD_IDENT_FREQ) / 2) - 1) >= (1<<8) /* 8 bits */ |
69 | #error SD IDENTIFICATION frequency is too low : clock divider will not fit ! | 142 | #error SD IDENTIFICATION frequency is too low : clock divider will not fit ! |
70 | #endif | 143 | #endif |
diff --git a/firmware/target/arm/as3525/debug-as3525.c b/firmware/target/arm/as3525/debug-as3525.c index ac7253d579..ea1bf9c381 100644 --- a/firmware/target/arm/as3525/debug-as3525.c +++ b/firmware/target/arm/as3525/debug-as3525.c | |||
@@ -120,39 +120,39 @@ int calc_freq(int clk) | |||
120 | switch(CGU_PROC & 3) { | 120 | switch(CGU_PROC & 3) { |
121 | case 0: | 121 | case 0: |
122 | return CLK_MAIN/ | 122 | return CLK_MAIN/ |
123 | ((8/(8-((CGU_PROC & 0xc)>>2)))*(((CGU_PROC & 0xf0)>>4) + 1)); | 123 | ((8/(8-((CGU_PROC>>2)& 0x3)))*(((CGU_PROC>>4)& 0xf) + 1)); |
124 | case 1: | 124 | case 1: |
125 | return calc_freq(CLK_PLLA)/ | 125 | return calc_freq(CLK_PLLA)/ |
126 | ((8/(8-((CGU_PROC & 0xc)>>2)))*(((CGU_PROC & 0xf0)>>4) + 1)); | 126 | ((8/(8-((CGU_PROC>>2)& 0x3)))*(((CGU_PROC>>4)& 0xf) + 1)); |
127 | case 2: | 127 | case 2: |
128 | return calc_freq(CLK_PLLB)/ | 128 | return calc_freq(CLK_PLLB)/ |
129 | ((8/(8-((CGU_PROC & 0xc)>>2)))*(((CGU_PROC & 0xf0)>>4) + 1)); | 129 | ((8/(8-((CGU_PROC>>2)& 0x3)))*(((CGU_PROC>>4)& 0xf) + 1)); |
130 | default: | 130 | default: |
131 | return 0; | 131 | return 0; |
132 | } | 132 | } |
133 | case CLK_EXTMEM: | 133 | case CLK_EXTMEM: |
134 | switch(CGU_PERI & 3) { | 134 | switch(CGU_PERI & 3) { |
135 | case 0: | 135 | case 0: |
136 | return CLK_MAIN/(((CGU_PERI & 0x3c)>>2)+1); | 136 | return CLK_MAIN/(((CGU_PERI>>2)& 0xf)+1); |
137 | case 1: | 137 | case 1: |
138 | return calc_freq(CLK_PLLA)/(((CGU_PERI & 0x3c)>>2)+1); | 138 | return calc_freq(CLK_PLLA)/(((CGU_PERI>>2)& 0xf)+1); |
139 | case 2: | 139 | case 2: |
140 | return calc_freq(CLK_PLLB)/(((CGU_PERI & 0x3c)>>2)+1); | 140 | return calc_freq(CLK_PLLB)/(((CGU_PERI>>2)& 0xf)+1); |
141 | case 3: | 141 | case 3: |
142 | return calc_freq(CLK_FCLK)/(((CGU_PERI & 0x3c)>>2)+1); | 142 | return calc_freq(CLK_FCLK)/(((CGU_PERI>>2)& 0xf)+1); |
143 | default: | 143 | default: |
144 | return 0; | 144 | return 0; |
145 | } | 145 | } |
146 | case CLK_PCLK: | 146 | case CLK_PCLK: |
147 | return calc_freq(CLK_EXTMEM)/(((CGU_PERI & 0x40)>>6)+1); | 147 | return calc_freq(CLK_EXTMEM)/(((CGU_PERI>>6)& 0x1)+1); |
148 | case CLK_IDE: | 148 | case CLK_IDE: |
149 | switch(CGU_IDE & 3) { | 149 | switch(CGU_IDE & 3) { |
150 | case 0: | 150 | case 0: |
151 | return CLK_MAIN/(((CGU_IDE & 0x3c)>>2)+1); | 151 | return CLK_MAIN/(((CGU_IDE>>2)& 0xf)+1); |
152 | case 1: | 152 | case 1: |
153 | return calc_freq(CLK_PLLA)/(((CGU_IDE & 0x3c)>>2)+1);; | 153 | return calc_freq(CLK_PLLA)/(((CGU_IDE>>2)& 0xf)+1); |
154 | case 2: | 154 | case 2: |
155 | return calc_freq(CLK_PLLB)/(((CGU_IDE & 0x3c)>>2)+1); | 155 | return calc_freq(CLK_PLLB)/(((CGU_IDE>>2)& 0xf)+1); |
156 | default: | 156 | default: |
157 | return 0; | 157 | return 0; |
158 | } | 158 | } |
diff --git a/firmware/target/arm/as3525/sansa-c200v2/lcd-c200v2.c b/firmware/target/arm/as3525/sansa-c200v2/lcd-c200v2.c index 0ffe0bdc8d..e16b082ce5 100644 --- a/firmware/target/arm/as3525/sansa-c200v2/lcd-c200v2.c +++ b/firmware/target/arm/as3525/sansa-c200v2/lcd-c200v2.c | |||
@@ -98,7 +98,7 @@ static void lcd_delay(int x) | |||
98 | /* DBOP initialisation, do what OF does */ | 98 | /* DBOP initialisation, do what OF does */ |
99 | static void ams3525_dbop_init(void) | 99 | static void ams3525_dbop_init(void) |
100 | { | 100 | { |
101 | CGU_DBOP = (1<<3) | (CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ) - 1); | 101 | CGU_DBOP = (1<<3) | AS3525_DBOP_DIV; |
102 | 102 | ||
103 | DBOP_TIMPOL_01 = 0xe167e167; | 103 | DBOP_TIMPOL_01 = 0xe167e167; |
104 | DBOP_TIMPOL_23 = 0xe167006e; | 104 | DBOP_TIMPOL_23 = 0xe167006e; |
diff --git a/firmware/target/arm/as3525/sansa-clip/lcd-ssd1303.c b/firmware/target/arm/as3525/sansa-clip/lcd-ssd1303.c index 70db6a3f0e..c0df1f766e 100644 --- a/firmware/target/arm/as3525/sansa-clip/lcd-ssd1303.c +++ b/firmware/target/arm/as3525/sansa-clip/lcd-ssd1303.c | |||
@@ -70,7 +70,7 @@ | |||
70 | /* DBOP initialisation, do what OF does */ | 70 | /* DBOP initialisation, do what OF does */ |
71 | static void ams3525_dbop_init(void) | 71 | static void ams3525_dbop_init(void) |
72 | { | 72 | { |
73 | CGU_DBOP = (1<<3) | (CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ) - 1); | 73 | CGU_DBOP = (1<<3) | AS3525_DBOP_DIV; |
74 | 74 | ||
75 | GPIOB_AFSEL = 0x08; /* DBOP on pin 3 */ | 75 | GPIOB_AFSEL = 0x08; /* DBOP on pin 3 */ |
76 | GPIOC_AFSEL = 0x0f; /* DBOP on pins 3:0 */ | 76 | GPIOC_AFSEL = 0x0f; /* DBOP on pins 3:0 */ |
diff --git a/firmware/target/arm/as3525/sansa-e200v2/lcd-e200v2.c b/firmware/target/arm/as3525/sansa-e200v2/lcd-e200v2.c index 9e23dac340..2958298b73 100644 --- a/firmware/target/arm/as3525/sansa-e200v2/lcd-e200v2.c +++ b/firmware/target/arm/as3525/sansa-e200v2/lcd-e200v2.c | |||
@@ -108,7 +108,7 @@ static void lcd_delay(int x) | |||
108 | /* DBOP initialisation, do what OF does */ | 108 | /* DBOP initialisation, do what OF does */ |
109 | static void ams3525_dbop_init(void) | 109 | static void ams3525_dbop_init(void) |
110 | { | 110 | { |
111 | CGU_DBOP = (1<<3) | (CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ) - 1); | 111 | CGU_DBOP = (1<<3) | AS3525_DBOP_DIV; |
112 | 112 | ||
113 | DBOP_TIMPOL_01 = 0xe167e167; | 113 | DBOP_TIMPOL_01 = 0xe167e167; |
114 | DBOP_TIMPOL_23 = 0xe167006e; | 114 | DBOP_TIMPOL_23 = 0xe167006e; |
diff --git a/firmware/target/arm/as3525/sansa-fuze/lcd-fuze.c b/firmware/target/arm/as3525/sansa-fuze/lcd-fuze.c index f0c85f53b4..f713425b9a 100644 --- a/firmware/target/arm/as3525/sansa-fuze/lcd-fuze.c +++ b/firmware/target/arm/as3525/sansa-fuze/lcd-fuze.c | |||
@@ -50,7 +50,7 @@ static bool lcd_busy = false; | |||
50 | 50 | ||
51 | static void as3525_dbop_init(void) | 51 | static void as3525_dbop_init(void) |
52 | { | 52 | { |
53 | CGU_DBOP = (1<<3) | (CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ) - 1); | 53 | CGU_DBOP = (1<<3) | AS3525_DBOP_DIV; |
54 | 54 | ||
55 | DBOP_TIMPOL_01 = 0xe167e167; | 55 | DBOP_TIMPOL_01 = 0xe167e167; |
56 | DBOP_TIMPOL_23 = 0xe167006e; | 56 | DBOP_TIMPOL_23 = 0xe167006e; |
diff --git a/firmware/target/arm/as3525/system-as3525.c b/firmware/target/arm/as3525/system-as3525.c index a5f34d9b80..2f320e91ab 100644 --- a/firmware/target/arm/as3525/system-as3525.c +++ b/firmware/target/arm/as3525/system-as3525.c | |||
@@ -229,29 +229,25 @@ void system_init(void) | |||
229 | CGU_PROC = 0; /* fclk 24 MHz */ | 229 | CGU_PROC = 0; /* fclk 24 MHz */ |
230 | CGU_PERI &= ~0x7f; /* pclk 24 MHz */ | 230 | CGU_PERI &= ~0x7f; /* pclk 24 MHz */ |
231 | 231 | ||
232 | asm volatile( | ||
233 | "mrc p15, 0, r0, c1, c0 \n" | ||
234 | "orr r0, r0, #0xC0000000 \n" /* asynchronous clocking */ | ||
235 | "mcr p15, 0, r0, c1, c0 \n" | ||
236 | : : : "r0" ); | ||
237 | |||
238 | CGU_PLLA = AS3525_PLLA_SETTING; | 232 | CGU_PLLA = AS3525_PLLA_SETTING; |
239 | while(!(CGU_INTCTRL & (1<<0))); /* wait until PLLA is locked */ | 233 | while(!(CGU_INTCTRL & (1<<0))); /* wait until PLLA is locked */ |
240 | 234 | ||
241 | CGU_PROC = (AS3525_CPU_PREDIV << 2) | 1; | 235 | /* Set FCLK frequency */ |
242 | 236 | CGU_PROC = ((AS3525_FCLK_POSTDIV << 4) | | |
243 | CGU_PERI |= ((CLK_DIV(AS3525_PLLA_FREQ, AS3525_PCLK_FREQ) - 1) << 2) | 237 | (AS3525_FCLK_PREDIV << 2) | |
244 | | 1; /* clk_in = PLLA */ | 238 | AS3525_FCLK_SEL); |
239 | /* Set PCLK frequency */ | ||
240 | CGU_PERI = ((CGU_PERI & 0xffffff80) | /* reset divider bits 0:6 */ | ||
241 | (AS3525_PCLK_DIV0 << 2) | | ||
242 | (AS3525_PCLK_DIV1 << 6) | | ||
243 | AS3525_PCLK_SEL); | ||
245 | 244 | ||
246 | |||
247 | /* FIXME: dcache will not be active, since the mmu is not running | ||
248 | * See arm922t datasheet */ | ||
249 | asm volatile( | 245 | asm volatile( |
250 | "mov r0, #0 \n" | 246 | "mov r0, #0 \n" |
251 | "mcr p15, 0, r0, c7, c7 \n" /* invalidate icache & dcache */ | 247 | "mcr p15, 0, r0, c7, c7 \n" /* invalidate icache & dcache */ |
252 | "mrc p15, 0, r0, c1, c0 \n" /* control register */ | 248 | "mrc p15, 0, r0, c1, c0 \n" /* control register */ |
253 | "orr r0, r0, #0x1000 \n" /* enable icache */ | 249 | "bic r0, r0, #3<<30 \n" /* clears bus bits & sets fastbus */ |
254 | "orr r0, r0, #4 \n" /* enable dcache */ | 250 | "orr r0, r0, #1<<12 \n" /* enable icache */ |
255 | "mcr p15, 0, r0, c1, c0 \n" | 251 | "mcr p15, 0, r0, c1, c0 \n" |
256 | : : : "r0" ); | 252 | : : : "r0" ); |
257 | 253 | ||
@@ -281,10 +277,6 @@ void system_init(void) | |||
281 | fmradio_i2c_init(); | 277 | fmradio_i2c_init(); |
282 | #endif | 278 | #endif |
283 | #endif /* !BOOTLOADER */ | 279 | #endif /* !BOOTLOADER */ |
284 | |||
285 | #ifdef HAVE_ADJUSTABLE_CPU_FREQ | ||
286 | set_cpu_frequency(CPUFREQ_DEFAULT); | ||
287 | #endif | ||
288 | } | 280 | } |
289 | 281 | ||
290 | void system_reboot(void) | 282 | void system_reboot(void) |
@@ -311,16 +303,34 @@ int system_memory_guard(int newmode) | |||
311 | #ifdef HAVE_ADJUSTABLE_CPU_FREQ | 303 | #ifdef HAVE_ADJUSTABLE_CPU_FREQ |
312 | void set_cpu_frequency(long frequency) | 304 | void set_cpu_frequency(long frequency) |
313 | { | 305 | { |
314 | int divider = frequency ? (CPUFREQ_MAX / frequency) : 16 /* minimal */ ; | 306 | if(frequency == CPUFREQ_MAX) |
307 | { | ||
315 | 308 | ||
316 | if(divider > 16) | 309 | asm volatile( |
317 | divider = 16; | 310 | "mrc p15, 0, r0, c1, c0 \n" |
318 | else if(divider < 1) | ||
319 | divider = 1; | ||
320 | 311 | ||
321 | cpu_frequency = CPUFREQ_MAX / divider; | 312 | #ifdef ASYNCHRONOUS_BUS |
313 | "orr r0, r0, #3<<30 \n" /* asynchronous bus clocking */ | ||
314 | #else | ||
315 | "bic r0, r0, #3<<30 \n" /* clear bus bits */ | ||
316 | "orr r0, r0, #1<<30 \n" /* synchronous bus clocking */ | ||
317 | #endif | ||
322 | 318 | ||
323 | CGU_PROC = (CGU_PROC & 0x0f) | ((divider-1) << 4); | 319 | "mcr p15, 0, r0, c1, c0 \n" |
320 | : : : "r0" ); | ||
321 | |||
322 | cpu_frequency = CPUFREQ_MAX; | ||
323 | } | ||
324 | else | ||
325 | { | ||
326 | asm volatile( | ||
327 | "mrc p15, 0, r0, c1, c0 \n" | ||
328 | "bic r0, r0, #3<<30 \n" /* fastbus clocking */ | ||
329 | "mcr p15, 0, r0, c1, c0 \n" | ||
330 | : : : "r0" ); | ||
331 | |||
332 | cpu_frequency = CPUFREQ_NORMAL; | ||
333 | } | ||
324 | } | 334 | } |
325 | #endif /* HAVE_ADJUSTABLE_CPU_FREQ */ | 335 | #endif /* HAVE_ADJUSTABLE_CPU_FREQ */ |
326 | #endif /* BOOTLOADER */ | 336 | #endif /* !BOOTLOADER */ |