1 files changed, 95 insertions, 22 deletions
diff --git a/firmware/target/arm/as3525/clock-target.h b/firmware/target/arm/as3525/clock-target.h
index 1928f1fbf2..a6e4927386 100644
--- a/firmware/target/arm/as3525/clock-target.h
+++ b/firmware/target/arm/as3525/clock-target.h
@@ -24,47 +24,120 @@
 /* returns clock divider, given maximal target frequency and clock reference */
 #define CLK_DIV(ref, target) ((ref + target - 1) / target)
-/* PLL */
-#define AS3525_PLLA_FREQ        248000000
+/*  Frequency and Bus Settings
+ *  These bus settings work on the assumption that unboosted performance will be
+ *  based on fastbus mode(FCLK == PCLK) at a frequency configured with this file.
+ *  Boosted performance defaults to synchronous bus but will be changed to
+ *  asynchronous bus if FCLK is not an integer multiple of PCLK.
+ *  The player starts up in fastbus mode and synchronous or asynchronous mode is
+ *  implemented in the set_cpu_frequency() function in system-as3525.c.  There
+ *  are limitations on both frequencies and frequency relationships listed in 7.3.14
+ *  of the as3525 datasheet that need to be observed.  If you are determined to
+ *  use a frequency that is not "legal" you can do that. There are no checks for
+ *  legal frequency values, only some validity checks to make sure the divider
+ *  value fits into the number of bits allotted to it.
+ *
+ *  The CLOCK_DIV macro does a pretty good job at selecting divider values but
+ *  you can always overide it by choosing your own value and commenting out the
+ *  macro.  If you are going to use AS3525_FCLK_PREDIV or AS3525_PCLK_DIV1 you
+ *  will have to do a manual calculation.  I have included USB & PLLB for future
+ *  use but commented them out for now.
+ */
+/* Clock Sources  */
+#define AS3525_CLK_MAIN           0
+#define AS3525_CLK_PLLA           1
+//#define AS3525_CLK_PLLB           2
+#define AS3525_CLK_FCLK           3         /* for synchronous bus only  */
+/* PLL  frequencies and settings*/
+#define AS3525_PLLA_FREQ        248000000   /*124,82.7,62,49.6,41.3,35.4 */
+       /* FCLK_PREDIV->  *7/8 = 217MHz      108.5 ,72.3, 54.25, 43.4, 36.17 */
+                      /* *6/8 = 186MHz      93, 62, 46.5, 37.2 */
+                      /* *5/8 = 155MHz      77.5, 51.67, 38.75 */
 #define AS3525_PLLA_SETTING     0x261F
-/* CPU */
+//#define AS3525_PLLA_FREQ        384000000 /*192,128,96,76.8,64,54.9,48,42.7,38.4*/
+       /* FCLK_PREDIV->  *7/8 = 336MHz      168, 112, 84, 67.2, 56, 48, 42, 37.3*/
+                      /* *6/8 = 288MHz      144, 96, 72, 57.6, 48, 41.1, */
+                      /* *5/8 = 240MHz      120, 80, 60, 48, 40  */
+//#define AS3525_PLLA_SETTING     0x2630
-/* ensure that PLLA_FREQ * prediv == CPUFREQ_MAX */
+/*  PLLB not used at this time! */
-#define AS3525_CPU_PREDIV       0 /* div = 1/1 */
+//#define AS3525_PLLB_FREQ
+//#define AS3525_PLLB_SETTING
-#define CPUFREQ_MAX             248000000
+/** ************ Change these to reconfigure clocking scheme *******************/
-#define CPUFREQ_DEFAULT         24800000
+#define AS3525_FCLK_FREQ         248000000          /* Boosted FCLK frequency  */
+#define AS3525_PCLK_FREQ         62000000           /* Initial PCLK frequency  */
+#define AS3525_DBOP_FREQ         AS3525_PCLK_FREQ   /* Initial DBOP frequency  */
-#define CPUFREQ_NORMAL          31000000
+/** ****************************************************************************/
-/* peripherals */
+/* Figure out if we need to use asynchronous bus */
+#if (AS3525_FCLK_FREQ % AS3525_PCLK_FREQ)
+#define ASYNCHRONOUS_BUS                          /* Boosted mode asynchronous */
+#endif
-#define AS3525_PCLK_FREQ        62000000
+/* Tell the software what frequencies we're running */
-#if (CLK_DIV(AS3525_PLLA_FREQ, AS3525_PCLK_FREQ) - 1) >= (1<<4) /* 4 bits */
+#define CPUFREQ_MAX              AS3525_FCLK_FREQ
-#error PCLK frequency is too low : clock divider will not fit !
+#define CPUFREQ_DEFAULT          AS3525_PCLK_FREQ
+#define CPUFREQ_NORMAL           AS3525_PCLK_FREQ
+/* FCLK */
+#define AS3525_FCLK_SEL          AS3525_CLK_PLLA
+#define AS3525_FCLK_PREDIV       0   /* div = (8-n)/8 acts strange when used!*/
+#define AS3525_FCLK_POSTDIV      (CLK_DIV(AS3525_PLLA_FREQ, AS3525_FCLK_FREQ) - 1) /*div=1/(n+1)*/
+/* PCLK */
+#ifdef ASYNCHRONOUS_BUS
+#define AS3525_PCLK_SEL          AS3525_CLK_PLLA    /* PLLA input for asynchronous */
+#define AS3525_PCLK_DIV0         (CLK_DIV(AS3525_PLLA_FREQ, AS3525_PCLK_FREQ) - 1)/*div=1/(n+1)*/
+#else
+#define AS3525_PCLK_SEL          AS3525_CLK_FCLK    /* Fclk input for synchronous */
+#define AS3525_PCLK_DIV0         (CLK_DIV(AS3525_FCLK_FREQ, AS3525_PCLK_FREQ) - 1) /*div=1/(n+1)*/
 #endif
+#define AS3525_PCLK_DIV1         0 /* div = 1/(n+1) unable to use successfuly so far*/
+   /* PCLK as Source */
+  #define AS3525_DBOP_DIV        (CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ) - 1) /*div=1/(n+1)*/
+  #define AS3525_I2C_PRESCALER   CLK_DIV(AS3525_PCLK_FREQ, AS3525_I2C_FREQ)
+  #define AS3525_I2C_FREQ        400000
+  #define AS3525_SD_IDENT_DIV    ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SD_IDENT_FREQ) / 2) - 1)
+  #define AS3525_SD_IDENT_FREQ   400000      /* must be between 100 & 400 kHz */
-#define AS3525_IDE_FREQ         90000000    /* The OF uses 66MHz maximal freq
+#define AS3525_IDE_SEL           AS3525_CLK_PLLA           /* Input Source   */
+#define AS3525_IDE_DIV           (CLK_DIV(AS3525_PLLA_FREQ, AS3525_IDE_FREQ) - 1)/*div=1/(n+1)*/
+#define AS3525_IDE_FREQ          90000000    /* The OF uses 66MHz maximal freq
                                               but sd transfers fail on some
                                               players with this limit */
+//#define AS3525_USB_SEL           AS3525_CLK_PLLA            /* Input Source   */
+//#define AS3525_USB_DIV           /* div = 1/(n=0?1:2n)*/
+/* Validity Checks */
+/* AS3525_PCLK_FREQ  */
+#if (CLK_DIV(AS3525_PLLA_FREQ, AS3525_PCLK_FREQ) - 1) >= (1<<4) /* 4 bits */
+#error PCLK frequency is too low : clock divider will not fit !
+#endif
+/*  AS3525_DBOP_FREQ */
+#if (CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ) - 1) >= (1<<3) /* 3 bits */
+#error DBOP frequency is too low : clock divider will not fit !
+#endif
+/* AS3525_IDE_FREQ */
 #if (CLK_DIV(AS3525_PLLA_FREQ, AS3525_IDE_FREQ) - 1) >= (1<<4) /* 4 bits */
 #error IDE frequency is too low : clock divider will not fit !
 #endif
+/* AS3525_I2C_FREQ */
-#define AS3525_I2C_FREQ         400000
 #if (CLK_DIV(AS3525_PCLK_FREQ, AS3525_I2C_FREQ)) >= (1<<10) /* 2+8 bits */
 #error I2C frequency is too low : clock divider will not fit !
 #endif
+/* AS3525_SD_IDENT_FREQ */
-#define AS3525_DBOP_FREQ        32000000
-#if (CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ) - 1) >= (1<<3) /* 3 bits */
-#error DBOP frequency is too low : clock divider will not fit !
-#endif
-#define AS3525_SD_IDENT_FREQ    400000      /* must be between 100 & 400 kHz */
 #if ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SD_IDENT_FREQ) / 2) - 1) >= (1<<8) /* 8 bits */
 #error SD IDENTIFICATION frequency is too low : clock divider will not fit !
 #endif

diff --git a/firmware/target/arm/as3525/clock-target.h b/firmware/target/arm/as3525/clock-target.h index 1928f1fbf2..a6e4927386 100644 --- a/firmware/target/arm/as3525/clock-target.h +++ b/firmware/target/arm/as3525/clock-target.h
@@ -24,47 +24,120 @@
24	/* returns clock divider, given maximal target frequency and clock reference */	24	/* returns clock divider, given maximal target frequency and clock reference */
25	#define CLK_DIV(ref, target) ((ref + target - 1) / target)	25	#define CLK_DIV(ref, target) ((ref + target - 1) / target)
26		26
27	/* PLL */
28		27
29	#define AS3525_PLLA_FREQ 248000000	28	/* Frequency and Bus Settings
		29	* These bus settings work on the assumption that unboosted performance will be
		30	* based on fastbus mode(FCLK == PCLK) at a frequency configured with this file.
		31	* Boosted performance defaults to synchronous bus but will be changed to
		32	* asynchronous bus if FCLK is not an integer multiple of PCLK.
		33	* The player starts up in fastbus mode and synchronous or asynchronous mode is
		34	* implemented in the set_cpu_frequency() function in system-as3525.c. There
		35	* are limitations on both frequencies and frequency relationships listed in 7.3.14
		36	* of the as3525 datasheet that need to be observed. If you are determined to
		37	* use a frequency that is not "legal" you can do that. There are no checks for
		38	* legal frequency values, only some validity checks to make sure the divider
		39	* value fits into the number of bits allotted to it.
		40	*
		41	* The CLOCK_DIV macro does a pretty good job at selecting divider values but
		42	* you can always overide it by choosing your own value and commenting out the
		43	* macro. If you are going to use AS3525_FCLK_PREDIV or AS3525_PCLK_DIV1 you
		44	* will have to do a manual calculation. I have included USB & PLLB for future
		45	* use but commented them out for now.
		46	*/
		47
		48	/* Clock Sources */
		49	#define AS3525_CLK_MAIN 0
		50	#define AS3525_CLK_PLLA 1
		51	//#define AS3525_CLK_PLLB 2
		52	#define AS3525_CLK_FCLK 3 /* for synchronous bus only */
		53
		54	/* PLL frequencies and settings*/
		55
		56	#define AS3525_PLLA_FREQ 248000000 /124,82.7,62,49.6,41.3,35.4 /
		57	/* FCLK_PREDIV-> 7/8 = 217MHz 108.5 ,72.3, 54.25, 43.4, 36.17 /
		58	/* 6/8 = 186MHz 93, 62, 46.5, 37.2 /
		59	/* 5/8 = 155MHz 77.5, 51.67, 38.75 /
30	#define AS3525_PLLA_SETTING 0x261F	60	#define AS3525_PLLA_SETTING 0x261F
31		61
32	/* CPU */	62	//#define AS3525_PLLA_FREQ 384000000 /192,128,96,76.8,64,54.9,48,42.7,38.4/
		63	/* FCLK_PREDIV-> 7/8 = 336MHz 168, 112, 84, 67.2, 56, 48, 42, 37.3/
		64	/* 6/8 = 288MHz 144, 96, 72, 57.6, 48, 41.1, /
		65	/* 5/8 = 240MHz 120, 80, 60, 48, 40 /
		66	//#define AS3525_PLLA_SETTING 0x2630
33		67
34	/* ensure that PLLA_FREQ * prediv == CPUFREQ_MAX */	68	/* PLLB not used at this time! */
35	#define AS3525_CPU_PREDIV 0 /* div = 1/1 */	69	//#define AS3525_PLLB_FREQ
		70	//#define AS3525_PLLB_SETTING
36		71
37	#define CPUFREQ_MAX 248000000	72	/ ******** Change these to reconfigure clocking scheme *****************/
38		73
39	#define CPUFREQ_DEFAULT 24800000	74	#define AS3525_FCLK_FREQ 248000000 /* Boosted FCLK frequency */
		75	#define AS3525_PCLK_FREQ 62000000 /* Initial PCLK frequency */
		76	#define AS3525_DBOP_FREQ AS3525_PCLK_FREQ /* Initial DBOP frequency */
40		77
41	#define CPUFREQ_NORMAL 31000000	78	/ **************************************************************************/
42		79
43	/* peripherals */	80	/* Figure out if we need to use asynchronous bus */
		81	#if (AS3525_FCLK_FREQ % AS3525_PCLK_FREQ)
		82	#define ASYNCHRONOUS_BUS /* Boosted mode asynchronous */
		83	#endif
44		84
45	#define AS3525_PCLK_FREQ 62000000	85	/* Tell the software what frequencies we're running */
46	#if (CLK_DIV(AS3525_PLLA_FREQ, AS3525_PCLK_FREQ) - 1) >= (1<<4) /* 4 bits */	86	#define CPUFREQ_MAX AS3525_FCLK_FREQ
47	#error PCLK frequency is too low : clock divider will not fit !	87	#define CPUFREQ_DEFAULT AS3525_PCLK_FREQ
		88	#define CPUFREQ_NORMAL AS3525_PCLK_FREQ
		89
		90	/* FCLK */
		91	#define AS3525_FCLK_SEL AS3525_CLK_PLLA
		92	#define AS3525_FCLK_PREDIV 0 /* div = (8-n)/8 acts strange when used!*/
		93	#define AS3525_FCLK_POSTDIV (CLK_DIV(AS3525_PLLA_FREQ, AS3525_FCLK_FREQ) - 1) /div=1/(n+1)/
		94
		95	/* PCLK */
		96	#ifdef ASYNCHRONOUS_BUS
		97	#define AS3525_PCLK_SEL AS3525_CLK_PLLA /* PLLA input for asynchronous */
		98	#define AS3525_PCLK_DIV0 (CLK_DIV(AS3525_PLLA_FREQ, AS3525_PCLK_FREQ) - 1)/div=1/(n+1)/
		99	#else
		100	#define AS3525_PCLK_SEL AS3525_CLK_FCLK /* Fclk input for synchronous */
		101	#define AS3525_PCLK_DIV0 (CLK_DIV(AS3525_FCLK_FREQ, AS3525_PCLK_FREQ) - 1) /div=1/(n+1)/
48	#endif	102	#endif
		103	#define AS3525_PCLK_DIV1 0 /* div = 1/(n+1) unable to use successfuly so far*/
		104
		105	/* PCLK as Source */
		106	#define AS3525_DBOP_DIV (CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ) - 1) /div=1/(n+1)/
		107	#define AS3525_I2C_PRESCALER CLK_DIV(AS3525_PCLK_FREQ, AS3525_I2C_FREQ)
		108	#define AS3525_I2C_FREQ 400000
		109	#define AS3525_SD_IDENT_DIV ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SD_IDENT_FREQ) / 2) - 1)
		110	#define AS3525_SD_IDENT_FREQ 400000 /* must be between 100 & 400 kHz */
49		111
50	#define AS3525_IDE_FREQ 90000000 /* The OF uses 66MHz maximal freq	112	#define AS3525_IDE_SEL AS3525_CLK_PLLA /* Input Source */
		113	#define AS3525_IDE_DIV (CLK_DIV(AS3525_PLLA_FREQ, AS3525_IDE_FREQ) - 1)/div=1/(n+1)/
		114	#define AS3525_IDE_FREQ 90000000 /* The OF uses 66MHz maximal freq
51	but sd transfers fail on some	115	but sd transfers fail on some
52	players with this limit */	116	players with this limit */
		117
		118	//#define AS3525_USB_SEL AS3525_CLK_PLLA /* Input Source */
		119	//#define AS3525_USB_DIV /* div = 1/(n=0?1:2n)*/
		120
		121
		122	/* Validity Checks */
		123
		124	/* AS3525_PCLK_FREQ */
		125	#if (CLK_DIV(AS3525_PLLA_FREQ, AS3525_PCLK_FREQ) - 1) >= (1<<4) /* 4 bits */
		126	#error PCLK frequency is too low : clock divider will not fit !
		127	#endif
		128	/* AS3525_DBOP_FREQ */
		129	#if (CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ) - 1) >= (1<<3) /* 3 bits */
		130	#error DBOP frequency is too low : clock divider will not fit !
		131	#endif
		132	/* AS3525_IDE_FREQ */
53	#if (CLK_DIV(AS3525_PLLA_FREQ, AS3525_IDE_FREQ) - 1) >= (1<<4) /* 4 bits */	133	#if (CLK_DIV(AS3525_PLLA_FREQ, AS3525_IDE_FREQ) - 1) >= (1<<4) /* 4 bits */
54	#error IDE frequency is too low : clock divider will not fit !	134	#error IDE frequency is too low : clock divider will not fit !
55	#endif	135	#endif
56		136	/* AS3525_I2C_FREQ */
57	#define AS3525_I2C_FREQ 400000
58	#if (CLK_DIV(AS3525_PCLK_FREQ, AS3525_I2C_FREQ)) >= (1<<10) /* 2+8 bits */	137	#if (CLK_DIV(AS3525_PCLK_FREQ, AS3525_I2C_FREQ)) >= (1<<10) /* 2+8 bits */
59	#error I2C frequency is too low : clock divider will not fit !	138	#error I2C frequency is too low : clock divider will not fit !
60	#endif	139	#endif
61		140	/* AS3525_SD_IDENT_FREQ */
62	#define AS3525_DBOP_FREQ 32000000
63	#if (CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ) - 1) >= (1<<3) /* 3 bits */
64	#error DBOP frequency is too low : clock divider will not fit !
65	#endif
66
67	#define AS3525_SD_IDENT_FREQ 400000 /* must be between 100 & 400 kHz */
68	#if ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SD_IDENT_FREQ) / 2) - 1) >= (1<<8) /* 8 bits */	141	#if ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SD_IDENT_FREQ) / 2) - 1) >= (1<<8) /* 8 bits */
69	#error SD IDENTIFICATION frequency is too low : clock divider will not fit !	142	#error SD IDENTIFICATION frequency is too low : clock divider will not fit !
70	#endif	143	#endif