diff options
| author | Michael Sevakis <jethead71@rockbox.org> | 2010-04-09 13:21:32 +0000 |
|---|---|---|
| committer | Michael Sevakis <jethead71@rockbox.org> | 2010-04-09 13:21:32 +0000 |
| commit | eb755ec351507c8706fc8cd0e292349034ddbe68 (patch) | |
| tree | ccd09ff319b83bc984fe87bbf69308e2cec24b6f | |
| parent | bad4142ce2eb1d2e5311cc3fab416b6544ca4634 (diff) | |
| download | rockbox-eb755ec351507c8706fc8cd0e292349034ddbe68.tar.gz rockbox-eb755ec351507c8706fc8cd0e292349034ddbe68.zip | |
Gigabeat S: Slow down the SPI clock to 1/8 current speed. It seems lower voltages can reveal the weakness that forbids maximum-speed clocking per the SPI spec. OF leaves it set much slower. Push it a bit over OF since it's been gotten away with fairly cleanly so far. Settings on pins and interface to be more thoroughly investigated.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25554 a1c6a512-1295-4272-9138-f99709370657
| -rw-r--r-- | firmware/target/arm/imx31/mc13783-imx31.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/firmware/target/arm/imx31/mc13783-imx31.c b/firmware/target/arm/imx31/mc13783-imx31.c index fc5dfa72f6..9b7248dc45 100644 --- a/firmware/target/arm/imx31/mc13783-imx31.c +++ b/firmware/target/arm/imx31/mc13783-imx31.c | |||
| @@ -38,7 +38,7 @@ static struct spi_node mc13783_spi = | |||
| 38 | CSPI2_NUM, /* CSPI module 2 */ | 38 | CSPI2_NUM, /* CSPI module 2 */ |
| 39 | CSPI_CONREG_CHIP_SELECT_SS0 | /* Chip select 0 */ | 39 | CSPI_CONREG_CHIP_SELECT_SS0 | /* Chip select 0 */ |
| 40 | CSPI_CONREG_DRCTL_DONT_CARE | /* Don't care about CSPI_RDY */ | 40 | CSPI_CONREG_DRCTL_DONT_CARE | /* Don't care about CSPI_RDY */ |
| 41 | CSPI_CONREG_DATA_RATE_DIV_4 | /* Clock = IPG_CLK/4 - 16.5MHz */ | 41 | CSPI_CONREG_DATA_RATE_DIV_32 | /* Clock = IPG_CLK/32 = 2,062,500Hz. */ |
| 42 | CSPI_BITCOUNT(32-1) | /* All 32 bits are to be transferred */ | 42 | CSPI_BITCOUNT(32-1) | /* All 32 bits are to be transferred */ |
| 43 | CSPI_CONREG_SSPOL | /* SS active high */ | 43 | CSPI_CONREG_SSPOL | /* SS active high */ |
| 44 | CSPI_CONREG_SSCTL | /* Negate SS between SPI bursts */ | 44 | CSPI_CONREG_SSCTL | /* Negate SS between SPI bursts */ |