imx233: generate register headers using headergen_v2 and update code for it

NOTE: this commit does not introduce any change, ideally even the binary should
be almost the same. I checked the disassembly by hand and there are only a few
differences here and there, mostly the compiler decides to compile very close
expressions slightly differently. I tried to run the new code on several targets
to make sure and saw no difference.

The major syntax changes of the new headers are as follows:
- BF_{WR,SET,CLR} are now superpowerful and allows to set several fileds at once:
  BF_WR(reg, field1(value1), field2(value2), ...)
- BF_CS (use like BF_WR) does a write to reg_CLR and then reg_SET instead of RMW
- there is no more need for macros like BF_{WR_,SET,CLR}_V, since one can simply
  BF_WR with field_V(name)
- the old BF_SETV macro has no trivial equivalent and is replaced with its
  its equivalent for BF_WR(reg_SET, ...)

I also rename the register headers: "regs/regs-x.h" -> "regs/x.h" to avoid the
redundant "regs".

Final note: the registers were generated using the following command:
./headergen_v2 -g imx -o ../../firmware/target/arm/imx233/regs/ desc/regs-stmp3{600,700,780}.xml

Change-Id: I7485e8b4315a0929a8edb63e7fa1edcaa54b1edc

306 files changed, 66936 insertions, 42319 deletions

diff --git a/firmware/drivers/rtc/rtc_imx233.c b/firmware/drivers/rtc/rtc_imx233.c
index c2df4d13dc..df139dbf41 100644
--- a/firmware/drivers/rtc/rtc_imx233.c
+++ b/firmware/drivers/rtc/rtc_imx233.c
@@ -114,9 +114,9 @@ void rtc_enable_alarm(bool enable)
     BF_CLR(RTC_CTRL, ALARM_IRQ_EN);
     BF_CLR(RTC_CTRL, ALARM_IRQ);
     uint32_t val = imx233_rtc_read_persistent(0);
-    BF_WRX(val, RTC_PERSISTENT0, ALARM_EN, enable);
-    BF_WRX(val, RTC_PERSISTENT0, ALARM_WAKE_EN, enable);
-    BF_WRX(val, RTC_PERSISTENT0, ALARM_WAKE, 0);
+    BF_WRX(val, RTC_PERSISTENT0, ALARM_EN(enable));
+    BF_WRX(val, RTC_PERSISTENT0, ALARM_WAKE_EN(enable));
+    BF_WRX(val, RTC_PERSISTENT0, ALARM_WAKE(0));
     imx233_rtc_write_persistent(0, val);
 }
 
diff --git a/firmware/target/arm/imx233/ata-imx233.c b/firmware/target/arm/imx233/ata-imx233.c
index da546ab2a1..6abd486862 100644
--- a/firmware/target/arm/imx233/ata-imx233.c
+++ b/firmware/target/arm/imx233/ata-imx233.c
@@ -28,7 +28,7 @@
 #include "ata-target.h"
 #include "ata-defines.h"
 
-#include "regs/regs-gpmi.h"
+#include "regs/gpmi.h"
 
 struct pio_timing_t
 {
@@ -60,11 +60,8 @@ static uint16_t imx233_ata_read_reg(unsigned reg)
     imx233_ata_wait_ready();
 
     /* setup command */
-    HW_GPMI_CTRL0 = BF_OR6(GPMI_CTRL0, RUN(1),
-        COMMAND_MODE(BV_GPMI_CTRL0_COMMAND_MODE__READ),
-        WORD_LENGTH(BV_GPMI_CTRL0_WORD_LENGTH__16_BIT),
-        CS(IMX233_ATA_REG_CS(reg)), ADDRESS(IMX233_ATA_REG_ADDR(reg)),
-        XFER_COUNT(1));
+    BF_WR_ALL(GPMI_CTRL0, RUN(1), COMMAND_MODE_V(READ), WORD_LENGTH_V(16_BIT),
+        CS(IMX233_ATA_REG_CS(reg)), ADDRESS(IMX233_ATA_REG_ADDR(reg)), XFER_COUNT(1));
 
     /* wait for completion */
     while(BF_RD(GPMI_STAT, FIFO_EMPTY));
@@ -79,11 +76,8 @@ static void imx233_ata_write_reg(unsigned reg, uint16_t data)
     imx233_ata_wait_ready();
 
     /* setup command */
-    HW_GPMI_CTRL0 = BF_OR6(GPMI_CTRL0, RUN(1),
-        COMMAND_MODE(BV_GPMI_CTRL0_COMMAND_MODE__WRITE),
-        WORD_LENGTH(BV_GPMI_CTRL0_WORD_LENGTH__16_BIT),
-        CS(IMX233_ATA_REG_CS(reg)), ADDRESS(IMX233_ATA_REG_ADDR(reg)),
-        XFER_COUNT(1));
+    BF_WR_ALL(GPMI_CTRL0, RUN(1), COMMAND_MODE_V(WRITE), WORD_LENGTH_V(16_BIT),
+        CS(IMX233_ATA_REG_CS(reg)), ADDRESS(IMX233_ATA_REG_ADDR(reg)), XFER_COUNT(1));
 
     /* send data */
     HW_GPMI_DATA = data;
@@ -123,16 +117,16 @@ void ata_set_pio_timings(int mode)
     adjust_to_clock(t.data_setup);
     /* write */
     imx233_ata_wait_ready();
-    HW_GPMI_TIMING0 = BF_OR3(GPMI_TIMING0, ADDRESS_SETUP(t.addr_setup),
-        DATA_HOLD(t.data_hold), DATA_SETUP(t.data_setup));
+    BF_WR_ALL(GPMI_TIMING0, ADDRESS_SETUP(t.addr_setup), DATA_HOLD(t.data_hold),
+        DATA_SETUP(t.data_setup));
 }
 
 void ata_reset(void)
 {
     /* reset device */
-    BF_WR_V(GPMI_CTRL1, DEV_RESET, ENABLED);
+    BF_WR(GPMI_CTRL1, DEV_RESET_V(ENABLED));
     sleep(HZ / 10);
-    BF_WR_V(GPMI_CTRL1, DEV_RESET, DISABLED);
+    BF_WR(GPMI_CTRL1, DEV_RESET_V(DISABLED));
 }
 
 void ata_enable(bool on)
@@ -212,7 +206,7 @@ void ata_device_init(void)
     imx233_pinctrl_setup_vpin(VPIN_GPMI_RDn, "ata rd", PINCTRL_DRIVE_4mA, false);
     imx233_pinctrl_setup_vpin(VPIN_GPMI_WRn, "ata wr", PINCTRL_DRIVE_4mA, false);
     /* setup ata mode */
-    BF_WR_V(GPMI_CTRL1, GPMI_MODE, ATA);
+    BF_WR(GPMI_CTRL1, GPMI_MODE_V(ATA));
     /* reset device */
     ata_reset();
     ata_enable(true);
diff --git a/firmware/target/arm/imx233/audioin-imx233.c b/firmware/target/arm/imx233/audioin-imx233.c
index 859e65f813..e538765244 100644
--- a/firmware/target/arm/imx233/audioin-imx233.c
+++ b/firmware/target/arm/imx233/audioin-imx233.c
@@ -22,6 +22,10 @@
 #include "pcm_sampr.h"
 #include "string.h"
 
+#include "regs/audioin.h"
+/* some audioout registers impact audioin */
+#include "regs/audioout.h"
+
 /* values in half-dB, one for each setting */
 static int audioin_vol[2][4]; /* 0=left, 1=right */
 static int audioin_select[2]; /* idem */
@@ -87,35 +91,35 @@ static void apply_config(void)
     {
         /* take lowest microphone gain to get back into the -100..22 range
          * achievable with mux+adc.*/
-        
+
         /* from 52.5 dB and beyond: 40dB gain */
         if(vol_l > 52 * 2)
         {
-            BF_WR_V(AUDIOIN_MICLINE, MIC_GAIN, 40dB);
+            BF_WR(AUDIOIN_MICLINE, MIC_GAIN_V(40dB));
             vol_l -= 40 * 2;
         }
         /* from 42.5 dB to 52dB: 30dB gain */
         else if(vol_l > 42 * 2)
         {
-            BF_WR_V(AUDIOIN_MICLINE, MIC_GAIN, 30dB);
+            BF_WR(AUDIOIN_MICLINE, MIC_GAIN_V(30dB));
             vol_l -= 30 * 2;
         }
         /* from 22.5 dB to 42dB: 20dB gain */
         else if(vol_l > 22 * 2)
         {
-            BF_WR_V(AUDIOIN_MICLINE, MIC_GAIN, 20dB);
+            BF_WR(AUDIOIN_MICLINE, MIC_GAIN_V(20dB));
             vol_l -= 20 * 2;
         }
         /* otherwise 0dB gain */
         else
-            BF_WR_V(AUDIOIN_MICLINE, MIC_GAIN, 0dB);
+            BF_WR(AUDIOIN_MICLINE, MIC_GAIN_V(0dB));
     }
     /* max is 22dB */
     vol_l = MIN(vol_l, 44);
     vol_r = MIN(vol_r, 44);
     /* we use the mux volume to reach the volume or higher with 1.5dB steps
      * and then we use the ADC to go below 0dB or to obtain 0.5dB accuracy */
-    
+
     int mux_vol_l = MAX(0, (vol_l + 2) / 3); /* 1.5dB = 3 * 0.5dB */
     int mux_vol_r = MAX(0, (vol_r + 2) / 3);
 #if IMX233_SUBTARGET >= 3700
@@ -123,7 +127,7 @@ static void apply_config(void)
 #else
     unsigned adc_zcd = 0;
 #endif
-    HW_AUDIOIN_ADCVOL = adc_zcd | BF_OR4(AUDIOIN_ADCVOL, SELECT_LEFT(select_l),
+    HW_AUDIOIN_ADCVOL = adc_zcd | BF_OR(AUDIOIN_ADCVOL, SELECT_LEFT(select_l),
         SELECT_RIGHT(select_r), GAIN_LEFT(mux_vol_l), GAIN_RIGHT(mux_vol_r));
 
     vol_l -= mux_vol_l * 3; /* mux vol is in 1.5dB = 3 * 0.5dB steps */
@@ -133,7 +137,7 @@ static void apply_config(void)
 
     /* unmute, enable zero cross and set volume.
      * 0xfe is -0.5dB */
-    HW_AUDIOIN_ADCVOLUME = BF_OR3(AUDIOIN_ADCVOLUME, EN_ZCD(1),
+    BF_WR_ALL(AUDIOIN_ADCVOLUME, EN_ZCD(1),
         VOLUME_LEFT(0xff + vol_l), VOLUME_RIGHT(0xff + vol_r));
 }
 
@@ -153,12 +157,12 @@ void imx233_audioin_enable_mic(bool enable)
 {
     if(enable)
     {
-        BF_WR_V(AUDIOIN_MICLINE, MIC_RESISTOR, 2KOhm);
-        BF_WR(AUDIOIN_MICLINE, MIC_BIAS, 4);
-        BF_WR(AUDIOIN_MICLINE, MIC_SELECT, 1);
+        BF_WR(AUDIOIN_MICLINE, MIC_RESISTOR_V(2KOhm));
+        BF_WR(AUDIOIN_MICLINE, MIC_BIAS(4));
+        BF_WR(AUDIOIN_MICLINE, MIC_SELECT(1));
     }
     else
-        BF_WR_V(AUDIOIN_MICLINE, MIC_RESISTOR, Off);
+        BF_WR(AUDIOIN_MICLINE, MIC_RESISTOR_V(Off));
 }
 
 void imx233_audioin_set_freq(int fsel)
@@ -185,7 +189,7 @@ void imx233_audioin_set_freq(int fsel)
         HW_HAVE_96_([HW_FREQ_96] = { 0x2, 0x0, 0xf, 0x13ff },)
     };
 
-    HW_AUDIOIN_ADCSRR = BF_OR4(AUDIOIN_ADCSRR,
+    BF_WR_ALL(AUDIOIN_ADCSRR,
         SRC_FRAC(dacssr[fsel].src_frac), SRC_INT(dacssr[fsel].src_int),
         SRC_HOLD(dacssr[fsel].src_hold), BASEMULT(dacssr[fsel].base_mult));
 }
diff --git a/firmware/target/arm/imx233/audioin-imx233.h b/firmware/target/arm/imx233/audioin-imx233.h
index 12c7b1dad5..4aef88ac0c 100644
--- a/firmware/target/arm/imx233/audioin-imx233.h
+++ b/firmware/target/arm/imx233/audioin-imx233.h
@@ -25,10 +25,6 @@
 #include "cpu.h"
 #include "system.h"
 
-#include "regs/regs-audioin.h"
-/* some audioout registers impact audioin */
-#include "regs/regs-audioout.h"
-
 #define AUDIOIN_SELECT_MICROPHONE   0
 #define AUDIOIN_SELECT_LINE1        1
 #define AUDIOIN_SELECT_HEADPHONE    2
diff --git a/firmware/target/arm/imx233/audioout-imx233.c b/firmware/target/arm/imx233/audioout-imx233.c
index 887d9d77f7..6ebeb8a469 100644
--- a/firmware/target/arm/imx233/audioout-imx233.c
+++ b/firmware/target/arm/imx233/audioout-imx233.c
@@ -30,6 +30,8 @@
 #include "audio-target.h"
 #include "power-imx233.h"
 
+#include "regs/audioout.h"
+
 #ifndef IMX233_AUDIO_COUPLING_MODE
 #error You must define IMX233_AUDIO_COUPLING_MODE
 #endif
@@ -75,8 +77,8 @@ void imx233_audioout_preinit(void)
     /* Set HP mode to AB */
     BF_SET(AUDIOOUT_ANACTRL, HP_CLASSAB);
     /* change bias to -50% */
-    BF_WR(AUDIOOUT_TEST, HP_I1_ADJ, 1);
-    BF_WR(AUDIOOUT_REFCTRL, BIAS_CTRL, 1);
+    BF_WR(AUDIOOUT_TEST, HP_I1_ADJ(1));
+    BF_WR(AUDIOOUT_REFCTRL, BIAS_CTRL(1));
 #if IMX233_SUBTARGET >= 3700
     BF_SET(AUDIOOUT_REFCTRL, RAISE_REF);
 #endif
@@ -84,11 +86,11 @@ void imx233_audioout_preinit(void)
     /* Stop holding to ground */
     BF_CLR(AUDIOOUT_ANACTRL, HP_HOLD_GND);
     /* Set dmawait count to 31 (see errata, workaround random stop) */
-    BF_WR(AUDIOOUT_CTRL, DMAWAIT_COUNT, 31);
+    BF_WR(AUDIOOUT_CTRL, DMAWAIT_COUNT(31));
     /* start converting audio */
     BF_SET(AUDIOOUT_CTRL, RUN);
     /* unmute DAC */
-    HW_AUDIOOUT_DACVOLUME_CLR = BM_OR2(AUDIOOUT_DACVOLUME, MUTE_LEFT, MUTE_RIGHT);
+    BF_CLR(AUDIOOUT_DACVOLUME, MUTE_LEFT, MUTE_RIGHT);
     /* send a few samples to avoid pop */
     HW_AUDIOOUT_DATA = 0;
     HW_AUDIOOUT_DATA = 0;
@@ -113,7 +115,7 @@ void imx233_audioout_close(void)
     /* Power down HP */
     BF_SET(AUDIOOUT_PWRDN, HEADPHONE);
     /* Mute DAC */
-    HW_AUDIOOUT_DACVOLUME_SET = BM_OR2(AUDIOOUT_DACVOLUME, MUTE_LEFT, MUTE_RIGHT);
+    BF_SET(AUDIOOUT_DACVOLUME, MUTE_LEFT, MUTE_RIGHT);
     /* Power down DAC */
     BF_SET(AUDIOOUT_PWRDN, DAC);
     /* Gate off DAC */
@@ -133,8 +135,8 @@ static void set_dac_vol(int vol_l, int vol_r)
     vol_r = MAX(-200, MIN(vol_r, 0));
     /* unmute, enable zero cross and set volume.
      * 0xff is 0dB */
-    HW_AUDIOOUT_DACVOLUME = BF_OR3(AUDIOOUT_DACVOLUME,
-        VOLUME_LEFT(0xff + vol_l), VOLUME_RIGHT(0xff + vol_r), EN_ZCD(1));
+    BF_WR_ALL(AUDIOOUT_DACVOLUME, VOLUME_LEFT(0xff + vol_l),
+        VOLUME_RIGHT(0xff + vol_r), EN_ZCD(1));
 }
 
 /* volume in half dB
@@ -154,7 +156,7 @@ static void set_hp_vol(int vol_l, int vol_r)
 #else
     unsigned mstr_zcd = 0;
 #endif
-    HW_AUDIOOUT_HPVOL = mstr_zcd | BF_OR3(AUDIOOUT_HPVOL, SELECT(input_line1),
+    HW_AUDIOOUT_HPVOL = mstr_zcd | BF_OR(AUDIOOUT_HPVOL, SELECT(input_line1),
         VOL_LEFT(max - vol_l), VOL_RIGHT(max - vol_r));
 }
 
@@ -206,10 +208,10 @@ void imx233_audioout_set_freq(int fsel)
         HW_HAVE_96_([HW_FREQ_96] = { 0x2, 0x0, 0xf, 0x13ff },)
     };
 
-    HW_AUDIOOUT_DACSRR = BF_OR4(AUDIOOUT_DACSRR,
+    BF_WR_ALL(AUDIOOUT_DACSRR,
         SRC_FRAC(dacssr[fsel].src_frac), SRC_INT(dacssr[fsel].src_int),
         SRC_HOLD(dacssr[fsel].src_hold), BASEMULT(dacssr[fsel].base_mult));
-    
+
     #if 0
     /* Select base_mult and src_hold depending on the audio range:
      *     0 < f <= 12000   --> base_mult = 1, src_hold = 3 (div by 4)
@@ -250,15 +252,15 @@ void imx233_audioout_set_3d_effect(int val)
     switch(val)
     {
         /* 0 and 1.5dB: off */
-        case 0: case 1: BF_WR(AUDIOOUT_CTRL, SS3D_EFFECT, 0); break;
+        case 0: case 1: BF_WR(AUDIOOUT_CTRL, SS3D_EFFECT(0)); break;
         /* 3dB: low */
-        case 2: BF_WR(AUDIOOUT_CTRL, SS3D_EFFECT, 1); break;
+        case 2: BF_WR(AUDIOOUT_CTRL, SS3D_EFFECT(1)); break;
         /* 4.5dB: low */
-        case 3: BF_WR(AUDIOOUT_CTRL, SS3D_EFFECT, 2); break;
+        case 3: BF_WR(AUDIOOUT_CTRL, SS3D_EFFECT(2)); break;
         /* 6dB: low */
-        case 4: BF_WR(AUDIOOUT_CTRL, SS3D_EFFECT, 3); break;
+        case 4: BF_WR(AUDIOOUT_CTRL, SS3D_EFFECT(3)); break;
         /* others: off */
-        default: BF_WR(AUDIOOUT_CTRL, SS3D_EFFECT, 0); break;
+        default: BF_WR(AUDIOOUT_CTRL, SS3D_EFFECT(0)); break;
     }
 }
 
@@ -285,7 +287,7 @@ void imx233_audioout_enable_spkr(bool en)
     if(en)
     {
         /** 1) make sure charge capacitors are discharged */
-        BF_WR(AUDIOOUT_LINEOUTCTRL, CHARGE_CAP, 2);
+        BF_WR(AUDIOOUT_LINEOUTCTRL, CHARGE_CAP(2));
         /** 2) set min gain, nominal vag levels and zerocross desires */
         /* volume is decreasing with the value in the register */
         BF_SET(AUDIOOUT_LINEOUTCTRL, VOLUME_LEFT);
@@ -294,22 +296,22 @@ void imx233_audioout_enable_spkr(bool en)
         /* vag should be set to VDDIO/2, 0 is 1.725V, 15 is 1.350V, 25mV steps */
         int vddio;
         imx233_power_get_regulator(REGULATOR_VDDIO, &vddio, NULL);
-        BF_WR(AUDIOOUT_LINEOUTCTRL, VAG_CTRL, 15 - (vddio / 2 - 1350) / 25);
+        BF_WR(AUDIOOUT_LINEOUTCTRL, VAG_CTRL(15 - (vddio / 2 - 1350) / 25));
         /** 3) Power up lineout */
         BF_CLR(AUDIOOUT_PWRDN, LINEOUT);
         /** 4) Ramp the vag */
-        BF_WR(AUDIOOUT_LINEOUTCTRL, CHARGE_CAP, 1);
+        BF_WR(AUDIOOUT_LINEOUTCTRL, CHARGE_CAP(1));
         /** 5) Unmute */
         BF_CLR(AUDIOOUT_LINEOUTCTRL, MUTE);
         /** 6) Ramp volume */
-        BF_WR(AUDIOOUT_LINEOUTCTRL, VOLUME_LEFT, 0);
-        BF_WR(AUDIOOUT_LINEOUTCTRL, VOLUME_RIGHT, 0);
+        BF_WR(AUDIOOUT_LINEOUTCTRL, VOLUME_LEFT(0));
+        BF_WR(AUDIOOUT_LINEOUTCTRL, VOLUME_RIGHT(0));
     }
     else
     {
         /** Reverse procedure */
         BF_SET(AUDIOOUT_LINEOUTCTRL, MUTE);
-        BF_WR(AUDIOOUT_LINEOUTCTRL, CHARGE_CAP, 2);
+        BF_WR(AUDIOOUT_LINEOUTCTRL, CHARGE_CAP(2));
         BF_SET(AUDIOOUT_PWRDN, LINEOUT);
     }
 #else
diff --git a/firmware/target/arm/imx233/audioout-imx233.h b/firmware/target/arm/imx233/audioout-imx233.h
index 47bb815a08..c819fdb294 100644
--- a/firmware/target/arm/imx233/audioout-imx233.h
+++ b/firmware/target/arm/imx233/audioout-imx233.h
@@ -25,8 +25,6 @@
 #include "cpu.h"
 #include "system.h"
 
-#include "regs/regs-audioout.h"
-
 /* target-defined output stage coupling method
  * its setting is IMX233_AUDIO_COUPLING_MODE and must be set for every target
  * Use ACM_CAP if output stage (i.e. headphones) have output capacitors,
diff --git a/firmware/target/arm/imx233/button-imx233.h b/firmware/target/arm/imx233/button-imx233.h
index 61adff8436..27ae03c63f 100644
--- a/firmware/target/arm/imx233/button-imx233.h
+++ b/firmware/target/arm/imx233/button-imx233.h
@@ -101,11 +101,11 @@ struct imx233_button_map_t
 #define IMX233_BUTTON_NAMEFLAGS3(_,name_,f1,f2)   .name = name_, \
     .flags = IMX233_BUTTON_##f1 | IMX233_BUTTON_##f2
 #define IMX233_BUTTON_NAMEFLAGS4(_,name_,f1,f2,f3)    .name = name_, \
-    .flags =IMX233_BUTTON_##f1 | IMX233_BUTTON_##f2 | IMX233_BUTTON_##f3
+    .flags = IMX233_BUTTON_##f1 | IMX233_BUTTON_##f2 | IMX233_BUTTON_##f3
 
 #define IMX233_BUTTON__(btn_, path_, ...) \
     {.btn = btn_, IMX233_BUTTON_PATH_##path_, \
-     REG_VARIADIC(IMX233_BUTTON_NAMEFLAGS, dummy, __VA_ARGS__)}
+     __VAR_EXPAND(IMX233_BUTTON_NAMEFLAGS, dummy, __VA_ARGS__)}
 #define IMX233_BUTTON_(btn_, path_, ...) \
     IMX233_BUTTON__(IMX233_BUTTON_##btn_, path_, __VA_ARGS__)
 #define IMX233_BUTTON(btn_, path_, ...) \
diff --git a/firmware/target/arm/imx233/clkctrl-imx233.c b/firmware/target/arm/imx233/clkctrl-imx233.c
index 2f507b076a..59c23c1a76 100644
--- a/firmware/target/arm/imx233/clkctrl-imx233.c
+++ b/firmware/target/arm/imx233/clkctrl-imx233.c
@@ -29,14 +29,14 @@ void imx233_clkctrl_enable(enum imx233_clock_t clk, bool enable)
     switch(clk)
     {
 #if IMX233_SUBTARGET >= 3700
-        case CLK_PIX: BF_WR(CLKCTRL_PIX, CLKGATE, gate); break;
+        case CLK_PIX: BF_WR(CLKCTRL_PIX, CLKGATE(gate)); break;
 #endif
-        case CLK_SSP: BF_WR(CLKCTRL_SSP, CLKGATE, gate); break;
-        case CLK_DRI: BF_WR(CLKCTRL_XTAL, DRI_CLK24M_GATE, gate); break;
-        case CLK_PWM: BF_WR(CLKCTRL_XTAL, PWM_CLK24M_GATE, gate); break;
-        case CLK_UART: BF_WR(CLKCTRL_XTAL, UART_CLK_GATE, gate); break;
-        case CLK_FILT: BF_WR(CLKCTRL_XTAL, FILT_CLK24M_GATE, gate); break;
-        case CLK_TIMROT: BF_WR(CLKCTRL_XTAL, TIMROT_CLK32K_GATE, gate); break;
+        case CLK_SSP: BF_WR(CLKCTRL_SSP, CLKGATE(gate)); break;
+        case CLK_DRI: BF_WR(CLKCTRL_XTAL, DRI_CLK24M_GATE(gate)); break;
+        case CLK_PWM: BF_WR(CLKCTRL_XTAL, PWM_CLK24M_GATE(gate)); break;
+        case CLK_UART: BF_WR(CLKCTRL_XTAL, UART_CLK_GATE(gate)); break;
+        case CLK_FILT: BF_WR(CLKCTRL_XTAL, FILT_CLK24M_GATE(gate)); break;
+        case CLK_TIMROT: BF_WR(CLKCTRL_XTAL, TIMROT_CLK32K_GATE(gate)); break;
         case CLK_PLL:
             /* pll is a special case */
             if(enable)
@@ -79,16 +79,16 @@ void imx233_clkctrl_set_div(enum imx233_clock_t clk, int div)
     switch(clk)
     {
 #if IMX233_SUBTARGET >= 3700
-        case CLK_PIX: BF_WR(CLKCTRL_PIX, DIV, div); break;
-        case CLK_CPU: BF_WR(CLKCTRL_CPU, DIV_CPU, div); break;
-        case CLK_EMI: BF_WR(CLKCTRL_EMI, DIV_EMI, div); break;
+        case CLK_PIX: BF_WR(CLKCTRL_PIX, DIV(div)); break;
+        case CLK_CPU: BF_WR(CLKCTRL_CPU, DIV_CPU(div)); break;
+        case CLK_EMI: BF_WR(CLKCTRL_EMI, DIV_EMI(div)); break;
 #else
-        case CLK_CPU: BF_WR(CLKCTRL_CPU, DIV, div); break;
-        case CLK_EMI: BF_WR(CLKCTRL_EMI, DIV, div); break;
+        case CLK_CPU: BF_WR(CLKCTRL_CPU, DIV(div)); break;
+        case CLK_EMI: BF_WR(CLKCTRL_EMI, DIV(div)); break;
 #endif
-        case CLK_SSP: BF_WR(CLKCTRL_SSP, DIV, div); break;
-        case CLK_HBUS: BF_WR(CLKCTRL_HBUS, DIV, div); break;
-        case CLK_XBUS: BF_WR(CLKCTRL_XBUS, DIV, div); break;
+        case CLK_SSP: BF_WR(CLKCTRL_SSP, DIV(div)); break;
+        case CLK_HBUS: BF_WR(CLKCTRL_HBUS, DIV(div)); break;
+        case CLK_XBUS: BF_WR(CLKCTRL_XBUS, DIV(div)); break;
         default: return;
     }
 }
@@ -121,7 +121,7 @@ void imx233_clkctrl_set_frac_div(enum imx233_clock_t clk, int fracdiv)
         if(fracdiv == 0) \
             BF_SET(CLKCTRL_FRAC, CLKGATE##dev); \
         else { \
-            BF_WR(CLKCTRL_FRAC, dev##FRAC, fracdiv); \
+            BF_WR(CLKCTRL_FRAC, dev##FRAC(fracdiv)); \
             BF_CLR(CLKCTRL_FRAC, CLKGATE##dev); } \
         break;
     switch(clk)
@@ -241,7 +241,7 @@ void imx233_clkctrl_set_auto_slow_div(unsigned div)
     /* the SLOW_DIV must only be set when auto-slow is disabled */
     bool old_status = imx233_clkctrl_is_auto_slow_enabled();
     imx233_clkctrl_enable_auto_slow(false);
-    BF_WR(CLKCTRL_HBUS, SLOW_DIV, div);
+    BF_WR(CLKCTRL_HBUS, SLOW_DIV(div));
     imx233_clkctrl_enable_auto_slow(old_status);
 }
 
@@ -253,7 +253,7 @@ unsigned imx233_clkctrl_get_auto_slow_div(void)
 void imx233_clkctrl_enable_auto_slow(bool enable)
 {
     /* NOTE: don't use SET/CLR because it doesn't exist on stmp3600 */
-    BF_WR(CLKCTRL_HBUS, AUTO_SLOW_MODE, enable);
+    BF_WR(CLKCTRL_HBUS, AUTO_SLOW_MODE(enable));
 }
 
 bool imx233_clkctrl_is_auto_slow_enabled(void)
@@ -387,15 +387,13 @@ void imx233_clkctrl_init(void)
 {
     /* set auto-slow monitor to all */
 #if IMX233_SUBTARGET >= 3700
-    HW_CLKCTRL_HBUS_SET = BF_OR6(CLKCTRL_HBUS,
-        APBHDMA_AS_ENABLE(1), TRAFFIC_JAM_AS_ENABLE(1), TRAFFIC_AS_ENABLE(1),
-        APBXDMA_AS_ENABLE(1), CPU_INSTR_AS_ENABLE(1), CPU_DATA_AS_ENABLE(1));
+    BF_SET(CLKCTRL_HBUS, APBHDMA_AS_ENABLE, TRAFFIC_JAM_AS_ENABLE, TRAFFIC_AS_ENABLE,
+        APBXDMA_AS_ENABLE, CPU_INSTR_AS_ENABLE, CPU_DATA_AS_ENABLE);
 #else
-    HW_CLKCTRL_HBUS = HW_CLKCTRL_HBUS | BF_OR7(CLKCTRL_HBUS, EMI_BUSY_FAST(1),
-        APBHDMA_BUSY_FAST(1), APBXDMA_BUSY_FAST(1), TRAFFIC_JAM_FAST(1),
-        TRAFFIC_FAST(1), CPU_DATA_FAST(1), CPU_INSTR_FAST(1));
+    BF_WR(CLKCTRL_HBUS, EMI_BUSY_FAST(1), APBHDMA_BUSY_FAST(1), APBXDMA_BUSY_FAST(1),
+        TRAFFIC_JAM_FAST(1), TRAFFIC_FAST(1), CPU_DATA_FAST(1), CPU_INSTR_FAST(1));
 #endif
 #if IMX233_SUBTARGET >= 3780
-    HW_CLKCTRL_HBUS_SET = BF_OR2(CLKCTRL_HBUS, DCP_AS_ENABLE(1), PXP_AS_ENABLE(1));
+    BF_SET(CLKCTRL_HBUS, DCP_AS_ENABLE, PXP_AS_ENABLE);
 #endif
 }
diff --git a/firmware/target/arm/imx233/clkctrl-imx233.h b/firmware/target/arm/imx233/clkctrl-imx233.h
index bca5494da8..f12d181c50 100644
--- a/firmware/target/arm/imx233/clkctrl-imx233.h
+++ b/firmware/target/arm/imx233/clkctrl-imx233.h
@@ -25,11 +25,11 @@
 #include "system.h"
 #include "cpu.h"
 
-#include "regs/regs-clkctrl.h"
+#include "regs/clkctrl.h"
 
 static inline void core_sleep(void)
 {
-    BF_WR(CLKCTRL_CPU, INTERRUPT_WAIT, 1);
+    BF_WR(CLKCTRL_CPU, INTERRUPT_WAIT(1));
     asm volatile (
         "mcr p15, 0, %0, c7, c0, 4 \n" /* Wait for interrupt */
         "nop\n" /* Datasheet unclear: "The lr sent to handler points here after RTI"*/
diff --git a/firmware/target/arm/imx233/creative-zen/lcd-zen.c b/firmware/target/arm/imx233/creative-zen/lcd-zen.c
index c594209db9..d4beebf736 100644
--- a/firmware/target/arm/imx233/creative-zen/lcd-zen.c
+++ b/firmware/target/arm/imx233/creative-zen/lcd-zen.c
@@ -38,6 +38,8 @@
 #include "action.h"
 #endif
 
+#include "regs/lcdif.h"
+
 /**
  * DMA
  */
@@ -321,15 +323,15 @@ void lcd_init_device(void)
     {
         unsigned xfer = MIN(IMX233_MAX_SINGLE_DMA_XFER_SIZE, size);
         lcdif_dma[i].dma.next = &lcdif_dma[(i + 1) % NR_CMDS].dma;
-        lcdif_dma[i].dma.cmd = BF_OR3(APB_CHx_CMD, CHAIN(1),
+        lcdif_dma[i].dma.cmd = BF_OR(APB_CHx_CMD, CHAIN(1),
             COMMAND(BV_APB_CHx_CMD_COMMAND__READ), XFER_COUNT(xfer));
         lcdif_dma[i].dma.buffer =  frame_p;
         size -= xfer;
         frame_p += xfer;
     }
     // first transfer: enable run, dotclk and so on
-    lcdif_dma[0].dma.cmd |= BF_OR1(APB_CHx_CMD, CMDWORDS(1));
-    lcdif_dma[0].ctrl = BF_OR4(LCDIF_CTRL, BYPASS_COUNT(1), DOTCLK_MODE(1),
+    lcdif_dma[0].dma.cmd |= BF_OR(APB_CHx_CMD, CMDWORDS(1));
+    lcdif_dma[0].ctrl = BF_OR(LCDIF_CTRL, BYPASS_COUNT(1), DOTCLK_MODE(1),
         RUN(1), WORD_LENGTH(1));
     // enable
     lcd_enable(true);
diff --git a/firmware/target/arm/imx233/debug-imx233.c b/firmware/target/arm/imx233/debug-imx233.c
index c6ffb48896..c28805bb6d 100644
--- a/firmware/target/arm/imx233/debug-imx233.c
+++ b/firmware/target/arm/imx233/debug-imx233.c
@@ -43,6 +43,9 @@
 #include "button.h"
 #include "button-imx233.h"
 
+#include "regs/usbphy.h"
+#include "regs/timrot.h"
+
 #define ACT_NONE    0
 #define ACT_CANCEL  1
 #define ACT_OK      2
diff --git a/firmware/target/arm/imx233/dma-imx233.c b/firmware/target/arm/imx233/dma-imx233.c
index 8e55e5dc5d..390add481b 100644
--- a/firmware/target/arm/imx233/dma-imx233.c
+++ b/firmware/target/arm/imx233/dma-imx233.c
@@ -26,6 +26,9 @@
 #include "lcd.h"
 #include "string.h"
 
+#include "regs/apbh.h"
+#include "regs/apbx.h"
+
 // statistics about unaligned transfers
 static int apb_nr_unaligned[32];
 
@@ -42,16 +45,16 @@ void imx233_dma_reset_channel(unsigned chan)
     if(APB_IS_APBX_CHANNEL(chan))
     {
 #if IMX233_SUBTARGET < 3780
-        BF_SETV(APBX_CTRL0, RESET_CHANNEL, bm);
+        BF_WR(APBX_CTRL0_SET, RESET_CHANNEL(bm));
         while(BF_RD(APBX_CTRL0, RESET_CHANNEL) & bm);
 #else
-        BF_SETV(APBX_CHANNEL_CTRL, RESET_CHANNEL, bm);
+        BF_WR(APBX_CHANNEL_CTRL_SET, RESET_CHANNEL(bm));
         while(BF_RD(APBX_CHANNEL_CTRL, RESET_CHANNEL) & bm);
 #endif
     }
     else
     {
-        BF_SETV(APBH_CTRL0, RESET_CHANNEL, bm);
+        BF_WR(APBH_CTRL0_SET, RESET_CHANNEL(bm));
         while(BF_RD(APBH_CTRL0, RESET_CHANNEL) & bm);
     }
 }
@@ -61,9 +64,9 @@ void imx233_dma_clkgate_channel(unsigned chan, bool enable_clock)
     if(APB_IS_APBX_CHANNEL(chan))
         return;
     if(enable_clock)
-        BF_CLRV(APBH_CTRL0, CLKGATE_CHANNEL, 1 << APB_GET_DMA_CHANNEL(chan));
+        BF_WR(APBH_CTRL0_CLR, CLKGATE_CHANNEL(1 << APB_GET_DMA_CHANNEL(chan)));
     else
-        BF_SETV(APBH_CTRL0, CLKGATE_CHANNEL, 1 << APB_GET_DMA_CHANNEL(chan));
+        BF_WR(APBH_CTRL0_SET, CLKGATE_CHANNEL(1 << APB_GET_DMA_CHANNEL(chan)));
 }
 
 void imx233_dma_freeze_channel(unsigned chan, bool freeze)
@@ -73,22 +76,22 @@ void imx233_dma_freeze_channel(unsigned chan, bool freeze)
     {
 #if IMX233_SUBTARGET < 3780
         if(freeze)
-            BF_SETV(APBX_CTRL0, FREEZE_CHANNEL, bm);
+            BF_WR(APBX_CTRL0_SET, FREEZE_CHANNEL(bm));
         else
-            BF_CLRV(APBX_CTRL0, FREEZE_CHANNEL, bm);
+            BF_WR(APBX_CTRL0_CLR, FREEZE_CHANNEL(bm));
 #else
         if(freeze)
-            BF_SETV(APBX_CHANNEL_CTRL, FREEZE_CHANNEL, bm);
+            BF_WR(APBX_CHANNEL_CTRL_SET, FREEZE_CHANNEL(bm));
         else
-            BF_CLRV(APBX_CHANNEL_CTRL, FREEZE_CHANNEL, bm);
+            BF_WR(APBX_CHANNEL_CTRL_CLR, FREEZE_CHANNEL(bm));
 #endif
     }
     else
     {
         if(freeze)
-            BF_SETV(APBH_CTRL0, FREEZE_CHANNEL, bm);
+            BF_WR(APBH_CTRL0_SET, FREEZE_CHANNEL(bm));
         else
-            BF_CLRV(APBH_CTRL0, FREEZE_CHANNEL, bm);
+            BF_WR(APBH_CTRL0_CLR, FREEZE_CHANNEL(bm));
     }
 }
 
@@ -98,16 +101,16 @@ void imx233_dma_enable_channel_interrupt(unsigned chan, bool enable)
     if(APB_IS_APBX_CHANNEL(chan))
     {
         if(enable)
-            BF_SETV(APBX_CTRL1, CH_CMDCMPLT_IRQ_EN, bm);
+            BF_WR(APBX_CTRL1_SET, CH_CMDCMPLT_IRQ_EN(bm));
         else
-            BF_CLRV(APBX_CTRL1, CH_CMDCMPLT_IRQ_EN, bm);
+            BF_WR(APBX_CTRL1_CLR, CH_CMDCMPLT_IRQ_EN(bm));
     }
     else
     {
         if(enable)
-            BF_SETV(APBH_CTRL1, CH_CMDCMPLT_IRQ_EN, bm);
+            BF_WR(APBH_CTRL1_SET, CH_CMDCMPLT_IRQ_EN(bm));
         else
-            BF_CLRV(APBH_CTRL1, CH_CMDCMPLT_IRQ_EN, bm);
+            BF_WR(APBH_CTRL1_CLR, CH_CMDCMPLT_IRQ_EN(bm));
     }
     imx233_dma_clear_channel_interrupt(chan);
 }
@@ -117,20 +120,20 @@ void imx233_dma_clear_channel_interrupt(unsigned chan)
     uint32_t bm = 1 << APB_GET_DMA_CHANNEL(chan);
     if(APB_IS_APBX_CHANNEL(chan))
     {
-        BF_CLRV(APBX_CTRL1, CH_CMDCMPLT_IRQ, bm);
+        BF_WR(APBX_CTRL1_CLR, CH_CMDCMPLT_IRQ(bm));
 #if IMX233_SUBTARGET >= 3780
-        BF_CLRV(APBX_CTRL2, CH_ERROR_IRQ, bm);
+        BF_WR(APBX_CTRL2_CLR, CH_ERROR_IRQ(bm));
 #elif IMX233_SUBTARGET >= 3700
-        BF_CLRV(APBX_CTRL1, CH_AHB_ERROR_IRQ, bm);
+        BF_WR(APBX_CTRL1_CLR, CH_AHB_ERROR_IRQ(bm));
 #endif
     }
     else
     {
-        BF_CLRV(APBH_CTRL1, CH_CMDCMPLT_IRQ, bm);
+        BF_WR(APBH_CTRL1_CLR, CH_CMDCMPLT_IRQ(bm));
 #if IMX233_SUBTARGET >= 3780
-        BF_CLRV(APBH_CTRL2, CH_ERROR_IRQ, bm);
+        BF_WR(APBH_CTRL2_CLR, CH_ERROR_IRQ(bm));
 #elif IMX233_SUBTARGET >= 3700
-        BF_CLRV(APBH_CTRL1, CH_AHB_ERROR_IRQ, bm);
+        BF_WR(APBH_CTRL1_CLR, CH_AHB_ERROR_IRQ(bm));
 #endif
     }
 }
@@ -168,7 +171,7 @@ void imx233_dma_prepare_command(unsigned chan, struct apb_dma_command_t *cmd)
 
     while(BF_RDX(cur->cmd, APB_CHx_CMD, UNUSED) != BV_APB_CHx_CMD_UNUSED__MAGIC)
     {
-        BF_WR_VX(cur->cmd, APB_CHx_CMD, UNUSED, MAGIC);
+        BF_WRX(cur->cmd, APB_CHx_CMD, UNUSED_V(MAGIC));
         int op = BF_RDX(cur->cmd, APB_CHx_CMD, COMMAND);
         int sz = BF_RDX(cur->cmd, APB_CHx_CMD, XFER_COUNT);
         /* device > host: discard */
@@ -191,7 +194,7 @@ void imx233_dma_prepare_command(unsigned chan, struct apb_dma_command_t *cmd)
     cur = cmd;
     while(BF_RDX(cur->cmd, APB_CHx, CMD_UNUSED) != 0)
     {
-        BF_WRX(cur->cmd, APB_CHx, CMD_UNUSED, 0);
+        BF_WRX(cur->cmd, APB_CHx, CMD_UNUSED(0));
         int sz = BF_RDX(cur->cmd, APB_CHx_CMD, CMDWORDS) * sizeof(uint32_t);
         /* commit descriptor and discard descriptor */
         /* chain ? */
@@ -238,10 +241,10 @@ int imx233_dma_wait_completion(unsigned chan, unsigned tmo)
     tmo += current_tick;
     int value = 0;
     if(APB_IS_APBX_CHANNEL(chan))
-        while((value = BF_RDn(APBX_CHn_SEMA, APB_GET_DMA_CHANNEL(chan), PHORE)) && !TIME_AFTER(current_tick, tmo))
+        while((value = BF_RD(APBX_CHn_SEMA(APB_GET_DMA_CHANNEL(chan)), PHORE)) && !TIME_AFTER(current_tick, tmo))
             yield();
     else
-        while((value = BF_RDn(APBH_CHn_SEMA, APB_GET_DMA_CHANNEL(chan), PHORE)) && !TIME_AFTER(current_tick, tmo))
+        while((value = BF_RD(APBH_CHn_SEMA(APB_GET_DMA_CHANNEL(chan)), PHORE)) && !TIME_AFTER(current_tick, tmo))
             yield();
 
     return value;
@@ -263,9 +266,9 @@ struct imx233_dma_info_t imx233_dma_get_info(unsigned chan, unsigned flags)
     if(flags & DMA_INFO_BAR)
         s.bar = apbx ? HW_APBX_CHn_BAR(dmac) : HW_APBH_CHn_BAR(dmac);
     if(flags & DMA_INFO_AHB_BYTES)
-        s.ahb_bytes = apbx ? BF_RDn(APBX_CHn_DEBUG2, dmac, AHB_BYTES) : BF_RDn(APBH_CHn_DEBUG2, dmac, AHB_BYTES);
+        s.ahb_bytes = apbx ? BF_RD(APBX_CHn_DEBUG2(dmac), AHB_BYTES) : BF_RD(APBH_CHn_DEBUG2(dmac),  AHB_BYTES);
     if(flags & DMA_INFO_APB_BYTES)
-        s.apb_bytes = apbx ? BF_RDn(APBX_CHn_DEBUG2, dmac, APB_BYTES) : BF_RDn(APBH_CHn_DEBUG2, dmac, APB_BYTES);
+        s.apb_bytes = apbx ? BF_RD(APBX_CHn_DEBUG2(dmac), APB_BYTES) : BF_RD(APBH_CHn_DEBUG2(dmac),  APB_BYTES);
     if(flags & DMA_INFO_FROZEN)
 #if IMX233_SUBTARGET < 3780
         s.frozen = !!((apbx ? BF_RD(APBX_CTRL0, FREEZE_CHANNEL) : BF_RD(APBH_CTRL0, FREEZE_CHANNEL)) & bm);
diff --git a/firmware/target/arm/imx233/dma-imx233.h b/firmware/target/arm/imx233/dma-imx233.h
index 8e15b4cb49..f48fbbccf3 100644
--- a/firmware/target/arm/imx233/dma-imx233.h
+++ b/firmware/target/arm/imx233/dma-imx233.h
@@ -25,9 +25,6 @@
 #include "system.h"
 #include "system-target.h"
 
-#include "regs/regs-apbh.h"
-#include "regs/regs-apbx.h"
-
 /************
  * CHANNELS *
  ************/
@@ -138,7 +135,10 @@ struct imx233_dma_info_t
 #define BP_APB_CHx_CMD_UNUSED           8
 #define BM_APB_CHx_CMD_UNUSED           (0xf << 8)
 #define BF_APB_CHx_CMD_UNUSED(v)        (((v) & 0xf) << 8)
+#define BF_APB_CHx_CMD_UNUSED_V(n)      BF_APB_CHx_CMD_UNUSED(BV_APB_CHx_CMD_UNUSED__##n)
+#define BFM_APB_CHx_CMD_UNUSED(v)       BM_APB_CHx_CMD_UNUSED
 #define BV_APB_CHx_CMD_UNUSED__MAGIC    0xa
+#define BFM_APB_CHx_CMD_UNUSED_V(v)     BM_APB_CHx_CMD_UNUSED
 
 /* A single descriptor cannot transfer more than 2^16 bytes but because of the
  * weird 0=64KiB, it's safer to restrict to 2^15 */
diff --git a/firmware/target/arm/imx233/emi-imx233.c b/firmware/target/arm/imx233/emi-imx233.c
index fcdb6d2353..d026e951f7 100644
--- a/firmware/target/arm/imx233/emi-imx233.c
+++ b/firmware/target/arm/imx233/emi-imx233.c
@@ -22,6 +22,12 @@
 #include "clkctrl-imx233.h"
 #include "string.h"
 
+#include "regs/clkctrl.h"
+#include "regs/emi.h"
+#include "regs/dram.h"
+
+#define HW_DRAM_CTLxx(xx) (*(&HW_DRAM_CTL00 + (xx)))
+
 struct emi_reg_t
 {
     int index;
@@ -108,10 +114,10 @@ static void set_frequency(unsigned long freq)
              * clk_emi@64 MHz */
             break;
     }
-    BF_WR(CLKCTRL_FRAC, CLKGATEEMI, 0);
-    BF_WR(CLKCTRL_FRAC, EMIFRAC, fracdiv);
-    BF_WR(CLKCTRL_EMI, CLKGATE, 0);
-    BF_WR(CLKCTRL_EMI, DIV_EMI, div);
+    BF_WR(CLKCTRL_FRAC, CLKGATEEMI(0));
+    BF_WR(CLKCTRL_FRAC, EMIFRAC(fracdiv));
+    BF_WR(CLKCTRL_EMI, CLKGATE(0));
+    BF_WR(CLKCTRL_EMI, DIV_EMI(div));
 }
 
 void imx233_emi_set_frequency(unsigned long freq) ICODE_ATTR;
diff --git a/firmware/target/arm/imx233/emi-imx233.h b/firmware/target/arm/imx233/emi-imx233.h
index 9f66d405f8..5983a0308e 100644
--- a/firmware/target/arm/imx233/emi-imx233.h
+++ b/firmware/target/arm/imx233/emi-imx233.h
@@ -25,11 +25,6 @@
 #include "system.h"
 #include "system-target.h"
 
-#include "regs/regs-emi.h"
-#include "regs/regs-dram.h"
-
-#define HW_DRAM_CTLxx(xx) (*(&HW_DRAM_CTL00 + (xx)))
-
 struct imx233_emi_info_t
 {
     int cas; // 1/2 cycle unit
diff --git a/firmware/target/arm/imx233/gpmi-imx233.h b/firmware/target/arm/imx233/gpmi-imx233.h
index efdda61c18..a04ad51e1e 100644
--- a/firmware/target/arm/imx233/gpmi-imx233.h
+++ b/firmware/target/arm/imx233/gpmi-imx233.h
@@ -23,6 +23,4 @@
 
 #include "system.h"
 
-#include "regs/regs-gpmi.h"
-
 #endif /* __GPMI_IMX233_H__ */
diff --git a/firmware/target/arm/imx233/i2c-imx233.c b/firmware/target/arm/imx233/i2c-imx233.c
index 782a6f6c7e..d4e20d8a21 100644
--- a/firmware/target/arm/imx233/i2c-imx233.c
+++ b/firmware/target/arm/imx233/i2c-imx233.c
@@ -26,6 +26,8 @@
 #include "pinctrl-imx233.h"
 #include "string.h"
 
+#include "regs/i2c.h"
+
 /**
  * Driver Architecture:
  * The driver has two interfaces: the good'n'old i2c_* api and a more
@@ -155,7 +157,7 @@ enum imx233_i2c_error_t imx233_i2c_add(bool start, bool transmit, void *buffer,
         i2c_stage[i2c_nr_stages].src = i2c_buffer + start_off;
         i2c_stage[i2c_nr_stages].dst = buffer;
     }
-    
+
     if(i2c_nr_stages > 0)
     {
         i2c_stage[i2c_nr_stages - 1].dma.next = &i2c_stage[i2c_nr_stages].dma;
@@ -165,11 +167,11 @@ enum imx233_i2c_error_t imx233_i2c_add(bool start, bool transmit, void *buffer,
     }
     i2c_stage[i2c_nr_stages].dma.buffer = i2c_buffer + start_off;
     i2c_stage[i2c_nr_stages].dma.next = NULL;
-    i2c_stage[i2c_nr_stages].dma.cmd = BF_OR4(APB_CHx_CMD,
+    i2c_stage[i2c_nr_stages].dma.cmd = BF_OR(APB_CHx_CMD,
         COMMAND(transmit ? BV_APB_CHx_CMD_COMMAND__READ : BV_APB_CHx_CMD_COMMAND__WRITE),
         WAIT4ENDCMD(1), CMDWORDS(1), XFER_COUNT(size));
     /* assume that any read is final (send nak on last) */
-    i2c_stage[i2c_nr_stages].ctrl0 = BF_OR6(I2C_CTRL0,
+    i2c_stage[i2c_nr_stages].ctrl0 = BF_OR(I2C_CTRL0,
         XFER_COUNT(size), DIRECTION(transmit), SEND_NAK_ON_LAST(!transmit),
         PRE_SEND_START(start), POST_SEND_STOP(stop), MASTER_MODE(1));
     i2c_nr_stages++;
@@ -194,7 +196,8 @@ enum imx233_i2c_error_t imx233_i2c_end(unsigned timeout)
         return I2C_ERROR;
     i2c_stage[i2c_nr_stages - 1].dma.cmd |= BM_APB_CHx_CMD_SEMAPHORE | BM_APB_CHx_CMD_IRQONCMPLT;
 
-    BF_CLR(I2C_CTRL1, ALL_IRQ);
+    BF_CLR(I2C_CTRL1, SLAVE_IRQ, SLAVE_STOP_IRQ, MASTER_LOSS_IRQ, EARLY_TERM_IRQ,
+        OVERSIZE_XFER_TERM_IRQ, NO_SLAVE_ACK_IRQ, DATA_ENGINE_CMPLT_IRQ, BUS_FREE_IRQ);
     imx233_dma_reset_channel(APB_I2C);
     imx233_icoll_enable_interrupt(INT_SRC_I2C_DMA, true);
     imx233_icoll_enable_interrupt(INT_SRC_I2C_ERROR, true);
diff --git a/firmware/target/arm/imx233/i2c-imx233.h b/firmware/target/arm/imx233/i2c-imx233.h
index 174fe020ce..263e93aa77 100644
--- a/firmware/target/arm/imx233/i2c-imx233.h
+++ b/firmware/target/arm/imx233/i2c-imx233.h
@@ -26,12 +26,6 @@
 #include "system-target.h"
 #include "i2c.h"
 
-#include "regs/regs-i2c.h"
-
-#define BM_I2C_CTRL1_ALL_IRQ \
-    BM_OR8(I2C_CTRL1, SLAVE_IRQ, SLAVE_STOP_IRQ, MASTER_LOSS_IRQ, EARLY_TERM_IRQ, \
-        OVERSIZE_XFER_TERM_IRQ, NO_SLAVE_ACK_IRQ, DATA_ENGINE_CMPLT_IRQ, BUS_FREE_IRQ)
-
 enum imx233_i2c_error_t
 {
     I2C_SUCCESS = 0,
diff --git a/firmware/target/arm/imx233/icoll-imx233.c b/firmware/target/arm/imx233/icoll-imx233.c
index 4e3c6fe864..3dff41394f 100644
--- a/firmware/target/arm/imx233/icoll-imx233.c
+++ b/firmware/target/arm/imx233/icoll-imx233.c
@@ -25,6 +25,20 @@
 #include "string.h"
 #include "timrot-imx233.h"
 
+#include "regs/icoll.h"
+
+/* helpers */
+#if IMX233_SUBTARGET >= 3600 && IMX233_SUBTARGET < 3780
+#define BP_ICOLL_PRIORITYn_ENABLEx(x)   (2 + 8 * (x))
+#define BM_ICOLL_PRIORITYn_ENABLEx(x)   (1 << (2 + 8 * (x)))
+#define BP_ICOLL_PRIORITYn_PRIORITYx(x) (0 + 8 * (x))
+#define BM_ICOLL_PRIORITYn_PRIORITYx(x) (3 << (0 + 8 * (x)))
+#define BF_ICOLL_PRIORITYn_PRIORITYx(x, v)  (((v) << BP_ICOLL_PRIORITYn_PRIORITYx(x)) & BM_ICOLL_PRIORITYn_PRIORITYx(x))
+#define BFM_ICOLL_PRIORITYn_PRIORITYx(x, v) BM_ICOLL_PRIORITYn_PRIORITYx(x)
+#define BP_ICOLL_PRIORITYn_SOFTIRQx(x)  (3 + 8 * (x))
+#define BM_ICOLL_PRIORITYn_SOFTIRQx(x)  (1 << (3 + 8 * (x)))
+#endif
+
 #define default_interrupt(name) \
     extern __attribute__((weak, alias("UIRQ"))) void name(void)
 
@@ -130,9 +144,9 @@ static uint32_t irq_count[INT_SRC_COUNT];
 unsigned imx233_icoll_get_priority(int src)
 {
 #if IMX233_SUBTARGET < 3780
-    return BF_RDn(ICOLL_PRIORITYn, src / 4, PRIORITYx(src % 4));
+    return BF_RD(ICOLL_PRIORITYn(src / 4), PRIORITYx(src % 4));
 #else
-    return BF_RDn(ICOLL_INTERRUPTn, src, PRIORITY);
+    return BF_RD(ICOLL_INTERRUPTn(src), PRIORITY);
 #endif
 }
 
@@ -140,9 +154,9 @@ struct imx233_icoll_irq_info_t imx233_icoll_get_irq_info(int src)
 {
     struct imx233_icoll_irq_info_t info;
 #if IMX233_SUBTARGET < 3780
-    info.enabled = BF_RDn(ICOLL_PRIORITYn, src / 4, ENABLEx(src % 4));
+    info.enabled = BF_RD(ICOLL_PRIORITYn(src / 4), ENABLEx(src % 4));
 #else
-    info.enabled = BF_RDn(ICOLL_INTERRUPTn, src, ENABLE);
+    info.enabled = BF_RD(ICOLL_INTERRUPTn(src), ENABLE);
 #endif
     info.priority = imx233_icoll_get_priority(src);
     info.freq = irq_count_old[src];
@@ -218,14 +232,14 @@ void imx233_icoll_force_irq(unsigned src, bool enable)
 {
 #if IMX233_SUBTARGET < 3780
     if(enable)
-        BF_SETn(ICOLL_PRIORITYn, src / 4, SOFTIRQx(src % 4));
+        BF_SET(ICOLL_PRIORITYn(src / 4), SOFTIRQx(src % 4));
     else
-        BF_CLRn(ICOLL_PRIORITYn, src / 4, SOFTIRQx(src % 4));
+        BF_CLR(ICOLL_PRIORITYn(src / 4), SOFTIRQx(src % 4));
 #else
     if(enable)
-        BF_SETn(ICOLL_INTERRUPTn, src, SOFTIRQ);
+        BF_SET(ICOLL_INTERRUPTn(src), SOFTIRQ);
     else
-        BF_CLRn(ICOLL_INTERRUPTn, src, SOFTIRQ);
+        BF_CLR(ICOLL_INTERRUPTn(src), SOFTIRQ);
 #endif
 }
 
@@ -233,23 +247,23 @@ void imx233_icoll_enable_interrupt(int src, bool enable)
 {
 #if IMX233_SUBTARGET < 3780
     if(enable)
-        BF_SETn(ICOLL_PRIORITYn, src / 4, ENABLEx(src % 4));
+        BF_SET(ICOLL_PRIORITYn(src / 4), ENABLEx(src % 4));
     else
-        BF_CLRn(ICOLL_PRIORITYn, src / 4, ENABLEx(src % 4));
+        BF_CLR(ICOLL_PRIORITYn(src / 4), ENABLEx(src % 4));
 #else
     if(enable)
-        BF_SETn(ICOLL_INTERRUPTn, src, ENABLE);
+        BF_SET(ICOLL_INTERRUPTn(src), ENABLE);
     else
-        BF_CLRn(ICOLL_INTERRUPTn, src, ENABLE);
+        BF_CLR(ICOLL_INTERRUPTn(src), ENABLE);
 #endif
 }
 
 void imx233_icoll_set_priority(int src, unsigned prio)
 {
 #if IMX233_SUBTARGET < 3780
-    BF_WRn(ICOLL_PRIORITYn, src / 4, PRIORITYx(src % 4), prio);
+    BF_WR(ICOLL_PRIORITYn(src / 4), PRIORITYx(src % 4, prio));
 #else
-    BF_WRn(ICOLL_INTERRUPTn, src, PRIORITY, prio);
+    BF_WR(ICOLL_INTERRUPTn(src), PRIORITY(prio));
 #endif
 }
 
diff --git a/firmware/target/arm/imx233/icoll-imx233.h b/firmware/target/arm/imx233/icoll-imx233.h
index f094930864..20b93648c9 100644
--- a/firmware/target/arm/imx233/icoll-imx233.h
+++ b/firmware/target/arm/imx233/icoll-imx233.h
@@ -24,8 +24,6 @@
 #include "config.h"
 #include "system.h"
 
-#include "regs/regs-icoll.h"
-
 #define INT_SRC_VDD5V       3
 #define INT_SRC_DAC_DMA     5
 #define INT_SRC_DAC_ERROR   6
@@ -68,16 +66,6 @@
 #define INT_SRC_COUNT       64
 #endif
 
-/* helpers */
-#if IMX233_SUBTARGET >= 3600 && IMX233_SUBTARGET < 3780
-#define BP_ICOLL_PRIORITYn_ENABLEx(x)   (2 + 8 * (x))
-#define BM_ICOLL_PRIORITYn_ENABLEx(x)   (1 << (2 + 8 * (x)))
-#define BP_ICOLL_PRIORITYn_PRIORITYx(x) (0 + 8 * (x))
-#define BM_ICOLL_PRIORITYn_PRIORITYx(x) (3 << (0 + 8 * (x)))
-#define BP_ICOLL_PRIORITYn_SOFTIRQx(x)  (3 + 8 * (x))
-#define BM_ICOLL_PRIORITYn_SOFTIRQx(x)  (1 << (3 + 8 * (x)))
-#endif
-
 /* Interrupt priorities for typical tasks */
 #define ICOLL_PRIO_NORMAL   0
 #define ICOLL_PRIO_AUDIO    1
diff --git a/firmware/target/arm/imx233/kernel-imx233.c b/firmware/target/arm/imx233/kernel-imx233.c
index 104f2e5aee..199015f564 100644
--- a/firmware/target/arm/imx233/kernel-imx233.c
+++ b/firmware/target/arm/imx233/kernel-imx233.c
@@ -23,6 +23,8 @@
 #include "clkctrl-imx233.h"
 #include "kernel-imx233.h"
 
+#include "regs/timrot.h"
+
 static void tick_timer(void)
 {
     /* Run through the list of tick tasks */
diff --git a/firmware/target/arm/imx233/lcdif-imx233.c b/firmware/target/arm/imx233/lcdif-imx233.c
index 01c7ec71e4..0470079747 100644
--- a/firmware/target/arm/imx233/lcdif-imx233.c
+++ b/firmware/target/arm/imx233/lcdif-imx233.c
@@ -22,6 +22,8 @@
 #include "pinctrl-imx233.h"
 #include "icoll-imx233.h"
 
+#include "regs/lcdif.h"
+
 #if IMX233_SUBTARGET >= 3700
 static lcdif_irq_cb_t g_cur_frame_cb = NULL;
 static lcdif_irq_cb_t g_vsync_edge_cb = NULL;
@@ -87,7 +89,7 @@ void imx233_lcdif_init(void)
 void imx233_lcdif_set_timings(unsigned data_setup, unsigned data_hold,
     unsigned cmd_setup, unsigned cmd_hold)
 {
-    HW_LCDIF_TIMING = BF_OR4(LCDIF_TIMING, DATA_SETUP(data_setup),
+    BF_WR_ALL(LCDIF_TIMING, DATA_SETUP(data_setup),
         DATA_HOLD(data_hold), CMD_SETUP(cmd_setup), CMD_HOLD(cmd_hold));
 }
 
@@ -95,11 +97,11 @@ void imx233_lcdif_set_word_length(unsigned word_length)
 {
     switch(word_length)
     {
-        case 8: BF_WR_V(LCDIF_CTRL, WORD_LENGTH, 8_BIT); break;
-        case 16: BF_WR_V(LCDIF_CTRL, WORD_LENGTH, 16_BIT); break;
+        case 8: BF_WR(LCDIF_CTRL, WORD_LENGTH_V(8_BIT)); break;
+        case 16: BF_WR(LCDIF_CTRL, WORD_LENGTH_V(16_BIT)); break;
 #if IMX233_SUBTARGET >= 3780
-        case 18: BF_WR_V(LCDIF_CTRL, WORD_LENGTH, 18_BIT); break;
-        case 24: BF_WR_V(LCDIF_CTRL, WORD_LENGTH, 24_BIT); break;
+        case 18: BF_WR(LCDIF_CTRL, WORD_LENGTH_V(18_BIT)); break;
+        case 24: BF_WR(LCDIF_CTRL, WORD_LENGTH_V(24_BIT)); break;
 #endif
         default:
             panicf("this chip cannot handle a lcd word length of %d", word_length);
@@ -115,9 +117,9 @@ void imx233_lcdif_wait_ready(void)
 void imx233_lcdif_set_data_swizzle(unsigned swizzle)
 {
 #if IMX233_SUBTARGET >= 3780
-    BF_WR(LCDIF_CTRL, INPUT_DATA_SWIZZLE, swizzle);
+    BF_WR(LCDIF_CTRL, INPUT_DATA_SWIZZLE(swizzle));
 #else
-    BF_WR(LCDIF_CTRL, DATA_SWIZZLE, swizzle);
+    BF_WR(LCDIF_CTRL, DATA_SWIZZLE(swizzle));
 #endif
 }
 
@@ -160,9 +162,9 @@ static void pio_send(unsigned len, unsigned bpp, uint8_t *buf)
     /* starting from now, all read are 32-bit */
     uint32_t *wbuf = (void *)buf;
 #if IMX233_SUBTARGET >= 3780
-    HW_LCDIF_TRANSFER_COUNT = BF_OR2(LCDIF_TRANSFER_COUNT, V_COUNT(1), H_COUNT(len));
+    BF_WR_ALL(LCDIF_TRANSFER_COUNT, V_COUNT(1), H_COUNT(len));
 #else
-    BF_WR(LCDIF_CTRL, COUNT, len);
+    BF_WR(LCDIF_CTRL, COUNT(len));
 #endif
     BF_SET(LCDIF_CTRL, RUN);
     while(count > 0)
@@ -212,7 +214,7 @@ void imx233_lcdif_dma_send(void *buf, unsigned width, unsigned height)
 #if IMX233_SUBTARGET >= 3780
     imx233_lcdif_enable_bus_master(true);
     HW_LCDIF_CUR_BUF = (uint32_t)buf;
-    HW_LCDIF_TRANSFER_COUNT = BF_OR2(LCDIF_TRANSFER_COUNT, V_COUNT(height), H_COUNT(width));
+    BF_WR_ALL(LCDIF_TRANSFER_COUNT, V_COUNT(height), H_COUNT(width));
     BF_SET(LCDIF_CTRL, DATA_SELECT);
     BF_SET(LCDIF_CTRL, RUN);
 #else
@@ -281,31 +283,31 @@ void imx233_lcdif_setup_dotclk_pins(unsigned bus_width, bool have_enable)
 
 void imx233_lcdif_set_byte_packing_format(unsigned byte_packing)
 {
-    BF_WR(LCDIF_CTRL1, BYTE_PACKING_FORMAT, byte_packing);
+    BF_WR(LCDIF_CTRL1, BYTE_PACKING_FORMAT(byte_packing));
 }
 #endif
 
 #if IMX233_SUBTARGET >= 3700 && IMX233_SUBTARGET < 3780
 void imx233_lcdif_enable_sync_signals(bool en)
 {
-    BF_WR(LCDIF_VDCTRL3, SYNC_SIGNALS_ON, en);
+    BF_WR(LCDIF_VDCTRL3, SYNC_SIGNALS_ON(en));
 }
 
 void imx233_lcdif_setup_dotclk(unsigned v_pulse_width, unsigned v_period,
     unsigned v_wait_cnt, unsigned v_active, unsigned h_pulse_width,
     unsigned h_period, unsigned h_wait_cnt, unsigned h_active, bool enable_present)
 {
-    HW_LCDIF_VDCTRL0 = BF_OR4(LCDIF_VDCTRL0, ENABLE_PRESENT(enable_present),
+    BF_WR_ALL(LCDIF_VDCTRL0, ENABLE_PRESENT(enable_present),
         VSYNC_PERIOD_UNIT(1), VSYNC_PULSE_WIDTH_UNIT(1),
          DOTCLK_V_VALID_DATA_CNT(v_active));
-    HW_LCDIF_VDCTRL1 = BF_OR2(LCDIF_VDCTRL1, VSYNC_PERIOD(v_period),
+    BF_WR_ALL(LCDIF_VDCTRL1, VSYNC_PERIOD(v_period),
         VSYNC_PULSE_WIDTH(v_pulse_width));
-    HW_LCDIF_VDCTRL2 = BF_OR3(LCDIF_VDCTRL2, HSYNC_PULSE_WIDTH(h_pulse_width),
+    BF_WR_ALL(LCDIF_VDCTRL2, HSYNC_PULSE_WIDTH(h_pulse_width),
         HSYNC_PERIOD(h_period), DOTCLK_H_VALID_DATA_CNT(h_active));
-    HW_LCDIF_VDCTRL3 = BF_OR2(LCDIF_VDCTRL3, VERTICAL_WAIT_CNT(v_wait_cnt),
+    BF_WR_ALL(LCDIF_VDCTRL3, VERTICAL_WAIT_CNT(v_wait_cnt),
         HORIZONTAL_WAIT_CNT(h_wait_cnt));
     // setup dotclk mode, always bypass count, apparently data select is needed
-    HW_LCDIF_CTRL_SET = BM_OR3(LCDIF_CTRL, DOTCLK_MODE, BYPASS_COUNT, DATA_SELECT);
+    BF_SET(LCDIF_CTRL, DOTCLK_MODE, BYPASS_COUNT, DATA_SELECT);
 }
 
 void imx233_lcdif_setup_dotclk_ex(unsigned v_pulse_width, unsigned v_back_porch,
@@ -369,10 +371,10 @@ void imx233_lcdif_set_lcd_databus_width(unsigned width)
 {
     switch(width)
     {
-        case 8: BF_WR_V(LCDIF_CTRL, LCD_DATABUS_WIDTH, 8_BIT); break;
-        case 16: BF_WR_V(LCDIF_CTRL, LCD_DATABUS_WIDTH, 16_BIT); break;
-        case 18: BF_WR_V(LCDIF_CTRL, LCD_DATABUS_WIDTH, 18_BIT); break;
-        case 24: BF_WR_V(LCDIF_CTRL, LCD_DATABUS_WIDTH, 24_BIT); break;
+        case 8: BF_WR(LCDIF_CTRL, LCD_DATABUS_WIDTH_V(8_BIT)); break;
+        case 16: BF_WR(LCDIF_CTRL, LCD_DATABUS_WIDTH_V(16_BIT)); break;
+        case 18: BF_WR(LCDIF_CTRL, LCD_DATABUS_WIDTH_V(18_BIT)); break;
+        case 24: BF_WR(LCDIF_CTRL, LCD_DATABUS_WIDTH_V(24_BIT)); break;
         default:
             panicf("this chip cannot handle a lcd bus width of %d", width);
             break;
@@ -394,4 +396,4 @@ void imx233_lcdif_enable_bus_master(bool enable)
     else
         BF_CLR(LCDIF_CTRL, LCDIF_MASTER);
 }
-#endif
\ No newline at end of file
+#endif
diff --git a/firmware/target/arm/imx233/lcdif-imx233.h b/firmware/target/arm/imx233/lcdif-imx233.h
index b45830f3d3..74e83bacde 100644
--- a/firmware/target/arm/imx233/lcdif-imx233.h
+++ b/firmware/target/arm/imx233/lcdif-imx233.h
@@ -26,8 +26,6 @@
 #include "system.h"
 #include "system-target.h"
 
-#include "regs/regs-lcdif.h"
-
 typedef void (*lcdif_irq_cb_t)(void);
 
 void imx233_lcdif_enable(bool enable);
diff --git a/firmware/target/arm/imx233/lradc-imx233.c b/firmware/target/arm/imx233/lradc-imx233.c
index db44f9100a..268a6ce46b 100644
--- a/firmware/target/arm/imx233/lradc-imx233.c
+++ b/firmware/target/arm/imx233/lradc-imx233.c
@@ -24,6 +24,20 @@
 #include "kernel-imx233.h"
 #include "stdlib.h"
 
+#include "regs/lradc.h"
+
+/** additional defines */
+#define BP_LRADC_CTRL4_LRADCxSELECT(x)  (4 * (x))
+#define BM_LRADC_CTRL4_LRADCxSELECT(x)  (0xf << (4 * (x)))
+#define BF_LRADC_CTRL4_LRADCxSELECT(x, v)   (((v) << BP_LRADC_CTRL4_LRADCxSELECT(x)) & BM_LRADC_CTRL4_LRADCxSELECT(x))
+#define BFM_LRADC_CTRL4_LRADCxSELECT(x, v)  BM_LRADC_CTRL4_LRADCxSELECT(x)
+
+#define BP_LRADC_CTRL1_LRADCx_IRQ(x)    (x)
+#define BM_LRADC_CTRL1_LRADCx_IRQ(x)    (1 << (x))
+
+#define BP_LRADC_CTRL1_LRADCx_IRQ_EN(x)    (16 + (x))
+#define BM_LRADC_CTRL1_LRADCx_IRQ_EN(x)    (1 << (16 + (x)))
+
 /* channels */
 #if IMX233_SUBTARGET >= 3700
 static struct channel_arbiter_t channel_arbiter;
@@ -69,23 +83,16 @@ void imx233_lradc_set_channel_irq_callback(int channel, lradc_irq_fn_t cb)
 void imx233_lradc_setup_source(int channel, bool div2, int src)
 {
     if(div2)
-        BF_SETV(LRADC_CTRL2, DIVIDE_BY_TWO, 1 << channel);
+        BF_WR(LRADC_CTRL2_SET, DIVIDE_BY_TWO(1 << channel));
     else
-        BF_CLRV(LRADC_CTRL2, DIVIDE_BY_TWO, 1 << channel);
+        BF_WR(LRADC_CTRL2_CLR, DIVIDE_BY_TWO(1 << channel));
 #if IMX233_SUBTARGET >= 3700
-    HW_LRADC_CTRL4_CLR = BM_LRADC_CTRL4_LRADCxSELECT(channel);
-    HW_LRADC_CTRL4_SET = src << BP_LRADC_CTRL4_LRADCxSELECT(channel);
+    BF_CS(LRADC_CTRL4, LRADCxSELECT(channel, src));
 #else
     if(channel == 6)
-    {
-        BF_CLR(LRADC_CTRL2, LRADC6SELECT);
-        BF_SETV(LRADC_CTRL2, LRADC6SELECT, src);
-    }
+        BF_CS(LRADC_CTRL2, LRADC6SELECT(src));
     else if(channel == 7)
-    {
-        BF_CLR(LRADC_CTRL2, LRADC7SELECT);
-        BF_SETV(LRADC_CTRL2, LRADC7SELECT, src);
-    }
+        BF_CS(LRADC_CTRL2, LRADC7SELECT(src));
     else if(channel != src)
         panicf("cannot configure channel %d for source %d", channel, src);
 #endif
@@ -93,14 +100,13 @@ void imx233_lradc_setup_source(int channel, bool div2, int src)
 
 void imx233_lradc_setup_sampling(int channel, bool acc, int nr_samples)
 {
-    HW_LRADC_CHn_CLR(channel) = BM_OR2(LRADC_CHn, NUM_SAMPLES, ACCUMULATE);
-    HW_LRADC_CHn_SET(channel) = BF_OR2(LRADC_CHn, NUM_SAMPLES(nr_samples), ACCUMULATE(acc));
+    BF_CS(LRADC_CHn(channel), NUM_SAMPLES(nr_samples), ACCUMULATE(acc));
 }
 
 void imx233_lradc_setup_delay(int dchan, int trigger_lradc, int trigger_delays,
     int loop_count, int delay)
 {
-    HW_LRADC_DELAYn(dchan) = BF_OR4(LRADC_DELAYn, TRIGGER_LRADCS(trigger_lradc),
+    BF_WR_ALL(LRADC_DELAYn(dchan), TRIGGER_LRADCS(trigger_lradc),
         TRIGGER_DELAYS(trigger_delays), LOOP_COUNT(loop_count), DELAY(delay));
 }
 
@@ -126,12 +132,12 @@ void imx233_lradc_enable_channel_irq(int channel, bool enable)
 void imx233_lradc_kick_channel(int channel)
 {
     imx233_lradc_clear_channel_irq(channel);
-    BF_SETV(LRADC_CTRL0, SCHEDULE, 1 << channel);
+    BF_WR(LRADC_CTRL0_SET, SCHEDULE(1 << channel));
 }
 
 void imx233_lradc_kick_delay(int dchan)
 {
-    BF_SETn(LRADC_DELAYn, dchan, KICK);
+    BF_SET(LRADC_DELAYn(dchan), KICK);
 }
 
 void imx233_lradc_wait_channel(int channel)
@@ -143,12 +149,12 @@ void imx233_lradc_wait_channel(int channel)
 
 int imx233_lradc_read_channel(int channel)
 {
-    return BF_RDn(LRADC_CHn, channel, VALUE);
+    return BF_RD(LRADC_CHn(channel), VALUE);
 }
 
 void imx233_lradc_clear_channel(int channel)
 {
-    BF_CLRn(LRADC_CHn, channel, VALUE);
+    BF_CLR(LRADC_CHn(channel), VALUE);
 }
 
 #if IMX233_SUBTARGET >= 3700
@@ -280,14 +286,13 @@ int imx233_lradc_sense_ext_temperature(int chan, int sensor)
     }
     /* disable sensor current */
     imx233_lradc_set_temp_isrc(sensor, BV_LRADC_CTRL2_TEMP_ISRC0__ZERO);
-    
+
     return (abs(b - a) / EXT_TEMP_ACC_COUNT) * 1104 / 1000;
 }
 
 void imx233_lradc_setup_battery_conversion(bool automatic, unsigned long scale_factor)
 {
-    BF_CLR(LRADC_CONVERSION, SCALE_FACTOR);
-    BF_SETV(LRADC_CONVERSION, SCALE_FACTOR, scale_factor);
+    BF_CS(LRADC_CONVERSION, SCALE_FACTOR(scale_factor));
     if(automatic)
         BF_SET(LRADC_CONVERSION, AUTOMATIC);
     else
@@ -302,9 +307,7 @@ int imx233_lradc_read_battery_voltage(void)
 void imx233_lradc_setup_touch(bool xminus_enable, bool yminus_enable,
     bool xplus_enable, bool yplus_enable, bool touch_detect)
 {
-    HW_LRADC_CTRL0_CLR = BM_OR5(LRADC_CTRL0, XMINUS_ENABLE, YMINUS_ENABLE,
-        XPLUS_ENABLE, YPLUS_ENABLE, TOUCH_DETECT_ENABLE);
-    HW_LRADC_CTRL0_SET = BF_OR5(LRADC_CTRL0, XMINUS_ENABLE(xminus_enable),
+    BF_CS(LRADC_CTRL0, XMINUS_ENABLE(xminus_enable),
         YMINUS_ENABLE(yminus_enable), XPLUS_ENABLE(xplus_enable),
         YPLUS_ENABLE(yplus_enable), TOUCH_DETECT_ENABLE(touch_detect));
 }
@@ -351,8 +354,7 @@ void imx233_lradc_init(void)
     BF_SET(LRADC_CTRL2, TEMPSENSE_PWD);
 #endif
     // set frequency
-    BF_CLR(LRADC_CTRL3, CYCLE_TIME);
-    BF_SETV(LRADC_CTRL3, CYCLE_TIME_V, 6MHZ);
+    BF_CS(LRADC_CTRL3, CYCLE_TIME_V(6MHZ));
     // setup battery
     battery_chan = 7;
     imx233_lradc_reserve_channel(battery_chan);
diff --git a/firmware/target/arm/imx233/lradc-imx233.h b/firmware/target/arm/imx233/lradc-imx233.h
index 0ef8858e02..fad0eb9121 100644
--- a/firmware/target/arm/imx233/lradc-imx233.h
+++ b/firmware/target/arm/imx233/lradc-imx233.h
@@ -28,18 +28,6 @@
 #include "system.h"
 #include "system-target.h"
 
-#include "regs/regs-lradc.h"
-
-/** additional defines */
-#define BP_LRADC_CTRL4_LRADCxSELECT(x)  (4 * (x))
-#define BM_LRADC_CTRL4_LRADCxSELECT(x)  (0xf << (4 * (x)))
-
-#define BP_LRADC_CTRL1_LRADCx_IRQ(x)    (x)
-#define BM_LRADC_CTRL1_LRADCx_IRQ(x)    (1 << (x))
-
-#define BP_LRADC_CTRL1_LRADCx_IRQ_EN(x)    (16 + (x))
-#define BM_LRADC_CTRL1_LRADCx_IRQ_EN(x)    (1 << (16 + (x)))
-
 #define LRADC_NUM_CHANNELS  8
 #define LRADC_NUM_DELAYS    4
 #define LRADC_NUM_SOURCES   16
diff --git a/firmware/target/arm/imx233/ocotp-imx233.h b/firmware/target/arm/imx233/ocotp-imx233.h
index 0827ea0d19..ddd7fec228 100644
--- a/firmware/target/arm/imx233/ocotp-imx233.h
+++ b/firmware/target/arm/imx233/ocotp-imx233.h
@@ -28,7 +28,7 @@
  * where STMP3600 has laser fuses. */
 
 #if IMX233_SUBTARGET >= 3700
-#include "regs/regs-ocotp.h"
+#include "regs/ocotp.h"
 
 #define IMX233_NUM_OCOTP_CUST   4
 #define IMX233_NUM_OCOTP_CRYPTO 4
@@ -57,15 +57,15 @@ static inline uint32_t imx233_ocotp_read(volatile uint32_t *reg)
     return val;
 }
 #else
-#include "regs/regs-rtc.h"
+#include "regs/rtc.h"
 
 #define IMX233_NUM_OCOTP_LASERFUSE  12
 
 static inline uint32_t imx233_ocotp_read(volatile uint32_t *reg)
 {
-    BF_WR_V(RTC_UNLOCK, KEY, VAL);
+    BF_WR(RTC_UNLOCK, KEY_V(VAL));
     uint32_t val = *reg;
-    BF_WR(RTC_UNLOCK, KEY, 0);
+    BF_WR(RTC_UNLOCK, KEY(0));
     return val;
 }
 #endif
diff --git a/firmware/target/arm/imx233/pcm-imx233.c b/firmware/target/arm/imx233/pcm-imx233.c
index 139717df5e..de0e1aabf5 100644
--- a/firmware/target/arm/imx233/pcm-imx233.c
+++ b/firmware/target/arm/imx233/pcm-imx233.c
@@ -71,7 +71,7 @@ static void play(void)
 
     dac_dma.dma.next = NULL;
     dac_dma.dma.buffer = (void *)dac_buf;
-    dac_dma.dma.cmd = BF_OR4(APB_CHx_CMD, COMMAND_V(READ),
+    dac_dma.dma.cmd = BF_OR(APB_CHx_CMD, COMMAND_V(READ),
         IRQONCMPLT(1), SEMAPHORE(1), XFER_COUNT(xfer));
     /* dma subsystem will make sure cached stuff is written to memory */
     dac_state = DAC_PLAYING;
@@ -252,7 +252,7 @@ static void rec(void)
 
     adc_dma.dma.next = NULL;
     adc_dma.dma.buffer = (void *)adc_buf;
-    adc_dma.dma.cmd = BF_OR4(APB_CHx_CMD, COMMAND_V(WRITE),
+    adc_dma.dma.cmd = BF_OR(APB_CHx_CMD, COMMAND_V(WRITE),
         IRQONCMPLT(1), SEMAPHORE(1), XFER_COUNT(xfer));
     /* dma subsystem will make sure cached stuff is written to memory */
     adc_state = ADC_RECORDING;
diff --git a/firmware/target/arm/imx233/pinctrl-imx233.h b/firmware/target/arm/imx233/pinctrl-imx233.h
index 3fcf042071..5ef812b97f 100644
--- a/firmware/target/arm/imx233/pinctrl-imx233.h
+++ b/firmware/target/arm/imx233/pinctrl-imx233.h
@@ -25,7 +25,7 @@
 
 #include "config.h"
 #include "system.h"
-#include "regs/regs-pinctrl.h"
+#include "regs/pinctrl.h"
 
 // set to debug pinctrl use
 #define IMX233_PINCTRL_DEBUG
@@ -59,7 +59,7 @@ typedef void (*pin_irq_cb_t)(int bank, int pin, intptr_t user);
 
 static inline void imx233_pinctrl_init(void)
 {
-    HW_PINCTRL_CTRL_CLR = BM_OR2(PINCTRL_CTRL, CLKGATE, SFTRST);
+    BF_CLR(PINCTRL_CTRL, CLKGATE, SFTRST);
 }
 
 #if IMX233_SUBTARGET >= 3700
diff --git a/firmware/target/arm/imx233/power-imx233.c b/firmware/target/arm/imx233/power-imx233.c
index c374644c0b..600f65eea6 100644
--- a/firmware/target/arm/imx233/power-imx233.c
+++ b/firmware/target/arm/imx233/power-imx233.c
@@ -29,6 +29,57 @@
 #include "pinctrl-imx233.h"
 #include "fmradio_i2c.h"
 
+#include "regs/power.h"
+
+#define BV_POWER_5VCTRL_CHARGE_4P2_ILIMIT__10mA    (1 << 0)
+#define BV_POWER_5VCTRL_CHARGE_4P2_ILIMIT__20mA    (1 << 1)
+#define BV_POWER_5VCTRL_CHARGE_4P2_ILIMIT__50mA    (1 << 2)
+#define BV_POWER_5VCTRL_CHARGE_4P2_ILIMIT__100mA   (1 << 3)
+#define BV_POWER_5VCTRL_CHARGE_4P2_ILIMIT__200mA   (1 << 4)
+#define BV_POWER_5VCTRL_CHARGE_4P2_ILIMIT__400mA   (1 << 5)
+
+
+#define BV_POWER_CHARGE_BATTCHRG_I__10mA   (1 << 0)
+#define BV_POWER_CHARGE_BATTCHRG_I__20mA   (1 << 1)
+#define BV_POWER_CHARGE_BATTCHRG_I__50mA   (1 << 2)
+#define BV_POWER_CHARGE_BATTCHRG_I__100mA  (1 << 3)
+#define BV_POWER_CHARGE_BATTCHRG_I__200mA  (1 << 4)
+#define BV_POWER_CHARGE_BATTCHRG_I__400mA  (1 << 5)
+
+#define BV_POWER_CHARGE_STOP_ILIMIT__10mA  (1 << 0)
+#define BV_POWER_CHARGE_STOP_ILIMIT__20mA  (1 << 1)
+#define BV_POWER_CHARGE_STOP_ILIMIT__50mA  (1 << 2)
+#define BV_POWER_CHARGE_STOP_ILIMIT__100mA (1 << 3)
+
+#if IMX233_SUBTARGET >= 3700
+#define HW_POWER_VDDDCTRL__TRG_STEP 25 /* mV */
+#define HW_POWER_VDDDCTRL__TRG_MIN  800 /* mV */
+
+#define HW_POWER_VDDACTRL__TRG_STEP 25 /* mV */
+#define HW_POWER_VDDACTRL__TRG_MIN  1500 /* mV */
+
+#define HW_POWER_VDDIOCTRL__TRG_STEP    25 /* mV */
+#define HW_POWER_VDDIOCTRL__TRG_MIN 2800 /* mV */
+
+#define HW_POWER_VDDMEMCTRL__TRG_STEP    50 /* mV */
+#define HW_POWER_VDDMEMCTRL__TRG_MIN 1700 /* mV */
+#else
+/* don't use the full available range because of the weird encodings for
+ * extreme values which are useless anyway */
+#define HW_POWER_VDDDCTRL__TRG_STEP 32 /* mV */
+#define HW_POWER_VDDDCTRL__TRG_MIN  1280 /* mV */
+#define HW_POWER_VDDDCTRL__TRG_OFF  8 /* below 8, the register value doesn't encode linearly */
+#endif
+
+#define BV_POWER_MISC_FREQSEL__RES         0
+#define BV_POWER_MISC_FREQSEL__20MHz       1
+#define BV_POWER_MISC_FREQSEL__24MHz       2
+#define BV_POWER_MISC_FREQSEL__19p2MHz     3
+#define BV_POWER_MISC_FREQSEL__14p4MHz     4
+#define BV_POWER_MISC_FREQSEL__18MHz       5
+#define BV_POWER_MISC_FREQSEL__21p6MHz     6
+#define BV_POWER_MISC_FREQSEL__17p28MHz    7
+
 struct current_step_bit_t
 {
     unsigned current;
@@ -103,7 +154,7 @@ void INT_VDD5V(void)
         else
             usb_remove_int();
         /* reverse polarity */
-        BF_TOG(POWER_CTRL, POLARITY_VBUSVALID);
+        BF_WR(POWER_CTRL_TOG, POLARITY_VBUSVALID(1));
         /* clear int */
         BF_CLR(POWER_CTRL, VBUSVALID_IRQ);
     }
@@ -115,7 +166,7 @@ void INT_VDD5V(void)
         else
             usb_remove_int();
         /* reverse polarity */
-        BF_TOG(POWER_CTRL, POLARITY_VDD5V_GT_VDDIO);
+        BF_WR(POWER_CTRL_TOG, POLARITY_VDD5V_GT_VDDIO(1));
         /* clear int */
         BF_CLR(POWER_CTRL, VDD5V_GT_VDDIO_IRQ);
     }
@@ -128,8 +179,7 @@ void imx233_power_init(void)
     BF_CLR(POWER_MINPWR, HALF_FETS);
 #endif
     /* setup vbusvalid parameters: set threshold to 4v and power up comparators */
-    BF_CLR(POWER_5VCTRL, VBUSVALID_TRSH);
-    BF_SETV(POWER_5VCTRL, VBUSVALID_TRSH, 1);
+    BF_CS(POWER_5VCTRL, VBUSVALID_TRSH(1));
 #if IMX233_SUBTARGET >= 3780
     BF_SET(POWER_5VCTRL, PWRUP_VBUS_CMPS);
 #else
@@ -190,7 +240,7 @@ void power_off(void)
     imx233_pinctrl_set_gpio(0, 9, true);
 #endif
     /* power down */
-    HW_POWER_RESET = BM_OR2(POWER_RESET, UNLOCK, PWD);
+    HW_POWER_RESET = BM_OR(POWER_RESET, UNLOCK, PWD); // FIXME bug
     while(1);
 }
 
@@ -218,9 +268,9 @@ void imx233_power_set_charge_current(unsigned current)
         {
             current -= g_charger_current_bits[i].current;
 #if IMX233_SUBTARGET >= 3700
-            BF_SETV(POWER_CHARGE, BATTCHRG_I, g_charger_current_bits[i].bit);
+            BF_WR(POWER_CHARGE_SET, BATTCHRG_I(g_charger_current_bits[i].bit));
 #else
-            BF_SETV(POWER_BATTCHRG, BATTCHRG_I, g_charger_current_bits[i].bit);
+            BF_WR(POWER_BATTCHRG_SET, BATTCHRG_I(g_charger_current_bits[i].bit));
 #endif
         }
 }
@@ -243,9 +293,9 @@ void imx233_power_set_stop_current(unsigned current)
         {
             current -= g_charger_stop_current_bits[i].current;
 #if IMX233_SUBTARGET >= 3700
-            BF_SETV(POWER_CHARGE, STOP_ILIMIT, g_charger_stop_current_bits[i].bit);
+            BF_WR(POWER_CHARGE_SET, STOP_ILIMIT(g_charger_stop_current_bits[i].bit));
 #else
-            BF_SETV(POWER_BATTCHRG, STOP_ILIMIT, g_charger_stop_current_bits[i].bit);
+            BF_WR(POWER_BATTCHRG_SET, STOP_ILIMIT(g_charger_stop_current_bits[i].bit));
 #endif
         }
     }
@@ -363,7 +413,7 @@ static void update_dcfuncv(void)
     imx233_power_get_regulator(REGULATOR_VDDA, &vdda, NULL);
     imx233_power_get_regulator(REGULATOR_VDDIO, &vddio, NULL);
     // assume Li-Ion, to divide by 6.25, do *100 and /625
-    HW_POWER_DCFUNCV = BF_OR2(POWER_DCFUNCV, VDDIO(((vddio - vdda) * 100) / 625),
+    BF_WR_ALL(POWER_DCFUNCV, VDDIO(((vddio - vdda) * 100) / 625),
         VDDD(((vdda - vddd) * 100) / 625));
 }
 #endif
@@ -447,13 +497,13 @@ int imx233_power_sense_die_temperature(int *min, int *max)
         -50, -40, -30, -20, -10, 0, 15, 25, 35, 45, 55, 70, 85, 95, 105, 115, 130
     };
     /* power up temperature sensor */
-    BF_CLRV(POWER_SPEEDTEMP, TEMP_CTRL, 1 << 3);
+    BF_WR(POWER_SPEEDTEMP_CLR, TEMP_CTRL(1 << 3));
     /* read temp */
     int sense = BF_RD(POWER_SPEEDTEMP, TEMP_STS);
     *min = die_temp[sense];
     *max = die_temp[sense + 1];
     /* power down temperature sensor */
-    BF_SETV(POWER_SPEEDTEMP, TEMP_CTRL, 1 << 3);
+    BF_WR(POWER_SPEEDTEMP_SET, TEMP_CTRL(1 << 3));
     return 0;
 }
 #endif
diff --git a/firmware/target/arm/imx233/power-imx233.h b/firmware/target/arm/imx233/power-imx233.h
index 9888bebe1f..867175c41f 100644
--- a/firmware/target/arm/imx233/power-imx233.h
+++ b/firmware/target/arm/imx233/power-imx233.h
@@ -25,57 +25,8 @@
 #include "system-target.h"
 #include "cpu.h"
 
-#include "regs/regs-power.h"
-
-#define BV_POWER_5VCTRL_CHARGE_4P2_ILIMIT__10mA    (1 << 0)
-#define BV_POWER_5VCTRL_CHARGE_4P2_ILIMIT__20mA    (1 << 1)
-#define BV_POWER_5VCTRL_CHARGE_4P2_ILIMIT__50mA    (1 << 2)
-#define BV_POWER_5VCTRL_CHARGE_4P2_ILIMIT__100mA   (1 << 3)
-#define BV_POWER_5VCTRL_CHARGE_4P2_ILIMIT__200mA   (1 << 4)
-#define BV_POWER_5VCTRL_CHARGE_4P2_ILIMIT__400mA   (1 << 5)
-
-
-#define BV_POWER_CHARGE_BATTCHRG_I__10mA   (1 << 0)
-#define BV_POWER_CHARGE_BATTCHRG_I__20mA   (1 << 1)
-#define BV_POWER_CHARGE_BATTCHRG_I__50mA   (1 << 2)
-#define BV_POWER_CHARGE_BATTCHRG_I__100mA  (1 << 3)
-#define BV_POWER_CHARGE_BATTCHRG_I__200mA  (1 << 4)
-#define BV_POWER_CHARGE_BATTCHRG_I__400mA  (1 << 5)
-
-#define BV_POWER_CHARGE_STOP_ILIMIT__10mA  (1 << 0)
-#define BV_POWER_CHARGE_STOP_ILIMIT__20mA  (1 << 1)
-#define BV_POWER_CHARGE_STOP_ILIMIT__50mA  (1 << 2)
-#define BV_POWER_CHARGE_STOP_ILIMIT__100mA (1 << 3)
-
-#if IMX233_SUBTARGET >= 3700
-#define HW_POWER_VDDDCTRL__TRG_STEP 25 /* mV */
-#define HW_POWER_VDDDCTRL__TRG_MIN  800 /* mV */
-
-#define HW_POWER_VDDACTRL__TRG_STEP 25 /* mV */
-#define HW_POWER_VDDACTRL__TRG_MIN  1500 /* mV */
-
-#define HW_POWER_VDDIOCTRL__TRG_STEP    25 /* mV */
-#define HW_POWER_VDDIOCTRL__TRG_MIN 2800 /* mV */
-
-#define HW_POWER_VDDMEMCTRL__TRG_STEP    50 /* mV */
-#define HW_POWER_VDDMEMCTRL__TRG_MIN 1700 /* mV */
-#else
-/* don't use the full available range because of the weird encodings for
- * extreme values which are useless anyway */
-#define HW_POWER_VDDDCTRL__TRG_STEP 32 /* mV */
-#define HW_POWER_VDDDCTRL__TRG_MIN  1280 /* mV */
-#define HW_POWER_VDDDCTRL__TRG_OFF  8 /* below 8, the register value doesn't encode linearly */
-#endif
-
-#define BV_POWER_MISC_FREQSEL__RES         0
-#define BV_POWER_MISC_FREQSEL__20MHz       1
-#define BV_POWER_MISC_FREQSEL__24MHz       2
-#define BV_POWER_MISC_FREQSEL__19p2MHz     3
-#define BV_POWER_MISC_FREQSEL__14p4MHz     4
-#define BV_POWER_MISC_FREQSEL__18MHz       5
-#define BV_POWER_MISC_FREQSEL__21p6MHz     6
-#define BV_POWER_MISC_FREQSEL__17p28MHz    7
-
+#include "regs/power.h"
+#include "regs/digctl.h"
 
 void imx233_power_init(void);
 
@@ -114,8 +65,8 @@ void imx233_power_set_regulator_linreg(enum imx233_regulator_t reg,
 static inline void imx233_power_set_dcdc_freq(bool pll, unsigned freq)
 {
     if(pll)
-        BF_WR(POWER_MISC, FREQSEL, freq);
-    BF_WR(POWER_MISC, SEL_PLLCLK, pll);
+        BF_WR(POWER_MISC, FREQSEL(freq));
+    BF_WR(POWER_MISC, SEL_PLLCLK(pll));
 }
 #endif
 
diff --git a/firmware/target/arm/imx233/powermgmt-imx233.c b/firmware/target/arm/imx233/powermgmt-imx233.c
index 01d0e3eae1..5db03d4127 100644
--- a/firmware/target/arm/imx233/powermgmt-imx233.c
+++ b/firmware/target/arm/imx233/powermgmt-imx233.c
@@ -28,6 +28,8 @@
 #include "logf.h"
 #include "powermgmt-imx233.h"
 
+#include "regs/power.h"
+
 #if !defined(IMX233_CHARGE_CURRENT) || !defined(IMX233_STOP_CURRENT) \
     || !defined(IMX233_CHARGING_TIMEOUT) || !defined(IMX233_TOPOFF_TIMEOUT)
 #error You must define IMX233_CHARGE_CURRENT, IMX233_STOP_CURRENT, \
@@ -52,17 +54,16 @@ void imx233_powermgmt_init(void)
     imx233_power_set_stop_current(IMX233_STOP_CURRENT);
 #if IMX233_SUBTARGET >= 3700
     /* assume that adc_init was called and battery monitoring via LRADC setup */
-    BF_WR(POWER_BATTMONITOR, EN_BATADJ, 1);
+    BF_WR(POWER_BATTMONITOR, EN_BATADJ(1));
     /* setup linear regulator offsets to 25 mV below to prevent contention between
      * linear regulators and DCDC */
-    BF_WR(POWER_VDDDCTRL, LINREG_OFFSET, 2);
-    BF_WR(POWER_VDDACTRL, LINREG_OFFSET, 2);
-    BF_WR(POWER_VDDIOCTRL, LINREG_OFFSET, 2);
+    BF_WR(POWER_VDDDCTRL, LINREG_OFFSET(2));
+    BF_WR(POWER_VDDACTRL, LINREG_OFFSET(2));
+    BF_WR(POWER_VDDIOCTRL, LINREG_OFFSET(2));
     /* enable a few bits controlling the DC-DC as recommended by Freescale */
     BF_SET(POWER_LOOPCTRL, TOGGLE_DIF);
     BF_SET(POWER_LOOPCTRL, EN_CM_HYST);
-    BF_CLR(POWER_LOOPCTRL, EN_RCSCALE);
-    BF_SETV(POWER_LOOPCTRL, EN_RCSCALE, 1);
+    BF_CS(POWER_LOOPCTRL, EN_RCSCALE(1));
 #else
     BF_SET(POWER_5VCTRL, LINREG_OFFSET);
 #endif
@@ -86,9 +87,9 @@ void charging_algorithm_step(void)
         /* 5V has been lost: disable 4p2 power rail */
         BF_SET(POWER_CHARGE, PWD_BATTCHRG);
 #if IMX233_SUBTARGET >= 3780
-        BF_WR(POWER_DCDC4P2, ENABLE_DCDC, 0);
-        BF_WR(POWER_DCDC4P2, ENABLE_4P2, 0);
-        BF_WR(POWER_5VCTRL, CHARGE_4P2_ILIMIT, 1);
+        BF_WR(POWER_DCDC4P2, ENABLE_DCDC(0));
+        BF_WR(POWER_DCDC4P2, ENABLE_4P2(0));
+        BF_WR(POWER_5VCTRL, CHARGE_4P2_ILIMIT(1));
         BF_SET(POWER_5VCTRL, PWD_CHARGE_4P2);
 #endif
         charge_state = DISCHARGING;
@@ -105,10 +106,10 @@ void charging_algorithm_step(void)
          * we must *NOT* disable it or this will shutdown the device. This procedure
          * is safe: it will never disable the DCDC and will not reduce the charge
          * limit on the 4P2 rail. */
-        BF_WR(POWER_DCDC4P2, ENABLE_4P2, 1);
+        BF_WR(POWER_DCDC4P2, ENABLE_4P2(1));
         BF_SET(POWER_CHARGE, ENABLE_LOAD);
         BF_CLR(POWER_5VCTRL, PWD_CHARGE_4P2);// FIXME: manual error ?
-        BF_WR(POWER_DCDC4P2, ENABLE_DCDC, 1);
+        BF_WR(POWER_DCDC4P2, ENABLE_DCDC(1));
 #endif
         timeout_4p2_ilimit_increase = current_tick + HZ / 100;
         charge_state = TRICKLE;
@@ -132,8 +133,8 @@ void charging_algorithm_step(void)
             logf("pwrmgmt: trickle -> charging");
 #if IMX233_SUBTARGET >= 3780
             /* adjust arbitration between 4.2 and battery */
-            BF_WR(POWER_DCDC4P2, CMPTRIP, 0); /* 85% */
-            BF_WR(POWER_DCDC4P2, DROPOUT_CTRL, 0xe); /* select greater, 200 mV drop */
+            BF_WR(POWER_DCDC4P2, CMPTRIP(0)); /* 85% */
+            BF_WR(POWER_DCDC4P2, DROPOUT_CTRL(0xe)); /* select greater, 200 mV drop */
 #endif
             /* switch to DCDC */
             BF_CLR(POWER_5VCTRL, DCDC_XFER);
diff --git a/firmware/target/arm/imx233/pwm-imx233.c b/firmware/target/arm/imx233/pwm-imx233.c
index fb14fcb91f..5e1cc1daa5 100644
--- a/firmware/target/arm/imx233/pwm-imx233.c
+++ b/firmware/target/arm/imx233/pwm-imx233.c
@@ -24,6 +24,14 @@
 #include "clkctrl-imx233.h"
 #include "pinctrl-imx233.h"
 
+#include "regs/pwm.h"
+
+/* fake field for simpler programming */
+#define BP_PWM_CTRL_PWMx_ENABLE(x)  (x)
+#define BM_PWM_CTRL_PWMx_ENABLE(x)  (1 << (x))
+#define BF_PWM_CTRL_PWMx_ENABLE(x, v)   (((v) << BP_PWM_CTRL_PWMx_ENABLE(x)) & BM_PWM_CTRL_PWMx_ENABLE(x))
+#define BFM_PWM_CTRL_PWMx_ENABLE(x, v)  BM_PWM_CTRL_PWMx_ENABLE(x)
+
 /* list of divisors + register value by increasing order of divisors */
 static int pwm_cdiv_table[] =
 {
@@ -62,8 +70,8 @@ void imx233_pwm_setup(int channel, int period, int cdiv, int active,
     imx233_pinctrl_setup_vpin(VPIN_PWM(channel), "pwm", PINCTRL_DRIVE_4mA, false);
     /* watch the order ! active THEN period
      * NOTE: the register value is period-1 */
-    HW_PWM_ACTIVEn(channel) = BF_OR2(PWM_ACTIVEn, ACTIVE(active), INACTIVE(inactive));
-    HW_PWM_PERIODn(channel) = BF_OR4(PWM_PERIODn, PERIOD(period - 1),
+    BF_WR_ALL(PWM_ACTIVEn(channel), ACTIVE(active), INACTIVE(inactive));
+    BF_WR_ALL(PWM_PERIODn(channel), PERIOD(period - 1),
         ACTIVE_STATE(active_state), INACTIVE_STATE(inactive_state), CDIV(cdiv));
     /* restore */
     imx233_pwm_enable(channel, enable);
@@ -120,11 +128,11 @@ struct imx233_pwm_info_t imx233_pwm_get_info(int channel)
     struct imx233_pwm_info_t info;
     memset(&info, 0, sizeof(info));
     info.enabled = imx233_pwm_is_enabled(channel);
-    info.cdiv = pwm_cdiv_table[BF_RDn(PWM_PERIODn, channel, CDIV)];
-    info.period = BF_RDn(PWM_PERIODn, channel, PERIOD) + 1;
-    info.active = BF_RDn(PWM_ACTIVEn, channel, ACTIVE);
-    info.inactive = BF_RDn(PWM_ACTIVEn, channel, INACTIVE);
-    info.active_state = active_state[BF_RDn(PWM_PERIODn, channel, ACTIVE_STATE)];
-    info.inactive_state = inactive_state[BF_RDn(PWM_PERIODn, channel, INACTIVE_STATE)];
+    info.cdiv = pwm_cdiv_table[BF_RD(PWM_PERIODn(channel), CDIV)];
+    info.period = BF_RD(PWM_PERIODn(channel), PERIOD) + 1;
+    info.active = BF_RD(PWM_ACTIVEn(channel), ACTIVE);
+    info.inactive = BF_RD(PWM_ACTIVEn(channel), INACTIVE);
+    info.active_state = active_state[BF_RD(PWM_PERIODn(channel), ACTIVE_STATE)];
+    info.inactive_state = inactive_state[BF_RD(PWM_PERIODn(channel), INACTIVE_STATE)];
     return info;
 }
diff --git a/firmware/target/arm/imx233/pwm-imx233.h b/firmware/target/arm/imx233/pwm-imx233.h
index 55c454b7cd..008cc0f84d 100644
--- a/firmware/target/arm/imx233/pwm-imx233.h
+++ b/firmware/target/arm/imx233/pwm-imx233.h
@@ -23,12 +23,6 @@
 
 #include "system.h"
 
-#include "regs/regs-pwm.h"
-
-/* fake field for simpler programming */
-#define BP_PWM_CTRL_PWMx_ENABLE(x)  (x)
-#define BM_PWM_CTRL_PWMx_ENABLE(x)  (1 << (x))
-
 #define IMX233_PWM_MAX_PERIOD   (1 << 16)
 
 #define IMX233_PWM_NR_CHANNELS  5
diff --git a/firmware/target/arm/imx233/regs/regs-hwecc.h b/firmware/target/arm/imx233/regs/anatop.h
index f156ef492c..2eec65a526 100644
--- a/firmware/target/arm/imx233/regs/regs-hwecc.h
+++ b/firmware/target/arm/imx233/regs/anatop.h
@@ -6,10 +6,9 @@
  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
  *                     \/            \/     \/    \/            \/
  * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3600:2.3.0
+ * headergen version: 3.0.0
  *
- * Copyright (C) 2013 by Amaury Pouly
+ * Copyright (C) 2015 by the authors
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
@@ -20,14 +19,15 @@
  * KIND, either express or implied.
  *
  ****************************************************************************/
-#ifndef __SELECT__HWECC__H__
-#define __SELECT__HWECC__H__
-#include "regs-macro.h"
+#ifndef __HEADERGEN_ANATOP_H__
+#define __HEADERGEN_ANATOP_H__
 
-#define STMP3600_INCLUDE "stmp3600/regs-hwecc.h"
+#include "macro.h"
 
-#include "regs-select.h"
+#define STMP3600_INCLUDE    "stmp3600/anatop.h"
+
+#include "select.h"
 
 #undef STMP3600_INCLUDE
 
-#endif /* __SELECT__HWECC__H__ */
+#endif /* __HEADERGEN_ANATOP_H__*/
diff --git a/firmware/target/arm/imx233/regs/apbh.h b/firmware/target/arm/imx233/regs/apbh.h
new file mode 100644
index 0000000000..ba97a2f67c
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/apbh.h
@@ -0,0 +1,37 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_APBH_H__
+#define __HEADERGEN_APBH_H__
+
+#include "macro.h"
+
+#define STMP3600_INCLUDE    "stmp3600/apbh.h"
+#define STMP3700_INCLUDE    "stmp3700/apbh.h"
+#define IMX233_INCLUDE      "imx233/apbh.h"
+
+#include "select.h"
+
+#undef STMP3600_INCLUDE
+#undef STMP3700_INCLUDE
+#undef IMX233_INCLUDE
+
+#endif /* __HEADERGEN_APBH_H__*/
diff --git a/firmware/target/arm/imx233/regs/apbx.h b/firmware/target/arm/imx233/regs/apbx.h
new file mode 100644
index 0000000000..9ef52b9a24
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/apbx.h
@@ -0,0 +1,37 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_APBX_H__
+#define __HEADERGEN_APBX_H__
+
+#include "macro.h"
+
+#define STMP3600_INCLUDE    "stmp3600/apbx.h"
+#define STMP3700_INCLUDE    "stmp3700/apbx.h"
+#define IMX233_INCLUDE      "imx233/apbx.h"
+
+#include "select.h"
+
+#undef STMP3600_INCLUDE
+#undef STMP3700_INCLUDE
+#undef IMX233_INCLUDE
+
+#endif /* __HEADERGEN_APBX_H__*/
diff --git a/firmware/target/arm/imx233/regs/regs-arc.h b/firmware/target/arm/imx233/regs/arc.h
index 412cf56590..cbec580697 100644
--- a/firmware/target/arm/imx233/regs/regs-arc.h
+++ b/firmware/target/arm/imx233/regs/arc.h
@@ -6,10 +6,9 @@
  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
  *                     \/            \/     \/    \/            \/
  * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3600:2.3.0
+ * headergen version: 3.0.0
  *
- * Copyright (C) 2013 by Amaury Pouly
+ * Copyright (C) 2015 by the authors
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
@@ -20,14 +19,15 @@
  * KIND, either express or implied.
  *
  ****************************************************************************/
-#ifndef __SELECT__ARC__H__
-#define __SELECT__ARC__H__
-#include "regs-macro.h"
+#ifndef __HEADERGEN_ARC_H__
+#define __HEADERGEN_ARC_H__
 
-#define STMP3600_INCLUDE "stmp3600/regs-arc.h"
+#include "macro.h"
 
-#include "regs-select.h"
+#define STMP3600_INCLUDE    "stmp3600/arc.h"
+
+#include "select.h"
 
 #undef STMP3600_INCLUDE
 
-#endif /* __SELECT__ARC__H__ */
+#endif /* __HEADERGEN_ARC_H__*/
diff --git a/firmware/target/arm/imx233/regs/audioin.h b/firmware/target/arm/imx233/regs/audioin.h
new file mode 100644
index 0000000000..8abf7443eb
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/audioin.h
@@ -0,0 +1,37 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_AUDIOIN_H__
+#define __HEADERGEN_AUDIOIN_H__
+
+#include "macro.h"
+
+#define STMP3600_INCLUDE    "stmp3600/audioin.h"
+#define STMP3700_INCLUDE    "stmp3700/audioin.h"
+#define IMX233_INCLUDE      "imx233/audioin.h"
+
+#include "select.h"
+
+#undef STMP3600_INCLUDE
+#undef STMP3700_INCLUDE
+#undef IMX233_INCLUDE
+
+#endif /* __HEADERGEN_AUDIOIN_H__*/
diff --git a/firmware/target/arm/imx233/regs/audioout.h b/firmware/target/arm/imx233/regs/audioout.h
new file mode 100644
index 0000000000..04d5c0f811
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/audioout.h
@@ -0,0 +1,37 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_AUDIOOUT_H__
+#define __HEADERGEN_AUDIOOUT_H__
+
+#include "macro.h"
+
+#define STMP3600_INCLUDE    "stmp3600/audioout.h"
+#define STMP3700_INCLUDE    "stmp3700/audioout.h"
+#define IMX233_INCLUDE      "imx233/audioout.h"
+
+#include "select.h"
+
+#undef STMP3600_INCLUDE
+#undef STMP3700_INCLUDE
+#undef IMX233_INCLUDE
+
+#endif /* __HEADERGEN_AUDIOOUT_H__*/
diff --git a/firmware/target/arm/imx233/regs/regs-bch.h b/firmware/target/arm/imx233/regs/bch.h
index 014f01385a..ff16dbd307 100644
--- a/firmware/target/arm/imx233/regs/regs-bch.h
+++ b/firmware/target/arm/imx233/regs/bch.h
@@ -6,10 +6,9 @@
  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
  *                     \/            \/     \/    \/            \/
  * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: imx233:3.2.0
+ * headergen version: 3.0.0
  *
- * Copyright (C) 2013 by Amaury Pouly
+ * Copyright (C) 2015 by the authors
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
@@ -20,14 +19,15 @@
  * KIND, either express or implied.
  *
  ****************************************************************************/
-#ifndef __SELECT__BCH__H__
-#define __SELECT__BCH__H__
-#include "regs-macro.h"
+#ifndef __HEADERGEN_BCH_H__
+#define __HEADERGEN_BCH_H__
 
-#define IMX233_INCLUDE "imx233/regs-bch.h"
+#include "macro.h"
 
-#include "regs-select.h"
+#define IMX233_INCLUDE  "imx233/bch.h"
+
+#include "select.h"
 
 #undef IMX233_INCLUDE
 
-#endif /* __SELECT__BCH__H__ */
+#endif /* __HEADERGEN_BCH_H__*/
diff --git a/firmware/target/arm/imx233/regs/clkctrl.h b/firmware/target/arm/imx233/regs/clkctrl.h
new file mode 100644
index 0000000000..8868495ec2
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/clkctrl.h
@@ -0,0 +1,37 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_CLKCTRL_H__
+#define __HEADERGEN_CLKCTRL_H__
+
+#include "macro.h"
+
+#define STMP3600_INCLUDE    "stmp3600/clkctrl.h"
+#define STMP3700_INCLUDE    "stmp3700/clkctrl.h"
+#define IMX233_INCLUDE      "imx233/clkctrl.h"
+
+#include "select.h"
+
+#undef STMP3600_INCLUDE
+#undef STMP3700_INCLUDE
+#undef IMX233_INCLUDE
+
+#endif /* __HEADERGEN_CLKCTRL_H__*/
diff --git a/firmware/target/arm/imx233/regs/regs-anatop.h b/firmware/target/arm/imx233/regs/dacdma.h
index 4072dc77d6..f0c42e88f1 100644
--- a/firmware/target/arm/imx233/regs/regs-anatop.h
+++ b/firmware/target/arm/imx233/regs/dacdma.h
@@ -6,10 +6,9 @@
  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
  *                     \/            \/     \/    \/            \/
  * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3600:2.3.0
+ * headergen version: 3.0.0
  *
- * Copyright (C) 2013 by Amaury Pouly
+ * Copyright (C) 2015 by the authors
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
@@ -20,14 +19,15 @@
  * KIND, either express or implied.
  *
  ****************************************************************************/
-#ifndef __SELECT__ANATOP__H__
-#define __SELECT__ANATOP__H__
-#include "regs-macro.h"
+#ifndef __HEADERGEN_DACDMA_H__
+#define __HEADERGEN_DACDMA_H__
 
-#define STMP3600_INCLUDE "stmp3600/regs-anatop.h"
+#include "macro.h"
 
-#include "regs-select.h"
+#define STMP3600_INCLUDE    "stmp3600/dacdma.h"
+
+#include "select.h"
 
 #undef STMP3600_INCLUDE
 
-#endif /* __SELECT__ANATOP__H__ */
+#endif /* __HEADERGEN_DACDMA_H__*/
diff --git a/firmware/target/arm/imx233/regs/dcp.h b/firmware/target/arm/imx233/regs/dcp.h
new file mode 100644
index 0000000000..5b72092248
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/dcp.h
@@ -0,0 +1,35 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_DCP_H__
+#define __HEADERGEN_DCP_H__
+
+#include "macro.h"
+
+#define STMP3700_INCLUDE    "stmp3700/dcp.h"
+#define IMX233_INCLUDE      "imx233/dcp.h"
+
+#include "select.h"
+
+#undef STMP3700_INCLUDE
+#undef IMX233_INCLUDE
+
+#endif /* __HEADERGEN_DCP_H__*/
diff --git a/firmware/target/arm/imx233/regs/digctl.h b/firmware/target/arm/imx233/regs/digctl.h
new file mode 100644
index 0000000000..27ee2c5b2e
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/digctl.h
@@ -0,0 +1,37 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_DIGCTL_H__
+#define __HEADERGEN_DIGCTL_H__
+
+#include "macro.h"
+
+#define STMP3600_INCLUDE    "stmp3600/digctl.h"
+#define STMP3700_INCLUDE    "stmp3700/digctl.h"
+#define IMX233_INCLUDE      "imx233/digctl.h"
+
+#include "select.h"
+
+#undef STMP3600_INCLUDE
+#undef STMP3700_INCLUDE
+#undef IMX233_INCLUDE
+
+#endif /* __HEADERGEN_DIGCTL_H__*/
diff --git a/firmware/target/arm/imx233/regs/dram.h b/firmware/target/arm/imx233/regs/dram.h
new file mode 100644
index 0000000000..dbd700ed9f
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/dram.h
@@ -0,0 +1,35 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_DRAM_H__
+#define __HEADERGEN_DRAM_H__
+
+#include "macro.h"
+
+#define STMP3700_INCLUDE    "stmp3700/dram.h"
+#define IMX233_INCLUDE      "imx233/dram.h"
+
+#include "select.h"
+
+#undef STMP3700_INCLUDE
+#undef IMX233_INCLUDE
+
+#endif /* __HEADERGEN_DRAM_H__*/
diff --git a/firmware/target/arm/imx233/regs/regs-dram.h b/firmware/target/arm/imx233/regs/dri.h
index ab9ff93624..7b72d85e7b 100644
--- a/firmware/target/arm/imx233/regs/regs-dram.h
+++ b/firmware/target/arm/imx233/regs/dri.h
@@ -6,10 +6,9 @@
  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
  *                     \/            \/     \/    \/            \/
  * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3700:3.2.0 imx233:3.2.0
+ * headergen version: 3.0.0
  *
- * Copyright (C) 2013 by Amaury Pouly
+ * Copyright (C) 2015 by the authors
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
@@ -20,16 +19,19 @@
  * KIND, either express or implied.
  *
  ****************************************************************************/
-#ifndef __SELECT__DRAM__H__
-#define __SELECT__DRAM__H__
-#include "regs-macro.h"
+#ifndef __HEADERGEN_DRI_H__
+#define __HEADERGEN_DRI_H__
 
-#define STMP3700_INCLUDE "stmp3700/regs-dram.h"
-#define IMX233_INCLUDE "imx233/regs-dram.h"
+#include "macro.h"
 
-#include "regs-select.h"
+#define STMP3600_INCLUDE    "stmp3600/dri.h"
+#define STMP3700_INCLUDE    "stmp3700/dri.h"
+#define IMX233_INCLUDE      "imx233/dri.h"
 
+#include "select.h"
+
+#undef STMP3600_INCLUDE
 #undef STMP3700_INCLUDE
 #undef IMX233_INCLUDE
 
-#endif /* __SELECT__DRAM__H__ */
+#endif /* __HEADERGEN_DRI_H__*/
diff --git a/firmware/target/arm/imx233/regs/ecc8.h b/firmware/target/arm/imx233/regs/ecc8.h
new file mode 100644
index 0000000000..66ff437f06
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/ecc8.h
@@ -0,0 +1,35 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_ECC8_H__
+#define __HEADERGEN_ECC8_H__
+
+#include "macro.h"
+
+#define STMP3700_INCLUDE    "stmp3700/ecc8.h"
+#define IMX233_INCLUDE      "imx233/ecc8.h"
+
+#include "select.h"
+
+#undef STMP3700_INCLUDE
+#undef IMX233_INCLUDE
+
+#endif /* __HEADERGEN_ECC8_H__*/
diff --git a/firmware/target/arm/imx233/regs/regs-ecc8.h b/firmware/target/arm/imx233/regs/emi.h
index b8be14b90c..969bcafae4 100644
--- a/firmware/target/arm/imx233/regs/regs-ecc8.h
+++ b/firmware/target/arm/imx233/regs/emi.h
@@ -6,10 +6,9 @@
  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
  *                     \/            \/     \/    \/            \/
  * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3700:3.2.0 imx233:3.2.0
+ * headergen version: 3.0.0
  *
- * Copyright (C) 2013 by Amaury Pouly
+ * Copyright (C) 2015 by the authors
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
@@ -20,16 +19,19 @@
  * KIND, either express or implied.
  *
  ****************************************************************************/
-#ifndef __SELECT__ECC8__H__
-#define __SELECT__ECC8__H__
-#include "regs-macro.h"
+#ifndef __HEADERGEN_EMI_H__
+#define __HEADERGEN_EMI_H__
 
-#define STMP3700_INCLUDE "stmp3700/regs-ecc8.h"
-#define IMX233_INCLUDE "imx233/regs-ecc8.h"
+#include "macro.h"
 
-#include "regs-select.h"
+#define STMP3600_INCLUDE    "stmp3600/emi.h"
+#define STMP3700_INCLUDE    "stmp3700/emi.h"
+#define IMX233_INCLUDE      "imx233/emi.h"
 
+#include "select.h"
+
+#undef STMP3600_INCLUDE
 #undef STMP3700_INCLUDE
 #undef IMX233_INCLUDE
 
-#endif /* __SELECT__ECC8__H__ */
+#endif /* __HEADERGEN_EMI_H__*/
diff --git a/firmware/target/arm/imx233/regs/regs-gpiomon.h b/firmware/target/arm/imx233/regs/gpiomon.h
index 1a04fa45fb..1336d6cc77 100644
--- a/firmware/target/arm/imx233/regs/regs-gpiomon.h
+++ b/firmware/target/arm/imx233/regs/gpiomon.h
@@ -6,10 +6,9 @@
  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
  *                     \/            \/     \/    \/            \/
  * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3700:3.2.0
+ * headergen version: 3.0.0
  *
- * Copyright (C) 2013 by Amaury Pouly
+ * Copyright (C) 2015 by the authors
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
@@ -20,14 +19,15 @@
  * KIND, either express or implied.
  *
  ****************************************************************************/
-#ifndef __SELECT__GPIOMON__H__
-#define __SELECT__GPIOMON__H__
-#include "regs-macro.h"
+#ifndef __HEADERGEN_GPIOMON_H__
+#define __HEADERGEN_GPIOMON_H__
 
-#define STMP3700_INCLUDE "stmp3700/regs-gpiomon.h"
+#include "macro.h"
 
-#include "regs-select.h"
+#define STMP3700_INCLUDE    "stmp3700/gpiomon.h"
+
+#include "select.h"
 
 #undef STMP3700_INCLUDE
 
-#endif /* __SELECT__GPIOMON__H__ */
+#endif /* __HEADERGEN_GPIOMON_H__*/
diff --git a/firmware/target/arm/imx233/regs/gpmi.h b/firmware/target/arm/imx233/regs/gpmi.h
new file mode 100644
index 0000000000..7b234d12d2
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/gpmi.h
@@ -0,0 +1,37 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_GPMI_H__
+#define __HEADERGEN_GPMI_H__
+
+#include "macro.h"
+
+#define STMP3600_INCLUDE    "stmp3600/gpmi.h"
+#define STMP3700_INCLUDE    "stmp3700/gpmi.h"
+#define IMX233_INCLUDE      "imx233/gpmi.h"
+
+#include "select.h"
+
+#undef STMP3600_INCLUDE
+#undef STMP3700_INCLUDE
+#undef IMX233_INCLUDE
+
+#endif /* __HEADERGEN_GPMI_H__*/
diff --git a/firmware/target/arm/imx233/regs/regs-dacdma.h b/firmware/target/arm/imx233/regs/hwecc.h
index 0b36addc9e..d7bc8390fb 100644
--- a/firmware/target/arm/imx233/regs/regs-dacdma.h
+++ b/firmware/target/arm/imx233/regs/hwecc.h
@@ -6,10 +6,9 @@
  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
  *                     \/            \/     \/    \/            \/
  * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3600:2.3.0
+ * headergen version: 3.0.0
  *
- * Copyright (C) 2013 by Amaury Pouly
+ * Copyright (C) 2015 by the authors
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
@@ -20,14 +19,15 @@
  * KIND, either express or implied.
  *
  ****************************************************************************/
-#ifndef __SELECT__DACDMA__H__
-#define __SELECT__DACDMA__H__
-#include "regs-macro.h"
+#ifndef __HEADERGEN_HWECC_H__
+#define __HEADERGEN_HWECC_H__
 
-#define STMP3600_INCLUDE "stmp3600/regs-dacdma.h"
+#include "macro.h"
 
-#include "regs-select.h"
+#define STMP3600_INCLUDE    "stmp3600/hwecc.h"
+
+#include "select.h"
 
 #undef STMP3600_INCLUDE
 
-#endif /* __SELECT__DACDMA__H__ */
+#endif /* __HEADERGEN_HWECC_H__*/
diff --git a/firmware/target/arm/imx233/regs/regs-ocotp.h b/firmware/target/arm/imx233/regs/i2c.h
index 14ded64ea3..7ec29a13bb 100644
--- a/firmware/target/arm/imx233/regs/regs-ocotp.h
+++ b/firmware/target/arm/imx233/regs/i2c.h
@@ -6,10 +6,9 @@
  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
  *                     \/            \/     \/    \/            \/
  * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3700:3.2.0 imx233:3.2.0
+ * headergen version: 3.0.0
  *
- * Copyright (C) 2013 by Amaury Pouly
+ * Copyright (C) 2015 by the authors
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
@@ -20,16 +19,19 @@
  * KIND, either express or implied.
  *
  ****************************************************************************/
-#ifndef __SELECT__OCOTP__H__
-#define __SELECT__OCOTP__H__
-#include "regs-macro.h"
+#ifndef __HEADERGEN_I2C_H__
+#define __HEADERGEN_I2C_H__
 
-#define STMP3700_INCLUDE "stmp3700/regs-ocotp.h"
-#define IMX233_INCLUDE "imx233/regs-ocotp.h"
+#include "macro.h"
 
-#include "regs-select.h"
+#define STMP3600_INCLUDE    "stmp3600/i2c.h"
+#define STMP3700_INCLUDE    "stmp3700/i2c.h"
+#define IMX233_INCLUDE      "imx233/i2c.h"
 
+#include "select.h"
+
+#undef STMP3600_INCLUDE
 #undef STMP3700_INCLUDE
 #undef IMX233_INCLUDE
 
-#endif /* __SELECT__OCOTP__H__ */
+#endif /* __HEADERGEN_I2C_H__*/
diff --git a/firmware/target/arm/imx233/regs/icoll.h b/firmware/target/arm/imx233/regs/icoll.h
new file mode 100644
index 0000000000..5d945b95bd
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/icoll.h
@@ -0,0 +1,37 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_ICOLL_H__
+#define __HEADERGEN_ICOLL_H__
+
+#include "macro.h"
+
+#define STMP3600_INCLUDE    "stmp3600/icoll.h"
+#define STMP3700_INCLUDE    "stmp3700/icoll.h"
+#define IMX233_INCLUDE      "imx233/icoll.h"
+
+#include "select.h"
+
+#undef STMP3600_INCLUDE
+#undef STMP3700_INCLUDE
+#undef IMX233_INCLUDE
+
+#endif /* __HEADERGEN_ICOLL_H__*/
diff --git a/firmware/target/arm/imx233/regs/imx233/apbh.h b/firmware/target/arm/imx233/regs/imx233/apbh.h
new file mode 100644
index 0000000000..9500ff086e
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/imx233/apbh.h
@@ -0,0 +1,554 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * imx233 version: 2.4.0
+ * imx233 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_IMX233_APBH_H__
+#define __HEADERGEN_IMX233_APBH_H__
+
+#define HW_APBH_CTRL0                           HW(APBH_CTRL0)
+#define HWA_APBH_CTRL0                          (0x80004000 + 0x0)
+#define HWT_APBH_CTRL0                          HWIO_32_RW
+#define HWN_APBH_CTRL0                          APBH_CTRL0
+#define HWI_APBH_CTRL0                          
+#define HW_APBH_CTRL0_SET                       HW(APBH_CTRL0_SET)
+#define HWA_APBH_CTRL0_SET                      (HWA_APBH_CTRL0 + 0x4)
+#define HWT_APBH_CTRL0_SET                      HWIO_32_WO
+#define HWN_APBH_CTRL0_SET                      APBH_CTRL0
+#define HWI_APBH_CTRL0_SET                      
+#define HW_APBH_CTRL0_CLR                       HW(APBH_CTRL0_CLR)
+#define HWA_APBH_CTRL0_CLR                      (HWA_APBH_CTRL0 + 0x8)
+#define HWT_APBH_CTRL0_CLR                      HWIO_32_WO
+#define HWN_APBH_CTRL0_CLR                      APBH_CTRL0
+#define HWI_APBH_CTRL0_CLR                      
+#define HW_APBH_CTRL0_TOG                       HW(APBH_CTRL0_TOG)
+#define HWA_APBH_CTRL0_TOG                      (HWA_APBH_CTRL0 + 0xc)
+#define HWT_APBH_CTRL0_TOG                      HWIO_32_WO
+#define HWN_APBH_CTRL0_TOG                      APBH_CTRL0
+#define HWI_APBH_CTRL0_TOG                      
+#define BP_APBH_CTRL0_SFTRST                    31
+#define BM_APBH_CTRL0_SFTRST                    0x80000000
+#define BF_APBH_CTRL0_SFTRST(v)                 (((v) & 0x1) << 31)
+#define BFM_APBH_CTRL0_SFTRST(v)                BM_APBH_CTRL0_SFTRST
+#define BF_APBH_CTRL0_SFTRST_V(e)               BF_APBH_CTRL0_SFTRST(BV_APBH_CTRL0_SFTRST__##e)
+#define BFM_APBH_CTRL0_SFTRST_V(v)              BM_APBH_CTRL0_SFTRST
+#define BP_APBH_CTRL0_CLKGATE                   30
+#define BM_APBH_CTRL0_CLKGATE                   0x40000000
+#define BF_APBH_CTRL0_CLKGATE(v)                (((v) & 0x1) << 30)
+#define BFM_APBH_CTRL0_CLKGATE(v)               BM_APBH_CTRL0_CLKGATE
+#define BF_APBH_CTRL0_CLKGATE_V(e)              BF_APBH_CTRL0_CLKGATE(BV_APBH_CTRL0_CLKGATE__##e)
+#define BFM_APBH_CTRL0_CLKGATE_V(v)             BM_APBH_CTRL0_CLKGATE
+#define BP_APBH_CTRL0_AHB_BURST8_EN             29
+#define BM_APBH_CTRL0_AHB_BURST8_EN             0x20000000
+#define BF_APBH_CTRL0_AHB_BURST8_EN(v)          (((v) & 0x1) << 29)
+#define BFM_APBH_CTRL0_AHB_BURST8_EN(v)         BM_APBH_CTRL0_AHB_BURST8_EN
+#define BF_APBH_CTRL0_AHB_BURST8_EN_V(e)        BF_APBH_CTRL0_AHB_BURST8_EN(BV_APBH_CTRL0_AHB_BURST8_EN__##e)
+#define BFM_APBH_CTRL0_AHB_BURST8_EN_V(v)       BM_APBH_CTRL0_AHB_BURST8_EN
+#define BP_APBH_CTRL0_APB_BURST4_EN             28
+#define BM_APBH_CTRL0_APB_BURST4_EN             0x10000000
+#define BF_APBH_CTRL0_APB_BURST4_EN(v)          (((v) & 0x1) << 28)
+#define BFM_APBH_CTRL0_APB_BURST4_EN(v)         BM_APBH_CTRL0_APB_BURST4_EN
+#define BF_APBH_CTRL0_APB_BURST4_EN_V(e)        BF_APBH_CTRL0_APB_BURST4_EN(BV_APBH_CTRL0_APB_BURST4_EN__##e)
+#define BFM_APBH_CTRL0_APB_BURST4_EN_V(v)       BM_APBH_CTRL0_APB_BURST4_EN
+#define BP_APBH_CTRL0_RSVD0                     24
+#define BM_APBH_CTRL0_RSVD0                     0xf000000
+#define BF_APBH_CTRL0_RSVD0(v)                  (((v) & 0xf) << 24)
+#define BFM_APBH_CTRL0_RSVD0(v)                 BM_APBH_CTRL0_RSVD0
+#define BF_APBH_CTRL0_RSVD0_V(e)                BF_APBH_CTRL0_RSVD0(BV_APBH_CTRL0_RSVD0__##e)
+#define BFM_APBH_CTRL0_RSVD0_V(v)               BM_APBH_CTRL0_RSVD0
+#define BP_APBH_CTRL0_RESET_CHANNEL             16
+#define BM_APBH_CTRL0_RESET_CHANNEL             0xff0000
+#define BV_APBH_CTRL0_RESET_CHANNEL__SSP1       0x2
+#define BV_APBH_CTRL0_RESET_CHANNEL__SSP2       0x4
+#define BV_APBH_CTRL0_RESET_CHANNEL__ATA        0x10
+#define BV_APBH_CTRL0_RESET_CHANNEL__NAND0      0x10
+#define BV_APBH_CTRL0_RESET_CHANNEL__NAND1      0x20
+#define BV_APBH_CTRL0_RESET_CHANNEL__NAND2      0x40
+#define BV_APBH_CTRL0_RESET_CHANNEL__NAND3      0x80
+#define BF_APBH_CTRL0_RESET_CHANNEL(v)          (((v) & 0xff) << 16)
+#define BFM_APBH_CTRL0_RESET_CHANNEL(v)         BM_APBH_CTRL0_RESET_CHANNEL
+#define BF_APBH_CTRL0_RESET_CHANNEL_V(e)        BF_APBH_CTRL0_RESET_CHANNEL(BV_APBH_CTRL0_RESET_CHANNEL__##e)
+#define BFM_APBH_CTRL0_RESET_CHANNEL_V(v)       BM_APBH_CTRL0_RESET_CHANNEL
+#define BP_APBH_CTRL0_CLKGATE_CHANNEL           8
+#define BM_APBH_CTRL0_CLKGATE_CHANNEL           0xff00
+#define BV_APBH_CTRL0_CLKGATE_CHANNEL__SSP1     0x2
+#define BV_APBH_CTRL0_CLKGATE_CHANNEL__SSP2     0x4
+#define BV_APBH_CTRL0_CLKGATE_CHANNEL__ATA      0x10
+#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND0    0x10
+#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND1    0x20
+#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND2    0x40
+#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND3    0x80
+#define BF_APBH_CTRL0_CLKGATE_CHANNEL(v)        (((v) & 0xff) << 8)
+#define BFM_APBH_CTRL0_CLKGATE_CHANNEL(v)       BM_APBH_CTRL0_CLKGATE_CHANNEL
+#define BF_APBH_CTRL0_CLKGATE_CHANNEL_V(e)      BF_APBH_CTRL0_CLKGATE_CHANNEL(BV_APBH_CTRL0_CLKGATE_CHANNEL__##e)
+#define BFM_APBH_CTRL0_CLKGATE_CHANNEL_V(v)     BM_APBH_CTRL0_CLKGATE_CHANNEL
+#define BP_APBH_CTRL0_FREEZE_CHANNEL            0
+#define BM_APBH_CTRL0_FREEZE_CHANNEL            0xff
+#define BV_APBH_CTRL0_FREEZE_CHANNEL__SSP1      0x2
+#define BV_APBH_CTRL0_FREEZE_CHANNEL__SSP2      0x4
+#define BV_APBH_CTRL0_FREEZE_CHANNEL__ATA       0x10
+#define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND0     0x10
+#define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND1     0x20
+#define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND2     0x40
+#define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND3     0x80
+#define BF_APBH_CTRL0_FREEZE_CHANNEL(v)         (((v) & 0xff) << 0)
+#define BFM_APBH_CTRL0_FREEZE_CHANNEL(v)        BM_APBH_CTRL0_FREEZE_CHANNEL
+#define BF_APBH_CTRL0_FREEZE_CHANNEL_V(e)       BF_APBH_CTRL0_FREEZE_CHANNEL(BV_APBH_CTRL0_FREEZE_CHANNEL__##e)
+#define BFM_APBH_CTRL0_FREEZE_CHANNEL_V(v)      BM_APBH_CTRL0_FREEZE_CHANNEL
+
+#define HW_APBH_CTRL1                           HW(APBH_CTRL1)
+#define HWA_APBH_CTRL1                          (0x80004000 + 0x10)
+#define HWT_APBH_CTRL1                          HWIO_32_RW
+#define HWN_APBH_CTRL1                          APBH_CTRL1
+#define HWI_APBH_CTRL1                          
+#define HW_APBH_CTRL1_SET                       HW(APBH_CTRL1_SET)
+#define HWA_APBH_CTRL1_SET                      (HWA_APBH_CTRL1 + 0x4)
+#define HWT_APBH_CTRL1_SET                      HWIO_32_WO
+#define HWN_APBH_CTRL1_SET                      APBH_CTRL1
+#define HWI_APBH_CTRL1_SET                      
+#define HW_APBH_CTRL1_CLR                       HW(APBH_CTRL1_CLR)
+#define HWA_APBH_CTRL1_CLR                      (HWA_APBH_CTRL1 + 0x8)
+#define HWT_APBH_CTRL1_CLR                      HWIO_32_WO
+#define HWN_APBH_CTRL1_CLR                      APBH_CTRL1
+#define HWI_APBH_CTRL1_CLR                      
+#define HW_APBH_CTRL1_TOG                       HW(APBH_CTRL1_TOG)
+#define HWA_APBH_CTRL1_TOG                      (HWA_APBH_CTRL1 + 0xc)
+#define HWT_APBH_CTRL1_TOG                      HWIO_32_WO
+#define HWN_APBH_CTRL1_TOG                      APBH_CTRL1
+#define HWI_APBH_CTRL1_TOG                      
+#define BP_APBH_CTRL1_RSVD1                     24
+#define BM_APBH_CTRL1_RSVD1                     0xff000000
+#define BF_APBH_CTRL1_RSVD1(v)                  (((v) & 0xff) << 24)
+#define BFM_APBH_CTRL1_RSVD1(v)                 BM_APBH_CTRL1_RSVD1
+#define BF_APBH_CTRL1_RSVD1_V(e)                BF_APBH_CTRL1_RSVD1(BV_APBH_CTRL1_RSVD1__##e)
+#define BFM_APBH_CTRL1_RSVD1_V(v)               BM_APBH_CTRL1_RSVD1
+#define BP_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN        16
+#define BM_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN        0xff0000
+#define BF_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN(v)     (((v) & 0xff) << 16)
+#define BFM_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN(v)    BM_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN
+#define BF_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_V(e)   BF_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN(BV_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN__##e)
+#define BFM_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_V(v)  BM_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN
+#define BP_APBH_CTRL1_RSVD0                     8
+#define BM_APBH_CTRL1_RSVD0                     0xff00
+#define BF_APBH_CTRL1_RSVD0(v)                  (((v) & 0xff) << 8)
+#define BFM_APBH_CTRL1_RSVD0(v)                 BM_APBH_CTRL1_RSVD0
+#define BF_APBH_CTRL1_RSVD0_V(e)                BF_APBH_CTRL1_RSVD0(BV_APBH_CTRL1_RSVD0__##e)
+#define BFM_APBH_CTRL1_RSVD0_V(v)               BM_APBH_CTRL1_RSVD0
+#define BP_APBH_CTRL1_CH_CMDCMPLT_IRQ           0
+#define BM_APBH_CTRL1_CH_CMDCMPLT_IRQ           0xff
+#define BF_APBH_CTRL1_CH_CMDCMPLT_IRQ(v)        (((v) & 0xff) << 0)
+#define BFM_APBH_CTRL1_CH_CMDCMPLT_IRQ(v)       BM_APBH_CTRL1_CH_CMDCMPLT_IRQ
+#define BF_APBH_CTRL1_CH_CMDCMPLT_IRQ_V(e)      BF_APBH_CTRL1_CH_CMDCMPLT_IRQ(BV_APBH_CTRL1_CH_CMDCMPLT_IRQ__##e)
+#define BFM_APBH_CTRL1_CH_CMDCMPLT_IRQ_V(v)     BM_APBH_CTRL1_CH_CMDCMPLT_IRQ
+
+#define HW_APBH_CTRL2                       HW(APBH_CTRL2)
+#define HWA_APBH_CTRL2                      (0x80004000 + 0x20)
+#define HWT_APBH_CTRL2                      HWIO_32_RW
+#define HWN_APBH_CTRL2                      APBH_CTRL2
+#define HWI_APBH_CTRL2                      
+#define HW_APBH_CTRL2_SET                   HW(APBH_CTRL2_SET)
+#define HWA_APBH_CTRL2_SET                  (HWA_APBH_CTRL2 + 0x4)
+#define HWT_APBH_CTRL2_SET                  HWIO_32_WO
+#define HWN_APBH_CTRL2_SET                  APBH_CTRL2
+#define HWI_APBH_CTRL2_SET                  
+#define HW_APBH_CTRL2_CLR                   HW(APBH_CTRL2_CLR)
+#define HWA_APBH_CTRL2_CLR                  (HWA_APBH_CTRL2 + 0x8)
+#define HWT_APBH_CTRL2_CLR                  HWIO_32_WO
+#define HWN_APBH_CTRL2_CLR                  APBH_CTRL2
+#define HWI_APBH_CTRL2_CLR                  
+#define HW_APBH_CTRL2_TOG                   HW(APBH_CTRL2_TOG)
+#define HWA_APBH_CTRL2_TOG                  (HWA_APBH_CTRL2 + 0xc)
+#define HWT_APBH_CTRL2_TOG                  HWIO_32_WO
+#define HWN_APBH_CTRL2_TOG                  APBH_CTRL2
+#define HWI_APBH_CTRL2_TOG                  
+#define BP_APBH_CTRL2_RSVD1                 24
+#define BM_APBH_CTRL2_RSVD1                 0xff000000
+#define BF_APBH_CTRL2_RSVD1(v)              (((v) & 0xff) << 24)
+#define BFM_APBH_CTRL2_RSVD1(v)             BM_APBH_CTRL2_RSVD1
+#define BF_APBH_CTRL2_RSVD1_V(e)            BF_APBH_CTRL2_RSVD1(BV_APBH_CTRL2_RSVD1__##e)
+#define BFM_APBH_CTRL2_RSVD1_V(v)           BM_APBH_CTRL2_RSVD1
+#define BP_APBH_CTRL2_CH_ERROR_STATUS       16
+#define BM_APBH_CTRL2_CH_ERROR_STATUS       0xff0000
+#define BF_APBH_CTRL2_CH_ERROR_STATUS(v)    (((v) & 0xff) << 16)
+#define BFM_APBH_CTRL2_CH_ERROR_STATUS(v)   BM_APBH_CTRL2_CH_ERROR_STATUS
+#define BF_APBH_CTRL2_CH_ERROR_STATUS_V(e)  BF_APBH_CTRL2_CH_ERROR_STATUS(BV_APBH_CTRL2_CH_ERROR_STATUS__##e)
+#define BFM_APBH_CTRL2_CH_ERROR_STATUS_V(v) BM_APBH_CTRL2_CH_ERROR_STATUS
+#define BP_APBH_CTRL2_RSVD0                 8
+#define BM_APBH_CTRL2_RSVD0                 0xff00
+#define BF_APBH_CTRL2_RSVD0(v)              (((v) & 0xff) << 8)
+#define BFM_APBH_CTRL2_RSVD0(v)             BM_APBH_CTRL2_RSVD0
+#define BF_APBH_CTRL2_RSVD0_V(e)            BF_APBH_CTRL2_RSVD0(BV_APBH_CTRL2_RSVD0__##e)
+#define BFM_APBH_CTRL2_RSVD0_V(v)           BM_APBH_CTRL2_RSVD0
+#define BP_APBH_CTRL2_CH_ERROR_IRQ          0
+#define BM_APBH_CTRL2_CH_ERROR_IRQ          0xff
+#define BF_APBH_CTRL2_CH_ERROR_IRQ(v)       (((v) & 0xff) << 0)
+#define BFM_APBH_CTRL2_CH_ERROR_IRQ(v)      BM_APBH_CTRL2_CH_ERROR_IRQ
+#define BF_APBH_CTRL2_CH_ERROR_IRQ_V(e)     BF_APBH_CTRL2_CH_ERROR_IRQ(BV_APBH_CTRL2_CH_ERROR_IRQ__##e)
+#define BFM_APBH_CTRL2_CH_ERROR_IRQ_V(v)    BM_APBH_CTRL2_CH_ERROR_IRQ
+
+#define HW_APBH_DEVSEL              HW(APBH_DEVSEL)
+#define HWA_APBH_DEVSEL             (0x80004000 + 0x30)
+#define HWT_APBH_DEVSEL             HWIO_32_RW
+#define HWN_APBH_DEVSEL             APBH_DEVSEL
+#define HWI_APBH_DEVSEL             
+#define BP_APBH_DEVSEL_CH7          28
+#define BM_APBH_DEVSEL_CH7          0xf0000000
+#define BF_APBH_DEVSEL_CH7(v)       (((v) & 0xf) << 28)
+#define BFM_APBH_DEVSEL_CH7(v)      BM_APBH_DEVSEL_CH7
+#define BF_APBH_DEVSEL_CH7_V(e)     BF_APBH_DEVSEL_CH7(BV_APBH_DEVSEL_CH7__##e)
+#define BFM_APBH_DEVSEL_CH7_V(v)    BM_APBH_DEVSEL_CH7
+#define BP_APBH_DEVSEL_CH6          24
+#define BM_APBH_DEVSEL_CH6          0xf000000
+#define BF_APBH_DEVSEL_CH6(v)       (((v) & 0xf) << 24)
+#define BFM_APBH_DEVSEL_CH6(v)      BM_APBH_DEVSEL_CH6
+#define BF_APBH_DEVSEL_CH6_V(e)     BF_APBH_DEVSEL_CH6(BV_APBH_DEVSEL_CH6__##e)
+#define BFM_APBH_DEVSEL_CH6_V(v)    BM_APBH_DEVSEL_CH6
+#define BP_APBH_DEVSEL_CH5          20
+#define BM_APBH_DEVSEL_CH5          0xf00000
+#define BF_APBH_DEVSEL_CH5(v)       (((v) & 0xf) << 20)
+#define BFM_APBH_DEVSEL_CH5(v)      BM_APBH_DEVSEL_CH5
+#define BF_APBH_DEVSEL_CH5_V(e)     BF_APBH_DEVSEL_CH5(BV_APBH_DEVSEL_CH5__##e)
+#define BFM_APBH_DEVSEL_CH5_V(v)    BM_APBH_DEVSEL_CH5
+#define BP_APBH_DEVSEL_CH4          16
+#define BM_APBH_DEVSEL_CH4          0xf0000
+#define BF_APBH_DEVSEL_CH4(v)       (((v) & 0xf) << 16)
+#define BFM_APBH_DEVSEL_CH4(v)      BM_APBH_DEVSEL_CH4
+#define BF_APBH_DEVSEL_CH4_V(e)     BF_APBH_DEVSEL_CH4(BV_APBH_DEVSEL_CH4__##e)
+#define BFM_APBH_DEVSEL_CH4_V(v)    BM_APBH_DEVSEL_CH4
+#define BP_APBH_DEVSEL_CH3          12
+#define BM_APBH_DEVSEL_CH3          0xf000
+#define BF_APBH_DEVSEL_CH3(v)       (((v) & 0xf) << 12)
+#define BFM_APBH_DEVSEL_CH3(v)      BM_APBH_DEVSEL_CH3
+#define BF_APBH_DEVSEL_CH3_V(e)     BF_APBH_DEVSEL_CH3(BV_APBH_DEVSEL_CH3__##e)
+#define BFM_APBH_DEVSEL_CH3_V(v)    BM_APBH_DEVSEL_CH3
+#define BP_APBH_DEVSEL_CH2          8
+#define BM_APBH_DEVSEL_CH2          0xf00
+#define BF_APBH_DEVSEL_CH2(v)       (((v) & 0xf) << 8)
+#define BFM_APBH_DEVSEL_CH2(v)      BM_APBH_DEVSEL_CH2
+#define BF_APBH_DEVSEL_CH2_V(e)     BF_APBH_DEVSEL_CH2(BV_APBH_DEVSEL_CH2__##e)
+#define BFM_APBH_DEVSEL_CH2_V(v)    BM_APBH_DEVSEL_CH2
+#define BP_APBH_DEVSEL_CH1          4
+#define BM_APBH_DEVSEL_CH1          0xf0
+#define BF_APBH_DEVSEL_CH1(v)       (((v) & 0xf) << 4)
+#define BFM_APBH_DEVSEL_CH1(v)      BM_APBH_DEVSEL_CH1
+#define BF_APBH_DEVSEL_CH1_V(e)     BF_APBH_DEVSEL_CH1(BV_APBH_DEVSEL_CH1__##e)
+#define BFM_APBH_DEVSEL_CH1_V(v)    BM_APBH_DEVSEL_CH1
+#define BP_APBH_DEVSEL_CH0          0
+#define BM_APBH_DEVSEL_CH0          0xf
+#define BF_APBH_DEVSEL_CH0(v)       (((v) & 0xf) << 0)
+#define BFM_APBH_DEVSEL_CH0(v)      BM_APBH_DEVSEL_CH0
+#define BF_APBH_DEVSEL_CH0_V(e)     BF_APBH_DEVSEL_CH0(BV_APBH_DEVSEL_CH0__##e)
+#define BFM_APBH_DEVSEL_CH0_V(v)    BM_APBH_DEVSEL_CH0
+
+#define HW_APBH_CHn_CURCMDAR(_n1)           HW(APBH_CHn_CURCMDAR(_n1))
+#define HWA_APBH_CHn_CURCMDAR(_n1)          (0x80004000 + 0x40 + (_n1) * 0x70)
+#define HWT_APBH_CHn_CURCMDAR(_n1)          HWIO_32_RW
+#define HWN_APBH_CHn_CURCMDAR(_n1)          APBH_CHn_CURCMDAR
+#define HWI_APBH_CHn_CURCMDAR(_n1)          (_n1)
+#define BP_APBH_CHn_CURCMDAR_CMD_ADDR       0
+#define BM_APBH_CHn_CURCMDAR_CMD_ADDR       0xffffffff
+#define BF_APBH_CHn_CURCMDAR_CMD_ADDR(v)    (((v) & 0xffffffff) << 0)
+#define BFM_APBH_CHn_CURCMDAR_CMD_ADDR(v)   BM_APBH_CHn_CURCMDAR_CMD_ADDR
+#define BF_APBH_CHn_CURCMDAR_CMD_ADDR_V(e)  BF_APBH_CHn_CURCMDAR_CMD_ADDR(BV_APBH_CHn_CURCMDAR_CMD_ADDR__##e)
+#define BFM_APBH_CHn_CURCMDAR_CMD_ADDR_V(v) BM_APBH_CHn_CURCMDAR_CMD_ADDR
+
+#define HW_APBH_CHn_NXTCMDAR(_n1)           HW(APBH_CHn_NXTCMDAR(_n1))
+#define HWA_APBH_CHn_NXTCMDAR(_n1)          (0x80004000 + 0x50 + (_n1) * 0x70)
+#define HWT_APBH_CHn_NXTCMDAR(_n1)          HWIO_32_RW
+#define HWN_APBH_CHn_NXTCMDAR(_n1)          APBH_CHn_NXTCMDAR
+#define HWI_APBH_CHn_NXTCMDAR(_n1)          (_n1)
+#define BP_APBH_CHn_NXTCMDAR_CMD_ADDR       0
+#define BM_APBH_CHn_NXTCMDAR_CMD_ADDR       0xffffffff
+#define BF_APBH_CHn_NXTCMDAR_CMD_ADDR(v)    (((v) & 0xffffffff) << 0)
+#define BFM_APBH_CHn_NXTCMDAR_CMD_ADDR(v)   BM_APBH_CHn_NXTCMDAR_CMD_ADDR
+#define BF_APBH_CHn_NXTCMDAR_CMD_ADDR_V(e)  BF_APBH_CHn_NXTCMDAR_CMD_ADDR(BV_APBH_CHn_NXTCMDAR_CMD_ADDR__##e)
+#define BFM_APBH_CHn_NXTCMDAR_CMD_ADDR_V(v) BM_APBH_CHn_NXTCMDAR_CMD_ADDR
+
+#define HW_APBH_CHn_CMD(_n1)                    HW(APBH_CHn_CMD(_n1))
+#define HWA_APBH_CHn_CMD(_n1)                   (0x80004000 + 0x60 + (_n1) * 0x70)
+#define HWT_APBH_CHn_CMD(_n1)                   HWIO_32_RW
+#define HWN_APBH_CHn_CMD(_n1)                   APBH_CHn_CMD
+#define HWI_APBH_CHn_CMD(_n1)                   (_n1)
+#define BP_APBH_CHn_CMD_XFER_COUNT              16
+#define BM_APBH_CHn_CMD_XFER_COUNT              0xffff0000
+#define BF_APBH_CHn_CMD_XFER_COUNT(v)           (((v) & 0xffff) << 16)
+#define BFM_APBH_CHn_CMD_XFER_COUNT(v)          BM_APBH_CHn_CMD_XFER_COUNT
+#define BF_APBH_CHn_CMD_XFER_COUNT_V(e)         BF_APBH_CHn_CMD_XFER_COUNT(BV_APBH_CHn_CMD_XFER_COUNT__##e)
+#define BFM_APBH_CHn_CMD_XFER_COUNT_V(v)        BM_APBH_CHn_CMD_XFER_COUNT
+#define BP_APBH_CHn_CMD_CMDWORDS                12
+#define BM_APBH_CHn_CMD_CMDWORDS                0xf000
+#define BF_APBH_CHn_CMD_CMDWORDS(v)             (((v) & 0xf) << 12)
+#define BFM_APBH_CHn_CMD_CMDWORDS(v)            BM_APBH_CHn_CMD_CMDWORDS
+#define BF_APBH_CHn_CMD_CMDWORDS_V(e)           BF_APBH_CHn_CMD_CMDWORDS(BV_APBH_CHn_CMD_CMDWORDS__##e)
+#define BFM_APBH_CHn_CMD_CMDWORDS_V(v)          BM_APBH_CHn_CMD_CMDWORDS
+#define BP_APBH_CHn_CMD_RSVD1                   9
+#define BM_APBH_CHn_CMD_RSVD1                   0xe00
+#define BF_APBH_CHn_CMD_RSVD1(v)                (((v) & 0x7) << 9)
+#define BFM_APBH_CHn_CMD_RSVD1(v)               BM_APBH_CHn_CMD_RSVD1
+#define BF_APBH_CHn_CMD_RSVD1_V(e)              BF_APBH_CHn_CMD_RSVD1(BV_APBH_CHn_CMD_RSVD1__##e)
+#define BFM_APBH_CHn_CMD_RSVD1_V(v)             BM_APBH_CHn_CMD_RSVD1
+#define BP_APBH_CHn_CMD_HALTONTERMINATE         8
+#define BM_APBH_CHn_CMD_HALTONTERMINATE         0x100
+#define BF_APBH_CHn_CMD_HALTONTERMINATE(v)      (((v) & 0x1) << 8)
+#define BFM_APBH_CHn_CMD_HALTONTERMINATE(v)     BM_APBH_CHn_CMD_HALTONTERMINATE
+#define BF_APBH_CHn_CMD_HALTONTERMINATE_V(e)    BF_APBH_CHn_CMD_HALTONTERMINATE(BV_APBH_CHn_CMD_HALTONTERMINATE__##e)
+#define BFM_APBH_CHn_CMD_HALTONTERMINATE_V(v)   BM_APBH_CHn_CMD_HALTONTERMINATE
+#define BP_APBH_CHn_CMD_WAIT4ENDCMD             7
+#define BM_APBH_CHn_CMD_WAIT4ENDCMD             0x80
+#define BF_APBH_CHn_CMD_WAIT4ENDCMD(v)          (((v) & 0x1) << 7)
+#define BFM_APBH_CHn_CMD_WAIT4ENDCMD(v)         BM_APBH_CHn_CMD_WAIT4ENDCMD
+#define BF_APBH_CHn_CMD_WAIT4ENDCMD_V(e)        BF_APBH_CHn_CMD_WAIT4ENDCMD(BV_APBH_CHn_CMD_WAIT4ENDCMD__##e)
+#define BFM_APBH_CHn_CMD_WAIT4ENDCMD_V(v)       BM_APBH_CHn_CMD_WAIT4ENDCMD
+#define BP_APBH_CHn_CMD_SEMAPHORE               6
+#define BM_APBH_CHn_CMD_SEMAPHORE               0x40
+#define BF_APBH_CHn_CMD_SEMAPHORE(v)            (((v) & 0x1) << 6)
+#define BFM_APBH_CHn_CMD_SEMAPHORE(v)           BM_APBH_CHn_CMD_SEMAPHORE
+#define BF_APBH_CHn_CMD_SEMAPHORE_V(e)          BF_APBH_CHn_CMD_SEMAPHORE(BV_APBH_CHn_CMD_SEMAPHORE__##e)
+#define BFM_APBH_CHn_CMD_SEMAPHORE_V(v)         BM_APBH_CHn_CMD_SEMAPHORE
+#define BP_APBH_CHn_CMD_NANDWAIT4READY          5
+#define BM_APBH_CHn_CMD_NANDWAIT4READY          0x20
+#define BF_APBH_CHn_CMD_NANDWAIT4READY(v)       (((v) & 0x1) << 5)
+#define BFM_APBH_CHn_CMD_NANDWAIT4READY(v)      BM_APBH_CHn_CMD_NANDWAIT4READY
+#define BF_APBH_CHn_CMD_NANDWAIT4READY_V(e)     BF_APBH_CHn_CMD_NANDWAIT4READY(BV_APBH_CHn_CMD_NANDWAIT4READY__##e)
+#define BFM_APBH_CHn_CMD_NANDWAIT4READY_V(v)    BM_APBH_CHn_CMD_NANDWAIT4READY
+#define BP_APBH_CHn_CMD_NANDLOCK                4
+#define BM_APBH_CHn_CMD_NANDLOCK                0x10
+#define BF_APBH_CHn_CMD_NANDLOCK(v)             (((v) & 0x1) << 4)
+#define BFM_APBH_CHn_CMD_NANDLOCK(v)            BM_APBH_CHn_CMD_NANDLOCK
+#define BF_APBH_CHn_CMD_NANDLOCK_V(e)           BF_APBH_CHn_CMD_NANDLOCK(BV_APBH_CHn_CMD_NANDLOCK__##e)
+#define BFM_APBH_CHn_CMD_NANDLOCK_V(v)          BM_APBH_CHn_CMD_NANDLOCK
+#define BP_APBH_CHn_CMD_IRQONCMPLT              3
+#define BM_APBH_CHn_CMD_IRQONCMPLT              0x8
+#define BF_APBH_CHn_CMD_IRQONCMPLT(v)           (((v) & 0x1) << 3)
+#define BFM_APBH_CHn_CMD_IRQONCMPLT(v)          BM_APBH_CHn_CMD_IRQONCMPLT
+#define BF_APBH_CHn_CMD_IRQONCMPLT_V(e)         BF_APBH_CHn_CMD_IRQONCMPLT(BV_APBH_CHn_CMD_IRQONCMPLT__##e)
+#define BFM_APBH_CHn_CMD_IRQONCMPLT_V(v)        BM_APBH_CHn_CMD_IRQONCMPLT
+#define BP_APBH_CHn_CMD_CHAIN                   2
+#define BM_APBH_CHn_CMD_CHAIN                   0x4
+#define BF_APBH_CHn_CMD_CHAIN(v)                (((v) & 0x1) << 2)
+#define BFM_APBH_CHn_CMD_CHAIN(v)               BM_APBH_CHn_CMD_CHAIN
+#define BF_APBH_CHn_CMD_CHAIN_V(e)              BF_APBH_CHn_CMD_CHAIN(BV_APBH_CHn_CMD_CHAIN__##e)
+#define BFM_APBH_CHn_CMD_CHAIN_V(v)             BM_APBH_CHn_CMD_CHAIN
+#define BP_APBH_CHn_CMD_COMMAND                 0
+#define BM_APBH_CHn_CMD_COMMAND                 0x3
+#define BV_APBH_CHn_CMD_COMMAND__NO_DMA_XFER    0x0
+#define BV_APBH_CHn_CMD_COMMAND__DMA_WRITE      0x1
+#define BV_APBH_CHn_CMD_COMMAND__DMA_READ       0x2
+#define BV_APBH_CHn_CMD_COMMAND__DMA_SENSE      0x3
+#define BF_APBH_CHn_CMD_COMMAND(v)              (((v) & 0x3) << 0)
+#define BFM_APBH_CHn_CMD_COMMAND(v)             BM_APBH_CHn_CMD_COMMAND
+#define BF_APBH_CHn_CMD_COMMAND_V(e)            BF_APBH_CHn_CMD_COMMAND(BV_APBH_CHn_CMD_COMMAND__##e)
+#define BFM_APBH_CHn_CMD_COMMAND_V(v)           BM_APBH_CHn_CMD_COMMAND
+
+#define HW_APBH_CHn_BAR(_n1)            HW(APBH_CHn_BAR(_n1))
+#define HWA_APBH_CHn_BAR(_n1)           (0x80004000 + 0x70 + (_n1) * 0x70)
+#define HWT_APBH_CHn_BAR(_n1)           HWIO_32_RW
+#define HWN_APBH_CHn_BAR(_n1)           APBH_CHn_BAR
+#define HWI_APBH_CHn_BAR(_n1)           (_n1)
+#define BP_APBH_CHn_BAR_ADDRESS         0
+#define BM_APBH_CHn_BAR_ADDRESS         0xffffffff
+#define BF_APBH_CHn_BAR_ADDRESS(v)      (((v) & 0xffffffff) << 0)
+#define BFM_APBH_CHn_BAR_ADDRESS(v)     BM_APBH_CHn_BAR_ADDRESS
+#define BF_APBH_CHn_BAR_ADDRESS_V(e)    BF_APBH_CHn_BAR_ADDRESS(BV_APBH_CHn_BAR_ADDRESS__##e)
+#define BFM_APBH_CHn_BAR_ADDRESS_V(v)   BM_APBH_CHn_BAR_ADDRESS
+
+#define HW_APBH_CHn_SEMA(_n1)                   HW(APBH_CHn_SEMA(_n1))
+#define HWA_APBH_CHn_SEMA(_n1)                  (0x80004000 + 0x80 + (_n1) * 0x70)
+#define HWT_APBH_CHn_SEMA(_n1)                  HWIO_32_RW
+#define HWN_APBH_CHn_SEMA(_n1)                  APBH_CHn_SEMA
+#define HWI_APBH_CHn_SEMA(_n1)                  (_n1)
+#define BP_APBH_CHn_SEMA_RSVD2                  24
+#define BM_APBH_CHn_SEMA_RSVD2                  0xff000000
+#define BF_APBH_CHn_SEMA_RSVD2(v)               (((v) & 0xff) << 24)
+#define BFM_APBH_CHn_SEMA_RSVD2(v)              BM_APBH_CHn_SEMA_RSVD2
+#define BF_APBH_CHn_SEMA_RSVD2_V(e)             BF_APBH_CHn_SEMA_RSVD2(BV_APBH_CHn_SEMA_RSVD2__##e)
+#define BFM_APBH_CHn_SEMA_RSVD2_V(v)            BM_APBH_CHn_SEMA_RSVD2
+#define BP_APBH_CHn_SEMA_PHORE                  16
+#define BM_APBH_CHn_SEMA_PHORE                  0xff0000
+#define BF_APBH_CHn_SEMA_PHORE(v)               (((v) & 0xff) << 16)
+#define BFM_APBH_CHn_SEMA_PHORE(v)              BM_APBH_CHn_SEMA_PHORE
+#define BF_APBH_CHn_SEMA_PHORE_V(e)             BF_APBH_CHn_SEMA_PHORE(BV_APBH_CHn_SEMA_PHORE__##e)
+#define BFM_APBH_CHn_SEMA_PHORE_V(v)            BM_APBH_CHn_SEMA_PHORE
+#define BP_APBH_CHn_SEMA_RSVD1                  8
+#define BM_APBH_CHn_SEMA_RSVD1                  0xff00
+#define BF_APBH_CHn_SEMA_RSVD1(v)               (((v) & 0xff) << 8)
+#define BFM_APBH_CHn_SEMA_RSVD1(v)              BM_APBH_CHn_SEMA_RSVD1
+#define BF_APBH_CHn_SEMA_RSVD1_V(e)             BF_APBH_CHn_SEMA_RSVD1(BV_APBH_CHn_SEMA_RSVD1__##e)
+#define BFM_APBH_CHn_SEMA_RSVD1_V(v)            BM_APBH_CHn_SEMA_RSVD1
+#define BP_APBH_CHn_SEMA_INCREMENT_SEMA         0
+#define BM_APBH_CHn_SEMA_INCREMENT_SEMA         0xff
+#define BF_APBH_CHn_SEMA_INCREMENT_SEMA(v)      (((v) & 0xff) << 0)
+#define BFM_APBH_CHn_SEMA_INCREMENT_SEMA(v)     BM_APBH_CHn_SEMA_INCREMENT_SEMA
+#define BF_APBH_CHn_SEMA_INCREMENT_SEMA_V(e)    BF_APBH_CHn_SEMA_INCREMENT_SEMA(BV_APBH_CHn_SEMA_INCREMENT_SEMA__##e)
+#define BFM_APBH_CHn_SEMA_INCREMENT_SEMA_V(v)   BM_APBH_CHn_SEMA_INCREMENT_SEMA
+
+#define HW_APBH_CHn_DEBUG1(_n1)                             HW(APBH_CHn_DEBUG1(_n1))
+#define HWA_APBH_CHn_DEBUG1(_n1)                            (0x80004000 + 0x90 + (_n1) * 0x70)
+#define HWT_APBH_CHn_DEBUG1(_n1)                            HWIO_32_RW
+#define HWN_APBH_CHn_DEBUG1(_n1)                            APBH_CHn_DEBUG1
+#define HWI_APBH_CHn_DEBUG1(_n1)                            (_n1)
+#define BP_APBH_CHn_DEBUG1_REQ                              31
+#define BM_APBH_CHn_DEBUG1_REQ                              0x80000000
+#define BF_APBH_CHn_DEBUG1_REQ(v)                           (((v) & 0x1) << 31)
+#define BFM_APBH_CHn_DEBUG1_REQ(v)                          BM_APBH_CHn_DEBUG1_REQ
+#define BF_APBH_CHn_DEBUG1_REQ_V(e)                         BF_APBH_CHn_DEBUG1_REQ(BV_APBH_CHn_DEBUG1_REQ__##e)
+#define BFM_APBH_CHn_DEBUG1_REQ_V(v)                        BM_APBH_CHn_DEBUG1_REQ
+#define BP_APBH_CHn_DEBUG1_BURST                            30
+#define BM_APBH_CHn_DEBUG1_BURST                            0x40000000
+#define BF_APBH_CHn_DEBUG1_BURST(v)                         (((v) & 0x1) << 30)
+#define BFM_APBH_CHn_DEBUG1_BURST(v)                        BM_APBH_CHn_DEBUG1_BURST
+#define BF_APBH_CHn_DEBUG1_BURST_V(e)                       BF_APBH_CHn_DEBUG1_BURST(BV_APBH_CHn_DEBUG1_BURST__##e)
+#define BFM_APBH_CHn_DEBUG1_BURST_V(v)                      BM_APBH_CHn_DEBUG1_BURST
+#define BP_APBH_CHn_DEBUG1_KICK                             29
+#define BM_APBH_CHn_DEBUG1_KICK                             0x20000000
+#define BF_APBH_CHn_DEBUG1_KICK(v)                          (((v) & 0x1) << 29)
+#define BFM_APBH_CHn_DEBUG1_KICK(v)                         BM_APBH_CHn_DEBUG1_KICK
+#define BF_APBH_CHn_DEBUG1_KICK_V(e)                        BF_APBH_CHn_DEBUG1_KICK(BV_APBH_CHn_DEBUG1_KICK__##e)
+#define BFM_APBH_CHn_DEBUG1_KICK_V(v)                       BM_APBH_CHn_DEBUG1_KICK
+#define BP_APBH_CHn_DEBUG1_END                              28
+#define BM_APBH_CHn_DEBUG1_END                              0x10000000
+#define BF_APBH_CHn_DEBUG1_END(v)                           (((v) & 0x1) << 28)
+#define BFM_APBH_CHn_DEBUG1_END(v)                          BM_APBH_CHn_DEBUG1_END
+#define BF_APBH_CHn_DEBUG1_END_V(e)                         BF_APBH_CHn_DEBUG1_END(BV_APBH_CHn_DEBUG1_END__##e)
+#define BFM_APBH_CHn_DEBUG1_END_V(v)                        BM_APBH_CHn_DEBUG1_END
+#define BP_APBH_CHn_DEBUG1_SENSE                            27
+#define BM_APBH_CHn_DEBUG1_SENSE                            0x8000000
+#define BF_APBH_CHn_DEBUG1_SENSE(v)                         (((v) & 0x1) << 27)
+#define BFM_APBH_CHn_DEBUG1_SENSE(v)                        BM_APBH_CHn_DEBUG1_SENSE
+#define BF_APBH_CHn_DEBUG1_SENSE_V(e)                       BF_APBH_CHn_DEBUG1_SENSE(BV_APBH_CHn_DEBUG1_SENSE__##e)
+#define BFM_APBH_CHn_DEBUG1_SENSE_V(v)                      BM_APBH_CHn_DEBUG1_SENSE
+#define BP_APBH_CHn_DEBUG1_READY                            26
+#define BM_APBH_CHn_DEBUG1_READY                            0x4000000
+#define BF_APBH_CHn_DEBUG1_READY(v)                         (((v) & 0x1) << 26)
+#define BFM_APBH_CHn_DEBUG1_READY(v)                        BM_APBH_CHn_DEBUG1_READY
+#define BF_APBH_CHn_DEBUG1_READY_V(e)                       BF_APBH_CHn_DEBUG1_READY(BV_APBH_CHn_DEBUG1_READY__##e)
+#define BFM_APBH_CHn_DEBUG1_READY_V(v)                      BM_APBH_CHn_DEBUG1_READY
+#define BP_APBH_CHn_DEBUG1_LOCK                             25
+#define BM_APBH_CHn_DEBUG1_LOCK                             0x2000000
+#define BF_APBH_CHn_DEBUG1_LOCK(v)                          (((v) & 0x1) << 25)
+#define BFM_APBH_CHn_DEBUG1_LOCK(v)                         BM_APBH_CHn_DEBUG1_LOCK
+#define BF_APBH_CHn_DEBUG1_LOCK_V(e)                        BF_APBH_CHn_DEBUG1_LOCK(BV_APBH_CHn_DEBUG1_LOCK__##e)
+#define BFM_APBH_CHn_DEBUG1_LOCK_V(v)                       BM_APBH_CHn_DEBUG1_LOCK
+#define BP_APBH_CHn_DEBUG1_NEXTCMDADDRVALID                 24
+#define BM_APBH_CHn_DEBUG1_NEXTCMDADDRVALID                 0x1000000
+#define BF_APBH_CHn_DEBUG1_NEXTCMDADDRVALID(v)              (((v) & 0x1) << 24)
+#define BFM_APBH_CHn_DEBUG1_NEXTCMDADDRVALID(v)             BM_APBH_CHn_DEBUG1_NEXTCMDADDRVALID
+#define BF_APBH_CHn_DEBUG1_NEXTCMDADDRVALID_V(e)            BF_APBH_CHn_DEBUG1_NEXTCMDADDRVALID(BV_APBH_CHn_DEBUG1_NEXTCMDADDRVALID__##e)
+#define BFM_APBH_CHn_DEBUG1_NEXTCMDADDRVALID_V(v)           BM_APBH_CHn_DEBUG1_NEXTCMDADDRVALID
+#define BP_APBH_CHn_DEBUG1_RD_FIFO_EMPTY                    23
+#define BM_APBH_CHn_DEBUG1_RD_FIFO_EMPTY                    0x800000
+#define BF_APBH_CHn_DEBUG1_RD_FIFO_EMPTY(v)                 (((v) & 0x1) << 23)
+#define BFM_APBH_CHn_DEBUG1_RD_FIFO_EMPTY(v)                BM_APBH_CHn_DEBUG1_RD_FIFO_EMPTY
+#define BF_APBH_CHn_DEBUG1_RD_FIFO_EMPTY_V(e)               BF_APBH_CHn_DEBUG1_RD_FIFO_EMPTY(BV_APBH_CHn_DEBUG1_RD_FIFO_EMPTY__##e)
+#define BFM_APBH_CHn_DEBUG1_RD_FIFO_EMPTY_V(v)              BM_APBH_CHn_DEBUG1_RD_FIFO_EMPTY
+#define BP_APBH_CHn_DEBUG1_RD_FIFO_FULL                     22
+#define BM_APBH_CHn_DEBUG1_RD_FIFO_FULL                     0x400000
+#define BF_APBH_CHn_DEBUG1_RD_FIFO_FULL(v)                  (((v) & 0x1) << 22)
+#define BFM_APBH_CHn_DEBUG1_RD_FIFO_FULL(v)                 BM_APBH_CHn_DEBUG1_RD_FIFO_FULL
+#define BF_APBH_CHn_DEBUG1_RD_FIFO_FULL_V(e)                BF_APBH_CHn_DEBUG1_RD_FIFO_FULL(BV_APBH_CHn_DEBUG1_RD_FIFO_FULL__##e)
+#define BFM_APBH_CHn_DEBUG1_RD_FIFO_FULL_V(v)               BM_APBH_CHn_DEBUG1_RD_FIFO_FULL
+#define BP_APBH_CHn_DEBUG1_WR_FIFO_EMPTY                    21
+#define BM_APBH_CHn_DEBUG1_WR_FIFO_EMPTY                    0x200000
+#define BF_APBH_CHn_DEBUG1_WR_FIFO_EMPTY(v)                 (((v) & 0x1) << 21)
+#define BFM_APBH_CHn_DEBUG1_WR_FIFO_EMPTY(v)                BM_APBH_CHn_DEBUG1_WR_FIFO_EMPTY
+#define BF_APBH_CHn_DEBUG1_WR_FIFO_EMPTY_V(e)               BF_APBH_CHn_DEBUG1_WR_FIFO_EMPTY(BV_APBH_CHn_DEBUG1_WR_FIFO_EMPTY__##e)
+#define BFM_APBH_CHn_DEBUG1_WR_FIFO_EMPTY_V(v)              BM_APBH_CHn_DEBUG1_WR_FIFO_EMPTY
+#define BP_APBH_CHn_DEBUG1_WR_FIFO_FULL                     20
+#define BM_APBH_CHn_DEBUG1_WR_FIFO_FULL                     0x100000
+#define BF_APBH_CHn_DEBUG1_WR_FIFO_FULL(v)                  (((v) & 0x1) << 20)
+#define BFM_APBH_CHn_DEBUG1_WR_FIFO_FULL(v)                 BM_APBH_CHn_DEBUG1_WR_FIFO_FULL
+#define BF_APBH_CHn_DEBUG1_WR_FIFO_FULL_V(e)                BF_APBH_CHn_DEBUG1_WR_FIFO_FULL(BV_APBH_CHn_DEBUG1_WR_FIFO_FULL__##e)
+#define BFM_APBH_CHn_DEBUG1_WR_FIFO_FULL_V(v)               BM_APBH_CHn_DEBUG1_WR_FIFO_FULL
+#define BP_APBH_CHn_DEBUG1_RSVD1                            5
+#define BM_APBH_CHn_DEBUG1_RSVD1                            0xfffe0
+#define BF_APBH_CHn_DEBUG1_RSVD1(v)                         (((v) & 0x7fff) << 5)
+#define BFM_APBH_CHn_DEBUG1_RSVD1(v)                        BM_APBH_CHn_DEBUG1_RSVD1
+#define BF_APBH_CHn_DEBUG1_RSVD1_V(e)                       BF_APBH_CHn_DEBUG1_RSVD1(BV_APBH_CHn_DEBUG1_RSVD1__##e)
+#define BFM_APBH_CHn_DEBUG1_RSVD1_V(v)                      BM_APBH_CHn_DEBUG1_RSVD1
+#define BP_APBH_CHn_DEBUG1_STATEMACHINE                     0
+#define BM_APBH_CHn_DEBUG1_STATEMACHINE                     0x1f
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__IDLE               0x0
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD1           0x1
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD3           0x2
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD2           0x3
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__XFER_DECODE        0x4
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_WAIT           0x5
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD4           0x6
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__PIO_REQ            0x7
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_FLUSH         0x8
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_WAIT          0x9
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__WRITE              0xc
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_REQ           0xd
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__CHECK_CHAIN        0xe
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__XFER_COMPLETE      0xf
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__TERMINATE          0x14
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__WAIT_END           0x15
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__WRITE_WAIT         0x1c
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__HALT_AFTER_TERM    0x1d
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__CHECK_WAIT         0x1e
+#define BF_APBH_CHn_DEBUG1_STATEMACHINE(v)                  (((v) & 0x1f) << 0)
+#define BFM_APBH_CHn_DEBUG1_STATEMACHINE(v)                 BM_APBH_CHn_DEBUG1_STATEMACHINE
+#define BF_APBH_CHn_DEBUG1_STATEMACHINE_V(e)                BF_APBH_CHn_DEBUG1_STATEMACHINE(BV_APBH_CHn_DEBUG1_STATEMACHINE__##e)
+#define BFM_APBH_CHn_DEBUG1_STATEMACHINE_V(v)               BM_APBH_CHn_DEBUG1_STATEMACHINE
+
+#define HW_APBH_CHn_DEBUG2(_n1)             HW(APBH_CHn_DEBUG2(_n1))
+#define HWA_APBH_CHn_DEBUG2(_n1)            (0x80004000 + 0xa0 + (_n1) * 0x70)
+#define HWT_APBH_CHn_DEBUG2(_n1)            HWIO_32_RW
+#define HWN_APBH_CHn_DEBUG2(_n1)            APBH_CHn_DEBUG2
+#define HWI_APBH_CHn_DEBUG2(_n1)            (_n1)
+#define BP_APBH_CHn_DEBUG2_APB_BYTES        16
+#define BM_APBH_CHn_DEBUG2_APB_BYTES        0xffff0000
+#define BF_APBH_CHn_DEBUG2_APB_BYTES(v)     (((v) & 0xffff) << 16)
+#define BFM_APBH_CHn_DEBUG2_APB_BYTES(v)    BM_APBH_CHn_DEBUG2_APB_BYTES
+#define BF_APBH_CHn_DEBUG2_APB_BYTES_V(e)   BF_APBH_CHn_DEBUG2_APB_BYTES(BV_APBH_CHn_DEBUG2_APB_BYTES__##e)
+#define BFM_APBH_CHn_DEBUG2_APB_BYTES_V(v)  BM_APBH_CHn_DEBUG2_APB_BYTES
+#define BP_APBH_CHn_DEBUG2_AHB_BYTES        0
+#define BM_APBH_CHn_DEBUG2_AHB_BYTES        0xffff
+#define BF_APBH_CHn_DEBUG2_AHB_BYTES(v)     (((v) & 0xffff) << 0)
+#define BFM_APBH_CHn_DEBUG2_AHB_BYTES(v)    BM_APBH_CHn_DEBUG2_AHB_BYTES
+#define BF_APBH_CHn_DEBUG2_AHB_BYTES_V(e)   BF_APBH_CHn_DEBUG2_AHB_BYTES(BV_APBH_CHn_DEBUG2_AHB_BYTES__##e)
+#define BFM_APBH_CHn_DEBUG2_AHB_BYTES_V(v)  BM_APBH_CHn_DEBUG2_AHB_BYTES
+
+#define HW_APBH_VERSION             HW(APBH_VERSION)
+#define HWA_APBH_VERSION            (0x80004000 + 0x3f0)
+#define HWT_APBH_VERSION            HWIO_32_RW
+#define HWN_APBH_VERSION            APBH_VERSION
+#define HWI_APBH_VERSION            
+#define BP_APBH_VERSION_MAJOR       24
+#define BM_APBH_VERSION_MAJOR       0xff000000
+#define BF_APBH_VERSION_MAJOR(v)    (((v) & 0xff) << 24)
+#define BFM_APBH_VERSION_MAJOR(v)   BM_APBH_VERSION_MAJOR
+#define BF_APBH_VERSION_MAJOR_V(e)  BF_APBH_VERSION_MAJOR(BV_APBH_VERSION_MAJOR__##e)
+#define BFM_APBH_VERSION_MAJOR_V(v) BM_APBH_VERSION_MAJOR
+#define BP_APBH_VERSION_MINOR       16
+#define BM_APBH_VERSION_MINOR       0xff0000
+#define BF_APBH_VERSION_MINOR(v)    (((v) & 0xff) << 16)
+#define BFM_APBH_VERSION_MINOR(v)   BM_APBH_VERSION_MINOR
+#define BF_APBH_VERSION_MINOR_V(e)  BF_APBH_VERSION_MINOR(BV_APBH_VERSION_MINOR__##e)
+#define BFM_APBH_VERSION_MINOR_V(v) BM_APBH_VERSION_MINOR
+#define BP_APBH_VERSION_STEP        0
+#define BM_APBH_VERSION_STEP        0xffff
+#define BF_APBH_VERSION_STEP(v)     (((v) & 0xffff) << 0)
+#define BFM_APBH_VERSION_STEP(v)    BM_APBH_VERSION_STEP
+#define BF_APBH_VERSION_STEP_V(e)   BF_APBH_VERSION_STEP(BV_APBH_VERSION_STEP__##e)
+#define BFM_APBH_VERSION_STEP_V(v)  BM_APBH_VERSION_STEP
+
+#endif /* __HEADERGEN_IMX233_APBH_H__*/
diff --git a/firmware/target/arm/imx233/regs/imx233/apbx.h b/firmware/target/arm/imx233/regs/imx233/apbx.h
new file mode 100644
index 0000000000..c57ece23af
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/imx233/apbx.h
@@ -0,0 +1,569 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * imx233 version: 2.4.0
+ * imx233 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_IMX233_APBX_H__
+#define __HEADERGEN_IMX233_APBX_H__
+
+#define HW_APBX_CTRL0               HW(APBX_CTRL0)
+#define HWA_APBX_CTRL0              (0x80024000 + 0x0)
+#define HWT_APBX_CTRL0              HWIO_32_RW
+#define HWN_APBX_CTRL0              APBX_CTRL0
+#define HWI_APBX_CTRL0              
+#define HW_APBX_CTRL0_SET           HW(APBX_CTRL0_SET)
+#define HWA_APBX_CTRL0_SET          (HWA_APBX_CTRL0 + 0x4)
+#define HWT_APBX_CTRL0_SET          HWIO_32_WO
+#define HWN_APBX_CTRL0_SET          APBX_CTRL0
+#define HWI_APBX_CTRL0_SET          
+#define HW_APBX_CTRL0_CLR           HW(APBX_CTRL0_CLR)
+#define HWA_APBX_CTRL0_CLR          (HWA_APBX_CTRL0 + 0x8)
+#define HWT_APBX_CTRL0_CLR          HWIO_32_WO
+#define HWN_APBX_CTRL0_CLR          APBX_CTRL0
+#define HWI_APBX_CTRL0_CLR          
+#define HW_APBX_CTRL0_TOG           HW(APBX_CTRL0_TOG)
+#define HWA_APBX_CTRL0_TOG          (HWA_APBX_CTRL0 + 0xc)
+#define HWT_APBX_CTRL0_TOG          HWIO_32_WO
+#define HWN_APBX_CTRL0_TOG          APBX_CTRL0
+#define HWI_APBX_CTRL0_TOG          
+#define BP_APBX_CTRL0_SFTRST        31
+#define BM_APBX_CTRL0_SFTRST        0x80000000
+#define BF_APBX_CTRL0_SFTRST(v)     (((v) & 0x1) << 31)
+#define BFM_APBX_CTRL0_SFTRST(v)    BM_APBX_CTRL0_SFTRST
+#define BF_APBX_CTRL0_SFTRST_V(e)   BF_APBX_CTRL0_SFTRST(BV_APBX_CTRL0_SFTRST__##e)
+#define BFM_APBX_CTRL0_SFTRST_V(v)  BM_APBX_CTRL0_SFTRST
+#define BP_APBX_CTRL0_CLKGATE       30
+#define BM_APBX_CTRL0_CLKGATE       0x40000000
+#define BF_APBX_CTRL0_CLKGATE(v)    (((v) & 0x1) << 30)
+#define BFM_APBX_CTRL0_CLKGATE(v)   BM_APBX_CTRL0_CLKGATE
+#define BF_APBX_CTRL0_CLKGATE_V(e)  BF_APBX_CTRL0_CLKGATE(BV_APBX_CTRL0_CLKGATE__##e)
+#define BFM_APBX_CTRL0_CLKGATE_V(v) BM_APBX_CTRL0_CLKGATE
+#define BP_APBX_CTRL0_RSVD0         0
+#define BM_APBX_CTRL0_RSVD0         0x3fffffff
+#define BF_APBX_CTRL0_RSVD0(v)      (((v) & 0x3fffffff) << 0)
+#define BFM_APBX_CTRL0_RSVD0(v)     BM_APBX_CTRL0_RSVD0
+#define BF_APBX_CTRL0_RSVD0_V(e)    BF_APBX_CTRL0_RSVD0(BV_APBX_CTRL0_RSVD0__##e)
+#define BFM_APBX_CTRL0_RSVD0_V(v)   BM_APBX_CTRL0_RSVD0
+
+#define HW_APBX_CTRL1                           HW(APBX_CTRL1)
+#define HWA_APBX_CTRL1                          (0x80024000 + 0x10)
+#define HWT_APBX_CTRL1                          HWIO_32_RW
+#define HWN_APBX_CTRL1                          APBX_CTRL1
+#define HWI_APBX_CTRL1                          
+#define HW_APBX_CTRL1_SET                       HW(APBX_CTRL1_SET)
+#define HWA_APBX_CTRL1_SET                      (HWA_APBX_CTRL1 + 0x4)
+#define HWT_APBX_CTRL1_SET                      HWIO_32_WO
+#define HWN_APBX_CTRL1_SET                      APBX_CTRL1
+#define HWI_APBX_CTRL1_SET                      
+#define HW_APBX_CTRL1_CLR                       HW(APBX_CTRL1_CLR)
+#define HWA_APBX_CTRL1_CLR                      (HWA_APBX_CTRL1 + 0x8)
+#define HWT_APBX_CTRL1_CLR                      HWIO_32_WO
+#define HWN_APBX_CTRL1_CLR                      APBX_CTRL1
+#define HWI_APBX_CTRL1_CLR                      
+#define HW_APBX_CTRL1_TOG                       HW(APBX_CTRL1_TOG)
+#define HWA_APBX_CTRL1_TOG                      (HWA_APBX_CTRL1 + 0xc)
+#define HWT_APBX_CTRL1_TOG                      HWIO_32_WO
+#define HWN_APBX_CTRL1_TOG                      APBX_CTRL1
+#define HWI_APBX_CTRL1_TOG                      
+#define BP_APBX_CTRL1_CH_CMDCMPLT_IRQ_EN        16
+#define BM_APBX_CTRL1_CH_CMDCMPLT_IRQ_EN        0xffff0000
+#define BF_APBX_CTRL1_CH_CMDCMPLT_IRQ_EN(v)     (((v) & 0xffff) << 16)
+#define BFM_APBX_CTRL1_CH_CMDCMPLT_IRQ_EN(v)    BM_APBX_CTRL1_CH_CMDCMPLT_IRQ_EN
+#define BF_APBX_CTRL1_CH_CMDCMPLT_IRQ_EN_V(e)   BF_APBX_CTRL1_CH_CMDCMPLT_IRQ_EN(BV_APBX_CTRL1_CH_CMDCMPLT_IRQ_EN__##e)
+#define BFM_APBX_CTRL1_CH_CMDCMPLT_IRQ_EN_V(v)  BM_APBX_CTRL1_CH_CMDCMPLT_IRQ_EN
+#define BP_APBX_CTRL1_CH_CMDCMPLT_IRQ           0
+#define BM_APBX_CTRL1_CH_CMDCMPLT_IRQ           0xffff
+#define BF_APBX_CTRL1_CH_CMDCMPLT_IRQ(v)        (((v) & 0xffff) << 0)
+#define BFM_APBX_CTRL1_CH_CMDCMPLT_IRQ(v)       BM_APBX_CTRL1_CH_CMDCMPLT_IRQ
+#define BF_APBX_CTRL1_CH_CMDCMPLT_IRQ_V(e)      BF_APBX_CTRL1_CH_CMDCMPLT_IRQ(BV_APBX_CTRL1_CH_CMDCMPLT_IRQ__##e)
+#define BFM_APBX_CTRL1_CH_CMDCMPLT_IRQ_V(v)     BM_APBX_CTRL1_CH_CMDCMPLT_IRQ
+
+#define HW_APBX_CTRL2                       HW(APBX_CTRL2)
+#define HWA_APBX_CTRL2                      (0x80024000 + 0x20)
+#define HWT_APBX_CTRL2                      HWIO_32_RW
+#define HWN_APBX_CTRL2                      APBX_CTRL2
+#define HWI_APBX_CTRL2                      
+#define HW_APBX_CTRL2_SET                   HW(APBX_CTRL2_SET)
+#define HWA_APBX_CTRL2_SET                  (HWA_APBX_CTRL2 + 0x4)
+#define HWT_APBX_CTRL2_SET                  HWIO_32_WO
+#define HWN_APBX_CTRL2_SET                  APBX_CTRL2
+#define HWI_APBX_CTRL2_SET                  
+#define HW_APBX_CTRL2_CLR                   HW(APBX_CTRL2_CLR)
+#define HWA_APBX_CTRL2_CLR                  (HWA_APBX_CTRL2 + 0x8)
+#define HWT_APBX_CTRL2_CLR                  HWIO_32_WO
+#define HWN_APBX_CTRL2_CLR                  APBX_CTRL2
+#define HWI_APBX_CTRL2_CLR                  
+#define HW_APBX_CTRL2_TOG                   HW(APBX_CTRL2_TOG)
+#define HWA_APBX_CTRL2_TOG                  (HWA_APBX_CTRL2 + 0xc)
+#define HWT_APBX_CTRL2_TOG                  HWIO_32_WO
+#define HWN_APBX_CTRL2_TOG                  APBX_CTRL2
+#define HWI_APBX_CTRL2_TOG                  
+#define BP_APBX_CTRL2_CH_ERROR_STATUS       16
+#define BM_APBX_CTRL2_CH_ERROR_STATUS       0xffff0000
+#define BF_APBX_CTRL2_CH_ERROR_STATUS(v)    (((v) & 0xffff) << 16)
+#define BFM_APBX_CTRL2_CH_ERROR_STATUS(v)   BM_APBX_CTRL2_CH_ERROR_STATUS
+#define BF_APBX_CTRL2_CH_ERROR_STATUS_V(e)  BF_APBX_CTRL2_CH_ERROR_STATUS(BV_APBX_CTRL2_CH_ERROR_STATUS__##e)
+#define BFM_APBX_CTRL2_CH_ERROR_STATUS_V(v) BM_APBX_CTRL2_CH_ERROR_STATUS
+#define BP_APBX_CTRL2_CH_ERROR_IRQ          0
+#define BM_APBX_CTRL2_CH_ERROR_IRQ          0xffff
+#define BF_APBX_CTRL2_CH_ERROR_IRQ(v)       (((v) & 0xffff) << 0)
+#define BFM_APBX_CTRL2_CH_ERROR_IRQ(v)      BM_APBX_CTRL2_CH_ERROR_IRQ
+#define BF_APBX_CTRL2_CH_ERROR_IRQ_V(e)     BF_APBX_CTRL2_CH_ERROR_IRQ(BV_APBX_CTRL2_CH_ERROR_IRQ__##e)
+#define BFM_APBX_CTRL2_CH_ERROR_IRQ_V(v)    BM_APBX_CTRL2_CH_ERROR_IRQ
+
+#define HW_APBX_CHANNEL_CTRL                            HW(APBX_CHANNEL_CTRL)
+#define HWA_APBX_CHANNEL_CTRL                           (0x80024000 + 0x30)
+#define HWT_APBX_CHANNEL_CTRL                           HWIO_32_RW
+#define HWN_APBX_CHANNEL_CTRL                           APBX_CHANNEL_CTRL
+#define HWI_APBX_CHANNEL_CTRL                           
+#define HW_APBX_CHANNEL_CTRL_SET                        HW(APBX_CHANNEL_CTRL_SET)
+#define HWA_APBX_CHANNEL_CTRL_SET                       (HWA_APBX_CHANNEL_CTRL + 0x4)
+#define HWT_APBX_CHANNEL_CTRL_SET                       HWIO_32_WO
+#define HWN_APBX_CHANNEL_CTRL_SET                       APBX_CHANNEL_CTRL
+#define HWI_APBX_CHANNEL_CTRL_SET                       
+#define HW_APBX_CHANNEL_CTRL_CLR                        HW(APBX_CHANNEL_CTRL_CLR)
+#define HWA_APBX_CHANNEL_CTRL_CLR                       (HWA_APBX_CHANNEL_CTRL + 0x8)
+#define HWT_APBX_CHANNEL_CTRL_CLR                       HWIO_32_WO
+#define HWN_APBX_CHANNEL_CTRL_CLR                       APBX_CHANNEL_CTRL
+#define HWI_APBX_CHANNEL_CTRL_CLR                       
+#define HW_APBX_CHANNEL_CTRL_TOG                        HW(APBX_CHANNEL_CTRL_TOG)
+#define HWA_APBX_CHANNEL_CTRL_TOG                       (HWA_APBX_CHANNEL_CTRL + 0xc)
+#define HWT_APBX_CHANNEL_CTRL_TOG                       HWIO_32_WO
+#define HWN_APBX_CHANNEL_CTRL_TOG                       APBX_CHANNEL_CTRL
+#define HWI_APBX_CHANNEL_CTRL_TOG                       
+#define BP_APBX_CHANNEL_CTRL_RESET_CHANNEL              16
+#define BM_APBX_CHANNEL_CTRL_RESET_CHANNEL              0xffff0000
+#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__AUDIOIN     0x1
+#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__AUDIOOUT    0x2
+#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__SPDIF_TX    0x4
+#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__I2C         0x8
+#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__SAIF1       0x10
+#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__DRI         0x20
+#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__IRDA_RX     0x40
+#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__UART0_RX    0x40
+#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__IRDA_TX     0x80
+#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__UART0_TX    0x80
+#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__UART1_RX    0x100
+#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__UART1_TX    0x200
+#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__SAIF2       0x400
+#define BF_APBX_CHANNEL_CTRL_RESET_CHANNEL(v)           (((v) & 0xffff) << 16)
+#define BFM_APBX_CHANNEL_CTRL_RESET_CHANNEL(v)          BM_APBX_CHANNEL_CTRL_RESET_CHANNEL
+#define BF_APBX_CHANNEL_CTRL_RESET_CHANNEL_V(e)         BF_APBX_CHANNEL_CTRL_RESET_CHANNEL(BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__##e)
+#define BFM_APBX_CHANNEL_CTRL_RESET_CHANNEL_V(v)        BM_APBX_CHANNEL_CTRL_RESET_CHANNEL
+#define BP_APBX_CHANNEL_CTRL_FREEZE_CHANNEL             0
+#define BM_APBX_CHANNEL_CTRL_FREEZE_CHANNEL             0xffff
+#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__AUDIOIN    0x1
+#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__AUDIOOUT   0x2
+#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__SPDIF_TX   0x4
+#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__I2C        0x8
+#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__SAIF1      0x10
+#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__DRI        0x20
+#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__IRDA_RX    0x40
+#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__UART0_RX   0x40
+#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__IRDA_TX    0x80
+#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__UART0_TX   0x80
+#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__UART1_RX   0x100
+#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__UART1_TX   0x200
+#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__SAIF2      0x400
+#define BF_APBX_CHANNEL_CTRL_FREEZE_CHANNEL(v)          (((v) & 0xffff) << 0)
+#define BFM_APBX_CHANNEL_CTRL_FREEZE_CHANNEL(v)         BM_APBX_CHANNEL_CTRL_FREEZE_CHANNEL
+#define BF_APBX_CHANNEL_CTRL_FREEZE_CHANNEL_V(e)        BF_APBX_CHANNEL_CTRL_FREEZE_CHANNEL(BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__##e)
+#define BFM_APBX_CHANNEL_CTRL_FREEZE_CHANNEL_V(v)       BM_APBX_CHANNEL_CTRL_FREEZE_CHANNEL
+
+#define HW_APBX_DEVSEL                  HW(APBX_DEVSEL)
+#define HWA_APBX_DEVSEL                 (0x80024000 + 0x40)
+#define HWT_APBX_DEVSEL                 HWIO_32_RW
+#define HWN_APBX_DEVSEL                 APBX_DEVSEL
+#define HWI_APBX_DEVSEL                 
+#define BP_APBX_DEVSEL_CH15             30
+#define BM_APBX_DEVSEL_CH15             0xc0000000
+#define BF_APBX_DEVSEL_CH15(v)          (((v) & 0x3) << 30)
+#define BFM_APBX_DEVSEL_CH15(v)         BM_APBX_DEVSEL_CH15
+#define BF_APBX_DEVSEL_CH15_V(e)        BF_APBX_DEVSEL_CH15(BV_APBX_DEVSEL_CH15__##e)
+#define BFM_APBX_DEVSEL_CH15_V(v)       BM_APBX_DEVSEL_CH15
+#define BP_APBX_DEVSEL_CH14             28
+#define BM_APBX_DEVSEL_CH14             0x30000000
+#define BF_APBX_DEVSEL_CH14(v)          (((v) & 0x3) << 28)
+#define BFM_APBX_DEVSEL_CH14(v)         BM_APBX_DEVSEL_CH14
+#define BF_APBX_DEVSEL_CH14_V(e)        BF_APBX_DEVSEL_CH14(BV_APBX_DEVSEL_CH14__##e)
+#define BFM_APBX_DEVSEL_CH14_V(v)       BM_APBX_DEVSEL_CH14
+#define BP_APBX_DEVSEL_CH13             26
+#define BM_APBX_DEVSEL_CH13             0xc000000
+#define BF_APBX_DEVSEL_CH13(v)          (((v) & 0x3) << 26)
+#define BFM_APBX_DEVSEL_CH13(v)         BM_APBX_DEVSEL_CH13
+#define BF_APBX_DEVSEL_CH13_V(e)        BF_APBX_DEVSEL_CH13(BV_APBX_DEVSEL_CH13__##e)
+#define BFM_APBX_DEVSEL_CH13_V(v)       BM_APBX_DEVSEL_CH13
+#define BP_APBX_DEVSEL_CH12             24
+#define BM_APBX_DEVSEL_CH12             0x3000000
+#define BF_APBX_DEVSEL_CH12(v)          (((v) & 0x3) << 24)
+#define BFM_APBX_DEVSEL_CH12(v)         BM_APBX_DEVSEL_CH12
+#define BF_APBX_DEVSEL_CH12_V(e)        BF_APBX_DEVSEL_CH12(BV_APBX_DEVSEL_CH12__##e)
+#define BFM_APBX_DEVSEL_CH12_V(v)       BM_APBX_DEVSEL_CH12
+#define BP_APBX_DEVSEL_CH11             22
+#define BM_APBX_DEVSEL_CH11             0xc00000
+#define BF_APBX_DEVSEL_CH11(v)          (((v) & 0x3) << 22)
+#define BFM_APBX_DEVSEL_CH11(v)         BM_APBX_DEVSEL_CH11
+#define BF_APBX_DEVSEL_CH11_V(e)        BF_APBX_DEVSEL_CH11(BV_APBX_DEVSEL_CH11__##e)
+#define BFM_APBX_DEVSEL_CH11_V(v)       BM_APBX_DEVSEL_CH11
+#define BP_APBX_DEVSEL_CH10             20
+#define BM_APBX_DEVSEL_CH10             0x300000
+#define BF_APBX_DEVSEL_CH10(v)          (((v) & 0x3) << 20)
+#define BFM_APBX_DEVSEL_CH10(v)         BM_APBX_DEVSEL_CH10
+#define BF_APBX_DEVSEL_CH10_V(e)        BF_APBX_DEVSEL_CH10(BV_APBX_DEVSEL_CH10__##e)
+#define BFM_APBX_DEVSEL_CH10_V(v)       BM_APBX_DEVSEL_CH10
+#define BP_APBX_DEVSEL_CH9              18
+#define BM_APBX_DEVSEL_CH9              0xc0000
+#define BF_APBX_DEVSEL_CH9(v)           (((v) & 0x3) << 18)
+#define BFM_APBX_DEVSEL_CH9(v)          BM_APBX_DEVSEL_CH9
+#define BF_APBX_DEVSEL_CH9_V(e)         BF_APBX_DEVSEL_CH9(BV_APBX_DEVSEL_CH9__##e)
+#define BFM_APBX_DEVSEL_CH9_V(v)        BM_APBX_DEVSEL_CH9
+#define BP_APBX_DEVSEL_CH8              16
+#define BM_APBX_DEVSEL_CH8              0x30000
+#define BF_APBX_DEVSEL_CH8(v)           (((v) & 0x3) << 16)
+#define BFM_APBX_DEVSEL_CH8(v)          BM_APBX_DEVSEL_CH8
+#define BF_APBX_DEVSEL_CH8_V(e)         BF_APBX_DEVSEL_CH8(BV_APBX_DEVSEL_CH8__##e)
+#define BFM_APBX_DEVSEL_CH8_V(v)        BM_APBX_DEVSEL_CH8
+#define BP_APBX_DEVSEL_CH7              14
+#define BM_APBX_DEVSEL_CH7              0xc000
+#define BV_APBX_DEVSEL_CH7__USE_I2C1    0x0
+#define BV_APBX_DEVSEL_CH7__USE_IRDA    0x1
+#define BF_APBX_DEVSEL_CH7(v)           (((v) & 0x3) << 14)
+#define BFM_APBX_DEVSEL_CH7(v)          BM_APBX_DEVSEL_CH7
+#define BF_APBX_DEVSEL_CH7_V(e)         BF_APBX_DEVSEL_CH7(BV_APBX_DEVSEL_CH7__##e)
+#define BFM_APBX_DEVSEL_CH7_V(v)        BM_APBX_DEVSEL_CH7
+#define BP_APBX_DEVSEL_CH6              12
+#define BM_APBX_DEVSEL_CH6              0x3000
+#define BV_APBX_DEVSEL_CH6__USE_SAIF1   0x0
+#define BV_APBX_DEVSEL_CH6__USE_IRDA    0x1
+#define BF_APBX_DEVSEL_CH6(v)           (((v) & 0x3) << 12)
+#define BFM_APBX_DEVSEL_CH6(v)          BM_APBX_DEVSEL_CH6
+#define BF_APBX_DEVSEL_CH6_V(e)         BF_APBX_DEVSEL_CH6(BV_APBX_DEVSEL_CH6__##e)
+#define BFM_APBX_DEVSEL_CH6_V(v)        BM_APBX_DEVSEL_CH6
+#define BP_APBX_DEVSEL_CH5              10
+#define BM_APBX_DEVSEL_CH5              0xc00
+#define BF_APBX_DEVSEL_CH5(v)           (((v) & 0x3) << 10)
+#define BFM_APBX_DEVSEL_CH5(v)          BM_APBX_DEVSEL_CH5
+#define BF_APBX_DEVSEL_CH5_V(e)         BF_APBX_DEVSEL_CH5(BV_APBX_DEVSEL_CH5__##e)
+#define BFM_APBX_DEVSEL_CH5_V(v)        BM_APBX_DEVSEL_CH5
+#define BP_APBX_DEVSEL_CH4              8
+#define BM_APBX_DEVSEL_CH4              0x300
+#define BF_APBX_DEVSEL_CH4(v)           (((v) & 0x3) << 8)
+#define BFM_APBX_DEVSEL_CH4(v)          BM_APBX_DEVSEL_CH4
+#define BF_APBX_DEVSEL_CH4_V(e)         BF_APBX_DEVSEL_CH4(BV_APBX_DEVSEL_CH4__##e)
+#define BFM_APBX_DEVSEL_CH4_V(v)        BM_APBX_DEVSEL_CH4
+#define BP_APBX_DEVSEL_CH3              6
+#define BM_APBX_DEVSEL_CH3              0xc0
+#define BF_APBX_DEVSEL_CH3(v)           (((v) & 0x3) << 6)
+#define BFM_APBX_DEVSEL_CH3(v)          BM_APBX_DEVSEL_CH3
+#define BF_APBX_DEVSEL_CH3_V(e)         BF_APBX_DEVSEL_CH3(BV_APBX_DEVSEL_CH3__##e)
+#define BFM_APBX_DEVSEL_CH3_V(v)        BM_APBX_DEVSEL_CH3
+#define BP_APBX_DEVSEL_CH2              4
+#define BM_APBX_DEVSEL_CH2              0x30
+#define BF_APBX_DEVSEL_CH2(v)           (((v) & 0x3) << 4)
+#define BFM_APBX_DEVSEL_CH2(v)          BM_APBX_DEVSEL_CH2
+#define BF_APBX_DEVSEL_CH2_V(e)         BF_APBX_DEVSEL_CH2(BV_APBX_DEVSEL_CH2__##e)
+#define BFM_APBX_DEVSEL_CH2_V(v)        BM_APBX_DEVSEL_CH2
+#define BP_APBX_DEVSEL_CH1              2
+#define BM_APBX_DEVSEL_CH1              0xc
+#define BF_APBX_DEVSEL_CH1(v)           (((v) & 0x3) << 2)
+#define BFM_APBX_DEVSEL_CH1(v)          BM_APBX_DEVSEL_CH1
+#define BF_APBX_DEVSEL_CH1_V(e)         BF_APBX_DEVSEL_CH1(BV_APBX_DEVSEL_CH1__##e)
+#define BFM_APBX_DEVSEL_CH1_V(v)        BM_APBX_DEVSEL_CH1
+#define BP_APBX_DEVSEL_CH0              0
+#define BM_APBX_DEVSEL_CH0              0x3
+#define BF_APBX_DEVSEL_CH0(v)           (((v) & 0x3) << 0)
+#define BFM_APBX_DEVSEL_CH0(v)          BM_APBX_DEVSEL_CH0
+#define BF_APBX_DEVSEL_CH0_V(e)         BF_APBX_DEVSEL_CH0(BV_APBX_DEVSEL_CH0__##e)
+#define BFM_APBX_DEVSEL_CH0_V(v)        BM_APBX_DEVSEL_CH0
+
+#define HW_APBX_CHn_CURCMDAR(_n1)           HW(APBX_CHn_CURCMDAR(_n1))
+#define HWA_APBX_CHn_CURCMDAR(_n1)          (0x80024000 + 0x100 + (_n1) * 0x70)
+#define HWT_APBX_CHn_CURCMDAR(_n1)          HWIO_32_RW
+#define HWN_APBX_CHn_CURCMDAR(_n1)          APBX_CHn_CURCMDAR
+#define HWI_APBX_CHn_CURCMDAR(_n1)          (_n1)
+#define BP_APBX_CHn_CURCMDAR_CMD_ADDR       0
+#define BM_APBX_CHn_CURCMDAR_CMD_ADDR       0xffffffff
+#define BF_APBX_CHn_CURCMDAR_CMD_ADDR(v)    (((v) & 0xffffffff) << 0)
+#define BFM_APBX_CHn_CURCMDAR_CMD_ADDR(v)   BM_APBX_CHn_CURCMDAR_CMD_ADDR
+#define BF_APBX_CHn_CURCMDAR_CMD_ADDR_V(e)  BF_APBX_CHn_CURCMDAR_CMD_ADDR(BV_APBX_CHn_CURCMDAR_CMD_ADDR__##e)
+#define BFM_APBX_CHn_CURCMDAR_CMD_ADDR_V(v) BM_APBX_CHn_CURCMDAR_CMD_ADDR
+
+#define HW_APBX_CHn_NXTCMDAR(_n1)           HW(APBX_CHn_NXTCMDAR(_n1))
+#define HWA_APBX_CHn_NXTCMDAR(_n1)          (0x80024000 + 0x110 + (_n1) * 0x70)
+#define HWT_APBX_CHn_NXTCMDAR(_n1)          HWIO_32_RW
+#define HWN_APBX_CHn_NXTCMDAR(_n1)          APBX_CHn_NXTCMDAR
+#define HWI_APBX_CHn_NXTCMDAR(_n1)          (_n1)
+#define BP_APBX_CHn_NXTCMDAR_CMD_ADDR       0
+#define BM_APBX_CHn_NXTCMDAR_CMD_ADDR       0xffffffff
+#define BF_APBX_CHn_NXTCMDAR_CMD_ADDR(v)    (((v) & 0xffffffff) << 0)
+#define BFM_APBX_CHn_NXTCMDAR_CMD_ADDR(v)   BM_APBX_CHn_NXTCMDAR_CMD_ADDR
+#define BF_APBX_CHn_NXTCMDAR_CMD_ADDR_V(e)  BF_APBX_CHn_NXTCMDAR_CMD_ADDR(BV_APBX_CHn_NXTCMDAR_CMD_ADDR__##e)
+#define BFM_APBX_CHn_NXTCMDAR_CMD_ADDR_V(v) BM_APBX_CHn_NXTCMDAR_CMD_ADDR
+
+#define HW_APBX_CHn_CMD(_n1)                    HW(APBX_CHn_CMD(_n1))
+#define HWA_APBX_CHn_CMD(_n1)                   (0x80024000 + 0x120 + (_n1) * 0x70)
+#define HWT_APBX_CHn_CMD(_n1)                   HWIO_32_RW
+#define HWN_APBX_CHn_CMD(_n1)                   APBX_CHn_CMD
+#define HWI_APBX_CHn_CMD(_n1)                   (_n1)
+#define BP_APBX_CHn_CMD_XFER_COUNT              16
+#define BM_APBX_CHn_CMD_XFER_COUNT              0xffff0000
+#define BF_APBX_CHn_CMD_XFER_COUNT(v)           (((v) & 0xffff) << 16)
+#define BFM_APBX_CHn_CMD_XFER_COUNT(v)          BM_APBX_CHn_CMD_XFER_COUNT
+#define BF_APBX_CHn_CMD_XFER_COUNT_V(e)         BF_APBX_CHn_CMD_XFER_COUNT(BV_APBX_CHn_CMD_XFER_COUNT__##e)
+#define BFM_APBX_CHn_CMD_XFER_COUNT_V(v)        BM_APBX_CHn_CMD_XFER_COUNT
+#define BP_APBX_CHn_CMD_CMDWORDS                12
+#define BM_APBX_CHn_CMD_CMDWORDS                0xf000
+#define BF_APBX_CHn_CMD_CMDWORDS(v)             (((v) & 0xf) << 12)
+#define BFM_APBX_CHn_CMD_CMDWORDS(v)            BM_APBX_CHn_CMD_CMDWORDS
+#define BF_APBX_CHn_CMD_CMDWORDS_V(e)           BF_APBX_CHn_CMD_CMDWORDS(BV_APBX_CHn_CMD_CMDWORDS__##e)
+#define BFM_APBX_CHn_CMD_CMDWORDS_V(v)          BM_APBX_CHn_CMD_CMDWORDS
+#define BP_APBX_CHn_CMD_RSVD1                   9
+#define BM_APBX_CHn_CMD_RSVD1                   0xe00
+#define BF_APBX_CHn_CMD_RSVD1(v)                (((v) & 0x7) << 9)
+#define BFM_APBX_CHn_CMD_RSVD1(v)               BM_APBX_CHn_CMD_RSVD1
+#define BF_APBX_CHn_CMD_RSVD1_V(e)              BF_APBX_CHn_CMD_RSVD1(BV_APBX_CHn_CMD_RSVD1__##e)
+#define BFM_APBX_CHn_CMD_RSVD1_V(v)             BM_APBX_CHn_CMD_RSVD1
+#define BP_APBX_CHn_CMD_HALTONTERMINATE         8
+#define BM_APBX_CHn_CMD_HALTONTERMINATE         0x100
+#define BF_APBX_CHn_CMD_HALTONTERMINATE(v)      (((v) & 0x1) << 8)
+#define BFM_APBX_CHn_CMD_HALTONTERMINATE(v)     BM_APBX_CHn_CMD_HALTONTERMINATE
+#define BF_APBX_CHn_CMD_HALTONTERMINATE_V(e)    BF_APBX_CHn_CMD_HALTONTERMINATE(BV_APBX_CHn_CMD_HALTONTERMINATE__##e)
+#define BFM_APBX_CHn_CMD_HALTONTERMINATE_V(v)   BM_APBX_CHn_CMD_HALTONTERMINATE
+#define BP_APBX_CHn_CMD_WAIT4ENDCMD             7
+#define BM_APBX_CHn_CMD_WAIT4ENDCMD             0x80
+#define BF_APBX_CHn_CMD_WAIT4ENDCMD(v)          (((v) & 0x1) << 7)
+#define BFM_APBX_CHn_CMD_WAIT4ENDCMD(v)         BM_APBX_CHn_CMD_WAIT4ENDCMD
+#define BF_APBX_CHn_CMD_WAIT4ENDCMD_V(e)        BF_APBX_CHn_CMD_WAIT4ENDCMD(BV_APBX_CHn_CMD_WAIT4ENDCMD__##e)
+#define BFM_APBX_CHn_CMD_WAIT4ENDCMD_V(v)       BM_APBX_CHn_CMD_WAIT4ENDCMD
+#define BP_APBX_CHn_CMD_SEMAPHORE               6
+#define BM_APBX_CHn_CMD_SEMAPHORE               0x40
+#define BF_APBX_CHn_CMD_SEMAPHORE(v)            (((v) & 0x1) << 6)
+#define BFM_APBX_CHn_CMD_SEMAPHORE(v)           BM_APBX_CHn_CMD_SEMAPHORE
+#define BF_APBX_CHn_CMD_SEMAPHORE_V(e)          BF_APBX_CHn_CMD_SEMAPHORE(BV_APBX_CHn_CMD_SEMAPHORE__##e)
+#define BFM_APBX_CHn_CMD_SEMAPHORE_V(v)         BM_APBX_CHn_CMD_SEMAPHORE
+#define BP_APBX_CHn_CMD_RSVD0                   4
+#define BM_APBX_CHn_CMD_RSVD0                   0x30
+#define BF_APBX_CHn_CMD_RSVD0(v)                (((v) & 0x3) << 4)
+#define BFM_APBX_CHn_CMD_RSVD0(v)               BM_APBX_CHn_CMD_RSVD0
+#define BF_APBX_CHn_CMD_RSVD0_V(e)              BF_APBX_CHn_CMD_RSVD0(BV_APBX_CHn_CMD_RSVD0__##e)
+#define BFM_APBX_CHn_CMD_RSVD0_V(v)             BM_APBX_CHn_CMD_RSVD0
+#define BP_APBX_CHn_CMD_IRQONCMPLT              3
+#define BM_APBX_CHn_CMD_IRQONCMPLT              0x8
+#define BF_APBX_CHn_CMD_IRQONCMPLT(v)           (((v) & 0x1) << 3)
+#define BFM_APBX_CHn_CMD_IRQONCMPLT(v)          BM_APBX_CHn_CMD_IRQONCMPLT
+#define BF_APBX_CHn_CMD_IRQONCMPLT_V(e)         BF_APBX_CHn_CMD_IRQONCMPLT(BV_APBX_CHn_CMD_IRQONCMPLT__##e)
+#define BFM_APBX_CHn_CMD_IRQONCMPLT_V(v)        BM_APBX_CHn_CMD_IRQONCMPLT
+#define BP_APBX_CHn_CMD_CHAIN                   2
+#define BM_APBX_CHn_CMD_CHAIN                   0x4
+#define BF_APBX_CHn_CMD_CHAIN(v)                (((v) & 0x1) << 2)
+#define BFM_APBX_CHn_CMD_CHAIN(v)               BM_APBX_CHn_CMD_CHAIN
+#define BF_APBX_CHn_CMD_CHAIN_V(e)              BF_APBX_CHn_CMD_CHAIN(BV_APBX_CHn_CMD_CHAIN__##e)
+#define BFM_APBX_CHn_CMD_CHAIN_V(v)             BM_APBX_CHn_CMD_CHAIN
+#define BP_APBX_CHn_CMD_COMMAND                 0
+#define BM_APBX_CHn_CMD_COMMAND                 0x3
+#define BV_APBX_CHn_CMD_COMMAND__NO_DMA_XFER    0x0
+#define BV_APBX_CHn_CMD_COMMAND__DMA_WRITE      0x1
+#define BV_APBX_CHn_CMD_COMMAND__DMA_READ       0x2
+#define BF_APBX_CHn_CMD_COMMAND(v)              (((v) & 0x3) << 0)
+#define BFM_APBX_CHn_CMD_COMMAND(v)             BM_APBX_CHn_CMD_COMMAND
+#define BF_APBX_CHn_CMD_COMMAND_V(e)            BF_APBX_CHn_CMD_COMMAND(BV_APBX_CHn_CMD_COMMAND__##e)
+#define BFM_APBX_CHn_CMD_COMMAND_V(v)           BM_APBX_CHn_CMD_COMMAND
+
+#define HW_APBX_CHn_BAR(_n1)            HW(APBX_CHn_BAR(_n1))
+#define HWA_APBX_CHn_BAR(_n1)           (0x80024000 + 0x130 + (_n1) * 0x70)
+#define HWT_APBX_CHn_BAR(_n1)           HWIO_32_RW
+#define HWN_APBX_CHn_BAR(_n1)           APBX_CHn_BAR
+#define HWI_APBX_CHn_BAR(_n1)           (_n1)
+#define BP_APBX_CHn_BAR_ADDRESS         0
+#define BM_APBX_CHn_BAR_ADDRESS         0xffffffff
+#define BF_APBX_CHn_BAR_ADDRESS(v)      (((v) & 0xffffffff) << 0)
+#define BFM_APBX_CHn_BAR_ADDRESS(v)     BM_APBX_CHn_BAR_ADDRESS
+#define BF_APBX_CHn_BAR_ADDRESS_V(e)    BF_APBX_CHn_BAR_ADDRESS(BV_APBX_CHn_BAR_ADDRESS__##e)
+#define BFM_APBX_CHn_BAR_ADDRESS_V(v)   BM_APBX_CHn_BAR_ADDRESS
+
+#define HW_APBX_CHn_SEMA(_n1)                   HW(APBX_CHn_SEMA(_n1))
+#define HWA_APBX_CHn_SEMA(_n1)                  (0x80024000 + 0x140 + (_n1) * 0x70)
+#define HWT_APBX_CHn_SEMA(_n1)                  HWIO_32_RW
+#define HWN_APBX_CHn_SEMA(_n1)                  APBX_CHn_SEMA
+#define HWI_APBX_CHn_SEMA(_n1)                  (_n1)
+#define BP_APBX_CHn_SEMA_RSVD2                  24
+#define BM_APBX_CHn_SEMA_RSVD2                  0xff000000
+#define BF_APBX_CHn_SEMA_RSVD2(v)               (((v) & 0xff) << 24)
+#define BFM_APBX_CHn_SEMA_RSVD2(v)              BM_APBX_CHn_SEMA_RSVD2
+#define BF_APBX_CHn_SEMA_RSVD2_V(e)             BF_APBX_CHn_SEMA_RSVD2(BV_APBX_CHn_SEMA_RSVD2__##e)
+#define BFM_APBX_CHn_SEMA_RSVD2_V(v)            BM_APBX_CHn_SEMA_RSVD2
+#define BP_APBX_CHn_SEMA_PHORE                  16
+#define BM_APBX_CHn_SEMA_PHORE                  0xff0000
+#define BF_APBX_CHn_SEMA_PHORE(v)               (((v) & 0xff) << 16)
+#define BFM_APBX_CHn_SEMA_PHORE(v)              BM_APBX_CHn_SEMA_PHORE
+#define BF_APBX_CHn_SEMA_PHORE_V(e)             BF_APBX_CHn_SEMA_PHORE(BV_APBX_CHn_SEMA_PHORE__##e)
+#define BFM_APBX_CHn_SEMA_PHORE_V(v)            BM_APBX_CHn_SEMA_PHORE
+#define BP_APBX_CHn_SEMA_RSVD1                  8
+#define BM_APBX_CHn_SEMA_RSVD1                  0xff00
+#define BF_APBX_CHn_SEMA_RSVD1(v)               (((v) & 0xff) << 8)
+#define BFM_APBX_CHn_SEMA_RSVD1(v)              BM_APBX_CHn_SEMA_RSVD1
+#define BF_APBX_CHn_SEMA_RSVD1_V(e)             BF_APBX_CHn_SEMA_RSVD1(BV_APBX_CHn_SEMA_RSVD1__##e)
+#define BFM_APBX_CHn_SEMA_RSVD1_V(v)            BM_APBX_CHn_SEMA_RSVD1
+#define BP_APBX_CHn_SEMA_INCREMENT_SEMA         0
+#define BM_APBX_CHn_SEMA_INCREMENT_SEMA         0xff
+#define BF_APBX_CHn_SEMA_INCREMENT_SEMA(v)      (((v) & 0xff) << 0)
+#define BFM_APBX_CHn_SEMA_INCREMENT_SEMA(v)     BM_APBX_CHn_SEMA_INCREMENT_SEMA
+#define BF_APBX_CHn_SEMA_INCREMENT_SEMA_V(e)    BF_APBX_CHn_SEMA_INCREMENT_SEMA(BV_APBX_CHn_SEMA_INCREMENT_SEMA__##e)
+#define BFM_APBX_CHn_SEMA_INCREMENT_SEMA_V(v)   BM_APBX_CHn_SEMA_INCREMENT_SEMA
+
+#define HW_APBX_CHn_DEBUG1(_n1)                         HW(APBX_CHn_DEBUG1(_n1))
+#define HWA_APBX_CHn_DEBUG1(_n1)                        (0x80024000 + 0x150 + (_n1) * 0x70)
+#define HWT_APBX_CHn_DEBUG1(_n1)                        HWIO_32_RW
+#define HWN_APBX_CHn_DEBUG1(_n1)                        APBX_CHn_DEBUG1
+#define HWI_APBX_CHn_DEBUG1(_n1)                        (_n1)
+#define BP_APBX_CHn_DEBUG1_REQ                          31
+#define BM_APBX_CHn_DEBUG1_REQ                          0x80000000
+#define BF_APBX_CHn_DEBUG1_REQ(v)                       (((v) & 0x1) << 31)
+#define BFM_APBX_CHn_DEBUG1_REQ(v)                      BM_APBX_CHn_DEBUG1_REQ
+#define BF_APBX_CHn_DEBUG1_REQ_V(e)                     BF_APBX_CHn_DEBUG1_REQ(BV_APBX_CHn_DEBUG1_REQ__##e)
+#define BFM_APBX_CHn_DEBUG1_REQ_V(v)                    BM_APBX_CHn_DEBUG1_REQ
+#define BP_APBX_CHn_DEBUG1_BURST                        30
+#define BM_APBX_CHn_DEBUG1_BURST                        0x40000000
+#define BF_APBX_CHn_DEBUG1_BURST(v)                     (((v) & 0x1) << 30)
+#define BFM_APBX_CHn_DEBUG1_BURST(v)                    BM_APBX_CHn_DEBUG1_BURST
+#define BF_APBX_CHn_DEBUG1_BURST_V(e)                   BF_APBX_CHn_DEBUG1_BURST(BV_APBX_CHn_DEBUG1_BURST__##e)
+#define BFM_APBX_CHn_DEBUG1_BURST_V(v)                  BM_APBX_CHn_DEBUG1_BURST
+#define BP_APBX_CHn_DEBUG1_KICK                         29
+#define BM_APBX_CHn_DEBUG1_KICK                         0x20000000
+#define BF_APBX_CHn_DEBUG1_KICK(v)                      (((v) & 0x1) << 29)
+#define BFM_APBX_CHn_DEBUG1_KICK(v)                     BM_APBX_CHn_DEBUG1_KICK
+#define BF_APBX_CHn_DEBUG1_KICK_V(e)                    BF_APBX_CHn_DEBUG1_KICK(BV_APBX_CHn_DEBUG1_KICK__##e)
+#define BFM_APBX_CHn_DEBUG1_KICK_V(v)                   BM_APBX_CHn_DEBUG1_KICK
+#define BP_APBX_CHn_DEBUG1_END                          28
+#define BM_APBX_CHn_DEBUG1_END                          0x10000000
+#define BF_APBX_CHn_DEBUG1_END(v)                       (((v) & 0x1) << 28)
+#define BFM_APBX_CHn_DEBUG1_END(v)                      BM_APBX_CHn_DEBUG1_END
+#define BF_APBX_CHn_DEBUG1_END_V(e)                     BF_APBX_CHn_DEBUG1_END(BV_APBX_CHn_DEBUG1_END__##e)
+#define BFM_APBX_CHn_DEBUG1_END_V(v)                    BM_APBX_CHn_DEBUG1_END
+#define BP_APBX_CHn_DEBUG1_RSVD2                        25
+#define BM_APBX_CHn_DEBUG1_RSVD2                        0xe000000
+#define BF_APBX_CHn_DEBUG1_RSVD2(v)                     (((v) & 0x7) << 25)
+#define BFM_APBX_CHn_DEBUG1_RSVD2(v)                    BM_APBX_CHn_DEBUG1_RSVD2
+#define BF_APBX_CHn_DEBUG1_RSVD2_V(e)                   BF_APBX_CHn_DEBUG1_RSVD2(BV_APBX_CHn_DEBUG1_RSVD2__##e)
+#define BFM_APBX_CHn_DEBUG1_RSVD2_V(v)                  BM_APBX_CHn_DEBUG1_RSVD2
+#define BP_APBX_CHn_DEBUG1_NEXTCMDADDRVALID             24
+#define BM_APBX_CHn_DEBUG1_NEXTCMDADDRVALID             0x1000000
+#define BF_APBX_CHn_DEBUG1_NEXTCMDADDRVALID(v)          (((v) & 0x1) << 24)
+#define BFM_APBX_CHn_DEBUG1_NEXTCMDADDRVALID(v)         BM_APBX_CHn_DEBUG1_NEXTCMDADDRVALID
+#define BF_APBX_CHn_DEBUG1_NEXTCMDADDRVALID_V(e)        BF_APBX_CHn_DEBUG1_NEXTCMDADDRVALID(BV_APBX_CHn_DEBUG1_NEXTCMDADDRVALID__##e)
+#define BFM_APBX_CHn_DEBUG1_NEXTCMDADDRVALID_V(v)       BM_APBX_CHn_DEBUG1_NEXTCMDADDRVALID
+#define BP_APBX_CHn_DEBUG1_RD_FIFO_EMPTY                23
+#define BM_APBX_CHn_DEBUG1_RD_FIFO_EMPTY                0x800000
+#define BF_APBX_CHn_DEBUG1_RD_FIFO_EMPTY(v)             (((v) & 0x1) << 23)
+#define BFM_APBX_CHn_DEBUG1_RD_FIFO_EMPTY(v)            BM_APBX_CHn_DEBUG1_RD_FIFO_EMPTY
+#define BF_APBX_CHn_DEBUG1_RD_FIFO_EMPTY_V(e)           BF_APBX_CHn_DEBUG1_RD_FIFO_EMPTY(BV_APBX_CHn_DEBUG1_RD_FIFO_EMPTY__##e)
+#define BFM_APBX_CHn_DEBUG1_RD_FIFO_EMPTY_V(v)          BM_APBX_CHn_DEBUG1_RD_FIFO_EMPTY
+#define BP_APBX_CHn_DEBUG1_RD_FIFO_FULL                 22
+#define BM_APBX_CHn_DEBUG1_RD_FIFO_FULL                 0x400000
+#define BF_APBX_CHn_DEBUG1_RD_FIFO_FULL(v)              (((v) & 0x1) << 22)
+#define BFM_APBX_CHn_DEBUG1_RD_FIFO_FULL(v)             BM_APBX_CHn_DEBUG1_RD_FIFO_FULL
+#define BF_APBX_CHn_DEBUG1_RD_FIFO_FULL_V(e)            BF_APBX_CHn_DEBUG1_RD_FIFO_FULL(BV_APBX_CHn_DEBUG1_RD_FIFO_FULL__##e)
+#define BFM_APBX_CHn_DEBUG1_RD_FIFO_FULL_V(v)           BM_APBX_CHn_DEBUG1_RD_FIFO_FULL
+#define BP_APBX_CHn_DEBUG1_WR_FIFO_EMPTY                21
+#define BM_APBX_CHn_DEBUG1_WR_FIFO_EMPTY                0x200000
+#define BF_APBX_CHn_DEBUG1_WR_FIFO_EMPTY(v)             (((v) & 0x1) << 21)
+#define BFM_APBX_CHn_DEBUG1_WR_FIFO_EMPTY(v)            BM_APBX_CHn_DEBUG1_WR_FIFO_EMPTY
+#define BF_APBX_CHn_DEBUG1_WR_FIFO_EMPTY_V(e)           BF_APBX_CHn_DEBUG1_WR_FIFO_EMPTY(BV_APBX_CHn_DEBUG1_WR_FIFO_EMPTY__##e)
+#define BFM_APBX_CHn_DEBUG1_WR_FIFO_EMPTY_V(v)          BM_APBX_CHn_DEBUG1_WR_FIFO_EMPTY
+#define BP_APBX_CHn_DEBUG1_WR_FIFO_FULL                 20
+#define BM_APBX_CHn_DEBUG1_WR_FIFO_FULL                 0x100000
+#define BF_APBX_CHn_DEBUG1_WR_FIFO_FULL(v)              (((v) & 0x1) << 20)
+#define BFM_APBX_CHn_DEBUG1_WR_FIFO_FULL(v)             BM_APBX_CHn_DEBUG1_WR_FIFO_FULL
+#define BF_APBX_CHn_DEBUG1_WR_FIFO_FULL_V(e)            BF_APBX_CHn_DEBUG1_WR_FIFO_FULL(BV_APBX_CHn_DEBUG1_WR_FIFO_FULL__##e)
+#define BFM_APBX_CHn_DEBUG1_WR_FIFO_FULL_V(v)           BM_APBX_CHn_DEBUG1_WR_FIFO_FULL
+#define BP_APBX_CHn_DEBUG1_RSVD1                        5
+#define BM_APBX_CHn_DEBUG1_RSVD1                        0xfffe0
+#define BF_APBX_CHn_DEBUG1_RSVD1(v)                     (((v) & 0x7fff) << 5)
+#define BFM_APBX_CHn_DEBUG1_RSVD1(v)                    BM_APBX_CHn_DEBUG1_RSVD1
+#define BF_APBX_CHn_DEBUG1_RSVD1_V(e)                   BF_APBX_CHn_DEBUG1_RSVD1(BV_APBX_CHn_DEBUG1_RSVD1__##e)
+#define BFM_APBX_CHn_DEBUG1_RSVD1_V(v)                  BM_APBX_CHn_DEBUG1_RSVD1
+#define BP_APBX_CHn_DEBUG1_STATEMACHINE                 0
+#define BM_APBX_CHn_DEBUG1_STATEMACHINE                 0x1f
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__IDLE           0x0
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD1       0x1
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD3       0x2
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD2       0x3
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__XFER_DECODE    0x4
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_WAIT       0x5
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD4       0x6
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__PIO_REQ        0x7
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__READ_FLUSH     0x8
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__READ_WAIT      0x9
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__WRITE          0xc
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__READ_REQ       0xd
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__CHECK_CHAIN    0xe
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__XFER_COMPLETE  0xf
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__WAIT_END       0x15
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__WRITE_WAIT     0x1c
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__CHECK_WAIT     0x1e
+#define BF_APBX_CHn_DEBUG1_STATEMACHINE(v)              (((v) & 0x1f) << 0)
+#define BFM_APBX_CHn_DEBUG1_STATEMACHINE(v)             BM_APBX_CHn_DEBUG1_STATEMACHINE
+#define BF_APBX_CHn_DEBUG1_STATEMACHINE_V(e)            BF_APBX_CHn_DEBUG1_STATEMACHINE(BV_APBX_CHn_DEBUG1_STATEMACHINE__##e)
+#define BFM_APBX_CHn_DEBUG1_STATEMACHINE_V(v)           BM_APBX_CHn_DEBUG1_STATEMACHINE
+
+#define HW_APBX_CHn_DEBUG2(_n1)             HW(APBX_CHn_DEBUG2(_n1))
+#define HWA_APBX_CHn_DEBUG2(_n1)            (0x80024000 + 0x160 + (_n1) * 0x70)
+#define HWT_APBX_CHn_DEBUG2(_n1)            HWIO_32_RW
+#define HWN_APBX_CHn_DEBUG2(_n1)            APBX_CHn_DEBUG2
+#define HWI_APBX_CHn_DEBUG2(_n1)            (_n1)
+#define BP_APBX_CHn_DEBUG2_APB_BYTES        16
+#define BM_APBX_CHn_DEBUG2_APB_BYTES        0xffff0000
+#define BF_APBX_CHn_DEBUG2_APB_BYTES(v)     (((v) & 0xffff) << 16)
+#define BFM_APBX_CHn_DEBUG2_APB_BYTES(v)    BM_APBX_CHn_DEBUG2_APB_BYTES
+#define BF_APBX_CHn_DEBUG2_APB_BYTES_V(e)   BF_APBX_CHn_DEBUG2_APB_BYTES(BV_APBX_CHn_DEBUG2_APB_BYTES__##e)
+#define BFM_APBX_CHn_DEBUG2_APB_BYTES_V(v)  BM_APBX_CHn_DEBUG2_APB_BYTES
+#define BP_APBX_CHn_DEBUG2_AHB_BYTES        0
+#define BM_APBX_CHn_DEBUG2_AHB_BYTES        0xffff
+#define BF_APBX_CHn_DEBUG2_AHB_BYTES(v)     (((v) & 0xffff) << 0)
+#define BFM_APBX_CHn_DEBUG2_AHB_BYTES(v)    BM_APBX_CHn_DEBUG2_AHB_BYTES
+#define BF_APBX_CHn_DEBUG2_AHB_BYTES_V(e)   BF_APBX_CHn_DEBUG2_AHB_BYTES(BV_APBX_CHn_DEBUG2_AHB_BYTES__##e)
+#define BFM_APBX_CHn_DEBUG2_AHB_BYTES_V(v)  BM_APBX_CHn_DEBUG2_AHB_BYTES
+
+#define HW_APBX_VERSION             HW(APBX_VERSION)
+#define HWA_APBX_VERSION            (0x80024000 + 0x800)
+#define HWT_APBX_VERSION            HWIO_32_RW
+#define HWN_APBX_VERSION            APBX_VERSION
+#define HWI_APBX_VERSION            
+#define BP_APBX_VERSION_MAJOR       24
+#define BM_APBX_VERSION_MAJOR       0xff000000
+#define BF_APBX_VERSION_MAJOR(v)    (((v) & 0xff) << 24)
+#define BFM_APBX_VERSION_MAJOR(v)   BM_APBX_VERSION_MAJOR
+#define BF_APBX_VERSION_MAJOR_V(e)  BF_APBX_VERSION_MAJOR(BV_APBX_VERSION_MAJOR__##e)
+#define BFM_APBX_VERSION_MAJOR_V(v) BM_APBX_VERSION_MAJOR
+#define BP_APBX_VERSION_MINOR       16
+#define BM_APBX_VERSION_MINOR       0xff0000
+#define BF_APBX_VERSION_MINOR(v)    (((v) & 0xff) << 16)
+#define BFM_APBX_VERSION_MINOR(v)   BM_APBX_VERSION_MINOR
+#define BF_APBX_VERSION_MINOR_V(e)  BF_APBX_VERSION_MINOR(BV_APBX_VERSION_MINOR__##e)
+#define BFM_APBX_VERSION_MINOR_V(v) BM_APBX_VERSION_MINOR
+#define BP_APBX_VERSION_STEP        0
+#define BM_APBX_VERSION_STEP        0xffff
+#define BF_APBX_VERSION_STEP(v)     (((v) & 0xffff) << 0)
+#define BFM_APBX_VERSION_STEP(v)    BM_APBX_VERSION_STEP
+#define BF_APBX_VERSION_STEP_V(e)   BF_APBX_VERSION_STEP(BV_APBX_VERSION_STEP__##e)
+#define BFM_APBX_VERSION_STEP_V(v)  BM_APBX_VERSION_STEP
+
+#endif /* __HEADERGEN_IMX233_APBX_H__*/
diff --git a/firmware/target/arm/imx233/regs/imx233/audioin.h b/firmware/target/arm/imx233/regs/imx233/audioin.h
new file mode 100644
index 0000000000..612568f8eb
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/imx233/audioin.h
@@ -0,0 +1,691 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * imx233 version: 2.4.0
+ * imx233 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_IMX233_AUDIOIN_H__
+#define __HEADERGEN_IMX233_AUDIOIN_H__
+
+#define HW_AUDIOIN_CTRL                             HW(AUDIOIN_CTRL)
+#define HWA_AUDIOIN_CTRL                            (0x8004c000 + 0x0)
+#define HWT_AUDIOIN_CTRL                            HWIO_32_RW
+#define HWN_AUDIOIN_CTRL                            AUDIOIN_CTRL
+#define HWI_AUDIOIN_CTRL                            
+#define HW_AUDIOIN_CTRL_SET                         HW(AUDIOIN_CTRL_SET)
+#define HWA_AUDIOIN_CTRL_SET                        (HWA_AUDIOIN_CTRL + 0x4)
+#define HWT_AUDIOIN_CTRL_SET                        HWIO_32_WO
+#define HWN_AUDIOIN_CTRL_SET                        AUDIOIN_CTRL
+#define HWI_AUDIOIN_CTRL_SET                        
+#define HW_AUDIOIN_CTRL_CLR                         HW(AUDIOIN_CTRL_CLR)
+#define HWA_AUDIOIN_CTRL_CLR                        (HWA_AUDIOIN_CTRL + 0x8)
+#define HWT_AUDIOIN_CTRL_CLR                        HWIO_32_WO
+#define HWN_AUDIOIN_CTRL_CLR                        AUDIOIN_CTRL
+#define HWI_AUDIOIN_CTRL_CLR                        
+#define HW_AUDIOIN_CTRL_TOG                         HW(AUDIOIN_CTRL_TOG)
+#define HWA_AUDIOIN_CTRL_TOG                        (HWA_AUDIOIN_CTRL + 0xc)
+#define HWT_AUDIOIN_CTRL_TOG                        HWIO_32_WO
+#define HWN_AUDIOIN_CTRL_TOG                        AUDIOIN_CTRL
+#define HWI_AUDIOIN_CTRL_TOG                        
+#define BP_AUDIOIN_CTRL_SFTRST                      31
+#define BM_AUDIOIN_CTRL_SFTRST                      0x80000000
+#define BF_AUDIOIN_CTRL_SFTRST(v)                   (((v) & 0x1) << 31)
+#define BFM_AUDIOIN_CTRL_SFTRST(v)                  BM_AUDIOIN_CTRL_SFTRST
+#define BF_AUDIOIN_CTRL_SFTRST_V(e)                 BF_AUDIOIN_CTRL_SFTRST(BV_AUDIOIN_CTRL_SFTRST__##e)
+#define BFM_AUDIOIN_CTRL_SFTRST_V(v)                BM_AUDIOIN_CTRL_SFTRST
+#define BP_AUDIOIN_CTRL_CLKGATE                     30
+#define BM_AUDIOIN_CTRL_CLKGATE                     0x40000000
+#define BF_AUDIOIN_CTRL_CLKGATE(v)                  (((v) & 0x1) << 30)
+#define BFM_AUDIOIN_CTRL_CLKGATE(v)                 BM_AUDIOIN_CTRL_CLKGATE
+#define BF_AUDIOIN_CTRL_CLKGATE_V(e)                BF_AUDIOIN_CTRL_CLKGATE(BV_AUDIOIN_CTRL_CLKGATE__##e)
+#define BFM_AUDIOIN_CTRL_CLKGATE_V(v)               BM_AUDIOIN_CTRL_CLKGATE
+#define BP_AUDIOIN_CTRL_RSRVD3                      21
+#define BM_AUDIOIN_CTRL_RSRVD3                      0x3fe00000
+#define BF_AUDIOIN_CTRL_RSRVD3(v)                   (((v) & 0x1ff) << 21)
+#define BFM_AUDIOIN_CTRL_RSRVD3(v)                  BM_AUDIOIN_CTRL_RSRVD3
+#define BF_AUDIOIN_CTRL_RSRVD3_V(e)                 BF_AUDIOIN_CTRL_RSRVD3(BV_AUDIOIN_CTRL_RSRVD3__##e)
+#define BFM_AUDIOIN_CTRL_RSRVD3_V(v)                BM_AUDIOIN_CTRL_RSRVD3
+#define BP_AUDIOIN_CTRL_DMAWAIT_COUNT               16
+#define BM_AUDIOIN_CTRL_DMAWAIT_COUNT               0x1f0000
+#define BF_AUDIOIN_CTRL_DMAWAIT_COUNT(v)            (((v) & 0x1f) << 16)
+#define BFM_AUDIOIN_CTRL_DMAWAIT_COUNT(v)           BM_AUDIOIN_CTRL_DMAWAIT_COUNT
+#define BF_AUDIOIN_CTRL_DMAWAIT_COUNT_V(e)          BF_AUDIOIN_CTRL_DMAWAIT_COUNT(BV_AUDIOIN_CTRL_DMAWAIT_COUNT__##e)
+#define BFM_AUDIOIN_CTRL_DMAWAIT_COUNT_V(v)         BM_AUDIOIN_CTRL_DMAWAIT_COUNT
+#define BP_AUDIOIN_CTRL_RSRVD1                      11
+#define BM_AUDIOIN_CTRL_RSRVD1                      0xf800
+#define BF_AUDIOIN_CTRL_RSRVD1(v)                   (((v) & 0x1f) << 11)
+#define BFM_AUDIOIN_CTRL_RSRVD1(v)                  BM_AUDIOIN_CTRL_RSRVD1
+#define BF_AUDIOIN_CTRL_RSRVD1_V(e)                 BF_AUDIOIN_CTRL_RSRVD1(BV_AUDIOIN_CTRL_RSRVD1__##e)
+#define BFM_AUDIOIN_CTRL_RSRVD1_V(v)                BM_AUDIOIN_CTRL_RSRVD1
+#define BP_AUDIOIN_CTRL_LR_SWAP                     10
+#define BM_AUDIOIN_CTRL_LR_SWAP                     0x400
+#define BF_AUDIOIN_CTRL_LR_SWAP(v)                  (((v) & 0x1) << 10)
+#define BFM_AUDIOIN_CTRL_LR_SWAP(v)                 BM_AUDIOIN_CTRL_LR_SWAP
+#define BF_AUDIOIN_CTRL_LR_SWAP_V(e)                BF_AUDIOIN_CTRL_LR_SWAP(BV_AUDIOIN_CTRL_LR_SWAP__##e)
+#define BFM_AUDIOIN_CTRL_LR_SWAP_V(v)               BM_AUDIOIN_CTRL_LR_SWAP
+#define BP_AUDIOIN_CTRL_EDGE_SYNC                   9
+#define BM_AUDIOIN_CTRL_EDGE_SYNC                   0x200
+#define BF_AUDIOIN_CTRL_EDGE_SYNC(v)                (((v) & 0x1) << 9)
+#define BFM_AUDIOIN_CTRL_EDGE_SYNC(v)               BM_AUDIOIN_CTRL_EDGE_SYNC
+#define BF_AUDIOIN_CTRL_EDGE_SYNC_V(e)              BF_AUDIOIN_CTRL_EDGE_SYNC(BV_AUDIOIN_CTRL_EDGE_SYNC__##e)
+#define BFM_AUDIOIN_CTRL_EDGE_SYNC_V(v)             BM_AUDIOIN_CTRL_EDGE_SYNC
+#define BP_AUDIOIN_CTRL_INVERT_1BIT                 8
+#define BM_AUDIOIN_CTRL_INVERT_1BIT                 0x100
+#define BF_AUDIOIN_CTRL_INVERT_1BIT(v)              (((v) & 0x1) << 8)
+#define BFM_AUDIOIN_CTRL_INVERT_1BIT(v)             BM_AUDIOIN_CTRL_INVERT_1BIT
+#define BF_AUDIOIN_CTRL_INVERT_1BIT_V(e)            BF_AUDIOIN_CTRL_INVERT_1BIT(BV_AUDIOIN_CTRL_INVERT_1BIT__##e)
+#define BFM_AUDIOIN_CTRL_INVERT_1BIT_V(v)           BM_AUDIOIN_CTRL_INVERT_1BIT
+#define BP_AUDIOIN_CTRL_OFFSET_ENABLE               7
+#define BM_AUDIOIN_CTRL_OFFSET_ENABLE               0x80
+#define BF_AUDIOIN_CTRL_OFFSET_ENABLE(v)            (((v) & 0x1) << 7)
+#define BFM_AUDIOIN_CTRL_OFFSET_ENABLE(v)           BM_AUDIOIN_CTRL_OFFSET_ENABLE
+#define BF_AUDIOIN_CTRL_OFFSET_ENABLE_V(e)          BF_AUDIOIN_CTRL_OFFSET_ENABLE(BV_AUDIOIN_CTRL_OFFSET_ENABLE__##e)
+#define BFM_AUDIOIN_CTRL_OFFSET_ENABLE_V(v)         BM_AUDIOIN_CTRL_OFFSET_ENABLE
+#define BP_AUDIOIN_CTRL_HPF_ENABLE                  6
+#define BM_AUDIOIN_CTRL_HPF_ENABLE                  0x40
+#define BF_AUDIOIN_CTRL_HPF_ENABLE(v)               (((v) & 0x1) << 6)
+#define BFM_AUDIOIN_CTRL_HPF_ENABLE(v)              BM_AUDIOIN_CTRL_HPF_ENABLE
+#define BF_AUDIOIN_CTRL_HPF_ENABLE_V(e)             BF_AUDIOIN_CTRL_HPF_ENABLE(BV_AUDIOIN_CTRL_HPF_ENABLE__##e)
+#define BFM_AUDIOIN_CTRL_HPF_ENABLE_V(v)            BM_AUDIOIN_CTRL_HPF_ENABLE
+#define BP_AUDIOIN_CTRL_WORD_LENGTH                 5
+#define BM_AUDIOIN_CTRL_WORD_LENGTH                 0x20
+#define BF_AUDIOIN_CTRL_WORD_LENGTH(v)              (((v) & 0x1) << 5)
+#define BFM_AUDIOIN_CTRL_WORD_LENGTH(v)             BM_AUDIOIN_CTRL_WORD_LENGTH
+#define BF_AUDIOIN_CTRL_WORD_LENGTH_V(e)            BF_AUDIOIN_CTRL_WORD_LENGTH(BV_AUDIOIN_CTRL_WORD_LENGTH__##e)
+#define BFM_AUDIOIN_CTRL_WORD_LENGTH_V(v)           BM_AUDIOIN_CTRL_WORD_LENGTH
+#define BP_AUDIOIN_CTRL_LOOPBACK                    4
+#define BM_AUDIOIN_CTRL_LOOPBACK                    0x10
+#define BF_AUDIOIN_CTRL_LOOPBACK(v)                 (((v) & 0x1) << 4)
+#define BFM_AUDIOIN_CTRL_LOOPBACK(v)                BM_AUDIOIN_CTRL_LOOPBACK
+#define BF_AUDIOIN_CTRL_LOOPBACK_V(e)               BF_AUDIOIN_CTRL_LOOPBACK(BV_AUDIOIN_CTRL_LOOPBACK__##e)
+#define BFM_AUDIOIN_CTRL_LOOPBACK_V(v)              BM_AUDIOIN_CTRL_LOOPBACK
+#define BP_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ          3
+#define BM_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ          0x8
+#define BF_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ(v)       (((v) & 0x1) << 3)
+#define BFM_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ(v)      BM_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ
+#define BF_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ_V(e)     BF_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ(BV_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ__##e)
+#define BFM_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ_V(v)    BM_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ
+#define BP_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ           2
+#define BM_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ           0x4
+#define BF_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ(v)        (((v) & 0x1) << 2)
+#define BFM_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ(v)       BM_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ
+#define BF_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ_V(e)      BF_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ(BV_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ__##e)
+#define BFM_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ_V(v)     BM_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ
+#define BP_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN           1
+#define BM_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN           0x2
+#define BF_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN(v)        (((v) & 0x1) << 1)
+#define BFM_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN(v)       BM_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN
+#define BF_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN_V(e)      BF_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN(BV_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN__##e)
+#define BFM_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN_V(v)     BM_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN
+#define BP_AUDIOIN_CTRL_RUN                         0
+#define BM_AUDIOIN_CTRL_RUN                         0x1
+#define BF_AUDIOIN_CTRL_RUN(v)                      (((v) & 0x1) << 0)
+#define BFM_AUDIOIN_CTRL_RUN(v)                     BM_AUDIOIN_CTRL_RUN
+#define BF_AUDIOIN_CTRL_RUN_V(e)                    BF_AUDIOIN_CTRL_RUN(BV_AUDIOIN_CTRL_RUN__##e)
+#define BFM_AUDIOIN_CTRL_RUN_V(v)                   BM_AUDIOIN_CTRL_RUN
+
+#define HW_AUDIOIN_STAT                     HW(AUDIOIN_STAT)
+#define HWA_AUDIOIN_STAT                    (0x8004c000 + 0x10)
+#define HWT_AUDIOIN_STAT                    HWIO_32_RW
+#define HWN_AUDIOIN_STAT                    AUDIOIN_STAT
+#define HWI_AUDIOIN_STAT                    
+#define HW_AUDIOIN_STAT_SET                 HW(AUDIOIN_STAT_SET)
+#define HWA_AUDIOIN_STAT_SET                (HWA_AUDIOIN_STAT + 0x4)
+#define HWT_AUDIOIN_STAT_SET                HWIO_32_WO
+#define HWN_AUDIOIN_STAT_SET                AUDIOIN_STAT
+#define HWI_AUDIOIN_STAT_SET                
+#define HW_AUDIOIN_STAT_CLR                 HW(AUDIOIN_STAT_CLR)
+#define HWA_AUDIOIN_STAT_CLR                (HWA_AUDIOIN_STAT + 0x8)
+#define HWT_AUDIOIN_STAT_CLR                HWIO_32_WO
+#define HWN_AUDIOIN_STAT_CLR                AUDIOIN_STAT
+#define HWI_AUDIOIN_STAT_CLR                
+#define HW_AUDIOIN_STAT_TOG                 HW(AUDIOIN_STAT_TOG)
+#define HWA_AUDIOIN_STAT_TOG                (HWA_AUDIOIN_STAT + 0xc)
+#define HWT_AUDIOIN_STAT_TOG                HWIO_32_WO
+#define HWN_AUDIOIN_STAT_TOG                AUDIOIN_STAT
+#define HWI_AUDIOIN_STAT_TOG                
+#define BP_AUDIOIN_STAT_ADC_PRESENT         31
+#define BM_AUDIOIN_STAT_ADC_PRESENT         0x80000000
+#define BF_AUDIOIN_STAT_ADC_PRESENT(v)      (((v) & 0x1) << 31)
+#define BFM_AUDIOIN_STAT_ADC_PRESENT(v)     BM_AUDIOIN_STAT_ADC_PRESENT
+#define BF_AUDIOIN_STAT_ADC_PRESENT_V(e)    BF_AUDIOIN_STAT_ADC_PRESENT(BV_AUDIOIN_STAT_ADC_PRESENT__##e)
+#define BFM_AUDIOIN_STAT_ADC_PRESENT_V(v)   BM_AUDIOIN_STAT_ADC_PRESENT
+#define BP_AUDIOIN_STAT_RSRVD3              0
+#define BM_AUDIOIN_STAT_RSRVD3              0x7fffffff
+#define BF_AUDIOIN_STAT_RSRVD3(v)           (((v) & 0x7fffffff) << 0)
+#define BFM_AUDIOIN_STAT_RSRVD3(v)          BM_AUDIOIN_STAT_RSRVD3
+#define BF_AUDIOIN_STAT_RSRVD3_V(e)         BF_AUDIOIN_STAT_RSRVD3(BV_AUDIOIN_STAT_RSRVD3__##e)
+#define BFM_AUDIOIN_STAT_RSRVD3_V(v)        BM_AUDIOIN_STAT_RSRVD3
+
+#define HW_AUDIOIN_ADCSRR                       HW(AUDIOIN_ADCSRR)
+#define HWA_AUDIOIN_ADCSRR                      (0x8004c000 + 0x20)
+#define HWT_AUDIOIN_ADCSRR                      HWIO_32_RW
+#define HWN_AUDIOIN_ADCSRR                      AUDIOIN_ADCSRR
+#define HWI_AUDIOIN_ADCSRR                      
+#define HW_AUDIOIN_ADCSRR_SET                   HW(AUDIOIN_ADCSRR_SET)
+#define HWA_AUDIOIN_ADCSRR_SET                  (HWA_AUDIOIN_ADCSRR + 0x4)
+#define HWT_AUDIOIN_ADCSRR_SET                  HWIO_32_WO
+#define HWN_AUDIOIN_ADCSRR_SET                  AUDIOIN_ADCSRR
+#define HWI_AUDIOIN_ADCSRR_SET                  
+#define HW_AUDIOIN_ADCSRR_CLR                   HW(AUDIOIN_ADCSRR_CLR)
+#define HWA_AUDIOIN_ADCSRR_CLR                  (HWA_AUDIOIN_ADCSRR + 0x8)
+#define HWT_AUDIOIN_ADCSRR_CLR                  HWIO_32_WO
+#define HWN_AUDIOIN_ADCSRR_CLR                  AUDIOIN_ADCSRR
+#define HWI_AUDIOIN_ADCSRR_CLR                  
+#define HW_AUDIOIN_ADCSRR_TOG                   HW(AUDIOIN_ADCSRR_TOG)
+#define HWA_AUDIOIN_ADCSRR_TOG                  (HWA_AUDIOIN_ADCSRR + 0xc)
+#define HWT_AUDIOIN_ADCSRR_TOG                  HWIO_32_WO
+#define HWN_AUDIOIN_ADCSRR_TOG                  AUDIOIN_ADCSRR
+#define HWI_AUDIOIN_ADCSRR_TOG                  
+#define BP_AUDIOIN_ADCSRR_OSR                   31
+#define BM_AUDIOIN_ADCSRR_OSR                   0x80000000
+#define BV_AUDIOIN_ADCSRR_OSR__OSR6             0x0
+#define BV_AUDIOIN_ADCSRR_OSR__OSR12            0x1
+#define BF_AUDIOIN_ADCSRR_OSR(v)                (((v) & 0x1) << 31)
+#define BFM_AUDIOIN_ADCSRR_OSR(v)               BM_AUDIOIN_ADCSRR_OSR
+#define BF_AUDIOIN_ADCSRR_OSR_V(e)              BF_AUDIOIN_ADCSRR_OSR(BV_AUDIOIN_ADCSRR_OSR__##e)
+#define BFM_AUDIOIN_ADCSRR_OSR_V(v)             BM_AUDIOIN_ADCSRR_OSR
+#define BP_AUDIOIN_ADCSRR_BASEMULT              28
+#define BM_AUDIOIN_ADCSRR_BASEMULT              0x70000000
+#define BV_AUDIOIN_ADCSRR_BASEMULT__SINGLE_RATE 0x1
+#define BV_AUDIOIN_ADCSRR_BASEMULT__DOUBLE_RATE 0x2
+#define BV_AUDIOIN_ADCSRR_BASEMULT__QUAD_RATE   0x4
+#define BF_AUDIOIN_ADCSRR_BASEMULT(v)           (((v) & 0x7) << 28)
+#define BFM_AUDIOIN_ADCSRR_BASEMULT(v)          BM_AUDIOIN_ADCSRR_BASEMULT
+#define BF_AUDIOIN_ADCSRR_BASEMULT_V(e)         BF_AUDIOIN_ADCSRR_BASEMULT(BV_AUDIOIN_ADCSRR_BASEMULT__##e)
+#define BFM_AUDIOIN_ADCSRR_BASEMULT_V(v)        BM_AUDIOIN_ADCSRR_BASEMULT
+#define BP_AUDIOIN_ADCSRR_RSRVD2                27
+#define BM_AUDIOIN_ADCSRR_RSRVD2                0x8000000
+#define BF_AUDIOIN_ADCSRR_RSRVD2(v)             (((v) & 0x1) << 27)
+#define BFM_AUDIOIN_ADCSRR_RSRVD2(v)            BM_AUDIOIN_ADCSRR_RSRVD2
+#define BF_AUDIOIN_ADCSRR_RSRVD2_V(e)           BF_AUDIOIN_ADCSRR_RSRVD2(BV_AUDIOIN_ADCSRR_RSRVD2__##e)
+#define BFM_AUDIOIN_ADCSRR_RSRVD2_V(v)          BM_AUDIOIN_ADCSRR_RSRVD2
+#define BP_AUDIOIN_ADCSRR_SRC_HOLD              24
+#define BM_AUDIOIN_ADCSRR_SRC_HOLD              0x7000000
+#define BF_AUDIOIN_ADCSRR_SRC_HOLD(v)           (((v) & 0x7) << 24)
+#define BFM_AUDIOIN_ADCSRR_SRC_HOLD(v)          BM_AUDIOIN_ADCSRR_SRC_HOLD
+#define BF_AUDIOIN_ADCSRR_SRC_HOLD_V(e)         BF_AUDIOIN_ADCSRR_SRC_HOLD(BV_AUDIOIN_ADCSRR_SRC_HOLD__##e)
+#define BFM_AUDIOIN_ADCSRR_SRC_HOLD_V(v)        BM_AUDIOIN_ADCSRR_SRC_HOLD
+#define BP_AUDIOIN_ADCSRR_RSRVD1                21
+#define BM_AUDIOIN_ADCSRR_RSRVD1                0xe00000
+#define BF_AUDIOIN_ADCSRR_RSRVD1(v)             (((v) & 0x7) << 21)
+#define BFM_AUDIOIN_ADCSRR_RSRVD1(v)            BM_AUDIOIN_ADCSRR_RSRVD1
+#define BF_AUDIOIN_ADCSRR_RSRVD1_V(e)           BF_AUDIOIN_ADCSRR_RSRVD1(BV_AUDIOIN_ADCSRR_RSRVD1__##e)
+#define BFM_AUDIOIN_ADCSRR_RSRVD1_V(v)          BM_AUDIOIN_ADCSRR_RSRVD1
+#define BP_AUDIOIN_ADCSRR_SRC_INT               16
+#define BM_AUDIOIN_ADCSRR_SRC_INT               0x1f0000
+#define BF_AUDIOIN_ADCSRR_SRC_INT(v)            (((v) & 0x1f) << 16)
+#define BFM_AUDIOIN_ADCSRR_SRC_INT(v)           BM_AUDIOIN_ADCSRR_SRC_INT
+#define BF_AUDIOIN_ADCSRR_SRC_INT_V(e)          BF_AUDIOIN_ADCSRR_SRC_INT(BV_AUDIOIN_ADCSRR_SRC_INT__##e)
+#define BFM_AUDIOIN_ADCSRR_SRC_INT_V(v)         BM_AUDIOIN_ADCSRR_SRC_INT
+#define BP_AUDIOIN_ADCSRR_RSRVD0                13
+#define BM_AUDIOIN_ADCSRR_RSRVD0                0xe000
+#define BF_AUDIOIN_ADCSRR_RSRVD0(v)             (((v) & 0x7) << 13)
+#define BFM_AUDIOIN_ADCSRR_RSRVD0(v)            BM_AUDIOIN_ADCSRR_RSRVD0
+#define BF_AUDIOIN_ADCSRR_RSRVD0_V(e)           BF_AUDIOIN_ADCSRR_RSRVD0(BV_AUDIOIN_ADCSRR_RSRVD0__##e)
+#define BFM_AUDIOIN_ADCSRR_RSRVD0_V(v)          BM_AUDIOIN_ADCSRR_RSRVD0
+#define BP_AUDIOIN_ADCSRR_SRC_FRAC              0
+#define BM_AUDIOIN_ADCSRR_SRC_FRAC              0x1fff
+#define BF_AUDIOIN_ADCSRR_SRC_FRAC(v)           (((v) & 0x1fff) << 0)
+#define BFM_AUDIOIN_ADCSRR_SRC_FRAC(v)          BM_AUDIOIN_ADCSRR_SRC_FRAC
+#define BF_AUDIOIN_ADCSRR_SRC_FRAC_V(e)         BF_AUDIOIN_ADCSRR_SRC_FRAC(BV_AUDIOIN_ADCSRR_SRC_FRAC__##e)
+#define BFM_AUDIOIN_ADCSRR_SRC_FRAC_V(v)        BM_AUDIOIN_ADCSRR_SRC_FRAC
+
+#define HW_AUDIOIN_ADCVOLUME                            HW(AUDIOIN_ADCVOLUME)
+#define HWA_AUDIOIN_ADCVOLUME                           (0x8004c000 + 0x30)
+#define HWT_AUDIOIN_ADCVOLUME                           HWIO_32_RW
+#define HWN_AUDIOIN_ADCVOLUME                           AUDIOIN_ADCVOLUME
+#define HWI_AUDIOIN_ADCVOLUME                           
+#define HW_AUDIOIN_ADCVOLUME_SET                        HW(AUDIOIN_ADCVOLUME_SET)
+#define HWA_AUDIOIN_ADCVOLUME_SET                       (HWA_AUDIOIN_ADCVOLUME + 0x4)
+#define HWT_AUDIOIN_ADCVOLUME_SET                       HWIO_32_WO
+#define HWN_AUDIOIN_ADCVOLUME_SET                       AUDIOIN_ADCVOLUME
+#define HWI_AUDIOIN_ADCVOLUME_SET                       
+#define HW_AUDIOIN_ADCVOLUME_CLR                        HW(AUDIOIN_ADCVOLUME_CLR)
+#define HWA_AUDIOIN_ADCVOLUME_CLR                       (HWA_AUDIOIN_ADCVOLUME + 0x8)
+#define HWT_AUDIOIN_ADCVOLUME_CLR                       HWIO_32_WO
+#define HWN_AUDIOIN_ADCVOLUME_CLR                       AUDIOIN_ADCVOLUME
+#define HWI_AUDIOIN_ADCVOLUME_CLR                       
+#define HW_AUDIOIN_ADCVOLUME_TOG                        HW(AUDIOIN_ADCVOLUME_TOG)
+#define HWA_AUDIOIN_ADCVOLUME_TOG                       (HWA_AUDIOIN_ADCVOLUME + 0xc)
+#define HWT_AUDIOIN_ADCVOLUME_TOG                       HWIO_32_WO
+#define HWN_AUDIOIN_ADCVOLUME_TOG                       AUDIOIN_ADCVOLUME
+#define HWI_AUDIOIN_ADCVOLUME_TOG                       
+#define BP_AUDIOIN_ADCVOLUME_RSRVD5                     29
+#define BM_AUDIOIN_ADCVOLUME_RSRVD5                     0xe0000000
+#define BF_AUDIOIN_ADCVOLUME_RSRVD5(v)                  (((v) & 0x7) << 29)
+#define BFM_AUDIOIN_ADCVOLUME_RSRVD5(v)                 BM_AUDIOIN_ADCVOLUME_RSRVD5
+#define BF_AUDIOIN_ADCVOLUME_RSRVD5_V(e)                BF_AUDIOIN_ADCVOLUME_RSRVD5(BV_AUDIOIN_ADCVOLUME_RSRVD5__##e)
+#define BFM_AUDIOIN_ADCVOLUME_RSRVD5_V(v)               BM_AUDIOIN_ADCVOLUME_RSRVD5
+#define BP_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_LEFT         28
+#define BM_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_LEFT         0x10000000
+#define BF_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_LEFT(v)      (((v) & 0x1) << 28)
+#define BFM_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_LEFT(v)     BM_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_LEFT
+#define BF_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_LEFT_V(e)    BF_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_LEFT(BV_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_LEFT__##e)
+#define BFM_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_LEFT_V(v)   BM_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_LEFT
+#define BP_AUDIOIN_ADCVOLUME_RSRVD4                     26
+#define BM_AUDIOIN_ADCVOLUME_RSRVD4                     0xc000000
+#define BF_AUDIOIN_ADCVOLUME_RSRVD4(v)                  (((v) & 0x3) << 26)
+#define BFM_AUDIOIN_ADCVOLUME_RSRVD4(v)                 BM_AUDIOIN_ADCVOLUME_RSRVD4
+#define BF_AUDIOIN_ADCVOLUME_RSRVD4_V(e)                BF_AUDIOIN_ADCVOLUME_RSRVD4(BV_AUDIOIN_ADCVOLUME_RSRVD4__##e)
+#define BFM_AUDIOIN_ADCVOLUME_RSRVD4_V(v)               BM_AUDIOIN_ADCVOLUME_RSRVD4
+#define BP_AUDIOIN_ADCVOLUME_EN_ZCD                     25
+#define BM_AUDIOIN_ADCVOLUME_EN_ZCD                     0x2000000
+#define BF_AUDIOIN_ADCVOLUME_EN_ZCD(v)                  (((v) & 0x1) << 25)
+#define BFM_AUDIOIN_ADCVOLUME_EN_ZCD(v)                 BM_AUDIOIN_ADCVOLUME_EN_ZCD
+#define BF_AUDIOIN_ADCVOLUME_EN_ZCD_V(e)                BF_AUDIOIN_ADCVOLUME_EN_ZCD(BV_AUDIOIN_ADCVOLUME_EN_ZCD__##e)
+#define BFM_AUDIOIN_ADCVOLUME_EN_ZCD_V(v)               BM_AUDIOIN_ADCVOLUME_EN_ZCD
+#define BP_AUDIOIN_ADCVOLUME_RSRVD3                     24
+#define BM_AUDIOIN_ADCVOLUME_RSRVD3                     0x1000000
+#define BF_AUDIOIN_ADCVOLUME_RSRVD3(v)                  (((v) & 0x1) << 24)
+#define BFM_AUDIOIN_ADCVOLUME_RSRVD3(v)                 BM_AUDIOIN_ADCVOLUME_RSRVD3
+#define BF_AUDIOIN_ADCVOLUME_RSRVD3_V(e)                BF_AUDIOIN_ADCVOLUME_RSRVD3(BV_AUDIOIN_ADCVOLUME_RSRVD3__##e)
+#define BFM_AUDIOIN_ADCVOLUME_RSRVD3_V(v)               BM_AUDIOIN_ADCVOLUME_RSRVD3
+#define BP_AUDIOIN_ADCVOLUME_VOLUME_LEFT                16
+#define BM_AUDIOIN_ADCVOLUME_VOLUME_LEFT                0xff0000
+#define BF_AUDIOIN_ADCVOLUME_VOLUME_LEFT(v)             (((v) & 0xff) << 16)
+#define BFM_AUDIOIN_ADCVOLUME_VOLUME_LEFT(v)            BM_AUDIOIN_ADCVOLUME_VOLUME_LEFT
+#define BF_AUDIOIN_ADCVOLUME_VOLUME_LEFT_V(e)           BF_AUDIOIN_ADCVOLUME_VOLUME_LEFT(BV_AUDIOIN_ADCVOLUME_VOLUME_LEFT__##e)
+#define BFM_AUDIOIN_ADCVOLUME_VOLUME_LEFT_V(v)          BM_AUDIOIN_ADCVOLUME_VOLUME_LEFT
+#define BP_AUDIOIN_ADCVOLUME_RSRVD2                     13
+#define BM_AUDIOIN_ADCVOLUME_RSRVD2                     0xe000
+#define BF_AUDIOIN_ADCVOLUME_RSRVD2(v)                  (((v) & 0x7) << 13)
+#define BFM_AUDIOIN_ADCVOLUME_RSRVD2(v)                 BM_AUDIOIN_ADCVOLUME_RSRVD2
+#define BF_AUDIOIN_ADCVOLUME_RSRVD2_V(e)                BF_AUDIOIN_ADCVOLUME_RSRVD2(BV_AUDIOIN_ADCVOLUME_RSRVD2__##e)
+#define BFM_AUDIOIN_ADCVOLUME_RSRVD2_V(v)               BM_AUDIOIN_ADCVOLUME_RSRVD2
+#define BP_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_RIGHT        12
+#define BM_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_RIGHT        0x1000
+#define BF_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_RIGHT(v)     (((v) & 0x1) << 12)
+#define BFM_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_RIGHT(v)    BM_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_RIGHT
+#define BF_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_RIGHT_V(e)   BF_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_RIGHT(BV_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_RIGHT__##e)
+#define BFM_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_RIGHT_V(v)  BM_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_RIGHT
+#define BP_AUDIOIN_ADCVOLUME_RSRVD1                     8
+#define BM_AUDIOIN_ADCVOLUME_RSRVD1                     0xf00
+#define BF_AUDIOIN_ADCVOLUME_RSRVD1(v)                  (((v) & 0xf) << 8)
+#define BFM_AUDIOIN_ADCVOLUME_RSRVD1(v)                 BM_AUDIOIN_ADCVOLUME_RSRVD1
+#define BF_AUDIOIN_ADCVOLUME_RSRVD1_V(e)                BF_AUDIOIN_ADCVOLUME_RSRVD1(BV_AUDIOIN_ADCVOLUME_RSRVD1__##e)
+#define BFM_AUDIOIN_ADCVOLUME_RSRVD1_V(v)               BM_AUDIOIN_ADCVOLUME_RSRVD1
+#define BP_AUDIOIN_ADCVOLUME_VOLUME_RIGHT               0
+#define BM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT               0xff
+#define BF_AUDIOIN_ADCVOLUME_VOLUME_RIGHT(v)            (((v) & 0xff) << 0)
+#define BFM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT(v)           BM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT
+#define BF_AUDIOIN_ADCVOLUME_VOLUME_RIGHT_V(e)          BF_AUDIOIN_ADCVOLUME_VOLUME_RIGHT(BV_AUDIOIN_ADCVOLUME_VOLUME_RIGHT__##e)
+#define BFM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT_V(v)         BM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT
+
+#define HW_AUDIOIN_ADCDEBUG                                         HW(AUDIOIN_ADCDEBUG)
+#define HWA_AUDIOIN_ADCDEBUG                                        (0x8004c000 + 0x40)
+#define HWT_AUDIOIN_ADCDEBUG                                        HWIO_32_RW
+#define HWN_AUDIOIN_ADCDEBUG                                        AUDIOIN_ADCDEBUG
+#define HWI_AUDIOIN_ADCDEBUG                                        
+#define HW_AUDIOIN_ADCDEBUG_SET                                     HW(AUDIOIN_ADCDEBUG_SET)
+#define HWA_AUDIOIN_ADCDEBUG_SET                                    (HWA_AUDIOIN_ADCDEBUG + 0x4)
+#define HWT_AUDIOIN_ADCDEBUG_SET                                    HWIO_32_WO
+#define HWN_AUDIOIN_ADCDEBUG_SET                                    AUDIOIN_ADCDEBUG
+#define HWI_AUDIOIN_ADCDEBUG_SET                                    
+#define HW_AUDIOIN_ADCDEBUG_CLR                                     HW(AUDIOIN_ADCDEBUG_CLR)
+#define HWA_AUDIOIN_ADCDEBUG_CLR                                    (HWA_AUDIOIN_ADCDEBUG + 0x8)
+#define HWT_AUDIOIN_ADCDEBUG_CLR                                    HWIO_32_WO
+#define HWN_AUDIOIN_ADCDEBUG_CLR                                    AUDIOIN_ADCDEBUG
+#define HWI_AUDIOIN_ADCDEBUG_CLR                                    
+#define HW_AUDIOIN_ADCDEBUG_TOG                                     HW(AUDIOIN_ADCDEBUG_TOG)
+#define HWA_AUDIOIN_ADCDEBUG_TOG                                    (HWA_AUDIOIN_ADCDEBUG + 0xc)
+#define HWT_AUDIOIN_ADCDEBUG_TOG                                    HWIO_32_WO
+#define HWN_AUDIOIN_ADCDEBUG_TOG                                    AUDIOIN_ADCDEBUG
+#define HWI_AUDIOIN_ADCDEBUG_TOG                                    
+#define BP_AUDIOIN_ADCDEBUG_ENABLE_ADCDMA                           31
+#define BM_AUDIOIN_ADCDEBUG_ENABLE_ADCDMA                           0x80000000
+#define BF_AUDIOIN_ADCDEBUG_ENABLE_ADCDMA(v)                        (((v) & 0x1) << 31)
+#define BFM_AUDIOIN_ADCDEBUG_ENABLE_ADCDMA(v)                       BM_AUDIOIN_ADCDEBUG_ENABLE_ADCDMA
+#define BF_AUDIOIN_ADCDEBUG_ENABLE_ADCDMA_V(e)                      BF_AUDIOIN_ADCDEBUG_ENABLE_ADCDMA(BV_AUDIOIN_ADCDEBUG_ENABLE_ADCDMA__##e)
+#define BFM_AUDIOIN_ADCDEBUG_ENABLE_ADCDMA_V(v)                     BM_AUDIOIN_ADCDEBUG_ENABLE_ADCDMA
+#define BP_AUDIOIN_ADCDEBUG_RSRVD1                                  4
+#define BM_AUDIOIN_ADCDEBUG_RSRVD1                                  0x7ffffff0
+#define BF_AUDIOIN_ADCDEBUG_RSRVD1(v)                               (((v) & 0x7ffffff) << 4)
+#define BFM_AUDIOIN_ADCDEBUG_RSRVD1(v)                              BM_AUDIOIN_ADCDEBUG_RSRVD1
+#define BF_AUDIOIN_ADCDEBUG_RSRVD1_V(e)                             BF_AUDIOIN_ADCDEBUG_RSRVD1(BV_AUDIOIN_ADCDEBUG_RSRVD1__##e)
+#define BFM_AUDIOIN_ADCDEBUG_RSRVD1_V(v)                            BM_AUDIOIN_ADCDEBUG_RSRVD1
+#define BP_AUDIOIN_ADCDEBUG_ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS        3
+#define BM_AUDIOIN_ADCDEBUG_ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS        0x8
+#define BF_AUDIOIN_ADCDEBUG_ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS(v)     (((v) & 0x1) << 3)
+#define BFM_AUDIOIN_ADCDEBUG_ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS(v)    BM_AUDIOIN_ADCDEBUG_ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS
+#define BF_AUDIOIN_ADCDEBUG_ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS_V(e)   BF_AUDIOIN_ADCDEBUG_ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS(BV_AUDIOIN_ADCDEBUG_ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS__##e)
+#define BFM_AUDIOIN_ADCDEBUG_ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS_V(v)  BM_AUDIOIN_ADCDEBUG_ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS
+#define BP_AUDIOIN_ADCDEBUG_SET_INTERRUPT3_HAND_SHAKE               2
+#define BM_AUDIOIN_ADCDEBUG_SET_INTERRUPT3_HAND_SHAKE               0x4
+#define BF_AUDIOIN_ADCDEBUG_SET_INTERRUPT3_HAND_SHAKE(v)            (((v) & 0x1) << 2)
+#define BFM_AUDIOIN_ADCDEBUG_SET_INTERRUPT3_HAND_SHAKE(v)           BM_AUDIOIN_ADCDEBUG_SET_INTERRUPT3_HAND_SHAKE
+#define BF_AUDIOIN_ADCDEBUG_SET_INTERRUPT3_HAND_SHAKE_V(e)          BF_AUDIOIN_ADCDEBUG_SET_INTERRUPT3_HAND_SHAKE(BV_AUDIOIN_ADCDEBUG_SET_INTERRUPT3_HAND_SHAKE__##e)
+#define BFM_AUDIOIN_ADCDEBUG_SET_INTERRUPT3_HAND_SHAKE_V(v)         BM_AUDIOIN_ADCDEBUG_SET_INTERRUPT3_HAND_SHAKE
+#define BP_AUDIOIN_ADCDEBUG_DMA_PREQ                                1
+#define BM_AUDIOIN_ADCDEBUG_DMA_PREQ                                0x2
+#define BF_AUDIOIN_ADCDEBUG_DMA_PREQ(v)                             (((v) & 0x1) << 1)
+#define BFM_AUDIOIN_ADCDEBUG_DMA_PREQ(v)                            BM_AUDIOIN_ADCDEBUG_DMA_PREQ
+#define BF_AUDIOIN_ADCDEBUG_DMA_PREQ_V(e)                           BF_AUDIOIN_ADCDEBUG_DMA_PREQ(BV_AUDIOIN_ADCDEBUG_DMA_PREQ__##e)
+#define BFM_AUDIOIN_ADCDEBUG_DMA_PREQ_V(v)                          BM_AUDIOIN_ADCDEBUG_DMA_PREQ
+#define BP_AUDIOIN_ADCDEBUG_FIFO_STATUS                             0
+#define BM_AUDIOIN_ADCDEBUG_FIFO_STATUS                             0x1
+#define BF_AUDIOIN_ADCDEBUG_FIFO_STATUS(v)                          (((v) & 0x1) << 0)
+#define BFM_AUDIOIN_ADCDEBUG_FIFO_STATUS(v)                         BM_AUDIOIN_ADCDEBUG_FIFO_STATUS
+#define BF_AUDIOIN_ADCDEBUG_FIFO_STATUS_V(e)                        BF_AUDIOIN_ADCDEBUG_FIFO_STATUS(BV_AUDIOIN_ADCDEBUG_FIFO_STATUS__##e)
+#define BFM_AUDIOIN_ADCDEBUG_FIFO_STATUS_V(v)                       BM_AUDIOIN_ADCDEBUG_FIFO_STATUS
+
+#define HW_AUDIOIN_ADCVOL                               HW(AUDIOIN_ADCVOL)
+#define HWA_AUDIOIN_ADCVOL                              (0x8004c000 + 0x50)
+#define HWT_AUDIOIN_ADCVOL                              HWIO_32_RW
+#define HWN_AUDIOIN_ADCVOL                              AUDIOIN_ADCVOL
+#define HWI_AUDIOIN_ADCVOL                              
+#define HW_AUDIOIN_ADCVOL_SET                           HW(AUDIOIN_ADCVOL_SET)
+#define HWA_AUDIOIN_ADCVOL_SET                          (HWA_AUDIOIN_ADCVOL + 0x4)
+#define HWT_AUDIOIN_ADCVOL_SET                          HWIO_32_WO
+#define HWN_AUDIOIN_ADCVOL_SET                          AUDIOIN_ADCVOL
+#define HWI_AUDIOIN_ADCVOL_SET                          
+#define HW_AUDIOIN_ADCVOL_CLR                           HW(AUDIOIN_ADCVOL_CLR)
+#define HWA_AUDIOIN_ADCVOL_CLR                          (HWA_AUDIOIN_ADCVOL + 0x8)
+#define HWT_AUDIOIN_ADCVOL_CLR                          HWIO_32_WO
+#define HWN_AUDIOIN_ADCVOL_CLR                          AUDIOIN_ADCVOL
+#define HWI_AUDIOIN_ADCVOL_CLR                          
+#define HW_AUDIOIN_ADCVOL_TOG                           HW(AUDIOIN_ADCVOL_TOG)
+#define HWA_AUDIOIN_ADCVOL_TOG                          (HWA_AUDIOIN_ADCVOL + 0xc)
+#define HWT_AUDIOIN_ADCVOL_TOG                          HWIO_32_WO
+#define HWN_AUDIOIN_ADCVOL_TOG                          AUDIOIN_ADCVOL
+#define HWI_AUDIOIN_ADCVOL_TOG                          
+#define BP_AUDIOIN_ADCVOL_RSRVD4                        29
+#define BM_AUDIOIN_ADCVOL_RSRVD4                        0xe0000000
+#define BF_AUDIOIN_ADCVOL_RSRVD4(v)                     (((v) & 0x7) << 29)
+#define BFM_AUDIOIN_ADCVOL_RSRVD4(v)                    BM_AUDIOIN_ADCVOL_RSRVD4
+#define BF_AUDIOIN_ADCVOL_RSRVD4_V(e)                   BF_AUDIOIN_ADCVOL_RSRVD4(BV_AUDIOIN_ADCVOL_RSRVD4__##e)
+#define BFM_AUDIOIN_ADCVOL_RSRVD4_V(v)                  BM_AUDIOIN_ADCVOL_RSRVD4
+#define BP_AUDIOIN_ADCVOL_VOLUME_UPDATE_PENDING         28
+#define BM_AUDIOIN_ADCVOL_VOLUME_UPDATE_PENDING         0x10000000
+#define BF_AUDIOIN_ADCVOL_VOLUME_UPDATE_PENDING(v)      (((v) & 0x1) << 28)
+#define BFM_AUDIOIN_ADCVOL_VOLUME_UPDATE_PENDING(v)     BM_AUDIOIN_ADCVOL_VOLUME_UPDATE_PENDING
+#define BF_AUDIOIN_ADCVOL_VOLUME_UPDATE_PENDING_V(e)    BF_AUDIOIN_ADCVOL_VOLUME_UPDATE_PENDING(BV_AUDIOIN_ADCVOL_VOLUME_UPDATE_PENDING__##e)
+#define BFM_AUDIOIN_ADCVOL_VOLUME_UPDATE_PENDING_V(v)   BM_AUDIOIN_ADCVOL_VOLUME_UPDATE_PENDING
+#define BP_AUDIOIN_ADCVOL_RSRVD3                        26
+#define BM_AUDIOIN_ADCVOL_RSRVD3                        0xc000000
+#define BF_AUDIOIN_ADCVOL_RSRVD3(v)                     (((v) & 0x3) << 26)
+#define BFM_AUDIOIN_ADCVOL_RSRVD3(v)                    BM_AUDIOIN_ADCVOL_RSRVD3
+#define BF_AUDIOIN_ADCVOL_RSRVD3_V(e)                   BF_AUDIOIN_ADCVOL_RSRVD3(BV_AUDIOIN_ADCVOL_RSRVD3__##e)
+#define BFM_AUDIOIN_ADCVOL_RSRVD3_V(v)                  BM_AUDIOIN_ADCVOL_RSRVD3
+#define BP_AUDIOIN_ADCVOL_EN_ADC_ZCD                    25
+#define BM_AUDIOIN_ADCVOL_EN_ADC_ZCD                    0x2000000
+#define BF_AUDIOIN_ADCVOL_EN_ADC_ZCD(v)                 (((v) & 0x1) << 25)
+#define BFM_AUDIOIN_ADCVOL_EN_ADC_ZCD(v)                BM_AUDIOIN_ADCVOL_EN_ADC_ZCD
+#define BF_AUDIOIN_ADCVOL_EN_ADC_ZCD_V(e)               BF_AUDIOIN_ADCVOL_EN_ADC_ZCD(BV_AUDIOIN_ADCVOL_EN_ADC_ZCD__##e)
+#define BFM_AUDIOIN_ADCVOL_EN_ADC_ZCD_V(v)              BM_AUDIOIN_ADCVOL_EN_ADC_ZCD
+#define BP_AUDIOIN_ADCVOL_MUTE                          24
+#define BM_AUDIOIN_ADCVOL_MUTE                          0x1000000
+#define BF_AUDIOIN_ADCVOL_MUTE(v)                       (((v) & 0x1) << 24)
+#define BFM_AUDIOIN_ADCVOL_MUTE(v)                      BM_AUDIOIN_ADCVOL_MUTE
+#define BF_AUDIOIN_ADCVOL_MUTE_V(e)                     BF_AUDIOIN_ADCVOL_MUTE(BV_AUDIOIN_ADCVOL_MUTE__##e)
+#define BFM_AUDIOIN_ADCVOL_MUTE_V(v)                    BM_AUDIOIN_ADCVOL_MUTE
+#define BP_AUDIOIN_ADCVOL_RSRVD2                        14
+#define BM_AUDIOIN_ADCVOL_RSRVD2                        0xffc000
+#define BF_AUDIOIN_ADCVOL_RSRVD2(v)                     (((v) & 0x3ff) << 14)
+#define BFM_AUDIOIN_ADCVOL_RSRVD2(v)                    BM_AUDIOIN_ADCVOL_RSRVD2
+#define BF_AUDIOIN_ADCVOL_RSRVD2_V(e)                   BF_AUDIOIN_ADCVOL_RSRVD2(BV_AUDIOIN_ADCVOL_RSRVD2__##e)
+#define BFM_AUDIOIN_ADCVOL_RSRVD2_V(v)                  BM_AUDIOIN_ADCVOL_RSRVD2
+#define BP_AUDIOIN_ADCVOL_SELECT_LEFT                   12
+#define BM_AUDIOIN_ADCVOL_SELECT_LEFT                   0x3000
+#define BF_AUDIOIN_ADCVOL_SELECT_LEFT(v)                (((v) & 0x3) << 12)
+#define BFM_AUDIOIN_ADCVOL_SELECT_LEFT(v)               BM_AUDIOIN_ADCVOL_SELECT_LEFT
+#define BF_AUDIOIN_ADCVOL_SELECT_LEFT_V(e)              BF_AUDIOIN_ADCVOL_SELECT_LEFT(BV_AUDIOIN_ADCVOL_SELECT_LEFT__##e)
+#define BFM_AUDIOIN_ADCVOL_SELECT_LEFT_V(v)             BM_AUDIOIN_ADCVOL_SELECT_LEFT
+#define BP_AUDIOIN_ADCVOL_GAIN_LEFT                     8
+#define BM_AUDIOIN_ADCVOL_GAIN_LEFT                     0xf00
+#define BF_AUDIOIN_ADCVOL_GAIN_LEFT(v)                  (((v) & 0xf) << 8)
+#define BFM_AUDIOIN_ADCVOL_GAIN_LEFT(v)                 BM_AUDIOIN_ADCVOL_GAIN_LEFT
+#define BF_AUDIOIN_ADCVOL_GAIN_LEFT_V(e)                BF_AUDIOIN_ADCVOL_GAIN_LEFT(BV_AUDIOIN_ADCVOL_GAIN_LEFT__##e)
+#define BFM_AUDIOIN_ADCVOL_GAIN_LEFT_V(v)               BM_AUDIOIN_ADCVOL_GAIN_LEFT
+#define BP_AUDIOIN_ADCVOL_RSRVD1                        6
+#define BM_AUDIOIN_ADCVOL_RSRVD1                        0xc0
+#define BF_AUDIOIN_ADCVOL_RSRVD1(v)                     (((v) & 0x3) << 6)
+#define BFM_AUDIOIN_ADCVOL_RSRVD1(v)                    BM_AUDIOIN_ADCVOL_RSRVD1
+#define BF_AUDIOIN_ADCVOL_RSRVD1_V(e)                   BF_AUDIOIN_ADCVOL_RSRVD1(BV_AUDIOIN_ADCVOL_RSRVD1__##e)
+#define BFM_AUDIOIN_ADCVOL_RSRVD1_V(v)                  BM_AUDIOIN_ADCVOL_RSRVD1
+#define BP_AUDIOIN_ADCVOL_SELECT_RIGHT                  4
+#define BM_AUDIOIN_ADCVOL_SELECT_RIGHT                  0x30
+#define BF_AUDIOIN_ADCVOL_SELECT_RIGHT(v)               (((v) & 0x3) << 4)
+#define BFM_AUDIOIN_ADCVOL_SELECT_RIGHT(v)              BM_AUDIOIN_ADCVOL_SELECT_RIGHT
+#define BF_AUDIOIN_ADCVOL_SELECT_RIGHT_V(e)             BF_AUDIOIN_ADCVOL_SELECT_RIGHT(BV_AUDIOIN_ADCVOL_SELECT_RIGHT__##e)
+#define BFM_AUDIOIN_ADCVOL_SELECT_RIGHT_V(v)            BM_AUDIOIN_ADCVOL_SELECT_RIGHT
+#define BP_AUDIOIN_ADCVOL_GAIN_RIGHT                    0
+#define BM_AUDIOIN_ADCVOL_GAIN_RIGHT                    0xf
+#define BF_AUDIOIN_ADCVOL_GAIN_RIGHT(v)                 (((v) & 0xf) << 0)
+#define BFM_AUDIOIN_ADCVOL_GAIN_RIGHT(v)                BM_AUDIOIN_ADCVOL_GAIN_RIGHT
+#define BF_AUDIOIN_ADCVOL_GAIN_RIGHT_V(e)               BF_AUDIOIN_ADCVOL_GAIN_RIGHT(BV_AUDIOIN_ADCVOL_GAIN_RIGHT__##e)
+#define BFM_AUDIOIN_ADCVOL_GAIN_RIGHT_V(v)              BM_AUDIOIN_ADCVOL_GAIN_RIGHT
+
+#define HW_AUDIOIN_MICLINE                      HW(AUDIOIN_MICLINE)
+#define HWA_AUDIOIN_MICLINE                     (0x8004c000 + 0x60)
+#define HWT_AUDIOIN_MICLINE                     HWIO_32_RW
+#define HWN_AUDIOIN_MICLINE                     AUDIOIN_MICLINE
+#define HWI_AUDIOIN_MICLINE                     
+#define HW_AUDIOIN_MICLINE_SET                  HW(AUDIOIN_MICLINE_SET)
+#define HWA_AUDIOIN_MICLINE_SET                 (HWA_AUDIOIN_MICLINE + 0x4)
+#define HWT_AUDIOIN_MICLINE_SET                 HWIO_32_WO
+#define HWN_AUDIOIN_MICLINE_SET                 AUDIOIN_MICLINE
+#define HWI_AUDIOIN_MICLINE_SET                 
+#define HW_AUDIOIN_MICLINE_CLR                  HW(AUDIOIN_MICLINE_CLR)
+#define HWA_AUDIOIN_MICLINE_CLR                 (HWA_AUDIOIN_MICLINE + 0x8)
+#define HWT_AUDIOIN_MICLINE_CLR                 HWIO_32_WO
+#define HWN_AUDIOIN_MICLINE_CLR                 AUDIOIN_MICLINE
+#define HWI_AUDIOIN_MICLINE_CLR                 
+#define HW_AUDIOIN_MICLINE_TOG                  HW(AUDIOIN_MICLINE_TOG)
+#define HWA_AUDIOIN_MICLINE_TOG                 (HWA_AUDIOIN_MICLINE + 0xc)
+#define HWT_AUDIOIN_MICLINE_TOG                 HWIO_32_WO
+#define HWN_AUDIOIN_MICLINE_TOG                 AUDIOIN_MICLINE
+#define HWI_AUDIOIN_MICLINE_TOG                 
+#define BP_AUDIOIN_MICLINE_RSRVD6               30
+#define BM_AUDIOIN_MICLINE_RSRVD6               0xc0000000
+#define BF_AUDIOIN_MICLINE_RSRVD6(v)            (((v) & 0x3) << 30)
+#define BFM_AUDIOIN_MICLINE_RSRVD6(v)           BM_AUDIOIN_MICLINE_RSRVD6
+#define BF_AUDIOIN_MICLINE_RSRVD6_V(e)          BF_AUDIOIN_MICLINE_RSRVD6(BV_AUDIOIN_MICLINE_RSRVD6__##e)
+#define BFM_AUDIOIN_MICLINE_RSRVD6_V(v)         BM_AUDIOIN_MICLINE_RSRVD6
+#define BP_AUDIOIN_MICLINE_DIVIDE_LINE1         29
+#define BM_AUDIOIN_MICLINE_DIVIDE_LINE1         0x20000000
+#define BF_AUDIOIN_MICLINE_DIVIDE_LINE1(v)      (((v) & 0x1) << 29)
+#define BFM_AUDIOIN_MICLINE_DIVIDE_LINE1(v)     BM_AUDIOIN_MICLINE_DIVIDE_LINE1
+#define BF_AUDIOIN_MICLINE_DIVIDE_LINE1_V(e)    BF_AUDIOIN_MICLINE_DIVIDE_LINE1(BV_AUDIOIN_MICLINE_DIVIDE_LINE1__##e)
+#define BFM_AUDIOIN_MICLINE_DIVIDE_LINE1_V(v)   BM_AUDIOIN_MICLINE_DIVIDE_LINE1
+#define BP_AUDIOIN_MICLINE_DIVIDE_LINE2         28
+#define BM_AUDIOIN_MICLINE_DIVIDE_LINE2         0x10000000
+#define BF_AUDIOIN_MICLINE_DIVIDE_LINE2(v)      (((v) & 0x1) << 28)
+#define BFM_AUDIOIN_MICLINE_DIVIDE_LINE2(v)     BM_AUDIOIN_MICLINE_DIVIDE_LINE2
+#define BF_AUDIOIN_MICLINE_DIVIDE_LINE2_V(e)    BF_AUDIOIN_MICLINE_DIVIDE_LINE2(BV_AUDIOIN_MICLINE_DIVIDE_LINE2__##e)
+#define BFM_AUDIOIN_MICLINE_DIVIDE_LINE2_V(v)   BM_AUDIOIN_MICLINE_DIVIDE_LINE2
+#define BP_AUDIOIN_MICLINE_RSRVD5               25
+#define BM_AUDIOIN_MICLINE_RSRVD5               0xe000000
+#define BF_AUDIOIN_MICLINE_RSRVD5(v)            (((v) & 0x7) << 25)
+#define BFM_AUDIOIN_MICLINE_RSRVD5(v)           BM_AUDIOIN_MICLINE_RSRVD5
+#define BF_AUDIOIN_MICLINE_RSRVD5_V(e)          BF_AUDIOIN_MICLINE_RSRVD5(BV_AUDIOIN_MICLINE_RSRVD5__##e)
+#define BFM_AUDIOIN_MICLINE_RSRVD5_V(v)         BM_AUDIOIN_MICLINE_RSRVD5
+#define BP_AUDIOIN_MICLINE_MIC_SELECT           24
+#define BM_AUDIOIN_MICLINE_MIC_SELECT           0x1000000
+#define BF_AUDIOIN_MICLINE_MIC_SELECT(v)        (((v) & 0x1) << 24)
+#define BFM_AUDIOIN_MICLINE_MIC_SELECT(v)       BM_AUDIOIN_MICLINE_MIC_SELECT
+#define BF_AUDIOIN_MICLINE_MIC_SELECT_V(e)      BF_AUDIOIN_MICLINE_MIC_SELECT(BV_AUDIOIN_MICLINE_MIC_SELECT__##e)
+#define BFM_AUDIOIN_MICLINE_MIC_SELECT_V(v)     BM_AUDIOIN_MICLINE_MIC_SELECT
+#define BP_AUDIOIN_MICLINE_RSRVD4               22
+#define BM_AUDIOIN_MICLINE_RSRVD4               0xc00000
+#define BF_AUDIOIN_MICLINE_RSRVD4(v)            (((v) & 0x3) << 22)
+#define BFM_AUDIOIN_MICLINE_RSRVD4(v)           BM_AUDIOIN_MICLINE_RSRVD4
+#define BF_AUDIOIN_MICLINE_RSRVD4_V(e)          BF_AUDIOIN_MICLINE_RSRVD4(BV_AUDIOIN_MICLINE_RSRVD4__##e)
+#define BFM_AUDIOIN_MICLINE_RSRVD4_V(v)         BM_AUDIOIN_MICLINE_RSRVD4
+#define BP_AUDIOIN_MICLINE_MIC_RESISTOR         20
+#define BM_AUDIOIN_MICLINE_MIC_RESISTOR         0x300000
+#define BV_AUDIOIN_MICLINE_MIC_RESISTOR__Off    0x0
+#define BV_AUDIOIN_MICLINE_MIC_RESISTOR__2KOhm  0x1
+#define BV_AUDIOIN_MICLINE_MIC_RESISTOR__4KOhm  0x2
+#define BV_AUDIOIN_MICLINE_MIC_RESISTOR__8KOhm  0x3
+#define BF_AUDIOIN_MICLINE_MIC_RESISTOR(v)      (((v) & 0x3) << 20)
+#define BFM_AUDIOIN_MICLINE_MIC_RESISTOR(v)     BM_AUDIOIN_MICLINE_MIC_RESISTOR
+#define BF_AUDIOIN_MICLINE_MIC_RESISTOR_V(e)    BF_AUDIOIN_MICLINE_MIC_RESISTOR(BV_AUDIOIN_MICLINE_MIC_RESISTOR__##e)
+#define BFM_AUDIOIN_MICLINE_MIC_RESISTOR_V(v)   BM_AUDIOIN_MICLINE_MIC_RESISTOR
+#define BP_AUDIOIN_MICLINE_RSRVD3               19
+#define BM_AUDIOIN_MICLINE_RSRVD3               0x80000
+#define BF_AUDIOIN_MICLINE_RSRVD3(v)            (((v) & 0x1) << 19)
+#define BFM_AUDIOIN_MICLINE_RSRVD3(v)           BM_AUDIOIN_MICLINE_RSRVD3
+#define BF_AUDIOIN_MICLINE_RSRVD3_V(e)          BF_AUDIOIN_MICLINE_RSRVD3(BV_AUDIOIN_MICLINE_RSRVD3__##e)
+#define BFM_AUDIOIN_MICLINE_RSRVD3_V(v)         BM_AUDIOIN_MICLINE_RSRVD3
+#define BP_AUDIOIN_MICLINE_MIC_BIAS             16
+#define BM_AUDIOIN_MICLINE_MIC_BIAS             0x70000
+#define BF_AUDIOIN_MICLINE_MIC_BIAS(v)          (((v) & 0x7) << 16)
+#define BFM_AUDIOIN_MICLINE_MIC_BIAS(v)         BM_AUDIOIN_MICLINE_MIC_BIAS
+#define BF_AUDIOIN_MICLINE_MIC_BIAS_V(e)        BF_AUDIOIN_MICLINE_MIC_BIAS(BV_AUDIOIN_MICLINE_MIC_BIAS__##e)
+#define BFM_AUDIOIN_MICLINE_MIC_BIAS_V(v)       BM_AUDIOIN_MICLINE_MIC_BIAS
+#define BP_AUDIOIN_MICLINE_RSRVD2               6
+#define BM_AUDIOIN_MICLINE_RSRVD2               0xffc0
+#define BF_AUDIOIN_MICLINE_RSRVD2(v)            (((v) & 0x3ff) << 6)
+#define BFM_AUDIOIN_MICLINE_RSRVD2(v)           BM_AUDIOIN_MICLINE_RSRVD2
+#define BF_AUDIOIN_MICLINE_RSRVD2_V(e)          BF_AUDIOIN_MICLINE_RSRVD2(BV_AUDIOIN_MICLINE_RSRVD2__##e)
+#define BFM_AUDIOIN_MICLINE_RSRVD2_V(v)         BM_AUDIOIN_MICLINE_RSRVD2
+#define BP_AUDIOIN_MICLINE_MIC_CHOPCLK          4
+#define BM_AUDIOIN_MICLINE_MIC_CHOPCLK          0x30
+#define BF_AUDIOIN_MICLINE_MIC_CHOPCLK(v)       (((v) & 0x3) << 4)
+#define BFM_AUDIOIN_MICLINE_MIC_CHOPCLK(v)      BM_AUDIOIN_MICLINE_MIC_CHOPCLK
+#define BF_AUDIOIN_MICLINE_MIC_CHOPCLK_V(e)     BF_AUDIOIN_MICLINE_MIC_CHOPCLK(BV_AUDIOIN_MICLINE_MIC_CHOPCLK__##e)
+#define BFM_AUDIOIN_MICLINE_MIC_CHOPCLK_V(v)    BM_AUDIOIN_MICLINE_MIC_CHOPCLK
+#define BP_AUDIOIN_MICLINE_RSRVD1               2
+#define BM_AUDIOIN_MICLINE_RSRVD1               0xc
+#define BF_AUDIOIN_MICLINE_RSRVD1(v)            (((v) & 0x3) << 2)
+#define BFM_AUDIOIN_MICLINE_RSRVD1(v)           BM_AUDIOIN_MICLINE_RSRVD1
+#define BF_AUDIOIN_MICLINE_RSRVD1_V(e)          BF_AUDIOIN_MICLINE_RSRVD1(BV_AUDIOIN_MICLINE_RSRVD1__##e)
+#define BFM_AUDIOIN_MICLINE_RSRVD1_V(v)         BM_AUDIOIN_MICLINE_RSRVD1
+#define BP_AUDIOIN_MICLINE_MIC_GAIN             0
+#define BM_AUDIOIN_MICLINE_MIC_GAIN             0x3
+#define BV_AUDIOIN_MICLINE_MIC_GAIN__0dB        0x0
+#define BV_AUDIOIN_MICLINE_MIC_GAIN__20dB       0x1
+#define BV_AUDIOIN_MICLINE_MIC_GAIN__30dB       0x2
+#define BV_AUDIOIN_MICLINE_MIC_GAIN__40dB       0x3
+#define BF_AUDIOIN_MICLINE_MIC_GAIN(v)          (((v) & 0x3) << 0)
+#define BFM_AUDIOIN_MICLINE_MIC_GAIN(v)         BM_AUDIOIN_MICLINE_MIC_GAIN
+#define BF_AUDIOIN_MICLINE_MIC_GAIN_V(e)        BF_AUDIOIN_MICLINE_MIC_GAIN(BV_AUDIOIN_MICLINE_MIC_GAIN__##e)
+#define BFM_AUDIOIN_MICLINE_MIC_GAIN_V(v)       BM_AUDIOIN_MICLINE_MIC_GAIN
+
+#define HW_AUDIOIN_ANACLKCTRL                       HW(AUDIOIN_ANACLKCTRL)
+#define HWA_AUDIOIN_ANACLKCTRL                      (0x8004c000 + 0x70)
+#define HWT_AUDIOIN_ANACLKCTRL                      HWIO_32_RW
+#define HWN_AUDIOIN_ANACLKCTRL                      AUDIOIN_ANACLKCTRL
+#define HWI_AUDIOIN_ANACLKCTRL                      
+#define HW_AUDIOIN_ANACLKCTRL_SET                   HW(AUDIOIN_ANACLKCTRL_SET)
+#define HWA_AUDIOIN_ANACLKCTRL_SET                  (HWA_AUDIOIN_ANACLKCTRL + 0x4)
+#define HWT_AUDIOIN_ANACLKCTRL_SET                  HWIO_32_WO
+#define HWN_AUDIOIN_ANACLKCTRL_SET                  AUDIOIN_ANACLKCTRL
+#define HWI_AUDIOIN_ANACLKCTRL_SET                  
+#define HW_AUDIOIN_ANACLKCTRL_CLR                   HW(AUDIOIN_ANACLKCTRL_CLR)
+#define HWA_AUDIOIN_ANACLKCTRL_CLR                  (HWA_AUDIOIN_ANACLKCTRL + 0x8)
+#define HWT_AUDIOIN_ANACLKCTRL_CLR                  HWIO_32_WO
+#define HWN_AUDIOIN_ANACLKCTRL_CLR                  AUDIOIN_ANACLKCTRL
+#define HWI_AUDIOIN_ANACLKCTRL_CLR                  
+#define HW_AUDIOIN_ANACLKCTRL_TOG                   HW(AUDIOIN_ANACLKCTRL_TOG)
+#define HWA_AUDIOIN_ANACLKCTRL_TOG                  (HWA_AUDIOIN_ANACLKCTRL + 0xc)
+#define HWT_AUDIOIN_ANACLKCTRL_TOG                  HWIO_32_WO
+#define HWN_AUDIOIN_ANACLKCTRL_TOG                  AUDIOIN_ANACLKCTRL
+#define HWI_AUDIOIN_ANACLKCTRL_TOG                  
+#define BP_AUDIOIN_ANACLKCTRL_CLKGATE               31
+#define BM_AUDIOIN_ANACLKCTRL_CLKGATE               0x80000000
+#define BF_AUDIOIN_ANACLKCTRL_CLKGATE(v)            (((v) & 0x1) << 31)
+#define BFM_AUDIOIN_ANACLKCTRL_CLKGATE(v)           BM_AUDIOIN_ANACLKCTRL_CLKGATE
+#define BF_AUDIOIN_ANACLKCTRL_CLKGATE_V(e)          BF_AUDIOIN_ANACLKCTRL_CLKGATE(BV_AUDIOIN_ANACLKCTRL_CLKGATE__##e)
+#define BFM_AUDIOIN_ANACLKCTRL_CLKGATE_V(v)         BM_AUDIOIN_ANACLKCTRL_CLKGATE
+#define BP_AUDIOIN_ANACLKCTRL_RSRVD4                11
+#define BM_AUDIOIN_ANACLKCTRL_RSRVD4                0x7ffff800
+#define BF_AUDIOIN_ANACLKCTRL_RSRVD4(v)             (((v) & 0xfffff) << 11)
+#define BFM_AUDIOIN_ANACLKCTRL_RSRVD4(v)            BM_AUDIOIN_ANACLKCTRL_RSRVD4
+#define BF_AUDIOIN_ANACLKCTRL_RSRVD4_V(e)           BF_AUDIOIN_ANACLKCTRL_RSRVD4(BV_AUDIOIN_ANACLKCTRL_RSRVD4__##e)
+#define BFM_AUDIOIN_ANACLKCTRL_RSRVD4_V(v)          BM_AUDIOIN_ANACLKCTRL_RSRVD4
+#define BP_AUDIOIN_ANACLKCTRL_DITHER_OFF            10
+#define BM_AUDIOIN_ANACLKCTRL_DITHER_OFF            0x400
+#define BF_AUDIOIN_ANACLKCTRL_DITHER_OFF(v)         (((v) & 0x1) << 10)
+#define BFM_AUDIOIN_ANACLKCTRL_DITHER_OFF(v)        BM_AUDIOIN_ANACLKCTRL_DITHER_OFF
+#define BF_AUDIOIN_ANACLKCTRL_DITHER_OFF_V(e)       BF_AUDIOIN_ANACLKCTRL_DITHER_OFF(BV_AUDIOIN_ANACLKCTRL_DITHER_OFF__##e)
+#define BFM_AUDIOIN_ANACLKCTRL_DITHER_OFF_V(v)      BM_AUDIOIN_ANACLKCTRL_DITHER_OFF
+#define BP_AUDIOIN_ANACLKCTRL_SLOW_DITHER           9
+#define BM_AUDIOIN_ANACLKCTRL_SLOW_DITHER           0x200
+#define BF_AUDIOIN_ANACLKCTRL_SLOW_DITHER(v)        (((v) & 0x1) << 9)
+#define BFM_AUDIOIN_ANACLKCTRL_SLOW_DITHER(v)       BM_AUDIOIN_ANACLKCTRL_SLOW_DITHER
+#define BF_AUDIOIN_ANACLKCTRL_SLOW_DITHER_V(e)      BF_AUDIOIN_ANACLKCTRL_SLOW_DITHER(BV_AUDIOIN_ANACLKCTRL_SLOW_DITHER__##e)
+#define BFM_AUDIOIN_ANACLKCTRL_SLOW_DITHER_V(v)     BM_AUDIOIN_ANACLKCTRL_SLOW_DITHER
+#define BP_AUDIOIN_ANACLKCTRL_INVERT_ADCCLK         8
+#define BM_AUDIOIN_ANACLKCTRL_INVERT_ADCCLK         0x100
+#define BF_AUDIOIN_ANACLKCTRL_INVERT_ADCCLK(v)      (((v) & 0x1) << 8)
+#define BFM_AUDIOIN_ANACLKCTRL_INVERT_ADCCLK(v)     BM_AUDIOIN_ANACLKCTRL_INVERT_ADCCLK
+#define BF_AUDIOIN_ANACLKCTRL_INVERT_ADCCLK_V(e)    BF_AUDIOIN_ANACLKCTRL_INVERT_ADCCLK(BV_AUDIOIN_ANACLKCTRL_INVERT_ADCCLK__##e)
+#define BFM_AUDIOIN_ANACLKCTRL_INVERT_ADCCLK_V(v)   BM_AUDIOIN_ANACLKCTRL_INVERT_ADCCLK
+#define BP_AUDIOIN_ANACLKCTRL_RSRVD3                6
+#define BM_AUDIOIN_ANACLKCTRL_RSRVD3                0xc0
+#define BF_AUDIOIN_ANACLKCTRL_RSRVD3(v)             (((v) & 0x3) << 6)
+#define BFM_AUDIOIN_ANACLKCTRL_RSRVD3(v)            BM_AUDIOIN_ANACLKCTRL_RSRVD3
+#define BF_AUDIOIN_ANACLKCTRL_RSRVD3_V(e)           BF_AUDIOIN_ANACLKCTRL_RSRVD3(BV_AUDIOIN_ANACLKCTRL_RSRVD3__##e)
+#define BFM_AUDIOIN_ANACLKCTRL_RSRVD3_V(v)          BM_AUDIOIN_ANACLKCTRL_RSRVD3
+#define BP_AUDIOIN_ANACLKCTRL_ADCCLK_SHIFT          4
+#define BM_AUDIOIN_ANACLKCTRL_ADCCLK_SHIFT          0x30
+#define BF_AUDIOIN_ANACLKCTRL_ADCCLK_SHIFT(v)       (((v) & 0x3) << 4)
+#define BFM_AUDIOIN_ANACLKCTRL_ADCCLK_SHIFT(v)      BM_AUDIOIN_ANACLKCTRL_ADCCLK_SHIFT
+#define BF_AUDIOIN_ANACLKCTRL_ADCCLK_SHIFT_V(e)     BF_AUDIOIN_ANACLKCTRL_ADCCLK_SHIFT(BV_AUDIOIN_ANACLKCTRL_ADCCLK_SHIFT__##e)
+#define BFM_AUDIOIN_ANACLKCTRL_ADCCLK_SHIFT_V(v)    BM_AUDIOIN_ANACLKCTRL_ADCCLK_SHIFT
+#define BP_AUDIOIN_ANACLKCTRL_RSRVD2                3
+#define BM_AUDIOIN_ANACLKCTRL_RSRVD2                0x8
+#define BF_AUDIOIN_ANACLKCTRL_RSRVD2(v)             (((v) & 0x1) << 3)
+#define BFM_AUDIOIN_ANACLKCTRL_RSRVD2(v)            BM_AUDIOIN_ANACLKCTRL_RSRVD2
+#define BF_AUDIOIN_ANACLKCTRL_RSRVD2_V(e)           BF_AUDIOIN_ANACLKCTRL_RSRVD2(BV_AUDIOIN_ANACLKCTRL_RSRVD2__##e)
+#define BFM_AUDIOIN_ANACLKCTRL_RSRVD2_V(v)          BM_AUDIOIN_ANACLKCTRL_RSRVD2
+#define BP_AUDIOIN_ANACLKCTRL_ADCDIV                0
+#define BM_AUDIOIN_ANACLKCTRL_ADCDIV                0x7
+#define BF_AUDIOIN_ANACLKCTRL_ADCDIV(v)             (((v) & 0x7) << 0)
+#define BFM_AUDIOIN_ANACLKCTRL_ADCDIV(v)            BM_AUDIOIN_ANACLKCTRL_ADCDIV
+#define BF_AUDIOIN_ANACLKCTRL_ADCDIV_V(e)           BF_AUDIOIN_ANACLKCTRL_ADCDIV(BV_AUDIOIN_ANACLKCTRL_ADCDIV__##e)
+#define BFM_AUDIOIN_ANACLKCTRL_ADCDIV_V(v)          BM_AUDIOIN_ANACLKCTRL_ADCDIV
+
+#define HW_AUDIOIN_DATA             HW(AUDIOIN_DATA)
+#define HWA_AUDIOIN_DATA            (0x8004c000 + 0x80)
+#define HWT_AUDIOIN_DATA            HWIO_32_RW
+#define HWN_AUDIOIN_DATA            AUDIOIN_DATA
+#define HWI_AUDIOIN_DATA            
+#define HW_AUDIOIN_DATA_SET         HW(AUDIOIN_DATA_SET)
+#define HWA_AUDIOIN_DATA_SET        (HWA_AUDIOIN_DATA + 0x4)
+#define HWT_AUDIOIN_DATA_SET        HWIO_32_WO
+#define HWN_AUDIOIN_DATA_SET        AUDIOIN_DATA
+#define HWI_AUDIOIN_DATA_SET        
+#define HW_AUDIOIN_DATA_CLR         HW(AUDIOIN_DATA_CLR)
+#define HWA_AUDIOIN_DATA_CLR        (HWA_AUDIOIN_DATA + 0x8)
+#define HWT_AUDIOIN_DATA_CLR        HWIO_32_WO
+#define HWN_AUDIOIN_DATA_CLR        AUDIOIN_DATA
+#define HWI_AUDIOIN_DATA_CLR        
+#define HW_AUDIOIN_DATA_TOG         HW(AUDIOIN_DATA_TOG)
+#define HWA_AUDIOIN_DATA_TOG        (HWA_AUDIOIN_DATA + 0xc)
+#define HWT_AUDIOIN_DATA_TOG        HWIO_32_WO
+#define HWN_AUDIOIN_DATA_TOG        AUDIOIN_DATA
+#define HWI_AUDIOIN_DATA_TOG        
+#define BP_AUDIOIN_DATA_HIGH        16
+#define BM_AUDIOIN_DATA_HIGH        0xffff0000
+#define BF_AUDIOIN_DATA_HIGH(v)     (((v) & 0xffff) << 16)
+#define BFM_AUDIOIN_DATA_HIGH(v)    BM_AUDIOIN_DATA_HIGH
+#define BF_AUDIOIN_DATA_HIGH_V(e)   BF_AUDIOIN_DATA_HIGH(BV_AUDIOIN_DATA_HIGH__##e)
+#define BFM_AUDIOIN_DATA_HIGH_V(v)  BM_AUDIOIN_DATA_HIGH
+#define BP_AUDIOIN_DATA_LOW         0
+#define BM_AUDIOIN_DATA_LOW         0xffff
+#define BF_AUDIOIN_DATA_LOW(v)      (((v) & 0xffff) << 0)
+#define BFM_AUDIOIN_DATA_LOW(v)     BM_AUDIOIN_DATA_LOW
+#define BF_AUDIOIN_DATA_LOW_V(e)    BF_AUDIOIN_DATA_LOW(BV_AUDIOIN_DATA_LOW__##e)
+#define BFM_AUDIOIN_DATA_LOW_V(v)   BM_AUDIOIN_DATA_LOW
+
+#endif /* __HEADERGEN_IMX233_AUDIOIN_H__*/
diff --git a/firmware/target/arm/imx233/regs/imx233/audioout.h b/firmware/target/arm/imx233/regs/imx233/audioout.h
new file mode 100644
index 0000000000..9b7d9ba119
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/imx233/audioout.h
@@ -0,0 +1,1313 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * imx233 version: 2.4.0
+ * imx233 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_IMX233_AUDIOOUT_H__
+#define __HEADERGEN_IMX233_AUDIOOUT_H__
+
+#define HW_AUDIOOUT_CTRL                            HW(AUDIOOUT_CTRL)
+#define HWA_AUDIOOUT_CTRL                           (0x80048000 + 0x0)
+#define HWT_AUDIOOUT_CTRL                           HWIO_32_RW
+#define HWN_AUDIOOUT_CTRL                           AUDIOOUT_CTRL
+#define HWI_AUDIOOUT_CTRL                           
+#define HW_AUDIOOUT_CTRL_SET                        HW(AUDIOOUT_CTRL_SET)
+#define HWA_AUDIOOUT_CTRL_SET                       (HWA_AUDIOOUT_CTRL + 0x4)
+#define HWT_AUDIOOUT_CTRL_SET                       HWIO_32_WO
+#define HWN_AUDIOOUT_CTRL_SET                       AUDIOOUT_CTRL
+#define HWI_AUDIOOUT_CTRL_SET                       
+#define HW_AUDIOOUT_CTRL_CLR                        HW(AUDIOOUT_CTRL_CLR)
+#define HWA_AUDIOOUT_CTRL_CLR                       (HWA_AUDIOOUT_CTRL + 0x8)
+#define HWT_AUDIOOUT_CTRL_CLR                       HWIO_32_WO
+#define HWN_AUDIOOUT_CTRL_CLR                       AUDIOOUT_CTRL
+#define HWI_AUDIOOUT_CTRL_CLR                       
+#define HW_AUDIOOUT_CTRL_TOG                        HW(AUDIOOUT_CTRL_TOG)
+#define HWA_AUDIOOUT_CTRL_TOG                       (HWA_AUDIOOUT_CTRL + 0xc)
+#define HWT_AUDIOOUT_CTRL_TOG                       HWIO_32_WO
+#define HWN_AUDIOOUT_CTRL_TOG                       AUDIOOUT_CTRL
+#define HWI_AUDIOOUT_CTRL_TOG                       
+#define BP_AUDIOOUT_CTRL_SFTRST                     31
+#define BM_AUDIOOUT_CTRL_SFTRST                     0x80000000
+#define BF_AUDIOOUT_CTRL_SFTRST(v)                  (((v) & 0x1) << 31)
+#define BFM_AUDIOOUT_CTRL_SFTRST(v)                 BM_AUDIOOUT_CTRL_SFTRST
+#define BF_AUDIOOUT_CTRL_SFTRST_V(e)                BF_AUDIOOUT_CTRL_SFTRST(BV_AUDIOOUT_CTRL_SFTRST__##e)
+#define BFM_AUDIOOUT_CTRL_SFTRST_V(v)               BM_AUDIOOUT_CTRL_SFTRST
+#define BP_AUDIOOUT_CTRL_CLKGATE                    30
+#define BM_AUDIOOUT_CTRL_CLKGATE                    0x40000000
+#define BF_AUDIOOUT_CTRL_CLKGATE(v)                 (((v) & 0x1) << 30)
+#define BFM_AUDIOOUT_CTRL_CLKGATE(v)                BM_AUDIOOUT_CTRL_CLKGATE
+#define BF_AUDIOOUT_CTRL_CLKGATE_V(e)               BF_AUDIOOUT_CTRL_CLKGATE(BV_AUDIOOUT_CTRL_CLKGATE__##e)
+#define BFM_AUDIOOUT_CTRL_CLKGATE_V(v)              BM_AUDIOOUT_CTRL_CLKGATE
+#define BP_AUDIOOUT_CTRL_RSRVD4                     21
+#define BM_AUDIOOUT_CTRL_RSRVD4                     0x3fe00000
+#define BF_AUDIOOUT_CTRL_RSRVD4(v)                  (((v) & 0x1ff) << 21)
+#define BFM_AUDIOOUT_CTRL_RSRVD4(v)                 BM_AUDIOOUT_CTRL_RSRVD4
+#define BF_AUDIOOUT_CTRL_RSRVD4_V(e)                BF_AUDIOOUT_CTRL_RSRVD4(BV_AUDIOOUT_CTRL_RSRVD4__##e)
+#define BFM_AUDIOOUT_CTRL_RSRVD4_V(v)               BM_AUDIOOUT_CTRL_RSRVD4
+#define BP_AUDIOOUT_CTRL_DMAWAIT_COUNT              16
+#define BM_AUDIOOUT_CTRL_DMAWAIT_COUNT              0x1f0000
+#define BF_AUDIOOUT_CTRL_DMAWAIT_COUNT(v)           (((v) & 0x1f) << 16)
+#define BFM_AUDIOOUT_CTRL_DMAWAIT_COUNT(v)          BM_AUDIOOUT_CTRL_DMAWAIT_COUNT
+#define BF_AUDIOOUT_CTRL_DMAWAIT_COUNT_V(e)         BF_AUDIOOUT_CTRL_DMAWAIT_COUNT(BV_AUDIOOUT_CTRL_DMAWAIT_COUNT__##e)
+#define BFM_AUDIOOUT_CTRL_DMAWAIT_COUNT_V(v)        BM_AUDIOOUT_CTRL_DMAWAIT_COUNT
+#define BP_AUDIOOUT_CTRL_RSRVD3                     15
+#define BM_AUDIOOUT_CTRL_RSRVD3                     0x8000
+#define BF_AUDIOOUT_CTRL_RSRVD3(v)                  (((v) & 0x1) << 15)
+#define BFM_AUDIOOUT_CTRL_RSRVD3(v)                 BM_AUDIOOUT_CTRL_RSRVD3
+#define BF_AUDIOOUT_CTRL_RSRVD3_V(e)                BF_AUDIOOUT_CTRL_RSRVD3(BV_AUDIOOUT_CTRL_RSRVD3__##e)
+#define BFM_AUDIOOUT_CTRL_RSRVD3_V(v)               BM_AUDIOOUT_CTRL_RSRVD3
+#define BP_AUDIOOUT_CTRL_LR_SWAP                    14
+#define BM_AUDIOOUT_CTRL_LR_SWAP                    0x4000
+#define BF_AUDIOOUT_CTRL_LR_SWAP(v)                 (((v) & 0x1) << 14)
+#define BFM_AUDIOOUT_CTRL_LR_SWAP(v)                BM_AUDIOOUT_CTRL_LR_SWAP
+#define BF_AUDIOOUT_CTRL_LR_SWAP_V(e)               BF_AUDIOOUT_CTRL_LR_SWAP(BV_AUDIOOUT_CTRL_LR_SWAP__##e)
+#define BFM_AUDIOOUT_CTRL_LR_SWAP_V(v)              BM_AUDIOOUT_CTRL_LR_SWAP
+#define BP_AUDIOOUT_CTRL_EDGE_SYNC                  13
+#define BM_AUDIOOUT_CTRL_EDGE_SYNC                  0x2000
+#define BF_AUDIOOUT_CTRL_EDGE_SYNC(v)               (((v) & 0x1) << 13)
+#define BFM_AUDIOOUT_CTRL_EDGE_SYNC(v)              BM_AUDIOOUT_CTRL_EDGE_SYNC
+#define BF_AUDIOOUT_CTRL_EDGE_SYNC_V(e)             BF_AUDIOOUT_CTRL_EDGE_SYNC(BV_AUDIOOUT_CTRL_EDGE_SYNC__##e)
+#define BFM_AUDIOOUT_CTRL_EDGE_SYNC_V(v)            BM_AUDIOOUT_CTRL_EDGE_SYNC
+#define BP_AUDIOOUT_CTRL_INVERT_1BIT                12
+#define BM_AUDIOOUT_CTRL_INVERT_1BIT                0x1000
+#define BF_AUDIOOUT_CTRL_INVERT_1BIT(v)             (((v) & 0x1) << 12)
+#define BFM_AUDIOOUT_CTRL_INVERT_1BIT(v)            BM_AUDIOOUT_CTRL_INVERT_1BIT
+#define BF_AUDIOOUT_CTRL_INVERT_1BIT_V(e)           BF_AUDIOOUT_CTRL_INVERT_1BIT(BV_AUDIOOUT_CTRL_INVERT_1BIT__##e)
+#define BFM_AUDIOOUT_CTRL_INVERT_1BIT_V(v)          BM_AUDIOOUT_CTRL_INVERT_1BIT
+#define BP_AUDIOOUT_CTRL_RSRVD2                     10
+#define BM_AUDIOOUT_CTRL_RSRVD2                     0xc00
+#define BF_AUDIOOUT_CTRL_RSRVD2(v)                  (((v) & 0x3) << 10)
+#define BFM_AUDIOOUT_CTRL_RSRVD2(v)                 BM_AUDIOOUT_CTRL_RSRVD2
+#define BF_AUDIOOUT_CTRL_RSRVD2_V(e)                BF_AUDIOOUT_CTRL_RSRVD2(BV_AUDIOOUT_CTRL_RSRVD2__##e)
+#define BFM_AUDIOOUT_CTRL_RSRVD2_V(v)               BM_AUDIOOUT_CTRL_RSRVD2
+#define BP_AUDIOOUT_CTRL_SS3D_EFFECT                8
+#define BM_AUDIOOUT_CTRL_SS3D_EFFECT                0x300
+#define BF_AUDIOOUT_CTRL_SS3D_EFFECT(v)             (((v) & 0x3) << 8)
+#define BFM_AUDIOOUT_CTRL_SS3D_EFFECT(v)            BM_AUDIOOUT_CTRL_SS3D_EFFECT
+#define BF_AUDIOOUT_CTRL_SS3D_EFFECT_V(e)           BF_AUDIOOUT_CTRL_SS3D_EFFECT(BV_AUDIOOUT_CTRL_SS3D_EFFECT__##e)
+#define BFM_AUDIOOUT_CTRL_SS3D_EFFECT_V(v)          BM_AUDIOOUT_CTRL_SS3D_EFFECT
+#define BP_AUDIOOUT_CTRL_RSRVD1                     7
+#define BM_AUDIOOUT_CTRL_RSRVD1                     0x80
+#define BF_AUDIOOUT_CTRL_RSRVD1(v)                  (((v) & 0x1) << 7)
+#define BFM_AUDIOOUT_CTRL_RSRVD1(v)                 BM_AUDIOOUT_CTRL_RSRVD1
+#define BF_AUDIOOUT_CTRL_RSRVD1_V(e)                BF_AUDIOOUT_CTRL_RSRVD1(BV_AUDIOOUT_CTRL_RSRVD1__##e)
+#define BFM_AUDIOOUT_CTRL_RSRVD1_V(v)               BM_AUDIOOUT_CTRL_RSRVD1
+#define BP_AUDIOOUT_CTRL_WORD_LENGTH                6
+#define BM_AUDIOOUT_CTRL_WORD_LENGTH                0x40
+#define BF_AUDIOOUT_CTRL_WORD_LENGTH(v)             (((v) & 0x1) << 6)
+#define BFM_AUDIOOUT_CTRL_WORD_LENGTH(v)            BM_AUDIOOUT_CTRL_WORD_LENGTH
+#define BF_AUDIOOUT_CTRL_WORD_LENGTH_V(e)           BF_AUDIOOUT_CTRL_WORD_LENGTH(BV_AUDIOOUT_CTRL_WORD_LENGTH__##e)
+#define BFM_AUDIOOUT_CTRL_WORD_LENGTH_V(v)          BM_AUDIOOUT_CTRL_WORD_LENGTH
+#define BP_AUDIOOUT_CTRL_DAC_ZERO_ENABLE            5
+#define BM_AUDIOOUT_CTRL_DAC_ZERO_ENABLE            0x20
+#define BF_AUDIOOUT_CTRL_DAC_ZERO_ENABLE(v)         (((v) & 0x1) << 5)
+#define BFM_AUDIOOUT_CTRL_DAC_ZERO_ENABLE(v)        BM_AUDIOOUT_CTRL_DAC_ZERO_ENABLE
+#define BF_AUDIOOUT_CTRL_DAC_ZERO_ENABLE_V(e)       BF_AUDIOOUT_CTRL_DAC_ZERO_ENABLE(BV_AUDIOOUT_CTRL_DAC_ZERO_ENABLE__##e)
+#define BFM_AUDIOOUT_CTRL_DAC_ZERO_ENABLE_V(v)      BM_AUDIOOUT_CTRL_DAC_ZERO_ENABLE
+#define BP_AUDIOOUT_CTRL_LOOPBACK                   4
+#define BM_AUDIOOUT_CTRL_LOOPBACK                   0x10
+#define BF_AUDIOOUT_CTRL_LOOPBACK(v)                (((v) & 0x1) << 4)
+#define BFM_AUDIOOUT_CTRL_LOOPBACK(v)               BM_AUDIOOUT_CTRL_LOOPBACK
+#define BF_AUDIOOUT_CTRL_LOOPBACK_V(e)              BF_AUDIOOUT_CTRL_LOOPBACK(BV_AUDIOOUT_CTRL_LOOPBACK__##e)
+#define BFM_AUDIOOUT_CTRL_LOOPBACK_V(v)             BM_AUDIOOUT_CTRL_LOOPBACK
+#define BP_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ         3
+#define BM_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ         0x8
+#define BF_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ(v)      (((v) & 0x1) << 3)
+#define BFM_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ(v)     BM_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ
+#define BF_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ_V(e)    BF_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ(BV_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ__##e)
+#define BFM_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ_V(v)   BM_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ
+#define BP_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ          2
+#define BM_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ          0x4
+#define BF_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ(v)       (((v) & 0x1) << 2)
+#define BFM_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ(v)      BM_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ
+#define BF_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ_V(e)     BF_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ(BV_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ__##e)
+#define BFM_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ_V(v)    BM_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ
+#define BP_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN          1
+#define BM_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN          0x2
+#define BF_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN(v)       (((v) & 0x1) << 1)
+#define BFM_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN(v)      BM_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN
+#define BF_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN_V(e)     BF_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN(BV_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN__##e)
+#define BFM_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN_V(v)    BM_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN
+#define BP_AUDIOOUT_CTRL_RUN                        0
+#define BM_AUDIOOUT_CTRL_RUN                        0x1
+#define BF_AUDIOOUT_CTRL_RUN(v)                     (((v) & 0x1) << 0)
+#define BFM_AUDIOOUT_CTRL_RUN(v)                    BM_AUDIOOUT_CTRL_RUN
+#define BF_AUDIOOUT_CTRL_RUN_V(e)                   BF_AUDIOOUT_CTRL_RUN(BV_AUDIOOUT_CTRL_RUN__##e)
+#define BFM_AUDIOOUT_CTRL_RUN_V(v)                  BM_AUDIOOUT_CTRL_RUN
+
+#define HW_AUDIOOUT_STAT                    HW(AUDIOOUT_STAT)
+#define HWA_AUDIOOUT_STAT                   (0x80048000 + 0x10)
+#define HWT_AUDIOOUT_STAT                   HWIO_32_RW
+#define HWN_AUDIOOUT_STAT                   AUDIOOUT_STAT
+#define HWI_AUDIOOUT_STAT                   
+#define HW_AUDIOOUT_STAT_SET                HW(AUDIOOUT_STAT_SET)
+#define HWA_AUDIOOUT_STAT_SET               (HWA_AUDIOOUT_STAT + 0x4)
+#define HWT_AUDIOOUT_STAT_SET               HWIO_32_WO
+#define HWN_AUDIOOUT_STAT_SET               AUDIOOUT_STAT
+#define HWI_AUDIOOUT_STAT_SET               
+#define HW_AUDIOOUT_STAT_CLR                HW(AUDIOOUT_STAT_CLR)
+#define HWA_AUDIOOUT_STAT_CLR               (HWA_AUDIOOUT_STAT + 0x8)
+#define HWT_AUDIOOUT_STAT_CLR               HWIO_32_WO
+#define HWN_AUDIOOUT_STAT_CLR               AUDIOOUT_STAT
+#define HWI_AUDIOOUT_STAT_CLR               
+#define HW_AUDIOOUT_STAT_TOG                HW(AUDIOOUT_STAT_TOG)
+#define HWA_AUDIOOUT_STAT_TOG               (HWA_AUDIOOUT_STAT + 0xc)
+#define HWT_AUDIOOUT_STAT_TOG               HWIO_32_WO
+#define HWN_AUDIOOUT_STAT_TOG               AUDIOOUT_STAT
+#define HWI_AUDIOOUT_STAT_TOG               
+#define BP_AUDIOOUT_STAT_DAC_PRESENT        31
+#define BM_AUDIOOUT_STAT_DAC_PRESENT        0x80000000
+#define BF_AUDIOOUT_STAT_DAC_PRESENT(v)     (((v) & 0x1) << 31)
+#define BFM_AUDIOOUT_STAT_DAC_PRESENT(v)    BM_AUDIOOUT_STAT_DAC_PRESENT
+#define BF_AUDIOOUT_STAT_DAC_PRESENT_V(e)   BF_AUDIOOUT_STAT_DAC_PRESENT(BV_AUDIOOUT_STAT_DAC_PRESENT__##e)
+#define BFM_AUDIOOUT_STAT_DAC_PRESENT_V(v)  BM_AUDIOOUT_STAT_DAC_PRESENT
+#define BP_AUDIOOUT_STAT_RSRVD1             0
+#define BM_AUDIOOUT_STAT_RSRVD1             0x7fffffff
+#define BF_AUDIOOUT_STAT_RSRVD1(v)          (((v) & 0x7fffffff) << 0)
+#define BFM_AUDIOOUT_STAT_RSRVD1(v)         BM_AUDIOOUT_STAT_RSRVD1
+#define BF_AUDIOOUT_STAT_RSRVD1_V(e)        BF_AUDIOOUT_STAT_RSRVD1(BV_AUDIOOUT_STAT_RSRVD1__##e)
+#define BFM_AUDIOOUT_STAT_RSRVD1_V(v)       BM_AUDIOOUT_STAT_RSRVD1
+
+#define HW_AUDIOOUT_DACSRR                          HW(AUDIOOUT_DACSRR)
+#define HWA_AUDIOOUT_DACSRR                         (0x80048000 + 0x20)
+#define HWT_AUDIOOUT_DACSRR                         HWIO_32_RW
+#define HWN_AUDIOOUT_DACSRR                         AUDIOOUT_DACSRR
+#define HWI_AUDIOOUT_DACSRR                         
+#define HW_AUDIOOUT_DACSRR_SET                      HW(AUDIOOUT_DACSRR_SET)
+#define HWA_AUDIOOUT_DACSRR_SET                     (HWA_AUDIOOUT_DACSRR + 0x4)
+#define HWT_AUDIOOUT_DACSRR_SET                     HWIO_32_WO
+#define HWN_AUDIOOUT_DACSRR_SET                     AUDIOOUT_DACSRR
+#define HWI_AUDIOOUT_DACSRR_SET                     
+#define HW_AUDIOOUT_DACSRR_CLR                      HW(AUDIOOUT_DACSRR_CLR)
+#define HWA_AUDIOOUT_DACSRR_CLR                     (HWA_AUDIOOUT_DACSRR + 0x8)
+#define HWT_AUDIOOUT_DACSRR_CLR                     HWIO_32_WO
+#define HWN_AUDIOOUT_DACSRR_CLR                     AUDIOOUT_DACSRR
+#define HWI_AUDIOOUT_DACSRR_CLR                     
+#define HW_AUDIOOUT_DACSRR_TOG                      HW(AUDIOOUT_DACSRR_TOG)
+#define HWA_AUDIOOUT_DACSRR_TOG                     (HWA_AUDIOOUT_DACSRR + 0xc)
+#define HWT_AUDIOOUT_DACSRR_TOG                     HWIO_32_WO
+#define HWN_AUDIOOUT_DACSRR_TOG                     AUDIOOUT_DACSRR
+#define HWI_AUDIOOUT_DACSRR_TOG                     
+#define BP_AUDIOOUT_DACSRR_OSR                      31
+#define BM_AUDIOOUT_DACSRR_OSR                      0x80000000
+#define BV_AUDIOOUT_DACSRR_OSR__OSR6                0x0
+#define BV_AUDIOOUT_DACSRR_OSR__OSR12               0x1
+#define BF_AUDIOOUT_DACSRR_OSR(v)                   (((v) & 0x1) << 31)
+#define BFM_AUDIOOUT_DACSRR_OSR(v)                  BM_AUDIOOUT_DACSRR_OSR
+#define BF_AUDIOOUT_DACSRR_OSR_V(e)                 BF_AUDIOOUT_DACSRR_OSR(BV_AUDIOOUT_DACSRR_OSR__##e)
+#define BFM_AUDIOOUT_DACSRR_OSR_V(v)                BM_AUDIOOUT_DACSRR_OSR
+#define BP_AUDIOOUT_DACSRR_BASEMULT                 28
+#define BM_AUDIOOUT_DACSRR_BASEMULT                 0x70000000
+#define BV_AUDIOOUT_DACSRR_BASEMULT__SINGLE_RATE    0x1
+#define BV_AUDIOOUT_DACSRR_BASEMULT__DOUBLE_RATE    0x2
+#define BV_AUDIOOUT_DACSRR_BASEMULT__QUAD_RATE      0x4
+#define BF_AUDIOOUT_DACSRR_BASEMULT(v)              (((v) & 0x7) << 28)
+#define BFM_AUDIOOUT_DACSRR_BASEMULT(v)             BM_AUDIOOUT_DACSRR_BASEMULT
+#define BF_AUDIOOUT_DACSRR_BASEMULT_V(e)            BF_AUDIOOUT_DACSRR_BASEMULT(BV_AUDIOOUT_DACSRR_BASEMULT__##e)
+#define BFM_AUDIOOUT_DACSRR_BASEMULT_V(v)           BM_AUDIOOUT_DACSRR_BASEMULT
+#define BP_AUDIOOUT_DACSRR_RSRVD2                   27
+#define BM_AUDIOOUT_DACSRR_RSRVD2                   0x8000000
+#define BF_AUDIOOUT_DACSRR_RSRVD2(v)                (((v) & 0x1) << 27)
+#define BFM_AUDIOOUT_DACSRR_RSRVD2(v)               BM_AUDIOOUT_DACSRR_RSRVD2
+#define BF_AUDIOOUT_DACSRR_RSRVD2_V(e)              BF_AUDIOOUT_DACSRR_RSRVD2(BV_AUDIOOUT_DACSRR_RSRVD2__##e)
+#define BFM_AUDIOOUT_DACSRR_RSRVD2_V(v)             BM_AUDIOOUT_DACSRR_RSRVD2
+#define BP_AUDIOOUT_DACSRR_SRC_HOLD                 24
+#define BM_AUDIOOUT_DACSRR_SRC_HOLD                 0x7000000
+#define BF_AUDIOOUT_DACSRR_SRC_HOLD(v)              (((v) & 0x7) << 24)
+#define BFM_AUDIOOUT_DACSRR_SRC_HOLD(v)             BM_AUDIOOUT_DACSRR_SRC_HOLD
+#define BF_AUDIOOUT_DACSRR_SRC_HOLD_V(e)            BF_AUDIOOUT_DACSRR_SRC_HOLD(BV_AUDIOOUT_DACSRR_SRC_HOLD__##e)
+#define BFM_AUDIOOUT_DACSRR_SRC_HOLD_V(v)           BM_AUDIOOUT_DACSRR_SRC_HOLD
+#define BP_AUDIOOUT_DACSRR_RSRVD1                   21
+#define BM_AUDIOOUT_DACSRR_RSRVD1                   0xe00000
+#define BF_AUDIOOUT_DACSRR_RSRVD1(v)                (((v) & 0x7) << 21)
+#define BFM_AUDIOOUT_DACSRR_RSRVD1(v)               BM_AUDIOOUT_DACSRR_RSRVD1
+#define BF_AUDIOOUT_DACSRR_RSRVD1_V(e)              BF_AUDIOOUT_DACSRR_RSRVD1(BV_AUDIOOUT_DACSRR_RSRVD1__##e)
+#define BFM_AUDIOOUT_DACSRR_RSRVD1_V(v)             BM_AUDIOOUT_DACSRR_RSRVD1
+#define BP_AUDIOOUT_DACSRR_SRC_INT                  16
+#define BM_AUDIOOUT_DACSRR_SRC_INT                  0x1f0000
+#define BF_AUDIOOUT_DACSRR_SRC_INT(v)               (((v) & 0x1f) << 16)
+#define BFM_AUDIOOUT_DACSRR_SRC_INT(v)              BM_AUDIOOUT_DACSRR_SRC_INT
+#define BF_AUDIOOUT_DACSRR_SRC_INT_V(e)             BF_AUDIOOUT_DACSRR_SRC_INT(BV_AUDIOOUT_DACSRR_SRC_INT__##e)
+#define BFM_AUDIOOUT_DACSRR_SRC_INT_V(v)            BM_AUDIOOUT_DACSRR_SRC_INT
+#define BP_AUDIOOUT_DACSRR_RSRVD0                   13
+#define BM_AUDIOOUT_DACSRR_RSRVD0                   0xe000
+#define BF_AUDIOOUT_DACSRR_RSRVD0(v)                (((v) & 0x7) << 13)
+#define BFM_AUDIOOUT_DACSRR_RSRVD0(v)               BM_AUDIOOUT_DACSRR_RSRVD0
+#define BF_AUDIOOUT_DACSRR_RSRVD0_V(e)              BF_AUDIOOUT_DACSRR_RSRVD0(BV_AUDIOOUT_DACSRR_RSRVD0__##e)
+#define BFM_AUDIOOUT_DACSRR_RSRVD0_V(v)             BM_AUDIOOUT_DACSRR_RSRVD0
+#define BP_AUDIOOUT_DACSRR_SRC_FRAC                 0
+#define BM_AUDIOOUT_DACSRR_SRC_FRAC                 0x1fff
+#define BF_AUDIOOUT_DACSRR_SRC_FRAC(v)              (((v) & 0x1fff) << 0)
+#define BFM_AUDIOOUT_DACSRR_SRC_FRAC(v)             BM_AUDIOOUT_DACSRR_SRC_FRAC
+#define BF_AUDIOOUT_DACSRR_SRC_FRAC_V(e)            BF_AUDIOOUT_DACSRR_SRC_FRAC(BV_AUDIOOUT_DACSRR_SRC_FRAC__##e)
+#define BFM_AUDIOOUT_DACSRR_SRC_FRAC_V(v)           BM_AUDIOOUT_DACSRR_SRC_FRAC
+
+#define HW_AUDIOOUT_DACVOLUME                           HW(AUDIOOUT_DACVOLUME)
+#define HWA_AUDIOOUT_DACVOLUME                          (0x80048000 + 0x30)
+#define HWT_AUDIOOUT_DACVOLUME                          HWIO_32_RW
+#define HWN_AUDIOOUT_DACVOLUME                          AUDIOOUT_DACVOLUME
+#define HWI_AUDIOOUT_DACVOLUME                          
+#define HW_AUDIOOUT_DACVOLUME_SET                       HW(AUDIOOUT_DACVOLUME_SET)
+#define HWA_AUDIOOUT_DACVOLUME_SET                      (HWA_AUDIOOUT_DACVOLUME + 0x4)
+#define HWT_AUDIOOUT_DACVOLUME_SET                      HWIO_32_WO
+#define HWN_AUDIOOUT_DACVOLUME_SET                      AUDIOOUT_DACVOLUME
+#define HWI_AUDIOOUT_DACVOLUME_SET                      
+#define HW_AUDIOOUT_DACVOLUME_CLR                       HW(AUDIOOUT_DACVOLUME_CLR)
+#define HWA_AUDIOOUT_DACVOLUME_CLR                      (HWA_AUDIOOUT_DACVOLUME + 0x8)
+#define HWT_AUDIOOUT_DACVOLUME_CLR                      HWIO_32_WO
+#define HWN_AUDIOOUT_DACVOLUME_CLR                      AUDIOOUT_DACVOLUME
+#define HWI_AUDIOOUT_DACVOLUME_CLR                      
+#define HW_AUDIOOUT_DACVOLUME_TOG                       HW(AUDIOOUT_DACVOLUME_TOG)
+#define HWA_AUDIOOUT_DACVOLUME_TOG                      (HWA_AUDIOOUT_DACVOLUME + 0xc)
+#define HWT_AUDIOOUT_DACVOLUME_TOG                      HWIO_32_WO
+#define HWN_AUDIOOUT_DACVOLUME_TOG                      AUDIOOUT_DACVOLUME
+#define HWI_AUDIOOUT_DACVOLUME_TOG                      
+#define BP_AUDIOOUT_DACVOLUME_RSRVD4                    29
+#define BM_AUDIOOUT_DACVOLUME_RSRVD4                    0xe0000000
+#define BF_AUDIOOUT_DACVOLUME_RSRVD4(v)                 (((v) & 0x7) << 29)
+#define BFM_AUDIOOUT_DACVOLUME_RSRVD4(v)                BM_AUDIOOUT_DACVOLUME_RSRVD4
+#define BF_AUDIOOUT_DACVOLUME_RSRVD4_V(e)               BF_AUDIOOUT_DACVOLUME_RSRVD4(BV_AUDIOOUT_DACVOLUME_RSRVD4__##e)
+#define BFM_AUDIOOUT_DACVOLUME_RSRVD4_V(v)              BM_AUDIOOUT_DACVOLUME_RSRVD4
+#define BP_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT        28
+#define BM_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT        0x10000000
+#define BF_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT(v)     (((v) & 0x1) << 28)
+#define BFM_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT(v)    BM_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT
+#define BF_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT_V(e)   BF_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT(BV_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT__##e)
+#define BFM_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT_V(v)  BM_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT
+#define BP_AUDIOOUT_DACVOLUME_RSRVD3                    26
+#define BM_AUDIOOUT_DACVOLUME_RSRVD3                    0xc000000
+#define BF_AUDIOOUT_DACVOLUME_RSRVD3(v)                 (((v) & 0x3) << 26)
+#define BFM_AUDIOOUT_DACVOLUME_RSRVD3(v)                BM_AUDIOOUT_DACVOLUME_RSRVD3
+#define BF_AUDIOOUT_DACVOLUME_RSRVD3_V(e)               BF_AUDIOOUT_DACVOLUME_RSRVD3(BV_AUDIOOUT_DACVOLUME_RSRVD3__##e)
+#define BFM_AUDIOOUT_DACVOLUME_RSRVD3_V(v)              BM_AUDIOOUT_DACVOLUME_RSRVD3
+#define BP_AUDIOOUT_DACVOLUME_EN_ZCD                    25
+#define BM_AUDIOOUT_DACVOLUME_EN_ZCD                    0x2000000
+#define BF_AUDIOOUT_DACVOLUME_EN_ZCD(v)                 (((v) & 0x1) << 25)
+#define BFM_AUDIOOUT_DACVOLUME_EN_ZCD(v)                BM_AUDIOOUT_DACVOLUME_EN_ZCD
+#define BF_AUDIOOUT_DACVOLUME_EN_ZCD_V(e)               BF_AUDIOOUT_DACVOLUME_EN_ZCD(BV_AUDIOOUT_DACVOLUME_EN_ZCD__##e)
+#define BFM_AUDIOOUT_DACVOLUME_EN_ZCD_V(v)              BM_AUDIOOUT_DACVOLUME_EN_ZCD
+#define BP_AUDIOOUT_DACVOLUME_MUTE_LEFT                 24
+#define BM_AUDIOOUT_DACVOLUME_MUTE_LEFT                 0x1000000
+#define BF_AUDIOOUT_DACVOLUME_MUTE_LEFT(v)              (((v) & 0x1) << 24)
+#define BFM_AUDIOOUT_DACVOLUME_MUTE_LEFT(v)             BM_AUDIOOUT_DACVOLUME_MUTE_LEFT
+#define BF_AUDIOOUT_DACVOLUME_MUTE_LEFT_V(e)            BF_AUDIOOUT_DACVOLUME_MUTE_LEFT(BV_AUDIOOUT_DACVOLUME_MUTE_LEFT__##e)
+#define BFM_AUDIOOUT_DACVOLUME_MUTE_LEFT_V(v)           BM_AUDIOOUT_DACVOLUME_MUTE_LEFT
+#define BP_AUDIOOUT_DACVOLUME_VOLUME_LEFT               16
+#define BM_AUDIOOUT_DACVOLUME_VOLUME_LEFT               0xff0000
+#define BF_AUDIOOUT_DACVOLUME_VOLUME_LEFT(v)            (((v) & 0xff) << 16)
+#define BFM_AUDIOOUT_DACVOLUME_VOLUME_LEFT(v)           BM_AUDIOOUT_DACVOLUME_VOLUME_LEFT
+#define BF_AUDIOOUT_DACVOLUME_VOLUME_LEFT_V(e)          BF_AUDIOOUT_DACVOLUME_VOLUME_LEFT(BV_AUDIOOUT_DACVOLUME_VOLUME_LEFT__##e)
+#define BFM_AUDIOOUT_DACVOLUME_VOLUME_LEFT_V(v)         BM_AUDIOOUT_DACVOLUME_VOLUME_LEFT
+#define BP_AUDIOOUT_DACVOLUME_RSRVD2                    13
+#define BM_AUDIOOUT_DACVOLUME_RSRVD2                    0xe000
+#define BF_AUDIOOUT_DACVOLUME_RSRVD2(v)                 (((v) & 0x7) << 13)
+#define BFM_AUDIOOUT_DACVOLUME_RSRVD2(v)                BM_AUDIOOUT_DACVOLUME_RSRVD2
+#define BF_AUDIOOUT_DACVOLUME_RSRVD2_V(e)               BF_AUDIOOUT_DACVOLUME_RSRVD2(BV_AUDIOOUT_DACVOLUME_RSRVD2__##e)
+#define BFM_AUDIOOUT_DACVOLUME_RSRVD2_V(v)              BM_AUDIOOUT_DACVOLUME_RSRVD2
+#define BP_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT       12
+#define BM_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT       0x1000
+#define BF_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT(v)    (((v) & 0x1) << 12)
+#define BFM_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT(v)   BM_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT
+#define BF_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT_V(e)  BF_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT(BV_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT__##e)
+#define BFM_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT_V(v) BM_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT
+#define BP_AUDIOOUT_DACVOLUME_RSRVD1                    9
+#define BM_AUDIOOUT_DACVOLUME_RSRVD1                    0xe00
+#define BF_AUDIOOUT_DACVOLUME_RSRVD1(v)                 (((v) & 0x7) << 9)
+#define BFM_AUDIOOUT_DACVOLUME_RSRVD1(v)                BM_AUDIOOUT_DACVOLUME_RSRVD1
+#define BF_AUDIOOUT_DACVOLUME_RSRVD1_V(e)               BF_AUDIOOUT_DACVOLUME_RSRVD1(BV_AUDIOOUT_DACVOLUME_RSRVD1__##e)
+#define BFM_AUDIOOUT_DACVOLUME_RSRVD1_V(v)              BM_AUDIOOUT_DACVOLUME_RSRVD1
+#define BP_AUDIOOUT_DACVOLUME_MUTE_RIGHT                8
+#define BM_AUDIOOUT_DACVOLUME_MUTE_RIGHT                0x100
+#define BF_AUDIOOUT_DACVOLUME_MUTE_RIGHT(v)             (((v) & 0x1) << 8)
+#define BFM_AUDIOOUT_DACVOLUME_MUTE_RIGHT(v)            BM_AUDIOOUT_DACVOLUME_MUTE_RIGHT
+#define BF_AUDIOOUT_DACVOLUME_MUTE_RIGHT_V(e)           BF_AUDIOOUT_DACVOLUME_MUTE_RIGHT(BV_AUDIOOUT_DACVOLUME_MUTE_RIGHT__##e)
+#define BFM_AUDIOOUT_DACVOLUME_MUTE_RIGHT_V(v)          BM_AUDIOOUT_DACVOLUME_MUTE_RIGHT
+#define BP_AUDIOOUT_DACVOLUME_VOLUME_RIGHT              0
+#define BM_AUDIOOUT_DACVOLUME_VOLUME_RIGHT              0xff
+#define BF_AUDIOOUT_DACVOLUME_VOLUME_RIGHT(v)           (((v) & 0xff) << 0)
+#define BFM_AUDIOOUT_DACVOLUME_VOLUME_RIGHT(v)          BM_AUDIOOUT_DACVOLUME_VOLUME_RIGHT
+#define BF_AUDIOOUT_DACVOLUME_VOLUME_RIGHT_V(e)         BF_AUDIOOUT_DACVOLUME_VOLUME_RIGHT(BV_AUDIOOUT_DACVOLUME_VOLUME_RIGHT__##e)
+#define BFM_AUDIOOUT_DACVOLUME_VOLUME_RIGHT_V(v)        BM_AUDIOOUT_DACVOLUME_VOLUME_RIGHT
+
+#define HW_AUDIOOUT_DACDEBUG                                    HW(AUDIOOUT_DACDEBUG)
+#define HWA_AUDIOOUT_DACDEBUG                                   (0x80048000 + 0x40)
+#define HWT_AUDIOOUT_DACDEBUG                                   HWIO_32_RW
+#define HWN_AUDIOOUT_DACDEBUG                                   AUDIOOUT_DACDEBUG
+#define HWI_AUDIOOUT_DACDEBUG                                   
+#define HW_AUDIOOUT_DACDEBUG_SET                                HW(AUDIOOUT_DACDEBUG_SET)
+#define HWA_AUDIOOUT_DACDEBUG_SET                               (HWA_AUDIOOUT_DACDEBUG + 0x4)
+#define HWT_AUDIOOUT_DACDEBUG_SET                               HWIO_32_WO
+#define HWN_AUDIOOUT_DACDEBUG_SET                               AUDIOOUT_DACDEBUG
+#define HWI_AUDIOOUT_DACDEBUG_SET                               
+#define HW_AUDIOOUT_DACDEBUG_CLR                                HW(AUDIOOUT_DACDEBUG_CLR)
+#define HWA_AUDIOOUT_DACDEBUG_CLR                               (HWA_AUDIOOUT_DACDEBUG + 0x8)
+#define HWT_AUDIOOUT_DACDEBUG_CLR                               HWIO_32_WO
+#define HWN_AUDIOOUT_DACDEBUG_CLR                               AUDIOOUT_DACDEBUG
+#define HWI_AUDIOOUT_DACDEBUG_CLR                               
+#define HW_AUDIOOUT_DACDEBUG_TOG                                HW(AUDIOOUT_DACDEBUG_TOG)
+#define HWA_AUDIOOUT_DACDEBUG_TOG                               (HWA_AUDIOOUT_DACDEBUG + 0xc)
+#define HWT_AUDIOOUT_DACDEBUG_TOG                               HWIO_32_WO
+#define HWN_AUDIOOUT_DACDEBUG_TOG                               AUDIOOUT_DACDEBUG
+#define HWI_AUDIOOUT_DACDEBUG_TOG                               
+#define BP_AUDIOOUT_DACDEBUG_ENABLE_DACDMA                      31
+#define BM_AUDIOOUT_DACDEBUG_ENABLE_DACDMA                      0x80000000
+#define BF_AUDIOOUT_DACDEBUG_ENABLE_DACDMA(v)                   (((v) & 0x1) << 31)
+#define BFM_AUDIOOUT_DACDEBUG_ENABLE_DACDMA(v)                  BM_AUDIOOUT_DACDEBUG_ENABLE_DACDMA
+#define BF_AUDIOOUT_DACDEBUG_ENABLE_DACDMA_V(e)                 BF_AUDIOOUT_DACDEBUG_ENABLE_DACDMA(BV_AUDIOOUT_DACDEBUG_ENABLE_DACDMA__##e)
+#define BFM_AUDIOOUT_DACDEBUG_ENABLE_DACDMA_V(v)                BM_AUDIOOUT_DACDEBUG_ENABLE_DACDMA
+#define BP_AUDIOOUT_DACDEBUG_RSRVD2                             12
+#define BM_AUDIOOUT_DACDEBUG_RSRVD2                             0x7ffff000
+#define BF_AUDIOOUT_DACDEBUG_RSRVD2(v)                          (((v) & 0x7ffff) << 12)
+#define BFM_AUDIOOUT_DACDEBUG_RSRVD2(v)                         BM_AUDIOOUT_DACDEBUG_RSRVD2
+#define BF_AUDIOOUT_DACDEBUG_RSRVD2_V(e)                        BF_AUDIOOUT_DACDEBUG_RSRVD2(BV_AUDIOOUT_DACDEBUG_RSRVD2__##e)
+#define BFM_AUDIOOUT_DACDEBUG_RSRVD2_V(v)                       BM_AUDIOOUT_DACDEBUG_RSRVD2
+#define BP_AUDIOOUT_DACDEBUG_RAM_SS                             8
+#define BM_AUDIOOUT_DACDEBUG_RAM_SS                             0xf00
+#define BF_AUDIOOUT_DACDEBUG_RAM_SS(v)                          (((v) & 0xf) << 8)
+#define BFM_AUDIOOUT_DACDEBUG_RAM_SS(v)                         BM_AUDIOOUT_DACDEBUG_RAM_SS
+#define BF_AUDIOOUT_DACDEBUG_RAM_SS_V(e)                        BF_AUDIOOUT_DACDEBUG_RAM_SS(BV_AUDIOOUT_DACDEBUG_RAM_SS__##e)
+#define BFM_AUDIOOUT_DACDEBUG_RAM_SS_V(v)                       BM_AUDIOOUT_DACDEBUG_RAM_SS
+#define BP_AUDIOOUT_DACDEBUG_RSRVD1                             6
+#define BM_AUDIOOUT_DACDEBUG_RSRVD1                             0xc0
+#define BF_AUDIOOUT_DACDEBUG_RSRVD1(v)                          (((v) & 0x3) << 6)
+#define BFM_AUDIOOUT_DACDEBUG_RSRVD1(v)                         BM_AUDIOOUT_DACDEBUG_RSRVD1
+#define BF_AUDIOOUT_DACDEBUG_RSRVD1_V(e)                        BF_AUDIOOUT_DACDEBUG_RSRVD1(BV_AUDIOOUT_DACDEBUG_RSRVD1__##e)
+#define BFM_AUDIOOUT_DACDEBUG_RSRVD1_V(v)                       BM_AUDIOOUT_DACDEBUG_RSRVD1
+#define BP_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS           5
+#define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS           0x20
+#define BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS(v)        (((v) & 0x1) << 5)
+#define BFM_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS(v)       BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS
+#define BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS_V(e)      BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS(BV_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS__##e)
+#define BFM_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS_V(v)     BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS
+#define BP_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS           4
+#define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS           0x10
+#define BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS(v)        (((v) & 0x1) << 4)
+#define BFM_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS(v)       BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS
+#define BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS_V(e)      BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS(BV_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS__##e)
+#define BFM_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS_V(v)     BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS
+#define BP_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE          3
+#define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE          0x8
+#define BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE(v)       (((v) & 0x1) << 3)
+#define BFM_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE(v)      BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE
+#define BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE_V(e)     BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE(BV_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE__##e)
+#define BFM_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE_V(v)    BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE
+#define BP_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE          2
+#define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE          0x4
+#define BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE(v)       (((v) & 0x1) << 2)
+#define BFM_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE(v)      BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE
+#define BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE_V(e)     BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE(BV_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE__##e)
+#define BFM_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE_V(v)    BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE
+#define BP_AUDIOOUT_DACDEBUG_DMA_PREQ                           1
+#define BM_AUDIOOUT_DACDEBUG_DMA_PREQ                           0x2
+#define BF_AUDIOOUT_DACDEBUG_DMA_PREQ(v)                        (((v) & 0x1) << 1)
+#define BFM_AUDIOOUT_DACDEBUG_DMA_PREQ(v)                       BM_AUDIOOUT_DACDEBUG_DMA_PREQ
+#define BF_AUDIOOUT_DACDEBUG_DMA_PREQ_V(e)                      BF_AUDIOOUT_DACDEBUG_DMA_PREQ(BV_AUDIOOUT_DACDEBUG_DMA_PREQ__##e)
+#define BFM_AUDIOOUT_DACDEBUG_DMA_PREQ_V(v)                     BM_AUDIOOUT_DACDEBUG_DMA_PREQ
+#define BP_AUDIOOUT_DACDEBUG_FIFO_STATUS                        0
+#define BM_AUDIOOUT_DACDEBUG_FIFO_STATUS                        0x1
+#define BF_AUDIOOUT_DACDEBUG_FIFO_STATUS(v)                     (((v) & 0x1) << 0)
+#define BFM_AUDIOOUT_DACDEBUG_FIFO_STATUS(v)                    BM_AUDIOOUT_DACDEBUG_FIFO_STATUS
+#define BF_AUDIOOUT_DACDEBUG_FIFO_STATUS_V(e)                   BF_AUDIOOUT_DACDEBUG_FIFO_STATUS(BV_AUDIOOUT_DACDEBUG_FIFO_STATUS__##e)
+#define BFM_AUDIOOUT_DACDEBUG_FIFO_STATUS_V(v)                  BM_AUDIOOUT_DACDEBUG_FIFO_STATUS
+
+#define HW_AUDIOOUT_HPVOL                               HW(AUDIOOUT_HPVOL)
+#define HWA_AUDIOOUT_HPVOL                              (0x80048000 + 0x50)
+#define HWT_AUDIOOUT_HPVOL                              HWIO_32_RW
+#define HWN_AUDIOOUT_HPVOL                              AUDIOOUT_HPVOL
+#define HWI_AUDIOOUT_HPVOL                              
+#define HW_AUDIOOUT_HPVOL_SET                           HW(AUDIOOUT_HPVOL_SET)
+#define HWA_AUDIOOUT_HPVOL_SET                          (HWA_AUDIOOUT_HPVOL + 0x4)
+#define HWT_AUDIOOUT_HPVOL_SET                          HWIO_32_WO
+#define HWN_AUDIOOUT_HPVOL_SET                          AUDIOOUT_HPVOL
+#define HWI_AUDIOOUT_HPVOL_SET                          
+#define HW_AUDIOOUT_HPVOL_CLR                           HW(AUDIOOUT_HPVOL_CLR)
+#define HWA_AUDIOOUT_HPVOL_CLR                          (HWA_AUDIOOUT_HPVOL + 0x8)
+#define HWT_AUDIOOUT_HPVOL_CLR                          HWIO_32_WO
+#define HWN_AUDIOOUT_HPVOL_CLR                          AUDIOOUT_HPVOL
+#define HWI_AUDIOOUT_HPVOL_CLR                          
+#define HW_AUDIOOUT_HPVOL_TOG                           HW(AUDIOOUT_HPVOL_TOG)
+#define HWA_AUDIOOUT_HPVOL_TOG                          (HWA_AUDIOOUT_HPVOL + 0xc)
+#define HWT_AUDIOOUT_HPVOL_TOG                          HWIO_32_WO
+#define HWN_AUDIOOUT_HPVOL_TOG                          AUDIOOUT_HPVOL
+#define HWI_AUDIOOUT_HPVOL_TOG                          
+#define BP_AUDIOOUT_HPVOL_RSRVD5                        29
+#define BM_AUDIOOUT_HPVOL_RSRVD5                        0xe0000000
+#define BF_AUDIOOUT_HPVOL_RSRVD5(v)                     (((v) & 0x7) << 29)
+#define BFM_AUDIOOUT_HPVOL_RSRVD5(v)                    BM_AUDIOOUT_HPVOL_RSRVD5
+#define BF_AUDIOOUT_HPVOL_RSRVD5_V(e)                   BF_AUDIOOUT_HPVOL_RSRVD5(BV_AUDIOOUT_HPVOL_RSRVD5__##e)
+#define BFM_AUDIOOUT_HPVOL_RSRVD5_V(v)                  BM_AUDIOOUT_HPVOL_RSRVD5
+#define BP_AUDIOOUT_HPVOL_VOLUME_UPDATE_PENDING         28
+#define BM_AUDIOOUT_HPVOL_VOLUME_UPDATE_PENDING         0x10000000
+#define BF_AUDIOOUT_HPVOL_VOLUME_UPDATE_PENDING(v)      (((v) & 0x1) << 28)
+#define BFM_AUDIOOUT_HPVOL_VOLUME_UPDATE_PENDING(v)     BM_AUDIOOUT_HPVOL_VOLUME_UPDATE_PENDING
+#define BF_AUDIOOUT_HPVOL_VOLUME_UPDATE_PENDING_V(e)    BF_AUDIOOUT_HPVOL_VOLUME_UPDATE_PENDING(BV_AUDIOOUT_HPVOL_VOLUME_UPDATE_PENDING__##e)
+#define BFM_AUDIOOUT_HPVOL_VOLUME_UPDATE_PENDING_V(v)   BM_AUDIOOUT_HPVOL_VOLUME_UPDATE_PENDING
+#define BP_AUDIOOUT_HPVOL_RSRVD4                        26
+#define BM_AUDIOOUT_HPVOL_RSRVD4                        0xc000000
+#define BF_AUDIOOUT_HPVOL_RSRVD4(v)                     (((v) & 0x3) << 26)
+#define BFM_AUDIOOUT_HPVOL_RSRVD4(v)                    BM_AUDIOOUT_HPVOL_RSRVD4
+#define BF_AUDIOOUT_HPVOL_RSRVD4_V(e)                   BF_AUDIOOUT_HPVOL_RSRVD4(BV_AUDIOOUT_HPVOL_RSRVD4__##e)
+#define BFM_AUDIOOUT_HPVOL_RSRVD4_V(v)                  BM_AUDIOOUT_HPVOL_RSRVD4
+#define BP_AUDIOOUT_HPVOL_EN_MSTR_ZCD                   25
+#define BM_AUDIOOUT_HPVOL_EN_MSTR_ZCD                   0x2000000
+#define BF_AUDIOOUT_HPVOL_EN_MSTR_ZCD(v)                (((v) & 0x1) << 25)
+#define BFM_AUDIOOUT_HPVOL_EN_MSTR_ZCD(v)               BM_AUDIOOUT_HPVOL_EN_MSTR_ZCD
+#define BF_AUDIOOUT_HPVOL_EN_MSTR_ZCD_V(e)              BF_AUDIOOUT_HPVOL_EN_MSTR_ZCD(BV_AUDIOOUT_HPVOL_EN_MSTR_ZCD__##e)
+#define BFM_AUDIOOUT_HPVOL_EN_MSTR_ZCD_V(v)             BM_AUDIOOUT_HPVOL_EN_MSTR_ZCD
+#define BP_AUDIOOUT_HPVOL_MUTE                          24
+#define BM_AUDIOOUT_HPVOL_MUTE                          0x1000000
+#define BF_AUDIOOUT_HPVOL_MUTE(v)                       (((v) & 0x1) << 24)
+#define BFM_AUDIOOUT_HPVOL_MUTE(v)                      BM_AUDIOOUT_HPVOL_MUTE
+#define BF_AUDIOOUT_HPVOL_MUTE_V(e)                     BF_AUDIOOUT_HPVOL_MUTE(BV_AUDIOOUT_HPVOL_MUTE__##e)
+#define BFM_AUDIOOUT_HPVOL_MUTE_V(v)                    BM_AUDIOOUT_HPVOL_MUTE
+#define BP_AUDIOOUT_HPVOL_RSRVD3                        17
+#define BM_AUDIOOUT_HPVOL_RSRVD3                        0xfe0000
+#define BF_AUDIOOUT_HPVOL_RSRVD3(v)                     (((v) & 0x7f) << 17)
+#define BFM_AUDIOOUT_HPVOL_RSRVD3(v)                    BM_AUDIOOUT_HPVOL_RSRVD3
+#define BF_AUDIOOUT_HPVOL_RSRVD3_V(e)                   BF_AUDIOOUT_HPVOL_RSRVD3(BV_AUDIOOUT_HPVOL_RSRVD3__##e)
+#define BFM_AUDIOOUT_HPVOL_RSRVD3_V(v)                  BM_AUDIOOUT_HPVOL_RSRVD3
+#define BP_AUDIOOUT_HPVOL_SELECT                        16
+#define BM_AUDIOOUT_HPVOL_SELECT                        0x10000
+#define BF_AUDIOOUT_HPVOL_SELECT(v)                     (((v) & 0x1) << 16)
+#define BFM_AUDIOOUT_HPVOL_SELECT(v)                    BM_AUDIOOUT_HPVOL_SELECT
+#define BF_AUDIOOUT_HPVOL_SELECT_V(e)                   BF_AUDIOOUT_HPVOL_SELECT(BV_AUDIOOUT_HPVOL_SELECT__##e)
+#define BFM_AUDIOOUT_HPVOL_SELECT_V(v)                  BM_AUDIOOUT_HPVOL_SELECT
+#define BP_AUDIOOUT_HPVOL_RSRVD2                        15
+#define BM_AUDIOOUT_HPVOL_RSRVD2                        0x8000
+#define BF_AUDIOOUT_HPVOL_RSRVD2(v)                     (((v) & 0x1) << 15)
+#define BFM_AUDIOOUT_HPVOL_RSRVD2(v)                    BM_AUDIOOUT_HPVOL_RSRVD2
+#define BF_AUDIOOUT_HPVOL_RSRVD2_V(e)                   BF_AUDIOOUT_HPVOL_RSRVD2(BV_AUDIOOUT_HPVOL_RSRVD2__##e)
+#define BFM_AUDIOOUT_HPVOL_RSRVD2_V(v)                  BM_AUDIOOUT_HPVOL_RSRVD2
+#define BP_AUDIOOUT_HPVOL_VOL_LEFT                      8
+#define BM_AUDIOOUT_HPVOL_VOL_LEFT                      0x7f00
+#define BF_AUDIOOUT_HPVOL_VOL_LEFT(v)                   (((v) & 0x7f) << 8)
+#define BFM_AUDIOOUT_HPVOL_VOL_LEFT(v)                  BM_AUDIOOUT_HPVOL_VOL_LEFT
+#define BF_AUDIOOUT_HPVOL_VOL_LEFT_V(e)                 BF_AUDIOOUT_HPVOL_VOL_LEFT(BV_AUDIOOUT_HPVOL_VOL_LEFT__##e)
+#define BFM_AUDIOOUT_HPVOL_VOL_LEFT_V(v)                BM_AUDIOOUT_HPVOL_VOL_LEFT
+#define BP_AUDIOOUT_HPVOL_RSRVD1                        7
+#define BM_AUDIOOUT_HPVOL_RSRVD1                        0x80
+#define BF_AUDIOOUT_HPVOL_RSRVD1(v)                     (((v) & 0x1) << 7)
+#define BFM_AUDIOOUT_HPVOL_RSRVD1(v)                    BM_AUDIOOUT_HPVOL_RSRVD1
+#define BF_AUDIOOUT_HPVOL_RSRVD1_V(e)                   BF_AUDIOOUT_HPVOL_RSRVD1(BV_AUDIOOUT_HPVOL_RSRVD1__##e)
+#define BFM_AUDIOOUT_HPVOL_RSRVD1_V(v)                  BM_AUDIOOUT_HPVOL_RSRVD1
+#define BP_AUDIOOUT_HPVOL_VOL_RIGHT                     0
+#define BM_AUDIOOUT_HPVOL_VOL_RIGHT                     0x7f
+#define BF_AUDIOOUT_HPVOL_VOL_RIGHT(v)                  (((v) & 0x7f) << 0)
+#define BFM_AUDIOOUT_HPVOL_VOL_RIGHT(v)                 BM_AUDIOOUT_HPVOL_VOL_RIGHT
+#define BF_AUDIOOUT_HPVOL_VOL_RIGHT_V(e)                BF_AUDIOOUT_HPVOL_VOL_RIGHT(BV_AUDIOOUT_HPVOL_VOL_RIGHT__##e)
+#define BFM_AUDIOOUT_HPVOL_VOL_RIGHT_V(v)               BM_AUDIOOUT_HPVOL_VOL_RIGHT
+
+#define HW_AUDIOOUT_RESERVED                HW(AUDIOOUT_RESERVED)
+#define HWA_AUDIOOUT_RESERVED               (0x80048000 + 0x60)
+#define HWT_AUDIOOUT_RESERVED               HWIO_32_RW
+#define HWN_AUDIOOUT_RESERVED               AUDIOOUT_RESERVED
+#define HWI_AUDIOOUT_RESERVED               
+#define HW_AUDIOOUT_RESERVED_SET            HW(AUDIOOUT_RESERVED_SET)
+#define HWA_AUDIOOUT_RESERVED_SET           (HWA_AUDIOOUT_RESERVED + 0x4)
+#define HWT_AUDIOOUT_RESERVED_SET           HWIO_32_WO
+#define HWN_AUDIOOUT_RESERVED_SET           AUDIOOUT_RESERVED
+#define HWI_AUDIOOUT_RESERVED_SET           
+#define HW_AUDIOOUT_RESERVED_CLR            HW(AUDIOOUT_RESERVED_CLR)
+#define HWA_AUDIOOUT_RESERVED_CLR           (HWA_AUDIOOUT_RESERVED + 0x8)
+#define HWT_AUDIOOUT_RESERVED_CLR           HWIO_32_WO
+#define HWN_AUDIOOUT_RESERVED_CLR           AUDIOOUT_RESERVED
+#define HWI_AUDIOOUT_RESERVED_CLR           
+#define HW_AUDIOOUT_RESERVED_TOG            HW(AUDIOOUT_RESERVED_TOG)
+#define HWA_AUDIOOUT_RESERVED_TOG           (HWA_AUDIOOUT_RESERVED + 0xc)
+#define HWT_AUDIOOUT_RESERVED_TOG           HWIO_32_WO
+#define HWN_AUDIOOUT_RESERVED_TOG           AUDIOOUT_RESERVED
+#define HWI_AUDIOOUT_RESERVED_TOG           
+#define BP_AUDIOOUT_RESERVED_RSRVD1         0
+#define BM_AUDIOOUT_RESERVED_RSRVD1         0xffffffff
+#define BF_AUDIOOUT_RESERVED_RSRVD1(v)      (((v) & 0xffffffff) << 0)
+#define BFM_AUDIOOUT_RESERVED_RSRVD1(v)     BM_AUDIOOUT_RESERVED_RSRVD1
+#define BF_AUDIOOUT_RESERVED_RSRVD1_V(e)    BF_AUDIOOUT_RESERVED_RSRVD1(BV_AUDIOOUT_RESERVED_RSRVD1__##e)
+#define BFM_AUDIOOUT_RESERVED_RSRVD1_V(v)   BM_AUDIOOUT_RESERVED_RSRVD1
+
+#define HW_AUDIOOUT_PWRDN                   HW(AUDIOOUT_PWRDN)
+#define HWA_AUDIOOUT_PWRDN                  (0x80048000 + 0x70)
+#define HWT_AUDIOOUT_PWRDN                  HWIO_32_RW
+#define HWN_AUDIOOUT_PWRDN                  AUDIOOUT_PWRDN
+#define HWI_AUDIOOUT_PWRDN                  
+#define HW_AUDIOOUT_PWRDN_SET               HW(AUDIOOUT_PWRDN_SET)
+#define HWA_AUDIOOUT_PWRDN_SET              (HWA_AUDIOOUT_PWRDN + 0x4)
+#define HWT_AUDIOOUT_PWRDN_SET              HWIO_32_WO
+#define HWN_AUDIOOUT_PWRDN_SET              AUDIOOUT_PWRDN
+#define HWI_AUDIOOUT_PWRDN_SET              
+#define HW_AUDIOOUT_PWRDN_CLR               HW(AUDIOOUT_PWRDN_CLR)
+#define HWA_AUDIOOUT_PWRDN_CLR              (HWA_AUDIOOUT_PWRDN + 0x8)
+#define HWT_AUDIOOUT_PWRDN_CLR              HWIO_32_WO
+#define HWN_AUDIOOUT_PWRDN_CLR              AUDIOOUT_PWRDN
+#define HWI_AUDIOOUT_PWRDN_CLR              
+#define HW_AUDIOOUT_PWRDN_TOG               HW(AUDIOOUT_PWRDN_TOG)
+#define HWA_AUDIOOUT_PWRDN_TOG              (HWA_AUDIOOUT_PWRDN + 0xc)
+#define HWT_AUDIOOUT_PWRDN_TOG              HWIO_32_WO
+#define HWN_AUDIOOUT_PWRDN_TOG              AUDIOOUT_PWRDN
+#define HWI_AUDIOOUT_PWRDN_TOG              
+#define BP_AUDIOOUT_PWRDN_RSRVD7            25
+#define BM_AUDIOOUT_PWRDN_RSRVD7            0xfe000000
+#define BF_AUDIOOUT_PWRDN_RSRVD7(v)         (((v) & 0x7f) << 25)
+#define BFM_AUDIOOUT_PWRDN_RSRVD7(v)        BM_AUDIOOUT_PWRDN_RSRVD7
+#define BF_AUDIOOUT_PWRDN_RSRVD7_V(e)       BF_AUDIOOUT_PWRDN_RSRVD7(BV_AUDIOOUT_PWRDN_RSRVD7__##e)
+#define BFM_AUDIOOUT_PWRDN_RSRVD7_V(v)      BM_AUDIOOUT_PWRDN_RSRVD7
+#define BP_AUDIOOUT_PWRDN_SPEAKER           24
+#define BM_AUDIOOUT_PWRDN_SPEAKER           0x1000000
+#define BF_AUDIOOUT_PWRDN_SPEAKER(v)        (((v) & 0x1) << 24)
+#define BFM_AUDIOOUT_PWRDN_SPEAKER(v)       BM_AUDIOOUT_PWRDN_SPEAKER
+#define BF_AUDIOOUT_PWRDN_SPEAKER_V(e)      BF_AUDIOOUT_PWRDN_SPEAKER(BV_AUDIOOUT_PWRDN_SPEAKER__##e)
+#define BFM_AUDIOOUT_PWRDN_SPEAKER_V(v)     BM_AUDIOOUT_PWRDN_SPEAKER
+#define BP_AUDIOOUT_PWRDN_RSRVD6            21
+#define BM_AUDIOOUT_PWRDN_RSRVD6            0xe00000
+#define BF_AUDIOOUT_PWRDN_RSRVD6(v)         (((v) & 0x7) << 21)
+#define BFM_AUDIOOUT_PWRDN_RSRVD6(v)        BM_AUDIOOUT_PWRDN_RSRVD6
+#define BF_AUDIOOUT_PWRDN_RSRVD6_V(e)       BF_AUDIOOUT_PWRDN_RSRVD6(BV_AUDIOOUT_PWRDN_RSRVD6__##e)
+#define BFM_AUDIOOUT_PWRDN_RSRVD6_V(v)      BM_AUDIOOUT_PWRDN_RSRVD6
+#define BP_AUDIOOUT_PWRDN_SELFBIAS          20
+#define BM_AUDIOOUT_PWRDN_SELFBIAS          0x100000
+#define BF_AUDIOOUT_PWRDN_SELFBIAS(v)       (((v) & 0x1) << 20)
+#define BFM_AUDIOOUT_PWRDN_SELFBIAS(v)      BM_AUDIOOUT_PWRDN_SELFBIAS
+#define BF_AUDIOOUT_PWRDN_SELFBIAS_V(e)     BF_AUDIOOUT_PWRDN_SELFBIAS(BV_AUDIOOUT_PWRDN_SELFBIAS__##e)
+#define BFM_AUDIOOUT_PWRDN_SELFBIAS_V(v)    BM_AUDIOOUT_PWRDN_SELFBIAS
+#define BP_AUDIOOUT_PWRDN_RSRVD5            17
+#define BM_AUDIOOUT_PWRDN_RSRVD5            0xe0000
+#define BF_AUDIOOUT_PWRDN_RSRVD5(v)         (((v) & 0x7) << 17)
+#define BFM_AUDIOOUT_PWRDN_RSRVD5(v)        BM_AUDIOOUT_PWRDN_RSRVD5
+#define BF_AUDIOOUT_PWRDN_RSRVD5_V(e)       BF_AUDIOOUT_PWRDN_RSRVD5(BV_AUDIOOUT_PWRDN_RSRVD5__##e)
+#define BFM_AUDIOOUT_PWRDN_RSRVD5_V(v)      BM_AUDIOOUT_PWRDN_RSRVD5
+#define BP_AUDIOOUT_PWRDN_RIGHT_ADC         16
+#define BM_AUDIOOUT_PWRDN_RIGHT_ADC         0x10000
+#define BF_AUDIOOUT_PWRDN_RIGHT_ADC(v)      (((v) & 0x1) << 16)
+#define BFM_AUDIOOUT_PWRDN_RIGHT_ADC(v)     BM_AUDIOOUT_PWRDN_RIGHT_ADC
+#define BF_AUDIOOUT_PWRDN_RIGHT_ADC_V(e)    BF_AUDIOOUT_PWRDN_RIGHT_ADC(BV_AUDIOOUT_PWRDN_RIGHT_ADC__##e)
+#define BFM_AUDIOOUT_PWRDN_RIGHT_ADC_V(v)   BM_AUDIOOUT_PWRDN_RIGHT_ADC
+#define BP_AUDIOOUT_PWRDN_RSRVD4            13
+#define BM_AUDIOOUT_PWRDN_RSRVD4            0xe000
+#define BF_AUDIOOUT_PWRDN_RSRVD4(v)         (((v) & 0x7) << 13)
+#define BFM_AUDIOOUT_PWRDN_RSRVD4(v)        BM_AUDIOOUT_PWRDN_RSRVD4
+#define BF_AUDIOOUT_PWRDN_RSRVD4_V(e)       BF_AUDIOOUT_PWRDN_RSRVD4(BV_AUDIOOUT_PWRDN_RSRVD4__##e)
+#define BFM_AUDIOOUT_PWRDN_RSRVD4_V(v)      BM_AUDIOOUT_PWRDN_RSRVD4
+#define BP_AUDIOOUT_PWRDN_DAC               12
+#define BM_AUDIOOUT_PWRDN_DAC               0x1000
+#define BF_AUDIOOUT_PWRDN_DAC(v)            (((v) & 0x1) << 12)
+#define BFM_AUDIOOUT_PWRDN_DAC(v)           BM_AUDIOOUT_PWRDN_DAC
+#define BF_AUDIOOUT_PWRDN_DAC_V(e)          BF_AUDIOOUT_PWRDN_DAC(BV_AUDIOOUT_PWRDN_DAC__##e)
+#define BFM_AUDIOOUT_PWRDN_DAC_V(v)         BM_AUDIOOUT_PWRDN_DAC
+#define BP_AUDIOOUT_PWRDN_RSRVD3            9
+#define BM_AUDIOOUT_PWRDN_RSRVD3            0xe00
+#define BF_AUDIOOUT_PWRDN_RSRVD3(v)         (((v) & 0x7) << 9)
+#define BFM_AUDIOOUT_PWRDN_RSRVD3(v)        BM_AUDIOOUT_PWRDN_RSRVD3
+#define BF_AUDIOOUT_PWRDN_RSRVD3_V(e)       BF_AUDIOOUT_PWRDN_RSRVD3(BV_AUDIOOUT_PWRDN_RSRVD3__##e)
+#define BFM_AUDIOOUT_PWRDN_RSRVD3_V(v)      BM_AUDIOOUT_PWRDN_RSRVD3
+#define BP_AUDIOOUT_PWRDN_ADC               8
+#define BM_AUDIOOUT_PWRDN_ADC               0x100
+#define BF_AUDIOOUT_PWRDN_ADC(v)            (((v) & 0x1) << 8)
+#define BFM_AUDIOOUT_PWRDN_ADC(v)           BM_AUDIOOUT_PWRDN_ADC
+#define BF_AUDIOOUT_PWRDN_ADC_V(e)          BF_AUDIOOUT_PWRDN_ADC(BV_AUDIOOUT_PWRDN_ADC__##e)
+#define BFM_AUDIOOUT_PWRDN_ADC_V(v)         BM_AUDIOOUT_PWRDN_ADC
+#define BP_AUDIOOUT_PWRDN_RSRVD2            5
+#define BM_AUDIOOUT_PWRDN_RSRVD2            0xe0
+#define BF_AUDIOOUT_PWRDN_RSRVD2(v)         (((v) & 0x7) << 5)
+#define BFM_AUDIOOUT_PWRDN_RSRVD2(v)        BM_AUDIOOUT_PWRDN_RSRVD2
+#define BF_AUDIOOUT_PWRDN_RSRVD2_V(e)       BF_AUDIOOUT_PWRDN_RSRVD2(BV_AUDIOOUT_PWRDN_RSRVD2__##e)
+#define BFM_AUDIOOUT_PWRDN_RSRVD2_V(v)      BM_AUDIOOUT_PWRDN_RSRVD2
+#define BP_AUDIOOUT_PWRDN_CAPLESS           4
+#define BM_AUDIOOUT_PWRDN_CAPLESS           0x10
+#define BF_AUDIOOUT_PWRDN_CAPLESS(v)        (((v) & 0x1) << 4)
+#define BFM_AUDIOOUT_PWRDN_CAPLESS(v)       BM_AUDIOOUT_PWRDN_CAPLESS
+#define BF_AUDIOOUT_PWRDN_CAPLESS_V(e)      BF_AUDIOOUT_PWRDN_CAPLESS(BV_AUDIOOUT_PWRDN_CAPLESS__##e)
+#define BFM_AUDIOOUT_PWRDN_CAPLESS_V(v)     BM_AUDIOOUT_PWRDN_CAPLESS
+#define BP_AUDIOOUT_PWRDN_RSRVD1            1
+#define BM_AUDIOOUT_PWRDN_RSRVD1            0xe
+#define BF_AUDIOOUT_PWRDN_RSRVD1(v)         (((v) & 0x7) << 1)
+#define BFM_AUDIOOUT_PWRDN_RSRVD1(v)        BM_AUDIOOUT_PWRDN_RSRVD1
+#define BF_AUDIOOUT_PWRDN_RSRVD1_V(e)       BF_AUDIOOUT_PWRDN_RSRVD1(BV_AUDIOOUT_PWRDN_RSRVD1__##e)
+#define BFM_AUDIOOUT_PWRDN_RSRVD1_V(v)      BM_AUDIOOUT_PWRDN_RSRVD1
+#define BP_AUDIOOUT_PWRDN_HEADPHONE         0
+#define BM_AUDIOOUT_PWRDN_HEADPHONE         0x1
+#define BF_AUDIOOUT_PWRDN_HEADPHONE(v)      (((v) & 0x1) << 0)
+#define BFM_AUDIOOUT_PWRDN_HEADPHONE(v)     BM_AUDIOOUT_PWRDN_HEADPHONE
+#define BF_AUDIOOUT_PWRDN_HEADPHONE_V(e)    BF_AUDIOOUT_PWRDN_HEADPHONE(BV_AUDIOOUT_PWRDN_HEADPHONE__##e)
+#define BFM_AUDIOOUT_PWRDN_HEADPHONE_V(v)   BM_AUDIOOUT_PWRDN_HEADPHONE
+
+#define HW_AUDIOOUT_REFCTRL                         HW(AUDIOOUT_REFCTRL)
+#define HWA_AUDIOOUT_REFCTRL                        (0x80048000 + 0x80)
+#define HWT_AUDIOOUT_REFCTRL                        HWIO_32_RW
+#define HWN_AUDIOOUT_REFCTRL                        AUDIOOUT_REFCTRL
+#define HWI_AUDIOOUT_REFCTRL                        
+#define HW_AUDIOOUT_REFCTRL_SET                     HW(AUDIOOUT_REFCTRL_SET)
+#define HWA_AUDIOOUT_REFCTRL_SET                    (HWA_AUDIOOUT_REFCTRL + 0x4)
+#define HWT_AUDIOOUT_REFCTRL_SET                    HWIO_32_WO
+#define HWN_AUDIOOUT_REFCTRL_SET                    AUDIOOUT_REFCTRL
+#define HWI_AUDIOOUT_REFCTRL_SET                    
+#define HW_AUDIOOUT_REFCTRL_CLR                     HW(AUDIOOUT_REFCTRL_CLR)
+#define HWA_AUDIOOUT_REFCTRL_CLR                    (HWA_AUDIOOUT_REFCTRL + 0x8)
+#define HWT_AUDIOOUT_REFCTRL_CLR                    HWIO_32_WO
+#define HWN_AUDIOOUT_REFCTRL_CLR                    AUDIOOUT_REFCTRL
+#define HWI_AUDIOOUT_REFCTRL_CLR                    
+#define HW_AUDIOOUT_REFCTRL_TOG                     HW(AUDIOOUT_REFCTRL_TOG)
+#define HWA_AUDIOOUT_REFCTRL_TOG                    (HWA_AUDIOOUT_REFCTRL + 0xc)
+#define HWT_AUDIOOUT_REFCTRL_TOG                    HWIO_32_WO
+#define HWN_AUDIOOUT_REFCTRL_TOG                    AUDIOOUT_REFCTRL
+#define HWI_AUDIOOUT_REFCTRL_TOG                    
+#define BP_AUDIOOUT_REFCTRL_RSRVD4                  27
+#define BM_AUDIOOUT_REFCTRL_RSRVD4                  0xf8000000
+#define BF_AUDIOOUT_REFCTRL_RSRVD4(v)               (((v) & 0x1f) << 27)
+#define BFM_AUDIOOUT_REFCTRL_RSRVD4(v)              BM_AUDIOOUT_REFCTRL_RSRVD4
+#define BF_AUDIOOUT_REFCTRL_RSRVD4_V(e)             BF_AUDIOOUT_REFCTRL_RSRVD4(BV_AUDIOOUT_REFCTRL_RSRVD4__##e)
+#define BFM_AUDIOOUT_REFCTRL_RSRVD4_V(v)            BM_AUDIOOUT_REFCTRL_RSRVD4
+#define BP_AUDIOOUT_REFCTRL_FASTSETTLING            26
+#define BM_AUDIOOUT_REFCTRL_FASTSETTLING            0x4000000
+#define BF_AUDIOOUT_REFCTRL_FASTSETTLING(v)         (((v) & 0x1) << 26)
+#define BFM_AUDIOOUT_REFCTRL_FASTSETTLING(v)        BM_AUDIOOUT_REFCTRL_FASTSETTLING
+#define BF_AUDIOOUT_REFCTRL_FASTSETTLING_V(e)       BF_AUDIOOUT_REFCTRL_FASTSETTLING(BV_AUDIOOUT_REFCTRL_FASTSETTLING__##e)
+#define BFM_AUDIOOUT_REFCTRL_FASTSETTLING_V(v)      BM_AUDIOOUT_REFCTRL_FASTSETTLING
+#define BP_AUDIOOUT_REFCTRL_RAISE_REF               25
+#define BM_AUDIOOUT_REFCTRL_RAISE_REF               0x2000000
+#define BF_AUDIOOUT_REFCTRL_RAISE_REF(v)            (((v) & 0x1) << 25)
+#define BFM_AUDIOOUT_REFCTRL_RAISE_REF(v)           BM_AUDIOOUT_REFCTRL_RAISE_REF
+#define BF_AUDIOOUT_REFCTRL_RAISE_REF_V(e)          BF_AUDIOOUT_REFCTRL_RAISE_REF(BV_AUDIOOUT_REFCTRL_RAISE_REF__##e)
+#define BFM_AUDIOOUT_REFCTRL_RAISE_REF_V(v)         BM_AUDIOOUT_REFCTRL_RAISE_REF
+#define BP_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS           24
+#define BM_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS           0x1000000
+#define BF_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS(v)        (((v) & 0x1) << 24)
+#define BFM_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS(v)       BM_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS
+#define BF_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS_V(e)      BF_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS(BV_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS__##e)
+#define BFM_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS_V(v)     BM_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS
+#define BP_AUDIOOUT_REFCTRL_RSRVD3                  23
+#define BM_AUDIOOUT_REFCTRL_RSRVD3                  0x800000
+#define BF_AUDIOOUT_REFCTRL_RSRVD3(v)               (((v) & 0x1) << 23)
+#define BFM_AUDIOOUT_REFCTRL_RSRVD3(v)              BM_AUDIOOUT_REFCTRL_RSRVD3
+#define BF_AUDIOOUT_REFCTRL_RSRVD3_V(e)             BF_AUDIOOUT_REFCTRL_RSRVD3(BV_AUDIOOUT_REFCTRL_RSRVD3__##e)
+#define BFM_AUDIOOUT_REFCTRL_RSRVD3_V(v)            BM_AUDIOOUT_REFCTRL_RSRVD3
+#define BP_AUDIOOUT_REFCTRL_VBG_ADJ                 20
+#define BM_AUDIOOUT_REFCTRL_VBG_ADJ                 0x700000
+#define BF_AUDIOOUT_REFCTRL_VBG_ADJ(v)              (((v) & 0x7) << 20)
+#define BFM_AUDIOOUT_REFCTRL_VBG_ADJ(v)             BM_AUDIOOUT_REFCTRL_VBG_ADJ
+#define BF_AUDIOOUT_REFCTRL_VBG_ADJ_V(e)            BF_AUDIOOUT_REFCTRL_VBG_ADJ(BV_AUDIOOUT_REFCTRL_VBG_ADJ__##e)
+#define BFM_AUDIOOUT_REFCTRL_VBG_ADJ_V(v)           BM_AUDIOOUT_REFCTRL_VBG_ADJ
+#define BP_AUDIOOUT_REFCTRL_LOW_PWR                 19
+#define BM_AUDIOOUT_REFCTRL_LOW_PWR                 0x80000
+#define BF_AUDIOOUT_REFCTRL_LOW_PWR(v)              (((v) & 0x1) << 19)
+#define BFM_AUDIOOUT_REFCTRL_LOW_PWR(v)             BM_AUDIOOUT_REFCTRL_LOW_PWR
+#define BF_AUDIOOUT_REFCTRL_LOW_PWR_V(e)            BF_AUDIOOUT_REFCTRL_LOW_PWR(BV_AUDIOOUT_REFCTRL_LOW_PWR__##e)
+#define BFM_AUDIOOUT_REFCTRL_LOW_PWR_V(v)           BM_AUDIOOUT_REFCTRL_LOW_PWR
+#define BP_AUDIOOUT_REFCTRL_LW_REF                  18
+#define BM_AUDIOOUT_REFCTRL_LW_REF                  0x40000
+#define BF_AUDIOOUT_REFCTRL_LW_REF(v)               (((v) & 0x1) << 18)
+#define BFM_AUDIOOUT_REFCTRL_LW_REF(v)              BM_AUDIOOUT_REFCTRL_LW_REF
+#define BF_AUDIOOUT_REFCTRL_LW_REF_V(e)             BF_AUDIOOUT_REFCTRL_LW_REF(BV_AUDIOOUT_REFCTRL_LW_REF__##e)
+#define BFM_AUDIOOUT_REFCTRL_LW_REF_V(v)            BM_AUDIOOUT_REFCTRL_LW_REF
+#define BP_AUDIOOUT_REFCTRL_BIAS_CTRL               16
+#define BM_AUDIOOUT_REFCTRL_BIAS_CTRL               0x30000
+#define BF_AUDIOOUT_REFCTRL_BIAS_CTRL(v)            (((v) & 0x3) << 16)
+#define BFM_AUDIOOUT_REFCTRL_BIAS_CTRL(v)           BM_AUDIOOUT_REFCTRL_BIAS_CTRL
+#define BF_AUDIOOUT_REFCTRL_BIAS_CTRL_V(e)          BF_AUDIOOUT_REFCTRL_BIAS_CTRL(BV_AUDIOOUT_REFCTRL_BIAS_CTRL__##e)
+#define BFM_AUDIOOUT_REFCTRL_BIAS_CTRL_V(v)         BM_AUDIOOUT_REFCTRL_BIAS_CTRL
+#define BP_AUDIOOUT_REFCTRL_RSRVD2                  15
+#define BM_AUDIOOUT_REFCTRL_RSRVD2                  0x8000
+#define BF_AUDIOOUT_REFCTRL_RSRVD2(v)               (((v) & 0x1) << 15)
+#define BFM_AUDIOOUT_REFCTRL_RSRVD2(v)              BM_AUDIOOUT_REFCTRL_RSRVD2
+#define BF_AUDIOOUT_REFCTRL_RSRVD2_V(e)             BF_AUDIOOUT_REFCTRL_RSRVD2(BV_AUDIOOUT_REFCTRL_RSRVD2__##e)
+#define BFM_AUDIOOUT_REFCTRL_RSRVD2_V(v)            BM_AUDIOOUT_REFCTRL_RSRVD2
+#define BP_AUDIOOUT_REFCTRL_VDDXTAL_TO_VDDD         14
+#define BM_AUDIOOUT_REFCTRL_VDDXTAL_TO_VDDD         0x4000
+#define BF_AUDIOOUT_REFCTRL_VDDXTAL_TO_VDDD(v)      (((v) & 0x1) << 14)
+#define BFM_AUDIOOUT_REFCTRL_VDDXTAL_TO_VDDD(v)     BM_AUDIOOUT_REFCTRL_VDDXTAL_TO_VDDD
+#define BF_AUDIOOUT_REFCTRL_VDDXTAL_TO_VDDD_V(e)    BF_AUDIOOUT_REFCTRL_VDDXTAL_TO_VDDD(BV_AUDIOOUT_REFCTRL_VDDXTAL_TO_VDDD__##e)
+#define BFM_AUDIOOUT_REFCTRL_VDDXTAL_TO_VDDD_V(v)   BM_AUDIOOUT_REFCTRL_VDDXTAL_TO_VDDD
+#define BP_AUDIOOUT_REFCTRL_ADJ_ADC                 13
+#define BM_AUDIOOUT_REFCTRL_ADJ_ADC                 0x2000
+#define BF_AUDIOOUT_REFCTRL_ADJ_ADC(v)              (((v) & 0x1) << 13)
+#define BFM_AUDIOOUT_REFCTRL_ADJ_ADC(v)             BM_AUDIOOUT_REFCTRL_ADJ_ADC
+#define BF_AUDIOOUT_REFCTRL_ADJ_ADC_V(e)            BF_AUDIOOUT_REFCTRL_ADJ_ADC(BV_AUDIOOUT_REFCTRL_ADJ_ADC__##e)
+#define BFM_AUDIOOUT_REFCTRL_ADJ_ADC_V(v)           BM_AUDIOOUT_REFCTRL_ADJ_ADC
+#define BP_AUDIOOUT_REFCTRL_ADJ_VAG                 12
+#define BM_AUDIOOUT_REFCTRL_ADJ_VAG                 0x1000
+#define BF_AUDIOOUT_REFCTRL_ADJ_VAG(v)              (((v) & 0x1) << 12)
+#define BFM_AUDIOOUT_REFCTRL_ADJ_VAG(v)             BM_AUDIOOUT_REFCTRL_ADJ_VAG
+#define BF_AUDIOOUT_REFCTRL_ADJ_VAG_V(e)            BF_AUDIOOUT_REFCTRL_ADJ_VAG(BV_AUDIOOUT_REFCTRL_ADJ_VAG__##e)
+#define BFM_AUDIOOUT_REFCTRL_ADJ_VAG_V(v)           BM_AUDIOOUT_REFCTRL_ADJ_VAG
+#define BP_AUDIOOUT_REFCTRL_ADC_REFVAL              8
+#define BM_AUDIOOUT_REFCTRL_ADC_REFVAL              0xf00
+#define BF_AUDIOOUT_REFCTRL_ADC_REFVAL(v)           (((v) & 0xf) << 8)
+#define BFM_AUDIOOUT_REFCTRL_ADC_REFVAL(v)          BM_AUDIOOUT_REFCTRL_ADC_REFVAL
+#define BF_AUDIOOUT_REFCTRL_ADC_REFVAL_V(e)         BF_AUDIOOUT_REFCTRL_ADC_REFVAL(BV_AUDIOOUT_REFCTRL_ADC_REFVAL__##e)
+#define BFM_AUDIOOUT_REFCTRL_ADC_REFVAL_V(v)        BM_AUDIOOUT_REFCTRL_ADC_REFVAL
+#define BP_AUDIOOUT_REFCTRL_VAG_VAL                 4
+#define BM_AUDIOOUT_REFCTRL_VAG_VAL                 0xf0
+#define BF_AUDIOOUT_REFCTRL_VAG_VAL(v)              (((v) & 0xf) << 4)
+#define BFM_AUDIOOUT_REFCTRL_VAG_VAL(v)             BM_AUDIOOUT_REFCTRL_VAG_VAL
+#define BF_AUDIOOUT_REFCTRL_VAG_VAL_V(e)            BF_AUDIOOUT_REFCTRL_VAG_VAL(BV_AUDIOOUT_REFCTRL_VAG_VAL__##e)
+#define BFM_AUDIOOUT_REFCTRL_VAG_VAL_V(v)           BM_AUDIOOUT_REFCTRL_VAG_VAL
+#define BP_AUDIOOUT_REFCTRL_RSRVD1                  3
+#define BM_AUDIOOUT_REFCTRL_RSRVD1                  0x8
+#define BF_AUDIOOUT_REFCTRL_RSRVD1(v)               (((v) & 0x1) << 3)
+#define BFM_AUDIOOUT_REFCTRL_RSRVD1(v)              BM_AUDIOOUT_REFCTRL_RSRVD1
+#define BF_AUDIOOUT_REFCTRL_RSRVD1_V(e)             BF_AUDIOOUT_REFCTRL_RSRVD1(BV_AUDIOOUT_REFCTRL_RSRVD1__##e)
+#define BFM_AUDIOOUT_REFCTRL_RSRVD1_V(v)            BM_AUDIOOUT_REFCTRL_RSRVD1
+#define BP_AUDIOOUT_REFCTRL_DAC_ADJ                 0
+#define BM_AUDIOOUT_REFCTRL_DAC_ADJ                 0x7
+#define BF_AUDIOOUT_REFCTRL_DAC_ADJ(v)              (((v) & 0x7) << 0)
+#define BFM_AUDIOOUT_REFCTRL_DAC_ADJ(v)             BM_AUDIOOUT_REFCTRL_DAC_ADJ
+#define BF_AUDIOOUT_REFCTRL_DAC_ADJ_V(e)            BF_AUDIOOUT_REFCTRL_DAC_ADJ(BV_AUDIOOUT_REFCTRL_DAC_ADJ__##e)
+#define BFM_AUDIOOUT_REFCTRL_DAC_ADJ_V(v)           BM_AUDIOOUT_REFCTRL_DAC_ADJ
+
+#define HW_AUDIOOUT_ANACTRL                     HW(AUDIOOUT_ANACTRL)
+#define HWA_AUDIOOUT_ANACTRL                    (0x80048000 + 0x90)
+#define HWT_AUDIOOUT_ANACTRL                    HWIO_32_RW
+#define HWN_AUDIOOUT_ANACTRL                    AUDIOOUT_ANACTRL
+#define HWI_AUDIOOUT_ANACTRL                    
+#define HW_AUDIOOUT_ANACTRL_SET                 HW(AUDIOOUT_ANACTRL_SET)
+#define HWA_AUDIOOUT_ANACTRL_SET                (HWA_AUDIOOUT_ANACTRL + 0x4)
+#define HWT_AUDIOOUT_ANACTRL_SET                HWIO_32_WO
+#define HWN_AUDIOOUT_ANACTRL_SET                AUDIOOUT_ANACTRL
+#define HWI_AUDIOOUT_ANACTRL_SET                
+#define HW_AUDIOOUT_ANACTRL_CLR                 HW(AUDIOOUT_ANACTRL_CLR)
+#define HWA_AUDIOOUT_ANACTRL_CLR                (HWA_AUDIOOUT_ANACTRL + 0x8)
+#define HWT_AUDIOOUT_ANACTRL_CLR                HWIO_32_WO
+#define HWN_AUDIOOUT_ANACTRL_CLR                AUDIOOUT_ANACTRL
+#define HWI_AUDIOOUT_ANACTRL_CLR                
+#define HW_AUDIOOUT_ANACTRL_TOG                 HW(AUDIOOUT_ANACTRL_TOG)
+#define HWA_AUDIOOUT_ANACTRL_TOG                (HWA_AUDIOOUT_ANACTRL + 0xc)
+#define HWT_AUDIOOUT_ANACTRL_TOG                HWIO_32_WO
+#define HWN_AUDIOOUT_ANACTRL_TOG                AUDIOOUT_ANACTRL
+#define HWI_AUDIOOUT_ANACTRL_TOG                
+#define BP_AUDIOOUT_ANACTRL_RSRVD8              29
+#define BM_AUDIOOUT_ANACTRL_RSRVD8              0xe0000000
+#define BF_AUDIOOUT_ANACTRL_RSRVD8(v)           (((v) & 0x7) << 29)
+#define BFM_AUDIOOUT_ANACTRL_RSRVD8(v)          BM_AUDIOOUT_ANACTRL_RSRVD8
+#define BF_AUDIOOUT_ANACTRL_RSRVD8_V(e)         BF_AUDIOOUT_ANACTRL_RSRVD8(BV_AUDIOOUT_ANACTRL_RSRVD8__##e)
+#define BFM_AUDIOOUT_ANACTRL_RSRVD8_V(v)        BM_AUDIOOUT_ANACTRL_RSRVD8
+#define BP_AUDIOOUT_ANACTRL_SHORT_CM_STS        28
+#define BM_AUDIOOUT_ANACTRL_SHORT_CM_STS        0x10000000
+#define BF_AUDIOOUT_ANACTRL_SHORT_CM_STS(v)     (((v) & 0x1) << 28)
+#define BFM_AUDIOOUT_ANACTRL_SHORT_CM_STS(v)    BM_AUDIOOUT_ANACTRL_SHORT_CM_STS
+#define BF_AUDIOOUT_ANACTRL_SHORT_CM_STS_V(e)   BF_AUDIOOUT_ANACTRL_SHORT_CM_STS(BV_AUDIOOUT_ANACTRL_SHORT_CM_STS__##e)
+#define BFM_AUDIOOUT_ANACTRL_SHORT_CM_STS_V(v)  BM_AUDIOOUT_ANACTRL_SHORT_CM_STS
+#define BP_AUDIOOUT_ANACTRL_RSRVD7              25
+#define BM_AUDIOOUT_ANACTRL_RSRVD7              0xe000000
+#define BF_AUDIOOUT_ANACTRL_RSRVD7(v)           (((v) & 0x7) << 25)
+#define BFM_AUDIOOUT_ANACTRL_RSRVD7(v)          BM_AUDIOOUT_ANACTRL_RSRVD7
+#define BF_AUDIOOUT_ANACTRL_RSRVD7_V(e)         BF_AUDIOOUT_ANACTRL_RSRVD7(BV_AUDIOOUT_ANACTRL_RSRVD7__##e)
+#define BFM_AUDIOOUT_ANACTRL_RSRVD7_V(v)        BM_AUDIOOUT_ANACTRL_RSRVD7
+#define BP_AUDIOOUT_ANACTRL_SHORT_LR_STS        24
+#define BM_AUDIOOUT_ANACTRL_SHORT_LR_STS        0x1000000
+#define BF_AUDIOOUT_ANACTRL_SHORT_LR_STS(v)     (((v) & 0x1) << 24)
+#define BFM_AUDIOOUT_ANACTRL_SHORT_LR_STS(v)    BM_AUDIOOUT_ANACTRL_SHORT_LR_STS
+#define BF_AUDIOOUT_ANACTRL_SHORT_LR_STS_V(e)   BF_AUDIOOUT_ANACTRL_SHORT_LR_STS(BV_AUDIOOUT_ANACTRL_SHORT_LR_STS__##e)
+#define BFM_AUDIOOUT_ANACTRL_SHORT_LR_STS_V(v)  BM_AUDIOOUT_ANACTRL_SHORT_LR_STS
+#define BP_AUDIOOUT_ANACTRL_RSRVD6              22
+#define BM_AUDIOOUT_ANACTRL_RSRVD6              0xc00000
+#define BF_AUDIOOUT_ANACTRL_RSRVD6(v)           (((v) & 0x3) << 22)
+#define BFM_AUDIOOUT_ANACTRL_RSRVD6(v)          BM_AUDIOOUT_ANACTRL_RSRVD6
+#define BF_AUDIOOUT_ANACTRL_RSRVD6_V(e)         BF_AUDIOOUT_ANACTRL_RSRVD6(BV_AUDIOOUT_ANACTRL_RSRVD6__##e)
+#define BFM_AUDIOOUT_ANACTRL_RSRVD6_V(v)        BM_AUDIOOUT_ANACTRL_RSRVD6
+#define BP_AUDIOOUT_ANACTRL_SHORTMODE_CM        20
+#define BM_AUDIOOUT_ANACTRL_SHORTMODE_CM        0x300000
+#define BF_AUDIOOUT_ANACTRL_SHORTMODE_CM(v)     (((v) & 0x3) << 20)
+#define BFM_AUDIOOUT_ANACTRL_SHORTMODE_CM(v)    BM_AUDIOOUT_ANACTRL_SHORTMODE_CM
+#define BF_AUDIOOUT_ANACTRL_SHORTMODE_CM_V(e)   BF_AUDIOOUT_ANACTRL_SHORTMODE_CM(BV_AUDIOOUT_ANACTRL_SHORTMODE_CM__##e)
+#define BFM_AUDIOOUT_ANACTRL_SHORTMODE_CM_V(v)  BM_AUDIOOUT_ANACTRL_SHORTMODE_CM
+#define BP_AUDIOOUT_ANACTRL_RSRVD5              19
+#define BM_AUDIOOUT_ANACTRL_RSRVD5              0x80000
+#define BF_AUDIOOUT_ANACTRL_RSRVD5(v)           (((v) & 0x1) << 19)
+#define BFM_AUDIOOUT_ANACTRL_RSRVD5(v)          BM_AUDIOOUT_ANACTRL_RSRVD5
+#define BF_AUDIOOUT_ANACTRL_RSRVD5_V(e)         BF_AUDIOOUT_ANACTRL_RSRVD5(BV_AUDIOOUT_ANACTRL_RSRVD5__##e)
+#define BFM_AUDIOOUT_ANACTRL_RSRVD5_V(v)        BM_AUDIOOUT_ANACTRL_RSRVD5
+#define BP_AUDIOOUT_ANACTRL_SHORTMODE_LR        17
+#define BM_AUDIOOUT_ANACTRL_SHORTMODE_LR        0x60000
+#define BF_AUDIOOUT_ANACTRL_SHORTMODE_LR(v)     (((v) & 0x3) << 17)
+#define BFM_AUDIOOUT_ANACTRL_SHORTMODE_LR(v)    BM_AUDIOOUT_ANACTRL_SHORTMODE_LR
+#define BF_AUDIOOUT_ANACTRL_SHORTMODE_LR_V(e)   BF_AUDIOOUT_ANACTRL_SHORTMODE_LR(BV_AUDIOOUT_ANACTRL_SHORTMODE_LR__##e)
+#define BFM_AUDIOOUT_ANACTRL_SHORTMODE_LR_V(v)  BM_AUDIOOUT_ANACTRL_SHORTMODE_LR
+#define BP_AUDIOOUT_ANACTRL_RSRVD4              15
+#define BM_AUDIOOUT_ANACTRL_RSRVD4              0x18000
+#define BF_AUDIOOUT_ANACTRL_RSRVD4(v)           (((v) & 0x3) << 15)
+#define BFM_AUDIOOUT_ANACTRL_RSRVD4(v)          BM_AUDIOOUT_ANACTRL_RSRVD4
+#define BF_AUDIOOUT_ANACTRL_RSRVD4_V(e)         BF_AUDIOOUT_ANACTRL_RSRVD4(BV_AUDIOOUT_ANACTRL_RSRVD4__##e)
+#define BFM_AUDIOOUT_ANACTRL_RSRVD4_V(v)        BM_AUDIOOUT_ANACTRL_RSRVD4
+#define BP_AUDIOOUT_ANACTRL_SHORT_LVLADJL       12
+#define BM_AUDIOOUT_ANACTRL_SHORT_LVLADJL       0x7000
+#define BF_AUDIOOUT_ANACTRL_SHORT_LVLADJL(v)    (((v) & 0x7) << 12)
+#define BFM_AUDIOOUT_ANACTRL_SHORT_LVLADJL(v)   BM_AUDIOOUT_ANACTRL_SHORT_LVLADJL
+#define BF_AUDIOOUT_ANACTRL_SHORT_LVLADJL_V(e)  BF_AUDIOOUT_ANACTRL_SHORT_LVLADJL(BV_AUDIOOUT_ANACTRL_SHORT_LVLADJL__##e)
+#define BFM_AUDIOOUT_ANACTRL_SHORT_LVLADJL_V(v) BM_AUDIOOUT_ANACTRL_SHORT_LVLADJL
+#define BP_AUDIOOUT_ANACTRL_RSRVD3              11
+#define BM_AUDIOOUT_ANACTRL_RSRVD3              0x800
+#define BF_AUDIOOUT_ANACTRL_RSRVD3(v)           (((v) & 0x1) << 11)
+#define BFM_AUDIOOUT_ANACTRL_RSRVD3(v)          BM_AUDIOOUT_ANACTRL_RSRVD3
+#define BF_AUDIOOUT_ANACTRL_RSRVD3_V(e)         BF_AUDIOOUT_ANACTRL_RSRVD3(BV_AUDIOOUT_ANACTRL_RSRVD3__##e)
+#define BFM_AUDIOOUT_ANACTRL_RSRVD3_V(v)        BM_AUDIOOUT_ANACTRL_RSRVD3
+#define BP_AUDIOOUT_ANACTRL_SHORT_LVLADJR       8
+#define BM_AUDIOOUT_ANACTRL_SHORT_LVLADJR       0x700
+#define BF_AUDIOOUT_ANACTRL_SHORT_LVLADJR(v)    (((v) & 0x7) << 8)
+#define BFM_AUDIOOUT_ANACTRL_SHORT_LVLADJR(v)   BM_AUDIOOUT_ANACTRL_SHORT_LVLADJR
+#define BF_AUDIOOUT_ANACTRL_SHORT_LVLADJR_V(e)  BF_AUDIOOUT_ANACTRL_SHORT_LVLADJR(BV_AUDIOOUT_ANACTRL_SHORT_LVLADJR__##e)
+#define BFM_AUDIOOUT_ANACTRL_SHORT_LVLADJR_V(v) BM_AUDIOOUT_ANACTRL_SHORT_LVLADJR
+#define BP_AUDIOOUT_ANACTRL_RSRVD2              6
+#define BM_AUDIOOUT_ANACTRL_RSRVD2              0xc0
+#define BF_AUDIOOUT_ANACTRL_RSRVD2(v)           (((v) & 0x3) << 6)
+#define BFM_AUDIOOUT_ANACTRL_RSRVD2(v)          BM_AUDIOOUT_ANACTRL_RSRVD2
+#define BF_AUDIOOUT_ANACTRL_RSRVD2_V(e)         BF_AUDIOOUT_ANACTRL_RSRVD2(BV_AUDIOOUT_ANACTRL_RSRVD2__##e)
+#define BFM_AUDIOOUT_ANACTRL_RSRVD2_V(v)        BM_AUDIOOUT_ANACTRL_RSRVD2
+#define BP_AUDIOOUT_ANACTRL_HP_HOLD_GND         5
+#define BM_AUDIOOUT_ANACTRL_HP_HOLD_GND         0x20
+#define BF_AUDIOOUT_ANACTRL_HP_HOLD_GND(v)      (((v) & 0x1) << 5)
+#define BFM_AUDIOOUT_ANACTRL_HP_HOLD_GND(v)     BM_AUDIOOUT_ANACTRL_HP_HOLD_GND
+#define BF_AUDIOOUT_ANACTRL_HP_HOLD_GND_V(e)    BF_AUDIOOUT_ANACTRL_HP_HOLD_GND(BV_AUDIOOUT_ANACTRL_HP_HOLD_GND__##e)
+#define BFM_AUDIOOUT_ANACTRL_HP_HOLD_GND_V(v)   BM_AUDIOOUT_ANACTRL_HP_HOLD_GND
+#define BP_AUDIOOUT_ANACTRL_HP_CLASSAB          4
+#define BM_AUDIOOUT_ANACTRL_HP_CLASSAB          0x10
+#define BF_AUDIOOUT_ANACTRL_HP_CLASSAB(v)       (((v) & 0x1) << 4)
+#define BFM_AUDIOOUT_ANACTRL_HP_CLASSAB(v)      BM_AUDIOOUT_ANACTRL_HP_CLASSAB
+#define BF_AUDIOOUT_ANACTRL_HP_CLASSAB_V(e)     BF_AUDIOOUT_ANACTRL_HP_CLASSAB(BV_AUDIOOUT_ANACTRL_HP_CLASSAB__##e)
+#define BFM_AUDIOOUT_ANACTRL_HP_CLASSAB_V(v)    BM_AUDIOOUT_ANACTRL_HP_CLASSAB
+#define BP_AUDIOOUT_ANACTRL_RSRVD1              0
+#define BM_AUDIOOUT_ANACTRL_RSRVD1              0xf
+#define BF_AUDIOOUT_ANACTRL_RSRVD1(v)           (((v) & 0xf) << 0)
+#define BFM_AUDIOOUT_ANACTRL_RSRVD1(v)          BM_AUDIOOUT_ANACTRL_RSRVD1
+#define BF_AUDIOOUT_ANACTRL_RSRVD1_V(e)         BF_AUDIOOUT_ANACTRL_RSRVD1(BV_AUDIOOUT_ANACTRL_RSRVD1__##e)
+#define BFM_AUDIOOUT_ANACTRL_RSRVD1_V(v)        BM_AUDIOOUT_ANACTRL_RSRVD1
+
+#define HW_AUDIOOUT_TEST                        HW(AUDIOOUT_TEST)
+#define HWA_AUDIOOUT_TEST                       (0x80048000 + 0xa0)
+#define HWT_AUDIOOUT_TEST                       HWIO_32_RW
+#define HWN_AUDIOOUT_TEST                       AUDIOOUT_TEST
+#define HWI_AUDIOOUT_TEST                       
+#define HW_AUDIOOUT_TEST_SET                    HW(AUDIOOUT_TEST_SET)
+#define HWA_AUDIOOUT_TEST_SET                   (HWA_AUDIOOUT_TEST + 0x4)
+#define HWT_AUDIOOUT_TEST_SET                   HWIO_32_WO
+#define HWN_AUDIOOUT_TEST_SET                   AUDIOOUT_TEST
+#define HWI_AUDIOOUT_TEST_SET                   
+#define HW_AUDIOOUT_TEST_CLR                    HW(AUDIOOUT_TEST_CLR)
+#define HWA_AUDIOOUT_TEST_CLR                   (HWA_AUDIOOUT_TEST + 0x8)
+#define HWT_AUDIOOUT_TEST_CLR                   HWIO_32_WO
+#define HWN_AUDIOOUT_TEST_CLR                   AUDIOOUT_TEST
+#define HWI_AUDIOOUT_TEST_CLR                   
+#define HW_AUDIOOUT_TEST_TOG                    HW(AUDIOOUT_TEST_TOG)
+#define HWA_AUDIOOUT_TEST_TOG                   (HWA_AUDIOOUT_TEST + 0xc)
+#define HWT_AUDIOOUT_TEST_TOG                   HWIO_32_WO
+#define HWN_AUDIOOUT_TEST_TOG                   AUDIOOUT_TEST
+#define HWI_AUDIOOUT_TEST_TOG                   
+#define BP_AUDIOOUT_TEST_RSRVD4                 31
+#define BM_AUDIOOUT_TEST_RSRVD4                 0x80000000
+#define BF_AUDIOOUT_TEST_RSRVD4(v)              (((v) & 0x1) << 31)
+#define BFM_AUDIOOUT_TEST_RSRVD4(v)             BM_AUDIOOUT_TEST_RSRVD4
+#define BF_AUDIOOUT_TEST_RSRVD4_V(e)            BF_AUDIOOUT_TEST_RSRVD4(BV_AUDIOOUT_TEST_RSRVD4__##e)
+#define BFM_AUDIOOUT_TEST_RSRVD4_V(v)           BM_AUDIOOUT_TEST_RSRVD4
+#define BP_AUDIOOUT_TEST_HP_ANTIPOP             28
+#define BM_AUDIOOUT_TEST_HP_ANTIPOP             0x70000000
+#define BF_AUDIOOUT_TEST_HP_ANTIPOP(v)          (((v) & 0x7) << 28)
+#define BFM_AUDIOOUT_TEST_HP_ANTIPOP(v)         BM_AUDIOOUT_TEST_HP_ANTIPOP
+#define BF_AUDIOOUT_TEST_HP_ANTIPOP_V(e)        BF_AUDIOOUT_TEST_HP_ANTIPOP(BV_AUDIOOUT_TEST_HP_ANTIPOP__##e)
+#define BFM_AUDIOOUT_TEST_HP_ANTIPOP_V(v)       BM_AUDIOOUT_TEST_HP_ANTIPOP
+#define BP_AUDIOOUT_TEST_RSRVD3                 27
+#define BM_AUDIOOUT_TEST_RSRVD3                 0x8000000
+#define BF_AUDIOOUT_TEST_RSRVD3(v)              (((v) & 0x1) << 27)
+#define BFM_AUDIOOUT_TEST_RSRVD3(v)             BM_AUDIOOUT_TEST_RSRVD3
+#define BF_AUDIOOUT_TEST_RSRVD3_V(e)            BF_AUDIOOUT_TEST_RSRVD3(BV_AUDIOOUT_TEST_RSRVD3__##e)
+#define BFM_AUDIOOUT_TEST_RSRVD3_V(v)           BM_AUDIOOUT_TEST_RSRVD3
+#define BP_AUDIOOUT_TEST_TM_ADCIN_TOHP          26
+#define BM_AUDIOOUT_TEST_TM_ADCIN_TOHP          0x4000000
+#define BF_AUDIOOUT_TEST_TM_ADCIN_TOHP(v)       (((v) & 0x1) << 26)
+#define BFM_AUDIOOUT_TEST_TM_ADCIN_TOHP(v)      BM_AUDIOOUT_TEST_TM_ADCIN_TOHP
+#define BF_AUDIOOUT_TEST_TM_ADCIN_TOHP_V(e)     BF_AUDIOOUT_TEST_TM_ADCIN_TOHP(BV_AUDIOOUT_TEST_TM_ADCIN_TOHP__##e)
+#define BFM_AUDIOOUT_TEST_TM_ADCIN_TOHP_V(v)    BM_AUDIOOUT_TEST_TM_ADCIN_TOHP
+#define BP_AUDIOOUT_TEST_TM_LOOP                25
+#define BM_AUDIOOUT_TEST_TM_LOOP                0x2000000
+#define BF_AUDIOOUT_TEST_TM_LOOP(v)             (((v) & 0x1) << 25)
+#define BFM_AUDIOOUT_TEST_TM_LOOP(v)            BM_AUDIOOUT_TEST_TM_LOOP
+#define BF_AUDIOOUT_TEST_TM_LOOP_V(e)           BF_AUDIOOUT_TEST_TM_LOOP(BV_AUDIOOUT_TEST_TM_LOOP__##e)
+#define BFM_AUDIOOUT_TEST_TM_LOOP_V(v)          BM_AUDIOOUT_TEST_TM_LOOP
+#define BP_AUDIOOUT_TEST_TM_HPCOMMON            24
+#define BM_AUDIOOUT_TEST_TM_HPCOMMON            0x1000000
+#define BF_AUDIOOUT_TEST_TM_HPCOMMON(v)         (((v) & 0x1) << 24)
+#define BFM_AUDIOOUT_TEST_TM_HPCOMMON(v)        BM_AUDIOOUT_TEST_TM_HPCOMMON
+#define BF_AUDIOOUT_TEST_TM_HPCOMMON_V(e)       BF_AUDIOOUT_TEST_TM_HPCOMMON(BV_AUDIOOUT_TEST_TM_HPCOMMON__##e)
+#define BFM_AUDIOOUT_TEST_TM_HPCOMMON_V(v)      BM_AUDIOOUT_TEST_TM_HPCOMMON
+#define BP_AUDIOOUT_TEST_HP_I1_ADJ              22
+#define BM_AUDIOOUT_TEST_HP_I1_ADJ              0xc00000
+#define BF_AUDIOOUT_TEST_HP_I1_ADJ(v)           (((v) & 0x3) << 22)
+#define BFM_AUDIOOUT_TEST_HP_I1_ADJ(v)          BM_AUDIOOUT_TEST_HP_I1_ADJ
+#define BF_AUDIOOUT_TEST_HP_I1_ADJ_V(e)         BF_AUDIOOUT_TEST_HP_I1_ADJ(BV_AUDIOOUT_TEST_HP_I1_ADJ__##e)
+#define BFM_AUDIOOUT_TEST_HP_I1_ADJ_V(v)        BM_AUDIOOUT_TEST_HP_I1_ADJ
+#define BP_AUDIOOUT_TEST_HP_IALL_ADJ            20
+#define BM_AUDIOOUT_TEST_HP_IALL_ADJ            0x300000
+#define BF_AUDIOOUT_TEST_HP_IALL_ADJ(v)         (((v) & 0x3) << 20)
+#define BFM_AUDIOOUT_TEST_HP_IALL_ADJ(v)        BM_AUDIOOUT_TEST_HP_IALL_ADJ
+#define BF_AUDIOOUT_TEST_HP_IALL_ADJ_V(e)       BF_AUDIOOUT_TEST_HP_IALL_ADJ(BV_AUDIOOUT_TEST_HP_IALL_ADJ__##e)
+#define BFM_AUDIOOUT_TEST_HP_IALL_ADJ_V(v)      BM_AUDIOOUT_TEST_HP_IALL_ADJ
+#define BP_AUDIOOUT_TEST_RSRVD2                 14
+#define BM_AUDIOOUT_TEST_RSRVD2                 0xfc000
+#define BF_AUDIOOUT_TEST_RSRVD2(v)              (((v) & 0x3f) << 14)
+#define BFM_AUDIOOUT_TEST_RSRVD2(v)             BM_AUDIOOUT_TEST_RSRVD2
+#define BF_AUDIOOUT_TEST_RSRVD2_V(e)            BF_AUDIOOUT_TEST_RSRVD2(BV_AUDIOOUT_TEST_RSRVD2__##e)
+#define BFM_AUDIOOUT_TEST_RSRVD2_V(v)           BM_AUDIOOUT_TEST_RSRVD2
+#define BP_AUDIOOUT_TEST_VAG_CLASSA             13
+#define BM_AUDIOOUT_TEST_VAG_CLASSA             0x2000
+#define BF_AUDIOOUT_TEST_VAG_CLASSA(v)          (((v) & 0x1) << 13)
+#define BFM_AUDIOOUT_TEST_VAG_CLASSA(v)         BM_AUDIOOUT_TEST_VAG_CLASSA
+#define BF_AUDIOOUT_TEST_VAG_CLASSA_V(e)        BF_AUDIOOUT_TEST_VAG_CLASSA(BV_AUDIOOUT_TEST_VAG_CLASSA__##e)
+#define BFM_AUDIOOUT_TEST_VAG_CLASSA_V(v)       BM_AUDIOOUT_TEST_VAG_CLASSA
+#define BP_AUDIOOUT_TEST_VAG_DOUBLE_I           12
+#define BM_AUDIOOUT_TEST_VAG_DOUBLE_I           0x1000
+#define BF_AUDIOOUT_TEST_VAG_DOUBLE_I(v)        (((v) & 0x1) << 12)
+#define BFM_AUDIOOUT_TEST_VAG_DOUBLE_I(v)       BM_AUDIOOUT_TEST_VAG_DOUBLE_I
+#define BF_AUDIOOUT_TEST_VAG_DOUBLE_I_V(e)      BF_AUDIOOUT_TEST_VAG_DOUBLE_I(BV_AUDIOOUT_TEST_VAG_DOUBLE_I__##e)
+#define BFM_AUDIOOUT_TEST_VAG_DOUBLE_I_V(v)     BM_AUDIOOUT_TEST_VAG_DOUBLE_I
+#define BP_AUDIOOUT_TEST_RSRVD1                 4
+#define BM_AUDIOOUT_TEST_RSRVD1                 0xff0
+#define BF_AUDIOOUT_TEST_RSRVD1(v)              (((v) & 0xff) << 4)
+#define BFM_AUDIOOUT_TEST_RSRVD1(v)             BM_AUDIOOUT_TEST_RSRVD1
+#define BF_AUDIOOUT_TEST_RSRVD1_V(e)            BF_AUDIOOUT_TEST_RSRVD1(BV_AUDIOOUT_TEST_RSRVD1__##e)
+#define BFM_AUDIOOUT_TEST_RSRVD1_V(v)           BM_AUDIOOUT_TEST_RSRVD1
+#define BP_AUDIOOUT_TEST_ADCTODAC_LOOP          3
+#define BM_AUDIOOUT_TEST_ADCTODAC_LOOP          0x8
+#define BF_AUDIOOUT_TEST_ADCTODAC_LOOP(v)       (((v) & 0x1) << 3)
+#define BFM_AUDIOOUT_TEST_ADCTODAC_LOOP(v)      BM_AUDIOOUT_TEST_ADCTODAC_LOOP
+#define BF_AUDIOOUT_TEST_ADCTODAC_LOOP_V(e)     BF_AUDIOOUT_TEST_ADCTODAC_LOOP(BV_AUDIOOUT_TEST_ADCTODAC_LOOP__##e)
+#define BFM_AUDIOOUT_TEST_ADCTODAC_LOOP_V(v)    BM_AUDIOOUT_TEST_ADCTODAC_LOOP
+#define BP_AUDIOOUT_TEST_DAC_CLASSA             2
+#define BM_AUDIOOUT_TEST_DAC_CLASSA             0x4
+#define BF_AUDIOOUT_TEST_DAC_CLASSA(v)          (((v) & 0x1) << 2)
+#define BFM_AUDIOOUT_TEST_DAC_CLASSA(v)         BM_AUDIOOUT_TEST_DAC_CLASSA
+#define BF_AUDIOOUT_TEST_DAC_CLASSA_V(e)        BF_AUDIOOUT_TEST_DAC_CLASSA(BV_AUDIOOUT_TEST_DAC_CLASSA__##e)
+#define BFM_AUDIOOUT_TEST_DAC_CLASSA_V(v)       BM_AUDIOOUT_TEST_DAC_CLASSA
+#define BP_AUDIOOUT_TEST_DAC_DOUBLE_I           1
+#define BM_AUDIOOUT_TEST_DAC_DOUBLE_I           0x2
+#define BF_AUDIOOUT_TEST_DAC_DOUBLE_I(v)        (((v) & 0x1) << 1)
+#define BFM_AUDIOOUT_TEST_DAC_DOUBLE_I(v)       BM_AUDIOOUT_TEST_DAC_DOUBLE_I
+#define BF_AUDIOOUT_TEST_DAC_DOUBLE_I_V(e)      BF_AUDIOOUT_TEST_DAC_DOUBLE_I(BV_AUDIOOUT_TEST_DAC_DOUBLE_I__##e)
+#define BFM_AUDIOOUT_TEST_DAC_DOUBLE_I_V(v)     BM_AUDIOOUT_TEST_DAC_DOUBLE_I
+#define BP_AUDIOOUT_TEST_DAC_DIS_RTZ            0
+#define BM_AUDIOOUT_TEST_DAC_DIS_RTZ            0x1
+#define BF_AUDIOOUT_TEST_DAC_DIS_RTZ(v)         (((v) & 0x1) << 0)
+#define BFM_AUDIOOUT_TEST_DAC_DIS_RTZ(v)        BM_AUDIOOUT_TEST_DAC_DIS_RTZ
+#define BF_AUDIOOUT_TEST_DAC_DIS_RTZ_V(e)       BF_AUDIOOUT_TEST_DAC_DIS_RTZ(BV_AUDIOOUT_TEST_DAC_DIS_RTZ__##e)
+#define BFM_AUDIOOUT_TEST_DAC_DIS_RTZ_V(v)      BM_AUDIOOUT_TEST_DAC_DIS_RTZ
+
+#define HW_AUDIOOUT_BISTCTRL                HW(AUDIOOUT_BISTCTRL)
+#define HWA_AUDIOOUT_BISTCTRL               (0x80048000 + 0xb0)
+#define HWT_AUDIOOUT_BISTCTRL               HWIO_32_RW
+#define HWN_AUDIOOUT_BISTCTRL               AUDIOOUT_BISTCTRL
+#define HWI_AUDIOOUT_BISTCTRL               
+#define HW_AUDIOOUT_BISTCTRL_SET            HW(AUDIOOUT_BISTCTRL_SET)
+#define HWA_AUDIOOUT_BISTCTRL_SET           (HWA_AUDIOOUT_BISTCTRL + 0x4)
+#define HWT_AUDIOOUT_BISTCTRL_SET           HWIO_32_WO
+#define HWN_AUDIOOUT_BISTCTRL_SET           AUDIOOUT_BISTCTRL
+#define HWI_AUDIOOUT_BISTCTRL_SET           
+#define HW_AUDIOOUT_BISTCTRL_CLR            HW(AUDIOOUT_BISTCTRL_CLR)
+#define HWA_AUDIOOUT_BISTCTRL_CLR           (HWA_AUDIOOUT_BISTCTRL + 0x8)
+#define HWT_AUDIOOUT_BISTCTRL_CLR           HWIO_32_WO
+#define HWN_AUDIOOUT_BISTCTRL_CLR           AUDIOOUT_BISTCTRL
+#define HWI_AUDIOOUT_BISTCTRL_CLR           
+#define HW_AUDIOOUT_BISTCTRL_TOG            HW(AUDIOOUT_BISTCTRL_TOG)
+#define HWA_AUDIOOUT_BISTCTRL_TOG           (HWA_AUDIOOUT_BISTCTRL + 0xc)
+#define HWT_AUDIOOUT_BISTCTRL_TOG           HWIO_32_WO
+#define HWN_AUDIOOUT_BISTCTRL_TOG           AUDIOOUT_BISTCTRL
+#define HWI_AUDIOOUT_BISTCTRL_TOG           
+#define BP_AUDIOOUT_BISTCTRL_RSVD0          4
+#define BM_AUDIOOUT_BISTCTRL_RSVD0          0xfffffff0
+#define BF_AUDIOOUT_BISTCTRL_RSVD0(v)       (((v) & 0xfffffff) << 4)
+#define BFM_AUDIOOUT_BISTCTRL_RSVD0(v)      BM_AUDIOOUT_BISTCTRL_RSVD0
+#define BF_AUDIOOUT_BISTCTRL_RSVD0_V(e)     BF_AUDIOOUT_BISTCTRL_RSVD0(BV_AUDIOOUT_BISTCTRL_RSVD0__##e)
+#define BFM_AUDIOOUT_BISTCTRL_RSVD0_V(v)    BM_AUDIOOUT_BISTCTRL_RSVD0
+#define BP_AUDIOOUT_BISTCTRL_FAIL           3
+#define BM_AUDIOOUT_BISTCTRL_FAIL           0x8
+#define BF_AUDIOOUT_BISTCTRL_FAIL(v)        (((v) & 0x1) << 3)
+#define BFM_AUDIOOUT_BISTCTRL_FAIL(v)       BM_AUDIOOUT_BISTCTRL_FAIL
+#define BF_AUDIOOUT_BISTCTRL_FAIL_V(e)      BF_AUDIOOUT_BISTCTRL_FAIL(BV_AUDIOOUT_BISTCTRL_FAIL__##e)
+#define BFM_AUDIOOUT_BISTCTRL_FAIL_V(v)     BM_AUDIOOUT_BISTCTRL_FAIL
+#define BP_AUDIOOUT_BISTCTRL_PASS           2
+#define BM_AUDIOOUT_BISTCTRL_PASS           0x4
+#define BF_AUDIOOUT_BISTCTRL_PASS(v)        (((v) & 0x1) << 2)
+#define BFM_AUDIOOUT_BISTCTRL_PASS(v)       BM_AUDIOOUT_BISTCTRL_PASS
+#define BF_AUDIOOUT_BISTCTRL_PASS_V(e)      BF_AUDIOOUT_BISTCTRL_PASS(BV_AUDIOOUT_BISTCTRL_PASS__##e)
+#define BFM_AUDIOOUT_BISTCTRL_PASS_V(v)     BM_AUDIOOUT_BISTCTRL_PASS
+#define BP_AUDIOOUT_BISTCTRL_DONE           1
+#define BM_AUDIOOUT_BISTCTRL_DONE           0x2
+#define BF_AUDIOOUT_BISTCTRL_DONE(v)        (((v) & 0x1) << 1)
+#define BFM_AUDIOOUT_BISTCTRL_DONE(v)       BM_AUDIOOUT_BISTCTRL_DONE
+#define BF_AUDIOOUT_BISTCTRL_DONE_V(e)      BF_AUDIOOUT_BISTCTRL_DONE(BV_AUDIOOUT_BISTCTRL_DONE__##e)
+#define BFM_AUDIOOUT_BISTCTRL_DONE_V(v)     BM_AUDIOOUT_BISTCTRL_DONE
+#define BP_AUDIOOUT_BISTCTRL_START          0
+#define BM_AUDIOOUT_BISTCTRL_START          0x1
+#define BF_AUDIOOUT_BISTCTRL_START(v)       (((v) & 0x1) << 0)
+#define BFM_AUDIOOUT_BISTCTRL_START(v)      BM_AUDIOOUT_BISTCTRL_START
+#define BF_AUDIOOUT_BISTCTRL_START_V(e)     BF_AUDIOOUT_BISTCTRL_START(BV_AUDIOOUT_BISTCTRL_START__##e)
+#define BFM_AUDIOOUT_BISTCTRL_START_V(v)    BM_AUDIOOUT_BISTCTRL_START
+
+#define HW_AUDIOOUT_BISTSTAT0               HW(AUDIOOUT_BISTSTAT0)
+#define HWA_AUDIOOUT_BISTSTAT0              (0x80048000 + 0xc0)
+#define HWT_AUDIOOUT_BISTSTAT0              HWIO_32_RW
+#define HWN_AUDIOOUT_BISTSTAT0              AUDIOOUT_BISTSTAT0
+#define HWI_AUDIOOUT_BISTSTAT0              
+#define HW_AUDIOOUT_BISTSTAT0_SET           HW(AUDIOOUT_BISTSTAT0_SET)
+#define HWA_AUDIOOUT_BISTSTAT0_SET          (HWA_AUDIOOUT_BISTSTAT0 + 0x4)
+#define HWT_AUDIOOUT_BISTSTAT0_SET          HWIO_32_WO
+#define HWN_AUDIOOUT_BISTSTAT0_SET          AUDIOOUT_BISTSTAT0
+#define HWI_AUDIOOUT_BISTSTAT0_SET          
+#define HW_AUDIOOUT_BISTSTAT0_CLR           HW(AUDIOOUT_BISTSTAT0_CLR)
+#define HWA_AUDIOOUT_BISTSTAT0_CLR          (HWA_AUDIOOUT_BISTSTAT0 + 0x8)
+#define HWT_AUDIOOUT_BISTSTAT0_CLR          HWIO_32_WO
+#define HWN_AUDIOOUT_BISTSTAT0_CLR          AUDIOOUT_BISTSTAT0
+#define HWI_AUDIOOUT_BISTSTAT0_CLR          
+#define HW_AUDIOOUT_BISTSTAT0_TOG           HW(AUDIOOUT_BISTSTAT0_TOG)
+#define HWA_AUDIOOUT_BISTSTAT0_TOG          (HWA_AUDIOOUT_BISTSTAT0 + 0xc)
+#define HWT_AUDIOOUT_BISTSTAT0_TOG          HWIO_32_WO
+#define HWN_AUDIOOUT_BISTSTAT0_TOG          AUDIOOUT_BISTSTAT0
+#define HWI_AUDIOOUT_BISTSTAT0_TOG          
+#define BP_AUDIOOUT_BISTSTAT0_RSVD0         24
+#define BM_AUDIOOUT_BISTSTAT0_RSVD0         0xff000000
+#define BF_AUDIOOUT_BISTSTAT0_RSVD0(v)      (((v) & 0xff) << 24)
+#define BFM_AUDIOOUT_BISTSTAT0_RSVD0(v)     BM_AUDIOOUT_BISTSTAT0_RSVD0
+#define BF_AUDIOOUT_BISTSTAT0_RSVD0_V(e)    BF_AUDIOOUT_BISTSTAT0_RSVD0(BV_AUDIOOUT_BISTSTAT0_RSVD0__##e)
+#define BFM_AUDIOOUT_BISTSTAT0_RSVD0_V(v)   BM_AUDIOOUT_BISTSTAT0_RSVD0
+#define BP_AUDIOOUT_BISTSTAT0_DATA          0
+#define BM_AUDIOOUT_BISTSTAT0_DATA          0xffffff
+#define BF_AUDIOOUT_BISTSTAT0_DATA(v)       (((v) & 0xffffff) << 0)
+#define BFM_AUDIOOUT_BISTSTAT0_DATA(v)      BM_AUDIOOUT_BISTSTAT0_DATA
+#define BF_AUDIOOUT_BISTSTAT0_DATA_V(e)     BF_AUDIOOUT_BISTSTAT0_DATA(BV_AUDIOOUT_BISTSTAT0_DATA__##e)
+#define BFM_AUDIOOUT_BISTSTAT0_DATA_V(v)    BM_AUDIOOUT_BISTSTAT0_DATA
+
+#define HW_AUDIOOUT_BISTSTAT1               HW(AUDIOOUT_BISTSTAT1)
+#define HWA_AUDIOOUT_BISTSTAT1              (0x80048000 + 0xd0)
+#define HWT_AUDIOOUT_BISTSTAT1              HWIO_32_RW
+#define HWN_AUDIOOUT_BISTSTAT1              AUDIOOUT_BISTSTAT1
+#define HWI_AUDIOOUT_BISTSTAT1              
+#define HW_AUDIOOUT_BISTSTAT1_SET           HW(AUDIOOUT_BISTSTAT1_SET)
+#define HWA_AUDIOOUT_BISTSTAT1_SET          (HWA_AUDIOOUT_BISTSTAT1 + 0x4)
+#define HWT_AUDIOOUT_BISTSTAT1_SET          HWIO_32_WO
+#define HWN_AUDIOOUT_BISTSTAT1_SET          AUDIOOUT_BISTSTAT1
+#define HWI_AUDIOOUT_BISTSTAT1_SET          
+#define HW_AUDIOOUT_BISTSTAT1_CLR           HW(AUDIOOUT_BISTSTAT1_CLR)
+#define HWA_AUDIOOUT_BISTSTAT1_CLR          (HWA_AUDIOOUT_BISTSTAT1 + 0x8)
+#define HWT_AUDIOOUT_BISTSTAT1_CLR          HWIO_32_WO
+#define HWN_AUDIOOUT_BISTSTAT1_CLR          AUDIOOUT_BISTSTAT1
+#define HWI_AUDIOOUT_BISTSTAT1_CLR          
+#define HW_AUDIOOUT_BISTSTAT1_TOG           HW(AUDIOOUT_BISTSTAT1_TOG)
+#define HWA_AUDIOOUT_BISTSTAT1_TOG          (HWA_AUDIOOUT_BISTSTAT1 + 0xc)
+#define HWT_AUDIOOUT_BISTSTAT1_TOG          HWIO_32_WO
+#define HWN_AUDIOOUT_BISTSTAT1_TOG          AUDIOOUT_BISTSTAT1
+#define HWI_AUDIOOUT_BISTSTAT1_TOG          
+#define BP_AUDIOOUT_BISTSTAT1_RSVD1         29
+#define BM_AUDIOOUT_BISTSTAT1_RSVD1         0xe0000000
+#define BF_AUDIOOUT_BISTSTAT1_RSVD1(v)      (((v) & 0x7) << 29)
+#define BFM_AUDIOOUT_BISTSTAT1_RSVD1(v)     BM_AUDIOOUT_BISTSTAT1_RSVD1
+#define BF_AUDIOOUT_BISTSTAT1_RSVD1_V(e)    BF_AUDIOOUT_BISTSTAT1_RSVD1(BV_AUDIOOUT_BISTSTAT1_RSVD1__##e)
+#define BFM_AUDIOOUT_BISTSTAT1_RSVD1_V(v)   BM_AUDIOOUT_BISTSTAT1_RSVD1
+#define BP_AUDIOOUT_BISTSTAT1_STATE         24
+#define BM_AUDIOOUT_BISTSTAT1_STATE         0x1f000000
+#define BF_AUDIOOUT_BISTSTAT1_STATE(v)      (((v) & 0x1f) << 24)
+#define BFM_AUDIOOUT_BISTSTAT1_STATE(v)     BM_AUDIOOUT_BISTSTAT1_STATE
+#define BF_AUDIOOUT_BISTSTAT1_STATE_V(e)    BF_AUDIOOUT_BISTSTAT1_STATE(BV_AUDIOOUT_BISTSTAT1_STATE__##e)
+#define BFM_AUDIOOUT_BISTSTAT1_STATE_V(v)   BM_AUDIOOUT_BISTSTAT1_STATE
+#define BP_AUDIOOUT_BISTSTAT1_RSVD0         8
+#define BM_AUDIOOUT_BISTSTAT1_RSVD0         0xffff00
+#define BF_AUDIOOUT_BISTSTAT1_RSVD0(v)      (((v) & 0xffff) << 8)
+#define BFM_AUDIOOUT_BISTSTAT1_RSVD0(v)     BM_AUDIOOUT_BISTSTAT1_RSVD0
+#define BF_AUDIOOUT_BISTSTAT1_RSVD0_V(e)    BF_AUDIOOUT_BISTSTAT1_RSVD0(BV_AUDIOOUT_BISTSTAT1_RSVD0__##e)
+#define BFM_AUDIOOUT_BISTSTAT1_RSVD0_V(v)   BM_AUDIOOUT_BISTSTAT1_RSVD0
+#define BP_AUDIOOUT_BISTSTAT1_ADDR          0
+#define BM_AUDIOOUT_BISTSTAT1_ADDR          0xff
+#define BF_AUDIOOUT_BISTSTAT1_ADDR(v)       (((v) & 0xff) << 0)
+#define BFM_AUDIOOUT_BISTSTAT1_ADDR(v)      BM_AUDIOOUT_BISTSTAT1_ADDR
+#define BF_AUDIOOUT_BISTSTAT1_ADDR_V(e)     BF_AUDIOOUT_BISTSTAT1_ADDR(BV_AUDIOOUT_BISTSTAT1_ADDR__##e)
+#define BFM_AUDIOOUT_BISTSTAT1_ADDR_V(v)    BM_AUDIOOUT_BISTSTAT1_ADDR
+
+#define HW_AUDIOOUT_ANACLKCTRL                      HW(AUDIOOUT_ANACLKCTRL)
+#define HWA_AUDIOOUT_ANACLKCTRL                     (0x80048000 + 0xe0)
+#define HWT_AUDIOOUT_ANACLKCTRL                     HWIO_32_RW
+#define HWN_AUDIOOUT_ANACLKCTRL                     AUDIOOUT_ANACLKCTRL
+#define HWI_AUDIOOUT_ANACLKCTRL                     
+#define HW_AUDIOOUT_ANACLKCTRL_SET                  HW(AUDIOOUT_ANACLKCTRL_SET)
+#define HWA_AUDIOOUT_ANACLKCTRL_SET                 (HWA_AUDIOOUT_ANACLKCTRL + 0x4)
+#define HWT_AUDIOOUT_ANACLKCTRL_SET                 HWIO_32_WO
+#define HWN_AUDIOOUT_ANACLKCTRL_SET                 AUDIOOUT_ANACLKCTRL
+#define HWI_AUDIOOUT_ANACLKCTRL_SET                 
+#define HW_AUDIOOUT_ANACLKCTRL_CLR                  HW(AUDIOOUT_ANACLKCTRL_CLR)
+#define HWA_AUDIOOUT_ANACLKCTRL_CLR                 (HWA_AUDIOOUT_ANACLKCTRL + 0x8)
+#define HWT_AUDIOOUT_ANACLKCTRL_CLR                 HWIO_32_WO
+#define HWN_AUDIOOUT_ANACLKCTRL_CLR                 AUDIOOUT_ANACLKCTRL
+#define HWI_AUDIOOUT_ANACLKCTRL_CLR                 
+#define HW_AUDIOOUT_ANACLKCTRL_TOG                  HW(AUDIOOUT_ANACLKCTRL_TOG)
+#define HWA_AUDIOOUT_ANACLKCTRL_TOG                 (HWA_AUDIOOUT_ANACLKCTRL + 0xc)
+#define HWT_AUDIOOUT_ANACLKCTRL_TOG                 HWIO_32_WO
+#define HWN_AUDIOOUT_ANACLKCTRL_TOG                 AUDIOOUT_ANACLKCTRL
+#define HWI_AUDIOOUT_ANACLKCTRL_TOG                 
+#define BP_AUDIOOUT_ANACLKCTRL_CLKGATE              31
+#define BM_AUDIOOUT_ANACLKCTRL_CLKGATE              0x80000000
+#define BF_AUDIOOUT_ANACLKCTRL_CLKGATE(v)           (((v) & 0x1) << 31)
+#define BFM_AUDIOOUT_ANACLKCTRL_CLKGATE(v)          BM_AUDIOOUT_ANACLKCTRL_CLKGATE
+#define BF_AUDIOOUT_ANACLKCTRL_CLKGATE_V(e)         BF_AUDIOOUT_ANACLKCTRL_CLKGATE(BV_AUDIOOUT_ANACLKCTRL_CLKGATE__##e)
+#define BFM_AUDIOOUT_ANACLKCTRL_CLKGATE_V(v)        BM_AUDIOOUT_ANACLKCTRL_CLKGATE
+#define BP_AUDIOOUT_ANACLKCTRL_RSRVD3               5
+#define BM_AUDIOOUT_ANACLKCTRL_RSRVD3               0x7fffffe0
+#define BF_AUDIOOUT_ANACLKCTRL_RSRVD3(v)            (((v) & 0x3ffffff) << 5)
+#define BFM_AUDIOOUT_ANACLKCTRL_RSRVD3(v)           BM_AUDIOOUT_ANACLKCTRL_RSRVD3
+#define BF_AUDIOOUT_ANACLKCTRL_RSRVD3_V(e)          BF_AUDIOOUT_ANACLKCTRL_RSRVD3(BV_AUDIOOUT_ANACLKCTRL_RSRVD3__##e)
+#define BFM_AUDIOOUT_ANACLKCTRL_RSRVD3_V(v)         BM_AUDIOOUT_ANACLKCTRL_RSRVD3
+#define BP_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK        4
+#define BM_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK        0x10
+#define BF_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK(v)     (((v) & 0x1) << 4)
+#define BFM_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK(v)    BM_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK
+#define BF_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK_V(e)   BF_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK(BV_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK__##e)
+#define BFM_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK_V(v)  BM_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK
+#define BP_AUDIOOUT_ANACLKCTRL_RSRVD2               3
+#define BM_AUDIOOUT_ANACLKCTRL_RSRVD2               0x8
+#define BF_AUDIOOUT_ANACLKCTRL_RSRVD2(v)            (((v) & 0x1) << 3)
+#define BFM_AUDIOOUT_ANACLKCTRL_RSRVD2(v)           BM_AUDIOOUT_ANACLKCTRL_RSRVD2
+#define BF_AUDIOOUT_ANACLKCTRL_RSRVD2_V(e)          BF_AUDIOOUT_ANACLKCTRL_RSRVD2(BV_AUDIOOUT_ANACLKCTRL_RSRVD2__##e)
+#define BFM_AUDIOOUT_ANACLKCTRL_RSRVD2_V(v)         BM_AUDIOOUT_ANACLKCTRL_RSRVD2
+#define BP_AUDIOOUT_ANACLKCTRL_DACDIV               0
+#define BM_AUDIOOUT_ANACLKCTRL_DACDIV               0x7
+#define BF_AUDIOOUT_ANACLKCTRL_DACDIV(v)            (((v) & 0x7) << 0)
+#define BFM_AUDIOOUT_ANACLKCTRL_DACDIV(v)           BM_AUDIOOUT_ANACLKCTRL_DACDIV
+#define BF_AUDIOOUT_ANACLKCTRL_DACDIV_V(e)          BF_AUDIOOUT_ANACLKCTRL_DACDIV(BV_AUDIOOUT_ANACLKCTRL_DACDIV__##e)
+#define BFM_AUDIOOUT_ANACLKCTRL_DACDIV_V(v)         BM_AUDIOOUT_ANACLKCTRL_DACDIV
+
+#define HW_AUDIOOUT_DATA            HW(AUDIOOUT_DATA)
+#define HWA_AUDIOOUT_DATA           (0x80048000 + 0xf0)
+#define HWT_AUDIOOUT_DATA           HWIO_32_RW
+#define HWN_AUDIOOUT_DATA           AUDIOOUT_DATA
+#define HWI_AUDIOOUT_DATA           
+#define HW_AUDIOOUT_DATA_SET        HW(AUDIOOUT_DATA_SET)
+#define HWA_AUDIOOUT_DATA_SET       (HWA_AUDIOOUT_DATA + 0x4)
+#define HWT_AUDIOOUT_DATA_SET       HWIO_32_WO
+#define HWN_AUDIOOUT_DATA_SET       AUDIOOUT_DATA
+#define HWI_AUDIOOUT_DATA_SET       
+#define HW_AUDIOOUT_DATA_CLR        HW(AUDIOOUT_DATA_CLR)
+#define HWA_AUDIOOUT_DATA_CLR       (HWA_AUDIOOUT_DATA + 0x8)
+#define HWT_AUDIOOUT_DATA_CLR       HWIO_32_WO
+#define HWN_AUDIOOUT_DATA_CLR       AUDIOOUT_DATA
+#define HWI_AUDIOOUT_DATA_CLR       
+#define HW_AUDIOOUT_DATA_TOG        HW(AUDIOOUT_DATA_TOG)
+#define HWA_AUDIOOUT_DATA_TOG       (HWA_AUDIOOUT_DATA + 0xc)
+#define HWT_AUDIOOUT_DATA_TOG       HWIO_32_WO
+#define HWN_AUDIOOUT_DATA_TOG       AUDIOOUT_DATA
+#define HWI_AUDIOOUT_DATA_TOG       
+#define BP_AUDIOOUT_DATA_HIGH       16
+#define BM_AUDIOOUT_DATA_HIGH       0xffff0000
+#define BF_AUDIOOUT_DATA_HIGH(v)    (((v) & 0xffff) << 16)
+#define BFM_AUDIOOUT_DATA_HIGH(v)   BM_AUDIOOUT_DATA_HIGH
+#define BF_AUDIOOUT_DATA_HIGH_V(e)  BF_AUDIOOUT_DATA_HIGH(BV_AUDIOOUT_DATA_HIGH__##e)
+#define BFM_AUDIOOUT_DATA_HIGH_V(v) BM_AUDIOOUT_DATA_HIGH
+#define BP_AUDIOOUT_DATA_LOW        0
+#define BM_AUDIOOUT_DATA_LOW        0xffff
+#define BF_AUDIOOUT_DATA_LOW(v)     (((v) & 0xffff) << 0)
+#define BFM_AUDIOOUT_DATA_LOW(v)    BM_AUDIOOUT_DATA_LOW
+#define BF_AUDIOOUT_DATA_LOW_V(e)   BF_AUDIOOUT_DATA_LOW(BV_AUDIOOUT_DATA_LOW__##e)
+#define BFM_AUDIOOUT_DATA_LOW_V(v)  BM_AUDIOOUT_DATA_LOW
+
+#define HW_AUDIOOUT_SPEAKERCTRL                 HW(AUDIOOUT_SPEAKERCTRL)
+#define HWA_AUDIOOUT_SPEAKERCTRL                (0x80048000 + 0x100)
+#define HWT_AUDIOOUT_SPEAKERCTRL                HWIO_32_RW
+#define HWN_AUDIOOUT_SPEAKERCTRL                AUDIOOUT_SPEAKERCTRL
+#define HWI_AUDIOOUT_SPEAKERCTRL                
+#define HW_AUDIOOUT_SPEAKERCTRL_SET             HW(AUDIOOUT_SPEAKERCTRL_SET)
+#define HWA_AUDIOOUT_SPEAKERCTRL_SET            (HWA_AUDIOOUT_SPEAKERCTRL + 0x4)
+#define HWT_AUDIOOUT_SPEAKERCTRL_SET            HWIO_32_WO
+#define HWN_AUDIOOUT_SPEAKERCTRL_SET            AUDIOOUT_SPEAKERCTRL
+#define HWI_AUDIOOUT_SPEAKERCTRL_SET            
+#define HW_AUDIOOUT_SPEAKERCTRL_CLR             HW(AUDIOOUT_SPEAKERCTRL_CLR)
+#define HWA_AUDIOOUT_SPEAKERCTRL_CLR            (HWA_AUDIOOUT_SPEAKERCTRL + 0x8)
+#define HWT_AUDIOOUT_SPEAKERCTRL_CLR            HWIO_32_WO
+#define HWN_AUDIOOUT_SPEAKERCTRL_CLR            AUDIOOUT_SPEAKERCTRL
+#define HWI_AUDIOOUT_SPEAKERCTRL_CLR            
+#define HW_AUDIOOUT_SPEAKERCTRL_TOG             HW(AUDIOOUT_SPEAKERCTRL_TOG)
+#define HWA_AUDIOOUT_SPEAKERCTRL_TOG            (HWA_AUDIOOUT_SPEAKERCTRL + 0xc)
+#define HWT_AUDIOOUT_SPEAKERCTRL_TOG            HWIO_32_WO
+#define HWN_AUDIOOUT_SPEAKERCTRL_TOG            AUDIOOUT_SPEAKERCTRL
+#define HWI_AUDIOOUT_SPEAKERCTRL_TOG            
+#define BP_AUDIOOUT_SPEAKERCTRL_RSRVD2          25
+#define BM_AUDIOOUT_SPEAKERCTRL_RSRVD2          0xfe000000
+#define BF_AUDIOOUT_SPEAKERCTRL_RSRVD2(v)       (((v) & 0x7f) << 25)
+#define BFM_AUDIOOUT_SPEAKERCTRL_RSRVD2(v)      BM_AUDIOOUT_SPEAKERCTRL_RSRVD2
+#define BF_AUDIOOUT_SPEAKERCTRL_RSRVD2_V(e)     BF_AUDIOOUT_SPEAKERCTRL_RSRVD2(BV_AUDIOOUT_SPEAKERCTRL_RSRVD2__##e)
+#define BFM_AUDIOOUT_SPEAKERCTRL_RSRVD2_V(v)    BM_AUDIOOUT_SPEAKERCTRL_RSRVD2
+#define BP_AUDIOOUT_SPEAKERCTRL_MUTE            24
+#define BM_AUDIOOUT_SPEAKERCTRL_MUTE            0x1000000
+#define BF_AUDIOOUT_SPEAKERCTRL_MUTE(v)         (((v) & 0x1) << 24)
+#define BFM_AUDIOOUT_SPEAKERCTRL_MUTE(v)        BM_AUDIOOUT_SPEAKERCTRL_MUTE
+#define BF_AUDIOOUT_SPEAKERCTRL_MUTE_V(e)       BF_AUDIOOUT_SPEAKERCTRL_MUTE(BV_AUDIOOUT_SPEAKERCTRL_MUTE__##e)
+#define BFM_AUDIOOUT_SPEAKERCTRL_MUTE_V(v)      BM_AUDIOOUT_SPEAKERCTRL_MUTE
+#define BP_AUDIOOUT_SPEAKERCTRL_I1_ADJ          22
+#define BM_AUDIOOUT_SPEAKERCTRL_I1_ADJ          0xc00000
+#define BF_AUDIOOUT_SPEAKERCTRL_I1_ADJ(v)       (((v) & 0x3) << 22)
+#define BFM_AUDIOOUT_SPEAKERCTRL_I1_ADJ(v)      BM_AUDIOOUT_SPEAKERCTRL_I1_ADJ
+#define BF_AUDIOOUT_SPEAKERCTRL_I1_ADJ_V(e)     BF_AUDIOOUT_SPEAKERCTRL_I1_ADJ(BV_AUDIOOUT_SPEAKERCTRL_I1_ADJ__##e)
+#define BFM_AUDIOOUT_SPEAKERCTRL_I1_ADJ_V(v)    BM_AUDIOOUT_SPEAKERCTRL_I1_ADJ
+#define BP_AUDIOOUT_SPEAKERCTRL_IALL_ADJ        20
+#define BM_AUDIOOUT_SPEAKERCTRL_IALL_ADJ        0x300000
+#define BF_AUDIOOUT_SPEAKERCTRL_IALL_ADJ(v)     (((v) & 0x3) << 20)
+#define BFM_AUDIOOUT_SPEAKERCTRL_IALL_ADJ(v)    BM_AUDIOOUT_SPEAKERCTRL_IALL_ADJ
+#define BF_AUDIOOUT_SPEAKERCTRL_IALL_ADJ_V(e)   BF_AUDIOOUT_SPEAKERCTRL_IALL_ADJ(BV_AUDIOOUT_SPEAKERCTRL_IALL_ADJ__##e)
+#define BFM_AUDIOOUT_SPEAKERCTRL_IALL_ADJ_V(v)  BM_AUDIOOUT_SPEAKERCTRL_IALL_ADJ
+#define BP_AUDIOOUT_SPEAKERCTRL_RSRVD1          16
+#define BM_AUDIOOUT_SPEAKERCTRL_RSRVD1          0xf0000
+#define BF_AUDIOOUT_SPEAKERCTRL_RSRVD1(v)       (((v) & 0xf) << 16)
+#define BFM_AUDIOOUT_SPEAKERCTRL_RSRVD1(v)      BM_AUDIOOUT_SPEAKERCTRL_RSRVD1
+#define BF_AUDIOOUT_SPEAKERCTRL_RSRVD1_V(e)     BF_AUDIOOUT_SPEAKERCTRL_RSRVD1(BV_AUDIOOUT_SPEAKERCTRL_RSRVD1__##e)
+#define BFM_AUDIOOUT_SPEAKERCTRL_RSRVD1_V(v)    BM_AUDIOOUT_SPEAKERCTRL_RSRVD1
+#define BP_AUDIOOUT_SPEAKERCTRL_POSDRIVER       14
+#define BM_AUDIOOUT_SPEAKERCTRL_POSDRIVER       0xc000
+#define BF_AUDIOOUT_SPEAKERCTRL_POSDRIVER(v)    (((v) & 0x3) << 14)
+#define BFM_AUDIOOUT_SPEAKERCTRL_POSDRIVER(v)   BM_AUDIOOUT_SPEAKERCTRL_POSDRIVER
+#define BF_AUDIOOUT_SPEAKERCTRL_POSDRIVER_V(e)  BF_AUDIOOUT_SPEAKERCTRL_POSDRIVER(BV_AUDIOOUT_SPEAKERCTRL_POSDRIVER__##e)
+#define BFM_AUDIOOUT_SPEAKERCTRL_POSDRIVER_V(v) BM_AUDIOOUT_SPEAKERCTRL_POSDRIVER
+#define BP_AUDIOOUT_SPEAKERCTRL_NEGDRIVER       12
+#define BM_AUDIOOUT_SPEAKERCTRL_NEGDRIVER       0x3000
+#define BF_AUDIOOUT_SPEAKERCTRL_NEGDRIVER(v)    (((v) & 0x3) << 12)
+#define BFM_AUDIOOUT_SPEAKERCTRL_NEGDRIVER(v)   BM_AUDIOOUT_SPEAKERCTRL_NEGDRIVER
+#define BF_AUDIOOUT_SPEAKERCTRL_NEGDRIVER_V(e)  BF_AUDIOOUT_SPEAKERCTRL_NEGDRIVER(BV_AUDIOOUT_SPEAKERCTRL_NEGDRIVER__##e)
+#define BFM_AUDIOOUT_SPEAKERCTRL_NEGDRIVER_V(v) BM_AUDIOOUT_SPEAKERCTRL_NEGDRIVER
+#define BP_AUDIOOUT_SPEAKERCTRL_RSRVD0          0
+#define BM_AUDIOOUT_SPEAKERCTRL_RSRVD0          0xfff
+#define BF_AUDIOOUT_SPEAKERCTRL_RSRVD0(v)       (((v) & 0xfff) << 0)
+#define BFM_AUDIOOUT_SPEAKERCTRL_RSRVD0(v)      BM_AUDIOOUT_SPEAKERCTRL_RSRVD0
+#define BF_AUDIOOUT_SPEAKERCTRL_RSRVD0_V(e)     BF_AUDIOOUT_SPEAKERCTRL_RSRVD0(BV_AUDIOOUT_SPEAKERCTRL_RSRVD0__##e)
+#define BFM_AUDIOOUT_SPEAKERCTRL_RSRVD0_V(v)    BM_AUDIOOUT_SPEAKERCTRL_RSRVD0
+
+#define HW_AUDIOOUT_VERSION             HW(AUDIOOUT_VERSION)
+#define HWA_AUDIOOUT_VERSION            (0x80048000 + 0x200)
+#define HWT_AUDIOOUT_VERSION            HWIO_32_RW
+#define HWN_AUDIOOUT_VERSION            AUDIOOUT_VERSION
+#define HWI_AUDIOOUT_VERSION            
+#define BP_AUDIOOUT_VERSION_MAJOR       24
+#define BM_AUDIOOUT_VERSION_MAJOR       0xff000000
+#define BF_AUDIOOUT_VERSION_MAJOR(v)    (((v) & 0xff) << 24)
+#define BFM_AUDIOOUT_VERSION_MAJOR(v)   BM_AUDIOOUT_VERSION_MAJOR
+#define BF_AUDIOOUT_VERSION_MAJOR_V(e)  BF_AUDIOOUT_VERSION_MAJOR(BV_AUDIOOUT_VERSION_MAJOR__##e)
+#define BFM_AUDIOOUT_VERSION_MAJOR_V(v) BM_AUDIOOUT_VERSION_MAJOR
+#define BP_AUDIOOUT_VERSION_MINOR       16
+#define BM_AUDIOOUT_VERSION_MINOR       0xff0000
+#define BF_AUDIOOUT_VERSION_MINOR(v)    (((v) & 0xff) << 16)
+#define BFM_AUDIOOUT_VERSION_MINOR(v)   BM_AUDIOOUT_VERSION_MINOR
+#define BF_AUDIOOUT_VERSION_MINOR_V(e)  BF_AUDIOOUT_VERSION_MINOR(BV_AUDIOOUT_VERSION_MINOR__##e)
+#define BFM_AUDIOOUT_VERSION_MINOR_V(v) BM_AUDIOOUT_VERSION_MINOR
+#define BP_AUDIOOUT_VERSION_STEP        0
+#define BM_AUDIOOUT_VERSION_STEP        0xffff
+#define BF_AUDIOOUT_VERSION_STEP(v)     (((v) & 0xffff) << 0)
+#define BFM_AUDIOOUT_VERSION_STEP(v)    BM_AUDIOOUT_VERSION_STEP
+#define BF_AUDIOOUT_VERSION_STEP_V(e)   BF_AUDIOOUT_VERSION_STEP(BV_AUDIOOUT_VERSION_STEP__##e)
+#define BFM_AUDIOOUT_VERSION_STEP_V(v)  BM_AUDIOOUT_VERSION_STEP
+
+#endif /* __HEADERGEN_IMX233_AUDIOOUT_H__*/
diff --git a/firmware/target/arm/imx233/regs/imx233/bch.h b/firmware/target/arm/imx233/regs/imx233/bch.h
new file mode 100644
index 0000000000..7b8ad3ade0
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/imx233/bch.h
@@ -0,0 +1,876 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * imx233 version: 2.4.0
+ * imx233 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_IMX233_BCH_H__
+#define __HEADERGEN_IMX233_BCH_H__
+
+#define HW_BCH_CTRL                             HW(BCH_CTRL)
+#define HWA_BCH_CTRL                            (0x8000a000 + 0x0)
+#define HWT_BCH_CTRL                            HWIO_32_RW
+#define HWN_BCH_CTRL                            BCH_CTRL
+#define HWI_BCH_CTRL                            
+#define HW_BCH_CTRL_SET                         HW(BCH_CTRL_SET)
+#define HWA_BCH_CTRL_SET                        (HWA_BCH_CTRL + 0x4)
+#define HWT_BCH_CTRL_SET                        HWIO_32_WO
+#define HWN_BCH_CTRL_SET                        BCH_CTRL
+#define HWI_BCH_CTRL_SET                        
+#define HW_BCH_CTRL_CLR                         HW(BCH_CTRL_CLR)
+#define HWA_BCH_CTRL_CLR                        (HWA_BCH_CTRL + 0x8)
+#define HWT_BCH_CTRL_CLR                        HWIO_32_WO
+#define HWN_BCH_CTRL_CLR                        BCH_CTRL
+#define HWI_BCH_CTRL_CLR                        
+#define HW_BCH_CTRL_TOG                         HW(BCH_CTRL_TOG)
+#define HWA_BCH_CTRL_TOG                        (HWA_BCH_CTRL + 0xc)
+#define HWT_BCH_CTRL_TOG                        HWIO_32_WO
+#define HWN_BCH_CTRL_TOG                        BCH_CTRL
+#define HWI_BCH_CTRL_TOG                        
+#define BP_BCH_CTRL_SFTRST                      31
+#define BM_BCH_CTRL_SFTRST                      0x80000000
+#define BV_BCH_CTRL_SFTRST__RUN                 0x0
+#define BV_BCH_CTRL_SFTRST__RESET               0x1
+#define BF_BCH_CTRL_SFTRST(v)                   (((v) & 0x1) << 31)
+#define BFM_BCH_CTRL_SFTRST(v)                  BM_BCH_CTRL_SFTRST
+#define BF_BCH_CTRL_SFTRST_V(e)                 BF_BCH_CTRL_SFTRST(BV_BCH_CTRL_SFTRST__##e)
+#define BFM_BCH_CTRL_SFTRST_V(v)                BM_BCH_CTRL_SFTRST
+#define BP_BCH_CTRL_CLKGATE                     30
+#define BM_BCH_CTRL_CLKGATE                     0x40000000
+#define BV_BCH_CTRL_CLKGATE__RUN                0x0
+#define BV_BCH_CTRL_CLKGATE__NO_CLKS            0x1
+#define BF_BCH_CTRL_CLKGATE(v)                  (((v) & 0x1) << 30)
+#define BFM_BCH_CTRL_CLKGATE(v)                 BM_BCH_CTRL_CLKGATE
+#define BF_BCH_CTRL_CLKGATE_V(e)                BF_BCH_CTRL_CLKGATE(BV_BCH_CTRL_CLKGATE__##e)
+#define BFM_BCH_CTRL_CLKGATE_V(v)               BM_BCH_CTRL_CLKGATE
+#define BP_BCH_CTRL_RSVD5                       23
+#define BM_BCH_CTRL_RSVD5                       0x3f800000
+#define BF_BCH_CTRL_RSVD5(v)                    (((v) & 0x7f) << 23)
+#define BFM_BCH_CTRL_RSVD5(v)                   BM_BCH_CTRL_RSVD5
+#define BF_BCH_CTRL_RSVD5_V(e)                  BF_BCH_CTRL_RSVD5(BV_BCH_CTRL_RSVD5__##e)
+#define BFM_BCH_CTRL_RSVD5_V(v)                 BM_BCH_CTRL_RSVD5
+#define BP_BCH_CTRL_DEBUGSYNDROME               22
+#define BM_BCH_CTRL_DEBUGSYNDROME               0x400000
+#define BF_BCH_CTRL_DEBUGSYNDROME(v)            (((v) & 0x1) << 22)
+#define BFM_BCH_CTRL_DEBUGSYNDROME(v)           BM_BCH_CTRL_DEBUGSYNDROME
+#define BF_BCH_CTRL_DEBUGSYNDROME_V(e)          BF_BCH_CTRL_DEBUGSYNDROME(BV_BCH_CTRL_DEBUGSYNDROME__##e)
+#define BFM_BCH_CTRL_DEBUGSYNDROME_V(v)         BM_BCH_CTRL_DEBUGSYNDROME
+#define BP_BCH_CTRL_RSVD4                       20
+#define BM_BCH_CTRL_RSVD4                       0x300000
+#define BF_BCH_CTRL_RSVD4(v)                    (((v) & 0x3) << 20)
+#define BFM_BCH_CTRL_RSVD4(v)                   BM_BCH_CTRL_RSVD4
+#define BF_BCH_CTRL_RSVD4_V(e)                  BF_BCH_CTRL_RSVD4(BV_BCH_CTRL_RSVD4__##e)
+#define BFM_BCH_CTRL_RSVD4_V(v)                 BM_BCH_CTRL_RSVD4
+#define BP_BCH_CTRL_M2M_LAYOUT                  18
+#define BM_BCH_CTRL_M2M_LAYOUT                  0xc0000
+#define BF_BCH_CTRL_M2M_LAYOUT(v)               (((v) & 0x3) << 18)
+#define BFM_BCH_CTRL_M2M_LAYOUT(v)              BM_BCH_CTRL_M2M_LAYOUT
+#define BF_BCH_CTRL_M2M_LAYOUT_V(e)             BF_BCH_CTRL_M2M_LAYOUT(BV_BCH_CTRL_M2M_LAYOUT__##e)
+#define BFM_BCH_CTRL_M2M_LAYOUT_V(v)            BM_BCH_CTRL_M2M_LAYOUT
+#define BP_BCH_CTRL_M2M_ENCODE                  17
+#define BM_BCH_CTRL_M2M_ENCODE                  0x20000
+#define BF_BCH_CTRL_M2M_ENCODE(v)               (((v) & 0x1) << 17)
+#define BFM_BCH_CTRL_M2M_ENCODE(v)              BM_BCH_CTRL_M2M_ENCODE
+#define BF_BCH_CTRL_M2M_ENCODE_V(e)             BF_BCH_CTRL_M2M_ENCODE(BV_BCH_CTRL_M2M_ENCODE__##e)
+#define BFM_BCH_CTRL_M2M_ENCODE_V(v)            BM_BCH_CTRL_M2M_ENCODE
+#define BP_BCH_CTRL_M2M_ENABLE                  16
+#define BM_BCH_CTRL_M2M_ENABLE                  0x10000
+#define BF_BCH_CTRL_M2M_ENABLE(v)               (((v) & 0x1) << 16)
+#define BFM_BCH_CTRL_M2M_ENABLE(v)              BM_BCH_CTRL_M2M_ENABLE
+#define BF_BCH_CTRL_M2M_ENABLE_V(e)             BF_BCH_CTRL_M2M_ENABLE(BV_BCH_CTRL_M2M_ENABLE__##e)
+#define BFM_BCH_CTRL_M2M_ENABLE_V(v)            BM_BCH_CTRL_M2M_ENABLE
+#define BP_BCH_CTRL_RSVD3                       11
+#define BM_BCH_CTRL_RSVD3                       0xf800
+#define BF_BCH_CTRL_RSVD3(v)                    (((v) & 0x1f) << 11)
+#define BFM_BCH_CTRL_RSVD3(v)                   BM_BCH_CTRL_RSVD3
+#define BF_BCH_CTRL_RSVD3_V(e)                  BF_BCH_CTRL_RSVD3(BV_BCH_CTRL_RSVD3__##e)
+#define BFM_BCH_CTRL_RSVD3_V(v)                 BM_BCH_CTRL_RSVD3
+#define BP_BCH_CTRL_DEBUG_STALL_IRQ_EN          10
+#define BM_BCH_CTRL_DEBUG_STALL_IRQ_EN          0x400
+#define BF_BCH_CTRL_DEBUG_STALL_IRQ_EN(v)       (((v) & 0x1) << 10)
+#define BFM_BCH_CTRL_DEBUG_STALL_IRQ_EN(v)      BM_BCH_CTRL_DEBUG_STALL_IRQ_EN
+#define BF_BCH_CTRL_DEBUG_STALL_IRQ_EN_V(e)     BF_BCH_CTRL_DEBUG_STALL_IRQ_EN(BV_BCH_CTRL_DEBUG_STALL_IRQ_EN__##e)
+#define BFM_BCH_CTRL_DEBUG_STALL_IRQ_EN_V(v)    BM_BCH_CTRL_DEBUG_STALL_IRQ_EN
+#define BP_BCH_CTRL_RSVD2                       9
+#define BM_BCH_CTRL_RSVD2                       0x200
+#define BF_BCH_CTRL_RSVD2(v)                    (((v) & 0x1) << 9)
+#define BFM_BCH_CTRL_RSVD2(v)                   BM_BCH_CTRL_RSVD2
+#define BF_BCH_CTRL_RSVD2_V(e)                  BF_BCH_CTRL_RSVD2(BV_BCH_CTRL_RSVD2__##e)
+#define BFM_BCH_CTRL_RSVD2_V(v)                 BM_BCH_CTRL_RSVD2
+#define BP_BCH_CTRL_COMPLETE_IRQ_EN             8
+#define BM_BCH_CTRL_COMPLETE_IRQ_EN             0x100
+#define BF_BCH_CTRL_COMPLETE_IRQ_EN(v)          (((v) & 0x1) << 8)
+#define BFM_BCH_CTRL_COMPLETE_IRQ_EN(v)         BM_BCH_CTRL_COMPLETE_IRQ_EN
+#define BF_BCH_CTRL_COMPLETE_IRQ_EN_V(e)        BF_BCH_CTRL_COMPLETE_IRQ_EN(BV_BCH_CTRL_COMPLETE_IRQ_EN__##e)
+#define BFM_BCH_CTRL_COMPLETE_IRQ_EN_V(v)       BM_BCH_CTRL_COMPLETE_IRQ_EN
+#define BP_BCH_CTRL_RSVD1                       4
+#define BM_BCH_CTRL_RSVD1                       0xf0
+#define BF_BCH_CTRL_RSVD1(v)                    (((v) & 0xf) << 4)
+#define BFM_BCH_CTRL_RSVD1(v)                   BM_BCH_CTRL_RSVD1
+#define BF_BCH_CTRL_RSVD1_V(e)                  BF_BCH_CTRL_RSVD1(BV_BCH_CTRL_RSVD1__##e)
+#define BFM_BCH_CTRL_RSVD1_V(v)                 BM_BCH_CTRL_RSVD1
+#define BP_BCH_CTRL_BM_ERROR_IRQ                3
+#define BM_BCH_CTRL_BM_ERROR_IRQ                0x8
+#define BF_BCH_CTRL_BM_ERROR_IRQ(v)             (((v) & 0x1) << 3)
+#define BFM_BCH_CTRL_BM_ERROR_IRQ(v)            BM_BCH_CTRL_BM_ERROR_IRQ
+#define BF_BCH_CTRL_BM_ERROR_IRQ_V(e)           BF_BCH_CTRL_BM_ERROR_IRQ(BV_BCH_CTRL_BM_ERROR_IRQ__##e)
+#define BFM_BCH_CTRL_BM_ERROR_IRQ_V(v)          BM_BCH_CTRL_BM_ERROR_IRQ
+#define BP_BCH_CTRL_DEBUG_STALL_IRQ             2
+#define BM_BCH_CTRL_DEBUG_STALL_IRQ             0x4
+#define BF_BCH_CTRL_DEBUG_STALL_IRQ(v)          (((v) & 0x1) << 2)
+#define BFM_BCH_CTRL_DEBUG_STALL_IRQ(v)         BM_BCH_CTRL_DEBUG_STALL_IRQ
+#define BF_BCH_CTRL_DEBUG_STALL_IRQ_V(e)        BF_BCH_CTRL_DEBUG_STALL_IRQ(BV_BCH_CTRL_DEBUG_STALL_IRQ__##e)
+#define BFM_BCH_CTRL_DEBUG_STALL_IRQ_V(v)       BM_BCH_CTRL_DEBUG_STALL_IRQ
+#define BP_BCH_CTRL_RSVD0                       1
+#define BM_BCH_CTRL_RSVD0                       0x2
+#define BF_BCH_CTRL_RSVD0(v)                    (((v) & 0x1) << 1)
+#define BFM_BCH_CTRL_RSVD0(v)                   BM_BCH_CTRL_RSVD0
+#define BF_BCH_CTRL_RSVD0_V(e)                  BF_BCH_CTRL_RSVD0(BV_BCH_CTRL_RSVD0__##e)
+#define BFM_BCH_CTRL_RSVD0_V(v)                 BM_BCH_CTRL_RSVD0
+#define BP_BCH_CTRL_COMPLETE_IRQ                0
+#define BM_BCH_CTRL_COMPLETE_IRQ                0x1
+#define BF_BCH_CTRL_COMPLETE_IRQ(v)             (((v) & 0x1) << 0)
+#define BFM_BCH_CTRL_COMPLETE_IRQ(v)            BM_BCH_CTRL_COMPLETE_IRQ
+#define BF_BCH_CTRL_COMPLETE_IRQ_V(e)           BF_BCH_CTRL_COMPLETE_IRQ(BV_BCH_CTRL_COMPLETE_IRQ__##e)
+#define BFM_BCH_CTRL_COMPLETE_IRQ_V(v)          BM_BCH_CTRL_COMPLETE_IRQ
+
+#define HW_BCH_STATUS0                              HW(BCH_STATUS0)
+#define HWA_BCH_STATUS0                             (0x8000a000 + 0x10)
+#define HWT_BCH_STATUS0                             HWIO_32_RW
+#define HWN_BCH_STATUS0                             BCH_STATUS0
+#define HWI_BCH_STATUS0                             
+#define BP_BCH_STATUS0_HANDLE                       20
+#define BM_BCH_STATUS0_HANDLE                       0xfff00000
+#define BF_BCH_STATUS0_HANDLE(v)                    (((v) & 0xfff) << 20)
+#define BFM_BCH_STATUS0_HANDLE(v)                   BM_BCH_STATUS0_HANDLE
+#define BF_BCH_STATUS0_HANDLE_V(e)                  BF_BCH_STATUS0_HANDLE(BV_BCH_STATUS0_HANDLE__##e)
+#define BFM_BCH_STATUS0_HANDLE_V(v)                 BM_BCH_STATUS0_HANDLE
+#define BP_BCH_STATUS0_COMPLETED_CE                 16
+#define BM_BCH_STATUS0_COMPLETED_CE                 0xf0000
+#define BF_BCH_STATUS0_COMPLETED_CE(v)              (((v) & 0xf) << 16)
+#define BFM_BCH_STATUS0_COMPLETED_CE(v)             BM_BCH_STATUS0_COMPLETED_CE
+#define BF_BCH_STATUS0_COMPLETED_CE_V(e)            BF_BCH_STATUS0_COMPLETED_CE(BV_BCH_STATUS0_COMPLETED_CE__##e)
+#define BFM_BCH_STATUS0_COMPLETED_CE_V(v)           BM_BCH_STATUS0_COMPLETED_CE
+#define BP_BCH_STATUS0_STATUS_BLK0                  8
+#define BM_BCH_STATUS0_STATUS_BLK0                  0xff00
+#define BV_BCH_STATUS0_STATUS_BLK0__ZERO            0x0
+#define BV_BCH_STATUS0_STATUS_BLK0__ERROR1          0x1
+#define BV_BCH_STATUS0_STATUS_BLK0__ERROR2          0x2
+#define BV_BCH_STATUS0_STATUS_BLK0__ERROR3          0x3
+#define BV_BCH_STATUS0_STATUS_BLK0__ERROR4          0x4
+#define BV_BCH_STATUS0_STATUS_BLK0__UNCORRECTABLE   0xfe
+#define BV_BCH_STATUS0_STATUS_BLK0__ERASED          0xff
+#define BF_BCH_STATUS0_STATUS_BLK0(v)               (((v) & 0xff) << 8)
+#define BFM_BCH_STATUS0_STATUS_BLK0(v)              BM_BCH_STATUS0_STATUS_BLK0
+#define BF_BCH_STATUS0_STATUS_BLK0_V(e)             BF_BCH_STATUS0_STATUS_BLK0(BV_BCH_STATUS0_STATUS_BLK0__##e)
+#define BFM_BCH_STATUS0_STATUS_BLK0_V(v)            BM_BCH_STATUS0_STATUS_BLK0
+#define BP_BCH_STATUS0_RSVD1                        5
+#define BM_BCH_STATUS0_RSVD1                        0xe0
+#define BF_BCH_STATUS0_RSVD1(v)                     (((v) & 0x7) << 5)
+#define BFM_BCH_STATUS0_RSVD1(v)                    BM_BCH_STATUS0_RSVD1
+#define BF_BCH_STATUS0_RSVD1_V(e)                   BF_BCH_STATUS0_RSVD1(BV_BCH_STATUS0_RSVD1__##e)
+#define BFM_BCH_STATUS0_RSVD1_V(v)                  BM_BCH_STATUS0_RSVD1
+#define BP_BCH_STATUS0_ALLONES                      4
+#define BM_BCH_STATUS0_ALLONES                      0x10
+#define BF_BCH_STATUS0_ALLONES(v)                   (((v) & 0x1) << 4)
+#define BFM_BCH_STATUS0_ALLONES(v)                  BM_BCH_STATUS0_ALLONES
+#define BF_BCH_STATUS0_ALLONES_V(e)                 BF_BCH_STATUS0_ALLONES(BV_BCH_STATUS0_ALLONES__##e)
+#define BFM_BCH_STATUS0_ALLONES_V(v)                BM_BCH_STATUS0_ALLONES
+#define BP_BCH_STATUS0_CORRECTED                    3
+#define BM_BCH_STATUS0_CORRECTED                    0x8
+#define BF_BCH_STATUS0_CORRECTED(v)                 (((v) & 0x1) << 3)
+#define BFM_BCH_STATUS0_CORRECTED(v)                BM_BCH_STATUS0_CORRECTED
+#define BF_BCH_STATUS0_CORRECTED_V(e)               BF_BCH_STATUS0_CORRECTED(BV_BCH_STATUS0_CORRECTED__##e)
+#define BFM_BCH_STATUS0_CORRECTED_V(v)              BM_BCH_STATUS0_CORRECTED
+#define BP_BCH_STATUS0_UNCORRECTABLE                2
+#define BM_BCH_STATUS0_UNCORRECTABLE                0x4
+#define BF_BCH_STATUS0_UNCORRECTABLE(v)             (((v) & 0x1) << 2)
+#define BFM_BCH_STATUS0_UNCORRECTABLE(v)            BM_BCH_STATUS0_UNCORRECTABLE
+#define BF_BCH_STATUS0_UNCORRECTABLE_V(e)           BF_BCH_STATUS0_UNCORRECTABLE(BV_BCH_STATUS0_UNCORRECTABLE__##e)
+#define BFM_BCH_STATUS0_UNCORRECTABLE_V(v)          BM_BCH_STATUS0_UNCORRECTABLE
+#define BP_BCH_STATUS0_RSVD0                        0
+#define BM_BCH_STATUS0_RSVD0                        0x3
+#define BF_BCH_STATUS0_RSVD0(v)                     (((v) & 0x3) << 0)
+#define BFM_BCH_STATUS0_RSVD0(v)                    BM_BCH_STATUS0_RSVD0
+#define BF_BCH_STATUS0_RSVD0_V(e)                   BF_BCH_STATUS0_RSVD0(BV_BCH_STATUS0_RSVD0__##e)
+#define BFM_BCH_STATUS0_RSVD0_V(v)                  BM_BCH_STATUS0_RSVD0
+
+#define HW_BCH_MODE                         HW(BCH_MODE)
+#define HWA_BCH_MODE                        (0x8000a000 + 0x20)
+#define HWT_BCH_MODE                        HWIO_32_RW
+#define HWN_BCH_MODE                        BCH_MODE
+#define HWI_BCH_MODE                        
+#define BP_BCH_MODE_RSVD                    8
+#define BM_BCH_MODE_RSVD                    0xffffff00
+#define BF_BCH_MODE_RSVD(v)                 (((v) & 0xffffff) << 8)
+#define BFM_BCH_MODE_RSVD(v)                BM_BCH_MODE_RSVD
+#define BF_BCH_MODE_RSVD_V(e)               BF_BCH_MODE_RSVD(BV_BCH_MODE_RSVD__##e)
+#define BFM_BCH_MODE_RSVD_V(v)              BM_BCH_MODE_RSVD
+#define BP_BCH_MODE_ERASE_THRESHOLD         0
+#define BM_BCH_MODE_ERASE_THRESHOLD         0xff
+#define BF_BCH_MODE_ERASE_THRESHOLD(v)      (((v) & 0xff) << 0)
+#define BFM_BCH_MODE_ERASE_THRESHOLD(v)     BM_BCH_MODE_ERASE_THRESHOLD
+#define BF_BCH_MODE_ERASE_THRESHOLD_V(e)    BF_BCH_MODE_ERASE_THRESHOLD(BV_BCH_MODE_ERASE_THRESHOLD__##e)
+#define BFM_BCH_MODE_ERASE_THRESHOLD_V(v)   BM_BCH_MODE_ERASE_THRESHOLD
+
+#define HW_BCH_ENCODEPTR            HW(BCH_ENCODEPTR)
+#define HWA_BCH_ENCODEPTR           (0x8000a000 + 0x30)
+#define HWT_BCH_ENCODEPTR           HWIO_32_RW
+#define HWN_BCH_ENCODEPTR           BCH_ENCODEPTR
+#define HWI_BCH_ENCODEPTR           
+#define BP_BCH_ENCODEPTR_ADDR       0
+#define BM_BCH_ENCODEPTR_ADDR       0xffffffff
+#define BF_BCH_ENCODEPTR_ADDR(v)    (((v) & 0xffffffff) << 0)
+#define BFM_BCH_ENCODEPTR_ADDR(v)   BM_BCH_ENCODEPTR_ADDR
+#define BF_BCH_ENCODEPTR_ADDR_V(e)  BF_BCH_ENCODEPTR_ADDR(BV_BCH_ENCODEPTR_ADDR__##e)
+#define BFM_BCH_ENCODEPTR_ADDR_V(v) BM_BCH_ENCODEPTR_ADDR
+
+#define HW_BCH_DATAPTR              HW(BCH_DATAPTR)
+#define HWA_BCH_DATAPTR             (0x8000a000 + 0x40)
+#define HWT_BCH_DATAPTR             HWIO_32_RW
+#define HWN_BCH_DATAPTR             BCH_DATAPTR
+#define HWI_BCH_DATAPTR             
+#define BP_BCH_DATAPTR_ADDR         0
+#define BM_BCH_DATAPTR_ADDR         0xffffffff
+#define BF_BCH_DATAPTR_ADDR(v)      (((v) & 0xffffffff) << 0)
+#define BFM_BCH_DATAPTR_ADDR(v)     BM_BCH_DATAPTR_ADDR
+#define BF_BCH_DATAPTR_ADDR_V(e)    BF_BCH_DATAPTR_ADDR(BV_BCH_DATAPTR_ADDR__##e)
+#define BFM_BCH_DATAPTR_ADDR_V(v)   BM_BCH_DATAPTR_ADDR
+
+#define HW_BCH_METAPTR              HW(BCH_METAPTR)
+#define HWA_BCH_METAPTR             (0x8000a000 + 0x50)
+#define HWT_BCH_METAPTR             HWIO_32_RW
+#define HWN_BCH_METAPTR             BCH_METAPTR
+#define HWI_BCH_METAPTR             
+#define BP_BCH_METAPTR_ADDR         0
+#define BM_BCH_METAPTR_ADDR         0xffffffff
+#define BF_BCH_METAPTR_ADDR(v)      (((v) & 0xffffffff) << 0)
+#define BFM_BCH_METAPTR_ADDR(v)     BM_BCH_METAPTR_ADDR
+#define BF_BCH_METAPTR_ADDR_V(e)    BF_BCH_METAPTR_ADDR(BV_BCH_METAPTR_ADDR__##e)
+#define BFM_BCH_METAPTR_ADDR_V(v)   BM_BCH_METAPTR_ADDR
+
+#define HW_BCH_LAYOUTSELECT                     HW(BCH_LAYOUTSELECT)
+#define HWA_BCH_LAYOUTSELECT                    (0x8000a000 + 0x70)
+#define HWT_BCH_LAYOUTSELECT                    HWIO_32_RW
+#define HWN_BCH_LAYOUTSELECT                    BCH_LAYOUTSELECT
+#define HWI_BCH_LAYOUTSELECT                    
+#define BP_BCH_LAYOUTSELECT_CS15_SELECT         30
+#define BM_BCH_LAYOUTSELECT_CS15_SELECT         0xc0000000
+#define BF_BCH_LAYOUTSELECT_CS15_SELECT(v)      (((v) & 0x3) << 30)
+#define BFM_BCH_LAYOUTSELECT_CS15_SELECT(v)     BM_BCH_LAYOUTSELECT_CS15_SELECT
+#define BF_BCH_LAYOUTSELECT_CS15_SELECT_V(e)    BF_BCH_LAYOUTSELECT_CS15_SELECT(BV_BCH_LAYOUTSELECT_CS15_SELECT__##e)
+#define BFM_BCH_LAYOUTSELECT_CS15_SELECT_V(v)   BM_BCH_LAYOUTSELECT_CS15_SELECT
+#define BP_BCH_LAYOUTSELECT_CS14_SELECT         28
+#define BM_BCH_LAYOUTSELECT_CS14_SELECT         0x30000000
+#define BF_BCH_LAYOUTSELECT_CS14_SELECT(v)      (((v) & 0x3) << 28)
+#define BFM_BCH_LAYOUTSELECT_CS14_SELECT(v)     BM_BCH_LAYOUTSELECT_CS14_SELECT
+#define BF_BCH_LAYOUTSELECT_CS14_SELECT_V(e)    BF_BCH_LAYOUTSELECT_CS14_SELECT(BV_BCH_LAYOUTSELECT_CS14_SELECT__##e)
+#define BFM_BCH_LAYOUTSELECT_CS14_SELECT_V(v)   BM_BCH_LAYOUTSELECT_CS14_SELECT
+#define BP_BCH_LAYOUTSELECT_CS13_SELECT         26
+#define BM_BCH_LAYOUTSELECT_CS13_SELECT         0xc000000
+#define BF_BCH_LAYOUTSELECT_CS13_SELECT(v)      (((v) & 0x3) << 26)
+#define BFM_BCH_LAYOUTSELECT_CS13_SELECT(v)     BM_BCH_LAYOUTSELECT_CS13_SELECT
+#define BF_BCH_LAYOUTSELECT_CS13_SELECT_V(e)    BF_BCH_LAYOUTSELECT_CS13_SELECT(BV_BCH_LAYOUTSELECT_CS13_SELECT__##e)
+#define BFM_BCH_LAYOUTSELECT_CS13_SELECT_V(v)   BM_BCH_LAYOUTSELECT_CS13_SELECT
+#define BP_BCH_LAYOUTSELECT_CS12_SELECT         24
+#define BM_BCH_LAYOUTSELECT_CS12_SELECT         0x3000000
+#define BF_BCH_LAYOUTSELECT_CS12_SELECT(v)      (((v) & 0x3) << 24)
+#define BFM_BCH_LAYOUTSELECT_CS12_SELECT(v)     BM_BCH_LAYOUTSELECT_CS12_SELECT
+#define BF_BCH_LAYOUTSELECT_CS12_SELECT_V(e)    BF_BCH_LAYOUTSELECT_CS12_SELECT(BV_BCH_LAYOUTSELECT_CS12_SELECT__##e)
+#define BFM_BCH_LAYOUTSELECT_CS12_SELECT_V(v)   BM_BCH_LAYOUTSELECT_CS12_SELECT
+#define BP_BCH_LAYOUTSELECT_CS11_SELECT         22
+#define BM_BCH_LAYOUTSELECT_CS11_SELECT         0xc00000
+#define BF_BCH_LAYOUTSELECT_CS11_SELECT(v)      (((v) & 0x3) << 22)
+#define BFM_BCH_LAYOUTSELECT_CS11_SELECT(v)     BM_BCH_LAYOUTSELECT_CS11_SELECT
+#define BF_BCH_LAYOUTSELECT_CS11_SELECT_V(e)    BF_BCH_LAYOUTSELECT_CS11_SELECT(BV_BCH_LAYOUTSELECT_CS11_SELECT__##e)
+#define BFM_BCH_LAYOUTSELECT_CS11_SELECT_V(v)   BM_BCH_LAYOUTSELECT_CS11_SELECT
+#define BP_BCH_LAYOUTSELECT_CS10_SELECT         20
+#define BM_BCH_LAYOUTSELECT_CS10_SELECT         0x300000
+#define BF_BCH_LAYOUTSELECT_CS10_SELECT(v)      (((v) & 0x3) << 20)
+#define BFM_BCH_LAYOUTSELECT_CS10_SELECT(v)     BM_BCH_LAYOUTSELECT_CS10_SELECT
+#define BF_BCH_LAYOUTSELECT_CS10_SELECT_V(e)    BF_BCH_LAYOUTSELECT_CS10_SELECT(BV_BCH_LAYOUTSELECT_CS10_SELECT__##e)
+#define BFM_BCH_LAYOUTSELECT_CS10_SELECT_V(v)   BM_BCH_LAYOUTSELECT_CS10_SELECT
+#define BP_BCH_LAYOUTSELECT_CS9_SELECT          18
+#define BM_BCH_LAYOUTSELECT_CS9_SELECT          0xc0000
+#define BF_BCH_LAYOUTSELECT_CS9_SELECT(v)       (((v) & 0x3) << 18)
+#define BFM_BCH_LAYOUTSELECT_CS9_SELECT(v)      BM_BCH_LAYOUTSELECT_CS9_SELECT
+#define BF_BCH_LAYOUTSELECT_CS9_SELECT_V(e)     BF_BCH_LAYOUTSELECT_CS9_SELECT(BV_BCH_LAYOUTSELECT_CS9_SELECT__##e)
+#define BFM_BCH_LAYOUTSELECT_CS9_SELECT_V(v)    BM_BCH_LAYOUTSELECT_CS9_SELECT
+#define BP_BCH_LAYOUTSELECT_CS8_SELECT          16
+#define BM_BCH_LAYOUTSELECT_CS8_SELECT          0x30000
+#define BF_BCH_LAYOUTSELECT_CS8_SELECT(v)       (((v) & 0x3) << 16)
+#define BFM_BCH_LAYOUTSELECT_CS8_SELECT(v)      BM_BCH_LAYOUTSELECT_CS8_SELECT
+#define BF_BCH_LAYOUTSELECT_CS8_SELECT_V(e)     BF_BCH_LAYOUTSELECT_CS8_SELECT(BV_BCH_LAYOUTSELECT_CS8_SELECT__##e)
+#define BFM_BCH_LAYOUTSELECT_CS8_SELECT_V(v)    BM_BCH_LAYOUTSELECT_CS8_SELECT
+#define BP_BCH_LAYOUTSELECT_CS7_SELECT          14
+#define BM_BCH_LAYOUTSELECT_CS7_SELECT          0xc000
+#define BF_BCH_LAYOUTSELECT_CS7_SELECT(v)       (((v) & 0x3) << 14)
+#define BFM_BCH_LAYOUTSELECT_CS7_SELECT(v)      BM_BCH_LAYOUTSELECT_CS7_SELECT
+#define BF_BCH_LAYOUTSELECT_CS7_SELECT_V(e)     BF_BCH_LAYOUTSELECT_CS7_SELECT(BV_BCH_LAYOUTSELECT_CS7_SELECT__##e)
+#define BFM_BCH_LAYOUTSELECT_CS7_SELECT_V(v)    BM_BCH_LAYOUTSELECT_CS7_SELECT
+#define BP_BCH_LAYOUTSELECT_CS6_SELECT          12
+#define BM_BCH_LAYOUTSELECT_CS6_SELECT          0x3000
+#define BF_BCH_LAYOUTSELECT_CS6_SELECT(v)       (((v) & 0x3) << 12)
+#define BFM_BCH_LAYOUTSELECT_CS6_SELECT(v)      BM_BCH_LAYOUTSELECT_CS6_SELECT
+#define BF_BCH_LAYOUTSELECT_CS6_SELECT_V(e)     BF_BCH_LAYOUTSELECT_CS6_SELECT(BV_BCH_LAYOUTSELECT_CS6_SELECT__##e)
+#define BFM_BCH_LAYOUTSELECT_CS6_SELECT_V(v)    BM_BCH_LAYOUTSELECT_CS6_SELECT
+#define BP_BCH_LAYOUTSELECT_CS5_SELECT          10
+#define BM_BCH_LAYOUTSELECT_CS5_SELECT          0xc00
+#define BF_BCH_LAYOUTSELECT_CS5_SELECT(v)       (((v) & 0x3) << 10)
+#define BFM_BCH_LAYOUTSELECT_CS5_SELECT(v)      BM_BCH_LAYOUTSELECT_CS5_SELECT
+#define BF_BCH_LAYOUTSELECT_CS5_SELECT_V(e)     BF_BCH_LAYOUTSELECT_CS5_SELECT(BV_BCH_LAYOUTSELECT_CS5_SELECT__##e)
+#define BFM_BCH_LAYOUTSELECT_CS5_SELECT_V(v)    BM_BCH_LAYOUTSELECT_CS5_SELECT
+#define BP_BCH_LAYOUTSELECT_CS4_SELECT          8
+#define BM_BCH_LAYOUTSELECT_CS4_SELECT          0x300
+#define BF_BCH_LAYOUTSELECT_CS4_SELECT(v)       (((v) & 0x3) << 8)
+#define BFM_BCH_LAYOUTSELECT_CS4_SELECT(v)      BM_BCH_LAYOUTSELECT_CS4_SELECT
+#define BF_BCH_LAYOUTSELECT_CS4_SELECT_V(e)     BF_BCH_LAYOUTSELECT_CS4_SELECT(BV_BCH_LAYOUTSELECT_CS4_SELECT__##e)
+#define BFM_BCH_LAYOUTSELECT_CS4_SELECT_V(v)    BM_BCH_LAYOUTSELECT_CS4_SELECT
+#define BP_BCH_LAYOUTSELECT_CS3_SELECT          6
+#define BM_BCH_LAYOUTSELECT_CS3_SELECT          0xc0
+#define BF_BCH_LAYOUTSELECT_CS3_SELECT(v)       (((v) & 0x3) << 6)
+#define BFM_BCH_LAYOUTSELECT_CS3_SELECT(v)      BM_BCH_LAYOUTSELECT_CS3_SELECT
+#define BF_BCH_LAYOUTSELECT_CS3_SELECT_V(e)     BF_BCH_LAYOUTSELECT_CS3_SELECT(BV_BCH_LAYOUTSELECT_CS3_SELECT__##e)
+#define BFM_BCH_LAYOUTSELECT_CS3_SELECT_V(v)    BM_BCH_LAYOUTSELECT_CS3_SELECT
+#define BP_BCH_LAYOUTSELECT_CS2_SELECT          4
+#define BM_BCH_LAYOUTSELECT_CS2_SELECT          0x30
+#define BF_BCH_LAYOUTSELECT_CS2_SELECT(v)       (((v) & 0x3) << 4)
+#define BFM_BCH_LAYOUTSELECT_CS2_SELECT(v)      BM_BCH_LAYOUTSELECT_CS2_SELECT
+#define BF_BCH_LAYOUTSELECT_CS2_SELECT_V(e)     BF_BCH_LAYOUTSELECT_CS2_SELECT(BV_BCH_LAYOUTSELECT_CS2_SELECT__##e)
+#define BFM_BCH_LAYOUTSELECT_CS2_SELECT_V(v)    BM_BCH_LAYOUTSELECT_CS2_SELECT
+#define BP_BCH_LAYOUTSELECT_CS1_SELECT          2
+#define BM_BCH_LAYOUTSELECT_CS1_SELECT          0xc
+#define BF_BCH_LAYOUTSELECT_CS1_SELECT(v)       (((v) & 0x3) << 2)
+#define BFM_BCH_LAYOUTSELECT_CS1_SELECT(v)      BM_BCH_LAYOUTSELECT_CS1_SELECT
+#define BF_BCH_LAYOUTSELECT_CS1_SELECT_V(e)     BF_BCH_LAYOUTSELECT_CS1_SELECT(BV_BCH_LAYOUTSELECT_CS1_SELECT__##e)
+#define BFM_BCH_LAYOUTSELECT_CS1_SELECT_V(v)    BM_BCH_LAYOUTSELECT_CS1_SELECT
+#define BP_BCH_LAYOUTSELECT_CS0_SELECT          0
+#define BM_BCH_LAYOUTSELECT_CS0_SELECT          0x3
+#define BF_BCH_LAYOUTSELECT_CS0_SELECT(v)       (((v) & 0x3) << 0)
+#define BFM_BCH_LAYOUTSELECT_CS0_SELECT(v)      BM_BCH_LAYOUTSELECT_CS0_SELECT
+#define BF_BCH_LAYOUTSELECT_CS0_SELECT_V(e)     BF_BCH_LAYOUTSELECT_CS0_SELECT(BV_BCH_LAYOUTSELECT_CS0_SELECT__##e)
+#define BFM_BCH_LAYOUTSELECT_CS0_SELECT_V(v)    BM_BCH_LAYOUTSELECT_CS0_SELECT
+
+#define HW_BCH_FLASH0LAYOUT0                    HW(BCH_FLASH0LAYOUT0)
+#define HWA_BCH_FLASH0LAYOUT0                   (0x8000a000 + 0x80)
+#define HWT_BCH_FLASH0LAYOUT0                   HWIO_32_RW
+#define HWN_BCH_FLASH0LAYOUT0                   BCH_FLASH0LAYOUT0
+#define HWI_BCH_FLASH0LAYOUT0                   
+#define BP_BCH_FLASH0LAYOUT0_NBLOCKS            24
+#define BM_BCH_FLASH0LAYOUT0_NBLOCKS            0xff000000
+#define BF_BCH_FLASH0LAYOUT0_NBLOCKS(v)         (((v) & 0xff) << 24)
+#define BFM_BCH_FLASH0LAYOUT0_NBLOCKS(v)        BM_BCH_FLASH0LAYOUT0_NBLOCKS
+#define BF_BCH_FLASH0LAYOUT0_NBLOCKS_V(e)       BF_BCH_FLASH0LAYOUT0_NBLOCKS(BV_BCH_FLASH0LAYOUT0_NBLOCKS__##e)
+#define BFM_BCH_FLASH0LAYOUT0_NBLOCKS_V(v)      BM_BCH_FLASH0LAYOUT0_NBLOCKS
+#define BP_BCH_FLASH0LAYOUT0_META_SIZE          16
+#define BM_BCH_FLASH0LAYOUT0_META_SIZE          0xff0000
+#define BF_BCH_FLASH0LAYOUT0_META_SIZE(v)       (((v) & 0xff) << 16)
+#define BFM_BCH_FLASH0LAYOUT0_META_SIZE(v)      BM_BCH_FLASH0LAYOUT0_META_SIZE
+#define BF_BCH_FLASH0LAYOUT0_META_SIZE_V(e)     BF_BCH_FLASH0LAYOUT0_META_SIZE(BV_BCH_FLASH0LAYOUT0_META_SIZE__##e)
+#define BFM_BCH_FLASH0LAYOUT0_META_SIZE_V(v)    BM_BCH_FLASH0LAYOUT0_META_SIZE
+#define BP_BCH_FLASH0LAYOUT0_ECC0               12
+#define BM_BCH_FLASH0LAYOUT0_ECC0               0xf000
+#define BV_BCH_FLASH0LAYOUT0_ECC0__NONE         0x0
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC2         0x1
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC4         0x2
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC6         0x3
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC8         0x4
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC10        0x5
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC12        0x6
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC14        0x7
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC16        0x8
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC18        0x9
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC20        0xa
+#define BF_BCH_FLASH0LAYOUT0_ECC0(v)            (((v) & 0xf) << 12)
+#define BFM_BCH_FLASH0LAYOUT0_ECC0(v)           BM_BCH_FLASH0LAYOUT0_ECC0
+#define BF_BCH_FLASH0LAYOUT0_ECC0_V(e)          BF_BCH_FLASH0LAYOUT0_ECC0(BV_BCH_FLASH0LAYOUT0_ECC0__##e)
+#define BFM_BCH_FLASH0LAYOUT0_ECC0_V(v)         BM_BCH_FLASH0LAYOUT0_ECC0
+#define BP_BCH_FLASH0LAYOUT0_DATA0_SIZE         0
+#define BM_BCH_FLASH0LAYOUT0_DATA0_SIZE         0xfff
+#define BF_BCH_FLASH0LAYOUT0_DATA0_SIZE(v)      (((v) & 0xfff) << 0)
+#define BFM_BCH_FLASH0LAYOUT0_DATA0_SIZE(v)     BM_BCH_FLASH0LAYOUT0_DATA0_SIZE
+#define BF_BCH_FLASH0LAYOUT0_DATA0_SIZE_V(e)    BF_BCH_FLASH0LAYOUT0_DATA0_SIZE(BV_BCH_FLASH0LAYOUT0_DATA0_SIZE__##e)
+#define BFM_BCH_FLASH0LAYOUT0_DATA0_SIZE_V(v)   BM_BCH_FLASH0LAYOUT0_DATA0_SIZE
+
+#define HW_BCH_FLASH0LAYOUT1                    HW(BCH_FLASH0LAYOUT1)
+#define HWA_BCH_FLASH0LAYOUT1                   (0x8000a000 + 0x90)
+#define HWT_BCH_FLASH0LAYOUT1                   HWIO_32_RW
+#define HWN_BCH_FLASH0LAYOUT1                   BCH_FLASH0LAYOUT1
+#define HWI_BCH_FLASH0LAYOUT1                   
+#define BP_BCH_FLASH0LAYOUT1_PAGE_SIZE          16
+#define BM_BCH_FLASH0LAYOUT1_PAGE_SIZE          0xffff0000
+#define BF_BCH_FLASH0LAYOUT1_PAGE_SIZE(v)       (((v) & 0xffff) << 16)
+#define BFM_BCH_FLASH0LAYOUT1_PAGE_SIZE(v)      BM_BCH_FLASH0LAYOUT1_PAGE_SIZE
+#define BF_BCH_FLASH0LAYOUT1_PAGE_SIZE_V(e)     BF_BCH_FLASH0LAYOUT1_PAGE_SIZE(BV_BCH_FLASH0LAYOUT1_PAGE_SIZE__##e)
+#define BFM_BCH_FLASH0LAYOUT1_PAGE_SIZE_V(v)    BM_BCH_FLASH0LAYOUT1_PAGE_SIZE
+#define BP_BCH_FLASH0LAYOUT1_ECCN               12
+#define BM_BCH_FLASH0LAYOUT1_ECCN               0xf000
+#define BV_BCH_FLASH0LAYOUT1_ECCN__NONE         0x0
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC2         0x1
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC4         0x2
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC6         0x3
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC8         0x4
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC10        0x5
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC12        0x6
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC14        0x7
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC16        0x8
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC18        0x9
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC20        0xa
+#define BF_BCH_FLASH0LAYOUT1_ECCN(v)            (((v) & 0xf) << 12)
+#define BFM_BCH_FLASH0LAYOUT1_ECCN(v)           BM_BCH_FLASH0LAYOUT1_ECCN
+#define BF_BCH_FLASH0LAYOUT1_ECCN_V(e)          BF_BCH_FLASH0LAYOUT1_ECCN(BV_BCH_FLASH0LAYOUT1_ECCN__##e)
+#define BFM_BCH_FLASH0LAYOUT1_ECCN_V(v)         BM_BCH_FLASH0LAYOUT1_ECCN
+#define BP_BCH_FLASH0LAYOUT1_DATAN_SIZE         0
+#define BM_BCH_FLASH0LAYOUT1_DATAN_SIZE         0xfff
+#define BF_BCH_FLASH0LAYOUT1_DATAN_SIZE(v)      (((v) & 0xfff) << 0)
+#define BFM_BCH_FLASH0LAYOUT1_DATAN_SIZE(v)     BM_BCH_FLASH0LAYOUT1_DATAN_SIZE
+#define BF_BCH_FLASH0LAYOUT1_DATAN_SIZE_V(e)    BF_BCH_FLASH0LAYOUT1_DATAN_SIZE(BV_BCH_FLASH0LAYOUT1_DATAN_SIZE__##e)
+#define BFM_BCH_FLASH0LAYOUT1_DATAN_SIZE_V(v)   BM_BCH_FLASH0LAYOUT1_DATAN_SIZE
+
+#define HW_BCH_FLASH1LAYOUT0                    HW(BCH_FLASH1LAYOUT0)
+#define HWA_BCH_FLASH1LAYOUT0                   (0x8000a000 + 0xa0)
+#define HWT_BCH_FLASH1LAYOUT0                   HWIO_32_RW
+#define HWN_BCH_FLASH1LAYOUT0                   BCH_FLASH1LAYOUT0
+#define HWI_BCH_FLASH1LAYOUT0                   
+#define BP_BCH_FLASH1LAYOUT0_NBLOCKS            24
+#define BM_BCH_FLASH1LAYOUT0_NBLOCKS            0xff000000
+#define BF_BCH_FLASH1LAYOUT0_NBLOCKS(v)         (((v) & 0xff) << 24)
+#define BFM_BCH_FLASH1LAYOUT0_NBLOCKS(v)        BM_BCH_FLASH1LAYOUT0_NBLOCKS
+#define BF_BCH_FLASH1LAYOUT0_NBLOCKS_V(e)       BF_BCH_FLASH1LAYOUT0_NBLOCKS(BV_BCH_FLASH1LAYOUT0_NBLOCKS__##e)
+#define BFM_BCH_FLASH1LAYOUT0_NBLOCKS_V(v)      BM_BCH_FLASH1LAYOUT0_NBLOCKS
+#define BP_BCH_FLASH1LAYOUT0_META_SIZE          16
+#define BM_BCH_FLASH1LAYOUT0_META_SIZE          0xff0000
+#define BF_BCH_FLASH1LAYOUT0_META_SIZE(v)       (((v) & 0xff) << 16)
+#define BFM_BCH_FLASH1LAYOUT0_META_SIZE(v)      BM_BCH_FLASH1LAYOUT0_META_SIZE
+#define BF_BCH_FLASH1LAYOUT0_META_SIZE_V(e)     BF_BCH_FLASH1LAYOUT0_META_SIZE(BV_BCH_FLASH1LAYOUT0_META_SIZE__##e)
+#define BFM_BCH_FLASH1LAYOUT0_META_SIZE_V(v)    BM_BCH_FLASH1LAYOUT0_META_SIZE
+#define BP_BCH_FLASH1LAYOUT0_ECC0               12
+#define BM_BCH_FLASH1LAYOUT0_ECC0               0xf000
+#define BV_BCH_FLASH1LAYOUT0_ECC0__NONE         0x0
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC2         0x1
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC4         0x2
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC6         0x3
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC8         0x4
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC10        0x5
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC12        0x6
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC14        0x7
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC16        0x8
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC18        0x9
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC20        0xa
+#define BF_BCH_FLASH1LAYOUT0_ECC0(v)            (((v) & 0xf) << 12)
+#define BFM_BCH_FLASH1LAYOUT0_ECC0(v)           BM_BCH_FLASH1LAYOUT0_ECC0
+#define BF_BCH_FLASH1LAYOUT0_ECC0_V(e)          BF_BCH_FLASH1LAYOUT0_ECC0(BV_BCH_FLASH1LAYOUT0_ECC0__##e)
+#define BFM_BCH_FLASH1LAYOUT0_ECC0_V(v)         BM_BCH_FLASH1LAYOUT0_ECC0
+#define BP_BCH_FLASH1LAYOUT0_DATA0_SIZE         0
+#define BM_BCH_FLASH1LAYOUT0_DATA0_SIZE         0xfff
+#define BF_BCH_FLASH1LAYOUT0_DATA0_SIZE(v)      (((v) & 0xfff) << 0)
+#define BFM_BCH_FLASH1LAYOUT0_DATA0_SIZE(v)     BM_BCH_FLASH1LAYOUT0_DATA0_SIZE
+#define BF_BCH_FLASH1LAYOUT0_DATA0_SIZE_V(e)    BF_BCH_FLASH1LAYOUT0_DATA0_SIZE(BV_BCH_FLASH1LAYOUT0_DATA0_SIZE__##e)
+#define BFM_BCH_FLASH1LAYOUT0_DATA0_SIZE_V(v)   BM_BCH_FLASH1LAYOUT0_DATA0_SIZE
+
+#define HW_BCH_FLASH1LAYOUT1                    HW(BCH_FLASH1LAYOUT1)
+#define HWA_BCH_FLASH1LAYOUT1                   (0x8000a000 + 0xb0)
+#define HWT_BCH_FLASH1LAYOUT1                   HWIO_32_RW
+#define HWN_BCH_FLASH1LAYOUT1                   BCH_FLASH1LAYOUT1
+#define HWI_BCH_FLASH1LAYOUT1                   
+#define BP_BCH_FLASH1LAYOUT1_PAGE_SIZE          16
+#define BM_BCH_FLASH1LAYOUT1_PAGE_SIZE          0xffff0000
+#define BF_BCH_FLASH1LAYOUT1_PAGE_SIZE(v)       (((v) & 0xffff) << 16)
+#define BFM_BCH_FLASH1LAYOUT1_PAGE_SIZE(v)      BM_BCH_FLASH1LAYOUT1_PAGE_SIZE
+#define BF_BCH_FLASH1LAYOUT1_PAGE_SIZE_V(e)     BF_BCH_FLASH1LAYOUT1_PAGE_SIZE(BV_BCH_FLASH1LAYOUT1_PAGE_SIZE__##e)
+#define BFM_BCH_FLASH1LAYOUT1_PAGE_SIZE_V(v)    BM_BCH_FLASH1LAYOUT1_PAGE_SIZE
+#define BP_BCH_FLASH1LAYOUT1_ECCN               12
+#define BM_BCH_FLASH1LAYOUT1_ECCN               0xf000
+#define BV_BCH_FLASH1LAYOUT1_ECCN__NONE         0x0
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC2         0x1
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC4         0x2
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC6         0x3
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC8         0x4
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC10        0x5
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC12        0x6
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC14        0x7
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC16        0x8
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC18        0x9
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC20        0xa
+#define BF_BCH_FLASH1LAYOUT1_ECCN(v)            (((v) & 0xf) << 12)
+#define BFM_BCH_FLASH1LAYOUT1_ECCN(v)           BM_BCH_FLASH1LAYOUT1_ECCN
+#define BF_BCH_FLASH1LAYOUT1_ECCN_V(e)          BF_BCH_FLASH1LAYOUT1_ECCN(BV_BCH_FLASH1LAYOUT1_ECCN__##e)
+#define BFM_BCH_FLASH1LAYOUT1_ECCN_V(v)         BM_BCH_FLASH1LAYOUT1_ECCN
+#define BP_BCH_FLASH1LAYOUT1_DATAN_SIZE         0
+#define BM_BCH_FLASH1LAYOUT1_DATAN_SIZE         0xfff
+#define BF_BCH_FLASH1LAYOUT1_DATAN_SIZE(v)      (((v) & 0xfff) << 0)
+#define BFM_BCH_FLASH1LAYOUT1_DATAN_SIZE(v)     BM_BCH_FLASH1LAYOUT1_DATAN_SIZE
+#define BF_BCH_FLASH1LAYOUT1_DATAN_SIZE_V(e)    BF_BCH_FLASH1LAYOUT1_DATAN_SIZE(BV_BCH_FLASH1LAYOUT1_DATAN_SIZE__##e)
+#define BFM_BCH_FLASH1LAYOUT1_DATAN_SIZE_V(v)   BM_BCH_FLASH1LAYOUT1_DATAN_SIZE
+
+#define HW_BCH_FLASH2LAYOUT0                    HW(BCH_FLASH2LAYOUT0)
+#define HWA_BCH_FLASH2LAYOUT0                   (0x8000a000 + 0xc0)
+#define HWT_BCH_FLASH2LAYOUT0                   HWIO_32_RW
+#define HWN_BCH_FLASH2LAYOUT0                   BCH_FLASH2LAYOUT0
+#define HWI_BCH_FLASH2LAYOUT0                   
+#define BP_BCH_FLASH2LAYOUT0_NBLOCKS            24
+#define BM_BCH_FLASH2LAYOUT0_NBLOCKS            0xff000000
+#define BF_BCH_FLASH2LAYOUT0_NBLOCKS(v)         (((v) & 0xff) << 24)
+#define BFM_BCH_FLASH2LAYOUT0_NBLOCKS(v)        BM_BCH_FLASH2LAYOUT0_NBLOCKS
+#define BF_BCH_FLASH2LAYOUT0_NBLOCKS_V(e)       BF_BCH_FLASH2LAYOUT0_NBLOCKS(BV_BCH_FLASH2LAYOUT0_NBLOCKS__##e)
+#define BFM_BCH_FLASH2LAYOUT0_NBLOCKS_V(v)      BM_BCH_FLASH2LAYOUT0_NBLOCKS
+#define BP_BCH_FLASH2LAYOUT0_META_SIZE          16
+#define BM_BCH_FLASH2LAYOUT0_META_SIZE          0xff0000
+#define BF_BCH_FLASH2LAYOUT0_META_SIZE(v)       (((v) & 0xff) << 16)
+#define BFM_BCH_FLASH2LAYOUT0_META_SIZE(v)      BM_BCH_FLASH2LAYOUT0_META_SIZE
+#define BF_BCH_FLASH2LAYOUT0_META_SIZE_V(e)     BF_BCH_FLASH2LAYOUT0_META_SIZE(BV_BCH_FLASH2LAYOUT0_META_SIZE__##e)
+#define BFM_BCH_FLASH2LAYOUT0_META_SIZE_V(v)    BM_BCH_FLASH2LAYOUT0_META_SIZE
+#define BP_BCH_FLASH2LAYOUT0_ECC0               12
+#define BM_BCH_FLASH2LAYOUT0_ECC0               0xf000
+#define BV_BCH_FLASH2LAYOUT0_ECC0__NONE         0x0
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC2         0x1
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC4         0x2
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC6         0x3
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC8         0x4
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC10        0x5
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC12        0x6
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC14        0x7
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC16        0x8
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC18        0x9
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC20        0xa
+#define BF_BCH_FLASH2LAYOUT0_ECC0(v)            (((v) & 0xf) << 12)
+#define BFM_BCH_FLASH2LAYOUT0_ECC0(v)           BM_BCH_FLASH2LAYOUT0_ECC0
+#define BF_BCH_FLASH2LAYOUT0_ECC0_V(e)          BF_BCH_FLASH2LAYOUT0_ECC0(BV_BCH_FLASH2LAYOUT0_ECC0__##e)
+#define BFM_BCH_FLASH2LAYOUT0_ECC0_V(v)         BM_BCH_FLASH2LAYOUT0_ECC0
+#define BP_BCH_FLASH2LAYOUT0_DATA0_SIZE         0
+#define BM_BCH_FLASH2LAYOUT0_DATA0_SIZE         0xfff
+#define BF_BCH_FLASH2LAYOUT0_DATA0_SIZE(v)      (((v) & 0xfff) << 0)
+#define BFM_BCH_FLASH2LAYOUT0_DATA0_SIZE(v)     BM_BCH_FLASH2LAYOUT0_DATA0_SIZE
+#define BF_BCH_FLASH2LAYOUT0_DATA0_SIZE_V(e)    BF_BCH_FLASH2LAYOUT0_DATA0_SIZE(BV_BCH_FLASH2LAYOUT0_DATA0_SIZE__##e)
+#define BFM_BCH_FLASH2LAYOUT0_DATA0_SIZE_V(v)   BM_BCH_FLASH2LAYOUT0_DATA0_SIZE
+
+#define HW_BCH_FLASH2LAYOUT1                    HW(BCH_FLASH2LAYOUT1)
+#define HWA_BCH_FLASH2LAYOUT1                   (0x8000a000 + 0xd0)
+#define HWT_BCH_FLASH2LAYOUT1                   HWIO_32_RW
+#define HWN_BCH_FLASH2LAYOUT1                   BCH_FLASH2LAYOUT1
+#define HWI_BCH_FLASH2LAYOUT1                   
+#define BP_BCH_FLASH2LAYOUT1_PAGE_SIZE          16
+#define BM_BCH_FLASH2LAYOUT1_PAGE_SIZE          0xffff0000
+#define BF_BCH_FLASH2LAYOUT1_PAGE_SIZE(v)       (((v) & 0xffff) << 16)
+#define BFM_BCH_FLASH2LAYOUT1_PAGE_SIZE(v)      BM_BCH_FLASH2LAYOUT1_PAGE_SIZE
+#define BF_BCH_FLASH2LAYOUT1_PAGE_SIZE_V(e)     BF_BCH_FLASH2LAYOUT1_PAGE_SIZE(BV_BCH_FLASH2LAYOUT1_PAGE_SIZE__##e)
+#define BFM_BCH_FLASH2LAYOUT1_PAGE_SIZE_V(v)    BM_BCH_FLASH2LAYOUT1_PAGE_SIZE
+#define BP_BCH_FLASH2LAYOUT1_ECCN               12
+#define BM_BCH_FLASH2LAYOUT1_ECCN               0xf000
+#define BV_BCH_FLASH2LAYOUT1_ECCN__NONE         0x0
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC2         0x1
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC4         0x2
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC6         0x3
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC8         0x4
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC10        0x5
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC12        0x6
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC14        0x7
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC16        0x8
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC18        0x9
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC20        0xa
+#define BF_BCH_FLASH2LAYOUT1_ECCN(v)            (((v) & 0xf) << 12)
+#define BFM_BCH_FLASH2LAYOUT1_ECCN(v)           BM_BCH_FLASH2LAYOUT1_ECCN
+#define BF_BCH_FLASH2LAYOUT1_ECCN_V(e)          BF_BCH_FLASH2LAYOUT1_ECCN(BV_BCH_FLASH2LAYOUT1_ECCN__##e)
+#define BFM_BCH_FLASH2LAYOUT1_ECCN_V(v)         BM_BCH_FLASH2LAYOUT1_ECCN
+#define BP_BCH_FLASH2LAYOUT1_DATAN_SIZE         0
+#define BM_BCH_FLASH2LAYOUT1_DATAN_SIZE         0xfff
+#define BF_BCH_FLASH2LAYOUT1_DATAN_SIZE(v)      (((v) & 0xfff) << 0)
+#define BFM_BCH_FLASH2LAYOUT1_DATAN_SIZE(v)     BM_BCH_FLASH2LAYOUT1_DATAN_SIZE
+#define BF_BCH_FLASH2LAYOUT1_DATAN_SIZE_V(e)    BF_BCH_FLASH2LAYOUT1_DATAN_SIZE(BV_BCH_FLASH2LAYOUT1_DATAN_SIZE__##e)
+#define BFM_BCH_FLASH2LAYOUT1_DATAN_SIZE_V(v)   BM_BCH_FLASH2LAYOUT1_DATAN_SIZE
+
+#define HW_BCH_FLASH3LAYOUT0                    HW(BCH_FLASH3LAYOUT0)
+#define HWA_BCH_FLASH3LAYOUT0                   (0x8000a000 + 0xe0)
+#define HWT_BCH_FLASH3LAYOUT0                   HWIO_32_RW
+#define HWN_BCH_FLASH3LAYOUT0                   BCH_FLASH3LAYOUT0
+#define HWI_BCH_FLASH3LAYOUT0                   
+#define BP_BCH_FLASH3LAYOUT0_NBLOCKS            24
+#define BM_BCH_FLASH3LAYOUT0_NBLOCKS            0xff000000
+#define BF_BCH_FLASH3LAYOUT0_NBLOCKS(v)         (((v) & 0xff) << 24)
+#define BFM_BCH_FLASH3LAYOUT0_NBLOCKS(v)        BM_BCH_FLASH3LAYOUT0_NBLOCKS
+#define BF_BCH_FLASH3LAYOUT0_NBLOCKS_V(e)       BF_BCH_FLASH3LAYOUT0_NBLOCKS(BV_BCH_FLASH3LAYOUT0_NBLOCKS__##e)
+#define BFM_BCH_FLASH3LAYOUT0_NBLOCKS_V(v)      BM_BCH_FLASH3LAYOUT0_NBLOCKS
+#define BP_BCH_FLASH3LAYOUT0_META_SIZE          16
+#define BM_BCH_FLASH3LAYOUT0_META_SIZE          0xff0000
+#define BF_BCH_FLASH3LAYOUT0_META_SIZE(v)       (((v) & 0xff) << 16)
+#define BFM_BCH_FLASH3LAYOUT0_META_SIZE(v)      BM_BCH_FLASH3LAYOUT0_META_SIZE
+#define BF_BCH_FLASH3LAYOUT0_META_SIZE_V(e)     BF_BCH_FLASH3LAYOUT0_META_SIZE(BV_BCH_FLASH3LAYOUT0_META_SIZE__##e)
+#define BFM_BCH_FLASH3LAYOUT0_META_SIZE_V(v)    BM_BCH_FLASH3LAYOUT0_META_SIZE
+#define BP_BCH_FLASH3LAYOUT0_ECC0               12
+#define BM_BCH_FLASH3LAYOUT0_ECC0               0xf000
+#define BV_BCH_FLASH3LAYOUT0_ECC0__NONE         0x0
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC2         0x1
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC4         0x2
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC6         0x3
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC8         0x4
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC10        0x5
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC12        0x6
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC14        0x7
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC16        0x8
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC18        0x9
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC20        0xa
+#define BF_BCH_FLASH3LAYOUT0_ECC0(v)            (((v) & 0xf) << 12)
+#define BFM_BCH_FLASH3LAYOUT0_ECC0(v)           BM_BCH_FLASH3LAYOUT0_ECC0
+#define BF_BCH_FLASH3LAYOUT0_ECC0_V(e)          BF_BCH_FLASH3LAYOUT0_ECC0(BV_BCH_FLASH3LAYOUT0_ECC0__##e)
+#define BFM_BCH_FLASH3LAYOUT0_ECC0_V(v)         BM_BCH_FLASH3LAYOUT0_ECC0
+#define BP_BCH_FLASH3LAYOUT0_DATA0_SIZE         0
+#define BM_BCH_FLASH3LAYOUT0_DATA0_SIZE         0xfff
+#define BF_BCH_FLASH3LAYOUT0_DATA0_SIZE(v)      (((v) & 0xfff) << 0)
+#define BFM_BCH_FLASH3LAYOUT0_DATA0_SIZE(v)     BM_BCH_FLASH3LAYOUT0_DATA0_SIZE
+#define BF_BCH_FLASH3LAYOUT0_DATA0_SIZE_V(e)    BF_BCH_FLASH3LAYOUT0_DATA0_SIZE(BV_BCH_FLASH3LAYOUT0_DATA0_SIZE__##e)
+#define BFM_BCH_FLASH3LAYOUT0_DATA0_SIZE_V(v)   BM_BCH_FLASH3LAYOUT0_DATA0_SIZE
+
+#define HW_BCH_FLASH3LAYOUT1                    HW(BCH_FLASH3LAYOUT1)
+#define HWA_BCH_FLASH3LAYOUT1                   (0x8000a000 + 0xf0)
+#define HWT_BCH_FLASH3LAYOUT1                   HWIO_32_RW
+#define HWN_BCH_FLASH3LAYOUT1                   BCH_FLASH3LAYOUT1
+#define HWI_BCH_FLASH3LAYOUT1                   
+#define BP_BCH_FLASH3LAYOUT1_PAGE_SIZE          16
+#define BM_BCH_FLASH3LAYOUT1_PAGE_SIZE          0xffff0000
+#define BF_BCH_FLASH3LAYOUT1_PAGE_SIZE(v)       (((v) & 0xffff) << 16)
+#define BFM_BCH_FLASH3LAYOUT1_PAGE_SIZE(v)      BM_BCH_FLASH3LAYOUT1_PAGE_SIZE
+#define BF_BCH_FLASH3LAYOUT1_PAGE_SIZE_V(e)     BF_BCH_FLASH3LAYOUT1_PAGE_SIZE(BV_BCH_FLASH3LAYOUT1_PAGE_SIZE__##e)
+#define BFM_BCH_FLASH3LAYOUT1_PAGE_SIZE_V(v)    BM_BCH_FLASH3LAYOUT1_PAGE_SIZE
+#define BP_BCH_FLASH3LAYOUT1_ECCN               12
+#define BM_BCH_FLASH3LAYOUT1_ECCN               0xf000
+#define BV_BCH_FLASH3LAYOUT1_ECCN__NONE         0x0
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC2         0x1
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC4         0x2
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC6         0x3
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC8         0x4
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC10        0x5
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC12        0x6
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC14        0x7
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC16        0x8
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC18        0x9
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC20        0xa
+#define BF_BCH_FLASH3LAYOUT1_ECCN(v)            (((v) & 0xf) << 12)
+#define BFM_BCH_FLASH3LAYOUT1_ECCN(v)           BM_BCH_FLASH3LAYOUT1_ECCN
+#define BF_BCH_FLASH3LAYOUT1_ECCN_V(e)          BF_BCH_FLASH3LAYOUT1_ECCN(BV_BCH_FLASH3LAYOUT1_ECCN__##e)
+#define BFM_BCH_FLASH3LAYOUT1_ECCN_V(v)         BM_BCH_FLASH3LAYOUT1_ECCN
+#define BP_BCH_FLASH3LAYOUT1_DATAN_SIZE         0
+#define BM_BCH_FLASH3LAYOUT1_DATAN_SIZE         0xfff
+#define BF_BCH_FLASH3LAYOUT1_DATAN_SIZE(v)      (((v) & 0xfff) << 0)
+#define BFM_BCH_FLASH3LAYOUT1_DATAN_SIZE(v)     BM_BCH_FLASH3LAYOUT1_DATAN_SIZE
+#define BF_BCH_FLASH3LAYOUT1_DATAN_SIZE_V(e)    BF_BCH_FLASH3LAYOUT1_DATAN_SIZE(BV_BCH_FLASH3LAYOUT1_DATAN_SIZE__##e)
+#define BFM_BCH_FLASH3LAYOUT1_DATAN_SIZE_V(v)   BM_BCH_FLASH3LAYOUT1_DATAN_SIZE
+
+#define HW_BCH_DEBUG0                                       HW(BCH_DEBUG0)
+#define HWA_BCH_DEBUG0                                      (0x8000a000 + 0x100)
+#define HWT_BCH_DEBUG0                                      HWIO_32_RW
+#define HWN_BCH_DEBUG0                                      BCH_DEBUG0
+#define HWI_BCH_DEBUG0                                      
+#define HW_BCH_DEBUG0_SET                                   HW(BCH_DEBUG0_SET)
+#define HWA_BCH_DEBUG0_SET                                  (HWA_BCH_DEBUG0 + 0x4)
+#define HWT_BCH_DEBUG0_SET                                  HWIO_32_WO
+#define HWN_BCH_DEBUG0_SET                                  BCH_DEBUG0
+#define HWI_BCH_DEBUG0_SET                                  
+#define HW_BCH_DEBUG0_CLR                                   HW(BCH_DEBUG0_CLR)
+#define HWA_BCH_DEBUG0_CLR                                  (HWA_BCH_DEBUG0 + 0x8)
+#define HWT_BCH_DEBUG0_CLR                                  HWIO_32_WO
+#define HWN_BCH_DEBUG0_CLR                                  BCH_DEBUG0
+#define HWI_BCH_DEBUG0_CLR                                  
+#define HW_BCH_DEBUG0_TOG                                   HW(BCH_DEBUG0_TOG)
+#define HWA_BCH_DEBUG0_TOG                                  (HWA_BCH_DEBUG0 + 0xc)
+#define HWT_BCH_DEBUG0_TOG                                  HWIO_32_WO
+#define HWN_BCH_DEBUG0_TOG                                  BCH_DEBUG0
+#define HWI_BCH_DEBUG0_TOG                                  
+#define BP_BCH_DEBUG0_RSVD1                                 27
+#define BM_BCH_DEBUG0_RSVD1                                 0xf8000000
+#define BF_BCH_DEBUG0_RSVD1(v)                              (((v) & 0x1f) << 27)
+#define BFM_BCH_DEBUG0_RSVD1(v)                             BM_BCH_DEBUG0_RSVD1
+#define BF_BCH_DEBUG0_RSVD1_V(e)                            BF_BCH_DEBUG0_RSVD1(BV_BCH_DEBUG0_RSVD1__##e)
+#define BFM_BCH_DEBUG0_RSVD1_V(v)                           BM_BCH_DEBUG0_RSVD1
+#define BP_BCH_DEBUG0_ROM_BIST_ENABLE                       26
+#define BM_BCH_DEBUG0_ROM_BIST_ENABLE                       0x4000000
+#define BF_BCH_DEBUG0_ROM_BIST_ENABLE(v)                    (((v) & 0x1) << 26)
+#define BFM_BCH_DEBUG0_ROM_BIST_ENABLE(v)                   BM_BCH_DEBUG0_ROM_BIST_ENABLE
+#define BF_BCH_DEBUG0_ROM_BIST_ENABLE_V(e)                  BF_BCH_DEBUG0_ROM_BIST_ENABLE(BV_BCH_DEBUG0_ROM_BIST_ENABLE__##e)
+#define BFM_BCH_DEBUG0_ROM_BIST_ENABLE_V(v)                 BM_BCH_DEBUG0_ROM_BIST_ENABLE
+#define BP_BCH_DEBUG0_ROM_BIST_COMPLETE                     25
+#define BM_BCH_DEBUG0_ROM_BIST_COMPLETE                     0x2000000
+#define BF_BCH_DEBUG0_ROM_BIST_COMPLETE(v)                  (((v) & 0x1) << 25)
+#define BFM_BCH_DEBUG0_ROM_BIST_COMPLETE(v)                 BM_BCH_DEBUG0_ROM_BIST_COMPLETE
+#define BF_BCH_DEBUG0_ROM_BIST_COMPLETE_V(e)                BF_BCH_DEBUG0_ROM_BIST_COMPLETE(BV_BCH_DEBUG0_ROM_BIST_COMPLETE__##e)
+#define BFM_BCH_DEBUG0_ROM_BIST_COMPLETE_V(v)               BM_BCH_DEBUG0_ROM_BIST_COMPLETE
+#define BP_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL             16
+#define BM_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL             0x1ff0000
+#define BV_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__NORMAL     0x0
+#define BV_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__TEST_MODE  0x1
+#define BF_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL(v)          (((v) & 0x1ff) << 16)
+#define BFM_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL(v)         BM_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL
+#define BF_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_V(e)        BF_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL(BV_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__##e)
+#define BFM_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_V(v)       BM_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL
+#define BP_BCH_DEBUG0_KES_DEBUG_SHIFT_SYND                  15
+#define BM_BCH_DEBUG0_KES_DEBUG_SHIFT_SYND                  0x8000
+#define BF_BCH_DEBUG0_KES_DEBUG_SHIFT_SYND(v)               (((v) & 0x1) << 15)
+#define BFM_BCH_DEBUG0_KES_DEBUG_SHIFT_SYND(v)              BM_BCH_DEBUG0_KES_DEBUG_SHIFT_SYND
+#define BF_BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_V(e)             BF_BCH_DEBUG0_KES_DEBUG_SHIFT_SYND(BV_BCH_DEBUG0_KES_DEBUG_SHIFT_SYND__##e)
+#define BFM_BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_V(v)            BM_BCH_DEBUG0_KES_DEBUG_SHIFT_SYND
+#define BP_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG                14
+#define BM_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG                0x4000
+#define BV_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__DATA          0x1
+#define BV_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__AUX           0x1
+#define BF_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG(v)             (((v) & 0x1) << 14)
+#define BFM_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG(v)            BM_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG
+#define BF_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_V(e)           BF_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG(BV_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__##e)
+#define BFM_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_V(v)          BM_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG
+#define BP_BCH_DEBUG0_KES_DEBUG_MODE4K                      13
+#define BM_BCH_DEBUG0_KES_DEBUG_MODE4K                      0x2000
+#define BV_BCH_DEBUG0_KES_DEBUG_MODE4K__4k                  0x1
+#define BV_BCH_DEBUG0_KES_DEBUG_MODE4K__2k                  0x1
+#define BF_BCH_DEBUG0_KES_DEBUG_MODE4K(v)                   (((v) & 0x1) << 13)
+#define BFM_BCH_DEBUG0_KES_DEBUG_MODE4K(v)                  BM_BCH_DEBUG0_KES_DEBUG_MODE4K
+#define BF_BCH_DEBUG0_KES_DEBUG_MODE4K_V(e)                 BF_BCH_DEBUG0_KES_DEBUG_MODE4K(BV_BCH_DEBUG0_KES_DEBUG_MODE4K__##e)
+#define BFM_BCH_DEBUG0_KES_DEBUG_MODE4K_V(v)                BM_BCH_DEBUG0_KES_DEBUG_MODE4K
+#define BP_BCH_DEBUG0_KES_DEBUG_KICK                        12
+#define BM_BCH_DEBUG0_KES_DEBUG_KICK                        0x1000
+#define BF_BCH_DEBUG0_KES_DEBUG_KICK(v)                     (((v) & 0x1) << 12)
+#define BFM_BCH_DEBUG0_KES_DEBUG_KICK(v)                    BM_BCH_DEBUG0_KES_DEBUG_KICK
+#define BF_BCH_DEBUG0_KES_DEBUG_KICK_V(e)                   BF_BCH_DEBUG0_KES_DEBUG_KICK(BV_BCH_DEBUG0_KES_DEBUG_KICK__##e)
+#define BFM_BCH_DEBUG0_KES_DEBUG_KICK_V(v)                  BM_BCH_DEBUG0_KES_DEBUG_KICK
+#define BP_BCH_DEBUG0_KES_STANDALONE                        11
+#define BM_BCH_DEBUG0_KES_STANDALONE                        0x800
+#define BV_BCH_DEBUG0_KES_STANDALONE__NORMAL                0x0
+#define BV_BCH_DEBUG0_KES_STANDALONE__TEST_MODE             0x1
+#define BF_BCH_DEBUG0_KES_STANDALONE(v)                     (((v) & 0x1) << 11)
+#define BFM_BCH_DEBUG0_KES_STANDALONE(v)                    BM_BCH_DEBUG0_KES_STANDALONE
+#define BF_BCH_DEBUG0_KES_STANDALONE_V(e)                   BF_BCH_DEBUG0_KES_STANDALONE(BV_BCH_DEBUG0_KES_STANDALONE__##e)
+#define BFM_BCH_DEBUG0_KES_STANDALONE_V(v)                  BM_BCH_DEBUG0_KES_STANDALONE
+#define BP_BCH_DEBUG0_KES_DEBUG_STEP                        10
+#define BM_BCH_DEBUG0_KES_DEBUG_STEP                        0x400
+#define BF_BCH_DEBUG0_KES_DEBUG_STEP(v)                     (((v) & 0x1) << 10)
+#define BFM_BCH_DEBUG0_KES_DEBUG_STEP(v)                    BM_BCH_DEBUG0_KES_DEBUG_STEP
+#define BF_BCH_DEBUG0_KES_DEBUG_STEP_V(e)                   BF_BCH_DEBUG0_KES_DEBUG_STEP(BV_BCH_DEBUG0_KES_DEBUG_STEP__##e)
+#define BFM_BCH_DEBUG0_KES_DEBUG_STEP_V(v)                  BM_BCH_DEBUG0_KES_DEBUG_STEP
+#define BP_BCH_DEBUG0_KES_DEBUG_STALL                       9
+#define BM_BCH_DEBUG0_KES_DEBUG_STALL                       0x200
+#define BV_BCH_DEBUG0_KES_DEBUG_STALL__NORMAL               0x0
+#define BV_BCH_DEBUG0_KES_DEBUG_STALL__WAIT                 0x1
+#define BF_BCH_DEBUG0_KES_DEBUG_STALL(v)                    (((v) & 0x1) << 9)
+#define BFM_BCH_DEBUG0_KES_DEBUG_STALL(v)                   BM_BCH_DEBUG0_KES_DEBUG_STALL
+#define BF_BCH_DEBUG0_KES_DEBUG_STALL_V(e)                  BF_BCH_DEBUG0_KES_DEBUG_STALL(BV_BCH_DEBUG0_KES_DEBUG_STALL__##e)
+#define BFM_BCH_DEBUG0_KES_DEBUG_STALL_V(v)                 BM_BCH_DEBUG0_KES_DEBUG_STALL
+#define BP_BCH_DEBUG0_BM_KES_TEST_BYPASS                    8
+#define BM_BCH_DEBUG0_BM_KES_TEST_BYPASS                    0x100
+#define BV_BCH_DEBUG0_BM_KES_TEST_BYPASS__NORMAL            0x0
+#define BV_BCH_DEBUG0_BM_KES_TEST_BYPASS__TEST_MODE         0x1
+#define BF_BCH_DEBUG0_BM_KES_TEST_BYPASS(v)                 (((v) & 0x1) << 8)
+#define BFM_BCH_DEBUG0_BM_KES_TEST_BYPASS(v)                BM_BCH_DEBUG0_BM_KES_TEST_BYPASS
+#define BF_BCH_DEBUG0_BM_KES_TEST_BYPASS_V(e)               BF_BCH_DEBUG0_BM_KES_TEST_BYPASS(BV_BCH_DEBUG0_BM_KES_TEST_BYPASS__##e)
+#define BFM_BCH_DEBUG0_BM_KES_TEST_BYPASS_V(v)              BM_BCH_DEBUG0_BM_KES_TEST_BYPASS
+#define BP_BCH_DEBUG0_RSVD0                                 6
+#define BM_BCH_DEBUG0_RSVD0                                 0xc0
+#define BF_BCH_DEBUG0_RSVD0(v)                              (((v) & 0x3) << 6)
+#define BFM_BCH_DEBUG0_RSVD0(v)                             BM_BCH_DEBUG0_RSVD0
+#define BF_BCH_DEBUG0_RSVD0_V(e)                            BF_BCH_DEBUG0_RSVD0(BV_BCH_DEBUG0_RSVD0__##e)
+#define BFM_BCH_DEBUG0_RSVD0_V(v)                           BM_BCH_DEBUG0_RSVD0
+#define BP_BCH_DEBUG0_DEBUG_REG_SELECT                      0
+#define BM_BCH_DEBUG0_DEBUG_REG_SELECT                      0x3f
+#define BF_BCH_DEBUG0_DEBUG_REG_SELECT(v)                   (((v) & 0x3f) << 0)
+#define BFM_BCH_DEBUG0_DEBUG_REG_SELECT(v)                  BM_BCH_DEBUG0_DEBUG_REG_SELECT
+#define BF_BCH_DEBUG0_DEBUG_REG_SELECT_V(e)                 BF_BCH_DEBUG0_DEBUG_REG_SELECT(BV_BCH_DEBUG0_DEBUG_REG_SELECT__##e)
+#define BFM_BCH_DEBUG0_DEBUG_REG_SELECT_V(v)                BM_BCH_DEBUG0_DEBUG_REG_SELECT
+
+#define HW_BCH_DBGKESREAD               HW(BCH_DBGKESREAD)
+#define HWA_BCH_DBGKESREAD              (0x8000a000 + 0x110)
+#define HWT_BCH_DBGKESREAD              HWIO_32_RW
+#define HWN_BCH_DBGKESREAD              BCH_DBGKESREAD
+#define HWI_BCH_DBGKESREAD              
+#define BP_BCH_DBGKESREAD_VALUES        0
+#define BM_BCH_DBGKESREAD_VALUES        0xffffffff
+#define BF_BCH_DBGKESREAD_VALUES(v)     (((v) & 0xffffffff) << 0)
+#define BFM_BCH_DBGKESREAD_VALUES(v)    BM_BCH_DBGKESREAD_VALUES
+#define BF_BCH_DBGKESREAD_VALUES_V(e)   BF_BCH_DBGKESREAD_VALUES(BV_BCH_DBGKESREAD_VALUES__##e)
+#define BFM_BCH_DBGKESREAD_VALUES_V(v)  BM_BCH_DBGKESREAD_VALUES
+
+#define HW_BCH_DBGCSFEREAD              HW(BCH_DBGCSFEREAD)
+#define HWA_BCH_DBGCSFEREAD             (0x8000a000 + 0x120)
+#define HWT_BCH_DBGCSFEREAD             HWIO_32_RW
+#define HWN_BCH_DBGCSFEREAD             BCH_DBGCSFEREAD
+#define HWI_BCH_DBGCSFEREAD             
+#define BP_BCH_DBGCSFEREAD_VALUES       0
+#define BM_BCH_DBGCSFEREAD_VALUES       0xffffffff
+#define BF_BCH_DBGCSFEREAD_VALUES(v)    (((v) & 0xffffffff) << 0)
+#define BFM_BCH_DBGCSFEREAD_VALUES(v)   BM_BCH_DBGCSFEREAD_VALUES
+#define BF_BCH_DBGCSFEREAD_VALUES_V(e)  BF_BCH_DBGCSFEREAD_VALUES(BV_BCH_DBGCSFEREAD_VALUES__##e)
+#define BFM_BCH_DBGCSFEREAD_VALUES_V(v) BM_BCH_DBGCSFEREAD_VALUES
+
+#define HW_BCH_DBGSYNDGENREAD               HW(BCH_DBGSYNDGENREAD)
+#define HWA_BCH_DBGSYNDGENREAD              (0x8000a000 + 0x130)
+#define HWT_BCH_DBGSYNDGENREAD              HWIO_32_RW
+#define HWN_BCH_DBGSYNDGENREAD              BCH_DBGSYNDGENREAD
+#define HWI_BCH_DBGSYNDGENREAD              
+#define BP_BCH_DBGSYNDGENREAD_VALUES        0
+#define BM_BCH_DBGSYNDGENREAD_VALUES        0xffffffff
+#define BF_BCH_DBGSYNDGENREAD_VALUES(v)     (((v) & 0xffffffff) << 0)
+#define BFM_BCH_DBGSYNDGENREAD_VALUES(v)    BM_BCH_DBGSYNDGENREAD_VALUES
+#define BF_BCH_DBGSYNDGENREAD_VALUES_V(e)   BF_BCH_DBGSYNDGENREAD_VALUES(BV_BCH_DBGSYNDGENREAD_VALUES__##e)
+#define BFM_BCH_DBGSYNDGENREAD_VALUES_V(v)  BM_BCH_DBGSYNDGENREAD_VALUES
+
+#define HW_BCH_DBGAHBMREAD              HW(BCH_DBGAHBMREAD)
+#define HWA_BCH_DBGAHBMREAD             (0x8000a000 + 0x140)
+#define HWT_BCH_DBGAHBMREAD             HWIO_32_RW
+#define HWN_BCH_DBGAHBMREAD             BCH_DBGAHBMREAD
+#define HWI_BCH_DBGAHBMREAD             
+#define BP_BCH_DBGAHBMREAD_VALUES       0
+#define BM_BCH_DBGAHBMREAD_VALUES       0xffffffff
+#define BF_BCH_DBGAHBMREAD_VALUES(v)    (((v) & 0xffffffff) << 0)
+#define BFM_BCH_DBGAHBMREAD_VALUES(v)   BM_BCH_DBGAHBMREAD_VALUES
+#define BF_BCH_DBGAHBMREAD_VALUES_V(e)  BF_BCH_DBGAHBMREAD_VALUES(BV_BCH_DBGAHBMREAD_VALUES__##e)
+#define BFM_BCH_DBGAHBMREAD_VALUES_V(v) BM_BCH_DBGAHBMREAD_VALUES
+
+#define HW_BCH_BLOCKNAME            HW(BCH_BLOCKNAME)
+#define HWA_BCH_BLOCKNAME           (0x8000a000 + 0x150)
+#define HWT_BCH_BLOCKNAME           HWIO_32_RW
+#define HWN_BCH_BLOCKNAME           BCH_BLOCKNAME
+#define HWI_BCH_BLOCKNAME           
+#define BP_BCH_BLOCKNAME_NAME       0
+#define BM_BCH_BLOCKNAME_NAME       0xffffffff
+#define BF_BCH_BLOCKNAME_NAME(v)    (((v) & 0xffffffff) << 0)
+#define BFM_BCH_BLOCKNAME_NAME(v)   BM_BCH_BLOCKNAME_NAME
+#define BF_BCH_BLOCKNAME_NAME_V(e)  BF_BCH_BLOCKNAME_NAME(BV_BCH_BLOCKNAME_NAME__##e)
+#define BFM_BCH_BLOCKNAME_NAME_V(v) BM_BCH_BLOCKNAME_NAME
+
+#define HW_BCH_VERSION              HW(BCH_VERSION)
+#define HWA_BCH_VERSION             (0x8000a000 + 0x160)
+#define HWT_BCH_VERSION             HWIO_32_RW
+#define HWN_BCH_VERSION             BCH_VERSION
+#define HWI_BCH_VERSION             
+#define BP_BCH_VERSION_MAJOR        24
+#define BM_BCH_VERSION_MAJOR        0xff000000
+#define BF_BCH_VERSION_MAJOR(v)     (((v) & 0xff) << 24)
+#define BFM_BCH_VERSION_MAJOR(v)    BM_BCH_VERSION_MAJOR
+#define BF_BCH_VERSION_MAJOR_V(e)   BF_BCH_VERSION_MAJOR(BV_BCH_VERSION_MAJOR__##e)
+#define BFM_BCH_VERSION_MAJOR_V(v)  BM_BCH_VERSION_MAJOR
+#define BP_BCH_VERSION_MINOR        16
+#define BM_BCH_VERSION_MINOR        0xff0000
+#define BF_BCH_VERSION_MINOR(v)     (((v) & 0xff) << 16)
+#define BFM_BCH_VERSION_MINOR(v)    BM_BCH_VERSION_MINOR
+#define BF_BCH_VERSION_MINOR_V(e)   BF_BCH_VERSION_MINOR(BV_BCH_VERSION_MINOR__##e)
+#define BFM_BCH_VERSION_MINOR_V(v)  BM_BCH_VERSION_MINOR
+#define BP_BCH_VERSION_STEP         0
+#define BM_BCH_VERSION_STEP         0xffff
+#define BF_BCH_VERSION_STEP(v)      (((v) & 0xffff) << 0)
+#define BFM_BCH_VERSION_STEP(v)     BM_BCH_VERSION_STEP
+#define BF_BCH_VERSION_STEP_V(e)    BF_BCH_VERSION_STEP(BV_BCH_VERSION_STEP__##e)
+#define BFM_BCH_VERSION_STEP_V(v)   BM_BCH_VERSION_STEP
+
+#endif /* __HEADERGEN_IMX233_BCH_H__*/
diff --git a/firmware/target/arm/imx233/regs/imx233/clkctrl.h b/firmware/target/arm/imx233/regs/imx233/clkctrl.h
new file mode 100644
index 0000000000..3aaefcbab5
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/imx233/clkctrl.h
@@ -0,0 +1,1146 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * imx233 version: 2.4.0
+ * imx233 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_IMX233_CLKCTRL_H__
+#define __HEADERGEN_IMX233_CLKCTRL_H__
+
+#define HW_CLKCTRL_PLLCTRL0                     HW(CLKCTRL_PLLCTRL0)
+#define HWA_CLKCTRL_PLLCTRL0                    (0x80040000 + 0x0)
+#define HWT_CLKCTRL_PLLCTRL0                    HWIO_32_RW
+#define HWN_CLKCTRL_PLLCTRL0                    CLKCTRL_PLLCTRL0
+#define HWI_CLKCTRL_PLLCTRL0                    
+#define HW_CLKCTRL_PLLCTRL0_SET                 HW(CLKCTRL_PLLCTRL0_SET)
+#define HWA_CLKCTRL_PLLCTRL0_SET                (HWA_CLKCTRL_PLLCTRL0 + 0x4)
+#define HWT_CLKCTRL_PLLCTRL0_SET                HWIO_32_WO
+#define HWN_CLKCTRL_PLLCTRL0_SET                CLKCTRL_PLLCTRL0
+#define HWI_CLKCTRL_PLLCTRL0_SET                
+#define HW_CLKCTRL_PLLCTRL0_CLR                 HW(CLKCTRL_PLLCTRL0_CLR)
+#define HWA_CLKCTRL_PLLCTRL0_CLR                (HWA_CLKCTRL_PLLCTRL0 + 0x8)
+#define HWT_CLKCTRL_PLLCTRL0_CLR                HWIO_32_WO
+#define HWN_CLKCTRL_PLLCTRL0_CLR                CLKCTRL_PLLCTRL0
+#define HWI_CLKCTRL_PLLCTRL0_CLR                
+#define HW_CLKCTRL_PLLCTRL0_TOG                 HW(CLKCTRL_PLLCTRL0_TOG)
+#define HWA_CLKCTRL_PLLCTRL0_TOG                (HWA_CLKCTRL_PLLCTRL0 + 0xc)
+#define HWT_CLKCTRL_PLLCTRL0_TOG                HWIO_32_WO
+#define HWN_CLKCTRL_PLLCTRL0_TOG                CLKCTRL_PLLCTRL0
+#define HWI_CLKCTRL_PLLCTRL0_TOG                
+#define BP_CLKCTRL_PLLCTRL0_RSRVD6              30
+#define BM_CLKCTRL_PLLCTRL0_RSRVD6              0xc0000000
+#define BF_CLKCTRL_PLLCTRL0_RSRVD6(v)           (((v) & 0x3) << 30)
+#define BFM_CLKCTRL_PLLCTRL0_RSRVD6(v)          BM_CLKCTRL_PLLCTRL0_RSRVD6
+#define BF_CLKCTRL_PLLCTRL0_RSRVD6_V(e)         BF_CLKCTRL_PLLCTRL0_RSRVD6(BV_CLKCTRL_PLLCTRL0_RSRVD6__##e)
+#define BFM_CLKCTRL_PLLCTRL0_RSRVD6_V(v)        BM_CLKCTRL_PLLCTRL0_RSRVD6
+#define BP_CLKCTRL_PLLCTRL0_LFR_SEL             28
+#define BM_CLKCTRL_PLLCTRL0_LFR_SEL             0x30000000
+#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__DEFAULT    0x0
+#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_2    0x1
+#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_05   0x2
+#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__UNDEFINED  0x3
+#define BF_CLKCTRL_PLLCTRL0_LFR_SEL(v)          (((v) & 0x3) << 28)
+#define BFM_CLKCTRL_PLLCTRL0_LFR_SEL(v)         BM_CLKCTRL_PLLCTRL0_LFR_SEL
+#define BF_CLKCTRL_PLLCTRL0_LFR_SEL_V(e)        BF_CLKCTRL_PLLCTRL0_LFR_SEL(BV_CLKCTRL_PLLCTRL0_LFR_SEL__##e)
+#define BFM_CLKCTRL_PLLCTRL0_LFR_SEL_V(v)       BM_CLKCTRL_PLLCTRL0_LFR_SEL
+#define BP_CLKCTRL_PLLCTRL0_RSRVD5              26
+#define BM_CLKCTRL_PLLCTRL0_RSRVD5              0xc000000
+#define BF_CLKCTRL_PLLCTRL0_RSRVD5(v)           (((v) & 0x3) << 26)
+#define BFM_CLKCTRL_PLLCTRL0_RSRVD5(v)          BM_CLKCTRL_PLLCTRL0_RSRVD5
+#define BF_CLKCTRL_PLLCTRL0_RSRVD5_V(e)         BF_CLKCTRL_PLLCTRL0_RSRVD5(BV_CLKCTRL_PLLCTRL0_RSRVD5__##e)
+#define BFM_CLKCTRL_PLLCTRL0_RSRVD5_V(v)        BM_CLKCTRL_PLLCTRL0_RSRVD5
+#define BP_CLKCTRL_PLLCTRL0_CP_SEL              24
+#define BM_CLKCTRL_PLLCTRL0_CP_SEL              0x3000000
+#define BV_CLKCTRL_PLLCTRL0_CP_SEL__DEFAULT     0x0
+#define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_2     0x1
+#define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_05    0x2
+#define BV_CLKCTRL_PLLCTRL0_CP_SEL__UNDEFINED   0x3
+#define BF_CLKCTRL_PLLCTRL0_CP_SEL(v)           (((v) & 0x3) << 24)
+#define BFM_CLKCTRL_PLLCTRL0_CP_SEL(v)          BM_CLKCTRL_PLLCTRL0_CP_SEL
+#define BF_CLKCTRL_PLLCTRL0_CP_SEL_V(e)         BF_CLKCTRL_PLLCTRL0_CP_SEL(BV_CLKCTRL_PLLCTRL0_CP_SEL__##e)
+#define BFM_CLKCTRL_PLLCTRL0_CP_SEL_V(v)        BM_CLKCTRL_PLLCTRL0_CP_SEL
+#define BP_CLKCTRL_PLLCTRL0_RSRVD4              22
+#define BM_CLKCTRL_PLLCTRL0_RSRVD4              0xc00000
+#define BF_CLKCTRL_PLLCTRL0_RSRVD4(v)           (((v) & 0x3) << 22)
+#define BFM_CLKCTRL_PLLCTRL0_RSRVD4(v)          BM_CLKCTRL_PLLCTRL0_RSRVD4
+#define BF_CLKCTRL_PLLCTRL0_RSRVD4_V(e)         BF_CLKCTRL_PLLCTRL0_RSRVD4(BV_CLKCTRL_PLLCTRL0_RSRVD4__##e)
+#define BFM_CLKCTRL_PLLCTRL0_RSRVD4_V(v)        BM_CLKCTRL_PLLCTRL0_RSRVD4
+#define BP_CLKCTRL_PLLCTRL0_DIV_SEL             20
+#define BM_CLKCTRL_PLLCTRL0_DIV_SEL             0x300000
+#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__DEFAULT    0x0
+#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWER      0x1
+#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWEST     0x2
+#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__UNDEFINED  0x3
+#define BF_CLKCTRL_PLLCTRL0_DIV_SEL(v)          (((v) & 0x3) << 20)
+#define BFM_CLKCTRL_PLLCTRL0_DIV_SEL(v)         BM_CLKCTRL_PLLCTRL0_DIV_SEL
+#define BF_CLKCTRL_PLLCTRL0_DIV_SEL_V(e)        BF_CLKCTRL_PLLCTRL0_DIV_SEL(BV_CLKCTRL_PLLCTRL0_DIV_SEL__##e)
+#define BFM_CLKCTRL_PLLCTRL0_DIV_SEL_V(v)       BM_CLKCTRL_PLLCTRL0_DIV_SEL
+#define BP_CLKCTRL_PLLCTRL0_RSRVD3              19
+#define BM_CLKCTRL_PLLCTRL0_RSRVD3              0x80000
+#define BF_CLKCTRL_PLLCTRL0_RSRVD3(v)           (((v) & 0x1) << 19)
+#define BFM_CLKCTRL_PLLCTRL0_RSRVD3(v)          BM_CLKCTRL_PLLCTRL0_RSRVD3
+#define BF_CLKCTRL_PLLCTRL0_RSRVD3_V(e)         BF_CLKCTRL_PLLCTRL0_RSRVD3(BV_CLKCTRL_PLLCTRL0_RSRVD3__##e)
+#define BFM_CLKCTRL_PLLCTRL0_RSRVD3_V(v)        BM_CLKCTRL_PLLCTRL0_RSRVD3
+#define BP_CLKCTRL_PLLCTRL0_EN_USB_CLKS         18
+#define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS         0x40000
+#define BF_CLKCTRL_PLLCTRL0_EN_USB_CLKS(v)      (((v) & 0x1) << 18)
+#define BFM_CLKCTRL_PLLCTRL0_EN_USB_CLKS(v)     BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS
+#define BF_CLKCTRL_PLLCTRL0_EN_USB_CLKS_V(e)    BF_CLKCTRL_PLLCTRL0_EN_USB_CLKS(BV_CLKCTRL_PLLCTRL0_EN_USB_CLKS__##e)
+#define BFM_CLKCTRL_PLLCTRL0_EN_USB_CLKS_V(v)   BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS
+#define BP_CLKCTRL_PLLCTRL0_RSRVD2              17
+#define BM_CLKCTRL_PLLCTRL0_RSRVD2              0x20000
+#define BF_CLKCTRL_PLLCTRL0_RSRVD2(v)           (((v) & 0x1) << 17)
+#define BFM_CLKCTRL_PLLCTRL0_RSRVD2(v)          BM_CLKCTRL_PLLCTRL0_RSRVD2
+#define BF_CLKCTRL_PLLCTRL0_RSRVD2_V(e)         BF_CLKCTRL_PLLCTRL0_RSRVD2(BV_CLKCTRL_PLLCTRL0_RSRVD2__##e)
+#define BFM_CLKCTRL_PLLCTRL0_RSRVD2_V(v)        BM_CLKCTRL_PLLCTRL0_RSRVD2
+#define BP_CLKCTRL_PLLCTRL0_POWER               16
+#define BM_CLKCTRL_PLLCTRL0_POWER               0x10000
+#define BF_CLKCTRL_PLLCTRL0_POWER(v)            (((v) & 0x1) << 16)
+#define BFM_CLKCTRL_PLLCTRL0_POWER(v)           BM_CLKCTRL_PLLCTRL0_POWER
+#define BF_CLKCTRL_PLLCTRL0_POWER_V(e)          BF_CLKCTRL_PLLCTRL0_POWER(BV_CLKCTRL_PLLCTRL0_POWER__##e)
+#define BFM_CLKCTRL_PLLCTRL0_POWER_V(v)         BM_CLKCTRL_PLLCTRL0_POWER
+#define BP_CLKCTRL_PLLCTRL0_RSRVD1              0
+#define BM_CLKCTRL_PLLCTRL0_RSRVD1              0xffff
+#define BF_CLKCTRL_PLLCTRL0_RSRVD1(v)           (((v) & 0xffff) << 0)
+#define BFM_CLKCTRL_PLLCTRL0_RSRVD1(v)          BM_CLKCTRL_PLLCTRL0_RSRVD1
+#define BF_CLKCTRL_PLLCTRL0_RSRVD1_V(e)         BF_CLKCTRL_PLLCTRL0_RSRVD1(BV_CLKCTRL_PLLCTRL0_RSRVD1__##e)
+#define BFM_CLKCTRL_PLLCTRL0_RSRVD1_V(v)        BM_CLKCTRL_PLLCTRL0_RSRVD1
+
+#define HW_CLKCTRL_PLLCTRL1                     HW(CLKCTRL_PLLCTRL1)
+#define HWA_CLKCTRL_PLLCTRL1                    (0x80040000 + 0x10)
+#define HWT_CLKCTRL_PLLCTRL1                    HWIO_32_RW
+#define HWN_CLKCTRL_PLLCTRL1                    CLKCTRL_PLLCTRL1
+#define HWI_CLKCTRL_PLLCTRL1                    
+#define BP_CLKCTRL_PLLCTRL1_LOCK                31
+#define BM_CLKCTRL_PLLCTRL1_LOCK                0x80000000
+#define BF_CLKCTRL_PLLCTRL1_LOCK(v)             (((v) & 0x1) << 31)
+#define BFM_CLKCTRL_PLLCTRL1_LOCK(v)            BM_CLKCTRL_PLLCTRL1_LOCK
+#define BF_CLKCTRL_PLLCTRL1_LOCK_V(e)           BF_CLKCTRL_PLLCTRL1_LOCK(BV_CLKCTRL_PLLCTRL1_LOCK__##e)
+#define BFM_CLKCTRL_PLLCTRL1_LOCK_V(v)          BM_CLKCTRL_PLLCTRL1_LOCK
+#define BP_CLKCTRL_PLLCTRL1_FORCE_LOCK          30
+#define BM_CLKCTRL_PLLCTRL1_FORCE_LOCK          0x40000000
+#define BF_CLKCTRL_PLLCTRL1_FORCE_LOCK(v)       (((v) & 0x1) << 30)
+#define BFM_CLKCTRL_PLLCTRL1_FORCE_LOCK(v)      BM_CLKCTRL_PLLCTRL1_FORCE_LOCK
+#define BF_CLKCTRL_PLLCTRL1_FORCE_LOCK_V(e)     BF_CLKCTRL_PLLCTRL1_FORCE_LOCK(BV_CLKCTRL_PLLCTRL1_FORCE_LOCK__##e)
+#define BFM_CLKCTRL_PLLCTRL1_FORCE_LOCK_V(v)    BM_CLKCTRL_PLLCTRL1_FORCE_LOCK
+#define BP_CLKCTRL_PLLCTRL1_RSRVD1              16
+#define BM_CLKCTRL_PLLCTRL1_RSRVD1              0x3fff0000
+#define BF_CLKCTRL_PLLCTRL1_RSRVD1(v)           (((v) & 0x3fff) << 16)
+#define BFM_CLKCTRL_PLLCTRL1_RSRVD1(v)          BM_CLKCTRL_PLLCTRL1_RSRVD1
+#define BF_CLKCTRL_PLLCTRL1_RSRVD1_V(e)         BF_CLKCTRL_PLLCTRL1_RSRVD1(BV_CLKCTRL_PLLCTRL1_RSRVD1__##e)
+#define BFM_CLKCTRL_PLLCTRL1_RSRVD1_V(v)        BM_CLKCTRL_PLLCTRL1_RSRVD1
+#define BP_CLKCTRL_PLLCTRL1_LOCK_COUNT          0
+#define BM_CLKCTRL_PLLCTRL1_LOCK_COUNT          0xffff
+#define BF_CLKCTRL_PLLCTRL1_LOCK_COUNT(v)       (((v) & 0xffff) << 0)
+#define BFM_CLKCTRL_PLLCTRL1_LOCK_COUNT(v)      BM_CLKCTRL_PLLCTRL1_LOCK_COUNT
+#define BF_CLKCTRL_PLLCTRL1_LOCK_COUNT_V(e)     BF_CLKCTRL_PLLCTRL1_LOCK_COUNT(BV_CLKCTRL_PLLCTRL1_LOCK_COUNT__##e)
+#define BFM_CLKCTRL_PLLCTRL1_LOCK_COUNT_V(v)    BM_CLKCTRL_PLLCTRL1_LOCK_COUNT
+
+#define HW_CLKCTRL_CPU                          HW(CLKCTRL_CPU)
+#define HWA_CLKCTRL_CPU                         (0x80040000 + 0x20)
+#define HWT_CLKCTRL_CPU                         HWIO_32_RW
+#define HWN_CLKCTRL_CPU                         CLKCTRL_CPU
+#define HWI_CLKCTRL_CPU                         
+#define HW_CLKCTRL_CPU_SET                      HW(CLKCTRL_CPU_SET)
+#define HWA_CLKCTRL_CPU_SET                     (HWA_CLKCTRL_CPU + 0x4)
+#define HWT_CLKCTRL_CPU_SET                     HWIO_32_WO
+#define HWN_CLKCTRL_CPU_SET                     CLKCTRL_CPU
+#define HWI_CLKCTRL_CPU_SET                     
+#define HW_CLKCTRL_CPU_CLR                      HW(CLKCTRL_CPU_CLR)
+#define HWA_CLKCTRL_CPU_CLR                     (HWA_CLKCTRL_CPU + 0x8)
+#define HWT_CLKCTRL_CPU_CLR                     HWIO_32_WO
+#define HWN_CLKCTRL_CPU_CLR                     CLKCTRL_CPU
+#define HWI_CLKCTRL_CPU_CLR                     
+#define HW_CLKCTRL_CPU_TOG                      HW(CLKCTRL_CPU_TOG)
+#define HWA_CLKCTRL_CPU_TOG                     (HWA_CLKCTRL_CPU + 0xc)
+#define HWT_CLKCTRL_CPU_TOG                     HWIO_32_WO
+#define HWN_CLKCTRL_CPU_TOG                     CLKCTRL_CPU
+#define HWI_CLKCTRL_CPU_TOG                     
+#define BP_CLKCTRL_CPU_RSRVD5                   30
+#define BM_CLKCTRL_CPU_RSRVD5                   0xc0000000
+#define BF_CLKCTRL_CPU_RSRVD5(v)                (((v) & 0x3) << 30)
+#define BFM_CLKCTRL_CPU_RSRVD5(v)               BM_CLKCTRL_CPU_RSRVD5
+#define BF_CLKCTRL_CPU_RSRVD5_V(e)              BF_CLKCTRL_CPU_RSRVD5(BV_CLKCTRL_CPU_RSRVD5__##e)
+#define BFM_CLKCTRL_CPU_RSRVD5_V(v)             BM_CLKCTRL_CPU_RSRVD5
+#define BP_CLKCTRL_CPU_BUSY_REF_XTAL            29
+#define BM_CLKCTRL_CPU_BUSY_REF_XTAL            0x20000000
+#define BF_CLKCTRL_CPU_BUSY_REF_XTAL(v)         (((v) & 0x1) << 29)
+#define BFM_CLKCTRL_CPU_BUSY_REF_XTAL(v)        BM_CLKCTRL_CPU_BUSY_REF_XTAL
+#define BF_CLKCTRL_CPU_BUSY_REF_XTAL_V(e)       BF_CLKCTRL_CPU_BUSY_REF_XTAL(BV_CLKCTRL_CPU_BUSY_REF_XTAL__##e)
+#define BFM_CLKCTRL_CPU_BUSY_REF_XTAL_V(v)      BM_CLKCTRL_CPU_BUSY_REF_XTAL
+#define BP_CLKCTRL_CPU_BUSY_REF_CPU             28
+#define BM_CLKCTRL_CPU_BUSY_REF_CPU             0x10000000
+#define BF_CLKCTRL_CPU_BUSY_REF_CPU(v)          (((v) & 0x1) << 28)
+#define BFM_CLKCTRL_CPU_BUSY_REF_CPU(v)         BM_CLKCTRL_CPU_BUSY_REF_CPU
+#define BF_CLKCTRL_CPU_BUSY_REF_CPU_V(e)        BF_CLKCTRL_CPU_BUSY_REF_CPU(BV_CLKCTRL_CPU_BUSY_REF_CPU__##e)
+#define BFM_CLKCTRL_CPU_BUSY_REF_CPU_V(v)       BM_CLKCTRL_CPU_BUSY_REF_CPU
+#define BP_CLKCTRL_CPU_RSRVD4                   27
+#define BM_CLKCTRL_CPU_RSRVD4                   0x8000000
+#define BF_CLKCTRL_CPU_RSRVD4(v)                (((v) & 0x1) << 27)
+#define BFM_CLKCTRL_CPU_RSRVD4(v)               BM_CLKCTRL_CPU_RSRVD4
+#define BF_CLKCTRL_CPU_RSRVD4_V(e)              BF_CLKCTRL_CPU_RSRVD4(BV_CLKCTRL_CPU_RSRVD4__##e)
+#define BFM_CLKCTRL_CPU_RSRVD4_V(v)             BM_CLKCTRL_CPU_RSRVD4
+#define BP_CLKCTRL_CPU_DIV_XTAL_FRAC_EN         26
+#define BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN         0x4000000
+#define BF_CLKCTRL_CPU_DIV_XTAL_FRAC_EN(v)      (((v) & 0x1) << 26)
+#define BFM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN(v)     BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN
+#define BF_CLKCTRL_CPU_DIV_XTAL_FRAC_EN_V(e)    BF_CLKCTRL_CPU_DIV_XTAL_FRAC_EN(BV_CLKCTRL_CPU_DIV_XTAL_FRAC_EN__##e)
+#define BFM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN_V(v)   BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN
+#define BP_CLKCTRL_CPU_DIV_XTAL                 16
+#define BM_CLKCTRL_CPU_DIV_XTAL                 0x3ff0000
+#define BF_CLKCTRL_CPU_DIV_XTAL(v)              (((v) & 0x3ff) << 16)
+#define BFM_CLKCTRL_CPU_DIV_XTAL(v)             BM_CLKCTRL_CPU_DIV_XTAL
+#define BF_CLKCTRL_CPU_DIV_XTAL_V(e)            BF_CLKCTRL_CPU_DIV_XTAL(BV_CLKCTRL_CPU_DIV_XTAL__##e)
+#define BFM_CLKCTRL_CPU_DIV_XTAL_V(v)           BM_CLKCTRL_CPU_DIV_XTAL
+#define BP_CLKCTRL_CPU_RSRVD3                   13
+#define BM_CLKCTRL_CPU_RSRVD3                   0xe000
+#define BF_CLKCTRL_CPU_RSRVD3(v)                (((v) & 0x7) << 13)
+#define BFM_CLKCTRL_CPU_RSRVD3(v)               BM_CLKCTRL_CPU_RSRVD3
+#define BF_CLKCTRL_CPU_RSRVD3_V(e)              BF_CLKCTRL_CPU_RSRVD3(BV_CLKCTRL_CPU_RSRVD3__##e)
+#define BFM_CLKCTRL_CPU_RSRVD3_V(v)             BM_CLKCTRL_CPU_RSRVD3
+#define BP_CLKCTRL_CPU_INTERRUPT_WAIT           12
+#define BM_CLKCTRL_CPU_INTERRUPT_WAIT           0x1000
+#define BF_CLKCTRL_CPU_INTERRUPT_WAIT(v)        (((v) & 0x1) << 12)
+#define BFM_CLKCTRL_CPU_INTERRUPT_WAIT(v)       BM_CLKCTRL_CPU_INTERRUPT_WAIT
+#define BF_CLKCTRL_CPU_INTERRUPT_WAIT_V(e)      BF_CLKCTRL_CPU_INTERRUPT_WAIT(BV_CLKCTRL_CPU_INTERRUPT_WAIT__##e)
+#define BFM_CLKCTRL_CPU_INTERRUPT_WAIT_V(v)     BM_CLKCTRL_CPU_INTERRUPT_WAIT
+#define BP_CLKCTRL_CPU_RSRVD2                   11
+#define BM_CLKCTRL_CPU_RSRVD2                   0x800
+#define BF_CLKCTRL_CPU_RSRVD2(v)                (((v) & 0x1) << 11)
+#define BFM_CLKCTRL_CPU_RSRVD2(v)               BM_CLKCTRL_CPU_RSRVD2
+#define BF_CLKCTRL_CPU_RSRVD2_V(e)              BF_CLKCTRL_CPU_RSRVD2(BV_CLKCTRL_CPU_RSRVD2__##e)
+#define BFM_CLKCTRL_CPU_RSRVD2_V(v)             BM_CLKCTRL_CPU_RSRVD2
+#define BP_CLKCTRL_CPU_DIV_CPU_FRAC_EN          10
+#define BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN          0x400
+#define BF_CLKCTRL_CPU_DIV_CPU_FRAC_EN(v)       (((v) & 0x1) << 10)
+#define BFM_CLKCTRL_CPU_DIV_CPU_FRAC_EN(v)      BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN
+#define BF_CLKCTRL_CPU_DIV_CPU_FRAC_EN_V(e)     BF_CLKCTRL_CPU_DIV_CPU_FRAC_EN(BV_CLKCTRL_CPU_DIV_CPU_FRAC_EN__##e)
+#define BFM_CLKCTRL_CPU_DIV_CPU_FRAC_EN_V(v)    BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN
+#define BP_CLKCTRL_CPU_RSRVD1                   6
+#define BM_CLKCTRL_CPU_RSRVD1                   0x3c0
+#define BF_CLKCTRL_CPU_RSRVD1(v)                (((v) & 0xf) << 6)
+#define BFM_CLKCTRL_CPU_RSRVD1(v)               BM_CLKCTRL_CPU_RSRVD1
+#define BF_CLKCTRL_CPU_RSRVD1_V(e)              BF_CLKCTRL_CPU_RSRVD1(BV_CLKCTRL_CPU_RSRVD1__##e)
+#define BFM_CLKCTRL_CPU_RSRVD1_V(v)             BM_CLKCTRL_CPU_RSRVD1
+#define BP_CLKCTRL_CPU_DIV_CPU                  0
+#define BM_CLKCTRL_CPU_DIV_CPU                  0x3f
+#define BF_CLKCTRL_CPU_DIV_CPU(v)               (((v) & 0x3f) << 0)
+#define BFM_CLKCTRL_CPU_DIV_CPU(v)              BM_CLKCTRL_CPU_DIV_CPU
+#define BF_CLKCTRL_CPU_DIV_CPU_V(e)             BF_CLKCTRL_CPU_DIV_CPU(BV_CLKCTRL_CPU_DIV_CPU__##e)
+#define BFM_CLKCTRL_CPU_DIV_CPU_V(v)            BM_CLKCTRL_CPU_DIV_CPU
+
+#define HW_CLKCTRL_HBUS                             HW(CLKCTRL_HBUS)
+#define HWA_CLKCTRL_HBUS                            (0x80040000 + 0x30)
+#define HWT_CLKCTRL_HBUS                            HWIO_32_RW
+#define HWN_CLKCTRL_HBUS                            CLKCTRL_HBUS
+#define HWI_CLKCTRL_HBUS                            
+#define HW_CLKCTRL_HBUS_SET                         HW(CLKCTRL_HBUS_SET)
+#define HWA_CLKCTRL_HBUS_SET                        (HWA_CLKCTRL_HBUS + 0x4)
+#define HWT_CLKCTRL_HBUS_SET                        HWIO_32_WO
+#define HWN_CLKCTRL_HBUS_SET                        CLKCTRL_HBUS
+#define HWI_CLKCTRL_HBUS_SET                        
+#define HW_CLKCTRL_HBUS_CLR                         HW(CLKCTRL_HBUS_CLR)
+#define HWA_CLKCTRL_HBUS_CLR                        (HWA_CLKCTRL_HBUS + 0x8)
+#define HWT_CLKCTRL_HBUS_CLR                        HWIO_32_WO
+#define HWN_CLKCTRL_HBUS_CLR                        CLKCTRL_HBUS
+#define HWI_CLKCTRL_HBUS_CLR                        
+#define HW_CLKCTRL_HBUS_TOG                         HW(CLKCTRL_HBUS_TOG)
+#define HWA_CLKCTRL_HBUS_TOG                        (HWA_CLKCTRL_HBUS + 0xc)
+#define HWT_CLKCTRL_HBUS_TOG                        HWIO_32_WO
+#define HWN_CLKCTRL_HBUS_TOG                        CLKCTRL_HBUS
+#define HWI_CLKCTRL_HBUS_TOG                        
+#define BP_CLKCTRL_HBUS_RSRVD4                      30
+#define BM_CLKCTRL_HBUS_RSRVD4                      0xc0000000
+#define BF_CLKCTRL_HBUS_RSRVD4(v)                   (((v) & 0x3) << 30)
+#define BFM_CLKCTRL_HBUS_RSRVD4(v)                  BM_CLKCTRL_HBUS_RSRVD4
+#define BF_CLKCTRL_HBUS_RSRVD4_V(e)                 BF_CLKCTRL_HBUS_RSRVD4(BV_CLKCTRL_HBUS_RSRVD4__##e)
+#define BFM_CLKCTRL_HBUS_RSRVD4_V(v)                BM_CLKCTRL_HBUS_RSRVD4
+#define BP_CLKCTRL_HBUS_BUSY                        29
+#define BM_CLKCTRL_HBUS_BUSY                        0x20000000
+#define BF_CLKCTRL_HBUS_BUSY(v)                     (((v) & 0x1) << 29)
+#define BFM_CLKCTRL_HBUS_BUSY(v)                    BM_CLKCTRL_HBUS_BUSY
+#define BF_CLKCTRL_HBUS_BUSY_V(e)                   BF_CLKCTRL_HBUS_BUSY(BV_CLKCTRL_HBUS_BUSY__##e)
+#define BFM_CLKCTRL_HBUS_BUSY_V(v)                  BM_CLKCTRL_HBUS_BUSY
+#define BP_CLKCTRL_HBUS_DCP_AS_ENABLE               28
+#define BM_CLKCTRL_HBUS_DCP_AS_ENABLE               0x10000000
+#define BF_CLKCTRL_HBUS_DCP_AS_ENABLE(v)            (((v) & 0x1) << 28)
+#define BFM_CLKCTRL_HBUS_DCP_AS_ENABLE(v)           BM_CLKCTRL_HBUS_DCP_AS_ENABLE
+#define BF_CLKCTRL_HBUS_DCP_AS_ENABLE_V(e)          BF_CLKCTRL_HBUS_DCP_AS_ENABLE(BV_CLKCTRL_HBUS_DCP_AS_ENABLE__##e)
+#define BFM_CLKCTRL_HBUS_DCP_AS_ENABLE_V(v)         BM_CLKCTRL_HBUS_DCP_AS_ENABLE
+#define BP_CLKCTRL_HBUS_PXP_AS_ENABLE               27
+#define BM_CLKCTRL_HBUS_PXP_AS_ENABLE               0x8000000
+#define BF_CLKCTRL_HBUS_PXP_AS_ENABLE(v)            (((v) & 0x1) << 27)
+#define BFM_CLKCTRL_HBUS_PXP_AS_ENABLE(v)           BM_CLKCTRL_HBUS_PXP_AS_ENABLE
+#define BF_CLKCTRL_HBUS_PXP_AS_ENABLE_V(e)          BF_CLKCTRL_HBUS_PXP_AS_ENABLE(BV_CLKCTRL_HBUS_PXP_AS_ENABLE__##e)
+#define BFM_CLKCTRL_HBUS_PXP_AS_ENABLE_V(v)         BM_CLKCTRL_HBUS_PXP_AS_ENABLE
+#define BP_CLKCTRL_HBUS_APBHDMA_AS_ENABLE           26
+#define BM_CLKCTRL_HBUS_APBHDMA_AS_ENABLE           0x4000000
+#define BF_CLKCTRL_HBUS_APBHDMA_AS_ENABLE(v)        (((v) & 0x1) << 26)
+#define BFM_CLKCTRL_HBUS_APBHDMA_AS_ENABLE(v)       BM_CLKCTRL_HBUS_APBHDMA_AS_ENABLE
+#define BF_CLKCTRL_HBUS_APBHDMA_AS_ENABLE_V(e)      BF_CLKCTRL_HBUS_APBHDMA_AS_ENABLE(BV_CLKCTRL_HBUS_APBHDMA_AS_ENABLE__##e)
+#define BFM_CLKCTRL_HBUS_APBHDMA_AS_ENABLE_V(v)     BM_CLKCTRL_HBUS_APBHDMA_AS_ENABLE
+#define BP_CLKCTRL_HBUS_APBXDMA_AS_ENABLE           25
+#define BM_CLKCTRL_HBUS_APBXDMA_AS_ENABLE           0x2000000
+#define BF_CLKCTRL_HBUS_APBXDMA_AS_ENABLE(v)        (((v) & 0x1) << 25)
+#define BFM_CLKCTRL_HBUS_APBXDMA_AS_ENABLE(v)       BM_CLKCTRL_HBUS_APBXDMA_AS_ENABLE
+#define BF_CLKCTRL_HBUS_APBXDMA_AS_ENABLE_V(e)      BF_CLKCTRL_HBUS_APBXDMA_AS_ENABLE(BV_CLKCTRL_HBUS_APBXDMA_AS_ENABLE__##e)
+#define BFM_CLKCTRL_HBUS_APBXDMA_AS_ENABLE_V(v)     BM_CLKCTRL_HBUS_APBXDMA_AS_ENABLE
+#define BP_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE       24
+#define BM_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE       0x1000000
+#define BF_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE(v)    (((v) & 0x1) << 24)
+#define BFM_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE(v)   BM_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE
+#define BF_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE_V(e)  BF_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE(BV_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE__##e)
+#define BFM_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE_V(v) BM_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE
+#define BP_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE           23
+#define BM_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE           0x800000
+#define BF_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE(v)        (((v) & 0x1) << 23)
+#define BFM_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE(v)       BM_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE
+#define BF_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE_V(e)      BF_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE(BV_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE__##e)
+#define BFM_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE_V(v)     BM_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE
+#define BP_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE          22
+#define BM_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE          0x400000
+#define BF_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE(v)       (((v) & 0x1) << 22)
+#define BFM_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE(v)      BM_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE
+#define BF_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE_V(e)     BF_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE(BV_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE__##e)
+#define BFM_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE_V(v)    BM_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE
+#define BP_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE         21
+#define BM_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE         0x200000
+#define BF_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE(v)      (((v) & 0x1) << 21)
+#define BFM_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE(v)     BM_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE
+#define BF_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE_V(e)    BF_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE(BV_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE__##e)
+#define BFM_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE_V(v)   BM_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE
+#define BP_CLKCTRL_HBUS_AUTO_SLOW_MODE              20
+#define BM_CLKCTRL_HBUS_AUTO_SLOW_MODE              0x100000
+#define BF_CLKCTRL_HBUS_AUTO_SLOW_MODE(v)           (((v) & 0x1) << 20)
+#define BFM_CLKCTRL_HBUS_AUTO_SLOW_MODE(v)          BM_CLKCTRL_HBUS_AUTO_SLOW_MODE
+#define BF_CLKCTRL_HBUS_AUTO_SLOW_MODE_V(e)         BF_CLKCTRL_HBUS_AUTO_SLOW_MODE(BV_CLKCTRL_HBUS_AUTO_SLOW_MODE__##e)
+#define BFM_CLKCTRL_HBUS_AUTO_SLOW_MODE_V(v)        BM_CLKCTRL_HBUS_AUTO_SLOW_MODE
+#define BP_CLKCTRL_HBUS_RSRVD2                      19
+#define BM_CLKCTRL_HBUS_RSRVD2                      0x80000
+#define BF_CLKCTRL_HBUS_RSRVD2(v)                   (((v) & 0x1) << 19)
+#define BFM_CLKCTRL_HBUS_RSRVD2(v)                  BM_CLKCTRL_HBUS_RSRVD2
+#define BF_CLKCTRL_HBUS_RSRVD2_V(e)                 BF_CLKCTRL_HBUS_RSRVD2(BV_CLKCTRL_HBUS_RSRVD2__##e)
+#define BFM_CLKCTRL_HBUS_RSRVD2_V(v)                BM_CLKCTRL_HBUS_RSRVD2
+#define BP_CLKCTRL_HBUS_SLOW_DIV                    16
+#define BM_CLKCTRL_HBUS_SLOW_DIV                    0x70000
+#define BV_CLKCTRL_HBUS_SLOW_DIV__BY1               0x0
+#define BV_CLKCTRL_HBUS_SLOW_DIV__BY2               0x1
+#define BV_CLKCTRL_HBUS_SLOW_DIV__BY4               0x2
+#define BV_CLKCTRL_HBUS_SLOW_DIV__BY8               0x3
+#define BV_CLKCTRL_HBUS_SLOW_DIV__BY16              0x4
+#define BV_CLKCTRL_HBUS_SLOW_DIV__BY32              0x5
+#define BF_CLKCTRL_HBUS_SLOW_DIV(v)                 (((v) & 0x7) << 16)
+#define BFM_CLKCTRL_HBUS_SLOW_DIV(v)                BM_CLKCTRL_HBUS_SLOW_DIV
+#define BF_CLKCTRL_HBUS_SLOW_DIV_V(e)               BF_CLKCTRL_HBUS_SLOW_DIV(BV_CLKCTRL_HBUS_SLOW_DIV__##e)
+#define BFM_CLKCTRL_HBUS_SLOW_DIV_V(v)              BM_CLKCTRL_HBUS_SLOW_DIV
+#define BP_CLKCTRL_HBUS_RSRVD1                      6
+#define BM_CLKCTRL_HBUS_RSRVD1                      0xffc0
+#define BF_CLKCTRL_HBUS_RSRVD1(v)                   (((v) & 0x3ff) << 6)
+#define BFM_CLKCTRL_HBUS_RSRVD1(v)                  BM_CLKCTRL_HBUS_RSRVD1
+#define BF_CLKCTRL_HBUS_RSRVD1_V(e)                 BF_CLKCTRL_HBUS_RSRVD1(BV_CLKCTRL_HBUS_RSRVD1__##e)
+#define BFM_CLKCTRL_HBUS_RSRVD1_V(v)                BM_CLKCTRL_HBUS_RSRVD1
+#define BP_CLKCTRL_HBUS_DIV_FRAC_EN                 5
+#define BM_CLKCTRL_HBUS_DIV_FRAC_EN                 0x20
+#define BF_CLKCTRL_HBUS_DIV_FRAC_EN(v)              (((v) & 0x1) << 5)
+#define BFM_CLKCTRL_HBUS_DIV_FRAC_EN(v)             BM_CLKCTRL_HBUS_DIV_FRAC_EN
+#define BF_CLKCTRL_HBUS_DIV_FRAC_EN_V(e)            BF_CLKCTRL_HBUS_DIV_FRAC_EN(BV_CLKCTRL_HBUS_DIV_FRAC_EN__##e)
+#define BFM_CLKCTRL_HBUS_DIV_FRAC_EN_V(v)           BM_CLKCTRL_HBUS_DIV_FRAC_EN
+#define BP_CLKCTRL_HBUS_DIV                         0
+#define BM_CLKCTRL_HBUS_DIV                         0x1f
+#define BF_CLKCTRL_HBUS_DIV(v)                      (((v) & 0x1f) << 0)
+#define BFM_CLKCTRL_HBUS_DIV(v)                     BM_CLKCTRL_HBUS_DIV
+#define BF_CLKCTRL_HBUS_DIV_V(e)                    BF_CLKCTRL_HBUS_DIV(BV_CLKCTRL_HBUS_DIV__##e)
+#define BFM_CLKCTRL_HBUS_DIV_V(v)                   BM_CLKCTRL_HBUS_DIV
+
+#define HW_CLKCTRL_XBUS                     HW(CLKCTRL_XBUS)
+#define HWA_CLKCTRL_XBUS                    (0x80040000 + 0x40)
+#define HWT_CLKCTRL_XBUS                    HWIO_32_RW
+#define HWN_CLKCTRL_XBUS                    CLKCTRL_XBUS
+#define HWI_CLKCTRL_XBUS                    
+#define BP_CLKCTRL_XBUS_BUSY                31
+#define BM_CLKCTRL_XBUS_BUSY                0x80000000
+#define BF_CLKCTRL_XBUS_BUSY(v)             (((v) & 0x1) << 31)
+#define BFM_CLKCTRL_XBUS_BUSY(v)            BM_CLKCTRL_XBUS_BUSY
+#define BF_CLKCTRL_XBUS_BUSY_V(e)           BF_CLKCTRL_XBUS_BUSY(BV_CLKCTRL_XBUS_BUSY__##e)
+#define BFM_CLKCTRL_XBUS_BUSY_V(v)          BM_CLKCTRL_XBUS_BUSY
+#define BP_CLKCTRL_XBUS_RSRVD1              11
+#define BM_CLKCTRL_XBUS_RSRVD1              0x7ffff800
+#define BF_CLKCTRL_XBUS_RSRVD1(v)           (((v) & 0xfffff) << 11)
+#define BFM_CLKCTRL_XBUS_RSRVD1(v)          BM_CLKCTRL_XBUS_RSRVD1
+#define BF_CLKCTRL_XBUS_RSRVD1_V(e)         BF_CLKCTRL_XBUS_RSRVD1(BV_CLKCTRL_XBUS_RSRVD1__##e)
+#define BFM_CLKCTRL_XBUS_RSRVD1_V(v)        BM_CLKCTRL_XBUS_RSRVD1
+#define BP_CLKCTRL_XBUS_DIV_FRAC_EN         10
+#define BM_CLKCTRL_XBUS_DIV_FRAC_EN         0x400
+#define BF_CLKCTRL_XBUS_DIV_FRAC_EN(v)      (((v) & 0x1) << 10)
+#define BFM_CLKCTRL_XBUS_DIV_FRAC_EN(v)     BM_CLKCTRL_XBUS_DIV_FRAC_EN
+#define BF_CLKCTRL_XBUS_DIV_FRAC_EN_V(e)    BF_CLKCTRL_XBUS_DIV_FRAC_EN(BV_CLKCTRL_XBUS_DIV_FRAC_EN__##e)
+#define BFM_CLKCTRL_XBUS_DIV_FRAC_EN_V(v)   BM_CLKCTRL_XBUS_DIV_FRAC_EN
+#define BP_CLKCTRL_XBUS_DIV                 0
+#define BM_CLKCTRL_XBUS_DIV                 0x3ff
+#define BF_CLKCTRL_XBUS_DIV(v)              (((v) & 0x3ff) << 0)
+#define BFM_CLKCTRL_XBUS_DIV(v)             BM_CLKCTRL_XBUS_DIV
+#define BF_CLKCTRL_XBUS_DIV_V(e)            BF_CLKCTRL_XBUS_DIV(BV_CLKCTRL_XBUS_DIV__##e)
+#define BFM_CLKCTRL_XBUS_DIV_V(v)           BM_CLKCTRL_XBUS_DIV
+
+#define HW_CLKCTRL_XTAL                             HW(CLKCTRL_XTAL)
+#define HWA_CLKCTRL_XTAL                            (0x80040000 + 0x50)
+#define HWT_CLKCTRL_XTAL                            HWIO_32_RW
+#define HWN_CLKCTRL_XTAL                            CLKCTRL_XTAL
+#define HWI_CLKCTRL_XTAL                            
+#define HW_CLKCTRL_XTAL_SET                         HW(CLKCTRL_XTAL_SET)
+#define HWA_CLKCTRL_XTAL_SET                        (HWA_CLKCTRL_XTAL + 0x4)
+#define HWT_CLKCTRL_XTAL_SET                        HWIO_32_WO
+#define HWN_CLKCTRL_XTAL_SET                        CLKCTRL_XTAL
+#define HWI_CLKCTRL_XTAL_SET                        
+#define HW_CLKCTRL_XTAL_CLR                         HW(CLKCTRL_XTAL_CLR)
+#define HWA_CLKCTRL_XTAL_CLR                        (HWA_CLKCTRL_XTAL + 0x8)
+#define HWT_CLKCTRL_XTAL_CLR                        HWIO_32_WO
+#define HWN_CLKCTRL_XTAL_CLR                        CLKCTRL_XTAL
+#define HWI_CLKCTRL_XTAL_CLR                        
+#define HW_CLKCTRL_XTAL_TOG                         HW(CLKCTRL_XTAL_TOG)
+#define HWA_CLKCTRL_XTAL_TOG                        (HWA_CLKCTRL_XTAL + 0xc)
+#define HWT_CLKCTRL_XTAL_TOG                        HWIO_32_WO
+#define HWN_CLKCTRL_XTAL_TOG                        CLKCTRL_XTAL
+#define HWI_CLKCTRL_XTAL_TOG                        
+#define BP_CLKCTRL_XTAL_UART_CLK_GATE               31
+#define BM_CLKCTRL_XTAL_UART_CLK_GATE               0x80000000
+#define BF_CLKCTRL_XTAL_UART_CLK_GATE(v)            (((v) & 0x1) << 31)
+#define BFM_CLKCTRL_XTAL_UART_CLK_GATE(v)           BM_CLKCTRL_XTAL_UART_CLK_GATE
+#define BF_CLKCTRL_XTAL_UART_CLK_GATE_V(e)          BF_CLKCTRL_XTAL_UART_CLK_GATE(BV_CLKCTRL_XTAL_UART_CLK_GATE__##e)
+#define BFM_CLKCTRL_XTAL_UART_CLK_GATE_V(v)         BM_CLKCTRL_XTAL_UART_CLK_GATE
+#define BP_CLKCTRL_XTAL_FILT_CLK24M_GATE            30
+#define BM_CLKCTRL_XTAL_FILT_CLK24M_GATE            0x40000000
+#define BF_CLKCTRL_XTAL_FILT_CLK24M_GATE(v)         (((v) & 0x1) << 30)
+#define BFM_CLKCTRL_XTAL_FILT_CLK24M_GATE(v)        BM_CLKCTRL_XTAL_FILT_CLK24M_GATE
+#define BF_CLKCTRL_XTAL_FILT_CLK24M_GATE_V(e)       BF_CLKCTRL_XTAL_FILT_CLK24M_GATE(BV_CLKCTRL_XTAL_FILT_CLK24M_GATE__##e)
+#define BFM_CLKCTRL_XTAL_FILT_CLK24M_GATE_V(v)      BM_CLKCTRL_XTAL_FILT_CLK24M_GATE
+#define BP_CLKCTRL_XTAL_PWM_CLK24M_GATE             29
+#define BM_CLKCTRL_XTAL_PWM_CLK24M_GATE             0x20000000
+#define BF_CLKCTRL_XTAL_PWM_CLK24M_GATE(v)          (((v) & 0x1) << 29)
+#define BFM_CLKCTRL_XTAL_PWM_CLK24M_GATE(v)         BM_CLKCTRL_XTAL_PWM_CLK24M_GATE
+#define BF_CLKCTRL_XTAL_PWM_CLK24M_GATE_V(e)        BF_CLKCTRL_XTAL_PWM_CLK24M_GATE(BV_CLKCTRL_XTAL_PWM_CLK24M_GATE__##e)
+#define BFM_CLKCTRL_XTAL_PWM_CLK24M_GATE_V(v)       BM_CLKCTRL_XTAL_PWM_CLK24M_GATE
+#define BP_CLKCTRL_XTAL_DRI_CLK24M_GATE             28
+#define BM_CLKCTRL_XTAL_DRI_CLK24M_GATE             0x10000000
+#define BF_CLKCTRL_XTAL_DRI_CLK24M_GATE(v)          (((v) & 0x1) << 28)
+#define BFM_CLKCTRL_XTAL_DRI_CLK24M_GATE(v)         BM_CLKCTRL_XTAL_DRI_CLK24M_GATE
+#define BF_CLKCTRL_XTAL_DRI_CLK24M_GATE_V(e)        BF_CLKCTRL_XTAL_DRI_CLK24M_GATE(BV_CLKCTRL_XTAL_DRI_CLK24M_GATE__##e)
+#define BFM_CLKCTRL_XTAL_DRI_CLK24M_GATE_V(v)       BM_CLKCTRL_XTAL_DRI_CLK24M_GATE
+#define BP_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE          27
+#define BM_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE          0x8000000
+#define BF_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE(v)       (((v) & 0x1) << 27)
+#define BFM_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE(v)      BM_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE
+#define BF_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE_V(e)     BF_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE(BV_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE__##e)
+#define BFM_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE_V(v)    BM_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE
+#define BP_CLKCTRL_XTAL_TIMROT_CLK32K_GATE          26
+#define BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE          0x4000000
+#define BF_CLKCTRL_XTAL_TIMROT_CLK32K_GATE(v)       (((v) & 0x1) << 26)
+#define BFM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE(v)      BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE
+#define BF_CLKCTRL_XTAL_TIMROT_CLK32K_GATE_V(e)     BF_CLKCTRL_XTAL_TIMROT_CLK32K_GATE(BV_CLKCTRL_XTAL_TIMROT_CLK32K_GATE__##e)
+#define BFM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE_V(v)    BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE
+#define BP_CLKCTRL_XTAL_RSRVD1                      2
+#define BM_CLKCTRL_XTAL_RSRVD1                      0x3fffffc
+#define BF_CLKCTRL_XTAL_RSRVD1(v)                   (((v) & 0xffffff) << 2)
+#define BFM_CLKCTRL_XTAL_RSRVD1(v)                  BM_CLKCTRL_XTAL_RSRVD1
+#define BF_CLKCTRL_XTAL_RSRVD1_V(e)                 BF_CLKCTRL_XTAL_RSRVD1(BV_CLKCTRL_XTAL_RSRVD1__##e)
+#define BFM_CLKCTRL_XTAL_RSRVD1_V(v)                BM_CLKCTRL_XTAL_RSRVD1
+#define BP_CLKCTRL_XTAL_DIV_UART                    0
+#define BM_CLKCTRL_XTAL_DIV_UART                    0x3
+#define BF_CLKCTRL_XTAL_DIV_UART(v)                 (((v) & 0x3) << 0)
+#define BFM_CLKCTRL_XTAL_DIV_UART(v)                BM_CLKCTRL_XTAL_DIV_UART
+#define BF_CLKCTRL_XTAL_DIV_UART_V(e)               BF_CLKCTRL_XTAL_DIV_UART(BV_CLKCTRL_XTAL_DIV_UART__##e)
+#define BFM_CLKCTRL_XTAL_DIV_UART_V(v)              BM_CLKCTRL_XTAL_DIV_UART
+
+#define HW_CLKCTRL_PIX                      HW(CLKCTRL_PIX)
+#define HWA_CLKCTRL_PIX                     (0x80040000 + 0x60)
+#define HWT_CLKCTRL_PIX                     HWIO_32_RW
+#define HWN_CLKCTRL_PIX                     CLKCTRL_PIX
+#define HWI_CLKCTRL_PIX                     
+#define BP_CLKCTRL_PIX_CLKGATE              31
+#define BM_CLKCTRL_PIX_CLKGATE              0x80000000
+#define BF_CLKCTRL_PIX_CLKGATE(v)           (((v) & 0x1) << 31)
+#define BFM_CLKCTRL_PIX_CLKGATE(v)          BM_CLKCTRL_PIX_CLKGATE
+#define BF_CLKCTRL_PIX_CLKGATE_V(e)         BF_CLKCTRL_PIX_CLKGATE(BV_CLKCTRL_PIX_CLKGATE__##e)
+#define BFM_CLKCTRL_PIX_CLKGATE_V(v)        BM_CLKCTRL_PIX_CLKGATE
+#define BP_CLKCTRL_PIX_RSRVD2               30
+#define BM_CLKCTRL_PIX_RSRVD2               0x40000000
+#define BF_CLKCTRL_PIX_RSRVD2(v)            (((v) & 0x1) << 30)
+#define BFM_CLKCTRL_PIX_RSRVD2(v)           BM_CLKCTRL_PIX_RSRVD2
+#define BF_CLKCTRL_PIX_RSRVD2_V(e)          BF_CLKCTRL_PIX_RSRVD2(BV_CLKCTRL_PIX_RSRVD2__##e)
+#define BFM_CLKCTRL_PIX_RSRVD2_V(v)         BM_CLKCTRL_PIX_RSRVD2
+#define BP_CLKCTRL_PIX_BUSY                 29
+#define BM_CLKCTRL_PIX_BUSY                 0x20000000
+#define BF_CLKCTRL_PIX_BUSY(v)              (((v) & 0x1) << 29)
+#define BFM_CLKCTRL_PIX_BUSY(v)             BM_CLKCTRL_PIX_BUSY
+#define BF_CLKCTRL_PIX_BUSY_V(e)            BF_CLKCTRL_PIX_BUSY(BV_CLKCTRL_PIX_BUSY__##e)
+#define BFM_CLKCTRL_PIX_BUSY_V(v)           BM_CLKCTRL_PIX_BUSY
+#define BP_CLKCTRL_PIX_RSRVD1               13
+#define BM_CLKCTRL_PIX_RSRVD1               0x1fffe000
+#define BF_CLKCTRL_PIX_RSRVD1(v)            (((v) & 0xffff) << 13)
+#define BFM_CLKCTRL_PIX_RSRVD1(v)           BM_CLKCTRL_PIX_RSRVD1
+#define BF_CLKCTRL_PIX_RSRVD1_V(e)          BF_CLKCTRL_PIX_RSRVD1(BV_CLKCTRL_PIX_RSRVD1__##e)
+#define BFM_CLKCTRL_PIX_RSRVD1_V(v)         BM_CLKCTRL_PIX_RSRVD1
+#define BP_CLKCTRL_PIX_DIV_FRAC_EN          12
+#define BM_CLKCTRL_PIX_DIV_FRAC_EN          0x1000
+#define BF_CLKCTRL_PIX_DIV_FRAC_EN(v)       (((v) & 0x1) << 12)
+#define BFM_CLKCTRL_PIX_DIV_FRAC_EN(v)      BM_CLKCTRL_PIX_DIV_FRAC_EN
+#define BF_CLKCTRL_PIX_DIV_FRAC_EN_V(e)     BF_CLKCTRL_PIX_DIV_FRAC_EN(BV_CLKCTRL_PIX_DIV_FRAC_EN__##e)
+#define BFM_CLKCTRL_PIX_DIV_FRAC_EN_V(v)    BM_CLKCTRL_PIX_DIV_FRAC_EN
+#define BP_CLKCTRL_PIX_DIV                  0
+#define BM_CLKCTRL_PIX_DIV                  0xfff
+#define BF_CLKCTRL_PIX_DIV(v)               (((v) & 0xfff) << 0)
+#define BFM_CLKCTRL_PIX_DIV(v)              BM_CLKCTRL_PIX_DIV
+#define BF_CLKCTRL_PIX_DIV_V(e)             BF_CLKCTRL_PIX_DIV(BV_CLKCTRL_PIX_DIV__##e)
+#define BFM_CLKCTRL_PIX_DIV_V(v)            BM_CLKCTRL_PIX_DIV
+
+#define HW_CLKCTRL_SSP                      HW(CLKCTRL_SSP)
+#define HWA_CLKCTRL_SSP                     (0x80040000 + 0x70)
+#define HWT_CLKCTRL_SSP                     HWIO_32_RW
+#define HWN_CLKCTRL_SSP                     CLKCTRL_SSP
+#define HWI_CLKCTRL_SSP                     
+#define BP_CLKCTRL_SSP_CLKGATE              31
+#define BM_CLKCTRL_SSP_CLKGATE              0x80000000
+#define BF_CLKCTRL_SSP_CLKGATE(v)           (((v) & 0x1) << 31)
+#define BFM_CLKCTRL_SSP_CLKGATE(v)          BM_CLKCTRL_SSP_CLKGATE
+#define BF_CLKCTRL_SSP_CLKGATE_V(e)         BF_CLKCTRL_SSP_CLKGATE(BV_CLKCTRL_SSP_CLKGATE__##e)
+#define BFM_CLKCTRL_SSP_CLKGATE_V(v)        BM_CLKCTRL_SSP_CLKGATE
+#define BP_CLKCTRL_SSP_RSRVD2               30
+#define BM_CLKCTRL_SSP_RSRVD2               0x40000000
+#define BF_CLKCTRL_SSP_RSRVD2(v)            (((v) & 0x1) << 30)
+#define BFM_CLKCTRL_SSP_RSRVD2(v)           BM_CLKCTRL_SSP_RSRVD2
+#define BF_CLKCTRL_SSP_RSRVD2_V(e)          BF_CLKCTRL_SSP_RSRVD2(BV_CLKCTRL_SSP_RSRVD2__##e)
+#define BFM_CLKCTRL_SSP_RSRVD2_V(v)         BM_CLKCTRL_SSP_RSRVD2
+#define BP_CLKCTRL_SSP_BUSY                 29
+#define BM_CLKCTRL_SSP_BUSY                 0x20000000
+#define BF_CLKCTRL_SSP_BUSY(v)              (((v) & 0x1) << 29)
+#define BFM_CLKCTRL_SSP_BUSY(v)             BM_CLKCTRL_SSP_BUSY
+#define BF_CLKCTRL_SSP_BUSY_V(e)            BF_CLKCTRL_SSP_BUSY(BV_CLKCTRL_SSP_BUSY__##e)
+#define BFM_CLKCTRL_SSP_BUSY_V(v)           BM_CLKCTRL_SSP_BUSY
+#define BP_CLKCTRL_SSP_RSRVD1               10
+#define BM_CLKCTRL_SSP_RSRVD1               0x1ffffc00
+#define BF_CLKCTRL_SSP_RSRVD1(v)            (((v) & 0x7ffff) << 10)
+#define BFM_CLKCTRL_SSP_RSRVD1(v)           BM_CLKCTRL_SSP_RSRVD1
+#define BF_CLKCTRL_SSP_RSRVD1_V(e)          BF_CLKCTRL_SSP_RSRVD1(BV_CLKCTRL_SSP_RSRVD1__##e)
+#define BFM_CLKCTRL_SSP_RSRVD1_V(v)         BM_CLKCTRL_SSP_RSRVD1
+#define BP_CLKCTRL_SSP_DIV_FRAC_EN          9
+#define BM_CLKCTRL_SSP_DIV_FRAC_EN          0x200
+#define BF_CLKCTRL_SSP_DIV_FRAC_EN(v)       (((v) & 0x1) << 9)
+#define BFM_CLKCTRL_SSP_DIV_FRAC_EN(v)      BM_CLKCTRL_SSP_DIV_FRAC_EN
+#define BF_CLKCTRL_SSP_DIV_FRAC_EN_V(e)     BF_CLKCTRL_SSP_DIV_FRAC_EN(BV_CLKCTRL_SSP_DIV_FRAC_EN__##e)
+#define BFM_CLKCTRL_SSP_DIV_FRAC_EN_V(v)    BM_CLKCTRL_SSP_DIV_FRAC_EN
+#define BP_CLKCTRL_SSP_DIV                  0
+#define BM_CLKCTRL_SSP_DIV                  0x1ff
+#define BF_CLKCTRL_SSP_DIV(v)               (((v) & 0x1ff) << 0)
+#define BFM_CLKCTRL_SSP_DIV(v)              BM_CLKCTRL_SSP_DIV
+#define BF_CLKCTRL_SSP_DIV_V(e)             BF_CLKCTRL_SSP_DIV(BV_CLKCTRL_SSP_DIV__##e)
+#define BFM_CLKCTRL_SSP_DIV_V(v)            BM_CLKCTRL_SSP_DIV
+
+#define HW_CLKCTRL_GPMI                     HW(CLKCTRL_GPMI)
+#define HWA_CLKCTRL_GPMI                    (0x80040000 + 0x80)
+#define HWT_CLKCTRL_GPMI                    HWIO_32_RW
+#define HWN_CLKCTRL_GPMI                    CLKCTRL_GPMI
+#define HWI_CLKCTRL_GPMI                    
+#define BP_CLKCTRL_GPMI_CLKGATE             31
+#define BM_CLKCTRL_GPMI_CLKGATE             0x80000000
+#define BF_CLKCTRL_GPMI_CLKGATE(v)          (((v) & 0x1) << 31)
+#define BFM_CLKCTRL_GPMI_CLKGATE(v)         BM_CLKCTRL_GPMI_CLKGATE
+#define BF_CLKCTRL_GPMI_CLKGATE_V(e)        BF_CLKCTRL_GPMI_CLKGATE(BV_CLKCTRL_GPMI_CLKGATE__##e)
+#define BFM_CLKCTRL_GPMI_CLKGATE_V(v)       BM_CLKCTRL_GPMI_CLKGATE
+#define BP_CLKCTRL_GPMI_RSRVD2              30
+#define BM_CLKCTRL_GPMI_RSRVD2              0x40000000
+#define BF_CLKCTRL_GPMI_RSRVD2(v)           (((v) & 0x1) << 30)
+#define BFM_CLKCTRL_GPMI_RSRVD2(v)          BM_CLKCTRL_GPMI_RSRVD2
+#define BF_CLKCTRL_GPMI_RSRVD2_V(e)         BF_CLKCTRL_GPMI_RSRVD2(BV_CLKCTRL_GPMI_RSRVD2__##e)
+#define BFM_CLKCTRL_GPMI_RSRVD2_V(v)        BM_CLKCTRL_GPMI_RSRVD2
+#define BP_CLKCTRL_GPMI_BUSY                29
+#define BM_CLKCTRL_GPMI_BUSY                0x20000000
+#define BF_CLKCTRL_GPMI_BUSY(v)             (((v) & 0x1) << 29)
+#define BFM_CLKCTRL_GPMI_BUSY(v)            BM_CLKCTRL_GPMI_BUSY
+#define BF_CLKCTRL_GPMI_BUSY_V(e)           BF_CLKCTRL_GPMI_BUSY(BV_CLKCTRL_GPMI_BUSY__##e)
+#define BFM_CLKCTRL_GPMI_BUSY_V(v)          BM_CLKCTRL_GPMI_BUSY
+#define BP_CLKCTRL_GPMI_RSRVD1              11
+#define BM_CLKCTRL_GPMI_RSRVD1              0x1ffff800
+#define BF_CLKCTRL_GPMI_RSRVD1(v)           (((v) & 0x3ffff) << 11)
+#define BFM_CLKCTRL_GPMI_RSRVD1(v)          BM_CLKCTRL_GPMI_RSRVD1
+#define BF_CLKCTRL_GPMI_RSRVD1_V(e)         BF_CLKCTRL_GPMI_RSRVD1(BV_CLKCTRL_GPMI_RSRVD1__##e)
+#define BFM_CLKCTRL_GPMI_RSRVD1_V(v)        BM_CLKCTRL_GPMI_RSRVD1
+#define BP_CLKCTRL_GPMI_DIV_FRAC_EN         10
+#define BM_CLKCTRL_GPMI_DIV_FRAC_EN         0x400
+#define BF_CLKCTRL_GPMI_DIV_FRAC_EN(v)      (((v) & 0x1) << 10)
+#define BFM_CLKCTRL_GPMI_DIV_FRAC_EN(v)     BM_CLKCTRL_GPMI_DIV_FRAC_EN
+#define BF_CLKCTRL_GPMI_DIV_FRAC_EN_V(e)    BF_CLKCTRL_GPMI_DIV_FRAC_EN(BV_CLKCTRL_GPMI_DIV_FRAC_EN__##e)
+#define BFM_CLKCTRL_GPMI_DIV_FRAC_EN_V(v)   BM_CLKCTRL_GPMI_DIV_FRAC_EN
+#define BP_CLKCTRL_GPMI_DIV                 0
+#define BM_CLKCTRL_GPMI_DIV                 0x3ff
+#define BF_CLKCTRL_GPMI_DIV(v)              (((v) & 0x3ff) << 0)
+#define BFM_CLKCTRL_GPMI_DIV(v)             BM_CLKCTRL_GPMI_DIV
+#define BF_CLKCTRL_GPMI_DIV_V(e)            BF_CLKCTRL_GPMI_DIV(BV_CLKCTRL_GPMI_DIV__##e)
+#define BFM_CLKCTRL_GPMI_DIV_V(v)           BM_CLKCTRL_GPMI_DIV
+
+#define HW_CLKCTRL_SPDIF                HW(CLKCTRL_SPDIF)
+#define HWA_CLKCTRL_SPDIF               (0x80040000 + 0x90)
+#define HWT_CLKCTRL_SPDIF               HWIO_32_RW
+#define HWN_CLKCTRL_SPDIF               CLKCTRL_SPDIF
+#define HWI_CLKCTRL_SPDIF               
+#define BP_CLKCTRL_SPDIF_CLKGATE        31
+#define BM_CLKCTRL_SPDIF_CLKGATE        0x80000000
+#define BF_CLKCTRL_SPDIF_CLKGATE(v)     (((v) & 0x1) << 31)
+#define BFM_CLKCTRL_SPDIF_CLKGATE(v)    BM_CLKCTRL_SPDIF_CLKGATE
+#define BF_CLKCTRL_SPDIF_CLKGATE_V(e)   BF_CLKCTRL_SPDIF_CLKGATE(BV_CLKCTRL_SPDIF_CLKGATE__##e)
+#define BFM_CLKCTRL_SPDIF_CLKGATE_V(v)  BM_CLKCTRL_SPDIF_CLKGATE
+#define BP_CLKCTRL_SPDIF_RSRVD          0
+#define BM_CLKCTRL_SPDIF_RSRVD          0x7fffffff
+#define BF_CLKCTRL_SPDIF_RSRVD(v)       (((v) & 0x7fffffff) << 0)
+#define BFM_CLKCTRL_SPDIF_RSRVD(v)      BM_CLKCTRL_SPDIF_RSRVD
+#define BF_CLKCTRL_SPDIF_RSRVD_V(e)     BF_CLKCTRL_SPDIF_RSRVD(BV_CLKCTRL_SPDIF_RSRVD__##e)
+#define BFM_CLKCTRL_SPDIF_RSRVD_V(v)    BM_CLKCTRL_SPDIF_RSRVD
+
+#define HW_CLKCTRL_EMI                          HW(CLKCTRL_EMI)
+#define HWA_CLKCTRL_EMI                         (0x80040000 + 0xa0)
+#define HWT_CLKCTRL_EMI                         HWIO_32_RW
+#define HWN_CLKCTRL_EMI                         CLKCTRL_EMI
+#define HWI_CLKCTRL_EMI                         
+#define BP_CLKCTRL_EMI_CLKGATE                  31
+#define BM_CLKCTRL_EMI_CLKGATE                  0x80000000
+#define BF_CLKCTRL_EMI_CLKGATE(v)               (((v) & 0x1) << 31)
+#define BFM_CLKCTRL_EMI_CLKGATE(v)              BM_CLKCTRL_EMI_CLKGATE
+#define BF_CLKCTRL_EMI_CLKGATE_V(e)             BF_CLKCTRL_EMI_CLKGATE(BV_CLKCTRL_EMI_CLKGATE__##e)
+#define BFM_CLKCTRL_EMI_CLKGATE_V(v)            BM_CLKCTRL_EMI_CLKGATE
+#define BP_CLKCTRL_EMI_SYNC_MODE_EN             30
+#define BM_CLKCTRL_EMI_SYNC_MODE_EN             0x40000000
+#define BF_CLKCTRL_EMI_SYNC_MODE_EN(v)          (((v) & 0x1) << 30)
+#define BFM_CLKCTRL_EMI_SYNC_MODE_EN(v)         BM_CLKCTRL_EMI_SYNC_MODE_EN
+#define BF_CLKCTRL_EMI_SYNC_MODE_EN_V(e)        BF_CLKCTRL_EMI_SYNC_MODE_EN(BV_CLKCTRL_EMI_SYNC_MODE_EN__##e)
+#define BFM_CLKCTRL_EMI_SYNC_MODE_EN_V(v)       BM_CLKCTRL_EMI_SYNC_MODE_EN
+#define BP_CLKCTRL_EMI_BUSY_REF_XTAL            29
+#define BM_CLKCTRL_EMI_BUSY_REF_XTAL            0x20000000
+#define BF_CLKCTRL_EMI_BUSY_REF_XTAL(v)         (((v) & 0x1) << 29)
+#define BFM_CLKCTRL_EMI_BUSY_REF_XTAL(v)        BM_CLKCTRL_EMI_BUSY_REF_XTAL
+#define BF_CLKCTRL_EMI_BUSY_REF_XTAL_V(e)       BF_CLKCTRL_EMI_BUSY_REF_XTAL(BV_CLKCTRL_EMI_BUSY_REF_XTAL__##e)
+#define BFM_CLKCTRL_EMI_BUSY_REF_XTAL_V(v)      BM_CLKCTRL_EMI_BUSY_REF_XTAL
+#define BP_CLKCTRL_EMI_BUSY_REF_EMI             28
+#define BM_CLKCTRL_EMI_BUSY_REF_EMI             0x10000000
+#define BF_CLKCTRL_EMI_BUSY_REF_EMI(v)          (((v) & 0x1) << 28)
+#define BFM_CLKCTRL_EMI_BUSY_REF_EMI(v)         BM_CLKCTRL_EMI_BUSY_REF_EMI
+#define BF_CLKCTRL_EMI_BUSY_REF_EMI_V(e)        BF_CLKCTRL_EMI_BUSY_REF_EMI(BV_CLKCTRL_EMI_BUSY_REF_EMI__##e)
+#define BFM_CLKCTRL_EMI_BUSY_REF_EMI_V(v)       BM_CLKCTRL_EMI_BUSY_REF_EMI
+#define BP_CLKCTRL_EMI_BUSY_REF_CPU             27
+#define BM_CLKCTRL_EMI_BUSY_REF_CPU             0x8000000
+#define BF_CLKCTRL_EMI_BUSY_REF_CPU(v)          (((v) & 0x1) << 27)
+#define BFM_CLKCTRL_EMI_BUSY_REF_CPU(v)         BM_CLKCTRL_EMI_BUSY_REF_CPU
+#define BF_CLKCTRL_EMI_BUSY_REF_CPU_V(e)        BF_CLKCTRL_EMI_BUSY_REF_CPU(BV_CLKCTRL_EMI_BUSY_REF_CPU__##e)
+#define BFM_CLKCTRL_EMI_BUSY_REF_CPU_V(v)       BM_CLKCTRL_EMI_BUSY_REF_CPU
+#define BP_CLKCTRL_EMI_BUSY_SYNC_MODE           26
+#define BM_CLKCTRL_EMI_BUSY_SYNC_MODE           0x4000000
+#define BF_CLKCTRL_EMI_BUSY_SYNC_MODE(v)        (((v) & 0x1) << 26)
+#define BFM_CLKCTRL_EMI_BUSY_SYNC_MODE(v)       BM_CLKCTRL_EMI_BUSY_SYNC_MODE
+#define BF_CLKCTRL_EMI_BUSY_SYNC_MODE_V(e)      BF_CLKCTRL_EMI_BUSY_SYNC_MODE(BV_CLKCTRL_EMI_BUSY_SYNC_MODE__##e)
+#define BFM_CLKCTRL_EMI_BUSY_SYNC_MODE_V(v)     BM_CLKCTRL_EMI_BUSY_SYNC_MODE
+#define BP_CLKCTRL_EMI_RSRVD3                   18
+#define BM_CLKCTRL_EMI_RSRVD3                   0x3fc0000
+#define BF_CLKCTRL_EMI_RSRVD3(v)                (((v) & 0xff) << 18)
+#define BFM_CLKCTRL_EMI_RSRVD3(v)               BM_CLKCTRL_EMI_RSRVD3
+#define BF_CLKCTRL_EMI_RSRVD3_V(e)              BF_CLKCTRL_EMI_RSRVD3(BV_CLKCTRL_EMI_RSRVD3__##e)
+#define BFM_CLKCTRL_EMI_RSRVD3_V(v)             BM_CLKCTRL_EMI_RSRVD3
+#define BP_CLKCTRL_EMI_BUSY_DCC_RESYNC          17
+#define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC          0x20000
+#define BF_CLKCTRL_EMI_BUSY_DCC_RESYNC(v)       (((v) & 0x1) << 17)
+#define BFM_CLKCTRL_EMI_BUSY_DCC_RESYNC(v)      BM_CLKCTRL_EMI_BUSY_DCC_RESYNC
+#define BF_CLKCTRL_EMI_BUSY_DCC_RESYNC_V(e)     BF_CLKCTRL_EMI_BUSY_DCC_RESYNC(BV_CLKCTRL_EMI_BUSY_DCC_RESYNC__##e)
+#define BFM_CLKCTRL_EMI_BUSY_DCC_RESYNC_V(v)    BM_CLKCTRL_EMI_BUSY_DCC_RESYNC
+#define BP_CLKCTRL_EMI_DCC_RESYNC_ENABLE        16
+#define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE        0x10000
+#define BF_CLKCTRL_EMI_DCC_RESYNC_ENABLE(v)     (((v) & 0x1) << 16)
+#define BFM_CLKCTRL_EMI_DCC_RESYNC_ENABLE(v)    BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE
+#define BF_CLKCTRL_EMI_DCC_RESYNC_ENABLE_V(e)   BF_CLKCTRL_EMI_DCC_RESYNC_ENABLE(BV_CLKCTRL_EMI_DCC_RESYNC_ENABLE__##e)
+#define BFM_CLKCTRL_EMI_DCC_RESYNC_ENABLE_V(v)  BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE
+#define BP_CLKCTRL_EMI_RSRVD2                   12
+#define BM_CLKCTRL_EMI_RSRVD2                   0xf000
+#define BF_CLKCTRL_EMI_RSRVD2(v)                (((v) & 0xf) << 12)
+#define BFM_CLKCTRL_EMI_RSRVD2(v)               BM_CLKCTRL_EMI_RSRVD2
+#define BF_CLKCTRL_EMI_RSRVD2_V(e)              BF_CLKCTRL_EMI_RSRVD2(BV_CLKCTRL_EMI_RSRVD2__##e)
+#define BFM_CLKCTRL_EMI_RSRVD2_V(v)             BM_CLKCTRL_EMI_RSRVD2
+#define BP_CLKCTRL_EMI_DIV_XTAL                 8
+#define BM_CLKCTRL_EMI_DIV_XTAL                 0xf00
+#define BF_CLKCTRL_EMI_DIV_XTAL(v)              (((v) & 0xf) << 8)
+#define BFM_CLKCTRL_EMI_DIV_XTAL(v)             BM_CLKCTRL_EMI_DIV_XTAL
+#define BF_CLKCTRL_EMI_DIV_XTAL_V(e)            BF_CLKCTRL_EMI_DIV_XTAL(BV_CLKCTRL_EMI_DIV_XTAL__##e)
+#define BFM_CLKCTRL_EMI_DIV_XTAL_V(v)           BM_CLKCTRL_EMI_DIV_XTAL
+#define BP_CLKCTRL_EMI_RSRVD1                   6
+#define BM_CLKCTRL_EMI_RSRVD1                   0xc0
+#define BF_CLKCTRL_EMI_RSRVD1(v)                (((v) & 0x3) << 6)
+#define BFM_CLKCTRL_EMI_RSRVD1(v)               BM_CLKCTRL_EMI_RSRVD1
+#define BF_CLKCTRL_EMI_RSRVD1_V(e)              BF_CLKCTRL_EMI_RSRVD1(BV_CLKCTRL_EMI_RSRVD1__##e)
+#define BFM_CLKCTRL_EMI_RSRVD1_V(v)             BM_CLKCTRL_EMI_RSRVD1
+#define BP_CLKCTRL_EMI_DIV_EMI                  0
+#define BM_CLKCTRL_EMI_DIV_EMI                  0x3f
+#define BF_CLKCTRL_EMI_DIV_EMI(v)               (((v) & 0x3f) << 0)
+#define BFM_CLKCTRL_EMI_DIV_EMI(v)              BM_CLKCTRL_EMI_DIV_EMI
+#define BF_CLKCTRL_EMI_DIV_EMI_V(e)             BF_CLKCTRL_EMI_DIV_EMI(BV_CLKCTRL_EMI_DIV_EMI__##e)
+#define BFM_CLKCTRL_EMI_DIV_EMI_V(v)            BM_CLKCTRL_EMI_DIV_EMI
+
+#define HW_CLKCTRL_IR                   HW(CLKCTRL_IR)
+#define HWA_CLKCTRL_IR                  (0x80040000 + 0xb0)
+#define HWT_CLKCTRL_IR                  HWIO_32_RW
+#define HWN_CLKCTRL_IR                  CLKCTRL_IR
+#define HWI_CLKCTRL_IR                  
+#define BP_CLKCTRL_IR_CLKGATE           31
+#define BM_CLKCTRL_IR_CLKGATE           0x80000000
+#define BF_CLKCTRL_IR_CLKGATE(v)        (((v) & 0x1) << 31)
+#define BFM_CLKCTRL_IR_CLKGATE(v)       BM_CLKCTRL_IR_CLKGATE
+#define BF_CLKCTRL_IR_CLKGATE_V(e)      BF_CLKCTRL_IR_CLKGATE(BV_CLKCTRL_IR_CLKGATE__##e)
+#define BFM_CLKCTRL_IR_CLKGATE_V(v)     BM_CLKCTRL_IR_CLKGATE
+#define BP_CLKCTRL_IR_RSRVD3            30
+#define BM_CLKCTRL_IR_RSRVD3            0x40000000
+#define BF_CLKCTRL_IR_RSRVD3(v)         (((v) & 0x1) << 30)
+#define BFM_CLKCTRL_IR_RSRVD3(v)        BM_CLKCTRL_IR_RSRVD3
+#define BF_CLKCTRL_IR_RSRVD3_V(e)       BF_CLKCTRL_IR_RSRVD3(BV_CLKCTRL_IR_RSRVD3__##e)
+#define BFM_CLKCTRL_IR_RSRVD3_V(v)      BM_CLKCTRL_IR_RSRVD3
+#define BP_CLKCTRL_IR_AUTO_DIV          29
+#define BM_CLKCTRL_IR_AUTO_DIV          0x20000000
+#define BF_CLKCTRL_IR_AUTO_DIV(v)       (((v) & 0x1) << 29)
+#define BFM_CLKCTRL_IR_AUTO_DIV(v)      BM_CLKCTRL_IR_AUTO_DIV
+#define BF_CLKCTRL_IR_AUTO_DIV_V(e)     BF_CLKCTRL_IR_AUTO_DIV(BV_CLKCTRL_IR_AUTO_DIV__##e)
+#define BFM_CLKCTRL_IR_AUTO_DIV_V(v)    BM_CLKCTRL_IR_AUTO_DIV
+#define BP_CLKCTRL_IR_IR_BUSY           28
+#define BM_CLKCTRL_IR_IR_BUSY           0x10000000
+#define BF_CLKCTRL_IR_IR_BUSY(v)        (((v) & 0x1) << 28)
+#define BFM_CLKCTRL_IR_IR_BUSY(v)       BM_CLKCTRL_IR_IR_BUSY
+#define BF_CLKCTRL_IR_IR_BUSY_V(e)      BF_CLKCTRL_IR_IR_BUSY(BV_CLKCTRL_IR_IR_BUSY__##e)
+#define BFM_CLKCTRL_IR_IR_BUSY_V(v)     BM_CLKCTRL_IR_IR_BUSY
+#define BP_CLKCTRL_IR_IROV_BUSY         27
+#define BM_CLKCTRL_IR_IROV_BUSY         0x8000000
+#define BF_CLKCTRL_IR_IROV_BUSY(v)      (((v) & 0x1) << 27)
+#define BFM_CLKCTRL_IR_IROV_BUSY(v)     BM_CLKCTRL_IR_IROV_BUSY
+#define BF_CLKCTRL_IR_IROV_BUSY_V(e)    BF_CLKCTRL_IR_IROV_BUSY(BV_CLKCTRL_IR_IROV_BUSY__##e)
+#define BFM_CLKCTRL_IR_IROV_BUSY_V(v)   BM_CLKCTRL_IR_IROV_BUSY
+#define BP_CLKCTRL_IR_RSRVD2            25
+#define BM_CLKCTRL_IR_RSRVD2            0x6000000
+#define BF_CLKCTRL_IR_RSRVD2(v)         (((v) & 0x3) << 25)
+#define BFM_CLKCTRL_IR_RSRVD2(v)        BM_CLKCTRL_IR_RSRVD2
+#define BF_CLKCTRL_IR_RSRVD2_V(e)       BF_CLKCTRL_IR_RSRVD2(BV_CLKCTRL_IR_RSRVD2__##e)
+#define BFM_CLKCTRL_IR_RSRVD2_V(v)      BM_CLKCTRL_IR_RSRVD2
+#define BP_CLKCTRL_IR_IROV_DIV          16
+#define BM_CLKCTRL_IR_IROV_DIV          0x1ff0000
+#define BF_CLKCTRL_IR_IROV_DIV(v)       (((v) & 0x1ff) << 16)
+#define BFM_CLKCTRL_IR_IROV_DIV(v)      BM_CLKCTRL_IR_IROV_DIV
+#define BF_CLKCTRL_IR_IROV_DIV_V(e)     BF_CLKCTRL_IR_IROV_DIV(BV_CLKCTRL_IR_IROV_DIV__##e)
+#define BFM_CLKCTRL_IR_IROV_DIV_V(v)    BM_CLKCTRL_IR_IROV_DIV
+#define BP_CLKCTRL_IR_RSRVD1            10
+#define BM_CLKCTRL_IR_RSRVD1            0xfc00
+#define BF_CLKCTRL_IR_RSRVD1(v)         (((v) & 0x3f) << 10)
+#define BFM_CLKCTRL_IR_RSRVD1(v)        BM_CLKCTRL_IR_RSRVD1
+#define BF_CLKCTRL_IR_RSRVD1_V(e)       BF_CLKCTRL_IR_RSRVD1(BV_CLKCTRL_IR_RSRVD1__##e)
+#define BFM_CLKCTRL_IR_RSRVD1_V(v)      BM_CLKCTRL_IR_RSRVD1
+#define BP_CLKCTRL_IR_IR_DIV            0
+#define BM_CLKCTRL_IR_IR_DIV            0x3ff
+#define BF_CLKCTRL_IR_IR_DIV(v)         (((v) & 0x3ff) << 0)
+#define BFM_CLKCTRL_IR_IR_DIV(v)        BM_CLKCTRL_IR_IR_DIV
+#define BF_CLKCTRL_IR_IR_DIV_V(e)       BF_CLKCTRL_IR_IR_DIV(BV_CLKCTRL_IR_IR_DIV__##e)
+#define BFM_CLKCTRL_IR_IR_DIV_V(v)      BM_CLKCTRL_IR_IR_DIV
+
+#define HW_CLKCTRL_SAIF                     HW(CLKCTRL_SAIF)
+#define HWA_CLKCTRL_SAIF                    (0x80040000 + 0xc0)
+#define HWT_CLKCTRL_SAIF                    HWIO_32_RW
+#define HWN_CLKCTRL_SAIF                    CLKCTRL_SAIF
+#define HWI_CLKCTRL_SAIF                    
+#define BP_CLKCTRL_SAIF_CLKGATE             31
+#define BM_CLKCTRL_SAIF_CLKGATE             0x80000000
+#define BF_CLKCTRL_SAIF_CLKGATE(v)          (((v) & 0x1) << 31)
+#define BFM_CLKCTRL_SAIF_CLKGATE(v)         BM_CLKCTRL_SAIF_CLKGATE
+#define BF_CLKCTRL_SAIF_CLKGATE_V(e)        BF_CLKCTRL_SAIF_CLKGATE(BV_CLKCTRL_SAIF_CLKGATE__##e)
+#define BFM_CLKCTRL_SAIF_CLKGATE_V(v)       BM_CLKCTRL_SAIF_CLKGATE
+#define BP_CLKCTRL_SAIF_RSRVD2              30
+#define BM_CLKCTRL_SAIF_RSRVD2              0x40000000
+#define BF_CLKCTRL_SAIF_RSRVD2(v)           (((v) & 0x1) << 30)
+#define BFM_CLKCTRL_SAIF_RSRVD2(v)          BM_CLKCTRL_SAIF_RSRVD2
+#define BF_CLKCTRL_SAIF_RSRVD2_V(e)         BF_CLKCTRL_SAIF_RSRVD2(BV_CLKCTRL_SAIF_RSRVD2__##e)
+#define BFM_CLKCTRL_SAIF_RSRVD2_V(v)        BM_CLKCTRL_SAIF_RSRVD2
+#define BP_CLKCTRL_SAIF_BUSY                29
+#define BM_CLKCTRL_SAIF_BUSY                0x20000000
+#define BF_CLKCTRL_SAIF_BUSY(v)             (((v) & 0x1) << 29)
+#define BFM_CLKCTRL_SAIF_BUSY(v)            BM_CLKCTRL_SAIF_BUSY
+#define BF_CLKCTRL_SAIF_BUSY_V(e)           BF_CLKCTRL_SAIF_BUSY(BV_CLKCTRL_SAIF_BUSY__##e)
+#define BFM_CLKCTRL_SAIF_BUSY_V(v)          BM_CLKCTRL_SAIF_BUSY
+#define BP_CLKCTRL_SAIF_RSRVD1              17
+#define BM_CLKCTRL_SAIF_RSRVD1              0x1ffe0000
+#define BF_CLKCTRL_SAIF_RSRVD1(v)           (((v) & 0xfff) << 17)
+#define BFM_CLKCTRL_SAIF_RSRVD1(v)          BM_CLKCTRL_SAIF_RSRVD1
+#define BF_CLKCTRL_SAIF_RSRVD1_V(e)         BF_CLKCTRL_SAIF_RSRVD1(BV_CLKCTRL_SAIF_RSRVD1__##e)
+#define BFM_CLKCTRL_SAIF_RSRVD1_V(v)        BM_CLKCTRL_SAIF_RSRVD1
+#define BP_CLKCTRL_SAIF_DIV_FRAC_EN         16
+#define BM_CLKCTRL_SAIF_DIV_FRAC_EN         0x10000
+#define BF_CLKCTRL_SAIF_DIV_FRAC_EN(v)      (((v) & 0x1) << 16)
+#define BFM_CLKCTRL_SAIF_DIV_FRAC_EN(v)     BM_CLKCTRL_SAIF_DIV_FRAC_EN
+#define BF_CLKCTRL_SAIF_DIV_FRAC_EN_V(e)    BF_CLKCTRL_SAIF_DIV_FRAC_EN(BV_CLKCTRL_SAIF_DIV_FRAC_EN__##e)
+#define BFM_CLKCTRL_SAIF_DIV_FRAC_EN_V(v)   BM_CLKCTRL_SAIF_DIV_FRAC_EN
+#define BP_CLKCTRL_SAIF_DIV                 0
+#define BM_CLKCTRL_SAIF_DIV                 0xffff
+#define BF_CLKCTRL_SAIF_DIV(v)              (((v) & 0xffff) << 0)
+#define BFM_CLKCTRL_SAIF_DIV(v)             BM_CLKCTRL_SAIF_DIV
+#define BF_CLKCTRL_SAIF_DIV_V(e)            BF_CLKCTRL_SAIF_DIV(BV_CLKCTRL_SAIF_DIV__##e)
+#define BFM_CLKCTRL_SAIF_DIV_V(v)           BM_CLKCTRL_SAIF_DIV
+
+#define HW_CLKCTRL_TV                       HW(CLKCTRL_TV)
+#define HWA_CLKCTRL_TV                      (0x80040000 + 0xd0)
+#define HWT_CLKCTRL_TV                      HWIO_32_RW
+#define HWN_CLKCTRL_TV                      CLKCTRL_TV
+#define HWI_CLKCTRL_TV                      
+#define BP_CLKCTRL_TV_CLK_TV108M_GATE       31
+#define BM_CLKCTRL_TV_CLK_TV108M_GATE       0x80000000
+#define BF_CLKCTRL_TV_CLK_TV108M_GATE(v)    (((v) & 0x1) << 31)
+#define BFM_CLKCTRL_TV_CLK_TV108M_GATE(v)   BM_CLKCTRL_TV_CLK_TV108M_GATE
+#define BF_CLKCTRL_TV_CLK_TV108M_GATE_V(e)  BF_CLKCTRL_TV_CLK_TV108M_GATE(BV_CLKCTRL_TV_CLK_TV108M_GATE__##e)
+#define BFM_CLKCTRL_TV_CLK_TV108M_GATE_V(v) BM_CLKCTRL_TV_CLK_TV108M_GATE
+#define BP_CLKCTRL_TV_CLK_TV_GATE           30
+#define BM_CLKCTRL_TV_CLK_TV_GATE           0x40000000
+#define BF_CLKCTRL_TV_CLK_TV_GATE(v)        (((v) & 0x1) << 30)
+#define BFM_CLKCTRL_TV_CLK_TV_GATE(v)       BM_CLKCTRL_TV_CLK_TV_GATE
+#define BF_CLKCTRL_TV_CLK_TV_GATE_V(e)      BF_CLKCTRL_TV_CLK_TV_GATE(BV_CLKCTRL_TV_CLK_TV_GATE__##e)
+#define BFM_CLKCTRL_TV_CLK_TV_GATE_V(v)     BM_CLKCTRL_TV_CLK_TV_GATE
+#define BP_CLKCTRL_TV_RSRVD                 0
+#define BM_CLKCTRL_TV_RSRVD                 0x3fffffff
+#define BF_CLKCTRL_TV_RSRVD(v)              (((v) & 0x3fffffff) << 0)
+#define BFM_CLKCTRL_TV_RSRVD(v)             BM_CLKCTRL_TV_RSRVD
+#define BF_CLKCTRL_TV_RSRVD_V(e)            BF_CLKCTRL_TV_RSRVD(BV_CLKCTRL_TV_RSRVD__##e)
+#define BFM_CLKCTRL_TV_RSRVD_V(v)           BM_CLKCTRL_TV_RSRVD
+
+#define HW_CLKCTRL_ETM                      HW(CLKCTRL_ETM)
+#define HWA_CLKCTRL_ETM                     (0x80040000 + 0xe0)
+#define HWT_CLKCTRL_ETM                     HWIO_32_RW
+#define HWN_CLKCTRL_ETM                     CLKCTRL_ETM
+#define HWI_CLKCTRL_ETM                     
+#define BP_CLKCTRL_ETM_CLKGATE              31
+#define BM_CLKCTRL_ETM_CLKGATE              0x80000000
+#define BF_CLKCTRL_ETM_CLKGATE(v)           (((v) & 0x1) << 31)
+#define BFM_CLKCTRL_ETM_CLKGATE(v)          BM_CLKCTRL_ETM_CLKGATE
+#define BF_CLKCTRL_ETM_CLKGATE_V(e)         BF_CLKCTRL_ETM_CLKGATE(BV_CLKCTRL_ETM_CLKGATE__##e)
+#define BFM_CLKCTRL_ETM_CLKGATE_V(v)        BM_CLKCTRL_ETM_CLKGATE
+#define BP_CLKCTRL_ETM_RSRVD2               30
+#define BM_CLKCTRL_ETM_RSRVD2               0x40000000
+#define BF_CLKCTRL_ETM_RSRVD2(v)            (((v) & 0x1) << 30)
+#define BFM_CLKCTRL_ETM_RSRVD2(v)           BM_CLKCTRL_ETM_RSRVD2
+#define BF_CLKCTRL_ETM_RSRVD2_V(e)          BF_CLKCTRL_ETM_RSRVD2(BV_CLKCTRL_ETM_RSRVD2__##e)
+#define BFM_CLKCTRL_ETM_RSRVD2_V(v)         BM_CLKCTRL_ETM_RSRVD2
+#define BP_CLKCTRL_ETM_BUSY                 29
+#define BM_CLKCTRL_ETM_BUSY                 0x20000000
+#define BF_CLKCTRL_ETM_BUSY(v)              (((v) & 0x1) << 29)
+#define BFM_CLKCTRL_ETM_BUSY(v)             BM_CLKCTRL_ETM_BUSY
+#define BF_CLKCTRL_ETM_BUSY_V(e)            BF_CLKCTRL_ETM_BUSY(BV_CLKCTRL_ETM_BUSY__##e)
+#define BFM_CLKCTRL_ETM_BUSY_V(v)           BM_CLKCTRL_ETM_BUSY
+#define BP_CLKCTRL_ETM_RSRVD1               7
+#define BM_CLKCTRL_ETM_RSRVD1               0x1fffff80
+#define BF_CLKCTRL_ETM_RSRVD1(v)            (((v) & 0x3fffff) << 7)
+#define BFM_CLKCTRL_ETM_RSRVD1(v)           BM_CLKCTRL_ETM_RSRVD1
+#define BF_CLKCTRL_ETM_RSRVD1_V(e)          BF_CLKCTRL_ETM_RSRVD1(BV_CLKCTRL_ETM_RSRVD1__##e)
+#define BFM_CLKCTRL_ETM_RSRVD1_V(v)         BM_CLKCTRL_ETM_RSRVD1
+#define BP_CLKCTRL_ETM_DIV_FRAC_EN          6
+#define BM_CLKCTRL_ETM_DIV_FRAC_EN          0x40
+#define BF_CLKCTRL_ETM_DIV_FRAC_EN(v)       (((v) & 0x1) << 6)
+#define BFM_CLKCTRL_ETM_DIV_FRAC_EN(v)      BM_CLKCTRL_ETM_DIV_FRAC_EN
+#define BF_CLKCTRL_ETM_DIV_FRAC_EN_V(e)     BF_CLKCTRL_ETM_DIV_FRAC_EN(BV_CLKCTRL_ETM_DIV_FRAC_EN__##e)
+#define BFM_CLKCTRL_ETM_DIV_FRAC_EN_V(v)    BM_CLKCTRL_ETM_DIV_FRAC_EN
+#define BP_CLKCTRL_ETM_DIV                  0
+#define BM_CLKCTRL_ETM_DIV                  0x3f
+#define BF_CLKCTRL_ETM_DIV(v)               (((v) & 0x3f) << 0)
+#define BFM_CLKCTRL_ETM_DIV(v)              BM_CLKCTRL_ETM_DIV
+#define BF_CLKCTRL_ETM_DIV_V(e)             BF_CLKCTRL_ETM_DIV(BV_CLKCTRL_ETM_DIV__##e)
+#define BFM_CLKCTRL_ETM_DIV_V(v)            BM_CLKCTRL_ETM_DIV
+
+#define HW_CLKCTRL_FRAC                     HW(CLKCTRL_FRAC)
+#define HWA_CLKCTRL_FRAC                    (0x80040000 + 0xf0)
+#define HWT_CLKCTRL_FRAC                    HWIO_32_RW
+#define HWN_CLKCTRL_FRAC                    CLKCTRL_FRAC
+#define HWI_CLKCTRL_FRAC                    
+#define HW_CLKCTRL_FRAC_SET                 HW(CLKCTRL_FRAC_SET)
+#define HWA_CLKCTRL_FRAC_SET                (HWA_CLKCTRL_FRAC + 0x4)
+#define HWT_CLKCTRL_FRAC_SET                HWIO_32_WO
+#define HWN_CLKCTRL_FRAC_SET                CLKCTRL_FRAC
+#define HWI_CLKCTRL_FRAC_SET                
+#define HW_CLKCTRL_FRAC_CLR                 HW(CLKCTRL_FRAC_CLR)
+#define HWA_CLKCTRL_FRAC_CLR                (HWA_CLKCTRL_FRAC + 0x8)
+#define HWT_CLKCTRL_FRAC_CLR                HWIO_32_WO
+#define HWN_CLKCTRL_FRAC_CLR                CLKCTRL_FRAC
+#define HWI_CLKCTRL_FRAC_CLR                
+#define HW_CLKCTRL_FRAC_TOG                 HW(CLKCTRL_FRAC_TOG)
+#define HWA_CLKCTRL_FRAC_TOG                (HWA_CLKCTRL_FRAC + 0xc)
+#define HWT_CLKCTRL_FRAC_TOG                HWIO_32_WO
+#define HWN_CLKCTRL_FRAC_TOG                CLKCTRL_FRAC
+#define HWI_CLKCTRL_FRAC_TOG                
+#define BP_CLKCTRL_FRAC_CLKGATEIO           31
+#define BM_CLKCTRL_FRAC_CLKGATEIO           0x80000000
+#define BF_CLKCTRL_FRAC_CLKGATEIO(v)        (((v) & 0x1) << 31)
+#define BFM_CLKCTRL_FRAC_CLKGATEIO(v)       BM_CLKCTRL_FRAC_CLKGATEIO
+#define BF_CLKCTRL_FRAC_CLKGATEIO_V(e)      BF_CLKCTRL_FRAC_CLKGATEIO(BV_CLKCTRL_FRAC_CLKGATEIO__##e)
+#define BFM_CLKCTRL_FRAC_CLKGATEIO_V(v)     BM_CLKCTRL_FRAC_CLKGATEIO
+#define BP_CLKCTRL_FRAC_IO_STABLE           30
+#define BM_CLKCTRL_FRAC_IO_STABLE           0x40000000
+#define BF_CLKCTRL_FRAC_IO_STABLE(v)        (((v) & 0x1) << 30)
+#define BFM_CLKCTRL_FRAC_IO_STABLE(v)       BM_CLKCTRL_FRAC_IO_STABLE
+#define BF_CLKCTRL_FRAC_IO_STABLE_V(e)      BF_CLKCTRL_FRAC_IO_STABLE(BV_CLKCTRL_FRAC_IO_STABLE__##e)
+#define BFM_CLKCTRL_FRAC_IO_STABLE_V(v)     BM_CLKCTRL_FRAC_IO_STABLE
+#define BP_CLKCTRL_FRAC_IOFRAC              24
+#define BM_CLKCTRL_FRAC_IOFRAC              0x3f000000
+#define BF_CLKCTRL_FRAC_IOFRAC(v)           (((v) & 0x3f) << 24)
+#define BFM_CLKCTRL_FRAC_IOFRAC(v)          BM_CLKCTRL_FRAC_IOFRAC
+#define BF_CLKCTRL_FRAC_IOFRAC_V(e)         BF_CLKCTRL_FRAC_IOFRAC(BV_CLKCTRL_FRAC_IOFRAC__##e)
+#define BFM_CLKCTRL_FRAC_IOFRAC_V(v)        BM_CLKCTRL_FRAC_IOFRAC
+#define BP_CLKCTRL_FRAC_CLKGATEPIX          23
+#define BM_CLKCTRL_FRAC_CLKGATEPIX          0x800000
+#define BF_CLKCTRL_FRAC_CLKGATEPIX(v)       (((v) & 0x1) << 23)
+#define BFM_CLKCTRL_FRAC_CLKGATEPIX(v)      BM_CLKCTRL_FRAC_CLKGATEPIX
+#define BF_CLKCTRL_FRAC_CLKGATEPIX_V(e)     BF_CLKCTRL_FRAC_CLKGATEPIX(BV_CLKCTRL_FRAC_CLKGATEPIX__##e)
+#define BFM_CLKCTRL_FRAC_CLKGATEPIX_V(v)    BM_CLKCTRL_FRAC_CLKGATEPIX
+#define BP_CLKCTRL_FRAC_PIX_STABLE          22
+#define BM_CLKCTRL_FRAC_PIX_STABLE          0x400000
+#define BF_CLKCTRL_FRAC_PIX_STABLE(v)       (((v) & 0x1) << 22)
+#define BFM_CLKCTRL_FRAC_PIX_STABLE(v)      BM_CLKCTRL_FRAC_PIX_STABLE
+#define BF_CLKCTRL_FRAC_PIX_STABLE_V(e)     BF_CLKCTRL_FRAC_PIX_STABLE(BV_CLKCTRL_FRAC_PIX_STABLE__##e)
+#define BFM_CLKCTRL_FRAC_PIX_STABLE_V(v)    BM_CLKCTRL_FRAC_PIX_STABLE
+#define BP_CLKCTRL_FRAC_PIXFRAC             16
+#define BM_CLKCTRL_FRAC_PIXFRAC             0x3f0000
+#define BF_CLKCTRL_FRAC_PIXFRAC(v)          (((v) & 0x3f) << 16)
+#define BFM_CLKCTRL_FRAC_PIXFRAC(v)         BM_CLKCTRL_FRAC_PIXFRAC
+#define BF_CLKCTRL_FRAC_PIXFRAC_V(e)        BF_CLKCTRL_FRAC_PIXFRAC(BV_CLKCTRL_FRAC_PIXFRAC__##e)
+#define BFM_CLKCTRL_FRAC_PIXFRAC_V(v)       BM_CLKCTRL_FRAC_PIXFRAC
+#define BP_CLKCTRL_FRAC_CLKGATEEMI          15
+#define BM_CLKCTRL_FRAC_CLKGATEEMI          0x8000
+#define BF_CLKCTRL_FRAC_CLKGATEEMI(v)       (((v) & 0x1) << 15)
+#define BFM_CLKCTRL_FRAC_CLKGATEEMI(v)      BM_CLKCTRL_FRAC_CLKGATEEMI
+#define BF_CLKCTRL_FRAC_CLKGATEEMI_V(e)     BF_CLKCTRL_FRAC_CLKGATEEMI(BV_CLKCTRL_FRAC_CLKGATEEMI__##e)
+#define BFM_CLKCTRL_FRAC_CLKGATEEMI_V(v)    BM_CLKCTRL_FRAC_CLKGATEEMI
+#define BP_CLKCTRL_FRAC_EMI_STABLE          14
+#define BM_CLKCTRL_FRAC_EMI_STABLE          0x4000
+#define BF_CLKCTRL_FRAC_EMI_STABLE(v)       (((v) & 0x1) << 14)
+#define BFM_CLKCTRL_FRAC_EMI_STABLE(v)      BM_CLKCTRL_FRAC_EMI_STABLE
+#define BF_CLKCTRL_FRAC_EMI_STABLE_V(e)     BF_CLKCTRL_FRAC_EMI_STABLE(BV_CLKCTRL_FRAC_EMI_STABLE__##e)
+#define BFM_CLKCTRL_FRAC_EMI_STABLE_V(v)    BM_CLKCTRL_FRAC_EMI_STABLE
+#define BP_CLKCTRL_FRAC_EMIFRAC             8
+#define BM_CLKCTRL_FRAC_EMIFRAC             0x3f00
+#define BF_CLKCTRL_FRAC_EMIFRAC(v)          (((v) & 0x3f) << 8)
+#define BFM_CLKCTRL_FRAC_EMIFRAC(v)         BM_CLKCTRL_FRAC_EMIFRAC
+#define BF_CLKCTRL_FRAC_EMIFRAC_V(e)        BF_CLKCTRL_FRAC_EMIFRAC(BV_CLKCTRL_FRAC_EMIFRAC__##e)
+#define BFM_CLKCTRL_FRAC_EMIFRAC_V(v)       BM_CLKCTRL_FRAC_EMIFRAC
+#define BP_CLKCTRL_FRAC_CLKGATECPU          7
+#define BM_CLKCTRL_FRAC_CLKGATECPU          0x80
+#define BF_CLKCTRL_FRAC_CLKGATECPU(v)       (((v) & 0x1) << 7)
+#define BFM_CLKCTRL_FRAC_CLKGATECPU(v)      BM_CLKCTRL_FRAC_CLKGATECPU
+#define BF_CLKCTRL_FRAC_CLKGATECPU_V(e)     BF_CLKCTRL_FRAC_CLKGATECPU(BV_CLKCTRL_FRAC_CLKGATECPU__##e)
+#define BFM_CLKCTRL_FRAC_CLKGATECPU_V(v)    BM_CLKCTRL_FRAC_CLKGATECPU
+#define BP_CLKCTRL_FRAC_CPU_STABLE          6
+#define BM_CLKCTRL_FRAC_CPU_STABLE          0x40
+#define BF_CLKCTRL_FRAC_CPU_STABLE(v)       (((v) & 0x1) << 6)
+#define BFM_CLKCTRL_FRAC_CPU_STABLE(v)      BM_CLKCTRL_FRAC_CPU_STABLE
+#define BF_CLKCTRL_FRAC_CPU_STABLE_V(e)     BF_CLKCTRL_FRAC_CPU_STABLE(BV_CLKCTRL_FRAC_CPU_STABLE__##e)
+#define BFM_CLKCTRL_FRAC_CPU_STABLE_V(v)    BM_CLKCTRL_FRAC_CPU_STABLE
+#define BP_CLKCTRL_FRAC_CPUFRAC             0
+#define BM_CLKCTRL_FRAC_CPUFRAC             0x3f
+#define BF_CLKCTRL_FRAC_CPUFRAC(v)          (((v) & 0x3f) << 0)
+#define BFM_CLKCTRL_FRAC_CPUFRAC(v)         BM_CLKCTRL_FRAC_CPUFRAC
+#define BF_CLKCTRL_FRAC_CPUFRAC_V(e)        BF_CLKCTRL_FRAC_CPUFRAC(BV_CLKCTRL_FRAC_CPUFRAC__##e)
+#define BFM_CLKCTRL_FRAC_CPUFRAC_V(v)       BM_CLKCTRL_FRAC_CPUFRAC
+
+#define HW_CLKCTRL_FRAC1                    HW(CLKCTRL_FRAC1)
+#define HWA_CLKCTRL_FRAC1                   (0x80040000 + 0x100)
+#define HWT_CLKCTRL_FRAC1                   HWIO_32_RW
+#define HWN_CLKCTRL_FRAC1                   CLKCTRL_FRAC1
+#define HWI_CLKCTRL_FRAC1                   
+#define HW_CLKCTRL_FRAC1_SET                HW(CLKCTRL_FRAC1_SET)
+#define HWA_CLKCTRL_FRAC1_SET               (HWA_CLKCTRL_FRAC1 + 0x4)
+#define HWT_CLKCTRL_FRAC1_SET               HWIO_32_WO
+#define HWN_CLKCTRL_FRAC1_SET               CLKCTRL_FRAC1
+#define HWI_CLKCTRL_FRAC1_SET               
+#define HW_CLKCTRL_FRAC1_CLR                HW(CLKCTRL_FRAC1_CLR)
+#define HWA_CLKCTRL_FRAC1_CLR               (HWA_CLKCTRL_FRAC1 + 0x8)
+#define HWT_CLKCTRL_FRAC1_CLR               HWIO_32_WO
+#define HWN_CLKCTRL_FRAC1_CLR               CLKCTRL_FRAC1
+#define HWI_CLKCTRL_FRAC1_CLR               
+#define HW_CLKCTRL_FRAC1_TOG                HW(CLKCTRL_FRAC1_TOG)
+#define HWA_CLKCTRL_FRAC1_TOG               (HWA_CLKCTRL_FRAC1 + 0xc)
+#define HWT_CLKCTRL_FRAC1_TOG               HWIO_32_WO
+#define HWN_CLKCTRL_FRAC1_TOG               CLKCTRL_FRAC1
+#define HWI_CLKCTRL_FRAC1_TOG               
+#define BP_CLKCTRL_FRAC1_CLKGATEVID         31
+#define BM_CLKCTRL_FRAC1_CLKGATEVID         0x80000000
+#define BF_CLKCTRL_FRAC1_CLKGATEVID(v)      (((v) & 0x1) << 31)
+#define BFM_CLKCTRL_FRAC1_CLKGATEVID(v)     BM_CLKCTRL_FRAC1_CLKGATEVID
+#define BF_CLKCTRL_FRAC1_CLKGATEVID_V(e)    BF_CLKCTRL_FRAC1_CLKGATEVID(BV_CLKCTRL_FRAC1_CLKGATEVID__##e)
+#define BFM_CLKCTRL_FRAC1_CLKGATEVID_V(v)   BM_CLKCTRL_FRAC1_CLKGATEVID
+#define BP_CLKCTRL_FRAC1_VID_STABLE         30
+#define BM_CLKCTRL_FRAC1_VID_STABLE         0x40000000
+#define BF_CLKCTRL_FRAC1_VID_STABLE(v)      (((v) & 0x1) << 30)
+#define BFM_CLKCTRL_FRAC1_VID_STABLE(v)     BM_CLKCTRL_FRAC1_VID_STABLE
+#define BF_CLKCTRL_FRAC1_VID_STABLE_V(e)    BF_CLKCTRL_FRAC1_VID_STABLE(BV_CLKCTRL_FRAC1_VID_STABLE__##e)
+#define BFM_CLKCTRL_FRAC1_VID_STABLE_V(v)   BM_CLKCTRL_FRAC1_VID_STABLE
+#define BP_CLKCTRL_FRAC1_RSRVD1             0
+#define BM_CLKCTRL_FRAC1_RSRVD1             0x3fffffff
+#define BF_CLKCTRL_FRAC1_RSRVD1(v)          (((v) & 0x3fffffff) << 0)
+#define BFM_CLKCTRL_FRAC1_RSRVD1(v)         BM_CLKCTRL_FRAC1_RSRVD1
+#define BF_CLKCTRL_FRAC1_RSRVD1_V(e)        BF_CLKCTRL_FRAC1_RSRVD1(BV_CLKCTRL_FRAC1_RSRVD1__##e)
+#define BFM_CLKCTRL_FRAC1_RSRVD1_V(v)       BM_CLKCTRL_FRAC1_RSRVD1
+
+#define HW_CLKCTRL_CLKSEQ                   HW(CLKCTRL_CLKSEQ)
+#define HWA_CLKCTRL_CLKSEQ                  (0x80040000 + 0x110)
+#define HWT_CLKCTRL_CLKSEQ                  HWIO_32_RW
+#define HWN_CLKCTRL_CLKSEQ                  CLKCTRL_CLKSEQ
+#define HWI_CLKCTRL_CLKSEQ                  
+#define HW_CLKCTRL_CLKSEQ_SET               HW(CLKCTRL_CLKSEQ_SET)
+#define HWA_CLKCTRL_CLKSEQ_SET              (HWA_CLKCTRL_CLKSEQ + 0x4)
+#define HWT_CLKCTRL_CLKSEQ_SET              HWIO_32_WO
+#define HWN_CLKCTRL_CLKSEQ_SET              CLKCTRL_CLKSEQ
+#define HWI_CLKCTRL_CLKSEQ_SET              
+#define HW_CLKCTRL_CLKSEQ_CLR               HW(CLKCTRL_CLKSEQ_CLR)
+#define HWA_CLKCTRL_CLKSEQ_CLR              (HWA_CLKCTRL_CLKSEQ + 0x8)
+#define HWT_CLKCTRL_CLKSEQ_CLR              HWIO_32_WO
+#define HWN_CLKCTRL_CLKSEQ_CLR              CLKCTRL_CLKSEQ
+#define HWI_CLKCTRL_CLKSEQ_CLR              
+#define HW_CLKCTRL_CLKSEQ_TOG               HW(CLKCTRL_CLKSEQ_TOG)
+#define HWA_CLKCTRL_CLKSEQ_TOG              (HWA_CLKCTRL_CLKSEQ + 0xc)
+#define HWT_CLKCTRL_CLKSEQ_TOG              HWIO_32_WO
+#define HWN_CLKCTRL_CLKSEQ_TOG              CLKCTRL_CLKSEQ
+#define HWI_CLKCTRL_CLKSEQ_TOG              
+#define BP_CLKCTRL_CLKSEQ_RSRVD1            9
+#define BM_CLKCTRL_CLKSEQ_RSRVD1            0xfffffe00
+#define BF_CLKCTRL_CLKSEQ_RSRVD1(v)         (((v) & 0x7fffff) << 9)
+#define BFM_CLKCTRL_CLKSEQ_RSRVD1(v)        BM_CLKCTRL_CLKSEQ_RSRVD1
+#define BF_CLKCTRL_CLKSEQ_RSRVD1_V(e)       BF_CLKCTRL_CLKSEQ_RSRVD1(BV_CLKCTRL_CLKSEQ_RSRVD1__##e)
+#define BFM_CLKCTRL_CLKSEQ_RSRVD1_V(v)      BM_CLKCTRL_CLKSEQ_RSRVD1
+#define BP_CLKCTRL_CLKSEQ_BYPASS_ETM        8
+#define BM_CLKCTRL_CLKSEQ_BYPASS_ETM        0x100
+#define BF_CLKCTRL_CLKSEQ_BYPASS_ETM(v)     (((v) & 0x1) << 8)
+#define BFM_CLKCTRL_CLKSEQ_BYPASS_ETM(v)    BM_CLKCTRL_CLKSEQ_BYPASS_ETM
+#define BF_CLKCTRL_CLKSEQ_BYPASS_ETM_V(e)   BF_CLKCTRL_CLKSEQ_BYPASS_ETM(BV_CLKCTRL_CLKSEQ_BYPASS_ETM__##e)
+#define BFM_CLKCTRL_CLKSEQ_BYPASS_ETM_V(v)  BM_CLKCTRL_CLKSEQ_BYPASS_ETM
+#define BP_CLKCTRL_CLKSEQ_BYPASS_CPU        7
+#define BM_CLKCTRL_CLKSEQ_BYPASS_CPU        0x80
+#define BF_CLKCTRL_CLKSEQ_BYPASS_CPU(v)     (((v) & 0x1) << 7)
+#define BFM_CLKCTRL_CLKSEQ_BYPASS_CPU(v)    BM_CLKCTRL_CLKSEQ_BYPASS_CPU
+#define BF_CLKCTRL_CLKSEQ_BYPASS_CPU_V(e)   BF_CLKCTRL_CLKSEQ_BYPASS_CPU(BV_CLKCTRL_CLKSEQ_BYPASS_CPU__##e)
+#define BFM_CLKCTRL_CLKSEQ_BYPASS_CPU_V(v)  BM_CLKCTRL_CLKSEQ_BYPASS_CPU
+#define BP_CLKCTRL_CLKSEQ_BYPASS_EMI        6
+#define BM_CLKCTRL_CLKSEQ_BYPASS_EMI        0x40
+#define BF_CLKCTRL_CLKSEQ_BYPASS_EMI(v)     (((v) & 0x1) << 6)
+#define BFM_CLKCTRL_CLKSEQ_BYPASS_EMI(v)    BM_CLKCTRL_CLKSEQ_BYPASS_EMI
+#define BF_CLKCTRL_CLKSEQ_BYPASS_EMI_V(e)   BF_CLKCTRL_CLKSEQ_BYPASS_EMI(BV_CLKCTRL_CLKSEQ_BYPASS_EMI__##e)
+#define BFM_CLKCTRL_CLKSEQ_BYPASS_EMI_V(v)  BM_CLKCTRL_CLKSEQ_BYPASS_EMI
+#define BP_CLKCTRL_CLKSEQ_BYPASS_SSP        5
+#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP        0x20
+#define BF_CLKCTRL_CLKSEQ_BYPASS_SSP(v)     (((v) & 0x1) << 5)
+#define BFM_CLKCTRL_CLKSEQ_BYPASS_SSP(v)    BM_CLKCTRL_CLKSEQ_BYPASS_SSP
+#define BF_CLKCTRL_CLKSEQ_BYPASS_SSP_V(e)   BF_CLKCTRL_CLKSEQ_BYPASS_SSP(BV_CLKCTRL_CLKSEQ_BYPASS_SSP__##e)
+#define BFM_CLKCTRL_CLKSEQ_BYPASS_SSP_V(v)  BM_CLKCTRL_CLKSEQ_BYPASS_SSP
+#define BP_CLKCTRL_CLKSEQ_BYPASS_GPMI       4
+#define BM_CLKCTRL_CLKSEQ_BYPASS_GPMI       0x10
+#define BF_CLKCTRL_CLKSEQ_BYPASS_GPMI(v)    (((v) & 0x1) << 4)
+#define BFM_CLKCTRL_CLKSEQ_BYPASS_GPMI(v)   BM_CLKCTRL_CLKSEQ_BYPASS_GPMI
+#define BF_CLKCTRL_CLKSEQ_BYPASS_GPMI_V(e)  BF_CLKCTRL_CLKSEQ_BYPASS_GPMI(BV_CLKCTRL_CLKSEQ_BYPASS_GPMI__##e)
+#define BFM_CLKCTRL_CLKSEQ_BYPASS_GPMI_V(v) BM_CLKCTRL_CLKSEQ_BYPASS_GPMI
+#define BP_CLKCTRL_CLKSEQ_BYPASS_IR         3
+#define BM_CLKCTRL_CLKSEQ_BYPASS_IR         0x8
+#define BF_CLKCTRL_CLKSEQ_BYPASS_IR(v)      (((v) & 0x1) << 3)
+#define BFM_CLKCTRL_CLKSEQ_BYPASS_IR(v)     BM_CLKCTRL_CLKSEQ_BYPASS_IR
+#define BF_CLKCTRL_CLKSEQ_BYPASS_IR_V(e)    BF_CLKCTRL_CLKSEQ_BYPASS_IR(BV_CLKCTRL_CLKSEQ_BYPASS_IR__##e)
+#define BFM_CLKCTRL_CLKSEQ_BYPASS_IR_V(v)   BM_CLKCTRL_CLKSEQ_BYPASS_IR
+#define BP_CLKCTRL_CLKSEQ_RSRVD0            2
+#define BM_CLKCTRL_CLKSEQ_RSRVD0            0x4
+#define BF_CLKCTRL_CLKSEQ_RSRVD0(v)         (((v) & 0x1) << 2)
+#define BFM_CLKCTRL_CLKSEQ_RSRVD0(v)        BM_CLKCTRL_CLKSEQ_RSRVD0
+#define BF_CLKCTRL_CLKSEQ_RSRVD0_V(e)       BF_CLKCTRL_CLKSEQ_RSRVD0(BV_CLKCTRL_CLKSEQ_RSRVD0__##e)
+#define BFM_CLKCTRL_CLKSEQ_RSRVD0_V(v)      BM_CLKCTRL_CLKSEQ_RSRVD0
+#define BP_CLKCTRL_CLKSEQ_BYPASS_PIX        1
+#define BM_CLKCTRL_CLKSEQ_BYPASS_PIX        0x2
+#define BF_CLKCTRL_CLKSEQ_BYPASS_PIX(v)     (((v) & 0x1) << 1)
+#define BFM_CLKCTRL_CLKSEQ_BYPASS_PIX(v)    BM_CLKCTRL_CLKSEQ_BYPASS_PIX
+#define BF_CLKCTRL_CLKSEQ_BYPASS_PIX_V(e)   BF_CLKCTRL_CLKSEQ_BYPASS_PIX(BV_CLKCTRL_CLKSEQ_BYPASS_PIX__##e)
+#define BFM_CLKCTRL_CLKSEQ_BYPASS_PIX_V(v)  BM_CLKCTRL_CLKSEQ_BYPASS_PIX
+#define BP_CLKCTRL_CLKSEQ_BYPASS_SAIF       0
+#define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF       0x1
+#define BF_CLKCTRL_CLKSEQ_BYPASS_SAIF(v)    (((v) & 0x1) << 0)
+#define BFM_CLKCTRL_CLKSEQ_BYPASS_SAIF(v)   BM_CLKCTRL_CLKSEQ_BYPASS_SAIF
+#define BF_CLKCTRL_CLKSEQ_BYPASS_SAIF_V(e)  BF_CLKCTRL_CLKSEQ_BYPASS_SAIF(BV_CLKCTRL_CLKSEQ_BYPASS_SAIF__##e)
+#define BFM_CLKCTRL_CLKSEQ_BYPASS_SAIF_V(v) BM_CLKCTRL_CLKSEQ_BYPASS_SAIF
+
+#define HW_CLKCTRL_RESET                HW(CLKCTRL_RESET)
+#define HWA_CLKCTRL_RESET               (0x80040000 + 0x120)
+#define HWT_CLKCTRL_RESET               HWIO_32_RW
+#define HWN_CLKCTRL_RESET               CLKCTRL_RESET
+#define HWI_CLKCTRL_RESET               
+#define BP_CLKCTRL_RESET_RSRVD          2
+#define BM_CLKCTRL_RESET_RSRVD          0xfffffffc
+#define BF_CLKCTRL_RESET_RSRVD(v)       (((v) & 0x3fffffff) << 2)
+#define BFM_CLKCTRL_RESET_RSRVD(v)      BM_CLKCTRL_RESET_RSRVD
+#define BF_CLKCTRL_RESET_RSRVD_V(e)     BF_CLKCTRL_RESET_RSRVD(BV_CLKCTRL_RESET_RSRVD__##e)
+#define BFM_CLKCTRL_RESET_RSRVD_V(v)    BM_CLKCTRL_RESET_RSRVD
+#define BP_CLKCTRL_RESET_CHIP           1
+#define BM_CLKCTRL_RESET_CHIP           0x2
+#define BF_CLKCTRL_RESET_CHIP(v)        (((v) & 0x1) << 1)
+#define BFM_CLKCTRL_RESET_CHIP(v)       BM_CLKCTRL_RESET_CHIP
+#define BF_CLKCTRL_RESET_CHIP_V(e)      BF_CLKCTRL_RESET_CHIP(BV_CLKCTRL_RESET_CHIP__##e)
+#define BFM_CLKCTRL_RESET_CHIP_V(v)     BM_CLKCTRL_RESET_CHIP
+#define BP_CLKCTRL_RESET_DIG            0
+#define BM_CLKCTRL_RESET_DIG            0x1
+#define BF_CLKCTRL_RESET_DIG(v)         (((v) & 0x1) << 0)
+#define BFM_CLKCTRL_RESET_DIG(v)        BM_CLKCTRL_RESET_DIG
+#define BF_CLKCTRL_RESET_DIG_V(e)       BF_CLKCTRL_RESET_DIG(BV_CLKCTRL_RESET_DIG__##e)
+#define BFM_CLKCTRL_RESET_DIG_V(v)      BM_CLKCTRL_RESET_DIG
+
+#define HW_CLKCTRL_STATUS                   HW(CLKCTRL_STATUS)
+#define HWA_CLKCTRL_STATUS                  (0x80040000 + 0x130)
+#define HWT_CLKCTRL_STATUS                  HWIO_32_RW
+#define HWN_CLKCTRL_STATUS                  CLKCTRL_STATUS
+#define HWI_CLKCTRL_STATUS                  
+#define BP_CLKCTRL_STATUS_CPU_LIMIT         30
+#define BM_CLKCTRL_STATUS_CPU_LIMIT         0xc0000000
+#define BF_CLKCTRL_STATUS_CPU_LIMIT(v)      (((v) & 0x3) << 30)
+#define BFM_CLKCTRL_STATUS_CPU_LIMIT(v)     BM_CLKCTRL_STATUS_CPU_LIMIT
+#define BF_CLKCTRL_STATUS_CPU_LIMIT_V(e)    BF_CLKCTRL_STATUS_CPU_LIMIT(BV_CLKCTRL_STATUS_CPU_LIMIT__##e)
+#define BFM_CLKCTRL_STATUS_CPU_LIMIT_V(v)   BM_CLKCTRL_STATUS_CPU_LIMIT
+#define BP_CLKCTRL_STATUS_RSRVD             0
+#define BM_CLKCTRL_STATUS_RSRVD             0x3fffffff
+#define BF_CLKCTRL_STATUS_RSRVD(v)          (((v) & 0x3fffffff) << 0)
+#define BFM_CLKCTRL_STATUS_RSRVD(v)         BM_CLKCTRL_STATUS_RSRVD
+#define BF_CLKCTRL_STATUS_RSRVD_V(e)        BF_CLKCTRL_STATUS_RSRVD(BV_CLKCTRL_STATUS_RSRVD__##e)
+#define BFM_CLKCTRL_STATUS_RSRVD_V(v)       BM_CLKCTRL_STATUS_RSRVD
+
+#define HW_CLKCTRL_VERSION              HW(CLKCTRL_VERSION)
+#define HWA_CLKCTRL_VERSION             (0x80040000 + 0x140)
+#define HWT_CLKCTRL_VERSION             HWIO_32_RW
+#define HWN_CLKCTRL_VERSION             CLKCTRL_VERSION
+#define HWI_CLKCTRL_VERSION             
+#define BP_CLKCTRL_VERSION_MAJOR        24
+#define BM_CLKCTRL_VERSION_MAJOR        0xff000000
+#define BF_CLKCTRL_VERSION_MAJOR(v)     (((v) & 0xff) << 24)
+#define BFM_CLKCTRL_VERSION_MAJOR(v)    BM_CLKCTRL_VERSION_MAJOR
+#define BF_CLKCTRL_VERSION_MAJOR_V(e)   BF_CLKCTRL_VERSION_MAJOR(BV_CLKCTRL_VERSION_MAJOR__##e)
+#define BFM_CLKCTRL_VERSION_MAJOR_V(v)  BM_CLKCTRL_VERSION_MAJOR
+#define BP_CLKCTRL_VERSION_MINOR        16
+#define BM_CLKCTRL_VERSION_MINOR        0xff0000
+#define BF_CLKCTRL_VERSION_MINOR(v)     (((v) & 0xff) << 16)
+#define BFM_CLKCTRL_VERSION_MINOR(v)    BM_CLKCTRL_VERSION_MINOR
+#define BF_CLKCTRL_VERSION_MINOR_V(e)   BF_CLKCTRL_VERSION_MINOR(BV_CLKCTRL_VERSION_MINOR__##e)
+#define BFM_CLKCTRL_VERSION_MINOR_V(v)  BM_CLKCTRL_VERSION_MINOR
+#define BP_CLKCTRL_VERSION_STEP         0
+#define BM_CLKCTRL_VERSION_STEP         0xffff
+#define BF_CLKCTRL_VERSION_STEP(v)      (((v) & 0xffff) << 0)
+#define BFM_CLKCTRL_VERSION_STEP(v)     BM_CLKCTRL_VERSION_STEP
+#define BF_CLKCTRL_VERSION_STEP_V(e)    BF_CLKCTRL_VERSION_STEP(BV_CLKCTRL_VERSION_STEP__##e)
+#define BFM_CLKCTRL_VERSION_STEP_V(v)   BM_CLKCTRL_VERSION_STEP
+
+#endif /* __HEADERGEN_IMX233_CLKCTRL_H__*/
diff --git a/firmware/target/arm/imx233/regs/imx233/dcp.h b/firmware/target/arm/imx233/regs/imx233/dcp.h
new file mode 100644
index 0000000000..ec3cf123c8
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/imx233/dcp.h
@@ -0,0 +1,1334 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * imx233 version: 2.4.0
+ * imx233 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_IMX233_DCP_H__
+#define __HEADERGEN_IMX233_DCP_H__
+
+#define HW_DCP_CTRL                                 HW(DCP_CTRL)
+#define HWA_DCP_CTRL                                (0x80028000 + 0x0)
+#define HWT_DCP_CTRL                                HWIO_32_RW
+#define HWN_DCP_CTRL                                DCP_CTRL
+#define HWI_DCP_CTRL                                
+#define HW_DCP_CTRL_SET                             HW(DCP_CTRL_SET)
+#define HWA_DCP_CTRL_SET                            (HWA_DCP_CTRL + 0x4)
+#define HWT_DCP_CTRL_SET                            HWIO_32_WO
+#define HWN_DCP_CTRL_SET                            DCP_CTRL
+#define HWI_DCP_CTRL_SET                            
+#define HW_DCP_CTRL_CLR                             HW(DCP_CTRL_CLR)
+#define HWA_DCP_CTRL_CLR                            (HWA_DCP_CTRL + 0x8)
+#define HWT_DCP_CTRL_CLR                            HWIO_32_WO
+#define HWN_DCP_CTRL_CLR                            DCP_CTRL
+#define HWI_DCP_CTRL_CLR                            
+#define HW_DCP_CTRL_TOG                             HW(DCP_CTRL_TOG)
+#define HWA_DCP_CTRL_TOG                            (HWA_DCP_CTRL + 0xc)
+#define HWT_DCP_CTRL_TOG                            HWIO_32_WO
+#define HWN_DCP_CTRL_TOG                            DCP_CTRL
+#define HWI_DCP_CTRL_TOG                            
+#define BP_DCP_CTRL_SFTRST                          31
+#define BM_DCP_CTRL_SFTRST                          0x80000000
+#define BF_DCP_CTRL_SFTRST(v)                       (((v) & 0x1) << 31)
+#define BFM_DCP_CTRL_SFTRST(v)                      BM_DCP_CTRL_SFTRST
+#define BF_DCP_CTRL_SFTRST_V(e)                     BF_DCP_CTRL_SFTRST(BV_DCP_CTRL_SFTRST__##e)
+#define BFM_DCP_CTRL_SFTRST_V(v)                    BM_DCP_CTRL_SFTRST
+#define BP_DCP_CTRL_CLKGATE                         30
+#define BM_DCP_CTRL_CLKGATE                         0x40000000
+#define BF_DCP_CTRL_CLKGATE(v)                      (((v) & 0x1) << 30)
+#define BFM_DCP_CTRL_CLKGATE(v)                     BM_DCP_CTRL_CLKGATE
+#define BF_DCP_CTRL_CLKGATE_V(e)                    BF_DCP_CTRL_CLKGATE(BV_DCP_CTRL_CLKGATE__##e)
+#define BFM_DCP_CTRL_CLKGATE_V(v)                   BM_DCP_CTRL_CLKGATE
+#define BP_DCP_CTRL_PRESENT_CRYPTO                  29
+#define BM_DCP_CTRL_PRESENT_CRYPTO                  0x20000000
+#define BV_DCP_CTRL_PRESENT_CRYPTO__Present         0x1
+#define BV_DCP_CTRL_PRESENT_CRYPTO__Absent          0x0
+#define BF_DCP_CTRL_PRESENT_CRYPTO(v)               (((v) & 0x1) << 29)
+#define BFM_DCP_CTRL_PRESENT_CRYPTO(v)              BM_DCP_CTRL_PRESENT_CRYPTO
+#define BF_DCP_CTRL_PRESENT_CRYPTO_V(e)             BF_DCP_CTRL_PRESENT_CRYPTO(BV_DCP_CTRL_PRESENT_CRYPTO__##e)
+#define BFM_DCP_CTRL_PRESENT_CRYPTO_V(v)            BM_DCP_CTRL_PRESENT_CRYPTO
+#define BP_DCP_CTRL_PRESENT_CSC                     28
+#define BM_DCP_CTRL_PRESENT_CSC                     0x10000000
+#define BV_DCP_CTRL_PRESENT_CSC__Present            0x1
+#define BV_DCP_CTRL_PRESENT_CSC__Absent             0x0
+#define BF_DCP_CTRL_PRESENT_CSC(v)                  (((v) & 0x1) << 28)
+#define BFM_DCP_CTRL_PRESENT_CSC(v)                 BM_DCP_CTRL_PRESENT_CSC
+#define BF_DCP_CTRL_PRESENT_CSC_V(e)                BF_DCP_CTRL_PRESENT_CSC(BV_DCP_CTRL_PRESENT_CSC__##e)
+#define BFM_DCP_CTRL_PRESENT_CSC_V(v)               BM_DCP_CTRL_PRESENT_CSC
+#define BP_DCP_CTRL_RSVD1                           24
+#define BM_DCP_CTRL_RSVD1                           0xf000000
+#define BF_DCP_CTRL_RSVD1(v)                        (((v) & 0xf) << 24)
+#define BFM_DCP_CTRL_RSVD1(v)                       BM_DCP_CTRL_RSVD1
+#define BF_DCP_CTRL_RSVD1_V(e)                      BF_DCP_CTRL_RSVD1(BV_DCP_CTRL_RSVD1__##e)
+#define BFM_DCP_CTRL_RSVD1_V(v)                     BM_DCP_CTRL_RSVD1
+#define BP_DCP_CTRL_GATHER_RESIDUAL_WRITES          23
+#define BM_DCP_CTRL_GATHER_RESIDUAL_WRITES          0x800000
+#define BF_DCP_CTRL_GATHER_RESIDUAL_WRITES(v)       (((v) & 0x1) << 23)
+#define BFM_DCP_CTRL_GATHER_RESIDUAL_WRITES(v)      BM_DCP_CTRL_GATHER_RESIDUAL_WRITES
+#define BF_DCP_CTRL_GATHER_RESIDUAL_WRITES_V(e)     BF_DCP_CTRL_GATHER_RESIDUAL_WRITES(BV_DCP_CTRL_GATHER_RESIDUAL_WRITES__##e)
+#define BFM_DCP_CTRL_GATHER_RESIDUAL_WRITES_V(v)    BM_DCP_CTRL_GATHER_RESIDUAL_WRITES
+#define BP_DCP_CTRL_ENABLE_CONTEXT_CACHING          22
+#define BM_DCP_CTRL_ENABLE_CONTEXT_CACHING          0x400000
+#define BF_DCP_CTRL_ENABLE_CONTEXT_CACHING(v)       (((v) & 0x1) << 22)
+#define BFM_DCP_CTRL_ENABLE_CONTEXT_CACHING(v)      BM_DCP_CTRL_ENABLE_CONTEXT_CACHING
+#define BF_DCP_CTRL_ENABLE_CONTEXT_CACHING_V(e)     BF_DCP_CTRL_ENABLE_CONTEXT_CACHING(BV_DCP_CTRL_ENABLE_CONTEXT_CACHING__##e)
+#define BFM_DCP_CTRL_ENABLE_CONTEXT_CACHING_V(v)    BM_DCP_CTRL_ENABLE_CONTEXT_CACHING
+#define BP_DCP_CTRL_ENABLE_CONTEXT_SWITCHING        21
+#define BM_DCP_CTRL_ENABLE_CONTEXT_SWITCHING        0x200000
+#define BF_DCP_CTRL_ENABLE_CONTEXT_SWITCHING(v)     (((v) & 0x1) << 21)
+#define BFM_DCP_CTRL_ENABLE_CONTEXT_SWITCHING(v)    BM_DCP_CTRL_ENABLE_CONTEXT_SWITCHING
+#define BF_DCP_CTRL_ENABLE_CONTEXT_SWITCHING_V(e)   BF_DCP_CTRL_ENABLE_CONTEXT_SWITCHING(BV_DCP_CTRL_ENABLE_CONTEXT_SWITCHING__##e)
+#define BFM_DCP_CTRL_ENABLE_CONTEXT_SWITCHING_V(v)  BM_DCP_CTRL_ENABLE_CONTEXT_SWITCHING
+#define BP_DCP_CTRL_RSVD0                           9
+#define BM_DCP_CTRL_RSVD0                           0x1ffe00
+#define BF_DCP_CTRL_RSVD0(v)                        (((v) & 0xfff) << 9)
+#define BFM_DCP_CTRL_RSVD0(v)                       BM_DCP_CTRL_RSVD0
+#define BF_DCP_CTRL_RSVD0_V(e)                      BF_DCP_CTRL_RSVD0(BV_DCP_CTRL_RSVD0__##e)
+#define BFM_DCP_CTRL_RSVD0_V(v)                     BM_DCP_CTRL_RSVD0
+#define BP_DCP_CTRL_CSC_INTERRUPT_ENABLE            8
+#define BM_DCP_CTRL_CSC_INTERRUPT_ENABLE            0x100
+#define BF_DCP_CTRL_CSC_INTERRUPT_ENABLE(v)         (((v) & 0x1) << 8)
+#define BFM_DCP_CTRL_CSC_INTERRUPT_ENABLE(v)        BM_DCP_CTRL_CSC_INTERRUPT_ENABLE
+#define BF_DCP_CTRL_CSC_INTERRUPT_ENABLE_V(e)       BF_DCP_CTRL_CSC_INTERRUPT_ENABLE(BV_DCP_CTRL_CSC_INTERRUPT_ENABLE__##e)
+#define BFM_DCP_CTRL_CSC_INTERRUPT_ENABLE_V(v)      BM_DCP_CTRL_CSC_INTERRUPT_ENABLE
+#define BP_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE        0
+#define BM_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE        0xff
+#define BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__CH0   0x1
+#define BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__CH1   0x2
+#define BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__CH2   0x4
+#define BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__CH3   0x8
+#define BF_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE(v)     (((v) & 0xff) << 0)
+#define BFM_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE(v)    BM_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE
+#define BF_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_V(e)   BF_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE(BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__##e)
+#define BFM_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_V(v)  BM_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE
+
+#define HW_DCP_STAT                         HW(DCP_STAT)
+#define HWA_DCP_STAT                        (0x80028000 + 0x10)
+#define HWT_DCP_STAT                        HWIO_32_RW
+#define HWN_DCP_STAT                        DCP_STAT
+#define HWI_DCP_STAT                        
+#define HW_DCP_STAT_SET                     HW(DCP_STAT_SET)
+#define HWA_DCP_STAT_SET                    (HWA_DCP_STAT + 0x4)
+#define HWT_DCP_STAT_SET                    HWIO_32_WO
+#define HWN_DCP_STAT_SET                    DCP_STAT
+#define HWI_DCP_STAT_SET                    
+#define HW_DCP_STAT_CLR                     HW(DCP_STAT_CLR)
+#define HWA_DCP_STAT_CLR                    (HWA_DCP_STAT + 0x8)
+#define HWT_DCP_STAT_CLR                    HWIO_32_WO
+#define HWN_DCP_STAT_CLR                    DCP_STAT
+#define HWI_DCP_STAT_CLR                    
+#define HW_DCP_STAT_TOG                     HW(DCP_STAT_TOG)
+#define HWA_DCP_STAT_TOG                    (HWA_DCP_STAT + 0xc)
+#define HWT_DCP_STAT_TOG                    HWIO_32_WO
+#define HWN_DCP_STAT_TOG                    DCP_STAT
+#define HWI_DCP_STAT_TOG                    
+#define BP_DCP_STAT_RSVD2                   29
+#define BM_DCP_STAT_RSVD2                   0xe0000000
+#define BF_DCP_STAT_RSVD2(v)                (((v) & 0x7) << 29)
+#define BFM_DCP_STAT_RSVD2(v)               BM_DCP_STAT_RSVD2
+#define BF_DCP_STAT_RSVD2_V(e)              BF_DCP_STAT_RSVD2(BV_DCP_STAT_RSVD2__##e)
+#define BFM_DCP_STAT_RSVD2_V(v)             BM_DCP_STAT_RSVD2
+#define BP_DCP_STAT_OTP_KEY_READY           28
+#define BM_DCP_STAT_OTP_KEY_READY           0x10000000
+#define BF_DCP_STAT_OTP_KEY_READY(v)        (((v) & 0x1) << 28)
+#define BFM_DCP_STAT_OTP_KEY_READY(v)       BM_DCP_STAT_OTP_KEY_READY
+#define BF_DCP_STAT_OTP_KEY_READY_V(e)      BF_DCP_STAT_OTP_KEY_READY(BV_DCP_STAT_OTP_KEY_READY__##e)
+#define BFM_DCP_STAT_OTP_KEY_READY_V(v)     BM_DCP_STAT_OTP_KEY_READY
+#define BP_DCP_STAT_CUR_CHANNEL             24
+#define BM_DCP_STAT_CUR_CHANNEL             0xf000000
+#define BV_DCP_STAT_CUR_CHANNEL__None       0x0
+#define BV_DCP_STAT_CUR_CHANNEL__CH0        0x1
+#define BV_DCP_STAT_CUR_CHANNEL__CH1        0x2
+#define BV_DCP_STAT_CUR_CHANNEL__CH2        0x3
+#define BV_DCP_STAT_CUR_CHANNEL__CH3        0x4
+#define BV_DCP_STAT_CUR_CHANNEL__CSC        0x8
+#define BF_DCP_STAT_CUR_CHANNEL(v)          (((v) & 0xf) << 24)
+#define BFM_DCP_STAT_CUR_CHANNEL(v)         BM_DCP_STAT_CUR_CHANNEL
+#define BF_DCP_STAT_CUR_CHANNEL_V(e)        BF_DCP_STAT_CUR_CHANNEL(BV_DCP_STAT_CUR_CHANNEL__##e)
+#define BFM_DCP_STAT_CUR_CHANNEL_V(v)       BM_DCP_STAT_CUR_CHANNEL
+#define BP_DCP_STAT_READY_CHANNELS          16
+#define BM_DCP_STAT_READY_CHANNELS          0xff0000
+#define BV_DCP_STAT_READY_CHANNELS__CH0     0x1
+#define BV_DCP_STAT_READY_CHANNELS__CH1     0x2
+#define BV_DCP_STAT_READY_CHANNELS__CH2     0x4
+#define BV_DCP_STAT_READY_CHANNELS__CH3     0x8
+#define BF_DCP_STAT_READY_CHANNELS(v)       (((v) & 0xff) << 16)
+#define BFM_DCP_STAT_READY_CHANNELS(v)      BM_DCP_STAT_READY_CHANNELS
+#define BF_DCP_STAT_READY_CHANNELS_V(e)     BF_DCP_STAT_READY_CHANNELS(BV_DCP_STAT_READY_CHANNELS__##e)
+#define BFM_DCP_STAT_READY_CHANNELS_V(v)    BM_DCP_STAT_READY_CHANNELS
+#define BP_DCP_STAT_RSVD1                   9
+#define BM_DCP_STAT_RSVD1                   0xfe00
+#define BF_DCP_STAT_RSVD1(v)                (((v) & 0x7f) << 9)
+#define BFM_DCP_STAT_RSVD1(v)               BM_DCP_STAT_RSVD1
+#define BF_DCP_STAT_RSVD1_V(e)              BF_DCP_STAT_RSVD1(BV_DCP_STAT_RSVD1__##e)
+#define BFM_DCP_STAT_RSVD1_V(v)             BM_DCP_STAT_RSVD1
+#define BP_DCP_STAT_CSCIRQ                  8
+#define BM_DCP_STAT_CSCIRQ                  0x100
+#define BF_DCP_STAT_CSCIRQ(v)               (((v) & 0x1) << 8)
+#define BFM_DCP_STAT_CSCIRQ(v)              BM_DCP_STAT_CSCIRQ
+#define BF_DCP_STAT_CSCIRQ_V(e)             BF_DCP_STAT_CSCIRQ(BV_DCP_STAT_CSCIRQ__##e)
+#define BFM_DCP_STAT_CSCIRQ_V(v)            BM_DCP_STAT_CSCIRQ
+#define BP_DCP_STAT_RSVD0                   4
+#define BM_DCP_STAT_RSVD0                   0xf0
+#define BF_DCP_STAT_RSVD0(v)                (((v) & 0xf) << 4)
+#define BFM_DCP_STAT_RSVD0(v)               BM_DCP_STAT_RSVD0
+#define BF_DCP_STAT_RSVD0_V(e)              BF_DCP_STAT_RSVD0(BV_DCP_STAT_RSVD0__##e)
+#define BFM_DCP_STAT_RSVD0_V(v)             BM_DCP_STAT_RSVD0
+#define BP_DCP_STAT_IRQ                     0
+#define BM_DCP_STAT_IRQ                     0xf
+#define BF_DCP_STAT_IRQ(v)                  (((v) & 0xf) << 0)
+#define BFM_DCP_STAT_IRQ(v)                 BM_DCP_STAT_IRQ
+#define BF_DCP_STAT_IRQ_V(e)                BF_DCP_STAT_IRQ(BV_DCP_STAT_IRQ__##e)
+#define BFM_DCP_STAT_IRQ_V(v)               BM_DCP_STAT_IRQ
+
+#define HW_DCP_CHANNELCTRL                              HW(DCP_CHANNELCTRL)
+#define HWA_DCP_CHANNELCTRL                             (0x80028000 + 0x20)
+#define HWT_DCP_CHANNELCTRL                             HWIO_32_RW
+#define HWN_DCP_CHANNELCTRL                             DCP_CHANNELCTRL
+#define HWI_DCP_CHANNELCTRL                             
+#define HW_DCP_CHANNELCTRL_SET                          HW(DCP_CHANNELCTRL_SET)
+#define HWA_DCP_CHANNELCTRL_SET                         (HWA_DCP_CHANNELCTRL + 0x4)
+#define HWT_DCP_CHANNELCTRL_SET                         HWIO_32_WO
+#define HWN_DCP_CHANNELCTRL_SET                         DCP_CHANNELCTRL
+#define HWI_DCP_CHANNELCTRL_SET                         
+#define HW_DCP_CHANNELCTRL_CLR                          HW(DCP_CHANNELCTRL_CLR)
+#define HWA_DCP_CHANNELCTRL_CLR                         (HWA_DCP_CHANNELCTRL + 0x8)
+#define HWT_DCP_CHANNELCTRL_CLR                         HWIO_32_WO
+#define HWN_DCP_CHANNELCTRL_CLR                         DCP_CHANNELCTRL
+#define HWI_DCP_CHANNELCTRL_CLR                         
+#define HW_DCP_CHANNELCTRL_TOG                          HW(DCP_CHANNELCTRL_TOG)
+#define HWA_DCP_CHANNELCTRL_TOG                         (HWA_DCP_CHANNELCTRL + 0xc)
+#define HWT_DCP_CHANNELCTRL_TOG                         HWIO_32_WO
+#define HWN_DCP_CHANNELCTRL_TOG                         DCP_CHANNELCTRL
+#define HWI_DCP_CHANNELCTRL_TOG                         
+#define BP_DCP_CHANNELCTRL_RSVD                         19
+#define BM_DCP_CHANNELCTRL_RSVD                         0xfff80000
+#define BF_DCP_CHANNELCTRL_RSVD(v)                      (((v) & 0x1fff) << 19)
+#define BFM_DCP_CHANNELCTRL_RSVD(v)                     BM_DCP_CHANNELCTRL_RSVD
+#define BF_DCP_CHANNELCTRL_RSVD_V(e)                    BF_DCP_CHANNELCTRL_RSVD(BV_DCP_CHANNELCTRL_RSVD__##e)
+#define BFM_DCP_CHANNELCTRL_RSVD_V(v)                   BM_DCP_CHANNELCTRL_RSVD
+#define BP_DCP_CHANNELCTRL_CSC_PRIORITY                 17
+#define BM_DCP_CHANNELCTRL_CSC_PRIORITY                 0x60000
+#define BV_DCP_CHANNELCTRL_CSC_PRIORITY__HIGH           0x3
+#define BV_DCP_CHANNELCTRL_CSC_PRIORITY__MED            0x2
+#define BV_DCP_CHANNELCTRL_CSC_PRIORITY__LOW            0x1
+#define BV_DCP_CHANNELCTRL_CSC_PRIORITY__BACKGROUND     0x0
+#define BF_DCP_CHANNELCTRL_CSC_PRIORITY(v)              (((v) & 0x3) << 17)
+#define BFM_DCP_CHANNELCTRL_CSC_PRIORITY(v)             BM_DCP_CHANNELCTRL_CSC_PRIORITY
+#define BF_DCP_CHANNELCTRL_CSC_PRIORITY_V(e)            BF_DCP_CHANNELCTRL_CSC_PRIORITY(BV_DCP_CHANNELCTRL_CSC_PRIORITY__##e)
+#define BFM_DCP_CHANNELCTRL_CSC_PRIORITY_V(v)           BM_DCP_CHANNELCTRL_CSC_PRIORITY
+#define BP_DCP_CHANNELCTRL_CH0_IRQ_MERGED               16
+#define BM_DCP_CHANNELCTRL_CH0_IRQ_MERGED               0x10000
+#define BF_DCP_CHANNELCTRL_CH0_IRQ_MERGED(v)            (((v) & 0x1) << 16)
+#define BFM_DCP_CHANNELCTRL_CH0_IRQ_MERGED(v)           BM_DCP_CHANNELCTRL_CH0_IRQ_MERGED
+#define BF_DCP_CHANNELCTRL_CH0_IRQ_MERGED_V(e)          BF_DCP_CHANNELCTRL_CH0_IRQ_MERGED(BV_DCP_CHANNELCTRL_CH0_IRQ_MERGED__##e)
+#define BFM_DCP_CHANNELCTRL_CH0_IRQ_MERGED_V(v)         BM_DCP_CHANNELCTRL_CH0_IRQ_MERGED
+#define BP_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL        8
+#define BM_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL        0xff00
+#define BV_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL__CH0   0x1
+#define BV_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL__CH1   0x2
+#define BV_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL__CH2   0x4
+#define BV_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL__CH3   0x8
+#define BF_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL(v)     (((v) & 0xff) << 8)
+#define BFM_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL(v)    BM_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL
+#define BF_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_V(e)   BF_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL(BV_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL__##e)
+#define BFM_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_V(v)  BM_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL
+#define BP_DCP_CHANNELCTRL_ENABLE_CHANNEL               0
+#define BM_DCP_CHANNELCTRL_ENABLE_CHANNEL               0xff
+#define BV_DCP_CHANNELCTRL_ENABLE_CHANNEL__CH0          0x1
+#define BV_DCP_CHANNELCTRL_ENABLE_CHANNEL__CH1          0x2
+#define BV_DCP_CHANNELCTRL_ENABLE_CHANNEL__CH2          0x4
+#define BV_DCP_CHANNELCTRL_ENABLE_CHANNEL__CH3          0x8
+#define BF_DCP_CHANNELCTRL_ENABLE_CHANNEL(v)            (((v) & 0xff) << 0)
+#define BFM_DCP_CHANNELCTRL_ENABLE_CHANNEL(v)           BM_DCP_CHANNELCTRL_ENABLE_CHANNEL
+#define BF_DCP_CHANNELCTRL_ENABLE_CHANNEL_V(e)          BF_DCP_CHANNELCTRL_ENABLE_CHANNEL(BV_DCP_CHANNELCTRL_ENABLE_CHANNEL__##e)
+#define BFM_DCP_CHANNELCTRL_ENABLE_CHANNEL_V(v)         BM_DCP_CHANNELCTRL_ENABLE_CHANNEL
+
+#define HW_DCP_CAPABILITY0                          HW(DCP_CAPABILITY0)
+#define HWA_DCP_CAPABILITY0                         (0x80028000 + 0x30)
+#define HWT_DCP_CAPABILITY0                         HWIO_32_RW
+#define HWN_DCP_CAPABILITY0                         DCP_CAPABILITY0
+#define HWI_DCP_CAPABILITY0                         
+#define BP_DCP_CAPABILITY0_DISABLE_DECRYPT          31
+#define BM_DCP_CAPABILITY0_DISABLE_DECRYPT          0x80000000
+#define BF_DCP_CAPABILITY0_DISABLE_DECRYPT(v)       (((v) & 0x1) << 31)
+#define BFM_DCP_CAPABILITY0_DISABLE_DECRYPT(v)      BM_DCP_CAPABILITY0_DISABLE_DECRYPT
+#define BF_DCP_CAPABILITY0_DISABLE_DECRYPT_V(e)     BF_DCP_CAPABILITY0_DISABLE_DECRYPT(BV_DCP_CAPABILITY0_DISABLE_DECRYPT__##e)
+#define BFM_DCP_CAPABILITY0_DISABLE_DECRYPT_V(v)    BM_DCP_CAPABILITY0_DISABLE_DECRYPT
+#define BP_DCP_CAPABILITY0_ENABLE_TZONE             30
+#define BM_DCP_CAPABILITY0_ENABLE_TZONE             0x40000000
+#define BF_DCP_CAPABILITY0_ENABLE_TZONE(v)          (((v) & 0x1) << 30)
+#define BFM_DCP_CAPABILITY0_ENABLE_TZONE(v)         BM_DCP_CAPABILITY0_ENABLE_TZONE
+#define BF_DCP_CAPABILITY0_ENABLE_TZONE_V(e)        BF_DCP_CAPABILITY0_ENABLE_TZONE(BV_DCP_CAPABILITY0_ENABLE_TZONE__##e)
+#define BFM_DCP_CAPABILITY0_ENABLE_TZONE_V(v)       BM_DCP_CAPABILITY0_ENABLE_TZONE
+#define BP_DCP_CAPABILITY0_RSVD                     12
+#define BM_DCP_CAPABILITY0_RSVD                     0x3ffff000
+#define BF_DCP_CAPABILITY0_RSVD(v)                  (((v) & 0x3ffff) << 12)
+#define BFM_DCP_CAPABILITY0_RSVD(v)                 BM_DCP_CAPABILITY0_RSVD
+#define BF_DCP_CAPABILITY0_RSVD_V(e)                BF_DCP_CAPABILITY0_RSVD(BV_DCP_CAPABILITY0_RSVD__##e)
+#define BFM_DCP_CAPABILITY0_RSVD_V(v)               BM_DCP_CAPABILITY0_RSVD
+#define BP_DCP_CAPABILITY0_NUM_CHANNELS             8
+#define BM_DCP_CAPABILITY0_NUM_CHANNELS             0xf00
+#define BF_DCP_CAPABILITY0_NUM_CHANNELS(v)          (((v) & 0xf) << 8)
+#define BFM_DCP_CAPABILITY0_NUM_CHANNELS(v)         BM_DCP_CAPABILITY0_NUM_CHANNELS
+#define BF_DCP_CAPABILITY0_NUM_CHANNELS_V(e)        BF_DCP_CAPABILITY0_NUM_CHANNELS(BV_DCP_CAPABILITY0_NUM_CHANNELS__##e)
+#define BFM_DCP_CAPABILITY0_NUM_CHANNELS_V(v)       BM_DCP_CAPABILITY0_NUM_CHANNELS
+#define BP_DCP_CAPABILITY0_NUM_KEYS                 0
+#define BM_DCP_CAPABILITY0_NUM_KEYS                 0xff
+#define BF_DCP_CAPABILITY0_NUM_KEYS(v)              (((v) & 0xff) << 0)
+#define BFM_DCP_CAPABILITY0_NUM_KEYS(v)             BM_DCP_CAPABILITY0_NUM_KEYS
+#define BF_DCP_CAPABILITY0_NUM_KEYS_V(e)            BF_DCP_CAPABILITY0_NUM_KEYS(BV_DCP_CAPABILITY0_NUM_KEYS__##e)
+#define BFM_DCP_CAPABILITY0_NUM_KEYS_V(v)           BM_DCP_CAPABILITY0_NUM_KEYS
+
+#define HW_DCP_CAPABILITY1                              HW(DCP_CAPABILITY1)
+#define HWA_DCP_CAPABILITY1                             (0x80028000 + 0x40)
+#define HWT_DCP_CAPABILITY1                             HWIO_32_RW
+#define HWN_DCP_CAPABILITY1                             DCP_CAPABILITY1
+#define HWI_DCP_CAPABILITY1                             
+#define BP_DCP_CAPABILITY1_HASH_ALGORITHMS              16
+#define BM_DCP_CAPABILITY1_HASH_ALGORITHMS              0xffff0000
+#define BV_DCP_CAPABILITY1_HASH_ALGORITHMS__SHA1        0x1
+#define BV_DCP_CAPABILITY1_HASH_ALGORITHMS__CRC32       0x2
+#define BF_DCP_CAPABILITY1_HASH_ALGORITHMS(v)           (((v) & 0xffff) << 16)
+#define BFM_DCP_CAPABILITY1_HASH_ALGORITHMS(v)          BM_DCP_CAPABILITY1_HASH_ALGORITHMS
+#define BF_DCP_CAPABILITY1_HASH_ALGORITHMS_V(e)         BF_DCP_CAPABILITY1_HASH_ALGORITHMS(BV_DCP_CAPABILITY1_HASH_ALGORITHMS__##e)
+#define BFM_DCP_CAPABILITY1_HASH_ALGORITHMS_V(v)        BM_DCP_CAPABILITY1_HASH_ALGORITHMS
+#define BP_DCP_CAPABILITY1_CIPHER_ALGORITHMS            0
+#define BM_DCP_CAPABILITY1_CIPHER_ALGORITHMS            0xffff
+#define BV_DCP_CAPABILITY1_CIPHER_ALGORITHMS__AES128    0x1
+#define BF_DCP_CAPABILITY1_CIPHER_ALGORITHMS(v)         (((v) & 0xffff) << 0)
+#define BFM_DCP_CAPABILITY1_CIPHER_ALGORITHMS(v)        BM_DCP_CAPABILITY1_CIPHER_ALGORITHMS
+#define BF_DCP_CAPABILITY1_CIPHER_ALGORITHMS_V(e)       BF_DCP_CAPABILITY1_CIPHER_ALGORITHMS(BV_DCP_CAPABILITY1_CIPHER_ALGORITHMS__##e)
+#define BFM_DCP_CAPABILITY1_CIPHER_ALGORITHMS_V(v)      BM_DCP_CAPABILITY1_CIPHER_ALGORITHMS
+
+#define HW_DCP_CONTEXT              HW(DCP_CONTEXT)
+#define HWA_DCP_CONTEXT             (0x80028000 + 0x50)
+#define HWT_DCP_CONTEXT             HWIO_32_RW
+#define HWN_DCP_CONTEXT             DCP_CONTEXT
+#define HWI_DCP_CONTEXT             
+#define BP_DCP_CONTEXT_ADDR         0
+#define BM_DCP_CONTEXT_ADDR         0xffffffff
+#define BF_DCP_CONTEXT_ADDR(v)      (((v) & 0xffffffff) << 0)
+#define BFM_DCP_CONTEXT_ADDR(v)     BM_DCP_CONTEXT_ADDR
+#define BF_DCP_CONTEXT_ADDR_V(e)    BF_DCP_CONTEXT_ADDR(BV_DCP_CONTEXT_ADDR__##e)
+#define BFM_DCP_CONTEXT_ADDR_V(v)   BM_DCP_CONTEXT_ADDR
+
+#define HW_DCP_KEY                      HW(DCP_KEY)
+#define HWA_DCP_KEY                     (0x80028000 + 0x60)
+#define HWT_DCP_KEY                     HWIO_32_RW
+#define HWN_DCP_KEY                     DCP_KEY
+#define HWI_DCP_KEY                     
+#define BP_DCP_KEY_RSVD                 8
+#define BM_DCP_KEY_RSVD                 0xffffff00
+#define BF_DCP_KEY_RSVD(v)              (((v) & 0xffffff) << 8)
+#define BFM_DCP_KEY_RSVD(v)             BM_DCP_KEY_RSVD
+#define BF_DCP_KEY_RSVD_V(e)            BF_DCP_KEY_RSVD(BV_DCP_KEY_RSVD__##e)
+#define BFM_DCP_KEY_RSVD_V(v)           BM_DCP_KEY_RSVD
+#define BP_DCP_KEY_RSVD_INDEX           6
+#define BM_DCP_KEY_RSVD_INDEX           0xc0
+#define BF_DCP_KEY_RSVD_INDEX(v)        (((v) & 0x3) << 6)
+#define BFM_DCP_KEY_RSVD_INDEX(v)       BM_DCP_KEY_RSVD_INDEX
+#define BF_DCP_KEY_RSVD_INDEX_V(e)      BF_DCP_KEY_RSVD_INDEX(BV_DCP_KEY_RSVD_INDEX__##e)
+#define BFM_DCP_KEY_RSVD_INDEX_V(v)     BM_DCP_KEY_RSVD_INDEX
+#define BP_DCP_KEY_INDEX                4
+#define BM_DCP_KEY_INDEX                0x30
+#define BF_DCP_KEY_INDEX(v)             (((v) & 0x3) << 4)
+#define BFM_DCP_KEY_INDEX(v)            BM_DCP_KEY_INDEX
+#define BF_DCP_KEY_INDEX_V(e)           BF_DCP_KEY_INDEX(BV_DCP_KEY_INDEX__##e)
+#define BFM_DCP_KEY_INDEX_V(v)          BM_DCP_KEY_INDEX
+#define BP_DCP_KEY_RSVD_SUBWORD         2
+#define BM_DCP_KEY_RSVD_SUBWORD         0xc
+#define BF_DCP_KEY_RSVD_SUBWORD(v)      (((v) & 0x3) << 2)
+#define BFM_DCP_KEY_RSVD_SUBWORD(v)     BM_DCP_KEY_RSVD_SUBWORD
+#define BF_DCP_KEY_RSVD_SUBWORD_V(e)    BF_DCP_KEY_RSVD_SUBWORD(BV_DCP_KEY_RSVD_SUBWORD__##e)
+#define BFM_DCP_KEY_RSVD_SUBWORD_V(v)   BM_DCP_KEY_RSVD_SUBWORD
+#define BP_DCP_KEY_SUBWORD              0
+#define BM_DCP_KEY_SUBWORD              0x3
+#define BF_DCP_KEY_SUBWORD(v)           (((v) & 0x3) << 0)
+#define BFM_DCP_KEY_SUBWORD(v)          BM_DCP_KEY_SUBWORD
+#define BF_DCP_KEY_SUBWORD_V(e)         BF_DCP_KEY_SUBWORD(BV_DCP_KEY_SUBWORD__##e)
+#define BFM_DCP_KEY_SUBWORD_V(v)        BM_DCP_KEY_SUBWORD
+
+#define HW_DCP_KEYDATA              HW(DCP_KEYDATA)
+#define HWA_DCP_KEYDATA             (0x80028000 + 0x70)
+#define HWT_DCP_KEYDATA             HWIO_32_RW
+#define HWN_DCP_KEYDATA             DCP_KEYDATA
+#define HWI_DCP_KEYDATA             
+#define BP_DCP_KEYDATA_DATA         0
+#define BM_DCP_KEYDATA_DATA         0xffffffff
+#define BF_DCP_KEYDATA_DATA(v)      (((v) & 0xffffffff) << 0)
+#define BFM_DCP_KEYDATA_DATA(v)     BM_DCP_KEYDATA_DATA
+#define BF_DCP_KEYDATA_DATA_V(e)    BF_DCP_KEYDATA_DATA(BV_DCP_KEYDATA_DATA__##e)
+#define BFM_DCP_KEYDATA_DATA_V(v)   BM_DCP_KEYDATA_DATA
+
+#define HW_DCP_PACKET0              HW(DCP_PACKET0)
+#define HWA_DCP_PACKET0             (0x80028000 + 0x80)
+#define HWT_DCP_PACKET0             HWIO_32_RW
+#define HWN_DCP_PACKET0             DCP_PACKET0
+#define HWI_DCP_PACKET0             
+#define BP_DCP_PACKET0_ADDR         0
+#define BM_DCP_PACKET0_ADDR         0xffffffff
+#define BF_DCP_PACKET0_ADDR(v)      (((v) & 0xffffffff) << 0)
+#define BFM_DCP_PACKET0_ADDR(v)     BM_DCP_PACKET0_ADDR
+#define BF_DCP_PACKET0_ADDR_V(e)    BF_DCP_PACKET0_ADDR(BV_DCP_PACKET0_ADDR__##e)
+#define BFM_DCP_PACKET0_ADDR_V(v)   BM_DCP_PACKET0_ADDR
+
+#define HW_DCP_PACKET1                          HW(DCP_PACKET1)
+#define HWA_DCP_PACKET1                         (0x80028000 + 0x90)
+#define HWT_DCP_PACKET1                         HWIO_32_RW
+#define HWN_DCP_PACKET1                         DCP_PACKET1
+#define HWI_DCP_PACKET1                         
+#define BP_DCP_PACKET1_TAG                      24
+#define BM_DCP_PACKET1_TAG                      0xff000000
+#define BF_DCP_PACKET1_TAG(v)                   (((v) & 0xff) << 24)
+#define BFM_DCP_PACKET1_TAG(v)                  BM_DCP_PACKET1_TAG
+#define BF_DCP_PACKET1_TAG_V(e)                 BF_DCP_PACKET1_TAG(BV_DCP_PACKET1_TAG__##e)
+#define BFM_DCP_PACKET1_TAG_V(v)                BM_DCP_PACKET1_TAG
+#define BP_DCP_PACKET1_OUTPUT_WORDSWAP          23
+#define BM_DCP_PACKET1_OUTPUT_WORDSWAP          0x800000
+#define BF_DCP_PACKET1_OUTPUT_WORDSWAP(v)       (((v) & 0x1) << 23)
+#define BFM_DCP_PACKET1_OUTPUT_WORDSWAP(v)      BM_DCP_PACKET1_OUTPUT_WORDSWAP
+#define BF_DCP_PACKET1_OUTPUT_WORDSWAP_V(e)     BF_DCP_PACKET1_OUTPUT_WORDSWAP(BV_DCP_PACKET1_OUTPUT_WORDSWAP__##e)
+#define BFM_DCP_PACKET1_OUTPUT_WORDSWAP_V(v)    BM_DCP_PACKET1_OUTPUT_WORDSWAP
+#define BP_DCP_PACKET1_OUTPUT_BYTESWAP          22
+#define BM_DCP_PACKET1_OUTPUT_BYTESWAP          0x400000
+#define BF_DCP_PACKET1_OUTPUT_BYTESWAP(v)       (((v) & 0x1) << 22)
+#define BFM_DCP_PACKET1_OUTPUT_BYTESWAP(v)      BM_DCP_PACKET1_OUTPUT_BYTESWAP
+#define BF_DCP_PACKET1_OUTPUT_BYTESWAP_V(e)     BF_DCP_PACKET1_OUTPUT_BYTESWAP(BV_DCP_PACKET1_OUTPUT_BYTESWAP__##e)
+#define BFM_DCP_PACKET1_OUTPUT_BYTESWAP_V(v)    BM_DCP_PACKET1_OUTPUT_BYTESWAP
+#define BP_DCP_PACKET1_INPUT_WORDSWAP           21
+#define BM_DCP_PACKET1_INPUT_WORDSWAP           0x200000
+#define BF_DCP_PACKET1_INPUT_WORDSWAP(v)        (((v) & 0x1) << 21)
+#define BFM_DCP_PACKET1_INPUT_WORDSWAP(v)       BM_DCP_PACKET1_INPUT_WORDSWAP
+#define BF_DCP_PACKET1_INPUT_WORDSWAP_V(e)      BF_DCP_PACKET1_INPUT_WORDSWAP(BV_DCP_PACKET1_INPUT_WORDSWAP__##e)
+#define BFM_DCP_PACKET1_INPUT_WORDSWAP_V(v)     BM_DCP_PACKET1_INPUT_WORDSWAP
+#define BP_DCP_PACKET1_INPUT_BYTESWAP           20
+#define BM_DCP_PACKET1_INPUT_BYTESWAP           0x100000
+#define BF_DCP_PACKET1_INPUT_BYTESWAP(v)        (((v) & 0x1) << 20)
+#define BFM_DCP_PACKET1_INPUT_BYTESWAP(v)       BM_DCP_PACKET1_INPUT_BYTESWAP
+#define BF_DCP_PACKET1_INPUT_BYTESWAP_V(e)      BF_DCP_PACKET1_INPUT_BYTESWAP(BV_DCP_PACKET1_INPUT_BYTESWAP__##e)
+#define BFM_DCP_PACKET1_INPUT_BYTESWAP_V(v)     BM_DCP_PACKET1_INPUT_BYTESWAP
+#define BP_DCP_PACKET1_KEY_WORDSWAP             19
+#define BM_DCP_PACKET1_KEY_WORDSWAP             0x80000
+#define BF_DCP_PACKET1_KEY_WORDSWAP(v)          (((v) & 0x1) << 19)
+#define BFM_DCP_PACKET1_KEY_WORDSWAP(v)         BM_DCP_PACKET1_KEY_WORDSWAP
+#define BF_DCP_PACKET1_KEY_WORDSWAP_V(e)        BF_DCP_PACKET1_KEY_WORDSWAP(BV_DCP_PACKET1_KEY_WORDSWAP__##e)
+#define BFM_DCP_PACKET1_KEY_WORDSWAP_V(v)       BM_DCP_PACKET1_KEY_WORDSWAP
+#define BP_DCP_PACKET1_KEY_BYTESWAP             18
+#define BM_DCP_PACKET1_KEY_BYTESWAP             0x40000
+#define BF_DCP_PACKET1_KEY_BYTESWAP(v)          (((v) & 0x1) << 18)
+#define BFM_DCP_PACKET1_KEY_BYTESWAP(v)         BM_DCP_PACKET1_KEY_BYTESWAP
+#define BF_DCP_PACKET1_KEY_BYTESWAP_V(e)        BF_DCP_PACKET1_KEY_BYTESWAP(BV_DCP_PACKET1_KEY_BYTESWAP__##e)
+#define BFM_DCP_PACKET1_KEY_BYTESWAP_V(v)       BM_DCP_PACKET1_KEY_BYTESWAP
+#define BP_DCP_PACKET1_TEST_SEMA_IRQ            17
+#define BM_DCP_PACKET1_TEST_SEMA_IRQ            0x20000
+#define BF_DCP_PACKET1_TEST_SEMA_IRQ(v)         (((v) & 0x1) << 17)
+#define BFM_DCP_PACKET1_TEST_SEMA_IRQ(v)        BM_DCP_PACKET1_TEST_SEMA_IRQ
+#define BF_DCP_PACKET1_TEST_SEMA_IRQ_V(e)       BF_DCP_PACKET1_TEST_SEMA_IRQ(BV_DCP_PACKET1_TEST_SEMA_IRQ__##e)
+#define BFM_DCP_PACKET1_TEST_SEMA_IRQ_V(v)      BM_DCP_PACKET1_TEST_SEMA_IRQ
+#define BP_DCP_PACKET1_CONSTANT_FILL            16
+#define BM_DCP_PACKET1_CONSTANT_FILL            0x10000
+#define BF_DCP_PACKET1_CONSTANT_FILL(v)         (((v) & 0x1) << 16)
+#define BFM_DCP_PACKET1_CONSTANT_FILL(v)        BM_DCP_PACKET1_CONSTANT_FILL
+#define BF_DCP_PACKET1_CONSTANT_FILL_V(e)       BF_DCP_PACKET1_CONSTANT_FILL(BV_DCP_PACKET1_CONSTANT_FILL__##e)
+#define BFM_DCP_PACKET1_CONSTANT_FILL_V(v)      BM_DCP_PACKET1_CONSTANT_FILL
+#define BP_DCP_PACKET1_HASH_OUTPUT              15
+#define BM_DCP_PACKET1_HASH_OUTPUT              0x8000
+#define BV_DCP_PACKET1_HASH_OUTPUT__INPUT       0x0
+#define BV_DCP_PACKET1_HASH_OUTPUT__OUTPUT      0x1
+#define BF_DCP_PACKET1_HASH_OUTPUT(v)           (((v) & 0x1) << 15)
+#define BFM_DCP_PACKET1_HASH_OUTPUT(v)          BM_DCP_PACKET1_HASH_OUTPUT
+#define BF_DCP_PACKET1_HASH_OUTPUT_V(e)         BF_DCP_PACKET1_HASH_OUTPUT(BV_DCP_PACKET1_HASH_OUTPUT__##e)
+#define BFM_DCP_PACKET1_HASH_OUTPUT_V(v)        BM_DCP_PACKET1_HASH_OUTPUT
+#define BP_DCP_PACKET1_CHECK_HASH               14
+#define BM_DCP_PACKET1_CHECK_HASH               0x4000
+#define BF_DCP_PACKET1_CHECK_HASH(v)            (((v) & 0x1) << 14)
+#define BFM_DCP_PACKET1_CHECK_HASH(v)           BM_DCP_PACKET1_CHECK_HASH
+#define BF_DCP_PACKET1_CHECK_HASH_V(e)          BF_DCP_PACKET1_CHECK_HASH(BV_DCP_PACKET1_CHECK_HASH__##e)
+#define BFM_DCP_PACKET1_CHECK_HASH_V(v)         BM_DCP_PACKET1_CHECK_HASH
+#define BP_DCP_PACKET1_HASH_TERM                13
+#define BM_DCP_PACKET1_HASH_TERM                0x2000
+#define BF_DCP_PACKET1_HASH_TERM(v)             (((v) & 0x1) << 13)
+#define BFM_DCP_PACKET1_HASH_TERM(v)            BM_DCP_PACKET1_HASH_TERM
+#define BF_DCP_PACKET1_HASH_TERM_V(e)           BF_DCP_PACKET1_HASH_TERM(BV_DCP_PACKET1_HASH_TERM__##e)
+#define BFM_DCP_PACKET1_HASH_TERM_V(v)          BM_DCP_PACKET1_HASH_TERM
+#define BP_DCP_PACKET1_HASH_INIT                12
+#define BM_DCP_PACKET1_HASH_INIT                0x1000
+#define BF_DCP_PACKET1_HASH_INIT(v)             (((v) & 0x1) << 12)
+#define BFM_DCP_PACKET1_HASH_INIT(v)            BM_DCP_PACKET1_HASH_INIT
+#define BF_DCP_PACKET1_HASH_INIT_V(e)           BF_DCP_PACKET1_HASH_INIT(BV_DCP_PACKET1_HASH_INIT__##e)
+#define BFM_DCP_PACKET1_HASH_INIT_V(v)          BM_DCP_PACKET1_HASH_INIT
+#define BP_DCP_PACKET1_PAYLOAD_KEY              11
+#define BM_DCP_PACKET1_PAYLOAD_KEY              0x800
+#define BF_DCP_PACKET1_PAYLOAD_KEY(v)           (((v) & 0x1) << 11)
+#define BFM_DCP_PACKET1_PAYLOAD_KEY(v)          BM_DCP_PACKET1_PAYLOAD_KEY
+#define BF_DCP_PACKET1_PAYLOAD_KEY_V(e)         BF_DCP_PACKET1_PAYLOAD_KEY(BV_DCP_PACKET1_PAYLOAD_KEY__##e)
+#define BFM_DCP_PACKET1_PAYLOAD_KEY_V(v)        BM_DCP_PACKET1_PAYLOAD_KEY
+#define BP_DCP_PACKET1_OTP_KEY                  10
+#define BM_DCP_PACKET1_OTP_KEY                  0x400
+#define BF_DCP_PACKET1_OTP_KEY(v)               (((v) & 0x1) << 10)
+#define BFM_DCP_PACKET1_OTP_KEY(v)              BM_DCP_PACKET1_OTP_KEY
+#define BF_DCP_PACKET1_OTP_KEY_V(e)             BF_DCP_PACKET1_OTP_KEY(BV_DCP_PACKET1_OTP_KEY__##e)
+#define BFM_DCP_PACKET1_OTP_KEY_V(v)            BM_DCP_PACKET1_OTP_KEY
+#define BP_DCP_PACKET1_CIPHER_INIT              9
+#define BM_DCP_PACKET1_CIPHER_INIT              0x200
+#define BF_DCP_PACKET1_CIPHER_INIT(v)           (((v) & 0x1) << 9)
+#define BFM_DCP_PACKET1_CIPHER_INIT(v)          BM_DCP_PACKET1_CIPHER_INIT
+#define BF_DCP_PACKET1_CIPHER_INIT_V(e)         BF_DCP_PACKET1_CIPHER_INIT(BV_DCP_PACKET1_CIPHER_INIT__##e)
+#define BFM_DCP_PACKET1_CIPHER_INIT_V(v)        BM_DCP_PACKET1_CIPHER_INIT
+#define BP_DCP_PACKET1_CIPHER_ENCRYPT           8
+#define BM_DCP_PACKET1_CIPHER_ENCRYPT           0x100
+#define BV_DCP_PACKET1_CIPHER_ENCRYPT__ENCRYPT  0x1
+#define BV_DCP_PACKET1_CIPHER_ENCRYPT__DECRYPT  0x0
+#define BF_DCP_PACKET1_CIPHER_ENCRYPT(v)        (((v) & 0x1) << 8)
+#define BFM_DCP_PACKET1_CIPHER_ENCRYPT(v)       BM_DCP_PACKET1_CIPHER_ENCRYPT
+#define BF_DCP_PACKET1_CIPHER_ENCRYPT_V(e)      BF_DCP_PACKET1_CIPHER_ENCRYPT(BV_DCP_PACKET1_CIPHER_ENCRYPT__##e)
+#define BFM_DCP_PACKET1_CIPHER_ENCRYPT_V(v)     BM_DCP_PACKET1_CIPHER_ENCRYPT
+#define BP_DCP_PACKET1_ENABLE_BLIT              7
+#define BM_DCP_PACKET1_ENABLE_BLIT              0x80
+#define BF_DCP_PACKET1_ENABLE_BLIT(v)           (((v) & 0x1) << 7)
+#define BFM_DCP_PACKET1_ENABLE_BLIT(v)          BM_DCP_PACKET1_ENABLE_BLIT
+#define BF_DCP_PACKET1_ENABLE_BLIT_V(e)         BF_DCP_PACKET1_ENABLE_BLIT(BV_DCP_PACKET1_ENABLE_BLIT__##e)
+#define BFM_DCP_PACKET1_ENABLE_BLIT_V(v)        BM_DCP_PACKET1_ENABLE_BLIT
+#define BP_DCP_PACKET1_ENABLE_HASH              6
+#define BM_DCP_PACKET1_ENABLE_HASH              0x40
+#define BF_DCP_PACKET1_ENABLE_HASH(v)           (((v) & 0x1) << 6)
+#define BFM_DCP_PACKET1_ENABLE_HASH(v)          BM_DCP_PACKET1_ENABLE_HASH
+#define BF_DCP_PACKET1_ENABLE_HASH_V(e)         BF_DCP_PACKET1_ENABLE_HASH(BV_DCP_PACKET1_ENABLE_HASH__##e)
+#define BFM_DCP_PACKET1_ENABLE_HASH_V(v)        BM_DCP_PACKET1_ENABLE_HASH
+#define BP_DCP_PACKET1_ENABLE_CIPHER            5
+#define BM_DCP_PACKET1_ENABLE_CIPHER            0x20
+#define BF_DCP_PACKET1_ENABLE_CIPHER(v)         (((v) & 0x1) << 5)
+#define BFM_DCP_PACKET1_ENABLE_CIPHER(v)        BM_DCP_PACKET1_ENABLE_CIPHER
+#define BF_DCP_PACKET1_ENABLE_CIPHER_V(e)       BF_DCP_PACKET1_ENABLE_CIPHER(BV_DCP_PACKET1_ENABLE_CIPHER__##e)
+#define BFM_DCP_PACKET1_ENABLE_CIPHER_V(v)      BM_DCP_PACKET1_ENABLE_CIPHER
+#define BP_DCP_PACKET1_ENABLE_MEMCOPY           4
+#define BM_DCP_PACKET1_ENABLE_MEMCOPY           0x10
+#define BF_DCP_PACKET1_ENABLE_MEMCOPY(v)        (((v) & 0x1) << 4)
+#define BFM_DCP_PACKET1_ENABLE_MEMCOPY(v)       BM_DCP_PACKET1_ENABLE_MEMCOPY
+#define BF_DCP_PACKET1_ENABLE_MEMCOPY_V(e)      BF_DCP_PACKET1_ENABLE_MEMCOPY(BV_DCP_PACKET1_ENABLE_MEMCOPY__##e)
+#define BFM_DCP_PACKET1_ENABLE_MEMCOPY_V(v)     BM_DCP_PACKET1_ENABLE_MEMCOPY
+#define BP_DCP_PACKET1_CHAIN_CONTIGUOUS         3
+#define BM_DCP_PACKET1_CHAIN_CONTIGUOUS         0x8
+#define BF_DCP_PACKET1_CHAIN_CONTIGUOUS(v)      (((v) & 0x1) << 3)
+#define BFM_DCP_PACKET1_CHAIN_CONTIGUOUS(v)     BM_DCP_PACKET1_CHAIN_CONTIGUOUS
+#define BF_DCP_PACKET1_CHAIN_CONTIGUOUS_V(e)    BF_DCP_PACKET1_CHAIN_CONTIGUOUS(BV_DCP_PACKET1_CHAIN_CONTIGUOUS__##e)
+#define BFM_DCP_PACKET1_CHAIN_CONTIGUOUS_V(v)   BM_DCP_PACKET1_CHAIN_CONTIGUOUS
+#define BP_DCP_PACKET1_CHAIN                    2
+#define BM_DCP_PACKET1_CHAIN                    0x4
+#define BF_DCP_PACKET1_CHAIN(v)                 (((v) & 0x1) << 2)
+#define BFM_DCP_PACKET1_CHAIN(v)                BM_DCP_PACKET1_CHAIN
+#define BF_DCP_PACKET1_CHAIN_V(e)               BF_DCP_PACKET1_CHAIN(BV_DCP_PACKET1_CHAIN__##e)
+#define BFM_DCP_PACKET1_CHAIN_V(v)              BM_DCP_PACKET1_CHAIN
+#define BP_DCP_PACKET1_DECR_SEMAPHORE           1
+#define BM_DCP_PACKET1_DECR_SEMAPHORE           0x2
+#define BF_DCP_PACKET1_DECR_SEMAPHORE(v)        (((v) & 0x1) << 1)
+#define BFM_DCP_PACKET1_DECR_SEMAPHORE(v)       BM_DCP_PACKET1_DECR_SEMAPHORE
+#define BF_DCP_PACKET1_DECR_SEMAPHORE_V(e)      BF_DCP_PACKET1_DECR_SEMAPHORE(BV_DCP_PACKET1_DECR_SEMAPHORE__##e)
+#define BFM_DCP_PACKET1_DECR_SEMAPHORE_V(v)     BM_DCP_PACKET1_DECR_SEMAPHORE
+#define BP_DCP_PACKET1_INTERRUPT                0
+#define BM_DCP_PACKET1_INTERRUPT                0x1
+#define BF_DCP_PACKET1_INTERRUPT(v)             (((v) & 0x1) << 0)
+#define BFM_DCP_PACKET1_INTERRUPT(v)            BM_DCP_PACKET1_INTERRUPT
+#define BF_DCP_PACKET1_INTERRUPT_V(e)           BF_DCP_PACKET1_INTERRUPT(BV_DCP_PACKET1_INTERRUPT__##e)
+#define BFM_DCP_PACKET1_INTERRUPT_V(v)          BM_DCP_PACKET1_INTERRUPT
+
+#define HW_DCP_PACKET2                          HW(DCP_PACKET2)
+#define HWA_DCP_PACKET2                         (0x80028000 + 0xa0)
+#define HWT_DCP_PACKET2                         HWIO_32_RW
+#define HWN_DCP_PACKET2                         DCP_PACKET2
+#define HWI_DCP_PACKET2                         
+#define BP_DCP_PACKET2_CIPHER_CFG               24
+#define BM_DCP_PACKET2_CIPHER_CFG               0xff000000
+#define BF_DCP_PACKET2_CIPHER_CFG(v)            (((v) & 0xff) << 24)
+#define BFM_DCP_PACKET2_CIPHER_CFG(v)           BM_DCP_PACKET2_CIPHER_CFG
+#define BF_DCP_PACKET2_CIPHER_CFG_V(e)          BF_DCP_PACKET2_CIPHER_CFG(BV_DCP_PACKET2_CIPHER_CFG__##e)
+#define BFM_DCP_PACKET2_CIPHER_CFG_V(v)         BM_DCP_PACKET2_CIPHER_CFG
+#define BP_DCP_PACKET2_RSVD                     20
+#define BM_DCP_PACKET2_RSVD                     0xf00000
+#define BF_DCP_PACKET2_RSVD(v)                  (((v) & 0xf) << 20)
+#define BFM_DCP_PACKET2_RSVD(v)                 BM_DCP_PACKET2_RSVD
+#define BF_DCP_PACKET2_RSVD_V(e)                BF_DCP_PACKET2_RSVD(BV_DCP_PACKET2_RSVD__##e)
+#define BFM_DCP_PACKET2_RSVD_V(v)               BM_DCP_PACKET2_RSVD
+#define BP_DCP_PACKET2_HASH_SELECT              16
+#define BM_DCP_PACKET2_HASH_SELECT              0xf0000
+#define BV_DCP_PACKET2_HASH_SELECT__SHA1        0x0
+#define BV_DCP_PACKET2_HASH_SELECT__CRC32       0x1
+#define BF_DCP_PACKET2_HASH_SELECT(v)           (((v) & 0xf) << 16)
+#define BFM_DCP_PACKET2_HASH_SELECT(v)          BM_DCP_PACKET2_HASH_SELECT
+#define BF_DCP_PACKET2_HASH_SELECT_V(e)         BF_DCP_PACKET2_HASH_SELECT(BV_DCP_PACKET2_HASH_SELECT__##e)
+#define BFM_DCP_PACKET2_HASH_SELECT_V(v)        BM_DCP_PACKET2_HASH_SELECT
+#define BP_DCP_PACKET2_KEY_SELECT               8
+#define BM_DCP_PACKET2_KEY_SELECT               0xff00
+#define BF_DCP_PACKET2_KEY_SELECT(v)            (((v) & 0xff) << 8)
+#define BFM_DCP_PACKET2_KEY_SELECT(v)           BM_DCP_PACKET2_KEY_SELECT
+#define BF_DCP_PACKET2_KEY_SELECT_V(e)          BF_DCP_PACKET2_KEY_SELECT(BV_DCP_PACKET2_KEY_SELECT__##e)
+#define BFM_DCP_PACKET2_KEY_SELECT_V(v)         BM_DCP_PACKET2_KEY_SELECT
+#define BP_DCP_PACKET2_CIPHER_MODE              4
+#define BM_DCP_PACKET2_CIPHER_MODE              0xf0
+#define BV_DCP_PACKET2_CIPHER_MODE__ECB         0x0
+#define BV_DCP_PACKET2_CIPHER_MODE__CBC         0x1
+#define BF_DCP_PACKET2_CIPHER_MODE(v)           (((v) & 0xf) << 4)
+#define BFM_DCP_PACKET2_CIPHER_MODE(v)          BM_DCP_PACKET2_CIPHER_MODE
+#define BF_DCP_PACKET2_CIPHER_MODE_V(e)         BF_DCP_PACKET2_CIPHER_MODE(BV_DCP_PACKET2_CIPHER_MODE__##e)
+#define BFM_DCP_PACKET2_CIPHER_MODE_V(v)        BM_DCP_PACKET2_CIPHER_MODE
+#define BP_DCP_PACKET2_CIPHER_SELECT            0
+#define BM_DCP_PACKET2_CIPHER_SELECT            0xf
+#define BV_DCP_PACKET2_CIPHER_SELECT__AES128    0x0
+#define BF_DCP_PACKET2_CIPHER_SELECT(v)         (((v) & 0xf) << 0)
+#define BFM_DCP_PACKET2_CIPHER_SELECT(v)        BM_DCP_PACKET2_CIPHER_SELECT
+#define BF_DCP_PACKET2_CIPHER_SELECT_V(e)       BF_DCP_PACKET2_CIPHER_SELECT(BV_DCP_PACKET2_CIPHER_SELECT__##e)
+#define BFM_DCP_PACKET2_CIPHER_SELECT_V(v)      BM_DCP_PACKET2_CIPHER_SELECT
+
+#define HW_DCP_PACKET3              HW(DCP_PACKET3)
+#define HWA_DCP_PACKET3             (0x80028000 + 0xb0)
+#define HWT_DCP_PACKET3             HWIO_32_RW
+#define HWN_DCP_PACKET3             DCP_PACKET3
+#define HWI_DCP_PACKET3             
+#define BP_DCP_PACKET3_ADDR         0
+#define BM_DCP_PACKET3_ADDR         0xffffffff
+#define BF_DCP_PACKET3_ADDR(v)      (((v) & 0xffffffff) << 0)
+#define BFM_DCP_PACKET3_ADDR(v)     BM_DCP_PACKET3_ADDR
+#define BF_DCP_PACKET3_ADDR_V(e)    BF_DCP_PACKET3_ADDR(BV_DCP_PACKET3_ADDR__##e)
+#define BFM_DCP_PACKET3_ADDR_V(v)   BM_DCP_PACKET3_ADDR
+
+#define HW_DCP_PACKET4              HW(DCP_PACKET4)
+#define HWA_DCP_PACKET4             (0x80028000 + 0xc0)
+#define HWT_DCP_PACKET4             HWIO_32_RW
+#define HWN_DCP_PACKET4             DCP_PACKET4
+#define HWI_DCP_PACKET4             
+#define BP_DCP_PACKET4_ADDR         0
+#define BM_DCP_PACKET4_ADDR         0xffffffff
+#define BF_DCP_PACKET4_ADDR(v)      (((v) & 0xffffffff) << 0)
+#define BFM_DCP_PACKET4_ADDR(v)     BM_DCP_PACKET4_ADDR
+#define BF_DCP_PACKET4_ADDR_V(e)    BF_DCP_PACKET4_ADDR(BV_DCP_PACKET4_ADDR__##e)
+#define BFM_DCP_PACKET4_ADDR_V(v)   BM_DCP_PACKET4_ADDR
+
+#define HW_DCP_PACKET5              HW(DCP_PACKET5)
+#define HWA_DCP_PACKET5             (0x80028000 + 0xd0)
+#define HWT_DCP_PACKET5             HWIO_32_RW
+#define HWN_DCP_PACKET5             DCP_PACKET5
+#define HWI_DCP_PACKET5             
+#define BP_DCP_PACKET5_COUNT        0
+#define BM_DCP_PACKET5_COUNT        0xffffffff
+#define BF_DCP_PACKET5_COUNT(v)     (((v) & 0xffffffff) << 0)
+#define BFM_DCP_PACKET5_COUNT(v)    BM_DCP_PACKET5_COUNT
+#define BF_DCP_PACKET5_COUNT_V(e)   BF_DCP_PACKET5_COUNT(BV_DCP_PACKET5_COUNT__##e)
+#define BFM_DCP_PACKET5_COUNT_V(v)  BM_DCP_PACKET5_COUNT
+
+#define HW_DCP_PACKET6              HW(DCP_PACKET6)
+#define HWA_DCP_PACKET6             (0x80028000 + 0xe0)
+#define HWT_DCP_PACKET6             HWIO_32_RW
+#define HWN_DCP_PACKET6             DCP_PACKET6
+#define HWI_DCP_PACKET6             
+#define BP_DCP_PACKET6_ADDR         0
+#define BM_DCP_PACKET6_ADDR         0xffffffff
+#define BF_DCP_PACKET6_ADDR(v)      (((v) & 0xffffffff) << 0)
+#define BFM_DCP_PACKET6_ADDR(v)     BM_DCP_PACKET6_ADDR
+#define BF_DCP_PACKET6_ADDR_V(e)    BF_DCP_PACKET6_ADDR(BV_DCP_PACKET6_ADDR__##e)
+#define BFM_DCP_PACKET6_ADDR_V(v)   BM_DCP_PACKET6_ADDR
+
+#define HW_DCP_CHnCMDPTR(_n1)       HW(DCP_CHnCMDPTR(_n1))
+#define HWA_DCP_CHnCMDPTR(_n1)      (0x80028000 + 0x100 + (_n1) * 0x40)
+#define HWT_DCP_CHnCMDPTR(_n1)      HWIO_32_RW
+#define HWN_DCP_CHnCMDPTR(_n1)      DCP_CHnCMDPTR
+#define HWI_DCP_CHnCMDPTR(_n1)      (_n1)
+#define BP_DCP_CHnCMDPTR_ADDR       0
+#define BM_DCP_CHnCMDPTR_ADDR       0xffffffff
+#define BF_DCP_CHnCMDPTR_ADDR(v)    (((v) & 0xffffffff) << 0)
+#define BFM_DCP_CHnCMDPTR_ADDR(v)   BM_DCP_CHnCMDPTR_ADDR
+#define BF_DCP_CHnCMDPTR_ADDR_V(e)  BF_DCP_CHnCMDPTR_ADDR(BV_DCP_CHnCMDPTR_ADDR__##e)
+#define BFM_DCP_CHnCMDPTR_ADDR_V(v) BM_DCP_CHnCMDPTR_ADDR
+
+#define HW_DCP_CHnSEMA(_n1)             HW(DCP_CHnSEMA(_n1))
+#define HWA_DCP_CHnSEMA(_n1)            (0x80028000 + 0x110 + (_n1) * 0x40)
+#define HWT_DCP_CHnSEMA(_n1)            HWIO_32_RW
+#define HWN_DCP_CHnSEMA(_n1)            DCP_CHnSEMA
+#define HWI_DCP_CHnSEMA(_n1)            (_n1)
+#define BP_DCP_CHnSEMA_RSVD2            24
+#define BM_DCP_CHnSEMA_RSVD2            0xff000000
+#define BF_DCP_CHnSEMA_RSVD2(v)         (((v) & 0xff) << 24)
+#define BFM_DCP_CHnSEMA_RSVD2(v)        BM_DCP_CHnSEMA_RSVD2
+#define BF_DCP_CHnSEMA_RSVD2_V(e)       BF_DCP_CHnSEMA_RSVD2(BV_DCP_CHnSEMA_RSVD2__##e)
+#define BFM_DCP_CHnSEMA_RSVD2_V(v)      BM_DCP_CHnSEMA_RSVD2
+#define BP_DCP_CHnSEMA_VALUE            16
+#define BM_DCP_CHnSEMA_VALUE            0xff0000
+#define BF_DCP_CHnSEMA_VALUE(v)         (((v) & 0xff) << 16)
+#define BFM_DCP_CHnSEMA_VALUE(v)        BM_DCP_CHnSEMA_VALUE
+#define BF_DCP_CHnSEMA_VALUE_V(e)       BF_DCP_CHnSEMA_VALUE(BV_DCP_CHnSEMA_VALUE__##e)
+#define BFM_DCP_CHnSEMA_VALUE_V(v)      BM_DCP_CHnSEMA_VALUE
+#define BP_DCP_CHnSEMA_RSVD1            8
+#define BM_DCP_CHnSEMA_RSVD1            0xff00
+#define BF_DCP_CHnSEMA_RSVD1(v)         (((v) & 0xff) << 8)
+#define BFM_DCP_CHnSEMA_RSVD1(v)        BM_DCP_CHnSEMA_RSVD1
+#define BF_DCP_CHnSEMA_RSVD1_V(e)       BF_DCP_CHnSEMA_RSVD1(BV_DCP_CHnSEMA_RSVD1__##e)
+#define BFM_DCP_CHnSEMA_RSVD1_V(v)      BM_DCP_CHnSEMA_RSVD1
+#define BP_DCP_CHnSEMA_INCREMENT        0
+#define BM_DCP_CHnSEMA_INCREMENT        0xff
+#define BF_DCP_CHnSEMA_INCREMENT(v)     (((v) & 0xff) << 0)
+#define BFM_DCP_CHnSEMA_INCREMENT(v)    BM_DCP_CHnSEMA_INCREMENT
+#define BF_DCP_CHnSEMA_INCREMENT_V(e)   BF_DCP_CHnSEMA_INCREMENT(BV_DCP_CHnSEMA_INCREMENT__##e)
+#define BFM_DCP_CHnSEMA_INCREMENT_V(v)  BM_DCP_CHnSEMA_INCREMENT
+
+#define HW_DCP_CHnSTAT(_n1)                         HW(DCP_CHnSTAT(_n1))
+#define HWA_DCP_CHnSTAT(_n1)                        (0x80028000 + 0x120 + (_n1) * 0x40)
+#define HWT_DCP_CHnSTAT(_n1)                        HWIO_32_RW
+#define HWN_DCP_CHnSTAT(_n1)                        DCP_CHnSTAT
+#define HWI_DCP_CHnSTAT(_n1)                        (_n1)
+#define HW_DCP_CHnSTAT_SET(_n1)                     HW(DCP_CHnSTAT_SET(_n1))
+#define HWA_DCP_CHnSTAT_SET(_n1)                    (HWA_DCP_CHnSTAT(_n1) + 0x4)
+#define HWT_DCP_CHnSTAT_SET(_n1)                    HWIO_32_WO
+#define HWN_DCP_CHnSTAT_SET(_n1)                    DCP_CHnSTAT
+#define HWI_DCP_CHnSTAT_SET(_n1)                    (_n1)
+#define HW_DCP_CHnSTAT_CLR(_n1)                     HW(DCP_CHnSTAT_CLR(_n1))
+#define HWA_DCP_CHnSTAT_CLR(_n1)                    (HWA_DCP_CHnSTAT(_n1) + 0x8)
+#define HWT_DCP_CHnSTAT_CLR(_n1)                    HWIO_32_WO
+#define HWN_DCP_CHnSTAT_CLR(_n1)                    DCP_CHnSTAT
+#define HWI_DCP_CHnSTAT_CLR(_n1)                    (_n1)
+#define HW_DCP_CHnSTAT_TOG(_n1)                     HW(DCP_CHnSTAT_TOG(_n1))
+#define HWA_DCP_CHnSTAT_TOG(_n1)                    (HWA_DCP_CHnSTAT(_n1) + 0xc)
+#define HWT_DCP_CHnSTAT_TOG(_n1)                    HWIO_32_WO
+#define HWN_DCP_CHnSTAT_TOG(_n1)                    DCP_CHnSTAT
+#define HWI_DCP_CHnSTAT_TOG(_n1)                    (_n1)
+#define BP_DCP_CHnSTAT_TAG                          24
+#define BM_DCP_CHnSTAT_TAG                          0xff000000
+#define BF_DCP_CHnSTAT_TAG(v)                       (((v) & 0xff) << 24)
+#define BFM_DCP_CHnSTAT_TAG(v)                      BM_DCP_CHnSTAT_TAG
+#define BF_DCP_CHnSTAT_TAG_V(e)                     BF_DCP_CHnSTAT_TAG(BV_DCP_CHnSTAT_TAG__##e)
+#define BFM_DCP_CHnSTAT_TAG_V(v)                    BM_DCP_CHnSTAT_TAG
+#define BP_DCP_CHnSTAT_ERROR_CODE                   16
+#define BM_DCP_CHnSTAT_ERROR_CODE                   0xff0000
+#define BV_DCP_CHnSTAT_ERROR_CODE__NEXT_CHAIN_IS_0  0x1
+#define BV_DCP_CHnSTAT_ERROR_CODE__NO_CHAIN         0x2
+#define BV_DCP_CHnSTAT_ERROR_CODE__CONTEXT_ERROR    0x3
+#define BV_DCP_CHnSTAT_ERROR_CODE__PAYLOAD_ERROR    0x4
+#define BV_DCP_CHnSTAT_ERROR_CODE__INVALID_MODE     0x5
+#define BF_DCP_CHnSTAT_ERROR_CODE(v)                (((v) & 0xff) << 16)
+#define BFM_DCP_CHnSTAT_ERROR_CODE(v)               BM_DCP_CHnSTAT_ERROR_CODE
+#define BF_DCP_CHnSTAT_ERROR_CODE_V(e)              BF_DCP_CHnSTAT_ERROR_CODE(BV_DCP_CHnSTAT_ERROR_CODE__##e)
+#define BFM_DCP_CHnSTAT_ERROR_CODE_V(v)             BM_DCP_CHnSTAT_ERROR_CODE
+#define BP_DCP_CHnSTAT_RSVD0                        7
+#define BM_DCP_CHnSTAT_RSVD0                        0xff80
+#define BF_DCP_CHnSTAT_RSVD0(v)                     (((v) & 0x1ff) << 7)
+#define BFM_DCP_CHnSTAT_RSVD0(v)                    BM_DCP_CHnSTAT_RSVD0
+#define BF_DCP_CHnSTAT_RSVD0_V(e)                   BF_DCP_CHnSTAT_RSVD0(BV_DCP_CHnSTAT_RSVD0__##e)
+#define BFM_DCP_CHnSTAT_RSVD0_V(v)                  BM_DCP_CHnSTAT_RSVD0
+#define BP_DCP_CHnSTAT_ERROR_PAGEFAULT              6
+#define BM_DCP_CHnSTAT_ERROR_PAGEFAULT              0x40
+#define BF_DCP_CHnSTAT_ERROR_PAGEFAULT(v)           (((v) & 0x1) << 6)
+#define BFM_DCP_CHnSTAT_ERROR_PAGEFAULT(v)          BM_DCP_CHnSTAT_ERROR_PAGEFAULT
+#define BF_DCP_CHnSTAT_ERROR_PAGEFAULT_V(e)         BF_DCP_CHnSTAT_ERROR_PAGEFAULT(BV_DCP_CHnSTAT_ERROR_PAGEFAULT__##e)
+#define BFM_DCP_CHnSTAT_ERROR_PAGEFAULT_V(v)        BM_DCP_CHnSTAT_ERROR_PAGEFAULT
+#define BP_DCP_CHnSTAT_ERROR_DST                    5
+#define BM_DCP_CHnSTAT_ERROR_DST                    0x20
+#define BF_DCP_CHnSTAT_ERROR_DST(v)                 (((v) & 0x1) << 5)
+#define BFM_DCP_CHnSTAT_ERROR_DST(v)                BM_DCP_CHnSTAT_ERROR_DST
+#define BF_DCP_CHnSTAT_ERROR_DST_V(e)               BF_DCP_CHnSTAT_ERROR_DST(BV_DCP_CHnSTAT_ERROR_DST__##e)
+#define BFM_DCP_CHnSTAT_ERROR_DST_V(v)              BM_DCP_CHnSTAT_ERROR_DST
+#define BP_DCP_CHnSTAT_ERROR_SRC                    4
+#define BM_DCP_CHnSTAT_ERROR_SRC                    0x10
+#define BF_DCP_CHnSTAT_ERROR_SRC(v)                 (((v) & 0x1) << 4)
+#define BFM_DCP_CHnSTAT_ERROR_SRC(v)                BM_DCP_CHnSTAT_ERROR_SRC
+#define BF_DCP_CHnSTAT_ERROR_SRC_V(e)               BF_DCP_CHnSTAT_ERROR_SRC(BV_DCP_CHnSTAT_ERROR_SRC__##e)
+#define BFM_DCP_CHnSTAT_ERROR_SRC_V(v)              BM_DCP_CHnSTAT_ERROR_SRC
+#define BP_DCP_CHnSTAT_ERROR_PACKET                 3
+#define BM_DCP_CHnSTAT_ERROR_PACKET                 0x8
+#define BF_DCP_CHnSTAT_ERROR_PACKET(v)              (((v) & 0x1) << 3)
+#define BFM_DCP_CHnSTAT_ERROR_PACKET(v)             BM_DCP_CHnSTAT_ERROR_PACKET
+#define BF_DCP_CHnSTAT_ERROR_PACKET_V(e)            BF_DCP_CHnSTAT_ERROR_PACKET(BV_DCP_CHnSTAT_ERROR_PACKET__##e)
+#define BFM_DCP_CHnSTAT_ERROR_PACKET_V(v)           BM_DCP_CHnSTAT_ERROR_PACKET
+#define BP_DCP_CHnSTAT_ERROR_SETUP                  2
+#define BM_DCP_CHnSTAT_ERROR_SETUP                  0x4
+#define BF_DCP_CHnSTAT_ERROR_SETUP(v)               (((v) & 0x1) << 2)
+#define BFM_DCP_CHnSTAT_ERROR_SETUP(v)              BM_DCP_CHnSTAT_ERROR_SETUP
+#define BF_DCP_CHnSTAT_ERROR_SETUP_V(e)             BF_DCP_CHnSTAT_ERROR_SETUP(BV_DCP_CHnSTAT_ERROR_SETUP__##e)
+#define BFM_DCP_CHnSTAT_ERROR_SETUP_V(v)            BM_DCP_CHnSTAT_ERROR_SETUP
+#define BP_DCP_CHnSTAT_HASH_MISMATCH                1
+#define BM_DCP_CHnSTAT_HASH_MISMATCH                0x2
+#define BF_DCP_CHnSTAT_HASH_MISMATCH(v)             (((v) & 0x1) << 1)
+#define BFM_DCP_CHnSTAT_HASH_MISMATCH(v)            BM_DCP_CHnSTAT_HASH_MISMATCH
+#define BF_DCP_CHnSTAT_HASH_MISMATCH_V(e)           BF_DCP_CHnSTAT_HASH_MISMATCH(BV_DCP_CHnSTAT_HASH_MISMATCH__##e)
+#define BFM_DCP_CHnSTAT_HASH_MISMATCH_V(v)          BM_DCP_CHnSTAT_HASH_MISMATCH
+#define BP_DCP_CHnSTAT_RSVD_COMPLETE                0
+#define BM_DCP_CHnSTAT_RSVD_COMPLETE                0x1
+#define BF_DCP_CHnSTAT_RSVD_COMPLETE(v)             (((v) & 0x1) << 0)
+#define BFM_DCP_CHnSTAT_RSVD_COMPLETE(v)            BM_DCP_CHnSTAT_RSVD_COMPLETE
+#define BF_DCP_CHnSTAT_RSVD_COMPLETE_V(e)           BF_DCP_CHnSTAT_RSVD_COMPLETE(BV_DCP_CHnSTAT_RSVD_COMPLETE__##e)
+#define BFM_DCP_CHnSTAT_RSVD_COMPLETE_V(v)          BM_DCP_CHnSTAT_RSVD_COMPLETE
+
+#define HW_DCP_CHnOPTS(_n1)                 HW(DCP_CHnOPTS(_n1))
+#define HWA_DCP_CHnOPTS(_n1)                (0x80028000 + 0x130 + (_n1) * 0x40)
+#define HWT_DCP_CHnOPTS(_n1)                HWIO_32_RW
+#define HWN_DCP_CHnOPTS(_n1)                DCP_CHnOPTS
+#define HWI_DCP_CHnOPTS(_n1)                (_n1)
+#define HW_DCP_CHnOPTS_SET(_n1)             HW(DCP_CHnOPTS_SET(_n1))
+#define HWA_DCP_CHnOPTS_SET(_n1)            (HWA_DCP_CHnOPTS(_n1) + 0x4)
+#define HWT_DCP_CHnOPTS_SET(_n1)            HWIO_32_WO
+#define HWN_DCP_CHnOPTS_SET(_n1)            DCP_CHnOPTS
+#define HWI_DCP_CHnOPTS_SET(_n1)            (_n1)
+#define HW_DCP_CHnOPTS_CLR(_n1)             HW(DCP_CHnOPTS_CLR(_n1))
+#define HWA_DCP_CHnOPTS_CLR(_n1)            (HWA_DCP_CHnOPTS(_n1) + 0x8)
+#define HWT_DCP_CHnOPTS_CLR(_n1)            HWIO_32_WO
+#define HWN_DCP_CHnOPTS_CLR(_n1)            DCP_CHnOPTS
+#define HWI_DCP_CHnOPTS_CLR(_n1)            (_n1)
+#define HW_DCP_CHnOPTS_TOG(_n1)             HW(DCP_CHnOPTS_TOG(_n1))
+#define HWA_DCP_CHnOPTS_TOG(_n1)            (HWA_DCP_CHnOPTS(_n1) + 0xc)
+#define HWT_DCP_CHnOPTS_TOG(_n1)            HWIO_32_WO
+#define HWN_DCP_CHnOPTS_TOG(_n1)            DCP_CHnOPTS
+#define HWI_DCP_CHnOPTS_TOG(_n1)            (_n1)
+#define BP_DCP_CHnOPTS_RSVD                 16
+#define BM_DCP_CHnOPTS_RSVD                 0xffff0000
+#define BF_DCP_CHnOPTS_RSVD(v)              (((v) & 0xffff) << 16)
+#define BFM_DCP_CHnOPTS_RSVD(v)             BM_DCP_CHnOPTS_RSVD
+#define BF_DCP_CHnOPTS_RSVD_V(e)            BF_DCP_CHnOPTS_RSVD(BV_DCP_CHnOPTS_RSVD__##e)
+#define BFM_DCP_CHnOPTS_RSVD_V(v)           BM_DCP_CHnOPTS_RSVD
+#define BP_DCP_CHnOPTS_RECOVERY_TIMER       0
+#define BM_DCP_CHnOPTS_RECOVERY_TIMER       0xffff
+#define BF_DCP_CHnOPTS_RECOVERY_TIMER(v)    (((v) & 0xffff) << 0)
+#define BFM_DCP_CHnOPTS_RECOVERY_TIMER(v)   BM_DCP_CHnOPTS_RECOVERY_TIMER
+#define BF_DCP_CHnOPTS_RECOVERY_TIMER_V(e)  BF_DCP_CHnOPTS_RECOVERY_TIMER(BV_DCP_CHnOPTS_RECOVERY_TIMER__##e)
+#define BFM_DCP_CHnOPTS_RECOVERY_TIMER_V(v) BM_DCP_CHnOPTS_RECOVERY_TIMER
+
+#define HW_DCP_CSCCTRL0                         HW(DCP_CSCCTRL0)
+#define HWA_DCP_CSCCTRL0                        (0x80028000 + 0x300)
+#define HWT_DCP_CSCCTRL0                        HWIO_32_RW
+#define HWN_DCP_CSCCTRL0                        DCP_CSCCTRL0
+#define HWI_DCP_CSCCTRL0                        
+#define HW_DCP_CSCCTRL0_SET                     HW(DCP_CSCCTRL0_SET)
+#define HWA_DCP_CSCCTRL0_SET                    (HWA_DCP_CSCCTRL0 + 0x4)
+#define HWT_DCP_CSCCTRL0_SET                    HWIO_32_WO
+#define HWN_DCP_CSCCTRL0_SET                    DCP_CSCCTRL0
+#define HWI_DCP_CSCCTRL0_SET                    
+#define HW_DCP_CSCCTRL0_CLR                     HW(DCP_CSCCTRL0_CLR)
+#define HWA_DCP_CSCCTRL0_CLR                    (HWA_DCP_CSCCTRL0 + 0x8)
+#define HWT_DCP_CSCCTRL0_CLR                    HWIO_32_WO
+#define HWN_DCP_CSCCTRL0_CLR                    DCP_CSCCTRL0
+#define HWI_DCP_CSCCTRL0_CLR                    
+#define HW_DCP_CSCCTRL0_TOG                     HW(DCP_CSCCTRL0_TOG)
+#define HWA_DCP_CSCCTRL0_TOG                    (HWA_DCP_CSCCTRL0 + 0xc)
+#define HWT_DCP_CSCCTRL0_TOG                    HWIO_32_WO
+#define HWN_DCP_CSCCTRL0_TOG                    DCP_CSCCTRL0
+#define HWI_DCP_CSCCTRL0_TOG                    
+#define BP_DCP_CSCCTRL0_RSVD1                   16
+#define BM_DCP_CSCCTRL0_RSVD1                   0xffff0000
+#define BF_DCP_CSCCTRL0_RSVD1(v)                (((v) & 0xffff) << 16)
+#define BFM_DCP_CSCCTRL0_RSVD1(v)               BM_DCP_CSCCTRL0_RSVD1
+#define BF_DCP_CSCCTRL0_RSVD1_V(e)              BF_DCP_CSCCTRL0_RSVD1(BV_DCP_CSCCTRL0_RSVD1__##e)
+#define BFM_DCP_CSCCTRL0_RSVD1_V(v)             BM_DCP_CSCCTRL0_RSVD1
+#define BP_DCP_CSCCTRL0_CLIP                    15
+#define BM_DCP_CSCCTRL0_CLIP                    0x8000
+#define BF_DCP_CSCCTRL0_CLIP(v)                 (((v) & 0x1) << 15)
+#define BFM_DCP_CSCCTRL0_CLIP(v)                BM_DCP_CSCCTRL0_CLIP
+#define BF_DCP_CSCCTRL0_CLIP_V(e)               BF_DCP_CSCCTRL0_CLIP(BV_DCP_CSCCTRL0_CLIP__##e)
+#define BFM_DCP_CSCCTRL0_CLIP_V(v)              BM_DCP_CSCCTRL0_CLIP
+#define BP_DCP_CSCCTRL0_UPSAMPLE                14
+#define BM_DCP_CSCCTRL0_UPSAMPLE                0x4000
+#define BF_DCP_CSCCTRL0_UPSAMPLE(v)             (((v) & 0x1) << 14)
+#define BFM_DCP_CSCCTRL0_UPSAMPLE(v)            BM_DCP_CSCCTRL0_UPSAMPLE
+#define BF_DCP_CSCCTRL0_UPSAMPLE_V(e)           BF_DCP_CSCCTRL0_UPSAMPLE(BV_DCP_CSCCTRL0_UPSAMPLE__##e)
+#define BFM_DCP_CSCCTRL0_UPSAMPLE_V(v)          BM_DCP_CSCCTRL0_UPSAMPLE
+#define BP_DCP_CSCCTRL0_SCALE                   13
+#define BM_DCP_CSCCTRL0_SCALE                   0x2000
+#define BF_DCP_CSCCTRL0_SCALE(v)                (((v) & 0x1) << 13)
+#define BFM_DCP_CSCCTRL0_SCALE(v)               BM_DCP_CSCCTRL0_SCALE
+#define BF_DCP_CSCCTRL0_SCALE_V(e)              BF_DCP_CSCCTRL0_SCALE(BV_DCP_CSCCTRL0_SCALE__##e)
+#define BFM_DCP_CSCCTRL0_SCALE_V(v)             BM_DCP_CSCCTRL0_SCALE
+#define BP_DCP_CSCCTRL0_ROTATE                  12
+#define BM_DCP_CSCCTRL0_ROTATE                  0x1000
+#define BF_DCP_CSCCTRL0_ROTATE(v)               (((v) & 0x1) << 12)
+#define BFM_DCP_CSCCTRL0_ROTATE(v)              BM_DCP_CSCCTRL0_ROTATE
+#define BF_DCP_CSCCTRL0_ROTATE_V(e)             BF_DCP_CSCCTRL0_ROTATE(BV_DCP_CSCCTRL0_ROTATE__##e)
+#define BFM_DCP_CSCCTRL0_ROTATE_V(v)            BM_DCP_CSCCTRL0_ROTATE
+#define BP_DCP_CSCCTRL0_SUBSAMPLE               11
+#define BM_DCP_CSCCTRL0_SUBSAMPLE               0x800
+#define BF_DCP_CSCCTRL0_SUBSAMPLE(v)            (((v) & 0x1) << 11)
+#define BFM_DCP_CSCCTRL0_SUBSAMPLE(v)           BM_DCP_CSCCTRL0_SUBSAMPLE
+#define BF_DCP_CSCCTRL0_SUBSAMPLE_V(e)          BF_DCP_CSCCTRL0_SUBSAMPLE(BV_DCP_CSCCTRL0_SUBSAMPLE__##e)
+#define BFM_DCP_CSCCTRL0_SUBSAMPLE_V(v)         BM_DCP_CSCCTRL0_SUBSAMPLE
+#define BP_DCP_CSCCTRL0_DELTA                   10
+#define BM_DCP_CSCCTRL0_DELTA                   0x400
+#define BF_DCP_CSCCTRL0_DELTA(v)                (((v) & 0x1) << 10)
+#define BFM_DCP_CSCCTRL0_DELTA(v)               BM_DCP_CSCCTRL0_DELTA
+#define BF_DCP_CSCCTRL0_DELTA_V(e)              BF_DCP_CSCCTRL0_DELTA(BV_DCP_CSCCTRL0_DELTA__##e)
+#define BFM_DCP_CSCCTRL0_DELTA_V(v)             BM_DCP_CSCCTRL0_DELTA
+#define BP_DCP_CSCCTRL0_RGB_FORMAT              8
+#define BM_DCP_CSCCTRL0_RGB_FORMAT              0x300
+#define BV_DCP_CSCCTRL0_RGB_FORMAT__RGB16_565   0x0
+#define BV_DCP_CSCCTRL0_RGB_FORMAT__YCbCrI      0x1
+#define BV_DCP_CSCCTRL0_RGB_FORMAT__RGB24       0x2
+#define BV_DCP_CSCCTRL0_RGB_FORMAT__YUV422I     0x3
+#define BF_DCP_CSCCTRL0_RGB_FORMAT(v)           (((v) & 0x3) << 8)
+#define BFM_DCP_CSCCTRL0_RGB_FORMAT(v)          BM_DCP_CSCCTRL0_RGB_FORMAT
+#define BF_DCP_CSCCTRL0_RGB_FORMAT_V(e)         BF_DCP_CSCCTRL0_RGB_FORMAT(BV_DCP_CSCCTRL0_RGB_FORMAT__##e)
+#define BFM_DCP_CSCCTRL0_RGB_FORMAT_V(v)        BM_DCP_CSCCTRL0_RGB_FORMAT
+#define BP_DCP_CSCCTRL0_YUV_FORMAT              4
+#define BM_DCP_CSCCTRL0_YUV_FORMAT              0xf0
+#define BV_DCP_CSCCTRL0_YUV_FORMAT__YUV420      0x0
+#define BV_DCP_CSCCTRL0_YUV_FORMAT__YUV422      0x2
+#define BF_DCP_CSCCTRL0_YUV_FORMAT(v)           (((v) & 0xf) << 4)
+#define BFM_DCP_CSCCTRL0_YUV_FORMAT(v)          BM_DCP_CSCCTRL0_YUV_FORMAT
+#define BF_DCP_CSCCTRL0_YUV_FORMAT_V(e)         BF_DCP_CSCCTRL0_YUV_FORMAT(BV_DCP_CSCCTRL0_YUV_FORMAT__##e)
+#define BFM_DCP_CSCCTRL0_YUV_FORMAT_V(v)        BM_DCP_CSCCTRL0_YUV_FORMAT
+#define BP_DCP_CSCCTRL0_RSVD0                   1
+#define BM_DCP_CSCCTRL0_RSVD0                   0xe
+#define BF_DCP_CSCCTRL0_RSVD0(v)                (((v) & 0x7) << 1)
+#define BFM_DCP_CSCCTRL0_RSVD0(v)               BM_DCP_CSCCTRL0_RSVD0
+#define BF_DCP_CSCCTRL0_RSVD0_V(e)              BF_DCP_CSCCTRL0_RSVD0(BV_DCP_CSCCTRL0_RSVD0__##e)
+#define BFM_DCP_CSCCTRL0_RSVD0_V(v)             BM_DCP_CSCCTRL0_RSVD0
+#define BP_DCP_CSCCTRL0_ENABLE                  0
+#define BM_DCP_CSCCTRL0_ENABLE                  0x1
+#define BF_DCP_CSCCTRL0_ENABLE(v)               (((v) & 0x1) << 0)
+#define BFM_DCP_CSCCTRL0_ENABLE(v)              BM_DCP_CSCCTRL0_ENABLE
+#define BF_DCP_CSCCTRL0_ENABLE_V(e)             BF_DCP_CSCCTRL0_ENABLE(BV_DCP_CSCCTRL0_ENABLE__##e)
+#define BFM_DCP_CSCCTRL0_ENABLE_V(v)            BM_DCP_CSCCTRL0_ENABLE
+
+#define HW_DCP_CSCSTAT                                  HW(DCP_CSCSTAT)
+#define HWA_DCP_CSCSTAT                                 (0x80028000 + 0x310)
+#define HWT_DCP_CSCSTAT                                 HWIO_32_RW
+#define HWN_DCP_CSCSTAT                                 DCP_CSCSTAT
+#define HWI_DCP_CSCSTAT                                 
+#define HW_DCP_CSCSTAT_SET                              HW(DCP_CSCSTAT_SET)
+#define HWA_DCP_CSCSTAT_SET                             (HWA_DCP_CSCSTAT + 0x4)
+#define HWT_DCP_CSCSTAT_SET                             HWIO_32_WO
+#define HWN_DCP_CSCSTAT_SET                             DCP_CSCSTAT
+#define HWI_DCP_CSCSTAT_SET                             
+#define HW_DCP_CSCSTAT_CLR                              HW(DCP_CSCSTAT_CLR)
+#define HWA_DCP_CSCSTAT_CLR                             (HWA_DCP_CSCSTAT + 0x8)
+#define HWT_DCP_CSCSTAT_CLR                             HWIO_32_WO
+#define HWN_DCP_CSCSTAT_CLR                             DCP_CSCSTAT
+#define HWI_DCP_CSCSTAT_CLR                             
+#define HW_DCP_CSCSTAT_TOG                              HW(DCP_CSCSTAT_TOG)
+#define HWA_DCP_CSCSTAT_TOG                             (HWA_DCP_CSCSTAT + 0xc)
+#define HWT_DCP_CSCSTAT_TOG                             HWIO_32_WO
+#define HWN_DCP_CSCSTAT_TOG                             DCP_CSCSTAT
+#define HWI_DCP_CSCSTAT_TOG                             
+#define BP_DCP_CSCSTAT_RSVD3                            24
+#define BM_DCP_CSCSTAT_RSVD3                            0xff000000
+#define BF_DCP_CSCSTAT_RSVD3(v)                         (((v) & 0xff) << 24)
+#define BFM_DCP_CSCSTAT_RSVD3(v)                        BM_DCP_CSCSTAT_RSVD3
+#define BF_DCP_CSCSTAT_RSVD3_V(e)                       BF_DCP_CSCSTAT_RSVD3(BV_DCP_CSCSTAT_RSVD3__##e)
+#define BFM_DCP_CSCSTAT_RSVD3_V(v)                      BM_DCP_CSCSTAT_RSVD3
+#define BP_DCP_CSCSTAT_ERROR_CODE                       16
+#define BM_DCP_CSCSTAT_ERROR_CODE                       0xff0000
+#define BV_DCP_CSCSTAT_ERROR_CODE__LUMA0_FETCH_ERROR_Y0 0x1
+#define BV_DCP_CSCSTAT_ERROR_CODE__LUMA1_FETCH_ERROR_Y1 0x2
+#define BV_DCP_CSCSTAT_ERROR_CODE__CHROMA_FETCH_ERROR_U 0x3
+#define BV_DCP_CSCSTAT_ERROR_CODE__CHROMA_FETCH_ERROR_V 0x4
+#define BF_DCP_CSCSTAT_ERROR_CODE(v)                    (((v) & 0xff) << 16)
+#define BFM_DCP_CSCSTAT_ERROR_CODE(v)                   BM_DCP_CSCSTAT_ERROR_CODE
+#define BF_DCP_CSCSTAT_ERROR_CODE_V(e)                  BF_DCP_CSCSTAT_ERROR_CODE(BV_DCP_CSCSTAT_ERROR_CODE__##e)
+#define BFM_DCP_CSCSTAT_ERROR_CODE_V(v)                 BM_DCP_CSCSTAT_ERROR_CODE
+#define BP_DCP_CSCSTAT_RSVD2                            7
+#define BM_DCP_CSCSTAT_RSVD2                            0xff80
+#define BF_DCP_CSCSTAT_RSVD2(v)                         (((v) & 0x1ff) << 7)
+#define BFM_DCP_CSCSTAT_RSVD2(v)                        BM_DCP_CSCSTAT_RSVD2
+#define BF_DCP_CSCSTAT_RSVD2_V(e)                       BF_DCP_CSCSTAT_RSVD2(BV_DCP_CSCSTAT_RSVD2__##e)
+#define BFM_DCP_CSCSTAT_RSVD2_V(v)                      BM_DCP_CSCSTAT_RSVD2
+#define BP_DCP_CSCSTAT_ERROR_PAGEFAULT                  6
+#define BM_DCP_CSCSTAT_ERROR_PAGEFAULT                  0x40
+#define BF_DCP_CSCSTAT_ERROR_PAGEFAULT(v)               (((v) & 0x1) << 6)
+#define BFM_DCP_CSCSTAT_ERROR_PAGEFAULT(v)              BM_DCP_CSCSTAT_ERROR_PAGEFAULT
+#define BF_DCP_CSCSTAT_ERROR_PAGEFAULT_V(e)             BF_DCP_CSCSTAT_ERROR_PAGEFAULT(BV_DCP_CSCSTAT_ERROR_PAGEFAULT__##e)
+#define BFM_DCP_CSCSTAT_ERROR_PAGEFAULT_V(v)            BM_DCP_CSCSTAT_ERROR_PAGEFAULT
+#define BP_DCP_CSCSTAT_ERROR_DST                        5
+#define BM_DCP_CSCSTAT_ERROR_DST                        0x20
+#define BF_DCP_CSCSTAT_ERROR_DST(v)                     (((v) & 0x1) << 5)
+#define BFM_DCP_CSCSTAT_ERROR_DST(v)                    BM_DCP_CSCSTAT_ERROR_DST
+#define BF_DCP_CSCSTAT_ERROR_DST_V(e)                   BF_DCP_CSCSTAT_ERROR_DST(BV_DCP_CSCSTAT_ERROR_DST__##e)
+#define BFM_DCP_CSCSTAT_ERROR_DST_V(v)                  BM_DCP_CSCSTAT_ERROR_DST
+#define BP_DCP_CSCSTAT_ERROR_SRC                        4
+#define BM_DCP_CSCSTAT_ERROR_SRC                        0x10
+#define BF_DCP_CSCSTAT_ERROR_SRC(v)                     (((v) & 0x1) << 4)
+#define BFM_DCP_CSCSTAT_ERROR_SRC(v)                    BM_DCP_CSCSTAT_ERROR_SRC
+#define BF_DCP_CSCSTAT_ERROR_SRC_V(e)                   BF_DCP_CSCSTAT_ERROR_SRC(BV_DCP_CSCSTAT_ERROR_SRC__##e)
+#define BFM_DCP_CSCSTAT_ERROR_SRC_V(v)                  BM_DCP_CSCSTAT_ERROR_SRC
+#define BP_DCP_CSCSTAT_RSVD1                            3
+#define BM_DCP_CSCSTAT_RSVD1                            0x8
+#define BF_DCP_CSCSTAT_RSVD1(v)                         (((v) & 0x1) << 3)
+#define BFM_DCP_CSCSTAT_RSVD1(v)                        BM_DCP_CSCSTAT_RSVD1
+#define BF_DCP_CSCSTAT_RSVD1_V(e)                       BF_DCP_CSCSTAT_RSVD1(BV_DCP_CSCSTAT_RSVD1__##e)
+#define BFM_DCP_CSCSTAT_RSVD1_V(v)                      BM_DCP_CSCSTAT_RSVD1
+#define BP_DCP_CSCSTAT_ERROR_SETUP                      2
+#define BM_DCP_CSCSTAT_ERROR_SETUP                      0x4
+#define BF_DCP_CSCSTAT_ERROR_SETUP(v)                   (((v) & 0x1) << 2)
+#define BFM_DCP_CSCSTAT_ERROR_SETUP(v)                  BM_DCP_CSCSTAT_ERROR_SETUP
+#define BF_DCP_CSCSTAT_ERROR_SETUP_V(e)                 BF_DCP_CSCSTAT_ERROR_SETUP(BV_DCP_CSCSTAT_ERROR_SETUP__##e)
+#define BFM_DCP_CSCSTAT_ERROR_SETUP_V(v)                BM_DCP_CSCSTAT_ERROR_SETUP
+#define BP_DCP_CSCSTAT_RSVD0                            1
+#define BM_DCP_CSCSTAT_RSVD0                            0x2
+#define BF_DCP_CSCSTAT_RSVD0(v)                         (((v) & 0x1) << 1)
+#define BFM_DCP_CSCSTAT_RSVD0(v)                        BM_DCP_CSCSTAT_RSVD0
+#define BF_DCP_CSCSTAT_RSVD0_V(e)                       BF_DCP_CSCSTAT_RSVD0(BV_DCP_CSCSTAT_RSVD0__##e)
+#define BFM_DCP_CSCSTAT_RSVD0_V(v)                      BM_DCP_CSCSTAT_RSVD0
+#define BP_DCP_CSCSTAT_COMPLETE                         0
+#define BM_DCP_CSCSTAT_COMPLETE                         0x1
+#define BF_DCP_CSCSTAT_COMPLETE(v)                      (((v) & 0x1) << 0)
+#define BFM_DCP_CSCSTAT_COMPLETE(v)                     BM_DCP_CSCSTAT_COMPLETE
+#define BF_DCP_CSCSTAT_COMPLETE_V(e)                    BF_DCP_CSCSTAT_COMPLETE(BV_DCP_CSCSTAT_COMPLETE__##e)
+#define BFM_DCP_CSCSTAT_COMPLETE_V(v)                   BM_DCP_CSCSTAT_COMPLETE
+
+#define HW_DCP_CSCOUTBUFPARAM                   HW(DCP_CSCOUTBUFPARAM)
+#define HWA_DCP_CSCOUTBUFPARAM                  (0x80028000 + 0x320)
+#define HWT_DCP_CSCOUTBUFPARAM                  HWIO_32_RW
+#define HWN_DCP_CSCOUTBUFPARAM                  DCP_CSCOUTBUFPARAM
+#define HWI_DCP_CSCOUTBUFPARAM                  
+#define BP_DCP_CSCOUTBUFPARAM_RSVD1             24
+#define BM_DCP_CSCOUTBUFPARAM_RSVD1             0xff000000
+#define BF_DCP_CSCOUTBUFPARAM_RSVD1(v)          (((v) & 0xff) << 24)
+#define BFM_DCP_CSCOUTBUFPARAM_RSVD1(v)         BM_DCP_CSCOUTBUFPARAM_RSVD1
+#define BF_DCP_CSCOUTBUFPARAM_RSVD1_V(e)        BF_DCP_CSCOUTBUFPARAM_RSVD1(BV_DCP_CSCOUTBUFPARAM_RSVD1__##e)
+#define BFM_DCP_CSCOUTBUFPARAM_RSVD1_V(v)       BM_DCP_CSCOUTBUFPARAM_RSVD1
+#define BP_DCP_CSCOUTBUFPARAM_FIELD_SIZE        12
+#define BM_DCP_CSCOUTBUFPARAM_FIELD_SIZE        0xfff000
+#define BF_DCP_CSCOUTBUFPARAM_FIELD_SIZE(v)     (((v) & 0xfff) << 12)
+#define BFM_DCP_CSCOUTBUFPARAM_FIELD_SIZE(v)    BM_DCP_CSCOUTBUFPARAM_FIELD_SIZE
+#define BF_DCP_CSCOUTBUFPARAM_FIELD_SIZE_V(e)   BF_DCP_CSCOUTBUFPARAM_FIELD_SIZE(BV_DCP_CSCOUTBUFPARAM_FIELD_SIZE__##e)
+#define BFM_DCP_CSCOUTBUFPARAM_FIELD_SIZE_V(v)  BM_DCP_CSCOUTBUFPARAM_FIELD_SIZE
+#define BP_DCP_CSCOUTBUFPARAM_LINE_SIZE         0
+#define BM_DCP_CSCOUTBUFPARAM_LINE_SIZE         0xfff
+#define BF_DCP_CSCOUTBUFPARAM_LINE_SIZE(v)      (((v) & 0xfff) << 0)
+#define BFM_DCP_CSCOUTBUFPARAM_LINE_SIZE(v)     BM_DCP_CSCOUTBUFPARAM_LINE_SIZE
+#define BF_DCP_CSCOUTBUFPARAM_LINE_SIZE_V(e)    BF_DCP_CSCOUTBUFPARAM_LINE_SIZE(BV_DCP_CSCOUTBUFPARAM_LINE_SIZE__##e)
+#define BFM_DCP_CSCOUTBUFPARAM_LINE_SIZE_V(v)   BM_DCP_CSCOUTBUFPARAM_LINE_SIZE
+
+#define HW_DCP_CSCINBUFPARAM                    HW(DCP_CSCINBUFPARAM)
+#define HWA_DCP_CSCINBUFPARAM                   (0x80028000 + 0x330)
+#define HWT_DCP_CSCINBUFPARAM                   HWIO_32_RW
+#define HWN_DCP_CSCINBUFPARAM                   DCP_CSCINBUFPARAM
+#define HWI_DCP_CSCINBUFPARAM                   
+#define BP_DCP_CSCINBUFPARAM_RSVD1              12
+#define BM_DCP_CSCINBUFPARAM_RSVD1              0xfffff000
+#define BF_DCP_CSCINBUFPARAM_RSVD1(v)           (((v) & 0xfffff) << 12)
+#define BFM_DCP_CSCINBUFPARAM_RSVD1(v)          BM_DCP_CSCINBUFPARAM_RSVD1
+#define BF_DCP_CSCINBUFPARAM_RSVD1_V(e)         BF_DCP_CSCINBUFPARAM_RSVD1(BV_DCP_CSCINBUFPARAM_RSVD1__##e)
+#define BFM_DCP_CSCINBUFPARAM_RSVD1_V(v)        BM_DCP_CSCINBUFPARAM_RSVD1
+#define BP_DCP_CSCINBUFPARAM_LINE_SIZE          0
+#define BM_DCP_CSCINBUFPARAM_LINE_SIZE          0xfff
+#define BF_DCP_CSCINBUFPARAM_LINE_SIZE(v)       (((v) & 0xfff) << 0)
+#define BFM_DCP_CSCINBUFPARAM_LINE_SIZE(v)      BM_DCP_CSCINBUFPARAM_LINE_SIZE
+#define BF_DCP_CSCINBUFPARAM_LINE_SIZE_V(e)     BF_DCP_CSCINBUFPARAM_LINE_SIZE(BV_DCP_CSCINBUFPARAM_LINE_SIZE__##e)
+#define BFM_DCP_CSCINBUFPARAM_LINE_SIZE_V(v)    BM_DCP_CSCINBUFPARAM_LINE_SIZE
+
+#define HW_DCP_CSCRGB               HW(DCP_CSCRGB)
+#define HWA_DCP_CSCRGB              (0x80028000 + 0x340)
+#define HWT_DCP_CSCRGB              HWIO_32_RW
+#define HWN_DCP_CSCRGB              DCP_CSCRGB
+#define HWI_DCP_CSCRGB              
+#define BP_DCP_CSCRGB_ADDR          0
+#define BM_DCP_CSCRGB_ADDR          0xffffffff
+#define BF_DCP_CSCRGB_ADDR(v)       (((v) & 0xffffffff) << 0)
+#define BFM_DCP_CSCRGB_ADDR(v)      BM_DCP_CSCRGB_ADDR
+#define BF_DCP_CSCRGB_ADDR_V(e)     BF_DCP_CSCRGB_ADDR(BV_DCP_CSCRGB_ADDR__##e)
+#define BFM_DCP_CSCRGB_ADDR_V(v)    BM_DCP_CSCRGB_ADDR
+
+#define HW_DCP_CSCLUMA              HW(DCP_CSCLUMA)
+#define HWA_DCP_CSCLUMA             (0x80028000 + 0x350)
+#define HWT_DCP_CSCLUMA             HWIO_32_RW
+#define HWN_DCP_CSCLUMA             DCP_CSCLUMA
+#define HWI_DCP_CSCLUMA             
+#define BP_DCP_CSCLUMA_ADDR         0
+#define BM_DCP_CSCLUMA_ADDR         0xffffffff
+#define BF_DCP_CSCLUMA_ADDR(v)      (((v) & 0xffffffff) << 0)
+#define BFM_DCP_CSCLUMA_ADDR(v)     BM_DCP_CSCLUMA_ADDR
+#define BF_DCP_CSCLUMA_ADDR_V(e)    BF_DCP_CSCLUMA_ADDR(BV_DCP_CSCLUMA_ADDR__##e)
+#define BFM_DCP_CSCLUMA_ADDR_V(v)   BM_DCP_CSCLUMA_ADDR
+
+#define HW_DCP_CSCCHROMAU               HW(DCP_CSCCHROMAU)
+#define HWA_DCP_CSCCHROMAU              (0x80028000 + 0x360)
+#define HWT_DCP_CSCCHROMAU              HWIO_32_RW
+#define HWN_DCP_CSCCHROMAU              DCP_CSCCHROMAU
+#define HWI_DCP_CSCCHROMAU              
+#define BP_DCP_CSCCHROMAU_ADDR          0
+#define BM_DCP_CSCCHROMAU_ADDR          0xffffffff
+#define BF_DCP_CSCCHROMAU_ADDR(v)       (((v) & 0xffffffff) << 0)
+#define BFM_DCP_CSCCHROMAU_ADDR(v)      BM_DCP_CSCCHROMAU_ADDR
+#define BF_DCP_CSCCHROMAU_ADDR_V(e)     BF_DCP_CSCCHROMAU_ADDR(BV_DCP_CSCCHROMAU_ADDR__##e)
+#define BFM_DCP_CSCCHROMAU_ADDR_V(v)    BM_DCP_CSCCHROMAU_ADDR
+
+#define HW_DCP_CSCCHROMAV               HW(DCP_CSCCHROMAV)
+#define HWA_DCP_CSCCHROMAV              (0x80028000 + 0x370)
+#define HWT_DCP_CSCCHROMAV              HWIO_32_RW
+#define HWN_DCP_CSCCHROMAV              DCP_CSCCHROMAV
+#define HWI_DCP_CSCCHROMAV              
+#define BP_DCP_CSCCHROMAV_ADDR          0
+#define BM_DCP_CSCCHROMAV_ADDR          0xffffffff
+#define BF_DCP_CSCCHROMAV_ADDR(v)       (((v) & 0xffffffff) << 0)
+#define BFM_DCP_CSCCHROMAV_ADDR(v)      BM_DCP_CSCCHROMAV_ADDR
+#define BF_DCP_CSCCHROMAV_ADDR_V(e)     BF_DCP_CSCCHROMAV_ADDR(BV_DCP_CSCCHROMAV_ADDR__##e)
+#define BFM_DCP_CSCCHROMAV_ADDR_V(v)    BM_DCP_CSCCHROMAV_ADDR
+
+#define HW_DCP_CSCCOEFF0                    HW(DCP_CSCCOEFF0)
+#define HWA_DCP_CSCCOEFF0                   (0x80028000 + 0x380)
+#define HWT_DCP_CSCCOEFF0                   HWIO_32_RW
+#define HWN_DCP_CSCCOEFF0                   DCP_CSCCOEFF0
+#define HWI_DCP_CSCCOEFF0                   
+#define BP_DCP_CSCCOEFF0_RSVD1              26
+#define BM_DCP_CSCCOEFF0_RSVD1              0xfc000000
+#define BF_DCP_CSCCOEFF0_RSVD1(v)           (((v) & 0x3f) << 26)
+#define BFM_DCP_CSCCOEFF0_RSVD1(v)          BM_DCP_CSCCOEFF0_RSVD1
+#define BF_DCP_CSCCOEFF0_RSVD1_V(e)         BF_DCP_CSCCOEFF0_RSVD1(BV_DCP_CSCCOEFF0_RSVD1__##e)
+#define BFM_DCP_CSCCOEFF0_RSVD1_V(v)        BM_DCP_CSCCOEFF0_RSVD1
+#define BP_DCP_CSCCOEFF0_C0                 16
+#define BM_DCP_CSCCOEFF0_C0                 0x3ff0000
+#define BF_DCP_CSCCOEFF0_C0(v)              (((v) & 0x3ff) << 16)
+#define BFM_DCP_CSCCOEFF0_C0(v)             BM_DCP_CSCCOEFF0_C0
+#define BF_DCP_CSCCOEFF0_C0_V(e)            BF_DCP_CSCCOEFF0_C0(BV_DCP_CSCCOEFF0_C0__##e)
+#define BFM_DCP_CSCCOEFF0_C0_V(v)           BM_DCP_CSCCOEFF0_C0
+#define BP_DCP_CSCCOEFF0_UV_OFFSET          8
+#define BM_DCP_CSCCOEFF0_UV_OFFSET          0xff00
+#define BF_DCP_CSCCOEFF0_UV_OFFSET(v)       (((v) & 0xff) << 8)
+#define BFM_DCP_CSCCOEFF0_UV_OFFSET(v)      BM_DCP_CSCCOEFF0_UV_OFFSET
+#define BF_DCP_CSCCOEFF0_UV_OFFSET_V(e)     BF_DCP_CSCCOEFF0_UV_OFFSET(BV_DCP_CSCCOEFF0_UV_OFFSET__##e)
+#define BFM_DCP_CSCCOEFF0_UV_OFFSET_V(v)    BM_DCP_CSCCOEFF0_UV_OFFSET
+#define BP_DCP_CSCCOEFF0_Y_OFFSET           0
+#define BM_DCP_CSCCOEFF0_Y_OFFSET           0xff
+#define BF_DCP_CSCCOEFF0_Y_OFFSET(v)        (((v) & 0xff) << 0)
+#define BFM_DCP_CSCCOEFF0_Y_OFFSET(v)       BM_DCP_CSCCOEFF0_Y_OFFSET
+#define BF_DCP_CSCCOEFF0_Y_OFFSET_V(e)      BF_DCP_CSCCOEFF0_Y_OFFSET(BV_DCP_CSCCOEFF0_Y_OFFSET__##e)
+#define BFM_DCP_CSCCOEFF0_Y_OFFSET_V(v)     BM_DCP_CSCCOEFF0_Y_OFFSET
+
+#define HW_DCP_CSCCOEFF1                HW(DCP_CSCCOEFF1)
+#define HWA_DCP_CSCCOEFF1               (0x80028000 + 0x390)
+#define HWT_DCP_CSCCOEFF1               HWIO_32_RW
+#define HWN_DCP_CSCCOEFF1               DCP_CSCCOEFF1
+#define HWI_DCP_CSCCOEFF1               
+#define BP_DCP_CSCCOEFF1_RSVD1          26
+#define BM_DCP_CSCCOEFF1_RSVD1          0xfc000000
+#define BF_DCP_CSCCOEFF1_RSVD1(v)       (((v) & 0x3f) << 26)
+#define BFM_DCP_CSCCOEFF1_RSVD1(v)      BM_DCP_CSCCOEFF1_RSVD1
+#define BF_DCP_CSCCOEFF1_RSVD1_V(e)     BF_DCP_CSCCOEFF1_RSVD1(BV_DCP_CSCCOEFF1_RSVD1__##e)
+#define BFM_DCP_CSCCOEFF1_RSVD1_V(v)    BM_DCP_CSCCOEFF1_RSVD1
+#define BP_DCP_CSCCOEFF1_C1             16
+#define BM_DCP_CSCCOEFF1_C1             0x3ff0000
+#define BF_DCP_CSCCOEFF1_C1(v)          (((v) & 0x3ff) << 16)
+#define BFM_DCP_CSCCOEFF1_C1(v)         BM_DCP_CSCCOEFF1_C1
+#define BF_DCP_CSCCOEFF1_C1_V(e)        BF_DCP_CSCCOEFF1_C1(BV_DCP_CSCCOEFF1_C1__##e)
+#define BFM_DCP_CSCCOEFF1_C1_V(v)       BM_DCP_CSCCOEFF1_C1
+#define BP_DCP_CSCCOEFF1_RSVD0          10
+#define BM_DCP_CSCCOEFF1_RSVD0          0xfc00
+#define BF_DCP_CSCCOEFF1_RSVD0(v)       (((v) & 0x3f) << 10)
+#define BFM_DCP_CSCCOEFF1_RSVD0(v)      BM_DCP_CSCCOEFF1_RSVD0
+#define BF_DCP_CSCCOEFF1_RSVD0_V(e)     BF_DCP_CSCCOEFF1_RSVD0(BV_DCP_CSCCOEFF1_RSVD0__##e)
+#define BFM_DCP_CSCCOEFF1_RSVD0_V(v)    BM_DCP_CSCCOEFF1_RSVD0
+#define BP_DCP_CSCCOEFF1_C4             0
+#define BM_DCP_CSCCOEFF1_C4             0x3ff
+#define BF_DCP_CSCCOEFF1_C4(v)          (((v) & 0x3ff) << 0)
+#define BFM_DCP_CSCCOEFF1_C4(v)         BM_DCP_CSCCOEFF1_C4
+#define BF_DCP_CSCCOEFF1_C4_V(e)        BF_DCP_CSCCOEFF1_C4(BV_DCP_CSCCOEFF1_C4__##e)
+#define BFM_DCP_CSCCOEFF1_C4_V(v)       BM_DCP_CSCCOEFF1_C4
+
+#define HW_DCP_CSCCOEFF2                HW(DCP_CSCCOEFF2)
+#define HWA_DCP_CSCCOEFF2               (0x80028000 + 0x3a0)
+#define HWT_DCP_CSCCOEFF2               HWIO_32_RW
+#define HWN_DCP_CSCCOEFF2               DCP_CSCCOEFF2
+#define HWI_DCP_CSCCOEFF2               
+#define BP_DCP_CSCCOEFF2_RSVD1          26
+#define BM_DCP_CSCCOEFF2_RSVD1          0xfc000000
+#define BF_DCP_CSCCOEFF2_RSVD1(v)       (((v) & 0x3f) << 26)
+#define BFM_DCP_CSCCOEFF2_RSVD1(v)      BM_DCP_CSCCOEFF2_RSVD1
+#define BF_DCP_CSCCOEFF2_RSVD1_V(e)     BF_DCP_CSCCOEFF2_RSVD1(BV_DCP_CSCCOEFF2_RSVD1__##e)
+#define BFM_DCP_CSCCOEFF2_RSVD1_V(v)    BM_DCP_CSCCOEFF2_RSVD1
+#define BP_DCP_CSCCOEFF2_C2             16
+#define BM_DCP_CSCCOEFF2_C2             0x3ff0000
+#define BF_DCP_CSCCOEFF2_C2(v)          (((v) & 0x3ff) << 16)
+#define BFM_DCP_CSCCOEFF2_C2(v)         BM_DCP_CSCCOEFF2_C2
+#define BF_DCP_CSCCOEFF2_C2_V(e)        BF_DCP_CSCCOEFF2_C2(BV_DCP_CSCCOEFF2_C2__##e)
+#define BFM_DCP_CSCCOEFF2_C2_V(v)       BM_DCP_CSCCOEFF2_C2
+#define BP_DCP_CSCCOEFF2_RSVD0          10
+#define BM_DCP_CSCCOEFF2_RSVD0          0xfc00
+#define BF_DCP_CSCCOEFF2_RSVD0(v)       (((v) & 0x3f) << 10)
+#define BFM_DCP_CSCCOEFF2_RSVD0(v)      BM_DCP_CSCCOEFF2_RSVD0
+#define BF_DCP_CSCCOEFF2_RSVD0_V(e)     BF_DCP_CSCCOEFF2_RSVD0(BV_DCP_CSCCOEFF2_RSVD0__##e)
+#define BFM_DCP_CSCCOEFF2_RSVD0_V(v)    BM_DCP_CSCCOEFF2_RSVD0
+#define BP_DCP_CSCCOEFF2_C3             0
+#define BM_DCP_CSCCOEFF2_C3             0x3ff
+#define BF_DCP_CSCCOEFF2_C3(v)          (((v) & 0x3ff) << 0)
+#define BFM_DCP_CSCCOEFF2_C3(v)         BM_DCP_CSCCOEFF2_C3
+#define BF_DCP_CSCCOEFF2_C3_V(e)        BF_DCP_CSCCOEFF2_C3(BV_DCP_CSCCOEFF2_C3__##e)
+#define BFM_DCP_CSCCOEFF2_C3_V(v)       BM_DCP_CSCCOEFF2_C3
+
+#define HW_DCP_CSCCLIP              HW(DCP_CSCCLIP)
+#define HWA_DCP_CSCCLIP             (0x80028000 + 0x3d0)
+#define HWT_DCP_CSCCLIP             HWIO_32_RW
+#define HWN_DCP_CSCCLIP             DCP_CSCCLIP
+#define HWI_DCP_CSCCLIP             
+#define BP_DCP_CSCCLIP_RSVD1        24
+#define BM_DCP_CSCCLIP_RSVD1        0xff000000
+#define BF_DCP_CSCCLIP_RSVD1(v)     (((v) & 0xff) << 24)
+#define BFM_DCP_CSCCLIP_RSVD1(v)    BM_DCP_CSCCLIP_RSVD1
+#define BF_DCP_CSCCLIP_RSVD1_V(e)   BF_DCP_CSCCLIP_RSVD1(BV_DCP_CSCCLIP_RSVD1__##e)
+#define BFM_DCP_CSCCLIP_RSVD1_V(v)  BM_DCP_CSCCLIP_RSVD1
+#define BP_DCP_CSCCLIP_HEIGHT       12
+#define BM_DCP_CSCCLIP_HEIGHT       0xfff000
+#define BF_DCP_CSCCLIP_HEIGHT(v)    (((v) & 0xfff) << 12)
+#define BFM_DCP_CSCCLIP_HEIGHT(v)   BM_DCP_CSCCLIP_HEIGHT
+#define BF_DCP_CSCCLIP_HEIGHT_V(e)  BF_DCP_CSCCLIP_HEIGHT(BV_DCP_CSCCLIP_HEIGHT__##e)
+#define BFM_DCP_CSCCLIP_HEIGHT_V(v) BM_DCP_CSCCLIP_HEIGHT
+#define BP_DCP_CSCCLIP_WIDTH        0
+#define BM_DCP_CSCCLIP_WIDTH        0xfff
+#define BF_DCP_CSCCLIP_WIDTH(v)     (((v) & 0xfff) << 0)
+#define BFM_DCP_CSCCLIP_WIDTH(v)    BM_DCP_CSCCLIP_WIDTH
+#define BF_DCP_CSCCLIP_WIDTH_V(e)   BF_DCP_CSCCLIP_WIDTH(BV_DCP_CSCCLIP_WIDTH__##e)
+#define BFM_DCP_CSCCLIP_WIDTH_V(v)  BM_DCP_CSCCLIP_WIDTH
+
+#define HW_DCP_CSCXSCALE                HW(DCP_CSCXSCALE)
+#define HWA_DCP_CSCXSCALE               (0x80028000 + 0x3e0)
+#define HWT_DCP_CSCXSCALE               HWIO_32_RW
+#define HWN_DCP_CSCXSCALE               DCP_CSCXSCALE
+#define HWI_DCP_CSCXSCALE               
+#define BP_DCP_CSCXSCALE_RSVD1          26
+#define BM_DCP_CSCXSCALE_RSVD1          0xfc000000
+#define BF_DCP_CSCXSCALE_RSVD1(v)       (((v) & 0x3f) << 26)
+#define BFM_DCP_CSCXSCALE_RSVD1(v)      BM_DCP_CSCXSCALE_RSVD1
+#define BF_DCP_CSCXSCALE_RSVD1_V(e)     BF_DCP_CSCXSCALE_RSVD1(BV_DCP_CSCXSCALE_RSVD1__##e)
+#define BFM_DCP_CSCXSCALE_RSVD1_V(v)    BM_DCP_CSCXSCALE_RSVD1
+#define BP_DCP_CSCXSCALE_INT            24
+#define BM_DCP_CSCXSCALE_INT            0x3000000
+#define BF_DCP_CSCXSCALE_INT(v)         (((v) & 0x3) << 24)
+#define BFM_DCP_CSCXSCALE_INT(v)        BM_DCP_CSCXSCALE_INT
+#define BF_DCP_CSCXSCALE_INT_V(e)       BF_DCP_CSCXSCALE_INT(BV_DCP_CSCXSCALE_INT__##e)
+#define BFM_DCP_CSCXSCALE_INT_V(v)      BM_DCP_CSCXSCALE_INT
+#define BP_DCP_CSCXSCALE_FRAC           12
+#define BM_DCP_CSCXSCALE_FRAC           0xfff000
+#define BF_DCP_CSCXSCALE_FRAC(v)        (((v) & 0xfff) << 12)
+#define BFM_DCP_CSCXSCALE_FRAC(v)       BM_DCP_CSCXSCALE_FRAC
+#define BF_DCP_CSCXSCALE_FRAC_V(e)      BF_DCP_CSCXSCALE_FRAC(BV_DCP_CSCXSCALE_FRAC__##e)
+#define BFM_DCP_CSCXSCALE_FRAC_V(v)     BM_DCP_CSCXSCALE_FRAC
+#define BP_DCP_CSCXSCALE_WIDTH          0
+#define BM_DCP_CSCXSCALE_WIDTH          0xfff
+#define BF_DCP_CSCXSCALE_WIDTH(v)       (((v) & 0xfff) << 0)
+#define BFM_DCP_CSCXSCALE_WIDTH(v)      BM_DCP_CSCXSCALE_WIDTH
+#define BF_DCP_CSCXSCALE_WIDTH_V(e)     BF_DCP_CSCXSCALE_WIDTH(BV_DCP_CSCXSCALE_WIDTH__##e)
+#define BFM_DCP_CSCXSCALE_WIDTH_V(v)    BM_DCP_CSCXSCALE_WIDTH
+
+#define HW_DCP_CSCYSCALE                HW(DCP_CSCYSCALE)
+#define HWA_DCP_CSCYSCALE               (0x80028000 + 0x3f0)
+#define HWT_DCP_CSCYSCALE               HWIO_32_RW
+#define HWN_DCP_CSCYSCALE               DCP_CSCYSCALE
+#define HWI_DCP_CSCYSCALE               
+#define BP_DCP_CSCYSCALE_RSVD1          26
+#define BM_DCP_CSCYSCALE_RSVD1          0xfc000000
+#define BF_DCP_CSCYSCALE_RSVD1(v)       (((v) & 0x3f) << 26)
+#define BFM_DCP_CSCYSCALE_RSVD1(v)      BM_DCP_CSCYSCALE_RSVD1
+#define BF_DCP_CSCYSCALE_RSVD1_V(e)     BF_DCP_CSCYSCALE_RSVD1(BV_DCP_CSCYSCALE_RSVD1__##e)
+#define BFM_DCP_CSCYSCALE_RSVD1_V(v)    BM_DCP_CSCYSCALE_RSVD1
+#define BP_DCP_CSCYSCALE_INT            24
+#define BM_DCP_CSCYSCALE_INT            0x3000000
+#define BF_DCP_CSCYSCALE_INT(v)         (((v) & 0x3) << 24)
+#define BFM_DCP_CSCYSCALE_INT(v)        BM_DCP_CSCYSCALE_INT
+#define BF_DCP_CSCYSCALE_INT_V(e)       BF_DCP_CSCYSCALE_INT(BV_DCP_CSCYSCALE_INT__##e)
+#define BFM_DCP_CSCYSCALE_INT_V(v)      BM_DCP_CSCYSCALE_INT
+#define BP_DCP_CSCYSCALE_FRAC           12
+#define BM_DCP_CSCYSCALE_FRAC           0xfff000
+#define BF_DCP_CSCYSCALE_FRAC(v)        (((v) & 0xfff) << 12)
+#define BFM_DCP_CSCYSCALE_FRAC(v)       BM_DCP_CSCYSCALE_FRAC
+#define BF_DCP_CSCYSCALE_FRAC_V(e)      BF_DCP_CSCYSCALE_FRAC(BV_DCP_CSCYSCALE_FRAC__##e)
+#define BFM_DCP_CSCYSCALE_FRAC_V(v)     BM_DCP_CSCYSCALE_FRAC
+#define BP_DCP_CSCYSCALE_HEIGHT         0
+#define BM_DCP_CSCYSCALE_HEIGHT         0xfff
+#define BF_DCP_CSCYSCALE_HEIGHT(v)      (((v) & 0xfff) << 0)
+#define BFM_DCP_CSCYSCALE_HEIGHT(v)     BM_DCP_CSCYSCALE_HEIGHT
+#define BF_DCP_CSCYSCALE_HEIGHT_V(e)    BF_DCP_CSCYSCALE_HEIGHT(BV_DCP_CSCYSCALE_HEIGHT__##e)
+#define BFM_DCP_CSCYSCALE_HEIGHT_V(v)   BM_DCP_CSCYSCALE_HEIGHT
+
+#define HW_DCP_DBGSELECT                HW(DCP_DBGSELECT)
+#define HWA_DCP_DBGSELECT               (0x80028000 + 0x400)
+#define HWT_DCP_DBGSELECT               HWIO_32_RW
+#define HWN_DCP_DBGSELECT               DCP_DBGSELECT
+#define HWI_DCP_DBGSELECT               
+#define BP_DCP_DBGSELECT_RSVD           8
+#define BM_DCP_DBGSELECT_RSVD           0xffffff00
+#define BF_DCP_DBGSELECT_RSVD(v)        (((v) & 0xffffff) << 8)
+#define BFM_DCP_DBGSELECT_RSVD(v)       BM_DCP_DBGSELECT_RSVD
+#define BF_DCP_DBGSELECT_RSVD_V(e)      BF_DCP_DBGSELECT_RSVD(BV_DCP_DBGSELECT_RSVD__##e)
+#define BFM_DCP_DBGSELECT_RSVD_V(v)     BM_DCP_DBGSELECT_RSVD
+#define BP_DCP_DBGSELECT_INDEX          0
+#define BM_DCP_DBGSELECT_INDEX          0xff
+#define BV_DCP_DBGSELECT_INDEX__CONTROL 0x1
+#define BV_DCP_DBGSELECT_INDEX__OTPKEY0 0x10
+#define BV_DCP_DBGSELECT_INDEX__OTPKEY1 0x11
+#define BV_DCP_DBGSELECT_INDEX__OTPKEY2 0x12
+#define BV_DCP_DBGSELECT_INDEX__OTPKEY3 0x13
+#define BF_DCP_DBGSELECT_INDEX(v)       (((v) & 0xff) << 0)
+#define BFM_DCP_DBGSELECT_INDEX(v)      BM_DCP_DBGSELECT_INDEX
+#define BF_DCP_DBGSELECT_INDEX_V(e)     BF_DCP_DBGSELECT_INDEX(BV_DCP_DBGSELECT_INDEX__##e)
+#define BFM_DCP_DBGSELECT_INDEX_V(v)    BM_DCP_DBGSELECT_INDEX
+
+#define HW_DCP_DBGDATA              HW(DCP_DBGDATA)
+#define HWA_DCP_DBGDATA             (0x80028000 + 0x410)
+#define HWT_DCP_DBGDATA             HWIO_32_RW
+#define HWN_DCP_DBGDATA             DCP_DBGDATA
+#define HWI_DCP_DBGDATA             
+#define BP_DCP_DBGDATA_DATA         0
+#define BM_DCP_DBGDATA_DATA         0xffffffff
+#define BF_DCP_DBGDATA_DATA(v)      (((v) & 0xffffffff) << 0)
+#define BFM_DCP_DBGDATA_DATA(v)     BM_DCP_DBGDATA_DATA
+#define BF_DCP_DBGDATA_DATA_V(e)    BF_DCP_DBGDATA_DATA(BV_DCP_DBGDATA_DATA__##e)
+#define BFM_DCP_DBGDATA_DATA_V(v)   BM_DCP_DBGDATA_DATA
+
+#define HW_DCP_PAGETABLE                HW(DCP_PAGETABLE)
+#define HWA_DCP_PAGETABLE               (0x80028000 + 0x420)
+#define HWT_DCP_PAGETABLE               HWIO_32_RW
+#define HWN_DCP_PAGETABLE               DCP_PAGETABLE
+#define HWI_DCP_PAGETABLE               
+#define BP_DCP_PAGETABLE_BASE           2
+#define BM_DCP_PAGETABLE_BASE           0xfffffffc
+#define BF_DCP_PAGETABLE_BASE(v)        (((v) & 0x3fffffff) << 2)
+#define BFM_DCP_PAGETABLE_BASE(v)       BM_DCP_PAGETABLE_BASE
+#define BF_DCP_PAGETABLE_BASE_V(e)      BF_DCP_PAGETABLE_BASE(BV_DCP_PAGETABLE_BASE__##e)
+#define BFM_DCP_PAGETABLE_BASE_V(v)     BM_DCP_PAGETABLE_BASE
+#define BP_DCP_PAGETABLE_FLUSH          1
+#define BM_DCP_PAGETABLE_FLUSH          0x2
+#define BF_DCP_PAGETABLE_FLUSH(v)       (((v) & 0x1) << 1)
+#define BFM_DCP_PAGETABLE_FLUSH(v)      BM_DCP_PAGETABLE_FLUSH
+#define BF_DCP_PAGETABLE_FLUSH_V(e)     BF_DCP_PAGETABLE_FLUSH(BV_DCP_PAGETABLE_FLUSH__##e)
+#define BFM_DCP_PAGETABLE_FLUSH_V(v)    BM_DCP_PAGETABLE_FLUSH
+#define BP_DCP_PAGETABLE_ENABLE         0
+#define BM_DCP_PAGETABLE_ENABLE         0x1
+#define BF_DCP_PAGETABLE_ENABLE(v)      (((v) & 0x1) << 0)
+#define BFM_DCP_PAGETABLE_ENABLE(v)     BM_DCP_PAGETABLE_ENABLE
+#define BF_DCP_PAGETABLE_ENABLE_V(e)    BF_DCP_PAGETABLE_ENABLE(BV_DCP_PAGETABLE_ENABLE__##e)
+#define BFM_DCP_PAGETABLE_ENABLE_V(v)   BM_DCP_PAGETABLE_ENABLE
+
+#define HW_DCP_VERSION              HW(DCP_VERSION)
+#define HWA_DCP_VERSION             (0x80028000 + 0x430)
+#define HWT_DCP_VERSION             HWIO_32_RW
+#define HWN_DCP_VERSION             DCP_VERSION
+#define HWI_DCP_VERSION             
+#define BP_DCP_VERSION_MAJOR        24
+#define BM_DCP_VERSION_MAJOR        0xff000000
+#define BF_DCP_VERSION_MAJOR(v)     (((v) & 0xff) << 24)
+#define BFM_DCP_VERSION_MAJOR(v)    BM_DCP_VERSION_MAJOR
+#define BF_DCP_VERSION_MAJOR_V(e)   BF_DCP_VERSION_MAJOR(BV_DCP_VERSION_MAJOR__##e)
+#define BFM_DCP_VERSION_MAJOR_V(v)  BM_DCP_VERSION_MAJOR
+#define BP_DCP_VERSION_MINOR        16
+#define BM_DCP_VERSION_MINOR        0xff0000
+#define BF_DCP_VERSION_MINOR(v)     (((v) & 0xff) << 16)
+#define BFM_DCP_VERSION_MINOR(v)    BM_DCP_VERSION_MINOR
+#define BF_DCP_VERSION_MINOR_V(e)   BF_DCP_VERSION_MINOR(BV_DCP_VERSION_MINOR__##e)
+#define BFM_DCP_VERSION_MINOR_V(v)  BM_DCP_VERSION_MINOR
+#define BP_DCP_VERSION_STEP         0
+#define BM_DCP_VERSION_STEP         0xffff
+#define BF_DCP_VERSION_STEP(v)      (((v) & 0xffff) << 0)
+#define BFM_DCP_VERSION_STEP(v)     BM_DCP_VERSION_STEP
+#define BF_DCP_VERSION_STEP_V(e)    BF_DCP_VERSION_STEP(BV_DCP_VERSION_STEP__##e)
+#define BFM_DCP_VERSION_STEP_V(v)   BM_DCP_VERSION_STEP
+
+#endif /* __HEADERGEN_IMX233_DCP_H__*/
diff --git a/firmware/target/arm/imx233/regs/imx233/digctl.h b/firmware/target/arm/imx233/regs/imx233/digctl.h
new file mode 100644
index 0000000000..d4bd27cf68
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/imx233/digctl.h
@@ -0,0 +1,1661 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * imx233 version: 2.4.0
+ * imx233 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_IMX233_DIGCTL_H__
+#define __HEADERGEN_IMX233_DIGCTL_H__
+
+#define HW_DIGCTL_CTRL                                      HW(DIGCTL_CTRL)
+#define HWA_DIGCTL_CTRL                                     (0x8001c000 + 0x0)
+#define HWT_DIGCTL_CTRL                                     HWIO_32_RW
+#define HWN_DIGCTL_CTRL                                     DIGCTL_CTRL
+#define HWI_DIGCTL_CTRL                                     
+#define HW_DIGCTL_CTRL_SET                                  HW(DIGCTL_CTRL_SET)
+#define HWA_DIGCTL_CTRL_SET                                 (HWA_DIGCTL_CTRL + 0x4)
+#define HWT_DIGCTL_CTRL_SET                                 HWIO_32_WO
+#define HWN_DIGCTL_CTRL_SET                                 DIGCTL_CTRL
+#define HWI_DIGCTL_CTRL_SET                                 
+#define HW_DIGCTL_CTRL_CLR                                  HW(DIGCTL_CTRL_CLR)
+#define HWA_DIGCTL_CTRL_CLR                                 (HWA_DIGCTL_CTRL + 0x8)
+#define HWT_DIGCTL_CTRL_CLR                                 HWIO_32_WO
+#define HWN_DIGCTL_CTRL_CLR                                 DIGCTL_CTRL
+#define HWI_DIGCTL_CTRL_CLR                                 
+#define HW_DIGCTL_CTRL_TOG                                  HW(DIGCTL_CTRL_TOG)
+#define HWA_DIGCTL_CTRL_TOG                                 (HWA_DIGCTL_CTRL + 0xc)
+#define HWT_DIGCTL_CTRL_TOG                                 HWIO_32_WO
+#define HWN_DIGCTL_CTRL_TOG                                 DIGCTL_CTRL
+#define HWI_DIGCTL_CTRL_TOG                                 
+#define BP_DIGCTL_CTRL_RSVD3                                31
+#define BM_DIGCTL_CTRL_RSVD3                                0x80000000
+#define BF_DIGCTL_CTRL_RSVD3(v)                             (((v) & 0x1) << 31)
+#define BFM_DIGCTL_CTRL_RSVD3(v)                            BM_DIGCTL_CTRL_RSVD3
+#define BF_DIGCTL_CTRL_RSVD3_V(e)                           BF_DIGCTL_CTRL_RSVD3(BV_DIGCTL_CTRL_RSVD3__##e)
+#define BFM_DIGCTL_CTRL_RSVD3_V(v)                          BM_DIGCTL_CTRL_RSVD3
+#define BP_DIGCTL_CTRL_XTAL24M_GATE                         30
+#define BM_DIGCTL_CTRL_XTAL24M_GATE                         0x40000000
+#define BF_DIGCTL_CTRL_XTAL24M_GATE(v)                      (((v) & 0x1) << 30)
+#define BFM_DIGCTL_CTRL_XTAL24M_GATE(v)                     BM_DIGCTL_CTRL_XTAL24M_GATE
+#define BF_DIGCTL_CTRL_XTAL24M_GATE_V(e)                    BF_DIGCTL_CTRL_XTAL24M_GATE(BV_DIGCTL_CTRL_XTAL24M_GATE__##e)
+#define BFM_DIGCTL_CTRL_XTAL24M_GATE_V(v)                   BM_DIGCTL_CTRL_XTAL24M_GATE
+#define BP_DIGCTL_CTRL_TRAP_IRQ                             29
+#define BM_DIGCTL_CTRL_TRAP_IRQ                             0x20000000
+#define BF_DIGCTL_CTRL_TRAP_IRQ(v)                          (((v) & 0x1) << 29)
+#define BFM_DIGCTL_CTRL_TRAP_IRQ(v)                         BM_DIGCTL_CTRL_TRAP_IRQ
+#define BF_DIGCTL_CTRL_TRAP_IRQ_V(e)                        BF_DIGCTL_CTRL_TRAP_IRQ(BV_DIGCTL_CTRL_TRAP_IRQ__##e)
+#define BFM_DIGCTL_CTRL_TRAP_IRQ_V(v)                       BM_DIGCTL_CTRL_TRAP_IRQ
+#define BP_DIGCTL_CTRL_RSVD2                                27
+#define BM_DIGCTL_CTRL_RSVD2                                0x18000000
+#define BF_DIGCTL_CTRL_RSVD2(v)                             (((v) & 0x3) << 27)
+#define BFM_DIGCTL_CTRL_RSVD2(v)                            BM_DIGCTL_CTRL_RSVD2
+#define BF_DIGCTL_CTRL_RSVD2_V(e)                           BF_DIGCTL_CTRL_RSVD2(BV_DIGCTL_CTRL_RSVD2__##e)
+#define BFM_DIGCTL_CTRL_RSVD2_V(v)                          BM_DIGCTL_CTRL_RSVD2
+#define BP_DIGCTL_CTRL_CACHE_BIST_TMODE                     26
+#define BM_DIGCTL_CTRL_CACHE_BIST_TMODE                     0x4000000
+#define BF_DIGCTL_CTRL_CACHE_BIST_TMODE(v)                  (((v) & 0x1) << 26)
+#define BFM_DIGCTL_CTRL_CACHE_BIST_TMODE(v)                 BM_DIGCTL_CTRL_CACHE_BIST_TMODE
+#define BF_DIGCTL_CTRL_CACHE_BIST_TMODE_V(e)                BF_DIGCTL_CTRL_CACHE_BIST_TMODE(BV_DIGCTL_CTRL_CACHE_BIST_TMODE__##e)
+#define BFM_DIGCTL_CTRL_CACHE_BIST_TMODE_V(v)               BM_DIGCTL_CTRL_CACHE_BIST_TMODE
+#define BP_DIGCTL_CTRL_LCD_BIST_CLKEN                       25
+#define BM_DIGCTL_CTRL_LCD_BIST_CLKEN                       0x2000000
+#define BF_DIGCTL_CTRL_LCD_BIST_CLKEN(v)                    (((v) & 0x1) << 25)
+#define BFM_DIGCTL_CTRL_LCD_BIST_CLKEN(v)                   BM_DIGCTL_CTRL_LCD_BIST_CLKEN
+#define BF_DIGCTL_CTRL_LCD_BIST_CLKEN_V(e)                  BF_DIGCTL_CTRL_LCD_BIST_CLKEN(BV_DIGCTL_CTRL_LCD_BIST_CLKEN__##e)
+#define BFM_DIGCTL_CTRL_LCD_BIST_CLKEN_V(v)                 BM_DIGCTL_CTRL_LCD_BIST_CLKEN
+#define BP_DIGCTL_CTRL_LCD_BIST_START                       24
+#define BM_DIGCTL_CTRL_LCD_BIST_START                       0x1000000
+#define BF_DIGCTL_CTRL_LCD_BIST_START(v)                    (((v) & 0x1) << 24)
+#define BFM_DIGCTL_CTRL_LCD_BIST_START(v)                   BM_DIGCTL_CTRL_LCD_BIST_START
+#define BF_DIGCTL_CTRL_LCD_BIST_START_V(e)                  BF_DIGCTL_CTRL_LCD_BIST_START(BV_DIGCTL_CTRL_LCD_BIST_START__##e)
+#define BFM_DIGCTL_CTRL_LCD_BIST_START_V(v)                 BM_DIGCTL_CTRL_LCD_BIST_START
+#define BP_DIGCTL_CTRL_DCP_BIST_CLKEN                       23
+#define BM_DIGCTL_CTRL_DCP_BIST_CLKEN                       0x800000
+#define BF_DIGCTL_CTRL_DCP_BIST_CLKEN(v)                    (((v) & 0x1) << 23)
+#define BFM_DIGCTL_CTRL_DCP_BIST_CLKEN(v)                   BM_DIGCTL_CTRL_DCP_BIST_CLKEN
+#define BF_DIGCTL_CTRL_DCP_BIST_CLKEN_V(e)                  BF_DIGCTL_CTRL_DCP_BIST_CLKEN(BV_DIGCTL_CTRL_DCP_BIST_CLKEN__##e)
+#define BFM_DIGCTL_CTRL_DCP_BIST_CLKEN_V(v)                 BM_DIGCTL_CTRL_DCP_BIST_CLKEN
+#define BP_DIGCTL_CTRL_DCP_BIST_START                       22
+#define BM_DIGCTL_CTRL_DCP_BIST_START                       0x400000
+#define BF_DIGCTL_CTRL_DCP_BIST_START(v)                    (((v) & 0x1) << 22)
+#define BFM_DIGCTL_CTRL_DCP_BIST_START(v)                   BM_DIGCTL_CTRL_DCP_BIST_START
+#define BF_DIGCTL_CTRL_DCP_BIST_START_V(e)                  BF_DIGCTL_CTRL_DCP_BIST_START(BV_DIGCTL_CTRL_DCP_BIST_START__##e)
+#define BFM_DIGCTL_CTRL_DCP_BIST_START_V(v)                 BM_DIGCTL_CTRL_DCP_BIST_START
+#define BP_DIGCTL_CTRL_ARM_BIST_CLKEN                       21
+#define BM_DIGCTL_CTRL_ARM_BIST_CLKEN                       0x200000
+#define BF_DIGCTL_CTRL_ARM_BIST_CLKEN(v)                    (((v) & 0x1) << 21)
+#define BFM_DIGCTL_CTRL_ARM_BIST_CLKEN(v)                   BM_DIGCTL_CTRL_ARM_BIST_CLKEN
+#define BF_DIGCTL_CTRL_ARM_BIST_CLKEN_V(e)                  BF_DIGCTL_CTRL_ARM_BIST_CLKEN(BV_DIGCTL_CTRL_ARM_BIST_CLKEN__##e)
+#define BFM_DIGCTL_CTRL_ARM_BIST_CLKEN_V(v)                 BM_DIGCTL_CTRL_ARM_BIST_CLKEN
+#define BP_DIGCTL_CTRL_USB_TESTMODE                         20
+#define BM_DIGCTL_CTRL_USB_TESTMODE                         0x100000
+#define BF_DIGCTL_CTRL_USB_TESTMODE(v)                      (((v) & 0x1) << 20)
+#define BFM_DIGCTL_CTRL_USB_TESTMODE(v)                     BM_DIGCTL_CTRL_USB_TESTMODE
+#define BF_DIGCTL_CTRL_USB_TESTMODE_V(e)                    BF_DIGCTL_CTRL_USB_TESTMODE(BV_DIGCTL_CTRL_USB_TESTMODE__##e)
+#define BFM_DIGCTL_CTRL_USB_TESTMODE_V(v)                   BM_DIGCTL_CTRL_USB_TESTMODE
+#define BP_DIGCTL_CTRL_ANALOG_TESTMODE                      19
+#define BM_DIGCTL_CTRL_ANALOG_TESTMODE                      0x80000
+#define BF_DIGCTL_CTRL_ANALOG_TESTMODE(v)                   (((v) & 0x1) << 19)
+#define BFM_DIGCTL_CTRL_ANALOG_TESTMODE(v)                  BM_DIGCTL_CTRL_ANALOG_TESTMODE
+#define BF_DIGCTL_CTRL_ANALOG_TESTMODE_V(e)                 BF_DIGCTL_CTRL_ANALOG_TESTMODE(BV_DIGCTL_CTRL_ANALOG_TESTMODE__##e)
+#define BFM_DIGCTL_CTRL_ANALOG_TESTMODE_V(v)                BM_DIGCTL_CTRL_ANALOG_TESTMODE
+#define BP_DIGCTL_CTRL_DIGITAL_TESTMODE                     18
+#define BM_DIGCTL_CTRL_DIGITAL_TESTMODE                     0x40000
+#define BF_DIGCTL_CTRL_DIGITAL_TESTMODE(v)                  (((v) & 0x1) << 18)
+#define BFM_DIGCTL_CTRL_DIGITAL_TESTMODE(v)                 BM_DIGCTL_CTRL_DIGITAL_TESTMODE
+#define BF_DIGCTL_CTRL_DIGITAL_TESTMODE_V(e)                BF_DIGCTL_CTRL_DIGITAL_TESTMODE(BV_DIGCTL_CTRL_DIGITAL_TESTMODE__##e)
+#define BFM_DIGCTL_CTRL_DIGITAL_TESTMODE_V(v)               BM_DIGCTL_CTRL_DIGITAL_TESTMODE
+#define BP_DIGCTL_CTRL_ARM_BIST_START                       17
+#define BM_DIGCTL_CTRL_ARM_BIST_START                       0x20000
+#define BF_DIGCTL_CTRL_ARM_BIST_START(v)                    (((v) & 0x1) << 17)
+#define BFM_DIGCTL_CTRL_ARM_BIST_START(v)                   BM_DIGCTL_CTRL_ARM_BIST_START
+#define BF_DIGCTL_CTRL_ARM_BIST_START_V(e)                  BF_DIGCTL_CTRL_ARM_BIST_START(BV_DIGCTL_CTRL_ARM_BIST_START__##e)
+#define BFM_DIGCTL_CTRL_ARM_BIST_START_V(v)                 BM_DIGCTL_CTRL_ARM_BIST_START
+#define BP_DIGCTL_CTRL_UART_LOOPBACK                        16
+#define BM_DIGCTL_CTRL_UART_LOOPBACK                        0x10000
+#define BV_DIGCTL_CTRL_UART_LOOPBACK__NORMAL                0x0
+#define BV_DIGCTL_CTRL_UART_LOOPBACK__LOOPIT                0x1
+#define BF_DIGCTL_CTRL_UART_LOOPBACK(v)                     (((v) & 0x1) << 16)
+#define BFM_DIGCTL_CTRL_UART_LOOPBACK(v)                    BM_DIGCTL_CTRL_UART_LOOPBACK
+#define BF_DIGCTL_CTRL_UART_LOOPBACK_V(e)                   BF_DIGCTL_CTRL_UART_LOOPBACK(BV_DIGCTL_CTRL_UART_LOOPBACK__##e)
+#define BFM_DIGCTL_CTRL_UART_LOOPBACK_V(v)                  BM_DIGCTL_CTRL_UART_LOOPBACK
+#define BP_DIGCTL_CTRL_SAIF_LOOPBACK                        15
+#define BM_DIGCTL_CTRL_SAIF_LOOPBACK                        0x8000
+#define BV_DIGCTL_CTRL_SAIF_LOOPBACK__NORMAL                0x0
+#define BV_DIGCTL_CTRL_SAIF_LOOPBACK__LOOPIT                0x1
+#define BF_DIGCTL_CTRL_SAIF_LOOPBACK(v)                     (((v) & 0x1) << 15)
+#define BFM_DIGCTL_CTRL_SAIF_LOOPBACK(v)                    BM_DIGCTL_CTRL_SAIF_LOOPBACK
+#define BF_DIGCTL_CTRL_SAIF_LOOPBACK_V(e)                   BF_DIGCTL_CTRL_SAIF_LOOPBACK(BV_DIGCTL_CTRL_SAIF_LOOPBACK__##e)
+#define BFM_DIGCTL_CTRL_SAIF_LOOPBACK_V(v)                  BM_DIGCTL_CTRL_SAIF_LOOPBACK
+#define BP_DIGCTL_CTRL_SAIF_CLKMUX_SEL                      13
+#define BM_DIGCTL_CTRL_SAIF_CLKMUX_SEL                      0x6000
+#define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__MBL_CLK_OUT         0x0
+#define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__BL_CLK_OUT          0x1
+#define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__M_CLK_OUT_BL_CLK_IN 0x2
+#define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__BL_CLK_IN           0x3
+#define BF_DIGCTL_CTRL_SAIF_CLKMUX_SEL(v)                   (((v) & 0x3) << 13)
+#define BFM_DIGCTL_CTRL_SAIF_CLKMUX_SEL(v)                  BM_DIGCTL_CTRL_SAIF_CLKMUX_SEL
+#define BF_DIGCTL_CTRL_SAIF_CLKMUX_SEL_V(e)                 BF_DIGCTL_CTRL_SAIF_CLKMUX_SEL(BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__##e)
+#define BFM_DIGCTL_CTRL_SAIF_CLKMUX_SEL_V(v)                BM_DIGCTL_CTRL_SAIF_CLKMUX_SEL
+#define BP_DIGCTL_CTRL_SAIF_CLKMST_SEL                      12
+#define BM_DIGCTL_CTRL_SAIF_CLKMST_SEL                      0x1000
+#define BV_DIGCTL_CTRL_SAIF_CLKMST_SEL__SAIF1_MST           0x0
+#define BV_DIGCTL_CTRL_SAIF_CLKMST_SEL__SAIF2_MST           0x1
+#define BF_DIGCTL_CTRL_SAIF_CLKMST_SEL(v)                   (((v) & 0x1) << 12)
+#define BFM_DIGCTL_CTRL_SAIF_CLKMST_SEL(v)                  BM_DIGCTL_CTRL_SAIF_CLKMST_SEL
+#define BF_DIGCTL_CTRL_SAIF_CLKMST_SEL_V(e)                 BF_DIGCTL_CTRL_SAIF_CLKMST_SEL(BV_DIGCTL_CTRL_SAIF_CLKMST_SEL__##e)
+#define BFM_DIGCTL_CTRL_SAIF_CLKMST_SEL_V(v)                BM_DIGCTL_CTRL_SAIF_CLKMST_SEL
+#define BP_DIGCTL_CTRL_SAIF_ALT_BITCLK_SEL                  11
+#define BM_DIGCTL_CTRL_SAIF_ALT_BITCLK_SEL                  0x800
+#define BF_DIGCTL_CTRL_SAIF_ALT_BITCLK_SEL(v)               (((v) & 0x1) << 11)
+#define BFM_DIGCTL_CTRL_SAIF_ALT_BITCLK_SEL(v)              BM_DIGCTL_CTRL_SAIF_ALT_BITCLK_SEL
+#define BF_DIGCTL_CTRL_SAIF_ALT_BITCLK_SEL_V(e)             BF_DIGCTL_CTRL_SAIF_ALT_BITCLK_SEL(BV_DIGCTL_CTRL_SAIF_ALT_BITCLK_SEL__##e)
+#define BFM_DIGCTL_CTRL_SAIF_ALT_BITCLK_SEL_V(v)            BM_DIGCTL_CTRL_SAIF_ALT_BITCLK_SEL
+#define BP_DIGCTL_CTRL_RSVD1                                10
+#define BM_DIGCTL_CTRL_RSVD1                                0x400
+#define BF_DIGCTL_CTRL_RSVD1(v)                             (((v) & 0x1) << 10)
+#define BFM_DIGCTL_CTRL_RSVD1(v)                            BM_DIGCTL_CTRL_RSVD1
+#define BF_DIGCTL_CTRL_RSVD1_V(e)                           BF_DIGCTL_CTRL_RSVD1(BV_DIGCTL_CTRL_RSVD1__##e)
+#define BFM_DIGCTL_CTRL_RSVD1_V(v)                          BM_DIGCTL_CTRL_RSVD1
+#define BP_DIGCTL_CTRL_SY_ENDIAN                            9
+#define BM_DIGCTL_CTRL_SY_ENDIAN                            0x200
+#define BF_DIGCTL_CTRL_SY_ENDIAN(v)                         (((v) & 0x1) << 9)
+#define BFM_DIGCTL_CTRL_SY_ENDIAN(v)                        BM_DIGCTL_CTRL_SY_ENDIAN
+#define BF_DIGCTL_CTRL_SY_ENDIAN_V(e)                       BF_DIGCTL_CTRL_SY_ENDIAN(BV_DIGCTL_CTRL_SY_ENDIAN__##e)
+#define BFM_DIGCTL_CTRL_SY_ENDIAN_V(v)                      BM_DIGCTL_CTRL_SY_ENDIAN
+#define BP_DIGCTL_CTRL_SY_SFTRST                            8
+#define BM_DIGCTL_CTRL_SY_SFTRST                            0x100
+#define BF_DIGCTL_CTRL_SY_SFTRST(v)                         (((v) & 0x1) << 8)
+#define BFM_DIGCTL_CTRL_SY_SFTRST(v)                        BM_DIGCTL_CTRL_SY_SFTRST
+#define BF_DIGCTL_CTRL_SY_SFTRST_V(e)                       BF_DIGCTL_CTRL_SY_SFTRST(BV_DIGCTL_CTRL_SY_SFTRST__##e)
+#define BFM_DIGCTL_CTRL_SY_SFTRST_V(v)                      BM_DIGCTL_CTRL_SY_SFTRST
+#define BP_DIGCTL_CTRL_SY_CLKGATE                           7
+#define BM_DIGCTL_CTRL_SY_CLKGATE                           0x80
+#define BF_DIGCTL_CTRL_SY_CLKGATE(v)                        (((v) & 0x1) << 7)
+#define BFM_DIGCTL_CTRL_SY_CLKGATE(v)                       BM_DIGCTL_CTRL_SY_CLKGATE
+#define BF_DIGCTL_CTRL_SY_CLKGATE_V(e)                      BF_DIGCTL_CTRL_SY_CLKGATE(BV_DIGCTL_CTRL_SY_CLKGATE__##e)
+#define BFM_DIGCTL_CTRL_SY_CLKGATE_V(v)                     BM_DIGCTL_CTRL_SY_CLKGATE
+#define BP_DIGCTL_CTRL_USE_SERIAL_JTAG                      6
+#define BM_DIGCTL_CTRL_USE_SERIAL_JTAG                      0x40
+#define BV_DIGCTL_CTRL_USE_SERIAL_JTAG__OLD_JTAG            0x0
+#define BV_DIGCTL_CTRL_USE_SERIAL_JTAG__SERIAL_JTAG         0x1
+#define BF_DIGCTL_CTRL_USE_SERIAL_JTAG(v)                   (((v) & 0x1) << 6)
+#define BFM_DIGCTL_CTRL_USE_SERIAL_JTAG(v)                  BM_DIGCTL_CTRL_USE_SERIAL_JTAG
+#define BF_DIGCTL_CTRL_USE_SERIAL_JTAG_V(e)                 BF_DIGCTL_CTRL_USE_SERIAL_JTAG(BV_DIGCTL_CTRL_USE_SERIAL_JTAG__##e)
+#define BFM_DIGCTL_CTRL_USE_SERIAL_JTAG_V(v)                BM_DIGCTL_CTRL_USE_SERIAL_JTAG
+#define BP_DIGCTL_CTRL_TRAP_IN_RANGE                        5
+#define BM_DIGCTL_CTRL_TRAP_IN_RANGE                        0x20
+#define BF_DIGCTL_CTRL_TRAP_IN_RANGE(v)                     (((v) & 0x1) << 5)
+#define BFM_DIGCTL_CTRL_TRAP_IN_RANGE(v)                    BM_DIGCTL_CTRL_TRAP_IN_RANGE
+#define BF_DIGCTL_CTRL_TRAP_IN_RANGE_V(e)                   BF_DIGCTL_CTRL_TRAP_IN_RANGE(BV_DIGCTL_CTRL_TRAP_IN_RANGE__##e)
+#define BFM_DIGCTL_CTRL_TRAP_IN_RANGE_V(v)                  BM_DIGCTL_CTRL_TRAP_IN_RANGE
+#define BP_DIGCTL_CTRL_TRAP_ENABLE                          4
+#define BM_DIGCTL_CTRL_TRAP_ENABLE                          0x10
+#define BF_DIGCTL_CTRL_TRAP_ENABLE(v)                       (((v) & 0x1) << 4)
+#define BFM_DIGCTL_CTRL_TRAP_ENABLE(v)                      BM_DIGCTL_CTRL_TRAP_ENABLE
+#define BF_DIGCTL_CTRL_TRAP_ENABLE_V(e)                     BF_DIGCTL_CTRL_TRAP_ENABLE(BV_DIGCTL_CTRL_TRAP_ENABLE__##e)
+#define BFM_DIGCTL_CTRL_TRAP_ENABLE_V(v)                    BM_DIGCTL_CTRL_TRAP_ENABLE
+#define BP_DIGCTL_CTRL_DEBUG_DISABLE                        3
+#define BM_DIGCTL_CTRL_DEBUG_DISABLE                        0x8
+#define BF_DIGCTL_CTRL_DEBUG_DISABLE(v)                     (((v) & 0x1) << 3)
+#define BFM_DIGCTL_CTRL_DEBUG_DISABLE(v)                    BM_DIGCTL_CTRL_DEBUG_DISABLE
+#define BF_DIGCTL_CTRL_DEBUG_DISABLE_V(e)                   BF_DIGCTL_CTRL_DEBUG_DISABLE(BV_DIGCTL_CTRL_DEBUG_DISABLE__##e)
+#define BFM_DIGCTL_CTRL_DEBUG_DISABLE_V(v)                  BM_DIGCTL_CTRL_DEBUG_DISABLE
+#define BP_DIGCTL_CTRL_USB_CLKGATE                          2
+#define BM_DIGCTL_CTRL_USB_CLKGATE                          0x4
+#define BV_DIGCTL_CTRL_USB_CLKGATE__RUN                     0x0
+#define BV_DIGCTL_CTRL_USB_CLKGATE__NO_CLKS                 0x1
+#define BF_DIGCTL_CTRL_USB_CLKGATE(v)                       (((v) & 0x1) << 2)
+#define BFM_DIGCTL_CTRL_USB_CLKGATE(v)                      BM_DIGCTL_CTRL_USB_CLKGATE
+#define BF_DIGCTL_CTRL_USB_CLKGATE_V(e)                     BF_DIGCTL_CTRL_USB_CLKGATE(BV_DIGCTL_CTRL_USB_CLKGATE__##e)
+#define BFM_DIGCTL_CTRL_USB_CLKGATE_V(v)                    BM_DIGCTL_CTRL_USB_CLKGATE
+#define BP_DIGCTL_CTRL_JTAG_SHIELD                          1
+#define BM_DIGCTL_CTRL_JTAG_SHIELD                          0x2
+#define BV_DIGCTL_CTRL_JTAG_SHIELD__NORMAL                  0x0
+#define BV_DIGCTL_CTRL_JTAG_SHIELD__SHIELDS_UP              0x1
+#define BF_DIGCTL_CTRL_JTAG_SHIELD(v)                       (((v) & 0x1) << 1)
+#define BFM_DIGCTL_CTRL_JTAG_SHIELD(v)                      BM_DIGCTL_CTRL_JTAG_SHIELD
+#define BF_DIGCTL_CTRL_JTAG_SHIELD_V(e)                     BF_DIGCTL_CTRL_JTAG_SHIELD(BV_DIGCTL_CTRL_JTAG_SHIELD__##e)
+#define BFM_DIGCTL_CTRL_JTAG_SHIELD_V(v)                    BM_DIGCTL_CTRL_JTAG_SHIELD
+#define BP_DIGCTL_CTRL_LATCH_ENTROPY                        0
+#define BM_DIGCTL_CTRL_LATCH_ENTROPY                        0x1
+#define BF_DIGCTL_CTRL_LATCH_ENTROPY(v)                     (((v) & 0x1) << 0)
+#define BFM_DIGCTL_CTRL_LATCH_ENTROPY(v)                    BM_DIGCTL_CTRL_LATCH_ENTROPY
+#define BF_DIGCTL_CTRL_LATCH_ENTROPY_V(e)                   BF_DIGCTL_CTRL_LATCH_ENTROPY(BV_DIGCTL_CTRL_LATCH_ENTROPY__##e)
+#define BFM_DIGCTL_CTRL_LATCH_ENTROPY_V(v)                  BM_DIGCTL_CTRL_LATCH_ENTROPY
+
+#define HW_DIGCTL_STATUS                            HW(DIGCTL_STATUS)
+#define HWA_DIGCTL_STATUS                           (0x8001c000 + 0x10)
+#define HWT_DIGCTL_STATUS                           HWIO_32_RW
+#define HWN_DIGCTL_STATUS                           DIGCTL_STATUS
+#define HWI_DIGCTL_STATUS                           
+#define HW_DIGCTL_STATUS_SET                        HW(DIGCTL_STATUS_SET)
+#define HWA_DIGCTL_STATUS_SET                       (HWA_DIGCTL_STATUS + 0x4)
+#define HWT_DIGCTL_STATUS_SET                       HWIO_32_WO
+#define HWN_DIGCTL_STATUS_SET                       DIGCTL_STATUS
+#define HWI_DIGCTL_STATUS_SET                       
+#define HW_DIGCTL_STATUS_CLR                        HW(DIGCTL_STATUS_CLR)
+#define HWA_DIGCTL_STATUS_CLR                       (HWA_DIGCTL_STATUS + 0x8)
+#define HWT_DIGCTL_STATUS_CLR                       HWIO_32_WO
+#define HWN_DIGCTL_STATUS_CLR                       DIGCTL_STATUS
+#define HWI_DIGCTL_STATUS_CLR                       
+#define HW_DIGCTL_STATUS_TOG                        HW(DIGCTL_STATUS_TOG)
+#define HWA_DIGCTL_STATUS_TOG                       (HWA_DIGCTL_STATUS + 0xc)
+#define HWT_DIGCTL_STATUS_TOG                       HWIO_32_WO
+#define HWN_DIGCTL_STATUS_TOG                       DIGCTL_STATUS
+#define HWI_DIGCTL_STATUS_TOG                       
+#define BP_DIGCTL_STATUS_USB_HS_PRESENT             31
+#define BM_DIGCTL_STATUS_USB_HS_PRESENT             0x80000000
+#define BF_DIGCTL_STATUS_USB_HS_PRESENT(v)          (((v) & 0x1) << 31)
+#define BFM_DIGCTL_STATUS_USB_HS_PRESENT(v)         BM_DIGCTL_STATUS_USB_HS_PRESENT
+#define BF_DIGCTL_STATUS_USB_HS_PRESENT_V(e)        BF_DIGCTL_STATUS_USB_HS_PRESENT(BV_DIGCTL_STATUS_USB_HS_PRESENT__##e)
+#define BFM_DIGCTL_STATUS_USB_HS_PRESENT_V(v)       BM_DIGCTL_STATUS_USB_HS_PRESENT
+#define BP_DIGCTL_STATUS_USB_OTG_PRESENT            30
+#define BM_DIGCTL_STATUS_USB_OTG_PRESENT            0x40000000
+#define BF_DIGCTL_STATUS_USB_OTG_PRESENT(v)         (((v) & 0x1) << 30)
+#define BFM_DIGCTL_STATUS_USB_OTG_PRESENT(v)        BM_DIGCTL_STATUS_USB_OTG_PRESENT
+#define BF_DIGCTL_STATUS_USB_OTG_PRESENT_V(e)       BF_DIGCTL_STATUS_USB_OTG_PRESENT(BV_DIGCTL_STATUS_USB_OTG_PRESENT__##e)
+#define BFM_DIGCTL_STATUS_USB_OTG_PRESENT_V(v)      BM_DIGCTL_STATUS_USB_OTG_PRESENT
+#define BP_DIGCTL_STATUS_USB_HOST_PRESENT           29
+#define BM_DIGCTL_STATUS_USB_HOST_PRESENT           0x20000000
+#define BF_DIGCTL_STATUS_USB_HOST_PRESENT(v)        (((v) & 0x1) << 29)
+#define BFM_DIGCTL_STATUS_USB_HOST_PRESENT(v)       BM_DIGCTL_STATUS_USB_HOST_PRESENT
+#define BF_DIGCTL_STATUS_USB_HOST_PRESENT_V(e)      BF_DIGCTL_STATUS_USB_HOST_PRESENT(BV_DIGCTL_STATUS_USB_HOST_PRESENT__##e)
+#define BFM_DIGCTL_STATUS_USB_HOST_PRESENT_V(v)     BM_DIGCTL_STATUS_USB_HOST_PRESENT
+#define BP_DIGCTL_STATUS_USB_DEVICE_PRESENT         28
+#define BM_DIGCTL_STATUS_USB_DEVICE_PRESENT         0x10000000
+#define BF_DIGCTL_STATUS_USB_DEVICE_PRESENT(v)      (((v) & 0x1) << 28)
+#define BFM_DIGCTL_STATUS_USB_DEVICE_PRESENT(v)     BM_DIGCTL_STATUS_USB_DEVICE_PRESENT
+#define BF_DIGCTL_STATUS_USB_DEVICE_PRESENT_V(e)    BF_DIGCTL_STATUS_USB_DEVICE_PRESENT(BV_DIGCTL_STATUS_USB_DEVICE_PRESENT__##e)
+#define BFM_DIGCTL_STATUS_USB_DEVICE_PRESENT_V(v)   BM_DIGCTL_STATUS_USB_DEVICE_PRESENT
+#define BP_DIGCTL_STATUS_RSVD2                      11
+#define BM_DIGCTL_STATUS_RSVD2                      0xffff800
+#define BF_DIGCTL_STATUS_RSVD2(v)                   (((v) & 0x1ffff) << 11)
+#define BFM_DIGCTL_STATUS_RSVD2(v)                  BM_DIGCTL_STATUS_RSVD2
+#define BF_DIGCTL_STATUS_RSVD2_V(e)                 BF_DIGCTL_STATUS_RSVD2(BV_DIGCTL_STATUS_RSVD2__##e)
+#define BFM_DIGCTL_STATUS_RSVD2_V(v)                BM_DIGCTL_STATUS_RSVD2
+#define BP_DIGCTL_STATUS_DCP_BIST_FAIL              10
+#define BM_DIGCTL_STATUS_DCP_BIST_FAIL              0x400
+#define BF_DIGCTL_STATUS_DCP_BIST_FAIL(v)           (((v) & 0x1) << 10)
+#define BFM_DIGCTL_STATUS_DCP_BIST_FAIL(v)          BM_DIGCTL_STATUS_DCP_BIST_FAIL
+#define BF_DIGCTL_STATUS_DCP_BIST_FAIL_V(e)         BF_DIGCTL_STATUS_DCP_BIST_FAIL(BV_DIGCTL_STATUS_DCP_BIST_FAIL__##e)
+#define BFM_DIGCTL_STATUS_DCP_BIST_FAIL_V(v)        BM_DIGCTL_STATUS_DCP_BIST_FAIL
+#define BP_DIGCTL_STATUS_DCP_BIST_PASS              9
+#define BM_DIGCTL_STATUS_DCP_BIST_PASS              0x200
+#define BF_DIGCTL_STATUS_DCP_BIST_PASS(v)           (((v) & 0x1) << 9)
+#define BFM_DIGCTL_STATUS_DCP_BIST_PASS(v)          BM_DIGCTL_STATUS_DCP_BIST_PASS
+#define BF_DIGCTL_STATUS_DCP_BIST_PASS_V(e)         BF_DIGCTL_STATUS_DCP_BIST_PASS(BV_DIGCTL_STATUS_DCP_BIST_PASS__##e)
+#define BFM_DIGCTL_STATUS_DCP_BIST_PASS_V(v)        BM_DIGCTL_STATUS_DCP_BIST_PASS
+#define BP_DIGCTL_STATUS_DCP_BIST_DONE              8
+#define BM_DIGCTL_STATUS_DCP_BIST_DONE              0x100
+#define BF_DIGCTL_STATUS_DCP_BIST_DONE(v)           (((v) & 0x1) << 8)
+#define BFM_DIGCTL_STATUS_DCP_BIST_DONE(v)          BM_DIGCTL_STATUS_DCP_BIST_DONE
+#define BF_DIGCTL_STATUS_DCP_BIST_DONE_V(e)         BF_DIGCTL_STATUS_DCP_BIST_DONE(BV_DIGCTL_STATUS_DCP_BIST_DONE__##e)
+#define BFM_DIGCTL_STATUS_DCP_BIST_DONE_V(v)        BM_DIGCTL_STATUS_DCP_BIST_DONE
+#define BP_DIGCTL_STATUS_LCD_BIST_FAIL              7
+#define BM_DIGCTL_STATUS_LCD_BIST_FAIL              0x80
+#define BF_DIGCTL_STATUS_LCD_BIST_FAIL(v)           (((v) & 0x1) << 7)
+#define BFM_DIGCTL_STATUS_LCD_BIST_FAIL(v)          BM_DIGCTL_STATUS_LCD_BIST_FAIL
+#define BF_DIGCTL_STATUS_LCD_BIST_FAIL_V(e)         BF_DIGCTL_STATUS_LCD_BIST_FAIL(BV_DIGCTL_STATUS_LCD_BIST_FAIL__##e)
+#define BFM_DIGCTL_STATUS_LCD_BIST_FAIL_V(v)        BM_DIGCTL_STATUS_LCD_BIST_FAIL
+#define BP_DIGCTL_STATUS_LCD_BIST_PASS              6
+#define BM_DIGCTL_STATUS_LCD_BIST_PASS              0x40
+#define BF_DIGCTL_STATUS_LCD_BIST_PASS(v)           (((v) & 0x1) << 6)
+#define BFM_DIGCTL_STATUS_LCD_BIST_PASS(v)          BM_DIGCTL_STATUS_LCD_BIST_PASS
+#define BF_DIGCTL_STATUS_LCD_BIST_PASS_V(e)         BF_DIGCTL_STATUS_LCD_BIST_PASS(BV_DIGCTL_STATUS_LCD_BIST_PASS__##e)
+#define BFM_DIGCTL_STATUS_LCD_BIST_PASS_V(v)        BM_DIGCTL_STATUS_LCD_BIST_PASS
+#define BP_DIGCTL_STATUS_LCD_BIST_DONE              5
+#define BM_DIGCTL_STATUS_LCD_BIST_DONE              0x20
+#define BF_DIGCTL_STATUS_LCD_BIST_DONE(v)           (((v) & 0x1) << 5)
+#define BFM_DIGCTL_STATUS_LCD_BIST_DONE(v)          BM_DIGCTL_STATUS_LCD_BIST_DONE
+#define BF_DIGCTL_STATUS_LCD_BIST_DONE_V(e)         BF_DIGCTL_STATUS_LCD_BIST_DONE(BV_DIGCTL_STATUS_LCD_BIST_DONE__##e)
+#define BFM_DIGCTL_STATUS_LCD_BIST_DONE_V(v)        BM_DIGCTL_STATUS_LCD_BIST_DONE
+#define BP_DIGCTL_STATUS_JTAG_IN_USE                4
+#define BM_DIGCTL_STATUS_JTAG_IN_USE                0x10
+#define BF_DIGCTL_STATUS_JTAG_IN_USE(v)             (((v) & 0x1) << 4)
+#define BFM_DIGCTL_STATUS_JTAG_IN_USE(v)            BM_DIGCTL_STATUS_JTAG_IN_USE
+#define BF_DIGCTL_STATUS_JTAG_IN_USE_V(e)           BF_DIGCTL_STATUS_JTAG_IN_USE(BV_DIGCTL_STATUS_JTAG_IN_USE__##e)
+#define BFM_DIGCTL_STATUS_JTAG_IN_USE_V(v)          BM_DIGCTL_STATUS_JTAG_IN_USE
+#define BP_DIGCTL_STATUS_PACKAGE_TYPE               1
+#define BM_DIGCTL_STATUS_PACKAGE_TYPE               0xe
+#define BF_DIGCTL_STATUS_PACKAGE_TYPE(v)            (((v) & 0x7) << 1)
+#define BFM_DIGCTL_STATUS_PACKAGE_TYPE(v)           BM_DIGCTL_STATUS_PACKAGE_TYPE
+#define BF_DIGCTL_STATUS_PACKAGE_TYPE_V(e)          BF_DIGCTL_STATUS_PACKAGE_TYPE(BV_DIGCTL_STATUS_PACKAGE_TYPE__##e)
+#define BFM_DIGCTL_STATUS_PACKAGE_TYPE_V(v)         BM_DIGCTL_STATUS_PACKAGE_TYPE
+#define BP_DIGCTL_STATUS_WRITTEN                    0
+#define BM_DIGCTL_STATUS_WRITTEN                    0x1
+#define BF_DIGCTL_STATUS_WRITTEN(v)                 (((v) & 0x1) << 0)
+#define BFM_DIGCTL_STATUS_WRITTEN(v)                BM_DIGCTL_STATUS_WRITTEN
+#define BF_DIGCTL_STATUS_WRITTEN_V(e)               BF_DIGCTL_STATUS_WRITTEN(BV_DIGCTL_STATUS_WRITTEN__##e)
+#define BFM_DIGCTL_STATUS_WRITTEN_V(v)              BM_DIGCTL_STATUS_WRITTEN
+
+#define HW_DIGCTL_HCLKCOUNT             HW(DIGCTL_HCLKCOUNT)
+#define HWA_DIGCTL_HCLKCOUNT            (0x8001c000 + 0x20)
+#define HWT_DIGCTL_HCLKCOUNT            HWIO_32_RW
+#define HWN_DIGCTL_HCLKCOUNT            DIGCTL_HCLKCOUNT
+#define HWI_DIGCTL_HCLKCOUNT            
+#define HW_DIGCTL_HCLKCOUNT_SET         HW(DIGCTL_HCLKCOUNT_SET)
+#define HWA_DIGCTL_HCLKCOUNT_SET        (HWA_DIGCTL_HCLKCOUNT + 0x4)
+#define HWT_DIGCTL_HCLKCOUNT_SET        HWIO_32_WO
+#define HWN_DIGCTL_HCLKCOUNT_SET        DIGCTL_HCLKCOUNT
+#define HWI_DIGCTL_HCLKCOUNT_SET        
+#define HW_DIGCTL_HCLKCOUNT_CLR         HW(DIGCTL_HCLKCOUNT_CLR)
+#define HWA_DIGCTL_HCLKCOUNT_CLR        (HWA_DIGCTL_HCLKCOUNT + 0x8)
+#define HWT_DIGCTL_HCLKCOUNT_CLR        HWIO_32_WO
+#define HWN_DIGCTL_HCLKCOUNT_CLR        DIGCTL_HCLKCOUNT
+#define HWI_DIGCTL_HCLKCOUNT_CLR        
+#define HW_DIGCTL_HCLKCOUNT_TOG         HW(DIGCTL_HCLKCOUNT_TOG)
+#define HWA_DIGCTL_HCLKCOUNT_TOG        (HWA_DIGCTL_HCLKCOUNT + 0xc)
+#define HWT_DIGCTL_HCLKCOUNT_TOG        HWIO_32_WO
+#define HWN_DIGCTL_HCLKCOUNT_TOG        DIGCTL_HCLKCOUNT
+#define HWI_DIGCTL_HCLKCOUNT_TOG        
+#define BP_DIGCTL_HCLKCOUNT_COUNT       0
+#define BM_DIGCTL_HCLKCOUNT_COUNT       0xffffffff
+#define BF_DIGCTL_HCLKCOUNT_COUNT(v)    (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_HCLKCOUNT_COUNT(v)   BM_DIGCTL_HCLKCOUNT_COUNT
+#define BF_DIGCTL_HCLKCOUNT_COUNT_V(e)  BF_DIGCTL_HCLKCOUNT_COUNT(BV_DIGCTL_HCLKCOUNT_COUNT__##e)
+#define BFM_DIGCTL_HCLKCOUNT_COUNT_V(v) BM_DIGCTL_HCLKCOUNT_COUNT
+
+#define HW_DIGCTL_RAMCTRL                       HW(DIGCTL_RAMCTRL)
+#define HWA_DIGCTL_RAMCTRL                      (0x8001c000 + 0x30)
+#define HWT_DIGCTL_RAMCTRL                      HWIO_32_RW
+#define HWN_DIGCTL_RAMCTRL                      DIGCTL_RAMCTRL
+#define HWI_DIGCTL_RAMCTRL                      
+#define HW_DIGCTL_RAMCTRL_SET                   HW(DIGCTL_RAMCTRL_SET)
+#define HWA_DIGCTL_RAMCTRL_SET                  (HWA_DIGCTL_RAMCTRL + 0x4)
+#define HWT_DIGCTL_RAMCTRL_SET                  HWIO_32_WO
+#define HWN_DIGCTL_RAMCTRL_SET                  DIGCTL_RAMCTRL
+#define HWI_DIGCTL_RAMCTRL_SET                  
+#define HW_DIGCTL_RAMCTRL_CLR                   HW(DIGCTL_RAMCTRL_CLR)
+#define HWA_DIGCTL_RAMCTRL_CLR                  (HWA_DIGCTL_RAMCTRL + 0x8)
+#define HWT_DIGCTL_RAMCTRL_CLR                  HWIO_32_WO
+#define HWN_DIGCTL_RAMCTRL_CLR                  DIGCTL_RAMCTRL
+#define HWI_DIGCTL_RAMCTRL_CLR                  
+#define HW_DIGCTL_RAMCTRL_TOG                   HW(DIGCTL_RAMCTRL_TOG)
+#define HWA_DIGCTL_RAMCTRL_TOG                  (HWA_DIGCTL_RAMCTRL + 0xc)
+#define HWT_DIGCTL_RAMCTRL_TOG                  HWIO_32_WO
+#define HWN_DIGCTL_RAMCTRL_TOG                  DIGCTL_RAMCTRL
+#define HWI_DIGCTL_RAMCTRL_TOG                  
+#define BP_DIGCTL_RAMCTRL_RSVD1                 12
+#define BM_DIGCTL_RAMCTRL_RSVD1                 0xfffff000
+#define BF_DIGCTL_RAMCTRL_RSVD1(v)              (((v) & 0xfffff) << 12)
+#define BFM_DIGCTL_RAMCTRL_RSVD1(v)             BM_DIGCTL_RAMCTRL_RSVD1
+#define BF_DIGCTL_RAMCTRL_RSVD1_V(e)            BF_DIGCTL_RAMCTRL_RSVD1(BV_DIGCTL_RAMCTRL_RSVD1__##e)
+#define BFM_DIGCTL_RAMCTRL_RSVD1_V(v)           BM_DIGCTL_RAMCTRL_RSVD1
+#define BP_DIGCTL_RAMCTRL_SPEED_SELECT          8
+#define BM_DIGCTL_RAMCTRL_SPEED_SELECT          0xf00
+#define BF_DIGCTL_RAMCTRL_SPEED_SELECT(v)       (((v) & 0xf) << 8)
+#define BFM_DIGCTL_RAMCTRL_SPEED_SELECT(v)      BM_DIGCTL_RAMCTRL_SPEED_SELECT
+#define BF_DIGCTL_RAMCTRL_SPEED_SELECT_V(e)     BF_DIGCTL_RAMCTRL_SPEED_SELECT(BV_DIGCTL_RAMCTRL_SPEED_SELECT__##e)
+#define BFM_DIGCTL_RAMCTRL_SPEED_SELECT_V(v)    BM_DIGCTL_RAMCTRL_SPEED_SELECT
+#define BP_DIGCTL_RAMCTRL_RSVD0                 1
+#define BM_DIGCTL_RAMCTRL_RSVD0                 0xfe
+#define BF_DIGCTL_RAMCTRL_RSVD0(v)              (((v) & 0x7f) << 1)
+#define BFM_DIGCTL_RAMCTRL_RSVD0(v)             BM_DIGCTL_RAMCTRL_RSVD0
+#define BF_DIGCTL_RAMCTRL_RSVD0_V(e)            BF_DIGCTL_RAMCTRL_RSVD0(BV_DIGCTL_RAMCTRL_RSVD0__##e)
+#define BFM_DIGCTL_RAMCTRL_RSVD0_V(v)           BM_DIGCTL_RAMCTRL_RSVD0
+#define BP_DIGCTL_RAMCTRL_RAM_REPAIR_EN         0
+#define BM_DIGCTL_RAMCTRL_RAM_REPAIR_EN         0x1
+#define BF_DIGCTL_RAMCTRL_RAM_REPAIR_EN(v)      (((v) & 0x1) << 0)
+#define BFM_DIGCTL_RAMCTRL_RAM_REPAIR_EN(v)     BM_DIGCTL_RAMCTRL_RAM_REPAIR_EN
+#define BF_DIGCTL_RAMCTRL_RAM_REPAIR_EN_V(e)    BF_DIGCTL_RAMCTRL_RAM_REPAIR_EN(BV_DIGCTL_RAMCTRL_RAM_REPAIR_EN__##e)
+#define BFM_DIGCTL_RAMCTRL_RAM_REPAIR_EN_V(v)   BM_DIGCTL_RAMCTRL_RAM_REPAIR_EN
+
+#define HW_DIGCTL_RAMREPAIR             HW(DIGCTL_RAMREPAIR)
+#define HWA_DIGCTL_RAMREPAIR            (0x8001c000 + 0x40)
+#define HWT_DIGCTL_RAMREPAIR            HWIO_32_RW
+#define HWN_DIGCTL_RAMREPAIR            DIGCTL_RAMREPAIR
+#define HWI_DIGCTL_RAMREPAIR            
+#define HW_DIGCTL_RAMREPAIR_SET         HW(DIGCTL_RAMREPAIR_SET)
+#define HWA_DIGCTL_RAMREPAIR_SET        (HWA_DIGCTL_RAMREPAIR + 0x4)
+#define HWT_DIGCTL_RAMREPAIR_SET        HWIO_32_WO
+#define HWN_DIGCTL_RAMREPAIR_SET        DIGCTL_RAMREPAIR
+#define HWI_DIGCTL_RAMREPAIR_SET        
+#define HW_DIGCTL_RAMREPAIR_CLR         HW(DIGCTL_RAMREPAIR_CLR)
+#define HWA_DIGCTL_RAMREPAIR_CLR        (HWA_DIGCTL_RAMREPAIR + 0x8)
+#define HWT_DIGCTL_RAMREPAIR_CLR        HWIO_32_WO
+#define HWN_DIGCTL_RAMREPAIR_CLR        DIGCTL_RAMREPAIR
+#define HWI_DIGCTL_RAMREPAIR_CLR        
+#define HW_DIGCTL_RAMREPAIR_TOG         HW(DIGCTL_RAMREPAIR_TOG)
+#define HWA_DIGCTL_RAMREPAIR_TOG        (HWA_DIGCTL_RAMREPAIR + 0xc)
+#define HWT_DIGCTL_RAMREPAIR_TOG        HWIO_32_WO
+#define HWN_DIGCTL_RAMREPAIR_TOG        DIGCTL_RAMREPAIR
+#define HWI_DIGCTL_RAMREPAIR_TOG        
+#define BP_DIGCTL_RAMREPAIR_RSVD1       16
+#define BM_DIGCTL_RAMREPAIR_RSVD1       0xffff0000
+#define BF_DIGCTL_RAMREPAIR_RSVD1(v)    (((v) & 0xffff) << 16)
+#define BFM_DIGCTL_RAMREPAIR_RSVD1(v)   BM_DIGCTL_RAMREPAIR_RSVD1
+#define BF_DIGCTL_RAMREPAIR_RSVD1_V(e)  BF_DIGCTL_RAMREPAIR_RSVD1(BV_DIGCTL_RAMREPAIR_RSVD1__##e)
+#define BFM_DIGCTL_RAMREPAIR_RSVD1_V(v) BM_DIGCTL_RAMREPAIR_RSVD1
+#define BP_DIGCTL_RAMREPAIR_ADDR        0
+#define BM_DIGCTL_RAMREPAIR_ADDR        0xffff
+#define BF_DIGCTL_RAMREPAIR_ADDR(v)     (((v) & 0xffff) << 0)
+#define BFM_DIGCTL_RAMREPAIR_ADDR(v)    BM_DIGCTL_RAMREPAIR_ADDR
+#define BF_DIGCTL_RAMREPAIR_ADDR_V(e)   BF_DIGCTL_RAMREPAIR_ADDR(BV_DIGCTL_RAMREPAIR_ADDR__##e)
+#define BFM_DIGCTL_RAMREPAIR_ADDR_V(v)  BM_DIGCTL_RAMREPAIR_ADDR
+
+#define HW_DIGCTL_ROMCTRL                   HW(DIGCTL_ROMCTRL)
+#define HWA_DIGCTL_ROMCTRL                  (0x8001c000 + 0x50)
+#define HWT_DIGCTL_ROMCTRL                  HWIO_32_RW
+#define HWN_DIGCTL_ROMCTRL                  DIGCTL_ROMCTRL
+#define HWI_DIGCTL_ROMCTRL                  
+#define HW_DIGCTL_ROMCTRL_SET               HW(DIGCTL_ROMCTRL_SET)
+#define HWA_DIGCTL_ROMCTRL_SET              (HWA_DIGCTL_ROMCTRL + 0x4)
+#define HWT_DIGCTL_ROMCTRL_SET              HWIO_32_WO
+#define HWN_DIGCTL_ROMCTRL_SET              DIGCTL_ROMCTRL
+#define HWI_DIGCTL_ROMCTRL_SET              
+#define HW_DIGCTL_ROMCTRL_CLR               HW(DIGCTL_ROMCTRL_CLR)
+#define HWA_DIGCTL_ROMCTRL_CLR              (HWA_DIGCTL_ROMCTRL + 0x8)
+#define HWT_DIGCTL_ROMCTRL_CLR              HWIO_32_WO
+#define HWN_DIGCTL_ROMCTRL_CLR              DIGCTL_ROMCTRL
+#define HWI_DIGCTL_ROMCTRL_CLR              
+#define HW_DIGCTL_ROMCTRL_TOG               HW(DIGCTL_ROMCTRL_TOG)
+#define HWA_DIGCTL_ROMCTRL_TOG              (HWA_DIGCTL_ROMCTRL + 0xc)
+#define HWT_DIGCTL_ROMCTRL_TOG              HWIO_32_WO
+#define HWN_DIGCTL_ROMCTRL_TOG              DIGCTL_ROMCTRL
+#define HWI_DIGCTL_ROMCTRL_TOG              
+#define BP_DIGCTL_ROMCTRL_RSVD0             4
+#define BM_DIGCTL_ROMCTRL_RSVD0             0xfffffff0
+#define BF_DIGCTL_ROMCTRL_RSVD0(v)          (((v) & 0xfffffff) << 4)
+#define BFM_DIGCTL_ROMCTRL_RSVD0(v)         BM_DIGCTL_ROMCTRL_RSVD0
+#define BF_DIGCTL_ROMCTRL_RSVD0_V(e)        BF_DIGCTL_ROMCTRL_RSVD0(BV_DIGCTL_ROMCTRL_RSVD0__##e)
+#define BFM_DIGCTL_ROMCTRL_RSVD0_V(v)       BM_DIGCTL_ROMCTRL_RSVD0
+#define BP_DIGCTL_ROMCTRL_RD_MARGIN         0
+#define BM_DIGCTL_ROMCTRL_RD_MARGIN         0xf
+#define BF_DIGCTL_ROMCTRL_RD_MARGIN(v)      (((v) & 0xf) << 0)
+#define BFM_DIGCTL_ROMCTRL_RD_MARGIN(v)     BM_DIGCTL_ROMCTRL_RD_MARGIN
+#define BF_DIGCTL_ROMCTRL_RD_MARGIN_V(e)    BF_DIGCTL_ROMCTRL_RD_MARGIN(BV_DIGCTL_ROMCTRL_RD_MARGIN__##e)
+#define BFM_DIGCTL_ROMCTRL_RD_MARGIN_V(v)   BM_DIGCTL_ROMCTRL_RD_MARGIN
+
+#define HW_DIGCTL_WRITEONCE             HW(DIGCTL_WRITEONCE)
+#define HWA_DIGCTL_WRITEONCE            (0x8001c000 + 0x60)
+#define HWT_DIGCTL_WRITEONCE            HWIO_32_RW
+#define HWN_DIGCTL_WRITEONCE            DIGCTL_WRITEONCE
+#define HWI_DIGCTL_WRITEONCE            
+#define BP_DIGCTL_WRITEONCE_BITS        0
+#define BM_DIGCTL_WRITEONCE_BITS        0xffffffff
+#define BF_DIGCTL_WRITEONCE_BITS(v)     (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_WRITEONCE_BITS(v)    BM_DIGCTL_WRITEONCE_BITS
+#define BF_DIGCTL_WRITEONCE_BITS_V(e)   BF_DIGCTL_WRITEONCE_BITS(BV_DIGCTL_WRITEONCE_BITS__##e)
+#define BFM_DIGCTL_WRITEONCE_BITS_V(v)  BM_DIGCTL_WRITEONCE_BITS
+
+#define HW_DIGCTL_ENTROPY               HW(DIGCTL_ENTROPY)
+#define HWA_DIGCTL_ENTROPY              (0x8001c000 + 0x90)
+#define HWT_DIGCTL_ENTROPY              HWIO_32_RW
+#define HWN_DIGCTL_ENTROPY              DIGCTL_ENTROPY
+#define HWI_DIGCTL_ENTROPY              
+#define BP_DIGCTL_ENTROPY_VALUE         0
+#define BM_DIGCTL_ENTROPY_VALUE         0xffffffff
+#define BF_DIGCTL_ENTROPY_VALUE(v)      (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_ENTROPY_VALUE(v)     BM_DIGCTL_ENTROPY_VALUE
+#define BF_DIGCTL_ENTROPY_VALUE_V(e)    BF_DIGCTL_ENTROPY_VALUE(BV_DIGCTL_ENTROPY_VALUE__##e)
+#define BFM_DIGCTL_ENTROPY_VALUE_V(v)   BM_DIGCTL_ENTROPY_VALUE
+
+#define HW_DIGCTL_ENTROPY_LATCHED               HW(DIGCTL_ENTROPY_LATCHED)
+#define HWA_DIGCTL_ENTROPY_LATCHED              (0x8001c000 + 0xa0)
+#define HWT_DIGCTL_ENTROPY_LATCHED              HWIO_32_RW
+#define HWN_DIGCTL_ENTROPY_LATCHED              DIGCTL_ENTROPY_LATCHED
+#define HWI_DIGCTL_ENTROPY_LATCHED              
+#define BP_DIGCTL_ENTROPY_LATCHED_VALUE         0
+#define BM_DIGCTL_ENTROPY_LATCHED_VALUE         0xffffffff
+#define BF_DIGCTL_ENTROPY_LATCHED_VALUE(v)      (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_ENTROPY_LATCHED_VALUE(v)     BM_DIGCTL_ENTROPY_LATCHED_VALUE
+#define BF_DIGCTL_ENTROPY_LATCHED_VALUE_V(e)    BF_DIGCTL_ENTROPY_LATCHED_VALUE(BV_DIGCTL_ENTROPY_LATCHED_VALUE__##e)
+#define BFM_DIGCTL_ENTROPY_LATCHED_VALUE_V(v)   BM_DIGCTL_ENTROPY_LATCHED_VALUE
+
+#define HW_DIGCTL_SJTAGDBG                          HW(DIGCTL_SJTAGDBG)
+#define HWA_DIGCTL_SJTAGDBG                         (0x8001c000 + 0xb0)
+#define HWT_DIGCTL_SJTAGDBG                         HWIO_32_RW
+#define HWN_DIGCTL_SJTAGDBG                         DIGCTL_SJTAGDBG
+#define HWI_DIGCTL_SJTAGDBG                         
+#define HW_DIGCTL_SJTAGDBG_SET                      HW(DIGCTL_SJTAGDBG_SET)
+#define HWA_DIGCTL_SJTAGDBG_SET                     (HWA_DIGCTL_SJTAGDBG + 0x4)
+#define HWT_DIGCTL_SJTAGDBG_SET                     HWIO_32_WO
+#define HWN_DIGCTL_SJTAGDBG_SET                     DIGCTL_SJTAGDBG
+#define HWI_DIGCTL_SJTAGDBG_SET                     
+#define HW_DIGCTL_SJTAGDBG_CLR                      HW(DIGCTL_SJTAGDBG_CLR)
+#define HWA_DIGCTL_SJTAGDBG_CLR                     (HWA_DIGCTL_SJTAGDBG + 0x8)
+#define HWT_DIGCTL_SJTAGDBG_CLR                     HWIO_32_WO
+#define HWN_DIGCTL_SJTAGDBG_CLR                     DIGCTL_SJTAGDBG
+#define HWI_DIGCTL_SJTAGDBG_CLR                     
+#define HW_DIGCTL_SJTAGDBG_TOG                      HW(DIGCTL_SJTAGDBG_TOG)
+#define HWA_DIGCTL_SJTAGDBG_TOG                     (HWA_DIGCTL_SJTAGDBG + 0xc)
+#define HWT_DIGCTL_SJTAGDBG_TOG                     HWIO_32_WO
+#define HWN_DIGCTL_SJTAGDBG_TOG                     DIGCTL_SJTAGDBG
+#define HWI_DIGCTL_SJTAGDBG_TOG                     
+#define BP_DIGCTL_SJTAGDBG_RSVD2                    27
+#define BM_DIGCTL_SJTAGDBG_RSVD2                    0xf8000000
+#define BF_DIGCTL_SJTAGDBG_RSVD2(v)                 (((v) & 0x1f) << 27)
+#define BFM_DIGCTL_SJTAGDBG_RSVD2(v)                BM_DIGCTL_SJTAGDBG_RSVD2
+#define BF_DIGCTL_SJTAGDBG_RSVD2_V(e)               BF_DIGCTL_SJTAGDBG_RSVD2(BV_DIGCTL_SJTAGDBG_RSVD2__##e)
+#define BFM_DIGCTL_SJTAGDBG_RSVD2_V(v)              BM_DIGCTL_SJTAGDBG_RSVD2
+#define BP_DIGCTL_SJTAGDBG_SJTAG_STATE              16
+#define BM_DIGCTL_SJTAGDBG_SJTAG_STATE              0x7ff0000
+#define BF_DIGCTL_SJTAGDBG_SJTAG_STATE(v)           (((v) & 0x7ff) << 16)
+#define BFM_DIGCTL_SJTAGDBG_SJTAG_STATE(v)          BM_DIGCTL_SJTAGDBG_SJTAG_STATE
+#define BF_DIGCTL_SJTAGDBG_SJTAG_STATE_V(e)         BF_DIGCTL_SJTAGDBG_SJTAG_STATE(BV_DIGCTL_SJTAGDBG_SJTAG_STATE__##e)
+#define BFM_DIGCTL_SJTAGDBG_SJTAG_STATE_V(v)        BM_DIGCTL_SJTAGDBG_SJTAG_STATE
+#define BP_DIGCTL_SJTAGDBG_RSVD1                    11
+#define BM_DIGCTL_SJTAGDBG_RSVD1                    0xf800
+#define BF_DIGCTL_SJTAGDBG_RSVD1(v)                 (((v) & 0x1f) << 11)
+#define BFM_DIGCTL_SJTAGDBG_RSVD1(v)                BM_DIGCTL_SJTAGDBG_RSVD1
+#define BF_DIGCTL_SJTAGDBG_RSVD1_V(e)               BF_DIGCTL_SJTAGDBG_RSVD1(BV_DIGCTL_SJTAGDBG_RSVD1__##e)
+#define BFM_DIGCTL_SJTAGDBG_RSVD1_V(v)              BM_DIGCTL_SJTAGDBG_RSVD1
+#define BP_DIGCTL_SJTAGDBG_SJTAG_TDO                10
+#define BM_DIGCTL_SJTAGDBG_SJTAG_TDO                0x400
+#define BF_DIGCTL_SJTAGDBG_SJTAG_TDO(v)             (((v) & 0x1) << 10)
+#define BFM_DIGCTL_SJTAGDBG_SJTAG_TDO(v)            BM_DIGCTL_SJTAGDBG_SJTAG_TDO
+#define BF_DIGCTL_SJTAGDBG_SJTAG_TDO_V(e)           BF_DIGCTL_SJTAGDBG_SJTAG_TDO(BV_DIGCTL_SJTAGDBG_SJTAG_TDO__##e)
+#define BFM_DIGCTL_SJTAGDBG_SJTAG_TDO_V(v)          BM_DIGCTL_SJTAGDBG_SJTAG_TDO
+#define BP_DIGCTL_SJTAGDBG_SJTAG_TDI                9
+#define BM_DIGCTL_SJTAGDBG_SJTAG_TDI                0x200
+#define BF_DIGCTL_SJTAGDBG_SJTAG_TDI(v)             (((v) & 0x1) << 9)
+#define BFM_DIGCTL_SJTAGDBG_SJTAG_TDI(v)            BM_DIGCTL_SJTAGDBG_SJTAG_TDI
+#define BF_DIGCTL_SJTAGDBG_SJTAG_TDI_V(e)           BF_DIGCTL_SJTAGDBG_SJTAG_TDI(BV_DIGCTL_SJTAGDBG_SJTAG_TDI__##e)
+#define BFM_DIGCTL_SJTAGDBG_SJTAG_TDI_V(v)          BM_DIGCTL_SJTAGDBG_SJTAG_TDI
+#define BP_DIGCTL_SJTAGDBG_SJTAG_MODE               8
+#define BM_DIGCTL_SJTAGDBG_SJTAG_MODE               0x100
+#define BF_DIGCTL_SJTAGDBG_SJTAG_MODE(v)            (((v) & 0x1) << 8)
+#define BFM_DIGCTL_SJTAGDBG_SJTAG_MODE(v)           BM_DIGCTL_SJTAGDBG_SJTAG_MODE
+#define BF_DIGCTL_SJTAGDBG_SJTAG_MODE_V(e)          BF_DIGCTL_SJTAGDBG_SJTAG_MODE(BV_DIGCTL_SJTAGDBG_SJTAG_MODE__##e)
+#define BFM_DIGCTL_SJTAGDBG_SJTAG_MODE_V(v)         BM_DIGCTL_SJTAGDBG_SJTAG_MODE
+#define BP_DIGCTL_SJTAGDBG_DELAYED_ACTIVE           4
+#define BM_DIGCTL_SJTAGDBG_DELAYED_ACTIVE           0xf0
+#define BF_DIGCTL_SJTAGDBG_DELAYED_ACTIVE(v)        (((v) & 0xf) << 4)
+#define BFM_DIGCTL_SJTAGDBG_DELAYED_ACTIVE(v)       BM_DIGCTL_SJTAGDBG_DELAYED_ACTIVE
+#define BF_DIGCTL_SJTAGDBG_DELAYED_ACTIVE_V(e)      BF_DIGCTL_SJTAGDBG_DELAYED_ACTIVE(BV_DIGCTL_SJTAGDBG_DELAYED_ACTIVE__##e)
+#define BFM_DIGCTL_SJTAGDBG_DELAYED_ACTIVE_V(v)     BM_DIGCTL_SJTAGDBG_DELAYED_ACTIVE
+#define BP_DIGCTL_SJTAGDBG_ACTIVE                   3
+#define BM_DIGCTL_SJTAGDBG_ACTIVE                   0x8
+#define BF_DIGCTL_SJTAGDBG_ACTIVE(v)                (((v) & 0x1) << 3)
+#define BFM_DIGCTL_SJTAGDBG_ACTIVE(v)               BM_DIGCTL_SJTAGDBG_ACTIVE
+#define BF_DIGCTL_SJTAGDBG_ACTIVE_V(e)              BF_DIGCTL_SJTAGDBG_ACTIVE(BV_DIGCTL_SJTAGDBG_ACTIVE__##e)
+#define BFM_DIGCTL_SJTAGDBG_ACTIVE_V(v)             BM_DIGCTL_SJTAGDBG_ACTIVE
+#define BP_DIGCTL_SJTAGDBG_SJTAG_PIN_STATE          2
+#define BM_DIGCTL_SJTAGDBG_SJTAG_PIN_STATE          0x4
+#define BF_DIGCTL_SJTAGDBG_SJTAG_PIN_STATE(v)       (((v) & 0x1) << 2)
+#define BFM_DIGCTL_SJTAGDBG_SJTAG_PIN_STATE(v)      BM_DIGCTL_SJTAGDBG_SJTAG_PIN_STATE
+#define BF_DIGCTL_SJTAGDBG_SJTAG_PIN_STATE_V(e)     BF_DIGCTL_SJTAGDBG_SJTAG_PIN_STATE(BV_DIGCTL_SJTAGDBG_SJTAG_PIN_STATE__##e)
+#define BFM_DIGCTL_SJTAGDBG_SJTAG_PIN_STATE_V(v)    BM_DIGCTL_SJTAGDBG_SJTAG_PIN_STATE
+#define BP_DIGCTL_SJTAGDBG_SJTAG_DEBUG_DATA         1
+#define BM_DIGCTL_SJTAGDBG_SJTAG_DEBUG_DATA         0x2
+#define BF_DIGCTL_SJTAGDBG_SJTAG_DEBUG_DATA(v)      (((v) & 0x1) << 1)
+#define BFM_DIGCTL_SJTAGDBG_SJTAG_DEBUG_DATA(v)     BM_DIGCTL_SJTAGDBG_SJTAG_DEBUG_DATA
+#define BF_DIGCTL_SJTAGDBG_SJTAG_DEBUG_DATA_V(e)    BF_DIGCTL_SJTAGDBG_SJTAG_DEBUG_DATA(BV_DIGCTL_SJTAGDBG_SJTAG_DEBUG_DATA__##e)
+#define BFM_DIGCTL_SJTAGDBG_SJTAG_DEBUG_DATA_V(v)   BM_DIGCTL_SJTAGDBG_SJTAG_DEBUG_DATA
+#define BP_DIGCTL_SJTAGDBG_SJTAG_DEBUG_OE           0
+#define BM_DIGCTL_SJTAGDBG_SJTAG_DEBUG_OE           0x1
+#define BF_DIGCTL_SJTAGDBG_SJTAG_DEBUG_OE(v)        (((v) & 0x1) << 0)
+#define BFM_DIGCTL_SJTAGDBG_SJTAG_DEBUG_OE(v)       BM_DIGCTL_SJTAGDBG_SJTAG_DEBUG_OE
+#define BF_DIGCTL_SJTAGDBG_SJTAG_DEBUG_OE_V(e)      BF_DIGCTL_SJTAGDBG_SJTAG_DEBUG_OE(BV_DIGCTL_SJTAGDBG_SJTAG_DEBUG_OE__##e)
+#define BFM_DIGCTL_SJTAGDBG_SJTAG_DEBUG_OE_V(v)     BM_DIGCTL_SJTAGDBG_SJTAG_DEBUG_OE
+
+#define HW_DIGCTL_MICROSECONDS              HW(DIGCTL_MICROSECONDS)
+#define HWA_DIGCTL_MICROSECONDS             (0x8001c000 + 0xc0)
+#define HWT_DIGCTL_MICROSECONDS             HWIO_32_RW
+#define HWN_DIGCTL_MICROSECONDS             DIGCTL_MICROSECONDS
+#define HWI_DIGCTL_MICROSECONDS             
+#define HW_DIGCTL_MICROSECONDS_SET          HW(DIGCTL_MICROSECONDS_SET)
+#define HWA_DIGCTL_MICROSECONDS_SET         (HWA_DIGCTL_MICROSECONDS + 0x4)
+#define HWT_DIGCTL_MICROSECONDS_SET         HWIO_32_WO
+#define HWN_DIGCTL_MICROSECONDS_SET         DIGCTL_MICROSECONDS
+#define HWI_DIGCTL_MICROSECONDS_SET         
+#define HW_DIGCTL_MICROSECONDS_CLR          HW(DIGCTL_MICROSECONDS_CLR)
+#define HWA_DIGCTL_MICROSECONDS_CLR         (HWA_DIGCTL_MICROSECONDS + 0x8)
+#define HWT_DIGCTL_MICROSECONDS_CLR         HWIO_32_WO
+#define HWN_DIGCTL_MICROSECONDS_CLR         DIGCTL_MICROSECONDS
+#define HWI_DIGCTL_MICROSECONDS_CLR         
+#define HW_DIGCTL_MICROSECONDS_TOG          HW(DIGCTL_MICROSECONDS_TOG)
+#define HWA_DIGCTL_MICROSECONDS_TOG         (HWA_DIGCTL_MICROSECONDS + 0xc)
+#define HWT_DIGCTL_MICROSECONDS_TOG         HWIO_32_WO
+#define HWN_DIGCTL_MICROSECONDS_TOG         DIGCTL_MICROSECONDS
+#define HWI_DIGCTL_MICROSECONDS_TOG         
+#define BP_DIGCTL_MICROSECONDS_VALUE        0
+#define BM_DIGCTL_MICROSECONDS_VALUE        0xffffffff
+#define BF_DIGCTL_MICROSECONDS_VALUE(v)     (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_MICROSECONDS_VALUE(v)    BM_DIGCTL_MICROSECONDS_VALUE
+#define BF_DIGCTL_MICROSECONDS_VALUE_V(e)   BF_DIGCTL_MICROSECONDS_VALUE(BV_DIGCTL_MICROSECONDS_VALUE__##e)
+#define BFM_DIGCTL_MICROSECONDS_VALUE_V(v)  BM_DIGCTL_MICROSECONDS_VALUE
+
+#define HW_DIGCTL_DBGRD                     HW(DIGCTL_DBGRD)
+#define HWA_DIGCTL_DBGRD                    (0x8001c000 + 0xd0)
+#define HWT_DIGCTL_DBGRD                    HWIO_32_RW
+#define HWN_DIGCTL_DBGRD                    DIGCTL_DBGRD
+#define HWI_DIGCTL_DBGRD                    
+#define BP_DIGCTL_DBGRD_COMPLEMENT          0
+#define BM_DIGCTL_DBGRD_COMPLEMENT          0xffffffff
+#define BF_DIGCTL_DBGRD_COMPLEMENT(v)       (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_DBGRD_COMPLEMENT(v)      BM_DIGCTL_DBGRD_COMPLEMENT
+#define BF_DIGCTL_DBGRD_COMPLEMENT_V(e)     BF_DIGCTL_DBGRD_COMPLEMENT(BV_DIGCTL_DBGRD_COMPLEMENT__##e)
+#define BFM_DIGCTL_DBGRD_COMPLEMENT_V(v)    BM_DIGCTL_DBGRD_COMPLEMENT
+
+#define HW_DIGCTL_DBG               HW(DIGCTL_DBG)
+#define HWA_DIGCTL_DBG              (0x8001c000 + 0xe0)
+#define HWT_DIGCTL_DBG              HWIO_32_RW
+#define HWN_DIGCTL_DBG              DIGCTL_DBG
+#define HWI_DIGCTL_DBG              
+#define BP_DIGCTL_DBG_VALUE         0
+#define BM_DIGCTL_DBG_VALUE         0xffffffff
+#define BF_DIGCTL_DBG_VALUE(v)      (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_DBG_VALUE(v)     BM_DIGCTL_DBG_VALUE
+#define BF_DIGCTL_DBG_VALUE_V(e)    BF_DIGCTL_DBG_VALUE(BV_DIGCTL_DBG_VALUE__##e)
+#define BFM_DIGCTL_DBG_VALUE_V(v)   BM_DIGCTL_DBG_VALUE
+
+#define HW_DIGCTL_OCRAM_BIST_CSR                        HW(DIGCTL_OCRAM_BIST_CSR)
+#define HWA_DIGCTL_OCRAM_BIST_CSR                       (0x8001c000 + 0xf0)
+#define HWT_DIGCTL_OCRAM_BIST_CSR                       HWIO_32_RW
+#define HWN_DIGCTL_OCRAM_BIST_CSR                       DIGCTL_OCRAM_BIST_CSR
+#define HWI_DIGCTL_OCRAM_BIST_CSR                       
+#define HW_DIGCTL_OCRAM_BIST_CSR_SET                    HW(DIGCTL_OCRAM_BIST_CSR_SET)
+#define HWA_DIGCTL_OCRAM_BIST_CSR_SET                   (HWA_DIGCTL_OCRAM_BIST_CSR + 0x4)
+#define HWT_DIGCTL_OCRAM_BIST_CSR_SET                   HWIO_32_WO
+#define HWN_DIGCTL_OCRAM_BIST_CSR_SET                   DIGCTL_OCRAM_BIST_CSR
+#define HWI_DIGCTL_OCRAM_BIST_CSR_SET                   
+#define HW_DIGCTL_OCRAM_BIST_CSR_CLR                    HW(DIGCTL_OCRAM_BIST_CSR_CLR)
+#define HWA_DIGCTL_OCRAM_BIST_CSR_CLR                   (HWA_DIGCTL_OCRAM_BIST_CSR + 0x8)
+#define HWT_DIGCTL_OCRAM_BIST_CSR_CLR                   HWIO_32_WO
+#define HWN_DIGCTL_OCRAM_BIST_CSR_CLR                   DIGCTL_OCRAM_BIST_CSR
+#define HWI_DIGCTL_OCRAM_BIST_CSR_CLR                   
+#define HW_DIGCTL_OCRAM_BIST_CSR_TOG                    HW(DIGCTL_OCRAM_BIST_CSR_TOG)
+#define HWA_DIGCTL_OCRAM_BIST_CSR_TOG                   (HWA_DIGCTL_OCRAM_BIST_CSR + 0xc)
+#define HWT_DIGCTL_OCRAM_BIST_CSR_TOG                   HWIO_32_WO
+#define HWN_DIGCTL_OCRAM_BIST_CSR_TOG                   DIGCTL_OCRAM_BIST_CSR
+#define HWI_DIGCTL_OCRAM_BIST_CSR_TOG                   
+#define BP_DIGCTL_OCRAM_BIST_CSR_RSVD1                  11
+#define BM_DIGCTL_OCRAM_BIST_CSR_RSVD1                  0xfffff800
+#define BF_DIGCTL_OCRAM_BIST_CSR_RSVD1(v)               (((v) & 0x1fffff) << 11)
+#define BFM_DIGCTL_OCRAM_BIST_CSR_RSVD1(v)              BM_DIGCTL_OCRAM_BIST_CSR_RSVD1
+#define BF_DIGCTL_OCRAM_BIST_CSR_RSVD1_V(e)             BF_DIGCTL_OCRAM_BIST_CSR_RSVD1(BV_DIGCTL_OCRAM_BIST_CSR_RSVD1__##e)
+#define BFM_DIGCTL_OCRAM_BIST_CSR_RSVD1_V(v)            BM_DIGCTL_OCRAM_BIST_CSR_RSVD1
+#define BP_DIGCTL_OCRAM_BIST_CSR_BIST_DEBUG_MODE        10
+#define BM_DIGCTL_OCRAM_BIST_CSR_BIST_DEBUG_MODE        0x400
+#define BF_DIGCTL_OCRAM_BIST_CSR_BIST_DEBUG_MODE(v)     (((v) & 0x1) << 10)
+#define BFM_DIGCTL_OCRAM_BIST_CSR_BIST_DEBUG_MODE(v)    BM_DIGCTL_OCRAM_BIST_CSR_BIST_DEBUG_MODE
+#define BF_DIGCTL_OCRAM_BIST_CSR_BIST_DEBUG_MODE_V(e)   BF_DIGCTL_OCRAM_BIST_CSR_BIST_DEBUG_MODE(BV_DIGCTL_OCRAM_BIST_CSR_BIST_DEBUG_MODE__##e)
+#define BFM_DIGCTL_OCRAM_BIST_CSR_BIST_DEBUG_MODE_V(v)  BM_DIGCTL_OCRAM_BIST_CSR_BIST_DEBUG_MODE
+#define BP_DIGCTL_OCRAM_BIST_CSR_BIST_DATA_CHANGE       9
+#define BM_DIGCTL_OCRAM_BIST_CSR_BIST_DATA_CHANGE       0x200
+#define BF_DIGCTL_OCRAM_BIST_CSR_BIST_DATA_CHANGE(v)    (((v) & 0x1) << 9)
+#define BFM_DIGCTL_OCRAM_BIST_CSR_BIST_DATA_CHANGE(v)   BM_DIGCTL_OCRAM_BIST_CSR_BIST_DATA_CHANGE
+#define BF_DIGCTL_OCRAM_BIST_CSR_BIST_DATA_CHANGE_V(e)  BF_DIGCTL_OCRAM_BIST_CSR_BIST_DATA_CHANGE(BV_DIGCTL_OCRAM_BIST_CSR_BIST_DATA_CHANGE__##e)
+#define BFM_DIGCTL_OCRAM_BIST_CSR_BIST_DATA_CHANGE_V(v) BM_DIGCTL_OCRAM_BIST_CSR_BIST_DATA_CHANGE
+#define BP_DIGCTL_OCRAM_BIST_CSR_BIST_CLKEN             8
+#define BM_DIGCTL_OCRAM_BIST_CSR_BIST_CLKEN             0x100
+#define BF_DIGCTL_OCRAM_BIST_CSR_BIST_CLKEN(v)          (((v) & 0x1) << 8)
+#define BFM_DIGCTL_OCRAM_BIST_CSR_BIST_CLKEN(v)         BM_DIGCTL_OCRAM_BIST_CSR_BIST_CLKEN
+#define BF_DIGCTL_OCRAM_BIST_CSR_BIST_CLKEN_V(e)        BF_DIGCTL_OCRAM_BIST_CSR_BIST_CLKEN(BV_DIGCTL_OCRAM_BIST_CSR_BIST_CLKEN__##e)
+#define BFM_DIGCTL_OCRAM_BIST_CSR_BIST_CLKEN_V(v)       BM_DIGCTL_OCRAM_BIST_CSR_BIST_CLKEN
+#define BP_DIGCTL_OCRAM_BIST_CSR_RSVD0                  4
+#define BM_DIGCTL_OCRAM_BIST_CSR_RSVD0                  0xf0
+#define BF_DIGCTL_OCRAM_BIST_CSR_RSVD0(v)               (((v) & 0xf) << 4)
+#define BFM_DIGCTL_OCRAM_BIST_CSR_RSVD0(v)              BM_DIGCTL_OCRAM_BIST_CSR_RSVD0
+#define BF_DIGCTL_OCRAM_BIST_CSR_RSVD0_V(e)             BF_DIGCTL_OCRAM_BIST_CSR_RSVD0(BV_DIGCTL_OCRAM_BIST_CSR_RSVD0__##e)
+#define BFM_DIGCTL_OCRAM_BIST_CSR_RSVD0_V(v)            BM_DIGCTL_OCRAM_BIST_CSR_RSVD0
+#define BP_DIGCTL_OCRAM_BIST_CSR_FAIL                   3
+#define BM_DIGCTL_OCRAM_BIST_CSR_FAIL                   0x8
+#define BF_DIGCTL_OCRAM_BIST_CSR_FAIL(v)                (((v) & 0x1) << 3)
+#define BFM_DIGCTL_OCRAM_BIST_CSR_FAIL(v)               BM_DIGCTL_OCRAM_BIST_CSR_FAIL
+#define BF_DIGCTL_OCRAM_BIST_CSR_FAIL_V(e)              BF_DIGCTL_OCRAM_BIST_CSR_FAIL(BV_DIGCTL_OCRAM_BIST_CSR_FAIL__##e)
+#define BFM_DIGCTL_OCRAM_BIST_CSR_FAIL_V(v)             BM_DIGCTL_OCRAM_BIST_CSR_FAIL
+#define BP_DIGCTL_OCRAM_BIST_CSR_PASS                   2
+#define BM_DIGCTL_OCRAM_BIST_CSR_PASS                   0x4
+#define BF_DIGCTL_OCRAM_BIST_CSR_PASS(v)                (((v) & 0x1) << 2)
+#define BFM_DIGCTL_OCRAM_BIST_CSR_PASS(v)               BM_DIGCTL_OCRAM_BIST_CSR_PASS
+#define BF_DIGCTL_OCRAM_BIST_CSR_PASS_V(e)              BF_DIGCTL_OCRAM_BIST_CSR_PASS(BV_DIGCTL_OCRAM_BIST_CSR_PASS__##e)
+#define BFM_DIGCTL_OCRAM_BIST_CSR_PASS_V(v)             BM_DIGCTL_OCRAM_BIST_CSR_PASS
+#define BP_DIGCTL_OCRAM_BIST_CSR_DONE                   1
+#define BM_DIGCTL_OCRAM_BIST_CSR_DONE                   0x2
+#define BF_DIGCTL_OCRAM_BIST_CSR_DONE(v)                (((v) & 0x1) << 1)
+#define BFM_DIGCTL_OCRAM_BIST_CSR_DONE(v)               BM_DIGCTL_OCRAM_BIST_CSR_DONE
+#define BF_DIGCTL_OCRAM_BIST_CSR_DONE_V(e)              BF_DIGCTL_OCRAM_BIST_CSR_DONE(BV_DIGCTL_OCRAM_BIST_CSR_DONE__##e)
+#define BFM_DIGCTL_OCRAM_BIST_CSR_DONE_V(v)             BM_DIGCTL_OCRAM_BIST_CSR_DONE
+#define BP_DIGCTL_OCRAM_BIST_CSR_START                  0
+#define BM_DIGCTL_OCRAM_BIST_CSR_START                  0x1
+#define BF_DIGCTL_OCRAM_BIST_CSR_START(v)               (((v) & 0x1) << 0)
+#define BFM_DIGCTL_OCRAM_BIST_CSR_START(v)              BM_DIGCTL_OCRAM_BIST_CSR_START
+#define BF_DIGCTL_OCRAM_BIST_CSR_START_V(e)             BF_DIGCTL_OCRAM_BIST_CSR_START(BV_DIGCTL_OCRAM_BIST_CSR_START__##e)
+#define BFM_DIGCTL_OCRAM_BIST_CSR_START_V(v)            BM_DIGCTL_OCRAM_BIST_CSR_START
+
+#define HW_DIGCTL_OCRAM_STATUS0                     HW(DIGCTL_OCRAM_STATUS0)
+#define HWA_DIGCTL_OCRAM_STATUS0                    (0x8001c000 + 0x110)
+#define HWT_DIGCTL_OCRAM_STATUS0                    HWIO_32_RW
+#define HWN_DIGCTL_OCRAM_STATUS0                    DIGCTL_OCRAM_STATUS0
+#define HWI_DIGCTL_OCRAM_STATUS0                    
+#define HW_DIGCTL_OCRAM_STATUS0_SET                 HW(DIGCTL_OCRAM_STATUS0_SET)
+#define HWA_DIGCTL_OCRAM_STATUS0_SET                (HWA_DIGCTL_OCRAM_STATUS0 + 0x4)
+#define HWT_DIGCTL_OCRAM_STATUS0_SET                HWIO_32_WO
+#define HWN_DIGCTL_OCRAM_STATUS0_SET                DIGCTL_OCRAM_STATUS0
+#define HWI_DIGCTL_OCRAM_STATUS0_SET                
+#define HW_DIGCTL_OCRAM_STATUS0_CLR                 HW(DIGCTL_OCRAM_STATUS0_CLR)
+#define HWA_DIGCTL_OCRAM_STATUS0_CLR                (HWA_DIGCTL_OCRAM_STATUS0 + 0x8)
+#define HWT_DIGCTL_OCRAM_STATUS0_CLR                HWIO_32_WO
+#define HWN_DIGCTL_OCRAM_STATUS0_CLR                DIGCTL_OCRAM_STATUS0
+#define HWI_DIGCTL_OCRAM_STATUS0_CLR                
+#define HW_DIGCTL_OCRAM_STATUS0_TOG                 HW(DIGCTL_OCRAM_STATUS0_TOG)
+#define HWA_DIGCTL_OCRAM_STATUS0_TOG                (HWA_DIGCTL_OCRAM_STATUS0 + 0xc)
+#define HWT_DIGCTL_OCRAM_STATUS0_TOG                HWIO_32_WO
+#define HWN_DIGCTL_OCRAM_STATUS0_TOG                DIGCTL_OCRAM_STATUS0
+#define HWI_DIGCTL_OCRAM_STATUS0_TOG                
+#define BP_DIGCTL_OCRAM_STATUS0_FAILDATA00          0
+#define BM_DIGCTL_OCRAM_STATUS0_FAILDATA00          0xffffffff
+#define BF_DIGCTL_OCRAM_STATUS0_FAILDATA00(v)       (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_OCRAM_STATUS0_FAILDATA00(v)      BM_DIGCTL_OCRAM_STATUS0_FAILDATA00
+#define BF_DIGCTL_OCRAM_STATUS0_FAILDATA00_V(e)     BF_DIGCTL_OCRAM_STATUS0_FAILDATA00(BV_DIGCTL_OCRAM_STATUS0_FAILDATA00__##e)
+#define BFM_DIGCTL_OCRAM_STATUS0_FAILDATA00_V(v)    BM_DIGCTL_OCRAM_STATUS0_FAILDATA00
+
+#define HW_DIGCTL_OCRAM_STATUS1                     HW(DIGCTL_OCRAM_STATUS1)
+#define HWA_DIGCTL_OCRAM_STATUS1                    (0x8001c000 + 0x120)
+#define HWT_DIGCTL_OCRAM_STATUS1                    HWIO_32_RW
+#define HWN_DIGCTL_OCRAM_STATUS1                    DIGCTL_OCRAM_STATUS1
+#define HWI_DIGCTL_OCRAM_STATUS1                    
+#define HW_DIGCTL_OCRAM_STATUS1_SET                 HW(DIGCTL_OCRAM_STATUS1_SET)
+#define HWA_DIGCTL_OCRAM_STATUS1_SET                (HWA_DIGCTL_OCRAM_STATUS1 + 0x4)
+#define HWT_DIGCTL_OCRAM_STATUS1_SET                HWIO_32_WO
+#define HWN_DIGCTL_OCRAM_STATUS1_SET                DIGCTL_OCRAM_STATUS1
+#define HWI_DIGCTL_OCRAM_STATUS1_SET                
+#define HW_DIGCTL_OCRAM_STATUS1_CLR                 HW(DIGCTL_OCRAM_STATUS1_CLR)
+#define HWA_DIGCTL_OCRAM_STATUS1_CLR                (HWA_DIGCTL_OCRAM_STATUS1 + 0x8)
+#define HWT_DIGCTL_OCRAM_STATUS1_CLR                HWIO_32_WO
+#define HWN_DIGCTL_OCRAM_STATUS1_CLR                DIGCTL_OCRAM_STATUS1
+#define HWI_DIGCTL_OCRAM_STATUS1_CLR                
+#define HW_DIGCTL_OCRAM_STATUS1_TOG                 HW(DIGCTL_OCRAM_STATUS1_TOG)
+#define HWA_DIGCTL_OCRAM_STATUS1_TOG                (HWA_DIGCTL_OCRAM_STATUS1 + 0xc)
+#define HWT_DIGCTL_OCRAM_STATUS1_TOG                HWIO_32_WO
+#define HWN_DIGCTL_OCRAM_STATUS1_TOG                DIGCTL_OCRAM_STATUS1
+#define HWI_DIGCTL_OCRAM_STATUS1_TOG                
+#define BP_DIGCTL_OCRAM_STATUS1_FAILDATA01          0
+#define BM_DIGCTL_OCRAM_STATUS1_FAILDATA01          0xffffffff
+#define BF_DIGCTL_OCRAM_STATUS1_FAILDATA01(v)       (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_OCRAM_STATUS1_FAILDATA01(v)      BM_DIGCTL_OCRAM_STATUS1_FAILDATA01
+#define BF_DIGCTL_OCRAM_STATUS1_FAILDATA01_V(e)     BF_DIGCTL_OCRAM_STATUS1_FAILDATA01(BV_DIGCTL_OCRAM_STATUS1_FAILDATA01__##e)
+#define BFM_DIGCTL_OCRAM_STATUS1_FAILDATA01_V(v)    BM_DIGCTL_OCRAM_STATUS1_FAILDATA01
+
+#define HW_DIGCTL_OCRAM_STATUS2                     HW(DIGCTL_OCRAM_STATUS2)
+#define HWA_DIGCTL_OCRAM_STATUS2                    (0x8001c000 + 0x130)
+#define HWT_DIGCTL_OCRAM_STATUS2                    HWIO_32_RW
+#define HWN_DIGCTL_OCRAM_STATUS2                    DIGCTL_OCRAM_STATUS2
+#define HWI_DIGCTL_OCRAM_STATUS2                    
+#define HW_DIGCTL_OCRAM_STATUS2_SET                 HW(DIGCTL_OCRAM_STATUS2_SET)
+#define HWA_DIGCTL_OCRAM_STATUS2_SET                (HWA_DIGCTL_OCRAM_STATUS2 + 0x4)
+#define HWT_DIGCTL_OCRAM_STATUS2_SET                HWIO_32_WO
+#define HWN_DIGCTL_OCRAM_STATUS2_SET                DIGCTL_OCRAM_STATUS2
+#define HWI_DIGCTL_OCRAM_STATUS2_SET                
+#define HW_DIGCTL_OCRAM_STATUS2_CLR                 HW(DIGCTL_OCRAM_STATUS2_CLR)
+#define HWA_DIGCTL_OCRAM_STATUS2_CLR                (HWA_DIGCTL_OCRAM_STATUS2 + 0x8)
+#define HWT_DIGCTL_OCRAM_STATUS2_CLR                HWIO_32_WO
+#define HWN_DIGCTL_OCRAM_STATUS2_CLR                DIGCTL_OCRAM_STATUS2
+#define HWI_DIGCTL_OCRAM_STATUS2_CLR                
+#define HW_DIGCTL_OCRAM_STATUS2_TOG                 HW(DIGCTL_OCRAM_STATUS2_TOG)
+#define HWA_DIGCTL_OCRAM_STATUS2_TOG                (HWA_DIGCTL_OCRAM_STATUS2 + 0xc)
+#define HWT_DIGCTL_OCRAM_STATUS2_TOG                HWIO_32_WO
+#define HWN_DIGCTL_OCRAM_STATUS2_TOG                DIGCTL_OCRAM_STATUS2
+#define HWI_DIGCTL_OCRAM_STATUS2_TOG                
+#define BP_DIGCTL_OCRAM_STATUS2_FAILDATA10          0
+#define BM_DIGCTL_OCRAM_STATUS2_FAILDATA10          0xffffffff
+#define BF_DIGCTL_OCRAM_STATUS2_FAILDATA10(v)       (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_OCRAM_STATUS2_FAILDATA10(v)      BM_DIGCTL_OCRAM_STATUS2_FAILDATA10
+#define BF_DIGCTL_OCRAM_STATUS2_FAILDATA10_V(e)     BF_DIGCTL_OCRAM_STATUS2_FAILDATA10(BV_DIGCTL_OCRAM_STATUS2_FAILDATA10__##e)
+#define BFM_DIGCTL_OCRAM_STATUS2_FAILDATA10_V(v)    BM_DIGCTL_OCRAM_STATUS2_FAILDATA10
+
+#define HW_DIGCTL_OCRAM_STATUS3                     HW(DIGCTL_OCRAM_STATUS3)
+#define HWA_DIGCTL_OCRAM_STATUS3                    (0x8001c000 + 0x140)
+#define HWT_DIGCTL_OCRAM_STATUS3                    HWIO_32_RW
+#define HWN_DIGCTL_OCRAM_STATUS3                    DIGCTL_OCRAM_STATUS3
+#define HWI_DIGCTL_OCRAM_STATUS3                    
+#define HW_DIGCTL_OCRAM_STATUS3_SET                 HW(DIGCTL_OCRAM_STATUS3_SET)
+#define HWA_DIGCTL_OCRAM_STATUS3_SET                (HWA_DIGCTL_OCRAM_STATUS3 + 0x4)
+#define HWT_DIGCTL_OCRAM_STATUS3_SET                HWIO_32_WO
+#define HWN_DIGCTL_OCRAM_STATUS3_SET                DIGCTL_OCRAM_STATUS3
+#define HWI_DIGCTL_OCRAM_STATUS3_SET                
+#define HW_DIGCTL_OCRAM_STATUS3_CLR                 HW(DIGCTL_OCRAM_STATUS3_CLR)
+#define HWA_DIGCTL_OCRAM_STATUS3_CLR                (HWA_DIGCTL_OCRAM_STATUS3 + 0x8)
+#define HWT_DIGCTL_OCRAM_STATUS3_CLR                HWIO_32_WO
+#define HWN_DIGCTL_OCRAM_STATUS3_CLR                DIGCTL_OCRAM_STATUS3
+#define HWI_DIGCTL_OCRAM_STATUS3_CLR                
+#define HW_DIGCTL_OCRAM_STATUS3_TOG                 HW(DIGCTL_OCRAM_STATUS3_TOG)
+#define HWA_DIGCTL_OCRAM_STATUS3_TOG                (HWA_DIGCTL_OCRAM_STATUS3 + 0xc)
+#define HWT_DIGCTL_OCRAM_STATUS3_TOG                HWIO_32_WO
+#define HWN_DIGCTL_OCRAM_STATUS3_TOG                DIGCTL_OCRAM_STATUS3
+#define HWI_DIGCTL_OCRAM_STATUS3_TOG                
+#define BP_DIGCTL_OCRAM_STATUS3_FAILDATA11          0
+#define BM_DIGCTL_OCRAM_STATUS3_FAILDATA11          0xffffffff
+#define BF_DIGCTL_OCRAM_STATUS3_FAILDATA11(v)       (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_OCRAM_STATUS3_FAILDATA11(v)      BM_DIGCTL_OCRAM_STATUS3_FAILDATA11
+#define BF_DIGCTL_OCRAM_STATUS3_FAILDATA11_V(e)     BF_DIGCTL_OCRAM_STATUS3_FAILDATA11(BV_DIGCTL_OCRAM_STATUS3_FAILDATA11__##e)
+#define BFM_DIGCTL_OCRAM_STATUS3_FAILDATA11_V(v)    BM_DIGCTL_OCRAM_STATUS3_FAILDATA11
+
+#define HW_DIGCTL_OCRAM_STATUS4                     HW(DIGCTL_OCRAM_STATUS4)
+#define HWA_DIGCTL_OCRAM_STATUS4                    (0x8001c000 + 0x150)
+#define HWT_DIGCTL_OCRAM_STATUS4                    HWIO_32_RW
+#define HWN_DIGCTL_OCRAM_STATUS4                    DIGCTL_OCRAM_STATUS4
+#define HWI_DIGCTL_OCRAM_STATUS4                    
+#define HW_DIGCTL_OCRAM_STATUS4_SET                 HW(DIGCTL_OCRAM_STATUS4_SET)
+#define HWA_DIGCTL_OCRAM_STATUS4_SET                (HWA_DIGCTL_OCRAM_STATUS4 + 0x4)
+#define HWT_DIGCTL_OCRAM_STATUS4_SET                HWIO_32_WO
+#define HWN_DIGCTL_OCRAM_STATUS4_SET                DIGCTL_OCRAM_STATUS4
+#define HWI_DIGCTL_OCRAM_STATUS4_SET                
+#define HW_DIGCTL_OCRAM_STATUS4_CLR                 HW(DIGCTL_OCRAM_STATUS4_CLR)
+#define HWA_DIGCTL_OCRAM_STATUS4_CLR                (HWA_DIGCTL_OCRAM_STATUS4 + 0x8)
+#define HWT_DIGCTL_OCRAM_STATUS4_CLR                HWIO_32_WO
+#define HWN_DIGCTL_OCRAM_STATUS4_CLR                DIGCTL_OCRAM_STATUS4
+#define HWI_DIGCTL_OCRAM_STATUS4_CLR                
+#define HW_DIGCTL_OCRAM_STATUS4_TOG                 HW(DIGCTL_OCRAM_STATUS4_TOG)
+#define HWA_DIGCTL_OCRAM_STATUS4_TOG                (HWA_DIGCTL_OCRAM_STATUS4 + 0xc)
+#define HWT_DIGCTL_OCRAM_STATUS4_TOG                HWIO_32_WO
+#define HWN_DIGCTL_OCRAM_STATUS4_TOG                DIGCTL_OCRAM_STATUS4
+#define HWI_DIGCTL_OCRAM_STATUS4_TOG                
+#define BP_DIGCTL_OCRAM_STATUS4_FAILDATA20          0
+#define BM_DIGCTL_OCRAM_STATUS4_FAILDATA20          0xffffffff
+#define BF_DIGCTL_OCRAM_STATUS4_FAILDATA20(v)       (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_OCRAM_STATUS4_FAILDATA20(v)      BM_DIGCTL_OCRAM_STATUS4_FAILDATA20
+#define BF_DIGCTL_OCRAM_STATUS4_FAILDATA20_V(e)     BF_DIGCTL_OCRAM_STATUS4_FAILDATA20(BV_DIGCTL_OCRAM_STATUS4_FAILDATA20__##e)
+#define BFM_DIGCTL_OCRAM_STATUS4_FAILDATA20_V(v)    BM_DIGCTL_OCRAM_STATUS4_FAILDATA20
+
+#define HW_DIGCTL_OCRAM_STATUS5                     HW(DIGCTL_OCRAM_STATUS5)
+#define HWA_DIGCTL_OCRAM_STATUS5                    (0x8001c000 + 0x160)
+#define HWT_DIGCTL_OCRAM_STATUS5                    HWIO_32_RW
+#define HWN_DIGCTL_OCRAM_STATUS5                    DIGCTL_OCRAM_STATUS5
+#define HWI_DIGCTL_OCRAM_STATUS5                    
+#define HW_DIGCTL_OCRAM_STATUS5_SET                 HW(DIGCTL_OCRAM_STATUS5_SET)
+#define HWA_DIGCTL_OCRAM_STATUS5_SET                (HWA_DIGCTL_OCRAM_STATUS5 + 0x4)
+#define HWT_DIGCTL_OCRAM_STATUS5_SET                HWIO_32_WO
+#define HWN_DIGCTL_OCRAM_STATUS5_SET                DIGCTL_OCRAM_STATUS5
+#define HWI_DIGCTL_OCRAM_STATUS5_SET                
+#define HW_DIGCTL_OCRAM_STATUS5_CLR                 HW(DIGCTL_OCRAM_STATUS5_CLR)
+#define HWA_DIGCTL_OCRAM_STATUS5_CLR                (HWA_DIGCTL_OCRAM_STATUS5 + 0x8)
+#define HWT_DIGCTL_OCRAM_STATUS5_CLR                HWIO_32_WO
+#define HWN_DIGCTL_OCRAM_STATUS5_CLR                DIGCTL_OCRAM_STATUS5
+#define HWI_DIGCTL_OCRAM_STATUS5_CLR                
+#define HW_DIGCTL_OCRAM_STATUS5_TOG                 HW(DIGCTL_OCRAM_STATUS5_TOG)
+#define HWA_DIGCTL_OCRAM_STATUS5_TOG                (HWA_DIGCTL_OCRAM_STATUS5 + 0xc)
+#define HWT_DIGCTL_OCRAM_STATUS5_TOG                HWIO_32_WO
+#define HWN_DIGCTL_OCRAM_STATUS5_TOG                DIGCTL_OCRAM_STATUS5
+#define HWI_DIGCTL_OCRAM_STATUS5_TOG                
+#define BP_DIGCTL_OCRAM_STATUS5_FAILDATA21          0
+#define BM_DIGCTL_OCRAM_STATUS5_FAILDATA21          0xffffffff
+#define BF_DIGCTL_OCRAM_STATUS5_FAILDATA21(v)       (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_OCRAM_STATUS5_FAILDATA21(v)      BM_DIGCTL_OCRAM_STATUS5_FAILDATA21
+#define BF_DIGCTL_OCRAM_STATUS5_FAILDATA21_V(e)     BF_DIGCTL_OCRAM_STATUS5_FAILDATA21(BV_DIGCTL_OCRAM_STATUS5_FAILDATA21__##e)
+#define BFM_DIGCTL_OCRAM_STATUS5_FAILDATA21_V(v)    BM_DIGCTL_OCRAM_STATUS5_FAILDATA21
+
+#define HW_DIGCTL_OCRAM_STATUS6                     HW(DIGCTL_OCRAM_STATUS6)
+#define HWA_DIGCTL_OCRAM_STATUS6                    (0x8001c000 + 0x170)
+#define HWT_DIGCTL_OCRAM_STATUS6                    HWIO_32_RW
+#define HWN_DIGCTL_OCRAM_STATUS6                    DIGCTL_OCRAM_STATUS6
+#define HWI_DIGCTL_OCRAM_STATUS6                    
+#define HW_DIGCTL_OCRAM_STATUS6_SET                 HW(DIGCTL_OCRAM_STATUS6_SET)
+#define HWA_DIGCTL_OCRAM_STATUS6_SET                (HWA_DIGCTL_OCRAM_STATUS6 + 0x4)
+#define HWT_DIGCTL_OCRAM_STATUS6_SET                HWIO_32_WO
+#define HWN_DIGCTL_OCRAM_STATUS6_SET                DIGCTL_OCRAM_STATUS6
+#define HWI_DIGCTL_OCRAM_STATUS6_SET                
+#define HW_DIGCTL_OCRAM_STATUS6_CLR                 HW(DIGCTL_OCRAM_STATUS6_CLR)
+#define HWA_DIGCTL_OCRAM_STATUS6_CLR                (HWA_DIGCTL_OCRAM_STATUS6 + 0x8)
+#define HWT_DIGCTL_OCRAM_STATUS6_CLR                HWIO_32_WO
+#define HWN_DIGCTL_OCRAM_STATUS6_CLR                DIGCTL_OCRAM_STATUS6
+#define HWI_DIGCTL_OCRAM_STATUS6_CLR                
+#define HW_DIGCTL_OCRAM_STATUS6_TOG                 HW(DIGCTL_OCRAM_STATUS6_TOG)
+#define HWA_DIGCTL_OCRAM_STATUS6_TOG                (HWA_DIGCTL_OCRAM_STATUS6 + 0xc)
+#define HWT_DIGCTL_OCRAM_STATUS6_TOG                HWIO_32_WO
+#define HWN_DIGCTL_OCRAM_STATUS6_TOG                DIGCTL_OCRAM_STATUS6
+#define HWI_DIGCTL_OCRAM_STATUS6_TOG                
+#define BP_DIGCTL_OCRAM_STATUS6_FAILDATA30          0
+#define BM_DIGCTL_OCRAM_STATUS6_FAILDATA30          0xffffffff
+#define BF_DIGCTL_OCRAM_STATUS6_FAILDATA30(v)       (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_OCRAM_STATUS6_FAILDATA30(v)      BM_DIGCTL_OCRAM_STATUS6_FAILDATA30
+#define BF_DIGCTL_OCRAM_STATUS6_FAILDATA30_V(e)     BF_DIGCTL_OCRAM_STATUS6_FAILDATA30(BV_DIGCTL_OCRAM_STATUS6_FAILDATA30__##e)
+#define BFM_DIGCTL_OCRAM_STATUS6_FAILDATA30_V(v)    BM_DIGCTL_OCRAM_STATUS6_FAILDATA30
+
+#define HW_DIGCTL_OCRAM_STATUS7                     HW(DIGCTL_OCRAM_STATUS7)
+#define HWA_DIGCTL_OCRAM_STATUS7                    (0x8001c000 + 0x180)
+#define HWT_DIGCTL_OCRAM_STATUS7                    HWIO_32_RW
+#define HWN_DIGCTL_OCRAM_STATUS7                    DIGCTL_OCRAM_STATUS7
+#define HWI_DIGCTL_OCRAM_STATUS7                    
+#define HW_DIGCTL_OCRAM_STATUS7_SET                 HW(DIGCTL_OCRAM_STATUS7_SET)
+#define HWA_DIGCTL_OCRAM_STATUS7_SET                (HWA_DIGCTL_OCRAM_STATUS7 + 0x4)
+#define HWT_DIGCTL_OCRAM_STATUS7_SET                HWIO_32_WO
+#define HWN_DIGCTL_OCRAM_STATUS7_SET                DIGCTL_OCRAM_STATUS7
+#define HWI_DIGCTL_OCRAM_STATUS7_SET                
+#define HW_DIGCTL_OCRAM_STATUS7_CLR                 HW(DIGCTL_OCRAM_STATUS7_CLR)
+#define HWA_DIGCTL_OCRAM_STATUS7_CLR                (HWA_DIGCTL_OCRAM_STATUS7 + 0x8)
+#define HWT_DIGCTL_OCRAM_STATUS7_CLR                HWIO_32_WO
+#define HWN_DIGCTL_OCRAM_STATUS7_CLR                DIGCTL_OCRAM_STATUS7
+#define HWI_DIGCTL_OCRAM_STATUS7_CLR                
+#define HW_DIGCTL_OCRAM_STATUS7_TOG                 HW(DIGCTL_OCRAM_STATUS7_TOG)
+#define HWA_DIGCTL_OCRAM_STATUS7_TOG                (HWA_DIGCTL_OCRAM_STATUS7 + 0xc)
+#define HWT_DIGCTL_OCRAM_STATUS7_TOG                HWIO_32_WO
+#define HWN_DIGCTL_OCRAM_STATUS7_TOG                DIGCTL_OCRAM_STATUS7
+#define HWI_DIGCTL_OCRAM_STATUS7_TOG                
+#define BP_DIGCTL_OCRAM_STATUS7_FAILDATA31          0
+#define BM_DIGCTL_OCRAM_STATUS7_FAILDATA31          0xffffffff
+#define BF_DIGCTL_OCRAM_STATUS7_FAILDATA31(v)       (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_OCRAM_STATUS7_FAILDATA31(v)      BM_DIGCTL_OCRAM_STATUS7_FAILDATA31
+#define BF_DIGCTL_OCRAM_STATUS7_FAILDATA31_V(e)     BF_DIGCTL_OCRAM_STATUS7_FAILDATA31(BV_DIGCTL_OCRAM_STATUS7_FAILDATA31__##e)
+#define BFM_DIGCTL_OCRAM_STATUS7_FAILDATA31_V(v)    BM_DIGCTL_OCRAM_STATUS7_FAILDATA31
+
+#define HW_DIGCTL_OCRAM_STATUS8                     HW(DIGCTL_OCRAM_STATUS8)
+#define HWA_DIGCTL_OCRAM_STATUS8                    (0x8001c000 + 0x190)
+#define HWT_DIGCTL_OCRAM_STATUS8                    HWIO_32_RW
+#define HWN_DIGCTL_OCRAM_STATUS8                    DIGCTL_OCRAM_STATUS8
+#define HWI_DIGCTL_OCRAM_STATUS8                    
+#define HW_DIGCTL_OCRAM_STATUS8_SET                 HW(DIGCTL_OCRAM_STATUS8_SET)
+#define HWA_DIGCTL_OCRAM_STATUS8_SET                (HWA_DIGCTL_OCRAM_STATUS8 + 0x4)
+#define HWT_DIGCTL_OCRAM_STATUS8_SET                HWIO_32_WO
+#define HWN_DIGCTL_OCRAM_STATUS8_SET                DIGCTL_OCRAM_STATUS8
+#define HWI_DIGCTL_OCRAM_STATUS8_SET                
+#define HW_DIGCTL_OCRAM_STATUS8_CLR                 HW(DIGCTL_OCRAM_STATUS8_CLR)
+#define HWA_DIGCTL_OCRAM_STATUS8_CLR                (HWA_DIGCTL_OCRAM_STATUS8 + 0x8)
+#define HWT_DIGCTL_OCRAM_STATUS8_CLR                HWIO_32_WO
+#define HWN_DIGCTL_OCRAM_STATUS8_CLR                DIGCTL_OCRAM_STATUS8
+#define HWI_DIGCTL_OCRAM_STATUS8_CLR                
+#define HW_DIGCTL_OCRAM_STATUS8_TOG                 HW(DIGCTL_OCRAM_STATUS8_TOG)
+#define HWA_DIGCTL_OCRAM_STATUS8_TOG                (HWA_DIGCTL_OCRAM_STATUS8 + 0xc)
+#define HWT_DIGCTL_OCRAM_STATUS8_TOG                HWIO_32_WO
+#define HWN_DIGCTL_OCRAM_STATUS8_TOG                DIGCTL_OCRAM_STATUS8
+#define HWI_DIGCTL_OCRAM_STATUS8_TOG                
+#define BP_DIGCTL_OCRAM_STATUS8_RSVD3               29
+#define BM_DIGCTL_OCRAM_STATUS8_RSVD3               0xe0000000
+#define BF_DIGCTL_OCRAM_STATUS8_RSVD3(v)            (((v) & 0x7) << 29)
+#define BFM_DIGCTL_OCRAM_STATUS8_RSVD3(v)           BM_DIGCTL_OCRAM_STATUS8_RSVD3
+#define BF_DIGCTL_OCRAM_STATUS8_RSVD3_V(e)          BF_DIGCTL_OCRAM_STATUS8_RSVD3(BV_DIGCTL_OCRAM_STATUS8_RSVD3__##e)
+#define BFM_DIGCTL_OCRAM_STATUS8_RSVD3_V(v)         BM_DIGCTL_OCRAM_STATUS8_RSVD3
+#define BP_DIGCTL_OCRAM_STATUS8_FAILADDR01          16
+#define BM_DIGCTL_OCRAM_STATUS8_FAILADDR01          0x1fff0000
+#define BF_DIGCTL_OCRAM_STATUS8_FAILADDR01(v)       (((v) & 0x1fff) << 16)
+#define BFM_DIGCTL_OCRAM_STATUS8_FAILADDR01(v)      BM_DIGCTL_OCRAM_STATUS8_FAILADDR01
+#define BF_DIGCTL_OCRAM_STATUS8_FAILADDR01_V(e)     BF_DIGCTL_OCRAM_STATUS8_FAILADDR01(BV_DIGCTL_OCRAM_STATUS8_FAILADDR01__##e)
+#define BFM_DIGCTL_OCRAM_STATUS8_FAILADDR01_V(v)    BM_DIGCTL_OCRAM_STATUS8_FAILADDR01
+#define BP_DIGCTL_OCRAM_STATUS8_RSVD2               13
+#define BM_DIGCTL_OCRAM_STATUS8_RSVD2               0xe000
+#define BF_DIGCTL_OCRAM_STATUS8_RSVD2(v)            (((v) & 0x7) << 13)
+#define BFM_DIGCTL_OCRAM_STATUS8_RSVD2(v)           BM_DIGCTL_OCRAM_STATUS8_RSVD2
+#define BF_DIGCTL_OCRAM_STATUS8_RSVD2_V(e)          BF_DIGCTL_OCRAM_STATUS8_RSVD2(BV_DIGCTL_OCRAM_STATUS8_RSVD2__##e)
+#define BFM_DIGCTL_OCRAM_STATUS8_RSVD2_V(v)         BM_DIGCTL_OCRAM_STATUS8_RSVD2
+#define BP_DIGCTL_OCRAM_STATUS8_FAILADDR00          0
+#define BM_DIGCTL_OCRAM_STATUS8_FAILADDR00          0x1fff
+#define BF_DIGCTL_OCRAM_STATUS8_FAILADDR00(v)       (((v) & 0x1fff) << 0)
+#define BFM_DIGCTL_OCRAM_STATUS8_FAILADDR00(v)      BM_DIGCTL_OCRAM_STATUS8_FAILADDR00
+#define BF_DIGCTL_OCRAM_STATUS8_FAILADDR00_V(e)     BF_DIGCTL_OCRAM_STATUS8_FAILADDR00(BV_DIGCTL_OCRAM_STATUS8_FAILADDR00__##e)
+#define BFM_DIGCTL_OCRAM_STATUS8_FAILADDR00_V(v)    BM_DIGCTL_OCRAM_STATUS8_FAILADDR00
+
+#define HW_DIGCTL_OCRAM_STATUS9                     HW(DIGCTL_OCRAM_STATUS9)
+#define HWA_DIGCTL_OCRAM_STATUS9                    (0x8001c000 + 0x1a0)
+#define HWT_DIGCTL_OCRAM_STATUS9                    HWIO_32_RW
+#define HWN_DIGCTL_OCRAM_STATUS9                    DIGCTL_OCRAM_STATUS9
+#define HWI_DIGCTL_OCRAM_STATUS9                    
+#define HW_DIGCTL_OCRAM_STATUS9_SET                 HW(DIGCTL_OCRAM_STATUS9_SET)
+#define HWA_DIGCTL_OCRAM_STATUS9_SET                (HWA_DIGCTL_OCRAM_STATUS9 + 0x4)
+#define HWT_DIGCTL_OCRAM_STATUS9_SET                HWIO_32_WO
+#define HWN_DIGCTL_OCRAM_STATUS9_SET                DIGCTL_OCRAM_STATUS9
+#define HWI_DIGCTL_OCRAM_STATUS9_SET                
+#define HW_DIGCTL_OCRAM_STATUS9_CLR                 HW(DIGCTL_OCRAM_STATUS9_CLR)
+#define HWA_DIGCTL_OCRAM_STATUS9_CLR                (HWA_DIGCTL_OCRAM_STATUS9 + 0x8)
+#define HWT_DIGCTL_OCRAM_STATUS9_CLR                HWIO_32_WO
+#define HWN_DIGCTL_OCRAM_STATUS9_CLR                DIGCTL_OCRAM_STATUS9
+#define HWI_DIGCTL_OCRAM_STATUS9_CLR                
+#define HW_DIGCTL_OCRAM_STATUS9_TOG                 HW(DIGCTL_OCRAM_STATUS9_TOG)
+#define HWA_DIGCTL_OCRAM_STATUS9_TOG                (HWA_DIGCTL_OCRAM_STATUS9 + 0xc)
+#define HWT_DIGCTL_OCRAM_STATUS9_TOG                HWIO_32_WO
+#define HWN_DIGCTL_OCRAM_STATUS9_TOG                DIGCTL_OCRAM_STATUS9
+#define HWI_DIGCTL_OCRAM_STATUS9_TOG                
+#define BP_DIGCTL_OCRAM_STATUS9_RSVD3               29
+#define BM_DIGCTL_OCRAM_STATUS9_RSVD3               0xe0000000
+#define BF_DIGCTL_OCRAM_STATUS9_RSVD3(v)            (((v) & 0x7) << 29)
+#define BFM_DIGCTL_OCRAM_STATUS9_RSVD3(v)           BM_DIGCTL_OCRAM_STATUS9_RSVD3
+#define BF_DIGCTL_OCRAM_STATUS9_RSVD3_V(e)          BF_DIGCTL_OCRAM_STATUS9_RSVD3(BV_DIGCTL_OCRAM_STATUS9_RSVD3__##e)
+#define BFM_DIGCTL_OCRAM_STATUS9_RSVD3_V(v)         BM_DIGCTL_OCRAM_STATUS9_RSVD3
+#define BP_DIGCTL_OCRAM_STATUS9_FAILADDR11          16
+#define BM_DIGCTL_OCRAM_STATUS9_FAILADDR11          0x1fff0000
+#define BF_DIGCTL_OCRAM_STATUS9_FAILADDR11(v)       (((v) & 0x1fff) << 16)
+#define BFM_DIGCTL_OCRAM_STATUS9_FAILADDR11(v)      BM_DIGCTL_OCRAM_STATUS9_FAILADDR11
+#define BF_DIGCTL_OCRAM_STATUS9_FAILADDR11_V(e)     BF_DIGCTL_OCRAM_STATUS9_FAILADDR11(BV_DIGCTL_OCRAM_STATUS9_FAILADDR11__##e)
+#define BFM_DIGCTL_OCRAM_STATUS9_FAILADDR11_V(v)    BM_DIGCTL_OCRAM_STATUS9_FAILADDR11
+#define BP_DIGCTL_OCRAM_STATUS9_RSVD2               13
+#define BM_DIGCTL_OCRAM_STATUS9_RSVD2               0xe000
+#define BF_DIGCTL_OCRAM_STATUS9_RSVD2(v)            (((v) & 0x7) << 13)
+#define BFM_DIGCTL_OCRAM_STATUS9_RSVD2(v)           BM_DIGCTL_OCRAM_STATUS9_RSVD2
+#define BF_DIGCTL_OCRAM_STATUS9_RSVD2_V(e)          BF_DIGCTL_OCRAM_STATUS9_RSVD2(BV_DIGCTL_OCRAM_STATUS9_RSVD2__##e)
+#define BFM_DIGCTL_OCRAM_STATUS9_RSVD2_V(v)         BM_DIGCTL_OCRAM_STATUS9_RSVD2
+#define BP_DIGCTL_OCRAM_STATUS9_FAILADDR10          0
+#define BM_DIGCTL_OCRAM_STATUS9_FAILADDR10          0x1fff
+#define BF_DIGCTL_OCRAM_STATUS9_FAILADDR10(v)       (((v) & 0x1fff) << 0)
+#define BFM_DIGCTL_OCRAM_STATUS9_FAILADDR10(v)      BM_DIGCTL_OCRAM_STATUS9_FAILADDR10
+#define BF_DIGCTL_OCRAM_STATUS9_FAILADDR10_V(e)     BF_DIGCTL_OCRAM_STATUS9_FAILADDR10(BV_DIGCTL_OCRAM_STATUS9_FAILADDR10__##e)
+#define BFM_DIGCTL_OCRAM_STATUS9_FAILADDR10_V(v)    BM_DIGCTL_OCRAM_STATUS9_FAILADDR10
+
+#define HW_DIGCTL_OCRAM_STATUS10                    HW(DIGCTL_OCRAM_STATUS10)
+#define HWA_DIGCTL_OCRAM_STATUS10                   (0x8001c000 + 0x1b0)
+#define HWT_DIGCTL_OCRAM_STATUS10                   HWIO_32_RW
+#define HWN_DIGCTL_OCRAM_STATUS10                   DIGCTL_OCRAM_STATUS10
+#define HWI_DIGCTL_OCRAM_STATUS10                   
+#define HW_DIGCTL_OCRAM_STATUS10_SET                HW(DIGCTL_OCRAM_STATUS10_SET)
+#define HWA_DIGCTL_OCRAM_STATUS10_SET               (HWA_DIGCTL_OCRAM_STATUS10 + 0x4)
+#define HWT_DIGCTL_OCRAM_STATUS10_SET               HWIO_32_WO
+#define HWN_DIGCTL_OCRAM_STATUS10_SET               DIGCTL_OCRAM_STATUS10
+#define HWI_DIGCTL_OCRAM_STATUS10_SET               
+#define HW_DIGCTL_OCRAM_STATUS10_CLR                HW(DIGCTL_OCRAM_STATUS10_CLR)
+#define HWA_DIGCTL_OCRAM_STATUS10_CLR               (HWA_DIGCTL_OCRAM_STATUS10 + 0x8)
+#define HWT_DIGCTL_OCRAM_STATUS10_CLR               HWIO_32_WO
+#define HWN_DIGCTL_OCRAM_STATUS10_CLR               DIGCTL_OCRAM_STATUS10
+#define HWI_DIGCTL_OCRAM_STATUS10_CLR               
+#define HW_DIGCTL_OCRAM_STATUS10_TOG                HW(DIGCTL_OCRAM_STATUS10_TOG)
+#define HWA_DIGCTL_OCRAM_STATUS10_TOG               (HWA_DIGCTL_OCRAM_STATUS10 + 0xc)
+#define HWT_DIGCTL_OCRAM_STATUS10_TOG               HWIO_32_WO
+#define HWN_DIGCTL_OCRAM_STATUS10_TOG               DIGCTL_OCRAM_STATUS10
+#define HWI_DIGCTL_OCRAM_STATUS10_TOG               
+#define BP_DIGCTL_OCRAM_STATUS10_RSVD3              29
+#define BM_DIGCTL_OCRAM_STATUS10_RSVD3              0xe0000000
+#define BF_DIGCTL_OCRAM_STATUS10_RSVD3(v)           (((v) & 0x7) << 29)
+#define BFM_DIGCTL_OCRAM_STATUS10_RSVD3(v)          BM_DIGCTL_OCRAM_STATUS10_RSVD3
+#define BF_DIGCTL_OCRAM_STATUS10_RSVD3_V(e)         BF_DIGCTL_OCRAM_STATUS10_RSVD3(BV_DIGCTL_OCRAM_STATUS10_RSVD3__##e)
+#define BFM_DIGCTL_OCRAM_STATUS10_RSVD3_V(v)        BM_DIGCTL_OCRAM_STATUS10_RSVD3
+#define BP_DIGCTL_OCRAM_STATUS10_FAILADDR21         16
+#define BM_DIGCTL_OCRAM_STATUS10_FAILADDR21         0x1fff0000
+#define BF_DIGCTL_OCRAM_STATUS10_FAILADDR21(v)      (((v) & 0x1fff) << 16)
+#define BFM_DIGCTL_OCRAM_STATUS10_FAILADDR21(v)     BM_DIGCTL_OCRAM_STATUS10_FAILADDR21
+#define BF_DIGCTL_OCRAM_STATUS10_FAILADDR21_V(e)    BF_DIGCTL_OCRAM_STATUS10_FAILADDR21(BV_DIGCTL_OCRAM_STATUS10_FAILADDR21__##e)
+#define BFM_DIGCTL_OCRAM_STATUS10_FAILADDR21_V(v)   BM_DIGCTL_OCRAM_STATUS10_FAILADDR21
+#define BP_DIGCTL_OCRAM_STATUS10_RSVD2              13
+#define BM_DIGCTL_OCRAM_STATUS10_RSVD2              0xe000
+#define BF_DIGCTL_OCRAM_STATUS10_RSVD2(v)           (((v) & 0x7) << 13)
+#define BFM_DIGCTL_OCRAM_STATUS10_RSVD2(v)          BM_DIGCTL_OCRAM_STATUS10_RSVD2
+#define BF_DIGCTL_OCRAM_STATUS10_RSVD2_V(e)         BF_DIGCTL_OCRAM_STATUS10_RSVD2(BV_DIGCTL_OCRAM_STATUS10_RSVD2__##e)
+#define BFM_DIGCTL_OCRAM_STATUS10_RSVD2_V(v)        BM_DIGCTL_OCRAM_STATUS10_RSVD2
+#define BP_DIGCTL_OCRAM_STATUS10_FAILADDR20         0
+#define BM_DIGCTL_OCRAM_STATUS10_FAILADDR20         0x1fff
+#define BF_DIGCTL_OCRAM_STATUS10_FAILADDR20(v)      (((v) & 0x1fff) << 0)
+#define BFM_DIGCTL_OCRAM_STATUS10_FAILADDR20(v)     BM_DIGCTL_OCRAM_STATUS10_FAILADDR20
+#define BF_DIGCTL_OCRAM_STATUS10_FAILADDR20_V(e)    BF_DIGCTL_OCRAM_STATUS10_FAILADDR20(BV_DIGCTL_OCRAM_STATUS10_FAILADDR20__##e)
+#define BFM_DIGCTL_OCRAM_STATUS10_FAILADDR20_V(v)   BM_DIGCTL_OCRAM_STATUS10_FAILADDR20
+
+#define HW_DIGCTL_OCRAM_STATUS11                    HW(DIGCTL_OCRAM_STATUS11)
+#define HWA_DIGCTL_OCRAM_STATUS11                   (0x8001c000 + 0x1c0)
+#define HWT_DIGCTL_OCRAM_STATUS11                   HWIO_32_RW
+#define HWN_DIGCTL_OCRAM_STATUS11                   DIGCTL_OCRAM_STATUS11
+#define HWI_DIGCTL_OCRAM_STATUS11                   
+#define HW_DIGCTL_OCRAM_STATUS11_SET                HW(DIGCTL_OCRAM_STATUS11_SET)
+#define HWA_DIGCTL_OCRAM_STATUS11_SET               (HWA_DIGCTL_OCRAM_STATUS11 + 0x4)
+#define HWT_DIGCTL_OCRAM_STATUS11_SET               HWIO_32_WO
+#define HWN_DIGCTL_OCRAM_STATUS11_SET               DIGCTL_OCRAM_STATUS11
+#define HWI_DIGCTL_OCRAM_STATUS11_SET               
+#define HW_DIGCTL_OCRAM_STATUS11_CLR                HW(DIGCTL_OCRAM_STATUS11_CLR)
+#define HWA_DIGCTL_OCRAM_STATUS11_CLR               (HWA_DIGCTL_OCRAM_STATUS11 + 0x8)
+#define HWT_DIGCTL_OCRAM_STATUS11_CLR               HWIO_32_WO
+#define HWN_DIGCTL_OCRAM_STATUS11_CLR               DIGCTL_OCRAM_STATUS11
+#define HWI_DIGCTL_OCRAM_STATUS11_CLR               
+#define HW_DIGCTL_OCRAM_STATUS11_TOG                HW(DIGCTL_OCRAM_STATUS11_TOG)
+#define HWA_DIGCTL_OCRAM_STATUS11_TOG               (HWA_DIGCTL_OCRAM_STATUS11 + 0xc)
+#define HWT_DIGCTL_OCRAM_STATUS11_TOG               HWIO_32_WO
+#define HWN_DIGCTL_OCRAM_STATUS11_TOG               DIGCTL_OCRAM_STATUS11
+#define HWI_DIGCTL_OCRAM_STATUS11_TOG               
+#define BP_DIGCTL_OCRAM_STATUS11_RSVD3              29
+#define BM_DIGCTL_OCRAM_STATUS11_RSVD3              0xe0000000
+#define BF_DIGCTL_OCRAM_STATUS11_RSVD3(v)           (((v) & 0x7) << 29)
+#define BFM_DIGCTL_OCRAM_STATUS11_RSVD3(v)          BM_DIGCTL_OCRAM_STATUS11_RSVD3
+#define BF_DIGCTL_OCRAM_STATUS11_RSVD3_V(e)         BF_DIGCTL_OCRAM_STATUS11_RSVD3(BV_DIGCTL_OCRAM_STATUS11_RSVD3__##e)
+#define BFM_DIGCTL_OCRAM_STATUS11_RSVD3_V(v)        BM_DIGCTL_OCRAM_STATUS11_RSVD3
+#define BP_DIGCTL_OCRAM_STATUS11_FAILADDR31         16
+#define BM_DIGCTL_OCRAM_STATUS11_FAILADDR31         0x1fff0000
+#define BF_DIGCTL_OCRAM_STATUS11_FAILADDR31(v)      (((v) & 0x1fff) << 16)
+#define BFM_DIGCTL_OCRAM_STATUS11_FAILADDR31(v)     BM_DIGCTL_OCRAM_STATUS11_FAILADDR31
+#define BF_DIGCTL_OCRAM_STATUS11_FAILADDR31_V(e)    BF_DIGCTL_OCRAM_STATUS11_FAILADDR31(BV_DIGCTL_OCRAM_STATUS11_FAILADDR31__##e)
+#define BFM_DIGCTL_OCRAM_STATUS11_FAILADDR31_V(v)   BM_DIGCTL_OCRAM_STATUS11_FAILADDR31
+#define BP_DIGCTL_OCRAM_STATUS11_RSVD2              13
+#define BM_DIGCTL_OCRAM_STATUS11_RSVD2              0xe000
+#define BF_DIGCTL_OCRAM_STATUS11_RSVD2(v)           (((v) & 0x7) << 13)
+#define BFM_DIGCTL_OCRAM_STATUS11_RSVD2(v)          BM_DIGCTL_OCRAM_STATUS11_RSVD2
+#define BF_DIGCTL_OCRAM_STATUS11_RSVD2_V(e)         BF_DIGCTL_OCRAM_STATUS11_RSVD2(BV_DIGCTL_OCRAM_STATUS11_RSVD2__##e)
+#define BFM_DIGCTL_OCRAM_STATUS11_RSVD2_V(v)        BM_DIGCTL_OCRAM_STATUS11_RSVD2
+#define BP_DIGCTL_OCRAM_STATUS11_FAILADDR30         0
+#define BM_DIGCTL_OCRAM_STATUS11_FAILADDR30         0x1fff
+#define BF_DIGCTL_OCRAM_STATUS11_FAILADDR30(v)      (((v) & 0x1fff) << 0)
+#define BFM_DIGCTL_OCRAM_STATUS11_FAILADDR30(v)     BM_DIGCTL_OCRAM_STATUS11_FAILADDR30
+#define BF_DIGCTL_OCRAM_STATUS11_FAILADDR30_V(e)    BF_DIGCTL_OCRAM_STATUS11_FAILADDR30(BV_DIGCTL_OCRAM_STATUS11_FAILADDR30__##e)
+#define BFM_DIGCTL_OCRAM_STATUS11_FAILADDR30_V(v)   BM_DIGCTL_OCRAM_STATUS11_FAILADDR30
+
+#define HW_DIGCTL_OCRAM_STATUS12                    HW(DIGCTL_OCRAM_STATUS12)
+#define HWA_DIGCTL_OCRAM_STATUS12                   (0x8001c000 + 0x1d0)
+#define HWT_DIGCTL_OCRAM_STATUS12                   HWIO_32_RW
+#define HWN_DIGCTL_OCRAM_STATUS12                   DIGCTL_OCRAM_STATUS12
+#define HWI_DIGCTL_OCRAM_STATUS12                   
+#define HW_DIGCTL_OCRAM_STATUS12_SET                HW(DIGCTL_OCRAM_STATUS12_SET)
+#define HWA_DIGCTL_OCRAM_STATUS12_SET               (HWA_DIGCTL_OCRAM_STATUS12 + 0x4)
+#define HWT_DIGCTL_OCRAM_STATUS12_SET               HWIO_32_WO
+#define HWN_DIGCTL_OCRAM_STATUS12_SET               DIGCTL_OCRAM_STATUS12
+#define HWI_DIGCTL_OCRAM_STATUS12_SET               
+#define HW_DIGCTL_OCRAM_STATUS12_CLR                HW(DIGCTL_OCRAM_STATUS12_CLR)
+#define HWA_DIGCTL_OCRAM_STATUS12_CLR               (HWA_DIGCTL_OCRAM_STATUS12 + 0x8)
+#define HWT_DIGCTL_OCRAM_STATUS12_CLR               HWIO_32_WO
+#define HWN_DIGCTL_OCRAM_STATUS12_CLR               DIGCTL_OCRAM_STATUS12
+#define HWI_DIGCTL_OCRAM_STATUS12_CLR               
+#define HW_DIGCTL_OCRAM_STATUS12_TOG                HW(DIGCTL_OCRAM_STATUS12_TOG)
+#define HWA_DIGCTL_OCRAM_STATUS12_TOG               (HWA_DIGCTL_OCRAM_STATUS12 + 0xc)
+#define HWT_DIGCTL_OCRAM_STATUS12_TOG               HWIO_32_WO
+#define HWN_DIGCTL_OCRAM_STATUS12_TOG               DIGCTL_OCRAM_STATUS12
+#define HWI_DIGCTL_OCRAM_STATUS12_TOG               
+#define BP_DIGCTL_OCRAM_STATUS12_RSVD3              28
+#define BM_DIGCTL_OCRAM_STATUS12_RSVD3              0xf0000000
+#define BF_DIGCTL_OCRAM_STATUS12_RSVD3(v)           (((v) & 0xf) << 28)
+#define BFM_DIGCTL_OCRAM_STATUS12_RSVD3(v)          BM_DIGCTL_OCRAM_STATUS12_RSVD3
+#define BF_DIGCTL_OCRAM_STATUS12_RSVD3_V(e)         BF_DIGCTL_OCRAM_STATUS12_RSVD3(BV_DIGCTL_OCRAM_STATUS12_RSVD3__##e)
+#define BFM_DIGCTL_OCRAM_STATUS12_RSVD3_V(v)        BM_DIGCTL_OCRAM_STATUS12_RSVD3
+#define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE11        24
+#define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE11        0xf000000
+#define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE11(v)     (((v) & 0xf) << 24)
+#define BFM_DIGCTL_OCRAM_STATUS12_FAILSTATE11(v)    BM_DIGCTL_OCRAM_STATUS12_FAILSTATE11
+#define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE11_V(e)   BF_DIGCTL_OCRAM_STATUS12_FAILSTATE11(BV_DIGCTL_OCRAM_STATUS12_FAILSTATE11__##e)
+#define BFM_DIGCTL_OCRAM_STATUS12_FAILSTATE11_V(v)  BM_DIGCTL_OCRAM_STATUS12_FAILSTATE11
+#define BP_DIGCTL_OCRAM_STATUS12_RSVD2              20
+#define BM_DIGCTL_OCRAM_STATUS12_RSVD2              0xf00000
+#define BF_DIGCTL_OCRAM_STATUS12_RSVD2(v)           (((v) & 0xf) << 20)
+#define BFM_DIGCTL_OCRAM_STATUS12_RSVD2(v)          BM_DIGCTL_OCRAM_STATUS12_RSVD2
+#define BF_DIGCTL_OCRAM_STATUS12_RSVD2_V(e)         BF_DIGCTL_OCRAM_STATUS12_RSVD2(BV_DIGCTL_OCRAM_STATUS12_RSVD2__##e)
+#define BFM_DIGCTL_OCRAM_STATUS12_RSVD2_V(v)        BM_DIGCTL_OCRAM_STATUS12_RSVD2
+#define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE10        16
+#define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE10        0xf0000
+#define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE10(v)     (((v) & 0xf) << 16)
+#define BFM_DIGCTL_OCRAM_STATUS12_FAILSTATE10(v)    BM_DIGCTL_OCRAM_STATUS12_FAILSTATE10
+#define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE10_V(e)   BF_DIGCTL_OCRAM_STATUS12_FAILSTATE10(BV_DIGCTL_OCRAM_STATUS12_FAILSTATE10__##e)
+#define BFM_DIGCTL_OCRAM_STATUS12_FAILSTATE10_V(v)  BM_DIGCTL_OCRAM_STATUS12_FAILSTATE10
+#define BP_DIGCTL_OCRAM_STATUS12_RSVD1              12
+#define BM_DIGCTL_OCRAM_STATUS12_RSVD1              0xf000
+#define BF_DIGCTL_OCRAM_STATUS12_RSVD1(v)           (((v) & 0xf) << 12)
+#define BFM_DIGCTL_OCRAM_STATUS12_RSVD1(v)          BM_DIGCTL_OCRAM_STATUS12_RSVD1
+#define BF_DIGCTL_OCRAM_STATUS12_RSVD1_V(e)         BF_DIGCTL_OCRAM_STATUS12_RSVD1(BV_DIGCTL_OCRAM_STATUS12_RSVD1__##e)
+#define BFM_DIGCTL_OCRAM_STATUS12_RSVD1_V(v)        BM_DIGCTL_OCRAM_STATUS12_RSVD1
+#define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE01        8
+#define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE01        0xf00
+#define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE01(v)     (((v) & 0xf) << 8)
+#define BFM_DIGCTL_OCRAM_STATUS12_FAILSTATE01(v)    BM_DIGCTL_OCRAM_STATUS12_FAILSTATE01
+#define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE01_V(e)   BF_DIGCTL_OCRAM_STATUS12_FAILSTATE01(BV_DIGCTL_OCRAM_STATUS12_FAILSTATE01__##e)
+#define BFM_DIGCTL_OCRAM_STATUS12_FAILSTATE01_V(v)  BM_DIGCTL_OCRAM_STATUS12_FAILSTATE01
+#define BP_DIGCTL_OCRAM_STATUS12_RSVD0              4
+#define BM_DIGCTL_OCRAM_STATUS12_RSVD0              0xf0
+#define BF_DIGCTL_OCRAM_STATUS12_RSVD0(v)           (((v) & 0xf) << 4)
+#define BFM_DIGCTL_OCRAM_STATUS12_RSVD0(v)          BM_DIGCTL_OCRAM_STATUS12_RSVD0
+#define BF_DIGCTL_OCRAM_STATUS12_RSVD0_V(e)         BF_DIGCTL_OCRAM_STATUS12_RSVD0(BV_DIGCTL_OCRAM_STATUS12_RSVD0__##e)
+#define BFM_DIGCTL_OCRAM_STATUS12_RSVD0_V(v)        BM_DIGCTL_OCRAM_STATUS12_RSVD0
+#define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE00        0
+#define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE00        0xf
+#define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE00(v)     (((v) & 0xf) << 0)
+#define BFM_DIGCTL_OCRAM_STATUS12_FAILSTATE00(v)    BM_DIGCTL_OCRAM_STATUS12_FAILSTATE00
+#define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE00_V(e)   BF_DIGCTL_OCRAM_STATUS12_FAILSTATE00(BV_DIGCTL_OCRAM_STATUS12_FAILSTATE00__##e)
+#define BFM_DIGCTL_OCRAM_STATUS12_FAILSTATE00_V(v)  BM_DIGCTL_OCRAM_STATUS12_FAILSTATE00
+
+#define HW_DIGCTL_OCRAM_STATUS13                    HW(DIGCTL_OCRAM_STATUS13)
+#define HWA_DIGCTL_OCRAM_STATUS13                   (0x8001c000 + 0x1e0)
+#define HWT_DIGCTL_OCRAM_STATUS13                   HWIO_32_RW
+#define HWN_DIGCTL_OCRAM_STATUS13                   DIGCTL_OCRAM_STATUS13
+#define HWI_DIGCTL_OCRAM_STATUS13                   
+#define HW_DIGCTL_OCRAM_STATUS13_SET                HW(DIGCTL_OCRAM_STATUS13_SET)
+#define HWA_DIGCTL_OCRAM_STATUS13_SET               (HWA_DIGCTL_OCRAM_STATUS13 + 0x4)
+#define HWT_DIGCTL_OCRAM_STATUS13_SET               HWIO_32_WO
+#define HWN_DIGCTL_OCRAM_STATUS13_SET               DIGCTL_OCRAM_STATUS13
+#define HWI_DIGCTL_OCRAM_STATUS13_SET               
+#define HW_DIGCTL_OCRAM_STATUS13_CLR                HW(DIGCTL_OCRAM_STATUS13_CLR)
+#define HWA_DIGCTL_OCRAM_STATUS13_CLR               (HWA_DIGCTL_OCRAM_STATUS13 + 0x8)
+#define HWT_DIGCTL_OCRAM_STATUS13_CLR               HWIO_32_WO
+#define HWN_DIGCTL_OCRAM_STATUS13_CLR               DIGCTL_OCRAM_STATUS13
+#define HWI_DIGCTL_OCRAM_STATUS13_CLR               
+#define HW_DIGCTL_OCRAM_STATUS13_TOG                HW(DIGCTL_OCRAM_STATUS13_TOG)
+#define HWA_DIGCTL_OCRAM_STATUS13_TOG               (HWA_DIGCTL_OCRAM_STATUS13 + 0xc)
+#define HWT_DIGCTL_OCRAM_STATUS13_TOG               HWIO_32_WO
+#define HWN_DIGCTL_OCRAM_STATUS13_TOG               DIGCTL_OCRAM_STATUS13
+#define HWI_DIGCTL_OCRAM_STATUS13_TOG               
+#define BP_DIGCTL_OCRAM_STATUS13_RSVD3              28
+#define BM_DIGCTL_OCRAM_STATUS13_RSVD3              0xf0000000
+#define BF_DIGCTL_OCRAM_STATUS13_RSVD3(v)           (((v) & 0xf) << 28)
+#define BFM_DIGCTL_OCRAM_STATUS13_RSVD3(v)          BM_DIGCTL_OCRAM_STATUS13_RSVD3
+#define BF_DIGCTL_OCRAM_STATUS13_RSVD3_V(e)         BF_DIGCTL_OCRAM_STATUS13_RSVD3(BV_DIGCTL_OCRAM_STATUS13_RSVD3__##e)
+#define BFM_DIGCTL_OCRAM_STATUS13_RSVD3_V(v)        BM_DIGCTL_OCRAM_STATUS13_RSVD3
+#define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE31        24
+#define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE31        0xf000000
+#define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE31(v)     (((v) & 0xf) << 24)
+#define BFM_DIGCTL_OCRAM_STATUS13_FAILSTATE31(v)    BM_DIGCTL_OCRAM_STATUS13_FAILSTATE31
+#define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE31_V(e)   BF_DIGCTL_OCRAM_STATUS13_FAILSTATE31(BV_DIGCTL_OCRAM_STATUS13_FAILSTATE31__##e)
+#define BFM_DIGCTL_OCRAM_STATUS13_FAILSTATE31_V(v)  BM_DIGCTL_OCRAM_STATUS13_FAILSTATE31
+#define BP_DIGCTL_OCRAM_STATUS13_RSVD2              20
+#define BM_DIGCTL_OCRAM_STATUS13_RSVD2              0xf00000
+#define BF_DIGCTL_OCRAM_STATUS13_RSVD2(v)           (((v) & 0xf) << 20)
+#define BFM_DIGCTL_OCRAM_STATUS13_RSVD2(v)          BM_DIGCTL_OCRAM_STATUS13_RSVD2
+#define BF_DIGCTL_OCRAM_STATUS13_RSVD2_V(e)         BF_DIGCTL_OCRAM_STATUS13_RSVD2(BV_DIGCTL_OCRAM_STATUS13_RSVD2__##e)
+#define BFM_DIGCTL_OCRAM_STATUS13_RSVD2_V(v)        BM_DIGCTL_OCRAM_STATUS13_RSVD2
+#define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE30        16
+#define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE30        0xf0000
+#define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE30(v)     (((v) & 0xf) << 16)
+#define BFM_DIGCTL_OCRAM_STATUS13_FAILSTATE30(v)    BM_DIGCTL_OCRAM_STATUS13_FAILSTATE30
+#define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE30_V(e)   BF_DIGCTL_OCRAM_STATUS13_FAILSTATE30(BV_DIGCTL_OCRAM_STATUS13_FAILSTATE30__##e)
+#define BFM_DIGCTL_OCRAM_STATUS13_FAILSTATE30_V(v)  BM_DIGCTL_OCRAM_STATUS13_FAILSTATE30
+#define BP_DIGCTL_OCRAM_STATUS13_RSVD1              12
+#define BM_DIGCTL_OCRAM_STATUS13_RSVD1              0xf000
+#define BF_DIGCTL_OCRAM_STATUS13_RSVD1(v)           (((v) & 0xf) << 12)
+#define BFM_DIGCTL_OCRAM_STATUS13_RSVD1(v)          BM_DIGCTL_OCRAM_STATUS13_RSVD1
+#define BF_DIGCTL_OCRAM_STATUS13_RSVD1_V(e)         BF_DIGCTL_OCRAM_STATUS13_RSVD1(BV_DIGCTL_OCRAM_STATUS13_RSVD1__##e)
+#define BFM_DIGCTL_OCRAM_STATUS13_RSVD1_V(v)        BM_DIGCTL_OCRAM_STATUS13_RSVD1
+#define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE21        8
+#define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE21        0xf00
+#define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE21(v)     (((v) & 0xf) << 8)
+#define BFM_DIGCTL_OCRAM_STATUS13_FAILSTATE21(v)    BM_DIGCTL_OCRAM_STATUS13_FAILSTATE21
+#define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE21_V(e)   BF_DIGCTL_OCRAM_STATUS13_FAILSTATE21(BV_DIGCTL_OCRAM_STATUS13_FAILSTATE21__##e)
+#define BFM_DIGCTL_OCRAM_STATUS13_FAILSTATE21_V(v)  BM_DIGCTL_OCRAM_STATUS13_FAILSTATE21
+#define BP_DIGCTL_OCRAM_STATUS13_RSVD0              4
+#define BM_DIGCTL_OCRAM_STATUS13_RSVD0              0xf0
+#define BF_DIGCTL_OCRAM_STATUS13_RSVD0(v)           (((v) & 0xf) << 4)
+#define BFM_DIGCTL_OCRAM_STATUS13_RSVD0(v)          BM_DIGCTL_OCRAM_STATUS13_RSVD0
+#define BF_DIGCTL_OCRAM_STATUS13_RSVD0_V(e)         BF_DIGCTL_OCRAM_STATUS13_RSVD0(BV_DIGCTL_OCRAM_STATUS13_RSVD0__##e)
+#define BFM_DIGCTL_OCRAM_STATUS13_RSVD0_V(v)        BM_DIGCTL_OCRAM_STATUS13_RSVD0
+#define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE20        0
+#define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE20        0xf
+#define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE20(v)     (((v) & 0xf) << 0)
+#define BFM_DIGCTL_OCRAM_STATUS13_FAILSTATE20(v)    BM_DIGCTL_OCRAM_STATUS13_FAILSTATE20
+#define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE20_V(e)   BF_DIGCTL_OCRAM_STATUS13_FAILSTATE20(BV_DIGCTL_OCRAM_STATUS13_FAILSTATE20__##e)
+#define BFM_DIGCTL_OCRAM_STATUS13_FAILSTATE20_V(v)  BM_DIGCTL_OCRAM_STATUS13_FAILSTATE20
+
+#define HW_DIGCTL_SCRATCH0              HW(DIGCTL_SCRATCH0)
+#define HWA_DIGCTL_SCRATCH0             (0x8001c000 + 0x290)
+#define HWT_DIGCTL_SCRATCH0             HWIO_32_RW
+#define HWN_DIGCTL_SCRATCH0             DIGCTL_SCRATCH0
+#define HWI_DIGCTL_SCRATCH0             
+#define BP_DIGCTL_SCRATCH0_PTR          0
+#define BM_DIGCTL_SCRATCH0_PTR          0xffffffff
+#define BF_DIGCTL_SCRATCH0_PTR(v)       (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_SCRATCH0_PTR(v)      BM_DIGCTL_SCRATCH0_PTR
+#define BF_DIGCTL_SCRATCH0_PTR_V(e)     BF_DIGCTL_SCRATCH0_PTR(BV_DIGCTL_SCRATCH0_PTR__##e)
+#define BFM_DIGCTL_SCRATCH0_PTR_V(v)    BM_DIGCTL_SCRATCH0_PTR
+
+#define HW_DIGCTL_SCRATCH1              HW(DIGCTL_SCRATCH1)
+#define HWA_DIGCTL_SCRATCH1             (0x8001c000 + 0x2a0)
+#define HWT_DIGCTL_SCRATCH1             HWIO_32_RW
+#define HWN_DIGCTL_SCRATCH1             DIGCTL_SCRATCH1
+#define HWI_DIGCTL_SCRATCH1             
+#define BP_DIGCTL_SCRATCH1_PTR          0
+#define BM_DIGCTL_SCRATCH1_PTR          0xffffffff
+#define BF_DIGCTL_SCRATCH1_PTR(v)       (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_SCRATCH1_PTR(v)      BM_DIGCTL_SCRATCH1_PTR
+#define BF_DIGCTL_SCRATCH1_PTR_V(e)     BF_DIGCTL_SCRATCH1_PTR(BV_DIGCTL_SCRATCH1_PTR__##e)
+#define BFM_DIGCTL_SCRATCH1_PTR_V(v)    BM_DIGCTL_SCRATCH1_PTR
+
+#define HW_DIGCTL_ARMCACHE                  HW(DIGCTL_ARMCACHE)
+#define HWA_DIGCTL_ARMCACHE                 (0x8001c000 + 0x2b0)
+#define HWT_DIGCTL_ARMCACHE                 HWIO_32_RW
+#define HWN_DIGCTL_ARMCACHE                 DIGCTL_ARMCACHE
+#define HWI_DIGCTL_ARMCACHE                 
+#define BP_DIGCTL_ARMCACHE_RSVD4            18
+#define BM_DIGCTL_ARMCACHE_RSVD4            0xfffc0000
+#define BF_DIGCTL_ARMCACHE_RSVD4(v)         (((v) & 0x3fff) << 18)
+#define BFM_DIGCTL_ARMCACHE_RSVD4(v)        BM_DIGCTL_ARMCACHE_RSVD4
+#define BF_DIGCTL_ARMCACHE_RSVD4_V(e)       BF_DIGCTL_ARMCACHE_RSVD4(BV_DIGCTL_ARMCACHE_RSVD4__##e)
+#define BFM_DIGCTL_ARMCACHE_RSVD4_V(v)      BM_DIGCTL_ARMCACHE_RSVD4
+#define BP_DIGCTL_ARMCACHE_VALID_SS         16
+#define BM_DIGCTL_ARMCACHE_VALID_SS         0x30000
+#define BF_DIGCTL_ARMCACHE_VALID_SS(v)      (((v) & 0x3) << 16)
+#define BFM_DIGCTL_ARMCACHE_VALID_SS(v)     BM_DIGCTL_ARMCACHE_VALID_SS
+#define BF_DIGCTL_ARMCACHE_VALID_SS_V(e)    BF_DIGCTL_ARMCACHE_VALID_SS(BV_DIGCTL_ARMCACHE_VALID_SS__##e)
+#define BFM_DIGCTL_ARMCACHE_VALID_SS_V(v)   BM_DIGCTL_ARMCACHE_VALID_SS
+#define BP_DIGCTL_ARMCACHE_RSVD3            14
+#define BM_DIGCTL_ARMCACHE_RSVD3            0xc000
+#define BF_DIGCTL_ARMCACHE_RSVD3(v)         (((v) & 0x3) << 14)
+#define BFM_DIGCTL_ARMCACHE_RSVD3(v)        BM_DIGCTL_ARMCACHE_RSVD3
+#define BF_DIGCTL_ARMCACHE_RSVD3_V(e)       BF_DIGCTL_ARMCACHE_RSVD3(BV_DIGCTL_ARMCACHE_RSVD3__##e)
+#define BFM_DIGCTL_ARMCACHE_RSVD3_V(v)      BM_DIGCTL_ARMCACHE_RSVD3
+#define BP_DIGCTL_ARMCACHE_DRTY_SS          12
+#define BM_DIGCTL_ARMCACHE_DRTY_SS          0x3000
+#define BF_DIGCTL_ARMCACHE_DRTY_SS(v)       (((v) & 0x3) << 12)
+#define BFM_DIGCTL_ARMCACHE_DRTY_SS(v)      BM_DIGCTL_ARMCACHE_DRTY_SS
+#define BF_DIGCTL_ARMCACHE_DRTY_SS_V(e)     BF_DIGCTL_ARMCACHE_DRTY_SS(BV_DIGCTL_ARMCACHE_DRTY_SS__##e)
+#define BFM_DIGCTL_ARMCACHE_DRTY_SS_V(v)    BM_DIGCTL_ARMCACHE_DRTY_SS
+#define BP_DIGCTL_ARMCACHE_RSVD2            10
+#define BM_DIGCTL_ARMCACHE_RSVD2            0xc00
+#define BF_DIGCTL_ARMCACHE_RSVD2(v)         (((v) & 0x3) << 10)
+#define BFM_DIGCTL_ARMCACHE_RSVD2(v)        BM_DIGCTL_ARMCACHE_RSVD2
+#define BF_DIGCTL_ARMCACHE_RSVD2_V(e)       BF_DIGCTL_ARMCACHE_RSVD2(BV_DIGCTL_ARMCACHE_RSVD2__##e)
+#define BFM_DIGCTL_ARMCACHE_RSVD2_V(v)      BM_DIGCTL_ARMCACHE_RSVD2
+#define BP_DIGCTL_ARMCACHE_CACHE_SS         8
+#define BM_DIGCTL_ARMCACHE_CACHE_SS         0x300
+#define BF_DIGCTL_ARMCACHE_CACHE_SS(v)      (((v) & 0x3) << 8)
+#define BFM_DIGCTL_ARMCACHE_CACHE_SS(v)     BM_DIGCTL_ARMCACHE_CACHE_SS
+#define BF_DIGCTL_ARMCACHE_CACHE_SS_V(e)    BF_DIGCTL_ARMCACHE_CACHE_SS(BV_DIGCTL_ARMCACHE_CACHE_SS__##e)
+#define BFM_DIGCTL_ARMCACHE_CACHE_SS_V(v)   BM_DIGCTL_ARMCACHE_CACHE_SS
+#define BP_DIGCTL_ARMCACHE_RSVD1            6
+#define BM_DIGCTL_ARMCACHE_RSVD1            0xc0
+#define BF_DIGCTL_ARMCACHE_RSVD1(v)         (((v) & 0x3) << 6)
+#define BFM_DIGCTL_ARMCACHE_RSVD1(v)        BM_DIGCTL_ARMCACHE_RSVD1
+#define BF_DIGCTL_ARMCACHE_RSVD1_V(e)       BF_DIGCTL_ARMCACHE_RSVD1(BV_DIGCTL_ARMCACHE_RSVD1__##e)
+#define BFM_DIGCTL_ARMCACHE_RSVD1_V(v)      BM_DIGCTL_ARMCACHE_RSVD1
+#define BP_DIGCTL_ARMCACHE_DTAG_SS          4
+#define BM_DIGCTL_ARMCACHE_DTAG_SS          0x30
+#define BF_DIGCTL_ARMCACHE_DTAG_SS(v)       (((v) & 0x3) << 4)
+#define BFM_DIGCTL_ARMCACHE_DTAG_SS(v)      BM_DIGCTL_ARMCACHE_DTAG_SS
+#define BF_DIGCTL_ARMCACHE_DTAG_SS_V(e)     BF_DIGCTL_ARMCACHE_DTAG_SS(BV_DIGCTL_ARMCACHE_DTAG_SS__##e)
+#define BFM_DIGCTL_ARMCACHE_DTAG_SS_V(v)    BM_DIGCTL_ARMCACHE_DTAG_SS
+#define BP_DIGCTL_ARMCACHE_RSVD0            2
+#define BM_DIGCTL_ARMCACHE_RSVD0            0xc
+#define BF_DIGCTL_ARMCACHE_RSVD0(v)         (((v) & 0x3) << 2)
+#define BFM_DIGCTL_ARMCACHE_RSVD0(v)        BM_DIGCTL_ARMCACHE_RSVD0
+#define BF_DIGCTL_ARMCACHE_RSVD0_V(e)       BF_DIGCTL_ARMCACHE_RSVD0(BV_DIGCTL_ARMCACHE_RSVD0__##e)
+#define BFM_DIGCTL_ARMCACHE_RSVD0_V(v)      BM_DIGCTL_ARMCACHE_RSVD0
+#define BP_DIGCTL_ARMCACHE_ITAG_SS          0
+#define BM_DIGCTL_ARMCACHE_ITAG_SS          0x3
+#define BF_DIGCTL_ARMCACHE_ITAG_SS(v)       (((v) & 0x3) << 0)
+#define BFM_DIGCTL_ARMCACHE_ITAG_SS(v)      BM_DIGCTL_ARMCACHE_ITAG_SS
+#define BF_DIGCTL_ARMCACHE_ITAG_SS_V(e)     BF_DIGCTL_ARMCACHE_ITAG_SS(BV_DIGCTL_ARMCACHE_ITAG_SS__##e)
+#define BFM_DIGCTL_ARMCACHE_ITAG_SS_V(v)    BM_DIGCTL_ARMCACHE_ITAG_SS
+
+#define HW_DIGCTL_DEBUG_TRAP_ADDR_LOW               HW(DIGCTL_DEBUG_TRAP_ADDR_LOW)
+#define HWA_DIGCTL_DEBUG_TRAP_ADDR_LOW              (0x8001c000 + 0x2c0)
+#define HWT_DIGCTL_DEBUG_TRAP_ADDR_LOW              HWIO_32_RW
+#define HWN_DIGCTL_DEBUG_TRAP_ADDR_LOW              DIGCTL_DEBUG_TRAP_ADDR_LOW
+#define HWI_DIGCTL_DEBUG_TRAP_ADDR_LOW              
+#define BP_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR          0
+#define BM_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR          0xffffffff
+#define BF_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR(v)       (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR(v)      BM_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR
+#define BF_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR_V(e)     BF_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR(BV_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR__##e)
+#define BFM_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR_V(v)    BM_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR
+
+#define HW_DIGCTL_DEBUG_TRAP_ADDR_HIGH              HW(DIGCTL_DEBUG_TRAP_ADDR_HIGH)
+#define HWA_DIGCTL_DEBUG_TRAP_ADDR_HIGH             (0x8001c000 + 0x2d0)
+#define HWT_DIGCTL_DEBUG_TRAP_ADDR_HIGH             HWIO_32_RW
+#define HWN_DIGCTL_DEBUG_TRAP_ADDR_HIGH             DIGCTL_DEBUG_TRAP_ADDR_HIGH
+#define HWI_DIGCTL_DEBUG_TRAP_ADDR_HIGH             
+#define BP_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR         0
+#define BM_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR         0xffffffff
+#define BF_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR(v)      (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR(v)     BM_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR
+#define BF_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR_V(e)    BF_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR(BV_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR__##e)
+#define BFM_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR_V(v)   BM_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR
+
+#define HW_DIGCTL_SGTL                  HW(DIGCTL_SGTL)
+#define HWA_DIGCTL_SGTL                 (0x8001c000 + 0x300)
+#define HWT_DIGCTL_SGTL                 HWIO_32_RW
+#define HWN_DIGCTL_SGTL                 DIGCTL_SGTL
+#define HWI_DIGCTL_SGTL                 
+#define BP_DIGCTL_SGTL_COPYRIGHT        0
+#define BM_DIGCTL_SGTL_COPYRIGHT        0xffffffff
+#define BF_DIGCTL_SGTL_COPYRIGHT(v)     (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_SGTL_COPYRIGHT(v)    BM_DIGCTL_SGTL_COPYRIGHT
+#define BF_DIGCTL_SGTL_COPYRIGHT_V(e)   BF_DIGCTL_SGTL_COPYRIGHT(BV_DIGCTL_SGTL_COPYRIGHT__##e)
+#define BFM_DIGCTL_SGTL_COPYRIGHT_V(v)  BM_DIGCTL_SGTL_COPYRIGHT
+
+#define HW_DIGCTL_CHIPID                    HW(DIGCTL_CHIPID)
+#define HWA_DIGCTL_CHIPID                   (0x8001c000 + 0x310)
+#define HWT_DIGCTL_CHIPID                   HWIO_32_RW
+#define HWN_DIGCTL_CHIPID                   DIGCTL_CHIPID
+#define HWI_DIGCTL_CHIPID                   
+#define BP_DIGCTL_CHIPID_PRODUCT_CODE       16
+#define BM_DIGCTL_CHIPID_PRODUCT_CODE       0xffff0000
+#define BF_DIGCTL_CHIPID_PRODUCT_CODE(v)    (((v) & 0xffff) << 16)
+#define BFM_DIGCTL_CHIPID_PRODUCT_CODE(v)   BM_DIGCTL_CHIPID_PRODUCT_CODE
+#define BF_DIGCTL_CHIPID_PRODUCT_CODE_V(e)  BF_DIGCTL_CHIPID_PRODUCT_CODE(BV_DIGCTL_CHIPID_PRODUCT_CODE__##e)
+#define BFM_DIGCTL_CHIPID_PRODUCT_CODE_V(v) BM_DIGCTL_CHIPID_PRODUCT_CODE
+#define BP_DIGCTL_CHIPID_RSVD0              8
+#define BM_DIGCTL_CHIPID_RSVD0              0xff00
+#define BF_DIGCTL_CHIPID_RSVD0(v)           (((v) & 0xff) << 8)
+#define BFM_DIGCTL_CHIPID_RSVD0(v)          BM_DIGCTL_CHIPID_RSVD0
+#define BF_DIGCTL_CHIPID_RSVD0_V(e)         BF_DIGCTL_CHIPID_RSVD0(BV_DIGCTL_CHIPID_RSVD0__##e)
+#define BFM_DIGCTL_CHIPID_RSVD0_V(v)        BM_DIGCTL_CHIPID_RSVD0
+#define BP_DIGCTL_CHIPID_REVISION           0
+#define BM_DIGCTL_CHIPID_REVISION           0xff
+#define BF_DIGCTL_CHIPID_REVISION(v)        (((v) & 0xff) << 0)
+#define BFM_DIGCTL_CHIPID_REVISION(v)       BM_DIGCTL_CHIPID_REVISION
+#define BF_DIGCTL_CHIPID_REVISION_V(e)      BF_DIGCTL_CHIPID_REVISION(BV_DIGCTL_CHIPID_REVISION__##e)
+#define BFM_DIGCTL_CHIPID_REVISION_V(v)     BM_DIGCTL_CHIPID_REVISION
+
+#define HW_DIGCTL_AHB_STATS_SELECT                          HW(DIGCTL_AHB_STATS_SELECT)
+#define HWA_DIGCTL_AHB_STATS_SELECT                         (0x8001c000 + 0x330)
+#define HWT_DIGCTL_AHB_STATS_SELECT                         HWIO_32_RW
+#define HWN_DIGCTL_AHB_STATS_SELECT                         DIGCTL_AHB_STATS_SELECT
+#define HWI_DIGCTL_AHB_STATS_SELECT                         
+#define BP_DIGCTL_AHB_STATS_SELECT_RSVD3                    28
+#define BM_DIGCTL_AHB_STATS_SELECT_RSVD3                    0xf0000000
+#define BF_DIGCTL_AHB_STATS_SELECT_RSVD3(v)                 (((v) & 0xf) << 28)
+#define BFM_DIGCTL_AHB_STATS_SELECT_RSVD3(v)                BM_DIGCTL_AHB_STATS_SELECT_RSVD3
+#define BF_DIGCTL_AHB_STATS_SELECT_RSVD3_V(e)               BF_DIGCTL_AHB_STATS_SELECT_RSVD3(BV_DIGCTL_AHB_STATS_SELECT_RSVD3__##e)
+#define BFM_DIGCTL_AHB_STATS_SELECT_RSVD3_V(v)              BM_DIGCTL_AHB_STATS_SELECT_RSVD3
+#define BP_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT         24
+#define BM_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT         0xf000000
+#define BV_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT__APBH   0x1
+#define BV_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT__APBX   0x2
+#define BV_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT__USB    0x4
+#define BF_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT(v)      (((v) & 0xf) << 24)
+#define BFM_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT(v)     BM_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT
+#define BF_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT_V(e)    BF_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT(BV_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT__##e)
+#define BFM_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT_V(v)   BM_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT
+#define BP_DIGCTL_AHB_STATS_SELECT_RSVD2                    20
+#define BM_DIGCTL_AHB_STATS_SELECT_RSVD2                    0xf00000
+#define BF_DIGCTL_AHB_STATS_SELECT_RSVD2(v)                 (((v) & 0xf) << 20)
+#define BFM_DIGCTL_AHB_STATS_SELECT_RSVD2(v)                BM_DIGCTL_AHB_STATS_SELECT_RSVD2
+#define BF_DIGCTL_AHB_STATS_SELECT_RSVD2_V(e)               BF_DIGCTL_AHB_STATS_SELECT_RSVD2(BV_DIGCTL_AHB_STATS_SELECT_RSVD2__##e)
+#define BFM_DIGCTL_AHB_STATS_SELECT_RSVD2_V(v)              BM_DIGCTL_AHB_STATS_SELECT_RSVD2
+#define BP_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT         16
+#define BM_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT         0xf0000
+#define BV_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT__ARM_D  0x1
+#define BF_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT(v)      (((v) & 0xf) << 16)
+#define BFM_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT(v)     BM_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT
+#define BF_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT_V(e)    BF_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT(BV_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT__##e)
+#define BFM_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT_V(v)   BM_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT
+#define BP_DIGCTL_AHB_STATS_SELECT_RSVD1                    12
+#define BM_DIGCTL_AHB_STATS_SELECT_RSVD1                    0xf000
+#define BF_DIGCTL_AHB_STATS_SELECT_RSVD1(v)                 (((v) & 0xf) << 12)
+#define BFM_DIGCTL_AHB_STATS_SELECT_RSVD1(v)                BM_DIGCTL_AHB_STATS_SELECT_RSVD1
+#define BF_DIGCTL_AHB_STATS_SELECT_RSVD1_V(e)               BF_DIGCTL_AHB_STATS_SELECT_RSVD1(BV_DIGCTL_AHB_STATS_SELECT_RSVD1__##e)
+#define BFM_DIGCTL_AHB_STATS_SELECT_RSVD1_V(v)              BM_DIGCTL_AHB_STATS_SELECT_RSVD1
+#define BP_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT         8
+#define BM_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT         0xf00
+#define BV_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT__ARM_I  0x1
+#define BF_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT(v)      (((v) & 0xf) << 8)
+#define BFM_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT(v)     BM_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT
+#define BF_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT_V(e)    BF_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT(BV_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT__##e)
+#define BFM_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT_V(v)   BM_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT
+#define BP_DIGCTL_AHB_STATS_SELECT_RSVD0                    4
+#define BM_DIGCTL_AHB_STATS_SELECT_RSVD0                    0xf0
+#define BF_DIGCTL_AHB_STATS_SELECT_RSVD0(v)                 (((v) & 0xf) << 4)
+#define BFM_DIGCTL_AHB_STATS_SELECT_RSVD0(v)                BM_DIGCTL_AHB_STATS_SELECT_RSVD0
+#define BF_DIGCTL_AHB_STATS_SELECT_RSVD0_V(e)               BF_DIGCTL_AHB_STATS_SELECT_RSVD0(BV_DIGCTL_AHB_STATS_SELECT_RSVD0__##e)
+#define BFM_DIGCTL_AHB_STATS_SELECT_RSVD0_V(v)              BM_DIGCTL_AHB_STATS_SELECT_RSVD0
+#define BP_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT         0
+#define BM_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT         0xf
+#define BV_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT__ECC8   0x1
+#define BV_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT__CRYPTO 0x2
+#define BF_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT(v)      (((v) & 0xf) << 0)
+#define BFM_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT(v)     BM_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT
+#define BF_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT_V(e)    BF_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT(BV_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT__##e)
+#define BFM_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT_V(v)   BM_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT
+
+#define HW_DIGCTL_L0_AHB_ACTIVE_CYCLES              HW(DIGCTL_L0_AHB_ACTIVE_CYCLES)
+#define HWA_DIGCTL_L0_AHB_ACTIVE_CYCLES             (0x8001c000 + 0x340)
+#define HWT_DIGCTL_L0_AHB_ACTIVE_CYCLES             HWIO_32_RW
+#define HWN_DIGCTL_L0_AHB_ACTIVE_CYCLES             DIGCTL_L0_AHB_ACTIVE_CYCLES
+#define HWI_DIGCTL_L0_AHB_ACTIVE_CYCLES             
+#define BP_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT        0
+#define BM_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT        0xffffffff
+#define BF_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT(v)     (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT(v)    BM_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT
+#define BF_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT_V(e)   BF_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT(BV_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT__##e)
+#define BFM_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT_V(v)  BM_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT
+
+#define HW_DIGCTL_L0_AHB_DATA_STALLED               HW(DIGCTL_L0_AHB_DATA_STALLED)
+#define HWA_DIGCTL_L0_AHB_DATA_STALLED              (0x8001c000 + 0x350)
+#define HWT_DIGCTL_L0_AHB_DATA_STALLED              HWIO_32_RW
+#define HWN_DIGCTL_L0_AHB_DATA_STALLED              DIGCTL_L0_AHB_DATA_STALLED
+#define HWI_DIGCTL_L0_AHB_DATA_STALLED              
+#define BP_DIGCTL_L0_AHB_DATA_STALLED_COUNT         0
+#define BM_DIGCTL_L0_AHB_DATA_STALLED_COUNT         0xffffffff
+#define BF_DIGCTL_L0_AHB_DATA_STALLED_COUNT(v)      (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_L0_AHB_DATA_STALLED_COUNT(v)     BM_DIGCTL_L0_AHB_DATA_STALLED_COUNT
+#define BF_DIGCTL_L0_AHB_DATA_STALLED_COUNT_V(e)    BF_DIGCTL_L0_AHB_DATA_STALLED_COUNT(BV_DIGCTL_L0_AHB_DATA_STALLED_COUNT__##e)
+#define BFM_DIGCTL_L0_AHB_DATA_STALLED_COUNT_V(v)   BM_DIGCTL_L0_AHB_DATA_STALLED_COUNT
+
+#define HW_DIGCTL_L0_AHB_DATA_CYCLES                HW(DIGCTL_L0_AHB_DATA_CYCLES)
+#define HWA_DIGCTL_L0_AHB_DATA_CYCLES               (0x8001c000 + 0x360)
+#define HWT_DIGCTL_L0_AHB_DATA_CYCLES               HWIO_32_RW
+#define HWN_DIGCTL_L0_AHB_DATA_CYCLES               DIGCTL_L0_AHB_DATA_CYCLES
+#define HWI_DIGCTL_L0_AHB_DATA_CYCLES               
+#define BP_DIGCTL_L0_AHB_DATA_CYCLES_COUNT          0
+#define BM_DIGCTL_L0_AHB_DATA_CYCLES_COUNT          0xffffffff
+#define BF_DIGCTL_L0_AHB_DATA_CYCLES_COUNT(v)       (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_L0_AHB_DATA_CYCLES_COUNT(v)      BM_DIGCTL_L0_AHB_DATA_CYCLES_COUNT
+#define BF_DIGCTL_L0_AHB_DATA_CYCLES_COUNT_V(e)     BF_DIGCTL_L0_AHB_DATA_CYCLES_COUNT(BV_DIGCTL_L0_AHB_DATA_CYCLES_COUNT__##e)
+#define BFM_DIGCTL_L0_AHB_DATA_CYCLES_COUNT_V(v)    BM_DIGCTL_L0_AHB_DATA_CYCLES_COUNT
+
+#define HW_DIGCTL_L1_AHB_ACTIVE_CYCLES              HW(DIGCTL_L1_AHB_ACTIVE_CYCLES)
+#define HWA_DIGCTL_L1_AHB_ACTIVE_CYCLES             (0x8001c000 + 0x370)
+#define HWT_DIGCTL_L1_AHB_ACTIVE_CYCLES             HWIO_32_RW
+#define HWN_DIGCTL_L1_AHB_ACTIVE_CYCLES             DIGCTL_L1_AHB_ACTIVE_CYCLES
+#define HWI_DIGCTL_L1_AHB_ACTIVE_CYCLES             
+#define BP_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT        0
+#define BM_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT        0xffffffff
+#define BF_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT(v)     (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT(v)    BM_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT
+#define BF_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT_V(e)   BF_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT(BV_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT__##e)
+#define BFM_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT_V(v)  BM_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT
+
+#define HW_DIGCTL_L1_AHB_DATA_STALLED               HW(DIGCTL_L1_AHB_DATA_STALLED)
+#define HWA_DIGCTL_L1_AHB_DATA_STALLED              (0x8001c000 + 0x380)
+#define HWT_DIGCTL_L1_AHB_DATA_STALLED              HWIO_32_RW
+#define HWN_DIGCTL_L1_AHB_DATA_STALLED              DIGCTL_L1_AHB_DATA_STALLED
+#define HWI_DIGCTL_L1_AHB_DATA_STALLED              
+#define BP_DIGCTL_L1_AHB_DATA_STALLED_COUNT         0
+#define BM_DIGCTL_L1_AHB_DATA_STALLED_COUNT         0xffffffff
+#define BF_DIGCTL_L1_AHB_DATA_STALLED_COUNT(v)      (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_L1_AHB_DATA_STALLED_COUNT(v)     BM_DIGCTL_L1_AHB_DATA_STALLED_COUNT
+#define BF_DIGCTL_L1_AHB_DATA_STALLED_COUNT_V(e)    BF_DIGCTL_L1_AHB_DATA_STALLED_COUNT(BV_DIGCTL_L1_AHB_DATA_STALLED_COUNT__##e)
+#define BFM_DIGCTL_L1_AHB_DATA_STALLED_COUNT_V(v)   BM_DIGCTL_L1_AHB_DATA_STALLED_COUNT
+
+#define HW_DIGCTL_L1_AHB_DATA_CYCLES                HW(DIGCTL_L1_AHB_DATA_CYCLES)
+#define HWA_DIGCTL_L1_AHB_DATA_CYCLES               (0x8001c000 + 0x390)
+#define HWT_DIGCTL_L1_AHB_DATA_CYCLES               HWIO_32_RW
+#define HWN_DIGCTL_L1_AHB_DATA_CYCLES               DIGCTL_L1_AHB_DATA_CYCLES
+#define HWI_DIGCTL_L1_AHB_DATA_CYCLES               
+#define BP_DIGCTL_L1_AHB_DATA_CYCLES_COUNT          0
+#define BM_DIGCTL_L1_AHB_DATA_CYCLES_COUNT          0xffffffff
+#define BF_DIGCTL_L1_AHB_DATA_CYCLES_COUNT(v)       (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_L1_AHB_DATA_CYCLES_COUNT(v)      BM_DIGCTL_L1_AHB_DATA_CYCLES_COUNT
+#define BF_DIGCTL_L1_AHB_DATA_CYCLES_COUNT_V(e)     BF_DIGCTL_L1_AHB_DATA_CYCLES_COUNT(BV_DIGCTL_L1_AHB_DATA_CYCLES_COUNT__##e)
+#define BFM_DIGCTL_L1_AHB_DATA_CYCLES_COUNT_V(v)    BM_DIGCTL_L1_AHB_DATA_CYCLES_COUNT
+
+#define HW_DIGCTL_L2_AHB_ACTIVE_CYCLES              HW(DIGCTL_L2_AHB_ACTIVE_CYCLES)
+#define HWA_DIGCTL_L2_AHB_ACTIVE_CYCLES             (0x8001c000 + 0x3a0)
+#define HWT_DIGCTL_L2_AHB_ACTIVE_CYCLES             HWIO_32_RW
+#define HWN_DIGCTL_L2_AHB_ACTIVE_CYCLES             DIGCTL_L2_AHB_ACTIVE_CYCLES
+#define HWI_DIGCTL_L2_AHB_ACTIVE_CYCLES             
+#define BP_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT        0
+#define BM_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT        0xffffffff
+#define BF_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT(v)     (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT(v)    BM_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT
+#define BF_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT_V(e)   BF_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT(BV_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT__##e)
+#define BFM_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT_V(v)  BM_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT
+
+#define HW_DIGCTL_L2_AHB_DATA_STALLED               HW(DIGCTL_L2_AHB_DATA_STALLED)
+#define HWA_DIGCTL_L2_AHB_DATA_STALLED              (0x8001c000 + 0x3b0)
+#define HWT_DIGCTL_L2_AHB_DATA_STALLED              HWIO_32_RW
+#define HWN_DIGCTL_L2_AHB_DATA_STALLED              DIGCTL_L2_AHB_DATA_STALLED
+#define HWI_DIGCTL_L2_AHB_DATA_STALLED              
+#define BP_DIGCTL_L2_AHB_DATA_STALLED_COUNT         0
+#define BM_DIGCTL_L2_AHB_DATA_STALLED_COUNT         0xffffffff
+#define BF_DIGCTL_L2_AHB_DATA_STALLED_COUNT(v)      (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_L2_AHB_DATA_STALLED_COUNT(v)     BM_DIGCTL_L2_AHB_DATA_STALLED_COUNT
+#define BF_DIGCTL_L2_AHB_DATA_STALLED_COUNT_V(e)    BF_DIGCTL_L2_AHB_DATA_STALLED_COUNT(BV_DIGCTL_L2_AHB_DATA_STALLED_COUNT__##e)
+#define BFM_DIGCTL_L2_AHB_DATA_STALLED_COUNT_V(v)   BM_DIGCTL_L2_AHB_DATA_STALLED_COUNT
+
+#define HW_DIGCTL_L2_AHB_DATA_CYCLES                HW(DIGCTL_L2_AHB_DATA_CYCLES)
+#define HWA_DIGCTL_L2_AHB_DATA_CYCLES               (0x8001c000 + 0x3c0)
+#define HWT_DIGCTL_L2_AHB_DATA_CYCLES               HWIO_32_RW
+#define HWN_DIGCTL_L2_AHB_DATA_CYCLES               DIGCTL_L2_AHB_DATA_CYCLES
+#define HWI_DIGCTL_L2_AHB_DATA_CYCLES               
+#define BP_DIGCTL_L2_AHB_DATA_CYCLES_COUNT          0
+#define BM_DIGCTL_L2_AHB_DATA_CYCLES_COUNT          0xffffffff
+#define BF_DIGCTL_L2_AHB_DATA_CYCLES_COUNT(v)       (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_L2_AHB_DATA_CYCLES_COUNT(v)      BM_DIGCTL_L2_AHB_DATA_CYCLES_COUNT
+#define BF_DIGCTL_L2_AHB_DATA_CYCLES_COUNT_V(e)     BF_DIGCTL_L2_AHB_DATA_CYCLES_COUNT(BV_DIGCTL_L2_AHB_DATA_CYCLES_COUNT__##e)
+#define BFM_DIGCTL_L2_AHB_DATA_CYCLES_COUNT_V(v)    BM_DIGCTL_L2_AHB_DATA_CYCLES_COUNT
+
+#define HW_DIGCTL_L3_AHB_ACTIVE_CYCLES              HW(DIGCTL_L3_AHB_ACTIVE_CYCLES)
+#define HWA_DIGCTL_L3_AHB_ACTIVE_CYCLES             (0x8001c000 + 0x3d0)
+#define HWT_DIGCTL_L3_AHB_ACTIVE_CYCLES             HWIO_32_RW
+#define HWN_DIGCTL_L3_AHB_ACTIVE_CYCLES             DIGCTL_L3_AHB_ACTIVE_CYCLES
+#define HWI_DIGCTL_L3_AHB_ACTIVE_CYCLES             
+#define BP_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT        0
+#define BM_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT        0xffffffff
+#define BF_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT(v)     (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT(v)    BM_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT
+#define BF_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT_V(e)   BF_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT(BV_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT__##e)
+#define BFM_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT_V(v)  BM_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT
+
+#define HW_DIGCTL_L3_AHB_DATA_STALLED               HW(DIGCTL_L3_AHB_DATA_STALLED)
+#define HWA_DIGCTL_L3_AHB_DATA_STALLED              (0x8001c000 + 0x3e0)
+#define HWT_DIGCTL_L3_AHB_DATA_STALLED              HWIO_32_RW
+#define HWN_DIGCTL_L3_AHB_DATA_STALLED              DIGCTL_L3_AHB_DATA_STALLED
+#define HWI_DIGCTL_L3_AHB_DATA_STALLED              
+#define BP_DIGCTL_L3_AHB_DATA_STALLED_COUNT         0
+#define BM_DIGCTL_L3_AHB_DATA_STALLED_COUNT         0xffffffff
+#define BF_DIGCTL_L3_AHB_DATA_STALLED_COUNT(v)      (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_L3_AHB_DATA_STALLED_COUNT(v)     BM_DIGCTL_L3_AHB_DATA_STALLED_COUNT
+#define BF_DIGCTL_L3_AHB_DATA_STALLED_COUNT_V(e)    BF_DIGCTL_L3_AHB_DATA_STALLED_COUNT(BV_DIGCTL_L3_AHB_DATA_STALLED_COUNT__##e)
+#define BFM_DIGCTL_L3_AHB_DATA_STALLED_COUNT_V(v)   BM_DIGCTL_L3_AHB_DATA_STALLED_COUNT
+
+#define HW_DIGCTL_L3_AHB_DATA_CYCLES                HW(DIGCTL_L3_AHB_DATA_CYCLES)
+#define HWA_DIGCTL_L3_AHB_DATA_CYCLES               (0x8001c000 + 0x3f0)
+#define HWT_DIGCTL_L3_AHB_DATA_CYCLES               HWIO_32_RW
+#define HWN_DIGCTL_L3_AHB_DATA_CYCLES               DIGCTL_L3_AHB_DATA_CYCLES
+#define HWI_DIGCTL_L3_AHB_DATA_CYCLES               
+#define BP_DIGCTL_L3_AHB_DATA_CYCLES_COUNT          0
+#define BM_DIGCTL_L3_AHB_DATA_CYCLES_COUNT          0xffffffff
+#define BF_DIGCTL_L3_AHB_DATA_CYCLES_COUNT(v)       (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_L3_AHB_DATA_CYCLES_COUNT(v)      BM_DIGCTL_L3_AHB_DATA_CYCLES_COUNT
+#define BF_DIGCTL_L3_AHB_DATA_CYCLES_COUNT_V(e)     BF_DIGCTL_L3_AHB_DATA_CYCLES_COUNT(BV_DIGCTL_L3_AHB_DATA_CYCLES_COUNT__##e)
+#define BFM_DIGCTL_L3_AHB_DATA_CYCLES_COUNT_V(v)    BM_DIGCTL_L3_AHB_DATA_CYCLES_COUNT
+
+#define HW_DIGCTL_MPTEn_LOC(_n1)        HW(DIGCTL_MPTEn_LOC(_n1))
+#define HWA_DIGCTL_MPTEn_LOC(_n1)       (0x8001c000 + 0x400 + (_n1) * 0x10)
+#define HWT_DIGCTL_MPTEn_LOC(_n1)       HWIO_32_RW
+#define HWN_DIGCTL_MPTEn_LOC(_n1)       DIGCTL_MPTEn_LOC
+#define HWI_DIGCTL_MPTEn_LOC(_n1)       (_n1)
+#define BP_DIGCTL_MPTEn_LOC_RSVD0       12
+#define BM_DIGCTL_MPTEn_LOC_RSVD0       0xfffff000
+#define BF_DIGCTL_MPTEn_LOC_RSVD0(v)    (((v) & 0xfffff) << 12)
+#define BFM_DIGCTL_MPTEn_LOC_RSVD0(v)   BM_DIGCTL_MPTEn_LOC_RSVD0
+#define BF_DIGCTL_MPTEn_LOC_RSVD0_V(e)  BF_DIGCTL_MPTEn_LOC_RSVD0(BV_DIGCTL_MPTEn_LOC_RSVD0__##e)
+#define BFM_DIGCTL_MPTEn_LOC_RSVD0_V(v) BM_DIGCTL_MPTEn_LOC_RSVD0
+#define BP_DIGCTL_MPTEn_LOC_LOC         0
+#define BM_DIGCTL_MPTEn_LOC_LOC         0xfff
+#define BF_DIGCTL_MPTEn_LOC_LOC(v)      (((v) & 0xfff) << 0)
+#define BFM_DIGCTL_MPTEn_LOC_LOC(v)     BM_DIGCTL_MPTEn_LOC_LOC
+#define BF_DIGCTL_MPTEn_LOC_LOC_V(e)    BF_DIGCTL_MPTEn_LOC_LOC(BV_DIGCTL_MPTEn_LOC_LOC__##e)
+#define BFM_DIGCTL_MPTEn_LOC_LOC_V(v)   BM_DIGCTL_MPTEn_LOC_LOC
+
+#define HW_DIGCTL_EMICLK_DELAY                  HW(DIGCTL_EMICLK_DELAY)
+#define HWA_DIGCTL_EMICLK_DELAY                 (0x8001c000 + 0x500)
+#define HWT_DIGCTL_EMICLK_DELAY                 HWIO_32_RW
+#define HWN_DIGCTL_EMICLK_DELAY                 DIGCTL_EMICLK_DELAY
+#define HWI_DIGCTL_EMICLK_DELAY                 
+#define BP_DIGCTL_EMICLK_DELAY_RSVD0            5
+#define BM_DIGCTL_EMICLK_DELAY_RSVD0            0xffffffe0
+#define BF_DIGCTL_EMICLK_DELAY_RSVD0(v)         (((v) & 0x7ffffff) << 5)
+#define BFM_DIGCTL_EMICLK_DELAY_RSVD0(v)        BM_DIGCTL_EMICLK_DELAY_RSVD0
+#define BF_DIGCTL_EMICLK_DELAY_RSVD0_V(e)       BF_DIGCTL_EMICLK_DELAY_RSVD0(BV_DIGCTL_EMICLK_DELAY_RSVD0__##e)
+#define BFM_DIGCTL_EMICLK_DELAY_RSVD0_V(v)      BM_DIGCTL_EMICLK_DELAY_RSVD0
+#define BP_DIGCTL_EMICLK_DELAY_NUM_TAPS         0
+#define BM_DIGCTL_EMICLK_DELAY_NUM_TAPS         0x1f
+#define BF_DIGCTL_EMICLK_DELAY_NUM_TAPS(v)      (((v) & 0x1f) << 0)
+#define BFM_DIGCTL_EMICLK_DELAY_NUM_TAPS(v)     BM_DIGCTL_EMICLK_DELAY_NUM_TAPS
+#define BF_DIGCTL_EMICLK_DELAY_NUM_TAPS_V(e)    BF_DIGCTL_EMICLK_DELAY_NUM_TAPS(BV_DIGCTL_EMICLK_DELAY_NUM_TAPS__##e)
+#define BFM_DIGCTL_EMICLK_DELAY_NUM_TAPS_V(v)   BM_DIGCTL_EMICLK_DELAY_NUM_TAPS
+
+#endif /* __HEADERGEN_IMX233_DIGCTL_H__*/
diff --git a/firmware/target/arm/imx233/regs/imx233/dram.h b/firmware/target/arm/imx233/regs/imx233/dram.h
new file mode 100644
index 0000000000..c8bafc2881
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/imx233/dram.h
@@ -0,0 +1,1599 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * imx233 version: 2.4.0
+ * imx233 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_IMX233_DRAM_H__
+#define __HEADERGEN_IMX233_DRAM_H__
+
+#define HW_DRAM_CTL00                           HW(DRAM_CTL00)
+#define HWA_DRAM_CTL00                          (0x800e0000 + 0x0)
+#define HWT_DRAM_CTL00                          HWIO_32_RW
+#define HWN_DRAM_CTL00                          DRAM_CTL00
+#define HWI_DRAM_CTL00                          
+#define BP_DRAM_CTL00_RSVD4                     25
+#define BM_DRAM_CTL00_RSVD4                     0xfe000000
+#define BF_DRAM_CTL00_RSVD4(v)                  (((v) & 0x7f) << 25)
+#define BFM_DRAM_CTL00_RSVD4(v)                 BM_DRAM_CTL00_RSVD4
+#define BF_DRAM_CTL00_RSVD4_V(e)                BF_DRAM_CTL00_RSVD4(BV_DRAM_CTL00_RSVD4__##e)
+#define BFM_DRAM_CTL00_RSVD4_V(v)               BM_DRAM_CTL00_RSVD4
+#define BP_DRAM_CTL00_AHB0_W_PRIORITY           24
+#define BM_DRAM_CTL00_AHB0_W_PRIORITY           0x1000000
+#define BF_DRAM_CTL00_AHB0_W_PRIORITY(v)        (((v) & 0x1) << 24)
+#define BFM_DRAM_CTL00_AHB0_W_PRIORITY(v)       BM_DRAM_CTL00_AHB0_W_PRIORITY
+#define BF_DRAM_CTL00_AHB0_W_PRIORITY_V(e)      BF_DRAM_CTL00_AHB0_W_PRIORITY(BV_DRAM_CTL00_AHB0_W_PRIORITY__##e)
+#define BFM_DRAM_CTL00_AHB0_W_PRIORITY_V(v)     BM_DRAM_CTL00_AHB0_W_PRIORITY
+#define BP_DRAM_CTL00_RSVD3                     17
+#define BM_DRAM_CTL00_RSVD3                     0xfe0000
+#define BF_DRAM_CTL00_RSVD3(v)                  (((v) & 0x7f) << 17)
+#define BFM_DRAM_CTL00_RSVD3(v)                 BM_DRAM_CTL00_RSVD3
+#define BF_DRAM_CTL00_RSVD3_V(e)                BF_DRAM_CTL00_RSVD3(BV_DRAM_CTL00_RSVD3__##e)
+#define BFM_DRAM_CTL00_RSVD3_V(v)               BM_DRAM_CTL00_RSVD3
+#define BP_DRAM_CTL00_AHB0_R_PRIORITY           16
+#define BM_DRAM_CTL00_AHB0_R_PRIORITY           0x10000
+#define BF_DRAM_CTL00_AHB0_R_PRIORITY(v)        (((v) & 0x1) << 16)
+#define BFM_DRAM_CTL00_AHB0_R_PRIORITY(v)       BM_DRAM_CTL00_AHB0_R_PRIORITY
+#define BF_DRAM_CTL00_AHB0_R_PRIORITY_V(e)      BF_DRAM_CTL00_AHB0_R_PRIORITY(BV_DRAM_CTL00_AHB0_R_PRIORITY__##e)
+#define BFM_DRAM_CTL00_AHB0_R_PRIORITY_V(v)     BM_DRAM_CTL00_AHB0_R_PRIORITY
+#define BP_DRAM_CTL00_RSVD2                     9
+#define BM_DRAM_CTL00_RSVD2                     0xfe00
+#define BF_DRAM_CTL00_RSVD2(v)                  (((v) & 0x7f) << 9)
+#define BFM_DRAM_CTL00_RSVD2(v)                 BM_DRAM_CTL00_RSVD2
+#define BF_DRAM_CTL00_RSVD2_V(e)                BF_DRAM_CTL00_RSVD2(BV_DRAM_CTL00_RSVD2__##e)
+#define BFM_DRAM_CTL00_RSVD2_V(v)               BM_DRAM_CTL00_RSVD2
+#define BP_DRAM_CTL00_AHB0_FIFO_TYPE_REG        8
+#define BM_DRAM_CTL00_AHB0_FIFO_TYPE_REG        0x100
+#define BF_DRAM_CTL00_AHB0_FIFO_TYPE_REG(v)     (((v) & 0x1) << 8)
+#define BFM_DRAM_CTL00_AHB0_FIFO_TYPE_REG(v)    BM_DRAM_CTL00_AHB0_FIFO_TYPE_REG
+#define BF_DRAM_CTL00_AHB0_FIFO_TYPE_REG_V(e)   BF_DRAM_CTL00_AHB0_FIFO_TYPE_REG(BV_DRAM_CTL00_AHB0_FIFO_TYPE_REG__##e)
+#define BFM_DRAM_CTL00_AHB0_FIFO_TYPE_REG_V(v)  BM_DRAM_CTL00_AHB0_FIFO_TYPE_REG
+#define BP_DRAM_CTL00_RSVD1                     1
+#define BM_DRAM_CTL00_RSVD1                     0xfe
+#define BF_DRAM_CTL00_RSVD1(v)                  (((v) & 0x7f) << 1)
+#define BFM_DRAM_CTL00_RSVD1(v)                 BM_DRAM_CTL00_RSVD1
+#define BF_DRAM_CTL00_RSVD1_V(e)                BF_DRAM_CTL00_RSVD1(BV_DRAM_CTL00_RSVD1__##e)
+#define BFM_DRAM_CTL00_RSVD1_V(v)               BM_DRAM_CTL00_RSVD1
+#define BP_DRAM_CTL00_ADDR_CMP_EN               0
+#define BM_DRAM_CTL00_ADDR_CMP_EN               0x1
+#define BF_DRAM_CTL00_ADDR_CMP_EN(v)            (((v) & 0x1) << 0)
+#define BFM_DRAM_CTL00_ADDR_CMP_EN(v)           BM_DRAM_CTL00_ADDR_CMP_EN
+#define BF_DRAM_CTL00_ADDR_CMP_EN_V(e)          BF_DRAM_CTL00_ADDR_CMP_EN(BV_DRAM_CTL00_ADDR_CMP_EN__##e)
+#define BFM_DRAM_CTL00_ADDR_CMP_EN_V(v)         BM_DRAM_CTL00_ADDR_CMP_EN
+
+#define HW_DRAM_CTL01                           HW(DRAM_CTL01)
+#define HWA_DRAM_CTL01                          (0x800e0000 + 0x4)
+#define HWT_DRAM_CTL01                          HWIO_32_RW
+#define HWN_DRAM_CTL01                          DRAM_CTL01
+#define HWI_DRAM_CTL01                          
+#define BP_DRAM_CTL01_RSVD4                     25
+#define BM_DRAM_CTL01_RSVD4                     0xfe000000
+#define BF_DRAM_CTL01_RSVD4(v)                  (((v) & 0x7f) << 25)
+#define BFM_DRAM_CTL01_RSVD4(v)                 BM_DRAM_CTL01_RSVD4
+#define BF_DRAM_CTL01_RSVD4_V(e)                BF_DRAM_CTL01_RSVD4(BV_DRAM_CTL01_RSVD4__##e)
+#define BFM_DRAM_CTL01_RSVD4_V(v)               BM_DRAM_CTL01_RSVD4
+#define BP_DRAM_CTL01_AHB2_FIFO_TYPE_REG        24
+#define BM_DRAM_CTL01_AHB2_FIFO_TYPE_REG        0x1000000
+#define BF_DRAM_CTL01_AHB2_FIFO_TYPE_REG(v)     (((v) & 0x1) << 24)
+#define BFM_DRAM_CTL01_AHB2_FIFO_TYPE_REG(v)    BM_DRAM_CTL01_AHB2_FIFO_TYPE_REG
+#define BF_DRAM_CTL01_AHB2_FIFO_TYPE_REG_V(e)   BF_DRAM_CTL01_AHB2_FIFO_TYPE_REG(BV_DRAM_CTL01_AHB2_FIFO_TYPE_REG__##e)
+#define BFM_DRAM_CTL01_AHB2_FIFO_TYPE_REG_V(v)  BM_DRAM_CTL01_AHB2_FIFO_TYPE_REG
+#define BP_DRAM_CTL01_RSVD3                     17
+#define BM_DRAM_CTL01_RSVD3                     0xfe0000
+#define BF_DRAM_CTL01_RSVD3(v)                  (((v) & 0x7f) << 17)
+#define BFM_DRAM_CTL01_RSVD3(v)                 BM_DRAM_CTL01_RSVD3
+#define BF_DRAM_CTL01_RSVD3_V(e)                BF_DRAM_CTL01_RSVD3(BV_DRAM_CTL01_RSVD3__##e)
+#define BFM_DRAM_CTL01_RSVD3_V(v)               BM_DRAM_CTL01_RSVD3
+#define BP_DRAM_CTL01_AHB1_W_PRIORITY           16
+#define BM_DRAM_CTL01_AHB1_W_PRIORITY           0x10000
+#define BF_DRAM_CTL01_AHB1_W_PRIORITY(v)        (((v) & 0x1) << 16)
+#define BFM_DRAM_CTL01_AHB1_W_PRIORITY(v)       BM_DRAM_CTL01_AHB1_W_PRIORITY
+#define BF_DRAM_CTL01_AHB1_W_PRIORITY_V(e)      BF_DRAM_CTL01_AHB1_W_PRIORITY(BV_DRAM_CTL01_AHB1_W_PRIORITY__##e)
+#define BFM_DRAM_CTL01_AHB1_W_PRIORITY_V(v)     BM_DRAM_CTL01_AHB1_W_PRIORITY
+#define BP_DRAM_CTL01_RSVD2                     9
+#define BM_DRAM_CTL01_RSVD2                     0xfe00
+#define BF_DRAM_CTL01_RSVD2(v)                  (((v) & 0x7f) << 9)
+#define BFM_DRAM_CTL01_RSVD2(v)                 BM_DRAM_CTL01_RSVD2
+#define BF_DRAM_CTL01_RSVD2_V(e)                BF_DRAM_CTL01_RSVD2(BV_DRAM_CTL01_RSVD2__##e)
+#define BFM_DRAM_CTL01_RSVD2_V(v)               BM_DRAM_CTL01_RSVD2
+#define BP_DRAM_CTL01_AHB1_R_PRIORITY           8
+#define BM_DRAM_CTL01_AHB1_R_PRIORITY           0x100
+#define BF_DRAM_CTL01_AHB1_R_PRIORITY(v)        (((v) & 0x1) << 8)
+#define BFM_DRAM_CTL01_AHB1_R_PRIORITY(v)       BM_DRAM_CTL01_AHB1_R_PRIORITY
+#define BF_DRAM_CTL01_AHB1_R_PRIORITY_V(e)      BF_DRAM_CTL01_AHB1_R_PRIORITY(BV_DRAM_CTL01_AHB1_R_PRIORITY__##e)
+#define BFM_DRAM_CTL01_AHB1_R_PRIORITY_V(v)     BM_DRAM_CTL01_AHB1_R_PRIORITY
+#define BP_DRAM_CTL01_RSVD1                     1
+#define BM_DRAM_CTL01_RSVD1                     0xfe
+#define BF_DRAM_CTL01_RSVD1(v)                  (((v) & 0x7f) << 1)
+#define BFM_DRAM_CTL01_RSVD1(v)                 BM_DRAM_CTL01_RSVD1
+#define BF_DRAM_CTL01_RSVD1_V(e)                BF_DRAM_CTL01_RSVD1(BV_DRAM_CTL01_RSVD1__##e)
+#define BFM_DRAM_CTL01_RSVD1_V(v)               BM_DRAM_CTL01_RSVD1
+#define BP_DRAM_CTL01_AHB1_FIFO_TYPE_REG        0
+#define BM_DRAM_CTL01_AHB1_FIFO_TYPE_REG        0x1
+#define BF_DRAM_CTL01_AHB1_FIFO_TYPE_REG(v)     (((v) & 0x1) << 0)
+#define BFM_DRAM_CTL01_AHB1_FIFO_TYPE_REG(v)    BM_DRAM_CTL01_AHB1_FIFO_TYPE_REG
+#define BF_DRAM_CTL01_AHB1_FIFO_TYPE_REG_V(e)   BF_DRAM_CTL01_AHB1_FIFO_TYPE_REG(BV_DRAM_CTL01_AHB1_FIFO_TYPE_REG__##e)
+#define BFM_DRAM_CTL01_AHB1_FIFO_TYPE_REG_V(v)  BM_DRAM_CTL01_AHB1_FIFO_TYPE_REG
+
+#define HW_DRAM_CTL02                           HW(DRAM_CTL02)
+#define HWA_DRAM_CTL02                          (0x800e0000 + 0x8)
+#define HWT_DRAM_CTL02                          HWIO_32_RW
+#define HWN_DRAM_CTL02                          DRAM_CTL02
+#define HWI_DRAM_CTL02                          
+#define BP_DRAM_CTL02_RSVD4                     25
+#define BM_DRAM_CTL02_RSVD4                     0xfe000000
+#define BF_DRAM_CTL02_RSVD4(v)                  (((v) & 0x7f) << 25)
+#define BFM_DRAM_CTL02_RSVD4(v)                 BM_DRAM_CTL02_RSVD4
+#define BF_DRAM_CTL02_RSVD4_V(e)                BF_DRAM_CTL02_RSVD4(BV_DRAM_CTL02_RSVD4__##e)
+#define BFM_DRAM_CTL02_RSVD4_V(v)               BM_DRAM_CTL02_RSVD4
+#define BP_DRAM_CTL02_AHB3_R_PRIORITY           24
+#define BM_DRAM_CTL02_AHB3_R_PRIORITY           0x1000000
+#define BF_DRAM_CTL02_AHB3_R_PRIORITY(v)        (((v) & 0x1) << 24)
+#define BFM_DRAM_CTL02_AHB3_R_PRIORITY(v)       BM_DRAM_CTL02_AHB3_R_PRIORITY
+#define BF_DRAM_CTL02_AHB3_R_PRIORITY_V(e)      BF_DRAM_CTL02_AHB3_R_PRIORITY(BV_DRAM_CTL02_AHB3_R_PRIORITY__##e)
+#define BFM_DRAM_CTL02_AHB3_R_PRIORITY_V(v)     BM_DRAM_CTL02_AHB3_R_PRIORITY
+#define BP_DRAM_CTL02_RSVD3                     17
+#define BM_DRAM_CTL02_RSVD3                     0xfe0000
+#define BF_DRAM_CTL02_RSVD3(v)                  (((v) & 0x7f) << 17)
+#define BFM_DRAM_CTL02_RSVD3(v)                 BM_DRAM_CTL02_RSVD3
+#define BF_DRAM_CTL02_RSVD3_V(e)                BF_DRAM_CTL02_RSVD3(BV_DRAM_CTL02_RSVD3__##e)
+#define BFM_DRAM_CTL02_RSVD3_V(v)               BM_DRAM_CTL02_RSVD3
+#define BP_DRAM_CTL02_AHB3_FIFO_TYPE_REG        16
+#define BM_DRAM_CTL02_AHB3_FIFO_TYPE_REG        0x10000
+#define BF_DRAM_CTL02_AHB3_FIFO_TYPE_REG(v)     (((v) & 0x1) << 16)
+#define BFM_DRAM_CTL02_AHB3_FIFO_TYPE_REG(v)    BM_DRAM_CTL02_AHB3_FIFO_TYPE_REG
+#define BF_DRAM_CTL02_AHB3_FIFO_TYPE_REG_V(e)   BF_DRAM_CTL02_AHB3_FIFO_TYPE_REG(BV_DRAM_CTL02_AHB3_FIFO_TYPE_REG__##e)
+#define BFM_DRAM_CTL02_AHB3_FIFO_TYPE_REG_V(v)  BM_DRAM_CTL02_AHB3_FIFO_TYPE_REG
+#define BP_DRAM_CTL02_RSVD2                     9
+#define BM_DRAM_CTL02_RSVD2                     0xfe00
+#define BF_DRAM_CTL02_RSVD2(v)                  (((v) & 0x7f) << 9)
+#define BFM_DRAM_CTL02_RSVD2(v)                 BM_DRAM_CTL02_RSVD2
+#define BF_DRAM_CTL02_RSVD2_V(e)                BF_DRAM_CTL02_RSVD2(BV_DRAM_CTL02_RSVD2__##e)
+#define BFM_DRAM_CTL02_RSVD2_V(v)               BM_DRAM_CTL02_RSVD2
+#define BP_DRAM_CTL02_AHB2_W_PRIORITY           8
+#define BM_DRAM_CTL02_AHB2_W_PRIORITY           0x100
+#define BF_DRAM_CTL02_AHB2_W_PRIORITY(v)        (((v) & 0x1) << 8)
+#define BFM_DRAM_CTL02_AHB2_W_PRIORITY(v)       BM_DRAM_CTL02_AHB2_W_PRIORITY
+#define BF_DRAM_CTL02_AHB2_W_PRIORITY_V(e)      BF_DRAM_CTL02_AHB2_W_PRIORITY(BV_DRAM_CTL02_AHB2_W_PRIORITY__##e)
+#define BFM_DRAM_CTL02_AHB2_W_PRIORITY_V(v)     BM_DRAM_CTL02_AHB2_W_PRIORITY
+#define BP_DRAM_CTL02_RSVD1                     1
+#define BM_DRAM_CTL02_RSVD1                     0xfe
+#define BF_DRAM_CTL02_RSVD1(v)                  (((v) & 0x7f) << 1)
+#define BFM_DRAM_CTL02_RSVD1(v)                 BM_DRAM_CTL02_RSVD1
+#define BF_DRAM_CTL02_RSVD1_V(e)                BF_DRAM_CTL02_RSVD1(BV_DRAM_CTL02_RSVD1__##e)
+#define BFM_DRAM_CTL02_RSVD1_V(v)               BM_DRAM_CTL02_RSVD1
+#define BP_DRAM_CTL02_AHB2_R_PRIORITY           0
+#define BM_DRAM_CTL02_AHB2_R_PRIORITY           0x1
+#define BF_DRAM_CTL02_AHB2_R_PRIORITY(v)        (((v) & 0x1) << 0)
+#define BFM_DRAM_CTL02_AHB2_R_PRIORITY(v)       BM_DRAM_CTL02_AHB2_R_PRIORITY
+#define BF_DRAM_CTL02_AHB2_R_PRIORITY_V(e)      BF_DRAM_CTL02_AHB2_R_PRIORITY(BV_DRAM_CTL02_AHB2_R_PRIORITY__##e)
+#define BFM_DRAM_CTL02_AHB2_R_PRIORITY_V(v)     BM_DRAM_CTL02_AHB2_R_PRIORITY
+
+#define HW_DRAM_CTL03                           HW(DRAM_CTL03)
+#define HWA_DRAM_CTL03                          (0x800e0000 + 0xc)
+#define HWT_DRAM_CTL03                          HWIO_32_RW
+#define HWN_DRAM_CTL03                          DRAM_CTL03
+#define HWI_DRAM_CTL03                          
+#define BP_DRAM_CTL03_RSVD4                     25
+#define BM_DRAM_CTL03_RSVD4                     0xfe000000
+#define BF_DRAM_CTL03_RSVD4(v)                  (((v) & 0x7f) << 25)
+#define BFM_DRAM_CTL03_RSVD4(v)                 BM_DRAM_CTL03_RSVD4
+#define BF_DRAM_CTL03_RSVD4_V(e)                BF_DRAM_CTL03_RSVD4(BV_DRAM_CTL03_RSVD4__##e)
+#define BFM_DRAM_CTL03_RSVD4_V(v)               BM_DRAM_CTL03_RSVD4
+#define BP_DRAM_CTL03_AUTO_REFRESH_MODE         24
+#define BM_DRAM_CTL03_AUTO_REFRESH_MODE         0x1000000
+#define BF_DRAM_CTL03_AUTO_REFRESH_MODE(v)      (((v) & 0x1) << 24)
+#define BFM_DRAM_CTL03_AUTO_REFRESH_MODE(v)     BM_DRAM_CTL03_AUTO_REFRESH_MODE
+#define BF_DRAM_CTL03_AUTO_REFRESH_MODE_V(e)    BF_DRAM_CTL03_AUTO_REFRESH_MODE(BV_DRAM_CTL03_AUTO_REFRESH_MODE__##e)
+#define BFM_DRAM_CTL03_AUTO_REFRESH_MODE_V(v)   BM_DRAM_CTL03_AUTO_REFRESH_MODE
+#define BP_DRAM_CTL03_RSVD3                     17
+#define BM_DRAM_CTL03_RSVD3                     0xfe0000
+#define BF_DRAM_CTL03_RSVD3(v)                  (((v) & 0x7f) << 17)
+#define BFM_DRAM_CTL03_RSVD3(v)                 BM_DRAM_CTL03_RSVD3
+#define BF_DRAM_CTL03_RSVD3_V(e)                BF_DRAM_CTL03_RSVD3(BV_DRAM_CTL03_RSVD3__##e)
+#define BFM_DRAM_CTL03_RSVD3_V(v)               BM_DRAM_CTL03_RSVD3
+#define BP_DRAM_CTL03_AREFRESH                  16
+#define BM_DRAM_CTL03_AREFRESH                  0x10000
+#define BF_DRAM_CTL03_AREFRESH(v)               (((v) & 0x1) << 16)
+#define BFM_DRAM_CTL03_AREFRESH(v)              BM_DRAM_CTL03_AREFRESH
+#define BF_DRAM_CTL03_AREFRESH_V(e)             BF_DRAM_CTL03_AREFRESH(BV_DRAM_CTL03_AREFRESH__##e)
+#define BFM_DRAM_CTL03_AREFRESH_V(v)            BM_DRAM_CTL03_AREFRESH
+#define BP_DRAM_CTL03_RSVD2                     9
+#define BM_DRAM_CTL03_RSVD2                     0xfe00
+#define BF_DRAM_CTL03_RSVD2(v)                  (((v) & 0x7f) << 9)
+#define BFM_DRAM_CTL03_RSVD2(v)                 BM_DRAM_CTL03_RSVD2
+#define BF_DRAM_CTL03_RSVD2_V(e)                BF_DRAM_CTL03_RSVD2(BV_DRAM_CTL03_RSVD2__##e)
+#define BFM_DRAM_CTL03_RSVD2_V(v)               BM_DRAM_CTL03_RSVD2
+#define BP_DRAM_CTL03_AP                        8
+#define BM_DRAM_CTL03_AP                        0x100
+#define BF_DRAM_CTL03_AP(v)                     (((v) & 0x1) << 8)
+#define BFM_DRAM_CTL03_AP(v)                    BM_DRAM_CTL03_AP
+#define BF_DRAM_CTL03_AP_V(e)                   BF_DRAM_CTL03_AP(BV_DRAM_CTL03_AP__##e)
+#define BFM_DRAM_CTL03_AP_V(v)                  BM_DRAM_CTL03_AP
+#define BP_DRAM_CTL03_RSVD1                     1
+#define BM_DRAM_CTL03_RSVD1                     0xfe
+#define BF_DRAM_CTL03_RSVD1(v)                  (((v) & 0x7f) << 1)
+#define BFM_DRAM_CTL03_RSVD1(v)                 BM_DRAM_CTL03_RSVD1
+#define BF_DRAM_CTL03_RSVD1_V(e)                BF_DRAM_CTL03_RSVD1(BV_DRAM_CTL03_RSVD1__##e)
+#define BFM_DRAM_CTL03_RSVD1_V(v)               BM_DRAM_CTL03_RSVD1
+#define BP_DRAM_CTL03_AHB3_W_PRIORITY           0
+#define BM_DRAM_CTL03_AHB3_W_PRIORITY           0x1
+#define BF_DRAM_CTL03_AHB3_W_PRIORITY(v)        (((v) & 0x1) << 0)
+#define BFM_DRAM_CTL03_AHB3_W_PRIORITY(v)       BM_DRAM_CTL03_AHB3_W_PRIORITY
+#define BF_DRAM_CTL03_AHB3_W_PRIORITY_V(e)      BF_DRAM_CTL03_AHB3_W_PRIORITY(BV_DRAM_CTL03_AHB3_W_PRIORITY__##e)
+#define BFM_DRAM_CTL03_AHB3_W_PRIORITY_V(v)     BM_DRAM_CTL03_AHB3_W_PRIORITY
+
+#define HW_DRAM_CTL04                       HW(DRAM_CTL04)
+#define HWA_DRAM_CTL04                      (0x800e0000 + 0x10)
+#define HWT_DRAM_CTL04                      HWIO_32_RW
+#define HWN_DRAM_CTL04                      DRAM_CTL04
+#define HWI_DRAM_CTL04                      
+#define BP_DRAM_CTL04_RSVD4                 25
+#define BM_DRAM_CTL04_RSVD4                 0xfe000000
+#define BF_DRAM_CTL04_RSVD4(v)              (((v) & 0x7f) << 25)
+#define BFM_DRAM_CTL04_RSVD4(v)             BM_DRAM_CTL04_RSVD4
+#define BF_DRAM_CTL04_RSVD4_V(e)            BF_DRAM_CTL04_RSVD4(BV_DRAM_CTL04_RSVD4__##e)
+#define BFM_DRAM_CTL04_RSVD4_V(v)           BM_DRAM_CTL04_RSVD4
+#define BP_DRAM_CTL04_DLL_BYPASS_MODE       24
+#define BM_DRAM_CTL04_DLL_BYPASS_MODE       0x1000000
+#define BF_DRAM_CTL04_DLL_BYPASS_MODE(v)    (((v) & 0x1) << 24)
+#define BFM_DRAM_CTL04_DLL_BYPASS_MODE(v)   BM_DRAM_CTL04_DLL_BYPASS_MODE
+#define BF_DRAM_CTL04_DLL_BYPASS_MODE_V(e)  BF_DRAM_CTL04_DLL_BYPASS_MODE(BV_DRAM_CTL04_DLL_BYPASS_MODE__##e)
+#define BFM_DRAM_CTL04_DLL_BYPASS_MODE_V(v) BM_DRAM_CTL04_DLL_BYPASS_MODE
+#define BP_DRAM_CTL04_RSVD3                 17
+#define BM_DRAM_CTL04_RSVD3                 0xfe0000
+#define BF_DRAM_CTL04_RSVD3(v)              (((v) & 0x7f) << 17)
+#define BFM_DRAM_CTL04_RSVD3(v)             BM_DRAM_CTL04_RSVD3
+#define BF_DRAM_CTL04_RSVD3_V(e)            BF_DRAM_CTL04_RSVD3(BV_DRAM_CTL04_RSVD3__##e)
+#define BFM_DRAM_CTL04_RSVD3_V(v)           BM_DRAM_CTL04_RSVD3
+#define BP_DRAM_CTL04_DLLLOCKREG            16
+#define BM_DRAM_CTL04_DLLLOCKREG            0x10000
+#define BF_DRAM_CTL04_DLLLOCKREG(v)         (((v) & 0x1) << 16)
+#define BFM_DRAM_CTL04_DLLLOCKREG(v)        BM_DRAM_CTL04_DLLLOCKREG
+#define BF_DRAM_CTL04_DLLLOCKREG_V(e)       BF_DRAM_CTL04_DLLLOCKREG(BV_DRAM_CTL04_DLLLOCKREG__##e)
+#define BFM_DRAM_CTL04_DLLLOCKREG_V(v)      BM_DRAM_CTL04_DLLLOCKREG
+#define BP_DRAM_CTL04_RSVD2                 9
+#define BM_DRAM_CTL04_RSVD2                 0xfe00
+#define BF_DRAM_CTL04_RSVD2(v)              (((v) & 0x7f) << 9)
+#define BFM_DRAM_CTL04_RSVD2(v)             BM_DRAM_CTL04_RSVD2
+#define BF_DRAM_CTL04_RSVD2_V(e)            BF_DRAM_CTL04_RSVD2(BV_DRAM_CTL04_RSVD2__##e)
+#define BFM_DRAM_CTL04_RSVD2_V(v)           BM_DRAM_CTL04_RSVD2
+#define BP_DRAM_CTL04_CONCURRENTAP          8
+#define BM_DRAM_CTL04_CONCURRENTAP          0x100
+#define BF_DRAM_CTL04_CONCURRENTAP(v)       (((v) & 0x1) << 8)
+#define BFM_DRAM_CTL04_CONCURRENTAP(v)      BM_DRAM_CTL04_CONCURRENTAP
+#define BF_DRAM_CTL04_CONCURRENTAP_V(e)     BF_DRAM_CTL04_CONCURRENTAP(BV_DRAM_CTL04_CONCURRENTAP__##e)
+#define BFM_DRAM_CTL04_CONCURRENTAP_V(v)    BM_DRAM_CTL04_CONCURRENTAP
+#define BP_DRAM_CTL04_RSVD1                 1
+#define BM_DRAM_CTL04_RSVD1                 0xfe
+#define BF_DRAM_CTL04_RSVD1(v)              (((v) & 0x7f) << 1)
+#define BFM_DRAM_CTL04_RSVD1(v)             BM_DRAM_CTL04_RSVD1
+#define BF_DRAM_CTL04_RSVD1_V(e)            BF_DRAM_CTL04_RSVD1(BV_DRAM_CTL04_RSVD1__##e)
+#define BFM_DRAM_CTL04_RSVD1_V(v)           BM_DRAM_CTL04_RSVD1
+#define BP_DRAM_CTL04_BANK_SPLIT_EN         0
+#define BM_DRAM_CTL04_BANK_SPLIT_EN         0x1
+#define BF_DRAM_CTL04_BANK_SPLIT_EN(v)      (((v) & 0x1) << 0)
+#define BFM_DRAM_CTL04_BANK_SPLIT_EN(v)     BM_DRAM_CTL04_BANK_SPLIT_EN
+#define BF_DRAM_CTL04_BANK_SPLIT_EN_V(e)    BF_DRAM_CTL04_BANK_SPLIT_EN(BV_DRAM_CTL04_BANK_SPLIT_EN__##e)
+#define BFM_DRAM_CTL04_BANK_SPLIT_EN_V(v)   BM_DRAM_CTL04_BANK_SPLIT_EN
+
+#define HW_DRAM_CTL05                           HW(DRAM_CTL05)
+#define HWA_DRAM_CTL05                          (0x800e0000 + 0x14)
+#define HWT_DRAM_CTL05                          HWIO_32_RW
+#define HWN_DRAM_CTL05                          DRAM_CTL05
+#define HWI_DRAM_CTL05                          
+#define BP_DRAM_CTL05_RSVD4                     25
+#define BM_DRAM_CTL05_RSVD4                     0xfe000000
+#define BF_DRAM_CTL05_RSVD4(v)                  (((v) & 0x7f) << 25)
+#define BFM_DRAM_CTL05_RSVD4(v)                 BM_DRAM_CTL05_RSVD4
+#define BF_DRAM_CTL05_RSVD4_V(e)                BF_DRAM_CTL05_RSVD4(BV_DRAM_CTL05_RSVD4__##e)
+#define BFM_DRAM_CTL05_RSVD4_V(v)               BM_DRAM_CTL05_RSVD4
+#define BP_DRAM_CTL05_INTRPTREADA               24
+#define BM_DRAM_CTL05_INTRPTREADA               0x1000000
+#define BF_DRAM_CTL05_INTRPTREADA(v)            (((v) & 0x1) << 24)
+#define BFM_DRAM_CTL05_INTRPTREADA(v)           BM_DRAM_CTL05_INTRPTREADA
+#define BF_DRAM_CTL05_INTRPTREADA_V(e)          BF_DRAM_CTL05_INTRPTREADA(BV_DRAM_CTL05_INTRPTREADA__##e)
+#define BFM_DRAM_CTL05_INTRPTREADA_V(v)         BM_DRAM_CTL05_INTRPTREADA
+#define BP_DRAM_CTL05_RSVD3                     17
+#define BM_DRAM_CTL05_RSVD3                     0xfe0000
+#define BF_DRAM_CTL05_RSVD3(v)                  (((v) & 0x7f) << 17)
+#define BFM_DRAM_CTL05_RSVD3(v)                 BM_DRAM_CTL05_RSVD3
+#define BF_DRAM_CTL05_RSVD3_V(e)                BF_DRAM_CTL05_RSVD3(BV_DRAM_CTL05_RSVD3__##e)
+#define BFM_DRAM_CTL05_RSVD3_V(v)               BM_DRAM_CTL05_RSVD3
+#define BP_DRAM_CTL05_INTRPTAPBURST             16
+#define BM_DRAM_CTL05_INTRPTAPBURST             0x10000
+#define BF_DRAM_CTL05_INTRPTAPBURST(v)          (((v) & 0x1) << 16)
+#define BFM_DRAM_CTL05_INTRPTAPBURST(v)         BM_DRAM_CTL05_INTRPTAPBURST
+#define BF_DRAM_CTL05_INTRPTAPBURST_V(e)        BF_DRAM_CTL05_INTRPTAPBURST(BV_DRAM_CTL05_INTRPTAPBURST__##e)
+#define BFM_DRAM_CTL05_INTRPTAPBURST_V(v)       BM_DRAM_CTL05_INTRPTAPBURST
+#define BP_DRAM_CTL05_RSVD2                     9
+#define BM_DRAM_CTL05_RSVD2                     0xfe00
+#define BF_DRAM_CTL05_RSVD2(v)                  (((v) & 0x7f) << 9)
+#define BFM_DRAM_CTL05_RSVD2(v)                 BM_DRAM_CTL05_RSVD2
+#define BF_DRAM_CTL05_RSVD2_V(e)                BF_DRAM_CTL05_RSVD2(BV_DRAM_CTL05_RSVD2__##e)
+#define BFM_DRAM_CTL05_RSVD2_V(v)               BM_DRAM_CTL05_RSVD2
+#define BP_DRAM_CTL05_FAST_WRITE                8
+#define BM_DRAM_CTL05_FAST_WRITE                0x100
+#define BF_DRAM_CTL05_FAST_WRITE(v)             (((v) & 0x1) << 8)
+#define BFM_DRAM_CTL05_FAST_WRITE(v)            BM_DRAM_CTL05_FAST_WRITE
+#define BF_DRAM_CTL05_FAST_WRITE_V(e)           BF_DRAM_CTL05_FAST_WRITE(BV_DRAM_CTL05_FAST_WRITE__##e)
+#define BFM_DRAM_CTL05_FAST_WRITE_V(v)          BM_DRAM_CTL05_FAST_WRITE
+#define BP_DRAM_CTL05_RSVD1                     1
+#define BM_DRAM_CTL05_RSVD1                     0xfe
+#define BF_DRAM_CTL05_RSVD1(v)                  (((v) & 0x7f) << 1)
+#define BFM_DRAM_CTL05_RSVD1(v)                 BM_DRAM_CTL05_RSVD1
+#define BF_DRAM_CTL05_RSVD1_V(e)                BF_DRAM_CTL05_RSVD1(BV_DRAM_CTL05_RSVD1__##e)
+#define BFM_DRAM_CTL05_RSVD1_V(v)               BM_DRAM_CTL05_RSVD1
+#define BP_DRAM_CTL05_EN_LOWPOWER_MODE          0
+#define BM_DRAM_CTL05_EN_LOWPOWER_MODE          0x1
+#define BF_DRAM_CTL05_EN_LOWPOWER_MODE(v)       (((v) & 0x1) << 0)
+#define BFM_DRAM_CTL05_EN_LOWPOWER_MODE(v)      BM_DRAM_CTL05_EN_LOWPOWER_MODE
+#define BF_DRAM_CTL05_EN_LOWPOWER_MODE_V(e)     BF_DRAM_CTL05_EN_LOWPOWER_MODE(BV_DRAM_CTL05_EN_LOWPOWER_MODE__##e)
+#define BFM_DRAM_CTL05_EN_LOWPOWER_MODE_V(v)    BM_DRAM_CTL05_EN_LOWPOWER_MODE
+
+#define HW_DRAM_CTL06                       HW(DRAM_CTL06)
+#define HWA_DRAM_CTL06                      (0x800e0000 + 0x18)
+#define HWT_DRAM_CTL06                      HWIO_32_RW
+#define HWN_DRAM_CTL06                      DRAM_CTL06
+#define HWI_DRAM_CTL06                      
+#define BP_DRAM_CTL06_RSVD4                 25
+#define BM_DRAM_CTL06_RSVD4                 0xfe000000
+#define BF_DRAM_CTL06_RSVD4(v)              (((v) & 0x7f) << 25)
+#define BFM_DRAM_CTL06_RSVD4(v)             BM_DRAM_CTL06_RSVD4
+#define BF_DRAM_CTL06_RSVD4_V(e)            BF_DRAM_CTL06_RSVD4(BV_DRAM_CTL06_RSVD4__##e)
+#define BFM_DRAM_CTL06_RSVD4_V(v)           BM_DRAM_CTL06_RSVD4
+#define BP_DRAM_CTL06_POWER_DOWN            24
+#define BM_DRAM_CTL06_POWER_DOWN            0x1000000
+#define BF_DRAM_CTL06_POWER_DOWN(v)         (((v) & 0x1) << 24)
+#define BFM_DRAM_CTL06_POWER_DOWN(v)        BM_DRAM_CTL06_POWER_DOWN
+#define BF_DRAM_CTL06_POWER_DOWN_V(e)       BF_DRAM_CTL06_POWER_DOWN(BV_DRAM_CTL06_POWER_DOWN__##e)
+#define BFM_DRAM_CTL06_POWER_DOWN_V(v)      BM_DRAM_CTL06_POWER_DOWN
+#define BP_DRAM_CTL06_RSVD3                 17
+#define BM_DRAM_CTL06_RSVD3                 0xfe0000
+#define BF_DRAM_CTL06_RSVD3(v)              (((v) & 0x7f) << 17)
+#define BFM_DRAM_CTL06_RSVD3(v)             BM_DRAM_CTL06_RSVD3
+#define BF_DRAM_CTL06_RSVD3_V(e)            BF_DRAM_CTL06_RSVD3(BV_DRAM_CTL06_RSVD3__##e)
+#define BFM_DRAM_CTL06_RSVD3_V(v)           BM_DRAM_CTL06_RSVD3
+#define BP_DRAM_CTL06_PLACEMENT_EN          16
+#define BM_DRAM_CTL06_PLACEMENT_EN          0x10000
+#define BF_DRAM_CTL06_PLACEMENT_EN(v)       (((v) & 0x1) << 16)
+#define BFM_DRAM_CTL06_PLACEMENT_EN(v)      BM_DRAM_CTL06_PLACEMENT_EN
+#define BF_DRAM_CTL06_PLACEMENT_EN_V(e)     BF_DRAM_CTL06_PLACEMENT_EN(BV_DRAM_CTL06_PLACEMENT_EN__##e)
+#define BFM_DRAM_CTL06_PLACEMENT_EN_V(v)    BM_DRAM_CTL06_PLACEMENT_EN
+#define BP_DRAM_CTL06_RSVD2                 9
+#define BM_DRAM_CTL06_RSVD2                 0xfe00
+#define BF_DRAM_CTL06_RSVD2(v)              (((v) & 0x7f) << 9)
+#define BFM_DRAM_CTL06_RSVD2(v)             BM_DRAM_CTL06_RSVD2
+#define BF_DRAM_CTL06_RSVD2_V(e)            BF_DRAM_CTL06_RSVD2(BV_DRAM_CTL06_RSVD2__##e)
+#define BFM_DRAM_CTL06_RSVD2_V(v)           BM_DRAM_CTL06_RSVD2
+#define BP_DRAM_CTL06_NO_CMD_INIT           8
+#define BM_DRAM_CTL06_NO_CMD_INIT           0x100
+#define BF_DRAM_CTL06_NO_CMD_INIT(v)        (((v) & 0x1) << 8)
+#define BFM_DRAM_CTL06_NO_CMD_INIT(v)       BM_DRAM_CTL06_NO_CMD_INIT
+#define BF_DRAM_CTL06_NO_CMD_INIT_V(e)      BF_DRAM_CTL06_NO_CMD_INIT(BV_DRAM_CTL06_NO_CMD_INIT__##e)
+#define BFM_DRAM_CTL06_NO_CMD_INIT_V(v)     BM_DRAM_CTL06_NO_CMD_INIT
+#define BP_DRAM_CTL06_RSVD1                 1
+#define BM_DRAM_CTL06_RSVD1                 0xfe
+#define BF_DRAM_CTL06_RSVD1(v)              (((v) & 0x7f) << 1)
+#define BFM_DRAM_CTL06_RSVD1(v)             BM_DRAM_CTL06_RSVD1
+#define BF_DRAM_CTL06_RSVD1_V(e)            BF_DRAM_CTL06_RSVD1(BV_DRAM_CTL06_RSVD1__##e)
+#define BFM_DRAM_CTL06_RSVD1_V(v)           BM_DRAM_CTL06_RSVD1
+#define BP_DRAM_CTL06_INTRPTWRITEA          0
+#define BM_DRAM_CTL06_INTRPTWRITEA          0x1
+#define BF_DRAM_CTL06_INTRPTWRITEA(v)       (((v) & 0x1) << 0)
+#define BFM_DRAM_CTL06_INTRPTWRITEA(v)      BM_DRAM_CTL06_INTRPTWRITEA
+#define BF_DRAM_CTL06_INTRPTWRITEA_V(e)     BF_DRAM_CTL06_INTRPTWRITEA(BV_DRAM_CTL06_INTRPTWRITEA__##e)
+#define BFM_DRAM_CTL06_INTRPTWRITEA_V(v)    BM_DRAM_CTL06_INTRPTWRITEA
+
+#define HW_DRAM_CTL07                       HW(DRAM_CTL07)
+#define HWA_DRAM_CTL07                      (0x800e0000 + 0x1c)
+#define HWT_DRAM_CTL07                      HWIO_32_RW
+#define HWN_DRAM_CTL07                      DRAM_CTL07
+#define HWI_DRAM_CTL07                      
+#define BP_DRAM_CTL07_RSVD4                 25
+#define BM_DRAM_CTL07_RSVD4                 0xfe000000
+#define BF_DRAM_CTL07_RSVD4(v)              (((v) & 0x7f) << 25)
+#define BFM_DRAM_CTL07_RSVD4(v)             BM_DRAM_CTL07_RSVD4
+#define BF_DRAM_CTL07_RSVD4_V(e)            BF_DRAM_CTL07_RSVD4(BV_DRAM_CTL07_RSVD4__##e)
+#define BFM_DRAM_CTL07_RSVD4_V(v)           BM_DRAM_CTL07_RSVD4
+#define BP_DRAM_CTL07_RW_SAME_EN            24
+#define BM_DRAM_CTL07_RW_SAME_EN            0x1000000
+#define BF_DRAM_CTL07_RW_SAME_EN(v)         (((v) & 0x1) << 24)
+#define BFM_DRAM_CTL07_RW_SAME_EN(v)        BM_DRAM_CTL07_RW_SAME_EN
+#define BF_DRAM_CTL07_RW_SAME_EN_V(e)       BF_DRAM_CTL07_RW_SAME_EN(BV_DRAM_CTL07_RW_SAME_EN__##e)
+#define BFM_DRAM_CTL07_RW_SAME_EN_V(v)      BM_DRAM_CTL07_RW_SAME_EN
+#define BP_DRAM_CTL07_RSVD3                 17
+#define BM_DRAM_CTL07_RSVD3                 0xfe0000
+#define BF_DRAM_CTL07_RSVD3(v)              (((v) & 0x7f) << 17)
+#define BFM_DRAM_CTL07_RSVD3(v)             BM_DRAM_CTL07_RSVD3
+#define BF_DRAM_CTL07_RSVD3_V(e)            BF_DRAM_CTL07_RSVD3(BV_DRAM_CTL07_RSVD3__##e)
+#define BFM_DRAM_CTL07_RSVD3_V(v)           BM_DRAM_CTL07_RSVD3
+#define BP_DRAM_CTL07_REG_DIMM_ENABLE       16
+#define BM_DRAM_CTL07_REG_DIMM_ENABLE       0x10000
+#define BF_DRAM_CTL07_REG_DIMM_ENABLE(v)    (((v) & 0x1) << 16)
+#define BFM_DRAM_CTL07_REG_DIMM_ENABLE(v)   BM_DRAM_CTL07_REG_DIMM_ENABLE
+#define BF_DRAM_CTL07_REG_DIMM_ENABLE_V(e)  BF_DRAM_CTL07_REG_DIMM_ENABLE(BV_DRAM_CTL07_REG_DIMM_ENABLE__##e)
+#define BFM_DRAM_CTL07_REG_DIMM_ENABLE_V(v) BM_DRAM_CTL07_REG_DIMM_ENABLE
+#define BP_DRAM_CTL07_RSVD2                 9
+#define BM_DRAM_CTL07_RSVD2                 0xfe00
+#define BF_DRAM_CTL07_RSVD2(v)              (((v) & 0x7f) << 9)
+#define BFM_DRAM_CTL07_RSVD2(v)             BM_DRAM_CTL07_RSVD2
+#define BF_DRAM_CTL07_RSVD2_V(e)            BF_DRAM_CTL07_RSVD2(BV_DRAM_CTL07_RSVD2__##e)
+#define BFM_DRAM_CTL07_RSVD2_V(v)           BM_DRAM_CTL07_RSVD2
+#define BP_DRAM_CTL07_RD2RD_TURN            8
+#define BM_DRAM_CTL07_RD2RD_TURN            0x100
+#define BF_DRAM_CTL07_RD2RD_TURN(v)         (((v) & 0x1) << 8)
+#define BFM_DRAM_CTL07_RD2RD_TURN(v)        BM_DRAM_CTL07_RD2RD_TURN
+#define BF_DRAM_CTL07_RD2RD_TURN_V(e)       BF_DRAM_CTL07_RD2RD_TURN(BV_DRAM_CTL07_RD2RD_TURN__##e)
+#define BFM_DRAM_CTL07_RD2RD_TURN_V(v)      BM_DRAM_CTL07_RD2RD_TURN
+#define BP_DRAM_CTL07_RSVD1                 1
+#define BM_DRAM_CTL07_RSVD1                 0xfe
+#define BF_DRAM_CTL07_RSVD1(v)              (((v) & 0x7f) << 1)
+#define BFM_DRAM_CTL07_RSVD1(v)             BM_DRAM_CTL07_RSVD1
+#define BF_DRAM_CTL07_RSVD1_V(e)            BF_DRAM_CTL07_RSVD1(BV_DRAM_CTL07_RSVD1__##e)
+#define BFM_DRAM_CTL07_RSVD1_V(v)           BM_DRAM_CTL07_RSVD1
+#define BP_DRAM_CTL07_PRIORITY_EN           0
+#define BM_DRAM_CTL07_PRIORITY_EN           0x1
+#define BF_DRAM_CTL07_PRIORITY_EN(v)        (((v) & 0x1) << 0)
+#define BFM_DRAM_CTL07_PRIORITY_EN(v)       BM_DRAM_CTL07_PRIORITY_EN
+#define BF_DRAM_CTL07_PRIORITY_EN_V(e)      BF_DRAM_CTL07_PRIORITY_EN(BV_DRAM_CTL07_PRIORITY_EN__##e)
+#define BFM_DRAM_CTL07_PRIORITY_EN_V(v)     BM_DRAM_CTL07_PRIORITY_EN
+
+#define HW_DRAM_CTL08                       HW(DRAM_CTL08)
+#define HWA_DRAM_CTL08                      (0x800e0000 + 0x20)
+#define HWT_DRAM_CTL08                      HWIO_32_RW
+#define HWN_DRAM_CTL08                      DRAM_CTL08
+#define HWI_DRAM_CTL08                      
+#define BP_DRAM_CTL08_RSVD4                 25
+#define BM_DRAM_CTL08_RSVD4                 0xfe000000
+#define BF_DRAM_CTL08_RSVD4(v)              (((v) & 0x7f) << 25)
+#define BFM_DRAM_CTL08_RSVD4(v)             BM_DRAM_CTL08_RSVD4
+#define BF_DRAM_CTL08_RSVD4_V(e)            BF_DRAM_CTL08_RSVD4(BV_DRAM_CTL08_RSVD4__##e)
+#define BFM_DRAM_CTL08_RSVD4_V(v)           BM_DRAM_CTL08_RSVD4
+#define BP_DRAM_CTL08_TRAS_LOCKOUT          24
+#define BM_DRAM_CTL08_TRAS_LOCKOUT          0x1000000
+#define BF_DRAM_CTL08_TRAS_LOCKOUT(v)       (((v) & 0x1) << 24)
+#define BFM_DRAM_CTL08_TRAS_LOCKOUT(v)      BM_DRAM_CTL08_TRAS_LOCKOUT
+#define BF_DRAM_CTL08_TRAS_LOCKOUT_V(e)     BF_DRAM_CTL08_TRAS_LOCKOUT(BV_DRAM_CTL08_TRAS_LOCKOUT__##e)
+#define BFM_DRAM_CTL08_TRAS_LOCKOUT_V(v)    BM_DRAM_CTL08_TRAS_LOCKOUT
+#define BP_DRAM_CTL08_RSVD3                 17
+#define BM_DRAM_CTL08_RSVD3                 0xfe0000
+#define BF_DRAM_CTL08_RSVD3(v)              (((v) & 0x7f) << 17)
+#define BFM_DRAM_CTL08_RSVD3(v)             BM_DRAM_CTL08_RSVD3
+#define BF_DRAM_CTL08_RSVD3_V(e)            BF_DRAM_CTL08_RSVD3(BV_DRAM_CTL08_RSVD3__##e)
+#define BFM_DRAM_CTL08_RSVD3_V(v)           BM_DRAM_CTL08_RSVD3
+#define BP_DRAM_CTL08_START                 16
+#define BM_DRAM_CTL08_START                 0x10000
+#define BF_DRAM_CTL08_START(v)              (((v) & 0x1) << 16)
+#define BFM_DRAM_CTL08_START(v)             BM_DRAM_CTL08_START
+#define BF_DRAM_CTL08_START_V(e)            BF_DRAM_CTL08_START(BV_DRAM_CTL08_START__##e)
+#define BFM_DRAM_CTL08_START_V(v)           BM_DRAM_CTL08_START
+#define BP_DRAM_CTL08_RSVD2                 9
+#define BM_DRAM_CTL08_RSVD2                 0xfe00
+#define BF_DRAM_CTL08_RSVD2(v)              (((v) & 0x7f) << 9)
+#define BFM_DRAM_CTL08_RSVD2(v)             BM_DRAM_CTL08_RSVD2
+#define BF_DRAM_CTL08_RSVD2_V(e)            BF_DRAM_CTL08_RSVD2(BV_DRAM_CTL08_RSVD2__##e)
+#define BFM_DRAM_CTL08_RSVD2_V(v)           BM_DRAM_CTL08_RSVD2
+#define BP_DRAM_CTL08_SREFRESH              8
+#define BM_DRAM_CTL08_SREFRESH              0x100
+#define BF_DRAM_CTL08_SREFRESH(v)           (((v) & 0x1) << 8)
+#define BFM_DRAM_CTL08_SREFRESH(v)          BM_DRAM_CTL08_SREFRESH
+#define BF_DRAM_CTL08_SREFRESH_V(e)         BF_DRAM_CTL08_SREFRESH(BV_DRAM_CTL08_SREFRESH__##e)
+#define BFM_DRAM_CTL08_SREFRESH_V(v)        BM_DRAM_CTL08_SREFRESH
+#define BP_DRAM_CTL08_RSVD1                 1
+#define BM_DRAM_CTL08_RSVD1                 0xfe
+#define BF_DRAM_CTL08_RSVD1(v)              (((v) & 0x7f) << 1)
+#define BFM_DRAM_CTL08_RSVD1(v)             BM_DRAM_CTL08_RSVD1
+#define BF_DRAM_CTL08_RSVD1_V(e)            BF_DRAM_CTL08_RSVD1(BV_DRAM_CTL08_RSVD1__##e)
+#define BFM_DRAM_CTL08_RSVD1_V(v)           BM_DRAM_CTL08_RSVD1
+#define BP_DRAM_CTL08_SDR_MODE              0
+#define BM_DRAM_CTL08_SDR_MODE              0x1
+#define BF_DRAM_CTL08_SDR_MODE(v)           (((v) & 0x1) << 0)
+#define BFM_DRAM_CTL08_SDR_MODE(v)          BM_DRAM_CTL08_SDR_MODE
+#define BF_DRAM_CTL08_SDR_MODE_V(e)         BF_DRAM_CTL08_SDR_MODE(BV_DRAM_CTL08_SDR_MODE__##e)
+#define BFM_DRAM_CTL08_SDR_MODE_V(v)        BM_DRAM_CTL08_SDR_MODE
+
+#define HW_DRAM_CTL09                               HW(DRAM_CTL09)
+#define HWA_DRAM_CTL09                              (0x800e0000 + 0x24)
+#define HWT_DRAM_CTL09                              HWIO_32_RW
+#define HWN_DRAM_CTL09                              DRAM_CTL09
+#define HWI_DRAM_CTL09                              
+#define BP_DRAM_CTL09_RSVD4                         26
+#define BM_DRAM_CTL09_RSVD4                         0xfc000000
+#define BF_DRAM_CTL09_RSVD4(v)                      (((v) & 0x3f) << 26)
+#define BFM_DRAM_CTL09_RSVD4(v)                     BM_DRAM_CTL09_RSVD4
+#define BF_DRAM_CTL09_RSVD4_V(e)                    BF_DRAM_CTL09_RSVD4(BV_DRAM_CTL09_RSVD4__##e)
+#define BFM_DRAM_CTL09_RSVD4_V(v)                   BM_DRAM_CTL09_RSVD4
+#define BP_DRAM_CTL09_OUT_OF_RANGE_TYPE             24
+#define BM_DRAM_CTL09_OUT_OF_RANGE_TYPE             0x3000000
+#define BF_DRAM_CTL09_OUT_OF_RANGE_TYPE(v)          (((v) & 0x3) << 24)
+#define BFM_DRAM_CTL09_OUT_OF_RANGE_TYPE(v)         BM_DRAM_CTL09_OUT_OF_RANGE_TYPE
+#define BF_DRAM_CTL09_OUT_OF_RANGE_TYPE_V(e)        BF_DRAM_CTL09_OUT_OF_RANGE_TYPE(BV_DRAM_CTL09_OUT_OF_RANGE_TYPE__##e)
+#define BFM_DRAM_CTL09_OUT_OF_RANGE_TYPE_V(v)       BM_DRAM_CTL09_OUT_OF_RANGE_TYPE
+#define BP_DRAM_CTL09_RSVD3                         18
+#define BM_DRAM_CTL09_RSVD3                         0xfc0000
+#define BF_DRAM_CTL09_RSVD3(v)                      (((v) & 0x3f) << 18)
+#define BFM_DRAM_CTL09_RSVD3(v)                     BM_DRAM_CTL09_RSVD3
+#define BF_DRAM_CTL09_RSVD3_V(e)                    BF_DRAM_CTL09_RSVD3(BV_DRAM_CTL09_RSVD3__##e)
+#define BFM_DRAM_CTL09_RSVD3_V(v)                   BM_DRAM_CTL09_RSVD3
+#define BP_DRAM_CTL09_OUT_OF_RANGE_SOURCE_ID        16
+#define BM_DRAM_CTL09_OUT_OF_RANGE_SOURCE_ID        0x30000
+#define BF_DRAM_CTL09_OUT_OF_RANGE_SOURCE_ID(v)     (((v) & 0x3) << 16)
+#define BFM_DRAM_CTL09_OUT_OF_RANGE_SOURCE_ID(v)    BM_DRAM_CTL09_OUT_OF_RANGE_SOURCE_ID
+#define BF_DRAM_CTL09_OUT_OF_RANGE_SOURCE_ID_V(e)   BF_DRAM_CTL09_OUT_OF_RANGE_SOURCE_ID(BV_DRAM_CTL09_OUT_OF_RANGE_SOURCE_ID__##e)
+#define BFM_DRAM_CTL09_OUT_OF_RANGE_SOURCE_ID_V(v)  BM_DRAM_CTL09_OUT_OF_RANGE_SOURCE_ID
+#define BP_DRAM_CTL09_RSVD2                         9
+#define BM_DRAM_CTL09_RSVD2                         0xfe00
+#define BF_DRAM_CTL09_RSVD2(v)                      (((v) & 0x7f) << 9)
+#define BFM_DRAM_CTL09_RSVD2(v)                     BM_DRAM_CTL09_RSVD2
+#define BF_DRAM_CTL09_RSVD2_V(e)                    BF_DRAM_CTL09_RSVD2(BV_DRAM_CTL09_RSVD2__##e)
+#define BFM_DRAM_CTL09_RSVD2_V(v)                   BM_DRAM_CTL09_RSVD2
+#define BP_DRAM_CTL09_WRITE_MODEREG                 8
+#define BM_DRAM_CTL09_WRITE_MODEREG                 0x100
+#define BF_DRAM_CTL09_WRITE_MODEREG(v)              (((v) & 0x1) << 8)
+#define BFM_DRAM_CTL09_WRITE_MODEREG(v)             BM_DRAM_CTL09_WRITE_MODEREG
+#define BF_DRAM_CTL09_WRITE_MODEREG_V(e)            BF_DRAM_CTL09_WRITE_MODEREG(BV_DRAM_CTL09_WRITE_MODEREG__##e)
+#define BFM_DRAM_CTL09_WRITE_MODEREG_V(v)           BM_DRAM_CTL09_WRITE_MODEREG
+#define BP_DRAM_CTL09_RSVD1                         1
+#define BM_DRAM_CTL09_RSVD1                         0xfe
+#define BF_DRAM_CTL09_RSVD1(v)                      (((v) & 0x7f) << 1)
+#define BFM_DRAM_CTL09_RSVD1(v)                     BM_DRAM_CTL09_RSVD1
+#define BF_DRAM_CTL09_RSVD1_V(e)                    BF_DRAM_CTL09_RSVD1(BV_DRAM_CTL09_RSVD1__##e)
+#define BFM_DRAM_CTL09_RSVD1_V(v)                   BM_DRAM_CTL09_RSVD1
+#define BP_DRAM_CTL09_WRITEINTERP                   0
+#define BM_DRAM_CTL09_WRITEINTERP                   0x1
+#define BF_DRAM_CTL09_WRITEINTERP(v)                (((v) & 0x1) << 0)
+#define BFM_DRAM_CTL09_WRITEINTERP(v)               BM_DRAM_CTL09_WRITEINTERP
+#define BF_DRAM_CTL09_WRITEINTERP_V(e)              BF_DRAM_CTL09_WRITEINTERP(BV_DRAM_CTL09_WRITEINTERP__##e)
+#define BFM_DRAM_CTL09_WRITEINTERP_V(v)             BM_DRAM_CTL09_WRITEINTERP
+
+#define HW_DRAM_CTL10                   HW(DRAM_CTL10)
+#define HWA_DRAM_CTL10                  (0x800e0000 + 0x28)
+#define HWT_DRAM_CTL10                  HWIO_32_RW
+#define HWN_DRAM_CTL10                  DRAM_CTL10
+#define HWI_DRAM_CTL10                  
+#define BP_DRAM_CTL10_RSVD4             27
+#define BM_DRAM_CTL10_RSVD4             0xf8000000
+#define BF_DRAM_CTL10_RSVD4(v)          (((v) & 0x1f) << 27)
+#define BFM_DRAM_CTL10_RSVD4(v)         BM_DRAM_CTL10_RSVD4
+#define BF_DRAM_CTL10_RSVD4_V(e)        BF_DRAM_CTL10_RSVD4(BV_DRAM_CTL10_RSVD4__##e)
+#define BFM_DRAM_CTL10_RSVD4_V(v)       BM_DRAM_CTL10_RSVD4
+#define BP_DRAM_CTL10_AGE_COUNT         24
+#define BM_DRAM_CTL10_AGE_COUNT         0x7000000
+#define BF_DRAM_CTL10_AGE_COUNT(v)      (((v) & 0x7) << 24)
+#define BFM_DRAM_CTL10_AGE_COUNT(v)     BM_DRAM_CTL10_AGE_COUNT
+#define BF_DRAM_CTL10_AGE_COUNT_V(e)    BF_DRAM_CTL10_AGE_COUNT(BV_DRAM_CTL10_AGE_COUNT__##e)
+#define BFM_DRAM_CTL10_AGE_COUNT_V(v)   BM_DRAM_CTL10_AGE_COUNT
+#define BP_DRAM_CTL10_RSVD3             19
+#define BM_DRAM_CTL10_RSVD3             0xf80000
+#define BF_DRAM_CTL10_RSVD3(v)          (((v) & 0x1f) << 19)
+#define BFM_DRAM_CTL10_RSVD3(v)         BM_DRAM_CTL10_RSVD3
+#define BF_DRAM_CTL10_RSVD3_V(e)        BF_DRAM_CTL10_RSVD3(BV_DRAM_CTL10_RSVD3__##e)
+#define BFM_DRAM_CTL10_RSVD3_V(v)       BM_DRAM_CTL10_RSVD3
+#define BP_DRAM_CTL10_ADDR_PINS         16
+#define BM_DRAM_CTL10_ADDR_PINS         0x70000
+#define BF_DRAM_CTL10_ADDR_PINS(v)      (((v) & 0x7) << 16)
+#define BFM_DRAM_CTL10_ADDR_PINS(v)     BM_DRAM_CTL10_ADDR_PINS
+#define BF_DRAM_CTL10_ADDR_PINS_V(e)    BF_DRAM_CTL10_ADDR_PINS(BV_DRAM_CTL10_ADDR_PINS__##e)
+#define BFM_DRAM_CTL10_ADDR_PINS_V(v)   BM_DRAM_CTL10_ADDR_PINS
+#define BP_DRAM_CTL10_RSVD2             10
+#define BM_DRAM_CTL10_RSVD2             0xfc00
+#define BF_DRAM_CTL10_RSVD2(v)          (((v) & 0x3f) << 10)
+#define BFM_DRAM_CTL10_RSVD2(v)         BM_DRAM_CTL10_RSVD2
+#define BF_DRAM_CTL10_RSVD2_V(e)        BF_DRAM_CTL10_RSVD2(BV_DRAM_CTL10_RSVD2__##e)
+#define BFM_DRAM_CTL10_RSVD2_V(v)       BM_DRAM_CTL10_RSVD2
+#define BP_DRAM_CTL10_TEMRS             8
+#define BM_DRAM_CTL10_TEMRS             0x300
+#define BF_DRAM_CTL10_TEMRS(v)          (((v) & 0x3) << 8)
+#define BFM_DRAM_CTL10_TEMRS(v)         BM_DRAM_CTL10_TEMRS
+#define BF_DRAM_CTL10_TEMRS_V(e)        BF_DRAM_CTL10_TEMRS(BV_DRAM_CTL10_TEMRS__##e)
+#define BFM_DRAM_CTL10_TEMRS_V(v)       BM_DRAM_CTL10_TEMRS
+#define BP_DRAM_CTL10_RSVD1             2
+#define BM_DRAM_CTL10_RSVD1             0xfc
+#define BF_DRAM_CTL10_RSVD1(v)          (((v) & 0x3f) << 2)
+#define BFM_DRAM_CTL10_RSVD1(v)         BM_DRAM_CTL10_RSVD1
+#define BF_DRAM_CTL10_RSVD1_V(e)        BF_DRAM_CTL10_RSVD1(BV_DRAM_CTL10_RSVD1__##e)
+#define BFM_DRAM_CTL10_RSVD1_V(v)       BM_DRAM_CTL10_RSVD1
+#define BP_DRAM_CTL10_Q_FULLNESS        0
+#define BM_DRAM_CTL10_Q_FULLNESS        0x3
+#define BF_DRAM_CTL10_Q_FULLNESS(v)     (((v) & 0x3) << 0)
+#define BFM_DRAM_CTL10_Q_FULLNESS(v)    BM_DRAM_CTL10_Q_FULLNESS
+#define BF_DRAM_CTL10_Q_FULLNESS_V(e)   BF_DRAM_CTL10_Q_FULLNESS(BV_DRAM_CTL10_Q_FULLNESS__##e)
+#define BFM_DRAM_CTL10_Q_FULLNESS_V(v)  BM_DRAM_CTL10_Q_FULLNESS
+
+#define HW_DRAM_CTL11                           HW(DRAM_CTL11)
+#define HWA_DRAM_CTL11                          (0x800e0000 + 0x2c)
+#define HWT_DRAM_CTL11                          HWIO_32_RW
+#define HWN_DRAM_CTL11                          DRAM_CTL11
+#define HWI_DRAM_CTL11                          
+#define BP_DRAM_CTL11_RSVD4                     27
+#define BM_DRAM_CTL11_RSVD4                     0xf8000000
+#define BF_DRAM_CTL11_RSVD4(v)                  (((v) & 0x1f) << 27)
+#define BFM_DRAM_CTL11_RSVD4(v)                 BM_DRAM_CTL11_RSVD4
+#define BF_DRAM_CTL11_RSVD4_V(e)                BF_DRAM_CTL11_RSVD4(BV_DRAM_CTL11_RSVD4__##e)
+#define BFM_DRAM_CTL11_RSVD4_V(v)               BM_DRAM_CTL11_RSVD4
+#define BP_DRAM_CTL11_MAX_CS_REG                24
+#define BM_DRAM_CTL11_MAX_CS_REG                0x7000000
+#define BF_DRAM_CTL11_MAX_CS_REG(v)             (((v) & 0x7) << 24)
+#define BFM_DRAM_CTL11_MAX_CS_REG(v)            BM_DRAM_CTL11_MAX_CS_REG
+#define BF_DRAM_CTL11_MAX_CS_REG_V(e)           BF_DRAM_CTL11_MAX_CS_REG(BV_DRAM_CTL11_MAX_CS_REG__##e)
+#define BFM_DRAM_CTL11_MAX_CS_REG_V(v)          BM_DRAM_CTL11_MAX_CS_REG
+#define BP_DRAM_CTL11_RSVD3                     19
+#define BM_DRAM_CTL11_RSVD3                     0xf80000
+#define BF_DRAM_CTL11_RSVD3(v)                  (((v) & 0x1f) << 19)
+#define BFM_DRAM_CTL11_RSVD3(v)                 BM_DRAM_CTL11_RSVD3
+#define BF_DRAM_CTL11_RSVD3_V(e)                BF_DRAM_CTL11_RSVD3(BV_DRAM_CTL11_RSVD3__##e)
+#define BFM_DRAM_CTL11_RSVD3_V(v)               BM_DRAM_CTL11_RSVD3
+#define BP_DRAM_CTL11_COMMAND_AGE_COUNT         16
+#define BM_DRAM_CTL11_COMMAND_AGE_COUNT         0x70000
+#define BF_DRAM_CTL11_COMMAND_AGE_COUNT(v)      (((v) & 0x7) << 16)
+#define BFM_DRAM_CTL11_COMMAND_AGE_COUNT(v)     BM_DRAM_CTL11_COMMAND_AGE_COUNT
+#define BF_DRAM_CTL11_COMMAND_AGE_COUNT_V(e)    BF_DRAM_CTL11_COMMAND_AGE_COUNT(BV_DRAM_CTL11_COMMAND_AGE_COUNT__##e)
+#define BFM_DRAM_CTL11_COMMAND_AGE_COUNT_V(v)   BM_DRAM_CTL11_COMMAND_AGE_COUNT
+#define BP_DRAM_CTL11_RSVD2                     11
+#define BM_DRAM_CTL11_RSVD2                     0xf800
+#define BF_DRAM_CTL11_RSVD2(v)                  (((v) & 0x1f) << 11)
+#define BFM_DRAM_CTL11_RSVD2(v)                 BM_DRAM_CTL11_RSVD2
+#define BF_DRAM_CTL11_RSVD2_V(e)                BF_DRAM_CTL11_RSVD2(BV_DRAM_CTL11_RSVD2__##e)
+#define BFM_DRAM_CTL11_RSVD2_V(v)               BM_DRAM_CTL11_RSVD2
+#define BP_DRAM_CTL11_COLUMN_SIZE               8
+#define BM_DRAM_CTL11_COLUMN_SIZE               0x700
+#define BF_DRAM_CTL11_COLUMN_SIZE(v)            (((v) & 0x7) << 8)
+#define BFM_DRAM_CTL11_COLUMN_SIZE(v)           BM_DRAM_CTL11_COLUMN_SIZE
+#define BF_DRAM_CTL11_COLUMN_SIZE_V(e)          BF_DRAM_CTL11_COLUMN_SIZE(BV_DRAM_CTL11_COLUMN_SIZE__##e)
+#define BFM_DRAM_CTL11_COLUMN_SIZE_V(v)         BM_DRAM_CTL11_COLUMN_SIZE
+#define BP_DRAM_CTL11_RSVD1                     3
+#define BM_DRAM_CTL11_RSVD1                     0xf8
+#define BF_DRAM_CTL11_RSVD1(v)                  (((v) & 0x1f) << 3)
+#define BFM_DRAM_CTL11_RSVD1(v)                 BM_DRAM_CTL11_RSVD1
+#define BF_DRAM_CTL11_RSVD1_V(e)                BF_DRAM_CTL11_RSVD1(BV_DRAM_CTL11_RSVD1__##e)
+#define BFM_DRAM_CTL11_RSVD1_V(v)               BM_DRAM_CTL11_RSVD1
+#define BP_DRAM_CTL11_CASLAT                    0
+#define BM_DRAM_CTL11_CASLAT                    0x7
+#define BF_DRAM_CTL11_CASLAT(v)                 (((v) & 0x7) << 0)
+#define BFM_DRAM_CTL11_CASLAT(v)                BM_DRAM_CTL11_CASLAT
+#define BF_DRAM_CTL11_CASLAT_V(e)               BF_DRAM_CTL11_CASLAT(BV_DRAM_CTL11_CASLAT__##e)
+#define BFM_DRAM_CTL11_CASLAT_V(v)              BM_DRAM_CTL11_CASLAT
+
+#define HW_DRAM_CTL12                   HW(DRAM_CTL12)
+#define HWA_DRAM_CTL12                  (0x800e0000 + 0x30)
+#define HWT_DRAM_CTL12                  HWIO_32_RW
+#define HWN_DRAM_CTL12                  DRAM_CTL12
+#define HWI_DRAM_CTL12                  
+#define BP_DRAM_CTL12_RSVD3             27
+#define BM_DRAM_CTL12_RSVD3             0xf8000000
+#define BF_DRAM_CTL12_RSVD3(v)          (((v) & 0x1f) << 27)
+#define BFM_DRAM_CTL12_RSVD3(v)         BM_DRAM_CTL12_RSVD3
+#define BF_DRAM_CTL12_RSVD3_V(e)        BF_DRAM_CTL12_RSVD3(BV_DRAM_CTL12_RSVD3__##e)
+#define BFM_DRAM_CTL12_RSVD3_V(v)       BM_DRAM_CTL12_RSVD3
+#define BP_DRAM_CTL12_TWR_INT           24
+#define BM_DRAM_CTL12_TWR_INT           0x7000000
+#define BF_DRAM_CTL12_TWR_INT(v)        (((v) & 0x7) << 24)
+#define BFM_DRAM_CTL12_TWR_INT(v)       BM_DRAM_CTL12_TWR_INT
+#define BF_DRAM_CTL12_TWR_INT_V(e)      BF_DRAM_CTL12_TWR_INT(BV_DRAM_CTL12_TWR_INT__##e)
+#define BFM_DRAM_CTL12_TWR_INT_V(v)     BM_DRAM_CTL12_TWR_INT
+#define BP_DRAM_CTL12_RSVD2             19
+#define BM_DRAM_CTL12_RSVD2             0xf80000
+#define BF_DRAM_CTL12_RSVD2(v)          (((v) & 0x1f) << 19)
+#define BFM_DRAM_CTL12_RSVD2(v)         BM_DRAM_CTL12_RSVD2
+#define BF_DRAM_CTL12_RSVD2_V(e)        BF_DRAM_CTL12_RSVD2(BV_DRAM_CTL12_RSVD2__##e)
+#define BFM_DRAM_CTL12_RSVD2_V(v)       BM_DRAM_CTL12_RSVD2
+#define BP_DRAM_CTL12_TRRD              16
+#define BM_DRAM_CTL12_TRRD              0x70000
+#define BF_DRAM_CTL12_TRRD(v)           (((v) & 0x7) << 16)
+#define BFM_DRAM_CTL12_TRRD(v)          BM_DRAM_CTL12_TRRD
+#define BF_DRAM_CTL12_TRRD_V(e)         BF_DRAM_CTL12_TRRD(BV_DRAM_CTL12_TRRD__##e)
+#define BFM_DRAM_CTL12_TRRD_V(v)        BM_DRAM_CTL12_TRRD
+#define BP_DRAM_CTL12_OBSOLETE          8
+#define BM_DRAM_CTL12_OBSOLETE          0xff00
+#define BF_DRAM_CTL12_OBSOLETE(v)       (((v) & 0xff) << 8)
+#define BFM_DRAM_CTL12_OBSOLETE(v)      BM_DRAM_CTL12_OBSOLETE
+#define BF_DRAM_CTL12_OBSOLETE_V(e)     BF_DRAM_CTL12_OBSOLETE(BV_DRAM_CTL12_OBSOLETE__##e)
+#define BFM_DRAM_CTL12_OBSOLETE_V(v)    BM_DRAM_CTL12_OBSOLETE
+#define BP_DRAM_CTL12_RSVD1             3
+#define BM_DRAM_CTL12_RSVD1             0xf8
+#define BF_DRAM_CTL12_RSVD1(v)          (((v) & 0x1f) << 3)
+#define BFM_DRAM_CTL12_RSVD1(v)         BM_DRAM_CTL12_RSVD1
+#define BF_DRAM_CTL12_RSVD1_V(e)        BF_DRAM_CTL12_RSVD1(BV_DRAM_CTL12_RSVD1__##e)
+#define BFM_DRAM_CTL12_RSVD1_V(v)       BM_DRAM_CTL12_RSVD1
+#define BP_DRAM_CTL12_TCKE              0
+#define BM_DRAM_CTL12_TCKE              0x7
+#define BF_DRAM_CTL12_TCKE(v)           (((v) & 0x7) << 0)
+#define BFM_DRAM_CTL12_TCKE(v)          BM_DRAM_CTL12_TCKE
+#define BF_DRAM_CTL12_TCKE_V(e)         BF_DRAM_CTL12_TCKE(BV_DRAM_CTL12_TCKE__##e)
+#define BFM_DRAM_CTL12_TCKE_V(v)        BM_DRAM_CTL12_TCKE
+
+#define HW_DRAM_CTL13                       HW(DRAM_CTL13)
+#define HWA_DRAM_CTL13                      (0x800e0000 + 0x34)
+#define HWT_DRAM_CTL13                      HWIO_32_RW
+#define HWN_DRAM_CTL13                      DRAM_CTL13
+#define HWI_DRAM_CTL13                      
+#define BP_DRAM_CTL13_RSVD4                 28
+#define BM_DRAM_CTL13_RSVD4                 0xf0000000
+#define BF_DRAM_CTL13_RSVD4(v)              (((v) & 0xf) << 28)
+#define BFM_DRAM_CTL13_RSVD4(v)             BM_DRAM_CTL13_RSVD4
+#define BF_DRAM_CTL13_RSVD4_V(e)            BF_DRAM_CTL13_RSVD4(BV_DRAM_CTL13_RSVD4__##e)
+#define BFM_DRAM_CTL13_RSVD4_V(v)           BM_DRAM_CTL13_RSVD4
+#define BP_DRAM_CTL13_CASLAT_LIN_GATE       24
+#define BM_DRAM_CTL13_CASLAT_LIN_GATE       0xf000000
+#define BF_DRAM_CTL13_CASLAT_LIN_GATE(v)    (((v) & 0xf) << 24)
+#define BFM_DRAM_CTL13_CASLAT_LIN_GATE(v)   BM_DRAM_CTL13_CASLAT_LIN_GATE
+#define BF_DRAM_CTL13_CASLAT_LIN_GATE_V(e)  BF_DRAM_CTL13_CASLAT_LIN_GATE(BV_DRAM_CTL13_CASLAT_LIN_GATE__##e)
+#define BFM_DRAM_CTL13_CASLAT_LIN_GATE_V(v) BM_DRAM_CTL13_CASLAT_LIN_GATE
+#define BP_DRAM_CTL13_RSVD3                 20
+#define BM_DRAM_CTL13_RSVD3                 0xf00000
+#define BF_DRAM_CTL13_RSVD3(v)              (((v) & 0xf) << 20)
+#define BFM_DRAM_CTL13_RSVD3(v)             BM_DRAM_CTL13_RSVD3
+#define BF_DRAM_CTL13_RSVD3_V(e)            BF_DRAM_CTL13_RSVD3(BV_DRAM_CTL13_RSVD3__##e)
+#define BFM_DRAM_CTL13_RSVD3_V(v)           BM_DRAM_CTL13_RSVD3
+#define BP_DRAM_CTL13_CASLAT_LIN            16
+#define BM_DRAM_CTL13_CASLAT_LIN            0xf0000
+#define BF_DRAM_CTL13_CASLAT_LIN(v)         (((v) & 0xf) << 16)
+#define BFM_DRAM_CTL13_CASLAT_LIN(v)        BM_DRAM_CTL13_CASLAT_LIN
+#define BF_DRAM_CTL13_CASLAT_LIN_V(e)       BF_DRAM_CTL13_CASLAT_LIN(BV_DRAM_CTL13_CASLAT_LIN__##e)
+#define BFM_DRAM_CTL13_CASLAT_LIN_V(v)      BM_DRAM_CTL13_CASLAT_LIN
+#define BP_DRAM_CTL13_RSVD2                 12
+#define BM_DRAM_CTL13_RSVD2                 0xf000
+#define BF_DRAM_CTL13_RSVD2(v)              (((v) & 0xf) << 12)
+#define BFM_DRAM_CTL13_RSVD2(v)             BM_DRAM_CTL13_RSVD2
+#define BF_DRAM_CTL13_RSVD2_V(e)            BF_DRAM_CTL13_RSVD2(BV_DRAM_CTL13_RSVD2__##e)
+#define BFM_DRAM_CTL13_RSVD2_V(v)           BM_DRAM_CTL13_RSVD2
+#define BP_DRAM_CTL13_APREBIT               8
+#define BM_DRAM_CTL13_APREBIT               0xf00
+#define BF_DRAM_CTL13_APREBIT(v)            (((v) & 0xf) << 8)
+#define BFM_DRAM_CTL13_APREBIT(v)           BM_DRAM_CTL13_APREBIT
+#define BF_DRAM_CTL13_APREBIT_V(e)          BF_DRAM_CTL13_APREBIT(BV_DRAM_CTL13_APREBIT__##e)
+#define BFM_DRAM_CTL13_APREBIT_V(v)         BM_DRAM_CTL13_APREBIT
+#define BP_DRAM_CTL13_RSVD1                 3
+#define BM_DRAM_CTL13_RSVD1                 0xf8
+#define BF_DRAM_CTL13_RSVD1(v)              (((v) & 0x1f) << 3)
+#define BFM_DRAM_CTL13_RSVD1(v)             BM_DRAM_CTL13_RSVD1
+#define BF_DRAM_CTL13_RSVD1_V(e)            BF_DRAM_CTL13_RSVD1(BV_DRAM_CTL13_RSVD1__##e)
+#define BFM_DRAM_CTL13_RSVD1_V(v)           BM_DRAM_CTL13_RSVD1
+#define BP_DRAM_CTL13_TWTR                  0
+#define BM_DRAM_CTL13_TWTR                  0x7
+#define BF_DRAM_CTL13_TWTR(v)               (((v) & 0x7) << 0)
+#define BFM_DRAM_CTL13_TWTR(v)              BM_DRAM_CTL13_TWTR
+#define BF_DRAM_CTL13_TWTR_V(e)             BF_DRAM_CTL13_TWTR(BV_DRAM_CTL13_TWTR__##e)
+#define BFM_DRAM_CTL13_TWTR_V(v)            BM_DRAM_CTL13_TWTR
+
+#define HW_DRAM_CTL14                               HW(DRAM_CTL14)
+#define HWA_DRAM_CTL14                              (0x800e0000 + 0x38)
+#define HWT_DRAM_CTL14                              HWIO_32_RW
+#define HWN_DRAM_CTL14                              DRAM_CTL14
+#define HWI_DRAM_CTL14                              
+#define BP_DRAM_CTL14_RSVD4                         28
+#define BM_DRAM_CTL14_RSVD4                         0xf0000000
+#define BF_DRAM_CTL14_RSVD4(v)                      (((v) & 0xf) << 28)
+#define BFM_DRAM_CTL14_RSVD4(v)                     BM_DRAM_CTL14_RSVD4
+#define BF_DRAM_CTL14_RSVD4_V(e)                    BF_DRAM_CTL14_RSVD4(BV_DRAM_CTL14_RSVD4__##e)
+#define BFM_DRAM_CTL14_RSVD4_V(v)                   BM_DRAM_CTL14_RSVD4
+#define BP_DRAM_CTL14_MAX_COL_REG                   24
+#define BM_DRAM_CTL14_MAX_COL_REG                   0xf000000
+#define BF_DRAM_CTL14_MAX_COL_REG(v)                (((v) & 0xf) << 24)
+#define BFM_DRAM_CTL14_MAX_COL_REG(v)               BM_DRAM_CTL14_MAX_COL_REG
+#define BF_DRAM_CTL14_MAX_COL_REG_V(e)              BF_DRAM_CTL14_MAX_COL_REG(BV_DRAM_CTL14_MAX_COL_REG__##e)
+#define BFM_DRAM_CTL14_MAX_COL_REG_V(v)             BM_DRAM_CTL14_MAX_COL_REG
+#define BP_DRAM_CTL14_RSVD3                         20
+#define BM_DRAM_CTL14_RSVD3                         0xf00000
+#define BF_DRAM_CTL14_RSVD3(v)                      (((v) & 0xf) << 20)
+#define BFM_DRAM_CTL14_RSVD3(v)                     BM_DRAM_CTL14_RSVD3
+#define BF_DRAM_CTL14_RSVD3_V(e)                    BF_DRAM_CTL14_RSVD3(BV_DRAM_CTL14_RSVD3__##e)
+#define BFM_DRAM_CTL14_RSVD3_V(v)                   BM_DRAM_CTL14_RSVD3
+#define BP_DRAM_CTL14_LOWPOWER_REFRESH_ENABLE       16
+#define BM_DRAM_CTL14_LOWPOWER_REFRESH_ENABLE       0xf0000
+#define BF_DRAM_CTL14_LOWPOWER_REFRESH_ENABLE(v)    (((v) & 0xf) << 16)
+#define BFM_DRAM_CTL14_LOWPOWER_REFRESH_ENABLE(v)   BM_DRAM_CTL14_LOWPOWER_REFRESH_ENABLE
+#define BF_DRAM_CTL14_LOWPOWER_REFRESH_ENABLE_V(e)  BF_DRAM_CTL14_LOWPOWER_REFRESH_ENABLE(BV_DRAM_CTL14_LOWPOWER_REFRESH_ENABLE__##e)
+#define BFM_DRAM_CTL14_LOWPOWER_REFRESH_ENABLE_V(v) BM_DRAM_CTL14_LOWPOWER_REFRESH_ENABLE
+#define BP_DRAM_CTL14_RSVD2                         12
+#define BM_DRAM_CTL14_RSVD2                         0xf000
+#define BF_DRAM_CTL14_RSVD2(v)                      (((v) & 0xf) << 12)
+#define BFM_DRAM_CTL14_RSVD2(v)                     BM_DRAM_CTL14_RSVD2
+#define BF_DRAM_CTL14_RSVD2_V(e)                    BF_DRAM_CTL14_RSVD2(BV_DRAM_CTL14_RSVD2__##e)
+#define BFM_DRAM_CTL14_RSVD2_V(v)                   BM_DRAM_CTL14_RSVD2
+#define BP_DRAM_CTL14_INITAREF                      8
+#define BM_DRAM_CTL14_INITAREF                      0xf00
+#define BF_DRAM_CTL14_INITAREF(v)                   (((v) & 0xf) << 8)
+#define BFM_DRAM_CTL14_INITAREF(v)                  BM_DRAM_CTL14_INITAREF
+#define BF_DRAM_CTL14_INITAREF_V(e)                 BF_DRAM_CTL14_INITAREF(BV_DRAM_CTL14_INITAREF__##e)
+#define BFM_DRAM_CTL14_INITAREF_V(v)                BM_DRAM_CTL14_INITAREF
+#define BP_DRAM_CTL14_RSVD1                         4
+#define BM_DRAM_CTL14_RSVD1                         0xf0
+#define BF_DRAM_CTL14_RSVD1(v)                      (((v) & 0xf) << 4)
+#define BFM_DRAM_CTL14_RSVD1(v)                     BM_DRAM_CTL14_RSVD1
+#define BF_DRAM_CTL14_RSVD1_V(e)                    BF_DRAM_CTL14_RSVD1(BV_DRAM_CTL14_RSVD1__##e)
+#define BFM_DRAM_CTL14_RSVD1_V(v)                   BM_DRAM_CTL14_RSVD1
+#define BP_DRAM_CTL14_CS_MAP                        0
+#define BM_DRAM_CTL14_CS_MAP                        0xf
+#define BF_DRAM_CTL14_CS_MAP(v)                     (((v) & 0xf) << 0)
+#define BFM_DRAM_CTL14_CS_MAP(v)                    BM_DRAM_CTL14_CS_MAP
+#define BF_DRAM_CTL14_CS_MAP_V(e)                   BF_DRAM_CTL14_CS_MAP(BV_DRAM_CTL14_CS_MAP__##e)
+#define BFM_DRAM_CTL14_CS_MAP_V(v)                  BM_DRAM_CTL14_CS_MAP
+
+#define HW_DRAM_CTL15                   HW(DRAM_CTL15)
+#define HWA_DRAM_CTL15                  (0x800e0000 + 0x3c)
+#define HWT_DRAM_CTL15                  HWIO_32_RW
+#define HWN_DRAM_CTL15                  DRAM_CTL15
+#define HWI_DRAM_CTL15                  
+#define BP_DRAM_CTL15_RSVD4             28
+#define BM_DRAM_CTL15_RSVD4             0xf0000000
+#define BF_DRAM_CTL15_RSVD4(v)          (((v) & 0xf) << 28)
+#define BFM_DRAM_CTL15_RSVD4(v)         BM_DRAM_CTL15_RSVD4
+#define BF_DRAM_CTL15_RSVD4_V(e)        BF_DRAM_CTL15_RSVD4(BV_DRAM_CTL15_RSVD4__##e)
+#define BFM_DRAM_CTL15_RSVD4_V(v)       BM_DRAM_CTL15_RSVD4
+#define BP_DRAM_CTL15_TRP               24
+#define BM_DRAM_CTL15_TRP               0xf000000
+#define BF_DRAM_CTL15_TRP(v)            (((v) & 0xf) << 24)
+#define BFM_DRAM_CTL15_TRP(v)           BM_DRAM_CTL15_TRP
+#define BF_DRAM_CTL15_TRP_V(e)          BF_DRAM_CTL15_TRP(BV_DRAM_CTL15_TRP__##e)
+#define BFM_DRAM_CTL15_TRP_V(v)         BM_DRAM_CTL15_TRP
+#define BP_DRAM_CTL15_RSVD3             20
+#define BM_DRAM_CTL15_RSVD3             0xf00000
+#define BF_DRAM_CTL15_RSVD3(v)          (((v) & 0xf) << 20)
+#define BFM_DRAM_CTL15_RSVD3(v)         BM_DRAM_CTL15_RSVD3
+#define BF_DRAM_CTL15_RSVD3_V(e)        BF_DRAM_CTL15_RSVD3(BV_DRAM_CTL15_RSVD3__##e)
+#define BFM_DRAM_CTL15_RSVD3_V(v)       BM_DRAM_CTL15_RSVD3
+#define BP_DRAM_CTL15_TDAL              16
+#define BM_DRAM_CTL15_TDAL              0xf0000
+#define BF_DRAM_CTL15_TDAL(v)           (((v) & 0xf) << 16)
+#define BFM_DRAM_CTL15_TDAL(v)          BM_DRAM_CTL15_TDAL
+#define BF_DRAM_CTL15_TDAL_V(e)         BF_DRAM_CTL15_TDAL(BV_DRAM_CTL15_TDAL__##e)
+#define BFM_DRAM_CTL15_TDAL_V(v)        BM_DRAM_CTL15_TDAL
+#define BP_DRAM_CTL15_RSVD2             12
+#define BM_DRAM_CTL15_RSVD2             0xf000
+#define BF_DRAM_CTL15_RSVD2(v)          (((v) & 0xf) << 12)
+#define BFM_DRAM_CTL15_RSVD2(v)         BM_DRAM_CTL15_RSVD2
+#define BF_DRAM_CTL15_RSVD2_V(e)        BF_DRAM_CTL15_RSVD2(BV_DRAM_CTL15_RSVD2__##e)
+#define BFM_DRAM_CTL15_RSVD2_V(v)       BM_DRAM_CTL15_RSVD2
+#define BP_DRAM_CTL15_PORT_BUSY         8
+#define BM_DRAM_CTL15_PORT_BUSY         0xf00
+#define BF_DRAM_CTL15_PORT_BUSY(v)      (((v) & 0xf) << 8)
+#define BFM_DRAM_CTL15_PORT_BUSY(v)     BM_DRAM_CTL15_PORT_BUSY
+#define BF_DRAM_CTL15_PORT_BUSY_V(e)    BF_DRAM_CTL15_PORT_BUSY(BV_DRAM_CTL15_PORT_BUSY__##e)
+#define BFM_DRAM_CTL15_PORT_BUSY_V(v)   BM_DRAM_CTL15_PORT_BUSY
+#define BP_DRAM_CTL15_RSVD1             4
+#define BM_DRAM_CTL15_RSVD1             0xf0
+#define BF_DRAM_CTL15_RSVD1(v)          (((v) & 0xf) << 4)
+#define BFM_DRAM_CTL15_RSVD1(v)         BM_DRAM_CTL15_RSVD1
+#define BF_DRAM_CTL15_RSVD1_V(e)        BF_DRAM_CTL15_RSVD1(BV_DRAM_CTL15_RSVD1__##e)
+#define BFM_DRAM_CTL15_RSVD1_V(v)       BM_DRAM_CTL15_RSVD1
+#define BP_DRAM_CTL15_MAX_ROW_REG       0
+#define BM_DRAM_CTL15_MAX_ROW_REG       0xf
+#define BF_DRAM_CTL15_MAX_ROW_REG(v)    (((v) & 0xf) << 0)
+#define BFM_DRAM_CTL15_MAX_ROW_REG(v)   BM_DRAM_CTL15_MAX_ROW_REG
+#define BF_DRAM_CTL15_MAX_ROW_REG_V(e)  BF_DRAM_CTL15_MAX_ROW_REG(BV_DRAM_CTL15_MAX_ROW_REG__##e)
+#define BFM_DRAM_CTL15_MAX_ROW_REG_V(v) BM_DRAM_CTL15_MAX_ROW_REG
+
+#define HW_DRAM_CTL16                               HW(DRAM_CTL16)
+#define HWA_DRAM_CTL16                              (0x800e0000 + 0x40)
+#define HWT_DRAM_CTL16                              HWIO_32_RW
+#define HWN_DRAM_CTL16                              DRAM_CTL16
+#define HWI_DRAM_CTL16                              
+#define BP_DRAM_CTL16_RSVD4                         29
+#define BM_DRAM_CTL16_RSVD4                         0xe0000000
+#define BF_DRAM_CTL16_RSVD4(v)                      (((v) & 0x7) << 29)
+#define BFM_DRAM_CTL16_RSVD4(v)                     BM_DRAM_CTL16_RSVD4
+#define BF_DRAM_CTL16_RSVD4_V(e)                    BF_DRAM_CTL16_RSVD4(BV_DRAM_CTL16_RSVD4__##e)
+#define BFM_DRAM_CTL16_RSVD4_V(v)                   BM_DRAM_CTL16_RSVD4
+#define BP_DRAM_CTL16_TMRD                          24
+#define BM_DRAM_CTL16_TMRD                          0x1f000000
+#define BF_DRAM_CTL16_TMRD(v)                       (((v) & 0x1f) << 24)
+#define BFM_DRAM_CTL16_TMRD(v)                      BM_DRAM_CTL16_TMRD
+#define BF_DRAM_CTL16_TMRD_V(e)                     BF_DRAM_CTL16_TMRD(BV_DRAM_CTL16_TMRD__##e)
+#define BFM_DRAM_CTL16_TMRD_V(v)                    BM_DRAM_CTL16_TMRD
+#define BP_DRAM_CTL16_RSVD3                         21
+#define BM_DRAM_CTL16_RSVD3                         0xe00000
+#define BF_DRAM_CTL16_RSVD3(v)                      (((v) & 0x7) << 21)
+#define BFM_DRAM_CTL16_RSVD3(v)                     BM_DRAM_CTL16_RSVD3
+#define BF_DRAM_CTL16_RSVD3_V(e)                    BF_DRAM_CTL16_RSVD3(BV_DRAM_CTL16_RSVD3__##e)
+#define BFM_DRAM_CTL16_RSVD3_V(v)                   BM_DRAM_CTL16_RSVD3
+#define BP_DRAM_CTL16_LOWPOWER_CONTROL              16
+#define BM_DRAM_CTL16_LOWPOWER_CONTROL              0x1f0000
+#define BF_DRAM_CTL16_LOWPOWER_CONTROL(v)           (((v) & 0x1f) << 16)
+#define BFM_DRAM_CTL16_LOWPOWER_CONTROL(v)          BM_DRAM_CTL16_LOWPOWER_CONTROL
+#define BF_DRAM_CTL16_LOWPOWER_CONTROL_V(e)         BF_DRAM_CTL16_LOWPOWER_CONTROL(BV_DRAM_CTL16_LOWPOWER_CONTROL__##e)
+#define BFM_DRAM_CTL16_LOWPOWER_CONTROL_V(v)        BM_DRAM_CTL16_LOWPOWER_CONTROL
+#define BP_DRAM_CTL16_RSVD2                         13
+#define BM_DRAM_CTL16_RSVD2                         0xe000
+#define BF_DRAM_CTL16_RSVD2(v)                      (((v) & 0x7) << 13)
+#define BFM_DRAM_CTL16_RSVD2(v)                     BM_DRAM_CTL16_RSVD2
+#define BF_DRAM_CTL16_RSVD2_V(e)                    BF_DRAM_CTL16_RSVD2(BV_DRAM_CTL16_RSVD2__##e)
+#define BFM_DRAM_CTL16_RSVD2_V(v)                   BM_DRAM_CTL16_RSVD2
+#define BP_DRAM_CTL16_LOWPOWER_AUTO_ENABLE          8
+#define BM_DRAM_CTL16_LOWPOWER_AUTO_ENABLE          0x1f00
+#define BF_DRAM_CTL16_LOWPOWER_AUTO_ENABLE(v)       (((v) & 0x1f) << 8)
+#define BFM_DRAM_CTL16_LOWPOWER_AUTO_ENABLE(v)      BM_DRAM_CTL16_LOWPOWER_AUTO_ENABLE
+#define BF_DRAM_CTL16_LOWPOWER_AUTO_ENABLE_V(e)     BF_DRAM_CTL16_LOWPOWER_AUTO_ENABLE(BV_DRAM_CTL16_LOWPOWER_AUTO_ENABLE__##e)
+#define BFM_DRAM_CTL16_LOWPOWER_AUTO_ENABLE_V(v)    BM_DRAM_CTL16_LOWPOWER_AUTO_ENABLE
+#define BP_DRAM_CTL16_RSVD1                         4
+#define BM_DRAM_CTL16_RSVD1                         0xf0
+#define BF_DRAM_CTL16_RSVD1(v)                      (((v) & 0xf) << 4)
+#define BFM_DRAM_CTL16_RSVD1(v)                     BM_DRAM_CTL16_RSVD1
+#define BF_DRAM_CTL16_RSVD1_V(e)                    BF_DRAM_CTL16_RSVD1(BV_DRAM_CTL16_RSVD1__##e)
+#define BFM_DRAM_CTL16_RSVD1_V(v)                   BM_DRAM_CTL16_RSVD1
+#define BP_DRAM_CTL16_INT_ACK                       0
+#define BM_DRAM_CTL16_INT_ACK                       0xf
+#define BF_DRAM_CTL16_INT_ACK(v)                    (((v) & 0xf) << 0)
+#define BFM_DRAM_CTL16_INT_ACK(v)                   BM_DRAM_CTL16_INT_ACK
+#define BF_DRAM_CTL16_INT_ACK_V(e)                  BF_DRAM_CTL16_INT_ACK(BV_DRAM_CTL16_INT_ACK__##e)
+#define BFM_DRAM_CTL16_INT_ACK_V(v)                 BM_DRAM_CTL16_INT_ACK
+
+#define HW_DRAM_CTL17                       HW(DRAM_CTL17)
+#define HWA_DRAM_CTL17                      (0x800e0000 + 0x44)
+#define HWT_DRAM_CTL17                      HWIO_32_RW
+#define HWN_DRAM_CTL17                      DRAM_CTL17
+#define HWI_DRAM_CTL17                      
+#define BP_DRAM_CTL17_DLL_START_POINT       24
+#define BM_DRAM_CTL17_DLL_START_POINT       0xff000000
+#define BF_DRAM_CTL17_DLL_START_POINT(v)    (((v) & 0xff) << 24)
+#define BFM_DRAM_CTL17_DLL_START_POINT(v)   BM_DRAM_CTL17_DLL_START_POINT
+#define BF_DRAM_CTL17_DLL_START_POINT_V(e)  BF_DRAM_CTL17_DLL_START_POINT(BV_DRAM_CTL17_DLL_START_POINT__##e)
+#define BFM_DRAM_CTL17_DLL_START_POINT_V(v) BM_DRAM_CTL17_DLL_START_POINT
+#define BP_DRAM_CTL17_DLL_LOCK              16
+#define BM_DRAM_CTL17_DLL_LOCK              0xff0000
+#define BF_DRAM_CTL17_DLL_LOCK(v)           (((v) & 0xff) << 16)
+#define BFM_DRAM_CTL17_DLL_LOCK(v)          BM_DRAM_CTL17_DLL_LOCK
+#define BF_DRAM_CTL17_DLL_LOCK_V(e)         BF_DRAM_CTL17_DLL_LOCK(BV_DRAM_CTL17_DLL_LOCK__##e)
+#define BFM_DRAM_CTL17_DLL_LOCK_V(v)        BM_DRAM_CTL17_DLL_LOCK
+#define BP_DRAM_CTL17_DLL_INCREMENT         8
+#define BM_DRAM_CTL17_DLL_INCREMENT         0xff00
+#define BF_DRAM_CTL17_DLL_INCREMENT(v)      (((v) & 0xff) << 8)
+#define BFM_DRAM_CTL17_DLL_INCREMENT(v)     BM_DRAM_CTL17_DLL_INCREMENT
+#define BF_DRAM_CTL17_DLL_INCREMENT_V(e)    BF_DRAM_CTL17_DLL_INCREMENT(BV_DRAM_CTL17_DLL_INCREMENT__##e)
+#define BFM_DRAM_CTL17_DLL_INCREMENT_V(v)   BM_DRAM_CTL17_DLL_INCREMENT
+#define BP_DRAM_CTL17_RSVD1                 5
+#define BM_DRAM_CTL17_RSVD1                 0xe0
+#define BF_DRAM_CTL17_RSVD1(v)              (((v) & 0x7) << 5)
+#define BFM_DRAM_CTL17_RSVD1(v)             BM_DRAM_CTL17_RSVD1
+#define BF_DRAM_CTL17_RSVD1_V(e)            BF_DRAM_CTL17_RSVD1(BV_DRAM_CTL17_RSVD1__##e)
+#define BFM_DRAM_CTL17_RSVD1_V(v)           BM_DRAM_CTL17_RSVD1
+#define BP_DRAM_CTL17_TRC                   0
+#define BM_DRAM_CTL17_TRC                   0x1f
+#define BF_DRAM_CTL17_TRC(v)                (((v) & 0x1f) << 0)
+#define BFM_DRAM_CTL17_TRC(v)               BM_DRAM_CTL17_TRC
+#define BF_DRAM_CTL17_TRC_V(e)              BF_DRAM_CTL17_TRC(BV_DRAM_CTL17_TRC__##e)
+#define BFM_DRAM_CTL17_TRC_V(v)             BM_DRAM_CTL17_TRC
+
+#define HW_DRAM_CTL18                       HW(DRAM_CTL18)
+#define HWA_DRAM_CTL18                      (0x800e0000 + 0x48)
+#define HWT_DRAM_CTL18                      HWIO_32_RW
+#define HWN_DRAM_CTL18                      DRAM_CTL18
+#define HWI_DRAM_CTL18                      
+#define BP_DRAM_CTL18_RSVD4                 31
+#define BM_DRAM_CTL18_RSVD4                 0x80000000
+#define BF_DRAM_CTL18_RSVD4(v)              (((v) & 0x1) << 31)
+#define BFM_DRAM_CTL18_RSVD4(v)             BM_DRAM_CTL18_RSVD4
+#define BF_DRAM_CTL18_RSVD4_V(e)            BF_DRAM_CTL18_RSVD4(BV_DRAM_CTL18_RSVD4__##e)
+#define BFM_DRAM_CTL18_RSVD4_V(v)           BM_DRAM_CTL18_RSVD4
+#define BP_DRAM_CTL18_DLL_DQS_DELAY_1       24
+#define BM_DRAM_CTL18_DLL_DQS_DELAY_1       0x7f000000
+#define BF_DRAM_CTL18_DLL_DQS_DELAY_1(v)    (((v) & 0x7f) << 24)
+#define BFM_DRAM_CTL18_DLL_DQS_DELAY_1(v)   BM_DRAM_CTL18_DLL_DQS_DELAY_1
+#define BF_DRAM_CTL18_DLL_DQS_DELAY_1_V(e)  BF_DRAM_CTL18_DLL_DQS_DELAY_1(BV_DRAM_CTL18_DLL_DQS_DELAY_1__##e)
+#define BFM_DRAM_CTL18_DLL_DQS_DELAY_1_V(v) BM_DRAM_CTL18_DLL_DQS_DELAY_1
+#define BP_DRAM_CTL18_RSVD3                 23
+#define BM_DRAM_CTL18_RSVD3                 0x800000
+#define BF_DRAM_CTL18_RSVD3(v)              (((v) & 0x1) << 23)
+#define BFM_DRAM_CTL18_RSVD3(v)             BM_DRAM_CTL18_RSVD3
+#define BF_DRAM_CTL18_RSVD3_V(e)            BF_DRAM_CTL18_RSVD3(BV_DRAM_CTL18_RSVD3__##e)
+#define BFM_DRAM_CTL18_RSVD3_V(v)           BM_DRAM_CTL18_RSVD3
+#define BP_DRAM_CTL18_DLL_DQS_DELAY_0       16
+#define BM_DRAM_CTL18_DLL_DQS_DELAY_0       0x7f0000
+#define BF_DRAM_CTL18_DLL_DQS_DELAY_0(v)    (((v) & 0x7f) << 16)
+#define BFM_DRAM_CTL18_DLL_DQS_DELAY_0(v)   BM_DRAM_CTL18_DLL_DQS_DELAY_0
+#define BF_DRAM_CTL18_DLL_DQS_DELAY_0_V(e)  BF_DRAM_CTL18_DLL_DQS_DELAY_0(BV_DRAM_CTL18_DLL_DQS_DELAY_0__##e)
+#define BFM_DRAM_CTL18_DLL_DQS_DELAY_0_V(v) BM_DRAM_CTL18_DLL_DQS_DELAY_0
+#define BP_DRAM_CTL18_RSVD2                 13
+#define BM_DRAM_CTL18_RSVD2                 0xe000
+#define BF_DRAM_CTL18_RSVD2(v)              (((v) & 0x7) << 13)
+#define BFM_DRAM_CTL18_RSVD2(v)             BM_DRAM_CTL18_RSVD2
+#define BF_DRAM_CTL18_RSVD2_V(e)            BF_DRAM_CTL18_RSVD2(BV_DRAM_CTL18_RSVD2__##e)
+#define BFM_DRAM_CTL18_RSVD2_V(v)           BM_DRAM_CTL18_RSVD2
+#define BP_DRAM_CTL18_INT_STATUS            8
+#define BM_DRAM_CTL18_INT_STATUS            0x1f00
+#define BF_DRAM_CTL18_INT_STATUS(v)         (((v) & 0x1f) << 8)
+#define BFM_DRAM_CTL18_INT_STATUS(v)        BM_DRAM_CTL18_INT_STATUS
+#define BF_DRAM_CTL18_INT_STATUS_V(e)       BF_DRAM_CTL18_INT_STATUS(BV_DRAM_CTL18_INT_STATUS__##e)
+#define BFM_DRAM_CTL18_INT_STATUS_V(v)      BM_DRAM_CTL18_INT_STATUS
+#define BP_DRAM_CTL18_RSVD1                 5
+#define BM_DRAM_CTL18_RSVD1                 0xe0
+#define BF_DRAM_CTL18_RSVD1(v)              (((v) & 0x7) << 5)
+#define BFM_DRAM_CTL18_RSVD1(v)             BM_DRAM_CTL18_RSVD1
+#define BF_DRAM_CTL18_RSVD1_V(e)            BF_DRAM_CTL18_RSVD1(BV_DRAM_CTL18_RSVD1__##e)
+#define BFM_DRAM_CTL18_RSVD1_V(v)           BM_DRAM_CTL18_RSVD1
+#define BP_DRAM_CTL18_INT_MASK              0
+#define BM_DRAM_CTL18_INT_MASK              0x1f
+#define BF_DRAM_CTL18_INT_MASK(v)           (((v) & 0x1f) << 0)
+#define BFM_DRAM_CTL18_INT_MASK(v)          BM_DRAM_CTL18_INT_MASK
+#define BF_DRAM_CTL18_INT_MASK_V(e)         BF_DRAM_CTL18_INT_MASK(BV_DRAM_CTL18_INT_MASK__##e)
+#define BFM_DRAM_CTL18_INT_MASK_V(v)        BM_DRAM_CTL18_INT_MASK
+
+#define HW_DRAM_CTL19                               HW(DRAM_CTL19)
+#define HWA_DRAM_CTL19                              (0x800e0000 + 0x4c)
+#define HWT_DRAM_CTL19                              HWIO_32_RW
+#define HWN_DRAM_CTL19                              DRAM_CTL19
+#define HWI_DRAM_CTL19                              
+#define BP_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS          24
+#define BM_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS          0xff000000
+#define BF_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS(v)       (((v) & 0xff) << 24)
+#define BFM_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS(v)      BM_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS
+#define BF_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS_V(e)     BF_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS(BV_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS__##e)
+#define BFM_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS_V(v)    BM_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS
+#define BP_DRAM_CTL19_RSVD1                         23
+#define BM_DRAM_CTL19_RSVD1                         0x800000
+#define BF_DRAM_CTL19_RSVD1(v)                      (((v) & 0x1) << 23)
+#define BFM_DRAM_CTL19_RSVD1(v)                     BM_DRAM_CTL19_RSVD1
+#define BF_DRAM_CTL19_RSVD1_V(e)                    BF_DRAM_CTL19_RSVD1(BV_DRAM_CTL19_RSVD1__##e)
+#define BFM_DRAM_CTL19_RSVD1_V(v)                   BM_DRAM_CTL19_RSVD1
+#define BP_DRAM_CTL19_DQS_OUT_SHIFT                 16
+#define BM_DRAM_CTL19_DQS_OUT_SHIFT                 0x7f0000
+#define BF_DRAM_CTL19_DQS_OUT_SHIFT(v)              (((v) & 0x7f) << 16)
+#define BFM_DRAM_CTL19_DQS_OUT_SHIFT(v)             BM_DRAM_CTL19_DQS_OUT_SHIFT
+#define BF_DRAM_CTL19_DQS_OUT_SHIFT_V(e)            BF_DRAM_CTL19_DQS_OUT_SHIFT(BV_DRAM_CTL19_DQS_OUT_SHIFT__##e)
+#define BFM_DRAM_CTL19_DQS_OUT_SHIFT_V(v)           BM_DRAM_CTL19_DQS_OUT_SHIFT
+#define BP_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1        8
+#define BM_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1        0xff00
+#define BF_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1(v)     (((v) & 0xff) << 8)
+#define BFM_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1(v)    BM_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1
+#define BF_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1_V(e)   BF_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1(BV_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1__##e)
+#define BFM_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1_V(v)  BM_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1
+#define BP_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0        0
+#define BM_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0        0xff
+#define BF_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0(v)     (((v) & 0xff) << 0)
+#define BFM_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0(v)    BM_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0
+#define BF_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0_V(e)   BF_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0(BV_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0__##e)
+#define BFM_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0_V(v)  BM_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0
+
+#define HW_DRAM_CTL20                           HW(DRAM_CTL20)
+#define HWA_DRAM_CTL20                          (0x800e0000 + 0x50)
+#define HWT_DRAM_CTL20                          HWIO_32_RW
+#define HWN_DRAM_CTL20                          DRAM_CTL20
+#define HWI_DRAM_CTL20                          
+#define BP_DRAM_CTL20_TRCD_INT                  24
+#define BM_DRAM_CTL20_TRCD_INT                  0xff000000
+#define BF_DRAM_CTL20_TRCD_INT(v)               (((v) & 0xff) << 24)
+#define BFM_DRAM_CTL20_TRCD_INT(v)              BM_DRAM_CTL20_TRCD_INT
+#define BF_DRAM_CTL20_TRCD_INT_V(e)             BF_DRAM_CTL20_TRCD_INT(BV_DRAM_CTL20_TRCD_INT__##e)
+#define BFM_DRAM_CTL20_TRCD_INT_V(v)            BM_DRAM_CTL20_TRCD_INT
+#define BP_DRAM_CTL20_TRAS_MIN                  16
+#define BM_DRAM_CTL20_TRAS_MIN                  0xff0000
+#define BF_DRAM_CTL20_TRAS_MIN(v)               (((v) & 0xff) << 16)
+#define BFM_DRAM_CTL20_TRAS_MIN(v)              BM_DRAM_CTL20_TRAS_MIN
+#define BF_DRAM_CTL20_TRAS_MIN_V(e)             BF_DRAM_CTL20_TRAS_MIN(BV_DRAM_CTL20_TRAS_MIN__##e)
+#define BFM_DRAM_CTL20_TRAS_MIN_V(v)            BM_DRAM_CTL20_TRAS_MIN
+#define BP_DRAM_CTL20_WR_DQS_SHIFT_BYPASS       8
+#define BM_DRAM_CTL20_WR_DQS_SHIFT_BYPASS       0xff00
+#define BF_DRAM_CTL20_WR_DQS_SHIFT_BYPASS(v)    (((v) & 0xff) << 8)
+#define BFM_DRAM_CTL20_WR_DQS_SHIFT_BYPASS(v)   BM_DRAM_CTL20_WR_DQS_SHIFT_BYPASS
+#define BF_DRAM_CTL20_WR_DQS_SHIFT_BYPASS_V(e)  BF_DRAM_CTL20_WR_DQS_SHIFT_BYPASS(BV_DRAM_CTL20_WR_DQS_SHIFT_BYPASS__##e)
+#define BFM_DRAM_CTL20_WR_DQS_SHIFT_BYPASS_V(v) BM_DRAM_CTL20_WR_DQS_SHIFT_BYPASS
+#define BP_DRAM_CTL20_RSVD1                     7
+#define BM_DRAM_CTL20_RSVD1                     0x80
+#define BF_DRAM_CTL20_RSVD1(v)                  (((v) & 0x1) << 7)
+#define BFM_DRAM_CTL20_RSVD1(v)                 BM_DRAM_CTL20_RSVD1
+#define BF_DRAM_CTL20_RSVD1_V(e)                BF_DRAM_CTL20_RSVD1(BV_DRAM_CTL20_RSVD1__##e)
+#define BFM_DRAM_CTL20_RSVD1_V(v)               BM_DRAM_CTL20_RSVD1
+#define BP_DRAM_CTL20_WR_DQS_SHIFT              0
+#define BM_DRAM_CTL20_WR_DQS_SHIFT              0x7f
+#define BF_DRAM_CTL20_WR_DQS_SHIFT(v)           (((v) & 0x7f) << 0)
+#define BFM_DRAM_CTL20_WR_DQS_SHIFT(v)          BM_DRAM_CTL20_WR_DQS_SHIFT
+#define BF_DRAM_CTL20_WR_DQS_SHIFT_V(e)         BF_DRAM_CTL20_WR_DQS_SHIFT(BV_DRAM_CTL20_WR_DQS_SHIFT__##e)
+#define BFM_DRAM_CTL20_WR_DQS_SHIFT_V(v)        BM_DRAM_CTL20_WR_DQS_SHIFT
+
+#define HW_DRAM_CTL21                           HW(DRAM_CTL21)
+#define HWA_DRAM_CTL21                          (0x800e0000 + 0x54)
+#define HWT_DRAM_CTL21                          HWIO_32_RW
+#define HWN_DRAM_CTL21                          DRAM_CTL21
+#define HWI_DRAM_CTL21                          
+#define BP_DRAM_CTL21_OBSOLETE                  24
+#define BM_DRAM_CTL21_OBSOLETE                  0xff000000
+#define BF_DRAM_CTL21_OBSOLETE(v)               (((v) & 0xff) << 24)
+#define BFM_DRAM_CTL21_OBSOLETE(v)              BM_DRAM_CTL21_OBSOLETE
+#define BF_DRAM_CTL21_OBSOLETE_V(e)             BF_DRAM_CTL21_OBSOLETE(BV_DRAM_CTL21_OBSOLETE__##e)
+#define BFM_DRAM_CTL21_OBSOLETE_V(v)            BM_DRAM_CTL21_OBSOLETE
+#define BP_DRAM_CTL21_RSVD1                     18
+#define BM_DRAM_CTL21_RSVD1                     0xfc0000
+#define BF_DRAM_CTL21_RSVD1(v)                  (((v) & 0x3f) << 18)
+#define BFM_DRAM_CTL21_RSVD1(v)                 BM_DRAM_CTL21_RSVD1
+#define BF_DRAM_CTL21_RSVD1_V(e)                BF_DRAM_CTL21_RSVD1(BV_DRAM_CTL21_RSVD1__##e)
+#define BFM_DRAM_CTL21_RSVD1_V(v)               BM_DRAM_CTL21_RSVD1
+#define BP_DRAM_CTL21_OUT_OF_RANGE_LENGTH       8
+#define BM_DRAM_CTL21_OUT_OF_RANGE_LENGTH       0x3ff00
+#define BF_DRAM_CTL21_OUT_OF_RANGE_LENGTH(v)    (((v) & 0x3ff) << 8)
+#define BFM_DRAM_CTL21_OUT_OF_RANGE_LENGTH(v)   BM_DRAM_CTL21_OUT_OF_RANGE_LENGTH
+#define BF_DRAM_CTL21_OUT_OF_RANGE_LENGTH_V(e)  BF_DRAM_CTL21_OUT_OF_RANGE_LENGTH(BV_DRAM_CTL21_OUT_OF_RANGE_LENGTH__##e)
+#define BFM_DRAM_CTL21_OUT_OF_RANGE_LENGTH_V(v) BM_DRAM_CTL21_OUT_OF_RANGE_LENGTH
+#define BP_DRAM_CTL21_TRFC                      0
+#define BM_DRAM_CTL21_TRFC                      0xff
+#define BF_DRAM_CTL21_TRFC(v)                   (((v) & 0xff) << 0)
+#define BFM_DRAM_CTL21_TRFC(v)                  BM_DRAM_CTL21_TRFC
+#define BF_DRAM_CTL21_TRFC_V(e)                 BF_DRAM_CTL21_TRFC(BV_DRAM_CTL21_TRFC__##e)
+#define BFM_DRAM_CTL21_TRFC_V(v)                BM_DRAM_CTL21_TRFC
+
+#define HW_DRAM_CTL22                   HW(DRAM_CTL22)
+#define HWA_DRAM_CTL22                  (0x800e0000 + 0x58)
+#define HWT_DRAM_CTL22                  HWIO_32_RW
+#define HWN_DRAM_CTL22                  DRAM_CTL22
+#define HWI_DRAM_CTL22                  
+#define BP_DRAM_CTL22_RSVD2             27
+#define BM_DRAM_CTL22_RSVD2             0xf8000000
+#define BF_DRAM_CTL22_RSVD2(v)          (((v) & 0x1f) << 27)
+#define BFM_DRAM_CTL22_RSVD2(v)         BM_DRAM_CTL22_RSVD2
+#define BF_DRAM_CTL22_RSVD2_V(e)        BF_DRAM_CTL22_RSVD2(BV_DRAM_CTL22_RSVD2__##e)
+#define BFM_DRAM_CTL22_RSVD2_V(v)       BM_DRAM_CTL22_RSVD2
+#define BP_DRAM_CTL22_AHB0_WRCNT        16
+#define BM_DRAM_CTL22_AHB0_WRCNT        0x7ff0000
+#define BF_DRAM_CTL22_AHB0_WRCNT(v)     (((v) & 0x7ff) << 16)
+#define BFM_DRAM_CTL22_AHB0_WRCNT(v)    BM_DRAM_CTL22_AHB0_WRCNT
+#define BF_DRAM_CTL22_AHB0_WRCNT_V(e)   BF_DRAM_CTL22_AHB0_WRCNT(BV_DRAM_CTL22_AHB0_WRCNT__##e)
+#define BFM_DRAM_CTL22_AHB0_WRCNT_V(v)  BM_DRAM_CTL22_AHB0_WRCNT
+#define BP_DRAM_CTL22_RSVD1             11
+#define BM_DRAM_CTL22_RSVD1             0xf800
+#define BF_DRAM_CTL22_RSVD1(v)          (((v) & 0x1f) << 11)
+#define BFM_DRAM_CTL22_RSVD1(v)         BM_DRAM_CTL22_RSVD1
+#define BF_DRAM_CTL22_RSVD1_V(e)        BF_DRAM_CTL22_RSVD1(BV_DRAM_CTL22_RSVD1__##e)
+#define BFM_DRAM_CTL22_RSVD1_V(v)       BM_DRAM_CTL22_RSVD1
+#define BP_DRAM_CTL22_AHB0_RDCNT        0
+#define BM_DRAM_CTL22_AHB0_RDCNT        0x7ff
+#define BF_DRAM_CTL22_AHB0_RDCNT(v)     (((v) & 0x7ff) << 0)
+#define BFM_DRAM_CTL22_AHB0_RDCNT(v)    BM_DRAM_CTL22_AHB0_RDCNT
+#define BF_DRAM_CTL22_AHB0_RDCNT_V(e)   BF_DRAM_CTL22_AHB0_RDCNT(BV_DRAM_CTL22_AHB0_RDCNT__##e)
+#define BFM_DRAM_CTL22_AHB0_RDCNT_V(v)  BM_DRAM_CTL22_AHB0_RDCNT
+
+#define HW_DRAM_CTL23                   HW(DRAM_CTL23)
+#define HWA_DRAM_CTL23                  (0x800e0000 + 0x5c)
+#define HWT_DRAM_CTL23                  HWIO_32_RW
+#define HWN_DRAM_CTL23                  DRAM_CTL23
+#define HWI_DRAM_CTL23                  
+#define BP_DRAM_CTL23_RSVD2             27
+#define BM_DRAM_CTL23_RSVD2             0xf8000000
+#define BF_DRAM_CTL23_RSVD2(v)          (((v) & 0x1f) << 27)
+#define BFM_DRAM_CTL23_RSVD2(v)         BM_DRAM_CTL23_RSVD2
+#define BF_DRAM_CTL23_RSVD2_V(e)        BF_DRAM_CTL23_RSVD2(BV_DRAM_CTL23_RSVD2__##e)
+#define BFM_DRAM_CTL23_RSVD2_V(v)       BM_DRAM_CTL23_RSVD2
+#define BP_DRAM_CTL23_AHB1_WRCNT        16
+#define BM_DRAM_CTL23_AHB1_WRCNT        0x7ff0000
+#define BF_DRAM_CTL23_AHB1_WRCNT(v)     (((v) & 0x7ff) << 16)
+#define BFM_DRAM_CTL23_AHB1_WRCNT(v)    BM_DRAM_CTL23_AHB1_WRCNT
+#define BF_DRAM_CTL23_AHB1_WRCNT_V(e)   BF_DRAM_CTL23_AHB1_WRCNT(BV_DRAM_CTL23_AHB1_WRCNT__##e)
+#define BFM_DRAM_CTL23_AHB1_WRCNT_V(v)  BM_DRAM_CTL23_AHB1_WRCNT
+#define BP_DRAM_CTL23_RSVD1             11
+#define BM_DRAM_CTL23_RSVD1             0xf800
+#define BF_DRAM_CTL23_RSVD1(v)          (((v) & 0x1f) << 11)
+#define BFM_DRAM_CTL23_RSVD1(v)         BM_DRAM_CTL23_RSVD1
+#define BF_DRAM_CTL23_RSVD1_V(e)        BF_DRAM_CTL23_RSVD1(BV_DRAM_CTL23_RSVD1__##e)
+#define BFM_DRAM_CTL23_RSVD1_V(v)       BM_DRAM_CTL23_RSVD1
+#define BP_DRAM_CTL23_AHB1_RDCNT        0
+#define BM_DRAM_CTL23_AHB1_RDCNT        0x7ff
+#define BF_DRAM_CTL23_AHB1_RDCNT(v)     (((v) & 0x7ff) << 0)
+#define BFM_DRAM_CTL23_AHB1_RDCNT(v)    BM_DRAM_CTL23_AHB1_RDCNT
+#define BF_DRAM_CTL23_AHB1_RDCNT_V(e)   BF_DRAM_CTL23_AHB1_RDCNT(BV_DRAM_CTL23_AHB1_RDCNT__##e)
+#define BFM_DRAM_CTL23_AHB1_RDCNT_V(v)  BM_DRAM_CTL23_AHB1_RDCNT
+
+#define HW_DRAM_CTL24                   HW(DRAM_CTL24)
+#define HWA_DRAM_CTL24                  (0x800e0000 + 0x60)
+#define HWT_DRAM_CTL24                  HWIO_32_RW
+#define HWN_DRAM_CTL24                  DRAM_CTL24
+#define HWI_DRAM_CTL24                  
+#define BP_DRAM_CTL24_RSVD2             27
+#define BM_DRAM_CTL24_RSVD2             0xf8000000
+#define BF_DRAM_CTL24_RSVD2(v)          (((v) & 0x1f) << 27)
+#define BFM_DRAM_CTL24_RSVD2(v)         BM_DRAM_CTL24_RSVD2
+#define BF_DRAM_CTL24_RSVD2_V(e)        BF_DRAM_CTL24_RSVD2(BV_DRAM_CTL24_RSVD2__##e)
+#define BFM_DRAM_CTL24_RSVD2_V(v)       BM_DRAM_CTL24_RSVD2
+#define BP_DRAM_CTL24_AHB2_WRCNT        16
+#define BM_DRAM_CTL24_AHB2_WRCNT        0x7ff0000
+#define BF_DRAM_CTL24_AHB2_WRCNT(v)     (((v) & 0x7ff) << 16)
+#define BFM_DRAM_CTL24_AHB2_WRCNT(v)    BM_DRAM_CTL24_AHB2_WRCNT
+#define BF_DRAM_CTL24_AHB2_WRCNT_V(e)   BF_DRAM_CTL24_AHB2_WRCNT(BV_DRAM_CTL24_AHB2_WRCNT__##e)
+#define BFM_DRAM_CTL24_AHB2_WRCNT_V(v)  BM_DRAM_CTL24_AHB2_WRCNT
+#define BP_DRAM_CTL24_RSVD1             11
+#define BM_DRAM_CTL24_RSVD1             0xf800
+#define BF_DRAM_CTL24_RSVD1(v)          (((v) & 0x1f) << 11)
+#define BFM_DRAM_CTL24_RSVD1(v)         BM_DRAM_CTL24_RSVD1
+#define BF_DRAM_CTL24_RSVD1_V(e)        BF_DRAM_CTL24_RSVD1(BV_DRAM_CTL24_RSVD1__##e)
+#define BFM_DRAM_CTL24_RSVD1_V(v)       BM_DRAM_CTL24_RSVD1
+#define BP_DRAM_CTL24_AHB2_RDCNT        0
+#define BM_DRAM_CTL24_AHB2_RDCNT        0x7ff
+#define BF_DRAM_CTL24_AHB2_RDCNT(v)     (((v) & 0x7ff) << 0)
+#define BFM_DRAM_CTL24_AHB2_RDCNT(v)    BM_DRAM_CTL24_AHB2_RDCNT
+#define BF_DRAM_CTL24_AHB2_RDCNT_V(e)   BF_DRAM_CTL24_AHB2_RDCNT(BV_DRAM_CTL24_AHB2_RDCNT__##e)
+#define BFM_DRAM_CTL24_AHB2_RDCNT_V(v)  BM_DRAM_CTL24_AHB2_RDCNT
+
+#define HW_DRAM_CTL25                   HW(DRAM_CTL25)
+#define HWA_DRAM_CTL25                  (0x800e0000 + 0x64)
+#define HWT_DRAM_CTL25                  HWIO_32_RW
+#define HWN_DRAM_CTL25                  DRAM_CTL25
+#define HWI_DRAM_CTL25                  
+#define BP_DRAM_CTL25_RSVD2             27
+#define BM_DRAM_CTL25_RSVD2             0xf8000000
+#define BF_DRAM_CTL25_RSVD2(v)          (((v) & 0x1f) << 27)
+#define BFM_DRAM_CTL25_RSVD2(v)         BM_DRAM_CTL25_RSVD2
+#define BF_DRAM_CTL25_RSVD2_V(e)        BF_DRAM_CTL25_RSVD2(BV_DRAM_CTL25_RSVD2__##e)
+#define BFM_DRAM_CTL25_RSVD2_V(v)       BM_DRAM_CTL25_RSVD2
+#define BP_DRAM_CTL25_AHB3_WRCNT        16
+#define BM_DRAM_CTL25_AHB3_WRCNT        0x7ff0000
+#define BF_DRAM_CTL25_AHB3_WRCNT(v)     (((v) & 0x7ff) << 16)
+#define BFM_DRAM_CTL25_AHB3_WRCNT(v)    BM_DRAM_CTL25_AHB3_WRCNT
+#define BF_DRAM_CTL25_AHB3_WRCNT_V(e)   BF_DRAM_CTL25_AHB3_WRCNT(BV_DRAM_CTL25_AHB3_WRCNT__##e)
+#define BFM_DRAM_CTL25_AHB3_WRCNT_V(v)  BM_DRAM_CTL25_AHB3_WRCNT
+#define BP_DRAM_CTL25_RSVD1             11
+#define BM_DRAM_CTL25_RSVD1             0xf800
+#define BF_DRAM_CTL25_RSVD1(v)          (((v) & 0x1f) << 11)
+#define BFM_DRAM_CTL25_RSVD1(v)         BM_DRAM_CTL25_RSVD1
+#define BF_DRAM_CTL25_RSVD1_V(e)        BF_DRAM_CTL25_RSVD1(BV_DRAM_CTL25_RSVD1__##e)
+#define BFM_DRAM_CTL25_RSVD1_V(v)       BM_DRAM_CTL25_RSVD1
+#define BP_DRAM_CTL25_AHB3_RDCNT        0
+#define BM_DRAM_CTL25_AHB3_RDCNT        0x7ff
+#define BF_DRAM_CTL25_AHB3_RDCNT(v)     (((v) & 0x7ff) << 0)
+#define BFM_DRAM_CTL25_AHB3_RDCNT(v)    BM_DRAM_CTL25_AHB3_RDCNT
+#define BF_DRAM_CTL25_AHB3_RDCNT_V(e)   BF_DRAM_CTL25_AHB3_RDCNT(BV_DRAM_CTL25_AHB3_RDCNT__##e)
+#define BFM_DRAM_CTL25_AHB3_RDCNT_V(v)  BM_DRAM_CTL25_AHB3_RDCNT
+
+#define HW_DRAM_CTL26                   HW(DRAM_CTL26)
+#define HWA_DRAM_CTL26                  (0x800e0000 + 0x68)
+#define HWT_DRAM_CTL26                  HWIO_32_RW
+#define HWN_DRAM_CTL26                  DRAM_CTL26
+#define HWI_DRAM_CTL26                  
+#define BP_DRAM_CTL26_OBSOLETE          16
+#define BM_DRAM_CTL26_OBSOLETE          0xffff0000
+#define BF_DRAM_CTL26_OBSOLETE(v)       (((v) & 0xffff) << 16)
+#define BFM_DRAM_CTL26_OBSOLETE(v)      BM_DRAM_CTL26_OBSOLETE
+#define BF_DRAM_CTL26_OBSOLETE_V(e)     BF_DRAM_CTL26_OBSOLETE(BV_DRAM_CTL26_OBSOLETE__##e)
+#define BFM_DRAM_CTL26_OBSOLETE_V(v)    BM_DRAM_CTL26_OBSOLETE
+#define BP_DRAM_CTL26_RSVD1             12
+#define BM_DRAM_CTL26_RSVD1             0xf000
+#define BF_DRAM_CTL26_RSVD1(v)          (((v) & 0xf) << 12)
+#define BFM_DRAM_CTL26_RSVD1(v)         BM_DRAM_CTL26_RSVD1
+#define BF_DRAM_CTL26_RSVD1_V(e)        BF_DRAM_CTL26_RSVD1(BV_DRAM_CTL26_RSVD1__##e)
+#define BFM_DRAM_CTL26_RSVD1_V(v)       BM_DRAM_CTL26_RSVD1
+#define BP_DRAM_CTL26_TREF              0
+#define BM_DRAM_CTL26_TREF              0xfff
+#define BF_DRAM_CTL26_TREF(v)           (((v) & 0xfff) << 0)
+#define BFM_DRAM_CTL26_TREF(v)          BM_DRAM_CTL26_TREF
+#define BF_DRAM_CTL26_TREF_V(e)         BF_DRAM_CTL26_TREF(BV_DRAM_CTL26_TREF__##e)
+#define BFM_DRAM_CTL26_TREF_V(v)        BM_DRAM_CTL26_TREF
+
+#define HW_DRAM_CTL27                   HW(DRAM_CTL27)
+#define HWA_DRAM_CTL27                  (0x800e0000 + 0x6c)
+#define HWT_DRAM_CTL27                  HWIO_32_RW
+#define HWN_DRAM_CTL27                  DRAM_CTL27
+#define HWI_DRAM_CTL27                  
+#define BP_DRAM_CTL27_OBSOLETE          0
+#define BM_DRAM_CTL27_OBSOLETE          0xffffffff
+#define BF_DRAM_CTL27_OBSOLETE(v)       (((v) & 0xffffffff) << 0)
+#define BFM_DRAM_CTL27_OBSOLETE(v)      BM_DRAM_CTL27_OBSOLETE
+#define BF_DRAM_CTL27_OBSOLETE_V(e)     BF_DRAM_CTL27_OBSOLETE(BV_DRAM_CTL27_OBSOLETE__##e)
+#define BFM_DRAM_CTL27_OBSOLETE_V(v)    BM_DRAM_CTL27_OBSOLETE
+
+#define HW_DRAM_CTL28                   HW(DRAM_CTL28)
+#define HWA_DRAM_CTL28                  (0x800e0000 + 0x70)
+#define HWT_DRAM_CTL28                  HWIO_32_RW
+#define HWN_DRAM_CTL28                  DRAM_CTL28
+#define HWI_DRAM_CTL28                  
+#define BP_DRAM_CTL28_OBSOLETE          0
+#define BM_DRAM_CTL28_OBSOLETE          0xffffffff
+#define BF_DRAM_CTL28_OBSOLETE(v)       (((v) & 0xffffffff) << 0)
+#define BFM_DRAM_CTL28_OBSOLETE(v)      BM_DRAM_CTL28_OBSOLETE
+#define BF_DRAM_CTL28_OBSOLETE_V(e)     BF_DRAM_CTL28_OBSOLETE(BV_DRAM_CTL28_OBSOLETE__##e)
+#define BFM_DRAM_CTL28_OBSOLETE_V(v)    BM_DRAM_CTL28_OBSOLETE
+
+#define HW_DRAM_CTL29                               HW(DRAM_CTL29)
+#define HWA_DRAM_CTL29                              (0x800e0000 + 0x74)
+#define HWT_DRAM_CTL29                              HWIO_32_RW
+#define HWN_DRAM_CTL29                              DRAM_CTL29
+#define HWI_DRAM_CTL29                              
+#define BP_DRAM_CTL29_LOWPOWER_INTERNAL_CNT         16
+#define BM_DRAM_CTL29_LOWPOWER_INTERNAL_CNT         0xffff0000
+#define BF_DRAM_CTL29_LOWPOWER_INTERNAL_CNT(v)      (((v) & 0xffff) << 16)
+#define BFM_DRAM_CTL29_LOWPOWER_INTERNAL_CNT(v)     BM_DRAM_CTL29_LOWPOWER_INTERNAL_CNT
+#define BF_DRAM_CTL29_LOWPOWER_INTERNAL_CNT_V(e)    BF_DRAM_CTL29_LOWPOWER_INTERNAL_CNT(BV_DRAM_CTL29_LOWPOWER_INTERNAL_CNT__##e)
+#define BFM_DRAM_CTL29_LOWPOWER_INTERNAL_CNT_V(v)   BM_DRAM_CTL29_LOWPOWER_INTERNAL_CNT
+#define BP_DRAM_CTL29_LOWPOWER_EXTERNAL_CNT         0
+#define BM_DRAM_CTL29_LOWPOWER_EXTERNAL_CNT         0xffff
+#define BF_DRAM_CTL29_LOWPOWER_EXTERNAL_CNT(v)      (((v) & 0xffff) << 0)
+#define BFM_DRAM_CTL29_LOWPOWER_EXTERNAL_CNT(v)     BM_DRAM_CTL29_LOWPOWER_EXTERNAL_CNT
+#define BF_DRAM_CTL29_LOWPOWER_EXTERNAL_CNT_V(e)    BF_DRAM_CTL29_LOWPOWER_EXTERNAL_CNT(BV_DRAM_CTL29_LOWPOWER_EXTERNAL_CNT__##e)
+#define BFM_DRAM_CTL29_LOWPOWER_EXTERNAL_CNT_V(v)   BM_DRAM_CTL29_LOWPOWER_EXTERNAL_CNT
+
+#define HW_DRAM_CTL30                               HW(DRAM_CTL30)
+#define HWA_DRAM_CTL30                              (0x800e0000 + 0x78)
+#define HWT_DRAM_CTL30                              HWIO_32_RW
+#define HWN_DRAM_CTL30                              DRAM_CTL30
+#define HWI_DRAM_CTL30                              
+#define BP_DRAM_CTL30_LOWPOWER_REFRESH_HOLD         16
+#define BM_DRAM_CTL30_LOWPOWER_REFRESH_HOLD         0xffff0000
+#define BF_DRAM_CTL30_LOWPOWER_REFRESH_HOLD(v)      (((v) & 0xffff) << 16)
+#define BFM_DRAM_CTL30_LOWPOWER_REFRESH_HOLD(v)     BM_DRAM_CTL30_LOWPOWER_REFRESH_HOLD
+#define BF_DRAM_CTL30_LOWPOWER_REFRESH_HOLD_V(e)    BF_DRAM_CTL30_LOWPOWER_REFRESH_HOLD(BV_DRAM_CTL30_LOWPOWER_REFRESH_HOLD__##e)
+#define BFM_DRAM_CTL30_LOWPOWER_REFRESH_HOLD_V(v)   BM_DRAM_CTL30_LOWPOWER_REFRESH_HOLD
+#define BP_DRAM_CTL30_LOWPOWER_POWER_DOWN_CNT       0
+#define BM_DRAM_CTL30_LOWPOWER_POWER_DOWN_CNT       0xffff
+#define BF_DRAM_CTL30_LOWPOWER_POWER_DOWN_CNT(v)    (((v) & 0xffff) << 0)
+#define BFM_DRAM_CTL30_LOWPOWER_POWER_DOWN_CNT(v)   BM_DRAM_CTL30_LOWPOWER_POWER_DOWN_CNT
+#define BF_DRAM_CTL30_LOWPOWER_POWER_DOWN_CNT_V(e)  BF_DRAM_CTL30_LOWPOWER_POWER_DOWN_CNT(BV_DRAM_CTL30_LOWPOWER_POWER_DOWN_CNT__##e)
+#define BFM_DRAM_CTL30_LOWPOWER_POWER_DOWN_CNT_V(v) BM_DRAM_CTL30_LOWPOWER_POWER_DOWN_CNT
+
+#define HW_DRAM_CTL31                                   HW(DRAM_CTL31)
+#define HWA_DRAM_CTL31                                  (0x800e0000 + 0x7c)
+#define HWT_DRAM_CTL31                                  HWIO_32_RW
+#define HWN_DRAM_CTL31                                  DRAM_CTL31
+#define HWI_DRAM_CTL31                                  
+#define BP_DRAM_CTL31_TDLL                              16
+#define BM_DRAM_CTL31_TDLL                              0xffff0000
+#define BF_DRAM_CTL31_TDLL(v)                           (((v) & 0xffff) << 16)
+#define BFM_DRAM_CTL31_TDLL(v)                          BM_DRAM_CTL31_TDLL
+#define BF_DRAM_CTL31_TDLL_V(e)                         BF_DRAM_CTL31_TDLL(BV_DRAM_CTL31_TDLL__##e)
+#define BFM_DRAM_CTL31_TDLL_V(v)                        BM_DRAM_CTL31_TDLL
+#define BP_DRAM_CTL31_LOWPOWER_SELF_REFRESH_CNT         0
+#define BM_DRAM_CTL31_LOWPOWER_SELF_REFRESH_CNT         0xffff
+#define BF_DRAM_CTL31_LOWPOWER_SELF_REFRESH_CNT(v)      (((v) & 0xffff) << 0)
+#define BFM_DRAM_CTL31_LOWPOWER_SELF_REFRESH_CNT(v)     BM_DRAM_CTL31_LOWPOWER_SELF_REFRESH_CNT
+#define BF_DRAM_CTL31_LOWPOWER_SELF_REFRESH_CNT_V(e)    BF_DRAM_CTL31_LOWPOWER_SELF_REFRESH_CNT(BV_DRAM_CTL31_LOWPOWER_SELF_REFRESH_CNT__##e)
+#define BFM_DRAM_CTL31_LOWPOWER_SELF_REFRESH_CNT_V(v)   BM_DRAM_CTL31_LOWPOWER_SELF_REFRESH_CNT
+
+#define HW_DRAM_CTL32                   HW(DRAM_CTL32)
+#define HWA_DRAM_CTL32                  (0x800e0000 + 0x80)
+#define HWT_DRAM_CTL32                  HWIO_32_RW
+#define HWN_DRAM_CTL32                  DRAM_CTL32
+#define HWI_DRAM_CTL32                  
+#define BP_DRAM_CTL32_TXSNR             16
+#define BM_DRAM_CTL32_TXSNR             0xffff0000
+#define BF_DRAM_CTL32_TXSNR(v)          (((v) & 0xffff) << 16)
+#define BFM_DRAM_CTL32_TXSNR(v)         BM_DRAM_CTL32_TXSNR
+#define BF_DRAM_CTL32_TXSNR_V(e)        BF_DRAM_CTL32_TXSNR(BV_DRAM_CTL32_TXSNR__##e)
+#define BFM_DRAM_CTL32_TXSNR_V(v)       BM_DRAM_CTL32_TXSNR
+#define BP_DRAM_CTL32_TRAS_MAX          0
+#define BM_DRAM_CTL32_TRAS_MAX          0xffff
+#define BF_DRAM_CTL32_TRAS_MAX(v)       (((v) & 0xffff) << 0)
+#define BFM_DRAM_CTL32_TRAS_MAX(v)      BM_DRAM_CTL32_TRAS_MAX
+#define BF_DRAM_CTL32_TRAS_MAX_V(e)     BF_DRAM_CTL32_TRAS_MAX(BV_DRAM_CTL32_TRAS_MAX__##e)
+#define BFM_DRAM_CTL32_TRAS_MAX_V(v)    BM_DRAM_CTL32_TRAS_MAX
+
+#define HW_DRAM_CTL33               HW(DRAM_CTL33)
+#define HWA_DRAM_CTL33              (0x800e0000 + 0x84)
+#define HWT_DRAM_CTL33              HWIO_32_RW
+#define HWN_DRAM_CTL33              DRAM_CTL33
+#define HWI_DRAM_CTL33              
+#define BP_DRAM_CTL33_VERSION       16
+#define BM_DRAM_CTL33_VERSION       0xffff0000
+#define BF_DRAM_CTL33_VERSION(v)    (((v) & 0xffff) << 16)
+#define BFM_DRAM_CTL33_VERSION(v)   BM_DRAM_CTL33_VERSION
+#define BF_DRAM_CTL33_VERSION_V(e)  BF_DRAM_CTL33_VERSION(BV_DRAM_CTL33_VERSION__##e)
+#define BFM_DRAM_CTL33_VERSION_V(v) BM_DRAM_CTL33_VERSION
+#define BP_DRAM_CTL33_TXSR          0
+#define BM_DRAM_CTL33_TXSR          0xffff
+#define BF_DRAM_CTL33_TXSR(v)       (((v) & 0xffff) << 0)
+#define BFM_DRAM_CTL33_TXSR(v)      BM_DRAM_CTL33_TXSR
+#define BF_DRAM_CTL33_TXSR_V(e)     BF_DRAM_CTL33_TXSR(BV_DRAM_CTL33_TXSR__##e)
+#define BFM_DRAM_CTL33_TXSR_V(v)    BM_DRAM_CTL33_TXSR
+
+#define HW_DRAM_CTL34               HW(DRAM_CTL34)
+#define HWA_DRAM_CTL34              (0x800e0000 + 0x88)
+#define HWT_DRAM_CTL34              HWIO_32_RW
+#define HWN_DRAM_CTL34              DRAM_CTL34
+#define HWI_DRAM_CTL34              
+#define BP_DRAM_CTL34_RSVD1         24
+#define BM_DRAM_CTL34_RSVD1         0xff000000
+#define BF_DRAM_CTL34_RSVD1(v)      (((v) & 0xff) << 24)
+#define BFM_DRAM_CTL34_RSVD1(v)     BM_DRAM_CTL34_RSVD1
+#define BF_DRAM_CTL34_RSVD1_V(e)    BF_DRAM_CTL34_RSVD1(BV_DRAM_CTL34_RSVD1__##e)
+#define BFM_DRAM_CTL34_RSVD1_V(v)   BM_DRAM_CTL34_RSVD1
+#define BP_DRAM_CTL34_TINIT         0
+#define BM_DRAM_CTL34_TINIT         0xffffff
+#define BF_DRAM_CTL34_TINIT(v)      (((v) & 0xffffff) << 0)
+#define BFM_DRAM_CTL34_TINIT(v)     BM_DRAM_CTL34_TINIT
+#define BF_DRAM_CTL34_TINIT_V(e)    BF_DRAM_CTL34_TINIT(BV_DRAM_CTL34_TINIT__##e)
+#define BFM_DRAM_CTL34_TINIT_V(v)   BM_DRAM_CTL34_TINIT
+
+#define HW_DRAM_CTL35                           HW(DRAM_CTL35)
+#define HWA_DRAM_CTL35                          (0x800e0000 + 0x8c)
+#define HWT_DRAM_CTL35                          HWIO_32_RW
+#define HWN_DRAM_CTL35                          DRAM_CTL35
+#define HWI_DRAM_CTL35                          
+#define BP_DRAM_CTL35_RSVD1                     31
+#define BM_DRAM_CTL35_RSVD1                     0x80000000
+#define BF_DRAM_CTL35_RSVD1(v)                  (((v) & 0x1) << 31)
+#define BFM_DRAM_CTL35_RSVD1(v)                 BM_DRAM_CTL35_RSVD1
+#define BF_DRAM_CTL35_RSVD1_V(e)                BF_DRAM_CTL35_RSVD1(BV_DRAM_CTL35_RSVD1__##e)
+#define BFM_DRAM_CTL35_RSVD1_V(v)               BM_DRAM_CTL35_RSVD1
+#define BP_DRAM_CTL35_OUT_OF_RANGE_ADDR         0
+#define BM_DRAM_CTL35_OUT_OF_RANGE_ADDR         0x7fffffff
+#define BF_DRAM_CTL35_OUT_OF_RANGE_ADDR(v)      (((v) & 0x7fffffff) << 0)
+#define BFM_DRAM_CTL35_OUT_OF_RANGE_ADDR(v)     BM_DRAM_CTL35_OUT_OF_RANGE_ADDR
+#define BF_DRAM_CTL35_OUT_OF_RANGE_ADDR_V(e)    BF_DRAM_CTL35_OUT_OF_RANGE_ADDR(BV_DRAM_CTL35_OUT_OF_RANGE_ADDR__##e)
+#define BFM_DRAM_CTL35_OUT_OF_RANGE_ADDR_V(v)   BM_DRAM_CTL35_OUT_OF_RANGE_ADDR
+
+#define HW_DRAM_CTL36                               HW(DRAM_CTL36)
+#define HWA_DRAM_CTL36                              (0x800e0000 + 0x90)
+#define HWT_DRAM_CTL36                              HWIO_32_RW
+#define HWN_DRAM_CTL36                              DRAM_CTL36
+#define HWI_DRAM_CTL36                              
+#define BP_DRAM_CTL36_RSVD4                         25
+#define BM_DRAM_CTL36_RSVD4                         0xfe000000
+#define BF_DRAM_CTL36_RSVD4(v)                      (((v) & 0x7f) << 25)
+#define BFM_DRAM_CTL36_RSVD4(v)                     BM_DRAM_CTL36_RSVD4
+#define BF_DRAM_CTL36_RSVD4_V(e)                    BF_DRAM_CTL36_RSVD4(BV_DRAM_CTL36_RSVD4__##e)
+#define BFM_DRAM_CTL36_RSVD4_V(v)                   BM_DRAM_CTL36_RSVD4
+#define BP_DRAM_CTL36_PWRUP_SREFRESH_EXIT           24
+#define BM_DRAM_CTL36_PWRUP_SREFRESH_EXIT           0x1000000
+#define BF_DRAM_CTL36_PWRUP_SREFRESH_EXIT(v)        (((v) & 0x1) << 24)
+#define BFM_DRAM_CTL36_PWRUP_SREFRESH_EXIT(v)       BM_DRAM_CTL36_PWRUP_SREFRESH_EXIT
+#define BF_DRAM_CTL36_PWRUP_SREFRESH_EXIT_V(e)      BF_DRAM_CTL36_PWRUP_SREFRESH_EXIT(BV_DRAM_CTL36_PWRUP_SREFRESH_EXIT__##e)
+#define BFM_DRAM_CTL36_PWRUP_SREFRESH_EXIT_V(v)     BM_DRAM_CTL36_PWRUP_SREFRESH_EXIT
+#define BP_DRAM_CTL36_RSVD3                         17
+#define BM_DRAM_CTL36_RSVD3                         0xfe0000
+#define BF_DRAM_CTL36_RSVD3(v)                      (((v) & 0x7f) << 17)
+#define BFM_DRAM_CTL36_RSVD3(v)                     BM_DRAM_CTL36_RSVD3
+#define BF_DRAM_CTL36_RSVD3_V(e)                    BF_DRAM_CTL36_RSVD3(BV_DRAM_CTL36_RSVD3__##e)
+#define BFM_DRAM_CTL36_RSVD3_V(v)                   BM_DRAM_CTL36_RSVD3
+#define BP_DRAM_CTL36_ENABLE_QUICK_SREFRESH         16
+#define BM_DRAM_CTL36_ENABLE_QUICK_SREFRESH         0x10000
+#define BF_DRAM_CTL36_ENABLE_QUICK_SREFRESH(v)      (((v) & 0x1) << 16)
+#define BFM_DRAM_CTL36_ENABLE_QUICK_SREFRESH(v)     BM_DRAM_CTL36_ENABLE_QUICK_SREFRESH
+#define BF_DRAM_CTL36_ENABLE_QUICK_SREFRESH_V(e)    BF_DRAM_CTL36_ENABLE_QUICK_SREFRESH(BV_DRAM_CTL36_ENABLE_QUICK_SREFRESH__##e)
+#define BFM_DRAM_CTL36_ENABLE_QUICK_SREFRESH_V(v)   BM_DRAM_CTL36_ENABLE_QUICK_SREFRESH
+#define BP_DRAM_CTL36_RSVD2                         9
+#define BM_DRAM_CTL36_RSVD2                         0xfe00
+#define BF_DRAM_CTL36_RSVD2(v)                      (((v) & 0x7f) << 9)
+#define BFM_DRAM_CTL36_RSVD2(v)                     BM_DRAM_CTL36_RSVD2
+#define BF_DRAM_CTL36_RSVD2_V(e)                    BF_DRAM_CTL36_RSVD2(BV_DRAM_CTL36_RSVD2__##e)
+#define BFM_DRAM_CTL36_RSVD2_V(v)                   BM_DRAM_CTL36_RSVD2
+#define BP_DRAM_CTL36_BUS_SHARE_ENABLE              8
+#define BM_DRAM_CTL36_BUS_SHARE_ENABLE              0x100
+#define BF_DRAM_CTL36_BUS_SHARE_ENABLE(v)           (((v) & 0x1) << 8)
+#define BFM_DRAM_CTL36_BUS_SHARE_ENABLE(v)          BM_DRAM_CTL36_BUS_SHARE_ENABLE
+#define BF_DRAM_CTL36_BUS_SHARE_ENABLE_V(e)         BF_DRAM_CTL36_BUS_SHARE_ENABLE(BV_DRAM_CTL36_BUS_SHARE_ENABLE__##e)
+#define BFM_DRAM_CTL36_BUS_SHARE_ENABLE_V(v)        BM_DRAM_CTL36_BUS_SHARE_ENABLE
+#define BP_DRAM_CTL36_RSVD1                         1
+#define BM_DRAM_CTL36_RSVD1                         0xfe
+#define BF_DRAM_CTL36_RSVD1(v)                      (((v) & 0x7f) << 1)
+#define BFM_DRAM_CTL36_RSVD1(v)                     BM_DRAM_CTL36_RSVD1
+#define BF_DRAM_CTL36_RSVD1_V(e)                    BF_DRAM_CTL36_RSVD1(BV_DRAM_CTL36_RSVD1__##e)
+#define BFM_DRAM_CTL36_RSVD1_V(v)                   BM_DRAM_CTL36_RSVD1
+#define BP_DRAM_CTL36_ACTIVE_AGING                  0
+#define BM_DRAM_CTL36_ACTIVE_AGING                  0x1
+#define BF_DRAM_CTL36_ACTIVE_AGING(v)               (((v) & 0x1) << 0)
+#define BFM_DRAM_CTL36_ACTIVE_AGING(v)              BM_DRAM_CTL36_ACTIVE_AGING
+#define BF_DRAM_CTL36_ACTIVE_AGING_V(e)             BF_DRAM_CTL36_ACTIVE_AGING(BV_DRAM_CTL36_ACTIVE_AGING__##e)
+#define BFM_DRAM_CTL36_ACTIVE_AGING_V(v)            BM_DRAM_CTL36_ACTIVE_AGING
+
+#define HW_DRAM_CTL37                           HW(DRAM_CTL37)
+#define HWA_DRAM_CTL37                          (0x800e0000 + 0x94)
+#define HWT_DRAM_CTL37                          HWIO_32_RW
+#define HWN_DRAM_CTL37                          DRAM_CTL37
+#define HWI_DRAM_CTL37                          
+#define BP_DRAM_CTL37_OBSOLETE                  24
+#define BM_DRAM_CTL37_OBSOLETE                  0xff000000
+#define BF_DRAM_CTL37_OBSOLETE(v)               (((v) & 0xff) << 24)
+#define BFM_DRAM_CTL37_OBSOLETE(v)              BM_DRAM_CTL37_OBSOLETE
+#define BF_DRAM_CTL37_OBSOLETE_V(e)             BF_DRAM_CTL37_OBSOLETE(BV_DRAM_CTL37_OBSOLETE__##e)
+#define BFM_DRAM_CTL37_OBSOLETE_V(v)            BM_DRAM_CTL37_OBSOLETE
+#define BP_DRAM_CTL37_RSVD2                     18
+#define BM_DRAM_CTL37_RSVD2                     0xfc0000
+#define BF_DRAM_CTL37_RSVD2(v)                  (((v) & 0x3f) << 18)
+#define BFM_DRAM_CTL37_RSVD2(v)                 BM_DRAM_CTL37_RSVD2
+#define BF_DRAM_CTL37_RSVD2_V(e)                BF_DRAM_CTL37_RSVD2(BV_DRAM_CTL37_RSVD2__##e)
+#define BFM_DRAM_CTL37_RSVD2_V(v)               BM_DRAM_CTL37_RSVD2
+#define BP_DRAM_CTL37_BUS_SHARE_TIMEOUT         8
+#define BM_DRAM_CTL37_BUS_SHARE_TIMEOUT         0x3ff00
+#define BF_DRAM_CTL37_BUS_SHARE_TIMEOUT(v)      (((v) & 0x3ff) << 8)
+#define BFM_DRAM_CTL37_BUS_SHARE_TIMEOUT(v)     BM_DRAM_CTL37_BUS_SHARE_TIMEOUT
+#define BF_DRAM_CTL37_BUS_SHARE_TIMEOUT_V(e)    BF_DRAM_CTL37_BUS_SHARE_TIMEOUT(BV_DRAM_CTL37_BUS_SHARE_TIMEOUT__##e)
+#define BFM_DRAM_CTL37_BUS_SHARE_TIMEOUT_V(v)   BM_DRAM_CTL37_BUS_SHARE_TIMEOUT
+#define BP_DRAM_CTL37_RSVD1                     1
+#define BM_DRAM_CTL37_RSVD1                     0xfe
+#define BF_DRAM_CTL37_RSVD1(v)                  (((v) & 0x7f) << 1)
+#define BFM_DRAM_CTL37_RSVD1(v)                 BM_DRAM_CTL37_RSVD1
+#define BF_DRAM_CTL37_RSVD1_V(e)                BF_DRAM_CTL37_RSVD1(BV_DRAM_CTL37_RSVD1__##e)
+#define BFM_DRAM_CTL37_RSVD1_V(v)               BM_DRAM_CTL37_RSVD1
+#define BP_DRAM_CTL37_TREF_ENABLE               0
+#define BM_DRAM_CTL37_TREF_ENABLE               0x1
+#define BF_DRAM_CTL37_TREF_ENABLE(v)            (((v) & 0x1) << 0)
+#define BFM_DRAM_CTL37_TREF_ENABLE(v)           BM_DRAM_CTL37_TREF_ENABLE
+#define BF_DRAM_CTL37_TREF_ENABLE_V(e)          BF_DRAM_CTL37_TREF_ENABLE(BV_DRAM_CTL37_TREF_ENABLE__##e)
+#define BFM_DRAM_CTL37_TREF_ENABLE_V(v)         BM_DRAM_CTL37_TREF_ENABLE
+
+#define HW_DRAM_CTL38                       HW(DRAM_CTL38)
+#define HWA_DRAM_CTL38                      (0x800e0000 + 0x98)
+#define HWT_DRAM_CTL38                      HWIO_32_RW
+#define HWN_DRAM_CTL38                      DRAM_CTL38
+#define HWI_DRAM_CTL38                      
+#define BP_DRAM_CTL38_RSVD2                 29
+#define BM_DRAM_CTL38_RSVD2                 0xe0000000
+#define BF_DRAM_CTL38_RSVD2(v)              (((v) & 0x7) << 29)
+#define BFM_DRAM_CTL38_RSVD2(v)             BM_DRAM_CTL38_RSVD2
+#define BF_DRAM_CTL38_RSVD2_V(e)            BF_DRAM_CTL38_RSVD2(BV_DRAM_CTL38_RSVD2__##e)
+#define BFM_DRAM_CTL38_RSVD2_V(v)           BM_DRAM_CTL38_RSVD2
+#define BP_DRAM_CTL38_EMRS2_DATA_0          16
+#define BM_DRAM_CTL38_EMRS2_DATA_0          0x1fff0000
+#define BF_DRAM_CTL38_EMRS2_DATA_0(v)       (((v) & 0x1fff) << 16)
+#define BFM_DRAM_CTL38_EMRS2_DATA_0(v)      BM_DRAM_CTL38_EMRS2_DATA_0
+#define BF_DRAM_CTL38_EMRS2_DATA_0_V(e)     BF_DRAM_CTL38_EMRS2_DATA_0(BV_DRAM_CTL38_EMRS2_DATA_0__##e)
+#define BFM_DRAM_CTL38_EMRS2_DATA_0_V(v)    BM_DRAM_CTL38_EMRS2_DATA_0
+#define BP_DRAM_CTL38_RSVD1                 13
+#define BM_DRAM_CTL38_RSVD1                 0xe000
+#define BF_DRAM_CTL38_RSVD1(v)              (((v) & 0x7) << 13)
+#define BFM_DRAM_CTL38_RSVD1(v)             BM_DRAM_CTL38_RSVD1
+#define BF_DRAM_CTL38_RSVD1_V(e)            BF_DRAM_CTL38_RSVD1(BV_DRAM_CTL38_RSVD1__##e)
+#define BFM_DRAM_CTL38_RSVD1_V(v)           BM_DRAM_CTL38_RSVD1
+#define BP_DRAM_CTL38_EMRS1_DATA            0
+#define BM_DRAM_CTL38_EMRS1_DATA            0x1fff
+#define BF_DRAM_CTL38_EMRS1_DATA(v)         (((v) & 0x1fff) << 0)
+#define BFM_DRAM_CTL38_EMRS1_DATA(v)        BM_DRAM_CTL38_EMRS1_DATA
+#define BF_DRAM_CTL38_EMRS1_DATA_V(e)       BF_DRAM_CTL38_EMRS1_DATA(BV_DRAM_CTL38_EMRS1_DATA__##e)
+#define BFM_DRAM_CTL38_EMRS1_DATA_V(v)      BM_DRAM_CTL38_EMRS1_DATA
+
+#define HW_DRAM_CTL39                       HW(DRAM_CTL39)
+#define HWA_DRAM_CTL39                      (0x800e0000 + 0x9c)
+#define HWT_DRAM_CTL39                      HWIO_32_RW
+#define HWN_DRAM_CTL39                      DRAM_CTL39
+#define HWI_DRAM_CTL39                      
+#define BP_DRAM_CTL39_RSVD2                 29
+#define BM_DRAM_CTL39_RSVD2                 0xe0000000
+#define BF_DRAM_CTL39_RSVD2(v)              (((v) & 0x7) << 29)
+#define BFM_DRAM_CTL39_RSVD2(v)             BM_DRAM_CTL39_RSVD2
+#define BF_DRAM_CTL39_RSVD2_V(e)            BF_DRAM_CTL39_RSVD2(BV_DRAM_CTL39_RSVD2__##e)
+#define BFM_DRAM_CTL39_RSVD2_V(v)           BM_DRAM_CTL39_RSVD2
+#define BP_DRAM_CTL39_EMRS2_DATA_2          16
+#define BM_DRAM_CTL39_EMRS2_DATA_2          0x1fff0000
+#define BF_DRAM_CTL39_EMRS2_DATA_2(v)       (((v) & 0x1fff) << 16)
+#define BFM_DRAM_CTL39_EMRS2_DATA_2(v)      BM_DRAM_CTL39_EMRS2_DATA_2
+#define BF_DRAM_CTL39_EMRS2_DATA_2_V(e)     BF_DRAM_CTL39_EMRS2_DATA_2(BV_DRAM_CTL39_EMRS2_DATA_2__##e)
+#define BFM_DRAM_CTL39_EMRS2_DATA_2_V(v)    BM_DRAM_CTL39_EMRS2_DATA_2
+#define BP_DRAM_CTL39_RSVD1                 13
+#define BM_DRAM_CTL39_RSVD1                 0xe000
+#define BF_DRAM_CTL39_RSVD1(v)              (((v) & 0x7) << 13)
+#define BFM_DRAM_CTL39_RSVD1(v)             BM_DRAM_CTL39_RSVD1
+#define BF_DRAM_CTL39_RSVD1_V(e)            BF_DRAM_CTL39_RSVD1(BV_DRAM_CTL39_RSVD1__##e)
+#define BFM_DRAM_CTL39_RSVD1_V(v)           BM_DRAM_CTL39_RSVD1
+#define BP_DRAM_CTL39_EMRS2_DATA_1          0
+#define BM_DRAM_CTL39_EMRS2_DATA_1          0x1fff
+#define BF_DRAM_CTL39_EMRS2_DATA_1(v)       (((v) & 0x1fff) << 0)
+#define BFM_DRAM_CTL39_EMRS2_DATA_1(v)      BM_DRAM_CTL39_EMRS2_DATA_1
+#define BF_DRAM_CTL39_EMRS2_DATA_1_V(e)     BF_DRAM_CTL39_EMRS2_DATA_1(BV_DRAM_CTL39_EMRS2_DATA_1__##e)
+#define BFM_DRAM_CTL39_EMRS2_DATA_1_V(v)    BM_DRAM_CTL39_EMRS2_DATA_1
+
+#define HW_DRAM_CTL40                       HW(DRAM_CTL40)
+#define HWA_DRAM_CTL40                      (0x800e0000 + 0xa0)
+#define HWT_DRAM_CTL40                      HWIO_32_RW
+#define HWN_DRAM_CTL40                      DRAM_CTL40
+#define HWI_DRAM_CTL40                      
+#define BP_DRAM_CTL40_TPDEX                 16
+#define BM_DRAM_CTL40_TPDEX                 0xffff0000
+#define BF_DRAM_CTL40_TPDEX(v)              (((v) & 0xffff) << 16)
+#define BFM_DRAM_CTL40_TPDEX(v)             BM_DRAM_CTL40_TPDEX
+#define BF_DRAM_CTL40_TPDEX_V(e)            BF_DRAM_CTL40_TPDEX(BV_DRAM_CTL40_TPDEX__##e)
+#define BFM_DRAM_CTL40_TPDEX_V(v)           BM_DRAM_CTL40_TPDEX
+#define BP_DRAM_CTL40_RSVD1                 13
+#define BM_DRAM_CTL40_RSVD1                 0xe000
+#define BF_DRAM_CTL40_RSVD1(v)              (((v) & 0x7) << 13)
+#define BFM_DRAM_CTL40_RSVD1(v)             BM_DRAM_CTL40_RSVD1
+#define BF_DRAM_CTL40_RSVD1_V(e)            BF_DRAM_CTL40_RSVD1(BV_DRAM_CTL40_RSVD1__##e)
+#define BFM_DRAM_CTL40_RSVD1_V(v)           BM_DRAM_CTL40_RSVD1
+#define BP_DRAM_CTL40_EMRS2_DATA_3          0
+#define BM_DRAM_CTL40_EMRS2_DATA_3          0x1fff
+#define BF_DRAM_CTL40_EMRS2_DATA_3(v)       (((v) & 0x1fff) << 0)
+#define BFM_DRAM_CTL40_EMRS2_DATA_3(v)      BM_DRAM_CTL40_EMRS2_DATA_3
+#define BF_DRAM_CTL40_EMRS2_DATA_3_V(e)     BF_DRAM_CTL40_EMRS2_DATA_3(BV_DRAM_CTL40_EMRS2_DATA_3__##e)
+#define BFM_DRAM_CTL40_EMRS2_DATA_3_V(v)    BM_DRAM_CTL40_EMRS2_DATA_3
+
+#endif /* __HEADERGEN_IMX233_DRAM_H__*/
diff --git a/firmware/target/arm/imx233/regs/imx233/dri.h b/firmware/target/arm/imx233/regs/imx233/dri.h
new file mode 100644
index 0000000000..a63c75950a
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/imx233/dri.h
@@ -0,0 +1,454 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * imx233 version: 2.4.0
+ * imx233 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_IMX233_DRI_H__
+#define __HEADERGEN_IMX233_DRI_H__
+
+#define HW_DRI_CTRL                                     HW(DRI_CTRL)
+#define HWA_DRI_CTRL                                    (0x80074000 + 0x0)
+#define HWT_DRI_CTRL                                    HWIO_32_RW
+#define HWN_DRI_CTRL                                    DRI_CTRL
+#define HWI_DRI_CTRL                                    
+#define HW_DRI_CTRL_SET                                 HW(DRI_CTRL_SET)
+#define HWA_DRI_CTRL_SET                                (HWA_DRI_CTRL + 0x4)
+#define HWT_DRI_CTRL_SET                                HWIO_32_WO
+#define HWN_DRI_CTRL_SET                                DRI_CTRL
+#define HWI_DRI_CTRL_SET                                
+#define HW_DRI_CTRL_CLR                                 HW(DRI_CTRL_CLR)
+#define HWA_DRI_CTRL_CLR                                (HWA_DRI_CTRL + 0x8)
+#define HWT_DRI_CTRL_CLR                                HWIO_32_WO
+#define HWN_DRI_CTRL_CLR                                DRI_CTRL
+#define HWI_DRI_CTRL_CLR                                
+#define HW_DRI_CTRL_TOG                                 HW(DRI_CTRL_TOG)
+#define HWA_DRI_CTRL_TOG                                (HWA_DRI_CTRL + 0xc)
+#define HWT_DRI_CTRL_TOG                                HWIO_32_WO
+#define HWN_DRI_CTRL_TOG                                DRI_CTRL
+#define HWI_DRI_CTRL_TOG                                
+#define BP_DRI_CTRL_SFTRST                              31
+#define BM_DRI_CTRL_SFTRST                              0x80000000
+#define BV_DRI_CTRL_SFTRST__RUN                         0x0
+#define BV_DRI_CTRL_SFTRST__RESET                       0x1
+#define BF_DRI_CTRL_SFTRST(v)                           (((v) & 0x1) << 31)
+#define BFM_DRI_CTRL_SFTRST(v)                          BM_DRI_CTRL_SFTRST
+#define BF_DRI_CTRL_SFTRST_V(e)                         BF_DRI_CTRL_SFTRST(BV_DRI_CTRL_SFTRST__##e)
+#define BFM_DRI_CTRL_SFTRST_V(v)                        BM_DRI_CTRL_SFTRST
+#define BP_DRI_CTRL_CLKGATE                             30
+#define BM_DRI_CTRL_CLKGATE                             0x40000000
+#define BV_DRI_CTRL_CLKGATE__RUN                        0x0
+#define BV_DRI_CTRL_CLKGATE__NO_CLKS                    0x1
+#define BF_DRI_CTRL_CLKGATE(v)                          (((v) & 0x1) << 30)
+#define BFM_DRI_CTRL_CLKGATE(v)                         BM_DRI_CTRL_CLKGATE
+#define BF_DRI_CTRL_CLKGATE_V(e)                        BF_DRI_CTRL_CLKGATE(BV_DRI_CTRL_CLKGATE__##e)
+#define BFM_DRI_CTRL_CLKGATE_V(v)                       BM_DRI_CTRL_CLKGATE
+#define BP_DRI_CTRL_ENABLE_INPUTS                       29
+#define BM_DRI_CTRL_ENABLE_INPUTS                       0x20000000
+#define BV_DRI_CTRL_ENABLE_INPUTS__ANALOG_LINE_IN       0x0
+#define BV_DRI_CTRL_ENABLE_INPUTS__DRI_DIGITAL_IN       0x1
+#define BF_DRI_CTRL_ENABLE_INPUTS(v)                    (((v) & 0x1) << 29)
+#define BFM_DRI_CTRL_ENABLE_INPUTS(v)                   BM_DRI_CTRL_ENABLE_INPUTS
+#define BF_DRI_CTRL_ENABLE_INPUTS_V(e)                  BF_DRI_CTRL_ENABLE_INPUTS(BV_DRI_CTRL_ENABLE_INPUTS__##e)
+#define BFM_DRI_CTRL_ENABLE_INPUTS_V(v)                 BM_DRI_CTRL_ENABLE_INPUTS
+#define BP_DRI_CTRL_RSVD4                               27
+#define BM_DRI_CTRL_RSVD4                               0x18000000
+#define BF_DRI_CTRL_RSVD4(v)                            (((v) & 0x3) << 27)
+#define BFM_DRI_CTRL_RSVD4(v)                           BM_DRI_CTRL_RSVD4
+#define BF_DRI_CTRL_RSVD4_V(e)                          BF_DRI_CTRL_RSVD4(BV_DRI_CTRL_RSVD4__##e)
+#define BFM_DRI_CTRL_RSVD4_V(v)                         BM_DRI_CTRL_RSVD4
+#define BP_DRI_CTRL_STOP_ON_OFLOW_ERROR                 26
+#define BM_DRI_CTRL_STOP_ON_OFLOW_ERROR                 0x4000000
+#define BV_DRI_CTRL_STOP_ON_OFLOW_ERROR__IGNORE         0x0
+#define BV_DRI_CTRL_STOP_ON_OFLOW_ERROR__STOP           0x1
+#define BF_DRI_CTRL_STOP_ON_OFLOW_ERROR(v)              (((v) & 0x1) << 26)
+#define BFM_DRI_CTRL_STOP_ON_OFLOW_ERROR(v)             BM_DRI_CTRL_STOP_ON_OFLOW_ERROR
+#define BF_DRI_CTRL_STOP_ON_OFLOW_ERROR_V(e)            BF_DRI_CTRL_STOP_ON_OFLOW_ERROR(BV_DRI_CTRL_STOP_ON_OFLOW_ERROR__##e)
+#define BFM_DRI_CTRL_STOP_ON_OFLOW_ERROR_V(v)           BM_DRI_CTRL_STOP_ON_OFLOW_ERROR
+#define BP_DRI_CTRL_STOP_ON_PILOT_ERROR                 25
+#define BM_DRI_CTRL_STOP_ON_PILOT_ERROR                 0x2000000
+#define BV_DRI_CTRL_STOP_ON_PILOT_ERROR__IGNORE         0x0
+#define BV_DRI_CTRL_STOP_ON_PILOT_ERROR__STOP           0x1
+#define BF_DRI_CTRL_STOP_ON_PILOT_ERROR(v)              (((v) & 0x1) << 25)
+#define BFM_DRI_CTRL_STOP_ON_PILOT_ERROR(v)             BM_DRI_CTRL_STOP_ON_PILOT_ERROR
+#define BF_DRI_CTRL_STOP_ON_PILOT_ERROR_V(e)            BF_DRI_CTRL_STOP_ON_PILOT_ERROR(BV_DRI_CTRL_STOP_ON_PILOT_ERROR__##e)
+#define BFM_DRI_CTRL_STOP_ON_PILOT_ERROR_V(v)           BM_DRI_CTRL_STOP_ON_PILOT_ERROR
+#define BP_DRI_CTRL_RSVD3                               21
+#define BM_DRI_CTRL_RSVD3                               0x1e00000
+#define BF_DRI_CTRL_RSVD3(v)                            (((v) & 0xf) << 21)
+#define BFM_DRI_CTRL_RSVD3(v)                           BM_DRI_CTRL_RSVD3
+#define BF_DRI_CTRL_RSVD3_V(e)                          BF_DRI_CTRL_RSVD3(BV_DRI_CTRL_RSVD3__##e)
+#define BFM_DRI_CTRL_RSVD3_V(v)                         BM_DRI_CTRL_RSVD3
+#define BP_DRI_CTRL_DMA_DELAY_COUNT                     16
+#define BM_DRI_CTRL_DMA_DELAY_COUNT                     0x1f0000
+#define BF_DRI_CTRL_DMA_DELAY_COUNT(v)                  (((v) & 0x1f) << 16)
+#define BFM_DRI_CTRL_DMA_DELAY_COUNT(v)                 BM_DRI_CTRL_DMA_DELAY_COUNT
+#define BF_DRI_CTRL_DMA_DELAY_COUNT_V(e)                BF_DRI_CTRL_DMA_DELAY_COUNT(BV_DRI_CTRL_DMA_DELAY_COUNT__##e)
+#define BFM_DRI_CTRL_DMA_DELAY_COUNT_V(v)               BM_DRI_CTRL_DMA_DELAY_COUNT
+#define BP_DRI_CTRL_REACQUIRE_PHASE                     15
+#define BM_DRI_CTRL_REACQUIRE_PHASE                     0x8000
+#define BV_DRI_CTRL_REACQUIRE_PHASE__NORMAL             0x0
+#define BV_DRI_CTRL_REACQUIRE_PHASE__NEW_PHASE          0x1
+#define BF_DRI_CTRL_REACQUIRE_PHASE(v)                  (((v) & 0x1) << 15)
+#define BFM_DRI_CTRL_REACQUIRE_PHASE(v)                 BM_DRI_CTRL_REACQUIRE_PHASE
+#define BF_DRI_CTRL_REACQUIRE_PHASE_V(e)                BF_DRI_CTRL_REACQUIRE_PHASE(BV_DRI_CTRL_REACQUIRE_PHASE__##e)
+#define BFM_DRI_CTRL_REACQUIRE_PHASE_V(v)               BM_DRI_CTRL_REACQUIRE_PHASE
+#define BP_DRI_CTRL_RSVD2                               12
+#define BM_DRI_CTRL_RSVD2                               0x7000
+#define BF_DRI_CTRL_RSVD2(v)                            (((v) & 0x7) << 12)
+#define BFM_DRI_CTRL_RSVD2(v)                           BM_DRI_CTRL_RSVD2
+#define BF_DRI_CTRL_RSVD2_V(e)                          BF_DRI_CTRL_RSVD2(BV_DRI_CTRL_RSVD2__##e)
+#define BFM_DRI_CTRL_RSVD2_V(v)                         BM_DRI_CTRL_RSVD2
+#define BP_DRI_CTRL_OVERFLOW_IRQ_EN                     11
+#define BM_DRI_CTRL_OVERFLOW_IRQ_EN                     0x800
+#define BV_DRI_CTRL_OVERFLOW_IRQ_EN__DISABLED           0x0
+#define BV_DRI_CTRL_OVERFLOW_IRQ_EN__ENABLED            0x1
+#define BF_DRI_CTRL_OVERFLOW_IRQ_EN(v)                  (((v) & 0x1) << 11)
+#define BFM_DRI_CTRL_OVERFLOW_IRQ_EN(v)                 BM_DRI_CTRL_OVERFLOW_IRQ_EN
+#define BF_DRI_CTRL_OVERFLOW_IRQ_EN_V(e)                BF_DRI_CTRL_OVERFLOW_IRQ_EN(BV_DRI_CTRL_OVERFLOW_IRQ_EN__##e)
+#define BFM_DRI_CTRL_OVERFLOW_IRQ_EN_V(v)               BM_DRI_CTRL_OVERFLOW_IRQ_EN
+#define BP_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN              10
+#define BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN              0x400
+#define BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN__DISABLED    0x0
+#define BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN__ENABLED     0x1
+#define BF_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN(v)           (((v) & 0x1) << 10)
+#define BFM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN(v)          BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN
+#define BF_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN_V(e)         BF_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN(BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN__##e)
+#define BFM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN_V(v)        BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN
+#define BP_DRI_CTRL_ATTENTION_IRQ_EN                    9
+#define BM_DRI_CTRL_ATTENTION_IRQ_EN                    0x200
+#define BV_DRI_CTRL_ATTENTION_IRQ_EN__DISABLED          0x0
+#define BV_DRI_CTRL_ATTENTION_IRQ_EN__ENABLED           0x1
+#define BF_DRI_CTRL_ATTENTION_IRQ_EN(v)                 (((v) & 0x1) << 9)
+#define BFM_DRI_CTRL_ATTENTION_IRQ_EN(v)                BM_DRI_CTRL_ATTENTION_IRQ_EN
+#define BF_DRI_CTRL_ATTENTION_IRQ_EN_V(e)               BF_DRI_CTRL_ATTENTION_IRQ_EN(BV_DRI_CTRL_ATTENTION_IRQ_EN__##e)
+#define BFM_DRI_CTRL_ATTENTION_IRQ_EN_V(v)              BM_DRI_CTRL_ATTENTION_IRQ_EN
+#define BP_DRI_CTRL_RSVD1                               4
+#define BM_DRI_CTRL_RSVD1                               0x1f0
+#define BF_DRI_CTRL_RSVD1(v)                            (((v) & 0x1f) << 4)
+#define BFM_DRI_CTRL_RSVD1(v)                           BM_DRI_CTRL_RSVD1
+#define BF_DRI_CTRL_RSVD1_V(e)                          BF_DRI_CTRL_RSVD1(BV_DRI_CTRL_RSVD1__##e)
+#define BFM_DRI_CTRL_RSVD1_V(v)                         BM_DRI_CTRL_RSVD1
+#define BP_DRI_CTRL_OVERFLOW_IRQ                        3
+#define BM_DRI_CTRL_OVERFLOW_IRQ                        0x8
+#define BV_DRI_CTRL_OVERFLOW_IRQ__NO_REQUEST            0x0
+#define BV_DRI_CTRL_OVERFLOW_IRQ__REQUEST               0x1
+#define BF_DRI_CTRL_OVERFLOW_IRQ(v)                     (((v) & 0x1) << 3)
+#define BFM_DRI_CTRL_OVERFLOW_IRQ(v)                    BM_DRI_CTRL_OVERFLOW_IRQ
+#define BF_DRI_CTRL_OVERFLOW_IRQ_V(e)                   BF_DRI_CTRL_OVERFLOW_IRQ(BV_DRI_CTRL_OVERFLOW_IRQ__##e)
+#define BFM_DRI_CTRL_OVERFLOW_IRQ_V(v)                  BM_DRI_CTRL_OVERFLOW_IRQ
+#define BP_DRI_CTRL_PILOT_SYNC_LOSS_IRQ                 2
+#define BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ                 0x4
+#define BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ__NO_REQUEST     0x0
+#define BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ__REQUEST        0x1
+#define BF_DRI_CTRL_PILOT_SYNC_LOSS_IRQ(v)              (((v) & 0x1) << 2)
+#define BFM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ(v)             BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ
+#define BF_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_V(e)            BF_DRI_CTRL_PILOT_SYNC_LOSS_IRQ(BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ__##e)
+#define BFM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_V(v)           BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ
+#define BP_DRI_CTRL_ATTENTION_IRQ                       1
+#define BM_DRI_CTRL_ATTENTION_IRQ                       0x2
+#define BV_DRI_CTRL_ATTENTION_IRQ__NO_REQUEST           0x0
+#define BV_DRI_CTRL_ATTENTION_IRQ__REQUEST              0x1
+#define BF_DRI_CTRL_ATTENTION_IRQ(v)                    (((v) & 0x1) << 1)
+#define BFM_DRI_CTRL_ATTENTION_IRQ(v)                   BM_DRI_CTRL_ATTENTION_IRQ
+#define BF_DRI_CTRL_ATTENTION_IRQ_V(e)                  BF_DRI_CTRL_ATTENTION_IRQ(BV_DRI_CTRL_ATTENTION_IRQ__##e)
+#define BFM_DRI_CTRL_ATTENTION_IRQ_V(v)                 BM_DRI_CTRL_ATTENTION_IRQ
+#define BP_DRI_CTRL_RUN                                 0
+#define BM_DRI_CTRL_RUN                                 0x1
+#define BV_DRI_CTRL_RUN__HALT                           0x0
+#define BV_DRI_CTRL_RUN__RUN                            0x1
+#define BF_DRI_CTRL_RUN(v)                              (((v) & 0x1) << 0)
+#define BFM_DRI_CTRL_RUN(v)                             BM_DRI_CTRL_RUN
+#define BF_DRI_CTRL_RUN_V(e)                            BF_DRI_CTRL_RUN(BV_DRI_CTRL_RUN__##e)
+#define BFM_DRI_CTRL_RUN_V(v)                           BM_DRI_CTRL_RUN
+
+#define HW_DRI_TIMING                               HW(DRI_TIMING)
+#define HWA_DRI_TIMING                              (0x80074000 + 0x10)
+#define HWT_DRI_TIMING                              HWIO_32_RW
+#define HWN_DRI_TIMING                              DRI_TIMING
+#define HWI_DRI_TIMING                              
+#define BP_DRI_TIMING_RSVD2                         20
+#define BM_DRI_TIMING_RSVD2                         0xfff00000
+#define BF_DRI_TIMING_RSVD2(v)                      (((v) & 0xfff) << 20)
+#define BFM_DRI_TIMING_RSVD2(v)                     BM_DRI_TIMING_RSVD2
+#define BF_DRI_TIMING_RSVD2_V(e)                    BF_DRI_TIMING_RSVD2(BV_DRI_TIMING_RSVD2__##e)
+#define BFM_DRI_TIMING_RSVD2_V(v)                   BM_DRI_TIMING_RSVD2
+#define BP_DRI_TIMING_PILOT_REP_RATE                16
+#define BM_DRI_TIMING_PILOT_REP_RATE                0xf0000
+#define BF_DRI_TIMING_PILOT_REP_RATE(v)             (((v) & 0xf) << 16)
+#define BFM_DRI_TIMING_PILOT_REP_RATE(v)            BM_DRI_TIMING_PILOT_REP_RATE
+#define BF_DRI_TIMING_PILOT_REP_RATE_V(e)           BF_DRI_TIMING_PILOT_REP_RATE(BV_DRI_TIMING_PILOT_REP_RATE__##e)
+#define BFM_DRI_TIMING_PILOT_REP_RATE_V(v)          BM_DRI_TIMING_PILOT_REP_RATE
+#define BP_DRI_TIMING_RSVD1                         8
+#define BM_DRI_TIMING_RSVD1                         0xff00
+#define BF_DRI_TIMING_RSVD1(v)                      (((v) & 0xff) << 8)
+#define BFM_DRI_TIMING_RSVD1(v)                     BM_DRI_TIMING_RSVD1
+#define BF_DRI_TIMING_RSVD1_V(e)                    BF_DRI_TIMING_RSVD1(BV_DRI_TIMING_RSVD1__##e)
+#define BFM_DRI_TIMING_RSVD1_V(v)                   BM_DRI_TIMING_RSVD1
+#define BP_DRI_TIMING_GAP_DETECTION_INTERVAL        0
+#define BM_DRI_TIMING_GAP_DETECTION_INTERVAL        0xff
+#define BF_DRI_TIMING_GAP_DETECTION_INTERVAL(v)     (((v) & 0xff) << 0)
+#define BFM_DRI_TIMING_GAP_DETECTION_INTERVAL(v)    BM_DRI_TIMING_GAP_DETECTION_INTERVAL
+#define BF_DRI_TIMING_GAP_DETECTION_INTERVAL_V(e)   BF_DRI_TIMING_GAP_DETECTION_INTERVAL(BV_DRI_TIMING_GAP_DETECTION_INTERVAL__##e)
+#define BFM_DRI_TIMING_GAP_DETECTION_INTERVAL_V(v)  BM_DRI_TIMING_GAP_DETECTION_INTERVAL
+
+#define HW_DRI_STAT                                         HW(DRI_STAT)
+#define HWA_DRI_STAT                                        (0x80074000 + 0x20)
+#define HWT_DRI_STAT                                        HWIO_32_RW
+#define HWN_DRI_STAT                                        DRI_STAT
+#define HWI_DRI_STAT                                        
+#define BP_DRI_STAT_DRI_PRESENT                             31
+#define BM_DRI_STAT_DRI_PRESENT                             0x80000000
+#define BV_DRI_STAT_DRI_PRESENT__UNAVAILABLE                0x0
+#define BV_DRI_STAT_DRI_PRESENT__AVAILABLE                  0x1
+#define BF_DRI_STAT_DRI_PRESENT(v)                          (((v) & 0x1) << 31)
+#define BFM_DRI_STAT_DRI_PRESENT(v)                         BM_DRI_STAT_DRI_PRESENT
+#define BF_DRI_STAT_DRI_PRESENT_V(e)                        BF_DRI_STAT_DRI_PRESENT(BV_DRI_STAT_DRI_PRESENT__##e)
+#define BFM_DRI_STAT_DRI_PRESENT_V(v)                       BM_DRI_STAT_DRI_PRESENT
+#define BP_DRI_STAT_RSVD3                                   20
+#define BM_DRI_STAT_RSVD3                                   0x7ff00000
+#define BF_DRI_STAT_RSVD3(v)                                (((v) & 0x7ff) << 20)
+#define BFM_DRI_STAT_RSVD3(v)                               BM_DRI_STAT_RSVD3
+#define BF_DRI_STAT_RSVD3_V(e)                              BF_DRI_STAT_RSVD3(BV_DRI_STAT_RSVD3__##e)
+#define BFM_DRI_STAT_RSVD3_V(v)                             BM_DRI_STAT_RSVD3
+#define BP_DRI_STAT_PILOT_PHASE                             16
+#define BM_DRI_STAT_PILOT_PHASE                             0xf0000
+#define BF_DRI_STAT_PILOT_PHASE(v)                          (((v) & 0xf) << 16)
+#define BFM_DRI_STAT_PILOT_PHASE(v)                         BM_DRI_STAT_PILOT_PHASE
+#define BF_DRI_STAT_PILOT_PHASE_V(e)                        BF_DRI_STAT_PILOT_PHASE(BV_DRI_STAT_PILOT_PHASE__##e)
+#define BFM_DRI_STAT_PILOT_PHASE_V(v)                       BM_DRI_STAT_PILOT_PHASE
+#define BP_DRI_STAT_RSVD2                                   4
+#define BM_DRI_STAT_RSVD2                                   0xfff0
+#define BF_DRI_STAT_RSVD2(v)                                (((v) & 0xfff) << 4)
+#define BFM_DRI_STAT_RSVD2(v)                               BM_DRI_STAT_RSVD2
+#define BF_DRI_STAT_RSVD2_V(e)                              BF_DRI_STAT_RSVD2(BV_DRI_STAT_RSVD2__##e)
+#define BFM_DRI_STAT_RSVD2_V(v)                             BM_DRI_STAT_RSVD2
+#define BP_DRI_STAT_OVERFLOW_IRQ_SUMMARY                    3
+#define BM_DRI_STAT_OVERFLOW_IRQ_SUMMARY                    0x8
+#define BV_DRI_STAT_OVERFLOW_IRQ_SUMMARY__NO_REQUEST        0x0
+#define BV_DRI_STAT_OVERFLOW_IRQ_SUMMARY__REQUEST           0x1
+#define BF_DRI_STAT_OVERFLOW_IRQ_SUMMARY(v)                 (((v) & 0x1) << 3)
+#define BFM_DRI_STAT_OVERFLOW_IRQ_SUMMARY(v)                BM_DRI_STAT_OVERFLOW_IRQ_SUMMARY
+#define BF_DRI_STAT_OVERFLOW_IRQ_SUMMARY_V(e)               BF_DRI_STAT_OVERFLOW_IRQ_SUMMARY(BV_DRI_STAT_OVERFLOW_IRQ_SUMMARY__##e)
+#define BFM_DRI_STAT_OVERFLOW_IRQ_SUMMARY_V(v)              BM_DRI_STAT_OVERFLOW_IRQ_SUMMARY
+#define BP_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY             2
+#define BM_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY             0x4
+#define BV_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY__NO_REQUEST 0x0
+#define BV_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY__REQUEST    0x1
+#define BF_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY(v)          (((v) & 0x1) << 2)
+#define BFM_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY(v)         BM_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY
+#define BF_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY_V(e)        BF_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY(BV_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY__##e)
+#define BFM_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY_V(v)       BM_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY
+#define BP_DRI_STAT_ATTENTION_IRQ_SUMMARY                   1
+#define BM_DRI_STAT_ATTENTION_IRQ_SUMMARY                   0x2
+#define BV_DRI_STAT_ATTENTION_IRQ_SUMMARY__NO_REQUEST       0x0
+#define BV_DRI_STAT_ATTENTION_IRQ_SUMMARY__REQUEST          0x1
+#define BF_DRI_STAT_ATTENTION_IRQ_SUMMARY(v)                (((v) & 0x1) << 1)
+#define BFM_DRI_STAT_ATTENTION_IRQ_SUMMARY(v)               BM_DRI_STAT_ATTENTION_IRQ_SUMMARY
+#define BF_DRI_STAT_ATTENTION_IRQ_SUMMARY_V(e)              BF_DRI_STAT_ATTENTION_IRQ_SUMMARY(BV_DRI_STAT_ATTENTION_IRQ_SUMMARY__##e)
+#define BFM_DRI_STAT_ATTENTION_IRQ_SUMMARY_V(v)             BM_DRI_STAT_ATTENTION_IRQ_SUMMARY
+#define BP_DRI_STAT_RSVD1                                   0
+#define BM_DRI_STAT_RSVD1                                   0x1
+#define BF_DRI_STAT_RSVD1(v)                                (((v) & 0x1) << 0)
+#define BFM_DRI_STAT_RSVD1(v)                               BM_DRI_STAT_RSVD1
+#define BF_DRI_STAT_RSVD1_V(e)                              BF_DRI_STAT_RSVD1(BV_DRI_STAT_RSVD1__##e)
+#define BFM_DRI_STAT_RSVD1_V(v)                             BM_DRI_STAT_RSVD1
+
+#define HW_DRI_DATA             HW(DRI_DATA)
+#define HWA_DRI_DATA            (0x80074000 + 0x30)
+#define HWT_DRI_DATA            HWIO_32_RW
+#define HWN_DRI_DATA            DRI_DATA
+#define HWI_DRI_DATA            
+#define BP_DRI_DATA_DATA        0
+#define BM_DRI_DATA_DATA        0xffffffff
+#define BF_DRI_DATA_DATA(v)     (((v) & 0xffffffff) << 0)
+#define BFM_DRI_DATA_DATA(v)    BM_DRI_DATA_DATA
+#define BF_DRI_DATA_DATA_V(e)   BF_DRI_DATA_DATA(BV_DRI_DATA_DATA__##e)
+#define BFM_DRI_DATA_DATA_V(v)  BM_DRI_DATA_DATA
+
+#define HW_DRI_DEBUG0                               HW(DRI_DEBUG0)
+#define HWA_DRI_DEBUG0                              (0x80074000 + 0x40)
+#define HWT_DRI_DEBUG0                              HWIO_32_RW
+#define HWN_DRI_DEBUG0                              DRI_DEBUG0
+#define HWI_DRI_DEBUG0                              
+#define HW_DRI_DEBUG0_SET                           HW(DRI_DEBUG0_SET)
+#define HWA_DRI_DEBUG0_SET                          (HWA_DRI_DEBUG0 + 0x4)
+#define HWT_DRI_DEBUG0_SET                          HWIO_32_WO
+#define HWN_DRI_DEBUG0_SET                          DRI_DEBUG0
+#define HWI_DRI_DEBUG0_SET                          
+#define HW_DRI_DEBUG0_CLR                           HW(DRI_DEBUG0_CLR)
+#define HWA_DRI_DEBUG0_CLR                          (HWA_DRI_DEBUG0 + 0x8)
+#define HWT_DRI_DEBUG0_CLR                          HWIO_32_WO
+#define HWN_DRI_DEBUG0_CLR                          DRI_DEBUG0
+#define HWI_DRI_DEBUG0_CLR                          
+#define HW_DRI_DEBUG0_TOG                           HW(DRI_DEBUG0_TOG)
+#define HWA_DRI_DEBUG0_TOG                          (HWA_DRI_DEBUG0 + 0xc)
+#define HWT_DRI_DEBUG0_TOG                          HWIO_32_WO
+#define HWN_DRI_DEBUG0_TOG                          DRI_DEBUG0
+#define HWI_DRI_DEBUG0_TOG                          
+#define BP_DRI_DEBUG0_DMAREQ                        31
+#define BM_DRI_DEBUG0_DMAREQ                        0x80000000
+#define BF_DRI_DEBUG0_DMAREQ(v)                     (((v) & 0x1) << 31)
+#define BFM_DRI_DEBUG0_DMAREQ(v)                    BM_DRI_DEBUG0_DMAREQ
+#define BF_DRI_DEBUG0_DMAREQ_V(e)                   BF_DRI_DEBUG0_DMAREQ(BV_DRI_DEBUG0_DMAREQ__##e)
+#define BFM_DRI_DEBUG0_DMAREQ_V(v)                  BM_DRI_DEBUG0_DMAREQ
+#define BP_DRI_DEBUG0_DMACMDKICK                    30
+#define BM_DRI_DEBUG0_DMACMDKICK                    0x40000000
+#define BF_DRI_DEBUG0_DMACMDKICK(v)                 (((v) & 0x1) << 30)
+#define BFM_DRI_DEBUG0_DMACMDKICK(v)                BM_DRI_DEBUG0_DMACMDKICK
+#define BF_DRI_DEBUG0_DMACMDKICK_V(e)               BF_DRI_DEBUG0_DMACMDKICK(BV_DRI_DEBUG0_DMACMDKICK__##e)
+#define BFM_DRI_DEBUG0_DMACMDKICK_V(v)              BM_DRI_DEBUG0_DMACMDKICK
+#define BP_DRI_DEBUG0_DRI_CLK_INPUT                 29
+#define BM_DRI_DEBUG0_DRI_CLK_INPUT                 0x20000000
+#define BF_DRI_DEBUG0_DRI_CLK_INPUT(v)              (((v) & 0x1) << 29)
+#define BFM_DRI_DEBUG0_DRI_CLK_INPUT(v)             BM_DRI_DEBUG0_DRI_CLK_INPUT
+#define BF_DRI_DEBUG0_DRI_CLK_INPUT_V(e)            BF_DRI_DEBUG0_DRI_CLK_INPUT(BV_DRI_DEBUG0_DRI_CLK_INPUT__##e)
+#define BFM_DRI_DEBUG0_DRI_CLK_INPUT_V(v)           BM_DRI_DEBUG0_DRI_CLK_INPUT
+#define BP_DRI_DEBUG0_DRI_DATA_INPUT                28
+#define BM_DRI_DEBUG0_DRI_DATA_INPUT                0x10000000
+#define BF_DRI_DEBUG0_DRI_DATA_INPUT(v)             (((v) & 0x1) << 28)
+#define BFM_DRI_DEBUG0_DRI_DATA_INPUT(v)            BM_DRI_DEBUG0_DRI_DATA_INPUT
+#define BF_DRI_DEBUG0_DRI_DATA_INPUT_V(e)           BF_DRI_DEBUG0_DRI_DATA_INPUT(BV_DRI_DEBUG0_DRI_DATA_INPUT__##e)
+#define BFM_DRI_DEBUG0_DRI_DATA_INPUT_V(v)          BM_DRI_DEBUG0_DRI_DATA_INPUT
+#define BP_DRI_DEBUG0_TEST_MODE                     27
+#define BM_DRI_DEBUG0_TEST_MODE                     0x8000000
+#define BF_DRI_DEBUG0_TEST_MODE(v)                  (((v) & 0x1) << 27)
+#define BFM_DRI_DEBUG0_TEST_MODE(v)                 BM_DRI_DEBUG0_TEST_MODE
+#define BF_DRI_DEBUG0_TEST_MODE_V(e)                BF_DRI_DEBUG0_TEST_MODE(BV_DRI_DEBUG0_TEST_MODE__##e)
+#define BFM_DRI_DEBUG0_TEST_MODE_V(v)               BM_DRI_DEBUG0_TEST_MODE
+#define BP_DRI_DEBUG0_PILOT_REP_RATE                26
+#define BM_DRI_DEBUG0_PILOT_REP_RATE                0x4000000
+#define BV_DRI_DEBUG0_PILOT_REP_RATE__8_AT_4MHZ     0x0
+#define BV_DRI_DEBUG0_PILOT_REP_RATE__12_AT_6MHZ    0x1
+#define BF_DRI_DEBUG0_PILOT_REP_RATE(v)             (((v) & 0x1) << 26)
+#define BFM_DRI_DEBUG0_PILOT_REP_RATE(v)            BM_DRI_DEBUG0_PILOT_REP_RATE
+#define BF_DRI_DEBUG0_PILOT_REP_RATE_V(e)           BF_DRI_DEBUG0_PILOT_REP_RATE(BV_DRI_DEBUG0_PILOT_REP_RATE__##e)
+#define BFM_DRI_DEBUG0_PILOT_REP_RATE_V(v)          BM_DRI_DEBUG0_PILOT_REP_RATE
+#define BP_DRI_DEBUG0_SPARE                         18
+#define BM_DRI_DEBUG0_SPARE                         0x3fc0000
+#define BF_DRI_DEBUG0_SPARE(v)                      (((v) & 0xff) << 18)
+#define BFM_DRI_DEBUG0_SPARE(v)                     BM_DRI_DEBUG0_SPARE
+#define BF_DRI_DEBUG0_SPARE_V(e)                    BF_DRI_DEBUG0_SPARE(BV_DRI_DEBUG0_SPARE__##e)
+#define BFM_DRI_DEBUG0_SPARE_V(v)                   BM_DRI_DEBUG0_SPARE
+#define BP_DRI_DEBUG0_FRAME                         0
+#define BM_DRI_DEBUG0_FRAME                         0x3ffff
+#define BF_DRI_DEBUG0_FRAME(v)                      (((v) & 0x3ffff) << 0)
+#define BFM_DRI_DEBUG0_FRAME(v)                     BM_DRI_DEBUG0_FRAME
+#define BF_DRI_DEBUG0_FRAME_V(e)                    BF_DRI_DEBUG0_FRAME(BV_DRI_DEBUG0_FRAME__##e)
+#define BFM_DRI_DEBUG0_FRAME_V(v)                   BM_DRI_DEBUG0_FRAME
+
+#define HW_DRI_DEBUG1                               HW(DRI_DEBUG1)
+#define HWA_DRI_DEBUG1                              (0x80074000 + 0x50)
+#define HWT_DRI_DEBUG1                              HWIO_32_RW
+#define HWN_DRI_DEBUG1                              DRI_DEBUG1
+#define HWI_DRI_DEBUG1                              
+#define HW_DRI_DEBUG1_SET                           HW(DRI_DEBUG1_SET)
+#define HWA_DRI_DEBUG1_SET                          (HWA_DRI_DEBUG1 + 0x4)
+#define HWT_DRI_DEBUG1_SET                          HWIO_32_WO
+#define HWN_DRI_DEBUG1_SET                          DRI_DEBUG1
+#define HWI_DRI_DEBUG1_SET                          
+#define HW_DRI_DEBUG1_CLR                           HW(DRI_DEBUG1_CLR)
+#define HWA_DRI_DEBUG1_CLR                          (HWA_DRI_DEBUG1 + 0x8)
+#define HWT_DRI_DEBUG1_CLR                          HWIO_32_WO
+#define HWN_DRI_DEBUG1_CLR                          DRI_DEBUG1
+#define HWI_DRI_DEBUG1_CLR                          
+#define HW_DRI_DEBUG1_TOG                           HW(DRI_DEBUG1_TOG)
+#define HWA_DRI_DEBUG1_TOG                          (HWA_DRI_DEBUG1 + 0xc)
+#define HWT_DRI_DEBUG1_TOG                          HWIO_32_WO
+#define HWN_DRI_DEBUG1_TOG                          DRI_DEBUG1
+#define HWI_DRI_DEBUG1_TOG                          
+#define BP_DRI_DEBUG1_INVERT_PILOT                  31
+#define BM_DRI_DEBUG1_INVERT_PILOT                  0x80000000
+#define BV_DRI_DEBUG1_INVERT_PILOT__NORMAL          0x0
+#define BV_DRI_DEBUG1_INVERT_PILOT__INVERTED        0x1
+#define BF_DRI_DEBUG1_INVERT_PILOT(v)               (((v) & 0x1) << 31)
+#define BFM_DRI_DEBUG1_INVERT_PILOT(v)              BM_DRI_DEBUG1_INVERT_PILOT
+#define BF_DRI_DEBUG1_INVERT_PILOT_V(e)             BF_DRI_DEBUG1_INVERT_PILOT(BV_DRI_DEBUG1_INVERT_PILOT__##e)
+#define BFM_DRI_DEBUG1_INVERT_PILOT_V(v)            BM_DRI_DEBUG1_INVERT_PILOT
+#define BP_DRI_DEBUG1_INVERT_ATTENTION              30
+#define BM_DRI_DEBUG1_INVERT_ATTENTION              0x40000000
+#define BV_DRI_DEBUG1_INVERT_ATTENTION__NORMAL      0x0
+#define BV_DRI_DEBUG1_INVERT_ATTENTION__INVERTED    0x1
+#define BF_DRI_DEBUG1_INVERT_ATTENTION(v)           (((v) & 0x1) << 30)
+#define BFM_DRI_DEBUG1_INVERT_ATTENTION(v)          BM_DRI_DEBUG1_INVERT_ATTENTION
+#define BF_DRI_DEBUG1_INVERT_ATTENTION_V(e)         BF_DRI_DEBUG1_INVERT_ATTENTION(BV_DRI_DEBUG1_INVERT_ATTENTION__##e)
+#define BFM_DRI_DEBUG1_INVERT_ATTENTION_V(v)        BM_DRI_DEBUG1_INVERT_ATTENTION
+#define BP_DRI_DEBUG1_INVERT_DRI_DATA               29
+#define BM_DRI_DEBUG1_INVERT_DRI_DATA               0x20000000
+#define BV_DRI_DEBUG1_INVERT_DRI_DATA__NORMAL       0x0
+#define BV_DRI_DEBUG1_INVERT_DRI_DATA__INVERTED     0x1
+#define BF_DRI_DEBUG1_INVERT_DRI_DATA(v)            (((v) & 0x1) << 29)
+#define BFM_DRI_DEBUG1_INVERT_DRI_DATA(v)           BM_DRI_DEBUG1_INVERT_DRI_DATA
+#define BF_DRI_DEBUG1_INVERT_DRI_DATA_V(e)          BF_DRI_DEBUG1_INVERT_DRI_DATA(BV_DRI_DEBUG1_INVERT_DRI_DATA__##e)
+#define BFM_DRI_DEBUG1_INVERT_DRI_DATA_V(v)         BM_DRI_DEBUG1_INVERT_DRI_DATA
+#define BP_DRI_DEBUG1_INVERT_DRI_CLOCK              28
+#define BM_DRI_DEBUG1_INVERT_DRI_CLOCK              0x10000000
+#define BV_DRI_DEBUG1_INVERT_DRI_CLOCK__NORMAL      0x0
+#define BV_DRI_DEBUG1_INVERT_DRI_CLOCK__INVERTED    0x1
+#define BF_DRI_DEBUG1_INVERT_DRI_CLOCK(v)           (((v) & 0x1) << 28)
+#define BFM_DRI_DEBUG1_INVERT_DRI_CLOCK(v)          BM_DRI_DEBUG1_INVERT_DRI_CLOCK
+#define BF_DRI_DEBUG1_INVERT_DRI_CLOCK_V(e)         BF_DRI_DEBUG1_INVERT_DRI_CLOCK(BV_DRI_DEBUG1_INVERT_DRI_CLOCK__##e)
+#define BFM_DRI_DEBUG1_INVERT_DRI_CLOCK_V(v)        BM_DRI_DEBUG1_INVERT_DRI_CLOCK
+#define BP_DRI_DEBUG1_REVERSE_FRAME                 27
+#define BM_DRI_DEBUG1_REVERSE_FRAME                 0x8000000
+#define BV_DRI_DEBUG1_REVERSE_FRAME__NORMAL         0x0
+#define BV_DRI_DEBUG1_REVERSE_FRAME__REVERSED       0x1
+#define BF_DRI_DEBUG1_REVERSE_FRAME(v)              (((v) & 0x1) << 27)
+#define BFM_DRI_DEBUG1_REVERSE_FRAME(v)             BM_DRI_DEBUG1_REVERSE_FRAME
+#define BF_DRI_DEBUG1_REVERSE_FRAME_V(e)            BF_DRI_DEBUG1_REVERSE_FRAME(BV_DRI_DEBUG1_REVERSE_FRAME__##e)
+#define BFM_DRI_DEBUG1_REVERSE_FRAME_V(v)           BM_DRI_DEBUG1_REVERSE_FRAME
+#define BP_DRI_DEBUG1_RSVD1                         18
+#define BM_DRI_DEBUG1_RSVD1                         0x7fc0000
+#define BF_DRI_DEBUG1_RSVD1(v)                      (((v) & 0x1ff) << 18)
+#define BFM_DRI_DEBUG1_RSVD1(v)                     BM_DRI_DEBUG1_RSVD1
+#define BF_DRI_DEBUG1_RSVD1_V(e)                    BF_DRI_DEBUG1_RSVD1(BV_DRI_DEBUG1_RSVD1__##e)
+#define BFM_DRI_DEBUG1_RSVD1_V(v)                   BM_DRI_DEBUG1_RSVD1
+#define BP_DRI_DEBUG1_SWIZZLED_FRAME                0
+#define BM_DRI_DEBUG1_SWIZZLED_FRAME                0x3ffff
+#define BF_DRI_DEBUG1_SWIZZLED_FRAME(v)             (((v) & 0x3ffff) << 0)
+#define BFM_DRI_DEBUG1_SWIZZLED_FRAME(v)            BM_DRI_DEBUG1_SWIZZLED_FRAME
+#define BF_DRI_DEBUG1_SWIZZLED_FRAME_V(e)           BF_DRI_DEBUG1_SWIZZLED_FRAME(BV_DRI_DEBUG1_SWIZZLED_FRAME__##e)
+#define BFM_DRI_DEBUG1_SWIZZLED_FRAME_V(v)          BM_DRI_DEBUG1_SWIZZLED_FRAME
+
+#define HW_DRI_VERSION              HW(DRI_VERSION)
+#define HWA_DRI_VERSION             (0x80074000 + 0x60)
+#define HWT_DRI_VERSION             HWIO_32_RW
+#define HWN_DRI_VERSION             DRI_VERSION
+#define HWI_DRI_VERSION             
+#define BP_DRI_VERSION_MAJOR        24
+#define BM_DRI_VERSION_MAJOR        0xff000000
+#define BF_DRI_VERSION_MAJOR(v)     (((v) & 0xff) << 24)
+#define BFM_DRI_VERSION_MAJOR(v)    BM_DRI_VERSION_MAJOR
+#define BF_DRI_VERSION_MAJOR_V(e)   BF_DRI_VERSION_MAJOR(BV_DRI_VERSION_MAJOR__##e)
+#define BFM_DRI_VERSION_MAJOR_V(v)  BM_DRI_VERSION_MAJOR
+#define BP_DRI_VERSION_MINOR        16
+#define BM_DRI_VERSION_MINOR        0xff0000
+#define BF_DRI_VERSION_MINOR(v)     (((v) & 0xff) << 16)
+#define BFM_DRI_VERSION_MINOR(v)    BM_DRI_VERSION_MINOR
+#define BF_DRI_VERSION_MINOR_V(e)   BF_DRI_VERSION_MINOR(BV_DRI_VERSION_MINOR__##e)
+#define BFM_DRI_VERSION_MINOR_V(v)  BM_DRI_VERSION_MINOR
+#define BP_DRI_VERSION_STEP         0
+#define BM_DRI_VERSION_STEP         0xffff
+#define BF_DRI_VERSION_STEP(v)      (((v) & 0xffff) << 0)
+#define BFM_DRI_VERSION_STEP(v)     BM_DRI_VERSION_STEP
+#define BF_DRI_VERSION_STEP_V(e)    BF_DRI_VERSION_STEP(BV_DRI_VERSION_STEP__##e)
+#define BFM_DRI_VERSION_STEP_V(v)   BM_DRI_VERSION_STEP
+
+#endif /* __HEADERGEN_IMX233_DRI_H__*/
diff --git a/firmware/target/arm/imx233/regs/imx233/ecc8.h b/firmware/target/arm/imx233/regs/imx233/ecc8.h
new file mode 100644
index 0000000000..898c506cc6
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/imx233/ecc8.h
@@ -0,0 +1,563 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * imx233 version: 2.4.0
+ * imx233 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_IMX233_ECC8_H__
+#define __HEADERGEN_IMX233_ECC8_H__
+
+#define HW_ECC8_CTRL                            HW(ECC8_CTRL)
+#define HWA_ECC8_CTRL                           (0x80008000 + 0x0)
+#define HWT_ECC8_CTRL                           HWIO_32_RW
+#define HWN_ECC8_CTRL                           ECC8_CTRL
+#define HWI_ECC8_CTRL                           
+#define HW_ECC8_CTRL_SET                        HW(ECC8_CTRL_SET)
+#define HWA_ECC8_CTRL_SET                       (HWA_ECC8_CTRL + 0x4)
+#define HWT_ECC8_CTRL_SET                       HWIO_32_WO
+#define HWN_ECC8_CTRL_SET                       ECC8_CTRL
+#define HWI_ECC8_CTRL_SET                       
+#define HW_ECC8_CTRL_CLR                        HW(ECC8_CTRL_CLR)
+#define HWA_ECC8_CTRL_CLR                       (HWA_ECC8_CTRL + 0x8)
+#define HWT_ECC8_CTRL_CLR                       HWIO_32_WO
+#define HWN_ECC8_CTRL_CLR                       ECC8_CTRL
+#define HWI_ECC8_CTRL_CLR                       
+#define HW_ECC8_CTRL_TOG                        HW(ECC8_CTRL_TOG)
+#define HWA_ECC8_CTRL_TOG                       (HWA_ECC8_CTRL + 0xc)
+#define HWT_ECC8_CTRL_TOG                       HWIO_32_WO
+#define HWN_ECC8_CTRL_TOG                       ECC8_CTRL
+#define HWI_ECC8_CTRL_TOG                       
+#define BP_ECC8_CTRL_SFTRST                     31
+#define BM_ECC8_CTRL_SFTRST                     0x80000000
+#define BV_ECC8_CTRL_SFTRST__RUN                0x0
+#define BV_ECC8_CTRL_SFTRST__RESET              0x1
+#define BF_ECC8_CTRL_SFTRST(v)                  (((v) & 0x1) << 31)
+#define BFM_ECC8_CTRL_SFTRST(v)                 BM_ECC8_CTRL_SFTRST
+#define BF_ECC8_CTRL_SFTRST_V(e)                BF_ECC8_CTRL_SFTRST(BV_ECC8_CTRL_SFTRST__##e)
+#define BFM_ECC8_CTRL_SFTRST_V(v)               BM_ECC8_CTRL_SFTRST
+#define BP_ECC8_CTRL_CLKGATE                    30
+#define BM_ECC8_CTRL_CLKGATE                    0x40000000
+#define BV_ECC8_CTRL_CLKGATE__RUN               0x0
+#define BV_ECC8_CTRL_CLKGATE__NO_CLKS           0x1
+#define BF_ECC8_CTRL_CLKGATE(v)                 (((v) & 0x1) << 30)
+#define BFM_ECC8_CTRL_CLKGATE(v)                BM_ECC8_CTRL_CLKGATE
+#define BF_ECC8_CTRL_CLKGATE_V(e)               BF_ECC8_CTRL_CLKGATE(BV_ECC8_CTRL_CLKGATE__##e)
+#define BFM_ECC8_CTRL_CLKGATE_V(v)              BM_ECC8_CTRL_CLKGATE
+#define BP_ECC8_CTRL_AHBM_SFTRST                29
+#define BM_ECC8_CTRL_AHBM_SFTRST                0x20000000
+#define BV_ECC8_CTRL_AHBM_SFTRST__RUN           0x0
+#define BV_ECC8_CTRL_AHBM_SFTRST__RESET         0x1
+#define BF_ECC8_CTRL_AHBM_SFTRST(v)             (((v) & 0x1) << 29)
+#define BFM_ECC8_CTRL_AHBM_SFTRST(v)            BM_ECC8_CTRL_AHBM_SFTRST
+#define BF_ECC8_CTRL_AHBM_SFTRST_V(e)           BF_ECC8_CTRL_AHBM_SFTRST(BV_ECC8_CTRL_AHBM_SFTRST__##e)
+#define BFM_ECC8_CTRL_AHBM_SFTRST_V(v)          BM_ECC8_CTRL_AHBM_SFTRST
+#define BP_ECC8_CTRL_RSRVD2                     28
+#define BM_ECC8_CTRL_RSRVD2                     0x10000000
+#define BF_ECC8_CTRL_RSRVD2(v)                  (((v) & 0x1) << 28)
+#define BFM_ECC8_CTRL_RSRVD2(v)                 BM_ECC8_CTRL_RSRVD2
+#define BF_ECC8_CTRL_RSRVD2_V(e)                BF_ECC8_CTRL_RSRVD2(BV_ECC8_CTRL_RSRVD2__##e)
+#define BFM_ECC8_CTRL_RSRVD2_V(v)               BM_ECC8_CTRL_RSRVD2
+#define BP_ECC8_CTRL_THROTTLE                   24
+#define BM_ECC8_CTRL_THROTTLE                   0xf000000
+#define BF_ECC8_CTRL_THROTTLE(v)                (((v) & 0xf) << 24)
+#define BFM_ECC8_CTRL_THROTTLE(v)               BM_ECC8_CTRL_THROTTLE
+#define BF_ECC8_CTRL_THROTTLE_V(e)              BF_ECC8_CTRL_THROTTLE(BV_ECC8_CTRL_THROTTLE__##e)
+#define BFM_ECC8_CTRL_THROTTLE_V(v)             BM_ECC8_CTRL_THROTTLE
+#define BP_ECC8_CTRL_RSRVD1                     11
+#define BM_ECC8_CTRL_RSRVD1                     0xfff800
+#define BF_ECC8_CTRL_RSRVD1(v)                  (((v) & 0x1fff) << 11)
+#define BFM_ECC8_CTRL_RSRVD1(v)                 BM_ECC8_CTRL_RSRVD1
+#define BF_ECC8_CTRL_RSRVD1_V(e)                BF_ECC8_CTRL_RSRVD1(BV_ECC8_CTRL_RSRVD1__##e)
+#define BFM_ECC8_CTRL_RSRVD1_V(v)               BM_ECC8_CTRL_RSRVD1
+#define BP_ECC8_CTRL_DEBUG_STALL_IRQ_EN         10
+#define BM_ECC8_CTRL_DEBUG_STALL_IRQ_EN         0x400
+#define BF_ECC8_CTRL_DEBUG_STALL_IRQ_EN(v)      (((v) & 0x1) << 10)
+#define BFM_ECC8_CTRL_DEBUG_STALL_IRQ_EN(v)     BM_ECC8_CTRL_DEBUG_STALL_IRQ_EN
+#define BF_ECC8_CTRL_DEBUG_STALL_IRQ_EN_V(e)    BF_ECC8_CTRL_DEBUG_STALL_IRQ_EN(BV_ECC8_CTRL_DEBUG_STALL_IRQ_EN__##e)
+#define BFM_ECC8_CTRL_DEBUG_STALL_IRQ_EN_V(v)   BM_ECC8_CTRL_DEBUG_STALL_IRQ_EN
+#define BP_ECC8_CTRL_DEBUG_WRITE_IRQ_EN         9
+#define BM_ECC8_CTRL_DEBUG_WRITE_IRQ_EN         0x200
+#define BF_ECC8_CTRL_DEBUG_WRITE_IRQ_EN(v)      (((v) & 0x1) << 9)
+#define BFM_ECC8_CTRL_DEBUG_WRITE_IRQ_EN(v)     BM_ECC8_CTRL_DEBUG_WRITE_IRQ_EN
+#define BF_ECC8_CTRL_DEBUG_WRITE_IRQ_EN_V(e)    BF_ECC8_CTRL_DEBUG_WRITE_IRQ_EN(BV_ECC8_CTRL_DEBUG_WRITE_IRQ_EN__##e)
+#define BFM_ECC8_CTRL_DEBUG_WRITE_IRQ_EN_V(v)   BM_ECC8_CTRL_DEBUG_WRITE_IRQ_EN
+#define BP_ECC8_CTRL_COMPLETE_IRQ_EN            8
+#define BM_ECC8_CTRL_COMPLETE_IRQ_EN            0x100
+#define BF_ECC8_CTRL_COMPLETE_IRQ_EN(v)         (((v) & 0x1) << 8)
+#define BFM_ECC8_CTRL_COMPLETE_IRQ_EN(v)        BM_ECC8_CTRL_COMPLETE_IRQ_EN
+#define BF_ECC8_CTRL_COMPLETE_IRQ_EN_V(e)       BF_ECC8_CTRL_COMPLETE_IRQ_EN(BV_ECC8_CTRL_COMPLETE_IRQ_EN__##e)
+#define BFM_ECC8_CTRL_COMPLETE_IRQ_EN_V(v)      BM_ECC8_CTRL_COMPLETE_IRQ_EN
+#define BP_ECC8_CTRL_RSRVD0                     4
+#define BM_ECC8_CTRL_RSRVD0                     0xf0
+#define BF_ECC8_CTRL_RSRVD0(v)                  (((v) & 0xf) << 4)
+#define BFM_ECC8_CTRL_RSRVD0(v)                 BM_ECC8_CTRL_RSRVD0
+#define BF_ECC8_CTRL_RSRVD0_V(e)                BF_ECC8_CTRL_RSRVD0(BV_ECC8_CTRL_RSRVD0__##e)
+#define BFM_ECC8_CTRL_RSRVD0_V(v)               BM_ECC8_CTRL_RSRVD0
+#define BP_ECC8_CTRL_BM_ERROR_IRQ               3
+#define BM_ECC8_CTRL_BM_ERROR_IRQ               0x8
+#define BF_ECC8_CTRL_BM_ERROR_IRQ(v)            (((v) & 0x1) << 3)
+#define BFM_ECC8_CTRL_BM_ERROR_IRQ(v)           BM_ECC8_CTRL_BM_ERROR_IRQ
+#define BF_ECC8_CTRL_BM_ERROR_IRQ_V(e)          BF_ECC8_CTRL_BM_ERROR_IRQ(BV_ECC8_CTRL_BM_ERROR_IRQ__##e)
+#define BFM_ECC8_CTRL_BM_ERROR_IRQ_V(v)         BM_ECC8_CTRL_BM_ERROR_IRQ
+#define BP_ECC8_CTRL_DEBUG_STALL_IRQ            2
+#define BM_ECC8_CTRL_DEBUG_STALL_IRQ            0x4
+#define BF_ECC8_CTRL_DEBUG_STALL_IRQ(v)         (((v) & 0x1) << 2)
+#define BFM_ECC8_CTRL_DEBUG_STALL_IRQ(v)        BM_ECC8_CTRL_DEBUG_STALL_IRQ
+#define BF_ECC8_CTRL_DEBUG_STALL_IRQ_V(e)       BF_ECC8_CTRL_DEBUG_STALL_IRQ(BV_ECC8_CTRL_DEBUG_STALL_IRQ__##e)
+#define BFM_ECC8_CTRL_DEBUG_STALL_IRQ_V(v)      BM_ECC8_CTRL_DEBUG_STALL_IRQ
+#define BP_ECC8_CTRL_DEBUG_WRITE_IRQ            1
+#define BM_ECC8_CTRL_DEBUG_WRITE_IRQ            0x2
+#define BF_ECC8_CTRL_DEBUG_WRITE_IRQ(v)         (((v) & 0x1) << 1)
+#define BFM_ECC8_CTRL_DEBUG_WRITE_IRQ(v)        BM_ECC8_CTRL_DEBUG_WRITE_IRQ
+#define BF_ECC8_CTRL_DEBUG_WRITE_IRQ_V(e)       BF_ECC8_CTRL_DEBUG_WRITE_IRQ(BV_ECC8_CTRL_DEBUG_WRITE_IRQ__##e)
+#define BFM_ECC8_CTRL_DEBUG_WRITE_IRQ_V(v)      BM_ECC8_CTRL_DEBUG_WRITE_IRQ
+#define BP_ECC8_CTRL_COMPLETE_IRQ               0
+#define BM_ECC8_CTRL_COMPLETE_IRQ               0x1
+#define BF_ECC8_CTRL_COMPLETE_IRQ(v)            (((v) & 0x1) << 0)
+#define BFM_ECC8_CTRL_COMPLETE_IRQ(v)           BM_ECC8_CTRL_COMPLETE_IRQ
+#define BF_ECC8_CTRL_COMPLETE_IRQ_V(e)          BF_ECC8_CTRL_COMPLETE_IRQ(BV_ECC8_CTRL_COMPLETE_IRQ__##e)
+#define BFM_ECC8_CTRL_COMPLETE_IRQ_V(v)         BM_ECC8_CTRL_COMPLETE_IRQ
+
+#define HW_ECC8_STATUS0                                 HW(ECC8_STATUS0)
+#define HWA_ECC8_STATUS0                                (0x80008000 + 0x10)
+#define HWT_ECC8_STATUS0                                HWIO_32_RW
+#define HWN_ECC8_STATUS0                                ECC8_STATUS0
+#define HWI_ECC8_STATUS0                                
+#define BP_ECC8_STATUS0_HANDLE                          20
+#define BM_ECC8_STATUS0_HANDLE                          0xfff00000
+#define BF_ECC8_STATUS0_HANDLE(v)                       (((v) & 0xfff) << 20)
+#define BFM_ECC8_STATUS0_HANDLE(v)                      BM_ECC8_STATUS0_HANDLE
+#define BF_ECC8_STATUS0_HANDLE_V(e)                     BF_ECC8_STATUS0_HANDLE(BV_ECC8_STATUS0_HANDLE__##e)
+#define BFM_ECC8_STATUS0_HANDLE_V(v)                    BM_ECC8_STATUS0_HANDLE
+#define BP_ECC8_STATUS0_COMPLETED_CE                    16
+#define BM_ECC8_STATUS0_COMPLETED_CE                    0xf0000
+#define BF_ECC8_STATUS0_COMPLETED_CE(v)                 (((v) & 0xf) << 16)
+#define BFM_ECC8_STATUS0_COMPLETED_CE(v)                BM_ECC8_STATUS0_COMPLETED_CE
+#define BF_ECC8_STATUS0_COMPLETED_CE_V(e)               BF_ECC8_STATUS0_COMPLETED_CE(BV_ECC8_STATUS0_COMPLETED_CE__##e)
+#define BFM_ECC8_STATUS0_COMPLETED_CE_V(v)              BM_ECC8_STATUS0_COMPLETED_CE
+#define BP_ECC8_STATUS0_RS8ECC_ENC_PRESENT              15
+#define BM_ECC8_STATUS0_RS8ECC_ENC_PRESENT              0x8000
+#define BF_ECC8_STATUS0_RS8ECC_ENC_PRESENT(v)           (((v) & 0x1) << 15)
+#define BFM_ECC8_STATUS0_RS8ECC_ENC_PRESENT(v)          BM_ECC8_STATUS0_RS8ECC_ENC_PRESENT
+#define BF_ECC8_STATUS0_RS8ECC_ENC_PRESENT_V(e)         BF_ECC8_STATUS0_RS8ECC_ENC_PRESENT(BV_ECC8_STATUS0_RS8ECC_ENC_PRESENT__##e)
+#define BFM_ECC8_STATUS0_RS8ECC_ENC_PRESENT_V(v)        BM_ECC8_STATUS0_RS8ECC_ENC_PRESENT
+#define BP_ECC8_STATUS0_RS8ECC_DEC_PRESENT              14
+#define BM_ECC8_STATUS0_RS8ECC_DEC_PRESENT              0x4000
+#define BF_ECC8_STATUS0_RS8ECC_DEC_PRESENT(v)           (((v) & 0x1) << 14)
+#define BFM_ECC8_STATUS0_RS8ECC_DEC_PRESENT(v)          BM_ECC8_STATUS0_RS8ECC_DEC_PRESENT
+#define BF_ECC8_STATUS0_RS8ECC_DEC_PRESENT_V(e)         BF_ECC8_STATUS0_RS8ECC_DEC_PRESENT(BV_ECC8_STATUS0_RS8ECC_DEC_PRESENT__##e)
+#define BFM_ECC8_STATUS0_RS8ECC_DEC_PRESENT_V(v)        BM_ECC8_STATUS0_RS8ECC_DEC_PRESENT
+#define BP_ECC8_STATUS0_RS4ECC_ENC_PRESENT              13
+#define BM_ECC8_STATUS0_RS4ECC_ENC_PRESENT              0x2000
+#define BF_ECC8_STATUS0_RS4ECC_ENC_PRESENT(v)           (((v) & 0x1) << 13)
+#define BFM_ECC8_STATUS0_RS4ECC_ENC_PRESENT(v)          BM_ECC8_STATUS0_RS4ECC_ENC_PRESENT
+#define BF_ECC8_STATUS0_RS4ECC_ENC_PRESENT_V(e)         BF_ECC8_STATUS0_RS4ECC_ENC_PRESENT(BV_ECC8_STATUS0_RS4ECC_ENC_PRESENT__##e)
+#define BFM_ECC8_STATUS0_RS4ECC_ENC_PRESENT_V(v)        BM_ECC8_STATUS0_RS4ECC_ENC_PRESENT
+#define BP_ECC8_STATUS0_RS4ECC_DEC_PRESENT              12
+#define BM_ECC8_STATUS0_RS4ECC_DEC_PRESENT              0x1000
+#define BF_ECC8_STATUS0_RS4ECC_DEC_PRESENT(v)           (((v) & 0x1) << 12)
+#define BFM_ECC8_STATUS0_RS4ECC_DEC_PRESENT(v)          BM_ECC8_STATUS0_RS4ECC_DEC_PRESENT
+#define BF_ECC8_STATUS0_RS4ECC_DEC_PRESENT_V(e)         BF_ECC8_STATUS0_RS4ECC_DEC_PRESENT(BV_ECC8_STATUS0_RS4ECC_DEC_PRESENT__##e)
+#define BFM_ECC8_STATUS0_RS4ECC_DEC_PRESENT_V(v)        BM_ECC8_STATUS0_RS4ECC_DEC_PRESENT
+#define BP_ECC8_STATUS0_STATUS_AUX                      8
+#define BM_ECC8_STATUS0_STATUS_AUX                      0xf00
+#define BV_ECC8_STATUS0_STATUS_AUX__NO_ERRORS           0x0
+#define BV_ECC8_STATUS0_STATUS_AUX__ONE_CORRECTABLE     0x1
+#define BV_ECC8_STATUS0_STATUS_AUX__TWO_CORRECTABLE     0x2
+#define BV_ECC8_STATUS0_STATUS_AUX__THREE_CORRECTABLE   0x3
+#define BV_ECC8_STATUS0_STATUS_AUX__FOUR_CORRECTABLE    0x4
+#define BV_ECC8_STATUS0_STATUS_AUX__NOT_CHECKED         0xc
+#define BV_ECC8_STATUS0_STATUS_AUX__UNCORRECTABLE       0xe
+#define BV_ECC8_STATUS0_STATUS_AUX__ALL_ONES            0xf
+#define BF_ECC8_STATUS0_STATUS_AUX(v)                   (((v) & 0xf) << 8)
+#define BFM_ECC8_STATUS0_STATUS_AUX(v)                  BM_ECC8_STATUS0_STATUS_AUX
+#define BF_ECC8_STATUS0_STATUS_AUX_V(e)                 BF_ECC8_STATUS0_STATUS_AUX(BV_ECC8_STATUS0_STATUS_AUX__##e)
+#define BFM_ECC8_STATUS0_STATUS_AUX_V(v)                BM_ECC8_STATUS0_STATUS_AUX
+#define BP_ECC8_STATUS0_RSVD1                           5
+#define BM_ECC8_STATUS0_RSVD1                           0xe0
+#define BF_ECC8_STATUS0_RSVD1(v)                        (((v) & 0x7) << 5)
+#define BFM_ECC8_STATUS0_RSVD1(v)                       BM_ECC8_STATUS0_RSVD1
+#define BF_ECC8_STATUS0_RSVD1_V(e)                      BF_ECC8_STATUS0_RSVD1(BV_ECC8_STATUS0_RSVD1__##e)
+#define BFM_ECC8_STATUS0_RSVD1_V(v)                     BM_ECC8_STATUS0_RSVD1
+#define BP_ECC8_STATUS0_ALLONES                         4
+#define BM_ECC8_STATUS0_ALLONES                         0x10
+#define BF_ECC8_STATUS0_ALLONES(v)                      (((v) & 0x1) << 4)
+#define BFM_ECC8_STATUS0_ALLONES(v)                     BM_ECC8_STATUS0_ALLONES
+#define BF_ECC8_STATUS0_ALLONES_V(e)                    BF_ECC8_STATUS0_ALLONES(BV_ECC8_STATUS0_ALLONES__##e)
+#define BFM_ECC8_STATUS0_ALLONES_V(v)                   BM_ECC8_STATUS0_ALLONES
+#define BP_ECC8_STATUS0_CORRECTED                       3
+#define BM_ECC8_STATUS0_CORRECTED                       0x8
+#define BF_ECC8_STATUS0_CORRECTED(v)                    (((v) & 0x1) << 3)
+#define BFM_ECC8_STATUS0_CORRECTED(v)                   BM_ECC8_STATUS0_CORRECTED
+#define BF_ECC8_STATUS0_CORRECTED_V(e)                  BF_ECC8_STATUS0_CORRECTED(BV_ECC8_STATUS0_CORRECTED__##e)
+#define BFM_ECC8_STATUS0_CORRECTED_V(v)                 BM_ECC8_STATUS0_CORRECTED
+#define BP_ECC8_STATUS0_UNCORRECTABLE                   2
+#define BM_ECC8_STATUS0_UNCORRECTABLE                   0x4
+#define BF_ECC8_STATUS0_UNCORRECTABLE(v)                (((v) & 0x1) << 2)
+#define BFM_ECC8_STATUS0_UNCORRECTABLE(v)               BM_ECC8_STATUS0_UNCORRECTABLE
+#define BF_ECC8_STATUS0_UNCORRECTABLE_V(e)              BF_ECC8_STATUS0_UNCORRECTABLE(BV_ECC8_STATUS0_UNCORRECTABLE__##e)
+#define BFM_ECC8_STATUS0_UNCORRECTABLE_V(v)             BM_ECC8_STATUS0_UNCORRECTABLE
+#define BP_ECC8_STATUS0_RSVD0                           0
+#define BM_ECC8_STATUS0_RSVD0                           0x3
+#define BF_ECC8_STATUS0_RSVD0(v)                        (((v) & 0x3) << 0)
+#define BFM_ECC8_STATUS0_RSVD0(v)                       BM_ECC8_STATUS0_RSVD0
+#define BF_ECC8_STATUS0_RSVD0_V(e)                      BF_ECC8_STATUS0_RSVD0(BV_ECC8_STATUS0_RSVD0__##e)
+#define BFM_ECC8_STATUS0_RSVD0_V(v)                     BM_ECC8_STATUS0_RSVD0
+
+#define HW_ECC8_STATUS1                                     HW(ECC8_STATUS1)
+#define HWA_ECC8_STATUS1                                    (0x80008000 + 0x20)
+#define HWT_ECC8_STATUS1                                    HWIO_32_RW
+#define HWN_ECC8_STATUS1                                    ECC8_STATUS1
+#define HWI_ECC8_STATUS1                                    
+#define BP_ECC8_STATUS1_STATUS_PAYLOAD7                     28
+#define BM_ECC8_STATUS1_STATUS_PAYLOAD7                     0xf0000000
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__NO_ERRORS          0x0
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__ONE_CORRECTABLE    0x1
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__TWO_CORRECTABLE    0x2
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__THREE_CORRECTABLE  0x3
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__FOUR_CORRECTABLE   0x4
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__FIVE_CORRECTABLE   0x5
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__SIX_CORRECTABLE    0x6
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__SEVEN_CORRECTABLE  0x7
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__EIGHT_CORRECTABLE  0x8
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__NOT_CHECKED        0xc
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__UNCORRECTABLE      0xe
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__ALL_ONES           0xf
+#define BF_ECC8_STATUS1_STATUS_PAYLOAD7(v)                  (((v) & 0xf) << 28)
+#define BFM_ECC8_STATUS1_STATUS_PAYLOAD7(v)                 BM_ECC8_STATUS1_STATUS_PAYLOAD7
+#define BF_ECC8_STATUS1_STATUS_PAYLOAD7_V(e)                BF_ECC8_STATUS1_STATUS_PAYLOAD7(BV_ECC8_STATUS1_STATUS_PAYLOAD7__##e)
+#define BFM_ECC8_STATUS1_STATUS_PAYLOAD7_V(v)               BM_ECC8_STATUS1_STATUS_PAYLOAD7
+#define BP_ECC8_STATUS1_STATUS_PAYLOAD6                     24
+#define BM_ECC8_STATUS1_STATUS_PAYLOAD6                     0xf000000
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__NO_ERRORS          0x0
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__ONE_CORRECTABLE    0x1
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__TWO_CORRECTABLE    0x2
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__THREE_CORRECTABLE  0x3
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__FOUR_CORRECTABLE   0x4
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__FIVE_CORRECTABLE   0x5
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__SIX_CORRECTABLE    0x6
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__SEVEN_CORRECTABLE  0x7
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__EIGHT_CORRECTABLE  0x8
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__NOT_CHECKED        0xc
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__UNCORRECTABLE      0xe
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__ALL_ONES           0xf
+#define BF_ECC8_STATUS1_STATUS_PAYLOAD6(v)                  (((v) & 0xf) << 24)
+#define BFM_ECC8_STATUS1_STATUS_PAYLOAD6(v)                 BM_ECC8_STATUS1_STATUS_PAYLOAD6
+#define BF_ECC8_STATUS1_STATUS_PAYLOAD6_V(e)                BF_ECC8_STATUS1_STATUS_PAYLOAD6(BV_ECC8_STATUS1_STATUS_PAYLOAD6__##e)
+#define BFM_ECC8_STATUS1_STATUS_PAYLOAD6_V(v)               BM_ECC8_STATUS1_STATUS_PAYLOAD6
+#define BP_ECC8_STATUS1_STATUS_PAYLOAD5                     20
+#define BM_ECC8_STATUS1_STATUS_PAYLOAD5                     0xf00000
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__NO_ERRORS          0x0
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__ONE_CORRECTABLE    0x1
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__TWO_CORRECTABLE    0x2
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__THREE_CORRECTABLE  0x3
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__FOUR_CORRECTABLE   0x4
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__FIVE_CORRECTABLE   0x5
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__SIX_CORRECTABLE    0x6
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__SEVEN_CORRECTABLE  0x7
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__EIGHT_CORRECTABLE  0x8
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__NOT_CHECKED        0xc
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__UNCORRECTABLE      0xe
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__ALL_ONES           0xf
+#define BF_ECC8_STATUS1_STATUS_PAYLOAD5(v)                  (((v) & 0xf) << 20)
+#define BFM_ECC8_STATUS1_STATUS_PAYLOAD5(v)                 BM_ECC8_STATUS1_STATUS_PAYLOAD5
+#define BF_ECC8_STATUS1_STATUS_PAYLOAD5_V(e)                BF_ECC8_STATUS1_STATUS_PAYLOAD5(BV_ECC8_STATUS1_STATUS_PAYLOAD5__##e)
+#define BFM_ECC8_STATUS1_STATUS_PAYLOAD5_V(v)               BM_ECC8_STATUS1_STATUS_PAYLOAD5
+#define BP_ECC8_STATUS1_STATUS_PAYLOAD4                     16
+#define BM_ECC8_STATUS1_STATUS_PAYLOAD4                     0xf0000
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__NO_ERRORS          0x0
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__ONE_CORRECTABLE    0x1
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__TWO_CORRECTABLE    0x2
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__THREE_CORRECTABLE  0x3
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__FOUR_CORRECTABLE   0x4
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__FIVE_CORRECTABLE   0x5
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__SIX_CORRECTABLE    0x6
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__SEVEN_CORRECTABLE  0x7
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__EIGHT_CORRECTABLE  0x8
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__NOT_CHECKED        0xc
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__UNCORRECTABLE      0xe
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__ALL_ONES           0xf
+#define BF_ECC8_STATUS1_STATUS_PAYLOAD4(v)                  (((v) & 0xf) << 16)
+#define BFM_ECC8_STATUS1_STATUS_PAYLOAD4(v)                 BM_ECC8_STATUS1_STATUS_PAYLOAD4
+#define BF_ECC8_STATUS1_STATUS_PAYLOAD4_V(e)                BF_ECC8_STATUS1_STATUS_PAYLOAD4(BV_ECC8_STATUS1_STATUS_PAYLOAD4__##e)
+#define BFM_ECC8_STATUS1_STATUS_PAYLOAD4_V(v)               BM_ECC8_STATUS1_STATUS_PAYLOAD4
+#define BP_ECC8_STATUS1_STATUS_PAYLOAD3                     12
+#define BM_ECC8_STATUS1_STATUS_PAYLOAD3                     0xf000
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__NO_ERRORS          0x0
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__ONE_CORRECTABLE    0x1
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__TWO_CORRECTABLE    0x2
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__THREE_CORRECTABLE  0x3
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__FOUR_CORRECTABLE   0x4
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__FIVE_CORRECTABLE   0x5
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__SIX_CORRECTABLE    0x6
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__SEVEN_CORRECTABLE  0x7
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__EIGHT_CORRECTABLE  0x8
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__NOT_CHECKED        0xc
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__UNCORRECTABLE      0xe
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__ALL_ONES           0xf
+#define BF_ECC8_STATUS1_STATUS_PAYLOAD3(v)                  (((v) & 0xf) << 12)
+#define BFM_ECC8_STATUS1_STATUS_PAYLOAD3(v)                 BM_ECC8_STATUS1_STATUS_PAYLOAD3
+#define BF_ECC8_STATUS1_STATUS_PAYLOAD3_V(e)                BF_ECC8_STATUS1_STATUS_PAYLOAD3(BV_ECC8_STATUS1_STATUS_PAYLOAD3__##e)
+#define BFM_ECC8_STATUS1_STATUS_PAYLOAD3_V(v)               BM_ECC8_STATUS1_STATUS_PAYLOAD3
+#define BP_ECC8_STATUS1_STATUS_PAYLOAD2                     8
+#define BM_ECC8_STATUS1_STATUS_PAYLOAD2                     0xf00
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__NO_ERRORS          0x0
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__ONE_CORRECTABLE    0x1
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__TWO_CORRECTABLE    0x2
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__THREE_CORRECTABLE  0x3
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__FOUR_CORRECTABLE   0x4
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__FIVE_CORRECTABLE   0x5
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__SIX_CORRECTABLE    0x6
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__SEVEN_CORRECTABLE  0x7
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__EIGHT_CORRECTABLE  0x8
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__NOT_CHECKED        0xc
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__UNCORRECTABLE      0xe
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__ALL_ONES           0xf
+#define BF_ECC8_STATUS1_STATUS_PAYLOAD2(v)                  (((v) & 0xf) << 8)
+#define BFM_ECC8_STATUS1_STATUS_PAYLOAD2(v)                 BM_ECC8_STATUS1_STATUS_PAYLOAD2
+#define BF_ECC8_STATUS1_STATUS_PAYLOAD2_V(e)                BF_ECC8_STATUS1_STATUS_PAYLOAD2(BV_ECC8_STATUS1_STATUS_PAYLOAD2__##e)
+#define BFM_ECC8_STATUS1_STATUS_PAYLOAD2_V(v)               BM_ECC8_STATUS1_STATUS_PAYLOAD2
+#define BP_ECC8_STATUS1_STATUS_PAYLOAD1                     4
+#define BM_ECC8_STATUS1_STATUS_PAYLOAD1                     0xf0
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__NO_ERRORS          0x0
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__ONE_CORRECTABLE    0x1
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__TWO_CORRECTABLE    0x2
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__THREE_CORRECTABLE  0x3
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__FOUR_CORRECTABLE   0x4
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__FIVE_CORRECTABLE   0x5
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__SIX_CORRECTABLE    0x6
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__SEVEN_CORRECTABLE  0x7
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__EIGHT_CORRECTABLE  0x8
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__NOT_CHECKED        0xc
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__UNCORRECTABLE      0xe
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__ALL_ONES           0xf
+#define BF_ECC8_STATUS1_STATUS_PAYLOAD1(v)                  (((v) & 0xf) << 4)
+#define BFM_ECC8_STATUS1_STATUS_PAYLOAD1(v)                 BM_ECC8_STATUS1_STATUS_PAYLOAD1
+#define BF_ECC8_STATUS1_STATUS_PAYLOAD1_V(e)                BF_ECC8_STATUS1_STATUS_PAYLOAD1(BV_ECC8_STATUS1_STATUS_PAYLOAD1__##e)
+#define BFM_ECC8_STATUS1_STATUS_PAYLOAD1_V(v)               BM_ECC8_STATUS1_STATUS_PAYLOAD1
+#define BP_ECC8_STATUS1_STATUS_PAYLOAD0                     0
+#define BM_ECC8_STATUS1_STATUS_PAYLOAD0                     0xf
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__NO_ERRORS          0x0
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__ONE_CORRECTABLE    0x1
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__TWO_CORRECTABLE    0x2
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__THREE_CORRECTABLE  0x3
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__FOUR_CORRECTABLE   0x4
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__FIVE_CORRECTABLE   0x5
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__SIX_CORRECTABLE    0x6
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__SEVEN_CORRECTABLE  0x7
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__EIGHT_CORRECTABLE  0x8
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__NOT_CHECKED        0xc
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__UNCORRECTABLE      0xe
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__ALL_ONES           0xf
+#define BF_ECC8_STATUS1_STATUS_PAYLOAD0(v)                  (((v) & 0xf) << 0)
+#define BFM_ECC8_STATUS1_STATUS_PAYLOAD0(v)                 BM_ECC8_STATUS1_STATUS_PAYLOAD0
+#define BF_ECC8_STATUS1_STATUS_PAYLOAD0_V(e)                BF_ECC8_STATUS1_STATUS_PAYLOAD0(BV_ECC8_STATUS1_STATUS_PAYLOAD0__##e)
+#define BFM_ECC8_STATUS1_STATUS_PAYLOAD0_V(v)               BM_ECC8_STATUS1_STATUS_PAYLOAD0
+
+#define HW_ECC8_DEBUG0                                      HW(ECC8_DEBUG0)
+#define HWA_ECC8_DEBUG0                                     (0x80008000 + 0x30)
+#define HWT_ECC8_DEBUG0                                     HWIO_32_RW
+#define HWN_ECC8_DEBUG0                                     ECC8_DEBUG0
+#define HWI_ECC8_DEBUG0                                     
+#define HW_ECC8_DEBUG0_SET                                  HW(ECC8_DEBUG0_SET)
+#define HWA_ECC8_DEBUG0_SET                                 (HWA_ECC8_DEBUG0 + 0x4)
+#define HWT_ECC8_DEBUG0_SET                                 HWIO_32_WO
+#define HWN_ECC8_DEBUG0_SET                                 ECC8_DEBUG0
+#define HWI_ECC8_DEBUG0_SET                                 
+#define HW_ECC8_DEBUG0_CLR                                  HW(ECC8_DEBUG0_CLR)
+#define HWA_ECC8_DEBUG0_CLR                                 (HWA_ECC8_DEBUG0 + 0x8)
+#define HWT_ECC8_DEBUG0_CLR                                 HWIO_32_WO
+#define HWN_ECC8_DEBUG0_CLR                                 ECC8_DEBUG0
+#define HWI_ECC8_DEBUG0_CLR                                 
+#define HW_ECC8_DEBUG0_TOG                                  HW(ECC8_DEBUG0_TOG)
+#define HWA_ECC8_DEBUG0_TOG                                 (HWA_ECC8_DEBUG0 + 0xc)
+#define HWT_ECC8_DEBUG0_TOG                                 HWIO_32_WO
+#define HWN_ECC8_DEBUG0_TOG                                 ECC8_DEBUG0
+#define HWI_ECC8_DEBUG0_TOG                                 
+#define BP_ECC8_DEBUG0_RSRVD1                               25
+#define BM_ECC8_DEBUG0_RSRVD1                               0xfe000000
+#define BF_ECC8_DEBUG0_RSRVD1(v)                            (((v) & 0x7f) << 25)
+#define BFM_ECC8_DEBUG0_RSRVD1(v)                           BM_ECC8_DEBUG0_RSRVD1
+#define BF_ECC8_DEBUG0_RSRVD1_V(e)                          BF_ECC8_DEBUG0_RSRVD1(BV_ECC8_DEBUG0_RSRVD1__##e)
+#define BFM_ECC8_DEBUG0_RSRVD1_V(v)                         BM_ECC8_DEBUG0_RSRVD1
+#define BP_ECC8_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL            16
+#define BM_ECC8_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL            0x1ff0000
+#define BV_ECC8_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__NORMAL    0x0
+#define BV_ECC8_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__TEST_MODE 0x1
+#define BF_ECC8_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL(v)         (((v) & 0x1ff) << 16)
+#define BFM_ECC8_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL(v)        BM_ECC8_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL
+#define BF_ECC8_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_V(e)       BF_ECC8_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL(BV_ECC8_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__##e)
+#define BFM_ECC8_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_V(v)      BM_ECC8_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL
+#define BP_ECC8_DEBUG0_KES_DEBUG_SHIFT_SYND                 15
+#define BM_ECC8_DEBUG0_KES_DEBUG_SHIFT_SYND                 0x8000
+#define BF_ECC8_DEBUG0_KES_DEBUG_SHIFT_SYND(v)              (((v) & 0x1) << 15)
+#define BFM_ECC8_DEBUG0_KES_DEBUG_SHIFT_SYND(v)             BM_ECC8_DEBUG0_KES_DEBUG_SHIFT_SYND
+#define BF_ECC8_DEBUG0_KES_DEBUG_SHIFT_SYND_V(e)            BF_ECC8_DEBUG0_KES_DEBUG_SHIFT_SYND(BV_ECC8_DEBUG0_KES_DEBUG_SHIFT_SYND__##e)
+#define BFM_ECC8_DEBUG0_KES_DEBUG_SHIFT_SYND_V(v)           BM_ECC8_DEBUG0_KES_DEBUG_SHIFT_SYND
+#define BP_ECC8_DEBUG0_KES_DEBUG_PAYLOAD_FLAG               14
+#define BM_ECC8_DEBUG0_KES_DEBUG_PAYLOAD_FLAG               0x4000
+#define BV_ECC8_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__DATA         0x1
+#define BV_ECC8_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__AUX          0x1
+#define BF_ECC8_DEBUG0_KES_DEBUG_PAYLOAD_FLAG(v)            (((v) & 0x1) << 14)
+#define BFM_ECC8_DEBUG0_KES_DEBUG_PAYLOAD_FLAG(v)           BM_ECC8_DEBUG0_KES_DEBUG_PAYLOAD_FLAG
+#define BF_ECC8_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_V(e)          BF_ECC8_DEBUG0_KES_DEBUG_PAYLOAD_FLAG(BV_ECC8_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__##e)
+#define BFM_ECC8_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_V(v)         BM_ECC8_DEBUG0_KES_DEBUG_PAYLOAD_FLAG
+#define BP_ECC8_DEBUG0_KES_DEBUG_MODE4K                     13
+#define BM_ECC8_DEBUG0_KES_DEBUG_MODE4K                     0x2000
+#define BV_ECC8_DEBUG0_KES_DEBUG_MODE4K__4k                 0x1
+#define BV_ECC8_DEBUG0_KES_DEBUG_MODE4K__2k                 0x1
+#define BF_ECC8_DEBUG0_KES_DEBUG_MODE4K(v)                  (((v) & 0x1) << 13)
+#define BFM_ECC8_DEBUG0_KES_DEBUG_MODE4K(v)                 BM_ECC8_DEBUG0_KES_DEBUG_MODE4K
+#define BF_ECC8_DEBUG0_KES_DEBUG_MODE4K_V(e)                BF_ECC8_DEBUG0_KES_DEBUG_MODE4K(BV_ECC8_DEBUG0_KES_DEBUG_MODE4K__##e)
+#define BFM_ECC8_DEBUG0_KES_DEBUG_MODE4K_V(v)               BM_ECC8_DEBUG0_KES_DEBUG_MODE4K
+#define BP_ECC8_DEBUG0_KES_DEBUG_KICK                       12
+#define BM_ECC8_DEBUG0_KES_DEBUG_KICK                       0x1000
+#define BF_ECC8_DEBUG0_KES_DEBUG_KICK(v)                    (((v) & 0x1) << 12)
+#define BFM_ECC8_DEBUG0_KES_DEBUG_KICK(v)                   BM_ECC8_DEBUG0_KES_DEBUG_KICK
+#define BF_ECC8_DEBUG0_KES_DEBUG_KICK_V(e)                  BF_ECC8_DEBUG0_KES_DEBUG_KICK(BV_ECC8_DEBUG0_KES_DEBUG_KICK__##e)
+#define BFM_ECC8_DEBUG0_KES_DEBUG_KICK_V(v)                 BM_ECC8_DEBUG0_KES_DEBUG_KICK
+#define BP_ECC8_DEBUG0_KES_STANDALONE                       11
+#define BM_ECC8_DEBUG0_KES_STANDALONE                       0x800
+#define BV_ECC8_DEBUG0_KES_STANDALONE__NORMAL               0x0
+#define BV_ECC8_DEBUG0_KES_STANDALONE__TEST_MODE            0x1
+#define BF_ECC8_DEBUG0_KES_STANDALONE(v)                    (((v) & 0x1) << 11)
+#define BFM_ECC8_DEBUG0_KES_STANDALONE(v)                   BM_ECC8_DEBUG0_KES_STANDALONE
+#define BF_ECC8_DEBUG0_KES_STANDALONE_V(e)                  BF_ECC8_DEBUG0_KES_STANDALONE(BV_ECC8_DEBUG0_KES_STANDALONE__##e)
+#define BFM_ECC8_DEBUG0_KES_STANDALONE_V(v)                 BM_ECC8_DEBUG0_KES_STANDALONE
+#define BP_ECC8_DEBUG0_KES_DEBUG_STEP                       10
+#define BM_ECC8_DEBUG0_KES_DEBUG_STEP                       0x400
+#define BF_ECC8_DEBUG0_KES_DEBUG_STEP(v)                    (((v) & 0x1) << 10)
+#define BFM_ECC8_DEBUG0_KES_DEBUG_STEP(v)                   BM_ECC8_DEBUG0_KES_DEBUG_STEP
+#define BF_ECC8_DEBUG0_KES_DEBUG_STEP_V(e)                  BF_ECC8_DEBUG0_KES_DEBUG_STEP(BV_ECC8_DEBUG0_KES_DEBUG_STEP__##e)
+#define BFM_ECC8_DEBUG0_KES_DEBUG_STEP_V(v)                 BM_ECC8_DEBUG0_KES_DEBUG_STEP
+#define BP_ECC8_DEBUG0_KES_DEBUG_STALL                      9
+#define BM_ECC8_DEBUG0_KES_DEBUG_STALL                      0x200
+#define BV_ECC8_DEBUG0_KES_DEBUG_STALL__NORMAL              0x0
+#define BV_ECC8_DEBUG0_KES_DEBUG_STALL__WAIT                0x1
+#define BF_ECC8_DEBUG0_KES_DEBUG_STALL(v)                   (((v) & 0x1) << 9)
+#define BFM_ECC8_DEBUG0_KES_DEBUG_STALL(v)                  BM_ECC8_DEBUG0_KES_DEBUG_STALL
+#define BF_ECC8_DEBUG0_KES_DEBUG_STALL_V(e)                 BF_ECC8_DEBUG0_KES_DEBUG_STALL(BV_ECC8_DEBUG0_KES_DEBUG_STALL__##e)
+#define BFM_ECC8_DEBUG0_KES_DEBUG_STALL_V(v)                BM_ECC8_DEBUG0_KES_DEBUG_STALL
+#define BP_ECC8_DEBUG0_BM_KES_TEST_BYPASS                   8
+#define BM_ECC8_DEBUG0_BM_KES_TEST_BYPASS                   0x100
+#define BV_ECC8_DEBUG0_BM_KES_TEST_BYPASS__NORMAL           0x0
+#define BV_ECC8_DEBUG0_BM_KES_TEST_BYPASS__TEST_MODE        0x1
+#define BF_ECC8_DEBUG0_BM_KES_TEST_BYPASS(v)                (((v) & 0x1) << 8)
+#define BFM_ECC8_DEBUG0_BM_KES_TEST_BYPASS(v)               BM_ECC8_DEBUG0_BM_KES_TEST_BYPASS
+#define BF_ECC8_DEBUG0_BM_KES_TEST_BYPASS_V(e)              BF_ECC8_DEBUG0_BM_KES_TEST_BYPASS(BV_ECC8_DEBUG0_BM_KES_TEST_BYPASS__##e)
+#define BFM_ECC8_DEBUG0_BM_KES_TEST_BYPASS_V(v)             BM_ECC8_DEBUG0_BM_KES_TEST_BYPASS
+#define BP_ECC8_DEBUG0_RSRVD0                               6
+#define BM_ECC8_DEBUG0_RSRVD0                               0xc0
+#define BF_ECC8_DEBUG0_RSRVD0(v)                            (((v) & 0x3) << 6)
+#define BFM_ECC8_DEBUG0_RSRVD0(v)                           BM_ECC8_DEBUG0_RSRVD0
+#define BF_ECC8_DEBUG0_RSRVD0_V(e)                          BF_ECC8_DEBUG0_RSRVD0(BV_ECC8_DEBUG0_RSRVD0__##e)
+#define BFM_ECC8_DEBUG0_RSRVD0_V(v)                         BM_ECC8_DEBUG0_RSRVD0
+#define BP_ECC8_DEBUG0_DEBUG_REG_SELECT                     0
+#define BM_ECC8_DEBUG0_DEBUG_REG_SELECT                     0x3f
+#define BF_ECC8_DEBUG0_DEBUG_REG_SELECT(v)                  (((v) & 0x3f) << 0)
+#define BFM_ECC8_DEBUG0_DEBUG_REG_SELECT(v)                 BM_ECC8_DEBUG0_DEBUG_REG_SELECT
+#define BF_ECC8_DEBUG0_DEBUG_REG_SELECT_V(e)                BF_ECC8_DEBUG0_DEBUG_REG_SELECT(BV_ECC8_DEBUG0_DEBUG_REG_SELECT__##e)
+#define BFM_ECC8_DEBUG0_DEBUG_REG_SELECT_V(v)               BM_ECC8_DEBUG0_DEBUG_REG_SELECT
+
+#define HW_ECC8_DBGKESREAD              HW(ECC8_DBGKESREAD)
+#define HWA_ECC8_DBGKESREAD             (0x80008000 + 0x40)
+#define HWT_ECC8_DBGKESREAD             HWIO_32_RW
+#define HWN_ECC8_DBGKESREAD             ECC8_DBGKESREAD
+#define HWI_ECC8_DBGKESREAD             
+#define BP_ECC8_DBGKESREAD_VALUES       0
+#define BM_ECC8_DBGKESREAD_VALUES       0xffffffff
+#define BF_ECC8_DBGKESREAD_VALUES(v)    (((v) & 0xffffffff) << 0)
+#define BFM_ECC8_DBGKESREAD_VALUES(v)   BM_ECC8_DBGKESREAD_VALUES
+#define BF_ECC8_DBGKESREAD_VALUES_V(e)  BF_ECC8_DBGKESREAD_VALUES(BV_ECC8_DBGKESREAD_VALUES__##e)
+#define BFM_ECC8_DBGKESREAD_VALUES_V(v) BM_ECC8_DBGKESREAD_VALUES
+
+#define HW_ECC8_DBGCSFEREAD                 HW(ECC8_DBGCSFEREAD)
+#define HWA_ECC8_DBGCSFEREAD                (0x80008000 + 0x50)
+#define HWT_ECC8_DBGCSFEREAD                HWIO_32_RW
+#define HWN_ECC8_DBGCSFEREAD                ECC8_DBGCSFEREAD
+#define HWI_ECC8_DBGCSFEREAD                
+#define BP_ECC8_DBGCSFEREAD_VALUES          0
+#define BM_ECC8_DBGCSFEREAD_VALUES          0xffffffff
+#define BF_ECC8_DBGCSFEREAD_VALUES(v)       (((v) & 0xffffffff) << 0)
+#define BFM_ECC8_DBGCSFEREAD_VALUES(v)      BM_ECC8_DBGCSFEREAD_VALUES
+#define BF_ECC8_DBGCSFEREAD_VALUES_V(e)     BF_ECC8_DBGCSFEREAD_VALUES(BV_ECC8_DBGCSFEREAD_VALUES__##e)
+#define BFM_ECC8_DBGCSFEREAD_VALUES_V(v)    BM_ECC8_DBGCSFEREAD_VALUES
+
+#define HW_ECC8_DBGSYNDGENREAD              HW(ECC8_DBGSYNDGENREAD)
+#define HWA_ECC8_DBGSYNDGENREAD             (0x80008000 + 0x60)
+#define HWT_ECC8_DBGSYNDGENREAD             HWIO_32_RW
+#define HWN_ECC8_DBGSYNDGENREAD             ECC8_DBGSYNDGENREAD
+#define HWI_ECC8_DBGSYNDGENREAD             
+#define BP_ECC8_DBGSYNDGENREAD_VALUES       0
+#define BM_ECC8_DBGSYNDGENREAD_VALUES       0xffffffff
+#define BF_ECC8_DBGSYNDGENREAD_VALUES(v)    (((v) & 0xffffffff) << 0)
+#define BFM_ECC8_DBGSYNDGENREAD_VALUES(v)   BM_ECC8_DBGSYNDGENREAD_VALUES
+#define BF_ECC8_DBGSYNDGENREAD_VALUES_V(e)  BF_ECC8_DBGSYNDGENREAD_VALUES(BV_ECC8_DBGSYNDGENREAD_VALUES__##e)
+#define BFM_ECC8_DBGSYNDGENREAD_VALUES_V(v) BM_ECC8_DBGSYNDGENREAD_VALUES
+
+#define HW_ECC8_DBGAHBMREAD                 HW(ECC8_DBGAHBMREAD)
+#define HWA_ECC8_DBGAHBMREAD                (0x80008000 + 0x70)
+#define HWT_ECC8_DBGAHBMREAD                HWIO_32_RW
+#define HWN_ECC8_DBGAHBMREAD                ECC8_DBGAHBMREAD
+#define HWI_ECC8_DBGAHBMREAD                
+#define BP_ECC8_DBGAHBMREAD_VALUES          0
+#define BM_ECC8_DBGAHBMREAD_VALUES          0xffffffff
+#define BF_ECC8_DBGAHBMREAD_VALUES(v)       (((v) & 0xffffffff) << 0)
+#define BFM_ECC8_DBGAHBMREAD_VALUES(v)      BM_ECC8_DBGAHBMREAD_VALUES
+#define BF_ECC8_DBGAHBMREAD_VALUES_V(e)     BF_ECC8_DBGAHBMREAD_VALUES(BV_ECC8_DBGAHBMREAD_VALUES__##e)
+#define BFM_ECC8_DBGAHBMREAD_VALUES_V(v)    BM_ECC8_DBGAHBMREAD_VALUES
+
+#define HW_ECC8_BLOCKNAME               HW(ECC8_BLOCKNAME)
+#define HWA_ECC8_BLOCKNAME              (0x80008000 + 0x80)
+#define HWT_ECC8_BLOCKNAME              HWIO_32_RW
+#define HWN_ECC8_BLOCKNAME              ECC8_BLOCKNAME
+#define HWI_ECC8_BLOCKNAME              
+#define BP_ECC8_BLOCKNAME_NAME          0
+#define BM_ECC8_BLOCKNAME_NAME          0xffffffff
+#define BF_ECC8_BLOCKNAME_NAME(v)       (((v) & 0xffffffff) << 0)
+#define BFM_ECC8_BLOCKNAME_NAME(v)      BM_ECC8_BLOCKNAME_NAME
+#define BF_ECC8_BLOCKNAME_NAME_V(e)     BF_ECC8_BLOCKNAME_NAME(BV_ECC8_BLOCKNAME_NAME__##e)
+#define BFM_ECC8_BLOCKNAME_NAME_V(v)    BM_ECC8_BLOCKNAME_NAME
+
+#define HW_ECC8_VERSION             HW(ECC8_VERSION)
+#define HWA_ECC8_VERSION            (0x80008000 + 0xa0)
+#define HWT_ECC8_VERSION            HWIO_32_RW
+#define HWN_ECC8_VERSION            ECC8_VERSION
+#define HWI_ECC8_VERSION            
+#define BP_ECC8_VERSION_MAJOR       24
+#define BM_ECC8_VERSION_MAJOR       0xff000000
+#define BF_ECC8_VERSION_MAJOR(v)    (((v) & 0xff) << 24)
+#define BFM_ECC8_VERSION_MAJOR(v)   BM_ECC8_VERSION_MAJOR
+#define BF_ECC8_VERSION_MAJOR_V(e)  BF_ECC8_VERSION_MAJOR(BV_ECC8_VERSION_MAJOR__##e)
+#define BFM_ECC8_VERSION_MAJOR_V(v) BM_ECC8_VERSION_MAJOR
+#define BP_ECC8_VERSION_MINOR       16
+#define BM_ECC8_VERSION_MINOR       0xff0000
+#define BF_ECC8_VERSION_MINOR(v)    (((v) & 0xff) << 16)
+#define BFM_ECC8_VERSION_MINOR(v)   BM_ECC8_VERSION_MINOR
+#define BF_ECC8_VERSION_MINOR_V(e)  BF_ECC8_VERSION_MINOR(BV_ECC8_VERSION_MINOR__##e)
+#define BFM_ECC8_VERSION_MINOR_V(v) BM_ECC8_VERSION_MINOR
+#define BP_ECC8_VERSION_STEP        0
+#define BM_ECC8_VERSION_STEP        0xffff
+#define BF_ECC8_VERSION_STEP(v)     (((v) & 0xffff) << 0)
+#define BFM_ECC8_VERSION_STEP(v)    BM_ECC8_VERSION_STEP
+#define BF_ECC8_VERSION_STEP_V(e)   BF_ECC8_VERSION_STEP(BV_ECC8_VERSION_STEP__##e)
+#define BFM_ECC8_VERSION_STEP_V(v)  BM_ECC8_VERSION_STEP
+
+#endif /* __HEADERGEN_IMX233_ECC8_H__*/
diff --git a/firmware/target/arm/imx233/regs/imx233/emi.h b/firmware/target/arm/imx233/regs/imx233/emi.h
new file mode 100644
index 0000000000..4fe92e5459
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/imx233/emi.h
@@ -0,0 +1,454 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * imx233 version: 2.4.0
+ * imx233 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_IMX233_EMI_H__
+#define __HEADERGEN_IMX233_EMI_H__
+
+#define HW_EMI_CTRL                                 HW(EMI_CTRL)
+#define HWA_EMI_CTRL                                (0x80020000 + 0x0)
+#define HWT_EMI_CTRL                                HWIO_32_RW
+#define HWN_EMI_CTRL                                EMI_CTRL
+#define HWI_EMI_CTRL                                
+#define HW_EMI_CTRL_SET                             HW(EMI_CTRL_SET)
+#define HWA_EMI_CTRL_SET                            (HWA_EMI_CTRL + 0x4)
+#define HWT_EMI_CTRL_SET                            HWIO_32_WO
+#define HWN_EMI_CTRL_SET                            EMI_CTRL
+#define HWI_EMI_CTRL_SET                            
+#define HW_EMI_CTRL_CLR                             HW(EMI_CTRL_CLR)
+#define HWA_EMI_CTRL_CLR                            (HWA_EMI_CTRL + 0x8)
+#define HWT_EMI_CTRL_CLR                            HWIO_32_WO
+#define HWN_EMI_CTRL_CLR                            EMI_CTRL
+#define HWI_EMI_CTRL_CLR                            
+#define HW_EMI_CTRL_TOG                             HW(EMI_CTRL_TOG)
+#define HWA_EMI_CTRL_TOG                            (HWA_EMI_CTRL + 0xc)
+#define HWT_EMI_CTRL_TOG                            HWIO_32_WO
+#define HWN_EMI_CTRL_TOG                            EMI_CTRL
+#define HWI_EMI_CTRL_TOG                            
+#define BP_EMI_CTRL_SFTRST                          31
+#define BM_EMI_CTRL_SFTRST                          0x80000000
+#define BF_EMI_CTRL_SFTRST(v)                       (((v) & 0x1) << 31)
+#define BFM_EMI_CTRL_SFTRST(v)                      BM_EMI_CTRL_SFTRST
+#define BF_EMI_CTRL_SFTRST_V(e)                     BF_EMI_CTRL_SFTRST(BV_EMI_CTRL_SFTRST__##e)
+#define BFM_EMI_CTRL_SFTRST_V(v)                    BM_EMI_CTRL_SFTRST
+#define BP_EMI_CTRL_CLKGATE                         30
+#define BM_EMI_CTRL_CLKGATE                         0x40000000
+#define BF_EMI_CTRL_CLKGATE(v)                      (((v) & 0x1) << 30)
+#define BFM_EMI_CTRL_CLKGATE(v)                     BM_EMI_CTRL_CLKGATE
+#define BF_EMI_CTRL_CLKGATE_V(e)                    BF_EMI_CTRL_CLKGATE(BV_EMI_CTRL_CLKGATE__##e)
+#define BFM_EMI_CTRL_CLKGATE_V(v)                   BM_EMI_CTRL_CLKGATE
+#define BP_EMI_CTRL_TRAP_SR                         29
+#define BM_EMI_CTRL_TRAP_SR                         0x20000000
+#define BF_EMI_CTRL_TRAP_SR(v)                      (((v) & 0x1) << 29)
+#define BFM_EMI_CTRL_TRAP_SR(v)                     BM_EMI_CTRL_TRAP_SR
+#define BF_EMI_CTRL_TRAP_SR_V(e)                    BF_EMI_CTRL_TRAP_SR(BV_EMI_CTRL_TRAP_SR__##e)
+#define BFM_EMI_CTRL_TRAP_SR_V(v)                   BM_EMI_CTRL_TRAP_SR
+#define BP_EMI_CTRL_TRAP_INIT                       28
+#define BM_EMI_CTRL_TRAP_INIT                       0x10000000
+#define BF_EMI_CTRL_TRAP_INIT(v)                    (((v) & 0x1) << 28)
+#define BFM_EMI_CTRL_TRAP_INIT(v)                   BM_EMI_CTRL_TRAP_INIT
+#define BF_EMI_CTRL_TRAP_INIT_V(e)                  BF_EMI_CTRL_TRAP_INIT(BV_EMI_CTRL_TRAP_INIT__##e)
+#define BFM_EMI_CTRL_TRAP_INIT_V(v)                 BM_EMI_CTRL_TRAP_INIT
+#define BP_EMI_CTRL_AXI_DEPTH                       26
+#define BM_EMI_CTRL_AXI_DEPTH                       0xc000000
+#define BV_EMI_CTRL_AXI_DEPTH__ONE                  0x0
+#define BV_EMI_CTRL_AXI_DEPTH__TWO                  0x1
+#define BV_EMI_CTRL_AXI_DEPTH__THREE                0x2
+#define BV_EMI_CTRL_AXI_DEPTH__FOUR                 0x3
+#define BF_EMI_CTRL_AXI_DEPTH(v)                    (((v) & 0x3) << 26)
+#define BFM_EMI_CTRL_AXI_DEPTH(v)                   BM_EMI_CTRL_AXI_DEPTH
+#define BF_EMI_CTRL_AXI_DEPTH_V(e)                  BF_EMI_CTRL_AXI_DEPTH(BV_EMI_CTRL_AXI_DEPTH__##e)
+#define BFM_EMI_CTRL_AXI_DEPTH_V(v)                 BM_EMI_CTRL_AXI_DEPTH
+#define BP_EMI_CTRL_DLL_SHIFT_RESET                 25
+#define BM_EMI_CTRL_DLL_SHIFT_RESET                 0x2000000
+#define BF_EMI_CTRL_DLL_SHIFT_RESET(v)              (((v) & 0x1) << 25)
+#define BFM_EMI_CTRL_DLL_SHIFT_RESET(v)             BM_EMI_CTRL_DLL_SHIFT_RESET
+#define BF_EMI_CTRL_DLL_SHIFT_RESET_V(e)            BF_EMI_CTRL_DLL_SHIFT_RESET(BV_EMI_CTRL_DLL_SHIFT_RESET__##e)
+#define BFM_EMI_CTRL_DLL_SHIFT_RESET_V(v)           BM_EMI_CTRL_DLL_SHIFT_RESET
+#define BP_EMI_CTRL_DLL_RESET                       24
+#define BM_EMI_CTRL_DLL_RESET                       0x1000000
+#define BF_EMI_CTRL_DLL_RESET(v)                    (((v) & 0x1) << 24)
+#define BFM_EMI_CTRL_DLL_RESET(v)                   BM_EMI_CTRL_DLL_RESET
+#define BF_EMI_CTRL_DLL_RESET_V(e)                  BF_EMI_CTRL_DLL_RESET(BV_EMI_CTRL_DLL_RESET__##e)
+#define BFM_EMI_CTRL_DLL_RESET_V(v)                 BM_EMI_CTRL_DLL_RESET
+#define BP_EMI_CTRL_ARB_MODE                        22
+#define BM_EMI_CTRL_ARB_MODE                        0xc00000
+#define BV_EMI_CTRL_ARB_MODE__TIMESTAMP             0x0
+#define BV_EMI_CTRL_ARB_MODE__WRITE_HYBRID          0x1
+#define BV_EMI_CTRL_ARB_MODE__PORT_PRIORITY         0x2
+#define BF_EMI_CTRL_ARB_MODE(v)                     (((v) & 0x3) << 22)
+#define BFM_EMI_CTRL_ARB_MODE(v)                    BM_EMI_CTRL_ARB_MODE
+#define BF_EMI_CTRL_ARB_MODE_V(e)                   BF_EMI_CTRL_ARB_MODE(BV_EMI_CTRL_ARB_MODE__##e)
+#define BFM_EMI_CTRL_ARB_MODE_V(v)                  BM_EMI_CTRL_ARB_MODE
+#define BP_EMI_CTRL_RSVD3                           21
+#define BM_EMI_CTRL_RSVD3                           0x200000
+#define BF_EMI_CTRL_RSVD3(v)                        (((v) & 0x1) << 21)
+#define BFM_EMI_CTRL_RSVD3(v)                       BM_EMI_CTRL_RSVD3
+#define BF_EMI_CTRL_RSVD3_V(e)                      BF_EMI_CTRL_RSVD3(BV_EMI_CTRL_RSVD3__##e)
+#define BFM_EMI_CTRL_RSVD3_V(v)                     BM_EMI_CTRL_RSVD3
+#define BP_EMI_CTRL_PORT_PRIORITY_ORDER             16
+#define BM_EMI_CTRL_PORT_PRIORITY_ORDER             0x1f0000
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT0123   0x0
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT0312   0x1
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT0231   0x2
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT0321   0x3
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT0213   0x4
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT0132   0x5
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT1023   0x6
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT1302   0x7
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT1230   0x8
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT1320   0x9
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT1203   0xa
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT1032   0xb
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT2013   0xc
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT2301   0xd
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT2130   0xe
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT2310   0xf
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT2103   0x10
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT2031   0x11
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT3012   0x12
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT3201   0x13
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT3120   0x14
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT3210   0x15
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT3102   0x16
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT3021   0x17
+#define BF_EMI_CTRL_PORT_PRIORITY_ORDER(v)          (((v) & 0x1f) << 16)
+#define BFM_EMI_CTRL_PORT_PRIORITY_ORDER(v)         BM_EMI_CTRL_PORT_PRIORITY_ORDER
+#define BF_EMI_CTRL_PORT_PRIORITY_ORDER_V(e)        BF_EMI_CTRL_PORT_PRIORITY_ORDER(BV_EMI_CTRL_PORT_PRIORITY_ORDER__##e)
+#define BFM_EMI_CTRL_PORT_PRIORITY_ORDER_V(v)       BM_EMI_CTRL_PORT_PRIORITY_ORDER
+#define BP_EMI_CTRL_RSVD2                           15
+#define BM_EMI_CTRL_RSVD2                           0x8000
+#define BF_EMI_CTRL_RSVD2(v)                        (((v) & 0x1) << 15)
+#define BFM_EMI_CTRL_RSVD2(v)                       BM_EMI_CTRL_RSVD2
+#define BF_EMI_CTRL_RSVD2_V(e)                      BF_EMI_CTRL_RSVD2(BV_EMI_CTRL_RSVD2__##e)
+#define BFM_EMI_CTRL_RSVD2_V(v)                     BM_EMI_CTRL_RSVD2
+#define BP_EMI_CTRL_PRIORITY_WRITE_ITER             12
+#define BM_EMI_CTRL_PRIORITY_WRITE_ITER             0x7000
+#define BF_EMI_CTRL_PRIORITY_WRITE_ITER(v)          (((v) & 0x7) << 12)
+#define BFM_EMI_CTRL_PRIORITY_WRITE_ITER(v)         BM_EMI_CTRL_PRIORITY_WRITE_ITER
+#define BF_EMI_CTRL_PRIORITY_WRITE_ITER_V(e)        BF_EMI_CTRL_PRIORITY_WRITE_ITER(BV_EMI_CTRL_PRIORITY_WRITE_ITER__##e)
+#define BFM_EMI_CTRL_PRIORITY_WRITE_ITER_V(v)       BM_EMI_CTRL_PRIORITY_WRITE_ITER
+#define BP_EMI_CTRL_RSVD1                           11
+#define BM_EMI_CTRL_RSVD1                           0x800
+#define BF_EMI_CTRL_RSVD1(v)                        (((v) & 0x1) << 11)
+#define BFM_EMI_CTRL_RSVD1(v)                       BM_EMI_CTRL_RSVD1
+#define BF_EMI_CTRL_RSVD1_V(e)                      BF_EMI_CTRL_RSVD1(BV_EMI_CTRL_RSVD1__##e)
+#define BFM_EMI_CTRL_RSVD1_V(v)                     BM_EMI_CTRL_RSVD1
+#define BP_EMI_CTRL_HIGH_PRIORITY_WRITE             8
+#define BM_EMI_CTRL_HIGH_PRIORITY_WRITE             0x700
+#define BF_EMI_CTRL_HIGH_PRIORITY_WRITE(v)          (((v) & 0x7) << 8)
+#define BFM_EMI_CTRL_HIGH_PRIORITY_WRITE(v)         BM_EMI_CTRL_HIGH_PRIORITY_WRITE
+#define BF_EMI_CTRL_HIGH_PRIORITY_WRITE_V(e)        BF_EMI_CTRL_HIGH_PRIORITY_WRITE(BV_EMI_CTRL_HIGH_PRIORITY_WRITE__##e)
+#define BFM_EMI_CTRL_HIGH_PRIORITY_WRITE_V(v)       BM_EMI_CTRL_HIGH_PRIORITY_WRITE
+#define BP_EMI_CTRL_RSVD0                           7
+#define BM_EMI_CTRL_RSVD0                           0x80
+#define BF_EMI_CTRL_RSVD0(v)                        (((v) & 0x1) << 7)
+#define BFM_EMI_CTRL_RSVD0(v)                       BM_EMI_CTRL_RSVD0
+#define BF_EMI_CTRL_RSVD0_V(e)                      BF_EMI_CTRL_RSVD0(BV_EMI_CTRL_RSVD0__##e)
+#define BFM_EMI_CTRL_RSVD0_V(v)                     BM_EMI_CTRL_RSVD0
+#define BP_EMI_CTRL_MEM_WIDTH                       6
+#define BM_EMI_CTRL_MEM_WIDTH                       0x40
+#define BF_EMI_CTRL_MEM_WIDTH(v)                    (((v) & 0x1) << 6)
+#define BFM_EMI_CTRL_MEM_WIDTH(v)                   BM_EMI_CTRL_MEM_WIDTH
+#define BF_EMI_CTRL_MEM_WIDTH_V(e)                  BF_EMI_CTRL_MEM_WIDTH(BV_EMI_CTRL_MEM_WIDTH__##e)
+#define BFM_EMI_CTRL_MEM_WIDTH_V(v)                 BM_EMI_CTRL_MEM_WIDTH
+#define BP_EMI_CTRL_WRITE_PROTECT                   5
+#define BM_EMI_CTRL_WRITE_PROTECT                   0x20
+#define BF_EMI_CTRL_WRITE_PROTECT(v)                (((v) & 0x1) << 5)
+#define BFM_EMI_CTRL_WRITE_PROTECT(v)               BM_EMI_CTRL_WRITE_PROTECT
+#define BF_EMI_CTRL_WRITE_PROTECT_V(e)              BF_EMI_CTRL_WRITE_PROTECT(BV_EMI_CTRL_WRITE_PROTECT__##e)
+#define BFM_EMI_CTRL_WRITE_PROTECT_V(v)             BM_EMI_CTRL_WRITE_PROTECT
+#define BP_EMI_CTRL_RESET_OUT                       4
+#define BM_EMI_CTRL_RESET_OUT                       0x10
+#define BF_EMI_CTRL_RESET_OUT(v)                    (((v) & 0x1) << 4)
+#define BFM_EMI_CTRL_RESET_OUT(v)                   BM_EMI_CTRL_RESET_OUT
+#define BF_EMI_CTRL_RESET_OUT_V(e)                  BF_EMI_CTRL_RESET_OUT(BV_EMI_CTRL_RESET_OUT__##e)
+#define BFM_EMI_CTRL_RESET_OUT_V(v)                 BM_EMI_CTRL_RESET_OUT
+#define BP_EMI_CTRL_CE_SELECT                       0
+#define BM_EMI_CTRL_CE_SELECT                       0xf
+#define BV_EMI_CTRL_CE_SELECT__NONE                 0x0
+#define BV_EMI_CTRL_CE_SELECT__CE0                  0x1
+#define BV_EMI_CTRL_CE_SELECT__CE1                  0x2
+#define BV_EMI_CTRL_CE_SELECT__CE2                  0x4
+#define BV_EMI_CTRL_CE_SELECT__CE3                  0x8
+#define BF_EMI_CTRL_CE_SELECT(v)                    (((v) & 0xf) << 0)
+#define BFM_EMI_CTRL_CE_SELECT(v)                   BM_EMI_CTRL_CE_SELECT
+#define BF_EMI_CTRL_CE_SELECT_V(e)                  BF_EMI_CTRL_CE_SELECT(BV_EMI_CTRL_CE_SELECT__##e)
+#define BFM_EMI_CTRL_CE_SELECT_V(v)                 BM_EMI_CTRL_CE_SELECT
+
+#define HW_EMI_STAT                             HW(EMI_STAT)
+#define HWA_EMI_STAT                            (0x80020000 + 0x10)
+#define HWT_EMI_STAT                            HWIO_32_RW
+#define HWN_EMI_STAT                            EMI_STAT
+#define HWI_EMI_STAT                            
+#define BP_EMI_STAT_DRAM_PRESENT                31
+#define BM_EMI_STAT_DRAM_PRESENT                0x80000000
+#define BF_EMI_STAT_DRAM_PRESENT(v)             (((v) & 0x1) << 31)
+#define BFM_EMI_STAT_DRAM_PRESENT(v)            BM_EMI_STAT_DRAM_PRESENT
+#define BF_EMI_STAT_DRAM_PRESENT_V(e)           BF_EMI_STAT_DRAM_PRESENT(BV_EMI_STAT_DRAM_PRESENT__##e)
+#define BFM_EMI_STAT_DRAM_PRESENT_V(v)          BM_EMI_STAT_DRAM_PRESENT
+#define BP_EMI_STAT_NOR_PRESENT                 30
+#define BM_EMI_STAT_NOR_PRESENT                 0x40000000
+#define BF_EMI_STAT_NOR_PRESENT(v)              (((v) & 0x1) << 30)
+#define BFM_EMI_STAT_NOR_PRESENT(v)             BM_EMI_STAT_NOR_PRESENT
+#define BF_EMI_STAT_NOR_PRESENT_V(e)            BF_EMI_STAT_NOR_PRESENT(BV_EMI_STAT_NOR_PRESENT__##e)
+#define BFM_EMI_STAT_NOR_PRESENT_V(v)           BM_EMI_STAT_NOR_PRESENT
+#define BP_EMI_STAT_LARGE_DRAM_ENABLED          29
+#define BM_EMI_STAT_LARGE_DRAM_ENABLED          0x20000000
+#define BF_EMI_STAT_LARGE_DRAM_ENABLED(v)       (((v) & 0x1) << 29)
+#define BFM_EMI_STAT_LARGE_DRAM_ENABLED(v)      BM_EMI_STAT_LARGE_DRAM_ENABLED
+#define BF_EMI_STAT_LARGE_DRAM_ENABLED_V(e)     BF_EMI_STAT_LARGE_DRAM_ENABLED(BV_EMI_STAT_LARGE_DRAM_ENABLED__##e)
+#define BFM_EMI_STAT_LARGE_DRAM_ENABLED_V(v)    BM_EMI_STAT_LARGE_DRAM_ENABLED
+#define BP_EMI_STAT_RSVD0                       2
+#define BM_EMI_STAT_RSVD0                       0x1ffffffc
+#define BF_EMI_STAT_RSVD0(v)                    (((v) & 0x7ffffff) << 2)
+#define BFM_EMI_STAT_RSVD0(v)                   BM_EMI_STAT_RSVD0
+#define BF_EMI_STAT_RSVD0_V(e)                  BF_EMI_STAT_RSVD0(BV_EMI_STAT_RSVD0__##e)
+#define BFM_EMI_STAT_RSVD0_V(v)                 BM_EMI_STAT_RSVD0
+#define BP_EMI_STAT_DRAM_HALTED                 1
+#define BM_EMI_STAT_DRAM_HALTED                 0x2
+#define BV_EMI_STAT_DRAM_HALTED__NOT_HALTED     0x0
+#define BV_EMI_STAT_DRAM_HALTED__HALTED         0x1
+#define BF_EMI_STAT_DRAM_HALTED(v)              (((v) & 0x1) << 1)
+#define BFM_EMI_STAT_DRAM_HALTED(v)             BM_EMI_STAT_DRAM_HALTED
+#define BF_EMI_STAT_DRAM_HALTED_V(e)            BF_EMI_STAT_DRAM_HALTED(BV_EMI_STAT_DRAM_HALTED__##e)
+#define BFM_EMI_STAT_DRAM_HALTED_V(v)           BM_EMI_STAT_DRAM_HALTED
+#define BP_EMI_STAT_NOR_BUSY                    0
+#define BM_EMI_STAT_NOR_BUSY                    0x1
+#define BV_EMI_STAT_NOR_BUSY__NOT_BUSY          0x0
+#define BV_EMI_STAT_NOR_BUSY__BUSY              0x1
+#define BF_EMI_STAT_NOR_BUSY(v)                 (((v) & 0x1) << 0)
+#define BFM_EMI_STAT_NOR_BUSY(v)                BM_EMI_STAT_NOR_BUSY
+#define BF_EMI_STAT_NOR_BUSY_V(e)               BF_EMI_STAT_NOR_BUSY(BV_EMI_STAT_NOR_BUSY__##e)
+#define BFM_EMI_STAT_NOR_BUSY_V(v)              BM_EMI_STAT_NOR_BUSY
+
+#define HW_EMI_TIME             HW(EMI_TIME)
+#define HWA_EMI_TIME            (0x80020000 + 0x20)
+#define HWT_EMI_TIME            HWIO_32_RW
+#define HWN_EMI_TIME            EMI_TIME
+#define HWI_EMI_TIME            
+#define HW_EMI_TIME_SET         HW(EMI_TIME_SET)
+#define HWA_EMI_TIME_SET        (HWA_EMI_TIME + 0x4)
+#define HWT_EMI_TIME_SET        HWIO_32_WO
+#define HWN_EMI_TIME_SET        EMI_TIME
+#define HWI_EMI_TIME_SET        
+#define HW_EMI_TIME_CLR         HW(EMI_TIME_CLR)
+#define HWA_EMI_TIME_CLR        (HWA_EMI_TIME + 0x8)
+#define HWT_EMI_TIME_CLR        HWIO_32_WO
+#define HWN_EMI_TIME_CLR        EMI_TIME
+#define HWI_EMI_TIME_CLR        
+#define HW_EMI_TIME_TOG         HW(EMI_TIME_TOG)
+#define HWA_EMI_TIME_TOG        (HWA_EMI_TIME + 0xc)
+#define HWT_EMI_TIME_TOG        HWIO_32_WO
+#define HWN_EMI_TIME_TOG        EMI_TIME
+#define HWI_EMI_TIME_TOG        
+#define BP_EMI_TIME_RSVD4       28
+#define BM_EMI_TIME_RSVD4       0xf0000000
+#define BF_EMI_TIME_RSVD4(v)    (((v) & 0xf) << 28)
+#define BFM_EMI_TIME_RSVD4(v)   BM_EMI_TIME_RSVD4
+#define BF_EMI_TIME_RSVD4_V(e)  BF_EMI_TIME_RSVD4(BV_EMI_TIME_RSVD4__##e)
+#define BFM_EMI_TIME_RSVD4_V(v) BM_EMI_TIME_RSVD4
+#define BP_EMI_TIME_THZ         24
+#define BM_EMI_TIME_THZ         0xf000000
+#define BF_EMI_TIME_THZ(v)      (((v) & 0xf) << 24)
+#define BFM_EMI_TIME_THZ(v)     BM_EMI_TIME_THZ
+#define BF_EMI_TIME_THZ_V(e)    BF_EMI_TIME_THZ(BV_EMI_TIME_THZ__##e)
+#define BFM_EMI_TIME_THZ_V(v)   BM_EMI_TIME_THZ
+#define BP_EMI_TIME_RSVD2       20
+#define BM_EMI_TIME_RSVD2       0xf00000
+#define BF_EMI_TIME_RSVD2(v)    (((v) & 0xf) << 20)
+#define BFM_EMI_TIME_RSVD2(v)   BM_EMI_TIME_RSVD2
+#define BF_EMI_TIME_RSVD2_V(e)  BF_EMI_TIME_RSVD2(BV_EMI_TIME_RSVD2__##e)
+#define BFM_EMI_TIME_RSVD2_V(v) BM_EMI_TIME_RSVD2
+#define BP_EMI_TIME_TDH         16
+#define BM_EMI_TIME_TDH         0xf0000
+#define BF_EMI_TIME_TDH(v)      (((v) & 0xf) << 16)
+#define BFM_EMI_TIME_TDH(v)     BM_EMI_TIME_TDH
+#define BF_EMI_TIME_TDH_V(e)    BF_EMI_TIME_TDH(BV_EMI_TIME_TDH__##e)
+#define BFM_EMI_TIME_TDH_V(v)   BM_EMI_TIME_TDH
+#define BP_EMI_TIME_RSVD1       13
+#define BM_EMI_TIME_RSVD1       0xe000
+#define BF_EMI_TIME_RSVD1(v)    (((v) & 0x7) << 13)
+#define BFM_EMI_TIME_RSVD1(v)   BM_EMI_TIME_RSVD1
+#define BF_EMI_TIME_RSVD1_V(e)  BF_EMI_TIME_RSVD1(BV_EMI_TIME_RSVD1__##e)
+#define BFM_EMI_TIME_RSVD1_V(v) BM_EMI_TIME_RSVD1
+#define BP_EMI_TIME_TDS         8
+#define BM_EMI_TIME_TDS         0x1f00
+#define BF_EMI_TIME_TDS(v)      (((v) & 0x1f) << 8)
+#define BFM_EMI_TIME_TDS(v)     BM_EMI_TIME_TDS
+#define BF_EMI_TIME_TDS_V(e)    BF_EMI_TIME_TDS(BV_EMI_TIME_TDS__##e)
+#define BFM_EMI_TIME_TDS_V(v)   BM_EMI_TIME_TDS
+#define BP_EMI_TIME_RSVD0       4
+#define BM_EMI_TIME_RSVD0       0xf0
+#define BF_EMI_TIME_RSVD0(v)    (((v) & 0xf) << 4)
+#define BFM_EMI_TIME_RSVD0(v)   BM_EMI_TIME_RSVD0
+#define BF_EMI_TIME_RSVD0_V(e)  BF_EMI_TIME_RSVD0(BV_EMI_TIME_RSVD0__##e)
+#define BFM_EMI_TIME_RSVD0_V(v) BM_EMI_TIME_RSVD0
+#define BP_EMI_TIME_TAS         0
+#define BM_EMI_TIME_TAS         0xf
+#define BF_EMI_TIME_TAS(v)      (((v) & 0xf) << 0)
+#define BFM_EMI_TIME_TAS(v)     BM_EMI_TIME_TAS
+#define BF_EMI_TIME_TAS_V(e)    BF_EMI_TIME_TAS(BV_EMI_TIME_TAS__##e)
+#define BFM_EMI_TIME_TAS_V(v)   BM_EMI_TIME_TAS
+
+#define HW_EMI_DDR_TEST_MODE_CSR                HW(EMI_DDR_TEST_MODE_CSR)
+#define HWA_EMI_DDR_TEST_MODE_CSR               (0x80020000 + 0x30)
+#define HWT_EMI_DDR_TEST_MODE_CSR               HWIO_32_RW
+#define HWN_EMI_DDR_TEST_MODE_CSR               EMI_DDR_TEST_MODE_CSR
+#define HWI_EMI_DDR_TEST_MODE_CSR               
+#define HW_EMI_DDR_TEST_MODE_CSR_SET            HW(EMI_DDR_TEST_MODE_CSR_SET)
+#define HWA_EMI_DDR_TEST_MODE_CSR_SET           (HWA_EMI_DDR_TEST_MODE_CSR + 0x4)
+#define HWT_EMI_DDR_TEST_MODE_CSR_SET           HWIO_32_WO
+#define HWN_EMI_DDR_TEST_MODE_CSR_SET           EMI_DDR_TEST_MODE_CSR
+#define HWI_EMI_DDR_TEST_MODE_CSR_SET           
+#define HW_EMI_DDR_TEST_MODE_CSR_CLR            HW(EMI_DDR_TEST_MODE_CSR_CLR)
+#define HWA_EMI_DDR_TEST_MODE_CSR_CLR           (HWA_EMI_DDR_TEST_MODE_CSR + 0x8)
+#define HWT_EMI_DDR_TEST_MODE_CSR_CLR           HWIO_32_WO
+#define HWN_EMI_DDR_TEST_MODE_CSR_CLR           EMI_DDR_TEST_MODE_CSR
+#define HWI_EMI_DDR_TEST_MODE_CSR_CLR           
+#define HW_EMI_DDR_TEST_MODE_CSR_TOG            HW(EMI_DDR_TEST_MODE_CSR_TOG)
+#define HWA_EMI_DDR_TEST_MODE_CSR_TOG           (HWA_EMI_DDR_TEST_MODE_CSR + 0xc)
+#define HWT_EMI_DDR_TEST_MODE_CSR_TOG           HWIO_32_WO
+#define HWN_EMI_DDR_TEST_MODE_CSR_TOG           EMI_DDR_TEST_MODE_CSR
+#define HWI_EMI_DDR_TEST_MODE_CSR_TOG           
+#define BP_EMI_DDR_TEST_MODE_CSR_RSVD1          2
+#define BM_EMI_DDR_TEST_MODE_CSR_RSVD1          0xfffffffc
+#define BF_EMI_DDR_TEST_MODE_CSR_RSVD1(v)       (((v) & 0x3fffffff) << 2)
+#define BFM_EMI_DDR_TEST_MODE_CSR_RSVD1(v)      BM_EMI_DDR_TEST_MODE_CSR_RSVD1
+#define BF_EMI_DDR_TEST_MODE_CSR_RSVD1_V(e)     BF_EMI_DDR_TEST_MODE_CSR_RSVD1(BV_EMI_DDR_TEST_MODE_CSR_RSVD1__##e)
+#define BFM_EMI_DDR_TEST_MODE_CSR_RSVD1_V(v)    BM_EMI_DDR_TEST_MODE_CSR_RSVD1
+#define BP_EMI_DDR_TEST_MODE_CSR_DONE           1
+#define BM_EMI_DDR_TEST_MODE_CSR_DONE           0x2
+#define BF_EMI_DDR_TEST_MODE_CSR_DONE(v)        (((v) & 0x1) << 1)
+#define BFM_EMI_DDR_TEST_MODE_CSR_DONE(v)       BM_EMI_DDR_TEST_MODE_CSR_DONE
+#define BF_EMI_DDR_TEST_MODE_CSR_DONE_V(e)      BF_EMI_DDR_TEST_MODE_CSR_DONE(BV_EMI_DDR_TEST_MODE_CSR_DONE__##e)
+#define BFM_EMI_DDR_TEST_MODE_CSR_DONE_V(v)     BM_EMI_DDR_TEST_MODE_CSR_DONE
+#define BP_EMI_DDR_TEST_MODE_CSR_START          0
+#define BM_EMI_DDR_TEST_MODE_CSR_START          0x1
+#define BF_EMI_DDR_TEST_MODE_CSR_START(v)       (((v) & 0x1) << 0)
+#define BFM_EMI_DDR_TEST_MODE_CSR_START(v)      BM_EMI_DDR_TEST_MODE_CSR_START
+#define BF_EMI_DDR_TEST_MODE_CSR_START_V(e)     BF_EMI_DDR_TEST_MODE_CSR_START(BV_EMI_DDR_TEST_MODE_CSR_START__##e)
+#define BFM_EMI_DDR_TEST_MODE_CSR_START_V(v)    BM_EMI_DDR_TEST_MODE_CSR_START
+
+#define HW_EMI_DEBUG                    HW(EMI_DEBUG)
+#define HWA_EMI_DEBUG                   (0x80020000 + 0x80)
+#define HWT_EMI_DEBUG                   HWIO_32_RW
+#define HWN_EMI_DEBUG                   EMI_DEBUG
+#define HWI_EMI_DEBUG                   
+#define BP_EMI_DEBUG_RSVD1              4
+#define BM_EMI_DEBUG_RSVD1              0xfffffff0
+#define BF_EMI_DEBUG_RSVD1(v)           (((v) & 0xfffffff) << 4)
+#define BFM_EMI_DEBUG_RSVD1(v)          BM_EMI_DEBUG_RSVD1
+#define BF_EMI_DEBUG_RSVD1_V(e)         BF_EMI_DEBUG_RSVD1(BV_EMI_DEBUG_RSVD1__##e)
+#define BFM_EMI_DEBUG_RSVD1_V(v)        BM_EMI_DEBUG_RSVD1
+#define BP_EMI_DEBUG_NOR_STATE          0
+#define BM_EMI_DEBUG_NOR_STATE          0xf
+#define BF_EMI_DEBUG_NOR_STATE(v)       (((v) & 0xf) << 0)
+#define BFM_EMI_DEBUG_NOR_STATE(v)      BM_EMI_DEBUG_NOR_STATE
+#define BF_EMI_DEBUG_NOR_STATE_V(e)     BF_EMI_DEBUG_NOR_STATE(BV_EMI_DEBUG_NOR_STATE__##e)
+#define BFM_EMI_DEBUG_NOR_STATE_V(v)    BM_EMI_DEBUG_NOR_STATE
+
+#define HW_EMI_DDR_TEST_MODE_STATUS0                HW(EMI_DDR_TEST_MODE_STATUS0)
+#define HWA_EMI_DDR_TEST_MODE_STATUS0               (0x80020000 + 0x90)
+#define HWT_EMI_DDR_TEST_MODE_STATUS0               HWIO_32_RW
+#define HWN_EMI_DDR_TEST_MODE_STATUS0               EMI_DDR_TEST_MODE_STATUS0
+#define HWI_EMI_DDR_TEST_MODE_STATUS0               
+#define BP_EMI_DDR_TEST_MODE_STATUS0_RSVD1          13
+#define BM_EMI_DDR_TEST_MODE_STATUS0_RSVD1          0xffffe000
+#define BF_EMI_DDR_TEST_MODE_STATUS0_RSVD1(v)       (((v) & 0x7ffff) << 13)
+#define BFM_EMI_DDR_TEST_MODE_STATUS0_RSVD1(v)      BM_EMI_DDR_TEST_MODE_STATUS0_RSVD1
+#define BF_EMI_DDR_TEST_MODE_STATUS0_RSVD1_V(e)     BF_EMI_DDR_TEST_MODE_STATUS0_RSVD1(BV_EMI_DDR_TEST_MODE_STATUS0_RSVD1__##e)
+#define BFM_EMI_DDR_TEST_MODE_STATUS0_RSVD1_V(v)    BM_EMI_DDR_TEST_MODE_STATUS0_RSVD1
+#define BP_EMI_DDR_TEST_MODE_STATUS0_ADDR0          0
+#define BM_EMI_DDR_TEST_MODE_STATUS0_ADDR0          0x1fff
+#define BF_EMI_DDR_TEST_MODE_STATUS0_ADDR0(v)       (((v) & 0x1fff) << 0)
+#define BFM_EMI_DDR_TEST_MODE_STATUS0_ADDR0(v)      BM_EMI_DDR_TEST_MODE_STATUS0_ADDR0
+#define BF_EMI_DDR_TEST_MODE_STATUS0_ADDR0_V(e)     BF_EMI_DDR_TEST_MODE_STATUS0_ADDR0(BV_EMI_DDR_TEST_MODE_STATUS0_ADDR0__##e)
+#define BFM_EMI_DDR_TEST_MODE_STATUS0_ADDR0_V(v)    BM_EMI_DDR_TEST_MODE_STATUS0_ADDR0
+
+#define HW_EMI_DDR_TEST_MODE_STATUS1                HW(EMI_DDR_TEST_MODE_STATUS1)
+#define HWA_EMI_DDR_TEST_MODE_STATUS1               (0x80020000 + 0xa0)
+#define HWT_EMI_DDR_TEST_MODE_STATUS1               HWIO_32_RW
+#define HWN_EMI_DDR_TEST_MODE_STATUS1               EMI_DDR_TEST_MODE_STATUS1
+#define HWI_EMI_DDR_TEST_MODE_STATUS1               
+#define BP_EMI_DDR_TEST_MODE_STATUS1_RSVD1          13
+#define BM_EMI_DDR_TEST_MODE_STATUS1_RSVD1          0xffffe000
+#define BF_EMI_DDR_TEST_MODE_STATUS1_RSVD1(v)       (((v) & 0x7ffff) << 13)
+#define BFM_EMI_DDR_TEST_MODE_STATUS1_RSVD1(v)      BM_EMI_DDR_TEST_MODE_STATUS1_RSVD1
+#define BF_EMI_DDR_TEST_MODE_STATUS1_RSVD1_V(e)     BF_EMI_DDR_TEST_MODE_STATUS1_RSVD1(BV_EMI_DDR_TEST_MODE_STATUS1_RSVD1__##e)
+#define BFM_EMI_DDR_TEST_MODE_STATUS1_RSVD1_V(v)    BM_EMI_DDR_TEST_MODE_STATUS1_RSVD1
+#define BP_EMI_DDR_TEST_MODE_STATUS1_ADDR1          0
+#define BM_EMI_DDR_TEST_MODE_STATUS1_ADDR1          0x1fff
+#define BF_EMI_DDR_TEST_MODE_STATUS1_ADDR1(v)       (((v) & 0x1fff) << 0)
+#define BFM_EMI_DDR_TEST_MODE_STATUS1_ADDR1(v)      BM_EMI_DDR_TEST_MODE_STATUS1_ADDR1
+#define BF_EMI_DDR_TEST_MODE_STATUS1_ADDR1_V(e)     BF_EMI_DDR_TEST_MODE_STATUS1_ADDR1(BV_EMI_DDR_TEST_MODE_STATUS1_ADDR1__##e)
+#define BFM_EMI_DDR_TEST_MODE_STATUS1_ADDR1_V(v)    BM_EMI_DDR_TEST_MODE_STATUS1_ADDR1
+
+#define HW_EMI_DDR_TEST_MODE_STATUS2                HW(EMI_DDR_TEST_MODE_STATUS2)
+#define HWA_EMI_DDR_TEST_MODE_STATUS2               (0x80020000 + 0xb0)
+#define HWT_EMI_DDR_TEST_MODE_STATUS2               HWIO_32_RW
+#define HWN_EMI_DDR_TEST_MODE_STATUS2               EMI_DDR_TEST_MODE_STATUS2
+#define HWI_EMI_DDR_TEST_MODE_STATUS2               
+#define BP_EMI_DDR_TEST_MODE_STATUS2_DATA0          0
+#define BM_EMI_DDR_TEST_MODE_STATUS2_DATA0          0xffffffff
+#define BF_EMI_DDR_TEST_MODE_STATUS2_DATA0(v)       (((v) & 0xffffffff) << 0)
+#define BFM_EMI_DDR_TEST_MODE_STATUS2_DATA0(v)      BM_EMI_DDR_TEST_MODE_STATUS2_DATA0
+#define BF_EMI_DDR_TEST_MODE_STATUS2_DATA0_V(e)     BF_EMI_DDR_TEST_MODE_STATUS2_DATA0(BV_EMI_DDR_TEST_MODE_STATUS2_DATA0__##e)
+#define BFM_EMI_DDR_TEST_MODE_STATUS2_DATA0_V(v)    BM_EMI_DDR_TEST_MODE_STATUS2_DATA0
+
+#define HW_EMI_DDR_TEST_MODE_STATUS3                HW(EMI_DDR_TEST_MODE_STATUS3)
+#define HWA_EMI_DDR_TEST_MODE_STATUS3               (0x80020000 + 0xc0)
+#define HWT_EMI_DDR_TEST_MODE_STATUS3               HWIO_32_RW
+#define HWN_EMI_DDR_TEST_MODE_STATUS3               EMI_DDR_TEST_MODE_STATUS3
+#define HWI_EMI_DDR_TEST_MODE_STATUS3               
+#define BP_EMI_DDR_TEST_MODE_STATUS3_DATA1          0
+#define BM_EMI_DDR_TEST_MODE_STATUS3_DATA1          0xffffffff
+#define BF_EMI_DDR_TEST_MODE_STATUS3_DATA1(v)       (((v) & 0xffffffff) << 0)
+#define BFM_EMI_DDR_TEST_MODE_STATUS3_DATA1(v)      BM_EMI_DDR_TEST_MODE_STATUS3_DATA1
+#define BF_EMI_DDR_TEST_MODE_STATUS3_DATA1_V(e)     BF_EMI_DDR_TEST_MODE_STATUS3_DATA1(BV_EMI_DDR_TEST_MODE_STATUS3_DATA1__##e)
+#define BFM_EMI_DDR_TEST_MODE_STATUS3_DATA1_V(v)    BM_EMI_DDR_TEST_MODE_STATUS3_DATA1
+
+#define HW_EMI_VERSION              HW(EMI_VERSION)
+#define HWA_EMI_VERSION             (0x80020000 + 0xf0)
+#define HWT_EMI_VERSION             HWIO_32_RW
+#define HWN_EMI_VERSION             EMI_VERSION
+#define HWI_EMI_VERSION             
+#define BP_EMI_VERSION_MAJOR        24
+#define BM_EMI_VERSION_MAJOR        0xff000000
+#define BF_EMI_VERSION_MAJOR(v)     (((v) & 0xff) << 24)
+#define BFM_EMI_VERSION_MAJOR(v)    BM_EMI_VERSION_MAJOR
+#define BF_EMI_VERSION_MAJOR_V(e)   BF_EMI_VERSION_MAJOR(BV_EMI_VERSION_MAJOR__##e)
+#define BFM_EMI_VERSION_MAJOR_V(v)  BM_EMI_VERSION_MAJOR
+#define BP_EMI_VERSION_MINOR        16
+#define BM_EMI_VERSION_MINOR        0xff0000
+#define BF_EMI_VERSION_MINOR(v)     (((v) & 0xff) << 16)
+#define BFM_EMI_VERSION_MINOR(v)    BM_EMI_VERSION_MINOR
+#define BF_EMI_VERSION_MINOR_V(e)   BF_EMI_VERSION_MINOR(BV_EMI_VERSION_MINOR__##e)
+#define BFM_EMI_VERSION_MINOR_V(v)  BM_EMI_VERSION_MINOR
+#define BP_EMI_VERSION_STEP         0
+#define BM_EMI_VERSION_STEP         0xffff
+#define BF_EMI_VERSION_STEP(v)      (((v) & 0xffff) << 0)
+#define BFM_EMI_VERSION_STEP(v)     BM_EMI_VERSION_STEP
+#define BF_EMI_VERSION_STEP_V(e)    BF_EMI_VERSION_STEP(BV_EMI_VERSION_STEP__##e)
+#define BFM_EMI_VERSION_STEP_V(v)   BM_EMI_VERSION_STEP
+
+#endif /* __HEADERGEN_IMX233_EMI_H__*/
diff --git a/firmware/target/arm/imx233/regs/imx233/gpmi.h b/firmware/target/arm/imx233/regs/imx233/gpmi.h
new file mode 100644
index 0000000000..98f367fe24
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/imx233/gpmi.h
@@ -0,0 +1,875 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * imx233 version: 2.4.0
+ * imx233 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_IMX233_GPMI_H__
+#define __HEADERGEN_IMX233_GPMI_H__
+
+#define HW_GPMI_CTRL0                                   HW(GPMI_CTRL0)
+#define HWA_GPMI_CTRL0                                  (0x8000c000 + 0x0)
+#define HWT_GPMI_CTRL0                                  HWIO_32_RW
+#define HWN_GPMI_CTRL0                                  GPMI_CTRL0
+#define HWI_GPMI_CTRL0                                  
+#define HW_GPMI_CTRL0_SET                               HW(GPMI_CTRL0_SET)
+#define HWA_GPMI_CTRL0_SET                              (HWA_GPMI_CTRL0 + 0x4)
+#define HWT_GPMI_CTRL0_SET                              HWIO_32_WO
+#define HWN_GPMI_CTRL0_SET                              GPMI_CTRL0
+#define HWI_GPMI_CTRL0_SET                              
+#define HW_GPMI_CTRL0_CLR                               HW(GPMI_CTRL0_CLR)
+#define HWA_GPMI_CTRL0_CLR                              (HWA_GPMI_CTRL0 + 0x8)
+#define HWT_GPMI_CTRL0_CLR                              HWIO_32_WO
+#define HWN_GPMI_CTRL0_CLR                              GPMI_CTRL0
+#define HWI_GPMI_CTRL0_CLR                              
+#define HW_GPMI_CTRL0_TOG                               HW(GPMI_CTRL0_TOG)
+#define HWA_GPMI_CTRL0_TOG                              (HWA_GPMI_CTRL0 + 0xc)
+#define HWT_GPMI_CTRL0_TOG                              HWIO_32_WO
+#define HWN_GPMI_CTRL0_TOG                              GPMI_CTRL0
+#define HWI_GPMI_CTRL0_TOG                              
+#define BP_GPMI_CTRL0_SFTRST                            31
+#define BM_GPMI_CTRL0_SFTRST                            0x80000000
+#define BV_GPMI_CTRL0_SFTRST__RUN                       0x0
+#define BV_GPMI_CTRL0_SFTRST__RESET                     0x1
+#define BF_GPMI_CTRL0_SFTRST(v)                         (((v) & 0x1) << 31)
+#define BFM_GPMI_CTRL0_SFTRST(v)                        BM_GPMI_CTRL0_SFTRST
+#define BF_GPMI_CTRL0_SFTRST_V(e)                       BF_GPMI_CTRL0_SFTRST(BV_GPMI_CTRL0_SFTRST__##e)
+#define BFM_GPMI_CTRL0_SFTRST_V(v)                      BM_GPMI_CTRL0_SFTRST
+#define BP_GPMI_CTRL0_CLKGATE                           30
+#define BM_GPMI_CTRL0_CLKGATE                           0x40000000
+#define BV_GPMI_CTRL0_CLKGATE__RUN                      0x0
+#define BV_GPMI_CTRL0_CLKGATE__NO_CLKS                  0x1
+#define BF_GPMI_CTRL0_CLKGATE(v)                        (((v) & 0x1) << 30)
+#define BFM_GPMI_CTRL0_CLKGATE(v)                       BM_GPMI_CTRL0_CLKGATE
+#define BF_GPMI_CTRL0_CLKGATE_V(e)                      BF_GPMI_CTRL0_CLKGATE(BV_GPMI_CTRL0_CLKGATE__##e)
+#define BFM_GPMI_CTRL0_CLKGATE_V(v)                     BM_GPMI_CTRL0_CLKGATE
+#define BP_GPMI_CTRL0_RUN                               29
+#define BM_GPMI_CTRL0_RUN                               0x20000000
+#define BV_GPMI_CTRL0_RUN__IDLE                         0x0
+#define BV_GPMI_CTRL0_RUN__BUSY                         0x1
+#define BF_GPMI_CTRL0_RUN(v)                            (((v) & 0x1) << 29)
+#define BFM_GPMI_CTRL0_RUN(v)                           BM_GPMI_CTRL0_RUN
+#define BF_GPMI_CTRL0_RUN_V(e)                          BF_GPMI_CTRL0_RUN(BV_GPMI_CTRL0_RUN__##e)
+#define BFM_GPMI_CTRL0_RUN_V(v)                         BM_GPMI_CTRL0_RUN
+#define BP_GPMI_CTRL0_DEV_IRQ_EN                        28
+#define BM_GPMI_CTRL0_DEV_IRQ_EN                        0x10000000
+#define BF_GPMI_CTRL0_DEV_IRQ_EN(v)                     (((v) & 0x1) << 28)
+#define BFM_GPMI_CTRL0_DEV_IRQ_EN(v)                    BM_GPMI_CTRL0_DEV_IRQ_EN
+#define BF_GPMI_CTRL0_DEV_IRQ_EN_V(e)                   BF_GPMI_CTRL0_DEV_IRQ_EN(BV_GPMI_CTRL0_DEV_IRQ_EN__##e)
+#define BFM_GPMI_CTRL0_DEV_IRQ_EN_V(v)                  BM_GPMI_CTRL0_DEV_IRQ_EN
+#define BP_GPMI_CTRL0_TIMEOUT_IRQ_EN                    27
+#define BM_GPMI_CTRL0_TIMEOUT_IRQ_EN                    0x8000000
+#define BF_GPMI_CTRL0_TIMEOUT_IRQ_EN(v)                 (((v) & 0x1) << 27)
+#define BFM_GPMI_CTRL0_TIMEOUT_IRQ_EN(v)                BM_GPMI_CTRL0_TIMEOUT_IRQ_EN
+#define BF_GPMI_CTRL0_TIMEOUT_IRQ_EN_V(e)               BF_GPMI_CTRL0_TIMEOUT_IRQ_EN(BV_GPMI_CTRL0_TIMEOUT_IRQ_EN__##e)
+#define BFM_GPMI_CTRL0_TIMEOUT_IRQ_EN_V(v)              BM_GPMI_CTRL0_TIMEOUT_IRQ_EN
+#define BP_GPMI_CTRL0_UDMA                              26
+#define BM_GPMI_CTRL0_UDMA                              0x4000000
+#define BV_GPMI_CTRL0_UDMA__DISABLED                    0x0
+#define BV_GPMI_CTRL0_UDMA__ENABLED                     0x1
+#define BF_GPMI_CTRL0_UDMA(v)                           (((v) & 0x1) << 26)
+#define BFM_GPMI_CTRL0_UDMA(v)                          BM_GPMI_CTRL0_UDMA
+#define BF_GPMI_CTRL0_UDMA_V(e)                         BF_GPMI_CTRL0_UDMA(BV_GPMI_CTRL0_UDMA__##e)
+#define BFM_GPMI_CTRL0_UDMA_V(v)                        BM_GPMI_CTRL0_UDMA
+#define BP_GPMI_CTRL0_COMMAND_MODE                      24
+#define BM_GPMI_CTRL0_COMMAND_MODE                      0x3000000
+#define BV_GPMI_CTRL0_COMMAND_MODE__WRITE               0x0
+#define BV_GPMI_CTRL0_COMMAND_MODE__READ                0x1
+#define BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE    0x2
+#define BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY      0x3
+#define BF_GPMI_CTRL0_COMMAND_MODE(v)                   (((v) & 0x3) << 24)
+#define BFM_GPMI_CTRL0_COMMAND_MODE(v)                  BM_GPMI_CTRL0_COMMAND_MODE
+#define BF_GPMI_CTRL0_COMMAND_MODE_V(e)                 BF_GPMI_CTRL0_COMMAND_MODE(BV_GPMI_CTRL0_COMMAND_MODE__##e)
+#define BFM_GPMI_CTRL0_COMMAND_MODE_V(v)                BM_GPMI_CTRL0_COMMAND_MODE
+#define BP_GPMI_CTRL0_WORD_LENGTH                       23
+#define BM_GPMI_CTRL0_WORD_LENGTH                       0x800000
+#define BV_GPMI_CTRL0_WORD_LENGTH__16_BIT               0x0
+#define BV_GPMI_CTRL0_WORD_LENGTH__8_BIT                0x1
+#define BF_GPMI_CTRL0_WORD_LENGTH(v)                    (((v) & 0x1) << 23)
+#define BFM_GPMI_CTRL0_WORD_LENGTH(v)                   BM_GPMI_CTRL0_WORD_LENGTH
+#define BF_GPMI_CTRL0_WORD_LENGTH_V(e)                  BF_GPMI_CTRL0_WORD_LENGTH(BV_GPMI_CTRL0_WORD_LENGTH__##e)
+#define BFM_GPMI_CTRL0_WORD_LENGTH_V(v)                 BM_GPMI_CTRL0_WORD_LENGTH
+#define BP_GPMI_CTRL0_LOCK_CS                           22
+#define BM_GPMI_CTRL0_LOCK_CS                           0x400000
+#define BV_GPMI_CTRL0_LOCK_CS__DISABLED                 0x0
+#define BV_GPMI_CTRL0_LOCK_CS__ENABLED                  0x1
+#define BF_GPMI_CTRL0_LOCK_CS(v)                        (((v) & 0x1) << 22)
+#define BFM_GPMI_CTRL0_LOCK_CS(v)                       BM_GPMI_CTRL0_LOCK_CS
+#define BF_GPMI_CTRL0_LOCK_CS_V(e)                      BF_GPMI_CTRL0_LOCK_CS(BV_GPMI_CTRL0_LOCK_CS__##e)
+#define BFM_GPMI_CTRL0_LOCK_CS_V(v)                     BM_GPMI_CTRL0_LOCK_CS
+#define BP_GPMI_CTRL0_CS                                20
+#define BM_GPMI_CTRL0_CS                                0x300000
+#define BF_GPMI_CTRL0_CS(v)                             (((v) & 0x3) << 20)
+#define BFM_GPMI_CTRL0_CS(v)                            BM_GPMI_CTRL0_CS
+#define BF_GPMI_CTRL0_CS_V(e)                           BF_GPMI_CTRL0_CS(BV_GPMI_CTRL0_CS__##e)
+#define BFM_GPMI_CTRL0_CS_V(v)                          BM_GPMI_CTRL0_CS
+#define BP_GPMI_CTRL0_ADDRESS                           17
+#define BM_GPMI_CTRL0_ADDRESS                           0xe0000
+#define BV_GPMI_CTRL0_ADDRESS__NAND_DATA                0x0
+#define BV_GPMI_CTRL0_ADDRESS__NAND_CLE                 0x1
+#define BV_GPMI_CTRL0_ADDRESS__NAND_ALE                 0x2
+#define BF_GPMI_CTRL0_ADDRESS(v)                        (((v) & 0x7) << 17)
+#define BFM_GPMI_CTRL0_ADDRESS(v)                       BM_GPMI_CTRL0_ADDRESS
+#define BF_GPMI_CTRL0_ADDRESS_V(e)                      BF_GPMI_CTRL0_ADDRESS(BV_GPMI_CTRL0_ADDRESS__##e)
+#define BFM_GPMI_CTRL0_ADDRESS_V(v)                     BM_GPMI_CTRL0_ADDRESS
+#define BP_GPMI_CTRL0_ADDRESS_INCREMENT                 16
+#define BM_GPMI_CTRL0_ADDRESS_INCREMENT                 0x10000
+#define BV_GPMI_CTRL0_ADDRESS_INCREMENT__DISABLED       0x0
+#define BV_GPMI_CTRL0_ADDRESS_INCREMENT__ENABLED        0x1
+#define BF_GPMI_CTRL0_ADDRESS_INCREMENT(v)              (((v) & 0x1) << 16)
+#define BFM_GPMI_CTRL0_ADDRESS_INCREMENT(v)             BM_GPMI_CTRL0_ADDRESS_INCREMENT
+#define BF_GPMI_CTRL0_ADDRESS_INCREMENT_V(e)            BF_GPMI_CTRL0_ADDRESS_INCREMENT(BV_GPMI_CTRL0_ADDRESS_INCREMENT__##e)
+#define BFM_GPMI_CTRL0_ADDRESS_INCREMENT_V(v)           BM_GPMI_CTRL0_ADDRESS_INCREMENT
+#define BP_GPMI_CTRL0_XFER_COUNT                        0
+#define BM_GPMI_CTRL0_XFER_COUNT                        0xffff
+#define BF_GPMI_CTRL0_XFER_COUNT(v)                     (((v) & 0xffff) << 0)
+#define BFM_GPMI_CTRL0_XFER_COUNT(v)                    BM_GPMI_CTRL0_XFER_COUNT
+#define BF_GPMI_CTRL0_XFER_COUNT_V(e)                   BF_GPMI_CTRL0_XFER_COUNT(BV_GPMI_CTRL0_XFER_COUNT__##e)
+#define BFM_GPMI_CTRL0_XFER_COUNT_V(v)                  BM_GPMI_CTRL0_XFER_COUNT
+
+#define HW_GPMI_COMPARE                 HW(GPMI_COMPARE)
+#define HWA_GPMI_COMPARE                (0x8000c000 + 0x10)
+#define HWT_GPMI_COMPARE                HWIO_32_RW
+#define HWN_GPMI_COMPARE                GPMI_COMPARE
+#define HWI_GPMI_COMPARE                
+#define BP_GPMI_COMPARE_MASK            16
+#define BM_GPMI_COMPARE_MASK            0xffff0000
+#define BF_GPMI_COMPARE_MASK(v)         (((v) & 0xffff) << 16)
+#define BFM_GPMI_COMPARE_MASK(v)        BM_GPMI_COMPARE_MASK
+#define BF_GPMI_COMPARE_MASK_V(e)       BF_GPMI_COMPARE_MASK(BV_GPMI_COMPARE_MASK__##e)
+#define BFM_GPMI_COMPARE_MASK_V(v)      BM_GPMI_COMPARE_MASK
+#define BP_GPMI_COMPARE_REFERENCE       0
+#define BM_GPMI_COMPARE_REFERENCE       0xffff
+#define BF_GPMI_COMPARE_REFERENCE(v)    (((v) & 0xffff) << 0)
+#define BFM_GPMI_COMPARE_REFERENCE(v)   BM_GPMI_COMPARE_REFERENCE
+#define BF_GPMI_COMPARE_REFERENCE_V(e)  BF_GPMI_COMPARE_REFERENCE(BV_GPMI_COMPARE_REFERENCE__##e)
+#define BFM_GPMI_COMPARE_REFERENCE_V(v) BM_GPMI_COMPARE_REFERENCE
+
+#define HW_GPMI_ECCCTRL                             HW(GPMI_ECCCTRL)
+#define HWA_GPMI_ECCCTRL                            (0x8000c000 + 0x20)
+#define HWT_GPMI_ECCCTRL                            HWIO_32_RW
+#define HWN_GPMI_ECCCTRL                            GPMI_ECCCTRL
+#define HWI_GPMI_ECCCTRL                            
+#define HW_GPMI_ECCCTRL_SET                         HW(GPMI_ECCCTRL_SET)
+#define HWA_GPMI_ECCCTRL_SET                        (HWA_GPMI_ECCCTRL + 0x4)
+#define HWT_GPMI_ECCCTRL_SET                        HWIO_32_WO
+#define HWN_GPMI_ECCCTRL_SET                        GPMI_ECCCTRL
+#define HWI_GPMI_ECCCTRL_SET                        
+#define HW_GPMI_ECCCTRL_CLR                         HW(GPMI_ECCCTRL_CLR)
+#define HWA_GPMI_ECCCTRL_CLR                        (HWA_GPMI_ECCCTRL + 0x8)
+#define HWT_GPMI_ECCCTRL_CLR                        HWIO_32_WO
+#define HWN_GPMI_ECCCTRL_CLR                        GPMI_ECCCTRL
+#define HWI_GPMI_ECCCTRL_CLR                        
+#define HW_GPMI_ECCCTRL_TOG                         HW(GPMI_ECCCTRL_TOG)
+#define HWA_GPMI_ECCCTRL_TOG                        (HWA_GPMI_ECCCTRL + 0xc)
+#define HWT_GPMI_ECCCTRL_TOG                        HWIO_32_WO
+#define HWN_GPMI_ECCCTRL_TOG                        GPMI_ECCCTRL
+#define HWI_GPMI_ECCCTRL_TOG                        
+#define BP_GPMI_ECCCTRL_HANDLE                      16
+#define BM_GPMI_ECCCTRL_HANDLE                      0xffff0000
+#define BF_GPMI_ECCCTRL_HANDLE(v)                   (((v) & 0xffff) << 16)
+#define BFM_GPMI_ECCCTRL_HANDLE(v)                  BM_GPMI_ECCCTRL_HANDLE
+#define BF_GPMI_ECCCTRL_HANDLE_V(e)                 BF_GPMI_ECCCTRL_HANDLE(BV_GPMI_ECCCTRL_HANDLE__##e)
+#define BFM_GPMI_ECCCTRL_HANDLE_V(v)                BM_GPMI_ECCCTRL_HANDLE
+#define BP_GPMI_ECCCTRL_RSVD2                       15
+#define BM_GPMI_ECCCTRL_RSVD2                       0x8000
+#define BF_GPMI_ECCCTRL_RSVD2(v)                    (((v) & 0x1) << 15)
+#define BFM_GPMI_ECCCTRL_RSVD2(v)                   BM_GPMI_ECCCTRL_RSVD2
+#define BF_GPMI_ECCCTRL_RSVD2_V(e)                  BF_GPMI_ECCCTRL_RSVD2(BV_GPMI_ECCCTRL_RSVD2__##e)
+#define BFM_GPMI_ECCCTRL_RSVD2_V(v)                 BM_GPMI_ECCCTRL_RSVD2
+#define BP_GPMI_ECCCTRL_ECC_CMD                     13
+#define BM_GPMI_ECCCTRL_ECC_CMD                     0x6000
+#define BV_GPMI_ECCCTRL_ECC_CMD__DECODE_4_BIT       0x0
+#define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE_4_BIT       0x1
+#define BV_GPMI_ECCCTRL_ECC_CMD__DECODE_8_BIT       0x2
+#define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE_8_BIT       0x3
+#define BF_GPMI_ECCCTRL_ECC_CMD(v)                  (((v) & 0x3) << 13)
+#define BFM_GPMI_ECCCTRL_ECC_CMD(v)                 BM_GPMI_ECCCTRL_ECC_CMD
+#define BF_GPMI_ECCCTRL_ECC_CMD_V(e)                BF_GPMI_ECCCTRL_ECC_CMD(BV_GPMI_ECCCTRL_ECC_CMD__##e)
+#define BFM_GPMI_ECCCTRL_ECC_CMD_V(v)               BM_GPMI_ECCCTRL_ECC_CMD
+#define BP_GPMI_ECCCTRL_ENABLE_ECC                  12
+#define BM_GPMI_ECCCTRL_ENABLE_ECC                  0x1000
+#define BV_GPMI_ECCCTRL_ENABLE_ECC__ENABLE          0x1
+#define BV_GPMI_ECCCTRL_ENABLE_ECC__DISABLE         0x0
+#define BF_GPMI_ECCCTRL_ENABLE_ECC(v)               (((v) & 0x1) << 12)
+#define BFM_GPMI_ECCCTRL_ENABLE_ECC(v)              BM_GPMI_ECCCTRL_ENABLE_ECC
+#define BF_GPMI_ECCCTRL_ENABLE_ECC_V(e)             BF_GPMI_ECCCTRL_ENABLE_ECC(BV_GPMI_ECCCTRL_ENABLE_ECC__##e)
+#define BFM_GPMI_ECCCTRL_ENABLE_ECC_V(v)            BM_GPMI_ECCCTRL_ENABLE_ECC
+#define BP_GPMI_ECCCTRL_RSVD1                       9
+#define BM_GPMI_ECCCTRL_RSVD1                       0xe00
+#define BF_GPMI_ECCCTRL_RSVD1(v)                    (((v) & 0x7) << 9)
+#define BFM_GPMI_ECCCTRL_RSVD1(v)                   BM_GPMI_ECCCTRL_RSVD1
+#define BF_GPMI_ECCCTRL_RSVD1_V(e)                  BF_GPMI_ECCCTRL_RSVD1(BV_GPMI_ECCCTRL_RSVD1__##e)
+#define BFM_GPMI_ECCCTRL_RSVD1_V(v)                 BM_GPMI_ECCCTRL_RSVD1
+#define BP_GPMI_ECCCTRL_BUFFER_MASK                 0
+#define BM_GPMI_ECCCTRL_BUFFER_MASK                 0x1ff
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY    0x100
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE       0x1ff
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__AUXILIARY      0x100
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER7        0x80
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER6        0x40
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER5        0x20
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER4        0x10
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER3        0x8
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER2        0x4
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER1        0x2
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER0        0x1
+#define BF_GPMI_ECCCTRL_BUFFER_MASK(v)              (((v) & 0x1ff) << 0)
+#define BFM_GPMI_ECCCTRL_BUFFER_MASK(v)             BM_GPMI_ECCCTRL_BUFFER_MASK
+#define BF_GPMI_ECCCTRL_BUFFER_MASK_V(e)            BF_GPMI_ECCCTRL_BUFFER_MASK(BV_GPMI_ECCCTRL_BUFFER_MASK__##e)
+#define BFM_GPMI_ECCCTRL_BUFFER_MASK_V(v)           BM_GPMI_ECCCTRL_BUFFER_MASK
+
+#define HW_GPMI_ECCCOUNT                HW(GPMI_ECCCOUNT)
+#define HWA_GPMI_ECCCOUNT               (0x8000c000 + 0x30)
+#define HWT_GPMI_ECCCOUNT               HWIO_32_RW
+#define HWN_GPMI_ECCCOUNT               GPMI_ECCCOUNT
+#define HWI_GPMI_ECCCOUNT               
+#define BP_GPMI_ECCCOUNT_RSVD2          16
+#define BM_GPMI_ECCCOUNT_RSVD2          0xffff0000
+#define BF_GPMI_ECCCOUNT_RSVD2(v)       (((v) & 0xffff) << 16)
+#define BFM_GPMI_ECCCOUNT_RSVD2(v)      BM_GPMI_ECCCOUNT_RSVD2
+#define BF_GPMI_ECCCOUNT_RSVD2_V(e)     BF_GPMI_ECCCOUNT_RSVD2(BV_GPMI_ECCCOUNT_RSVD2__##e)
+#define BFM_GPMI_ECCCOUNT_RSVD2_V(v)    BM_GPMI_ECCCOUNT_RSVD2
+#define BP_GPMI_ECCCOUNT_COUNT          0
+#define BM_GPMI_ECCCOUNT_COUNT          0xffff
+#define BF_GPMI_ECCCOUNT_COUNT(v)       (((v) & 0xffff) << 0)
+#define BFM_GPMI_ECCCOUNT_COUNT(v)      BM_GPMI_ECCCOUNT_COUNT
+#define BF_GPMI_ECCCOUNT_COUNT_V(e)     BF_GPMI_ECCCOUNT_COUNT(BV_GPMI_ECCCOUNT_COUNT__##e)
+#define BFM_GPMI_ECCCOUNT_COUNT_V(v)    BM_GPMI_ECCCOUNT_COUNT
+
+#define HW_GPMI_PAYLOAD                 HW(GPMI_PAYLOAD)
+#define HWA_GPMI_PAYLOAD                (0x8000c000 + 0x40)
+#define HWT_GPMI_PAYLOAD                HWIO_32_RW
+#define HWN_GPMI_PAYLOAD                GPMI_PAYLOAD
+#define HWI_GPMI_PAYLOAD                
+#define BP_GPMI_PAYLOAD_ADDRESS         2
+#define BM_GPMI_PAYLOAD_ADDRESS         0xfffffffc
+#define BF_GPMI_PAYLOAD_ADDRESS(v)      (((v) & 0x3fffffff) << 2)
+#define BFM_GPMI_PAYLOAD_ADDRESS(v)     BM_GPMI_PAYLOAD_ADDRESS
+#define BF_GPMI_PAYLOAD_ADDRESS_V(e)    BF_GPMI_PAYLOAD_ADDRESS(BV_GPMI_PAYLOAD_ADDRESS__##e)
+#define BFM_GPMI_PAYLOAD_ADDRESS_V(v)   BM_GPMI_PAYLOAD_ADDRESS
+#define BP_GPMI_PAYLOAD_RSVD0           0
+#define BM_GPMI_PAYLOAD_RSVD0           0x3
+#define BF_GPMI_PAYLOAD_RSVD0(v)        (((v) & 0x3) << 0)
+#define BFM_GPMI_PAYLOAD_RSVD0(v)       BM_GPMI_PAYLOAD_RSVD0
+#define BF_GPMI_PAYLOAD_RSVD0_V(e)      BF_GPMI_PAYLOAD_RSVD0(BV_GPMI_PAYLOAD_RSVD0__##e)
+#define BFM_GPMI_PAYLOAD_RSVD0_V(v)     BM_GPMI_PAYLOAD_RSVD0
+
+#define HW_GPMI_AUXILIARY               HW(GPMI_AUXILIARY)
+#define HWA_GPMI_AUXILIARY              (0x8000c000 + 0x50)
+#define HWT_GPMI_AUXILIARY              HWIO_32_RW
+#define HWN_GPMI_AUXILIARY              GPMI_AUXILIARY
+#define HWI_GPMI_AUXILIARY              
+#define BP_GPMI_AUXILIARY_ADDRESS       2
+#define BM_GPMI_AUXILIARY_ADDRESS       0xfffffffc
+#define BF_GPMI_AUXILIARY_ADDRESS(v)    (((v) & 0x3fffffff) << 2)
+#define BFM_GPMI_AUXILIARY_ADDRESS(v)   BM_GPMI_AUXILIARY_ADDRESS
+#define BF_GPMI_AUXILIARY_ADDRESS_V(e)  BF_GPMI_AUXILIARY_ADDRESS(BV_GPMI_AUXILIARY_ADDRESS__##e)
+#define BFM_GPMI_AUXILIARY_ADDRESS_V(v) BM_GPMI_AUXILIARY_ADDRESS
+#define BP_GPMI_AUXILIARY_RSVD0         0
+#define BM_GPMI_AUXILIARY_RSVD0         0x3
+#define BF_GPMI_AUXILIARY_RSVD0(v)      (((v) & 0x3) << 0)
+#define BFM_GPMI_AUXILIARY_RSVD0(v)     BM_GPMI_AUXILIARY_RSVD0
+#define BF_GPMI_AUXILIARY_RSVD0_V(e)    BF_GPMI_AUXILIARY_RSVD0(BV_GPMI_AUXILIARY_RSVD0__##e)
+#define BFM_GPMI_AUXILIARY_RSVD0_V(v)   BM_GPMI_AUXILIARY_RSVD0
+
+#define HW_GPMI_CTRL1                                   HW(GPMI_CTRL1)
+#define HWA_GPMI_CTRL1                                  (0x8000c000 + 0x60)
+#define HWT_GPMI_CTRL1                                  HWIO_32_RW
+#define HWN_GPMI_CTRL1                                  GPMI_CTRL1
+#define HWI_GPMI_CTRL1                                  
+#define HW_GPMI_CTRL1_SET                               HW(GPMI_CTRL1_SET)
+#define HWA_GPMI_CTRL1_SET                              (HWA_GPMI_CTRL1 + 0x4)
+#define HWT_GPMI_CTRL1_SET                              HWIO_32_WO
+#define HWN_GPMI_CTRL1_SET                              GPMI_CTRL1
+#define HWI_GPMI_CTRL1_SET                              
+#define HW_GPMI_CTRL1_CLR                               HW(GPMI_CTRL1_CLR)
+#define HWA_GPMI_CTRL1_CLR                              (HWA_GPMI_CTRL1 + 0x8)
+#define HWT_GPMI_CTRL1_CLR                              HWIO_32_WO
+#define HWN_GPMI_CTRL1_CLR                              GPMI_CTRL1
+#define HWI_GPMI_CTRL1_CLR                              
+#define HW_GPMI_CTRL1_TOG                               HW(GPMI_CTRL1_TOG)
+#define HWA_GPMI_CTRL1_TOG                              (HWA_GPMI_CTRL1 + 0xc)
+#define HWT_GPMI_CTRL1_TOG                              HWIO_32_WO
+#define HWN_GPMI_CTRL1_TOG                              GPMI_CTRL1
+#define HWI_GPMI_CTRL1_TOG                              
+#define BP_GPMI_CTRL1_RSVD2                             24
+#define BM_GPMI_CTRL1_RSVD2                             0xff000000
+#define BF_GPMI_CTRL1_RSVD2(v)                          (((v) & 0xff) << 24)
+#define BFM_GPMI_CTRL1_RSVD2(v)                         BM_GPMI_CTRL1_RSVD2
+#define BF_GPMI_CTRL1_RSVD2_V(e)                        BF_GPMI_CTRL1_RSVD2(BV_GPMI_CTRL1_RSVD2__##e)
+#define BFM_GPMI_CTRL1_RSVD2_V(v)                       BM_GPMI_CTRL1_RSVD2
+#define BP_GPMI_CTRL1_CE3_SEL                           23
+#define BM_GPMI_CTRL1_CE3_SEL                           0x800000
+#define BF_GPMI_CTRL1_CE3_SEL(v)                        (((v) & 0x1) << 23)
+#define BFM_GPMI_CTRL1_CE3_SEL(v)                       BM_GPMI_CTRL1_CE3_SEL
+#define BF_GPMI_CTRL1_CE3_SEL_V(e)                      BF_GPMI_CTRL1_CE3_SEL(BV_GPMI_CTRL1_CE3_SEL__##e)
+#define BFM_GPMI_CTRL1_CE3_SEL_V(v)                     BM_GPMI_CTRL1_CE3_SEL
+#define BP_GPMI_CTRL1_CE2_SEL                           22
+#define BM_GPMI_CTRL1_CE2_SEL                           0x400000
+#define BF_GPMI_CTRL1_CE2_SEL(v)                        (((v) & 0x1) << 22)
+#define BFM_GPMI_CTRL1_CE2_SEL(v)                       BM_GPMI_CTRL1_CE2_SEL
+#define BF_GPMI_CTRL1_CE2_SEL_V(e)                      BF_GPMI_CTRL1_CE2_SEL(BV_GPMI_CTRL1_CE2_SEL__##e)
+#define BFM_GPMI_CTRL1_CE2_SEL_V(v)                     BM_GPMI_CTRL1_CE2_SEL
+#define BP_GPMI_CTRL1_CE1_SEL                           21
+#define BM_GPMI_CTRL1_CE1_SEL                           0x200000
+#define BF_GPMI_CTRL1_CE1_SEL(v)                        (((v) & 0x1) << 21)
+#define BFM_GPMI_CTRL1_CE1_SEL(v)                       BM_GPMI_CTRL1_CE1_SEL
+#define BF_GPMI_CTRL1_CE1_SEL_V(e)                      BF_GPMI_CTRL1_CE1_SEL(BV_GPMI_CTRL1_CE1_SEL__##e)
+#define BFM_GPMI_CTRL1_CE1_SEL_V(v)                     BM_GPMI_CTRL1_CE1_SEL
+#define BP_GPMI_CTRL1_CE0_SEL                           20
+#define BM_GPMI_CTRL1_CE0_SEL                           0x100000
+#define BF_GPMI_CTRL1_CE0_SEL(v)                        (((v) & 0x1) << 20)
+#define BFM_GPMI_CTRL1_CE0_SEL(v)                       BM_GPMI_CTRL1_CE0_SEL
+#define BF_GPMI_CTRL1_CE0_SEL_V(e)                      BF_GPMI_CTRL1_CE0_SEL(BV_GPMI_CTRL1_CE0_SEL__##e)
+#define BFM_GPMI_CTRL1_CE0_SEL_V(v)                     BM_GPMI_CTRL1_CE0_SEL
+#define BP_GPMI_CTRL1_GANGED_RDYBUSY                    19
+#define BM_GPMI_CTRL1_GANGED_RDYBUSY                    0x80000
+#define BF_GPMI_CTRL1_GANGED_RDYBUSY(v)                 (((v) & 0x1) << 19)
+#define BFM_GPMI_CTRL1_GANGED_RDYBUSY(v)                BM_GPMI_CTRL1_GANGED_RDYBUSY
+#define BF_GPMI_CTRL1_GANGED_RDYBUSY_V(e)               BF_GPMI_CTRL1_GANGED_RDYBUSY(BV_GPMI_CTRL1_GANGED_RDYBUSY__##e)
+#define BFM_GPMI_CTRL1_GANGED_RDYBUSY_V(v)              BM_GPMI_CTRL1_GANGED_RDYBUSY
+#define BP_GPMI_CTRL1_BCH_MODE                          18
+#define BM_GPMI_CTRL1_BCH_MODE                          0x40000
+#define BF_GPMI_CTRL1_BCH_MODE(v)                       (((v) & 0x1) << 18)
+#define BFM_GPMI_CTRL1_BCH_MODE(v)                      BM_GPMI_CTRL1_BCH_MODE
+#define BF_GPMI_CTRL1_BCH_MODE_V(e)                     BF_GPMI_CTRL1_BCH_MODE(BV_GPMI_CTRL1_BCH_MODE__##e)
+#define BFM_GPMI_CTRL1_BCH_MODE_V(v)                    BM_GPMI_CTRL1_BCH_MODE
+#define BP_GPMI_CTRL1_DLL_ENABLE                        17
+#define BM_GPMI_CTRL1_DLL_ENABLE                        0x20000
+#define BF_GPMI_CTRL1_DLL_ENABLE(v)                     (((v) & 0x1) << 17)
+#define BFM_GPMI_CTRL1_DLL_ENABLE(v)                    BM_GPMI_CTRL1_DLL_ENABLE
+#define BF_GPMI_CTRL1_DLL_ENABLE_V(e)                   BF_GPMI_CTRL1_DLL_ENABLE(BV_GPMI_CTRL1_DLL_ENABLE__##e)
+#define BFM_GPMI_CTRL1_DLL_ENABLE_V(v)                  BM_GPMI_CTRL1_DLL_ENABLE
+#define BP_GPMI_CTRL1_HALF_PERIOD                       16
+#define BM_GPMI_CTRL1_HALF_PERIOD                       0x10000
+#define BF_GPMI_CTRL1_HALF_PERIOD(v)                    (((v) & 0x1) << 16)
+#define BFM_GPMI_CTRL1_HALF_PERIOD(v)                   BM_GPMI_CTRL1_HALF_PERIOD
+#define BF_GPMI_CTRL1_HALF_PERIOD_V(e)                  BF_GPMI_CTRL1_HALF_PERIOD(BV_GPMI_CTRL1_HALF_PERIOD__##e)
+#define BFM_GPMI_CTRL1_HALF_PERIOD_V(v)                 BM_GPMI_CTRL1_HALF_PERIOD
+#define BP_GPMI_CTRL1_RDN_DELAY                         12
+#define BM_GPMI_CTRL1_RDN_DELAY                         0xf000
+#define BF_GPMI_CTRL1_RDN_DELAY(v)                      (((v) & 0xf) << 12)
+#define BFM_GPMI_CTRL1_RDN_DELAY(v)                     BM_GPMI_CTRL1_RDN_DELAY
+#define BF_GPMI_CTRL1_RDN_DELAY_V(e)                    BF_GPMI_CTRL1_RDN_DELAY(BV_GPMI_CTRL1_RDN_DELAY__##e)
+#define BFM_GPMI_CTRL1_RDN_DELAY_V(v)                   BM_GPMI_CTRL1_RDN_DELAY
+#define BP_GPMI_CTRL1_DMA2ECC_MODE                      11
+#define BM_GPMI_CTRL1_DMA2ECC_MODE                      0x800
+#define BF_GPMI_CTRL1_DMA2ECC_MODE(v)                   (((v) & 0x1) << 11)
+#define BFM_GPMI_CTRL1_DMA2ECC_MODE(v)                  BM_GPMI_CTRL1_DMA2ECC_MODE
+#define BF_GPMI_CTRL1_DMA2ECC_MODE_V(e)                 BF_GPMI_CTRL1_DMA2ECC_MODE(BV_GPMI_CTRL1_DMA2ECC_MODE__##e)
+#define BFM_GPMI_CTRL1_DMA2ECC_MODE_V(v)                BM_GPMI_CTRL1_DMA2ECC_MODE
+#define BP_GPMI_CTRL1_DEV_IRQ                           10
+#define BM_GPMI_CTRL1_DEV_IRQ                           0x400
+#define BF_GPMI_CTRL1_DEV_IRQ(v)                        (((v) & 0x1) << 10)
+#define BFM_GPMI_CTRL1_DEV_IRQ(v)                       BM_GPMI_CTRL1_DEV_IRQ
+#define BF_GPMI_CTRL1_DEV_IRQ_V(e)                      BF_GPMI_CTRL1_DEV_IRQ(BV_GPMI_CTRL1_DEV_IRQ__##e)
+#define BFM_GPMI_CTRL1_DEV_IRQ_V(v)                     BM_GPMI_CTRL1_DEV_IRQ
+#define BP_GPMI_CTRL1_TIMEOUT_IRQ                       9
+#define BM_GPMI_CTRL1_TIMEOUT_IRQ                       0x200
+#define BF_GPMI_CTRL1_TIMEOUT_IRQ(v)                    (((v) & 0x1) << 9)
+#define BFM_GPMI_CTRL1_TIMEOUT_IRQ(v)                   BM_GPMI_CTRL1_TIMEOUT_IRQ
+#define BF_GPMI_CTRL1_TIMEOUT_IRQ_V(e)                  BF_GPMI_CTRL1_TIMEOUT_IRQ(BV_GPMI_CTRL1_TIMEOUT_IRQ__##e)
+#define BFM_GPMI_CTRL1_TIMEOUT_IRQ_V(v)                 BM_GPMI_CTRL1_TIMEOUT_IRQ
+#define BP_GPMI_CTRL1_BURST_EN                          8
+#define BM_GPMI_CTRL1_BURST_EN                          0x100
+#define BF_GPMI_CTRL1_BURST_EN(v)                       (((v) & 0x1) << 8)
+#define BFM_GPMI_CTRL1_BURST_EN(v)                      BM_GPMI_CTRL1_BURST_EN
+#define BF_GPMI_CTRL1_BURST_EN_V(e)                     BF_GPMI_CTRL1_BURST_EN(BV_GPMI_CTRL1_BURST_EN__##e)
+#define BFM_GPMI_CTRL1_BURST_EN_V(v)                    BM_GPMI_CTRL1_BURST_EN
+#define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY3             7
+#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY3             0x80
+#define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY3(v)          (((v) & 0x1) << 7)
+#define BFM_GPMI_CTRL1_ABORT_WAIT_FOR_READY3(v)         BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY3
+#define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY3_V(e)        BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY3(BV_GPMI_CTRL1_ABORT_WAIT_FOR_READY3__##e)
+#define BFM_GPMI_CTRL1_ABORT_WAIT_FOR_READY3_V(v)       BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY3
+#define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY2             6
+#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY2             0x40
+#define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY2(v)          (((v) & 0x1) << 6)
+#define BFM_GPMI_CTRL1_ABORT_WAIT_FOR_READY2(v)         BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY2
+#define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY2_V(e)        BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY2(BV_GPMI_CTRL1_ABORT_WAIT_FOR_READY2__##e)
+#define BFM_GPMI_CTRL1_ABORT_WAIT_FOR_READY2_V(v)       BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY2
+#define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY1             5
+#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY1             0x20
+#define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY1(v)          (((v) & 0x1) << 5)
+#define BFM_GPMI_CTRL1_ABORT_WAIT_FOR_READY1(v)         BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY1
+#define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY1_V(e)        BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY1(BV_GPMI_CTRL1_ABORT_WAIT_FOR_READY1__##e)
+#define BFM_GPMI_CTRL1_ABORT_WAIT_FOR_READY1_V(v)       BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY1
+#define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY0             4
+#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY0             0x10
+#define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY0(v)          (((v) & 0x1) << 4)
+#define BFM_GPMI_CTRL1_ABORT_WAIT_FOR_READY0(v)         BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY0
+#define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY0_V(e)        BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY0(BV_GPMI_CTRL1_ABORT_WAIT_FOR_READY0__##e)
+#define BFM_GPMI_CTRL1_ABORT_WAIT_FOR_READY0_V(v)       BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY0
+#define BP_GPMI_CTRL1_DEV_RESET                         3
+#define BM_GPMI_CTRL1_DEV_RESET                         0x8
+#define BV_GPMI_CTRL1_DEV_RESET__ENABLED                0x0
+#define BV_GPMI_CTRL1_DEV_RESET__DISABLED               0x1
+#define BF_GPMI_CTRL1_DEV_RESET(v)                      (((v) & 0x1) << 3)
+#define BFM_GPMI_CTRL1_DEV_RESET(v)                     BM_GPMI_CTRL1_DEV_RESET
+#define BF_GPMI_CTRL1_DEV_RESET_V(e)                    BF_GPMI_CTRL1_DEV_RESET(BV_GPMI_CTRL1_DEV_RESET__##e)
+#define BFM_GPMI_CTRL1_DEV_RESET_V(v)                   BM_GPMI_CTRL1_DEV_RESET
+#define BP_GPMI_CTRL1_ATA_IRQRDY_POLARITY               2
+#define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY               0x4
+#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVELOW    0x0
+#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVEHIGH   0x1
+#define BF_GPMI_CTRL1_ATA_IRQRDY_POLARITY(v)            (((v) & 0x1) << 2)
+#define BFM_GPMI_CTRL1_ATA_IRQRDY_POLARITY(v)           BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY
+#define BF_GPMI_CTRL1_ATA_IRQRDY_POLARITY_V(e)          BF_GPMI_CTRL1_ATA_IRQRDY_POLARITY(BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__##e)
+#define BFM_GPMI_CTRL1_ATA_IRQRDY_POLARITY_V(v)         BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY
+#define BP_GPMI_CTRL1_CAMERA_MODE                       1
+#define BM_GPMI_CTRL1_CAMERA_MODE                       0x2
+#define BF_GPMI_CTRL1_CAMERA_MODE(v)                    (((v) & 0x1) << 1)
+#define BFM_GPMI_CTRL1_CAMERA_MODE(v)                   BM_GPMI_CTRL1_CAMERA_MODE
+#define BF_GPMI_CTRL1_CAMERA_MODE_V(e)                  BF_GPMI_CTRL1_CAMERA_MODE(BV_GPMI_CTRL1_CAMERA_MODE__##e)
+#define BFM_GPMI_CTRL1_CAMERA_MODE_V(v)                 BM_GPMI_CTRL1_CAMERA_MODE
+#define BP_GPMI_CTRL1_GPMI_MODE                         0
+#define BM_GPMI_CTRL1_GPMI_MODE                         0x1
+#define BV_GPMI_CTRL1_GPMI_MODE__NAND                   0x0
+#define BV_GPMI_CTRL1_GPMI_MODE__ATA                    0x1
+#define BF_GPMI_CTRL1_GPMI_MODE(v)                      (((v) & 0x1) << 0)
+#define BFM_GPMI_CTRL1_GPMI_MODE(v)                     BM_GPMI_CTRL1_GPMI_MODE
+#define BF_GPMI_CTRL1_GPMI_MODE_V(e)                    BF_GPMI_CTRL1_GPMI_MODE(BV_GPMI_CTRL1_GPMI_MODE__##e)
+#define BFM_GPMI_CTRL1_GPMI_MODE_V(v)                   BM_GPMI_CTRL1_GPMI_MODE
+
+#define HW_GPMI_TIMING0                     HW(GPMI_TIMING0)
+#define HWA_GPMI_TIMING0                    (0x8000c000 + 0x70)
+#define HWT_GPMI_TIMING0                    HWIO_32_RW
+#define HWN_GPMI_TIMING0                    GPMI_TIMING0
+#define HWI_GPMI_TIMING0                    
+#define BP_GPMI_TIMING0_RSVD1               24
+#define BM_GPMI_TIMING0_RSVD1               0xff000000
+#define BF_GPMI_TIMING0_RSVD1(v)            (((v) & 0xff) << 24)
+#define BFM_GPMI_TIMING0_RSVD1(v)           BM_GPMI_TIMING0_RSVD1
+#define BF_GPMI_TIMING0_RSVD1_V(e)          BF_GPMI_TIMING0_RSVD1(BV_GPMI_TIMING0_RSVD1__##e)
+#define BFM_GPMI_TIMING0_RSVD1_V(v)         BM_GPMI_TIMING0_RSVD1
+#define BP_GPMI_TIMING0_ADDRESS_SETUP       16
+#define BM_GPMI_TIMING0_ADDRESS_SETUP       0xff0000
+#define BF_GPMI_TIMING0_ADDRESS_SETUP(v)    (((v) & 0xff) << 16)
+#define BFM_GPMI_TIMING0_ADDRESS_SETUP(v)   BM_GPMI_TIMING0_ADDRESS_SETUP
+#define BF_GPMI_TIMING0_ADDRESS_SETUP_V(e)  BF_GPMI_TIMING0_ADDRESS_SETUP(BV_GPMI_TIMING0_ADDRESS_SETUP__##e)
+#define BFM_GPMI_TIMING0_ADDRESS_SETUP_V(v) BM_GPMI_TIMING0_ADDRESS_SETUP
+#define BP_GPMI_TIMING0_DATA_HOLD           8
+#define BM_GPMI_TIMING0_DATA_HOLD           0xff00
+#define BF_GPMI_TIMING0_DATA_HOLD(v)        (((v) & 0xff) << 8)
+#define BFM_GPMI_TIMING0_DATA_HOLD(v)       BM_GPMI_TIMING0_DATA_HOLD
+#define BF_GPMI_TIMING0_DATA_HOLD_V(e)      BF_GPMI_TIMING0_DATA_HOLD(BV_GPMI_TIMING0_DATA_HOLD__##e)
+#define BFM_GPMI_TIMING0_DATA_HOLD_V(v)     BM_GPMI_TIMING0_DATA_HOLD
+#define BP_GPMI_TIMING0_DATA_SETUP          0
+#define BM_GPMI_TIMING0_DATA_SETUP          0xff
+#define BF_GPMI_TIMING0_DATA_SETUP(v)       (((v) & 0xff) << 0)
+#define BFM_GPMI_TIMING0_DATA_SETUP(v)      BM_GPMI_TIMING0_DATA_SETUP
+#define BF_GPMI_TIMING0_DATA_SETUP_V(e)     BF_GPMI_TIMING0_DATA_SETUP(BV_GPMI_TIMING0_DATA_SETUP__##e)
+#define BFM_GPMI_TIMING0_DATA_SETUP_V(v)    BM_GPMI_TIMING0_DATA_SETUP
+
+#define HW_GPMI_TIMING1                             HW(GPMI_TIMING1)
+#define HWA_GPMI_TIMING1                            (0x8000c000 + 0x80)
+#define HWT_GPMI_TIMING1                            HWIO_32_RW
+#define HWN_GPMI_TIMING1                            GPMI_TIMING1
+#define HWI_GPMI_TIMING1                            
+#define BP_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT         16
+#define BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT         0xffff0000
+#define BF_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(v)      (((v) & 0xffff) << 16)
+#define BFM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(v)     BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT
+#define BF_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_V(e)    BF_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(BV_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT__##e)
+#define BFM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_V(v)   BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT
+#define BP_GPMI_TIMING1_RSVD1                       0
+#define BM_GPMI_TIMING1_RSVD1                       0xffff
+#define BF_GPMI_TIMING1_RSVD1(v)                    (((v) & 0xffff) << 0)
+#define BFM_GPMI_TIMING1_RSVD1(v)                   BM_GPMI_TIMING1_RSVD1
+#define BF_GPMI_TIMING1_RSVD1_V(e)                  BF_GPMI_TIMING1_RSVD1(BV_GPMI_TIMING1_RSVD1__##e)
+#define BFM_GPMI_TIMING1_RSVD1_V(v)                 BM_GPMI_TIMING1_RSVD1
+
+#define HW_GPMI_TIMING2                     HW(GPMI_TIMING2)
+#define HWA_GPMI_TIMING2                    (0x8000c000 + 0x90)
+#define HWT_GPMI_TIMING2                    HWIO_32_RW
+#define HWN_GPMI_TIMING2                    GPMI_TIMING2
+#define HWI_GPMI_TIMING2                    
+#define BP_GPMI_TIMING2_UDMA_TRP            24
+#define BM_GPMI_TIMING2_UDMA_TRP            0xff000000
+#define BF_GPMI_TIMING2_UDMA_TRP(v)         (((v) & 0xff) << 24)
+#define BFM_GPMI_TIMING2_UDMA_TRP(v)        BM_GPMI_TIMING2_UDMA_TRP
+#define BF_GPMI_TIMING2_UDMA_TRP_V(e)       BF_GPMI_TIMING2_UDMA_TRP(BV_GPMI_TIMING2_UDMA_TRP__##e)
+#define BFM_GPMI_TIMING2_UDMA_TRP_V(v)      BM_GPMI_TIMING2_UDMA_TRP
+#define BP_GPMI_TIMING2_UDMA_ENV            16
+#define BM_GPMI_TIMING2_UDMA_ENV            0xff0000
+#define BF_GPMI_TIMING2_UDMA_ENV(v)         (((v) & 0xff) << 16)
+#define BFM_GPMI_TIMING2_UDMA_ENV(v)        BM_GPMI_TIMING2_UDMA_ENV
+#define BF_GPMI_TIMING2_UDMA_ENV_V(e)       BF_GPMI_TIMING2_UDMA_ENV(BV_GPMI_TIMING2_UDMA_ENV__##e)
+#define BFM_GPMI_TIMING2_UDMA_ENV_V(v)      BM_GPMI_TIMING2_UDMA_ENV
+#define BP_GPMI_TIMING2_UDMA_HOLD           8
+#define BM_GPMI_TIMING2_UDMA_HOLD           0xff00
+#define BF_GPMI_TIMING2_UDMA_HOLD(v)        (((v) & 0xff) << 8)
+#define BFM_GPMI_TIMING2_UDMA_HOLD(v)       BM_GPMI_TIMING2_UDMA_HOLD
+#define BF_GPMI_TIMING2_UDMA_HOLD_V(e)      BF_GPMI_TIMING2_UDMA_HOLD(BV_GPMI_TIMING2_UDMA_HOLD__##e)
+#define BFM_GPMI_TIMING2_UDMA_HOLD_V(v)     BM_GPMI_TIMING2_UDMA_HOLD
+#define BP_GPMI_TIMING2_UDMA_SETUP          0
+#define BM_GPMI_TIMING2_UDMA_SETUP          0xff
+#define BF_GPMI_TIMING2_UDMA_SETUP(v)       (((v) & 0xff) << 0)
+#define BFM_GPMI_TIMING2_UDMA_SETUP(v)      BM_GPMI_TIMING2_UDMA_SETUP
+#define BF_GPMI_TIMING2_UDMA_SETUP_V(e)     BF_GPMI_TIMING2_UDMA_SETUP(BV_GPMI_TIMING2_UDMA_SETUP__##e)
+#define BFM_GPMI_TIMING2_UDMA_SETUP_V(v)    BM_GPMI_TIMING2_UDMA_SETUP
+
+#define HW_GPMI_DATA            HW(GPMI_DATA)
+#define HWA_GPMI_DATA           (0x8000c000 + 0xa0)
+#define HWT_GPMI_DATA           HWIO_32_RW
+#define HWN_GPMI_DATA           GPMI_DATA
+#define HWI_GPMI_DATA           
+#define BP_GPMI_DATA_DATA       0
+#define BM_GPMI_DATA_DATA       0xffffffff
+#define BF_GPMI_DATA_DATA(v)    (((v) & 0xffffffff) << 0)
+#define BFM_GPMI_DATA_DATA(v)   BM_GPMI_DATA_DATA
+#define BF_GPMI_DATA_DATA_V(e)  BF_GPMI_DATA_DATA(BV_GPMI_DATA_DATA__##e)
+#define BFM_GPMI_DATA_DATA_V(v) BM_GPMI_DATA_DATA
+
+#define HW_GPMI_STAT                            HW(GPMI_STAT)
+#define HWA_GPMI_STAT                           (0x8000c000 + 0xb0)
+#define HWT_GPMI_STAT                           HWIO_32_RW
+#define HWN_GPMI_STAT                           GPMI_STAT
+#define HWI_GPMI_STAT                           
+#define BP_GPMI_STAT_PRESENT                    31
+#define BM_GPMI_STAT_PRESENT                    0x80000000
+#define BV_GPMI_STAT_PRESENT__UNAVAILABLE       0x0
+#define BV_GPMI_STAT_PRESENT__AVAILABLE         0x1
+#define BF_GPMI_STAT_PRESENT(v)                 (((v) & 0x1) << 31)
+#define BFM_GPMI_STAT_PRESENT(v)                BM_GPMI_STAT_PRESENT
+#define BF_GPMI_STAT_PRESENT_V(e)               BF_GPMI_STAT_PRESENT(BV_GPMI_STAT_PRESENT__##e)
+#define BFM_GPMI_STAT_PRESENT_V(v)              BM_GPMI_STAT_PRESENT
+#define BP_GPMI_STAT_RSVD1                      12
+#define BM_GPMI_STAT_RSVD1                      0x7ffff000
+#define BF_GPMI_STAT_RSVD1(v)                   (((v) & 0x7ffff) << 12)
+#define BFM_GPMI_STAT_RSVD1(v)                  BM_GPMI_STAT_RSVD1
+#define BF_GPMI_STAT_RSVD1_V(e)                 BF_GPMI_STAT_RSVD1(BV_GPMI_STAT_RSVD1__##e)
+#define BFM_GPMI_STAT_RSVD1_V(v)                BM_GPMI_STAT_RSVD1
+#define BP_GPMI_STAT_RDY_TIMEOUT                8
+#define BM_GPMI_STAT_RDY_TIMEOUT                0xf00
+#define BF_GPMI_STAT_RDY_TIMEOUT(v)             (((v) & 0xf) << 8)
+#define BFM_GPMI_STAT_RDY_TIMEOUT(v)            BM_GPMI_STAT_RDY_TIMEOUT
+#define BF_GPMI_STAT_RDY_TIMEOUT_V(e)           BF_GPMI_STAT_RDY_TIMEOUT(BV_GPMI_STAT_RDY_TIMEOUT__##e)
+#define BFM_GPMI_STAT_RDY_TIMEOUT_V(v)          BM_GPMI_STAT_RDY_TIMEOUT
+#define BP_GPMI_STAT_ATA_IRQ                    7
+#define BM_GPMI_STAT_ATA_IRQ                    0x80
+#define BF_GPMI_STAT_ATA_IRQ(v)                 (((v) & 0x1) << 7)
+#define BFM_GPMI_STAT_ATA_IRQ(v)                BM_GPMI_STAT_ATA_IRQ
+#define BF_GPMI_STAT_ATA_IRQ_V(e)               BF_GPMI_STAT_ATA_IRQ(BV_GPMI_STAT_ATA_IRQ__##e)
+#define BFM_GPMI_STAT_ATA_IRQ_V(v)              BM_GPMI_STAT_ATA_IRQ
+#define BP_GPMI_STAT_INVALID_BUFFER_MASK        6
+#define BM_GPMI_STAT_INVALID_BUFFER_MASK        0x40
+#define BF_GPMI_STAT_INVALID_BUFFER_MASK(v)     (((v) & 0x1) << 6)
+#define BFM_GPMI_STAT_INVALID_BUFFER_MASK(v)    BM_GPMI_STAT_INVALID_BUFFER_MASK
+#define BF_GPMI_STAT_INVALID_BUFFER_MASK_V(e)   BF_GPMI_STAT_INVALID_BUFFER_MASK(BV_GPMI_STAT_INVALID_BUFFER_MASK__##e)
+#define BFM_GPMI_STAT_INVALID_BUFFER_MASK_V(v)  BM_GPMI_STAT_INVALID_BUFFER_MASK
+#define BP_GPMI_STAT_FIFO_EMPTY                 5
+#define BM_GPMI_STAT_FIFO_EMPTY                 0x20
+#define BV_GPMI_STAT_FIFO_EMPTY__NOT_EMPTY      0x0
+#define BV_GPMI_STAT_FIFO_EMPTY__EMPTY          0x1
+#define BF_GPMI_STAT_FIFO_EMPTY(v)              (((v) & 0x1) << 5)
+#define BFM_GPMI_STAT_FIFO_EMPTY(v)             BM_GPMI_STAT_FIFO_EMPTY
+#define BF_GPMI_STAT_FIFO_EMPTY_V(e)            BF_GPMI_STAT_FIFO_EMPTY(BV_GPMI_STAT_FIFO_EMPTY__##e)
+#define BFM_GPMI_STAT_FIFO_EMPTY_V(v)           BM_GPMI_STAT_FIFO_EMPTY
+#define BP_GPMI_STAT_FIFO_FULL                  4
+#define BM_GPMI_STAT_FIFO_FULL                  0x10
+#define BV_GPMI_STAT_FIFO_FULL__NOT_FULL        0x0
+#define BV_GPMI_STAT_FIFO_FULL__FULL            0x1
+#define BF_GPMI_STAT_FIFO_FULL(v)               (((v) & 0x1) << 4)
+#define BFM_GPMI_STAT_FIFO_FULL(v)              BM_GPMI_STAT_FIFO_FULL
+#define BF_GPMI_STAT_FIFO_FULL_V(e)             BF_GPMI_STAT_FIFO_FULL(BV_GPMI_STAT_FIFO_FULL__##e)
+#define BFM_GPMI_STAT_FIFO_FULL_V(v)            BM_GPMI_STAT_FIFO_FULL
+#define BP_GPMI_STAT_DEV3_ERROR                 3
+#define BM_GPMI_STAT_DEV3_ERROR                 0x8
+#define BF_GPMI_STAT_DEV3_ERROR(v)              (((v) & 0x1) << 3)
+#define BFM_GPMI_STAT_DEV3_ERROR(v)             BM_GPMI_STAT_DEV3_ERROR
+#define BF_GPMI_STAT_DEV3_ERROR_V(e)            BF_GPMI_STAT_DEV3_ERROR(BV_GPMI_STAT_DEV3_ERROR__##e)
+#define BFM_GPMI_STAT_DEV3_ERROR_V(v)           BM_GPMI_STAT_DEV3_ERROR
+#define BP_GPMI_STAT_DEV2_ERROR                 2
+#define BM_GPMI_STAT_DEV2_ERROR                 0x4
+#define BF_GPMI_STAT_DEV2_ERROR(v)              (((v) & 0x1) << 2)
+#define BFM_GPMI_STAT_DEV2_ERROR(v)             BM_GPMI_STAT_DEV2_ERROR
+#define BF_GPMI_STAT_DEV2_ERROR_V(e)            BF_GPMI_STAT_DEV2_ERROR(BV_GPMI_STAT_DEV2_ERROR__##e)
+#define BFM_GPMI_STAT_DEV2_ERROR_V(v)           BM_GPMI_STAT_DEV2_ERROR
+#define BP_GPMI_STAT_DEV1_ERROR                 1
+#define BM_GPMI_STAT_DEV1_ERROR                 0x2
+#define BF_GPMI_STAT_DEV1_ERROR(v)              (((v) & 0x1) << 1)
+#define BFM_GPMI_STAT_DEV1_ERROR(v)             BM_GPMI_STAT_DEV1_ERROR
+#define BF_GPMI_STAT_DEV1_ERROR_V(e)            BF_GPMI_STAT_DEV1_ERROR(BV_GPMI_STAT_DEV1_ERROR__##e)
+#define BFM_GPMI_STAT_DEV1_ERROR_V(v)           BM_GPMI_STAT_DEV1_ERROR
+#define BP_GPMI_STAT_DEV0_ERROR                 0
+#define BM_GPMI_STAT_DEV0_ERROR                 0x1
+#define BF_GPMI_STAT_DEV0_ERROR(v)              (((v) & 0x1) << 0)
+#define BFM_GPMI_STAT_DEV0_ERROR(v)             BM_GPMI_STAT_DEV0_ERROR
+#define BF_GPMI_STAT_DEV0_ERROR_V(e)            BF_GPMI_STAT_DEV0_ERROR(BV_GPMI_STAT_DEV0_ERROR__##e)
+#define BFM_GPMI_STAT_DEV0_ERROR_V(v)           BM_GPMI_STAT_DEV0_ERROR
+
+#define HW_GPMI_DEBUG                           HW(GPMI_DEBUG)
+#define HWA_GPMI_DEBUG                          (0x8000c000 + 0xc0)
+#define HWT_GPMI_DEBUG                          HWIO_32_RW
+#define HWN_GPMI_DEBUG                          GPMI_DEBUG
+#define HWI_GPMI_DEBUG                          
+#define BP_GPMI_DEBUG_READY3                    31
+#define BM_GPMI_DEBUG_READY3                    0x80000000
+#define BF_GPMI_DEBUG_READY3(v)                 (((v) & 0x1) << 31)
+#define BFM_GPMI_DEBUG_READY3(v)                BM_GPMI_DEBUG_READY3
+#define BF_GPMI_DEBUG_READY3_V(e)               BF_GPMI_DEBUG_READY3(BV_GPMI_DEBUG_READY3__##e)
+#define BFM_GPMI_DEBUG_READY3_V(v)              BM_GPMI_DEBUG_READY3
+#define BP_GPMI_DEBUG_READY2                    30
+#define BM_GPMI_DEBUG_READY2                    0x40000000
+#define BF_GPMI_DEBUG_READY2(v)                 (((v) & 0x1) << 30)
+#define BFM_GPMI_DEBUG_READY2(v)                BM_GPMI_DEBUG_READY2
+#define BF_GPMI_DEBUG_READY2_V(e)               BF_GPMI_DEBUG_READY2(BV_GPMI_DEBUG_READY2__##e)
+#define BFM_GPMI_DEBUG_READY2_V(v)              BM_GPMI_DEBUG_READY2
+#define BP_GPMI_DEBUG_READY1                    29
+#define BM_GPMI_DEBUG_READY1                    0x20000000
+#define BF_GPMI_DEBUG_READY1(v)                 (((v) & 0x1) << 29)
+#define BFM_GPMI_DEBUG_READY1(v)                BM_GPMI_DEBUG_READY1
+#define BF_GPMI_DEBUG_READY1_V(e)               BF_GPMI_DEBUG_READY1(BV_GPMI_DEBUG_READY1__##e)
+#define BFM_GPMI_DEBUG_READY1_V(v)              BM_GPMI_DEBUG_READY1
+#define BP_GPMI_DEBUG_READY0                    28
+#define BM_GPMI_DEBUG_READY0                    0x10000000
+#define BF_GPMI_DEBUG_READY0(v)                 (((v) & 0x1) << 28)
+#define BFM_GPMI_DEBUG_READY0(v)                BM_GPMI_DEBUG_READY0
+#define BF_GPMI_DEBUG_READY0_V(e)               BF_GPMI_DEBUG_READY0(BV_GPMI_DEBUG_READY0__##e)
+#define BFM_GPMI_DEBUG_READY0_V(v)              BM_GPMI_DEBUG_READY0
+#define BP_GPMI_DEBUG_WAIT_FOR_READY_END3       27
+#define BM_GPMI_DEBUG_WAIT_FOR_READY_END3       0x8000000
+#define BF_GPMI_DEBUG_WAIT_FOR_READY_END3(v)    (((v) & 0x1) << 27)
+#define BFM_GPMI_DEBUG_WAIT_FOR_READY_END3(v)   BM_GPMI_DEBUG_WAIT_FOR_READY_END3
+#define BF_GPMI_DEBUG_WAIT_FOR_READY_END3_V(e)  BF_GPMI_DEBUG_WAIT_FOR_READY_END3(BV_GPMI_DEBUG_WAIT_FOR_READY_END3__##e)
+#define BFM_GPMI_DEBUG_WAIT_FOR_READY_END3_V(v) BM_GPMI_DEBUG_WAIT_FOR_READY_END3
+#define BP_GPMI_DEBUG_WAIT_FOR_READY_END2       26
+#define BM_GPMI_DEBUG_WAIT_FOR_READY_END2       0x4000000
+#define BF_GPMI_DEBUG_WAIT_FOR_READY_END2(v)    (((v) & 0x1) << 26)
+#define BFM_GPMI_DEBUG_WAIT_FOR_READY_END2(v)   BM_GPMI_DEBUG_WAIT_FOR_READY_END2
+#define BF_GPMI_DEBUG_WAIT_FOR_READY_END2_V(e)  BF_GPMI_DEBUG_WAIT_FOR_READY_END2(BV_GPMI_DEBUG_WAIT_FOR_READY_END2__##e)
+#define BFM_GPMI_DEBUG_WAIT_FOR_READY_END2_V(v) BM_GPMI_DEBUG_WAIT_FOR_READY_END2
+#define BP_GPMI_DEBUG_WAIT_FOR_READY_END1       25
+#define BM_GPMI_DEBUG_WAIT_FOR_READY_END1       0x2000000
+#define BF_GPMI_DEBUG_WAIT_FOR_READY_END1(v)    (((v) & 0x1) << 25)
+#define BFM_GPMI_DEBUG_WAIT_FOR_READY_END1(v)   BM_GPMI_DEBUG_WAIT_FOR_READY_END1
+#define BF_GPMI_DEBUG_WAIT_FOR_READY_END1_V(e)  BF_GPMI_DEBUG_WAIT_FOR_READY_END1(BV_GPMI_DEBUG_WAIT_FOR_READY_END1__##e)
+#define BFM_GPMI_DEBUG_WAIT_FOR_READY_END1_V(v) BM_GPMI_DEBUG_WAIT_FOR_READY_END1
+#define BP_GPMI_DEBUG_WAIT_FOR_READY_END0       24
+#define BM_GPMI_DEBUG_WAIT_FOR_READY_END0       0x1000000
+#define BF_GPMI_DEBUG_WAIT_FOR_READY_END0(v)    (((v) & 0x1) << 24)
+#define BFM_GPMI_DEBUG_WAIT_FOR_READY_END0(v)   BM_GPMI_DEBUG_WAIT_FOR_READY_END0
+#define BF_GPMI_DEBUG_WAIT_FOR_READY_END0_V(e)  BF_GPMI_DEBUG_WAIT_FOR_READY_END0(BV_GPMI_DEBUG_WAIT_FOR_READY_END0__##e)
+#define BFM_GPMI_DEBUG_WAIT_FOR_READY_END0_V(v) BM_GPMI_DEBUG_WAIT_FOR_READY_END0
+#define BP_GPMI_DEBUG_SENSE3                    23
+#define BM_GPMI_DEBUG_SENSE3                    0x800000
+#define BF_GPMI_DEBUG_SENSE3(v)                 (((v) & 0x1) << 23)
+#define BFM_GPMI_DEBUG_SENSE3(v)                BM_GPMI_DEBUG_SENSE3
+#define BF_GPMI_DEBUG_SENSE3_V(e)               BF_GPMI_DEBUG_SENSE3(BV_GPMI_DEBUG_SENSE3__##e)
+#define BFM_GPMI_DEBUG_SENSE3_V(v)              BM_GPMI_DEBUG_SENSE3
+#define BP_GPMI_DEBUG_SENSE2                    22
+#define BM_GPMI_DEBUG_SENSE2                    0x400000
+#define BF_GPMI_DEBUG_SENSE2(v)                 (((v) & 0x1) << 22)
+#define BFM_GPMI_DEBUG_SENSE2(v)                BM_GPMI_DEBUG_SENSE2
+#define BF_GPMI_DEBUG_SENSE2_V(e)               BF_GPMI_DEBUG_SENSE2(BV_GPMI_DEBUG_SENSE2__##e)
+#define BFM_GPMI_DEBUG_SENSE2_V(v)              BM_GPMI_DEBUG_SENSE2
+#define BP_GPMI_DEBUG_SENSE1                    21
+#define BM_GPMI_DEBUG_SENSE1                    0x200000
+#define BF_GPMI_DEBUG_SENSE1(v)                 (((v) & 0x1) << 21)
+#define BFM_GPMI_DEBUG_SENSE1(v)                BM_GPMI_DEBUG_SENSE1
+#define BF_GPMI_DEBUG_SENSE1_V(e)               BF_GPMI_DEBUG_SENSE1(BV_GPMI_DEBUG_SENSE1__##e)
+#define BFM_GPMI_DEBUG_SENSE1_V(v)              BM_GPMI_DEBUG_SENSE1
+#define BP_GPMI_DEBUG_SENSE0                    20
+#define BM_GPMI_DEBUG_SENSE0                    0x100000
+#define BF_GPMI_DEBUG_SENSE0(v)                 (((v) & 0x1) << 20)
+#define BFM_GPMI_DEBUG_SENSE0(v)                BM_GPMI_DEBUG_SENSE0
+#define BF_GPMI_DEBUG_SENSE0_V(e)               BF_GPMI_DEBUG_SENSE0(BV_GPMI_DEBUG_SENSE0__##e)
+#define BFM_GPMI_DEBUG_SENSE0_V(v)              BM_GPMI_DEBUG_SENSE0
+#define BP_GPMI_DEBUG_DMAREQ3                   19
+#define BM_GPMI_DEBUG_DMAREQ3                   0x80000
+#define BF_GPMI_DEBUG_DMAREQ3(v)                (((v) & 0x1) << 19)
+#define BFM_GPMI_DEBUG_DMAREQ3(v)               BM_GPMI_DEBUG_DMAREQ3
+#define BF_GPMI_DEBUG_DMAREQ3_V(e)              BF_GPMI_DEBUG_DMAREQ3(BV_GPMI_DEBUG_DMAREQ3__##e)
+#define BFM_GPMI_DEBUG_DMAREQ3_V(v)             BM_GPMI_DEBUG_DMAREQ3
+#define BP_GPMI_DEBUG_DMAREQ2                   18
+#define BM_GPMI_DEBUG_DMAREQ2                   0x40000
+#define BF_GPMI_DEBUG_DMAREQ2(v)                (((v) & 0x1) << 18)
+#define BFM_GPMI_DEBUG_DMAREQ2(v)               BM_GPMI_DEBUG_DMAREQ2
+#define BF_GPMI_DEBUG_DMAREQ2_V(e)              BF_GPMI_DEBUG_DMAREQ2(BV_GPMI_DEBUG_DMAREQ2__##e)
+#define BFM_GPMI_DEBUG_DMAREQ2_V(v)             BM_GPMI_DEBUG_DMAREQ2
+#define BP_GPMI_DEBUG_DMAREQ1                   17
+#define BM_GPMI_DEBUG_DMAREQ1                   0x20000
+#define BF_GPMI_DEBUG_DMAREQ1(v)                (((v) & 0x1) << 17)
+#define BFM_GPMI_DEBUG_DMAREQ1(v)               BM_GPMI_DEBUG_DMAREQ1
+#define BF_GPMI_DEBUG_DMAREQ1_V(e)              BF_GPMI_DEBUG_DMAREQ1(BV_GPMI_DEBUG_DMAREQ1__##e)
+#define BFM_GPMI_DEBUG_DMAREQ1_V(v)             BM_GPMI_DEBUG_DMAREQ1
+#define BP_GPMI_DEBUG_DMAREQ0                   16
+#define BM_GPMI_DEBUG_DMAREQ0                   0x10000
+#define BF_GPMI_DEBUG_DMAREQ0(v)                (((v) & 0x1) << 16)
+#define BFM_GPMI_DEBUG_DMAREQ0(v)               BM_GPMI_DEBUG_DMAREQ0
+#define BF_GPMI_DEBUG_DMAREQ0_V(e)              BF_GPMI_DEBUG_DMAREQ0(BV_GPMI_DEBUG_DMAREQ0__##e)
+#define BFM_GPMI_DEBUG_DMAREQ0_V(v)             BM_GPMI_DEBUG_DMAREQ0
+#define BP_GPMI_DEBUG_CMD_END                   12
+#define BM_GPMI_DEBUG_CMD_END                   0xf000
+#define BF_GPMI_DEBUG_CMD_END(v)                (((v) & 0xf) << 12)
+#define BFM_GPMI_DEBUG_CMD_END(v)               BM_GPMI_DEBUG_CMD_END
+#define BF_GPMI_DEBUG_CMD_END_V(e)              BF_GPMI_DEBUG_CMD_END(BV_GPMI_DEBUG_CMD_END__##e)
+#define BFM_GPMI_DEBUG_CMD_END_V(v)             BM_GPMI_DEBUG_CMD_END
+#define BP_GPMI_DEBUG_UDMA_STATE                8
+#define BM_GPMI_DEBUG_UDMA_STATE                0xf00
+#define BF_GPMI_DEBUG_UDMA_STATE(v)             (((v) & 0xf) << 8)
+#define BFM_GPMI_DEBUG_UDMA_STATE(v)            BM_GPMI_DEBUG_UDMA_STATE
+#define BF_GPMI_DEBUG_UDMA_STATE_V(e)           BF_GPMI_DEBUG_UDMA_STATE(BV_GPMI_DEBUG_UDMA_STATE__##e)
+#define BFM_GPMI_DEBUG_UDMA_STATE_V(v)          BM_GPMI_DEBUG_UDMA_STATE
+#define BP_GPMI_DEBUG_BUSY                      7
+#define BM_GPMI_DEBUG_BUSY                      0x80
+#define BV_GPMI_DEBUG_BUSY__DISABLED            0x0
+#define BV_GPMI_DEBUG_BUSY__ENABLED             0x1
+#define BF_GPMI_DEBUG_BUSY(v)                   (((v) & 0x1) << 7)
+#define BFM_GPMI_DEBUG_BUSY(v)                  BM_GPMI_DEBUG_BUSY
+#define BF_GPMI_DEBUG_BUSY_V(e)                 BF_GPMI_DEBUG_BUSY(BV_GPMI_DEBUG_BUSY__##e)
+#define BFM_GPMI_DEBUG_BUSY_V(v)                BM_GPMI_DEBUG_BUSY
+#define BP_GPMI_DEBUG_PIN_STATE                 4
+#define BM_GPMI_DEBUG_PIN_STATE                 0x70
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_IDLE       0x0
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_BYTCNT     0x1
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_ADDR       0x2
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_STALL      0x3
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_STROBE     0x4
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_ATARDY     0x5
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_DHOLD      0x6
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_DONE       0x7
+#define BF_GPMI_DEBUG_PIN_STATE(v)              (((v) & 0x7) << 4)
+#define BFM_GPMI_DEBUG_PIN_STATE(v)             BM_GPMI_DEBUG_PIN_STATE
+#define BF_GPMI_DEBUG_PIN_STATE_V(e)            BF_GPMI_DEBUG_PIN_STATE(BV_GPMI_DEBUG_PIN_STATE__##e)
+#define BFM_GPMI_DEBUG_PIN_STATE_V(v)           BM_GPMI_DEBUG_PIN_STATE
+#define BP_GPMI_DEBUG_MAIN_STATE                0
+#define BM_GPMI_DEBUG_MAIN_STATE                0xf
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_IDLE      0x0
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_BYTCNT    0x1
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFE    0x2
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFR    0x3
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_DMAREQ    0x4
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_DMAACK    0x5
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFF    0x6
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_LDFIFO    0x7
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_LDDMAR    0x8
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_RDCMP     0x9
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_DONE      0xa
+#define BF_GPMI_DEBUG_MAIN_STATE(v)             (((v) & 0xf) << 0)
+#define BFM_GPMI_DEBUG_MAIN_STATE(v)            BM_GPMI_DEBUG_MAIN_STATE
+#define BF_GPMI_DEBUG_MAIN_STATE_V(e)           BF_GPMI_DEBUG_MAIN_STATE(BV_GPMI_DEBUG_MAIN_STATE__##e)
+#define BFM_GPMI_DEBUG_MAIN_STATE_V(v)          BM_GPMI_DEBUG_MAIN_STATE
+
+#define HW_GPMI_VERSION             HW(GPMI_VERSION)
+#define HWA_GPMI_VERSION            (0x8000c000 + 0xd0)
+#define HWT_GPMI_VERSION            HWIO_32_RW
+#define HWN_GPMI_VERSION            GPMI_VERSION
+#define HWI_GPMI_VERSION            
+#define BP_GPMI_VERSION_MAJOR       24
+#define BM_GPMI_VERSION_MAJOR       0xff000000
+#define BF_GPMI_VERSION_MAJOR(v)    (((v) & 0xff) << 24)
+#define BFM_GPMI_VERSION_MAJOR(v)   BM_GPMI_VERSION_MAJOR
+#define BF_GPMI_VERSION_MAJOR_V(e)  BF_GPMI_VERSION_MAJOR(BV_GPMI_VERSION_MAJOR__##e)
+#define BFM_GPMI_VERSION_MAJOR_V(v) BM_GPMI_VERSION_MAJOR
+#define BP_GPMI_VERSION_MINOR       16
+#define BM_GPMI_VERSION_MINOR       0xff0000
+#define BF_GPMI_VERSION_MINOR(v)    (((v) & 0xff) << 16)
+#define BFM_GPMI_VERSION_MINOR(v)   BM_GPMI_VERSION_MINOR
+#define BF_GPMI_VERSION_MINOR_V(e)  BF_GPMI_VERSION_MINOR(BV_GPMI_VERSION_MINOR__##e)
+#define BFM_GPMI_VERSION_MINOR_V(v) BM_GPMI_VERSION_MINOR
+#define BP_GPMI_VERSION_STEP        0
+#define BM_GPMI_VERSION_STEP        0xffff
+#define BF_GPMI_VERSION_STEP(v)     (((v) & 0xffff) << 0)
+#define BFM_GPMI_VERSION_STEP(v)    BM_GPMI_VERSION_STEP
+#define BF_GPMI_VERSION_STEP_V(e)   BF_GPMI_VERSION_STEP(BV_GPMI_VERSION_STEP__##e)
+#define BFM_GPMI_VERSION_STEP_V(v)  BM_GPMI_VERSION_STEP
+
+#define HW_GPMI_DEBUG2                          HW(GPMI_DEBUG2)
+#define HWA_GPMI_DEBUG2                         (0x8000c000 + 0xe0)
+#define HWT_GPMI_DEBUG2                         HWIO_32_RW
+#define HWN_GPMI_DEBUG2                         GPMI_DEBUG2
+#define HWI_GPMI_DEBUG2                         
+#define BP_GPMI_DEBUG2_RSVD1                    16
+#define BM_GPMI_DEBUG2_RSVD1                    0xffff0000
+#define BF_GPMI_DEBUG2_RSVD1(v)                 (((v) & 0xffff) << 16)
+#define BFM_GPMI_DEBUG2_RSVD1(v)                BM_GPMI_DEBUG2_RSVD1
+#define BF_GPMI_DEBUG2_RSVD1_V(e)               BF_GPMI_DEBUG2_RSVD1(BV_GPMI_DEBUG2_RSVD1__##e)
+#define BFM_GPMI_DEBUG2_RSVD1_V(v)              BM_GPMI_DEBUG2_RSVD1
+#define BP_GPMI_DEBUG2_SYND2GPMI_BE             12
+#define BM_GPMI_DEBUG2_SYND2GPMI_BE             0xf000
+#define BF_GPMI_DEBUG2_SYND2GPMI_BE(v)          (((v) & 0xf) << 12)
+#define BFM_GPMI_DEBUG2_SYND2GPMI_BE(v)         BM_GPMI_DEBUG2_SYND2GPMI_BE
+#define BF_GPMI_DEBUG2_SYND2GPMI_BE_V(e)        BF_GPMI_DEBUG2_SYND2GPMI_BE(BV_GPMI_DEBUG2_SYND2GPMI_BE__##e)
+#define BFM_GPMI_DEBUG2_SYND2GPMI_BE_V(v)       BM_GPMI_DEBUG2_SYND2GPMI_BE
+#define BP_GPMI_DEBUG2_GPMI2SYND_VALID          11
+#define BM_GPMI_DEBUG2_GPMI2SYND_VALID          0x800
+#define BF_GPMI_DEBUG2_GPMI2SYND_VALID(v)       (((v) & 0x1) << 11)
+#define BFM_GPMI_DEBUG2_GPMI2SYND_VALID(v)      BM_GPMI_DEBUG2_GPMI2SYND_VALID
+#define BF_GPMI_DEBUG2_GPMI2SYND_VALID_V(e)     BF_GPMI_DEBUG2_GPMI2SYND_VALID(BV_GPMI_DEBUG2_GPMI2SYND_VALID__##e)
+#define BFM_GPMI_DEBUG2_GPMI2SYND_VALID_V(v)    BM_GPMI_DEBUG2_GPMI2SYND_VALID
+#define BP_GPMI_DEBUG2_GPMI2SYND_READY          10
+#define BM_GPMI_DEBUG2_GPMI2SYND_READY          0x400
+#define BF_GPMI_DEBUG2_GPMI2SYND_READY(v)       (((v) & 0x1) << 10)
+#define BFM_GPMI_DEBUG2_GPMI2SYND_READY(v)      BM_GPMI_DEBUG2_GPMI2SYND_READY
+#define BF_GPMI_DEBUG2_GPMI2SYND_READY_V(e)     BF_GPMI_DEBUG2_GPMI2SYND_READY(BV_GPMI_DEBUG2_GPMI2SYND_READY__##e)
+#define BFM_GPMI_DEBUG2_GPMI2SYND_READY_V(v)    BM_GPMI_DEBUG2_GPMI2SYND_READY
+#define BP_GPMI_DEBUG2_SYND2GPMI_VALID          9
+#define BM_GPMI_DEBUG2_SYND2GPMI_VALID          0x200
+#define BF_GPMI_DEBUG2_SYND2GPMI_VALID(v)       (((v) & 0x1) << 9)
+#define BFM_GPMI_DEBUG2_SYND2GPMI_VALID(v)      BM_GPMI_DEBUG2_SYND2GPMI_VALID
+#define BF_GPMI_DEBUG2_SYND2GPMI_VALID_V(e)     BF_GPMI_DEBUG2_SYND2GPMI_VALID(BV_GPMI_DEBUG2_SYND2GPMI_VALID__##e)
+#define BFM_GPMI_DEBUG2_SYND2GPMI_VALID_V(v)    BM_GPMI_DEBUG2_SYND2GPMI_VALID
+#define BP_GPMI_DEBUG2_SYND2GPMI_READY          8
+#define BM_GPMI_DEBUG2_SYND2GPMI_READY          0x100
+#define BF_GPMI_DEBUG2_SYND2GPMI_READY(v)       (((v) & 0x1) << 8)
+#define BFM_GPMI_DEBUG2_SYND2GPMI_READY(v)      BM_GPMI_DEBUG2_SYND2GPMI_READY
+#define BF_GPMI_DEBUG2_SYND2GPMI_READY_V(e)     BF_GPMI_DEBUG2_SYND2GPMI_READY(BV_GPMI_DEBUG2_SYND2GPMI_READY__##e)
+#define BFM_GPMI_DEBUG2_SYND2GPMI_READY_V(v)    BM_GPMI_DEBUG2_SYND2GPMI_READY
+#define BP_GPMI_DEBUG2_VIEW_DELAYED_RDN         7
+#define BM_GPMI_DEBUG2_VIEW_DELAYED_RDN         0x80
+#define BF_GPMI_DEBUG2_VIEW_DELAYED_RDN(v)      (((v) & 0x1) << 7)
+#define BFM_GPMI_DEBUG2_VIEW_DELAYED_RDN(v)     BM_GPMI_DEBUG2_VIEW_DELAYED_RDN
+#define BF_GPMI_DEBUG2_VIEW_DELAYED_RDN_V(e)    BF_GPMI_DEBUG2_VIEW_DELAYED_RDN(BV_GPMI_DEBUG2_VIEW_DELAYED_RDN__##e)
+#define BFM_GPMI_DEBUG2_VIEW_DELAYED_RDN_V(v)   BM_GPMI_DEBUG2_VIEW_DELAYED_RDN
+#define BP_GPMI_DEBUG2_UPDATE_WINDOW            6
+#define BM_GPMI_DEBUG2_UPDATE_WINDOW            0x40
+#define BF_GPMI_DEBUG2_UPDATE_WINDOW(v)         (((v) & 0x1) << 6)
+#define BFM_GPMI_DEBUG2_UPDATE_WINDOW(v)        BM_GPMI_DEBUG2_UPDATE_WINDOW
+#define BF_GPMI_DEBUG2_UPDATE_WINDOW_V(e)       BF_GPMI_DEBUG2_UPDATE_WINDOW(BV_GPMI_DEBUG2_UPDATE_WINDOW__##e)
+#define BFM_GPMI_DEBUG2_UPDATE_WINDOW_V(v)      BM_GPMI_DEBUG2_UPDATE_WINDOW
+#define BP_GPMI_DEBUG2_RDN_TAP                  0
+#define BM_GPMI_DEBUG2_RDN_TAP                  0x3f
+#define BF_GPMI_DEBUG2_RDN_TAP(v)               (((v) & 0x3f) << 0)
+#define BFM_GPMI_DEBUG2_RDN_TAP(v)              BM_GPMI_DEBUG2_RDN_TAP
+#define BF_GPMI_DEBUG2_RDN_TAP_V(e)             BF_GPMI_DEBUG2_RDN_TAP(BV_GPMI_DEBUG2_RDN_TAP__##e)
+#define BFM_GPMI_DEBUG2_RDN_TAP_V(v)            BM_GPMI_DEBUG2_RDN_TAP
+
+#define HW_GPMI_DEBUG3                      HW(GPMI_DEBUG3)
+#define HWA_GPMI_DEBUG3                     (0x8000c000 + 0xf0)
+#define HWT_GPMI_DEBUG3                     HWIO_32_RW
+#define HWN_GPMI_DEBUG3                     GPMI_DEBUG3
+#define HWI_GPMI_DEBUG3                     
+#define BP_GPMI_DEBUG3_APB_WORD_CNTR        16
+#define BM_GPMI_DEBUG3_APB_WORD_CNTR        0xffff0000
+#define BF_GPMI_DEBUG3_APB_WORD_CNTR(v)     (((v) & 0xffff) << 16)
+#define BFM_GPMI_DEBUG3_APB_WORD_CNTR(v)    BM_GPMI_DEBUG3_APB_WORD_CNTR
+#define BF_GPMI_DEBUG3_APB_WORD_CNTR_V(e)   BF_GPMI_DEBUG3_APB_WORD_CNTR(BV_GPMI_DEBUG3_APB_WORD_CNTR__##e)
+#define BFM_GPMI_DEBUG3_APB_WORD_CNTR_V(v)  BM_GPMI_DEBUG3_APB_WORD_CNTR
+#define BP_GPMI_DEBUG3_DEV_WORD_CNTR        0
+#define BM_GPMI_DEBUG3_DEV_WORD_CNTR        0xffff
+#define BF_GPMI_DEBUG3_DEV_WORD_CNTR(v)     (((v) & 0xffff) << 0)
+#define BFM_GPMI_DEBUG3_DEV_WORD_CNTR(v)    BM_GPMI_DEBUG3_DEV_WORD_CNTR
+#define BF_GPMI_DEBUG3_DEV_WORD_CNTR_V(e)   BF_GPMI_DEBUG3_DEV_WORD_CNTR(BV_GPMI_DEBUG3_DEV_WORD_CNTR__##e)
+#define BFM_GPMI_DEBUG3_DEV_WORD_CNTR_V(v)  BM_GPMI_DEBUG3_DEV_WORD_CNTR
+
+#endif /* __HEADERGEN_IMX233_GPMI_H__*/
diff --git a/firmware/target/arm/imx233/regs/imx233/i2c.h b/firmware/target/arm/imx233/regs/imx233/i2c.h
new file mode 100644
index 0000000000..9b2feaa58e
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/imx233/i2c.h
@@ -0,0 +1,930 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * imx233 version: 2.4.0
+ * imx233 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_IMX233_I2C_H__
+#define __HEADERGEN_IMX233_I2C_H__
+
+#define HW_I2C_CTRL0                                HW(I2C_CTRL0)
+#define HWA_I2C_CTRL0                               (0x80058000 + 0x0)
+#define HWT_I2C_CTRL0                               HWIO_32_RW
+#define HWN_I2C_CTRL0                               I2C_CTRL0
+#define HWI_I2C_CTRL0                               
+#define HW_I2C_CTRL0_SET                            HW(I2C_CTRL0_SET)
+#define HWA_I2C_CTRL0_SET                           (HWA_I2C_CTRL0 + 0x4)
+#define HWT_I2C_CTRL0_SET                           HWIO_32_WO
+#define HWN_I2C_CTRL0_SET                           I2C_CTRL0
+#define HWI_I2C_CTRL0_SET                           
+#define HW_I2C_CTRL0_CLR                            HW(I2C_CTRL0_CLR)
+#define HWA_I2C_CTRL0_CLR                           (HWA_I2C_CTRL0 + 0x8)
+#define HWT_I2C_CTRL0_CLR                           HWIO_32_WO
+#define HWN_I2C_CTRL0_CLR                           I2C_CTRL0
+#define HWI_I2C_CTRL0_CLR                           
+#define HW_I2C_CTRL0_TOG                            HW(I2C_CTRL0_TOG)
+#define HWA_I2C_CTRL0_TOG                           (HWA_I2C_CTRL0 + 0xc)
+#define HWT_I2C_CTRL0_TOG                           HWIO_32_WO
+#define HWN_I2C_CTRL0_TOG                           I2C_CTRL0
+#define HWI_I2C_CTRL0_TOG                           
+#define BP_I2C_CTRL0_SFTRST                         31
+#define BM_I2C_CTRL0_SFTRST                         0x80000000
+#define BV_I2C_CTRL0_SFTRST__RUN                    0x0
+#define BV_I2C_CTRL0_SFTRST__RESET                  0x1
+#define BF_I2C_CTRL0_SFTRST(v)                      (((v) & 0x1) << 31)
+#define BFM_I2C_CTRL0_SFTRST(v)                     BM_I2C_CTRL0_SFTRST
+#define BF_I2C_CTRL0_SFTRST_V(e)                    BF_I2C_CTRL0_SFTRST(BV_I2C_CTRL0_SFTRST__##e)
+#define BFM_I2C_CTRL0_SFTRST_V(v)                   BM_I2C_CTRL0_SFTRST
+#define BP_I2C_CTRL0_CLKGATE                        30
+#define BM_I2C_CTRL0_CLKGATE                        0x40000000
+#define BV_I2C_CTRL0_CLKGATE__RUN                   0x0
+#define BV_I2C_CTRL0_CLKGATE__NO_CLKS               0x1
+#define BF_I2C_CTRL0_CLKGATE(v)                     (((v) & 0x1) << 30)
+#define BFM_I2C_CTRL0_CLKGATE(v)                    BM_I2C_CTRL0_CLKGATE
+#define BF_I2C_CTRL0_CLKGATE_V(e)                   BF_I2C_CTRL0_CLKGATE(BV_I2C_CTRL0_CLKGATE__##e)
+#define BFM_I2C_CTRL0_CLKGATE_V(v)                  BM_I2C_CTRL0_CLKGATE
+#define BP_I2C_CTRL0_RUN                            29
+#define BM_I2C_CTRL0_RUN                            0x20000000
+#define BV_I2C_CTRL0_RUN__HALT                      0x0
+#define BV_I2C_CTRL0_RUN__RUN                       0x1
+#define BF_I2C_CTRL0_RUN(v)                         (((v) & 0x1) << 29)
+#define BFM_I2C_CTRL0_RUN(v)                        BM_I2C_CTRL0_RUN
+#define BF_I2C_CTRL0_RUN_V(e)                       BF_I2C_CTRL0_RUN(BV_I2C_CTRL0_RUN__##e)
+#define BFM_I2C_CTRL0_RUN_V(v)                      BM_I2C_CTRL0_RUN
+#define BP_I2C_CTRL0_RSVD1                          28
+#define BM_I2C_CTRL0_RSVD1                          0x10000000
+#define BF_I2C_CTRL0_RSVD1(v)                       (((v) & 0x1) << 28)
+#define BFM_I2C_CTRL0_RSVD1(v)                      BM_I2C_CTRL0_RSVD1
+#define BF_I2C_CTRL0_RSVD1_V(e)                     BF_I2C_CTRL0_RSVD1(BV_I2C_CTRL0_RSVD1__##e)
+#define BFM_I2C_CTRL0_RSVD1_V(v)                    BM_I2C_CTRL0_RSVD1
+#define BP_I2C_CTRL0_PRE_ACK                        27
+#define BM_I2C_CTRL0_PRE_ACK                        0x8000000
+#define BF_I2C_CTRL0_PRE_ACK(v)                     (((v) & 0x1) << 27)
+#define BFM_I2C_CTRL0_PRE_ACK(v)                    BM_I2C_CTRL0_PRE_ACK
+#define BF_I2C_CTRL0_PRE_ACK_V(e)                   BF_I2C_CTRL0_PRE_ACK(BV_I2C_CTRL0_PRE_ACK__##e)
+#define BFM_I2C_CTRL0_PRE_ACK_V(v)                  BM_I2C_CTRL0_PRE_ACK
+#define BP_I2C_CTRL0_ACKNOWLEDGE                    26
+#define BM_I2C_CTRL0_ACKNOWLEDGE                    0x4000000
+#define BV_I2C_CTRL0_ACKNOWLEDGE__SNAK              0x0
+#define BV_I2C_CTRL0_ACKNOWLEDGE__ACK               0x1
+#define BF_I2C_CTRL0_ACKNOWLEDGE(v)                 (((v) & 0x1) << 26)
+#define BFM_I2C_CTRL0_ACKNOWLEDGE(v)                BM_I2C_CTRL0_ACKNOWLEDGE
+#define BF_I2C_CTRL0_ACKNOWLEDGE_V(e)               BF_I2C_CTRL0_ACKNOWLEDGE(BV_I2C_CTRL0_ACKNOWLEDGE__##e)
+#define BFM_I2C_CTRL0_ACKNOWLEDGE_V(v)              BM_I2C_CTRL0_ACKNOWLEDGE
+#define BP_I2C_CTRL0_SEND_NAK_ON_LAST               25
+#define BM_I2C_CTRL0_SEND_NAK_ON_LAST               0x2000000
+#define BV_I2C_CTRL0_SEND_NAK_ON_LAST__ACK_IT       0x0
+#define BV_I2C_CTRL0_SEND_NAK_ON_LAST__NAK_IT       0x1
+#define BF_I2C_CTRL0_SEND_NAK_ON_LAST(v)            (((v) & 0x1) << 25)
+#define BFM_I2C_CTRL0_SEND_NAK_ON_LAST(v)           BM_I2C_CTRL0_SEND_NAK_ON_LAST
+#define BF_I2C_CTRL0_SEND_NAK_ON_LAST_V(e)          BF_I2C_CTRL0_SEND_NAK_ON_LAST(BV_I2C_CTRL0_SEND_NAK_ON_LAST__##e)
+#define BFM_I2C_CTRL0_SEND_NAK_ON_LAST_V(v)         BM_I2C_CTRL0_SEND_NAK_ON_LAST
+#define BP_I2C_CTRL0_PIO_MODE                       24
+#define BM_I2C_CTRL0_PIO_MODE                       0x1000000
+#define BF_I2C_CTRL0_PIO_MODE(v)                    (((v) & 0x1) << 24)
+#define BFM_I2C_CTRL0_PIO_MODE(v)                   BM_I2C_CTRL0_PIO_MODE
+#define BF_I2C_CTRL0_PIO_MODE_V(e)                  BF_I2C_CTRL0_PIO_MODE(BV_I2C_CTRL0_PIO_MODE__##e)
+#define BFM_I2C_CTRL0_PIO_MODE_V(v)                 BM_I2C_CTRL0_PIO_MODE
+#define BP_I2C_CTRL0_MULTI_MASTER                   23
+#define BM_I2C_CTRL0_MULTI_MASTER                   0x800000
+#define BV_I2C_CTRL0_MULTI_MASTER__SINGLE           0x0
+#define BV_I2C_CTRL0_MULTI_MASTER__MULTIPLE         0x1
+#define BF_I2C_CTRL0_MULTI_MASTER(v)                (((v) & 0x1) << 23)
+#define BFM_I2C_CTRL0_MULTI_MASTER(v)               BM_I2C_CTRL0_MULTI_MASTER
+#define BF_I2C_CTRL0_MULTI_MASTER_V(e)              BF_I2C_CTRL0_MULTI_MASTER(BV_I2C_CTRL0_MULTI_MASTER__##e)
+#define BFM_I2C_CTRL0_MULTI_MASTER_V(v)             BM_I2C_CTRL0_MULTI_MASTER
+#define BP_I2C_CTRL0_CLOCK_HELD                     22
+#define BM_I2C_CTRL0_CLOCK_HELD                     0x400000
+#define BV_I2C_CTRL0_CLOCK_HELD__RELEASE            0x0
+#define BV_I2C_CTRL0_CLOCK_HELD__HELD_LOW           0x1
+#define BF_I2C_CTRL0_CLOCK_HELD(v)                  (((v) & 0x1) << 22)
+#define BFM_I2C_CTRL0_CLOCK_HELD(v)                 BM_I2C_CTRL0_CLOCK_HELD
+#define BF_I2C_CTRL0_CLOCK_HELD_V(e)                BF_I2C_CTRL0_CLOCK_HELD(BV_I2C_CTRL0_CLOCK_HELD__##e)
+#define BFM_I2C_CTRL0_CLOCK_HELD_V(v)               BM_I2C_CTRL0_CLOCK_HELD
+#define BP_I2C_CTRL0_RETAIN_CLOCK                   21
+#define BM_I2C_CTRL0_RETAIN_CLOCK                   0x200000
+#define BV_I2C_CTRL0_RETAIN_CLOCK__RELEASE          0x0
+#define BV_I2C_CTRL0_RETAIN_CLOCK__HOLD_LOW         0x1
+#define BF_I2C_CTRL0_RETAIN_CLOCK(v)                (((v) & 0x1) << 21)
+#define BFM_I2C_CTRL0_RETAIN_CLOCK(v)               BM_I2C_CTRL0_RETAIN_CLOCK
+#define BF_I2C_CTRL0_RETAIN_CLOCK_V(e)              BF_I2C_CTRL0_RETAIN_CLOCK(BV_I2C_CTRL0_RETAIN_CLOCK__##e)
+#define BFM_I2C_CTRL0_RETAIN_CLOCK_V(v)             BM_I2C_CTRL0_RETAIN_CLOCK
+#define BP_I2C_CTRL0_POST_SEND_STOP                 20
+#define BM_I2C_CTRL0_POST_SEND_STOP                 0x100000
+#define BV_I2C_CTRL0_POST_SEND_STOP__NO_STOP        0x0
+#define BV_I2C_CTRL0_POST_SEND_STOP__SEND_STOP      0x1
+#define BF_I2C_CTRL0_POST_SEND_STOP(v)              (((v) & 0x1) << 20)
+#define BFM_I2C_CTRL0_POST_SEND_STOP(v)             BM_I2C_CTRL0_POST_SEND_STOP
+#define BF_I2C_CTRL0_POST_SEND_STOP_V(e)            BF_I2C_CTRL0_POST_SEND_STOP(BV_I2C_CTRL0_POST_SEND_STOP__##e)
+#define BFM_I2C_CTRL0_POST_SEND_STOP_V(v)           BM_I2C_CTRL0_POST_SEND_STOP
+#define BP_I2C_CTRL0_PRE_SEND_START                 19
+#define BM_I2C_CTRL0_PRE_SEND_START                 0x80000
+#define BV_I2C_CTRL0_PRE_SEND_START__NO_START       0x0
+#define BV_I2C_CTRL0_PRE_SEND_START__SEND_START     0x1
+#define BF_I2C_CTRL0_PRE_SEND_START(v)              (((v) & 0x1) << 19)
+#define BFM_I2C_CTRL0_PRE_SEND_START(v)             BM_I2C_CTRL0_PRE_SEND_START
+#define BF_I2C_CTRL0_PRE_SEND_START_V(e)            BF_I2C_CTRL0_PRE_SEND_START(BV_I2C_CTRL0_PRE_SEND_START__##e)
+#define BFM_I2C_CTRL0_PRE_SEND_START_V(v)           BM_I2C_CTRL0_PRE_SEND_START
+#define BP_I2C_CTRL0_SLAVE_ADDRESS_ENABLE           18
+#define BM_I2C_CTRL0_SLAVE_ADDRESS_ENABLE           0x40000
+#define BV_I2C_CTRL0_SLAVE_ADDRESS_ENABLE__DISABLED 0x0
+#define BV_I2C_CTRL0_SLAVE_ADDRESS_ENABLE__ENABLED  0x1
+#define BF_I2C_CTRL0_SLAVE_ADDRESS_ENABLE(v)        (((v) & 0x1) << 18)
+#define BFM_I2C_CTRL0_SLAVE_ADDRESS_ENABLE(v)       BM_I2C_CTRL0_SLAVE_ADDRESS_ENABLE
+#define BF_I2C_CTRL0_SLAVE_ADDRESS_ENABLE_V(e)      BF_I2C_CTRL0_SLAVE_ADDRESS_ENABLE(BV_I2C_CTRL0_SLAVE_ADDRESS_ENABLE__##e)
+#define BFM_I2C_CTRL0_SLAVE_ADDRESS_ENABLE_V(v)     BM_I2C_CTRL0_SLAVE_ADDRESS_ENABLE
+#define BP_I2C_CTRL0_MASTER_MODE                    17
+#define BM_I2C_CTRL0_MASTER_MODE                    0x20000
+#define BV_I2C_CTRL0_MASTER_MODE__SLAVE             0x0
+#define BV_I2C_CTRL0_MASTER_MODE__MASTER            0x1
+#define BF_I2C_CTRL0_MASTER_MODE(v)                 (((v) & 0x1) << 17)
+#define BFM_I2C_CTRL0_MASTER_MODE(v)                BM_I2C_CTRL0_MASTER_MODE
+#define BF_I2C_CTRL0_MASTER_MODE_V(e)               BF_I2C_CTRL0_MASTER_MODE(BV_I2C_CTRL0_MASTER_MODE__##e)
+#define BFM_I2C_CTRL0_MASTER_MODE_V(v)              BM_I2C_CTRL0_MASTER_MODE
+#define BP_I2C_CTRL0_DIRECTION                      16
+#define BM_I2C_CTRL0_DIRECTION                      0x10000
+#define BV_I2C_CTRL0_DIRECTION__RECEIVE             0x0
+#define BV_I2C_CTRL0_DIRECTION__TRANSMIT            0x1
+#define BF_I2C_CTRL0_DIRECTION(v)                   (((v) & 0x1) << 16)
+#define BFM_I2C_CTRL0_DIRECTION(v)                  BM_I2C_CTRL0_DIRECTION
+#define BF_I2C_CTRL0_DIRECTION_V(e)                 BF_I2C_CTRL0_DIRECTION(BV_I2C_CTRL0_DIRECTION__##e)
+#define BFM_I2C_CTRL0_DIRECTION_V(v)                BM_I2C_CTRL0_DIRECTION
+#define BP_I2C_CTRL0_XFER_COUNT                     0
+#define BM_I2C_CTRL0_XFER_COUNT                     0xffff
+#define BF_I2C_CTRL0_XFER_COUNT(v)                  (((v) & 0xffff) << 0)
+#define BFM_I2C_CTRL0_XFER_COUNT(v)                 BM_I2C_CTRL0_XFER_COUNT
+#define BF_I2C_CTRL0_XFER_COUNT_V(e)                BF_I2C_CTRL0_XFER_COUNT(BV_I2C_CTRL0_XFER_COUNT__##e)
+#define BFM_I2C_CTRL0_XFER_COUNT_V(v)               BM_I2C_CTRL0_XFER_COUNT
+
+#define HW_I2C_TIMING0                  HW(I2C_TIMING0)
+#define HWA_I2C_TIMING0                 (0x80058000 + 0x10)
+#define HWT_I2C_TIMING0                 HWIO_32_RW
+#define HWN_I2C_TIMING0                 I2C_TIMING0
+#define HWI_I2C_TIMING0                 
+#define HW_I2C_TIMING0_SET              HW(I2C_TIMING0_SET)
+#define HWA_I2C_TIMING0_SET             (HWA_I2C_TIMING0 + 0x4)
+#define HWT_I2C_TIMING0_SET             HWIO_32_WO
+#define HWN_I2C_TIMING0_SET             I2C_TIMING0
+#define HWI_I2C_TIMING0_SET             
+#define HW_I2C_TIMING0_CLR              HW(I2C_TIMING0_CLR)
+#define HWA_I2C_TIMING0_CLR             (HWA_I2C_TIMING0 + 0x8)
+#define HWT_I2C_TIMING0_CLR             HWIO_32_WO
+#define HWN_I2C_TIMING0_CLR             I2C_TIMING0
+#define HWI_I2C_TIMING0_CLR             
+#define HW_I2C_TIMING0_TOG              HW(I2C_TIMING0_TOG)
+#define HWA_I2C_TIMING0_TOG             (HWA_I2C_TIMING0 + 0xc)
+#define HWT_I2C_TIMING0_TOG             HWIO_32_WO
+#define HWN_I2C_TIMING0_TOG             I2C_TIMING0
+#define HWI_I2C_TIMING0_TOG             
+#define BP_I2C_TIMING0_RSVD2            26
+#define BM_I2C_TIMING0_RSVD2            0xfc000000
+#define BF_I2C_TIMING0_RSVD2(v)         (((v) & 0x3f) << 26)
+#define BFM_I2C_TIMING0_RSVD2(v)        BM_I2C_TIMING0_RSVD2
+#define BF_I2C_TIMING0_RSVD2_V(e)       BF_I2C_TIMING0_RSVD2(BV_I2C_TIMING0_RSVD2__##e)
+#define BFM_I2C_TIMING0_RSVD2_V(v)      BM_I2C_TIMING0_RSVD2
+#define BP_I2C_TIMING0_HIGH_COUNT       16
+#define BM_I2C_TIMING0_HIGH_COUNT       0x3ff0000
+#define BF_I2C_TIMING0_HIGH_COUNT(v)    (((v) & 0x3ff) << 16)
+#define BFM_I2C_TIMING0_HIGH_COUNT(v)   BM_I2C_TIMING0_HIGH_COUNT
+#define BF_I2C_TIMING0_HIGH_COUNT_V(e)  BF_I2C_TIMING0_HIGH_COUNT(BV_I2C_TIMING0_HIGH_COUNT__##e)
+#define BFM_I2C_TIMING0_HIGH_COUNT_V(v) BM_I2C_TIMING0_HIGH_COUNT
+#define BP_I2C_TIMING0_RSVD1            10
+#define BM_I2C_TIMING0_RSVD1            0xfc00
+#define BF_I2C_TIMING0_RSVD1(v)         (((v) & 0x3f) << 10)
+#define BFM_I2C_TIMING0_RSVD1(v)        BM_I2C_TIMING0_RSVD1
+#define BF_I2C_TIMING0_RSVD1_V(e)       BF_I2C_TIMING0_RSVD1(BV_I2C_TIMING0_RSVD1__##e)
+#define BFM_I2C_TIMING0_RSVD1_V(v)      BM_I2C_TIMING0_RSVD1
+#define BP_I2C_TIMING0_RCV_COUNT        0
+#define BM_I2C_TIMING0_RCV_COUNT        0x3ff
+#define BF_I2C_TIMING0_RCV_COUNT(v)     (((v) & 0x3ff) << 0)
+#define BFM_I2C_TIMING0_RCV_COUNT(v)    BM_I2C_TIMING0_RCV_COUNT
+#define BF_I2C_TIMING0_RCV_COUNT_V(e)   BF_I2C_TIMING0_RCV_COUNT(BV_I2C_TIMING0_RCV_COUNT__##e)
+#define BFM_I2C_TIMING0_RCV_COUNT_V(v)  BM_I2C_TIMING0_RCV_COUNT
+
+#define HW_I2C_TIMING1                  HW(I2C_TIMING1)
+#define HWA_I2C_TIMING1                 (0x80058000 + 0x20)
+#define HWT_I2C_TIMING1                 HWIO_32_RW
+#define HWN_I2C_TIMING1                 I2C_TIMING1
+#define HWI_I2C_TIMING1                 
+#define HW_I2C_TIMING1_SET              HW(I2C_TIMING1_SET)
+#define HWA_I2C_TIMING1_SET             (HWA_I2C_TIMING1 + 0x4)
+#define HWT_I2C_TIMING1_SET             HWIO_32_WO
+#define HWN_I2C_TIMING1_SET             I2C_TIMING1
+#define HWI_I2C_TIMING1_SET             
+#define HW_I2C_TIMING1_CLR              HW(I2C_TIMING1_CLR)
+#define HWA_I2C_TIMING1_CLR             (HWA_I2C_TIMING1 + 0x8)
+#define HWT_I2C_TIMING1_CLR             HWIO_32_WO
+#define HWN_I2C_TIMING1_CLR             I2C_TIMING1
+#define HWI_I2C_TIMING1_CLR             
+#define HW_I2C_TIMING1_TOG              HW(I2C_TIMING1_TOG)
+#define HWA_I2C_TIMING1_TOG             (HWA_I2C_TIMING1 + 0xc)
+#define HWT_I2C_TIMING1_TOG             HWIO_32_WO
+#define HWN_I2C_TIMING1_TOG             I2C_TIMING1
+#define HWI_I2C_TIMING1_TOG             
+#define BP_I2C_TIMING1_RSVD2            26
+#define BM_I2C_TIMING1_RSVD2            0xfc000000
+#define BF_I2C_TIMING1_RSVD2(v)         (((v) & 0x3f) << 26)
+#define BFM_I2C_TIMING1_RSVD2(v)        BM_I2C_TIMING1_RSVD2
+#define BF_I2C_TIMING1_RSVD2_V(e)       BF_I2C_TIMING1_RSVD2(BV_I2C_TIMING1_RSVD2__##e)
+#define BFM_I2C_TIMING1_RSVD2_V(v)      BM_I2C_TIMING1_RSVD2
+#define BP_I2C_TIMING1_LOW_COUNT        16
+#define BM_I2C_TIMING1_LOW_COUNT        0x3ff0000
+#define BF_I2C_TIMING1_LOW_COUNT(v)     (((v) & 0x3ff) << 16)
+#define BFM_I2C_TIMING1_LOW_COUNT(v)    BM_I2C_TIMING1_LOW_COUNT
+#define BF_I2C_TIMING1_LOW_COUNT_V(e)   BF_I2C_TIMING1_LOW_COUNT(BV_I2C_TIMING1_LOW_COUNT__##e)
+#define BFM_I2C_TIMING1_LOW_COUNT_V(v)  BM_I2C_TIMING1_LOW_COUNT
+#define BP_I2C_TIMING1_RSVD1            10
+#define BM_I2C_TIMING1_RSVD1            0xfc00
+#define BF_I2C_TIMING1_RSVD1(v)         (((v) & 0x3f) << 10)
+#define BFM_I2C_TIMING1_RSVD1(v)        BM_I2C_TIMING1_RSVD1
+#define BF_I2C_TIMING1_RSVD1_V(e)       BF_I2C_TIMING1_RSVD1(BV_I2C_TIMING1_RSVD1__##e)
+#define BFM_I2C_TIMING1_RSVD1_V(v)      BM_I2C_TIMING1_RSVD1
+#define BP_I2C_TIMING1_XMIT_COUNT       0
+#define BM_I2C_TIMING1_XMIT_COUNT       0x3ff
+#define BF_I2C_TIMING1_XMIT_COUNT(v)    (((v) & 0x3ff) << 0)
+#define BFM_I2C_TIMING1_XMIT_COUNT(v)   BM_I2C_TIMING1_XMIT_COUNT
+#define BF_I2C_TIMING1_XMIT_COUNT_V(e)  BF_I2C_TIMING1_XMIT_COUNT(BV_I2C_TIMING1_XMIT_COUNT__##e)
+#define BFM_I2C_TIMING1_XMIT_COUNT_V(v) BM_I2C_TIMING1_XMIT_COUNT
+
+#define HW_I2C_TIMING2                      HW(I2C_TIMING2)
+#define HWA_I2C_TIMING2                     (0x80058000 + 0x30)
+#define HWT_I2C_TIMING2                     HWIO_32_RW
+#define HWN_I2C_TIMING2                     I2C_TIMING2
+#define HWI_I2C_TIMING2                     
+#define HW_I2C_TIMING2_SET                  HW(I2C_TIMING2_SET)
+#define HWA_I2C_TIMING2_SET                 (HWA_I2C_TIMING2 + 0x4)
+#define HWT_I2C_TIMING2_SET                 HWIO_32_WO
+#define HWN_I2C_TIMING2_SET                 I2C_TIMING2
+#define HWI_I2C_TIMING2_SET                 
+#define HW_I2C_TIMING2_CLR                  HW(I2C_TIMING2_CLR)
+#define HWA_I2C_TIMING2_CLR                 (HWA_I2C_TIMING2 + 0x8)
+#define HWT_I2C_TIMING2_CLR                 HWIO_32_WO
+#define HWN_I2C_TIMING2_CLR                 I2C_TIMING2
+#define HWI_I2C_TIMING2_CLR                 
+#define HW_I2C_TIMING2_TOG                  HW(I2C_TIMING2_TOG)
+#define HWA_I2C_TIMING2_TOG                 (HWA_I2C_TIMING2 + 0xc)
+#define HWT_I2C_TIMING2_TOG                 HWIO_32_WO
+#define HWN_I2C_TIMING2_TOG                 I2C_TIMING2
+#define HWI_I2C_TIMING2_TOG                 
+#define BP_I2C_TIMING2_RSVD2                26
+#define BM_I2C_TIMING2_RSVD2                0xfc000000
+#define BF_I2C_TIMING2_RSVD2(v)             (((v) & 0x3f) << 26)
+#define BFM_I2C_TIMING2_RSVD2(v)            BM_I2C_TIMING2_RSVD2
+#define BF_I2C_TIMING2_RSVD2_V(e)           BF_I2C_TIMING2_RSVD2(BV_I2C_TIMING2_RSVD2__##e)
+#define BFM_I2C_TIMING2_RSVD2_V(v)          BM_I2C_TIMING2_RSVD2
+#define BP_I2C_TIMING2_BUS_FREE             16
+#define BM_I2C_TIMING2_BUS_FREE             0x3ff0000
+#define BF_I2C_TIMING2_BUS_FREE(v)          (((v) & 0x3ff) << 16)
+#define BFM_I2C_TIMING2_BUS_FREE(v)         BM_I2C_TIMING2_BUS_FREE
+#define BF_I2C_TIMING2_BUS_FREE_V(e)        BF_I2C_TIMING2_BUS_FREE(BV_I2C_TIMING2_BUS_FREE__##e)
+#define BFM_I2C_TIMING2_BUS_FREE_V(v)       BM_I2C_TIMING2_BUS_FREE
+#define BP_I2C_TIMING2_RSVD1                10
+#define BM_I2C_TIMING2_RSVD1                0xfc00
+#define BF_I2C_TIMING2_RSVD1(v)             (((v) & 0x3f) << 10)
+#define BFM_I2C_TIMING2_RSVD1(v)            BM_I2C_TIMING2_RSVD1
+#define BF_I2C_TIMING2_RSVD1_V(e)           BF_I2C_TIMING2_RSVD1(BV_I2C_TIMING2_RSVD1__##e)
+#define BFM_I2C_TIMING2_RSVD1_V(v)          BM_I2C_TIMING2_RSVD1
+#define BP_I2C_TIMING2_LEADIN_COUNT         0
+#define BM_I2C_TIMING2_LEADIN_COUNT         0x3ff
+#define BF_I2C_TIMING2_LEADIN_COUNT(v)      (((v) & 0x3ff) << 0)
+#define BFM_I2C_TIMING2_LEADIN_COUNT(v)     BM_I2C_TIMING2_LEADIN_COUNT
+#define BF_I2C_TIMING2_LEADIN_COUNT_V(e)    BF_I2C_TIMING2_LEADIN_COUNT(BV_I2C_TIMING2_LEADIN_COUNT__##e)
+#define BFM_I2C_TIMING2_LEADIN_COUNT_V(v)   BM_I2C_TIMING2_LEADIN_COUNT
+
+#define HW_I2C_CTRL1                                        HW(I2C_CTRL1)
+#define HWA_I2C_CTRL1                                       (0x80058000 + 0x40)
+#define HWT_I2C_CTRL1                                       HWIO_32_RW
+#define HWN_I2C_CTRL1                                       I2C_CTRL1
+#define HWI_I2C_CTRL1                                       
+#define HW_I2C_CTRL1_SET                                    HW(I2C_CTRL1_SET)
+#define HWA_I2C_CTRL1_SET                                   (HWA_I2C_CTRL1 + 0x4)
+#define HWT_I2C_CTRL1_SET                                   HWIO_32_WO
+#define HWN_I2C_CTRL1_SET                                   I2C_CTRL1
+#define HWI_I2C_CTRL1_SET                                   
+#define HW_I2C_CTRL1_CLR                                    HW(I2C_CTRL1_CLR)
+#define HWA_I2C_CTRL1_CLR                                   (HWA_I2C_CTRL1 + 0x8)
+#define HWT_I2C_CTRL1_CLR                                   HWIO_32_WO
+#define HWN_I2C_CTRL1_CLR                                   I2C_CTRL1
+#define HWI_I2C_CTRL1_CLR                                   
+#define HW_I2C_CTRL1_TOG                                    HW(I2C_CTRL1_TOG)
+#define HWA_I2C_CTRL1_TOG                                   (HWA_I2C_CTRL1 + 0xc)
+#define HWT_I2C_CTRL1_TOG                                   HWIO_32_WO
+#define HWN_I2C_CTRL1_TOG                                   I2C_CTRL1
+#define HWI_I2C_CTRL1_TOG                                   
+#define BP_I2C_CTRL1_RSVD1                                  29
+#define BM_I2C_CTRL1_RSVD1                                  0xe0000000
+#define BF_I2C_CTRL1_RSVD1(v)                               (((v) & 0x7) << 29)
+#define BFM_I2C_CTRL1_RSVD1(v)                              BM_I2C_CTRL1_RSVD1
+#define BF_I2C_CTRL1_RSVD1_V(e)                             BF_I2C_CTRL1_RSVD1(BV_I2C_CTRL1_RSVD1__##e)
+#define BFM_I2C_CTRL1_RSVD1_V(v)                            BM_I2C_CTRL1_RSVD1
+#define BP_I2C_CTRL1_CLR_GOT_A_NAK                          28
+#define BM_I2C_CTRL1_CLR_GOT_A_NAK                          0x10000000
+#define BV_I2C_CTRL1_CLR_GOT_A_NAK__DO_NOTHING              0x0
+#define BV_I2C_CTRL1_CLR_GOT_A_NAK__CLEAR                   0x1
+#define BF_I2C_CTRL1_CLR_GOT_A_NAK(v)                       (((v) & 0x1) << 28)
+#define BFM_I2C_CTRL1_CLR_GOT_A_NAK(v)                      BM_I2C_CTRL1_CLR_GOT_A_NAK
+#define BF_I2C_CTRL1_CLR_GOT_A_NAK_V(e)                     BF_I2C_CTRL1_CLR_GOT_A_NAK(BV_I2C_CTRL1_CLR_GOT_A_NAK__##e)
+#define BFM_I2C_CTRL1_CLR_GOT_A_NAK_V(v)                    BM_I2C_CTRL1_CLR_GOT_A_NAK
+#define BP_I2C_CTRL1_ACK_MODE                               27
+#define BM_I2C_CTRL1_ACK_MODE                               0x8000000
+#define BV_I2C_CTRL1_ACK_MODE__ACK_AFTER_HOLD_LOW           0x0
+#define BV_I2C_CTRL1_ACK_MODE__ACK_BEFORE_HOLD_LOW          0x1
+#define BF_I2C_CTRL1_ACK_MODE(v)                            (((v) & 0x1) << 27)
+#define BFM_I2C_CTRL1_ACK_MODE(v)                           BM_I2C_CTRL1_ACK_MODE
+#define BF_I2C_CTRL1_ACK_MODE_V(e)                          BF_I2C_CTRL1_ACK_MODE(BV_I2C_CTRL1_ACK_MODE__##e)
+#define BFM_I2C_CTRL1_ACK_MODE_V(v)                         BM_I2C_CTRL1_ACK_MODE
+#define BP_I2C_CTRL1_FORCE_DATA_IDLE                        26
+#define BM_I2C_CTRL1_FORCE_DATA_IDLE                        0x4000000
+#define BF_I2C_CTRL1_FORCE_DATA_IDLE(v)                     (((v) & 0x1) << 26)
+#define BFM_I2C_CTRL1_FORCE_DATA_IDLE(v)                    BM_I2C_CTRL1_FORCE_DATA_IDLE
+#define BF_I2C_CTRL1_FORCE_DATA_IDLE_V(e)                   BF_I2C_CTRL1_FORCE_DATA_IDLE(BV_I2C_CTRL1_FORCE_DATA_IDLE__##e)
+#define BFM_I2C_CTRL1_FORCE_DATA_IDLE_V(v)                  BM_I2C_CTRL1_FORCE_DATA_IDLE
+#define BP_I2C_CTRL1_FORCE_CLK_IDLE                         25
+#define BM_I2C_CTRL1_FORCE_CLK_IDLE                         0x2000000
+#define BF_I2C_CTRL1_FORCE_CLK_IDLE(v)                      (((v) & 0x1) << 25)
+#define BFM_I2C_CTRL1_FORCE_CLK_IDLE(v)                     BM_I2C_CTRL1_FORCE_CLK_IDLE
+#define BF_I2C_CTRL1_FORCE_CLK_IDLE_V(e)                    BF_I2C_CTRL1_FORCE_CLK_IDLE(BV_I2C_CTRL1_FORCE_CLK_IDLE__##e)
+#define BFM_I2C_CTRL1_FORCE_CLK_IDLE_V(v)                   BM_I2C_CTRL1_FORCE_CLK_IDLE
+#define BP_I2C_CTRL1_BCAST_SLAVE_EN                         24
+#define BM_I2C_CTRL1_BCAST_SLAVE_EN                         0x1000000
+#define BV_I2C_CTRL1_BCAST_SLAVE_EN__NO_BCAST               0x0
+#define BV_I2C_CTRL1_BCAST_SLAVE_EN__WATCH_BCAST            0x1
+#define BF_I2C_CTRL1_BCAST_SLAVE_EN(v)                      (((v) & 0x1) << 24)
+#define BFM_I2C_CTRL1_BCAST_SLAVE_EN(v)                     BM_I2C_CTRL1_BCAST_SLAVE_EN
+#define BF_I2C_CTRL1_BCAST_SLAVE_EN_V(e)                    BF_I2C_CTRL1_BCAST_SLAVE_EN(BV_I2C_CTRL1_BCAST_SLAVE_EN__##e)
+#define BFM_I2C_CTRL1_BCAST_SLAVE_EN_V(v)                   BM_I2C_CTRL1_BCAST_SLAVE_EN
+#define BP_I2C_CTRL1_SLAVE_ADDRESS_BYTE                     16
+#define BM_I2C_CTRL1_SLAVE_ADDRESS_BYTE                     0xff0000
+#define BF_I2C_CTRL1_SLAVE_ADDRESS_BYTE(v)                  (((v) & 0xff) << 16)
+#define BFM_I2C_CTRL1_SLAVE_ADDRESS_BYTE(v)                 BM_I2C_CTRL1_SLAVE_ADDRESS_BYTE
+#define BF_I2C_CTRL1_SLAVE_ADDRESS_BYTE_V(e)                BF_I2C_CTRL1_SLAVE_ADDRESS_BYTE(BV_I2C_CTRL1_SLAVE_ADDRESS_BYTE__##e)
+#define BFM_I2C_CTRL1_SLAVE_ADDRESS_BYTE_V(v)               BM_I2C_CTRL1_SLAVE_ADDRESS_BYTE
+#define BP_I2C_CTRL1_BUS_FREE_IRQ_EN                        15
+#define BM_I2C_CTRL1_BUS_FREE_IRQ_EN                        0x8000
+#define BV_I2C_CTRL1_BUS_FREE_IRQ_EN__DISABLED              0x0
+#define BV_I2C_CTRL1_BUS_FREE_IRQ_EN__ENABLED               0x1
+#define BF_I2C_CTRL1_BUS_FREE_IRQ_EN(v)                     (((v) & 0x1) << 15)
+#define BFM_I2C_CTRL1_BUS_FREE_IRQ_EN(v)                    BM_I2C_CTRL1_BUS_FREE_IRQ_EN
+#define BF_I2C_CTRL1_BUS_FREE_IRQ_EN_V(e)                   BF_I2C_CTRL1_BUS_FREE_IRQ_EN(BV_I2C_CTRL1_BUS_FREE_IRQ_EN__##e)
+#define BFM_I2C_CTRL1_BUS_FREE_IRQ_EN_V(v)                  BM_I2C_CTRL1_BUS_FREE_IRQ_EN
+#define BP_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN               14
+#define BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN               0x4000
+#define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN__DISABLED     0x0
+#define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN__ENABLED      0x1
+#define BF_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN(v)            (((v) & 0x1) << 14)
+#define BFM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN(v)           BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN
+#define BF_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN_V(e)          BF_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN(BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN__##e)
+#define BFM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN_V(v)         BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN
+#define BP_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN                    13
+#define BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN                    0x2000
+#define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN__DISABLED          0x0
+#define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN__ENABLED           0x1
+#define BF_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN(v)                 (((v) & 0x1) << 13)
+#define BFM_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN(v)                BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN
+#define BF_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN_V(e)               BF_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN(BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN__##e)
+#define BFM_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN_V(v)              BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN
+#define BP_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN              12
+#define BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN              0x1000
+#define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN__DISABLED    0x0
+#define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN__ENABLED     0x1
+#define BF_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN(v)           (((v) & 0x1) << 12)
+#define BFM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN(v)          BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN
+#define BF_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN_V(e)         BF_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN(BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN__##e)
+#define BFM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN_V(v)        BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN
+#define BP_I2C_CTRL1_EARLY_TERM_IRQ_EN                      11
+#define BM_I2C_CTRL1_EARLY_TERM_IRQ_EN                      0x800
+#define BV_I2C_CTRL1_EARLY_TERM_IRQ_EN__DISABLED            0x0
+#define BV_I2C_CTRL1_EARLY_TERM_IRQ_EN__ENABLED             0x1
+#define BF_I2C_CTRL1_EARLY_TERM_IRQ_EN(v)                   (((v) & 0x1) << 11)
+#define BFM_I2C_CTRL1_EARLY_TERM_IRQ_EN(v)                  BM_I2C_CTRL1_EARLY_TERM_IRQ_EN
+#define BF_I2C_CTRL1_EARLY_TERM_IRQ_EN_V(e)                 BF_I2C_CTRL1_EARLY_TERM_IRQ_EN(BV_I2C_CTRL1_EARLY_TERM_IRQ_EN__##e)
+#define BFM_I2C_CTRL1_EARLY_TERM_IRQ_EN_V(v)                BM_I2C_CTRL1_EARLY_TERM_IRQ_EN
+#define BP_I2C_CTRL1_MASTER_LOSS_IRQ_EN                     10
+#define BM_I2C_CTRL1_MASTER_LOSS_IRQ_EN                     0x400
+#define BV_I2C_CTRL1_MASTER_LOSS_IRQ_EN__DISABLED           0x0
+#define BV_I2C_CTRL1_MASTER_LOSS_IRQ_EN__ENABLED            0x1
+#define BF_I2C_CTRL1_MASTER_LOSS_IRQ_EN(v)                  (((v) & 0x1) << 10)
+#define BFM_I2C_CTRL1_MASTER_LOSS_IRQ_EN(v)                 BM_I2C_CTRL1_MASTER_LOSS_IRQ_EN
+#define BF_I2C_CTRL1_MASTER_LOSS_IRQ_EN_V(e)                BF_I2C_CTRL1_MASTER_LOSS_IRQ_EN(BV_I2C_CTRL1_MASTER_LOSS_IRQ_EN__##e)
+#define BFM_I2C_CTRL1_MASTER_LOSS_IRQ_EN_V(v)               BM_I2C_CTRL1_MASTER_LOSS_IRQ_EN
+#define BP_I2C_CTRL1_SLAVE_STOP_IRQ_EN                      9
+#define BM_I2C_CTRL1_SLAVE_STOP_IRQ_EN                      0x200
+#define BV_I2C_CTRL1_SLAVE_STOP_IRQ_EN__DISABLED            0x0
+#define BV_I2C_CTRL1_SLAVE_STOP_IRQ_EN__ENABLED             0x1
+#define BF_I2C_CTRL1_SLAVE_STOP_IRQ_EN(v)                   (((v) & 0x1) << 9)
+#define BFM_I2C_CTRL1_SLAVE_STOP_IRQ_EN(v)                  BM_I2C_CTRL1_SLAVE_STOP_IRQ_EN
+#define BF_I2C_CTRL1_SLAVE_STOP_IRQ_EN_V(e)                 BF_I2C_CTRL1_SLAVE_STOP_IRQ_EN(BV_I2C_CTRL1_SLAVE_STOP_IRQ_EN__##e)
+#define BFM_I2C_CTRL1_SLAVE_STOP_IRQ_EN_V(v)                BM_I2C_CTRL1_SLAVE_STOP_IRQ_EN
+#define BP_I2C_CTRL1_SLAVE_IRQ_EN                           8
+#define BM_I2C_CTRL1_SLAVE_IRQ_EN                           0x100
+#define BV_I2C_CTRL1_SLAVE_IRQ_EN__DISABLED                 0x0
+#define BV_I2C_CTRL1_SLAVE_IRQ_EN__ENABLED                  0x1
+#define BF_I2C_CTRL1_SLAVE_IRQ_EN(v)                        (((v) & 0x1) << 8)
+#define BFM_I2C_CTRL1_SLAVE_IRQ_EN(v)                       BM_I2C_CTRL1_SLAVE_IRQ_EN
+#define BF_I2C_CTRL1_SLAVE_IRQ_EN_V(e)                      BF_I2C_CTRL1_SLAVE_IRQ_EN(BV_I2C_CTRL1_SLAVE_IRQ_EN__##e)
+#define BFM_I2C_CTRL1_SLAVE_IRQ_EN_V(v)                     BM_I2C_CTRL1_SLAVE_IRQ_EN
+#define BP_I2C_CTRL1_BUS_FREE_IRQ                           7
+#define BM_I2C_CTRL1_BUS_FREE_IRQ                           0x80
+#define BV_I2C_CTRL1_BUS_FREE_IRQ__NO_REQUEST               0x0
+#define BV_I2C_CTRL1_BUS_FREE_IRQ__REQUEST                  0x1
+#define BF_I2C_CTRL1_BUS_FREE_IRQ(v)                        (((v) & 0x1) << 7)
+#define BFM_I2C_CTRL1_BUS_FREE_IRQ(v)                       BM_I2C_CTRL1_BUS_FREE_IRQ
+#define BF_I2C_CTRL1_BUS_FREE_IRQ_V(e)                      BF_I2C_CTRL1_BUS_FREE_IRQ(BV_I2C_CTRL1_BUS_FREE_IRQ__##e)
+#define BFM_I2C_CTRL1_BUS_FREE_IRQ_V(v)                     BM_I2C_CTRL1_BUS_FREE_IRQ
+#define BP_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ                  6
+#define BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ                  0x40
+#define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ__NO_REQUEST      0x0
+#define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ__REQUEST         0x1
+#define BF_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ(v)               (((v) & 0x1) << 6)
+#define BFM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ(v)              BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ
+#define BF_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_V(e)             BF_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ(BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ__##e)
+#define BFM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_V(v)            BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ
+#define BP_I2C_CTRL1_NO_SLAVE_ACK_IRQ                       5
+#define BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ                       0x20
+#define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ__NO_REQUEST           0x0
+#define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ__REQUEST              0x1
+#define BF_I2C_CTRL1_NO_SLAVE_ACK_IRQ(v)                    (((v) & 0x1) << 5)
+#define BFM_I2C_CTRL1_NO_SLAVE_ACK_IRQ(v)                   BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ
+#define BF_I2C_CTRL1_NO_SLAVE_ACK_IRQ_V(e)                  BF_I2C_CTRL1_NO_SLAVE_ACK_IRQ(BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ__##e)
+#define BFM_I2C_CTRL1_NO_SLAVE_ACK_IRQ_V(v)                 BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ
+#define BP_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ                 4
+#define BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ                 0x10
+#define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ__NO_REQUEST     0x0
+#define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ__REQUEST        0x1
+#define BF_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ(v)              (((v) & 0x1) << 4)
+#define BFM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ(v)             BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ
+#define BF_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_V(e)            BF_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ(BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ__##e)
+#define BFM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_V(v)           BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ
+#define BP_I2C_CTRL1_EARLY_TERM_IRQ                         3
+#define BM_I2C_CTRL1_EARLY_TERM_IRQ                         0x8
+#define BV_I2C_CTRL1_EARLY_TERM_IRQ__NO_REQUEST             0x0
+#define BV_I2C_CTRL1_EARLY_TERM_IRQ__REQUEST                0x1
+#define BF_I2C_CTRL1_EARLY_TERM_IRQ(v)                      (((v) & 0x1) << 3)
+#define BFM_I2C_CTRL1_EARLY_TERM_IRQ(v)                     BM_I2C_CTRL1_EARLY_TERM_IRQ
+#define BF_I2C_CTRL1_EARLY_TERM_IRQ_V(e)                    BF_I2C_CTRL1_EARLY_TERM_IRQ(BV_I2C_CTRL1_EARLY_TERM_IRQ__##e)
+#define BFM_I2C_CTRL1_EARLY_TERM_IRQ_V(v)                   BM_I2C_CTRL1_EARLY_TERM_IRQ
+#define BP_I2C_CTRL1_MASTER_LOSS_IRQ                        2
+#define BM_I2C_CTRL1_MASTER_LOSS_IRQ                        0x4
+#define BV_I2C_CTRL1_MASTER_LOSS_IRQ__NO_REQUEST            0x0
+#define BV_I2C_CTRL1_MASTER_LOSS_IRQ__REQUEST               0x1
+#define BF_I2C_CTRL1_MASTER_LOSS_IRQ(v)                     (((v) & 0x1) << 2)
+#define BFM_I2C_CTRL1_MASTER_LOSS_IRQ(v)                    BM_I2C_CTRL1_MASTER_LOSS_IRQ
+#define BF_I2C_CTRL1_MASTER_LOSS_IRQ_V(e)                   BF_I2C_CTRL1_MASTER_LOSS_IRQ(BV_I2C_CTRL1_MASTER_LOSS_IRQ__##e)
+#define BFM_I2C_CTRL1_MASTER_LOSS_IRQ_V(v)                  BM_I2C_CTRL1_MASTER_LOSS_IRQ
+#define BP_I2C_CTRL1_SLAVE_STOP_IRQ                         1
+#define BM_I2C_CTRL1_SLAVE_STOP_IRQ                         0x2
+#define BV_I2C_CTRL1_SLAVE_STOP_IRQ__NO_REQUEST             0x0
+#define BV_I2C_CTRL1_SLAVE_STOP_IRQ__REQUEST                0x1
+#define BF_I2C_CTRL1_SLAVE_STOP_IRQ(v)                      (((v) & 0x1) << 1)
+#define BFM_I2C_CTRL1_SLAVE_STOP_IRQ(v)                     BM_I2C_CTRL1_SLAVE_STOP_IRQ
+#define BF_I2C_CTRL1_SLAVE_STOP_IRQ_V(e)                    BF_I2C_CTRL1_SLAVE_STOP_IRQ(BV_I2C_CTRL1_SLAVE_STOP_IRQ__##e)
+#define BFM_I2C_CTRL1_SLAVE_STOP_IRQ_V(v)                   BM_I2C_CTRL1_SLAVE_STOP_IRQ
+#define BP_I2C_CTRL1_SLAVE_IRQ                              0
+#define BM_I2C_CTRL1_SLAVE_IRQ                              0x1
+#define BV_I2C_CTRL1_SLAVE_IRQ__NO_REQUEST                  0x0
+#define BV_I2C_CTRL1_SLAVE_IRQ__REQUEST                     0x1
+#define BF_I2C_CTRL1_SLAVE_IRQ(v)                           (((v) & 0x1) << 0)
+#define BFM_I2C_CTRL1_SLAVE_IRQ(v)                          BM_I2C_CTRL1_SLAVE_IRQ
+#define BF_I2C_CTRL1_SLAVE_IRQ_V(e)                         BF_I2C_CTRL1_SLAVE_IRQ(BV_I2C_CTRL1_SLAVE_IRQ__##e)
+#define BFM_I2C_CTRL1_SLAVE_IRQ_V(v)                        BM_I2C_CTRL1_SLAVE_IRQ
+
+#define HW_I2C_STAT                                             HW(I2C_STAT)
+#define HWA_I2C_STAT                                            (0x80058000 + 0x50)
+#define HWT_I2C_STAT                                            HWIO_32_RW
+#define HWN_I2C_STAT                                            I2C_STAT
+#define HWI_I2C_STAT                                            
+#define BP_I2C_STAT_MASTER_PRESENT                              31
+#define BM_I2C_STAT_MASTER_PRESENT                              0x80000000
+#define BV_I2C_STAT_MASTER_PRESENT__UNAVAILABLE                 0x0
+#define BV_I2C_STAT_MASTER_PRESENT__AVAILABLE                   0x1
+#define BF_I2C_STAT_MASTER_PRESENT(v)                           (((v) & 0x1) << 31)
+#define BFM_I2C_STAT_MASTER_PRESENT(v)                          BM_I2C_STAT_MASTER_PRESENT
+#define BF_I2C_STAT_MASTER_PRESENT_V(e)                         BF_I2C_STAT_MASTER_PRESENT(BV_I2C_STAT_MASTER_PRESENT__##e)
+#define BFM_I2C_STAT_MASTER_PRESENT_V(v)                        BM_I2C_STAT_MASTER_PRESENT
+#define BP_I2C_STAT_SLAVE_PRESENT                               30
+#define BM_I2C_STAT_SLAVE_PRESENT                               0x40000000
+#define BV_I2C_STAT_SLAVE_PRESENT__UNAVAILABLE                  0x0
+#define BV_I2C_STAT_SLAVE_PRESENT__AVAILABLE                    0x1
+#define BF_I2C_STAT_SLAVE_PRESENT(v)                            (((v) & 0x1) << 30)
+#define BFM_I2C_STAT_SLAVE_PRESENT(v)                           BM_I2C_STAT_SLAVE_PRESENT
+#define BF_I2C_STAT_SLAVE_PRESENT_V(e)                          BF_I2C_STAT_SLAVE_PRESENT(BV_I2C_STAT_SLAVE_PRESENT__##e)
+#define BFM_I2C_STAT_SLAVE_PRESENT_V(v)                         BM_I2C_STAT_SLAVE_PRESENT
+#define BP_I2C_STAT_ANY_ENABLED_IRQ                             29
+#define BM_I2C_STAT_ANY_ENABLED_IRQ                             0x20000000
+#define BV_I2C_STAT_ANY_ENABLED_IRQ__NO_REQUESTS                0x0
+#define BV_I2C_STAT_ANY_ENABLED_IRQ__AT_LEAST_ONE_REQUEST       0x1
+#define BF_I2C_STAT_ANY_ENABLED_IRQ(v)                          (((v) & 0x1) << 29)
+#define BFM_I2C_STAT_ANY_ENABLED_IRQ(v)                         BM_I2C_STAT_ANY_ENABLED_IRQ
+#define BF_I2C_STAT_ANY_ENABLED_IRQ_V(e)                        BF_I2C_STAT_ANY_ENABLED_IRQ(BV_I2C_STAT_ANY_ENABLED_IRQ__##e)
+#define BFM_I2C_STAT_ANY_ENABLED_IRQ_V(v)                       BM_I2C_STAT_ANY_ENABLED_IRQ
+#define BP_I2C_STAT_GOT_A_NAK                                   28
+#define BM_I2C_STAT_GOT_A_NAK                                   0x10000000
+#define BV_I2C_STAT_GOT_A_NAK__NO_NAK                           0x0
+#define BV_I2C_STAT_GOT_A_NAK__DETECTED_NAK                     0x1
+#define BF_I2C_STAT_GOT_A_NAK(v)                                (((v) & 0x1) << 28)
+#define BFM_I2C_STAT_GOT_A_NAK(v)                               BM_I2C_STAT_GOT_A_NAK
+#define BF_I2C_STAT_GOT_A_NAK_V(e)                              BF_I2C_STAT_GOT_A_NAK(BV_I2C_STAT_GOT_A_NAK__##e)
+#define BFM_I2C_STAT_GOT_A_NAK_V(v)                             BM_I2C_STAT_GOT_A_NAK
+#define BP_I2C_STAT_RSVD1                                       24
+#define BM_I2C_STAT_RSVD1                                       0xf000000
+#define BF_I2C_STAT_RSVD1(v)                                    (((v) & 0xf) << 24)
+#define BFM_I2C_STAT_RSVD1(v)                                   BM_I2C_STAT_RSVD1
+#define BF_I2C_STAT_RSVD1_V(e)                                  BF_I2C_STAT_RSVD1(BV_I2C_STAT_RSVD1__##e)
+#define BFM_I2C_STAT_RSVD1_V(v)                                 BM_I2C_STAT_RSVD1
+#define BP_I2C_STAT_RCVD_SLAVE_ADDR                             16
+#define BM_I2C_STAT_RCVD_SLAVE_ADDR                             0xff0000
+#define BF_I2C_STAT_RCVD_SLAVE_ADDR(v)                          (((v) & 0xff) << 16)
+#define BFM_I2C_STAT_RCVD_SLAVE_ADDR(v)                         BM_I2C_STAT_RCVD_SLAVE_ADDR
+#define BF_I2C_STAT_RCVD_SLAVE_ADDR_V(e)                        BF_I2C_STAT_RCVD_SLAVE_ADDR(BV_I2C_STAT_RCVD_SLAVE_ADDR__##e)
+#define BFM_I2C_STAT_RCVD_SLAVE_ADDR_V(v)                       BM_I2C_STAT_RCVD_SLAVE_ADDR
+#define BP_I2C_STAT_SLAVE_ADDR_EQ_ZERO                          15
+#define BM_I2C_STAT_SLAVE_ADDR_EQ_ZERO                          0x8000
+#define BV_I2C_STAT_SLAVE_ADDR_EQ_ZERO__ZERO_NOT_MATCHED        0x0
+#define BV_I2C_STAT_SLAVE_ADDR_EQ_ZERO__WAS_ZERO                0x1
+#define BF_I2C_STAT_SLAVE_ADDR_EQ_ZERO(v)                       (((v) & 0x1) << 15)
+#define BFM_I2C_STAT_SLAVE_ADDR_EQ_ZERO(v)                      BM_I2C_STAT_SLAVE_ADDR_EQ_ZERO
+#define BF_I2C_STAT_SLAVE_ADDR_EQ_ZERO_V(e)                     BF_I2C_STAT_SLAVE_ADDR_EQ_ZERO(BV_I2C_STAT_SLAVE_ADDR_EQ_ZERO__##e)
+#define BFM_I2C_STAT_SLAVE_ADDR_EQ_ZERO_V(v)                    BM_I2C_STAT_SLAVE_ADDR_EQ_ZERO
+#define BP_I2C_STAT_SLAVE_FOUND                                 14
+#define BM_I2C_STAT_SLAVE_FOUND                                 0x4000
+#define BV_I2C_STAT_SLAVE_FOUND__IDLE                           0x0
+#define BV_I2C_STAT_SLAVE_FOUND__WAITING                        0x1
+#define BF_I2C_STAT_SLAVE_FOUND(v)                              (((v) & 0x1) << 14)
+#define BFM_I2C_STAT_SLAVE_FOUND(v)                             BM_I2C_STAT_SLAVE_FOUND
+#define BF_I2C_STAT_SLAVE_FOUND_V(e)                            BF_I2C_STAT_SLAVE_FOUND(BV_I2C_STAT_SLAVE_FOUND__##e)
+#define BFM_I2C_STAT_SLAVE_FOUND_V(v)                           BM_I2C_STAT_SLAVE_FOUND
+#define BP_I2C_STAT_SLAVE_SEARCHING                             13
+#define BM_I2C_STAT_SLAVE_SEARCHING                             0x2000
+#define BV_I2C_STAT_SLAVE_SEARCHING__IDLE                       0x0
+#define BV_I2C_STAT_SLAVE_SEARCHING__ACTIVE                     0x1
+#define BF_I2C_STAT_SLAVE_SEARCHING(v)                          (((v) & 0x1) << 13)
+#define BFM_I2C_STAT_SLAVE_SEARCHING(v)                         BM_I2C_STAT_SLAVE_SEARCHING
+#define BF_I2C_STAT_SLAVE_SEARCHING_V(e)                        BF_I2C_STAT_SLAVE_SEARCHING(BV_I2C_STAT_SLAVE_SEARCHING__##e)
+#define BFM_I2C_STAT_SLAVE_SEARCHING_V(v)                       BM_I2C_STAT_SLAVE_SEARCHING
+#define BP_I2C_STAT_DATA_ENGINE_DMA_WAIT                        12
+#define BM_I2C_STAT_DATA_ENGINE_DMA_WAIT                        0x1000
+#define BV_I2C_STAT_DATA_ENGINE_DMA_WAIT__CONTINUE              0x0
+#define BV_I2C_STAT_DATA_ENGINE_DMA_WAIT__WAITING               0x1
+#define BF_I2C_STAT_DATA_ENGINE_DMA_WAIT(v)                     (((v) & 0x1) << 12)
+#define BFM_I2C_STAT_DATA_ENGINE_DMA_WAIT(v)                    BM_I2C_STAT_DATA_ENGINE_DMA_WAIT
+#define BF_I2C_STAT_DATA_ENGINE_DMA_WAIT_V(e)                   BF_I2C_STAT_DATA_ENGINE_DMA_WAIT(BV_I2C_STAT_DATA_ENGINE_DMA_WAIT__##e)
+#define BFM_I2C_STAT_DATA_ENGINE_DMA_WAIT_V(v)                  BM_I2C_STAT_DATA_ENGINE_DMA_WAIT
+#define BP_I2C_STAT_BUS_BUSY                                    11
+#define BM_I2C_STAT_BUS_BUSY                                    0x800
+#define BV_I2C_STAT_BUS_BUSY__IDLE                              0x0
+#define BV_I2C_STAT_BUS_BUSY__BUSY                              0x1
+#define BF_I2C_STAT_BUS_BUSY(v)                                 (((v) & 0x1) << 11)
+#define BFM_I2C_STAT_BUS_BUSY(v)                                BM_I2C_STAT_BUS_BUSY
+#define BF_I2C_STAT_BUS_BUSY_V(e)                               BF_I2C_STAT_BUS_BUSY(BV_I2C_STAT_BUS_BUSY__##e)
+#define BFM_I2C_STAT_BUS_BUSY_V(v)                              BM_I2C_STAT_BUS_BUSY
+#define BP_I2C_STAT_CLK_GEN_BUSY                                10
+#define BM_I2C_STAT_CLK_GEN_BUSY                                0x400
+#define BV_I2C_STAT_CLK_GEN_BUSY__IDLE                          0x0
+#define BV_I2C_STAT_CLK_GEN_BUSY__BUSY                          0x1
+#define BF_I2C_STAT_CLK_GEN_BUSY(v)                             (((v) & 0x1) << 10)
+#define BFM_I2C_STAT_CLK_GEN_BUSY(v)                            BM_I2C_STAT_CLK_GEN_BUSY
+#define BF_I2C_STAT_CLK_GEN_BUSY_V(e)                           BF_I2C_STAT_CLK_GEN_BUSY(BV_I2C_STAT_CLK_GEN_BUSY__##e)
+#define BFM_I2C_STAT_CLK_GEN_BUSY_V(v)                          BM_I2C_STAT_CLK_GEN_BUSY
+#define BP_I2C_STAT_DATA_ENGINE_BUSY                            9
+#define BM_I2C_STAT_DATA_ENGINE_BUSY                            0x200
+#define BV_I2C_STAT_DATA_ENGINE_BUSY__IDLE                      0x0
+#define BV_I2C_STAT_DATA_ENGINE_BUSY__BUSY                      0x1
+#define BF_I2C_STAT_DATA_ENGINE_BUSY(v)                         (((v) & 0x1) << 9)
+#define BFM_I2C_STAT_DATA_ENGINE_BUSY(v)                        BM_I2C_STAT_DATA_ENGINE_BUSY
+#define BF_I2C_STAT_DATA_ENGINE_BUSY_V(e)                       BF_I2C_STAT_DATA_ENGINE_BUSY(BV_I2C_STAT_DATA_ENGINE_BUSY__##e)
+#define BFM_I2C_STAT_DATA_ENGINE_BUSY_V(v)                      BM_I2C_STAT_DATA_ENGINE_BUSY
+#define BP_I2C_STAT_SLAVE_BUSY                                  8
+#define BM_I2C_STAT_SLAVE_BUSY                                  0x100
+#define BV_I2C_STAT_SLAVE_BUSY__IDLE                            0x0
+#define BV_I2C_STAT_SLAVE_BUSY__BUSY                            0x1
+#define BF_I2C_STAT_SLAVE_BUSY(v)                               (((v) & 0x1) << 8)
+#define BFM_I2C_STAT_SLAVE_BUSY(v)                              BM_I2C_STAT_SLAVE_BUSY
+#define BF_I2C_STAT_SLAVE_BUSY_V(e)                             BF_I2C_STAT_SLAVE_BUSY(BV_I2C_STAT_SLAVE_BUSY__##e)
+#define BFM_I2C_STAT_SLAVE_BUSY_V(v)                            BM_I2C_STAT_SLAVE_BUSY
+#define BP_I2C_STAT_BUS_FREE_IRQ_SUMMARY                        7
+#define BM_I2C_STAT_BUS_FREE_IRQ_SUMMARY                        0x80
+#define BV_I2C_STAT_BUS_FREE_IRQ_SUMMARY__NO_REQUEST            0x0
+#define BV_I2C_STAT_BUS_FREE_IRQ_SUMMARY__REQUEST               0x1
+#define BF_I2C_STAT_BUS_FREE_IRQ_SUMMARY(v)                     (((v) & 0x1) << 7)
+#define BFM_I2C_STAT_BUS_FREE_IRQ_SUMMARY(v)                    BM_I2C_STAT_BUS_FREE_IRQ_SUMMARY
+#define BF_I2C_STAT_BUS_FREE_IRQ_SUMMARY_V(e)                   BF_I2C_STAT_BUS_FREE_IRQ_SUMMARY(BV_I2C_STAT_BUS_FREE_IRQ_SUMMARY__##e)
+#define BFM_I2C_STAT_BUS_FREE_IRQ_SUMMARY_V(v)                  BM_I2C_STAT_BUS_FREE_IRQ_SUMMARY
+#define BP_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY               6
+#define BM_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY               0x40
+#define BV_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY__NO_REQUEST   0x0
+#define BV_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY__REQUEST      0x1
+#define BF_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY(v)            (((v) & 0x1) << 6)
+#define BFM_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY(v)           BM_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY
+#define BF_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY_V(e)          BF_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY(BV_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY__##e)
+#define BFM_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY_V(v)         BM_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY
+#define BP_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY                    5
+#define BM_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY                    0x20
+#define BV_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY__NO_REQUEST        0x0
+#define BV_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY__REQUEST           0x1
+#define BF_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY(v)                 (((v) & 0x1) << 5)
+#define BFM_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY(v)                BM_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY
+#define BF_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY_V(e)               BF_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY(BV_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY__##e)
+#define BFM_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY_V(v)              BM_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY
+#define BP_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY              4
+#define BM_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY              0x10
+#define BV_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY__NO_REQUEST  0x0
+#define BV_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY__REQUEST     0x1
+#define BF_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY(v)           (((v) & 0x1) << 4)
+#define BFM_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY(v)          BM_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY
+#define BF_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY_V(e)         BF_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY(BV_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY__##e)
+#define BFM_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY_V(v)        BM_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY
+#define BP_I2C_STAT_EARLY_TERM_IRQ_SUMMARY                      3
+#define BM_I2C_STAT_EARLY_TERM_IRQ_SUMMARY                      0x8
+#define BV_I2C_STAT_EARLY_TERM_IRQ_SUMMARY__NO_REQUEST          0x0
+#define BV_I2C_STAT_EARLY_TERM_IRQ_SUMMARY__REQUEST             0x1
+#define BF_I2C_STAT_EARLY_TERM_IRQ_SUMMARY(v)                   (((v) & 0x1) << 3)
+#define BFM_I2C_STAT_EARLY_TERM_IRQ_SUMMARY(v)                  BM_I2C_STAT_EARLY_TERM_IRQ_SUMMARY
+#define BF_I2C_STAT_EARLY_TERM_IRQ_SUMMARY_V(e)                 BF_I2C_STAT_EARLY_TERM_IRQ_SUMMARY(BV_I2C_STAT_EARLY_TERM_IRQ_SUMMARY__##e)
+#define BFM_I2C_STAT_EARLY_TERM_IRQ_SUMMARY_V(v)                BM_I2C_STAT_EARLY_TERM_IRQ_SUMMARY
+#define BP_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY                     2
+#define BM_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY                     0x4
+#define BV_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY__NO_REQUEST         0x0
+#define BV_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY__REQUEST            0x1
+#define BF_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY(v)                  (((v) & 0x1) << 2)
+#define BFM_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY(v)                 BM_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY
+#define BF_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY_V(e)                BF_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY(BV_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY__##e)
+#define BFM_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY_V(v)               BM_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY
+#define BP_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY                      1
+#define BM_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY                      0x2
+#define BV_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY__NO_REQUEST          0x0
+#define BV_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY__REQUEST             0x1
+#define BF_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY(v)                   (((v) & 0x1) << 1)
+#define BFM_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY(v)                  BM_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY
+#define BF_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY_V(e)                 BF_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY(BV_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY__##e)
+#define BFM_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY_V(v)                BM_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY
+#define BP_I2C_STAT_SLAVE_IRQ_SUMMARY                           0
+#define BM_I2C_STAT_SLAVE_IRQ_SUMMARY                           0x1
+#define BV_I2C_STAT_SLAVE_IRQ_SUMMARY__NO_REQUEST               0x0
+#define BV_I2C_STAT_SLAVE_IRQ_SUMMARY__REQUEST                  0x1
+#define BF_I2C_STAT_SLAVE_IRQ_SUMMARY(v)                        (((v) & 0x1) << 0)
+#define BFM_I2C_STAT_SLAVE_IRQ_SUMMARY(v)                       BM_I2C_STAT_SLAVE_IRQ_SUMMARY
+#define BF_I2C_STAT_SLAVE_IRQ_SUMMARY_V(e)                      BF_I2C_STAT_SLAVE_IRQ_SUMMARY(BV_I2C_STAT_SLAVE_IRQ_SUMMARY__##e)
+#define BFM_I2C_STAT_SLAVE_IRQ_SUMMARY_V(v)                     BM_I2C_STAT_SLAVE_IRQ_SUMMARY
+
+#define HW_I2C_DATA             HW(I2C_DATA)
+#define HWA_I2C_DATA            (0x80058000 + 0x60)
+#define HWT_I2C_DATA            HWIO_32_RW
+#define HWN_I2C_DATA            I2C_DATA
+#define HWI_I2C_DATA            
+#define BP_I2C_DATA_DATA        0
+#define BM_I2C_DATA_DATA        0xffffffff
+#define BF_I2C_DATA_DATA(v)     (((v) & 0xffffffff) << 0)
+#define BFM_I2C_DATA_DATA(v)    BM_I2C_DATA_DATA
+#define BF_I2C_DATA_DATA_V(e)   BF_I2C_DATA_DATA(BV_I2C_DATA_DATA__##e)
+#define BFM_I2C_DATA_DATA_V(v)  BM_I2C_DATA_DATA
+
+#define HW_I2C_DEBUG0                       HW(I2C_DEBUG0)
+#define HWA_I2C_DEBUG0                      (0x80058000 + 0x70)
+#define HWT_I2C_DEBUG0                      HWIO_32_RW
+#define HWN_I2C_DEBUG0                      I2C_DEBUG0
+#define HWI_I2C_DEBUG0                      
+#define HW_I2C_DEBUG0_SET                   HW(I2C_DEBUG0_SET)
+#define HWA_I2C_DEBUG0_SET                  (HWA_I2C_DEBUG0 + 0x4)
+#define HWT_I2C_DEBUG0_SET                  HWIO_32_WO
+#define HWN_I2C_DEBUG0_SET                  I2C_DEBUG0
+#define HWI_I2C_DEBUG0_SET                  
+#define HW_I2C_DEBUG0_CLR                   HW(I2C_DEBUG0_CLR)
+#define HWA_I2C_DEBUG0_CLR                  (HWA_I2C_DEBUG0 + 0x8)
+#define HWT_I2C_DEBUG0_CLR                  HWIO_32_WO
+#define HWN_I2C_DEBUG0_CLR                  I2C_DEBUG0
+#define HWI_I2C_DEBUG0_CLR                  
+#define HW_I2C_DEBUG0_TOG                   HW(I2C_DEBUG0_TOG)
+#define HWA_I2C_DEBUG0_TOG                  (HWA_I2C_DEBUG0 + 0xc)
+#define HWT_I2C_DEBUG0_TOG                  HWIO_32_WO
+#define HWN_I2C_DEBUG0_TOG                  I2C_DEBUG0
+#define HWI_I2C_DEBUG0_TOG                  
+#define BP_I2C_DEBUG0_DMAREQ                31
+#define BM_I2C_DEBUG0_DMAREQ                0x80000000
+#define BF_I2C_DEBUG0_DMAREQ(v)             (((v) & 0x1) << 31)
+#define BFM_I2C_DEBUG0_DMAREQ(v)            BM_I2C_DEBUG0_DMAREQ
+#define BF_I2C_DEBUG0_DMAREQ_V(e)           BF_I2C_DEBUG0_DMAREQ(BV_I2C_DEBUG0_DMAREQ__##e)
+#define BFM_I2C_DEBUG0_DMAREQ_V(v)          BM_I2C_DEBUG0_DMAREQ
+#define BP_I2C_DEBUG0_DMAENDCMD             30
+#define BM_I2C_DEBUG0_DMAENDCMD             0x40000000
+#define BF_I2C_DEBUG0_DMAENDCMD(v)          (((v) & 0x1) << 30)
+#define BFM_I2C_DEBUG0_DMAENDCMD(v)         BM_I2C_DEBUG0_DMAENDCMD
+#define BF_I2C_DEBUG0_DMAENDCMD_V(e)        BF_I2C_DEBUG0_DMAENDCMD(BV_I2C_DEBUG0_DMAENDCMD__##e)
+#define BFM_I2C_DEBUG0_DMAENDCMD_V(v)       BM_I2C_DEBUG0_DMAENDCMD
+#define BP_I2C_DEBUG0_DMAKICK               29
+#define BM_I2C_DEBUG0_DMAKICK               0x20000000
+#define BF_I2C_DEBUG0_DMAKICK(v)            (((v) & 0x1) << 29)
+#define BFM_I2C_DEBUG0_DMAKICK(v)           BM_I2C_DEBUG0_DMAKICK
+#define BF_I2C_DEBUG0_DMAKICK_V(e)          BF_I2C_DEBUG0_DMAKICK(BV_I2C_DEBUG0_DMAKICK__##e)
+#define BFM_I2C_DEBUG0_DMAKICK_V(v)         BM_I2C_DEBUG0_DMAKICK
+#define BP_I2C_DEBUG0_DMATERMINATE          28
+#define BM_I2C_DEBUG0_DMATERMINATE          0x10000000
+#define BF_I2C_DEBUG0_DMATERMINATE(v)       (((v) & 0x1) << 28)
+#define BFM_I2C_DEBUG0_DMATERMINATE(v)      BM_I2C_DEBUG0_DMATERMINATE
+#define BF_I2C_DEBUG0_DMATERMINATE_V(e)     BF_I2C_DEBUG0_DMATERMINATE(BV_I2C_DEBUG0_DMATERMINATE__##e)
+#define BFM_I2C_DEBUG0_DMATERMINATE_V(v)    BM_I2C_DEBUG0_DMATERMINATE
+#define BP_I2C_DEBUG0_TBD                   26
+#define BM_I2C_DEBUG0_TBD                   0xc000000
+#define BF_I2C_DEBUG0_TBD(v)                (((v) & 0x3) << 26)
+#define BFM_I2C_DEBUG0_TBD(v)               BM_I2C_DEBUG0_TBD
+#define BF_I2C_DEBUG0_TBD_V(e)              BF_I2C_DEBUG0_TBD(BV_I2C_DEBUG0_TBD__##e)
+#define BFM_I2C_DEBUG0_TBD_V(v)             BM_I2C_DEBUG0_TBD
+#define BP_I2C_DEBUG0_DMA_STATE             16
+#define BM_I2C_DEBUG0_DMA_STATE             0x3ff0000
+#define BF_I2C_DEBUG0_DMA_STATE(v)          (((v) & 0x3ff) << 16)
+#define BFM_I2C_DEBUG0_DMA_STATE(v)         BM_I2C_DEBUG0_DMA_STATE
+#define BF_I2C_DEBUG0_DMA_STATE_V(e)        BF_I2C_DEBUG0_DMA_STATE(BV_I2C_DEBUG0_DMA_STATE__##e)
+#define BFM_I2C_DEBUG0_DMA_STATE_V(v)       BM_I2C_DEBUG0_DMA_STATE
+#define BP_I2C_DEBUG0_START_TOGGLE          15
+#define BM_I2C_DEBUG0_START_TOGGLE          0x8000
+#define BF_I2C_DEBUG0_START_TOGGLE(v)       (((v) & 0x1) << 15)
+#define BFM_I2C_DEBUG0_START_TOGGLE(v)      BM_I2C_DEBUG0_START_TOGGLE
+#define BF_I2C_DEBUG0_START_TOGGLE_V(e)     BF_I2C_DEBUG0_START_TOGGLE(BV_I2C_DEBUG0_START_TOGGLE__##e)
+#define BFM_I2C_DEBUG0_START_TOGGLE_V(v)    BM_I2C_DEBUG0_START_TOGGLE
+#define BP_I2C_DEBUG0_STOP_TOGGLE           14
+#define BM_I2C_DEBUG0_STOP_TOGGLE           0x4000
+#define BF_I2C_DEBUG0_STOP_TOGGLE(v)        (((v) & 0x1) << 14)
+#define BFM_I2C_DEBUG0_STOP_TOGGLE(v)       BM_I2C_DEBUG0_STOP_TOGGLE
+#define BF_I2C_DEBUG0_STOP_TOGGLE_V(e)      BF_I2C_DEBUG0_STOP_TOGGLE(BV_I2C_DEBUG0_STOP_TOGGLE__##e)
+#define BFM_I2C_DEBUG0_STOP_TOGGLE_V(v)     BM_I2C_DEBUG0_STOP_TOGGLE
+#define BP_I2C_DEBUG0_GRAB_TOGGLE           13
+#define BM_I2C_DEBUG0_GRAB_TOGGLE           0x2000
+#define BF_I2C_DEBUG0_GRAB_TOGGLE(v)        (((v) & 0x1) << 13)
+#define BFM_I2C_DEBUG0_GRAB_TOGGLE(v)       BM_I2C_DEBUG0_GRAB_TOGGLE
+#define BF_I2C_DEBUG0_GRAB_TOGGLE_V(e)      BF_I2C_DEBUG0_GRAB_TOGGLE(BV_I2C_DEBUG0_GRAB_TOGGLE__##e)
+#define BFM_I2C_DEBUG0_GRAB_TOGGLE_V(v)     BM_I2C_DEBUG0_GRAB_TOGGLE
+#define BP_I2C_DEBUG0_CHANGE_TOGGLE         12
+#define BM_I2C_DEBUG0_CHANGE_TOGGLE         0x1000
+#define BF_I2C_DEBUG0_CHANGE_TOGGLE(v)      (((v) & 0x1) << 12)
+#define BFM_I2C_DEBUG0_CHANGE_TOGGLE(v)     BM_I2C_DEBUG0_CHANGE_TOGGLE
+#define BF_I2C_DEBUG0_CHANGE_TOGGLE_V(e)    BF_I2C_DEBUG0_CHANGE_TOGGLE(BV_I2C_DEBUG0_CHANGE_TOGGLE__##e)
+#define BFM_I2C_DEBUG0_CHANGE_TOGGLE_V(v)   BM_I2C_DEBUG0_CHANGE_TOGGLE
+#define BP_I2C_DEBUG0_TESTMODE              11
+#define BM_I2C_DEBUG0_TESTMODE              0x800
+#define BF_I2C_DEBUG0_TESTMODE(v)           (((v) & 0x1) << 11)
+#define BFM_I2C_DEBUG0_TESTMODE(v)          BM_I2C_DEBUG0_TESTMODE
+#define BF_I2C_DEBUG0_TESTMODE_V(e)         BF_I2C_DEBUG0_TESTMODE(BV_I2C_DEBUG0_TESTMODE__##e)
+#define BFM_I2C_DEBUG0_TESTMODE_V(v)        BM_I2C_DEBUG0_TESTMODE
+#define BP_I2C_DEBUG0_SLAVE_HOLD_CLK        10
+#define BM_I2C_DEBUG0_SLAVE_HOLD_CLK        0x400
+#define BF_I2C_DEBUG0_SLAVE_HOLD_CLK(v)     (((v) & 0x1) << 10)
+#define BFM_I2C_DEBUG0_SLAVE_HOLD_CLK(v)    BM_I2C_DEBUG0_SLAVE_HOLD_CLK
+#define BF_I2C_DEBUG0_SLAVE_HOLD_CLK_V(e)   BF_I2C_DEBUG0_SLAVE_HOLD_CLK(BV_I2C_DEBUG0_SLAVE_HOLD_CLK__##e)
+#define BFM_I2C_DEBUG0_SLAVE_HOLD_CLK_V(v)  BM_I2C_DEBUG0_SLAVE_HOLD_CLK
+#define BP_I2C_DEBUG0_SLAVE_STATE           0
+#define BM_I2C_DEBUG0_SLAVE_STATE           0x3ff
+#define BF_I2C_DEBUG0_SLAVE_STATE(v)        (((v) & 0x3ff) << 0)
+#define BFM_I2C_DEBUG0_SLAVE_STATE(v)       BM_I2C_DEBUG0_SLAVE_STATE
+#define BF_I2C_DEBUG0_SLAVE_STATE_V(e)      BF_I2C_DEBUG0_SLAVE_STATE(BV_I2C_DEBUG0_SLAVE_STATE__##e)
+#define BFM_I2C_DEBUG0_SLAVE_STATE_V(v)     BM_I2C_DEBUG0_SLAVE_STATE
+
+#define HW_I2C_DEBUG1                           HW(I2C_DEBUG1)
+#define HWA_I2C_DEBUG1                          (0x80058000 + 0x80)
+#define HWT_I2C_DEBUG1                          HWIO_32_RW
+#define HWN_I2C_DEBUG1                          I2C_DEBUG1
+#define HWI_I2C_DEBUG1                          
+#define HW_I2C_DEBUG1_SET                       HW(I2C_DEBUG1_SET)
+#define HWA_I2C_DEBUG1_SET                      (HWA_I2C_DEBUG1 + 0x4)
+#define HWT_I2C_DEBUG1_SET                      HWIO_32_WO
+#define HWN_I2C_DEBUG1_SET                      I2C_DEBUG1
+#define HWI_I2C_DEBUG1_SET                      
+#define HW_I2C_DEBUG1_CLR                       HW(I2C_DEBUG1_CLR)
+#define HWA_I2C_DEBUG1_CLR                      (HWA_I2C_DEBUG1 + 0x8)
+#define HWT_I2C_DEBUG1_CLR                      HWIO_32_WO
+#define HWN_I2C_DEBUG1_CLR                      I2C_DEBUG1
+#define HWI_I2C_DEBUG1_CLR                      
+#define HW_I2C_DEBUG1_TOG                       HW(I2C_DEBUG1_TOG)
+#define HWA_I2C_DEBUG1_TOG                      (HWA_I2C_DEBUG1 + 0xc)
+#define HWT_I2C_DEBUG1_TOG                      HWIO_32_WO
+#define HWN_I2C_DEBUG1_TOG                      I2C_DEBUG1
+#define HWI_I2C_DEBUG1_TOG                      
+#define BP_I2C_DEBUG1_I2C_CLK_IN                31
+#define BM_I2C_DEBUG1_I2C_CLK_IN                0x80000000
+#define BF_I2C_DEBUG1_I2C_CLK_IN(v)             (((v) & 0x1) << 31)
+#define BFM_I2C_DEBUG1_I2C_CLK_IN(v)            BM_I2C_DEBUG1_I2C_CLK_IN
+#define BF_I2C_DEBUG1_I2C_CLK_IN_V(e)           BF_I2C_DEBUG1_I2C_CLK_IN(BV_I2C_DEBUG1_I2C_CLK_IN__##e)
+#define BFM_I2C_DEBUG1_I2C_CLK_IN_V(v)          BM_I2C_DEBUG1_I2C_CLK_IN
+#define BP_I2C_DEBUG1_I2C_DATA_IN               30
+#define BM_I2C_DEBUG1_I2C_DATA_IN               0x40000000
+#define BF_I2C_DEBUG1_I2C_DATA_IN(v)            (((v) & 0x1) << 30)
+#define BFM_I2C_DEBUG1_I2C_DATA_IN(v)           BM_I2C_DEBUG1_I2C_DATA_IN
+#define BF_I2C_DEBUG1_I2C_DATA_IN_V(e)          BF_I2C_DEBUG1_I2C_DATA_IN(BV_I2C_DEBUG1_I2C_DATA_IN__##e)
+#define BFM_I2C_DEBUG1_I2C_DATA_IN_V(v)         BM_I2C_DEBUG1_I2C_DATA_IN
+#define BP_I2C_DEBUG1_RSVD4                     28
+#define BM_I2C_DEBUG1_RSVD4                     0x30000000
+#define BF_I2C_DEBUG1_RSVD4(v)                  (((v) & 0x3) << 28)
+#define BFM_I2C_DEBUG1_RSVD4(v)                 BM_I2C_DEBUG1_RSVD4
+#define BF_I2C_DEBUG1_RSVD4_V(e)                BF_I2C_DEBUG1_RSVD4(BV_I2C_DEBUG1_RSVD4__##e)
+#define BFM_I2C_DEBUG1_RSVD4_V(v)               BM_I2C_DEBUG1_RSVD4
+#define BP_I2C_DEBUG1_DMA_BYTE_ENABLES          24
+#define BM_I2C_DEBUG1_DMA_BYTE_ENABLES          0xf000000
+#define BF_I2C_DEBUG1_DMA_BYTE_ENABLES(v)       (((v) & 0xf) << 24)
+#define BFM_I2C_DEBUG1_DMA_BYTE_ENABLES(v)      BM_I2C_DEBUG1_DMA_BYTE_ENABLES
+#define BF_I2C_DEBUG1_DMA_BYTE_ENABLES_V(e)     BF_I2C_DEBUG1_DMA_BYTE_ENABLES(BV_I2C_DEBUG1_DMA_BYTE_ENABLES__##e)
+#define BFM_I2C_DEBUG1_DMA_BYTE_ENABLES_V(v)    BM_I2C_DEBUG1_DMA_BYTE_ENABLES
+#define BP_I2C_DEBUG1_CLK_GEN_STATE             16
+#define BM_I2C_DEBUG1_CLK_GEN_STATE             0xff0000
+#define BF_I2C_DEBUG1_CLK_GEN_STATE(v)          (((v) & 0xff) << 16)
+#define BFM_I2C_DEBUG1_CLK_GEN_STATE(v)         BM_I2C_DEBUG1_CLK_GEN_STATE
+#define BF_I2C_DEBUG1_CLK_GEN_STATE_V(e)        BF_I2C_DEBUG1_CLK_GEN_STATE(BV_I2C_DEBUG1_CLK_GEN_STATE__##e)
+#define BFM_I2C_DEBUG1_CLK_GEN_STATE_V(v)       BM_I2C_DEBUG1_CLK_GEN_STATE
+#define BP_I2C_DEBUG1_RSVD2                     11
+#define BM_I2C_DEBUG1_RSVD2                     0xf800
+#define BF_I2C_DEBUG1_RSVD2(v)                  (((v) & 0x1f) << 11)
+#define BFM_I2C_DEBUG1_RSVD2(v)                 BM_I2C_DEBUG1_RSVD2
+#define BF_I2C_DEBUG1_RSVD2_V(e)                BF_I2C_DEBUG1_RSVD2(BV_I2C_DEBUG1_RSVD2__##e)
+#define BFM_I2C_DEBUG1_RSVD2_V(v)               BM_I2C_DEBUG1_RSVD2
+#define BP_I2C_DEBUG1_LST_MODE                  9
+#define BM_I2C_DEBUG1_LST_MODE                  0x600
+#define BV_I2C_DEBUG1_LST_MODE__BCAST           0x0
+#define BV_I2C_DEBUG1_LST_MODE__MY_WRITE        0x1
+#define BV_I2C_DEBUG1_LST_MODE__MY_READ         0x2
+#define BV_I2C_DEBUG1_LST_MODE__NOT_ME          0x3
+#define BF_I2C_DEBUG1_LST_MODE(v)               (((v) & 0x3) << 9)
+#define BFM_I2C_DEBUG1_LST_MODE(v)              BM_I2C_DEBUG1_LST_MODE
+#define BF_I2C_DEBUG1_LST_MODE_V(e)             BF_I2C_DEBUG1_LST_MODE(BV_I2C_DEBUG1_LST_MODE__##e)
+#define BFM_I2C_DEBUG1_LST_MODE_V(v)            BM_I2C_DEBUG1_LST_MODE
+#define BP_I2C_DEBUG1_LOCAL_SLAVE_TEST          8
+#define BM_I2C_DEBUG1_LOCAL_SLAVE_TEST          0x100
+#define BF_I2C_DEBUG1_LOCAL_SLAVE_TEST(v)       (((v) & 0x1) << 8)
+#define BFM_I2C_DEBUG1_LOCAL_SLAVE_TEST(v)      BM_I2C_DEBUG1_LOCAL_SLAVE_TEST
+#define BF_I2C_DEBUG1_LOCAL_SLAVE_TEST_V(e)     BF_I2C_DEBUG1_LOCAL_SLAVE_TEST(BV_I2C_DEBUG1_LOCAL_SLAVE_TEST__##e)
+#define BFM_I2C_DEBUG1_LOCAL_SLAVE_TEST_V(v)    BM_I2C_DEBUG1_LOCAL_SLAVE_TEST
+#define BP_I2C_DEBUG1_RSVD1                     5
+#define BM_I2C_DEBUG1_RSVD1                     0xe0
+#define BF_I2C_DEBUG1_RSVD1(v)                  (((v) & 0x7) << 5)
+#define BFM_I2C_DEBUG1_RSVD1(v)                 BM_I2C_DEBUG1_RSVD1
+#define BF_I2C_DEBUG1_RSVD1_V(e)                BF_I2C_DEBUG1_RSVD1(BV_I2C_DEBUG1_RSVD1__##e)
+#define BFM_I2C_DEBUG1_RSVD1_V(v)               BM_I2C_DEBUG1_RSVD1
+#define BP_I2C_DEBUG1_FORCE_CLK_ON              4
+#define BM_I2C_DEBUG1_FORCE_CLK_ON              0x10
+#define BF_I2C_DEBUG1_FORCE_CLK_ON(v)           (((v) & 0x1) << 4)
+#define BFM_I2C_DEBUG1_FORCE_CLK_ON(v)          BM_I2C_DEBUG1_FORCE_CLK_ON
+#define BF_I2C_DEBUG1_FORCE_CLK_ON_V(e)         BF_I2C_DEBUG1_FORCE_CLK_ON(BV_I2C_DEBUG1_FORCE_CLK_ON__##e)
+#define BFM_I2C_DEBUG1_FORCE_CLK_ON_V(v)        BM_I2C_DEBUG1_FORCE_CLK_ON
+#define BP_I2C_DEBUG1_FORCE_ARB_LOSS            3
+#define BM_I2C_DEBUG1_FORCE_ARB_LOSS            0x8
+#define BF_I2C_DEBUG1_FORCE_ARB_LOSS(v)         (((v) & 0x1) << 3)
+#define BFM_I2C_DEBUG1_FORCE_ARB_LOSS(v)        BM_I2C_DEBUG1_FORCE_ARB_LOSS
+#define BF_I2C_DEBUG1_FORCE_ARB_LOSS_V(e)       BF_I2C_DEBUG1_FORCE_ARB_LOSS(BV_I2C_DEBUG1_FORCE_ARB_LOSS__##e)
+#define BFM_I2C_DEBUG1_FORCE_ARB_LOSS_V(v)      BM_I2C_DEBUG1_FORCE_ARB_LOSS
+#define BP_I2C_DEBUG1_FORCE_RCV_ACK             2
+#define BM_I2C_DEBUG1_FORCE_RCV_ACK             0x4
+#define BF_I2C_DEBUG1_FORCE_RCV_ACK(v)          (((v) & 0x1) << 2)
+#define BFM_I2C_DEBUG1_FORCE_RCV_ACK(v)         BM_I2C_DEBUG1_FORCE_RCV_ACK
+#define BF_I2C_DEBUG1_FORCE_RCV_ACK_V(e)        BF_I2C_DEBUG1_FORCE_RCV_ACK(BV_I2C_DEBUG1_FORCE_RCV_ACK__##e)
+#define BFM_I2C_DEBUG1_FORCE_RCV_ACK_V(v)       BM_I2C_DEBUG1_FORCE_RCV_ACK
+#define BP_I2C_DEBUG1_FORCE_I2C_DATA_OE         1
+#define BM_I2C_DEBUG1_FORCE_I2C_DATA_OE         0x2
+#define BF_I2C_DEBUG1_FORCE_I2C_DATA_OE(v)      (((v) & 0x1) << 1)
+#define BFM_I2C_DEBUG1_FORCE_I2C_DATA_OE(v)     BM_I2C_DEBUG1_FORCE_I2C_DATA_OE
+#define BF_I2C_DEBUG1_FORCE_I2C_DATA_OE_V(e)    BF_I2C_DEBUG1_FORCE_I2C_DATA_OE(BV_I2C_DEBUG1_FORCE_I2C_DATA_OE__##e)
+#define BFM_I2C_DEBUG1_FORCE_I2C_DATA_OE_V(v)   BM_I2C_DEBUG1_FORCE_I2C_DATA_OE
+#define BP_I2C_DEBUG1_FORCE_I2C_CLK_OE          0
+#define BM_I2C_DEBUG1_FORCE_I2C_CLK_OE          0x1
+#define BF_I2C_DEBUG1_FORCE_I2C_CLK_OE(v)       (((v) & 0x1) << 0)
+#define BFM_I2C_DEBUG1_FORCE_I2C_CLK_OE(v)      BM_I2C_DEBUG1_FORCE_I2C_CLK_OE
+#define BF_I2C_DEBUG1_FORCE_I2C_CLK_OE_V(e)     BF_I2C_DEBUG1_FORCE_I2C_CLK_OE(BV_I2C_DEBUG1_FORCE_I2C_CLK_OE__##e)
+#define BFM_I2C_DEBUG1_FORCE_I2C_CLK_OE_V(v)    BM_I2C_DEBUG1_FORCE_I2C_CLK_OE
+
+#define HW_I2C_VERSION              HW(I2C_VERSION)
+#define HWA_I2C_VERSION             (0x80058000 + 0x90)
+#define HWT_I2C_VERSION             HWIO_32_RW
+#define HWN_I2C_VERSION             I2C_VERSION
+#define HWI_I2C_VERSION             
+#define BP_I2C_VERSION_MAJOR        24
+#define BM_I2C_VERSION_MAJOR        0xff000000
+#define BF_I2C_VERSION_MAJOR(v)     (((v) & 0xff) << 24)
+#define BFM_I2C_VERSION_MAJOR(v)    BM_I2C_VERSION_MAJOR
+#define BF_I2C_VERSION_MAJOR_V(e)   BF_I2C_VERSION_MAJOR(BV_I2C_VERSION_MAJOR__##e)
+#define BFM_I2C_VERSION_MAJOR_V(v)  BM_I2C_VERSION_MAJOR
+#define BP_I2C_VERSION_MINOR        16
+#define BM_I2C_VERSION_MINOR        0xff0000
+#define BF_I2C_VERSION_MINOR(v)     (((v) & 0xff) << 16)
+#define BFM_I2C_VERSION_MINOR(v)    BM_I2C_VERSION_MINOR
+#define BF_I2C_VERSION_MINOR_V(e)   BF_I2C_VERSION_MINOR(BV_I2C_VERSION_MINOR__##e)
+#define BFM_I2C_VERSION_MINOR_V(v)  BM_I2C_VERSION_MINOR
+#define BP_I2C_VERSION_STEP         0
+#define BM_I2C_VERSION_STEP         0xffff
+#define BF_I2C_VERSION_STEP(v)      (((v) & 0xffff) << 0)
+#define BFM_I2C_VERSION_STEP(v)     BM_I2C_VERSION_STEP
+#define BF_I2C_VERSION_STEP_V(e)    BF_I2C_VERSION_STEP(BV_I2C_VERSION_STEP__##e)
+#define BFM_I2C_VERSION_STEP_V(v)   BM_I2C_VERSION_STEP
+
+#endif /* __HEADERGEN_IMX233_I2C_H__*/
diff --git a/firmware/target/arm/imx233/regs/imx233/icoll.h b/firmware/target/arm/imx233/regs/imx233/icoll.h
new file mode 100644
index 0000000000..17c5d3bd75
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/imx233/icoll.h
@@ -0,0 +1,556 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * imx233 version: 2.4.0
+ * imx233 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_IMX233_ICOLL_H__
+#define __HEADERGEN_IMX233_ICOLL_H__
+
+#define HW_ICOLL_VECTOR                 HW(ICOLL_VECTOR)
+#define HWA_ICOLL_VECTOR                (0x80000000 + 0x0)
+#define HWT_ICOLL_VECTOR                HWIO_32_RW
+#define HWN_ICOLL_VECTOR                ICOLL_VECTOR
+#define HWI_ICOLL_VECTOR                
+#define HW_ICOLL_VECTOR_SET             HW(ICOLL_VECTOR_SET)
+#define HWA_ICOLL_VECTOR_SET            (HWA_ICOLL_VECTOR + 0x4)
+#define HWT_ICOLL_VECTOR_SET            HWIO_32_WO
+#define HWN_ICOLL_VECTOR_SET            ICOLL_VECTOR
+#define HWI_ICOLL_VECTOR_SET            
+#define HW_ICOLL_VECTOR_CLR             HW(ICOLL_VECTOR_CLR)
+#define HWA_ICOLL_VECTOR_CLR            (HWA_ICOLL_VECTOR + 0x8)
+#define HWT_ICOLL_VECTOR_CLR            HWIO_32_WO
+#define HWN_ICOLL_VECTOR_CLR            ICOLL_VECTOR
+#define HWI_ICOLL_VECTOR_CLR            
+#define HW_ICOLL_VECTOR_TOG             HW(ICOLL_VECTOR_TOG)
+#define HWA_ICOLL_VECTOR_TOG            (HWA_ICOLL_VECTOR + 0xc)
+#define HWT_ICOLL_VECTOR_TOG            HWIO_32_WO
+#define HWN_ICOLL_VECTOR_TOG            ICOLL_VECTOR
+#define HWI_ICOLL_VECTOR_TOG            
+#define BP_ICOLL_VECTOR_IRQVECTOR       2
+#define BM_ICOLL_VECTOR_IRQVECTOR       0xfffffffc
+#define BF_ICOLL_VECTOR_IRQVECTOR(v)    (((v) & 0x3fffffff) << 2)
+#define BFM_ICOLL_VECTOR_IRQVECTOR(v)   BM_ICOLL_VECTOR_IRQVECTOR
+#define BF_ICOLL_VECTOR_IRQVECTOR_V(e)  BF_ICOLL_VECTOR_IRQVECTOR(BV_ICOLL_VECTOR_IRQVECTOR__##e)
+#define BFM_ICOLL_VECTOR_IRQVECTOR_V(v) BM_ICOLL_VECTOR_IRQVECTOR
+#define BP_ICOLL_VECTOR_RSRVD1          0
+#define BM_ICOLL_VECTOR_RSRVD1          0x3
+#define BF_ICOLL_VECTOR_RSRVD1(v)       (((v) & 0x3) << 0)
+#define BFM_ICOLL_VECTOR_RSRVD1(v)      BM_ICOLL_VECTOR_RSRVD1
+#define BF_ICOLL_VECTOR_RSRVD1_V(e)     BF_ICOLL_VECTOR_RSRVD1(BV_ICOLL_VECTOR_RSRVD1__##e)
+#define BFM_ICOLL_VECTOR_RSRVD1_V(v)    BM_ICOLL_VECTOR_RSRVD1
+
+#define HW_ICOLL_LEVELACK                       HW(ICOLL_LEVELACK)
+#define HWA_ICOLL_LEVELACK                      (0x80000000 + 0x10)
+#define HWT_ICOLL_LEVELACK                      HWIO_32_RW
+#define HWN_ICOLL_LEVELACK                      ICOLL_LEVELACK
+#define HWI_ICOLL_LEVELACK                      
+#define BP_ICOLL_LEVELACK_RSRVD1                4
+#define BM_ICOLL_LEVELACK_RSRVD1                0xfffffff0
+#define BF_ICOLL_LEVELACK_RSRVD1(v)             (((v) & 0xfffffff) << 4)
+#define BFM_ICOLL_LEVELACK_RSRVD1(v)            BM_ICOLL_LEVELACK_RSRVD1
+#define BF_ICOLL_LEVELACK_RSRVD1_V(e)           BF_ICOLL_LEVELACK_RSRVD1(BV_ICOLL_LEVELACK_RSRVD1__##e)
+#define BFM_ICOLL_LEVELACK_RSRVD1_V(v)          BM_ICOLL_LEVELACK_RSRVD1
+#define BP_ICOLL_LEVELACK_IRQLEVELACK           0
+#define BM_ICOLL_LEVELACK_IRQLEVELACK           0xf
+#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0   0x1
+#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL1   0x2
+#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL2   0x4
+#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL3   0x8
+#define BF_ICOLL_LEVELACK_IRQLEVELACK(v)        (((v) & 0xf) << 0)
+#define BFM_ICOLL_LEVELACK_IRQLEVELACK(v)       BM_ICOLL_LEVELACK_IRQLEVELACK
+#define BF_ICOLL_LEVELACK_IRQLEVELACK_V(e)      BF_ICOLL_LEVELACK_IRQLEVELACK(BV_ICOLL_LEVELACK_IRQLEVELACK__##e)
+#define BFM_ICOLL_LEVELACK_IRQLEVELACK_V(v)     BM_ICOLL_LEVELACK_IRQLEVELACK
+
+#define HW_ICOLL_CTRL                           HW(ICOLL_CTRL)
+#define HWA_ICOLL_CTRL                          (0x80000000 + 0x20)
+#define HWT_ICOLL_CTRL                          HWIO_32_RW
+#define HWN_ICOLL_CTRL                          ICOLL_CTRL
+#define HWI_ICOLL_CTRL                          
+#define HW_ICOLL_CTRL_SET                       HW(ICOLL_CTRL_SET)
+#define HWA_ICOLL_CTRL_SET                      (HWA_ICOLL_CTRL + 0x4)
+#define HWT_ICOLL_CTRL_SET                      HWIO_32_WO
+#define HWN_ICOLL_CTRL_SET                      ICOLL_CTRL
+#define HWI_ICOLL_CTRL_SET                      
+#define HW_ICOLL_CTRL_CLR                       HW(ICOLL_CTRL_CLR)
+#define HWA_ICOLL_CTRL_CLR                      (HWA_ICOLL_CTRL + 0x8)
+#define HWT_ICOLL_CTRL_CLR                      HWIO_32_WO
+#define HWN_ICOLL_CTRL_CLR                      ICOLL_CTRL
+#define HWI_ICOLL_CTRL_CLR                      
+#define HW_ICOLL_CTRL_TOG                       HW(ICOLL_CTRL_TOG)
+#define HWA_ICOLL_CTRL_TOG                      (HWA_ICOLL_CTRL + 0xc)
+#define HWT_ICOLL_CTRL_TOG                      HWIO_32_WO
+#define HWN_ICOLL_CTRL_TOG                      ICOLL_CTRL
+#define HWI_ICOLL_CTRL_TOG                      
+#define BP_ICOLL_CTRL_SFTRST                    31
+#define BM_ICOLL_CTRL_SFTRST                    0x80000000
+#define BV_ICOLL_CTRL_SFTRST__RUN               0x0
+#define BV_ICOLL_CTRL_SFTRST__IN_RESET          0x1
+#define BF_ICOLL_CTRL_SFTRST(v)                 (((v) & 0x1) << 31)
+#define BFM_ICOLL_CTRL_SFTRST(v)                BM_ICOLL_CTRL_SFTRST
+#define BF_ICOLL_CTRL_SFTRST_V(e)               BF_ICOLL_CTRL_SFTRST(BV_ICOLL_CTRL_SFTRST__##e)
+#define BFM_ICOLL_CTRL_SFTRST_V(v)              BM_ICOLL_CTRL_SFTRST
+#define BP_ICOLL_CTRL_CLKGATE                   30
+#define BM_ICOLL_CTRL_CLKGATE                   0x40000000
+#define BV_ICOLL_CTRL_CLKGATE__RUN              0x0
+#define BV_ICOLL_CTRL_CLKGATE__NO_CLOCKS        0x1
+#define BF_ICOLL_CTRL_CLKGATE(v)                (((v) & 0x1) << 30)
+#define BFM_ICOLL_CTRL_CLKGATE(v)               BM_ICOLL_CTRL_CLKGATE
+#define BF_ICOLL_CTRL_CLKGATE_V(e)              BF_ICOLL_CTRL_CLKGATE(BV_ICOLL_CTRL_CLKGATE__##e)
+#define BFM_ICOLL_CTRL_CLKGATE_V(v)             BM_ICOLL_CTRL_CLKGATE
+#define BP_ICOLL_CTRL_RSRVD3                    24
+#define BM_ICOLL_CTRL_RSRVD3                    0x3f000000
+#define BF_ICOLL_CTRL_RSRVD3(v)                 (((v) & 0x3f) << 24)
+#define BFM_ICOLL_CTRL_RSRVD3(v)                BM_ICOLL_CTRL_RSRVD3
+#define BF_ICOLL_CTRL_RSRVD3_V(e)               BF_ICOLL_CTRL_RSRVD3(BV_ICOLL_CTRL_RSRVD3__##e)
+#define BFM_ICOLL_CTRL_RSRVD3_V(v)              BM_ICOLL_CTRL_RSRVD3
+#define BP_ICOLL_CTRL_VECTOR_PITCH              21
+#define BM_ICOLL_CTRL_VECTOR_PITCH              0xe00000
+#define BV_ICOLL_CTRL_VECTOR_PITCH__DEFAULT_BY4 0x0
+#define BV_ICOLL_CTRL_VECTOR_PITCH__BY4         0x1
+#define BV_ICOLL_CTRL_VECTOR_PITCH__BY8         0x2
+#define BV_ICOLL_CTRL_VECTOR_PITCH__BY12        0x3
+#define BV_ICOLL_CTRL_VECTOR_PITCH__BY16        0x4
+#define BV_ICOLL_CTRL_VECTOR_PITCH__BY20        0x5
+#define BV_ICOLL_CTRL_VECTOR_PITCH__BY24        0x6
+#define BV_ICOLL_CTRL_VECTOR_PITCH__BY28        0x7
+#define BF_ICOLL_CTRL_VECTOR_PITCH(v)           (((v) & 0x7) << 21)
+#define BFM_ICOLL_CTRL_VECTOR_PITCH(v)          BM_ICOLL_CTRL_VECTOR_PITCH
+#define BF_ICOLL_CTRL_VECTOR_PITCH_V(e)         BF_ICOLL_CTRL_VECTOR_PITCH(BV_ICOLL_CTRL_VECTOR_PITCH__##e)
+#define BFM_ICOLL_CTRL_VECTOR_PITCH_V(v)        BM_ICOLL_CTRL_VECTOR_PITCH
+#define BP_ICOLL_CTRL_BYPASS_FSM                20
+#define BM_ICOLL_CTRL_BYPASS_FSM                0x100000
+#define BV_ICOLL_CTRL_BYPASS_FSM__NORMAL        0x0
+#define BV_ICOLL_CTRL_BYPASS_FSM__BYPASS        0x1
+#define BF_ICOLL_CTRL_BYPASS_FSM(v)             (((v) & 0x1) << 20)
+#define BFM_ICOLL_CTRL_BYPASS_FSM(v)            BM_ICOLL_CTRL_BYPASS_FSM
+#define BF_ICOLL_CTRL_BYPASS_FSM_V(e)           BF_ICOLL_CTRL_BYPASS_FSM(BV_ICOLL_CTRL_BYPASS_FSM__##e)
+#define BFM_ICOLL_CTRL_BYPASS_FSM_V(v)          BM_ICOLL_CTRL_BYPASS_FSM
+#define BP_ICOLL_CTRL_NO_NESTING                19
+#define BM_ICOLL_CTRL_NO_NESTING                0x80000
+#define BV_ICOLL_CTRL_NO_NESTING__NORMAL        0x0
+#define BV_ICOLL_CTRL_NO_NESTING__NO_NEST       0x1
+#define BF_ICOLL_CTRL_NO_NESTING(v)             (((v) & 0x1) << 19)
+#define BFM_ICOLL_CTRL_NO_NESTING(v)            BM_ICOLL_CTRL_NO_NESTING
+#define BF_ICOLL_CTRL_NO_NESTING_V(e)           BF_ICOLL_CTRL_NO_NESTING(BV_ICOLL_CTRL_NO_NESTING__##e)
+#define BFM_ICOLL_CTRL_NO_NESTING_V(v)          BM_ICOLL_CTRL_NO_NESTING
+#define BP_ICOLL_CTRL_ARM_RSE_MODE              18
+#define BM_ICOLL_CTRL_ARM_RSE_MODE              0x40000
+#define BF_ICOLL_CTRL_ARM_RSE_MODE(v)           (((v) & 0x1) << 18)
+#define BFM_ICOLL_CTRL_ARM_RSE_MODE(v)          BM_ICOLL_CTRL_ARM_RSE_MODE
+#define BF_ICOLL_CTRL_ARM_RSE_MODE_V(e)         BF_ICOLL_CTRL_ARM_RSE_MODE(BV_ICOLL_CTRL_ARM_RSE_MODE__##e)
+#define BFM_ICOLL_CTRL_ARM_RSE_MODE_V(v)        BM_ICOLL_CTRL_ARM_RSE_MODE
+#define BP_ICOLL_CTRL_FIQ_FINAL_ENABLE          17
+#define BM_ICOLL_CTRL_FIQ_FINAL_ENABLE          0x20000
+#define BV_ICOLL_CTRL_FIQ_FINAL_ENABLE__DISABLE 0x0
+#define BV_ICOLL_CTRL_FIQ_FINAL_ENABLE__ENABLE  0x1
+#define BF_ICOLL_CTRL_FIQ_FINAL_ENABLE(v)       (((v) & 0x1) << 17)
+#define BFM_ICOLL_CTRL_FIQ_FINAL_ENABLE(v)      BM_ICOLL_CTRL_FIQ_FINAL_ENABLE
+#define BF_ICOLL_CTRL_FIQ_FINAL_ENABLE_V(e)     BF_ICOLL_CTRL_FIQ_FINAL_ENABLE(BV_ICOLL_CTRL_FIQ_FINAL_ENABLE__##e)
+#define BFM_ICOLL_CTRL_FIQ_FINAL_ENABLE_V(v)    BM_ICOLL_CTRL_FIQ_FINAL_ENABLE
+#define BP_ICOLL_CTRL_IRQ_FINAL_ENABLE          16
+#define BM_ICOLL_CTRL_IRQ_FINAL_ENABLE          0x10000
+#define BV_ICOLL_CTRL_IRQ_FINAL_ENABLE__DISABLE 0x0
+#define BV_ICOLL_CTRL_IRQ_FINAL_ENABLE__ENABLE  0x1
+#define BF_ICOLL_CTRL_IRQ_FINAL_ENABLE(v)       (((v) & 0x1) << 16)
+#define BFM_ICOLL_CTRL_IRQ_FINAL_ENABLE(v)      BM_ICOLL_CTRL_IRQ_FINAL_ENABLE
+#define BF_ICOLL_CTRL_IRQ_FINAL_ENABLE_V(e)     BF_ICOLL_CTRL_IRQ_FINAL_ENABLE(BV_ICOLL_CTRL_IRQ_FINAL_ENABLE__##e)
+#define BFM_ICOLL_CTRL_IRQ_FINAL_ENABLE_V(v)    BM_ICOLL_CTRL_IRQ_FINAL_ENABLE
+#define BP_ICOLL_CTRL_RSRVD1                    0
+#define BM_ICOLL_CTRL_RSRVD1                    0xffff
+#define BF_ICOLL_CTRL_RSRVD1(v)                 (((v) & 0xffff) << 0)
+#define BFM_ICOLL_CTRL_RSRVD1(v)                BM_ICOLL_CTRL_RSRVD1
+#define BF_ICOLL_CTRL_RSRVD1_V(e)               BF_ICOLL_CTRL_RSRVD1(BV_ICOLL_CTRL_RSRVD1__##e)
+#define BFM_ICOLL_CTRL_RSRVD1_V(v)              BM_ICOLL_CTRL_RSRVD1
+
+#define HW_ICOLL_VBASE                      HW(ICOLL_VBASE)
+#define HWA_ICOLL_VBASE                     (0x80000000 + 0x40)
+#define HWT_ICOLL_VBASE                     HWIO_32_RW
+#define HWN_ICOLL_VBASE                     ICOLL_VBASE
+#define HWI_ICOLL_VBASE                     
+#define HW_ICOLL_VBASE_SET                  HW(ICOLL_VBASE_SET)
+#define HWA_ICOLL_VBASE_SET                 (HWA_ICOLL_VBASE + 0x4)
+#define HWT_ICOLL_VBASE_SET                 HWIO_32_WO
+#define HWN_ICOLL_VBASE_SET                 ICOLL_VBASE
+#define HWI_ICOLL_VBASE_SET                 
+#define HW_ICOLL_VBASE_CLR                  HW(ICOLL_VBASE_CLR)
+#define HWA_ICOLL_VBASE_CLR                 (HWA_ICOLL_VBASE + 0x8)
+#define HWT_ICOLL_VBASE_CLR                 HWIO_32_WO
+#define HWN_ICOLL_VBASE_CLR                 ICOLL_VBASE
+#define HWI_ICOLL_VBASE_CLR                 
+#define HW_ICOLL_VBASE_TOG                  HW(ICOLL_VBASE_TOG)
+#define HWA_ICOLL_VBASE_TOG                 (HWA_ICOLL_VBASE + 0xc)
+#define HWT_ICOLL_VBASE_TOG                 HWIO_32_WO
+#define HWN_ICOLL_VBASE_TOG                 ICOLL_VBASE
+#define HWI_ICOLL_VBASE_TOG                 
+#define BP_ICOLL_VBASE_TABLE_ADDRESS        2
+#define BM_ICOLL_VBASE_TABLE_ADDRESS        0xfffffffc
+#define BF_ICOLL_VBASE_TABLE_ADDRESS(v)     (((v) & 0x3fffffff) << 2)
+#define BFM_ICOLL_VBASE_TABLE_ADDRESS(v)    BM_ICOLL_VBASE_TABLE_ADDRESS
+#define BF_ICOLL_VBASE_TABLE_ADDRESS_V(e)   BF_ICOLL_VBASE_TABLE_ADDRESS(BV_ICOLL_VBASE_TABLE_ADDRESS__##e)
+#define BFM_ICOLL_VBASE_TABLE_ADDRESS_V(v)  BM_ICOLL_VBASE_TABLE_ADDRESS
+#define BP_ICOLL_VBASE_RSRVD1               0
+#define BM_ICOLL_VBASE_RSRVD1               0x3
+#define BF_ICOLL_VBASE_RSRVD1(v)            (((v) & 0x3) << 0)
+#define BFM_ICOLL_VBASE_RSRVD1(v)           BM_ICOLL_VBASE_RSRVD1
+#define BF_ICOLL_VBASE_RSRVD1_V(e)          BF_ICOLL_VBASE_RSRVD1(BV_ICOLL_VBASE_RSRVD1__##e)
+#define BFM_ICOLL_VBASE_RSRVD1_V(v)         BM_ICOLL_VBASE_RSRVD1
+
+#define HW_ICOLL_STAT                       HW(ICOLL_STAT)
+#define HWA_ICOLL_STAT                      (0x80000000 + 0x70)
+#define HWT_ICOLL_STAT                      HWIO_32_RW
+#define HWN_ICOLL_STAT                      ICOLL_STAT
+#define HWI_ICOLL_STAT                      
+#define BP_ICOLL_STAT_RSRVD1                7
+#define BM_ICOLL_STAT_RSRVD1                0xffffff80
+#define BF_ICOLL_STAT_RSRVD1(v)             (((v) & 0x1ffffff) << 7)
+#define BFM_ICOLL_STAT_RSRVD1(v)            BM_ICOLL_STAT_RSRVD1
+#define BF_ICOLL_STAT_RSRVD1_V(e)           BF_ICOLL_STAT_RSRVD1(BV_ICOLL_STAT_RSRVD1__##e)
+#define BFM_ICOLL_STAT_RSRVD1_V(v)          BM_ICOLL_STAT_RSRVD1
+#define BP_ICOLL_STAT_VECTOR_NUMBER         0
+#define BM_ICOLL_STAT_VECTOR_NUMBER         0x7f
+#define BF_ICOLL_STAT_VECTOR_NUMBER(v)      (((v) & 0x7f) << 0)
+#define BFM_ICOLL_STAT_VECTOR_NUMBER(v)     BM_ICOLL_STAT_VECTOR_NUMBER
+#define BF_ICOLL_STAT_VECTOR_NUMBER_V(e)    BF_ICOLL_STAT_VECTOR_NUMBER(BV_ICOLL_STAT_VECTOR_NUMBER__##e)
+#define BFM_ICOLL_STAT_VECTOR_NUMBER_V(v)   BM_ICOLL_STAT_VECTOR_NUMBER
+
+#define HW_ICOLL_RAWn(_n1)              HW(ICOLL_RAWn(_n1))
+#define HWA_ICOLL_RAWn(_n1)             (0x80000000 + 0xa0 + (_n1) * 0x10)
+#define HWT_ICOLL_RAWn(_n1)             HWIO_32_RW
+#define HWN_ICOLL_RAWn(_n1)             ICOLL_RAWn
+#define HWI_ICOLL_RAWn(_n1)             (_n1)
+#define HW_ICOLL_RAWn_SET(_n1)          HW(ICOLL_RAWn_SET(_n1))
+#define HWA_ICOLL_RAWn_SET(_n1)         (HWA_ICOLL_RAWn(_n1) + 0x4)
+#define HWT_ICOLL_RAWn_SET(_n1)         HWIO_32_WO
+#define HWN_ICOLL_RAWn_SET(_n1)         ICOLL_RAWn
+#define HWI_ICOLL_RAWn_SET(_n1)         (_n1)
+#define HW_ICOLL_RAWn_CLR(_n1)          HW(ICOLL_RAWn_CLR(_n1))
+#define HWA_ICOLL_RAWn_CLR(_n1)         (HWA_ICOLL_RAWn(_n1) + 0x8)
+#define HWT_ICOLL_RAWn_CLR(_n1)         HWIO_32_WO
+#define HWN_ICOLL_RAWn_CLR(_n1)         ICOLL_RAWn
+#define HWI_ICOLL_RAWn_CLR(_n1)         (_n1)
+#define HW_ICOLL_RAWn_TOG(_n1)          HW(ICOLL_RAWn_TOG(_n1))
+#define HWA_ICOLL_RAWn_TOG(_n1)         (HWA_ICOLL_RAWn(_n1) + 0xc)
+#define HWT_ICOLL_RAWn_TOG(_n1)         HWIO_32_WO
+#define HWN_ICOLL_RAWn_TOG(_n1)         ICOLL_RAWn
+#define HWI_ICOLL_RAWn_TOG(_n1)         (_n1)
+#define BP_ICOLL_RAWn_RAW_IRQS          0
+#define BM_ICOLL_RAWn_RAW_IRQS          0xffffffff
+#define BF_ICOLL_RAWn_RAW_IRQS(v)       (((v) & 0xffffffff) << 0)
+#define BFM_ICOLL_RAWn_RAW_IRQS(v)      BM_ICOLL_RAWn_RAW_IRQS
+#define BF_ICOLL_RAWn_RAW_IRQS_V(e)     BF_ICOLL_RAWn_RAW_IRQS(BV_ICOLL_RAWn_RAW_IRQS__##e)
+#define BFM_ICOLL_RAWn_RAW_IRQS_V(v)    BM_ICOLL_RAWn_RAW_IRQS
+
+#define HW_ICOLL_INTERRUPTn(_n1)                        HW(ICOLL_INTERRUPTn(_n1))
+#define HWA_ICOLL_INTERRUPTn(_n1)                       (0x80000000 + 0x120 + (_n1) * 0x10)
+#define HWT_ICOLL_INTERRUPTn(_n1)                       HWIO_32_RW
+#define HWN_ICOLL_INTERRUPTn(_n1)                       ICOLL_INTERRUPTn
+#define HWI_ICOLL_INTERRUPTn(_n1)                       (_n1)
+#define HW_ICOLL_INTERRUPTn_SET(_n1)                    HW(ICOLL_INTERRUPTn_SET(_n1))
+#define HWA_ICOLL_INTERRUPTn_SET(_n1)                   (HWA_ICOLL_INTERRUPTn(_n1) + 0x4)
+#define HWT_ICOLL_INTERRUPTn_SET(_n1)                   HWIO_32_WO
+#define HWN_ICOLL_INTERRUPTn_SET(_n1)                   ICOLL_INTERRUPTn
+#define HWI_ICOLL_INTERRUPTn_SET(_n1)                   (_n1)
+#define HW_ICOLL_INTERRUPTn_CLR(_n1)                    HW(ICOLL_INTERRUPTn_CLR(_n1))
+#define HWA_ICOLL_INTERRUPTn_CLR(_n1)                   (HWA_ICOLL_INTERRUPTn(_n1) + 0x8)
+#define HWT_ICOLL_INTERRUPTn_CLR(_n1)                   HWIO_32_WO
+#define HWN_ICOLL_INTERRUPTn_CLR(_n1)                   ICOLL_INTERRUPTn
+#define HWI_ICOLL_INTERRUPTn_CLR(_n1)                   (_n1)
+#define HW_ICOLL_INTERRUPTn_TOG(_n1)                    HW(ICOLL_INTERRUPTn_TOG(_n1))
+#define HWA_ICOLL_INTERRUPTn_TOG(_n1)                   (HWA_ICOLL_INTERRUPTn(_n1) + 0xc)
+#define HWT_ICOLL_INTERRUPTn_TOG(_n1)                   HWIO_32_WO
+#define HWN_ICOLL_INTERRUPTn_TOG(_n1)                   ICOLL_INTERRUPTn
+#define HWI_ICOLL_INTERRUPTn_TOG(_n1)                   (_n1)
+#define BP_ICOLL_INTERRUPTn_RSRVD1                      5
+#define BM_ICOLL_INTERRUPTn_RSRVD1                      0xffffffe0
+#define BF_ICOLL_INTERRUPTn_RSRVD1(v)                   (((v) & 0x7ffffff) << 5)
+#define BFM_ICOLL_INTERRUPTn_RSRVD1(v)                  BM_ICOLL_INTERRUPTn_RSRVD1
+#define BF_ICOLL_INTERRUPTn_RSRVD1_V(e)                 BF_ICOLL_INTERRUPTn_RSRVD1(BV_ICOLL_INTERRUPTn_RSRVD1__##e)
+#define BFM_ICOLL_INTERRUPTn_RSRVD1_V(v)                BM_ICOLL_INTERRUPTn_RSRVD1
+#define BP_ICOLL_INTERRUPTn_ENFIQ                       4
+#define BM_ICOLL_INTERRUPTn_ENFIQ                       0x10
+#define BV_ICOLL_INTERRUPTn_ENFIQ__DISABLE              0x0
+#define BV_ICOLL_INTERRUPTn_ENFIQ__ENABLE               0x1
+#define BF_ICOLL_INTERRUPTn_ENFIQ(v)                    (((v) & 0x1) << 4)
+#define BFM_ICOLL_INTERRUPTn_ENFIQ(v)                   BM_ICOLL_INTERRUPTn_ENFIQ
+#define BF_ICOLL_INTERRUPTn_ENFIQ_V(e)                  BF_ICOLL_INTERRUPTn_ENFIQ(BV_ICOLL_INTERRUPTn_ENFIQ__##e)
+#define BFM_ICOLL_INTERRUPTn_ENFIQ_V(v)                 BM_ICOLL_INTERRUPTn_ENFIQ
+#define BP_ICOLL_INTERRUPTn_SOFTIRQ                     3
+#define BM_ICOLL_INTERRUPTn_SOFTIRQ                     0x8
+#define BV_ICOLL_INTERRUPTn_SOFTIRQ__NO_INTERRUPT       0x0
+#define BV_ICOLL_INTERRUPTn_SOFTIRQ__FORCE_INTERRUPT    0x1
+#define BF_ICOLL_INTERRUPTn_SOFTIRQ(v)                  (((v) & 0x1) << 3)
+#define BFM_ICOLL_INTERRUPTn_SOFTIRQ(v)                 BM_ICOLL_INTERRUPTn_SOFTIRQ
+#define BF_ICOLL_INTERRUPTn_SOFTIRQ_V(e)                BF_ICOLL_INTERRUPTn_SOFTIRQ(BV_ICOLL_INTERRUPTn_SOFTIRQ__##e)
+#define BFM_ICOLL_INTERRUPTn_SOFTIRQ_V(v)               BM_ICOLL_INTERRUPTn_SOFTIRQ
+#define BP_ICOLL_INTERRUPTn_ENABLE                      2
+#define BM_ICOLL_INTERRUPTn_ENABLE                      0x4
+#define BV_ICOLL_INTERRUPTn_ENABLE__DISABLE             0x0
+#define BV_ICOLL_INTERRUPTn_ENABLE__ENABLE              0x1
+#define BF_ICOLL_INTERRUPTn_ENABLE(v)                   (((v) & 0x1) << 2)
+#define BFM_ICOLL_INTERRUPTn_ENABLE(v)                  BM_ICOLL_INTERRUPTn_ENABLE
+#define BF_ICOLL_INTERRUPTn_ENABLE_V(e)                 BF_ICOLL_INTERRUPTn_ENABLE(BV_ICOLL_INTERRUPTn_ENABLE__##e)
+#define BFM_ICOLL_INTERRUPTn_ENABLE_V(v)                BM_ICOLL_INTERRUPTn_ENABLE
+#define BP_ICOLL_INTERRUPTn_PRIORITY                    0
+#define BM_ICOLL_INTERRUPTn_PRIORITY                    0x3
+#define BV_ICOLL_INTERRUPTn_PRIORITY__LEVEL0            0x0
+#define BV_ICOLL_INTERRUPTn_PRIORITY__LEVEL1            0x1
+#define BV_ICOLL_INTERRUPTn_PRIORITY__LEVEL2            0x2
+#define BV_ICOLL_INTERRUPTn_PRIORITY__LEVEL3            0x3
+#define BF_ICOLL_INTERRUPTn_PRIORITY(v)                 (((v) & 0x3) << 0)
+#define BFM_ICOLL_INTERRUPTn_PRIORITY(v)                BM_ICOLL_INTERRUPTn_PRIORITY
+#define BF_ICOLL_INTERRUPTn_PRIORITY_V(e)               BF_ICOLL_INTERRUPTn_PRIORITY(BV_ICOLL_INTERRUPTn_PRIORITY__##e)
+#define BFM_ICOLL_INTERRUPTn_PRIORITY_V(v)              BM_ICOLL_INTERRUPTn_PRIORITY
+
+#define HW_ICOLL_DEBUG                              HW(ICOLL_DEBUG)
+#define HWA_ICOLL_DEBUG                             (0x80000000 + 0x1120)
+#define HWT_ICOLL_DEBUG                             HWIO_32_RW
+#define HWN_ICOLL_DEBUG                             ICOLL_DEBUG
+#define HWI_ICOLL_DEBUG                             
+#define HW_ICOLL_DEBUG_SET                          HW(ICOLL_DEBUG_SET)
+#define HWA_ICOLL_DEBUG_SET                         (HWA_ICOLL_DEBUG + 0x4)
+#define HWT_ICOLL_DEBUG_SET                         HWIO_32_WO
+#define HWN_ICOLL_DEBUG_SET                         ICOLL_DEBUG
+#define HWI_ICOLL_DEBUG_SET                         
+#define HW_ICOLL_DEBUG_CLR                          HW(ICOLL_DEBUG_CLR)
+#define HWA_ICOLL_DEBUG_CLR                         (HWA_ICOLL_DEBUG + 0x8)
+#define HWT_ICOLL_DEBUG_CLR                         HWIO_32_WO
+#define HWN_ICOLL_DEBUG_CLR                         ICOLL_DEBUG
+#define HWI_ICOLL_DEBUG_CLR                         
+#define HW_ICOLL_DEBUG_TOG                          HW(ICOLL_DEBUG_TOG)
+#define HWA_ICOLL_DEBUG_TOG                         (HWA_ICOLL_DEBUG + 0xc)
+#define HWT_ICOLL_DEBUG_TOG                         HWIO_32_WO
+#define HWN_ICOLL_DEBUG_TOG                         ICOLL_DEBUG
+#define HWI_ICOLL_DEBUG_TOG                         
+#define BP_ICOLL_DEBUG_INSERVICE                    28
+#define BM_ICOLL_DEBUG_INSERVICE                    0xf0000000
+#define BV_ICOLL_DEBUG_INSERVICE__LEVEL0            0x1
+#define BV_ICOLL_DEBUG_INSERVICE__LEVEL1            0x2
+#define BV_ICOLL_DEBUG_INSERVICE__LEVEL2            0x4
+#define BV_ICOLL_DEBUG_INSERVICE__LEVEL3            0x8
+#define BF_ICOLL_DEBUG_INSERVICE(v)                 (((v) & 0xf) << 28)
+#define BFM_ICOLL_DEBUG_INSERVICE(v)                BM_ICOLL_DEBUG_INSERVICE
+#define BF_ICOLL_DEBUG_INSERVICE_V(e)               BF_ICOLL_DEBUG_INSERVICE(BV_ICOLL_DEBUG_INSERVICE__##e)
+#define BFM_ICOLL_DEBUG_INSERVICE_V(v)              BM_ICOLL_DEBUG_INSERVICE
+#define BP_ICOLL_DEBUG_LEVEL_REQUESTS               24
+#define BM_ICOLL_DEBUG_LEVEL_REQUESTS               0xf000000
+#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL0       0x1
+#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL1       0x2
+#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL2       0x4
+#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL3       0x8
+#define BF_ICOLL_DEBUG_LEVEL_REQUESTS(v)            (((v) & 0xf) << 24)
+#define BFM_ICOLL_DEBUG_LEVEL_REQUESTS(v)           BM_ICOLL_DEBUG_LEVEL_REQUESTS
+#define BF_ICOLL_DEBUG_LEVEL_REQUESTS_V(e)          BF_ICOLL_DEBUG_LEVEL_REQUESTS(BV_ICOLL_DEBUG_LEVEL_REQUESTS__##e)
+#define BFM_ICOLL_DEBUG_LEVEL_REQUESTS_V(v)         BM_ICOLL_DEBUG_LEVEL_REQUESTS
+#define BP_ICOLL_DEBUG_REQUESTS_BY_LEVEL            20
+#define BM_ICOLL_DEBUG_REQUESTS_BY_LEVEL            0xf00000
+#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL0    0x1
+#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL1    0x2
+#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL2    0x4
+#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL3    0x8
+#define BF_ICOLL_DEBUG_REQUESTS_BY_LEVEL(v)         (((v) & 0xf) << 20)
+#define BFM_ICOLL_DEBUG_REQUESTS_BY_LEVEL(v)        BM_ICOLL_DEBUG_REQUESTS_BY_LEVEL
+#define BF_ICOLL_DEBUG_REQUESTS_BY_LEVEL_V(e)       BF_ICOLL_DEBUG_REQUESTS_BY_LEVEL(BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__##e)
+#define BFM_ICOLL_DEBUG_REQUESTS_BY_LEVEL_V(v)      BM_ICOLL_DEBUG_REQUESTS_BY_LEVEL
+#define BP_ICOLL_DEBUG_RSRVD2                       18
+#define BM_ICOLL_DEBUG_RSRVD2                       0xc0000
+#define BF_ICOLL_DEBUG_RSRVD2(v)                    (((v) & 0x3) << 18)
+#define BFM_ICOLL_DEBUG_RSRVD2(v)                   BM_ICOLL_DEBUG_RSRVD2
+#define BF_ICOLL_DEBUG_RSRVD2_V(e)                  BF_ICOLL_DEBUG_RSRVD2(BV_ICOLL_DEBUG_RSRVD2__##e)
+#define BFM_ICOLL_DEBUG_RSRVD2_V(v)                 BM_ICOLL_DEBUG_RSRVD2
+#define BP_ICOLL_DEBUG_FIQ                          17
+#define BM_ICOLL_DEBUG_FIQ                          0x20000
+#define BV_ICOLL_DEBUG_FIQ__NO_FIQ_REQUESTED        0x0
+#define BV_ICOLL_DEBUG_FIQ__FIQ_REQUESTED           0x1
+#define BF_ICOLL_DEBUG_FIQ(v)                       (((v) & 0x1) << 17)
+#define BFM_ICOLL_DEBUG_FIQ(v)                      BM_ICOLL_DEBUG_FIQ
+#define BF_ICOLL_DEBUG_FIQ_V(e)                     BF_ICOLL_DEBUG_FIQ(BV_ICOLL_DEBUG_FIQ__##e)
+#define BFM_ICOLL_DEBUG_FIQ_V(v)                    BM_ICOLL_DEBUG_FIQ
+#define BP_ICOLL_DEBUG_IRQ                          16
+#define BM_ICOLL_DEBUG_IRQ                          0x10000
+#define BV_ICOLL_DEBUG_IRQ__NO_IRQ_REQUESTED        0x0
+#define BV_ICOLL_DEBUG_IRQ__IRQ_REQUESTED           0x1
+#define BF_ICOLL_DEBUG_IRQ(v)                       (((v) & 0x1) << 16)
+#define BFM_ICOLL_DEBUG_IRQ(v)                      BM_ICOLL_DEBUG_IRQ
+#define BF_ICOLL_DEBUG_IRQ_V(e)                     BF_ICOLL_DEBUG_IRQ(BV_ICOLL_DEBUG_IRQ__##e)
+#define BFM_ICOLL_DEBUG_IRQ_V(v)                    BM_ICOLL_DEBUG_IRQ
+#define BP_ICOLL_DEBUG_RSRVD1                       10
+#define BM_ICOLL_DEBUG_RSRVD1                       0xfc00
+#define BF_ICOLL_DEBUG_RSRVD1(v)                    (((v) & 0x3f) << 10)
+#define BFM_ICOLL_DEBUG_RSRVD1(v)                   BM_ICOLL_DEBUG_RSRVD1
+#define BF_ICOLL_DEBUG_RSRVD1_V(e)                  BF_ICOLL_DEBUG_RSRVD1(BV_ICOLL_DEBUG_RSRVD1__##e)
+#define BFM_ICOLL_DEBUG_RSRVD1_V(v)                 BM_ICOLL_DEBUG_RSRVD1
+#define BP_ICOLL_DEBUG_VECTOR_FSM                   0
+#define BM_ICOLL_DEBUG_VECTOR_FSM                   0x3ff
+#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_IDLE         0x0
+#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE1  0x1
+#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE2  0x2
+#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_PENDING      0x4
+#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE3  0x8
+#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE4  0x10
+#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING1 0x20
+#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING2 0x40
+#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING3 0x80
+#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE5  0x100
+#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE6  0x200
+#define BF_ICOLL_DEBUG_VECTOR_FSM(v)                (((v) & 0x3ff) << 0)
+#define BFM_ICOLL_DEBUG_VECTOR_FSM(v)               BM_ICOLL_DEBUG_VECTOR_FSM
+#define BF_ICOLL_DEBUG_VECTOR_FSM_V(e)              BF_ICOLL_DEBUG_VECTOR_FSM(BV_ICOLL_DEBUG_VECTOR_FSM__##e)
+#define BFM_ICOLL_DEBUG_VECTOR_FSM_V(v)             BM_ICOLL_DEBUG_VECTOR_FSM
+
+#define HW_ICOLL_DBGREAD0               HW(ICOLL_DBGREAD0)
+#define HWA_ICOLL_DBGREAD0              (0x80000000 + 0x1130)
+#define HWT_ICOLL_DBGREAD0              HWIO_32_RW
+#define HWN_ICOLL_DBGREAD0              ICOLL_DBGREAD0
+#define HWI_ICOLL_DBGREAD0              
+#define HW_ICOLL_DBGREAD0_SET           HW(ICOLL_DBGREAD0_SET)
+#define HWA_ICOLL_DBGREAD0_SET          (HWA_ICOLL_DBGREAD0 + 0x4)
+#define HWT_ICOLL_DBGREAD0_SET          HWIO_32_WO
+#define HWN_ICOLL_DBGREAD0_SET          ICOLL_DBGREAD0
+#define HWI_ICOLL_DBGREAD0_SET          
+#define HW_ICOLL_DBGREAD0_CLR           HW(ICOLL_DBGREAD0_CLR)
+#define HWA_ICOLL_DBGREAD0_CLR          (HWA_ICOLL_DBGREAD0 + 0x8)
+#define HWT_ICOLL_DBGREAD0_CLR          HWIO_32_WO
+#define HWN_ICOLL_DBGREAD0_CLR          ICOLL_DBGREAD0
+#define HWI_ICOLL_DBGREAD0_CLR          
+#define HW_ICOLL_DBGREAD0_TOG           HW(ICOLL_DBGREAD0_TOG)
+#define HWA_ICOLL_DBGREAD0_TOG          (HWA_ICOLL_DBGREAD0 + 0xc)
+#define HWT_ICOLL_DBGREAD0_TOG          HWIO_32_WO
+#define HWN_ICOLL_DBGREAD0_TOG          ICOLL_DBGREAD0
+#define HWI_ICOLL_DBGREAD0_TOG          
+#define BP_ICOLL_DBGREAD0_VALUE         0
+#define BM_ICOLL_DBGREAD0_VALUE         0xffffffff
+#define BF_ICOLL_DBGREAD0_VALUE(v)      (((v) & 0xffffffff) << 0)
+#define BFM_ICOLL_DBGREAD0_VALUE(v)     BM_ICOLL_DBGREAD0_VALUE
+#define BF_ICOLL_DBGREAD0_VALUE_V(e)    BF_ICOLL_DBGREAD0_VALUE(BV_ICOLL_DBGREAD0_VALUE__##e)
+#define BFM_ICOLL_DBGREAD0_VALUE_V(v)   BM_ICOLL_DBGREAD0_VALUE
+
+#define HW_ICOLL_DBGREAD1               HW(ICOLL_DBGREAD1)
+#define HWA_ICOLL_DBGREAD1              (0x80000000 + 0x1140)
+#define HWT_ICOLL_DBGREAD1              HWIO_32_RW
+#define HWN_ICOLL_DBGREAD1              ICOLL_DBGREAD1
+#define HWI_ICOLL_DBGREAD1              
+#define HW_ICOLL_DBGREAD1_SET           HW(ICOLL_DBGREAD1_SET)
+#define HWA_ICOLL_DBGREAD1_SET          (HWA_ICOLL_DBGREAD1 + 0x4)
+#define HWT_ICOLL_DBGREAD1_SET          HWIO_32_WO
+#define HWN_ICOLL_DBGREAD1_SET          ICOLL_DBGREAD1
+#define HWI_ICOLL_DBGREAD1_SET          
+#define HW_ICOLL_DBGREAD1_CLR           HW(ICOLL_DBGREAD1_CLR)
+#define HWA_ICOLL_DBGREAD1_CLR          (HWA_ICOLL_DBGREAD1 + 0x8)
+#define HWT_ICOLL_DBGREAD1_CLR          HWIO_32_WO
+#define HWN_ICOLL_DBGREAD1_CLR          ICOLL_DBGREAD1
+#define HWI_ICOLL_DBGREAD1_CLR          
+#define HW_ICOLL_DBGREAD1_TOG           HW(ICOLL_DBGREAD1_TOG)
+#define HWA_ICOLL_DBGREAD1_TOG          (HWA_ICOLL_DBGREAD1 + 0xc)
+#define HWT_ICOLL_DBGREAD1_TOG          HWIO_32_WO
+#define HWN_ICOLL_DBGREAD1_TOG          ICOLL_DBGREAD1
+#define HWI_ICOLL_DBGREAD1_TOG          
+#define BP_ICOLL_DBGREAD1_VALUE         0
+#define BM_ICOLL_DBGREAD1_VALUE         0xffffffff
+#define BF_ICOLL_DBGREAD1_VALUE(v)      (((v) & 0xffffffff) << 0)
+#define BFM_ICOLL_DBGREAD1_VALUE(v)     BM_ICOLL_DBGREAD1_VALUE
+#define BF_ICOLL_DBGREAD1_VALUE_V(e)    BF_ICOLL_DBGREAD1_VALUE(BV_ICOLL_DBGREAD1_VALUE__##e)
+#define BFM_ICOLL_DBGREAD1_VALUE_V(v)   BM_ICOLL_DBGREAD1_VALUE
+
+#define HW_ICOLL_DBGFLAG                HW(ICOLL_DBGFLAG)
+#define HWA_ICOLL_DBGFLAG               (0x80000000 + 0x1150)
+#define HWT_ICOLL_DBGFLAG               HWIO_32_RW
+#define HWN_ICOLL_DBGFLAG               ICOLL_DBGFLAG
+#define HWI_ICOLL_DBGFLAG               
+#define HW_ICOLL_DBGFLAG_SET            HW(ICOLL_DBGFLAG_SET)
+#define HWA_ICOLL_DBGFLAG_SET           (HWA_ICOLL_DBGFLAG + 0x4)
+#define HWT_ICOLL_DBGFLAG_SET           HWIO_32_WO
+#define HWN_ICOLL_DBGFLAG_SET           ICOLL_DBGFLAG
+#define HWI_ICOLL_DBGFLAG_SET           
+#define HW_ICOLL_DBGFLAG_CLR            HW(ICOLL_DBGFLAG_CLR)
+#define HWA_ICOLL_DBGFLAG_CLR           (HWA_ICOLL_DBGFLAG + 0x8)
+#define HWT_ICOLL_DBGFLAG_CLR           HWIO_32_WO
+#define HWN_ICOLL_DBGFLAG_CLR           ICOLL_DBGFLAG
+#define HWI_ICOLL_DBGFLAG_CLR           
+#define HW_ICOLL_DBGFLAG_TOG            HW(ICOLL_DBGFLAG_TOG)
+#define HWA_ICOLL_DBGFLAG_TOG           (HWA_ICOLL_DBGFLAG + 0xc)
+#define HWT_ICOLL_DBGFLAG_TOG           HWIO_32_WO
+#define HWN_ICOLL_DBGFLAG_TOG           ICOLL_DBGFLAG
+#define HWI_ICOLL_DBGFLAG_TOG           
+#define BP_ICOLL_DBGFLAG_RSRVD1         16
+#define BM_ICOLL_DBGFLAG_RSRVD1         0xffff0000
+#define BF_ICOLL_DBGFLAG_RSRVD1(v)      (((v) & 0xffff) << 16)
+#define BFM_ICOLL_DBGFLAG_RSRVD1(v)     BM_ICOLL_DBGFLAG_RSRVD1
+#define BF_ICOLL_DBGFLAG_RSRVD1_V(e)    BF_ICOLL_DBGFLAG_RSRVD1(BV_ICOLL_DBGFLAG_RSRVD1__##e)
+#define BFM_ICOLL_DBGFLAG_RSRVD1_V(v)   BM_ICOLL_DBGFLAG_RSRVD1
+#define BP_ICOLL_DBGFLAG_FLAG           0
+#define BM_ICOLL_DBGFLAG_FLAG           0xffff
+#define BF_ICOLL_DBGFLAG_FLAG(v)        (((v) & 0xffff) << 0)
+#define BFM_ICOLL_DBGFLAG_FLAG(v)       BM_ICOLL_DBGFLAG_FLAG
+#define BF_ICOLL_DBGFLAG_FLAG_V(e)      BF_ICOLL_DBGFLAG_FLAG(BV_ICOLL_DBGFLAG_FLAG__##e)
+#define BFM_ICOLL_DBGFLAG_FLAG_V(v)     BM_ICOLL_DBGFLAG_FLAG
+
+#define HW_ICOLL_DBGREQUESTn(_n1)       HW(ICOLL_DBGREQUESTn(_n1))
+#define HWA_ICOLL_DBGREQUESTn(_n1)      (0x80000000 + 0x1160 + (_n1) * 0x10)
+#define HWT_ICOLL_DBGREQUESTn(_n1)      HWIO_32_RW
+#define HWN_ICOLL_DBGREQUESTn(_n1)      ICOLL_DBGREQUESTn
+#define HWI_ICOLL_DBGREQUESTn(_n1)      (_n1)
+#define HW_ICOLL_DBGREQUESTn_SET(_n1)   HW(ICOLL_DBGREQUESTn_SET(_n1))
+#define HWA_ICOLL_DBGREQUESTn_SET(_n1)  (HWA_ICOLL_DBGREQUESTn(_n1) + 0x4)
+#define HWT_ICOLL_DBGREQUESTn_SET(_n1)  HWIO_32_WO
+#define HWN_ICOLL_DBGREQUESTn_SET(_n1)  ICOLL_DBGREQUESTn
+#define HWI_ICOLL_DBGREQUESTn_SET(_n1)  (_n1)
+#define HW_ICOLL_DBGREQUESTn_CLR(_n1)   HW(ICOLL_DBGREQUESTn_CLR(_n1))
+#define HWA_ICOLL_DBGREQUESTn_CLR(_n1)  (HWA_ICOLL_DBGREQUESTn(_n1) + 0x8)
+#define HWT_ICOLL_DBGREQUESTn_CLR(_n1)  HWIO_32_WO
+#define HWN_ICOLL_DBGREQUESTn_CLR(_n1)  ICOLL_DBGREQUESTn
+#define HWI_ICOLL_DBGREQUESTn_CLR(_n1)  (_n1)
+#define HW_ICOLL_DBGREQUESTn_TOG(_n1)   HW(ICOLL_DBGREQUESTn_TOG(_n1))
+#define HWA_ICOLL_DBGREQUESTn_TOG(_n1)  (HWA_ICOLL_DBGREQUESTn(_n1) + 0xc)
+#define HWT_ICOLL_DBGREQUESTn_TOG(_n1)  HWIO_32_WO
+#define HWN_ICOLL_DBGREQUESTn_TOG(_n1)  ICOLL_DBGREQUESTn
+#define HWI_ICOLL_DBGREQUESTn_TOG(_n1)  (_n1)
+#define BP_ICOLL_DBGREQUESTn_BITS       0
+#define BM_ICOLL_DBGREQUESTn_BITS       0xffffffff
+#define BF_ICOLL_DBGREQUESTn_BITS(v)    (((v) & 0xffffffff) << 0)
+#define BFM_ICOLL_DBGREQUESTn_BITS(v)   BM_ICOLL_DBGREQUESTn_BITS
+#define BF_ICOLL_DBGREQUESTn_BITS_V(e)  BF_ICOLL_DBGREQUESTn_BITS(BV_ICOLL_DBGREQUESTn_BITS__##e)
+#define BFM_ICOLL_DBGREQUESTn_BITS_V(v) BM_ICOLL_DBGREQUESTn_BITS
+
+#define HW_ICOLL_VERSION                HW(ICOLL_VERSION)
+#define HWA_ICOLL_VERSION               (0x80000000 + 0x11e0)
+#define HWT_ICOLL_VERSION               HWIO_32_RW
+#define HWN_ICOLL_VERSION               ICOLL_VERSION
+#define HWI_ICOLL_VERSION               
+#define BP_ICOLL_VERSION_MAJOR          24
+#define BM_ICOLL_VERSION_MAJOR          0xff000000
+#define BF_ICOLL_VERSION_MAJOR(v)       (((v) & 0xff) << 24)
+#define BFM_ICOLL_VERSION_MAJOR(v)      BM_ICOLL_VERSION_MAJOR
+#define BF_ICOLL_VERSION_MAJOR_V(e)     BF_ICOLL_VERSION_MAJOR(BV_ICOLL_VERSION_MAJOR__##e)
+#define BFM_ICOLL_VERSION_MAJOR_V(v)    BM_ICOLL_VERSION_MAJOR
+#define BP_ICOLL_VERSION_MINOR          16
+#define BM_ICOLL_VERSION_MINOR          0xff0000
+#define BF_ICOLL_VERSION_MINOR(v)       (((v) & 0xff) << 16)
+#define BFM_ICOLL_VERSION_MINOR(v)      BM_ICOLL_VERSION_MINOR
+#define BF_ICOLL_VERSION_MINOR_V(e)     BF_ICOLL_VERSION_MINOR(BV_ICOLL_VERSION_MINOR__##e)
+#define BFM_ICOLL_VERSION_MINOR_V(v)    BM_ICOLL_VERSION_MINOR
+#define BP_ICOLL_VERSION_STEP           0
+#define BM_ICOLL_VERSION_STEP           0xffff
+#define BF_ICOLL_VERSION_STEP(v)        (((v) & 0xffff) << 0)
+#define BFM_ICOLL_VERSION_STEP(v)       BM_ICOLL_VERSION_STEP
+#define BF_ICOLL_VERSION_STEP_V(e)      BF_ICOLL_VERSION_STEP(BV_ICOLL_VERSION_STEP__##e)
+#define BFM_ICOLL_VERSION_STEP_V(v)     BM_ICOLL_VERSION_STEP
+
+#endif /* __HEADERGEN_IMX233_ICOLL_H__*/
diff --git a/firmware/target/arm/imx233/regs/imx233/ir.h b/firmware/target/arm/imx233/regs/imx233/ir.h
new file mode 100644
index 0000000000..2b89b3b716
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/imx233/ir.h
@@ -0,0 +1,847 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * imx233 version: 2.4.0
+ * imx233 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_IMX233_IR_H__
+#define __HEADERGEN_IMX233_IR_H__
+
+#define HW_IR_CTRL                      HW(IR_CTRL)
+#define HWA_IR_CTRL                     (0x80078000 + 0x0)
+#define HWT_IR_CTRL                     HWIO_32_RW
+#define HWN_IR_CTRL                     IR_CTRL
+#define HWI_IR_CTRL                     
+#define HW_IR_CTRL_SET                  HW(IR_CTRL_SET)
+#define HWA_IR_CTRL_SET                 (HWA_IR_CTRL + 0x4)
+#define HWT_IR_CTRL_SET                 HWIO_32_WO
+#define HWN_IR_CTRL_SET                 IR_CTRL
+#define HWI_IR_CTRL_SET                 
+#define HW_IR_CTRL_CLR                  HW(IR_CTRL_CLR)
+#define HWA_IR_CTRL_CLR                 (HWA_IR_CTRL + 0x8)
+#define HWT_IR_CTRL_CLR                 HWIO_32_WO
+#define HWN_IR_CTRL_CLR                 IR_CTRL
+#define HWI_IR_CTRL_CLR                 
+#define HW_IR_CTRL_TOG                  HW(IR_CTRL_TOG)
+#define HWA_IR_CTRL_TOG                 (HWA_IR_CTRL + 0xc)
+#define HWT_IR_CTRL_TOG                 HWIO_32_WO
+#define HWN_IR_CTRL_TOG                 IR_CTRL
+#define HWI_IR_CTRL_TOG                 
+#define BP_IR_CTRL_SFTRST               31
+#define BM_IR_CTRL_SFTRST               0x80000000
+#define BV_IR_CTRL_SFTRST__RUN          0x0
+#define BV_IR_CTRL_SFTRST__RESET        0x1
+#define BF_IR_CTRL_SFTRST(v)            (((v) & 0x1) << 31)
+#define BFM_IR_CTRL_SFTRST(v)           BM_IR_CTRL_SFTRST
+#define BF_IR_CTRL_SFTRST_V(e)          BF_IR_CTRL_SFTRST(BV_IR_CTRL_SFTRST__##e)
+#define BFM_IR_CTRL_SFTRST_V(v)         BM_IR_CTRL_SFTRST
+#define BP_IR_CTRL_CLKGATE              30
+#define BM_IR_CTRL_CLKGATE              0x40000000
+#define BF_IR_CTRL_CLKGATE(v)           (((v) & 0x1) << 30)
+#define BFM_IR_CTRL_CLKGATE(v)          BM_IR_CTRL_CLKGATE
+#define BF_IR_CTRL_CLKGATE_V(e)         BF_IR_CTRL_CLKGATE(BV_IR_CTRL_CLKGATE__##e)
+#define BFM_IR_CTRL_CLKGATE_V(v)        BM_IR_CTRL_CLKGATE
+#define BP_IR_CTRL_RSVD2                27
+#define BM_IR_CTRL_RSVD2                0x38000000
+#define BF_IR_CTRL_RSVD2(v)             (((v) & 0x7) << 27)
+#define BFM_IR_CTRL_RSVD2(v)            BM_IR_CTRL_RSVD2
+#define BF_IR_CTRL_RSVD2_V(e)           BF_IR_CTRL_RSVD2(BV_IR_CTRL_RSVD2__##e)
+#define BFM_IR_CTRL_RSVD2_V(v)          BM_IR_CTRL_RSVD2
+#define BP_IR_CTRL_MTA                  24
+#define BM_IR_CTRL_MTA                  0x7000000
+#define BV_IR_CTRL_MTA__MTA_10MS        0x0
+#define BV_IR_CTRL_MTA__MTA_5MS         0x1
+#define BV_IR_CTRL_MTA__MTA_1MS         0x2
+#define BV_IR_CTRL_MTA__MTA_500US       0x3
+#define BV_IR_CTRL_MTA__MTA_100US       0x4
+#define BV_IR_CTRL_MTA__MTA_50US        0x5
+#define BV_IR_CTRL_MTA__MTA_10US        0x6
+#define BV_IR_CTRL_MTA__MTA_0           0x7
+#define BF_IR_CTRL_MTA(v)               (((v) & 0x7) << 24)
+#define BFM_IR_CTRL_MTA(v)              BM_IR_CTRL_MTA
+#define BF_IR_CTRL_MTA_V(e)             BF_IR_CTRL_MTA(BV_IR_CTRL_MTA__##e)
+#define BFM_IR_CTRL_MTA_V(v)            BM_IR_CTRL_MTA
+#define BP_IR_CTRL_MODE                 22
+#define BM_IR_CTRL_MODE                 0xc00000
+#define BV_IR_CTRL_MODE__SIR            0x0
+#define BV_IR_CTRL_MODE__MIR            0x1
+#define BV_IR_CTRL_MODE__FIR            0x2
+#define BV_IR_CTRL_MODE__VFIR           0x3
+#define BF_IR_CTRL_MODE(v)              (((v) & 0x3) << 22)
+#define BFM_IR_CTRL_MODE(v)             BM_IR_CTRL_MODE
+#define BF_IR_CTRL_MODE_V(e)            BF_IR_CTRL_MODE(BV_IR_CTRL_MODE__##e)
+#define BFM_IR_CTRL_MODE_V(v)           BM_IR_CTRL_MODE
+#define BP_IR_CTRL_SPEED                19
+#define BM_IR_CTRL_SPEED                0x380000
+#define BV_IR_CTRL_SPEED__SPD000        0x0
+#define BV_IR_CTRL_SPEED__SPD001        0x1
+#define BV_IR_CTRL_SPEED__SPD010        0x2
+#define BV_IR_CTRL_SPEED__SPD011        0x3
+#define BV_IR_CTRL_SPEED__SPD100        0x4
+#define BV_IR_CTRL_SPEED__SPD101        0x5
+#define BF_IR_CTRL_SPEED(v)             (((v) & 0x7) << 19)
+#define BFM_IR_CTRL_SPEED(v)            BM_IR_CTRL_SPEED
+#define BF_IR_CTRL_SPEED_V(e)           BF_IR_CTRL_SPEED(BV_IR_CTRL_SPEED__##e)
+#define BFM_IR_CTRL_SPEED_V(v)          BM_IR_CTRL_SPEED
+#define BP_IR_CTRL_RSVD1                14
+#define BM_IR_CTRL_RSVD1                0x7c000
+#define BF_IR_CTRL_RSVD1(v)             (((v) & 0x1f) << 14)
+#define BFM_IR_CTRL_RSVD1(v)            BM_IR_CTRL_RSVD1
+#define BF_IR_CTRL_RSVD1_V(e)           BF_IR_CTRL_RSVD1(BV_IR_CTRL_RSVD1__##e)
+#define BFM_IR_CTRL_RSVD1_V(v)          BM_IR_CTRL_RSVD1
+#define BP_IR_CTRL_TC_TIME_DIV          8
+#define BM_IR_CTRL_TC_TIME_DIV          0x3f00
+#define BF_IR_CTRL_TC_TIME_DIV(v)       (((v) & 0x3f) << 8)
+#define BFM_IR_CTRL_TC_TIME_DIV(v)      BM_IR_CTRL_TC_TIME_DIV
+#define BF_IR_CTRL_TC_TIME_DIV_V(e)     BF_IR_CTRL_TC_TIME_DIV(BV_IR_CTRL_TC_TIME_DIV__##e)
+#define BFM_IR_CTRL_TC_TIME_DIV_V(v)    BM_IR_CTRL_TC_TIME_DIV
+#define BP_IR_CTRL_TC_TYPE              7
+#define BM_IR_CTRL_TC_TYPE              0x80
+#define BF_IR_CTRL_TC_TYPE(v)           (((v) & 0x1) << 7)
+#define BFM_IR_CTRL_TC_TYPE(v)          BM_IR_CTRL_TC_TYPE
+#define BF_IR_CTRL_TC_TYPE_V(e)         BF_IR_CTRL_TC_TYPE(BV_IR_CTRL_TC_TYPE__##e)
+#define BFM_IR_CTRL_TC_TYPE_V(v)        BM_IR_CTRL_TC_TYPE
+#define BP_IR_CTRL_SIR_GAP              4
+#define BM_IR_CTRL_SIR_GAP              0x70
+#define BV_IR_CTRL_SIR_GAP__GAP_10K     0x0
+#define BV_IR_CTRL_SIR_GAP__GAP_5K      0x1
+#define BV_IR_CTRL_SIR_GAP__GAP_1K      0x2
+#define BV_IR_CTRL_SIR_GAP__GAP_500     0x3
+#define BV_IR_CTRL_SIR_GAP__GAP_100     0x4
+#define BV_IR_CTRL_SIR_GAP__GAP_50      0x5
+#define BV_IR_CTRL_SIR_GAP__GAP_10      0x6
+#define BV_IR_CTRL_SIR_GAP__GAP_0       0x7
+#define BF_IR_CTRL_SIR_GAP(v)           (((v) & 0x7) << 4)
+#define BFM_IR_CTRL_SIR_GAP(v)          BM_IR_CTRL_SIR_GAP
+#define BF_IR_CTRL_SIR_GAP_V(e)         BF_IR_CTRL_SIR_GAP(BV_IR_CTRL_SIR_GAP__##e)
+#define BFM_IR_CTRL_SIR_GAP_V(v)        BM_IR_CTRL_SIR_GAP
+#define BP_IR_CTRL_SIPEN                3
+#define BM_IR_CTRL_SIPEN                0x8
+#define BF_IR_CTRL_SIPEN(v)             (((v) & 0x1) << 3)
+#define BFM_IR_CTRL_SIPEN(v)            BM_IR_CTRL_SIPEN
+#define BF_IR_CTRL_SIPEN_V(e)           BF_IR_CTRL_SIPEN(BV_IR_CTRL_SIPEN__##e)
+#define BFM_IR_CTRL_SIPEN_V(v)          BM_IR_CTRL_SIPEN
+#define BP_IR_CTRL_TCEN                 2
+#define BM_IR_CTRL_TCEN                 0x4
+#define BF_IR_CTRL_TCEN(v)              (((v) & 0x1) << 2)
+#define BFM_IR_CTRL_TCEN(v)             BM_IR_CTRL_TCEN
+#define BF_IR_CTRL_TCEN_V(e)            BF_IR_CTRL_TCEN(BV_IR_CTRL_TCEN__##e)
+#define BFM_IR_CTRL_TCEN_V(v)           BM_IR_CTRL_TCEN
+#define BP_IR_CTRL_TXEN                 1
+#define BM_IR_CTRL_TXEN                 0x2
+#define BF_IR_CTRL_TXEN(v)              (((v) & 0x1) << 1)
+#define BFM_IR_CTRL_TXEN(v)             BM_IR_CTRL_TXEN
+#define BF_IR_CTRL_TXEN_V(e)            BF_IR_CTRL_TXEN(BV_IR_CTRL_TXEN__##e)
+#define BFM_IR_CTRL_TXEN_V(v)           BM_IR_CTRL_TXEN
+#define BP_IR_CTRL_RXEN                 0
+#define BM_IR_CTRL_RXEN                 0x1
+#define BF_IR_CTRL_RXEN(v)              (((v) & 0x1) << 0)
+#define BFM_IR_CTRL_RXEN(v)             BM_IR_CTRL_RXEN
+#define BF_IR_CTRL_RXEN_V(e)            BF_IR_CTRL_RXEN(BV_IR_CTRL_RXEN__##e)
+#define BFM_IR_CTRL_RXEN_V(v)           BM_IR_CTRL_RXEN
+
+#define HW_IR_TXDMA                     HW(IR_TXDMA)
+#define HWA_IR_TXDMA                    (0x80078000 + 0x10)
+#define HWT_IR_TXDMA                    HWIO_32_RW
+#define HWN_IR_TXDMA                    IR_TXDMA
+#define HWI_IR_TXDMA                    
+#define HW_IR_TXDMA_SET                 HW(IR_TXDMA_SET)
+#define HWA_IR_TXDMA_SET                (HWA_IR_TXDMA + 0x4)
+#define HWT_IR_TXDMA_SET                HWIO_32_WO
+#define HWN_IR_TXDMA_SET                IR_TXDMA
+#define HWI_IR_TXDMA_SET                
+#define HW_IR_TXDMA_CLR                 HW(IR_TXDMA_CLR)
+#define HWA_IR_TXDMA_CLR                (HWA_IR_TXDMA + 0x8)
+#define HWT_IR_TXDMA_CLR                HWIO_32_WO
+#define HWN_IR_TXDMA_CLR                IR_TXDMA
+#define HWI_IR_TXDMA_CLR                
+#define HW_IR_TXDMA_TOG                 HW(IR_TXDMA_TOG)
+#define HWA_IR_TXDMA_TOG                (HWA_IR_TXDMA + 0xc)
+#define HWT_IR_TXDMA_TOG                HWIO_32_WO
+#define HWN_IR_TXDMA_TOG                IR_TXDMA
+#define HWI_IR_TXDMA_TOG                
+#define BP_IR_TXDMA_RUN                 31
+#define BM_IR_TXDMA_RUN                 0x80000000
+#define BF_IR_TXDMA_RUN(v)              (((v) & 0x1) << 31)
+#define BFM_IR_TXDMA_RUN(v)             BM_IR_TXDMA_RUN
+#define BF_IR_TXDMA_RUN_V(e)            BF_IR_TXDMA_RUN(BV_IR_TXDMA_RUN__##e)
+#define BFM_IR_TXDMA_RUN_V(v)           BM_IR_TXDMA_RUN
+#define BP_IR_TXDMA_RSVD2               30
+#define BM_IR_TXDMA_RSVD2               0x40000000
+#define BF_IR_TXDMA_RSVD2(v)            (((v) & 0x1) << 30)
+#define BFM_IR_TXDMA_RSVD2(v)           BM_IR_TXDMA_RSVD2
+#define BF_IR_TXDMA_RSVD2_V(e)          BF_IR_TXDMA_RSVD2(BV_IR_TXDMA_RSVD2__##e)
+#define BFM_IR_TXDMA_RSVD2_V(v)         BM_IR_TXDMA_RSVD2
+#define BP_IR_TXDMA_EMPTY               29
+#define BM_IR_TXDMA_EMPTY               0x20000000
+#define BF_IR_TXDMA_EMPTY(v)            (((v) & 0x1) << 29)
+#define BFM_IR_TXDMA_EMPTY(v)           BM_IR_TXDMA_EMPTY
+#define BF_IR_TXDMA_EMPTY_V(e)          BF_IR_TXDMA_EMPTY(BV_IR_TXDMA_EMPTY__##e)
+#define BFM_IR_TXDMA_EMPTY_V(v)         BM_IR_TXDMA_EMPTY
+#define BP_IR_TXDMA_INT                 28
+#define BM_IR_TXDMA_INT                 0x10000000
+#define BF_IR_TXDMA_INT(v)              (((v) & 0x1) << 28)
+#define BFM_IR_TXDMA_INT(v)             BM_IR_TXDMA_INT
+#define BF_IR_TXDMA_INT_V(e)            BF_IR_TXDMA_INT(BV_IR_TXDMA_INT__##e)
+#define BFM_IR_TXDMA_INT_V(v)           BM_IR_TXDMA_INT
+#define BP_IR_TXDMA_CHANGE              27
+#define BM_IR_TXDMA_CHANGE              0x8000000
+#define BF_IR_TXDMA_CHANGE(v)           (((v) & 0x1) << 27)
+#define BFM_IR_TXDMA_CHANGE(v)          BM_IR_TXDMA_CHANGE
+#define BF_IR_TXDMA_CHANGE_V(e)         BF_IR_TXDMA_CHANGE(BV_IR_TXDMA_CHANGE__##e)
+#define BFM_IR_TXDMA_CHANGE_V(v)        BM_IR_TXDMA_CHANGE
+#define BP_IR_TXDMA_NEW_MTA             24
+#define BM_IR_TXDMA_NEW_MTA             0x7000000
+#define BF_IR_TXDMA_NEW_MTA(v)          (((v) & 0x7) << 24)
+#define BFM_IR_TXDMA_NEW_MTA(v)         BM_IR_TXDMA_NEW_MTA
+#define BF_IR_TXDMA_NEW_MTA_V(e)        BF_IR_TXDMA_NEW_MTA(BV_IR_TXDMA_NEW_MTA__##e)
+#define BFM_IR_TXDMA_NEW_MTA_V(v)       BM_IR_TXDMA_NEW_MTA
+#define BP_IR_TXDMA_NEW_MODE            22
+#define BM_IR_TXDMA_NEW_MODE            0xc00000
+#define BF_IR_TXDMA_NEW_MODE(v)         (((v) & 0x3) << 22)
+#define BFM_IR_TXDMA_NEW_MODE(v)        BM_IR_TXDMA_NEW_MODE
+#define BF_IR_TXDMA_NEW_MODE_V(e)       BF_IR_TXDMA_NEW_MODE(BV_IR_TXDMA_NEW_MODE__##e)
+#define BFM_IR_TXDMA_NEW_MODE_V(v)      BM_IR_TXDMA_NEW_MODE
+#define BP_IR_TXDMA_NEW_SPEED           19
+#define BM_IR_TXDMA_NEW_SPEED           0x380000
+#define BF_IR_TXDMA_NEW_SPEED(v)        (((v) & 0x7) << 19)
+#define BFM_IR_TXDMA_NEW_SPEED(v)       BM_IR_TXDMA_NEW_SPEED
+#define BF_IR_TXDMA_NEW_SPEED_V(e)      BF_IR_TXDMA_NEW_SPEED(BV_IR_TXDMA_NEW_SPEED__##e)
+#define BFM_IR_TXDMA_NEW_SPEED_V(v)     BM_IR_TXDMA_NEW_SPEED
+#define BP_IR_TXDMA_BOF_TYPE            18
+#define BM_IR_TXDMA_BOF_TYPE            0x40000
+#define BF_IR_TXDMA_BOF_TYPE(v)         (((v) & 0x1) << 18)
+#define BFM_IR_TXDMA_BOF_TYPE(v)        BM_IR_TXDMA_BOF_TYPE
+#define BF_IR_TXDMA_BOF_TYPE_V(e)       BF_IR_TXDMA_BOF_TYPE(BV_IR_TXDMA_BOF_TYPE__##e)
+#define BFM_IR_TXDMA_BOF_TYPE_V(v)      BM_IR_TXDMA_BOF_TYPE
+#define BP_IR_TXDMA_XBOFS               12
+#define BM_IR_TXDMA_XBOFS               0x3f000
+#define BF_IR_TXDMA_XBOFS(v)            (((v) & 0x3f) << 12)
+#define BFM_IR_TXDMA_XBOFS(v)           BM_IR_TXDMA_XBOFS
+#define BF_IR_TXDMA_XBOFS_V(e)          BF_IR_TXDMA_XBOFS(BV_IR_TXDMA_XBOFS__##e)
+#define BFM_IR_TXDMA_XBOFS_V(v)         BM_IR_TXDMA_XBOFS
+#define BP_IR_TXDMA_XFER_COUNT          0
+#define BM_IR_TXDMA_XFER_COUNT          0xfff
+#define BF_IR_TXDMA_XFER_COUNT(v)       (((v) & 0xfff) << 0)
+#define BFM_IR_TXDMA_XFER_COUNT(v)      BM_IR_TXDMA_XFER_COUNT
+#define BF_IR_TXDMA_XFER_COUNT_V(e)     BF_IR_TXDMA_XFER_COUNT(BV_IR_TXDMA_XFER_COUNT__##e)
+#define BFM_IR_TXDMA_XFER_COUNT_V(v)    BM_IR_TXDMA_XFER_COUNT
+
+#define HW_IR_RXDMA                     HW(IR_RXDMA)
+#define HWA_IR_RXDMA                    (0x80078000 + 0x20)
+#define HWT_IR_RXDMA                    HWIO_32_RW
+#define HWN_IR_RXDMA                    IR_RXDMA
+#define HWI_IR_RXDMA                    
+#define HW_IR_RXDMA_SET                 HW(IR_RXDMA_SET)
+#define HWA_IR_RXDMA_SET                (HWA_IR_RXDMA + 0x4)
+#define HWT_IR_RXDMA_SET                HWIO_32_WO
+#define HWN_IR_RXDMA_SET                IR_RXDMA
+#define HWI_IR_RXDMA_SET                
+#define HW_IR_RXDMA_CLR                 HW(IR_RXDMA_CLR)
+#define HWA_IR_RXDMA_CLR                (HWA_IR_RXDMA + 0x8)
+#define HWT_IR_RXDMA_CLR                HWIO_32_WO
+#define HWN_IR_RXDMA_CLR                IR_RXDMA
+#define HWI_IR_RXDMA_CLR                
+#define HW_IR_RXDMA_TOG                 HW(IR_RXDMA_TOG)
+#define HWA_IR_RXDMA_TOG                (HWA_IR_RXDMA + 0xc)
+#define HWT_IR_RXDMA_TOG                HWIO_32_WO
+#define HWN_IR_RXDMA_TOG                IR_RXDMA
+#define HWI_IR_RXDMA_TOG                
+#define BP_IR_RXDMA_RUN                 31
+#define BM_IR_RXDMA_RUN                 0x80000000
+#define BF_IR_RXDMA_RUN(v)              (((v) & 0x1) << 31)
+#define BFM_IR_RXDMA_RUN(v)             BM_IR_RXDMA_RUN
+#define BF_IR_RXDMA_RUN_V(e)            BF_IR_RXDMA_RUN(BV_IR_RXDMA_RUN__##e)
+#define BFM_IR_RXDMA_RUN_V(v)           BM_IR_RXDMA_RUN
+#define BP_IR_RXDMA_RSVD                10
+#define BM_IR_RXDMA_RSVD                0x7ffffc00
+#define BF_IR_RXDMA_RSVD(v)             (((v) & 0x1fffff) << 10)
+#define BFM_IR_RXDMA_RSVD(v)            BM_IR_RXDMA_RSVD
+#define BF_IR_RXDMA_RSVD_V(e)           BF_IR_RXDMA_RSVD(BV_IR_RXDMA_RSVD__##e)
+#define BFM_IR_RXDMA_RSVD_V(v)          BM_IR_RXDMA_RSVD
+#define BP_IR_RXDMA_XFER_COUNT          0
+#define BM_IR_RXDMA_XFER_COUNT          0x3ff
+#define BF_IR_RXDMA_XFER_COUNT(v)       (((v) & 0x3ff) << 0)
+#define BFM_IR_RXDMA_XFER_COUNT(v)      BM_IR_RXDMA_XFER_COUNT
+#define BF_IR_RXDMA_XFER_COUNT_V(e)     BF_IR_RXDMA_XFER_COUNT(BV_IR_RXDMA_XFER_COUNT__##e)
+#define BFM_IR_RXDMA_XFER_COUNT_V(v)    BM_IR_RXDMA_XFER_COUNT
+
+#define HW_IR_DBGCTRL                   HW(IR_DBGCTRL)
+#define HWA_IR_DBGCTRL                  (0x80078000 + 0x30)
+#define HWT_IR_DBGCTRL                  HWIO_32_RW
+#define HWN_IR_DBGCTRL                  IR_DBGCTRL
+#define HWI_IR_DBGCTRL                  
+#define HW_IR_DBGCTRL_SET               HW(IR_DBGCTRL_SET)
+#define HWA_IR_DBGCTRL_SET              (HWA_IR_DBGCTRL + 0x4)
+#define HWT_IR_DBGCTRL_SET              HWIO_32_WO
+#define HWN_IR_DBGCTRL_SET              IR_DBGCTRL
+#define HWI_IR_DBGCTRL_SET              
+#define HW_IR_DBGCTRL_CLR               HW(IR_DBGCTRL_CLR)
+#define HWA_IR_DBGCTRL_CLR              (HWA_IR_DBGCTRL + 0x8)
+#define HWT_IR_DBGCTRL_CLR              HWIO_32_WO
+#define HWN_IR_DBGCTRL_CLR              IR_DBGCTRL
+#define HWI_IR_DBGCTRL_CLR              
+#define HW_IR_DBGCTRL_TOG               HW(IR_DBGCTRL_TOG)
+#define HWA_IR_DBGCTRL_TOG              (HWA_IR_DBGCTRL + 0xc)
+#define HWT_IR_DBGCTRL_TOG              HWIO_32_WO
+#define HWN_IR_DBGCTRL_TOG              IR_DBGCTRL
+#define HWI_IR_DBGCTRL_TOG              
+#define BP_IR_DBGCTRL_RSVD2             13
+#define BM_IR_DBGCTRL_RSVD2             0xffffe000
+#define BF_IR_DBGCTRL_RSVD2(v)          (((v) & 0x7ffff) << 13)
+#define BFM_IR_DBGCTRL_RSVD2(v)         BM_IR_DBGCTRL_RSVD2
+#define BF_IR_DBGCTRL_RSVD2_V(e)        BF_IR_DBGCTRL_RSVD2(BV_IR_DBGCTRL_RSVD2__##e)
+#define BFM_IR_DBGCTRL_RSVD2_V(v)       BM_IR_DBGCTRL_RSVD2
+#define BP_IR_DBGCTRL_VFIRSWZ           12
+#define BM_IR_DBGCTRL_VFIRSWZ           0x1000
+#define BV_IR_DBGCTRL_VFIRSWZ__NORMAL   0x0
+#define BV_IR_DBGCTRL_VFIRSWZ__SWAP     0x1
+#define BF_IR_DBGCTRL_VFIRSWZ(v)        (((v) & 0x1) << 12)
+#define BFM_IR_DBGCTRL_VFIRSWZ(v)       BM_IR_DBGCTRL_VFIRSWZ
+#define BF_IR_DBGCTRL_VFIRSWZ_V(e)      BF_IR_DBGCTRL_VFIRSWZ(BV_IR_DBGCTRL_VFIRSWZ__##e)
+#define BFM_IR_DBGCTRL_VFIRSWZ_V(v)     BM_IR_DBGCTRL_VFIRSWZ
+#define BP_IR_DBGCTRL_RXFRMOFF          11
+#define BM_IR_DBGCTRL_RXFRMOFF          0x800
+#define BF_IR_DBGCTRL_RXFRMOFF(v)       (((v) & 0x1) << 11)
+#define BFM_IR_DBGCTRL_RXFRMOFF(v)      BM_IR_DBGCTRL_RXFRMOFF
+#define BF_IR_DBGCTRL_RXFRMOFF_V(e)     BF_IR_DBGCTRL_RXFRMOFF(BV_IR_DBGCTRL_RXFRMOFF__##e)
+#define BFM_IR_DBGCTRL_RXFRMOFF_V(v)    BM_IR_DBGCTRL_RXFRMOFF
+#define BP_IR_DBGCTRL_RXCRCOFF          10
+#define BM_IR_DBGCTRL_RXCRCOFF          0x400
+#define BF_IR_DBGCTRL_RXCRCOFF(v)       (((v) & 0x1) << 10)
+#define BFM_IR_DBGCTRL_RXCRCOFF(v)      BM_IR_DBGCTRL_RXCRCOFF
+#define BF_IR_DBGCTRL_RXCRCOFF_V(e)     BF_IR_DBGCTRL_RXCRCOFF(BV_IR_DBGCTRL_RXCRCOFF__##e)
+#define BFM_IR_DBGCTRL_RXCRCOFF_V(v)    BM_IR_DBGCTRL_RXCRCOFF
+#define BP_IR_DBGCTRL_RXINVERT          9
+#define BM_IR_DBGCTRL_RXINVERT          0x200
+#define BF_IR_DBGCTRL_RXINVERT(v)       (((v) & 0x1) << 9)
+#define BFM_IR_DBGCTRL_RXINVERT(v)      BM_IR_DBGCTRL_RXINVERT
+#define BF_IR_DBGCTRL_RXINVERT_V(e)     BF_IR_DBGCTRL_RXINVERT(BV_IR_DBGCTRL_RXINVERT__##e)
+#define BFM_IR_DBGCTRL_RXINVERT_V(v)    BM_IR_DBGCTRL_RXINVERT
+#define BP_IR_DBGCTRL_TXFRMOFF          8
+#define BM_IR_DBGCTRL_TXFRMOFF          0x100
+#define BF_IR_DBGCTRL_TXFRMOFF(v)       (((v) & 0x1) << 8)
+#define BFM_IR_DBGCTRL_TXFRMOFF(v)      BM_IR_DBGCTRL_TXFRMOFF
+#define BF_IR_DBGCTRL_TXFRMOFF_V(e)     BF_IR_DBGCTRL_TXFRMOFF(BV_IR_DBGCTRL_TXFRMOFF__##e)
+#define BFM_IR_DBGCTRL_TXFRMOFF_V(v)    BM_IR_DBGCTRL_TXFRMOFF
+#define BP_IR_DBGCTRL_TXCRCOFF          7
+#define BM_IR_DBGCTRL_TXCRCOFF          0x80
+#define BF_IR_DBGCTRL_TXCRCOFF(v)       (((v) & 0x1) << 7)
+#define BFM_IR_DBGCTRL_TXCRCOFF(v)      BM_IR_DBGCTRL_TXCRCOFF
+#define BF_IR_DBGCTRL_TXCRCOFF_V(e)     BF_IR_DBGCTRL_TXCRCOFF(BV_IR_DBGCTRL_TXCRCOFF__##e)
+#define BFM_IR_DBGCTRL_TXCRCOFF_V(v)    BM_IR_DBGCTRL_TXCRCOFF
+#define BP_IR_DBGCTRL_TXINVERT          6
+#define BM_IR_DBGCTRL_TXINVERT          0x40
+#define BF_IR_DBGCTRL_TXINVERT(v)       (((v) & 0x1) << 6)
+#define BFM_IR_DBGCTRL_TXINVERT(v)      BM_IR_DBGCTRL_TXINVERT
+#define BF_IR_DBGCTRL_TXINVERT_V(e)     BF_IR_DBGCTRL_TXINVERT(BV_IR_DBGCTRL_TXINVERT__##e)
+#define BFM_IR_DBGCTRL_TXINVERT_V(v)    BM_IR_DBGCTRL_TXINVERT
+#define BP_IR_DBGCTRL_INTLOOPBACK       5
+#define BM_IR_DBGCTRL_INTLOOPBACK       0x20
+#define BF_IR_DBGCTRL_INTLOOPBACK(v)    (((v) & 0x1) << 5)
+#define BFM_IR_DBGCTRL_INTLOOPBACK(v)   BM_IR_DBGCTRL_INTLOOPBACK
+#define BF_IR_DBGCTRL_INTLOOPBACK_V(e)  BF_IR_DBGCTRL_INTLOOPBACK(BV_IR_DBGCTRL_INTLOOPBACK__##e)
+#define BFM_IR_DBGCTRL_INTLOOPBACK_V(v) BM_IR_DBGCTRL_INTLOOPBACK
+#define BP_IR_DBGCTRL_DUPLEX            4
+#define BM_IR_DBGCTRL_DUPLEX            0x10
+#define BF_IR_DBGCTRL_DUPLEX(v)         (((v) & 0x1) << 4)
+#define BFM_IR_DBGCTRL_DUPLEX(v)        BM_IR_DBGCTRL_DUPLEX
+#define BF_IR_DBGCTRL_DUPLEX_V(e)       BF_IR_DBGCTRL_DUPLEX(BV_IR_DBGCTRL_DUPLEX__##e)
+#define BFM_IR_DBGCTRL_DUPLEX_V(v)      BM_IR_DBGCTRL_DUPLEX
+#define BP_IR_DBGCTRL_MIO_RX            3
+#define BM_IR_DBGCTRL_MIO_RX            0x8
+#define BF_IR_DBGCTRL_MIO_RX(v)         (((v) & 0x1) << 3)
+#define BFM_IR_DBGCTRL_MIO_RX(v)        BM_IR_DBGCTRL_MIO_RX
+#define BF_IR_DBGCTRL_MIO_RX_V(e)       BF_IR_DBGCTRL_MIO_RX(BV_IR_DBGCTRL_MIO_RX__##e)
+#define BFM_IR_DBGCTRL_MIO_RX_V(v)      BM_IR_DBGCTRL_MIO_RX
+#define BP_IR_DBGCTRL_MIO_TX            2
+#define BM_IR_DBGCTRL_MIO_TX            0x4
+#define BF_IR_DBGCTRL_MIO_TX(v)         (((v) & 0x1) << 2)
+#define BFM_IR_DBGCTRL_MIO_TX(v)        BM_IR_DBGCTRL_MIO_TX
+#define BF_IR_DBGCTRL_MIO_TX_V(e)       BF_IR_DBGCTRL_MIO_TX(BV_IR_DBGCTRL_MIO_TX__##e)
+#define BFM_IR_DBGCTRL_MIO_TX_V(v)      BM_IR_DBGCTRL_MIO_TX
+#define BP_IR_DBGCTRL_MIO_SCLK          1
+#define BM_IR_DBGCTRL_MIO_SCLK          0x2
+#define BF_IR_DBGCTRL_MIO_SCLK(v)       (((v) & 0x1) << 1)
+#define BFM_IR_DBGCTRL_MIO_SCLK(v)      BM_IR_DBGCTRL_MIO_SCLK
+#define BF_IR_DBGCTRL_MIO_SCLK_V(e)     BF_IR_DBGCTRL_MIO_SCLK(BV_IR_DBGCTRL_MIO_SCLK__##e)
+#define BFM_IR_DBGCTRL_MIO_SCLK_V(v)    BM_IR_DBGCTRL_MIO_SCLK
+#define BP_IR_DBGCTRL_MIO_EN            0
+#define BM_IR_DBGCTRL_MIO_EN            0x1
+#define BF_IR_DBGCTRL_MIO_EN(v)         (((v) & 0x1) << 0)
+#define BFM_IR_DBGCTRL_MIO_EN(v)        BM_IR_DBGCTRL_MIO_EN
+#define BF_IR_DBGCTRL_MIO_EN_V(e)       BF_IR_DBGCTRL_MIO_EN(BV_IR_DBGCTRL_MIO_EN__##e)
+#define BFM_IR_DBGCTRL_MIO_EN_V(v)      BM_IR_DBGCTRL_MIO_EN
+
+#define HW_IR_INTR                          HW(IR_INTR)
+#define HWA_IR_INTR                         (0x80078000 + 0x40)
+#define HWT_IR_INTR                         HWIO_32_RW
+#define HWN_IR_INTR                         IR_INTR
+#define HWI_IR_INTR                         
+#define HW_IR_INTR_SET                      HW(IR_INTR_SET)
+#define HWA_IR_INTR_SET                     (HWA_IR_INTR + 0x4)
+#define HWT_IR_INTR_SET                     HWIO_32_WO
+#define HWN_IR_INTR_SET                     IR_INTR
+#define HWI_IR_INTR_SET                     
+#define HW_IR_INTR_CLR                      HW(IR_INTR_CLR)
+#define HWA_IR_INTR_CLR                     (HWA_IR_INTR + 0x8)
+#define HWT_IR_INTR_CLR                     HWIO_32_WO
+#define HWN_IR_INTR_CLR                     IR_INTR
+#define HWI_IR_INTR_CLR                     
+#define HW_IR_INTR_TOG                      HW(IR_INTR_TOG)
+#define HWA_IR_INTR_TOG                     (HWA_IR_INTR + 0xc)
+#define HWT_IR_INTR_TOG                     HWIO_32_WO
+#define HWN_IR_INTR_TOG                     IR_INTR
+#define HWI_IR_INTR_TOG                     
+#define BP_IR_INTR_RSVD2                    23
+#define BM_IR_INTR_RSVD2                    0xff800000
+#define BF_IR_INTR_RSVD2(v)                 (((v) & 0x1ff) << 23)
+#define BFM_IR_INTR_RSVD2(v)                BM_IR_INTR_RSVD2
+#define BF_IR_INTR_RSVD2_V(e)               BF_IR_INTR_RSVD2(BV_IR_INTR_RSVD2__##e)
+#define BFM_IR_INTR_RSVD2_V(v)              BM_IR_INTR_RSVD2
+#define BP_IR_INTR_RXABORT_IRQ_EN           22
+#define BM_IR_INTR_RXABORT_IRQ_EN           0x400000
+#define BV_IR_INTR_RXABORT_IRQ_EN__DISABLED 0x0
+#define BV_IR_INTR_RXABORT_IRQ_EN__ENABLED  0x1
+#define BF_IR_INTR_RXABORT_IRQ_EN(v)        (((v) & 0x1) << 22)
+#define BFM_IR_INTR_RXABORT_IRQ_EN(v)       BM_IR_INTR_RXABORT_IRQ_EN
+#define BF_IR_INTR_RXABORT_IRQ_EN_V(e)      BF_IR_INTR_RXABORT_IRQ_EN(BV_IR_INTR_RXABORT_IRQ_EN__##e)
+#define BFM_IR_INTR_RXABORT_IRQ_EN_V(v)     BM_IR_INTR_RXABORT_IRQ_EN
+#define BP_IR_INTR_SPEED_IRQ_EN             21
+#define BM_IR_INTR_SPEED_IRQ_EN             0x200000
+#define BV_IR_INTR_SPEED_IRQ_EN__DISABLED   0x0
+#define BV_IR_INTR_SPEED_IRQ_EN__ENABLED    0x1
+#define BF_IR_INTR_SPEED_IRQ_EN(v)          (((v) & 0x1) << 21)
+#define BFM_IR_INTR_SPEED_IRQ_EN(v)         BM_IR_INTR_SPEED_IRQ_EN
+#define BF_IR_INTR_SPEED_IRQ_EN_V(e)        BF_IR_INTR_SPEED_IRQ_EN(BV_IR_INTR_SPEED_IRQ_EN__##e)
+#define BFM_IR_INTR_SPEED_IRQ_EN_V(v)       BM_IR_INTR_SPEED_IRQ_EN
+#define BP_IR_INTR_RXOF_IRQ_EN              20
+#define BM_IR_INTR_RXOF_IRQ_EN              0x100000
+#define BV_IR_INTR_RXOF_IRQ_EN__DISABLED    0x0
+#define BV_IR_INTR_RXOF_IRQ_EN__ENABLED     0x1
+#define BF_IR_INTR_RXOF_IRQ_EN(v)           (((v) & 0x1) << 20)
+#define BFM_IR_INTR_RXOF_IRQ_EN(v)          BM_IR_INTR_RXOF_IRQ_EN
+#define BF_IR_INTR_RXOF_IRQ_EN_V(e)         BF_IR_INTR_RXOF_IRQ_EN(BV_IR_INTR_RXOF_IRQ_EN__##e)
+#define BFM_IR_INTR_RXOF_IRQ_EN_V(v)        BM_IR_INTR_RXOF_IRQ_EN
+#define BP_IR_INTR_TXUF_IRQ_EN              19
+#define BM_IR_INTR_TXUF_IRQ_EN              0x80000
+#define BV_IR_INTR_TXUF_IRQ_EN__DISABLED    0x0
+#define BV_IR_INTR_TXUF_IRQ_EN__ENABLED     0x1
+#define BF_IR_INTR_TXUF_IRQ_EN(v)           (((v) & 0x1) << 19)
+#define BFM_IR_INTR_TXUF_IRQ_EN(v)          BM_IR_INTR_TXUF_IRQ_EN
+#define BF_IR_INTR_TXUF_IRQ_EN_V(e)         BF_IR_INTR_TXUF_IRQ_EN(BV_IR_INTR_TXUF_IRQ_EN__##e)
+#define BFM_IR_INTR_TXUF_IRQ_EN_V(v)        BM_IR_INTR_TXUF_IRQ_EN
+#define BP_IR_INTR_TC_IRQ_EN                18
+#define BM_IR_INTR_TC_IRQ_EN                0x40000
+#define BV_IR_INTR_TC_IRQ_EN__DISABLED      0x0
+#define BV_IR_INTR_TC_IRQ_EN__ENABLED       0x1
+#define BF_IR_INTR_TC_IRQ_EN(v)             (((v) & 0x1) << 18)
+#define BFM_IR_INTR_TC_IRQ_EN(v)            BM_IR_INTR_TC_IRQ_EN
+#define BF_IR_INTR_TC_IRQ_EN_V(e)           BF_IR_INTR_TC_IRQ_EN(BV_IR_INTR_TC_IRQ_EN__##e)
+#define BFM_IR_INTR_TC_IRQ_EN_V(v)          BM_IR_INTR_TC_IRQ_EN
+#define BP_IR_INTR_RX_IRQ_EN                17
+#define BM_IR_INTR_RX_IRQ_EN                0x20000
+#define BV_IR_INTR_RX_IRQ_EN__DISABLED      0x0
+#define BV_IR_INTR_RX_IRQ_EN__ENABLED       0x1
+#define BF_IR_INTR_RX_IRQ_EN(v)             (((v) & 0x1) << 17)
+#define BFM_IR_INTR_RX_IRQ_EN(v)            BM_IR_INTR_RX_IRQ_EN
+#define BF_IR_INTR_RX_IRQ_EN_V(e)           BF_IR_INTR_RX_IRQ_EN(BV_IR_INTR_RX_IRQ_EN__##e)
+#define BFM_IR_INTR_RX_IRQ_EN_V(v)          BM_IR_INTR_RX_IRQ_EN
+#define BP_IR_INTR_TX_IRQ_EN                16
+#define BM_IR_INTR_TX_IRQ_EN                0x10000
+#define BV_IR_INTR_TX_IRQ_EN__DISABLED      0x0
+#define BV_IR_INTR_TX_IRQ_EN__ENABLED       0x1
+#define BF_IR_INTR_TX_IRQ_EN(v)             (((v) & 0x1) << 16)
+#define BFM_IR_INTR_TX_IRQ_EN(v)            BM_IR_INTR_TX_IRQ_EN
+#define BF_IR_INTR_TX_IRQ_EN_V(e)           BF_IR_INTR_TX_IRQ_EN(BV_IR_INTR_TX_IRQ_EN__##e)
+#define BFM_IR_INTR_TX_IRQ_EN_V(v)          BM_IR_INTR_TX_IRQ_EN
+#define BP_IR_INTR_RSVD1                    7
+#define BM_IR_INTR_RSVD1                    0xff80
+#define BF_IR_INTR_RSVD1(v)                 (((v) & 0x1ff) << 7)
+#define BFM_IR_INTR_RSVD1(v)                BM_IR_INTR_RSVD1
+#define BF_IR_INTR_RSVD1_V(e)               BF_IR_INTR_RSVD1(BV_IR_INTR_RSVD1__##e)
+#define BFM_IR_INTR_RSVD1_V(v)              BM_IR_INTR_RSVD1
+#define BP_IR_INTR_RXABORT_IRQ              6
+#define BM_IR_INTR_RXABORT_IRQ              0x40
+#define BV_IR_INTR_RXABORT_IRQ__NO_REQUEST  0x0
+#define BV_IR_INTR_RXABORT_IRQ__REQUEST     0x1
+#define BF_IR_INTR_RXABORT_IRQ(v)           (((v) & 0x1) << 6)
+#define BFM_IR_INTR_RXABORT_IRQ(v)          BM_IR_INTR_RXABORT_IRQ
+#define BF_IR_INTR_RXABORT_IRQ_V(e)         BF_IR_INTR_RXABORT_IRQ(BV_IR_INTR_RXABORT_IRQ__##e)
+#define BFM_IR_INTR_RXABORT_IRQ_V(v)        BM_IR_INTR_RXABORT_IRQ
+#define BP_IR_INTR_SPEED_IRQ                5
+#define BM_IR_INTR_SPEED_IRQ                0x20
+#define BV_IR_INTR_SPEED_IRQ__NO_REQUEST    0x0
+#define BV_IR_INTR_SPEED_IRQ__REQUEST       0x1
+#define BF_IR_INTR_SPEED_IRQ(v)             (((v) & 0x1) << 5)
+#define BFM_IR_INTR_SPEED_IRQ(v)            BM_IR_INTR_SPEED_IRQ
+#define BF_IR_INTR_SPEED_IRQ_V(e)           BF_IR_INTR_SPEED_IRQ(BV_IR_INTR_SPEED_IRQ__##e)
+#define BFM_IR_INTR_SPEED_IRQ_V(v)          BM_IR_INTR_SPEED_IRQ
+#define BP_IR_INTR_RXOF_IRQ                 4
+#define BM_IR_INTR_RXOF_IRQ                 0x10
+#define BV_IR_INTR_RXOF_IRQ__NO_REQUEST     0x0
+#define BV_IR_INTR_RXOF_IRQ__REQUEST        0x1
+#define BF_IR_INTR_RXOF_IRQ(v)              (((v) & 0x1) << 4)
+#define BFM_IR_INTR_RXOF_IRQ(v)             BM_IR_INTR_RXOF_IRQ
+#define BF_IR_INTR_RXOF_IRQ_V(e)            BF_IR_INTR_RXOF_IRQ(BV_IR_INTR_RXOF_IRQ__##e)
+#define BFM_IR_INTR_RXOF_IRQ_V(v)           BM_IR_INTR_RXOF_IRQ
+#define BP_IR_INTR_TXUF_IRQ                 3
+#define BM_IR_INTR_TXUF_IRQ                 0x8
+#define BV_IR_INTR_TXUF_IRQ__NO_REQUEST     0x0
+#define BV_IR_INTR_TXUF_IRQ__REQUEST        0x1
+#define BF_IR_INTR_TXUF_IRQ(v)              (((v) & 0x1) << 3)
+#define BFM_IR_INTR_TXUF_IRQ(v)             BM_IR_INTR_TXUF_IRQ
+#define BF_IR_INTR_TXUF_IRQ_V(e)            BF_IR_INTR_TXUF_IRQ(BV_IR_INTR_TXUF_IRQ__##e)
+#define BFM_IR_INTR_TXUF_IRQ_V(v)           BM_IR_INTR_TXUF_IRQ
+#define BP_IR_INTR_TC_IRQ                   2
+#define BM_IR_INTR_TC_IRQ                   0x4
+#define BV_IR_INTR_TC_IRQ__NO_REQUEST       0x0
+#define BV_IR_INTR_TC_IRQ__REQUEST          0x1
+#define BF_IR_INTR_TC_IRQ(v)                (((v) & 0x1) << 2)
+#define BFM_IR_INTR_TC_IRQ(v)               BM_IR_INTR_TC_IRQ
+#define BF_IR_INTR_TC_IRQ_V(e)              BF_IR_INTR_TC_IRQ(BV_IR_INTR_TC_IRQ__##e)
+#define BFM_IR_INTR_TC_IRQ_V(v)             BM_IR_INTR_TC_IRQ
+#define BP_IR_INTR_RX_IRQ                   1
+#define BM_IR_INTR_RX_IRQ                   0x2
+#define BV_IR_INTR_RX_IRQ__NO_REQUEST       0x0
+#define BV_IR_INTR_RX_IRQ__REQUEST          0x1
+#define BF_IR_INTR_RX_IRQ(v)                (((v) & 0x1) << 1)
+#define BFM_IR_INTR_RX_IRQ(v)               BM_IR_INTR_RX_IRQ
+#define BF_IR_INTR_RX_IRQ_V(e)              BF_IR_INTR_RX_IRQ(BV_IR_INTR_RX_IRQ__##e)
+#define BFM_IR_INTR_RX_IRQ_V(v)             BM_IR_INTR_RX_IRQ
+#define BP_IR_INTR_TX_IRQ                   0
+#define BM_IR_INTR_TX_IRQ                   0x1
+#define BV_IR_INTR_TX_IRQ__NO_REQUEST       0x0
+#define BV_IR_INTR_TX_IRQ__REQUEST          0x1
+#define BF_IR_INTR_TX_IRQ(v)                (((v) & 0x1) << 0)
+#define BFM_IR_INTR_TX_IRQ(v)               BM_IR_INTR_TX_IRQ
+#define BF_IR_INTR_TX_IRQ_V(e)              BF_IR_INTR_TX_IRQ(BV_IR_INTR_TX_IRQ__##e)
+#define BFM_IR_INTR_TX_IRQ_V(v)             BM_IR_INTR_TX_IRQ
+
+#define HW_IR_DATA              HW(IR_DATA)
+#define HWA_IR_DATA             (0x80078000 + 0x50)
+#define HWT_IR_DATA             HWIO_32_RW
+#define HWN_IR_DATA             IR_DATA
+#define HWI_IR_DATA             
+#define BP_IR_DATA_DATA         0
+#define BM_IR_DATA_DATA         0xffffffff
+#define BF_IR_DATA_DATA(v)      (((v) & 0xffffffff) << 0)
+#define BFM_IR_DATA_DATA(v)     BM_IR_DATA_DATA
+#define BF_IR_DATA_DATA_V(e)    BF_IR_DATA_DATA(BV_IR_DATA_DATA__##e)
+#define BFM_IR_DATA_DATA_V(v)   BM_IR_DATA_DATA
+
+#define HW_IR_STAT                              HW(IR_STAT)
+#define HWA_IR_STAT                             (0x80078000 + 0x60)
+#define HWT_IR_STAT                             HWIO_32_RW
+#define HWN_IR_STAT                             IR_STAT
+#define HWI_IR_STAT                             
+#define BP_IR_STAT_PRESENT                      31
+#define BM_IR_STAT_PRESENT                      0x80000000
+#define BV_IR_STAT_PRESENT__UNAVAILABLE         0x0
+#define BV_IR_STAT_PRESENT__AVAILABLE           0x1
+#define BF_IR_STAT_PRESENT(v)                   (((v) & 0x1) << 31)
+#define BFM_IR_STAT_PRESENT(v)                  BM_IR_STAT_PRESENT
+#define BF_IR_STAT_PRESENT_V(e)                 BF_IR_STAT_PRESENT(BV_IR_STAT_PRESENT__##e)
+#define BFM_IR_STAT_PRESENT_V(v)                BM_IR_STAT_PRESENT
+#define BP_IR_STAT_MODE_ALLOWED                 29
+#define BM_IR_STAT_MODE_ALLOWED                 0x60000000
+#define BV_IR_STAT_MODE_ALLOWED__VFIR           0x0
+#define BV_IR_STAT_MODE_ALLOWED__FIR            0x1
+#define BV_IR_STAT_MODE_ALLOWED__MIR            0x2
+#define BV_IR_STAT_MODE_ALLOWED__SIR            0x3
+#define BF_IR_STAT_MODE_ALLOWED(v)              (((v) & 0x3) << 29)
+#define BFM_IR_STAT_MODE_ALLOWED(v)             BM_IR_STAT_MODE_ALLOWED
+#define BF_IR_STAT_MODE_ALLOWED_V(e)            BF_IR_STAT_MODE_ALLOWED(BV_IR_STAT_MODE_ALLOWED__##e)
+#define BFM_IR_STAT_MODE_ALLOWED_V(v)           BM_IR_STAT_MODE_ALLOWED
+#define BP_IR_STAT_ANY_IRQ                      28
+#define BM_IR_STAT_ANY_IRQ                      0x10000000
+#define BV_IR_STAT_ANY_IRQ__NO_REQUEST          0x0
+#define BV_IR_STAT_ANY_IRQ__REQUEST             0x1
+#define BF_IR_STAT_ANY_IRQ(v)                   (((v) & 0x1) << 28)
+#define BFM_IR_STAT_ANY_IRQ(v)                  BM_IR_STAT_ANY_IRQ
+#define BF_IR_STAT_ANY_IRQ_V(e)                 BF_IR_STAT_ANY_IRQ(BV_IR_STAT_ANY_IRQ__##e)
+#define BFM_IR_STAT_ANY_IRQ_V(v)                BM_IR_STAT_ANY_IRQ
+#define BP_IR_STAT_RSVD2                        23
+#define BM_IR_STAT_RSVD2                        0xf800000
+#define BF_IR_STAT_RSVD2(v)                     (((v) & 0x1f) << 23)
+#define BFM_IR_STAT_RSVD2(v)                    BM_IR_STAT_RSVD2
+#define BF_IR_STAT_RSVD2_V(e)                   BF_IR_STAT_RSVD2(BV_IR_STAT_RSVD2__##e)
+#define BFM_IR_STAT_RSVD2_V(v)                  BM_IR_STAT_RSVD2
+#define BP_IR_STAT_RXABORT_SUMMARY              22
+#define BM_IR_STAT_RXABORT_SUMMARY              0x400000
+#define BV_IR_STAT_RXABORT_SUMMARY__NO_REQUEST  0x0
+#define BV_IR_STAT_RXABORT_SUMMARY__REQUEST     0x1
+#define BF_IR_STAT_RXABORT_SUMMARY(v)           (((v) & 0x1) << 22)
+#define BFM_IR_STAT_RXABORT_SUMMARY(v)          BM_IR_STAT_RXABORT_SUMMARY
+#define BF_IR_STAT_RXABORT_SUMMARY_V(e)         BF_IR_STAT_RXABORT_SUMMARY(BV_IR_STAT_RXABORT_SUMMARY__##e)
+#define BFM_IR_STAT_RXABORT_SUMMARY_V(v)        BM_IR_STAT_RXABORT_SUMMARY
+#define BP_IR_STAT_SPEED_SUMMARY                21
+#define BM_IR_STAT_SPEED_SUMMARY                0x200000
+#define BV_IR_STAT_SPEED_SUMMARY__NO_REQUEST    0x0
+#define BV_IR_STAT_SPEED_SUMMARY__REQUEST       0x1
+#define BF_IR_STAT_SPEED_SUMMARY(v)             (((v) & 0x1) << 21)
+#define BFM_IR_STAT_SPEED_SUMMARY(v)            BM_IR_STAT_SPEED_SUMMARY
+#define BF_IR_STAT_SPEED_SUMMARY_V(e)           BF_IR_STAT_SPEED_SUMMARY(BV_IR_STAT_SPEED_SUMMARY__##e)
+#define BFM_IR_STAT_SPEED_SUMMARY_V(v)          BM_IR_STAT_SPEED_SUMMARY
+#define BP_IR_STAT_RXOF_SUMMARY                 20
+#define BM_IR_STAT_RXOF_SUMMARY                 0x100000
+#define BV_IR_STAT_RXOF_SUMMARY__NO_REQUEST     0x0
+#define BV_IR_STAT_RXOF_SUMMARY__REQUEST        0x1
+#define BF_IR_STAT_RXOF_SUMMARY(v)              (((v) & 0x1) << 20)
+#define BFM_IR_STAT_RXOF_SUMMARY(v)             BM_IR_STAT_RXOF_SUMMARY
+#define BF_IR_STAT_RXOF_SUMMARY_V(e)            BF_IR_STAT_RXOF_SUMMARY(BV_IR_STAT_RXOF_SUMMARY__##e)
+#define BFM_IR_STAT_RXOF_SUMMARY_V(v)           BM_IR_STAT_RXOF_SUMMARY
+#define BP_IR_STAT_TXUF_SUMMARY                 19
+#define BM_IR_STAT_TXUF_SUMMARY                 0x80000
+#define BV_IR_STAT_TXUF_SUMMARY__NO_REQUEST     0x0
+#define BV_IR_STAT_TXUF_SUMMARY__REQUEST        0x1
+#define BF_IR_STAT_TXUF_SUMMARY(v)              (((v) & 0x1) << 19)
+#define BFM_IR_STAT_TXUF_SUMMARY(v)             BM_IR_STAT_TXUF_SUMMARY
+#define BF_IR_STAT_TXUF_SUMMARY_V(e)            BF_IR_STAT_TXUF_SUMMARY(BV_IR_STAT_TXUF_SUMMARY__##e)
+#define BFM_IR_STAT_TXUF_SUMMARY_V(v)           BM_IR_STAT_TXUF_SUMMARY
+#define BP_IR_STAT_TC_SUMMARY                   18
+#define BM_IR_STAT_TC_SUMMARY                   0x40000
+#define BV_IR_STAT_TC_SUMMARY__NO_REQUEST       0x0
+#define BV_IR_STAT_TC_SUMMARY__REQUEST          0x1
+#define BF_IR_STAT_TC_SUMMARY(v)                (((v) & 0x1) << 18)
+#define BFM_IR_STAT_TC_SUMMARY(v)               BM_IR_STAT_TC_SUMMARY
+#define BF_IR_STAT_TC_SUMMARY_V(e)              BF_IR_STAT_TC_SUMMARY(BV_IR_STAT_TC_SUMMARY__##e)
+#define BFM_IR_STAT_TC_SUMMARY_V(v)             BM_IR_STAT_TC_SUMMARY
+#define BP_IR_STAT_RX_SUMMARY                   17
+#define BM_IR_STAT_RX_SUMMARY                   0x20000
+#define BV_IR_STAT_RX_SUMMARY__NO_REQUEST       0x0
+#define BV_IR_STAT_RX_SUMMARY__REQUEST          0x1
+#define BF_IR_STAT_RX_SUMMARY(v)                (((v) & 0x1) << 17)
+#define BFM_IR_STAT_RX_SUMMARY(v)               BM_IR_STAT_RX_SUMMARY
+#define BF_IR_STAT_RX_SUMMARY_V(e)              BF_IR_STAT_RX_SUMMARY(BV_IR_STAT_RX_SUMMARY__##e)
+#define BFM_IR_STAT_RX_SUMMARY_V(v)             BM_IR_STAT_RX_SUMMARY
+#define BP_IR_STAT_TX_SUMMARY                   16
+#define BM_IR_STAT_TX_SUMMARY                   0x10000
+#define BV_IR_STAT_TX_SUMMARY__NO_REQUEST       0x0
+#define BV_IR_STAT_TX_SUMMARY__REQUEST          0x1
+#define BF_IR_STAT_TX_SUMMARY(v)                (((v) & 0x1) << 16)
+#define BFM_IR_STAT_TX_SUMMARY(v)               BM_IR_STAT_TX_SUMMARY
+#define BF_IR_STAT_TX_SUMMARY_V(e)              BF_IR_STAT_TX_SUMMARY(BV_IR_STAT_TX_SUMMARY__##e)
+#define BFM_IR_STAT_TX_SUMMARY_V(v)             BM_IR_STAT_TX_SUMMARY
+#define BP_IR_STAT_RSVD1                        3
+#define BM_IR_STAT_RSVD1                        0xfff8
+#define BF_IR_STAT_RSVD1(v)                     (((v) & 0x1fff) << 3)
+#define BFM_IR_STAT_RSVD1(v)                    BM_IR_STAT_RSVD1
+#define BF_IR_STAT_RSVD1_V(e)                   BF_IR_STAT_RSVD1(BV_IR_STAT_RSVD1__##e)
+#define BFM_IR_STAT_RSVD1_V(v)                  BM_IR_STAT_RSVD1
+#define BP_IR_STAT_MEDIA_BUSY                   2
+#define BM_IR_STAT_MEDIA_BUSY                   0x4
+#define BF_IR_STAT_MEDIA_BUSY(v)                (((v) & 0x1) << 2)
+#define BFM_IR_STAT_MEDIA_BUSY(v)               BM_IR_STAT_MEDIA_BUSY
+#define BF_IR_STAT_MEDIA_BUSY_V(e)              BF_IR_STAT_MEDIA_BUSY(BV_IR_STAT_MEDIA_BUSY__##e)
+#define BFM_IR_STAT_MEDIA_BUSY_V(v)             BM_IR_STAT_MEDIA_BUSY
+#define BP_IR_STAT_RX_ACTIVE                    1
+#define BM_IR_STAT_RX_ACTIVE                    0x2
+#define BF_IR_STAT_RX_ACTIVE(v)                 (((v) & 0x1) << 1)
+#define BFM_IR_STAT_RX_ACTIVE(v)                BM_IR_STAT_RX_ACTIVE
+#define BF_IR_STAT_RX_ACTIVE_V(e)               BF_IR_STAT_RX_ACTIVE(BV_IR_STAT_RX_ACTIVE__##e)
+#define BFM_IR_STAT_RX_ACTIVE_V(v)              BM_IR_STAT_RX_ACTIVE
+#define BP_IR_STAT_TX_ACTIVE                    0
+#define BM_IR_STAT_TX_ACTIVE                    0x1
+#define BF_IR_STAT_TX_ACTIVE(v)                 (((v) & 0x1) << 0)
+#define BFM_IR_STAT_TX_ACTIVE(v)                BM_IR_STAT_TX_ACTIVE
+#define BF_IR_STAT_TX_ACTIVE_V(e)               BF_IR_STAT_TX_ACTIVE(BV_IR_STAT_TX_ACTIVE__##e)
+#define BFM_IR_STAT_TX_ACTIVE_V(v)              BM_IR_STAT_TX_ACTIVE
+
+#define HW_IR_TCCTRL                HW(IR_TCCTRL)
+#define HWA_IR_TCCTRL               (0x80078000 + 0x70)
+#define HWT_IR_TCCTRL               HWIO_32_RW
+#define HWN_IR_TCCTRL               IR_TCCTRL
+#define HWI_IR_TCCTRL               
+#define HW_IR_TCCTRL_SET            HW(IR_TCCTRL_SET)
+#define HWA_IR_TCCTRL_SET           (HWA_IR_TCCTRL + 0x4)
+#define HWT_IR_TCCTRL_SET           HWIO_32_WO
+#define HWN_IR_TCCTRL_SET           IR_TCCTRL
+#define HWI_IR_TCCTRL_SET           
+#define HW_IR_TCCTRL_CLR            HW(IR_TCCTRL_CLR)
+#define HWA_IR_TCCTRL_CLR           (HWA_IR_TCCTRL + 0x8)
+#define HWT_IR_TCCTRL_CLR           HWIO_32_WO
+#define HWN_IR_TCCTRL_CLR           IR_TCCTRL
+#define HWI_IR_TCCTRL_CLR           
+#define HW_IR_TCCTRL_TOG            HW(IR_TCCTRL_TOG)
+#define HWA_IR_TCCTRL_TOG           (HWA_IR_TCCTRL + 0xc)
+#define HWT_IR_TCCTRL_TOG           HWIO_32_WO
+#define HWN_IR_TCCTRL_TOG           IR_TCCTRL
+#define HWI_IR_TCCTRL_TOG           
+#define BP_IR_TCCTRL_INIT           31
+#define BM_IR_TCCTRL_INIT           0x80000000
+#define BF_IR_TCCTRL_INIT(v)        (((v) & 0x1) << 31)
+#define BFM_IR_TCCTRL_INIT(v)       BM_IR_TCCTRL_INIT
+#define BF_IR_TCCTRL_INIT_V(e)      BF_IR_TCCTRL_INIT(BV_IR_TCCTRL_INIT__##e)
+#define BFM_IR_TCCTRL_INIT_V(v)     BM_IR_TCCTRL_INIT
+#define BP_IR_TCCTRL_GO             30
+#define BM_IR_TCCTRL_GO             0x40000000
+#define BF_IR_TCCTRL_GO(v)          (((v) & 0x1) << 30)
+#define BFM_IR_TCCTRL_GO(v)         BM_IR_TCCTRL_GO
+#define BF_IR_TCCTRL_GO_V(e)        BF_IR_TCCTRL_GO(BV_IR_TCCTRL_GO__##e)
+#define BFM_IR_TCCTRL_GO_V(v)       BM_IR_TCCTRL_GO
+#define BP_IR_TCCTRL_BUSY           29
+#define BM_IR_TCCTRL_BUSY           0x20000000
+#define BF_IR_TCCTRL_BUSY(v)        (((v) & 0x1) << 29)
+#define BFM_IR_TCCTRL_BUSY(v)       BM_IR_TCCTRL_BUSY
+#define BF_IR_TCCTRL_BUSY_V(e)      BF_IR_TCCTRL_BUSY(BV_IR_TCCTRL_BUSY__##e)
+#define BFM_IR_TCCTRL_BUSY_V(v)     BM_IR_TCCTRL_BUSY
+#define BP_IR_TCCTRL_RSVD           25
+#define BM_IR_TCCTRL_RSVD           0x1e000000
+#define BF_IR_TCCTRL_RSVD(v)        (((v) & 0xf) << 25)
+#define BFM_IR_TCCTRL_RSVD(v)       BM_IR_TCCTRL_RSVD
+#define BF_IR_TCCTRL_RSVD_V(e)      BF_IR_TCCTRL_RSVD(BV_IR_TCCTRL_RSVD__##e)
+#define BFM_IR_TCCTRL_RSVD_V(v)     BM_IR_TCCTRL_RSVD
+#define BP_IR_TCCTRL_TEMIC          24
+#define BM_IR_TCCTRL_TEMIC          0x1000000
+#define BV_IR_TCCTRL_TEMIC__LOW     0x0
+#define BV_IR_TCCTRL_TEMIC__HIGH    0x1
+#define BF_IR_TCCTRL_TEMIC(v)       (((v) & 0x1) << 24)
+#define BFM_IR_TCCTRL_TEMIC(v)      BM_IR_TCCTRL_TEMIC
+#define BF_IR_TCCTRL_TEMIC_V(e)     BF_IR_TCCTRL_TEMIC(BV_IR_TCCTRL_TEMIC__##e)
+#define BFM_IR_TCCTRL_TEMIC_V(v)    BM_IR_TCCTRL_TEMIC
+#define BP_IR_TCCTRL_EXT_DATA       16
+#define BM_IR_TCCTRL_EXT_DATA       0xff0000
+#define BF_IR_TCCTRL_EXT_DATA(v)    (((v) & 0xff) << 16)
+#define BFM_IR_TCCTRL_EXT_DATA(v)   BM_IR_TCCTRL_EXT_DATA
+#define BF_IR_TCCTRL_EXT_DATA_V(e)  BF_IR_TCCTRL_EXT_DATA(BV_IR_TCCTRL_EXT_DATA__##e)
+#define BFM_IR_TCCTRL_EXT_DATA_V(v) BM_IR_TCCTRL_EXT_DATA
+#define BP_IR_TCCTRL_DATA           8
+#define BM_IR_TCCTRL_DATA           0xff00
+#define BF_IR_TCCTRL_DATA(v)        (((v) & 0xff) << 8)
+#define BFM_IR_TCCTRL_DATA(v)       BM_IR_TCCTRL_DATA
+#define BF_IR_TCCTRL_DATA_V(e)      BF_IR_TCCTRL_DATA(BV_IR_TCCTRL_DATA__##e)
+#define BFM_IR_TCCTRL_DATA_V(v)     BM_IR_TCCTRL_DATA
+#define BP_IR_TCCTRL_ADDR           5
+#define BM_IR_TCCTRL_ADDR           0xe0
+#define BF_IR_TCCTRL_ADDR(v)        (((v) & 0x7) << 5)
+#define BFM_IR_TCCTRL_ADDR(v)       BM_IR_TCCTRL_ADDR
+#define BF_IR_TCCTRL_ADDR_V(e)      BF_IR_TCCTRL_ADDR(BV_IR_TCCTRL_ADDR__##e)
+#define BFM_IR_TCCTRL_ADDR_V(v)     BM_IR_TCCTRL_ADDR
+#define BP_IR_TCCTRL_INDX           1
+#define BM_IR_TCCTRL_INDX           0x1e
+#define BF_IR_TCCTRL_INDX(v)        (((v) & 0xf) << 1)
+#define BFM_IR_TCCTRL_INDX(v)       BM_IR_TCCTRL_INDX
+#define BF_IR_TCCTRL_INDX_V(e)      BF_IR_TCCTRL_INDX(BV_IR_TCCTRL_INDX__##e)
+#define BFM_IR_TCCTRL_INDX_V(v)     BM_IR_TCCTRL_INDX
+#define BP_IR_TCCTRL_C              0
+#define BM_IR_TCCTRL_C              0x1
+#define BF_IR_TCCTRL_C(v)           (((v) & 0x1) << 0)
+#define BFM_IR_TCCTRL_C(v)          BM_IR_TCCTRL_C
+#define BF_IR_TCCTRL_C_V(e)         BF_IR_TCCTRL_C(BV_IR_TCCTRL_C__##e)
+#define BFM_IR_TCCTRL_C_V(v)        BM_IR_TCCTRL_C
+
+#define HW_IR_SI_READ               HW(IR_SI_READ)
+#define HWA_IR_SI_READ              (0x80078000 + 0x80)
+#define HWT_IR_SI_READ              HWIO_32_RW
+#define HWN_IR_SI_READ              IR_SI_READ
+#define HWI_IR_SI_READ              
+#define BP_IR_SI_READ_RSVD1         9
+#define BM_IR_SI_READ_RSVD1         0xfffffe00
+#define BF_IR_SI_READ_RSVD1(v)      (((v) & 0x7fffff) << 9)
+#define BFM_IR_SI_READ_RSVD1(v)     BM_IR_SI_READ_RSVD1
+#define BF_IR_SI_READ_RSVD1_V(e)    BF_IR_SI_READ_RSVD1(BV_IR_SI_READ_RSVD1__##e)
+#define BFM_IR_SI_READ_RSVD1_V(v)   BM_IR_SI_READ_RSVD1
+#define BP_IR_SI_READ_ABORT         8
+#define BM_IR_SI_READ_ABORT         0x100
+#define BF_IR_SI_READ_ABORT(v)      (((v) & 0x1) << 8)
+#define BFM_IR_SI_READ_ABORT(v)     BM_IR_SI_READ_ABORT
+#define BF_IR_SI_READ_ABORT_V(e)    BF_IR_SI_READ_ABORT(BV_IR_SI_READ_ABORT__##e)
+#define BFM_IR_SI_READ_ABORT_V(v)   BM_IR_SI_READ_ABORT
+#define BP_IR_SI_READ_DATA          0
+#define BM_IR_SI_READ_DATA          0xff
+#define BF_IR_SI_READ_DATA(v)       (((v) & 0xff) << 0)
+#define BFM_IR_SI_READ_DATA(v)      BM_IR_SI_READ_DATA
+#define BF_IR_SI_READ_DATA_V(e)     BF_IR_SI_READ_DATA(BV_IR_SI_READ_DATA__##e)
+#define BFM_IR_SI_READ_DATA_V(v)    BM_IR_SI_READ_DATA
+
+#define HW_IR_DEBUG                 HW(IR_DEBUG)
+#define HWA_IR_DEBUG                (0x80078000 + 0x90)
+#define HWT_IR_DEBUG                HWIO_32_RW
+#define HWN_IR_DEBUG                IR_DEBUG
+#define HWI_IR_DEBUG                
+#define BP_IR_DEBUG_RSVD1           6
+#define BM_IR_DEBUG_RSVD1           0xffffffc0
+#define BF_IR_DEBUG_RSVD1(v)        (((v) & 0x3ffffff) << 6)
+#define BFM_IR_DEBUG_RSVD1(v)       BM_IR_DEBUG_RSVD1
+#define BF_IR_DEBUG_RSVD1_V(e)      BF_IR_DEBUG_RSVD1(BV_IR_DEBUG_RSVD1__##e)
+#define BFM_IR_DEBUG_RSVD1_V(v)     BM_IR_DEBUG_RSVD1
+#define BP_IR_DEBUG_TXDMAKICK       5
+#define BM_IR_DEBUG_TXDMAKICK       0x20
+#define BF_IR_DEBUG_TXDMAKICK(v)    (((v) & 0x1) << 5)
+#define BFM_IR_DEBUG_TXDMAKICK(v)   BM_IR_DEBUG_TXDMAKICK
+#define BF_IR_DEBUG_TXDMAKICK_V(e)  BF_IR_DEBUG_TXDMAKICK(BV_IR_DEBUG_TXDMAKICK__##e)
+#define BFM_IR_DEBUG_TXDMAKICK_V(v) BM_IR_DEBUG_TXDMAKICK
+#define BP_IR_DEBUG_RXDMAKICK       4
+#define BM_IR_DEBUG_RXDMAKICK       0x10
+#define BF_IR_DEBUG_RXDMAKICK(v)    (((v) & 0x1) << 4)
+#define BFM_IR_DEBUG_RXDMAKICK(v)   BM_IR_DEBUG_RXDMAKICK
+#define BF_IR_DEBUG_RXDMAKICK_V(e)  BF_IR_DEBUG_RXDMAKICK(BV_IR_DEBUG_RXDMAKICK__##e)
+#define BFM_IR_DEBUG_RXDMAKICK_V(v) BM_IR_DEBUG_RXDMAKICK
+#define BP_IR_DEBUG_TXDMAEND        3
+#define BM_IR_DEBUG_TXDMAEND        0x8
+#define BF_IR_DEBUG_TXDMAEND(v)     (((v) & 0x1) << 3)
+#define BFM_IR_DEBUG_TXDMAEND(v)    BM_IR_DEBUG_TXDMAEND
+#define BF_IR_DEBUG_TXDMAEND_V(e)   BF_IR_DEBUG_TXDMAEND(BV_IR_DEBUG_TXDMAEND__##e)
+#define BFM_IR_DEBUG_TXDMAEND_V(v)  BM_IR_DEBUG_TXDMAEND
+#define BP_IR_DEBUG_RXDMAEND        2
+#define BM_IR_DEBUG_RXDMAEND        0x4
+#define BF_IR_DEBUG_RXDMAEND(v)     (((v) & 0x1) << 2)
+#define BFM_IR_DEBUG_RXDMAEND(v)    BM_IR_DEBUG_RXDMAEND
+#define BF_IR_DEBUG_RXDMAEND_V(e)   BF_IR_DEBUG_RXDMAEND(BV_IR_DEBUG_RXDMAEND__##e)
+#define BFM_IR_DEBUG_RXDMAEND_V(v)  BM_IR_DEBUG_RXDMAEND
+#define BP_IR_DEBUG_TXDMAREQ        1
+#define BM_IR_DEBUG_TXDMAREQ        0x2
+#define BF_IR_DEBUG_TXDMAREQ(v)     (((v) & 0x1) << 1)
+#define BFM_IR_DEBUG_TXDMAREQ(v)    BM_IR_DEBUG_TXDMAREQ
+#define BF_IR_DEBUG_TXDMAREQ_V(e)   BF_IR_DEBUG_TXDMAREQ(BV_IR_DEBUG_TXDMAREQ__##e)
+#define BFM_IR_DEBUG_TXDMAREQ_V(v)  BM_IR_DEBUG_TXDMAREQ
+#define BP_IR_DEBUG_RXDMAREQ        0
+#define BM_IR_DEBUG_RXDMAREQ        0x1
+#define BF_IR_DEBUG_RXDMAREQ(v)     (((v) & 0x1) << 0)
+#define BFM_IR_DEBUG_RXDMAREQ(v)    BM_IR_DEBUG_RXDMAREQ
+#define BF_IR_DEBUG_RXDMAREQ_V(e)   BF_IR_DEBUG_RXDMAREQ(BV_IR_DEBUG_RXDMAREQ__##e)
+#define BFM_IR_DEBUG_RXDMAREQ_V(v)  BM_IR_DEBUG_RXDMAREQ
+
+#define HW_IR_VERSION               HW(IR_VERSION)
+#define HWA_IR_VERSION              (0x80078000 + 0xa0)
+#define HWT_IR_VERSION              HWIO_32_RW
+#define HWN_IR_VERSION              IR_VERSION
+#define HWI_IR_VERSION              
+#define BP_IR_VERSION_MAJOR         24
+#define BM_IR_VERSION_MAJOR         0xff000000
+#define BF_IR_VERSION_MAJOR(v)      (((v) & 0xff) << 24)
+#define BFM_IR_VERSION_MAJOR(v)     BM_IR_VERSION_MAJOR
+#define BF_IR_VERSION_MAJOR_V(e)    BF_IR_VERSION_MAJOR(BV_IR_VERSION_MAJOR__##e)
+#define BFM_IR_VERSION_MAJOR_V(v)   BM_IR_VERSION_MAJOR
+#define BP_IR_VERSION_MINOR         16
+#define BM_IR_VERSION_MINOR         0xff0000
+#define BF_IR_VERSION_MINOR(v)      (((v) & 0xff) << 16)
+#define BFM_IR_VERSION_MINOR(v)     BM_IR_VERSION_MINOR
+#define BF_IR_VERSION_MINOR_V(e)    BF_IR_VERSION_MINOR(BV_IR_VERSION_MINOR__##e)
+#define BFM_IR_VERSION_MINOR_V(v)   BM_IR_VERSION_MINOR
+#define BP_IR_VERSION_STEP          0
+#define BM_IR_VERSION_STEP          0xffff
+#define BF_IR_VERSION_STEP(v)       (((v) & 0xffff) << 0)
+#define BFM_IR_VERSION_STEP(v)      BM_IR_VERSION_STEP
+#define BF_IR_VERSION_STEP_V(e)     BF_IR_VERSION_STEP(BV_IR_VERSION_STEP__##e)
+#define BFM_IR_VERSION_STEP_V(v)    BM_IR_VERSION_STEP
+
+#endif /* __HEADERGEN_IMX233_IR_H__*/
diff --git a/firmware/target/arm/imx233/regs/imx233/lcdif.h b/firmware/target/arm/imx233/regs/imx233/lcdif.h
new file mode 100644
index 0000000000..ebbd8d8936
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/imx233/lcdif.h
@@ -0,0 +1,1411 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * imx233 version: 2.4.0
+ * imx233 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_IMX233_LCDIF_H__
+#define __HEADERGEN_IMX233_LCDIF_H__
+
+#define HW_LCDIF_CTRL                                                   HW(LCDIF_CTRL)
+#define HWA_LCDIF_CTRL                                                  (0x80030000 + 0x0)
+#define HWT_LCDIF_CTRL                                                  HWIO_32_RW
+#define HWN_LCDIF_CTRL                                                  LCDIF_CTRL
+#define HWI_LCDIF_CTRL                                                  
+#define HW_LCDIF_CTRL_SET                                               HW(LCDIF_CTRL_SET)
+#define HWA_LCDIF_CTRL_SET                                              (HWA_LCDIF_CTRL + 0x4)
+#define HWT_LCDIF_CTRL_SET                                              HWIO_32_WO
+#define HWN_LCDIF_CTRL_SET                                              LCDIF_CTRL
+#define HWI_LCDIF_CTRL_SET                                              
+#define HW_LCDIF_CTRL_CLR                                               HW(LCDIF_CTRL_CLR)
+#define HWA_LCDIF_CTRL_CLR                                              (HWA_LCDIF_CTRL + 0x8)
+#define HWT_LCDIF_CTRL_CLR                                              HWIO_32_WO
+#define HWN_LCDIF_CTRL_CLR                                              LCDIF_CTRL
+#define HWI_LCDIF_CTRL_CLR                                              
+#define HW_LCDIF_CTRL_TOG                                               HW(LCDIF_CTRL_TOG)
+#define HWA_LCDIF_CTRL_TOG                                              (HWA_LCDIF_CTRL + 0xc)
+#define HWT_LCDIF_CTRL_TOG                                              HWIO_32_WO
+#define HWN_LCDIF_CTRL_TOG                                              LCDIF_CTRL
+#define HWI_LCDIF_CTRL_TOG                                              
+#define BP_LCDIF_CTRL_SFTRST                                            31
+#define BM_LCDIF_CTRL_SFTRST                                            0x80000000
+#define BF_LCDIF_CTRL_SFTRST(v)                                         (((v) & 0x1) << 31)
+#define BFM_LCDIF_CTRL_SFTRST(v)                                        BM_LCDIF_CTRL_SFTRST
+#define BF_LCDIF_CTRL_SFTRST_V(e)                                       BF_LCDIF_CTRL_SFTRST(BV_LCDIF_CTRL_SFTRST__##e)
+#define BFM_LCDIF_CTRL_SFTRST_V(v)                                      BM_LCDIF_CTRL_SFTRST
+#define BP_LCDIF_CTRL_CLKGATE                                           30
+#define BM_LCDIF_CTRL_CLKGATE                                           0x40000000
+#define BF_LCDIF_CTRL_CLKGATE(v)                                        (((v) & 0x1) << 30)
+#define BFM_LCDIF_CTRL_CLKGATE(v)                                       BM_LCDIF_CTRL_CLKGATE
+#define BF_LCDIF_CTRL_CLKGATE_V(e)                                      BF_LCDIF_CTRL_CLKGATE(BV_LCDIF_CTRL_CLKGATE__##e)
+#define BFM_LCDIF_CTRL_CLKGATE_V(v)                                     BM_LCDIF_CTRL_CLKGATE
+#define BP_LCDIF_CTRL_YCBCR422_INPUT                                    29
+#define BM_LCDIF_CTRL_YCBCR422_INPUT                                    0x20000000
+#define BF_LCDIF_CTRL_YCBCR422_INPUT(v)                                 (((v) & 0x1) << 29)
+#define BFM_LCDIF_CTRL_YCBCR422_INPUT(v)                                BM_LCDIF_CTRL_YCBCR422_INPUT
+#define BF_LCDIF_CTRL_YCBCR422_INPUT_V(e)                               BF_LCDIF_CTRL_YCBCR422_INPUT(BV_LCDIF_CTRL_YCBCR422_INPUT__##e)
+#define BFM_LCDIF_CTRL_YCBCR422_INPUT_V(v)                              BM_LCDIF_CTRL_YCBCR422_INPUT
+#define BP_LCDIF_CTRL_RSRVD0                                            28
+#define BM_LCDIF_CTRL_RSRVD0                                            0x10000000
+#define BF_LCDIF_CTRL_RSRVD0(v)                                         (((v) & 0x1) << 28)
+#define BFM_LCDIF_CTRL_RSRVD0(v)                                        BM_LCDIF_CTRL_RSRVD0
+#define BF_LCDIF_CTRL_RSRVD0_V(e)                                       BF_LCDIF_CTRL_RSRVD0(BV_LCDIF_CTRL_RSRVD0__##e)
+#define BFM_LCDIF_CTRL_RSRVD0_V(v)                                      BM_LCDIF_CTRL_RSRVD0
+#define BP_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE                               27
+#define BM_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE                               0x8000000
+#define BF_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE(v)                            (((v) & 0x1) << 27)
+#define BFM_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE(v)                           BM_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE
+#define BF_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE_V(e)                          BF_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE(BV_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE__##e)
+#define BFM_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE_V(v)                         BM_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE
+#define BP_LCDIF_CTRL_DATA_SHIFT_DIR                                    26
+#define BM_LCDIF_CTRL_DATA_SHIFT_DIR                                    0x4000000
+#define BV_LCDIF_CTRL_DATA_SHIFT_DIR__TXDATA_SHIFT_LEFT                 0x0
+#define BV_LCDIF_CTRL_DATA_SHIFT_DIR__TXDATA_SHIFT_RIGHT                0x1
+#define BF_LCDIF_CTRL_DATA_SHIFT_DIR(v)                                 (((v) & 0x1) << 26)
+#define BFM_LCDIF_CTRL_DATA_SHIFT_DIR(v)                                BM_LCDIF_CTRL_DATA_SHIFT_DIR
+#define BF_LCDIF_CTRL_DATA_SHIFT_DIR_V(e)                               BF_LCDIF_CTRL_DATA_SHIFT_DIR(BV_LCDIF_CTRL_DATA_SHIFT_DIR__##e)
+#define BFM_LCDIF_CTRL_DATA_SHIFT_DIR_V(v)                              BM_LCDIF_CTRL_DATA_SHIFT_DIR
+#define BP_LCDIF_CTRL_SHIFT_NUM_BITS                                    21
+#define BM_LCDIF_CTRL_SHIFT_NUM_BITS                                    0x3e00000
+#define BF_LCDIF_CTRL_SHIFT_NUM_BITS(v)                                 (((v) & 0x1f) << 21)
+#define BFM_LCDIF_CTRL_SHIFT_NUM_BITS(v)                                BM_LCDIF_CTRL_SHIFT_NUM_BITS
+#define BF_LCDIF_CTRL_SHIFT_NUM_BITS_V(e)                               BF_LCDIF_CTRL_SHIFT_NUM_BITS(BV_LCDIF_CTRL_SHIFT_NUM_BITS__##e)
+#define BFM_LCDIF_CTRL_SHIFT_NUM_BITS_V(v)                              BM_LCDIF_CTRL_SHIFT_NUM_BITS
+#define BP_LCDIF_CTRL_DVI_MODE                                          20
+#define BM_LCDIF_CTRL_DVI_MODE                                          0x100000
+#define BF_LCDIF_CTRL_DVI_MODE(v)                                       (((v) & 0x1) << 20)
+#define BFM_LCDIF_CTRL_DVI_MODE(v)                                      BM_LCDIF_CTRL_DVI_MODE
+#define BF_LCDIF_CTRL_DVI_MODE_V(e)                                     BF_LCDIF_CTRL_DVI_MODE(BV_LCDIF_CTRL_DVI_MODE__##e)
+#define BFM_LCDIF_CTRL_DVI_MODE_V(v)                                    BM_LCDIF_CTRL_DVI_MODE
+#define BP_LCDIF_CTRL_BYPASS_COUNT                                      19
+#define BM_LCDIF_CTRL_BYPASS_COUNT                                      0x80000
+#define BF_LCDIF_CTRL_BYPASS_COUNT(v)                                   (((v) & 0x1) << 19)
+#define BFM_LCDIF_CTRL_BYPASS_COUNT(v)                                  BM_LCDIF_CTRL_BYPASS_COUNT
+#define BF_LCDIF_CTRL_BYPASS_COUNT_V(e)                                 BF_LCDIF_CTRL_BYPASS_COUNT(BV_LCDIF_CTRL_BYPASS_COUNT__##e)
+#define BFM_LCDIF_CTRL_BYPASS_COUNT_V(v)                                BM_LCDIF_CTRL_BYPASS_COUNT
+#define BP_LCDIF_CTRL_VSYNC_MODE                                        18
+#define BM_LCDIF_CTRL_VSYNC_MODE                                        0x40000
+#define BF_LCDIF_CTRL_VSYNC_MODE(v)                                     (((v) & 0x1) << 18)
+#define BFM_LCDIF_CTRL_VSYNC_MODE(v)                                    BM_LCDIF_CTRL_VSYNC_MODE
+#define BF_LCDIF_CTRL_VSYNC_MODE_V(e)                                   BF_LCDIF_CTRL_VSYNC_MODE(BV_LCDIF_CTRL_VSYNC_MODE__##e)
+#define BFM_LCDIF_CTRL_VSYNC_MODE_V(v)                                  BM_LCDIF_CTRL_VSYNC_MODE
+#define BP_LCDIF_CTRL_DOTCLK_MODE                                       17
+#define BM_LCDIF_CTRL_DOTCLK_MODE                                       0x20000
+#define BF_LCDIF_CTRL_DOTCLK_MODE(v)                                    (((v) & 0x1) << 17)
+#define BFM_LCDIF_CTRL_DOTCLK_MODE(v)                                   BM_LCDIF_CTRL_DOTCLK_MODE
+#define BF_LCDIF_CTRL_DOTCLK_MODE_V(e)                                  BF_LCDIF_CTRL_DOTCLK_MODE(BV_LCDIF_CTRL_DOTCLK_MODE__##e)
+#define BFM_LCDIF_CTRL_DOTCLK_MODE_V(v)                                 BM_LCDIF_CTRL_DOTCLK_MODE
+#define BP_LCDIF_CTRL_DATA_SELECT                                       16
+#define BM_LCDIF_CTRL_DATA_SELECT                                       0x10000
+#define BV_LCDIF_CTRL_DATA_SELECT__CMD_MODE                             0x0
+#define BV_LCDIF_CTRL_DATA_SELECT__DATA_MODE                            0x1
+#define BF_LCDIF_CTRL_DATA_SELECT(v)                                    (((v) & 0x1) << 16)
+#define BFM_LCDIF_CTRL_DATA_SELECT(v)                                   BM_LCDIF_CTRL_DATA_SELECT
+#define BF_LCDIF_CTRL_DATA_SELECT_V(e)                                  BF_LCDIF_CTRL_DATA_SELECT(BV_LCDIF_CTRL_DATA_SELECT__##e)
+#define BFM_LCDIF_CTRL_DATA_SELECT_V(v)                                 BM_LCDIF_CTRL_DATA_SELECT
+#define BP_LCDIF_CTRL_INPUT_DATA_SWIZZLE                                14
+#define BM_LCDIF_CTRL_INPUT_DATA_SWIZZLE                                0xc000
+#define BV_LCDIF_CTRL_INPUT_DATA_SWIZZLE__NO_SWAP                       0x0
+#define BV_LCDIF_CTRL_INPUT_DATA_SWIZZLE__LITTLE_ENDIAN                 0x0
+#define BV_LCDIF_CTRL_INPUT_DATA_SWIZZLE__BIG_ENDIAN_SWAP               0x1
+#define BV_LCDIF_CTRL_INPUT_DATA_SWIZZLE__SWAP_ALL_BYTES                0x1
+#define BV_LCDIF_CTRL_INPUT_DATA_SWIZZLE__HWD_SWAP                      0x2
+#define BV_LCDIF_CTRL_INPUT_DATA_SWIZZLE__HWD_BYTE_SWAP                 0x3
+#define BF_LCDIF_CTRL_INPUT_DATA_SWIZZLE(v)                             (((v) & 0x3) << 14)
+#define BFM_LCDIF_CTRL_INPUT_DATA_SWIZZLE(v)                            BM_LCDIF_CTRL_INPUT_DATA_SWIZZLE
+#define BF_LCDIF_CTRL_INPUT_DATA_SWIZZLE_V(e)                           BF_LCDIF_CTRL_INPUT_DATA_SWIZZLE(BV_LCDIF_CTRL_INPUT_DATA_SWIZZLE__##e)
+#define BFM_LCDIF_CTRL_INPUT_DATA_SWIZZLE_V(v)                          BM_LCDIF_CTRL_INPUT_DATA_SWIZZLE
+#define BP_LCDIF_CTRL_CSC_DATA_SWIZZLE                                  12
+#define BM_LCDIF_CTRL_CSC_DATA_SWIZZLE                                  0x3000
+#define BV_LCDIF_CTRL_CSC_DATA_SWIZZLE__NO_SWAP                         0x0
+#define BV_LCDIF_CTRL_CSC_DATA_SWIZZLE__LITTLE_ENDIAN                   0x0
+#define BV_LCDIF_CTRL_CSC_DATA_SWIZZLE__BIG_ENDIAN_SWAP                 0x1
+#define BV_LCDIF_CTRL_CSC_DATA_SWIZZLE__SWAP_ALL_BYTES                  0x1
+#define BV_LCDIF_CTRL_CSC_DATA_SWIZZLE__HWD_SWAP                        0x2
+#define BV_LCDIF_CTRL_CSC_DATA_SWIZZLE__HWD_BYTE_SWAP                   0x3
+#define BF_LCDIF_CTRL_CSC_DATA_SWIZZLE(v)                               (((v) & 0x3) << 12)
+#define BFM_LCDIF_CTRL_CSC_DATA_SWIZZLE(v)                              BM_LCDIF_CTRL_CSC_DATA_SWIZZLE
+#define BF_LCDIF_CTRL_CSC_DATA_SWIZZLE_V(e)                             BF_LCDIF_CTRL_CSC_DATA_SWIZZLE(BV_LCDIF_CTRL_CSC_DATA_SWIZZLE__##e)
+#define BFM_LCDIF_CTRL_CSC_DATA_SWIZZLE_V(v)                            BM_LCDIF_CTRL_CSC_DATA_SWIZZLE
+#define BP_LCDIF_CTRL_LCD_DATABUS_WIDTH                                 10
+#define BM_LCDIF_CTRL_LCD_DATABUS_WIDTH                                 0xc00
+#define BV_LCDIF_CTRL_LCD_DATABUS_WIDTH__16_BIT                         0x0
+#define BV_LCDIF_CTRL_LCD_DATABUS_WIDTH__8_BIT                          0x1
+#define BV_LCDIF_CTRL_LCD_DATABUS_WIDTH__18_BIT                         0x2
+#define BV_LCDIF_CTRL_LCD_DATABUS_WIDTH__24_BIT                         0x3
+#define BF_LCDIF_CTRL_LCD_DATABUS_WIDTH(v)                              (((v) & 0x3) << 10)
+#define BFM_LCDIF_CTRL_LCD_DATABUS_WIDTH(v)                             BM_LCDIF_CTRL_LCD_DATABUS_WIDTH
+#define BF_LCDIF_CTRL_LCD_DATABUS_WIDTH_V(e)                            BF_LCDIF_CTRL_LCD_DATABUS_WIDTH(BV_LCDIF_CTRL_LCD_DATABUS_WIDTH__##e)
+#define BFM_LCDIF_CTRL_LCD_DATABUS_WIDTH_V(v)                           BM_LCDIF_CTRL_LCD_DATABUS_WIDTH
+#define BP_LCDIF_CTRL_WORD_LENGTH                                       8
+#define BM_LCDIF_CTRL_WORD_LENGTH                                       0x300
+#define BV_LCDIF_CTRL_WORD_LENGTH__16_BIT                               0x0
+#define BV_LCDIF_CTRL_WORD_LENGTH__8_BIT                                0x1
+#define BV_LCDIF_CTRL_WORD_LENGTH__18_BIT                               0x2
+#define BV_LCDIF_CTRL_WORD_LENGTH__24_BIT                               0x3
+#define BF_LCDIF_CTRL_WORD_LENGTH(v)                                    (((v) & 0x3) << 8)
+#define BFM_LCDIF_CTRL_WORD_LENGTH(v)                                   BM_LCDIF_CTRL_WORD_LENGTH
+#define BF_LCDIF_CTRL_WORD_LENGTH_V(e)                                  BF_LCDIF_CTRL_WORD_LENGTH(BV_LCDIF_CTRL_WORD_LENGTH__##e)
+#define BFM_LCDIF_CTRL_WORD_LENGTH_V(v)                                 BM_LCDIF_CTRL_WORD_LENGTH
+#define BP_LCDIF_CTRL_RGB_TO_YCBCR422_CSC                               7
+#define BM_LCDIF_CTRL_RGB_TO_YCBCR422_CSC                               0x80
+#define BF_LCDIF_CTRL_RGB_TO_YCBCR422_CSC(v)                            (((v) & 0x1) << 7)
+#define BFM_LCDIF_CTRL_RGB_TO_YCBCR422_CSC(v)                           BM_LCDIF_CTRL_RGB_TO_YCBCR422_CSC
+#define BF_LCDIF_CTRL_RGB_TO_YCBCR422_CSC_V(e)                          BF_LCDIF_CTRL_RGB_TO_YCBCR422_CSC(BV_LCDIF_CTRL_RGB_TO_YCBCR422_CSC__##e)
+#define BFM_LCDIF_CTRL_RGB_TO_YCBCR422_CSC_V(v)                         BM_LCDIF_CTRL_RGB_TO_YCBCR422_CSC
+#define BP_LCDIF_CTRL_ENABLE_PXP_HANDSHAKE                              6
+#define BM_LCDIF_CTRL_ENABLE_PXP_HANDSHAKE                              0x40
+#define BF_LCDIF_CTRL_ENABLE_PXP_HANDSHAKE(v)                           (((v) & 0x1) << 6)
+#define BFM_LCDIF_CTRL_ENABLE_PXP_HANDSHAKE(v)                          BM_LCDIF_CTRL_ENABLE_PXP_HANDSHAKE
+#define BF_LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_V(e)                         BF_LCDIF_CTRL_ENABLE_PXP_HANDSHAKE(BV_LCDIF_CTRL_ENABLE_PXP_HANDSHAKE__##e)
+#define BFM_LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_V(v)                        BM_LCDIF_CTRL_ENABLE_PXP_HANDSHAKE
+#define BP_LCDIF_CTRL_LCDIF_MASTER                                      5
+#define BM_LCDIF_CTRL_LCDIF_MASTER                                      0x20
+#define BF_LCDIF_CTRL_LCDIF_MASTER(v)                                   (((v) & 0x1) << 5)
+#define BFM_LCDIF_CTRL_LCDIF_MASTER(v)                                  BM_LCDIF_CTRL_LCDIF_MASTER
+#define BF_LCDIF_CTRL_LCDIF_MASTER_V(e)                                 BF_LCDIF_CTRL_LCDIF_MASTER(BV_LCDIF_CTRL_LCDIF_MASTER__##e)
+#define BFM_LCDIF_CTRL_LCDIF_MASTER_V(v)                                BM_LCDIF_CTRL_LCDIF_MASTER
+#define BP_LCDIF_CTRL_DMA_BURST_LENGTH                                  4
+#define BM_LCDIF_CTRL_DMA_BURST_LENGTH                                  0x10
+#define BF_LCDIF_CTRL_DMA_BURST_LENGTH(v)                               (((v) & 0x1) << 4)
+#define BFM_LCDIF_CTRL_DMA_BURST_LENGTH(v)                              BM_LCDIF_CTRL_DMA_BURST_LENGTH
+#define BF_LCDIF_CTRL_DMA_BURST_LENGTH_V(e)                             BF_LCDIF_CTRL_DMA_BURST_LENGTH(BV_LCDIF_CTRL_DMA_BURST_LENGTH__##e)
+#define BFM_LCDIF_CTRL_DMA_BURST_LENGTH_V(v)                            BM_LCDIF_CTRL_DMA_BURST_LENGTH
+#define BP_LCDIF_CTRL_DATA_FORMAT_16_BIT                                3
+#define BM_LCDIF_CTRL_DATA_FORMAT_16_BIT                                0x8
+#define BF_LCDIF_CTRL_DATA_FORMAT_16_BIT(v)                             (((v) & 0x1) << 3)
+#define BFM_LCDIF_CTRL_DATA_FORMAT_16_BIT(v)                            BM_LCDIF_CTRL_DATA_FORMAT_16_BIT
+#define BF_LCDIF_CTRL_DATA_FORMAT_16_BIT_V(e)                           BF_LCDIF_CTRL_DATA_FORMAT_16_BIT(BV_LCDIF_CTRL_DATA_FORMAT_16_BIT__##e)
+#define BFM_LCDIF_CTRL_DATA_FORMAT_16_BIT_V(v)                          BM_LCDIF_CTRL_DATA_FORMAT_16_BIT
+#define BP_LCDIF_CTRL_DATA_FORMAT_18_BIT                                2
+#define BM_LCDIF_CTRL_DATA_FORMAT_18_BIT                                0x4
+#define BV_LCDIF_CTRL_DATA_FORMAT_18_BIT__LOWER_18_BITS_VALID           0x0
+#define BV_LCDIF_CTRL_DATA_FORMAT_18_BIT__UPPER_18_BITS_VALID           0x1
+#define BF_LCDIF_CTRL_DATA_FORMAT_18_BIT(v)                             (((v) & 0x1) << 2)
+#define BFM_LCDIF_CTRL_DATA_FORMAT_18_BIT(v)                            BM_LCDIF_CTRL_DATA_FORMAT_18_BIT
+#define BF_LCDIF_CTRL_DATA_FORMAT_18_BIT_V(e)                           BF_LCDIF_CTRL_DATA_FORMAT_18_BIT(BV_LCDIF_CTRL_DATA_FORMAT_18_BIT__##e)
+#define BFM_LCDIF_CTRL_DATA_FORMAT_18_BIT_V(v)                          BM_LCDIF_CTRL_DATA_FORMAT_18_BIT
+#define BP_LCDIF_CTRL_DATA_FORMAT_24_BIT                                1
+#define BM_LCDIF_CTRL_DATA_FORMAT_24_BIT                                0x2
+#define BV_LCDIF_CTRL_DATA_FORMAT_24_BIT__ALL_24_BITS_VALID             0x0
+#define BV_LCDIF_CTRL_DATA_FORMAT_24_BIT__DROP_UPPER_2_BITS_PER_BYTE    0x1
+#define BF_LCDIF_CTRL_DATA_FORMAT_24_BIT(v)                             (((v) & 0x1) << 1)
+#define BFM_LCDIF_CTRL_DATA_FORMAT_24_BIT(v)                            BM_LCDIF_CTRL_DATA_FORMAT_24_BIT
+#define BF_LCDIF_CTRL_DATA_FORMAT_24_BIT_V(e)                           BF_LCDIF_CTRL_DATA_FORMAT_24_BIT(BV_LCDIF_CTRL_DATA_FORMAT_24_BIT__##e)
+#define BFM_LCDIF_CTRL_DATA_FORMAT_24_BIT_V(v)                          BM_LCDIF_CTRL_DATA_FORMAT_24_BIT
+#define BP_LCDIF_CTRL_RUN                                               0
+#define BM_LCDIF_CTRL_RUN                                               0x1
+#define BF_LCDIF_CTRL_RUN(v)                                            (((v) & 0x1) << 0)
+#define BFM_LCDIF_CTRL_RUN(v)                                           BM_LCDIF_CTRL_RUN
+#define BF_LCDIF_CTRL_RUN_V(e)                                          BF_LCDIF_CTRL_RUN(BV_LCDIF_CTRL_RUN__##e)
+#define BFM_LCDIF_CTRL_RUN_V(v)                                         BM_LCDIF_CTRL_RUN
+
+#define HW_LCDIF_CTRL1                                          HW(LCDIF_CTRL1)
+#define HWA_LCDIF_CTRL1                                         (0x80030000 + 0x10)
+#define HWT_LCDIF_CTRL1                                         HWIO_32_RW
+#define HWN_LCDIF_CTRL1                                         LCDIF_CTRL1
+#define HWI_LCDIF_CTRL1                                         
+#define HW_LCDIF_CTRL1_SET                                      HW(LCDIF_CTRL1_SET)
+#define HWA_LCDIF_CTRL1_SET                                     (HWA_LCDIF_CTRL1 + 0x4)
+#define HWT_LCDIF_CTRL1_SET                                     HWIO_32_WO
+#define HWN_LCDIF_CTRL1_SET                                     LCDIF_CTRL1
+#define HWI_LCDIF_CTRL1_SET                                     
+#define HW_LCDIF_CTRL1_CLR                                      HW(LCDIF_CTRL1_CLR)
+#define HWA_LCDIF_CTRL1_CLR                                     (HWA_LCDIF_CTRL1 + 0x8)
+#define HWT_LCDIF_CTRL1_CLR                                     HWIO_32_WO
+#define HWN_LCDIF_CTRL1_CLR                                     LCDIF_CTRL1
+#define HWI_LCDIF_CTRL1_CLR                                     
+#define HW_LCDIF_CTRL1_TOG                                      HW(LCDIF_CTRL1_TOG)
+#define HWA_LCDIF_CTRL1_TOG                                     (HWA_LCDIF_CTRL1 + 0xc)
+#define HWT_LCDIF_CTRL1_TOG                                     HWIO_32_WO
+#define HWN_LCDIF_CTRL1_TOG                                     LCDIF_CTRL1
+#define HWI_LCDIF_CTRL1_TOG                                     
+#define BP_LCDIF_CTRL1_RSRVD1                                   27
+#define BM_LCDIF_CTRL1_RSRVD1                                   0xf8000000
+#define BF_LCDIF_CTRL1_RSRVD1(v)                                (((v) & 0x1f) << 27)
+#define BFM_LCDIF_CTRL1_RSRVD1(v)                               BM_LCDIF_CTRL1_RSRVD1
+#define BF_LCDIF_CTRL1_RSRVD1_V(e)                              BF_LCDIF_CTRL1_RSRVD1(BV_LCDIF_CTRL1_RSRVD1__##e)
+#define BFM_LCDIF_CTRL1_RSRVD1_V(v)                             BM_LCDIF_CTRL1_RSRVD1
+#define BP_LCDIF_CTRL1_BM_ERROR_IRQ_EN                          26
+#define BM_LCDIF_CTRL1_BM_ERROR_IRQ_EN                          0x4000000
+#define BF_LCDIF_CTRL1_BM_ERROR_IRQ_EN(v)                       (((v) & 0x1) << 26)
+#define BFM_LCDIF_CTRL1_BM_ERROR_IRQ_EN(v)                      BM_LCDIF_CTRL1_BM_ERROR_IRQ_EN
+#define BF_LCDIF_CTRL1_BM_ERROR_IRQ_EN_V(e)                     BF_LCDIF_CTRL1_BM_ERROR_IRQ_EN(BV_LCDIF_CTRL1_BM_ERROR_IRQ_EN__##e)
+#define BFM_LCDIF_CTRL1_BM_ERROR_IRQ_EN_V(v)                    BM_LCDIF_CTRL1_BM_ERROR_IRQ_EN
+#define BP_LCDIF_CTRL1_BM_ERROR_IRQ                             25
+#define BM_LCDIF_CTRL1_BM_ERROR_IRQ                             0x2000000
+#define BV_LCDIF_CTRL1_BM_ERROR_IRQ__NO_REQUEST                 0x0
+#define BV_LCDIF_CTRL1_BM_ERROR_IRQ__REQUEST                    0x1
+#define BF_LCDIF_CTRL1_BM_ERROR_IRQ(v)                          (((v) & 0x1) << 25)
+#define BFM_LCDIF_CTRL1_BM_ERROR_IRQ(v)                         BM_LCDIF_CTRL1_BM_ERROR_IRQ
+#define BF_LCDIF_CTRL1_BM_ERROR_IRQ_V(e)                        BF_LCDIF_CTRL1_BM_ERROR_IRQ(BV_LCDIF_CTRL1_BM_ERROR_IRQ__##e)
+#define BFM_LCDIF_CTRL1_BM_ERROR_IRQ_V(v)                       BM_LCDIF_CTRL1_BM_ERROR_IRQ
+#define BP_LCDIF_CTRL1_RECOVER_ON_UNDERFLOW                     24
+#define BM_LCDIF_CTRL1_RECOVER_ON_UNDERFLOW                     0x1000000
+#define BF_LCDIF_CTRL1_RECOVER_ON_UNDERFLOW(v)                  (((v) & 0x1) << 24)
+#define BFM_LCDIF_CTRL1_RECOVER_ON_UNDERFLOW(v)                 BM_LCDIF_CTRL1_RECOVER_ON_UNDERFLOW
+#define BF_LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_V(e)                BF_LCDIF_CTRL1_RECOVER_ON_UNDERFLOW(BV_LCDIF_CTRL1_RECOVER_ON_UNDERFLOW__##e)
+#define BFM_LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_V(v)               BM_LCDIF_CTRL1_RECOVER_ON_UNDERFLOW
+#define BP_LCDIF_CTRL1_INTERLACE_FIELDS                         23
+#define BM_LCDIF_CTRL1_INTERLACE_FIELDS                         0x800000
+#define BF_LCDIF_CTRL1_INTERLACE_FIELDS(v)                      (((v) & 0x1) << 23)
+#define BFM_LCDIF_CTRL1_INTERLACE_FIELDS(v)                     BM_LCDIF_CTRL1_INTERLACE_FIELDS
+#define BF_LCDIF_CTRL1_INTERLACE_FIELDS_V(e)                    BF_LCDIF_CTRL1_INTERLACE_FIELDS(BV_LCDIF_CTRL1_INTERLACE_FIELDS__##e)
+#define BFM_LCDIF_CTRL1_INTERLACE_FIELDS_V(v)                   BM_LCDIF_CTRL1_INTERLACE_FIELDS
+#define BP_LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD        22
+#define BM_LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD        0x400000
+#define BF_LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD(v)     (((v) & 0x1) << 22)
+#define BFM_LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD(v)    BM_LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD
+#define BF_LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_V(e)   BF_LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD(BV_LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD__##e)
+#define BFM_LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_V(v)  BM_LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD
+#define BP_LCDIF_CTRL1_FIFO_CLEAR                               21
+#define BM_LCDIF_CTRL1_FIFO_CLEAR                               0x200000
+#define BF_LCDIF_CTRL1_FIFO_CLEAR(v)                            (((v) & 0x1) << 21)
+#define BFM_LCDIF_CTRL1_FIFO_CLEAR(v)                           BM_LCDIF_CTRL1_FIFO_CLEAR
+#define BF_LCDIF_CTRL1_FIFO_CLEAR_V(e)                          BF_LCDIF_CTRL1_FIFO_CLEAR(BV_LCDIF_CTRL1_FIFO_CLEAR__##e)
+#define BFM_LCDIF_CTRL1_FIFO_CLEAR_V(v)                         BM_LCDIF_CTRL1_FIFO_CLEAR
+#define BP_LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS                  20
+#define BM_LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS                  0x100000
+#define BF_LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS(v)               (((v) & 0x1) << 20)
+#define BFM_LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS(v)              BM_LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS
+#define BF_LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_V(e)             BF_LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS(BV_LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS__##e)
+#define BFM_LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_V(v)            BM_LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS
+#define BP_LCDIF_CTRL1_BYTE_PACKING_FORMAT                      16
+#define BM_LCDIF_CTRL1_BYTE_PACKING_FORMAT                      0xf0000
+#define BF_LCDIF_CTRL1_BYTE_PACKING_FORMAT(v)                   (((v) & 0xf) << 16)
+#define BFM_LCDIF_CTRL1_BYTE_PACKING_FORMAT(v)                  BM_LCDIF_CTRL1_BYTE_PACKING_FORMAT
+#define BF_LCDIF_CTRL1_BYTE_PACKING_FORMAT_V(e)                 BF_LCDIF_CTRL1_BYTE_PACKING_FORMAT(BV_LCDIF_CTRL1_BYTE_PACKING_FORMAT__##e)
+#define BFM_LCDIF_CTRL1_BYTE_PACKING_FORMAT_V(v)                BM_LCDIF_CTRL1_BYTE_PACKING_FORMAT
+#define BP_LCDIF_CTRL1_OVERFLOW_IRQ_EN                          15
+#define BM_LCDIF_CTRL1_OVERFLOW_IRQ_EN                          0x8000
+#define BF_LCDIF_CTRL1_OVERFLOW_IRQ_EN(v)                       (((v) & 0x1) << 15)
+#define BFM_LCDIF_CTRL1_OVERFLOW_IRQ_EN(v)                      BM_LCDIF_CTRL1_OVERFLOW_IRQ_EN
+#define BF_LCDIF_CTRL1_OVERFLOW_IRQ_EN_V(e)                     BF_LCDIF_CTRL1_OVERFLOW_IRQ_EN(BV_LCDIF_CTRL1_OVERFLOW_IRQ_EN__##e)
+#define BFM_LCDIF_CTRL1_OVERFLOW_IRQ_EN_V(v)                    BM_LCDIF_CTRL1_OVERFLOW_IRQ_EN
+#define BP_LCDIF_CTRL1_UNDERFLOW_IRQ_EN                         14
+#define BM_LCDIF_CTRL1_UNDERFLOW_IRQ_EN                         0x4000
+#define BF_LCDIF_CTRL1_UNDERFLOW_IRQ_EN(v)                      (((v) & 0x1) << 14)
+#define BFM_LCDIF_CTRL1_UNDERFLOW_IRQ_EN(v)                     BM_LCDIF_CTRL1_UNDERFLOW_IRQ_EN
+#define BF_LCDIF_CTRL1_UNDERFLOW_IRQ_EN_V(e)                    BF_LCDIF_CTRL1_UNDERFLOW_IRQ_EN(BV_LCDIF_CTRL1_UNDERFLOW_IRQ_EN__##e)
+#define BFM_LCDIF_CTRL1_UNDERFLOW_IRQ_EN_V(v)                   BM_LCDIF_CTRL1_UNDERFLOW_IRQ_EN
+#define BP_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN                    13
+#define BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN                    0x2000
+#define BF_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN(v)                 (((v) & 0x1) << 13)
+#define BFM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN(v)                BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN
+#define BF_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_V(e)               BF_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN(BV_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN__##e)
+#define BFM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_V(v)              BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN
+#define BP_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN                        12
+#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN                        0x1000
+#define BF_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN(v)                     (((v) & 0x1) << 12)
+#define BFM_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN(v)                    BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN
+#define BF_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_V(e)                   BF_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN(BV_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN__##e)
+#define BFM_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_V(v)                  BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN
+#define BP_LCDIF_CTRL1_OVERFLOW_IRQ                             11
+#define BM_LCDIF_CTRL1_OVERFLOW_IRQ                             0x800
+#define BV_LCDIF_CTRL1_OVERFLOW_IRQ__NO_REQUEST                 0x0
+#define BV_LCDIF_CTRL1_OVERFLOW_IRQ__REQUEST                    0x1
+#define BF_LCDIF_CTRL1_OVERFLOW_IRQ(v)                          (((v) & 0x1) << 11)
+#define BFM_LCDIF_CTRL1_OVERFLOW_IRQ(v)                         BM_LCDIF_CTRL1_OVERFLOW_IRQ
+#define BF_LCDIF_CTRL1_OVERFLOW_IRQ_V(e)                        BF_LCDIF_CTRL1_OVERFLOW_IRQ(BV_LCDIF_CTRL1_OVERFLOW_IRQ__##e)
+#define BFM_LCDIF_CTRL1_OVERFLOW_IRQ_V(v)                       BM_LCDIF_CTRL1_OVERFLOW_IRQ
+#define BP_LCDIF_CTRL1_UNDERFLOW_IRQ                            10
+#define BM_LCDIF_CTRL1_UNDERFLOW_IRQ                            0x400
+#define BV_LCDIF_CTRL1_UNDERFLOW_IRQ__NO_REQUEST                0x0
+#define BV_LCDIF_CTRL1_UNDERFLOW_IRQ__REQUEST                   0x1
+#define BF_LCDIF_CTRL1_UNDERFLOW_IRQ(v)                         (((v) & 0x1) << 10)
+#define BFM_LCDIF_CTRL1_UNDERFLOW_IRQ(v)                        BM_LCDIF_CTRL1_UNDERFLOW_IRQ
+#define BF_LCDIF_CTRL1_UNDERFLOW_IRQ_V(e)                       BF_LCDIF_CTRL1_UNDERFLOW_IRQ(BV_LCDIF_CTRL1_UNDERFLOW_IRQ__##e)
+#define BFM_LCDIF_CTRL1_UNDERFLOW_IRQ_V(v)                      BM_LCDIF_CTRL1_UNDERFLOW_IRQ
+#define BP_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ                       9
+#define BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ                       0x200
+#define BV_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ__NO_REQUEST           0x0
+#define BV_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ__REQUEST              0x1
+#define BF_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ(v)                    (((v) & 0x1) << 9)
+#define BFM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ(v)                   BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ
+#define BF_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_V(e)                  BF_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ(BV_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ__##e)
+#define BFM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_V(v)                 BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ
+#define BP_LCDIF_CTRL1_VSYNC_EDGE_IRQ                           8
+#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ                           0x100
+#define BV_LCDIF_CTRL1_VSYNC_EDGE_IRQ__NO_REQUEST               0x0
+#define BV_LCDIF_CTRL1_VSYNC_EDGE_IRQ__REQUEST                  0x1
+#define BF_LCDIF_CTRL1_VSYNC_EDGE_IRQ(v)                        (((v) & 0x1) << 8)
+#define BFM_LCDIF_CTRL1_VSYNC_EDGE_IRQ(v)                       BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ
+#define BF_LCDIF_CTRL1_VSYNC_EDGE_IRQ_V(e)                      BF_LCDIF_CTRL1_VSYNC_EDGE_IRQ(BV_LCDIF_CTRL1_VSYNC_EDGE_IRQ__##e)
+#define BFM_LCDIF_CTRL1_VSYNC_EDGE_IRQ_V(v)                     BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ
+#define BP_LCDIF_CTRL1_RSRVD0                                   7
+#define BM_LCDIF_CTRL1_RSRVD0                                   0x80
+#define BF_LCDIF_CTRL1_RSRVD0(v)                                (((v) & 0x1) << 7)
+#define BFM_LCDIF_CTRL1_RSRVD0(v)                               BM_LCDIF_CTRL1_RSRVD0
+#define BF_LCDIF_CTRL1_RSRVD0_V(e)                              BF_LCDIF_CTRL1_RSRVD0(BV_LCDIF_CTRL1_RSRVD0__##e)
+#define BFM_LCDIF_CTRL1_RSRVD0_V(v)                             BM_LCDIF_CTRL1_RSRVD0
+#define BP_LCDIF_CTRL1_PAUSE_TRANSFER                           6
+#define BM_LCDIF_CTRL1_PAUSE_TRANSFER                           0x40
+#define BF_LCDIF_CTRL1_PAUSE_TRANSFER(v)                        (((v) & 0x1) << 6)
+#define BFM_LCDIF_CTRL1_PAUSE_TRANSFER(v)                       BM_LCDIF_CTRL1_PAUSE_TRANSFER
+#define BF_LCDIF_CTRL1_PAUSE_TRANSFER_V(e)                      BF_LCDIF_CTRL1_PAUSE_TRANSFER(BV_LCDIF_CTRL1_PAUSE_TRANSFER__##e)
+#define BFM_LCDIF_CTRL1_PAUSE_TRANSFER_V(v)                     BM_LCDIF_CTRL1_PAUSE_TRANSFER
+#define BP_LCDIF_CTRL1_PAUSE_TRANSFER_IRQ_EN                    5
+#define BM_LCDIF_CTRL1_PAUSE_TRANSFER_IRQ_EN                    0x20
+#define BF_LCDIF_CTRL1_PAUSE_TRANSFER_IRQ_EN(v)                 (((v) & 0x1) << 5)
+#define BFM_LCDIF_CTRL1_PAUSE_TRANSFER_IRQ_EN(v)                BM_LCDIF_CTRL1_PAUSE_TRANSFER_IRQ_EN
+#define BF_LCDIF_CTRL1_PAUSE_TRANSFER_IRQ_EN_V(e)               BF_LCDIF_CTRL1_PAUSE_TRANSFER_IRQ_EN(BV_LCDIF_CTRL1_PAUSE_TRANSFER_IRQ_EN__##e)
+#define BFM_LCDIF_CTRL1_PAUSE_TRANSFER_IRQ_EN_V(v)              BM_LCDIF_CTRL1_PAUSE_TRANSFER_IRQ_EN
+#define BP_LCDIF_CTRL1_PAUSE_TRANSFER_IRQ                       4
+#define BM_LCDIF_CTRL1_PAUSE_TRANSFER_IRQ                       0x10
+#define BV_LCDIF_CTRL1_PAUSE_TRANSFER_IRQ__NO_REQUEST           0x0
+#define BV_LCDIF_CTRL1_PAUSE_TRANSFER_IRQ__REQUEST              0x1
+#define BF_LCDIF_CTRL1_PAUSE_TRANSFER_IRQ(v)                    (((v) & 0x1) << 4)
+#define BFM_LCDIF_CTRL1_PAUSE_TRANSFER_IRQ(v)                   BM_LCDIF_CTRL1_PAUSE_TRANSFER_IRQ
+#define BF_LCDIF_CTRL1_PAUSE_TRANSFER_IRQ_V(e)                  BF_LCDIF_CTRL1_PAUSE_TRANSFER_IRQ(BV_LCDIF_CTRL1_PAUSE_TRANSFER_IRQ__##e)
+#define BFM_LCDIF_CTRL1_PAUSE_TRANSFER_IRQ_V(v)                 BM_LCDIF_CTRL1_PAUSE_TRANSFER_IRQ
+#define BP_LCDIF_CTRL1_LCD_CS_CTRL                              3
+#define BM_LCDIF_CTRL1_LCD_CS_CTRL                              0x8
+#define BF_LCDIF_CTRL1_LCD_CS_CTRL(v)                           (((v) & 0x1) << 3)
+#define BFM_LCDIF_CTRL1_LCD_CS_CTRL(v)                          BM_LCDIF_CTRL1_LCD_CS_CTRL
+#define BF_LCDIF_CTRL1_LCD_CS_CTRL_V(e)                         BF_LCDIF_CTRL1_LCD_CS_CTRL(BV_LCDIF_CTRL1_LCD_CS_CTRL__##e)
+#define BFM_LCDIF_CTRL1_LCD_CS_CTRL_V(v)                        BM_LCDIF_CTRL1_LCD_CS_CTRL
+#define BP_LCDIF_CTRL1_BUSY_ENABLE                              2
+#define BM_LCDIF_CTRL1_BUSY_ENABLE                              0x4
+#define BV_LCDIF_CTRL1_BUSY_ENABLE__BUSY_DISABLED               0x0
+#define BV_LCDIF_CTRL1_BUSY_ENABLE__BUSY_ENABLED                0x1
+#define BF_LCDIF_CTRL1_BUSY_ENABLE(v)                           (((v) & 0x1) << 2)
+#define BFM_LCDIF_CTRL1_BUSY_ENABLE(v)                          BM_LCDIF_CTRL1_BUSY_ENABLE
+#define BF_LCDIF_CTRL1_BUSY_ENABLE_V(e)                         BF_LCDIF_CTRL1_BUSY_ENABLE(BV_LCDIF_CTRL1_BUSY_ENABLE__##e)
+#define BFM_LCDIF_CTRL1_BUSY_ENABLE_V(v)                        BM_LCDIF_CTRL1_BUSY_ENABLE
+#define BP_LCDIF_CTRL1_MODE86                                   1
+#define BM_LCDIF_CTRL1_MODE86                                   0x2
+#define BV_LCDIF_CTRL1_MODE86__8080_MODE                        0x0
+#define BV_LCDIF_CTRL1_MODE86__6800_MODE                        0x1
+#define BF_LCDIF_CTRL1_MODE86(v)                                (((v) & 0x1) << 1)
+#define BFM_LCDIF_CTRL1_MODE86(v)                               BM_LCDIF_CTRL1_MODE86
+#define BF_LCDIF_CTRL1_MODE86_V(e)                              BF_LCDIF_CTRL1_MODE86(BV_LCDIF_CTRL1_MODE86__##e)
+#define BFM_LCDIF_CTRL1_MODE86_V(v)                             BM_LCDIF_CTRL1_MODE86
+#define BP_LCDIF_CTRL1_RESET                                    0
+#define BM_LCDIF_CTRL1_RESET                                    0x1
+#define BV_LCDIF_CTRL1_RESET__LCDRESET_LOW                      0x0
+#define BV_LCDIF_CTRL1_RESET__LCDRESET_HIGH                     0x1
+#define BF_LCDIF_CTRL1_RESET(v)                                 (((v) & 0x1) << 0)
+#define BFM_LCDIF_CTRL1_RESET(v)                                BM_LCDIF_CTRL1_RESET
+#define BF_LCDIF_CTRL1_RESET_V(e)                               BF_LCDIF_CTRL1_RESET(BV_LCDIF_CTRL1_RESET__##e)
+#define BFM_LCDIF_CTRL1_RESET_V(v)                              BM_LCDIF_CTRL1_RESET
+
+#define HW_LCDIF_TRANSFER_COUNT                 HW(LCDIF_TRANSFER_COUNT)
+#define HWA_LCDIF_TRANSFER_COUNT                (0x80030000 + 0x20)
+#define HWT_LCDIF_TRANSFER_COUNT                HWIO_32_RW
+#define HWN_LCDIF_TRANSFER_COUNT                LCDIF_TRANSFER_COUNT
+#define HWI_LCDIF_TRANSFER_COUNT                
+#define BP_LCDIF_TRANSFER_COUNT_V_COUNT         16
+#define BM_LCDIF_TRANSFER_COUNT_V_COUNT         0xffff0000
+#define BF_LCDIF_TRANSFER_COUNT_V_COUNT(v)      (((v) & 0xffff) << 16)
+#define BFM_LCDIF_TRANSFER_COUNT_V_COUNT(v)     BM_LCDIF_TRANSFER_COUNT_V_COUNT
+#define BF_LCDIF_TRANSFER_COUNT_V_COUNT_V(e)    BF_LCDIF_TRANSFER_COUNT_V_COUNT(BV_LCDIF_TRANSFER_COUNT_V_COUNT__##e)
+#define BFM_LCDIF_TRANSFER_COUNT_V_COUNT_V(v)   BM_LCDIF_TRANSFER_COUNT_V_COUNT
+#define BP_LCDIF_TRANSFER_COUNT_H_COUNT         0
+#define BM_LCDIF_TRANSFER_COUNT_H_COUNT         0xffff
+#define BF_LCDIF_TRANSFER_COUNT_H_COUNT(v)      (((v) & 0xffff) << 0)
+#define BFM_LCDIF_TRANSFER_COUNT_H_COUNT(v)     BM_LCDIF_TRANSFER_COUNT_H_COUNT
+#define BF_LCDIF_TRANSFER_COUNT_H_COUNT_V(e)    BF_LCDIF_TRANSFER_COUNT_H_COUNT(BV_LCDIF_TRANSFER_COUNT_H_COUNT__##e)
+#define BFM_LCDIF_TRANSFER_COUNT_H_COUNT_V(v)   BM_LCDIF_TRANSFER_COUNT_H_COUNT
+
+#define HW_LCDIF_CUR_BUF            HW(LCDIF_CUR_BUF)
+#define HWA_LCDIF_CUR_BUF           (0x80030000 + 0x30)
+#define HWT_LCDIF_CUR_BUF           HWIO_32_RW
+#define HWN_LCDIF_CUR_BUF           LCDIF_CUR_BUF
+#define HWI_LCDIF_CUR_BUF           
+#define BP_LCDIF_CUR_BUF_ADDR       0
+#define BM_LCDIF_CUR_BUF_ADDR       0xffffffff
+#define BF_LCDIF_CUR_BUF_ADDR(v)    (((v) & 0xffffffff) << 0)
+#define BFM_LCDIF_CUR_BUF_ADDR(v)   BM_LCDIF_CUR_BUF_ADDR
+#define BF_LCDIF_CUR_BUF_ADDR_V(e)  BF_LCDIF_CUR_BUF_ADDR(BV_LCDIF_CUR_BUF_ADDR__##e)
+#define BFM_LCDIF_CUR_BUF_ADDR_V(v) BM_LCDIF_CUR_BUF_ADDR
+
+#define HW_LCDIF_NEXT_BUF               HW(LCDIF_NEXT_BUF)
+#define HWA_LCDIF_NEXT_BUF              (0x80030000 + 0x40)
+#define HWT_LCDIF_NEXT_BUF              HWIO_32_RW
+#define HWN_LCDIF_NEXT_BUF              LCDIF_NEXT_BUF
+#define HWI_LCDIF_NEXT_BUF              
+#define BP_LCDIF_NEXT_BUF_ADDR          0
+#define BM_LCDIF_NEXT_BUF_ADDR          0xffffffff
+#define BF_LCDIF_NEXT_BUF_ADDR(v)       (((v) & 0xffffffff) << 0)
+#define BFM_LCDIF_NEXT_BUF_ADDR(v)      BM_LCDIF_NEXT_BUF_ADDR
+#define BF_LCDIF_NEXT_BUF_ADDR_V(e)     BF_LCDIF_NEXT_BUF_ADDR(BV_LCDIF_NEXT_BUF_ADDR__##e)
+#define BFM_LCDIF_NEXT_BUF_ADDR_V(v)    BM_LCDIF_NEXT_BUF_ADDR
+
+#define HW_LCDIF_PAGETABLE              HW(LCDIF_PAGETABLE)
+#define HWA_LCDIF_PAGETABLE             (0x80030000 + 0x50)
+#define HWT_LCDIF_PAGETABLE             HWIO_32_RW
+#define HWN_LCDIF_PAGETABLE             LCDIF_PAGETABLE
+#define HWI_LCDIF_PAGETABLE             
+#define BP_LCDIF_PAGETABLE_BASE         14
+#define BM_LCDIF_PAGETABLE_BASE         0xffffc000
+#define BF_LCDIF_PAGETABLE_BASE(v)      (((v) & 0x3ffff) << 14)
+#define BFM_LCDIF_PAGETABLE_BASE(v)     BM_LCDIF_PAGETABLE_BASE
+#define BF_LCDIF_PAGETABLE_BASE_V(e)    BF_LCDIF_PAGETABLE_BASE(BV_LCDIF_PAGETABLE_BASE__##e)
+#define BFM_LCDIF_PAGETABLE_BASE_V(v)   BM_LCDIF_PAGETABLE_BASE
+#define BP_LCDIF_PAGETABLE_RSVD1        2
+#define BM_LCDIF_PAGETABLE_RSVD1        0x3ffc
+#define BF_LCDIF_PAGETABLE_RSVD1(v)     (((v) & 0xfff) << 2)
+#define BFM_LCDIF_PAGETABLE_RSVD1(v)    BM_LCDIF_PAGETABLE_RSVD1
+#define BF_LCDIF_PAGETABLE_RSVD1_V(e)   BF_LCDIF_PAGETABLE_RSVD1(BV_LCDIF_PAGETABLE_RSVD1__##e)
+#define BFM_LCDIF_PAGETABLE_RSVD1_V(v)  BM_LCDIF_PAGETABLE_RSVD1
+#define BP_LCDIF_PAGETABLE_FLUSH        1
+#define BM_LCDIF_PAGETABLE_FLUSH        0x2
+#define BF_LCDIF_PAGETABLE_FLUSH(v)     (((v) & 0x1) << 1)
+#define BFM_LCDIF_PAGETABLE_FLUSH(v)    BM_LCDIF_PAGETABLE_FLUSH
+#define BF_LCDIF_PAGETABLE_FLUSH_V(e)   BF_LCDIF_PAGETABLE_FLUSH(BV_LCDIF_PAGETABLE_FLUSH__##e)
+#define BFM_LCDIF_PAGETABLE_FLUSH_V(v)  BM_LCDIF_PAGETABLE_FLUSH
+#define BP_LCDIF_PAGETABLE_ENABLE       0
+#define BM_LCDIF_PAGETABLE_ENABLE       0x1
+#define BF_LCDIF_PAGETABLE_ENABLE(v)    (((v) & 0x1) << 0)
+#define BFM_LCDIF_PAGETABLE_ENABLE(v)   BM_LCDIF_PAGETABLE_ENABLE
+#define BF_LCDIF_PAGETABLE_ENABLE_V(e)  BF_LCDIF_PAGETABLE_ENABLE(BV_LCDIF_PAGETABLE_ENABLE__##e)
+#define BFM_LCDIF_PAGETABLE_ENABLE_V(v) BM_LCDIF_PAGETABLE_ENABLE
+
+#define HW_LCDIF_TIMING                     HW(LCDIF_TIMING)
+#define HWA_LCDIF_TIMING                    (0x80030000 + 0x60)
+#define HWT_LCDIF_TIMING                    HWIO_32_RW
+#define HWN_LCDIF_TIMING                    LCDIF_TIMING
+#define HWI_LCDIF_TIMING                    
+#define BP_LCDIF_TIMING_CMD_HOLD            24
+#define BM_LCDIF_TIMING_CMD_HOLD            0xff000000
+#define BF_LCDIF_TIMING_CMD_HOLD(v)         (((v) & 0xff) << 24)
+#define BFM_LCDIF_TIMING_CMD_HOLD(v)        BM_LCDIF_TIMING_CMD_HOLD
+#define BF_LCDIF_TIMING_CMD_HOLD_V(e)       BF_LCDIF_TIMING_CMD_HOLD(BV_LCDIF_TIMING_CMD_HOLD__##e)
+#define BFM_LCDIF_TIMING_CMD_HOLD_V(v)      BM_LCDIF_TIMING_CMD_HOLD
+#define BP_LCDIF_TIMING_CMD_SETUP           16
+#define BM_LCDIF_TIMING_CMD_SETUP           0xff0000
+#define BF_LCDIF_TIMING_CMD_SETUP(v)        (((v) & 0xff) << 16)
+#define BFM_LCDIF_TIMING_CMD_SETUP(v)       BM_LCDIF_TIMING_CMD_SETUP
+#define BF_LCDIF_TIMING_CMD_SETUP_V(e)      BF_LCDIF_TIMING_CMD_SETUP(BV_LCDIF_TIMING_CMD_SETUP__##e)
+#define BFM_LCDIF_TIMING_CMD_SETUP_V(v)     BM_LCDIF_TIMING_CMD_SETUP
+#define BP_LCDIF_TIMING_DATA_HOLD           8
+#define BM_LCDIF_TIMING_DATA_HOLD           0xff00
+#define BF_LCDIF_TIMING_DATA_HOLD(v)        (((v) & 0xff) << 8)
+#define BFM_LCDIF_TIMING_DATA_HOLD(v)       BM_LCDIF_TIMING_DATA_HOLD
+#define BF_LCDIF_TIMING_DATA_HOLD_V(e)      BF_LCDIF_TIMING_DATA_HOLD(BV_LCDIF_TIMING_DATA_HOLD__##e)
+#define BFM_LCDIF_TIMING_DATA_HOLD_V(v)     BM_LCDIF_TIMING_DATA_HOLD
+#define BP_LCDIF_TIMING_DATA_SETUP          0
+#define BM_LCDIF_TIMING_DATA_SETUP          0xff
+#define BF_LCDIF_TIMING_DATA_SETUP(v)       (((v) & 0xff) << 0)
+#define BFM_LCDIF_TIMING_DATA_SETUP(v)      BM_LCDIF_TIMING_DATA_SETUP
+#define BF_LCDIF_TIMING_DATA_SETUP_V(e)     BF_LCDIF_TIMING_DATA_SETUP(BV_LCDIF_TIMING_DATA_SETUP__##e)
+#define BFM_LCDIF_TIMING_DATA_SETUP_V(v)    BM_LCDIF_TIMING_DATA_SETUP
+
+#define HW_LCDIF_VDCTRL0                                HW(LCDIF_VDCTRL0)
+#define HWA_LCDIF_VDCTRL0                               (0x80030000 + 0x70)
+#define HWT_LCDIF_VDCTRL0                               HWIO_32_RW
+#define HWN_LCDIF_VDCTRL0                               LCDIF_VDCTRL0
+#define HWI_LCDIF_VDCTRL0                               
+#define HW_LCDIF_VDCTRL0_SET                            HW(LCDIF_VDCTRL0_SET)
+#define HWA_LCDIF_VDCTRL0_SET                           (HWA_LCDIF_VDCTRL0 + 0x4)
+#define HWT_LCDIF_VDCTRL0_SET                           HWIO_32_WO
+#define HWN_LCDIF_VDCTRL0_SET                           LCDIF_VDCTRL0
+#define HWI_LCDIF_VDCTRL0_SET                           
+#define HW_LCDIF_VDCTRL0_CLR                            HW(LCDIF_VDCTRL0_CLR)
+#define HWA_LCDIF_VDCTRL0_CLR                           (HWA_LCDIF_VDCTRL0 + 0x8)
+#define HWT_LCDIF_VDCTRL0_CLR                           HWIO_32_WO
+#define HWN_LCDIF_VDCTRL0_CLR                           LCDIF_VDCTRL0
+#define HWI_LCDIF_VDCTRL0_CLR                           
+#define HW_LCDIF_VDCTRL0_TOG                            HW(LCDIF_VDCTRL0_TOG)
+#define HWA_LCDIF_VDCTRL0_TOG                           (HWA_LCDIF_VDCTRL0 + 0xc)
+#define HWT_LCDIF_VDCTRL0_TOG                           HWIO_32_WO
+#define HWN_LCDIF_VDCTRL0_TOG                           LCDIF_VDCTRL0
+#define HWI_LCDIF_VDCTRL0_TOG                           
+#define BP_LCDIF_VDCTRL0_RSRVD2                         30
+#define BM_LCDIF_VDCTRL0_RSRVD2                         0xc0000000
+#define BF_LCDIF_VDCTRL0_RSRVD2(v)                      (((v) & 0x3) << 30)
+#define BFM_LCDIF_VDCTRL0_RSRVD2(v)                     BM_LCDIF_VDCTRL0_RSRVD2
+#define BF_LCDIF_VDCTRL0_RSRVD2_V(e)                    BF_LCDIF_VDCTRL0_RSRVD2(BV_LCDIF_VDCTRL0_RSRVD2__##e)
+#define BFM_LCDIF_VDCTRL0_RSRVD2_V(v)                   BM_LCDIF_VDCTRL0_RSRVD2
+#define BP_LCDIF_VDCTRL0_VSYNC_OEB                      29
+#define BM_LCDIF_VDCTRL0_VSYNC_OEB                      0x20000000
+#define BV_LCDIF_VDCTRL0_VSYNC_OEB__VSYNC_OUTPUT        0x0
+#define BV_LCDIF_VDCTRL0_VSYNC_OEB__VSYNC_INPUT         0x1
+#define BF_LCDIF_VDCTRL0_VSYNC_OEB(v)                   (((v) & 0x1) << 29)
+#define BFM_LCDIF_VDCTRL0_VSYNC_OEB(v)                  BM_LCDIF_VDCTRL0_VSYNC_OEB
+#define BF_LCDIF_VDCTRL0_VSYNC_OEB_V(e)                 BF_LCDIF_VDCTRL0_VSYNC_OEB(BV_LCDIF_VDCTRL0_VSYNC_OEB__##e)
+#define BFM_LCDIF_VDCTRL0_VSYNC_OEB_V(v)                BM_LCDIF_VDCTRL0_VSYNC_OEB
+#define BP_LCDIF_VDCTRL0_ENABLE_PRESENT                 28
+#define BM_LCDIF_VDCTRL0_ENABLE_PRESENT                 0x10000000
+#define BF_LCDIF_VDCTRL0_ENABLE_PRESENT(v)              (((v) & 0x1) << 28)
+#define BFM_LCDIF_VDCTRL0_ENABLE_PRESENT(v)             BM_LCDIF_VDCTRL0_ENABLE_PRESENT
+#define BF_LCDIF_VDCTRL0_ENABLE_PRESENT_V(e)            BF_LCDIF_VDCTRL0_ENABLE_PRESENT(BV_LCDIF_VDCTRL0_ENABLE_PRESENT__##e)
+#define BFM_LCDIF_VDCTRL0_ENABLE_PRESENT_V(v)           BM_LCDIF_VDCTRL0_ENABLE_PRESENT
+#define BP_LCDIF_VDCTRL0_VSYNC_POL                      27
+#define BM_LCDIF_VDCTRL0_VSYNC_POL                      0x8000000
+#define BF_LCDIF_VDCTRL0_VSYNC_POL(v)                   (((v) & 0x1) << 27)
+#define BFM_LCDIF_VDCTRL0_VSYNC_POL(v)                  BM_LCDIF_VDCTRL0_VSYNC_POL
+#define BF_LCDIF_VDCTRL0_VSYNC_POL_V(e)                 BF_LCDIF_VDCTRL0_VSYNC_POL(BV_LCDIF_VDCTRL0_VSYNC_POL__##e)
+#define BFM_LCDIF_VDCTRL0_VSYNC_POL_V(v)                BM_LCDIF_VDCTRL0_VSYNC_POL
+#define BP_LCDIF_VDCTRL0_HSYNC_POL                      26
+#define BM_LCDIF_VDCTRL0_HSYNC_POL                      0x4000000
+#define BF_LCDIF_VDCTRL0_HSYNC_POL(v)                   (((v) & 0x1) << 26)
+#define BFM_LCDIF_VDCTRL0_HSYNC_POL(v)                  BM_LCDIF_VDCTRL0_HSYNC_POL
+#define BF_LCDIF_VDCTRL0_HSYNC_POL_V(e)                 BF_LCDIF_VDCTRL0_HSYNC_POL(BV_LCDIF_VDCTRL0_HSYNC_POL__##e)
+#define BFM_LCDIF_VDCTRL0_HSYNC_POL_V(v)                BM_LCDIF_VDCTRL0_HSYNC_POL
+#define BP_LCDIF_VDCTRL0_DOTCLK_POL                     25
+#define BM_LCDIF_VDCTRL0_DOTCLK_POL                     0x2000000
+#define BF_LCDIF_VDCTRL0_DOTCLK_POL(v)                  (((v) & 0x1) << 25)
+#define BFM_LCDIF_VDCTRL0_DOTCLK_POL(v)                 BM_LCDIF_VDCTRL0_DOTCLK_POL
+#define BF_LCDIF_VDCTRL0_DOTCLK_POL_V(e)                BF_LCDIF_VDCTRL0_DOTCLK_POL(BV_LCDIF_VDCTRL0_DOTCLK_POL__##e)
+#define BFM_LCDIF_VDCTRL0_DOTCLK_POL_V(v)               BM_LCDIF_VDCTRL0_DOTCLK_POL
+#define BP_LCDIF_VDCTRL0_ENABLE_POL                     24
+#define BM_LCDIF_VDCTRL0_ENABLE_POL                     0x1000000
+#define BF_LCDIF_VDCTRL0_ENABLE_POL(v)                  (((v) & 0x1) << 24)
+#define BFM_LCDIF_VDCTRL0_ENABLE_POL(v)                 BM_LCDIF_VDCTRL0_ENABLE_POL
+#define BF_LCDIF_VDCTRL0_ENABLE_POL_V(e)                BF_LCDIF_VDCTRL0_ENABLE_POL(BV_LCDIF_VDCTRL0_ENABLE_POL__##e)
+#define BFM_LCDIF_VDCTRL0_ENABLE_POL_V(v)               BM_LCDIF_VDCTRL0_ENABLE_POL
+#define BP_LCDIF_VDCTRL0_RSRVD1                         22
+#define BM_LCDIF_VDCTRL0_RSRVD1                         0xc00000
+#define BF_LCDIF_VDCTRL0_RSRVD1(v)                      (((v) & 0x3) << 22)
+#define BFM_LCDIF_VDCTRL0_RSRVD1(v)                     BM_LCDIF_VDCTRL0_RSRVD1
+#define BF_LCDIF_VDCTRL0_RSRVD1_V(e)                    BF_LCDIF_VDCTRL0_RSRVD1(BV_LCDIF_VDCTRL0_RSRVD1__##e)
+#define BFM_LCDIF_VDCTRL0_RSRVD1_V(v)                   BM_LCDIF_VDCTRL0_RSRVD1
+#define BP_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT              21
+#define BM_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT              0x200000
+#define BF_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT(v)           (((v) & 0x1) << 21)
+#define BFM_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT(v)          BM_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT
+#define BF_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_V(e)         BF_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT(BV_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT__##e)
+#define BFM_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_V(v)        BM_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT
+#define BP_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT         20
+#define BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT         0x100000
+#define BF_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT(v)      (((v) & 0x1) << 20)
+#define BFM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT(v)     BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT
+#define BF_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_V(e)    BF_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT(BV_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT__##e)
+#define BFM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_V(v)   BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT
+#define BP_LCDIF_VDCTRL0_HALF_LINE                      19
+#define BM_LCDIF_VDCTRL0_HALF_LINE                      0x80000
+#define BF_LCDIF_VDCTRL0_HALF_LINE(v)                   (((v) & 0x1) << 19)
+#define BFM_LCDIF_VDCTRL0_HALF_LINE(v)                  BM_LCDIF_VDCTRL0_HALF_LINE
+#define BF_LCDIF_VDCTRL0_HALF_LINE_V(e)                 BF_LCDIF_VDCTRL0_HALF_LINE(BV_LCDIF_VDCTRL0_HALF_LINE__##e)
+#define BFM_LCDIF_VDCTRL0_HALF_LINE_V(v)                BM_LCDIF_VDCTRL0_HALF_LINE
+#define BP_LCDIF_VDCTRL0_HALF_LINE_MODE                 18
+#define BM_LCDIF_VDCTRL0_HALF_LINE_MODE                 0x40000
+#define BF_LCDIF_VDCTRL0_HALF_LINE_MODE(v)              (((v) & 0x1) << 18)
+#define BFM_LCDIF_VDCTRL0_HALF_LINE_MODE(v)             BM_LCDIF_VDCTRL0_HALF_LINE_MODE
+#define BF_LCDIF_VDCTRL0_HALF_LINE_MODE_V(e)            BF_LCDIF_VDCTRL0_HALF_LINE_MODE(BV_LCDIF_VDCTRL0_HALF_LINE_MODE__##e)
+#define BFM_LCDIF_VDCTRL0_HALF_LINE_MODE_V(v)           BM_LCDIF_VDCTRL0_HALF_LINE_MODE
+#define BP_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH              0
+#define BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH              0x3ffff
+#define BF_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH(v)           (((v) & 0x3ffff) << 0)
+#define BFM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH(v)          BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH
+#define BF_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_V(e)         BF_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH(BV_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH__##e)
+#define BFM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_V(v)        BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH
+
+#define HW_LCDIF_VDCTRL1                    HW(LCDIF_VDCTRL1)
+#define HWA_LCDIF_VDCTRL1                   (0x80030000 + 0x80)
+#define HWT_LCDIF_VDCTRL1                   HWIO_32_RW
+#define HWN_LCDIF_VDCTRL1                   LCDIF_VDCTRL1
+#define HWI_LCDIF_VDCTRL1                   
+#define BP_LCDIF_VDCTRL1_VSYNC_PERIOD       0
+#define BM_LCDIF_VDCTRL1_VSYNC_PERIOD       0xffffffff
+#define BF_LCDIF_VDCTRL1_VSYNC_PERIOD(v)    (((v) & 0xffffffff) << 0)
+#define BFM_LCDIF_VDCTRL1_VSYNC_PERIOD(v)   BM_LCDIF_VDCTRL1_VSYNC_PERIOD
+#define BF_LCDIF_VDCTRL1_VSYNC_PERIOD_V(e)  BF_LCDIF_VDCTRL1_VSYNC_PERIOD(BV_LCDIF_VDCTRL1_VSYNC_PERIOD__##e)
+#define BFM_LCDIF_VDCTRL1_VSYNC_PERIOD_V(v) BM_LCDIF_VDCTRL1_VSYNC_PERIOD
+
+#define HW_LCDIF_VDCTRL2                            HW(LCDIF_VDCTRL2)
+#define HWA_LCDIF_VDCTRL2                           (0x80030000 + 0x90)
+#define HWT_LCDIF_VDCTRL2                           HWIO_32_RW
+#define HWN_LCDIF_VDCTRL2                           LCDIF_VDCTRL2
+#define HWI_LCDIF_VDCTRL2                           
+#define BP_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH          24
+#define BM_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH          0xff000000
+#define BF_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(v)       (((v) & 0xff) << 24)
+#define BFM_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(v)      BM_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH
+#define BF_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_V(e)     BF_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(BV_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH__##e)
+#define BFM_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_V(v)    BM_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH
+#define BP_LCDIF_VDCTRL2_RSRVD0                     18
+#define BM_LCDIF_VDCTRL2_RSRVD0                     0xfc0000
+#define BF_LCDIF_VDCTRL2_RSRVD0(v)                  (((v) & 0x3f) << 18)
+#define BFM_LCDIF_VDCTRL2_RSRVD0(v)                 BM_LCDIF_VDCTRL2_RSRVD0
+#define BF_LCDIF_VDCTRL2_RSRVD0_V(e)                BF_LCDIF_VDCTRL2_RSRVD0(BV_LCDIF_VDCTRL2_RSRVD0__##e)
+#define BFM_LCDIF_VDCTRL2_RSRVD0_V(v)               BM_LCDIF_VDCTRL2_RSRVD0
+#define BP_LCDIF_VDCTRL2_HSYNC_PERIOD               0
+#define BM_LCDIF_VDCTRL2_HSYNC_PERIOD               0x3ffff
+#define BF_LCDIF_VDCTRL2_HSYNC_PERIOD(v)            (((v) & 0x3ffff) << 0)
+#define BFM_LCDIF_VDCTRL2_HSYNC_PERIOD(v)           BM_LCDIF_VDCTRL2_HSYNC_PERIOD
+#define BF_LCDIF_VDCTRL2_HSYNC_PERIOD_V(e)          BF_LCDIF_VDCTRL2_HSYNC_PERIOD(BV_LCDIF_VDCTRL2_HSYNC_PERIOD__##e)
+#define BFM_LCDIF_VDCTRL2_HSYNC_PERIOD_V(v)         BM_LCDIF_VDCTRL2_HSYNC_PERIOD
+
+#define HW_LCDIF_VDCTRL3                            HW(LCDIF_VDCTRL3)
+#define HWA_LCDIF_VDCTRL3                           (0x80030000 + 0xa0)
+#define HWT_LCDIF_VDCTRL3                           HWIO_32_RW
+#define HWN_LCDIF_VDCTRL3                           LCDIF_VDCTRL3
+#define HWI_LCDIF_VDCTRL3                           
+#define BP_LCDIF_VDCTRL3_RSRVD0                     30
+#define BM_LCDIF_VDCTRL3_RSRVD0                     0xc0000000
+#define BF_LCDIF_VDCTRL3_RSRVD0(v)                  (((v) & 0x3) << 30)
+#define BFM_LCDIF_VDCTRL3_RSRVD0(v)                 BM_LCDIF_VDCTRL3_RSRVD0
+#define BF_LCDIF_VDCTRL3_RSRVD0_V(e)                BF_LCDIF_VDCTRL3_RSRVD0(BV_LCDIF_VDCTRL3_RSRVD0__##e)
+#define BFM_LCDIF_VDCTRL3_RSRVD0_V(v)               BM_LCDIF_VDCTRL3_RSRVD0
+#define BP_LCDIF_VDCTRL3_MUX_SYNC_SIGNALS           29
+#define BM_LCDIF_VDCTRL3_MUX_SYNC_SIGNALS           0x20000000
+#define BF_LCDIF_VDCTRL3_MUX_SYNC_SIGNALS(v)        (((v) & 0x1) << 29)
+#define BFM_LCDIF_VDCTRL3_MUX_SYNC_SIGNALS(v)       BM_LCDIF_VDCTRL3_MUX_SYNC_SIGNALS
+#define BF_LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_V(e)      BF_LCDIF_VDCTRL3_MUX_SYNC_SIGNALS(BV_LCDIF_VDCTRL3_MUX_SYNC_SIGNALS__##e)
+#define BFM_LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_V(v)     BM_LCDIF_VDCTRL3_MUX_SYNC_SIGNALS
+#define BP_LCDIF_VDCTRL3_VSYNC_ONLY                 28
+#define BM_LCDIF_VDCTRL3_VSYNC_ONLY                 0x10000000
+#define BF_LCDIF_VDCTRL3_VSYNC_ONLY(v)              (((v) & 0x1) << 28)
+#define BFM_LCDIF_VDCTRL3_VSYNC_ONLY(v)             BM_LCDIF_VDCTRL3_VSYNC_ONLY
+#define BF_LCDIF_VDCTRL3_VSYNC_ONLY_V(e)            BF_LCDIF_VDCTRL3_VSYNC_ONLY(BV_LCDIF_VDCTRL3_VSYNC_ONLY__##e)
+#define BFM_LCDIF_VDCTRL3_VSYNC_ONLY_V(v)           BM_LCDIF_VDCTRL3_VSYNC_ONLY
+#define BP_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT        16
+#define BM_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT        0xfff0000
+#define BF_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(v)     (((v) & 0xfff) << 16)
+#define BFM_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(v)    BM_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT
+#define BF_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_V(e)   BF_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(BV_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT__##e)
+#define BFM_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_V(v)  BM_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT
+#define BP_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT          0
+#define BM_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT          0xffff
+#define BF_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT(v)       (((v) & 0xffff) << 0)
+#define BFM_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT(v)      BM_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT
+#define BF_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_V(e)     BF_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT(BV_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT__##e)
+#define BFM_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_V(v)    BM_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT
+
+#define HW_LCDIF_VDCTRL4                                HW(LCDIF_VDCTRL4)
+#define HWA_LCDIF_VDCTRL4                               (0x80030000 + 0xb0)
+#define HWT_LCDIF_VDCTRL4                               HWIO_32_RW
+#define HWN_LCDIF_VDCTRL4                               LCDIF_VDCTRL4
+#define HWI_LCDIF_VDCTRL4                               
+#define BP_LCDIF_VDCTRL4_RSRVD0                         19
+#define BM_LCDIF_VDCTRL4_RSRVD0                         0xfff80000
+#define BF_LCDIF_VDCTRL4_RSRVD0(v)                      (((v) & 0x1fff) << 19)
+#define BFM_LCDIF_VDCTRL4_RSRVD0(v)                     BM_LCDIF_VDCTRL4_RSRVD0
+#define BF_LCDIF_VDCTRL4_RSRVD0_V(e)                    BF_LCDIF_VDCTRL4_RSRVD0(BV_LCDIF_VDCTRL4_RSRVD0__##e)
+#define BFM_LCDIF_VDCTRL4_RSRVD0_V(v)                   BM_LCDIF_VDCTRL4_RSRVD0
+#define BP_LCDIF_VDCTRL4_SYNC_SIGNALS_ON                18
+#define BM_LCDIF_VDCTRL4_SYNC_SIGNALS_ON                0x40000
+#define BF_LCDIF_VDCTRL4_SYNC_SIGNALS_ON(v)             (((v) & 0x1) << 18)
+#define BFM_LCDIF_VDCTRL4_SYNC_SIGNALS_ON(v)            BM_LCDIF_VDCTRL4_SYNC_SIGNALS_ON
+#define BF_LCDIF_VDCTRL4_SYNC_SIGNALS_ON_V(e)           BF_LCDIF_VDCTRL4_SYNC_SIGNALS_ON(BV_LCDIF_VDCTRL4_SYNC_SIGNALS_ON__##e)
+#define BFM_LCDIF_VDCTRL4_SYNC_SIGNALS_ON_V(v)          BM_LCDIF_VDCTRL4_SYNC_SIGNALS_ON
+#define BP_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT        0
+#define BM_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT        0x3ffff
+#define BF_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(v)     (((v) & 0x3ffff) << 0)
+#define BFM_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(v)    BM_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT
+#define BF_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_V(e)   BF_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(BV_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT__##e)
+#define BFM_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_V(v)  BM_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT
+
+#define HW_LCDIF_DVICTRL0                       HW(LCDIF_DVICTRL0)
+#define HWA_LCDIF_DVICTRL0                      (0x80030000 + 0xc0)
+#define HWT_LCDIF_DVICTRL0                      HWIO_32_RW
+#define HWN_LCDIF_DVICTRL0                      LCDIF_DVICTRL0
+#define HWI_LCDIF_DVICTRL0                      
+#define BP_LCDIF_DVICTRL0_START_TRS             31
+#define BM_LCDIF_DVICTRL0_START_TRS             0x80000000
+#define BF_LCDIF_DVICTRL0_START_TRS(v)          (((v) & 0x1) << 31)
+#define BFM_LCDIF_DVICTRL0_START_TRS(v)         BM_LCDIF_DVICTRL0_START_TRS
+#define BF_LCDIF_DVICTRL0_START_TRS_V(e)        BF_LCDIF_DVICTRL0_START_TRS(BV_LCDIF_DVICTRL0_START_TRS__##e)
+#define BFM_LCDIF_DVICTRL0_START_TRS_V(v)       BM_LCDIF_DVICTRL0_START_TRS
+#define BP_LCDIF_DVICTRL0_H_ACTIVE_CNT          20
+#define BM_LCDIF_DVICTRL0_H_ACTIVE_CNT          0x7ff00000
+#define BF_LCDIF_DVICTRL0_H_ACTIVE_CNT(v)       (((v) & 0x7ff) << 20)
+#define BFM_LCDIF_DVICTRL0_H_ACTIVE_CNT(v)      BM_LCDIF_DVICTRL0_H_ACTIVE_CNT
+#define BF_LCDIF_DVICTRL0_H_ACTIVE_CNT_V(e)     BF_LCDIF_DVICTRL0_H_ACTIVE_CNT(BV_LCDIF_DVICTRL0_H_ACTIVE_CNT__##e)
+#define BFM_LCDIF_DVICTRL0_H_ACTIVE_CNT_V(v)    BM_LCDIF_DVICTRL0_H_ACTIVE_CNT
+#define BP_LCDIF_DVICTRL0_H_BLANKING_CNT        10
+#define BM_LCDIF_DVICTRL0_H_BLANKING_CNT        0xffc00
+#define BF_LCDIF_DVICTRL0_H_BLANKING_CNT(v)     (((v) & 0x3ff) << 10)
+#define BFM_LCDIF_DVICTRL0_H_BLANKING_CNT(v)    BM_LCDIF_DVICTRL0_H_BLANKING_CNT
+#define BF_LCDIF_DVICTRL0_H_BLANKING_CNT_V(e)   BF_LCDIF_DVICTRL0_H_BLANKING_CNT(BV_LCDIF_DVICTRL0_H_BLANKING_CNT__##e)
+#define BFM_LCDIF_DVICTRL0_H_BLANKING_CNT_V(v)  BM_LCDIF_DVICTRL0_H_BLANKING_CNT
+#define BP_LCDIF_DVICTRL0_V_LINES_CNT           0
+#define BM_LCDIF_DVICTRL0_V_LINES_CNT           0x3ff
+#define BF_LCDIF_DVICTRL0_V_LINES_CNT(v)        (((v) & 0x3ff) << 0)
+#define BFM_LCDIF_DVICTRL0_V_LINES_CNT(v)       BM_LCDIF_DVICTRL0_V_LINES_CNT
+#define BF_LCDIF_DVICTRL0_V_LINES_CNT_V(e)      BF_LCDIF_DVICTRL0_V_LINES_CNT(BV_LCDIF_DVICTRL0_V_LINES_CNT__##e)
+#define BFM_LCDIF_DVICTRL0_V_LINES_CNT_V(v)     BM_LCDIF_DVICTRL0_V_LINES_CNT
+
+#define HW_LCDIF_DVICTRL1                       HW(LCDIF_DVICTRL1)
+#define HWA_LCDIF_DVICTRL1                      (0x80030000 + 0xd0)
+#define HWT_LCDIF_DVICTRL1                      HWIO_32_RW
+#define HWN_LCDIF_DVICTRL1                      LCDIF_DVICTRL1
+#define HWI_LCDIF_DVICTRL1                      
+#define BP_LCDIF_DVICTRL1_RSRVD0                30
+#define BM_LCDIF_DVICTRL1_RSRVD0                0xc0000000
+#define BF_LCDIF_DVICTRL1_RSRVD0(v)             (((v) & 0x3) << 30)
+#define BFM_LCDIF_DVICTRL1_RSRVD0(v)            BM_LCDIF_DVICTRL1_RSRVD0
+#define BF_LCDIF_DVICTRL1_RSRVD0_V(e)           BF_LCDIF_DVICTRL1_RSRVD0(BV_LCDIF_DVICTRL1_RSRVD0__##e)
+#define BFM_LCDIF_DVICTRL1_RSRVD0_V(v)          BM_LCDIF_DVICTRL1_RSRVD0
+#define BP_LCDIF_DVICTRL1_F1_START_LINE         20
+#define BM_LCDIF_DVICTRL1_F1_START_LINE         0x3ff00000
+#define BF_LCDIF_DVICTRL1_F1_START_LINE(v)      (((v) & 0x3ff) << 20)
+#define BFM_LCDIF_DVICTRL1_F1_START_LINE(v)     BM_LCDIF_DVICTRL1_F1_START_LINE
+#define BF_LCDIF_DVICTRL1_F1_START_LINE_V(e)    BF_LCDIF_DVICTRL1_F1_START_LINE(BV_LCDIF_DVICTRL1_F1_START_LINE__##e)
+#define BFM_LCDIF_DVICTRL1_F1_START_LINE_V(v)   BM_LCDIF_DVICTRL1_F1_START_LINE
+#define BP_LCDIF_DVICTRL1_F1_END_LINE           10
+#define BM_LCDIF_DVICTRL1_F1_END_LINE           0xffc00
+#define BF_LCDIF_DVICTRL1_F1_END_LINE(v)        (((v) & 0x3ff) << 10)
+#define BFM_LCDIF_DVICTRL1_F1_END_LINE(v)       BM_LCDIF_DVICTRL1_F1_END_LINE
+#define BF_LCDIF_DVICTRL1_F1_END_LINE_V(e)      BF_LCDIF_DVICTRL1_F1_END_LINE(BV_LCDIF_DVICTRL1_F1_END_LINE__##e)
+#define BFM_LCDIF_DVICTRL1_F1_END_LINE_V(v)     BM_LCDIF_DVICTRL1_F1_END_LINE
+#define BP_LCDIF_DVICTRL1_F2_START_LINE         0
+#define BM_LCDIF_DVICTRL1_F2_START_LINE         0x3ff
+#define BF_LCDIF_DVICTRL1_F2_START_LINE(v)      (((v) & 0x3ff) << 0)
+#define BFM_LCDIF_DVICTRL1_F2_START_LINE(v)     BM_LCDIF_DVICTRL1_F2_START_LINE
+#define BF_LCDIF_DVICTRL1_F2_START_LINE_V(e)    BF_LCDIF_DVICTRL1_F2_START_LINE(BV_LCDIF_DVICTRL1_F2_START_LINE__##e)
+#define BFM_LCDIF_DVICTRL1_F2_START_LINE_V(v)   BM_LCDIF_DVICTRL1_F2_START_LINE
+
+#define HW_LCDIF_DVICTRL2                           HW(LCDIF_DVICTRL2)
+#define HWA_LCDIF_DVICTRL2                          (0x80030000 + 0xe0)
+#define HWT_LCDIF_DVICTRL2                          HWIO_32_RW
+#define HWN_LCDIF_DVICTRL2                          LCDIF_DVICTRL2
+#define HWI_LCDIF_DVICTRL2                          
+#define BP_LCDIF_DVICTRL2_RSRVD0                    30
+#define BM_LCDIF_DVICTRL2_RSRVD0                    0xc0000000
+#define BF_LCDIF_DVICTRL2_RSRVD0(v)                 (((v) & 0x3) << 30)
+#define BFM_LCDIF_DVICTRL2_RSRVD0(v)                BM_LCDIF_DVICTRL2_RSRVD0
+#define BF_LCDIF_DVICTRL2_RSRVD0_V(e)               BF_LCDIF_DVICTRL2_RSRVD0(BV_LCDIF_DVICTRL2_RSRVD0__##e)
+#define BFM_LCDIF_DVICTRL2_RSRVD0_V(v)              BM_LCDIF_DVICTRL2_RSRVD0
+#define BP_LCDIF_DVICTRL2_F2_END_LINE               20
+#define BM_LCDIF_DVICTRL2_F2_END_LINE               0x3ff00000
+#define BF_LCDIF_DVICTRL2_F2_END_LINE(v)            (((v) & 0x3ff) << 20)
+#define BFM_LCDIF_DVICTRL2_F2_END_LINE(v)           BM_LCDIF_DVICTRL2_F2_END_LINE
+#define BF_LCDIF_DVICTRL2_F2_END_LINE_V(e)          BF_LCDIF_DVICTRL2_F2_END_LINE(BV_LCDIF_DVICTRL2_F2_END_LINE__##e)
+#define BFM_LCDIF_DVICTRL2_F2_END_LINE_V(v)         BM_LCDIF_DVICTRL2_F2_END_LINE
+#define BP_LCDIF_DVICTRL2_V1_BLANK_START_LINE       10
+#define BM_LCDIF_DVICTRL2_V1_BLANK_START_LINE       0xffc00
+#define BF_LCDIF_DVICTRL2_V1_BLANK_START_LINE(v)    (((v) & 0x3ff) << 10)
+#define BFM_LCDIF_DVICTRL2_V1_BLANK_START_LINE(v)   BM_LCDIF_DVICTRL2_V1_BLANK_START_LINE
+#define BF_LCDIF_DVICTRL2_V1_BLANK_START_LINE_V(e)  BF_LCDIF_DVICTRL2_V1_BLANK_START_LINE(BV_LCDIF_DVICTRL2_V1_BLANK_START_LINE__##e)
+#define BFM_LCDIF_DVICTRL2_V1_BLANK_START_LINE_V(v) BM_LCDIF_DVICTRL2_V1_BLANK_START_LINE
+#define BP_LCDIF_DVICTRL2_V1_BLANK_END_LINE         0
+#define BM_LCDIF_DVICTRL2_V1_BLANK_END_LINE         0x3ff
+#define BF_LCDIF_DVICTRL2_V1_BLANK_END_LINE(v)      (((v) & 0x3ff) << 0)
+#define BFM_LCDIF_DVICTRL2_V1_BLANK_END_LINE(v)     BM_LCDIF_DVICTRL2_V1_BLANK_END_LINE
+#define BF_LCDIF_DVICTRL2_V1_BLANK_END_LINE_V(e)    BF_LCDIF_DVICTRL2_V1_BLANK_END_LINE(BV_LCDIF_DVICTRL2_V1_BLANK_END_LINE__##e)
+#define BFM_LCDIF_DVICTRL2_V1_BLANK_END_LINE_V(v)   BM_LCDIF_DVICTRL2_V1_BLANK_END_LINE
+
+#define HW_LCDIF_DVICTRL3                           HW(LCDIF_DVICTRL3)
+#define HWA_LCDIF_DVICTRL3                          (0x80030000 + 0xf0)
+#define HWT_LCDIF_DVICTRL3                          HWIO_32_RW
+#define HWN_LCDIF_DVICTRL3                          LCDIF_DVICTRL3
+#define HWI_LCDIF_DVICTRL3                          
+#define BP_LCDIF_DVICTRL3_RSRVD1                    26
+#define BM_LCDIF_DVICTRL3_RSRVD1                    0xfc000000
+#define BF_LCDIF_DVICTRL3_RSRVD1(v)                 (((v) & 0x3f) << 26)
+#define BFM_LCDIF_DVICTRL3_RSRVD1(v)                BM_LCDIF_DVICTRL3_RSRVD1
+#define BF_LCDIF_DVICTRL3_RSRVD1_V(e)               BF_LCDIF_DVICTRL3_RSRVD1(BV_LCDIF_DVICTRL3_RSRVD1__##e)
+#define BFM_LCDIF_DVICTRL3_RSRVD1_V(v)              BM_LCDIF_DVICTRL3_RSRVD1
+#define BP_LCDIF_DVICTRL3_V2_BLANK_START_LINE       16
+#define BM_LCDIF_DVICTRL3_V2_BLANK_START_LINE       0x3ff0000
+#define BF_LCDIF_DVICTRL3_V2_BLANK_START_LINE(v)    (((v) & 0x3ff) << 16)
+#define BFM_LCDIF_DVICTRL3_V2_BLANK_START_LINE(v)   BM_LCDIF_DVICTRL3_V2_BLANK_START_LINE
+#define BF_LCDIF_DVICTRL3_V2_BLANK_START_LINE_V(e)  BF_LCDIF_DVICTRL3_V2_BLANK_START_LINE(BV_LCDIF_DVICTRL3_V2_BLANK_START_LINE__##e)
+#define BFM_LCDIF_DVICTRL3_V2_BLANK_START_LINE_V(v) BM_LCDIF_DVICTRL3_V2_BLANK_START_LINE
+#define BP_LCDIF_DVICTRL3_RSRVD0                    10
+#define BM_LCDIF_DVICTRL3_RSRVD0                    0xfc00
+#define BF_LCDIF_DVICTRL3_RSRVD0(v)                 (((v) & 0x3f) << 10)
+#define BFM_LCDIF_DVICTRL3_RSRVD0(v)                BM_LCDIF_DVICTRL3_RSRVD0
+#define BF_LCDIF_DVICTRL3_RSRVD0_V(e)               BF_LCDIF_DVICTRL3_RSRVD0(BV_LCDIF_DVICTRL3_RSRVD0__##e)
+#define BFM_LCDIF_DVICTRL3_RSRVD0_V(v)              BM_LCDIF_DVICTRL3_RSRVD0
+#define BP_LCDIF_DVICTRL3_V2_BLANK_END_LINE         0
+#define BM_LCDIF_DVICTRL3_V2_BLANK_END_LINE         0x3ff
+#define BF_LCDIF_DVICTRL3_V2_BLANK_END_LINE(v)      (((v) & 0x3ff) << 0)
+#define BFM_LCDIF_DVICTRL3_V2_BLANK_END_LINE(v)     BM_LCDIF_DVICTRL3_V2_BLANK_END_LINE
+#define BF_LCDIF_DVICTRL3_V2_BLANK_END_LINE_V(e)    BF_LCDIF_DVICTRL3_V2_BLANK_END_LINE(BV_LCDIF_DVICTRL3_V2_BLANK_END_LINE__##e)
+#define BFM_LCDIF_DVICTRL3_V2_BLANK_END_LINE_V(v)   BM_LCDIF_DVICTRL3_V2_BLANK_END_LINE
+
+#define HW_LCDIF_DVICTRL4                       HW(LCDIF_DVICTRL4)
+#define HWA_LCDIF_DVICTRL4                      (0x80030000 + 0x100)
+#define HWT_LCDIF_DVICTRL4                      HWIO_32_RW
+#define HWN_LCDIF_DVICTRL4                      LCDIF_DVICTRL4
+#define HWI_LCDIF_DVICTRL4                      
+#define BP_LCDIF_DVICTRL4_Y_FILL_VALUE          24
+#define BM_LCDIF_DVICTRL4_Y_FILL_VALUE          0xff000000
+#define BF_LCDIF_DVICTRL4_Y_FILL_VALUE(v)       (((v) & 0xff) << 24)
+#define BFM_LCDIF_DVICTRL4_Y_FILL_VALUE(v)      BM_LCDIF_DVICTRL4_Y_FILL_VALUE
+#define BF_LCDIF_DVICTRL4_Y_FILL_VALUE_V(e)     BF_LCDIF_DVICTRL4_Y_FILL_VALUE(BV_LCDIF_DVICTRL4_Y_FILL_VALUE__##e)
+#define BFM_LCDIF_DVICTRL4_Y_FILL_VALUE_V(v)    BM_LCDIF_DVICTRL4_Y_FILL_VALUE
+#define BP_LCDIF_DVICTRL4_CB_FILL_VALUE         16
+#define BM_LCDIF_DVICTRL4_CB_FILL_VALUE         0xff0000
+#define BF_LCDIF_DVICTRL4_CB_FILL_VALUE(v)      (((v) & 0xff) << 16)
+#define BFM_LCDIF_DVICTRL4_CB_FILL_VALUE(v)     BM_LCDIF_DVICTRL4_CB_FILL_VALUE
+#define BF_LCDIF_DVICTRL4_CB_FILL_VALUE_V(e)    BF_LCDIF_DVICTRL4_CB_FILL_VALUE(BV_LCDIF_DVICTRL4_CB_FILL_VALUE__##e)
+#define BFM_LCDIF_DVICTRL4_CB_FILL_VALUE_V(v)   BM_LCDIF_DVICTRL4_CB_FILL_VALUE
+#define BP_LCDIF_DVICTRL4_CR_FILL_VALUE         8
+#define BM_LCDIF_DVICTRL4_CR_FILL_VALUE         0xff00
+#define BF_LCDIF_DVICTRL4_CR_FILL_VALUE(v)      (((v) & 0xff) << 8)
+#define BFM_LCDIF_DVICTRL4_CR_FILL_VALUE(v)     BM_LCDIF_DVICTRL4_CR_FILL_VALUE
+#define BF_LCDIF_DVICTRL4_CR_FILL_VALUE_V(e)    BF_LCDIF_DVICTRL4_CR_FILL_VALUE(BV_LCDIF_DVICTRL4_CR_FILL_VALUE__##e)
+#define BFM_LCDIF_DVICTRL4_CR_FILL_VALUE_V(v)   BM_LCDIF_DVICTRL4_CR_FILL_VALUE
+#define BP_LCDIF_DVICTRL4_H_FILL_CNT            0
+#define BM_LCDIF_DVICTRL4_H_FILL_CNT            0xff
+#define BF_LCDIF_DVICTRL4_H_FILL_CNT(v)         (((v) & 0xff) << 0)
+#define BFM_LCDIF_DVICTRL4_H_FILL_CNT(v)        BM_LCDIF_DVICTRL4_H_FILL_CNT
+#define BF_LCDIF_DVICTRL4_H_FILL_CNT_V(e)       BF_LCDIF_DVICTRL4_H_FILL_CNT(BV_LCDIF_DVICTRL4_H_FILL_CNT__##e)
+#define BFM_LCDIF_DVICTRL4_H_FILL_CNT_V(v)      BM_LCDIF_DVICTRL4_H_FILL_CNT
+
+#define HW_LCDIF_CSC_COEFF0                                         HW(LCDIF_CSC_COEFF0)
+#define HWA_LCDIF_CSC_COEFF0                                        (0x80030000 + 0x110)
+#define HWT_LCDIF_CSC_COEFF0                                        HWIO_32_RW
+#define HWN_LCDIF_CSC_COEFF0                                        LCDIF_CSC_COEFF0
+#define HWI_LCDIF_CSC_COEFF0                                        
+#define BP_LCDIF_CSC_COEFF0_RSRVD1                                  26
+#define BM_LCDIF_CSC_COEFF0_RSRVD1                                  0xfc000000
+#define BF_LCDIF_CSC_COEFF0_RSRVD1(v)                               (((v) & 0x3f) << 26)
+#define BFM_LCDIF_CSC_COEFF0_RSRVD1(v)                              BM_LCDIF_CSC_COEFF0_RSRVD1
+#define BF_LCDIF_CSC_COEFF0_RSRVD1_V(e)                             BF_LCDIF_CSC_COEFF0_RSRVD1(BV_LCDIF_CSC_COEFF0_RSRVD1__##e)
+#define BFM_LCDIF_CSC_COEFF0_RSRVD1_V(v)                            BM_LCDIF_CSC_COEFF0_RSRVD1
+#define BP_LCDIF_CSC_COEFF0_C0                                      16
+#define BM_LCDIF_CSC_COEFF0_C0                                      0x3ff0000
+#define BF_LCDIF_CSC_COEFF0_C0(v)                                   (((v) & 0x3ff) << 16)
+#define BFM_LCDIF_CSC_COEFF0_C0(v)                                  BM_LCDIF_CSC_COEFF0_C0
+#define BF_LCDIF_CSC_COEFF0_C0_V(e)                                 BF_LCDIF_CSC_COEFF0_C0(BV_LCDIF_CSC_COEFF0_C0__##e)
+#define BFM_LCDIF_CSC_COEFF0_C0_V(v)                                BM_LCDIF_CSC_COEFF0_C0
+#define BP_LCDIF_CSC_COEFF0_RSRVD0                                  2
+#define BM_LCDIF_CSC_COEFF0_RSRVD0                                  0xfffc
+#define BF_LCDIF_CSC_COEFF0_RSRVD0(v)                               (((v) & 0x3fff) << 2)
+#define BFM_LCDIF_CSC_COEFF0_RSRVD0(v)                              BM_LCDIF_CSC_COEFF0_RSRVD0
+#define BF_LCDIF_CSC_COEFF0_RSRVD0_V(e)                             BF_LCDIF_CSC_COEFF0_RSRVD0(BV_LCDIF_CSC_COEFF0_RSRVD0__##e)
+#define BFM_LCDIF_CSC_COEFF0_RSRVD0_V(v)                            BM_LCDIF_CSC_COEFF0_RSRVD0
+#define BP_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER                    0
+#define BM_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER                    0x3
+#define BV_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER__SAMPLE_AND_HOLD   0x0
+#define BV_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER__RSRVD             0x1
+#define BV_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER__INTERSTITIAL      0x2
+#define BV_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER__COSITED           0x3
+#define BF_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER(v)                 (((v) & 0x3) << 0)
+#define BFM_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER(v)                BM_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER
+#define BF_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER_V(e)               BF_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER(BV_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER__##e)
+#define BFM_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER_V(v)              BM_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER
+
+#define HW_LCDIF_CSC_COEFF1                 HW(LCDIF_CSC_COEFF1)
+#define HWA_LCDIF_CSC_COEFF1                (0x80030000 + 0x120)
+#define HWT_LCDIF_CSC_COEFF1                HWIO_32_RW
+#define HWN_LCDIF_CSC_COEFF1                LCDIF_CSC_COEFF1
+#define HWI_LCDIF_CSC_COEFF1                
+#define BP_LCDIF_CSC_COEFF1_RSRVD1          26
+#define BM_LCDIF_CSC_COEFF1_RSRVD1          0xfc000000
+#define BF_LCDIF_CSC_COEFF1_RSRVD1(v)       (((v) & 0x3f) << 26)
+#define BFM_LCDIF_CSC_COEFF1_RSRVD1(v)      BM_LCDIF_CSC_COEFF1_RSRVD1
+#define BF_LCDIF_CSC_COEFF1_RSRVD1_V(e)     BF_LCDIF_CSC_COEFF1_RSRVD1(BV_LCDIF_CSC_COEFF1_RSRVD1__##e)
+#define BFM_LCDIF_CSC_COEFF1_RSRVD1_V(v)    BM_LCDIF_CSC_COEFF1_RSRVD1
+#define BP_LCDIF_CSC_COEFF1_C2              16
+#define BM_LCDIF_CSC_COEFF1_C2              0x3ff0000
+#define BF_LCDIF_CSC_COEFF1_C2(v)           (((v) & 0x3ff) << 16)
+#define BFM_LCDIF_CSC_COEFF1_C2(v)          BM_LCDIF_CSC_COEFF1_C2
+#define BF_LCDIF_CSC_COEFF1_C2_V(e)         BF_LCDIF_CSC_COEFF1_C2(BV_LCDIF_CSC_COEFF1_C2__##e)
+#define BFM_LCDIF_CSC_COEFF1_C2_V(v)        BM_LCDIF_CSC_COEFF1_C2
+#define BP_LCDIF_CSC_COEFF1_RSRVD0          10
+#define BM_LCDIF_CSC_COEFF1_RSRVD0          0xfc00
+#define BF_LCDIF_CSC_COEFF1_RSRVD0(v)       (((v) & 0x3f) << 10)
+#define BFM_LCDIF_CSC_COEFF1_RSRVD0(v)      BM_LCDIF_CSC_COEFF1_RSRVD0
+#define BF_LCDIF_CSC_COEFF1_RSRVD0_V(e)     BF_LCDIF_CSC_COEFF1_RSRVD0(BV_LCDIF_CSC_COEFF1_RSRVD0__##e)
+#define BFM_LCDIF_CSC_COEFF1_RSRVD0_V(v)    BM_LCDIF_CSC_COEFF1_RSRVD0
+#define BP_LCDIF_CSC_COEFF1_C1              0
+#define BM_LCDIF_CSC_COEFF1_C1              0x3ff
+#define BF_LCDIF_CSC_COEFF1_C1(v)           (((v) & 0x3ff) << 0)
+#define BFM_LCDIF_CSC_COEFF1_C1(v)          BM_LCDIF_CSC_COEFF1_C1
+#define BF_LCDIF_CSC_COEFF1_C1_V(e)         BF_LCDIF_CSC_COEFF1_C1(BV_LCDIF_CSC_COEFF1_C1__##e)
+#define BFM_LCDIF_CSC_COEFF1_C1_V(v)        BM_LCDIF_CSC_COEFF1_C1
+
+#define HW_LCDIF_CSC_COEFF2                 HW(LCDIF_CSC_COEFF2)
+#define HWA_LCDIF_CSC_COEFF2                (0x80030000 + 0x130)
+#define HWT_LCDIF_CSC_COEFF2                HWIO_32_RW
+#define HWN_LCDIF_CSC_COEFF2                LCDIF_CSC_COEFF2
+#define HWI_LCDIF_CSC_COEFF2                
+#define BP_LCDIF_CSC_COEFF2_RSRVD1          26
+#define BM_LCDIF_CSC_COEFF2_RSRVD1          0xfc000000
+#define BF_LCDIF_CSC_COEFF2_RSRVD1(v)       (((v) & 0x3f) << 26)
+#define BFM_LCDIF_CSC_COEFF2_RSRVD1(v)      BM_LCDIF_CSC_COEFF2_RSRVD1
+#define BF_LCDIF_CSC_COEFF2_RSRVD1_V(e)     BF_LCDIF_CSC_COEFF2_RSRVD1(BV_LCDIF_CSC_COEFF2_RSRVD1__##e)
+#define BFM_LCDIF_CSC_COEFF2_RSRVD1_V(v)    BM_LCDIF_CSC_COEFF2_RSRVD1
+#define BP_LCDIF_CSC_COEFF2_C4              16
+#define BM_LCDIF_CSC_COEFF2_C4              0x3ff0000
+#define BF_LCDIF_CSC_COEFF2_C4(v)           (((v) & 0x3ff) << 16)
+#define BFM_LCDIF_CSC_COEFF2_C4(v)          BM_LCDIF_CSC_COEFF2_C4
+#define BF_LCDIF_CSC_COEFF2_C4_V(e)         BF_LCDIF_CSC_COEFF2_C4(BV_LCDIF_CSC_COEFF2_C4__##e)
+#define BFM_LCDIF_CSC_COEFF2_C4_V(v)        BM_LCDIF_CSC_COEFF2_C4
+#define BP_LCDIF_CSC_COEFF2_RSRVD0          10
+#define BM_LCDIF_CSC_COEFF2_RSRVD0          0xfc00
+#define BF_LCDIF_CSC_COEFF2_RSRVD0(v)       (((v) & 0x3f) << 10)
+#define BFM_LCDIF_CSC_COEFF2_RSRVD0(v)      BM_LCDIF_CSC_COEFF2_RSRVD0
+#define BF_LCDIF_CSC_COEFF2_RSRVD0_V(e)     BF_LCDIF_CSC_COEFF2_RSRVD0(BV_LCDIF_CSC_COEFF2_RSRVD0__##e)
+#define BFM_LCDIF_CSC_COEFF2_RSRVD0_V(v)    BM_LCDIF_CSC_COEFF2_RSRVD0
+#define BP_LCDIF_CSC_COEFF2_C3              0
+#define BM_LCDIF_CSC_COEFF2_C3              0x3ff
+#define BF_LCDIF_CSC_COEFF2_C3(v)           (((v) & 0x3ff) << 0)
+#define BFM_LCDIF_CSC_COEFF2_C3(v)          BM_LCDIF_CSC_COEFF2_C3
+#define BF_LCDIF_CSC_COEFF2_C3_V(e)         BF_LCDIF_CSC_COEFF2_C3(BV_LCDIF_CSC_COEFF2_C3__##e)
+#define BFM_LCDIF_CSC_COEFF2_C3_V(v)        BM_LCDIF_CSC_COEFF2_C3
+
+#define HW_LCDIF_CSC_COEFF3                 HW(LCDIF_CSC_COEFF3)
+#define HWA_LCDIF_CSC_COEFF3                (0x80030000 + 0x140)
+#define HWT_LCDIF_CSC_COEFF3                HWIO_32_RW
+#define HWN_LCDIF_CSC_COEFF3                LCDIF_CSC_COEFF3
+#define HWI_LCDIF_CSC_COEFF3                
+#define BP_LCDIF_CSC_COEFF3_RSRVD1          26
+#define BM_LCDIF_CSC_COEFF3_RSRVD1          0xfc000000
+#define BF_LCDIF_CSC_COEFF3_RSRVD1(v)       (((v) & 0x3f) << 26)
+#define BFM_LCDIF_CSC_COEFF3_RSRVD1(v)      BM_LCDIF_CSC_COEFF3_RSRVD1
+#define BF_LCDIF_CSC_COEFF3_RSRVD1_V(e)     BF_LCDIF_CSC_COEFF3_RSRVD1(BV_LCDIF_CSC_COEFF3_RSRVD1__##e)
+#define BFM_LCDIF_CSC_COEFF3_RSRVD1_V(v)    BM_LCDIF_CSC_COEFF3_RSRVD1
+#define BP_LCDIF_CSC_COEFF3_C6              16
+#define BM_LCDIF_CSC_COEFF3_C6              0x3ff0000
+#define BF_LCDIF_CSC_COEFF3_C6(v)           (((v) & 0x3ff) << 16)
+#define BFM_LCDIF_CSC_COEFF3_C6(v)          BM_LCDIF_CSC_COEFF3_C6
+#define BF_LCDIF_CSC_COEFF3_C6_V(e)         BF_LCDIF_CSC_COEFF3_C6(BV_LCDIF_CSC_COEFF3_C6__##e)
+#define BFM_LCDIF_CSC_COEFF3_C6_V(v)        BM_LCDIF_CSC_COEFF3_C6
+#define BP_LCDIF_CSC_COEFF3_RSRVD0          10
+#define BM_LCDIF_CSC_COEFF3_RSRVD0          0xfc00
+#define BF_LCDIF_CSC_COEFF3_RSRVD0(v)       (((v) & 0x3f) << 10)
+#define BFM_LCDIF_CSC_COEFF3_RSRVD0(v)      BM_LCDIF_CSC_COEFF3_RSRVD0
+#define BF_LCDIF_CSC_COEFF3_RSRVD0_V(e)     BF_LCDIF_CSC_COEFF3_RSRVD0(BV_LCDIF_CSC_COEFF3_RSRVD0__##e)
+#define BFM_LCDIF_CSC_COEFF3_RSRVD0_V(v)    BM_LCDIF_CSC_COEFF3_RSRVD0
+#define BP_LCDIF_CSC_COEFF3_C5              0
+#define BM_LCDIF_CSC_COEFF3_C5              0x3ff
+#define BF_LCDIF_CSC_COEFF3_C5(v)           (((v) & 0x3ff) << 0)
+#define BFM_LCDIF_CSC_COEFF3_C5(v)          BM_LCDIF_CSC_COEFF3_C5
+#define BF_LCDIF_CSC_COEFF3_C5_V(e)         BF_LCDIF_CSC_COEFF3_C5(BV_LCDIF_CSC_COEFF3_C5__##e)
+#define BFM_LCDIF_CSC_COEFF3_C5_V(v)        BM_LCDIF_CSC_COEFF3_C5
+
+#define HW_LCDIF_CSC_COEFF4                 HW(LCDIF_CSC_COEFF4)
+#define HWA_LCDIF_CSC_COEFF4                (0x80030000 + 0x150)
+#define HWT_LCDIF_CSC_COEFF4                HWIO_32_RW
+#define HWN_LCDIF_CSC_COEFF4                LCDIF_CSC_COEFF4
+#define HWI_LCDIF_CSC_COEFF4                
+#define BP_LCDIF_CSC_COEFF4_RSRVD1          26
+#define BM_LCDIF_CSC_COEFF4_RSRVD1          0xfc000000
+#define BF_LCDIF_CSC_COEFF4_RSRVD1(v)       (((v) & 0x3f) << 26)
+#define BFM_LCDIF_CSC_COEFF4_RSRVD1(v)      BM_LCDIF_CSC_COEFF4_RSRVD1
+#define BF_LCDIF_CSC_COEFF4_RSRVD1_V(e)     BF_LCDIF_CSC_COEFF4_RSRVD1(BV_LCDIF_CSC_COEFF4_RSRVD1__##e)
+#define BFM_LCDIF_CSC_COEFF4_RSRVD1_V(v)    BM_LCDIF_CSC_COEFF4_RSRVD1
+#define BP_LCDIF_CSC_COEFF4_C8              16
+#define BM_LCDIF_CSC_COEFF4_C8              0x3ff0000
+#define BF_LCDIF_CSC_COEFF4_C8(v)           (((v) & 0x3ff) << 16)
+#define BFM_LCDIF_CSC_COEFF4_C8(v)          BM_LCDIF_CSC_COEFF4_C8
+#define BF_LCDIF_CSC_COEFF4_C8_V(e)         BF_LCDIF_CSC_COEFF4_C8(BV_LCDIF_CSC_COEFF4_C8__##e)
+#define BFM_LCDIF_CSC_COEFF4_C8_V(v)        BM_LCDIF_CSC_COEFF4_C8
+#define BP_LCDIF_CSC_COEFF4_RSRVD0          10
+#define BM_LCDIF_CSC_COEFF4_RSRVD0          0xfc00
+#define BF_LCDIF_CSC_COEFF4_RSRVD0(v)       (((v) & 0x3f) << 10)
+#define BFM_LCDIF_CSC_COEFF4_RSRVD0(v)      BM_LCDIF_CSC_COEFF4_RSRVD0
+#define BF_LCDIF_CSC_COEFF4_RSRVD0_V(e)     BF_LCDIF_CSC_COEFF4_RSRVD0(BV_LCDIF_CSC_COEFF4_RSRVD0__##e)
+#define BFM_LCDIF_CSC_COEFF4_RSRVD0_V(v)    BM_LCDIF_CSC_COEFF4_RSRVD0
+#define BP_LCDIF_CSC_COEFF4_C7              0
+#define BM_LCDIF_CSC_COEFF4_C7              0x3ff
+#define BF_LCDIF_CSC_COEFF4_C7(v)           (((v) & 0x3ff) << 0)
+#define BFM_LCDIF_CSC_COEFF4_C7(v)          BM_LCDIF_CSC_COEFF4_C7
+#define BF_LCDIF_CSC_COEFF4_C7_V(e)         BF_LCDIF_CSC_COEFF4_C7(BV_LCDIF_CSC_COEFF4_C7__##e)
+#define BFM_LCDIF_CSC_COEFF4_C7_V(v)        BM_LCDIF_CSC_COEFF4_C7
+
+#define HW_LCDIF_CSC_OFFSET                     HW(LCDIF_CSC_OFFSET)
+#define HWA_LCDIF_CSC_OFFSET                    (0x80030000 + 0x160)
+#define HWT_LCDIF_CSC_OFFSET                    HWIO_32_RW
+#define HWN_LCDIF_CSC_OFFSET                    LCDIF_CSC_OFFSET
+#define HWI_LCDIF_CSC_OFFSET                    
+#define BP_LCDIF_CSC_OFFSET_RSRVD1              25
+#define BM_LCDIF_CSC_OFFSET_RSRVD1              0xfe000000
+#define BF_LCDIF_CSC_OFFSET_RSRVD1(v)           (((v) & 0x7f) << 25)
+#define BFM_LCDIF_CSC_OFFSET_RSRVD1(v)          BM_LCDIF_CSC_OFFSET_RSRVD1
+#define BF_LCDIF_CSC_OFFSET_RSRVD1_V(e)         BF_LCDIF_CSC_OFFSET_RSRVD1(BV_LCDIF_CSC_OFFSET_RSRVD1__##e)
+#define BFM_LCDIF_CSC_OFFSET_RSRVD1_V(v)        BM_LCDIF_CSC_OFFSET_RSRVD1
+#define BP_LCDIF_CSC_OFFSET_CBCR_OFFSET         16
+#define BM_LCDIF_CSC_OFFSET_CBCR_OFFSET         0x1ff0000
+#define BF_LCDIF_CSC_OFFSET_CBCR_OFFSET(v)      (((v) & 0x1ff) << 16)
+#define BFM_LCDIF_CSC_OFFSET_CBCR_OFFSET(v)     BM_LCDIF_CSC_OFFSET_CBCR_OFFSET
+#define BF_LCDIF_CSC_OFFSET_CBCR_OFFSET_V(e)    BF_LCDIF_CSC_OFFSET_CBCR_OFFSET(BV_LCDIF_CSC_OFFSET_CBCR_OFFSET__##e)
+#define BFM_LCDIF_CSC_OFFSET_CBCR_OFFSET_V(v)   BM_LCDIF_CSC_OFFSET_CBCR_OFFSET
+#define BP_LCDIF_CSC_OFFSET_RSRVD0              9
+#define BM_LCDIF_CSC_OFFSET_RSRVD0              0xfe00
+#define BF_LCDIF_CSC_OFFSET_RSRVD0(v)           (((v) & 0x7f) << 9)
+#define BFM_LCDIF_CSC_OFFSET_RSRVD0(v)          BM_LCDIF_CSC_OFFSET_RSRVD0
+#define BF_LCDIF_CSC_OFFSET_RSRVD0_V(e)         BF_LCDIF_CSC_OFFSET_RSRVD0(BV_LCDIF_CSC_OFFSET_RSRVD0__##e)
+#define BFM_LCDIF_CSC_OFFSET_RSRVD0_V(v)        BM_LCDIF_CSC_OFFSET_RSRVD0
+#define BP_LCDIF_CSC_OFFSET_Y_OFFSET            0
+#define BM_LCDIF_CSC_OFFSET_Y_OFFSET            0x1ff
+#define BF_LCDIF_CSC_OFFSET_Y_OFFSET(v)         (((v) & 0x1ff) << 0)
+#define BFM_LCDIF_CSC_OFFSET_Y_OFFSET(v)        BM_LCDIF_CSC_OFFSET_Y_OFFSET
+#define BF_LCDIF_CSC_OFFSET_Y_OFFSET_V(e)       BF_LCDIF_CSC_OFFSET_Y_OFFSET(BV_LCDIF_CSC_OFFSET_Y_OFFSET__##e)
+#define BFM_LCDIF_CSC_OFFSET_Y_OFFSET_V(v)      BM_LCDIF_CSC_OFFSET_Y_OFFSET
+
+#define HW_LCDIF_CSC_LIMIT                  HW(LCDIF_CSC_LIMIT)
+#define HWA_LCDIF_CSC_LIMIT                 (0x80030000 + 0x170)
+#define HWT_LCDIF_CSC_LIMIT                 HWIO_32_RW
+#define HWN_LCDIF_CSC_LIMIT                 LCDIF_CSC_LIMIT
+#define HWI_LCDIF_CSC_LIMIT                 
+#define BP_LCDIF_CSC_LIMIT_CBCR_MIN         24
+#define BM_LCDIF_CSC_LIMIT_CBCR_MIN         0xff000000
+#define BF_LCDIF_CSC_LIMIT_CBCR_MIN(v)      (((v) & 0xff) << 24)
+#define BFM_LCDIF_CSC_LIMIT_CBCR_MIN(v)     BM_LCDIF_CSC_LIMIT_CBCR_MIN
+#define BF_LCDIF_CSC_LIMIT_CBCR_MIN_V(e)    BF_LCDIF_CSC_LIMIT_CBCR_MIN(BV_LCDIF_CSC_LIMIT_CBCR_MIN__##e)
+#define BFM_LCDIF_CSC_LIMIT_CBCR_MIN_V(v)   BM_LCDIF_CSC_LIMIT_CBCR_MIN
+#define BP_LCDIF_CSC_LIMIT_CBCR_MAX         16
+#define BM_LCDIF_CSC_LIMIT_CBCR_MAX         0xff0000
+#define BF_LCDIF_CSC_LIMIT_CBCR_MAX(v)      (((v) & 0xff) << 16)
+#define BFM_LCDIF_CSC_LIMIT_CBCR_MAX(v)     BM_LCDIF_CSC_LIMIT_CBCR_MAX
+#define BF_LCDIF_CSC_LIMIT_CBCR_MAX_V(e)    BF_LCDIF_CSC_LIMIT_CBCR_MAX(BV_LCDIF_CSC_LIMIT_CBCR_MAX__##e)
+#define BFM_LCDIF_CSC_LIMIT_CBCR_MAX_V(v)   BM_LCDIF_CSC_LIMIT_CBCR_MAX
+#define BP_LCDIF_CSC_LIMIT_Y_MIN            8
+#define BM_LCDIF_CSC_LIMIT_Y_MIN            0xff00
+#define BF_LCDIF_CSC_LIMIT_Y_MIN(v)         (((v) & 0xff) << 8)
+#define BFM_LCDIF_CSC_LIMIT_Y_MIN(v)        BM_LCDIF_CSC_LIMIT_Y_MIN
+#define BF_LCDIF_CSC_LIMIT_Y_MIN_V(e)       BF_LCDIF_CSC_LIMIT_Y_MIN(BV_LCDIF_CSC_LIMIT_Y_MIN__##e)
+#define BFM_LCDIF_CSC_LIMIT_Y_MIN_V(v)      BM_LCDIF_CSC_LIMIT_Y_MIN
+#define BP_LCDIF_CSC_LIMIT_Y_MAX            0
+#define BM_LCDIF_CSC_LIMIT_Y_MAX            0xff
+#define BF_LCDIF_CSC_LIMIT_Y_MAX(v)         (((v) & 0xff) << 0)
+#define BFM_LCDIF_CSC_LIMIT_Y_MAX(v)        BM_LCDIF_CSC_LIMIT_Y_MAX
+#define BF_LCDIF_CSC_LIMIT_Y_MAX_V(e)       BF_LCDIF_CSC_LIMIT_Y_MAX(BV_LCDIF_CSC_LIMIT_Y_MAX__##e)
+#define BFM_LCDIF_CSC_LIMIT_Y_MAX_V(v)      BM_LCDIF_CSC_LIMIT_Y_MAX
+
+#define HW_LCDIF_PIN_SHARING_CTRL0                              HW(LCDIF_PIN_SHARING_CTRL0)
+#define HWA_LCDIF_PIN_SHARING_CTRL0                             (0x80030000 + 0x180)
+#define HWT_LCDIF_PIN_SHARING_CTRL0                             HWIO_32_RW
+#define HWN_LCDIF_PIN_SHARING_CTRL0                             LCDIF_PIN_SHARING_CTRL0
+#define HWI_LCDIF_PIN_SHARING_CTRL0                             
+#define HW_LCDIF_PIN_SHARING_CTRL0_SET                          HW(LCDIF_PIN_SHARING_CTRL0_SET)
+#define HWA_LCDIF_PIN_SHARING_CTRL0_SET                         (HWA_LCDIF_PIN_SHARING_CTRL0 + 0x4)
+#define HWT_LCDIF_PIN_SHARING_CTRL0_SET                         HWIO_32_WO
+#define HWN_LCDIF_PIN_SHARING_CTRL0_SET                         LCDIF_PIN_SHARING_CTRL0
+#define HWI_LCDIF_PIN_SHARING_CTRL0_SET                         
+#define HW_LCDIF_PIN_SHARING_CTRL0_CLR                          HW(LCDIF_PIN_SHARING_CTRL0_CLR)
+#define HWA_LCDIF_PIN_SHARING_CTRL0_CLR                         (HWA_LCDIF_PIN_SHARING_CTRL0 + 0x8)
+#define HWT_LCDIF_PIN_SHARING_CTRL0_CLR                         HWIO_32_WO
+#define HWN_LCDIF_PIN_SHARING_CTRL0_CLR                         LCDIF_PIN_SHARING_CTRL0
+#define HWI_LCDIF_PIN_SHARING_CTRL0_CLR                         
+#define HW_LCDIF_PIN_SHARING_CTRL0_TOG                          HW(LCDIF_PIN_SHARING_CTRL0_TOG)
+#define HWA_LCDIF_PIN_SHARING_CTRL0_TOG                         (HWA_LCDIF_PIN_SHARING_CTRL0 + 0xc)
+#define HWT_LCDIF_PIN_SHARING_CTRL0_TOG                         HWIO_32_WO
+#define HWN_LCDIF_PIN_SHARING_CTRL0_TOG                         LCDIF_PIN_SHARING_CTRL0
+#define HWI_LCDIF_PIN_SHARING_CTRL0_TOG                         
+#define BP_LCDIF_PIN_SHARING_CTRL0_RSRVD1                       6
+#define BM_LCDIF_PIN_SHARING_CTRL0_RSRVD1                       0xffffffc0
+#define BF_LCDIF_PIN_SHARING_CTRL0_RSRVD1(v)                    (((v) & 0x3ffffff) << 6)
+#define BFM_LCDIF_PIN_SHARING_CTRL0_RSRVD1(v)                   BM_LCDIF_PIN_SHARING_CTRL0_RSRVD1
+#define BF_LCDIF_PIN_SHARING_CTRL0_RSRVD1_V(e)                  BF_LCDIF_PIN_SHARING_CTRL0_RSRVD1(BV_LCDIF_PIN_SHARING_CTRL0_RSRVD1__##e)
+#define BFM_LCDIF_PIN_SHARING_CTRL0_RSRVD1_V(v)                 BM_LCDIF_PIN_SHARING_CTRL0_RSRVD1
+#define BP_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE                 4
+#define BM_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE                 0x30
+#define BV_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE__NO_OVERRIDE    0x0
+#define BV_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE__RSRVD          0x1
+#define BV_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE__LCDIF_SEL      0x2
+#define BV_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE__GPMI_SEL       0x3
+#define BF_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE(v)              (((v) & 0x3) << 4)
+#define BFM_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE(v)             BM_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE
+#define BF_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE_V(e)            BF_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE(BV_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE__##e)
+#define BFM_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE_V(v)           BM_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE
+#define BP_LCDIF_PIN_SHARING_CTRL0_RSRVD0                       3
+#define BM_LCDIF_PIN_SHARING_CTRL0_RSRVD0                       0x8
+#define BF_LCDIF_PIN_SHARING_CTRL0_RSRVD0(v)                    (((v) & 0x1) << 3)
+#define BFM_LCDIF_PIN_SHARING_CTRL0_RSRVD0(v)                   BM_LCDIF_PIN_SHARING_CTRL0_RSRVD0
+#define BF_LCDIF_PIN_SHARING_CTRL0_RSRVD0_V(e)                  BF_LCDIF_PIN_SHARING_CTRL0_RSRVD0(BV_LCDIF_PIN_SHARING_CTRL0_RSRVD0__##e)
+#define BFM_LCDIF_PIN_SHARING_CTRL0_RSRVD0_V(v)                 BM_LCDIF_PIN_SHARING_CTRL0_RSRVD0
+#define BP_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_IRQ_EN           2
+#define BM_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_IRQ_EN           0x4
+#define BF_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_IRQ_EN(v)        (((v) & 0x1) << 2)
+#define BFM_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_IRQ_EN(v)       BM_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_IRQ_EN
+#define BF_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_IRQ_EN_V(e)      BF_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_IRQ_EN(BV_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_IRQ_EN__##e)
+#define BFM_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_IRQ_EN_V(v)     BM_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_IRQ_EN
+#define BP_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_IRQ              1
+#define BM_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_IRQ              0x2
+#define BV_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_IRQ__NO_REQUEST  0x0
+#define BV_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_IRQ__REQUEST     0x1
+#define BF_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_IRQ(v)           (((v) & 0x1) << 1)
+#define BFM_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_IRQ(v)          BM_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_IRQ
+#define BF_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_IRQ_V(e)         BF_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_IRQ(BV_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_IRQ__##e)
+#define BFM_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_IRQ_V(v)        BM_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_IRQ
+#define BP_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_ENABLE           0
+#define BM_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_ENABLE           0x1
+#define BF_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_ENABLE(v)        (((v) & 0x1) << 0)
+#define BFM_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_ENABLE(v)       BM_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_ENABLE
+#define BF_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_ENABLE_V(e)      BF_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_ENABLE(BV_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_ENABLE__##e)
+#define BFM_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_ENABLE_V(v)     BM_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_ENABLE
+
+#define HW_LCDIF_PIN_SHARING_CTRL1                  HW(LCDIF_PIN_SHARING_CTRL1)
+#define HWA_LCDIF_PIN_SHARING_CTRL1                 (0x80030000 + 0x190)
+#define HWT_LCDIF_PIN_SHARING_CTRL1                 HWIO_32_RW
+#define HWN_LCDIF_PIN_SHARING_CTRL1                 LCDIF_PIN_SHARING_CTRL1
+#define HWI_LCDIF_PIN_SHARING_CTRL1                 
+#define BP_LCDIF_PIN_SHARING_CTRL1_THRESHOLD1       0
+#define BM_LCDIF_PIN_SHARING_CTRL1_THRESHOLD1       0xffffffff
+#define BF_LCDIF_PIN_SHARING_CTRL1_THRESHOLD1(v)    (((v) & 0xffffffff) << 0)
+#define BFM_LCDIF_PIN_SHARING_CTRL1_THRESHOLD1(v)   BM_LCDIF_PIN_SHARING_CTRL1_THRESHOLD1
+#define BF_LCDIF_PIN_SHARING_CTRL1_THRESHOLD1_V(e)  BF_LCDIF_PIN_SHARING_CTRL1_THRESHOLD1(BV_LCDIF_PIN_SHARING_CTRL1_THRESHOLD1__##e)
+#define BFM_LCDIF_PIN_SHARING_CTRL1_THRESHOLD1_V(v) BM_LCDIF_PIN_SHARING_CTRL1_THRESHOLD1
+
+#define HW_LCDIF_PIN_SHARING_CTRL2                  HW(LCDIF_PIN_SHARING_CTRL2)
+#define HWA_LCDIF_PIN_SHARING_CTRL2                 (0x80030000 + 0x1a0)
+#define HWT_LCDIF_PIN_SHARING_CTRL2                 HWIO_32_RW
+#define HWN_LCDIF_PIN_SHARING_CTRL2                 LCDIF_PIN_SHARING_CTRL2
+#define HWI_LCDIF_PIN_SHARING_CTRL2                 
+#define BP_LCDIF_PIN_SHARING_CTRL2_THRESHOLD2       0
+#define BM_LCDIF_PIN_SHARING_CTRL2_THRESHOLD2       0xffffffff
+#define BF_LCDIF_PIN_SHARING_CTRL2_THRESHOLD2(v)    (((v) & 0xffffffff) << 0)
+#define BFM_LCDIF_PIN_SHARING_CTRL2_THRESHOLD2(v)   BM_LCDIF_PIN_SHARING_CTRL2_THRESHOLD2
+#define BF_LCDIF_PIN_SHARING_CTRL2_THRESHOLD2_V(e)  BF_LCDIF_PIN_SHARING_CTRL2_THRESHOLD2(BV_LCDIF_PIN_SHARING_CTRL2_THRESHOLD2__##e)
+#define BFM_LCDIF_PIN_SHARING_CTRL2_THRESHOLD2_V(v) BM_LCDIF_PIN_SHARING_CTRL2_THRESHOLD2
+
+#define HW_LCDIF_DATA                   HW(LCDIF_DATA)
+#define HWA_LCDIF_DATA                  (0x80030000 + 0x1b0)
+#define HWT_LCDIF_DATA                  HWIO_32_RW
+#define HWN_LCDIF_DATA                  LCDIF_DATA
+#define HWI_LCDIF_DATA                  
+#define BP_LCDIF_DATA_DATA_THREE        24
+#define BM_LCDIF_DATA_DATA_THREE        0xff000000
+#define BF_LCDIF_DATA_DATA_THREE(v)     (((v) & 0xff) << 24)
+#define BFM_LCDIF_DATA_DATA_THREE(v)    BM_LCDIF_DATA_DATA_THREE
+#define BF_LCDIF_DATA_DATA_THREE_V(e)   BF_LCDIF_DATA_DATA_THREE(BV_LCDIF_DATA_DATA_THREE__##e)
+#define BFM_LCDIF_DATA_DATA_THREE_V(v)  BM_LCDIF_DATA_DATA_THREE
+#define BP_LCDIF_DATA_DATA_TWO          16
+#define BM_LCDIF_DATA_DATA_TWO          0xff0000
+#define BF_LCDIF_DATA_DATA_TWO(v)       (((v) & 0xff) << 16)
+#define BFM_LCDIF_DATA_DATA_TWO(v)      BM_LCDIF_DATA_DATA_TWO
+#define BF_LCDIF_DATA_DATA_TWO_V(e)     BF_LCDIF_DATA_DATA_TWO(BV_LCDIF_DATA_DATA_TWO__##e)
+#define BFM_LCDIF_DATA_DATA_TWO_V(v)    BM_LCDIF_DATA_DATA_TWO
+#define BP_LCDIF_DATA_DATA_ONE          8
+#define BM_LCDIF_DATA_DATA_ONE          0xff00
+#define BF_LCDIF_DATA_DATA_ONE(v)       (((v) & 0xff) << 8)
+#define BFM_LCDIF_DATA_DATA_ONE(v)      BM_LCDIF_DATA_DATA_ONE
+#define BF_LCDIF_DATA_DATA_ONE_V(e)     BF_LCDIF_DATA_DATA_ONE(BV_LCDIF_DATA_DATA_ONE__##e)
+#define BFM_LCDIF_DATA_DATA_ONE_V(v)    BM_LCDIF_DATA_DATA_ONE
+#define BP_LCDIF_DATA_DATA_ZERO         0
+#define BM_LCDIF_DATA_DATA_ZERO         0xff
+#define BF_LCDIF_DATA_DATA_ZERO(v)      (((v) & 0xff) << 0)
+#define BFM_LCDIF_DATA_DATA_ZERO(v)     BM_LCDIF_DATA_DATA_ZERO
+#define BF_LCDIF_DATA_DATA_ZERO_V(e)    BF_LCDIF_DATA_DATA_ZERO(BV_LCDIF_DATA_DATA_ZERO__##e)
+#define BFM_LCDIF_DATA_DATA_ZERO_V(v)   BM_LCDIF_DATA_DATA_ZERO
+
+#define HW_LCDIF_BM_ERROR_STAT              HW(LCDIF_BM_ERROR_STAT)
+#define HWA_LCDIF_BM_ERROR_STAT             (0x80030000 + 0x1c0)
+#define HWT_LCDIF_BM_ERROR_STAT             HWIO_32_RW
+#define HWN_LCDIF_BM_ERROR_STAT             LCDIF_BM_ERROR_STAT
+#define HWI_LCDIF_BM_ERROR_STAT             
+#define BP_LCDIF_BM_ERROR_STAT_ADDR         0
+#define BM_LCDIF_BM_ERROR_STAT_ADDR         0xffffffff
+#define BF_LCDIF_BM_ERROR_STAT_ADDR(v)      (((v) & 0xffffffff) << 0)
+#define BFM_LCDIF_BM_ERROR_STAT_ADDR(v)     BM_LCDIF_BM_ERROR_STAT_ADDR
+#define BF_LCDIF_BM_ERROR_STAT_ADDR_V(e)    BF_LCDIF_BM_ERROR_STAT_ADDR(BV_LCDIF_BM_ERROR_STAT_ADDR__##e)
+#define BFM_LCDIF_BM_ERROR_STAT_ADDR_V(v)   BM_LCDIF_BM_ERROR_STAT_ADDR
+
+#define HW_LCDIF_STAT                           HW(LCDIF_STAT)
+#define HWA_LCDIF_STAT                          (0x80030000 + 0x1d0)
+#define HWT_LCDIF_STAT                          HWIO_32_RW
+#define HWN_LCDIF_STAT                          LCDIF_STAT
+#define HWI_LCDIF_STAT                          
+#define BP_LCDIF_STAT_PRESENT                   31
+#define BM_LCDIF_STAT_PRESENT                   0x80000000
+#define BF_LCDIF_STAT_PRESENT(v)                (((v) & 0x1) << 31)
+#define BFM_LCDIF_STAT_PRESENT(v)               BM_LCDIF_STAT_PRESENT
+#define BF_LCDIF_STAT_PRESENT_V(e)              BF_LCDIF_STAT_PRESENT(BV_LCDIF_STAT_PRESENT__##e)
+#define BFM_LCDIF_STAT_PRESENT_V(v)             BM_LCDIF_STAT_PRESENT
+#define BP_LCDIF_STAT_DMA_REQ                   30
+#define BM_LCDIF_STAT_DMA_REQ                   0x40000000
+#define BF_LCDIF_STAT_DMA_REQ(v)                (((v) & 0x1) << 30)
+#define BFM_LCDIF_STAT_DMA_REQ(v)               BM_LCDIF_STAT_DMA_REQ
+#define BF_LCDIF_STAT_DMA_REQ_V(e)              BF_LCDIF_STAT_DMA_REQ(BV_LCDIF_STAT_DMA_REQ__##e)
+#define BFM_LCDIF_STAT_DMA_REQ_V(v)             BM_LCDIF_STAT_DMA_REQ
+#define BP_LCDIF_STAT_LFIFO_FULL                29
+#define BM_LCDIF_STAT_LFIFO_FULL                0x20000000
+#define BF_LCDIF_STAT_LFIFO_FULL(v)             (((v) & 0x1) << 29)
+#define BFM_LCDIF_STAT_LFIFO_FULL(v)            BM_LCDIF_STAT_LFIFO_FULL
+#define BF_LCDIF_STAT_LFIFO_FULL_V(e)           BF_LCDIF_STAT_LFIFO_FULL(BV_LCDIF_STAT_LFIFO_FULL__##e)
+#define BFM_LCDIF_STAT_LFIFO_FULL_V(v)          BM_LCDIF_STAT_LFIFO_FULL
+#define BP_LCDIF_STAT_LFIFO_EMPTY               28
+#define BM_LCDIF_STAT_LFIFO_EMPTY               0x10000000
+#define BF_LCDIF_STAT_LFIFO_EMPTY(v)            (((v) & 0x1) << 28)
+#define BFM_LCDIF_STAT_LFIFO_EMPTY(v)           BM_LCDIF_STAT_LFIFO_EMPTY
+#define BF_LCDIF_STAT_LFIFO_EMPTY_V(e)          BF_LCDIF_STAT_LFIFO_EMPTY(BV_LCDIF_STAT_LFIFO_EMPTY__##e)
+#define BFM_LCDIF_STAT_LFIFO_EMPTY_V(v)         BM_LCDIF_STAT_LFIFO_EMPTY
+#define BP_LCDIF_STAT_TXFIFO_FULL               27
+#define BM_LCDIF_STAT_TXFIFO_FULL               0x8000000
+#define BF_LCDIF_STAT_TXFIFO_FULL(v)            (((v) & 0x1) << 27)
+#define BFM_LCDIF_STAT_TXFIFO_FULL(v)           BM_LCDIF_STAT_TXFIFO_FULL
+#define BF_LCDIF_STAT_TXFIFO_FULL_V(e)          BF_LCDIF_STAT_TXFIFO_FULL(BV_LCDIF_STAT_TXFIFO_FULL__##e)
+#define BFM_LCDIF_STAT_TXFIFO_FULL_V(v)         BM_LCDIF_STAT_TXFIFO_FULL
+#define BP_LCDIF_STAT_TXFIFO_EMPTY              26
+#define BM_LCDIF_STAT_TXFIFO_EMPTY              0x4000000
+#define BF_LCDIF_STAT_TXFIFO_EMPTY(v)           (((v) & 0x1) << 26)
+#define BFM_LCDIF_STAT_TXFIFO_EMPTY(v)          BM_LCDIF_STAT_TXFIFO_EMPTY
+#define BF_LCDIF_STAT_TXFIFO_EMPTY_V(e)         BF_LCDIF_STAT_TXFIFO_EMPTY(BV_LCDIF_STAT_TXFIFO_EMPTY__##e)
+#define BFM_LCDIF_STAT_TXFIFO_EMPTY_V(v)        BM_LCDIF_STAT_TXFIFO_EMPTY
+#define BP_LCDIF_STAT_BUSY                      25
+#define BM_LCDIF_STAT_BUSY                      0x2000000
+#define BF_LCDIF_STAT_BUSY(v)                   (((v) & 0x1) << 25)
+#define BFM_LCDIF_STAT_BUSY(v)                  BM_LCDIF_STAT_BUSY
+#define BF_LCDIF_STAT_BUSY_V(e)                 BF_LCDIF_STAT_BUSY(BV_LCDIF_STAT_BUSY__##e)
+#define BFM_LCDIF_STAT_BUSY_V(v)                BM_LCDIF_STAT_BUSY
+#define BP_LCDIF_STAT_DVI_CURRENT_FIELD         24
+#define BM_LCDIF_STAT_DVI_CURRENT_FIELD         0x1000000
+#define BF_LCDIF_STAT_DVI_CURRENT_FIELD(v)      (((v) & 0x1) << 24)
+#define BFM_LCDIF_STAT_DVI_CURRENT_FIELD(v)     BM_LCDIF_STAT_DVI_CURRENT_FIELD
+#define BF_LCDIF_STAT_DVI_CURRENT_FIELD_V(e)    BF_LCDIF_STAT_DVI_CURRENT_FIELD(BV_LCDIF_STAT_DVI_CURRENT_FIELD__##e)
+#define BFM_LCDIF_STAT_DVI_CURRENT_FIELD_V(v)   BM_LCDIF_STAT_DVI_CURRENT_FIELD
+#define BP_LCDIF_STAT_RSRVD0                    0
+#define BM_LCDIF_STAT_RSRVD0                    0xffffff
+#define BF_LCDIF_STAT_RSRVD0(v)                 (((v) & 0xffffff) << 0)
+#define BFM_LCDIF_STAT_RSRVD0(v)                BM_LCDIF_STAT_RSRVD0
+#define BF_LCDIF_STAT_RSRVD0_V(e)               BF_LCDIF_STAT_RSRVD0(BV_LCDIF_STAT_RSRVD0__##e)
+#define BFM_LCDIF_STAT_RSRVD0_V(v)              BM_LCDIF_STAT_RSRVD0
+
+#define HW_LCDIF_VERSION                HW(LCDIF_VERSION)
+#define HWA_LCDIF_VERSION               (0x80030000 + 0x1e0)
+#define HWT_LCDIF_VERSION               HWIO_32_RW
+#define HWN_LCDIF_VERSION               LCDIF_VERSION
+#define HWI_LCDIF_VERSION               
+#define BP_LCDIF_VERSION_MAJOR          24
+#define BM_LCDIF_VERSION_MAJOR          0xff000000
+#define BF_LCDIF_VERSION_MAJOR(v)       (((v) & 0xff) << 24)
+#define BFM_LCDIF_VERSION_MAJOR(v)      BM_LCDIF_VERSION_MAJOR
+#define BF_LCDIF_VERSION_MAJOR_V(e)     BF_LCDIF_VERSION_MAJOR(BV_LCDIF_VERSION_MAJOR__##e)
+#define BFM_LCDIF_VERSION_MAJOR_V(v)    BM_LCDIF_VERSION_MAJOR
+#define BP_LCDIF_VERSION_MINOR          16
+#define BM_LCDIF_VERSION_MINOR          0xff0000
+#define BF_LCDIF_VERSION_MINOR(v)       (((v) & 0xff) << 16)
+#define BFM_LCDIF_VERSION_MINOR(v)      BM_LCDIF_VERSION_MINOR
+#define BF_LCDIF_VERSION_MINOR_V(e)     BF_LCDIF_VERSION_MINOR(BV_LCDIF_VERSION_MINOR__##e)
+#define BFM_LCDIF_VERSION_MINOR_V(v)    BM_LCDIF_VERSION_MINOR
+#define BP_LCDIF_VERSION_STEP           0
+#define BM_LCDIF_VERSION_STEP           0xffff
+#define BF_LCDIF_VERSION_STEP(v)        (((v) & 0xffff) << 0)
+#define BFM_LCDIF_VERSION_STEP(v)       BM_LCDIF_VERSION_STEP
+#define BF_LCDIF_VERSION_STEP_V(e)      BF_LCDIF_VERSION_STEP(BV_LCDIF_VERSION_STEP__##e)
+#define BFM_LCDIF_VERSION_STEP_V(v)     BM_LCDIF_VERSION_STEP
+
+#define HW_LCDIF_DEBUG0                                 HW(LCDIF_DEBUG0)
+#define HWA_LCDIF_DEBUG0                                (0x80030000 + 0x1f0)
+#define HWT_LCDIF_DEBUG0                                HWIO_32_RW
+#define HWN_LCDIF_DEBUG0                                LCDIF_DEBUG0
+#define HWI_LCDIF_DEBUG0                                
+#define BP_LCDIF_DEBUG0_STREAMING_END_DETECTED          31
+#define BM_LCDIF_DEBUG0_STREAMING_END_DETECTED          0x80000000
+#define BF_LCDIF_DEBUG0_STREAMING_END_DETECTED(v)       (((v) & 0x1) << 31)
+#define BFM_LCDIF_DEBUG0_STREAMING_END_DETECTED(v)      BM_LCDIF_DEBUG0_STREAMING_END_DETECTED
+#define BF_LCDIF_DEBUG0_STREAMING_END_DETECTED_V(e)     BF_LCDIF_DEBUG0_STREAMING_END_DETECTED(BV_LCDIF_DEBUG0_STREAMING_END_DETECTED__##e)
+#define BFM_LCDIF_DEBUG0_STREAMING_END_DETECTED_V(v)    BM_LCDIF_DEBUG0_STREAMING_END_DETECTED
+#define BP_LCDIF_DEBUG0_WAIT_FOR_VSYNC_EDGE_OUT         30
+#define BM_LCDIF_DEBUG0_WAIT_FOR_VSYNC_EDGE_OUT         0x40000000
+#define BF_LCDIF_DEBUG0_WAIT_FOR_VSYNC_EDGE_OUT(v)      (((v) & 0x1) << 30)
+#define BFM_LCDIF_DEBUG0_WAIT_FOR_VSYNC_EDGE_OUT(v)     BM_LCDIF_DEBUG0_WAIT_FOR_VSYNC_EDGE_OUT
+#define BF_LCDIF_DEBUG0_WAIT_FOR_VSYNC_EDGE_OUT_V(e)    BF_LCDIF_DEBUG0_WAIT_FOR_VSYNC_EDGE_OUT(BV_LCDIF_DEBUG0_WAIT_FOR_VSYNC_EDGE_OUT__##e)
+#define BFM_LCDIF_DEBUG0_WAIT_FOR_VSYNC_EDGE_OUT_V(v)   BM_LCDIF_DEBUG0_WAIT_FOR_VSYNC_EDGE_OUT
+#define BP_LCDIF_DEBUG0_SYNC_SIGNALS_ON_REG             29
+#define BM_LCDIF_DEBUG0_SYNC_SIGNALS_ON_REG             0x20000000
+#define BF_LCDIF_DEBUG0_SYNC_SIGNALS_ON_REG(v)          (((v) & 0x1) << 29)
+#define BFM_LCDIF_DEBUG0_SYNC_SIGNALS_ON_REG(v)         BM_LCDIF_DEBUG0_SYNC_SIGNALS_ON_REG
+#define BF_LCDIF_DEBUG0_SYNC_SIGNALS_ON_REG_V(e)        BF_LCDIF_DEBUG0_SYNC_SIGNALS_ON_REG(BV_LCDIF_DEBUG0_SYNC_SIGNALS_ON_REG__##e)
+#define BFM_LCDIF_DEBUG0_SYNC_SIGNALS_ON_REG_V(v)       BM_LCDIF_DEBUG0_SYNC_SIGNALS_ON_REG
+#define BP_LCDIF_DEBUG0_DMACMDKICK                      28
+#define BM_LCDIF_DEBUG0_DMACMDKICK                      0x10000000
+#define BF_LCDIF_DEBUG0_DMACMDKICK(v)                   (((v) & 0x1) << 28)
+#define BFM_LCDIF_DEBUG0_DMACMDKICK(v)                  BM_LCDIF_DEBUG0_DMACMDKICK
+#define BF_LCDIF_DEBUG0_DMACMDKICK_V(e)                 BF_LCDIF_DEBUG0_DMACMDKICK(BV_LCDIF_DEBUG0_DMACMDKICK__##e)
+#define BFM_LCDIF_DEBUG0_DMACMDKICK_V(v)                BM_LCDIF_DEBUG0_DMACMDKICK
+#define BP_LCDIF_DEBUG0_ENABLE                          27
+#define BM_LCDIF_DEBUG0_ENABLE                          0x8000000
+#define BF_LCDIF_DEBUG0_ENABLE(v)                       (((v) & 0x1) << 27)
+#define BFM_LCDIF_DEBUG0_ENABLE(v)                      BM_LCDIF_DEBUG0_ENABLE
+#define BF_LCDIF_DEBUG0_ENABLE_V(e)                     BF_LCDIF_DEBUG0_ENABLE(BV_LCDIF_DEBUG0_ENABLE__##e)
+#define BFM_LCDIF_DEBUG0_ENABLE_V(v)                    BM_LCDIF_DEBUG0_ENABLE
+#define BP_LCDIF_DEBUG0_HSYNC                           26
+#define BM_LCDIF_DEBUG0_HSYNC                           0x4000000
+#define BF_LCDIF_DEBUG0_HSYNC(v)                        (((v) & 0x1) << 26)
+#define BFM_LCDIF_DEBUG0_HSYNC(v)                       BM_LCDIF_DEBUG0_HSYNC
+#define BF_LCDIF_DEBUG0_HSYNC_V(e)                      BF_LCDIF_DEBUG0_HSYNC(BV_LCDIF_DEBUG0_HSYNC__##e)
+#define BFM_LCDIF_DEBUG0_HSYNC_V(v)                     BM_LCDIF_DEBUG0_HSYNC
+#define BP_LCDIF_DEBUG0_VSYNC                           25
+#define BM_LCDIF_DEBUG0_VSYNC                           0x2000000
+#define BF_LCDIF_DEBUG0_VSYNC(v)                        (((v) & 0x1) << 25)
+#define BFM_LCDIF_DEBUG0_VSYNC(v)                       BM_LCDIF_DEBUG0_VSYNC
+#define BF_LCDIF_DEBUG0_VSYNC_V(e)                      BF_LCDIF_DEBUG0_VSYNC(BV_LCDIF_DEBUG0_VSYNC__##e)
+#define BFM_LCDIF_DEBUG0_VSYNC_V(v)                     BM_LCDIF_DEBUG0_VSYNC
+#define BP_LCDIF_DEBUG0_CUR_FRAME_TX                    24
+#define BM_LCDIF_DEBUG0_CUR_FRAME_TX                    0x1000000
+#define BF_LCDIF_DEBUG0_CUR_FRAME_TX(v)                 (((v) & 0x1) << 24)
+#define BFM_LCDIF_DEBUG0_CUR_FRAME_TX(v)                BM_LCDIF_DEBUG0_CUR_FRAME_TX
+#define BF_LCDIF_DEBUG0_CUR_FRAME_TX_V(e)               BF_LCDIF_DEBUG0_CUR_FRAME_TX(BV_LCDIF_DEBUG0_CUR_FRAME_TX__##e)
+#define BFM_LCDIF_DEBUG0_CUR_FRAME_TX_V(v)              BM_LCDIF_DEBUG0_CUR_FRAME_TX
+#define BP_LCDIF_DEBUG0_EMPTY_WORD                      23
+#define BM_LCDIF_DEBUG0_EMPTY_WORD                      0x800000
+#define BF_LCDIF_DEBUG0_EMPTY_WORD(v)                   (((v) & 0x1) << 23)
+#define BFM_LCDIF_DEBUG0_EMPTY_WORD(v)                  BM_LCDIF_DEBUG0_EMPTY_WORD
+#define BF_LCDIF_DEBUG0_EMPTY_WORD_V(e)                 BF_LCDIF_DEBUG0_EMPTY_WORD(BV_LCDIF_DEBUG0_EMPTY_WORD__##e)
+#define BFM_LCDIF_DEBUG0_EMPTY_WORD_V(v)                BM_LCDIF_DEBUG0_EMPTY_WORD
+#define BP_LCDIF_DEBUG0_CUR_STATE                       16
+#define BM_LCDIF_DEBUG0_CUR_STATE                       0x7f0000
+#define BF_LCDIF_DEBUG0_CUR_STATE(v)                    (((v) & 0x7f) << 16)
+#define BFM_LCDIF_DEBUG0_CUR_STATE(v)                   BM_LCDIF_DEBUG0_CUR_STATE
+#define BF_LCDIF_DEBUG0_CUR_STATE_V(e)                  BF_LCDIF_DEBUG0_CUR_STATE(BV_LCDIF_DEBUG0_CUR_STATE__##e)
+#define BFM_LCDIF_DEBUG0_CUR_STATE_V(v)                 BM_LCDIF_DEBUG0_CUR_STATE
+#define BP_LCDIF_DEBUG0_PXP_LCDIF_B0_READY              15
+#define BM_LCDIF_DEBUG0_PXP_LCDIF_B0_READY              0x8000
+#define BF_LCDIF_DEBUG0_PXP_LCDIF_B0_READY(v)           (((v) & 0x1) << 15)
+#define BFM_LCDIF_DEBUG0_PXP_LCDIF_B0_READY(v)          BM_LCDIF_DEBUG0_PXP_LCDIF_B0_READY
+#define BF_LCDIF_DEBUG0_PXP_LCDIF_B0_READY_V(e)         BF_LCDIF_DEBUG0_PXP_LCDIF_B0_READY(BV_LCDIF_DEBUG0_PXP_LCDIF_B0_READY__##e)
+#define BFM_LCDIF_DEBUG0_PXP_LCDIF_B0_READY_V(v)        BM_LCDIF_DEBUG0_PXP_LCDIF_B0_READY
+#define BP_LCDIF_DEBUG0_LCDIF_PXP_B0_DONE               14
+#define BM_LCDIF_DEBUG0_LCDIF_PXP_B0_DONE               0x4000
+#define BF_LCDIF_DEBUG0_LCDIF_PXP_B0_DONE(v)            (((v) & 0x1) << 14)
+#define BFM_LCDIF_DEBUG0_LCDIF_PXP_B0_DONE(v)           BM_LCDIF_DEBUG0_LCDIF_PXP_B0_DONE
+#define BF_LCDIF_DEBUG0_LCDIF_PXP_B0_DONE_V(e)          BF_LCDIF_DEBUG0_LCDIF_PXP_B0_DONE(BV_LCDIF_DEBUG0_LCDIF_PXP_B0_DONE__##e)
+#define BFM_LCDIF_DEBUG0_LCDIF_PXP_B0_DONE_V(v)         BM_LCDIF_DEBUG0_LCDIF_PXP_B0_DONE
+#define BP_LCDIF_DEBUG0_PXP_LCDIF_B1_READY              13
+#define BM_LCDIF_DEBUG0_PXP_LCDIF_B1_READY              0x2000
+#define BF_LCDIF_DEBUG0_PXP_LCDIF_B1_READY(v)           (((v) & 0x1) << 13)
+#define BFM_LCDIF_DEBUG0_PXP_LCDIF_B1_READY(v)          BM_LCDIF_DEBUG0_PXP_LCDIF_B1_READY
+#define BF_LCDIF_DEBUG0_PXP_LCDIF_B1_READY_V(e)         BF_LCDIF_DEBUG0_PXP_LCDIF_B1_READY(BV_LCDIF_DEBUG0_PXP_LCDIF_B1_READY__##e)
+#define BFM_LCDIF_DEBUG0_PXP_LCDIF_B1_READY_V(v)        BM_LCDIF_DEBUG0_PXP_LCDIF_B1_READY
+#define BP_LCDIF_DEBUG0_LCDIF_PXP_B1_DONE               12
+#define BM_LCDIF_DEBUG0_LCDIF_PXP_B1_DONE               0x1000
+#define BF_LCDIF_DEBUG0_LCDIF_PXP_B1_DONE(v)            (((v) & 0x1) << 12)
+#define BFM_LCDIF_DEBUG0_LCDIF_PXP_B1_DONE(v)           BM_LCDIF_DEBUG0_LCDIF_PXP_B1_DONE
+#define BF_LCDIF_DEBUG0_LCDIF_PXP_B1_DONE_V(e)          BF_LCDIF_DEBUG0_LCDIF_PXP_B1_DONE(BV_LCDIF_DEBUG0_LCDIF_PXP_B1_DONE__##e)
+#define BFM_LCDIF_DEBUG0_LCDIF_PXP_B1_DONE_V(v)         BM_LCDIF_DEBUG0_LCDIF_PXP_B1_DONE
+#define BP_LCDIF_DEBUG0_GPMI_LCDIF_REQ                  11
+#define BM_LCDIF_DEBUG0_GPMI_LCDIF_REQ                  0x800
+#define BF_LCDIF_DEBUG0_GPMI_LCDIF_REQ(v)               (((v) & 0x1) << 11)
+#define BFM_LCDIF_DEBUG0_GPMI_LCDIF_REQ(v)              BM_LCDIF_DEBUG0_GPMI_LCDIF_REQ
+#define BF_LCDIF_DEBUG0_GPMI_LCDIF_REQ_V(e)             BF_LCDIF_DEBUG0_GPMI_LCDIF_REQ(BV_LCDIF_DEBUG0_GPMI_LCDIF_REQ__##e)
+#define BFM_LCDIF_DEBUG0_GPMI_LCDIF_REQ_V(v)            BM_LCDIF_DEBUG0_GPMI_LCDIF_REQ
+#define BP_LCDIF_DEBUG0_LCDIF_GPMI_GRANT                10
+#define BM_LCDIF_DEBUG0_LCDIF_GPMI_GRANT                0x400
+#define BF_LCDIF_DEBUG0_LCDIF_GPMI_GRANT(v)             (((v) & 0x1) << 10)
+#define BFM_LCDIF_DEBUG0_LCDIF_GPMI_GRANT(v)            BM_LCDIF_DEBUG0_LCDIF_GPMI_GRANT
+#define BF_LCDIF_DEBUG0_LCDIF_GPMI_GRANT_V(e)           BF_LCDIF_DEBUG0_LCDIF_GPMI_GRANT(BV_LCDIF_DEBUG0_LCDIF_GPMI_GRANT__##e)
+#define BFM_LCDIF_DEBUG0_LCDIF_GPMI_GRANT_V(v)          BM_LCDIF_DEBUG0_LCDIF_GPMI_GRANT
+#define BP_LCDIF_DEBUG0_RSRVD0                          0
+#define BM_LCDIF_DEBUG0_RSRVD0                          0x3ff
+#define BF_LCDIF_DEBUG0_RSRVD0(v)                       (((v) & 0x3ff) << 0)
+#define BFM_LCDIF_DEBUG0_RSRVD0(v)                      BM_LCDIF_DEBUG0_RSRVD0
+#define BF_LCDIF_DEBUG0_RSRVD0_V(e)                     BF_LCDIF_DEBUG0_RSRVD0(BV_LCDIF_DEBUG0_RSRVD0__##e)
+#define BFM_LCDIF_DEBUG0_RSRVD0_V(v)                    BM_LCDIF_DEBUG0_RSRVD0
+
+#define HW_LCDIF_DEBUG1                     HW(LCDIF_DEBUG1)
+#define HWA_LCDIF_DEBUG1                    (0x80030000 + 0x200)
+#define HWT_LCDIF_DEBUG1                    HWIO_32_RW
+#define HWN_LCDIF_DEBUG1                    LCDIF_DEBUG1
+#define HWI_LCDIF_DEBUG1                    
+#define BP_LCDIF_DEBUG1_H_DATA_COUNT        16
+#define BM_LCDIF_DEBUG1_H_DATA_COUNT        0xffff0000
+#define BF_LCDIF_DEBUG1_H_DATA_COUNT(v)     (((v) & 0xffff) << 16)
+#define BFM_LCDIF_DEBUG1_H_DATA_COUNT(v)    BM_LCDIF_DEBUG1_H_DATA_COUNT
+#define BF_LCDIF_DEBUG1_H_DATA_COUNT_V(e)   BF_LCDIF_DEBUG1_H_DATA_COUNT(BV_LCDIF_DEBUG1_H_DATA_COUNT__##e)
+#define BFM_LCDIF_DEBUG1_H_DATA_COUNT_V(v)  BM_LCDIF_DEBUG1_H_DATA_COUNT
+#define BP_LCDIF_DEBUG1_V_DATA_COUNT        0
+#define BM_LCDIF_DEBUG1_V_DATA_COUNT        0xffff
+#define BF_LCDIF_DEBUG1_V_DATA_COUNT(v)     (((v) & 0xffff) << 0)
+#define BFM_LCDIF_DEBUG1_V_DATA_COUNT(v)    BM_LCDIF_DEBUG1_V_DATA_COUNT
+#define BF_LCDIF_DEBUG1_V_DATA_COUNT_V(e)   BF_LCDIF_DEBUG1_V_DATA_COUNT(BV_LCDIF_DEBUG1_V_DATA_COUNT__##e)
+#define BFM_LCDIF_DEBUG1_V_DATA_COUNT_V(v)  BM_LCDIF_DEBUG1_V_DATA_COUNT
+
+#endif /* __HEADERGEN_IMX233_LCDIF_H__*/
diff --git a/firmware/target/arm/imx233/regs/imx233/lradc.h b/firmware/target/arm/imx233/regs/imx233/lradc.h
new file mode 100644
index 0000000000..14a483f43d
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/imx233/lradc.h
@@ -0,0 +1,1181 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * imx233 version: 2.4.0
+ * imx233 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_IMX233_LRADC_H__
+#define __HEADERGEN_IMX233_LRADC_H__
+
+#define HW_LRADC_CTRL0                              HW(LRADC_CTRL0)
+#define HWA_LRADC_CTRL0                             (0x80050000 + 0x0)
+#define HWT_LRADC_CTRL0                             HWIO_32_RW
+#define HWN_LRADC_CTRL0                             LRADC_CTRL0
+#define HWI_LRADC_CTRL0                             
+#define HW_LRADC_CTRL0_SET                          HW(LRADC_CTRL0_SET)
+#define HWA_LRADC_CTRL0_SET                         (HWA_LRADC_CTRL0 + 0x4)
+#define HWT_LRADC_CTRL0_SET                         HWIO_32_WO
+#define HWN_LRADC_CTRL0_SET                         LRADC_CTRL0
+#define HWI_LRADC_CTRL0_SET                         
+#define HW_LRADC_CTRL0_CLR                          HW(LRADC_CTRL0_CLR)
+#define HWA_LRADC_CTRL0_CLR                         (HWA_LRADC_CTRL0 + 0x8)
+#define HWT_LRADC_CTRL0_CLR                         HWIO_32_WO
+#define HWN_LRADC_CTRL0_CLR                         LRADC_CTRL0
+#define HWI_LRADC_CTRL0_CLR                         
+#define HW_LRADC_CTRL0_TOG                          HW(LRADC_CTRL0_TOG)
+#define HWA_LRADC_CTRL0_TOG                         (HWA_LRADC_CTRL0 + 0xc)
+#define HWT_LRADC_CTRL0_TOG                         HWIO_32_WO
+#define HWN_LRADC_CTRL0_TOG                         LRADC_CTRL0
+#define HWI_LRADC_CTRL0_TOG                         
+#define BP_LRADC_CTRL0_SFTRST                       31
+#define BM_LRADC_CTRL0_SFTRST                       0x80000000
+#define BF_LRADC_CTRL0_SFTRST(v)                    (((v) & 0x1) << 31)
+#define BFM_LRADC_CTRL0_SFTRST(v)                   BM_LRADC_CTRL0_SFTRST
+#define BF_LRADC_CTRL0_SFTRST_V(e)                  BF_LRADC_CTRL0_SFTRST(BV_LRADC_CTRL0_SFTRST__##e)
+#define BFM_LRADC_CTRL0_SFTRST_V(v)                 BM_LRADC_CTRL0_SFTRST
+#define BP_LRADC_CTRL0_CLKGATE                      30
+#define BM_LRADC_CTRL0_CLKGATE                      0x40000000
+#define BF_LRADC_CTRL0_CLKGATE(v)                   (((v) & 0x1) << 30)
+#define BFM_LRADC_CTRL0_CLKGATE(v)                  BM_LRADC_CTRL0_CLKGATE
+#define BF_LRADC_CTRL0_CLKGATE_V(e)                 BF_LRADC_CTRL0_CLKGATE(BV_LRADC_CTRL0_CLKGATE__##e)
+#define BFM_LRADC_CTRL0_CLKGATE_V(v)                BM_LRADC_CTRL0_CLKGATE
+#define BP_LRADC_CTRL0_RSRVD2                       22
+#define BM_LRADC_CTRL0_RSRVD2                       0x3fc00000
+#define BF_LRADC_CTRL0_RSRVD2(v)                    (((v) & 0xff) << 22)
+#define BFM_LRADC_CTRL0_RSRVD2(v)                   BM_LRADC_CTRL0_RSRVD2
+#define BF_LRADC_CTRL0_RSRVD2_V(e)                  BF_LRADC_CTRL0_RSRVD2(BV_LRADC_CTRL0_RSRVD2__##e)
+#define BFM_LRADC_CTRL0_RSRVD2_V(v)                 BM_LRADC_CTRL0_RSRVD2
+#define BP_LRADC_CTRL0_ONCHIP_GROUNDREF             21
+#define BM_LRADC_CTRL0_ONCHIP_GROUNDREF             0x200000
+#define BV_LRADC_CTRL0_ONCHIP_GROUNDREF__OFF        0x0
+#define BV_LRADC_CTRL0_ONCHIP_GROUNDREF__ON         0x1
+#define BF_LRADC_CTRL0_ONCHIP_GROUNDREF(v)          (((v) & 0x1) << 21)
+#define BFM_LRADC_CTRL0_ONCHIP_GROUNDREF(v)         BM_LRADC_CTRL0_ONCHIP_GROUNDREF
+#define BF_LRADC_CTRL0_ONCHIP_GROUNDREF_V(e)        BF_LRADC_CTRL0_ONCHIP_GROUNDREF(BV_LRADC_CTRL0_ONCHIP_GROUNDREF__##e)
+#define BFM_LRADC_CTRL0_ONCHIP_GROUNDREF_V(v)       BM_LRADC_CTRL0_ONCHIP_GROUNDREF
+#define BP_LRADC_CTRL0_TOUCH_DETECT_ENABLE          20
+#define BM_LRADC_CTRL0_TOUCH_DETECT_ENABLE          0x100000
+#define BV_LRADC_CTRL0_TOUCH_DETECT_ENABLE__OFF     0x0
+#define BV_LRADC_CTRL0_TOUCH_DETECT_ENABLE__ON      0x1
+#define BF_LRADC_CTRL0_TOUCH_DETECT_ENABLE(v)       (((v) & 0x1) << 20)
+#define BFM_LRADC_CTRL0_TOUCH_DETECT_ENABLE(v)      BM_LRADC_CTRL0_TOUCH_DETECT_ENABLE
+#define BF_LRADC_CTRL0_TOUCH_DETECT_ENABLE_V(e)     BF_LRADC_CTRL0_TOUCH_DETECT_ENABLE(BV_LRADC_CTRL0_TOUCH_DETECT_ENABLE__##e)
+#define BFM_LRADC_CTRL0_TOUCH_DETECT_ENABLE_V(v)    BM_LRADC_CTRL0_TOUCH_DETECT_ENABLE
+#define BP_LRADC_CTRL0_YMINUS_ENABLE                19
+#define BM_LRADC_CTRL0_YMINUS_ENABLE                0x80000
+#define BV_LRADC_CTRL0_YMINUS_ENABLE__OFF           0x0
+#define BV_LRADC_CTRL0_YMINUS_ENABLE__ON            0x1
+#define BF_LRADC_CTRL0_YMINUS_ENABLE(v)             (((v) & 0x1) << 19)
+#define BFM_LRADC_CTRL0_YMINUS_ENABLE(v)            BM_LRADC_CTRL0_YMINUS_ENABLE
+#define BF_LRADC_CTRL0_YMINUS_ENABLE_V(e)           BF_LRADC_CTRL0_YMINUS_ENABLE(BV_LRADC_CTRL0_YMINUS_ENABLE__##e)
+#define BFM_LRADC_CTRL0_YMINUS_ENABLE_V(v)          BM_LRADC_CTRL0_YMINUS_ENABLE
+#define BP_LRADC_CTRL0_XMINUS_ENABLE                18
+#define BM_LRADC_CTRL0_XMINUS_ENABLE                0x40000
+#define BV_LRADC_CTRL0_XMINUS_ENABLE__OFF           0x0
+#define BV_LRADC_CTRL0_XMINUS_ENABLE__ON            0x1
+#define BF_LRADC_CTRL0_XMINUS_ENABLE(v)             (((v) & 0x1) << 18)
+#define BFM_LRADC_CTRL0_XMINUS_ENABLE(v)            BM_LRADC_CTRL0_XMINUS_ENABLE
+#define BF_LRADC_CTRL0_XMINUS_ENABLE_V(e)           BF_LRADC_CTRL0_XMINUS_ENABLE(BV_LRADC_CTRL0_XMINUS_ENABLE__##e)
+#define BFM_LRADC_CTRL0_XMINUS_ENABLE_V(v)          BM_LRADC_CTRL0_XMINUS_ENABLE
+#define BP_LRADC_CTRL0_YPLUS_ENABLE                 17
+#define BM_LRADC_CTRL0_YPLUS_ENABLE                 0x20000
+#define BV_LRADC_CTRL0_YPLUS_ENABLE__OFF            0x0
+#define BV_LRADC_CTRL0_YPLUS_ENABLE__ON             0x1
+#define BF_LRADC_CTRL0_YPLUS_ENABLE(v)              (((v) & 0x1) << 17)
+#define BFM_LRADC_CTRL0_YPLUS_ENABLE(v)             BM_LRADC_CTRL0_YPLUS_ENABLE
+#define BF_LRADC_CTRL0_YPLUS_ENABLE_V(e)            BF_LRADC_CTRL0_YPLUS_ENABLE(BV_LRADC_CTRL0_YPLUS_ENABLE__##e)
+#define BFM_LRADC_CTRL0_YPLUS_ENABLE_V(v)           BM_LRADC_CTRL0_YPLUS_ENABLE
+#define BP_LRADC_CTRL0_XPLUS_ENABLE                 16
+#define BM_LRADC_CTRL0_XPLUS_ENABLE                 0x10000
+#define BV_LRADC_CTRL0_XPLUS_ENABLE__OFF            0x0
+#define BV_LRADC_CTRL0_XPLUS_ENABLE__ON             0x1
+#define BF_LRADC_CTRL0_XPLUS_ENABLE(v)              (((v) & 0x1) << 16)
+#define BFM_LRADC_CTRL0_XPLUS_ENABLE(v)             BM_LRADC_CTRL0_XPLUS_ENABLE
+#define BF_LRADC_CTRL0_XPLUS_ENABLE_V(e)            BF_LRADC_CTRL0_XPLUS_ENABLE(BV_LRADC_CTRL0_XPLUS_ENABLE__##e)
+#define BFM_LRADC_CTRL0_XPLUS_ENABLE_V(v)           BM_LRADC_CTRL0_XPLUS_ENABLE
+#define BP_LRADC_CTRL0_RSRVD1                       8
+#define BM_LRADC_CTRL0_RSRVD1                       0xff00
+#define BF_LRADC_CTRL0_RSRVD1(v)                    (((v) & 0xff) << 8)
+#define BFM_LRADC_CTRL0_RSRVD1(v)                   BM_LRADC_CTRL0_RSRVD1
+#define BF_LRADC_CTRL0_RSRVD1_V(e)                  BF_LRADC_CTRL0_RSRVD1(BV_LRADC_CTRL0_RSRVD1__##e)
+#define BFM_LRADC_CTRL0_RSRVD1_V(v)                 BM_LRADC_CTRL0_RSRVD1
+#define BP_LRADC_CTRL0_SCHEDULE                     0
+#define BM_LRADC_CTRL0_SCHEDULE                     0xff
+#define BF_LRADC_CTRL0_SCHEDULE(v)                  (((v) & 0xff) << 0)
+#define BFM_LRADC_CTRL0_SCHEDULE(v)                 BM_LRADC_CTRL0_SCHEDULE
+#define BF_LRADC_CTRL0_SCHEDULE_V(e)                BF_LRADC_CTRL0_SCHEDULE(BV_LRADC_CTRL0_SCHEDULE__##e)
+#define BFM_LRADC_CTRL0_SCHEDULE_V(v)               BM_LRADC_CTRL0_SCHEDULE
+
+#define HW_LRADC_CTRL1                              HW(LRADC_CTRL1)
+#define HWA_LRADC_CTRL1                             (0x80050000 + 0x10)
+#define HWT_LRADC_CTRL1                             HWIO_32_RW
+#define HWN_LRADC_CTRL1                             LRADC_CTRL1
+#define HWI_LRADC_CTRL1                             
+#define HW_LRADC_CTRL1_SET                          HW(LRADC_CTRL1_SET)
+#define HWA_LRADC_CTRL1_SET                         (HWA_LRADC_CTRL1 + 0x4)
+#define HWT_LRADC_CTRL1_SET                         HWIO_32_WO
+#define HWN_LRADC_CTRL1_SET                         LRADC_CTRL1
+#define HWI_LRADC_CTRL1_SET                         
+#define HW_LRADC_CTRL1_CLR                          HW(LRADC_CTRL1_CLR)
+#define HWA_LRADC_CTRL1_CLR                         (HWA_LRADC_CTRL1 + 0x8)
+#define HWT_LRADC_CTRL1_CLR                         HWIO_32_WO
+#define HWN_LRADC_CTRL1_CLR                         LRADC_CTRL1
+#define HWI_LRADC_CTRL1_CLR                         
+#define HW_LRADC_CTRL1_TOG                          HW(LRADC_CTRL1_TOG)
+#define HWA_LRADC_CTRL1_TOG                         (HWA_LRADC_CTRL1 + 0xc)
+#define HWT_LRADC_CTRL1_TOG                         HWIO_32_WO
+#define HWN_LRADC_CTRL1_TOG                         LRADC_CTRL1
+#define HWI_LRADC_CTRL1_TOG                         
+#define BP_LRADC_CTRL1_RSRVD2                       25
+#define BM_LRADC_CTRL1_RSRVD2                       0xfe000000
+#define BF_LRADC_CTRL1_RSRVD2(v)                    (((v) & 0x7f) << 25)
+#define BFM_LRADC_CTRL1_RSRVD2(v)                   BM_LRADC_CTRL1_RSRVD2
+#define BF_LRADC_CTRL1_RSRVD2_V(e)                  BF_LRADC_CTRL1_RSRVD2(BV_LRADC_CTRL1_RSRVD2__##e)
+#define BFM_LRADC_CTRL1_RSRVD2_V(v)                 BM_LRADC_CTRL1_RSRVD2
+#define BP_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN          24
+#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN          0x1000000
+#define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN__DISABLE 0x0
+#define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN__ENABLE  0x1
+#define BF_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN(v)       (((v) & 0x1) << 24)
+#define BFM_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN(v)      BM_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN
+#define BF_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN_V(e)     BF_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN(BV_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN__##e)
+#define BFM_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN_V(v)    BM_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN
+#define BP_LRADC_CTRL1_LRADC7_IRQ_EN                23
+#define BM_LRADC_CTRL1_LRADC7_IRQ_EN                0x800000
+#define BV_LRADC_CTRL1_LRADC7_IRQ_EN__DISABLE       0x0
+#define BV_LRADC_CTRL1_LRADC7_IRQ_EN__ENABLE        0x1
+#define BF_LRADC_CTRL1_LRADC7_IRQ_EN(v)             (((v) & 0x1) << 23)
+#define BFM_LRADC_CTRL1_LRADC7_IRQ_EN(v)            BM_LRADC_CTRL1_LRADC7_IRQ_EN
+#define BF_LRADC_CTRL1_LRADC7_IRQ_EN_V(e)           BF_LRADC_CTRL1_LRADC7_IRQ_EN(BV_LRADC_CTRL1_LRADC7_IRQ_EN__##e)
+#define BFM_LRADC_CTRL1_LRADC7_IRQ_EN_V(v)          BM_LRADC_CTRL1_LRADC7_IRQ_EN
+#define BP_LRADC_CTRL1_LRADC6_IRQ_EN                22
+#define BM_LRADC_CTRL1_LRADC6_IRQ_EN                0x400000
+#define BV_LRADC_CTRL1_LRADC6_IRQ_EN__DISABLE       0x0
+#define BV_LRADC_CTRL1_LRADC6_IRQ_EN__ENABLE        0x1
+#define BF_LRADC_CTRL1_LRADC6_IRQ_EN(v)             (((v) & 0x1) << 22)
+#define BFM_LRADC_CTRL1_LRADC6_IRQ_EN(v)            BM_LRADC_CTRL1_LRADC6_IRQ_EN
+#define BF_LRADC_CTRL1_LRADC6_IRQ_EN_V(e)           BF_LRADC_CTRL1_LRADC6_IRQ_EN(BV_LRADC_CTRL1_LRADC6_IRQ_EN__##e)
+#define BFM_LRADC_CTRL1_LRADC6_IRQ_EN_V(v)          BM_LRADC_CTRL1_LRADC6_IRQ_EN
+#define BP_LRADC_CTRL1_LRADC5_IRQ_EN                21
+#define BM_LRADC_CTRL1_LRADC5_IRQ_EN                0x200000
+#define BV_LRADC_CTRL1_LRADC5_IRQ_EN__DISABLE       0x0
+#define BV_LRADC_CTRL1_LRADC5_IRQ_EN__ENABLE        0x1
+#define BF_LRADC_CTRL1_LRADC5_IRQ_EN(v)             (((v) & 0x1) << 21)
+#define BFM_LRADC_CTRL1_LRADC5_IRQ_EN(v)            BM_LRADC_CTRL1_LRADC5_IRQ_EN
+#define BF_LRADC_CTRL1_LRADC5_IRQ_EN_V(e)           BF_LRADC_CTRL1_LRADC5_IRQ_EN(BV_LRADC_CTRL1_LRADC5_IRQ_EN__##e)
+#define BFM_LRADC_CTRL1_LRADC5_IRQ_EN_V(v)          BM_LRADC_CTRL1_LRADC5_IRQ_EN
+#define BP_LRADC_CTRL1_LRADC4_IRQ_EN                20
+#define BM_LRADC_CTRL1_LRADC4_IRQ_EN                0x100000
+#define BV_LRADC_CTRL1_LRADC4_IRQ_EN__DISABLE       0x0
+#define BV_LRADC_CTRL1_LRADC4_IRQ_EN__ENABLE        0x1
+#define BF_LRADC_CTRL1_LRADC4_IRQ_EN(v)             (((v) & 0x1) << 20)
+#define BFM_LRADC_CTRL1_LRADC4_IRQ_EN(v)            BM_LRADC_CTRL1_LRADC4_IRQ_EN
+#define BF_LRADC_CTRL1_LRADC4_IRQ_EN_V(e)           BF_LRADC_CTRL1_LRADC4_IRQ_EN(BV_LRADC_CTRL1_LRADC4_IRQ_EN__##e)
+#define BFM_LRADC_CTRL1_LRADC4_IRQ_EN_V(v)          BM_LRADC_CTRL1_LRADC4_IRQ_EN
+#define BP_LRADC_CTRL1_LRADC3_IRQ_EN                19
+#define BM_LRADC_CTRL1_LRADC3_IRQ_EN                0x80000
+#define BV_LRADC_CTRL1_LRADC3_IRQ_EN__DISABLE       0x0
+#define BV_LRADC_CTRL1_LRADC3_IRQ_EN__ENABLE        0x1
+#define BF_LRADC_CTRL1_LRADC3_IRQ_EN(v)             (((v) & 0x1) << 19)
+#define BFM_LRADC_CTRL1_LRADC3_IRQ_EN(v)            BM_LRADC_CTRL1_LRADC3_IRQ_EN
+#define BF_LRADC_CTRL1_LRADC3_IRQ_EN_V(e)           BF_LRADC_CTRL1_LRADC3_IRQ_EN(BV_LRADC_CTRL1_LRADC3_IRQ_EN__##e)
+#define BFM_LRADC_CTRL1_LRADC3_IRQ_EN_V(v)          BM_LRADC_CTRL1_LRADC3_IRQ_EN
+#define BP_LRADC_CTRL1_LRADC2_IRQ_EN                18
+#define BM_LRADC_CTRL1_LRADC2_IRQ_EN                0x40000
+#define BV_LRADC_CTRL1_LRADC2_IRQ_EN__DISABLE       0x0
+#define BV_LRADC_CTRL1_LRADC2_IRQ_EN__ENABLE        0x1
+#define BF_LRADC_CTRL1_LRADC2_IRQ_EN(v)             (((v) & 0x1) << 18)
+#define BFM_LRADC_CTRL1_LRADC2_IRQ_EN(v)            BM_LRADC_CTRL1_LRADC2_IRQ_EN
+#define BF_LRADC_CTRL1_LRADC2_IRQ_EN_V(e)           BF_LRADC_CTRL1_LRADC2_IRQ_EN(BV_LRADC_CTRL1_LRADC2_IRQ_EN__##e)
+#define BFM_LRADC_CTRL1_LRADC2_IRQ_EN_V(v)          BM_LRADC_CTRL1_LRADC2_IRQ_EN
+#define BP_LRADC_CTRL1_LRADC1_IRQ_EN                17
+#define BM_LRADC_CTRL1_LRADC1_IRQ_EN                0x20000
+#define BV_LRADC_CTRL1_LRADC1_IRQ_EN__DISABLE       0x0
+#define BV_LRADC_CTRL1_LRADC1_IRQ_EN__ENABLE        0x1
+#define BF_LRADC_CTRL1_LRADC1_IRQ_EN(v)             (((v) & 0x1) << 17)
+#define BFM_LRADC_CTRL1_LRADC1_IRQ_EN(v)            BM_LRADC_CTRL1_LRADC1_IRQ_EN
+#define BF_LRADC_CTRL1_LRADC1_IRQ_EN_V(e)           BF_LRADC_CTRL1_LRADC1_IRQ_EN(BV_LRADC_CTRL1_LRADC1_IRQ_EN__##e)
+#define BFM_LRADC_CTRL1_LRADC1_IRQ_EN_V(v)          BM_LRADC_CTRL1_LRADC1_IRQ_EN
+#define BP_LRADC_CTRL1_LRADC0_IRQ_EN                16
+#define BM_LRADC_CTRL1_LRADC0_IRQ_EN                0x10000
+#define BV_LRADC_CTRL1_LRADC0_IRQ_EN__DISABLE       0x0
+#define BV_LRADC_CTRL1_LRADC0_IRQ_EN__ENABLE        0x1
+#define BF_LRADC_CTRL1_LRADC0_IRQ_EN(v)             (((v) & 0x1) << 16)
+#define BFM_LRADC_CTRL1_LRADC0_IRQ_EN(v)            BM_LRADC_CTRL1_LRADC0_IRQ_EN
+#define BF_LRADC_CTRL1_LRADC0_IRQ_EN_V(e)           BF_LRADC_CTRL1_LRADC0_IRQ_EN(BV_LRADC_CTRL1_LRADC0_IRQ_EN__##e)
+#define BFM_LRADC_CTRL1_LRADC0_IRQ_EN_V(v)          BM_LRADC_CTRL1_LRADC0_IRQ_EN
+#define BP_LRADC_CTRL1_RSRVD1                       9
+#define BM_LRADC_CTRL1_RSRVD1                       0xfe00
+#define BF_LRADC_CTRL1_RSRVD1(v)                    (((v) & 0x7f) << 9)
+#define BFM_LRADC_CTRL1_RSRVD1(v)                   BM_LRADC_CTRL1_RSRVD1
+#define BF_LRADC_CTRL1_RSRVD1_V(e)                  BF_LRADC_CTRL1_RSRVD1(BV_LRADC_CTRL1_RSRVD1__##e)
+#define BFM_LRADC_CTRL1_RSRVD1_V(v)                 BM_LRADC_CTRL1_RSRVD1
+#define BP_LRADC_CTRL1_TOUCH_DETECT_IRQ             8
+#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ             0x100
+#define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ__CLEAR      0x0
+#define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ__PENDING    0x1
+#define BF_LRADC_CTRL1_TOUCH_DETECT_IRQ(v)          (((v) & 0x1) << 8)
+#define BFM_LRADC_CTRL1_TOUCH_DETECT_IRQ(v)         BM_LRADC_CTRL1_TOUCH_DETECT_IRQ
+#define BF_LRADC_CTRL1_TOUCH_DETECT_IRQ_V(e)        BF_LRADC_CTRL1_TOUCH_DETECT_IRQ(BV_LRADC_CTRL1_TOUCH_DETECT_IRQ__##e)
+#define BFM_LRADC_CTRL1_TOUCH_DETECT_IRQ_V(v)       BM_LRADC_CTRL1_TOUCH_DETECT_IRQ
+#define BP_LRADC_CTRL1_LRADC7_IRQ                   7
+#define BM_LRADC_CTRL1_LRADC7_IRQ                   0x80
+#define BV_LRADC_CTRL1_LRADC7_IRQ__CLEAR            0x0
+#define BV_LRADC_CTRL1_LRADC7_IRQ__PENDING          0x1
+#define BF_LRADC_CTRL1_LRADC7_IRQ(v)                (((v) & 0x1) << 7)
+#define BFM_LRADC_CTRL1_LRADC7_IRQ(v)               BM_LRADC_CTRL1_LRADC7_IRQ
+#define BF_LRADC_CTRL1_LRADC7_IRQ_V(e)              BF_LRADC_CTRL1_LRADC7_IRQ(BV_LRADC_CTRL1_LRADC7_IRQ__##e)
+#define BFM_LRADC_CTRL1_LRADC7_IRQ_V(v)             BM_LRADC_CTRL1_LRADC7_IRQ
+#define BP_LRADC_CTRL1_LRADC6_IRQ                   6
+#define BM_LRADC_CTRL1_LRADC6_IRQ                   0x40
+#define BV_LRADC_CTRL1_LRADC6_IRQ__CLEAR            0x0
+#define BV_LRADC_CTRL1_LRADC6_IRQ__PENDING          0x1
+#define BF_LRADC_CTRL1_LRADC6_IRQ(v)                (((v) & 0x1) << 6)
+#define BFM_LRADC_CTRL1_LRADC6_IRQ(v)               BM_LRADC_CTRL1_LRADC6_IRQ
+#define BF_LRADC_CTRL1_LRADC6_IRQ_V(e)              BF_LRADC_CTRL1_LRADC6_IRQ(BV_LRADC_CTRL1_LRADC6_IRQ__##e)
+#define BFM_LRADC_CTRL1_LRADC6_IRQ_V(v)             BM_LRADC_CTRL1_LRADC6_IRQ
+#define BP_LRADC_CTRL1_LRADC5_IRQ                   5
+#define BM_LRADC_CTRL1_LRADC5_IRQ                   0x20
+#define BV_LRADC_CTRL1_LRADC5_IRQ__CLEAR            0x0
+#define BV_LRADC_CTRL1_LRADC5_IRQ__PENDING          0x1
+#define BF_LRADC_CTRL1_LRADC5_IRQ(v)                (((v) & 0x1) << 5)
+#define BFM_LRADC_CTRL1_LRADC5_IRQ(v)               BM_LRADC_CTRL1_LRADC5_IRQ
+#define BF_LRADC_CTRL1_LRADC5_IRQ_V(e)              BF_LRADC_CTRL1_LRADC5_IRQ(BV_LRADC_CTRL1_LRADC5_IRQ__##e)
+#define BFM_LRADC_CTRL1_LRADC5_IRQ_V(v)             BM_LRADC_CTRL1_LRADC5_IRQ
+#define BP_LRADC_CTRL1_LRADC4_IRQ                   4
+#define BM_LRADC_CTRL1_LRADC4_IRQ                   0x10
+#define BV_LRADC_CTRL1_LRADC4_IRQ__CLEAR            0x0
+#define BV_LRADC_CTRL1_LRADC4_IRQ__PENDING          0x1
+#define BF_LRADC_CTRL1_LRADC4_IRQ(v)                (((v) & 0x1) << 4)
+#define BFM_LRADC_CTRL1_LRADC4_IRQ(v)               BM_LRADC_CTRL1_LRADC4_IRQ
+#define BF_LRADC_CTRL1_LRADC4_IRQ_V(e)              BF_LRADC_CTRL1_LRADC4_IRQ(BV_LRADC_CTRL1_LRADC4_IRQ__##e)
+#define BFM_LRADC_CTRL1_LRADC4_IRQ_V(v)             BM_LRADC_CTRL1_LRADC4_IRQ
+#define BP_LRADC_CTRL1_LRADC3_IRQ                   3
+#define BM_LRADC_CTRL1_LRADC3_IRQ                   0x8
+#define BV_LRADC_CTRL1_LRADC3_IRQ__CLEAR            0x0
+#define BV_LRADC_CTRL1_LRADC3_IRQ__PENDING          0x1
+#define BF_LRADC_CTRL1_LRADC3_IRQ(v)                (((v) & 0x1) << 3)
+#define BFM_LRADC_CTRL1_LRADC3_IRQ(v)               BM_LRADC_CTRL1_LRADC3_IRQ
+#define BF_LRADC_CTRL1_LRADC3_IRQ_V(e)              BF_LRADC_CTRL1_LRADC3_IRQ(BV_LRADC_CTRL1_LRADC3_IRQ__##e)
+#define BFM_LRADC_CTRL1_LRADC3_IRQ_V(v)             BM_LRADC_CTRL1_LRADC3_IRQ
+#define BP_LRADC_CTRL1_LRADC2_IRQ                   2
+#define BM_LRADC_CTRL1_LRADC2_IRQ                   0x4
+#define BV_LRADC_CTRL1_LRADC2_IRQ__CLEAR            0x0
+#define BV_LRADC_CTRL1_LRADC2_IRQ__PENDING          0x1
+#define BF_LRADC_CTRL1_LRADC2_IRQ(v)                (((v) & 0x1) << 2)
+#define BFM_LRADC_CTRL1_LRADC2_IRQ(v)               BM_LRADC_CTRL1_LRADC2_IRQ
+#define BF_LRADC_CTRL1_LRADC2_IRQ_V(e)              BF_LRADC_CTRL1_LRADC2_IRQ(BV_LRADC_CTRL1_LRADC2_IRQ__##e)
+#define BFM_LRADC_CTRL1_LRADC2_IRQ_V(v)             BM_LRADC_CTRL1_LRADC2_IRQ
+#define BP_LRADC_CTRL1_LRADC1_IRQ                   1
+#define BM_LRADC_CTRL1_LRADC1_IRQ                   0x2
+#define BV_LRADC_CTRL1_LRADC1_IRQ__CLEAR            0x0
+#define BV_LRADC_CTRL1_LRADC1_IRQ__PENDING          0x1
+#define BF_LRADC_CTRL1_LRADC1_IRQ(v)                (((v) & 0x1) << 1)
+#define BFM_LRADC_CTRL1_LRADC1_IRQ(v)               BM_LRADC_CTRL1_LRADC1_IRQ
+#define BF_LRADC_CTRL1_LRADC1_IRQ_V(e)              BF_LRADC_CTRL1_LRADC1_IRQ(BV_LRADC_CTRL1_LRADC1_IRQ__##e)
+#define BFM_LRADC_CTRL1_LRADC1_IRQ_V(v)             BM_LRADC_CTRL1_LRADC1_IRQ
+#define BP_LRADC_CTRL1_LRADC0_IRQ                   0
+#define BM_LRADC_CTRL1_LRADC0_IRQ                   0x1
+#define BV_LRADC_CTRL1_LRADC0_IRQ__CLEAR            0x0
+#define BV_LRADC_CTRL1_LRADC0_IRQ__PENDING          0x1
+#define BF_LRADC_CTRL1_LRADC0_IRQ(v)                (((v) & 0x1) << 0)
+#define BFM_LRADC_CTRL1_LRADC0_IRQ(v)               BM_LRADC_CTRL1_LRADC0_IRQ
+#define BF_LRADC_CTRL1_LRADC0_IRQ_V(e)              BF_LRADC_CTRL1_LRADC0_IRQ(BV_LRADC_CTRL1_LRADC0_IRQ__##e)
+#define BFM_LRADC_CTRL1_LRADC0_IRQ_V(v)             BM_LRADC_CTRL1_LRADC0_IRQ
+
+#define HW_LRADC_CTRL2                                  HW(LRADC_CTRL2)
+#define HWA_LRADC_CTRL2                                 (0x80050000 + 0x20)
+#define HWT_LRADC_CTRL2                                 HWIO_32_RW
+#define HWN_LRADC_CTRL2                                 LRADC_CTRL2
+#define HWI_LRADC_CTRL2                                 
+#define HW_LRADC_CTRL2_SET                              HW(LRADC_CTRL2_SET)
+#define HWA_LRADC_CTRL2_SET                             (HWA_LRADC_CTRL2 + 0x4)
+#define HWT_LRADC_CTRL2_SET                             HWIO_32_WO
+#define HWN_LRADC_CTRL2_SET                             LRADC_CTRL2
+#define HWI_LRADC_CTRL2_SET                             
+#define HW_LRADC_CTRL2_CLR                              HW(LRADC_CTRL2_CLR)
+#define HWA_LRADC_CTRL2_CLR                             (HWA_LRADC_CTRL2 + 0x8)
+#define HWT_LRADC_CTRL2_CLR                             HWIO_32_WO
+#define HWN_LRADC_CTRL2_CLR                             LRADC_CTRL2
+#define HWI_LRADC_CTRL2_CLR                             
+#define HW_LRADC_CTRL2_TOG                              HW(LRADC_CTRL2_TOG)
+#define HWA_LRADC_CTRL2_TOG                             (HWA_LRADC_CTRL2 + 0xc)
+#define HWT_LRADC_CTRL2_TOG                             HWIO_32_WO
+#define HWN_LRADC_CTRL2_TOG                             LRADC_CTRL2
+#define HWI_LRADC_CTRL2_TOG                             
+#define BP_LRADC_CTRL2_DIVIDE_BY_TWO                    24
+#define BM_LRADC_CTRL2_DIVIDE_BY_TWO                    0xff000000
+#define BF_LRADC_CTRL2_DIVIDE_BY_TWO(v)                 (((v) & 0xff) << 24)
+#define BFM_LRADC_CTRL2_DIVIDE_BY_TWO(v)                BM_LRADC_CTRL2_DIVIDE_BY_TWO
+#define BF_LRADC_CTRL2_DIVIDE_BY_TWO_V(e)               BF_LRADC_CTRL2_DIVIDE_BY_TWO(BV_LRADC_CTRL2_DIVIDE_BY_TWO__##e)
+#define BFM_LRADC_CTRL2_DIVIDE_BY_TWO_V(v)              BM_LRADC_CTRL2_DIVIDE_BY_TWO
+#define BP_LRADC_CTRL2_BL_AMP_BYPASS                    23
+#define BM_LRADC_CTRL2_BL_AMP_BYPASS                    0x800000
+#define BV_LRADC_CTRL2_BL_AMP_BYPASS__DISABLE           0x0
+#define BV_LRADC_CTRL2_BL_AMP_BYPASS__ENABLE            0x1
+#define BF_LRADC_CTRL2_BL_AMP_BYPASS(v)                 (((v) & 0x1) << 23)
+#define BFM_LRADC_CTRL2_BL_AMP_BYPASS(v)                BM_LRADC_CTRL2_BL_AMP_BYPASS
+#define BF_LRADC_CTRL2_BL_AMP_BYPASS_V(e)               BF_LRADC_CTRL2_BL_AMP_BYPASS(BV_LRADC_CTRL2_BL_AMP_BYPASS__##e)
+#define BFM_LRADC_CTRL2_BL_AMP_BYPASS_V(v)              BM_LRADC_CTRL2_BL_AMP_BYPASS
+#define BP_LRADC_CTRL2_BL_ENABLE                        22
+#define BM_LRADC_CTRL2_BL_ENABLE                        0x400000
+#define BF_LRADC_CTRL2_BL_ENABLE(v)                     (((v) & 0x1) << 22)
+#define BFM_LRADC_CTRL2_BL_ENABLE(v)                    BM_LRADC_CTRL2_BL_ENABLE
+#define BF_LRADC_CTRL2_BL_ENABLE_V(e)                   BF_LRADC_CTRL2_BL_ENABLE(BV_LRADC_CTRL2_BL_ENABLE__##e)
+#define BFM_LRADC_CTRL2_BL_ENABLE_V(v)                  BM_LRADC_CTRL2_BL_ENABLE
+#define BP_LRADC_CTRL2_BL_MUX_SELECT                    21
+#define BM_LRADC_CTRL2_BL_MUX_SELECT                    0x200000
+#define BF_LRADC_CTRL2_BL_MUX_SELECT(v)                 (((v) & 0x1) << 21)
+#define BFM_LRADC_CTRL2_BL_MUX_SELECT(v)                BM_LRADC_CTRL2_BL_MUX_SELECT
+#define BF_LRADC_CTRL2_BL_MUX_SELECT_V(e)               BF_LRADC_CTRL2_BL_MUX_SELECT(BV_LRADC_CTRL2_BL_MUX_SELECT__##e)
+#define BFM_LRADC_CTRL2_BL_MUX_SELECT_V(v)              BM_LRADC_CTRL2_BL_MUX_SELECT
+#define BP_LRADC_CTRL2_BL_BRIGHTNESS                    16
+#define BM_LRADC_CTRL2_BL_BRIGHTNESS                    0x1f0000
+#define BF_LRADC_CTRL2_BL_BRIGHTNESS(v)                 (((v) & 0x1f) << 16)
+#define BFM_LRADC_CTRL2_BL_BRIGHTNESS(v)                BM_LRADC_CTRL2_BL_BRIGHTNESS
+#define BF_LRADC_CTRL2_BL_BRIGHTNESS_V(e)               BF_LRADC_CTRL2_BL_BRIGHTNESS(BV_LRADC_CTRL2_BL_BRIGHTNESS__##e)
+#define BFM_LRADC_CTRL2_BL_BRIGHTNESS_V(v)              BM_LRADC_CTRL2_BL_BRIGHTNESS
+#define BP_LRADC_CTRL2_TEMPSENSE_PWD                    15
+#define BM_LRADC_CTRL2_TEMPSENSE_PWD                    0x8000
+#define BV_LRADC_CTRL2_TEMPSENSE_PWD__ENABLE            0x0
+#define BV_LRADC_CTRL2_TEMPSENSE_PWD__DISABLE           0x1
+#define BF_LRADC_CTRL2_TEMPSENSE_PWD(v)                 (((v) & 0x1) << 15)
+#define BFM_LRADC_CTRL2_TEMPSENSE_PWD(v)                BM_LRADC_CTRL2_TEMPSENSE_PWD
+#define BF_LRADC_CTRL2_TEMPSENSE_PWD_V(e)               BF_LRADC_CTRL2_TEMPSENSE_PWD(BV_LRADC_CTRL2_TEMPSENSE_PWD__##e)
+#define BFM_LRADC_CTRL2_TEMPSENSE_PWD_V(v)              BM_LRADC_CTRL2_TEMPSENSE_PWD
+#define BP_LRADC_CTRL2_RSRVD1                           14
+#define BM_LRADC_CTRL2_RSRVD1                           0x4000
+#define BF_LRADC_CTRL2_RSRVD1(v)                        (((v) & 0x1) << 14)
+#define BFM_LRADC_CTRL2_RSRVD1(v)                       BM_LRADC_CTRL2_RSRVD1
+#define BF_LRADC_CTRL2_RSRVD1_V(e)                      BF_LRADC_CTRL2_RSRVD1(BV_LRADC_CTRL2_RSRVD1__##e)
+#define BFM_LRADC_CTRL2_RSRVD1_V(v)                     BM_LRADC_CTRL2_RSRVD1
+#define BP_LRADC_CTRL2_EXT_EN1                          13
+#define BM_LRADC_CTRL2_EXT_EN1                          0x2000
+#define BV_LRADC_CTRL2_EXT_EN1__DISABLE                 0x0
+#define BV_LRADC_CTRL2_EXT_EN1__ENABLE                  0x1
+#define BF_LRADC_CTRL2_EXT_EN1(v)                       (((v) & 0x1) << 13)
+#define BFM_LRADC_CTRL2_EXT_EN1(v)                      BM_LRADC_CTRL2_EXT_EN1
+#define BF_LRADC_CTRL2_EXT_EN1_V(e)                     BF_LRADC_CTRL2_EXT_EN1(BV_LRADC_CTRL2_EXT_EN1__##e)
+#define BFM_LRADC_CTRL2_EXT_EN1_V(v)                    BM_LRADC_CTRL2_EXT_EN1
+#define BP_LRADC_CTRL2_EXT_EN0                          12
+#define BM_LRADC_CTRL2_EXT_EN0                          0x1000
+#define BF_LRADC_CTRL2_EXT_EN0(v)                       (((v) & 0x1) << 12)
+#define BFM_LRADC_CTRL2_EXT_EN0(v)                      BM_LRADC_CTRL2_EXT_EN0
+#define BF_LRADC_CTRL2_EXT_EN0_V(e)                     BF_LRADC_CTRL2_EXT_EN0(BV_LRADC_CTRL2_EXT_EN0__##e)
+#define BFM_LRADC_CTRL2_EXT_EN0_V(v)                    BM_LRADC_CTRL2_EXT_EN0
+#define BP_LRADC_CTRL2_RSRVD2                           10
+#define BM_LRADC_CTRL2_RSRVD2                           0xc00
+#define BF_LRADC_CTRL2_RSRVD2(v)                        (((v) & 0x3) << 10)
+#define BFM_LRADC_CTRL2_RSRVD2(v)                       BM_LRADC_CTRL2_RSRVD2
+#define BF_LRADC_CTRL2_RSRVD2_V(e)                      BF_LRADC_CTRL2_RSRVD2(BV_LRADC_CTRL2_RSRVD2__##e)
+#define BFM_LRADC_CTRL2_RSRVD2_V(v)                     BM_LRADC_CTRL2_RSRVD2
+#define BP_LRADC_CTRL2_TEMP_SENSOR_IENABLE1             9
+#define BM_LRADC_CTRL2_TEMP_SENSOR_IENABLE1             0x200
+#define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE1__DISABLE    0x0
+#define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE1__ENABLE     0x1
+#define BF_LRADC_CTRL2_TEMP_SENSOR_IENABLE1(v)          (((v) & 0x1) << 9)
+#define BFM_LRADC_CTRL2_TEMP_SENSOR_IENABLE1(v)         BM_LRADC_CTRL2_TEMP_SENSOR_IENABLE1
+#define BF_LRADC_CTRL2_TEMP_SENSOR_IENABLE1_V(e)        BF_LRADC_CTRL2_TEMP_SENSOR_IENABLE1(BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE1__##e)
+#define BFM_LRADC_CTRL2_TEMP_SENSOR_IENABLE1_V(v)       BM_LRADC_CTRL2_TEMP_SENSOR_IENABLE1
+#define BP_LRADC_CTRL2_TEMP_SENSOR_IENABLE0             8
+#define BM_LRADC_CTRL2_TEMP_SENSOR_IENABLE0             0x100
+#define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE0__DISABLE    0x0
+#define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE0__ENABLE     0x1
+#define BF_LRADC_CTRL2_TEMP_SENSOR_IENABLE0(v)          (((v) & 0x1) << 8)
+#define BFM_LRADC_CTRL2_TEMP_SENSOR_IENABLE0(v)         BM_LRADC_CTRL2_TEMP_SENSOR_IENABLE0
+#define BF_LRADC_CTRL2_TEMP_SENSOR_IENABLE0_V(e)        BF_LRADC_CTRL2_TEMP_SENSOR_IENABLE0(BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE0__##e)
+#define BFM_LRADC_CTRL2_TEMP_SENSOR_IENABLE0_V(v)       BM_LRADC_CTRL2_TEMP_SENSOR_IENABLE0
+#define BP_LRADC_CTRL2_TEMP_ISRC1                       4
+#define BM_LRADC_CTRL2_TEMP_ISRC1                       0xf0
+#define BV_LRADC_CTRL2_TEMP_ISRC1__300                  0xf
+#define BV_LRADC_CTRL2_TEMP_ISRC1__280                  0xe
+#define BV_LRADC_CTRL2_TEMP_ISRC1__260                  0xd
+#define BV_LRADC_CTRL2_TEMP_ISRC1__240                  0xc
+#define BV_LRADC_CTRL2_TEMP_ISRC1__220                  0xb
+#define BV_LRADC_CTRL2_TEMP_ISRC1__200                  0xa
+#define BV_LRADC_CTRL2_TEMP_ISRC1__180                  0x9
+#define BV_LRADC_CTRL2_TEMP_ISRC1__160                  0x8
+#define BV_LRADC_CTRL2_TEMP_ISRC1__140                  0x7
+#define BV_LRADC_CTRL2_TEMP_ISRC1__120                  0x6
+#define BV_LRADC_CTRL2_TEMP_ISRC1__100                  0x5
+#define BV_LRADC_CTRL2_TEMP_ISRC1__80                   0x4
+#define BV_LRADC_CTRL2_TEMP_ISRC1__60                   0x3
+#define BV_LRADC_CTRL2_TEMP_ISRC1__40                   0x2
+#define BV_LRADC_CTRL2_TEMP_ISRC1__20                   0x1
+#define BV_LRADC_CTRL2_TEMP_ISRC1__ZERO                 0x0
+#define BF_LRADC_CTRL2_TEMP_ISRC1(v)                    (((v) & 0xf) << 4)
+#define BFM_LRADC_CTRL2_TEMP_ISRC1(v)                   BM_LRADC_CTRL2_TEMP_ISRC1
+#define BF_LRADC_CTRL2_TEMP_ISRC1_V(e)                  BF_LRADC_CTRL2_TEMP_ISRC1(BV_LRADC_CTRL2_TEMP_ISRC1__##e)
+#define BFM_LRADC_CTRL2_TEMP_ISRC1_V(v)                 BM_LRADC_CTRL2_TEMP_ISRC1
+#define BP_LRADC_CTRL2_TEMP_ISRC0                       0
+#define BM_LRADC_CTRL2_TEMP_ISRC0                       0xf
+#define BV_LRADC_CTRL2_TEMP_ISRC0__300                  0xf
+#define BV_LRADC_CTRL2_TEMP_ISRC0__280                  0xe
+#define BV_LRADC_CTRL2_TEMP_ISRC0__260                  0xd
+#define BV_LRADC_CTRL2_TEMP_ISRC0__240                  0xc
+#define BV_LRADC_CTRL2_TEMP_ISRC0__220                  0xb
+#define BV_LRADC_CTRL2_TEMP_ISRC0__200                  0xa
+#define BV_LRADC_CTRL2_TEMP_ISRC0__180                  0x9
+#define BV_LRADC_CTRL2_TEMP_ISRC0__160                  0x8
+#define BV_LRADC_CTRL2_TEMP_ISRC0__140                  0x7
+#define BV_LRADC_CTRL2_TEMP_ISRC0__120                  0x6
+#define BV_LRADC_CTRL2_TEMP_ISRC0__100                  0x5
+#define BV_LRADC_CTRL2_TEMP_ISRC0__80                   0x4
+#define BV_LRADC_CTRL2_TEMP_ISRC0__60                   0x3
+#define BV_LRADC_CTRL2_TEMP_ISRC0__40                   0x2
+#define BV_LRADC_CTRL2_TEMP_ISRC0__20                   0x1
+#define BV_LRADC_CTRL2_TEMP_ISRC0__ZERO                 0x0
+#define BF_LRADC_CTRL2_TEMP_ISRC0(v)                    (((v) & 0xf) << 0)
+#define BFM_LRADC_CTRL2_TEMP_ISRC0(v)                   BM_LRADC_CTRL2_TEMP_ISRC0
+#define BF_LRADC_CTRL2_TEMP_ISRC0_V(e)                  BF_LRADC_CTRL2_TEMP_ISRC0(BV_LRADC_CTRL2_TEMP_ISRC0__##e)
+#define BFM_LRADC_CTRL2_TEMP_ISRC0_V(v)                 BM_LRADC_CTRL2_TEMP_ISRC0
+
+#define HW_LRADC_CTRL3                          HW(LRADC_CTRL3)
+#define HWA_LRADC_CTRL3                         (0x80050000 + 0x30)
+#define HWT_LRADC_CTRL3                         HWIO_32_RW
+#define HWN_LRADC_CTRL3                         LRADC_CTRL3
+#define HWI_LRADC_CTRL3                         
+#define HW_LRADC_CTRL3_SET                      HW(LRADC_CTRL3_SET)
+#define HWA_LRADC_CTRL3_SET                     (HWA_LRADC_CTRL3 + 0x4)
+#define HWT_LRADC_CTRL3_SET                     HWIO_32_WO
+#define HWN_LRADC_CTRL3_SET                     LRADC_CTRL3
+#define HWI_LRADC_CTRL3_SET                     
+#define HW_LRADC_CTRL3_CLR                      HW(LRADC_CTRL3_CLR)
+#define HWA_LRADC_CTRL3_CLR                     (HWA_LRADC_CTRL3 + 0x8)
+#define HWT_LRADC_CTRL3_CLR                     HWIO_32_WO
+#define HWN_LRADC_CTRL3_CLR                     LRADC_CTRL3
+#define HWI_LRADC_CTRL3_CLR                     
+#define HW_LRADC_CTRL3_TOG                      HW(LRADC_CTRL3_TOG)
+#define HWA_LRADC_CTRL3_TOG                     (HWA_LRADC_CTRL3 + 0xc)
+#define HWT_LRADC_CTRL3_TOG                     HWIO_32_WO
+#define HWN_LRADC_CTRL3_TOG                     LRADC_CTRL3
+#define HWI_LRADC_CTRL3_TOG                     
+#define BP_LRADC_CTRL3_RSRVD5                   26
+#define BM_LRADC_CTRL3_RSRVD5                   0xfc000000
+#define BF_LRADC_CTRL3_RSRVD5(v)                (((v) & 0x3f) << 26)
+#define BFM_LRADC_CTRL3_RSRVD5(v)               BM_LRADC_CTRL3_RSRVD5
+#define BF_LRADC_CTRL3_RSRVD5_V(e)              BF_LRADC_CTRL3_RSRVD5(BV_LRADC_CTRL3_RSRVD5__##e)
+#define BFM_LRADC_CTRL3_RSRVD5_V(v)             BM_LRADC_CTRL3_RSRVD5
+#define BP_LRADC_CTRL3_DISCARD                  24
+#define BM_LRADC_CTRL3_DISCARD                  0x3000000
+#define BV_LRADC_CTRL3_DISCARD__1_SAMPLE        0x1
+#define BV_LRADC_CTRL3_DISCARD__2_SAMPLES       0x2
+#define BV_LRADC_CTRL3_DISCARD__3_SAMPLES       0x3
+#define BF_LRADC_CTRL3_DISCARD(v)               (((v) & 0x3) << 24)
+#define BFM_LRADC_CTRL3_DISCARD(v)              BM_LRADC_CTRL3_DISCARD
+#define BF_LRADC_CTRL3_DISCARD_V(e)             BF_LRADC_CTRL3_DISCARD(BV_LRADC_CTRL3_DISCARD__##e)
+#define BFM_LRADC_CTRL3_DISCARD_V(v)            BM_LRADC_CTRL3_DISCARD
+#define BP_LRADC_CTRL3_FORCE_ANALOG_PWUP        23
+#define BM_LRADC_CTRL3_FORCE_ANALOG_PWUP        0x800000
+#define BV_LRADC_CTRL3_FORCE_ANALOG_PWUP__OFF   0x0
+#define BV_LRADC_CTRL3_FORCE_ANALOG_PWUP__ON    0x1
+#define BF_LRADC_CTRL3_FORCE_ANALOG_PWUP(v)     (((v) & 0x1) << 23)
+#define BFM_LRADC_CTRL3_FORCE_ANALOG_PWUP(v)    BM_LRADC_CTRL3_FORCE_ANALOG_PWUP
+#define BF_LRADC_CTRL3_FORCE_ANALOG_PWUP_V(e)   BF_LRADC_CTRL3_FORCE_ANALOG_PWUP(BV_LRADC_CTRL3_FORCE_ANALOG_PWUP__##e)
+#define BFM_LRADC_CTRL3_FORCE_ANALOG_PWUP_V(v)  BM_LRADC_CTRL3_FORCE_ANALOG_PWUP
+#define BP_LRADC_CTRL3_FORCE_ANALOG_PWDN        22
+#define BM_LRADC_CTRL3_FORCE_ANALOG_PWDN        0x400000
+#define BV_LRADC_CTRL3_FORCE_ANALOG_PWDN__ON    0x0
+#define BV_LRADC_CTRL3_FORCE_ANALOG_PWDN__OFF   0x1
+#define BF_LRADC_CTRL3_FORCE_ANALOG_PWDN(v)     (((v) & 0x1) << 22)
+#define BFM_LRADC_CTRL3_FORCE_ANALOG_PWDN(v)    BM_LRADC_CTRL3_FORCE_ANALOG_PWDN
+#define BF_LRADC_CTRL3_FORCE_ANALOG_PWDN_V(e)   BF_LRADC_CTRL3_FORCE_ANALOG_PWDN(BV_LRADC_CTRL3_FORCE_ANALOG_PWDN__##e)
+#define BFM_LRADC_CTRL3_FORCE_ANALOG_PWDN_V(v)  BM_LRADC_CTRL3_FORCE_ANALOG_PWDN
+#define BP_LRADC_CTRL3_RSRVD4                   14
+#define BM_LRADC_CTRL3_RSRVD4                   0x3fc000
+#define BF_LRADC_CTRL3_RSRVD4(v)                (((v) & 0xff) << 14)
+#define BFM_LRADC_CTRL3_RSRVD4(v)               BM_LRADC_CTRL3_RSRVD4
+#define BF_LRADC_CTRL3_RSRVD4_V(e)              BF_LRADC_CTRL3_RSRVD4(BV_LRADC_CTRL3_RSRVD4__##e)
+#define BFM_LRADC_CTRL3_RSRVD4_V(v)             BM_LRADC_CTRL3_RSRVD4
+#define BP_LRADC_CTRL3_RSRVD3                   10
+#define BM_LRADC_CTRL3_RSRVD3                   0x3c00
+#define BF_LRADC_CTRL3_RSRVD3(v)                (((v) & 0xf) << 10)
+#define BFM_LRADC_CTRL3_RSRVD3(v)               BM_LRADC_CTRL3_RSRVD3
+#define BF_LRADC_CTRL3_RSRVD3_V(e)              BF_LRADC_CTRL3_RSRVD3(BV_LRADC_CTRL3_RSRVD3__##e)
+#define BFM_LRADC_CTRL3_RSRVD3_V(v)             BM_LRADC_CTRL3_RSRVD3
+#define BP_LRADC_CTRL3_CYCLE_TIME               8
+#define BM_LRADC_CTRL3_CYCLE_TIME               0x300
+#define BV_LRADC_CTRL3_CYCLE_TIME__6MHZ         0x0
+#define BV_LRADC_CTRL3_CYCLE_TIME__4MHZ         0x1
+#define BV_LRADC_CTRL3_CYCLE_TIME__3MHZ         0x2
+#define BV_LRADC_CTRL3_CYCLE_TIME__2MHZ         0x3
+#define BF_LRADC_CTRL3_CYCLE_TIME(v)            (((v) & 0x3) << 8)
+#define BFM_LRADC_CTRL3_CYCLE_TIME(v)           BM_LRADC_CTRL3_CYCLE_TIME
+#define BF_LRADC_CTRL3_CYCLE_TIME_V(e)          BF_LRADC_CTRL3_CYCLE_TIME(BV_LRADC_CTRL3_CYCLE_TIME__##e)
+#define BFM_LRADC_CTRL3_CYCLE_TIME_V(v)         BM_LRADC_CTRL3_CYCLE_TIME
+#define BP_LRADC_CTRL3_RSRVD2                   6
+#define BM_LRADC_CTRL3_RSRVD2                   0xc0
+#define BF_LRADC_CTRL3_RSRVD2(v)                (((v) & 0x3) << 6)
+#define BFM_LRADC_CTRL3_RSRVD2(v)               BM_LRADC_CTRL3_RSRVD2
+#define BF_LRADC_CTRL3_RSRVD2_V(e)              BF_LRADC_CTRL3_RSRVD2(BV_LRADC_CTRL3_RSRVD2__##e)
+#define BFM_LRADC_CTRL3_RSRVD2_V(v)             BM_LRADC_CTRL3_RSRVD2
+#define BP_LRADC_CTRL3_HIGH_TIME                4
+#define BM_LRADC_CTRL3_HIGH_TIME                0x30
+#define BV_LRADC_CTRL3_HIGH_TIME__42NS          0x0
+#define BV_LRADC_CTRL3_HIGH_TIME__83NS          0x1
+#define BV_LRADC_CTRL3_HIGH_TIME__125NS         0x2
+#define BV_LRADC_CTRL3_HIGH_TIME__250NS         0x3
+#define BF_LRADC_CTRL3_HIGH_TIME(v)             (((v) & 0x3) << 4)
+#define BFM_LRADC_CTRL3_HIGH_TIME(v)            BM_LRADC_CTRL3_HIGH_TIME
+#define BF_LRADC_CTRL3_HIGH_TIME_V(e)           BF_LRADC_CTRL3_HIGH_TIME(BV_LRADC_CTRL3_HIGH_TIME__##e)
+#define BFM_LRADC_CTRL3_HIGH_TIME_V(v)          BM_LRADC_CTRL3_HIGH_TIME
+#define BP_LRADC_CTRL3_RSRVD1                   2
+#define BM_LRADC_CTRL3_RSRVD1                   0xc
+#define BF_LRADC_CTRL3_RSRVD1(v)                (((v) & 0x3) << 2)
+#define BFM_LRADC_CTRL3_RSRVD1(v)               BM_LRADC_CTRL3_RSRVD1
+#define BF_LRADC_CTRL3_RSRVD1_V(e)              BF_LRADC_CTRL3_RSRVD1(BV_LRADC_CTRL3_RSRVD1__##e)
+#define BFM_LRADC_CTRL3_RSRVD1_V(v)             BM_LRADC_CTRL3_RSRVD1
+#define BP_LRADC_CTRL3_DELAY_CLOCK              1
+#define BM_LRADC_CTRL3_DELAY_CLOCK              0x2
+#define BV_LRADC_CTRL3_DELAY_CLOCK__NORMAL      0x0
+#define BV_LRADC_CTRL3_DELAY_CLOCK__DELAYED     0x1
+#define BF_LRADC_CTRL3_DELAY_CLOCK(v)           (((v) & 0x1) << 1)
+#define BFM_LRADC_CTRL3_DELAY_CLOCK(v)          BM_LRADC_CTRL3_DELAY_CLOCK
+#define BF_LRADC_CTRL3_DELAY_CLOCK_V(e)         BF_LRADC_CTRL3_DELAY_CLOCK(BV_LRADC_CTRL3_DELAY_CLOCK__##e)
+#define BFM_LRADC_CTRL3_DELAY_CLOCK_V(v)        BM_LRADC_CTRL3_DELAY_CLOCK
+#define BP_LRADC_CTRL3_INVERT_CLOCK             0
+#define BM_LRADC_CTRL3_INVERT_CLOCK             0x1
+#define BV_LRADC_CTRL3_INVERT_CLOCK__NORMAL     0x0
+#define BV_LRADC_CTRL3_INVERT_CLOCK__INVERT     0x1
+#define BF_LRADC_CTRL3_INVERT_CLOCK(v)          (((v) & 0x1) << 0)
+#define BFM_LRADC_CTRL3_INVERT_CLOCK(v)         BM_LRADC_CTRL3_INVERT_CLOCK
+#define BF_LRADC_CTRL3_INVERT_CLOCK_V(e)        BF_LRADC_CTRL3_INVERT_CLOCK(BV_LRADC_CTRL3_INVERT_CLOCK__##e)
+#define BFM_LRADC_CTRL3_INVERT_CLOCK_V(v)       BM_LRADC_CTRL3_INVERT_CLOCK
+
+#define HW_LRADC_STATUS                             HW(LRADC_STATUS)
+#define HWA_LRADC_STATUS                            (0x80050000 + 0x40)
+#define HWT_LRADC_STATUS                            HWIO_32_RW
+#define HWN_LRADC_STATUS                            LRADC_STATUS
+#define HWI_LRADC_STATUS                            
+#define HW_LRADC_STATUS_SET                         HW(LRADC_STATUS_SET)
+#define HWA_LRADC_STATUS_SET                        (HWA_LRADC_STATUS + 0x4)
+#define HWT_LRADC_STATUS_SET                        HWIO_32_WO
+#define HWN_LRADC_STATUS_SET                        LRADC_STATUS
+#define HWI_LRADC_STATUS_SET                        
+#define HW_LRADC_STATUS_CLR                         HW(LRADC_STATUS_CLR)
+#define HWA_LRADC_STATUS_CLR                        (HWA_LRADC_STATUS + 0x8)
+#define HWT_LRADC_STATUS_CLR                        HWIO_32_WO
+#define HWN_LRADC_STATUS_CLR                        LRADC_STATUS
+#define HWI_LRADC_STATUS_CLR                        
+#define HW_LRADC_STATUS_TOG                         HW(LRADC_STATUS_TOG)
+#define HWA_LRADC_STATUS_TOG                        (HWA_LRADC_STATUS + 0xc)
+#define HWT_LRADC_STATUS_TOG                        HWIO_32_WO
+#define HWN_LRADC_STATUS_TOG                        LRADC_STATUS
+#define HWI_LRADC_STATUS_TOG                        
+#define BP_LRADC_STATUS_RSRVD3                      27
+#define BM_LRADC_STATUS_RSRVD3                      0xf8000000
+#define BF_LRADC_STATUS_RSRVD3(v)                   (((v) & 0x1f) << 27)
+#define BFM_LRADC_STATUS_RSRVD3(v)                  BM_LRADC_STATUS_RSRVD3
+#define BF_LRADC_STATUS_RSRVD3_V(e)                 BF_LRADC_STATUS_RSRVD3(BV_LRADC_STATUS_RSRVD3__##e)
+#define BFM_LRADC_STATUS_RSRVD3_V(v)                BM_LRADC_STATUS_RSRVD3
+#define BP_LRADC_STATUS_TEMP1_PRESENT               26
+#define BM_LRADC_STATUS_TEMP1_PRESENT               0x4000000
+#define BF_LRADC_STATUS_TEMP1_PRESENT(v)            (((v) & 0x1) << 26)
+#define BFM_LRADC_STATUS_TEMP1_PRESENT(v)           BM_LRADC_STATUS_TEMP1_PRESENT
+#define BF_LRADC_STATUS_TEMP1_PRESENT_V(e)          BF_LRADC_STATUS_TEMP1_PRESENT(BV_LRADC_STATUS_TEMP1_PRESENT__##e)
+#define BFM_LRADC_STATUS_TEMP1_PRESENT_V(v)         BM_LRADC_STATUS_TEMP1_PRESENT
+#define BP_LRADC_STATUS_TEMP0_PRESENT               25
+#define BM_LRADC_STATUS_TEMP0_PRESENT               0x2000000
+#define BF_LRADC_STATUS_TEMP0_PRESENT(v)            (((v) & 0x1) << 25)
+#define BFM_LRADC_STATUS_TEMP0_PRESENT(v)           BM_LRADC_STATUS_TEMP0_PRESENT
+#define BF_LRADC_STATUS_TEMP0_PRESENT_V(e)          BF_LRADC_STATUS_TEMP0_PRESENT(BV_LRADC_STATUS_TEMP0_PRESENT__##e)
+#define BFM_LRADC_STATUS_TEMP0_PRESENT_V(v)         BM_LRADC_STATUS_TEMP0_PRESENT
+#define BP_LRADC_STATUS_TOUCH_PANEL_PRESENT         24
+#define BM_LRADC_STATUS_TOUCH_PANEL_PRESENT         0x1000000
+#define BF_LRADC_STATUS_TOUCH_PANEL_PRESENT(v)      (((v) & 0x1) << 24)
+#define BFM_LRADC_STATUS_TOUCH_PANEL_PRESENT(v)     BM_LRADC_STATUS_TOUCH_PANEL_PRESENT
+#define BF_LRADC_STATUS_TOUCH_PANEL_PRESENT_V(e)    BF_LRADC_STATUS_TOUCH_PANEL_PRESENT(BV_LRADC_STATUS_TOUCH_PANEL_PRESENT__##e)
+#define BFM_LRADC_STATUS_TOUCH_PANEL_PRESENT_V(v)   BM_LRADC_STATUS_TOUCH_PANEL_PRESENT
+#define BP_LRADC_STATUS_CHANNEL7_PRESENT            23
+#define BM_LRADC_STATUS_CHANNEL7_PRESENT            0x800000
+#define BF_LRADC_STATUS_CHANNEL7_PRESENT(v)         (((v) & 0x1) << 23)
+#define BFM_LRADC_STATUS_CHANNEL7_PRESENT(v)        BM_LRADC_STATUS_CHANNEL7_PRESENT
+#define BF_LRADC_STATUS_CHANNEL7_PRESENT_V(e)       BF_LRADC_STATUS_CHANNEL7_PRESENT(BV_LRADC_STATUS_CHANNEL7_PRESENT__##e)
+#define BFM_LRADC_STATUS_CHANNEL7_PRESENT_V(v)      BM_LRADC_STATUS_CHANNEL7_PRESENT
+#define BP_LRADC_STATUS_CHANNEL6_PRESENT            22
+#define BM_LRADC_STATUS_CHANNEL6_PRESENT            0x400000
+#define BF_LRADC_STATUS_CHANNEL6_PRESENT(v)         (((v) & 0x1) << 22)
+#define BFM_LRADC_STATUS_CHANNEL6_PRESENT(v)        BM_LRADC_STATUS_CHANNEL6_PRESENT
+#define BF_LRADC_STATUS_CHANNEL6_PRESENT_V(e)       BF_LRADC_STATUS_CHANNEL6_PRESENT(BV_LRADC_STATUS_CHANNEL6_PRESENT__##e)
+#define BFM_LRADC_STATUS_CHANNEL6_PRESENT_V(v)      BM_LRADC_STATUS_CHANNEL6_PRESENT
+#define BP_LRADC_STATUS_CHANNEL5_PRESENT            21
+#define BM_LRADC_STATUS_CHANNEL5_PRESENT            0x200000
+#define BF_LRADC_STATUS_CHANNEL5_PRESENT(v)         (((v) & 0x1) << 21)
+#define BFM_LRADC_STATUS_CHANNEL5_PRESENT(v)        BM_LRADC_STATUS_CHANNEL5_PRESENT
+#define BF_LRADC_STATUS_CHANNEL5_PRESENT_V(e)       BF_LRADC_STATUS_CHANNEL5_PRESENT(BV_LRADC_STATUS_CHANNEL5_PRESENT__##e)
+#define BFM_LRADC_STATUS_CHANNEL5_PRESENT_V(v)      BM_LRADC_STATUS_CHANNEL5_PRESENT
+#define BP_LRADC_STATUS_CHANNEL4_PRESENT            20
+#define BM_LRADC_STATUS_CHANNEL4_PRESENT            0x100000
+#define BF_LRADC_STATUS_CHANNEL4_PRESENT(v)         (((v) & 0x1) << 20)
+#define BFM_LRADC_STATUS_CHANNEL4_PRESENT(v)        BM_LRADC_STATUS_CHANNEL4_PRESENT
+#define BF_LRADC_STATUS_CHANNEL4_PRESENT_V(e)       BF_LRADC_STATUS_CHANNEL4_PRESENT(BV_LRADC_STATUS_CHANNEL4_PRESENT__##e)
+#define BFM_LRADC_STATUS_CHANNEL4_PRESENT_V(v)      BM_LRADC_STATUS_CHANNEL4_PRESENT
+#define BP_LRADC_STATUS_CHANNEL3_PRESENT            19
+#define BM_LRADC_STATUS_CHANNEL3_PRESENT            0x80000
+#define BF_LRADC_STATUS_CHANNEL3_PRESENT(v)         (((v) & 0x1) << 19)
+#define BFM_LRADC_STATUS_CHANNEL3_PRESENT(v)        BM_LRADC_STATUS_CHANNEL3_PRESENT
+#define BF_LRADC_STATUS_CHANNEL3_PRESENT_V(e)       BF_LRADC_STATUS_CHANNEL3_PRESENT(BV_LRADC_STATUS_CHANNEL3_PRESENT__##e)
+#define BFM_LRADC_STATUS_CHANNEL3_PRESENT_V(v)      BM_LRADC_STATUS_CHANNEL3_PRESENT
+#define BP_LRADC_STATUS_CHANNEL2_PRESENT            18
+#define BM_LRADC_STATUS_CHANNEL2_PRESENT            0x40000
+#define BF_LRADC_STATUS_CHANNEL2_PRESENT(v)         (((v) & 0x1) << 18)
+#define BFM_LRADC_STATUS_CHANNEL2_PRESENT(v)        BM_LRADC_STATUS_CHANNEL2_PRESENT
+#define BF_LRADC_STATUS_CHANNEL2_PRESENT_V(e)       BF_LRADC_STATUS_CHANNEL2_PRESENT(BV_LRADC_STATUS_CHANNEL2_PRESENT__##e)
+#define BFM_LRADC_STATUS_CHANNEL2_PRESENT_V(v)      BM_LRADC_STATUS_CHANNEL2_PRESENT
+#define BP_LRADC_STATUS_CHANNEL1_PRESENT            17
+#define BM_LRADC_STATUS_CHANNEL1_PRESENT            0x20000
+#define BF_LRADC_STATUS_CHANNEL1_PRESENT(v)         (((v) & 0x1) << 17)
+#define BFM_LRADC_STATUS_CHANNEL1_PRESENT(v)        BM_LRADC_STATUS_CHANNEL1_PRESENT
+#define BF_LRADC_STATUS_CHANNEL1_PRESENT_V(e)       BF_LRADC_STATUS_CHANNEL1_PRESENT(BV_LRADC_STATUS_CHANNEL1_PRESENT__##e)
+#define BFM_LRADC_STATUS_CHANNEL1_PRESENT_V(v)      BM_LRADC_STATUS_CHANNEL1_PRESENT
+#define BP_LRADC_STATUS_CHANNEL0_PRESENT            16
+#define BM_LRADC_STATUS_CHANNEL0_PRESENT            0x10000
+#define BF_LRADC_STATUS_CHANNEL0_PRESENT(v)         (((v) & 0x1) << 16)
+#define BFM_LRADC_STATUS_CHANNEL0_PRESENT(v)        BM_LRADC_STATUS_CHANNEL0_PRESENT
+#define BF_LRADC_STATUS_CHANNEL0_PRESENT_V(e)       BF_LRADC_STATUS_CHANNEL0_PRESENT(BV_LRADC_STATUS_CHANNEL0_PRESENT__##e)
+#define BFM_LRADC_STATUS_CHANNEL0_PRESENT_V(v)      BM_LRADC_STATUS_CHANNEL0_PRESENT
+#define BP_LRADC_STATUS_RSRVD2                      1
+#define BM_LRADC_STATUS_RSRVD2                      0xfffe
+#define BF_LRADC_STATUS_RSRVD2(v)                   (((v) & 0x7fff) << 1)
+#define BFM_LRADC_STATUS_RSRVD2(v)                  BM_LRADC_STATUS_RSRVD2
+#define BF_LRADC_STATUS_RSRVD2_V(e)                 BF_LRADC_STATUS_RSRVD2(BV_LRADC_STATUS_RSRVD2__##e)
+#define BFM_LRADC_STATUS_RSRVD2_V(v)                BM_LRADC_STATUS_RSRVD2
+#define BP_LRADC_STATUS_TOUCH_DETECT_RAW            0
+#define BM_LRADC_STATUS_TOUCH_DETECT_RAW            0x1
+#define BV_LRADC_STATUS_TOUCH_DETECT_RAW__OPEN      0x0
+#define BV_LRADC_STATUS_TOUCH_DETECT_RAW__HIT       0x1
+#define BF_LRADC_STATUS_TOUCH_DETECT_RAW(v)         (((v) & 0x1) << 0)
+#define BFM_LRADC_STATUS_TOUCH_DETECT_RAW(v)        BM_LRADC_STATUS_TOUCH_DETECT_RAW
+#define BF_LRADC_STATUS_TOUCH_DETECT_RAW_V(e)       BF_LRADC_STATUS_TOUCH_DETECT_RAW(BV_LRADC_STATUS_TOUCH_DETECT_RAW__##e)
+#define BFM_LRADC_STATUS_TOUCH_DETECT_RAW_V(v)      BM_LRADC_STATUS_TOUCH_DETECT_RAW
+
+#define HW_LRADC_CHn(_n1)               HW(LRADC_CHn(_n1))
+#define HWA_LRADC_CHn(_n1)              (0x80050000 + 0x50 + (_n1) * 0x10)
+#define HWT_LRADC_CHn(_n1)              HWIO_32_RW
+#define HWN_LRADC_CHn(_n1)              LRADC_CHn
+#define HWI_LRADC_CHn(_n1)              (_n1)
+#define HW_LRADC_CHn_SET(_n1)           HW(LRADC_CHn_SET(_n1))
+#define HWA_LRADC_CHn_SET(_n1)          (HWA_LRADC_CHn(_n1) + 0x4)
+#define HWT_LRADC_CHn_SET(_n1)          HWIO_32_WO
+#define HWN_LRADC_CHn_SET(_n1)          LRADC_CHn
+#define HWI_LRADC_CHn_SET(_n1)          (_n1)
+#define HW_LRADC_CHn_CLR(_n1)           HW(LRADC_CHn_CLR(_n1))
+#define HWA_LRADC_CHn_CLR(_n1)          (HWA_LRADC_CHn(_n1) + 0x8)
+#define HWT_LRADC_CHn_CLR(_n1)          HWIO_32_WO
+#define HWN_LRADC_CHn_CLR(_n1)          LRADC_CHn
+#define HWI_LRADC_CHn_CLR(_n1)          (_n1)
+#define HW_LRADC_CHn_TOG(_n1)           HW(LRADC_CHn_TOG(_n1))
+#define HWA_LRADC_CHn_TOG(_n1)          (HWA_LRADC_CHn(_n1) + 0xc)
+#define HWT_LRADC_CHn_TOG(_n1)          HWIO_32_WO
+#define HWN_LRADC_CHn_TOG(_n1)          LRADC_CHn
+#define HWI_LRADC_CHn_TOG(_n1)          (_n1)
+#define BP_LRADC_CHn_TOGGLE             31
+#define BM_LRADC_CHn_TOGGLE             0x80000000
+#define BF_LRADC_CHn_TOGGLE(v)          (((v) & 0x1) << 31)
+#define BFM_LRADC_CHn_TOGGLE(v)         BM_LRADC_CHn_TOGGLE
+#define BF_LRADC_CHn_TOGGLE_V(e)        BF_LRADC_CHn_TOGGLE(BV_LRADC_CHn_TOGGLE__##e)
+#define BFM_LRADC_CHn_TOGGLE_V(v)       BM_LRADC_CHn_TOGGLE
+#define BP_LRADC_CHn_RSRVD2             30
+#define BM_LRADC_CHn_RSRVD2             0x40000000
+#define BF_LRADC_CHn_RSRVD2(v)          (((v) & 0x1) << 30)
+#define BFM_LRADC_CHn_RSRVD2(v)         BM_LRADC_CHn_RSRVD2
+#define BF_LRADC_CHn_RSRVD2_V(e)        BF_LRADC_CHn_RSRVD2(BV_LRADC_CHn_RSRVD2__##e)
+#define BFM_LRADC_CHn_RSRVD2_V(v)       BM_LRADC_CHn_RSRVD2
+#define BP_LRADC_CHn_ACCUMULATE         29
+#define BM_LRADC_CHn_ACCUMULATE         0x20000000
+#define BF_LRADC_CHn_ACCUMULATE(v)      (((v) & 0x1) << 29)
+#define BFM_LRADC_CHn_ACCUMULATE(v)     BM_LRADC_CHn_ACCUMULATE
+#define BF_LRADC_CHn_ACCUMULATE_V(e)    BF_LRADC_CHn_ACCUMULATE(BV_LRADC_CHn_ACCUMULATE__##e)
+#define BFM_LRADC_CHn_ACCUMULATE_V(v)   BM_LRADC_CHn_ACCUMULATE
+#define BP_LRADC_CHn_NUM_SAMPLES        24
+#define BM_LRADC_CHn_NUM_SAMPLES        0x1f000000
+#define BF_LRADC_CHn_NUM_SAMPLES(v)     (((v) & 0x1f) << 24)
+#define BFM_LRADC_CHn_NUM_SAMPLES(v)    BM_LRADC_CHn_NUM_SAMPLES
+#define BF_LRADC_CHn_NUM_SAMPLES_V(e)   BF_LRADC_CHn_NUM_SAMPLES(BV_LRADC_CHn_NUM_SAMPLES__##e)
+#define BFM_LRADC_CHn_NUM_SAMPLES_V(v)  BM_LRADC_CHn_NUM_SAMPLES
+#define BP_LRADC_CHn_RSRVD1             18
+#define BM_LRADC_CHn_RSRVD1             0xfc0000
+#define BF_LRADC_CHn_RSRVD1(v)          (((v) & 0x3f) << 18)
+#define BFM_LRADC_CHn_RSRVD1(v)         BM_LRADC_CHn_RSRVD1
+#define BF_LRADC_CHn_RSRVD1_V(e)        BF_LRADC_CHn_RSRVD1(BV_LRADC_CHn_RSRVD1__##e)
+#define BFM_LRADC_CHn_RSRVD1_V(v)       BM_LRADC_CHn_RSRVD1
+#define BP_LRADC_CHn_VALUE              0
+#define BM_LRADC_CHn_VALUE              0x3ffff
+#define BF_LRADC_CHn_VALUE(v)           (((v) & 0x3ffff) << 0)
+#define BFM_LRADC_CHn_VALUE(v)          BM_LRADC_CHn_VALUE
+#define BF_LRADC_CHn_VALUE_V(e)         BF_LRADC_CHn_VALUE(BV_LRADC_CHn_VALUE__##e)
+#define BFM_LRADC_CHn_VALUE_V(v)        BM_LRADC_CHn_VALUE
+
+#define HW_LRADC_DELAYn(_n1)                    HW(LRADC_DELAYn(_n1))
+#define HWA_LRADC_DELAYn(_n1)                   (0x80050000 + 0xd0 + (_n1) * 0x10)
+#define HWT_LRADC_DELAYn(_n1)                   HWIO_32_RW
+#define HWN_LRADC_DELAYn(_n1)                   LRADC_DELAYn
+#define HWI_LRADC_DELAYn(_n1)                   (_n1)
+#define HW_LRADC_DELAYn_SET(_n1)                HW(LRADC_DELAYn_SET(_n1))
+#define HWA_LRADC_DELAYn_SET(_n1)               (HWA_LRADC_DELAYn(_n1) + 0x4)
+#define HWT_LRADC_DELAYn_SET(_n1)               HWIO_32_WO
+#define HWN_LRADC_DELAYn_SET(_n1)               LRADC_DELAYn
+#define HWI_LRADC_DELAYn_SET(_n1)               (_n1)
+#define HW_LRADC_DELAYn_CLR(_n1)                HW(LRADC_DELAYn_CLR(_n1))
+#define HWA_LRADC_DELAYn_CLR(_n1)               (HWA_LRADC_DELAYn(_n1) + 0x8)
+#define HWT_LRADC_DELAYn_CLR(_n1)               HWIO_32_WO
+#define HWN_LRADC_DELAYn_CLR(_n1)               LRADC_DELAYn
+#define HWI_LRADC_DELAYn_CLR(_n1)               (_n1)
+#define HW_LRADC_DELAYn_TOG(_n1)                HW(LRADC_DELAYn_TOG(_n1))
+#define HWA_LRADC_DELAYn_TOG(_n1)               (HWA_LRADC_DELAYn(_n1) + 0xc)
+#define HWT_LRADC_DELAYn_TOG(_n1)               HWIO_32_WO
+#define HWN_LRADC_DELAYn_TOG(_n1)               LRADC_DELAYn
+#define HWI_LRADC_DELAYn_TOG(_n1)               (_n1)
+#define BP_LRADC_DELAYn_TRIGGER_LRADCS          24
+#define BM_LRADC_DELAYn_TRIGGER_LRADCS          0xff000000
+#define BF_LRADC_DELAYn_TRIGGER_LRADCS(v)       (((v) & 0xff) << 24)
+#define BFM_LRADC_DELAYn_TRIGGER_LRADCS(v)      BM_LRADC_DELAYn_TRIGGER_LRADCS
+#define BF_LRADC_DELAYn_TRIGGER_LRADCS_V(e)     BF_LRADC_DELAYn_TRIGGER_LRADCS(BV_LRADC_DELAYn_TRIGGER_LRADCS__##e)
+#define BFM_LRADC_DELAYn_TRIGGER_LRADCS_V(v)    BM_LRADC_DELAYn_TRIGGER_LRADCS
+#define BP_LRADC_DELAYn_RSRVD2                  21
+#define BM_LRADC_DELAYn_RSRVD2                  0xe00000
+#define BF_LRADC_DELAYn_RSRVD2(v)               (((v) & 0x7) << 21)
+#define BFM_LRADC_DELAYn_RSRVD2(v)              BM_LRADC_DELAYn_RSRVD2
+#define BF_LRADC_DELAYn_RSRVD2_V(e)             BF_LRADC_DELAYn_RSRVD2(BV_LRADC_DELAYn_RSRVD2__##e)
+#define BFM_LRADC_DELAYn_RSRVD2_V(v)            BM_LRADC_DELAYn_RSRVD2
+#define BP_LRADC_DELAYn_KICK                    20
+#define BM_LRADC_DELAYn_KICK                    0x100000
+#define BF_LRADC_DELAYn_KICK(v)                 (((v) & 0x1) << 20)
+#define BFM_LRADC_DELAYn_KICK(v)                BM_LRADC_DELAYn_KICK
+#define BF_LRADC_DELAYn_KICK_V(e)               BF_LRADC_DELAYn_KICK(BV_LRADC_DELAYn_KICK__##e)
+#define BFM_LRADC_DELAYn_KICK_V(v)              BM_LRADC_DELAYn_KICK
+#define BP_LRADC_DELAYn_TRIGGER_DELAYS          16
+#define BM_LRADC_DELAYn_TRIGGER_DELAYS          0xf0000
+#define BF_LRADC_DELAYn_TRIGGER_DELAYS(v)       (((v) & 0xf) << 16)
+#define BFM_LRADC_DELAYn_TRIGGER_DELAYS(v)      BM_LRADC_DELAYn_TRIGGER_DELAYS
+#define BF_LRADC_DELAYn_TRIGGER_DELAYS_V(e)     BF_LRADC_DELAYn_TRIGGER_DELAYS(BV_LRADC_DELAYn_TRIGGER_DELAYS__##e)
+#define BFM_LRADC_DELAYn_TRIGGER_DELAYS_V(v)    BM_LRADC_DELAYn_TRIGGER_DELAYS
+#define BP_LRADC_DELAYn_LOOP_COUNT              11
+#define BM_LRADC_DELAYn_LOOP_COUNT              0xf800
+#define BF_LRADC_DELAYn_LOOP_COUNT(v)           (((v) & 0x1f) << 11)
+#define BFM_LRADC_DELAYn_LOOP_COUNT(v)          BM_LRADC_DELAYn_LOOP_COUNT
+#define BF_LRADC_DELAYn_LOOP_COUNT_V(e)         BF_LRADC_DELAYn_LOOP_COUNT(BV_LRADC_DELAYn_LOOP_COUNT__##e)
+#define BFM_LRADC_DELAYn_LOOP_COUNT_V(v)        BM_LRADC_DELAYn_LOOP_COUNT
+#define BP_LRADC_DELAYn_DELAY                   0
+#define BM_LRADC_DELAYn_DELAY                   0x7ff
+#define BF_LRADC_DELAYn_DELAY(v)                (((v) & 0x7ff) << 0)
+#define BFM_LRADC_DELAYn_DELAY(v)               BM_LRADC_DELAYn_DELAY
+#define BF_LRADC_DELAYn_DELAY_V(e)              BF_LRADC_DELAYn_DELAY(BV_LRADC_DELAYn_DELAY__##e)
+#define BFM_LRADC_DELAYn_DELAY_V(v)             BM_LRADC_DELAYn_DELAY
+
+#define HW_LRADC_DEBUG0                 HW(LRADC_DEBUG0)
+#define HWA_LRADC_DEBUG0                (0x80050000 + 0x110)
+#define HWT_LRADC_DEBUG0                HWIO_32_RW
+#define HWN_LRADC_DEBUG0                LRADC_DEBUG0
+#define HWI_LRADC_DEBUG0                
+#define HW_LRADC_DEBUG0_SET             HW(LRADC_DEBUG0_SET)
+#define HWA_LRADC_DEBUG0_SET            (HWA_LRADC_DEBUG0 + 0x4)
+#define HWT_LRADC_DEBUG0_SET            HWIO_32_WO
+#define HWN_LRADC_DEBUG0_SET            LRADC_DEBUG0
+#define HWI_LRADC_DEBUG0_SET            
+#define HW_LRADC_DEBUG0_CLR             HW(LRADC_DEBUG0_CLR)
+#define HWA_LRADC_DEBUG0_CLR            (HWA_LRADC_DEBUG0 + 0x8)
+#define HWT_LRADC_DEBUG0_CLR            HWIO_32_WO
+#define HWN_LRADC_DEBUG0_CLR            LRADC_DEBUG0
+#define HWI_LRADC_DEBUG0_CLR            
+#define HW_LRADC_DEBUG0_TOG             HW(LRADC_DEBUG0_TOG)
+#define HWA_LRADC_DEBUG0_TOG            (HWA_LRADC_DEBUG0 + 0xc)
+#define HWT_LRADC_DEBUG0_TOG            HWIO_32_WO
+#define HWN_LRADC_DEBUG0_TOG            LRADC_DEBUG0
+#define HWI_LRADC_DEBUG0_TOG            
+#define BP_LRADC_DEBUG0_READONLY        16
+#define BM_LRADC_DEBUG0_READONLY        0xffff0000
+#define BF_LRADC_DEBUG0_READONLY(v)     (((v) & 0xffff) << 16)
+#define BFM_LRADC_DEBUG0_READONLY(v)    BM_LRADC_DEBUG0_READONLY
+#define BF_LRADC_DEBUG0_READONLY_V(e)   BF_LRADC_DEBUG0_READONLY(BV_LRADC_DEBUG0_READONLY__##e)
+#define BFM_LRADC_DEBUG0_READONLY_V(v)  BM_LRADC_DEBUG0_READONLY
+#define BP_LRADC_DEBUG0_RSRVD1          12
+#define BM_LRADC_DEBUG0_RSRVD1          0xf000
+#define BF_LRADC_DEBUG0_RSRVD1(v)       (((v) & 0xf) << 12)
+#define BFM_LRADC_DEBUG0_RSRVD1(v)      BM_LRADC_DEBUG0_RSRVD1
+#define BF_LRADC_DEBUG0_RSRVD1_V(e)     BF_LRADC_DEBUG0_RSRVD1(BV_LRADC_DEBUG0_RSRVD1__##e)
+#define BFM_LRADC_DEBUG0_RSRVD1_V(v)    BM_LRADC_DEBUG0_RSRVD1
+#define BP_LRADC_DEBUG0_STATE           0
+#define BM_LRADC_DEBUG0_STATE           0xfff
+#define BF_LRADC_DEBUG0_STATE(v)        (((v) & 0xfff) << 0)
+#define BFM_LRADC_DEBUG0_STATE(v)       BM_LRADC_DEBUG0_STATE
+#define BF_LRADC_DEBUG0_STATE_V(e)      BF_LRADC_DEBUG0_STATE(BV_LRADC_DEBUG0_STATE__##e)
+#define BFM_LRADC_DEBUG0_STATE_V(v)     BM_LRADC_DEBUG0_STATE
+
+#define HW_LRADC_DEBUG1                         HW(LRADC_DEBUG1)
+#define HWA_LRADC_DEBUG1                        (0x80050000 + 0x120)
+#define HWT_LRADC_DEBUG1                        HWIO_32_RW
+#define HWN_LRADC_DEBUG1                        LRADC_DEBUG1
+#define HWI_LRADC_DEBUG1                        
+#define HW_LRADC_DEBUG1_SET                     HW(LRADC_DEBUG1_SET)
+#define HWA_LRADC_DEBUG1_SET                    (HWA_LRADC_DEBUG1 + 0x4)
+#define HWT_LRADC_DEBUG1_SET                    HWIO_32_WO
+#define HWN_LRADC_DEBUG1_SET                    LRADC_DEBUG1
+#define HWI_LRADC_DEBUG1_SET                    
+#define HW_LRADC_DEBUG1_CLR                     HW(LRADC_DEBUG1_CLR)
+#define HWA_LRADC_DEBUG1_CLR                    (HWA_LRADC_DEBUG1 + 0x8)
+#define HWT_LRADC_DEBUG1_CLR                    HWIO_32_WO
+#define HWN_LRADC_DEBUG1_CLR                    LRADC_DEBUG1
+#define HWI_LRADC_DEBUG1_CLR                    
+#define HW_LRADC_DEBUG1_TOG                     HW(LRADC_DEBUG1_TOG)
+#define HWA_LRADC_DEBUG1_TOG                    (HWA_LRADC_DEBUG1 + 0xc)
+#define HWT_LRADC_DEBUG1_TOG                    HWIO_32_WO
+#define HWN_LRADC_DEBUG1_TOG                    LRADC_DEBUG1
+#define HWI_LRADC_DEBUG1_TOG                    
+#define BP_LRADC_DEBUG1_RSRVD3                  24
+#define BM_LRADC_DEBUG1_RSRVD3                  0xff000000
+#define BF_LRADC_DEBUG1_RSRVD3(v)               (((v) & 0xff) << 24)
+#define BFM_LRADC_DEBUG1_RSRVD3(v)              BM_LRADC_DEBUG1_RSRVD3
+#define BF_LRADC_DEBUG1_RSRVD3_V(e)             BF_LRADC_DEBUG1_RSRVD3(BV_LRADC_DEBUG1_RSRVD3__##e)
+#define BFM_LRADC_DEBUG1_RSRVD3_V(v)            BM_LRADC_DEBUG1_RSRVD3
+#define BP_LRADC_DEBUG1_REQUEST                 16
+#define BM_LRADC_DEBUG1_REQUEST                 0xff0000
+#define BF_LRADC_DEBUG1_REQUEST(v)              (((v) & 0xff) << 16)
+#define BFM_LRADC_DEBUG1_REQUEST(v)             BM_LRADC_DEBUG1_REQUEST
+#define BF_LRADC_DEBUG1_REQUEST_V(e)            BF_LRADC_DEBUG1_REQUEST(BV_LRADC_DEBUG1_REQUEST__##e)
+#define BFM_LRADC_DEBUG1_REQUEST_V(v)           BM_LRADC_DEBUG1_REQUEST
+#define BP_LRADC_DEBUG1_RSRVD2                  13
+#define BM_LRADC_DEBUG1_RSRVD2                  0xe000
+#define BF_LRADC_DEBUG1_RSRVD2(v)               (((v) & 0x7) << 13)
+#define BFM_LRADC_DEBUG1_RSRVD2(v)              BM_LRADC_DEBUG1_RSRVD2
+#define BF_LRADC_DEBUG1_RSRVD2_V(e)             BF_LRADC_DEBUG1_RSRVD2(BV_LRADC_DEBUG1_RSRVD2__##e)
+#define BFM_LRADC_DEBUG1_RSRVD2_V(v)            BM_LRADC_DEBUG1_RSRVD2
+#define BP_LRADC_DEBUG1_TESTMODE_COUNT          8
+#define BM_LRADC_DEBUG1_TESTMODE_COUNT          0x1f00
+#define BF_LRADC_DEBUG1_TESTMODE_COUNT(v)       (((v) & 0x1f) << 8)
+#define BFM_LRADC_DEBUG1_TESTMODE_COUNT(v)      BM_LRADC_DEBUG1_TESTMODE_COUNT
+#define BF_LRADC_DEBUG1_TESTMODE_COUNT_V(e)     BF_LRADC_DEBUG1_TESTMODE_COUNT(BV_LRADC_DEBUG1_TESTMODE_COUNT__##e)
+#define BFM_LRADC_DEBUG1_TESTMODE_COUNT_V(v)    BM_LRADC_DEBUG1_TESTMODE_COUNT
+#define BP_LRADC_DEBUG1_RSRVD1                  3
+#define BM_LRADC_DEBUG1_RSRVD1                  0xf8
+#define BF_LRADC_DEBUG1_RSRVD1(v)               (((v) & 0x1f) << 3)
+#define BFM_LRADC_DEBUG1_RSRVD1(v)              BM_LRADC_DEBUG1_RSRVD1
+#define BF_LRADC_DEBUG1_RSRVD1_V(e)             BF_LRADC_DEBUG1_RSRVD1(BV_LRADC_DEBUG1_RSRVD1__##e)
+#define BFM_LRADC_DEBUG1_RSRVD1_V(v)            BM_LRADC_DEBUG1_RSRVD1
+#define BP_LRADC_DEBUG1_TESTMODE6               2
+#define BM_LRADC_DEBUG1_TESTMODE6               0x4
+#define BV_LRADC_DEBUG1_TESTMODE6__NORMAL       0x0
+#define BV_LRADC_DEBUG1_TESTMODE6__TEST         0x1
+#define BF_LRADC_DEBUG1_TESTMODE6(v)            (((v) & 0x1) << 2)
+#define BFM_LRADC_DEBUG1_TESTMODE6(v)           BM_LRADC_DEBUG1_TESTMODE6
+#define BF_LRADC_DEBUG1_TESTMODE6_V(e)          BF_LRADC_DEBUG1_TESTMODE6(BV_LRADC_DEBUG1_TESTMODE6__##e)
+#define BFM_LRADC_DEBUG1_TESTMODE6_V(v)         BM_LRADC_DEBUG1_TESTMODE6
+#define BP_LRADC_DEBUG1_TESTMODE5               1
+#define BM_LRADC_DEBUG1_TESTMODE5               0x2
+#define BV_LRADC_DEBUG1_TESTMODE5__NORMAL       0x0
+#define BV_LRADC_DEBUG1_TESTMODE5__TEST         0x1
+#define BF_LRADC_DEBUG1_TESTMODE5(v)            (((v) & 0x1) << 1)
+#define BFM_LRADC_DEBUG1_TESTMODE5(v)           BM_LRADC_DEBUG1_TESTMODE5
+#define BF_LRADC_DEBUG1_TESTMODE5_V(e)          BF_LRADC_DEBUG1_TESTMODE5(BV_LRADC_DEBUG1_TESTMODE5__##e)
+#define BFM_LRADC_DEBUG1_TESTMODE5_V(v)         BM_LRADC_DEBUG1_TESTMODE5
+#define BP_LRADC_DEBUG1_TESTMODE                0
+#define BM_LRADC_DEBUG1_TESTMODE                0x1
+#define BV_LRADC_DEBUG1_TESTMODE__NORMAL        0x0
+#define BV_LRADC_DEBUG1_TESTMODE__TEST          0x1
+#define BF_LRADC_DEBUG1_TESTMODE(v)             (((v) & 0x1) << 0)
+#define BFM_LRADC_DEBUG1_TESTMODE(v)            BM_LRADC_DEBUG1_TESTMODE
+#define BF_LRADC_DEBUG1_TESTMODE_V(e)           BF_LRADC_DEBUG1_TESTMODE(BV_LRADC_DEBUG1_TESTMODE__##e)
+#define BFM_LRADC_DEBUG1_TESTMODE_V(v)          BM_LRADC_DEBUG1_TESTMODE
+
+#define HW_LRADC_CONVERSION                             HW(LRADC_CONVERSION)
+#define HWA_LRADC_CONVERSION                            (0x80050000 + 0x130)
+#define HWT_LRADC_CONVERSION                            HWIO_32_RW
+#define HWN_LRADC_CONVERSION                            LRADC_CONVERSION
+#define HWI_LRADC_CONVERSION                            
+#define HW_LRADC_CONVERSION_SET                         HW(LRADC_CONVERSION_SET)
+#define HWA_LRADC_CONVERSION_SET                        (HWA_LRADC_CONVERSION + 0x4)
+#define HWT_LRADC_CONVERSION_SET                        HWIO_32_WO
+#define HWN_LRADC_CONVERSION_SET                        LRADC_CONVERSION
+#define HWI_LRADC_CONVERSION_SET                        
+#define HW_LRADC_CONVERSION_CLR                         HW(LRADC_CONVERSION_CLR)
+#define HWA_LRADC_CONVERSION_CLR                        (HWA_LRADC_CONVERSION + 0x8)
+#define HWT_LRADC_CONVERSION_CLR                        HWIO_32_WO
+#define HWN_LRADC_CONVERSION_CLR                        LRADC_CONVERSION
+#define HWI_LRADC_CONVERSION_CLR                        
+#define HW_LRADC_CONVERSION_TOG                         HW(LRADC_CONVERSION_TOG)
+#define HWA_LRADC_CONVERSION_TOG                        (HWA_LRADC_CONVERSION + 0xc)
+#define HWT_LRADC_CONVERSION_TOG                        HWIO_32_WO
+#define HWN_LRADC_CONVERSION_TOG                        LRADC_CONVERSION
+#define HWI_LRADC_CONVERSION_TOG                        
+#define BP_LRADC_CONVERSION_RSRVD3                      21
+#define BM_LRADC_CONVERSION_RSRVD3                      0xffe00000
+#define BF_LRADC_CONVERSION_RSRVD3(v)                   (((v) & 0x7ff) << 21)
+#define BFM_LRADC_CONVERSION_RSRVD3(v)                  BM_LRADC_CONVERSION_RSRVD3
+#define BF_LRADC_CONVERSION_RSRVD3_V(e)                 BF_LRADC_CONVERSION_RSRVD3(BV_LRADC_CONVERSION_RSRVD3__##e)
+#define BFM_LRADC_CONVERSION_RSRVD3_V(v)                BM_LRADC_CONVERSION_RSRVD3
+#define BP_LRADC_CONVERSION_AUTOMATIC                   20
+#define BM_LRADC_CONVERSION_AUTOMATIC                   0x100000
+#define BV_LRADC_CONVERSION_AUTOMATIC__DISABLE          0x0
+#define BV_LRADC_CONVERSION_AUTOMATIC__ENABLE           0x1
+#define BF_LRADC_CONVERSION_AUTOMATIC(v)                (((v) & 0x1) << 20)
+#define BFM_LRADC_CONVERSION_AUTOMATIC(v)               BM_LRADC_CONVERSION_AUTOMATIC
+#define BF_LRADC_CONVERSION_AUTOMATIC_V(e)              BF_LRADC_CONVERSION_AUTOMATIC(BV_LRADC_CONVERSION_AUTOMATIC__##e)
+#define BFM_LRADC_CONVERSION_AUTOMATIC_V(v)             BM_LRADC_CONVERSION_AUTOMATIC
+#define BP_LRADC_CONVERSION_RSRVD2                      18
+#define BM_LRADC_CONVERSION_RSRVD2                      0xc0000
+#define BF_LRADC_CONVERSION_RSRVD2(v)                   (((v) & 0x3) << 18)
+#define BFM_LRADC_CONVERSION_RSRVD2(v)                  BM_LRADC_CONVERSION_RSRVD2
+#define BF_LRADC_CONVERSION_RSRVD2_V(e)                 BF_LRADC_CONVERSION_RSRVD2(BV_LRADC_CONVERSION_RSRVD2__##e)
+#define BFM_LRADC_CONVERSION_RSRVD2_V(v)                BM_LRADC_CONVERSION_RSRVD2
+#define BP_LRADC_CONVERSION_SCALE_FACTOR                16
+#define BM_LRADC_CONVERSION_SCALE_FACTOR                0x30000
+#define BV_LRADC_CONVERSION_SCALE_FACTOR__NIMH          0x0
+#define BV_LRADC_CONVERSION_SCALE_FACTOR__DUAL_NIMH     0x1
+#define BV_LRADC_CONVERSION_SCALE_FACTOR__LI_ION        0x2
+#define BV_LRADC_CONVERSION_SCALE_FACTOR__ALT_LI_ION    0x3
+#define BF_LRADC_CONVERSION_SCALE_FACTOR(v)             (((v) & 0x3) << 16)
+#define BFM_LRADC_CONVERSION_SCALE_FACTOR(v)            BM_LRADC_CONVERSION_SCALE_FACTOR
+#define BF_LRADC_CONVERSION_SCALE_FACTOR_V(e)           BF_LRADC_CONVERSION_SCALE_FACTOR(BV_LRADC_CONVERSION_SCALE_FACTOR__##e)
+#define BFM_LRADC_CONVERSION_SCALE_FACTOR_V(v)          BM_LRADC_CONVERSION_SCALE_FACTOR
+#define BP_LRADC_CONVERSION_RSRVD1                      10
+#define BM_LRADC_CONVERSION_RSRVD1                      0xfc00
+#define BF_LRADC_CONVERSION_RSRVD1(v)                   (((v) & 0x3f) << 10)
+#define BFM_LRADC_CONVERSION_RSRVD1(v)                  BM_LRADC_CONVERSION_RSRVD1
+#define BF_LRADC_CONVERSION_RSRVD1_V(e)                 BF_LRADC_CONVERSION_RSRVD1(BV_LRADC_CONVERSION_RSRVD1__##e)
+#define BFM_LRADC_CONVERSION_RSRVD1_V(v)                BM_LRADC_CONVERSION_RSRVD1
+#define BP_LRADC_CONVERSION_SCALED_BATT_VOLTAGE         0
+#define BM_LRADC_CONVERSION_SCALED_BATT_VOLTAGE         0x3ff
+#define BF_LRADC_CONVERSION_SCALED_BATT_VOLTAGE(v)      (((v) & 0x3ff) << 0)
+#define BFM_LRADC_CONVERSION_SCALED_BATT_VOLTAGE(v)     BM_LRADC_CONVERSION_SCALED_BATT_VOLTAGE
+#define BF_LRADC_CONVERSION_SCALED_BATT_VOLTAGE_V(e)    BF_LRADC_CONVERSION_SCALED_BATT_VOLTAGE(BV_LRADC_CONVERSION_SCALED_BATT_VOLTAGE__##e)
+#define BFM_LRADC_CONVERSION_SCALED_BATT_VOLTAGE_V(v)   BM_LRADC_CONVERSION_SCALED_BATT_VOLTAGE
+
+#define HW_LRADC_CTRL4                          HW(LRADC_CTRL4)
+#define HWA_LRADC_CTRL4                         (0x80050000 + 0x140)
+#define HWT_LRADC_CTRL4                         HWIO_32_RW
+#define HWN_LRADC_CTRL4                         LRADC_CTRL4
+#define HWI_LRADC_CTRL4                         
+#define HW_LRADC_CTRL4_SET                      HW(LRADC_CTRL4_SET)
+#define HWA_LRADC_CTRL4_SET                     (HWA_LRADC_CTRL4 + 0x4)
+#define HWT_LRADC_CTRL4_SET                     HWIO_32_WO
+#define HWN_LRADC_CTRL4_SET                     LRADC_CTRL4
+#define HWI_LRADC_CTRL4_SET                     
+#define HW_LRADC_CTRL4_CLR                      HW(LRADC_CTRL4_CLR)
+#define HWA_LRADC_CTRL4_CLR                     (HWA_LRADC_CTRL4 + 0x8)
+#define HWT_LRADC_CTRL4_CLR                     HWIO_32_WO
+#define HWN_LRADC_CTRL4_CLR                     LRADC_CTRL4
+#define HWI_LRADC_CTRL4_CLR                     
+#define HW_LRADC_CTRL4_TOG                      HW(LRADC_CTRL4_TOG)
+#define HWA_LRADC_CTRL4_TOG                     (HWA_LRADC_CTRL4 + 0xc)
+#define HWT_LRADC_CTRL4_TOG                     HWIO_32_WO
+#define HWN_LRADC_CTRL4_TOG                     LRADC_CTRL4
+#define HWI_LRADC_CTRL4_TOG                     
+#define BP_LRADC_CTRL4_LRADC7SELECT             28
+#define BM_LRADC_CTRL4_LRADC7SELECT             0xf0000000
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL0   0x0
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL1   0x1
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL2   0x2
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL3   0x3
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL4   0x4
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL5   0x5
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL6   0x6
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL7   0x7
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL8   0x8
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL9   0x9
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL10  0xa
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL11  0xb
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL12  0xc
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL13  0xd
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL14  0xe
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL15  0xf
+#define BF_LRADC_CTRL4_LRADC7SELECT(v)          (((v) & 0xf) << 28)
+#define BFM_LRADC_CTRL4_LRADC7SELECT(v)         BM_LRADC_CTRL4_LRADC7SELECT
+#define BF_LRADC_CTRL4_LRADC7SELECT_V(e)        BF_LRADC_CTRL4_LRADC7SELECT(BV_LRADC_CTRL4_LRADC7SELECT__##e)
+#define BFM_LRADC_CTRL4_LRADC7SELECT_V(v)       BM_LRADC_CTRL4_LRADC7SELECT
+#define BP_LRADC_CTRL4_LRADC6SELECT             24
+#define BM_LRADC_CTRL4_LRADC6SELECT             0xf000000
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL0   0x0
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL1   0x1
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL2   0x2
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL3   0x3
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL4   0x4
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL5   0x5
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL6   0x6
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL7   0x7
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL8   0x8
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL9   0x9
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL10  0xa
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL11  0xb
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL12  0xc
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL13  0xd
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL14  0xe
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL15  0xf
+#define BF_LRADC_CTRL4_LRADC6SELECT(v)          (((v) & 0xf) << 24)
+#define BFM_LRADC_CTRL4_LRADC6SELECT(v)         BM_LRADC_CTRL4_LRADC6SELECT
+#define BF_LRADC_CTRL4_LRADC6SELECT_V(e)        BF_LRADC_CTRL4_LRADC6SELECT(BV_LRADC_CTRL4_LRADC6SELECT__##e)
+#define BFM_LRADC_CTRL4_LRADC6SELECT_V(v)       BM_LRADC_CTRL4_LRADC6SELECT
+#define BP_LRADC_CTRL4_LRADC5SELECT             20
+#define BM_LRADC_CTRL4_LRADC5SELECT             0xf00000
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL0   0x0
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL1   0x1
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL2   0x2
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL3   0x3
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL4   0x4
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL5   0x5
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL6   0x6
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL7   0x7
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL8   0x8
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL9   0x9
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL10  0xa
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL11  0xb
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL12  0xc
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL13  0xd
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL14  0xe
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL15  0xf
+#define BF_LRADC_CTRL4_LRADC5SELECT(v)          (((v) & 0xf) << 20)
+#define BFM_LRADC_CTRL4_LRADC5SELECT(v)         BM_LRADC_CTRL4_LRADC5SELECT
+#define BF_LRADC_CTRL4_LRADC5SELECT_V(e)        BF_LRADC_CTRL4_LRADC5SELECT(BV_LRADC_CTRL4_LRADC5SELECT__##e)
+#define BFM_LRADC_CTRL4_LRADC5SELECT_V(v)       BM_LRADC_CTRL4_LRADC5SELECT
+#define BP_LRADC_CTRL4_LRADC4SELECT             16
+#define BM_LRADC_CTRL4_LRADC4SELECT             0xf0000
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL0   0x0
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL1   0x1
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL2   0x2
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL3   0x3
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL4   0x4
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL5   0x5
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL6   0x6
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL7   0x7
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL8   0x8
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL9   0x9
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL10  0xa
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL11  0xb
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL12  0xc
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL13  0xd
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL14  0xe
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL15  0xf
+#define BF_LRADC_CTRL4_LRADC4SELECT(v)          (((v) & 0xf) << 16)
+#define BFM_LRADC_CTRL4_LRADC4SELECT(v)         BM_LRADC_CTRL4_LRADC4SELECT
+#define BF_LRADC_CTRL4_LRADC4SELECT_V(e)        BF_LRADC_CTRL4_LRADC4SELECT(BV_LRADC_CTRL4_LRADC4SELECT__##e)
+#define BFM_LRADC_CTRL4_LRADC4SELECT_V(v)       BM_LRADC_CTRL4_LRADC4SELECT
+#define BP_LRADC_CTRL4_LRADC3SELECT             12
+#define BM_LRADC_CTRL4_LRADC3SELECT             0xf000
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL0   0x0
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL1   0x1
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL2   0x2
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL3   0x3
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL4   0x4
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL5   0x5
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL6   0x6
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL7   0x7
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL8   0x8
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL9   0x9
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL10  0xa
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL11  0xb
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL12  0xc
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL13  0xd
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL14  0xe
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL15  0xf
+#define BF_LRADC_CTRL4_LRADC3SELECT(v)          (((v) & 0xf) << 12)
+#define BFM_LRADC_CTRL4_LRADC3SELECT(v)         BM_LRADC_CTRL4_LRADC3SELECT
+#define BF_LRADC_CTRL4_LRADC3SELECT_V(e)        BF_LRADC_CTRL4_LRADC3SELECT(BV_LRADC_CTRL4_LRADC3SELECT__##e)
+#define BFM_LRADC_CTRL4_LRADC3SELECT_V(v)       BM_LRADC_CTRL4_LRADC3SELECT
+#define BP_LRADC_CTRL4_LRADC2SELECT             8
+#define BM_LRADC_CTRL4_LRADC2SELECT             0xf00
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL0   0x0
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL1   0x1
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL2   0x2
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL3   0x3
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL4   0x4
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL5   0x5
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL6   0x6
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL7   0x7
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL8   0x8
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL9   0x9
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL10  0xa
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL11  0xb
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL12  0xc
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL13  0xd
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL14  0xe
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL15  0xf
+#define BF_LRADC_CTRL4_LRADC2SELECT(v)          (((v) & 0xf) << 8)
+#define BFM_LRADC_CTRL4_LRADC2SELECT(v)         BM_LRADC_CTRL4_LRADC2SELECT
+#define BF_LRADC_CTRL4_LRADC2SELECT_V(e)        BF_LRADC_CTRL4_LRADC2SELECT(BV_LRADC_CTRL4_LRADC2SELECT__##e)
+#define BFM_LRADC_CTRL4_LRADC2SELECT_V(v)       BM_LRADC_CTRL4_LRADC2SELECT
+#define BP_LRADC_CTRL4_LRADC1SELECT             4
+#define BM_LRADC_CTRL4_LRADC1SELECT             0xf0
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL0   0x0
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL1   0x1
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL2   0x2
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL3   0x3
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL4   0x4
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL5   0x5
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL6   0x6
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL7   0x7
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL8   0x8
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL9   0x9
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL10  0xa
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL11  0xb
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL12  0xc
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL13  0xd
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL14  0xe
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL15  0xf
+#define BF_LRADC_CTRL4_LRADC1SELECT(v)          (((v) & 0xf) << 4)
+#define BFM_LRADC_CTRL4_LRADC1SELECT(v)         BM_LRADC_CTRL4_LRADC1SELECT
+#define BF_LRADC_CTRL4_LRADC1SELECT_V(e)        BF_LRADC_CTRL4_LRADC1SELECT(BV_LRADC_CTRL4_LRADC1SELECT__##e)
+#define BFM_LRADC_CTRL4_LRADC1SELECT_V(v)       BM_LRADC_CTRL4_LRADC1SELECT
+#define BP_LRADC_CTRL4_LRADC0SELECT             0
+#define BM_LRADC_CTRL4_LRADC0SELECT             0xf
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL0   0x0
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL1   0x1
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL2   0x2
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL3   0x3
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL4   0x4
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL5   0x5
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL6   0x6
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL7   0x7
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL8   0x8
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL9   0x9
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL10  0xa
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL11  0xb
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL12  0xc
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL13  0xd
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL14  0xe
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL15  0xf
+#define BF_LRADC_CTRL4_LRADC0SELECT(v)          (((v) & 0xf) << 0)
+#define BFM_LRADC_CTRL4_LRADC0SELECT(v)         BM_LRADC_CTRL4_LRADC0SELECT
+#define BF_LRADC_CTRL4_LRADC0SELECT_V(e)        BF_LRADC_CTRL4_LRADC0SELECT(BV_LRADC_CTRL4_LRADC0SELECT__##e)
+#define BFM_LRADC_CTRL4_LRADC0SELECT_V(v)       BM_LRADC_CTRL4_LRADC0SELECT
+
+#define HW_LRADC_VERSION                HW(LRADC_VERSION)
+#define HWA_LRADC_VERSION               (0x80050000 + 0x150)
+#define HWT_LRADC_VERSION               HWIO_32_RW
+#define HWN_LRADC_VERSION               LRADC_VERSION
+#define HWI_LRADC_VERSION               
+#define BP_LRADC_VERSION_MAJOR          24
+#define BM_LRADC_VERSION_MAJOR          0xff000000
+#define BF_LRADC_VERSION_MAJOR(v)       (((v) & 0xff) << 24)
+#define BFM_LRADC_VERSION_MAJOR(v)      BM_LRADC_VERSION_MAJOR
+#define BF_LRADC_VERSION_MAJOR_V(e)     BF_LRADC_VERSION_MAJOR(BV_LRADC_VERSION_MAJOR__##e)
+#define BFM_LRADC_VERSION_MAJOR_V(v)    BM_LRADC_VERSION_MAJOR
+#define BP_LRADC_VERSION_MINOR          16
+#define BM_LRADC_VERSION_MINOR          0xff0000
+#define BF_LRADC_VERSION_MINOR(v)       (((v) & 0xff) << 16)
+#define BFM_LRADC_VERSION_MINOR(v)      BM_LRADC_VERSION_MINOR
+#define BF_LRADC_VERSION_MINOR_V(e)     BF_LRADC_VERSION_MINOR(BV_LRADC_VERSION_MINOR__##e)
+#define BFM_LRADC_VERSION_MINOR_V(v)    BM_LRADC_VERSION_MINOR
+#define BP_LRADC_VERSION_STEP           0
+#define BM_LRADC_VERSION_STEP           0xffff
+#define BF_LRADC_VERSION_STEP(v)        (((v) & 0xffff) << 0)
+#define BFM_LRADC_VERSION_STEP(v)       BM_LRADC_VERSION_STEP
+#define BF_LRADC_VERSION_STEP_V(e)      BF_LRADC_VERSION_STEP(BV_LRADC_VERSION_STEP__##e)
+#define BFM_LRADC_VERSION_STEP_V(v)     BM_LRADC_VERSION_STEP
+
+#endif /* __HEADERGEN_IMX233_LRADC_H__*/
diff --git a/firmware/target/arm/imx233/regs/imx233/ocotp.h b/firmware/target/arm/imx233/regs/imx233/ocotp.h
new file mode 100644
index 0000000000..64c4928697
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/imx233/ocotp.h
@@ -0,0 +1,451 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * imx233 version: 2.4.0
+ * imx233 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_IMX233_OCOTP_H__
+#define __HEADERGEN_IMX233_OCOTP_H__
+
+#define HW_OCOTP_CTRL                       HW(OCOTP_CTRL)
+#define HWA_OCOTP_CTRL                      (0x8002c000 + 0x0)
+#define HWT_OCOTP_CTRL                      HWIO_32_RW
+#define HWN_OCOTP_CTRL                      OCOTP_CTRL
+#define HWI_OCOTP_CTRL                      
+#define HW_OCOTP_CTRL_SET                   HW(OCOTP_CTRL_SET)
+#define HWA_OCOTP_CTRL_SET                  (HWA_OCOTP_CTRL + 0x4)
+#define HWT_OCOTP_CTRL_SET                  HWIO_32_WO
+#define HWN_OCOTP_CTRL_SET                  OCOTP_CTRL
+#define HWI_OCOTP_CTRL_SET                  
+#define HW_OCOTP_CTRL_CLR                   HW(OCOTP_CTRL_CLR)
+#define HWA_OCOTP_CTRL_CLR                  (HWA_OCOTP_CTRL + 0x8)
+#define HWT_OCOTP_CTRL_CLR                  HWIO_32_WO
+#define HWN_OCOTP_CTRL_CLR                  OCOTP_CTRL
+#define HWI_OCOTP_CTRL_CLR                  
+#define HW_OCOTP_CTRL_TOG                   HW(OCOTP_CTRL_TOG)
+#define HWA_OCOTP_CTRL_TOG                  (HWA_OCOTP_CTRL + 0xc)
+#define HWT_OCOTP_CTRL_TOG                  HWIO_32_WO
+#define HWN_OCOTP_CTRL_TOG                  OCOTP_CTRL
+#define HWI_OCOTP_CTRL_TOG                  
+#define BP_OCOTP_CTRL_WR_UNLOCK             16
+#define BM_OCOTP_CTRL_WR_UNLOCK             0xffff0000
+#define BV_OCOTP_CTRL_WR_UNLOCK__KEY        0x3e77
+#define BF_OCOTP_CTRL_WR_UNLOCK(v)          (((v) & 0xffff) << 16)
+#define BFM_OCOTP_CTRL_WR_UNLOCK(v)         BM_OCOTP_CTRL_WR_UNLOCK
+#define BF_OCOTP_CTRL_WR_UNLOCK_V(e)        BF_OCOTP_CTRL_WR_UNLOCK(BV_OCOTP_CTRL_WR_UNLOCK__##e)
+#define BFM_OCOTP_CTRL_WR_UNLOCK_V(v)       BM_OCOTP_CTRL_WR_UNLOCK
+#define BP_OCOTP_CTRL_RSRVD2                14
+#define BM_OCOTP_CTRL_RSRVD2                0xc000
+#define BF_OCOTP_CTRL_RSRVD2(v)             (((v) & 0x3) << 14)
+#define BFM_OCOTP_CTRL_RSRVD2(v)            BM_OCOTP_CTRL_RSRVD2
+#define BF_OCOTP_CTRL_RSRVD2_V(e)           BF_OCOTP_CTRL_RSRVD2(BV_OCOTP_CTRL_RSRVD2__##e)
+#define BFM_OCOTP_CTRL_RSRVD2_V(v)          BM_OCOTP_CTRL_RSRVD2
+#define BP_OCOTP_CTRL_RELOAD_SHADOWS        13
+#define BM_OCOTP_CTRL_RELOAD_SHADOWS        0x2000
+#define BF_OCOTP_CTRL_RELOAD_SHADOWS(v)     (((v) & 0x1) << 13)
+#define BFM_OCOTP_CTRL_RELOAD_SHADOWS(v)    BM_OCOTP_CTRL_RELOAD_SHADOWS
+#define BF_OCOTP_CTRL_RELOAD_SHADOWS_V(e)   BF_OCOTP_CTRL_RELOAD_SHADOWS(BV_OCOTP_CTRL_RELOAD_SHADOWS__##e)
+#define BFM_OCOTP_CTRL_RELOAD_SHADOWS_V(v)  BM_OCOTP_CTRL_RELOAD_SHADOWS
+#define BP_OCOTP_CTRL_RD_BANK_OPEN          12
+#define BM_OCOTP_CTRL_RD_BANK_OPEN          0x1000
+#define BF_OCOTP_CTRL_RD_BANK_OPEN(v)       (((v) & 0x1) << 12)
+#define BFM_OCOTP_CTRL_RD_BANK_OPEN(v)      BM_OCOTP_CTRL_RD_BANK_OPEN
+#define BF_OCOTP_CTRL_RD_BANK_OPEN_V(e)     BF_OCOTP_CTRL_RD_BANK_OPEN(BV_OCOTP_CTRL_RD_BANK_OPEN__##e)
+#define BFM_OCOTP_CTRL_RD_BANK_OPEN_V(v)    BM_OCOTP_CTRL_RD_BANK_OPEN
+#define BP_OCOTP_CTRL_RSRVD1                10
+#define BM_OCOTP_CTRL_RSRVD1                0xc00
+#define BF_OCOTP_CTRL_RSRVD1(v)             (((v) & 0x3) << 10)
+#define BFM_OCOTP_CTRL_RSRVD1(v)            BM_OCOTP_CTRL_RSRVD1
+#define BF_OCOTP_CTRL_RSRVD1_V(e)           BF_OCOTP_CTRL_RSRVD1(BV_OCOTP_CTRL_RSRVD1__##e)
+#define BFM_OCOTP_CTRL_RSRVD1_V(v)          BM_OCOTP_CTRL_RSRVD1
+#define BP_OCOTP_CTRL_ERROR                 9
+#define BM_OCOTP_CTRL_ERROR                 0x200
+#define BF_OCOTP_CTRL_ERROR(v)              (((v) & 0x1) << 9)
+#define BFM_OCOTP_CTRL_ERROR(v)             BM_OCOTP_CTRL_ERROR
+#define BF_OCOTP_CTRL_ERROR_V(e)            BF_OCOTP_CTRL_ERROR(BV_OCOTP_CTRL_ERROR__##e)
+#define BFM_OCOTP_CTRL_ERROR_V(v)           BM_OCOTP_CTRL_ERROR
+#define BP_OCOTP_CTRL_BUSY                  8
+#define BM_OCOTP_CTRL_BUSY                  0x100
+#define BF_OCOTP_CTRL_BUSY(v)               (((v) & 0x1) << 8)
+#define BFM_OCOTP_CTRL_BUSY(v)              BM_OCOTP_CTRL_BUSY
+#define BF_OCOTP_CTRL_BUSY_V(e)             BF_OCOTP_CTRL_BUSY(BV_OCOTP_CTRL_BUSY__##e)
+#define BFM_OCOTP_CTRL_BUSY_V(v)            BM_OCOTP_CTRL_BUSY
+#define BP_OCOTP_CTRL_RSRVD0                5
+#define BM_OCOTP_CTRL_RSRVD0                0xe0
+#define BF_OCOTP_CTRL_RSRVD0(v)             (((v) & 0x7) << 5)
+#define BFM_OCOTP_CTRL_RSRVD0(v)            BM_OCOTP_CTRL_RSRVD0
+#define BF_OCOTP_CTRL_RSRVD0_V(e)           BF_OCOTP_CTRL_RSRVD0(BV_OCOTP_CTRL_RSRVD0__##e)
+#define BFM_OCOTP_CTRL_RSRVD0_V(v)          BM_OCOTP_CTRL_RSRVD0
+#define BP_OCOTP_CTRL_ADDR                  0
+#define BM_OCOTP_CTRL_ADDR                  0x1f
+#define BF_OCOTP_CTRL_ADDR(v)               (((v) & 0x1f) << 0)
+#define BFM_OCOTP_CTRL_ADDR(v)              BM_OCOTP_CTRL_ADDR
+#define BF_OCOTP_CTRL_ADDR_V(e)             BF_OCOTP_CTRL_ADDR(BV_OCOTP_CTRL_ADDR__##e)
+#define BFM_OCOTP_CTRL_ADDR_V(v)            BM_OCOTP_CTRL_ADDR
+
+#define HW_OCOTP_DATA               HW(OCOTP_DATA)
+#define HWA_OCOTP_DATA              (0x8002c000 + 0x10)
+#define HWT_OCOTP_DATA              HWIO_32_RW
+#define HWN_OCOTP_DATA              OCOTP_DATA
+#define HWI_OCOTP_DATA              
+#define BP_OCOTP_DATA_DATA          0
+#define BM_OCOTP_DATA_DATA          0xffffffff
+#define BF_OCOTP_DATA_DATA(v)       (((v) & 0xffffffff) << 0)
+#define BFM_OCOTP_DATA_DATA(v)      BM_OCOTP_DATA_DATA
+#define BF_OCOTP_DATA_DATA_V(e)     BF_OCOTP_DATA_DATA(BV_OCOTP_DATA_DATA__##e)
+#define BFM_OCOTP_DATA_DATA_V(v)    BM_OCOTP_DATA_DATA
+
+#define HW_OCOTP_CUSTn(_n1)         HW(OCOTP_CUSTn(_n1))
+#define HWA_OCOTP_CUSTn(_n1)        (0x8002c000 + 0x20 + (_n1) * 0x10)
+#define HWT_OCOTP_CUSTn(_n1)        HWIO_32_RW
+#define HWN_OCOTP_CUSTn(_n1)        OCOTP_CUSTn
+#define HWI_OCOTP_CUSTn(_n1)        (_n1)
+#define BP_OCOTP_CUSTn_BITS         0
+#define BM_OCOTP_CUSTn_BITS         0xffffffff
+#define BF_OCOTP_CUSTn_BITS(v)      (((v) & 0xffffffff) << 0)
+#define BFM_OCOTP_CUSTn_BITS(v)     BM_OCOTP_CUSTn_BITS
+#define BF_OCOTP_CUSTn_BITS_V(e)    BF_OCOTP_CUSTn_BITS(BV_OCOTP_CUSTn_BITS__##e)
+#define BFM_OCOTP_CUSTn_BITS_V(v)   BM_OCOTP_CUSTn_BITS
+
+#define HW_OCOTP_CRYPTOn(_n1)       HW(OCOTP_CRYPTOn(_n1))
+#define HWA_OCOTP_CRYPTOn(_n1)      (0x8002c000 + 0x60 + (_n1) * 0x10)
+#define HWT_OCOTP_CRYPTOn(_n1)      HWIO_32_RW
+#define HWN_OCOTP_CRYPTOn(_n1)      OCOTP_CRYPTOn
+#define HWI_OCOTP_CRYPTOn(_n1)      (_n1)
+#define BP_OCOTP_CRYPTOn_BITS       0
+#define BM_OCOTP_CRYPTOn_BITS       0xffffffff
+#define BF_OCOTP_CRYPTOn_BITS(v)    (((v) & 0xffffffff) << 0)
+#define BFM_OCOTP_CRYPTOn_BITS(v)   BM_OCOTP_CRYPTOn_BITS
+#define BF_OCOTP_CRYPTOn_BITS_V(e)  BF_OCOTP_CRYPTOn_BITS(BV_OCOTP_CRYPTOn_BITS__##e)
+#define BFM_OCOTP_CRYPTOn_BITS_V(v) BM_OCOTP_CRYPTOn_BITS
+
+#define HW_OCOTP_HWCAPn(_n1)        HW(OCOTP_HWCAPn(_n1))
+#define HWA_OCOTP_HWCAPn(_n1)       (0x8002c000 + 0xa0 + (_n1) * 0x10)
+#define HWT_OCOTP_HWCAPn(_n1)       HWIO_32_RW
+#define HWN_OCOTP_HWCAPn(_n1)       OCOTP_HWCAPn
+#define HWI_OCOTP_HWCAPn(_n1)       (_n1)
+#define BP_OCOTP_HWCAPn_BITS        0
+#define BM_OCOTP_HWCAPn_BITS        0xffffffff
+#define BF_OCOTP_HWCAPn_BITS(v)     (((v) & 0xffffffff) << 0)
+#define BFM_OCOTP_HWCAPn_BITS(v)    BM_OCOTP_HWCAPn_BITS
+#define BF_OCOTP_HWCAPn_BITS_V(e)   BF_OCOTP_HWCAPn_BITS(BV_OCOTP_HWCAPn_BITS__##e)
+#define BFM_OCOTP_HWCAPn_BITS_V(v)  BM_OCOTP_HWCAPn_BITS
+
+#define HW_OCOTP_SWCAP              HW(OCOTP_SWCAP)
+#define HWA_OCOTP_SWCAP             (0x8002c000 + 0x100)
+#define HWT_OCOTP_SWCAP             HWIO_32_RW
+#define HWN_OCOTP_SWCAP             OCOTP_SWCAP
+#define HWI_OCOTP_SWCAP             
+#define BP_OCOTP_SWCAP_BITS         0
+#define BM_OCOTP_SWCAP_BITS         0xffffffff
+#define BF_OCOTP_SWCAP_BITS(v)      (((v) & 0xffffffff) << 0)
+#define BFM_OCOTP_SWCAP_BITS(v)     BM_OCOTP_SWCAP_BITS
+#define BF_OCOTP_SWCAP_BITS_V(e)    BF_OCOTP_SWCAP_BITS(BV_OCOTP_SWCAP_BITS__##e)
+#define BFM_OCOTP_SWCAP_BITS_V(v)   BM_OCOTP_SWCAP_BITS
+
+#define HW_OCOTP_CUSTCAP                                HW(OCOTP_CUSTCAP)
+#define HWA_OCOTP_CUSTCAP                               (0x8002c000 + 0x110)
+#define HWT_OCOTP_CUSTCAP                               HWIO_32_RW
+#define HWN_OCOTP_CUSTCAP                               OCOTP_CUSTCAP
+#define HWI_OCOTP_CUSTCAP                               
+#define BP_OCOTP_CUSTCAP_CUST_DISABLE_WMADRM9           31
+#define BM_OCOTP_CUSTCAP_CUST_DISABLE_WMADRM9           0x80000000
+#define BF_OCOTP_CUSTCAP_CUST_DISABLE_WMADRM9(v)        (((v) & 0x1) << 31)
+#define BFM_OCOTP_CUSTCAP_CUST_DISABLE_WMADRM9(v)       BM_OCOTP_CUSTCAP_CUST_DISABLE_WMADRM9
+#define BF_OCOTP_CUSTCAP_CUST_DISABLE_WMADRM9_V(e)      BF_OCOTP_CUSTCAP_CUST_DISABLE_WMADRM9(BV_OCOTP_CUSTCAP_CUST_DISABLE_WMADRM9__##e)
+#define BFM_OCOTP_CUSTCAP_CUST_DISABLE_WMADRM9_V(v)     BM_OCOTP_CUSTCAP_CUST_DISABLE_WMADRM9
+#define BP_OCOTP_CUSTCAP_CUST_DISABLE_JANUSDRM10        30
+#define BM_OCOTP_CUSTCAP_CUST_DISABLE_JANUSDRM10        0x40000000
+#define BF_OCOTP_CUSTCAP_CUST_DISABLE_JANUSDRM10(v)     (((v) & 0x1) << 30)
+#define BFM_OCOTP_CUSTCAP_CUST_DISABLE_JANUSDRM10(v)    BM_OCOTP_CUSTCAP_CUST_DISABLE_JANUSDRM10
+#define BF_OCOTP_CUSTCAP_CUST_DISABLE_JANUSDRM10_V(e)   BF_OCOTP_CUSTCAP_CUST_DISABLE_JANUSDRM10(BV_OCOTP_CUSTCAP_CUST_DISABLE_JANUSDRM10__##e)
+#define BFM_OCOTP_CUSTCAP_CUST_DISABLE_JANUSDRM10_V(v)  BM_OCOTP_CUSTCAP_CUST_DISABLE_JANUSDRM10
+#define BP_OCOTP_CUSTCAP_RSRVD1                         5
+#define BM_OCOTP_CUSTCAP_RSRVD1                         0x3fffffe0
+#define BF_OCOTP_CUSTCAP_RSRVD1(v)                      (((v) & 0x1ffffff) << 5)
+#define BFM_OCOTP_CUSTCAP_RSRVD1(v)                     BM_OCOTP_CUSTCAP_RSRVD1
+#define BF_OCOTP_CUSTCAP_RSRVD1_V(e)                    BF_OCOTP_CUSTCAP_RSRVD1(BV_OCOTP_CUSTCAP_RSRVD1__##e)
+#define BFM_OCOTP_CUSTCAP_RSRVD1_V(v)                   BM_OCOTP_CUSTCAP_RSRVD1
+#define BP_OCOTP_CUSTCAP_ENABLE_SJTAG_12MA_DRIVE        4
+#define BM_OCOTP_CUSTCAP_ENABLE_SJTAG_12MA_DRIVE        0x10
+#define BF_OCOTP_CUSTCAP_ENABLE_SJTAG_12MA_DRIVE(v)     (((v) & 0x1) << 4)
+#define BFM_OCOTP_CUSTCAP_ENABLE_SJTAG_12MA_DRIVE(v)    BM_OCOTP_CUSTCAP_ENABLE_SJTAG_12MA_DRIVE
+#define BF_OCOTP_CUSTCAP_ENABLE_SJTAG_12MA_DRIVE_V(e)   BF_OCOTP_CUSTCAP_ENABLE_SJTAG_12MA_DRIVE(BV_OCOTP_CUSTCAP_ENABLE_SJTAG_12MA_DRIVE__##e)
+#define BFM_OCOTP_CUSTCAP_ENABLE_SJTAG_12MA_DRIVE_V(v)  BM_OCOTP_CUSTCAP_ENABLE_SJTAG_12MA_DRIVE
+#define BP_OCOTP_CUSTCAP_USE_PARALLEL_JTAG              3
+#define BM_OCOTP_CUSTCAP_USE_PARALLEL_JTAG              0x8
+#define BF_OCOTP_CUSTCAP_USE_PARALLEL_JTAG(v)           (((v) & 0x1) << 3)
+#define BFM_OCOTP_CUSTCAP_USE_PARALLEL_JTAG(v)          BM_OCOTP_CUSTCAP_USE_PARALLEL_JTAG
+#define BF_OCOTP_CUSTCAP_USE_PARALLEL_JTAG_V(e)         BF_OCOTP_CUSTCAP_USE_PARALLEL_JTAG(BV_OCOTP_CUSTCAP_USE_PARALLEL_JTAG__##e)
+#define BFM_OCOTP_CUSTCAP_USE_PARALLEL_JTAG_V(v)        BM_OCOTP_CUSTCAP_USE_PARALLEL_JTAG
+#define BP_OCOTP_CUSTCAP_RTC_XTAL_32768_PRESENT         2
+#define BM_OCOTP_CUSTCAP_RTC_XTAL_32768_PRESENT         0x4
+#define BF_OCOTP_CUSTCAP_RTC_XTAL_32768_PRESENT(v)      (((v) & 0x1) << 2)
+#define BFM_OCOTP_CUSTCAP_RTC_XTAL_32768_PRESENT(v)     BM_OCOTP_CUSTCAP_RTC_XTAL_32768_PRESENT
+#define BF_OCOTP_CUSTCAP_RTC_XTAL_32768_PRESENT_V(e)    BF_OCOTP_CUSTCAP_RTC_XTAL_32768_PRESENT(BV_OCOTP_CUSTCAP_RTC_XTAL_32768_PRESENT__##e)
+#define BFM_OCOTP_CUSTCAP_RTC_XTAL_32768_PRESENT_V(v)   BM_OCOTP_CUSTCAP_RTC_XTAL_32768_PRESENT
+#define BP_OCOTP_CUSTCAP_RTC_XTAL_32000_PRESENT         1
+#define BM_OCOTP_CUSTCAP_RTC_XTAL_32000_PRESENT         0x2
+#define BF_OCOTP_CUSTCAP_RTC_XTAL_32000_PRESENT(v)      (((v) & 0x1) << 1)
+#define BFM_OCOTP_CUSTCAP_RTC_XTAL_32000_PRESENT(v)     BM_OCOTP_CUSTCAP_RTC_XTAL_32000_PRESENT
+#define BF_OCOTP_CUSTCAP_RTC_XTAL_32000_PRESENT_V(e)    BF_OCOTP_CUSTCAP_RTC_XTAL_32000_PRESENT(BV_OCOTP_CUSTCAP_RTC_XTAL_32000_PRESENT__##e)
+#define BFM_OCOTP_CUSTCAP_RTC_XTAL_32000_PRESENT_V(v)   BM_OCOTP_CUSTCAP_RTC_XTAL_32000_PRESENT
+#define BP_OCOTP_CUSTCAP_RSRVD0                         0
+#define BM_OCOTP_CUSTCAP_RSRVD0                         0x1
+#define BF_OCOTP_CUSTCAP_RSRVD0(v)                      (((v) & 0x1) << 0)
+#define BFM_OCOTP_CUSTCAP_RSRVD0(v)                     BM_OCOTP_CUSTCAP_RSRVD0
+#define BF_OCOTP_CUSTCAP_RSRVD0_V(e)                    BF_OCOTP_CUSTCAP_RSRVD0(BV_OCOTP_CUSTCAP_RSRVD0__##e)
+#define BFM_OCOTP_CUSTCAP_RSRVD0_V(v)                   BM_OCOTP_CUSTCAP_RSRVD0
+
+#define HW_OCOTP_LOCK                       HW(OCOTP_LOCK)
+#define HWA_OCOTP_LOCK                      (0x8002c000 + 0x120)
+#define HWT_OCOTP_LOCK                      HWIO_32_RW
+#define HWN_OCOTP_LOCK                      OCOTP_LOCK
+#define HWI_OCOTP_LOCK                      
+#define BP_OCOTP_LOCK_ROM7                  31
+#define BM_OCOTP_LOCK_ROM7                  0x80000000
+#define BF_OCOTP_LOCK_ROM7(v)               (((v) & 0x1) << 31)
+#define BFM_OCOTP_LOCK_ROM7(v)              BM_OCOTP_LOCK_ROM7
+#define BF_OCOTP_LOCK_ROM7_V(e)             BF_OCOTP_LOCK_ROM7(BV_OCOTP_LOCK_ROM7__##e)
+#define BFM_OCOTP_LOCK_ROM7_V(v)            BM_OCOTP_LOCK_ROM7
+#define BP_OCOTP_LOCK_ROM6                  30
+#define BM_OCOTP_LOCK_ROM6                  0x40000000
+#define BF_OCOTP_LOCK_ROM6(v)               (((v) & 0x1) << 30)
+#define BFM_OCOTP_LOCK_ROM6(v)              BM_OCOTP_LOCK_ROM6
+#define BF_OCOTP_LOCK_ROM6_V(e)             BF_OCOTP_LOCK_ROM6(BV_OCOTP_LOCK_ROM6__##e)
+#define BFM_OCOTP_LOCK_ROM6_V(v)            BM_OCOTP_LOCK_ROM6
+#define BP_OCOTP_LOCK_ROM5                  29
+#define BM_OCOTP_LOCK_ROM5                  0x20000000
+#define BF_OCOTP_LOCK_ROM5(v)               (((v) & 0x1) << 29)
+#define BFM_OCOTP_LOCK_ROM5(v)              BM_OCOTP_LOCK_ROM5
+#define BF_OCOTP_LOCK_ROM5_V(e)             BF_OCOTP_LOCK_ROM5(BV_OCOTP_LOCK_ROM5__##e)
+#define BFM_OCOTP_LOCK_ROM5_V(v)            BM_OCOTP_LOCK_ROM5
+#define BP_OCOTP_LOCK_ROM4                  28
+#define BM_OCOTP_LOCK_ROM4                  0x10000000
+#define BF_OCOTP_LOCK_ROM4(v)               (((v) & 0x1) << 28)
+#define BFM_OCOTP_LOCK_ROM4(v)              BM_OCOTP_LOCK_ROM4
+#define BF_OCOTP_LOCK_ROM4_V(e)             BF_OCOTP_LOCK_ROM4(BV_OCOTP_LOCK_ROM4__##e)
+#define BFM_OCOTP_LOCK_ROM4_V(v)            BM_OCOTP_LOCK_ROM4
+#define BP_OCOTP_LOCK_ROM3                  27
+#define BM_OCOTP_LOCK_ROM3                  0x8000000
+#define BF_OCOTP_LOCK_ROM3(v)               (((v) & 0x1) << 27)
+#define BFM_OCOTP_LOCK_ROM3(v)              BM_OCOTP_LOCK_ROM3
+#define BF_OCOTP_LOCK_ROM3_V(e)             BF_OCOTP_LOCK_ROM3(BV_OCOTP_LOCK_ROM3__##e)
+#define BFM_OCOTP_LOCK_ROM3_V(v)            BM_OCOTP_LOCK_ROM3
+#define BP_OCOTP_LOCK_ROM2                  26
+#define BM_OCOTP_LOCK_ROM2                  0x4000000
+#define BF_OCOTP_LOCK_ROM2(v)               (((v) & 0x1) << 26)
+#define BFM_OCOTP_LOCK_ROM2(v)              BM_OCOTP_LOCK_ROM2
+#define BF_OCOTP_LOCK_ROM2_V(e)             BF_OCOTP_LOCK_ROM2(BV_OCOTP_LOCK_ROM2__##e)
+#define BFM_OCOTP_LOCK_ROM2_V(v)            BM_OCOTP_LOCK_ROM2
+#define BP_OCOTP_LOCK_ROM1                  25
+#define BM_OCOTP_LOCK_ROM1                  0x2000000
+#define BF_OCOTP_LOCK_ROM1(v)               (((v) & 0x1) << 25)
+#define BFM_OCOTP_LOCK_ROM1(v)              BM_OCOTP_LOCK_ROM1
+#define BF_OCOTP_LOCK_ROM1_V(e)             BF_OCOTP_LOCK_ROM1(BV_OCOTP_LOCK_ROM1__##e)
+#define BFM_OCOTP_LOCK_ROM1_V(v)            BM_OCOTP_LOCK_ROM1
+#define BP_OCOTP_LOCK_ROM0                  24
+#define BM_OCOTP_LOCK_ROM0                  0x1000000
+#define BF_OCOTP_LOCK_ROM0(v)               (((v) & 0x1) << 24)
+#define BFM_OCOTP_LOCK_ROM0(v)              BM_OCOTP_LOCK_ROM0
+#define BF_OCOTP_LOCK_ROM0_V(e)             BF_OCOTP_LOCK_ROM0(BV_OCOTP_LOCK_ROM0__##e)
+#define BFM_OCOTP_LOCK_ROM0_V(v)            BM_OCOTP_LOCK_ROM0
+#define BP_OCOTP_LOCK_HWSW_SHADOW_ALT       23
+#define BM_OCOTP_LOCK_HWSW_SHADOW_ALT       0x800000
+#define BF_OCOTP_LOCK_HWSW_SHADOW_ALT(v)    (((v) & 0x1) << 23)
+#define BFM_OCOTP_LOCK_HWSW_SHADOW_ALT(v)   BM_OCOTP_LOCK_HWSW_SHADOW_ALT
+#define BF_OCOTP_LOCK_HWSW_SHADOW_ALT_V(e)  BF_OCOTP_LOCK_HWSW_SHADOW_ALT(BV_OCOTP_LOCK_HWSW_SHADOW_ALT__##e)
+#define BFM_OCOTP_LOCK_HWSW_SHADOW_ALT_V(v) BM_OCOTP_LOCK_HWSW_SHADOW_ALT
+#define BP_OCOTP_LOCK_CRYPTODCP_ALT         22
+#define BM_OCOTP_LOCK_CRYPTODCP_ALT         0x400000
+#define BF_OCOTP_LOCK_CRYPTODCP_ALT(v)      (((v) & 0x1) << 22)
+#define BFM_OCOTP_LOCK_CRYPTODCP_ALT(v)     BM_OCOTP_LOCK_CRYPTODCP_ALT
+#define BF_OCOTP_LOCK_CRYPTODCP_ALT_V(e)    BF_OCOTP_LOCK_CRYPTODCP_ALT(BV_OCOTP_LOCK_CRYPTODCP_ALT__##e)
+#define BFM_OCOTP_LOCK_CRYPTODCP_ALT_V(v)   BM_OCOTP_LOCK_CRYPTODCP_ALT
+#define BP_OCOTP_LOCK_CRYPTOKEY_ALT         21
+#define BM_OCOTP_LOCK_CRYPTOKEY_ALT         0x200000
+#define BF_OCOTP_LOCK_CRYPTOKEY_ALT(v)      (((v) & 0x1) << 21)
+#define BFM_OCOTP_LOCK_CRYPTOKEY_ALT(v)     BM_OCOTP_LOCK_CRYPTOKEY_ALT
+#define BF_OCOTP_LOCK_CRYPTOKEY_ALT_V(e)    BF_OCOTP_LOCK_CRYPTOKEY_ALT(BV_OCOTP_LOCK_CRYPTOKEY_ALT__##e)
+#define BFM_OCOTP_LOCK_CRYPTOKEY_ALT_V(v)   BM_OCOTP_LOCK_CRYPTOKEY_ALT
+#define BP_OCOTP_LOCK_PIN                   20
+#define BM_OCOTP_LOCK_PIN                   0x100000
+#define BF_OCOTP_LOCK_PIN(v)                (((v) & 0x1) << 20)
+#define BFM_OCOTP_LOCK_PIN(v)               BM_OCOTP_LOCK_PIN
+#define BF_OCOTP_LOCK_PIN_V(e)              BF_OCOTP_LOCK_PIN(BV_OCOTP_LOCK_PIN__##e)
+#define BFM_OCOTP_LOCK_PIN_V(v)             BM_OCOTP_LOCK_PIN
+#define BP_OCOTP_LOCK_OPS                   19
+#define BM_OCOTP_LOCK_OPS                   0x80000
+#define BF_OCOTP_LOCK_OPS(v)                (((v) & 0x1) << 19)
+#define BFM_OCOTP_LOCK_OPS(v)               BM_OCOTP_LOCK_OPS
+#define BF_OCOTP_LOCK_OPS_V(e)              BF_OCOTP_LOCK_OPS(BV_OCOTP_LOCK_OPS__##e)
+#define BFM_OCOTP_LOCK_OPS_V(v)             BM_OCOTP_LOCK_OPS
+#define BP_OCOTP_LOCK_UN2                   18
+#define BM_OCOTP_LOCK_UN2                   0x40000
+#define BF_OCOTP_LOCK_UN2(v)                (((v) & 0x1) << 18)
+#define BFM_OCOTP_LOCK_UN2(v)               BM_OCOTP_LOCK_UN2
+#define BF_OCOTP_LOCK_UN2_V(e)              BF_OCOTP_LOCK_UN2(BV_OCOTP_LOCK_UN2__##e)
+#define BFM_OCOTP_LOCK_UN2_V(v)             BM_OCOTP_LOCK_UN2
+#define BP_OCOTP_LOCK_UN1                   17
+#define BM_OCOTP_LOCK_UN1                   0x20000
+#define BF_OCOTP_LOCK_UN1(v)                (((v) & 0x1) << 17)
+#define BFM_OCOTP_LOCK_UN1(v)               BM_OCOTP_LOCK_UN1
+#define BF_OCOTP_LOCK_UN1_V(e)              BF_OCOTP_LOCK_UN1(BV_OCOTP_LOCK_UN1__##e)
+#define BFM_OCOTP_LOCK_UN1_V(v)             BM_OCOTP_LOCK_UN1
+#define BP_OCOTP_LOCK_UN0                   16
+#define BM_OCOTP_LOCK_UN0                   0x10000
+#define BF_OCOTP_LOCK_UN0(v)                (((v) & 0x1) << 16)
+#define BFM_OCOTP_LOCK_UN0(v)               BM_OCOTP_LOCK_UN0
+#define BF_OCOTP_LOCK_UN0_V(e)              BF_OCOTP_LOCK_UN0(BV_OCOTP_LOCK_UN0__##e)
+#define BFM_OCOTP_LOCK_UN0_V(v)             BM_OCOTP_LOCK_UN0
+#define BP_OCOTP_LOCK_UNALLOCATED           11
+#define BM_OCOTP_LOCK_UNALLOCATED           0xf800
+#define BF_OCOTP_LOCK_UNALLOCATED(v)        (((v) & 0x1f) << 11)
+#define BFM_OCOTP_LOCK_UNALLOCATED(v)       BM_OCOTP_LOCK_UNALLOCATED
+#define BF_OCOTP_LOCK_UNALLOCATED_V(e)      BF_OCOTP_LOCK_UNALLOCATED(BV_OCOTP_LOCK_UNALLOCATED__##e)
+#define BFM_OCOTP_LOCK_UNALLOCATED_V(v)     BM_OCOTP_LOCK_UNALLOCATED
+#define BP_OCOTP_LOCK_ROM_SHADOW            10
+#define BM_OCOTP_LOCK_ROM_SHADOW            0x400
+#define BF_OCOTP_LOCK_ROM_SHADOW(v)         (((v) & 0x1) << 10)
+#define BFM_OCOTP_LOCK_ROM_SHADOW(v)        BM_OCOTP_LOCK_ROM_SHADOW
+#define BF_OCOTP_LOCK_ROM_SHADOW_V(e)       BF_OCOTP_LOCK_ROM_SHADOW(BV_OCOTP_LOCK_ROM_SHADOW__##e)
+#define BFM_OCOTP_LOCK_ROM_SHADOW_V(v)      BM_OCOTP_LOCK_ROM_SHADOW
+#define BP_OCOTP_LOCK_CUSTCAP               9
+#define BM_OCOTP_LOCK_CUSTCAP               0x200
+#define BF_OCOTP_LOCK_CUSTCAP(v)            (((v) & 0x1) << 9)
+#define BFM_OCOTP_LOCK_CUSTCAP(v)           BM_OCOTP_LOCK_CUSTCAP
+#define BF_OCOTP_LOCK_CUSTCAP_V(e)          BF_OCOTP_LOCK_CUSTCAP(BV_OCOTP_LOCK_CUSTCAP__##e)
+#define BFM_OCOTP_LOCK_CUSTCAP_V(v)         BM_OCOTP_LOCK_CUSTCAP
+#define BP_OCOTP_LOCK_HWSW                  8
+#define BM_OCOTP_LOCK_HWSW                  0x100
+#define BF_OCOTP_LOCK_HWSW(v)               (((v) & 0x1) << 8)
+#define BFM_OCOTP_LOCK_HWSW(v)              BM_OCOTP_LOCK_HWSW
+#define BF_OCOTP_LOCK_HWSW_V(e)             BF_OCOTP_LOCK_HWSW(BV_OCOTP_LOCK_HWSW__##e)
+#define BFM_OCOTP_LOCK_HWSW_V(v)            BM_OCOTP_LOCK_HWSW
+#define BP_OCOTP_LOCK_CUSTCAP_SHADOW        7
+#define BM_OCOTP_LOCK_CUSTCAP_SHADOW        0x80
+#define BF_OCOTP_LOCK_CUSTCAP_SHADOW(v)     (((v) & 0x1) << 7)
+#define BFM_OCOTP_LOCK_CUSTCAP_SHADOW(v)    BM_OCOTP_LOCK_CUSTCAP_SHADOW
+#define BF_OCOTP_LOCK_CUSTCAP_SHADOW_V(e)   BF_OCOTP_LOCK_CUSTCAP_SHADOW(BV_OCOTP_LOCK_CUSTCAP_SHADOW__##e)
+#define BFM_OCOTP_LOCK_CUSTCAP_SHADOW_V(v)  BM_OCOTP_LOCK_CUSTCAP_SHADOW
+#define BP_OCOTP_LOCK_HWSW_SHADOW           6
+#define BM_OCOTP_LOCK_HWSW_SHADOW           0x40
+#define BF_OCOTP_LOCK_HWSW_SHADOW(v)        (((v) & 0x1) << 6)
+#define BFM_OCOTP_LOCK_HWSW_SHADOW(v)       BM_OCOTP_LOCK_HWSW_SHADOW
+#define BF_OCOTP_LOCK_HWSW_SHADOW_V(e)      BF_OCOTP_LOCK_HWSW_SHADOW(BV_OCOTP_LOCK_HWSW_SHADOW__##e)
+#define BFM_OCOTP_LOCK_HWSW_SHADOW_V(v)     BM_OCOTP_LOCK_HWSW_SHADOW
+#define BP_OCOTP_LOCK_CRYPTODCP             5
+#define BM_OCOTP_LOCK_CRYPTODCP             0x20
+#define BF_OCOTP_LOCK_CRYPTODCP(v)          (((v) & 0x1) << 5)
+#define BFM_OCOTP_LOCK_CRYPTODCP(v)         BM_OCOTP_LOCK_CRYPTODCP
+#define BF_OCOTP_LOCK_CRYPTODCP_V(e)        BF_OCOTP_LOCK_CRYPTODCP(BV_OCOTP_LOCK_CRYPTODCP__##e)
+#define BFM_OCOTP_LOCK_CRYPTODCP_V(v)       BM_OCOTP_LOCK_CRYPTODCP
+#define BP_OCOTP_LOCK_CRYPTOKEY             4
+#define BM_OCOTP_LOCK_CRYPTOKEY             0x10
+#define BF_OCOTP_LOCK_CRYPTOKEY(v)          (((v) & 0x1) << 4)
+#define BFM_OCOTP_LOCK_CRYPTOKEY(v)         BM_OCOTP_LOCK_CRYPTOKEY
+#define BF_OCOTP_LOCK_CRYPTOKEY_V(e)        BF_OCOTP_LOCK_CRYPTOKEY(BV_OCOTP_LOCK_CRYPTOKEY__##e)
+#define BFM_OCOTP_LOCK_CRYPTOKEY_V(v)       BM_OCOTP_LOCK_CRYPTOKEY
+#define BP_OCOTP_LOCK_CUST3                 3
+#define BM_OCOTP_LOCK_CUST3                 0x8
+#define BF_OCOTP_LOCK_CUST3(v)              (((v) & 0x1) << 3)
+#define BFM_OCOTP_LOCK_CUST3(v)             BM_OCOTP_LOCK_CUST3
+#define BF_OCOTP_LOCK_CUST3_V(e)            BF_OCOTP_LOCK_CUST3(BV_OCOTP_LOCK_CUST3__##e)
+#define BFM_OCOTP_LOCK_CUST3_V(v)           BM_OCOTP_LOCK_CUST3
+#define BP_OCOTP_LOCK_CUST2                 2
+#define BM_OCOTP_LOCK_CUST2                 0x4
+#define BF_OCOTP_LOCK_CUST2(v)              (((v) & 0x1) << 2)
+#define BFM_OCOTP_LOCK_CUST2(v)             BM_OCOTP_LOCK_CUST2
+#define BF_OCOTP_LOCK_CUST2_V(e)            BF_OCOTP_LOCK_CUST2(BV_OCOTP_LOCK_CUST2__##e)
+#define BFM_OCOTP_LOCK_CUST2_V(v)           BM_OCOTP_LOCK_CUST2
+#define BP_OCOTP_LOCK_CUST1                 1
+#define BM_OCOTP_LOCK_CUST1                 0x2
+#define BF_OCOTP_LOCK_CUST1(v)              (((v) & 0x1) << 1)
+#define BFM_OCOTP_LOCK_CUST1(v)             BM_OCOTP_LOCK_CUST1
+#define BF_OCOTP_LOCK_CUST1_V(e)            BF_OCOTP_LOCK_CUST1(BV_OCOTP_LOCK_CUST1__##e)
+#define BFM_OCOTP_LOCK_CUST1_V(v)           BM_OCOTP_LOCK_CUST1
+#define BP_OCOTP_LOCK_CUST0                 0
+#define BM_OCOTP_LOCK_CUST0                 0x1
+#define BF_OCOTP_LOCK_CUST0(v)              (((v) & 0x1) << 0)
+#define BFM_OCOTP_LOCK_CUST0(v)             BM_OCOTP_LOCK_CUST0
+#define BF_OCOTP_LOCK_CUST0_V(e)            BF_OCOTP_LOCK_CUST0(BV_OCOTP_LOCK_CUST0__##e)
+#define BFM_OCOTP_LOCK_CUST0_V(v)           BM_OCOTP_LOCK_CUST0
+
+#define HW_OCOTP_OPSn(_n1)          HW(OCOTP_OPSn(_n1))
+#define HWA_OCOTP_OPSn(_n1)         (0x8002c000 + 0x130 + (_n1) * 0x10)
+#define HWT_OCOTP_OPSn(_n1)         HWIO_32_RW
+#define HWN_OCOTP_OPSn(_n1)         OCOTP_OPSn
+#define HWI_OCOTP_OPSn(_n1)         (_n1)
+#define BP_OCOTP_OPSn_BITS          0
+#define BM_OCOTP_OPSn_BITS          0xffffffff
+#define BF_OCOTP_OPSn_BITS(v)       (((v) & 0xffffffff) << 0)
+#define BFM_OCOTP_OPSn_BITS(v)      BM_OCOTP_OPSn_BITS
+#define BF_OCOTP_OPSn_BITS_V(e)     BF_OCOTP_OPSn_BITS(BV_OCOTP_OPSn_BITS__##e)
+#define BFM_OCOTP_OPSn_BITS_V(v)    BM_OCOTP_OPSn_BITS
+
+#define HW_OCOTP_UNn(_n1)       HW(OCOTP_UNn(_n1))
+#define HWA_OCOTP_UNn(_n1)      (0x8002c000 + 0x170 + (_n1) * 0x10)
+#define HWT_OCOTP_UNn(_n1)      HWIO_32_RW
+#define HWN_OCOTP_UNn(_n1)      OCOTP_UNn
+#define HWI_OCOTP_UNn(_n1)      (_n1)
+#define BP_OCOTP_UNn_BITS       0
+#define BM_OCOTP_UNn_BITS       0xffffffff
+#define BF_OCOTP_UNn_BITS(v)    (((v) & 0xffffffff) << 0)
+#define BFM_OCOTP_UNn_BITS(v)   BM_OCOTP_UNn_BITS
+#define BF_OCOTP_UNn_BITS_V(e)  BF_OCOTP_UNn_BITS(BV_OCOTP_UNn_BITS__##e)
+#define BFM_OCOTP_UNn_BITS_V(v) BM_OCOTP_UNn_BITS
+
+#define HW_OCOTP_ROMn(_n1)          HW(OCOTP_ROMn(_n1))
+#define HWA_OCOTP_ROMn(_n1)         (0x8002c000 + 0x1a0 + (_n1) * 0x10)
+#define HWT_OCOTP_ROMn(_n1)         HWIO_32_RW
+#define HWN_OCOTP_ROMn(_n1)         OCOTP_ROMn
+#define HWI_OCOTP_ROMn(_n1)         (_n1)
+#define BP_OCOTP_ROMn_BITS          0
+#define BM_OCOTP_ROMn_BITS          0xffffffff
+#define BF_OCOTP_ROMn_BITS(v)       (((v) & 0xffffffff) << 0)
+#define BFM_OCOTP_ROMn_BITS(v)      BM_OCOTP_ROMn_BITS
+#define BF_OCOTP_ROMn_BITS_V(e)     BF_OCOTP_ROMn_BITS(BV_OCOTP_ROMn_BITS__##e)
+#define BFM_OCOTP_ROMn_BITS_V(v)    BM_OCOTP_ROMn_BITS
+
+#define HW_OCOTP_VERSION                HW(OCOTP_VERSION)
+#define HWA_OCOTP_VERSION               (0x8002c000 + 0x220)
+#define HWT_OCOTP_VERSION               HWIO_32_RW
+#define HWN_OCOTP_VERSION               OCOTP_VERSION
+#define HWI_OCOTP_VERSION               
+#define BP_OCOTP_VERSION_MAJOR          24
+#define BM_OCOTP_VERSION_MAJOR          0xff000000
+#define BF_OCOTP_VERSION_MAJOR(v)       (((v) & 0xff) << 24)
+#define BFM_OCOTP_VERSION_MAJOR(v)      BM_OCOTP_VERSION_MAJOR
+#define BF_OCOTP_VERSION_MAJOR_V(e)     BF_OCOTP_VERSION_MAJOR(BV_OCOTP_VERSION_MAJOR__##e)
+#define BFM_OCOTP_VERSION_MAJOR_V(v)    BM_OCOTP_VERSION_MAJOR
+#define BP_OCOTP_VERSION_MINOR          16
+#define BM_OCOTP_VERSION_MINOR          0xff0000
+#define BF_OCOTP_VERSION_MINOR(v)       (((v) & 0xff) << 16)
+#define BFM_OCOTP_VERSION_MINOR(v)      BM_OCOTP_VERSION_MINOR
+#define BF_OCOTP_VERSION_MINOR_V(e)     BF_OCOTP_VERSION_MINOR(BV_OCOTP_VERSION_MINOR__##e)
+#define BFM_OCOTP_VERSION_MINOR_V(v)    BM_OCOTP_VERSION_MINOR
+#define BP_OCOTP_VERSION_STEP           0
+#define BM_OCOTP_VERSION_STEP           0xffff
+#define BF_OCOTP_VERSION_STEP(v)        (((v) & 0xffff) << 0)
+#define BFM_OCOTP_VERSION_STEP(v)       BM_OCOTP_VERSION_STEP
+#define BF_OCOTP_VERSION_STEP_V(e)      BF_OCOTP_VERSION_STEP(BV_OCOTP_VERSION_STEP__##e)
+#define BFM_OCOTP_VERSION_STEP_V(v)     BM_OCOTP_VERSION_STEP
+
+#endif /* __HEADERGEN_IMX233_OCOTP_H__*/
diff --git a/firmware/target/arm/imx233/regs/imx233/pinctrl.h b/firmware/target/arm/imx233/regs/imx233/pinctrl.h
new file mode 100644
index 0000000000..59a0d0cd39
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/imx233/pinctrl.h
@@ -0,0 +1,411 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * imx233 version: 2.4.0
+ * imx233 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_IMX233_PINCTRL_H__
+#define __HEADERGEN_IMX233_PINCTRL_H__
+
+#define HW_PINCTRL_CTRL                 HW(PINCTRL_CTRL)
+#define HWA_PINCTRL_CTRL                (0x80018000 + 0x0)
+#define HWT_PINCTRL_CTRL                HWIO_32_RW
+#define HWN_PINCTRL_CTRL                PINCTRL_CTRL
+#define HWI_PINCTRL_CTRL                
+#define HW_PINCTRL_CTRL_SET             HW(PINCTRL_CTRL_SET)
+#define HWA_PINCTRL_CTRL_SET            (HWA_PINCTRL_CTRL + 0x4)
+#define HWT_PINCTRL_CTRL_SET            HWIO_32_WO
+#define HWN_PINCTRL_CTRL_SET            PINCTRL_CTRL
+#define HWI_PINCTRL_CTRL_SET            
+#define HW_PINCTRL_CTRL_CLR             HW(PINCTRL_CTRL_CLR)
+#define HWA_PINCTRL_CTRL_CLR            (HWA_PINCTRL_CTRL + 0x8)
+#define HWT_PINCTRL_CTRL_CLR            HWIO_32_WO
+#define HWN_PINCTRL_CTRL_CLR            PINCTRL_CTRL
+#define HWI_PINCTRL_CTRL_CLR            
+#define HW_PINCTRL_CTRL_TOG             HW(PINCTRL_CTRL_TOG)
+#define HWA_PINCTRL_CTRL_TOG            (HWA_PINCTRL_CTRL + 0xc)
+#define HWT_PINCTRL_CTRL_TOG            HWIO_32_WO
+#define HWN_PINCTRL_CTRL_TOG            PINCTRL_CTRL
+#define HWI_PINCTRL_CTRL_TOG            
+#define BP_PINCTRL_CTRL_SFTRST          31
+#define BM_PINCTRL_CTRL_SFTRST          0x80000000
+#define BF_PINCTRL_CTRL_SFTRST(v)       (((v) & 0x1) << 31)
+#define BFM_PINCTRL_CTRL_SFTRST(v)      BM_PINCTRL_CTRL_SFTRST
+#define BF_PINCTRL_CTRL_SFTRST_V(e)     BF_PINCTRL_CTRL_SFTRST(BV_PINCTRL_CTRL_SFTRST__##e)
+#define BFM_PINCTRL_CTRL_SFTRST_V(v)    BM_PINCTRL_CTRL_SFTRST
+#define BP_PINCTRL_CTRL_CLKGATE         30
+#define BM_PINCTRL_CTRL_CLKGATE         0x40000000
+#define BF_PINCTRL_CTRL_CLKGATE(v)      (((v) & 0x1) << 30)
+#define BFM_PINCTRL_CTRL_CLKGATE(v)     BM_PINCTRL_CTRL_CLKGATE
+#define BF_PINCTRL_CTRL_CLKGATE_V(e)    BF_PINCTRL_CTRL_CLKGATE(BV_PINCTRL_CTRL_CLKGATE__##e)
+#define BFM_PINCTRL_CTRL_CLKGATE_V(v)   BM_PINCTRL_CTRL_CLKGATE
+#define BP_PINCTRL_CTRL_RSRVD2          28
+#define BM_PINCTRL_CTRL_RSRVD2          0x30000000
+#define BF_PINCTRL_CTRL_RSRVD2(v)       (((v) & 0x3) << 28)
+#define BFM_PINCTRL_CTRL_RSRVD2(v)      BM_PINCTRL_CTRL_RSRVD2
+#define BF_PINCTRL_CTRL_RSRVD2_V(e)     BF_PINCTRL_CTRL_RSRVD2(BV_PINCTRL_CTRL_RSRVD2__##e)
+#define BFM_PINCTRL_CTRL_RSRVD2_V(v)    BM_PINCTRL_CTRL_RSRVD2
+#define BP_PINCTRL_CTRL_PRESENT3        27
+#define BM_PINCTRL_CTRL_PRESENT3        0x8000000
+#define BF_PINCTRL_CTRL_PRESENT3(v)     (((v) & 0x1) << 27)
+#define BFM_PINCTRL_CTRL_PRESENT3(v)    BM_PINCTRL_CTRL_PRESENT3
+#define BF_PINCTRL_CTRL_PRESENT3_V(e)   BF_PINCTRL_CTRL_PRESENT3(BV_PINCTRL_CTRL_PRESENT3__##e)
+#define BFM_PINCTRL_CTRL_PRESENT3_V(v)  BM_PINCTRL_CTRL_PRESENT3
+#define BP_PINCTRL_CTRL_PRESENT2        26
+#define BM_PINCTRL_CTRL_PRESENT2        0x4000000
+#define BF_PINCTRL_CTRL_PRESENT2(v)     (((v) & 0x1) << 26)
+#define BFM_PINCTRL_CTRL_PRESENT2(v)    BM_PINCTRL_CTRL_PRESENT2
+#define BF_PINCTRL_CTRL_PRESENT2_V(e)   BF_PINCTRL_CTRL_PRESENT2(BV_PINCTRL_CTRL_PRESENT2__##e)
+#define BFM_PINCTRL_CTRL_PRESENT2_V(v)  BM_PINCTRL_CTRL_PRESENT2
+#define BP_PINCTRL_CTRL_PRESENT1        25
+#define BM_PINCTRL_CTRL_PRESENT1        0x2000000
+#define BF_PINCTRL_CTRL_PRESENT1(v)     (((v) & 0x1) << 25)
+#define BFM_PINCTRL_CTRL_PRESENT1(v)    BM_PINCTRL_CTRL_PRESENT1
+#define BF_PINCTRL_CTRL_PRESENT1_V(e)   BF_PINCTRL_CTRL_PRESENT1(BV_PINCTRL_CTRL_PRESENT1__##e)
+#define BFM_PINCTRL_CTRL_PRESENT1_V(v)  BM_PINCTRL_CTRL_PRESENT1
+#define BP_PINCTRL_CTRL_PRESENT0        24
+#define BM_PINCTRL_CTRL_PRESENT0        0x1000000
+#define BF_PINCTRL_CTRL_PRESENT0(v)     (((v) & 0x1) << 24)
+#define BFM_PINCTRL_CTRL_PRESENT0(v)    BM_PINCTRL_CTRL_PRESENT0
+#define BF_PINCTRL_CTRL_PRESENT0_V(e)   BF_PINCTRL_CTRL_PRESENT0(BV_PINCTRL_CTRL_PRESENT0__##e)
+#define BFM_PINCTRL_CTRL_PRESENT0_V(v)  BM_PINCTRL_CTRL_PRESENT0
+#define BP_PINCTRL_CTRL_RSRVD1          3
+#define BM_PINCTRL_CTRL_RSRVD1          0xfffff8
+#define BF_PINCTRL_CTRL_RSRVD1(v)       (((v) & 0x1fffff) << 3)
+#define BFM_PINCTRL_CTRL_RSRVD1(v)      BM_PINCTRL_CTRL_RSRVD1
+#define BF_PINCTRL_CTRL_RSRVD1_V(e)     BF_PINCTRL_CTRL_RSRVD1(BV_PINCTRL_CTRL_RSRVD1__##e)
+#define BFM_PINCTRL_CTRL_RSRVD1_V(v)    BM_PINCTRL_CTRL_RSRVD1
+#define BP_PINCTRL_CTRL_IRQOUT2         2
+#define BM_PINCTRL_CTRL_IRQOUT2         0x4
+#define BF_PINCTRL_CTRL_IRQOUT2(v)      (((v) & 0x1) << 2)
+#define BFM_PINCTRL_CTRL_IRQOUT2(v)     BM_PINCTRL_CTRL_IRQOUT2
+#define BF_PINCTRL_CTRL_IRQOUT2_V(e)    BF_PINCTRL_CTRL_IRQOUT2(BV_PINCTRL_CTRL_IRQOUT2__##e)
+#define BFM_PINCTRL_CTRL_IRQOUT2_V(v)   BM_PINCTRL_CTRL_IRQOUT2
+#define BP_PINCTRL_CTRL_IRQOUT1         1
+#define BM_PINCTRL_CTRL_IRQOUT1         0x2
+#define BF_PINCTRL_CTRL_IRQOUT1(v)      (((v) & 0x1) << 1)
+#define BFM_PINCTRL_CTRL_IRQOUT1(v)     BM_PINCTRL_CTRL_IRQOUT1
+#define BF_PINCTRL_CTRL_IRQOUT1_V(e)    BF_PINCTRL_CTRL_IRQOUT1(BV_PINCTRL_CTRL_IRQOUT1__##e)
+#define BFM_PINCTRL_CTRL_IRQOUT1_V(v)   BM_PINCTRL_CTRL_IRQOUT1
+#define BP_PINCTRL_CTRL_IRQOUT0         0
+#define BM_PINCTRL_CTRL_IRQOUT0         0x1
+#define BF_PINCTRL_CTRL_IRQOUT0(v)      (((v) & 0x1) << 0)
+#define BFM_PINCTRL_CTRL_IRQOUT0(v)     BM_PINCTRL_CTRL_IRQOUT0
+#define BF_PINCTRL_CTRL_IRQOUT0_V(e)    BF_PINCTRL_CTRL_IRQOUT0(BV_PINCTRL_CTRL_IRQOUT0__##e)
+#define BFM_PINCTRL_CTRL_IRQOUT0_V(v)   BM_PINCTRL_CTRL_IRQOUT0
+
+#define HW_PINCTRL_MUXSELn(_n1)         HW(PINCTRL_MUXSELn(_n1))
+#define HWA_PINCTRL_MUXSELn(_n1)        (0x80018000 + 0x100 + (_n1) * 0x10)
+#define HWT_PINCTRL_MUXSELn(_n1)        HWIO_32_RW
+#define HWN_PINCTRL_MUXSELn(_n1)        PINCTRL_MUXSELn
+#define HWI_PINCTRL_MUXSELn(_n1)        (_n1)
+#define HW_PINCTRL_MUXSELn_SET(_n1)     HW(PINCTRL_MUXSELn_SET(_n1))
+#define HWA_PINCTRL_MUXSELn_SET(_n1)    (HWA_PINCTRL_MUXSELn(_n1) + 0x4)
+#define HWT_PINCTRL_MUXSELn_SET(_n1)    HWIO_32_WO
+#define HWN_PINCTRL_MUXSELn_SET(_n1)    PINCTRL_MUXSELn
+#define HWI_PINCTRL_MUXSELn_SET(_n1)    (_n1)
+#define HW_PINCTRL_MUXSELn_CLR(_n1)     HW(PINCTRL_MUXSELn_CLR(_n1))
+#define HWA_PINCTRL_MUXSELn_CLR(_n1)    (HWA_PINCTRL_MUXSELn(_n1) + 0x8)
+#define HWT_PINCTRL_MUXSELn_CLR(_n1)    HWIO_32_WO
+#define HWN_PINCTRL_MUXSELn_CLR(_n1)    PINCTRL_MUXSELn
+#define HWI_PINCTRL_MUXSELn_CLR(_n1)    (_n1)
+#define HW_PINCTRL_MUXSELn_TOG(_n1)     HW(PINCTRL_MUXSELn_TOG(_n1))
+#define HWA_PINCTRL_MUXSELn_TOG(_n1)    (HWA_PINCTRL_MUXSELn(_n1) + 0xc)
+#define HWT_PINCTRL_MUXSELn_TOG(_n1)    HWIO_32_WO
+#define HWN_PINCTRL_MUXSELn_TOG(_n1)    PINCTRL_MUXSELn
+#define HWI_PINCTRL_MUXSELn_TOG(_n1)    (_n1)
+#define BP_PINCTRL_MUXSELn_BITS         0
+#define BM_PINCTRL_MUXSELn_BITS         0xffffffff
+#define BF_PINCTRL_MUXSELn_BITS(v)      (((v) & 0xffffffff) << 0)
+#define BFM_PINCTRL_MUXSELn_BITS(v)     BM_PINCTRL_MUXSELn_BITS
+#define BF_PINCTRL_MUXSELn_BITS_V(e)    BF_PINCTRL_MUXSELn_BITS(BV_PINCTRL_MUXSELn_BITS__##e)
+#define BFM_PINCTRL_MUXSELn_BITS_V(v)   BM_PINCTRL_MUXSELn_BITS
+
+#define HW_PINCTRL_DRIVEn(_n1)          HW(PINCTRL_DRIVEn(_n1))
+#define HWA_PINCTRL_DRIVEn(_n1)         (0x80018000 + 0x200 + (_n1) * 0x10)
+#define HWT_PINCTRL_DRIVEn(_n1)         HWIO_32_RW
+#define HWN_PINCTRL_DRIVEn(_n1)         PINCTRL_DRIVEn
+#define HWI_PINCTRL_DRIVEn(_n1)         (_n1)
+#define HW_PINCTRL_DRIVEn_SET(_n1)      HW(PINCTRL_DRIVEn_SET(_n1))
+#define HWA_PINCTRL_DRIVEn_SET(_n1)     (HWA_PINCTRL_DRIVEn(_n1) + 0x4)
+#define HWT_PINCTRL_DRIVEn_SET(_n1)     HWIO_32_WO
+#define HWN_PINCTRL_DRIVEn_SET(_n1)     PINCTRL_DRIVEn
+#define HWI_PINCTRL_DRIVEn_SET(_n1)     (_n1)
+#define HW_PINCTRL_DRIVEn_CLR(_n1)      HW(PINCTRL_DRIVEn_CLR(_n1))
+#define HWA_PINCTRL_DRIVEn_CLR(_n1)     (HWA_PINCTRL_DRIVEn(_n1) + 0x8)
+#define HWT_PINCTRL_DRIVEn_CLR(_n1)     HWIO_32_WO
+#define HWN_PINCTRL_DRIVEn_CLR(_n1)     PINCTRL_DRIVEn
+#define HWI_PINCTRL_DRIVEn_CLR(_n1)     (_n1)
+#define HW_PINCTRL_DRIVEn_TOG(_n1)      HW(PINCTRL_DRIVEn_TOG(_n1))
+#define HWA_PINCTRL_DRIVEn_TOG(_n1)     (HWA_PINCTRL_DRIVEn(_n1) + 0xc)
+#define HWT_PINCTRL_DRIVEn_TOG(_n1)     HWIO_32_WO
+#define HWN_PINCTRL_DRIVEn_TOG(_n1)     PINCTRL_DRIVEn
+#define HWI_PINCTRL_DRIVEn_TOG(_n1)     (_n1)
+#define BP_PINCTRL_DRIVEn_BITS          0
+#define BM_PINCTRL_DRIVEn_BITS          0xffffffff
+#define BF_PINCTRL_DRIVEn_BITS(v)       (((v) & 0xffffffff) << 0)
+#define BFM_PINCTRL_DRIVEn_BITS(v)      BM_PINCTRL_DRIVEn_BITS
+#define BF_PINCTRL_DRIVEn_BITS_V(e)     BF_PINCTRL_DRIVEn_BITS(BV_PINCTRL_DRIVEn_BITS__##e)
+#define BFM_PINCTRL_DRIVEn_BITS_V(v)    BM_PINCTRL_DRIVEn_BITS
+
+#define HW_PINCTRL_PULLn(_n1)       HW(PINCTRL_PULLn(_n1))
+#define HWA_PINCTRL_PULLn(_n1)      (0x80018000 + 0x400 + (_n1) * 0x10)
+#define HWT_PINCTRL_PULLn(_n1)      HWIO_32_RW
+#define HWN_PINCTRL_PULLn(_n1)      PINCTRL_PULLn
+#define HWI_PINCTRL_PULLn(_n1)      (_n1)
+#define HW_PINCTRL_PULLn_SET(_n1)   HW(PINCTRL_PULLn_SET(_n1))
+#define HWA_PINCTRL_PULLn_SET(_n1)  (HWA_PINCTRL_PULLn(_n1) + 0x4)
+#define HWT_PINCTRL_PULLn_SET(_n1)  HWIO_32_WO
+#define HWN_PINCTRL_PULLn_SET(_n1)  PINCTRL_PULLn
+#define HWI_PINCTRL_PULLn_SET(_n1)  (_n1)
+#define HW_PINCTRL_PULLn_CLR(_n1)   HW(PINCTRL_PULLn_CLR(_n1))
+#define HWA_PINCTRL_PULLn_CLR(_n1)  (HWA_PINCTRL_PULLn(_n1) + 0x8)
+#define HWT_PINCTRL_PULLn_CLR(_n1)  HWIO_32_WO
+#define HWN_PINCTRL_PULLn_CLR(_n1)  PINCTRL_PULLn
+#define HWI_PINCTRL_PULLn_CLR(_n1)  (_n1)
+#define HW_PINCTRL_PULLn_TOG(_n1)   HW(PINCTRL_PULLn_TOG(_n1))
+#define HWA_PINCTRL_PULLn_TOG(_n1)  (HWA_PINCTRL_PULLn(_n1) + 0xc)
+#define HWT_PINCTRL_PULLn_TOG(_n1)  HWIO_32_WO
+#define HWN_PINCTRL_PULLn_TOG(_n1)  PINCTRL_PULLn
+#define HWI_PINCTRL_PULLn_TOG(_n1)  (_n1)
+#define BP_PINCTRL_PULLn_BITS       0
+#define BM_PINCTRL_PULLn_BITS       0xffffffff
+#define BF_PINCTRL_PULLn_BITS(v)    (((v) & 0xffffffff) << 0)
+#define BFM_PINCTRL_PULLn_BITS(v)   BM_PINCTRL_PULLn_BITS
+#define BF_PINCTRL_PULLn_BITS_V(e)  BF_PINCTRL_PULLn_BITS(BV_PINCTRL_PULLn_BITS__##e)
+#define BFM_PINCTRL_PULLn_BITS_V(v) BM_PINCTRL_PULLn_BITS
+
+#define HW_PINCTRL_DOUTn(_n1)       HW(PINCTRL_DOUTn(_n1))
+#define HWA_PINCTRL_DOUTn(_n1)      (0x80018000 + 0x500 + (_n1) * 0x10)
+#define HWT_PINCTRL_DOUTn(_n1)      HWIO_32_RW
+#define HWN_PINCTRL_DOUTn(_n1)      PINCTRL_DOUTn
+#define HWI_PINCTRL_DOUTn(_n1)      (_n1)
+#define HW_PINCTRL_DOUTn_SET(_n1)   HW(PINCTRL_DOUTn_SET(_n1))
+#define HWA_PINCTRL_DOUTn_SET(_n1)  (HWA_PINCTRL_DOUTn(_n1) + 0x4)
+#define HWT_PINCTRL_DOUTn_SET(_n1)  HWIO_32_WO
+#define HWN_PINCTRL_DOUTn_SET(_n1)  PINCTRL_DOUTn
+#define HWI_PINCTRL_DOUTn_SET(_n1)  (_n1)
+#define HW_PINCTRL_DOUTn_CLR(_n1)   HW(PINCTRL_DOUTn_CLR(_n1))
+#define HWA_PINCTRL_DOUTn_CLR(_n1)  (HWA_PINCTRL_DOUTn(_n1) + 0x8)
+#define HWT_PINCTRL_DOUTn_CLR(_n1)  HWIO_32_WO
+#define HWN_PINCTRL_DOUTn_CLR(_n1)  PINCTRL_DOUTn
+#define HWI_PINCTRL_DOUTn_CLR(_n1)  (_n1)
+#define HW_PINCTRL_DOUTn_TOG(_n1)   HW(PINCTRL_DOUTn_TOG(_n1))
+#define HWA_PINCTRL_DOUTn_TOG(_n1)  (HWA_PINCTRL_DOUTn(_n1) + 0xc)
+#define HWT_PINCTRL_DOUTn_TOG(_n1)  HWIO_32_WO
+#define HWN_PINCTRL_DOUTn_TOG(_n1)  PINCTRL_DOUTn
+#define HWI_PINCTRL_DOUTn_TOG(_n1)  (_n1)
+#define BP_PINCTRL_DOUTn_BITS       0
+#define BM_PINCTRL_DOUTn_BITS       0xffffffff
+#define BF_PINCTRL_DOUTn_BITS(v)    (((v) & 0xffffffff) << 0)
+#define BFM_PINCTRL_DOUTn_BITS(v)   BM_PINCTRL_DOUTn_BITS
+#define BF_PINCTRL_DOUTn_BITS_V(e)  BF_PINCTRL_DOUTn_BITS(BV_PINCTRL_DOUTn_BITS__##e)
+#define BFM_PINCTRL_DOUTn_BITS_V(v) BM_PINCTRL_DOUTn_BITS
+
+#define HW_PINCTRL_DINn(_n1)        HW(PINCTRL_DINn(_n1))
+#define HWA_PINCTRL_DINn(_n1)       (0x80018000 + 0x600 + (_n1) * 0x10)
+#define HWT_PINCTRL_DINn(_n1)       HWIO_32_RW
+#define HWN_PINCTRL_DINn(_n1)       PINCTRL_DINn
+#define HWI_PINCTRL_DINn(_n1)       (_n1)
+#define HW_PINCTRL_DINn_SET(_n1)    HW(PINCTRL_DINn_SET(_n1))
+#define HWA_PINCTRL_DINn_SET(_n1)   (HWA_PINCTRL_DINn(_n1) + 0x4)
+#define HWT_PINCTRL_DINn_SET(_n1)   HWIO_32_WO
+#define HWN_PINCTRL_DINn_SET(_n1)   PINCTRL_DINn
+#define HWI_PINCTRL_DINn_SET(_n1)   (_n1)
+#define HW_PINCTRL_DINn_CLR(_n1)    HW(PINCTRL_DINn_CLR(_n1))
+#define HWA_PINCTRL_DINn_CLR(_n1)   (HWA_PINCTRL_DINn(_n1) + 0x8)
+#define HWT_PINCTRL_DINn_CLR(_n1)   HWIO_32_WO
+#define HWN_PINCTRL_DINn_CLR(_n1)   PINCTRL_DINn
+#define HWI_PINCTRL_DINn_CLR(_n1)   (_n1)
+#define HW_PINCTRL_DINn_TOG(_n1)    HW(PINCTRL_DINn_TOG(_n1))
+#define HWA_PINCTRL_DINn_TOG(_n1)   (HWA_PINCTRL_DINn(_n1) + 0xc)
+#define HWT_PINCTRL_DINn_TOG(_n1)   HWIO_32_WO
+#define HWN_PINCTRL_DINn_TOG(_n1)   PINCTRL_DINn
+#define HWI_PINCTRL_DINn_TOG(_n1)   (_n1)
+#define BP_PINCTRL_DINn_BITS        0
+#define BM_PINCTRL_DINn_BITS        0xffffffff
+#define BF_PINCTRL_DINn_BITS(v)     (((v) & 0xffffffff) << 0)
+#define BFM_PINCTRL_DINn_BITS(v)    BM_PINCTRL_DINn_BITS
+#define BF_PINCTRL_DINn_BITS_V(e)   BF_PINCTRL_DINn_BITS(BV_PINCTRL_DINn_BITS__##e)
+#define BFM_PINCTRL_DINn_BITS_V(v)  BM_PINCTRL_DINn_BITS
+
+#define HW_PINCTRL_DOEn(_n1)        HW(PINCTRL_DOEn(_n1))
+#define HWA_PINCTRL_DOEn(_n1)       (0x80018000 + 0x700 + (_n1) * 0x10)
+#define HWT_PINCTRL_DOEn(_n1)       HWIO_32_RW
+#define HWN_PINCTRL_DOEn(_n1)       PINCTRL_DOEn
+#define HWI_PINCTRL_DOEn(_n1)       (_n1)
+#define HW_PINCTRL_DOEn_SET(_n1)    HW(PINCTRL_DOEn_SET(_n1))
+#define HWA_PINCTRL_DOEn_SET(_n1)   (HWA_PINCTRL_DOEn(_n1) + 0x4)
+#define HWT_PINCTRL_DOEn_SET(_n1)   HWIO_32_WO
+#define HWN_PINCTRL_DOEn_SET(_n1)   PINCTRL_DOEn
+#define HWI_PINCTRL_DOEn_SET(_n1)   (_n1)
+#define HW_PINCTRL_DOEn_CLR(_n1)    HW(PINCTRL_DOEn_CLR(_n1))
+#define HWA_PINCTRL_DOEn_CLR(_n1)   (HWA_PINCTRL_DOEn(_n1) + 0x8)
+#define HWT_PINCTRL_DOEn_CLR(_n1)   HWIO_32_WO
+#define HWN_PINCTRL_DOEn_CLR(_n1)   PINCTRL_DOEn
+#define HWI_PINCTRL_DOEn_CLR(_n1)   (_n1)
+#define HW_PINCTRL_DOEn_TOG(_n1)    HW(PINCTRL_DOEn_TOG(_n1))
+#define HWA_PINCTRL_DOEn_TOG(_n1)   (HWA_PINCTRL_DOEn(_n1) + 0xc)
+#define HWT_PINCTRL_DOEn_TOG(_n1)   HWIO_32_WO
+#define HWN_PINCTRL_DOEn_TOG(_n1)   PINCTRL_DOEn
+#define HWI_PINCTRL_DOEn_TOG(_n1)   (_n1)
+#define BP_PINCTRL_DOEn_BITS        0
+#define BM_PINCTRL_DOEn_BITS        0xffffffff
+#define BF_PINCTRL_DOEn_BITS(v)     (((v) & 0xffffffff) << 0)
+#define BFM_PINCTRL_DOEn_BITS(v)    BM_PINCTRL_DOEn_BITS
+#define BF_PINCTRL_DOEn_BITS_V(e)   BF_PINCTRL_DOEn_BITS(BV_PINCTRL_DOEn_BITS__##e)
+#define BFM_PINCTRL_DOEn_BITS_V(v)  BM_PINCTRL_DOEn_BITS
+
+#define HW_PINCTRL_PIN2IRQn(_n1)        HW(PINCTRL_PIN2IRQn(_n1))
+#define HWA_PINCTRL_PIN2IRQn(_n1)       (0x80018000 + 0x800 + (_n1) * 0x10)
+#define HWT_PINCTRL_PIN2IRQn(_n1)       HWIO_32_RW
+#define HWN_PINCTRL_PIN2IRQn(_n1)       PINCTRL_PIN2IRQn
+#define HWI_PINCTRL_PIN2IRQn(_n1)       (_n1)
+#define HW_PINCTRL_PIN2IRQn_SET(_n1)    HW(PINCTRL_PIN2IRQn_SET(_n1))
+#define HWA_PINCTRL_PIN2IRQn_SET(_n1)   (HWA_PINCTRL_PIN2IRQn(_n1) + 0x4)
+#define HWT_PINCTRL_PIN2IRQn_SET(_n1)   HWIO_32_WO
+#define HWN_PINCTRL_PIN2IRQn_SET(_n1)   PINCTRL_PIN2IRQn
+#define HWI_PINCTRL_PIN2IRQn_SET(_n1)   (_n1)
+#define HW_PINCTRL_PIN2IRQn_CLR(_n1)    HW(PINCTRL_PIN2IRQn_CLR(_n1))
+#define HWA_PINCTRL_PIN2IRQn_CLR(_n1)   (HWA_PINCTRL_PIN2IRQn(_n1) + 0x8)
+#define HWT_PINCTRL_PIN2IRQn_CLR(_n1)   HWIO_32_WO
+#define HWN_PINCTRL_PIN2IRQn_CLR(_n1)   PINCTRL_PIN2IRQn
+#define HWI_PINCTRL_PIN2IRQn_CLR(_n1)   (_n1)
+#define HW_PINCTRL_PIN2IRQn_TOG(_n1)    HW(PINCTRL_PIN2IRQn_TOG(_n1))
+#define HWA_PINCTRL_PIN2IRQn_TOG(_n1)   (HWA_PINCTRL_PIN2IRQn(_n1) + 0xc)
+#define HWT_PINCTRL_PIN2IRQn_TOG(_n1)   HWIO_32_WO
+#define HWN_PINCTRL_PIN2IRQn_TOG(_n1)   PINCTRL_PIN2IRQn
+#define HWI_PINCTRL_PIN2IRQn_TOG(_n1)   (_n1)
+#define BP_PINCTRL_PIN2IRQn_BITS        0
+#define BM_PINCTRL_PIN2IRQn_BITS        0xffffffff
+#define BF_PINCTRL_PIN2IRQn_BITS(v)     (((v) & 0xffffffff) << 0)
+#define BFM_PINCTRL_PIN2IRQn_BITS(v)    BM_PINCTRL_PIN2IRQn_BITS
+#define BF_PINCTRL_PIN2IRQn_BITS_V(e)   BF_PINCTRL_PIN2IRQn_BITS(BV_PINCTRL_PIN2IRQn_BITS__##e)
+#define BFM_PINCTRL_PIN2IRQn_BITS_V(v)  BM_PINCTRL_PIN2IRQn_BITS
+
+#define HW_PINCTRL_IRQENn(_n1)          HW(PINCTRL_IRQENn(_n1))
+#define HWA_PINCTRL_IRQENn(_n1)         (0x80018000 + 0x900 + (_n1) * 0x10)
+#define HWT_PINCTRL_IRQENn(_n1)         HWIO_32_RW
+#define HWN_PINCTRL_IRQENn(_n1)         PINCTRL_IRQENn
+#define HWI_PINCTRL_IRQENn(_n1)         (_n1)
+#define HW_PINCTRL_IRQENn_SET(_n1)      HW(PINCTRL_IRQENn_SET(_n1))
+#define HWA_PINCTRL_IRQENn_SET(_n1)     (HWA_PINCTRL_IRQENn(_n1) + 0x4)
+#define HWT_PINCTRL_IRQENn_SET(_n1)     HWIO_32_WO
+#define HWN_PINCTRL_IRQENn_SET(_n1)     PINCTRL_IRQENn
+#define HWI_PINCTRL_IRQENn_SET(_n1)     (_n1)
+#define HW_PINCTRL_IRQENn_CLR(_n1)      HW(PINCTRL_IRQENn_CLR(_n1))
+#define HWA_PINCTRL_IRQENn_CLR(_n1)     (HWA_PINCTRL_IRQENn(_n1) + 0x8)
+#define HWT_PINCTRL_IRQENn_CLR(_n1)     HWIO_32_WO
+#define HWN_PINCTRL_IRQENn_CLR(_n1)     PINCTRL_IRQENn
+#define HWI_PINCTRL_IRQENn_CLR(_n1)     (_n1)
+#define HW_PINCTRL_IRQENn_TOG(_n1)      HW(PINCTRL_IRQENn_TOG(_n1))
+#define HWA_PINCTRL_IRQENn_TOG(_n1)     (HWA_PINCTRL_IRQENn(_n1) + 0xc)
+#define HWT_PINCTRL_IRQENn_TOG(_n1)     HWIO_32_WO
+#define HWN_PINCTRL_IRQENn_TOG(_n1)     PINCTRL_IRQENn
+#define HWI_PINCTRL_IRQENn_TOG(_n1)     (_n1)
+#define BP_PINCTRL_IRQENn_BITS          0
+#define BM_PINCTRL_IRQENn_BITS          0xffffffff
+#define BF_PINCTRL_IRQENn_BITS(v)       (((v) & 0xffffffff) << 0)
+#define BFM_PINCTRL_IRQENn_BITS(v)      BM_PINCTRL_IRQENn_BITS
+#define BF_PINCTRL_IRQENn_BITS_V(e)     BF_PINCTRL_IRQENn_BITS(BV_PINCTRL_IRQENn_BITS__##e)
+#define BFM_PINCTRL_IRQENn_BITS_V(v)    BM_PINCTRL_IRQENn_BITS
+
+#define HW_PINCTRL_IRQLEVELn(_n1)       HW(PINCTRL_IRQLEVELn(_n1))
+#define HWA_PINCTRL_IRQLEVELn(_n1)      (0x80018000 + 0xa00 + (_n1) * 0x10)
+#define HWT_PINCTRL_IRQLEVELn(_n1)      HWIO_32_RW
+#define HWN_PINCTRL_IRQLEVELn(_n1)      PINCTRL_IRQLEVELn
+#define HWI_PINCTRL_IRQLEVELn(_n1)      (_n1)
+#define HW_PINCTRL_IRQLEVELn_SET(_n1)   HW(PINCTRL_IRQLEVELn_SET(_n1))
+#define HWA_PINCTRL_IRQLEVELn_SET(_n1)  (HWA_PINCTRL_IRQLEVELn(_n1) + 0x4)
+#define HWT_PINCTRL_IRQLEVELn_SET(_n1)  HWIO_32_WO
+#define HWN_PINCTRL_IRQLEVELn_SET(_n1)  PINCTRL_IRQLEVELn
+#define HWI_PINCTRL_IRQLEVELn_SET(_n1)  (_n1)
+#define HW_PINCTRL_IRQLEVELn_CLR(_n1)   HW(PINCTRL_IRQLEVELn_CLR(_n1))
+#define HWA_PINCTRL_IRQLEVELn_CLR(_n1)  (HWA_PINCTRL_IRQLEVELn(_n1) + 0x8)
+#define HWT_PINCTRL_IRQLEVELn_CLR(_n1)  HWIO_32_WO
+#define HWN_PINCTRL_IRQLEVELn_CLR(_n1)  PINCTRL_IRQLEVELn
+#define HWI_PINCTRL_IRQLEVELn_CLR(_n1)  (_n1)
+#define HW_PINCTRL_IRQLEVELn_TOG(_n1)   HW(PINCTRL_IRQLEVELn_TOG(_n1))
+#define HWA_PINCTRL_IRQLEVELn_TOG(_n1)  (HWA_PINCTRL_IRQLEVELn(_n1) + 0xc)
+#define HWT_PINCTRL_IRQLEVELn_TOG(_n1)  HWIO_32_WO
+#define HWN_PINCTRL_IRQLEVELn_TOG(_n1)  PINCTRL_IRQLEVELn
+#define HWI_PINCTRL_IRQLEVELn_TOG(_n1)  (_n1)
+#define BP_PINCTRL_IRQLEVELn_BITS       0
+#define BM_PINCTRL_IRQLEVELn_BITS       0xffffffff
+#define BF_PINCTRL_IRQLEVELn_BITS(v)    (((v) & 0xffffffff) << 0)
+#define BFM_PINCTRL_IRQLEVELn_BITS(v)   BM_PINCTRL_IRQLEVELn_BITS
+#define BF_PINCTRL_IRQLEVELn_BITS_V(e)  BF_PINCTRL_IRQLEVELn_BITS(BV_PINCTRL_IRQLEVELn_BITS__##e)
+#define BFM_PINCTRL_IRQLEVELn_BITS_V(v) BM_PINCTRL_IRQLEVELn_BITS
+
+#define HW_PINCTRL_IRQPOLn(_n1)         HW(PINCTRL_IRQPOLn(_n1))
+#define HWA_PINCTRL_IRQPOLn(_n1)        (0x80018000 + 0xb00 + (_n1) * 0x10)
+#define HWT_PINCTRL_IRQPOLn(_n1)        HWIO_32_RW
+#define HWN_PINCTRL_IRQPOLn(_n1)        PINCTRL_IRQPOLn
+#define HWI_PINCTRL_IRQPOLn(_n1)        (_n1)
+#define HW_PINCTRL_IRQPOLn_SET(_n1)     HW(PINCTRL_IRQPOLn_SET(_n1))
+#define HWA_PINCTRL_IRQPOLn_SET(_n1)    (HWA_PINCTRL_IRQPOLn(_n1) + 0x4)
+#define HWT_PINCTRL_IRQPOLn_SET(_n1)    HWIO_32_WO
+#define HWN_PINCTRL_IRQPOLn_SET(_n1)    PINCTRL_IRQPOLn
+#define HWI_PINCTRL_IRQPOLn_SET(_n1)    (_n1)
+#define HW_PINCTRL_IRQPOLn_CLR(_n1)     HW(PINCTRL_IRQPOLn_CLR(_n1))
+#define HWA_PINCTRL_IRQPOLn_CLR(_n1)    (HWA_PINCTRL_IRQPOLn(_n1) + 0x8)
+#define HWT_PINCTRL_IRQPOLn_CLR(_n1)    HWIO_32_WO
+#define HWN_PINCTRL_IRQPOLn_CLR(_n1)    PINCTRL_IRQPOLn
+#define HWI_PINCTRL_IRQPOLn_CLR(_n1)    (_n1)
+#define HW_PINCTRL_IRQPOLn_TOG(_n1)     HW(PINCTRL_IRQPOLn_TOG(_n1))
+#define HWA_PINCTRL_IRQPOLn_TOG(_n1)    (HWA_PINCTRL_IRQPOLn(_n1) + 0xc)
+#define HWT_PINCTRL_IRQPOLn_TOG(_n1)    HWIO_32_WO
+#define HWN_PINCTRL_IRQPOLn_TOG(_n1)    PINCTRL_IRQPOLn
+#define HWI_PINCTRL_IRQPOLn_TOG(_n1)    (_n1)
+#define BP_PINCTRL_IRQPOLn_BITS         0
+#define BM_PINCTRL_IRQPOLn_BITS         0xffffffff
+#define BF_PINCTRL_IRQPOLn_BITS(v)      (((v) & 0xffffffff) << 0)
+#define BFM_PINCTRL_IRQPOLn_BITS(v)     BM_PINCTRL_IRQPOLn_BITS
+#define BF_PINCTRL_IRQPOLn_BITS_V(e)    BF_PINCTRL_IRQPOLn_BITS(BV_PINCTRL_IRQPOLn_BITS__##e)
+#define BFM_PINCTRL_IRQPOLn_BITS_V(v)   BM_PINCTRL_IRQPOLn_BITS
+
+#define HW_PINCTRL_IRQSTATn(_n1)        HW(PINCTRL_IRQSTATn(_n1))
+#define HWA_PINCTRL_IRQSTATn(_n1)       (0x80018000 + 0xc00 + (_n1) * 0x10)
+#define HWT_PINCTRL_IRQSTATn(_n1)       HWIO_32_RW
+#define HWN_PINCTRL_IRQSTATn(_n1)       PINCTRL_IRQSTATn
+#define HWI_PINCTRL_IRQSTATn(_n1)       (_n1)
+#define HW_PINCTRL_IRQSTATn_SET(_n1)    HW(PINCTRL_IRQSTATn_SET(_n1))
+#define HWA_PINCTRL_IRQSTATn_SET(_n1)   (HWA_PINCTRL_IRQSTATn(_n1) + 0x4)
+#define HWT_PINCTRL_IRQSTATn_SET(_n1)   HWIO_32_WO
+#define HWN_PINCTRL_IRQSTATn_SET(_n1)   PINCTRL_IRQSTATn
+#define HWI_PINCTRL_IRQSTATn_SET(_n1)   (_n1)
+#define HW_PINCTRL_IRQSTATn_CLR(_n1)    HW(PINCTRL_IRQSTATn_CLR(_n1))
+#define HWA_PINCTRL_IRQSTATn_CLR(_n1)   (HWA_PINCTRL_IRQSTATn(_n1) + 0x8)
+#define HWT_PINCTRL_IRQSTATn_CLR(_n1)   HWIO_32_WO
+#define HWN_PINCTRL_IRQSTATn_CLR(_n1)   PINCTRL_IRQSTATn
+#define HWI_PINCTRL_IRQSTATn_CLR(_n1)   (_n1)
+#define HW_PINCTRL_IRQSTATn_TOG(_n1)    HW(PINCTRL_IRQSTATn_TOG(_n1))
+#define HWA_PINCTRL_IRQSTATn_TOG(_n1)   (HWA_PINCTRL_IRQSTATn(_n1) + 0xc)
+#define HWT_PINCTRL_IRQSTATn_TOG(_n1)   HWIO_32_WO
+#define HWN_PINCTRL_IRQSTATn_TOG(_n1)   PINCTRL_IRQSTATn
+#define HWI_PINCTRL_IRQSTATn_TOG(_n1)   (_n1)
+#define BP_PINCTRL_IRQSTATn_BITS        0
+#define BM_PINCTRL_IRQSTATn_BITS        0xffffffff
+#define BF_PINCTRL_IRQSTATn_BITS(v)     (((v) & 0xffffffff) << 0)
+#define BFM_PINCTRL_IRQSTATn_BITS(v)    BM_PINCTRL_IRQSTATn_BITS
+#define BF_PINCTRL_IRQSTATn_BITS_V(e)   BF_PINCTRL_IRQSTATn_BITS(BV_PINCTRL_IRQSTATn_BITS__##e)
+#define BFM_PINCTRL_IRQSTATn_BITS_V(v)  BM_PINCTRL_IRQSTATn_BITS
+
+#endif /* __HEADERGEN_IMX233_PINCTRL_H__*/
diff --git a/firmware/target/arm/imx233/regs/imx233/power.h b/firmware/target/arm/imx233/regs/imx233/power.h
new file mode 100644
index 0000000000..abc3710347
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/imx233/power.h
@@ -0,0 +1,1507 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * imx233 version: 2.4.0
+ * imx233 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_IMX233_POWER_H__
+#define __HEADERGEN_IMX233_POWER_H__
+
+#define HW_POWER_CTRL                               HW(POWER_CTRL)
+#define HWA_POWER_CTRL                              (0x80044000 + 0x0)
+#define HWT_POWER_CTRL                              HWIO_32_RW
+#define HWN_POWER_CTRL                              POWER_CTRL
+#define HWI_POWER_CTRL                              
+#define HW_POWER_CTRL_SET                           HW(POWER_CTRL_SET)
+#define HWA_POWER_CTRL_SET                          (HWA_POWER_CTRL + 0x4)
+#define HWT_POWER_CTRL_SET                          HWIO_32_WO
+#define HWN_POWER_CTRL_SET                          POWER_CTRL
+#define HWI_POWER_CTRL_SET                          
+#define HW_POWER_CTRL_CLR                           HW(POWER_CTRL_CLR)
+#define HWA_POWER_CTRL_CLR                          (HWA_POWER_CTRL + 0x8)
+#define HWT_POWER_CTRL_CLR                          HWIO_32_WO
+#define HWN_POWER_CTRL_CLR                          POWER_CTRL
+#define HWI_POWER_CTRL_CLR                          
+#define HW_POWER_CTRL_TOG                           HW(POWER_CTRL_TOG)
+#define HWA_POWER_CTRL_TOG                          (HWA_POWER_CTRL + 0xc)
+#define HWT_POWER_CTRL_TOG                          HWIO_32_WO
+#define HWN_POWER_CTRL_TOG                          POWER_CTRL
+#define HWI_POWER_CTRL_TOG                          
+#define BP_POWER_CTRL_RSRVD3                        31
+#define BM_POWER_CTRL_RSRVD3                        0x80000000
+#define BF_POWER_CTRL_RSRVD3(v)                     (((v) & 0x1) << 31)
+#define BFM_POWER_CTRL_RSRVD3(v)                    BM_POWER_CTRL_RSRVD3
+#define BF_POWER_CTRL_RSRVD3_V(e)                   BF_POWER_CTRL_RSRVD3(BV_POWER_CTRL_RSRVD3__##e)
+#define BFM_POWER_CTRL_RSRVD3_V(v)                  BM_POWER_CTRL_RSRVD3
+#define BP_POWER_CTRL_CLKGATE                       30
+#define BM_POWER_CTRL_CLKGATE                       0x40000000
+#define BF_POWER_CTRL_CLKGATE(v)                    (((v) & 0x1) << 30)
+#define BFM_POWER_CTRL_CLKGATE(v)                   BM_POWER_CTRL_CLKGATE
+#define BF_POWER_CTRL_CLKGATE_V(e)                  BF_POWER_CTRL_CLKGATE(BV_POWER_CTRL_CLKGATE__##e)
+#define BFM_POWER_CTRL_CLKGATE_V(v)                 BM_POWER_CTRL_CLKGATE
+#define BP_POWER_CTRL_RSRVD2                        28
+#define BM_POWER_CTRL_RSRVD2                        0x30000000
+#define BF_POWER_CTRL_RSRVD2(v)                     (((v) & 0x3) << 28)
+#define BFM_POWER_CTRL_RSRVD2(v)                    BM_POWER_CTRL_RSRVD2
+#define BF_POWER_CTRL_RSRVD2_V(e)                   BF_POWER_CTRL_RSRVD2(BV_POWER_CTRL_RSRVD2__##e)
+#define BFM_POWER_CTRL_RSRVD2_V(v)                  BM_POWER_CTRL_RSRVD2
+#define BP_POWER_CTRL_PSWITCH_MID_TRAN              27
+#define BM_POWER_CTRL_PSWITCH_MID_TRAN              0x8000000
+#define BF_POWER_CTRL_PSWITCH_MID_TRAN(v)           (((v) & 0x1) << 27)
+#define BFM_POWER_CTRL_PSWITCH_MID_TRAN(v)          BM_POWER_CTRL_PSWITCH_MID_TRAN
+#define BF_POWER_CTRL_PSWITCH_MID_TRAN_V(e)         BF_POWER_CTRL_PSWITCH_MID_TRAN(BV_POWER_CTRL_PSWITCH_MID_TRAN__##e)
+#define BFM_POWER_CTRL_PSWITCH_MID_TRAN_V(v)        BM_POWER_CTRL_PSWITCH_MID_TRAN
+#define BP_POWER_CTRL_RSRVD1                        25
+#define BM_POWER_CTRL_RSRVD1                        0x6000000
+#define BF_POWER_CTRL_RSRVD1(v)                     (((v) & 0x3) << 25)
+#define BFM_POWER_CTRL_RSRVD1(v)                    BM_POWER_CTRL_RSRVD1
+#define BF_POWER_CTRL_RSRVD1_V(e)                   BF_POWER_CTRL_RSRVD1(BV_POWER_CTRL_RSRVD1__##e)
+#define BFM_POWER_CTRL_RSRVD1_V(v)                  BM_POWER_CTRL_RSRVD1
+#define BP_POWER_CTRL_DCDC4P2_BO_IRQ                24
+#define BM_POWER_CTRL_DCDC4P2_BO_IRQ                0x1000000
+#define BF_POWER_CTRL_DCDC4P2_BO_IRQ(v)             (((v) & 0x1) << 24)
+#define BFM_POWER_CTRL_DCDC4P2_BO_IRQ(v)            BM_POWER_CTRL_DCDC4P2_BO_IRQ
+#define BF_POWER_CTRL_DCDC4P2_BO_IRQ_V(e)           BF_POWER_CTRL_DCDC4P2_BO_IRQ(BV_POWER_CTRL_DCDC4P2_BO_IRQ__##e)
+#define BFM_POWER_CTRL_DCDC4P2_BO_IRQ_V(v)          BM_POWER_CTRL_DCDC4P2_BO_IRQ
+#define BP_POWER_CTRL_ENIRQ_DCDC4P2_BO              23
+#define BM_POWER_CTRL_ENIRQ_DCDC4P2_BO              0x800000
+#define BF_POWER_CTRL_ENIRQ_DCDC4P2_BO(v)           (((v) & 0x1) << 23)
+#define BFM_POWER_CTRL_ENIRQ_DCDC4P2_BO(v)          BM_POWER_CTRL_ENIRQ_DCDC4P2_BO
+#define BF_POWER_CTRL_ENIRQ_DCDC4P2_BO_V(e)         BF_POWER_CTRL_ENIRQ_DCDC4P2_BO(BV_POWER_CTRL_ENIRQ_DCDC4P2_BO__##e)
+#define BFM_POWER_CTRL_ENIRQ_DCDC4P2_BO_V(v)        BM_POWER_CTRL_ENIRQ_DCDC4P2_BO
+#define BP_POWER_CTRL_VDD5V_DROOP_IRQ               22
+#define BM_POWER_CTRL_VDD5V_DROOP_IRQ               0x400000
+#define BF_POWER_CTRL_VDD5V_DROOP_IRQ(v)            (((v) & 0x1) << 22)
+#define BFM_POWER_CTRL_VDD5V_DROOP_IRQ(v)           BM_POWER_CTRL_VDD5V_DROOP_IRQ
+#define BF_POWER_CTRL_VDD5V_DROOP_IRQ_V(e)          BF_POWER_CTRL_VDD5V_DROOP_IRQ(BV_POWER_CTRL_VDD5V_DROOP_IRQ__##e)
+#define BFM_POWER_CTRL_VDD5V_DROOP_IRQ_V(v)         BM_POWER_CTRL_VDD5V_DROOP_IRQ
+#define BP_POWER_CTRL_ENIRQ_VDD5V_DROOP             21
+#define BM_POWER_CTRL_ENIRQ_VDD5V_DROOP             0x200000
+#define BF_POWER_CTRL_ENIRQ_VDD5V_DROOP(v)          (((v) & 0x1) << 21)
+#define BFM_POWER_CTRL_ENIRQ_VDD5V_DROOP(v)         BM_POWER_CTRL_ENIRQ_VDD5V_DROOP
+#define BF_POWER_CTRL_ENIRQ_VDD5V_DROOP_V(e)        BF_POWER_CTRL_ENIRQ_VDD5V_DROOP(BV_POWER_CTRL_ENIRQ_VDD5V_DROOP__##e)
+#define BFM_POWER_CTRL_ENIRQ_VDD5V_DROOP_V(v)       BM_POWER_CTRL_ENIRQ_VDD5V_DROOP
+#define BP_POWER_CTRL_PSWITCH_IRQ                   20
+#define BM_POWER_CTRL_PSWITCH_IRQ                   0x100000
+#define BF_POWER_CTRL_PSWITCH_IRQ(v)                (((v) & 0x1) << 20)
+#define BFM_POWER_CTRL_PSWITCH_IRQ(v)               BM_POWER_CTRL_PSWITCH_IRQ
+#define BF_POWER_CTRL_PSWITCH_IRQ_V(e)              BF_POWER_CTRL_PSWITCH_IRQ(BV_POWER_CTRL_PSWITCH_IRQ__##e)
+#define BFM_POWER_CTRL_PSWITCH_IRQ_V(v)             BM_POWER_CTRL_PSWITCH_IRQ
+#define BP_POWER_CTRL_PSWITCH_IRQ_SRC               19
+#define BM_POWER_CTRL_PSWITCH_IRQ_SRC               0x80000
+#define BF_POWER_CTRL_PSWITCH_IRQ_SRC(v)            (((v) & 0x1) << 19)
+#define BFM_POWER_CTRL_PSWITCH_IRQ_SRC(v)           BM_POWER_CTRL_PSWITCH_IRQ_SRC
+#define BF_POWER_CTRL_PSWITCH_IRQ_SRC_V(e)          BF_POWER_CTRL_PSWITCH_IRQ_SRC(BV_POWER_CTRL_PSWITCH_IRQ_SRC__##e)
+#define BFM_POWER_CTRL_PSWITCH_IRQ_SRC_V(v)         BM_POWER_CTRL_PSWITCH_IRQ_SRC
+#define BP_POWER_CTRL_POLARITY_PSWITCH              18
+#define BM_POWER_CTRL_POLARITY_PSWITCH              0x40000
+#define BF_POWER_CTRL_POLARITY_PSWITCH(v)           (((v) & 0x1) << 18)
+#define BFM_POWER_CTRL_POLARITY_PSWITCH(v)          BM_POWER_CTRL_POLARITY_PSWITCH
+#define BF_POWER_CTRL_POLARITY_PSWITCH_V(e)         BF_POWER_CTRL_POLARITY_PSWITCH(BV_POWER_CTRL_POLARITY_PSWITCH__##e)
+#define BFM_POWER_CTRL_POLARITY_PSWITCH_V(v)        BM_POWER_CTRL_POLARITY_PSWITCH
+#define BP_POWER_CTRL_ENIRQ_PSWITCH                 17
+#define BM_POWER_CTRL_ENIRQ_PSWITCH                 0x20000
+#define BF_POWER_CTRL_ENIRQ_PSWITCH(v)              (((v) & 0x1) << 17)
+#define BFM_POWER_CTRL_ENIRQ_PSWITCH(v)             BM_POWER_CTRL_ENIRQ_PSWITCH
+#define BF_POWER_CTRL_ENIRQ_PSWITCH_V(e)            BF_POWER_CTRL_ENIRQ_PSWITCH(BV_POWER_CTRL_ENIRQ_PSWITCH__##e)
+#define BFM_POWER_CTRL_ENIRQ_PSWITCH_V(v)           BM_POWER_CTRL_ENIRQ_PSWITCH
+#define BP_POWER_CTRL_POLARITY_DC_OK                16
+#define BM_POWER_CTRL_POLARITY_DC_OK                0x10000
+#define BF_POWER_CTRL_POLARITY_DC_OK(v)             (((v) & 0x1) << 16)
+#define BFM_POWER_CTRL_POLARITY_DC_OK(v)            BM_POWER_CTRL_POLARITY_DC_OK
+#define BF_POWER_CTRL_POLARITY_DC_OK_V(e)           BF_POWER_CTRL_POLARITY_DC_OK(BV_POWER_CTRL_POLARITY_DC_OK__##e)
+#define BFM_POWER_CTRL_POLARITY_DC_OK_V(v)          BM_POWER_CTRL_POLARITY_DC_OK
+#define BP_POWER_CTRL_DC_OK_IRQ                     15
+#define BM_POWER_CTRL_DC_OK_IRQ                     0x8000
+#define BF_POWER_CTRL_DC_OK_IRQ(v)                  (((v) & 0x1) << 15)
+#define BFM_POWER_CTRL_DC_OK_IRQ(v)                 BM_POWER_CTRL_DC_OK_IRQ
+#define BF_POWER_CTRL_DC_OK_IRQ_V(e)                BF_POWER_CTRL_DC_OK_IRQ(BV_POWER_CTRL_DC_OK_IRQ__##e)
+#define BFM_POWER_CTRL_DC_OK_IRQ_V(v)               BM_POWER_CTRL_DC_OK_IRQ
+#define BP_POWER_CTRL_ENIRQ_DC_OK                   14
+#define BM_POWER_CTRL_ENIRQ_DC_OK                   0x4000
+#define BF_POWER_CTRL_ENIRQ_DC_OK(v)                (((v) & 0x1) << 14)
+#define BFM_POWER_CTRL_ENIRQ_DC_OK(v)               BM_POWER_CTRL_ENIRQ_DC_OK
+#define BF_POWER_CTRL_ENIRQ_DC_OK_V(e)              BF_POWER_CTRL_ENIRQ_DC_OK(BV_POWER_CTRL_ENIRQ_DC_OK__##e)
+#define BFM_POWER_CTRL_ENIRQ_DC_OK_V(v)             BM_POWER_CTRL_ENIRQ_DC_OK
+#define BP_POWER_CTRL_BATT_BO_IRQ                   13
+#define BM_POWER_CTRL_BATT_BO_IRQ                   0x2000
+#define BF_POWER_CTRL_BATT_BO_IRQ(v)                (((v) & 0x1) << 13)
+#define BFM_POWER_CTRL_BATT_BO_IRQ(v)               BM_POWER_CTRL_BATT_BO_IRQ
+#define BF_POWER_CTRL_BATT_BO_IRQ_V(e)              BF_POWER_CTRL_BATT_BO_IRQ(BV_POWER_CTRL_BATT_BO_IRQ__##e)
+#define BFM_POWER_CTRL_BATT_BO_IRQ_V(v)             BM_POWER_CTRL_BATT_BO_IRQ
+#define BP_POWER_CTRL_ENIRQBATT_BO                  12
+#define BM_POWER_CTRL_ENIRQBATT_BO                  0x1000
+#define BF_POWER_CTRL_ENIRQBATT_BO(v)               (((v) & 0x1) << 12)
+#define BFM_POWER_CTRL_ENIRQBATT_BO(v)              BM_POWER_CTRL_ENIRQBATT_BO
+#define BF_POWER_CTRL_ENIRQBATT_BO_V(e)             BF_POWER_CTRL_ENIRQBATT_BO(BV_POWER_CTRL_ENIRQBATT_BO__##e)
+#define BFM_POWER_CTRL_ENIRQBATT_BO_V(v)            BM_POWER_CTRL_ENIRQBATT_BO
+#define BP_POWER_CTRL_VDDIO_BO_IRQ                  11
+#define BM_POWER_CTRL_VDDIO_BO_IRQ                  0x800
+#define BF_POWER_CTRL_VDDIO_BO_IRQ(v)               (((v) & 0x1) << 11)
+#define BFM_POWER_CTRL_VDDIO_BO_IRQ(v)              BM_POWER_CTRL_VDDIO_BO_IRQ
+#define BF_POWER_CTRL_VDDIO_BO_IRQ_V(e)             BF_POWER_CTRL_VDDIO_BO_IRQ(BV_POWER_CTRL_VDDIO_BO_IRQ__##e)
+#define BFM_POWER_CTRL_VDDIO_BO_IRQ_V(v)            BM_POWER_CTRL_VDDIO_BO_IRQ
+#define BP_POWER_CTRL_ENIRQ_VDDIO_BO                10
+#define BM_POWER_CTRL_ENIRQ_VDDIO_BO                0x400
+#define BF_POWER_CTRL_ENIRQ_VDDIO_BO(v)             (((v) & 0x1) << 10)
+#define BFM_POWER_CTRL_ENIRQ_VDDIO_BO(v)            BM_POWER_CTRL_ENIRQ_VDDIO_BO
+#define BF_POWER_CTRL_ENIRQ_VDDIO_BO_V(e)           BF_POWER_CTRL_ENIRQ_VDDIO_BO(BV_POWER_CTRL_ENIRQ_VDDIO_BO__##e)
+#define BFM_POWER_CTRL_ENIRQ_VDDIO_BO_V(v)          BM_POWER_CTRL_ENIRQ_VDDIO_BO
+#define BP_POWER_CTRL_VDDA_BO_IRQ                   9
+#define BM_POWER_CTRL_VDDA_BO_IRQ                   0x200
+#define BF_POWER_CTRL_VDDA_BO_IRQ(v)                (((v) & 0x1) << 9)
+#define BFM_POWER_CTRL_VDDA_BO_IRQ(v)               BM_POWER_CTRL_VDDA_BO_IRQ
+#define BF_POWER_CTRL_VDDA_BO_IRQ_V(e)              BF_POWER_CTRL_VDDA_BO_IRQ(BV_POWER_CTRL_VDDA_BO_IRQ__##e)
+#define BFM_POWER_CTRL_VDDA_BO_IRQ_V(v)             BM_POWER_CTRL_VDDA_BO_IRQ
+#define BP_POWER_CTRL_ENIRQ_VDDA_BO                 8
+#define BM_POWER_CTRL_ENIRQ_VDDA_BO                 0x100
+#define BF_POWER_CTRL_ENIRQ_VDDA_BO(v)              (((v) & 0x1) << 8)
+#define BFM_POWER_CTRL_ENIRQ_VDDA_BO(v)             BM_POWER_CTRL_ENIRQ_VDDA_BO
+#define BF_POWER_CTRL_ENIRQ_VDDA_BO_V(e)            BF_POWER_CTRL_ENIRQ_VDDA_BO(BV_POWER_CTRL_ENIRQ_VDDA_BO__##e)
+#define BFM_POWER_CTRL_ENIRQ_VDDA_BO_V(v)           BM_POWER_CTRL_ENIRQ_VDDA_BO
+#define BP_POWER_CTRL_VDDD_BO_IRQ                   7
+#define BM_POWER_CTRL_VDDD_BO_IRQ                   0x80
+#define BF_POWER_CTRL_VDDD_BO_IRQ(v)                (((v) & 0x1) << 7)
+#define BFM_POWER_CTRL_VDDD_BO_IRQ(v)               BM_POWER_CTRL_VDDD_BO_IRQ
+#define BF_POWER_CTRL_VDDD_BO_IRQ_V(e)              BF_POWER_CTRL_VDDD_BO_IRQ(BV_POWER_CTRL_VDDD_BO_IRQ__##e)
+#define BFM_POWER_CTRL_VDDD_BO_IRQ_V(v)             BM_POWER_CTRL_VDDD_BO_IRQ
+#define BP_POWER_CTRL_ENIRQ_VDDD_BO                 6
+#define BM_POWER_CTRL_ENIRQ_VDDD_BO                 0x40
+#define BF_POWER_CTRL_ENIRQ_VDDD_BO(v)              (((v) & 0x1) << 6)
+#define BFM_POWER_CTRL_ENIRQ_VDDD_BO(v)             BM_POWER_CTRL_ENIRQ_VDDD_BO
+#define BF_POWER_CTRL_ENIRQ_VDDD_BO_V(e)            BF_POWER_CTRL_ENIRQ_VDDD_BO(BV_POWER_CTRL_ENIRQ_VDDD_BO__##e)
+#define BFM_POWER_CTRL_ENIRQ_VDDD_BO_V(v)           BM_POWER_CTRL_ENIRQ_VDDD_BO
+#define BP_POWER_CTRL_POLARITY_VBUSVALID            5
+#define BM_POWER_CTRL_POLARITY_VBUSVALID            0x20
+#define BF_POWER_CTRL_POLARITY_VBUSVALID(v)         (((v) & 0x1) << 5)
+#define BFM_POWER_CTRL_POLARITY_VBUSVALID(v)        BM_POWER_CTRL_POLARITY_VBUSVALID
+#define BF_POWER_CTRL_POLARITY_VBUSVALID_V(e)       BF_POWER_CTRL_POLARITY_VBUSVALID(BV_POWER_CTRL_POLARITY_VBUSVALID__##e)
+#define BFM_POWER_CTRL_POLARITY_VBUSVALID_V(v)      BM_POWER_CTRL_POLARITY_VBUSVALID
+#define BP_POWER_CTRL_VBUSVALID_IRQ                 4
+#define BM_POWER_CTRL_VBUSVALID_IRQ                 0x10
+#define BF_POWER_CTRL_VBUSVALID_IRQ(v)              (((v) & 0x1) << 4)
+#define BFM_POWER_CTRL_VBUSVALID_IRQ(v)             BM_POWER_CTRL_VBUSVALID_IRQ
+#define BF_POWER_CTRL_VBUSVALID_IRQ_V(e)            BF_POWER_CTRL_VBUSVALID_IRQ(BV_POWER_CTRL_VBUSVALID_IRQ__##e)
+#define BFM_POWER_CTRL_VBUSVALID_IRQ_V(v)           BM_POWER_CTRL_VBUSVALID_IRQ
+#define BP_POWER_CTRL_ENIRQ_VBUS_VALID              3
+#define BM_POWER_CTRL_ENIRQ_VBUS_VALID              0x8
+#define BF_POWER_CTRL_ENIRQ_VBUS_VALID(v)           (((v) & 0x1) << 3)
+#define BFM_POWER_CTRL_ENIRQ_VBUS_VALID(v)          BM_POWER_CTRL_ENIRQ_VBUS_VALID
+#define BF_POWER_CTRL_ENIRQ_VBUS_VALID_V(e)         BF_POWER_CTRL_ENIRQ_VBUS_VALID(BV_POWER_CTRL_ENIRQ_VBUS_VALID__##e)
+#define BFM_POWER_CTRL_ENIRQ_VBUS_VALID_V(v)        BM_POWER_CTRL_ENIRQ_VBUS_VALID
+#define BP_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO       2
+#define BM_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO       0x4
+#define BF_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO(v)    (((v) & 0x1) << 2)
+#define BFM_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO(v)   BM_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO
+#define BF_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO_V(e)  BF_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO(BV_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO__##e)
+#define BFM_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO_V(v) BM_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO
+#define BP_POWER_CTRL_VDD5V_GT_VDDIO_IRQ            1
+#define BM_POWER_CTRL_VDD5V_GT_VDDIO_IRQ            0x2
+#define BF_POWER_CTRL_VDD5V_GT_VDDIO_IRQ(v)         (((v) & 0x1) << 1)
+#define BFM_POWER_CTRL_VDD5V_GT_VDDIO_IRQ(v)        BM_POWER_CTRL_VDD5V_GT_VDDIO_IRQ
+#define BF_POWER_CTRL_VDD5V_GT_VDDIO_IRQ_V(e)       BF_POWER_CTRL_VDD5V_GT_VDDIO_IRQ(BV_POWER_CTRL_VDD5V_GT_VDDIO_IRQ__##e)
+#define BFM_POWER_CTRL_VDD5V_GT_VDDIO_IRQ_V(v)      BM_POWER_CTRL_VDD5V_GT_VDDIO_IRQ
+#define BP_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO          0
+#define BM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO          0x1
+#define BF_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO(v)       (((v) & 0x1) << 0)
+#define BFM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO(v)      BM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO
+#define BF_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO_V(e)     BF_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO(BV_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO__##e)
+#define BFM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO_V(v)    BM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO
+
+#define HW_POWER_5VCTRL                             HW(POWER_5VCTRL)
+#define HWA_POWER_5VCTRL                            (0x80044000 + 0x10)
+#define HWT_POWER_5VCTRL                            HWIO_32_RW
+#define HWN_POWER_5VCTRL                            POWER_5VCTRL
+#define HWI_POWER_5VCTRL                            
+#define HW_POWER_5VCTRL_SET                         HW(POWER_5VCTRL_SET)
+#define HWA_POWER_5VCTRL_SET                        (HWA_POWER_5VCTRL + 0x4)
+#define HWT_POWER_5VCTRL_SET                        HWIO_32_WO
+#define HWN_POWER_5VCTRL_SET                        POWER_5VCTRL
+#define HWI_POWER_5VCTRL_SET                        
+#define HW_POWER_5VCTRL_CLR                         HW(POWER_5VCTRL_CLR)
+#define HWA_POWER_5VCTRL_CLR                        (HWA_POWER_5VCTRL + 0x8)
+#define HWT_POWER_5VCTRL_CLR                        HWIO_32_WO
+#define HWN_POWER_5VCTRL_CLR                        POWER_5VCTRL
+#define HWI_POWER_5VCTRL_CLR                        
+#define HW_POWER_5VCTRL_TOG                         HW(POWER_5VCTRL_TOG)
+#define HWA_POWER_5VCTRL_TOG                        (HWA_POWER_5VCTRL + 0xc)
+#define HWT_POWER_5VCTRL_TOG                        HWIO_32_WO
+#define HWN_POWER_5VCTRL_TOG                        POWER_5VCTRL
+#define HWI_POWER_5VCTRL_TOG                        
+#define BP_POWER_5VCTRL_RSRVD6                      30
+#define BM_POWER_5VCTRL_RSRVD6                      0xc0000000
+#define BF_POWER_5VCTRL_RSRVD6(v)                   (((v) & 0x3) << 30)
+#define BFM_POWER_5VCTRL_RSRVD6(v)                  BM_POWER_5VCTRL_RSRVD6
+#define BF_POWER_5VCTRL_RSRVD6_V(e)                 BF_POWER_5VCTRL_RSRVD6(BV_POWER_5VCTRL_RSRVD6__##e)
+#define BFM_POWER_5VCTRL_RSRVD6_V(v)                BM_POWER_5VCTRL_RSRVD6
+#define BP_POWER_5VCTRL_VBUSDROOP_TRSH              28
+#define BM_POWER_5VCTRL_VBUSDROOP_TRSH              0x30000000
+#define BF_POWER_5VCTRL_VBUSDROOP_TRSH(v)           (((v) & 0x3) << 28)
+#define BFM_POWER_5VCTRL_VBUSDROOP_TRSH(v)          BM_POWER_5VCTRL_VBUSDROOP_TRSH
+#define BF_POWER_5VCTRL_VBUSDROOP_TRSH_V(e)         BF_POWER_5VCTRL_VBUSDROOP_TRSH(BV_POWER_5VCTRL_VBUSDROOP_TRSH__##e)
+#define BFM_POWER_5VCTRL_VBUSDROOP_TRSH_V(v)        BM_POWER_5VCTRL_VBUSDROOP_TRSH
+#define BP_POWER_5VCTRL_RSRVD5                      27
+#define BM_POWER_5VCTRL_RSRVD5                      0x8000000
+#define BF_POWER_5VCTRL_RSRVD5(v)                   (((v) & 0x1) << 27)
+#define BFM_POWER_5VCTRL_RSRVD5(v)                  BM_POWER_5VCTRL_RSRVD5
+#define BF_POWER_5VCTRL_RSRVD5_V(e)                 BF_POWER_5VCTRL_RSRVD5(BV_POWER_5VCTRL_RSRVD5__##e)
+#define BFM_POWER_5VCTRL_RSRVD5_V(v)                BM_POWER_5VCTRL_RSRVD5
+#define BP_POWER_5VCTRL_HEADROOM_ADJ                24
+#define BM_POWER_5VCTRL_HEADROOM_ADJ                0x7000000
+#define BF_POWER_5VCTRL_HEADROOM_ADJ(v)             (((v) & 0x7) << 24)
+#define BFM_POWER_5VCTRL_HEADROOM_ADJ(v)            BM_POWER_5VCTRL_HEADROOM_ADJ
+#define BF_POWER_5VCTRL_HEADROOM_ADJ_V(e)           BF_POWER_5VCTRL_HEADROOM_ADJ(BV_POWER_5VCTRL_HEADROOM_ADJ__##e)
+#define BFM_POWER_5VCTRL_HEADROOM_ADJ_V(v)          BM_POWER_5VCTRL_HEADROOM_ADJ
+#define BP_POWER_5VCTRL_RSRVD4                      21
+#define BM_POWER_5VCTRL_RSRVD4                      0xe00000
+#define BF_POWER_5VCTRL_RSRVD4(v)                   (((v) & 0x7) << 21)
+#define BFM_POWER_5VCTRL_RSRVD4(v)                  BM_POWER_5VCTRL_RSRVD4
+#define BF_POWER_5VCTRL_RSRVD4_V(e)                 BF_POWER_5VCTRL_RSRVD4(BV_POWER_5VCTRL_RSRVD4__##e)
+#define BFM_POWER_5VCTRL_RSRVD4_V(v)                BM_POWER_5VCTRL_RSRVD4
+#define BP_POWER_5VCTRL_PWD_CHARGE_4P2              20
+#define BM_POWER_5VCTRL_PWD_CHARGE_4P2              0x100000
+#define BF_POWER_5VCTRL_PWD_CHARGE_4P2(v)           (((v) & 0x1) << 20)
+#define BFM_POWER_5VCTRL_PWD_CHARGE_4P2(v)          BM_POWER_5VCTRL_PWD_CHARGE_4P2
+#define BF_POWER_5VCTRL_PWD_CHARGE_4P2_V(e)         BF_POWER_5VCTRL_PWD_CHARGE_4P2(BV_POWER_5VCTRL_PWD_CHARGE_4P2__##e)
+#define BFM_POWER_5VCTRL_PWD_CHARGE_4P2_V(v)        BM_POWER_5VCTRL_PWD_CHARGE_4P2
+#define BP_POWER_5VCTRL_RSRVD3                      18
+#define BM_POWER_5VCTRL_RSRVD3                      0xc0000
+#define BF_POWER_5VCTRL_RSRVD3(v)                   (((v) & 0x3) << 18)
+#define BFM_POWER_5VCTRL_RSRVD3(v)                  BM_POWER_5VCTRL_RSRVD3
+#define BF_POWER_5VCTRL_RSRVD3_V(e)                 BF_POWER_5VCTRL_RSRVD3(BV_POWER_5VCTRL_RSRVD3__##e)
+#define BFM_POWER_5VCTRL_RSRVD3_V(v)                BM_POWER_5VCTRL_RSRVD3
+#define BP_POWER_5VCTRL_CHARGE_4P2_ILIMIT           12
+#define BM_POWER_5VCTRL_CHARGE_4P2_ILIMIT           0x3f000
+#define BF_POWER_5VCTRL_CHARGE_4P2_ILIMIT(v)        (((v) & 0x3f) << 12)
+#define BFM_POWER_5VCTRL_CHARGE_4P2_ILIMIT(v)       BM_POWER_5VCTRL_CHARGE_4P2_ILIMIT
+#define BF_POWER_5VCTRL_CHARGE_4P2_ILIMIT_V(e)      BF_POWER_5VCTRL_CHARGE_4P2_ILIMIT(BV_POWER_5VCTRL_CHARGE_4P2_ILIMIT__##e)
+#define BFM_POWER_5VCTRL_CHARGE_4P2_ILIMIT_V(v)     BM_POWER_5VCTRL_CHARGE_4P2_ILIMIT
+#define BP_POWER_5VCTRL_RSRVD2                      11
+#define BM_POWER_5VCTRL_RSRVD2                      0x800
+#define BF_POWER_5VCTRL_RSRVD2(v)                   (((v) & 0x1) << 11)
+#define BFM_POWER_5VCTRL_RSRVD2(v)                  BM_POWER_5VCTRL_RSRVD2
+#define BF_POWER_5VCTRL_RSRVD2_V(e)                 BF_POWER_5VCTRL_RSRVD2(BV_POWER_5VCTRL_RSRVD2__##e)
+#define BFM_POWER_5VCTRL_RSRVD2_V(v)                BM_POWER_5VCTRL_RSRVD2
+#define BP_POWER_5VCTRL_VBUSVALID_TRSH              8
+#define BM_POWER_5VCTRL_VBUSVALID_TRSH              0x700
+#define BF_POWER_5VCTRL_VBUSVALID_TRSH(v)           (((v) & 0x7) << 8)
+#define BFM_POWER_5VCTRL_VBUSVALID_TRSH(v)          BM_POWER_5VCTRL_VBUSVALID_TRSH
+#define BF_POWER_5VCTRL_VBUSVALID_TRSH_V(e)         BF_POWER_5VCTRL_VBUSVALID_TRSH(BV_POWER_5VCTRL_VBUSVALID_TRSH__##e)
+#define BFM_POWER_5VCTRL_VBUSVALID_TRSH_V(v)        BM_POWER_5VCTRL_VBUSVALID_TRSH
+#define BP_POWER_5VCTRL_PWDN_5VBRNOUT               7
+#define BM_POWER_5VCTRL_PWDN_5VBRNOUT               0x80
+#define BF_POWER_5VCTRL_PWDN_5VBRNOUT(v)            (((v) & 0x1) << 7)
+#define BFM_POWER_5VCTRL_PWDN_5VBRNOUT(v)           BM_POWER_5VCTRL_PWDN_5VBRNOUT
+#define BF_POWER_5VCTRL_PWDN_5VBRNOUT_V(e)          BF_POWER_5VCTRL_PWDN_5VBRNOUT(BV_POWER_5VCTRL_PWDN_5VBRNOUT__##e)
+#define BFM_POWER_5VCTRL_PWDN_5VBRNOUT_V(v)         BM_POWER_5VCTRL_PWDN_5VBRNOUT
+#define BP_POWER_5VCTRL_ENABLE_LINREG_ILIMIT        6
+#define BM_POWER_5VCTRL_ENABLE_LINREG_ILIMIT        0x40
+#define BF_POWER_5VCTRL_ENABLE_LINREG_ILIMIT(v)     (((v) & 0x1) << 6)
+#define BFM_POWER_5VCTRL_ENABLE_LINREG_ILIMIT(v)    BM_POWER_5VCTRL_ENABLE_LINREG_ILIMIT
+#define BF_POWER_5VCTRL_ENABLE_LINREG_ILIMIT_V(e)   BF_POWER_5VCTRL_ENABLE_LINREG_ILIMIT(BV_POWER_5VCTRL_ENABLE_LINREG_ILIMIT__##e)
+#define BFM_POWER_5VCTRL_ENABLE_LINREG_ILIMIT_V(v)  BM_POWER_5VCTRL_ENABLE_LINREG_ILIMIT
+#define BP_POWER_5VCTRL_DCDC_XFER                   5
+#define BM_POWER_5VCTRL_DCDC_XFER                   0x20
+#define BF_POWER_5VCTRL_DCDC_XFER(v)                (((v) & 0x1) << 5)
+#define BFM_POWER_5VCTRL_DCDC_XFER(v)               BM_POWER_5VCTRL_DCDC_XFER
+#define BF_POWER_5VCTRL_DCDC_XFER_V(e)              BF_POWER_5VCTRL_DCDC_XFER(BV_POWER_5VCTRL_DCDC_XFER__##e)
+#define BFM_POWER_5VCTRL_DCDC_XFER_V(v)             BM_POWER_5VCTRL_DCDC_XFER
+#define BP_POWER_5VCTRL_VBUSVALID_5VDETECT          4
+#define BM_POWER_5VCTRL_VBUSVALID_5VDETECT          0x10
+#define BF_POWER_5VCTRL_VBUSVALID_5VDETECT(v)       (((v) & 0x1) << 4)
+#define BFM_POWER_5VCTRL_VBUSVALID_5VDETECT(v)      BM_POWER_5VCTRL_VBUSVALID_5VDETECT
+#define BF_POWER_5VCTRL_VBUSVALID_5VDETECT_V(e)     BF_POWER_5VCTRL_VBUSVALID_5VDETECT(BV_POWER_5VCTRL_VBUSVALID_5VDETECT__##e)
+#define BFM_POWER_5VCTRL_VBUSVALID_5VDETECT_V(v)    BM_POWER_5VCTRL_VBUSVALID_5VDETECT
+#define BP_POWER_5VCTRL_VBUSVALID_TO_B              3
+#define BM_POWER_5VCTRL_VBUSVALID_TO_B              0x8
+#define BF_POWER_5VCTRL_VBUSVALID_TO_B(v)           (((v) & 0x1) << 3)
+#define BFM_POWER_5VCTRL_VBUSVALID_TO_B(v)          BM_POWER_5VCTRL_VBUSVALID_TO_B
+#define BF_POWER_5VCTRL_VBUSVALID_TO_B_V(e)         BF_POWER_5VCTRL_VBUSVALID_TO_B(BV_POWER_5VCTRL_VBUSVALID_TO_B__##e)
+#define BFM_POWER_5VCTRL_VBUSVALID_TO_B_V(v)        BM_POWER_5VCTRL_VBUSVALID_TO_B
+#define BP_POWER_5VCTRL_ILIMIT_EQ_ZERO              2
+#define BM_POWER_5VCTRL_ILIMIT_EQ_ZERO              0x4
+#define BF_POWER_5VCTRL_ILIMIT_EQ_ZERO(v)           (((v) & 0x1) << 2)
+#define BFM_POWER_5VCTRL_ILIMIT_EQ_ZERO(v)          BM_POWER_5VCTRL_ILIMIT_EQ_ZERO
+#define BF_POWER_5VCTRL_ILIMIT_EQ_ZERO_V(e)         BF_POWER_5VCTRL_ILIMIT_EQ_ZERO(BV_POWER_5VCTRL_ILIMIT_EQ_ZERO__##e)
+#define BFM_POWER_5VCTRL_ILIMIT_EQ_ZERO_V(v)        BM_POWER_5VCTRL_ILIMIT_EQ_ZERO
+#define BP_POWER_5VCTRL_PWRUP_VBUS_CMPS             1
+#define BM_POWER_5VCTRL_PWRUP_VBUS_CMPS             0x2
+#define BF_POWER_5VCTRL_PWRUP_VBUS_CMPS(v)          (((v) & 0x1) << 1)
+#define BFM_POWER_5VCTRL_PWRUP_VBUS_CMPS(v)         BM_POWER_5VCTRL_PWRUP_VBUS_CMPS
+#define BF_POWER_5VCTRL_PWRUP_VBUS_CMPS_V(e)        BF_POWER_5VCTRL_PWRUP_VBUS_CMPS(BV_POWER_5VCTRL_PWRUP_VBUS_CMPS__##e)
+#define BFM_POWER_5VCTRL_PWRUP_VBUS_CMPS_V(v)       BM_POWER_5VCTRL_PWRUP_VBUS_CMPS
+#define BP_POWER_5VCTRL_ENABLE_DCDC                 0
+#define BM_POWER_5VCTRL_ENABLE_DCDC                 0x1
+#define BF_POWER_5VCTRL_ENABLE_DCDC(v)              (((v) & 0x1) << 0)
+#define BFM_POWER_5VCTRL_ENABLE_DCDC(v)             BM_POWER_5VCTRL_ENABLE_DCDC
+#define BF_POWER_5VCTRL_ENABLE_DCDC_V(e)            BF_POWER_5VCTRL_ENABLE_DCDC(BV_POWER_5VCTRL_ENABLE_DCDC__##e)
+#define BFM_POWER_5VCTRL_ENABLE_DCDC_V(v)           BM_POWER_5VCTRL_ENABLE_DCDC
+
+#define HW_POWER_MINPWR                         HW(POWER_MINPWR)
+#define HWA_POWER_MINPWR                        (0x80044000 + 0x20)
+#define HWT_POWER_MINPWR                        HWIO_32_RW
+#define HWN_POWER_MINPWR                        POWER_MINPWR
+#define HWI_POWER_MINPWR                        
+#define HW_POWER_MINPWR_SET                     HW(POWER_MINPWR_SET)
+#define HWA_POWER_MINPWR_SET                    (HWA_POWER_MINPWR + 0x4)
+#define HWT_POWER_MINPWR_SET                    HWIO_32_WO
+#define HWN_POWER_MINPWR_SET                    POWER_MINPWR
+#define HWI_POWER_MINPWR_SET                    
+#define HW_POWER_MINPWR_CLR                     HW(POWER_MINPWR_CLR)
+#define HWA_POWER_MINPWR_CLR                    (HWA_POWER_MINPWR + 0x8)
+#define HWT_POWER_MINPWR_CLR                    HWIO_32_WO
+#define HWN_POWER_MINPWR_CLR                    POWER_MINPWR
+#define HWI_POWER_MINPWR_CLR                    
+#define HW_POWER_MINPWR_TOG                     HW(POWER_MINPWR_TOG)
+#define HWA_POWER_MINPWR_TOG                    (HWA_POWER_MINPWR + 0xc)
+#define HWT_POWER_MINPWR_TOG                    HWIO_32_WO
+#define HWN_POWER_MINPWR_TOG                    POWER_MINPWR
+#define HWI_POWER_MINPWR_TOG                    
+#define BP_POWER_MINPWR_RSRVD1                  15
+#define BM_POWER_MINPWR_RSRVD1                  0xffff8000
+#define BF_POWER_MINPWR_RSRVD1(v)               (((v) & 0x1ffff) << 15)
+#define BFM_POWER_MINPWR_RSRVD1(v)              BM_POWER_MINPWR_RSRVD1
+#define BF_POWER_MINPWR_RSRVD1_V(e)             BF_POWER_MINPWR_RSRVD1(BV_POWER_MINPWR_RSRVD1__##e)
+#define BFM_POWER_MINPWR_RSRVD1_V(v)            BM_POWER_MINPWR_RSRVD1
+#define BP_POWER_MINPWR_LOWPWR_4P2              14
+#define BM_POWER_MINPWR_LOWPWR_4P2              0x4000
+#define BF_POWER_MINPWR_LOWPWR_4P2(v)           (((v) & 0x1) << 14)
+#define BFM_POWER_MINPWR_LOWPWR_4P2(v)          BM_POWER_MINPWR_LOWPWR_4P2
+#define BF_POWER_MINPWR_LOWPWR_4P2_V(e)         BF_POWER_MINPWR_LOWPWR_4P2(BV_POWER_MINPWR_LOWPWR_4P2__##e)
+#define BFM_POWER_MINPWR_LOWPWR_4P2_V(v)        BM_POWER_MINPWR_LOWPWR_4P2
+#define BP_POWER_MINPWR_VDAC_DUMP_CTRL          13
+#define BM_POWER_MINPWR_VDAC_DUMP_CTRL          0x2000
+#define BF_POWER_MINPWR_VDAC_DUMP_CTRL(v)       (((v) & 0x1) << 13)
+#define BFM_POWER_MINPWR_VDAC_DUMP_CTRL(v)      BM_POWER_MINPWR_VDAC_DUMP_CTRL
+#define BF_POWER_MINPWR_VDAC_DUMP_CTRL_V(e)     BF_POWER_MINPWR_VDAC_DUMP_CTRL(BV_POWER_MINPWR_VDAC_DUMP_CTRL__##e)
+#define BFM_POWER_MINPWR_VDAC_DUMP_CTRL_V(v)    BM_POWER_MINPWR_VDAC_DUMP_CTRL
+#define BP_POWER_MINPWR_PWD_BO                  12
+#define BM_POWER_MINPWR_PWD_BO                  0x1000
+#define BF_POWER_MINPWR_PWD_BO(v)               (((v) & 0x1) << 12)
+#define BFM_POWER_MINPWR_PWD_BO(v)              BM_POWER_MINPWR_PWD_BO
+#define BF_POWER_MINPWR_PWD_BO_V(e)             BF_POWER_MINPWR_PWD_BO(BV_POWER_MINPWR_PWD_BO__##e)
+#define BFM_POWER_MINPWR_PWD_BO_V(v)            BM_POWER_MINPWR_PWD_BO
+#define BP_POWER_MINPWR_USE_VDDXTAL_VBG         11
+#define BM_POWER_MINPWR_USE_VDDXTAL_VBG         0x800
+#define BF_POWER_MINPWR_USE_VDDXTAL_VBG(v)      (((v) & 0x1) << 11)
+#define BFM_POWER_MINPWR_USE_VDDXTAL_VBG(v)     BM_POWER_MINPWR_USE_VDDXTAL_VBG
+#define BF_POWER_MINPWR_USE_VDDXTAL_VBG_V(e)    BF_POWER_MINPWR_USE_VDDXTAL_VBG(BV_POWER_MINPWR_USE_VDDXTAL_VBG__##e)
+#define BFM_POWER_MINPWR_USE_VDDXTAL_VBG_V(v)   BM_POWER_MINPWR_USE_VDDXTAL_VBG
+#define BP_POWER_MINPWR_PWD_ANA_CMPS            10
+#define BM_POWER_MINPWR_PWD_ANA_CMPS            0x400
+#define BF_POWER_MINPWR_PWD_ANA_CMPS(v)         (((v) & 0x1) << 10)
+#define BFM_POWER_MINPWR_PWD_ANA_CMPS(v)        BM_POWER_MINPWR_PWD_ANA_CMPS
+#define BF_POWER_MINPWR_PWD_ANA_CMPS_V(e)       BF_POWER_MINPWR_PWD_ANA_CMPS(BV_POWER_MINPWR_PWD_ANA_CMPS__##e)
+#define BFM_POWER_MINPWR_PWD_ANA_CMPS_V(v)      BM_POWER_MINPWR_PWD_ANA_CMPS
+#define BP_POWER_MINPWR_ENABLE_OSC              9
+#define BM_POWER_MINPWR_ENABLE_OSC              0x200
+#define BF_POWER_MINPWR_ENABLE_OSC(v)           (((v) & 0x1) << 9)
+#define BFM_POWER_MINPWR_ENABLE_OSC(v)          BM_POWER_MINPWR_ENABLE_OSC
+#define BF_POWER_MINPWR_ENABLE_OSC_V(e)         BF_POWER_MINPWR_ENABLE_OSC(BV_POWER_MINPWR_ENABLE_OSC__##e)
+#define BFM_POWER_MINPWR_ENABLE_OSC_V(v)        BM_POWER_MINPWR_ENABLE_OSC
+#define BP_POWER_MINPWR_SELECT_OSC              8
+#define BM_POWER_MINPWR_SELECT_OSC              0x100
+#define BF_POWER_MINPWR_SELECT_OSC(v)           (((v) & 0x1) << 8)
+#define BFM_POWER_MINPWR_SELECT_OSC(v)          BM_POWER_MINPWR_SELECT_OSC
+#define BF_POWER_MINPWR_SELECT_OSC_V(e)         BF_POWER_MINPWR_SELECT_OSC(BV_POWER_MINPWR_SELECT_OSC__##e)
+#define BFM_POWER_MINPWR_SELECT_OSC_V(v)        BM_POWER_MINPWR_SELECT_OSC
+#define BP_POWER_MINPWR_VBG_OFF                 7
+#define BM_POWER_MINPWR_VBG_OFF                 0x80
+#define BF_POWER_MINPWR_VBG_OFF(v)              (((v) & 0x1) << 7)
+#define BFM_POWER_MINPWR_VBG_OFF(v)             BM_POWER_MINPWR_VBG_OFF
+#define BF_POWER_MINPWR_VBG_OFF_V(e)            BF_POWER_MINPWR_VBG_OFF(BV_POWER_MINPWR_VBG_OFF__##e)
+#define BFM_POWER_MINPWR_VBG_OFF_V(v)           BM_POWER_MINPWR_VBG_OFF
+#define BP_POWER_MINPWR_DOUBLE_FETS             6
+#define BM_POWER_MINPWR_DOUBLE_FETS             0x40
+#define BF_POWER_MINPWR_DOUBLE_FETS(v)          (((v) & 0x1) << 6)
+#define BFM_POWER_MINPWR_DOUBLE_FETS(v)         BM_POWER_MINPWR_DOUBLE_FETS
+#define BF_POWER_MINPWR_DOUBLE_FETS_V(e)        BF_POWER_MINPWR_DOUBLE_FETS(BV_POWER_MINPWR_DOUBLE_FETS__##e)
+#define BFM_POWER_MINPWR_DOUBLE_FETS_V(v)       BM_POWER_MINPWR_DOUBLE_FETS
+#define BP_POWER_MINPWR_HALF_FETS               5
+#define BM_POWER_MINPWR_HALF_FETS               0x20
+#define BF_POWER_MINPWR_HALF_FETS(v)            (((v) & 0x1) << 5)
+#define BFM_POWER_MINPWR_HALF_FETS(v)           BM_POWER_MINPWR_HALF_FETS
+#define BF_POWER_MINPWR_HALF_FETS_V(e)          BF_POWER_MINPWR_HALF_FETS(BV_POWER_MINPWR_HALF_FETS__##e)
+#define BFM_POWER_MINPWR_HALF_FETS_V(v)         BM_POWER_MINPWR_HALF_FETS
+#define BP_POWER_MINPWR_LESSANA_I               4
+#define BM_POWER_MINPWR_LESSANA_I               0x10
+#define BF_POWER_MINPWR_LESSANA_I(v)            (((v) & 0x1) << 4)
+#define BFM_POWER_MINPWR_LESSANA_I(v)           BM_POWER_MINPWR_LESSANA_I
+#define BF_POWER_MINPWR_LESSANA_I_V(e)          BF_POWER_MINPWR_LESSANA_I(BV_POWER_MINPWR_LESSANA_I__##e)
+#define BFM_POWER_MINPWR_LESSANA_I_V(v)         BM_POWER_MINPWR_LESSANA_I
+#define BP_POWER_MINPWR_PWD_XTAL24              3
+#define BM_POWER_MINPWR_PWD_XTAL24              0x8
+#define BF_POWER_MINPWR_PWD_XTAL24(v)           (((v) & 0x1) << 3)
+#define BFM_POWER_MINPWR_PWD_XTAL24(v)          BM_POWER_MINPWR_PWD_XTAL24
+#define BF_POWER_MINPWR_PWD_XTAL24_V(e)         BF_POWER_MINPWR_PWD_XTAL24(BV_POWER_MINPWR_PWD_XTAL24__##e)
+#define BFM_POWER_MINPWR_PWD_XTAL24_V(v)        BM_POWER_MINPWR_PWD_XTAL24
+#define BP_POWER_MINPWR_DC_STOPCLK              2
+#define BM_POWER_MINPWR_DC_STOPCLK              0x4
+#define BF_POWER_MINPWR_DC_STOPCLK(v)           (((v) & 0x1) << 2)
+#define BFM_POWER_MINPWR_DC_STOPCLK(v)          BM_POWER_MINPWR_DC_STOPCLK
+#define BF_POWER_MINPWR_DC_STOPCLK_V(e)         BF_POWER_MINPWR_DC_STOPCLK(BV_POWER_MINPWR_DC_STOPCLK__##e)
+#define BFM_POWER_MINPWR_DC_STOPCLK_V(v)        BM_POWER_MINPWR_DC_STOPCLK
+#define BP_POWER_MINPWR_EN_DC_PFM               1
+#define BM_POWER_MINPWR_EN_DC_PFM               0x2
+#define BF_POWER_MINPWR_EN_DC_PFM(v)            (((v) & 0x1) << 1)
+#define BFM_POWER_MINPWR_EN_DC_PFM(v)           BM_POWER_MINPWR_EN_DC_PFM
+#define BF_POWER_MINPWR_EN_DC_PFM_V(e)          BF_POWER_MINPWR_EN_DC_PFM(BV_POWER_MINPWR_EN_DC_PFM__##e)
+#define BFM_POWER_MINPWR_EN_DC_PFM_V(v)         BM_POWER_MINPWR_EN_DC_PFM
+#define BP_POWER_MINPWR_DC_HALFCLK              0
+#define BM_POWER_MINPWR_DC_HALFCLK              0x1
+#define BF_POWER_MINPWR_DC_HALFCLK(v)           (((v) & 0x1) << 0)
+#define BFM_POWER_MINPWR_DC_HALFCLK(v)          BM_POWER_MINPWR_DC_HALFCLK
+#define BF_POWER_MINPWR_DC_HALFCLK_V(e)         BF_POWER_MINPWR_DC_HALFCLK(BV_POWER_MINPWR_DC_HALFCLK__##e)
+#define BFM_POWER_MINPWR_DC_HALFCLK_V(v)        BM_POWER_MINPWR_DC_HALFCLK
+
+#define HW_POWER_CHARGE                                 HW(POWER_CHARGE)
+#define HWA_POWER_CHARGE                                (0x80044000 + 0x30)
+#define HWT_POWER_CHARGE                                HWIO_32_RW
+#define HWN_POWER_CHARGE                                POWER_CHARGE
+#define HWI_POWER_CHARGE                                
+#define HW_POWER_CHARGE_SET                             HW(POWER_CHARGE_SET)
+#define HWA_POWER_CHARGE_SET                            (HWA_POWER_CHARGE + 0x4)
+#define HWT_POWER_CHARGE_SET                            HWIO_32_WO
+#define HWN_POWER_CHARGE_SET                            POWER_CHARGE
+#define HWI_POWER_CHARGE_SET                            
+#define HW_POWER_CHARGE_CLR                             HW(POWER_CHARGE_CLR)
+#define HWA_POWER_CHARGE_CLR                            (HWA_POWER_CHARGE + 0x8)
+#define HWT_POWER_CHARGE_CLR                            HWIO_32_WO
+#define HWN_POWER_CHARGE_CLR                            POWER_CHARGE
+#define HWI_POWER_CHARGE_CLR                            
+#define HW_POWER_CHARGE_TOG                             HW(POWER_CHARGE_TOG)
+#define HWA_POWER_CHARGE_TOG                            (HWA_POWER_CHARGE + 0xc)
+#define HWT_POWER_CHARGE_TOG                            HWIO_32_WO
+#define HWN_POWER_CHARGE_TOG                            POWER_CHARGE
+#define HWI_POWER_CHARGE_TOG                            
+#define BP_POWER_CHARGE_RSRVD4                          27
+#define BM_POWER_CHARGE_RSRVD4                          0xf8000000
+#define BF_POWER_CHARGE_RSRVD4(v)                       (((v) & 0x1f) << 27)
+#define BFM_POWER_CHARGE_RSRVD4(v)                      BM_POWER_CHARGE_RSRVD4
+#define BF_POWER_CHARGE_RSRVD4_V(e)                     BF_POWER_CHARGE_RSRVD4(BV_POWER_CHARGE_RSRVD4__##e)
+#define BFM_POWER_CHARGE_RSRVD4_V(v)                    BM_POWER_CHARGE_RSRVD4
+#define BP_POWER_CHARGE_ADJ_VOLT                        24
+#define BM_POWER_CHARGE_ADJ_VOLT                        0x7000000
+#define BF_POWER_CHARGE_ADJ_VOLT(v)                     (((v) & 0x7) << 24)
+#define BFM_POWER_CHARGE_ADJ_VOLT(v)                    BM_POWER_CHARGE_ADJ_VOLT
+#define BF_POWER_CHARGE_ADJ_VOLT_V(e)                   BF_POWER_CHARGE_ADJ_VOLT(BV_POWER_CHARGE_ADJ_VOLT__##e)
+#define BFM_POWER_CHARGE_ADJ_VOLT_V(v)                  BM_POWER_CHARGE_ADJ_VOLT
+#define BP_POWER_CHARGE_RSRVD3                          23
+#define BM_POWER_CHARGE_RSRVD3                          0x800000
+#define BF_POWER_CHARGE_RSRVD3(v)                       (((v) & 0x1) << 23)
+#define BFM_POWER_CHARGE_RSRVD3(v)                      BM_POWER_CHARGE_RSRVD3
+#define BF_POWER_CHARGE_RSRVD3_V(e)                     BF_POWER_CHARGE_RSRVD3(BV_POWER_CHARGE_RSRVD3__##e)
+#define BFM_POWER_CHARGE_RSRVD3_V(v)                    BM_POWER_CHARGE_RSRVD3
+#define BP_POWER_CHARGE_ENABLE_LOAD                     22
+#define BM_POWER_CHARGE_ENABLE_LOAD                     0x400000
+#define BF_POWER_CHARGE_ENABLE_LOAD(v)                  (((v) & 0x1) << 22)
+#define BFM_POWER_CHARGE_ENABLE_LOAD(v)                 BM_POWER_CHARGE_ENABLE_LOAD
+#define BF_POWER_CHARGE_ENABLE_LOAD_V(e)                BF_POWER_CHARGE_ENABLE_LOAD(BV_POWER_CHARGE_ENABLE_LOAD__##e)
+#define BFM_POWER_CHARGE_ENABLE_LOAD_V(v)               BM_POWER_CHARGE_ENABLE_LOAD
+#define BP_POWER_CHARGE_ENABLE_CHARGER_RESISTORS        21
+#define BM_POWER_CHARGE_ENABLE_CHARGER_RESISTORS        0x200000
+#define BF_POWER_CHARGE_ENABLE_CHARGER_RESISTORS(v)     (((v) & 0x1) << 21)
+#define BFM_POWER_CHARGE_ENABLE_CHARGER_RESISTORS(v)    BM_POWER_CHARGE_ENABLE_CHARGER_RESISTORS
+#define BF_POWER_CHARGE_ENABLE_CHARGER_RESISTORS_V(e)   BF_POWER_CHARGE_ENABLE_CHARGER_RESISTORS(BV_POWER_CHARGE_ENABLE_CHARGER_RESISTORS__##e)
+#define BFM_POWER_CHARGE_ENABLE_CHARGER_RESISTORS_V(v)  BM_POWER_CHARGE_ENABLE_CHARGER_RESISTORS
+#define BP_POWER_CHARGE_ENABLE_FAULT_DETECT             20
+#define BM_POWER_CHARGE_ENABLE_FAULT_DETECT             0x100000
+#define BF_POWER_CHARGE_ENABLE_FAULT_DETECT(v)          (((v) & 0x1) << 20)
+#define BFM_POWER_CHARGE_ENABLE_FAULT_DETECT(v)         BM_POWER_CHARGE_ENABLE_FAULT_DETECT
+#define BF_POWER_CHARGE_ENABLE_FAULT_DETECT_V(e)        BF_POWER_CHARGE_ENABLE_FAULT_DETECT(BV_POWER_CHARGE_ENABLE_FAULT_DETECT__##e)
+#define BFM_POWER_CHARGE_ENABLE_FAULT_DETECT_V(v)       BM_POWER_CHARGE_ENABLE_FAULT_DETECT
+#define BP_POWER_CHARGE_CHRG_STS_OFF                    19
+#define BM_POWER_CHARGE_CHRG_STS_OFF                    0x80000
+#define BF_POWER_CHARGE_CHRG_STS_OFF(v)                 (((v) & 0x1) << 19)
+#define BFM_POWER_CHARGE_CHRG_STS_OFF(v)                BM_POWER_CHARGE_CHRG_STS_OFF
+#define BF_POWER_CHARGE_CHRG_STS_OFF_V(e)               BF_POWER_CHARGE_CHRG_STS_OFF(BV_POWER_CHARGE_CHRG_STS_OFF__##e)
+#define BFM_POWER_CHARGE_CHRG_STS_OFF_V(v)              BM_POWER_CHARGE_CHRG_STS_OFF
+#define BP_POWER_CHARGE_LIION_4P1                       18
+#define BM_POWER_CHARGE_LIION_4P1                       0x40000
+#define BF_POWER_CHARGE_LIION_4P1(v)                    (((v) & 0x1) << 18)
+#define BFM_POWER_CHARGE_LIION_4P1(v)                   BM_POWER_CHARGE_LIION_4P1
+#define BF_POWER_CHARGE_LIION_4P1_V(e)                  BF_POWER_CHARGE_LIION_4P1(BV_POWER_CHARGE_LIION_4P1__##e)
+#define BFM_POWER_CHARGE_LIION_4P1_V(v)                 BM_POWER_CHARGE_LIION_4P1
+#define BP_POWER_CHARGE_USE_EXTERN_R                    17
+#define BM_POWER_CHARGE_USE_EXTERN_R                    0x20000
+#define BF_POWER_CHARGE_USE_EXTERN_R(v)                 (((v) & 0x1) << 17)
+#define BFM_POWER_CHARGE_USE_EXTERN_R(v)                BM_POWER_CHARGE_USE_EXTERN_R
+#define BF_POWER_CHARGE_USE_EXTERN_R_V(e)               BF_POWER_CHARGE_USE_EXTERN_R(BV_POWER_CHARGE_USE_EXTERN_R__##e)
+#define BFM_POWER_CHARGE_USE_EXTERN_R_V(v)              BM_POWER_CHARGE_USE_EXTERN_R
+#define BP_POWER_CHARGE_PWD_BATTCHRG                    16
+#define BM_POWER_CHARGE_PWD_BATTCHRG                    0x10000
+#define BF_POWER_CHARGE_PWD_BATTCHRG(v)                 (((v) & 0x1) << 16)
+#define BFM_POWER_CHARGE_PWD_BATTCHRG(v)                BM_POWER_CHARGE_PWD_BATTCHRG
+#define BF_POWER_CHARGE_PWD_BATTCHRG_V(e)               BF_POWER_CHARGE_PWD_BATTCHRG(BV_POWER_CHARGE_PWD_BATTCHRG__##e)
+#define BFM_POWER_CHARGE_PWD_BATTCHRG_V(v)              BM_POWER_CHARGE_PWD_BATTCHRG
+#define BP_POWER_CHARGE_RSRVD2                          12
+#define BM_POWER_CHARGE_RSRVD2                          0xf000
+#define BF_POWER_CHARGE_RSRVD2(v)                       (((v) & 0xf) << 12)
+#define BFM_POWER_CHARGE_RSRVD2(v)                      BM_POWER_CHARGE_RSRVD2
+#define BF_POWER_CHARGE_RSRVD2_V(e)                     BF_POWER_CHARGE_RSRVD2(BV_POWER_CHARGE_RSRVD2__##e)
+#define BFM_POWER_CHARGE_RSRVD2_V(v)                    BM_POWER_CHARGE_RSRVD2
+#define BP_POWER_CHARGE_STOP_ILIMIT                     8
+#define BM_POWER_CHARGE_STOP_ILIMIT                     0xf00
+#define BF_POWER_CHARGE_STOP_ILIMIT(v)                  (((v) & 0xf) << 8)
+#define BFM_POWER_CHARGE_STOP_ILIMIT(v)                 BM_POWER_CHARGE_STOP_ILIMIT
+#define BF_POWER_CHARGE_STOP_ILIMIT_V(e)                BF_POWER_CHARGE_STOP_ILIMIT(BV_POWER_CHARGE_STOP_ILIMIT__##e)
+#define BFM_POWER_CHARGE_STOP_ILIMIT_V(v)               BM_POWER_CHARGE_STOP_ILIMIT
+#define BP_POWER_CHARGE_RSRVD1                          6
+#define BM_POWER_CHARGE_RSRVD1                          0xc0
+#define BF_POWER_CHARGE_RSRVD1(v)                       (((v) & 0x3) << 6)
+#define BFM_POWER_CHARGE_RSRVD1(v)                      BM_POWER_CHARGE_RSRVD1
+#define BF_POWER_CHARGE_RSRVD1_V(e)                     BF_POWER_CHARGE_RSRVD1(BV_POWER_CHARGE_RSRVD1__##e)
+#define BFM_POWER_CHARGE_RSRVD1_V(v)                    BM_POWER_CHARGE_RSRVD1
+#define BP_POWER_CHARGE_BATTCHRG_I                      0
+#define BM_POWER_CHARGE_BATTCHRG_I                      0x3f
+#define BF_POWER_CHARGE_BATTCHRG_I(v)                   (((v) & 0x3f) << 0)
+#define BFM_POWER_CHARGE_BATTCHRG_I(v)                  BM_POWER_CHARGE_BATTCHRG_I
+#define BF_POWER_CHARGE_BATTCHRG_I_V(e)                 BF_POWER_CHARGE_BATTCHRG_I(BV_POWER_CHARGE_BATTCHRG_I__##e)
+#define BFM_POWER_CHARGE_BATTCHRG_I_V(v)                BM_POWER_CHARGE_BATTCHRG_I
+
+#define HW_POWER_VDDDCTRL                           HW(POWER_VDDDCTRL)
+#define HWA_POWER_VDDDCTRL                          (0x80044000 + 0x40)
+#define HWT_POWER_VDDDCTRL                          HWIO_32_RW
+#define HWN_POWER_VDDDCTRL                          POWER_VDDDCTRL
+#define HWI_POWER_VDDDCTRL                          
+#define BP_POWER_VDDDCTRL_ADJTN                     28
+#define BM_POWER_VDDDCTRL_ADJTN                     0xf0000000
+#define BF_POWER_VDDDCTRL_ADJTN(v)                  (((v) & 0xf) << 28)
+#define BFM_POWER_VDDDCTRL_ADJTN(v)                 BM_POWER_VDDDCTRL_ADJTN
+#define BF_POWER_VDDDCTRL_ADJTN_V(e)                BF_POWER_VDDDCTRL_ADJTN(BV_POWER_VDDDCTRL_ADJTN__##e)
+#define BFM_POWER_VDDDCTRL_ADJTN_V(v)               BM_POWER_VDDDCTRL_ADJTN
+#define BP_POWER_VDDDCTRL_RSRVD4                    24
+#define BM_POWER_VDDDCTRL_RSRVD4                    0xf000000
+#define BF_POWER_VDDDCTRL_RSRVD4(v)                 (((v) & 0xf) << 24)
+#define BFM_POWER_VDDDCTRL_RSRVD4(v)                BM_POWER_VDDDCTRL_RSRVD4
+#define BF_POWER_VDDDCTRL_RSRVD4_V(e)               BF_POWER_VDDDCTRL_RSRVD4(BV_POWER_VDDDCTRL_RSRVD4__##e)
+#define BFM_POWER_VDDDCTRL_RSRVD4_V(v)              BM_POWER_VDDDCTRL_RSRVD4
+#define BP_POWER_VDDDCTRL_PWDN_BRNOUT               23
+#define BM_POWER_VDDDCTRL_PWDN_BRNOUT               0x800000
+#define BF_POWER_VDDDCTRL_PWDN_BRNOUT(v)            (((v) & 0x1) << 23)
+#define BFM_POWER_VDDDCTRL_PWDN_BRNOUT(v)           BM_POWER_VDDDCTRL_PWDN_BRNOUT
+#define BF_POWER_VDDDCTRL_PWDN_BRNOUT_V(e)          BF_POWER_VDDDCTRL_PWDN_BRNOUT(BV_POWER_VDDDCTRL_PWDN_BRNOUT__##e)
+#define BFM_POWER_VDDDCTRL_PWDN_BRNOUT_V(v)         BM_POWER_VDDDCTRL_PWDN_BRNOUT
+#define BP_POWER_VDDDCTRL_DISABLE_STEPPING          22
+#define BM_POWER_VDDDCTRL_DISABLE_STEPPING          0x400000
+#define BF_POWER_VDDDCTRL_DISABLE_STEPPING(v)       (((v) & 0x1) << 22)
+#define BFM_POWER_VDDDCTRL_DISABLE_STEPPING(v)      BM_POWER_VDDDCTRL_DISABLE_STEPPING
+#define BF_POWER_VDDDCTRL_DISABLE_STEPPING_V(e)     BF_POWER_VDDDCTRL_DISABLE_STEPPING(BV_POWER_VDDDCTRL_DISABLE_STEPPING__##e)
+#define BFM_POWER_VDDDCTRL_DISABLE_STEPPING_V(v)    BM_POWER_VDDDCTRL_DISABLE_STEPPING
+#define BP_POWER_VDDDCTRL_ENABLE_LINREG             21
+#define BM_POWER_VDDDCTRL_ENABLE_LINREG             0x200000
+#define BF_POWER_VDDDCTRL_ENABLE_LINREG(v)          (((v) & 0x1) << 21)
+#define BFM_POWER_VDDDCTRL_ENABLE_LINREG(v)         BM_POWER_VDDDCTRL_ENABLE_LINREG
+#define BF_POWER_VDDDCTRL_ENABLE_LINREG_V(e)        BF_POWER_VDDDCTRL_ENABLE_LINREG(BV_POWER_VDDDCTRL_ENABLE_LINREG__##e)
+#define BFM_POWER_VDDDCTRL_ENABLE_LINREG_V(v)       BM_POWER_VDDDCTRL_ENABLE_LINREG
+#define BP_POWER_VDDDCTRL_DISABLE_FET               20
+#define BM_POWER_VDDDCTRL_DISABLE_FET               0x100000
+#define BF_POWER_VDDDCTRL_DISABLE_FET(v)            (((v) & 0x1) << 20)
+#define BFM_POWER_VDDDCTRL_DISABLE_FET(v)           BM_POWER_VDDDCTRL_DISABLE_FET
+#define BF_POWER_VDDDCTRL_DISABLE_FET_V(e)          BF_POWER_VDDDCTRL_DISABLE_FET(BV_POWER_VDDDCTRL_DISABLE_FET__##e)
+#define BFM_POWER_VDDDCTRL_DISABLE_FET_V(v)         BM_POWER_VDDDCTRL_DISABLE_FET
+#define BP_POWER_VDDDCTRL_RSRVD3                    18
+#define BM_POWER_VDDDCTRL_RSRVD3                    0xc0000
+#define BF_POWER_VDDDCTRL_RSRVD3(v)                 (((v) & 0x3) << 18)
+#define BFM_POWER_VDDDCTRL_RSRVD3(v)                BM_POWER_VDDDCTRL_RSRVD3
+#define BF_POWER_VDDDCTRL_RSRVD3_V(e)               BF_POWER_VDDDCTRL_RSRVD3(BV_POWER_VDDDCTRL_RSRVD3__##e)
+#define BFM_POWER_VDDDCTRL_RSRVD3_V(v)              BM_POWER_VDDDCTRL_RSRVD3
+#define BP_POWER_VDDDCTRL_LINREG_OFFSET             16
+#define BM_POWER_VDDDCTRL_LINREG_OFFSET             0x30000
+#define BF_POWER_VDDDCTRL_LINREG_OFFSET(v)          (((v) & 0x3) << 16)
+#define BFM_POWER_VDDDCTRL_LINREG_OFFSET(v)         BM_POWER_VDDDCTRL_LINREG_OFFSET
+#define BF_POWER_VDDDCTRL_LINREG_OFFSET_V(e)        BF_POWER_VDDDCTRL_LINREG_OFFSET(BV_POWER_VDDDCTRL_LINREG_OFFSET__##e)
+#define BFM_POWER_VDDDCTRL_LINREG_OFFSET_V(v)       BM_POWER_VDDDCTRL_LINREG_OFFSET
+#define BP_POWER_VDDDCTRL_RSRVD2                    11
+#define BM_POWER_VDDDCTRL_RSRVD2                    0xf800
+#define BF_POWER_VDDDCTRL_RSRVD2(v)                 (((v) & 0x1f) << 11)
+#define BFM_POWER_VDDDCTRL_RSRVD2(v)                BM_POWER_VDDDCTRL_RSRVD2
+#define BF_POWER_VDDDCTRL_RSRVD2_V(e)               BF_POWER_VDDDCTRL_RSRVD2(BV_POWER_VDDDCTRL_RSRVD2__##e)
+#define BFM_POWER_VDDDCTRL_RSRVD2_V(v)              BM_POWER_VDDDCTRL_RSRVD2
+#define BP_POWER_VDDDCTRL_BO_OFFSET                 8
+#define BM_POWER_VDDDCTRL_BO_OFFSET                 0x700
+#define BF_POWER_VDDDCTRL_BO_OFFSET(v)              (((v) & 0x7) << 8)
+#define BFM_POWER_VDDDCTRL_BO_OFFSET(v)             BM_POWER_VDDDCTRL_BO_OFFSET
+#define BF_POWER_VDDDCTRL_BO_OFFSET_V(e)            BF_POWER_VDDDCTRL_BO_OFFSET(BV_POWER_VDDDCTRL_BO_OFFSET__##e)
+#define BFM_POWER_VDDDCTRL_BO_OFFSET_V(v)           BM_POWER_VDDDCTRL_BO_OFFSET
+#define BP_POWER_VDDDCTRL_RSRVD1                    5
+#define BM_POWER_VDDDCTRL_RSRVD1                    0xe0
+#define BF_POWER_VDDDCTRL_RSRVD1(v)                 (((v) & 0x7) << 5)
+#define BFM_POWER_VDDDCTRL_RSRVD1(v)                BM_POWER_VDDDCTRL_RSRVD1
+#define BF_POWER_VDDDCTRL_RSRVD1_V(e)               BF_POWER_VDDDCTRL_RSRVD1(BV_POWER_VDDDCTRL_RSRVD1__##e)
+#define BFM_POWER_VDDDCTRL_RSRVD1_V(v)              BM_POWER_VDDDCTRL_RSRVD1
+#define BP_POWER_VDDDCTRL_TRG                       0
+#define BM_POWER_VDDDCTRL_TRG                       0x1f
+#define BF_POWER_VDDDCTRL_TRG(v)                    (((v) & 0x1f) << 0)
+#define BFM_POWER_VDDDCTRL_TRG(v)                   BM_POWER_VDDDCTRL_TRG
+#define BF_POWER_VDDDCTRL_TRG_V(e)                  BF_POWER_VDDDCTRL_TRG(BV_POWER_VDDDCTRL_TRG__##e)
+#define BFM_POWER_VDDDCTRL_TRG_V(v)                 BM_POWER_VDDDCTRL_TRG
+
+#define HW_POWER_VDDACTRL                           HW(POWER_VDDACTRL)
+#define HWA_POWER_VDDACTRL                          (0x80044000 + 0x50)
+#define HWT_POWER_VDDACTRL                          HWIO_32_RW
+#define HWN_POWER_VDDACTRL                          POWER_VDDACTRL
+#define HWI_POWER_VDDACTRL                          
+#define BP_POWER_VDDACTRL_RSRVD4                    20
+#define BM_POWER_VDDACTRL_RSRVD4                    0xfff00000
+#define BF_POWER_VDDACTRL_RSRVD4(v)                 (((v) & 0xfff) << 20)
+#define BFM_POWER_VDDACTRL_RSRVD4(v)                BM_POWER_VDDACTRL_RSRVD4
+#define BF_POWER_VDDACTRL_RSRVD4_V(e)               BF_POWER_VDDACTRL_RSRVD4(BV_POWER_VDDACTRL_RSRVD4__##e)
+#define BFM_POWER_VDDACTRL_RSRVD4_V(v)              BM_POWER_VDDACTRL_RSRVD4
+#define BP_POWER_VDDACTRL_PWDN_BRNOUT               19
+#define BM_POWER_VDDACTRL_PWDN_BRNOUT               0x80000
+#define BF_POWER_VDDACTRL_PWDN_BRNOUT(v)            (((v) & 0x1) << 19)
+#define BFM_POWER_VDDACTRL_PWDN_BRNOUT(v)           BM_POWER_VDDACTRL_PWDN_BRNOUT
+#define BF_POWER_VDDACTRL_PWDN_BRNOUT_V(e)          BF_POWER_VDDACTRL_PWDN_BRNOUT(BV_POWER_VDDACTRL_PWDN_BRNOUT__##e)
+#define BFM_POWER_VDDACTRL_PWDN_BRNOUT_V(v)         BM_POWER_VDDACTRL_PWDN_BRNOUT
+#define BP_POWER_VDDACTRL_DISABLE_STEPPING          18
+#define BM_POWER_VDDACTRL_DISABLE_STEPPING          0x40000
+#define BF_POWER_VDDACTRL_DISABLE_STEPPING(v)       (((v) & 0x1) << 18)
+#define BFM_POWER_VDDACTRL_DISABLE_STEPPING(v)      BM_POWER_VDDACTRL_DISABLE_STEPPING
+#define BF_POWER_VDDACTRL_DISABLE_STEPPING_V(e)     BF_POWER_VDDACTRL_DISABLE_STEPPING(BV_POWER_VDDACTRL_DISABLE_STEPPING__##e)
+#define BFM_POWER_VDDACTRL_DISABLE_STEPPING_V(v)    BM_POWER_VDDACTRL_DISABLE_STEPPING
+#define BP_POWER_VDDACTRL_ENABLE_LINREG             17
+#define BM_POWER_VDDACTRL_ENABLE_LINREG             0x20000
+#define BF_POWER_VDDACTRL_ENABLE_LINREG(v)          (((v) & 0x1) << 17)
+#define BFM_POWER_VDDACTRL_ENABLE_LINREG(v)         BM_POWER_VDDACTRL_ENABLE_LINREG
+#define BF_POWER_VDDACTRL_ENABLE_LINREG_V(e)        BF_POWER_VDDACTRL_ENABLE_LINREG(BV_POWER_VDDACTRL_ENABLE_LINREG__##e)
+#define BFM_POWER_VDDACTRL_ENABLE_LINREG_V(v)       BM_POWER_VDDACTRL_ENABLE_LINREG
+#define BP_POWER_VDDACTRL_DISABLE_FET               16
+#define BM_POWER_VDDACTRL_DISABLE_FET               0x10000
+#define BF_POWER_VDDACTRL_DISABLE_FET(v)            (((v) & 0x1) << 16)
+#define BFM_POWER_VDDACTRL_DISABLE_FET(v)           BM_POWER_VDDACTRL_DISABLE_FET
+#define BF_POWER_VDDACTRL_DISABLE_FET_V(e)          BF_POWER_VDDACTRL_DISABLE_FET(BV_POWER_VDDACTRL_DISABLE_FET__##e)
+#define BFM_POWER_VDDACTRL_DISABLE_FET_V(v)         BM_POWER_VDDACTRL_DISABLE_FET
+#define BP_POWER_VDDACTRL_RSRVD3                    14
+#define BM_POWER_VDDACTRL_RSRVD3                    0xc000
+#define BF_POWER_VDDACTRL_RSRVD3(v)                 (((v) & 0x3) << 14)
+#define BFM_POWER_VDDACTRL_RSRVD3(v)                BM_POWER_VDDACTRL_RSRVD3
+#define BF_POWER_VDDACTRL_RSRVD3_V(e)               BF_POWER_VDDACTRL_RSRVD3(BV_POWER_VDDACTRL_RSRVD3__##e)
+#define BFM_POWER_VDDACTRL_RSRVD3_V(v)              BM_POWER_VDDACTRL_RSRVD3
+#define BP_POWER_VDDACTRL_LINREG_OFFSET             12
+#define BM_POWER_VDDACTRL_LINREG_OFFSET             0x3000
+#define BF_POWER_VDDACTRL_LINREG_OFFSET(v)          (((v) & 0x3) << 12)
+#define BFM_POWER_VDDACTRL_LINREG_OFFSET(v)         BM_POWER_VDDACTRL_LINREG_OFFSET
+#define BF_POWER_VDDACTRL_LINREG_OFFSET_V(e)        BF_POWER_VDDACTRL_LINREG_OFFSET(BV_POWER_VDDACTRL_LINREG_OFFSET__##e)
+#define BFM_POWER_VDDACTRL_LINREG_OFFSET_V(v)       BM_POWER_VDDACTRL_LINREG_OFFSET
+#define BP_POWER_VDDACTRL_RSRVD2                    11
+#define BM_POWER_VDDACTRL_RSRVD2                    0x800
+#define BF_POWER_VDDACTRL_RSRVD2(v)                 (((v) & 0x1) << 11)
+#define BFM_POWER_VDDACTRL_RSRVD2(v)                BM_POWER_VDDACTRL_RSRVD2
+#define BF_POWER_VDDACTRL_RSRVD2_V(e)               BF_POWER_VDDACTRL_RSRVD2(BV_POWER_VDDACTRL_RSRVD2__##e)
+#define BFM_POWER_VDDACTRL_RSRVD2_V(v)              BM_POWER_VDDACTRL_RSRVD2
+#define BP_POWER_VDDACTRL_BO_OFFSET                 8
+#define BM_POWER_VDDACTRL_BO_OFFSET                 0x700
+#define BF_POWER_VDDACTRL_BO_OFFSET(v)              (((v) & 0x7) << 8)
+#define BFM_POWER_VDDACTRL_BO_OFFSET(v)             BM_POWER_VDDACTRL_BO_OFFSET
+#define BF_POWER_VDDACTRL_BO_OFFSET_V(e)            BF_POWER_VDDACTRL_BO_OFFSET(BV_POWER_VDDACTRL_BO_OFFSET__##e)
+#define BFM_POWER_VDDACTRL_BO_OFFSET_V(v)           BM_POWER_VDDACTRL_BO_OFFSET
+#define BP_POWER_VDDACTRL_RSRVD1                    5
+#define BM_POWER_VDDACTRL_RSRVD1                    0xe0
+#define BF_POWER_VDDACTRL_RSRVD1(v)                 (((v) & 0x7) << 5)
+#define BFM_POWER_VDDACTRL_RSRVD1(v)                BM_POWER_VDDACTRL_RSRVD1
+#define BF_POWER_VDDACTRL_RSRVD1_V(e)               BF_POWER_VDDACTRL_RSRVD1(BV_POWER_VDDACTRL_RSRVD1__##e)
+#define BFM_POWER_VDDACTRL_RSRVD1_V(v)              BM_POWER_VDDACTRL_RSRVD1
+#define BP_POWER_VDDACTRL_TRG                       0
+#define BM_POWER_VDDACTRL_TRG                       0x1f
+#define BF_POWER_VDDACTRL_TRG(v)                    (((v) & 0x1f) << 0)
+#define BFM_POWER_VDDACTRL_TRG(v)                   BM_POWER_VDDACTRL_TRG
+#define BF_POWER_VDDACTRL_TRG_V(e)                  BF_POWER_VDDACTRL_TRG(BV_POWER_VDDACTRL_TRG__##e)
+#define BFM_POWER_VDDACTRL_TRG_V(v)                 BM_POWER_VDDACTRL_TRG
+
+#define HW_POWER_VDDIOCTRL                          HW(POWER_VDDIOCTRL)
+#define HWA_POWER_VDDIOCTRL                         (0x80044000 + 0x60)
+#define HWT_POWER_VDDIOCTRL                         HWIO_32_RW
+#define HWN_POWER_VDDIOCTRL                         POWER_VDDIOCTRL
+#define HWI_POWER_VDDIOCTRL                         
+#define BP_POWER_VDDIOCTRL_RSRVD5                   24
+#define BM_POWER_VDDIOCTRL_RSRVD5                   0xff000000
+#define BF_POWER_VDDIOCTRL_RSRVD5(v)                (((v) & 0xff) << 24)
+#define BFM_POWER_VDDIOCTRL_RSRVD5(v)               BM_POWER_VDDIOCTRL_RSRVD5
+#define BF_POWER_VDDIOCTRL_RSRVD5_V(e)              BF_POWER_VDDIOCTRL_RSRVD5(BV_POWER_VDDIOCTRL_RSRVD5__##e)
+#define BFM_POWER_VDDIOCTRL_RSRVD5_V(v)             BM_POWER_VDDIOCTRL_RSRVD5
+#define BP_POWER_VDDIOCTRL_ADJTN                    20
+#define BM_POWER_VDDIOCTRL_ADJTN                    0xf00000
+#define BF_POWER_VDDIOCTRL_ADJTN(v)                 (((v) & 0xf) << 20)
+#define BFM_POWER_VDDIOCTRL_ADJTN(v)                BM_POWER_VDDIOCTRL_ADJTN
+#define BF_POWER_VDDIOCTRL_ADJTN_V(e)               BF_POWER_VDDIOCTRL_ADJTN(BV_POWER_VDDIOCTRL_ADJTN__##e)
+#define BFM_POWER_VDDIOCTRL_ADJTN_V(v)              BM_POWER_VDDIOCTRL_ADJTN
+#define BP_POWER_VDDIOCTRL_RSRVD4                   19
+#define BM_POWER_VDDIOCTRL_RSRVD4                   0x80000
+#define BF_POWER_VDDIOCTRL_RSRVD4(v)                (((v) & 0x1) << 19)
+#define BFM_POWER_VDDIOCTRL_RSRVD4(v)               BM_POWER_VDDIOCTRL_RSRVD4
+#define BF_POWER_VDDIOCTRL_RSRVD4_V(e)              BF_POWER_VDDIOCTRL_RSRVD4(BV_POWER_VDDIOCTRL_RSRVD4__##e)
+#define BFM_POWER_VDDIOCTRL_RSRVD4_V(v)             BM_POWER_VDDIOCTRL_RSRVD4
+#define BP_POWER_VDDIOCTRL_PWDN_BRNOUT              18
+#define BM_POWER_VDDIOCTRL_PWDN_BRNOUT              0x40000
+#define BF_POWER_VDDIOCTRL_PWDN_BRNOUT(v)           (((v) & 0x1) << 18)
+#define BFM_POWER_VDDIOCTRL_PWDN_BRNOUT(v)          BM_POWER_VDDIOCTRL_PWDN_BRNOUT
+#define BF_POWER_VDDIOCTRL_PWDN_BRNOUT_V(e)         BF_POWER_VDDIOCTRL_PWDN_BRNOUT(BV_POWER_VDDIOCTRL_PWDN_BRNOUT__##e)
+#define BFM_POWER_VDDIOCTRL_PWDN_BRNOUT_V(v)        BM_POWER_VDDIOCTRL_PWDN_BRNOUT
+#define BP_POWER_VDDIOCTRL_DISABLE_STEPPING         17
+#define BM_POWER_VDDIOCTRL_DISABLE_STEPPING         0x20000
+#define BF_POWER_VDDIOCTRL_DISABLE_STEPPING(v)      (((v) & 0x1) << 17)
+#define BFM_POWER_VDDIOCTRL_DISABLE_STEPPING(v)     BM_POWER_VDDIOCTRL_DISABLE_STEPPING
+#define BF_POWER_VDDIOCTRL_DISABLE_STEPPING_V(e)    BF_POWER_VDDIOCTRL_DISABLE_STEPPING(BV_POWER_VDDIOCTRL_DISABLE_STEPPING__##e)
+#define BFM_POWER_VDDIOCTRL_DISABLE_STEPPING_V(v)   BM_POWER_VDDIOCTRL_DISABLE_STEPPING
+#define BP_POWER_VDDIOCTRL_DISABLE_FET              16
+#define BM_POWER_VDDIOCTRL_DISABLE_FET              0x10000
+#define BF_POWER_VDDIOCTRL_DISABLE_FET(v)           (((v) & 0x1) << 16)
+#define BFM_POWER_VDDIOCTRL_DISABLE_FET(v)          BM_POWER_VDDIOCTRL_DISABLE_FET
+#define BF_POWER_VDDIOCTRL_DISABLE_FET_V(e)         BF_POWER_VDDIOCTRL_DISABLE_FET(BV_POWER_VDDIOCTRL_DISABLE_FET__##e)
+#define BFM_POWER_VDDIOCTRL_DISABLE_FET_V(v)        BM_POWER_VDDIOCTRL_DISABLE_FET
+#define BP_POWER_VDDIOCTRL_RSRVD3                   14
+#define BM_POWER_VDDIOCTRL_RSRVD3                   0xc000
+#define BF_POWER_VDDIOCTRL_RSRVD3(v)                (((v) & 0x3) << 14)
+#define BFM_POWER_VDDIOCTRL_RSRVD3(v)               BM_POWER_VDDIOCTRL_RSRVD3
+#define BF_POWER_VDDIOCTRL_RSRVD3_V(e)              BF_POWER_VDDIOCTRL_RSRVD3(BV_POWER_VDDIOCTRL_RSRVD3__##e)
+#define BFM_POWER_VDDIOCTRL_RSRVD3_V(v)             BM_POWER_VDDIOCTRL_RSRVD3
+#define BP_POWER_VDDIOCTRL_LINREG_OFFSET            12
+#define BM_POWER_VDDIOCTRL_LINREG_OFFSET            0x3000
+#define BF_POWER_VDDIOCTRL_LINREG_OFFSET(v)         (((v) & 0x3) << 12)
+#define BFM_POWER_VDDIOCTRL_LINREG_OFFSET(v)        BM_POWER_VDDIOCTRL_LINREG_OFFSET
+#define BF_POWER_VDDIOCTRL_LINREG_OFFSET_V(e)       BF_POWER_VDDIOCTRL_LINREG_OFFSET(BV_POWER_VDDIOCTRL_LINREG_OFFSET__##e)
+#define BFM_POWER_VDDIOCTRL_LINREG_OFFSET_V(v)      BM_POWER_VDDIOCTRL_LINREG_OFFSET
+#define BP_POWER_VDDIOCTRL_RSRVD2                   11
+#define BM_POWER_VDDIOCTRL_RSRVD2                   0x800
+#define BF_POWER_VDDIOCTRL_RSRVD2(v)                (((v) & 0x1) << 11)
+#define BFM_POWER_VDDIOCTRL_RSRVD2(v)               BM_POWER_VDDIOCTRL_RSRVD2
+#define BF_POWER_VDDIOCTRL_RSRVD2_V(e)              BF_POWER_VDDIOCTRL_RSRVD2(BV_POWER_VDDIOCTRL_RSRVD2__##e)
+#define BFM_POWER_VDDIOCTRL_RSRVD2_V(v)             BM_POWER_VDDIOCTRL_RSRVD2
+#define BP_POWER_VDDIOCTRL_BO_OFFSET                8
+#define BM_POWER_VDDIOCTRL_BO_OFFSET                0x700
+#define BF_POWER_VDDIOCTRL_BO_OFFSET(v)             (((v) & 0x7) << 8)
+#define BFM_POWER_VDDIOCTRL_BO_OFFSET(v)            BM_POWER_VDDIOCTRL_BO_OFFSET
+#define BF_POWER_VDDIOCTRL_BO_OFFSET_V(e)           BF_POWER_VDDIOCTRL_BO_OFFSET(BV_POWER_VDDIOCTRL_BO_OFFSET__##e)
+#define BFM_POWER_VDDIOCTRL_BO_OFFSET_V(v)          BM_POWER_VDDIOCTRL_BO_OFFSET
+#define BP_POWER_VDDIOCTRL_RSRVD1                   5
+#define BM_POWER_VDDIOCTRL_RSRVD1                   0xe0
+#define BF_POWER_VDDIOCTRL_RSRVD1(v)                (((v) & 0x7) << 5)
+#define BFM_POWER_VDDIOCTRL_RSRVD1(v)               BM_POWER_VDDIOCTRL_RSRVD1
+#define BF_POWER_VDDIOCTRL_RSRVD1_V(e)              BF_POWER_VDDIOCTRL_RSRVD1(BV_POWER_VDDIOCTRL_RSRVD1__##e)
+#define BFM_POWER_VDDIOCTRL_RSRVD1_V(v)             BM_POWER_VDDIOCTRL_RSRVD1
+#define BP_POWER_VDDIOCTRL_TRG                      0
+#define BM_POWER_VDDIOCTRL_TRG                      0x1f
+#define BF_POWER_VDDIOCTRL_TRG(v)                   (((v) & 0x1f) << 0)
+#define BFM_POWER_VDDIOCTRL_TRG(v)                  BM_POWER_VDDIOCTRL_TRG
+#define BF_POWER_VDDIOCTRL_TRG_V(e)                 BF_POWER_VDDIOCTRL_TRG(BV_POWER_VDDIOCTRL_TRG__##e)
+#define BFM_POWER_VDDIOCTRL_TRG_V(v)                BM_POWER_VDDIOCTRL_TRG
+
+#define HW_POWER_VDDMEMCTRL                         HW(POWER_VDDMEMCTRL)
+#define HWA_POWER_VDDMEMCTRL                        (0x80044000 + 0x70)
+#define HWT_POWER_VDDMEMCTRL                        HWIO_32_RW
+#define HWN_POWER_VDDMEMCTRL                        POWER_VDDMEMCTRL
+#define HWI_POWER_VDDMEMCTRL                        
+#define BP_POWER_VDDMEMCTRL_RSRVD2                  11
+#define BM_POWER_VDDMEMCTRL_RSRVD2                  0xfffff800
+#define BF_POWER_VDDMEMCTRL_RSRVD2(v)               (((v) & 0x1fffff) << 11)
+#define BFM_POWER_VDDMEMCTRL_RSRVD2(v)              BM_POWER_VDDMEMCTRL_RSRVD2
+#define BF_POWER_VDDMEMCTRL_RSRVD2_V(e)             BF_POWER_VDDMEMCTRL_RSRVD2(BV_POWER_VDDMEMCTRL_RSRVD2__##e)
+#define BFM_POWER_VDDMEMCTRL_RSRVD2_V(v)            BM_POWER_VDDMEMCTRL_RSRVD2
+#define BP_POWER_VDDMEMCTRL_PULLDOWN_ACTIVE         10
+#define BM_POWER_VDDMEMCTRL_PULLDOWN_ACTIVE         0x400
+#define BF_POWER_VDDMEMCTRL_PULLDOWN_ACTIVE(v)      (((v) & 0x1) << 10)
+#define BFM_POWER_VDDMEMCTRL_PULLDOWN_ACTIVE(v)     BM_POWER_VDDMEMCTRL_PULLDOWN_ACTIVE
+#define BF_POWER_VDDMEMCTRL_PULLDOWN_ACTIVE_V(e)    BF_POWER_VDDMEMCTRL_PULLDOWN_ACTIVE(BV_POWER_VDDMEMCTRL_PULLDOWN_ACTIVE__##e)
+#define BFM_POWER_VDDMEMCTRL_PULLDOWN_ACTIVE_V(v)   BM_POWER_VDDMEMCTRL_PULLDOWN_ACTIVE
+#define BP_POWER_VDDMEMCTRL_ENABLE_ILIMIT           9
+#define BM_POWER_VDDMEMCTRL_ENABLE_ILIMIT           0x200
+#define BF_POWER_VDDMEMCTRL_ENABLE_ILIMIT(v)        (((v) & 0x1) << 9)
+#define BFM_POWER_VDDMEMCTRL_ENABLE_ILIMIT(v)       BM_POWER_VDDMEMCTRL_ENABLE_ILIMIT
+#define BF_POWER_VDDMEMCTRL_ENABLE_ILIMIT_V(e)      BF_POWER_VDDMEMCTRL_ENABLE_ILIMIT(BV_POWER_VDDMEMCTRL_ENABLE_ILIMIT__##e)
+#define BFM_POWER_VDDMEMCTRL_ENABLE_ILIMIT_V(v)     BM_POWER_VDDMEMCTRL_ENABLE_ILIMIT
+#define BP_POWER_VDDMEMCTRL_ENABLE_LINREG           8
+#define BM_POWER_VDDMEMCTRL_ENABLE_LINREG           0x100
+#define BF_POWER_VDDMEMCTRL_ENABLE_LINREG(v)        (((v) & 0x1) << 8)
+#define BFM_POWER_VDDMEMCTRL_ENABLE_LINREG(v)       BM_POWER_VDDMEMCTRL_ENABLE_LINREG
+#define BF_POWER_VDDMEMCTRL_ENABLE_LINREG_V(e)      BF_POWER_VDDMEMCTRL_ENABLE_LINREG(BV_POWER_VDDMEMCTRL_ENABLE_LINREG__##e)
+#define BFM_POWER_VDDMEMCTRL_ENABLE_LINREG_V(v)     BM_POWER_VDDMEMCTRL_ENABLE_LINREG
+#define BP_POWER_VDDMEMCTRL_RSRVD1                  5
+#define BM_POWER_VDDMEMCTRL_RSRVD1                  0xe0
+#define BF_POWER_VDDMEMCTRL_RSRVD1(v)               (((v) & 0x7) << 5)
+#define BFM_POWER_VDDMEMCTRL_RSRVD1(v)              BM_POWER_VDDMEMCTRL_RSRVD1
+#define BF_POWER_VDDMEMCTRL_RSRVD1_V(e)             BF_POWER_VDDMEMCTRL_RSRVD1(BV_POWER_VDDMEMCTRL_RSRVD1__##e)
+#define BFM_POWER_VDDMEMCTRL_RSRVD1_V(v)            BM_POWER_VDDMEMCTRL_RSRVD1
+#define BP_POWER_VDDMEMCTRL_TRG                     0
+#define BM_POWER_VDDMEMCTRL_TRG                     0x1f
+#define BF_POWER_VDDMEMCTRL_TRG(v)                  (((v) & 0x1f) << 0)
+#define BFM_POWER_VDDMEMCTRL_TRG(v)                 BM_POWER_VDDMEMCTRL_TRG
+#define BF_POWER_VDDMEMCTRL_TRG_V(e)                BF_POWER_VDDMEMCTRL_TRG(BV_POWER_VDDMEMCTRL_TRG__##e)
+#define BFM_POWER_VDDMEMCTRL_TRG_V(v)               BM_POWER_VDDMEMCTRL_TRG
+
+#define HW_POWER_DCDC4P2                        HW(POWER_DCDC4P2)
+#define HWA_POWER_DCDC4P2                       (0x80044000 + 0x80)
+#define HWT_POWER_DCDC4P2                       HWIO_32_RW
+#define HWN_POWER_DCDC4P2                       POWER_DCDC4P2
+#define HWI_POWER_DCDC4P2                       
+#define BP_POWER_DCDC4P2_DROPOUT_CTRL           28
+#define BM_POWER_DCDC4P2_DROPOUT_CTRL           0xf0000000
+#define BF_POWER_DCDC4P2_DROPOUT_CTRL(v)        (((v) & 0xf) << 28)
+#define BFM_POWER_DCDC4P2_DROPOUT_CTRL(v)       BM_POWER_DCDC4P2_DROPOUT_CTRL
+#define BF_POWER_DCDC4P2_DROPOUT_CTRL_V(e)      BF_POWER_DCDC4P2_DROPOUT_CTRL(BV_POWER_DCDC4P2_DROPOUT_CTRL__##e)
+#define BFM_POWER_DCDC4P2_DROPOUT_CTRL_V(v)     BM_POWER_DCDC4P2_DROPOUT_CTRL
+#define BP_POWER_DCDC4P2_RSRVD5                 26
+#define BM_POWER_DCDC4P2_RSRVD5                 0xc000000
+#define BF_POWER_DCDC4P2_RSRVD5(v)              (((v) & 0x3) << 26)
+#define BFM_POWER_DCDC4P2_RSRVD5(v)             BM_POWER_DCDC4P2_RSRVD5
+#define BF_POWER_DCDC4P2_RSRVD5_V(e)            BF_POWER_DCDC4P2_RSRVD5(BV_POWER_DCDC4P2_RSRVD5__##e)
+#define BFM_POWER_DCDC4P2_RSRVD5_V(v)           BM_POWER_DCDC4P2_RSRVD5
+#define BP_POWER_DCDC4P2_ISTEAL_THRESH          24
+#define BM_POWER_DCDC4P2_ISTEAL_THRESH          0x3000000
+#define BF_POWER_DCDC4P2_ISTEAL_THRESH(v)       (((v) & 0x3) << 24)
+#define BFM_POWER_DCDC4P2_ISTEAL_THRESH(v)      BM_POWER_DCDC4P2_ISTEAL_THRESH
+#define BF_POWER_DCDC4P2_ISTEAL_THRESH_V(e)     BF_POWER_DCDC4P2_ISTEAL_THRESH(BV_POWER_DCDC4P2_ISTEAL_THRESH__##e)
+#define BFM_POWER_DCDC4P2_ISTEAL_THRESH_V(v)    BM_POWER_DCDC4P2_ISTEAL_THRESH
+#define BP_POWER_DCDC4P2_ENABLE_4P2             23
+#define BM_POWER_DCDC4P2_ENABLE_4P2             0x800000
+#define BF_POWER_DCDC4P2_ENABLE_4P2(v)          (((v) & 0x1) << 23)
+#define BFM_POWER_DCDC4P2_ENABLE_4P2(v)         BM_POWER_DCDC4P2_ENABLE_4P2
+#define BF_POWER_DCDC4P2_ENABLE_4P2_V(e)        BF_POWER_DCDC4P2_ENABLE_4P2(BV_POWER_DCDC4P2_ENABLE_4P2__##e)
+#define BFM_POWER_DCDC4P2_ENABLE_4P2_V(v)       BM_POWER_DCDC4P2_ENABLE_4P2
+#define BP_POWER_DCDC4P2_ENABLE_DCDC            22
+#define BM_POWER_DCDC4P2_ENABLE_DCDC            0x400000
+#define BF_POWER_DCDC4P2_ENABLE_DCDC(v)         (((v) & 0x1) << 22)
+#define BFM_POWER_DCDC4P2_ENABLE_DCDC(v)        BM_POWER_DCDC4P2_ENABLE_DCDC
+#define BF_POWER_DCDC4P2_ENABLE_DCDC_V(e)       BF_POWER_DCDC4P2_ENABLE_DCDC(BV_POWER_DCDC4P2_ENABLE_DCDC__##e)
+#define BFM_POWER_DCDC4P2_ENABLE_DCDC_V(v)      BM_POWER_DCDC4P2_ENABLE_DCDC
+#define BP_POWER_DCDC4P2_HYST_DIR               21
+#define BM_POWER_DCDC4P2_HYST_DIR               0x200000
+#define BF_POWER_DCDC4P2_HYST_DIR(v)            (((v) & 0x1) << 21)
+#define BFM_POWER_DCDC4P2_HYST_DIR(v)           BM_POWER_DCDC4P2_HYST_DIR
+#define BF_POWER_DCDC4P2_HYST_DIR_V(e)          BF_POWER_DCDC4P2_HYST_DIR(BV_POWER_DCDC4P2_HYST_DIR__##e)
+#define BFM_POWER_DCDC4P2_HYST_DIR_V(v)         BM_POWER_DCDC4P2_HYST_DIR
+#define BP_POWER_DCDC4P2_HYST_THRESH            20
+#define BM_POWER_DCDC4P2_HYST_THRESH            0x100000
+#define BF_POWER_DCDC4P2_HYST_THRESH(v)         (((v) & 0x1) << 20)
+#define BFM_POWER_DCDC4P2_HYST_THRESH(v)        BM_POWER_DCDC4P2_HYST_THRESH
+#define BF_POWER_DCDC4P2_HYST_THRESH_V(e)       BF_POWER_DCDC4P2_HYST_THRESH(BV_POWER_DCDC4P2_HYST_THRESH__##e)
+#define BFM_POWER_DCDC4P2_HYST_THRESH_V(v)      BM_POWER_DCDC4P2_HYST_THRESH
+#define BP_POWER_DCDC4P2_RSRVD3                 19
+#define BM_POWER_DCDC4P2_RSRVD3                 0x80000
+#define BF_POWER_DCDC4P2_RSRVD3(v)              (((v) & 0x1) << 19)
+#define BFM_POWER_DCDC4P2_RSRVD3(v)             BM_POWER_DCDC4P2_RSRVD3
+#define BF_POWER_DCDC4P2_RSRVD3_V(e)            BF_POWER_DCDC4P2_RSRVD3(BV_POWER_DCDC4P2_RSRVD3__##e)
+#define BFM_POWER_DCDC4P2_RSRVD3_V(v)           BM_POWER_DCDC4P2_RSRVD3
+#define BP_POWER_DCDC4P2_TRG                    16
+#define BM_POWER_DCDC4P2_TRG                    0x70000
+#define BF_POWER_DCDC4P2_TRG(v)                 (((v) & 0x7) << 16)
+#define BFM_POWER_DCDC4P2_TRG(v)                BM_POWER_DCDC4P2_TRG
+#define BF_POWER_DCDC4P2_TRG_V(e)               BF_POWER_DCDC4P2_TRG(BV_POWER_DCDC4P2_TRG__##e)
+#define BFM_POWER_DCDC4P2_TRG_V(v)              BM_POWER_DCDC4P2_TRG
+#define BP_POWER_DCDC4P2_RSRVD2                 13
+#define BM_POWER_DCDC4P2_RSRVD2                 0xe000
+#define BF_POWER_DCDC4P2_RSRVD2(v)              (((v) & 0x7) << 13)
+#define BFM_POWER_DCDC4P2_RSRVD2(v)             BM_POWER_DCDC4P2_RSRVD2
+#define BF_POWER_DCDC4P2_RSRVD2_V(e)            BF_POWER_DCDC4P2_RSRVD2(BV_POWER_DCDC4P2_RSRVD2__##e)
+#define BFM_POWER_DCDC4P2_RSRVD2_V(v)           BM_POWER_DCDC4P2_RSRVD2
+#define BP_POWER_DCDC4P2_BO                     8
+#define BM_POWER_DCDC4P2_BO                     0x1f00
+#define BF_POWER_DCDC4P2_BO(v)                  (((v) & 0x1f) << 8)
+#define BFM_POWER_DCDC4P2_BO(v)                 BM_POWER_DCDC4P2_BO
+#define BF_POWER_DCDC4P2_BO_V(e)                BF_POWER_DCDC4P2_BO(BV_POWER_DCDC4P2_BO__##e)
+#define BFM_POWER_DCDC4P2_BO_V(v)               BM_POWER_DCDC4P2_BO
+#define BP_POWER_DCDC4P2_RSRVD1                 5
+#define BM_POWER_DCDC4P2_RSRVD1                 0xe0
+#define BF_POWER_DCDC4P2_RSRVD1(v)              (((v) & 0x7) << 5)
+#define BFM_POWER_DCDC4P2_RSRVD1(v)             BM_POWER_DCDC4P2_RSRVD1
+#define BF_POWER_DCDC4P2_RSRVD1_V(e)            BF_POWER_DCDC4P2_RSRVD1(BV_POWER_DCDC4P2_RSRVD1__##e)
+#define BFM_POWER_DCDC4P2_RSRVD1_V(v)           BM_POWER_DCDC4P2_RSRVD1
+#define BP_POWER_DCDC4P2_CMPTRIP                0
+#define BM_POWER_DCDC4P2_CMPTRIP                0x1f
+#define BF_POWER_DCDC4P2_CMPTRIP(v)             (((v) & 0x1f) << 0)
+#define BFM_POWER_DCDC4P2_CMPTRIP(v)            BM_POWER_DCDC4P2_CMPTRIP
+#define BF_POWER_DCDC4P2_CMPTRIP_V(e)           BF_POWER_DCDC4P2_CMPTRIP(BV_POWER_DCDC4P2_CMPTRIP__##e)
+#define BFM_POWER_DCDC4P2_CMPTRIP_V(v)          BM_POWER_DCDC4P2_CMPTRIP
+
+#define HW_POWER_MISC                       HW(POWER_MISC)
+#define HWA_POWER_MISC                      (0x80044000 + 0x90)
+#define HWT_POWER_MISC                      HWIO_32_RW
+#define HWN_POWER_MISC                      POWER_MISC
+#define HWI_POWER_MISC                      
+#define BP_POWER_MISC_RSRVD2                7
+#define BM_POWER_MISC_RSRVD2                0xffffff80
+#define BF_POWER_MISC_RSRVD2(v)             (((v) & 0x1ffffff) << 7)
+#define BFM_POWER_MISC_RSRVD2(v)            BM_POWER_MISC_RSRVD2
+#define BF_POWER_MISC_RSRVD2_V(e)           BF_POWER_MISC_RSRVD2(BV_POWER_MISC_RSRVD2__##e)
+#define BFM_POWER_MISC_RSRVD2_V(v)          BM_POWER_MISC_RSRVD2
+#define BP_POWER_MISC_FREQSEL               4
+#define BM_POWER_MISC_FREQSEL               0x70
+#define BF_POWER_MISC_FREQSEL(v)            (((v) & 0x7) << 4)
+#define BFM_POWER_MISC_FREQSEL(v)           BM_POWER_MISC_FREQSEL
+#define BF_POWER_MISC_FREQSEL_V(e)          BF_POWER_MISC_FREQSEL(BV_POWER_MISC_FREQSEL__##e)
+#define BFM_POWER_MISC_FREQSEL_V(v)         BM_POWER_MISC_FREQSEL
+#define BP_POWER_MISC_RSRVD1                3
+#define BM_POWER_MISC_RSRVD1                0x8
+#define BF_POWER_MISC_RSRVD1(v)             (((v) & 0x1) << 3)
+#define BFM_POWER_MISC_RSRVD1(v)            BM_POWER_MISC_RSRVD1
+#define BF_POWER_MISC_RSRVD1_V(e)           BF_POWER_MISC_RSRVD1(BV_POWER_MISC_RSRVD1__##e)
+#define BFM_POWER_MISC_RSRVD1_V(v)          BM_POWER_MISC_RSRVD1
+#define BP_POWER_MISC_DELAY_TIMING          2
+#define BM_POWER_MISC_DELAY_TIMING          0x4
+#define BF_POWER_MISC_DELAY_TIMING(v)       (((v) & 0x1) << 2)
+#define BFM_POWER_MISC_DELAY_TIMING(v)      BM_POWER_MISC_DELAY_TIMING
+#define BF_POWER_MISC_DELAY_TIMING_V(e)     BF_POWER_MISC_DELAY_TIMING(BV_POWER_MISC_DELAY_TIMING__##e)
+#define BFM_POWER_MISC_DELAY_TIMING_V(v)    BM_POWER_MISC_DELAY_TIMING
+#define BP_POWER_MISC_TEST                  1
+#define BM_POWER_MISC_TEST                  0x2
+#define BF_POWER_MISC_TEST(v)               (((v) & 0x1) << 1)
+#define BFM_POWER_MISC_TEST(v)              BM_POWER_MISC_TEST
+#define BF_POWER_MISC_TEST_V(e)             BF_POWER_MISC_TEST(BV_POWER_MISC_TEST__##e)
+#define BFM_POWER_MISC_TEST_V(v)            BM_POWER_MISC_TEST
+#define BP_POWER_MISC_SEL_PLLCLK            0
+#define BM_POWER_MISC_SEL_PLLCLK            0x1
+#define BF_POWER_MISC_SEL_PLLCLK(v)         (((v) & 0x1) << 0)
+#define BFM_POWER_MISC_SEL_PLLCLK(v)        BM_POWER_MISC_SEL_PLLCLK
+#define BF_POWER_MISC_SEL_PLLCLK_V(e)       BF_POWER_MISC_SEL_PLLCLK(BV_POWER_MISC_SEL_PLLCLK__##e)
+#define BFM_POWER_MISC_SEL_PLLCLK_V(v)      BM_POWER_MISC_SEL_PLLCLK
+
+#define HW_POWER_DCLIMITS                       HW(POWER_DCLIMITS)
+#define HWA_POWER_DCLIMITS                      (0x80044000 + 0xa0)
+#define HWT_POWER_DCLIMITS                      HWIO_32_RW
+#define HWN_POWER_DCLIMITS                      POWER_DCLIMITS
+#define HWI_POWER_DCLIMITS                      
+#define BP_POWER_DCLIMITS_RSRVD3                16
+#define BM_POWER_DCLIMITS_RSRVD3                0xffff0000
+#define BF_POWER_DCLIMITS_RSRVD3(v)             (((v) & 0xffff) << 16)
+#define BFM_POWER_DCLIMITS_RSRVD3(v)            BM_POWER_DCLIMITS_RSRVD3
+#define BF_POWER_DCLIMITS_RSRVD3_V(e)           BF_POWER_DCLIMITS_RSRVD3(BV_POWER_DCLIMITS_RSRVD3__##e)
+#define BFM_POWER_DCLIMITS_RSRVD3_V(v)          BM_POWER_DCLIMITS_RSRVD3
+#define BP_POWER_DCLIMITS_RSRVD2                15
+#define BM_POWER_DCLIMITS_RSRVD2                0x8000
+#define BF_POWER_DCLIMITS_RSRVD2(v)             (((v) & 0x1) << 15)
+#define BFM_POWER_DCLIMITS_RSRVD2(v)            BM_POWER_DCLIMITS_RSRVD2
+#define BF_POWER_DCLIMITS_RSRVD2_V(e)           BF_POWER_DCLIMITS_RSRVD2(BV_POWER_DCLIMITS_RSRVD2__##e)
+#define BFM_POWER_DCLIMITS_RSRVD2_V(v)          BM_POWER_DCLIMITS_RSRVD2
+#define BP_POWER_DCLIMITS_POSLIMIT_BUCK         8
+#define BM_POWER_DCLIMITS_POSLIMIT_BUCK         0x7f00
+#define BF_POWER_DCLIMITS_POSLIMIT_BUCK(v)      (((v) & 0x7f) << 8)
+#define BFM_POWER_DCLIMITS_POSLIMIT_BUCK(v)     BM_POWER_DCLIMITS_POSLIMIT_BUCK
+#define BF_POWER_DCLIMITS_POSLIMIT_BUCK_V(e)    BF_POWER_DCLIMITS_POSLIMIT_BUCK(BV_POWER_DCLIMITS_POSLIMIT_BUCK__##e)
+#define BFM_POWER_DCLIMITS_POSLIMIT_BUCK_V(v)   BM_POWER_DCLIMITS_POSLIMIT_BUCK
+#define BP_POWER_DCLIMITS_RSRVD1                7
+#define BM_POWER_DCLIMITS_RSRVD1                0x80
+#define BF_POWER_DCLIMITS_RSRVD1(v)             (((v) & 0x1) << 7)
+#define BFM_POWER_DCLIMITS_RSRVD1(v)            BM_POWER_DCLIMITS_RSRVD1
+#define BF_POWER_DCLIMITS_RSRVD1_V(e)           BF_POWER_DCLIMITS_RSRVD1(BV_POWER_DCLIMITS_RSRVD1__##e)
+#define BFM_POWER_DCLIMITS_RSRVD1_V(v)          BM_POWER_DCLIMITS_RSRVD1
+#define BP_POWER_DCLIMITS_NEGLIMIT              0
+#define BM_POWER_DCLIMITS_NEGLIMIT              0x7f
+#define BF_POWER_DCLIMITS_NEGLIMIT(v)           (((v) & 0x7f) << 0)
+#define BFM_POWER_DCLIMITS_NEGLIMIT(v)          BM_POWER_DCLIMITS_NEGLIMIT
+#define BF_POWER_DCLIMITS_NEGLIMIT_V(e)         BF_POWER_DCLIMITS_NEGLIMIT(BV_POWER_DCLIMITS_NEGLIMIT__##e)
+#define BFM_POWER_DCLIMITS_NEGLIMIT_V(v)        BM_POWER_DCLIMITS_NEGLIMIT
+
+#define HW_POWER_LOOPCTRL                       HW(POWER_LOOPCTRL)
+#define HWA_POWER_LOOPCTRL                      (0x80044000 + 0xb0)
+#define HWT_POWER_LOOPCTRL                      HWIO_32_RW
+#define HWN_POWER_LOOPCTRL                      POWER_LOOPCTRL
+#define HWI_POWER_LOOPCTRL                      
+#define HW_POWER_LOOPCTRL_SET                   HW(POWER_LOOPCTRL_SET)
+#define HWA_POWER_LOOPCTRL_SET                  (HWA_POWER_LOOPCTRL + 0x4)
+#define HWT_POWER_LOOPCTRL_SET                  HWIO_32_WO
+#define HWN_POWER_LOOPCTRL_SET                  POWER_LOOPCTRL
+#define HWI_POWER_LOOPCTRL_SET                  
+#define HW_POWER_LOOPCTRL_CLR                   HW(POWER_LOOPCTRL_CLR)
+#define HWA_POWER_LOOPCTRL_CLR                  (HWA_POWER_LOOPCTRL + 0x8)
+#define HWT_POWER_LOOPCTRL_CLR                  HWIO_32_WO
+#define HWN_POWER_LOOPCTRL_CLR                  POWER_LOOPCTRL
+#define HWI_POWER_LOOPCTRL_CLR                  
+#define HW_POWER_LOOPCTRL_TOG                   HW(POWER_LOOPCTRL_TOG)
+#define HWA_POWER_LOOPCTRL_TOG                  (HWA_POWER_LOOPCTRL + 0xc)
+#define HWT_POWER_LOOPCTRL_TOG                  HWIO_32_WO
+#define HWN_POWER_LOOPCTRL_TOG                  POWER_LOOPCTRL
+#define HWI_POWER_LOOPCTRL_TOG                  
+#define BP_POWER_LOOPCTRL_RSRVD3                21
+#define BM_POWER_LOOPCTRL_RSRVD3                0xffe00000
+#define BF_POWER_LOOPCTRL_RSRVD3(v)             (((v) & 0x7ff) << 21)
+#define BFM_POWER_LOOPCTRL_RSRVD3(v)            BM_POWER_LOOPCTRL_RSRVD3
+#define BF_POWER_LOOPCTRL_RSRVD3_V(e)           BF_POWER_LOOPCTRL_RSRVD3(BV_POWER_LOOPCTRL_RSRVD3__##e)
+#define BFM_POWER_LOOPCTRL_RSRVD3_V(v)          BM_POWER_LOOPCTRL_RSRVD3
+#define BP_POWER_LOOPCTRL_TOGGLE_DIF            20
+#define BM_POWER_LOOPCTRL_TOGGLE_DIF            0x100000
+#define BF_POWER_LOOPCTRL_TOGGLE_DIF(v)         (((v) & 0x1) << 20)
+#define BFM_POWER_LOOPCTRL_TOGGLE_DIF(v)        BM_POWER_LOOPCTRL_TOGGLE_DIF
+#define BF_POWER_LOOPCTRL_TOGGLE_DIF_V(e)       BF_POWER_LOOPCTRL_TOGGLE_DIF(BV_POWER_LOOPCTRL_TOGGLE_DIF__##e)
+#define BFM_POWER_LOOPCTRL_TOGGLE_DIF_V(v)      BM_POWER_LOOPCTRL_TOGGLE_DIF
+#define BP_POWER_LOOPCTRL_HYST_SIGN             19
+#define BM_POWER_LOOPCTRL_HYST_SIGN             0x80000
+#define BF_POWER_LOOPCTRL_HYST_SIGN(v)          (((v) & 0x1) << 19)
+#define BFM_POWER_LOOPCTRL_HYST_SIGN(v)         BM_POWER_LOOPCTRL_HYST_SIGN
+#define BF_POWER_LOOPCTRL_HYST_SIGN_V(e)        BF_POWER_LOOPCTRL_HYST_SIGN(BV_POWER_LOOPCTRL_HYST_SIGN__##e)
+#define BFM_POWER_LOOPCTRL_HYST_SIGN_V(v)       BM_POWER_LOOPCTRL_HYST_SIGN
+#define BP_POWER_LOOPCTRL_EN_CM_HYST            18
+#define BM_POWER_LOOPCTRL_EN_CM_HYST            0x40000
+#define BF_POWER_LOOPCTRL_EN_CM_HYST(v)         (((v) & 0x1) << 18)
+#define BFM_POWER_LOOPCTRL_EN_CM_HYST(v)        BM_POWER_LOOPCTRL_EN_CM_HYST
+#define BF_POWER_LOOPCTRL_EN_CM_HYST_V(e)       BF_POWER_LOOPCTRL_EN_CM_HYST(BV_POWER_LOOPCTRL_EN_CM_HYST__##e)
+#define BFM_POWER_LOOPCTRL_EN_CM_HYST_V(v)      BM_POWER_LOOPCTRL_EN_CM_HYST
+#define BP_POWER_LOOPCTRL_EN_DF_HYST            17
+#define BM_POWER_LOOPCTRL_EN_DF_HYST            0x20000
+#define BF_POWER_LOOPCTRL_EN_DF_HYST(v)         (((v) & 0x1) << 17)
+#define BFM_POWER_LOOPCTRL_EN_DF_HYST(v)        BM_POWER_LOOPCTRL_EN_DF_HYST
+#define BF_POWER_LOOPCTRL_EN_DF_HYST_V(e)       BF_POWER_LOOPCTRL_EN_DF_HYST(BV_POWER_LOOPCTRL_EN_DF_HYST__##e)
+#define BFM_POWER_LOOPCTRL_EN_DF_HYST_V(v)      BM_POWER_LOOPCTRL_EN_DF_HYST
+#define BP_POWER_LOOPCTRL_CM_HYST_THRESH        16
+#define BM_POWER_LOOPCTRL_CM_HYST_THRESH        0x10000
+#define BF_POWER_LOOPCTRL_CM_HYST_THRESH(v)     (((v) & 0x1) << 16)
+#define BFM_POWER_LOOPCTRL_CM_HYST_THRESH(v)    BM_POWER_LOOPCTRL_CM_HYST_THRESH
+#define BF_POWER_LOOPCTRL_CM_HYST_THRESH_V(e)   BF_POWER_LOOPCTRL_CM_HYST_THRESH(BV_POWER_LOOPCTRL_CM_HYST_THRESH__##e)
+#define BFM_POWER_LOOPCTRL_CM_HYST_THRESH_V(v)  BM_POWER_LOOPCTRL_CM_HYST_THRESH
+#define BP_POWER_LOOPCTRL_DF_HYST_THRESH        15
+#define BM_POWER_LOOPCTRL_DF_HYST_THRESH        0x8000
+#define BF_POWER_LOOPCTRL_DF_HYST_THRESH(v)     (((v) & 0x1) << 15)
+#define BFM_POWER_LOOPCTRL_DF_HYST_THRESH(v)    BM_POWER_LOOPCTRL_DF_HYST_THRESH
+#define BF_POWER_LOOPCTRL_DF_HYST_THRESH_V(e)   BF_POWER_LOOPCTRL_DF_HYST_THRESH(BV_POWER_LOOPCTRL_DF_HYST_THRESH__##e)
+#define BFM_POWER_LOOPCTRL_DF_HYST_THRESH_V(v)  BM_POWER_LOOPCTRL_DF_HYST_THRESH
+#define BP_POWER_LOOPCTRL_RCSCALE_THRESH        14
+#define BM_POWER_LOOPCTRL_RCSCALE_THRESH        0x4000
+#define BF_POWER_LOOPCTRL_RCSCALE_THRESH(v)     (((v) & 0x1) << 14)
+#define BFM_POWER_LOOPCTRL_RCSCALE_THRESH(v)    BM_POWER_LOOPCTRL_RCSCALE_THRESH
+#define BF_POWER_LOOPCTRL_RCSCALE_THRESH_V(e)   BF_POWER_LOOPCTRL_RCSCALE_THRESH(BV_POWER_LOOPCTRL_RCSCALE_THRESH__##e)
+#define BFM_POWER_LOOPCTRL_RCSCALE_THRESH_V(v)  BM_POWER_LOOPCTRL_RCSCALE_THRESH
+#define BP_POWER_LOOPCTRL_EN_RCSCALE            12
+#define BM_POWER_LOOPCTRL_EN_RCSCALE            0x3000
+#define BF_POWER_LOOPCTRL_EN_RCSCALE(v)         (((v) & 0x3) << 12)
+#define BFM_POWER_LOOPCTRL_EN_RCSCALE(v)        BM_POWER_LOOPCTRL_EN_RCSCALE
+#define BF_POWER_LOOPCTRL_EN_RCSCALE_V(e)       BF_POWER_LOOPCTRL_EN_RCSCALE(BV_POWER_LOOPCTRL_EN_RCSCALE__##e)
+#define BFM_POWER_LOOPCTRL_EN_RCSCALE_V(v)      BM_POWER_LOOPCTRL_EN_RCSCALE
+#define BP_POWER_LOOPCTRL_RSRVD2                11
+#define BM_POWER_LOOPCTRL_RSRVD2                0x800
+#define BF_POWER_LOOPCTRL_RSRVD2(v)             (((v) & 0x1) << 11)
+#define BFM_POWER_LOOPCTRL_RSRVD2(v)            BM_POWER_LOOPCTRL_RSRVD2
+#define BF_POWER_LOOPCTRL_RSRVD2_V(e)           BF_POWER_LOOPCTRL_RSRVD2(BV_POWER_LOOPCTRL_RSRVD2__##e)
+#define BFM_POWER_LOOPCTRL_RSRVD2_V(v)          BM_POWER_LOOPCTRL_RSRVD2
+#define BP_POWER_LOOPCTRL_DC_FF                 8
+#define BM_POWER_LOOPCTRL_DC_FF                 0x700
+#define BF_POWER_LOOPCTRL_DC_FF(v)              (((v) & 0x7) << 8)
+#define BFM_POWER_LOOPCTRL_DC_FF(v)             BM_POWER_LOOPCTRL_DC_FF
+#define BF_POWER_LOOPCTRL_DC_FF_V(e)            BF_POWER_LOOPCTRL_DC_FF(BV_POWER_LOOPCTRL_DC_FF__##e)
+#define BFM_POWER_LOOPCTRL_DC_FF_V(v)           BM_POWER_LOOPCTRL_DC_FF
+#define BP_POWER_LOOPCTRL_DC_R                  4
+#define BM_POWER_LOOPCTRL_DC_R                  0xf0
+#define BF_POWER_LOOPCTRL_DC_R(v)               (((v) & 0xf) << 4)
+#define BFM_POWER_LOOPCTRL_DC_R(v)              BM_POWER_LOOPCTRL_DC_R
+#define BF_POWER_LOOPCTRL_DC_R_V(e)             BF_POWER_LOOPCTRL_DC_R(BV_POWER_LOOPCTRL_DC_R__##e)
+#define BFM_POWER_LOOPCTRL_DC_R_V(v)            BM_POWER_LOOPCTRL_DC_R
+#define BP_POWER_LOOPCTRL_RSRVD1                2
+#define BM_POWER_LOOPCTRL_RSRVD1                0xc
+#define BF_POWER_LOOPCTRL_RSRVD1(v)             (((v) & 0x3) << 2)
+#define BFM_POWER_LOOPCTRL_RSRVD1(v)            BM_POWER_LOOPCTRL_RSRVD1
+#define BF_POWER_LOOPCTRL_RSRVD1_V(e)           BF_POWER_LOOPCTRL_RSRVD1(BV_POWER_LOOPCTRL_RSRVD1__##e)
+#define BFM_POWER_LOOPCTRL_RSRVD1_V(v)          BM_POWER_LOOPCTRL_RSRVD1
+#define BP_POWER_LOOPCTRL_DC_C                  0
+#define BM_POWER_LOOPCTRL_DC_C                  0x3
+#define BF_POWER_LOOPCTRL_DC_C(v)               (((v) & 0x3) << 0)
+#define BFM_POWER_LOOPCTRL_DC_C(v)              BM_POWER_LOOPCTRL_DC_C
+#define BF_POWER_LOOPCTRL_DC_C_V(e)             BF_POWER_LOOPCTRL_DC_C(BV_POWER_LOOPCTRL_DC_C__##e)
+#define BFM_POWER_LOOPCTRL_DC_C_V(v)            BM_POWER_LOOPCTRL_DC_C
+
+#define HW_POWER_STS                        HW(POWER_STS)
+#define HWA_POWER_STS                       (0x80044000 + 0xc0)
+#define HWT_POWER_STS                       HWIO_32_RW
+#define HWN_POWER_STS                       POWER_STS
+#define HWI_POWER_STS                       
+#define BP_POWER_STS_RSRVD3                 30
+#define BM_POWER_STS_RSRVD3                 0xc0000000
+#define BF_POWER_STS_RSRVD3(v)              (((v) & 0x3) << 30)
+#define BFM_POWER_STS_RSRVD3(v)             BM_POWER_STS_RSRVD3
+#define BF_POWER_STS_RSRVD3_V(e)            BF_POWER_STS_RSRVD3(BV_POWER_STS_RSRVD3__##e)
+#define BFM_POWER_STS_RSRVD3_V(v)           BM_POWER_STS_RSRVD3
+#define BP_POWER_STS_PWRUP_SOURCE           24
+#define BM_POWER_STS_PWRUP_SOURCE           0x3f000000
+#define BF_POWER_STS_PWRUP_SOURCE(v)        (((v) & 0x3f) << 24)
+#define BFM_POWER_STS_PWRUP_SOURCE(v)       BM_POWER_STS_PWRUP_SOURCE
+#define BF_POWER_STS_PWRUP_SOURCE_V(e)      BF_POWER_STS_PWRUP_SOURCE(BV_POWER_STS_PWRUP_SOURCE__##e)
+#define BFM_POWER_STS_PWRUP_SOURCE_V(v)     BM_POWER_STS_PWRUP_SOURCE
+#define BP_POWER_STS_RSRVD2                 22
+#define BM_POWER_STS_RSRVD2                 0xc00000
+#define BF_POWER_STS_RSRVD2(v)              (((v) & 0x3) << 22)
+#define BFM_POWER_STS_RSRVD2(v)             BM_POWER_STS_RSRVD2
+#define BF_POWER_STS_RSRVD2_V(e)            BF_POWER_STS_RSRVD2(BV_POWER_STS_RSRVD2__##e)
+#define BFM_POWER_STS_RSRVD2_V(v)           BM_POWER_STS_RSRVD2
+#define BP_POWER_STS_PSWITCH                20
+#define BM_POWER_STS_PSWITCH                0x300000
+#define BF_POWER_STS_PSWITCH(v)             (((v) & 0x3) << 20)
+#define BFM_POWER_STS_PSWITCH(v)            BM_POWER_STS_PSWITCH
+#define BF_POWER_STS_PSWITCH_V(e)           BF_POWER_STS_PSWITCH(BV_POWER_STS_PSWITCH__##e)
+#define BFM_POWER_STS_PSWITCH_V(v)          BM_POWER_STS_PSWITCH
+#define BP_POWER_STS_RSRVD1                 18
+#define BM_POWER_STS_RSRVD1                 0xc0000
+#define BF_POWER_STS_RSRVD1(v)              (((v) & 0x3) << 18)
+#define BFM_POWER_STS_RSRVD1(v)             BM_POWER_STS_RSRVD1
+#define BF_POWER_STS_RSRVD1_V(e)            BF_POWER_STS_RSRVD1(BV_POWER_STS_RSRVD1__##e)
+#define BFM_POWER_STS_RSRVD1_V(v)           BM_POWER_STS_RSRVD1
+#define BP_POWER_STS_AVALID_STATUS          17
+#define BM_POWER_STS_AVALID_STATUS          0x20000
+#define BF_POWER_STS_AVALID_STATUS(v)       (((v) & 0x1) << 17)
+#define BFM_POWER_STS_AVALID_STATUS(v)      BM_POWER_STS_AVALID_STATUS
+#define BF_POWER_STS_AVALID_STATUS_V(e)     BF_POWER_STS_AVALID_STATUS(BV_POWER_STS_AVALID_STATUS__##e)
+#define BFM_POWER_STS_AVALID_STATUS_V(v)    BM_POWER_STS_AVALID_STATUS
+#define BP_POWER_STS_BVALID_STATUS          16
+#define BM_POWER_STS_BVALID_STATUS          0x10000
+#define BF_POWER_STS_BVALID_STATUS(v)       (((v) & 0x1) << 16)
+#define BFM_POWER_STS_BVALID_STATUS(v)      BM_POWER_STS_BVALID_STATUS
+#define BF_POWER_STS_BVALID_STATUS_V(e)     BF_POWER_STS_BVALID_STATUS(BV_POWER_STS_BVALID_STATUS__##e)
+#define BFM_POWER_STS_BVALID_STATUS_V(v)    BM_POWER_STS_BVALID_STATUS
+#define BP_POWER_STS_VBUSVALID_STATUS       15
+#define BM_POWER_STS_VBUSVALID_STATUS       0x8000
+#define BF_POWER_STS_VBUSVALID_STATUS(v)    (((v) & 0x1) << 15)
+#define BFM_POWER_STS_VBUSVALID_STATUS(v)   BM_POWER_STS_VBUSVALID_STATUS
+#define BF_POWER_STS_VBUSVALID_STATUS_V(e)  BF_POWER_STS_VBUSVALID_STATUS(BV_POWER_STS_VBUSVALID_STATUS__##e)
+#define BFM_POWER_STS_VBUSVALID_STATUS_V(v) BM_POWER_STS_VBUSVALID_STATUS
+#define BP_POWER_STS_SESSEND_STATUS         14
+#define BM_POWER_STS_SESSEND_STATUS         0x4000
+#define BF_POWER_STS_SESSEND_STATUS(v)      (((v) & 0x1) << 14)
+#define BFM_POWER_STS_SESSEND_STATUS(v)     BM_POWER_STS_SESSEND_STATUS
+#define BF_POWER_STS_SESSEND_STATUS_V(e)    BF_POWER_STS_SESSEND_STATUS(BV_POWER_STS_SESSEND_STATUS__##e)
+#define BFM_POWER_STS_SESSEND_STATUS_V(v)   BM_POWER_STS_SESSEND_STATUS
+#define BP_POWER_STS_BATT_BO                13
+#define BM_POWER_STS_BATT_BO                0x2000
+#define BF_POWER_STS_BATT_BO(v)             (((v) & 0x1) << 13)
+#define BFM_POWER_STS_BATT_BO(v)            BM_POWER_STS_BATT_BO
+#define BF_POWER_STS_BATT_BO_V(e)           BF_POWER_STS_BATT_BO(BV_POWER_STS_BATT_BO__##e)
+#define BFM_POWER_STS_BATT_BO_V(v)          BM_POWER_STS_BATT_BO
+#define BP_POWER_STS_VDD5V_FAULT            12
+#define BM_POWER_STS_VDD5V_FAULT            0x1000
+#define BF_POWER_STS_VDD5V_FAULT(v)         (((v) & 0x1) << 12)
+#define BFM_POWER_STS_VDD5V_FAULT(v)        BM_POWER_STS_VDD5V_FAULT
+#define BF_POWER_STS_VDD5V_FAULT_V(e)       BF_POWER_STS_VDD5V_FAULT(BV_POWER_STS_VDD5V_FAULT__##e)
+#define BFM_POWER_STS_VDD5V_FAULT_V(v)      BM_POWER_STS_VDD5V_FAULT
+#define BP_POWER_STS_CHRGSTS                11
+#define BM_POWER_STS_CHRGSTS                0x800
+#define BF_POWER_STS_CHRGSTS(v)             (((v) & 0x1) << 11)
+#define BFM_POWER_STS_CHRGSTS(v)            BM_POWER_STS_CHRGSTS
+#define BF_POWER_STS_CHRGSTS_V(e)           BF_POWER_STS_CHRGSTS(BV_POWER_STS_CHRGSTS__##e)
+#define BFM_POWER_STS_CHRGSTS_V(v)          BM_POWER_STS_CHRGSTS
+#define BP_POWER_STS_DCDC_4P2_BO            10
+#define BM_POWER_STS_DCDC_4P2_BO            0x400
+#define BF_POWER_STS_DCDC_4P2_BO(v)         (((v) & 0x1) << 10)
+#define BFM_POWER_STS_DCDC_4P2_BO(v)        BM_POWER_STS_DCDC_4P2_BO
+#define BF_POWER_STS_DCDC_4P2_BO_V(e)       BF_POWER_STS_DCDC_4P2_BO(BV_POWER_STS_DCDC_4P2_BO__##e)
+#define BFM_POWER_STS_DCDC_4P2_BO_V(v)      BM_POWER_STS_DCDC_4P2_BO
+#define BP_POWER_STS_DC_OK                  9
+#define BM_POWER_STS_DC_OK                  0x200
+#define BF_POWER_STS_DC_OK(v)               (((v) & 0x1) << 9)
+#define BFM_POWER_STS_DC_OK(v)              BM_POWER_STS_DC_OK
+#define BF_POWER_STS_DC_OK_V(e)             BF_POWER_STS_DC_OK(BV_POWER_STS_DC_OK__##e)
+#define BFM_POWER_STS_DC_OK_V(v)            BM_POWER_STS_DC_OK
+#define BP_POWER_STS_VDDIO_BO               8
+#define BM_POWER_STS_VDDIO_BO               0x100
+#define BF_POWER_STS_VDDIO_BO(v)            (((v) & 0x1) << 8)
+#define BFM_POWER_STS_VDDIO_BO(v)           BM_POWER_STS_VDDIO_BO
+#define BF_POWER_STS_VDDIO_BO_V(e)          BF_POWER_STS_VDDIO_BO(BV_POWER_STS_VDDIO_BO__##e)
+#define BFM_POWER_STS_VDDIO_BO_V(v)         BM_POWER_STS_VDDIO_BO
+#define BP_POWER_STS_VDDA_BO                7
+#define BM_POWER_STS_VDDA_BO                0x80
+#define BF_POWER_STS_VDDA_BO(v)             (((v) & 0x1) << 7)
+#define BFM_POWER_STS_VDDA_BO(v)            BM_POWER_STS_VDDA_BO
+#define BF_POWER_STS_VDDA_BO_V(e)           BF_POWER_STS_VDDA_BO(BV_POWER_STS_VDDA_BO__##e)
+#define BFM_POWER_STS_VDDA_BO_V(v)          BM_POWER_STS_VDDA_BO
+#define BP_POWER_STS_VDDD_BO                6
+#define BM_POWER_STS_VDDD_BO                0x40
+#define BF_POWER_STS_VDDD_BO(v)             (((v) & 0x1) << 6)
+#define BFM_POWER_STS_VDDD_BO(v)            BM_POWER_STS_VDDD_BO
+#define BF_POWER_STS_VDDD_BO_V(e)           BF_POWER_STS_VDDD_BO(BV_POWER_STS_VDDD_BO__##e)
+#define BFM_POWER_STS_VDDD_BO_V(v)          BM_POWER_STS_VDDD_BO
+#define BP_POWER_STS_VDD5V_GT_VDDIO         5
+#define BM_POWER_STS_VDD5V_GT_VDDIO         0x20
+#define BF_POWER_STS_VDD5V_GT_VDDIO(v)      (((v) & 0x1) << 5)
+#define BFM_POWER_STS_VDD5V_GT_VDDIO(v)     BM_POWER_STS_VDD5V_GT_VDDIO
+#define BF_POWER_STS_VDD5V_GT_VDDIO_V(e)    BF_POWER_STS_VDD5V_GT_VDDIO(BV_POWER_STS_VDD5V_GT_VDDIO__##e)
+#define BFM_POWER_STS_VDD5V_GT_VDDIO_V(v)   BM_POWER_STS_VDD5V_GT_VDDIO
+#define BP_POWER_STS_VDD5V_DROOP            4
+#define BM_POWER_STS_VDD5V_DROOP            0x10
+#define BF_POWER_STS_VDD5V_DROOP(v)         (((v) & 0x1) << 4)
+#define BFM_POWER_STS_VDD5V_DROOP(v)        BM_POWER_STS_VDD5V_DROOP
+#define BF_POWER_STS_VDD5V_DROOP_V(e)       BF_POWER_STS_VDD5V_DROOP(BV_POWER_STS_VDD5V_DROOP__##e)
+#define BFM_POWER_STS_VDD5V_DROOP_V(v)      BM_POWER_STS_VDD5V_DROOP
+#define BP_POWER_STS_AVALID                 3
+#define BM_POWER_STS_AVALID                 0x8
+#define BF_POWER_STS_AVALID(v)              (((v) & 0x1) << 3)
+#define BFM_POWER_STS_AVALID(v)             BM_POWER_STS_AVALID
+#define BF_POWER_STS_AVALID_V(e)            BF_POWER_STS_AVALID(BV_POWER_STS_AVALID__##e)
+#define BFM_POWER_STS_AVALID_V(v)           BM_POWER_STS_AVALID
+#define BP_POWER_STS_BVALID                 2
+#define BM_POWER_STS_BVALID                 0x4
+#define BF_POWER_STS_BVALID(v)              (((v) & 0x1) << 2)
+#define BFM_POWER_STS_BVALID(v)             BM_POWER_STS_BVALID
+#define BF_POWER_STS_BVALID_V(e)            BF_POWER_STS_BVALID(BV_POWER_STS_BVALID__##e)
+#define BFM_POWER_STS_BVALID_V(v)           BM_POWER_STS_BVALID
+#define BP_POWER_STS_VBUSVALID              1
+#define BM_POWER_STS_VBUSVALID              0x2
+#define BF_POWER_STS_VBUSVALID(v)           (((v) & 0x1) << 1)
+#define BFM_POWER_STS_VBUSVALID(v)          BM_POWER_STS_VBUSVALID
+#define BF_POWER_STS_VBUSVALID_V(e)         BF_POWER_STS_VBUSVALID(BV_POWER_STS_VBUSVALID__##e)
+#define BFM_POWER_STS_VBUSVALID_V(v)        BM_POWER_STS_VBUSVALID
+#define BP_POWER_STS_SESSEND                0
+#define BM_POWER_STS_SESSEND                0x1
+#define BF_POWER_STS_SESSEND(v)             (((v) & 0x1) << 0)
+#define BFM_POWER_STS_SESSEND(v)            BM_POWER_STS_SESSEND
+#define BF_POWER_STS_SESSEND_V(e)           BF_POWER_STS_SESSEND(BV_POWER_STS_SESSEND__##e)
+#define BFM_POWER_STS_SESSEND_V(v)          BM_POWER_STS_SESSEND
+
+#define HW_POWER_SPEED              HW(POWER_SPEED)
+#define HWA_POWER_SPEED             (0x80044000 + 0xd0)
+#define HWT_POWER_SPEED             HWIO_32_RW
+#define HWN_POWER_SPEED             POWER_SPEED
+#define HWI_POWER_SPEED             
+#define HW_POWER_SPEED_SET          HW(POWER_SPEED_SET)
+#define HWA_POWER_SPEED_SET         (HWA_POWER_SPEED + 0x4)
+#define HWT_POWER_SPEED_SET         HWIO_32_WO
+#define HWN_POWER_SPEED_SET         POWER_SPEED
+#define HWI_POWER_SPEED_SET         
+#define HW_POWER_SPEED_CLR          HW(POWER_SPEED_CLR)
+#define HWA_POWER_SPEED_CLR         (HWA_POWER_SPEED + 0x8)
+#define HWT_POWER_SPEED_CLR         HWIO_32_WO
+#define HWN_POWER_SPEED_CLR         POWER_SPEED
+#define HWI_POWER_SPEED_CLR         
+#define HW_POWER_SPEED_TOG          HW(POWER_SPEED_TOG)
+#define HWA_POWER_SPEED_TOG         (HWA_POWER_SPEED + 0xc)
+#define HWT_POWER_SPEED_TOG         HWIO_32_WO
+#define HWN_POWER_SPEED_TOG         POWER_SPEED
+#define HWI_POWER_SPEED_TOG         
+#define BP_POWER_SPEED_RSRVD1       24
+#define BM_POWER_SPEED_RSRVD1       0xff000000
+#define BF_POWER_SPEED_RSRVD1(v)    (((v) & 0xff) << 24)
+#define BFM_POWER_SPEED_RSRVD1(v)   BM_POWER_SPEED_RSRVD1
+#define BF_POWER_SPEED_RSRVD1_V(e)  BF_POWER_SPEED_RSRVD1(BV_POWER_SPEED_RSRVD1__##e)
+#define BFM_POWER_SPEED_RSRVD1_V(v) BM_POWER_SPEED_RSRVD1
+#define BP_POWER_SPEED_STATUS       16
+#define BM_POWER_SPEED_STATUS       0xff0000
+#define BF_POWER_SPEED_STATUS(v)    (((v) & 0xff) << 16)
+#define BFM_POWER_SPEED_STATUS(v)   BM_POWER_SPEED_STATUS
+#define BF_POWER_SPEED_STATUS_V(e)  BF_POWER_SPEED_STATUS(BV_POWER_SPEED_STATUS__##e)
+#define BFM_POWER_SPEED_STATUS_V(v) BM_POWER_SPEED_STATUS
+#define BP_POWER_SPEED_RSRVD0       2
+#define BM_POWER_SPEED_RSRVD0       0xfffc
+#define BF_POWER_SPEED_RSRVD0(v)    (((v) & 0x3fff) << 2)
+#define BFM_POWER_SPEED_RSRVD0(v)   BM_POWER_SPEED_RSRVD0
+#define BF_POWER_SPEED_RSRVD0_V(e)  BF_POWER_SPEED_RSRVD0(BV_POWER_SPEED_RSRVD0__##e)
+#define BFM_POWER_SPEED_RSRVD0_V(v) BM_POWER_SPEED_RSRVD0
+#define BP_POWER_SPEED_CTRL         0
+#define BM_POWER_SPEED_CTRL         0x3
+#define BF_POWER_SPEED_CTRL(v)      (((v) & 0x3) << 0)
+#define BFM_POWER_SPEED_CTRL(v)     BM_POWER_SPEED_CTRL
+#define BF_POWER_SPEED_CTRL_V(e)    BF_POWER_SPEED_CTRL(BV_POWER_SPEED_CTRL__##e)
+#define BFM_POWER_SPEED_CTRL_V(v)   BM_POWER_SPEED_CTRL
+
+#define HW_POWER_BATTMONITOR                        HW(POWER_BATTMONITOR)
+#define HWA_POWER_BATTMONITOR                       (0x80044000 + 0xe0)
+#define HWT_POWER_BATTMONITOR                       HWIO_32_RW
+#define HWN_POWER_BATTMONITOR                       POWER_BATTMONITOR
+#define HWI_POWER_BATTMONITOR                       
+#define BP_POWER_BATTMONITOR_RSRVD3                 26
+#define BM_POWER_BATTMONITOR_RSRVD3                 0xfc000000
+#define BF_POWER_BATTMONITOR_RSRVD3(v)              (((v) & 0x3f) << 26)
+#define BFM_POWER_BATTMONITOR_RSRVD3(v)             BM_POWER_BATTMONITOR_RSRVD3
+#define BF_POWER_BATTMONITOR_RSRVD3_V(e)            BF_POWER_BATTMONITOR_RSRVD3(BV_POWER_BATTMONITOR_RSRVD3__##e)
+#define BFM_POWER_BATTMONITOR_RSRVD3_V(v)           BM_POWER_BATTMONITOR_RSRVD3
+#define BP_POWER_BATTMONITOR_BATT_VAL               16
+#define BM_POWER_BATTMONITOR_BATT_VAL               0x3ff0000
+#define BF_POWER_BATTMONITOR_BATT_VAL(v)            (((v) & 0x3ff) << 16)
+#define BFM_POWER_BATTMONITOR_BATT_VAL(v)           BM_POWER_BATTMONITOR_BATT_VAL
+#define BF_POWER_BATTMONITOR_BATT_VAL_V(e)          BF_POWER_BATTMONITOR_BATT_VAL(BV_POWER_BATTMONITOR_BATT_VAL__##e)
+#define BFM_POWER_BATTMONITOR_BATT_VAL_V(v)         BM_POWER_BATTMONITOR_BATT_VAL
+#define BP_POWER_BATTMONITOR_RSRVD2                 11
+#define BM_POWER_BATTMONITOR_RSRVD2                 0xf800
+#define BF_POWER_BATTMONITOR_RSRVD2(v)              (((v) & 0x1f) << 11)
+#define BFM_POWER_BATTMONITOR_RSRVD2(v)             BM_POWER_BATTMONITOR_RSRVD2
+#define BF_POWER_BATTMONITOR_RSRVD2_V(e)            BF_POWER_BATTMONITOR_RSRVD2(BV_POWER_BATTMONITOR_RSRVD2__##e)
+#define BFM_POWER_BATTMONITOR_RSRVD2_V(v)           BM_POWER_BATTMONITOR_RSRVD2
+#define BP_POWER_BATTMONITOR_EN_BATADJ              10
+#define BM_POWER_BATTMONITOR_EN_BATADJ              0x400
+#define BF_POWER_BATTMONITOR_EN_BATADJ(v)           (((v) & 0x1) << 10)
+#define BFM_POWER_BATTMONITOR_EN_BATADJ(v)          BM_POWER_BATTMONITOR_EN_BATADJ
+#define BF_POWER_BATTMONITOR_EN_BATADJ_V(e)         BF_POWER_BATTMONITOR_EN_BATADJ(BV_POWER_BATTMONITOR_EN_BATADJ__##e)
+#define BFM_POWER_BATTMONITOR_EN_BATADJ_V(v)        BM_POWER_BATTMONITOR_EN_BATADJ
+#define BP_POWER_BATTMONITOR_PWDN_BATTBRNOUT        9
+#define BM_POWER_BATTMONITOR_PWDN_BATTBRNOUT        0x200
+#define BF_POWER_BATTMONITOR_PWDN_BATTBRNOUT(v)     (((v) & 0x1) << 9)
+#define BFM_POWER_BATTMONITOR_PWDN_BATTBRNOUT(v)    BM_POWER_BATTMONITOR_PWDN_BATTBRNOUT
+#define BF_POWER_BATTMONITOR_PWDN_BATTBRNOUT_V(e)   BF_POWER_BATTMONITOR_PWDN_BATTBRNOUT(BV_POWER_BATTMONITOR_PWDN_BATTBRNOUT__##e)
+#define BFM_POWER_BATTMONITOR_PWDN_BATTBRNOUT_V(v)  BM_POWER_BATTMONITOR_PWDN_BATTBRNOUT
+#define BP_POWER_BATTMONITOR_BRWNOUT_PWD            8
+#define BM_POWER_BATTMONITOR_BRWNOUT_PWD            0x100
+#define BF_POWER_BATTMONITOR_BRWNOUT_PWD(v)         (((v) & 0x1) << 8)
+#define BFM_POWER_BATTMONITOR_BRWNOUT_PWD(v)        BM_POWER_BATTMONITOR_BRWNOUT_PWD
+#define BF_POWER_BATTMONITOR_BRWNOUT_PWD_V(e)       BF_POWER_BATTMONITOR_BRWNOUT_PWD(BV_POWER_BATTMONITOR_BRWNOUT_PWD__##e)
+#define BFM_POWER_BATTMONITOR_BRWNOUT_PWD_V(v)      BM_POWER_BATTMONITOR_BRWNOUT_PWD
+#define BP_POWER_BATTMONITOR_RSRVD1                 5
+#define BM_POWER_BATTMONITOR_RSRVD1                 0xe0
+#define BF_POWER_BATTMONITOR_RSRVD1(v)              (((v) & 0x7) << 5)
+#define BFM_POWER_BATTMONITOR_RSRVD1(v)             BM_POWER_BATTMONITOR_RSRVD1
+#define BF_POWER_BATTMONITOR_RSRVD1_V(e)            BF_POWER_BATTMONITOR_RSRVD1(BV_POWER_BATTMONITOR_RSRVD1__##e)
+#define BFM_POWER_BATTMONITOR_RSRVD1_V(v)           BM_POWER_BATTMONITOR_RSRVD1
+#define BP_POWER_BATTMONITOR_BRWNOUT_LVL            0
+#define BM_POWER_BATTMONITOR_BRWNOUT_LVL            0x1f
+#define BF_POWER_BATTMONITOR_BRWNOUT_LVL(v)         (((v) & 0x1f) << 0)
+#define BFM_POWER_BATTMONITOR_BRWNOUT_LVL(v)        BM_POWER_BATTMONITOR_BRWNOUT_LVL
+#define BF_POWER_BATTMONITOR_BRWNOUT_LVL_V(e)       BF_POWER_BATTMONITOR_BRWNOUT_LVL(BV_POWER_BATTMONITOR_BRWNOUT_LVL__##e)
+#define BFM_POWER_BATTMONITOR_BRWNOUT_LVL_V(v)      BM_POWER_BATTMONITOR_BRWNOUT_LVL
+
+#define HW_POWER_RESET                  HW(POWER_RESET)
+#define HWA_POWER_RESET                 (0x80044000 + 0x100)
+#define HWT_POWER_RESET                 HWIO_32_RW
+#define HWN_POWER_RESET                 POWER_RESET
+#define HWI_POWER_RESET                 
+#define HW_POWER_RESET_SET              HW(POWER_RESET_SET)
+#define HWA_POWER_RESET_SET             (HWA_POWER_RESET + 0x4)
+#define HWT_POWER_RESET_SET             HWIO_32_WO
+#define HWN_POWER_RESET_SET             POWER_RESET
+#define HWI_POWER_RESET_SET             
+#define HW_POWER_RESET_CLR              HW(POWER_RESET_CLR)
+#define HWA_POWER_RESET_CLR             (HWA_POWER_RESET + 0x8)
+#define HWT_POWER_RESET_CLR             HWIO_32_WO
+#define HWN_POWER_RESET_CLR             POWER_RESET
+#define HWI_POWER_RESET_CLR             
+#define HW_POWER_RESET_TOG              HW(POWER_RESET_TOG)
+#define HWA_POWER_RESET_TOG             (HWA_POWER_RESET + 0xc)
+#define HWT_POWER_RESET_TOG             HWIO_32_WO
+#define HWN_POWER_RESET_TOG             POWER_RESET
+#define HWI_POWER_RESET_TOG             
+#define BP_POWER_RESET_UNLOCK           16
+#define BM_POWER_RESET_UNLOCK           0xffff0000
+#define BV_POWER_RESET_UNLOCK__KEY      0x3e77
+#define BF_POWER_RESET_UNLOCK(v)        (((v) & 0xffff) << 16)
+#define BFM_POWER_RESET_UNLOCK(v)       BM_POWER_RESET_UNLOCK
+#define BF_POWER_RESET_UNLOCK_V(e)      BF_POWER_RESET_UNLOCK(BV_POWER_RESET_UNLOCK__##e)
+#define BFM_POWER_RESET_UNLOCK_V(v)     BM_POWER_RESET_UNLOCK
+#define BP_POWER_RESET_RSRVD1           2
+#define BM_POWER_RESET_RSRVD1           0xfffc
+#define BF_POWER_RESET_RSRVD1(v)        (((v) & 0x3fff) << 2)
+#define BFM_POWER_RESET_RSRVD1(v)       BM_POWER_RESET_RSRVD1
+#define BF_POWER_RESET_RSRVD1_V(e)      BF_POWER_RESET_RSRVD1(BV_POWER_RESET_RSRVD1__##e)
+#define BFM_POWER_RESET_RSRVD1_V(v)     BM_POWER_RESET_RSRVD1
+#define BP_POWER_RESET_PWD_OFF          1
+#define BM_POWER_RESET_PWD_OFF          0x2
+#define BF_POWER_RESET_PWD_OFF(v)       (((v) & 0x1) << 1)
+#define BFM_POWER_RESET_PWD_OFF(v)      BM_POWER_RESET_PWD_OFF
+#define BF_POWER_RESET_PWD_OFF_V(e)     BF_POWER_RESET_PWD_OFF(BV_POWER_RESET_PWD_OFF__##e)
+#define BFM_POWER_RESET_PWD_OFF_V(v)    BM_POWER_RESET_PWD_OFF
+#define BP_POWER_RESET_PWD              0
+#define BM_POWER_RESET_PWD              0x1
+#define BF_POWER_RESET_PWD(v)           (((v) & 0x1) << 0)
+#define BFM_POWER_RESET_PWD(v)          BM_POWER_RESET_PWD
+#define BF_POWER_RESET_PWD_V(e)         BF_POWER_RESET_PWD(BV_POWER_RESET_PWD__##e)
+#define BFM_POWER_RESET_PWD_V(v)        BM_POWER_RESET_PWD
+
+#define HW_POWER_DEBUG                          HW(POWER_DEBUG)
+#define HWA_POWER_DEBUG                         (0x80044000 + 0x110)
+#define HWT_POWER_DEBUG                         HWIO_32_RW
+#define HWN_POWER_DEBUG                         POWER_DEBUG
+#define HWI_POWER_DEBUG                         
+#define HW_POWER_DEBUG_SET                      HW(POWER_DEBUG_SET)
+#define HWA_POWER_DEBUG_SET                     (HWA_POWER_DEBUG + 0x4)
+#define HWT_POWER_DEBUG_SET                     HWIO_32_WO
+#define HWN_POWER_DEBUG_SET                     POWER_DEBUG
+#define HWI_POWER_DEBUG_SET                     
+#define HW_POWER_DEBUG_CLR                      HW(POWER_DEBUG_CLR)
+#define HWA_POWER_DEBUG_CLR                     (HWA_POWER_DEBUG + 0x8)
+#define HWT_POWER_DEBUG_CLR                     HWIO_32_WO
+#define HWN_POWER_DEBUG_CLR                     POWER_DEBUG
+#define HWI_POWER_DEBUG_CLR                     
+#define HW_POWER_DEBUG_TOG                      HW(POWER_DEBUG_TOG)
+#define HWA_POWER_DEBUG_TOG                     (HWA_POWER_DEBUG + 0xc)
+#define HWT_POWER_DEBUG_TOG                     HWIO_32_WO
+#define HWN_POWER_DEBUG_TOG                     POWER_DEBUG
+#define HWI_POWER_DEBUG_TOG                     
+#define BP_POWER_DEBUG_RSRVD0                   4
+#define BM_POWER_DEBUG_RSRVD0                   0xfffffff0
+#define BF_POWER_DEBUG_RSRVD0(v)                (((v) & 0xfffffff) << 4)
+#define BFM_POWER_DEBUG_RSRVD0(v)               BM_POWER_DEBUG_RSRVD0
+#define BF_POWER_DEBUG_RSRVD0_V(e)              BF_POWER_DEBUG_RSRVD0(BV_POWER_DEBUG_RSRVD0__##e)
+#define BFM_POWER_DEBUG_RSRVD0_V(v)             BM_POWER_DEBUG_RSRVD0
+#define BP_POWER_DEBUG_VBUSVALIDPIOLOCK         3
+#define BM_POWER_DEBUG_VBUSVALIDPIOLOCK         0x8
+#define BF_POWER_DEBUG_VBUSVALIDPIOLOCK(v)      (((v) & 0x1) << 3)
+#define BFM_POWER_DEBUG_VBUSVALIDPIOLOCK(v)     BM_POWER_DEBUG_VBUSVALIDPIOLOCK
+#define BF_POWER_DEBUG_VBUSVALIDPIOLOCK_V(e)    BF_POWER_DEBUG_VBUSVALIDPIOLOCK(BV_POWER_DEBUG_VBUSVALIDPIOLOCK__##e)
+#define BFM_POWER_DEBUG_VBUSVALIDPIOLOCK_V(v)   BM_POWER_DEBUG_VBUSVALIDPIOLOCK
+#define BP_POWER_DEBUG_AVALIDPIOLOCK            2
+#define BM_POWER_DEBUG_AVALIDPIOLOCK            0x4
+#define BF_POWER_DEBUG_AVALIDPIOLOCK(v)         (((v) & 0x1) << 2)
+#define BFM_POWER_DEBUG_AVALIDPIOLOCK(v)        BM_POWER_DEBUG_AVALIDPIOLOCK
+#define BF_POWER_DEBUG_AVALIDPIOLOCK_V(e)       BF_POWER_DEBUG_AVALIDPIOLOCK(BV_POWER_DEBUG_AVALIDPIOLOCK__##e)
+#define BFM_POWER_DEBUG_AVALIDPIOLOCK_V(v)      BM_POWER_DEBUG_AVALIDPIOLOCK
+#define BP_POWER_DEBUG_BVALIDPIOLOCK            1
+#define BM_POWER_DEBUG_BVALIDPIOLOCK            0x2
+#define BF_POWER_DEBUG_BVALIDPIOLOCK(v)         (((v) & 0x1) << 1)
+#define BFM_POWER_DEBUG_BVALIDPIOLOCK(v)        BM_POWER_DEBUG_BVALIDPIOLOCK
+#define BF_POWER_DEBUG_BVALIDPIOLOCK_V(e)       BF_POWER_DEBUG_BVALIDPIOLOCK(BV_POWER_DEBUG_BVALIDPIOLOCK__##e)
+#define BFM_POWER_DEBUG_BVALIDPIOLOCK_V(v)      BM_POWER_DEBUG_BVALIDPIOLOCK
+#define BP_POWER_DEBUG_SESSENDPIOLOCK           0
+#define BM_POWER_DEBUG_SESSENDPIOLOCK           0x1
+#define BF_POWER_DEBUG_SESSENDPIOLOCK(v)        (((v) & 0x1) << 0)
+#define BFM_POWER_DEBUG_SESSENDPIOLOCK(v)       BM_POWER_DEBUG_SESSENDPIOLOCK
+#define BF_POWER_DEBUG_SESSENDPIOLOCK_V(e)      BF_POWER_DEBUG_SESSENDPIOLOCK(BV_POWER_DEBUG_SESSENDPIOLOCK__##e)
+#define BFM_POWER_DEBUG_SESSENDPIOLOCK_V(v)     BM_POWER_DEBUG_SESSENDPIOLOCK
+
+#define HW_POWER_SPECIAL            HW(POWER_SPECIAL)
+#define HWA_POWER_SPECIAL           (0x80044000 + 0x120)
+#define HWT_POWER_SPECIAL           HWIO_32_RW
+#define HWN_POWER_SPECIAL           POWER_SPECIAL
+#define HWI_POWER_SPECIAL           
+#define HW_POWER_SPECIAL_SET        HW(POWER_SPECIAL_SET)
+#define HWA_POWER_SPECIAL_SET       (HWA_POWER_SPECIAL + 0x4)
+#define HWT_POWER_SPECIAL_SET       HWIO_32_WO
+#define HWN_POWER_SPECIAL_SET       POWER_SPECIAL
+#define HWI_POWER_SPECIAL_SET       
+#define HW_POWER_SPECIAL_CLR        HW(POWER_SPECIAL_CLR)
+#define HWA_POWER_SPECIAL_CLR       (HWA_POWER_SPECIAL + 0x8)
+#define HWT_POWER_SPECIAL_CLR       HWIO_32_WO
+#define HWN_POWER_SPECIAL_CLR       POWER_SPECIAL
+#define HWI_POWER_SPECIAL_CLR       
+#define HW_POWER_SPECIAL_TOG        HW(POWER_SPECIAL_TOG)
+#define HWA_POWER_SPECIAL_TOG       (HWA_POWER_SPECIAL + 0xc)
+#define HWT_POWER_SPECIAL_TOG       HWIO_32_WO
+#define HWN_POWER_SPECIAL_TOG       POWER_SPECIAL
+#define HWI_POWER_SPECIAL_TOG       
+#define BP_POWER_SPECIAL_TEST       0
+#define BM_POWER_SPECIAL_TEST       0xffffffff
+#define BF_POWER_SPECIAL_TEST(v)    (((v) & 0xffffffff) << 0)
+#define BFM_POWER_SPECIAL_TEST(v)   BM_POWER_SPECIAL_TEST
+#define BF_POWER_SPECIAL_TEST_V(e)  BF_POWER_SPECIAL_TEST(BV_POWER_SPECIAL_TEST__##e)
+#define BFM_POWER_SPECIAL_TEST_V(v) BM_POWER_SPECIAL_TEST
+
+#define HW_POWER_VERSION                HW(POWER_VERSION)
+#define HWA_POWER_VERSION               (0x80044000 + 0x130)
+#define HWT_POWER_VERSION               HWIO_32_RW
+#define HWN_POWER_VERSION               POWER_VERSION
+#define HWI_POWER_VERSION               
+#define BP_POWER_VERSION_MAJOR          24
+#define BM_POWER_VERSION_MAJOR          0xff000000
+#define BF_POWER_VERSION_MAJOR(v)       (((v) & 0xff) << 24)
+#define BFM_POWER_VERSION_MAJOR(v)      BM_POWER_VERSION_MAJOR
+#define BF_POWER_VERSION_MAJOR_V(e)     BF_POWER_VERSION_MAJOR(BV_POWER_VERSION_MAJOR__##e)
+#define BFM_POWER_VERSION_MAJOR_V(v)    BM_POWER_VERSION_MAJOR
+#define BP_POWER_VERSION_MINOR          16
+#define BM_POWER_VERSION_MINOR          0xff0000
+#define BF_POWER_VERSION_MINOR(v)       (((v) & 0xff) << 16)
+#define BFM_POWER_VERSION_MINOR(v)      BM_POWER_VERSION_MINOR
+#define BF_POWER_VERSION_MINOR_V(e)     BF_POWER_VERSION_MINOR(BV_POWER_VERSION_MINOR__##e)
+#define BFM_POWER_VERSION_MINOR_V(v)    BM_POWER_VERSION_MINOR
+#define BP_POWER_VERSION_STEP           0
+#define BM_POWER_VERSION_STEP           0xffff
+#define BF_POWER_VERSION_STEP(v)        (((v) & 0xffff) << 0)
+#define BFM_POWER_VERSION_STEP(v)       BM_POWER_VERSION_STEP
+#define BF_POWER_VERSION_STEP_V(e)      BF_POWER_VERSION_STEP(BV_POWER_VERSION_STEP__##e)
+#define BFM_POWER_VERSION_STEP_V(v)     BM_POWER_VERSION_STEP
+
+#endif /* __HEADERGEN_IMX233_POWER_H__*/
diff --git a/firmware/target/arm/imx233/regs/imx233/pwm.h b/firmware/target/arm/imx233/regs/imx233/pwm.h
new file mode 100644
index 0000000000..3a406b1a2c
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/imx233/pwm.h
@@ -0,0 +1,272 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * imx233 version: 2.4.0
+ * imx233 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_IMX233_PWM_H__
+#define __HEADERGEN_IMX233_PWM_H__
+
+#define HW_PWM_CTRL                             HW(PWM_CTRL)
+#define HWA_PWM_CTRL                            (0x80064000 + 0x0)
+#define HWT_PWM_CTRL                            HWIO_32_RW
+#define HWN_PWM_CTRL                            PWM_CTRL
+#define HWI_PWM_CTRL                            
+#define HW_PWM_CTRL_SET                         HW(PWM_CTRL_SET)
+#define HWA_PWM_CTRL_SET                        (HWA_PWM_CTRL + 0x4)
+#define HWT_PWM_CTRL_SET                        HWIO_32_WO
+#define HWN_PWM_CTRL_SET                        PWM_CTRL
+#define HWI_PWM_CTRL_SET                        
+#define HW_PWM_CTRL_CLR                         HW(PWM_CTRL_CLR)
+#define HWA_PWM_CTRL_CLR                        (HWA_PWM_CTRL + 0x8)
+#define HWT_PWM_CTRL_CLR                        HWIO_32_WO
+#define HWN_PWM_CTRL_CLR                        PWM_CTRL
+#define HWI_PWM_CTRL_CLR                        
+#define HW_PWM_CTRL_TOG                         HW(PWM_CTRL_TOG)
+#define HWA_PWM_CTRL_TOG                        (HWA_PWM_CTRL + 0xc)
+#define HWT_PWM_CTRL_TOG                        HWIO_32_WO
+#define HWN_PWM_CTRL_TOG                        PWM_CTRL
+#define HWI_PWM_CTRL_TOG                        
+#define BP_PWM_CTRL_SFTRST                      31
+#define BM_PWM_CTRL_SFTRST                      0x80000000
+#define BF_PWM_CTRL_SFTRST(v)                   (((v) & 0x1) << 31)
+#define BFM_PWM_CTRL_SFTRST(v)                  BM_PWM_CTRL_SFTRST
+#define BF_PWM_CTRL_SFTRST_V(e)                 BF_PWM_CTRL_SFTRST(BV_PWM_CTRL_SFTRST__##e)
+#define BFM_PWM_CTRL_SFTRST_V(v)                BM_PWM_CTRL_SFTRST
+#define BP_PWM_CTRL_CLKGATE                     30
+#define BM_PWM_CTRL_CLKGATE                     0x40000000
+#define BF_PWM_CTRL_CLKGATE(v)                  (((v) & 0x1) << 30)
+#define BFM_PWM_CTRL_CLKGATE(v)                 BM_PWM_CTRL_CLKGATE
+#define BF_PWM_CTRL_CLKGATE_V(e)                BF_PWM_CTRL_CLKGATE(BV_PWM_CTRL_CLKGATE__##e)
+#define BFM_PWM_CTRL_CLKGATE_V(v)               BM_PWM_CTRL_CLKGATE
+#define BP_PWM_CTRL_PWM4_PRESENT                29
+#define BM_PWM_CTRL_PWM4_PRESENT                0x20000000
+#define BF_PWM_CTRL_PWM4_PRESENT(v)             (((v) & 0x1) << 29)
+#define BFM_PWM_CTRL_PWM4_PRESENT(v)            BM_PWM_CTRL_PWM4_PRESENT
+#define BF_PWM_CTRL_PWM4_PRESENT_V(e)           BF_PWM_CTRL_PWM4_PRESENT(BV_PWM_CTRL_PWM4_PRESENT__##e)
+#define BFM_PWM_CTRL_PWM4_PRESENT_V(v)          BM_PWM_CTRL_PWM4_PRESENT
+#define BP_PWM_CTRL_PWM3_PRESENT                28
+#define BM_PWM_CTRL_PWM3_PRESENT                0x10000000
+#define BF_PWM_CTRL_PWM3_PRESENT(v)             (((v) & 0x1) << 28)
+#define BFM_PWM_CTRL_PWM3_PRESENT(v)            BM_PWM_CTRL_PWM3_PRESENT
+#define BF_PWM_CTRL_PWM3_PRESENT_V(e)           BF_PWM_CTRL_PWM3_PRESENT(BV_PWM_CTRL_PWM3_PRESENT__##e)
+#define BFM_PWM_CTRL_PWM3_PRESENT_V(v)          BM_PWM_CTRL_PWM3_PRESENT
+#define BP_PWM_CTRL_PWM2_PRESENT                27
+#define BM_PWM_CTRL_PWM2_PRESENT                0x8000000
+#define BF_PWM_CTRL_PWM2_PRESENT(v)             (((v) & 0x1) << 27)
+#define BFM_PWM_CTRL_PWM2_PRESENT(v)            BM_PWM_CTRL_PWM2_PRESENT
+#define BF_PWM_CTRL_PWM2_PRESENT_V(e)           BF_PWM_CTRL_PWM2_PRESENT(BV_PWM_CTRL_PWM2_PRESENT__##e)
+#define BFM_PWM_CTRL_PWM2_PRESENT_V(v)          BM_PWM_CTRL_PWM2_PRESENT
+#define BP_PWM_CTRL_PWM1_PRESENT                26
+#define BM_PWM_CTRL_PWM1_PRESENT                0x4000000
+#define BF_PWM_CTRL_PWM1_PRESENT(v)             (((v) & 0x1) << 26)
+#define BFM_PWM_CTRL_PWM1_PRESENT(v)            BM_PWM_CTRL_PWM1_PRESENT
+#define BF_PWM_CTRL_PWM1_PRESENT_V(e)           BF_PWM_CTRL_PWM1_PRESENT(BV_PWM_CTRL_PWM1_PRESENT__##e)
+#define BFM_PWM_CTRL_PWM1_PRESENT_V(v)          BM_PWM_CTRL_PWM1_PRESENT
+#define BP_PWM_CTRL_PWM0_PRESENT                25
+#define BM_PWM_CTRL_PWM0_PRESENT                0x2000000
+#define BF_PWM_CTRL_PWM0_PRESENT(v)             (((v) & 0x1) << 25)
+#define BFM_PWM_CTRL_PWM0_PRESENT(v)            BM_PWM_CTRL_PWM0_PRESENT
+#define BF_PWM_CTRL_PWM0_PRESENT_V(e)           BF_PWM_CTRL_PWM0_PRESENT(BV_PWM_CTRL_PWM0_PRESENT__##e)
+#define BFM_PWM_CTRL_PWM0_PRESENT_V(v)          BM_PWM_CTRL_PWM0_PRESENT
+#define BP_PWM_CTRL_RSRVD1                      7
+#define BM_PWM_CTRL_RSRVD1                      0x1ffff80
+#define BF_PWM_CTRL_RSRVD1(v)                   (((v) & 0x3ffff) << 7)
+#define BFM_PWM_CTRL_RSRVD1(v)                  BM_PWM_CTRL_RSRVD1
+#define BF_PWM_CTRL_RSRVD1_V(e)                 BF_PWM_CTRL_RSRVD1(BV_PWM_CTRL_RSRVD1__##e)
+#define BFM_PWM_CTRL_RSRVD1_V(v)                BM_PWM_CTRL_RSRVD1
+#define BP_PWM_CTRL_OUTPUT_CUTOFF_EN            6
+#define BM_PWM_CTRL_OUTPUT_CUTOFF_EN            0x40
+#define BF_PWM_CTRL_OUTPUT_CUTOFF_EN(v)         (((v) & 0x1) << 6)
+#define BFM_PWM_CTRL_OUTPUT_CUTOFF_EN(v)        BM_PWM_CTRL_OUTPUT_CUTOFF_EN
+#define BF_PWM_CTRL_OUTPUT_CUTOFF_EN_V(e)       BF_PWM_CTRL_OUTPUT_CUTOFF_EN(BV_PWM_CTRL_OUTPUT_CUTOFF_EN__##e)
+#define BFM_PWM_CTRL_OUTPUT_CUTOFF_EN_V(v)      BM_PWM_CTRL_OUTPUT_CUTOFF_EN
+#define BP_PWM_CTRL_PWM2_ANA_CTRL_ENABLE        5
+#define BM_PWM_CTRL_PWM2_ANA_CTRL_ENABLE        0x20
+#define BF_PWM_CTRL_PWM2_ANA_CTRL_ENABLE(v)     (((v) & 0x1) << 5)
+#define BFM_PWM_CTRL_PWM2_ANA_CTRL_ENABLE(v)    BM_PWM_CTRL_PWM2_ANA_CTRL_ENABLE
+#define BF_PWM_CTRL_PWM2_ANA_CTRL_ENABLE_V(e)   BF_PWM_CTRL_PWM2_ANA_CTRL_ENABLE(BV_PWM_CTRL_PWM2_ANA_CTRL_ENABLE__##e)
+#define BFM_PWM_CTRL_PWM2_ANA_CTRL_ENABLE_V(v)  BM_PWM_CTRL_PWM2_ANA_CTRL_ENABLE
+#define BP_PWM_CTRL_PWM4_ENABLE                 4
+#define BM_PWM_CTRL_PWM4_ENABLE                 0x10
+#define BF_PWM_CTRL_PWM4_ENABLE(v)              (((v) & 0x1) << 4)
+#define BFM_PWM_CTRL_PWM4_ENABLE(v)             BM_PWM_CTRL_PWM4_ENABLE
+#define BF_PWM_CTRL_PWM4_ENABLE_V(e)            BF_PWM_CTRL_PWM4_ENABLE(BV_PWM_CTRL_PWM4_ENABLE__##e)
+#define BFM_PWM_CTRL_PWM4_ENABLE_V(v)           BM_PWM_CTRL_PWM4_ENABLE
+#define BP_PWM_CTRL_PWM3_ENABLE                 3
+#define BM_PWM_CTRL_PWM3_ENABLE                 0x8
+#define BF_PWM_CTRL_PWM3_ENABLE(v)              (((v) & 0x1) << 3)
+#define BFM_PWM_CTRL_PWM3_ENABLE(v)             BM_PWM_CTRL_PWM3_ENABLE
+#define BF_PWM_CTRL_PWM3_ENABLE_V(e)            BF_PWM_CTRL_PWM3_ENABLE(BV_PWM_CTRL_PWM3_ENABLE__##e)
+#define BFM_PWM_CTRL_PWM3_ENABLE_V(v)           BM_PWM_CTRL_PWM3_ENABLE
+#define BP_PWM_CTRL_PWM2_ENABLE                 2
+#define BM_PWM_CTRL_PWM2_ENABLE                 0x4
+#define BF_PWM_CTRL_PWM2_ENABLE(v)              (((v) & 0x1) << 2)
+#define BFM_PWM_CTRL_PWM2_ENABLE(v)             BM_PWM_CTRL_PWM2_ENABLE
+#define BF_PWM_CTRL_PWM2_ENABLE_V(e)            BF_PWM_CTRL_PWM2_ENABLE(BV_PWM_CTRL_PWM2_ENABLE__##e)
+#define BFM_PWM_CTRL_PWM2_ENABLE_V(v)           BM_PWM_CTRL_PWM2_ENABLE
+#define BP_PWM_CTRL_PWM1_ENABLE                 1
+#define BM_PWM_CTRL_PWM1_ENABLE                 0x2
+#define BF_PWM_CTRL_PWM1_ENABLE(v)              (((v) & 0x1) << 1)
+#define BFM_PWM_CTRL_PWM1_ENABLE(v)             BM_PWM_CTRL_PWM1_ENABLE
+#define BF_PWM_CTRL_PWM1_ENABLE_V(e)            BF_PWM_CTRL_PWM1_ENABLE(BV_PWM_CTRL_PWM1_ENABLE__##e)
+#define BFM_PWM_CTRL_PWM1_ENABLE_V(v)           BM_PWM_CTRL_PWM1_ENABLE
+#define BP_PWM_CTRL_PWM0_ENABLE                 0
+#define BM_PWM_CTRL_PWM0_ENABLE                 0x1
+#define BF_PWM_CTRL_PWM0_ENABLE(v)              (((v) & 0x1) << 0)
+#define BFM_PWM_CTRL_PWM0_ENABLE(v)             BM_PWM_CTRL_PWM0_ENABLE
+#define BF_PWM_CTRL_PWM0_ENABLE_V(e)            BF_PWM_CTRL_PWM0_ENABLE(BV_PWM_CTRL_PWM0_ENABLE__##e)
+#define BFM_PWM_CTRL_PWM0_ENABLE_V(v)           BM_PWM_CTRL_PWM0_ENABLE
+
+#define HW_PWM_ACTIVEn(_n1)             HW(PWM_ACTIVEn(_n1))
+#define HWA_PWM_ACTIVEn(_n1)            (0x80064000 + 0x10 + (_n1) * 0x20)
+#define HWT_PWM_ACTIVEn(_n1)            HWIO_32_RW
+#define HWN_PWM_ACTIVEn(_n1)            PWM_ACTIVEn
+#define HWI_PWM_ACTIVEn(_n1)            (_n1)
+#define HW_PWM_ACTIVEn_SET(_n1)         HW(PWM_ACTIVEn_SET(_n1))
+#define HWA_PWM_ACTIVEn_SET(_n1)        (HWA_PWM_ACTIVEn(_n1) + 0x4)
+#define HWT_PWM_ACTIVEn_SET(_n1)        HWIO_32_WO
+#define HWN_PWM_ACTIVEn_SET(_n1)        PWM_ACTIVEn
+#define HWI_PWM_ACTIVEn_SET(_n1)        (_n1)
+#define HW_PWM_ACTIVEn_CLR(_n1)         HW(PWM_ACTIVEn_CLR(_n1))
+#define HWA_PWM_ACTIVEn_CLR(_n1)        (HWA_PWM_ACTIVEn(_n1) + 0x8)
+#define HWT_PWM_ACTIVEn_CLR(_n1)        HWIO_32_WO
+#define HWN_PWM_ACTIVEn_CLR(_n1)        PWM_ACTIVEn
+#define HWI_PWM_ACTIVEn_CLR(_n1)        (_n1)
+#define HW_PWM_ACTIVEn_TOG(_n1)         HW(PWM_ACTIVEn_TOG(_n1))
+#define HWA_PWM_ACTIVEn_TOG(_n1)        (HWA_PWM_ACTIVEn(_n1) + 0xc)
+#define HWT_PWM_ACTIVEn_TOG(_n1)        HWIO_32_WO
+#define HWN_PWM_ACTIVEn_TOG(_n1)        PWM_ACTIVEn
+#define HWI_PWM_ACTIVEn_TOG(_n1)        (_n1)
+#define BP_PWM_ACTIVEn_INACTIVE         16
+#define BM_PWM_ACTIVEn_INACTIVE         0xffff0000
+#define BF_PWM_ACTIVEn_INACTIVE(v)      (((v) & 0xffff) << 16)
+#define BFM_PWM_ACTIVEn_INACTIVE(v)     BM_PWM_ACTIVEn_INACTIVE
+#define BF_PWM_ACTIVEn_INACTIVE_V(e)    BF_PWM_ACTIVEn_INACTIVE(BV_PWM_ACTIVEn_INACTIVE__##e)
+#define BFM_PWM_ACTIVEn_INACTIVE_V(v)   BM_PWM_ACTIVEn_INACTIVE
+#define BP_PWM_ACTIVEn_ACTIVE           0
+#define BM_PWM_ACTIVEn_ACTIVE           0xffff
+#define BF_PWM_ACTIVEn_ACTIVE(v)        (((v) & 0xffff) << 0)
+#define BFM_PWM_ACTIVEn_ACTIVE(v)       BM_PWM_ACTIVEn_ACTIVE
+#define BF_PWM_ACTIVEn_ACTIVE_V(e)      BF_PWM_ACTIVEn_ACTIVE(BV_PWM_ACTIVEn_ACTIVE__##e)
+#define BFM_PWM_ACTIVEn_ACTIVE_V(v)     BM_PWM_ACTIVEn_ACTIVE
+
+#define HW_PWM_PERIODn(_n1)                 HW(PWM_PERIODn(_n1))
+#define HWA_PWM_PERIODn(_n1)                (0x80064000 + 0x20 + (_n1) * 0x20)
+#define HWT_PWM_PERIODn(_n1)                HWIO_32_RW
+#define HWN_PWM_PERIODn(_n1)                PWM_PERIODn
+#define HWI_PWM_PERIODn(_n1)                (_n1)
+#define HW_PWM_PERIODn_SET(_n1)             HW(PWM_PERIODn_SET(_n1))
+#define HWA_PWM_PERIODn_SET(_n1)            (HWA_PWM_PERIODn(_n1) + 0x4)
+#define HWT_PWM_PERIODn_SET(_n1)            HWIO_32_WO
+#define HWN_PWM_PERIODn_SET(_n1)            PWM_PERIODn
+#define HWI_PWM_PERIODn_SET(_n1)            (_n1)
+#define HW_PWM_PERIODn_CLR(_n1)             HW(PWM_PERIODn_CLR(_n1))
+#define HWA_PWM_PERIODn_CLR(_n1)            (HWA_PWM_PERIODn(_n1) + 0x8)
+#define HWT_PWM_PERIODn_CLR(_n1)            HWIO_32_WO
+#define HWN_PWM_PERIODn_CLR(_n1)            PWM_PERIODn
+#define HWI_PWM_PERIODn_CLR(_n1)            (_n1)
+#define HW_PWM_PERIODn_TOG(_n1)             HW(PWM_PERIODn_TOG(_n1))
+#define HWA_PWM_PERIODn_TOG(_n1)            (HWA_PWM_PERIODn(_n1) + 0xc)
+#define HWT_PWM_PERIODn_TOG(_n1)            HWIO_32_WO
+#define HWN_PWM_PERIODn_TOG(_n1)            PWM_PERIODn
+#define HWI_PWM_PERIODn_TOG(_n1)            (_n1)
+#define BP_PWM_PERIODn_RSRVD2               25
+#define BM_PWM_PERIODn_RSRVD2               0xfe000000
+#define BF_PWM_PERIODn_RSRVD2(v)            (((v) & 0x7f) << 25)
+#define BFM_PWM_PERIODn_RSRVD2(v)           BM_PWM_PERIODn_RSRVD2
+#define BF_PWM_PERIODn_RSRVD2_V(e)          BF_PWM_PERIODn_RSRVD2(BV_PWM_PERIODn_RSRVD2__##e)
+#define BFM_PWM_PERIODn_RSRVD2_V(v)         BM_PWM_PERIODn_RSRVD2
+#define BP_PWM_PERIODn_MATT_SEL             24
+#define BM_PWM_PERIODn_MATT_SEL             0x1000000
+#define BF_PWM_PERIODn_MATT_SEL(v)          (((v) & 0x1) << 24)
+#define BFM_PWM_PERIODn_MATT_SEL(v)         BM_PWM_PERIODn_MATT_SEL
+#define BF_PWM_PERIODn_MATT_SEL_V(e)        BF_PWM_PERIODn_MATT_SEL(BV_PWM_PERIODn_MATT_SEL__##e)
+#define BFM_PWM_PERIODn_MATT_SEL_V(v)       BM_PWM_PERIODn_MATT_SEL
+#define BP_PWM_PERIODn_MATT                 23
+#define BM_PWM_PERIODn_MATT                 0x800000
+#define BF_PWM_PERIODn_MATT(v)              (((v) & 0x1) << 23)
+#define BFM_PWM_PERIODn_MATT(v)             BM_PWM_PERIODn_MATT
+#define BF_PWM_PERIODn_MATT_V(e)            BF_PWM_PERIODn_MATT(BV_PWM_PERIODn_MATT__##e)
+#define BFM_PWM_PERIODn_MATT_V(v)           BM_PWM_PERIODn_MATT
+#define BP_PWM_PERIODn_CDIV                 20
+#define BM_PWM_PERIODn_CDIV                 0x700000
+#define BV_PWM_PERIODn_CDIV__DIV_1          0x0
+#define BV_PWM_PERIODn_CDIV__DIV_2          0x1
+#define BV_PWM_PERIODn_CDIV__DIV_4          0x2
+#define BV_PWM_PERIODn_CDIV__DIV_8          0x3
+#define BV_PWM_PERIODn_CDIV__DIV_16         0x4
+#define BV_PWM_PERIODn_CDIV__DIV_64         0x5
+#define BV_PWM_PERIODn_CDIV__DIV_256        0x6
+#define BV_PWM_PERIODn_CDIV__DIV_1024       0x7
+#define BF_PWM_PERIODn_CDIV(v)              (((v) & 0x7) << 20)
+#define BFM_PWM_PERIODn_CDIV(v)             BM_PWM_PERIODn_CDIV
+#define BF_PWM_PERIODn_CDIV_V(e)            BF_PWM_PERIODn_CDIV(BV_PWM_PERIODn_CDIV__##e)
+#define BFM_PWM_PERIODn_CDIV_V(v)           BM_PWM_PERIODn_CDIV
+#define BP_PWM_PERIODn_INACTIVE_STATE       18
+#define BM_PWM_PERIODn_INACTIVE_STATE       0xc0000
+#define BV_PWM_PERIODn_INACTIVE_STATE__HI_Z 0x0
+#define BV_PWM_PERIODn_INACTIVE_STATE__0    0x2
+#define BV_PWM_PERIODn_INACTIVE_STATE__1    0x3
+#define BF_PWM_PERIODn_INACTIVE_STATE(v)    (((v) & 0x3) << 18)
+#define BFM_PWM_PERIODn_INACTIVE_STATE(v)   BM_PWM_PERIODn_INACTIVE_STATE
+#define BF_PWM_PERIODn_INACTIVE_STATE_V(e)  BF_PWM_PERIODn_INACTIVE_STATE(BV_PWM_PERIODn_INACTIVE_STATE__##e)
+#define BFM_PWM_PERIODn_INACTIVE_STATE_V(v) BM_PWM_PERIODn_INACTIVE_STATE
+#define BP_PWM_PERIODn_ACTIVE_STATE         16
+#define BM_PWM_PERIODn_ACTIVE_STATE         0x30000
+#define BV_PWM_PERIODn_ACTIVE_STATE__HI_Z   0x0
+#define BV_PWM_PERIODn_ACTIVE_STATE__0      0x2
+#define BV_PWM_PERIODn_ACTIVE_STATE__1      0x3
+#define BF_PWM_PERIODn_ACTIVE_STATE(v)      (((v) & 0x3) << 16)
+#define BFM_PWM_PERIODn_ACTIVE_STATE(v)     BM_PWM_PERIODn_ACTIVE_STATE
+#define BF_PWM_PERIODn_ACTIVE_STATE_V(e)    BF_PWM_PERIODn_ACTIVE_STATE(BV_PWM_PERIODn_ACTIVE_STATE__##e)
+#define BFM_PWM_PERIODn_ACTIVE_STATE_V(v)   BM_PWM_PERIODn_ACTIVE_STATE
+#define BP_PWM_PERIODn_PERIOD               0
+#define BM_PWM_PERIODn_PERIOD               0xffff
+#define BF_PWM_PERIODn_PERIOD(v)            (((v) & 0xffff) << 0)
+#define BFM_PWM_PERIODn_PERIOD(v)           BM_PWM_PERIODn_PERIOD
+#define BF_PWM_PERIODn_PERIOD_V(e)          BF_PWM_PERIODn_PERIOD(BV_PWM_PERIODn_PERIOD__##e)
+#define BFM_PWM_PERIODn_PERIOD_V(v)         BM_PWM_PERIODn_PERIOD
+
+#define HW_PWM_VERSION              HW(PWM_VERSION)
+#define HWA_PWM_VERSION             (0x80064000 + 0xb0)
+#define HWT_PWM_VERSION             HWIO_32_RW
+#define HWN_PWM_VERSION             PWM_VERSION
+#define HWI_PWM_VERSION             
+#define BP_PWM_VERSION_MAJOR        24
+#define BM_PWM_VERSION_MAJOR        0xff000000
+#define BF_PWM_VERSION_MAJOR(v)     (((v) & 0xff) << 24)
+#define BFM_PWM_VERSION_MAJOR(v)    BM_PWM_VERSION_MAJOR
+#define BF_PWM_VERSION_MAJOR_V(e)   BF_PWM_VERSION_MAJOR(BV_PWM_VERSION_MAJOR__##e)
+#define BFM_PWM_VERSION_MAJOR_V(v)  BM_PWM_VERSION_MAJOR
+#define BP_PWM_VERSION_MINOR        16
+#define BM_PWM_VERSION_MINOR        0xff0000
+#define BF_PWM_VERSION_MINOR(v)     (((v) & 0xff) << 16)
+#define BFM_PWM_VERSION_MINOR(v)    BM_PWM_VERSION_MINOR
+#define BF_PWM_VERSION_MINOR_V(e)   BF_PWM_VERSION_MINOR(BV_PWM_VERSION_MINOR__##e)
+#define BFM_PWM_VERSION_MINOR_V(v)  BM_PWM_VERSION_MINOR
+#define BP_PWM_VERSION_STEP         0
+#define BM_PWM_VERSION_STEP         0xffff
+#define BF_PWM_VERSION_STEP(v)      (((v) & 0xffff) << 0)
+#define BFM_PWM_VERSION_STEP(v)     BM_PWM_VERSION_STEP
+#define BF_PWM_VERSION_STEP_V(e)    BF_PWM_VERSION_STEP(BV_PWM_VERSION_STEP__##e)
+#define BFM_PWM_VERSION_STEP_V(v)   BM_PWM_VERSION_STEP
+
+#endif /* __HEADERGEN_IMX233_PWM_H__*/
diff --git a/firmware/target/arm/imx233/regs/imx233/pxp.h b/firmware/target/arm/imx233/regs/imx233/pxp.h
new file mode 100644
index 0000000000..5dc0b73d06
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/imx233/pxp.h
@@ -0,0 +1,916 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * imx233 version: 2.4.0
+ * imx233 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_IMX233_PXP_H__
+#define __HEADERGEN_IMX233_PXP_H__
+
+#define HW_PXP_CTRL                                 HW(PXP_CTRL)
+#define HWA_PXP_CTRL                                (0x8002a000 + 0x0)
+#define HWT_PXP_CTRL                                HWIO_32_RW
+#define HWN_PXP_CTRL                                PXP_CTRL
+#define HWI_PXP_CTRL                                
+#define HW_PXP_CTRL_SET                             HW(PXP_CTRL_SET)
+#define HWA_PXP_CTRL_SET                            (HWA_PXP_CTRL + 0x4)
+#define HWT_PXP_CTRL_SET                            HWIO_32_WO
+#define HWN_PXP_CTRL_SET                            PXP_CTRL
+#define HWI_PXP_CTRL_SET                            
+#define HW_PXP_CTRL_CLR                             HW(PXP_CTRL_CLR)
+#define HWA_PXP_CTRL_CLR                            (HWA_PXP_CTRL + 0x8)
+#define HWT_PXP_CTRL_CLR                            HWIO_32_WO
+#define HWN_PXP_CTRL_CLR                            PXP_CTRL
+#define HWI_PXP_CTRL_CLR                            
+#define HW_PXP_CTRL_TOG                             HW(PXP_CTRL_TOG)
+#define HWA_PXP_CTRL_TOG                            (HWA_PXP_CTRL + 0xc)
+#define HWT_PXP_CTRL_TOG                            HWIO_32_WO
+#define HWN_PXP_CTRL_TOG                            PXP_CTRL
+#define HWI_PXP_CTRL_TOG                            
+#define BP_PXP_CTRL_SFTRST                          31
+#define BM_PXP_CTRL_SFTRST                          0x80000000
+#define BF_PXP_CTRL_SFTRST(v)                       (((v) & 0x1) << 31)
+#define BFM_PXP_CTRL_SFTRST(v)                      BM_PXP_CTRL_SFTRST
+#define BF_PXP_CTRL_SFTRST_V(e)                     BF_PXP_CTRL_SFTRST(BV_PXP_CTRL_SFTRST__##e)
+#define BFM_PXP_CTRL_SFTRST_V(v)                    BM_PXP_CTRL_SFTRST
+#define BP_PXP_CTRL_CLKGATE                         30
+#define BM_PXP_CTRL_CLKGATE                         0x40000000
+#define BF_PXP_CTRL_CLKGATE(v)                      (((v) & 0x1) << 30)
+#define BFM_PXP_CTRL_CLKGATE(v)                     BM_PXP_CTRL_CLKGATE
+#define BF_PXP_CTRL_CLKGATE_V(e)                    BF_PXP_CTRL_CLKGATE(BV_PXP_CTRL_CLKGATE__##e)
+#define BFM_PXP_CTRL_CLKGATE_V(v)                   BM_PXP_CTRL_CLKGATE
+#define BP_PXP_CTRL_RSVD2                           28
+#define BM_PXP_CTRL_RSVD2                           0x30000000
+#define BF_PXP_CTRL_RSVD2(v)                        (((v) & 0x3) << 28)
+#define BFM_PXP_CTRL_RSVD2(v)                       BM_PXP_CTRL_RSVD2
+#define BF_PXP_CTRL_RSVD2_V(e)                      BF_PXP_CTRL_RSVD2(BV_PXP_CTRL_RSVD2__##e)
+#define BFM_PXP_CTRL_RSVD2_V(v)                     BM_PXP_CTRL_RSVD2
+#define BP_PXP_CTRL_INTERLACED_OUTPUT               26
+#define BM_PXP_CTRL_INTERLACED_OUTPUT               0xc000000
+#define BV_PXP_CTRL_INTERLACED_OUTPUT__PROGRESSIVE  0x0
+#define BV_PXP_CTRL_INTERLACED_OUTPUT__FIELD0       0x1
+#define BV_PXP_CTRL_INTERLACED_OUTPUT__FIELD1       0x2
+#define BV_PXP_CTRL_INTERLACED_OUTPUT__INTERLACED   0x3
+#define BF_PXP_CTRL_INTERLACED_OUTPUT(v)            (((v) & 0x3) << 26)
+#define BFM_PXP_CTRL_INTERLACED_OUTPUT(v)           BM_PXP_CTRL_INTERLACED_OUTPUT
+#define BF_PXP_CTRL_INTERLACED_OUTPUT_V(e)          BF_PXP_CTRL_INTERLACED_OUTPUT(BV_PXP_CTRL_INTERLACED_OUTPUT__##e)
+#define BFM_PXP_CTRL_INTERLACED_OUTPUT_V(v)         BM_PXP_CTRL_INTERLACED_OUTPUT
+#define BP_PXP_CTRL_INTERLACED_INPUT                24
+#define BM_PXP_CTRL_INTERLACED_INPUT                0x3000000
+#define BV_PXP_CTRL_INTERLACED_INPUT__PROGRESSIVE   0x0
+#define BV_PXP_CTRL_INTERLACED_INPUT__FIELD0        0x2
+#define BV_PXP_CTRL_INTERLACED_INPUT__FIELD1        0x3
+#define BF_PXP_CTRL_INTERLACED_INPUT(v)             (((v) & 0x3) << 24)
+#define BFM_PXP_CTRL_INTERLACED_INPUT(v)            BM_PXP_CTRL_INTERLACED_INPUT
+#define BF_PXP_CTRL_INTERLACED_INPUT_V(e)           BF_PXP_CTRL_INTERLACED_INPUT(BV_PXP_CTRL_INTERLACED_INPUT__##e)
+#define BFM_PXP_CTRL_INTERLACED_INPUT_V(v)          BM_PXP_CTRL_INTERLACED_INPUT
+#define BP_PXP_CTRL_RSVD1                           23
+#define BM_PXP_CTRL_RSVD1                           0x800000
+#define BF_PXP_CTRL_RSVD1(v)                        (((v) & 0x1) << 23)
+#define BFM_PXP_CTRL_RSVD1(v)                       BM_PXP_CTRL_RSVD1
+#define BF_PXP_CTRL_RSVD1_V(e)                      BF_PXP_CTRL_RSVD1(BV_PXP_CTRL_RSVD1__##e)
+#define BFM_PXP_CTRL_RSVD1_V(v)                     BM_PXP_CTRL_RSVD1
+#define BP_PXP_CTRL_ALPHA_OUTPUT                    22
+#define BM_PXP_CTRL_ALPHA_OUTPUT                    0x400000
+#define BF_PXP_CTRL_ALPHA_OUTPUT(v)                 (((v) & 0x1) << 22)
+#define BFM_PXP_CTRL_ALPHA_OUTPUT(v)                BM_PXP_CTRL_ALPHA_OUTPUT
+#define BF_PXP_CTRL_ALPHA_OUTPUT_V(e)               BF_PXP_CTRL_ALPHA_OUTPUT(BV_PXP_CTRL_ALPHA_OUTPUT__##e)
+#define BFM_PXP_CTRL_ALPHA_OUTPUT_V(v)              BM_PXP_CTRL_ALPHA_OUTPUT
+#define BP_PXP_CTRL_IN_PLACE                        21
+#define BM_PXP_CTRL_IN_PLACE                        0x200000
+#define BF_PXP_CTRL_IN_PLACE(v)                     (((v) & 0x1) << 21)
+#define BFM_PXP_CTRL_IN_PLACE(v)                    BM_PXP_CTRL_IN_PLACE
+#define BF_PXP_CTRL_IN_PLACE_V(e)                   BF_PXP_CTRL_IN_PLACE(BV_PXP_CTRL_IN_PLACE__##e)
+#define BFM_PXP_CTRL_IN_PLACE_V(v)                  BM_PXP_CTRL_IN_PLACE
+#define BP_PXP_CTRL_DELTA                           20
+#define BM_PXP_CTRL_DELTA                           0x100000
+#define BF_PXP_CTRL_DELTA(v)                        (((v) & 0x1) << 20)
+#define BFM_PXP_CTRL_DELTA(v)                       BM_PXP_CTRL_DELTA
+#define BF_PXP_CTRL_DELTA_V(e)                      BF_PXP_CTRL_DELTA(BV_PXP_CTRL_DELTA__##e)
+#define BFM_PXP_CTRL_DELTA_V(v)                     BM_PXP_CTRL_DELTA
+#define BP_PXP_CTRL_CROP                            19
+#define BM_PXP_CTRL_CROP                            0x80000
+#define BF_PXP_CTRL_CROP(v)                         (((v) & 0x1) << 19)
+#define BFM_PXP_CTRL_CROP(v)                        BM_PXP_CTRL_CROP
+#define BF_PXP_CTRL_CROP_V(e)                       BF_PXP_CTRL_CROP(BV_PXP_CTRL_CROP__##e)
+#define BFM_PXP_CTRL_CROP_V(v)                      BM_PXP_CTRL_CROP
+#define BP_PXP_CTRL_SCALE                           18
+#define BM_PXP_CTRL_SCALE                           0x40000
+#define BF_PXP_CTRL_SCALE(v)                        (((v) & 0x1) << 18)
+#define BFM_PXP_CTRL_SCALE(v)                       BM_PXP_CTRL_SCALE
+#define BF_PXP_CTRL_SCALE_V(e)                      BF_PXP_CTRL_SCALE(BV_PXP_CTRL_SCALE__##e)
+#define BFM_PXP_CTRL_SCALE_V(v)                     BM_PXP_CTRL_SCALE
+#define BP_PXP_CTRL_UPSAMPLE                        17
+#define BM_PXP_CTRL_UPSAMPLE                        0x20000
+#define BF_PXP_CTRL_UPSAMPLE(v)                     (((v) & 0x1) << 17)
+#define BFM_PXP_CTRL_UPSAMPLE(v)                    BM_PXP_CTRL_UPSAMPLE
+#define BF_PXP_CTRL_UPSAMPLE_V(e)                   BF_PXP_CTRL_UPSAMPLE(BV_PXP_CTRL_UPSAMPLE__##e)
+#define BFM_PXP_CTRL_UPSAMPLE_V(v)                  BM_PXP_CTRL_UPSAMPLE
+#define BP_PXP_CTRL_SUBSAMPLE                       16
+#define BM_PXP_CTRL_SUBSAMPLE                       0x10000
+#define BF_PXP_CTRL_SUBSAMPLE(v)                    (((v) & 0x1) << 16)
+#define BFM_PXP_CTRL_SUBSAMPLE(v)                   BM_PXP_CTRL_SUBSAMPLE
+#define BF_PXP_CTRL_SUBSAMPLE_V(e)                  BF_PXP_CTRL_SUBSAMPLE(BV_PXP_CTRL_SUBSAMPLE__##e)
+#define BFM_PXP_CTRL_SUBSAMPLE_V(v)                 BM_PXP_CTRL_SUBSAMPLE
+#define BP_PXP_CTRL_S0_FORMAT                       12
+#define BM_PXP_CTRL_S0_FORMAT                       0xf000
+#define BV_PXP_CTRL_S0_FORMAT__RGB888               0x1
+#define BV_PXP_CTRL_S0_FORMAT__RGB565               0x4
+#define BV_PXP_CTRL_S0_FORMAT__RGB555               0x5
+#define BV_PXP_CTRL_S0_FORMAT__YUV422               0x8
+#define BV_PXP_CTRL_S0_FORMAT__YUV420               0x9
+#define BF_PXP_CTRL_S0_FORMAT(v)                    (((v) & 0xf) << 12)
+#define BFM_PXP_CTRL_S0_FORMAT(v)                   BM_PXP_CTRL_S0_FORMAT
+#define BF_PXP_CTRL_S0_FORMAT_V(e)                  BF_PXP_CTRL_S0_FORMAT(BV_PXP_CTRL_S0_FORMAT__##e)
+#define BFM_PXP_CTRL_S0_FORMAT_V(v)                 BM_PXP_CTRL_S0_FORMAT
+#define BP_PXP_CTRL_VFLIP                           11
+#define BM_PXP_CTRL_VFLIP                           0x800
+#define BF_PXP_CTRL_VFLIP(v)                        (((v) & 0x1) << 11)
+#define BFM_PXP_CTRL_VFLIP(v)                       BM_PXP_CTRL_VFLIP
+#define BF_PXP_CTRL_VFLIP_V(e)                      BF_PXP_CTRL_VFLIP(BV_PXP_CTRL_VFLIP__##e)
+#define BFM_PXP_CTRL_VFLIP_V(v)                     BM_PXP_CTRL_VFLIP
+#define BP_PXP_CTRL_HFLIP                           10
+#define BM_PXP_CTRL_HFLIP                           0x400
+#define BF_PXP_CTRL_HFLIP(v)                        (((v) & 0x1) << 10)
+#define BFM_PXP_CTRL_HFLIP(v)                       BM_PXP_CTRL_HFLIP
+#define BF_PXP_CTRL_HFLIP_V(e)                      BF_PXP_CTRL_HFLIP(BV_PXP_CTRL_HFLIP__##e)
+#define BFM_PXP_CTRL_HFLIP_V(v)                     BM_PXP_CTRL_HFLIP
+#define BP_PXP_CTRL_ROTATE                          8
+#define BM_PXP_CTRL_ROTATE                          0x300
+#define BV_PXP_CTRL_ROTATE__ROT_0                   0x0
+#define BV_PXP_CTRL_ROTATE__ROT_90                  0x1
+#define BV_PXP_CTRL_ROTATE__ROT_180                 0x2
+#define BV_PXP_CTRL_ROTATE__ROT_270                 0x3
+#define BF_PXP_CTRL_ROTATE(v)                       (((v) & 0x3) << 8)
+#define BFM_PXP_CTRL_ROTATE(v)                      BM_PXP_CTRL_ROTATE
+#define BF_PXP_CTRL_ROTATE_V(e)                     BF_PXP_CTRL_ROTATE(BV_PXP_CTRL_ROTATE__##e)
+#define BFM_PXP_CTRL_ROTATE_V(v)                    BM_PXP_CTRL_ROTATE
+#define BP_PXP_CTRL_OUTPUT_RGB_FORMAT               4
+#define BM_PXP_CTRL_OUTPUT_RGB_FORMAT               0xf0
+#define BV_PXP_CTRL_OUTPUT_RGB_FORMAT__ARGB8888     0x0
+#define BV_PXP_CTRL_OUTPUT_RGB_FORMAT__RGB888       0x1
+#define BV_PXP_CTRL_OUTPUT_RGB_FORMAT__RGB888P      0x2
+#define BV_PXP_CTRL_OUTPUT_RGB_FORMAT__ARGB1555     0x3
+#define BV_PXP_CTRL_OUTPUT_RGB_FORMAT__RGB565       0x4
+#define BV_PXP_CTRL_OUTPUT_RGB_FORMAT__RGB555       0x5
+#define BF_PXP_CTRL_OUTPUT_RGB_FORMAT(v)            (((v) & 0xf) << 4)
+#define BFM_PXP_CTRL_OUTPUT_RGB_FORMAT(v)           BM_PXP_CTRL_OUTPUT_RGB_FORMAT
+#define BF_PXP_CTRL_OUTPUT_RGB_FORMAT_V(e)          BF_PXP_CTRL_OUTPUT_RGB_FORMAT(BV_PXP_CTRL_OUTPUT_RGB_FORMAT__##e)
+#define BFM_PXP_CTRL_OUTPUT_RGB_FORMAT_V(v)         BM_PXP_CTRL_OUTPUT_RGB_FORMAT
+#define BP_PXP_CTRL_RSVD0                           3
+#define BM_PXP_CTRL_RSVD0                           0x8
+#define BF_PXP_CTRL_RSVD0(v)                        (((v) & 0x1) << 3)
+#define BFM_PXP_CTRL_RSVD0(v)                       BM_PXP_CTRL_RSVD0
+#define BF_PXP_CTRL_RSVD0_V(e)                      BF_PXP_CTRL_RSVD0(BV_PXP_CTRL_RSVD0__##e)
+#define BFM_PXP_CTRL_RSVD0_V(v)                     BM_PXP_CTRL_RSVD0
+#define BP_PXP_CTRL_ENABLE_LCD_HANDSHAKE            2
+#define BM_PXP_CTRL_ENABLE_LCD_HANDSHAKE            0x4
+#define BF_PXP_CTRL_ENABLE_LCD_HANDSHAKE(v)         (((v) & 0x1) << 2)
+#define BFM_PXP_CTRL_ENABLE_LCD_HANDSHAKE(v)        BM_PXP_CTRL_ENABLE_LCD_HANDSHAKE
+#define BF_PXP_CTRL_ENABLE_LCD_HANDSHAKE_V(e)       BF_PXP_CTRL_ENABLE_LCD_HANDSHAKE(BV_PXP_CTRL_ENABLE_LCD_HANDSHAKE__##e)
+#define BFM_PXP_CTRL_ENABLE_LCD_HANDSHAKE_V(v)      BM_PXP_CTRL_ENABLE_LCD_HANDSHAKE
+#define BP_PXP_CTRL_IRQ_ENABLE                      1
+#define BM_PXP_CTRL_IRQ_ENABLE                      0x2
+#define BF_PXP_CTRL_IRQ_ENABLE(v)                   (((v) & 0x1) << 1)
+#define BFM_PXP_CTRL_IRQ_ENABLE(v)                  BM_PXP_CTRL_IRQ_ENABLE
+#define BF_PXP_CTRL_IRQ_ENABLE_V(e)                 BF_PXP_CTRL_IRQ_ENABLE(BV_PXP_CTRL_IRQ_ENABLE__##e)
+#define BFM_PXP_CTRL_IRQ_ENABLE_V(v)                BM_PXP_CTRL_IRQ_ENABLE
+#define BP_PXP_CTRL_ENABLE                          0
+#define BM_PXP_CTRL_ENABLE                          0x1
+#define BF_PXP_CTRL_ENABLE(v)                       (((v) & 0x1) << 0)
+#define BFM_PXP_CTRL_ENABLE(v)                      BM_PXP_CTRL_ENABLE
+#define BF_PXP_CTRL_ENABLE_V(e)                     BF_PXP_CTRL_ENABLE(BV_PXP_CTRL_ENABLE__##e)
+#define BFM_PXP_CTRL_ENABLE_V(v)                    BM_PXP_CTRL_ENABLE
+
+#define HW_PXP_STAT                         HW(PXP_STAT)
+#define HWA_PXP_STAT                        (0x8002a000 + 0x10)
+#define HWT_PXP_STAT                        HWIO_32_RW
+#define HWN_PXP_STAT                        PXP_STAT
+#define HWI_PXP_STAT                        
+#define HW_PXP_STAT_SET                     HW(PXP_STAT_SET)
+#define HWA_PXP_STAT_SET                    (HWA_PXP_STAT + 0x4)
+#define HWT_PXP_STAT_SET                    HWIO_32_WO
+#define HWN_PXP_STAT_SET                    PXP_STAT
+#define HWI_PXP_STAT_SET                    
+#define HW_PXP_STAT_CLR                     HW(PXP_STAT_CLR)
+#define HWA_PXP_STAT_CLR                    (HWA_PXP_STAT + 0x8)
+#define HWT_PXP_STAT_CLR                    HWIO_32_WO
+#define HWN_PXP_STAT_CLR                    PXP_STAT
+#define HWI_PXP_STAT_CLR                    
+#define HW_PXP_STAT_TOG                     HW(PXP_STAT_TOG)
+#define HWA_PXP_STAT_TOG                    (HWA_PXP_STAT + 0xc)
+#define HWT_PXP_STAT_TOG                    HWIO_32_WO
+#define HWN_PXP_STAT_TOG                    PXP_STAT
+#define HWI_PXP_STAT_TOG                    
+#define BP_PXP_STAT_BLOCKX                  24
+#define BM_PXP_STAT_BLOCKX                  0xff000000
+#define BF_PXP_STAT_BLOCKX(v)               (((v) & 0xff) << 24)
+#define BFM_PXP_STAT_BLOCKX(v)              BM_PXP_STAT_BLOCKX
+#define BF_PXP_STAT_BLOCKX_V(e)             BF_PXP_STAT_BLOCKX(BV_PXP_STAT_BLOCKX__##e)
+#define BFM_PXP_STAT_BLOCKX_V(v)            BM_PXP_STAT_BLOCKX
+#define BP_PXP_STAT_BLOCKY                  16
+#define BM_PXP_STAT_BLOCKY                  0xff0000
+#define BF_PXP_STAT_BLOCKY(v)               (((v) & 0xff) << 16)
+#define BFM_PXP_STAT_BLOCKY(v)              BM_PXP_STAT_BLOCKY
+#define BF_PXP_STAT_BLOCKY_V(e)             BF_PXP_STAT_BLOCKY(BV_PXP_STAT_BLOCKY__##e)
+#define BFM_PXP_STAT_BLOCKY_V(v)            BM_PXP_STAT_BLOCKY
+#define BP_PXP_STAT_RSVD2                   8
+#define BM_PXP_STAT_RSVD2                   0xff00
+#define BF_PXP_STAT_RSVD2(v)                (((v) & 0xff) << 8)
+#define BFM_PXP_STAT_RSVD2(v)               BM_PXP_STAT_RSVD2
+#define BF_PXP_STAT_RSVD2_V(e)              BF_PXP_STAT_RSVD2(BV_PXP_STAT_RSVD2__##e)
+#define BFM_PXP_STAT_RSVD2_V(v)             BM_PXP_STAT_RSVD2
+#define BP_PXP_STAT_AXI_ERROR_ID            4
+#define BM_PXP_STAT_AXI_ERROR_ID            0xf0
+#define BF_PXP_STAT_AXI_ERROR_ID(v)         (((v) & 0xf) << 4)
+#define BFM_PXP_STAT_AXI_ERROR_ID(v)        BM_PXP_STAT_AXI_ERROR_ID
+#define BF_PXP_STAT_AXI_ERROR_ID_V(e)       BF_PXP_STAT_AXI_ERROR_ID(BV_PXP_STAT_AXI_ERROR_ID__##e)
+#define BFM_PXP_STAT_AXI_ERROR_ID_V(v)      BM_PXP_STAT_AXI_ERROR_ID
+#define BP_PXP_STAT_RSVD1                   3
+#define BM_PXP_STAT_RSVD1                   0x8
+#define BF_PXP_STAT_RSVD1(v)                (((v) & 0x1) << 3)
+#define BFM_PXP_STAT_RSVD1(v)               BM_PXP_STAT_RSVD1
+#define BF_PXP_STAT_RSVD1_V(e)              BF_PXP_STAT_RSVD1(BV_PXP_STAT_RSVD1__##e)
+#define BFM_PXP_STAT_RSVD1_V(v)             BM_PXP_STAT_RSVD1
+#define BP_PXP_STAT_AXI_READ_ERROR          2
+#define BM_PXP_STAT_AXI_READ_ERROR          0x4
+#define BF_PXP_STAT_AXI_READ_ERROR(v)       (((v) & 0x1) << 2)
+#define BFM_PXP_STAT_AXI_READ_ERROR(v)      BM_PXP_STAT_AXI_READ_ERROR
+#define BF_PXP_STAT_AXI_READ_ERROR_V(e)     BF_PXP_STAT_AXI_READ_ERROR(BV_PXP_STAT_AXI_READ_ERROR__##e)
+#define BFM_PXP_STAT_AXI_READ_ERROR_V(v)    BM_PXP_STAT_AXI_READ_ERROR
+#define BP_PXP_STAT_AXI_WRITE_ERROR         1
+#define BM_PXP_STAT_AXI_WRITE_ERROR         0x2
+#define BF_PXP_STAT_AXI_WRITE_ERROR(v)      (((v) & 0x1) << 1)
+#define BFM_PXP_STAT_AXI_WRITE_ERROR(v)     BM_PXP_STAT_AXI_WRITE_ERROR
+#define BF_PXP_STAT_AXI_WRITE_ERROR_V(e)    BF_PXP_STAT_AXI_WRITE_ERROR(BV_PXP_STAT_AXI_WRITE_ERROR__##e)
+#define BFM_PXP_STAT_AXI_WRITE_ERROR_V(v)   BM_PXP_STAT_AXI_WRITE_ERROR
+#define BP_PXP_STAT_IRQ                     0
+#define BM_PXP_STAT_IRQ                     0x1
+#define BF_PXP_STAT_IRQ(v)                  (((v) & 0x1) << 0)
+#define BFM_PXP_STAT_IRQ(v)                 BM_PXP_STAT_IRQ
+#define BF_PXP_STAT_IRQ_V(e)                BF_PXP_STAT_IRQ(BV_PXP_STAT_IRQ__##e)
+#define BFM_PXP_STAT_IRQ_V(v)               BM_PXP_STAT_IRQ
+
+#define HW_PXP_RGBBUF               HW(PXP_RGBBUF)
+#define HWA_PXP_RGBBUF              (0x8002a000 + 0x20)
+#define HWT_PXP_RGBBUF              HWIO_32_RW
+#define HWN_PXP_RGBBUF              PXP_RGBBUF
+#define HWI_PXP_RGBBUF              
+#define BP_PXP_RGBBUF_ADDR          0
+#define BM_PXP_RGBBUF_ADDR          0xffffffff
+#define BF_PXP_RGBBUF_ADDR(v)       (((v) & 0xffffffff) << 0)
+#define BFM_PXP_RGBBUF_ADDR(v)      BM_PXP_RGBBUF_ADDR
+#define BF_PXP_RGBBUF_ADDR_V(e)     BF_PXP_RGBBUF_ADDR(BV_PXP_RGBBUF_ADDR__##e)
+#define BFM_PXP_RGBBUF_ADDR_V(v)    BM_PXP_RGBBUF_ADDR
+
+#define HW_PXP_RGBBUF2              HW(PXP_RGBBUF2)
+#define HWA_PXP_RGBBUF2             (0x8002a000 + 0x30)
+#define HWT_PXP_RGBBUF2             HWIO_32_RW
+#define HWN_PXP_RGBBUF2             PXP_RGBBUF2
+#define HWI_PXP_RGBBUF2             
+#define BP_PXP_RGBBUF2_ADDR         0
+#define BM_PXP_RGBBUF2_ADDR         0xffffffff
+#define BF_PXP_RGBBUF2_ADDR(v)      (((v) & 0xffffffff) << 0)
+#define BFM_PXP_RGBBUF2_ADDR(v)     BM_PXP_RGBBUF2_ADDR
+#define BF_PXP_RGBBUF2_ADDR_V(e)    BF_PXP_RGBBUF2_ADDR(BV_PXP_RGBBUF2_ADDR__##e)
+#define BFM_PXP_RGBBUF2_ADDR_V(v)   BM_PXP_RGBBUF2_ADDR
+
+#define HW_PXP_RGBSIZE              HW(PXP_RGBSIZE)
+#define HWA_PXP_RGBSIZE             (0x8002a000 + 0x40)
+#define HWT_PXP_RGBSIZE             HWIO_32_RW
+#define HWN_PXP_RGBSIZE             PXP_RGBSIZE
+#define HWI_PXP_RGBSIZE             
+#define BP_PXP_RGBSIZE_ALPHA        24
+#define BM_PXP_RGBSIZE_ALPHA        0xff000000
+#define BF_PXP_RGBSIZE_ALPHA(v)     (((v) & 0xff) << 24)
+#define BFM_PXP_RGBSIZE_ALPHA(v)    BM_PXP_RGBSIZE_ALPHA
+#define BF_PXP_RGBSIZE_ALPHA_V(e)   BF_PXP_RGBSIZE_ALPHA(BV_PXP_RGBSIZE_ALPHA__##e)
+#define BFM_PXP_RGBSIZE_ALPHA_V(v)  BM_PXP_RGBSIZE_ALPHA
+#define BP_PXP_RGBSIZE_WIDTH        12
+#define BM_PXP_RGBSIZE_WIDTH        0xfff000
+#define BF_PXP_RGBSIZE_WIDTH(v)     (((v) & 0xfff) << 12)
+#define BFM_PXP_RGBSIZE_WIDTH(v)    BM_PXP_RGBSIZE_WIDTH
+#define BF_PXP_RGBSIZE_WIDTH_V(e)   BF_PXP_RGBSIZE_WIDTH(BV_PXP_RGBSIZE_WIDTH__##e)
+#define BFM_PXP_RGBSIZE_WIDTH_V(v)  BM_PXP_RGBSIZE_WIDTH
+#define BP_PXP_RGBSIZE_HEIGHT       0
+#define BM_PXP_RGBSIZE_HEIGHT       0xfff
+#define BF_PXP_RGBSIZE_HEIGHT(v)    (((v) & 0xfff) << 0)
+#define BFM_PXP_RGBSIZE_HEIGHT(v)   BM_PXP_RGBSIZE_HEIGHT
+#define BF_PXP_RGBSIZE_HEIGHT_V(e)  BF_PXP_RGBSIZE_HEIGHT(BV_PXP_RGBSIZE_HEIGHT__##e)
+#define BFM_PXP_RGBSIZE_HEIGHT_V(v) BM_PXP_RGBSIZE_HEIGHT
+
+#define HW_PXP_S0BUF            HW(PXP_S0BUF)
+#define HWA_PXP_S0BUF           (0x8002a000 + 0x50)
+#define HWT_PXP_S0BUF           HWIO_32_RW
+#define HWN_PXP_S0BUF           PXP_S0BUF
+#define HWI_PXP_S0BUF           
+#define BP_PXP_S0BUF_ADDR       0
+#define BM_PXP_S0BUF_ADDR       0xffffffff
+#define BF_PXP_S0BUF_ADDR(v)    (((v) & 0xffffffff) << 0)
+#define BFM_PXP_S0BUF_ADDR(v)   BM_PXP_S0BUF_ADDR
+#define BF_PXP_S0BUF_ADDR_V(e)  BF_PXP_S0BUF_ADDR(BV_PXP_S0BUF_ADDR__##e)
+#define BFM_PXP_S0BUF_ADDR_V(v) BM_PXP_S0BUF_ADDR
+
+#define HW_PXP_S0UBUF               HW(PXP_S0UBUF)
+#define HWA_PXP_S0UBUF              (0x8002a000 + 0x60)
+#define HWT_PXP_S0UBUF              HWIO_32_RW
+#define HWN_PXP_S0UBUF              PXP_S0UBUF
+#define HWI_PXP_S0UBUF              
+#define BP_PXP_S0UBUF_ADDR          0
+#define BM_PXP_S0UBUF_ADDR          0xffffffff
+#define BF_PXP_S0UBUF_ADDR(v)       (((v) & 0xffffffff) << 0)
+#define BFM_PXP_S0UBUF_ADDR(v)      BM_PXP_S0UBUF_ADDR
+#define BF_PXP_S0UBUF_ADDR_V(e)     BF_PXP_S0UBUF_ADDR(BV_PXP_S0UBUF_ADDR__##e)
+#define BFM_PXP_S0UBUF_ADDR_V(v)    BM_PXP_S0UBUF_ADDR
+
+#define HW_PXP_S0VBUF               HW(PXP_S0VBUF)
+#define HWA_PXP_S0VBUF              (0x8002a000 + 0x70)
+#define HWT_PXP_S0VBUF              HWIO_32_RW
+#define HWN_PXP_S0VBUF              PXP_S0VBUF
+#define HWI_PXP_S0VBUF              
+#define BP_PXP_S0VBUF_ADDR          0
+#define BM_PXP_S0VBUF_ADDR          0xffffffff
+#define BF_PXP_S0VBUF_ADDR(v)       (((v) & 0xffffffff) << 0)
+#define BFM_PXP_S0VBUF_ADDR(v)      BM_PXP_S0VBUF_ADDR
+#define BF_PXP_S0VBUF_ADDR_V(e)     BF_PXP_S0VBUF_ADDR(BV_PXP_S0VBUF_ADDR__##e)
+#define BFM_PXP_S0VBUF_ADDR_V(v)    BM_PXP_S0VBUF_ADDR
+
+#define HW_PXP_S0PARAM              HW(PXP_S0PARAM)
+#define HWA_PXP_S0PARAM             (0x8002a000 + 0x80)
+#define HWT_PXP_S0PARAM             HWIO_32_RW
+#define HWN_PXP_S0PARAM             PXP_S0PARAM
+#define HWI_PXP_S0PARAM             
+#define BP_PXP_S0PARAM_XBASE        24
+#define BM_PXP_S0PARAM_XBASE        0xff000000
+#define BF_PXP_S0PARAM_XBASE(v)     (((v) & 0xff) << 24)
+#define BFM_PXP_S0PARAM_XBASE(v)    BM_PXP_S0PARAM_XBASE
+#define BF_PXP_S0PARAM_XBASE_V(e)   BF_PXP_S0PARAM_XBASE(BV_PXP_S0PARAM_XBASE__##e)
+#define BFM_PXP_S0PARAM_XBASE_V(v)  BM_PXP_S0PARAM_XBASE
+#define BP_PXP_S0PARAM_YBASE        16
+#define BM_PXP_S0PARAM_YBASE        0xff0000
+#define BF_PXP_S0PARAM_YBASE(v)     (((v) & 0xff) << 16)
+#define BFM_PXP_S0PARAM_YBASE(v)    BM_PXP_S0PARAM_YBASE
+#define BF_PXP_S0PARAM_YBASE_V(e)   BF_PXP_S0PARAM_YBASE(BV_PXP_S0PARAM_YBASE__##e)
+#define BFM_PXP_S0PARAM_YBASE_V(v)  BM_PXP_S0PARAM_YBASE
+#define BP_PXP_S0PARAM_WIDTH        8
+#define BM_PXP_S0PARAM_WIDTH        0xff00
+#define BF_PXP_S0PARAM_WIDTH(v)     (((v) & 0xff) << 8)
+#define BFM_PXP_S0PARAM_WIDTH(v)    BM_PXP_S0PARAM_WIDTH
+#define BF_PXP_S0PARAM_WIDTH_V(e)   BF_PXP_S0PARAM_WIDTH(BV_PXP_S0PARAM_WIDTH__##e)
+#define BFM_PXP_S0PARAM_WIDTH_V(v)  BM_PXP_S0PARAM_WIDTH
+#define BP_PXP_S0PARAM_HEIGHT       0
+#define BM_PXP_S0PARAM_HEIGHT       0xff
+#define BF_PXP_S0PARAM_HEIGHT(v)    (((v) & 0xff) << 0)
+#define BFM_PXP_S0PARAM_HEIGHT(v)   BM_PXP_S0PARAM_HEIGHT
+#define BF_PXP_S0PARAM_HEIGHT_V(e)  BF_PXP_S0PARAM_HEIGHT(BV_PXP_S0PARAM_HEIGHT__##e)
+#define BFM_PXP_S0PARAM_HEIGHT_V(v) BM_PXP_S0PARAM_HEIGHT
+
+#define HW_PXP_S0BACKGROUND             HW(PXP_S0BACKGROUND)
+#define HWA_PXP_S0BACKGROUND            (0x8002a000 + 0x90)
+#define HWT_PXP_S0BACKGROUND            HWIO_32_RW
+#define HWN_PXP_S0BACKGROUND            PXP_S0BACKGROUND
+#define HWI_PXP_S0BACKGROUND            
+#define BP_PXP_S0BACKGROUND_COLOR       0
+#define BM_PXP_S0BACKGROUND_COLOR       0xffffffff
+#define BF_PXP_S0BACKGROUND_COLOR(v)    (((v) & 0xffffffff) << 0)
+#define BFM_PXP_S0BACKGROUND_COLOR(v)   BM_PXP_S0BACKGROUND_COLOR
+#define BF_PXP_S0BACKGROUND_COLOR_V(e)  BF_PXP_S0BACKGROUND_COLOR(BV_PXP_S0BACKGROUND_COLOR__##e)
+#define BFM_PXP_S0BACKGROUND_COLOR_V(v) BM_PXP_S0BACKGROUND_COLOR
+
+#define HW_PXP_S0CROP               HW(PXP_S0CROP)
+#define HWA_PXP_S0CROP              (0x8002a000 + 0xa0)
+#define HWT_PXP_S0CROP              HWIO_32_RW
+#define HWN_PXP_S0CROP              PXP_S0CROP
+#define HWI_PXP_S0CROP              
+#define BP_PXP_S0CROP_XBASE         24
+#define BM_PXP_S0CROP_XBASE         0xff000000
+#define BF_PXP_S0CROP_XBASE(v)      (((v) & 0xff) << 24)
+#define BFM_PXP_S0CROP_XBASE(v)     BM_PXP_S0CROP_XBASE
+#define BF_PXP_S0CROP_XBASE_V(e)    BF_PXP_S0CROP_XBASE(BV_PXP_S0CROP_XBASE__##e)
+#define BFM_PXP_S0CROP_XBASE_V(v)   BM_PXP_S0CROP_XBASE
+#define BP_PXP_S0CROP_YBASE         16
+#define BM_PXP_S0CROP_YBASE         0xff0000
+#define BF_PXP_S0CROP_YBASE(v)      (((v) & 0xff) << 16)
+#define BFM_PXP_S0CROP_YBASE(v)     BM_PXP_S0CROP_YBASE
+#define BF_PXP_S0CROP_YBASE_V(e)    BF_PXP_S0CROP_YBASE(BV_PXP_S0CROP_YBASE__##e)
+#define BFM_PXP_S0CROP_YBASE_V(v)   BM_PXP_S0CROP_YBASE
+#define BP_PXP_S0CROP_WIDTH         8
+#define BM_PXP_S0CROP_WIDTH         0xff00
+#define BF_PXP_S0CROP_WIDTH(v)      (((v) & 0xff) << 8)
+#define BFM_PXP_S0CROP_WIDTH(v)     BM_PXP_S0CROP_WIDTH
+#define BF_PXP_S0CROP_WIDTH_V(e)    BF_PXP_S0CROP_WIDTH(BV_PXP_S0CROP_WIDTH__##e)
+#define BFM_PXP_S0CROP_WIDTH_V(v)   BM_PXP_S0CROP_WIDTH
+#define BP_PXP_S0CROP_HEIGHT        0
+#define BM_PXP_S0CROP_HEIGHT        0xff
+#define BF_PXP_S0CROP_HEIGHT(v)     (((v) & 0xff) << 0)
+#define BFM_PXP_S0CROP_HEIGHT(v)    BM_PXP_S0CROP_HEIGHT
+#define BF_PXP_S0CROP_HEIGHT_V(e)   BF_PXP_S0CROP_HEIGHT(BV_PXP_S0CROP_HEIGHT__##e)
+#define BFM_PXP_S0CROP_HEIGHT_V(v)  BM_PXP_S0CROP_HEIGHT
+
+#define HW_PXP_S0SCALE              HW(PXP_S0SCALE)
+#define HWA_PXP_S0SCALE             (0x8002a000 + 0xb0)
+#define HWT_PXP_S0SCALE             HWIO_32_RW
+#define HWN_PXP_S0SCALE             PXP_S0SCALE
+#define HWI_PXP_S0SCALE             
+#define BP_PXP_S0SCALE_RSVD2        30
+#define BM_PXP_S0SCALE_RSVD2        0xc0000000
+#define BF_PXP_S0SCALE_RSVD2(v)     (((v) & 0x3) << 30)
+#define BFM_PXP_S0SCALE_RSVD2(v)    BM_PXP_S0SCALE_RSVD2
+#define BF_PXP_S0SCALE_RSVD2_V(e)   BF_PXP_S0SCALE_RSVD2(BV_PXP_S0SCALE_RSVD2__##e)
+#define BFM_PXP_S0SCALE_RSVD2_V(v)  BM_PXP_S0SCALE_RSVD2
+#define BP_PXP_S0SCALE_YSCALE       16
+#define BM_PXP_S0SCALE_YSCALE       0x3fff0000
+#define BF_PXP_S0SCALE_YSCALE(v)    (((v) & 0x3fff) << 16)
+#define BFM_PXP_S0SCALE_YSCALE(v)   BM_PXP_S0SCALE_YSCALE
+#define BF_PXP_S0SCALE_YSCALE_V(e)  BF_PXP_S0SCALE_YSCALE(BV_PXP_S0SCALE_YSCALE__##e)
+#define BFM_PXP_S0SCALE_YSCALE_V(v) BM_PXP_S0SCALE_YSCALE
+#define BP_PXP_S0SCALE_RSVD1        14
+#define BM_PXP_S0SCALE_RSVD1        0xc000
+#define BF_PXP_S0SCALE_RSVD1(v)     (((v) & 0x3) << 14)
+#define BFM_PXP_S0SCALE_RSVD1(v)    BM_PXP_S0SCALE_RSVD1
+#define BF_PXP_S0SCALE_RSVD1_V(e)   BF_PXP_S0SCALE_RSVD1(BV_PXP_S0SCALE_RSVD1__##e)
+#define BFM_PXP_S0SCALE_RSVD1_V(v)  BM_PXP_S0SCALE_RSVD1
+#define BP_PXP_S0SCALE_XSCALE       0
+#define BM_PXP_S0SCALE_XSCALE       0x3fff
+#define BF_PXP_S0SCALE_XSCALE(v)    (((v) & 0x3fff) << 0)
+#define BFM_PXP_S0SCALE_XSCALE(v)   BM_PXP_S0SCALE_XSCALE
+#define BF_PXP_S0SCALE_XSCALE_V(e)  BF_PXP_S0SCALE_XSCALE(BV_PXP_S0SCALE_XSCALE__##e)
+#define BFM_PXP_S0SCALE_XSCALE_V(v) BM_PXP_S0SCALE_XSCALE
+
+#define HW_PXP_S0OFFSET                 HW(PXP_S0OFFSET)
+#define HWA_PXP_S0OFFSET                (0x8002a000 + 0xc0)
+#define HWT_PXP_S0OFFSET                HWIO_32_RW
+#define HWN_PXP_S0OFFSET                PXP_S0OFFSET
+#define HWI_PXP_S0OFFSET                
+#define BP_PXP_S0OFFSET_RSVD2           28
+#define BM_PXP_S0OFFSET_RSVD2           0xf0000000
+#define BF_PXP_S0OFFSET_RSVD2(v)        (((v) & 0xf) << 28)
+#define BFM_PXP_S0OFFSET_RSVD2(v)       BM_PXP_S0OFFSET_RSVD2
+#define BF_PXP_S0OFFSET_RSVD2_V(e)      BF_PXP_S0OFFSET_RSVD2(BV_PXP_S0OFFSET_RSVD2__##e)
+#define BFM_PXP_S0OFFSET_RSVD2_V(v)     BM_PXP_S0OFFSET_RSVD2
+#define BP_PXP_S0OFFSET_YOFFSET         16
+#define BM_PXP_S0OFFSET_YOFFSET         0xfff0000
+#define BF_PXP_S0OFFSET_YOFFSET(v)      (((v) & 0xfff) << 16)
+#define BFM_PXP_S0OFFSET_YOFFSET(v)     BM_PXP_S0OFFSET_YOFFSET
+#define BF_PXP_S0OFFSET_YOFFSET_V(e)    BF_PXP_S0OFFSET_YOFFSET(BV_PXP_S0OFFSET_YOFFSET__##e)
+#define BFM_PXP_S0OFFSET_YOFFSET_V(v)   BM_PXP_S0OFFSET_YOFFSET
+#define BP_PXP_S0OFFSET_RSVD1           12
+#define BM_PXP_S0OFFSET_RSVD1           0xf000
+#define BF_PXP_S0OFFSET_RSVD1(v)        (((v) & 0xf) << 12)
+#define BFM_PXP_S0OFFSET_RSVD1(v)       BM_PXP_S0OFFSET_RSVD1
+#define BF_PXP_S0OFFSET_RSVD1_V(e)      BF_PXP_S0OFFSET_RSVD1(BV_PXP_S0OFFSET_RSVD1__##e)
+#define BFM_PXP_S0OFFSET_RSVD1_V(v)     BM_PXP_S0OFFSET_RSVD1
+#define BP_PXP_S0OFFSET_XOFFSET         0
+#define BM_PXP_S0OFFSET_XOFFSET         0xfff
+#define BF_PXP_S0OFFSET_XOFFSET(v)      (((v) & 0xfff) << 0)
+#define BFM_PXP_S0OFFSET_XOFFSET(v)     BM_PXP_S0OFFSET_XOFFSET
+#define BF_PXP_S0OFFSET_XOFFSET_V(e)    BF_PXP_S0OFFSET_XOFFSET(BV_PXP_S0OFFSET_XOFFSET__##e)
+#define BFM_PXP_S0OFFSET_XOFFSET_V(v)   BM_PXP_S0OFFSET_XOFFSET
+
+#define HW_PXP_CSCCOEFF0                    HW(PXP_CSCCOEFF0)
+#define HWA_PXP_CSCCOEFF0                   (0x8002a000 + 0xd0)
+#define HWT_PXP_CSCCOEFF0                   HWIO_32_RW
+#define HWN_PXP_CSCCOEFF0                   PXP_CSCCOEFF0
+#define HWI_PXP_CSCCOEFF0                   
+#define BP_PXP_CSCCOEFF0_YCBCR_MODE         31
+#define BM_PXP_CSCCOEFF0_YCBCR_MODE         0x80000000
+#define BF_PXP_CSCCOEFF0_YCBCR_MODE(v)      (((v) & 0x1) << 31)
+#define BFM_PXP_CSCCOEFF0_YCBCR_MODE(v)     BM_PXP_CSCCOEFF0_YCBCR_MODE
+#define BF_PXP_CSCCOEFF0_YCBCR_MODE_V(e)    BF_PXP_CSCCOEFF0_YCBCR_MODE(BV_PXP_CSCCOEFF0_YCBCR_MODE__##e)
+#define BFM_PXP_CSCCOEFF0_YCBCR_MODE_V(v)   BM_PXP_CSCCOEFF0_YCBCR_MODE
+#define BP_PXP_CSCCOEFF0_RSVD1              29
+#define BM_PXP_CSCCOEFF0_RSVD1              0x60000000
+#define BF_PXP_CSCCOEFF0_RSVD1(v)           (((v) & 0x3) << 29)
+#define BFM_PXP_CSCCOEFF0_RSVD1(v)          BM_PXP_CSCCOEFF0_RSVD1
+#define BF_PXP_CSCCOEFF0_RSVD1_V(e)         BF_PXP_CSCCOEFF0_RSVD1(BV_PXP_CSCCOEFF0_RSVD1__##e)
+#define BFM_PXP_CSCCOEFF0_RSVD1_V(v)        BM_PXP_CSCCOEFF0_RSVD1
+#define BP_PXP_CSCCOEFF0_C0                 18
+#define BM_PXP_CSCCOEFF0_C0                 0x1ffc0000
+#define BF_PXP_CSCCOEFF0_C0(v)              (((v) & 0x7ff) << 18)
+#define BFM_PXP_CSCCOEFF0_C0(v)             BM_PXP_CSCCOEFF0_C0
+#define BF_PXP_CSCCOEFF0_C0_V(e)            BF_PXP_CSCCOEFF0_C0(BV_PXP_CSCCOEFF0_C0__##e)
+#define BFM_PXP_CSCCOEFF0_C0_V(v)           BM_PXP_CSCCOEFF0_C0
+#define BP_PXP_CSCCOEFF0_UV_OFFSET          9
+#define BM_PXP_CSCCOEFF0_UV_OFFSET          0x3fe00
+#define BF_PXP_CSCCOEFF0_UV_OFFSET(v)       (((v) & 0x1ff) << 9)
+#define BFM_PXP_CSCCOEFF0_UV_OFFSET(v)      BM_PXP_CSCCOEFF0_UV_OFFSET
+#define BF_PXP_CSCCOEFF0_UV_OFFSET_V(e)     BF_PXP_CSCCOEFF0_UV_OFFSET(BV_PXP_CSCCOEFF0_UV_OFFSET__##e)
+#define BFM_PXP_CSCCOEFF0_UV_OFFSET_V(v)    BM_PXP_CSCCOEFF0_UV_OFFSET
+#define BP_PXP_CSCCOEFF0_Y_OFFSET           0
+#define BM_PXP_CSCCOEFF0_Y_OFFSET           0x1ff
+#define BF_PXP_CSCCOEFF0_Y_OFFSET(v)        (((v) & 0x1ff) << 0)
+#define BFM_PXP_CSCCOEFF0_Y_OFFSET(v)       BM_PXP_CSCCOEFF0_Y_OFFSET
+#define BF_PXP_CSCCOEFF0_Y_OFFSET_V(e)      BF_PXP_CSCCOEFF0_Y_OFFSET(BV_PXP_CSCCOEFF0_Y_OFFSET__##e)
+#define BFM_PXP_CSCCOEFF0_Y_OFFSET_V(v)     BM_PXP_CSCCOEFF0_Y_OFFSET
+
+#define HW_PXP_CSCCOEFF1                HW(PXP_CSCCOEFF1)
+#define HWA_PXP_CSCCOEFF1               (0x8002a000 + 0xe0)
+#define HWT_PXP_CSCCOEFF1               HWIO_32_RW
+#define HWN_PXP_CSCCOEFF1               PXP_CSCCOEFF1
+#define HWI_PXP_CSCCOEFF1               
+#define BP_PXP_CSCCOEFF1_RSVD1          27
+#define BM_PXP_CSCCOEFF1_RSVD1          0xf8000000
+#define BF_PXP_CSCCOEFF1_RSVD1(v)       (((v) & 0x1f) << 27)
+#define BFM_PXP_CSCCOEFF1_RSVD1(v)      BM_PXP_CSCCOEFF1_RSVD1
+#define BF_PXP_CSCCOEFF1_RSVD1_V(e)     BF_PXP_CSCCOEFF1_RSVD1(BV_PXP_CSCCOEFF1_RSVD1__##e)
+#define BFM_PXP_CSCCOEFF1_RSVD1_V(v)    BM_PXP_CSCCOEFF1_RSVD1
+#define BP_PXP_CSCCOEFF1_C1             16
+#define BM_PXP_CSCCOEFF1_C1             0x7ff0000
+#define BF_PXP_CSCCOEFF1_C1(v)          (((v) & 0x7ff) << 16)
+#define BFM_PXP_CSCCOEFF1_C1(v)         BM_PXP_CSCCOEFF1_C1
+#define BF_PXP_CSCCOEFF1_C1_V(e)        BF_PXP_CSCCOEFF1_C1(BV_PXP_CSCCOEFF1_C1__##e)
+#define BFM_PXP_CSCCOEFF1_C1_V(v)       BM_PXP_CSCCOEFF1_C1
+#define BP_PXP_CSCCOEFF1_RSVD0          11
+#define BM_PXP_CSCCOEFF1_RSVD0          0xf800
+#define BF_PXP_CSCCOEFF1_RSVD0(v)       (((v) & 0x1f) << 11)
+#define BFM_PXP_CSCCOEFF1_RSVD0(v)      BM_PXP_CSCCOEFF1_RSVD0
+#define BF_PXP_CSCCOEFF1_RSVD0_V(e)     BF_PXP_CSCCOEFF1_RSVD0(BV_PXP_CSCCOEFF1_RSVD0__##e)
+#define BFM_PXP_CSCCOEFF1_RSVD0_V(v)    BM_PXP_CSCCOEFF1_RSVD0
+#define BP_PXP_CSCCOEFF1_C4             0
+#define BM_PXP_CSCCOEFF1_C4             0x7ff
+#define BF_PXP_CSCCOEFF1_C4(v)          (((v) & 0x7ff) << 0)
+#define BFM_PXP_CSCCOEFF1_C4(v)         BM_PXP_CSCCOEFF1_C4
+#define BF_PXP_CSCCOEFF1_C4_V(e)        BF_PXP_CSCCOEFF1_C4(BV_PXP_CSCCOEFF1_C4__##e)
+#define BFM_PXP_CSCCOEFF1_C4_V(v)       BM_PXP_CSCCOEFF1_C4
+
+#define HW_PXP_CSCCOEFF2                HW(PXP_CSCCOEFF2)
+#define HWA_PXP_CSCCOEFF2               (0x8002a000 + 0xf0)
+#define HWT_PXP_CSCCOEFF2               HWIO_32_RW
+#define HWN_PXP_CSCCOEFF2               PXP_CSCCOEFF2
+#define HWI_PXP_CSCCOEFF2               
+#define BP_PXP_CSCCOEFF2_RSVD1          27
+#define BM_PXP_CSCCOEFF2_RSVD1          0xf8000000
+#define BF_PXP_CSCCOEFF2_RSVD1(v)       (((v) & 0x1f) << 27)
+#define BFM_PXP_CSCCOEFF2_RSVD1(v)      BM_PXP_CSCCOEFF2_RSVD1
+#define BF_PXP_CSCCOEFF2_RSVD1_V(e)     BF_PXP_CSCCOEFF2_RSVD1(BV_PXP_CSCCOEFF2_RSVD1__##e)
+#define BFM_PXP_CSCCOEFF2_RSVD1_V(v)    BM_PXP_CSCCOEFF2_RSVD1
+#define BP_PXP_CSCCOEFF2_C2             16
+#define BM_PXP_CSCCOEFF2_C2             0x7ff0000
+#define BF_PXP_CSCCOEFF2_C2(v)          (((v) & 0x7ff) << 16)
+#define BFM_PXP_CSCCOEFF2_C2(v)         BM_PXP_CSCCOEFF2_C2
+#define BF_PXP_CSCCOEFF2_C2_V(e)        BF_PXP_CSCCOEFF2_C2(BV_PXP_CSCCOEFF2_C2__##e)
+#define BFM_PXP_CSCCOEFF2_C2_V(v)       BM_PXP_CSCCOEFF2_C2
+#define BP_PXP_CSCCOEFF2_RSVD0          11
+#define BM_PXP_CSCCOEFF2_RSVD0          0xf800
+#define BF_PXP_CSCCOEFF2_RSVD0(v)       (((v) & 0x1f) << 11)
+#define BFM_PXP_CSCCOEFF2_RSVD0(v)      BM_PXP_CSCCOEFF2_RSVD0
+#define BF_PXP_CSCCOEFF2_RSVD0_V(e)     BF_PXP_CSCCOEFF2_RSVD0(BV_PXP_CSCCOEFF2_RSVD0__##e)
+#define BFM_PXP_CSCCOEFF2_RSVD0_V(v)    BM_PXP_CSCCOEFF2_RSVD0
+#define BP_PXP_CSCCOEFF2_C3             0
+#define BM_PXP_CSCCOEFF2_C3             0x7ff
+#define BF_PXP_CSCCOEFF2_C3(v)          (((v) & 0x7ff) << 0)
+#define BFM_PXP_CSCCOEFF2_C3(v)         BM_PXP_CSCCOEFF2_C3
+#define BF_PXP_CSCCOEFF2_C3_V(e)        BF_PXP_CSCCOEFF2_C3(BV_PXP_CSCCOEFF2_C3__##e)
+#define BFM_PXP_CSCCOEFF2_C3_V(v)       BM_PXP_CSCCOEFF2_C3
+
+#define HW_PXP_NEXT                 HW(PXP_NEXT)
+#define HWA_PXP_NEXT                (0x8002a000 + 0x100)
+#define HWT_PXP_NEXT                HWIO_32_RW
+#define HWN_PXP_NEXT                PXP_NEXT
+#define HWI_PXP_NEXT                
+#define HW_PXP_NEXT_SET             HW(PXP_NEXT_SET)
+#define HWA_PXP_NEXT_SET            (HWA_PXP_NEXT + 0x4)
+#define HWT_PXP_NEXT_SET            HWIO_32_WO
+#define HWN_PXP_NEXT_SET            PXP_NEXT
+#define HWI_PXP_NEXT_SET            
+#define HW_PXP_NEXT_CLR             HW(PXP_NEXT_CLR)
+#define HWA_PXP_NEXT_CLR            (HWA_PXP_NEXT + 0x8)
+#define HWT_PXP_NEXT_CLR            HWIO_32_WO
+#define HWN_PXP_NEXT_CLR            PXP_NEXT
+#define HWI_PXP_NEXT_CLR            
+#define HW_PXP_NEXT_TOG             HW(PXP_NEXT_TOG)
+#define HWA_PXP_NEXT_TOG            (HWA_PXP_NEXT + 0xc)
+#define HWT_PXP_NEXT_TOG            HWIO_32_WO
+#define HWN_PXP_NEXT_TOG            PXP_NEXT
+#define HWI_PXP_NEXT_TOG            
+#define BP_PXP_NEXT_POINTER         2
+#define BM_PXP_NEXT_POINTER         0xfffffffc
+#define BF_PXP_NEXT_POINTER(v)      (((v) & 0x3fffffff) << 2)
+#define BFM_PXP_NEXT_POINTER(v)     BM_PXP_NEXT_POINTER
+#define BF_PXP_NEXT_POINTER_V(e)    BF_PXP_NEXT_POINTER(BV_PXP_NEXT_POINTER__##e)
+#define BFM_PXP_NEXT_POINTER_V(v)   BM_PXP_NEXT_POINTER
+#define BP_PXP_NEXT_RSVD            1
+#define BM_PXP_NEXT_RSVD            0x2
+#define BF_PXP_NEXT_RSVD(v)         (((v) & 0x1) << 1)
+#define BFM_PXP_NEXT_RSVD(v)        BM_PXP_NEXT_RSVD
+#define BF_PXP_NEXT_RSVD_V(e)       BF_PXP_NEXT_RSVD(BV_PXP_NEXT_RSVD__##e)
+#define BFM_PXP_NEXT_RSVD_V(v)      BM_PXP_NEXT_RSVD
+#define BP_PXP_NEXT_ENABLED         0
+#define BM_PXP_NEXT_ENABLED         0x1
+#define BF_PXP_NEXT_ENABLED(v)      (((v) & 0x1) << 0)
+#define BFM_PXP_NEXT_ENABLED(v)     BM_PXP_NEXT_ENABLED
+#define BF_PXP_NEXT_ENABLED_V(e)    BF_PXP_NEXT_ENABLED(BV_PXP_NEXT_ENABLED__##e)
+#define BFM_PXP_NEXT_ENABLED_V(v)   BM_PXP_NEXT_ENABLED
+
+#define HW_PXP_PAGETABLE                HW(PXP_PAGETABLE)
+#define HWA_PXP_PAGETABLE               (0x8002a000 + 0x170)
+#define HWT_PXP_PAGETABLE               HWIO_32_RW
+#define HWN_PXP_PAGETABLE               PXP_PAGETABLE
+#define HWI_PXP_PAGETABLE               
+#define BP_PXP_PAGETABLE_BASE           14
+#define BM_PXP_PAGETABLE_BASE           0xffffc000
+#define BF_PXP_PAGETABLE_BASE(v)        (((v) & 0x3ffff) << 14)
+#define BFM_PXP_PAGETABLE_BASE(v)       BM_PXP_PAGETABLE_BASE
+#define BF_PXP_PAGETABLE_BASE_V(e)      BF_PXP_PAGETABLE_BASE(BV_PXP_PAGETABLE_BASE__##e)
+#define BFM_PXP_PAGETABLE_BASE_V(v)     BM_PXP_PAGETABLE_BASE
+#define BP_PXP_PAGETABLE_RSVD1          2
+#define BM_PXP_PAGETABLE_RSVD1          0x3ffc
+#define BF_PXP_PAGETABLE_RSVD1(v)       (((v) & 0xfff) << 2)
+#define BFM_PXP_PAGETABLE_RSVD1(v)      BM_PXP_PAGETABLE_RSVD1
+#define BF_PXP_PAGETABLE_RSVD1_V(e)     BF_PXP_PAGETABLE_RSVD1(BV_PXP_PAGETABLE_RSVD1__##e)
+#define BFM_PXP_PAGETABLE_RSVD1_V(v)    BM_PXP_PAGETABLE_RSVD1
+#define BP_PXP_PAGETABLE_FLUSH          1
+#define BM_PXP_PAGETABLE_FLUSH          0x2
+#define BF_PXP_PAGETABLE_FLUSH(v)       (((v) & 0x1) << 1)
+#define BFM_PXP_PAGETABLE_FLUSH(v)      BM_PXP_PAGETABLE_FLUSH
+#define BF_PXP_PAGETABLE_FLUSH_V(e)     BF_PXP_PAGETABLE_FLUSH(BV_PXP_PAGETABLE_FLUSH__##e)
+#define BFM_PXP_PAGETABLE_FLUSH_V(v)    BM_PXP_PAGETABLE_FLUSH
+#define BP_PXP_PAGETABLE_ENABLE         0
+#define BM_PXP_PAGETABLE_ENABLE         0x1
+#define BF_PXP_PAGETABLE_ENABLE(v)      (((v) & 0x1) << 0)
+#define BFM_PXP_PAGETABLE_ENABLE(v)     BM_PXP_PAGETABLE_ENABLE
+#define BF_PXP_PAGETABLE_ENABLE_V(e)    BF_PXP_PAGETABLE_ENABLE(BV_PXP_PAGETABLE_ENABLE__##e)
+#define BFM_PXP_PAGETABLE_ENABLE_V(v)   BM_PXP_PAGETABLE_ENABLE
+
+#define HW_PXP_S0COLORKEYLOW                HW(PXP_S0COLORKEYLOW)
+#define HWA_PXP_S0COLORKEYLOW               (0x8002a000 + 0x180)
+#define HWT_PXP_S0COLORKEYLOW               HWIO_32_RW
+#define HWN_PXP_S0COLORKEYLOW               PXP_S0COLORKEYLOW
+#define HWI_PXP_S0COLORKEYLOW               
+#define BP_PXP_S0COLORKEYLOW_RSVD1          24
+#define BM_PXP_S0COLORKEYLOW_RSVD1          0xff000000
+#define BF_PXP_S0COLORKEYLOW_RSVD1(v)       (((v) & 0xff) << 24)
+#define BFM_PXP_S0COLORKEYLOW_RSVD1(v)      BM_PXP_S0COLORKEYLOW_RSVD1
+#define BF_PXP_S0COLORKEYLOW_RSVD1_V(e)     BF_PXP_S0COLORKEYLOW_RSVD1(BV_PXP_S0COLORKEYLOW_RSVD1__##e)
+#define BFM_PXP_S0COLORKEYLOW_RSVD1_V(v)    BM_PXP_S0COLORKEYLOW_RSVD1
+#define BP_PXP_S0COLORKEYLOW_PIXEL          0
+#define BM_PXP_S0COLORKEYLOW_PIXEL          0xffffff
+#define BF_PXP_S0COLORKEYLOW_PIXEL(v)       (((v) & 0xffffff) << 0)
+#define BFM_PXP_S0COLORKEYLOW_PIXEL(v)      BM_PXP_S0COLORKEYLOW_PIXEL
+#define BF_PXP_S0COLORKEYLOW_PIXEL_V(e)     BF_PXP_S0COLORKEYLOW_PIXEL(BV_PXP_S0COLORKEYLOW_PIXEL__##e)
+#define BFM_PXP_S0COLORKEYLOW_PIXEL_V(v)    BM_PXP_S0COLORKEYLOW_PIXEL
+
+#define HW_PXP_S0COLORKEYHIGH               HW(PXP_S0COLORKEYHIGH)
+#define HWA_PXP_S0COLORKEYHIGH              (0x8002a000 + 0x190)
+#define HWT_PXP_S0COLORKEYHIGH              HWIO_32_RW
+#define HWN_PXP_S0COLORKEYHIGH              PXP_S0COLORKEYHIGH
+#define HWI_PXP_S0COLORKEYHIGH              
+#define BP_PXP_S0COLORKEYHIGH_RSVD1         24
+#define BM_PXP_S0COLORKEYHIGH_RSVD1         0xff000000
+#define BF_PXP_S0COLORKEYHIGH_RSVD1(v)      (((v) & 0xff) << 24)
+#define BFM_PXP_S0COLORKEYHIGH_RSVD1(v)     BM_PXP_S0COLORKEYHIGH_RSVD1
+#define BF_PXP_S0COLORKEYHIGH_RSVD1_V(e)    BF_PXP_S0COLORKEYHIGH_RSVD1(BV_PXP_S0COLORKEYHIGH_RSVD1__##e)
+#define BFM_PXP_S0COLORKEYHIGH_RSVD1_V(v)   BM_PXP_S0COLORKEYHIGH_RSVD1
+#define BP_PXP_S0COLORKEYHIGH_PIXEL         0
+#define BM_PXP_S0COLORKEYHIGH_PIXEL         0xffffff
+#define BF_PXP_S0COLORKEYHIGH_PIXEL(v)      (((v) & 0xffffff) << 0)
+#define BFM_PXP_S0COLORKEYHIGH_PIXEL(v)     BM_PXP_S0COLORKEYHIGH_PIXEL
+#define BF_PXP_S0COLORKEYHIGH_PIXEL_V(e)    BF_PXP_S0COLORKEYHIGH_PIXEL(BV_PXP_S0COLORKEYHIGH_PIXEL__##e)
+#define BFM_PXP_S0COLORKEYHIGH_PIXEL_V(v)   BM_PXP_S0COLORKEYHIGH_PIXEL
+
+#define HW_PXP_OLCOLORKEYLOW                HW(PXP_OLCOLORKEYLOW)
+#define HWA_PXP_OLCOLORKEYLOW               (0x8002a000 + 0x1a0)
+#define HWT_PXP_OLCOLORKEYLOW               HWIO_32_RW
+#define HWN_PXP_OLCOLORKEYLOW               PXP_OLCOLORKEYLOW
+#define HWI_PXP_OLCOLORKEYLOW               
+#define BP_PXP_OLCOLORKEYLOW_RSVD1          24
+#define BM_PXP_OLCOLORKEYLOW_RSVD1          0xff000000
+#define BF_PXP_OLCOLORKEYLOW_RSVD1(v)       (((v) & 0xff) << 24)
+#define BFM_PXP_OLCOLORKEYLOW_RSVD1(v)      BM_PXP_OLCOLORKEYLOW_RSVD1
+#define BF_PXP_OLCOLORKEYLOW_RSVD1_V(e)     BF_PXP_OLCOLORKEYLOW_RSVD1(BV_PXP_OLCOLORKEYLOW_RSVD1__##e)
+#define BFM_PXP_OLCOLORKEYLOW_RSVD1_V(v)    BM_PXP_OLCOLORKEYLOW_RSVD1
+#define BP_PXP_OLCOLORKEYLOW_PIXEL          0
+#define BM_PXP_OLCOLORKEYLOW_PIXEL          0xffffff
+#define BF_PXP_OLCOLORKEYLOW_PIXEL(v)       (((v) & 0xffffff) << 0)
+#define BFM_PXP_OLCOLORKEYLOW_PIXEL(v)      BM_PXP_OLCOLORKEYLOW_PIXEL
+#define BF_PXP_OLCOLORKEYLOW_PIXEL_V(e)     BF_PXP_OLCOLORKEYLOW_PIXEL(BV_PXP_OLCOLORKEYLOW_PIXEL__##e)
+#define BFM_PXP_OLCOLORKEYLOW_PIXEL_V(v)    BM_PXP_OLCOLORKEYLOW_PIXEL
+
+#define HW_PXP_OLCOLORKEYHIGH               HW(PXP_OLCOLORKEYHIGH)
+#define HWA_PXP_OLCOLORKEYHIGH              (0x8002a000 + 0x1b0)
+#define HWT_PXP_OLCOLORKEYHIGH              HWIO_32_RW
+#define HWN_PXP_OLCOLORKEYHIGH              PXP_OLCOLORKEYHIGH
+#define HWI_PXP_OLCOLORKEYHIGH              
+#define BP_PXP_OLCOLORKEYHIGH_RSVD1         24
+#define BM_PXP_OLCOLORKEYHIGH_RSVD1         0xff000000
+#define BF_PXP_OLCOLORKEYHIGH_RSVD1(v)      (((v) & 0xff) << 24)
+#define BFM_PXP_OLCOLORKEYHIGH_RSVD1(v)     BM_PXP_OLCOLORKEYHIGH_RSVD1
+#define BF_PXP_OLCOLORKEYHIGH_RSVD1_V(e)    BF_PXP_OLCOLORKEYHIGH_RSVD1(BV_PXP_OLCOLORKEYHIGH_RSVD1__##e)
+#define BFM_PXP_OLCOLORKEYHIGH_RSVD1_V(v)   BM_PXP_OLCOLORKEYHIGH_RSVD1
+#define BP_PXP_OLCOLORKEYHIGH_PIXEL         0
+#define BM_PXP_OLCOLORKEYHIGH_PIXEL         0xffffff
+#define BF_PXP_OLCOLORKEYHIGH_PIXEL(v)      (((v) & 0xffffff) << 0)
+#define BFM_PXP_OLCOLORKEYHIGH_PIXEL(v)     BM_PXP_OLCOLORKEYHIGH_PIXEL
+#define BF_PXP_OLCOLORKEYHIGH_PIXEL_V(e)    BF_PXP_OLCOLORKEYHIGH_PIXEL(BV_PXP_OLCOLORKEYHIGH_PIXEL__##e)
+#define BFM_PXP_OLCOLORKEYHIGH_PIXEL_V(v)   BM_PXP_OLCOLORKEYHIGH_PIXEL
+
+#define HW_PXP_DEBUGCTRL                        HW(PXP_DEBUGCTRL)
+#define HWA_PXP_DEBUGCTRL                       (0x8002a000 + 0x1d0)
+#define HWT_PXP_DEBUGCTRL                       HWIO_32_RW
+#define HWN_PXP_DEBUGCTRL                       PXP_DEBUGCTRL
+#define HWI_PXP_DEBUGCTRL                       
+#define BP_PXP_DEBUGCTRL_RSVD                   9
+#define BM_PXP_DEBUGCTRL_RSVD                   0xfffffe00
+#define BF_PXP_DEBUGCTRL_RSVD(v)                (((v) & 0x7fffff) << 9)
+#define BFM_PXP_DEBUGCTRL_RSVD(v)               BM_PXP_DEBUGCTRL_RSVD
+#define BF_PXP_DEBUGCTRL_RSVD_V(e)              BF_PXP_DEBUGCTRL_RSVD(BV_PXP_DEBUGCTRL_RSVD__##e)
+#define BFM_PXP_DEBUGCTRL_RSVD_V(v)             BM_PXP_DEBUGCTRL_RSVD
+#define BP_PXP_DEBUGCTRL_RESET_TLB_STATS        8
+#define BM_PXP_DEBUGCTRL_RESET_TLB_STATS        0x100
+#define BF_PXP_DEBUGCTRL_RESET_TLB_STATS(v)     (((v) & 0x1) << 8)
+#define BFM_PXP_DEBUGCTRL_RESET_TLB_STATS(v)    BM_PXP_DEBUGCTRL_RESET_TLB_STATS
+#define BF_PXP_DEBUGCTRL_RESET_TLB_STATS_V(e)   BF_PXP_DEBUGCTRL_RESET_TLB_STATS(BV_PXP_DEBUGCTRL_RESET_TLB_STATS__##e)
+#define BFM_PXP_DEBUGCTRL_RESET_TLB_STATS_V(v)  BM_PXP_DEBUGCTRL_RESET_TLB_STATS
+#define BP_PXP_DEBUGCTRL_SELECT                 0
+#define BM_PXP_DEBUGCTRL_SELECT                 0xff
+#define BV_PXP_DEBUGCTRL_SELECT__NONE           0x0
+#define BV_PXP_DEBUGCTRL_SELECT__CTRL           0x1
+#define BV_PXP_DEBUGCTRL_SELECT__S0REGS         0x2
+#define BV_PXP_DEBUGCTRL_SELECT__S0BAX          0x3
+#define BV_PXP_DEBUGCTRL_SELECT__S0BAY          0x4
+#define BV_PXP_DEBUGCTRL_SELECT__PXBUF          0x5
+#define BV_PXP_DEBUGCTRL_SELECT__ROTATION       0x6
+#define BV_PXP_DEBUGCTRL_SELECT__ROTBUF0        0x7
+#define BV_PXP_DEBUGCTRL_SELECT__ROTBUF1        0x8
+#define BF_PXP_DEBUGCTRL_SELECT(v)              (((v) & 0xff) << 0)
+#define BFM_PXP_DEBUGCTRL_SELECT(v)             BM_PXP_DEBUGCTRL_SELECT
+#define BF_PXP_DEBUGCTRL_SELECT_V(e)            BF_PXP_DEBUGCTRL_SELECT(BV_PXP_DEBUGCTRL_SELECT__##e)
+#define BFM_PXP_DEBUGCTRL_SELECT_V(v)           BM_PXP_DEBUGCTRL_SELECT
+
+#define HW_PXP_DEBUG            HW(PXP_DEBUG)
+#define HWA_PXP_DEBUG           (0x8002a000 + 0x1e0)
+#define HWT_PXP_DEBUG           HWIO_32_RW
+#define HWN_PXP_DEBUG           PXP_DEBUG
+#define HWI_PXP_DEBUG           
+#define BP_PXP_DEBUG_DATA       0
+#define BM_PXP_DEBUG_DATA       0xffffffff
+#define BF_PXP_DEBUG_DATA(v)    (((v) & 0xffffffff) << 0)
+#define BFM_PXP_DEBUG_DATA(v)   BM_PXP_DEBUG_DATA
+#define BF_PXP_DEBUG_DATA_V(e)  BF_PXP_DEBUG_DATA(BV_PXP_DEBUG_DATA__##e)
+#define BFM_PXP_DEBUG_DATA_V(v) BM_PXP_DEBUG_DATA
+
+#define HW_PXP_VERSION              HW(PXP_VERSION)
+#define HWA_PXP_VERSION             (0x8002a000 + 0x1f0)
+#define HWT_PXP_VERSION             HWIO_32_RW
+#define HWN_PXP_VERSION             PXP_VERSION
+#define HWI_PXP_VERSION             
+#define BP_PXP_VERSION_MAJOR        24
+#define BM_PXP_VERSION_MAJOR        0xff000000
+#define BF_PXP_VERSION_MAJOR(v)     (((v) & 0xff) << 24)
+#define BFM_PXP_VERSION_MAJOR(v)    BM_PXP_VERSION_MAJOR
+#define BF_PXP_VERSION_MAJOR_V(e)   BF_PXP_VERSION_MAJOR(BV_PXP_VERSION_MAJOR__##e)
+#define BFM_PXP_VERSION_MAJOR_V(v)  BM_PXP_VERSION_MAJOR
+#define BP_PXP_VERSION_MINOR        16
+#define BM_PXP_VERSION_MINOR        0xff0000
+#define BF_PXP_VERSION_MINOR(v)     (((v) & 0xff) << 16)
+#define BFM_PXP_VERSION_MINOR(v)    BM_PXP_VERSION_MINOR
+#define BF_PXP_VERSION_MINOR_V(e)   BF_PXP_VERSION_MINOR(BV_PXP_VERSION_MINOR__##e)
+#define BFM_PXP_VERSION_MINOR_V(v)  BM_PXP_VERSION_MINOR
+#define BP_PXP_VERSION_STEP         0
+#define BM_PXP_VERSION_STEP         0xffff
+#define BF_PXP_VERSION_STEP(v)      (((v) & 0xffff) << 0)
+#define BFM_PXP_VERSION_STEP(v)     BM_PXP_VERSION_STEP
+#define BF_PXP_VERSION_STEP_V(e)    BF_PXP_VERSION_STEP(BV_PXP_VERSION_STEP__##e)
+#define BFM_PXP_VERSION_STEP_V(v)   BM_PXP_VERSION_STEP
+
+#define HW_PXP_OLn(_n1)         HW(PXP_OLn(_n1))
+#define HWA_PXP_OLn(_n1)        (0x8002a000 + 0x200 + (_n1) * 0x40)
+#define HWT_PXP_OLn(_n1)        HWIO_32_RW
+#define HWN_PXP_OLn(_n1)        PXP_OLn
+#define HWI_PXP_OLn(_n1)        (_n1)
+#define BP_PXP_OLn_ADDR         0
+#define BM_PXP_OLn_ADDR         0xffffffff
+#define BF_PXP_OLn_ADDR(v)      (((v) & 0xffffffff) << 0)
+#define BFM_PXP_OLn_ADDR(v)     BM_PXP_OLn_ADDR
+#define BF_PXP_OLn_ADDR_V(e)    BF_PXP_OLn_ADDR(BV_PXP_OLn_ADDR__##e)
+#define BFM_PXP_OLn_ADDR_V(v)   BM_PXP_OLn_ADDR
+
+#define HW_PXP_OLnSIZE(_n1)         HW(PXP_OLnSIZE(_n1))
+#define HWA_PXP_OLnSIZE(_n1)        (0x8002a000 + 0x210 + (_n1) * 0x40)
+#define HWT_PXP_OLnSIZE(_n1)        HWIO_32_RW
+#define HWN_PXP_OLnSIZE(_n1)        PXP_OLnSIZE
+#define HWI_PXP_OLnSIZE(_n1)        (_n1)
+#define BP_PXP_OLnSIZE_XBASE        24
+#define BM_PXP_OLnSIZE_XBASE        0xff000000
+#define BF_PXP_OLnSIZE_XBASE(v)     (((v) & 0xff) << 24)
+#define BFM_PXP_OLnSIZE_XBASE(v)    BM_PXP_OLnSIZE_XBASE
+#define BF_PXP_OLnSIZE_XBASE_V(e)   BF_PXP_OLnSIZE_XBASE(BV_PXP_OLnSIZE_XBASE__##e)
+#define BFM_PXP_OLnSIZE_XBASE_V(v)  BM_PXP_OLnSIZE_XBASE
+#define BP_PXP_OLnSIZE_YBASE        16
+#define BM_PXP_OLnSIZE_YBASE        0xff0000
+#define BF_PXP_OLnSIZE_YBASE(v)     (((v) & 0xff) << 16)
+#define BFM_PXP_OLnSIZE_YBASE(v)    BM_PXP_OLnSIZE_YBASE
+#define BF_PXP_OLnSIZE_YBASE_V(e)   BF_PXP_OLnSIZE_YBASE(BV_PXP_OLnSIZE_YBASE__##e)
+#define BFM_PXP_OLnSIZE_YBASE_V(v)  BM_PXP_OLnSIZE_YBASE
+#define BP_PXP_OLnSIZE_WIDTH        8
+#define BM_PXP_OLnSIZE_WIDTH        0xff00
+#define BF_PXP_OLnSIZE_WIDTH(v)     (((v) & 0xff) << 8)
+#define BFM_PXP_OLnSIZE_WIDTH(v)    BM_PXP_OLnSIZE_WIDTH
+#define BF_PXP_OLnSIZE_WIDTH_V(e)   BF_PXP_OLnSIZE_WIDTH(BV_PXP_OLnSIZE_WIDTH__##e)
+#define BFM_PXP_OLnSIZE_WIDTH_V(v)  BM_PXP_OLnSIZE_WIDTH
+#define BP_PXP_OLnSIZE_HEIGHT       0
+#define BM_PXP_OLnSIZE_HEIGHT       0xff
+#define BF_PXP_OLnSIZE_HEIGHT(v)    (((v) & 0xff) << 0)
+#define BFM_PXP_OLnSIZE_HEIGHT(v)   BM_PXP_OLnSIZE_HEIGHT
+#define BF_PXP_OLnSIZE_HEIGHT_V(e)  BF_PXP_OLnSIZE_HEIGHT(BV_PXP_OLnSIZE_HEIGHT__##e)
+#define BFM_PXP_OLnSIZE_HEIGHT_V(v) BM_PXP_OLnSIZE_HEIGHT
+
+#define HW_PXP_OLnPARAM(_n1)                    HW(PXP_OLnPARAM(_n1))
+#define HWA_PXP_OLnPARAM(_n1)                   (0x8002a000 + 0x220 + (_n1) * 0x40)
+#define HWT_PXP_OLnPARAM(_n1)                   HWIO_32_RW
+#define HWN_PXP_OLnPARAM(_n1)                   PXP_OLnPARAM
+#define HWI_PXP_OLnPARAM(_n1)                   (_n1)
+#define BP_PXP_OLnPARAM_RSVD1                   20
+#define BM_PXP_OLnPARAM_RSVD1                   0xfff00000
+#define BF_PXP_OLnPARAM_RSVD1(v)                (((v) & 0xfff) << 20)
+#define BFM_PXP_OLnPARAM_RSVD1(v)               BM_PXP_OLnPARAM_RSVD1
+#define BF_PXP_OLnPARAM_RSVD1_V(e)              BF_PXP_OLnPARAM_RSVD1(BV_PXP_OLnPARAM_RSVD1__##e)
+#define BFM_PXP_OLnPARAM_RSVD1_V(v)             BM_PXP_OLnPARAM_RSVD1
+#define BP_PXP_OLnPARAM_ROP                     16
+#define BM_PXP_OLnPARAM_ROP                     0xf0000
+#define BV_PXP_OLnPARAM_ROP__MASKOL             0x0
+#define BV_PXP_OLnPARAM_ROP__MASKNOTOL          0x1
+#define BV_PXP_OLnPARAM_ROP__MASKOLNOT          0x2
+#define BV_PXP_OLnPARAM_ROP__MERGEOL            0x3
+#define BV_PXP_OLnPARAM_ROP__MERGENOTOL         0x4
+#define BV_PXP_OLnPARAM_ROP__MERGEOLNOT         0x5
+#define BV_PXP_OLnPARAM_ROP__NOTCOPYOL          0x6
+#define BV_PXP_OLnPARAM_ROP__NOT                0x7
+#define BV_PXP_OLnPARAM_ROP__NOTMASKOL          0x8
+#define BV_PXP_OLnPARAM_ROP__NOTMERGEOL         0x9
+#define BV_PXP_OLnPARAM_ROP__XOROL              0xa
+#define BV_PXP_OLnPARAM_ROP__NOTXOROL           0xb
+#define BF_PXP_OLnPARAM_ROP(v)                  (((v) & 0xf) << 16)
+#define BFM_PXP_OLnPARAM_ROP(v)                 BM_PXP_OLnPARAM_ROP
+#define BF_PXP_OLnPARAM_ROP_V(e)                BF_PXP_OLnPARAM_ROP(BV_PXP_OLnPARAM_ROP__##e)
+#define BFM_PXP_OLnPARAM_ROP_V(v)               BM_PXP_OLnPARAM_ROP
+#define BP_PXP_OLnPARAM_ALPHA                   8
+#define BM_PXP_OLnPARAM_ALPHA                   0xff00
+#define BF_PXP_OLnPARAM_ALPHA(v)                (((v) & 0xff) << 8)
+#define BFM_PXP_OLnPARAM_ALPHA(v)               BM_PXP_OLnPARAM_ALPHA
+#define BF_PXP_OLnPARAM_ALPHA_V(e)              BF_PXP_OLnPARAM_ALPHA(BV_PXP_OLnPARAM_ALPHA__##e)
+#define BFM_PXP_OLnPARAM_ALPHA_V(v)             BM_PXP_OLnPARAM_ALPHA
+#define BP_PXP_OLnPARAM_FORMAT                  4
+#define BM_PXP_OLnPARAM_FORMAT                  0xf0
+#define BV_PXP_OLnPARAM_FORMAT__ARGB8888        0x0
+#define BV_PXP_OLnPARAM_FORMAT__RGB888          0x1
+#define BV_PXP_OLnPARAM_FORMAT__ARGB1555        0x3
+#define BV_PXP_OLnPARAM_FORMAT__RGB565          0x4
+#define BV_PXP_OLnPARAM_FORMAT__RGB555          0x5
+#define BF_PXP_OLnPARAM_FORMAT(v)               (((v) & 0xf) << 4)
+#define BFM_PXP_OLnPARAM_FORMAT(v)              BM_PXP_OLnPARAM_FORMAT
+#define BF_PXP_OLnPARAM_FORMAT_V(e)             BF_PXP_OLnPARAM_FORMAT(BV_PXP_OLnPARAM_FORMAT__##e)
+#define BFM_PXP_OLnPARAM_FORMAT_V(v)            BM_PXP_OLnPARAM_FORMAT
+#define BP_PXP_OLnPARAM_ENABLE_COLORKEY         3
+#define BM_PXP_OLnPARAM_ENABLE_COLORKEY         0x8
+#define BF_PXP_OLnPARAM_ENABLE_COLORKEY(v)      (((v) & 0x1) << 3)
+#define BFM_PXP_OLnPARAM_ENABLE_COLORKEY(v)     BM_PXP_OLnPARAM_ENABLE_COLORKEY
+#define BF_PXP_OLnPARAM_ENABLE_COLORKEY_V(e)    BF_PXP_OLnPARAM_ENABLE_COLORKEY(BV_PXP_OLnPARAM_ENABLE_COLORKEY__##e)
+#define BFM_PXP_OLnPARAM_ENABLE_COLORKEY_V(v)   BM_PXP_OLnPARAM_ENABLE_COLORKEY
+#define BP_PXP_OLnPARAM_ALPHA_CNTL              1
+#define BM_PXP_OLnPARAM_ALPHA_CNTL              0x6
+#define BV_PXP_OLnPARAM_ALPHA_CNTL__Embedded    0x0
+#define BV_PXP_OLnPARAM_ALPHA_CNTL__Override    0x1
+#define BV_PXP_OLnPARAM_ALPHA_CNTL__Multiply    0x2
+#define BV_PXP_OLnPARAM_ALPHA_CNTL__ROPs        0x3
+#define BF_PXP_OLnPARAM_ALPHA_CNTL(v)           (((v) & 0x3) << 1)
+#define BFM_PXP_OLnPARAM_ALPHA_CNTL(v)          BM_PXP_OLnPARAM_ALPHA_CNTL
+#define BF_PXP_OLnPARAM_ALPHA_CNTL_V(e)         BF_PXP_OLnPARAM_ALPHA_CNTL(BV_PXP_OLnPARAM_ALPHA_CNTL__##e)
+#define BFM_PXP_OLnPARAM_ALPHA_CNTL_V(v)        BM_PXP_OLnPARAM_ALPHA_CNTL
+#define BP_PXP_OLnPARAM_ENABLE                  0
+#define BM_PXP_OLnPARAM_ENABLE                  0x1
+#define BF_PXP_OLnPARAM_ENABLE(v)               (((v) & 0x1) << 0)
+#define BFM_PXP_OLnPARAM_ENABLE(v)              BM_PXP_OLnPARAM_ENABLE
+#define BF_PXP_OLnPARAM_ENABLE_V(e)             BF_PXP_OLnPARAM_ENABLE(BV_PXP_OLnPARAM_ENABLE__##e)
+#define BFM_PXP_OLnPARAM_ENABLE_V(v)            BM_PXP_OLnPARAM_ENABLE
+
+#define HW_PXP_OLnPARAM2(_n1)       HW(PXP_OLnPARAM2(_n1))
+#define HWA_PXP_OLnPARAM2(_n1)      (0x8002a000 + 0x230 + (_n1) * 0x40)
+#define HWT_PXP_OLnPARAM2(_n1)      HWIO_32_RW
+#define HWN_PXP_OLnPARAM2(_n1)      PXP_OLnPARAM2
+#define HWI_PXP_OLnPARAM2(_n1)      (_n1)
+#define BP_PXP_OLnPARAM2_RSVD       0
+#define BM_PXP_OLnPARAM2_RSVD       0xffffffff
+#define BF_PXP_OLnPARAM2_RSVD(v)    (((v) & 0xffffffff) << 0)
+#define BFM_PXP_OLnPARAM2_RSVD(v)   BM_PXP_OLnPARAM2_RSVD
+#define BF_PXP_OLnPARAM2_RSVD_V(e)  BF_PXP_OLnPARAM2_RSVD(BV_PXP_OLnPARAM2_RSVD__##e)
+#define BFM_PXP_OLnPARAM2_RSVD_V(v) BM_PXP_OLnPARAM2_RSVD
+
+#endif /* __HEADERGEN_IMX233_PXP_H__*/
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-apbh.h b/firmware/target/arm/imx233/regs/imx233/regs-apbh.h
deleted file mode 100644
index 8787352e89..0000000000
--- a/firmware/target/arm/imx233/regs/imx233/regs-apbh.h
+++ /dev/null
@@ -1,355 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: imx233:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__IMX233__APBH__H__
-#define __HEADERGEN__IMX233__APBH__H__
-
-#define REGS_APBH_BASE (0x80004000)
-
-#define REGS_APBH_VERSION "3.2.0"
-
-/**
- * Register: HW_APBH_CTRL0
- * Address: 0
- * SCT: yes
-*/
-#define HW_APBH_CTRL0                           (*(volatile unsigned long *)(REGS_APBH_BASE + 0x0 + 0x0))
-#define HW_APBH_CTRL0_SET                       (*(volatile unsigned long *)(REGS_APBH_BASE + 0x0 + 0x4))
-#define HW_APBH_CTRL0_CLR                       (*(volatile unsigned long *)(REGS_APBH_BASE + 0x0 + 0x8))
-#define HW_APBH_CTRL0_TOG                       (*(volatile unsigned long *)(REGS_APBH_BASE + 0x0 + 0xc))
-#define BP_APBH_CTRL0_SFTRST                    31
-#define BM_APBH_CTRL0_SFTRST                    0x80000000
-#define BF_APBH_CTRL0_SFTRST(v)                 (((v) << 31) & 0x80000000)
-#define BP_APBH_CTRL0_CLKGATE                   30
-#define BM_APBH_CTRL0_CLKGATE                   0x40000000
-#define BF_APBH_CTRL0_CLKGATE(v)                (((v) << 30) & 0x40000000)
-#define BP_APBH_CTRL0_AHB_BURST8_EN             29
-#define BM_APBH_CTRL0_AHB_BURST8_EN             0x20000000
-#define BF_APBH_CTRL0_AHB_BURST8_EN(v)          (((v) << 29) & 0x20000000)
-#define BP_APBH_CTRL0_APB_BURST4_EN             28
-#define BM_APBH_CTRL0_APB_BURST4_EN             0x10000000
-#define BF_APBH_CTRL0_APB_BURST4_EN(v)          (((v) << 28) & 0x10000000)
-#define BP_APBH_CTRL0_RSVD0                     24
-#define BM_APBH_CTRL0_RSVD0                     0xf000000
-#define BF_APBH_CTRL0_RSVD0(v)                  (((v) << 24) & 0xf000000)
-#define BP_APBH_CTRL0_RESET_CHANNEL             16
-#define BM_APBH_CTRL0_RESET_CHANNEL             0xff0000
-#define BV_APBH_CTRL0_RESET_CHANNEL__SSP1       0x2
-#define BV_APBH_CTRL0_RESET_CHANNEL__SSP2       0x4
-#define BV_APBH_CTRL0_RESET_CHANNEL__ATA        0x10
-#define BV_APBH_CTRL0_RESET_CHANNEL__NAND0      0x10
-#define BV_APBH_CTRL0_RESET_CHANNEL__NAND1      0x20
-#define BV_APBH_CTRL0_RESET_CHANNEL__NAND2      0x40
-#define BV_APBH_CTRL0_RESET_CHANNEL__NAND3      0x80
-#define BF_APBH_CTRL0_RESET_CHANNEL(v)          (((v) << 16) & 0xff0000)
-#define BF_APBH_CTRL0_RESET_CHANNEL_V(v)        ((BV_APBH_CTRL0_RESET_CHANNEL__##v << 16) & 0xff0000)
-#define BP_APBH_CTRL0_CLKGATE_CHANNEL           8
-#define BM_APBH_CTRL0_CLKGATE_CHANNEL           0xff00
-#define BV_APBH_CTRL0_CLKGATE_CHANNEL__SSP1     0x2
-#define BV_APBH_CTRL0_CLKGATE_CHANNEL__SSP2     0x4
-#define BV_APBH_CTRL0_CLKGATE_CHANNEL__ATA      0x10
-#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND0    0x10
-#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND1    0x20
-#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND2    0x40
-#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND3    0x80
-#define BF_APBH_CTRL0_CLKGATE_CHANNEL(v)        (((v) << 8) & 0xff00)
-#define BF_APBH_CTRL0_CLKGATE_CHANNEL_V(v)      ((BV_APBH_CTRL0_CLKGATE_CHANNEL__##v << 8) & 0xff00)
-#define BP_APBH_CTRL0_FREEZE_CHANNEL            0
-#define BM_APBH_CTRL0_FREEZE_CHANNEL            0xff
-#define BV_APBH_CTRL0_FREEZE_CHANNEL__SSP1      0x2
-#define BV_APBH_CTRL0_FREEZE_CHANNEL__SSP2      0x4
-#define BV_APBH_CTRL0_FREEZE_CHANNEL__ATA       0x10
-#define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND0     0x10
-#define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND1     0x20
-#define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND2     0x40
-#define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND3     0x80
-#define BF_APBH_CTRL0_FREEZE_CHANNEL(v)         (((v) << 0) & 0xff)
-#define BF_APBH_CTRL0_FREEZE_CHANNEL_V(v)       ((BV_APBH_CTRL0_FREEZE_CHANNEL__##v << 0) & 0xff)
-
-/**
- * Register: HW_APBH_CTRL1
- * Address: 0x10
- * SCT: yes
-*/
-#define HW_APBH_CTRL1                       (*(volatile unsigned long *)(REGS_APBH_BASE + 0x10 + 0x0))
-#define HW_APBH_CTRL1_SET                   (*(volatile unsigned long *)(REGS_APBH_BASE + 0x10 + 0x4))
-#define HW_APBH_CTRL1_CLR                   (*(volatile unsigned long *)(REGS_APBH_BASE + 0x10 + 0x8))
-#define HW_APBH_CTRL1_TOG                   (*(volatile unsigned long *)(REGS_APBH_BASE + 0x10 + 0xc))
-#define BP_APBH_CTRL1_RSVD1                 24
-#define BM_APBH_CTRL1_RSVD1                 0xff000000
-#define BF_APBH_CTRL1_RSVD1(v)              (((v) << 24) & 0xff000000)
-#define BP_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN    16
-#define BM_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN    0xff0000
-#define BF_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN(v) (((v) << 16) & 0xff0000)
-#define BP_APBH_CTRL1_RSVD0                 8
-#define BM_APBH_CTRL1_RSVD0                 0xff00
-#define BF_APBH_CTRL1_RSVD0(v)              (((v) << 8) & 0xff00)
-#define BP_APBH_CTRL1_CH_CMDCMPLT_IRQ       0
-#define BM_APBH_CTRL1_CH_CMDCMPLT_IRQ       0xff
-#define BF_APBH_CTRL1_CH_CMDCMPLT_IRQ(v)    (((v) << 0) & 0xff)
-
-/**
- * Register: HW_APBH_CTRL2
- * Address: 0x20
- * SCT: yes
-*/
-#define HW_APBH_CTRL2                       (*(volatile unsigned long *)(REGS_APBH_BASE + 0x20 + 0x0))
-#define HW_APBH_CTRL2_SET                   (*(volatile unsigned long *)(REGS_APBH_BASE + 0x20 + 0x4))
-#define HW_APBH_CTRL2_CLR                   (*(volatile unsigned long *)(REGS_APBH_BASE + 0x20 + 0x8))
-#define HW_APBH_CTRL2_TOG                   (*(volatile unsigned long *)(REGS_APBH_BASE + 0x20 + 0xc))
-#define BP_APBH_CTRL2_RSVD1                 24
-#define BM_APBH_CTRL2_RSVD1                 0xff000000
-#define BF_APBH_CTRL2_RSVD1(v)              (((v) << 24) & 0xff000000)
-#define BP_APBH_CTRL2_CH_ERROR_STATUS       16
-#define BM_APBH_CTRL2_CH_ERROR_STATUS       0xff0000
-#define BF_APBH_CTRL2_CH_ERROR_STATUS(v)    (((v) << 16) & 0xff0000)
-#define BP_APBH_CTRL2_RSVD0                 8
-#define BM_APBH_CTRL2_RSVD0                 0xff00
-#define BF_APBH_CTRL2_RSVD0(v)              (((v) << 8) & 0xff00)
-#define BP_APBH_CTRL2_CH_ERROR_IRQ          0
-#define BM_APBH_CTRL2_CH_ERROR_IRQ          0xff
-#define BF_APBH_CTRL2_CH_ERROR_IRQ(v)       (((v) << 0) & 0xff)
-
-/**
- * Register: HW_APBH_DEVSEL
- * Address: 0x30
- * SCT: no
-*/
-#define HW_APBH_DEVSEL          (*(volatile unsigned long *)(REGS_APBH_BASE + 0x30))
-#define BP_APBH_DEVSEL_CH7      28
-#define BM_APBH_DEVSEL_CH7      0xf0000000
-#define BF_APBH_DEVSEL_CH7(v)   (((v) << 28) & 0xf0000000)
-#define BP_APBH_DEVSEL_CH6      24
-#define BM_APBH_DEVSEL_CH6      0xf000000
-#define BF_APBH_DEVSEL_CH6(v)   (((v) << 24) & 0xf000000)
-#define BP_APBH_DEVSEL_CH5      20
-#define BM_APBH_DEVSEL_CH5      0xf00000
-#define BF_APBH_DEVSEL_CH5(v)   (((v) << 20) & 0xf00000)
-#define BP_APBH_DEVSEL_CH4      16
-#define BM_APBH_DEVSEL_CH4      0xf0000
-#define BF_APBH_DEVSEL_CH4(v)   (((v) << 16) & 0xf0000)
-#define BP_APBH_DEVSEL_CH3      12
-#define BM_APBH_DEVSEL_CH3      0xf000
-#define BF_APBH_DEVSEL_CH3(v)   (((v) << 12) & 0xf000)
-#define BP_APBH_DEVSEL_CH2      8
-#define BM_APBH_DEVSEL_CH2      0xf00
-#define BF_APBH_DEVSEL_CH2(v)   (((v) << 8) & 0xf00)
-#define BP_APBH_DEVSEL_CH1      4
-#define BM_APBH_DEVSEL_CH1      0xf0
-#define BF_APBH_DEVSEL_CH1(v)   (((v) << 4) & 0xf0)
-#define BP_APBH_DEVSEL_CH0      0
-#define BM_APBH_DEVSEL_CH0      0xf
-#define BF_APBH_DEVSEL_CH0(v)   (((v) << 0) & 0xf)
-
-/**
- * Register: HW_APBH_CHn_CURCMDAR
- * Address: 0x40+n*0x70
- * SCT: no
-*/
-#define HW_APBH_CHn_CURCMDAR(n)             (*(volatile unsigned long *)(REGS_APBH_BASE + 0x40+(n)*0x70))
-#define BP_APBH_CHn_CURCMDAR_CMD_ADDR       0
-#define BM_APBH_CHn_CURCMDAR_CMD_ADDR       0xffffffff
-#define BF_APBH_CHn_CURCMDAR_CMD_ADDR(v)    (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_APBH_CHn_NXTCMDAR
- * Address: 0x50+n*0x70
- * SCT: no
-*/
-#define HW_APBH_CHn_NXTCMDAR(n)             (*(volatile unsigned long *)(REGS_APBH_BASE + 0x50+(n)*0x70))
-#define BP_APBH_CHn_NXTCMDAR_CMD_ADDR       0
-#define BM_APBH_CHn_NXTCMDAR_CMD_ADDR       0xffffffff
-#define BF_APBH_CHn_NXTCMDAR_CMD_ADDR(v)    (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_APBH_CHn_CMD
- * Address: 0x60+n*0x70
- * SCT: no
-*/
-#define HW_APBH_CHn_CMD(n)                      (*(volatile unsigned long *)(REGS_APBH_BASE + 0x60+(n)*0x70))
-#define BP_APBH_CHn_CMD_XFER_COUNT              16
-#define BM_APBH_CHn_CMD_XFER_COUNT              0xffff0000
-#define BF_APBH_CHn_CMD_XFER_COUNT(v)           (((v) << 16) & 0xffff0000)
-#define BP_APBH_CHn_CMD_CMDWORDS                12
-#define BM_APBH_CHn_CMD_CMDWORDS                0xf000
-#define BF_APBH_CHn_CMD_CMDWORDS(v)             (((v) << 12) & 0xf000)
-#define BP_APBH_CHn_CMD_RSVD1                   9
-#define BM_APBH_CHn_CMD_RSVD1                   0xe00
-#define BF_APBH_CHn_CMD_RSVD1(v)                (((v) << 9) & 0xe00)
-#define BP_APBH_CHn_CMD_HALTONTERMINATE         8
-#define BM_APBH_CHn_CMD_HALTONTERMINATE         0x100
-#define BF_APBH_CHn_CMD_HALTONTERMINATE(v)      (((v) << 8) & 0x100)
-#define BP_APBH_CHn_CMD_WAIT4ENDCMD             7
-#define BM_APBH_CHn_CMD_WAIT4ENDCMD             0x80
-#define BF_APBH_CHn_CMD_WAIT4ENDCMD(v)          (((v) << 7) & 0x80)
-#define BP_APBH_CHn_CMD_SEMAPHORE               6
-#define BM_APBH_CHn_CMD_SEMAPHORE               0x40
-#define BF_APBH_CHn_CMD_SEMAPHORE(v)            (((v) << 6) & 0x40)
-#define BP_APBH_CHn_CMD_NANDWAIT4READY          5
-#define BM_APBH_CHn_CMD_NANDWAIT4READY          0x20
-#define BF_APBH_CHn_CMD_NANDWAIT4READY(v)       (((v) << 5) & 0x20)
-#define BP_APBH_CHn_CMD_NANDLOCK                4
-#define BM_APBH_CHn_CMD_NANDLOCK                0x10
-#define BF_APBH_CHn_CMD_NANDLOCK(v)             (((v) << 4) & 0x10)
-#define BP_APBH_CHn_CMD_IRQONCMPLT              3
-#define BM_APBH_CHn_CMD_IRQONCMPLT              0x8
-#define BF_APBH_CHn_CMD_IRQONCMPLT(v)           (((v) << 3) & 0x8)
-#define BP_APBH_CHn_CMD_CHAIN                   2
-#define BM_APBH_CHn_CMD_CHAIN                   0x4
-#define BF_APBH_CHn_CMD_CHAIN(v)                (((v) << 2) & 0x4)
-#define BP_APBH_CHn_CMD_COMMAND                 0
-#define BM_APBH_CHn_CMD_COMMAND                 0x3
-#define BV_APBH_CHn_CMD_COMMAND__NO_DMA_XFER    0x0
-#define BV_APBH_CHn_CMD_COMMAND__DMA_WRITE      0x1
-#define BV_APBH_CHn_CMD_COMMAND__DMA_READ       0x2
-#define BV_APBH_CHn_CMD_COMMAND__DMA_SENSE      0x3
-#define BF_APBH_CHn_CMD_COMMAND(v)              (((v) << 0) & 0x3)
-#define BF_APBH_CHn_CMD_COMMAND_V(v)            ((BV_APBH_CHn_CMD_COMMAND__##v << 0) & 0x3)
-
-/**
- * Register: HW_APBH_CHn_BAR
- * Address: 0x70+n*0x70
- * SCT: no
-*/
-#define HW_APBH_CHn_BAR(n)          (*(volatile unsigned long *)(REGS_APBH_BASE + 0x70+(n)*0x70))
-#define BP_APBH_CHn_BAR_ADDRESS     0
-#define BM_APBH_CHn_BAR_ADDRESS     0xffffffff
-#define BF_APBH_CHn_BAR_ADDRESS(v)  (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_APBH_CHn_SEMA
- * Address: 0x80+n*0x70
- * SCT: no
-*/
-#define HW_APBH_CHn_SEMA(n)                 (*(volatile unsigned long *)(REGS_APBH_BASE + 0x80+(n)*0x70))
-#define BP_APBH_CHn_SEMA_RSVD2              24
-#define BM_APBH_CHn_SEMA_RSVD2              0xff000000
-#define BF_APBH_CHn_SEMA_RSVD2(v)           (((v) << 24) & 0xff000000)
-#define BP_APBH_CHn_SEMA_PHORE              16
-#define BM_APBH_CHn_SEMA_PHORE              0xff0000
-#define BF_APBH_CHn_SEMA_PHORE(v)           (((v) << 16) & 0xff0000)
-#define BP_APBH_CHn_SEMA_RSVD1              8
-#define BM_APBH_CHn_SEMA_RSVD1              0xff00
-#define BF_APBH_CHn_SEMA_RSVD1(v)           (((v) << 8) & 0xff00)
-#define BP_APBH_CHn_SEMA_INCREMENT_SEMA     0
-#define BM_APBH_CHn_SEMA_INCREMENT_SEMA     0xff
-#define BF_APBH_CHn_SEMA_INCREMENT_SEMA(v)  (((v) << 0) & 0xff)
-
-/**
- * Register: HW_APBH_CHn_DEBUG1
- * Address: 0x90+n*0x70
- * SCT: no
-*/
-#define HW_APBH_CHn_DEBUG1(n)                               (*(volatile unsigned long *)(REGS_APBH_BASE + 0x90+(n)*0x70))
-#define BP_APBH_CHn_DEBUG1_REQ                              31
-#define BM_APBH_CHn_DEBUG1_REQ                              0x80000000
-#define BF_APBH_CHn_DEBUG1_REQ(v)                           (((v) << 31) & 0x80000000)
-#define BP_APBH_CHn_DEBUG1_BURST                            30
-#define BM_APBH_CHn_DEBUG1_BURST                            0x40000000
-#define BF_APBH_CHn_DEBUG1_BURST(v)                         (((v) << 30) & 0x40000000)
-#define BP_APBH_CHn_DEBUG1_KICK                             29
-#define BM_APBH_CHn_DEBUG1_KICK                             0x20000000
-#define BF_APBH_CHn_DEBUG1_KICK(v)                          (((v) << 29) & 0x20000000)
-#define BP_APBH_CHn_DEBUG1_END                              28
-#define BM_APBH_CHn_DEBUG1_END                              0x10000000
-#define BF_APBH_CHn_DEBUG1_END(v)                           (((v) << 28) & 0x10000000)
-#define BP_APBH_CHn_DEBUG1_SENSE                            27
-#define BM_APBH_CHn_DEBUG1_SENSE                            0x8000000
-#define BF_APBH_CHn_DEBUG1_SENSE(v)                         (((v) << 27) & 0x8000000)
-#define BP_APBH_CHn_DEBUG1_READY                            26
-#define BM_APBH_CHn_DEBUG1_READY                            0x4000000
-#define BF_APBH_CHn_DEBUG1_READY(v)                         (((v) << 26) & 0x4000000)
-#define BP_APBH_CHn_DEBUG1_LOCK                             25
-#define BM_APBH_CHn_DEBUG1_LOCK                             0x2000000
-#define BF_APBH_CHn_DEBUG1_LOCK(v)                          (((v) << 25) & 0x2000000)
-#define BP_APBH_CHn_DEBUG1_NEXTCMDADDRVALID                 24
-#define BM_APBH_CHn_DEBUG1_NEXTCMDADDRVALID                 0x1000000
-#define BF_APBH_CHn_DEBUG1_NEXTCMDADDRVALID(v)              (((v) << 24) & 0x1000000)
-#define BP_APBH_CHn_DEBUG1_RD_FIFO_EMPTY                    23
-#define BM_APBH_CHn_DEBUG1_RD_FIFO_EMPTY                    0x800000
-#define BF_APBH_CHn_DEBUG1_RD_FIFO_EMPTY(v)                 (((v) << 23) & 0x800000)
-#define BP_APBH_CHn_DEBUG1_RD_FIFO_FULL                     22
-#define BM_APBH_CHn_DEBUG1_RD_FIFO_FULL                     0x400000
-#define BF_APBH_CHn_DEBUG1_RD_FIFO_FULL(v)                  (((v) << 22) & 0x400000)
-#define BP_APBH_CHn_DEBUG1_WR_FIFO_EMPTY                    21
-#define BM_APBH_CHn_DEBUG1_WR_FIFO_EMPTY                    0x200000
-#define BF_APBH_CHn_DEBUG1_WR_FIFO_EMPTY(v)                 (((v) << 21) & 0x200000)
-#define BP_APBH_CHn_DEBUG1_WR_FIFO_FULL                     20
-#define BM_APBH_CHn_DEBUG1_WR_FIFO_FULL                     0x100000
-#define BF_APBH_CHn_DEBUG1_WR_FIFO_FULL(v)                  (((v) << 20) & 0x100000)
-#define BP_APBH_CHn_DEBUG1_RSVD1                            5
-#define BM_APBH_CHn_DEBUG1_RSVD1                            0xfffe0
-#define BF_APBH_CHn_DEBUG1_RSVD1(v)                         (((v) << 5) & 0xfffe0)
-#define BP_APBH_CHn_DEBUG1_STATEMACHINE                     0
-#define BM_APBH_CHn_DEBUG1_STATEMACHINE                     0x1f
-#define BV_APBH_CHn_DEBUG1_STATEMACHINE__IDLE               0x0
-#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD1           0x1
-#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD3           0x2
-#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD2           0x3
-#define BV_APBH_CHn_DEBUG1_STATEMACHINE__XFER_DECODE        0x4
-#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_WAIT           0x5
-#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD4           0x6
-#define BV_APBH_CHn_DEBUG1_STATEMACHINE__PIO_REQ            0x7
-#define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_FLUSH         0x8
-#define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_WAIT          0x9
-#define BV_APBH_CHn_DEBUG1_STATEMACHINE__WRITE              0xc
-#define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_REQ           0xd
-#define BV_APBH_CHn_DEBUG1_STATEMACHINE__CHECK_CHAIN        0xe
-#define BV_APBH_CHn_DEBUG1_STATEMACHINE__XFER_COMPLETE      0xf
-#define BV_APBH_CHn_DEBUG1_STATEMACHINE__TERMINATE          0x14
-#define BV_APBH_CHn_DEBUG1_STATEMACHINE__WAIT_END           0x15
-#define BV_APBH_CHn_DEBUG1_STATEMACHINE__WRITE_WAIT         0x1c
-#define BV_APBH_CHn_DEBUG1_STATEMACHINE__HALT_AFTER_TERM    0x1d
-#define BV_APBH_CHn_DEBUG1_STATEMACHINE__CHECK_WAIT         0x1e
-#define BF_APBH_CHn_DEBUG1_STATEMACHINE(v)                  (((v) << 0) & 0x1f)
-#define BF_APBH_CHn_DEBUG1_STATEMACHINE_V(v)                ((BV_APBH_CHn_DEBUG1_STATEMACHINE__##v << 0) & 0x1f)
-
-/**
- * Register: HW_APBH_CHn_DEBUG2
- * Address: 0xa0+n*0x70
- * SCT: no
-*/
-#define HW_APBH_CHn_DEBUG2(n)           (*(volatile unsigned long *)(REGS_APBH_BASE + 0xa0+(n)*0x70))
-#define BP_APBH_CHn_DEBUG2_APB_BYTES    16
-#define BM_APBH_CHn_DEBUG2_APB_BYTES    0xffff0000
-#define BF_APBH_CHn_DEBUG2_APB_BYTES(v) (((v) << 16) & 0xffff0000)
-#define BP_APBH_CHn_DEBUG2_AHB_BYTES    0
-#define BM_APBH_CHn_DEBUG2_AHB_BYTES    0xffff
-#define BF_APBH_CHn_DEBUG2_AHB_BYTES(v) (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_APBH_VERSION
- * Address: 0x3f0
- * SCT: no
-*/
-#define HW_APBH_VERSION             (*(volatile unsigned long *)(REGS_APBH_BASE + 0x3f0))
-#define BP_APBH_VERSION_MAJOR       24
-#define BM_APBH_VERSION_MAJOR       0xff000000
-#define BF_APBH_VERSION_MAJOR(v)    (((v) << 24) & 0xff000000)
-#define BP_APBH_VERSION_MINOR       16
-#define BM_APBH_VERSION_MINOR       0xff0000
-#define BF_APBH_VERSION_MINOR(v)    (((v) << 16) & 0xff0000)
-#define BP_APBH_VERSION_STEP        0
-#define BM_APBH_VERSION_STEP        0xffff
-#define BF_APBH_VERSION_STEP(v)     (((v) << 0) & 0xffff)
-
-#endif /* __HEADERGEN__IMX233__APBH__H__ */
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-apbx.h b/firmware/target/arm/imx233/regs/imx233/regs-apbx.h
deleted file mode 100644
index 6789cf4a4d..0000000000
--- a/firmware/target/arm/imx233/regs/imx233/regs-apbx.h
+++ /dev/null
@@ -1,366 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: imx233:3.2.1
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__IMX233__APBX__H__
-#define __HEADERGEN__IMX233__APBX__H__
-
-#define REGS_APBX_BASE (0x80024000)
-
-#define REGS_APBX_VERSION "3.2.1"
-
-/**
- * Register: HW_APBX_CTRL0
- * Address: 0
- * SCT: yes
-*/
-#define HW_APBX_CTRL0               (*(volatile unsigned long *)(REGS_APBX_BASE + 0x0 + 0x0))
-#define HW_APBX_CTRL0_SET           (*(volatile unsigned long *)(REGS_APBX_BASE + 0x0 + 0x4))
-#define HW_APBX_CTRL0_CLR           (*(volatile unsigned long *)(REGS_APBX_BASE + 0x0 + 0x8))
-#define HW_APBX_CTRL0_TOG           (*(volatile unsigned long *)(REGS_APBX_BASE + 0x0 + 0xc))
-#define BP_APBX_CTRL0_SFTRST        31
-#define BM_APBX_CTRL0_SFTRST        0x80000000
-#define BF_APBX_CTRL0_SFTRST(v)     (((v) << 31) & 0x80000000)
-#define BP_APBX_CTRL0_CLKGATE       30
-#define BM_APBX_CTRL0_CLKGATE       0x40000000
-#define BF_APBX_CTRL0_CLKGATE(v)    (((v) << 30) & 0x40000000)
-#define BP_APBX_CTRL0_RSVD0         0
-#define BM_APBX_CTRL0_RSVD0         0x3fffffff
-#define BF_APBX_CTRL0_RSVD0(v)      (((v) << 0) & 0x3fffffff)
-
-/**
- * Register: HW_APBX_CTRL1
- * Address: 0x10
- * SCT: yes
-*/
-#define HW_APBX_CTRL1                       (*(volatile unsigned long *)(REGS_APBX_BASE + 0x10 + 0x0))
-#define HW_APBX_CTRL1_SET                   (*(volatile unsigned long *)(REGS_APBX_BASE + 0x10 + 0x4))
-#define HW_APBX_CTRL1_CLR                   (*(volatile unsigned long *)(REGS_APBX_BASE + 0x10 + 0x8))
-#define HW_APBX_CTRL1_TOG                   (*(volatile unsigned long *)(REGS_APBX_BASE + 0x10 + 0xc))
-#define BP_APBX_CTRL1_CH_CMDCMPLT_IRQ_EN    16
-#define BM_APBX_CTRL1_CH_CMDCMPLT_IRQ_EN    0xffff0000
-#define BF_APBX_CTRL1_CH_CMDCMPLT_IRQ_EN(v) (((v) << 16) & 0xffff0000)
-#define BP_APBX_CTRL1_CH_CMDCMPLT_IRQ       0
-#define BM_APBX_CTRL1_CH_CMDCMPLT_IRQ       0xffff
-#define BF_APBX_CTRL1_CH_CMDCMPLT_IRQ(v)    (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_APBX_CTRL2
- * Address: 0x20
- * SCT: yes
-*/
-#define HW_APBX_CTRL2                       (*(volatile unsigned long *)(REGS_APBX_BASE + 0x20 + 0x0))
-#define HW_APBX_CTRL2_SET                   (*(volatile unsigned long *)(REGS_APBX_BASE + 0x20 + 0x4))
-#define HW_APBX_CTRL2_CLR                   (*(volatile unsigned long *)(REGS_APBX_BASE + 0x20 + 0x8))
-#define HW_APBX_CTRL2_TOG                   (*(volatile unsigned long *)(REGS_APBX_BASE + 0x20 + 0xc))
-#define BP_APBX_CTRL2_CH_ERROR_STATUS       16
-#define BM_APBX_CTRL2_CH_ERROR_STATUS       0xffff0000
-#define BF_APBX_CTRL2_CH_ERROR_STATUS(v)    (((v) << 16) & 0xffff0000)
-#define BP_APBX_CTRL2_CH_ERROR_IRQ          0
-#define BM_APBX_CTRL2_CH_ERROR_IRQ          0xffff
-#define BF_APBX_CTRL2_CH_ERROR_IRQ(v)       (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_APBX_CHANNEL_CTRL
- * Address: 0x30
- * SCT: yes
-*/
-#define HW_APBX_CHANNEL_CTRL                            (*(volatile unsigned long *)(REGS_APBX_BASE + 0x30 + 0x0))
-#define HW_APBX_CHANNEL_CTRL_SET                        (*(volatile unsigned long *)(REGS_APBX_BASE + 0x30 + 0x4))
-#define HW_APBX_CHANNEL_CTRL_CLR                        (*(volatile unsigned long *)(REGS_APBX_BASE + 0x30 + 0x8))
-#define HW_APBX_CHANNEL_CTRL_TOG                        (*(volatile unsigned long *)(REGS_APBX_BASE + 0x30 + 0xc))
-#define BP_APBX_CHANNEL_CTRL_RESET_CHANNEL              16
-#define BM_APBX_CHANNEL_CTRL_RESET_CHANNEL              0xffff0000
-#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__AUDIOIN     0x1
-#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__AUDIOOUT    0x2
-#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__SPDIF_TX    0x4
-#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__I2C         0x8
-#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__SAIF1       0x10
-#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__DRI         0x20
-#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__IRDA_RX     0x40
-#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__UART0_RX    0x40
-#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__IRDA_TX     0x80
-#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__UART0_TX    0x80
-#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__UART1_RX    0x100
-#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__UART1_TX    0x200
-#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__SAIF2       0x400
-#define BF_APBX_CHANNEL_CTRL_RESET_CHANNEL(v)           (((v) << 16) & 0xffff0000)
-#define BF_APBX_CHANNEL_CTRL_RESET_CHANNEL_V(v)         ((BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__##v << 16) & 0xffff0000)
-#define BP_APBX_CHANNEL_CTRL_FREEZE_CHANNEL             0
-#define BM_APBX_CHANNEL_CTRL_FREEZE_CHANNEL             0xffff
-#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__AUDIOIN    0x1
-#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__AUDIOOUT   0x2
-#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__SPDIF_TX   0x4
-#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__I2C        0x8
-#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__SAIF1      0x10
-#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__DRI        0x20
-#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__IRDA_RX    0x40
-#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__UART0_RX   0x40
-#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__IRDA_TX    0x80
-#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__UART0_TX   0x80
-#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__UART1_RX   0x100
-#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__UART1_TX   0x200
-#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__SAIF2      0x400
-#define BF_APBX_CHANNEL_CTRL_FREEZE_CHANNEL(v)          (((v) << 0) & 0xffff)
-#define BF_APBX_CHANNEL_CTRL_FREEZE_CHANNEL_V(v)        ((BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__##v << 0) & 0xffff)
-
-/**
- * Register: HW_APBX_DEVSEL
- * Address: 0x40
- * SCT: no
-*/
-#define HW_APBX_DEVSEL                  (*(volatile unsigned long *)(REGS_APBX_BASE + 0x40))
-#define BP_APBX_DEVSEL_CH15             30
-#define BM_APBX_DEVSEL_CH15             0xc0000000
-#define BF_APBX_DEVSEL_CH15(v)          (((v) << 30) & 0xc0000000)
-#define BP_APBX_DEVSEL_CH14             28
-#define BM_APBX_DEVSEL_CH14             0x30000000
-#define BF_APBX_DEVSEL_CH14(v)          (((v) << 28) & 0x30000000)
-#define BP_APBX_DEVSEL_CH13             26
-#define BM_APBX_DEVSEL_CH13             0xc000000
-#define BF_APBX_DEVSEL_CH13(v)          (((v) << 26) & 0xc000000)
-#define BP_APBX_DEVSEL_CH12             24
-#define BM_APBX_DEVSEL_CH12             0x3000000
-#define BF_APBX_DEVSEL_CH12(v)          (((v) << 24) & 0x3000000)
-#define BP_APBX_DEVSEL_CH11             22
-#define BM_APBX_DEVSEL_CH11             0xc00000
-#define BF_APBX_DEVSEL_CH11(v)          (((v) << 22) & 0xc00000)
-#define BP_APBX_DEVSEL_CH10             20
-#define BM_APBX_DEVSEL_CH10             0x300000
-#define BF_APBX_DEVSEL_CH10(v)          (((v) << 20) & 0x300000)
-#define BP_APBX_DEVSEL_CH9              18
-#define BM_APBX_DEVSEL_CH9              0xc0000
-#define BF_APBX_DEVSEL_CH9(v)           (((v) << 18) & 0xc0000)
-#define BP_APBX_DEVSEL_CH8              16
-#define BM_APBX_DEVSEL_CH8              0x30000
-#define BF_APBX_DEVSEL_CH8(v)           (((v) << 16) & 0x30000)
-#define BP_APBX_DEVSEL_CH7              14
-#define BM_APBX_DEVSEL_CH7              0xc000
-#define BV_APBX_DEVSEL_CH7__USE_I2C1    0x0
-#define BV_APBX_DEVSEL_CH7__USE_IRDA    0x1
-#define BF_APBX_DEVSEL_CH7(v)           (((v) << 14) & 0xc000)
-#define BF_APBX_DEVSEL_CH7_V(v)         ((BV_APBX_DEVSEL_CH7__##v << 14) & 0xc000)
-#define BP_APBX_DEVSEL_CH6              12
-#define BM_APBX_DEVSEL_CH6              0x3000
-#define BV_APBX_DEVSEL_CH6__USE_SAIF1   0x0
-#define BV_APBX_DEVSEL_CH6__USE_IRDA    0x1
-#define BF_APBX_DEVSEL_CH6(v)           (((v) << 12) & 0x3000)
-#define BF_APBX_DEVSEL_CH6_V(v)         ((BV_APBX_DEVSEL_CH6__##v << 12) & 0x3000)
-#define BP_APBX_DEVSEL_CH5              10
-#define BM_APBX_DEVSEL_CH5              0xc00
-#define BF_APBX_DEVSEL_CH5(v)           (((v) << 10) & 0xc00)
-#define BP_APBX_DEVSEL_CH4              8
-#define BM_APBX_DEVSEL_CH4              0x300
-#define BF_APBX_DEVSEL_CH4(v)           (((v) << 8) & 0x300)
-#define BP_APBX_DEVSEL_CH3              6
-#define BM_APBX_DEVSEL_CH3              0xc0
-#define BF_APBX_DEVSEL_CH3(v)           (((v) << 6) & 0xc0)
-#define BP_APBX_DEVSEL_CH2              4
-#define BM_APBX_DEVSEL_CH2              0x30
-#define BF_APBX_DEVSEL_CH2(v)           (((v) << 4) & 0x30)
-#define BP_APBX_DEVSEL_CH1              2
-#define BM_APBX_DEVSEL_CH1              0xc
-#define BF_APBX_DEVSEL_CH1(v)           (((v) << 2) & 0xc)
-#define BP_APBX_DEVSEL_CH0              0
-#define BM_APBX_DEVSEL_CH0              0x3
-#define BF_APBX_DEVSEL_CH0(v)           (((v) << 0) & 0x3)
-
-/**
- * Register: HW_APBX_CHn_CURCMDAR
- * Address: 0x100+n*0x70
- * SCT: no
-*/
-#define HW_APBX_CHn_CURCMDAR(n)             (*(volatile unsigned long *)(REGS_APBX_BASE + 0x100+(n)*0x70))
-#define BP_APBX_CHn_CURCMDAR_CMD_ADDR       0
-#define BM_APBX_CHn_CURCMDAR_CMD_ADDR       0xffffffff
-#define BF_APBX_CHn_CURCMDAR_CMD_ADDR(v)    (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_APBX_CHn_NXTCMDAR
- * Address: 0x110+n*0x70
- * SCT: no
-*/
-#define HW_APBX_CHn_NXTCMDAR(n)             (*(volatile unsigned long *)(REGS_APBX_BASE + 0x110+(n)*0x70))
-#define BP_APBX_CHn_NXTCMDAR_CMD_ADDR       0
-#define BM_APBX_CHn_NXTCMDAR_CMD_ADDR       0xffffffff
-#define BF_APBX_CHn_NXTCMDAR_CMD_ADDR(v)    (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_APBX_CHn_CMD
- * Address: 0x120+n*0x70
- * SCT: no
-*/
-#define HW_APBX_CHn_CMD(n)                      (*(volatile unsigned long *)(REGS_APBX_BASE + 0x120+(n)*0x70))
-#define BP_APBX_CHn_CMD_XFER_COUNT              16
-#define BM_APBX_CHn_CMD_XFER_COUNT              0xffff0000
-#define BF_APBX_CHn_CMD_XFER_COUNT(v)           (((v) << 16) & 0xffff0000)
-#define BP_APBX_CHn_CMD_CMDWORDS                12
-#define BM_APBX_CHn_CMD_CMDWORDS                0xf000
-#define BF_APBX_CHn_CMD_CMDWORDS(v)             (((v) << 12) & 0xf000)
-#define BP_APBX_CHn_CMD_RSVD1                   9
-#define BM_APBX_CHn_CMD_RSVD1                   0xe00
-#define BF_APBX_CHn_CMD_RSVD1(v)                (((v) << 9) & 0xe00)
-#define BP_APBX_CHn_CMD_HALTONTERMINATE         8
-#define BM_APBX_CHn_CMD_HALTONTERMINATE         0x100
-#define BF_APBX_CHn_CMD_HALTONTERMINATE(v)      (((v) << 8) & 0x100)
-#define BP_APBX_CHn_CMD_WAIT4ENDCMD             7
-#define BM_APBX_CHn_CMD_WAIT4ENDCMD             0x80
-#define BF_APBX_CHn_CMD_WAIT4ENDCMD(v)          (((v) << 7) & 0x80)
-#define BP_APBX_CHn_CMD_SEMAPHORE               6
-#define BM_APBX_CHn_CMD_SEMAPHORE               0x40
-#define BF_APBX_CHn_CMD_SEMAPHORE(v)            (((v) << 6) & 0x40)
-#define BP_APBX_CHn_CMD_RSVD0                   4
-#define BM_APBX_CHn_CMD_RSVD0                   0x30
-#define BF_APBX_CHn_CMD_RSVD0(v)                (((v) << 4) & 0x30)
-#define BP_APBX_CHn_CMD_IRQONCMPLT              3
-#define BM_APBX_CHn_CMD_IRQONCMPLT              0x8
-#define BF_APBX_CHn_CMD_IRQONCMPLT(v)           (((v) << 3) & 0x8)
-#define BP_APBX_CHn_CMD_CHAIN                   2
-#define BM_APBX_CHn_CMD_CHAIN                   0x4
-#define BF_APBX_CHn_CMD_CHAIN(v)                (((v) << 2) & 0x4)
-#define BP_APBX_CHn_CMD_COMMAND                 0
-#define BM_APBX_CHn_CMD_COMMAND                 0x3
-#define BV_APBX_CHn_CMD_COMMAND__NO_DMA_XFER    0x0
-#define BV_APBX_CHn_CMD_COMMAND__DMA_WRITE      0x1
-#define BV_APBX_CHn_CMD_COMMAND__DMA_READ       0x2
-#define BF_APBX_CHn_CMD_COMMAND(v)              (((v) << 0) & 0x3)
-#define BF_APBX_CHn_CMD_COMMAND_V(v)            ((BV_APBX_CHn_CMD_COMMAND__##v << 0) & 0x3)
-
-/**
- * Register: HW_APBX_CHn_BAR
- * Address: 0x130+n*0x70
- * SCT: no
-*/
-#define HW_APBX_CHn_BAR(n)          (*(volatile unsigned long *)(REGS_APBX_BASE + 0x130+(n)*0x70))
-#define BP_APBX_CHn_BAR_ADDRESS     0
-#define BM_APBX_CHn_BAR_ADDRESS     0xffffffff
-#define BF_APBX_CHn_BAR_ADDRESS(v)  (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_APBX_CHn_SEMA
- * Address: 0x140+n*0x70
- * SCT: no
-*/
-#define HW_APBX_CHn_SEMA(n)                 (*(volatile unsigned long *)(REGS_APBX_BASE + 0x140+(n)*0x70))
-#define BP_APBX_CHn_SEMA_RSVD2              24
-#define BM_APBX_CHn_SEMA_RSVD2              0xff000000
-#define BF_APBX_CHn_SEMA_RSVD2(v)           (((v) << 24) & 0xff000000)
-#define BP_APBX_CHn_SEMA_PHORE              16
-#define BM_APBX_CHn_SEMA_PHORE              0xff0000
-#define BF_APBX_CHn_SEMA_PHORE(v)           (((v) << 16) & 0xff0000)
-#define BP_APBX_CHn_SEMA_RSVD1              8
-#define BM_APBX_CHn_SEMA_RSVD1              0xff00
-#define BF_APBX_CHn_SEMA_RSVD1(v)           (((v) << 8) & 0xff00)
-#define BP_APBX_CHn_SEMA_INCREMENT_SEMA     0
-#define BM_APBX_CHn_SEMA_INCREMENT_SEMA     0xff
-#define BF_APBX_CHn_SEMA_INCREMENT_SEMA(v)  (((v) << 0) & 0xff)
-
-/**
- * Register: HW_APBX_CHn_DEBUG1
- * Address: 0x150+n*0x70
- * SCT: no
-*/
-#define HW_APBX_CHn_DEBUG1(n)                           (*(volatile unsigned long *)(REGS_APBX_BASE + 0x150+(n)*0x70))
-#define BP_APBX_CHn_DEBUG1_REQ                          31
-#define BM_APBX_CHn_DEBUG1_REQ                          0x80000000
-#define BF_APBX_CHn_DEBUG1_REQ(v)                       (((v) << 31) & 0x80000000)
-#define BP_APBX_CHn_DEBUG1_BURST                        30
-#define BM_APBX_CHn_DEBUG1_BURST                        0x40000000
-#define BF_APBX_CHn_DEBUG1_BURST(v)                     (((v) << 30) & 0x40000000)
-#define BP_APBX_CHn_DEBUG1_KICK                         29
-#define BM_APBX_CHn_DEBUG1_KICK                         0x20000000
-#define BF_APBX_CHn_DEBUG1_KICK(v)                      (((v) << 29) & 0x20000000)
-#define BP_APBX_CHn_DEBUG1_END                          28
-#define BM_APBX_CHn_DEBUG1_END                          0x10000000
-#define BF_APBX_CHn_DEBUG1_END(v)                       (((v) << 28) & 0x10000000)
-#define BP_APBX_CHn_DEBUG1_RSVD2                        25
-#define BM_APBX_CHn_DEBUG1_RSVD2                        0xe000000
-#define BF_APBX_CHn_DEBUG1_RSVD2(v)                     (((v) << 25) & 0xe000000)
-#define BP_APBX_CHn_DEBUG1_NEXTCMDADDRVALID             24
-#define BM_APBX_CHn_DEBUG1_NEXTCMDADDRVALID             0x1000000
-#define BF_APBX_CHn_DEBUG1_NEXTCMDADDRVALID(v)          (((v) << 24) & 0x1000000)
-#define BP_APBX_CHn_DEBUG1_RD_FIFO_EMPTY                23
-#define BM_APBX_CHn_DEBUG1_RD_FIFO_EMPTY                0x800000
-#define BF_APBX_CHn_DEBUG1_RD_FIFO_EMPTY(v)             (((v) << 23) & 0x800000)
-#define BP_APBX_CHn_DEBUG1_RD_FIFO_FULL                 22
-#define BM_APBX_CHn_DEBUG1_RD_FIFO_FULL                 0x400000
-#define BF_APBX_CHn_DEBUG1_RD_FIFO_FULL(v)              (((v) << 22) & 0x400000)
-#define BP_APBX_CHn_DEBUG1_WR_FIFO_EMPTY                21
-#define BM_APBX_CHn_DEBUG1_WR_FIFO_EMPTY                0x200000
-#define BF_APBX_CHn_DEBUG1_WR_FIFO_EMPTY(v)             (((v) << 21) & 0x200000)
-#define BP_APBX_CHn_DEBUG1_WR_FIFO_FULL                 20
-#define BM_APBX_CHn_DEBUG1_WR_FIFO_FULL                 0x100000
-#define BF_APBX_CHn_DEBUG1_WR_FIFO_FULL(v)              (((v) << 20) & 0x100000)
-#define BP_APBX_CHn_DEBUG1_RSVD1                        5
-#define BM_APBX_CHn_DEBUG1_RSVD1                        0xfffe0
-#define BF_APBX_CHn_DEBUG1_RSVD1(v)                     (((v) << 5) & 0xfffe0)
-#define BP_APBX_CHn_DEBUG1_STATEMACHINE                 0
-#define BM_APBX_CHn_DEBUG1_STATEMACHINE                 0x1f
-#define BV_APBX_CHn_DEBUG1_STATEMACHINE__IDLE           0x0
-#define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD1       0x1
-#define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD3       0x2
-#define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD2       0x3
-#define BV_APBX_CHn_DEBUG1_STATEMACHINE__XFER_DECODE    0x4
-#define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_WAIT       0x5
-#define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD4       0x6
-#define BV_APBX_CHn_DEBUG1_STATEMACHINE__PIO_REQ        0x7
-#define BV_APBX_CHn_DEBUG1_STATEMACHINE__READ_FLUSH     0x8
-#define BV_APBX_CHn_DEBUG1_STATEMACHINE__READ_WAIT      0x9
-#define BV_APBX_CHn_DEBUG1_STATEMACHINE__WRITE          0xc
-#define BV_APBX_CHn_DEBUG1_STATEMACHINE__READ_REQ       0xd
-#define BV_APBX_CHn_DEBUG1_STATEMACHINE__CHECK_CHAIN    0xe
-#define BV_APBX_CHn_DEBUG1_STATEMACHINE__XFER_COMPLETE  0xf
-#define BV_APBX_CHn_DEBUG1_STATEMACHINE__WAIT_END       0x15
-#define BV_APBX_CHn_DEBUG1_STATEMACHINE__WRITE_WAIT     0x1c
-#define BV_APBX_CHn_DEBUG1_STATEMACHINE__CHECK_WAIT     0x1e
-#define BF_APBX_CHn_DEBUG1_STATEMACHINE(v)              (((v) << 0) & 0x1f)
-#define BF_APBX_CHn_DEBUG1_STATEMACHINE_V(v)            ((BV_APBX_CHn_DEBUG1_STATEMACHINE__##v << 0) & 0x1f)
-
-/**
- * Register: HW_APBX_CHn_DEBUG2
- * Address: 0x160+n*0x70
- * SCT: no
-*/
-#define HW_APBX_CHn_DEBUG2(n)           (*(volatile unsigned long *)(REGS_APBX_BASE + 0x160+(n)*0x70))
-#define BP_APBX_CHn_DEBUG2_APB_BYTES    16
-#define BM_APBX_CHn_DEBUG2_APB_BYTES    0xffff0000
-#define BF_APBX_CHn_DEBUG2_APB_BYTES(v) (((v) << 16) & 0xffff0000)
-#define BP_APBX_CHn_DEBUG2_AHB_BYTES    0
-#define BM_APBX_CHn_DEBUG2_AHB_BYTES    0xffff
-#define BF_APBX_CHn_DEBUG2_AHB_BYTES(v) (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_APBX_VERSION
- * Address: 0x800
- * SCT: no
-*/
-#define HW_APBX_VERSION             (*(volatile unsigned long *)(REGS_APBX_BASE + 0x800))
-#define BP_APBX_VERSION_MAJOR       24
-#define BM_APBX_VERSION_MAJOR       0xff000000
-#define BF_APBX_VERSION_MAJOR(v)    (((v) << 24) & 0xff000000)
-#define BP_APBX_VERSION_MINOR       16
-#define BM_APBX_VERSION_MINOR       0xff0000
-#define BF_APBX_VERSION_MINOR(v)    (((v) << 16) & 0xff0000)
-#define BP_APBX_VERSION_STEP        0
-#define BM_APBX_VERSION_STEP        0xffff
-#define BF_APBX_VERSION_STEP(v)     (((v) << 0) & 0xffff)
-
-#endif /* __HEADERGEN__IMX233__APBX__H__ */
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-audioin.h b/firmware/target/arm/imx233/regs/imx233/regs-audioin.h
deleted file mode 100644
index 4e2e46a612..0000000000
--- a/firmware/target/arm/imx233/regs/imx233/regs-audioin.h
+++ /dev/null
@@ -1,368 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: imx233:3.4.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__IMX233__AUDIOIN__H__
-#define __HEADERGEN__IMX233__AUDIOIN__H__
-
-#define REGS_AUDIOIN_BASE (0x8004c000)
-
-#define REGS_AUDIOIN_VERSION "3.4.0"
-
-/**
- * Register: HW_AUDIOIN_CTRL
- * Address: 0
- * SCT: yes
-*/
-#define HW_AUDIOIN_CTRL                         (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x0 + 0x0))
-#define HW_AUDIOIN_CTRL_SET                     (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x0 + 0x4))
-#define HW_AUDIOIN_CTRL_CLR                     (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x0 + 0x8))
-#define HW_AUDIOIN_CTRL_TOG                     (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x0 + 0xc))
-#define BP_AUDIOIN_CTRL_SFTRST                  31
-#define BM_AUDIOIN_CTRL_SFTRST                  0x80000000
-#define BF_AUDIOIN_CTRL_SFTRST(v)               (((v) << 31) & 0x80000000)
-#define BP_AUDIOIN_CTRL_CLKGATE                 30
-#define BM_AUDIOIN_CTRL_CLKGATE                 0x40000000
-#define BF_AUDIOIN_CTRL_CLKGATE(v)              (((v) << 30) & 0x40000000)
-#define BP_AUDIOIN_CTRL_RSRVD3                  21
-#define BM_AUDIOIN_CTRL_RSRVD3                  0x3fe00000
-#define BF_AUDIOIN_CTRL_RSRVD3(v)               (((v) << 21) & 0x3fe00000)
-#define BP_AUDIOIN_CTRL_DMAWAIT_COUNT           16
-#define BM_AUDIOIN_CTRL_DMAWAIT_COUNT           0x1f0000
-#define BF_AUDIOIN_CTRL_DMAWAIT_COUNT(v)        (((v) << 16) & 0x1f0000)
-#define BP_AUDIOIN_CTRL_RSRVD1                  11
-#define BM_AUDIOIN_CTRL_RSRVD1                  0xf800
-#define BF_AUDIOIN_CTRL_RSRVD1(v)               (((v) << 11) & 0xf800)
-#define BP_AUDIOIN_CTRL_LR_SWAP                 10
-#define BM_AUDIOIN_CTRL_LR_SWAP                 0x400
-#define BF_AUDIOIN_CTRL_LR_SWAP(v)              (((v) << 10) & 0x400)
-#define BP_AUDIOIN_CTRL_EDGE_SYNC               9
-#define BM_AUDIOIN_CTRL_EDGE_SYNC               0x200
-#define BF_AUDIOIN_CTRL_EDGE_SYNC(v)            (((v) << 9) & 0x200)
-#define BP_AUDIOIN_CTRL_INVERT_1BIT             8
-#define BM_AUDIOIN_CTRL_INVERT_1BIT             0x100
-#define BF_AUDIOIN_CTRL_INVERT_1BIT(v)          (((v) << 8) & 0x100)
-#define BP_AUDIOIN_CTRL_OFFSET_ENABLE           7
-#define BM_AUDIOIN_CTRL_OFFSET_ENABLE           0x80
-#define BF_AUDIOIN_CTRL_OFFSET_ENABLE(v)        (((v) << 7) & 0x80)
-#define BP_AUDIOIN_CTRL_HPF_ENABLE              6
-#define BM_AUDIOIN_CTRL_HPF_ENABLE              0x40
-#define BF_AUDIOIN_CTRL_HPF_ENABLE(v)           (((v) << 6) & 0x40)
-#define BP_AUDIOIN_CTRL_WORD_LENGTH             5
-#define BM_AUDIOIN_CTRL_WORD_LENGTH             0x20
-#define BF_AUDIOIN_CTRL_WORD_LENGTH(v)          (((v) << 5) & 0x20)
-#define BP_AUDIOIN_CTRL_LOOPBACK                4
-#define BM_AUDIOIN_CTRL_LOOPBACK                0x10
-#define BF_AUDIOIN_CTRL_LOOPBACK(v)             (((v) << 4) & 0x10)
-#define BP_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ      3
-#define BM_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ      0x8
-#define BF_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ(v)   (((v) << 3) & 0x8)
-#define BP_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ       2
-#define BM_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ       0x4
-#define BF_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ(v)    (((v) << 2) & 0x4)
-#define BP_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN       1
-#define BM_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN       0x2
-#define BF_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN(v)    (((v) << 1) & 0x2)
-#define BP_AUDIOIN_CTRL_RUN                     0
-#define BM_AUDIOIN_CTRL_RUN                     0x1
-#define BF_AUDIOIN_CTRL_RUN(v)                  (((v) << 0) & 0x1)
-
-/**
- * Register: HW_AUDIOIN_STAT
- * Address: 0x10
- * SCT: yes
-*/
-#define HW_AUDIOIN_STAT                 (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x10 + 0x0))
-#define HW_AUDIOIN_STAT_SET             (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x10 + 0x4))
-#define HW_AUDIOIN_STAT_CLR             (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x10 + 0x8))
-#define HW_AUDIOIN_STAT_TOG             (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x10 + 0xc))
-#define BP_AUDIOIN_STAT_ADC_PRESENT     31
-#define BM_AUDIOIN_STAT_ADC_PRESENT     0x80000000
-#define BF_AUDIOIN_STAT_ADC_PRESENT(v)  (((v) << 31) & 0x80000000)
-#define BP_AUDIOIN_STAT_RSRVD3          0
-#define BM_AUDIOIN_STAT_RSRVD3          0x7fffffff
-#define BF_AUDIOIN_STAT_RSRVD3(v)       (((v) << 0) & 0x7fffffff)
-
-/**
- * Register: HW_AUDIOIN_ADCSRR
- * Address: 0x20
- * SCT: yes
-*/
-#define HW_AUDIOIN_ADCSRR                       (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x20 + 0x0))
-#define HW_AUDIOIN_ADCSRR_SET                   (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x20 + 0x4))
-#define HW_AUDIOIN_ADCSRR_CLR                   (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x20 + 0x8))
-#define HW_AUDIOIN_ADCSRR_TOG                   (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x20 + 0xc))
-#define BP_AUDIOIN_ADCSRR_OSR                   31
-#define BM_AUDIOIN_ADCSRR_OSR                   0x80000000
-#define BV_AUDIOIN_ADCSRR_OSR__OSR6             0x0
-#define BV_AUDIOIN_ADCSRR_OSR__OSR12            0x1
-#define BF_AUDIOIN_ADCSRR_OSR(v)                (((v) << 31) & 0x80000000)
-#define BF_AUDIOIN_ADCSRR_OSR_V(v)              ((BV_AUDIOIN_ADCSRR_OSR__##v << 31) & 0x80000000)
-#define BP_AUDIOIN_ADCSRR_BASEMULT              28
-#define BM_AUDIOIN_ADCSRR_BASEMULT              0x70000000
-#define BV_AUDIOIN_ADCSRR_BASEMULT__SINGLE_RATE 0x1
-#define BV_AUDIOIN_ADCSRR_BASEMULT__DOUBLE_RATE 0x2
-#define BV_AUDIOIN_ADCSRR_BASEMULT__QUAD_RATE   0x4
-#define BF_AUDIOIN_ADCSRR_BASEMULT(v)           (((v) << 28) & 0x70000000)
-#define BF_AUDIOIN_ADCSRR_BASEMULT_V(v)         ((BV_AUDIOIN_ADCSRR_BASEMULT__##v << 28) & 0x70000000)
-#define BP_AUDIOIN_ADCSRR_RSRVD2                27
-#define BM_AUDIOIN_ADCSRR_RSRVD2                0x8000000
-#define BF_AUDIOIN_ADCSRR_RSRVD2(v)             (((v) << 27) & 0x8000000)
-#define BP_AUDIOIN_ADCSRR_SRC_HOLD              24
-#define BM_AUDIOIN_ADCSRR_SRC_HOLD              0x7000000
-#define BF_AUDIOIN_ADCSRR_SRC_HOLD(v)           (((v) << 24) & 0x7000000)
-#define BP_AUDIOIN_ADCSRR_RSRVD1                21
-#define BM_AUDIOIN_ADCSRR_RSRVD1                0xe00000
-#define BF_AUDIOIN_ADCSRR_RSRVD1(v)             (((v) << 21) & 0xe00000)
-#define BP_AUDIOIN_ADCSRR_SRC_INT               16
-#define BM_AUDIOIN_ADCSRR_SRC_INT               0x1f0000
-#define BF_AUDIOIN_ADCSRR_SRC_INT(v)            (((v) << 16) & 0x1f0000)
-#define BP_AUDIOIN_ADCSRR_RSRVD0                13
-#define BM_AUDIOIN_ADCSRR_RSRVD0                0xe000
-#define BF_AUDIOIN_ADCSRR_RSRVD0(v)             (((v) << 13) & 0xe000)
-#define BP_AUDIOIN_ADCSRR_SRC_FRAC              0
-#define BM_AUDIOIN_ADCSRR_SRC_FRAC              0x1fff
-#define BF_AUDIOIN_ADCSRR_SRC_FRAC(v)           (((v) << 0) & 0x1fff)
-
-/**
- * Register: HW_AUDIOIN_ADCVOLUME
- * Address: 0x30
- * SCT: yes
-*/
-#define HW_AUDIOIN_ADCVOLUME                        (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x30 + 0x0))
-#define HW_AUDIOIN_ADCVOLUME_SET                    (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x30 + 0x4))
-#define HW_AUDIOIN_ADCVOLUME_CLR                    (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x30 + 0x8))
-#define HW_AUDIOIN_ADCVOLUME_TOG                    (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x30 + 0xc))
-#define BP_AUDIOIN_ADCVOLUME_RSRVD5                 29
-#define BM_AUDIOIN_ADCVOLUME_RSRVD5                 0xe0000000
-#define BF_AUDIOIN_ADCVOLUME_RSRVD5(v)              (((v) << 29) & 0xe0000000)
-#define BP_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_LEFT     28
-#define BM_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_LEFT     0x10000000
-#define BF_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_LEFT(v)  (((v) << 28) & 0x10000000)
-#define BP_AUDIOIN_ADCVOLUME_RSRVD4                 26
-#define BM_AUDIOIN_ADCVOLUME_RSRVD4                 0xc000000
-#define BF_AUDIOIN_ADCVOLUME_RSRVD4(v)              (((v) << 26) & 0xc000000)
-#define BP_AUDIOIN_ADCVOLUME_EN_ZCD                 25
-#define BM_AUDIOIN_ADCVOLUME_EN_ZCD                 0x2000000
-#define BF_AUDIOIN_ADCVOLUME_EN_ZCD(v)              (((v) << 25) & 0x2000000)
-#define BP_AUDIOIN_ADCVOLUME_RSRVD3                 24
-#define BM_AUDIOIN_ADCVOLUME_RSRVD3                 0x1000000
-#define BF_AUDIOIN_ADCVOLUME_RSRVD3(v)              (((v) << 24) & 0x1000000)
-#define BP_AUDIOIN_ADCVOLUME_VOLUME_LEFT            16
-#define BM_AUDIOIN_ADCVOLUME_VOLUME_LEFT            0xff0000
-#define BF_AUDIOIN_ADCVOLUME_VOLUME_LEFT(v)         (((v) << 16) & 0xff0000)
-#define BP_AUDIOIN_ADCVOLUME_RSRVD2                 13
-#define BM_AUDIOIN_ADCVOLUME_RSRVD2                 0xe000
-#define BF_AUDIOIN_ADCVOLUME_RSRVD2(v)              (((v) << 13) & 0xe000)
-#define BP_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_RIGHT    12
-#define BM_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_RIGHT    0x1000
-#define BF_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_RIGHT(v) (((v) << 12) & 0x1000)
-#define BP_AUDIOIN_ADCVOLUME_RSRVD1                 8
-#define BM_AUDIOIN_ADCVOLUME_RSRVD1                 0xf00
-#define BF_AUDIOIN_ADCVOLUME_RSRVD1(v)              (((v) << 8) & 0xf00)
-#define BP_AUDIOIN_ADCVOLUME_VOLUME_RIGHT           0
-#define BM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT           0xff
-#define BF_AUDIOIN_ADCVOLUME_VOLUME_RIGHT(v)        (((v) << 0) & 0xff)
-
-/**
- * Register: HW_AUDIOIN_ADCDEBUG
- * Address: 0x40
- * SCT: yes
-*/
-#define HW_AUDIOIN_ADCDEBUG                                     (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x40 + 0x0))
-#define HW_AUDIOIN_ADCDEBUG_SET                                 (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x40 + 0x4))
-#define HW_AUDIOIN_ADCDEBUG_CLR                                 (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x40 + 0x8))
-#define HW_AUDIOIN_ADCDEBUG_TOG                                 (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x40 + 0xc))
-#define BP_AUDIOIN_ADCDEBUG_ENABLE_ADCDMA                       31
-#define BM_AUDIOIN_ADCDEBUG_ENABLE_ADCDMA                       0x80000000
-#define BF_AUDIOIN_ADCDEBUG_ENABLE_ADCDMA(v)                    (((v) << 31) & 0x80000000)
-#define BP_AUDIOIN_ADCDEBUG_RSRVD1                              4
-#define BM_AUDIOIN_ADCDEBUG_RSRVD1                              0x7ffffff0
-#define BF_AUDIOIN_ADCDEBUG_RSRVD1(v)                           (((v) << 4) & 0x7ffffff0)
-#define BP_AUDIOIN_ADCDEBUG_ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS    3
-#define BM_AUDIOIN_ADCDEBUG_ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS    0x8
-#define BF_AUDIOIN_ADCDEBUG_ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS(v) (((v) << 3) & 0x8)
-#define BP_AUDIOIN_ADCDEBUG_SET_INTERRUPT3_HAND_SHAKE           2
-#define BM_AUDIOIN_ADCDEBUG_SET_INTERRUPT3_HAND_SHAKE           0x4
-#define BF_AUDIOIN_ADCDEBUG_SET_INTERRUPT3_HAND_SHAKE(v)        (((v) << 2) & 0x4)
-#define BP_AUDIOIN_ADCDEBUG_DMA_PREQ                            1
-#define BM_AUDIOIN_ADCDEBUG_DMA_PREQ                            0x2
-#define BF_AUDIOIN_ADCDEBUG_DMA_PREQ(v)                         (((v) << 1) & 0x2)
-#define BP_AUDIOIN_ADCDEBUG_FIFO_STATUS                         0
-#define BM_AUDIOIN_ADCDEBUG_FIFO_STATUS                         0x1
-#define BF_AUDIOIN_ADCDEBUG_FIFO_STATUS(v)                      (((v) << 0) & 0x1)
-
-/**
- * Register: HW_AUDIOIN_ADCVOL
- * Address: 0x50
- * SCT: yes
-*/
-#define HW_AUDIOIN_ADCVOL                           (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x50 + 0x0))
-#define HW_AUDIOIN_ADCVOL_SET                       (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x50 + 0x4))
-#define HW_AUDIOIN_ADCVOL_CLR                       (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x50 + 0x8))
-#define HW_AUDIOIN_ADCVOL_TOG                       (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x50 + 0xc))
-#define BP_AUDIOIN_ADCVOL_RSRVD4                    29
-#define BM_AUDIOIN_ADCVOL_RSRVD4                    0xe0000000
-#define BF_AUDIOIN_ADCVOL_RSRVD4(v)                 (((v) << 29) & 0xe0000000)
-#define BP_AUDIOIN_ADCVOL_VOLUME_UPDATE_PENDING     28
-#define BM_AUDIOIN_ADCVOL_VOLUME_UPDATE_PENDING     0x10000000
-#define BF_AUDIOIN_ADCVOL_VOLUME_UPDATE_PENDING(v)  (((v) << 28) & 0x10000000)
-#define BP_AUDIOIN_ADCVOL_RSRVD3                    26
-#define BM_AUDIOIN_ADCVOL_RSRVD3                    0xc000000
-#define BF_AUDIOIN_ADCVOL_RSRVD3(v)                 (((v) << 26) & 0xc000000)
-#define BP_AUDIOIN_ADCVOL_EN_ADC_ZCD                25
-#define BM_AUDIOIN_ADCVOL_EN_ADC_ZCD                0x2000000
-#define BF_AUDIOIN_ADCVOL_EN_ADC_ZCD(v)             (((v) << 25) & 0x2000000)
-#define BP_AUDIOIN_ADCVOL_MUTE                      24
-#define BM_AUDIOIN_ADCVOL_MUTE                      0x1000000
-#define BF_AUDIOIN_ADCVOL_MUTE(v)                   (((v) << 24) & 0x1000000)
-#define BP_AUDIOIN_ADCVOL_RSRVD2                    14
-#define BM_AUDIOIN_ADCVOL_RSRVD2                    0xffc000
-#define BF_AUDIOIN_ADCVOL_RSRVD2(v)                 (((v) << 14) & 0xffc000)
-#define BP_AUDIOIN_ADCVOL_SELECT_LEFT               12
-#define BM_AUDIOIN_ADCVOL_SELECT_LEFT               0x3000
-#define BF_AUDIOIN_ADCVOL_SELECT_LEFT(v)            (((v) << 12) & 0x3000)
-#define BP_AUDIOIN_ADCVOL_GAIN_LEFT                 8
-#define BM_AUDIOIN_ADCVOL_GAIN_LEFT                 0xf00
-#define BF_AUDIOIN_ADCVOL_GAIN_LEFT(v)              (((v) << 8) & 0xf00)
-#define BP_AUDIOIN_ADCVOL_RSRVD1                    6
-#define BM_AUDIOIN_ADCVOL_RSRVD1                    0xc0
-#define BF_AUDIOIN_ADCVOL_RSRVD1(v)                 (((v) << 6) & 0xc0)
-#define BP_AUDIOIN_ADCVOL_SELECT_RIGHT              4
-#define BM_AUDIOIN_ADCVOL_SELECT_RIGHT              0x30
-#define BF_AUDIOIN_ADCVOL_SELECT_RIGHT(v)           (((v) << 4) & 0x30)
-#define BP_AUDIOIN_ADCVOL_GAIN_RIGHT                0
-#define BM_AUDIOIN_ADCVOL_GAIN_RIGHT                0xf
-#define BF_AUDIOIN_ADCVOL_GAIN_RIGHT(v)             (((v) << 0) & 0xf)
-
-/**
- * Register: HW_AUDIOIN_MICLINE
- * Address: 0x60
- * SCT: yes
-*/
-#define HW_AUDIOIN_MICLINE                      (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x60 + 0x0))
-#define HW_AUDIOIN_MICLINE_SET                  (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x60 + 0x4))
-#define HW_AUDIOIN_MICLINE_CLR                  (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x60 + 0x8))
-#define HW_AUDIOIN_MICLINE_TOG                  (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x60 + 0xc))
-#define BP_AUDIOIN_MICLINE_RSRVD6               30
-#define BM_AUDIOIN_MICLINE_RSRVD6               0xc0000000
-#define BF_AUDIOIN_MICLINE_RSRVD6(v)            (((v) << 30) & 0xc0000000)
-#define BP_AUDIOIN_MICLINE_DIVIDE_LINE1         29
-#define BM_AUDIOIN_MICLINE_DIVIDE_LINE1         0x20000000
-#define BF_AUDIOIN_MICLINE_DIVIDE_LINE1(v)      (((v) << 29) & 0x20000000)
-#define BP_AUDIOIN_MICLINE_DIVIDE_LINE2         28
-#define BM_AUDIOIN_MICLINE_DIVIDE_LINE2         0x10000000
-#define BF_AUDIOIN_MICLINE_DIVIDE_LINE2(v)      (((v) << 28) & 0x10000000)
-#define BP_AUDIOIN_MICLINE_RSRVD5               25
-#define BM_AUDIOIN_MICLINE_RSRVD5               0xe000000
-#define BF_AUDIOIN_MICLINE_RSRVD5(v)            (((v) << 25) & 0xe000000)
-#define BP_AUDIOIN_MICLINE_MIC_SELECT           24
-#define BM_AUDIOIN_MICLINE_MIC_SELECT           0x1000000
-#define BF_AUDIOIN_MICLINE_MIC_SELECT(v)        (((v) << 24) & 0x1000000)
-#define BP_AUDIOIN_MICLINE_RSRVD4               22
-#define BM_AUDIOIN_MICLINE_RSRVD4               0xc00000
-#define BF_AUDIOIN_MICLINE_RSRVD4(v)            (((v) << 22) & 0xc00000)
-#define BP_AUDIOIN_MICLINE_MIC_RESISTOR         20
-#define BM_AUDIOIN_MICLINE_MIC_RESISTOR         0x300000
-#define BV_AUDIOIN_MICLINE_MIC_RESISTOR__Off    0x0
-#define BV_AUDIOIN_MICLINE_MIC_RESISTOR__2KOhm  0x1
-#define BV_AUDIOIN_MICLINE_MIC_RESISTOR__4KOhm  0x2
-#define BV_AUDIOIN_MICLINE_MIC_RESISTOR__8KOhm  0x3
-#define BF_AUDIOIN_MICLINE_MIC_RESISTOR(v)      (((v) << 20) & 0x300000)
-#define BF_AUDIOIN_MICLINE_MIC_RESISTOR_V(v)    ((BV_AUDIOIN_MICLINE_MIC_RESISTOR__##v << 20) & 0x300000)
-#define BP_AUDIOIN_MICLINE_RSRVD3               19
-#define BM_AUDIOIN_MICLINE_RSRVD3               0x80000
-#define BF_AUDIOIN_MICLINE_RSRVD3(v)            (((v) << 19) & 0x80000)
-#define BP_AUDIOIN_MICLINE_MIC_BIAS             16
-#define BM_AUDIOIN_MICLINE_MIC_BIAS             0x70000
-#define BF_AUDIOIN_MICLINE_MIC_BIAS(v)          (((v) << 16) & 0x70000)
-#define BP_AUDIOIN_MICLINE_RSRVD2               6
-#define BM_AUDIOIN_MICLINE_RSRVD2               0xffc0
-#define BF_AUDIOIN_MICLINE_RSRVD2(v)            (((v) << 6) & 0xffc0)
-#define BP_AUDIOIN_MICLINE_MIC_CHOPCLK          4
-#define BM_AUDIOIN_MICLINE_MIC_CHOPCLK          0x30
-#define BF_AUDIOIN_MICLINE_MIC_CHOPCLK(v)       (((v) << 4) & 0x30)
-#define BP_AUDIOIN_MICLINE_RSRVD1               2
-#define BM_AUDIOIN_MICLINE_RSRVD1               0xc
-#define BF_AUDIOIN_MICLINE_RSRVD1(v)            (((v) << 2) & 0xc)
-#define BP_AUDIOIN_MICLINE_MIC_GAIN             0
-#define BM_AUDIOIN_MICLINE_MIC_GAIN             0x3
-#define BV_AUDIOIN_MICLINE_MIC_GAIN__0dB        0x0
-#define BV_AUDIOIN_MICLINE_MIC_GAIN__20dB       0x1
-#define BV_AUDIOIN_MICLINE_MIC_GAIN__30dB       0x2
-#define BV_AUDIOIN_MICLINE_MIC_GAIN__40dB       0x3
-#define BF_AUDIOIN_MICLINE_MIC_GAIN(v)          (((v) << 0) & 0x3)
-#define BF_AUDIOIN_MICLINE_MIC_GAIN_V(v)        ((BV_AUDIOIN_MICLINE_MIC_GAIN__##v << 0) & 0x3)
-
-/**
- * Register: HW_AUDIOIN_ANACLKCTRL
- * Address: 0x70
- * SCT: yes
-*/
-#define HW_AUDIOIN_ANACLKCTRL                   (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x70 + 0x0))
-#define HW_AUDIOIN_ANACLKCTRL_SET               (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x70 + 0x4))
-#define HW_AUDIOIN_ANACLKCTRL_CLR               (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x70 + 0x8))
-#define HW_AUDIOIN_ANACLKCTRL_TOG               (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x70 + 0xc))
-#define BP_AUDIOIN_ANACLKCTRL_CLKGATE           31
-#define BM_AUDIOIN_ANACLKCTRL_CLKGATE           0x80000000
-#define BF_AUDIOIN_ANACLKCTRL_CLKGATE(v)        (((v) << 31) & 0x80000000)
-#define BP_AUDIOIN_ANACLKCTRL_RSRVD4            11
-#define BM_AUDIOIN_ANACLKCTRL_RSRVD4            0x7ffff800
-#define BF_AUDIOIN_ANACLKCTRL_RSRVD4(v)         (((v) << 11) & 0x7ffff800)
-#define BP_AUDIOIN_ANACLKCTRL_DITHER_OFF        10
-#define BM_AUDIOIN_ANACLKCTRL_DITHER_OFF        0x400
-#define BF_AUDIOIN_ANACLKCTRL_DITHER_OFF(v)     (((v) << 10) & 0x400)
-#define BP_AUDIOIN_ANACLKCTRL_SLOW_DITHER       9
-#define BM_AUDIOIN_ANACLKCTRL_SLOW_DITHER       0x200
-#define BF_AUDIOIN_ANACLKCTRL_SLOW_DITHER(v)    (((v) << 9) & 0x200)
-#define BP_AUDIOIN_ANACLKCTRL_INVERT_ADCCLK     8
-#define BM_AUDIOIN_ANACLKCTRL_INVERT_ADCCLK     0x100
-#define BF_AUDIOIN_ANACLKCTRL_INVERT_ADCCLK(v)  (((v) << 8) & 0x100)
-#define BP_AUDIOIN_ANACLKCTRL_RSRVD3            6
-#define BM_AUDIOIN_ANACLKCTRL_RSRVD3            0xc0
-#define BF_AUDIOIN_ANACLKCTRL_RSRVD3(v)         (((v) << 6) & 0xc0)
-#define BP_AUDIOIN_ANACLKCTRL_ADCCLK_SHIFT      4
-#define BM_AUDIOIN_ANACLKCTRL_ADCCLK_SHIFT      0x30
-#define BF_AUDIOIN_ANACLKCTRL_ADCCLK_SHIFT(v)   (((v) << 4) & 0x30)
-#define BP_AUDIOIN_ANACLKCTRL_RSRVD2            3
-#define BM_AUDIOIN_ANACLKCTRL_RSRVD2            0x8
-#define BF_AUDIOIN_ANACLKCTRL_RSRVD2(v)         (((v) << 3) & 0x8)
-#define BP_AUDIOIN_ANACLKCTRL_ADCDIV            0
-#define BM_AUDIOIN_ANACLKCTRL_ADCDIV            0x7
-#define BF_AUDIOIN_ANACLKCTRL_ADCDIV(v)         (((v) << 0) & 0x7)
-
-/**
- * Register: HW_AUDIOIN_DATA
- * Address: 0x80
- * SCT: yes
-*/
-#define HW_AUDIOIN_DATA         (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x80 + 0x0))
-#define HW_AUDIOIN_DATA_SET     (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x80 + 0x4))
-#define HW_AUDIOIN_DATA_CLR     (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x80 + 0x8))
-#define HW_AUDIOIN_DATA_TOG     (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x80 + 0xc))
-#define BP_AUDIOIN_DATA_HIGH    16
-#define BM_AUDIOIN_DATA_HIGH    0xffff0000
-#define BF_AUDIOIN_DATA_HIGH(v) (((v) << 16) & 0xffff0000)
-#define BP_AUDIOIN_DATA_LOW     0
-#define BM_AUDIOIN_DATA_LOW     0xffff
-#define BF_AUDIOIN_DATA_LOW(v)  (((v) << 0) & 0xffff)
-
-#endif /* __HEADERGEN__IMX233__AUDIOIN__H__ */
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-audioout.h b/firmware/target/arm/imx233/regs/imx233/regs-audioout.h
deleted file mode 100644
index fdf48c4a8b..0000000000
--- a/firmware/target/arm/imx233/regs/imx233/regs-audioout.h
+++ /dev/null
@@ -1,673 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: imx233:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__IMX233__AUDIOOUT__H__
-#define __HEADERGEN__IMX233__AUDIOOUT__H__
-
-#define REGS_AUDIOOUT_BASE (0x80048000)
-
-#define REGS_AUDIOOUT_VERSION "3.2.0"
-
-/**
- * Register: HW_AUDIOOUT_CTRL
- * Address: 0
- * SCT: yes
-*/
-#define HW_AUDIOOUT_CTRL                        (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x0 + 0x0))
-#define HW_AUDIOOUT_CTRL_SET                    (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x0 + 0x4))
-#define HW_AUDIOOUT_CTRL_CLR                    (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x0 + 0x8))
-#define HW_AUDIOOUT_CTRL_TOG                    (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x0 + 0xc))
-#define BP_AUDIOOUT_CTRL_SFTRST                 31
-#define BM_AUDIOOUT_CTRL_SFTRST                 0x80000000
-#define BF_AUDIOOUT_CTRL_SFTRST(v)              (((v) << 31) & 0x80000000)
-#define BP_AUDIOOUT_CTRL_CLKGATE                30
-#define BM_AUDIOOUT_CTRL_CLKGATE                0x40000000
-#define BF_AUDIOOUT_CTRL_CLKGATE(v)             (((v) << 30) & 0x40000000)
-#define BP_AUDIOOUT_CTRL_RSRVD4                 21
-#define BM_AUDIOOUT_CTRL_RSRVD4                 0x3fe00000
-#define BF_AUDIOOUT_CTRL_RSRVD4(v)              (((v) << 21) & 0x3fe00000)
-#define BP_AUDIOOUT_CTRL_DMAWAIT_COUNT          16
-#define BM_AUDIOOUT_CTRL_DMAWAIT_COUNT          0x1f0000
-#define BF_AUDIOOUT_CTRL_DMAWAIT_COUNT(v)       (((v) << 16) & 0x1f0000)
-#define BP_AUDIOOUT_CTRL_RSRVD3                 15
-#define BM_AUDIOOUT_CTRL_RSRVD3                 0x8000
-#define BF_AUDIOOUT_CTRL_RSRVD3(v)              (((v) << 15) & 0x8000)
-#define BP_AUDIOOUT_CTRL_LR_SWAP                14
-#define BM_AUDIOOUT_CTRL_LR_SWAP                0x4000
-#define BF_AUDIOOUT_CTRL_LR_SWAP(v)             (((v) << 14) & 0x4000)
-#define BP_AUDIOOUT_CTRL_EDGE_SYNC              13
-#define BM_AUDIOOUT_CTRL_EDGE_SYNC              0x2000
-#define BF_AUDIOOUT_CTRL_EDGE_SYNC(v)           (((v) << 13) & 0x2000)
-#define BP_AUDIOOUT_CTRL_INVERT_1BIT            12
-#define BM_AUDIOOUT_CTRL_INVERT_1BIT            0x1000
-#define BF_AUDIOOUT_CTRL_INVERT_1BIT(v)         (((v) << 12) & 0x1000)
-#define BP_AUDIOOUT_CTRL_RSRVD2                 10
-#define BM_AUDIOOUT_CTRL_RSRVD2                 0xc00
-#define BF_AUDIOOUT_CTRL_RSRVD2(v)              (((v) << 10) & 0xc00)
-#define BP_AUDIOOUT_CTRL_SS3D_EFFECT            8
-#define BM_AUDIOOUT_CTRL_SS3D_EFFECT            0x300
-#define BF_AUDIOOUT_CTRL_SS3D_EFFECT(v)         (((v) << 8) & 0x300)
-#define BP_AUDIOOUT_CTRL_RSRVD1                 7
-#define BM_AUDIOOUT_CTRL_RSRVD1                 0x80
-#define BF_AUDIOOUT_CTRL_RSRVD1(v)              (((v) << 7) & 0x80)
-#define BP_AUDIOOUT_CTRL_WORD_LENGTH            6
-#define BM_AUDIOOUT_CTRL_WORD_LENGTH            0x40
-#define BF_AUDIOOUT_CTRL_WORD_LENGTH(v)         (((v) << 6) & 0x40)
-#define BP_AUDIOOUT_CTRL_DAC_ZERO_ENABLE        5
-#define BM_AUDIOOUT_CTRL_DAC_ZERO_ENABLE        0x20
-#define BF_AUDIOOUT_CTRL_DAC_ZERO_ENABLE(v)     (((v) << 5) & 0x20)
-#define BP_AUDIOOUT_CTRL_LOOPBACK               4
-#define BM_AUDIOOUT_CTRL_LOOPBACK               0x10
-#define BF_AUDIOOUT_CTRL_LOOPBACK(v)            (((v) << 4) & 0x10)
-#define BP_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ     3
-#define BM_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ     0x8
-#define BF_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ(v)  (((v) << 3) & 0x8)
-#define BP_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ      2
-#define BM_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ      0x4
-#define BF_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ(v)   (((v) << 2) & 0x4)
-#define BP_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN      1
-#define BM_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN      0x2
-#define BF_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN(v)   (((v) << 1) & 0x2)
-#define BP_AUDIOOUT_CTRL_RUN                    0
-#define BM_AUDIOOUT_CTRL_RUN                    0x1
-#define BF_AUDIOOUT_CTRL_RUN(v)                 (((v) << 0) & 0x1)
-
-/**
- * Register: HW_AUDIOOUT_STAT
- * Address: 0x10
- * SCT: yes
-*/
-#define HW_AUDIOOUT_STAT                (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x10 + 0x0))
-#define HW_AUDIOOUT_STAT_SET            (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x10 + 0x4))
-#define HW_AUDIOOUT_STAT_CLR            (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x10 + 0x8))
-#define HW_AUDIOOUT_STAT_TOG            (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x10 + 0xc))
-#define BP_AUDIOOUT_STAT_DAC_PRESENT    31
-#define BM_AUDIOOUT_STAT_DAC_PRESENT    0x80000000
-#define BF_AUDIOOUT_STAT_DAC_PRESENT(v) (((v) << 31) & 0x80000000)
-#define BP_AUDIOOUT_STAT_RSRVD1         0
-#define BM_AUDIOOUT_STAT_RSRVD1         0x7fffffff
-#define BF_AUDIOOUT_STAT_RSRVD1(v)      (((v) << 0) & 0x7fffffff)
-
-/**
- * Register: HW_AUDIOOUT_DACSRR
- * Address: 0x20
- * SCT: yes
-*/
-#define HW_AUDIOOUT_DACSRR                          (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x20 + 0x0))
-#define HW_AUDIOOUT_DACSRR_SET                      (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x20 + 0x4))
-#define HW_AUDIOOUT_DACSRR_CLR                      (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x20 + 0x8))
-#define HW_AUDIOOUT_DACSRR_TOG                      (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x20 + 0xc))
-#define BP_AUDIOOUT_DACSRR_OSR                      31
-#define BM_AUDIOOUT_DACSRR_OSR                      0x80000000
-#define BV_AUDIOOUT_DACSRR_OSR__OSR6                0x0
-#define BV_AUDIOOUT_DACSRR_OSR__OSR12               0x1
-#define BF_AUDIOOUT_DACSRR_OSR(v)                   (((v) << 31) & 0x80000000)
-#define BF_AUDIOOUT_DACSRR_OSR_V(v)                 ((BV_AUDIOOUT_DACSRR_OSR__##v << 31) & 0x80000000)
-#define BP_AUDIOOUT_DACSRR_BASEMULT                 28
-#define BM_AUDIOOUT_DACSRR_BASEMULT                 0x70000000
-#define BV_AUDIOOUT_DACSRR_BASEMULT__SINGLE_RATE    0x1
-#define BV_AUDIOOUT_DACSRR_BASEMULT__DOUBLE_RATE    0x2
-#define BV_AUDIOOUT_DACSRR_BASEMULT__QUAD_RATE      0x4
-#define BF_AUDIOOUT_DACSRR_BASEMULT(v)              (((v) << 28) & 0x70000000)
-#define BF_AUDIOOUT_DACSRR_BASEMULT_V(v)            ((BV_AUDIOOUT_DACSRR_BASEMULT__##v << 28) & 0x70000000)
-#define BP_AUDIOOUT_DACSRR_RSRVD2                   27
-#define BM_AUDIOOUT_DACSRR_RSRVD2                   0x8000000
-#define BF_AUDIOOUT_DACSRR_RSRVD2(v)                (((v) << 27) & 0x8000000)
-#define BP_AUDIOOUT_DACSRR_SRC_HOLD                 24
-#define BM_AUDIOOUT_DACSRR_SRC_HOLD                 0x7000000
-#define BF_AUDIOOUT_DACSRR_SRC_HOLD(v)              (((v) << 24) & 0x7000000)
-#define BP_AUDIOOUT_DACSRR_RSRVD1                   21
-#define BM_AUDIOOUT_DACSRR_RSRVD1                   0xe00000
-#define BF_AUDIOOUT_DACSRR_RSRVD1(v)                (((v) << 21) & 0xe00000)
-#define BP_AUDIOOUT_DACSRR_SRC_INT                  16
-#define BM_AUDIOOUT_DACSRR_SRC_INT                  0x1f0000
-#define BF_AUDIOOUT_DACSRR_SRC_INT(v)               (((v) << 16) & 0x1f0000)
-#define BP_AUDIOOUT_DACSRR_RSRVD0                   13
-#define BM_AUDIOOUT_DACSRR_RSRVD0                   0xe000
-#define BF_AUDIOOUT_DACSRR_RSRVD0(v)                (((v) << 13) & 0xe000)
-#define BP_AUDIOOUT_DACSRR_SRC_FRAC                 0
-#define BM_AUDIOOUT_DACSRR_SRC_FRAC                 0x1fff
-#define BF_AUDIOOUT_DACSRR_SRC_FRAC(v)              (((v) << 0) & 0x1fff)
-
-/**
- * Register: HW_AUDIOOUT_DACVOLUME
- * Address: 0x30
- * SCT: yes
-*/
-#define HW_AUDIOOUT_DACVOLUME                           (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x30 + 0x0))
-#define HW_AUDIOOUT_DACVOLUME_SET                       (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x30 + 0x4))
-#define HW_AUDIOOUT_DACVOLUME_CLR                       (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x30 + 0x8))
-#define HW_AUDIOOUT_DACVOLUME_TOG                       (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x30 + 0xc))
-#define BP_AUDIOOUT_DACVOLUME_RSRVD4                    29
-#define BM_AUDIOOUT_DACVOLUME_RSRVD4                    0xe0000000
-#define BF_AUDIOOUT_DACVOLUME_RSRVD4(v)                 (((v) << 29) & 0xe0000000)
-#define BP_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT        28
-#define BM_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT        0x10000000
-#define BF_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT(v)     (((v) << 28) & 0x10000000)
-#define BP_AUDIOOUT_DACVOLUME_RSRVD3                    26
-#define BM_AUDIOOUT_DACVOLUME_RSRVD3                    0xc000000
-#define BF_AUDIOOUT_DACVOLUME_RSRVD3(v)                 (((v) << 26) & 0xc000000)
-#define BP_AUDIOOUT_DACVOLUME_EN_ZCD                    25
-#define BM_AUDIOOUT_DACVOLUME_EN_ZCD                    0x2000000
-#define BF_AUDIOOUT_DACVOLUME_EN_ZCD(v)                 (((v) << 25) & 0x2000000)
-#define BP_AUDIOOUT_DACVOLUME_MUTE_LEFT                 24
-#define BM_AUDIOOUT_DACVOLUME_MUTE_LEFT                 0x1000000
-#define BF_AUDIOOUT_DACVOLUME_MUTE_LEFT(v)              (((v) << 24) & 0x1000000)
-#define BP_AUDIOOUT_DACVOLUME_VOLUME_LEFT               16
-#define BM_AUDIOOUT_DACVOLUME_VOLUME_LEFT               0xff0000
-#define BF_AUDIOOUT_DACVOLUME_VOLUME_LEFT(v)            (((v) << 16) & 0xff0000)
-#define BP_AUDIOOUT_DACVOLUME_RSRVD2                    13
-#define BM_AUDIOOUT_DACVOLUME_RSRVD2                    0xe000
-#define BF_AUDIOOUT_DACVOLUME_RSRVD2(v)                 (((v) << 13) & 0xe000)
-#define BP_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT       12
-#define BM_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT       0x1000
-#define BF_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT(v)    (((v) << 12) & 0x1000)
-#define BP_AUDIOOUT_DACVOLUME_RSRVD1                    9
-#define BM_AUDIOOUT_DACVOLUME_RSRVD1                    0xe00
-#define BF_AUDIOOUT_DACVOLUME_RSRVD1(v)                 (((v) << 9) & 0xe00)
-#define BP_AUDIOOUT_DACVOLUME_MUTE_RIGHT                8
-#define BM_AUDIOOUT_DACVOLUME_MUTE_RIGHT                0x100
-#define BF_AUDIOOUT_DACVOLUME_MUTE_RIGHT(v)             (((v) << 8) & 0x100)
-#define BP_AUDIOOUT_DACVOLUME_VOLUME_RIGHT              0
-#define BM_AUDIOOUT_DACVOLUME_VOLUME_RIGHT              0xff
-#define BF_AUDIOOUT_DACVOLUME_VOLUME_RIGHT(v)           (((v) << 0) & 0xff)
-
-/**
- * Register: HW_AUDIOOUT_DACDEBUG
- * Address: 0x40
- * SCT: yes
-*/
-#define HW_AUDIOOUT_DACDEBUG                                (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x40 + 0x0))
-#define HW_AUDIOOUT_DACDEBUG_SET                            (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x40 + 0x4))
-#define HW_AUDIOOUT_DACDEBUG_CLR                            (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x40 + 0x8))
-#define HW_AUDIOOUT_DACDEBUG_TOG                            (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x40 + 0xc))
-#define BP_AUDIOOUT_DACDEBUG_ENABLE_DACDMA                  31
-#define BM_AUDIOOUT_DACDEBUG_ENABLE_DACDMA                  0x80000000
-#define BF_AUDIOOUT_DACDEBUG_ENABLE_DACDMA(v)               (((v) << 31) & 0x80000000)
-#define BP_AUDIOOUT_DACDEBUG_RSRVD2                         12
-#define BM_AUDIOOUT_DACDEBUG_RSRVD2                         0x7ffff000
-#define BF_AUDIOOUT_DACDEBUG_RSRVD2(v)                      (((v) << 12) & 0x7ffff000)
-#define BP_AUDIOOUT_DACDEBUG_RAM_SS                         8
-#define BM_AUDIOOUT_DACDEBUG_RAM_SS                         0xf00
-#define BF_AUDIOOUT_DACDEBUG_RAM_SS(v)                      (((v) << 8) & 0xf00)
-#define BP_AUDIOOUT_DACDEBUG_RSRVD1                         6
-#define BM_AUDIOOUT_DACDEBUG_RSRVD1                         0xc0
-#define BF_AUDIOOUT_DACDEBUG_RSRVD1(v)                      (((v) << 6) & 0xc0)
-#define BP_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS       5
-#define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS       0x20
-#define BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS(v)    (((v) << 5) & 0x20)
-#define BP_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS       4
-#define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS       0x10
-#define BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS(v)    (((v) << 4) & 0x10)
-#define BP_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE      3
-#define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE      0x8
-#define BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE(v)   (((v) << 3) & 0x8)
-#define BP_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE      2
-#define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE      0x4
-#define BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE(v)   (((v) << 2) & 0x4)
-#define BP_AUDIOOUT_DACDEBUG_DMA_PREQ                       1
-#define BM_AUDIOOUT_DACDEBUG_DMA_PREQ                       0x2
-#define BF_AUDIOOUT_DACDEBUG_DMA_PREQ(v)                    (((v) << 1) & 0x2)
-#define BP_AUDIOOUT_DACDEBUG_FIFO_STATUS                    0
-#define BM_AUDIOOUT_DACDEBUG_FIFO_STATUS                    0x1
-#define BF_AUDIOOUT_DACDEBUG_FIFO_STATUS(v)                 (((v) << 0) & 0x1)
-
-/**
- * Register: HW_AUDIOOUT_HPVOL
- * Address: 0x50
- * SCT: yes
-*/
-#define HW_AUDIOOUT_HPVOL                           (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x50 + 0x0))
-#define HW_AUDIOOUT_HPVOL_SET                       (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x50 + 0x4))
-#define HW_AUDIOOUT_HPVOL_CLR                       (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x50 + 0x8))
-#define HW_AUDIOOUT_HPVOL_TOG                       (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x50 + 0xc))
-#define BP_AUDIOOUT_HPVOL_RSRVD5                    29
-#define BM_AUDIOOUT_HPVOL_RSRVD5                    0xe0000000
-#define BF_AUDIOOUT_HPVOL_RSRVD5(v)                 (((v) << 29) & 0xe0000000)
-#define BP_AUDIOOUT_HPVOL_VOLUME_UPDATE_PENDING     28
-#define BM_AUDIOOUT_HPVOL_VOLUME_UPDATE_PENDING     0x10000000
-#define BF_AUDIOOUT_HPVOL_VOLUME_UPDATE_PENDING(v)  (((v) << 28) & 0x10000000)
-#define BP_AUDIOOUT_HPVOL_RSRVD4                    26
-#define BM_AUDIOOUT_HPVOL_RSRVD4                    0xc000000
-#define BF_AUDIOOUT_HPVOL_RSRVD4(v)                 (((v) << 26) & 0xc000000)
-#define BP_AUDIOOUT_HPVOL_EN_MSTR_ZCD               25
-#define BM_AUDIOOUT_HPVOL_EN_MSTR_ZCD               0x2000000
-#define BF_AUDIOOUT_HPVOL_EN_MSTR_ZCD(v)            (((v) << 25) & 0x2000000)
-#define BP_AUDIOOUT_HPVOL_MUTE                      24
-#define BM_AUDIOOUT_HPVOL_MUTE                      0x1000000
-#define BF_AUDIOOUT_HPVOL_MUTE(v)                   (((v) << 24) & 0x1000000)
-#define BP_AUDIOOUT_HPVOL_RSRVD3                    17
-#define BM_AUDIOOUT_HPVOL_RSRVD3                    0xfe0000
-#define BF_AUDIOOUT_HPVOL_RSRVD3(v)                 (((v) << 17) & 0xfe0000)
-#define BP_AUDIOOUT_HPVOL_SELECT                    16
-#define BM_AUDIOOUT_HPVOL_SELECT                    0x10000
-#define BF_AUDIOOUT_HPVOL_SELECT(v)                 (((v) << 16) & 0x10000)
-#define BP_AUDIOOUT_HPVOL_RSRVD2                    15
-#define BM_AUDIOOUT_HPVOL_RSRVD2                    0x8000
-#define BF_AUDIOOUT_HPVOL_RSRVD2(v)                 (((v) << 15) & 0x8000)
-#define BP_AUDIOOUT_HPVOL_VOL_LEFT                  8
-#define BM_AUDIOOUT_HPVOL_VOL_LEFT                  0x7f00
-#define BF_AUDIOOUT_HPVOL_VOL_LEFT(v)               (((v) << 8) & 0x7f00)
-#define BP_AUDIOOUT_HPVOL_RSRVD1                    7
-#define BM_AUDIOOUT_HPVOL_RSRVD1                    0x80
-#define BF_AUDIOOUT_HPVOL_RSRVD1(v)                 (((v) << 7) & 0x80)
-#define BP_AUDIOOUT_HPVOL_VOL_RIGHT                 0
-#define BM_AUDIOOUT_HPVOL_VOL_RIGHT                 0x7f
-#define BF_AUDIOOUT_HPVOL_VOL_RIGHT(v)              (((v) << 0) & 0x7f)
-
-/**
- * Register: HW_AUDIOOUT_RESERVED
- * Address: 0x60
- * SCT: yes
-*/
-#define HW_AUDIOOUT_RESERVED            (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x60 + 0x0))
-#define HW_AUDIOOUT_RESERVED_SET        (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x60 + 0x4))
-#define HW_AUDIOOUT_RESERVED_CLR        (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x60 + 0x8))
-#define HW_AUDIOOUT_RESERVED_TOG        (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x60 + 0xc))
-#define BP_AUDIOOUT_RESERVED_RSRVD1     0
-#define BM_AUDIOOUT_RESERVED_RSRVD1     0xffffffff
-#define BF_AUDIOOUT_RESERVED_RSRVD1(v)  (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_AUDIOOUT_PWRDN
- * Address: 0x70
- * SCT: yes
-*/
-#define HW_AUDIOOUT_PWRDN               (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x70 + 0x0))
-#define HW_AUDIOOUT_PWRDN_SET           (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x70 + 0x4))
-#define HW_AUDIOOUT_PWRDN_CLR           (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x70 + 0x8))
-#define HW_AUDIOOUT_PWRDN_TOG           (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x70 + 0xc))
-#define BP_AUDIOOUT_PWRDN_RSRVD7        25
-#define BM_AUDIOOUT_PWRDN_RSRVD7        0xfe000000
-#define BF_AUDIOOUT_PWRDN_RSRVD7(v)     (((v) << 25) & 0xfe000000)
-#define BP_AUDIOOUT_PWRDN_SPEAKER       24
-#define BM_AUDIOOUT_PWRDN_SPEAKER       0x1000000
-#define BF_AUDIOOUT_PWRDN_SPEAKER(v)    (((v) << 24) & 0x1000000)
-#define BP_AUDIOOUT_PWRDN_RSRVD6        21
-#define BM_AUDIOOUT_PWRDN_RSRVD6        0xe00000
-#define BF_AUDIOOUT_PWRDN_RSRVD6(v)     (((v) << 21) & 0xe00000)
-#define BP_AUDIOOUT_PWRDN_SELFBIAS      20
-#define BM_AUDIOOUT_PWRDN_SELFBIAS      0x100000
-#define BF_AUDIOOUT_PWRDN_SELFBIAS(v)   (((v) << 20) & 0x100000)
-#define BP_AUDIOOUT_PWRDN_RSRVD5        17
-#define BM_AUDIOOUT_PWRDN_RSRVD5        0xe0000
-#define BF_AUDIOOUT_PWRDN_RSRVD5(v)     (((v) << 17) & 0xe0000)
-#define BP_AUDIOOUT_PWRDN_RIGHT_ADC     16
-#define BM_AUDIOOUT_PWRDN_RIGHT_ADC     0x10000
-#define BF_AUDIOOUT_PWRDN_RIGHT_ADC(v)  (((v) << 16) & 0x10000)
-#define BP_AUDIOOUT_PWRDN_RSRVD4        13
-#define BM_AUDIOOUT_PWRDN_RSRVD4        0xe000
-#define BF_AUDIOOUT_PWRDN_RSRVD4(v)     (((v) << 13) & 0xe000)
-#define BP_AUDIOOUT_PWRDN_DAC           12
-#define BM_AUDIOOUT_PWRDN_DAC           0x1000
-#define BF_AUDIOOUT_PWRDN_DAC(v)        (((v) << 12) & 0x1000)
-#define BP_AUDIOOUT_PWRDN_RSRVD3        9
-#define BM_AUDIOOUT_PWRDN_RSRVD3        0xe00
-#define BF_AUDIOOUT_PWRDN_RSRVD3(v)     (((v) << 9) & 0xe00)
-#define BP_AUDIOOUT_PWRDN_ADC           8
-#define BM_AUDIOOUT_PWRDN_ADC           0x100
-#define BF_AUDIOOUT_PWRDN_ADC(v)        (((v) << 8) & 0x100)
-#define BP_AUDIOOUT_PWRDN_RSRVD2        5
-#define BM_AUDIOOUT_PWRDN_RSRVD2        0xe0
-#define BF_AUDIOOUT_PWRDN_RSRVD2(v)     (((v) << 5) & 0xe0)
-#define BP_AUDIOOUT_PWRDN_CAPLESS       4
-#define BM_AUDIOOUT_PWRDN_CAPLESS       0x10
-#define BF_AUDIOOUT_PWRDN_CAPLESS(v)    (((v) << 4) & 0x10)
-#define BP_AUDIOOUT_PWRDN_RSRVD1        1
-#define BM_AUDIOOUT_PWRDN_RSRVD1        0xe
-#define BF_AUDIOOUT_PWRDN_RSRVD1(v)     (((v) << 1) & 0xe)
-#define BP_AUDIOOUT_PWRDN_HEADPHONE     0
-#define BM_AUDIOOUT_PWRDN_HEADPHONE     0x1
-#define BF_AUDIOOUT_PWRDN_HEADPHONE(v)  (((v) << 0) & 0x1)
-
-/**
- * Register: HW_AUDIOOUT_REFCTRL
- * Address: 0x80
- * SCT: yes
-*/
-#define HW_AUDIOOUT_REFCTRL                     (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x80 + 0x0))
-#define HW_AUDIOOUT_REFCTRL_SET                 (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x80 + 0x4))
-#define HW_AUDIOOUT_REFCTRL_CLR                 (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x80 + 0x8))
-#define HW_AUDIOOUT_REFCTRL_TOG                 (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x80 + 0xc))
-#define BP_AUDIOOUT_REFCTRL_RSRVD4              27
-#define BM_AUDIOOUT_REFCTRL_RSRVD4              0xf8000000
-#define BF_AUDIOOUT_REFCTRL_RSRVD4(v)           (((v) << 27) & 0xf8000000)
-#define BP_AUDIOOUT_REFCTRL_FASTSETTLING        26
-#define BM_AUDIOOUT_REFCTRL_FASTSETTLING        0x4000000
-#define BF_AUDIOOUT_REFCTRL_FASTSETTLING(v)     (((v) << 26) & 0x4000000)
-#define BP_AUDIOOUT_REFCTRL_RAISE_REF           25
-#define BM_AUDIOOUT_REFCTRL_RAISE_REF           0x2000000
-#define BF_AUDIOOUT_REFCTRL_RAISE_REF(v)        (((v) << 25) & 0x2000000)
-#define BP_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS       24
-#define BM_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS       0x1000000
-#define BF_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS(v)    (((v) << 24) & 0x1000000)
-#define BP_AUDIOOUT_REFCTRL_RSRVD3              23
-#define BM_AUDIOOUT_REFCTRL_RSRVD3              0x800000
-#define BF_AUDIOOUT_REFCTRL_RSRVD3(v)           (((v) << 23) & 0x800000)
-#define BP_AUDIOOUT_REFCTRL_VBG_ADJ             20
-#define BM_AUDIOOUT_REFCTRL_VBG_ADJ             0x700000
-#define BF_AUDIOOUT_REFCTRL_VBG_ADJ(v)          (((v) << 20) & 0x700000)
-#define BP_AUDIOOUT_REFCTRL_LOW_PWR             19
-#define BM_AUDIOOUT_REFCTRL_LOW_PWR             0x80000
-#define BF_AUDIOOUT_REFCTRL_LOW_PWR(v)          (((v) << 19) & 0x80000)
-#define BP_AUDIOOUT_REFCTRL_LW_REF              18
-#define BM_AUDIOOUT_REFCTRL_LW_REF              0x40000
-#define BF_AUDIOOUT_REFCTRL_LW_REF(v)           (((v) << 18) & 0x40000)
-#define BP_AUDIOOUT_REFCTRL_BIAS_CTRL           16
-#define BM_AUDIOOUT_REFCTRL_BIAS_CTRL           0x30000
-#define BF_AUDIOOUT_REFCTRL_BIAS_CTRL(v)        (((v) << 16) & 0x30000)
-#define BP_AUDIOOUT_REFCTRL_RSRVD2              15
-#define BM_AUDIOOUT_REFCTRL_RSRVD2              0x8000
-#define BF_AUDIOOUT_REFCTRL_RSRVD2(v)           (((v) << 15) & 0x8000)
-#define BP_AUDIOOUT_REFCTRL_VDDXTAL_TO_VDDD     14
-#define BM_AUDIOOUT_REFCTRL_VDDXTAL_TO_VDDD     0x4000
-#define BF_AUDIOOUT_REFCTRL_VDDXTAL_TO_VDDD(v)  (((v) << 14) & 0x4000)
-#define BP_AUDIOOUT_REFCTRL_ADJ_ADC             13
-#define BM_AUDIOOUT_REFCTRL_ADJ_ADC             0x2000
-#define BF_AUDIOOUT_REFCTRL_ADJ_ADC(v)          (((v) << 13) & 0x2000)
-#define BP_AUDIOOUT_REFCTRL_ADJ_VAG             12
-#define BM_AUDIOOUT_REFCTRL_ADJ_VAG             0x1000
-#define BF_AUDIOOUT_REFCTRL_ADJ_VAG(v)          (((v) << 12) & 0x1000)
-#define BP_AUDIOOUT_REFCTRL_ADC_REFVAL          8
-#define BM_AUDIOOUT_REFCTRL_ADC_REFVAL          0xf00
-#define BF_AUDIOOUT_REFCTRL_ADC_REFVAL(v)       (((v) << 8) & 0xf00)
-#define BP_AUDIOOUT_REFCTRL_VAG_VAL             4
-#define BM_AUDIOOUT_REFCTRL_VAG_VAL             0xf0
-#define BF_AUDIOOUT_REFCTRL_VAG_VAL(v)          (((v) << 4) & 0xf0)
-#define BP_AUDIOOUT_REFCTRL_RSRVD1              3
-#define BM_AUDIOOUT_REFCTRL_RSRVD1              0x8
-#define BF_AUDIOOUT_REFCTRL_RSRVD1(v)           (((v) << 3) & 0x8)
-#define BP_AUDIOOUT_REFCTRL_DAC_ADJ             0
-#define BM_AUDIOOUT_REFCTRL_DAC_ADJ             0x7
-#define BF_AUDIOOUT_REFCTRL_DAC_ADJ(v)          (((v) << 0) & 0x7)
-
-/**
- * Register: HW_AUDIOOUT_ANACTRL
- * Address: 0x90
- * SCT: yes
-*/
-#define HW_AUDIOOUT_ANACTRL                     (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x90 + 0x0))
-#define HW_AUDIOOUT_ANACTRL_SET                 (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x90 + 0x4))
-#define HW_AUDIOOUT_ANACTRL_CLR                 (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x90 + 0x8))
-#define HW_AUDIOOUT_ANACTRL_TOG                 (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x90 + 0xc))
-#define BP_AUDIOOUT_ANACTRL_RSRVD8              29
-#define BM_AUDIOOUT_ANACTRL_RSRVD8              0xe0000000
-#define BF_AUDIOOUT_ANACTRL_RSRVD8(v)           (((v) << 29) & 0xe0000000)
-#define BP_AUDIOOUT_ANACTRL_SHORT_CM_STS        28
-#define BM_AUDIOOUT_ANACTRL_SHORT_CM_STS        0x10000000
-#define BF_AUDIOOUT_ANACTRL_SHORT_CM_STS(v)     (((v) << 28) & 0x10000000)
-#define BP_AUDIOOUT_ANACTRL_RSRVD7              25
-#define BM_AUDIOOUT_ANACTRL_RSRVD7              0xe000000
-#define BF_AUDIOOUT_ANACTRL_RSRVD7(v)           (((v) << 25) & 0xe000000)
-#define BP_AUDIOOUT_ANACTRL_SHORT_LR_STS        24
-#define BM_AUDIOOUT_ANACTRL_SHORT_LR_STS        0x1000000
-#define BF_AUDIOOUT_ANACTRL_SHORT_LR_STS(v)     (((v) << 24) & 0x1000000)
-#define BP_AUDIOOUT_ANACTRL_RSRVD6              22
-#define BM_AUDIOOUT_ANACTRL_RSRVD6              0xc00000
-#define BF_AUDIOOUT_ANACTRL_RSRVD6(v)           (((v) << 22) & 0xc00000)
-#define BP_AUDIOOUT_ANACTRL_SHORTMODE_CM        20
-#define BM_AUDIOOUT_ANACTRL_SHORTMODE_CM        0x300000
-#define BF_AUDIOOUT_ANACTRL_SHORTMODE_CM(v)     (((v) << 20) & 0x300000)
-#define BP_AUDIOOUT_ANACTRL_RSRVD5              19
-#define BM_AUDIOOUT_ANACTRL_RSRVD5              0x80000
-#define BF_AUDIOOUT_ANACTRL_RSRVD5(v)           (((v) << 19) & 0x80000)
-#define BP_AUDIOOUT_ANACTRL_SHORTMODE_LR        17
-#define BM_AUDIOOUT_ANACTRL_SHORTMODE_LR        0x60000
-#define BF_AUDIOOUT_ANACTRL_SHORTMODE_LR(v)     (((v) << 17) & 0x60000)
-#define BP_AUDIOOUT_ANACTRL_RSRVD4              15
-#define BM_AUDIOOUT_ANACTRL_RSRVD4              0x18000
-#define BF_AUDIOOUT_ANACTRL_RSRVD4(v)           (((v) << 15) & 0x18000)
-#define BP_AUDIOOUT_ANACTRL_SHORT_LVLADJL       12
-#define BM_AUDIOOUT_ANACTRL_SHORT_LVLADJL       0x7000
-#define BF_AUDIOOUT_ANACTRL_SHORT_LVLADJL(v)    (((v) << 12) & 0x7000)
-#define BP_AUDIOOUT_ANACTRL_RSRVD3              11
-#define BM_AUDIOOUT_ANACTRL_RSRVD3              0x800
-#define BF_AUDIOOUT_ANACTRL_RSRVD3(v)           (((v) << 11) & 0x800)
-#define BP_AUDIOOUT_ANACTRL_SHORT_LVLADJR       8
-#define BM_AUDIOOUT_ANACTRL_SHORT_LVLADJR       0x700
-#define BF_AUDIOOUT_ANACTRL_SHORT_LVLADJR(v)    (((v) << 8) & 0x700)
-#define BP_AUDIOOUT_ANACTRL_RSRVD2              6
-#define BM_AUDIOOUT_ANACTRL_RSRVD2              0xc0
-#define BF_AUDIOOUT_ANACTRL_RSRVD2(v)           (((v) << 6) & 0xc0)
-#define BP_AUDIOOUT_ANACTRL_HP_HOLD_GND         5
-#define BM_AUDIOOUT_ANACTRL_HP_HOLD_GND         0x20
-#define BF_AUDIOOUT_ANACTRL_HP_HOLD_GND(v)      (((v) << 5) & 0x20)
-#define BP_AUDIOOUT_ANACTRL_HP_CLASSAB          4
-#define BM_AUDIOOUT_ANACTRL_HP_CLASSAB          0x10
-#define BF_AUDIOOUT_ANACTRL_HP_CLASSAB(v)       (((v) << 4) & 0x10)
-#define BP_AUDIOOUT_ANACTRL_RSRVD1              0
-#define BM_AUDIOOUT_ANACTRL_RSRVD1              0xf
-#define BF_AUDIOOUT_ANACTRL_RSRVD1(v)           (((v) << 0) & 0xf)
-
-/**
- * Register: HW_AUDIOOUT_TEST
- * Address: 0xa0
- * SCT: yes
-*/
-#define HW_AUDIOOUT_TEST                    (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xa0 + 0x0))
-#define HW_AUDIOOUT_TEST_SET                (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xa0 + 0x4))
-#define HW_AUDIOOUT_TEST_CLR                (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xa0 + 0x8))
-#define HW_AUDIOOUT_TEST_TOG                (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xa0 + 0xc))
-#define BP_AUDIOOUT_TEST_RSRVD4             31
-#define BM_AUDIOOUT_TEST_RSRVD4             0x80000000
-#define BF_AUDIOOUT_TEST_RSRVD4(v)          (((v) << 31) & 0x80000000)
-#define BP_AUDIOOUT_TEST_HP_ANTIPOP         28
-#define BM_AUDIOOUT_TEST_HP_ANTIPOP         0x70000000
-#define BF_AUDIOOUT_TEST_HP_ANTIPOP(v)      (((v) << 28) & 0x70000000)
-#define BP_AUDIOOUT_TEST_RSRVD3             27
-#define BM_AUDIOOUT_TEST_RSRVD3             0x8000000
-#define BF_AUDIOOUT_TEST_RSRVD3(v)          (((v) << 27) & 0x8000000)
-#define BP_AUDIOOUT_TEST_TM_ADCIN_TOHP      26
-#define BM_AUDIOOUT_TEST_TM_ADCIN_TOHP      0x4000000
-#define BF_AUDIOOUT_TEST_TM_ADCIN_TOHP(v)   (((v) << 26) & 0x4000000)
-#define BP_AUDIOOUT_TEST_TM_LOOP            25
-#define BM_AUDIOOUT_TEST_TM_LOOP            0x2000000
-#define BF_AUDIOOUT_TEST_TM_LOOP(v)         (((v) << 25) & 0x2000000)
-#define BP_AUDIOOUT_TEST_TM_HPCOMMON        24
-#define BM_AUDIOOUT_TEST_TM_HPCOMMON        0x1000000
-#define BF_AUDIOOUT_TEST_TM_HPCOMMON(v)     (((v) << 24) & 0x1000000)
-#define BP_AUDIOOUT_TEST_HP_I1_ADJ          22
-#define BM_AUDIOOUT_TEST_HP_I1_ADJ          0xc00000
-#define BF_AUDIOOUT_TEST_HP_I1_ADJ(v)       (((v) << 22) & 0xc00000)
-#define BP_AUDIOOUT_TEST_HP_IALL_ADJ        20
-#define BM_AUDIOOUT_TEST_HP_IALL_ADJ        0x300000
-#define BF_AUDIOOUT_TEST_HP_IALL_ADJ(v)     (((v) << 20) & 0x300000)
-#define BP_AUDIOOUT_TEST_RSRVD2             14
-#define BM_AUDIOOUT_TEST_RSRVD2             0xfc000
-#define BF_AUDIOOUT_TEST_RSRVD2(v)          (((v) << 14) & 0xfc000)
-#define BP_AUDIOOUT_TEST_VAG_CLASSA         13
-#define BM_AUDIOOUT_TEST_VAG_CLASSA         0x2000
-#define BF_AUDIOOUT_TEST_VAG_CLASSA(v)      (((v) << 13) & 0x2000)
-#define BP_AUDIOOUT_TEST_VAG_DOUBLE_I       12
-#define BM_AUDIOOUT_TEST_VAG_DOUBLE_I       0x1000
-#define BF_AUDIOOUT_TEST_VAG_DOUBLE_I(v)    (((v) << 12) & 0x1000)
-#define BP_AUDIOOUT_TEST_RSRVD1             4
-#define BM_AUDIOOUT_TEST_RSRVD1             0xff0
-#define BF_AUDIOOUT_TEST_RSRVD1(v)          (((v) << 4) & 0xff0)
-#define BP_AUDIOOUT_TEST_ADCTODAC_LOOP      3
-#define BM_AUDIOOUT_TEST_ADCTODAC_LOOP      0x8
-#define BF_AUDIOOUT_TEST_ADCTODAC_LOOP(v)   (((v) << 3) & 0x8)
-#define BP_AUDIOOUT_TEST_DAC_CLASSA         2
-#define BM_AUDIOOUT_TEST_DAC_CLASSA         0x4
-#define BF_AUDIOOUT_TEST_DAC_CLASSA(v)      (((v) << 2) & 0x4)
-#define BP_AUDIOOUT_TEST_DAC_DOUBLE_I       1
-#define BM_AUDIOOUT_TEST_DAC_DOUBLE_I       0x2
-#define BF_AUDIOOUT_TEST_DAC_DOUBLE_I(v)    (((v) << 1) & 0x2)
-#define BP_AUDIOOUT_TEST_DAC_DIS_RTZ        0
-#define BM_AUDIOOUT_TEST_DAC_DIS_RTZ        0x1
-#define BF_AUDIOOUT_TEST_DAC_DIS_RTZ(v)     (((v) << 0) & 0x1)
-
-/**
- * Register: HW_AUDIOOUT_BISTCTRL
- * Address: 0xb0
- * SCT: yes
-*/
-#define HW_AUDIOOUT_BISTCTRL            (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xb0 + 0x0))
-#define HW_AUDIOOUT_BISTCTRL_SET        (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xb0 + 0x4))
-#define HW_AUDIOOUT_BISTCTRL_CLR        (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xb0 + 0x8))
-#define HW_AUDIOOUT_BISTCTRL_TOG        (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xb0 + 0xc))
-#define BP_AUDIOOUT_BISTCTRL_RSVD0      4
-#define BM_AUDIOOUT_BISTCTRL_RSVD0      0xfffffff0
-#define BF_AUDIOOUT_BISTCTRL_RSVD0(v)   (((v) << 4) & 0xfffffff0)
-#define BP_AUDIOOUT_BISTCTRL_FAIL       3
-#define BM_AUDIOOUT_BISTCTRL_FAIL       0x8
-#define BF_AUDIOOUT_BISTCTRL_FAIL(v)    (((v) << 3) & 0x8)
-#define BP_AUDIOOUT_BISTCTRL_PASS       2
-#define BM_AUDIOOUT_BISTCTRL_PASS       0x4
-#define BF_AUDIOOUT_BISTCTRL_PASS(v)    (((v) << 2) & 0x4)
-#define BP_AUDIOOUT_BISTCTRL_DONE       1
-#define BM_AUDIOOUT_BISTCTRL_DONE       0x2
-#define BF_AUDIOOUT_BISTCTRL_DONE(v)    (((v) << 1) & 0x2)
-#define BP_AUDIOOUT_BISTCTRL_START      0
-#define BM_AUDIOOUT_BISTCTRL_START      0x1
-#define BF_AUDIOOUT_BISTCTRL_START(v)   (((v) << 0) & 0x1)
-
-/**
- * Register: HW_AUDIOOUT_BISTSTAT0
- * Address: 0xc0
- * SCT: yes
-*/
-#define HW_AUDIOOUT_BISTSTAT0           (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xc0 + 0x0))
-#define HW_AUDIOOUT_BISTSTAT0_SET       (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xc0 + 0x4))
-#define HW_AUDIOOUT_BISTSTAT0_CLR       (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xc0 + 0x8))
-#define HW_AUDIOOUT_BISTSTAT0_TOG       (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xc0 + 0xc))
-#define BP_AUDIOOUT_BISTSTAT0_RSVD0     24
-#define BM_AUDIOOUT_BISTSTAT0_RSVD0     0xff000000
-#define BF_AUDIOOUT_BISTSTAT0_RSVD0(v)  (((v) << 24) & 0xff000000)
-#define BP_AUDIOOUT_BISTSTAT0_DATA      0
-#define BM_AUDIOOUT_BISTSTAT0_DATA      0xffffff
-#define BF_AUDIOOUT_BISTSTAT0_DATA(v)   (((v) << 0) & 0xffffff)
-
-/**
- * Register: HW_AUDIOOUT_BISTSTAT1
- * Address: 0xd0
- * SCT: yes
-*/
-#define HW_AUDIOOUT_BISTSTAT1           (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xd0 + 0x0))
-#define HW_AUDIOOUT_BISTSTAT1_SET       (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xd0 + 0x4))
-#define HW_AUDIOOUT_BISTSTAT1_CLR       (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xd0 + 0x8))
-#define HW_AUDIOOUT_BISTSTAT1_TOG       (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xd0 + 0xc))
-#define BP_AUDIOOUT_BISTSTAT1_RSVD1     29
-#define BM_AUDIOOUT_BISTSTAT1_RSVD1     0xe0000000
-#define BF_AUDIOOUT_BISTSTAT1_RSVD1(v)  (((v) << 29) & 0xe0000000)
-#define BP_AUDIOOUT_BISTSTAT1_STATE     24
-#define BM_AUDIOOUT_BISTSTAT1_STATE     0x1f000000
-#define BF_AUDIOOUT_BISTSTAT1_STATE(v)  (((v) << 24) & 0x1f000000)
-#define BP_AUDIOOUT_BISTSTAT1_RSVD0     8
-#define BM_AUDIOOUT_BISTSTAT1_RSVD0     0xffff00
-#define BF_AUDIOOUT_BISTSTAT1_RSVD0(v)  (((v) << 8) & 0xffff00)
-#define BP_AUDIOOUT_BISTSTAT1_ADDR      0
-#define BM_AUDIOOUT_BISTSTAT1_ADDR      0xff
-#define BF_AUDIOOUT_BISTSTAT1_ADDR(v)   (((v) << 0) & 0xff)
-
-/**
- * Register: HW_AUDIOOUT_ANACLKCTRL
- * Address: 0xe0
- * SCT: yes
-*/
-#define HW_AUDIOOUT_ANACLKCTRL                  (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xe0 + 0x0))
-#define HW_AUDIOOUT_ANACLKCTRL_SET              (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xe0 + 0x4))
-#define HW_AUDIOOUT_ANACLKCTRL_CLR              (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xe0 + 0x8))
-#define HW_AUDIOOUT_ANACLKCTRL_TOG              (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xe0 + 0xc))
-#define BP_AUDIOOUT_ANACLKCTRL_CLKGATE          31
-#define BM_AUDIOOUT_ANACLKCTRL_CLKGATE          0x80000000
-#define BF_AUDIOOUT_ANACLKCTRL_CLKGATE(v)       (((v) << 31) & 0x80000000)
-#define BP_AUDIOOUT_ANACLKCTRL_RSRVD3           5
-#define BM_AUDIOOUT_ANACLKCTRL_RSRVD3           0x7fffffe0
-#define BF_AUDIOOUT_ANACLKCTRL_RSRVD3(v)        (((v) << 5) & 0x7fffffe0)
-#define BP_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK    4
-#define BM_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK    0x10
-#define BF_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK(v) (((v) << 4) & 0x10)
-#define BP_AUDIOOUT_ANACLKCTRL_RSRVD2           3
-#define BM_AUDIOOUT_ANACLKCTRL_RSRVD2           0x8
-#define BF_AUDIOOUT_ANACLKCTRL_RSRVD2(v)        (((v) << 3) & 0x8)
-#define BP_AUDIOOUT_ANACLKCTRL_DACDIV           0
-#define BM_AUDIOOUT_ANACLKCTRL_DACDIV           0x7
-#define BF_AUDIOOUT_ANACLKCTRL_DACDIV(v)        (((v) << 0) & 0x7)
-
-/**
- * Register: HW_AUDIOOUT_DATA
- * Address: 0xf0
- * SCT: yes
-*/
-#define HW_AUDIOOUT_DATA            (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xf0 + 0x0))
-#define HW_AUDIOOUT_DATA_SET        (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xf0 + 0x4))
-#define HW_AUDIOOUT_DATA_CLR        (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xf0 + 0x8))
-#define HW_AUDIOOUT_DATA_TOG        (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xf0 + 0xc))
-#define BP_AUDIOOUT_DATA_HIGH       16
-#define BM_AUDIOOUT_DATA_HIGH       0xffff0000
-#define BF_AUDIOOUT_DATA_HIGH(v)    (((v) << 16) & 0xffff0000)
-#define BP_AUDIOOUT_DATA_LOW        0
-#define BM_AUDIOOUT_DATA_LOW        0xffff
-#define BF_AUDIOOUT_DATA_LOW(v)     (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_AUDIOOUT_SPEAKERCTRL
- * Address: 0x100
- * SCT: yes
-*/
-#define HW_AUDIOOUT_SPEAKERCTRL                 (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x100 + 0x0))
-#define HW_AUDIOOUT_SPEAKERCTRL_SET             (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x100 + 0x4))
-#define HW_AUDIOOUT_SPEAKERCTRL_CLR             (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x100 + 0x8))
-#define HW_AUDIOOUT_SPEAKERCTRL_TOG             (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x100 + 0xc))
-#define BP_AUDIOOUT_SPEAKERCTRL_RSRVD2          25
-#define BM_AUDIOOUT_SPEAKERCTRL_RSRVD2          0xfe000000
-#define BF_AUDIOOUT_SPEAKERCTRL_RSRVD2(v)       (((v) << 25) & 0xfe000000)
-#define BP_AUDIOOUT_SPEAKERCTRL_MUTE            24
-#define BM_AUDIOOUT_SPEAKERCTRL_MUTE            0x1000000
-#define BF_AUDIOOUT_SPEAKERCTRL_MUTE(v)         (((v) << 24) & 0x1000000)
-#define BP_AUDIOOUT_SPEAKERCTRL_I1_ADJ          22
-#define BM_AUDIOOUT_SPEAKERCTRL_I1_ADJ          0xc00000
-#define BF_AUDIOOUT_SPEAKERCTRL_I1_ADJ(v)       (((v) << 22) & 0xc00000)
-#define BP_AUDIOOUT_SPEAKERCTRL_IALL_ADJ        20
-#define BM_AUDIOOUT_SPEAKERCTRL_IALL_ADJ        0x300000
-#define BF_AUDIOOUT_SPEAKERCTRL_IALL_ADJ(v)     (((v) << 20) & 0x300000)
-#define BP_AUDIOOUT_SPEAKERCTRL_RSRVD1          16
-#define BM_AUDIOOUT_SPEAKERCTRL_RSRVD1          0xf0000
-#define BF_AUDIOOUT_SPEAKERCTRL_RSRVD1(v)       (((v) << 16) & 0xf0000)
-#define BP_AUDIOOUT_SPEAKERCTRL_POSDRIVER       14
-#define BM_AUDIOOUT_SPEAKERCTRL_POSDRIVER       0xc000
-#define BF_AUDIOOUT_SPEAKERCTRL_POSDRIVER(v)    (((v) << 14) & 0xc000)
-#define BP_AUDIOOUT_SPEAKERCTRL_NEGDRIVER       12
-#define BM_AUDIOOUT_SPEAKERCTRL_NEGDRIVER       0x3000
-#define BF_AUDIOOUT_SPEAKERCTRL_NEGDRIVER(v)    (((v) << 12) & 0x3000)
-#define BP_AUDIOOUT_SPEAKERCTRL_RSRVD0          0
-#define BM_AUDIOOUT_SPEAKERCTRL_RSRVD0          0xfff
-#define BF_AUDIOOUT_SPEAKERCTRL_RSRVD0(v)       (((v) << 0) & 0xfff)
-
-/**
- * Register: HW_AUDIOOUT_VERSION
- * Address: 0x200
- * SCT: no
-*/
-#define HW_AUDIOOUT_VERSION             (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x200))
-#define BP_AUDIOOUT_VERSION_MAJOR       24
-#define BM_AUDIOOUT_VERSION_MAJOR       0xff000000
-#define BF_AUDIOOUT_VERSION_MAJOR(v)    (((v) << 24) & 0xff000000)
-#define BP_AUDIOOUT_VERSION_MINOR       16
-#define BM_AUDIOOUT_VERSION_MINOR       0xff0000
-#define BF_AUDIOOUT_VERSION_MINOR(v)    (((v) << 16) & 0xff0000)
-#define BP_AUDIOOUT_VERSION_STEP        0
-#define BM_AUDIOOUT_VERSION_STEP        0xffff
-#define BF_AUDIOOUT_VERSION_STEP(v)     (((v) << 0) & 0xffff)
-
-#endif /* __HEADERGEN__IMX233__AUDIOOUT__H__ */
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-bch.h b/firmware/target/arm/imx233/regs/imx233/regs-bch.h
deleted file mode 100644
index e4d7008d68..0000000000
--- a/firmware/target/arm/imx233/regs/imx233/regs-bch.h
+++ /dev/null
@@ -1,606 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: imx233:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__IMX233__BCH__H__
-#define __HEADERGEN__IMX233__BCH__H__
-
-#define REGS_BCH_BASE (0x8000a000)
-
-#define REGS_BCH_VERSION "3.2.0"
-
-/**
- * Register: HW_BCH_CTRL
- * Address: 0
- * SCT: yes
-*/
-#define HW_BCH_CTRL                         (*(volatile unsigned long *)(REGS_BCH_BASE + 0x0 + 0x0))
-#define HW_BCH_CTRL_SET                     (*(volatile unsigned long *)(REGS_BCH_BASE + 0x0 + 0x4))
-#define HW_BCH_CTRL_CLR                     (*(volatile unsigned long *)(REGS_BCH_BASE + 0x0 + 0x8))
-#define HW_BCH_CTRL_TOG                     (*(volatile unsigned long *)(REGS_BCH_BASE + 0x0 + 0xc))
-#define BP_BCH_CTRL_SFTRST                  31
-#define BM_BCH_CTRL_SFTRST                  0x80000000
-#define BV_BCH_CTRL_SFTRST__RUN             0x0
-#define BV_BCH_CTRL_SFTRST__RESET           0x1
-#define BF_BCH_CTRL_SFTRST(v)               (((v) << 31) & 0x80000000)
-#define BF_BCH_CTRL_SFTRST_V(v)             ((BV_BCH_CTRL_SFTRST__##v << 31) & 0x80000000)
-#define BP_BCH_CTRL_CLKGATE                 30
-#define BM_BCH_CTRL_CLKGATE                 0x40000000
-#define BV_BCH_CTRL_CLKGATE__RUN            0x0
-#define BV_BCH_CTRL_CLKGATE__NO_CLKS        0x1
-#define BF_BCH_CTRL_CLKGATE(v)              (((v) << 30) & 0x40000000)
-#define BF_BCH_CTRL_CLKGATE_V(v)            ((BV_BCH_CTRL_CLKGATE__##v << 30) & 0x40000000)
-#define BP_BCH_CTRL_RSVD5                   23
-#define BM_BCH_CTRL_RSVD5                   0x3f800000
-#define BF_BCH_CTRL_RSVD5(v)                (((v) << 23) & 0x3f800000)
-#define BP_BCH_CTRL_DEBUGSYNDROME           22
-#define BM_BCH_CTRL_DEBUGSYNDROME           0x400000
-#define BF_BCH_CTRL_DEBUGSYNDROME(v)        (((v) << 22) & 0x400000)
-#define BP_BCH_CTRL_RSVD4                   20
-#define BM_BCH_CTRL_RSVD4                   0x300000
-#define BF_BCH_CTRL_RSVD4(v)                (((v) << 20) & 0x300000)
-#define BP_BCH_CTRL_M2M_LAYOUT              18
-#define BM_BCH_CTRL_M2M_LAYOUT              0xc0000
-#define BF_BCH_CTRL_M2M_LAYOUT(v)           (((v) << 18) & 0xc0000)
-#define BP_BCH_CTRL_M2M_ENCODE              17
-#define BM_BCH_CTRL_M2M_ENCODE              0x20000
-#define BF_BCH_CTRL_M2M_ENCODE(v)           (((v) << 17) & 0x20000)
-#define BP_BCH_CTRL_M2M_ENABLE              16
-#define BM_BCH_CTRL_M2M_ENABLE              0x10000
-#define BF_BCH_CTRL_M2M_ENABLE(v)           (((v) << 16) & 0x10000)
-#define BP_BCH_CTRL_RSVD3                   11
-#define BM_BCH_CTRL_RSVD3                   0xf800
-#define BF_BCH_CTRL_RSVD3(v)                (((v) << 11) & 0xf800)
-#define BP_BCH_CTRL_DEBUG_STALL_IRQ_EN      10
-#define BM_BCH_CTRL_DEBUG_STALL_IRQ_EN      0x400
-#define BF_BCH_CTRL_DEBUG_STALL_IRQ_EN(v)   (((v) << 10) & 0x400)
-#define BP_BCH_CTRL_RSVD2                   9
-#define BM_BCH_CTRL_RSVD2                   0x200
-#define BF_BCH_CTRL_RSVD2(v)                (((v) << 9) & 0x200)
-#define BP_BCH_CTRL_COMPLETE_IRQ_EN         8
-#define BM_BCH_CTRL_COMPLETE_IRQ_EN         0x100
-#define BF_BCH_CTRL_COMPLETE_IRQ_EN(v)      (((v) << 8) & 0x100)
-#define BP_BCH_CTRL_RSVD1                   4
-#define BM_BCH_CTRL_RSVD1                   0xf0
-#define BF_BCH_CTRL_RSVD1(v)                (((v) << 4) & 0xf0)
-#define BP_BCH_CTRL_BM_ERROR_IRQ            3
-#define BM_BCH_CTRL_BM_ERROR_IRQ            0x8
-#define BF_BCH_CTRL_BM_ERROR_IRQ(v)         (((v) << 3) & 0x8)
-#define BP_BCH_CTRL_DEBUG_STALL_IRQ         2
-#define BM_BCH_CTRL_DEBUG_STALL_IRQ         0x4
-#define BF_BCH_CTRL_DEBUG_STALL_IRQ(v)      (((v) << 2) & 0x4)
-#define BP_BCH_CTRL_RSVD0                   1
-#define BM_BCH_CTRL_RSVD0                   0x2
-#define BF_BCH_CTRL_RSVD0(v)                (((v) << 1) & 0x2)
-#define BP_BCH_CTRL_COMPLETE_IRQ            0
-#define BM_BCH_CTRL_COMPLETE_IRQ            0x1
-#define BF_BCH_CTRL_COMPLETE_IRQ(v)         (((v) << 0) & 0x1)
-
-/**
- * Register: HW_BCH_STATUS0
- * Address: 0x10
- * SCT: no
-*/
-#define HW_BCH_STATUS0                              (*(volatile unsigned long *)(REGS_BCH_BASE + 0x10))
-#define BP_BCH_STATUS0_HANDLE                       20
-#define BM_BCH_STATUS0_HANDLE                       0xfff00000
-#define BF_BCH_STATUS0_HANDLE(v)                    (((v) << 20) & 0xfff00000)
-#define BP_BCH_STATUS0_COMPLETED_CE                 16
-#define BM_BCH_STATUS0_COMPLETED_CE                 0xf0000
-#define BF_BCH_STATUS0_COMPLETED_CE(v)              (((v) << 16) & 0xf0000)
-#define BP_BCH_STATUS0_STATUS_BLK0                  8
-#define BM_BCH_STATUS0_STATUS_BLK0                  0xff00
-#define BV_BCH_STATUS0_STATUS_BLK0__ZERO            0x0
-#define BV_BCH_STATUS0_STATUS_BLK0__ERROR1          0x1
-#define BV_BCH_STATUS0_STATUS_BLK0__ERROR2          0x2
-#define BV_BCH_STATUS0_STATUS_BLK0__ERROR3          0x3
-#define BV_BCH_STATUS0_STATUS_BLK0__ERROR4          0x4
-#define BV_BCH_STATUS0_STATUS_BLK0__UNCORRECTABLE   0xfe
-#define BV_BCH_STATUS0_STATUS_BLK0__ERASED          0xff
-#define BF_BCH_STATUS0_STATUS_BLK0(v)               (((v) << 8) & 0xff00)
-#define BF_BCH_STATUS0_STATUS_BLK0_V(v)             ((BV_BCH_STATUS0_STATUS_BLK0__##v << 8) & 0xff00)
-#define BP_BCH_STATUS0_RSVD1                        5
-#define BM_BCH_STATUS0_RSVD1                        0xe0
-#define BF_BCH_STATUS0_RSVD1(v)                     (((v) << 5) & 0xe0)
-#define BP_BCH_STATUS0_ALLONES                      4
-#define BM_BCH_STATUS0_ALLONES                      0x10
-#define BF_BCH_STATUS0_ALLONES(v)                   (((v) << 4) & 0x10)
-#define BP_BCH_STATUS0_CORRECTED                    3
-#define BM_BCH_STATUS0_CORRECTED                    0x8
-#define BF_BCH_STATUS0_CORRECTED(v)                 (((v) << 3) & 0x8)
-#define BP_BCH_STATUS0_UNCORRECTABLE                2
-#define BM_BCH_STATUS0_UNCORRECTABLE                0x4
-#define BF_BCH_STATUS0_UNCORRECTABLE(v)             (((v) << 2) & 0x4)
-#define BP_BCH_STATUS0_RSVD0                        0
-#define BM_BCH_STATUS0_RSVD0                        0x3
-#define BF_BCH_STATUS0_RSVD0(v)                     (((v) << 0) & 0x3)
-
-/**
- * Register: HW_BCH_MODE
- * Address: 0x20
- * SCT: no
-*/
-#define HW_BCH_MODE                     (*(volatile unsigned long *)(REGS_BCH_BASE + 0x20))
-#define BP_BCH_MODE_RSVD                8
-#define BM_BCH_MODE_RSVD                0xffffff00
-#define BF_BCH_MODE_RSVD(v)             (((v) << 8) & 0xffffff00)
-#define BP_BCH_MODE_ERASE_THRESHOLD     0
-#define BM_BCH_MODE_ERASE_THRESHOLD     0xff
-#define BF_BCH_MODE_ERASE_THRESHOLD(v)  (((v) << 0) & 0xff)
-
-/**
- * Register: HW_BCH_ENCODEPTR
- * Address: 0x30
- * SCT: no
-*/
-#define HW_BCH_ENCODEPTR            (*(volatile unsigned long *)(REGS_BCH_BASE + 0x30))
-#define BP_BCH_ENCODEPTR_ADDR       0
-#define BM_BCH_ENCODEPTR_ADDR       0xffffffff
-#define BF_BCH_ENCODEPTR_ADDR(v)    (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_BCH_DATAPTR
- * Address: 0x40
- * SCT: no
-*/
-#define HW_BCH_DATAPTR          (*(volatile unsigned long *)(REGS_BCH_BASE + 0x40))
-#define BP_BCH_DATAPTR_ADDR     0
-#define BM_BCH_DATAPTR_ADDR     0xffffffff
-#define BF_BCH_DATAPTR_ADDR(v)  (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_BCH_METAPTR
- * Address: 0x50
- * SCT: no
-*/
-#define HW_BCH_METAPTR          (*(volatile unsigned long *)(REGS_BCH_BASE + 0x50))
-#define BP_BCH_METAPTR_ADDR     0
-#define BM_BCH_METAPTR_ADDR     0xffffffff
-#define BF_BCH_METAPTR_ADDR(v)  (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_BCH_LAYOUTSELECT
- * Address: 0x70
- * SCT: no
-*/
-#define HW_BCH_LAYOUTSELECT                 (*(volatile unsigned long *)(REGS_BCH_BASE + 0x70))
-#define BP_BCH_LAYOUTSELECT_CS15_SELECT     30
-#define BM_BCH_LAYOUTSELECT_CS15_SELECT     0xc0000000
-#define BF_BCH_LAYOUTSELECT_CS15_SELECT(v)  (((v) << 30) & 0xc0000000)
-#define BP_BCH_LAYOUTSELECT_CS14_SELECT     28
-#define BM_BCH_LAYOUTSELECT_CS14_SELECT     0x30000000
-#define BF_BCH_LAYOUTSELECT_CS14_SELECT(v)  (((v) << 28) & 0x30000000)
-#define BP_BCH_LAYOUTSELECT_CS13_SELECT     26
-#define BM_BCH_LAYOUTSELECT_CS13_SELECT     0xc000000
-#define BF_BCH_LAYOUTSELECT_CS13_SELECT(v)  (((v) << 26) & 0xc000000)
-#define BP_BCH_LAYOUTSELECT_CS12_SELECT     24
-#define BM_BCH_LAYOUTSELECT_CS12_SELECT     0x3000000
-#define BF_BCH_LAYOUTSELECT_CS12_SELECT(v)  (((v) << 24) & 0x3000000)
-#define BP_BCH_LAYOUTSELECT_CS11_SELECT     22
-#define BM_BCH_LAYOUTSELECT_CS11_SELECT     0xc00000
-#define BF_BCH_LAYOUTSELECT_CS11_SELECT(v)  (((v) << 22) & 0xc00000)
-#define BP_BCH_LAYOUTSELECT_CS10_SELECT     20
-#define BM_BCH_LAYOUTSELECT_CS10_SELECT     0x300000
-#define BF_BCH_LAYOUTSELECT_CS10_SELECT(v)  (((v) << 20) & 0x300000)
-#define BP_BCH_LAYOUTSELECT_CS9_SELECT      18
-#define BM_BCH_LAYOUTSELECT_CS9_SELECT      0xc0000
-#define BF_BCH_LAYOUTSELECT_CS9_SELECT(v)   (((v) << 18) & 0xc0000)
-#define BP_BCH_LAYOUTSELECT_CS8_SELECT      16
-#define BM_BCH_LAYOUTSELECT_CS8_SELECT      0x30000
-#define BF_BCH_LAYOUTSELECT_CS8_SELECT(v)   (((v) << 16) & 0x30000)
-#define BP_BCH_LAYOUTSELECT_CS7_SELECT      14
-#define BM_BCH_LAYOUTSELECT_CS7_SELECT      0xc000
-#define BF_BCH_LAYOUTSELECT_CS7_SELECT(v)   (((v) << 14) & 0xc000)
-#define BP_BCH_LAYOUTSELECT_CS6_SELECT      12
-#define BM_BCH_LAYOUTSELECT_CS6_SELECT      0x3000
-#define BF_BCH_LAYOUTSELECT_CS6_SELECT(v)   (((v) << 12) & 0x3000)
-#define BP_BCH_LAYOUTSELECT_CS5_SELECT      10
-#define BM_BCH_LAYOUTSELECT_CS5_SELECT      0xc00
-#define BF_BCH_LAYOUTSELECT_CS5_SELECT(v)   (((v) << 10) & 0xc00)
-#define BP_BCH_LAYOUTSELECT_CS4_SELECT      8
-#define BM_BCH_LAYOUTSELECT_CS4_SELECT      0x300
-#define BF_BCH_LAYOUTSELECT_CS4_SELECT(v)   (((v) << 8) & 0x300)
-#define BP_BCH_LAYOUTSELECT_CS3_SELECT      6
-#define BM_BCH_LAYOUTSELECT_CS3_SELECT      0xc0
-#define BF_BCH_LAYOUTSELECT_CS3_SELECT(v)   (((v) << 6) & 0xc0)
-#define BP_BCH_LAYOUTSELECT_CS2_SELECT      4
-#define BM_BCH_LAYOUTSELECT_CS2_SELECT      0x30
-#define BF_BCH_LAYOUTSELECT_CS2_SELECT(v)   (((v) << 4) & 0x30)
-#define BP_BCH_LAYOUTSELECT_CS1_SELECT      2
-#define BM_BCH_LAYOUTSELECT_CS1_SELECT      0xc
-#define BF_BCH_LAYOUTSELECT_CS1_SELECT(v)   (((v) << 2) & 0xc)
-#define BP_BCH_LAYOUTSELECT_CS0_SELECT      0
-#define BM_BCH_LAYOUTSELECT_CS0_SELECT      0x3
-#define BF_BCH_LAYOUTSELECT_CS0_SELECT(v)   (((v) << 0) & 0x3)
-
-/**
- * Register: HW_BCH_FLASH0LAYOUT0
- * Address: 0x80
- * SCT: no
-*/
-#define HW_BCH_FLASH0LAYOUT0                (*(volatile unsigned long *)(REGS_BCH_BASE + 0x80))
-#define BP_BCH_FLASH0LAYOUT0_NBLOCKS        24
-#define BM_BCH_FLASH0LAYOUT0_NBLOCKS        0xff000000
-#define BF_BCH_FLASH0LAYOUT0_NBLOCKS(v)     (((v) << 24) & 0xff000000)
-#define BP_BCH_FLASH0LAYOUT0_META_SIZE      16
-#define BM_BCH_FLASH0LAYOUT0_META_SIZE      0xff0000
-#define BF_BCH_FLASH0LAYOUT0_META_SIZE(v)   (((v) << 16) & 0xff0000)
-#define BP_BCH_FLASH0LAYOUT0_ECC0           12
-#define BM_BCH_FLASH0LAYOUT0_ECC0           0xf000
-#define BV_BCH_FLASH0LAYOUT0_ECC0__NONE     0x0
-#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC2     0x1
-#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC4     0x2
-#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC6     0x3
-#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC8     0x4
-#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC10    0x5
-#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC12    0x6
-#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC14    0x7
-#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC16    0x8
-#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC18    0x9
-#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC20    0xa
-#define BF_BCH_FLASH0LAYOUT0_ECC0(v)        (((v) << 12) & 0xf000)
-#define BF_BCH_FLASH0LAYOUT0_ECC0_V(v)      ((BV_BCH_FLASH0LAYOUT0_ECC0__##v << 12) & 0xf000)
-#define BP_BCH_FLASH0LAYOUT0_DATA0_SIZE     0
-#define BM_BCH_FLASH0LAYOUT0_DATA0_SIZE     0xfff
-#define BF_BCH_FLASH0LAYOUT0_DATA0_SIZE(v)  (((v) << 0) & 0xfff)
-
-/**
- * Register: HW_BCH_FLASH0LAYOUT1
- * Address: 0x90
- * SCT: no
-*/
-#define HW_BCH_FLASH0LAYOUT1                (*(volatile unsigned long *)(REGS_BCH_BASE + 0x90))
-#define BP_BCH_FLASH0LAYOUT1_PAGE_SIZE      16
-#define BM_BCH_FLASH0LAYOUT1_PAGE_SIZE      0xffff0000
-#define BF_BCH_FLASH0LAYOUT1_PAGE_SIZE(v)   (((v) << 16) & 0xffff0000)
-#define BP_BCH_FLASH0LAYOUT1_ECCN           12
-#define BM_BCH_FLASH0LAYOUT1_ECCN           0xf000
-#define BV_BCH_FLASH0LAYOUT1_ECCN__NONE     0x0
-#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC2     0x1
-#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC4     0x2
-#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC6     0x3
-#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC8     0x4
-#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC10    0x5
-#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC12    0x6
-#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC14    0x7
-#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC16    0x8
-#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC18    0x9
-#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC20    0xa
-#define BF_BCH_FLASH0LAYOUT1_ECCN(v)        (((v) << 12) & 0xf000)
-#define BF_BCH_FLASH0LAYOUT1_ECCN_V(v)      ((BV_BCH_FLASH0LAYOUT1_ECCN__##v << 12) & 0xf000)
-#define BP_BCH_FLASH0LAYOUT1_DATAN_SIZE     0
-#define BM_BCH_FLASH0LAYOUT1_DATAN_SIZE     0xfff
-#define BF_BCH_FLASH0LAYOUT1_DATAN_SIZE(v)  (((v) << 0) & 0xfff)
-
-/**
- * Register: HW_BCH_FLASH1LAYOUT0
- * Address: 0xa0
- * SCT: no
-*/
-#define HW_BCH_FLASH1LAYOUT0                (*(volatile unsigned long *)(REGS_BCH_BASE + 0xa0))
-#define BP_BCH_FLASH1LAYOUT0_NBLOCKS        24
-#define BM_BCH_FLASH1LAYOUT0_NBLOCKS        0xff000000
-#define BF_BCH_FLASH1LAYOUT0_NBLOCKS(v)     (((v) << 24) & 0xff000000)
-#define BP_BCH_FLASH1LAYOUT0_META_SIZE      16
-#define BM_BCH_FLASH1LAYOUT0_META_SIZE      0xff0000
-#define BF_BCH_FLASH1LAYOUT0_META_SIZE(v)   (((v) << 16) & 0xff0000)
-#define BP_BCH_FLASH1LAYOUT0_ECC0           12
-#define BM_BCH_FLASH1LAYOUT0_ECC0           0xf000
-#define BV_BCH_FLASH1LAYOUT0_ECC0__NONE     0x0
-#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC2     0x1
-#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC4     0x2
-#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC6     0x3
-#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC8     0x4
-#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC10    0x5
-#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC12    0x6
-#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC14    0x7
-#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC16    0x8
-#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC18    0x9
-#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC20    0xa
-#define BF_BCH_FLASH1LAYOUT0_ECC0(v)        (((v) << 12) & 0xf000)
-#define BF_BCH_FLASH1LAYOUT0_ECC0_V(v)      ((BV_BCH_FLASH1LAYOUT0_ECC0__##v << 12) & 0xf000)
-#define BP_BCH_FLASH1LAYOUT0_DATA0_SIZE     0
-#define BM_BCH_FLASH1LAYOUT0_DATA0_SIZE     0xfff
-#define BF_BCH_FLASH1LAYOUT0_DATA0_SIZE(v)  (((v) << 0) & 0xfff)
-
-/**
- * Register: HW_BCH_FLASH1LAYOUT1
- * Address: 0xb0
- * SCT: no
-*/
-#define HW_BCH_FLASH1LAYOUT1                (*(volatile unsigned long *)(REGS_BCH_BASE + 0xb0))
-#define BP_BCH_FLASH1LAYOUT1_PAGE_SIZE      16
-#define BM_BCH_FLASH1LAYOUT1_PAGE_SIZE      0xffff0000
-#define BF_BCH_FLASH1LAYOUT1_PAGE_SIZE(v)   (((v) << 16) & 0xffff0000)
-#define BP_BCH_FLASH1LAYOUT1_ECCN           12
-#define BM_BCH_FLASH1LAYOUT1_ECCN           0xf000
-#define BV_BCH_FLASH1LAYOUT1_ECCN__NONE     0x0
-#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC2     0x1
-#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC4     0x2
-#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC6     0x3
-#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC8     0x4
-#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC10    0x5
-#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC12    0x6
-#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC14    0x7
-#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC16    0x8
-#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC18    0x9
-#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC20    0xa
-#define BF_BCH_FLASH1LAYOUT1_ECCN(v)        (((v) << 12) & 0xf000)
-#define BF_BCH_FLASH1LAYOUT1_ECCN_V(v)      ((BV_BCH_FLASH1LAYOUT1_ECCN__##v << 12) & 0xf000)
-#define BP_BCH_FLASH1LAYOUT1_DATAN_SIZE     0
-#define BM_BCH_FLASH1LAYOUT1_DATAN_SIZE     0xfff
-#define BF_BCH_FLASH1LAYOUT1_DATAN_SIZE(v)  (((v) << 0) & 0xfff)
-
-/**
- * Register: HW_BCH_FLASH2LAYOUT0
- * Address: 0xc0
- * SCT: no
-*/
-#define HW_BCH_FLASH2LAYOUT0                (*(volatile unsigned long *)(REGS_BCH_BASE + 0xc0))
-#define BP_BCH_FLASH2LAYOUT0_NBLOCKS        24
-#define BM_BCH_FLASH2LAYOUT0_NBLOCKS        0xff000000
-#define BF_BCH_FLASH2LAYOUT0_NBLOCKS(v)     (((v) << 24) & 0xff000000)
-#define BP_BCH_FLASH2LAYOUT0_META_SIZE      16
-#define BM_BCH_FLASH2LAYOUT0_META_SIZE      0xff0000
-#define BF_BCH_FLASH2LAYOUT0_META_SIZE(v)   (((v) << 16) & 0xff0000)
-#define BP_BCH_FLASH2LAYOUT0_ECC0           12
-#define BM_BCH_FLASH2LAYOUT0_ECC0           0xf000
-#define BV_BCH_FLASH2LAYOUT0_ECC0__NONE     0x0
-#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC2     0x1
-#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC4     0x2
-#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC6     0x3
-#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC8     0x4
-#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC10    0x5
-#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC12    0x6
-#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC14    0x7
-#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC16    0x8
-#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC18    0x9
-#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC20    0xa
-#define BF_BCH_FLASH2LAYOUT0_ECC0(v)        (((v) << 12) & 0xf000)
-#define BF_BCH_FLASH2LAYOUT0_ECC0_V(v)      ((BV_BCH_FLASH2LAYOUT0_ECC0__##v << 12) & 0xf000)
-#define BP_BCH_FLASH2LAYOUT0_DATA0_SIZE     0
-#define BM_BCH_FLASH2LAYOUT0_DATA0_SIZE     0xfff
-#define BF_BCH_FLASH2LAYOUT0_DATA0_SIZE(v)  (((v) << 0) & 0xfff)
-
-/**
- * Register: HW_BCH_FLASH2LAYOUT1
- * Address: 0xd0
- * SCT: no
-*/
-#define HW_BCH_FLASH2LAYOUT1                (*(volatile unsigned long *)(REGS_BCH_BASE + 0xd0))
-#define BP_BCH_FLASH2LAYOUT1_PAGE_SIZE      16
-#define BM_BCH_FLASH2LAYOUT1_PAGE_SIZE      0xffff0000
-#define BF_BCH_FLASH2LAYOUT1_PAGE_SIZE(v)   (((v) << 16) & 0xffff0000)
-#define BP_BCH_FLASH2LAYOUT1_ECCN           12
-#define BM_BCH_FLASH2LAYOUT1_ECCN           0xf000
-#define BV_BCH_FLASH2LAYOUT1_ECCN__NONE     0x0
-#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC2     0x1
-#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC4     0x2
-#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC6     0x3
-#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC8     0x4
-#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC10    0x5
-#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC12    0x6
-#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC14    0x7
-#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC16    0x8
-#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC18    0x9
-#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC20    0xa
-#define BF_BCH_FLASH2LAYOUT1_ECCN(v)        (((v) << 12) & 0xf000)
-#define BF_BCH_FLASH2LAYOUT1_ECCN_V(v)      ((BV_BCH_FLASH2LAYOUT1_ECCN__##v << 12) & 0xf000)
-#define BP_BCH_FLASH2LAYOUT1_DATAN_SIZE     0
-#define BM_BCH_FLASH2LAYOUT1_DATAN_SIZE     0xfff
-#define BF_BCH_FLASH2LAYOUT1_DATAN_SIZE(v)  (((v) << 0) & 0xfff)
-
-/**
- * Register: HW_BCH_FLASH3LAYOUT0
- * Address: 0xe0
- * SCT: no
-*/
-#define HW_BCH_FLASH3LAYOUT0                (*(volatile unsigned long *)(REGS_BCH_BASE + 0xe0))
-#define BP_BCH_FLASH3LAYOUT0_NBLOCKS        24
-#define BM_BCH_FLASH3LAYOUT0_NBLOCKS        0xff000000
-#define BF_BCH_FLASH3LAYOUT0_NBLOCKS(v)     (((v) << 24) & 0xff000000)
-#define BP_BCH_FLASH3LAYOUT0_META_SIZE      16
-#define BM_BCH_FLASH3LAYOUT0_META_SIZE      0xff0000
-#define BF_BCH_FLASH3LAYOUT0_META_SIZE(v)   (((v) << 16) & 0xff0000)
-#define BP_BCH_FLASH3LAYOUT0_ECC0           12
-#define BM_BCH_FLASH3LAYOUT0_ECC0           0xf000
-#define BV_BCH_FLASH3LAYOUT0_ECC0__NONE     0x0
-#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC2     0x1
-#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC4     0x2
-#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC6     0x3
-#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC8     0x4
-#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC10    0x5
-#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC12    0x6
-#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC14    0x7
-#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC16    0x8
-#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC18    0x9
-#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC20    0xa
-#define BF_BCH_FLASH3LAYOUT0_ECC0(v)        (((v) << 12) & 0xf000)
-#define BF_BCH_FLASH3LAYOUT0_ECC0_V(v)      ((BV_BCH_FLASH3LAYOUT0_ECC0__##v << 12) & 0xf000)
-#define BP_BCH_FLASH3LAYOUT0_DATA0_SIZE     0
-#define BM_BCH_FLASH3LAYOUT0_DATA0_SIZE     0xfff
-#define BF_BCH_FLASH3LAYOUT0_DATA0_SIZE(v)  (((v) << 0) & 0xfff)
-
-/**
- * Register: HW_BCH_FLASH3LAYOUT1
- * Address: 0xf0
- * SCT: no
-*/
-#define HW_BCH_FLASH3LAYOUT1                (*(volatile unsigned long *)(REGS_BCH_BASE + 0xf0))
-#define BP_BCH_FLASH3LAYOUT1_PAGE_SIZE      16
-#define BM_BCH_FLASH3LAYOUT1_PAGE_SIZE      0xffff0000
-#define BF_BCH_FLASH3LAYOUT1_PAGE_SIZE(v)   (((v) << 16) & 0xffff0000)
-#define BP_BCH_FLASH3LAYOUT1_ECCN           12
-#define BM_BCH_FLASH3LAYOUT1_ECCN           0xf000
-#define BV_BCH_FLASH3LAYOUT1_ECCN__NONE     0x0
-#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC2     0x1
-#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC4     0x2
-#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC6     0x3
-#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC8     0x4
-#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC10    0x5
-#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC12    0x6
-#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC14    0x7
-#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC16    0x8
-#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC18    0x9
-#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC20    0xa
-#define BF_BCH_FLASH3LAYOUT1_ECCN(v)        (((v) << 12) & 0xf000)
-#define BF_BCH_FLASH3LAYOUT1_ECCN_V(v)      ((BV_BCH_FLASH3LAYOUT1_ECCN__##v << 12) & 0xf000)
-#define BP_BCH_FLASH3LAYOUT1_DATAN_SIZE     0
-#define BM_BCH_FLASH3LAYOUT1_DATAN_SIZE     0xfff
-#define BF_BCH_FLASH3LAYOUT1_DATAN_SIZE(v)  (((v) << 0) & 0xfff)
-
-/**
- * Register: HW_BCH_DEBUG0
- * Address: 0x100
- * SCT: yes
-*/
-#define HW_BCH_DEBUG0                                       (*(volatile unsigned long *)(REGS_BCH_BASE + 0x100 + 0x0))
-#define HW_BCH_DEBUG0_SET                                   (*(volatile unsigned long *)(REGS_BCH_BASE + 0x100 + 0x4))
-#define HW_BCH_DEBUG0_CLR                                   (*(volatile unsigned long *)(REGS_BCH_BASE + 0x100 + 0x8))
-#define HW_BCH_DEBUG0_TOG                                   (*(volatile unsigned long *)(REGS_BCH_BASE + 0x100 + 0xc))
-#define BP_BCH_DEBUG0_RSVD1                                 27
-#define BM_BCH_DEBUG0_RSVD1                                 0xf8000000
-#define BF_BCH_DEBUG0_RSVD1(v)                              (((v) << 27) & 0xf8000000)
-#define BP_BCH_DEBUG0_ROM_BIST_ENABLE                       26
-#define BM_BCH_DEBUG0_ROM_BIST_ENABLE                       0x4000000
-#define BF_BCH_DEBUG0_ROM_BIST_ENABLE(v)                    (((v) << 26) & 0x4000000)
-#define BP_BCH_DEBUG0_ROM_BIST_COMPLETE                     25
-#define BM_BCH_DEBUG0_ROM_BIST_COMPLETE                     0x2000000
-#define BF_BCH_DEBUG0_ROM_BIST_COMPLETE(v)                  (((v) << 25) & 0x2000000)
-#define BP_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL             16
-#define BM_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL             0x1ff0000
-#define BV_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__NORMAL     0x0
-#define BV_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__TEST_MODE  0x1
-#define BF_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL(v)          (((v) << 16) & 0x1ff0000)
-#define BF_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_V(v)        ((BV_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__##v << 16) & 0x1ff0000)
-#define BP_BCH_DEBUG0_KES_DEBUG_SHIFT_SYND                  15
-#define BM_BCH_DEBUG0_KES_DEBUG_SHIFT_SYND                  0x8000
-#define BF_BCH_DEBUG0_KES_DEBUG_SHIFT_SYND(v)               (((v) << 15) & 0x8000)
-#define BP_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG                14
-#define BM_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG                0x4000
-#define BV_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__DATA          0x1
-#define BV_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__AUX           0x1
-#define BF_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG(v)             (((v) << 14) & 0x4000)
-#define BF_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_V(v)           ((BV_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__##v << 14) & 0x4000)
-#define BP_BCH_DEBUG0_KES_DEBUG_MODE4K                      13
-#define BM_BCH_DEBUG0_KES_DEBUG_MODE4K                      0x2000
-#define BV_BCH_DEBUG0_KES_DEBUG_MODE4K__4k                  0x1
-#define BV_BCH_DEBUG0_KES_DEBUG_MODE4K__2k                  0x1
-#define BF_BCH_DEBUG0_KES_DEBUG_MODE4K(v)                   (((v) << 13) & 0x2000)
-#define BF_BCH_DEBUG0_KES_DEBUG_MODE4K_V(v)                 ((BV_BCH_DEBUG0_KES_DEBUG_MODE4K__##v << 13) & 0x2000)
-#define BP_BCH_DEBUG0_KES_DEBUG_KICK                        12
-#define BM_BCH_DEBUG0_KES_DEBUG_KICK                        0x1000
-#define BF_BCH_DEBUG0_KES_DEBUG_KICK(v)                     (((v) << 12) & 0x1000)
-#define BP_BCH_DEBUG0_KES_STANDALONE                        11
-#define BM_BCH_DEBUG0_KES_STANDALONE                        0x800
-#define BV_BCH_DEBUG0_KES_STANDALONE__NORMAL                0x0
-#define BV_BCH_DEBUG0_KES_STANDALONE__TEST_MODE             0x1
-#define BF_BCH_DEBUG0_KES_STANDALONE(v)                     (((v) << 11) & 0x800)
-#define BF_BCH_DEBUG0_KES_STANDALONE_V(v)                   ((BV_BCH_DEBUG0_KES_STANDALONE__##v << 11) & 0x800)
-#define BP_BCH_DEBUG0_KES_DEBUG_STEP                        10
-#define BM_BCH_DEBUG0_KES_DEBUG_STEP                        0x400
-#define BF_BCH_DEBUG0_KES_DEBUG_STEP(v)                     (((v) << 10) & 0x400)
-#define BP_BCH_DEBUG0_KES_DEBUG_STALL                       9
-#define BM_BCH_DEBUG0_KES_DEBUG_STALL                       0x200
-#define BV_BCH_DEBUG0_KES_DEBUG_STALL__NORMAL               0x0
-#define BV_BCH_DEBUG0_KES_DEBUG_STALL__WAIT                 0x1
-#define BF_BCH_DEBUG0_KES_DEBUG_STALL(v)                    (((v) << 9) & 0x200)
-#define BF_BCH_DEBUG0_KES_DEBUG_STALL_V(v)                  ((BV_BCH_DEBUG0_KES_DEBUG_STALL__##v << 9) & 0x200)
-#define BP_BCH_DEBUG0_BM_KES_TEST_BYPASS                    8
-#define BM_BCH_DEBUG0_BM_KES_TEST_BYPASS                    0x100
-#define BV_BCH_DEBUG0_BM_KES_TEST_BYPASS__NORMAL            0x0
-#define BV_BCH_DEBUG0_BM_KES_TEST_BYPASS__TEST_MODE         0x1
-#define BF_BCH_DEBUG0_BM_KES_TEST_BYPASS(v)                 (((v) << 8) & 0x100)
-#define BF_BCH_DEBUG0_BM_KES_TEST_BYPASS_V(v)               ((BV_BCH_DEBUG0_BM_KES_TEST_BYPASS__##v << 8) & 0x100)
-#define BP_BCH_DEBUG0_RSVD0                                 6
-#define BM_BCH_DEBUG0_RSVD0                                 0xc0
-#define BF_BCH_DEBUG0_RSVD0(v)                              (((v) << 6) & 0xc0)
-#define BP_BCH_DEBUG0_DEBUG_REG_SELECT                      0
-#define BM_BCH_DEBUG0_DEBUG_REG_SELECT                      0x3f
-#define BF_BCH_DEBUG0_DEBUG_REG_SELECT(v)                   (((v) << 0) & 0x3f)
-
-/**
- * Register: HW_BCH_DBGKESREAD
- * Address: 0x110
- * SCT: no
-*/
-#define HW_BCH_DBGKESREAD           (*(volatile unsigned long *)(REGS_BCH_BASE + 0x110))
-#define BP_BCH_DBGKESREAD_VALUES    0
-#define BM_BCH_DBGKESREAD_VALUES    0xffffffff
-#define BF_BCH_DBGKESREAD_VALUES(v) (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_BCH_DBGCSFEREAD
- * Address: 0x120
- * SCT: no
-*/
-#define HW_BCH_DBGCSFEREAD              (*(volatile unsigned long *)(REGS_BCH_BASE + 0x120))
-#define BP_BCH_DBGCSFEREAD_VALUES       0
-#define BM_BCH_DBGCSFEREAD_VALUES       0xffffffff
-#define BF_BCH_DBGCSFEREAD_VALUES(v)    (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_BCH_DBGSYNDGENREAD
- * Address: 0x130
- * SCT: no
-*/
-#define HW_BCH_DBGSYNDGENREAD           (*(volatile unsigned long *)(REGS_BCH_BASE + 0x130))
-#define BP_BCH_DBGSYNDGENREAD_VALUES    0
-#define BM_BCH_DBGSYNDGENREAD_VALUES    0xffffffff
-#define BF_BCH_DBGSYNDGENREAD_VALUES(v) (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_BCH_DBGAHBMREAD
- * Address: 0x140
- * SCT: no
-*/
-#define HW_BCH_DBGAHBMREAD              (*(volatile unsigned long *)(REGS_BCH_BASE + 0x140))
-#define BP_BCH_DBGAHBMREAD_VALUES       0
-#define BM_BCH_DBGAHBMREAD_VALUES       0xffffffff
-#define BF_BCH_DBGAHBMREAD_VALUES(v)    (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_BCH_BLOCKNAME
- * Address: 0x150
- * SCT: no
-*/
-#define HW_BCH_BLOCKNAME            (*(volatile unsigned long *)(REGS_BCH_BASE + 0x150))
-#define BP_BCH_BLOCKNAME_NAME       0
-#define BM_BCH_BLOCKNAME_NAME       0xffffffff
-#define BF_BCH_BLOCKNAME_NAME(v)    (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_BCH_VERSION
- * Address: 0x160
- * SCT: no
-*/
-#define HW_BCH_VERSION          (*(volatile unsigned long *)(REGS_BCH_BASE + 0x160))
-#define BP_BCH_VERSION_MAJOR    24
-#define BM_BCH_VERSION_MAJOR    0xff000000
-#define BF_BCH_VERSION_MAJOR(v) (((v) << 24) & 0xff000000)
-#define BP_BCH_VERSION_MINOR    16
-#define BM_BCH_VERSION_MINOR    0xff0000
-#define BF_BCH_VERSION_MINOR(v) (((v) << 16) & 0xff0000)
-#define BP_BCH_VERSION_STEP     0
-#define BM_BCH_VERSION_STEP     0xffff
-#define BF_BCH_VERSION_STEP(v)  (((v) << 0) & 0xffff)
-
-#endif /* __HEADERGEN__IMX233__BCH__H__ */
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-clkctrl.h b/firmware/target/arm/imx233/regs/imx233/regs-clkctrl.h
deleted file mode 100644
index e5c9ed37aa..0000000000
--- a/firmware/target/arm/imx233/regs/imx233/regs-clkctrl.h
+++ /dev/null
@@ -1,655 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: imx233:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__IMX233__CLKCTRL__H__
-#define __HEADERGEN__IMX233__CLKCTRL__H__
-
-#define REGS_CLKCTRL_BASE (0x80040000)
-
-#define REGS_CLKCTRL_VERSION "3.2.0"
-
-/**
- * Register: HW_CLKCTRL_PLLCTRL0
- * Address: 0
- * SCT: yes
-*/
-#define HW_CLKCTRL_PLLCTRL0                     (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x0 + 0x0))
-#define HW_CLKCTRL_PLLCTRL0_SET                 (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x0 + 0x4))
-#define HW_CLKCTRL_PLLCTRL0_CLR                 (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x0 + 0x8))
-#define HW_CLKCTRL_PLLCTRL0_TOG                 (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x0 + 0xc))
-#define BP_CLKCTRL_PLLCTRL0_RSRVD6              30
-#define BM_CLKCTRL_PLLCTRL0_RSRVD6              0xc0000000
-#define BF_CLKCTRL_PLLCTRL0_RSRVD6(v)           (((v) << 30) & 0xc0000000)
-#define BP_CLKCTRL_PLLCTRL0_LFR_SEL             28
-#define BM_CLKCTRL_PLLCTRL0_LFR_SEL             0x30000000
-#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__DEFAULT    0x0
-#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_2    0x1
-#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_05   0x2
-#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__UNDEFINED  0x3
-#define BF_CLKCTRL_PLLCTRL0_LFR_SEL(v)          (((v) << 28) & 0x30000000)
-#define BF_CLKCTRL_PLLCTRL0_LFR_SEL_V(v)        ((BV_CLKCTRL_PLLCTRL0_LFR_SEL__##v << 28) & 0x30000000)
-#define BP_CLKCTRL_PLLCTRL0_RSRVD5              26
-#define BM_CLKCTRL_PLLCTRL0_RSRVD5              0xc000000
-#define BF_CLKCTRL_PLLCTRL0_RSRVD5(v)           (((v) << 26) & 0xc000000)
-#define BP_CLKCTRL_PLLCTRL0_CP_SEL              24
-#define BM_CLKCTRL_PLLCTRL0_CP_SEL              0x3000000
-#define BV_CLKCTRL_PLLCTRL0_CP_SEL__DEFAULT     0x0
-#define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_2     0x1
-#define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_05    0x2
-#define BV_CLKCTRL_PLLCTRL0_CP_SEL__UNDEFINED   0x3
-#define BF_CLKCTRL_PLLCTRL0_CP_SEL(v)           (((v) << 24) & 0x3000000)
-#define BF_CLKCTRL_PLLCTRL0_CP_SEL_V(v)         ((BV_CLKCTRL_PLLCTRL0_CP_SEL__##v << 24) & 0x3000000)
-#define BP_CLKCTRL_PLLCTRL0_RSRVD4              22
-#define BM_CLKCTRL_PLLCTRL0_RSRVD4              0xc00000
-#define BF_CLKCTRL_PLLCTRL0_RSRVD4(v)           (((v) << 22) & 0xc00000)
-#define BP_CLKCTRL_PLLCTRL0_DIV_SEL             20
-#define BM_CLKCTRL_PLLCTRL0_DIV_SEL             0x300000
-#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__DEFAULT    0x0
-#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWER      0x1
-#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWEST     0x2
-#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__UNDEFINED  0x3
-#define BF_CLKCTRL_PLLCTRL0_DIV_SEL(v)          (((v) << 20) & 0x300000)
-#define BF_CLKCTRL_PLLCTRL0_DIV_SEL_V(v)        ((BV_CLKCTRL_PLLCTRL0_DIV_SEL__##v << 20) & 0x300000)
-#define BP_CLKCTRL_PLLCTRL0_RSRVD3              19
-#define BM_CLKCTRL_PLLCTRL0_RSRVD3              0x80000
-#define BF_CLKCTRL_PLLCTRL0_RSRVD3(v)           (((v) << 19) & 0x80000)
-#define BP_CLKCTRL_PLLCTRL0_EN_USB_CLKS         18
-#define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS         0x40000
-#define BF_CLKCTRL_PLLCTRL0_EN_USB_CLKS(v)      (((v) << 18) & 0x40000)
-#define BP_CLKCTRL_PLLCTRL0_RSRVD2              17
-#define BM_CLKCTRL_PLLCTRL0_RSRVD2              0x20000
-#define BF_CLKCTRL_PLLCTRL0_RSRVD2(v)           (((v) << 17) & 0x20000)
-#define BP_CLKCTRL_PLLCTRL0_POWER               16
-#define BM_CLKCTRL_PLLCTRL0_POWER               0x10000
-#define BF_CLKCTRL_PLLCTRL0_POWER(v)            (((v) << 16) & 0x10000)
-#define BP_CLKCTRL_PLLCTRL0_RSRVD1              0
-#define BM_CLKCTRL_PLLCTRL0_RSRVD1              0xffff
-#define BF_CLKCTRL_PLLCTRL0_RSRVD1(v)           (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_CLKCTRL_PLLCTRL1
- * Address: 0x10
- * SCT: no
-*/
-#define HW_CLKCTRL_PLLCTRL1                 (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x10))
-#define BP_CLKCTRL_PLLCTRL1_LOCK            31
-#define BM_CLKCTRL_PLLCTRL1_LOCK            0x80000000
-#define BF_CLKCTRL_PLLCTRL1_LOCK(v)         (((v) << 31) & 0x80000000)
-#define BP_CLKCTRL_PLLCTRL1_FORCE_LOCK      30
-#define BM_CLKCTRL_PLLCTRL1_FORCE_LOCK      0x40000000
-#define BF_CLKCTRL_PLLCTRL1_FORCE_LOCK(v)   (((v) << 30) & 0x40000000)
-#define BP_CLKCTRL_PLLCTRL1_RSRVD1          16
-#define BM_CLKCTRL_PLLCTRL1_RSRVD1          0x3fff0000
-#define BF_CLKCTRL_PLLCTRL1_RSRVD1(v)       (((v) << 16) & 0x3fff0000)
-#define BP_CLKCTRL_PLLCTRL1_LOCK_COUNT      0
-#define BM_CLKCTRL_PLLCTRL1_LOCK_COUNT      0xffff
-#define BF_CLKCTRL_PLLCTRL1_LOCK_COUNT(v)   (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_CLKCTRL_CPU
- * Address: 0x20
- * SCT: yes
-*/
-#define HW_CLKCTRL_CPU                      (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x20 + 0x0))
-#define HW_CLKCTRL_CPU_SET                  (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x20 + 0x4))
-#define HW_CLKCTRL_CPU_CLR                  (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x20 + 0x8))
-#define HW_CLKCTRL_CPU_TOG                  (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x20 + 0xc))
-#define BP_CLKCTRL_CPU_RSRVD5               30
-#define BM_CLKCTRL_CPU_RSRVD5               0xc0000000
-#define BF_CLKCTRL_CPU_RSRVD5(v)            (((v) << 30) & 0xc0000000)
-#define BP_CLKCTRL_CPU_BUSY_REF_XTAL        29
-#define BM_CLKCTRL_CPU_BUSY_REF_XTAL        0x20000000
-#define BF_CLKCTRL_CPU_BUSY_REF_XTAL(v)     (((v) << 29) & 0x20000000)
-#define BP_CLKCTRL_CPU_BUSY_REF_CPU         28
-#define BM_CLKCTRL_CPU_BUSY_REF_CPU         0x10000000
-#define BF_CLKCTRL_CPU_BUSY_REF_CPU(v)      (((v) << 28) & 0x10000000)
-#define BP_CLKCTRL_CPU_RSRVD4               27
-#define BM_CLKCTRL_CPU_RSRVD4               0x8000000
-#define BF_CLKCTRL_CPU_RSRVD4(v)            (((v) << 27) & 0x8000000)
-#define BP_CLKCTRL_CPU_DIV_XTAL_FRAC_EN     26
-#define BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN     0x4000000
-#define BF_CLKCTRL_CPU_DIV_XTAL_FRAC_EN(v)  (((v) << 26) & 0x4000000)
-#define BP_CLKCTRL_CPU_DIV_XTAL             16
-#define BM_CLKCTRL_CPU_DIV_XTAL             0x3ff0000
-#define BF_CLKCTRL_CPU_DIV_XTAL(v)          (((v) << 16) & 0x3ff0000)
-#define BP_CLKCTRL_CPU_RSRVD3               13
-#define BM_CLKCTRL_CPU_RSRVD3               0xe000
-#define BF_CLKCTRL_CPU_RSRVD3(v)            (((v) << 13) & 0xe000)
-#define BP_CLKCTRL_CPU_INTERRUPT_WAIT       12
-#define BM_CLKCTRL_CPU_INTERRUPT_WAIT       0x1000
-#define BF_CLKCTRL_CPU_INTERRUPT_WAIT(v)    (((v) << 12) & 0x1000)
-#define BP_CLKCTRL_CPU_RSRVD2               11
-#define BM_CLKCTRL_CPU_RSRVD2               0x800
-#define BF_CLKCTRL_CPU_RSRVD2(v)            (((v) << 11) & 0x800)
-#define BP_CLKCTRL_CPU_DIV_CPU_FRAC_EN      10
-#define BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN      0x400
-#define BF_CLKCTRL_CPU_DIV_CPU_FRAC_EN(v)   (((v) << 10) & 0x400)
-#define BP_CLKCTRL_CPU_RSRVD1               6
-#define BM_CLKCTRL_CPU_RSRVD1               0x3c0
-#define BF_CLKCTRL_CPU_RSRVD1(v)            (((v) << 6) & 0x3c0)
-#define BP_CLKCTRL_CPU_DIV_CPU              0
-#define BM_CLKCTRL_CPU_DIV_CPU              0x3f
-#define BF_CLKCTRL_CPU_DIV_CPU(v)           (((v) << 0) & 0x3f)
-
-/**
- * Register: HW_CLKCTRL_HBUS
- * Address: 0x30
- * SCT: yes
-*/
-#define HW_CLKCTRL_HBUS                             (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x30 + 0x0))
-#define HW_CLKCTRL_HBUS_SET                         (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x30 + 0x4))
-#define HW_CLKCTRL_HBUS_CLR                         (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x30 + 0x8))
-#define HW_CLKCTRL_HBUS_TOG                         (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x30 + 0xc))
-#define BP_CLKCTRL_HBUS_RSRVD4                      30
-#define BM_CLKCTRL_HBUS_RSRVD4                      0xc0000000
-#define BF_CLKCTRL_HBUS_RSRVD4(v)                   (((v) << 30) & 0xc0000000)
-#define BP_CLKCTRL_HBUS_BUSY                        29
-#define BM_CLKCTRL_HBUS_BUSY                        0x20000000
-#define BF_CLKCTRL_HBUS_BUSY(v)                     (((v) << 29) & 0x20000000)
-#define BP_CLKCTRL_HBUS_DCP_AS_ENABLE               28
-#define BM_CLKCTRL_HBUS_DCP_AS_ENABLE               0x10000000
-#define BF_CLKCTRL_HBUS_DCP_AS_ENABLE(v)            (((v) << 28) & 0x10000000)
-#define BP_CLKCTRL_HBUS_PXP_AS_ENABLE               27
-#define BM_CLKCTRL_HBUS_PXP_AS_ENABLE               0x8000000
-#define BF_CLKCTRL_HBUS_PXP_AS_ENABLE(v)            (((v) << 27) & 0x8000000)
-#define BP_CLKCTRL_HBUS_APBHDMA_AS_ENABLE           26
-#define BM_CLKCTRL_HBUS_APBHDMA_AS_ENABLE           0x4000000
-#define BF_CLKCTRL_HBUS_APBHDMA_AS_ENABLE(v)        (((v) << 26) & 0x4000000)
-#define BP_CLKCTRL_HBUS_APBXDMA_AS_ENABLE           25
-#define BM_CLKCTRL_HBUS_APBXDMA_AS_ENABLE           0x2000000
-#define BF_CLKCTRL_HBUS_APBXDMA_AS_ENABLE(v)        (((v) << 25) & 0x2000000)
-#define BP_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE       24
-#define BM_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE       0x1000000
-#define BF_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE(v)    (((v) << 24) & 0x1000000)
-#define BP_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE           23
-#define BM_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE           0x800000
-#define BF_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE(v)        (((v) << 23) & 0x800000)
-#define BP_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE          22
-#define BM_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE          0x400000
-#define BF_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE(v)       (((v) << 22) & 0x400000)
-#define BP_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE         21
-#define BM_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE         0x200000
-#define BF_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE(v)      (((v) << 21) & 0x200000)
-#define BP_CLKCTRL_HBUS_AUTO_SLOW_MODE              20
-#define BM_CLKCTRL_HBUS_AUTO_SLOW_MODE              0x100000
-#define BF_CLKCTRL_HBUS_AUTO_SLOW_MODE(v)           (((v) << 20) & 0x100000)
-#define BP_CLKCTRL_HBUS_RSRVD2                      19
-#define BM_CLKCTRL_HBUS_RSRVD2                      0x80000
-#define BF_CLKCTRL_HBUS_RSRVD2(v)                   (((v) << 19) & 0x80000)
-#define BP_CLKCTRL_HBUS_SLOW_DIV                    16
-#define BM_CLKCTRL_HBUS_SLOW_DIV                    0x70000
-#define BV_CLKCTRL_HBUS_SLOW_DIV__BY1               0x0
-#define BV_CLKCTRL_HBUS_SLOW_DIV__BY2               0x1
-#define BV_CLKCTRL_HBUS_SLOW_DIV__BY4               0x2
-#define BV_CLKCTRL_HBUS_SLOW_DIV__BY8               0x3
-#define BV_CLKCTRL_HBUS_SLOW_DIV__BY16              0x4
-#define BV_CLKCTRL_HBUS_SLOW_DIV__BY32              0x5
-#define BF_CLKCTRL_HBUS_SLOW_DIV(v)                 (((v) << 16) & 0x70000)
-#define BF_CLKCTRL_HBUS_SLOW_DIV_V(v)               ((BV_CLKCTRL_HBUS_SLOW_DIV__##v << 16) & 0x70000)
-#define BP_CLKCTRL_HBUS_RSRVD1                      6
-#define BM_CLKCTRL_HBUS_RSRVD1                      0xffc0
-#define BF_CLKCTRL_HBUS_RSRVD1(v)                   (((v) << 6) & 0xffc0)
-#define BP_CLKCTRL_HBUS_DIV_FRAC_EN                 5
-#define BM_CLKCTRL_HBUS_DIV_FRAC_EN                 0x20
-#define BF_CLKCTRL_HBUS_DIV_FRAC_EN(v)              (((v) << 5) & 0x20)
-#define BP_CLKCTRL_HBUS_DIV                         0
-#define BM_CLKCTRL_HBUS_DIV                         0x1f
-#define BF_CLKCTRL_HBUS_DIV(v)                      (((v) << 0) & 0x1f)
-
-/**
- * Register: HW_CLKCTRL_XBUS
- * Address: 0x40
- * SCT: no
-*/
-#define HW_CLKCTRL_XBUS                 (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x40))
-#define BP_CLKCTRL_XBUS_BUSY            31
-#define BM_CLKCTRL_XBUS_BUSY            0x80000000
-#define BF_CLKCTRL_XBUS_BUSY(v)         (((v) << 31) & 0x80000000)
-#define BP_CLKCTRL_XBUS_RSRVD1          11
-#define BM_CLKCTRL_XBUS_RSRVD1          0x7ffff800
-#define BF_CLKCTRL_XBUS_RSRVD1(v)       (((v) << 11) & 0x7ffff800)
-#define BP_CLKCTRL_XBUS_DIV_FRAC_EN     10
-#define BM_CLKCTRL_XBUS_DIV_FRAC_EN     0x400
-#define BF_CLKCTRL_XBUS_DIV_FRAC_EN(v)  (((v) << 10) & 0x400)
-#define BP_CLKCTRL_XBUS_DIV             0
-#define BM_CLKCTRL_XBUS_DIV             0x3ff
-#define BF_CLKCTRL_XBUS_DIV(v)          (((v) << 0) & 0x3ff)
-
-/**
- * Register: HW_CLKCTRL_XTAL
- * Address: 0x50
- * SCT: yes
-*/
-#define HW_CLKCTRL_XTAL                         (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x50 + 0x0))
-#define HW_CLKCTRL_XTAL_SET                     (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x50 + 0x4))
-#define HW_CLKCTRL_XTAL_CLR                     (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x50 + 0x8))
-#define HW_CLKCTRL_XTAL_TOG                     (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x50 + 0xc))
-#define BP_CLKCTRL_XTAL_UART_CLK_GATE           31
-#define BM_CLKCTRL_XTAL_UART_CLK_GATE           0x80000000
-#define BF_CLKCTRL_XTAL_UART_CLK_GATE(v)        (((v) << 31) & 0x80000000)
-#define BP_CLKCTRL_XTAL_FILT_CLK24M_GATE        30
-#define BM_CLKCTRL_XTAL_FILT_CLK24M_GATE        0x40000000
-#define BF_CLKCTRL_XTAL_FILT_CLK24M_GATE(v)     (((v) << 30) & 0x40000000)
-#define BP_CLKCTRL_XTAL_PWM_CLK24M_GATE         29
-#define BM_CLKCTRL_XTAL_PWM_CLK24M_GATE         0x20000000
-#define BF_CLKCTRL_XTAL_PWM_CLK24M_GATE(v)      (((v) << 29) & 0x20000000)
-#define BP_CLKCTRL_XTAL_DRI_CLK24M_GATE         28
-#define BM_CLKCTRL_XTAL_DRI_CLK24M_GATE         0x10000000
-#define BF_CLKCTRL_XTAL_DRI_CLK24M_GATE(v)      (((v) << 28) & 0x10000000)
-#define BP_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE      27
-#define BM_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE      0x8000000
-#define BF_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE(v)   (((v) << 27) & 0x8000000)
-#define BP_CLKCTRL_XTAL_TIMROT_CLK32K_GATE      26
-#define BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE      0x4000000
-#define BF_CLKCTRL_XTAL_TIMROT_CLK32K_GATE(v)   (((v) << 26) & 0x4000000)
-#define BP_CLKCTRL_XTAL_RSRVD1                  2
-#define BM_CLKCTRL_XTAL_RSRVD1                  0x3fffffc
-#define BF_CLKCTRL_XTAL_RSRVD1(v)               (((v) << 2) & 0x3fffffc)
-#define BP_CLKCTRL_XTAL_DIV_UART                0
-#define BM_CLKCTRL_XTAL_DIV_UART                0x3
-#define BF_CLKCTRL_XTAL_DIV_UART(v)             (((v) << 0) & 0x3)
-
-/**
- * Register: HW_CLKCTRL_PIX
- * Address: 0x60
- * SCT: no
-*/
-#define HW_CLKCTRL_PIX                  (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x60))
-#define BP_CLKCTRL_PIX_CLKGATE          31
-#define BM_CLKCTRL_PIX_CLKGATE          0x80000000
-#define BF_CLKCTRL_PIX_CLKGATE(v)       (((v) << 31) & 0x80000000)
-#define BP_CLKCTRL_PIX_RSRVD2           30
-#define BM_CLKCTRL_PIX_RSRVD2           0x40000000
-#define BF_CLKCTRL_PIX_RSRVD2(v)        (((v) << 30) & 0x40000000)
-#define BP_CLKCTRL_PIX_BUSY             29
-#define BM_CLKCTRL_PIX_BUSY             0x20000000
-#define BF_CLKCTRL_PIX_BUSY(v)          (((v) << 29) & 0x20000000)
-#define BP_CLKCTRL_PIX_RSRVD1           13
-#define BM_CLKCTRL_PIX_RSRVD1           0x1fffe000
-#define BF_CLKCTRL_PIX_RSRVD1(v)        (((v) << 13) & 0x1fffe000)
-#define BP_CLKCTRL_PIX_DIV_FRAC_EN      12
-#define BM_CLKCTRL_PIX_DIV_FRAC_EN      0x1000
-#define BF_CLKCTRL_PIX_DIV_FRAC_EN(v)   (((v) << 12) & 0x1000)
-#define BP_CLKCTRL_PIX_DIV              0
-#define BM_CLKCTRL_PIX_DIV              0xfff
-#define BF_CLKCTRL_PIX_DIV(v)           (((v) << 0) & 0xfff)
-
-/**
- * Register: HW_CLKCTRL_SSP
- * Address: 0x70
- * SCT: no
-*/
-#define HW_CLKCTRL_SSP                  (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x70))
-#define BP_CLKCTRL_SSP_CLKGATE          31
-#define BM_CLKCTRL_SSP_CLKGATE          0x80000000
-#define BF_CLKCTRL_SSP_CLKGATE(v)       (((v) << 31) & 0x80000000)
-#define BP_CLKCTRL_SSP_RSRVD2           30
-#define BM_CLKCTRL_SSP_RSRVD2           0x40000000
-#define BF_CLKCTRL_SSP_RSRVD2(v)        (((v) << 30) & 0x40000000)
-#define BP_CLKCTRL_SSP_BUSY             29
-#define BM_CLKCTRL_SSP_BUSY             0x20000000
-#define BF_CLKCTRL_SSP_BUSY(v)          (((v) << 29) & 0x20000000)
-#define BP_CLKCTRL_SSP_RSRVD1           10
-#define BM_CLKCTRL_SSP_RSRVD1           0x1ffffc00
-#define BF_CLKCTRL_SSP_RSRVD1(v)        (((v) << 10) & 0x1ffffc00)
-#define BP_CLKCTRL_SSP_DIV_FRAC_EN      9
-#define BM_CLKCTRL_SSP_DIV_FRAC_EN      0x200
-#define BF_CLKCTRL_SSP_DIV_FRAC_EN(v)   (((v) << 9) & 0x200)
-#define BP_CLKCTRL_SSP_DIV              0
-#define BM_CLKCTRL_SSP_DIV              0x1ff
-#define BF_CLKCTRL_SSP_DIV(v)           (((v) << 0) & 0x1ff)
-
-/**
- * Register: HW_CLKCTRL_GPMI
- * Address: 0x80
- * SCT: no
-*/
-#define HW_CLKCTRL_GPMI                 (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x80))
-#define BP_CLKCTRL_GPMI_CLKGATE         31
-#define BM_CLKCTRL_GPMI_CLKGATE         0x80000000
-#define BF_CLKCTRL_GPMI_CLKGATE(v)      (((v) << 31) & 0x80000000)
-#define BP_CLKCTRL_GPMI_RSRVD2          30
-#define BM_CLKCTRL_GPMI_RSRVD2          0x40000000
-#define BF_CLKCTRL_GPMI_RSRVD2(v)       (((v) << 30) & 0x40000000)
-#define BP_CLKCTRL_GPMI_BUSY            29
-#define BM_CLKCTRL_GPMI_BUSY            0x20000000
-#define BF_CLKCTRL_GPMI_BUSY(v)         (((v) << 29) & 0x20000000)
-#define BP_CLKCTRL_GPMI_RSRVD1          11
-#define BM_CLKCTRL_GPMI_RSRVD1          0x1ffff800
-#define BF_CLKCTRL_GPMI_RSRVD1(v)       (((v) << 11) & 0x1ffff800)
-#define BP_CLKCTRL_GPMI_DIV_FRAC_EN     10
-#define BM_CLKCTRL_GPMI_DIV_FRAC_EN     0x400
-#define BF_CLKCTRL_GPMI_DIV_FRAC_EN(v)  (((v) << 10) & 0x400)
-#define BP_CLKCTRL_GPMI_DIV             0
-#define BM_CLKCTRL_GPMI_DIV             0x3ff
-#define BF_CLKCTRL_GPMI_DIV(v)          (((v) << 0) & 0x3ff)
-
-/**
- * Register: HW_CLKCTRL_SPDIF
- * Address: 0x90
- * SCT: no
-*/
-#define HW_CLKCTRL_SPDIF            (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x90))
-#define BP_CLKCTRL_SPDIF_CLKGATE    31
-#define BM_CLKCTRL_SPDIF_CLKGATE    0x80000000
-#define BF_CLKCTRL_SPDIF_CLKGATE(v) (((v) << 31) & 0x80000000)
-#define BP_CLKCTRL_SPDIF_RSRVD      0
-#define BM_CLKCTRL_SPDIF_RSRVD      0x7fffffff
-#define BF_CLKCTRL_SPDIF_RSRVD(v)   (((v) << 0) & 0x7fffffff)
-
-/**
- * Register: HW_CLKCTRL_EMI
- * Address: 0xa0
- * SCT: no
-*/
-#define HW_CLKCTRL_EMI                      (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xa0))
-#define BP_CLKCTRL_EMI_CLKGATE              31
-#define BM_CLKCTRL_EMI_CLKGATE              0x80000000
-#define BF_CLKCTRL_EMI_CLKGATE(v)           (((v) << 31) & 0x80000000)
-#define BP_CLKCTRL_EMI_SYNC_MODE_EN         30
-#define BM_CLKCTRL_EMI_SYNC_MODE_EN         0x40000000
-#define BF_CLKCTRL_EMI_SYNC_MODE_EN(v)      (((v) << 30) & 0x40000000)
-#define BP_CLKCTRL_EMI_BUSY_REF_XTAL        29
-#define BM_CLKCTRL_EMI_BUSY_REF_XTAL        0x20000000
-#define BF_CLKCTRL_EMI_BUSY_REF_XTAL(v)     (((v) << 29) & 0x20000000)
-#define BP_CLKCTRL_EMI_BUSY_REF_EMI         28
-#define BM_CLKCTRL_EMI_BUSY_REF_EMI         0x10000000
-#define BF_CLKCTRL_EMI_BUSY_REF_EMI(v)      (((v) << 28) & 0x10000000)
-#define BP_CLKCTRL_EMI_BUSY_REF_CPU         27
-#define BM_CLKCTRL_EMI_BUSY_REF_CPU         0x8000000
-#define BF_CLKCTRL_EMI_BUSY_REF_CPU(v)      (((v) << 27) & 0x8000000)
-#define BP_CLKCTRL_EMI_BUSY_SYNC_MODE       26
-#define BM_CLKCTRL_EMI_BUSY_SYNC_MODE       0x4000000
-#define BF_CLKCTRL_EMI_BUSY_SYNC_MODE(v)    (((v) << 26) & 0x4000000)
-#define BP_CLKCTRL_EMI_RSRVD3               18
-#define BM_CLKCTRL_EMI_RSRVD3               0x3fc0000
-#define BF_CLKCTRL_EMI_RSRVD3(v)            (((v) << 18) & 0x3fc0000)
-#define BP_CLKCTRL_EMI_BUSY_DCC_RESYNC      17
-#define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC      0x20000
-#define BF_CLKCTRL_EMI_BUSY_DCC_RESYNC(v)   (((v) << 17) & 0x20000)
-#define BP_CLKCTRL_EMI_DCC_RESYNC_ENABLE    16
-#define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE    0x10000
-#define BF_CLKCTRL_EMI_DCC_RESYNC_ENABLE(v) (((v) << 16) & 0x10000)
-#define BP_CLKCTRL_EMI_RSRVD2               12
-#define BM_CLKCTRL_EMI_RSRVD2               0xf000
-#define BF_CLKCTRL_EMI_RSRVD2(v)            (((v) << 12) & 0xf000)
-#define BP_CLKCTRL_EMI_DIV_XTAL             8
-#define BM_CLKCTRL_EMI_DIV_XTAL             0xf00
-#define BF_CLKCTRL_EMI_DIV_XTAL(v)          (((v) << 8) & 0xf00)
-#define BP_CLKCTRL_EMI_RSRVD1               6
-#define BM_CLKCTRL_EMI_RSRVD1               0xc0
-#define BF_CLKCTRL_EMI_RSRVD1(v)            (((v) << 6) & 0xc0)
-#define BP_CLKCTRL_EMI_DIV_EMI              0
-#define BM_CLKCTRL_EMI_DIV_EMI              0x3f
-#define BF_CLKCTRL_EMI_DIV_EMI(v)           (((v) << 0) & 0x3f)
-
-/**
- * Register: HW_CLKCTRL_IR
- * Address: 0xb0
- * SCT: no
-*/
-#define HW_CLKCTRL_IR               (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xb0))
-#define BP_CLKCTRL_IR_CLKGATE       31
-#define BM_CLKCTRL_IR_CLKGATE       0x80000000
-#define BF_CLKCTRL_IR_CLKGATE(v)    (((v) << 31) & 0x80000000)
-#define BP_CLKCTRL_IR_RSRVD3        30
-#define BM_CLKCTRL_IR_RSRVD3        0x40000000
-#define BF_CLKCTRL_IR_RSRVD3(v)     (((v) << 30) & 0x40000000)
-#define BP_CLKCTRL_IR_AUTO_DIV      29
-#define BM_CLKCTRL_IR_AUTO_DIV      0x20000000
-#define BF_CLKCTRL_IR_AUTO_DIV(v)   (((v) << 29) & 0x20000000)
-#define BP_CLKCTRL_IR_IR_BUSY       28
-#define BM_CLKCTRL_IR_IR_BUSY       0x10000000
-#define BF_CLKCTRL_IR_IR_BUSY(v)    (((v) << 28) & 0x10000000)
-#define BP_CLKCTRL_IR_IROV_BUSY     27
-#define BM_CLKCTRL_IR_IROV_BUSY     0x8000000
-#define BF_CLKCTRL_IR_IROV_BUSY(v)  (((v) << 27) & 0x8000000)
-#define BP_CLKCTRL_IR_RSRVD2        25
-#define BM_CLKCTRL_IR_RSRVD2        0x6000000
-#define BF_CLKCTRL_IR_RSRVD2(v)     (((v) << 25) & 0x6000000)
-#define BP_CLKCTRL_IR_IROV_DIV      16
-#define BM_CLKCTRL_IR_IROV_DIV      0x1ff0000
-#define BF_CLKCTRL_IR_IROV_DIV(v)   (((v) << 16) & 0x1ff0000)
-#define BP_CLKCTRL_IR_RSRVD1        10
-#define BM_CLKCTRL_IR_RSRVD1        0xfc00
-#define BF_CLKCTRL_IR_RSRVD1(v)     (((v) << 10) & 0xfc00)
-#define BP_CLKCTRL_IR_IR_DIV        0
-#define BM_CLKCTRL_IR_IR_DIV        0x3ff
-#define BF_CLKCTRL_IR_IR_DIV(v)     (((v) << 0) & 0x3ff)
-
-/**
- * Register: HW_CLKCTRL_SAIF
- * Address: 0xc0
- * SCT: no
-*/
-#define HW_CLKCTRL_SAIF                 (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xc0))
-#define BP_CLKCTRL_SAIF_CLKGATE         31
-#define BM_CLKCTRL_SAIF_CLKGATE         0x80000000
-#define BF_CLKCTRL_SAIF_CLKGATE(v)      (((v) << 31) & 0x80000000)
-#define BP_CLKCTRL_SAIF_RSRVD2          30
-#define BM_CLKCTRL_SAIF_RSRVD2          0x40000000
-#define BF_CLKCTRL_SAIF_RSRVD2(v)       (((v) << 30) & 0x40000000)
-#define BP_CLKCTRL_SAIF_BUSY            29
-#define BM_CLKCTRL_SAIF_BUSY            0x20000000
-#define BF_CLKCTRL_SAIF_BUSY(v)         (((v) << 29) & 0x20000000)
-#define BP_CLKCTRL_SAIF_RSRVD1          17
-#define BM_CLKCTRL_SAIF_RSRVD1          0x1ffe0000
-#define BF_CLKCTRL_SAIF_RSRVD1(v)       (((v) << 17) & 0x1ffe0000)
-#define BP_CLKCTRL_SAIF_DIV_FRAC_EN     16
-#define BM_CLKCTRL_SAIF_DIV_FRAC_EN     0x10000
-#define BF_CLKCTRL_SAIF_DIV_FRAC_EN(v)  (((v) << 16) & 0x10000)
-#define BP_CLKCTRL_SAIF_DIV             0
-#define BM_CLKCTRL_SAIF_DIV             0xffff
-#define BF_CLKCTRL_SAIF_DIV(v)          (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_CLKCTRL_TV
- * Address: 0xd0
- * SCT: no
-*/
-#define HW_CLKCTRL_TV                       (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xd0))
-#define BP_CLKCTRL_TV_CLK_TV108M_GATE       31
-#define BM_CLKCTRL_TV_CLK_TV108M_GATE       0x80000000
-#define BF_CLKCTRL_TV_CLK_TV108M_GATE(v)    (((v) << 31) & 0x80000000)
-#define BP_CLKCTRL_TV_CLK_TV_GATE           30
-#define BM_CLKCTRL_TV_CLK_TV_GATE           0x40000000
-#define BF_CLKCTRL_TV_CLK_TV_GATE(v)        (((v) << 30) & 0x40000000)
-#define BP_CLKCTRL_TV_RSRVD                 0
-#define BM_CLKCTRL_TV_RSRVD                 0x3fffffff
-#define BF_CLKCTRL_TV_RSRVD(v)              (((v) << 0) & 0x3fffffff)
-
-/**
- * Register: HW_CLKCTRL_ETM
- * Address: 0xe0
- * SCT: no
-*/
-#define HW_CLKCTRL_ETM                  (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xe0))
-#define BP_CLKCTRL_ETM_CLKGATE          31
-#define BM_CLKCTRL_ETM_CLKGATE          0x80000000
-#define BF_CLKCTRL_ETM_CLKGATE(v)       (((v) << 31) & 0x80000000)
-#define BP_CLKCTRL_ETM_RSRVD2           30
-#define BM_CLKCTRL_ETM_RSRVD2           0x40000000
-#define BF_CLKCTRL_ETM_RSRVD2(v)        (((v) << 30) & 0x40000000)
-#define BP_CLKCTRL_ETM_BUSY             29
-#define BM_CLKCTRL_ETM_BUSY             0x20000000
-#define BF_CLKCTRL_ETM_BUSY(v)          (((v) << 29) & 0x20000000)
-#define BP_CLKCTRL_ETM_RSRVD1           7
-#define BM_CLKCTRL_ETM_RSRVD1           0x1fffff80
-#define BF_CLKCTRL_ETM_RSRVD1(v)        (((v) << 7) & 0x1fffff80)
-#define BP_CLKCTRL_ETM_DIV_FRAC_EN      6
-#define BM_CLKCTRL_ETM_DIV_FRAC_EN      0x40
-#define BF_CLKCTRL_ETM_DIV_FRAC_EN(v)   (((v) << 6) & 0x40)
-#define BP_CLKCTRL_ETM_DIV              0
-#define BM_CLKCTRL_ETM_DIV              0x3f
-#define BF_CLKCTRL_ETM_DIV(v)           (((v) << 0) & 0x3f)
-
-/**
- * Register: HW_CLKCTRL_FRAC
- * Address: 0xf0
- * SCT: yes
-*/
-#define HW_CLKCTRL_FRAC                 (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xf0 + 0x0))
-#define HW_CLKCTRL_FRAC_SET             (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xf0 + 0x4))
-#define HW_CLKCTRL_FRAC_CLR             (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xf0 + 0x8))
-#define HW_CLKCTRL_FRAC_TOG             (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xf0 + 0xc))
-#define BP_CLKCTRL_FRAC_CLKGATEIO       31
-#define BM_CLKCTRL_FRAC_CLKGATEIO       0x80000000
-#define BF_CLKCTRL_FRAC_CLKGATEIO(v)    (((v) << 31) & 0x80000000)
-#define BP_CLKCTRL_FRAC_IO_STABLE       30
-#define BM_CLKCTRL_FRAC_IO_STABLE       0x40000000
-#define BF_CLKCTRL_FRAC_IO_STABLE(v)    (((v) << 30) & 0x40000000)
-#define BP_CLKCTRL_FRAC_IOFRAC          24
-#define BM_CLKCTRL_FRAC_IOFRAC          0x3f000000
-#define BF_CLKCTRL_FRAC_IOFRAC(v)       (((v) << 24) & 0x3f000000)
-#define BP_CLKCTRL_FRAC_CLKGATEPIX      23
-#define BM_CLKCTRL_FRAC_CLKGATEPIX      0x800000
-#define BF_CLKCTRL_FRAC_CLKGATEPIX(v)   (((v) << 23) & 0x800000)
-#define BP_CLKCTRL_FRAC_PIX_STABLE      22
-#define BM_CLKCTRL_FRAC_PIX_STABLE      0x400000
-#define BF_CLKCTRL_FRAC_PIX_STABLE(v)   (((v) << 22) & 0x400000)
-#define BP_CLKCTRL_FRAC_PIXFRAC         16
-#define BM_CLKCTRL_FRAC_PIXFRAC         0x3f0000
-#define BF_CLKCTRL_FRAC_PIXFRAC(v)      (((v) << 16) & 0x3f0000)
-#define BP_CLKCTRL_FRAC_CLKGATEEMI      15
-#define BM_CLKCTRL_FRAC_CLKGATEEMI      0x8000
-#define BF_CLKCTRL_FRAC_CLKGATEEMI(v)   (((v) << 15) & 0x8000)
-#define BP_CLKCTRL_FRAC_EMI_STABLE      14
-#define BM_CLKCTRL_FRAC_EMI_STABLE      0x4000
-#define BF_CLKCTRL_FRAC_EMI_STABLE(v)   (((v) << 14) & 0x4000)
-#define BP_CLKCTRL_FRAC_EMIFRAC         8
-#define BM_CLKCTRL_FRAC_EMIFRAC         0x3f00
-#define BF_CLKCTRL_FRAC_EMIFRAC(v)      (((v) << 8) & 0x3f00)
-#define BP_CLKCTRL_FRAC_CLKGATECPU      7
-#define BM_CLKCTRL_FRAC_CLKGATECPU      0x80
-#define BF_CLKCTRL_FRAC_CLKGATECPU(v)   (((v) << 7) & 0x80)
-#define BP_CLKCTRL_FRAC_CPU_STABLE      6
-#define BM_CLKCTRL_FRAC_CPU_STABLE      0x40
-#define BF_CLKCTRL_FRAC_CPU_STABLE(v)   (((v) << 6) & 0x40)
-#define BP_CLKCTRL_FRAC_CPUFRAC         0
-#define BM_CLKCTRL_FRAC_CPUFRAC         0x3f
-#define BF_CLKCTRL_FRAC_CPUFRAC(v)      (((v) << 0) & 0x3f)
-
-/**
- * Register: HW_CLKCTRL_FRAC1
- * Address: 0x100
- * SCT: yes
-*/
-#define HW_CLKCTRL_FRAC1                (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x100 + 0x0))
-#define HW_CLKCTRL_FRAC1_SET            (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x100 + 0x4))
-#define HW_CLKCTRL_FRAC1_CLR            (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x100 + 0x8))
-#define HW_CLKCTRL_FRAC1_TOG            (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x100 + 0xc))
-#define BP_CLKCTRL_FRAC1_CLKGATEVID     31
-#define BM_CLKCTRL_FRAC1_CLKGATEVID     0x80000000
-#define BF_CLKCTRL_FRAC1_CLKGATEVID(v)  (((v) << 31) & 0x80000000)
-#define BP_CLKCTRL_FRAC1_VID_STABLE     30
-#define BM_CLKCTRL_FRAC1_VID_STABLE     0x40000000
-#define BF_CLKCTRL_FRAC1_VID_STABLE(v)  (((v) << 30) & 0x40000000)
-#define BP_CLKCTRL_FRAC1_RSRVD1         0
-#define BM_CLKCTRL_FRAC1_RSRVD1         0x3fffffff
-#define BF_CLKCTRL_FRAC1_RSRVD1(v)      (((v) << 0) & 0x3fffffff)
-
-/**
- * Register: HW_CLKCTRL_CLKSEQ
- * Address: 0x110
- * SCT: yes
-*/
-#define HW_CLKCTRL_CLKSEQ                   (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x110 + 0x0))
-#define HW_CLKCTRL_CLKSEQ_SET               (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x110 + 0x4))
-#define HW_CLKCTRL_CLKSEQ_CLR               (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x110 + 0x8))
-#define HW_CLKCTRL_CLKSEQ_TOG               (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x110 + 0xc))
-#define BP_CLKCTRL_CLKSEQ_RSRVD1            9
-#define BM_CLKCTRL_CLKSEQ_RSRVD1            0xfffffe00
-#define BF_CLKCTRL_CLKSEQ_RSRVD1(v)         (((v) << 9) & 0xfffffe00)
-#define BP_CLKCTRL_CLKSEQ_BYPASS_ETM        8
-#define BM_CLKCTRL_CLKSEQ_BYPASS_ETM        0x100
-#define BF_CLKCTRL_CLKSEQ_BYPASS_ETM(v)     (((v) << 8) & 0x100)
-#define BP_CLKCTRL_CLKSEQ_BYPASS_CPU        7
-#define BM_CLKCTRL_CLKSEQ_BYPASS_CPU        0x80
-#define BF_CLKCTRL_CLKSEQ_BYPASS_CPU(v)     (((v) << 7) & 0x80)
-#define BP_CLKCTRL_CLKSEQ_BYPASS_EMI        6
-#define BM_CLKCTRL_CLKSEQ_BYPASS_EMI        0x40
-#define BF_CLKCTRL_CLKSEQ_BYPASS_EMI(v)     (((v) << 6) & 0x40)
-#define BP_CLKCTRL_CLKSEQ_BYPASS_SSP        5
-#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP        0x20
-#define BF_CLKCTRL_CLKSEQ_BYPASS_SSP(v)     (((v) << 5) & 0x20)
-#define BP_CLKCTRL_CLKSEQ_BYPASS_GPMI       4
-#define BM_CLKCTRL_CLKSEQ_BYPASS_GPMI       0x10
-#define BF_CLKCTRL_CLKSEQ_BYPASS_GPMI(v)    (((v) << 4) & 0x10)
-#define BP_CLKCTRL_CLKSEQ_BYPASS_IR         3
-#define BM_CLKCTRL_CLKSEQ_BYPASS_IR         0x8
-#define BF_CLKCTRL_CLKSEQ_BYPASS_IR(v)      (((v) << 3) & 0x8)
-#define BP_CLKCTRL_CLKSEQ_RSRVD0            2
-#define BM_CLKCTRL_CLKSEQ_RSRVD0            0x4
-#define BF_CLKCTRL_CLKSEQ_RSRVD0(v)         (((v) << 2) & 0x4)
-#define BP_CLKCTRL_CLKSEQ_BYPASS_PIX        1
-#define BM_CLKCTRL_CLKSEQ_BYPASS_PIX        0x2
-#define BF_CLKCTRL_CLKSEQ_BYPASS_PIX(v)     (((v) << 1) & 0x2)
-#define BP_CLKCTRL_CLKSEQ_BYPASS_SAIF       0
-#define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF       0x1
-#define BF_CLKCTRL_CLKSEQ_BYPASS_SAIF(v)    (((v) << 0) & 0x1)
-
-/**
- * Register: HW_CLKCTRL_RESET
- * Address: 0x120
- * SCT: no
-*/
-#define HW_CLKCTRL_RESET            (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x120))
-#define BP_CLKCTRL_RESET_RSRVD      2
-#define BM_CLKCTRL_RESET_RSRVD      0xfffffffc
-#define BF_CLKCTRL_RESET_RSRVD(v)   (((v) << 2) & 0xfffffffc)
-#define BP_CLKCTRL_RESET_CHIP       1
-#define BM_CLKCTRL_RESET_CHIP       0x2
-#define BF_CLKCTRL_RESET_CHIP(v)    (((v) << 1) & 0x2)
-#define BP_CLKCTRL_RESET_DIG        0
-#define BM_CLKCTRL_RESET_DIG        0x1
-#define BF_CLKCTRL_RESET_DIG(v)     (((v) << 0) & 0x1)
-
-/**
- * Register: HW_CLKCTRL_STATUS
- * Address: 0x130
- * SCT: no
-*/
-#define HW_CLKCTRL_STATUS               (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x130))
-#define BP_CLKCTRL_STATUS_CPU_LIMIT     30
-#define BM_CLKCTRL_STATUS_CPU_LIMIT     0xc0000000
-#define BF_CLKCTRL_STATUS_CPU_LIMIT(v)  (((v) << 30) & 0xc0000000)
-#define BP_CLKCTRL_STATUS_RSRVD         0
-#define BM_CLKCTRL_STATUS_RSRVD         0x3fffffff
-#define BF_CLKCTRL_STATUS_RSRVD(v)      (((v) << 0) & 0x3fffffff)
-
-/**
- * Register: HW_CLKCTRL_VERSION
- * Address: 0x140
- * SCT: no
-*/
-#define HW_CLKCTRL_VERSION          (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x140))
-#define BP_CLKCTRL_VERSION_MAJOR    24
-#define BM_CLKCTRL_VERSION_MAJOR    0xff000000
-#define BF_CLKCTRL_VERSION_MAJOR(v) (((v) << 24) & 0xff000000)
-#define BP_CLKCTRL_VERSION_MINOR    16
-#define BM_CLKCTRL_VERSION_MINOR    0xff0000
-#define BF_CLKCTRL_VERSION_MINOR(v) (((v) << 16) & 0xff0000)
-#define BP_CLKCTRL_VERSION_STEP     0
-#define BM_CLKCTRL_VERSION_STEP     0xffff
-#define BF_CLKCTRL_VERSION_STEP(v)  (((v) << 0) & 0xffff)
-
-#endif /* __HEADERGEN__IMX233__CLKCTRL__H__ */
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-dcp.h b/firmware/target/arm/imx233/regs/imx233/regs-dcp.h
deleted file mode 100644
index c60afea204..0000000000
--- a/firmware/target/arm/imx233/regs/imx233/regs-dcp.h
+++ /dev/null
@@ -1,851 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: imx233:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__IMX233__DCP__H__
-#define __HEADERGEN__IMX233__DCP__H__
-
-#define REGS_DCP_BASE (0x80028000)
-
-#define REGS_DCP_VERSION "3.2.0"
-
-/**
- * Register: HW_DCP_CTRL
- * Address: 0
- * SCT: yes
-*/
-#define HW_DCP_CTRL                                 (*(volatile unsigned long *)(REGS_DCP_BASE + 0x0 + 0x0))
-#define HW_DCP_CTRL_SET                             (*(volatile unsigned long *)(REGS_DCP_BASE + 0x0 + 0x4))
-#define HW_DCP_CTRL_CLR                             (*(volatile unsigned long *)(REGS_DCP_BASE + 0x0 + 0x8))
-#define HW_DCP_CTRL_TOG                             (*(volatile unsigned long *)(REGS_DCP_BASE + 0x0 + 0xc))
-#define BP_DCP_CTRL_SFTRST                          31
-#define BM_DCP_CTRL_SFTRST                          0x80000000
-#define BF_DCP_CTRL_SFTRST(v)                       (((v) << 31) & 0x80000000)
-#define BP_DCP_CTRL_CLKGATE                         30
-#define BM_DCP_CTRL_CLKGATE                         0x40000000
-#define BF_DCP_CTRL_CLKGATE(v)                      (((v) << 30) & 0x40000000)
-#define BP_DCP_CTRL_PRESENT_CRYPTO                  29
-#define BM_DCP_CTRL_PRESENT_CRYPTO                  0x20000000
-#define BV_DCP_CTRL_PRESENT_CRYPTO__Present         0x1
-#define BV_DCP_CTRL_PRESENT_CRYPTO__Absent          0x0
-#define BF_DCP_CTRL_PRESENT_CRYPTO(v)               (((v) << 29) & 0x20000000)
-#define BF_DCP_CTRL_PRESENT_CRYPTO_V(v)             ((BV_DCP_CTRL_PRESENT_CRYPTO__##v << 29) & 0x20000000)
-#define BP_DCP_CTRL_PRESENT_CSC                     28
-#define BM_DCP_CTRL_PRESENT_CSC                     0x10000000
-#define BV_DCP_CTRL_PRESENT_CSC__Present            0x1
-#define BV_DCP_CTRL_PRESENT_CSC__Absent             0x0
-#define BF_DCP_CTRL_PRESENT_CSC(v)                  (((v) << 28) & 0x10000000)
-#define BF_DCP_CTRL_PRESENT_CSC_V(v)                ((BV_DCP_CTRL_PRESENT_CSC__##v << 28) & 0x10000000)
-#define BP_DCP_CTRL_RSVD1                           24
-#define BM_DCP_CTRL_RSVD1                           0xf000000
-#define BF_DCP_CTRL_RSVD1(v)                        (((v) << 24) & 0xf000000)
-#define BP_DCP_CTRL_GATHER_RESIDUAL_WRITES          23
-#define BM_DCP_CTRL_GATHER_RESIDUAL_WRITES          0x800000
-#define BF_DCP_CTRL_GATHER_RESIDUAL_WRITES(v)       (((v) << 23) & 0x800000)
-#define BP_DCP_CTRL_ENABLE_CONTEXT_CACHING          22
-#define BM_DCP_CTRL_ENABLE_CONTEXT_CACHING          0x400000
-#define BF_DCP_CTRL_ENABLE_CONTEXT_CACHING(v)       (((v) << 22) & 0x400000)
-#define BP_DCP_CTRL_ENABLE_CONTEXT_SWITCHING        21
-#define BM_DCP_CTRL_ENABLE_CONTEXT_SWITCHING        0x200000
-#define BF_DCP_CTRL_ENABLE_CONTEXT_SWITCHING(v)     (((v) << 21) & 0x200000)
-#define BP_DCP_CTRL_RSVD0                           9
-#define BM_DCP_CTRL_RSVD0                           0x1ffe00
-#define BF_DCP_CTRL_RSVD0(v)                        (((v) << 9) & 0x1ffe00)
-#define BP_DCP_CTRL_CSC_INTERRUPT_ENABLE            8
-#define BM_DCP_CTRL_CSC_INTERRUPT_ENABLE            0x100
-#define BF_DCP_CTRL_CSC_INTERRUPT_ENABLE(v)         (((v) << 8) & 0x100)
-#define BP_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE        0
-#define BM_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE        0xff
-#define BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__CH0   0x1
-#define BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__CH1   0x2
-#define BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__CH2   0x4
-#define BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__CH3   0x8
-#define BF_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE(v)     (((v) << 0) & 0xff)
-#define BF_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_V(v)   ((BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__##v << 0) & 0xff)
-
-/**
- * Register: HW_DCP_STAT
- * Address: 0x10
- * SCT: yes
-*/
-#define HW_DCP_STAT                     (*(volatile unsigned long *)(REGS_DCP_BASE + 0x10 + 0x0))
-#define HW_DCP_STAT_SET                 (*(volatile unsigned long *)(REGS_DCP_BASE + 0x10 + 0x4))
-#define HW_DCP_STAT_CLR                 (*(volatile unsigned long *)(REGS_DCP_BASE + 0x10 + 0x8))
-#define HW_DCP_STAT_TOG                 (*(volatile unsigned long *)(REGS_DCP_BASE + 0x10 + 0xc))
-#define BP_DCP_STAT_RSVD2               29
-#define BM_DCP_STAT_RSVD2               0xe0000000
-#define BF_DCP_STAT_RSVD2(v)            (((v) << 29) & 0xe0000000)
-#define BP_DCP_STAT_OTP_KEY_READY       28
-#define BM_DCP_STAT_OTP_KEY_READY       0x10000000
-#define BF_DCP_STAT_OTP_KEY_READY(v)    (((v) << 28) & 0x10000000)
-#define BP_DCP_STAT_CUR_CHANNEL         24
-#define BM_DCP_STAT_CUR_CHANNEL         0xf000000
-#define BV_DCP_STAT_CUR_CHANNEL__None   0x0
-#define BV_DCP_STAT_CUR_CHANNEL__CH0    0x1
-#define BV_DCP_STAT_CUR_CHANNEL__CH1    0x2
-#define BV_DCP_STAT_CUR_CHANNEL__CH2    0x3
-#define BV_DCP_STAT_CUR_CHANNEL__CH3    0x4
-#define BV_DCP_STAT_CUR_CHANNEL__CSC    0x8
-#define BF_DCP_STAT_CUR_CHANNEL(v)      (((v) << 24) & 0xf000000)
-#define BF_DCP_STAT_CUR_CHANNEL_V(v)    ((BV_DCP_STAT_CUR_CHANNEL__##v << 24) & 0xf000000)
-#define BP_DCP_STAT_READY_CHANNELS      16
-#define BM_DCP_STAT_READY_CHANNELS      0xff0000
-#define BV_DCP_STAT_READY_CHANNELS__CH0 0x1
-#define BV_DCP_STAT_READY_CHANNELS__CH1 0x2
-#define BV_DCP_STAT_READY_CHANNELS__CH2 0x4
-#define BV_DCP_STAT_READY_CHANNELS__CH3 0x8
-#define BF_DCP_STAT_READY_CHANNELS(v)   (((v) << 16) & 0xff0000)
-#define BF_DCP_STAT_READY_CHANNELS_V(v) ((BV_DCP_STAT_READY_CHANNELS__##v << 16) & 0xff0000)
-#define BP_DCP_STAT_RSVD1               9
-#define BM_DCP_STAT_RSVD1               0xfe00
-#define BF_DCP_STAT_RSVD1(v)            (((v) << 9) & 0xfe00)
-#define BP_DCP_STAT_CSCIRQ              8
-#define BM_DCP_STAT_CSCIRQ              0x100
-#define BF_DCP_STAT_CSCIRQ(v)           (((v) << 8) & 0x100)
-#define BP_DCP_STAT_RSVD0               4
-#define BM_DCP_STAT_RSVD0               0xf0
-#define BF_DCP_STAT_RSVD0(v)            (((v) << 4) & 0xf0)
-#define BP_DCP_STAT_IRQ                 0
-#define BM_DCP_STAT_IRQ                 0xf
-#define BF_DCP_STAT_IRQ(v)              (((v) << 0) & 0xf)
-
-/**
- * Register: HW_DCP_CHANNELCTRL
- * Address: 0x20
- * SCT: yes
-*/
-#define HW_DCP_CHANNELCTRL                              (*(volatile unsigned long *)(REGS_DCP_BASE + 0x20 + 0x0))
-#define HW_DCP_CHANNELCTRL_SET                          (*(volatile unsigned long *)(REGS_DCP_BASE + 0x20 + 0x4))
-#define HW_DCP_CHANNELCTRL_CLR                          (*(volatile unsigned long *)(REGS_DCP_BASE + 0x20 + 0x8))
-#define HW_DCP_CHANNELCTRL_TOG                          (*(volatile unsigned long *)(REGS_DCP_BASE + 0x20 + 0xc))
-#define BP_DCP_CHANNELCTRL_RSVD                         19
-#define BM_DCP_CHANNELCTRL_RSVD                         0xfff80000
-#define BF_DCP_CHANNELCTRL_RSVD(v)                      (((v) << 19) & 0xfff80000)
-#define BP_DCP_CHANNELCTRL_CSC_PRIORITY                 17
-#define BM_DCP_CHANNELCTRL_CSC_PRIORITY                 0x60000
-#define BV_DCP_CHANNELCTRL_CSC_PRIORITY__HIGH           0x3
-#define BV_DCP_CHANNELCTRL_CSC_PRIORITY__MED            0x2
-#define BV_DCP_CHANNELCTRL_CSC_PRIORITY__LOW            0x1
-#define BV_DCP_CHANNELCTRL_CSC_PRIORITY__BACKGROUND     0x0
-#define BF_DCP_CHANNELCTRL_CSC_PRIORITY(v)              (((v) << 17) & 0x60000)
-#define BF_DCP_CHANNELCTRL_CSC_PRIORITY_V(v)            ((BV_DCP_CHANNELCTRL_CSC_PRIORITY__##v << 17) & 0x60000)
-#define BP_DCP_CHANNELCTRL_CH0_IRQ_MERGED               16
-#define BM_DCP_CHANNELCTRL_CH0_IRQ_MERGED               0x10000
-#define BF_DCP_CHANNELCTRL_CH0_IRQ_MERGED(v)            (((v) << 16) & 0x10000)
-#define BP_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL        8
-#define BM_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL        0xff00
-#define BV_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL__CH0   0x1
-#define BV_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL__CH1   0x2
-#define BV_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL__CH2   0x4
-#define BV_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL__CH3   0x8
-#define BF_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL(v)     (((v) << 8) & 0xff00)
-#define BF_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_V(v)   ((BV_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL__##v << 8) & 0xff00)
-#define BP_DCP_CHANNELCTRL_ENABLE_CHANNEL               0
-#define BM_DCP_CHANNELCTRL_ENABLE_CHANNEL               0xff
-#define BV_DCP_CHANNELCTRL_ENABLE_CHANNEL__CH0          0x1
-#define BV_DCP_CHANNELCTRL_ENABLE_CHANNEL__CH1          0x2
-#define BV_DCP_CHANNELCTRL_ENABLE_CHANNEL__CH2          0x4
-#define BV_DCP_CHANNELCTRL_ENABLE_CHANNEL__CH3          0x8
-#define BF_DCP_CHANNELCTRL_ENABLE_CHANNEL(v)            (((v) << 0) & 0xff)
-#define BF_DCP_CHANNELCTRL_ENABLE_CHANNEL_V(v)          ((BV_DCP_CHANNELCTRL_ENABLE_CHANNEL__##v << 0) & 0xff)
-
-/**
- * Register: HW_DCP_CAPABILITY0
- * Address: 0x30
- * SCT: no
-*/
-#define HW_DCP_CAPABILITY0                      (*(volatile unsigned long *)(REGS_DCP_BASE + 0x30))
-#define BP_DCP_CAPABILITY0_DISABLE_DECRYPT      31
-#define BM_DCP_CAPABILITY0_DISABLE_DECRYPT      0x80000000
-#define BF_DCP_CAPABILITY0_DISABLE_DECRYPT(v)   (((v) << 31) & 0x80000000)
-#define BP_DCP_CAPABILITY0_ENABLE_TZONE         30
-#define BM_DCP_CAPABILITY0_ENABLE_TZONE         0x40000000
-#define BF_DCP_CAPABILITY0_ENABLE_TZONE(v)      (((v) << 30) & 0x40000000)
-#define BP_DCP_CAPABILITY0_RSVD                 12
-#define BM_DCP_CAPABILITY0_RSVD                 0x3ffff000
-#define BF_DCP_CAPABILITY0_RSVD(v)              (((v) << 12) & 0x3ffff000)
-#define BP_DCP_CAPABILITY0_NUM_CHANNELS         8
-#define BM_DCP_CAPABILITY0_NUM_CHANNELS         0xf00
-#define BF_DCP_CAPABILITY0_NUM_CHANNELS(v)      (((v) << 8) & 0xf00)
-#define BP_DCP_CAPABILITY0_NUM_KEYS             0
-#define BM_DCP_CAPABILITY0_NUM_KEYS             0xff
-#define BF_DCP_CAPABILITY0_NUM_KEYS(v)          (((v) << 0) & 0xff)
-
-/**
- * Register: HW_DCP_CAPABILITY1
- * Address: 0x40
- * SCT: no
-*/
-#define HW_DCP_CAPABILITY1                              (*(volatile unsigned long *)(REGS_DCP_BASE + 0x40))
-#define BP_DCP_CAPABILITY1_HASH_ALGORITHMS              16
-#define BM_DCP_CAPABILITY1_HASH_ALGORITHMS              0xffff0000
-#define BV_DCP_CAPABILITY1_HASH_ALGORITHMS__SHA1        0x1
-#define BV_DCP_CAPABILITY1_HASH_ALGORITHMS__CRC32       0x2
-#define BF_DCP_CAPABILITY1_HASH_ALGORITHMS(v)           (((v) << 16) & 0xffff0000)
-#define BF_DCP_CAPABILITY1_HASH_ALGORITHMS_V(v)         ((BV_DCP_CAPABILITY1_HASH_ALGORITHMS__##v << 16) & 0xffff0000)
-#define BP_DCP_CAPABILITY1_CIPHER_ALGORITHMS            0
-#define BM_DCP_CAPABILITY1_CIPHER_ALGORITHMS            0xffff
-#define BV_DCP_CAPABILITY1_CIPHER_ALGORITHMS__AES128    0x1
-#define BF_DCP_CAPABILITY1_CIPHER_ALGORITHMS(v)         (((v) << 0) & 0xffff)
-#define BF_DCP_CAPABILITY1_CIPHER_ALGORITHMS_V(v)       ((BV_DCP_CAPABILITY1_CIPHER_ALGORITHMS__##v << 0) & 0xffff)
-
-/**
- * Register: HW_DCP_CONTEXT
- * Address: 0x50
- * SCT: no
-*/
-#define HW_DCP_CONTEXT          (*(volatile unsigned long *)(REGS_DCP_BASE + 0x50))
-#define BP_DCP_CONTEXT_ADDR     0
-#define BM_DCP_CONTEXT_ADDR     0xffffffff
-#define BF_DCP_CONTEXT_ADDR(v)  (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DCP_KEY
- * Address: 0x60
- * SCT: no
-*/
-#define HW_DCP_KEY                  (*(volatile unsigned long *)(REGS_DCP_BASE + 0x60))
-#define BP_DCP_KEY_RSVD             8
-#define BM_DCP_KEY_RSVD             0xffffff00
-#define BF_DCP_KEY_RSVD(v)          (((v) << 8) & 0xffffff00)
-#define BP_DCP_KEY_RSVD_INDEX       6
-#define BM_DCP_KEY_RSVD_INDEX       0xc0
-#define BF_DCP_KEY_RSVD_INDEX(v)    (((v) << 6) & 0xc0)
-#define BP_DCP_KEY_INDEX            4
-#define BM_DCP_KEY_INDEX            0x30
-#define BF_DCP_KEY_INDEX(v)         (((v) << 4) & 0x30)
-#define BP_DCP_KEY_RSVD_SUBWORD     2
-#define BM_DCP_KEY_RSVD_SUBWORD     0xc
-#define BF_DCP_KEY_RSVD_SUBWORD(v)  (((v) << 2) & 0xc)
-#define BP_DCP_KEY_SUBWORD          0
-#define BM_DCP_KEY_SUBWORD          0x3
-#define BF_DCP_KEY_SUBWORD(v)       (((v) << 0) & 0x3)
-
-/**
- * Register: HW_DCP_KEYDATA
- * Address: 0x70
- * SCT: no
-*/
-#define HW_DCP_KEYDATA          (*(volatile unsigned long *)(REGS_DCP_BASE + 0x70))
-#define BP_DCP_KEYDATA_DATA     0
-#define BM_DCP_KEYDATA_DATA     0xffffffff
-#define BF_DCP_KEYDATA_DATA(v)  (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DCP_PACKET0
- * Address: 0x80
- * SCT: no
-*/
-#define HW_DCP_PACKET0          (*(volatile unsigned long *)(REGS_DCP_BASE + 0x80))
-#define BP_DCP_PACKET0_ADDR     0
-#define BM_DCP_PACKET0_ADDR     0xffffffff
-#define BF_DCP_PACKET0_ADDR(v)  (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DCP_PACKET1
- * Address: 0x90
- * SCT: no
-*/
-#define HW_DCP_PACKET1                          (*(volatile unsigned long *)(REGS_DCP_BASE + 0x90))
-#define BP_DCP_PACKET1_TAG                      24
-#define BM_DCP_PACKET1_TAG                      0xff000000
-#define BF_DCP_PACKET1_TAG(v)                   (((v) << 24) & 0xff000000)
-#define BP_DCP_PACKET1_OUTPUT_WORDSWAP          23
-#define BM_DCP_PACKET1_OUTPUT_WORDSWAP          0x800000
-#define BF_DCP_PACKET1_OUTPUT_WORDSWAP(v)       (((v) << 23) & 0x800000)
-#define BP_DCP_PACKET1_OUTPUT_BYTESWAP          22
-#define BM_DCP_PACKET1_OUTPUT_BYTESWAP          0x400000
-#define BF_DCP_PACKET1_OUTPUT_BYTESWAP(v)       (((v) << 22) & 0x400000)
-#define BP_DCP_PACKET1_INPUT_WORDSWAP           21
-#define BM_DCP_PACKET1_INPUT_WORDSWAP           0x200000
-#define BF_DCP_PACKET1_INPUT_WORDSWAP(v)        (((v) << 21) & 0x200000)
-#define BP_DCP_PACKET1_INPUT_BYTESWAP           20
-#define BM_DCP_PACKET1_INPUT_BYTESWAP           0x100000
-#define BF_DCP_PACKET1_INPUT_BYTESWAP(v)        (((v) << 20) & 0x100000)
-#define BP_DCP_PACKET1_KEY_WORDSWAP             19
-#define BM_DCP_PACKET1_KEY_WORDSWAP             0x80000
-#define BF_DCP_PACKET1_KEY_WORDSWAP(v)          (((v) << 19) & 0x80000)
-#define BP_DCP_PACKET1_KEY_BYTESWAP             18
-#define BM_DCP_PACKET1_KEY_BYTESWAP             0x40000
-#define BF_DCP_PACKET1_KEY_BYTESWAP(v)          (((v) << 18) & 0x40000)
-#define BP_DCP_PACKET1_TEST_SEMA_IRQ            17
-#define BM_DCP_PACKET1_TEST_SEMA_IRQ            0x20000
-#define BF_DCP_PACKET1_TEST_SEMA_IRQ(v)         (((v) << 17) & 0x20000)
-#define BP_DCP_PACKET1_CONSTANT_FILL            16
-#define BM_DCP_PACKET1_CONSTANT_FILL            0x10000
-#define BF_DCP_PACKET1_CONSTANT_FILL(v)         (((v) << 16) & 0x10000)
-#define BP_DCP_PACKET1_HASH_OUTPUT              15
-#define BM_DCP_PACKET1_HASH_OUTPUT              0x8000
-#define BV_DCP_PACKET1_HASH_OUTPUT__INPUT       0x0
-#define BV_DCP_PACKET1_HASH_OUTPUT__OUTPUT      0x1
-#define BF_DCP_PACKET1_HASH_OUTPUT(v)           (((v) << 15) & 0x8000)
-#define BF_DCP_PACKET1_HASH_OUTPUT_V(v)         ((BV_DCP_PACKET1_HASH_OUTPUT__##v << 15) & 0x8000)
-#define BP_DCP_PACKET1_CHECK_HASH               14
-#define BM_DCP_PACKET1_CHECK_HASH               0x4000
-#define BF_DCP_PACKET1_CHECK_HASH(v)            (((v) << 14) & 0x4000)
-#define BP_DCP_PACKET1_HASH_TERM                13
-#define BM_DCP_PACKET1_HASH_TERM                0x2000
-#define BF_DCP_PACKET1_HASH_TERM(v)             (((v) << 13) & 0x2000)
-#define BP_DCP_PACKET1_HASH_INIT                12
-#define BM_DCP_PACKET1_HASH_INIT                0x1000
-#define BF_DCP_PACKET1_HASH_INIT(v)             (((v) << 12) & 0x1000)
-#define BP_DCP_PACKET1_PAYLOAD_KEY              11
-#define BM_DCP_PACKET1_PAYLOAD_KEY              0x800
-#define BF_DCP_PACKET1_PAYLOAD_KEY(v)           (((v) << 11) & 0x800)
-#define BP_DCP_PACKET1_OTP_KEY                  10
-#define BM_DCP_PACKET1_OTP_KEY                  0x400
-#define BF_DCP_PACKET1_OTP_KEY(v)               (((v) << 10) & 0x400)
-#define BP_DCP_PACKET1_CIPHER_INIT              9
-#define BM_DCP_PACKET1_CIPHER_INIT              0x200
-#define BF_DCP_PACKET1_CIPHER_INIT(v)           (((v) << 9) & 0x200)
-#define BP_DCP_PACKET1_CIPHER_ENCRYPT           8
-#define BM_DCP_PACKET1_CIPHER_ENCRYPT           0x100
-#define BV_DCP_PACKET1_CIPHER_ENCRYPT__ENCRYPT  0x1
-#define BV_DCP_PACKET1_CIPHER_ENCRYPT__DECRYPT  0x0
-#define BF_DCP_PACKET1_CIPHER_ENCRYPT(v)        (((v) << 8) & 0x100)
-#define BF_DCP_PACKET1_CIPHER_ENCRYPT_V(v)      ((BV_DCP_PACKET1_CIPHER_ENCRYPT__##v << 8) & 0x100)
-#define BP_DCP_PACKET1_ENABLE_BLIT              7
-#define BM_DCP_PACKET1_ENABLE_BLIT              0x80
-#define BF_DCP_PACKET1_ENABLE_BLIT(v)           (((v) << 7) & 0x80)
-#define BP_DCP_PACKET1_ENABLE_HASH              6
-#define BM_DCP_PACKET1_ENABLE_HASH              0x40
-#define BF_DCP_PACKET1_ENABLE_HASH(v)           (((v) << 6) & 0x40)
-#define BP_DCP_PACKET1_ENABLE_CIPHER            5
-#define BM_DCP_PACKET1_ENABLE_CIPHER            0x20
-#define BF_DCP_PACKET1_ENABLE_CIPHER(v)         (((v) << 5) & 0x20)
-#define BP_DCP_PACKET1_ENABLE_MEMCOPY           4
-#define BM_DCP_PACKET1_ENABLE_MEMCOPY           0x10
-#define BF_DCP_PACKET1_ENABLE_MEMCOPY(v)        (((v) << 4) & 0x10)
-#define BP_DCP_PACKET1_CHAIN_CONTIGUOUS         3
-#define BM_DCP_PACKET1_CHAIN_CONTIGUOUS         0x8
-#define BF_DCP_PACKET1_CHAIN_CONTIGUOUS(v)      (((v) << 3) & 0x8)
-#define BP_DCP_PACKET1_CHAIN                    2
-#define BM_DCP_PACKET1_CHAIN                    0x4
-#define BF_DCP_PACKET1_CHAIN(v)                 (((v) << 2) & 0x4)
-#define BP_DCP_PACKET1_DECR_SEMAPHORE           1
-#define BM_DCP_PACKET1_DECR_SEMAPHORE           0x2
-#define BF_DCP_PACKET1_DECR_SEMAPHORE(v)        (((v) << 1) & 0x2)
-#define BP_DCP_PACKET1_INTERRUPT                0
-#define BM_DCP_PACKET1_INTERRUPT                0x1
-#define BF_DCP_PACKET1_INTERRUPT(v)             (((v) << 0) & 0x1)
-
-/**
- * Register: HW_DCP_PACKET2
- * Address: 0xa0
- * SCT: no
-*/
-#define HW_DCP_PACKET2                          (*(volatile unsigned long *)(REGS_DCP_BASE + 0xa0))
-#define BP_DCP_PACKET2_CIPHER_CFG               24
-#define BM_DCP_PACKET2_CIPHER_CFG               0xff000000
-#define BF_DCP_PACKET2_CIPHER_CFG(v)            (((v) << 24) & 0xff000000)
-#define BP_DCP_PACKET2_RSVD                     20
-#define BM_DCP_PACKET2_RSVD                     0xf00000
-#define BF_DCP_PACKET2_RSVD(v)                  (((v) << 20) & 0xf00000)
-#define BP_DCP_PACKET2_HASH_SELECT              16
-#define BM_DCP_PACKET2_HASH_SELECT              0xf0000
-#define BV_DCP_PACKET2_HASH_SELECT__SHA1        0x0
-#define BV_DCP_PACKET2_HASH_SELECT__CRC32       0x1
-#define BF_DCP_PACKET2_HASH_SELECT(v)           (((v) << 16) & 0xf0000)
-#define BF_DCP_PACKET2_HASH_SELECT_V(v)         ((BV_DCP_PACKET2_HASH_SELECT__##v << 16) & 0xf0000)
-#define BP_DCP_PACKET2_KEY_SELECT               8
-#define BM_DCP_PACKET2_KEY_SELECT               0xff00
-#define BF_DCP_PACKET2_KEY_SELECT(v)            (((v) << 8) & 0xff00)
-#define BP_DCP_PACKET2_CIPHER_MODE              4
-#define BM_DCP_PACKET2_CIPHER_MODE              0xf0
-#define BV_DCP_PACKET2_CIPHER_MODE__ECB         0x0
-#define BV_DCP_PACKET2_CIPHER_MODE__CBC         0x1
-#define BF_DCP_PACKET2_CIPHER_MODE(v)           (((v) << 4) & 0xf0)
-#define BF_DCP_PACKET2_CIPHER_MODE_V(v)         ((BV_DCP_PACKET2_CIPHER_MODE__##v << 4) & 0xf0)
-#define BP_DCP_PACKET2_CIPHER_SELECT            0
-#define BM_DCP_PACKET2_CIPHER_SELECT            0xf
-#define BV_DCP_PACKET2_CIPHER_SELECT__AES128    0x0
-#define BF_DCP_PACKET2_CIPHER_SELECT(v)         (((v) << 0) & 0xf)
-#define BF_DCP_PACKET2_CIPHER_SELECT_V(v)       ((BV_DCP_PACKET2_CIPHER_SELECT__##v << 0) & 0xf)
-
-/**
- * Register: HW_DCP_PACKET3
- * Address: 0xb0
- * SCT: no
-*/
-#define HW_DCP_PACKET3          (*(volatile unsigned long *)(REGS_DCP_BASE + 0xb0))
-#define BP_DCP_PACKET3_ADDR     0
-#define BM_DCP_PACKET3_ADDR     0xffffffff
-#define BF_DCP_PACKET3_ADDR(v)  (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DCP_PACKET4
- * Address: 0xc0
- * SCT: no
-*/
-#define HW_DCP_PACKET4          (*(volatile unsigned long *)(REGS_DCP_BASE + 0xc0))
-#define BP_DCP_PACKET4_ADDR     0
-#define BM_DCP_PACKET4_ADDR     0xffffffff
-#define BF_DCP_PACKET4_ADDR(v)  (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DCP_PACKET5
- * Address: 0xd0
- * SCT: no
-*/
-#define HW_DCP_PACKET5          (*(volatile unsigned long *)(REGS_DCP_BASE + 0xd0))
-#define BP_DCP_PACKET5_COUNT    0
-#define BM_DCP_PACKET5_COUNT    0xffffffff
-#define BF_DCP_PACKET5_COUNT(v) (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DCP_PACKET6
- * Address: 0xe0
- * SCT: no
-*/
-#define HW_DCP_PACKET6          (*(volatile unsigned long *)(REGS_DCP_BASE + 0xe0))
-#define BP_DCP_PACKET6_ADDR     0
-#define BM_DCP_PACKET6_ADDR     0xffffffff
-#define BF_DCP_PACKET6_ADDR(v)  (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DCP_CHnCMDPTR
- * Address: 0x100+n*0x40
- * SCT: no
-*/
-#define HW_DCP_CHnCMDPTR(n)         (*(volatile unsigned long *)(REGS_DCP_BASE + 0x100+(n)*0x40))
-#define BP_DCP_CHnCMDPTR_ADDR       0
-#define BM_DCP_CHnCMDPTR_ADDR       0xffffffff
-#define BF_DCP_CHnCMDPTR_ADDR(v)    (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DCP_CHnSEMA
- * Address: 0x110+n*0x40
- * SCT: no
-*/
-#define HW_DCP_CHnSEMA(n)           (*(volatile unsigned long *)(REGS_DCP_BASE + 0x110+(n)*0x40))
-#define BP_DCP_CHnSEMA_RSVD2        24
-#define BM_DCP_CHnSEMA_RSVD2        0xff000000
-#define BF_DCP_CHnSEMA_RSVD2(v)     (((v) << 24) & 0xff000000)
-#define BP_DCP_CHnSEMA_VALUE        16
-#define BM_DCP_CHnSEMA_VALUE        0xff0000
-#define BF_DCP_CHnSEMA_VALUE(v)     (((v) << 16) & 0xff0000)
-#define BP_DCP_CHnSEMA_RSVD1        8
-#define BM_DCP_CHnSEMA_RSVD1        0xff00
-#define BF_DCP_CHnSEMA_RSVD1(v)     (((v) << 8) & 0xff00)
-#define BP_DCP_CHnSEMA_INCREMENT    0
-#define BM_DCP_CHnSEMA_INCREMENT    0xff
-#define BF_DCP_CHnSEMA_INCREMENT(v) (((v) << 0) & 0xff)
-
-/**
- * Register: HW_DCP_CHnSTAT
- * Address: 0x120+n*0x40
- * SCT: yes
-*/
-#define HW_DCP_CHnSTAT(n)                           (*(volatile unsigned long *)(REGS_DCP_BASE + 0x120+(n)*0x40 + 0x0))
-#define HW_DCP_CHnSTAT_SET(n)                       (*(volatile unsigned long *)(REGS_DCP_BASE + 0x120+(n)*0x40 + 0x4))
-#define HW_DCP_CHnSTAT_CLR(n)                       (*(volatile unsigned long *)(REGS_DCP_BASE + 0x120+(n)*0x40 + 0x8))
-#define HW_DCP_CHnSTAT_TOG(n)                       (*(volatile unsigned long *)(REGS_DCP_BASE + 0x120+(n)*0x40 + 0xc))
-#define BP_DCP_CHnSTAT_TAG                          24
-#define BM_DCP_CHnSTAT_TAG                          0xff000000
-#define BF_DCP_CHnSTAT_TAG(v)                       (((v) << 24) & 0xff000000)
-#define BP_DCP_CHnSTAT_ERROR_CODE                   16
-#define BM_DCP_CHnSTAT_ERROR_CODE                   0xff0000
-#define BV_DCP_CHnSTAT_ERROR_CODE__NEXT_CHAIN_IS_0  0x1
-#define BV_DCP_CHnSTAT_ERROR_CODE__NO_CHAIN         0x2
-#define BV_DCP_CHnSTAT_ERROR_CODE__CONTEXT_ERROR    0x3
-#define BV_DCP_CHnSTAT_ERROR_CODE__PAYLOAD_ERROR    0x4
-#define BV_DCP_CHnSTAT_ERROR_CODE__INVALID_MODE     0x5
-#define BF_DCP_CHnSTAT_ERROR_CODE(v)                (((v) << 16) & 0xff0000)
-#define BF_DCP_CHnSTAT_ERROR_CODE_V(v)              ((BV_DCP_CHnSTAT_ERROR_CODE__##v << 16) & 0xff0000)
-#define BP_DCP_CHnSTAT_RSVD0                        7
-#define BM_DCP_CHnSTAT_RSVD0                        0xff80
-#define BF_DCP_CHnSTAT_RSVD0(v)                     (((v) << 7) & 0xff80)
-#define BP_DCP_CHnSTAT_ERROR_PAGEFAULT              6
-#define BM_DCP_CHnSTAT_ERROR_PAGEFAULT              0x40
-#define BF_DCP_CHnSTAT_ERROR_PAGEFAULT(v)           (((v) << 6) & 0x40)
-#define BP_DCP_CHnSTAT_ERROR_DST                    5
-#define BM_DCP_CHnSTAT_ERROR_DST                    0x20
-#define BF_DCP_CHnSTAT_ERROR_DST(v)                 (((v) << 5) & 0x20)
-#define BP_DCP_CHnSTAT_ERROR_SRC                    4
-#define BM_DCP_CHnSTAT_ERROR_SRC                    0x10
-#define BF_DCP_CHnSTAT_ERROR_SRC(v)                 (((v) << 4) & 0x10)
-#define BP_DCP_CHnSTAT_ERROR_PACKET                 3
-#define BM_DCP_CHnSTAT_ERROR_PACKET                 0x8
-#define BF_DCP_CHnSTAT_ERROR_PACKET(v)              (((v) << 3) & 0x8)
-#define BP_DCP_CHnSTAT_ERROR_SETUP                  2
-#define BM_DCP_CHnSTAT_ERROR_SETUP                  0x4
-#define BF_DCP_CHnSTAT_ERROR_SETUP(v)               (((v) << 2) & 0x4)
-#define BP_DCP_CHnSTAT_HASH_MISMATCH                1
-#define BM_DCP_CHnSTAT_HASH_MISMATCH                0x2
-#define BF_DCP_CHnSTAT_HASH_MISMATCH(v)             (((v) << 1) & 0x2)
-#define BP_DCP_CHnSTAT_RSVD_COMPLETE                0
-#define BM_DCP_CHnSTAT_RSVD_COMPLETE                0x1
-#define BF_DCP_CHnSTAT_RSVD_COMPLETE(v)             (((v) << 0) & 0x1)
-
-/**
- * Register: HW_DCP_CHnOPTS
- * Address: 0x130+n*0x40
- * SCT: yes
-*/
-#define HW_DCP_CHnOPTS(n)                   (*(volatile unsigned long *)(REGS_DCP_BASE + 0x130+(n)*0x40 + 0x0))
-#define HW_DCP_CHnOPTS_SET(n)               (*(volatile unsigned long *)(REGS_DCP_BASE + 0x130+(n)*0x40 + 0x4))
-#define HW_DCP_CHnOPTS_CLR(n)               (*(volatile unsigned long *)(REGS_DCP_BASE + 0x130+(n)*0x40 + 0x8))
-#define HW_DCP_CHnOPTS_TOG(n)               (*(volatile unsigned long *)(REGS_DCP_BASE + 0x130+(n)*0x40 + 0xc))
-#define BP_DCP_CHnOPTS_RSVD                 16
-#define BM_DCP_CHnOPTS_RSVD                 0xffff0000
-#define BF_DCP_CHnOPTS_RSVD(v)              (((v) << 16) & 0xffff0000)
-#define BP_DCP_CHnOPTS_RECOVERY_TIMER       0
-#define BM_DCP_CHnOPTS_RECOVERY_TIMER       0xffff
-#define BF_DCP_CHnOPTS_RECOVERY_TIMER(v)    (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_DCP_CSCCTRL0
- * Address: 0x300
- * SCT: yes
-*/
-#define HW_DCP_CSCCTRL0                         (*(volatile unsigned long *)(REGS_DCP_BASE + 0x300 + 0x0))
-#define HW_DCP_CSCCTRL0_SET                     (*(volatile unsigned long *)(REGS_DCP_BASE + 0x300 + 0x4))
-#define HW_DCP_CSCCTRL0_CLR                     (*(volatile unsigned long *)(REGS_DCP_BASE + 0x300 + 0x8))
-#define HW_DCP_CSCCTRL0_TOG                     (*(volatile unsigned long *)(REGS_DCP_BASE + 0x300 + 0xc))
-#define BP_DCP_CSCCTRL0_RSVD1                   16
-#define BM_DCP_CSCCTRL0_RSVD1                   0xffff0000
-#define BF_DCP_CSCCTRL0_RSVD1(v)                (((v) << 16) & 0xffff0000)
-#define BP_DCP_CSCCTRL0_CLIP                    15
-#define BM_DCP_CSCCTRL0_CLIP                    0x8000
-#define BF_DCP_CSCCTRL0_CLIP(v)                 (((v) << 15) & 0x8000)
-#define BP_DCP_CSCCTRL0_UPSAMPLE                14
-#define BM_DCP_CSCCTRL0_UPSAMPLE                0x4000
-#define BF_DCP_CSCCTRL0_UPSAMPLE(v)             (((v) << 14) & 0x4000)
-#define BP_DCP_CSCCTRL0_SCALE                   13
-#define BM_DCP_CSCCTRL0_SCALE                   0x2000
-#define BF_DCP_CSCCTRL0_SCALE(v)                (((v) << 13) & 0x2000)
-#define BP_DCP_CSCCTRL0_ROTATE                  12
-#define BM_DCP_CSCCTRL0_ROTATE                  0x1000
-#define BF_DCP_CSCCTRL0_ROTATE(v)               (((v) << 12) & 0x1000)
-#define BP_DCP_CSCCTRL0_SUBSAMPLE               11
-#define BM_DCP_CSCCTRL0_SUBSAMPLE               0x800
-#define BF_DCP_CSCCTRL0_SUBSAMPLE(v)            (((v) << 11) & 0x800)
-#define BP_DCP_CSCCTRL0_DELTA                   10
-#define BM_DCP_CSCCTRL0_DELTA                   0x400
-#define BF_DCP_CSCCTRL0_DELTA(v)                (((v) << 10) & 0x400)
-#define BP_DCP_CSCCTRL0_RGB_FORMAT              8
-#define BM_DCP_CSCCTRL0_RGB_FORMAT              0x300
-#define BV_DCP_CSCCTRL0_RGB_FORMAT__RGB16_565   0x0
-#define BV_DCP_CSCCTRL0_RGB_FORMAT__YCbCrI      0x1
-#define BV_DCP_CSCCTRL0_RGB_FORMAT__RGB24       0x2
-#define BV_DCP_CSCCTRL0_RGB_FORMAT__YUV422I     0x3
-#define BF_DCP_CSCCTRL0_RGB_FORMAT(v)           (((v) << 8) & 0x300)
-#define BF_DCP_CSCCTRL0_RGB_FORMAT_V(v)         ((BV_DCP_CSCCTRL0_RGB_FORMAT__##v << 8) & 0x300)
-#define BP_DCP_CSCCTRL0_YUV_FORMAT              4
-#define BM_DCP_CSCCTRL0_YUV_FORMAT              0xf0
-#define BV_DCP_CSCCTRL0_YUV_FORMAT__YUV420      0x0
-#define BV_DCP_CSCCTRL0_YUV_FORMAT__YUV422      0x2
-#define BF_DCP_CSCCTRL0_YUV_FORMAT(v)           (((v) << 4) & 0xf0)
-#define BF_DCP_CSCCTRL0_YUV_FORMAT_V(v)         ((BV_DCP_CSCCTRL0_YUV_FORMAT__##v << 4) & 0xf0)
-#define BP_DCP_CSCCTRL0_RSVD0                   1
-#define BM_DCP_CSCCTRL0_RSVD0                   0xe
-#define BF_DCP_CSCCTRL0_RSVD0(v)                (((v) << 1) & 0xe)
-#define BP_DCP_CSCCTRL0_ENABLE                  0
-#define BM_DCP_CSCCTRL0_ENABLE                  0x1
-#define BF_DCP_CSCCTRL0_ENABLE(v)               (((v) << 0) & 0x1)
-
-/**
- * Register: HW_DCP_CSCSTAT
- * Address: 0x310
- * SCT: yes
-*/
-#define HW_DCP_CSCSTAT                                  (*(volatile unsigned long *)(REGS_DCP_BASE + 0x310 + 0x0))
-#define HW_DCP_CSCSTAT_SET                              (*(volatile unsigned long *)(REGS_DCP_BASE + 0x310 + 0x4))
-#define HW_DCP_CSCSTAT_CLR                              (*(volatile unsigned long *)(REGS_DCP_BASE + 0x310 + 0x8))
-#define HW_DCP_CSCSTAT_TOG                              (*(volatile unsigned long *)(REGS_DCP_BASE + 0x310 + 0xc))
-#define BP_DCP_CSCSTAT_RSVD3                            24
-#define BM_DCP_CSCSTAT_RSVD3                            0xff000000
-#define BF_DCP_CSCSTAT_RSVD3(v)                         (((v) << 24) & 0xff000000)
-#define BP_DCP_CSCSTAT_ERROR_CODE                       16
-#define BM_DCP_CSCSTAT_ERROR_CODE                       0xff0000
-#define BV_DCP_CSCSTAT_ERROR_CODE__LUMA0_FETCH_ERROR_Y0 0x1
-#define BV_DCP_CSCSTAT_ERROR_CODE__LUMA1_FETCH_ERROR_Y1 0x2
-#define BV_DCP_CSCSTAT_ERROR_CODE__CHROMA_FETCH_ERROR_U 0x3
-#define BV_DCP_CSCSTAT_ERROR_CODE__CHROMA_FETCH_ERROR_V 0x4
-#define BF_DCP_CSCSTAT_ERROR_CODE(v)                    (((v) << 16) & 0xff0000)
-#define BF_DCP_CSCSTAT_ERROR_CODE_V(v)                  ((BV_DCP_CSCSTAT_ERROR_CODE__##v << 16) & 0xff0000)
-#define BP_DCP_CSCSTAT_RSVD2                            7
-#define BM_DCP_CSCSTAT_RSVD2                            0xff80
-#define BF_DCP_CSCSTAT_RSVD2(v)                         (((v) << 7) & 0xff80)
-#define BP_DCP_CSCSTAT_ERROR_PAGEFAULT                  6
-#define BM_DCP_CSCSTAT_ERROR_PAGEFAULT                  0x40
-#define BF_DCP_CSCSTAT_ERROR_PAGEFAULT(v)               (((v) << 6) & 0x40)
-#define BP_DCP_CSCSTAT_ERROR_DST                        5
-#define BM_DCP_CSCSTAT_ERROR_DST                        0x20
-#define BF_DCP_CSCSTAT_ERROR_DST(v)                     (((v) << 5) & 0x20)
-#define BP_DCP_CSCSTAT_ERROR_SRC                        4
-#define BM_DCP_CSCSTAT_ERROR_SRC                        0x10
-#define BF_DCP_CSCSTAT_ERROR_SRC(v)                     (((v) << 4) & 0x10)
-#define BP_DCP_CSCSTAT_RSVD1                            3
-#define BM_DCP_CSCSTAT_RSVD1                            0x8
-#define BF_DCP_CSCSTAT_RSVD1(v)                         (((v) << 3) & 0x8)
-#define BP_DCP_CSCSTAT_ERROR_SETUP                      2
-#define BM_DCP_CSCSTAT_ERROR_SETUP                      0x4
-#define BF_DCP_CSCSTAT_ERROR_SETUP(v)                   (((v) << 2) & 0x4)
-#define BP_DCP_CSCSTAT_RSVD0                            1
-#define BM_DCP_CSCSTAT_RSVD0                            0x2
-#define BF_DCP_CSCSTAT_RSVD0(v)                         (((v) << 1) & 0x2)
-#define BP_DCP_CSCSTAT_COMPLETE                         0
-#define BM_DCP_CSCSTAT_COMPLETE                         0x1
-#define BF_DCP_CSCSTAT_COMPLETE(v)                      (((v) << 0) & 0x1)
-
-/**
- * Register: HW_DCP_CSCOUTBUFPARAM
- * Address: 0x320
- * SCT: no
-*/
-#define HW_DCP_CSCOUTBUFPARAM               (*(volatile unsigned long *)(REGS_DCP_BASE + 0x320))
-#define BP_DCP_CSCOUTBUFPARAM_RSVD1         24
-#define BM_DCP_CSCOUTBUFPARAM_RSVD1         0xff000000
-#define BF_DCP_CSCOUTBUFPARAM_RSVD1(v)      (((v) << 24) & 0xff000000)
-#define BP_DCP_CSCOUTBUFPARAM_FIELD_SIZE    12
-#define BM_DCP_CSCOUTBUFPARAM_FIELD_SIZE    0xfff000
-#define BF_DCP_CSCOUTBUFPARAM_FIELD_SIZE(v) (((v) << 12) & 0xfff000)
-#define BP_DCP_CSCOUTBUFPARAM_LINE_SIZE     0
-#define BM_DCP_CSCOUTBUFPARAM_LINE_SIZE     0xfff
-#define BF_DCP_CSCOUTBUFPARAM_LINE_SIZE(v)  (((v) << 0) & 0xfff)
-
-/**
- * Register: HW_DCP_CSCINBUFPARAM
- * Address: 0x330
- * SCT: no
-*/
-#define HW_DCP_CSCINBUFPARAM                (*(volatile unsigned long *)(REGS_DCP_BASE + 0x330))
-#define BP_DCP_CSCINBUFPARAM_RSVD1          12
-#define BM_DCP_CSCINBUFPARAM_RSVD1          0xfffff000
-#define BF_DCP_CSCINBUFPARAM_RSVD1(v)       (((v) << 12) & 0xfffff000)
-#define BP_DCP_CSCINBUFPARAM_LINE_SIZE      0
-#define BM_DCP_CSCINBUFPARAM_LINE_SIZE      0xfff
-#define BF_DCP_CSCINBUFPARAM_LINE_SIZE(v)   (((v) << 0) & 0xfff)
-
-/**
- * Register: HW_DCP_CSCRGB
- * Address: 0x340
- * SCT: no
-*/
-#define HW_DCP_CSCRGB           (*(volatile unsigned long *)(REGS_DCP_BASE + 0x340))
-#define BP_DCP_CSCRGB_ADDR      0
-#define BM_DCP_CSCRGB_ADDR      0xffffffff
-#define BF_DCP_CSCRGB_ADDR(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DCP_CSCLUMA
- * Address: 0x350
- * SCT: no
-*/
-#define HW_DCP_CSCLUMA          (*(volatile unsigned long *)(REGS_DCP_BASE + 0x350))
-#define BP_DCP_CSCLUMA_ADDR     0
-#define BM_DCP_CSCLUMA_ADDR     0xffffffff
-#define BF_DCP_CSCLUMA_ADDR(v)  (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DCP_CSCCHROMAU
- * Address: 0x360
- * SCT: no
-*/
-#define HW_DCP_CSCCHROMAU           (*(volatile unsigned long *)(REGS_DCP_BASE + 0x360))
-#define BP_DCP_CSCCHROMAU_ADDR      0
-#define BM_DCP_CSCCHROMAU_ADDR      0xffffffff
-#define BF_DCP_CSCCHROMAU_ADDR(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DCP_CSCCHROMAV
- * Address: 0x370
- * SCT: no
-*/
-#define HW_DCP_CSCCHROMAV           (*(volatile unsigned long *)(REGS_DCP_BASE + 0x370))
-#define BP_DCP_CSCCHROMAV_ADDR      0
-#define BM_DCP_CSCCHROMAV_ADDR      0xffffffff
-#define BF_DCP_CSCCHROMAV_ADDR(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DCP_CSCCOEFF0
- * Address: 0x380
- * SCT: no
-*/
-#define HW_DCP_CSCCOEFF0                (*(volatile unsigned long *)(REGS_DCP_BASE + 0x380))
-#define BP_DCP_CSCCOEFF0_RSVD1          26
-#define BM_DCP_CSCCOEFF0_RSVD1          0xfc000000
-#define BF_DCP_CSCCOEFF0_RSVD1(v)       (((v) << 26) & 0xfc000000)
-#define BP_DCP_CSCCOEFF0_C0             16
-#define BM_DCP_CSCCOEFF0_C0             0x3ff0000
-#define BF_DCP_CSCCOEFF0_C0(v)          (((v) << 16) & 0x3ff0000)
-#define BP_DCP_CSCCOEFF0_UV_OFFSET      8
-#define BM_DCP_CSCCOEFF0_UV_OFFSET      0xff00
-#define BF_DCP_CSCCOEFF0_UV_OFFSET(v)   (((v) << 8) & 0xff00)
-#define BP_DCP_CSCCOEFF0_Y_OFFSET       0
-#define BM_DCP_CSCCOEFF0_Y_OFFSET       0xff
-#define BF_DCP_CSCCOEFF0_Y_OFFSET(v)    (((v) << 0) & 0xff)
-
-/**
- * Register: HW_DCP_CSCCOEFF1
- * Address: 0x390
- * SCT: no
-*/
-#define HW_DCP_CSCCOEFF1            (*(volatile unsigned long *)(REGS_DCP_BASE + 0x390))
-#define BP_DCP_CSCCOEFF1_RSVD1      26
-#define BM_DCP_CSCCOEFF1_RSVD1      0xfc000000
-#define BF_DCP_CSCCOEFF1_RSVD1(v)   (((v) << 26) & 0xfc000000)
-#define BP_DCP_CSCCOEFF1_C1         16
-#define BM_DCP_CSCCOEFF1_C1         0x3ff0000
-#define BF_DCP_CSCCOEFF1_C1(v)      (((v) << 16) & 0x3ff0000)
-#define BP_DCP_CSCCOEFF1_RSVD0      10
-#define BM_DCP_CSCCOEFF1_RSVD0      0xfc00
-#define BF_DCP_CSCCOEFF1_RSVD0(v)   (((v) << 10) & 0xfc00)
-#define BP_DCP_CSCCOEFF1_C4         0
-#define BM_DCP_CSCCOEFF1_C4         0x3ff
-#define BF_DCP_CSCCOEFF1_C4(v)      (((v) << 0) & 0x3ff)
-
-/**
- * Register: HW_DCP_CSCCOEFF2
- * Address: 0x3a0
- * SCT: no
-*/
-#define HW_DCP_CSCCOEFF2            (*(volatile unsigned long *)(REGS_DCP_BASE + 0x3a0))
-#define BP_DCP_CSCCOEFF2_RSVD1      26
-#define BM_DCP_CSCCOEFF2_RSVD1      0xfc000000
-#define BF_DCP_CSCCOEFF2_RSVD1(v)   (((v) << 26) & 0xfc000000)
-#define BP_DCP_CSCCOEFF2_C2         16
-#define BM_DCP_CSCCOEFF2_C2         0x3ff0000
-#define BF_DCP_CSCCOEFF2_C2(v)      (((v) << 16) & 0x3ff0000)
-#define BP_DCP_CSCCOEFF2_RSVD0      10
-#define BM_DCP_CSCCOEFF2_RSVD0      0xfc00
-#define BF_DCP_CSCCOEFF2_RSVD0(v)   (((v) << 10) & 0xfc00)
-#define BP_DCP_CSCCOEFF2_C3         0
-#define BM_DCP_CSCCOEFF2_C3         0x3ff
-#define BF_DCP_CSCCOEFF2_C3(v)      (((v) << 0) & 0x3ff)
-
-/**
- * Register: HW_DCP_CSCCLIP
- * Address: 0x3d0
- * SCT: no
-*/
-#define HW_DCP_CSCCLIP              (*(volatile unsigned long *)(REGS_DCP_BASE + 0x3d0))
-#define BP_DCP_CSCCLIP_RSVD1        24
-#define BM_DCP_CSCCLIP_RSVD1        0xff000000
-#define BF_DCP_CSCCLIP_RSVD1(v)     (((v) << 24) & 0xff000000)
-#define BP_DCP_CSCCLIP_HEIGHT       12
-#define BM_DCP_CSCCLIP_HEIGHT       0xfff000
-#define BF_DCP_CSCCLIP_HEIGHT(v)    (((v) << 12) & 0xfff000)
-#define BP_DCP_CSCCLIP_WIDTH        0
-#define BM_DCP_CSCCLIP_WIDTH        0xfff
-#define BF_DCP_CSCCLIP_WIDTH(v)     (((v) << 0) & 0xfff)
-
-/**
- * Register: HW_DCP_CSCXSCALE
- * Address: 0x3e0
- * SCT: no
-*/
-#define HW_DCP_CSCXSCALE            (*(volatile unsigned long *)(REGS_DCP_BASE + 0x3e0))
-#define BP_DCP_CSCXSCALE_RSVD1      26
-#define BM_DCP_CSCXSCALE_RSVD1      0xfc000000
-#define BF_DCP_CSCXSCALE_RSVD1(v)   (((v) << 26) & 0xfc000000)
-#define BP_DCP_CSCXSCALE_INT        24
-#define BM_DCP_CSCXSCALE_INT        0x3000000
-#define BF_DCP_CSCXSCALE_INT(v)     (((v) << 24) & 0x3000000)
-#define BP_DCP_CSCXSCALE_FRAC       12
-#define BM_DCP_CSCXSCALE_FRAC       0xfff000
-#define BF_DCP_CSCXSCALE_FRAC(v)    (((v) << 12) & 0xfff000)
-#define BP_DCP_CSCXSCALE_WIDTH      0
-#define BM_DCP_CSCXSCALE_WIDTH      0xfff
-#define BF_DCP_CSCXSCALE_WIDTH(v)   (((v) << 0) & 0xfff)
-
-/**
- * Register: HW_DCP_CSCYSCALE
- * Address: 0x3f0
- * SCT: no
-*/
-#define HW_DCP_CSCYSCALE            (*(volatile unsigned long *)(REGS_DCP_BASE + 0x3f0))
-#define BP_DCP_CSCYSCALE_RSVD1      26
-#define BM_DCP_CSCYSCALE_RSVD1      0xfc000000
-#define BF_DCP_CSCYSCALE_RSVD1(v)   (((v) << 26) & 0xfc000000)
-#define BP_DCP_CSCYSCALE_INT        24
-#define BM_DCP_CSCYSCALE_INT        0x3000000
-#define BF_DCP_CSCYSCALE_INT(v)     (((v) << 24) & 0x3000000)
-#define BP_DCP_CSCYSCALE_FRAC       12
-#define BM_DCP_CSCYSCALE_FRAC       0xfff000
-#define BF_DCP_CSCYSCALE_FRAC(v)    (((v) << 12) & 0xfff000)
-#define BP_DCP_CSCYSCALE_HEIGHT     0
-#define BM_DCP_CSCYSCALE_HEIGHT     0xfff
-#define BF_DCP_CSCYSCALE_HEIGHT(v)  (((v) << 0) & 0xfff)
-
-/**
- * Register: HW_DCP_DBGSELECT
- * Address: 0x400
- * SCT: no
-*/
-#define HW_DCP_DBGSELECT                (*(volatile unsigned long *)(REGS_DCP_BASE + 0x400))
-#define BP_DCP_DBGSELECT_RSVD           8
-#define BM_DCP_DBGSELECT_RSVD           0xffffff00
-#define BF_DCP_DBGSELECT_RSVD(v)        (((v) << 8) & 0xffffff00)
-#define BP_DCP_DBGSELECT_INDEX          0
-#define BM_DCP_DBGSELECT_INDEX          0xff
-#define BV_DCP_DBGSELECT_INDEX__CONTROL 0x1
-#define BV_DCP_DBGSELECT_INDEX__OTPKEY0 0x10
-#define BV_DCP_DBGSELECT_INDEX__OTPKEY1 0x11
-#define BV_DCP_DBGSELECT_INDEX__OTPKEY2 0x12
-#define BV_DCP_DBGSELECT_INDEX__OTPKEY3 0x13
-#define BF_DCP_DBGSELECT_INDEX(v)       (((v) << 0) & 0xff)
-#define BF_DCP_DBGSELECT_INDEX_V(v)     ((BV_DCP_DBGSELECT_INDEX__##v << 0) & 0xff)
-
-/**
- * Register: HW_DCP_DBGDATA
- * Address: 0x410
- * SCT: no
-*/
-#define HW_DCP_DBGDATA          (*(volatile unsigned long *)(REGS_DCP_BASE + 0x410))
-#define BP_DCP_DBGDATA_DATA     0
-#define BM_DCP_DBGDATA_DATA     0xffffffff
-#define BF_DCP_DBGDATA_DATA(v)  (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DCP_PAGETABLE
- * Address: 0x420
- * SCT: no
-*/
-#define HW_DCP_PAGETABLE            (*(volatile unsigned long *)(REGS_DCP_BASE + 0x420))
-#define BP_DCP_PAGETABLE_BASE       2
-#define BM_DCP_PAGETABLE_BASE       0xfffffffc
-#define BF_DCP_PAGETABLE_BASE(v)    (((v) << 2) & 0xfffffffc)
-#define BP_DCP_PAGETABLE_FLUSH      1
-#define BM_DCP_PAGETABLE_FLUSH      0x2
-#define BF_DCP_PAGETABLE_FLUSH(v)   (((v) << 1) & 0x2)
-#define BP_DCP_PAGETABLE_ENABLE     0
-#define BM_DCP_PAGETABLE_ENABLE     0x1
-#define BF_DCP_PAGETABLE_ENABLE(v)  (((v) << 0) & 0x1)
-
-/**
- * Register: HW_DCP_VERSION
- * Address: 0x430
- * SCT: no
-*/
-#define HW_DCP_VERSION          (*(volatile unsigned long *)(REGS_DCP_BASE + 0x430))
-#define BP_DCP_VERSION_MAJOR    24
-#define BM_DCP_VERSION_MAJOR    0xff000000
-#define BF_DCP_VERSION_MAJOR(v) (((v) << 24) & 0xff000000)
-#define BP_DCP_VERSION_MINOR    16
-#define BM_DCP_VERSION_MINOR    0xff0000
-#define BF_DCP_VERSION_MINOR(v) (((v) << 16) & 0xff0000)
-#define BP_DCP_VERSION_STEP     0
-#define BM_DCP_VERSION_STEP     0xffff
-#define BF_DCP_VERSION_STEP(v)  (((v) << 0) & 0xffff)
-
-#endif /* __HEADERGEN__IMX233__DCP__H__ */
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-digctl.h b/firmware/target/arm/imx233/regs/imx233/regs-digctl.h
deleted file mode 100644
index 0a67cb10c5..0000000000
--- a/firmware/target/arm/imx233/regs/imx233/regs-digctl.h
+++ /dev/null
@@ -1,966 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: imx233:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__IMX233__DIGCTL__H__
-#define __HEADERGEN__IMX233__DIGCTL__H__
-
-#define REGS_DIGCTL_BASE (0x8001c000)
-
-#define REGS_DIGCTL_VERSION "3.2.0"
-
-/**
- * Register: HW_DIGCTL_CTRL
- * Address: 0
- * SCT: yes
-*/
-#define HW_DIGCTL_CTRL                                      (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x0 + 0x0))
-#define HW_DIGCTL_CTRL_SET                                  (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x0 + 0x4))
-#define HW_DIGCTL_CTRL_CLR                                  (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x0 + 0x8))
-#define HW_DIGCTL_CTRL_TOG                                  (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x0 + 0xc))
-#define BP_DIGCTL_CTRL_RSVD3                                31
-#define BM_DIGCTL_CTRL_RSVD3                                0x80000000
-#define BF_DIGCTL_CTRL_RSVD3(v)                             (((v) << 31) & 0x80000000)
-#define BP_DIGCTL_CTRL_XTAL24M_GATE                         30
-#define BM_DIGCTL_CTRL_XTAL24M_GATE                         0x40000000
-#define BF_DIGCTL_CTRL_XTAL24M_GATE(v)                      (((v) << 30) & 0x40000000)
-#define BP_DIGCTL_CTRL_TRAP_IRQ                             29
-#define BM_DIGCTL_CTRL_TRAP_IRQ                             0x20000000
-#define BF_DIGCTL_CTRL_TRAP_IRQ(v)                          (((v) << 29) & 0x20000000)
-#define BP_DIGCTL_CTRL_RSVD2                                27
-#define BM_DIGCTL_CTRL_RSVD2                                0x18000000
-#define BF_DIGCTL_CTRL_RSVD2(v)                             (((v) << 27) & 0x18000000)
-#define BP_DIGCTL_CTRL_CACHE_BIST_TMODE                     26
-#define BM_DIGCTL_CTRL_CACHE_BIST_TMODE                     0x4000000
-#define BF_DIGCTL_CTRL_CACHE_BIST_TMODE(v)                  (((v) << 26) & 0x4000000)
-#define BP_DIGCTL_CTRL_LCD_BIST_CLKEN                       25
-#define BM_DIGCTL_CTRL_LCD_BIST_CLKEN                       0x2000000
-#define BF_DIGCTL_CTRL_LCD_BIST_CLKEN(v)                    (((v) << 25) & 0x2000000)
-#define BP_DIGCTL_CTRL_LCD_BIST_START                       24
-#define BM_DIGCTL_CTRL_LCD_BIST_START                       0x1000000
-#define BF_DIGCTL_CTRL_LCD_BIST_START(v)                    (((v) << 24) & 0x1000000)
-#define BP_DIGCTL_CTRL_DCP_BIST_CLKEN                       23
-#define BM_DIGCTL_CTRL_DCP_BIST_CLKEN                       0x800000
-#define BF_DIGCTL_CTRL_DCP_BIST_CLKEN(v)                    (((v) << 23) & 0x800000)
-#define BP_DIGCTL_CTRL_DCP_BIST_START                       22
-#define BM_DIGCTL_CTRL_DCP_BIST_START                       0x400000
-#define BF_DIGCTL_CTRL_DCP_BIST_START(v)                    (((v) << 22) & 0x400000)
-#define BP_DIGCTL_CTRL_ARM_BIST_CLKEN                       21
-#define BM_DIGCTL_CTRL_ARM_BIST_CLKEN                       0x200000
-#define BF_DIGCTL_CTRL_ARM_BIST_CLKEN(v)                    (((v) << 21) & 0x200000)
-#define BP_DIGCTL_CTRL_USB_TESTMODE                         20
-#define BM_DIGCTL_CTRL_USB_TESTMODE                         0x100000
-#define BF_DIGCTL_CTRL_USB_TESTMODE(v)                      (((v) << 20) & 0x100000)
-#define BP_DIGCTL_CTRL_ANALOG_TESTMODE                      19
-#define BM_DIGCTL_CTRL_ANALOG_TESTMODE                      0x80000
-#define BF_DIGCTL_CTRL_ANALOG_TESTMODE(v)                   (((v) << 19) & 0x80000)
-#define BP_DIGCTL_CTRL_DIGITAL_TESTMODE                     18
-#define BM_DIGCTL_CTRL_DIGITAL_TESTMODE                     0x40000
-#define BF_DIGCTL_CTRL_DIGITAL_TESTMODE(v)                  (((v) << 18) & 0x40000)
-#define BP_DIGCTL_CTRL_ARM_BIST_START                       17
-#define BM_DIGCTL_CTRL_ARM_BIST_START                       0x20000
-#define BF_DIGCTL_CTRL_ARM_BIST_START(v)                    (((v) << 17) & 0x20000)
-#define BP_DIGCTL_CTRL_UART_LOOPBACK                        16
-#define BM_DIGCTL_CTRL_UART_LOOPBACK                        0x10000
-#define BV_DIGCTL_CTRL_UART_LOOPBACK__NORMAL                0x0
-#define BV_DIGCTL_CTRL_UART_LOOPBACK__LOOPIT                0x1
-#define BF_DIGCTL_CTRL_UART_LOOPBACK(v)                     (((v) << 16) & 0x10000)
-#define BF_DIGCTL_CTRL_UART_LOOPBACK_V(v)                   ((BV_DIGCTL_CTRL_UART_LOOPBACK__##v << 16) & 0x10000)
-#define BP_DIGCTL_CTRL_SAIF_LOOPBACK                        15
-#define BM_DIGCTL_CTRL_SAIF_LOOPBACK                        0x8000
-#define BV_DIGCTL_CTRL_SAIF_LOOPBACK__NORMAL                0x0
-#define BV_DIGCTL_CTRL_SAIF_LOOPBACK__LOOPIT                0x1
-#define BF_DIGCTL_CTRL_SAIF_LOOPBACK(v)                     (((v) << 15) & 0x8000)
-#define BF_DIGCTL_CTRL_SAIF_LOOPBACK_V(v)                   ((BV_DIGCTL_CTRL_SAIF_LOOPBACK__##v << 15) & 0x8000)
-#define BP_DIGCTL_CTRL_SAIF_CLKMUX_SEL                      13
-#define BM_DIGCTL_CTRL_SAIF_CLKMUX_SEL                      0x6000
-#define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__MBL_CLK_OUT         0x0
-#define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__BL_CLK_OUT          0x1
-#define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__M_CLK_OUT_BL_CLK_IN 0x2
-#define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__BL_CLK_IN           0x3
-#define BF_DIGCTL_CTRL_SAIF_CLKMUX_SEL(v)                   (((v) << 13) & 0x6000)
-#define BF_DIGCTL_CTRL_SAIF_CLKMUX_SEL_V(v)                 ((BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__##v << 13) & 0x6000)
-#define BP_DIGCTL_CTRL_SAIF_CLKMST_SEL                      12
-#define BM_DIGCTL_CTRL_SAIF_CLKMST_SEL                      0x1000
-#define BV_DIGCTL_CTRL_SAIF_CLKMST_SEL__SAIF1_MST           0x0
-#define BV_DIGCTL_CTRL_SAIF_CLKMST_SEL__SAIF2_MST           0x1
-#define BF_DIGCTL_CTRL_SAIF_CLKMST_SEL(v)                   (((v) << 12) & 0x1000)
-#define BF_DIGCTL_CTRL_SAIF_CLKMST_SEL_V(v)                 ((BV_DIGCTL_CTRL_SAIF_CLKMST_SEL__##v << 12) & 0x1000)
-#define BP_DIGCTL_CTRL_SAIF_ALT_BITCLK_SEL                  11
-#define BM_DIGCTL_CTRL_SAIF_ALT_BITCLK_SEL                  0x800
-#define BF_DIGCTL_CTRL_SAIF_ALT_BITCLK_SEL(v)               (((v) << 11) & 0x800)
-#define BP_DIGCTL_CTRL_RSVD1                                10
-#define BM_DIGCTL_CTRL_RSVD1                                0x400
-#define BF_DIGCTL_CTRL_RSVD1(v)                             (((v) << 10) & 0x400)
-#define BP_DIGCTL_CTRL_SY_ENDIAN                            9
-#define BM_DIGCTL_CTRL_SY_ENDIAN                            0x200
-#define BF_DIGCTL_CTRL_SY_ENDIAN(v)                         (((v) << 9) & 0x200)
-#define BP_DIGCTL_CTRL_SY_SFTRST                            8
-#define BM_DIGCTL_CTRL_SY_SFTRST                            0x100
-#define BF_DIGCTL_CTRL_SY_SFTRST(v)                         (((v) << 8) & 0x100)
-#define BP_DIGCTL_CTRL_SY_CLKGATE                           7
-#define BM_DIGCTL_CTRL_SY_CLKGATE                           0x80
-#define BF_DIGCTL_CTRL_SY_CLKGATE(v)                        (((v) << 7) & 0x80)
-#define BP_DIGCTL_CTRL_USE_SERIAL_JTAG                      6
-#define BM_DIGCTL_CTRL_USE_SERIAL_JTAG                      0x40
-#define BV_DIGCTL_CTRL_USE_SERIAL_JTAG__OLD_JTAG            0x0
-#define BV_DIGCTL_CTRL_USE_SERIAL_JTAG__SERIAL_JTAG         0x1
-#define BF_DIGCTL_CTRL_USE_SERIAL_JTAG(v)                   (((v) << 6) & 0x40)
-#define BF_DIGCTL_CTRL_USE_SERIAL_JTAG_V(v)                 ((BV_DIGCTL_CTRL_USE_SERIAL_JTAG__##v << 6) & 0x40)
-#define BP_DIGCTL_CTRL_TRAP_IN_RANGE                        5
-#define BM_DIGCTL_CTRL_TRAP_IN_RANGE                        0x20
-#define BF_DIGCTL_CTRL_TRAP_IN_RANGE(v)                     (((v) << 5) & 0x20)
-#define BP_DIGCTL_CTRL_TRAP_ENABLE                          4
-#define BM_DIGCTL_CTRL_TRAP_ENABLE                          0x10
-#define BF_DIGCTL_CTRL_TRAP_ENABLE(v)                       (((v) << 4) & 0x10)
-#define BP_DIGCTL_CTRL_DEBUG_DISABLE                        3
-#define BM_DIGCTL_CTRL_DEBUG_DISABLE                        0x8
-#define BF_DIGCTL_CTRL_DEBUG_DISABLE(v)                     (((v) << 3) & 0x8)
-#define BP_DIGCTL_CTRL_USB_CLKGATE                          2
-#define BM_DIGCTL_CTRL_USB_CLKGATE                          0x4
-#define BV_DIGCTL_CTRL_USB_CLKGATE__RUN                     0x0
-#define BV_DIGCTL_CTRL_USB_CLKGATE__NO_CLKS                 0x1
-#define BF_DIGCTL_CTRL_USB_CLKGATE(v)                       (((v) << 2) & 0x4)
-#define BF_DIGCTL_CTRL_USB_CLKGATE_V(v)                     ((BV_DIGCTL_CTRL_USB_CLKGATE__##v << 2) & 0x4)
-#define BP_DIGCTL_CTRL_JTAG_SHIELD                          1
-#define BM_DIGCTL_CTRL_JTAG_SHIELD                          0x2
-#define BV_DIGCTL_CTRL_JTAG_SHIELD__NORMAL                  0x0
-#define BV_DIGCTL_CTRL_JTAG_SHIELD__SHIELDS_UP              0x1
-#define BF_DIGCTL_CTRL_JTAG_SHIELD(v)                       (((v) << 1) & 0x2)
-#define BF_DIGCTL_CTRL_JTAG_SHIELD_V(v)                     ((BV_DIGCTL_CTRL_JTAG_SHIELD__##v << 1) & 0x2)
-#define BP_DIGCTL_CTRL_LATCH_ENTROPY                        0
-#define BM_DIGCTL_CTRL_LATCH_ENTROPY                        0x1
-#define BF_DIGCTL_CTRL_LATCH_ENTROPY(v)                     (((v) << 0) & 0x1)
-
-/**
- * Register: HW_DIGCTL_STATUS
- * Address: 0x10
- * SCT: yes
-*/
-#define HW_DIGCTL_STATUS                        (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x10 + 0x0))
-#define HW_DIGCTL_STATUS_SET                    (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x10 + 0x4))
-#define HW_DIGCTL_STATUS_CLR                    (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x10 + 0x8))
-#define HW_DIGCTL_STATUS_TOG                    (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x10 + 0xc))
-#define BP_DIGCTL_STATUS_USB_HS_PRESENT         31
-#define BM_DIGCTL_STATUS_USB_HS_PRESENT         0x80000000
-#define BF_DIGCTL_STATUS_USB_HS_PRESENT(v)      (((v) << 31) & 0x80000000)
-#define BP_DIGCTL_STATUS_USB_OTG_PRESENT        30
-#define BM_DIGCTL_STATUS_USB_OTG_PRESENT        0x40000000
-#define BF_DIGCTL_STATUS_USB_OTG_PRESENT(v)     (((v) << 30) & 0x40000000)
-#define BP_DIGCTL_STATUS_USB_HOST_PRESENT       29
-#define BM_DIGCTL_STATUS_USB_HOST_PRESENT       0x20000000
-#define BF_DIGCTL_STATUS_USB_HOST_PRESENT(v)    (((v) << 29) & 0x20000000)
-#define BP_DIGCTL_STATUS_USB_DEVICE_PRESENT     28
-#define BM_DIGCTL_STATUS_USB_DEVICE_PRESENT     0x10000000
-#define BF_DIGCTL_STATUS_USB_DEVICE_PRESENT(v)  (((v) << 28) & 0x10000000)
-#define BP_DIGCTL_STATUS_RSVD2                  11
-#define BM_DIGCTL_STATUS_RSVD2                  0xffff800
-#define BF_DIGCTL_STATUS_RSVD2(v)               (((v) << 11) & 0xffff800)
-#define BP_DIGCTL_STATUS_DCP_BIST_FAIL          10
-#define BM_DIGCTL_STATUS_DCP_BIST_FAIL          0x400
-#define BF_DIGCTL_STATUS_DCP_BIST_FAIL(v)       (((v) << 10) & 0x400)
-#define BP_DIGCTL_STATUS_DCP_BIST_PASS          9
-#define BM_DIGCTL_STATUS_DCP_BIST_PASS          0x200
-#define BF_DIGCTL_STATUS_DCP_BIST_PASS(v)       (((v) << 9) & 0x200)
-#define BP_DIGCTL_STATUS_DCP_BIST_DONE          8
-#define BM_DIGCTL_STATUS_DCP_BIST_DONE          0x100
-#define BF_DIGCTL_STATUS_DCP_BIST_DONE(v)       (((v) << 8) & 0x100)
-#define BP_DIGCTL_STATUS_LCD_BIST_FAIL          7
-#define BM_DIGCTL_STATUS_LCD_BIST_FAIL          0x80
-#define BF_DIGCTL_STATUS_LCD_BIST_FAIL(v)       (((v) << 7) & 0x80)
-#define BP_DIGCTL_STATUS_LCD_BIST_PASS          6
-#define BM_DIGCTL_STATUS_LCD_BIST_PASS          0x40
-#define BF_DIGCTL_STATUS_LCD_BIST_PASS(v)       (((v) << 6) & 0x40)
-#define BP_DIGCTL_STATUS_LCD_BIST_DONE          5
-#define BM_DIGCTL_STATUS_LCD_BIST_DONE          0x20
-#define BF_DIGCTL_STATUS_LCD_BIST_DONE(v)       (((v) << 5) & 0x20)
-#define BP_DIGCTL_STATUS_JTAG_IN_USE            4
-#define BM_DIGCTL_STATUS_JTAG_IN_USE            0x10
-#define BF_DIGCTL_STATUS_JTAG_IN_USE(v)         (((v) << 4) & 0x10)
-#define BP_DIGCTL_STATUS_PACKAGE_TYPE           1
-#define BM_DIGCTL_STATUS_PACKAGE_TYPE           0xe
-#define BF_DIGCTL_STATUS_PACKAGE_TYPE(v)        (((v) << 1) & 0xe)
-#define BP_DIGCTL_STATUS_WRITTEN                0
-#define BM_DIGCTL_STATUS_WRITTEN                0x1
-#define BF_DIGCTL_STATUS_WRITTEN(v)             (((v) << 0) & 0x1)
-
-/**
- * Register: HW_DIGCTL_HCLKCOUNT
- * Address: 0x20
- * SCT: yes
-*/
-#define HW_DIGCTL_HCLKCOUNT             (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x20 + 0x0))
-#define HW_DIGCTL_HCLKCOUNT_SET         (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x20 + 0x4))
-#define HW_DIGCTL_HCLKCOUNT_CLR         (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x20 + 0x8))
-#define HW_DIGCTL_HCLKCOUNT_TOG         (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x20 + 0xc))
-#define BP_DIGCTL_HCLKCOUNT_COUNT       0
-#define BM_DIGCTL_HCLKCOUNT_COUNT       0xffffffff
-#define BF_DIGCTL_HCLKCOUNT_COUNT(v)    (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_RAMCTRL
- * Address: 0x30
- * SCT: yes
-*/
-#define HW_DIGCTL_RAMCTRL                   (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x30 + 0x0))
-#define HW_DIGCTL_RAMCTRL_SET               (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x30 + 0x4))
-#define HW_DIGCTL_RAMCTRL_CLR               (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x30 + 0x8))
-#define HW_DIGCTL_RAMCTRL_TOG               (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x30 + 0xc))
-#define BP_DIGCTL_RAMCTRL_RSVD1             12
-#define BM_DIGCTL_RAMCTRL_RSVD1             0xfffff000
-#define BF_DIGCTL_RAMCTRL_RSVD1(v)          (((v) << 12) & 0xfffff000)
-#define BP_DIGCTL_RAMCTRL_SPEED_SELECT      8
-#define BM_DIGCTL_RAMCTRL_SPEED_SELECT      0xf00
-#define BF_DIGCTL_RAMCTRL_SPEED_SELECT(v)   (((v) << 8) & 0xf00)
-#define BP_DIGCTL_RAMCTRL_RSVD0             1
-#define BM_DIGCTL_RAMCTRL_RSVD0             0xfe
-#define BF_DIGCTL_RAMCTRL_RSVD0(v)          (((v) << 1) & 0xfe)
-#define BP_DIGCTL_RAMCTRL_RAM_REPAIR_EN     0
-#define BM_DIGCTL_RAMCTRL_RAM_REPAIR_EN     0x1
-#define BF_DIGCTL_RAMCTRL_RAM_REPAIR_EN(v)  (((v) << 0) & 0x1)
-
-/**
- * Register: HW_DIGCTL_RAMREPAIR
- * Address: 0x40
- * SCT: yes
-*/
-#define HW_DIGCTL_RAMREPAIR             (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x40 + 0x0))
-#define HW_DIGCTL_RAMREPAIR_SET         (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x40 + 0x4))
-#define HW_DIGCTL_RAMREPAIR_CLR         (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x40 + 0x8))
-#define HW_DIGCTL_RAMREPAIR_TOG         (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x40 + 0xc))
-#define BP_DIGCTL_RAMREPAIR_RSVD1       16
-#define BM_DIGCTL_RAMREPAIR_RSVD1       0xffff0000
-#define BF_DIGCTL_RAMREPAIR_RSVD1(v)    (((v) << 16) & 0xffff0000)
-#define BP_DIGCTL_RAMREPAIR_ADDR        0
-#define BM_DIGCTL_RAMREPAIR_ADDR        0xffff
-#define BF_DIGCTL_RAMREPAIR_ADDR(v)     (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_DIGCTL_ROMCTRL
- * Address: 0x50
- * SCT: yes
-*/
-#define HW_DIGCTL_ROMCTRL               (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x50 + 0x0))
-#define HW_DIGCTL_ROMCTRL_SET           (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x50 + 0x4))
-#define HW_DIGCTL_ROMCTRL_CLR           (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x50 + 0x8))
-#define HW_DIGCTL_ROMCTRL_TOG           (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x50 + 0xc))
-#define BP_DIGCTL_ROMCTRL_RSVD0         4
-#define BM_DIGCTL_ROMCTRL_RSVD0         0xfffffff0
-#define BF_DIGCTL_ROMCTRL_RSVD0(v)      (((v) << 4) & 0xfffffff0)
-#define BP_DIGCTL_ROMCTRL_RD_MARGIN     0
-#define BM_DIGCTL_ROMCTRL_RD_MARGIN     0xf
-#define BF_DIGCTL_ROMCTRL_RD_MARGIN(v)  (((v) << 0) & 0xf)
-
-/**
- * Register: HW_DIGCTL_WRITEONCE
- * Address: 0x60
- * SCT: no
-*/
-#define HW_DIGCTL_WRITEONCE         (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x60))
-#define BP_DIGCTL_WRITEONCE_BITS    0
-#define BM_DIGCTL_WRITEONCE_BITS    0xffffffff
-#define BF_DIGCTL_WRITEONCE_BITS(v) (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_ENTROPY
- * Address: 0x90
- * SCT: no
-*/
-#define HW_DIGCTL_ENTROPY           (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x90))
-#define BP_DIGCTL_ENTROPY_VALUE     0
-#define BM_DIGCTL_ENTROPY_VALUE     0xffffffff
-#define BF_DIGCTL_ENTROPY_VALUE(v)  (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_ENTROPY_LATCHED
- * Address: 0xa0
- * SCT: no
-*/
-#define HW_DIGCTL_ENTROPY_LATCHED           (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xa0))
-#define BP_DIGCTL_ENTROPY_LATCHED_VALUE     0
-#define BM_DIGCTL_ENTROPY_LATCHED_VALUE     0xffffffff
-#define BF_DIGCTL_ENTROPY_LATCHED_VALUE(v)  (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_SJTAGDBG
- * Address: 0xb0
- * SCT: yes
-*/
-#define HW_DIGCTL_SJTAGDBG                      (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xb0 + 0x0))
-#define HW_DIGCTL_SJTAGDBG_SET                  (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xb0 + 0x4))
-#define HW_DIGCTL_SJTAGDBG_CLR                  (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xb0 + 0x8))
-#define HW_DIGCTL_SJTAGDBG_TOG                  (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xb0 + 0xc))
-#define BP_DIGCTL_SJTAGDBG_RSVD2                27
-#define BM_DIGCTL_SJTAGDBG_RSVD2                0xf8000000
-#define BF_DIGCTL_SJTAGDBG_RSVD2(v)             (((v) << 27) & 0xf8000000)
-#define BP_DIGCTL_SJTAGDBG_SJTAG_STATE          16
-#define BM_DIGCTL_SJTAGDBG_SJTAG_STATE          0x7ff0000
-#define BF_DIGCTL_SJTAGDBG_SJTAG_STATE(v)       (((v) << 16) & 0x7ff0000)
-#define BP_DIGCTL_SJTAGDBG_RSVD1                11
-#define BM_DIGCTL_SJTAGDBG_RSVD1                0xf800
-#define BF_DIGCTL_SJTAGDBG_RSVD1(v)             (((v) << 11) & 0xf800)
-#define BP_DIGCTL_SJTAGDBG_SJTAG_TDO            10
-#define BM_DIGCTL_SJTAGDBG_SJTAG_TDO            0x400
-#define BF_DIGCTL_SJTAGDBG_SJTAG_TDO(v)         (((v) << 10) & 0x400)
-#define BP_DIGCTL_SJTAGDBG_SJTAG_TDI            9
-#define BM_DIGCTL_SJTAGDBG_SJTAG_TDI            0x200
-#define BF_DIGCTL_SJTAGDBG_SJTAG_TDI(v)         (((v) << 9) & 0x200)
-#define BP_DIGCTL_SJTAGDBG_SJTAG_MODE           8
-#define BM_DIGCTL_SJTAGDBG_SJTAG_MODE           0x100
-#define BF_DIGCTL_SJTAGDBG_SJTAG_MODE(v)        (((v) << 8) & 0x100)
-#define BP_DIGCTL_SJTAGDBG_DELAYED_ACTIVE       4
-#define BM_DIGCTL_SJTAGDBG_DELAYED_ACTIVE       0xf0
-#define BF_DIGCTL_SJTAGDBG_DELAYED_ACTIVE(v)    (((v) << 4) & 0xf0)
-#define BP_DIGCTL_SJTAGDBG_ACTIVE               3
-#define BM_DIGCTL_SJTAGDBG_ACTIVE               0x8
-#define BF_DIGCTL_SJTAGDBG_ACTIVE(v)            (((v) << 3) & 0x8)
-#define BP_DIGCTL_SJTAGDBG_SJTAG_PIN_STATE      2
-#define BM_DIGCTL_SJTAGDBG_SJTAG_PIN_STATE      0x4
-#define BF_DIGCTL_SJTAGDBG_SJTAG_PIN_STATE(v)   (((v) << 2) & 0x4)
-#define BP_DIGCTL_SJTAGDBG_SJTAG_DEBUG_DATA     1
-#define BM_DIGCTL_SJTAGDBG_SJTAG_DEBUG_DATA     0x2
-#define BF_DIGCTL_SJTAGDBG_SJTAG_DEBUG_DATA(v)  (((v) << 1) & 0x2)
-#define BP_DIGCTL_SJTAGDBG_SJTAG_DEBUG_OE       0
-#define BM_DIGCTL_SJTAGDBG_SJTAG_DEBUG_OE       0x1
-#define BF_DIGCTL_SJTAGDBG_SJTAG_DEBUG_OE(v)    (((v) << 0) & 0x1)
-
-/**
- * Register: HW_DIGCTL_MICROSECONDS
- * Address: 0xc0
- * SCT: yes
-*/
-#define HW_DIGCTL_MICROSECONDS          (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xc0 + 0x0))
-#define HW_DIGCTL_MICROSECONDS_SET      (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xc0 + 0x4))
-#define HW_DIGCTL_MICROSECONDS_CLR      (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xc0 + 0x8))
-#define HW_DIGCTL_MICROSECONDS_TOG      (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xc0 + 0xc))
-#define BP_DIGCTL_MICROSECONDS_VALUE    0
-#define BM_DIGCTL_MICROSECONDS_VALUE    0xffffffff
-#define BF_DIGCTL_MICROSECONDS_VALUE(v) (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_DBGRD
- * Address: 0xd0
- * SCT: no
-*/
-#define HW_DIGCTL_DBGRD                 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xd0))
-#define BP_DIGCTL_DBGRD_COMPLEMENT      0
-#define BM_DIGCTL_DBGRD_COMPLEMENT      0xffffffff
-#define BF_DIGCTL_DBGRD_COMPLEMENT(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_DBG
- * Address: 0xe0
- * SCT: no
-*/
-#define HW_DIGCTL_DBG           (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xe0))
-#define BP_DIGCTL_DBG_VALUE     0
-#define BM_DIGCTL_DBG_VALUE     0xffffffff
-#define BF_DIGCTL_DBG_VALUE(v)  (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_OCRAM_BIST_CSR
- * Address: 0xf0
- * SCT: yes
-*/
-#define HW_DIGCTL_OCRAM_BIST_CSR                        (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xf0 + 0x0))
-#define HW_DIGCTL_OCRAM_BIST_CSR_SET                    (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xf0 + 0x4))
-#define HW_DIGCTL_OCRAM_BIST_CSR_CLR                    (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xf0 + 0x8))
-#define HW_DIGCTL_OCRAM_BIST_CSR_TOG                    (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xf0 + 0xc))
-#define BP_DIGCTL_OCRAM_BIST_CSR_RSVD1                  11
-#define BM_DIGCTL_OCRAM_BIST_CSR_RSVD1                  0xfffff800
-#define BF_DIGCTL_OCRAM_BIST_CSR_RSVD1(v)               (((v) << 11) & 0xfffff800)
-#define BP_DIGCTL_OCRAM_BIST_CSR_BIST_DEBUG_MODE        10
-#define BM_DIGCTL_OCRAM_BIST_CSR_BIST_DEBUG_MODE        0x400
-#define BF_DIGCTL_OCRAM_BIST_CSR_BIST_DEBUG_MODE(v)     (((v) << 10) & 0x400)
-#define BP_DIGCTL_OCRAM_BIST_CSR_BIST_DATA_CHANGE       9
-#define BM_DIGCTL_OCRAM_BIST_CSR_BIST_DATA_CHANGE       0x200
-#define BF_DIGCTL_OCRAM_BIST_CSR_BIST_DATA_CHANGE(v)    (((v) << 9) & 0x200)
-#define BP_DIGCTL_OCRAM_BIST_CSR_BIST_CLKEN             8
-#define BM_DIGCTL_OCRAM_BIST_CSR_BIST_CLKEN             0x100
-#define BF_DIGCTL_OCRAM_BIST_CSR_BIST_CLKEN(v)          (((v) << 8) & 0x100)
-#define BP_DIGCTL_OCRAM_BIST_CSR_RSVD0                  4
-#define BM_DIGCTL_OCRAM_BIST_CSR_RSVD0                  0xf0
-#define BF_DIGCTL_OCRAM_BIST_CSR_RSVD0(v)               (((v) << 4) & 0xf0)
-#define BP_DIGCTL_OCRAM_BIST_CSR_FAIL                   3
-#define BM_DIGCTL_OCRAM_BIST_CSR_FAIL                   0x8
-#define BF_DIGCTL_OCRAM_BIST_CSR_FAIL(v)                (((v) << 3) & 0x8)
-#define BP_DIGCTL_OCRAM_BIST_CSR_PASS                   2
-#define BM_DIGCTL_OCRAM_BIST_CSR_PASS                   0x4
-#define BF_DIGCTL_OCRAM_BIST_CSR_PASS(v)                (((v) << 2) & 0x4)
-#define BP_DIGCTL_OCRAM_BIST_CSR_DONE                   1
-#define BM_DIGCTL_OCRAM_BIST_CSR_DONE                   0x2
-#define BF_DIGCTL_OCRAM_BIST_CSR_DONE(v)                (((v) << 1) & 0x2)
-#define BP_DIGCTL_OCRAM_BIST_CSR_START                  0
-#define BM_DIGCTL_OCRAM_BIST_CSR_START                  0x1
-#define BF_DIGCTL_OCRAM_BIST_CSR_START(v)               (((v) << 0) & 0x1)
-
-/**
- * Register: HW_DIGCTL_OCRAM_STATUS0
- * Address: 0x110
- * SCT: yes
-*/
-#define HW_DIGCTL_OCRAM_STATUS0                 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x110 + 0x0))
-#define HW_DIGCTL_OCRAM_STATUS0_SET             (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x110 + 0x4))
-#define HW_DIGCTL_OCRAM_STATUS0_CLR             (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x110 + 0x8))
-#define HW_DIGCTL_OCRAM_STATUS0_TOG             (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x110 + 0xc))
-#define BP_DIGCTL_OCRAM_STATUS0_FAILDATA00      0
-#define BM_DIGCTL_OCRAM_STATUS0_FAILDATA00      0xffffffff
-#define BF_DIGCTL_OCRAM_STATUS0_FAILDATA00(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_OCRAM_STATUS1
- * Address: 0x120
- * SCT: yes
-*/
-#define HW_DIGCTL_OCRAM_STATUS1                 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x120 + 0x0))
-#define HW_DIGCTL_OCRAM_STATUS1_SET             (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x120 + 0x4))
-#define HW_DIGCTL_OCRAM_STATUS1_CLR             (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x120 + 0x8))
-#define HW_DIGCTL_OCRAM_STATUS1_TOG             (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x120 + 0xc))
-#define BP_DIGCTL_OCRAM_STATUS1_FAILDATA01      0
-#define BM_DIGCTL_OCRAM_STATUS1_FAILDATA01      0xffffffff
-#define BF_DIGCTL_OCRAM_STATUS1_FAILDATA01(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_OCRAM_STATUS2
- * Address: 0x130
- * SCT: yes
-*/
-#define HW_DIGCTL_OCRAM_STATUS2                 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x130 + 0x0))
-#define HW_DIGCTL_OCRAM_STATUS2_SET             (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x130 + 0x4))
-#define HW_DIGCTL_OCRAM_STATUS2_CLR             (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x130 + 0x8))
-#define HW_DIGCTL_OCRAM_STATUS2_TOG             (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x130 + 0xc))
-#define BP_DIGCTL_OCRAM_STATUS2_FAILDATA10      0
-#define BM_DIGCTL_OCRAM_STATUS2_FAILDATA10      0xffffffff
-#define BF_DIGCTL_OCRAM_STATUS2_FAILDATA10(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_OCRAM_STATUS3
- * Address: 0x140
- * SCT: yes
-*/
-#define HW_DIGCTL_OCRAM_STATUS3                 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x140 + 0x0))
-#define HW_DIGCTL_OCRAM_STATUS3_SET             (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x140 + 0x4))
-#define HW_DIGCTL_OCRAM_STATUS3_CLR             (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x140 + 0x8))
-#define HW_DIGCTL_OCRAM_STATUS3_TOG             (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x140 + 0xc))
-#define BP_DIGCTL_OCRAM_STATUS3_FAILDATA11      0
-#define BM_DIGCTL_OCRAM_STATUS3_FAILDATA11      0xffffffff
-#define BF_DIGCTL_OCRAM_STATUS3_FAILDATA11(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_OCRAM_STATUS4
- * Address: 0x150
- * SCT: yes
-*/
-#define HW_DIGCTL_OCRAM_STATUS4                 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x150 + 0x0))
-#define HW_DIGCTL_OCRAM_STATUS4_SET             (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x150 + 0x4))
-#define HW_DIGCTL_OCRAM_STATUS4_CLR             (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x150 + 0x8))
-#define HW_DIGCTL_OCRAM_STATUS4_TOG             (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x150 + 0xc))
-#define BP_DIGCTL_OCRAM_STATUS4_FAILDATA20      0
-#define BM_DIGCTL_OCRAM_STATUS4_FAILDATA20      0xffffffff
-#define BF_DIGCTL_OCRAM_STATUS4_FAILDATA20(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_OCRAM_STATUS5
- * Address: 0x160
- * SCT: yes
-*/
-#define HW_DIGCTL_OCRAM_STATUS5                 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x160 + 0x0))
-#define HW_DIGCTL_OCRAM_STATUS5_SET             (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x160 + 0x4))
-#define HW_DIGCTL_OCRAM_STATUS5_CLR             (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x160 + 0x8))
-#define HW_DIGCTL_OCRAM_STATUS5_TOG             (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x160 + 0xc))
-#define BP_DIGCTL_OCRAM_STATUS5_FAILDATA21      0
-#define BM_DIGCTL_OCRAM_STATUS5_FAILDATA21      0xffffffff
-#define BF_DIGCTL_OCRAM_STATUS5_FAILDATA21(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_OCRAM_STATUS6
- * Address: 0x170
- * SCT: yes
-*/
-#define HW_DIGCTL_OCRAM_STATUS6                 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x170 + 0x0))
-#define HW_DIGCTL_OCRAM_STATUS6_SET             (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x170 + 0x4))
-#define HW_DIGCTL_OCRAM_STATUS6_CLR             (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x170 + 0x8))
-#define HW_DIGCTL_OCRAM_STATUS6_TOG             (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x170 + 0xc))
-#define BP_DIGCTL_OCRAM_STATUS6_FAILDATA30      0
-#define BM_DIGCTL_OCRAM_STATUS6_FAILDATA30      0xffffffff
-#define BF_DIGCTL_OCRAM_STATUS6_FAILDATA30(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_OCRAM_STATUS7
- * Address: 0x180
- * SCT: yes
-*/
-#define HW_DIGCTL_OCRAM_STATUS7                 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x180 + 0x0))
-#define HW_DIGCTL_OCRAM_STATUS7_SET             (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x180 + 0x4))
-#define HW_DIGCTL_OCRAM_STATUS7_CLR             (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x180 + 0x8))
-#define HW_DIGCTL_OCRAM_STATUS7_TOG             (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x180 + 0xc))
-#define BP_DIGCTL_OCRAM_STATUS7_FAILDATA31      0
-#define BM_DIGCTL_OCRAM_STATUS7_FAILDATA31      0xffffffff
-#define BF_DIGCTL_OCRAM_STATUS7_FAILDATA31(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_OCRAM_STATUS8
- * Address: 0x190
- * SCT: yes
-*/
-#define HW_DIGCTL_OCRAM_STATUS8                 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x190 + 0x0))
-#define HW_DIGCTL_OCRAM_STATUS8_SET             (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x190 + 0x4))
-#define HW_DIGCTL_OCRAM_STATUS8_CLR             (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x190 + 0x8))
-#define HW_DIGCTL_OCRAM_STATUS8_TOG             (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x190 + 0xc))
-#define BP_DIGCTL_OCRAM_STATUS8_RSVD3           29
-#define BM_DIGCTL_OCRAM_STATUS8_RSVD3           0xe0000000
-#define BF_DIGCTL_OCRAM_STATUS8_RSVD3(v)        (((v) << 29) & 0xe0000000)
-#define BP_DIGCTL_OCRAM_STATUS8_FAILADDR01      16
-#define BM_DIGCTL_OCRAM_STATUS8_FAILADDR01      0x1fff0000
-#define BF_DIGCTL_OCRAM_STATUS8_FAILADDR01(v)   (((v) << 16) & 0x1fff0000)
-#define BP_DIGCTL_OCRAM_STATUS8_RSVD2           13
-#define BM_DIGCTL_OCRAM_STATUS8_RSVD2           0xe000
-#define BF_DIGCTL_OCRAM_STATUS8_RSVD2(v)        (((v) << 13) & 0xe000)
-#define BP_DIGCTL_OCRAM_STATUS8_FAILADDR00      0
-#define BM_DIGCTL_OCRAM_STATUS8_FAILADDR00      0x1fff
-#define BF_DIGCTL_OCRAM_STATUS8_FAILADDR00(v)   (((v) << 0) & 0x1fff)
-
-/**
- * Register: HW_DIGCTL_OCRAM_STATUS9
- * Address: 0x1a0
- * SCT: yes
-*/
-#define HW_DIGCTL_OCRAM_STATUS9                 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1a0 + 0x0))
-#define HW_DIGCTL_OCRAM_STATUS9_SET             (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1a0 + 0x4))
-#define HW_DIGCTL_OCRAM_STATUS9_CLR             (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1a0 + 0x8))
-#define HW_DIGCTL_OCRAM_STATUS9_TOG             (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1a0 + 0xc))
-#define BP_DIGCTL_OCRAM_STATUS9_RSVD3           29
-#define BM_DIGCTL_OCRAM_STATUS9_RSVD3           0xe0000000
-#define BF_DIGCTL_OCRAM_STATUS9_RSVD3(v)        (((v) << 29) & 0xe0000000)
-#define BP_DIGCTL_OCRAM_STATUS9_FAILADDR11      16
-#define BM_DIGCTL_OCRAM_STATUS9_FAILADDR11      0x1fff0000
-#define BF_DIGCTL_OCRAM_STATUS9_FAILADDR11(v)   (((v) << 16) & 0x1fff0000)
-#define BP_DIGCTL_OCRAM_STATUS9_RSVD2           13
-#define BM_DIGCTL_OCRAM_STATUS9_RSVD2           0xe000
-#define BF_DIGCTL_OCRAM_STATUS9_RSVD2(v)        (((v) << 13) & 0xe000)
-#define BP_DIGCTL_OCRAM_STATUS9_FAILADDR10      0
-#define BM_DIGCTL_OCRAM_STATUS9_FAILADDR10      0x1fff
-#define BF_DIGCTL_OCRAM_STATUS9_FAILADDR10(v)   (((v) << 0) & 0x1fff)
-
-/**
- * Register: HW_DIGCTL_OCRAM_STATUS10
- * Address: 0x1b0
- * SCT: yes
-*/
-#define HW_DIGCTL_OCRAM_STATUS10                (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1b0 + 0x0))
-#define HW_DIGCTL_OCRAM_STATUS10_SET            (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1b0 + 0x4))
-#define HW_DIGCTL_OCRAM_STATUS10_CLR            (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1b0 + 0x8))
-#define HW_DIGCTL_OCRAM_STATUS10_TOG            (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1b0 + 0xc))
-#define BP_DIGCTL_OCRAM_STATUS10_RSVD3          29
-#define BM_DIGCTL_OCRAM_STATUS10_RSVD3          0xe0000000
-#define BF_DIGCTL_OCRAM_STATUS10_RSVD3(v)       (((v) << 29) & 0xe0000000)
-#define BP_DIGCTL_OCRAM_STATUS10_FAILADDR21     16
-#define BM_DIGCTL_OCRAM_STATUS10_FAILADDR21     0x1fff0000
-#define BF_DIGCTL_OCRAM_STATUS10_FAILADDR21(v)  (((v) << 16) & 0x1fff0000)
-#define BP_DIGCTL_OCRAM_STATUS10_RSVD2          13
-#define BM_DIGCTL_OCRAM_STATUS10_RSVD2          0xe000
-#define BF_DIGCTL_OCRAM_STATUS10_RSVD2(v)       (((v) << 13) & 0xe000)
-#define BP_DIGCTL_OCRAM_STATUS10_FAILADDR20     0
-#define BM_DIGCTL_OCRAM_STATUS10_FAILADDR20     0x1fff
-#define BF_DIGCTL_OCRAM_STATUS10_FAILADDR20(v)  (((v) << 0) & 0x1fff)
-
-/**
- * Register: HW_DIGCTL_OCRAM_STATUS11
- * Address: 0x1c0
- * SCT: yes
-*/
-#define HW_DIGCTL_OCRAM_STATUS11                (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1c0 + 0x0))
-#define HW_DIGCTL_OCRAM_STATUS11_SET            (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1c0 + 0x4))
-#define HW_DIGCTL_OCRAM_STATUS11_CLR            (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1c0 + 0x8))
-#define HW_DIGCTL_OCRAM_STATUS11_TOG            (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1c0 + 0xc))
-#define BP_DIGCTL_OCRAM_STATUS11_RSVD3          29
-#define BM_DIGCTL_OCRAM_STATUS11_RSVD3          0xe0000000
-#define BF_DIGCTL_OCRAM_STATUS11_RSVD3(v)       (((v) << 29) & 0xe0000000)
-#define BP_DIGCTL_OCRAM_STATUS11_FAILADDR31     16
-#define BM_DIGCTL_OCRAM_STATUS11_FAILADDR31     0x1fff0000
-#define BF_DIGCTL_OCRAM_STATUS11_FAILADDR31(v)  (((v) << 16) & 0x1fff0000)
-#define BP_DIGCTL_OCRAM_STATUS11_RSVD2          13
-#define BM_DIGCTL_OCRAM_STATUS11_RSVD2          0xe000
-#define BF_DIGCTL_OCRAM_STATUS11_RSVD2(v)       (((v) << 13) & 0xe000)
-#define BP_DIGCTL_OCRAM_STATUS11_FAILADDR30     0
-#define BM_DIGCTL_OCRAM_STATUS11_FAILADDR30     0x1fff
-#define BF_DIGCTL_OCRAM_STATUS11_FAILADDR30(v)  (((v) << 0) & 0x1fff)
-
-/**
- * Register: HW_DIGCTL_OCRAM_STATUS12
- * Address: 0x1d0
- * SCT: yes
-*/
-#define HW_DIGCTL_OCRAM_STATUS12                (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1d0 + 0x0))
-#define HW_DIGCTL_OCRAM_STATUS12_SET            (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1d0 + 0x4))
-#define HW_DIGCTL_OCRAM_STATUS12_CLR            (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1d0 + 0x8))
-#define HW_DIGCTL_OCRAM_STATUS12_TOG            (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1d0 + 0xc))
-#define BP_DIGCTL_OCRAM_STATUS12_RSVD3          28
-#define BM_DIGCTL_OCRAM_STATUS12_RSVD3          0xf0000000
-#define BF_DIGCTL_OCRAM_STATUS12_RSVD3(v)       (((v) << 28) & 0xf0000000)
-#define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE11    24
-#define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE11    0xf000000
-#define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE11(v) (((v) << 24) & 0xf000000)
-#define BP_DIGCTL_OCRAM_STATUS12_RSVD2          20
-#define BM_DIGCTL_OCRAM_STATUS12_RSVD2          0xf00000
-#define BF_DIGCTL_OCRAM_STATUS12_RSVD2(v)       (((v) << 20) & 0xf00000)
-#define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE10    16
-#define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE10    0xf0000
-#define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE10(v) (((v) << 16) & 0xf0000)
-#define BP_DIGCTL_OCRAM_STATUS12_RSVD1          12
-#define BM_DIGCTL_OCRAM_STATUS12_RSVD1          0xf000
-#define BF_DIGCTL_OCRAM_STATUS12_RSVD1(v)       (((v) << 12) & 0xf000)
-#define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE01    8
-#define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE01    0xf00
-#define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE01(v) (((v) << 8) & 0xf00)
-#define BP_DIGCTL_OCRAM_STATUS12_RSVD0          4
-#define BM_DIGCTL_OCRAM_STATUS12_RSVD0          0xf0
-#define BF_DIGCTL_OCRAM_STATUS12_RSVD0(v)       (((v) << 4) & 0xf0)
-#define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE00    0
-#define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE00    0xf
-#define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE00(v) (((v) << 0) & 0xf)
-
-/**
- * Register: HW_DIGCTL_OCRAM_STATUS13
- * Address: 0x1e0
- * SCT: yes
-*/
-#define HW_DIGCTL_OCRAM_STATUS13                (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1e0 + 0x0))
-#define HW_DIGCTL_OCRAM_STATUS13_SET            (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1e0 + 0x4))
-#define HW_DIGCTL_OCRAM_STATUS13_CLR            (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1e0 + 0x8))
-#define HW_DIGCTL_OCRAM_STATUS13_TOG            (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1e0 + 0xc))
-#define BP_DIGCTL_OCRAM_STATUS13_RSVD3          28
-#define BM_DIGCTL_OCRAM_STATUS13_RSVD3          0xf0000000
-#define BF_DIGCTL_OCRAM_STATUS13_RSVD3(v)       (((v) << 28) & 0xf0000000)
-#define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE31    24
-#define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE31    0xf000000
-#define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE31(v) (((v) << 24) & 0xf000000)
-#define BP_DIGCTL_OCRAM_STATUS13_RSVD2          20
-#define BM_DIGCTL_OCRAM_STATUS13_RSVD2          0xf00000
-#define BF_DIGCTL_OCRAM_STATUS13_RSVD2(v)       (((v) << 20) & 0xf00000)
-#define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE30    16
-#define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE30    0xf0000
-#define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE30(v) (((v) << 16) & 0xf0000)
-#define BP_DIGCTL_OCRAM_STATUS13_RSVD1          12
-#define BM_DIGCTL_OCRAM_STATUS13_RSVD1          0xf000
-#define BF_DIGCTL_OCRAM_STATUS13_RSVD1(v)       (((v) << 12) & 0xf000)
-#define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE21    8
-#define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE21    0xf00
-#define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE21(v) (((v) << 8) & 0xf00)
-#define BP_DIGCTL_OCRAM_STATUS13_RSVD0          4
-#define BM_DIGCTL_OCRAM_STATUS13_RSVD0          0xf0
-#define BF_DIGCTL_OCRAM_STATUS13_RSVD0(v)       (((v) << 4) & 0xf0)
-#define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE20    0
-#define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE20    0xf
-#define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE20(v) (((v) << 0) & 0xf)
-
-/**
- * Register: HW_DIGCTL_SCRATCH0
- * Address: 0x290
- * SCT: no
-*/
-#define HW_DIGCTL_SCRATCH0          (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x290))
-#define BP_DIGCTL_SCRATCH0_PTR      0
-#define BM_DIGCTL_SCRATCH0_PTR      0xffffffff
-#define BF_DIGCTL_SCRATCH0_PTR(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_SCRATCH1
- * Address: 0x2a0
- * SCT: no
-*/
-#define HW_DIGCTL_SCRATCH1          (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x2a0))
-#define BP_DIGCTL_SCRATCH1_PTR      0
-#define BM_DIGCTL_SCRATCH1_PTR      0xffffffff
-#define BF_DIGCTL_SCRATCH1_PTR(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_ARMCACHE
- * Address: 0x2b0
- * SCT: no
-*/
-#define HW_DIGCTL_ARMCACHE              (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x2b0))
-#define BP_DIGCTL_ARMCACHE_RSVD4        18
-#define BM_DIGCTL_ARMCACHE_RSVD4        0xfffc0000
-#define BF_DIGCTL_ARMCACHE_RSVD4(v)     (((v) << 18) & 0xfffc0000)
-#define BP_DIGCTL_ARMCACHE_VALID_SS     16
-#define BM_DIGCTL_ARMCACHE_VALID_SS     0x30000
-#define BF_DIGCTL_ARMCACHE_VALID_SS(v)  (((v) << 16) & 0x30000)
-#define BP_DIGCTL_ARMCACHE_RSVD3        14
-#define BM_DIGCTL_ARMCACHE_RSVD3        0xc000
-#define BF_DIGCTL_ARMCACHE_RSVD3(v)     (((v) << 14) & 0xc000)
-#define BP_DIGCTL_ARMCACHE_DRTY_SS      12
-#define BM_DIGCTL_ARMCACHE_DRTY_SS      0x3000
-#define BF_DIGCTL_ARMCACHE_DRTY_SS(v)   (((v) << 12) & 0x3000)
-#define BP_DIGCTL_ARMCACHE_RSVD2        10
-#define BM_DIGCTL_ARMCACHE_RSVD2        0xc00
-#define BF_DIGCTL_ARMCACHE_RSVD2(v)     (((v) << 10) & 0xc00)
-#define BP_DIGCTL_ARMCACHE_CACHE_SS     8
-#define BM_DIGCTL_ARMCACHE_CACHE_SS     0x300
-#define BF_DIGCTL_ARMCACHE_CACHE_SS(v)  (((v) << 8) & 0x300)
-#define BP_DIGCTL_ARMCACHE_RSVD1        6
-#define BM_DIGCTL_ARMCACHE_RSVD1        0xc0
-#define BF_DIGCTL_ARMCACHE_RSVD1(v)     (((v) << 6) & 0xc0)
-#define BP_DIGCTL_ARMCACHE_DTAG_SS      4
-#define BM_DIGCTL_ARMCACHE_DTAG_SS      0x30
-#define BF_DIGCTL_ARMCACHE_DTAG_SS(v)   (((v) << 4) & 0x30)
-#define BP_DIGCTL_ARMCACHE_RSVD0        2
-#define BM_DIGCTL_ARMCACHE_RSVD0        0xc
-#define BF_DIGCTL_ARMCACHE_RSVD0(v)     (((v) << 2) & 0xc)
-#define BP_DIGCTL_ARMCACHE_ITAG_SS      0
-#define BM_DIGCTL_ARMCACHE_ITAG_SS      0x3
-#define BF_DIGCTL_ARMCACHE_ITAG_SS(v)   (((v) << 0) & 0x3)
-
-/**
- * Register: HW_DIGCTL_DEBUG_TRAP_ADDR_LOW
- * Address: 0x2c0
- * SCT: no
-*/
-#define HW_DIGCTL_DEBUG_TRAP_ADDR_LOW           (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x2c0))
-#define BP_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR      0
-#define BM_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR      0xffffffff
-#define BF_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_DEBUG_TRAP_ADDR_HIGH
- * Address: 0x2d0
- * SCT: no
-*/
-#define HW_DIGCTL_DEBUG_TRAP_ADDR_HIGH          (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x2d0))
-#define BP_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR     0
-#define BM_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR     0xffffffff
-#define BF_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR(v)  (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_SGTL
- * Address: 0x300
- * SCT: no
-*/
-#define HW_DIGCTL_SGTL              (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x300))
-#define BP_DIGCTL_SGTL_COPYRIGHT    0
-#define BM_DIGCTL_SGTL_COPYRIGHT    0xffffffff
-#define BF_DIGCTL_SGTL_COPYRIGHT(v) (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_CHIPID
- * Address: 0x310
- * SCT: no
-*/
-#define HW_DIGCTL_CHIPID                    (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x310))
-#define BP_DIGCTL_CHIPID_PRODUCT_CODE       16
-#define BM_DIGCTL_CHIPID_PRODUCT_CODE       0xffff0000
-#define BF_DIGCTL_CHIPID_PRODUCT_CODE(v)    (((v) << 16) & 0xffff0000)
-#define BP_DIGCTL_CHIPID_RSVD0              8
-#define BM_DIGCTL_CHIPID_RSVD0              0xff00
-#define BF_DIGCTL_CHIPID_RSVD0(v)           (((v) << 8) & 0xff00)
-#define BP_DIGCTL_CHIPID_REVISION           0
-#define BM_DIGCTL_CHIPID_REVISION           0xff
-#define BF_DIGCTL_CHIPID_REVISION(v)        (((v) << 0) & 0xff)
-
-/**
- * Register: HW_DIGCTL_AHB_STATS_SELECT
- * Address: 0x330
- * SCT: no
-*/
-#define HW_DIGCTL_AHB_STATS_SELECT                          (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x330))
-#define BP_DIGCTL_AHB_STATS_SELECT_RSVD3                    28
-#define BM_DIGCTL_AHB_STATS_SELECT_RSVD3                    0xf0000000
-#define BF_DIGCTL_AHB_STATS_SELECT_RSVD3(v)                 (((v) << 28) & 0xf0000000)
-#define BP_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT         24
-#define BM_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT         0xf000000
-#define BV_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT__APBH   0x1
-#define BV_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT__APBX   0x2
-#define BV_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT__USB    0x4
-#define BF_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT(v)      (((v) << 24) & 0xf000000)
-#define BF_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT_V(v)    ((BV_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT__##v << 24) & 0xf000000)
-#define BP_DIGCTL_AHB_STATS_SELECT_RSVD2                    20
-#define BM_DIGCTL_AHB_STATS_SELECT_RSVD2                    0xf00000
-#define BF_DIGCTL_AHB_STATS_SELECT_RSVD2(v)                 (((v) << 20) & 0xf00000)
-#define BP_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT         16
-#define BM_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT         0xf0000
-#define BV_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT__ARM_D  0x1
-#define BF_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT(v)      (((v) << 16) & 0xf0000)
-#define BF_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT_V(v)    ((BV_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT__##v << 16) & 0xf0000)
-#define BP_DIGCTL_AHB_STATS_SELECT_RSVD1                    12
-#define BM_DIGCTL_AHB_STATS_SELECT_RSVD1                    0xf000
-#define BF_DIGCTL_AHB_STATS_SELECT_RSVD1(v)                 (((v) << 12) & 0xf000)
-#define BP_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT         8
-#define BM_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT         0xf00
-#define BV_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT__ARM_I  0x1
-#define BF_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT(v)      (((v) << 8) & 0xf00)
-#define BF_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT_V(v)    ((BV_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT__##v << 8) & 0xf00)
-#define BP_DIGCTL_AHB_STATS_SELECT_RSVD0                    4
-#define BM_DIGCTL_AHB_STATS_SELECT_RSVD0                    0xf0
-#define BF_DIGCTL_AHB_STATS_SELECT_RSVD0(v)                 (((v) << 4) & 0xf0)
-#define BP_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT         0
-#define BM_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT         0xf
-#define BV_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT__ECC8   0x1
-#define BV_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT__CRYPTO 0x2
-#define BF_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT(v)      (((v) << 0) & 0xf)
-#define BF_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT_V(v)    ((BV_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT__##v << 0) & 0xf)
-
-/**
- * Register: HW_DIGCTL_L0_AHB_ACTIVE_CYCLES
- * Address: 0x340
- * SCT: no
-*/
-#define HW_DIGCTL_L0_AHB_ACTIVE_CYCLES          (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x340))
-#define BP_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT    0
-#define BM_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT    0xffffffff
-#define BF_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT(v) (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_L0_AHB_DATA_STALLED
- * Address: 0x350
- * SCT: no
-*/
-#define HW_DIGCTL_L0_AHB_DATA_STALLED           (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x350))
-#define BP_DIGCTL_L0_AHB_DATA_STALLED_COUNT     0
-#define BM_DIGCTL_L0_AHB_DATA_STALLED_COUNT     0xffffffff
-#define BF_DIGCTL_L0_AHB_DATA_STALLED_COUNT(v)  (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_L0_AHB_DATA_CYCLES
- * Address: 0x360
- * SCT: no
-*/
-#define HW_DIGCTL_L0_AHB_DATA_CYCLES            (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x360))
-#define BP_DIGCTL_L0_AHB_DATA_CYCLES_COUNT      0
-#define BM_DIGCTL_L0_AHB_DATA_CYCLES_COUNT      0xffffffff
-#define BF_DIGCTL_L0_AHB_DATA_CYCLES_COUNT(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_L1_AHB_ACTIVE_CYCLES
- * Address: 0x370
- * SCT: no
-*/
-#define HW_DIGCTL_L1_AHB_ACTIVE_CYCLES          (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x370))
-#define BP_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT    0
-#define BM_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT    0xffffffff
-#define BF_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT(v) (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_L1_AHB_DATA_STALLED
- * Address: 0x380
- * SCT: no
-*/
-#define HW_DIGCTL_L1_AHB_DATA_STALLED           (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x380))
-#define BP_DIGCTL_L1_AHB_DATA_STALLED_COUNT     0
-#define BM_DIGCTL_L1_AHB_DATA_STALLED_COUNT     0xffffffff
-#define BF_DIGCTL_L1_AHB_DATA_STALLED_COUNT(v)  (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_L1_AHB_DATA_CYCLES
- * Address: 0x390
- * SCT: no
-*/
-#define HW_DIGCTL_L1_AHB_DATA_CYCLES            (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x390))
-#define BP_DIGCTL_L1_AHB_DATA_CYCLES_COUNT      0
-#define BM_DIGCTL_L1_AHB_DATA_CYCLES_COUNT      0xffffffff
-#define BF_DIGCTL_L1_AHB_DATA_CYCLES_COUNT(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_L2_AHB_ACTIVE_CYCLES
- * Address: 0x3a0
- * SCT: no
-*/
-#define HW_DIGCTL_L2_AHB_ACTIVE_CYCLES          (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x3a0))
-#define BP_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT    0
-#define BM_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT    0xffffffff
-#define BF_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT(v) (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_L2_AHB_DATA_STALLED
- * Address: 0x3b0
- * SCT: no
-*/
-#define HW_DIGCTL_L2_AHB_DATA_STALLED           (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x3b0))
-#define BP_DIGCTL_L2_AHB_DATA_STALLED_COUNT     0
-#define BM_DIGCTL_L2_AHB_DATA_STALLED_COUNT     0xffffffff
-#define BF_DIGCTL_L2_AHB_DATA_STALLED_COUNT(v)  (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_L2_AHB_DATA_CYCLES
- * Address: 0x3c0
- * SCT: no
-*/
-#define HW_DIGCTL_L2_AHB_DATA_CYCLES            (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x3c0))
-#define BP_DIGCTL_L2_AHB_DATA_CYCLES_COUNT      0
-#define BM_DIGCTL_L2_AHB_DATA_CYCLES_COUNT      0xffffffff
-#define BF_DIGCTL_L2_AHB_DATA_CYCLES_COUNT(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_L3_AHB_ACTIVE_CYCLES
- * Address: 0x3d0
- * SCT: no
-*/
-#define HW_DIGCTL_L3_AHB_ACTIVE_CYCLES          (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x3d0))
-#define BP_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT    0
-#define BM_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT    0xffffffff
-#define BF_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT(v) (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_L3_AHB_DATA_STALLED
- * Address: 0x3e0
- * SCT: no
-*/
-#define HW_DIGCTL_L3_AHB_DATA_STALLED           (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x3e0))
-#define BP_DIGCTL_L3_AHB_DATA_STALLED_COUNT     0
-#define BM_DIGCTL_L3_AHB_DATA_STALLED_COUNT     0xffffffff
-#define BF_DIGCTL_L3_AHB_DATA_STALLED_COUNT(v)  (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_L3_AHB_DATA_CYCLES
- * Address: 0x3f0
- * SCT: no
-*/
-#define HW_DIGCTL_L3_AHB_DATA_CYCLES            (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x3f0))
-#define BP_DIGCTL_L3_AHB_DATA_CYCLES_COUNT      0
-#define BM_DIGCTL_L3_AHB_DATA_CYCLES_COUNT      0xffffffff
-#define BF_DIGCTL_L3_AHB_DATA_CYCLES_COUNT(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_MPTEn_LOC
- * Address: 0x400+n*0x10
- * SCT: no
-*/
-#define HW_DIGCTL_MPTEn_LOC(n)          (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x400+(n)*0x10))
-#define BP_DIGCTL_MPTEn_LOC_RSVD0       12
-#define BM_DIGCTL_MPTEn_LOC_RSVD0       0xfffff000
-#define BF_DIGCTL_MPTEn_LOC_RSVD0(v)    (((v) << 12) & 0xfffff000)
-#define BP_DIGCTL_MPTEn_LOC_LOC         0
-#define BM_DIGCTL_MPTEn_LOC_LOC         0xfff
-#define BF_DIGCTL_MPTEn_LOC_LOC(v)      (((v) << 0) & 0xfff)
-
-/**
- * Register: HW_DIGCTL_EMICLK_DELAY
- * Address: 0x500
- * SCT: no
-*/
-#define HW_DIGCTL_EMICLK_DELAY              (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x500))
-#define BP_DIGCTL_EMICLK_DELAY_RSVD0        5
-#define BM_DIGCTL_EMICLK_DELAY_RSVD0        0xffffffe0
-#define BF_DIGCTL_EMICLK_DELAY_RSVD0(v)     (((v) << 5) & 0xffffffe0)
-#define BP_DIGCTL_EMICLK_DELAY_NUM_TAPS     0
-#define BM_DIGCTL_EMICLK_DELAY_NUM_TAPS     0x1f
-#define BF_DIGCTL_EMICLK_DELAY_NUM_TAPS(v)  (((v) << 0) & 0x1f)
-
-#endif /* __HEADERGEN__IMX233__DIGCTL__H__ */
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-dram.h b/firmware/target/arm/imx233/regs/imx233/regs-dram.h
deleted file mode 100644
index 778256b9e3..0000000000
--- a/firmware/target/arm/imx233/regs/imx233/regs-dram.h
+++ /dev/null
@@ -1,980 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: imx233:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__IMX233__DRAM__H__
-#define __HEADERGEN__IMX233__DRAM__H__
-
-#define REGS_DRAM_BASE (0x800e0000)
-
-#define REGS_DRAM_VERSION "3.2.0"
-
-/**
- * Register: HW_DRAM_CTL00
- * Address: 0
- * SCT: no
-*/
-#define HW_DRAM_CTL00                       (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x0))
-#define BP_DRAM_CTL00_RSVD4                 25
-#define BM_DRAM_CTL00_RSVD4                 0xfe000000
-#define BF_DRAM_CTL00_RSVD4(v)              (((v) << 25) & 0xfe000000)
-#define BP_DRAM_CTL00_AHB0_W_PRIORITY       24
-#define BM_DRAM_CTL00_AHB0_W_PRIORITY       0x1000000
-#define BF_DRAM_CTL00_AHB0_W_PRIORITY(v)    (((v) << 24) & 0x1000000)
-#define BP_DRAM_CTL00_RSVD3                 17
-#define BM_DRAM_CTL00_RSVD3                 0xfe0000
-#define BF_DRAM_CTL00_RSVD3(v)              (((v) << 17) & 0xfe0000)
-#define BP_DRAM_CTL00_AHB0_R_PRIORITY       16
-#define BM_DRAM_CTL00_AHB0_R_PRIORITY       0x10000
-#define BF_DRAM_CTL00_AHB0_R_PRIORITY(v)    (((v) << 16) & 0x10000)
-#define BP_DRAM_CTL00_RSVD2                 9
-#define BM_DRAM_CTL00_RSVD2                 0xfe00
-#define BF_DRAM_CTL00_RSVD2(v)              (((v) << 9) & 0xfe00)
-#define BP_DRAM_CTL00_AHB0_FIFO_TYPE_REG    8
-#define BM_DRAM_CTL00_AHB0_FIFO_TYPE_REG    0x100
-#define BF_DRAM_CTL00_AHB0_FIFO_TYPE_REG(v) (((v) << 8) & 0x100)
-#define BP_DRAM_CTL00_RSVD1                 1
-#define BM_DRAM_CTL00_RSVD1                 0xfe
-#define BF_DRAM_CTL00_RSVD1(v)              (((v) << 1) & 0xfe)
-#define BP_DRAM_CTL00_ADDR_CMP_EN           0
-#define BM_DRAM_CTL00_ADDR_CMP_EN           0x1
-#define BF_DRAM_CTL00_ADDR_CMP_EN(v)        (((v) << 0) & 0x1)
-
-/**
- * Register: HW_DRAM_CTL01
- * Address: 0x4
- * SCT: no
-*/
-#define HW_DRAM_CTL01                       (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x4))
-#define BP_DRAM_CTL01_RSVD4                 25
-#define BM_DRAM_CTL01_RSVD4                 0xfe000000
-#define BF_DRAM_CTL01_RSVD4(v)              (((v) << 25) & 0xfe000000)
-#define BP_DRAM_CTL01_AHB2_FIFO_TYPE_REG    24
-#define BM_DRAM_CTL01_AHB2_FIFO_TYPE_REG    0x1000000
-#define BF_DRAM_CTL01_AHB2_FIFO_TYPE_REG(v) (((v) << 24) & 0x1000000)
-#define BP_DRAM_CTL01_RSVD3                 17
-#define BM_DRAM_CTL01_RSVD3                 0xfe0000
-#define BF_DRAM_CTL01_RSVD3(v)              (((v) << 17) & 0xfe0000)
-#define BP_DRAM_CTL01_AHB1_W_PRIORITY       16
-#define BM_DRAM_CTL01_AHB1_W_PRIORITY       0x10000
-#define BF_DRAM_CTL01_AHB1_W_PRIORITY(v)    (((v) << 16) & 0x10000)
-#define BP_DRAM_CTL01_RSVD2                 9
-#define BM_DRAM_CTL01_RSVD2                 0xfe00
-#define BF_DRAM_CTL01_RSVD2(v)              (((v) << 9) & 0xfe00)
-#define BP_DRAM_CTL01_AHB1_R_PRIORITY       8
-#define BM_DRAM_CTL01_AHB1_R_PRIORITY       0x100
-#define BF_DRAM_CTL01_AHB1_R_PRIORITY(v)    (((v) << 8) & 0x100)
-#define BP_DRAM_CTL01_RSVD1                 1
-#define BM_DRAM_CTL01_RSVD1                 0xfe
-#define BF_DRAM_CTL01_RSVD1(v)              (((v) << 1) & 0xfe)
-#define BP_DRAM_CTL01_AHB1_FIFO_TYPE_REG    0
-#define BM_DRAM_CTL01_AHB1_FIFO_TYPE_REG    0x1
-#define BF_DRAM_CTL01_AHB1_FIFO_TYPE_REG(v) (((v) << 0) & 0x1)
-
-/**
- * Register: HW_DRAM_CTL02
- * Address: 0x8
- * SCT: no
-*/
-#define HW_DRAM_CTL02                       (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x8))
-#define BP_DRAM_CTL02_RSVD4                 25
-#define BM_DRAM_CTL02_RSVD4                 0xfe000000
-#define BF_DRAM_CTL02_RSVD4(v)              (((v) << 25) & 0xfe000000)
-#define BP_DRAM_CTL02_AHB3_R_PRIORITY       24
-#define BM_DRAM_CTL02_AHB3_R_PRIORITY       0x1000000
-#define BF_DRAM_CTL02_AHB3_R_PRIORITY(v)    (((v) << 24) & 0x1000000)
-#define BP_DRAM_CTL02_RSVD3                 17
-#define BM_DRAM_CTL02_RSVD3                 0xfe0000
-#define BF_DRAM_CTL02_RSVD3(v)              (((v) << 17) & 0xfe0000)
-#define BP_DRAM_CTL02_AHB3_FIFO_TYPE_REG    16
-#define BM_DRAM_CTL02_AHB3_FIFO_TYPE_REG    0x10000
-#define BF_DRAM_CTL02_AHB3_FIFO_TYPE_REG(v) (((v) << 16) & 0x10000)
-#define BP_DRAM_CTL02_RSVD2                 9
-#define BM_DRAM_CTL02_RSVD2                 0xfe00
-#define BF_DRAM_CTL02_RSVD2(v)              (((v) << 9) & 0xfe00)
-#define BP_DRAM_CTL02_AHB2_W_PRIORITY       8
-#define BM_DRAM_CTL02_AHB2_W_PRIORITY       0x100
-#define BF_DRAM_CTL02_AHB2_W_PRIORITY(v)    (((v) << 8) & 0x100)
-#define BP_DRAM_CTL02_RSVD1                 1
-#define BM_DRAM_CTL02_RSVD1                 0xfe
-#define BF_DRAM_CTL02_RSVD1(v)              (((v) << 1) & 0xfe)
-#define BP_DRAM_CTL02_AHB2_R_PRIORITY       0
-#define BM_DRAM_CTL02_AHB2_R_PRIORITY       0x1
-#define BF_DRAM_CTL02_AHB2_R_PRIORITY(v)    (((v) << 0) & 0x1)
-
-/**
- * Register: HW_DRAM_CTL03
- * Address: 0xc
- * SCT: no
-*/
-#define HW_DRAM_CTL03                       (*(volatile unsigned long *)(REGS_DRAM_BASE + 0xc))
-#define BP_DRAM_CTL03_RSVD4                 25
-#define BM_DRAM_CTL03_RSVD4                 0xfe000000
-#define BF_DRAM_CTL03_RSVD4(v)              (((v) << 25) & 0xfe000000)
-#define BP_DRAM_CTL03_AUTO_REFRESH_MODE     24
-#define BM_DRAM_CTL03_AUTO_REFRESH_MODE     0x1000000
-#define BF_DRAM_CTL03_AUTO_REFRESH_MODE(v)  (((v) << 24) & 0x1000000)
-#define BP_DRAM_CTL03_RSVD3                 17
-#define BM_DRAM_CTL03_RSVD3                 0xfe0000
-#define BF_DRAM_CTL03_RSVD3(v)              (((v) << 17) & 0xfe0000)
-#define BP_DRAM_CTL03_AREFRESH              16
-#define BM_DRAM_CTL03_AREFRESH              0x10000
-#define BF_DRAM_CTL03_AREFRESH(v)           (((v) << 16) & 0x10000)
-#define BP_DRAM_CTL03_RSVD2                 9
-#define BM_DRAM_CTL03_RSVD2                 0xfe00
-#define BF_DRAM_CTL03_RSVD2(v)              (((v) << 9) & 0xfe00)
-#define BP_DRAM_CTL03_AP                    8
-#define BM_DRAM_CTL03_AP                    0x100
-#define BF_DRAM_CTL03_AP(v)                 (((v) << 8) & 0x100)
-#define BP_DRAM_CTL03_RSVD1                 1
-#define BM_DRAM_CTL03_RSVD1                 0xfe
-#define BF_DRAM_CTL03_RSVD1(v)              (((v) << 1) & 0xfe)
-#define BP_DRAM_CTL03_AHB3_W_PRIORITY       0
-#define BM_DRAM_CTL03_AHB3_W_PRIORITY       0x1
-#define BF_DRAM_CTL03_AHB3_W_PRIORITY(v)    (((v) << 0) & 0x1)
-
-/**
- * Register: HW_DRAM_CTL04
- * Address: 0x10
- * SCT: no
-*/
-#define HW_DRAM_CTL04                       (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x10))
-#define BP_DRAM_CTL04_RSVD4                 25
-#define BM_DRAM_CTL04_RSVD4                 0xfe000000
-#define BF_DRAM_CTL04_RSVD4(v)              (((v) << 25) & 0xfe000000)
-#define BP_DRAM_CTL04_DLL_BYPASS_MODE       24
-#define BM_DRAM_CTL04_DLL_BYPASS_MODE       0x1000000
-#define BF_DRAM_CTL04_DLL_BYPASS_MODE(v)    (((v) << 24) & 0x1000000)
-#define BP_DRAM_CTL04_RSVD3                 17
-#define BM_DRAM_CTL04_RSVD3                 0xfe0000
-#define BF_DRAM_CTL04_RSVD3(v)              (((v) << 17) & 0xfe0000)
-#define BP_DRAM_CTL04_DLLLOCKREG            16
-#define BM_DRAM_CTL04_DLLLOCKREG            0x10000
-#define BF_DRAM_CTL04_DLLLOCKREG(v)         (((v) << 16) & 0x10000)
-#define BP_DRAM_CTL04_RSVD2                 9
-#define BM_DRAM_CTL04_RSVD2                 0xfe00
-#define BF_DRAM_CTL04_RSVD2(v)              (((v) << 9) & 0xfe00)
-#define BP_DRAM_CTL04_CONCURRENTAP          8
-#define BM_DRAM_CTL04_CONCURRENTAP          0x100
-#define BF_DRAM_CTL04_CONCURRENTAP(v)       (((v) << 8) & 0x100)
-#define BP_DRAM_CTL04_RSVD1                 1
-#define BM_DRAM_CTL04_RSVD1                 0xfe
-#define BF_DRAM_CTL04_RSVD1(v)              (((v) << 1) & 0xfe)
-#define BP_DRAM_CTL04_BANK_SPLIT_EN         0
-#define BM_DRAM_CTL04_BANK_SPLIT_EN         0x1
-#define BF_DRAM_CTL04_BANK_SPLIT_EN(v)      (((v) << 0) & 0x1)
-
-/**
- * Register: HW_DRAM_CTL05
- * Address: 0x14
- * SCT: no
-*/
-#define HW_DRAM_CTL05                       (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x14))
-#define BP_DRAM_CTL05_RSVD4                 25
-#define BM_DRAM_CTL05_RSVD4                 0xfe000000
-#define BF_DRAM_CTL05_RSVD4(v)              (((v) << 25) & 0xfe000000)
-#define BP_DRAM_CTL05_INTRPTREADA           24
-#define BM_DRAM_CTL05_INTRPTREADA           0x1000000
-#define BF_DRAM_CTL05_INTRPTREADA(v)        (((v) << 24) & 0x1000000)
-#define BP_DRAM_CTL05_RSVD3                 17
-#define BM_DRAM_CTL05_RSVD3                 0xfe0000
-#define BF_DRAM_CTL05_RSVD3(v)              (((v) << 17) & 0xfe0000)
-#define BP_DRAM_CTL05_INTRPTAPBURST         16
-#define BM_DRAM_CTL05_INTRPTAPBURST         0x10000
-#define BF_DRAM_CTL05_INTRPTAPBURST(v)      (((v) << 16) & 0x10000)
-#define BP_DRAM_CTL05_RSVD2                 9
-#define BM_DRAM_CTL05_RSVD2                 0xfe00
-#define BF_DRAM_CTL05_RSVD2(v)              (((v) << 9) & 0xfe00)
-#define BP_DRAM_CTL05_FAST_WRITE            8
-#define BM_DRAM_CTL05_FAST_WRITE            0x100
-#define BF_DRAM_CTL05_FAST_WRITE(v)         (((v) << 8) & 0x100)
-#define BP_DRAM_CTL05_RSVD1                 1
-#define BM_DRAM_CTL05_RSVD1                 0xfe
-#define BF_DRAM_CTL05_RSVD1(v)              (((v) << 1) & 0xfe)
-#define BP_DRAM_CTL05_EN_LOWPOWER_MODE      0
-#define BM_DRAM_CTL05_EN_LOWPOWER_MODE      0x1
-#define BF_DRAM_CTL05_EN_LOWPOWER_MODE(v)   (((v) << 0) & 0x1)
-
-/**
- * Register: HW_DRAM_CTL06
- * Address: 0x18
- * SCT: no
-*/
-#define HW_DRAM_CTL06                   (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x18))
-#define BP_DRAM_CTL06_RSVD4             25
-#define BM_DRAM_CTL06_RSVD4             0xfe000000
-#define BF_DRAM_CTL06_RSVD4(v)          (((v) << 25) & 0xfe000000)
-#define BP_DRAM_CTL06_POWER_DOWN        24
-#define BM_DRAM_CTL06_POWER_DOWN        0x1000000
-#define BF_DRAM_CTL06_POWER_DOWN(v)     (((v) << 24) & 0x1000000)
-#define BP_DRAM_CTL06_RSVD3             17
-#define BM_DRAM_CTL06_RSVD3             0xfe0000
-#define BF_DRAM_CTL06_RSVD3(v)          (((v) << 17) & 0xfe0000)
-#define BP_DRAM_CTL06_PLACEMENT_EN      16
-#define BM_DRAM_CTL06_PLACEMENT_EN      0x10000
-#define BF_DRAM_CTL06_PLACEMENT_EN(v)   (((v) << 16) & 0x10000)
-#define BP_DRAM_CTL06_RSVD2             9
-#define BM_DRAM_CTL06_RSVD2             0xfe00
-#define BF_DRAM_CTL06_RSVD2(v)          (((v) << 9) & 0xfe00)
-#define BP_DRAM_CTL06_NO_CMD_INIT       8
-#define BM_DRAM_CTL06_NO_CMD_INIT       0x100
-#define BF_DRAM_CTL06_NO_CMD_INIT(v)    (((v) << 8) & 0x100)
-#define BP_DRAM_CTL06_RSVD1             1
-#define BM_DRAM_CTL06_RSVD1             0xfe
-#define BF_DRAM_CTL06_RSVD1(v)          (((v) << 1) & 0xfe)
-#define BP_DRAM_CTL06_INTRPTWRITEA      0
-#define BM_DRAM_CTL06_INTRPTWRITEA      0x1
-#define BF_DRAM_CTL06_INTRPTWRITEA(v)   (((v) << 0) & 0x1)
-
-/**
- * Register: HW_DRAM_CTL07
- * Address: 0x1c
- * SCT: no
-*/
-#define HW_DRAM_CTL07                       (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x1c))
-#define BP_DRAM_CTL07_RSVD4                 25
-#define BM_DRAM_CTL07_RSVD4                 0xfe000000
-#define BF_DRAM_CTL07_RSVD4(v)              (((v) << 25) & 0xfe000000)
-#define BP_DRAM_CTL07_RW_SAME_EN            24
-#define BM_DRAM_CTL07_RW_SAME_EN            0x1000000
-#define BF_DRAM_CTL07_RW_SAME_EN(v)         (((v) << 24) & 0x1000000)
-#define BP_DRAM_CTL07_RSVD3                 17
-#define BM_DRAM_CTL07_RSVD3                 0xfe0000
-#define BF_DRAM_CTL07_RSVD3(v)              (((v) << 17) & 0xfe0000)
-#define BP_DRAM_CTL07_REG_DIMM_ENABLE       16
-#define BM_DRAM_CTL07_REG_DIMM_ENABLE       0x10000
-#define BF_DRAM_CTL07_REG_DIMM_ENABLE(v)    (((v) << 16) & 0x10000)
-#define BP_DRAM_CTL07_RSVD2                 9
-#define BM_DRAM_CTL07_RSVD2                 0xfe00
-#define BF_DRAM_CTL07_RSVD2(v)              (((v) << 9) & 0xfe00)
-#define BP_DRAM_CTL07_RD2RD_TURN            8
-#define BM_DRAM_CTL07_RD2RD_TURN            0x100
-#define BF_DRAM_CTL07_RD2RD_TURN(v)         (((v) << 8) & 0x100)
-#define BP_DRAM_CTL07_RSVD1                 1
-#define BM_DRAM_CTL07_RSVD1                 0xfe
-#define BF_DRAM_CTL07_RSVD1(v)              (((v) << 1) & 0xfe)
-#define BP_DRAM_CTL07_PRIORITY_EN           0
-#define BM_DRAM_CTL07_PRIORITY_EN           0x1
-#define BF_DRAM_CTL07_PRIORITY_EN(v)        (((v) << 0) & 0x1)
-
-/**
- * Register: HW_DRAM_CTL08
- * Address: 0x20
- * SCT: no
-*/
-#define HW_DRAM_CTL08                   (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x20))
-#define BP_DRAM_CTL08_RSVD4             25
-#define BM_DRAM_CTL08_RSVD4             0xfe000000
-#define BF_DRAM_CTL08_RSVD4(v)          (((v) << 25) & 0xfe000000)
-#define BP_DRAM_CTL08_TRAS_LOCKOUT      24
-#define BM_DRAM_CTL08_TRAS_LOCKOUT      0x1000000
-#define BF_DRAM_CTL08_TRAS_LOCKOUT(v)   (((v) << 24) & 0x1000000)
-#define BP_DRAM_CTL08_RSVD3             17
-#define BM_DRAM_CTL08_RSVD3             0xfe0000
-#define BF_DRAM_CTL08_RSVD3(v)          (((v) << 17) & 0xfe0000)
-#define BP_DRAM_CTL08_START             16
-#define BM_DRAM_CTL08_START             0x10000
-#define BF_DRAM_CTL08_START(v)          (((v) << 16) & 0x10000)
-#define BP_DRAM_CTL08_RSVD2             9
-#define BM_DRAM_CTL08_RSVD2             0xfe00
-#define BF_DRAM_CTL08_RSVD2(v)          (((v) << 9) & 0xfe00)
-#define BP_DRAM_CTL08_SREFRESH          8
-#define BM_DRAM_CTL08_SREFRESH          0x100
-#define BF_DRAM_CTL08_SREFRESH(v)       (((v) << 8) & 0x100)
-#define BP_DRAM_CTL08_RSVD1             1
-#define BM_DRAM_CTL08_RSVD1             0xfe
-#define BF_DRAM_CTL08_RSVD1(v)          (((v) << 1) & 0xfe)
-#define BP_DRAM_CTL08_SDR_MODE          0
-#define BM_DRAM_CTL08_SDR_MODE          0x1
-#define BF_DRAM_CTL08_SDR_MODE(v)       (((v) << 0) & 0x1)
-
-/**
- * Register: HW_DRAM_CTL09
- * Address: 0x24
- * SCT: no
-*/
-#define HW_DRAM_CTL09                           (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x24))
-#define BP_DRAM_CTL09_RSVD4                     26
-#define BM_DRAM_CTL09_RSVD4                     0xfc000000
-#define BF_DRAM_CTL09_RSVD4(v)                  (((v) << 26) & 0xfc000000)
-#define BP_DRAM_CTL09_OUT_OF_RANGE_TYPE         24
-#define BM_DRAM_CTL09_OUT_OF_RANGE_TYPE         0x3000000
-#define BF_DRAM_CTL09_OUT_OF_RANGE_TYPE(v)      (((v) << 24) & 0x3000000)
-#define BP_DRAM_CTL09_RSVD3                     18
-#define BM_DRAM_CTL09_RSVD3                     0xfc0000
-#define BF_DRAM_CTL09_RSVD3(v)                  (((v) << 18) & 0xfc0000)
-#define BP_DRAM_CTL09_OUT_OF_RANGE_SOURCE_ID    16
-#define BM_DRAM_CTL09_OUT_OF_RANGE_SOURCE_ID    0x30000
-#define BF_DRAM_CTL09_OUT_OF_RANGE_SOURCE_ID(v) (((v) << 16) & 0x30000)
-#define BP_DRAM_CTL09_RSVD2                     9
-#define BM_DRAM_CTL09_RSVD2                     0xfe00
-#define BF_DRAM_CTL09_RSVD2(v)                  (((v) << 9) & 0xfe00)
-#define BP_DRAM_CTL09_WRITE_MODEREG             8
-#define BM_DRAM_CTL09_WRITE_MODEREG             0x100
-#define BF_DRAM_CTL09_WRITE_MODEREG(v)          (((v) << 8) & 0x100)
-#define BP_DRAM_CTL09_RSVD1                     1
-#define BM_DRAM_CTL09_RSVD1                     0xfe
-#define BF_DRAM_CTL09_RSVD1(v)                  (((v) << 1) & 0xfe)
-#define BP_DRAM_CTL09_WRITEINTERP               0
-#define BM_DRAM_CTL09_WRITEINTERP               0x1
-#define BF_DRAM_CTL09_WRITEINTERP(v)            (((v) << 0) & 0x1)
-
-/**
- * Register: HW_DRAM_CTL10
- * Address: 0x28
- * SCT: no
-*/
-#define HW_DRAM_CTL10               (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x28))
-#define BP_DRAM_CTL10_RSVD4         27
-#define BM_DRAM_CTL10_RSVD4         0xf8000000
-#define BF_DRAM_CTL10_RSVD4(v)      (((v) << 27) & 0xf8000000)
-#define BP_DRAM_CTL10_AGE_COUNT     24
-#define BM_DRAM_CTL10_AGE_COUNT     0x7000000
-#define BF_DRAM_CTL10_AGE_COUNT(v)  (((v) << 24) & 0x7000000)
-#define BP_DRAM_CTL10_RSVD3         19
-#define BM_DRAM_CTL10_RSVD3         0xf80000
-#define BF_DRAM_CTL10_RSVD3(v)      (((v) << 19) & 0xf80000)
-#define BP_DRAM_CTL10_ADDR_PINS     16
-#define BM_DRAM_CTL10_ADDR_PINS     0x70000
-#define BF_DRAM_CTL10_ADDR_PINS(v)  (((v) << 16) & 0x70000)
-#define BP_DRAM_CTL10_RSVD2         10
-#define BM_DRAM_CTL10_RSVD2         0xfc00
-#define BF_DRAM_CTL10_RSVD2(v)      (((v) << 10) & 0xfc00)
-#define BP_DRAM_CTL10_TEMRS         8
-#define BM_DRAM_CTL10_TEMRS         0x300
-#define BF_DRAM_CTL10_TEMRS(v)      (((v) << 8) & 0x300)
-#define BP_DRAM_CTL10_RSVD1         2
-#define BM_DRAM_CTL10_RSVD1         0xfc
-#define BF_DRAM_CTL10_RSVD1(v)      (((v) << 2) & 0xfc)
-#define BP_DRAM_CTL10_Q_FULLNESS    0
-#define BM_DRAM_CTL10_Q_FULLNESS    0x3
-#define BF_DRAM_CTL10_Q_FULLNESS(v) (((v) << 0) & 0x3)
-
-/**
- * Register: HW_DRAM_CTL11
- * Address: 0x2c
- * SCT: no
-*/
-#define HW_DRAM_CTL11                       (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x2c))
-#define BP_DRAM_CTL11_RSVD4                 27
-#define BM_DRAM_CTL11_RSVD4                 0xf8000000
-#define BF_DRAM_CTL11_RSVD4(v)              (((v) << 27) & 0xf8000000)
-#define BP_DRAM_CTL11_MAX_CS_REG            24
-#define BM_DRAM_CTL11_MAX_CS_REG            0x7000000
-#define BF_DRAM_CTL11_MAX_CS_REG(v)         (((v) << 24) & 0x7000000)
-#define BP_DRAM_CTL11_RSVD3                 19
-#define BM_DRAM_CTL11_RSVD3                 0xf80000
-#define BF_DRAM_CTL11_RSVD3(v)              (((v) << 19) & 0xf80000)
-#define BP_DRAM_CTL11_COMMAND_AGE_COUNT     16
-#define BM_DRAM_CTL11_COMMAND_AGE_COUNT     0x70000
-#define BF_DRAM_CTL11_COMMAND_AGE_COUNT(v)  (((v) << 16) & 0x70000)
-#define BP_DRAM_CTL11_RSVD2                 11
-#define BM_DRAM_CTL11_RSVD2                 0xf800
-#define BF_DRAM_CTL11_RSVD2(v)              (((v) << 11) & 0xf800)
-#define BP_DRAM_CTL11_COLUMN_SIZE           8
-#define BM_DRAM_CTL11_COLUMN_SIZE           0x700
-#define BF_DRAM_CTL11_COLUMN_SIZE(v)        (((v) << 8) & 0x700)
-#define BP_DRAM_CTL11_RSVD1                 3
-#define BM_DRAM_CTL11_RSVD1                 0xf8
-#define BF_DRAM_CTL11_RSVD1(v)              (((v) << 3) & 0xf8)
-#define BP_DRAM_CTL11_CASLAT                0
-#define BM_DRAM_CTL11_CASLAT                0x7
-#define BF_DRAM_CTL11_CASLAT(v)             (((v) << 0) & 0x7)
-
-/**
- * Register: HW_DRAM_CTL12
- * Address: 0x30
- * SCT: no
-*/
-#define HW_DRAM_CTL12               (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x30))
-#define BP_DRAM_CTL12_RSVD3         27
-#define BM_DRAM_CTL12_RSVD3         0xf8000000
-#define BF_DRAM_CTL12_RSVD3(v)      (((v) << 27) & 0xf8000000)
-#define BP_DRAM_CTL12_TWR_INT       24
-#define BM_DRAM_CTL12_TWR_INT       0x7000000
-#define BF_DRAM_CTL12_TWR_INT(v)    (((v) << 24) & 0x7000000)
-#define BP_DRAM_CTL12_RSVD2         19
-#define BM_DRAM_CTL12_RSVD2         0xf80000
-#define BF_DRAM_CTL12_RSVD2(v)      (((v) << 19) & 0xf80000)
-#define BP_DRAM_CTL12_TRRD          16
-#define BM_DRAM_CTL12_TRRD          0x70000
-#define BF_DRAM_CTL12_TRRD(v)       (((v) << 16) & 0x70000)
-#define BP_DRAM_CTL12_OBSOLETE      8
-#define BM_DRAM_CTL12_OBSOLETE      0xff00
-#define BF_DRAM_CTL12_OBSOLETE(v)   (((v) << 8) & 0xff00)
-#define BP_DRAM_CTL12_RSVD1         3
-#define BM_DRAM_CTL12_RSVD1         0xf8
-#define BF_DRAM_CTL12_RSVD1(v)      (((v) << 3) & 0xf8)
-#define BP_DRAM_CTL12_TCKE          0
-#define BM_DRAM_CTL12_TCKE          0x7
-#define BF_DRAM_CTL12_TCKE(v)       (((v) << 0) & 0x7)
-
-/**
- * Register: HW_DRAM_CTL13
- * Address: 0x34
- * SCT: no
-*/
-#define HW_DRAM_CTL13                       (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x34))
-#define BP_DRAM_CTL13_RSVD4                 28
-#define BM_DRAM_CTL13_RSVD4                 0xf0000000
-#define BF_DRAM_CTL13_RSVD4(v)              (((v) << 28) & 0xf0000000)
-#define BP_DRAM_CTL13_CASLAT_LIN_GATE       24
-#define BM_DRAM_CTL13_CASLAT_LIN_GATE       0xf000000
-#define BF_DRAM_CTL13_CASLAT_LIN_GATE(v)    (((v) << 24) & 0xf000000)
-#define BP_DRAM_CTL13_RSVD3                 20
-#define BM_DRAM_CTL13_RSVD3                 0xf00000
-#define BF_DRAM_CTL13_RSVD3(v)              (((v) << 20) & 0xf00000)
-#define BP_DRAM_CTL13_CASLAT_LIN            16
-#define BM_DRAM_CTL13_CASLAT_LIN            0xf0000
-#define BF_DRAM_CTL13_CASLAT_LIN(v)         (((v) << 16) & 0xf0000)
-#define BP_DRAM_CTL13_RSVD2                 12
-#define BM_DRAM_CTL13_RSVD2                 0xf000
-#define BF_DRAM_CTL13_RSVD2(v)              (((v) << 12) & 0xf000)
-#define BP_DRAM_CTL13_APREBIT               8
-#define BM_DRAM_CTL13_APREBIT               0xf00
-#define BF_DRAM_CTL13_APREBIT(v)            (((v) << 8) & 0xf00)
-#define BP_DRAM_CTL13_RSVD1                 3
-#define BM_DRAM_CTL13_RSVD1                 0xf8
-#define BF_DRAM_CTL13_RSVD1(v)              (((v) << 3) & 0xf8)
-#define BP_DRAM_CTL13_TWTR                  0
-#define BM_DRAM_CTL13_TWTR                  0x7
-#define BF_DRAM_CTL13_TWTR(v)               (((v) << 0) & 0x7)
-
-/**
- * Register: HW_DRAM_CTL14
- * Address: 0x38
- * SCT: no
-*/
-#define HW_DRAM_CTL14                               (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x38))
-#define BP_DRAM_CTL14_RSVD4                         28
-#define BM_DRAM_CTL14_RSVD4                         0xf0000000
-#define BF_DRAM_CTL14_RSVD4(v)                      (((v) << 28) & 0xf0000000)
-#define BP_DRAM_CTL14_MAX_COL_REG                   24
-#define BM_DRAM_CTL14_MAX_COL_REG                   0xf000000
-#define BF_DRAM_CTL14_MAX_COL_REG(v)                (((v) << 24) & 0xf000000)
-#define BP_DRAM_CTL14_RSVD3                         20
-#define BM_DRAM_CTL14_RSVD3                         0xf00000
-#define BF_DRAM_CTL14_RSVD3(v)                      (((v) << 20) & 0xf00000)
-#define BP_DRAM_CTL14_LOWPOWER_REFRESH_ENABLE       16
-#define BM_DRAM_CTL14_LOWPOWER_REFRESH_ENABLE       0xf0000
-#define BF_DRAM_CTL14_LOWPOWER_REFRESH_ENABLE(v)    (((v) << 16) & 0xf0000)
-#define BP_DRAM_CTL14_RSVD2                         12
-#define BM_DRAM_CTL14_RSVD2                         0xf000
-#define BF_DRAM_CTL14_RSVD2(v)                      (((v) << 12) & 0xf000)
-#define BP_DRAM_CTL14_INITAREF                      8
-#define BM_DRAM_CTL14_INITAREF                      0xf00
-#define BF_DRAM_CTL14_INITAREF(v)                   (((v) << 8) & 0xf00)
-#define BP_DRAM_CTL14_RSVD1                         4
-#define BM_DRAM_CTL14_RSVD1                         0xf0
-#define BF_DRAM_CTL14_RSVD1(v)                      (((v) << 4) & 0xf0)
-#define BP_DRAM_CTL14_CS_MAP                        0
-#define BM_DRAM_CTL14_CS_MAP                        0xf
-#define BF_DRAM_CTL14_CS_MAP(v)                     (((v) << 0) & 0xf)
-
-/**
- * Register: HW_DRAM_CTL15
- * Address: 0x3c
- * SCT: no
-*/
-#define HW_DRAM_CTL15                   (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x3c))
-#define BP_DRAM_CTL15_RSVD4             28
-#define BM_DRAM_CTL15_RSVD4             0xf0000000
-#define BF_DRAM_CTL15_RSVD4(v)          (((v) << 28) & 0xf0000000)
-#define BP_DRAM_CTL15_TRP               24
-#define BM_DRAM_CTL15_TRP               0xf000000
-#define BF_DRAM_CTL15_TRP(v)            (((v) << 24) & 0xf000000)
-#define BP_DRAM_CTL15_RSVD3             20
-#define BM_DRAM_CTL15_RSVD3             0xf00000
-#define BF_DRAM_CTL15_RSVD3(v)          (((v) << 20) & 0xf00000)
-#define BP_DRAM_CTL15_TDAL              16
-#define BM_DRAM_CTL15_TDAL              0xf0000
-#define BF_DRAM_CTL15_TDAL(v)           (((v) << 16) & 0xf0000)
-#define BP_DRAM_CTL15_RSVD2             12
-#define BM_DRAM_CTL15_RSVD2             0xf000
-#define BF_DRAM_CTL15_RSVD2(v)          (((v) << 12) & 0xf000)
-#define BP_DRAM_CTL15_PORT_BUSY         8
-#define BM_DRAM_CTL15_PORT_BUSY         0xf00
-#define BF_DRAM_CTL15_PORT_BUSY(v)      (((v) << 8) & 0xf00)
-#define BP_DRAM_CTL15_RSVD1             4
-#define BM_DRAM_CTL15_RSVD1             0xf0
-#define BF_DRAM_CTL15_RSVD1(v)          (((v) << 4) & 0xf0)
-#define BP_DRAM_CTL15_MAX_ROW_REG       0
-#define BM_DRAM_CTL15_MAX_ROW_REG       0xf
-#define BF_DRAM_CTL15_MAX_ROW_REG(v)    (((v) << 0) & 0xf)
-
-/**
- * Register: HW_DRAM_CTL16
- * Address: 0x40
- * SCT: no
-*/
-#define HW_DRAM_CTL16                           (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x40))
-#define BP_DRAM_CTL16_RSVD4                     29
-#define BM_DRAM_CTL16_RSVD4                     0xe0000000
-#define BF_DRAM_CTL16_RSVD4(v)                  (((v) << 29) & 0xe0000000)
-#define BP_DRAM_CTL16_TMRD                      24
-#define BM_DRAM_CTL16_TMRD                      0x1f000000
-#define BF_DRAM_CTL16_TMRD(v)                   (((v) << 24) & 0x1f000000)
-#define BP_DRAM_CTL16_RSVD3                     21
-#define BM_DRAM_CTL16_RSVD3                     0xe00000
-#define BF_DRAM_CTL16_RSVD3(v)                  (((v) << 21) & 0xe00000)
-#define BP_DRAM_CTL16_LOWPOWER_CONTROL          16
-#define BM_DRAM_CTL16_LOWPOWER_CONTROL          0x1f0000
-#define BF_DRAM_CTL16_LOWPOWER_CONTROL(v)       (((v) << 16) & 0x1f0000)
-#define BP_DRAM_CTL16_RSVD2                     13
-#define BM_DRAM_CTL16_RSVD2                     0xe000
-#define BF_DRAM_CTL16_RSVD2(v)                  (((v) << 13) & 0xe000)
-#define BP_DRAM_CTL16_LOWPOWER_AUTO_ENABLE      8
-#define BM_DRAM_CTL16_LOWPOWER_AUTO_ENABLE      0x1f00
-#define BF_DRAM_CTL16_LOWPOWER_AUTO_ENABLE(v)   (((v) << 8) & 0x1f00)
-#define BP_DRAM_CTL16_RSVD1                     4
-#define BM_DRAM_CTL16_RSVD1                     0xf0
-#define BF_DRAM_CTL16_RSVD1(v)                  (((v) << 4) & 0xf0)
-#define BP_DRAM_CTL16_INT_ACK                   0
-#define BM_DRAM_CTL16_INT_ACK                   0xf
-#define BF_DRAM_CTL16_INT_ACK(v)                (((v) << 0) & 0xf)
-
-/**
- * Register: HW_DRAM_CTL17
- * Address: 0x44
- * SCT: no
-*/
-#define HW_DRAM_CTL17                       (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x44))
-#define BP_DRAM_CTL17_DLL_START_POINT       24
-#define BM_DRAM_CTL17_DLL_START_POINT       0xff000000
-#define BF_DRAM_CTL17_DLL_START_POINT(v)    (((v) << 24) & 0xff000000)
-#define BP_DRAM_CTL17_DLL_LOCK              16
-#define BM_DRAM_CTL17_DLL_LOCK              0xff0000
-#define BF_DRAM_CTL17_DLL_LOCK(v)           (((v) << 16) & 0xff0000)
-#define BP_DRAM_CTL17_DLL_INCREMENT         8
-#define BM_DRAM_CTL17_DLL_INCREMENT         0xff00
-#define BF_DRAM_CTL17_DLL_INCREMENT(v)      (((v) << 8) & 0xff00)
-#define BP_DRAM_CTL17_RSVD1                 5
-#define BM_DRAM_CTL17_RSVD1                 0xe0
-#define BF_DRAM_CTL17_RSVD1(v)              (((v) << 5) & 0xe0)
-#define BP_DRAM_CTL17_TRC                   0
-#define BM_DRAM_CTL17_TRC                   0x1f
-#define BF_DRAM_CTL17_TRC(v)                (((v) << 0) & 0x1f)
-
-/**
- * Register: HW_DRAM_CTL18
- * Address: 0x48
- * SCT: no
-*/
-#define HW_DRAM_CTL18                       (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x48))
-#define BP_DRAM_CTL18_RSVD4                 31
-#define BM_DRAM_CTL18_RSVD4                 0x80000000
-#define BF_DRAM_CTL18_RSVD4(v)              (((v) << 31) & 0x80000000)
-#define BP_DRAM_CTL18_DLL_DQS_DELAY_1       24
-#define BM_DRAM_CTL18_DLL_DQS_DELAY_1       0x7f000000
-#define BF_DRAM_CTL18_DLL_DQS_DELAY_1(v)    (((v) << 24) & 0x7f000000)
-#define BP_DRAM_CTL18_RSVD3                 23
-#define BM_DRAM_CTL18_RSVD3                 0x800000
-#define BF_DRAM_CTL18_RSVD3(v)              (((v) << 23) & 0x800000)
-#define BP_DRAM_CTL18_DLL_DQS_DELAY_0       16
-#define BM_DRAM_CTL18_DLL_DQS_DELAY_0       0x7f0000
-#define BF_DRAM_CTL18_DLL_DQS_DELAY_0(v)    (((v) << 16) & 0x7f0000)
-#define BP_DRAM_CTL18_RSVD2                 13
-#define BM_DRAM_CTL18_RSVD2                 0xe000
-#define BF_DRAM_CTL18_RSVD2(v)              (((v) << 13) & 0xe000)
-#define BP_DRAM_CTL18_INT_STATUS            8
-#define BM_DRAM_CTL18_INT_STATUS            0x1f00
-#define BF_DRAM_CTL18_INT_STATUS(v)         (((v) << 8) & 0x1f00)
-#define BP_DRAM_CTL18_RSVD1                 5
-#define BM_DRAM_CTL18_RSVD1                 0xe0
-#define BF_DRAM_CTL18_RSVD1(v)              (((v) << 5) & 0xe0)
-#define BP_DRAM_CTL18_INT_MASK              0
-#define BM_DRAM_CTL18_INT_MASK              0x1f
-#define BF_DRAM_CTL18_INT_MASK(v)           (((v) << 0) & 0x1f)
-
-/**
- * Register: HW_DRAM_CTL19
- * Address: 0x4c
- * SCT: no
-*/
-#define HW_DRAM_CTL19                           (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x4c))
-#define BP_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS      24
-#define BM_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS      0xff000000
-#define BF_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS(v)   (((v) << 24) & 0xff000000)
-#define BP_DRAM_CTL19_RSVD1                     23
-#define BM_DRAM_CTL19_RSVD1                     0x800000
-#define BF_DRAM_CTL19_RSVD1(v)                  (((v) << 23) & 0x800000)
-#define BP_DRAM_CTL19_DQS_OUT_SHIFT             16
-#define BM_DRAM_CTL19_DQS_OUT_SHIFT             0x7f0000
-#define BF_DRAM_CTL19_DQS_OUT_SHIFT(v)          (((v) << 16) & 0x7f0000)
-#define BP_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1    8
-#define BM_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1    0xff00
-#define BF_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1(v) (((v) << 8) & 0xff00)
-#define BP_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0    0
-#define BM_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0    0xff
-#define BF_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0(v) (((v) << 0) & 0xff)
-
-/**
- * Register: HW_DRAM_CTL20
- * Address: 0x50
- * SCT: no
-*/
-#define HW_DRAM_CTL20                           (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x50))
-#define BP_DRAM_CTL20_TRCD_INT                  24
-#define BM_DRAM_CTL20_TRCD_INT                  0xff000000
-#define BF_DRAM_CTL20_TRCD_INT(v)               (((v) << 24) & 0xff000000)
-#define BP_DRAM_CTL20_TRAS_MIN                  16
-#define BM_DRAM_CTL20_TRAS_MIN                  0xff0000
-#define BF_DRAM_CTL20_TRAS_MIN(v)               (((v) << 16) & 0xff0000)
-#define BP_DRAM_CTL20_WR_DQS_SHIFT_BYPASS       8
-#define BM_DRAM_CTL20_WR_DQS_SHIFT_BYPASS       0xff00
-#define BF_DRAM_CTL20_WR_DQS_SHIFT_BYPASS(v)    (((v) << 8) & 0xff00)
-#define BP_DRAM_CTL20_RSVD1                     7
-#define BM_DRAM_CTL20_RSVD1                     0x80
-#define BF_DRAM_CTL20_RSVD1(v)                  (((v) << 7) & 0x80)
-#define BP_DRAM_CTL20_WR_DQS_SHIFT              0
-#define BM_DRAM_CTL20_WR_DQS_SHIFT              0x7f
-#define BF_DRAM_CTL20_WR_DQS_SHIFT(v)           (((v) << 0) & 0x7f)
-
-/**
- * Register: HW_DRAM_CTL21
- * Address: 0x54
- * SCT: no
-*/
-#define HW_DRAM_CTL21                           (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x54))
-#define BP_DRAM_CTL21_OBSOLETE                  24
-#define BM_DRAM_CTL21_OBSOLETE                  0xff000000
-#define BF_DRAM_CTL21_OBSOLETE(v)               (((v) << 24) & 0xff000000)
-#define BP_DRAM_CTL21_RSVD1                     18
-#define BM_DRAM_CTL21_RSVD1                     0xfc0000
-#define BF_DRAM_CTL21_RSVD1(v)                  (((v) << 18) & 0xfc0000)
-#define BP_DRAM_CTL21_OUT_OF_RANGE_LENGTH       8
-#define BM_DRAM_CTL21_OUT_OF_RANGE_LENGTH       0x3ff00
-#define BF_DRAM_CTL21_OUT_OF_RANGE_LENGTH(v)    (((v) << 8) & 0x3ff00)
-#define BP_DRAM_CTL21_TRFC                      0
-#define BM_DRAM_CTL21_TRFC                      0xff
-#define BF_DRAM_CTL21_TRFC(v)                   (((v) << 0) & 0xff)
-
-/**
- * Register: HW_DRAM_CTL22
- * Address: 0x58
- * SCT: no
-*/
-#define HW_DRAM_CTL22               (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x58))
-#define BP_DRAM_CTL22_RSVD2         27
-#define BM_DRAM_CTL22_RSVD2         0xf8000000
-#define BF_DRAM_CTL22_RSVD2(v)      (((v) << 27) & 0xf8000000)
-#define BP_DRAM_CTL22_AHB0_WRCNT    16
-#define BM_DRAM_CTL22_AHB0_WRCNT    0x7ff0000
-#define BF_DRAM_CTL22_AHB0_WRCNT(v) (((v) << 16) & 0x7ff0000)
-#define BP_DRAM_CTL22_RSVD1         11
-#define BM_DRAM_CTL22_RSVD1         0xf800
-#define BF_DRAM_CTL22_RSVD1(v)      (((v) << 11) & 0xf800)
-#define BP_DRAM_CTL22_AHB0_RDCNT    0
-#define BM_DRAM_CTL22_AHB0_RDCNT    0x7ff
-#define BF_DRAM_CTL22_AHB0_RDCNT(v) (((v) << 0) & 0x7ff)
-
-/**
- * Register: HW_DRAM_CTL23
- * Address: 0x5c
- * SCT: no
-*/
-#define HW_DRAM_CTL23               (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x5c))
-#define BP_DRAM_CTL23_RSVD2         27
-#define BM_DRAM_CTL23_RSVD2         0xf8000000
-#define BF_DRAM_CTL23_RSVD2(v)      (((v) << 27) & 0xf8000000)
-#define BP_DRAM_CTL23_AHB1_WRCNT    16
-#define BM_DRAM_CTL23_AHB1_WRCNT    0x7ff0000
-#define BF_DRAM_CTL23_AHB1_WRCNT(v) (((v) << 16) & 0x7ff0000)
-#define BP_DRAM_CTL23_RSVD1         11
-#define BM_DRAM_CTL23_RSVD1         0xf800
-#define BF_DRAM_CTL23_RSVD1(v)      (((v) << 11) & 0xf800)
-#define BP_DRAM_CTL23_AHB1_RDCNT    0
-#define BM_DRAM_CTL23_AHB1_RDCNT    0x7ff
-#define BF_DRAM_CTL23_AHB1_RDCNT(v) (((v) << 0) & 0x7ff)
-
-/**
- * Register: HW_DRAM_CTL24
- * Address: 0x60
- * SCT: no
-*/
-#define HW_DRAM_CTL24               (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x60))
-#define BP_DRAM_CTL24_RSVD2         27
-#define BM_DRAM_CTL24_RSVD2         0xf8000000
-#define BF_DRAM_CTL24_RSVD2(v)      (((v) << 27) & 0xf8000000)
-#define BP_DRAM_CTL24_AHB2_WRCNT    16
-#define BM_DRAM_CTL24_AHB2_WRCNT    0x7ff0000
-#define BF_DRAM_CTL24_AHB2_WRCNT(v) (((v) << 16) & 0x7ff0000)
-#define BP_DRAM_CTL24_RSVD1         11
-#define BM_DRAM_CTL24_RSVD1         0xf800
-#define BF_DRAM_CTL24_RSVD1(v)      (((v) << 11) & 0xf800)
-#define BP_DRAM_CTL24_AHB2_RDCNT    0
-#define BM_DRAM_CTL24_AHB2_RDCNT    0x7ff
-#define BF_DRAM_CTL24_AHB2_RDCNT(v) (((v) << 0) & 0x7ff)
-
-/**
- * Register: HW_DRAM_CTL25
- * Address: 0x64
- * SCT: no
-*/
-#define HW_DRAM_CTL25               (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x64))
-#define BP_DRAM_CTL25_RSVD2         27
-#define BM_DRAM_CTL25_RSVD2         0xf8000000
-#define BF_DRAM_CTL25_RSVD2(v)      (((v) << 27) & 0xf8000000)
-#define BP_DRAM_CTL25_AHB3_WRCNT    16
-#define BM_DRAM_CTL25_AHB3_WRCNT    0x7ff0000
-#define BF_DRAM_CTL25_AHB3_WRCNT(v) (((v) << 16) & 0x7ff0000)
-#define BP_DRAM_CTL25_RSVD1         11
-#define BM_DRAM_CTL25_RSVD1         0xf800
-#define BF_DRAM_CTL25_RSVD1(v)      (((v) << 11) & 0xf800)
-#define BP_DRAM_CTL25_AHB3_RDCNT    0
-#define BM_DRAM_CTL25_AHB3_RDCNT    0x7ff
-#define BF_DRAM_CTL25_AHB3_RDCNT(v) (((v) << 0) & 0x7ff)
-
-/**
- * Register: HW_DRAM_CTL26
- * Address: 0x68
- * SCT: no
-*/
-#define HW_DRAM_CTL26               (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x68))
-#define BP_DRAM_CTL26_OBSOLETE      16
-#define BM_DRAM_CTL26_OBSOLETE      0xffff0000
-#define BF_DRAM_CTL26_OBSOLETE(v)   (((v) << 16) & 0xffff0000)
-#define BP_DRAM_CTL26_RSVD1         12
-#define BM_DRAM_CTL26_RSVD1         0xf000
-#define BF_DRAM_CTL26_RSVD1(v)      (((v) << 12) & 0xf000)
-#define BP_DRAM_CTL26_TREF          0
-#define BM_DRAM_CTL26_TREF          0xfff
-#define BF_DRAM_CTL26_TREF(v)       (((v) << 0) & 0xfff)
-
-/**
- * Register: HW_DRAM_CTL27
- * Address: 0x6c
- * SCT: no
-*/
-#define HW_DRAM_CTL27               (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x6c))
-#define BP_DRAM_CTL27_OBSOLETE      0
-#define BM_DRAM_CTL27_OBSOLETE      0xffffffff
-#define BF_DRAM_CTL27_OBSOLETE(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DRAM_CTL28
- * Address: 0x70
- * SCT: no
-*/
-#define HW_DRAM_CTL28               (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x70))
-#define BP_DRAM_CTL28_OBSOLETE      0
-#define BM_DRAM_CTL28_OBSOLETE      0xffffffff
-#define BF_DRAM_CTL28_OBSOLETE(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DRAM_CTL29
- * Address: 0x74
- * SCT: no
-*/
-#define HW_DRAM_CTL29                           (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x74))
-#define BP_DRAM_CTL29_LOWPOWER_INTERNAL_CNT     16
-#define BM_DRAM_CTL29_LOWPOWER_INTERNAL_CNT     0xffff0000
-#define BF_DRAM_CTL29_LOWPOWER_INTERNAL_CNT(v)  (((v) << 16) & 0xffff0000)
-#define BP_DRAM_CTL29_LOWPOWER_EXTERNAL_CNT     0
-#define BM_DRAM_CTL29_LOWPOWER_EXTERNAL_CNT     0xffff
-#define BF_DRAM_CTL29_LOWPOWER_EXTERNAL_CNT(v)  (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_DRAM_CTL30
- * Address: 0x78
- * SCT: no
-*/
-#define HW_DRAM_CTL30                               (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x78))
-#define BP_DRAM_CTL30_LOWPOWER_REFRESH_HOLD         16
-#define BM_DRAM_CTL30_LOWPOWER_REFRESH_HOLD         0xffff0000
-#define BF_DRAM_CTL30_LOWPOWER_REFRESH_HOLD(v)      (((v) << 16) & 0xffff0000)
-#define BP_DRAM_CTL30_LOWPOWER_POWER_DOWN_CNT       0
-#define BM_DRAM_CTL30_LOWPOWER_POWER_DOWN_CNT       0xffff
-#define BF_DRAM_CTL30_LOWPOWER_POWER_DOWN_CNT(v)    (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_DRAM_CTL31
- * Address: 0x7c
- * SCT: no
-*/
-#define HW_DRAM_CTL31                               (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x7c))
-#define BP_DRAM_CTL31_TDLL                          16
-#define BM_DRAM_CTL31_TDLL                          0xffff0000
-#define BF_DRAM_CTL31_TDLL(v)                       (((v) << 16) & 0xffff0000)
-#define BP_DRAM_CTL31_LOWPOWER_SELF_REFRESH_CNT     0
-#define BM_DRAM_CTL31_LOWPOWER_SELF_REFRESH_CNT     0xffff
-#define BF_DRAM_CTL31_LOWPOWER_SELF_REFRESH_CNT(v)  (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_DRAM_CTL32
- * Address: 0x80
- * SCT: no
-*/
-#define HW_DRAM_CTL32               (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x80))
-#define BP_DRAM_CTL32_TXSNR         16
-#define BM_DRAM_CTL32_TXSNR         0xffff0000
-#define BF_DRAM_CTL32_TXSNR(v)      (((v) << 16) & 0xffff0000)
-#define BP_DRAM_CTL32_TRAS_MAX      0
-#define BM_DRAM_CTL32_TRAS_MAX      0xffff
-#define BF_DRAM_CTL32_TRAS_MAX(v)   (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_DRAM_CTL33
- * Address: 0x84
- * SCT: no
-*/
-#define HW_DRAM_CTL33               (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x84))
-#define BP_DRAM_CTL33_VERSION       16
-#define BM_DRAM_CTL33_VERSION       0xffff0000
-#define BF_DRAM_CTL33_VERSION(v)    (((v) << 16) & 0xffff0000)
-#define BP_DRAM_CTL33_TXSR          0
-#define BM_DRAM_CTL33_TXSR          0xffff
-#define BF_DRAM_CTL33_TXSR(v)       (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_DRAM_CTL34
- * Address: 0x88
- * SCT: no
-*/
-#define HW_DRAM_CTL34           (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x88))
-#define BP_DRAM_CTL34_RSVD1     24
-#define BM_DRAM_CTL34_RSVD1     0xff000000
-#define BF_DRAM_CTL34_RSVD1(v)  (((v) << 24) & 0xff000000)
-#define BP_DRAM_CTL34_TINIT     0
-#define BM_DRAM_CTL34_TINIT     0xffffff
-#define BF_DRAM_CTL34_TINIT(v)  (((v) << 0) & 0xffffff)
-
-/**
- * Register: HW_DRAM_CTL35
- * Address: 0x8c
- * SCT: no
-*/
-#define HW_DRAM_CTL35                       (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x8c))
-#define BP_DRAM_CTL35_RSVD1                 31
-#define BM_DRAM_CTL35_RSVD1                 0x80000000
-#define BF_DRAM_CTL35_RSVD1(v)              (((v) << 31) & 0x80000000)
-#define BP_DRAM_CTL35_OUT_OF_RANGE_ADDR     0
-#define BM_DRAM_CTL35_OUT_OF_RANGE_ADDR     0x7fffffff
-#define BF_DRAM_CTL35_OUT_OF_RANGE_ADDR(v)  (((v) << 0) & 0x7fffffff)
-
-/**
- * Register: HW_DRAM_CTL36
- * Address: 0x90
- * SCT: no
-*/
-#define HW_DRAM_CTL36                           (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x90))
-#define BP_DRAM_CTL36_RSVD4                     25
-#define BM_DRAM_CTL36_RSVD4                     0xfe000000
-#define BF_DRAM_CTL36_RSVD4(v)                  (((v) << 25) & 0xfe000000)
-#define BP_DRAM_CTL36_PWRUP_SREFRESH_EXIT       24
-#define BM_DRAM_CTL36_PWRUP_SREFRESH_EXIT       0x1000000
-#define BF_DRAM_CTL36_PWRUP_SREFRESH_EXIT(v)    (((v) << 24) & 0x1000000)
-#define BP_DRAM_CTL36_RSVD3                     17
-#define BM_DRAM_CTL36_RSVD3                     0xfe0000
-#define BF_DRAM_CTL36_RSVD3(v)                  (((v) << 17) & 0xfe0000)
-#define BP_DRAM_CTL36_ENABLE_QUICK_SREFRESH     16
-#define BM_DRAM_CTL36_ENABLE_QUICK_SREFRESH     0x10000
-#define BF_DRAM_CTL36_ENABLE_QUICK_SREFRESH(v)  (((v) << 16) & 0x10000)
-#define BP_DRAM_CTL36_RSVD2                     9
-#define BM_DRAM_CTL36_RSVD2                     0xfe00
-#define BF_DRAM_CTL36_RSVD2(v)                  (((v) << 9) & 0xfe00)
-#define BP_DRAM_CTL36_BUS_SHARE_ENABLE          8
-#define BM_DRAM_CTL36_BUS_SHARE_ENABLE          0x100
-#define BF_DRAM_CTL36_BUS_SHARE_ENABLE(v)       (((v) << 8) & 0x100)
-#define BP_DRAM_CTL36_RSVD1                     1
-#define BM_DRAM_CTL36_RSVD1                     0xfe
-#define BF_DRAM_CTL36_RSVD1(v)                  (((v) << 1) & 0xfe)
-#define BP_DRAM_CTL36_ACTIVE_AGING              0
-#define BM_DRAM_CTL36_ACTIVE_AGING              0x1
-#define BF_DRAM_CTL36_ACTIVE_AGING(v)           (((v) << 0) & 0x1)
-
-/**
- * Register: HW_DRAM_CTL37
- * Address: 0x94
- * SCT: no
-*/
-#define HW_DRAM_CTL37                       (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x94))
-#define BP_DRAM_CTL37_OBSOLETE              24
-#define BM_DRAM_CTL37_OBSOLETE              0xff000000
-#define BF_DRAM_CTL37_OBSOLETE(v)           (((v) << 24) & 0xff000000)
-#define BP_DRAM_CTL37_RSVD2                 18
-#define BM_DRAM_CTL37_RSVD2                 0xfc0000
-#define BF_DRAM_CTL37_RSVD2(v)              (((v) << 18) & 0xfc0000)
-#define BP_DRAM_CTL37_BUS_SHARE_TIMEOUT     8
-#define BM_DRAM_CTL37_BUS_SHARE_TIMEOUT     0x3ff00
-#define BF_DRAM_CTL37_BUS_SHARE_TIMEOUT(v)  (((v) << 8) & 0x3ff00)
-#define BP_DRAM_CTL37_RSVD1                 1
-#define BM_DRAM_CTL37_RSVD1                 0xfe
-#define BF_DRAM_CTL37_RSVD1(v)              (((v) << 1) & 0xfe)
-#define BP_DRAM_CTL37_TREF_ENABLE           0
-#define BM_DRAM_CTL37_TREF_ENABLE           0x1
-#define BF_DRAM_CTL37_TREF_ENABLE(v)        (((v) << 0) & 0x1)
-
-/**
- * Register: HW_DRAM_CTL38
- * Address: 0x98
- * SCT: no
-*/
-#define HW_DRAM_CTL38                   (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x98))
-#define BP_DRAM_CTL38_RSVD2             29
-#define BM_DRAM_CTL38_RSVD2             0xe0000000
-#define BF_DRAM_CTL38_RSVD2(v)          (((v) << 29) & 0xe0000000)
-#define BP_DRAM_CTL38_EMRS2_DATA_0      16
-#define BM_DRAM_CTL38_EMRS2_DATA_0      0x1fff0000
-#define BF_DRAM_CTL38_EMRS2_DATA_0(v)   (((v) << 16) & 0x1fff0000)
-#define BP_DRAM_CTL38_RSVD1             13
-#define BM_DRAM_CTL38_RSVD1             0xe000
-#define BF_DRAM_CTL38_RSVD1(v)          (((v) << 13) & 0xe000)
-#define BP_DRAM_CTL38_EMRS1_DATA        0
-#define BM_DRAM_CTL38_EMRS1_DATA        0x1fff
-#define BF_DRAM_CTL38_EMRS1_DATA(v)     (((v) << 0) & 0x1fff)
-
-/**
- * Register: HW_DRAM_CTL39
- * Address: 0x9c
- * SCT: no
-*/
-#define HW_DRAM_CTL39                   (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x9c))
-#define BP_DRAM_CTL39_RSVD2             29
-#define BM_DRAM_CTL39_RSVD2             0xe0000000
-#define BF_DRAM_CTL39_RSVD2(v)          (((v) << 29) & 0xe0000000)
-#define BP_DRAM_CTL39_EMRS2_DATA_2      16
-#define BM_DRAM_CTL39_EMRS2_DATA_2      0x1fff0000
-#define BF_DRAM_CTL39_EMRS2_DATA_2(v)   (((v) << 16) & 0x1fff0000)
-#define BP_DRAM_CTL39_RSVD1             13
-#define BM_DRAM_CTL39_RSVD1             0xe000
-#define BF_DRAM_CTL39_RSVD1(v)          (((v) << 13) & 0xe000)
-#define BP_DRAM_CTL39_EMRS2_DATA_1      0
-#define BM_DRAM_CTL39_EMRS2_DATA_1      0x1fff
-#define BF_DRAM_CTL39_EMRS2_DATA_1(v)   (((v) << 0) & 0x1fff)
-
-/**
- * Register: HW_DRAM_CTL40
- * Address: 0xa0
- * SCT: no
-*/
-#define HW_DRAM_CTL40                   (*(volatile unsigned long *)(REGS_DRAM_BASE + 0xa0))
-#define BP_DRAM_CTL40_TPDEX             16
-#define BM_DRAM_CTL40_TPDEX             0xffff0000
-#define BF_DRAM_CTL40_TPDEX(v)          (((v) << 16) & 0xffff0000)
-#define BP_DRAM_CTL40_RSVD1             13
-#define BM_DRAM_CTL40_RSVD1             0xe000
-#define BF_DRAM_CTL40_RSVD1(v)          (((v) << 13) & 0xe000)
-#define BP_DRAM_CTL40_EMRS2_DATA_3      0
-#define BM_DRAM_CTL40_EMRS2_DATA_3      0x1fff
-#define BF_DRAM_CTL40_EMRS2_DATA_3(v)   (((v) << 0) & 0x1fff)
-
-#endif /* __HEADERGEN__IMX233__DRAM__H__ */
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-dri.h b/firmware/target/arm/imx233/regs/imx233/regs-dri.h
deleted file mode 100644
index 736fe7c5c4..0000000000
--- a/firmware/target/arm/imx233/regs/imx233/regs-dri.h
+++ /dev/null
@@ -1,304 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: imx233:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__IMX233__DRI__H__
-#define __HEADERGEN__IMX233__DRI__H__
-
-#define REGS_DRI_BASE (0x80074000)
-
-#define REGS_DRI_VERSION "3.2.0"
-
-/**
- * Register: HW_DRI_CTRL
- * Address: 0
- * SCT: yes
-*/
-#define HW_DRI_CTRL                                     (*(volatile unsigned long *)(REGS_DRI_BASE + 0x0 + 0x0))
-#define HW_DRI_CTRL_SET                                 (*(volatile unsigned long *)(REGS_DRI_BASE + 0x0 + 0x4))
-#define HW_DRI_CTRL_CLR                                 (*(volatile unsigned long *)(REGS_DRI_BASE + 0x0 + 0x8))
-#define HW_DRI_CTRL_TOG                                 (*(volatile unsigned long *)(REGS_DRI_BASE + 0x0 + 0xc))
-#define BP_DRI_CTRL_SFTRST                              31
-#define BM_DRI_CTRL_SFTRST                              0x80000000
-#define BV_DRI_CTRL_SFTRST__RUN                         0x0
-#define BV_DRI_CTRL_SFTRST__RESET                       0x1
-#define BF_DRI_CTRL_SFTRST(v)                           (((v) << 31) & 0x80000000)
-#define BF_DRI_CTRL_SFTRST_V(v)                         ((BV_DRI_CTRL_SFTRST__##v << 31) & 0x80000000)
-#define BP_DRI_CTRL_CLKGATE                             30
-#define BM_DRI_CTRL_CLKGATE                             0x40000000
-#define BV_DRI_CTRL_CLKGATE__RUN                        0x0
-#define BV_DRI_CTRL_CLKGATE__NO_CLKS                    0x1
-#define BF_DRI_CTRL_CLKGATE(v)                          (((v) << 30) & 0x40000000)
-#define BF_DRI_CTRL_CLKGATE_V(v)                        ((BV_DRI_CTRL_CLKGATE__##v << 30) & 0x40000000)
-#define BP_DRI_CTRL_ENABLE_INPUTS                       29
-#define BM_DRI_CTRL_ENABLE_INPUTS                       0x20000000
-#define BV_DRI_CTRL_ENABLE_INPUTS__ANALOG_LINE_IN       0x0
-#define BV_DRI_CTRL_ENABLE_INPUTS__DRI_DIGITAL_IN       0x1
-#define BF_DRI_CTRL_ENABLE_INPUTS(v)                    (((v) << 29) & 0x20000000)
-#define BF_DRI_CTRL_ENABLE_INPUTS_V(v)                  ((BV_DRI_CTRL_ENABLE_INPUTS__##v << 29) & 0x20000000)
-#define BP_DRI_CTRL_RSVD4                               27
-#define BM_DRI_CTRL_RSVD4                               0x18000000
-#define BF_DRI_CTRL_RSVD4(v)                            (((v) << 27) & 0x18000000)
-#define BP_DRI_CTRL_STOP_ON_OFLOW_ERROR                 26
-#define BM_DRI_CTRL_STOP_ON_OFLOW_ERROR                 0x4000000
-#define BV_DRI_CTRL_STOP_ON_OFLOW_ERROR__IGNORE         0x0
-#define BV_DRI_CTRL_STOP_ON_OFLOW_ERROR__STOP           0x1
-#define BF_DRI_CTRL_STOP_ON_OFLOW_ERROR(v)              (((v) << 26) & 0x4000000)
-#define BF_DRI_CTRL_STOP_ON_OFLOW_ERROR_V(v)            ((BV_DRI_CTRL_STOP_ON_OFLOW_ERROR__##v << 26) & 0x4000000)
-#define BP_DRI_CTRL_STOP_ON_PILOT_ERROR                 25
-#define BM_DRI_CTRL_STOP_ON_PILOT_ERROR                 0x2000000
-#define BV_DRI_CTRL_STOP_ON_PILOT_ERROR__IGNORE         0x0
-#define BV_DRI_CTRL_STOP_ON_PILOT_ERROR__STOP           0x1
-#define BF_DRI_CTRL_STOP_ON_PILOT_ERROR(v)              (((v) << 25) & 0x2000000)
-#define BF_DRI_CTRL_STOP_ON_PILOT_ERROR_V(v)            ((BV_DRI_CTRL_STOP_ON_PILOT_ERROR__##v << 25) & 0x2000000)
-#define BP_DRI_CTRL_RSVD3                               21
-#define BM_DRI_CTRL_RSVD3                               0x1e00000
-#define BF_DRI_CTRL_RSVD3(v)                            (((v) << 21) & 0x1e00000)
-#define BP_DRI_CTRL_DMA_DELAY_COUNT                     16
-#define BM_DRI_CTRL_DMA_DELAY_COUNT                     0x1f0000
-#define BF_DRI_CTRL_DMA_DELAY_COUNT(v)                  (((v) << 16) & 0x1f0000)
-#define BP_DRI_CTRL_REACQUIRE_PHASE                     15
-#define BM_DRI_CTRL_REACQUIRE_PHASE                     0x8000
-#define BV_DRI_CTRL_REACQUIRE_PHASE__NORMAL             0x0
-#define BV_DRI_CTRL_REACQUIRE_PHASE__NEW_PHASE          0x1
-#define BF_DRI_CTRL_REACQUIRE_PHASE(v)                  (((v) << 15) & 0x8000)
-#define BF_DRI_CTRL_REACQUIRE_PHASE_V(v)                ((BV_DRI_CTRL_REACQUIRE_PHASE__##v << 15) & 0x8000)
-#define BP_DRI_CTRL_RSVD2                               12
-#define BM_DRI_CTRL_RSVD2                               0x7000
-#define BF_DRI_CTRL_RSVD2(v)                            (((v) << 12) & 0x7000)
-#define BP_DRI_CTRL_OVERFLOW_IRQ_EN                     11
-#define BM_DRI_CTRL_OVERFLOW_IRQ_EN                     0x800
-#define BV_DRI_CTRL_OVERFLOW_IRQ_EN__DISABLED           0x0
-#define BV_DRI_CTRL_OVERFLOW_IRQ_EN__ENABLED            0x1
-#define BF_DRI_CTRL_OVERFLOW_IRQ_EN(v)                  (((v) << 11) & 0x800)
-#define BF_DRI_CTRL_OVERFLOW_IRQ_EN_V(v)                ((BV_DRI_CTRL_OVERFLOW_IRQ_EN__##v << 11) & 0x800)
-#define BP_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN              10
-#define BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN              0x400
-#define BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN__DISABLED    0x0
-#define BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN__ENABLED     0x1
-#define BF_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN(v)           (((v) << 10) & 0x400)
-#define BF_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN_V(v)         ((BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN__##v << 10) & 0x400)
-#define BP_DRI_CTRL_ATTENTION_IRQ_EN                    9
-#define BM_DRI_CTRL_ATTENTION_IRQ_EN                    0x200
-#define BV_DRI_CTRL_ATTENTION_IRQ_EN__DISABLED          0x0
-#define BV_DRI_CTRL_ATTENTION_IRQ_EN__ENABLED           0x1
-#define BF_DRI_CTRL_ATTENTION_IRQ_EN(v)                 (((v) << 9) & 0x200)
-#define BF_DRI_CTRL_ATTENTION_IRQ_EN_V(v)               ((BV_DRI_CTRL_ATTENTION_IRQ_EN__##v << 9) & 0x200)
-#define BP_DRI_CTRL_RSVD1                               4
-#define BM_DRI_CTRL_RSVD1                               0x1f0
-#define BF_DRI_CTRL_RSVD1(v)                            (((v) << 4) & 0x1f0)
-#define BP_DRI_CTRL_OVERFLOW_IRQ                        3
-#define BM_DRI_CTRL_OVERFLOW_IRQ                        0x8
-#define BV_DRI_CTRL_OVERFLOW_IRQ__NO_REQUEST            0x0
-#define BV_DRI_CTRL_OVERFLOW_IRQ__REQUEST               0x1
-#define BF_DRI_CTRL_OVERFLOW_IRQ(v)                     (((v) << 3) & 0x8)
-#define BF_DRI_CTRL_OVERFLOW_IRQ_V(v)                   ((BV_DRI_CTRL_OVERFLOW_IRQ__##v << 3) & 0x8)
-#define BP_DRI_CTRL_PILOT_SYNC_LOSS_IRQ                 2
-#define BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ                 0x4
-#define BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ__NO_REQUEST     0x0
-#define BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ__REQUEST        0x1
-#define BF_DRI_CTRL_PILOT_SYNC_LOSS_IRQ(v)              (((v) << 2) & 0x4)
-#define BF_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_V(v)            ((BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ__##v << 2) & 0x4)
-#define BP_DRI_CTRL_ATTENTION_IRQ                       1
-#define BM_DRI_CTRL_ATTENTION_IRQ                       0x2
-#define BV_DRI_CTRL_ATTENTION_IRQ__NO_REQUEST           0x0
-#define BV_DRI_CTRL_ATTENTION_IRQ__REQUEST              0x1
-#define BF_DRI_CTRL_ATTENTION_IRQ(v)                    (((v) << 1) & 0x2)
-#define BF_DRI_CTRL_ATTENTION_IRQ_V(v)                  ((BV_DRI_CTRL_ATTENTION_IRQ__##v << 1) & 0x2)
-#define BP_DRI_CTRL_RUN                                 0
-#define BM_DRI_CTRL_RUN                                 0x1
-#define BV_DRI_CTRL_RUN__HALT                           0x0
-#define BV_DRI_CTRL_RUN__RUN                            0x1
-#define BF_DRI_CTRL_RUN(v)                              (((v) << 0) & 0x1)
-#define BF_DRI_CTRL_RUN_V(v)                            ((BV_DRI_CTRL_RUN__##v << 0) & 0x1)
-
-/**
- * Register: HW_DRI_TIMING
- * Address: 0x10
- * SCT: no
-*/
-#define HW_DRI_TIMING                           (*(volatile unsigned long *)(REGS_DRI_BASE + 0x10))
-#define BP_DRI_TIMING_RSVD2                     20
-#define BM_DRI_TIMING_RSVD2                     0xfff00000
-#define BF_DRI_TIMING_RSVD2(v)                  (((v) << 20) & 0xfff00000)
-#define BP_DRI_TIMING_PILOT_REP_RATE            16
-#define BM_DRI_TIMING_PILOT_REP_RATE            0xf0000
-#define BF_DRI_TIMING_PILOT_REP_RATE(v)         (((v) << 16) & 0xf0000)
-#define BP_DRI_TIMING_RSVD1                     8
-#define BM_DRI_TIMING_RSVD1                     0xff00
-#define BF_DRI_TIMING_RSVD1(v)                  (((v) << 8) & 0xff00)
-#define BP_DRI_TIMING_GAP_DETECTION_INTERVAL    0
-#define BM_DRI_TIMING_GAP_DETECTION_INTERVAL    0xff
-#define BF_DRI_TIMING_GAP_DETECTION_INTERVAL(v) (((v) << 0) & 0xff)
-
-/**
- * Register: HW_DRI_STAT
- * Address: 0x20
- * SCT: no
-*/
-#define HW_DRI_STAT                                         (*(volatile unsigned long *)(REGS_DRI_BASE + 0x20))
-#define BP_DRI_STAT_DRI_PRESENT                             31
-#define BM_DRI_STAT_DRI_PRESENT                             0x80000000
-#define BV_DRI_STAT_DRI_PRESENT__UNAVAILABLE                0x0
-#define BV_DRI_STAT_DRI_PRESENT__AVAILABLE                  0x1
-#define BF_DRI_STAT_DRI_PRESENT(v)                          (((v) << 31) & 0x80000000)
-#define BF_DRI_STAT_DRI_PRESENT_V(v)                        ((BV_DRI_STAT_DRI_PRESENT__##v << 31) & 0x80000000)
-#define BP_DRI_STAT_RSVD3                                   20
-#define BM_DRI_STAT_RSVD3                                   0x7ff00000
-#define BF_DRI_STAT_RSVD3(v)                                (((v) << 20) & 0x7ff00000)
-#define BP_DRI_STAT_PILOT_PHASE                             16
-#define BM_DRI_STAT_PILOT_PHASE                             0xf0000
-#define BF_DRI_STAT_PILOT_PHASE(v)                          (((v) << 16) & 0xf0000)
-#define BP_DRI_STAT_RSVD2                                   4
-#define BM_DRI_STAT_RSVD2                                   0xfff0
-#define BF_DRI_STAT_RSVD2(v)                                (((v) << 4) & 0xfff0)
-#define BP_DRI_STAT_OVERFLOW_IRQ_SUMMARY                    3
-#define BM_DRI_STAT_OVERFLOW_IRQ_SUMMARY                    0x8
-#define BV_DRI_STAT_OVERFLOW_IRQ_SUMMARY__NO_REQUEST        0x0
-#define BV_DRI_STAT_OVERFLOW_IRQ_SUMMARY__REQUEST           0x1
-#define BF_DRI_STAT_OVERFLOW_IRQ_SUMMARY(v)                 (((v) << 3) & 0x8)
-#define BF_DRI_STAT_OVERFLOW_IRQ_SUMMARY_V(v)               ((BV_DRI_STAT_OVERFLOW_IRQ_SUMMARY__##v << 3) & 0x8)
-#define BP_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY             2
-#define BM_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY             0x4
-#define BV_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY__NO_REQUEST 0x0
-#define BV_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY__REQUEST    0x1
-#define BF_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY(v)          (((v) << 2) & 0x4)
-#define BF_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY_V(v)        ((BV_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY__##v << 2) & 0x4)
-#define BP_DRI_STAT_ATTENTION_IRQ_SUMMARY                   1
-#define BM_DRI_STAT_ATTENTION_IRQ_SUMMARY                   0x2
-#define BV_DRI_STAT_ATTENTION_IRQ_SUMMARY__NO_REQUEST       0x0
-#define BV_DRI_STAT_ATTENTION_IRQ_SUMMARY__REQUEST          0x1
-#define BF_DRI_STAT_ATTENTION_IRQ_SUMMARY(v)                (((v) << 1) & 0x2)
-#define BF_DRI_STAT_ATTENTION_IRQ_SUMMARY_V(v)              ((BV_DRI_STAT_ATTENTION_IRQ_SUMMARY__##v << 1) & 0x2)
-#define BP_DRI_STAT_RSVD1                                   0
-#define BM_DRI_STAT_RSVD1                                   0x1
-#define BF_DRI_STAT_RSVD1(v)                                (((v) << 0) & 0x1)
-
-/**
- * Register: HW_DRI_DATA
- * Address: 0x30
- * SCT: no
-*/
-#define HW_DRI_DATA         (*(volatile unsigned long *)(REGS_DRI_BASE + 0x30))
-#define BP_DRI_DATA_DATA    0
-#define BM_DRI_DATA_DATA    0xffffffff
-#define BF_DRI_DATA_DATA(v) (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DRI_DEBUG0
- * Address: 0x40
- * SCT: yes
-*/
-#define HW_DRI_DEBUG0                               (*(volatile unsigned long *)(REGS_DRI_BASE + 0x40 + 0x0))
-#define HW_DRI_DEBUG0_SET                           (*(volatile unsigned long *)(REGS_DRI_BASE + 0x40 + 0x4))
-#define HW_DRI_DEBUG0_CLR                           (*(volatile unsigned long *)(REGS_DRI_BASE + 0x40 + 0x8))
-#define HW_DRI_DEBUG0_TOG                           (*(volatile unsigned long *)(REGS_DRI_BASE + 0x40 + 0xc))
-#define BP_DRI_DEBUG0_DMAREQ                        31
-#define BM_DRI_DEBUG0_DMAREQ                        0x80000000
-#define BF_DRI_DEBUG0_DMAREQ(v)                     (((v) << 31) & 0x80000000)
-#define BP_DRI_DEBUG0_DMACMDKICK                    30
-#define BM_DRI_DEBUG0_DMACMDKICK                    0x40000000
-#define BF_DRI_DEBUG0_DMACMDKICK(v)                 (((v) << 30) & 0x40000000)
-#define BP_DRI_DEBUG0_DRI_CLK_INPUT                 29
-#define BM_DRI_DEBUG0_DRI_CLK_INPUT                 0x20000000
-#define BF_DRI_DEBUG0_DRI_CLK_INPUT(v)              (((v) << 29) & 0x20000000)
-#define BP_DRI_DEBUG0_DRI_DATA_INPUT                28
-#define BM_DRI_DEBUG0_DRI_DATA_INPUT                0x10000000
-#define BF_DRI_DEBUG0_DRI_DATA_INPUT(v)             (((v) << 28) & 0x10000000)
-#define BP_DRI_DEBUG0_TEST_MODE                     27
-#define BM_DRI_DEBUG0_TEST_MODE                     0x8000000
-#define BF_DRI_DEBUG0_TEST_MODE(v)                  (((v) << 27) & 0x8000000)
-#define BP_DRI_DEBUG0_PILOT_REP_RATE                26
-#define BM_DRI_DEBUG0_PILOT_REP_RATE                0x4000000
-#define BV_DRI_DEBUG0_PILOT_REP_RATE__8_AT_4MHZ     0x0
-#define BV_DRI_DEBUG0_PILOT_REP_RATE__12_AT_6MHZ    0x1
-#define BF_DRI_DEBUG0_PILOT_REP_RATE(v)             (((v) << 26) & 0x4000000)
-#define BF_DRI_DEBUG0_PILOT_REP_RATE_V(v)           ((BV_DRI_DEBUG0_PILOT_REP_RATE__##v << 26) & 0x4000000)
-#define BP_DRI_DEBUG0_SPARE                         18
-#define BM_DRI_DEBUG0_SPARE                         0x3fc0000
-#define BF_DRI_DEBUG0_SPARE(v)                      (((v) << 18) & 0x3fc0000)
-#define BP_DRI_DEBUG0_FRAME                         0
-#define BM_DRI_DEBUG0_FRAME                         0x3ffff
-#define BF_DRI_DEBUG0_FRAME(v)                      (((v) << 0) & 0x3ffff)
-
-/**
- * Register: HW_DRI_DEBUG1
- * Address: 0x50
- * SCT: yes
-*/
-#define HW_DRI_DEBUG1                               (*(volatile unsigned long *)(REGS_DRI_BASE + 0x50 + 0x0))
-#define HW_DRI_DEBUG1_SET                           (*(volatile unsigned long *)(REGS_DRI_BASE + 0x50 + 0x4))
-#define HW_DRI_DEBUG1_CLR                           (*(volatile unsigned long *)(REGS_DRI_BASE + 0x50 + 0x8))
-#define HW_DRI_DEBUG1_TOG                           (*(volatile unsigned long *)(REGS_DRI_BASE + 0x50 + 0xc))
-#define BP_DRI_DEBUG1_INVERT_PILOT                  31
-#define BM_DRI_DEBUG1_INVERT_PILOT                  0x80000000
-#define BV_DRI_DEBUG1_INVERT_PILOT__NORMAL          0x0
-#define BV_DRI_DEBUG1_INVERT_PILOT__INVERTED        0x1
-#define BF_DRI_DEBUG1_INVERT_PILOT(v)               (((v) << 31) & 0x80000000)
-#define BF_DRI_DEBUG1_INVERT_PILOT_V(v)             ((BV_DRI_DEBUG1_INVERT_PILOT__##v << 31) & 0x80000000)
-#define BP_DRI_DEBUG1_INVERT_ATTENTION              30
-#define BM_DRI_DEBUG1_INVERT_ATTENTION              0x40000000
-#define BV_DRI_DEBUG1_INVERT_ATTENTION__NORMAL      0x0
-#define BV_DRI_DEBUG1_INVERT_ATTENTION__INVERTED    0x1
-#define BF_DRI_DEBUG1_INVERT_ATTENTION(v)           (((v) << 30) & 0x40000000)
-#define BF_DRI_DEBUG1_INVERT_ATTENTION_V(v)         ((BV_DRI_DEBUG1_INVERT_ATTENTION__##v << 30) & 0x40000000)
-#define BP_DRI_DEBUG1_INVERT_DRI_DATA               29
-#define BM_DRI_DEBUG1_INVERT_DRI_DATA               0x20000000
-#define BV_DRI_DEBUG1_INVERT_DRI_DATA__NORMAL       0x0
-#define BV_DRI_DEBUG1_INVERT_DRI_DATA__INVERTED     0x1
-#define BF_DRI_DEBUG1_INVERT_DRI_DATA(v)            (((v) << 29) & 0x20000000)
-#define BF_DRI_DEBUG1_INVERT_DRI_DATA_V(v)          ((BV_DRI_DEBUG1_INVERT_DRI_DATA__##v << 29) & 0x20000000)
-#define BP_DRI_DEBUG1_INVERT_DRI_CLOCK              28
-#define BM_DRI_DEBUG1_INVERT_DRI_CLOCK              0x10000000
-#define BV_DRI_DEBUG1_INVERT_DRI_CLOCK__NORMAL      0x0
-#define BV_DRI_DEBUG1_INVERT_DRI_CLOCK__INVERTED    0x1
-#define BF_DRI_DEBUG1_INVERT_DRI_CLOCK(v)           (((v) << 28) & 0x10000000)
-#define BF_DRI_DEBUG1_INVERT_DRI_CLOCK_V(v)         ((BV_DRI_DEBUG1_INVERT_DRI_CLOCK__##v << 28) & 0x10000000)
-#define BP_DRI_DEBUG1_REVERSE_FRAME                 27
-#define BM_DRI_DEBUG1_REVERSE_FRAME                 0x8000000
-#define BV_DRI_DEBUG1_REVERSE_FRAME__NORMAL         0x0
-#define BV_DRI_DEBUG1_REVERSE_FRAME__REVERSED       0x1
-#define BF_DRI_DEBUG1_REVERSE_FRAME(v)              (((v) << 27) & 0x8000000)
-#define BF_DRI_DEBUG1_REVERSE_FRAME_V(v)            ((BV_DRI_DEBUG1_REVERSE_FRAME__##v << 27) & 0x8000000)
-#define BP_DRI_DEBUG1_RSVD1                         18
-#define BM_DRI_DEBUG1_RSVD1                         0x7fc0000
-#define BF_DRI_DEBUG1_RSVD1(v)                      (((v) << 18) & 0x7fc0000)
-#define BP_DRI_DEBUG1_SWIZZLED_FRAME                0
-#define BM_DRI_DEBUG1_SWIZZLED_FRAME                0x3ffff
-#define BF_DRI_DEBUG1_SWIZZLED_FRAME(v)             (((v) << 0) & 0x3ffff)
-
-/**
- * Register: HW_DRI_VERSION
- * Address: 0x60
- * SCT: no
-*/
-#define HW_DRI_VERSION          (*(volatile unsigned long *)(REGS_DRI_BASE + 0x60))
-#define BP_DRI_VERSION_MAJOR    24
-#define BM_DRI_VERSION_MAJOR    0xff000000
-#define BF_DRI_VERSION_MAJOR(v) (((v) << 24) & 0xff000000)
-#define BP_DRI_VERSION_MINOR    16
-#define BM_DRI_VERSION_MINOR    0xff0000
-#define BF_DRI_VERSION_MINOR(v) (((v) << 16) & 0xff0000)
-#define BP_DRI_VERSION_STEP     0
-#define BM_DRI_VERSION_STEP     0xffff
-#define BF_DRI_VERSION_STEP(v)  (((v) << 0) & 0xffff)
-
-#endif /* __HEADERGEN__IMX233__DRI__H__ */
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-ecc8.h b/firmware/target/arm/imx233/regs/imx233/regs-ecc8.h
deleted file mode 100644
index fd792771de..0000000000
--- a/firmware/target/arm/imx233/regs/imx233/regs-ecc8.h
+++ /dev/null
@@ -1,408 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: imx233:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__IMX233__ECC8__H__
-#define __HEADERGEN__IMX233__ECC8__H__
-
-#define REGS_ECC8_BASE (0x80008000)
-
-#define REGS_ECC8_VERSION "3.2.0"
-
-/**
- * Register: HW_ECC8_CTRL
- * Address: 0
- * SCT: yes
-*/
-#define HW_ECC8_CTRL                        (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x0 + 0x0))
-#define HW_ECC8_CTRL_SET                    (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x0 + 0x4))
-#define HW_ECC8_CTRL_CLR                    (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x0 + 0x8))
-#define HW_ECC8_CTRL_TOG                    (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x0 + 0xc))
-#define BP_ECC8_CTRL_SFTRST                 31
-#define BM_ECC8_CTRL_SFTRST                 0x80000000
-#define BV_ECC8_CTRL_SFTRST__RUN            0x0
-#define BV_ECC8_CTRL_SFTRST__RESET          0x1
-#define BF_ECC8_CTRL_SFTRST(v)              (((v) << 31) & 0x80000000)
-#define BF_ECC8_CTRL_SFTRST_V(v)            ((BV_ECC8_CTRL_SFTRST__##v << 31) & 0x80000000)
-#define BP_ECC8_CTRL_CLKGATE                30
-#define BM_ECC8_CTRL_CLKGATE                0x40000000
-#define BV_ECC8_CTRL_CLKGATE__RUN           0x0
-#define BV_ECC8_CTRL_CLKGATE__NO_CLKS       0x1
-#define BF_ECC8_CTRL_CLKGATE(v)             (((v) << 30) & 0x40000000)
-#define BF_ECC8_CTRL_CLKGATE_V(v)           ((BV_ECC8_CTRL_CLKGATE__##v << 30) & 0x40000000)
-#define BP_ECC8_CTRL_AHBM_SFTRST            29
-#define BM_ECC8_CTRL_AHBM_SFTRST            0x20000000
-#define BV_ECC8_CTRL_AHBM_SFTRST__RUN       0x0
-#define BV_ECC8_CTRL_AHBM_SFTRST__RESET     0x1
-#define BF_ECC8_CTRL_AHBM_SFTRST(v)         (((v) << 29) & 0x20000000)
-#define BF_ECC8_CTRL_AHBM_SFTRST_V(v)       ((BV_ECC8_CTRL_AHBM_SFTRST__##v << 29) & 0x20000000)
-#define BP_ECC8_CTRL_RSRVD2                 28
-#define BM_ECC8_CTRL_RSRVD2                 0x10000000
-#define BF_ECC8_CTRL_RSRVD2(v)              (((v) << 28) & 0x10000000)
-#define BP_ECC8_CTRL_THROTTLE               24
-#define BM_ECC8_CTRL_THROTTLE               0xf000000
-#define BF_ECC8_CTRL_THROTTLE(v)            (((v) << 24) & 0xf000000)
-#define BP_ECC8_CTRL_RSRVD1                 11
-#define BM_ECC8_CTRL_RSRVD1                 0xfff800
-#define BF_ECC8_CTRL_RSRVD1(v)              (((v) << 11) & 0xfff800)
-#define BP_ECC8_CTRL_DEBUG_STALL_IRQ_EN     10
-#define BM_ECC8_CTRL_DEBUG_STALL_IRQ_EN     0x400
-#define BF_ECC8_CTRL_DEBUG_STALL_IRQ_EN(v)  (((v) << 10) & 0x400)
-#define BP_ECC8_CTRL_DEBUG_WRITE_IRQ_EN     9
-#define BM_ECC8_CTRL_DEBUG_WRITE_IRQ_EN     0x200
-#define BF_ECC8_CTRL_DEBUG_WRITE_IRQ_EN(v)  (((v) << 9) & 0x200)
-#define BP_ECC8_CTRL_COMPLETE_IRQ_EN        8
-#define BM_ECC8_CTRL_COMPLETE_IRQ_EN        0x100
-#define BF_ECC8_CTRL_COMPLETE_IRQ_EN(v)     (((v) << 8) & 0x100)
-#define BP_ECC8_CTRL_RSRVD0                 4
-#define BM_ECC8_CTRL_RSRVD0                 0xf0
-#define BF_ECC8_CTRL_RSRVD0(v)              (((v) << 4) & 0xf0)
-#define BP_ECC8_CTRL_BM_ERROR_IRQ           3
-#define BM_ECC8_CTRL_BM_ERROR_IRQ           0x8
-#define BF_ECC8_CTRL_BM_ERROR_IRQ(v)        (((v) << 3) & 0x8)
-#define BP_ECC8_CTRL_DEBUG_STALL_IRQ        2
-#define BM_ECC8_CTRL_DEBUG_STALL_IRQ        0x4
-#define BF_ECC8_CTRL_DEBUG_STALL_IRQ(v)     (((v) << 2) & 0x4)
-#define BP_ECC8_CTRL_DEBUG_WRITE_IRQ        1
-#define BM_ECC8_CTRL_DEBUG_WRITE_IRQ        0x2
-#define BF_ECC8_CTRL_DEBUG_WRITE_IRQ(v)     (((v) << 1) & 0x2)
-#define BP_ECC8_CTRL_COMPLETE_IRQ           0
-#define BM_ECC8_CTRL_COMPLETE_IRQ           0x1
-#define BF_ECC8_CTRL_COMPLETE_IRQ(v)        (((v) << 0) & 0x1)
-
-/**
- * Register: HW_ECC8_STATUS0
- * Address: 0x10
- * SCT: no
-*/
-#define HW_ECC8_STATUS0                                 (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x10))
-#define BP_ECC8_STATUS0_HANDLE                          20
-#define BM_ECC8_STATUS0_HANDLE                          0xfff00000
-#define BF_ECC8_STATUS0_HANDLE(v)                       (((v) << 20) & 0xfff00000)
-#define BP_ECC8_STATUS0_COMPLETED_CE                    16
-#define BM_ECC8_STATUS0_COMPLETED_CE                    0xf0000
-#define BF_ECC8_STATUS0_COMPLETED_CE(v)                 (((v) << 16) & 0xf0000)
-#define BP_ECC8_STATUS0_RS8ECC_ENC_PRESENT              15
-#define BM_ECC8_STATUS0_RS8ECC_ENC_PRESENT              0x8000
-#define BF_ECC8_STATUS0_RS8ECC_ENC_PRESENT(v)           (((v) << 15) & 0x8000)
-#define BP_ECC8_STATUS0_RS8ECC_DEC_PRESENT              14
-#define BM_ECC8_STATUS0_RS8ECC_DEC_PRESENT              0x4000
-#define BF_ECC8_STATUS0_RS8ECC_DEC_PRESENT(v)           (((v) << 14) & 0x4000)
-#define BP_ECC8_STATUS0_RS4ECC_ENC_PRESENT              13
-#define BM_ECC8_STATUS0_RS4ECC_ENC_PRESENT              0x2000
-#define BF_ECC8_STATUS0_RS4ECC_ENC_PRESENT(v)           (((v) << 13) & 0x2000)
-#define BP_ECC8_STATUS0_RS4ECC_DEC_PRESENT              12
-#define BM_ECC8_STATUS0_RS4ECC_DEC_PRESENT              0x1000
-#define BF_ECC8_STATUS0_RS4ECC_DEC_PRESENT(v)           (((v) << 12) & 0x1000)
-#define BP_ECC8_STATUS0_STATUS_AUX                      8
-#define BM_ECC8_STATUS0_STATUS_AUX                      0xf00
-#define BV_ECC8_STATUS0_STATUS_AUX__NO_ERRORS           0x0
-#define BV_ECC8_STATUS0_STATUS_AUX__ONE_CORRECTABLE     0x1
-#define BV_ECC8_STATUS0_STATUS_AUX__TWO_CORRECTABLE     0x2
-#define BV_ECC8_STATUS0_STATUS_AUX__THREE_CORRECTABLE   0x3
-#define BV_ECC8_STATUS0_STATUS_AUX__FOUR_CORRECTABLE    0x4
-#define BV_ECC8_STATUS0_STATUS_AUX__NOT_CHECKED         0xc
-#define BV_ECC8_STATUS0_STATUS_AUX__UNCORRECTABLE       0xe
-#define BV_ECC8_STATUS0_STATUS_AUX__ALL_ONES            0xf
-#define BF_ECC8_STATUS0_STATUS_AUX(v)                   (((v) << 8) & 0xf00)
-#define BF_ECC8_STATUS0_STATUS_AUX_V(v)                 ((BV_ECC8_STATUS0_STATUS_AUX__##v << 8) & 0xf00)
-#define BP_ECC8_STATUS0_RSVD1                           5
-#define BM_ECC8_STATUS0_RSVD1                           0xe0
-#define BF_ECC8_STATUS0_RSVD1(v)                        (((v) << 5) & 0xe0)
-#define BP_ECC8_STATUS0_ALLONES                         4
-#define BM_ECC8_STATUS0_ALLONES                         0x10
-#define BF_ECC8_STATUS0_ALLONES(v)                      (((v) << 4) & 0x10)
-#define BP_ECC8_STATUS0_CORRECTED                       3
-#define BM_ECC8_STATUS0_CORRECTED                       0x8
-#define BF_ECC8_STATUS0_CORRECTED(v)                    (((v) << 3) & 0x8)
-#define BP_ECC8_STATUS0_UNCORRECTABLE                   2
-#define BM_ECC8_STATUS0_UNCORRECTABLE                   0x4
-#define BF_ECC8_STATUS0_UNCORRECTABLE(v)                (((v) << 2) & 0x4)
-#define BP_ECC8_STATUS0_RSVD0                           0
-#define BM_ECC8_STATUS0_RSVD0                           0x3
-#define BF_ECC8_STATUS0_RSVD0(v)                        (((v) << 0) & 0x3)
-
-/**
- * Register: HW_ECC8_STATUS1
- * Address: 0x20
- * SCT: no
-*/
-#define HW_ECC8_STATUS1                                     (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x20))
-#define BP_ECC8_STATUS1_STATUS_PAYLOAD7                     28
-#define BM_ECC8_STATUS1_STATUS_PAYLOAD7                     0xf0000000
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__NO_ERRORS          0x0
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__ONE_CORRECTABLE    0x1
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__TWO_CORRECTABLE    0x2
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__THREE_CORRECTABLE  0x3
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__FOUR_CORRECTABLE   0x4
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__FIVE_CORRECTABLE   0x5
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__SIX_CORRECTABLE    0x6
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__SEVEN_CORRECTABLE  0x7
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__EIGHT_CORRECTABLE  0x8
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__NOT_CHECKED        0xc
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__UNCORRECTABLE      0xe
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__ALL_ONES           0xf
-#define BF_ECC8_STATUS1_STATUS_PAYLOAD7(v)                  (((v) << 28) & 0xf0000000)
-#define BF_ECC8_STATUS1_STATUS_PAYLOAD7_V(v)                ((BV_ECC8_STATUS1_STATUS_PAYLOAD7__##v << 28) & 0xf0000000)
-#define BP_ECC8_STATUS1_STATUS_PAYLOAD6                     24
-#define BM_ECC8_STATUS1_STATUS_PAYLOAD6                     0xf000000
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__NO_ERRORS          0x0
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__ONE_CORRECTABLE    0x1
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__TWO_CORRECTABLE    0x2
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__THREE_CORRECTABLE  0x3
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__FOUR_CORRECTABLE   0x4
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__FIVE_CORRECTABLE   0x5
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__SIX_CORRECTABLE    0x6
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__SEVEN_CORRECTABLE  0x7
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__EIGHT_CORRECTABLE  0x8
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__NOT_CHECKED        0xc
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__UNCORRECTABLE      0xe
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__ALL_ONES           0xf
-#define BF_ECC8_STATUS1_STATUS_PAYLOAD6(v)                  (((v) << 24) & 0xf000000)
-#define BF_ECC8_STATUS1_STATUS_PAYLOAD6_V(v)                ((BV_ECC8_STATUS1_STATUS_PAYLOAD6__##v << 24) & 0xf000000)
-#define BP_ECC8_STATUS1_STATUS_PAYLOAD5                     20
-#define BM_ECC8_STATUS1_STATUS_PAYLOAD5                     0xf00000
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__NO_ERRORS          0x0
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__ONE_CORRECTABLE    0x1
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__TWO_CORRECTABLE    0x2
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__THREE_CORRECTABLE  0x3
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__FOUR_CORRECTABLE   0x4
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__FIVE_CORRECTABLE   0x5
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__SIX_CORRECTABLE    0x6
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__SEVEN_CORRECTABLE  0x7
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__EIGHT_CORRECTABLE  0x8
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__NOT_CHECKED        0xc
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__UNCORRECTABLE      0xe
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__ALL_ONES           0xf
-#define BF_ECC8_STATUS1_STATUS_PAYLOAD5(v)                  (((v) << 20) & 0xf00000)
-#define BF_ECC8_STATUS1_STATUS_PAYLOAD5_V(v)                ((BV_ECC8_STATUS1_STATUS_PAYLOAD5__##v << 20) & 0xf00000)
-#define BP_ECC8_STATUS1_STATUS_PAYLOAD4                     16
-#define BM_ECC8_STATUS1_STATUS_PAYLOAD4                     0xf0000
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__NO_ERRORS          0x0
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__ONE_CORRECTABLE    0x1
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__TWO_CORRECTABLE    0x2
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__THREE_CORRECTABLE  0x3
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__FOUR_CORRECTABLE   0x4
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__FIVE_CORRECTABLE   0x5
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__SIX_CORRECTABLE    0x6
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__SEVEN_CORRECTABLE  0x7
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__EIGHT_CORRECTABLE  0x8
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__NOT_CHECKED        0xc
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__UNCORRECTABLE      0xe
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__ALL_ONES           0xf
-#define BF_ECC8_STATUS1_STATUS_PAYLOAD4(v)                  (((v) << 16) & 0xf0000)
-#define BF_ECC8_STATUS1_STATUS_PAYLOAD4_V(v)                ((BV_ECC8_STATUS1_STATUS_PAYLOAD4__##v << 16) & 0xf0000)
-#define BP_ECC8_STATUS1_STATUS_PAYLOAD3                     12
-#define BM_ECC8_STATUS1_STATUS_PAYLOAD3                     0xf000
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__NO_ERRORS          0x0
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__ONE_CORRECTABLE    0x1
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__TWO_CORRECTABLE    0x2
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__THREE_CORRECTABLE  0x3
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__FOUR_CORRECTABLE   0x4
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__FIVE_CORRECTABLE   0x5
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__SIX_CORRECTABLE    0x6
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__SEVEN_CORRECTABLE  0x7
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__EIGHT_CORRECTABLE  0x8
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__NOT_CHECKED        0xc
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__UNCORRECTABLE      0xe
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__ALL_ONES           0xf
-#define BF_ECC8_STATUS1_STATUS_PAYLOAD3(v)                  (((v) << 12) & 0xf000)
-#define BF_ECC8_STATUS1_STATUS_PAYLOAD3_V(v)                ((BV_ECC8_STATUS1_STATUS_PAYLOAD3__##v << 12) & 0xf000)
-#define BP_ECC8_STATUS1_STATUS_PAYLOAD2                     8
-#define BM_ECC8_STATUS1_STATUS_PAYLOAD2                     0xf00
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__NO_ERRORS          0x0
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__ONE_CORRECTABLE    0x1
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__TWO_CORRECTABLE    0x2
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__THREE_CORRECTABLE  0x3
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__FOUR_CORRECTABLE   0x4
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__FIVE_CORRECTABLE   0x5
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__SIX_CORRECTABLE    0x6
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__SEVEN_CORRECTABLE  0x7
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__EIGHT_CORRECTABLE  0x8
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__NOT_CHECKED        0xc
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__UNCORRECTABLE      0xe
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__ALL_ONES           0xf
-#define BF_ECC8_STATUS1_STATUS_PAYLOAD2(v)                  (((v) << 8) & 0xf00)
-#define BF_ECC8_STATUS1_STATUS_PAYLOAD2_V(v)                ((BV_ECC8_STATUS1_STATUS_PAYLOAD2__##v << 8) & 0xf00)
-#define BP_ECC8_STATUS1_STATUS_PAYLOAD1                     4
-#define BM_ECC8_STATUS1_STATUS_PAYLOAD1                     0xf0
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__NO_ERRORS          0x0
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__ONE_CORRECTABLE    0x1
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__TWO_CORRECTABLE    0x2
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__THREE_CORRECTABLE  0x3
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__FOUR_CORRECTABLE   0x4
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__FIVE_CORRECTABLE   0x5
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__SIX_CORRECTABLE    0x6
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__SEVEN_CORRECTABLE  0x7
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__EIGHT_CORRECTABLE  0x8
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__NOT_CHECKED        0xc
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__UNCORRECTABLE      0xe
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__ALL_ONES           0xf
-#define BF_ECC8_STATUS1_STATUS_PAYLOAD1(v)                  (((v) << 4) & 0xf0)
-#define BF_ECC8_STATUS1_STATUS_PAYLOAD1_V(v)                ((BV_ECC8_STATUS1_STATUS_PAYLOAD1__##v << 4) & 0xf0)
-#define BP_ECC8_STATUS1_STATUS_PAYLOAD0                     0
-#define BM_ECC8_STATUS1_STATUS_PAYLOAD0                     0xf
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__NO_ERRORS          0x0
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__ONE_CORRECTABLE    0x1
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__TWO_CORRECTABLE    0x2
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__THREE_CORRECTABLE  0x3
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__FOUR_CORRECTABLE   0x4
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__FIVE_CORRECTABLE   0x5
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__SIX_CORRECTABLE    0x6
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__SEVEN_CORRECTABLE  0x7
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__EIGHT_CORRECTABLE  0x8
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__NOT_CHECKED        0xc
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__UNCORRECTABLE      0xe
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__ALL_ONES           0xf
-#define BF_ECC8_STATUS1_STATUS_PAYLOAD0(v)                  (((v) << 0) & 0xf)
-#define BF_ECC8_STATUS1_STATUS_PAYLOAD0_V(v)                ((BV_ECC8_STATUS1_STATUS_PAYLOAD0__##v << 0) & 0xf)
-
-/**
- * Register: HW_ECC8_DEBUG0
- * Address: 0x30
- * SCT: yes
-*/
-#define HW_ECC8_DEBUG0                                      (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x30 + 0x0))
-#define HW_ECC8_DEBUG0_SET                                  (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x30 + 0x4))
-#define HW_ECC8_DEBUG0_CLR                                  (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x30 + 0x8))
-#define HW_ECC8_DEBUG0_TOG                                  (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x30 + 0xc))
-#define BP_ECC8_DEBUG0_RSRVD1                               25
-#define BM_ECC8_DEBUG0_RSRVD1                               0xfe000000
-#define BF_ECC8_DEBUG0_RSRVD1(v)                            (((v) << 25) & 0xfe000000)
-#define BP_ECC8_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL            16
-#define BM_ECC8_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL            0x1ff0000
-#define BV_ECC8_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__NORMAL    0x0
-#define BV_ECC8_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__TEST_MODE 0x1
-#define BF_ECC8_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL(v)         (((v) << 16) & 0x1ff0000)
-#define BF_ECC8_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_V(v)       ((BV_ECC8_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__##v << 16) & 0x1ff0000)
-#define BP_ECC8_DEBUG0_KES_DEBUG_SHIFT_SYND                 15
-#define BM_ECC8_DEBUG0_KES_DEBUG_SHIFT_SYND                 0x8000
-#define BF_ECC8_DEBUG0_KES_DEBUG_SHIFT_SYND(v)              (((v) << 15) & 0x8000)
-#define BP_ECC8_DEBUG0_KES_DEBUG_PAYLOAD_FLAG               14
-#define BM_ECC8_DEBUG0_KES_DEBUG_PAYLOAD_FLAG               0x4000
-#define BV_ECC8_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__DATA         0x1
-#define BV_ECC8_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__AUX          0x1
-#define BF_ECC8_DEBUG0_KES_DEBUG_PAYLOAD_FLAG(v)            (((v) << 14) & 0x4000)
-#define BF_ECC8_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_V(v)          ((BV_ECC8_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__##v << 14) & 0x4000)
-#define BP_ECC8_DEBUG0_KES_DEBUG_MODE4K                     13
-#define BM_ECC8_DEBUG0_KES_DEBUG_MODE4K                     0x2000
-#define BV_ECC8_DEBUG0_KES_DEBUG_MODE4K__4k                 0x1
-#define BV_ECC8_DEBUG0_KES_DEBUG_MODE4K__2k                 0x1
-#define BF_ECC8_DEBUG0_KES_DEBUG_MODE4K(v)                  (((v) << 13) & 0x2000)
-#define BF_ECC8_DEBUG0_KES_DEBUG_MODE4K_V(v)                ((BV_ECC8_DEBUG0_KES_DEBUG_MODE4K__##v << 13) & 0x2000)
-#define BP_ECC8_DEBUG0_KES_DEBUG_KICK                       12
-#define BM_ECC8_DEBUG0_KES_DEBUG_KICK                       0x1000
-#define BF_ECC8_DEBUG0_KES_DEBUG_KICK(v)                    (((v) << 12) & 0x1000)
-#define BP_ECC8_DEBUG0_KES_STANDALONE                       11
-#define BM_ECC8_DEBUG0_KES_STANDALONE                       0x800
-#define BV_ECC8_DEBUG0_KES_STANDALONE__NORMAL               0x0
-#define BV_ECC8_DEBUG0_KES_STANDALONE__TEST_MODE            0x1
-#define BF_ECC8_DEBUG0_KES_STANDALONE(v)                    (((v) << 11) & 0x800)
-#define BF_ECC8_DEBUG0_KES_STANDALONE_V(v)                  ((BV_ECC8_DEBUG0_KES_STANDALONE__##v << 11) & 0x800)
-#define BP_ECC8_DEBUG0_KES_DEBUG_STEP                       10
-#define BM_ECC8_DEBUG0_KES_DEBUG_STEP                       0x400
-#define BF_ECC8_DEBUG0_KES_DEBUG_STEP(v)                    (((v) << 10) & 0x400)
-#define BP_ECC8_DEBUG0_KES_DEBUG_STALL                      9
-#define BM_ECC8_DEBUG0_KES_DEBUG_STALL                      0x200
-#define BV_ECC8_DEBUG0_KES_DEBUG_STALL__NORMAL              0x0
-#define BV_ECC8_DEBUG0_KES_DEBUG_STALL__WAIT                0x1
-#define BF_ECC8_DEBUG0_KES_DEBUG_STALL(v)                   (((v) << 9) & 0x200)
-#define BF_ECC8_DEBUG0_KES_DEBUG_STALL_V(v)                 ((BV_ECC8_DEBUG0_KES_DEBUG_STALL__##v << 9) & 0x200)
-#define BP_ECC8_DEBUG0_BM_KES_TEST_BYPASS                   8
-#define BM_ECC8_DEBUG0_BM_KES_TEST_BYPASS                   0x100
-#define BV_ECC8_DEBUG0_BM_KES_TEST_BYPASS__NORMAL           0x0
-#define BV_ECC8_DEBUG0_BM_KES_TEST_BYPASS__TEST_MODE        0x1
-#define BF_ECC8_DEBUG0_BM_KES_TEST_BYPASS(v)                (((v) << 8) & 0x100)
-#define BF_ECC8_DEBUG0_BM_KES_TEST_BYPASS_V(v)              ((BV_ECC8_DEBUG0_BM_KES_TEST_BYPASS__##v << 8) & 0x100)
-#define BP_ECC8_DEBUG0_RSRVD0                               6
-#define BM_ECC8_DEBUG0_RSRVD0                               0xc0
-#define BF_ECC8_DEBUG0_RSRVD0(v)                            (((v) << 6) & 0xc0)
-#define BP_ECC8_DEBUG0_DEBUG_REG_SELECT                     0
-#define BM_ECC8_DEBUG0_DEBUG_REG_SELECT                     0x3f
-#define BF_ECC8_DEBUG0_DEBUG_REG_SELECT(v)                  (((v) << 0) & 0x3f)
-
-/**
- * Register: HW_ECC8_DBGKESREAD
- * Address: 0x40
- * SCT: no
-*/
-#define HW_ECC8_DBGKESREAD              (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x40))
-#define BP_ECC8_DBGKESREAD_VALUES       0
-#define BM_ECC8_DBGKESREAD_VALUES       0xffffffff
-#define BF_ECC8_DBGKESREAD_VALUES(v)    (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_ECC8_DBGCSFEREAD
- * Address: 0x50
- * SCT: no
-*/
-#define HW_ECC8_DBGCSFEREAD             (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x50))
-#define BP_ECC8_DBGCSFEREAD_VALUES      0
-#define BM_ECC8_DBGCSFEREAD_VALUES      0xffffffff
-#define BF_ECC8_DBGCSFEREAD_VALUES(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_ECC8_DBGSYNDGENREAD
- * Address: 0x60
- * SCT: no
-*/
-#define HW_ECC8_DBGSYNDGENREAD              (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x60))
-#define BP_ECC8_DBGSYNDGENREAD_VALUES       0
-#define BM_ECC8_DBGSYNDGENREAD_VALUES       0xffffffff
-#define BF_ECC8_DBGSYNDGENREAD_VALUES(v)    (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_ECC8_DBGAHBMREAD
- * Address: 0x70
- * SCT: no
-*/
-#define HW_ECC8_DBGAHBMREAD             (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x70))
-#define BP_ECC8_DBGAHBMREAD_VALUES      0
-#define BM_ECC8_DBGAHBMREAD_VALUES      0xffffffff
-#define BF_ECC8_DBGAHBMREAD_VALUES(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_ECC8_BLOCKNAME
- * Address: 0x80
- * SCT: no
-*/
-#define HW_ECC8_BLOCKNAME           (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x80))
-#define BP_ECC8_BLOCKNAME_NAME      0
-#define BM_ECC8_BLOCKNAME_NAME      0xffffffff
-#define BF_ECC8_BLOCKNAME_NAME(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_ECC8_VERSION
- * Address: 0xa0
- * SCT: no
-*/
-#define HW_ECC8_VERSION             (*(volatile unsigned long *)(REGS_ECC8_BASE + 0xa0))
-#define BP_ECC8_VERSION_MAJOR       24
-#define BM_ECC8_VERSION_MAJOR       0xff000000
-#define BF_ECC8_VERSION_MAJOR(v)    (((v) << 24) & 0xff000000)
-#define BP_ECC8_VERSION_MINOR       16
-#define BM_ECC8_VERSION_MINOR       0xff0000
-#define BF_ECC8_VERSION_MINOR(v)    (((v) << 16) & 0xff0000)
-#define BP_ECC8_VERSION_STEP        0
-#define BM_ECC8_VERSION_STEP        0xffff
-#define BF_ECC8_VERSION_STEP(v)     (((v) << 0) & 0xffff)
-
-#endif /* __HEADERGEN__IMX233__ECC8__H__ */
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-emi.h b/firmware/target/arm/imx233/regs/imx233/regs-emi.h
deleted file mode 100644
index 28877d60af..0000000000
--- a/firmware/target/arm/imx233/regs/imx233/regs-emi.h
+++ /dev/null
@@ -1,296 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: imx233:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__IMX233__EMI__H__
-#define __HEADERGEN__IMX233__EMI__H__
-
-#define REGS_EMI_BASE (0x80020000)
-
-#define REGS_EMI_VERSION "3.2.0"
-
-/**
- * Register: HW_EMI_CTRL
- * Address: 0
- * SCT: yes
-*/
-#define HW_EMI_CTRL                                 (*(volatile unsigned long *)(REGS_EMI_BASE + 0x0 + 0x0))
-#define HW_EMI_CTRL_SET                             (*(volatile unsigned long *)(REGS_EMI_BASE + 0x0 + 0x4))
-#define HW_EMI_CTRL_CLR                             (*(volatile unsigned long *)(REGS_EMI_BASE + 0x0 + 0x8))
-#define HW_EMI_CTRL_TOG                             (*(volatile unsigned long *)(REGS_EMI_BASE + 0x0 + 0xc))
-#define BP_EMI_CTRL_SFTRST                          31
-#define BM_EMI_CTRL_SFTRST                          0x80000000
-#define BF_EMI_CTRL_SFTRST(v)                       (((v) << 31) & 0x80000000)
-#define BP_EMI_CTRL_CLKGATE                         30
-#define BM_EMI_CTRL_CLKGATE                         0x40000000
-#define BF_EMI_CTRL_CLKGATE(v)                      (((v) << 30) & 0x40000000)
-#define BP_EMI_CTRL_TRAP_SR                         29
-#define BM_EMI_CTRL_TRAP_SR                         0x20000000
-#define BF_EMI_CTRL_TRAP_SR(v)                      (((v) << 29) & 0x20000000)
-#define BP_EMI_CTRL_TRAP_INIT                       28
-#define BM_EMI_CTRL_TRAP_INIT                       0x10000000
-#define BF_EMI_CTRL_TRAP_INIT(v)                    (((v) << 28) & 0x10000000)
-#define BP_EMI_CTRL_AXI_DEPTH                       26
-#define BM_EMI_CTRL_AXI_DEPTH                       0xc000000
-#define BV_EMI_CTRL_AXI_DEPTH__ONE                  0x0
-#define BV_EMI_CTRL_AXI_DEPTH__TWO                  0x1
-#define BV_EMI_CTRL_AXI_DEPTH__THREE                0x2
-#define BV_EMI_CTRL_AXI_DEPTH__FOUR                 0x3
-#define BF_EMI_CTRL_AXI_DEPTH(v)                    (((v) << 26) & 0xc000000)
-#define BF_EMI_CTRL_AXI_DEPTH_V(v)                  ((BV_EMI_CTRL_AXI_DEPTH__##v << 26) & 0xc000000)
-#define BP_EMI_CTRL_DLL_SHIFT_RESET                 25
-#define BM_EMI_CTRL_DLL_SHIFT_RESET                 0x2000000
-#define BF_EMI_CTRL_DLL_SHIFT_RESET(v)              (((v) << 25) & 0x2000000)
-#define BP_EMI_CTRL_DLL_RESET                       24
-#define BM_EMI_CTRL_DLL_RESET                       0x1000000
-#define BF_EMI_CTRL_DLL_RESET(v)                    (((v) << 24) & 0x1000000)
-#define BP_EMI_CTRL_ARB_MODE                        22
-#define BM_EMI_CTRL_ARB_MODE                        0xc00000
-#define BV_EMI_CTRL_ARB_MODE__TIMESTAMP             0x0
-#define BV_EMI_CTRL_ARB_MODE__WRITE_HYBRID          0x1
-#define BV_EMI_CTRL_ARB_MODE__PORT_PRIORITY         0x2
-#define BF_EMI_CTRL_ARB_MODE(v)                     (((v) << 22) & 0xc00000)
-#define BF_EMI_CTRL_ARB_MODE_V(v)                   ((BV_EMI_CTRL_ARB_MODE__##v << 22) & 0xc00000)
-#define BP_EMI_CTRL_RSVD3                           21
-#define BM_EMI_CTRL_RSVD3                           0x200000
-#define BF_EMI_CTRL_RSVD3(v)                        (((v) << 21) & 0x200000)
-#define BP_EMI_CTRL_PORT_PRIORITY_ORDER             16
-#define BM_EMI_CTRL_PORT_PRIORITY_ORDER             0x1f0000
-#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT0123   0x0
-#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT0312   0x1
-#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT0231   0x2
-#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT0321   0x3
-#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT0213   0x4
-#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT0132   0x5
-#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT1023   0x6
-#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT1302   0x7
-#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT1230   0x8
-#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT1320   0x9
-#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT1203   0xa
-#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT1032   0xb
-#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT2013   0xc
-#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT2301   0xd
-#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT2130   0xe
-#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT2310   0xf
-#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT2103   0x10
-#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT2031   0x11
-#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT3012   0x12
-#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT3201   0x13
-#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT3120   0x14
-#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT3210   0x15
-#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT3102   0x16
-#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT3021   0x17
-#define BF_EMI_CTRL_PORT_PRIORITY_ORDER(v)          (((v) << 16) & 0x1f0000)
-#define BF_EMI_CTRL_PORT_PRIORITY_ORDER_V(v)        ((BV_EMI_CTRL_PORT_PRIORITY_ORDER__##v << 16) & 0x1f0000)
-#define BP_EMI_CTRL_RSVD2                           15
-#define BM_EMI_CTRL_RSVD2                           0x8000
-#define BF_EMI_CTRL_RSVD2(v)                        (((v) << 15) & 0x8000)
-#define BP_EMI_CTRL_PRIORITY_WRITE_ITER             12
-#define BM_EMI_CTRL_PRIORITY_WRITE_ITER             0x7000
-#define BF_EMI_CTRL_PRIORITY_WRITE_ITER(v)          (((v) << 12) & 0x7000)
-#define BP_EMI_CTRL_RSVD1                           11
-#define BM_EMI_CTRL_RSVD1                           0x800
-#define BF_EMI_CTRL_RSVD1(v)                        (((v) << 11) & 0x800)
-#define BP_EMI_CTRL_HIGH_PRIORITY_WRITE             8
-#define BM_EMI_CTRL_HIGH_PRIORITY_WRITE             0x700
-#define BF_EMI_CTRL_HIGH_PRIORITY_WRITE(v)          (((v) << 8) & 0x700)
-#define BP_EMI_CTRL_RSVD0                           7
-#define BM_EMI_CTRL_RSVD0                           0x80
-#define BF_EMI_CTRL_RSVD0(v)                        (((v) << 7) & 0x80)
-#define BP_EMI_CTRL_MEM_WIDTH                       6
-#define BM_EMI_CTRL_MEM_WIDTH                       0x40
-#define BF_EMI_CTRL_MEM_WIDTH(v)                    (((v) << 6) & 0x40)
-#define BP_EMI_CTRL_WRITE_PROTECT                   5
-#define BM_EMI_CTRL_WRITE_PROTECT                   0x20
-#define BF_EMI_CTRL_WRITE_PROTECT(v)                (((v) << 5) & 0x20)
-#define BP_EMI_CTRL_RESET_OUT                       4
-#define BM_EMI_CTRL_RESET_OUT                       0x10
-#define BF_EMI_CTRL_RESET_OUT(v)                    (((v) << 4) & 0x10)
-#define BP_EMI_CTRL_CE_SELECT                       0
-#define BM_EMI_CTRL_CE_SELECT                       0xf
-#define BV_EMI_CTRL_CE_SELECT__NONE                 0x0
-#define BV_EMI_CTRL_CE_SELECT__CE0                  0x1
-#define BV_EMI_CTRL_CE_SELECT__CE1                  0x2
-#define BV_EMI_CTRL_CE_SELECT__CE2                  0x4
-#define BV_EMI_CTRL_CE_SELECT__CE3                  0x8
-#define BF_EMI_CTRL_CE_SELECT(v)                    (((v) << 0) & 0xf)
-#define BF_EMI_CTRL_CE_SELECT_V(v)                  ((BV_EMI_CTRL_CE_SELECT__##v << 0) & 0xf)
-
-/**
- * Register: HW_EMI_STAT
- * Address: 0x10
- * SCT: no
-*/
-#define HW_EMI_STAT                         (*(volatile unsigned long *)(REGS_EMI_BASE + 0x10))
-#define BP_EMI_STAT_DRAM_PRESENT            31
-#define BM_EMI_STAT_DRAM_PRESENT            0x80000000
-#define BF_EMI_STAT_DRAM_PRESENT(v)         (((v) << 31) & 0x80000000)
-#define BP_EMI_STAT_NOR_PRESENT             30
-#define BM_EMI_STAT_NOR_PRESENT             0x40000000
-#define BF_EMI_STAT_NOR_PRESENT(v)          (((v) << 30) & 0x40000000)
-#define BP_EMI_STAT_LARGE_DRAM_ENABLED      29
-#define BM_EMI_STAT_LARGE_DRAM_ENABLED      0x20000000
-#define BF_EMI_STAT_LARGE_DRAM_ENABLED(v)   (((v) << 29) & 0x20000000)
-#define BP_EMI_STAT_RSVD0                   2
-#define BM_EMI_STAT_RSVD0                   0x1ffffffc
-#define BF_EMI_STAT_RSVD0(v)                (((v) << 2) & 0x1ffffffc)
-#define BP_EMI_STAT_DRAM_HALTED             1
-#define BM_EMI_STAT_DRAM_HALTED             0x2
-#define BV_EMI_STAT_DRAM_HALTED__NOT_HALTED 0x0
-#define BV_EMI_STAT_DRAM_HALTED__HALTED     0x1
-#define BF_EMI_STAT_DRAM_HALTED(v)          (((v) << 1) & 0x2)
-#define BF_EMI_STAT_DRAM_HALTED_V(v)        ((BV_EMI_STAT_DRAM_HALTED__##v << 1) & 0x2)
-#define BP_EMI_STAT_NOR_BUSY                0
-#define BM_EMI_STAT_NOR_BUSY                0x1
-#define BV_EMI_STAT_NOR_BUSY__NOT_BUSY      0x0
-#define BV_EMI_STAT_NOR_BUSY__BUSY          0x1
-#define BF_EMI_STAT_NOR_BUSY(v)             (((v) << 0) & 0x1)
-#define BF_EMI_STAT_NOR_BUSY_V(v)           ((BV_EMI_STAT_NOR_BUSY__##v << 0) & 0x1)
-
-/**
- * Register: HW_EMI_TIME
- * Address: 0x20
- * SCT: yes
-*/
-#define HW_EMI_TIME             (*(volatile unsigned long *)(REGS_EMI_BASE + 0x20 + 0x0))
-#define HW_EMI_TIME_SET         (*(volatile unsigned long *)(REGS_EMI_BASE + 0x20 + 0x4))
-#define HW_EMI_TIME_CLR         (*(volatile unsigned long *)(REGS_EMI_BASE + 0x20 + 0x8))
-#define HW_EMI_TIME_TOG         (*(volatile unsigned long *)(REGS_EMI_BASE + 0x20 + 0xc))
-#define BP_EMI_TIME_RSVD4       28
-#define BM_EMI_TIME_RSVD4       0xf0000000
-#define BF_EMI_TIME_RSVD4(v)    (((v) << 28) & 0xf0000000)
-#define BP_EMI_TIME_THZ         24
-#define BM_EMI_TIME_THZ         0xf000000
-#define BF_EMI_TIME_THZ(v)      (((v) << 24) & 0xf000000)
-#define BP_EMI_TIME_RSVD2       20
-#define BM_EMI_TIME_RSVD2       0xf00000
-#define BF_EMI_TIME_RSVD2(v)    (((v) << 20) & 0xf00000)
-#define BP_EMI_TIME_TDH         16
-#define BM_EMI_TIME_TDH         0xf0000
-#define BF_EMI_TIME_TDH(v)      (((v) << 16) & 0xf0000)
-#define BP_EMI_TIME_RSVD1       13
-#define BM_EMI_TIME_RSVD1       0xe000
-#define BF_EMI_TIME_RSVD1(v)    (((v) << 13) & 0xe000)
-#define BP_EMI_TIME_TDS         8
-#define BM_EMI_TIME_TDS         0x1f00
-#define BF_EMI_TIME_TDS(v)      (((v) << 8) & 0x1f00)
-#define BP_EMI_TIME_RSVD0       4
-#define BM_EMI_TIME_RSVD0       0xf0
-#define BF_EMI_TIME_RSVD0(v)    (((v) << 4) & 0xf0)
-#define BP_EMI_TIME_TAS         0
-#define BM_EMI_TIME_TAS         0xf
-#define BF_EMI_TIME_TAS(v)      (((v) << 0) & 0xf)
-
-/**
- * Register: HW_EMI_DDR_TEST_MODE_CSR
- * Address: 0x30
- * SCT: yes
-*/
-#define HW_EMI_DDR_TEST_MODE_CSR            (*(volatile unsigned long *)(REGS_EMI_BASE + 0x30 + 0x0))
-#define HW_EMI_DDR_TEST_MODE_CSR_SET        (*(volatile unsigned long *)(REGS_EMI_BASE + 0x30 + 0x4))
-#define HW_EMI_DDR_TEST_MODE_CSR_CLR        (*(volatile unsigned long *)(REGS_EMI_BASE + 0x30 + 0x8))
-#define HW_EMI_DDR_TEST_MODE_CSR_TOG        (*(volatile unsigned long *)(REGS_EMI_BASE + 0x30 + 0xc))
-#define BP_EMI_DDR_TEST_MODE_CSR_RSVD1      2
-#define BM_EMI_DDR_TEST_MODE_CSR_RSVD1      0xfffffffc
-#define BF_EMI_DDR_TEST_MODE_CSR_RSVD1(v)   (((v) << 2) & 0xfffffffc)
-#define BP_EMI_DDR_TEST_MODE_CSR_DONE       1
-#define BM_EMI_DDR_TEST_MODE_CSR_DONE       0x2
-#define BF_EMI_DDR_TEST_MODE_CSR_DONE(v)    (((v) << 1) & 0x2)
-#define BP_EMI_DDR_TEST_MODE_CSR_START      0
-#define BM_EMI_DDR_TEST_MODE_CSR_START      0x1
-#define BF_EMI_DDR_TEST_MODE_CSR_START(v)   (((v) << 0) & 0x1)
-
-/**
- * Register: HW_EMI_DEBUG
- * Address: 0x80
- * SCT: no
-*/
-#define HW_EMI_DEBUG                (*(volatile unsigned long *)(REGS_EMI_BASE + 0x80))
-#define BP_EMI_DEBUG_RSVD1          4
-#define BM_EMI_DEBUG_RSVD1          0xfffffff0
-#define BF_EMI_DEBUG_RSVD1(v)       (((v) << 4) & 0xfffffff0)
-#define BP_EMI_DEBUG_NOR_STATE      0
-#define BM_EMI_DEBUG_NOR_STATE      0xf
-#define BF_EMI_DEBUG_NOR_STATE(v)   (((v) << 0) & 0xf)
-
-/**
- * Register: HW_EMI_DDR_TEST_MODE_STATUS0
- * Address: 0x90
- * SCT: no
-*/
-#define HW_EMI_DDR_TEST_MODE_STATUS0            (*(volatile unsigned long *)(REGS_EMI_BASE + 0x90))
-#define BP_EMI_DDR_TEST_MODE_STATUS0_RSVD1      13
-#define BM_EMI_DDR_TEST_MODE_STATUS0_RSVD1      0xffffe000
-#define BF_EMI_DDR_TEST_MODE_STATUS0_RSVD1(v)   (((v) << 13) & 0xffffe000)
-#define BP_EMI_DDR_TEST_MODE_STATUS0_ADDR0      0
-#define BM_EMI_DDR_TEST_MODE_STATUS0_ADDR0      0x1fff
-#define BF_EMI_DDR_TEST_MODE_STATUS0_ADDR0(v)   (((v) << 0) & 0x1fff)
-
-/**
- * Register: HW_EMI_DDR_TEST_MODE_STATUS1
- * Address: 0xa0
- * SCT: no
-*/
-#define HW_EMI_DDR_TEST_MODE_STATUS1            (*(volatile unsigned long *)(REGS_EMI_BASE + 0xa0))
-#define BP_EMI_DDR_TEST_MODE_STATUS1_RSVD1      13
-#define BM_EMI_DDR_TEST_MODE_STATUS1_RSVD1      0xffffe000
-#define BF_EMI_DDR_TEST_MODE_STATUS1_RSVD1(v)   (((v) << 13) & 0xffffe000)
-#define BP_EMI_DDR_TEST_MODE_STATUS1_ADDR1      0
-#define BM_EMI_DDR_TEST_MODE_STATUS1_ADDR1      0x1fff
-#define BF_EMI_DDR_TEST_MODE_STATUS1_ADDR1(v)   (((v) << 0) & 0x1fff)
-
-/**
- * Register: HW_EMI_DDR_TEST_MODE_STATUS2
- * Address: 0xb0
- * SCT: no
-*/
-#define HW_EMI_DDR_TEST_MODE_STATUS2            (*(volatile unsigned long *)(REGS_EMI_BASE + 0xb0))
-#define BP_EMI_DDR_TEST_MODE_STATUS2_DATA0      0
-#define BM_EMI_DDR_TEST_MODE_STATUS2_DATA0      0xffffffff
-#define BF_EMI_DDR_TEST_MODE_STATUS2_DATA0(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_EMI_DDR_TEST_MODE_STATUS3
- * Address: 0xc0
- * SCT: no
-*/
-#define HW_EMI_DDR_TEST_MODE_STATUS3            (*(volatile unsigned long *)(REGS_EMI_BASE + 0xc0))
-#define BP_EMI_DDR_TEST_MODE_STATUS3_DATA1      0
-#define BM_EMI_DDR_TEST_MODE_STATUS3_DATA1      0xffffffff
-#define BF_EMI_DDR_TEST_MODE_STATUS3_DATA1(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_EMI_VERSION
- * Address: 0xf0
- * SCT: no
-*/
-#define HW_EMI_VERSION          (*(volatile unsigned long *)(REGS_EMI_BASE + 0xf0))
-#define BP_EMI_VERSION_MAJOR    24
-#define BM_EMI_VERSION_MAJOR    0xff000000
-#define BF_EMI_VERSION_MAJOR(v) (((v) << 24) & 0xff000000)
-#define BP_EMI_VERSION_MINOR    16
-#define BM_EMI_VERSION_MINOR    0xff0000
-#define BF_EMI_VERSION_MINOR(v) (((v) << 16) & 0xff0000)
-#define BP_EMI_VERSION_STEP     0
-#define BM_EMI_VERSION_STEP     0xffff
-#define BF_EMI_VERSION_STEP(v)  (((v) << 0) & 0xffff)
-
-#endif /* __HEADERGEN__IMX233__EMI__H__ */
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-gpmi.h b/firmware/target/arm/imx233/regs/imx233/regs-gpmi.h
deleted file mode 100644
index 1cb87e79c8..0000000000
--- a/firmware/target/arm/imx233/regs/imx233/regs-gpmi.h
+++ /dev/null
@@ -1,561 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: imx233:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__IMX233__GPMI__H__
-#define __HEADERGEN__IMX233__GPMI__H__
-
-#define REGS_GPMI_BASE (0x8000c000)
-
-#define REGS_GPMI_VERSION "3.2.0"
-
-/**
- * Register: HW_GPMI_CTRL0
- * Address: 0
- * SCT: yes
-*/
-#define HW_GPMI_CTRL0                                   (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x0 + 0x0))
-#define HW_GPMI_CTRL0_SET                               (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x0 + 0x4))
-#define HW_GPMI_CTRL0_CLR                               (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x0 + 0x8))
-#define HW_GPMI_CTRL0_TOG                               (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x0 + 0xc))
-#define BP_GPMI_CTRL0_SFTRST                            31
-#define BM_GPMI_CTRL0_SFTRST                            0x80000000
-#define BV_GPMI_CTRL0_SFTRST__RUN                       0x0
-#define BV_GPMI_CTRL0_SFTRST__RESET                     0x1
-#define BF_GPMI_CTRL0_SFTRST(v)                         (((v) << 31) & 0x80000000)
-#define BF_GPMI_CTRL0_SFTRST_V(v)                       ((BV_GPMI_CTRL0_SFTRST__##v << 31) & 0x80000000)
-#define BP_GPMI_CTRL0_CLKGATE                           30
-#define BM_GPMI_CTRL0_CLKGATE                           0x40000000
-#define BV_GPMI_CTRL0_CLKGATE__RUN                      0x0
-#define BV_GPMI_CTRL0_CLKGATE__NO_CLKS                  0x1
-#define BF_GPMI_CTRL0_CLKGATE(v)                        (((v) << 30) & 0x40000000)
-#define BF_GPMI_CTRL0_CLKGATE_V(v)                      ((BV_GPMI_CTRL0_CLKGATE__##v << 30) & 0x40000000)
-#define BP_GPMI_CTRL0_RUN                               29
-#define BM_GPMI_CTRL0_RUN                               0x20000000
-#define BV_GPMI_CTRL0_RUN__IDLE                         0x0
-#define BV_GPMI_CTRL0_RUN__BUSY                         0x1
-#define BF_GPMI_CTRL0_RUN(v)                            (((v) << 29) & 0x20000000)
-#define BF_GPMI_CTRL0_RUN_V(v)                          ((BV_GPMI_CTRL0_RUN__##v << 29) & 0x20000000)
-#define BP_GPMI_CTRL0_DEV_IRQ_EN                        28
-#define BM_GPMI_CTRL0_DEV_IRQ_EN                        0x10000000
-#define BF_GPMI_CTRL0_DEV_IRQ_EN(v)                     (((v) << 28) & 0x10000000)
-#define BP_GPMI_CTRL0_TIMEOUT_IRQ_EN                    27
-#define BM_GPMI_CTRL0_TIMEOUT_IRQ_EN                    0x8000000
-#define BF_GPMI_CTRL0_TIMEOUT_IRQ_EN(v)                 (((v) << 27) & 0x8000000)
-#define BP_GPMI_CTRL0_UDMA                              26
-#define BM_GPMI_CTRL0_UDMA                              0x4000000
-#define BV_GPMI_CTRL0_UDMA__DISABLED                    0x0
-#define BV_GPMI_CTRL0_UDMA__ENABLED                     0x1
-#define BF_GPMI_CTRL0_UDMA(v)                           (((v) << 26) & 0x4000000)
-#define BF_GPMI_CTRL0_UDMA_V(v)                         ((BV_GPMI_CTRL0_UDMA__##v << 26) & 0x4000000)
-#define BP_GPMI_CTRL0_COMMAND_MODE                      24
-#define BM_GPMI_CTRL0_COMMAND_MODE                      0x3000000
-#define BV_GPMI_CTRL0_COMMAND_MODE__WRITE               0x0
-#define BV_GPMI_CTRL0_COMMAND_MODE__READ                0x1
-#define BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE    0x2
-#define BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY      0x3
-#define BF_GPMI_CTRL0_COMMAND_MODE(v)                   (((v) << 24) & 0x3000000)
-#define BF_GPMI_CTRL0_COMMAND_MODE_V(v)                 ((BV_GPMI_CTRL0_COMMAND_MODE__##v << 24) & 0x3000000)
-#define BP_GPMI_CTRL0_WORD_LENGTH                       23
-#define BM_GPMI_CTRL0_WORD_LENGTH                       0x800000
-#define BV_GPMI_CTRL0_WORD_LENGTH__16_BIT               0x0
-#define BV_GPMI_CTRL0_WORD_LENGTH__8_BIT                0x1
-#define BF_GPMI_CTRL0_WORD_LENGTH(v)                    (((v) << 23) & 0x800000)
-#define BF_GPMI_CTRL0_WORD_LENGTH_V(v)                  ((BV_GPMI_CTRL0_WORD_LENGTH__##v << 23) & 0x800000)
-#define BP_GPMI_CTRL0_LOCK_CS                           22
-#define BM_GPMI_CTRL0_LOCK_CS                           0x400000
-#define BV_GPMI_CTRL0_LOCK_CS__DISABLED                 0x0
-#define BV_GPMI_CTRL0_LOCK_CS__ENABLED                  0x1
-#define BF_GPMI_CTRL0_LOCK_CS(v)                        (((v) << 22) & 0x400000)
-#define BF_GPMI_CTRL0_LOCK_CS_V(v)                      ((BV_GPMI_CTRL0_LOCK_CS__##v << 22) & 0x400000)
-#define BP_GPMI_CTRL0_CS                                20
-#define BM_GPMI_CTRL0_CS                                0x300000
-#define BF_GPMI_CTRL0_CS(v)                             (((v) << 20) & 0x300000)
-#define BP_GPMI_CTRL0_ADDRESS                           17
-#define BM_GPMI_CTRL0_ADDRESS                           0xe0000
-#define BV_GPMI_CTRL0_ADDRESS__NAND_DATA                0x0
-#define BV_GPMI_CTRL0_ADDRESS__NAND_CLE                 0x1
-#define BV_GPMI_CTRL0_ADDRESS__NAND_ALE                 0x2
-#define BF_GPMI_CTRL0_ADDRESS(v)                        (((v) << 17) & 0xe0000)
-#define BF_GPMI_CTRL0_ADDRESS_V(v)                      ((BV_GPMI_CTRL0_ADDRESS__##v << 17) & 0xe0000)
-#define BP_GPMI_CTRL0_ADDRESS_INCREMENT                 16
-#define BM_GPMI_CTRL0_ADDRESS_INCREMENT                 0x10000
-#define BV_GPMI_CTRL0_ADDRESS_INCREMENT__DISABLED       0x0
-#define BV_GPMI_CTRL0_ADDRESS_INCREMENT__ENABLED        0x1
-#define BF_GPMI_CTRL0_ADDRESS_INCREMENT(v)              (((v) << 16) & 0x10000)
-#define BF_GPMI_CTRL0_ADDRESS_INCREMENT_V(v)            ((BV_GPMI_CTRL0_ADDRESS_INCREMENT__##v << 16) & 0x10000)
-#define BP_GPMI_CTRL0_XFER_COUNT                        0
-#define BM_GPMI_CTRL0_XFER_COUNT                        0xffff
-#define BF_GPMI_CTRL0_XFER_COUNT(v)                     (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_GPMI_COMPARE
- * Address: 0x10
- * SCT: no
-*/
-#define HW_GPMI_COMPARE                 (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x10))
-#define BP_GPMI_COMPARE_MASK            16
-#define BM_GPMI_COMPARE_MASK            0xffff0000
-#define BF_GPMI_COMPARE_MASK(v)         (((v) << 16) & 0xffff0000)
-#define BP_GPMI_COMPARE_REFERENCE       0
-#define BM_GPMI_COMPARE_REFERENCE       0xffff
-#define BF_GPMI_COMPARE_REFERENCE(v)    (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_GPMI_ECCCTRL
- * Address: 0x20
- * SCT: yes
-*/
-#define HW_GPMI_ECCCTRL                             (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x20 + 0x0))
-#define HW_GPMI_ECCCTRL_SET                         (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x20 + 0x4))
-#define HW_GPMI_ECCCTRL_CLR                         (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x20 + 0x8))
-#define HW_GPMI_ECCCTRL_TOG                         (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x20 + 0xc))
-#define BP_GPMI_ECCCTRL_HANDLE                      16
-#define BM_GPMI_ECCCTRL_HANDLE                      0xffff0000
-#define BF_GPMI_ECCCTRL_HANDLE(v)                   (((v) << 16) & 0xffff0000)
-#define BP_GPMI_ECCCTRL_RSVD2                       15
-#define BM_GPMI_ECCCTRL_RSVD2                       0x8000
-#define BF_GPMI_ECCCTRL_RSVD2(v)                    (((v) << 15) & 0x8000)
-#define BP_GPMI_ECCCTRL_ECC_CMD                     13
-#define BM_GPMI_ECCCTRL_ECC_CMD                     0x6000
-#define BV_GPMI_ECCCTRL_ECC_CMD__DECODE_4_BIT       0x0
-#define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE_4_BIT       0x1
-#define BV_GPMI_ECCCTRL_ECC_CMD__DECODE_8_BIT       0x2
-#define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE_8_BIT       0x3
-#define BF_GPMI_ECCCTRL_ECC_CMD(v)                  (((v) << 13) & 0x6000)
-#define BF_GPMI_ECCCTRL_ECC_CMD_V(v)                ((BV_GPMI_ECCCTRL_ECC_CMD__##v << 13) & 0x6000)
-#define BP_GPMI_ECCCTRL_ENABLE_ECC                  12
-#define BM_GPMI_ECCCTRL_ENABLE_ECC                  0x1000
-#define BV_GPMI_ECCCTRL_ENABLE_ECC__ENABLE          0x1
-#define BV_GPMI_ECCCTRL_ENABLE_ECC__DISABLE         0x0
-#define BF_GPMI_ECCCTRL_ENABLE_ECC(v)               (((v) << 12) & 0x1000)
-#define BF_GPMI_ECCCTRL_ENABLE_ECC_V(v)             ((BV_GPMI_ECCCTRL_ENABLE_ECC__##v << 12) & 0x1000)
-#define BP_GPMI_ECCCTRL_RSVD1                       9
-#define BM_GPMI_ECCCTRL_RSVD1                       0xe00
-#define BF_GPMI_ECCCTRL_RSVD1(v)                    (((v) << 9) & 0xe00)
-#define BP_GPMI_ECCCTRL_BUFFER_MASK                 0
-#define BM_GPMI_ECCCTRL_BUFFER_MASK                 0x1ff
-#define BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY    0x100
-#define BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE       0x1ff
-#define BV_GPMI_ECCCTRL_BUFFER_MASK__AUXILIARY      0x100
-#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER7        0x80
-#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER6        0x40
-#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER5        0x20
-#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER4        0x10
-#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER3        0x8
-#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER2        0x4
-#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER1        0x2
-#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER0        0x1
-#define BF_GPMI_ECCCTRL_BUFFER_MASK(v)              (((v) << 0) & 0x1ff)
-#define BF_GPMI_ECCCTRL_BUFFER_MASK_V(v)            ((BV_GPMI_ECCCTRL_BUFFER_MASK__##v << 0) & 0x1ff)
-
-/**
- * Register: HW_GPMI_ECCCOUNT
- * Address: 0x30
- * SCT: no
-*/
-#define HW_GPMI_ECCCOUNT            (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x30))
-#define BP_GPMI_ECCCOUNT_RSVD2      16
-#define BM_GPMI_ECCCOUNT_RSVD2      0xffff0000
-#define BF_GPMI_ECCCOUNT_RSVD2(v)   (((v) << 16) & 0xffff0000)
-#define BP_GPMI_ECCCOUNT_COUNT      0
-#define BM_GPMI_ECCCOUNT_COUNT      0xffff
-#define BF_GPMI_ECCCOUNT_COUNT(v)   (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_GPMI_PAYLOAD
- * Address: 0x40
- * SCT: no
-*/
-#define HW_GPMI_PAYLOAD             (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x40))
-#define BP_GPMI_PAYLOAD_ADDRESS     2
-#define BM_GPMI_PAYLOAD_ADDRESS     0xfffffffc
-#define BF_GPMI_PAYLOAD_ADDRESS(v)  (((v) << 2) & 0xfffffffc)
-#define BP_GPMI_PAYLOAD_RSVD0       0
-#define BM_GPMI_PAYLOAD_RSVD0       0x3
-#define BF_GPMI_PAYLOAD_RSVD0(v)    (((v) << 0) & 0x3)
-
-/**
- * Register: HW_GPMI_AUXILIARY
- * Address: 0x50
- * SCT: no
-*/
-#define HW_GPMI_AUXILIARY               (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x50))
-#define BP_GPMI_AUXILIARY_ADDRESS       2
-#define BM_GPMI_AUXILIARY_ADDRESS       0xfffffffc
-#define BF_GPMI_AUXILIARY_ADDRESS(v)    (((v) << 2) & 0xfffffffc)
-#define BP_GPMI_AUXILIARY_RSVD0         0
-#define BM_GPMI_AUXILIARY_RSVD0         0x3
-#define BF_GPMI_AUXILIARY_RSVD0(v)      (((v) << 0) & 0x3)
-
-/**
- * Register: HW_GPMI_CTRL1
- * Address: 0x60
- * SCT: yes
-*/
-#define HW_GPMI_CTRL1                                   (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x60 + 0x0))
-#define HW_GPMI_CTRL1_SET                               (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x60 + 0x4))
-#define HW_GPMI_CTRL1_CLR                               (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x60 + 0x8))
-#define HW_GPMI_CTRL1_TOG                               (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x60 + 0xc))
-#define BP_GPMI_CTRL1_RSVD2                             24
-#define BM_GPMI_CTRL1_RSVD2                             0xff000000
-#define BF_GPMI_CTRL1_RSVD2(v)                          (((v) << 24) & 0xff000000)
-#define BP_GPMI_CTRL1_CE3_SEL                           23
-#define BM_GPMI_CTRL1_CE3_SEL                           0x800000
-#define BF_GPMI_CTRL1_CE3_SEL(v)                        (((v) << 23) & 0x800000)
-#define BP_GPMI_CTRL1_CE2_SEL                           22
-#define BM_GPMI_CTRL1_CE2_SEL                           0x400000
-#define BF_GPMI_CTRL1_CE2_SEL(v)                        (((v) << 22) & 0x400000)
-#define BP_GPMI_CTRL1_CE1_SEL                           21
-#define BM_GPMI_CTRL1_CE1_SEL                           0x200000
-#define BF_GPMI_CTRL1_CE1_SEL(v)                        (((v) << 21) & 0x200000)
-#define BP_GPMI_CTRL1_CE0_SEL                           20
-#define BM_GPMI_CTRL1_CE0_SEL                           0x100000
-#define BF_GPMI_CTRL1_CE0_SEL(v)                        (((v) << 20) & 0x100000)
-#define BP_GPMI_CTRL1_GANGED_RDYBUSY                    19
-#define BM_GPMI_CTRL1_GANGED_RDYBUSY                    0x80000
-#define BF_GPMI_CTRL1_GANGED_RDYBUSY(v)                 (((v) << 19) & 0x80000)
-#define BP_GPMI_CTRL1_BCH_MODE                          18
-#define BM_GPMI_CTRL1_BCH_MODE                          0x40000
-#define BF_GPMI_CTRL1_BCH_MODE(v)                       (((v) << 18) & 0x40000)
-#define BP_GPMI_CTRL1_DLL_ENABLE                        17
-#define BM_GPMI_CTRL1_DLL_ENABLE                        0x20000
-#define BF_GPMI_CTRL1_DLL_ENABLE(v)                     (((v) << 17) & 0x20000)
-#define BP_GPMI_CTRL1_HALF_PERIOD                       16
-#define BM_GPMI_CTRL1_HALF_PERIOD                       0x10000
-#define BF_GPMI_CTRL1_HALF_PERIOD(v)                    (((v) << 16) & 0x10000)
-#define BP_GPMI_CTRL1_RDN_DELAY                         12
-#define BM_GPMI_CTRL1_RDN_DELAY                         0xf000
-#define BF_GPMI_CTRL1_RDN_DELAY(v)                      (((v) << 12) & 0xf000)
-#define BP_GPMI_CTRL1_DMA2ECC_MODE                      11
-#define BM_GPMI_CTRL1_DMA2ECC_MODE                      0x800
-#define BF_GPMI_CTRL1_DMA2ECC_MODE(v)                   (((v) << 11) & 0x800)
-#define BP_GPMI_CTRL1_DEV_IRQ                           10
-#define BM_GPMI_CTRL1_DEV_IRQ                           0x400
-#define BF_GPMI_CTRL1_DEV_IRQ(v)                        (((v) << 10) & 0x400)
-#define BP_GPMI_CTRL1_TIMEOUT_IRQ                       9
-#define BM_GPMI_CTRL1_TIMEOUT_IRQ                       0x200
-#define BF_GPMI_CTRL1_TIMEOUT_IRQ(v)                    (((v) << 9) & 0x200)
-#define BP_GPMI_CTRL1_BURST_EN                          8
-#define BM_GPMI_CTRL1_BURST_EN                          0x100
-#define BF_GPMI_CTRL1_BURST_EN(v)                       (((v) << 8) & 0x100)
-#define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY3             7
-#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY3             0x80
-#define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY3(v)          (((v) << 7) & 0x80)
-#define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY2             6
-#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY2             0x40
-#define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY2(v)          (((v) << 6) & 0x40)
-#define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY1             5
-#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY1             0x20
-#define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY1(v)          (((v) << 5) & 0x20)
-#define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY0             4
-#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY0             0x10
-#define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY0(v)          (((v) << 4) & 0x10)
-#define BP_GPMI_CTRL1_DEV_RESET                         3
-#define BM_GPMI_CTRL1_DEV_RESET                         0x8
-#define BV_GPMI_CTRL1_DEV_RESET__ENABLED                0x0
-#define BV_GPMI_CTRL1_DEV_RESET__DISABLED               0x1
-#define BF_GPMI_CTRL1_DEV_RESET(v)                      (((v) << 3) & 0x8)
-#define BF_GPMI_CTRL1_DEV_RESET_V(v)                    ((BV_GPMI_CTRL1_DEV_RESET__##v << 3) & 0x8)
-#define BP_GPMI_CTRL1_ATA_IRQRDY_POLARITY               2
-#define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY               0x4
-#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVELOW    0x0
-#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVEHIGH   0x1
-#define BF_GPMI_CTRL1_ATA_IRQRDY_POLARITY(v)            (((v) << 2) & 0x4)
-#define BF_GPMI_CTRL1_ATA_IRQRDY_POLARITY_V(v)          ((BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__##v << 2) & 0x4)
-#define BP_GPMI_CTRL1_CAMERA_MODE                       1
-#define BM_GPMI_CTRL1_CAMERA_MODE                       0x2
-#define BF_GPMI_CTRL1_CAMERA_MODE(v)                    (((v) << 1) & 0x2)
-#define BP_GPMI_CTRL1_GPMI_MODE                         0
-#define BM_GPMI_CTRL1_GPMI_MODE                         0x1
-#define BV_GPMI_CTRL1_GPMI_MODE__NAND                   0x0
-#define BV_GPMI_CTRL1_GPMI_MODE__ATA                    0x1
-#define BF_GPMI_CTRL1_GPMI_MODE(v)                      (((v) << 0) & 0x1)
-#define BF_GPMI_CTRL1_GPMI_MODE_V(v)                    ((BV_GPMI_CTRL1_GPMI_MODE__##v << 0) & 0x1)
-
-/**
- * Register: HW_GPMI_TIMING0
- * Address: 0x70
- * SCT: no
-*/
-#define HW_GPMI_TIMING0                     (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x70))
-#define BP_GPMI_TIMING0_RSVD1               24
-#define BM_GPMI_TIMING0_RSVD1               0xff000000
-#define BF_GPMI_TIMING0_RSVD1(v)            (((v) << 24) & 0xff000000)
-#define BP_GPMI_TIMING0_ADDRESS_SETUP       16
-#define BM_GPMI_TIMING0_ADDRESS_SETUP       0xff0000
-#define BF_GPMI_TIMING0_ADDRESS_SETUP(v)    (((v) << 16) & 0xff0000)
-#define BP_GPMI_TIMING0_DATA_HOLD           8
-#define BM_GPMI_TIMING0_DATA_HOLD           0xff00
-#define BF_GPMI_TIMING0_DATA_HOLD(v)        (((v) << 8) & 0xff00)
-#define BP_GPMI_TIMING0_DATA_SETUP          0
-#define BM_GPMI_TIMING0_DATA_SETUP          0xff
-#define BF_GPMI_TIMING0_DATA_SETUP(v)       (((v) << 0) & 0xff)
-
-/**
- * Register: HW_GPMI_TIMING1
- * Address: 0x80
- * SCT: no
-*/
-#define HW_GPMI_TIMING1                         (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x80))
-#define BP_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT     16
-#define BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT     0xffff0000
-#define BF_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(v)  (((v) << 16) & 0xffff0000)
-#define BP_GPMI_TIMING1_RSVD1                   0
-#define BM_GPMI_TIMING1_RSVD1                   0xffff
-#define BF_GPMI_TIMING1_RSVD1(v)                (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_GPMI_TIMING2
- * Address: 0x90
- * SCT: no
-*/
-#define HW_GPMI_TIMING2                 (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x90))
-#define BP_GPMI_TIMING2_UDMA_TRP        24
-#define BM_GPMI_TIMING2_UDMA_TRP        0xff000000
-#define BF_GPMI_TIMING2_UDMA_TRP(v)     (((v) << 24) & 0xff000000)
-#define BP_GPMI_TIMING2_UDMA_ENV        16
-#define BM_GPMI_TIMING2_UDMA_ENV        0xff0000
-#define BF_GPMI_TIMING2_UDMA_ENV(v)     (((v) << 16) & 0xff0000)
-#define BP_GPMI_TIMING2_UDMA_HOLD       8
-#define BM_GPMI_TIMING2_UDMA_HOLD       0xff00
-#define BF_GPMI_TIMING2_UDMA_HOLD(v)    (((v) << 8) & 0xff00)
-#define BP_GPMI_TIMING2_UDMA_SETUP      0
-#define BM_GPMI_TIMING2_UDMA_SETUP      0xff
-#define BF_GPMI_TIMING2_UDMA_SETUP(v)   (((v) << 0) & 0xff)
-
-/**
- * Register: HW_GPMI_DATA
- * Address: 0xa0
- * SCT: no
-*/
-#define HW_GPMI_DATA            (*(volatile unsigned long *)(REGS_GPMI_BASE + 0xa0))
-#define BP_GPMI_DATA_DATA       0
-#define BM_GPMI_DATA_DATA       0xffffffff
-#define BF_GPMI_DATA_DATA(v)    (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_GPMI_STAT
- * Address: 0xb0
- * SCT: no
-*/
-#define HW_GPMI_STAT                        (*(volatile unsigned long *)(REGS_GPMI_BASE + 0xb0))
-#define BP_GPMI_STAT_PRESENT                31
-#define BM_GPMI_STAT_PRESENT                0x80000000
-#define BV_GPMI_STAT_PRESENT__UNAVAILABLE   0x0
-#define BV_GPMI_STAT_PRESENT__AVAILABLE     0x1
-#define BF_GPMI_STAT_PRESENT(v)             (((v) << 31) & 0x80000000)
-#define BF_GPMI_STAT_PRESENT_V(v)           ((BV_GPMI_STAT_PRESENT__##v << 31) & 0x80000000)
-#define BP_GPMI_STAT_RSVD1                  12
-#define BM_GPMI_STAT_RSVD1                  0x7ffff000
-#define BF_GPMI_STAT_RSVD1(v)               (((v) << 12) & 0x7ffff000)
-#define BP_GPMI_STAT_RDY_TIMEOUT            8
-#define BM_GPMI_STAT_RDY_TIMEOUT            0xf00
-#define BF_GPMI_STAT_RDY_TIMEOUT(v)         (((v) << 8) & 0xf00)
-#define BP_GPMI_STAT_ATA_IRQ                7
-#define BM_GPMI_STAT_ATA_IRQ                0x80
-#define BF_GPMI_STAT_ATA_IRQ(v)             (((v) << 7) & 0x80)
-#define BP_GPMI_STAT_INVALID_BUFFER_MASK    6
-#define BM_GPMI_STAT_INVALID_BUFFER_MASK    0x40
-#define BF_GPMI_STAT_INVALID_BUFFER_MASK(v) (((v) << 6) & 0x40)
-#define BP_GPMI_STAT_FIFO_EMPTY             5
-#define BM_GPMI_STAT_FIFO_EMPTY             0x20
-#define BV_GPMI_STAT_FIFO_EMPTY__NOT_EMPTY  0x0
-#define BV_GPMI_STAT_FIFO_EMPTY__EMPTY      0x1
-#define BF_GPMI_STAT_FIFO_EMPTY(v)          (((v) << 5) & 0x20)
-#define BF_GPMI_STAT_FIFO_EMPTY_V(v)        ((BV_GPMI_STAT_FIFO_EMPTY__##v << 5) & 0x20)
-#define BP_GPMI_STAT_FIFO_FULL              4
-#define BM_GPMI_STAT_FIFO_FULL              0x10
-#define BV_GPMI_STAT_FIFO_FULL__NOT_FULL    0x0
-#define BV_GPMI_STAT_FIFO_FULL__FULL        0x1
-#define BF_GPMI_STAT_FIFO_FULL(v)           (((v) << 4) & 0x10)
-#define BF_GPMI_STAT_FIFO_FULL_V(v)         ((BV_GPMI_STAT_FIFO_FULL__##v << 4) & 0x10)
-#define BP_GPMI_STAT_DEV3_ERROR             3
-#define BM_GPMI_STAT_DEV3_ERROR             0x8
-#define BF_GPMI_STAT_DEV3_ERROR(v)          (((v) << 3) & 0x8)
-#define BP_GPMI_STAT_DEV2_ERROR             2
-#define BM_GPMI_STAT_DEV2_ERROR             0x4
-#define BF_GPMI_STAT_DEV2_ERROR(v)          (((v) << 2) & 0x4)
-#define BP_GPMI_STAT_DEV1_ERROR             1
-#define BM_GPMI_STAT_DEV1_ERROR             0x2
-#define BF_GPMI_STAT_DEV1_ERROR(v)          (((v) << 1) & 0x2)
-#define BP_GPMI_STAT_DEV0_ERROR             0
-#define BM_GPMI_STAT_DEV0_ERROR             0x1
-#define BF_GPMI_STAT_DEV0_ERROR(v)          (((v) << 0) & 0x1)
-
-/**
- * Register: HW_GPMI_DEBUG
- * Address: 0xc0
- * SCT: no
-*/
-#define HW_GPMI_DEBUG                           (*(volatile unsigned long *)(REGS_GPMI_BASE + 0xc0))
-#define BP_GPMI_DEBUG_READY3                    31
-#define BM_GPMI_DEBUG_READY3                    0x80000000
-#define BF_GPMI_DEBUG_READY3(v)                 (((v) << 31) & 0x80000000)
-#define BP_GPMI_DEBUG_READY2                    30
-#define BM_GPMI_DEBUG_READY2                    0x40000000
-#define BF_GPMI_DEBUG_READY2(v)                 (((v) << 30) & 0x40000000)
-#define BP_GPMI_DEBUG_READY1                    29
-#define BM_GPMI_DEBUG_READY1                    0x20000000
-#define BF_GPMI_DEBUG_READY1(v)                 (((v) << 29) & 0x20000000)
-#define BP_GPMI_DEBUG_READY0                    28
-#define BM_GPMI_DEBUG_READY0                    0x10000000
-#define BF_GPMI_DEBUG_READY0(v)                 (((v) << 28) & 0x10000000)
-#define BP_GPMI_DEBUG_WAIT_FOR_READY_END3       27
-#define BM_GPMI_DEBUG_WAIT_FOR_READY_END3       0x8000000
-#define BF_GPMI_DEBUG_WAIT_FOR_READY_END3(v)    (((v) << 27) & 0x8000000)
-#define BP_GPMI_DEBUG_WAIT_FOR_READY_END2       26
-#define BM_GPMI_DEBUG_WAIT_FOR_READY_END2       0x4000000
-#define BF_GPMI_DEBUG_WAIT_FOR_READY_END2(v)    (((v) << 26) & 0x4000000)
-#define BP_GPMI_DEBUG_WAIT_FOR_READY_END1       25
-#define BM_GPMI_DEBUG_WAIT_FOR_READY_END1       0x2000000
-#define BF_GPMI_DEBUG_WAIT_FOR_READY_END1(v)    (((v) << 25) & 0x2000000)
-#define BP_GPMI_DEBUG_WAIT_FOR_READY_END0       24
-#define BM_GPMI_DEBUG_WAIT_FOR_READY_END0       0x1000000
-#define BF_GPMI_DEBUG_WAIT_FOR_READY_END0(v)    (((v) << 24) & 0x1000000)
-#define BP_GPMI_DEBUG_SENSE3                    23
-#define BM_GPMI_DEBUG_SENSE3                    0x800000
-#define BF_GPMI_DEBUG_SENSE3(v)                 (((v) << 23) & 0x800000)
-#define BP_GPMI_DEBUG_SENSE2                    22
-#define BM_GPMI_DEBUG_SENSE2                    0x400000
-#define BF_GPMI_DEBUG_SENSE2(v)                 (((v) << 22) & 0x400000)
-#define BP_GPMI_DEBUG_SENSE1                    21
-#define BM_GPMI_DEBUG_SENSE1                    0x200000
-#define BF_GPMI_DEBUG_SENSE1(v)                 (((v) << 21) & 0x200000)
-#define BP_GPMI_DEBUG_SENSE0                    20
-#define BM_GPMI_DEBUG_SENSE0                    0x100000
-#define BF_GPMI_DEBUG_SENSE0(v)                 (((v) << 20) & 0x100000)
-#define BP_GPMI_DEBUG_DMAREQ3                   19
-#define BM_GPMI_DEBUG_DMAREQ3                   0x80000
-#define BF_GPMI_DEBUG_DMAREQ3(v)                (((v) << 19) & 0x80000)
-#define BP_GPMI_DEBUG_DMAREQ2                   18
-#define BM_GPMI_DEBUG_DMAREQ2                   0x40000
-#define BF_GPMI_DEBUG_DMAREQ2(v)                (((v) << 18) & 0x40000)
-#define BP_GPMI_DEBUG_DMAREQ1                   17
-#define BM_GPMI_DEBUG_DMAREQ1                   0x20000
-#define BF_GPMI_DEBUG_DMAREQ1(v)                (((v) << 17) & 0x20000)
-#define BP_GPMI_DEBUG_DMAREQ0                   16
-#define BM_GPMI_DEBUG_DMAREQ0                   0x10000
-#define BF_GPMI_DEBUG_DMAREQ0(v)                (((v) << 16) & 0x10000)
-#define BP_GPMI_DEBUG_CMD_END                   12
-#define BM_GPMI_DEBUG_CMD_END                   0xf000
-#define BF_GPMI_DEBUG_CMD_END(v)                (((v) << 12) & 0xf000)
-#define BP_GPMI_DEBUG_UDMA_STATE                8
-#define BM_GPMI_DEBUG_UDMA_STATE                0xf00
-#define BF_GPMI_DEBUG_UDMA_STATE(v)             (((v) << 8) & 0xf00)
-#define BP_GPMI_DEBUG_BUSY                      7
-#define BM_GPMI_DEBUG_BUSY                      0x80
-#define BV_GPMI_DEBUG_BUSY__DISABLED            0x0
-#define BV_GPMI_DEBUG_BUSY__ENABLED             0x1
-#define BF_GPMI_DEBUG_BUSY(v)                   (((v) << 7) & 0x80)
-#define BF_GPMI_DEBUG_BUSY_V(v)                 ((BV_GPMI_DEBUG_BUSY__##v << 7) & 0x80)
-#define BP_GPMI_DEBUG_PIN_STATE                 4
-#define BM_GPMI_DEBUG_PIN_STATE                 0x70
-#define BV_GPMI_DEBUG_PIN_STATE__PSM_IDLE       0x0
-#define BV_GPMI_DEBUG_PIN_STATE__PSM_BYTCNT     0x1
-#define BV_GPMI_DEBUG_PIN_STATE__PSM_ADDR       0x2
-#define BV_GPMI_DEBUG_PIN_STATE__PSM_STALL      0x3
-#define BV_GPMI_DEBUG_PIN_STATE__PSM_STROBE     0x4
-#define BV_GPMI_DEBUG_PIN_STATE__PSM_ATARDY     0x5
-#define BV_GPMI_DEBUG_PIN_STATE__PSM_DHOLD      0x6
-#define BV_GPMI_DEBUG_PIN_STATE__PSM_DONE       0x7
-#define BF_GPMI_DEBUG_PIN_STATE(v)              (((v) << 4) & 0x70)
-#define BF_GPMI_DEBUG_PIN_STATE_V(v)            ((BV_GPMI_DEBUG_PIN_STATE__##v << 4) & 0x70)
-#define BP_GPMI_DEBUG_MAIN_STATE                0
-#define BM_GPMI_DEBUG_MAIN_STATE                0xf
-#define BV_GPMI_DEBUG_MAIN_STATE__MSM_IDLE      0x0
-#define BV_GPMI_DEBUG_MAIN_STATE__MSM_BYTCNT    0x1
-#define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFE    0x2
-#define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFR    0x3
-#define BV_GPMI_DEBUG_MAIN_STATE__MSM_DMAREQ    0x4
-#define BV_GPMI_DEBUG_MAIN_STATE__MSM_DMAACK    0x5
-#define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFF    0x6
-#define BV_GPMI_DEBUG_MAIN_STATE__MSM_LDFIFO    0x7
-#define BV_GPMI_DEBUG_MAIN_STATE__MSM_LDDMAR    0x8
-#define BV_GPMI_DEBUG_MAIN_STATE__MSM_RDCMP     0x9
-#define BV_GPMI_DEBUG_MAIN_STATE__MSM_DONE      0xa
-#define BF_GPMI_DEBUG_MAIN_STATE(v)             (((v) << 0) & 0xf)
-#define BF_GPMI_DEBUG_MAIN_STATE_V(v)           ((BV_GPMI_DEBUG_MAIN_STATE__##v << 0) & 0xf)
-
-/**
- * Register: HW_GPMI_VERSION
- * Address: 0xd0
- * SCT: no
-*/
-#define HW_GPMI_VERSION             (*(volatile unsigned long *)(REGS_GPMI_BASE + 0xd0))
-#define BP_GPMI_VERSION_MAJOR       24
-#define BM_GPMI_VERSION_MAJOR       0xff000000
-#define BF_GPMI_VERSION_MAJOR(v)    (((v) << 24) & 0xff000000)
-#define BP_GPMI_VERSION_MINOR       16
-#define BM_GPMI_VERSION_MINOR       0xff0000
-#define BF_GPMI_VERSION_MINOR(v)    (((v) << 16) & 0xff0000)
-#define BP_GPMI_VERSION_STEP        0
-#define BM_GPMI_VERSION_STEP        0xffff
-#define BF_GPMI_VERSION_STEP(v)     (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_GPMI_DEBUG2
- * Address: 0xe0
- * SCT: no
-*/
-#define HW_GPMI_DEBUG2                      (*(volatile unsigned long *)(REGS_GPMI_BASE + 0xe0))
-#define BP_GPMI_DEBUG2_RSVD1                16
-#define BM_GPMI_DEBUG2_RSVD1                0xffff0000
-#define BF_GPMI_DEBUG2_RSVD1(v)             (((v) << 16) & 0xffff0000)
-#define BP_GPMI_DEBUG2_SYND2GPMI_BE         12
-#define BM_GPMI_DEBUG2_SYND2GPMI_BE         0xf000
-#define BF_GPMI_DEBUG2_SYND2GPMI_BE(v)      (((v) << 12) & 0xf000)
-#define BP_GPMI_DEBUG2_GPMI2SYND_VALID      11
-#define BM_GPMI_DEBUG2_GPMI2SYND_VALID      0x800
-#define BF_GPMI_DEBUG2_GPMI2SYND_VALID(v)   (((v) << 11) & 0x800)
-#define BP_GPMI_DEBUG2_GPMI2SYND_READY      10
-#define BM_GPMI_DEBUG2_GPMI2SYND_READY      0x400
-#define BF_GPMI_DEBUG2_GPMI2SYND_READY(v)   (((v) << 10) & 0x400)
-#define BP_GPMI_DEBUG2_SYND2GPMI_VALID      9
-#define BM_GPMI_DEBUG2_SYND2GPMI_VALID      0x200
-#define BF_GPMI_DEBUG2_SYND2GPMI_VALID(v)   (((v) << 9) & 0x200)
-#define BP_GPMI_DEBUG2_SYND2GPMI_READY      8
-#define BM_GPMI_DEBUG2_SYND2GPMI_READY      0x100
-#define BF_GPMI_DEBUG2_SYND2GPMI_READY(v)   (((v) << 8) & 0x100)
-#define BP_GPMI_DEBUG2_VIEW_DELAYED_RDN     7
-#define BM_GPMI_DEBUG2_VIEW_DELAYED_RDN     0x80
-#define BF_GPMI_DEBUG2_VIEW_DELAYED_RDN(v)  (((v) << 7) & 0x80)
-#define BP_GPMI_DEBUG2_UPDATE_WINDOW        6
-#define BM_GPMI_DEBUG2_UPDATE_WINDOW        0x40
-#define BF_GPMI_DEBUG2_UPDATE_WINDOW(v)     (((v) << 6) & 0x40)
-#define BP_GPMI_DEBUG2_RDN_TAP              0
-#define BM_GPMI_DEBUG2_RDN_TAP              0x3f
-#define BF_GPMI_DEBUG2_RDN_TAP(v)           (((v) << 0) & 0x3f)
-
-/**
- * Register: HW_GPMI_DEBUG3
- * Address: 0xf0
- * SCT: no
-*/
-#define HW_GPMI_DEBUG3                  (*(volatile unsigned long *)(REGS_GPMI_BASE + 0xf0))
-#define BP_GPMI_DEBUG3_APB_WORD_CNTR    16
-#define BM_GPMI_DEBUG3_APB_WORD_CNTR    0xffff0000
-#define BF_GPMI_DEBUG3_APB_WORD_CNTR(v) (((v) << 16) & 0xffff0000)
-#define BP_GPMI_DEBUG3_DEV_WORD_CNTR    0
-#define BM_GPMI_DEBUG3_DEV_WORD_CNTR    0xffff
-#define BF_GPMI_DEBUG3_DEV_WORD_CNTR(v) (((v) << 0) & 0xffff)
-
-#endif /* __HEADERGEN__IMX233__GPMI__H__ */
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-i2c.h b/firmware/target/arm/imx233/regs/imx233/regs-i2c.h
deleted file mode 100644
index 430603e9cf..0000000000
--- a/firmware/target/arm/imx233/regs/imx233/regs-i2c.h
+++ /dev/null
@@ -1,597 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: imx233:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__IMX233__I2C__H__
-#define __HEADERGEN__IMX233__I2C__H__
-
-#define REGS_I2C_BASE (0x80058000)
-
-#define REGS_I2C_VERSION "3.2.0"
-
-/**
- * Register: HW_I2C_CTRL0
- * Address: 0
- * SCT: yes
-*/
-#define HW_I2C_CTRL0                                (*(volatile unsigned long *)(REGS_I2C_BASE + 0x0 + 0x0))
-#define HW_I2C_CTRL0_SET                            (*(volatile unsigned long *)(REGS_I2C_BASE + 0x0 + 0x4))
-#define HW_I2C_CTRL0_CLR                            (*(volatile unsigned long *)(REGS_I2C_BASE + 0x0 + 0x8))
-#define HW_I2C_CTRL0_TOG                            (*(volatile unsigned long *)(REGS_I2C_BASE + 0x0 + 0xc))
-#define BP_I2C_CTRL0_SFTRST                         31
-#define BM_I2C_CTRL0_SFTRST                         0x80000000
-#define BV_I2C_CTRL0_SFTRST__RUN                    0x0
-#define BV_I2C_CTRL0_SFTRST__RESET                  0x1
-#define BF_I2C_CTRL0_SFTRST(v)                      (((v) << 31) & 0x80000000)
-#define BF_I2C_CTRL0_SFTRST_V(v)                    ((BV_I2C_CTRL0_SFTRST__##v << 31) & 0x80000000)
-#define BP_I2C_CTRL0_CLKGATE                        30
-#define BM_I2C_CTRL0_CLKGATE                        0x40000000
-#define BV_I2C_CTRL0_CLKGATE__RUN                   0x0
-#define BV_I2C_CTRL0_CLKGATE__NO_CLKS               0x1
-#define BF_I2C_CTRL0_CLKGATE(v)                     (((v) << 30) & 0x40000000)
-#define BF_I2C_CTRL0_CLKGATE_V(v)                   ((BV_I2C_CTRL0_CLKGATE__##v << 30) & 0x40000000)
-#define BP_I2C_CTRL0_RUN                            29
-#define BM_I2C_CTRL0_RUN                            0x20000000
-#define BV_I2C_CTRL0_RUN__HALT                      0x0
-#define BV_I2C_CTRL0_RUN__RUN                       0x1
-#define BF_I2C_CTRL0_RUN(v)                         (((v) << 29) & 0x20000000)
-#define BF_I2C_CTRL0_RUN_V(v)                       ((BV_I2C_CTRL0_RUN__##v << 29) & 0x20000000)
-#define BP_I2C_CTRL0_RSVD1                          28
-#define BM_I2C_CTRL0_RSVD1                          0x10000000
-#define BF_I2C_CTRL0_RSVD1(v)                       (((v) << 28) & 0x10000000)
-#define BP_I2C_CTRL0_PRE_ACK                        27
-#define BM_I2C_CTRL0_PRE_ACK                        0x8000000
-#define BF_I2C_CTRL0_PRE_ACK(v)                     (((v) << 27) & 0x8000000)
-#define BP_I2C_CTRL0_ACKNOWLEDGE                    26
-#define BM_I2C_CTRL0_ACKNOWLEDGE                    0x4000000
-#define BV_I2C_CTRL0_ACKNOWLEDGE__SNAK              0x0
-#define BV_I2C_CTRL0_ACKNOWLEDGE__ACK               0x1
-#define BF_I2C_CTRL0_ACKNOWLEDGE(v)                 (((v) << 26) & 0x4000000)
-#define BF_I2C_CTRL0_ACKNOWLEDGE_V(v)               ((BV_I2C_CTRL0_ACKNOWLEDGE__##v << 26) & 0x4000000)
-#define BP_I2C_CTRL0_SEND_NAK_ON_LAST               25
-#define BM_I2C_CTRL0_SEND_NAK_ON_LAST               0x2000000
-#define BV_I2C_CTRL0_SEND_NAK_ON_LAST__ACK_IT       0x0
-#define BV_I2C_CTRL0_SEND_NAK_ON_LAST__NAK_IT       0x1
-#define BF_I2C_CTRL0_SEND_NAK_ON_LAST(v)            (((v) << 25) & 0x2000000)
-#define BF_I2C_CTRL0_SEND_NAK_ON_LAST_V(v)          ((BV_I2C_CTRL0_SEND_NAK_ON_LAST__##v << 25) & 0x2000000)
-#define BP_I2C_CTRL0_PIO_MODE                       24
-#define BM_I2C_CTRL0_PIO_MODE                       0x1000000
-#define BF_I2C_CTRL0_PIO_MODE(v)                    (((v) << 24) & 0x1000000)
-#define BP_I2C_CTRL0_MULTI_MASTER                   23
-#define BM_I2C_CTRL0_MULTI_MASTER                   0x800000
-#define BV_I2C_CTRL0_MULTI_MASTER__SINGLE           0x0
-#define BV_I2C_CTRL0_MULTI_MASTER__MULTIPLE         0x1
-#define BF_I2C_CTRL0_MULTI_MASTER(v)                (((v) << 23) & 0x800000)
-#define BF_I2C_CTRL0_MULTI_MASTER_V(v)              ((BV_I2C_CTRL0_MULTI_MASTER__##v << 23) & 0x800000)
-#define BP_I2C_CTRL0_CLOCK_HELD                     22
-#define BM_I2C_CTRL0_CLOCK_HELD                     0x400000
-#define BV_I2C_CTRL0_CLOCK_HELD__RELEASE            0x0
-#define BV_I2C_CTRL0_CLOCK_HELD__HELD_LOW           0x1
-#define BF_I2C_CTRL0_CLOCK_HELD(v)                  (((v) << 22) & 0x400000)
-#define BF_I2C_CTRL0_CLOCK_HELD_V(v)                ((BV_I2C_CTRL0_CLOCK_HELD__##v << 22) & 0x400000)
-#define BP_I2C_CTRL0_RETAIN_CLOCK                   21
-#define BM_I2C_CTRL0_RETAIN_CLOCK                   0x200000
-#define BV_I2C_CTRL0_RETAIN_CLOCK__RELEASE          0x0
-#define BV_I2C_CTRL0_RETAIN_CLOCK__HOLD_LOW         0x1
-#define BF_I2C_CTRL0_RETAIN_CLOCK(v)                (((v) << 21) & 0x200000)
-#define BF_I2C_CTRL0_RETAIN_CLOCK_V(v)              ((BV_I2C_CTRL0_RETAIN_CLOCK__##v << 21) & 0x200000)
-#define BP_I2C_CTRL0_POST_SEND_STOP                 20
-#define BM_I2C_CTRL0_POST_SEND_STOP                 0x100000
-#define BV_I2C_CTRL0_POST_SEND_STOP__NO_STOP        0x0
-#define BV_I2C_CTRL0_POST_SEND_STOP__SEND_STOP      0x1
-#define BF_I2C_CTRL0_POST_SEND_STOP(v)              (((v) << 20) & 0x100000)
-#define BF_I2C_CTRL0_POST_SEND_STOP_V(v)            ((BV_I2C_CTRL0_POST_SEND_STOP__##v << 20) & 0x100000)
-#define BP_I2C_CTRL0_PRE_SEND_START                 19
-#define BM_I2C_CTRL0_PRE_SEND_START                 0x80000
-#define BV_I2C_CTRL0_PRE_SEND_START__NO_START       0x0
-#define BV_I2C_CTRL0_PRE_SEND_START__SEND_START     0x1
-#define BF_I2C_CTRL0_PRE_SEND_START(v)              (((v) << 19) & 0x80000)
-#define BF_I2C_CTRL0_PRE_SEND_START_V(v)            ((BV_I2C_CTRL0_PRE_SEND_START__##v << 19) & 0x80000)
-#define BP_I2C_CTRL0_SLAVE_ADDRESS_ENABLE           18
-#define BM_I2C_CTRL0_SLAVE_ADDRESS_ENABLE           0x40000
-#define BV_I2C_CTRL0_SLAVE_ADDRESS_ENABLE__DISABLED 0x0
-#define BV_I2C_CTRL0_SLAVE_ADDRESS_ENABLE__ENABLED  0x1
-#define BF_I2C_CTRL0_SLAVE_ADDRESS_ENABLE(v)        (((v) << 18) & 0x40000)
-#define BF_I2C_CTRL0_SLAVE_ADDRESS_ENABLE_V(v)      ((BV_I2C_CTRL0_SLAVE_ADDRESS_ENABLE__##v << 18) & 0x40000)
-#define BP_I2C_CTRL0_MASTER_MODE                    17
-#define BM_I2C_CTRL0_MASTER_MODE                    0x20000
-#define BV_I2C_CTRL0_MASTER_MODE__SLAVE             0x0
-#define BV_I2C_CTRL0_MASTER_MODE__MASTER            0x1
-#define BF_I2C_CTRL0_MASTER_MODE(v)                 (((v) << 17) & 0x20000)
-#define BF_I2C_CTRL0_MASTER_MODE_V(v)               ((BV_I2C_CTRL0_MASTER_MODE__##v << 17) & 0x20000)
-#define BP_I2C_CTRL0_DIRECTION                      16
-#define BM_I2C_CTRL0_DIRECTION                      0x10000
-#define BV_I2C_CTRL0_DIRECTION__RECEIVE             0x0
-#define BV_I2C_CTRL0_DIRECTION__TRANSMIT            0x1
-#define BF_I2C_CTRL0_DIRECTION(v)                   (((v) << 16) & 0x10000)
-#define BF_I2C_CTRL0_DIRECTION_V(v)                 ((BV_I2C_CTRL0_DIRECTION__##v << 16) & 0x10000)
-#define BP_I2C_CTRL0_XFER_COUNT                     0
-#define BM_I2C_CTRL0_XFER_COUNT                     0xffff
-#define BF_I2C_CTRL0_XFER_COUNT(v)                  (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_I2C_TIMING0
- * Address: 0x10
- * SCT: yes
-*/
-#define HW_I2C_TIMING0                  (*(volatile unsigned long *)(REGS_I2C_BASE + 0x10 + 0x0))
-#define HW_I2C_TIMING0_SET              (*(volatile unsigned long *)(REGS_I2C_BASE + 0x10 + 0x4))
-#define HW_I2C_TIMING0_CLR              (*(volatile unsigned long *)(REGS_I2C_BASE + 0x10 + 0x8))
-#define HW_I2C_TIMING0_TOG              (*(volatile unsigned long *)(REGS_I2C_BASE + 0x10 + 0xc))
-#define BP_I2C_TIMING0_RSVD2            26
-#define BM_I2C_TIMING0_RSVD2            0xfc000000
-#define BF_I2C_TIMING0_RSVD2(v)         (((v) << 26) & 0xfc000000)
-#define BP_I2C_TIMING0_HIGH_COUNT       16
-#define BM_I2C_TIMING0_HIGH_COUNT       0x3ff0000
-#define BF_I2C_TIMING0_HIGH_COUNT(v)    (((v) << 16) & 0x3ff0000)
-#define BP_I2C_TIMING0_RSVD1            10
-#define BM_I2C_TIMING0_RSVD1            0xfc00
-#define BF_I2C_TIMING0_RSVD1(v)         (((v) << 10) & 0xfc00)
-#define BP_I2C_TIMING0_RCV_COUNT        0
-#define BM_I2C_TIMING0_RCV_COUNT        0x3ff
-#define BF_I2C_TIMING0_RCV_COUNT(v)     (((v) << 0) & 0x3ff)
-
-/**
- * Register: HW_I2C_TIMING1
- * Address: 0x20
- * SCT: yes
-*/
-#define HW_I2C_TIMING1                  (*(volatile unsigned long *)(REGS_I2C_BASE + 0x20 + 0x0))
-#define HW_I2C_TIMING1_SET              (*(volatile unsigned long *)(REGS_I2C_BASE + 0x20 + 0x4))
-#define HW_I2C_TIMING1_CLR              (*(volatile unsigned long *)(REGS_I2C_BASE + 0x20 + 0x8))
-#define HW_I2C_TIMING1_TOG              (*(volatile unsigned long *)(REGS_I2C_BASE + 0x20 + 0xc))
-#define BP_I2C_TIMING1_RSVD2            26
-#define BM_I2C_TIMING1_RSVD2            0xfc000000
-#define BF_I2C_TIMING1_RSVD2(v)         (((v) << 26) & 0xfc000000)
-#define BP_I2C_TIMING1_LOW_COUNT        16
-#define BM_I2C_TIMING1_LOW_COUNT        0x3ff0000
-#define BF_I2C_TIMING1_LOW_COUNT(v)     (((v) << 16) & 0x3ff0000)
-#define BP_I2C_TIMING1_RSVD1            10
-#define BM_I2C_TIMING1_RSVD1            0xfc00
-#define BF_I2C_TIMING1_RSVD1(v)         (((v) << 10) & 0xfc00)
-#define BP_I2C_TIMING1_XMIT_COUNT       0
-#define BM_I2C_TIMING1_XMIT_COUNT       0x3ff
-#define BF_I2C_TIMING1_XMIT_COUNT(v)    (((v) << 0) & 0x3ff)
-
-/**
- * Register: HW_I2C_TIMING2
- * Address: 0x30
- * SCT: yes
-*/
-#define HW_I2C_TIMING2                  (*(volatile unsigned long *)(REGS_I2C_BASE + 0x30 + 0x0))
-#define HW_I2C_TIMING2_SET              (*(volatile unsigned long *)(REGS_I2C_BASE + 0x30 + 0x4))
-#define HW_I2C_TIMING2_CLR              (*(volatile unsigned long *)(REGS_I2C_BASE + 0x30 + 0x8))
-#define HW_I2C_TIMING2_TOG              (*(volatile unsigned long *)(REGS_I2C_BASE + 0x30 + 0xc))
-#define BP_I2C_TIMING2_RSVD2            26
-#define BM_I2C_TIMING2_RSVD2            0xfc000000
-#define BF_I2C_TIMING2_RSVD2(v)         (((v) << 26) & 0xfc000000)
-#define BP_I2C_TIMING2_BUS_FREE         16
-#define BM_I2C_TIMING2_BUS_FREE         0x3ff0000
-#define BF_I2C_TIMING2_BUS_FREE(v)      (((v) << 16) & 0x3ff0000)
-#define BP_I2C_TIMING2_RSVD1            10
-#define BM_I2C_TIMING2_RSVD1            0xfc00
-#define BF_I2C_TIMING2_RSVD1(v)         (((v) << 10) & 0xfc00)
-#define BP_I2C_TIMING2_LEADIN_COUNT     0
-#define BM_I2C_TIMING2_LEADIN_COUNT     0x3ff
-#define BF_I2C_TIMING2_LEADIN_COUNT(v)  (((v) << 0) & 0x3ff)
-
-/**
- * Register: HW_I2C_CTRL1
- * Address: 0x40
- * SCT: yes
-*/
-#define HW_I2C_CTRL1                                        (*(volatile unsigned long *)(REGS_I2C_BASE + 0x40 + 0x0))
-#define HW_I2C_CTRL1_SET                                    (*(volatile unsigned long *)(REGS_I2C_BASE + 0x40 + 0x4))
-#define HW_I2C_CTRL1_CLR                                    (*(volatile unsigned long *)(REGS_I2C_BASE + 0x40 + 0x8))
-#define HW_I2C_CTRL1_TOG                                    (*(volatile unsigned long *)(REGS_I2C_BASE + 0x40 + 0xc))
-#define BP_I2C_CTRL1_RSVD1                                  29
-#define BM_I2C_CTRL1_RSVD1                                  0xe0000000
-#define BF_I2C_CTRL1_RSVD1(v)                               (((v) << 29) & 0xe0000000)
-#define BP_I2C_CTRL1_CLR_GOT_A_NAK                          28
-#define BM_I2C_CTRL1_CLR_GOT_A_NAK                          0x10000000
-#define BV_I2C_CTRL1_CLR_GOT_A_NAK__DO_NOTHING              0x0
-#define BV_I2C_CTRL1_CLR_GOT_A_NAK__CLEAR                   0x1
-#define BF_I2C_CTRL1_CLR_GOT_A_NAK(v)                       (((v) << 28) & 0x10000000)
-#define BF_I2C_CTRL1_CLR_GOT_A_NAK_V(v)                     ((BV_I2C_CTRL1_CLR_GOT_A_NAK__##v << 28) & 0x10000000)
-#define BP_I2C_CTRL1_ACK_MODE                               27
-#define BM_I2C_CTRL1_ACK_MODE                               0x8000000
-#define BV_I2C_CTRL1_ACK_MODE__ACK_AFTER_HOLD_LOW           0x0
-#define BV_I2C_CTRL1_ACK_MODE__ACK_BEFORE_HOLD_LOW          0x1
-#define BF_I2C_CTRL1_ACK_MODE(v)                            (((v) << 27) & 0x8000000)
-#define BF_I2C_CTRL1_ACK_MODE_V(v)                          ((BV_I2C_CTRL1_ACK_MODE__##v << 27) & 0x8000000)
-#define BP_I2C_CTRL1_FORCE_DATA_IDLE                        26
-#define BM_I2C_CTRL1_FORCE_DATA_IDLE                        0x4000000
-#define BF_I2C_CTRL1_FORCE_DATA_IDLE(v)                     (((v) << 26) & 0x4000000)
-#define BP_I2C_CTRL1_FORCE_CLK_IDLE                         25
-#define BM_I2C_CTRL1_FORCE_CLK_IDLE                         0x2000000
-#define BF_I2C_CTRL1_FORCE_CLK_IDLE(v)                      (((v) << 25) & 0x2000000)
-#define BP_I2C_CTRL1_BCAST_SLAVE_EN                         24
-#define BM_I2C_CTRL1_BCAST_SLAVE_EN                         0x1000000
-#define BV_I2C_CTRL1_BCAST_SLAVE_EN__NO_BCAST               0x0
-#define BV_I2C_CTRL1_BCAST_SLAVE_EN__WATCH_BCAST            0x1
-#define BF_I2C_CTRL1_BCAST_SLAVE_EN(v)                      (((v) << 24) & 0x1000000)
-#define BF_I2C_CTRL1_BCAST_SLAVE_EN_V(v)                    ((BV_I2C_CTRL1_BCAST_SLAVE_EN__##v << 24) & 0x1000000)
-#define BP_I2C_CTRL1_SLAVE_ADDRESS_BYTE                     16
-#define BM_I2C_CTRL1_SLAVE_ADDRESS_BYTE                     0xff0000
-#define BF_I2C_CTRL1_SLAVE_ADDRESS_BYTE(v)                  (((v) << 16) & 0xff0000)
-#define BP_I2C_CTRL1_BUS_FREE_IRQ_EN                        15
-#define BM_I2C_CTRL1_BUS_FREE_IRQ_EN                        0x8000
-#define BV_I2C_CTRL1_BUS_FREE_IRQ_EN__DISABLED              0x0
-#define BV_I2C_CTRL1_BUS_FREE_IRQ_EN__ENABLED               0x1
-#define BF_I2C_CTRL1_BUS_FREE_IRQ_EN(v)                     (((v) << 15) & 0x8000)
-#define BF_I2C_CTRL1_BUS_FREE_IRQ_EN_V(v)                   ((BV_I2C_CTRL1_BUS_FREE_IRQ_EN__##v << 15) & 0x8000)
-#define BP_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN               14
-#define BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN               0x4000
-#define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN__DISABLED     0x0
-#define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN__ENABLED      0x1
-#define BF_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN(v)            (((v) << 14) & 0x4000)
-#define BF_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN_V(v)          ((BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN__##v << 14) & 0x4000)
-#define BP_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN                    13
-#define BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN                    0x2000
-#define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN__DISABLED          0x0
-#define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN__ENABLED           0x1
-#define BF_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN(v)                 (((v) << 13) & 0x2000)
-#define BF_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN_V(v)               ((BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN__##v << 13) & 0x2000)
-#define BP_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN              12
-#define BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN              0x1000
-#define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN__DISABLED    0x0
-#define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN__ENABLED     0x1
-#define BF_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN(v)           (((v) << 12) & 0x1000)
-#define BF_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN_V(v)         ((BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN__##v << 12) & 0x1000)
-#define BP_I2C_CTRL1_EARLY_TERM_IRQ_EN                      11
-#define BM_I2C_CTRL1_EARLY_TERM_IRQ_EN                      0x800
-#define BV_I2C_CTRL1_EARLY_TERM_IRQ_EN__DISABLED            0x0
-#define BV_I2C_CTRL1_EARLY_TERM_IRQ_EN__ENABLED             0x1
-#define BF_I2C_CTRL1_EARLY_TERM_IRQ_EN(v)                   (((v) << 11) & 0x800)
-#define BF_I2C_CTRL1_EARLY_TERM_IRQ_EN_V(v)                 ((BV_I2C_CTRL1_EARLY_TERM_IRQ_EN__##v << 11) & 0x800)
-#define BP_I2C_CTRL1_MASTER_LOSS_IRQ_EN                     10
-#define BM_I2C_CTRL1_MASTER_LOSS_IRQ_EN                     0x400
-#define BV_I2C_CTRL1_MASTER_LOSS_IRQ_EN__DISABLED           0x0
-#define BV_I2C_CTRL1_MASTER_LOSS_IRQ_EN__ENABLED            0x1
-#define BF_I2C_CTRL1_MASTER_LOSS_IRQ_EN(v)                  (((v) << 10) & 0x400)
-#define BF_I2C_CTRL1_MASTER_LOSS_IRQ_EN_V(v)                ((BV_I2C_CTRL1_MASTER_LOSS_IRQ_EN__##v << 10) & 0x400)
-#define BP_I2C_CTRL1_SLAVE_STOP_IRQ_EN                      9
-#define BM_I2C_CTRL1_SLAVE_STOP_IRQ_EN                      0x200
-#define BV_I2C_CTRL1_SLAVE_STOP_IRQ_EN__DISABLED            0x0
-#define BV_I2C_CTRL1_SLAVE_STOP_IRQ_EN__ENABLED             0x1
-#define BF_I2C_CTRL1_SLAVE_STOP_IRQ_EN(v)                   (((v) << 9) & 0x200)
-#define BF_I2C_CTRL1_SLAVE_STOP_IRQ_EN_V(v)                 ((BV_I2C_CTRL1_SLAVE_STOP_IRQ_EN__##v << 9) & 0x200)
-#define BP_I2C_CTRL1_SLAVE_IRQ_EN                           8
-#define BM_I2C_CTRL1_SLAVE_IRQ_EN                           0x100
-#define BV_I2C_CTRL1_SLAVE_IRQ_EN__DISABLED                 0x0
-#define BV_I2C_CTRL1_SLAVE_IRQ_EN__ENABLED                  0x1
-#define BF_I2C_CTRL1_SLAVE_IRQ_EN(v)                        (((v) << 8) & 0x100)
-#define BF_I2C_CTRL1_SLAVE_IRQ_EN_V(v)                      ((BV_I2C_CTRL1_SLAVE_IRQ_EN__##v << 8) & 0x100)
-#define BP_I2C_CTRL1_BUS_FREE_IRQ                           7
-#define BM_I2C_CTRL1_BUS_FREE_IRQ                           0x80
-#define BV_I2C_CTRL1_BUS_FREE_IRQ__NO_REQUEST               0x0
-#define BV_I2C_CTRL1_BUS_FREE_IRQ__REQUEST                  0x1
-#define BF_I2C_CTRL1_BUS_FREE_IRQ(v)                        (((v) << 7) & 0x80)
-#define BF_I2C_CTRL1_BUS_FREE_IRQ_V(v)                      ((BV_I2C_CTRL1_BUS_FREE_IRQ__##v << 7) & 0x80)
-#define BP_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ                  6
-#define BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ                  0x40
-#define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ__NO_REQUEST      0x0
-#define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ__REQUEST         0x1
-#define BF_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ(v)               (((v) << 6) & 0x40)
-#define BF_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_V(v)             ((BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ__##v << 6) & 0x40)
-#define BP_I2C_CTRL1_NO_SLAVE_ACK_IRQ                       5
-#define BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ                       0x20
-#define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ__NO_REQUEST           0x0
-#define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ__REQUEST              0x1
-#define BF_I2C_CTRL1_NO_SLAVE_ACK_IRQ(v)                    (((v) << 5) & 0x20)
-#define BF_I2C_CTRL1_NO_SLAVE_ACK_IRQ_V(v)                  ((BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ__##v << 5) & 0x20)
-#define BP_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ                 4
-#define BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ                 0x10
-#define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ__NO_REQUEST     0x0
-#define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ__REQUEST        0x1
-#define BF_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ(v)              (((v) << 4) & 0x10)
-#define BF_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_V(v)            ((BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ__##v << 4) & 0x10)
-#define BP_I2C_CTRL1_EARLY_TERM_IRQ                         3
-#define BM_I2C_CTRL1_EARLY_TERM_IRQ                         0x8
-#define BV_I2C_CTRL1_EARLY_TERM_IRQ__NO_REQUEST             0x0
-#define BV_I2C_CTRL1_EARLY_TERM_IRQ__REQUEST                0x1
-#define BF_I2C_CTRL1_EARLY_TERM_IRQ(v)                      (((v) << 3) & 0x8)
-#define BF_I2C_CTRL1_EARLY_TERM_IRQ_V(v)                    ((BV_I2C_CTRL1_EARLY_TERM_IRQ__##v << 3) & 0x8)
-#define BP_I2C_CTRL1_MASTER_LOSS_IRQ                        2
-#define BM_I2C_CTRL1_MASTER_LOSS_IRQ                        0x4
-#define BV_I2C_CTRL1_MASTER_LOSS_IRQ__NO_REQUEST            0x0
-#define BV_I2C_CTRL1_MASTER_LOSS_IRQ__REQUEST               0x1
-#define BF_I2C_CTRL1_MASTER_LOSS_IRQ(v)                     (((v) << 2) & 0x4)
-#define BF_I2C_CTRL1_MASTER_LOSS_IRQ_V(v)                   ((BV_I2C_CTRL1_MASTER_LOSS_IRQ__##v << 2) & 0x4)
-#define BP_I2C_CTRL1_SLAVE_STOP_IRQ                         1
-#define BM_I2C_CTRL1_SLAVE_STOP_IRQ                         0x2
-#define BV_I2C_CTRL1_SLAVE_STOP_IRQ__NO_REQUEST             0x0
-#define BV_I2C_CTRL1_SLAVE_STOP_IRQ__REQUEST                0x1
-#define BF_I2C_CTRL1_SLAVE_STOP_IRQ(v)                      (((v) << 1) & 0x2)
-#define BF_I2C_CTRL1_SLAVE_STOP_IRQ_V(v)                    ((BV_I2C_CTRL1_SLAVE_STOP_IRQ__##v << 1) & 0x2)
-#define BP_I2C_CTRL1_SLAVE_IRQ                              0
-#define BM_I2C_CTRL1_SLAVE_IRQ                              0x1
-#define BV_I2C_CTRL1_SLAVE_IRQ__NO_REQUEST                  0x0
-#define BV_I2C_CTRL1_SLAVE_IRQ__REQUEST                     0x1
-#define BF_I2C_CTRL1_SLAVE_IRQ(v)                           (((v) << 0) & 0x1)
-#define BF_I2C_CTRL1_SLAVE_IRQ_V(v)                         ((BV_I2C_CTRL1_SLAVE_IRQ__##v << 0) & 0x1)
-
-/**
- * Register: HW_I2C_STAT
- * Address: 0x50
- * SCT: no
-*/
-#define HW_I2C_STAT                                             (*(volatile unsigned long *)(REGS_I2C_BASE + 0x50))
-#define BP_I2C_STAT_MASTER_PRESENT                              31
-#define BM_I2C_STAT_MASTER_PRESENT                              0x80000000
-#define BV_I2C_STAT_MASTER_PRESENT__UNAVAILABLE                 0x0
-#define BV_I2C_STAT_MASTER_PRESENT__AVAILABLE                   0x1
-#define BF_I2C_STAT_MASTER_PRESENT(v)                           (((v) << 31) & 0x80000000)
-#define BF_I2C_STAT_MASTER_PRESENT_V(v)                         ((BV_I2C_STAT_MASTER_PRESENT__##v << 31) & 0x80000000)
-#define BP_I2C_STAT_SLAVE_PRESENT                               30
-#define BM_I2C_STAT_SLAVE_PRESENT                               0x40000000
-#define BV_I2C_STAT_SLAVE_PRESENT__UNAVAILABLE                  0x0
-#define BV_I2C_STAT_SLAVE_PRESENT__AVAILABLE                    0x1
-#define BF_I2C_STAT_SLAVE_PRESENT(v)                            (((v) << 30) & 0x40000000)
-#define BF_I2C_STAT_SLAVE_PRESENT_V(v)                          ((BV_I2C_STAT_SLAVE_PRESENT__##v << 30) & 0x40000000)
-#define BP_I2C_STAT_ANY_ENABLED_IRQ                             29
-#define BM_I2C_STAT_ANY_ENABLED_IRQ                             0x20000000
-#define BV_I2C_STAT_ANY_ENABLED_IRQ__NO_REQUESTS                0x0
-#define BV_I2C_STAT_ANY_ENABLED_IRQ__AT_LEAST_ONE_REQUEST       0x1
-#define BF_I2C_STAT_ANY_ENABLED_IRQ(v)                          (((v) << 29) & 0x20000000)
-#define BF_I2C_STAT_ANY_ENABLED_IRQ_V(v)                        ((BV_I2C_STAT_ANY_ENABLED_IRQ__##v << 29) & 0x20000000)
-#define BP_I2C_STAT_GOT_A_NAK                                   28
-#define BM_I2C_STAT_GOT_A_NAK                                   0x10000000
-#define BV_I2C_STAT_GOT_A_NAK__NO_NAK                           0x0
-#define BV_I2C_STAT_GOT_A_NAK__DETECTED_NAK                     0x1
-#define BF_I2C_STAT_GOT_A_NAK(v)                                (((v) << 28) & 0x10000000)
-#define BF_I2C_STAT_GOT_A_NAK_V(v)                              ((BV_I2C_STAT_GOT_A_NAK__##v << 28) & 0x10000000)
-#define BP_I2C_STAT_RSVD1                                       24
-#define BM_I2C_STAT_RSVD1                                       0xf000000
-#define BF_I2C_STAT_RSVD1(v)                                    (((v) << 24) & 0xf000000)
-#define BP_I2C_STAT_RCVD_SLAVE_ADDR                             16
-#define BM_I2C_STAT_RCVD_SLAVE_ADDR                             0xff0000
-#define BF_I2C_STAT_RCVD_SLAVE_ADDR(v)                          (((v) << 16) & 0xff0000)
-#define BP_I2C_STAT_SLAVE_ADDR_EQ_ZERO                          15
-#define BM_I2C_STAT_SLAVE_ADDR_EQ_ZERO                          0x8000
-#define BV_I2C_STAT_SLAVE_ADDR_EQ_ZERO__ZERO_NOT_MATCHED        0x0
-#define BV_I2C_STAT_SLAVE_ADDR_EQ_ZERO__WAS_ZERO                0x1
-#define BF_I2C_STAT_SLAVE_ADDR_EQ_ZERO(v)                       (((v) << 15) & 0x8000)
-#define BF_I2C_STAT_SLAVE_ADDR_EQ_ZERO_V(v)                     ((BV_I2C_STAT_SLAVE_ADDR_EQ_ZERO__##v << 15) & 0x8000)
-#define BP_I2C_STAT_SLAVE_FOUND                                 14
-#define BM_I2C_STAT_SLAVE_FOUND                                 0x4000
-#define BV_I2C_STAT_SLAVE_FOUND__IDLE                           0x0
-#define BV_I2C_STAT_SLAVE_FOUND__WAITING                        0x1
-#define BF_I2C_STAT_SLAVE_FOUND(v)                              (((v) << 14) & 0x4000)
-#define BF_I2C_STAT_SLAVE_FOUND_V(v)                            ((BV_I2C_STAT_SLAVE_FOUND__##v << 14) & 0x4000)
-#define BP_I2C_STAT_SLAVE_SEARCHING                             13
-#define BM_I2C_STAT_SLAVE_SEARCHING                             0x2000
-#define BV_I2C_STAT_SLAVE_SEARCHING__IDLE                       0x0
-#define BV_I2C_STAT_SLAVE_SEARCHING__ACTIVE                     0x1
-#define BF_I2C_STAT_SLAVE_SEARCHING(v)                          (((v) << 13) & 0x2000)
-#define BF_I2C_STAT_SLAVE_SEARCHING_V(v)                        ((BV_I2C_STAT_SLAVE_SEARCHING__##v << 13) & 0x2000)
-#define BP_I2C_STAT_DATA_ENGINE_DMA_WAIT                        12
-#define BM_I2C_STAT_DATA_ENGINE_DMA_WAIT                        0x1000
-#define BV_I2C_STAT_DATA_ENGINE_DMA_WAIT__CONTINUE              0x0
-#define BV_I2C_STAT_DATA_ENGINE_DMA_WAIT__WAITING               0x1
-#define BF_I2C_STAT_DATA_ENGINE_DMA_WAIT(v)                     (((v) << 12) & 0x1000)
-#define BF_I2C_STAT_DATA_ENGINE_DMA_WAIT_V(v)                   ((BV_I2C_STAT_DATA_ENGINE_DMA_WAIT__##v << 12) & 0x1000)
-#define BP_I2C_STAT_BUS_BUSY                                    11
-#define BM_I2C_STAT_BUS_BUSY                                    0x800
-#define BV_I2C_STAT_BUS_BUSY__IDLE                              0x0
-#define BV_I2C_STAT_BUS_BUSY__BUSY                              0x1
-#define BF_I2C_STAT_BUS_BUSY(v)                                 (((v) << 11) & 0x800)
-#define BF_I2C_STAT_BUS_BUSY_V(v)                               ((BV_I2C_STAT_BUS_BUSY__##v << 11) & 0x800)
-#define BP_I2C_STAT_CLK_GEN_BUSY                                10
-#define BM_I2C_STAT_CLK_GEN_BUSY                                0x400
-#define BV_I2C_STAT_CLK_GEN_BUSY__IDLE                          0x0
-#define BV_I2C_STAT_CLK_GEN_BUSY__BUSY                          0x1
-#define BF_I2C_STAT_CLK_GEN_BUSY(v)                             (((v) << 10) & 0x400)
-#define BF_I2C_STAT_CLK_GEN_BUSY_V(v)                           ((BV_I2C_STAT_CLK_GEN_BUSY__##v << 10) & 0x400)
-#define BP_I2C_STAT_DATA_ENGINE_BUSY                            9
-#define BM_I2C_STAT_DATA_ENGINE_BUSY                            0x200
-#define BV_I2C_STAT_DATA_ENGINE_BUSY__IDLE                      0x0
-#define BV_I2C_STAT_DATA_ENGINE_BUSY__BUSY                      0x1
-#define BF_I2C_STAT_DATA_ENGINE_BUSY(v)                         (((v) << 9) & 0x200)
-#define BF_I2C_STAT_DATA_ENGINE_BUSY_V(v)                       ((BV_I2C_STAT_DATA_ENGINE_BUSY__##v << 9) & 0x200)
-#define BP_I2C_STAT_SLAVE_BUSY                                  8
-#define BM_I2C_STAT_SLAVE_BUSY                                  0x100
-#define BV_I2C_STAT_SLAVE_BUSY__IDLE                            0x0
-#define BV_I2C_STAT_SLAVE_BUSY__BUSY                            0x1
-#define BF_I2C_STAT_SLAVE_BUSY(v)                               (((v) << 8) & 0x100)
-#define BF_I2C_STAT_SLAVE_BUSY_V(v)                             ((BV_I2C_STAT_SLAVE_BUSY__##v << 8) & 0x100)
-#define BP_I2C_STAT_BUS_FREE_IRQ_SUMMARY                        7
-#define BM_I2C_STAT_BUS_FREE_IRQ_SUMMARY                        0x80
-#define BV_I2C_STAT_BUS_FREE_IRQ_SUMMARY__NO_REQUEST            0x0
-#define BV_I2C_STAT_BUS_FREE_IRQ_SUMMARY__REQUEST               0x1
-#define BF_I2C_STAT_BUS_FREE_IRQ_SUMMARY(v)                     (((v) << 7) & 0x80)
-#define BF_I2C_STAT_BUS_FREE_IRQ_SUMMARY_V(v)                   ((BV_I2C_STAT_BUS_FREE_IRQ_SUMMARY__##v << 7) & 0x80)
-#define BP_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY               6
-#define BM_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY               0x40
-#define BV_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY__NO_REQUEST   0x0
-#define BV_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY__REQUEST      0x1
-#define BF_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY(v)            (((v) << 6) & 0x40)
-#define BF_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY_V(v)          ((BV_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY__##v << 6) & 0x40)
-#define BP_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY                    5
-#define BM_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY                    0x20
-#define BV_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY__NO_REQUEST        0x0
-#define BV_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY__REQUEST           0x1
-#define BF_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY(v)                 (((v) << 5) & 0x20)
-#define BF_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY_V(v)               ((BV_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY__##v << 5) & 0x20)
-#define BP_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY              4
-#define BM_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY              0x10
-#define BV_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY__NO_REQUEST  0x0
-#define BV_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY__REQUEST     0x1
-#define BF_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY(v)           (((v) << 4) & 0x10)
-#define BF_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY_V(v)         ((BV_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY__##v << 4) & 0x10)
-#define BP_I2C_STAT_EARLY_TERM_IRQ_SUMMARY                      3
-#define BM_I2C_STAT_EARLY_TERM_IRQ_SUMMARY                      0x8
-#define BV_I2C_STAT_EARLY_TERM_IRQ_SUMMARY__NO_REQUEST          0x0
-#define BV_I2C_STAT_EARLY_TERM_IRQ_SUMMARY__REQUEST             0x1
-#define BF_I2C_STAT_EARLY_TERM_IRQ_SUMMARY(v)                   (((v) << 3) & 0x8)
-#define BF_I2C_STAT_EARLY_TERM_IRQ_SUMMARY_V(v)                 ((BV_I2C_STAT_EARLY_TERM_IRQ_SUMMARY__##v << 3) & 0x8)
-#define BP_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY                     2
-#define BM_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY                     0x4
-#define BV_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY__NO_REQUEST         0x0
-#define BV_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY__REQUEST            0x1
-#define BF_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY(v)                  (((v) << 2) & 0x4)
-#define BF_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY_V(v)                ((BV_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY__##v << 2) & 0x4)
-#define BP_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY                      1
-#define BM_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY                      0x2
-#define BV_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY__NO_REQUEST          0x0
-#define BV_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY__REQUEST             0x1
-#define BF_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY(v)                   (((v) << 1) & 0x2)
-#define BF_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY_V(v)                 ((BV_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY__##v << 1) & 0x2)
-#define BP_I2C_STAT_SLAVE_IRQ_SUMMARY                           0
-#define BM_I2C_STAT_SLAVE_IRQ_SUMMARY                           0x1
-#define BV_I2C_STAT_SLAVE_IRQ_SUMMARY__NO_REQUEST               0x0
-#define BV_I2C_STAT_SLAVE_IRQ_SUMMARY__REQUEST                  0x1
-#define BF_I2C_STAT_SLAVE_IRQ_SUMMARY(v)                        (((v) << 0) & 0x1)
-#define BF_I2C_STAT_SLAVE_IRQ_SUMMARY_V(v)                      ((BV_I2C_STAT_SLAVE_IRQ_SUMMARY__##v << 0) & 0x1)
-
-/**
- * Register: HW_I2C_DATA
- * Address: 0x60
- * SCT: no
-*/
-#define HW_I2C_DATA         (*(volatile unsigned long *)(REGS_I2C_BASE + 0x60))
-#define BP_I2C_DATA_DATA    0
-#define BM_I2C_DATA_DATA    0xffffffff
-#define BF_I2C_DATA_DATA(v) (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_I2C_DEBUG0
- * Address: 0x70
- * SCT: yes
-*/
-#define HW_I2C_DEBUG0                   (*(volatile unsigned long *)(REGS_I2C_BASE + 0x70 + 0x0))
-#define HW_I2C_DEBUG0_SET               (*(volatile unsigned long *)(REGS_I2C_BASE + 0x70 + 0x4))
-#define HW_I2C_DEBUG0_CLR               (*(volatile unsigned long *)(REGS_I2C_BASE + 0x70 + 0x8))
-#define HW_I2C_DEBUG0_TOG               (*(volatile unsigned long *)(REGS_I2C_BASE + 0x70 + 0xc))
-#define BP_I2C_DEBUG0_DMAREQ            31
-#define BM_I2C_DEBUG0_DMAREQ            0x80000000
-#define BF_I2C_DEBUG0_DMAREQ(v)         (((v) << 31) & 0x80000000)
-#define BP_I2C_DEBUG0_DMAENDCMD         30
-#define BM_I2C_DEBUG0_DMAENDCMD         0x40000000
-#define BF_I2C_DEBUG0_DMAENDCMD(v)      (((v) << 30) & 0x40000000)
-#define BP_I2C_DEBUG0_DMAKICK           29
-#define BM_I2C_DEBUG0_DMAKICK           0x20000000
-#define BF_I2C_DEBUG0_DMAKICK(v)        (((v) << 29) & 0x20000000)
-#define BP_I2C_DEBUG0_DMATERMINATE      28
-#define BM_I2C_DEBUG0_DMATERMINATE      0x10000000
-#define BF_I2C_DEBUG0_DMATERMINATE(v)   (((v) << 28) & 0x10000000)
-#define BP_I2C_DEBUG0_TBD               26
-#define BM_I2C_DEBUG0_TBD               0xc000000
-#define BF_I2C_DEBUG0_TBD(v)            (((v) << 26) & 0xc000000)
-#define BP_I2C_DEBUG0_DMA_STATE         16
-#define BM_I2C_DEBUG0_DMA_STATE         0x3ff0000
-#define BF_I2C_DEBUG0_DMA_STATE(v)      (((v) << 16) & 0x3ff0000)
-#define BP_I2C_DEBUG0_START_TOGGLE      15
-#define BM_I2C_DEBUG0_START_TOGGLE      0x8000
-#define BF_I2C_DEBUG0_START_TOGGLE(v)   (((v) << 15) & 0x8000)
-#define BP_I2C_DEBUG0_STOP_TOGGLE       14
-#define BM_I2C_DEBUG0_STOP_TOGGLE       0x4000
-#define BF_I2C_DEBUG0_STOP_TOGGLE(v)    (((v) << 14) & 0x4000)
-#define BP_I2C_DEBUG0_GRAB_TOGGLE       13
-#define BM_I2C_DEBUG0_GRAB_TOGGLE       0x2000
-#define BF_I2C_DEBUG0_GRAB_TOGGLE(v)    (((v) << 13) & 0x2000)
-#define BP_I2C_DEBUG0_CHANGE_TOGGLE     12
-#define BM_I2C_DEBUG0_CHANGE_TOGGLE     0x1000
-#define BF_I2C_DEBUG0_CHANGE_TOGGLE(v)  (((v) << 12) & 0x1000)
-#define BP_I2C_DEBUG0_TESTMODE          11
-#define BM_I2C_DEBUG0_TESTMODE          0x800
-#define BF_I2C_DEBUG0_TESTMODE(v)       (((v) << 11) & 0x800)
-#define BP_I2C_DEBUG0_SLAVE_HOLD_CLK    10
-#define BM_I2C_DEBUG0_SLAVE_HOLD_CLK    0x400
-#define BF_I2C_DEBUG0_SLAVE_HOLD_CLK(v) (((v) << 10) & 0x400)
-#define BP_I2C_DEBUG0_SLAVE_STATE       0
-#define BM_I2C_DEBUG0_SLAVE_STATE       0x3ff
-#define BF_I2C_DEBUG0_SLAVE_STATE(v)    (((v) << 0) & 0x3ff)
-
-/**
- * Register: HW_I2C_DEBUG1
- * Address: 0x80
- * SCT: yes
-*/
-#define HW_I2C_DEBUG1                       (*(volatile unsigned long *)(REGS_I2C_BASE + 0x80 + 0x0))
-#define HW_I2C_DEBUG1_SET                   (*(volatile unsigned long *)(REGS_I2C_BASE + 0x80 + 0x4))
-#define HW_I2C_DEBUG1_CLR                   (*(volatile unsigned long *)(REGS_I2C_BASE + 0x80 + 0x8))
-#define HW_I2C_DEBUG1_TOG                   (*(volatile unsigned long *)(REGS_I2C_BASE + 0x80 + 0xc))
-#define BP_I2C_DEBUG1_I2C_CLK_IN            31
-#define BM_I2C_DEBUG1_I2C_CLK_IN            0x80000000
-#define BF_I2C_DEBUG1_I2C_CLK_IN(v)         (((v) << 31) & 0x80000000)
-#define BP_I2C_DEBUG1_I2C_DATA_IN           30
-#define BM_I2C_DEBUG1_I2C_DATA_IN           0x40000000
-#define BF_I2C_DEBUG1_I2C_DATA_IN(v)        (((v) << 30) & 0x40000000)
-#define BP_I2C_DEBUG1_RSVD4                 28
-#define BM_I2C_DEBUG1_RSVD4                 0x30000000
-#define BF_I2C_DEBUG1_RSVD4(v)              (((v) << 28) & 0x30000000)
-#define BP_I2C_DEBUG1_DMA_BYTE_ENABLES      24
-#define BM_I2C_DEBUG1_DMA_BYTE_ENABLES      0xf000000
-#define BF_I2C_DEBUG1_DMA_BYTE_ENABLES(v)   (((v) << 24) & 0xf000000)
-#define BP_I2C_DEBUG1_CLK_GEN_STATE         16
-#define BM_I2C_DEBUG1_CLK_GEN_STATE         0xff0000
-#define BF_I2C_DEBUG1_CLK_GEN_STATE(v)      (((v) << 16) & 0xff0000)
-#define BP_I2C_DEBUG1_RSVD2                 11
-#define BM_I2C_DEBUG1_RSVD2                 0xf800
-#define BF_I2C_DEBUG1_RSVD2(v)              (((v) << 11) & 0xf800)
-#define BP_I2C_DEBUG1_LST_MODE              9
-#define BM_I2C_DEBUG1_LST_MODE              0x600
-#define BV_I2C_DEBUG1_LST_MODE__BCAST       0x0
-#define BV_I2C_DEBUG1_LST_MODE__MY_WRITE    0x1
-#define BV_I2C_DEBUG1_LST_MODE__MY_READ     0x2
-#define BV_I2C_DEBUG1_LST_MODE__NOT_ME      0x3
-#define BF_I2C_DEBUG1_LST_MODE(v)           (((v) << 9) & 0x600)
-#define BF_I2C_DEBUG1_LST_MODE_V(v)         ((BV_I2C_DEBUG1_LST_MODE__##v << 9) & 0x600)
-#define BP_I2C_DEBUG1_LOCAL_SLAVE_TEST      8
-#define BM_I2C_DEBUG1_LOCAL_SLAVE_TEST      0x100
-#define BF_I2C_DEBUG1_LOCAL_SLAVE_TEST(v)   (((v) << 8) & 0x100)
-#define BP_I2C_DEBUG1_RSVD1                 5
-#define BM_I2C_DEBUG1_RSVD1                 0xe0
-#define BF_I2C_DEBUG1_RSVD1(v)              (((v) << 5) & 0xe0)
-#define BP_I2C_DEBUG1_FORCE_CLK_ON          4
-#define BM_I2C_DEBUG1_FORCE_CLK_ON          0x10
-#define BF_I2C_DEBUG1_FORCE_CLK_ON(v)       (((v) << 4) & 0x10)
-#define BP_I2C_DEBUG1_FORCE_ARB_LOSS        3
-#define BM_I2C_DEBUG1_FORCE_ARB_LOSS        0x8
-#define BF_I2C_DEBUG1_FORCE_ARB_LOSS(v)     (((v) << 3) & 0x8)
-#define BP_I2C_DEBUG1_FORCE_RCV_ACK         2
-#define BM_I2C_DEBUG1_FORCE_RCV_ACK         0x4
-#define BF_I2C_DEBUG1_FORCE_RCV_ACK(v)      (((v) << 2) & 0x4)
-#define BP_I2C_DEBUG1_FORCE_I2C_DATA_OE     1
-#define BM_I2C_DEBUG1_FORCE_I2C_DATA_OE     0x2
-#define BF_I2C_DEBUG1_FORCE_I2C_DATA_OE(v)  (((v) << 1) & 0x2)
-#define BP_I2C_DEBUG1_FORCE_I2C_CLK_OE      0
-#define BM_I2C_DEBUG1_FORCE_I2C_CLK_OE      0x1
-#define BF_I2C_DEBUG1_FORCE_I2C_CLK_OE(v)   (((v) << 0) & 0x1)
-
-/**
- * Register: HW_I2C_VERSION
- * Address: 0x90
- * SCT: no
-*/
-#define HW_I2C_VERSION          (*(volatile unsigned long *)(REGS_I2C_BASE + 0x90))
-#define BP_I2C_VERSION_MAJOR    24
-#define BM_I2C_VERSION_MAJOR    0xff000000
-#define BF_I2C_VERSION_MAJOR(v) (((v) << 24) & 0xff000000)
-#define BP_I2C_VERSION_MINOR    16
-#define BM_I2C_VERSION_MINOR    0xff0000
-#define BF_I2C_VERSION_MINOR(v) (((v) << 16) & 0xff0000)
-#define BP_I2C_VERSION_STEP     0
-#define BM_I2C_VERSION_STEP     0xffff
-#define BF_I2C_VERSION_STEP(v)  (((v) << 0) & 0xffff)
-
-#endif /* __HEADERGEN__IMX233__I2C__H__ */
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-icoll.h b/firmware/target/arm/imx233/regs/imx233/regs-icoll.h
deleted file mode 100644
index 015ce3effa..0000000000
--- a/firmware/target/arm/imx233/regs/imx233/regs-icoll.h
+++ /dev/null
@@ -1,350 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: imx233:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__IMX233__ICOLL__H__
-#define __HEADERGEN__IMX233__ICOLL__H__
-
-#define REGS_ICOLL_BASE (0x80000000)
-
-#define REGS_ICOLL_VERSION "3.2.0"
-
-/**
- * Register: HW_ICOLL_VECTOR
- * Address: 0
- * SCT: yes
-*/
-#define HW_ICOLL_VECTOR                 (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x0 + 0x0))
-#define HW_ICOLL_VECTOR_SET             (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x0 + 0x4))
-#define HW_ICOLL_VECTOR_CLR             (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x0 + 0x8))
-#define HW_ICOLL_VECTOR_TOG             (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x0 + 0xc))
-#define BP_ICOLL_VECTOR_IRQVECTOR       2
-#define BM_ICOLL_VECTOR_IRQVECTOR       0xfffffffc
-#define BF_ICOLL_VECTOR_IRQVECTOR(v)    (((v) << 2) & 0xfffffffc)
-#define BP_ICOLL_VECTOR_RSRVD1          0
-#define BM_ICOLL_VECTOR_RSRVD1          0x3
-#define BF_ICOLL_VECTOR_RSRVD1(v)       (((v) << 0) & 0x3)
-
-/**
- * Register: HW_ICOLL_LEVELACK
- * Address: 0x10
- * SCT: no
-*/
-#define HW_ICOLL_LEVELACK                       (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x10))
-#define BP_ICOLL_LEVELACK_RSRVD1                4
-#define BM_ICOLL_LEVELACK_RSRVD1                0xfffffff0
-#define BF_ICOLL_LEVELACK_RSRVD1(v)             (((v) << 4) & 0xfffffff0)
-#define BP_ICOLL_LEVELACK_IRQLEVELACK           0
-#define BM_ICOLL_LEVELACK_IRQLEVELACK           0xf
-#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0   0x1
-#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL1   0x2
-#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL2   0x4
-#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL3   0x8
-#define BF_ICOLL_LEVELACK_IRQLEVELACK(v)        (((v) << 0) & 0xf)
-#define BF_ICOLL_LEVELACK_IRQLEVELACK_V(v)      ((BV_ICOLL_LEVELACK_IRQLEVELACK__##v << 0) & 0xf)
-
-/**
- * Register: HW_ICOLL_CTRL
- * Address: 0x20
- * SCT: yes
-*/
-#define HW_ICOLL_CTRL                           (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x20 + 0x0))
-#define HW_ICOLL_CTRL_SET                       (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x20 + 0x4))
-#define HW_ICOLL_CTRL_CLR                       (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x20 + 0x8))
-#define HW_ICOLL_CTRL_TOG                       (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x20 + 0xc))
-#define BP_ICOLL_CTRL_SFTRST                    31
-#define BM_ICOLL_CTRL_SFTRST                    0x80000000
-#define BV_ICOLL_CTRL_SFTRST__RUN               0x0
-#define BV_ICOLL_CTRL_SFTRST__IN_RESET          0x1
-#define BF_ICOLL_CTRL_SFTRST(v)                 (((v) << 31) & 0x80000000)
-#define BF_ICOLL_CTRL_SFTRST_V(v)               ((BV_ICOLL_CTRL_SFTRST__##v << 31) & 0x80000000)
-#define BP_ICOLL_CTRL_CLKGATE                   30
-#define BM_ICOLL_CTRL_CLKGATE                   0x40000000
-#define BV_ICOLL_CTRL_CLKGATE__RUN              0x0
-#define BV_ICOLL_CTRL_CLKGATE__NO_CLOCKS        0x1
-#define BF_ICOLL_CTRL_CLKGATE(v)                (((v) << 30) & 0x40000000)
-#define BF_ICOLL_CTRL_CLKGATE_V(v)              ((BV_ICOLL_CTRL_CLKGATE__##v << 30) & 0x40000000)
-#define BP_ICOLL_CTRL_RSRVD3                    24
-#define BM_ICOLL_CTRL_RSRVD3                    0x3f000000
-#define BF_ICOLL_CTRL_RSRVD3(v)                 (((v) << 24) & 0x3f000000)
-#define BP_ICOLL_CTRL_VECTOR_PITCH              21
-#define BM_ICOLL_CTRL_VECTOR_PITCH              0xe00000
-#define BV_ICOLL_CTRL_VECTOR_PITCH__DEFAULT_BY4 0x0
-#define BV_ICOLL_CTRL_VECTOR_PITCH__BY4         0x1
-#define BV_ICOLL_CTRL_VECTOR_PITCH__BY8         0x2
-#define BV_ICOLL_CTRL_VECTOR_PITCH__BY12        0x3
-#define BV_ICOLL_CTRL_VECTOR_PITCH__BY16        0x4
-#define BV_ICOLL_CTRL_VECTOR_PITCH__BY20        0x5
-#define BV_ICOLL_CTRL_VECTOR_PITCH__BY24        0x6
-#define BV_ICOLL_CTRL_VECTOR_PITCH__BY28        0x7
-#define BF_ICOLL_CTRL_VECTOR_PITCH(v)           (((v) << 21) & 0xe00000)
-#define BF_ICOLL_CTRL_VECTOR_PITCH_V(v)         ((BV_ICOLL_CTRL_VECTOR_PITCH__##v << 21) & 0xe00000)
-#define BP_ICOLL_CTRL_BYPASS_FSM                20
-#define BM_ICOLL_CTRL_BYPASS_FSM                0x100000
-#define BV_ICOLL_CTRL_BYPASS_FSM__NORMAL        0x0
-#define BV_ICOLL_CTRL_BYPASS_FSM__BYPASS        0x1
-#define BF_ICOLL_CTRL_BYPASS_FSM(v)             (((v) << 20) & 0x100000)
-#define BF_ICOLL_CTRL_BYPASS_FSM_V(v)           ((BV_ICOLL_CTRL_BYPASS_FSM__##v << 20) & 0x100000)
-#define BP_ICOLL_CTRL_NO_NESTING                19
-#define BM_ICOLL_CTRL_NO_NESTING                0x80000
-#define BV_ICOLL_CTRL_NO_NESTING__NORMAL        0x0
-#define BV_ICOLL_CTRL_NO_NESTING__NO_NEST       0x1
-#define BF_ICOLL_CTRL_NO_NESTING(v)             (((v) << 19) & 0x80000)
-#define BF_ICOLL_CTRL_NO_NESTING_V(v)           ((BV_ICOLL_CTRL_NO_NESTING__##v << 19) & 0x80000)
-#define BP_ICOLL_CTRL_ARM_RSE_MODE              18
-#define BM_ICOLL_CTRL_ARM_RSE_MODE              0x40000
-#define BF_ICOLL_CTRL_ARM_RSE_MODE(v)           (((v) << 18) & 0x40000)
-#define BP_ICOLL_CTRL_FIQ_FINAL_ENABLE          17
-#define BM_ICOLL_CTRL_FIQ_FINAL_ENABLE          0x20000
-#define BV_ICOLL_CTRL_FIQ_FINAL_ENABLE__DISABLE 0x0
-#define BV_ICOLL_CTRL_FIQ_FINAL_ENABLE__ENABLE  0x1
-#define BF_ICOLL_CTRL_FIQ_FINAL_ENABLE(v)       (((v) << 17) & 0x20000)
-#define BF_ICOLL_CTRL_FIQ_FINAL_ENABLE_V(v)     ((BV_ICOLL_CTRL_FIQ_FINAL_ENABLE__##v << 17) & 0x20000)
-#define BP_ICOLL_CTRL_IRQ_FINAL_ENABLE          16
-#define BM_ICOLL_CTRL_IRQ_FINAL_ENABLE          0x10000
-#define BV_ICOLL_CTRL_IRQ_FINAL_ENABLE__DISABLE 0x0
-#define BV_ICOLL_CTRL_IRQ_FINAL_ENABLE__ENABLE  0x1
-#define BF_ICOLL_CTRL_IRQ_FINAL_ENABLE(v)       (((v) << 16) & 0x10000)
-#define BF_ICOLL_CTRL_IRQ_FINAL_ENABLE_V(v)     ((BV_ICOLL_CTRL_IRQ_FINAL_ENABLE__##v << 16) & 0x10000)
-#define BP_ICOLL_CTRL_RSRVD1                    0
-#define BM_ICOLL_CTRL_RSRVD1                    0xffff
-#define BF_ICOLL_CTRL_RSRVD1(v)                 (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_ICOLL_VBASE
- * Address: 0x40
- * SCT: yes
-*/
-#define HW_ICOLL_VBASE                  (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x40 + 0x0))
-#define HW_ICOLL_VBASE_SET              (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x40 + 0x4))
-#define HW_ICOLL_VBASE_CLR              (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x40 + 0x8))
-#define HW_ICOLL_VBASE_TOG              (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x40 + 0xc))
-#define BP_ICOLL_VBASE_TABLE_ADDRESS    2
-#define BM_ICOLL_VBASE_TABLE_ADDRESS    0xfffffffc
-#define BF_ICOLL_VBASE_TABLE_ADDRESS(v) (((v) << 2) & 0xfffffffc)
-#define BP_ICOLL_VBASE_RSRVD1           0
-#define BM_ICOLL_VBASE_RSRVD1           0x3
-#define BF_ICOLL_VBASE_RSRVD1(v)        (((v) << 0) & 0x3)
-
-/**
- * Register: HW_ICOLL_STAT
- * Address: 0x70
- * SCT: no
-*/
-#define HW_ICOLL_STAT                   (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x70))
-#define BP_ICOLL_STAT_RSRVD1            7
-#define BM_ICOLL_STAT_RSRVD1            0xffffff80
-#define BF_ICOLL_STAT_RSRVD1(v)         (((v) << 7) & 0xffffff80)
-#define BP_ICOLL_STAT_VECTOR_NUMBER     0
-#define BM_ICOLL_STAT_VECTOR_NUMBER     0x7f
-#define BF_ICOLL_STAT_VECTOR_NUMBER(v)  (((v) << 0) & 0x7f)
-
-/**
- * Register: HW_ICOLL_RAWn
- * Address: 0xa0+n*0x10
- * SCT: yes
-*/
-#define HW_ICOLL_RAWn(n)            (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0xa0+(n)*0x10 + 0x0))
-#define HW_ICOLL_RAWn_SET(n)        (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0xa0+(n)*0x10 + 0x4))
-#define HW_ICOLL_RAWn_CLR(n)        (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0xa0+(n)*0x10 + 0x8))
-#define HW_ICOLL_RAWn_TOG(n)        (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0xa0+(n)*0x10 + 0xc))
-#define BP_ICOLL_RAWn_RAW_IRQS      0
-#define BM_ICOLL_RAWn_RAW_IRQS      0xffffffff
-#define BF_ICOLL_RAWn_RAW_IRQS(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_ICOLL_INTERRUPTn
- * Address: 0x120+n*0x10
- * SCT: yes
-*/
-#define HW_ICOLL_INTERRUPTn(n)                          (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x120+(n)*0x10 + 0x0))
-#define HW_ICOLL_INTERRUPTn_SET(n)                      (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x120+(n)*0x10 + 0x4))
-#define HW_ICOLL_INTERRUPTn_CLR(n)                      (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x120+(n)*0x10 + 0x8))
-#define HW_ICOLL_INTERRUPTn_TOG(n)                      (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x120+(n)*0x10 + 0xc))
-#define BP_ICOLL_INTERRUPTn_RSRVD1                      5
-#define BM_ICOLL_INTERRUPTn_RSRVD1                      0xffffffe0
-#define BF_ICOLL_INTERRUPTn_RSRVD1(v)                   (((v) << 5) & 0xffffffe0)
-#define BP_ICOLL_INTERRUPTn_ENFIQ                       4
-#define BM_ICOLL_INTERRUPTn_ENFIQ                       0x10
-#define BV_ICOLL_INTERRUPTn_ENFIQ__DISABLE              0x0
-#define BV_ICOLL_INTERRUPTn_ENFIQ__ENABLE               0x1
-#define BF_ICOLL_INTERRUPTn_ENFIQ(v)                    (((v) << 4) & 0x10)
-#define BF_ICOLL_INTERRUPTn_ENFIQ_V(v)                  ((BV_ICOLL_INTERRUPTn_ENFIQ__##v << 4) & 0x10)
-#define BP_ICOLL_INTERRUPTn_SOFTIRQ                     3
-#define BM_ICOLL_INTERRUPTn_SOFTIRQ                     0x8
-#define BV_ICOLL_INTERRUPTn_SOFTIRQ__NO_INTERRUPT       0x0
-#define BV_ICOLL_INTERRUPTn_SOFTIRQ__FORCE_INTERRUPT    0x1
-#define BF_ICOLL_INTERRUPTn_SOFTIRQ(v)                  (((v) << 3) & 0x8)
-#define BF_ICOLL_INTERRUPTn_SOFTIRQ_V(v)                ((BV_ICOLL_INTERRUPTn_SOFTIRQ__##v << 3) & 0x8)
-#define BP_ICOLL_INTERRUPTn_ENABLE                      2
-#define BM_ICOLL_INTERRUPTn_ENABLE                      0x4
-#define BV_ICOLL_INTERRUPTn_ENABLE__DISABLE             0x0
-#define BV_ICOLL_INTERRUPTn_ENABLE__ENABLE              0x1
-#define BF_ICOLL_INTERRUPTn_ENABLE(v)                   (((v) << 2) & 0x4)
-#define BF_ICOLL_INTERRUPTn_ENABLE_V(v)                 ((BV_ICOLL_INTERRUPTn_ENABLE__##v << 2) & 0x4)
-#define BP_ICOLL_INTERRUPTn_PRIORITY                    0
-#define BM_ICOLL_INTERRUPTn_PRIORITY                    0x3
-#define BV_ICOLL_INTERRUPTn_PRIORITY__LEVEL0            0x0
-#define BV_ICOLL_INTERRUPTn_PRIORITY__LEVEL1            0x1
-#define BV_ICOLL_INTERRUPTn_PRIORITY__LEVEL2            0x2
-#define BV_ICOLL_INTERRUPTn_PRIORITY__LEVEL3            0x3
-#define BF_ICOLL_INTERRUPTn_PRIORITY(v)                 (((v) << 0) & 0x3)
-#define BF_ICOLL_INTERRUPTn_PRIORITY_V(v)               ((BV_ICOLL_INTERRUPTn_PRIORITY__##v << 0) & 0x3)
-
-/**
- * Register: HW_ICOLL_DEBUG
- * Address: 0x1120
- * SCT: yes
-*/
-#define HW_ICOLL_DEBUG                              (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1120 + 0x0))
-#define HW_ICOLL_DEBUG_SET                          (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1120 + 0x4))
-#define HW_ICOLL_DEBUG_CLR                          (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1120 + 0x8))
-#define HW_ICOLL_DEBUG_TOG                          (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1120 + 0xc))
-#define BP_ICOLL_DEBUG_INSERVICE                    28
-#define BM_ICOLL_DEBUG_INSERVICE                    0xf0000000
-#define BV_ICOLL_DEBUG_INSERVICE__LEVEL0            0x1
-#define BV_ICOLL_DEBUG_INSERVICE__LEVEL1            0x2
-#define BV_ICOLL_DEBUG_INSERVICE__LEVEL2            0x4
-#define BV_ICOLL_DEBUG_INSERVICE__LEVEL3            0x8
-#define BF_ICOLL_DEBUG_INSERVICE(v)                 (((v) << 28) & 0xf0000000)
-#define BF_ICOLL_DEBUG_INSERVICE_V(v)               ((BV_ICOLL_DEBUG_INSERVICE__##v << 28) & 0xf0000000)
-#define BP_ICOLL_DEBUG_LEVEL_REQUESTS               24
-#define BM_ICOLL_DEBUG_LEVEL_REQUESTS               0xf000000
-#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL0       0x1
-#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL1       0x2
-#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL2       0x4
-#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL3       0x8
-#define BF_ICOLL_DEBUG_LEVEL_REQUESTS(v)            (((v) << 24) & 0xf000000)
-#define BF_ICOLL_DEBUG_LEVEL_REQUESTS_V(v)          ((BV_ICOLL_DEBUG_LEVEL_REQUESTS__##v << 24) & 0xf000000)
-#define BP_ICOLL_DEBUG_REQUESTS_BY_LEVEL            20
-#define BM_ICOLL_DEBUG_REQUESTS_BY_LEVEL            0xf00000
-#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL0    0x1
-#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL1    0x2
-#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL2    0x4
-#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL3    0x8
-#define BF_ICOLL_DEBUG_REQUESTS_BY_LEVEL(v)         (((v) << 20) & 0xf00000)
-#define BF_ICOLL_DEBUG_REQUESTS_BY_LEVEL_V(v)       ((BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__##v << 20) & 0xf00000)
-#define BP_ICOLL_DEBUG_RSRVD2                       18
-#define BM_ICOLL_DEBUG_RSRVD2                       0xc0000
-#define BF_ICOLL_DEBUG_RSRVD2(v)                    (((v) << 18) & 0xc0000)
-#define BP_ICOLL_DEBUG_FIQ                          17
-#define BM_ICOLL_DEBUG_FIQ                          0x20000
-#define BV_ICOLL_DEBUG_FIQ__NO_FIQ_REQUESTED        0x0
-#define BV_ICOLL_DEBUG_FIQ__FIQ_REQUESTED           0x1
-#define BF_ICOLL_DEBUG_FIQ(v)                       (((v) << 17) & 0x20000)
-#define BF_ICOLL_DEBUG_FIQ_V(v)                     ((BV_ICOLL_DEBUG_FIQ__##v << 17) & 0x20000)
-#define BP_ICOLL_DEBUG_IRQ                          16
-#define BM_ICOLL_DEBUG_IRQ                          0x10000
-#define BV_ICOLL_DEBUG_IRQ__NO_IRQ_REQUESTED        0x0
-#define BV_ICOLL_DEBUG_IRQ__IRQ_REQUESTED           0x1
-#define BF_ICOLL_DEBUG_IRQ(v)                       (((v) << 16) & 0x10000)
-#define BF_ICOLL_DEBUG_IRQ_V(v)                     ((BV_ICOLL_DEBUG_IRQ__##v << 16) & 0x10000)
-#define BP_ICOLL_DEBUG_RSRVD1                       10
-#define BM_ICOLL_DEBUG_RSRVD1                       0xfc00
-#define BF_ICOLL_DEBUG_RSRVD1(v)                    (((v) << 10) & 0xfc00)
-#define BP_ICOLL_DEBUG_VECTOR_FSM                   0
-#define BM_ICOLL_DEBUG_VECTOR_FSM                   0x3ff
-#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_IDLE         0x0
-#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE1  0x1
-#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE2  0x2
-#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_PENDING      0x4
-#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE3  0x8
-#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE4  0x10
-#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING1 0x20
-#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING2 0x40
-#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING3 0x80
-#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE5  0x100
-#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE6  0x200
-#define BF_ICOLL_DEBUG_VECTOR_FSM(v)                (((v) << 0) & 0x3ff)
-#define BF_ICOLL_DEBUG_VECTOR_FSM_V(v)              ((BV_ICOLL_DEBUG_VECTOR_FSM__##v << 0) & 0x3ff)
-
-/**
- * Register: HW_ICOLL_DBGREAD0
- * Address: 0x1130
- * SCT: yes
-*/
-#define HW_ICOLL_DBGREAD0           (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1130 + 0x0))
-#define HW_ICOLL_DBGREAD0_SET       (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1130 + 0x4))
-#define HW_ICOLL_DBGREAD0_CLR       (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1130 + 0x8))
-#define HW_ICOLL_DBGREAD0_TOG       (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1130 + 0xc))
-#define BP_ICOLL_DBGREAD0_VALUE     0
-#define BM_ICOLL_DBGREAD0_VALUE     0xffffffff
-#define BF_ICOLL_DBGREAD0_VALUE(v)  (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_ICOLL_DBGREAD1
- * Address: 0x1140
- * SCT: yes
-*/
-#define HW_ICOLL_DBGREAD1           (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1140 + 0x0))
-#define HW_ICOLL_DBGREAD1_SET       (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1140 + 0x4))
-#define HW_ICOLL_DBGREAD1_CLR       (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1140 + 0x8))
-#define HW_ICOLL_DBGREAD1_TOG       (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1140 + 0xc))
-#define BP_ICOLL_DBGREAD1_VALUE     0
-#define BM_ICOLL_DBGREAD1_VALUE     0xffffffff
-#define BF_ICOLL_DBGREAD1_VALUE(v)  (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_ICOLL_DBGFLAG
- * Address: 0x1150
- * SCT: yes
-*/
-#define HW_ICOLL_DBGFLAG            (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1150 + 0x0))
-#define HW_ICOLL_DBGFLAG_SET        (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1150 + 0x4))
-#define HW_ICOLL_DBGFLAG_CLR        (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1150 + 0x8))
-#define HW_ICOLL_DBGFLAG_TOG        (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1150 + 0xc))
-#define BP_ICOLL_DBGFLAG_RSRVD1     16
-#define BM_ICOLL_DBGFLAG_RSRVD1     0xffff0000
-#define BF_ICOLL_DBGFLAG_RSRVD1(v)  (((v) << 16) & 0xffff0000)
-#define BP_ICOLL_DBGFLAG_FLAG       0
-#define BM_ICOLL_DBGFLAG_FLAG       0xffff
-#define BF_ICOLL_DBGFLAG_FLAG(v)    (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_ICOLL_DBGREQUESTn
- * Address: 0x1160+n*0x10
- * SCT: yes
-*/
-#define HW_ICOLL_DBGREQUESTn(n)         (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1160+(n)*0x10 + 0x0))
-#define HW_ICOLL_DBGREQUESTn_SET(n)     (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1160+(n)*0x10 + 0x4))
-#define HW_ICOLL_DBGREQUESTn_CLR(n)     (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1160+(n)*0x10 + 0x8))
-#define HW_ICOLL_DBGREQUESTn_TOG(n)     (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1160+(n)*0x10 + 0xc))
-#define BP_ICOLL_DBGREQUESTn_BITS       0
-#define BM_ICOLL_DBGREQUESTn_BITS       0xffffffff
-#define BF_ICOLL_DBGREQUESTn_BITS(v)    (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_ICOLL_VERSION
- * Address: 0x11e0
- * SCT: no
-*/
-#define HW_ICOLL_VERSION            (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x11e0))
-#define BP_ICOLL_VERSION_MAJOR      24
-#define BM_ICOLL_VERSION_MAJOR      0xff000000
-#define BF_ICOLL_VERSION_MAJOR(v)   (((v) << 24) & 0xff000000)
-#define BP_ICOLL_VERSION_MINOR      16
-#define BM_ICOLL_VERSION_MINOR      0xff0000
-#define BF_ICOLL_VERSION_MINOR(v)   (((v) << 16) & 0xff0000)
-#define BP_ICOLL_VERSION_STEP       0
-#define BM_ICOLL_VERSION_STEP       0xffff
-#define BF_ICOLL_VERSION_STEP(v)    (((v) << 0) & 0xffff)
-
-#endif /* __HEADERGEN__IMX233__ICOLL__H__ */
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-ir.h b/firmware/target/arm/imx233/regs/imx233/regs-ir.h
deleted file mode 100644
index 48d4159234..0000000000
--- a/firmware/target/arm/imx233/regs/imx233/regs-ir.h
+++ /dev/null
@@ -1,529 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: imx233:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__IMX233__IR__H__
-#define __HEADERGEN__IMX233__IR__H__
-
-#define REGS_IR_BASE (0x80078000)
-
-#define REGS_IR_VERSION "3.2.0"
-
-/**
- * Register: HW_IR_CTRL
- * Address: 0
- * SCT: yes
-*/
-#define HW_IR_CTRL                  (*(volatile unsigned long *)(REGS_IR_BASE + 0x0 + 0x0))
-#define HW_IR_CTRL_SET              (*(volatile unsigned long *)(REGS_IR_BASE + 0x0 + 0x4))
-#define HW_IR_CTRL_CLR              (*(volatile unsigned long *)(REGS_IR_BASE + 0x0 + 0x8))
-#define HW_IR_CTRL_TOG              (*(volatile unsigned long *)(REGS_IR_BASE + 0x0 + 0xc))
-#define BP_IR_CTRL_SFTRST           31
-#define BM_IR_CTRL_SFTRST           0x80000000
-#define BV_IR_CTRL_SFTRST__RUN      0x0
-#define BV_IR_CTRL_SFTRST__RESET    0x1
-#define BF_IR_CTRL_SFTRST(v)        (((v) << 31) & 0x80000000)
-#define BF_IR_CTRL_SFTRST_V(v)      ((BV_IR_CTRL_SFTRST__##v << 31) & 0x80000000)
-#define BP_IR_CTRL_CLKGATE          30
-#define BM_IR_CTRL_CLKGATE          0x40000000
-#define BF_IR_CTRL_CLKGATE(v)       (((v) << 30) & 0x40000000)
-#define BP_IR_CTRL_RSVD2            27
-#define BM_IR_CTRL_RSVD2            0x38000000
-#define BF_IR_CTRL_RSVD2(v)         (((v) << 27) & 0x38000000)
-#define BP_IR_CTRL_MTA              24
-#define BM_IR_CTRL_MTA              0x7000000
-#define BV_IR_CTRL_MTA__MTA_10MS    0x0
-#define BV_IR_CTRL_MTA__MTA_5MS     0x1
-#define BV_IR_CTRL_MTA__MTA_1MS     0x2
-#define BV_IR_CTRL_MTA__MTA_500US   0x3
-#define BV_IR_CTRL_MTA__MTA_100US   0x4
-#define BV_IR_CTRL_MTA__MTA_50US    0x5
-#define BV_IR_CTRL_MTA__MTA_10US    0x6
-#define BV_IR_CTRL_MTA__MTA_0       0x7
-#define BF_IR_CTRL_MTA(v)           (((v) << 24) & 0x7000000)
-#define BF_IR_CTRL_MTA_V(v)         ((BV_IR_CTRL_MTA__##v << 24) & 0x7000000)
-#define BP_IR_CTRL_MODE             22
-#define BM_IR_CTRL_MODE             0xc00000
-#define BV_IR_CTRL_MODE__SIR        0x0
-#define BV_IR_CTRL_MODE__MIR        0x1
-#define BV_IR_CTRL_MODE__FIR        0x2
-#define BV_IR_CTRL_MODE__VFIR       0x3
-#define BF_IR_CTRL_MODE(v)          (((v) << 22) & 0xc00000)
-#define BF_IR_CTRL_MODE_V(v)        ((BV_IR_CTRL_MODE__##v << 22) & 0xc00000)
-#define BP_IR_CTRL_SPEED            19
-#define BM_IR_CTRL_SPEED            0x380000
-#define BV_IR_CTRL_SPEED__SPD000    0x0
-#define BV_IR_CTRL_SPEED__SPD001    0x1
-#define BV_IR_CTRL_SPEED__SPD010    0x2
-#define BV_IR_CTRL_SPEED__SPD011    0x3
-#define BV_IR_CTRL_SPEED__SPD100    0x4
-#define BV_IR_CTRL_SPEED__SPD101    0x5
-#define BF_IR_CTRL_SPEED(v)         (((v) << 19) & 0x380000)
-#define BF_IR_CTRL_SPEED_V(v)       ((BV_IR_CTRL_SPEED__##v << 19) & 0x380000)
-#define BP_IR_CTRL_RSVD1            14
-#define BM_IR_CTRL_RSVD1            0x7c000
-#define BF_IR_CTRL_RSVD1(v)         (((v) << 14) & 0x7c000)
-#define BP_IR_CTRL_TC_TIME_DIV      8
-#define BM_IR_CTRL_TC_TIME_DIV      0x3f00
-#define BF_IR_CTRL_TC_TIME_DIV(v)   (((v) << 8) & 0x3f00)
-#define BP_IR_CTRL_TC_TYPE          7
-#define BM_IR_CTRL_TC_TYPE          0x80
-#define BF_IR_CTRL_TC_TYPE(v)       (((v) << 7) & 0x80)
-#define BP_IR_CTRL_SIR_GAP          4
-#define BM_IR_CTRL_SIR_GAP          0x70
-#define BV_IR_CTRL_SIR_GAP__GAP_10K 0x0
-#define BV_IR_CTRL_SIR_GAP__GAP_5K  0x1
-#define BV_IR_CTRL_SIR_GAP__GAP_1K  0x2
-#define BV_IR_CTRL_SIR_GAP__GAP_500 0x3
-#define BV_IR_CTRL_SIR_GAP__GAP_100 0x4
-#define BV_IR_CTRL_SIR_GAP__GAP_50  0x5
-#define BV_IR_CTRL_SIR_GAP__GAP_10  0x6
-#define BV_IR_CTRL_SIR_GAP__GAP_0   0x7
-#define BF_IR_CTRL_SIR_GAP(v)       (((v) << 4) & 0x70)
-#define BF_IR_CTRL_SIR_GAP_V(v)     ((BV_IR_CTRL_SIR_GAP__##v << 4) & 0x70)
-#define BP_IR_CTRL_SIPEN            3
-#define BM_IR_CTRL_SIPEN            0x8
-#define BF_IR_CTRL_SIPEN(v)         (((v) << 3) & 0x8)
-#define BP_IR_CTRL_TCEN             2
-#define BM_IR_CTRL_TCEN             0x4
-#define BF_IR_CTRL_TCEN(v)          (((v) << 2) & 0x4)
-#define BP_IR_CTRL_TXEN             1
-#define BM_IR_CTRL_TXEN             0x2
-#define BF_IR_CTRL_TXEN(v)          (((v) << 1) & 0x2)
-#define BP_IR_CTRL_RXEN             0
-#define BM_IR_CTRL_RXEN             0x1
-#define BF_IR_CTRL_RXEN(v)          (((v) << 0) & 0x1)
-
-/**
- * Register: HW_IR_TXDMA
- * Address: 0x10
- * SCT: yes
-*/
-#define HW_IR_TXDMA                 (*(volatile unsigned long *)(REGS_IR_BASE + 0x10 + 0x0))
-#define HW_IR_TXDMA_SET             (*(volatile unsigned long *)(REGS_IR_BASE + 0x10 + 0x4))
-#define HW_IR_TXDMA_CLR             (*(volatile unsigned long *)(REGS_IR_BASE + 0x10 + 0x8))
-#define HW_IR_TXDMA_TOG             (*(volatile unsigned long *)(REGS_IR_BASE + 0x10 + 0xc))
-#define BP_IR_TXDMA_RUN             31
-#define BM_IR_TXDMA_RUN             0x80000000
-#define BF_IR_TXDMA_RUN(v)          (((v) << 31) & 0x80000000)
-#define BP_IR_TXDMA_RSVD2           30
-#define BM_IR_TXDMA_RSVD2           0x40000000
-#define BF_IR_TXDMA_RSVD2(v)        (((v) << 30) & 0x40000000)
-#define BP_IR_TXDMA_EMPTY           29
-#define BM_IR_TXDMA_EMPTY           0x20000000
-#define BF_IR_TXDMA_EMPTY(v)        (((v) << 29) & 0x20000000)
-#define BP_IR_TXDMA_INT             28
-#define BM_IR_TXDMA_INT             0x10000000
-#define BF_IR_TXDMA_INT(v)          (((v) << 28) & 0x10000000)
-#define BP_IR_TXDMA_CHANGE          27
-#define BM_IR_TXDMA_CHANGE          0x8000000
-#define BF_IR_TXDMA_CHANGE(v)       (((v) << 27) & 0x8000000)
-#define BP_IR_TXDMA_NEW_MTA         24
-#define BM_IR_TXDMA_NEW_MTA         0x7000000
-#define BF_IR_TXDMA_NEW_MTA(v)      (((v) << 24) & 0x7000000)
-#define BP_IR_TXDMA_NEW_MODE        22
-#define BM_IR_TXDMA_NEW_MODE        0xc00000
-#define BF_IR_TXDMA_NEW_MODE(v)     (((v) << 22) & 0xc00000)
-#define BP_IR_TXDMA_NEW_SPEED       19
-#define BM_IR_TXDMA_NEW_SPEED       0x380000
-#define BF_IR_TXDMA_NEW_SPEED(v)    (((v) << 19) & 0x380000)
-#define BP_IR_TXDMA_BOF_TYPE        18
-#define BM_IR_TXDMA_BOF_TYPE        0x40000
-#define BF_IR_TXDMA_BOF_TYPE(v)     (((v) << 18) & 0x40000)
-#define BP_IR_TXDMA_XBOFS           12
-#define BM_IR_TXDMA_XBOFS           0x3f000
-#define BF_IR_TXDMA_XBOFS(v)        (((v) << 12) & 0x3f000)
-#define BP_IR_TXDMA_XFER_COUNT      0
-#define BM_IR_TXDMA_XFER_COUNT      0xfff
-#define BF_IR_TXDMA_XFER_COUNT(v)   (((v) << 0) & 0xfff)
-
-/**
- * Register: HW_IR_RXDMA
- * Address: 0x20
- * SCT: yes
-*/
-#define HW_IR_RXDMA                 (*(volatile unsigned long *)(REGS_IR_BASE + 0x20 + 0x0))
-#define HW_IR_RXDMA_SET             (*(volatile unsigned long *)(REGS_IR_BASE + 0x20 + 0x4))
-#define HW_IR_RXDMA_CLR             (*(volatile unsigned long *)(REGS_IR_BASE + 0x20 + 0x8))
-#define HW_IR_RXDMA_TOG             (*(volatile unsigned long *)(REGS_IR_BASE + 0x20 + 0xc))
-#define BP_IR_RXDMA_RUN             31
-#define BM_IR_RXDMA_RUN             0x80000000
-#define BF_IR_RXDMA_RUN(v)          (((v) << 31) & 0x80000000)
-#define BP_IR_RXDMA_RSVD            10
-#define BM_IR_RXDMA_RSVD            0x7ffffc00
-#define BF_IR_RXDMA_RSVD(v)         (((v) << 10) & 0x7ffffc00)
-#define BP_IR_RXDMA_XFER_COUNT      0
-#define BM_IR_RXDMA_XFER_COUNT      0x3ff
-#define BF_IR_RXDMA_XFER_COUNT(v)   (((v) << 0) & 0x3ff)
-
-/**
- * Register: HW_IR_DBGCTRL
- * Address: 0x30
- * SCT: yes
-*/
-#define HW_IR_DBGCTRL                   (*(volatile unsigned long *)(REGS_IR_BASE + 0x30 + 0x0))
-#define HW_IR_DBGCTRL_SET               (*(volatile unsigned long *)(REGS_IR_BASE + 0x30 + 0x4))
-#define HW_IR_DBGCTRL_CLR               (*(volatile unsigned long *)(REGS_IR_BASE + 0x30 + 0x8))
-#define HW_IR_DBGCTRL_TOG               (*(volatile unsigned long *)(REGS_IR_BASE + 0x30 + 0xc))
-#define BP_IR_DBGCTRL_RSVD2             13
-#define BM_IR_DBGCTRL_RSVD2             0xffffe000
-#define BF_IR_DBGCTRL_RSVD2(v)          (((v) << 13) & 0xffffe000)
-#define BP_IR_DBGCTRL_VFIRSWZ           12
-#define BM_IR_DBGCTRL_VFIRSWZ           0x1000
-#define BV_IR_DBGCTRL_VFIRSWZ__NORMAL   0x0
-#define BV_IR_DBGCTRL_VFIRSWZ__SWAP     0x1
-#define BF_IR_DBGCTRL_VFIRSWZ(v)        (((v) << 12) & 0x1000)
-#define BF_IR_DBGCTRL_VFIRSWZ_V(v)      ((BV_IR_DBGCTRL_VFIRSWZ__##v << 12) & 0x1000)
-#define BP_IR_DBGCTRL_RXFRMOFF          11
-#define BM_IR_DBGCTRL_RXFRMOFF          0x800
-#define BF_IR_DBGCTRL_RXFRMOFF(v)       (((v) << 11) & 0x800)
-#define BP_IR_DBGCTRL_RXCRCOFF          10
-#define BM_IR_DBGCTRL_RXCRCOFF          0x400
-#define BF_IR_DBGCTRL_RXCRCOFF(v)       (((v) << 10) & 0x400)
-#define BP_IR_DBGCTRL_RXINVERT          9
-#define BM_IR_DBGCTRL_RXINVERT          0x200
-#define BF_IR_DBGCTRL_RXINVERT(v)       (((v) << 9) & 0x200)
-#define BP_IR_DBGCTRL_TXFRMOFF          8
-#define BM_IR_DBGCTRL_TXFRMOFF          0x100
-#define BF_IR_DBGCTRL_TXFRMOFF(v)       (((v) << 8) & 0x100)
-#define BP_IR_DBGCTRL_TXCRCOFF          7
-#define BM_IR_DBGCTRL_TXCRCOFF          0x80
-#define BF_IR_DBGCTRL_TXCRCOFF(v)       (((v) << 7) & 0x80)
-#define BP_IR_DBGCTRL_TXINVERT          6
-#define BM_IR_DBGCTRL_TXINVERT          0x40
-#define BF_IR_DBGCTRL_TXINVERT(v)       (((v) << 6) & 0x40)
-#define BP_IR_DBGCTRL_INTLOOPBACK       5
-#define BM_IR_DBGCTRL_INTLOOPBACK       0x20
-#define BF_IR_DBGCTRL_INTLOOPBACK(v)    (((v) << 5) & 0x20)
-#define BP_IR_DBGCTRL_DUPLEX            4
-#define BM_IR_DBGCTRL_DUPLEX            0x10
-#define BF_IR_DBGCTRL_DUPLEX(v)         (((v) << 4) & 0x10)
-#define BP_IR_DBGCTRL_MIO_RX            3
-#define BM_IR_DBGCTRL_MIO_RX            0x8
-#define BF_IR_DBGCTRL_MIO_RX(v)         (((v) << 3) & 0x8)
-#define BP_IR_DBGCTRL_MIO_TX            2
-#define BM_IR_DBGCTRL_MIO_TX            0x4
-#define BF_IR_DBGCTRL_MIO_TX(v)         (((v) << 2) & 0x4)
-#define BP_IR_DBGCTRL_MIO_SCLK          1
-#define BM_IR_DBGCTRL_MIO_SCLK          0x2
-#define BF_IR_DBGCTRL_MIO_SCLK(v)       (((v) << 1) & 0x2)
-#define BP_IR_DBGCTRL_MIO_EN            0
-#define BM_IR_DBGCTRL_MIO_EN            0x1
-#define BF_IR_DBGCTRL_MIO_EN(v)         (((v) << 0) & 0x1)
-
-/**
- * Register: HW_IR_INTR
- * Address: 0x40
- * SCT: yes
-*/
-#define HW_IR_INTR                          (*(volatile unsigned long *)(REGS_IR_BASE + 0x40 + 0x0))
-#define HW_IR_INTR_SET                      (*(volatile unsigned long *)(REGS_IR_BASE + 0x40 + 0x4))
-#define HW_IR_INTR_CLR                      (*(volatile unsigned long *)(REGS_IR_BASE + 0x40 + 0x8))
-#define HW_IR_INTR_TOG                      (*(volatile unsigned long *)(REGS_IR_BASE + 0x40 + 0xc))
-#define BP_IR_INTR_RSVD2                    23
-#define BM_IR_INTR_RSVD2                    0xff800000
-#define BF_IR_INTR_RSVD2(v)                 (((v) << 23) & 0xff800000)
-#define BP_IR_INTR_RXABORT_IRQ_EN           22
-#define BM_IR_INTR_RXABORT_IRQ_EN           0x400000
-#define BV_IR_INTR_RXABORT_IRQ_EN__DISABLED 0x0
-#define BV_IR_INTR_RXABORT_IRQ_EN__ENABLED  0x1
-#define BF_IR_INTR_RXABORT_IRQ_EN(v)        (((v) << 22) & 0x400000)
-#define BF_IR_INTR_RXABORT_IRQ_EN_V(v)      ((BV_IR_INTR_RXABORT_IRQ_EN__##v << 22) & 0x400000)
-#define BP_IR_INTR_SPEED_IRQ_EN             21
-#define BM_IR_INTR_SPEED_IRQ_EN             0x200000
-#define BV_IR_INTR_SPEED_IRQ_EN__DISABLED   0x0
-#define BV_IR_INTR_SPEED_IRQ_EN__ENABLED    0x1
-#define BF_IR_INTR_SPEED_IRQ_EN(v)          (((v) << 21) & 0x200000)
-#define BF_IR_INTR_SPEED_IRQ_EN_V(v)        ((BV_IR_INTR_SPEED_IRQ_EN__##v << 21) & 0x200000)
-#define BP_IR_INTR_RXOF_IRQ_EN              20
-#define BM_IR_INTR_RXOF_IRQ_EN              0x100000
-#define BV_IR_INTR_RXOF_IRQ_EN__DISABLED    0x0
-#define BV_IR_INTR_RXOF_IRQ_EN__ENABLED     0x1
-#define BF_IR_INTR_RXOF_IRQ_EN(v)           (((v) << 20) & 0x100000)
-#define BF_IR_INTR_RXOF_IRQ_EN_V(v)         ((BV_IR_INTR_RXOF_IRQ_EN__##v << 20) & 0x100000)
-#define BP_IR_INTR_TXUF_IRQ_EN              19
-#define BM_IR_INTR_TXUF_IRQ_EN              0x80000
-#define BV_IR_INTR_TXUF_IRQ_EN__DISABLED    0x0
-#define BV_IR_INTR_TXUF_IRQ_EN__ENABLED     0x1
-#define BF_IR_INTR_TXUF_IRQ_EN(v)           (((v) << 19) & 0x80000)
-#define BF_IR_INTR_TXUF_IRQ_EN_V(v)         ((BV_IR_INTR_TXUF_IRQ_EN__##v << 19) & 0x80000)
-#define BP_IR_INTR_TC_IRQ_EN                18
-#define BM_IR_INTR_TC_IRQ_EN                0x40000
-#define BV_IR_INTR_TC_IRQ_EN__DISABLED      0x0
-#define BV_IR_INTR_TC_IRQ_EN__ENABLED       0x1
-#define BF_IR_INTR_TC_IRQ_EN(v)             (((v) << 18) & 0x40000)
-#define BF_IR_INTR_TC_IRQ_EN_V(v)           ((BV_IR_INTR_TC_IRQ_EN__##v << 18) & 0x40000)
-#define BP_IR_INTR_RX_IRQ_EN                17
-#define BM_IR_INTR_RX_IRQ_EN                0x20000
-#define BV_IR_INTR_RX_IRQ_EN__DISABLED      0x0
-#define BV_IR_INTR_RX_IRQ_EN__ENABLED       0x1
-#define BF_IR_INTR_RX_IRQ_EN(v)             (((v) << 17) & 0x20000)
-#define BF_IR_INTR_RX_IRQ_EN_V(v)           ((BV_IR_INTR_RX_IRQ_EN__##v << 17) & 0x20000)
-#define BP_IR_INTR_TX_IRQ_EN                16
-#define BM_IR_INTR_TX_IRQ_EN                0x10000
-#define BV_IR_INTR_TX_IRQ_EN__DISABLED      0x0
-#define BV_IR_INTR_TX_IRQ_EN__ENABLED       0x1
-#define BF_IR_INTR_TX_IRQ_EN(v)             (((v) << 16) & 0x10000)
-#define BF_IR_INTR_TX_IRQ_EN_V(v)           ((BV_IR_INTR_TX_IRQ_EN__##v << 16) & 0x10000)
-#define BP_IR_INTR_RSVD1                    7
-#define BM_IR_INTR_RSVD1                    0xff80
-#define BF_IR_INTR_RSVD1(v)                 (((v) << 7) & 0xff80)
-#define BP_IR_INTR_RXABORT_IRQ              6
-#define BM_IR_INTR_RXABORT_IRQ              0x40
-#define BV_IR_INTR_RXABORT_IRQ__NO_REQUEST  0x0
-#define BV_IR_INTR_RXABORT_IRQ__REQUEST     0x1
-#define BF_IR_INTR_RXABORT_IRQ(v)           (((v) << 6) & 0x40)
-#define BF_IR_INTR_RXABORT_IRQ_V(v)         ((BV_IR_INTR_RXABORT_IRQ__##v << 6) & 0x40)
-#define BP_IR_INTR_SPEED_IRQ                5
-#define BM_IR_INTR_SPEED_IRQ                0x20
-#define BV_IR_INTR_SPEED_IRQ__NO_REQUEST    0x0
-#define BV_IR_INTR_SPEED_IRQ__REQUEST       0x1
-#define BF_IR_INTR_SPEED_IRQ(v)             (((v) << 5) & 0x20)
-#define BF_IR_INTR_SPEED_IRQ_V(v)           ((BV_IR_INTR_SPEED_IRQ__##v << 5) & 0x20)
-#define BP_IR_INTR_RXOF_IRQ                 4
-#define BM_IR_INTR_RXOF_IRQ                 0x10
-#define BV_IR_INTR_RXOF_IRQ__NO_REQUEST     0x0
-#define BV_IR_INTR_RXOF_IRQ__REQUEST        0x1
-#define BF_IR_INTR_RXOF_IRQ(v)              (((v) << 4) & 0x10)
-#define BF_IR_INTR_RXOF_IRQ_V(v)            ((BV_IR_INTR_RXOF_IRQ__##v << 4) & 0x10)
-#define BP_IR_INTR_TXUF_IRQ                 3
-#define BM_IR_INTR_TXUF_IRQ                 0x8
-#define BV_IR_INTR_TXUF_IRQ__NO_REQUEST     0x0
-#define BV_IR_INTR_TXUF_IRQ__REQUEST        0x1
-#define BF_IR_INTR_TXUF_IRQ(v)              (((v) << 3) & 0x8)
-#define BF_IR_INTR_TXUF_IRQ_V(v)            ((BV_IR_INTR_TXUF_IRQ__##v << 3) & 0x8)
-#define BP_IR_INTR_TC_IRQ                   2
-#define BM_IR_INTR_TC_IRQ                   0x4
-#define BV_IR_INTR_TC_IRQ__NO_REQUEST       0x0
-#define BV_IR_INTR_TC_IRQ__REQUEST          0x1
-#define BF_IR_INTR_TC_IRQ(v)                (((v) << 2) & 0x4)
-#define BF_IR_INTR_TC_IRQ_V(v)              ((BV_IR_INTR_TC_IRQ__##v << 2) & 0x4)
-#define BP_IR_INTR_RX_IRQ                   1
-#define BM_IR_INTR_RX_IRQ                   0x2
-#define BV_IR_INTR_RX_IRQ__NO_REQUEST       0x0
-#define BV_IR_INTR_RX_IRQ__REQUEST          0x1
-#define BF_IR_INTR_RX_IRQ(v)                (((v) << 1) & 0x2)
-#define BF_IR_INTR_RX_IRQ_V(v)              ((BV_IR_INTR_RX_IRQ__##v << 1) & 0x2)
-#define BP_IR_INTR_TX_IRQ                   0
-#define BM_IR_INTR_TX_IRQ                   0x1
-#define BV_IR_INTR_TX_IRQ__NO_REQUEST       0x0
-#define BV_IR_INTR_TX_IRQ__REQUEST          0x1
-#define BF_IR_INTR_TX_IRQ(v)                (((v) << 0) & 0x1)
-#define BF_IR_INTR_TX_IRQ_V(v)              ((BV_IR_INTR_TX_IRQ__##v << 0) & 0x1)
-
-/**
- * Register: HW_IR_DATA
- * Address: 0x50
- * SCT: no
-*/
-#define HW_IR_DATA          (*(volatile unsigned long *)(REGS_IR_BASE + 0x50))
-#define BP_IR_DATA_DATA     0
-#define BM_IR_DATA_DATA     0xffffffff
-#define BF_IR_DATA_DATA(v)  (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_IR_STAT
- * Address: 0x60
- * SCT: no
-*/
-#define HW_IR_STAT                              (*(volatile unsigned long *)(REGS_IR_BASE + 0x60))
-#define BP_IR_STAT_PRESENT                      31
-#define BM_IR_STAT_PRESENT                      0x80000000
-#define BV_IR_STAT_PRESENT__UNAVAILABLE         0x0
-#define BV_IR_STAT_PRESENT__AVAILABLE           0x1
-#define BF_IR_STAT_PRESENT(v)                   (((v) << 31) & 0x80000000)
-#define BF_IR_STAT_PRESENT_V(v)                 ((BV_IR_STAT_PRESENT__##v << 31) & 0x80000000)
-#define BP_IR_STAT_MODE_ALLOWED                 29
-#define BM_IR_STAT_MODE_ALLOWED                 0x60000000
-#define BV_IR_STAT_MODE_ALLOWED__VFIR           0x0
-#define BV_IR_STAT_MODE_ALLOWED__FIR            0x1
-#define BV_IR_STAT_MODE_ALLOWED__MIR            0x2
-#define BV_IR_STAT_MODE_ALLOWED__SIR            0x3
-#define BF_IR_STAT_MODE_ALLOWED(v)              (((v) << 29) & 0x60000000)
-#define BF_IR_STAT_MODE_ALLOWED_V(v)            ((BV_IR_STAT_MODE_ALLOWED__##v << 29) & 0x60000000)
-#define BP_IR_STAT_ANY_IRQ                      28
-#define BM_IR_STAT_ANY_IRQ                      0x10000000
-#define BV_IR_STAT_ANY_IRQ__NO_REQUEST          0x0
-#define BV_IR_STAT_ANY_IRQ__REQUEST             0x1
-#define BF_IR_STAT_ANY_IRQ(v)                   (((v) << 28) & 0x10000000)
-#define BF_IR_STAT_ANY_IRQ_V(v)                 ((BV_IR_STAT_ANY_IRQ__##v << 28) & 0x10000000)
-#define BP_IR_STAT_RSVD2                        23
-#define BM_IR_STAT_RSVD2                        0xf800000
-#define BF_IR_STAT_RSVD2(v)                     (((v) << 23) & 0xf800000)
-#define BP_IR_STAT_RXABORT_SUMMARY              22
-#define BM_IR_STAT_RXABORT_SUMMARY              0x400000
-#define BV_IR_STAT_RXABORT_SUMMARY__NO_REQUEST  0x0
-#define BV_IR_STAT_RXABORT_SUMMARY__REQUEST     0x1
-#define BF_IR_STAT_RXABORT_SUMMARY(v)           (((v) << 22) & 0x400000)
-#define BF_IR_STAT_RXABORT_SUMMARY_V(v)         ((BV_IR_STAT_RXABORT_SUMMARY__##v << 22) & 0x400000)
-#define BP_IR_STAT_SPEED_SUMMARY                21
-#define BM_IR_STAT_SPEED_SUMMARY                0x200000
-#define BV_IR_STAT_SPEED_SUMMARY__NO_REQUEST    0x0
-#define BV_IR_STAT_SPEED_SUMMARY__REQUEST       0x1
-#define BF_IR_STAT_SPEED_SUMMARY(v)             (((v) << 21) & 0x200000)
-#define BF_IR_STAT_SPEED_SUMMARY_V(v)           ((BV_IR_STAT_SPEED_SUMMARY__##v << 21) & 0x200000)
-#define BP_IR_STAT_RXOF_SUMMARY                 20
-#define BM_IR_STAT_RXOF_SUMMARY                 0x100000
-#define BV_IR_STAT_RXOF_SUMMARY__NO_REQUEST     0x0
-#define BV_IR_STAT_RXOF_SUMMARY__REQUEST        0x1
-#define BF_IR_STAT_RXOF_SUMMARY(v)              (((v) << 20) & 0x100000)
-#define BF_IR_STAT_RXOF_SUMMARY_V(v)            ((BV_IR_STAT_RXOF_SUMMARY__##v << 20) & 0x100000)
-#define BP_IR_STAT_TXUF_SUMMARY                 19
-#define BM_IR_STAT_TXUF_SUMMARY                 0x80000
-#define BV_IR_STAT_TXUF_SUMMARY__NO_REQUEST     0x0
-#define BV_IR_STAT_TXUF_SUMMARY__REQUEST        0x1
-#define BF_IR_STAT_TXUF_SUMMARY(v)              (((v) << 19) & 0x80000)
-#define BF_IR_STAT_TXUF_SUMMARY_V(v)            ((BV_IR_STAT_TXUF_SUMMARY__##v << 19) & 0x80000)
-#define BP_IR_STAT_TC_SUMMARY                   18
-#define BM_IR_STAT_TC_SUMMARY                   0x40000
-#define BV_IR_STAT_TC_SUMMARY__NO_REQUEST       0x0
-#define BV_IR_STAT_TC_SUMMARY__REQUEST          0x1
-#define BF_IR_STAT_TC_SUMMARY(v)                (((v) << 18) & 0x40000)
-#define BF_IR_STAT_TC_SUMMARY_V(v)              ((BV_IR_STAT_TC_SUMMARY__##v << 18) & 0x40000)
-#define BP_IR_STAT_RX_SUMMARY                   17
-#define BM_IR_STAT_RX_SUMMARY                   0x20000
-#define BV_IR_STAT_RX_SUMMARY__NO_REQUEST       0x0
-#define BV_IR_STAT_RX_SUMMARY__REQUEST          0x1
-#define BF_IR_STAT_RX_SUMMARY(v)                (((v) << 17) & 0x20000)
-#define BF_IR_STAT_RX_SUMMARY_V(v)              ((BV_IR_STAT_RX_SUMMARY__##v << 17) & 0x20000)
-#define BP_IR_STAT_TX_SUMMARY                   16
-#define BM_IR_STAT_TX_SUMMARY                   0x10000
-#define BV_IR_STAT_TX_SUMMARY__NO_REQUEST       0x0
-#define BV_IR_STAT_TX_SUMMARY__REQUEST          0x1
-#define BF_IR_STAT_TX_SUMMARY(v)                (((v) << 16) & 0x10000)
-#define BF_IR_STAT_TX_SUMMARY_V(v)              ((BV_IR_STAT_TX_SUMMARY__##v << 16) & 0x10000)
-#define BP_IR_STAT_RSVD1                        3
-#define BM_IR_STAT_RSVD1                        0xfff8
-#define BF_IR_STAT_RSVD1(v)                     (((v) << 3) & 0xfff8)
-#define BP_IR_STAT_MEDIA_BUSY                   2
-#define BM_IR_STAT_MEDIA_BUSY                   0x4
-#define BF_IR_STAT_MEDIA_BUSY(v)                (((v) << 2) & 0x4)
-#define BP_IR_STAT_RX_ACTIVE                    1
-#define BM_IR_STAT_RX_ACTIVE                    0x2
-#define BF_IR_STAT_RX_ACTIVE(v)                 (((v) << 1) & 0x2)
-#define BP_IR_STAT_TX_ACTIVE                    0
-#define BM_IR_STAT_TX_ACTIVE                    0x1
-#define BF_IR_STAT_TX_ACTIVE(v)                 (((v) << 0) & 0x1)
-
-/**
- * Register: HW_IR_TCCTRL
- * Address: 0x70
- * SCT: yes
-*/
-#define HW_IR_TCCTRL                (*(volatile unsigned long *)(REGS_IR_BASE + 0x70 + 0x0))
-#define HW_IR_TCCTRL_SET            (*(volatile unsigned long *)(REGS_IR_BASE + 0x70 + 0x4))
-#define HW_IR_TCCTRL_CLR            (*(volatile unsigned long *)(REGS_IR_BASE + 0x70 + 0x8))
-#define HW_IR_TCCTRL_TOG            (*(volatile unsigned long *)(REGS_IR_BASE + 0x70 + 0xc))
-#define BP_IR_TCCTRL_INIT           31
-#define BM_IR_TCCTRL_INIT           0x80000000
-#define BF_IR_TCCTRL_INIT(v)        (((v) << 31) & 0x80000000)
-#define BP_IR_TCCTRL_GO             30
-#define BM_IR_TCCTRL_GO             0x40000000
-#define BF_IR_TCCTRL_GO(v)          (((v) << 30) & 0x40000000)
-#define BP_IR_TCCTRL_BUSY           29
-#define BM_IR_TCCTRL_BUSY           0x20000000
-#define BF_IR_TCCTRL_BUSY(v)        (((v) << 29) & 0x20000000)
-#define BP_IR_TCCTRL_RSVD           25
-#define BM_IR_TCCTRL_RSVD           0x1e000000
-#define BF_IR_TCCTRL_RSVD(v)        (((v) << 25) & 0x1e000000)
-#define BP_IR_TCCTRL_TEMIC          24
-#define BM_IR_TCCTRL_TEMIC          0x1000000
-#define BV_IR_TCCTRL_TEMIC__LOW     0x0
-#define BV_IR_TCCTRL_TEMIC__HIGH    0x1
-#define BF_IR_TCCTRL_TEMIC(v)       (((v) << 24) & 0x1000000)
-#define BF_IR_TCCTRL_TEMIC_V(v)     ((BV_IR_TCCTRL_TEMIC__##v << 24) & 0x1000000)
-#define BP_IR_TCCTRL_EXT_DATA       16
-#define BM_IR_TCCTRL_EXT_DATA       0xff0000
-#define BF_IR_TCCTRL_EXT_DATA(v)    (((v) << 16) & 0xff0000)
-#define BP_IR_TCCTRL_DATA           8
-#define BM_IR_TCCTRL_DATA           0xff00
-#define BF_IR_TCCTRL_DATA(v)        (((v) << 8) & 0xff00)
-#define BP_IR_TCCTRL_ADDR           5
-#define BM_IR_TCCTRL_ADDR           0xe0
-#define BF_IR_TCCTRL_ADDR(v)        (((v) << 5) & 0xe0)
-#define BP_IR_TCCTRL_INDX           1
-#define BM_IR_TCCTRL_INDX           0x1e
-#define BF_IR_TCCTRL_INDX(v)        (((v) << 1) & 0x1e)
-#define BP_IR_TCCTRL_C              0
-#define BM_IR_TCCTRL_C              0x1
-#define BF_IR_TCCTRL_C(v)           (((v) << 0) & 0x1)
-
-/**
- * Register: HW_IR_SI_READ
- * Address: 0x80
- * SCT: no
-*/
-#define HW_IR_SI_READ           (*(volatile unsigned long *)(REGS_IR_BASE + 0x80))
-#define BP_IR_SI_READ_RSVD1     9
-#define BM_IR_SI_READ_RSVD1     0xfffffe00
-#define BF_IR_SI_READ_RSVD1(v)  (((v) << 9) & 0xfffffe00)
-#define BP_IR_SI_READ_ABORT     8
-#define BM_IR_SI_READ_ABORT     0x100
-#define BF_IR_SI_READ_ABORT(v)  (((v) << 8) & 0x100)
-#define BP_IR_SI_READ_DATA      0
-#define BM_IR_SI_READ_DATA      0xff
-#define BF_IR_SI_READ_DATA(v)   (((v) << 0) & 0xff)
-
-/**
- * Register: HW_IR_DEBUG
- * Address: 0x90
- * SCT: no
-*/
-#define HW_IR_DEBUG                 (*(volatile unsigned long *)(REGS_IR_BASE + 0x90))
-#define BP_IR_DEBUG_RSVD1           6
-#define BM_IR_DEBUG_RSVD1           0xffffffc0
-#define BF_IR_DEBUG_RSVD1(v)        (((v) << 6) & 0xffffffc0)
-#define BP_IR_DEBUG_TXDMAKICK       5
-#define BM_IR_DEBUG_TXDMAKICK       0x20
-#define BF_IR_DEBUG_TXDMAKICK(v)    (((v) << 5) & 0x20)
-#define BP_IR_DEBUG_RXDMAKICK       4
-#define BM_IR_DEBUG_RXDMAKICK       0x10
-#define BF_IR_DEBUG_RXDMAKICK(v)    (((v) << 4) & 0x10)
-#define BP_IR_DEBUG_TXDMAEND        3
-#define BM_IR_DEBUG_TXDMAEND        0x8
-#define BF_IR_DEBUG_TXDMAEND(v)     (((v) << 3) & 0x8)
-#define BP_IR_DEBUG_RXDMAEND        2
-#define BM_IR_DEBUG_RXDMAEND        0x4
-#define BF_IR_DEBUG_RXDMAEND(v)     (((v) << 2) & 0x4)
-#define BP_IR_DEBUG_TXDMAREQ        1
-#define BM_IR_DEBUG_TXDMAREQ        0x2
-#define BF_IR_DEBUG_TXDMAREQ(v)     (((v) << 1) & 0x2)
-#define BP_IR_DEBUG_RXDMAREQ        0
-#define BM_IR_DEBUG_RXDMAREQ        0x1
-#define BF_IR_DEBUG_RXDMAREQ(v)     (((v) << 0) & 0x1)
-
-/**
- * Register: HW_IR_VERSION
- * Address: 0xa0
- * SCT: no
-*/
-#define HW_IR_VERSION           (*(volatile unsigned long *)(REGS_IR_BASE + 0xa0))
-#define BP_IR_VERSION_MAJOR     24
-#define BM_IR_VERSION_MAJOR     0xff000000
-#define BF_IR_VERSION_MAJOR(v)  (((v) << 24) & 0xff000000)
-#define BP_IR_VERSION_MINOR     16
-#define BM_IR_VERSION_MINOR     0xff0000
-#define BF_IR_VERSION_MINOR(v)  (((v) << 16) & 0xff0000)
-#define BP_IR_VERSION_STEP      0
-#define BM_IR_VERSION_STEP      0xffff
-#define BF_IR_VERSION_STEP(v)   (((v) << 0) & 0xffff)
-
-#endif /* __HEADERGEN__IMX233__IR__H__ */
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-lcdif.h b/firmware/target/arm/imx233/regs/imx233/regs-lcdif.h
deleted file mode 100644
index eda38c7519..0000000000
--- a/firmware/target/arm/imx233/regs/imx233/regs-lcdif.h
+++ /dev/null
@@ -1,886 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: imx233:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__IMX233__LCDIF__H__
-#define __HEADERGEN__IMX233__LCDIF__H__
-
-#define REGS_LCDIF_BASE (0x80030000)
-
-#define REGS_LCDIF_VERSION "3.2.0"
-
-/**
- * Register: HW_LCDIF_CTRL
- * Address: 0
- * SCT: yes
-*/
-#define HW_LCDIF_CTRL                                                   (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x0 + 0x0))
-#define HW_LCDIF_CTRL_SET                                               (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x0 + 0x4))
-#define HW_LCDIF_CTRL_CLR                                               (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x0 + 0x8))
-#define HW_LCDIF_CTRL_TOG                                               (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x0 + 0xc))
-#define BP_LCDIF_CTRL_SFTRST                                            31
-#define BM_LCDIF_CTRL_SFTRST                                            0x80000000
-#define BF_LCDIF_CTRL_SFTRST(v)                                         (((v) << 31) & 0x80000000)
-#define BP_LCDIF_CTRL_CLKGATE                                           30
-#define BM_LCDIF_CTRL_CLKGATE                                           0x40000000
-#define BF_LCDIF_CTRL_CLKGATE(v)                                        (((v) << 30) & 0x40000000)
-#define BP_LCDIF_CTRL_YCBCR422_INPUT                                    29
-#define BM_LCDIF_CTRL_YCBCR422_INPUT                                    0x20000000
-#define BF_LCDIF_CTRL_YCBCR422_INPUT(v)                                 (((v) << 29) & 0x20000000)
-#define BP_LCDIF_CTRL_RSRVD0                                            28
-#define BM_LCDIF_CTRL_RSRVD0                                            0x10000000
-#define BF_LCDIF_CTRL_RSRVD0(v)                                         (((v) << 28) & 0x10000000)
-#define BP_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE                               27
-#define BM_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE                               0x8000000
-#define BF_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE(v)                            (((v) << 27) & 0x8000000)
-#define BP_LCDIF_CTRL_DATA_SHIFT_DIR                                    26
-#define BM_LCDIF_CTRL_DATA_SHIFT_DIR                                    0x4000000
-#define BV_LCDIF_CTRL_DATA_SHIFT_DIR__TXDATA_SHIFT_LEFT                 0x0
-#define BV_LCDIF_CTRL_DATA_SHIFT_DIR__TXDATA_SHIFT_RIGHT                0x1
-#define BF_LCDIF_CTRL_DATA_SHIFT_DIR(v)                                 (((v) << 26) & 0x4000000)
-#define BF_LCDIF_CTRL_DATA_SHIFT_DIR_V(v)                               ((BV_LCDIF_CTRL_DATA_SHIFT_DIR__##v << 26) & 0x4000000)
-#define BP_LCDIF_CTRL_SHIFT_NUM_BITS                                    21
-#define BM_LCDIF_CTRL_SHIFT_NUM_BITS                                    0x3e00000
-#define BF_LCDIF_CTRL_SHIFT_NUM_BITS(v)                                 (((v) << 21) & 0x3e00000)
-#define BP_LCDIF_CTRL_DVI_MODE                                          20
-#define BM_LCDIF_CTRL_DVI_MODE                                          0x100000
-#define BF_LCDIF_CTRL_DVI_MODE(v)                                       (((v) << 20) & 0x100000)
-#define BP_LCDIF_CTRL_BYPASS_COUNT                                      19
-#define BM_LCDIF_CTRL_BYPASS_COUNT                                      0x80000
-#define BF_LCDIF_CTRL_BYPASS_COUNT(v)                                   (((v) << 19) & 0x80000)
-#define BP_LCDIF_CTRL_VSYNC_MODE                                        18
-#define BM_LCDIF_CTRL_VSYNC_MODE                                        0x40000
-#define BF_LCDIF_CTRL_VSYNC_MODE(v)                                     (((v) << 18) & 0x40000)
-#define BP_LCDIF_CTRL_DOTCLK_MODE                                       17
-#define BM_LCDIF_CTRL_DOTCLK_MODE                                       0x20000
-#define BF_LCDIF_CTRL_DOTCLK_MODE(v)                                    (((v) << 17) & 0x20000)
-#define BP_LCDIF_CTRL_DATA_SELECT                                       16
-#define BM_LCDIF_CTRL_DATA_SELECT                                       0x10000
-#define BV_LCDIF_CTRL_DATA_SELECT__CMD_MODE                             0x0
-#define BV_LCDIF_CTRL_DATA_SELECT__DATA_MODE                            0x1
-#define BF_LCDIF_CTRL_DATA_SELECT(v)                                    (((v) << 16) & 0x10000)
-#define BF_LCDIF_CTRL_DATA_SELECT_V(v)                                  ((BV_LCDIF_CTRL_DATA_SELECT__##v << 16) & 0x10000)
-#define BP_LCDIF_CTRL_INPUT_DATA_SWIZZLE                                14
-#define BM_LCDIF_CTRL_INPUT_DATA_SWIZZLE                                0xc000
-#define BV_LCDIF_CTRL_INPUT_DATA_SWIZZLE__NO_SWAP                       0x0
-#define BV_LCDIF_CTRL_INPUT_DATA_SWIZZLE__LITTLE_ENDIAN                 0x0
-#define BV_LCDIF_CTRL_INPUT_DATA_SWIZZLE__BIG_ENDIAN_SWAP               0x1
-#define BV_LCDIF_CTRL_INPUT_DATA_SWIZZLE__SWAP_ALL_BYTES                0x1
-#define BV_LCDIF_CTRL_INPUT_DATA_SWIZZLE__HWD_SWAP                      0x2
-#define BV_LCDIF_CTRL_INPUT_DATA_SWIZZLE__HWD_BYTE_SWAP                 0x3
-#define BF_LCDIF_CTRL_INPUT_DATA_SWIZZLE(v)                             (((v) << 14) & 0xc000)
-#define BF_LCDIF_CTRL_INPUT_DATA_SWIZZLE_V(v)                           ((BV_LCDIF_CTRL_INPUT_DATA_SWIZZLE__##v << 14) & 0xc000)
-#define BP_LCDIF_CTRL_CSC_DATA_SWIZZLE                                  12
-#define BM_LCDIF_CTRL_CSC_DATA_SWIZZLE                                  0x3000
-#define BV_LCDIF_CTRL_CSC_DATA_SWIZZLE__NO_SWAP                         0x0
-#define BV_LCDIF_CTRL_CSC_DATA_SWIZZLE__LITTLE_ENDIAN                   0x0
-#define BV_LCDIF_CTRL_CSC_DATA_SWIZZLE__BIG_ENDIAN_SWAP                 0x1
-#define BV_LCDIF_CTRL_CSC_DATA_SWIZZLE__SWAP_ALL_BYTES                  0x1
-#define BV_LCDIF_CTRL_CSC_DATA_SWIZZLE__HWD_SWAP                        0x2
-#define BV_LCDIF_CTRL_CSC_DATA_SWIZZLE__HWD_BYTE_SWAP                   0x3
-#define BF_LCDIF_CTRL_CSC_DATA_SWIZZLE(v)                               (((v) << 12) & 0x3000)
-#define BF_LCDIF_CTRL_CSC_DATA_SWIZZLE_V(v)                             ((BV_LCDIF_CTRL_CSC_DATA_SWIZZLE__##v << 12) & 0x3000)
-#define BP_LCDIF_CTRL_LCD_DATABUS_WIDTH                                 10
-#define BM_LCDIF_CTRL_LCD_DATABUS_WIDTH                                 0xc00
-#define BV_LCDIF_CTRL_LCD_DATABUS_WIDTH__16_BIT                         0x0
-#define BV_LCDIF_CTRL_LCD_DATABUS_WIDTH__8_BIT                          0x1
-#define BV_LCDIF_CTRL_LCD_DATABUS_WIDTH__18_BIT                         0x2
-#define BV_LCDIF_CTRL_LCD_DATABUS_WIDTH__24_BIT                         0x3
-#define BF_LCDIF_CTRL_LCD_DATABUS_WIDTH(v)                              (((v) << 10) & 0xc00)
-#define BF_LCDIF_CTRL_LCD_DATABUS_WIDTH_V(v)                            ((BV_LCDIF_CTRL_LCD_DATABUS_WIDTH__##v << 10) & 0xc00)
-#define BP_LCDIF_CTRL_WORD_LENGTH                                       8
-#define BM_LCDIF_CTRL_WORD_LENGTH                                       0x300
-#define BV_LCDIF_CTRL_WORD_LENGTH__16_BIT                               0x0
-#define BV_LCDIF_CTRL_WORD_LENGTH__8_BIT                                0x1
-#define BV_LCDIF_CTRL_WORD_LENGTH__18_BIT                               0x2
-#define BV_LCDIF_CTRL_WORD_LENGTH__24_BIT                               0x3
-#define BF_LCDIF_CTRL_WORD_LENGTH(v)                                    (((v) << 8) & 0x300)
-#define BF_LCDIF_CTRL_WORD_LENGTH_V(v)                                  ((BV_LCDIF_CTRL_WORD_LENGTH__##v << 8) & 0x300)
-#define BP_LCDIF_CTRL_RGB_TO_YCBCR422_CSC                               7
-#define BM_LCDIF_CTRL_RGB_TO_YCBCR422_CSC                               0x80
-#define BF_LCDIF_CTRL_RGB_TO_YCBCR422_CSC(v)                            (((v) << 7) & 0x80)
-#define BP_LCDIF_CTRL_ENABLE_PXP_HANDSHAKE                              6
-#define BM_LCDIF_CTRL_ENABLE_PXP_HANDSHAKE                              0x40
-#define BF_LCDIF_CTRL_ENABLE_PXP_HANDSHAKE(v)                           (((v) << 6) & 0x40)
-#define BP_LCDIF_CTRL_LCDIF_MASTER                                      5
-#define BM_LCDIF_CTRL_LCDIF_MASTER                                      0x20
-#define BF_LCDIF_CTRL_LCDIF_MASTER(v)                                   (((v) << 5) & 0x20)
-#define BP_LCDIF_CTRL_DMA_BURST_LENGTH                                  4
-#define BM_LCDIF_CTRL_DMA_BURST_LENGTH                                  0x10
-#define BF_LCDIF_CTRL_DMA_BURST_LENGTH(v)                               (((v) << 4) & 0x10)
-#define BP_LCDIF_CTRL_DATA_FORMAT_16_BIT                                3
-#define BM_LCDIF_CTRL_DATA_FORMAT_16_BIT                                0x8
-#define BF_LCDIF_CTRL_DATA_FORMAT_16_BIT(v)                             (((v) << 3) & 0x8)
-#define BP_LCDIF_CTRL_DATA_FORMAT_18_BIT                                2
-#define BM_LCDIF_CTRL_DATA_FORMAT_18_BIT                                0x4
-#define BV_LCDIF_CTRL_DATA_FORMAT_18_BIT__LOWER_18_BITS_VALID           0x0
-#define BV_LCDIF_CTRL_DATA_FORMAT_18_BIT__UPPER_18_BITS_VALID           0x1
-#define BF_LCDIF_CTRL_DATA_FORMAT_18_BIT(v)                             (((v) << 2) & 0x4)
-#define BF_LCDIF_CTRL_DATA_FORMAT_18_BIT_V(v)                           ((BV_LCDIF_CTRL_DATA_FORMAT_18_BIT__##v << 2) & 0x4)
-#define BP_LCDIF_CTRL_DATA_FORMAT_24_BIT                                1
-#define BM_LCDIF_CTRL_DATA_FORMAT_24_BIT                                0x2
-#define BV_LCDIF_CTRL_DATA_FORMAT_24_BIT__ALL_24_BITS_VALID             0x0
-#define BV_LCDIF_CTRL_DATA_FORMAT_24_BIT__DROP_UPPER_2_BITS_PER_BYTE    0x1
-#define BF_LCDIF_CTRL_DATA_FORMAT_24_BIT(v)                             (((v) << 1) & 0x2)
-#define BF_LCDIF_CTRL_DATA_FORMAT_24_BIT_V(v)                           ((BV_LCDIF_CTRL_DATA_FORMAT_24_BIT__##v << 1) & 0x2)
-#define BP_LCDIF_CTRL_RUN                                               0
-#define BM_LCDIF_CTRL_RUN                                               0x1
-#define BF_LCDIF_CTRL_RUN(v)                                            (((v) << 0) & 0x1)
-
-/**
- * Register: HW_LCDIF_CTRL1
- * Address: 0x10
- * SCT: yes
-*/
-#define HW_LCDIF_CTRL1                                      (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x10 + 0x0))
-#define HW_LCDIF_CTRL1_SET                                  (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x10 + 0x4))
-#define HW_LCDIF_CTRL1_CLR                                  (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x10 + 0x8))
-#define HW_LCDIF_CTRL1_TOG                                  (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x10 + 0xc))
-#define BP_LCDIF_CTRL1_RSRVD1                               27
-#define BM_LCDIF_CTRL1_RSRVD1                               0xf8000000
-#define BF_LCDIF_CTRL1_RSRVD1(v)                            (((v) << 27) & 0xf8000000)
-#define BP_LCDIF_CTRL1_BM_ERROR_IRQ_EN                      26
-#define BM_LCDIF_CTRL1_BM_ERROR_IRQ_EN                      0x4000000
-#define BF_LCDIF_CTRL1_BM_ERROR_IRQ_EN(v)                   (((v) << 26) & 0x4000000)
-#define BP_LCDIF_CTRL1_BM_ERROR_IRQ                         25
-#define BM_LCDIF_CTRL1_BM_ERROR_IRQ                         0x2000000
-#define BV_LCDIF_CTRL1_BM_ERROR_IRQ__NO_REQUEST             0x0
-#define BV_LCDIF_CTRL1_BM_ERROR_IRQ__REQUEST                0x1
-#define BF_LCDIF_CTRL1_BM_ERROR_IRQ(v)                      (((v) << 25) & 0x2000000)
-#define BF_LCDIF_CTRL1_BM_ERROR_IRQ_V(v)                    ((BV_LCDIF_CTRL1_BM_ERROR_IRQ__##v << 25) & 0x2000000)
-#define BP_LCDIF_CTRL1_RECOVER_ON_UNDERFLOW                 24
-#define BM_LCDIF_CTRL1_RECOVER_ON_UNDERFLOW                 0x1000000
-#define BF_LCDIF_CTRL1_RECOVER_ON_UNDERFLOW(v)              (((v) << 24) & 0x1000000)
-#define BP_LCDIF_CTRL1_INTERLACE_FIELDS                     23
-#define BM_LCDIF_CTRL1_INTERLACE_FIELDS                     0x800000
-#define BF_LCDIF_CTRL1_INTERLACE_FIELDS(v)                  (((v) << 23) & 0x800000)
-#define BP_LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD    22
-#define BM_LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD    0x400000
-#define BF_LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD(v) (((v) << 22) & 0x400000)
-#define BP_LCDIF_CTRL1_FIFO_CLEAR                           21
-#define BM_LCDIF_CTRL1_FIFO_CLEAR                           0x200000
-#define BF_LCDIF_CTRL1_FIFO_CLEAR(v)                        (((v) << 21) & 0x200000)
-#define BP_LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS              20
-#define BM_LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS              0x100000
-#define BF_LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS(v)           (((v) << 20) & 0x100000)
-#define BP_LCDIF_CTRL1_BYTE_PACKING_FORMAT                  16
-#define BM_LCDIF_CTRL1_BYTE_PACKING_FORMAT                  0xf0000
-#define BF_LCDIF_CTRL1_BYTE_PACKING_FORMAT(v)               (((v) << 16) & 0xf0000)
-#define BP_LCDIF_CTRL1_OVERFLOW_IRQ_EN                      15
-#define BM_LCDIF_CTRL1_OVERFLOW_IRQ_EN                      0x8000
-#define BF_LCDIF_CTRL1_OVERFLOW_IRQ_EN(v)                   (((v) << 15) & 0x8000)
-#define BP_LCDIF_CTRL1_UNDERFLOW_IRQ_EN                     14
-#define BM_LCDIF_CTRL1_UNDERFLOW_IRQ_EN                     0x4000
-#define BF_LCDIF_CTRL1_UNDERFLOW_IRQ_EN(v)                  (((v) << 14) & 0x4000)
-#define BP_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN                13
-#define BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN                0x2000
-#define BF_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN(v)             (((v) << 13) & 0x2000)
-#define BP_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN                    12
-#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN                    0x1000
-#define BF_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN(v)                 (((v) << 12) & 0x1000)
-#define BP_LCDIF_CTRL1_OVERFLOW_IRQ                         11
-#define BM_LCDIF_CTRL1_OVERFLOW_IRQ                         0x800
-#define BV_LCDIF_CTRL1_OVERFLOW_IRQ__NO_REQUEST             0x0
-#define BV_LCDIF_CTRL1_OVERFLOW_IRQ__REQUEST                0x1
-#define BF_LCDIF_CTRL1_OVERFLOW_IRQ(v)                      (((v) << 11) & 0x800)
-#define BF_LCDIF_CTRL1_OVERFLOW_IRQ_V(v)                    ((BV_LCDIF_CTRL1_OVERFLOW_IRQ__##v << 11) & 0x800)
-#define BP_LCDIF_CTRL1_UNDERFLOW_IRQ                        10
-#define BM_LCDIF_CTRL1_UNDERFLOW_IRQ                        0x400
-#define BV_LCDIF_CTRL1_UNDERFLOW_IRQ__NO_REQUEST            0x0
-#define BV_LCDIF_CTRL1_UNDERFLOW_IRQ__REQUEST               0x1
-#define BF_LCDIF_CTRL1_UNDERFLOW_IRQ(v)                     (((v) << 10) & 0x400)
-#define BF_LCDIF_CTRL1_UNDERFLOW_IRQ_V(v)                   ((BV_LCDIF_CTRL1_UNDERFLOW_IRQ__##v << 10) & 0x400)
-#define BP_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ                   9
-#define BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ                   0x200
-#define BV_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ__NO_REQUEST       0x0
-#define BV_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ__REQUEST          0x1
-#define BF_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ(v)                (((v) << 9) & 0x200)
-#define BF_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_V(v)              ((BV_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ__##v << 9) & 0x200)
-#define BP_LCDIF_CTRL1_VSYNC_EDGE_IRQ                       8
-#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ                       0x100
-#define BV_LCDIF_CTRL1_VSYNC_EDGE_IRQ__NO_REQUEST           0x0
-#define BV_LCDIF_CTRL1_VSYNC_EDGE_IRQ__REQUEST              0x1
-#define BF_LCDIF_CTRL1_VSYNC_EDGE_IRQ(v)                    (((v) << 8) & 0x100)
-#define BF_LCDIF_CTRL1_VSYNC_EDGE_IRQ_V(v)                  ((BV_LCDIF_CTRL1_VSYNC_EDGE_IRQ__##v << 8) & 0x100)
-#define BP_LCDIF_CTRL1_RSRVD0                               7
-#define BM_LCDIF_CTRL1_RSRVD0                               0x80
-#define BF_LCDIF_CTRL1_RSRVD0(v)                            (((v) << 7) & 0x80)
-#define BP_LCDIF_CTRL1_PAUSE_TRANSFER                       6
-#define BM_LCDIF_CTRL1_PAUSE_TRANSFER                       0x40
-#define BF_LCDIF_CTRL1_PAUSE_TRANSFER(v)                    (((v) << 6) & 0x40)
-#define BP_LCDIF_CTRL1_PAUSE_TRANSFER_IRQ_EN                5
-#define BM_LCDIF_CTRL1_PAUSE_TRANSFER_IRQ_EN                0x20
-#define BF_LCDIF_CTRL1_PAUSE_TRANSFER_IRQ_EN(v)             (((v) << 5) & 0x20)
-#define BP_LCDIF_CTRL1_PAUSE_TRANSFER_IRQ                   4
-#define BM_LCDIF_CTRL1_PAUSE_TRANSFER_IRQ                   0x10
-#define BV_LCDIF_CTRL1_PAUSE_TRANSFER_IRQ__NO_REQUEST       0x0
-#define BV_LCDIF_CTRL1_PAUSE_TRANSFER_IRQ__REQUEST          0x1
-#define BF_LCDIF_CTRL1_PAUSE_TRANSFER_IRQ(v)                (((v) << 4) & 0x10)
-#define BF_LCDIF_CTRL1_PAUSE_TRANSFER_IRQ_V(v)              ((BV_LCDIF_CTRL1_PAUSE_TRANSFER_IRQ__##v << 4) & 0x10)
-#define BP_LCDIF_CTRL1_LCD_CS_CTRL                          3
-#define BM_LCDIF_CTRL1_LCD_CS_CTRL                          0x8
-#define BF_LCDIF_CTRL1_LCD_CS_CTRL(v)                       (((v) << 3) & 0x8)
-#define BP_LCDIF_CTRL1_BUSY_ENABLE                          2
-#define BM_LCDIF_CTRL1_BUSY_ENABLE                          0x4
-#define BV_LCDIF_CTRL1_BUSY_ENABLE__BUSY_DISABLED           0x0
-#define BV_LCDIF_CTRL1_BUSY_ENABLE__BUSY_ENABLED            0x1
-#define BF_LCDIF_CTRL1_BUSY_ENABLE(v)                       (((v) << 2) & 0x4)
-#define BF_LCDIF_CTRL1_BUSY_ENABLE_V(v)                     ((BV_LCDIF_CTRL1_BUSY_ENABLE__##v << 2) & 0x4)
-#define BP_LCDIF_CTRL1_MODE86                               1
-#define BM_LCDIF_CTRL1_MODE86                               0x2
-#define BV_LCDIF_CTRL1_MODE86__8080_MODE                    0x0
-#define BV_LCDIF_CTRL1_MODE86__6800_MODE                    0x1
-#define BF_LCDIF_CTRL1_MODE86(v)                            (((v) << 1) & 0x2)
-#define BF_LCDIF_CTRL1_MODE86_V(v)                          ((BV_LCDIF_CTRL1_MODE86__##v << 1) & 0x2)
-#define BP_LCDIF_CTRL1_RESET                                0
-#define BM_LCDIF_CTRL1_RESET                                0x1
-#define BV_LCDIF_CTRL1_RESET__LCDRESET_LOW                  0x0
-#define BV_LCDIF_CTRL1_RESET__LCDRESET_HIGH                 0x1
-#define BF_LCDIF_CTRL1_RESET(v)                             (((v) << 0) & 0x1)
-#define BF_LCDIF_CTRL1_RESET_V(v)                           ((BV_LCDIF_CTRL1_RESET__##v << 0) & 0x1)
-
-/**
- * Register: HW_LCDIF_TRANSFER_COUNT
- * Address: 0x20
- * SCT: no
-*/
-#define HW_LCDIF_TRANSFER_COUNT             (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x20))
-#define BP_LCDIF_TRANSFER_COUNT_V_COUNT     16
-#define BM_LCDIF_TRANSFER_COUNT_V_COUNT     0xffff0000
-#define BF_LCDIF_TRANSFER_COUNT_V_COUNT(v)  (((v) << 16) & 0xffff0000)
-#define BP_LCDIF_TRANSFER_COUNT_H_COUNT     0
-#define BM_LCDIF_TRANSFER_COUNT_H_COUNT     0xffff
-#define BF_LCDIF_TRANSFER_COUNT_H_COUNT(v)  (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_LCDIF_CUR_BUF
- * Address: 0x30
- * SCT: no
-*/
-#define HW_LCDIF_CUR_BUF            (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x30))
-#define BP_LCDIF_CUR_BUF_ADDR       0
-#define BM_LCDIF_CUR_BUF_ADDR       0xffffffff
-#define BF_LCDIF_CUR_BUF_ADDR(v)    (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_LCDIF_NEXT_BUF
- * Address: 0x40
- * SCT: no
-*/
-#define HW_LCDIF_NEXT_BUF           (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x40))
-#define BP_LCDIF_NEXT_BUF_ADDR      0
-#define BM_LCDIF_NEXT_BUF_ADDR      0xffffffff
-#define BF_LCDIF_NEXT_BUF_ADDR(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_LCDIF_PAGETABLE
- * Address: 0x50
- * SCT: no
-*/
-#define HW_LCDIF_PAGETABLE              (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x50))
-#define BP_LCDIF_PAGETABLE_BASE         14
-#define BM_LCDIF_PAGETABLE_BASE         0xffffc000
-#define BF_LCDIF_PAGETABLE_BASE(v)      (((v) << 14) & 0xffffc000)
-#define BP_LCDIF_PAGETABLE_RSVD1        2
-#define BM_LCDIF_PAGETABLE_RSVD1        0x3ffc
-#define BF_LCDIF_PAGETABLE_RSVD1(v)     (((v) << 2) & 0x3ffc)
-#define BP_LCDIF_PAGETABLE_FLUSH        1
-#define BM_LCDIF_PAGETABLE_FLUSH        0x2
-#define BF_LCDIF_PAGETABLE_FLUSH(v)     (((v) << 1) & 0x2)
-#define BP_LCDIF_PAGETABLE_ENABLE       0
-#define BM_LCDIF_PAGETABLE_ENABLE       0x1
-#define BF_LCDIF_PAGETABLE_ENABLE(v)    (((v) << 0) & 0x1)
-
-/**
- * Register: HW_LCDIF_TIMING
- * Address: 0x60
- * SCT: no
-*/
-#define HW_LCDIF_TIMING                 (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x60))
-#define BP_LCDIF_TIMING_CMD_HOLD        24
-#define BM_LCDIF_TIMING_CMD_HOLD        0xff000000
-#define BF_LCDIF_TIMING_CMD_HOLD(v)     (((v) << 24) & 0xff000000)
-#define BP_LCDIF_TIMING_CMD_SETUP       16
-#define BM_LCDIF_TIMING_CMD_SETUP       0xff0000
-#define BF_LCDIF_TIMING_CMD_SETUP(v)    (((v) << 16) & 0xff0000)
-#define BP_LCDIF_TIMING_DATA_HOLD       8
-#define BM_LCDIF_TIMING_DATA_HOLD       0xff00
-#define BF_LCDIF_TIMING_DATA_HOLD(v)    (((v) << 8) & 0xff00)
-#define BP_LCDIF_TIMING_DATA_SETUP      0
-#define BM_LCDIF_TIMING_DATA_SETUP      0xff
-#define BF_LCDIF_TIMING_DATA_SETUP(v)   (((v) << 0) & 0xff)
-
-/**
- * Register: HW_LCDIF_VDCTRL0
- * Address: 0x70
- * SCT: yes
-*/
-#define HW_LCDIF_VDCTRL0                            (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x70 + 0x0))
-#define HW_LCDIF_VDCTRL0_SET                        (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x70 + 0x4))
-#define HW_LCDIF_VDCTRL0_CLR                        (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x70 + 0x8))
-#define HW_LCDIF_VDCTRL0_TOG                        (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x70 + 0xc))
-#define BP_LCDIF_VDCTRL0_RSRVD2                     30
-#define BM_LCDIF_VDCTRL0_RSRVD2                     0xc0000000
-#define BF_LCDIF_VDCTRL0_RSRVD2(v)                  (((v) << 30) & 0xc0000000)
-#define BP_LCDIF_VDCTRL0_VSYNC_OEB                  29
-#define BM_LCDIF_VDCTRL0_VSYNC_OEB                  0x20000000
-#define BV_LCDIF_VDCTRL0_VSYNC_OEB__VSYNC_OUTPUT    0x0
-#define BV_LCDIF_VDCTRL0_VSYNC_OEB__VSYNC_INPUT     0x1
-#define BF_LCDIF_VDCTRL0_VSYNC_OEB(v)               (((v) << 29) & 0x20000000)
-#define BF_LCDIF_VDCTRL0_VSYNC_OEB_V(v)             ((BV_LCDIF_VDCTRL0_VSYNC_OEB__##v << 29) & 0x20000000)
-#define BP_LCDIF_VDCTRL0_ENABLE_PRESENT             28
-#define BM_LCDIF_VDCTRL0_ENABLE_PRESENT             0x10000000
-#define BF_LCDIF_VDCTRL0_ENABLE_PRESENT(v)          (((v) << 28) & 0x10000000)
-#define BP_LCDIF_VDCTRL0_VSYNC_POL                  27
-#define BM_LCDIF_VDCTRL0_VSYNC_POL                  0x8000000
-#define BF_LCDIF_VDCTRL0_VSYNC_POL(v)               (((v) << 27) & 0x8000000)
-#define BP_LCDIF_VDCTRL0_HSYNC_POL                  26
-#define BM_LCDIF_VDCTRL0_HSYNC_POL                  0x4000000
-#define BF_LCDIF_VDCTRL0_HSYNC_POL(v)               (((v) << 26) & 0x4000000)
-#define BP_LCDIF_VDCTRL0_DOTCLK_POL                 25
-#define BM_LCDIF_VDCTRL0_DOTCLK_POL                 0x2000000
-#define BF_LCDIF_VDCTRL0_DOTCLK_POL(v)              (((v) << 25) & 0x2000000)
-#define BP_LCDIF_VDCTRL0_ENABLE_POL                 24
-#define BM_LCDIF_VDCTRL0_ENABLE_POL                 0x1000000
-#define BF_LCDIF_VDCTRL0_ENABLE_POL(v)              (((v) << 24) & 0x1000000)
-#define BP_LCDIF_VDCTRL0_RSRVD1                     22
-#define BM_LCDIF_VDCTRL0_RSRVD1                     0xc00000
-#define BF_LCDIF_VDCTRL0_RSRVD1(v)                  (((v) << 22) & 0xc00000)
-#define BP_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT          21
-#define BM_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT          0x200000
-#define BF_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT(v)       (((v) << 21) & 0x200000)
-#define BP_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT     20
-#define BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT     0x100000
-#define BF_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT(v)  (((v) << 20) & 0x100000)
-#define BP_LCDIF_VDCTRL0_HALF_LINE                  19
-#define BM_LCDIF_VDCTRL0_HALF_LINE                  0x80000
-#define BF_LCDIF_VDCTRL0_HALF_LINE(v)               (((v) << 19) & 0x80000)
-#define BP_LCDIF_VDCTRL0_HALF_LINE_MODE             18
-#define BM_LCDIF_VDCTRL0_HALF_LINE_MODE             0x40000
-#define BF_LCDIF_VDCTRL0_HALF_LINE_MODE(v)          (((v) << 18) & 0x40000)
-#define BP_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH          0
-#define BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH          0x3ffff
-#define BF_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH(v)       (((v) << 0) & 0x3ffff)
-
-/**
- * Register: HW_LCDIF_VDCTRL1
- * Address: 0x80
- * SCT: no
-*/
-#define HW_LCDIF_VDCTRL1                    (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x80))
-#define BP_LCDIF_VDCTRL1_VSYNC_PERIOD       0
-#define BM_LCDIF_VDCTRL1_VSYNC_PERIOD       0xffffffff
-#define BF_LCDIF_VDCTRL1_VSYNC_PERIOD(v)    (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_LCDIF_VDCTRL2
- * Address: 0x90
- * SCT: no
-*/
-#define HW_LCDIF_VDCTRL2                        (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x90))
-#define BP_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH      24
-#define BM_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH      0xff000000
-#define BF_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(v)   (((v) << 24) & 0xff000000)
-#define BP_LCDIF_VDCTRL2_RSRVD0                 18
-#define BM_LCDIF_VDCTRL2_RSRVD0                 0xfc0000
-#define BF_LCDIF_VDCTRL2_RSRVD0(v)              (((v) << 18) & 0xfc0000)
-#define BP_LCDIF_VDCTRL2_HSYNC_PERIOD           0
-#define BM_LCDIF_VDCTRL2_HSYNC_PERIOD           0x3ffff
-#define BF_LCDIF_VDCTRL2_HSYNC_PERIOD(v)        (((v) << 0) & 0x3ffff)
-
-/**
- * Register: HW_LCDIF_VDCTRL3
- * Address: 0xa0
- * SCT: no
-*/
-#define HW_LCDIF_VDCTRL3                        (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0xa0))
-#define BP_LCDIF_VDCTRL3_RSRVD0                 30
-#define BM_LCDIF_VDCTRL3_RSRVD0                 0xc0000000
-#define BF_LCDIF_VDCTRL3_RSRVD0(v)              (((v) << 30) & 0xc0000000)
-#define BP_LCDIF_VDCTRL3_MUX_SYNC_SIGNALS       29
-#define BM_LCDIF_VDCTRL3_MUX_SYNC_SIGNALS       0x20000000
-#define BF_LCDIF_VDCTRL3_MUX_SYNC_SIGNALS(v)    (((v) << 29) & 0x20000000)
-#define BP_LCDIF_VDCTRL3_VSYNC_ONLY             28
-#define BM_LCDIF_VDCTRL3_VSYNC_ONLY             0x10000000
-#define BF_LCDIF_VDCTRL3_VSYNC_ONLY(v)          (((v) << 28) & 0x10000000)
-#define BP_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT    16
-#define BM_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT    0xfff0000
-#define BF_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(v) (((v) << 16) & 0xfff0000)
-#define BP_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT      0
-#define BM_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT      0xffff
-#define BF_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT(v)   (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_LCDIF_VDCTRL4
- * Address: 0xb0
- * SCT: no
-*/
-#define HW_LCDIF_VDCTRL4                            (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0xb0))
-#define BP_LCDIF_VDCTRL4_RSRVD0                     19
-#define BM_LCDIF_VDCTRL4_RSRVD0                     0xfff80000
-#define BF_LCDIF_VDCTRL4_RSRVD0(v)                  (((v) << 19) & 0xfff80000)
-#define BP_LCDIF_VDCTRL4_SYNC_SIGNALS_ON            18
-#define BM_LCDIF_VDCTRL4_SYNC_SIGNALS_ON            0x40000
-#define BF_LCDIF_VDCTRL4_SYNC_SIGNALS_ON(v)         (((v) << 18) & 0x40000)
-#define BP_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT    0
-#define BM_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT    0x3ffff
-#define BF_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(v) (((v) << 0) & 0x3ffff)
-
-/**
- * Register: HW_LCDIF_DVICTRL0
- * Address: 0xc0
- * SCT: no
-*/
-#define HW_LCDIF_DVICTRL0                   (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0xc0))
-#define BP_LCDIF_DVICTRL0_START_TRS         31
-#define BM_LCDIF_DVICTRL0_START_TRS         0x80000000
-#define BF_LCDIF_DVICTRL0_START_TRS(v)      (((v) << 31) & 0x80000000)
-#define BP_LCDIF_DVICTRL0_H_ACTIVE_CNT      20
-#define BM_LCDIF_DVICTRL0_H_ACTIVE_CNT      0x7ff00000
-#define BF_LCDIF_DVICTRL0_H_ACTIVE_CNT(v)   (((v) << 20) & 0x7ff00000)
-#define BP_LCDIF_DVICTRL0_H_BLANKING_CNT    10
-#define BM_LCDIF_DVICTRL0_H_BLANKING_CNT    0xffc00
-#define BF_LCDIF_DVICTRL0_H_BLANKING_CNT(v) (((v) << 10) & 0xffc00)
-#define BP_LCDIF_DVICTRL0_V_LINES_CNT       0
-#define BM_LCDIF_DVICTRL0_V_LINES_CNT       0x3ff
-#define BF_LCDIF_DVICTRL0_V_LINES_CNT(v)    (((v) << 0) & 0x3ff)
-
-/**
- * Register: HW_LCDIF_DVICTRL1
- * Address: 0xd0
- * SCT: no
-*/
-#define HW_LCDIF_DVICTRL1                   (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0xd0))
-#define BP_LCDIF_DVICTRL1_RSRVD0            30
-#define BM_LCDIF_DVICTRL1_RSRVD0            0xc0000000
-#define BF_LCDIF_DVICTRL1_RSRVD0(v)         (((v) << 30) & 0xc0000000)
-#define BP_LCDIF_DVICTRL1_F1_START_LINE     20
-#define BM_LCDIF_DVICTRL1_F1_START_LINE     0x3ff00000
-#define BF_LCDIF_DVICTRL1_F1_START_LINE(v)  (((v) << 20) & 0x3ff00000)
-#define BP_LCDIF_DVICTRL1_F1_END_LINE       10
-#define BM_LCDIF_DVICTRL1_F1_END_LINE       0xffc00
-#define BF_LCDIF_DVICTRL1_F1_END_LINE(v)    (((v) << 10) & 0xffc00)
-#define BP_LCDIF_DVICTRL1_F2_START_LINE     0
-#define BM_LCDIF_DVICTRL1_F2_START_LINE     0x3ff
-#define BF_LCDIF_DVICTRL1_F2_START_LINE(v)  (((v) << 0) & 0x3ff)
-
-/**
- * Register: HW_LCDIF_DVICTRL2
- * Address: 0xe0
- * SCT: no
-*/
-#define HW_LCDIF_DVICTRL2                           (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0xe0))
-#define BP_LCDIF_DVICTRL2_RSRVD0                    30
-#define BM_LCDIF_DVICTRL2_RSRVD0                    0xc0000000
-#define BF_LCDIF_DVICTRL2_RSRVD0(v)                 (((v) << 30) & 0xc0000000)
-#define BP_LCDIF_DVICTRL2_F2_END_LINE               20
-#define BM_LCDIF_DVICTRL2_F2_END_LINE               0x3ff00000
-#define BF_LCDIF_DVICTRL2_F2_END_LINE(v)            (((v) << 20) & 0x3ff00000)
-#define BP_LCDIF_DVICTRL2_V1_BLANK_START_LINE       10
-#define BM_LCDIF_DVICTRL2_V1_BLANK_START_LINE       0xffc00
-#define BF_LCDIF_DVICTRL2_V1_BLANK_START_LINE(v)    (((v) << 10) & 0xffc00)
-#define BP_LCDIF_DVICTRL2_V1_BLANK_END_LINE         0
-#define BM_LCDIF_DVICTRL2_V1_BLANK_END_LINE         0x3ff
-#define BF_LCDIF_DVICTRL2_V1_BLANK_END_LINE(v)      (((v) << 0) & 0x3ff)
-
-/**
- * Register: HW_LCDIF_DVICTRL3
- * Address: 0xf0
- * SCT: no
-*/
-#define HW_LCDIF_DVICTRL3                           (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0xf0))
-#define BP_LCDIF_DVICTRL3_RSRVD1                    26
-#define BM_LCDIF_DVICTRL3_RSRVD1                    0xfc000000
-#define BF_LCDIF_DVICTRL3_RSRVD1(v)                 (((v) << 26) & 0xfc000000)
-#define BP_LCDIF_DVICTRL3_V2_BLANK_START_LINE       16
-#define BM_LCDIF_DVICTRL3_V2_BLANK_START_LINE       0x3ff0000
-#define BF_LCDIF_DVICTRL3_V2_BLANK_START_LINE(v)    (((v) << 16) & 0x3ff0000)
-#define BP_LCDIF_DVICTRL3_RSRVD0                    10
-#define BM_LCDIF_DVICTRL3_RSRVD0                    0xfc00
-#define BF_LCDIF_DVICTRL3_RSRVD0(v)                 (((v) << 10) & 0xfc00)
-#define BP_LCDIF_DVICTRL3_V2_BLANK_END_LINE         0
-#define BM_LCDIF_DVICTRL3_V2_BLANK_END_LINE         0x3ff
-#define BF_LCDIF_DVICTRL3_V2_BLANK_END_LINE(v)      (((v) << 0) & 0x3ff)
-
-/**
- * Register: HW_LCDIF_DVICTRL4
- * Address: 0x100
- * SCT: no
-*/
-#define HW_LCDIF_DVICTRL4                   (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x100))
-#define BP_LCDIF_DVICTRL4_Y_FILL_VALUE      24
-#define BM_LCDIF_DVICTRL4_Y_FILL_VALUE      0xff000000
-#define BF_LCDIF_DVICTRL4_Y_FILL_VALUE(v)   (((v) << 24) & 0xff000000)
-#define BP_LCDIF_DVICTRL4_CB_FILL_VALUE     16
-#define BM_LCDIF_DVICTRL4_CB_FILL_VALUE     0xff0000
-#define BF_LCDIF_DVICTRL4_CB_FILL_VALUE(v)  (((v) << 16) & 0xff0000)
-#define BP_LCDIF_DVICTRL4_CR_FILL_VALUE     8
-#define BM_LCDIF_DVICTRL4_CR_FILL_VALUE     0xff00
-#define BF_LCDIF_DVICTRL4_CR_FILL_VALUE(v)  (((v) << 8) & 0xff00)
-#define BP_LCDIF_DVICTRL4_H_FILL_CNT        0
-#define BM_LCDIF_DVICTRL4_H_FILL_CNT        0xff
-#define BF_LCDIF_DVICTRL4_H_FILL_CNT(v)     (((v) << 0) & 0xff)
-
-/**
- * Register: HW_LCDIF_CSC_COEFF0
- * Address: 0x110
- * SCT: no
-*/
-#define HW_LCDIF_CSC_COEFF0                                         (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x110))
-#define BP_LCDIF_CSC_COEFF0_RSRVD1                                  26
-#define BM_LCDIF_CSC_COEFF0_RSRVD1                                  0xfc000000
-#define BF_LCDIF_CSC_COEFF0_RSRVD1(v)                               (((v) << 26) & 0xfc000000)
-#define BP_LCDIF_CSC_COEFF0_C0                                      16
-#define BM_LCDIF_CSC_COEFF0_C0                                      0x3ff0000
-#define BF_LCDIF_CSC_COEFF0_C0(v)                                   (((v) << 16) & 0x3ff0000)
-#define BP_LCDIF_CSC_COEFF0_RSRVD0                                  2
-#define BM_LCDIF_CSC_COEFF0_RSRVD0                                  0xfffc
-#define BF_LCDIF_CSC_COEFF0_RSRVD0(v)                               (((v) << 2) & 0xfffc)
-#define BP_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER                    0
-#define BM_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER                    0x3
-#define BV_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER__SAMPLE_AND_HOLD   0x0
-#define BV_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER__RSRVD             0x1
-#define BV_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER__INTERSTITIAL      0x2
-#define BV_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER__COSITED           0x3
-#define BF_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER(v)                 (((v) << 0) & 0x3)
-#define BF_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER_V(v)               ((BV_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER__##v << 0) & 0x3)
-
-/**
- * Register: HW_LCDIF_CSC_COEFF1
- * Address: 0x120
- * SCT: no
-*/
-#define HW_LCDIF_CSC_COEFF1             (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x120))
-#define BP_LCDIF_CSC_COEFF1_RSRVD1      26
-#define BM_LCDIF_CSC_COEFF1_RSRVD1      0xfc000000
-#define BF_LCDIF_CSC_COEFF1_RSRVD1(v)   (((v) << 26) & 0xfc000000)
-#define BP_LCDIF_CSC_COEFF1_C2          16
-#define BM_LCDIF_CSC_COEFF1_C2          0x3ff0000
-#define BF_LCDIF_CSC_COEFF1_C2(v)       (((v) << 16) & 0x3ff0000)
-#define BP_LCDIF_CSC_COEFF1_RSRVD0      10
-#define BM_LCDIF_CSC_COEFF1_RSRVD0      0xfc00
-#define BF_LCDIF_CSC_COEFF1_RSRVD0(v)   (((v) << 10) & 0xfc00)
-#define BP_LCDIF_CSC_COEFF1_C1          0
-#define BM_LCDIF_CSC_COEFF1_C1          0x3ff
-#define BF_LCDIF_CSC_COEFF1_C1(v)       (((v) << 0) & 0x3ff)
-
-/**
- * Register: HW_LCDIF_CSC_COEFF2
- * Address: 0x130
- * SCT: no
-*/
-#define HW_LCDIF_CSC_COEFF2             (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x130))
-#define BP_LCDIF_CSC_COEFF2_RSRVD1      26
-#define BM_LCDIF_CSC_COEFF2_RSRVD1      0xfc000000
-#define BF_LCDIF_CSC_COEFF2_RSRVD1(v)   (((v) << 26) & 0xfc000000)
-#define BP_LCDIF_CSC_COEFF2_C4          16
-#define BM_LCDIF_CSC_COEFF2_C4          0x3ff0000
-#define BF_LCDIF_CSC_COEFF2_C4(v)       (((v) << 16) & 0x3ff0000)
-#define BP_LCDIF_CSC_COEFF2_RSRVD0      10
-#define BM_LCDIF_CSC_COEFF2_RSRVD0      0xfc00
-#define BF_LCDIF_CSC_COEFF2_RSRVD0(v)   (((v) << 10) & 0xfc00)
-#define BP_LCDIF_CSC_COEFF2_C3          0
-#define BM_LCDIF_CSC_COEFF2_C3          0x3ff
-#define BF_LCDIF_CSC_COEFF2_C3(v)       (((v) << 0) & 0x3ff)
-
-/**
- * Register: HW_LCDIF_CSC_COEFF3
- * Address: 0x140
- * SCT: no
-*/
-#define HW_LCDIF_CSC_COEFF3             (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x140))
-#define BP_LCDIF_CSC_COEFF3_RSRVD1      26
-#define BM_LCDIF_CSC_COEFF3_RSRVD1      0xfc000000
-#define BF_LCDIF_CSC_COEFF3_RSRVD1(v)   (((v) << 26) & 0xfc000000)
-#define BP_LCDIF_CSC_COEFF3_C6          16
-#define BM_LCDIF_CSC_COEFF3_C6          0x3ff0000
-#define BF_LCDIF_CSC_COEFF3_C6(v)       (((v) << 16) & 0x3ff0000)
-#define BP_LCDIF_CSC_COEFF3_RSRVD0      10
-#define BM_LCDIF_CSC_COEFF3_RSRVD0      0xfc00
-#define BF_LCDIF_CSC_COEFF3_RSRVD0(v)   (((v) << 10) & 0xfc00)
-#define BP_LCDIF_CSC_COEFF3_C5          0
-#define BM_LCDIF_CSC_COEFF3_C5          0x3ff
-#define BF_LCDIF_CSC_COEFF3_C5(v)       (((v) << 0) & 0x3ff)
-
-/**
- * Register: HW_LCDIF_CSC_COEFF4
- * Address: 0x150
- * SCT: no
-*/
-#define HW_LCDIF_CSC_COEFF4             (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x150))
-#define BP_LCDIF_CSC_COEFF4_RSRVD1      26
-#define BM_LCDIF_CSC_COEFF4_RSRVD1      0xfc000000
-#define BF_LCDIF_CSC_COEFF4_RSRVD1(v)   (((v) << 26) & 0xfc000000)
-#define BP_LCDIF_CSC_COEFF4_C8          16
-#define BM_LCDIF_CSC_COEFF4_C8          0x3ff0000
-#define BF_LCDIF_CSC_COEFF4_C8(v)       (((v) << 16) & 0x3ff0000)
-#define BP_LCDIF_CSC_COEFF4_RSRVD0      10
-#define BM_LCDIF_CSC_COEFF4_RSRVD0      0xfc00
-#define BF_LCDIF_CSC_COEFF4_RSRVD0(v)   (((v) << 10) & 0xfc00)
-#define BP_LCDIF_CSC_COEFF4_C7          0
-#define BM_LCDIF_CSC_COEFF4_C7          0x3ff
-#define BF_LCDIF_CSC_COEFF4_C7(v)       (((v) << 0) & 0x3ff)
-
-/**
- * Register: HW_LCDIF_CSC_OFFSET
- * Address: 0x160
- * SCT: no
-*/
-#define HW_LCDIF_CSC_OFFSET                 (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x160))
-#define BP_LCDIF_CSC_OFFSET_RSRVD1          25
-#define BM_LCDIF_CSC_OFFSET_RSRVD1          0xfe000000
-#define BF_LCDIF_CSC_OFFSET_RSRVD1(v)       (((v) << 25) & 0xfe000000)
-#define BP_LCDIF_CSC_OFFSET_CBCR_OFFSET     16
-#define BM_LCDIF_CSC_OFFSET_CBCR_OFFSET     0x1ff0000
-#define BF_LCDIF_CSC_OFFSET_CBCR_OFFSET(v)  (((v) << 16) & 0x1ff0000)
-#define BP_LCDIF_CSC_OFFSET_RSRVD0          9
-#define BM_LCDIF_CSC_OFFSET_RSRVD0          0xfe00
-#define BF_LCDIF_CSC_OFFSET_RSRVD0(v)       (((v) << 9) & 0xfe00)
-#define BP_LCDIF_CSC_OFFSET_Y_OFFSET        0
-#define BM_LCDIF_CSC_OFFSET_Y_OFFSET        0x1ff
-#define BF_LCDIF_CSC_OFFSET_Y_OFFSET(v)     (((v) << 0) & 0x1ff)
-
-/**
- * Register: HW_LCDIF_CSC_LIMIT
- * Address: 0x170
- * SCT: no
-*/
-#define HW_LCDIF_CSC_LIMIT              (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x170))
-#define BP_LCDIF_CSC_LIMIT_CBCR_MIN     24
-#define BM_LCDIF_CSC_LIMIT_CBCR_MIN     0xff000000
-#define BF_LCDIF_CSC_LIMIT_CBCR_MIN(v)  (((v) << 24) & 0xff000000)
-#define BP_LCDIF_CSC_LIMIT_CBCR_MAX     16
-#define BM_LCDIF_CSC_LIMIT_CBCR_MAX     0xff0000
-#define BF_LCDIF_CSC_LIMIT_CBCR_MAX(v)  (((v) << 16) & 0xff0000)
-#define BP_LCDIF_CSC_LIMIT_Y_MIN        8
-#define BM_LCDIF_CSC_LIMIT_Y_MIN        0xff00
-#define BF_LCDIF_CSC_LIMIT_Y_MIN(v)     (((v) << 8) & 0xff00)
-#define BP_LCDIF_CSC_LIMIT_Y_MAX        0
-#define BM_LCDIF_CSC_LIMIT_Y_MAX        0xff
-#define BF_LCDIF_CSC_LIMIT_Y_MAX(v)     (((v) << 0) & 0xff)
-
-/**
- * Register: HW_LCDIF_PIN_SHARING_CTRL0
- * Address: 0x180
- * SCT: yes
-*/
-#define HW_LCDIF_PIN_SHARING_CTRL0                              (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x180 + 0x0))
-#define HW_LCDIF_PIN_SHARING_CTRL0_SET                          (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x180 + 0x4))
-#define HW_LCDIF_PIN_SHARING_CTRL0_CLR                          (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x180 + 0x8))
-#define HW_LCDIF_PIN_SHARING_CTRL0_TOG                          (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x180 + 0xc))
-#define BP_LCDIF_PIN_SHARING_CTRL0_RSRVD1                       6
-#define BM_LCDIF_PIN_SHARING_CTRL0_RSRVD1                       0xffffffc0
-#define BF_LCDIF_PIN_SHARING_CTRL0_RSRVD1(v)                    (((v) << 6) & 0xffffffc0)
-#define BP_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE                 4
-#define BM_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE                 0x30
-#define BV_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE__NO_OVERRIDE    0x0
-#define BV_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE__RSRVD          0x1
-#define BV_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE__LCDIF_SEL      0x2
-#define BV_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE__GPMI_SEL       0x3
-#define BF_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE(v)              (((v) << 4) & 0x30)
-#define BF_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE_V(v)            ((BV_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE__##v << 4) & 0x30)
-#define BP_LCDIF_PIN_SHARING_CTRL0_RSRVD0                       3
-#define BM_LCDIF_PIN_SHARING_CTRL0_RSRVD0                       0x8
-#define BF_LCDIF_PIN_SHARING_CTRL0_RSRVD0(v)                    (((v) << 3) & 0x8)
-#define BP_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_IRQ_EN           2
-#define BM_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_IRQ_EN           0x4
-#define BF_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_IRQ_EN(v)        (((v) << 2) & 0x4)
-#define BP_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_IRQ              1
-#define BM_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_IRQ              0x2
-#define BV_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_IRQ__NO_REQUEST  0x0
-#define BV_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_IRQ__REQUEST     0x1
-#define BF_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_IRQ(v)           (((v) << 1) & 0x2)
-#define BF_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_IRQ_V(v)         ((BV_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_IRQ__##v << 1) & 0x2)
-#define BP_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_ENABLE           0
-#define BM_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_ENABLE           0x1
-#define BF_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_ENABLE(v)        (((v) << 0) & 0x1)
-
-/**
- * Register: HW_LCDIF_PIN_SHARING_CTRL1
- * Address: 0x190
- * SCT: no
-*/
-#define HW_LCDIF_PIN_SHARING_CTRL1                  (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x190))
-#define BP_LCDIF_PIN_SHARING_CTRL1_THRESHOLD1       0
-#define BM_LCDIF_PIN_SHARING_CTRL1_THRESHOLD1       0xffffffff
-#define BF_LCDIF_PIN_SHARING_CTRL1_THRESHOLD1(v)    (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_LCDIF_PIN_SHARING_CTRL2
- * Address: 0x1a0
- * SCT: no
-*/
-#define HW_LCDIF_PIN_SHARING_CTRL2                  (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x1a0))
-#define BP_LCDIF_PIN_SHARING_CTRL2_THRESHOLD2       0
-#define BM_LCDIF_PIN_SHARING_CTRL2_THRESHOLD2       0xffffffff
-#define BF_LCDIF_PIN_SHARING_CTRL2_THRESHOLD2(v)    (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_LCDIF_DATA
- * Address: 0x1b0
- * SCT: no
-*/
-#define HW_LCDIF_DATA               (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x1b0))
-#define BP_LCDIF_DATA_DATA_THREE    24
-#define BM_LCDIF_DATA_DATA_THREE    0xff000000
-#define BF_LCDIF_DATA_DATA_THREE(v) (((v) << 24) & 0xff000000)
-#define BP_LCDIF_DATA_DATA_TWO      16
-#define BM_LCDIF_DATA_DATA_TWO      0xff0000
-#define BF_LCDIF_DATA_DATA_TWO(v)   (((v) << 16) & 0xff0000)
-#define BP_LCDIF_DATA_DATA_ONE      8
-#define BM_LCDIF_DATA_DATA_ONE      0xff00
-#define BF_LCDIF_DATA_DATA_ONE(v)   (((v) << 8) & 0xff00)
-#define BP_LCDIF_DATA_DATA_ZERO     0
-#define BM_LCDIF_DATA_DATA_ZERO     0xff
-#define BF_LCDIF_DATA_DATA_ZERO(v)  (((v) << 0) & 0xff)
-
-/**
- * Register: HW_LCDIF_BM_ERROR_STAT
- * Address: 0x1c0
- * SCT: no
-*/
-#define HW_LCDIF_BM_ERROR_STAT          (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x1c0))
-#define BP_LCDIF_BM_ERROR_STAT_ADDR     0
-#define BM_LCDIF_BM_ERROR_STAT_ADDR     0xffffffff
-#define BF_LCDIF_BM_ERROR_STAT_ADDR(v)  (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_LCDIF_STAT
- * Address: 0x1d0
- * SCT: no
-*/
-#define HW_LCDIF_STAT                       (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x1d0))
-#define BP_LCDIF_STAT_PRESENT               31
-#define BM_LCDIF_STAT_PRESENT               0x80000000
-#define BF_LCDIF_STAT_PRESENT(v)            (((v) << 31) & 0x80000000)
-#define BP_LCDIF_STAT_DMA_REQ               30
-#define BM_LCDIF_STAT_DMA_REQ               0x40000000
-#define BF_LCDIF_STAT_DMA_REQ(v)            (((v) << 30) & 0x40000000)
-#define BP_LCDIF_STAT_LFIFO_FULL            29
-#define BM_LCDIF_STAT_LFIFO_FULL            0x20000000
-#define BF_LCDIF_STAT_LFIFO_FULL(v)         (((v) << 29) & 0x20000000)
-#define BP_LCDIF_STAT_LFIFO_EMPTY           28
-#define BM_LCDIF_STAT_LFIFO_EMPTY           0x10000000
-#define BF_LCDIF_STAT_LFIFO_EMPTY(v)        (((v) << 28) & 0x10000000)
-#define BP_LCDIF_STAT_TXFIFO_FULL           27
-#define BM_LCDIF_STAT_TXFIFO_FULL           0x8000000
-#define BF_LCDIF_STAT_TXFIFO_FULL(v)        (((v) << 27) & 0x8000000)
-#define BP_LCDIF_STAT_TXFIFO_EMPTY          26
-#define BM_LCDIF_STAT_TXFIFO_EMPTY          0x4000000
-#define BF_LCDIF_STAT_TXFIFO_EMPTY(v)       (((v) << 26) & 0x4000000)
-#define BP_LCDIF_STAT_BUSY                  25
-#define BM_LCDIF_STAT_BUSY                  0x2000000
-#define BF_LCDIF_STAT_BUSY(v)               (((v) << 25) & 0x2000000)
-#define BP_LCDIF_STAT_DVI_CURRENT_FIELD     24
-#define BM_LCDIF_STAT_DVI_CURRENT_FIELD     0x1000000
-#define BF_LCDIF_STAT_DVI_CURRENT_FIELD(v)  (((v) << 24) & 0x1000000)
-#define BP_LCDIF_STAT_RSRVD0                0
-#define BM_LCDIF_STAT_RSRVD0                0xffffff
-#define BF_LCDIF_STAT_RSRVD0(v)             (((v) << 0) & 0xffffff)
-
-/**
- * Register: HW_LCDIF_VERSION
- * Address: 0x1e0
- * SCT: no
-*/
-#define HW_LCDIF_VERSION            (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x1e0))
-#define BP_LCDIF_VERSION_MAJOR      24
-#define BM_LCDIF_VERSION_MAJOR      0xff000000
-#define BF_LCDIF_VERSION_MAJOR(v)   (((v) << 24) & 0xff000000)
-#define BP_LCDIF_VERSION_MINOR      16
-#define BM_LCDIF_VERSION_MINOR      0xff0000
-#define BF_LCDIF_VERSION_MINOR(v)   (((v) << 16) & 0xff0000)
-#define BP_LCDIF_VERSION_STEP       0
-#define BM_LCDIF_VERSION_STEP       0xffff
-#define BF_LCDIF_VERSION_STEP(v)    (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_LCDIF_DEBUG0
- * Address: 0x1f0
- * SCT: no
-*/
-#define HW_LCDIF_DEBUG0                             (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x1f0))
-#define BP_LCDIF_DEBUG0_STREAMING_END_DETECTED      31
-#define BM_LCDIF_DEBUG0_STREAMING_END_DETECTED      0x80000000
-#define BF_LCDIF_DEBUG0_STREAMING_END_DETECTED(v)   (((v) << 31) & 0x80000000)
-#define BP_LCDIF_DEBUG0_WAIT_FOR_VSYNC_EDGE_OUT     30
-#define BM_LCDIF_DEBUG0_WAIT_FOR_VSYNC_EDGE_OUT     0x40000000
-#define BF_LCDIF_DEBUG0_WAIT_FOR_VSYNC_EDGE_OUT(v)  (((v) << 30) & 0x40000000)
-#define BP_LCDIF_DEBUG0_SYNC_SIGNALS_ON_REG         29
-#define BM_LCDIF_DEBUG0_SYNC_SIGNALS_ON_REG         0x20000000
-#define BF_LCDIF_DEBUG0_SYNC_SIGNALS_ON_REG(v)      (((v) << 29) & 0x20000000)
-#define BP_LCDIF_DEBUG0_DMACMDKICK                  28
-#define BM_LCDIF_DEBUG0_DMACMDKICK                  0x10000000
-#define BF_LCDIF_DEBUG0_DMACMDKICK(v)               (((v) << 28) & 0x10000000)
-#define BP_LCDIF_DEBUG0_ENABLE                      27
-#define BM_LCDIF_DEBUG0_ENABLE                      0x8000000
-#define BF_LCDIF_DEBUG0_ENABLE(v)                   (((v) << 27) & 0x8000000)
-#define BP_LCDIF_DEBUG0_HSYNC                       26
-#define BM_LCDIF_DEBUG0_HSYNC                       0x4000000
-#define BF_LCDIF_DEBUG0_HSYNC(v)                    (((v) << 26) & 0x4000000)
-#define BP_LCDIF_DEBUG0_VSYNC                       25
-#define BM_LCDIF_DEBUG0_VSYNC                       0x2000000
-#define BF_LCDIF_DEBUG0_VSYNC(v)                    (((v) << 25) & 0x2000000)
-#define BP_LCDIF_DEBUG0_CUR_FRAME_TX                24
-#define BM_LCDIF_DEBUG0_CUR_FRAME_TX                0x1000000
-#define BF_LCDIF_DEBUG0_CUR_FRAME_TX(v)             (((v) << 24) & 0x1000000)
-#define BP_LCDIF_DEBUG0_EMPTY_WORD                  23
-#define BM_LCDIF_DEBUG0_EMPTY_WORD                  0x800000
-#define BF_LCDIF_DEBUG0_EMPTY_WORD(v)               (((v) << 23) & 0x800000)
-#define BP_LCDIF_DEBUG0_CUR_STATE                   16
-#define BM_LCDIF_DEBUG0_CUR_STATE                   0x7f0000
-#define BF_LCDIF_DEBUG0_CUR_STATE(v)                (((v) << 16) & 0x7f0000)
-#define BP_LCDIF_DEBUG0_PXP_LCDIF_B0_READY          15
-#define BM_LCDIF_DEBUG0_PXP_LCDIF_B0_READY          0x8000
-#define BF_LCDIF_DEBUG0_PXP_LCDIF_B0_READY(v)       (((v) << 15) & 0x8000)
-#define BP_LCDIF_DEBUG0_LCDIF_PXP_B0_DONE           14
-#define BM_LCDIF_DEBUG0_LCDIF_PXP_B0_DONE           0x4000
-#define BF_LCDIF_DEBUG0_LCDIF_PXP_B0_DONE(v)        (((v) << 14) & 0x4000)
-#define BP_LCDIF_DEBUG0_PXP_LCDIF_B1_READY          13
-#define BM_LCDIF_DEBUG0_PXP_LCDIF_B1_READY          0x2000
-#define BF_LCDIF_DEBUG0_PXP_LCDIF_B1_READY(v)       (((v) << 13) & 0x2000)
-#define BP_LCDIF_DEBUG0_LCDIF_PXP_B1_DONE           12
-#define BM_LCDIF_DEBUG0_LCDIF_PXP_B1_DONE           0x1000
-#define BF_LCDIF_DEBUG0_LCDIF_PXP_B1_DONE(v)        (((v) << 12) & 0x1000)
-#define BP_LCDIF_DEBUG0_GPMI_LCDIF_REQ              11
-#define BM_LCDIF_DEBUG0_GPMI_LCDIF_REQ              0x800
-#define BF_LCDIF_DEBUG0_GPMI_LCDIF_REQ(v)           (((v) << 11) & 0x800)
-#define BP_LCDIF_DEBUG0_LCDIF_GPMI_GRANT            10
-#define BM_LCDIF_DEBUG0_LCDIF_GPMI_GRANT            0x400
-#define BF_LCDIF_DEBUG0_LCDIF_GPMI_GRANT(v)         (((v) << 10) & 0x400)
-#define BP_LCDIF_DEBUG0_RSRVD0                      0
-#define BM_LCDIF_DEBUG0_RSRVD0                      0x3ff
-#define BF_LCDIF_DEBUG0_RSRVD0(v)                   (((v) << 0) & 0x3ff)
-
-/**
- * Register: HW_LCDIF_DEBUG1
- * Address: 0x200
- * SCT: no
-*/
-#define HW_LCDIF_DEBUG1                 (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x200))
-#define BP_LCDIF_DEBUG1_H_DATA_COUNT    16
-#define BM_LCDIF_DEBUG1_H_DATA_COUNT    0xffff0000
-#define BF_LCDIF_DEBUG1_H_DATA_COUNT(v) (((v) << 16) & 0xffff0000)
-#define BP_LCDIF_DEBUG1_V_DATA_COUNT    0
-#define BM_LCDIF_DEBUG1_V_DATA_COUNT    0xffff
-#define BF_LCDIF_DEBUG1_V_DATA_COUNT(v) (((v) << 0) & 0xffff)
-
-#endif /* __HEADERGEN__IMX233__LCDIF__H__ */
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-lradc.h b/firmware/target/arm/imx233/regs/imx233/regs-lradc.h
deleted file mode 100644
index 191e18345f..0000000000
--- a/firmware/target/arm/imx233/regs/imx233/regs-lradc.h
+++ /dev/null
@@ -1,783 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: imx233:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__IMX233__LRADC__H__
-#define __HEADERGEN__IMX233__LRADC__H__
-
-#define REGS_LRADC_BASE (0x80050000)
-
-#define REGS_LRADC_VERSION "3.2.0"
-
-/**
- * Register: HW_LRADC_CTRL0
- * Address: 0
- * SCT: yes
-*/
-#define HW_LRADC_CTRL0                          (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x0 + 0x0))
-#define HW_LRADC_CTRL0_SET                      (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x0 + 0x4))
-#define HW_LRADC_CTRL0_CLR                      (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x0 + 0x8))
-#define HW_LRADC_CTRL0_TOG                      (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x0 + 0xc))
-#define BP_LRADC_CTRL0_SFTRST                   31
-#define BM_LRADC_CTRL0_SFTRST                   0x80000000
-#define BF_LRADC_CTRL0_SFTRST(v)                (((v) << 31) & 0x80000000)
-#define BP_LRADC_CTRL0_CLKGATE                  30
-#define BM_LRADC_CTRL0_CLKGATE                  0x40000000
-#define BF_LRADC_CTRL0_CLKGATE(v)               (((v) << 30) & 0x40000000)
-#define BP_LRADC_CTRL0_RSRVD2                   22
-#define BM_LRADC_CTRL0_RSRVD2                   0x3fc00000
-#define BF_LRADC_CTRL0_RSRVD2(v)                (((v) << 22) & 0x3fc00000)
-#define BP_LRADC_CTRL0_ONCHIP_GROUNDREF         21
-#define BM_LRADC_CTRL0_ONCHIP_GROUNDREF         0x200000
-#define BV_LRADC_CTRL0_ONCHIP_GROUNDREF__OFF    0x0
-#define BV_LRADC_CTRL0_ONCHIP_GROUNDREF__ON     0x1
-#define BF_LRADC_CTRL0_ONCHIP_GROUNDREF(v)      (((v) << 21) & 0x200000)
-#define BF_LRADC_CTRL0_ONCHIP_GROUNDREF_V(v)    ((BV_LRADC_CTRL0_ONCHIP_GROUNDREF__##v << 21) & 0x200000)
-#define BP_LRADC_CTRL0_TOUCH_DETECT_ENABLE      20
-#define BM_LRADC_CTRL0_TOUCH_DETECT_ENABLE      0x100000
-#define BV_LRADC_CTRL0_TOUCH_DETECT_ENABLE__OFF 0x0
-#define BV_LRADC_CTRL0_TOUCH_DETECT_ENABLE__ON  0x1
-#define BF_LRADC_CTRL0_TOUCH_DETECT_ENABLE(v)   (((v) << 20) & 0x100000)
-#define BF_LRADC_CTRL0_TOUCH_DETECT_ENABLE_V(v) ((BV_LRADC_CTRL0_TOUCH_DETECT_ENABLE__##v << 20) & 0x100000)
-#define BP_LRADC_CTRL0_YMINUS_ENABLE            19
-#define BM_LRADC_CTRL0_YMINUS_ENABLE            0x80000
-#define BV_LRADC_CTRL0_YMINUS_ENABLE__OFF       0x0
-#define BV_LRADC_CTRL0_YMINUS_ENABLE__ON        0x1
-#define BF_LRADC_CTRL0_YMINUS_ENABLE(v)         (((v) << 19) & 0x80000)
-#define BF_LRADC_CTRL0_YMINUS_ENABLE_V(v)       ((BV_LRADC_CTRL0_YMINUS_ENABLE__##v << 19) & 0x80000)
-#define BP_LRADC_CTRL0_XMINUS_ENABLE            18
-#define BM_LRADC_CTRL0_XMINUS_ENABLE            0x40000
-#define BV_LRADC_CTRL0_XMINUS_ENABLE__OFF       0x0
-#define BV_LRADC_CTRL0_XMINUS_ENABLE__ON        0x1
-#define BF_LRADC_CTRL0_XMINUS_ENABLE(v)         (((v) << 18) & 0x40000)
-#define BF_LRADC_CTRL0_XMINUS_ENABLE_V(v)       ((BV_LRADC_CTRL0_XMINUS_ENABLE__##v << 18) & 0x40000)
-#define BP_LRADC_CTRL0_YPLUS_ENABLE             17
-#define BM_LRADC_CTRL0_YPLUS_ENABLE             0x20000
-#define BV_LRADC_CTRL0_YPLUS_ENABLE__OFF        0x0
-#define BV_LRADC_CTRL0_YPLUS_ENABLE__ON         0x1
-#define BF_LRADC_CTRL0_YPLUS_ENABLE(v)          (((v) << 17) & 0x20000)
-#define BF_LRADC_CTRL0_YPLUS_ENABLE_V(v)        ((BV_LRADC_CTRL0_YPLUS_ENABLE__##v << 17) & 0x20000)
-#define BP_LRADC_CTRL0_XPLUS_ENABLE             16
-#define BM_LRADC_CTRL0_XPLUS_ENABLE             0x10000
-#define BV_LRADC_CTRL0_XPLUS_ENABLE__OFF        0x0
-#define BV_LRADC_CTRL0_XPLUS_ENABLE__ON         0x1
-#define BF_LRADC_CTRL0_XPLUS_ENABLE(v)          (((v) << 16) & 0x10000)
-#define BF_LRADC_CTRL0_XPLUS_ENABLE_V(v)        ((BV_LRADC_CTRL0_XPLUS_ENABLE__##v << 16) & 0x10000)
-#define BP_LRADC_CTRL0_RSRVD1                   8
-#define BM_LRADC_CTRL0_RSRVD1                   0xff00
-#define BF_LRADC_CTRL0_RSRVD1(v)                (((v) << 8) & 0xff00)
-#define BP_LRADC_CTRL0_SCHEDULE                 0
-#define BM_LRADC_CTRL0_SCHEDULE                 0xff
-#define BF_LRADC_CTRL0_SCHEDULE(v)              (((v) << 0) & 0xff)
-
-/**
- * Register: HW_LRADC_CTRL1
- * Address: 0x10
- * SCT: yes
-*/
-#define HW_LRADC_CTRL1                              (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x10 + 0x0))
-#define HW_LRADC_CTRL1_SET                          (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x10 + 0x4))
-#define HW_LRADC_CTRL1_CLR                          (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x10 + 0x8))
-#define HW_LRADC_CTRL1_TOG                          (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x10 + 0xc))
-#define BP_LRADC_CTRL1_RSRVD2                       25
-#define BM_LRADC_CTRL1_RSRVD2                       0xfe000000
-#define BF_LRADC_CTRL1_RSRVD2(v)                    (((v) << 25) & 0xfe000000)
-#define BP_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN          24
-#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN          0x1000000
-#define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN__DISABLE 0x0
-#define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN__ENABLE  0x1
-#define BF_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN(v)       (((v) << 24) & 0x1000000)
-#define BF_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN_V(v)     ((BV_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN__##v << 24) & 0x1000000)
-#define BP_LRADC_CTRL1_LRADC7_IRQ_EN                23
-#define BM_LRADC_CTRL1_LRADC7_IRQ_EN                0x800000
-#define BV_LRADC_CTRL1_LRADC7_IRQ_EN__DISABLE       0x0
-#define BV_LRADC_CTRL1_LRADC7_IRQ_EN__ENABLE        0x1
-#define BF_LRADC_CTRL1_LRADC7_IRQ_EN(v)             (((v) << 23) & 0x800000)
-#define BF_LRADC_CTRL1_LRADC7_IRQ_EN_V(v)           ((BV_LRADC_CTRL1_LRADC7_IRQ_EN__##v << 23) & 0x800000)
-#define BP_LRADC_CTRL1_LRADC6_IRQ_EN                22
-#define BM_LRADC_CTRL1_LRADC6_IRQ_EN                0x400000
-#define BV_LRADC_CTRL1_LRADC6_IRQ_EN__DISABLE       0x0
-#define BV_LRADC_CTRL1_LRADC6_IRQ_EN__ENABLE        0x1
-#define BF_LRADC_CTRL1_LRADC6_IRQ_EN(v)             (((v) << 22) & 0x400000)
-#define BF_LRADC_CTRL1_LRADC6_IRQ_EN_V(v)           ((BV_LRADC_CTRL1_LRADC6_IRQ_EN__##v << 22) & 0x400000)
-#define BP_LRADC_CTRL1_LRADC5_IRQ_EN                21
-#define BM_LRADC_CTRL1_LRADC5_IRQ_EN                0x200000
-#define BV_LRADC_CTRL1_LRADC5_IRQ_EN__DISABLE       0x0
-#define BV_LRADC_CTRL1_LRADC5_IRQ_EN__ENABLE        0x1
-#define BF_LRADC_CTRL1_LRADC5_IRQ_EN(v)             (((v) << 21) & 0x200000)
-#define BF_LRADC_CTRL1_LRADC5_IRQ_EN_V(v)           ((BV_LRADC_CTRL1_LRADC5_IRQ_EN__##v << 21) & 0x200000)
-#define BP_LRADC_CTRL1_LRADC4_IRQ_EN                20
-#define BM_LRADC_CTRL1_LRADC4_IRQ_EN                0x100000
-#define BV_LRADC_CTRL1_LRADC4_IRQ_EN__DISABLE       0x0
-#define BV_LRADC_CTRL1_LRADC4_IRQ_EN__ENABLE        0x1
-#define BF_LRADC_CTRL1_LRADC4_IRQ_EN(v)             (((v) << 20) & 0x100000)
-#define BF_LRADC_CTRL1_LRADC4_IRQ_EN_V(v)           ((BV_LRADC_CTRL1_LRADC4_IRQ_EN__##v << 20) & 0x100000)
-#define BP_LRADC_CTRL1_LRADC3_IRQ_EN                19
-#define BM_LRADC_CTRL1_LRADC3_IRQ_EN                0x80000
-#define BV_LRADC_CTRL1_LRADC3_IRQ_EN__DISABLE       0x0
-#define BV_LRADC_CTRL1_LRADC3_IRQ_EN__ENABLE        0x1
-#define BF_LRADC_CTRL1_LRADC3_IRQ_EN(v)             (((v) << 19) & 0x80000)
-#define BF_LRADC_CTRL1_LRADC3_IRQ_EN_V(v)           ((BV_LRADC_CTRL1_LRADC3_IRQ_EN__##v << 19) & 0x80000)
-#define BP_LRADC_CTRL1_LRADC2_IRQ_EN                18
-#define BM_LRADC_CTRL1_LRADC2_IRQ_EN                0x40000
-#define BV_LRADC_CTRL1_LRADC2_IRQ_EN__DISABLE       0x0
-#define BV_LRADC_CTRL1_LRADC2_IRQ_EN__ENABLE        0x1
-#define BF_LRADC_CTRL1_LRADC2_IRQ_EN(v)             (((v) << 18) & 0x40000)
-#define BF_LRADC_CTRL1_LRADC2_IRQ_EN_V(v)           ((BV_LRADC_CTRL1_LRADC2_IRQ_EN__##v << 18) & 0x40000)
-#define BP_LRADC_CTRL1_LRADC1_IRQ_EN                17
-#define BM_LRADC_CTRL1_LRADC1_IRQ_EN                0x20000
-#define BV_LRADC_CTRL1_LRADC1_IRQ_EN__DISABLE       0x0
-#define BV_LRADC_CTRL1_LRADC1_IRQ_EN__ENABLE        0x1
-#define BF_LRADC_CTRL1_LRADC1_IRQ_EN(v)             (((v) << 17) & 0x20000)
-#define BF_LRADC_CTRL1_LRADC1_IRQ_EN_V(v)           ((BV_LRADC_CTRL1_LRADC1_IRQ_EN__##v << 17) & 0x20000)
-#define BP_LRADC_CTRL1_LRADC0_IRQ_EN                16
-#define BM_LRADC_CTRL1_LRADC0_IRQ_EN                0x10000
-#define BV_LRADC_CTRL1_LRADC0_IRQ_EN__DISABLE       0x0
-#define BV_LRADC_CTRL1_LRADC0_IRQ_EN__ENABLE        0x1
-#define BF_LRADC_CTRL1_LRADC0_IRQ_EN(v)             (((v) << 16) & 0x10000)
-#define BF_LRADC_CTRL1_LRADC0_IRQ_EN_V(v)           ((BV_LRADC_CTRL1_LRADC0_IRQ_EN__##v << 16) & 0x10000)
-#define BP_LRADC_CTRL1_RSRVD1                       9
-#define BM_LRADC_CTRL1_RSRVD1                       0xfe00
-#define BF_LRADC_CTRL1_RSRVD1(v)                    (((v) << 9) & 0xfe00)
-#define BP_LRADC_CTRL1_TOUCH_DETECT_IRQ             8
-#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ             0x100
-#define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ__CLEAR      0x0
-#define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ__PENDING    0x1
-#define BF_LRADC_CTRL1_TOUCH_DETECT_IRQ(v)          (((v) << 8) & 0x100)
-#define BF_LRADC_CTRL1_TOUCH_DETECT_IRQ_V(v)        ((BV_LRADC_CTRL1_TOUCH_DETECT_IRQ__##v << 8) & 0x100)
-#define BP_LRADC_CTRL1_LRADC7_IRQ                   7
-#define BM_LRADC_CTRL1_LRADC7_IRQ                   0x80
-#define BV_LRADC_CTRL1_LRADC7_IRQ__CLEAR            0x0
-#define BV_LRADC_CTRL1_LRADC7_IRQ__PENDING          0x1
-#define BF_LRADC_CTRL1_LRADC7_IRQ(v)                (((v) << 7) & 0x80)
-#define BF_LRADC_CTRL1_LRADC7_IRQ_V(v)              ((BV_LRADC_CTRL1_LRADC7_IRQ__##v << 7) & 0x80)
-#define BP_LRADC_CTRL1_LRADC6_IRQ                   6
-#define BM_LRADC_CTRL1_LRADC6_IRQ                   0x40
-#define BV_LRADC_CTRL1_LRADC6_IRQ__CLEAR            0x0
-#define BV_LRADC_CTRL1_LRADC6_IRQ__PENDING          0x1
-#define BF_LRADC_CTRL1_LRADC6_IRQ(v)                (((v) << 6) & 0x40)
-#define BF_LRADC_CTRL1_LRADC6_IRQ_V(v)              ((BV_LRADC_CTRL1_LRADC6_IRQ__##v << 6) & 0x40)
-#define BP_LRADC_CTRL1_LRADC5_IRQ                   5
-#define BM_LRADC_CTRL1_LRADC5_IRQ                   0x20
-#define BV_LRADC_CTRL1_LRADC5_IRQ__CLEAR            0x0
-#define BV_LRADC_CTRL1_LRADC5_IRQ__PENDING          0x1
-#define BF_LRADC_CTRL1_LRADC5_IRQ(v)                (((v) << 5) & 0x20)
-#define BF_LRADC_CTRL1_LRADC5_IRQ_V(v)              ((BV_LRADC_CTRL1_LRADC5_IRQ__##v << 5) & 0x20)
-#define BP_LRADC_CTRL1_LRADC4_IRQ                   4
-#define BM_LRADC_CTRL1_LRADC4_IRQ                   0x10
-#define BV_LRADC_CTRL1_LRADC4_IRQ__CLEAR            0x0
-#define BV_LRADC_CTRL1_LRADC4_IRQ__PENDING          0x1
-#define BF_LRADC_CTRL1_LRADC4_IRQ(v)                (((v) << 4) & 0x10)
-#define BF_LRADC_CTRL1_LRADC4_IRQ_V(v)              ((BV_LRADC_CTRL1_LRADC4_IRQ__##v << 4) & 0x10)
-#define BP_LRADC_CTRL1_LRADC3_IRQ                   3
-#define BM_LRADC_CTRL1_LRADC3_IRQ                   0x8
-#define BV_LRADC_CTRL1_LRADC3_IRQ__CLEAR            0x0
-#define BV_LRADC_CTRL1_LRADC3_IRQ__PENDING          0x1
-#define BF_LRADC_CTRL1_LRADC3_IRQ(v)                (((v) << 3) & 0x8)
-#define BF_LRADC_CTRL1_LRADC3_IRQ_V(v)              ((BV_LRADC_CTRL1_LRADC3_IRQ__##v << 3) & 0x8)
-#define BP_LRADC_CTRL1_LRADC2_IRQ                   2
-#define BM_LRADC_CTRL1_LRADC2_IRQ                   0x4
-#define BV_LRADC_CTRL1_LRADC2_IRQ__CLEAR            0x0
-#define BV_LRADC_CTRL1_LRADC2_IRQ__PENDING          0x1
-#define BF_LRADC_CTRL1_LRADC2_IRQ(v)                (((v) << 2) & 0x4)
-#define BF_LRADC_CTRL1_LRADC2_IRQ_V(v)              ((BV_LRADC_CTRL1_LRADC2_IRQ__##v << 2) & 0x4)
-#define BP_LRADC_CTRL1_LRADC1_IRQ                   1
-#define BM_LRADC_CTRL1_LRADC1_IRQ                   0x2
-#define BV_LRADC_CTRL1_LRADC1_IRQ__CLEAR            0x0
-#define BV_LRADC_CTRL1_LRADC1_IRQ__PENDING          0x1
-#define BF_LRADC_CTRL1_LRADC1_IRQ(v)                (((v) << 1) & 0x2)
-#define BF_LRADC_CTRL1_LRADC1_IRQ_V(v)              ((BV_LRADC_CTRL1_LRADC1_IRQ__##v << 1) & 0x2)
-#define BP_LRADC_CTRL1_LRADC0_IRQ                   0
-#define BM_LRADC_CTRL1_LRADC0_IRQ                   0x1
-#define BV_LRADC_CTRL1_LRADC0_IRQ__CLEAR            0x0
-#define BV_LRADC_CTRL1_LRADC0_IRQ__PENDING          0x1
-#define BF_LRADC_CTRL1_LRADC0_IRQ(v)                (((v) << 0) & 0x1)
-#define BF_LRADC_CTRL1_LRADC0_IRQ_V(v)              ((BV_LRADC_CTRL1_LRADC0_IRQ__##v << 0) & 0x1)
-
-/**
- * Register: HW_LRADC_CTRL2
- * Address: 0x20
- * SCT: yes
-*/
-#define HW_LRADC_CTRL2                                  (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x20 + 0x0))
-#define HW_LRADC_CTRL2_SET                              (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x20 + 0x4))
-#define HW_LRADC_CTRL2_CLR                              (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x20 + 0x8))
-#define HW_LRADC_CTRL2_TOG                              (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x20 + 0xc))
-#define BP_LRADC_CTRL2_DIVIDE_BY_TWO                    24
-#define BM_LRADC_CTRL2_DIVIDE_BY_TWO                    0xff000000
-#define BF_LRADC_CTRL2_DIVIDE_BY_TWO(v)                 (((v) << 24) & 0xff000000)
-#define BP_LRADC_CTRL2_BL_AMP_BYPASS                    23
-#define BM_LRADC_CTRL2_BL_AMP_BYPASS                    0x800000
-#define BV_LRADC_CTRL2_BL_AMP_BYPASS__DISABLE           0x0
-#define BV_LRADC_CTRL2_BL_AMP_BYPASS__ENABLE            0x1
-#define BF_LRADC_CTRL2_BL_AMP_BYPASS(v)                 (((v) << 23) & 0x800000)
-#define BF_LRADC_CTRL2_BL_AMP_BYPASS_V(v)               ((BV_LRADC_CTRL2_BL_AMP_BYPASS__##v << 23) & 0x800000)
-#define BP_LRADC_CTRL2_BL_ENABLE                        22
-#define BM_LRADC_CTRL2_BL_ENABLE                        0x400000
-#define BF_LRADC_CTRL2_BL_ENABLE(v)                     (((v) << 22) & 0x400000)
-#define BP_LRADC_CTRL2_BL_MUX_SELECT                    21
-#define BM_LRADC_CTRL2_BL_MUX_SELECT                    0x200000
-#define BF_LRADC_CTRL2_BL_MUX_SELECT(v)                 (((v) << 21) & 0x200000)
-#define BP_LRADC_CTRL2_BL_BRIGHTNESS                    16
-#define BM_LRADC_CTRL2_BL_BRIGHTNESS                    0x1f0000
-#define BF_LRADC_CTRL2_BL_BRIGHTNESS(v)                 (((v) << 16) & 0x1f0000)
-#define BP_LRADC_CTRL2_TEMPSENSE_PWD                    15
-#define BM_LRADC_CTRL2_TEMPSENSE_PWD                    0x8000
-#define BV_LRADC_CTRL2_TEMPSENSE_PWD__ENABLE            0x0
-#define BV_LRADC_CTRL2_TEMPSENSE_PWD__DISABLE           0x1
-#define BF_LRADC_CTRL2_TEMPSENSE_PWD(v)                 (((v) << 15) & 0x8000)
-#define BF_LRADC_CTRL2_TEMPSENSE_PWD_V(v)               ((BV_LRADC_CTRL2_TEMPSENSE_PWD__##v << 15) & 0x8000)
-#define BP_LRADC_CTRL2_RSRVD1                           14
-#define BM_LRADC_CTRL2_RSRVD1                           0x4000
-#define BF_LRADC_CTRL2_RSRVD1(v)                        (((v) << 14) & 0x4000)
-#define BP_LRADC_CTRL2_EXT_EN1                          13
-#define BM_LRADC_CTRL2_EXT_EN1                          0x2000
-#define BV_LRADC_CTRL2_EXT_EN1__DISABLE                 0x0
-#define BV_LRADC_CTRL2_EXT_EN1__ENABLE                  0x1
-#define BF_LRADC_CTRL2_EXT_EN1(v)                       (((v) << 13) & 0x2000)
-#define BF_LRADC_CTRL2_EXT_EN1_V(v)                     ((BV_LRADC_CTRL2_EXT_EN1__##v << 13) & 0x2000)
-#define BP_LRADC_CTRL2_EXT_EN0                          12
-#define BM_LRADC_CTRL2_EXT_EN0                          0x1000
-#define BF_LRADC_CTRL2_EXT_EN0(v)                       (((v) << 12) & 0x1000)
-#define BP_LRADC_CTRL2_RSRVD2                           10
-#define BM_LRADC_CTRL2_RSRVD2                           0xc00
-#define BF_LRADC_CTRL2_RSRVD2(v)                        (((v) << 10) & 0xc00)
-#define BP_LRADC_CTRL2_TEMP_SENSOR_IENABLE1             9
-#define BM_LRADC_CTRL2_TEMP_SENSOR_IENABLE1             0x200
-#define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE1__DISABLE    0x0
-#define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE1__ENABLE     0x1
-#define BF_LRADC_CTRL2_TEMP_SENSOR_IENABLE1(v)          (((v) << 9) & 0x200)
-#define BF_LRADC_CTRL2_TEMP_SENSOR_IENABLE1_V(v)        ((BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE1__##v << 9) & 0x200)
-#define BP_LRADC_CTRL2_TEMP_SENSOR_IENABLE0             8
-#define BM_LRADC_CTRL2_TEMP_SENSOR_IENABLE0             0x100
-#define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE0__DISABLE    0x0
-#define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE0__ENABLE     0x1
-#define BF_LRADC_CTRL2_TEMP_SENSOR_IENABLE0(v)          (((v) << 8) & 0x100)
-#define BF_LRADC_CTRL2_TEMP_SENSOR_IENABLE0_V(v)        ((BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE0__##v << 8) & 0x100)
-#define BP_LRADC_CTRL2_TEMP_ISRC1                       4
-#define BM_LRADC_CTRL2_TEMP_ISRC1                       0xf0
-#define BV_LRADC_CTRL2_TEMP_ISRC1__300                  0xf
-#define BV_LRADC_CTRL2_TEMP_ISRC1__280                  0xe
-#define BV_LRADC_CTRL2_TEMP_ISRC1__260                  0xd
-#define BV_LRADC_CTRL2_TEMP_ISRC1__240                  0xc
-#define BV_LRADC_CTRL2_TEMP_ISRC1__220                  0xb
-#define BV_LRADC_CTRL2_TEMP_ISRC1__200                  0xa
-#define BV_LRADC_CTRL2_TEMP_ISRC1__180                  0x9
-#define BV_LRADC_CTRL2_TEMP_ISRC1__160                  0x8
-#define BV_LRADC_CTRL2_TEMP_ISRC1__140                  0x7
-#define BV_LRADC_CTRL2_TEMP_ISRC1__120                  0x6
-#define BV_LRADC_CTRL2_TEMP_ISRC1__100                  0x5
-#define BV_LRADC_CTRL2_TEMP_ISRC1__80                   0x4
-#define BV_LRADC_CTRL2_TEMP_ISRC1__60                   0x3
-#define BV_LRADC_CTRL2_TEMP_ISRC1__40                   0x2
-#define BV_LRADC_CTRL2_TEMP_ISRC1__20                   0x1
-#define BV_LRADC_CTRL2_TEMP_ISRC1__ZERO                 0x0
-#define BF_LRADC_CTRL2_TEMP_ISRC1(v)                    (((v) << 4) & 0xf0)
-#define BF_LRADC_CTRL2_TEMP_ISRC1_V(v)                  ((BV_LRADC_CTRL2_TEMP_ISRC1__##v << 4) & 0xf0)
-#define BP_LRADC_CTRL2_TEMP_ISRC0                       0
-#define BM_LRADC_CTRL2_TEMP_ISRC0                       0xf
-#define BV_LRADC_CTRL2_TEMP_ISRC0__300                  0xf
-#define BV_LRADC_CTRL2_TEMP_ISRC0__280                  0xe
-#define BV_LRADC_CTRL2_TEMP_ISRC0__260                  0xd
-#define BV_LRADC_CTRL2_TEMP_ISRC0__240                  0xc
-#define BV_LRADC_CTRL2_TEMP_ISRC0__220                  0xb
-#define BV_LRADC_CTRL2_TEMP_ISRC0__200                  0xa
-#define BV_LRADC_CTRL2_TEMP_ISRC0__180                  0x9
-#define BV_LRADC_CTRL2_TEMP_ISRC0__160                  0x8
-#define BV_LRADC_CTRL2_TEMP_ISRC0__140                  0x7
-#define BV_LRADC_CTRL2_TEMP_ISRC0__120                  0x6
-#define BV_LRADC_CTRL2_TEMP_ISRC0__100                  0x5
-#define BV_LRADC_CTRL2_TEMP_ISRC0__80                   0x4
-#define BV_LRADC_CTRL2_TEMP_ISRC0__60                   0x3
-#define BV_LRADC_CTRL2_TEMP_ISRC0__40                   0x2
-#define BV_LRADC_CTRL2_TEMP_ISRC0__20                   0x1
-#define BV_LRADC_CTRL2_TEMP_ISRC0__ZERO                 0x0
-#define BF_LRADC_CTRL2_TEMP_ISRC0(v)                    (((v) << 0) & 0xf)
-#define BF_LRADC_CTRL2_TEMP_ISRC0_V(v)                  ((BV_LRADC_CTRL2_TEMP_ISRC0__##v << 0) & 0xf)
-
-/**
- * Register: HW_LRADC_CTRL3
- * Address: 0x30
- * SCT: yes
-*/
-#define HW_LRADC_CTRL3                          (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x30 + 0x0))
-#define HW_LRADC_CTRL3_SET                      (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x30 + 0x4))
-#define HW_LRADC_CTRL3_CLR                      (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x30 + 0x8))
-#define HW_LRADC_CTRL3_TOG                      (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x30 + 0xc))
-#define BP_LRADC_CTRL3_RSRVD5                   26
-#define BM_LRADC_CTRL3_RSRVD5                   0xfc000000
-#define BF_LRADC_CTRL3_RSRVD5(v)                (((v) << 26) & 0xfc000000)
-#define BP_LRADC_CTRL3_DISCARD                  24
-#define BM_LRADC_CTRL3_DISCARD                  0x3000000
-#define BV_LRADC_CTRL3_DISCARD__1_SAMPLE        0x1
-#define BV_LRADC_CTRL3_DISCARD__2_SAMPLES       0x2
-#define BV_LRADC_CTRL3_DISCARD__3_SAMPLES       0x3
-#define BF_LRADC_CTRL3_DISCARD(v)               (((v) << 24) & 0x3000000)
-#define BF_LRADC_CTRL3_DISCARD_V(v)             ((BV_LRADC_CTRL3_DISCARD__##v << 24) & 0x3000000)
-#define BP_LRADC_CTRL3_FORCE_ANALOG_PWUP        23
-#define BM_LRADC_CTRL3_FORCE_ANALOG_PWUP        0x800000
-#define BV_LRADC_CTRL3_FORCE_ANALOG_PWUP__OFF   0x0
-#define BV_LRADC_CTRL3_FORCE_ANALOG_PWUP__ON    0x1
-#define BF_LRADC_CTRL3_FORCE_ANALOG_PWUP(v)     (((v) << 23) & 0x800000)
-#define BF_LRADC_CTRL3_FORCE_ANALOG_PWUP_V(v)   ((BV_LRADC_CTRL3_FORCE_ANALOG_PWUP__##v << 23) & 0x800000)
-#define BP_LRADC_CTRL3_FORCE_ANALOG_PWDN        22
-#define BM_LRADC_CTRL3_FORCE_ANALOG_PWDN        0x400000
-#define BV_LRADC_CTRL3_FORCE_ANALOG_PWDN__ON    0x0
-#define BV_LRADC_CTRL3_FORCE_ANALOG_PWDN__OFF   0x1
-#define BF_LRADC_CTRL3_FORCE_ANALOG_PWDN(v)     (((v) << 22) & 0x400000)
-#define BF_LRADC_CTRL3_FORCE_ANALOG_PWDN_V(v)   ((BV_LRADC_CTRL3_FORCE_ANALOG_PWDN__##v << 22) & 0x400000)
-#define BP_LRADC_CTRL3_RSRVD4                   14
-#define BM_LRADC_CTRL3_RSRVD4                   0x3fc000
-#define BF_LRADC_CTRL3_RSRVD4(v)                (((v) << 14) & 0x3fc000)
-#define BP_LRADC_CTRL3_RSRVD3                   10
-#define BM_LRADC_CTRL3_RSRVD3                   0x3c00
-#define BF_LRADC_CTRL3_RSRVD3(v)                (((v) << 10) & 0x3c00)
-#define BP_LRADC_CTRL3_CYCLE_TIME               8
-#define BM_LRADC_CTRL3_CYCLE_TIME               0x300
-#define BV_LRADC_CTRL3_CYCLE_TIME__6MHZ         0x0
-#define BV_LRADC_CTRL3_CYCLE_TIME__4MHZ         0x1
-#define BV_LRADC_CTRL3_CYCLE_TIME__3MHZ         0x2
-#define BV_LRADC_CTRL3_CYCLE_TIME__2MHZ         0x3
-#define BF_LRADC_CTRL3_CYCLE_TIME(v)            (((v) << 8) & 0x300)
-#define BF_LRADC_CTRL3_CYCLE_TIME_V(v)          ((BV_LRADC_CTRL3_CYCLE_TIME__##v << 8) & 0x300)
-#define BP_LRADC_CTRL3_RSRVD2                   6
-#define BM_LRADC_CTRL3_RSRVD2                   0xc0
-#define BF_LRADC_CTRL3_RSRVD2(v)                (((v) << 6) & 0xc0)
-#define BP_LRADC_CTRL3_HIGH_TIME                4
-#define BM_LRADC_CTRL3_HIGH_TIME                0x30
-#define BV_LRADC_CTRL3_HIGH_TIME__42NS          0x0
-#define BV_LRADC_CTRL3_HIGH_TIME__83NS          0x1
-#define BV_LRADC_CTRL3_HIGH_TIME__125NS         0x2
-#define BV_LRADC_CTRL3_HIGH_TIME__250NS         0x3
-#define BF_LRADC_CTRL3_HIGH_TIME(v)             (((v) << 4) & 0x30)
-#define BF_LRADC_CTRL3_HIGH_TIME_V(v)           ((BV_LRADC_CTRL3_HIGH_TIME__##v << 4) & 0x30)
-#define BP_LRADC_CTRL3_RSRVD1                   2
-#define BM_LRADC_CTRL3_RSRVD1                   0xc
-#define BF_LRADC_CTRL3_RSRVD1(v)                (((v) << 2) & 0xc)
-#define BP_LRADC_CTRL3_DELAY_CLOCK              1
-#define BM_LRADC_CTRL3_DELAY_CLOCK              0x2
-#define BV_LRADC_CTRL3_DELAY_CLOCK__NORMAL      0x0
-#define BV_LRADC_CTRL3_DELAY_CLOCK__DELAYED     0x1
-#define BF_LRADC_CTRL3_DELAY_CLOCK(v)           (((v) << 1) & 0x2)
-#define BF_LRADC_CTRL3_DELAY_CLOCK_V(v)         ((BV_LRADC_CTRL3_DELAY_CLOCK__##v << 1) & 0x2)
-#define BP_LRADC_CTRL3_INVERT_CLOCK             0
-#define BM_LRADC_CTRL3_INVERT_CLOCK             0x1
-#define BV_LRADC_CTRL3_INVERT_CLOCK__NORMAL     0x0
-#define BV_LRADC_CTRL3_INVERT_CLOCK__INVERT     0x1
-#define BF_LRADC_CTRL3_INVERT_CLOCK(v)          (((v) << 0) & 0x1)
-#define BF_LRADC_CTRL3_INVERT_CLOCK_V(v)        ((BV_LRADC_CTRL3_INVERT_CLOCK__##v << 0) & 0x1)
-
-/**
- * Register: HW_LRADC_STATUS
- * Address: 0x40
- * SCT: yes
-*/
-#define HW_LRADC_STATUS                         (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x40 + 0x0))
-#define HW_LRADC_STATUS_SET                     (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x40 + 0x4))
-#define HW_LRADC_STATUS_CLR                     (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x40 + 0x8))
-#define HW_LRADC_STATUS_TOG                     (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x40 + 0xc))
-#define BP_LRADC_STATUS_RSRVD3                  27
-#define BM_LRADC_STATUS_RSRVD3                  0xf8000000
-#define BF_LRADC_STATUS_RSRVD3(v)               (((v) << 27) & 0xf8000000)
-#define BP_LRADC_STATUS_TEMP1_PRESENT           26
-#define BM_LRADC_STATUS_TEMP1_PRESENT           0x4000000
-#define BF_LRADC_STATUS_TEMP1_PRESENT(v)        (((v) << 26) & 0x4000000)
-#define BP_LRADC_STATUS_TEMP0_PRESENT           25
-#define BM_LRADC_STATUS_TEMP0_PRESENT           0x2000000
-#define BF_LRADC_STATUS_TEMP0_PRESENT(v)        (((v) << 25) & 0x2000000)
-#define BP_LRADC_STATUS_TOUCH_PANEL_PRESENT     24
-#define BM_LRADC_STATUS_TOUCH_PANEL_PRESENT     0x1000000
-#define BF_LRADC_STATUS_TOUCH_PANEL_PRESENT(v)  (((v) << 24) & 0x1000000)
-#define BP_LRADC_STATUS_CHANNEL7_PRESENT        23
-#define BM_LRADC_STATUS_CHANNEL7_PRESENT        0x800000
-#define BF_LRADC_STATUS_CHANNEL7_PRESENT(v)     (((v) << 23) & 0x800000)
-#define BP_LRADC_STATUS_CHANNEL6_PRESENT        22
-#define BM_LRADC_STATUS_CHANNEL6_PRESENT        0x400000
-#define BF_LRADC_STATUS_CHANNEL6_PRESENT(v)     (((v) << 22) & 0x400000)
-#define BP_LRADC_STATUS_CHANNEL5_PRESENT        21
-#define BM_LRADC_STATUS_CHANNEL5_PRESENT        0x200000
-#define BF_LRADC_STATUS_CHANNEL5_PRESENT(v)     (((v) << 21) & 0x200000)
-#define BP_LRADC_STATUS_CHANNEL4_PRESENT        20
-#define BM_LRADC_STATUS_CHANNEL4_PRESENT        0x100000
-#define BF_LRADC_STATUS_CHANNEL4_PRESENT(v)     (((v) << 20) & 0x100000)
-#define BP_LRADC_STATUS_CHANNEL3_PRESENT        19
-#define BM_LRADC_STATUS_CHANNEL3_PRESENT        0x80000
-#define BF_LRADC_STATUS_CHANNEL3_PRESENT(v)     (((v) << 19) & 0x80000)
-#define BP_LRADC_STATUS_CHANNEL2_PRESENT        18
-#define BM_LRADC_STATUS_CHANNEL2_PRESENT        0x40000
-#define BF_LRADC_STATUS_CHANNEL2_PRESENT(v)     (((v) << 18) & 0x40000)
-#define BP_LRADC_STATUS_CHANNEL1_PRESENT        17
-#define BM_LRADC_STATUS_CHANNEL1_PRESENT        0x20000
-#define BF_LRADC_STATUS_CHANNEL1_PRESENT(v)     (((v) << 17) & 0x20000)
-#define BP_LRADC_STATUS_CHANNEL0_PRESENT        16
-#define BM_LRADC_STATUS_CHANNEL0_PRESENT        0x10000
-#define BF_LRADC_STATUS_CHANNEL0_PRESENT(v)     (((v) << 16) & 0x10000)
-#define BP_LRADC_STATUS_RSRVD2                  1
-#define BM_LRADC_STATUS_RSRVD2                  0xfffe
-#define BF_LRADC_STATUS_RSRVD2(v)               (((v) << 1) & 0xfffe)
-#define BP_LRADC_STATUS_TOUCH_DETECT_RAW        0
-#define BM_LRADC_STATUS_TOUCH_DETECT_RAW        0x1
-#define BV_LRADC_STATUS_TOUCH_DETECT_RAW__OPEN  0x0
-#define BV_LRADC_STATUS_TOUCH_DETECT_RAW__HIT   0x1
-#define BF_LRADC_STATUS_TOUCH_DETECT_RAW(v)     (((v) << 0) & 0x1)
-#define BF_LRADC_STATUS_TOUCH_DETECT_RAW_V(v)   ((BV_LRADC_STATUS_TOUCH_DETECT_RAW__##v << 0) & 0x1)
-
-/**
- * Register: HW_LRADC_CHn
- * Address: 0x50+n*0x10
- * SCT: yes
-*/
-#define HW_LRADC_CHn(n)             (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x50+(n)*0x10 + 0x0))
-#define HW_LRADC_CHn_SET(n)         (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x50+(n)*0x10 + 0x4))
-#define HW_LRADC_CHn_CLR(n)         (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x50+(n)*0x10 + 0x8))
-#define HW_LRADC_CHn_TOG(n)         (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x50+(n)*0x10 + 0xc))
-#define BP_LRADC_CHn_TOGGLE         31
-#define BM_LRADC_CHn_TOGGLE         0x80000000
-#define BF_LRADC_CHn_TOGGLE(v)      (((v) << 31) & 0x80000000)
-#define BP_LRADC_CHn_RSRVD2         30
-#define BM_LRADC_CHn_RSRVD2         0x40000000
-#define BF_LRADC_CHn_RSRVD2(v)      (((v) << 30) & 0x40000000)
-#define BP_LRADC_CHn_ACCUMULATE     29
-#define BM_LRADC_CHn_ACCUMULATE     0x20000000
-#define BF_LRADC_CHn_ACCUMULATE(v)  (((v) << 29) & 0x20000000)
-#define BP_LRADC_CHn_NUM_SAMPLES    24
-#define BM_LRADC_CHn_NUM_SAMPLES    0x1f000000
-#define BF_LRADC_CHn_NUM_SAMPLES(v) (((v) << 24) & 0x1f000000)
-#define BP_LRADC_CHn_RSRVD1         18
-#define BM_LRADC_CHn_RSRVD1         0xfc0000
-#define BF_LRADC_CHn_RSRVD1(v)      (((v) << 18) & 0xfc0000)
-#define BP_LRADC_CHn_VALUE          0
-#define BM_LRADC_CHn_VALUE          0x3ffff
-#define BF_LRADC_CHn_VALUE(v)       (((v) << 0) & 0x3ffff)
-
-/**
- * Register: HW_LRADC_DELAYn
- * Address: 0xd0+n*0x10
- * SCT: yes
-*/
-#define HW_LRADC_DELAYn(n)                  (*(volatile unsigned long *)(REGS_LRADC_BASE + 0xd0+(n)*0x10 + 0x0))
-#define HW_LRADC_DELAYn_SET(n)              (*(volatile unsigned long *)(REGS_LRADC_BASE + 0xd0+(n)*0x10 + 0x4))
-#define HW_LRADC_DELAYn_CLR(n)              (*(volatile unsigned long *)(REGS_LRADC_BASE + 0xd0+(n)*0x10 + 0x8))
-#define HW_LRADC_DELAYn_TOG(n)              (*(volatile unsigned long *)(REGS_LRADC_BASE + 0xd0+(n)*0x10 + 0xc))
-#define BP_LRADC_DELAYn_TRIGGER_LRADCS      24
-#define BM_LRADC_DELAYn_TRIGGER_LRADCS      0xff000000
-#define BF_LRADC_DELAYn_TRIGGER_LRADCS(v)   (((v) << 24) & 0xff000000)
-#define BP_LRADC_DELAYn_RSRVD2              21
-#define BM_LRADC_DELAYn_RSRVD2              0xe00000
-#define BF_LRADC_DELAYn_RSRVD2(v)           (((v) << 21) & 0xe00000)
-#define BP_LRADC_DELAYn_KICK                20
-#define BM_LRADC_DELAYn_KICK                0x100000
-#define BF_LRADC_DELAYn_KICK(v)             (((v) << 20) & 0x100000)
-#define BP_LRADC_DELAYn_TRIGGER_DELAYS      16
-#define BM_LRADC_DELAYn_TRIGGER_DELAYS      0xf0000
-#define BF_LRADC_DELAYn_TRIGGER_DELAYS(v)   (((v) << 16) & 0xf0000)
-#define BP_LRADC_DELAYn_LOOP_COUNT          11
-#define BM_LRADC_DELAYn_LOOP_COUNT          0xf800
-#define BF_LRADC_DELAYn_LOOP_COUNT(v)       (((v) << 11) & 0xf800)
-#define BP_LRADC_DELAYn_DELAY               0
-#define BM_LRADC_DELAYn_DELAY               0x7ff
-#define BF_LRADC_DELAYn_DELAY(v)            (((v) << 0) & 0x7ff)
-
-/**
- * Register: HW_LRADC_DEBUG0
- * Address: 0x110
- * SCT: yes
-*/
-#define HW_LRADC_DEBUG0             (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x110 + 0x0))
-#define HW_LRADC_DEBUG0_SET         (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x110 + 0x4))
-#define HW_LRADC_DEBUG0_CLR         (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x110 + 0x8))
-#define HW_LRADC_DEBUG0_TOG         (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x110 + 0xc))
-#define BP_LRADC_DEBUG0_READONLY    16
-#define BM_LRADC_DEBUG0_READONLY    0xffff0000
-#define BF_LRADC_DEBUG0_READONLY(v) (((v) << 16) & 0xffff0000)
-#define BP_LRADC_DEBUG0_RSRVD1      12
-#define BM_LRADC_DEBUG0_RSRVD1      0xf000
-#define BF_LRADC_DEBUG0_RSRVD1(v)   (((v) << 12) & 0xf000)
-#define BP_LRADC_DEBUG0_STATE       0
-#define BM_LRADC_DEBUG0_STATE       0xfff
-#define BF_LRADC_DEBUG0_STATE(v)    (((v) << 0) & 0xfff)
-
-/**
- * Register: HW_LRADC_DEBUG1
- * Address: 0x120
- * SCT: yes
-*/
-#define HW_LRADC_DEBUG1                     (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x120 + 0x0))
-#define HW_LRADC_DEBUG1_SET                 (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x120 + 0x4))
-#define HW_LRADC_DEBUG1_CLR                 (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x120 + 0x8))
-#define HW_LRADC_DEBUG1_TOG                 (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x120 + 0xc))
-#define BP_LRADC_DEBUG1_RSRVD3              24
-#define BM_LRADC_DEBUG1_RSRVD3              0xff000000
-#define BF_LRADC_DEBUG1_RSRVD3(v)           (((v) << 24) & 0xff000000)
-#define BP_LRADC_DEBUG1_REQUEST             16
-#define BM_LRADC_DEBUG1_REQUEST             0xff0000
-#define BF_LRADC_DEBUG1_REQUEST(v)          (((v) << 16) & 0xff0000)
-#define BP_LRADC_DEBUG1_RSRVD2              13
-#define BM_LRADC_DEBUG1_RSRVD2              0xe000
-#define BF_LRADC_DEBUG1_RSRVD2(v)           (((v) << 13) & 0xe000)
-#define BP_LRADC_DEBUG1_TESTMODE_COUNT      8
-#define BM_LRADC_DEBUG1_TESTMODE_COUNT      0x1f00
-#define BF_LRADC_DEBUG1_TESTMODE_COUNT(v)   (((v) << 8) & 0x1f00)
-#define BP_LRADC_DEBUG1_RSRVD1              3
-#define BM_LRADC_DEBUG1_RSRVD1              0xf8
-#define BF_LRADC_DEBUG1_RSRVD1(v)           (((v) << 3) & 0xf8)
-#define BP_LRADC_DEBUG1_TESTMODE6           2
-#define BM_LRADC_DEBUG1_TESTMODE6           0x4
-#define BV_LRADC_DEBUG1_TESTMODE6__NORMAL   0x0
-#define BV_LRADC_DEBUG1_TESTMODE6__TEST     0x1
-#define BF_LRADC_DEBUG1_TESTMODE6(v)        (((v) << 2) & 0x4)
-#define BF_LRADC_DEBUG1_TESTMODE6_V(v)      ((BV_LRADC_DEBUG1_TESTMODE6__##v << 2) & 0x4)
-#define BP_LRADC_DEBUG1_TESTMODE5           1
-#define BM_LRADC_DEBUG1_TESTMODE5           0x2
-#define BV_LRADC_DEBUG1_TESTMODE5__NORMAL   0x0
-#define BV_LRADC_DEBUG1_TESTMODE5__TEST     0x1
-#define BF_LRADC_DEBUG1_TESTMODE5(v)        (((v) << 1) & 0x2)
-#define BF_LRADC_DEBUG1_TESTMODE5_V(v)      ((BV_LRADC_DEBUG1_TESTMODE5__##v << 1) & 0x2)
-#define BP_LRADC_DEBUG1_TESTMODE            0
-#define BM_LRADC_DEBUG1_TESTMODE            0x1
-#define BV_LRADC_DEBUG1_TESTMODE__NORMAL    0x0
-#define BV_LRADC_DEBUG1_TESTMODE__TEST      0x1
-#define BF_LRADC_DEBUG1_TESTMODE(v)         (((v) << 0) & 0x1)
-#define BF_LRADC_DEBUG1_TESTMODE_V(v)       ((BV_LRADC_DEBUG1_TESTMODE__##v << 0) & 0x1)
-
-/**
- * Register: HW_LRADC_CONVERSION
- * Address: 0x130
- * SCT: yes
-*/
-#define HW_LRADC_CONVERSION                             (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x130 + 0x0))
-#define HW_LRADC_CONVERSION_SET                         (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x130 + 0x4))
-#define HW_LRADC_CONVERSION_CLR                         (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x130 + 0x8))
-#define HW_LRADC_CONVERSION_TOG                         (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x130 + 0xc))
-#define BP_LRADC_CONVERSION_RSRVD3                      21
-#define BM_LRADC_CONVERSION_RSRVD3                      0xffe00000
-#define BF_LRADC_CONVERSION_RSRVD3(v)                   (((v) << 21) & 0xffe00000)
-#define BP_LRADC_CONVERSION_AUTOMATIC                   20
-#define BM_LRADC_CONVERSION_AUTOMATIC                   0x100000
-#define BV_LRADC_CONVERSION_AUTOMATIC__DISABLE          0x0
-#define BV_LRADC_CONVERSION_AUTOMATIC__ENABLE           0x1
-#define BF_LRADC_CONVERSION_AUTOMATIC(v)                (((v) << 20) & 0x100000)
-#define BF_LRADC_CONVERSION_AUTOMATIC_V(v)              ((BV_LRADC_CONVERSION_AUTOMATIC__##v << 20) & 0x100000)
-#define BP_LRADC_CONVERSION_RSRVD2                      18
-#define BM_LRADC_CONVERSION_RSRVD2                      0xc0000
-#define BF_LRADC_CONVERSION_RSRVD2(v)                   (((v) << 18) & 0xc0000)
-#define BP_LRADC_CONVERSION_SCALE_FACTOR                16
-#define BM_LRADC_CONVERSION_SCALE_FACTOR                0x30000
-#define BV_LRADC_CONVERSION_SCALE_FACTOR__NIMH          0x0
-#define BV_LRADC_CONVERSION_SCALE_FACTOR__DUAL_NIMH     0x1
-#define BV_LRADC_CONVERSION_SCALE_FACTOR__LI_ION        0x2
-#define BV_LRADC_CONVERSION_SCALE_FACTOR__ALT_LI_ION    0x3
-#define BF_LRADC_CONVERSION_SCALE_FACTOR(v)             (((v) << 16) & 0x30000)
-#define BF_LRADC_CONVERSION_SCALE_FACTOR_V(v)           ((BV_LRADC_CONVERSION_SCALE_FACTOR__##v << 16) & 0x30000)
-#define BP_LRADC_CONVERSION_RSRVD1                      10
-#define BM_LRADC_CONVERSION_RSRVD1                      0xfc00
-#define BF_LRADC_CONVERSION_RSRVD1(v)                   (((v) << 10) & 0xfc00)
-#define BP_LRADC_CONVERSION_SCALED_BATT_VOLTAGE         0
-#define BM_LRADC_CONVERSION_SCALED_BATT_VOLTAGE         0x3ff
-#define BF_LRADC_CONVERSION_SCALED_BATT_VOLTAGE(v)      (((v) << 0) & 0x3ff)
-
-/**
- * Register: HW_LRADC_CTRL4
- * Address: 0x140
- * SCT: yes
-*/
-#define HW_LRADC_CTRL4                          (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x140 + 0x0))
-#define HW_LRADC_CTRL4_SET                      (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x140 + 0x4))
-#define HW_LRADC_CTRL4_CLR                      (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x140 + 0x8))
-#define HW_LRADC_CTRL4_TOG                      (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x140 + 0xc))
-#define BP_LRADC_CTRL4_LRADC7SELECT             28
-#define BM_LRADC_CTRL4_LRADC7SELECT             0xf0000000
-#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL0   0x0
-#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL1   0x1
-#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL2   0x2
-#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL3   0x3
-#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL4   0x4
-#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL5   0x5
-#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL6   0x6
-#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL7   0x7
-#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL8   0x8
-#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL9   0x9
-#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL10  0xa
-#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL11  0xb
-#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL12  0xc
-#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL13  0xd
-#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL14  0xe
-#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL15  0xf
-#define BF_LRADC_CTRL4_LRADC7SELECT(v)          (((v) << 28) & 0xf0000000)
-#define BF_LRADC_CTRL4_LRADC7SELECT_V(v)        ((BV_LRADC_CTRL4_LRADC7SELECT__##v << 28) & 0xf0000000)
-#define BP_LRADC_CTRL4_LRADC6SELECT             24
-#define BM_LRADC_CTRL4_LRADC6SELECT             0xf000000
-#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL0   0x0
-#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL1   0x1
-#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL2   0x2
-#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL3   0x3
-#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL4   0x4
-#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL5   0x5
-#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL6   0x6
-#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL7   0x7
-#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL8   0x8
-#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL9   0x9
-#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL10  0xa
-#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL11  0xb
-#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL12  0xc
-#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL13  0xd
-#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL14  0xe
-#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL15  0xf
-#define BF_LRADC_CTRL4_LRADC6SELECT(v)          (((v) << 24) & 0xf000000)
-#define BF_LRADC_CTRL4_LRADC6SELECT_V(v)        ((BV_LRADC_CTRL4_LRADC6SELECT__##v << 24) & 0xf000000)
-#define BP_LRADC_CTRL4_LRADC5SELECT             20
-#define BM_LRADC_CTRL4_LRADC5SELECT             0xf00000
-#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL0   0x0
-#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL1   0x1
-#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL2   0x2
-#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL3   0x3
-#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL4   0x4
-#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL5   0x5
-#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL6   0x6
-#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL7   0x7
-#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL8   0x8
-#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL9   0x9
-#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL10  0xa
-#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL11  0xb
-#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL12  0xc
-#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL13  0xd
-#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL14  0xe
-#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL15  0xf
-#define BF_LRADC_CTRL4_LRADC5SELECT(v)          (((v) << 20) & 0xf00000)
-#define BF_LRADC_CTRL4_LRADC5SELECT_V(v)        ((BV_LRADC_CTRL4_LRADC5SELECT__##v << 20) & 0xf00000)
-#define BP_LRADC_CTRL4_LRADC4SELECT             16
-#define BM_LRADC_CTRL4_LRADC4SELECT             0xf0000
-#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL0   0x0
-#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL1   0x1
-#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL2   0x2
-#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL3   0x3
-#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL4   0x4
-#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL5   0x5
-#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL6   0x6
-#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL7   0x7
-#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL8   0x8
-#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL9   0x9
-#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL10  0xa
-#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL11  0xb
-#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL12  0xc
-#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL13  0xd
-#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL14  0xe
-#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL15  0xf
-#define BF_LRADC_CTRL4_LRADC4SELECT(v)          (((v) << 16) & 0xf0000)
-#define BF_LRADC_CTRL4_LRADC4SELECT_V(v)        ((BV_LRADC_CTRL4_LRADC4SELECT__##v << 16) & 0xf0000)
-#define BP_LRADC_CTRL4_LRADC3SELECT             12
-#define BM_LRADC_CTRL4_LRADC3SELECT             0xf000
-#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL0   0x0
-#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL1   0x1
-#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL2   0x2
-#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL3   0x3
-#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL4   0x4
-#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL5   0x5
-#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL6   0x6
-#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL7   0x7
-#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL8   0x8
-#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL9   0x9
-#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL10  0xa
-#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL11  0xb
-#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL12  0xc
-#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL13  0xd
-#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL14  0xe
-#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL15  0xf
-#define BF_LRADC_CTRL4_LRADC3SELECT(v)          (((v) << 12) & 0xf000)
-#define BF_LRADC_CTRL4_LRADC3SELECT_V(v)        ((BV_LRADC_CTRL4_LRADC3SELECT__##v << 12) & 0xf000)
-#define BP_LRADC_CTRL4_LRADC2SELECT             8
-#define BM_LRADC_CTRL4_LRADC2SELECT             0xf00
-#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL0   0x0
-#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL1   0x1
-#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL2   0x2
-#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL3   0x3
-#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL4   0x4
-#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL5   0x5
-#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL6   0x6
-#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL7   0x7
-#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL8   0x8
-#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL9   0x9
-#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL10  0xa
-#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL11  0xb
-#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL12  0xc
-#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL13  0xd
-#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL14  0xe
-#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL15  0xf
-#define BF_LRADC_CTRL4_LRADC2SELECT(v)          (((v) << 8) & 0xf00)
-#define BF_LRADC_CTRL4_LRADC2SELECT_V(v)        ((BV_LRADC_CTRL4_LRADC2SELECT__##v << 8) & 0xf00)
-#define BP_LRADC_CTRL4_LRADC1SELECT             4
-#define BM_LRADC_CTRL4_LRADC1SELECT             0xf0
-#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL0   0x0
-#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL1   0x1
-#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL2   0x2
-#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL3   0x3
-#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL4   0x4
-#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL5   0x5
-#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL6   0x6
-#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL7   0x7
-#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL8   0x8
-#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL9   0x9
-#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL10  0xa
-#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL11  0xb
-#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL12  0xc
-#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL13  0xd
-#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL14  0xe
-#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL15  0xf
-#define BF_LRADC_CTRL4_LRADC1SELECT(v)          (((v) << 4) & 0xf0)
-#define BF_LRADC_CTRL4_LRADC1SELECT_V(v)        ((BV_LRADC_CTRL4_LRADC1SELECT__##v << 4) & 0xf0)
-#define BP_LRADC_CTRL4_LRADC0SELECT             0
-#define BM_LRADC_CTRL4_LRADC0SELECT             0xf
-#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL0   0x0
-#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL1   0x1
-#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL2   0x2
-#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL3   0x3
-#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL4   0x4
-#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL5   0x5
-#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL6   0x6
-#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL7   0x7
-#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL8   0x8
-#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL9   0x9
-#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL10  0xa
-#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL11  0xb
-#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL12  0xc
-#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL13  0xd
-#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL14  0xe
-#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL15  0xf
-#define BF_LRADC_CTRL4_LRADC0SELECT(v)          (((v) << 0) & 0xf)
-#define BF_LRADC_CTRL4_LRADC0SELECT_V(v)        ((BV_LRADC_CTRL4_LRADC0SELECT__##v << 0) & 0xf)
-
-/**
- * Register: HW_LRADC_VERSION
- * Address: 0x150
- * SCT: no
-*/
-#define HW_LRADC_VERSION            (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x150))
-#define BP_LRADC_VERSION_MAJOR      24
-#define BM_LRADC_VERSION_MAJOR      0xff000000
-#define BF_LRADC_VERSION_MAJOR(v)   (((v) << 24) & 0xff000000)
-#define BP_LRADC_VERSION_MINOR      16
-#define BM_LRADC_VERSION_MINOR      0xff0000
-#define BF_LRADC_VERSION_MINOR(v)   (((v) << 16) & 0xff0000)
-#define BP_LRADC_VERSION_STEP       0
-#define BM_LRADC_VERSION_STEP       0xffff
-#define BF_LRADC_VERSION_STEP(v)    (((v) << 0) & 0xffff)
-
-#endif /* __HEADERGEN__IMX233__LRADC__H__ */
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-ocotp.h b/firmware/target/arm/imx233/regs/imx233/regs-ocotp.h
deleted file mode 100644
index ebda017d78..0000000000
--- a/firmware/target/arm/imx233/regs/imx233/regs-ocotp.h
+++ /dev/null
@@ -1,287 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: imx233:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__IMX233__OCOTP__H__
-#define __HEADERGEN__IMX233__OCOTP__H__
-
-#define REGS_OCOTP_BASE (0x8002c000)
-
-#define REGS_OCOTP_VERSION "3.2.0"
-
-/**
- * Register: HW_OCOTP_CTRL
- * Address: 0
- * SCT: yes
-*/
-#define HW_OCOTP_CTRL                   (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x0 + 0x0))
-#define HW_OCOTP_CTRL_SET               (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x0 + 0x4))
-#define HW_OCOTP_CTRL_CLR               (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x0 + 0x8))
-#define HW_OCOTP_CTRL_TOG               (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x0 + 0xc))
-#define BP_OCOTP_CTRL_WR_UNLOCK         16
-#define BM_OCOTP_CTRL_WR_UNLOCK         0xffff0000
-#define BV_OCOTP_CTRL_WR_UNLOCK__KEY    0x3e77
-#define BF_OCOTP_CTRL_WR_UNLOCK(v)      (((v) << 16) & 0xffff0000)
-#define BF_OCOTP_CTRL_WR_UNLOCK_V(v)    ((BV_OCOTP_CTRL_WR_UNLOCK__##v << 16) & 0xffff0000)
-#define BP_OCOTP_CTRL_RSRVD2            14
-#define BM_OCOTP_CTRL_RSRVD2            0xc000
-#define BF_OCOTP_CTRL_RSRVD2(v)         (((v) << 14) & 0xc000)
-#define BP_OCOTP_CTRL_RELOAD_SHADOWS    13
-#define BM_OCOTP_CTRL_RELOAD_SHADOWS    0x2000
-#define BF_OCOTP_CTRL_RELOAD_SHADOWS(v) (((v) << 13) & 0x2000)
-#define BP_OCOTP_CTRL_RD_BANK_OPEN      12
-#define BM_OCOTP_CTRL_RD_BANK_OPEN      0x1000
-#define BF_OCOTP_CTRL_RD_BANK_OPEN(v)   (((v) << 12) & 0x1000)
-#define BP_OCOTP_CTRL_RSRVD1            10
-#define BM_OCOTP_CTRL_RSRVD1            0xc00
-#define BF_OCOTP_CTRL_RSRVD1(v)         (((v) << 10) & 0xc00)
-#define BP_OCOTP_CTRL_ERROR             9
-#define BM_OCOTP_CTRL_ERROR             0x200
-#define BF_OCOTP_CTRL_ERROR(v)          (((v) << 9) & 0x200)
-#define BP_OCOTP_CTRL_BUSY              8
-#define BM_OCOTP_CTRL_BUSY              0x100
-#define BF_OCOTP_CTRL_BUSY(v)           (((v) << 8) & 0x100)
-#define BP_OCOTP_CTRL_RSRVD0            5
-#define BM_OCOTP_CTRL_RSRVD0            0xe0
-#define BF_OCOTP_CTRL_RSRVD0(v)         (((v) << 5) & 0xe0)
-#define BP_OCOTP_CTRL_ADDR              0
-#define BM_OCOTP_CTRL_ADDR              0x1f
-#define BF_OCOTP_CTRL_ADDR(v)           (((v) << 0) & 0x1f)
-
-/**
- * Register: HW_OCOTP_DATA
- * Address: 0x10
- * SCT: no
-*/
-#define HW_OCOTP_DATA           (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x10))
-#define BP_OCOTP_DATA_DATA      0
-#define BM_OCOTP_DATA_DATA      0xffffffff
-#define BF_OCOTP_DATA_DATA(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_OCOTP_CUSTn
- * Address: 0x20+n*0x10
- * SCT: no
-*/
-#define HW_OCOTP_CUSTn(n)       (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x20+(n)*0x10))
-#define BP_OCOTP_CUSTn_BITS     0
-#define BM_OCOTP_CUSTn_BITS     0xffffffff
-#define BF_OCOTP_CUSTn_BITS(v)  (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_OCOTP_CRYPTOn
- * Address: 0x60+n*0x10
- * SCT: no
-*/
-#define HW_OCOTP_CRYPTOn(n)         (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x60+(n)*0x10))
-#define BP_OCOTP_CRYPTOn_BITS       0
-#define BM_OCOTP_CRYPTOn_BITS       0xffffffff
-#define BF_OCOTP_CRYPTOn_BITS(v)    (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_OCOTP_HWCAPn
- * Address: 0xa0+n*0x10
- * SCT: no
-*/
-#define HW_OCOTP_HWCAPn(n)      (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0xa0+(n)*0x10))
-#define BP_OCOTP_HWCAPn_BITS    0
-#define BM_OCOTP_HWCAPn_BITS    0xffffffff
-#define BF_OCOTP_HWCAPn_BITS(v) (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_OCOTP_SWCAP
- * Address: 0x100
- * SCT: no
-*/
-#define HW_OCOTP_SWCAP          (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x100))
-#define BP_OCOTP_SWCAP_BITS     0
-#define BM_OCOTP_SWCAP_BITS     0xffffffff
-#define BF_OCOTP_SWCAP_BITS(v)  (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_OCOTP_CUSTCAP
- * Address: 0x110
- * SCT: no
-*/
-#define HW_OCOTP_CUSTCAP                            (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x110))
-#define BP_OCOTP_CUSTCAP_CUST_DISABLE_WMADRM9       31
-#define BM_OCOTP_CUSTCAP_CUST_DISABLE_WMADRM9       0x80000000
-#define BF_OCOTP_CUSTCAP_CUST_DISABLE_WMADRM9(v)    (((v) << 31) & 0x80000000)
-#define BP_OCOTP_CUSTCAP_CUST_DISABLE_JANUSDRM10    30
-#define BM_OCOTP_CUSTCAP_CUST_DISABLE_JANUSDRM10    0x40000000
-#define BF_OCOTP_CUSTCAP_CUST_DISABLE_JANUSDRM10(v) (((v) << 30) & 0x40000000)
-#define BP_OCOTP_CUSTCAP_RSRVD1                     5
-#define BM_OCOTP_CUSTCAP_RSRVD1                     0x3fffffe0
-#define BF_OCOTP_CUSTCAP_RSRVD1(v)                  (((v) << 5) & 0x3fffffe0)
-#define BP_OCOTP_CUSTCAP_ENABLE_SJTAG_12MA_DRIVE    4
-#define BM_OCOTP_CUSTCAP_ENABLE_SJTAG_12MA_DRIVE    0x10
-#define BF_OCOTP_CUSTCAP_ENABLE_SJTAG_12MA_DRIVE(v) (((v) << 4) & 0x10)
-#define BP_OCOTP_CUSTCAP_USE_PARALLEL_JTAG          3
-#define BM_OCOTP_CUSTCAP_USE_PARALLEL_JTAG          0x8
-#define BF_OCOTP_CUSTCAP_USE_PARALLEL_JTAG(v)       (((v) << 3) & 0x8)
-#define BP_OCOTP_CUSTCAP_RTC_XTAL_32768_PRESENT     2
-#define BM_OCOTP_CUSTCAP_RTC_XTAL_32768_PRESENT     0x4
-#define BF_OCOTP_CUSTCAP_RTC_XTAL_32768_PRESENT(v)  (((v) << 2) & 0x4)
-#define BP_OCOTP_CUSTCAP_RTC_XTAL_32000_PRESENT     1
-#define BM_OCOTP_CUSTCAP_RTC_XTAL_32000_PRESENT     0x2
-#define BF_OCOTP_CUSTCAP_RTC_XTAL_32000_PRESENT(v)  (((v) << 1) & 0x2)
-#define BP_OCOTP_CUSTCAP_RSRVD0                     0
-#define BM_OCOTP_CUSTCAP_RSRVD0                     0x1
-#define BF_OCOTP_CUSTCAP_RSRVD0(v)                  (((v) << 0) & 0x1)
-
-/**
- * Register: HW_OCOTP_LOCK
- * Address: 0x120
- * SCT: no
-*/
-#define HW_OCOTP_LOCK                       (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x120))
-#define BP_OCOTP_LOCK_ROM7                  31
-#define BM_OCOTP_LOCK_ROM7                  0x80000000
-#define BF_OCOTP_LOCK_ROM7(v)               (((v) << 31) & 0x80000000)
-#define BP_OCOTP_LOCK_ROM6                  30
-#define BM_OCOTP_LOCK_ROM6                  0x40000000
-#define BF_OCOTP_LOCK_ROM6(v)               (((v) << 30) & 0x40000000)
-#define BP_OCOTP_LOCK_ROM5                  29
-#define BM_OCOTP_LOCK_ROM5                  0x20000000
-#define BF_OCOTP_LOCK_ROM5(v)               (((v) << 29) & 0x20000000)
-#define BP_OCOTP_LOCK_ROM4                  28
-#define BM_OCOTP_LOCK_ROM4                  0x10000000
-#define BF_OCOTP_LOCK_ROM4(v)               (((v) << 28) & 0x10000000)
-#define BP_OCOTP_LOCK_ROM3                  27
-#define BM_OCOTP_LOCK_ROM3                  0x8000000
-#define BF_OCOTP_LOCK_ROM3(v)               (((v) << 27) & 0x8000000)
-#define BP_OCOTP_LOCK_ROM2                  26
-#define BM_OCOTP_LOCK_ROM2                  0x4000000
-#define BF_OCOTP_LOCK_ROM2(v)               (((v) << 26) & 0x4000000)
-#define BP_OCOTP_LOCK_ROM1                  25
-#define BM_OCOTP_LOCK_ROM1                  0x2000000
-#define BF_OCOTP_LOCK_ROM1(v)               (((v) << 25) & 0x2000000)
-#define BP_OCOTP_LOCK_ROM0                  24
-#define BM_OCOTP_LOCK_ROM0                  0x1000000
-#define BF_OCOTP_LOCK_ROM0(v)               (((v) << 24) & 0x1000000)
-#define BP_OCOTP_LOCK_HWSW_SHADOW_ALT       23
-#define BM_OCOTP_LOCK_HWSW_SHADOW_ALT       0x800000
-#define BF_OCOTP_LOCK_HWSW_SHADOW_ALT(v)    (((v) << 23) & 0x800000)
-#define BP_OCOTP_LOCK_CRYPTODCP_ALT         22
-#define BM_OCOTP_LOCK_CRYPTODCP_ALT         0x400000
-#define BF_OCOTP_LOCK_CRYPTODCP_ALT(v)      (((v) << 22) & 0x400000)
-#define BP_OCOTP_LOCK_CRYPTOKEY_ALT         21
-#define BM_OCOTP_LOCK_CRYPTOKEY_ALT         0x200000
-#define BF_OCOTP_LOCK_CRYPTOKEY_ALT(v)      (((v) << 21) & 0x200000)
-#define BP_OCOTP_LOCK_PIN                   20
-#define BM_OCOTP_LOCK_PIN                   0x100000
-#define BF_OCOTP_LOCK_PIN(v)                (((v) << 20) & 0x100000)
-#define BP_OCOTP_LOCK_OPS                   19
-#define BM_OCOTP_LOCK_OPS                   0x80000
-#define BF_OCOTP_LOCK_OPS(v)                (((v) << 19) & 0x80000)
-#define BP_OCOTP_LOCK_UN2                   18
-#define BM_OCOTP_LOCK_UN2                   0x40000
-#define BF_OCOTP_LOCK_UN2(v)                (((v) << 18) & 0x40000)
-#define BP_OCOTP_LOCK_UN1                   17
-#define BM_OCOTP_LOCK_UN1                   0x20000
-#define BF_OCOTP_LOCK_UN1(v)                (((v) << 17) & 0x20000)
-#define BP_OCOTP_LOCK_UN0                   16
-#define BM_OCOTP_LOCK_UN0                   0x10000
-#define BF_OCOTP_LOCK_UN0(v)                (((v) << 16) & 0x10000)
-#define BP_OCOTP_LOCK_UNALLOCATED           11
-#define BM_OCOTP_LOCK_UNALLOCATED           0xf800
-#define BF_OCOTP_LOCK_UNALLOCATED(v)        (((v) << 11) & 0xf800)
-#define BP_OCOTP_LOCK_ROM_SHADOW            10
-#define BM_OCOTP_LOCK_ROM_SHADOW            0x400
-#define BF_OCOTP_LOCK_ROM_SHADOW(v)         (((v) << 10) & 0x400)
-#define BP_OCOTP_LOCK_CUSTCAP               9
-#define BM_OCOTP_LOCK_CUSTCAP               0x200
-#define BF_OCOTP_LOCK_CUSTCAP(v)            (((v) << 9) & 0x200)
-#define BP_OCOTP_LOCK_HWSW                  8
-#define BM_OCOTP_LOCK_HWSW                  0x100
-#define BF_OCOTP_LOCK_HWSW(v)               (((v) << 8) & 0x100)
-#define BP_OCOTP_LOCK_CUSTCAP_SHADOW        7
-#define BM_OCOTP_LOCK_CUSTCAP_SHADOW        0x80
-#define BF_OCOTP_LOCK_CUSTCAP_SHADOW(v)     (((v) << 7) & 0x80)
-#define BP_OCOTP_LOCK_HWSW_SHADOW           6
-#define BM_OCOTP_LOCK_HWSW_SHADOW           0x40
-#define BF_OCOTP_LOCK_HWSW_SHADOW(v)        (((v) << 6) & 0x40)
-#define BP_OCOTP_LOCK_CRYPTODCP             5
-#define BM_OCOTP_LOCK_CRYPTODCP             0x20
-#define BF_OCOTP_LOCK_CRYPTODCP(v)          (((v) << 5) & 0x20)
-#define BP_OCOTP_LOCK_CRYPTOKEY             4
-#define BM_OCOTP_LOCK_CRYPTOKEY             0x10
-#define BF_OCOTP_LOCK_CRYPTOKEY(v)          (((v) << 4) & 0x10)
-#define BP_OCOTP_LOCK_CUST3                 3
-#define BM_OCOTP_LOCK_CUST3                 0x8
-#define BF_OCOTP_LOCK_CUST3(v)              (((v) << 3) & 0x8)
-#define BP_OCOTP_LOCK_CUST2                 2
-#define BM_OCOTP_LOCK_CUST2                 0x4
-#define BF_OCOTP_LOCK_CUST2(v)              (((v) << 2) & 0x4)
-#define BP_OCOTP_LOCK_CUST1                 1
-#define BM_OCOTP_LOCK_CUST1                 0x2
-#define BF_OCOTP_LOCK_CUST1(v)              (((v) << 1) & 0x2)
-#define BP_OCOTP_LOCK_CUST0                 0
-#define BM_OCOTP_LOCK_CUST0                 0x1
-#define BF_OCOTP_LOCK_CUST0(v)              (((v) << 0) & 0x1)
-
-/**
- * Register: HW_OCOTP_OPSn
- * Address: 0x130+n*0x10
- * SCT: no
-*/
-#define HW_OCOTP_OPSn(n)        (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x130+(n)*0x10))
-#define BP_OCOTP_OPSn_BITS      0
-#define BM_OCOTP_OPSn_BITS      0xffffffff
-#define BF_OCOTP_OPSn_BITS(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_OCOTP_UNn
- * Address: 0x170+n*0x10
- * SCT: no
-*/
-#define HW_OCOTP_UNn(n)         (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x170+(n)*0x10))
-#define BP_OCOTP_UNn_BITS       0
-#define BM_OCOTP_UNn_BITS       0xffffffff
-#define BF_OCOTP_UNn_BITS(v)    (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_OCOTP_ROMn
- * Address: 0x1a0+n*0x10
- * SCT: no
-*/
-#define HW_OCOTP_ROMn(n)        (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x1a0+(n)*0x10))
-#define BP_OCOTP_ROMn_BITS      0
-#define BM_OCOTP_ROMn_BITS      0xffffffff
-#define BF_OCOTP_ROMn_BITS(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_OCOTP_VERSION
- * Address: 0x220
- * SCT: no
-*/
-#define HW_OCOTP_VERSION            (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x220))
-#define BP_OCOTP_VERSION_MAJOR      24
-#define BM_OCOTP_VERSION_MAJOR      0xff000000
-#define BF_OCOTP_VERSION_MAJOR(v)   (((v) << 24) & 0xff000000)
-#define BP_OCOTP_VERSION_MINOR      16
-#define BM_OCOTP_VERSION_MINOR      0xff0000
-#define BF_OCOTP_VERSION_MINOR(v)   (((v) << 16) & 0xff0000)
-#define BP_OCOTP_VERSION_STEP       0
-#define BM_OCOTP_VERSION_STEP       0xffff
-#define BF_OCOTP_VERSION_STEP(v)    (((v) << 0) & 0xffff)
-
-#endif /* __HEADERGEN__IMX233__OCOTP__H__ */
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-pinctrl.h b/firmware/target/arm/imx233/regs/imx233/regs-pinctrl.h
deleted file mode 100644
index d9a3f17d77..0000000000
--- a/firmware/target/arm/imx233/regs/imx233/regs-pinctrl.h
+++ /dev/null
@@ -1,216 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: imx233:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__IMX233__PINCTRL__H__
-#define __HEADERGEN__IMX233__PINCTRL__H__
-
-#define REGS_PINCTRL_BASE (0x80018000)
-
-#define REGS_PINCTRL_VERSION "3.2.0"
-
-/**
- * Register: HW_PINCTRL_CTRL
- * Address: 0
- * SCT: yes
-*/
-#define HW_PINCTRL_CTRL             (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x0 + 0x0))
-#define HW_PINCTRL_CTRL_SET         (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x0 + 0x4))
-#define HW_PINCTRL_CTRL_CLR         (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x0 + 0x8))
-#define HW_PINCTRL_CTRL_TOG         (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x0 + 0xc))
-#define BP_PINCTRL_CTRL_SFTRST      31
-#define BM_PINCTRL_CTRL_SFTRST      0x80000000
-#define BF_PINCTRL_CTRL_SFTRST(v)   (((v) << 31) & 0x80000000)
-#define BP_PINCTRL_CTRL_CLKGATE     30
-#define BM_PINCTRL_CTRL_CLKGATE     0x40000000
-#define BF_PINCTRL_CTRL_CLKGATE(v)  (((v) << 30) & 0x40000000)
-#define BP_PINCTRL_CTRL_RSRVD2      28
-#define BM_PINCTRL_CTRL_RSRVD2      0x30000000
-#define BF_PINCTRL_CTRL_RSRVD2(v)   (((v) << 28) & 0x30000000)
-#define BP_PINCTRL_CTRL_PRESENT3    27
-#define BM_PINCTRL_CTRL_PRESENT3    0x8000000
-#define BF_PINCTRL_CTRL_PRESENT3(v) (((v) << 27) & 0x8000000)
-#define BP_PINCTRL_CTRL_PRESENT2    26
-#define BM_PINCTRL_CTRL_PRESENT2    0x4000000
-#define BF_PINCTRL_CTRL_PRESENT2(v) (((v) << 26) & 0x4000000)
-#define BP_PINCTRL_CTRL_PRESENT1    25
-#define BM_PINCTRL_CTRL_PRESENT1    0x2000000
-#define BF_PINCTRL_CTRL_PRESENT1(v) (((v) << 25) & 0x2000000)
-#define BP_PINCTRL_CTRL_PRESENT0    24
-#define BM_PINCTRL_CTRL_PRESENT0    0x1000000
-#define BF_PINCTRL_CTRL_PRESENT0(v) (((v) << 24) & 0x1000000)
-#define BP_PINCTRL_CTRL_RSRVD1      3
-#define BM_PINCTRL_CTRL_RSRVD1      0xfffff8
-#define BF_PINCTRL_CTRL_RSRVD1(v)   (((v) << 3) & 0xfffff8)
-#define BP_PINCTRL_CTRL_IRQOUT2     2
-#define BM_PINCTRL_CTRL_IRQOUT2     0x4
-#define BF_PINCTRL_CTRL_IRQOUT2(v)  (((v) << 2) & 0x4)
-#define BP_PINCTRL_CTRL_IRQOUT1     1
-#define BM_PINCTRL_CTRL_IRQOUT1     0x2
-#define BF_PINCTRL_CTRL_IRQOUT1(v)  (((v) << 1) & 0x2)
-#define BP_PINCTRL_CTRL_IRQOUT0     0
-#define BM_PINCTRL_CTRL_IRQOUT0     0x1
-#define BF_PINCTRL_CTRL_IRQOUT0(v)  (((v) << 0) & 0x1)
-
-/**
- * Register: HW_PINCTRL_MUXSELn
- * Address: 0x100+n*0x10
- * SCT: yes
-*/
-#define HW_PINCTRL_MUXSELn(n)       (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x100+(n)*0x10 + 0x0))
-#define HW_PINCTRL_MUXSELn_SET(n)   (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x100+(n)*0x10 + 0x4))
-#define HW_PINCTRL_MUXSELn_CLR(n)   (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x100+(n)*0x10 + 0x8))
-#define HW_PINCTRL_MUXSELn_TOG(n)   (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x100+(n)*0x10 + 0xc))
-#define BP_PINCTRL_MUXSELn_BITS     0
-#define BM_PINCTRL_MUXSELn_BITS     0xffffffff
-#define BF_PINCTRL_MUXSELn_BITS(v)  (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_PINCTRL_DRIVEn
- * Address: 0x200+n*0x10
- * SCT: yes
-*/
-#define HW_PINCTRL_DRIVEn(n)        (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x200+(n)*0x10 + 0x0))
-#define HW_PINCTRL_DRIVEn_SET(n)    (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x200+(n)*0x10 + 0x4))
-#define HW_PINCTRL_DRIVEn_CLR(n)    (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x200+(n)*0x10 + 0x8))
-#define HW_PINCTRL_DRIVEn_TOG(n)    (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x200+(n)*0x10 + 0xc))
-#define BP_PINCTRL_DRIVEn_BITS      0
-#define BM_PINCTRL_DRIVEn_BITS      0xffffffff
-#define BF_PINCTRL_DRIVEn_BITS(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_PINCTRL_PULLn
- * Address: 0x400+n*0x10
- * SCT: yes
-*/
-#define HW_PINCTRL_PULLn(n)         (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x400+(n)*0x10 + 0x0))
-#define HW_PINCTRL_PULLn_SET(n)     (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x400+(n)*0x10 + 0x4))
-#define HW_PINCTRL_PULLn_CLR(n)     (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x400+(n)*0x10 + 0x8))
-#define HW_PINCTRL_PULLn_TOG(n)     (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x400+(n)*0x10 + 0xc))
-#define BP_PINCTRL_PULLn_BITS       0
-#define BM_PINCTRL_PULLn_BITS       0xffffffff
-#define BF_PINCTRL_PULLn_BITS(v)    (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_PINCTRL_DOUTn
- * Address: 0x500+n*0x10
- * SCT: yes
-*/
-#define HW_PINCTRL_DOUTn(n)         (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x500+(n)*0x10 + 0x0))
-#define HW_PINCTRL_DOUTn_SET(n)     (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x500+(n)*0x10 + 0x4))
-#define HW_PINCTRL_DOUTn_CLR(n)     (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x500+(n)*0x10 + 0x8))
-#define HW_PINCTRL_DOUTn_TOG(n)     (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x500+(n)*0x10 + 0xc))
-#define BP_PINCTRL_DOUTn_BITS       0
-#define BM_PINCTRL_DOUTn_BITS       0xffffffff
-#define BF_PINCTRL_DOUTn_BITS(v)    (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_PINCTRL_DINn
- * Address: 0x600+n*0x10
- * SCT: yes
-*/
-#define HW_PINCTRL_DINn(n)      (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x600+(n)*0x10 + 0x0))
-#define HW_PINCTRL_DINn_SET(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x600+(n)*0x10 + 0x4))
-#define HW_PINCTRL_DINn_CLR(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x600+(n)*0x10 + 0x8))
-#define HW_PINCTRL_DINn_TOG(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x600+(n)*0x10 + 0xc))
-#define BP_PINCTRL_DINn_BITS    0
-#define BM_PINCTRL_DINn_BITS    0xffffffff
-#define BF_PINCTRL_DINn_BITS(v) (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_PINCTRL_DOEn
- * Address: 0x700+n*0x10
- * SCT: yes
-*/
-#define HW_PINCTRL_DOEn(n)      (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x700+(n)*0x10 + 0x0))
-#define HW_PINCTRL_DOEn_SET(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x700+(n)*0x10 + 0x4))
-#define HW_PINCTRL_DOEn_CLR(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x700+(n)*0x10 + 0x8))
-#define HW_PINCTRL_DOEn_TOG(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x700+(n)*0x10 + 0xc))
-#define BP_PINCTRL_DOEn_BITS    0
-#define BM_PINCTRL_DOEn_BITS    0xffffffff
-#define BF_PINCTRL_DOEn_BITS(v) (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_PINCTRL_PIN2IRQn
- * Address: 0x800+n*0x10
- * SCT: yes
-*/
-#define HW_PINCTRL_PIN2IRQn(n)      (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x800+(n)*0x10 + 0x0))
-#define HW_PINCTRL_PIN2IRQn_SET(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x800+(n)*0x10 + 0x4))
-#define HW_PINCTRL_PIN2IRQn_CLR(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x800+(n)*0x10 + 0x8))
-#define HW_PINCTRL_PIN2IRQn_TOG(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x800+(n)*0x10 + 0xc))
-#define BP_PINCTRL_PIN2IRQn_BITS    0
-#define BM_PINCTRL_PIN2IRQn_BITS    0xffffffff
-#define BF_PINCTRL_PIN2IRQn_BITS(v) (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_PINCTRL_IRQENn
- * Address: 0x900+n*0x10
- * SCT: yes
-*/
-#define HW_PINCTRL_IRQENn(n)        (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x900+(n)*0x10 + 0x0))
-#define HW_PINCTRL_IRQENn_SET(n)    (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x900+(n)*0x10 + 0x4))
-#define HW_PINCTRL_IRQENn_CLR(n)    (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x900+(n)*0x10 + 0x8))
-#define HW_PINCTRL_IRQENn_TOG(n)    (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x900+(n)*0x10 + 0xc))
-#define BP_PINCTRL_IRQENn_BITS      0
-#define BM_PINCTRL_IRQENn_BITS      0xffffffff
-#define BF_PINCTRL_IRQENn_BITS(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_PINCTRL_IRQLEVELn
- * Address: 0xa00+n*0x10
- * SCT: yes
-*/
-#define HW_PINCTRL_IRQLEVELn(n)         (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xa00+(n)*0x10 + 0x0))
-#define HW_PINCTRL_IRQLEVELn_SET(n)     (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xa00+(n)*0x10 + 0x4))
-#define HW_PINCTRL_IRQLEVELn_CLR(n)     (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xa00+(n)*0x10 + 0x8))
-#define HW_PINCTRL_IRQLEVELn_TOG(n)     (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xa00+(n)*0x10 + 0xc))
-#define BP_PINCTRL_IRQLEVELn_BITS       0
-#define BM_PINCTRL_IRQLEVELn_BITS       0xffffffff
-#define BF_PINCTRL_IRQLEVELn_BITS(v)    (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_PINCTRL_IRQPOLn
- * Address: 0xb00+n*0x10
- * SCT: yes
-*/
-#define HW_PINCTRL_IRQPOLn(n)       (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xb00+(n)*0x10 + 0x0))
-#define HW_PINCTRL_IRQPOLn_SET(n)   (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xb00+(n)*0x10 + 0x4))
-#define HW_PINCTRL_IRQPOLn_CLR(n)   (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xb00+(n)*0x10 + 0x8))
-#define HW_PINCTRL_IRQPOLn_TOG(n)   (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xb00+(n)*0x10 + 0xc))
-#define BP_PINCTRL_IRQPOLn_BITS     0
-#define BM_PINCTRL_IRQPOLn_BITS     0xffffffff
-#define BF_PINCTRL_IRQPOLn_BITS(v)  (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_PINCTRL_IRQSTATn
- * Address: 0xc00+n*0x10
- * SCT: yes
-*/
-#define HW_PINCTRL_IRQSTATn(n)      (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xc00+(n)*0x10 + 0x0))
-#define HW_PINCTRL_IRQSTATn_SET(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xc00+(n)*0x10 + 0x4))
-#define HW_PINCTRL_IRQSTATn_CLR(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xc00+(n)*0x10 + 0x8))
-#define HW_PINCTRL_IRQSTATn_TOG(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xc00+(n)*0x10 + 0xc))
-#define BP_PINCTRL_IRQSTATn_BITS    0
-#define BM_PINCTRL_IRQSTATn_BITS    0xffffffff
-#define BF_PINCTRL_IRQSTATn_BITS(v) (((v) << 0) & 0xffffffff)
-
-#endif /* __HEADERGEN__IMX233__PINCTRL__H__ */
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-power.h b/firmware/target/arm/imx233/regs/imx233/regs-power.h
deleted file mode 100644
index 8b0ba2ce5c..0000000000
--- a/firmware/target/arm/imx233/regs/imx233/regs-power.h
+++ /dev/null
@@ -1,807 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: imx233:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__IMX233__POWER__H__
-#define __HEADERGEN__IMX233__POWER__H__
-
-#define REGS_POWER_BASE (0x80044000)
-
-#define REGS_POWER_VERSION "3.2.0"
-
-/**
- * Register: HW_POWER_CTRL
- * Address: 0
- * SCT: yes
-*/
-#define HW_POWER_CTRL                               (*(volatile unsigned long *)(REGS_POWER_BASE + 0x0 + 0x0))
-#define HW_POWER_CTRL_SET                           (*(volatile unsigned long *)(REGS_POWER_BASE + 0x0 + 0x4))
-#define HW_POWER_CTRL_CLR                           (*(volatile unsigned long *)(REGS_POWER_BASE + 0x0 + 0x8))
-#define HW_POWER_CTRL_TOG                           (*(volatile unsigned long *)(REGS_POWER_BASE + 0x0 + 0xc))
-#define BP_POWER_CTRL_RSRVD3                        31
-#define BM_POWER_CTRL_RSRVD3                        0x80000000
-#define BF_POWER_CTRL_RSRVD3(v)                     (((v) << 31) & 0x80000000)
-#define BP_POWER_CTRL_CLKGATE                       30
-#define BM_POWER_CTRL_CLKGATE                       0x40000000
-#define BF_POWER_CTRL_CLKGATE(v)                    (((v) << 30) & 0x40000000)
-#define BP_POWER_CTRL_RSRVD2                        28
-#define BM_POWER_CTRL_RSRVD2                        0x30000000
-#define BF_POWER_CTRL_RSRVD2(v)                     (((v) << 28) & 0x30000000)
-#define BP_POWER_CTRL_PSWITCH_MID_TRAN              27
-#define BM_POWER_CTRL_PSWITCH_MID_TRAN              0x8000000
-#define BF_POWER_CTRL_PSWITCH_MID_TRAN(v)           (((v) << 27) & 0x8000000)
-#define BP_POWER_CTRL_RSRVD1                        25
-#define BM_POWER_CTRL_RSRVD1                        0x6000000
-#define BF_POWER_CTRL_RSRVD1(v)                     (((v) << 25) & 0x6000000)
-#define BP_POWER_CTRL_DCDC4P2_BO_IRQ                24
-#define BM_POWER_CTRL_DCDC4P2_BO_IRQ                0x1000000
-#define BF_POWER_CTRL_DCDC4P2_BO_IRQ(v)             (((v) << 24) & 0x1000000)
-#define BP_POWER_CTRL_ENIRQ_DCDC4P2_BO              23
-#define BM_POWER_CTRL_ENIRQ_DCDC4P2_BO              0x800000
-#define BF_POWER_CTRL_ENIRQ_DCDC4P2_BO(v)           (((v) << 23) & 0x800000)
-#define BP_POWER_CTRL_VDD5V_DROOP_IRQ               22
-#define BM_POWER_CTRL_VDD5V_DROOP_IRQ               0x400000
-#define BF_POWER_CTRL_VDD5V_DROOP_IRQ(v)            (((v) << 22) & 0x400000)
-#define BP_POWER_CTRL_ENIRQ_VDD5V_DROOP             21
-#define BM_POWER_CTRL_ENIRQ_VDD5V_DROOP             0x200000
-#define BF_POWER_CTRL_ENIRQ_VDD5V_DROOP(v)          (((v) << 21) & 0x200000)
-#define BP_POWER_CTRL_PSWITCH_IRQ                   20
-#define BM_POWER_CTRL_PSWITCH_IRQ                   0x100000
-#define BF_POWER_CTRL_PSWITCH_IRQ(v)                (((v) << 20) & 0x100000)
-#define BP_POWER_CTRL_PSWITCH_IRQ_SRC               19
-#define BM_POWER_CTRL_PSWITCH_IRQ_SRC               0x80000
-#define BF_POWER_CTRL_PSWITCH_IRQ_SRC(v)            (((v) << 19) & 0x80000)
-#define BP_POWER_CTRL_POLARITY_PSWITCH              18
-#define BM_POWER_CTRL_POLARITY_PSWITCH              0x40000
-#define BF_POWER_CTRL_POLARITY_PSWITCH(v)           (((v) << 18) & 0x40000)
-#define BP_POWER_CTRL_ENIRQ_PSWITCH                 17
-#define BM_POWER_CTRL_ENIRQ_PSWITCH                 0x20000
-#define BF_POWER_CTRL_ENIRQ_PSWITCH(v)              (((v) << 17) & 0x20000)
-#define BP_POWER_CTRL_POLARITY_DC_OK                16
-#define BM_POWER_CTRL_POLARITY_DC_OK                0x10000
-#define BF_POWER_CTRL_POLARITY_DC_OK(v)             (((v) << 16) & 0x10000)
-#define BP_POWER_CTRL_DC_OK_IRQ                     15
-#define BM_POWER_CTRL_DC_OK_IRQ                     0x8000
-#define BF_POWER_CTRL_DC_OK_IRQ(v)                  (((v) << 15) & 0x8000)
-#define BP_POWER_CTRL_ENIRQ_DC_OK                   14
-#define BM_POWER_CTRL_ENIRQ_DC_OK                   0x4000
-#define BF_POWER_CTRL_ENIRQ_DC_OK(v)                (((v) << 14) & 0x4000)
-#define BP_POWER_CTRL_BATT_BO_IRQ                   13
-#define BM_POWER_CTRL_BATT_BO_IRQ                   0x2000
-#define BF_POWER_CTRL_BATT_BO_IRQ(v)                (((v) << 13) & 0x2000)
-#define BP_POWER_CTRL_ENIRQBATT_BO                  12
-#define BM_POWER_CTRL_ENIRQBATT_BO                  0x1000
-#define BF_POWER_CTRL_ENIRQBATT_BO(v)               (((v) << 12) & 0x1000)
-#define BP_POWER_CTRL_VDDIO_BO_IRQ                  11
-#define BM_POWER_CTRL_VDDIO_BO_IRQ                  0x800
-#define BF_POWER_CTRL_VDDIO_BO_IRQ(v)               (((v) << 11) & 0x800)
-#define BP_POWER_CTRL_ENIRQ_VDDIO_BO                10
-#define BM_POWER_CTRL_ENIRQ_VDDIO_BO                0x400
-#define BF_POWER_CTRL_ENIRQ_VDDIO_BO(v)             (((v) << 10) & 0x400)
-#define BP_POWER_CTRL_VDDA_BO_IRQ                   9
-#define BM_POWER_CTRL_VDDA_BO_IRQ                   0x200
-#define BF_POWER_CTRL_VDDA_BO_IRQ(v)                (((v) << 9) & 0x200)
-#define BP_POWER_CTRL_ENIRQ_VDDA_BO                 8
-#define BM_POWER_CTRL_ENIRQ_VDDA_BO                 0x100
-#define BF_POWER_CTRL_ENIRQ_VDDA_BO(v)              (((v) << 8) & 0x100)
-#define BP_POWER_CTRL_VDDD_BO_IRQ                   7
-#define BM_POWER_CTRL_VDDD_BO_IRQ                   0x80
-#define BF_POWER_CTRL_VDDD_BO_IRQ(v)                (((v) << 7) & 0x80)
-#define BP_POWER_CTRL_ENIRQ_VDDD_BO                 6
-#define BM_POWER_CTRL_ENIRQ_VDDD_BO                 0x40
-#define BF_POWER_CTRL_ENIRQ_VDDD_BO(v)              (((v) << 6) & 0x40)
-#define BP_POWER_CTRL_POLARITY_VBUSVALID            5
-#define BM_POWER_CTRL_POLARITY_VBUSVALID            0x20
-#define BF_POWER_CTRL_POLARITY_VBUSVALID(v)         (((v) << 5) & 0x20)
-#define BP_POWER_CTRL_VBUSVALID_IRQ                 4
-#define BM_POWER_CTRL_VBUSVALID_IRQ                 0x10
-#define BF_POWER_CTRL_VBUSVALID_IRQ(v)              (((v) << 4) & 0x10)
-#define BP_POWER_CTRL_ENIRQ_VBUS_VALID              3
-#define BM_POWER_CTRL_ENIRQ_VBUS_VALID              0x8
-#define BF_POWER_CTRL_ENIRQ_VBUS_VALID(v)           (((v) << 3) & 0x8)
-#define BP_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO       2
-#define BM_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO       0x4
-#define BF_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO(v)    (((v) << 2) & 0x4)
-#define BP_POWER_CTRL_VDD5V_GT_VDDIO_IRQ            1
-#define BM_POWER_CTRL_VDD5V_GT_VDDIO_IRQ            0x2
-#define BF_POWER_CTRL_VDD5V_GT_VDDIO_IRQ(v)         (((v) << 1) & 0x2)
-#define BP_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO          0
-#define BM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO          0x1
-#define BF_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO(v)       (((v) << 0) & 0x1)
-
-/**
- * Register: HW_POWER_5VCTRL
- * Address: 0x10
- * SCT: yes
-*/
-#define HW_POWER_5VCTRL                         (*(volatile unsigned long *)(REGS_POWER_BASE + 0x10 + 0x0))
-#define HW_POWER_5VCTRL_SET                     (*(volatile unsigned long *)(REGS_POWER_BASE + 0x10 + 0x4))
-#define HW_POWER_5VCTRL_CLR                     (*(volatile unsigned long *)(REGS_POWER_BASE + 0x10 + 0x8))
-#define HW_POWER_5VCTRL_TOG                     (*(volatile unsigned long *)(REGS_POWER_BASE + 0x10 + 0xc))
-#define BP_POWER_5VCTRL_RSRVD6                  30
-#define BM_POWER_5VCTRL_RSRVD6                  0xc0000000
-#define BF_POWER_5VCTRL_RSRVD6(v)               (((v) << 30) & 0xc0000000)
-#define BP_POWER_5VCTRL_VBUSDROOP_TRSH          28
-#define BM_POWER_5VCTRL_VBUSDROOP_TRSH          0x30000000
-#define BF_POWER_5VCTRL_VBUSDROOP_TRSH(v)       (((v) << 28) & 0x30000000)
-#define BP_POWER_5VCTRL_RSRVD5                  27
-#define BM_POWER_5VCTRL_RSRVD5                  0x8000000
-#define BF_POWER_5VCTRL_RSRVD5(v)               (((v) << 27) & 0x8000000)
-#define BP_POWER_5VCTRL_HEADROOM_ADJ            24
-#define BM_POWER_5VCTRL_HEADROOM_ADJ            0x7000000
-#define BF_POWER_5VCTRL_HEADROOM_ADJ(v)         (((v) << 24) & 0x7000000)
-#define BP_POWER_5VCTRL_RSRVD4                  21
-#define BM_POWER_5VCTRL_RSRVD4                  0xe00000
-#define BF_POWER_5VCTRL_RSRVD4(v)               (((v) << 21) & 0xe00000)
-#define BP_POWER_5VCTRL_PWD_CHARGE_4P2          20
-#define BM_POWER_5VCTRL_PWD_CHARGE_4P2          0x100000
-#define BF_POWER_5VCTRL_PWD_CHARGE_4P2(v)       (((v) << 20) & 0x100000)
-#define BP_POWER_5VCTRL_RSRVD3                  18
-#define BM_POWER_5VCTRL_RSRVD3                  0xc0000
-#define BF_POWER_5VCTRL_RSRVD3(v)               (((v) << 18) & 0xc0000)
-#define BP_POWER_5VCTRL_CHARGE_4P2_ILIMIT       12
-#define BM_POWER_5VCTRL_CHARGE_4P2_ILIMIT       0x3f000
-#define BF_POWER_5VCTRL_CHARGE_4P2_ILIMIT(v)    (((v) << 12) & 0x3f000)
-#define BP_POWER_5VCTRL_RSRVD2                  11
-#define BM_POWER_5VCTRL_RSRVD2                  0x800
-#define BF_POWER_5VCTRL_RSRVD2(v)               (((v) << 11) & 0x800)
-#define BP_POWER_5VCTRL_VBUSVALID_TRSH          8
-#define BM_POWER_5VCTRL_VBUSVALID_TRSH          0x700
-#define BF_POWER_5VCTRL_VBUSVALID_TRSH(v)       (((v) << 8) & 0x700)
-#define BP_POWER_5VCTRL_PWDN_5VBRNOUT           7
-#define BM_POWER_5VCTRL_PWDN_5VBRNOUT           0x80
-#define BF_POWER_5VCTRL_PWDN_5VBRNOUT(v)        (((v) << 7) & 0x80)
-#define BP_POWER_5VCTRL_ENABLE_LINREG_ILIMIT    6
-#define BM_POWER_5VCTRL_ENABLE_LINREG_ILIMIT    0x40
-#define BF_POWER_5VCTRL_ENABLE_LINREG_ILIMIT(v) (((v) << 6) & 0x40)
-#define BP_POWER_5VCTRL_DCDC_XFER               5
-#define BM_POWER_5VCTRL_DCDC_XFER               0x20
-#define BF_POWER_5VCTRL_DCDC_XFER(v)            (((v) << 5) & 0x20)
-#define BP_POWER_5VCTRL_VBUSVALID_5VDETECT      4
-#define BM_POWER_5VCTRL_VBUSVALID_5VDETECT      0x10
-#define BF_POWER_5VCTRL_VBUSVALID_5VDETECT(v)   (((v) << 4) & 0x10)
-#define BP_POWER_5VCTRL_VBUSVALID_TO_B          3
-#define BM_POWER_5VCTRL_VBUSVALID_TO_B          0x8
-#define BF_POWER_5VCTRL_VBUSVALID_TO_B(v)       (((v) << 3) & 0x8)
-#define BP_POWER_5VCTRL_ILIMIT_EQ_ZERO          2
-#define BM_POWER_5VCTRL_ILIMIT_EQ_ZERO          0x4
-#define BF_POWER_5VCTRL_ILIMIT_EQ_ZERO(v)       (((v) << 2) & 0x4)
-#define BP_POWER_5VCTRL_PWRUP_VBUS_CMPS         1
-#define BM_POWER_5VCTRL_PWRUP_VBUS_CMPS         0x2
-#define BF_POWER_5VCTRL_PWRUP_VBUS_CMPS(v)      (((v) << 1) & 0x2)
-#define BP_POWER_5VCTRL_ENABLE_DCDC             0
-#define BM_POWER_5VCTRL_ENABLE_DCDC             0x1
-#define BF_POWER_5VCTRL_ENABLE_DCDC(v)          (((v) << 0) & 0x1)
-
-/**
- * Register: HW_POWER_MINPWR
- * Address: 0x20
- * SCT: yes
-*/
-#define HW_POWER_MINPWR                     (*(volatile unsigned long *)(REGS_POWER_BASE + 0x20 + 0x0))
-#define HW_POWER_MINPWR_SET                 (*(volatile unsigned long *)(REGS_POWER_BASE + 0x20 + 0x4))
-#define HW_POWER_MINPWR_CLR                 (*(volatile unsigned long *)(REGS_POWER_BASE + 0x20 + 0x8))
-#define HW_POWER_MINPWR_TOG                 (*(volatile unsigned long *)(REGS_POWER_BASE + 0x20 + 0xc))
-#define BP_POWER_MINPWR_RSRVD1              15
-#define BM_POWER_MINPWR_RSRVD1              0xffff8000
-#define BF_POWER_MINPWR_RSRVD1(v)           (((v) << 15) & 0xffff8000)
-#define BP_POWER_MINPWR_LOWPWR_4P2          14
-#define BM_POWER_MINPWR_LOWPWR_4P2          0x4000
-#define BF_POWER_MINPWR_LOWPWR_4P2(v)       (((v) << 14) & 0x4000)
-#define BP_POWER_MINPWR_VDAC_DUMP_CTRL      13
-#define BM_POWER_MINPWR_VDAC_DUMP_CTRL      0x2000
-#define BF_POWER_MINPWR_VDAC_DUMP_CTRL(v)   (((v) << 13) & 0x2000)
-#define BP_POWER_MINPWR_PWD_BO              12
-#define BM_POWER_MINPWR_PWD_BO              0x1000
-#define BF_POWER_MINPWR_PWD_BO(v)           (((v) << 12) & 0x1000)
-#define BP_POWER_MINPWR_USE_VDDXTAL_VBG     11
-#define BM_POWER_MINPWR_USE_VDDXTAL_VBG     0x800
-#define BF_POWER_MINPWR_USE_VDDXTAL_VBG(v)  (((v) << 11) & 0x800)
-#define BP_POWER_MINPWR_PWD_ANA_CMPS        10
-#define BM_POWER_MINPWR_PWD_ANA_CMPS        0x400
-#define BF_POWER_MINPWR_PWD_ANA_CMPS(v)     (((v) << 10) & 0x400)
-#define BP_POWER_MINPWR_ENABLE_OSC          9
-#define BM_POWER_MINPWR_ENABLE_OSC          0x200
-#define BF_POWER_MINPWR_ENABLE_OSC(v)       (((v) << 9) & 0x200)
-#define BP_POWER_MINPWR_SELECT_OSC          8
-#define BM_POWER_MINPWR_SELECT_OSC          0x100
-#define BF_POWER_MINPWR_SELECT_OSC(v)       (((v) << 8) & 0x100)
-#define BP_POWER_MINPWR_VBG_OFF             7
-#define BM_POWER_MINPWR_VBG_OFF             0x80
-#define BF_POWER_MINPWR_VBG_OFF(v)          (((v) << 7) & 0x80)
-#define BP_POWER_MINPWR_DOUBLE_FETS         6
-#define BM_POWER_MINPWR_DOUBLE_FETS         0x40
-#define BF_POWER_MINPWR_DOUBLE_FETS(v)      (((v) << 6) & 0x40)
-#define BP_POWER_MINPWR_HALF_FETS           5
-#define BM_POWER_MINPWR_HALF_FETS           0x20
-#define BF_POWER_MINPWR_HALF_FETS(v)        (((v) << 5) & 0x20)
-#define BP_POWER_MINPWR_LESSANA_I           4
-#define BM_POWER_MINPWR_LESSANA_I           0x10
-#define BF_POWER_MINPWR_LESSANA_I(v)        (((v) << 4) & 0x10)
-#define BP_POWER_MINPWR_PWD_XTAL24          3
-#define BM_POWER_MINPWR_PWD_XTAL24          0x8
-#define BF_POWER_MINPWR_PWD_XTAL24(v)       (((v) << 3) & 0x8)
-#define BP_POWER_MINPWR_DC_STOPCLK          2
-#define BM_POWER_MINPWR_DC_STOPCLK          0x4
-#define BF_POWER_MINPWR_DC_STOPCLK(v)       (((v) << 2) & 0x4)
-#define BP_POWER_MINPWR_EN_DC_PFM           1
-#define BM_POWER_MINPWR_EN_DC_PFM           0x2
-#define BF_POWER_MINPWR_EN_DC_PFM(v)        (((v) << 1) & 0x2)
-#define BP_POWER_MINPWR_DC_HALFCLK          0
-#define BM_POWER_MINPWR_DC_HALFCLK          0x1
-#define BF_POWER_MINPWR_DC_HALFCLK(v)       (((v) << 0) & 0x1)
-
-/**
- * Register: HW_POWER_CHARGE
- * Address: 0x30
- * SCT: yes
-*/
-#define HW_POWER_CHARGE                             (*(volatile unsigned long *)(REGS_POWER_BASE + 0x30 + 0x0))
-#define HW_POWER_CHARGE_SET                         (*(volatile unsigned long *)(REGS_POWER_BASE + 0x30 + 0x4))
-#define HW_POWER_CHARGE_CLR                         (*(volatile unsigned long *)(REGS_POWER_BASE + 0x30 + 0x8))
-#define HW_POWER_CHARGE_TOG                         (*(volatile unsigned long *)(REGS_POWER_BASE + 0x30 + 0xc))
-#define BP_POWER_CHARGE_RSRVD4                      27
-#define BM_POWER_CHARGE_RSRVD4                      0xf8000000
-#define BF_POWER_CHARGE_RSRVD4(v)                   (((v) << 27) & 0xf8000000)
-#define BP_POWER_CHARGE_ADJ_VOLT                    24
-#define BM_POWER_CHARGE_ADJ_VOLT                    0x7000000
-#define BF_POWER_CHARGE_ADJ_VOLT(v)                 (((v) << 24) & 0x7000000)
-#define BP_POWER_CHARGE_RSRVD3                      23
-#define BM_POWER_CHARGE_RSRVD3                      0x800000
-#define BF_POWER_CHARGE_RSRVD3(v)                   (((v) << 23) & 0x800000)
-#define BP_POWER_CHARGE_ENABLE_LOAD                 22
-#define BM_POWER_CHARGE_ENABLE_LOAD                 0x400000
-#define BF_POWER_CHARGE_ENABLE_LOAD(v)              (((v) << 22) & 0x400000)
-#define BP_POWER_CHARGE_ENABLE_CHARGER_RESISTORS    21
-#define BM_POWER_CHARGE_ENABLE_CHARGER_RESISTORS    0x200000
-#define BF_POWER_CHARGE_ENABLE_CHARGER_RESISTORS(v) (((v) << 21) & 0x200000)
-#define BP_POWER_CHARGE_ENABLE_FAULT_DETECT         20
-#define BM_POWER_CHARGE_ENABLE_FAULT_DETECT         0x100000
-#define BF_POWER_CHARGE_ENABLE_FAULT_DETECT(v)      (((v) << 20) & 0x100000)
-#define BP_POWER_CHARGE_CHRG_STS_OFF                19
-#define BM_POWER_CHARGE_CHRG_STS_OFF                0x80000
-#define BF_POWER_CHARGE_CHRG_STS_OFF(v)             (((v) << 19) & 0x80000)
-#define BP_POWER_CHARGE_LIION_4P1                   18
-#define BM_POWER_CHARGE_LIION_4P1                   0x40000
-#define BF_POWER_CHARGE_LIION_4P1(v)                (((v) << 18) & 0x40000)
-#define BP_POWER_CHARGE_USE_EXTERN_R                17
-#define BM_POWER_CHARGE_USE_EXTERN_R                0x20000
-#define BF_POWER_CHARGE_USE_EXTERN_R(v)             (((v) << 17) & 0x20000)
-#define BP_POWER_CHARGE_PWD_BATTCHRG                16
-#define BM_POWER_CHARGE_PWD_BATTCHRG                0x10000
-#define BF_POWER_CHARGE_PWD_BATTCHRG(v)             (((v) << 16) & 0x10000)
-#define BP_POWER_CHARGE_RSRVD2                      12
-#define BM_POWER_CHARGE_RSRVD2                      0xf000
-#define BF_POWER_CHARGE_RSRVD2(v)                   (((v) << 12) & 0xf000)
-#define BP_POWER_CHARGE_STOP_ILIMIT                 8
-#define BM_POWER_CHARGE_STOP_ILIMIT                 0xf00
-#define BF_POWER_CHARGE_STOP_ILIMIT(v)              (((v) << 8) & 0xf00)
-#define BP_POWER_CHARGE_RSRVD1                      6
-#define BM_POWER_CHARGE_RSRVD1                      0xc0
-#define BF_POWER_CHARGE_RSRVD1(v)                   (((v) << 6) & 0xc0)
-#define BP_POWER_CHARGE_BATTCHRG_I                  0
-#define BM_POWER_CHARGE_BATTCHRG_I                  0x3f
-#define BF_POWER_CHARGE_BATTCHRG_I(v)               (((v) << 0) & 0x3f)
-
-/**
- * Register: HW_POWER_VDDDCTRL
- * Address: 0x40
- * SCT: no
-*/
-#define HW_POWER_VDDDCTRL                       (*(volatile unsigned long *)(REGS_POWER_BASE + 0x40))
-#define BP_POWER_VDDDCTRL_ADJTN                 28
-#define BM_POWER_VDDDCTRL_ADJTN                 0xf0000000
-#define BF_POWER_VDDDCTRL_ADJTN(v)              (((v) << 28) & 0xf0000000)
-#define BP_POWER_VDDDCTRL_RSRVD4                24
-#define BM_POWER_VDDDCTRL_RSRVD4                0xf000000
-#define BF_POWER_VDDDCTRL_RSRVD4(v)             (((v) << 24) & 0xf000000)
-#define BP_POWER_VDDDCTRL_PWDN_BRNOUT           23
-#define BM_POWER_VDDDCTRL_PWDN_BRNOUT           0x800000
-#define BF_POWER_VDDDCTRL_PWDN_BRNOUT(v)        (((v) << 23) & 0x800000)
-#define BP_POWER_VDDDCTRL_DISABLE_STEPPING      22
-#define BM_POWER_VDDDCTRL_DISABLE_STEPPING      0x400000
-#define BF_POWER_VDDDCTRL_DISABLE_STEPPING(v)   (((v) << 22) & 0x400000)
-#define BP_POWER_VDDDCTRL_ENABLE_LINREG         21
-#define BM_POWER_VDDDCTRL_ENABLE_LINREG         0x200000
-#define BF_POWER_VDDDCTRL_ENABLE_LINREG(v)      (((v) << 21) & 0x200000)
-#define BP_POWER_VDDDCTRL_DISABLE_FET           20
-#define BM_POWER_VDDDCTRL_DISABLE_FET           0x100000
-#define BF_POWER_VDDDCTRL_DISABLE_FET(v)        (((v) << 20) & 0x100000)
-#define BP_POWER_VDDDCTRL_RSRVD3                18
-#define BM_POWER_VDDDCTRL_RSRVD3                0xc0000
-#define BF_POWER_VDDDCTRL_RSRVD3(v)             (((v) << 18) & 0xc0000)
-#define BP_POWER_VDDDCTRL_LINREG_OFFSET         16
-#define BM_POWER_VDDDCTRL_LINREG_OFFSET         0x30000
-#define BF_POWER_VDDDCTRL_LINREG_OFFSET(v)      (((v) << 16) & 0x30000)
-#define BP_POWER_VDDDCTRL_RSRVD2                11
-#define BM_POWER_VDDDCTRL_RSRVD2                0xf800
-#define BF_POWER_VDDDCTRL_RSRVD2(v)             (((v) << 11) & 0xf800)
-#define BP_POWER_VDDDCTRL_BO_OFFSET             8
-#define BM_POWER_VDDDCTRL_BO_OFFSET             0x700
-#define BF_POWER_VDDDCTRL_BO_OFFSET(v)          (((v) << 8) & 0x700)
-#define BP_POWER_VDDDCTRL_RSRVD1                5
-#define BM_POWER_VDDDCTRL_RSRVD1                0xe0
-#define BF_POWER_VDDDCTRL_RSRVD1(v)             (((v) << 5) & 0xe0)
-#define BP_POWER_VDDDCTRL_TRG                   0
-#define BM_POWER_VDDDCTRL_TRG                   0x1f
-#define BF_POWER_VDDDCTRL_TRG(v)                (((v) << 0) & 0x1f)
-
-/**
- * Register: HW_POWER_VDDACTRL
- * Address: 0x50
- * SCT: no
-*/
-#define HW_POWER_VDDACTRL                       (*(volatile unsigned long *)(REGS_POWER_BASE + 0x50))
-#define BP_POWER_VDDACTRL_RSRVD4                20
-#define BM_POWER_VDDACTRL_RSRVD4                0xfff00000
-#define BF_POWER_VDDACTRL_RSRVD4(v)             (((v) << 20) & 0xfff00000)
-#define BP_POWER_VDDACTRL_PWDN_BRNOUT           19
-#define BM_POWER_VDDACTRL_PWDN_BRNOUT           0x80000
-#define BF_POWER_VDDACTRL_PWDN_BRNOUT(v)        (((v) << 19) & 0x80000)
-#define BP_POWER_VDDACTRL_DISABLE_STEPPING      18
-#define BM_POWER_VDDACTRL_DISABLE_STEPPING      0x40000
-#define BF_POWER_VDDACTRL_DISABLE_STEPPING(v)   (((v) << 18) & 0x40000)
-#define BP_POWER_VDDACTRL_ENABLE_LINREG         17
-#define BM_POWER_VDDACTRL_ENABLE_LINREG         0x20000
-#define BF_POWER_VDDACTRL_ENABLE_LINREG(v)      (((v) << 17) & 0x20000)
-#define BP_POWER_VDDACTRL_DISABLE_FET           16
-#define BM_POWER_VDDACTRL_DISABLE_FET           0x10000
-#define BF_POWER_VDDACTRL_DISABLE_FET(v)        (((v) << 16) & 0x10000)
-#define BP_POWER_VDDACTRL_RSRVD3                14
-#define BM_POWER_VDDACTRL_RSRVD3                0xc000
-#define BF_POWER_VDDACTRL_RSRVD3(v)             (((v) << 14) & 0xc000)
-#define BP_POWER_VDDACTRL_LINREG_OFFSET         12
-#define BM_POWER_VDDACTRL_LINREG_OFFSET         0x3000
-#define BF_POWER_VDDACTRL_LINREG_OFFSET(v)      (((v) << 12) & 0x3000)
-#define BP_POWER_VDDACTRL_RSRVD2                11
-#define BM_POWER_VDDACTRL_RSRVD2                0x800
-#define BF_POWER_VDDACTRL_RSRVD2(v)             (((v) << 11) & 0x800)
-#define BP_POWER_VDDACTRL_BO_OFFSET             8
-#define BM_POWER_VDDACTRL_BO_OFFSET             0x700
-#define BF_POWER_VDDACTRL_BO_OFFSET(v)          (((v) << 8) & 0x700)
-#define BP_POWER_VDDACTRL_RSRVD1                5
-#define BM_POWER_VDDACTRL_RSRVD1                0xe0
-#define BF_POWER_VDDACTRL_RSRVD1(v)             (((v) << 5) & 0xe0)
-#define BP_POWER_VDDACTRL_TRG                   0
-#define BM_POWER_VDDACTRL_TRG                   0x1f
-#define BF_POWER_VDDACTRL_TRG(v)                (((v) << 0) & 0x1f)
-
-/**
- * Register: HW_POWER_VDDIOCTRL
- * Address: 0x60
- * SCT: no
-*/
-#define HW_POWER_VDDIOCTRL                      (*(volatile unsigned long *)(REGS_POWER_BASE + 0x60))
-#define BP_POWER_VDDIOCTRL_RSRVD5               24
-#define BM_POWER_VDDIOCTRL_RSRVD5               0xff000000
-#define BF_POWER_VDDIOCTRL_RSRVD5(v)            (((v) << 24) & 0xff000000)
-#define BP_POWER_VDDIOCTRL_ADJTN                20
-#define BM_POWER_VDDIOCTRL_ADJTN                0xf00000
-#define BF_POWER_VDDIOCTRL_ADJTN(v)             (((v) << 20) & 0xf00000)
-#define BP_POWER_VDDIOCTRL_RSRVD4               19
-#define BM_POWER_VDDIOCTRL_RSRVD4               0x80000
-#define BF_POWER_VDDIOCTRL_RSRVD4(v)            (((v) << 19) & 0x80000)
-#define BP_POWER_VDDIOCTRL_PWDN_BRNOUT          18
-#define BM_POWER_VDDIOCTRL_PWDN_BRNOUT          0x40000
-#define BF_POWER_VDDIOCTRL_PWDN_BRNOUT(v)       (((v) << 18) & 0x40000)
-#define BP_POWER_VDDIOCTRL_DISABLE_STEPPING     17
-#define BM_POWER_VDDIOCTRL_DISABLE_STEPPING     0x20000
-#define BF_POWER_VDDIOCTRL_DISABLE_STEPPING(v)  (((v) << 17) & 0x20000)
-#define BP_POWER_VDDIOCTRL_DISABLE_FET          16
-#define BM_POWER_VDDIOCTRL_DISABLE_FET          0x10000
-#define BF_POWER_VDDIOCTRL_DISABLE_FET(v)       (((v) << 16) & 0x10000)
-#define BP_POWER_VDDIOCTRL_RSRVD3               14
-#define BM_POWER_VDDIOCTRL_RSRVD3               0xc000
-#define BF_POWER_VDDIOCTRL_RSRVD3(v)            (((v) << 14) & 0xc000)
-#define BP_POWER_VDDIOCTRL_LINREG_OFFSET        12
-#define BM_POWER_VDDIOCTRL_LINREG_OFFSET        0x3000
-#define BF_POWER_VDDIOCTRL_LINREG_OFFSET(v)     (((v) << 12) & 0x3000)
-#define BP_POWER_VDDIOCTRL_RSRVD2               11
-#define BM_POWER_VDDIOCTRL_RSRVD2               0x800
-#define BF_POWER_VDDIOCTRL_RSRVD2(v)            (((v) << 11) & 0x800)
-#define BP_POWER_VDDIOCTRL_BO_OFFSET            8
-#define BM_POWER_VDDIOCTRL_BO_OFFSET            0x700
-#define BF_POWER_VDDIOCTRL_BO_OFFSET(v)         (((v) << 8) & 0x700)
-#define BP_POWER_VDDIOCTRL_RSRVD1               5
-#define BM_POWER_VDDIOCTRL_RSRVD1               0xe0
-#define BF_POWER_VDDIOCTRL_RSRVD1(v)            (((v) << 5) & 0xe0)
-#define BP_POWER_VDDIOCTRL_TRG                  0
-#define BM_POWER_VDDIOCTRL_TRG                  0x1f
-#define BF_POWER_VDDIOCTRL_TRG(v)               (((v) << 0) & 0x1f)
-
-/**
- * Register: HW_POWER_VDDMEMCTRL
- * Address: 0x70
- * SCT: no
-*/
-#define HW_POWER_VDDMEMCTRL                     (*(volatile unsigned long *)(REGS_POWER_BASE + 0x70))
-#define BP_POWER_VDDMEMCTRL_RSRVD2              11
-#define BM_POWER_VDDMEMCTRL_RSRVD2              0xfffff800
-#define BF_POWER_VDDMEMCTRL_RSRVD2(v)           (((v) << 11) & 0xfffff800)
-#define BP_POWER_VDDMEMCTRL_PULLDOWN_ACTIVE     10
-#define BM_POWER_VDDMEMCTRL_PULLDOWN_ACTIVE     0x400
-#define BF_POWER_VDDMEMCTRL_PULLDOWN_ACTIVE(v)  (((v) << 10) & 0x400)
-#define BP_POWER_VDDMEMCTRL_ENABLE_ILIMIT       9
-#define BM_POWER_VDDMEMCTRL_ENABLE_ILIMIT       0x200
-#define BF_POWER_VDDMEMCTRL_ENABLE_ILIMIT(v)    (((v) << 9) & 0x200)
-#define BP_POWER_VDDMEMCTRL_ENABLE_LINREG       8
-#define BM_POWER_VDDMEMCTRL_ENABLE_LINREG       0x100
-#define BF_POWER_VDDMEMCTRL_ENABLE_LINREG(v)    (((v) << 8) & 0x100)
-#define BP_POWER_VDDMEMCTRL_RSRVD1              5
-#define BM_POWER_VDDMEMCTRL_RSRVD1              0xe0
-#define BF_POWER_VDDMEMCTRL_RSRVD1(v)           (((v) << 5) & 0xe0)
-#define BP_POWER_VDDMEMCTRL_TRG                 0
-#define BM_POWER_VDDMEMCTRL_TRG                 0x1f
-#define BF_POWER_VDDMEMCTRL_TRG(v)              (((v) << 0) & 0x1f)
-
-/**
- * Register: HW_POWER_DCDC4P2
- * Address: 0x80
- * SCT: no
-*/
-#define HW_POWER_DCDC4P2                    (*(volatile unsigned long *)(REGS_POWER_BASE + 0x80))
-#define BP_POWER_DCDC4P2_DROPOUT_CTRL       28
-#define BM_POWER_DCDC4P2_DROPOUT_CTRL       0xf0000000
-#define BF_POWER_DCDC4P2_DROPOUT_CTRL(v)    (((v) << 28) & 0xf0000000)
-#define BP_POWER_DCDC4P2_RSRVD5             26
-#define BM_POWER_DCDC4P2_RSRVD5             0xc000000
-#define BF_POWER_DCDC4P2_RSRVD5(v)          (((v) << 26) & 0xc000000)
-#define BP_POWER_DCDC4P2_ISTEAL_THRESH      24
-#define BM_POWER_DCDC4P2_ISTEAL_THRESH      0x3000000
-#define BF_POWER_DCDC4P2_ISTEAL_THRESH(v)   (((v) << 24) & 0x3000000)
-#define BP_POWER_DCDC4P2_ENABLE_4P2         23
-#define BM_POWER_DCDC4P2_ENABLE_4P2         0x800000
-#define BF_POWER_DCDC4P2_ENABLE_4P2(v)      (((v) << 23) & 0x800000)
-#define BP_POWER_DCDC4P2_ENABLE_DCDC        22
-#define BM_POWER_DCDC4P2_ENABLE_DCDC        0x400000
-#define BF_POWER_DCDC4P2_ENABLE_DCDC(v)     (((v) << 22) & 0x400000)
-#define BP_POWER_DCDC4P2_HYST_DIR           21
-#define BM_POWER_DCDC4P2_HYST_DIR           0x200000
-#define BF_POWER_DCDC4P2_HYST_DIR(v)        (((v) << 21) & 0x200000)
-#define BP_POWER_DCDC4P2_HYST_THRESH        20
-#define BM_POWER_DCDC4P2_HYST_THRESH        0x100000
-#define BF_POWER_DCDC4P2_HYST_THRESH(v)     (((v) << 20) & 0x100000)
-#define BP_POWER_DCDC4P2_RSRVD3             19
-#define BM_POWER_DCDC4P2_RSRVD3             0x80000
-#define BF_POWER_DCDC4P2_RSRVD3(v)          (((v) << 19) & 0x80000)
-#define BP_POWER_DCDC4P2_TRG                16
-#define BM_POWER_DCDC4P2_TRG                0x70000
-#define BF_POWER_DCDC4P2_TRG(v)             (((v) << 16) & 0x70000)
-#define BP_POWER_DCDC4P2_RSRVD2             13
-#define BM_POWER_DCDC4P2_RSRVD2             0xe000
-#define BF_POWER_DCDC4P2_RSRVD2(v)          (((v) << 13) & 0xe000)
-#define BP_POWER_DCDC4P2_BO                 8
-#define BM_POWER_DCDC4P2_BO                 0x1f00
-#define BF_POWER_DCDC4P2_BO(v)              (((v) << 8) & 0x1f00)
-#define BP_POWER_DCDC4P2_RSRVD1             5
-#define BM_POWER_DCDC4P2_RSRVD1             0xe0
-#define BF_POWER_DCDC4P2_RSRVD1(v)          (((v) << 5) & 0xe0)
-#define BP_POWER_DCDC4P2_CMPTRIP            0
-#define BM_POWER_DCDC4P2_CMPTRIP            0x1f
-#define BF_POWER_DCDC4P2_CMPTRIP(v)         (((v) << 0) & 0x1f)
-
-/**
- * Register: HW_POWER_MISC
- * Address: 0x90
- * SCT: no
-*/
-#define HW_POWER_MISC                   (*(volatile unsigned long *)(REGS_POWER_BASE + 0x90))
-#define BP_POWER_MISC_RSRVD2            7
-#define BM_POWER_MISC_RSRVD2            0xffffff80
-#define BF_POWER_MISC_RSRVD2(v)         (((v) << 7) & 0xffffff80)
-#define BP_POWER_MISC_FREQSEL           4
-#define BM_POWER_MISC_FREQSEL           0x70
-#define BF_POWER_MISC_FREQSEL(v)        (((v) << 4) & 0x70)
-#define BP_POWER_MISC_RSRVD1            3
-#define BM_POWER_MISC_RSRVD1            0x8
-#define BF_POWER_MISC_RSRVD1(v)         (((v) << 3) & 0x8)
-#define BP_POWER_MISC_DELAY_TIMING      2
-#define BM_POWER_MISC_DELAY_TIMING      0x4
-#define BF_POWER_MISC_DELAY_TIMING(v)   (((v) << 2) & 0x4)
-#define BP_POWER_MISC_TEST              1
-#define BM_POWER_MISC_TEST              0x2
-#define BF_POWER_MISC_TEST(v)           (((v) << 1) & 0x2)
-#define BP_POWER_MISC_SEL_PLLCLK        0
-#define BM_POWER_MISC_SEL_PLLCLK        0x1
-#define BF_POWER_MISC_SEL_PLLCLK(v)     (((v) << 0) & 0x1)
-
-/**
- * Register: HW_POWER_DCLIMITS
- * Address: 0xa0
- * SCT: no
-*/
-#define HW_POWER_DCLIMITS                   (*(volatile unsigned long *)(REGS_POWER_BASE + 0xa0))
-#define BP_POWER_DCLIMITS_RSRVD3            16
-#define BM_POWER_DCLIMITS_RSRVD3            0xffff0000
-#define BF_POWER_DCLIMITS_RSRVD3(v)         (((v) << 16) & 0xffff0000)
-#define BP_POWER_DCLIMITS_RSRVD2            15
-#define BM_POWER_DCLIMITS_RSRVD2            0x8000
-#define BF_POWER_DCLIMITS_RSRVD2(v)         (((v) << 15) & 0x8000)
-#define BP_POWER_DCLIMITS_POSLIMIT_BUCK     8
-#define BM_POWER_DCLIMITS_POSLIMIT_BUCK     0x7f00
-#define BF_POWER_DCLIMITS_POSLIMIT_BUCK(v)  (((v) << 8) & 0x7f00)
-#define BP_POWER_DCLIMITS_RSRVD1            7
-#define BM_POWER_DCLIMITS_RSRVD1            0x80
-#define BF_POWER_DCLIMITS_RSRVD1(v)         (((v) << 7) & 0x80)
-#define BP_POWER_DCLIMITS_NEGLIMIT          0
-#define BM_POWER_DCLIMITS_NEGLIMIT          0x7f
-#define BF_POWER_DCLIMITS_NEGLIMIT(v)       (((v) << 0) & 0x7f)
-
-/**
- * Register: HW_POWER_LOOPCTRL
- * Address: 0xb0
- * SCT: yes
-*/
-#define HW_POWER_LOOPCTRL                   (*(volatile unsigned long *)(REGS_POWER_BASE + 0xb0 + 0x0))
-#define HW_POWER_LOOPCTRL_SET               (*(volatile unsigned long *)(REGS_POWER_BASE + 0xb0 + 0x4))
-#define HW_POWER_LOOPCTRL_CLR               (*(volatile unsigned long *)(REGS_POWER_BASE + 0xb0 + 0x8))
-#define HW_POWER_LOOPCTRL_TOG               (*(volatile unsigned long *)(REGS_POWER_BASE + 0xb0 + 0xc))
-#define BP_POWER_LOOPCTRL_RSRVD3            21
-#define BM_POWER_LOOPCTRL_RSRVD3            0xffe00000
-#define BF_POWER_LOOPCTRL_RSRVD3(v)         (((v) << 21) & 0xffe00000)
-#define BP_POWER_LOOPCTRL_TOGGLE_DIF        20
-#define BM_POWER_LOOPCTRL_TOGGLE_DIF        0x100000
-#define BF_POWER_LOOPCTRL_TOGGLE_DIF(v)     (((v) << 20) & 0x100000)
-#define BP_POWER_LOOPCTRL_HYST_SIGN         19
-#define BM_POWER_LOOPCTRL_HYST_SIGN         0x80000
-#define BF_POWER_LOOPCTRL_HYST_SIGN(v)      (((v) << 19) & 0x80000)
-#define BP_POWER_LOOPCTRL_EN_CM_HYST        18
-#define BM_POWER_LOOPCTRL_EN_CM_HYST        0x40000
-#define BF_POWER_LOOPCTRL_EN_CM_HYST(v)     (((v) << 18) & 0x40000)
-#define BP_POWER_LOOPCTRL_EN_DF_HYST        17
-#define BM_POWER_LOOPCTRL_EN_DF_HYST        0x20000
-#define BF_POWER_LOOPCTRL_EN_DF_HYST(v)     (((v) << 17) & 0x20000)
-#define BP_POWER_LOOPCTRL_CM_HYST_THRESH    16
-#define BM_POWER_LOOPCTRL_CM_HYST_THRESH    0x10000
-#define BF_POWER_LOOPCTRL_CM_HYST_THRESH(v) (((v) << 16) & 0x10000)
-#define BP_POWER_LOOPCTRL_DF_HYST_THRESH    15
-#define BM_POWER_LOOPCTRL_DF_HYST_THRESH    0x8000
-#define BF_POWER_LOOPCTRL_DF_HYST_THRESH(v) (((v) << 15) & 0x8000)
-#define BP_POWER_LOOPCTRL_RCSCALE_THRESH    14
-#define BM_POWER_LOOPCTRL_RCSCALE_THRESH    0x4000
-#define BF_POWER_LOOPCTRL_RCSCALE_THRESH(v) (((v) << 14) & 0x4000)
-#define BP_POWER_LOOPCTRL_EN_RCSCALE        12
-#define BM_POWER_LOOPCTRL_EN_RCSCALE        0x3000
-#define BF_POWER_LOOPCTRL_EN_RCSCALE(v)     (((v) << 12) & 0x3000)
-#define BP_POWER_LOOPCTRL_RSRVD2            11
-#define BM_POWER_LOOPCTRL_RSRVD2            0x800
-#define BF_POWER_LOOPCTRL_RSRVD2(v)         (((v) << 11) & 0x800)
-#define BP_POWER_LOOPCTRL_DC_FF             8
-#define BM_POWER_LOOPCTRL_DC_FF             0x700
-#define BF_POWER_LOOPCTRL_DC_FF(v)          (((v) << 8) & 0x700)
-#define BP_POWER_LOOPCTRL_DC_R              4
-#define BM_POWER_LOOPCTRL_DC_R              0xf0
-#define BF_POWER_LOOPCTRL_DC_R(v)           (((v) << 4) & 0xf0)
-#define BP_POWER_LOOPCTRL_RSRVD1            2
-#define BM_POWER_LOOPCTRL_RSRVD1            0xc
-#define BF_POWER_LOOPCTRL_RSRVD1(v)         (((v) << 2) & 0xc)
-#define BP_POWER_LOOPCTRL_DC_C              0
-#define BM_POWER_LOOPCTRL_DC_C              0x3
-#define BF_POWER_LOOPCTRL_DC_C(v)           (((v) << 0) & 0x3)
-
-/**
- * Register: HW_POWER_STS
- * Address: 0xc0
- * SCT: no
-*/
-#define HW_POWER_STS                        (*(volatile unsigned long *)(REGS_POWER_BASE + 0xc0))
-#define BP_POWER_STS_RSRVD3                 30
-#define BM_POWER_STS_RSRVD3                 0xc0000000
-#define BF_POWER_STS_RSRVD3(v)              (((v) << 30) & 0xc0000000)
-#define BP_POWER_STS_PWRUP_SOURCE           24
-#define BM_POWER_STS_PWRUP_SOURCE           0x3f000000
-#define BF_POWER_STS_PWRUP_SOURCE(v)        (((v) << 24) & 0x3f000000)
-#define BP_POWER_STS_RSRVD2                 22
-#define BM_POWER_STS_RSRVD2                 0xc00000
-#define BF_POWER_STS_RSRVD2(v)              (((v) << 22) & 0xc00000)
-#define BP_POWER_STS_PSWITCH                20
-#define BM_POWER_STS_PSWITCH                0x300000
-#define BF_POWER_STS_PSWITCH(v)             (((v) << 20) & 0x300000)
-#define BP_POWER_STS_RSRVD1                 18
-#define BM_POWER_STS_RSRVD1                 0xc0000
-#define BF_POWER_STS_RSRVD1(v)              (((v) << 18) & 0xc0000)
-#define BP_POWER_STS_AVALID_STATUS          17
-#define BM_POWER_STS_AVALID_STATUS          0x20000
-#define BF_POWER_STS_AVALID_STATUS(v)       (((v) << 17) & 0x20000)
-#define BP_POWER_STS_BVALID_STATUS          16
-#define BM_POWER_STS_BVALID_STATUS          0x10000
-#define BF_POWER_STS_BVALID_STATUS(v)       (((v) << 16) & 0x10000)
-#define BP_POWER_STS_VBUSVALID_STATUS       15
-#define BM_POWER_STS_VBUSVALID_STATUS       0x8000
-#define BF_POWER_STS_VBUSVALID_STATUS(v)    (((v) << 15) & 0x8000)
-#define BP_POWER_STS_SESSEND_STATUS         14
-#define BM_POWER_STS_SESSEND_STATUS         0x4000
-#define BF_POWER_STS_SESSEND_STATUS(v)      (((v) << 14) & 0x4000)
-#define BP_POWER_STS_BATT_BO                13
-#define BM_POWER_STS_BATT_BO                0x2000
-#define BF_POWER_STS_BATT_BO(v)             (((v) << 13) & 0x2000)
-#define BP_POWER_STS_VDD5V_FAULT            12
-#define BM_POWER_STS_VDD5V_FAULT            0x1000
-#define BF_POWER_STS_VDD5V_FAULT(v)         (((v) << 12) & 0x1000)
-#define BP_POWER_STS_CHRGSTS                11
-#define BM_POWER_STS_CHRGSTS                0x800
-#define BF_POWER_STS_CHRGSTS(v)             (((v) << 11) & 0x800)
-#define BP_POWER_STS_DCDC_4P2_BO            10
-#define BM_POWER_STS_DCDC_4P2_BO            0x400
-#define BF_POWER_STS_DCDC_4P2_BO(v)         (((v) << 10) & 0x400)
-#define BP_POWER_STS_DC_OK                  9
-#define BM_POWER_STS_DC_OK                  0x200
-#define BF_POWER_STS_DC_OK(v)               (((v) << 9) & 0x200)
-#define BP_POWER_STS_VDDIO_BO               8
-#define BM_POWER_STS_VDDIO_BO               0x100
-#define BF_POWER_STS_VDDIO_BO(v)            (((v) << 8) & 0x100)
-#define BP_POWER_STS_VDDA_BO                7
-#define BM_POWER_STS_VDDA_BO                0x80
-#define BF_POWER_STS_VDDA_BO(v)             (((v) << 7) & 0x80)
-#define BP_POWER_STS_VDDD_BO                6
-#define BM_POWER_STS_VDDD_BO                0x40
-#define BF_POWER_STS_VDDD_BO(v)             (((v) << 6) & 0x40)
-#define BP_POWER_STS_VDD5V_GT_VDDIO         5
-#define BM_POWER_STS_VDD5V_GT_VDDIO         0x20
-#define BF_POWER_STS_VDD5V_GT_VDDIO(v)      (((v) << 5) & 0x20)
-#define BP_POWER_STS_VDD5V_DROOP            4
-#define BM_POWER_STS_VDD5V_DROOP            0x10
-#define BF_POWER_STS_VDD5V_DROOP(v)         (((v) << 4) & 0x10)
-#define BP_POWER_STS_AVALID                 3
-#define BM_POWER_STS_AVALID                 0x8
-#define BF_POWER_STS_AVALID(v)              (((v) << 3) & 0x8)
-#define BP_POWER_STS_BVALID                 2
-#define BM_POWER_STS_BVALID                 0x4
-#define BF_POWER_STS_BVALID(v)              (((v) << 2) & 0x4)
-#define BP_POWER_STS_VBUSVALID              1
-#define BM_POWER_STS_VBUSVALID              0x2
-#define BF_POWER_STS_VBUSVALID(v)           (((v) << 1) & 0x2)
-#define BP_POWER_STS_SESSEND                0
-#define BM_POWER_STS_SESSEND                0x1
-#define BF_POWER_STS_SESSEND(v)             (((v) << 0) & 0x1)
-
-/**
- * Register: HW_POWER_SPEED
- * Address: 0xd0
- * SCT: yes
-*/
-#define HW_POWER_SPEED              (*(volatile unsigned long *)(REGS_POWER_BASE + 0xd0 + 0x0))
-#define HW_POWER_SPEED_SET          (*(volatile unsigned long *)(REGS_POWER_BASE + 0xd0 + 0x4))
-#define HW_POWER_SPEED_CLR          (*(volatile unsigned long *)(REGS_POWER_BASE + 0xd0 + 0x8))
-#define HW_POWER_SPEED_TOG          (*(volatile unsigned long *)(REGS_POWER_BASE + 0xd0 + 0xc))
-#define BP_POWER_SPEED_RSRVD1       24
-#define BM_POWER_SPEED_RSRVD1       0xff000000
-#define BF_POWER_SPEED_RSRVD1(v)    (((v) << 24) & 0xff000000)
-#define BP_POWER_SPEED_STATUS       16
-#define BM_POWER_SPEED_STATUS       0xff0000
-#define BF_POWER_SPEED_STATUS(v)    (((v) << 16) & 0xff0000)
-#define BP_POWER_SPEED_RSRVD0       2
-#define BM_POWER_SPEED_RSRVD0       0xfffc
-#define BF_POWER_SPEED_RSRVD0(v)    (((v) << 2) & 0xfffc)
-#define BP_POWER_SPEED_CTRL         0
-#define BM_POWER_SPEED_CTRL         0x3
-#define BF_POWER_SPEED_CTRL(v)      (((v) << 0) & 0x3)
-
-/**
- * Register: HW_POWER_BATTMONITOR
- * Address: 0xe0
- * SCT: no
-*/
-#define HW_POWER_BATTMONITOR                    (*(volatile unsigned long *)(REGS_POWER_BASE + 0xe0))
-#define BP_POWER_BATTMONITOR_RSRVD3             26
-#define BM_POWER_BATTMONITOR_RSRVD3             0xfc000000
-#define BF_POWER_BATTMONITOR_RSRVD3(v)          (((v) << 26) & 0xfc000000)
-#define BP_POWER_BATTMONITOR_BATT_VAL           16
-#define BM_POWER_BATTMONITOR_BATT_VAL           0x3ff0000
-#define BF_POWER_BATTMONITOR_BATT_VAL(v)        (((v) << 16) & 0x3ff0000)
-#define BP_POWER_BATTMONITOR_RSRVD2             11
-#define BM_POWER_BATTMONITOR_RSRVD2             0xf800
-#define BF_POWER_BATTMONITOR_RSRVD2(v)          (((v) << 11) & 0xf800)
-#define BP_POWER_BATTMONITOR_EN_BATADJ          10
-#define BM_POWER_BATTMONITOR_EN_BATADJ          0x400
-#define BF_POWER_BATTMONITOR_EN_BATADJ(v)       (((v) << 10) & 0x400)
-#define BP_POWER_BATTMONITOR_PWDN_BATTBRNOUT    9
-#define BM_POWER_BATTMONITOR_PWDN_BATTBRNOUT    0x200
-#define BF_POWER_BATTMONITOR_PWDN_BATTBRNOUT(v) (((v) << 9) & 0x200)
-#define BP_POWER_BATTMONITOR_BRWNOUT_PWD        8
-#define BM_POWER_BATTMONITOR_BRWNOUT_PWD        0x100
-#define BF_POWER_BATTMONITOR_BRWNOUT_PWD(v)     (((v) << 8) & 0x100)
-#define BP_POWER_BATTMONITOR_RSRVD1             5
-#define BM_POWER_BATTMONITOR_RSRVD1             0xe0
-#define BF_POWER_BATTMONITOR_RSRVD1(v)          (((v) << 5) & 0xe0)
-#define BP_POWER_BATTMONITOR_BRWNOUT_LVL        0
-#define BM_POWER_BATTMONITOR_BRWNOUT_LVL        0x1f
-#define BF_POWER_BATTMONITOR_BRWNOUT_LVL(v)     (((v) << 0) & 0x1f)
-
-/**
- * Register: HW_POWER_RESET
- * Address: 0x100
- * SCT: yes
-*/
-#define HW_POWER_RESET              (*(volatile unsigned long *)(REGS_POWER_BASE + 0x100 + 0x0))
-#define HW_POWER_RESET_SET          (*(volatile unsigned long *)(REGS_POWER_BASE + 0x100 + 0x4))
-#define HW_POWER_RESET_CLR          (*(volatile unsigned long *)(REGS_POWER_BASE + 0x100 + 0x8))
-#define HW_POWER_RESET_TOG          (*(volatile unsigned long *)(REGS_POWER_BASE + 0x100 + 0xc))
-#define BP_POWER_RESET_UNLOCK       16
-#define BM_POWER_RESET_UNLOCK       0xffff0000
-#define BV_POWER_RESET_UNLOCK__KEY  0x3e77
-#define BF_POWER_RESET_UNLOCK(v)    (((v) << 16) & 0xffff0000)
-#define BF_POWER_RESET_UNLOCK_V(v)  ((BV_POWER_RESET_UNLOCK__##v << 16) & 0xffff0000)
-#define BP_POWER_RESET_RSRVD1       2
-#define BM_POWER_RESET_RSRVD1       0xfffc
-#define BF_POWER_RESET_RSRVD1(v)    (((v) << 2) & 0xfffc)
-#define BP_POWER_RESET_PWD_OFF      1
-#define BM_POWER_RESET_PWD_OFF      0x2
-#define BF_POWER_RESET_PWD_OFF(v)   (((v) << 1) & 0x2)
-#define BP_POWER_RESET_PWD          0
-#define BM_POWER_RESET_PWD          0x1
-#define BF_POWER_RESET_PWD(v)       (((v) << 0) & 0x1)
-
-/**
- * Register: HW_POWER_DEBUG
- * Address: 0x110
- * SCT: yes
-*/
-#define HW_POWER_DEBUG                      (*(volatile unsigned long *)(REGS_POWER_BASE + 0x110 + 0x0))
-#define HW_POWER_DEBUG_SET                  (*(volatile unsigned long *)(REGS_POWER_BASE + 0x110 + 0x4))
-#define HW_POWER_DEBUG_CLR                  (*(volatile unsigned long *)(REGS_POWER_BASE + 0x110 + 0x8))
-#define HW_POWER_DEBUG_TOG                  (*(volatile unsigned long *)(REGS_POWER_BASE + 0x110 + 0xc))
-#define BP_POWER_DEBUG_RSRVD0               4
-#define BM_POWER_DEBUG_RSRVD0               0xfffffff0
-#define BF_POWER_DEBUG_RSRVD0(v)            (((v) << 4) & 0xfffffff0)
-#define BP_POWER_DEBUG_VBUSVALIDPIOLOCK     3
-#define BM_POWER_DEBUG_VBUSVALIDPIOLOCK     0x8
-#define BF_POWER_DEBUG_VBUSVALIDPIOLOCK(v)  (((v) << 3) & 0x8)
-#define BP_POWER_DEBUG_AVALIDPIOLOCK        2
-#define BM_POWER_DEBUG_AVALIDPIOLOCK        0x4
-#define BF_POWER_DEBUG_AVALIDPIOLOCK(v)     (((v) << 2) & 0x4)
-#define BP_POWER_DEBUG_BVALIDPIOLOCK        1
-#define BM_POWER_DEBUG_BVALIDPIOLOCK        0x2
-#define BF_POWER_DEBUG_BVALIDPIOLOCK(v)     (((v) << 1) & 0x2)
-#define BP_POWER_DEBUG_SESSENDPIOLOCK       0
-#define BM_POWER_DEBUG_SESSENDPIOLOCK       0x1
-#define BF_POWER_DEBUG_SESSENDPIOLOCK(v)    (((v) << 0) & 0x1)
-
-/**
- * Register: HW_POWER_SPECIAL
- * Address: 0x120
- * SCT: yes
-*/
-#define HW_POWER_SPECIAL            (*(volatile unsigned long *)(REGS_POWER_BASE + 0x120 + 0x0))
-#define HW_POWER_SPECIAL_SET        (*(volatile unsigned long *)(REGS_POWER_BASE + 0x120 + 0x4))
-#define HW_POWER_SPECIAL_CLR        (*(volatile unsigned long *)(REGS_POWER_BASE + 0x120 + 0x8))
-#define HW_POWER_SPECIAL_TOG        (*(volatile unsigned long *)(REGS_POWER_BASE + 0x120 + 0xc))
-#define BP_POWER_SPECIAL_TEST       0
-#define BM_POWER_SPECIAL_TEST       0xffffffff
-#define BF_POWER_SPECIAL_TEST(v)    (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_POWER_VERSION
- * Address: 0x130
- * SCT: no
-*/
-#define HW_POWER_VERSION            (*(volatile unsigned long *)(REGS_POWER_BASE + 0x130))
-#define BP_POWER_VERSION_MAJOR      24
-#define BM_POWER_VERSION_MAJOR      0xff000000
-#define BF_POWER_VERSION_MAJOR(v)   (((v) << 24) & 0xff000000)
-#define BP_POWER_VERSION_MINOR      16
-#define BM_POWER_VERSION_MINOR      0xff0000
-#define BF_POWER_VERSION_MINOR(v)   (((v) << 16) & 0xff0000)
-#define BP_POWER_VERSION_STEP       0
-#define BM_POWER_VERSION_STEP       0xffff
-#define BF_POWER_VERSION_STEP(v)    (((v) << 0) & 0xffff)
-
-#endif /* __HEADERGEN__IMX233__POWER__H__ */
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-pwm.h b/firmware/target/arm/imx233/regs/imx233/regs-pwm.h
deleted file mode 100644
index 52a6a68527..0000000000
--- a/firmware/target/arm/imx233/regs/imx233/regs-pwm.h
+++ /dev/null
@@ -1,165 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: imx233:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__IMX233__PWM__H__
-#define __HEADERGEN__IMX233__PWM__H__
-
-#define REGS_PWM_BASE (0x80064000)
-
-#define REGS_PWM_VERSION "3.2.0"
-
-/**
- * Register: HW_PWM_CTRL
- * Address: 0
- * SCT: yes
-*/
-#define HW_PWM_CTRL                         (*(volatile unsigned long *)(REGS_PWM_BASE + 0x0 + 0x0))
-#define HW_PWM_CTRL_SET                     (*(volatile unsigned long *)(REGS_PWM_BASE + 0x0 + 0x4))
-#define HW_PWM_CTRL_CLR                     (*(volatile unsigned long *)(REGS_PWM_BASE + 0x0 + 0x8))
-#define HW_PWM_CTRL_TOG                     (*(volatile unsigned long *)(REGS_PWM_BASE + 0x0 + 0xc))
-#define BP_PWM_CTRL_SFTRST                  31
-#define BM_PWM_CTRL_SFTRST                  0x80000000
-#define BF_PWM_CTRL_SFTRST(v)               (((v) << 31) & 0x80000000)
-#define BP_PWM_CTRL_CLKGATE                 30
-#define BM_PWM_CTRL_CLKGATE                 0x40000000
-#define BF_PWM_CTRL_CLKGATE(v)              (((v) << 30) & 0x40000000)
-#define BP_PWM_CTRL_PWM4_PRESENT            29
-#define BM_PWM_CTRL_PWM4_PRESENT            0x20000000
-#define BF_PWM_CTRL_PWM4_PRESENT(v)         (((v) << 29) & 0x20000000)
-#define BP_PWM_CTRL_PWM3_PRESENT            28
-#define BM_PWM_CTRL_PWM3_PRESENT            0x10000000
-#define BF_PWM_CTRL_PWM3_PRESENT(v)         (((v) << 28) & 0x10000000)
-#define BP_PWM_CTRL_PWM2_PRESENT            27
-#define BM_PWM_CTRL_PWM2_PRESENT            0x8000000
-#define BF_PWM_CTRL_PWM2_PRESENT(v)         (((v) << 27) & 0x8000000)
-#define BP_PWM_CTRL_PWM1_PRESENT            26
-#define BM_PWM_CTRL_PWM1_PRESENT            0x4000000
-#define BF_PWM_CTRL_PWM1_PRESENT(v)         (((v) << 26) & 0x4000000)
-#define BP_PWM_CTRL_PWM0_PRESENT            25
-#define BM_PWM_CTRL_PWM0_PRESENT            0x2000000
-#define BF_PWM_CTRL_PWM0_PRESENT(v)         (((v) << 25) & 0x2000000)
-#define BP_PWM_CTRL_RSRVD1                  7
-#define BM_PWM_CTRL_RSRVD1                  0x1ffff80
-#define BF_PWM_CTRL_RSRVD1(v)               (((v) << 7) & 0x1ffff80)
-#define BP_PWM_CTRL_OUTPUT_CUTOFF_EN        6
-#define BM_PWM_CTRL_OUTPUT_CUTOFF_EN        0x40
-#define BF_PWM_CTRL_OUTPUT_CUTOFF_EN(v)     (((v) << 6) & 0x40)
-#define BP_PWM_CTRL_PWM2_ANA_CTRL_ENABLE    5
-#define BM_PWM_CTRL_PWM2_ANA_CTRL_ENABLE    0x20
-#define BF_PWM_CTRL_PWM2_ANA_CTRL_ENABLE(v) (((v) << 5) & 0x20)
-#define BP_PWM_CTRL_PWM4_ENABLE             4
-#define BM_PWM_CTRL_PWM4_ENABLE             0x10
-#define BF_PWM_CTRL_PWM4_ENABLE(v)          (((v) << 4) & 0x10)
-#define BP_PWM_CTRL_PWM3_ENABLE             3
-#define BM_PWM_CTRL_PWM3_ENABLE             0x8
-#define BF_PWM_CTRL_PWM3_ENABLE(v)          (((v) << 3) & 0x8)
-#define BP_PWM_CTRL_PWM2_ENABLE             2
-#define BM_PWM_CTRL_PWM2_ENABLE             0x4
-#define BF_PWM_CTRL_PWM2_ENABLE(v)          (((v) << 2) & 0x4)
-#define BP_PWM_CTRL_PWM1_ENABLE             1
-#define BM_PWM_CTRL_PWM1_ENABLE             0x2
-#define BF_PWM_CTRL_PWM1_ENABLE(v)          (((v) << 1) & 0x2)
-#define BP_PWM_CTRL_PWM0_ENABLE             0
-#define BM_PWM_CTRL_PWM0_ENABLE             0x1
-#define BF_PWM_CTRL_PWM0_ENABLE(v)          (((v) << 0) & 0x1)
-
-/**
- * Register: HW_PWM_ACTIVEn
- * Address: 0x10+n*0x20
- * SCT: yes
-*/
-#define HW_PWM_ACTIVEn(n)           (*(volatile unsigned long *)(REGS_PWM_BASE + 0x10+(n)*0x20 + 0x0))
-#define HW_PWM_ACTIVEn_SET(n)       (*(volatile unsigned long *)(REGS_PWM_BASE + 0x10+(n)*0x20 + 0x4))
-#define HW_PWM_ACTIVEn_CLR(n)       (*(volatile unsigned long *)(REGS_PWM_BASE + 0x10+(n)*0x20 + 0x8))
-#define HW_PWM_ACTIVEn_TOG(n)       (*(volatile unsigned long *)(REGS_PWM_BASE + 0x10+(n)*0x20 + 0xc))
-#define BP_PWM_ACTIVEn_INACTIVE     16
-#define BM_PWM_ACTIVEn_INACTIVE     0xffff0000
-#define BF_PWM_ACTIVEn_INACTIVE(v)  (((v) << 16) & 0xffff0000)
-#define BP_PWM_ACTIVEn_ACTIVE       0
-#define BM_PWM_ACTIVEn_ACTIVE       0xffff
-#define BF_PWM_ACTIVEn_ACTIVE(v)    (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_PWM_PERIODn
- * Address: 0x20+n*0x20
- * SCT: yes
-*/
-#define HW_PWM_PERIODn(n)                   (*(volatile unsigned long *)(REGS_PWM_BASE + 0x20+(n)*0x20 + 0x0))
-#define HW_PWM_PERIODn_SET(n)               (*(volatile unsigned long *)(REGS_PWM_BASE + 0x20+(n)*0x20 + 0x4))
-#define HW_PWM_PERIODn_CLR(n)               (*(volatile unsigned long *)(REGS_PWM_BASE + 0x20+(n)*0x20 + 0x8))
-#define HW_PWM_PERIODn_TOG(n)               (*(volatile unsigned long *)(REGS_PWM_BASE + 0x20+(n)*0x20 + 0xc))
-#define BP_PWM_PERIODn_RSRVD2               25
-#define BM_PWM_PERIODn_RSRVD2               0xfe000000
-#define BF_PWM_PERIODn_RSRVD2(v)            (((v) << 25) & 0xfe000000)
-#define BP_PWM_PERIODn_MATT_SEL             24
-#define BM_PWM_PERIODn_MATT_SEL             0x1000000
-#define BF_PWM_PERIODn_MATT_SEL(v)          (((v) << 24) & 0x1000000)
-#define BP_PWM_PERIODn_MATT                 23
-#define BM_PWM_PERIODn_MATT                 0x800000
-#define BF_PWM_PERIODn_MATT(v)              (((v) << 23) & 0x800000)
-#define BP_PWM_PERIODn_CDIV                 20
-#define BM_PWM_PERIODn_CDIV                 0x700000
-#define BV_PWM_PERIODn_CDIV__DIV_1          0x0
-#define BV_PWM_PERIODn_CDIV__DIV_2          0x1
-#define BV_PWM_PERIODn_CDIV__DIV_4          0x2
-#define BV_PWM_PERIODn_CDIV__DIV_8          0x3
-#define BV_PWM_PERIODn_CDIV__DIV_16         0x4
-#define BV_PWM_PERIODn_CDIV__DIV_64         0x5
-#define BV_PWM_PERIODn_CDIV__DIV_256        0x6
-#define BV_PWM_PERIODn_CDIV__DIV_1024       0x7
-#define BF_PWM_PERIODn_CDIV(v)              (((v) << 20) & 0x700000)
-#define BF_PWM_PERIODn_CDIV_V(v)            ((BV_PWM_PERIODn_CDIV__##v << 20) & 0x700000)
-#define BP_PWM_PERIODn_INACTIVE_STATE       18
-#define BM_PWM_PERIODn_INACTIVE_STATE       0xc0000
-#define BV_PWM_PERIODn_INACTIVE_STATE__HI_Z 0x0
-#define BV_PWM_PERIODn_INACTIVE_STATE__0    0x2
-#define BV_PWM_PERIODn_INACTIVE_STATE__1    0x3
-#define BF_PWM_PERIODn_INACTIVE_STATE(v)    (((v) << 18) & 0xc0000)
-#define BF_PWM_PERIODn_INACTIVE_STATE_V(v)  ((BV_PWM_PERIODn_INACTIVE_STATE__##v << 18) & 0xc0000)
-#define BP_PWM_PERIODn_ACTIVE_STATE         16
-#define BM_PWM_PERIODn_ACTIVE_STATE         0x30000
-#define BV_PWM_PERIODn_ACTIVE_STATE__HI_Z   0x0
-#define BV_PWM_PERIODn_ACTIVE_STATE__0      0x2
-#define BV_PWM_PERIODn_ACTIVE_STATE__1      0x3
-#define BF_PWM_PERIODn_ACTIVE_STATE(v)      (((v) << 16) & 0x30000)
-#define BF_PWM_PERIODn_ACTIVE_STATE_V(v)    ((BV_PWM_PERIODn_ACTIVE_STATE__##v << 16) & 0x30000)
-#define BP_PWM_PERIODn_PERIOD               0
-#define BM_PWM_PERIODn_PERIOD               0xffff
-#define BF_PWM_PERIODn_PERIOD(v)            (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_PWM_VERSION
- * Address: 0xb0
- * SCT: no
-*/
-#define HW_PWM_VERSION          (*(volatile unsigned long *)(REGS_PWM_BASE + 0xb0))
-#define BP_PWM_VERSION_MAJOR    24
-#define BM_PWM_VERSION_MAJOR    0xff000000
-#define BF_PWM_VERSION_MAJOR(v) (((v) << 24) & 0xff000000)
-#define BP_PWM_VERSION_MINOR    16
-#define BM_PWM_VERSION_MINOR    0xff0000
-#define BF_PWM_VERSION_MINOR(v) (((v) << 16) & 0xff0000)
-#define BP_PWM_VERSION_STEP     0
-#define BM_PWM_VERSION_STEP     0xffff
-#define BF_PWM_VERSION_STEP(v)  (((v) << 0) & 0xffff)
-
-#endif /* __HEADERGEN__IMX233__PWM__H__ */
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-pxp.h b/firmware/target/arm/imx233/regs/imx233/regs-pxp.h
deleted file mode 100644
index d39125834a..0000000000
--- a/firmware/target/arm/imx233/regs/imx233/regs-pxp.h
+++ /dev/null
@@ -1,612 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: imx233:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__IMX233__PXP__H__
-#define __HEADERGEN__IMX233__PXP__H__
-
-#define REGS_PXP_BASE (0x8002a000)
-
-#define REGS_PXP_VERSION "3.2.0"
-
-/**
- * Register: HW_PXP_CTRL
- * Address: 0
- * SCT: yes
-*/
-#define HW_PXP_CTRL                                 (*(volatile unsigned long *)(REGS_PXP_BASE + 0x0 + 0x0))
-#define HW_PXP_CTRL_SET                             (*(volatile unsigned long *)(REGS_PXP_BASE + 0x0 + 0x4))
-#define HW_PXP_CTRL_CLR                             (*(volatile unsigned long *)(REGS_PXP_BASE + 0x0 + 0x8))
-#define HW_PXP_CTRL_TOG                             (*(volatile unsigned long *)(REGS_PXP_BASE + 0x0 + 0xc))
-#define BP_PXP_CTRL_SFTRST                          31
-#define BM_PXP_CTRL_SFTRST                          0x80000000
-#define BF_PXP_CTRL_SFTRST(v)                       (((v) << 31) & 0x80000000)
-#define BP_PXP_CTRL_CLKGATE                         30
-#define BM_PXP_CTRL_CLKGATE                         0x40000000
-#define BF_PXP_CTRL_CLKGATE(v)                      (((v) << 30) & 0x40000000)
-#define BP_PXP_CTRL_RSVD2                           28
-#define BM_PXP_CTRL_RSVD2                           0x30000000
-#define BF_PXP_CTRL_RSVD2(v)                        (((v) << 28) & 0x30000000)
-#define BP_PXP_CTRL_INTERLACED_OUTPUT               26
-#define BM_PXP_CTRL_INTERLACED_OUTPUT               0xc000000
-#define BV_PXP_CTRL_INTERLACED_OUTPUT__PROGRESSIVE  0x0
-#define BV_PXP_CTRL_INTERLACED_OUTPUT__FIELD0       0x1
-#define BV_PXP_CTRL_INTERLACED_OUTPUT__FIELD1       0x2
-#define BV_PXP_CTRL_INTERLACED_OUTPUT__INTERLACED   0x3
-#define BF_PXP_CTRL_INTERLACED_OUTPUT(v)            (((v) << 26) & 0xc000000)
-#define BF_PXP_CTRL_INTERLACED_OUTPUT_V(v)          ((BV_PXP_CTRL_INTERLACED_OUTPUT__##v << 26) & 0xc000000)
-#define BP_PXP_CTRL_INTERLACED_INPUT                24
-#define BM_PXP_CTRL_INTERLACED_INPUT                0x3000000
-#define BV_PXP_CTRL_INTERLACED_INPUT__PROGRESSIVE   0x0
-#define BV_PXP_CTRL_INTERLACED_INPUT__FIELD0        0x2
-#define BV_PXP_CTRL_INTERLACED_INPUT__FIELD1        0x3
-#define BF_PXP_CTRL_INTERLACED_INPUT(v)             (((v) << 24) & 0x3000000)
-#define BF_PXP_CTRL_INTERLACED_INPUT_V(v)           ((BV_PXP_CTRL_INTERLACED_INPUT__##v << 24) & 0x3000000)
-#define BP_PXP_CTRL_RSVD1                           23
-#define BM_PXP_CTRL_RSVD1                           0x800000
-#define BF_PXP_CTRL_RSVD1(v)                        (((v) << 23) & 0x800000)
-#define BP_PXP_CTRL_ALPHA_OUTPUT                    22
-#define BM_PXP_CTRL_ALPHA_OUTPUT                    0x400000
-#define BF_PXP_CTRL_ALPHA_OUTPUT(v)                 (((v) << 22) & 0x400000)
-#define BP_PXP_CTRL_IN_PLACE                        21
-#define BM_PXP_CTRL_IN_PLACE                        0x200000
-#define BF_PXP_CTRL_IN_PLACE(v)                     (((v) << 21) & 0x200000)
-#define BP_PXP_CTRL_DELTA                           20
-#define BM_PXP_CTRL_DELTA                           0x100000
-#define BF_PXP_CTRL_DELTA(v)                        (((v) << 20) & 0x100000)
-#define BP_PXP_CTRL_CROP                            19
-#define BM_PXP_CTRL_CROP                            0x80000
-#define BF_PXP_CTRL_CROP(v)                         (((v) << 19) & 0x80000)
-#define BP_PXP_CTRL_SCALE                           18
-#define BM_PXP_CTRL_SCALE                           0x40000
-#define BF_PXP_CTRL_SCALE(v)                        (((v) << 18) & 0x40000)
-#define BP_PXP_CTRL_UPSAMPLE                        17
-#define BM_PXP_CTRL_UPSAMPLE                        0x20000
-#define BF_PXP_CTRL_UPSAMPLE(v)                     (((v) << 17) & 0x20000)
-#define BP_PXP_CTRL_SUBSAMPLE                       16
-#define BM_PXP_CTRL_SUBSAMPLE                       0x10000
-#define BF_PXP_CTRL_SUBSAMPLE(v)                    (((v) << 16) & 0x10000)
-#define BP_PXP_CTRL_S0_FORMAT                       12
-#define BM_PXP_CTRL_S0_FORMAT                       0xf000
-#define BV_PXP_CTRL_S0_FORMAT__RGB888               0x1
-#define BV_PXP_CTRL_S0_FORMAT__RGB565               0x4
-#define BV_PXP_CTRL_S0_FORMAT__RGB555               0x5
-#define BV_PXP_CTRL_S0_FORMAT__YUV422               0x8
-#define BV_PXP_CTRL_S0_FORMAT__YUV420               0x9
-#define BF_PXP_CTRL_S0_FORMAT(v)                    (((v) << 12) & 0xf000)
-#define BF_PXP_CTRL_S0_FORMAT_V(v)                  ((BV_PXP_CTRL_S0_FORMAT__##v << 12) & 0xf000)
-#define BP_PXP_CTRL_VFLIP                           11
-#define BM_PXP_CTRL_VFLIP                           0x800
-#define BF_PXP_CTRL_VFLIP(v)                        (((v) << 11) & 0x800)
-#define BP_PXP_CTRL_HFLIP                           10
-#define BM_PXP_CTRL_HFLIP                           0x400
-#define BF_PXP_CTRL_HFLIP(v)                        (((v) << 10) & 0x400)
-#define BP_PXP_CTRL_ROTATE                          8
-#define BM_PXP_CTRL_ROTATE                          0x300
-#define BV_PXP_CTRL_ROTATE__ROT_0                   0x0
-#define BV_PXP_CTRL_ROTATE__ROT_90                  0x1
-#define BV_PXP_CTRL_ROTATE__ROT_180                 0x2
-#define BV_PXP_CTRL_ROTATE__ROT_270                 0x3
-#define BF_PXP_CTRL_ROTATE(v)                       (((v) << 8) & 0x300)
-#define BF_PXP_CTRL_ROTATE_V(v)                     ((BV_PXP_CTRL_ROTATE__##v << 8) & 0x300)
-#define BP_PXP_CTRL_OUTPUT_RGB_FORMAT               4
-#define BM_PXP_CTRL_OUTPUT_RGB_FORMAT               0xf0
-#define BV_PXP_CTRL_OUTPUT_RGB_FORMAT__ARGB8888     0x0
-#define BV_PXP_CTRL_OUTPUT_RGB_FORMAT__RGB888       0x1
-#define BV_PXP_CTRL_OUTPUT_RGB_FORMAT__RGB888P      0x2
-#define BV_PXP_CTRL_OUTPUT_RGB_FORMAT__ARGB1555     0x3
-#define BV_PXP_CTRL_OUTPUT_RGB_FORMAT__RGB565       0x4
-#define BV_PXP_CTRL_OUTPUT_RGB_FORMAT__RGB555       0x5
-#define BF_PXP_CTRL_OUTPUT_RGB_FORMAT(v)            (((v) << 4) & 0xf0)
-#define BF_PXP_CTRL_OUTPUT_RGB_FORMAT_V(v)          ((BV_PXP_CTRL_OUTPUT_RGB_FORMAT__##v << 4) & 0xf0)
-#define BP_PXP_CTRL_RSVD0                           3
-#define BM_PXP_CTRL_RSVD0                           0x8
-#define BF_PXP_CTRL_RSVD0(v)                        (((v) << 3) & 0x8)
-#define BP_PXP_CTRL_ENABLE_LCD_HANDSHAKE            2
-#define BM_PXP_CTRL_ENABLE_LCD_HANDSHAKE            0x4
-#define BF_PXP_CTRL_ENABLE_LCD_HANDSHAKE(v)         (((v) << 2) & 0x4)
-#define BP_PXP_CTRL_IRQ_ENABLE                      1
-#define BM_PXP_CTRL_IRQ_ENABLE                      0x2
-#define BF_PXP_CTRL_IRQ_ENABLE(v)                   (((v) << 1) & 0x2)
-#define BP_PXP_CTRL_ENABLE                          0
-#define BM_PXP_CTRL_ENABLE                          0x1
-#define BF_PXP_CTRL_ENABLE(v)                       (((v) << 0) & 0x1)
-
-/**
- * Register: HW_PXP_STAT
- * Address: 0x10
- * SCT: yes
-*/
-#define HW_PXP_STAT                     (*(volatile unsigned long *)(REGS_PXP_BASE + 0x10 + 0x0))
-#define HW_PXP_STAT_SET                 (*(volatile unsigned long *)(REGS_PXP_BASE + 0x10 + 0x4))
-#define HW_PXP_STAT_CLR                 (*(volatile unsigned long *)(REGS_PXP_BASE + 0x10 + 0x8))
-#define HW_PXP_STAT_TOG                 (*(volatile unsigned long *)(REGS_PXP_BASE + 0x10 + 0xc))
-#define BP_PXP_STAT_BLOCKX              24
-#define BM_PXP_STAT_BLOCKX              0xff000000
-#define BF_PXP_STAT_BLOCKX(v)           (((v) << 24) & 0xff000000)
-#define BP_PXP_STAT_BLOCKY              16
-#define BM_PXP_STAT_BLOCKY              0xff0000
-#define BF_PXP_STAT_BLOCKY(v)           (((v) << 16) & 0xff0000)
-#define BP_PXP_STAT_RSVD2               8
-#define BM_PXP_STAT_RSVD2               0xff00
-#define BF_PXP_STAT_RSVD2(v)            (((v) << 8) & 0xff00)
-#define BP_PXP_STAT_AXI_ERROR_ID        4
-#define BM_PXP_STAT_AXI_ERROR_ID        0xf0
-#define BF_PXP_STAT_AXI_ERROR_ID(v)     (((v) << 4) & 0xf0)
-#define BP_PXP_STAT_RSVD1               3
-#define BM_PXP_STAT_RSVD1               0x8
-#define BF_PXP_STAT_RSVD1(v)            (((v) << 3) & 0x8)
-#define BP_PXP_STAT_AXI_READ_ERROR      2
-#define BM_PXP_STAT_AXI_READ_ERROR      0x4
-#define BF_PXP_STAT_AXI_READ_ERROR(v)   (((v) << 2) & 0x4)
-#define BP_PXP_STAT_AXI_WRITE_ERROR     1
-#define BM_PXP_STAT_AXI_WRITE_ERROR     0x2
-#define BF_PXP_STAT_AXI_WRITE_ERROR(v)  (((v) << 1) & 0x2)
-#define BP_PXP_STAT_IRQ                 0
-#define BM_PXP_STAT_IRQ                 0x1
-#define BF_PXP_STAT_IRQ(v)              (((v) << 0) & 0x1)
-
-/**
- * Register: HW_PXP_RGBBUF
- * Address: 0x20
- * SCT: no
-*/
-#define HW_PXP_RGBBUF           (*(volatile unsigned long *)(REGS_PXP_BASE + 0x20))
-#define BP_PXP_RGBBUF_ADDR      0
-#define BM_PXP_RGBBUF_ADDR      0xffffffff
-#define BF_PXP_RGBBUF_ADDR(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_PXP_RGBBUF2
- * Address: 0x30
- * SCT: no
-*/
-#define HW_PXP_RGBBUF2          (*(volatile unsigned long *)(REGS_PXP_BASE + 0x30))
-#define BP_PXP_RGBBUF2_ADDR     0
-#define BM_PXP_RGBBUF2_ADDR     0xffffffff
-#define BF_PXP_RGBBUF2_ADDR(v)  (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_PXP_RGBSIZE
- * Address: 0x40
- * SCT: no
-*/
-#define HW_PXP_RGBSIZE              (*(volatile unsigned long *)(REGS_PXP_BASE + 0x40))
-#define BP_PXP_RGBSIZE_ALPHA        24
-#define BM_PXP_RGBSIZE_ALPHA        0xff000000
-#define BF_PXP_RGBSIZE_ALPHA(v)     (((v) << 24) & 0xff000000)
-#define BP_PXP_RGBSIZE_WIDTH        12
-#define BM_PXP_RGBSIZE_WIDTH        0xfff000
-#define BF_PXP_RGBSIZE_WIDTH(v)     (((v) << 12) & 0xfff000)
-#define BP_PXP_RGBSIZE_HEIGHT       0
-#define BM_PXP_RGBSIZE_HEIGHT       0xfff
-#define BF_PXP_RGBSIZE_HEIGHT(v)    (((v) << 0) & 0xfff)
-
-/**
- * Register: HW_PXP_S0BUF
- * Address: 0x50
- * SCT: no
-*/
-#define HW_PXP_S0BUF            (*(volatile unsigned long *)(REGS_PXP_BASE + 0x50))
-#define BP_PXP_S0BUF_ADDR       0
-#define BM_PXP_S0BUF_ADDR       0xffffffff
-#define BF_PXP_S0BUF_ADDR(v)    (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_PXP_S0UBUF
- * Address: 0x60
- * SCT: no
-*/
-#define HW_PXP_S0UBUF           (*(volatile unsigned long *)(REGS_PXP_BASE + 0x60))
-#define BP_PXP_S0UBUF_ADDR      0
-#define BM_PXP_S0UBUF_ADDR      0xffffffff
-#define BF_PXP_S0UBUF_ADDR(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_PXP_S0VBUF
- * Address: 0x70
- * SCT: no
-*/
-#define HW_PXP_S0VBUF           (*(volatile unsigned long *)(REGS_PXP_BASE + 0x70))
-#define BP_PXP_S0VBUF_ADDR      0
-#define BM_PXP_S0VBUF_ADDR      0xffffffff
-#define BF_PXP_S0VBUF_ADDR(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_PXP_S0PARAM
- * Address: 0x80
- * SCT: no
-*/
-#define HW_PXP_S0PARAM              (*(volatile unsigned long *)(REGS_PXP_BASE + 0x80))
-#define BP_PXP_S0PARAM_XBASE        24
-#define BM_PXP_S0PARAM_XBASE        0xff000000
-#define BF_PXP_S0PARAM_XBASE(v)     (((v) << 24) & 0xff000000)
-#define BP_PXP_S0PARAM_YBASE        16
-#define BM_PXP_S0PARAM_YBASE        0xff0000
-#define BF_PXP_S0PARAM_YBASE(v)     (((v) << 16) & 0xff0000)
-#define BP_PXP_S0PARAM_WIDTH        8
-#define BM_PXP_S0PARAM_WIDTH        0xff00
-#define BF_PXP_S0PARAM_WIDTH(v)     (((v) << 8) & 0xff00)
-#define BP_PXP_S0PARAM_HEIGHT       0
-#define BM_PXP_S0PARAM_HEIGHT       0xff
-#define BF_PXP_S0PARAM_HEIGHT(v)    (((v) << 0) & 0xff)
-
-/**
- * Register: HW_PXP_S0BACKGROUND
- * Address: 0x90
- * SCT: no
-*/
-#define HW_PXP_S0BACKGROUND             (*(volatile unsigned long *)(REGS_PXP_BASE + 0x90))
-#define BP_PXP_S0BACKGROUND_COLOR       0
-#define BM_PXP_S0BACKGROUND_COLOR       0xffffffff
-#define BF_PXP_S0BACKGROUND_COLOR(v)    (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_PXP_S0CROP
- * Address: 0xa0
- * SCT: no
-*/
-#define HW_PXP_S0CROP           (*(volatile unsigned long *)(REGS_PXP_BASE + 0xa0))
-#define BP_PXP_S0CROP_XBASE     24
-#define BM_PXP_S0CROP_XBASE     0xff000000
-#define BF_PXP_S0CROP_XBASE(v)  (((v) << 24) & 0xff000000)
-#define BP_PXP_S0CROP_YBASE     16
-#define BM_PXP_S0CROP_YBASE     0xff0000
-#define BF_PXP_S0CROP_YBASE(v)  (((v) << 16) & 0xff0000)
-#define BP_PXP_S0CROP_WIDTH     8
-#define BM_PXP_S0CROP_WIDTH     0xff00
-#define BF_PXP_S0CROP_WIDTH(v)  (((v) << 8) & 0xff00)
-#define BP_PXP_S0CROP_HEIGHT    0
-#define BM_PXP_S0CROP_HEIGHT    0xff
-#define BF_PXP_S0CROP_HEIGHT(v) (((v) << 0) & 0xff)
-
-/**
- * Register: HW_PXP_S0SCALE
- * Address: 0xb0
- * SCT: no
-*/
-#define HW_PXP_S0SCALE              (*(volatile unsigned long *)(REGS_PXP_BASE + 0xb0))
-#define BP_PXP_S0SCALE_RSVD2        30
-#define BM_PXP_S0SCALE_RSVD2        0xc0000000
-#define BF_PXP_S0SCALE_RSVD2(v)     (((v) << 30) & 0xc0000000)
-#define BP_PXP_S0SCALE_YSCALE       16
-#define BM_PXP_S0SCALE_YSCALE       0x3fff0000
-#define BF_PXP_S0SCALE_YSCALE(v)    (((v) << 16) & 0x3fff0000)
-#define BP_PXP_S0SCALE_RSVD1        14
-#define BM_PXP_S0SCALE_RSVD1        0xc000
-#define BF_PXP_S0SCALE_RSVD1(v)     (((v) << 14) & 0xc000)
-#define BP_PXP_S0SCALE_XSCALE       0
-#define BM_PXP_S0SCALE_XSCALE       0x3fff
-#define BF_PXP_S0SCALE_XSCALE(v)    (((v) << 0) & 0x3fff)
-
-/**
- * Register: HW_PXP_S0OFFSET
- * Address: 0xc0
- * SCT: no
-*/
-#define HW_PXP_S0OFFSET             (*(volatile unsigned long *)(REGS_PXP_BASE + 0xc0))
-#define BP_PXP_S0OFFSET_RSVD2       28
-#define BM_PXP_S0OFFSET_RSVD2       0xf0000000
-#define BF_PXP_S0OFFSET_RSVD2(v)    (((v) << 28) & 0xf0000000)
-#define BP_PXP_S0OFFSET_YOFFSET     16
-#define BM_PXP_S0OFFSET_YOFFSET     0xfff0000
-#define BF_PXP_S0OFFSET_YOFFSET(v)  (((v) << 16) & 0xfff0000)
-#define BP_PXP_S0OFFSET_RSVD1       12
-#define BM_PXP_S0OFFSET_RSVD1       0xf000
-#define BF_PXP_S0OFFSET_RSVD1(v)    (((v) << 12) & 0xf000)
-#define BP_PXP_S0OFFSET_XOFFSET     0
-#define BM_PXP_S0OFFSET_XOFFSET     0xfff
-#define BF_PXP_S0OFFSET_XOFFSET(v)  (((v) << 0) & 0xfff)
-
-/**
- * Register: HW_PXP_CSCCOEFF0
- * Address: 0xd0
- * SCT: no
-*/
-#define HW_PXP_CSCCOEFF0                (*(volatile unsigned long *)(REGS_PXP_BASE + 0xd0))
-#define BP_PXP_CSCCOEFF0_YCBCR_MODE     31
-#define BM_PXP_CSCCOEFF0_YCBCR_MODE     0x80000000
-#define BF_PXP_CSCCOEFF0_YCBCR_MODE(v)  (((v) << 31) & 0x80000000)
-#define BP_PXP_CSCCOEFF0_RSVD1          29
-#define BM_PXP_CSCCOEFF0_RSVD1          0x60000000
-#define BF_PXP_CSCCOEFF0_RSVD1(v)       (((v) << 29) & 0x60000000)
-#define BP_PXP_CSCCOEFF0_C0             18
-#define BM_PXP_CSCCOEFF0_C0             0x1ffc0000
-#define BF_PXP_CSCCOEFF0_C0(v)          (((v) << 18) & 0x1ffc0000)
-#define BP_PXP_CSCCOEFF0_UV_OFFSET      9
-#define BM_PXP_CSCCOEFF0_UV_OFFSET      0x3fe00
-#define BF_PXP_CSCCOEFF0_UV_OFFSET(v)   (((v) << 9) & 0x3fe00)
-#define BP_PXP_CSCCOEFF0_Y_OFFSET       0
-#define BM_PXP_CSCCOEFF0_Y_OFFSET       0x1ff
-#define BF_PXP_CSCCOEFF0_Y_OFFSET(v)    (((v) << 0) & 0x1ff)
-
-/**
- * Register: HW_PXP_CSCCOEFF1
- * Address: 0xe0
- * SCT: no
-*/
-#define HW_PXP_CSCCOEFF1            (*(volatile unsigned long *)(REGS_PXP_BASE + 0xe0))
-#define BP_PXP_CSCCOEFF1_RSVD1      27
-#define BM_PXP_CSCCOEFF1_RSVD1      0xf8000000
-#define BF_PXP_CSCCOEFF1_RSVD1(v)   (((v) << 27) & 0xf8000000)
-#define BP_PXP_CSCCOEFF1_C1         16
-#define BM_PXP_CSCCOEFF1_C1         0x7ff0000
-#define BF_PXP_CSCCOEFF1_C1(v)      (((v) << 16) & 0x7ff0000)
-#define BP_PXP_CSCCOEFF1_RSVD0      11
-#define BM_PXP_CSCCOEFF1_RSVD0      0xf800
-#define BF_PXP_CSCCOEFF1_RSVD0(v)   (((v) << 11) & 0xf800)
-#define BP_PXP_CSCCOEFF1_C4         0
-#define BM_PXP_CSCCOEFF1_C4         0x7ff
-#define BF_PXP_CSCCOEFF1_C4(v)      (((v) << 0) & 0x7ff)
-
-/**
- * Register: HW_PXP_CSCCOEFF2
- * Address: 0xf0
- * SCT: no
-*/
-#define HW_PXP_CSCCOEFF2            (*(volatile unsigned long *)(REGS_PXP_BASE + 0xf0))
-#define BP_PXP_CSCCOEFF2_RSVD1      27
-#define BM_PXP_CSCCOEFF2_RSVD1      0xf8000000
-#define BF_PXP_CSCCOEFF2_RSVD1(v)   (((v) << 27) & 0xf8000000)
-#define BP_PXP_CSCCOEFF2_C2         16
-#define BM_PXP_CSCCOEFF2_C2         0x7ff0000
-#define BF_PXP_CSCCOEFF2_C2(v)      (((v) << 16) & 0x7ff0000)
-#define BP_PXP_CSCCOEFF2_RSVD0      11
-#define BM_PXP_CSCCOEFF2_RSVD0      0xf800
-#define BF_PXP_CSCCOEFF2_RSVD0(v)   (((v) << 11) & 0xf800)
-#define BP_PXP_CSCCOEFF2_C3         0
-#define BM_PXP_CSCCOEFF2_C3         0x7ff
-#define BF_PXP_CSCCOEFF2_C3(v)      (((v) << 0) & 0x7ff)
-
-/**
- * Register: HW_PXP_NEXT
- * Address: 0x100
- * SCT: yes
-*/
-#define HW_PXP_NEXT             (*(volatile unsigned long *)(REGS_PXP_BASE + 0x100 + 0x0))
-#define HW_PXP_NEXT_SET         (*(volatile unsigned long *)(REGS_PXP_BASE + 0x100 + 0x4))
-#define HW_PXP_NEXT_CLR         (*(volatile unsigned long *)(REGS_PXP_BASE + 0x100 + 0x8))
-#define HW_PXP_NEXT_TOG         (*(volatile unsigned long *)(REGS_PXP_BASE + 0x100 + 0xc))
-#define BP_PXP_NEXT_POINTER     2
-#define BM_PXP_NEXT_POINTER     0xfffffffc
-#define BF_PXP_NEXT_POINTER(v)  (((v) << 2) & 0xfffffffc)
-#define BP_PXP_NEXT_RSVD        1
-#define BM_PXP_NEXT_RSVD        0x2
-#define BF_PXP_NEXT_RSVD(v)     (((v) << 1) & 0x2)
-#define BP_PXP_NEXT_ENABLED     0
-#define BM_PXP_NEXT_ENABLED     0x1
-#define BF_PXP_NEXT_ENABLED(v)  (((v) << 0) & 0x1)
-
-/**
- * Register: HW_PXP_PAGETABLE
- * Address: 0x170
- * SCT: no
-*/
-#define HW_PXP_PAGETABLE            (*(volatile unsigned long *)(REGS_PXP_BASE + 0x170))
-#define BP_PXP_PAGETABLE_BASE       14
-#define BM_PXP_PAGETABLE_BASE       0xffffc000
-#define BF_PXP_PAGETABLE_BASE(v)    (((v) << 14) & 0xffffc000)
-#define BP_PXP_PAGETABLE_RSVD1      2
-#define BM_PXP_PAGETABLE_RSVD1      0x3ffc
-#define BF_PXP_PAGETABLE_RSVD1(v)   (((v) << 2) & 0x3ffc)
-#define BP_PXP_PAGETABLE_FLUSH      1
-#define BM_PXP_PAGETABLE_FLUSH      0x2
-#define BF_PXP_PAGETABLE_FLUSH(v)   (((v) << 1) & 0x2)
-#define BP_PXP_PAGETABLE_ENABLE     0
-#define BM_PXP_PAGETABLE_ENABLE     0x1
-#define BF_PXP_PAGETABLE_ENABLE(v)  (((v) << 0) & 0x1)
-
-/**
- * Register: HW_PXP_S0COLORKEYLOW
- * Address: 0x180
- * SCT: no
-*/
-#define HW_PXP_S0COLORKEYLOW            (*(volatile unsigned long *)(REGS_PXP_BASE + 0x180))
-#define BP_PXP_S0COLORKEYLOW_RSVD1      24
-#define BM_PXP_S0COLORKEYLOW_RSVD1      0xff000000
-#define BF_PXP_S0COLORKEYLOW_RSVD1(v)   (((v) << 24) & 0xff000000)
-#define BP_PXP_S0COLORKEYLOW_PIXEL      0
-#define BM_PXP_S0COLORKEYLOW_PIXEL      0xffffff
-#define BF_PXP_S0COLORKEYLOW_PIXEL(v)   (((v) << 0) & 0xffffff)
-
-/**
- * Register: HW_PXP_S0COLORKEYHIGH
- * Address: 0x190
- * SCT: no
-*/
-#define HW_PXP_S0COLORKEYHIGH           (*(volatile unsigned long *)(REGS_PXP_BASE + 0x190))
-#define BP_PXP_S0COLORKEYHIGH_RSVD1     24
-#define BM_PXP_S0COLORKEYHIGH_RSVD1     0xff000000
-#define BF_PXP_S0COLORKEYHIGH_RSVD1(v)  (((v) << 24) & 0xff000000)
-#define BP_PXP_S0COLORKEYHIGH_PIXEL     0
-#define BM_PXP_S0COLORKEYHIGH_PIXEL     0xffffff
-#define BF_PXP_S0COLORKEYHIGH_PIXEL(v)  (((v) << 0) & 0xffffff)
-
-/**
- * Register: HW_PXP_OLCOLORKEYLOW
- * Address: 0x1a0
- * SCT: no
-*/
-#define HW_PXP_OLCOLORKEYLOW            (*(volatile unsigned long *)(REGS_PXP_BASE + 0x1a0))
-#define BP_PXP_OLCOLORKEYLOW_RSVD1      24
-#define BM_PXP_OLCOLORKEYLOW_RSVD1      0xff000000
-#define BF_PXP_OLCOLORKEYLOW_RSVD1(v)   (((v) << 24) & 0xff000000)
-#define BP_PXP_OLCOLORKEYLOW_PIXEL      0
-#define BM_PXP_OLCOLORKEYLOW_PIXEL      0xffffff
-#define BF_PXP_OLCOLORKEYLOW_PIXEL(v)   (((v) << 0) & 0xffffff)
-
-/**
- * Register: HW_PXP_OLCOLORKEYHIGH
- * Address: 0x1b0
- * SCT: no
-*/
-#define HW_PXP_OLCOLORKEYHIGH           (*(volatile unsigned long *)(REGS_PXP_BASE + 0x1b0))
-#define BP_PXP_OLCOLORKEYHIGH_RSVD1     24
-#define BM_PXP_OLCOLORKEYHIGH_RSVD1     0xff000000
-#define BF_PXP_OLCOLORKEYHIGH_RSVD1(v)  (((v) << 24) & 0xff000000)
-#define BP_PXP_OLCOLORKEYHIGH_PIXEL     0
-#define BM_PXP_OLCOLORKEYHIGH_PIXEL     0xffffff
-#define BF_PXP_OLCOLORKEYHIGH_PIXEL(v)  (((v) << 0) & 0xffffff)
-
-/**
- * Register: HW_PXP_DEBUGCTRL
- * Address: 0x1d0
- * SCT: no
-*/
-#define HW_PXP_DEBUGCTRL                    (*(volatile unsigned long *)(REGS_PXP_BASE + 0x1d0))
-#define BP_PXP_DEBUGCTRL_RSVD               9
-#define BM_PXP_DEBUGCTRL_RSVD               0xfffffe00
-#define BF_PXP_DEBUGCTRL_RSVD(v)            (((v) << 9) & 0xfffffe00)
-#define BP_PXP_DEBUGCTRL_RESET_TLB_STATS    8
-#define BM_PXP_DEBUGCTRL_RESET_TLB_STATS    0x100
-#define BF_PXP_DEBUGCTRL_RESET_TLB_STATS(v) (((v) << 8) & 0x100)
-#define BP_PXP_DEBUGCTRL_SELECT             0
-#define BM_PXP_DEBUGCTRL_SELECT             0xff
-#define BV_PXP_DEBUGCTRL_SELECT__NONE       0x0
-#define BV_PXP_DEBUGCTRL_SELECT__CTRL       0x1
-#define BV_PXP_DEBUGCTRL_SELECT__S0REGS     0x2
-#define BV_PXP_DEBUGCTRL_SELECT__S0BAX      0x3
-#define BV_PXP_DEBUGCTRL_SELECT__S0BAY      0x4
-#define BV_PXP_DEBUGCTRL_SELECT__PXBUF      0x5
-#define BV_PXP_DEBUGCTRL_SELECT__ROTATION   0x6
-#define BV_PXP_DEBUGCTRL_SELECT__ROTBUF0    0x7
-#define BV_PXP_DEBUGCTRL_SELECT__ROTBUF1    0x8
-#define BF_PXP_DEBUGCTRL_SELECT(v)          (((v) << 0) & 0xff)
-#define BF_PXP_DEBUGCTRL_SELECT_V(v)        ((BV_PXP_DEBUGCTRL_SELECT__##v << 0) & 0xff)
-
-/**
- * Register: HW_PXP_DEBUG
- * Address: 0x1e0
- * SCT: no
-*/
-#define HW_PXP_DEBUG            (*(volatile unsigned long *)(REGS_PXP_BASE + 0x1e0))
-#define BP_PXP_DEBUG_DATA       0
-#define BM_PXP_DEBUG_DATA       0xffffffff
-#define BF_PXP_DEBUG_DATA(v)    (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_PXP_VERSION
- * Address: 0x1f0
- * SCT: no
-*/
-#define HW_PXP_VERSION          (*(volatile unsigned long *)(REGS_PXP_BASE + 0x1f0))
-#define BP_PXP_VERSION_MAJOR    24
-#define BM_PXP_VERSION_MAJOR    0xff000000
-#define BF_PXP_VERSION_MAJOR(v) (((v) << 24) & 0xff000000)
-#define BP_PXP_VERSION_MINOR    16
-#define BM_PXP_VERSION_MINOR    0xff0000
-#define BF_PXP_VERSION_MINOR(v) (((v) << 16) & 0xff0000)
-#define BP_PXP_VERSION_STEP     0
-#define BM_PXP_VERSION_STEP     0xffff
-#define BF_PXP_VERSION_STEP(v)  (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_PXP_OLn
- * Address: 0x200+n*0x40
- * SCT: no
-*/
-#define HW_PXP_OLn(n)       (*(volatile unsigned long *)(REGS_PXP_BASE + 0x200+(n)*0x40))
-#define BP_PXP_OLn_ADDR     0
-#define BM_PXP_OLn_ADDR     0xffffffff
-#define BF_PXP_OLn_ADDR(v)  (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_PXP_OLnSIZE
- * Address: 0x210+n*0x40
- * SCT: no
-*/
-#define HW_PXP_OLnSIZE(n)           (*(volatile unsigned long *)(REGS_PXP_BASE + 0x210+(n)*0x40))
-#define BP_PXP_OLnSIZE_XBASE        24
-#define BM_PXP_OLnSIZE_XBASE        0xff000000
-#define BF_PXP_OLnSIZE_XBASE(v)     (((v) << 24) & 0xff000000)
-#define BP_PXP_OLnSIZE_YBASE        16
-#define BM_PXP_OLnSIZE_YBASE        0xff0000
-#define BF_PXP_OLnSIZE_YBASE(v)     (((v) << 16) & 0xff0000)
-#define BP_PXP_OLnSIZE_WIDTH        8
-#define BM_PXP_OLnSIZE_WIDTH        0xff00
-#define BF_PXP_OLnSIZE_WIDTH(v)     (((v) << 8) & 0xff00)
-#define BP_PXP_OLnSIZE_HEIGHT       0
-#define BM_PXP_OLnSIZE_HEIGHT       0xff
-#define BF_PXP_OLnSIZE_HEIGHT(v)    (((v) << 0) & 0xff)
-
-/**
- * Register: HW_PXP_OLnPARAM
- * Address: 0x220+n*0x40
- * SCT: no
-*/
-#define HW_PXP_OLnPARAM(n)                      (*(volatile unsigned long *)(REGS_PXP_BASE + 0x220+(n)*0x40))
-#define BP_PXP_OLnPARAM_RSVD1                   20
-#define BM_PXP_OLnPARAM_RSVD1                   0xfff00000
-#define BF_PXP_OLnPARAM_RSVD1(v)                (((v) << 20) & 0xfff00000)
-#define BP_PXP_OLnPARAM_ROP                     16
-#define BM_PXP_OLnPARAM_ROP                     0xf0000
-#define BV_PXP_OLnPARAM_ROP__MASKOL             0x0
-#define BV_PXP_OLnPARAM_ROP__MASKNOTOL          0x1
-#define BV_PXP_OLnPARAM_ROP__MASKOLNOT          0x2
-#define BV_PXP_OLnPARAM_ROP__MERGEOL            0x3
-#define BV_PXP_OLnPARAM_ROP__MERGENOTOL         0x4
-#define BV_PXP_OLnPARAM_ROP__MERGEOLNOT         0x5
-#define BV_PXP_OLnPARAM_ROP__NOTCOPYOL          0x6
-#define BV_PXP_OLnPARAM_ROP__NOT                0x7
-#define BV_PXP_OLnPARAM_ROP__NOTMASKOL          0x8
-#define BV_PXP_OLnPARAM_ROP__NOTMERGEOL         0x9
-#define BV_PXP_OLnPARAM_ROP__XOROL              0xa
-#define BV_PXP_OLnPARAM_ROP__NOTXOROL           0xb
-#define BF_PXP_OLnPARAM_ROP(v)                  (((v) << 16) & 0xf0000)
-#define BF_PXP_OLnPARAM_ROP_V(v)                ((BV_PXP_OLnPARAM_ROP__##v << 16) & 0xf0000)
-#define BP_PXP_OLnPARAM_ALPHA                   8
-#define BM_PXP_OLnPARAM_ALPHA                   0xff00
-#define BF_PXP_OLnPARAM_ALPHA(v)                (((v) << 8) & 0xff00)
-#define BP_PXP_OLnPARAM_FORMAT                  4
-#define BM_PXP_OLnPARAM_FORMAT                  0xf0
-#define BV_PXP_OLnPARAM_FORMAT__ARGB8888        0x0
-#define BV_PXP_OLnPARAM_FORMAT__RGB888          0x1
-#define BV_PXP_OLnPARAM_FORMAT__ARGB1555        0x3
-#define BV_PXP_OLnPARAM_FORMAT__RGB565          0x4
-#define BV_PXP_OLnPARAM_FORMAT__RGB555          0x5
-#define BF_PXP_OLnPARAM_FORMAT(v)               (((v) << 4) & 0xf0)
-#define BF_PXP_OLnPARAM_FORMAT_V(v)             ((BV_PXP_OLnPARAM_FORMAT__##v << 4) & 0xf0)
-#define BP_PXP_OLnPARAM_ENABLE_COLORKEY         3
-#define BM_PXP_OLnPARAM_ENABLE_COLORKEY         0x8
-#define BF_PXP_OLnPARAM_ENABLE_COLORKEY(v)      (((v) << 3) & 0x8)
-#define BP_PXP_OLnPARAM_ALPHA_CNTL              1
-#define BM_PXP_OLnPARAM_ALPHA_CNTL              0x6
-#define BV_PXP_OLnPARAM_ALPHA_CNTL__Embedded    0x0
-#define BV_PXP_OLnPARAM_ALPHA_CNTL__Override    0x1
-#define BV_PXP_OLnPARAM_ALPHA_CNTL__Multiply    0x2
-#define BV_PXP_OLnPARAM_ALPHA_CNTL__ROPs        0x3
-#define BF_PXP_OLnPARAM_ALPHA_CNTL(v)           (((v) << 1) & 0x6)
-#define BF_PXP_OLnPARAM_ALPHA_CNTL_V(v)         ((BV_PXP_OLnPARAM_ALPHA_CNTL__##v << 1) & 0x6)
-#define BP_PXP_OLnPARAM_ENABLE                  0
-#define BM_PXP_OLnPARAM_ENABLE                  0x1
-#define BF_PXP_OLnPARAM_ENABLE(v)               (((v) << 0) & 0x1)
-
-/**
- * Register: HW_PXP_OLnPARAM2
- * Address: 0x230+n*0x40
- * SCT: no
-*/
-#define HW_PXP_OLnPARAM2(n)         (*(volatile unsigned long *)(REGS_PXP_BASE + 0x230+(n)*0x40))
-#define BP_PXP_OLnPARAM2_RSVD       0
-#define BM_PXP_OLnPARAM2_RSVD       0xffffffff
-#define BF_PXP_OLnPARAM2_RSVD(v)    (((v) << 0) & 0xffffffff)
-
-#endif /* __HEADERGEN__IMX233__PXP__H__ */
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-rtc.h b/firmware/target/arm/imx233/regs/imx233/regs-rtc.h
deleted file mode 100644
index 7d3628650f..0000000000
--- a/firmware/target/arm/imx233/regs/imx233/regs-rtc.h
+++ /dev/null
@@ -1,318 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: imx233:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__IMX233__RTC__H__
-#define __HEADERGEN__IMX233__RTC__H__
-
-#define REGS_RTC_BASE (0x8005c000)
-
-#define REGS_RTC_VERSION "3.2.0"
-
-/**
- * Register: HW_RTC_CTRL
- * Address: 0
- * SCT: yes
-*/
-#define HW_RTC_CTRL                         (*(volatile unsigned long *)(REGS_RTC_BASE + 0x0 + 0x0))
-#define HW_RTC_CTRL_SET                     (*(volatile unsigned long *)(REGS_RTC_BASE + 0x0 + 0x4))
-#define HW_RTC_CTRL_CLR                     (*(volatile unsigned long *)(REGS_RTC_BASE + 0x0 + 0x8))
-#define HW_RTC_CTRL_TOG                     (*(volatile unsigned long *)(REGS_RTC_BASE + 0x0 + 0xc))
-#define BP_RTC_CTRL_SFTRST                  31
-#define BM_RTC_CTRL_SFTRST                  0x80000000
-#define BF_RTC_CTRL_SFTRST(v)               (((v) << 31) & 0x80000000)
-#define BP_RTC_CTRL_CLKGATE                 30
-#define BM_RTC_CTRL_CLKGATE                 0x40000000
-#define BF_RTC_CTRL_CLKGATE(v)              (((v) << 30) & 0x40000000)
-#define BP_RTC_CTRL_RSVD0                   7
-#define BM_RTC_CTRL_RSVD0                   0x3fffff80
-#define BF_RTC_CTRL_RSVD0(v)                (((v) << 7) & 0x3fffff80)
-#define BP_RTC_CTRL_SUPPRESS_COPY2ANALOG    6
-#define BM_RTC_CTRL_SUPPRESS_COPY2ANALOG    0x40
-#define BF_RTC_CTRL_SUPPRESS_COPY2ANALOG(v) (((v) << 6) & 0x40)
-#define BP_RTC_CTRL_FORCE_UPDATE            5
-#define BM_RTC_CTRL_FORCE_UPDATE            0x20
-#define BF_RTC_CTRL_FORCE_UPDATE(v)         (((v) << 5) & 0x20)
-#define BP_RTC_CTRL_WATCHDOGEN              4
-#define BM_RTC_CTRL_WATCHDOGEN              0x10
-#define BF_RTC_CTRL_WATCHDOGEN(v)           (((v) << 4) & 0x10)
-#define BP_RTC_CTRL_ONEMSEC_IRQ             3
-#define BM_RTC_CTRL_ONEMSEC_IRQ             0x8
-#define BF_RTC_CTRL_ONEMSEC_IRQ(v)          (((v) << 3) & 0x8)
-#define BP_RTC_CTRL_ALARM_IRQ               2
-#define BM_RTC_CTRL_ALARM_IRQ               0x4
-#define BF_RTC_CTRL_ALARM_IRQ(v)            (((v) << 2) & 0x4)
-#define BP_RTC_CTRL_ONEMSEC_IRQ_EN          1
-#define BM_RTC_CTRL_ONEMSEC_IRQ_EN          0x2
-#define BF_RTC_CTRL_ONEMSEC_IRQ_EN(v)       (((v) << 1) & 0x2)
-#define BP_RTC_CTRL_ALARM_IRQ_EN            0
-#define BM_RTC_CTRL_ALARM_IRQ_EN            0x1
-#define BF_RTC_CTRL_ALARM_IRQ_EN(v)         (((v) << 0) & 0x1)
-
-/**
- * Register: HW_RTC_STAT
- * Address: 0x10
- * SCT: yes
-*/
-#define HW_RTC_STAT                         (*(volatile unsigned long *)(REGS_RTC_BASE + 0x10 + 0x0))
-#define HW_RTC_STAT_SET                     (*(volatile unsigned long *)(REGS_RTC_BASE + 0x10 + 0x4))
-#define HW_RTC_STAT_CLR                     (*(volatile unsigned long *)(REGS_RTC_BASE + 0x10 + 0x8))
-#define HW_RTC_STAT_TOG                     (*(volatile unsigned long *)(REGS_RTC_BASE + 0x10 + 0xc))
-#define BP_RTC_STAT_RTC_PRESENT             31
-#define BM_RTC_STAT_RTC_PRESENT             0x80000000
-#define BF_RTC_STAT_RTC_PRESENT(v)          (((v) << 31) & 0x80000000)
-#define BP_RTC_STAT_ALARM_PRESENT           30
-#define BM_RTC_STAT_ALARM_PRESENT           0x40000000
-#define BF_RTC_STAT_ALARM_PRESENT(v)        (((v) << 30) & 0x40000000)
-#define BP_RTC_STAT_WATCHDOG_PRESENT        29
-#define BM_RTC_STAT_WATCHDOG_PRESENT        0x20000000
-#define BF_RTC_STAT_WATCHDOG_PRESENT(v)     (((v) << 29) & 0x20000000)
-#define BP_RTC_STAT_XTAL32000_PRESENT       28
-#define BM_RTC_STAT_XTAL32000_PRESENT       0x10000000
-#define BF_RTC_STAT_XTAL32000_PRESENT(v)    (((v) << 28) & 0x10000000)
-#define BP_RTC_STAT_XTAL32768_PRESENT       27
-#define BM_RTC_STAT_XTAL32768_PRESENT       0x8000000
-#define BF_RTC_STAT_XTAL32768_PRESENT(v)    (((v) << 27) & 0x8000000)
-#define BP_RTC_STAT_RSVD1                   24
-#define BM_RTC_STAT_RSVD1                   0x7000000
-#define BF_RTC_STAT_RSVD1(v)                (((v) << 24) & 0x7000000)
-#define BP_RTC_STAT_STALE_REGS              16
-#define BM_RTC_STAT_STALE_REGS              0xff0000
-#define BF_RTC_STAT_STALE_REGS(v)           (((v) << 16) & 0xff0000)
-#define BP_RTC_STAT_NEW_REGS                8
-#define BM_RTC_STAT_NEW_REGS                0xff00
-#define BF_RTC_STAT_NEW_REGS(v)             (((v) << 8) & 0xff00)
-#define BP_RTC_STAT_RSVD0                   0
-#define BM_RTC_STAT_RSVD0                   0xff
-#define BF_RTC_STAT_RSVD0(v)                (((v) << 0) & 0xff)
-
-/**
- * Register: HW_RTC_MILLISECONDS
- * Address: 0x20
- * SCT: yes
-*/
-#define HW_RTC_MILLISECONDS             (*(volatile unsigned long *)(REGS_RTC_BASE + 0x20 + 0x0))
-#define HW_RTC_MILLISECONDS_SET         (*(volatile unsigned long *)(REGS_RTC_BASE + 0x20 + 0x4))
-#define HW_RTC_MILLISECONDS_CLR         (*(volatile unsigned long *)(REGS_RTC_BASE + 0x20 + 0x8))
-#define HW_RTC_MILLISECONDS_TOG         (*(volatile unsigned long *)(REGS_RTC_BASE + 0x20 + 0xc))
-#define BP_RTC_MILLISECONDS_COUNT       0
-#define BM_RTC_MILLISECONDS_COUNT       0xffffffff
-#define BF_RTC_MILLISECONDS_COUNT(v)    (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_RTC_SECONDS
- * Address: 0x30
- * SCT: yes
-*/
-#define HW_RTC_SECONDS          (*(volatile unsigned long *)(REGS_RTC_BASE + 0x30 + 0x0))
-#define HW_RTC_SECONDS_SET      (*(volatile unsigned long *)(REGS_RTC_BASE + 0x30 + 0x4))
-#define HW_RTC_SECONDS_CLR      (*(volatile unsigned long *)(REGS_RTC_BASE + 0x30 + 0x8))
-#define HW_RTC_SECONDS_TOG      (*(volatile unsigned long *)(REGS_RTC_BASE + 0x30 + 0xc))
-#define BP_RTC_SECONDS_COUNT    0
-#define BM_RTC_SECONDS_COUNT    0xffffffff
-#define BF_RTC_SECONDS_COUNT(v) (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_RTC_ALARM
- * Address: 0x40
- * SCT: yes
-*/
-#define HW_RTC_ALARM            (*(volatile unsigned long *)(REGS_RTC_BASE + 0x40 + 0x0))
-#define HW_RTC_ALARM_SET        (*(volatile unsigned long *)(REGS_RTC_BASE + 0x40 + 0x4))
-#define HW_RTC_ALARM_CLR        (*(volatile unsigned long *)(REGS_RTC_BASE + 0x40 + 0x8))
-#define HW_RTC_ALARM_TOG        (*(volatile unsigned long *)(REGS_RTC_BASE + 0x40 + 0xc))
-#define BP_RTC_ALARM_VALUE      0
-#define BM_RTC_ALARM_VALUE      0xffffffff
-#define BF_RTC_ALARM_VALUE(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_RTC_WATCHDOG
- * Address: 0x50
- * SCT: yes
-*/
-#define HW_RTC_WATCHDOG             (*(volatile unsigned long *)(REGS_RTC_BASE + 0x50 + 0x0))
-#define HW_RTC_WATCHDOG_SET         (*(volatile unsigned long *)(REGS_RTC_BASE + 0x50 + 0x4))
-#define HW_RTC_WATCHDOG_CLR         (*(volatile unsigned long *)(REGS_RTC_BASE + 0x50 + 0x8))
-#define HW_RTC_WATCHDOG_TOG         (*(volatile unsigned long *)(REGS_RTC_BASE + 0x50 + 0xc))
-#define BP_RTC_WATCHDOG_COUNT       0
-#define BM_RTC_WATCHDOG_COUNT       0xffffffff
-#define BF_RTC_WATCHDOG_COUNT(v)    (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_RTC_PERSISTENT0
- * Address: 0x60
- * SCT: yes
-*/
-#define HW_RTC_PERSISTENT0                      (*(volatile unsigned long *)(REGS_RTC_BASE + 0x60 + 0x0))
-#define HW_RTC_PERSISTENT0_SET                  (*(volatile unsigned long *)(REGS_RTC_BASE + 0x60 + 0x4))
-#define HW_RTC_PERSISTENT0_CLR                  (*(volatile unsigned long *)(REGS_RTC_BASE + 0x60 + 0x8))
-#define HW_RTC_PERSISTENT0_TOG                  (*(volatile unsigned long *)(REGS_RTC_BASE + 0x60 + 0xc))
-#define BP_RTC_PERSISTENT0_SPARE_ANALOG         18
-#define BM_RTC_PERSISTENT0_SPARE_ANALOG         0xfffc0000
-#define BF_RTC_PERSISTENT0_SPARE_ANALOG(v)      (((v) << 18) & 0xfffc0000)
-#define BP_RTC_PERSISTENT0_AUTO_RESTART         17
-#define BM_RTC_PERSISTENT0_AUTO_RESTART         0x20000
-#define BF_RTC_PERSISTENT0_AUTO_RESTART(v)      (((v) << 17) & 0x20000)
-#define BP_RTC_PERSISTENT0_DISABLE_PSWITCH      16
-#define BM_RTC_PERSISTENT0_DISABLE_PSWITCH      0x10000
-#define BF_RTC_PERSISTENT0_DISABLE_PSWITCH(v)   (((v) << 16) & 0x10000)
-#define BP_RTC_PERSISTENT0_LOWERBIAS            14
-#define BM_RTC_PERSISTENT0_LOWERBIAS            0xc000
-#define BF_RTC_PERSISTENT0_LOWERBIAS(v)         (((v) << 14) & 0xc000)
-#define BP_RTC_PERSISTENT0_DISABLE_XTALOK       13
-#define BM_RTC_PERSISTENT0_DISABLE_XTALOK       0x2000
-#define BF_RTC_PERSISTENT0_DISABLE_XTALOK(v)    (((v) << 13) & 0x2000)
-#define BP_RTC_PERSISTENT0_MSEC_RES             8
-#define BM_RTC_PERSISTENT0_MSEC_RES             0x1f00
-#define BF_RTC_PERSISTENT0_MSEC_RES(v)          (((v) << 8) & 0x1f00)
-#define BP_RTC_PERSISTENT0_ALARM_WAKE           7
-#define BM_RTC_PERSISTENT0_ALARM_WAKE           0x80
-#define BF_RTC_PERSISTENT0_ALARM_WAKE(v)        (((v) << 7) & 0x80)
-#define BP_RTC_PERSISTENT0_XTAL32_FREQ          6
-#define BM_RTC_PERSISTENT0_XTAL32_FREQ          0x40
-#define BF_RTC_PERSISTENT0_XTAL32_FREQ(v)       (((v) << 6) & 0x40)
-#define BP_RTC_PERSISTENT0_XTAL32KHZ_PWRUP      5
-#define BM_RTC_PERSISTENT0_XTAL32KHZ_PWRUP      0x20
-#define BF_RTC_PERSISTENT0_XTAL32KHZ_PWRUP(v)   (((v) << 5) & 0x20)
-#define BP_RTC_PERSISTENT0_XTAL24MHZ_PWRUP      4
-#define BM_RTC_PERSISTENT0_XTAL24MHZ_PWRUP      0x10
-#define BF_RTC_PERSISTENT0_XTAL24MHZ_PWRUP(v)   (((v) << 4) & 0x10)
-#define BP_RTC_PERSISTENT0_LCK_SECS             3
-#define BM_RTC_PERSISTENT0_LCK_SECS             0x8
-#define BF_RTC_PERSISTENT0_LCK_SECS(v)          (((v) << 3) & 0x8)
-#define BP_RTC_PERSISTENT0_ALARM_EN             2
-#define BM_RTC_PERSISTENT0_ALARM_EN             0x4
-#define BF_RTC_PERSISTENT0_ALARM_EN(v)          (((v) << 2) & 0x4)
-#define BP_RTC_PERSISTENT0_ALARM_WAKE_EN        1
-#define BM_RTC_PERSISTENT0_ALARM_WAKE_EN        0x2
-#define BF_RTC_PERSISTENT0_ALARM_WAKE_EN(v)     (((v) << 1) & 0x2)
-#define BP_RTC_PERSISTENT0_CLOCKSOURCE          0
-#define BM_RTC_PERSISTENT0_CLOCKSOURCE          0x1
-#define BF_RTC_PERSISTENT0_CLOCKSOURCE(v)       (((v) << 0) & 0x1)
-
-/**
- * Register: HW_RTC_PERSISTENT1
- * Address: 0x70
- * SCT: yes
-*/
-#define HW_RTC_PERSISTENT1                                  (*(volatile unsigned long *)(REGS_RTC_BASE + 0x70 + 0x0))
-#define HW_RTC_PERSISTENT1_SET                              (*(volatile unsigned long *)(REGS_RTC_BASE + 0x70 + 0x4))
-#define HW_RTC_PERSISTENT1_CLR                              (*(volatile unsigned long *)(REGS_RTC_BASE + 0x70 + 0x8))
-#define HW_RTC_PERSISTENT1_TOG                              (*(volatile unsigned long *)(REGS_RTC_BASE + 0x70 + 0xc))
-#define BP_RTC_PERSISTENT1_GENERAL                          0
-#define BM_RTC_PERSISTENT1_GENERAL                          0xffffffff
-#define BV_RTC_PERSISTENT1_GENERAL__ENUMERATE_500MA_TWICE   0x1000
-#define BV_RTC_PERSISTENT1_GENERAL__USB_BOOT_PLAYER_MODE    0x800
-#define BV_RTC_PERSISTENT1_GENERAL__SKIP_CHECKDISK          0x400
-#define BV_RTC_PERSISTENT1_GENERAL__USB_LOW_POWER_MODE      0x200
-#define BV_RTC_PERSISTENT1_GENERAL__OTG_HNP_BIT             0x100
-#define BV_RTC_PERSISTENT1_GENERAL__OTG_ATL_ROLE_BIT        0x80
-#define BF_RTC_PERSISTENT1_GENERAL(v)                       (((v) << 0) & 0xffffffff)
-#define BF_RTC_PERSISTENT1_GENERAL_V(v)                     ((BV_RTC_PERSISTENT1_GENERAL__##v << 0) & 0xffffffff)
-
-/**
- * Register: HW_RTC_PERSISTENT2
- * Address: 0x80
- * SCT: yes
-*/
-#define HW_RTC_PERSISTENT2              (*(volatile unsigned long *)(REGS_RTC_BASE + 0x80 + 0x0))
-#define HW_RTC_PERSISTENT2_SET          (*(volatile unsigned long *)(REGS_RTC_BASE + 0x80 + 0x4))
-#define HW_RTC_PERSISTENT2_CLR          (*(volatile unsigned long *)(REGS_RTC_BASE + 0x80 + 0x8))
-#define HW_RTC_PERSISTENT2_TOG          (*(volatile unsigned long *)(REGS_RTC_BASE + 0x80 + 0xc))
-#define BP_RTC_PERSISTENT2_GENERAL      0
-#define BM_RTC_PERSISTENT2_GENERAL      0xffffffff
-#define BF_RTC_PERSISTENT2_GENERAL(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_RTC_PERSISTENT3
- * Address: 0x90
- * SCT: yes
-*/
-#define HW_RTC_PERSISTENT3              (*(volatile unsigned long *)(REGS_RTC_BASE + 0x90 + 0x0))
-#define HW_RTC_PERSISTENT3_SET          (*(volatile unsigned long *)(REGS_RTC_BASE + 0x90 + 0x4))
-#define HW_RTC_PERSISTENT3_CLR          (*(volatile unsigned long *)(REGS_RTC_BASE + 0x90 + 0x8))
-#define HW_RTC_PERSISTENT3_TOG          (*(volatile unsigned long *)(REGS_RTC_BASE + 0x90 + 0xc))
-#define BP_RTC_PERSISTENT3_GENERAL      0
-#define BM_RTC_PERSISTENT3_GENERAL      0xffffffff
-#define BF_RTC_PERSISTENT3_GENERAL(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_RTC_PERSISTENT4
- * Address: 0xa0
- * SCT: yes
-*/
-#define HW_RTC_PERSISTENT4              (*(volatile unsigned long *)(REGS_RTC_BASE + 0xa0 + 0x0))
-#define HW_RTC_PERSISTENT4_SET          (*(volatile unsigned long *)(REGS_RTC_BASE + 0xa0 + 0x4))
-#define HW_RTC_PERSISTENT4_CLR          (*(volatile unsigned long *)(REGS_RTC_BASE + 0xa0 + 0x8))
-#define HW_RTC_PERSISTENT4_TOG          (*(volatile unsigned long *)(REGS_RTC_BASE + 0xa0 + 0xc))
-#define BP_RTC_PERSISTENT4_GENERAL      0
-#define BM_RTC_PERSISTENT4_GENERAL      0xffffffff
-#define BF_RTC_PERSISTENT4_GENERAL(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_RTC_PERSISTENT5
- * Address: 0xb0
- * SCT: yes
-*/
-#define HW_RTC_PERSISTENT5              (*(volatile unsigned long *)(REGS_RTC_BASE + 0xb0 + 0x0))
-#define HW_RTC_PERSISTENT5_SET          (*(volatile unsigned long *)(REGS_RTC_BASE + 0xb0 + 0x4))
-#define HW_RTC_PERSISTENT5_CLR          (*(volatile unsigned long *)(REGS_RTC_BASE + 0xb0 + 0x8))
-#define HW_RTC_PERSISTENT5_TOG          (*(volatile unsigned long *)(REGS_RTC_BASE + 0xb0 + 0xc))
-#define BP_RTC_PERSISTENT5_GENERAL      0
-#define BM_RTC_PERSISTENT5_GENERAL      0xffffffff
-#define BF_RTC_PERSISTENT5_GENERAL(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_RTC_DEBUG
- * Address: 0xc0
- * SCT: yes
-*/
-#define HW_RTC_DEBUG                        (*(volatile unsigned long *)(REGS_RTC_BASE + 0xc0 + 0x0))
-#define HW_RTC_DEBUG_SET                    (*(volatile unsigned long *)(REGS_RTC_BASE + 0xc0 + 0x4))
-#define HW_RTC_DEBUG_CLR                    (*(volatile unsigned long *)(REGS_RTC_BASE + 0xc0 + 0x8))
-#define HW_RTC_DEBUG_TOG                    (*(volatile unsigned long *)(REGS_RTC_BASE + 0xc0 + 0xc))
-#define BP_RTC_DEBUG_RSVD0                  2
-#define BM_RTC_DEBUG_RSVD0                  0xfffffffc
-#define BF_RTC_DEBUG_RSVD0(v)               (((v) << 2) & 0xfffffffc)
-#define BP_RTC_DEBUG_WATCHDOG_RESET_MASK    1
-#define BM_RTC_DEBUG_WATCHDOG_RESET_MASK    0x2
-#define BF_RTC_DEBUG_WATCHDOG_RESET_MASK(v) (((v) << 1) & 0x2)
-#define BP_RTC_DEBUG_WATCHDOG_RESET         0
-#define BM_RTC_DEBUG_WATCHDOG_RESET         0x1
-#define BF_RTC_DEBUG_WATCHDOG_RESET(v)      (((v) << 0) & 0x1)
-
-/**
- * Register: HW_RTC_VERSION
- * Address: 0xd0
- * SCT: no
-*/
-#define HW_RTC_VERSION          (*(volatile unsigned long *)(REGS_RTC_BASE + 0xd0))
-#define BP_RTC_VERSION_MAJOR    24
-#define BM_RTC_VERSION_MAJOR    0xff000000
-#define BF_RTC_VERSION_MAJOR(v) (((v) << 24) & 0xff000000)
-#define BP_RTC_VERSION_MINOR    16
-#define BM_RTC_VERSION_MINOR    0xff0000
-#define BF_RTC_VERSION_MINOR(v) (((v) << 16) & 0xff0000)
-#define BP_RTC_VERSION_STEP     0
-#define BM_RTC_VERSION_STEP     0xffff
-#define BF_RTC_VERSION_STEP(v)  (((v) << 0) & 0xffff)
-
-#endif /* __HEADERGEN__IMX233__RTC__H__ */
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-saif.h b/firmware/target/arm/imx233/regs/imx233/regs-saif.h
deleted file mode 100644
index 1a8e7d838a..0000000000
--- a/firmware/target/arm/imx233/regs/imx233/regs-saif.h
+++ /dev/null
@@ -1,169 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: imx233:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__IMX233__SAIF__H__
-#define __HEADERGEN__IMX233__SAIF__H__
-
-#define REGS_SAIF_BASE(i) ((i) == 1 ? 0x80042000 : 0x80046000)
-
-#define REGS_SAIF_VERSION "3.2.0"
-
-/**
- * Register: HW_SAIF_CTRL
- * Address: 0
- * SCT: yes
-*/
-#define HW_SAIF_CTRL(d)                     (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x0 + 0x0))
-#define HW_SAIF_CTRL_SET(d)                 (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x0 + 0x4))
-#define HW_SAIF_CTRL_CLR(d)                 (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x0 + 0x8))
-#define HW_SAIF_CTRL_TOG(d)                 (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x0 + 0xc))
-#define BP_SAIF_CTRL_SFTRST                 31
-#define BM_SAIF_CTRL_SFTRST                 0x80000000
-#define BF_SAIF_CTRL_SFTRST(v)              (((v) << 31) & 0x80000000)
-#define BP_SAIF_CTRL_CLKGATE                30
-#define BM_SAIF_CTRL_CLKGATE                0x40000000
-#define BF_SAIF_CTRL_CLKGATE(v)             (((v) << 30) & 0x40000000)
-#define BP_SAIF_CTRL_BITCLK_MULT_RATE       27
-#define BM_SAIF_CTRL_BITCLK_MULT_RATE       0x38000000
-#define BF_SAIF_CTRL_BITCLK_MULT_RATE(v)    (((v) << 27) & 0x38000000)
-#define BP_SAIF_CTRL_BITCLK_BASE_RATE       26
-#define BM_SAIF_CTRL_BITCLK_BASE_RATE       0x4000000
-#define BF_SAIF_CTRL_BITCLK_BASE_RATE(v)    (((v) << 26) & 0x4000000)
-#define BP_SAIF_CTRL_FIFO_ERROR_IRQ_EN      25
-#define BM_SAIF_CTRL_FIFO_ERROR_IRQ_EN      0x2000000
-#define BF_SAIF_CTRL_FIFO_ERROR_IRQ_EN(v)   (((v) << 25) & 0x2000000)
-#define BP_SAIF_CTRL_FIFO_SERVICE_IRQ_EN    24
-#define BM_SAIF_CTRL_FIFO_SERVICE_IRQ_EN    0x1000000
-#define BF_SAIF_CTRL_FIFO_SERVICE_IRQ_EN(v) (((v) << 24) & 0x1000000)
-#define BP_SAIF_CTRL_RSRVD2                 21
-#define BM_SAIF_CTRL_RSRVD2                 0xe00000
-#define BF_SAIF_CTRL_RSRVD2(v)              (((v) << 21) & 0xe00000)
-#define BP_SAIF_CTRL_DMAWAIT_COUNT          16
-#define BM_SAIF_CTRL_DMAWAIT_COUNT          0x1f0000
-#define BF_SAIF_CTRL_DMAWAIT_COUNT(v)       (((v) << 16) & 0x1f0000)
-#define BP_SAIF_CTRL_CHANNEL_NUM_SELECT     14
-#define BM_SAIF_CTRL_CHANNEL_NUM_SELECT     0xc000
-#define BF_SAIF_CTRL_CHANNEL_NUM_SELECT(v)  (((v) << 14) & 0xc000)
-#define BP_SAIF_CTRL_RSRVD1                 13
-#define BM_SAIF_CTRL_RSRVD1                 0x2000
-#define BF_SAIF_CTRL_RSRVD1(v)              (((v) << 13) & 0x2000)
-#define BP_SAIF_CTRL_BIT_ORDER              12
-#define BM_SAIF_CTRL_BIT_ORDER              0x1000
-#define BF_SAIF_CTRL_BIT_ORDER(v)           (((v) << 12) & 0x1000)
-#define BP_SAIF_CTRL_DELAY                  11
-#define BM_SAIF_CTRL_DELAY                  0x800
-#define BF_SAIF_CTRL_DELAY(v)               (((v) << 11) & 0x800)
-#define BP_SAIF_CTRL_JUSTIFY                10
-#define BM_SAIF_CTRL_JUSTIFY                0x400
-#define BF_SAIF_CTRL_JUSTIFY(v)             (((v) << 10) & 0x400)
-#define BP_SAIF_CTRL_LRCLK_POLARITY         9
-#define BM_SAIF_CTRL_LRCLK_POLARITY         0x200
-#define BF_SAIF_CTRL_LRCLK_POLARITY(v)      (((v) << 9) & 0x200)
-#define BP_SAIF_CTRL_BITCLK_EDGE            8
-#define BM_SAIF_CTRL_BITCLK_EDGE            0x100
-#define BF_SAIF_CTRL_BITCLK_EDGE(v)         (((v) << 8) & 0x100)
-#define BP_SAIF_CTRL_WORD_LENGTH            4
-#define BM_SAIF_CTRL_WORD_LENGTH            0xf0
-#define BF_SAIF_CTRL_WORD_LENGTH(v)         (((v) << 4) & 0xf0)
-#define BP_SAIF_CTRL_BITCLK_48XFS_ENABLE    3
-#define BM_SAIF_CTRL_BITCLK_48XFS_ENABLE    0x8
-#define BF_SAIF_CTRL_BITCLK_48XFS_ENABLE(v) (((v) << 3) & 0x8)
-#define BP_SAIF_CTRL_SLAVE_MODE             2
-#define BM_SAIF_CTRL_SLAVE_MODE             0x4
-#define BF_SAIF_CTRL_SLAVE_MODE(v)          (((v) << 2) & 0x4)
-#define BP_SAIF_CTRL_READ_MODE              1
-#define BM_SAIF_CTRL_READ_MODE              0x2
-#define BF_SAIF_CTRL_READ_MODE(v)           (((v) << 1) & 0x2)
-#define BP_SAIF_CTRL_RUN                    0
-#define BM_SAIF_CTRL_RUN                    0x1
-#define BF_SAIF_CTRL_RUN(v)                 (((v) << 0) & 0x1)
-
-/**
- * Register: HW_SAIF_STAT
- * Address: 0x10
- * SCT: yes
-*/
-#define HW_SAIF_STAT(d)                     (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x10 + 0x0))
-#define HW_SAIF_STAT_SET(d)                 (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x10 + 0x4))
-#define HW_SAIF_STAT_CLR(d)                 (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x10 + 0x8))
-#define HW_SAIF_STAT_TOG(d)                 (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x10 + 0xc))
-#define BP_SAIF_STAT_PRESENT                31
-#define BM_SAIF_STAT_PRESENT                0x80000000
-#define BF_SAIF_STAT_PRESENT(v)             (((v) << 31) & 0x80000000)
-#define BP_SAIF_STAT_RSRVD2                 17
-#define BM_SAIF_STAT_RSRVD2                 0x7ffe0000
-#define BF_SAIF_STAT_RSRVD2(v)              (((v) << 17) & 0x7ffe0000)
-#define BP_SAIF_STAT_DMA_PREQ               16
-#define BM_SAIF_STAT_DMA_PREQ               0x10000
-#define BF_SAIF_STAT_DMA_PREQ(v)            (((v) << 16) & 0x10000)
-#define BP_SAIF_STAT_RSRVD1                 7
-#define BM_SAIF_STAT_RSRVD1                 0xff80
-#define BF_SAIF_STAT_RSRVD1(v)              (((v) << 7) & 0xff80)
-#define BP_SAIF_STAT_FIFO_UNDERFLOW_IRQ     6
-#define BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ     0x40
-#define BF_SAIF_STAT_FIFO_UNDERFLOW_IRQ(v)  (((v) << 6) & 0x40)
-#define BP_SAIF_STAT_FIFO_OVERFLOW_IRQ      5
-#define BM_SAIF_STAT_FIFO_OVERFLOW_IRQ      0x20
-#define BF_SAIF_STAT_FIFO_OVERFLOW_IRQ(v)   (((v) << 5) & 0x20)
-#define BP_SAIF_STAT_FIFO_SERVICE_IRQ       4
-#define BM_SAIF_STAT_FIFO_SERVICE_IRQ       0x10
-#define BF_SAIF_STAT_FIFO_SERVICE_IRQ(v)    (((v) << 4) & 0x10)
-#define BP_SAIF_STAT_RSRVD0                 1
-#define BM_SAIF_STAT_RSRVD0                 0xe
-#define BF_SAIF_STAT_RSRVD0(v)              (((v) << 1) & 0xe)
-#define BP_SAIF_STAT_BUSY                   0
-#define BM_SAIF_STAT_BUSY                   0x1
-#define BF_SAIF_STAT_BUSY(v)                (((v) << 0) & 0x1)
-
-/**
- * Register: HW_SAIF_DATA
- * Address: 0x20
- * SCT: yes
-*/
-#define HW_SAIF_DATA(d)             (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x20 + 0x0))
-#define HW_SAIF_DATA_SET(d)         (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x20 + 0x4))
-#define HW_SAIF_DATA_CLR(d)         (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x20 + 0x8))
-#define HW_SAIF_DATA_TOG(d)         (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x20 + 0xc))
-#define BP_SAIF_DATA_PCM_RIGHT      16
-#define BM_SAIF_DATA_PCM_RIGHT      0xffff0000
-#define BF_SAIF_DATA_PCM_RIGHT(v)   (((v) << 16) & 0xffff0000)
-#define BP_SAIF_DATA_PCM_LEFT       0
-#define BM_SAIF_DATA_PCM_LEFT       0xffff
-#define BF_SAIF_DATA_PCM_LEFT(v)    (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_SAIF_VERSION
- * Address: 0x30
- * SCT: no
-*/
-#define HW_SAIF_VERSION(d)          (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x30))
-#define BP_SAIF_VERSION_MAJOR       24
-#define BM_SAIF_VERSION_MAJOR       0xff000000
-#define BF_SAIF_VERSION_MAJOR(v)    (((v) << 24) & 0xff000000)
-#define BP_SAIF_VERSION_MINOR       16
-#define BM_SAIF_VERSION_MINOR       0xff0000
-#define BF_SAIF_VERSION_MINOR(v)    (((v) << 16) & 0xff0000)
-#define BP_SAIF_VERSION_STEP        0
-#define BM_SAIF_VERSION_STEP        0xffff
-#define BF_SAIF_VERSION_STEP(v)     (((v) << 0) & 0xffff)
-
-#endif /* __HEADERGEN__IMX233__SAIF__H__ */
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-spdif.h b/firmware/target/arm/imx233/regs/imx233/regs-spdif.h
deleted file mode 100644
index 45ba7f2724..0000000000
--- a/firmware/target/arm/imx233/regs/imx233/regs-spdif.h
+++ /dev/null
@@ -1,214 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: imx233:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__IMX233__SPDIF__H__
-#define __HEADERGEN__IMX233__SPDIF__H__
-
-#define REGS_SPDIF_BASE (0x80054000)
-
-#define REGS_SPDIF_VERSION "3.2.0"
-
-/**
- * Register: HW_SPDIF_CTRL
- * Address: 0
- * SCT: yes
-*/
-#define HW_SPDIF_CTRL                       (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x0 + 0x0))
-#define HW_SPDIF_CTRL_SET                   (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x0 + 0x4))
-#define HW_SPDIF_CTRL_CLR                   (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x0 + 0x8))
-#define HW_SPDIF_CTRL_TOG                   (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x0 + 0xc))
-#define BP_SPDIF_CTRL_SFTRST                31
-#define BM_SPDIF_CTRL_SFTRST                0x80000000
-#define BF_SPDIF_CTRL_SFTRST(v)             (((v) << 31) & 0x80000000)
-#define BP_SPDIF_CTRL_CLKGATE               30
-#define BM_SPDIF_CTRL_CLKGATE               0x40000000
-#define BF_SPDIF_CTRL_CLKGATE(v)            (((v) << 30) & 0x40000000)
-#define BP_SPDIF_CTRL_RSRVD1                21
-#define BM_SPDIF_CTRL_RSRVD1                0x3fe00000
-#define BF_SPDIF_CTRL_RSRVD1(v)             (((v) << 21) & 0x3fe00000)
-#define BP_SPDIF_CTRL_DMAWAIT_COUNT         16
-#define BM_SPDIF_CTRL_DMAWAIT_COUNT         0x1f0000
-#define BF_SPDIF_CTRL_DMAWAIT_COUNT(v)      (((v) << 16) & 0x1f0000)
-#define BP_SPDIF_CTRL_RSRVD0                6
-#define BM_SPDIF_CTRL_RSRVD0                0xffc0
-#define BF_SPDIF_CTRL_RSRVD0(v)             (((v) << 6) & 0xffc0)
-#define BP_SPDIF_CTRL_WAIT_END_XFER         5
-#define BM_SPDIF_CTRL_WAIT_END_XFER         0x20
-#define BF_SPDIF_CTRL_WAIT_END_XFER(v)      (((v) << 5) & 0x20)
-#define BP_SPDIF_CTRL_WORD_LENGTH           4
-#define BM_SPDIF_CTRL_WORD_LENGTH           0x10
-#define BF_SPDIF_CTRL_WORD_LENGTH(v)        (((v) << 4) & 0x10)
-#define BP_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ    3
-#define BM_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ    0x8
-#define BF_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ(v) (((v) << 3) & 0x8)
-#define BP_SPDIF_CTRL_FIFO_OVERFLOW_IRQ     2
-#define BM_SPDIF_CTRL_FIFO_OVERFLOW_IRQ     0x4
-#define BF_SPDIF_CTRL_FIFO_OVERFLOW_IRQ(v)  (((v) << 2) & 0x4)
-#define BP_SPDIF_CTRL_FIFO_ERROR_IRQ_EN     1
-#define BM_SPDIF_CTRL_FIFO_ERROR_IRQ_EN     0x2
-#define BF_SPDIF_CTRL_FIFO_ERROR_IRQ_EN(v)  (((v) << 1) & 0x2)
-#define BP_SPDIF_CTRL_RUN                   0
-#define BM_SPDIF_CTRL_RUN                   0x1
-#define BF_SPDIF_CTRL_RUN(v)                (((v) << 0) & 0x1)
-
-/**
- * Register: HW_SPDIF_STAT
- * Address: 0x10
- * SCT: yes
-*/
-#define HW_SPDIF_STAT               (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x10 + 0x0))
-#define HW_SPDIF_STAT_SET           (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x10 + 0x4))
-#define HW_SPDIF_STAT_CLR           (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x10 + 0x8))
-#define HW_SPDIF_STAT_TOG           (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x10 + 0xc))
-#define BP_SPDIF_STAT_PRESENT       31
-#define BM_SPDIF_STAT_PRESENT       0x80000000
-#define BF_SPDIF_STAT_PRESENT(v)    (((v) << 31) & 0x80000000)
-#define BP_SPDIF_STAT_RSRVD1        1
-#define BM_SPDIF_STAT_RSRVD1        0x7ffffffe
-#define BF_SPDIF_STAT_RSRVD1(v)     (((v) << 1) & 0x7ffffffe)
-#define BP_SPDIF_STAT_END_XFER      0
-#define BM_SPDIF_STAT_END_XFER      0x1
-#define BF_SPDIF_STAT_END_XFER(v)   (((v) << 0) & 0x1)
-
-/**
- * Register: HW_SPDIF_FRAMECTRL
- * Address: 0x20
- * SCT: yes
-*/
-#define HW_SPDIF_FRAMECTRL              (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x20 + 0x0))
-#define HW_SPDIF_FRAMECTRL_SET          (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x20 + 0x4))
-#define HW_SPDIF_FRAMECTRL_CLR          (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x20 + 0x8))
-#define HW_SPDIF_FRAMECTRL_TOG          (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x20 + 0xc))
-#define BP_SPDIF_FRAMECTRL_RSRVD2       18
-#define BM_SPDIF_FRAMECTRL_RSRVD2       0xfffc0000
-#define BF_SPDIF_FRAMECTRL_RSRVD2(v)    (((v) << 18) & 0xfffc0000)
-#define BP_SPDIF_FRAMECTRL_V_CONFIG     17
-#define BM_SPDIF_FRAMECTRL_V_CONFIG     0x20000
-#define BF_SPDIF_FRAMECTRL_V_CONFIG(v)  (((v) << 17) & 0x20000)
-#define BP_SPDIF_FRAMECTRL_AUTO_MUTE    16
-#define BM_SPDIF_FRAMECTRL_AUTO_MUTE    0x10000
-#define BF_SPDIF_FRAMECTRL_AUTO_MUTE(v) (((v) << 16) & 0x10000)
-#define BP_SPDIF_FRAMECTRL_RSRVD1       15
-#define BM_SPDIF_FRAMECTRL_RSRVD1       0x8000
-#define BF_SPDIF_FRAMECTRL_RSRVD1(v)    (((v) << 15) & 0x8000)
-#define BP_SPDIF_FRAMECTRL_USER_DATA    14
-#define BM_SPDIF_FRAMECTRL_USER_DATA    0x4000
-#define BF_SPDIF_FRAMECTRL_USER_DATA(v) (((v) << 14) & 0x4000)
-#define BP_SPDIF_FRAMECTRL_V            13
-#define BM_SPDIF_FRAMECTRL_V            0x2000
-#define BF_SPDIF_FRAMECTRL_V(v)         (((v) << 13) & 0x2000)
-#define BP_SPDIF_FRAMECTRL_L            12
-#define BM_SPDIF_FRAMECTRL_L            0x1000
-#define BF_SPDIF_FRAMECTRL_L(v)         (((v) << 12) & 0x1000)
-#define BP_SPDIF_FRAMECTRL_RSRVD0       11
-#define BM_SPDIF_FRAMECTRL_RSRVD0       0x800
-#define BF_SPDIF_FRAMECTRL_RSRVD0(v)    (((v) << 11) & 0x800)
-#define BP_SPDIF_FRAMECTRL_CC           4
-#define BM_SPDIF_FRAMECTRL_CC           0x7f0
-#define BF_SPDIF_FRAMECTRL_CC(v)        (((v) << 4) & 0x7f0)
-#define BP_SPDIF_FRAMECTRL_PRE          3
-#define BM_SPDIF_FRAMECTRL_PRE          0x8
-#define BF_SPDIF_FRAMECTRL_PRE(v)       (((v) << 3) & 0x8)
-#define BP_SPDIF_FRAMECTRL_COPY         2
-#define BM_SPDIF_FRAMECTRL_COPY         0x4
-#define BF_SPDIF_FRAMECTRL_COPY(v)      (((v) << 2) & 0x4)
-#define BP_SPDIF_FRAMECTRL_AUDIO        1
-#define BM_SPDIF_FRAMECTRL_AUDIO        0x2
-#define BF_SPDIF_FRAMECTRL_AUDIO(v)     (((v) << 1) & 0x2)
-#define BP_SPDIF_FRAMECTRL_PRO          0
-#define BM_SPDIF_FRAMECTRL_PRO          0x1
-#define BF_SPDIF_FRAMECTRL_PRO(v)       (((v) << 0) & 0x1)
-
-/**
- * Register: HW_SPDIF_SRR
- * Address: 0x30
- * SCT: yes
-*/
-#define HW_SPDIF_SRR                (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x30 + 0x0))
-#define HW_SPDIF_SRR_SET            (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x30 + 0x4))
-#define HW_SPDIF_SRR_CLR            (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x30 + 0x8))
-#define HW_SPDIF_SRR_TOG            (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x30 + 0xc))
-#define BP_SPDIF_SRR_RSRVD1         31
-#define BM_SPDIF_SRR_RSRVD1         0x80000000
-#define BF_SPDIF_SRR_RSRVD1(v)      (((v) << 31) & 0x80000000)
-#define BP_SPDIF_SRR_BASEMULT       28
-#define BM_SPDIF_SRR_BASEMULT       0x70000000
-#define BF_SPDIF_SRR_BASEMULT(v)    (((v) << 28) & 0x70000000)
-#define BP_SPDIF_SRR_RSRVD0         20
-#define BM_SPDIF_SRR_RSRVD0         0xff00000
-#define BF_SPDIF_SRR_RSRVD0(v)      (((v) << 20) & 0xff00000)
-#define BP_SPDIF_SRR_RATE           0
-#define BM_SPDIF_SRR_RATE           0xfffff
-#define BF_SPDIF_SRR_RATE(v)        (((v) << 0) & 0xfffff)
-
-/**
- * Register: HW_SPDIF_DEBUG
- * Address: 0x40
- * SCT: yes
-*/
-#define HW_SPDIF_DEBUG                  (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x40 + 0x0))
-#define HW_SPDIF_DEBUG_SET              (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x40 + 0x4))
-#define HW_SPDIF_DEBUG_CLR              (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x40 + 0x8))
-#define HW_SPDIF_DEBUG_TOG              (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x40 + 0xc))
-#define BP_SPDIF_DEBUG_RSRVD1           2
-#define BM_SPDIF_DEBUG_RSRVD1           0xfffffffc
-#define BF_SPDIF_DEBUG_RSRVD1(v)        (((v) << 2) & 0xfffffffc)
-#define BP_SPDIF_DEBUG_DMA_PREQ         1
-#define BM_SPDIF_DEBUG_DMA_PREQ         0x2
-#define BF_SPDIF_DEBUG_DMA_PREQ(v)      (((v) << 1) & 0x2)
-#define BP_SPDIF_DEBUG_FIFO_STATUS      0
-#define BM_SPDIF_DEBUG_FIFO_STATUS      0x1
-#define BF_SPDIF_DEBUG_FIFO_STATUS(v)   (((v) << 0) & 0x1)
-
-/**
- * Register: HW_SPDIF_DATA
- * Address: 0x50
- * SCT: yes
-*/
-#define HW_SPDIF_DATA           (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x50 + 0x0))
-#define HW_SPDIF_DATA_SET       (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x50 + 0x4))
-#define HW_SPDIF_DATA_CLR       (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x50 + 0x8))
-#define HW_SPDIF_DATA_TOG       (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x50 + 0xc))
-#define BP_SPDIF_DATA_HIGH      16
-#define BM_SPDIF_DATA_HIGH      0xffff0000
-#define BF_SPDIF_DATA_HIGH(v)   (((v) << 16) & 0xffff0000)
-#define BP_SPDIF_DATA_LOW       0
-#define BM_SPDIF_DATA_LOW       0xffff
-#define BF_SPDIF_DATA_LOW(v)    (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_SPDIF_VERSION
- * Address: 0x60
- * SCT: no
-*/
-#define HW_SPDIF_VERSION            (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x60))
-#define BP_SPDIF_VERSION_MAJOR      24
-#define BM_SPDIF_VERSION_MAJOR      0xff000000
-#define BF_SPDIF_VERSION_MAJOR(v)   (((v) << 24) & 0xff000000)
-#define BP_SPDIF_VERSION_MINOR      16
-#define BM_SPDIF_VERSION_MINOR      0xff0000
-#define BF_SPDIF_VERSION_MINOR(v)   (((v) << 16) & 0xff0000)
-#define BP_SPDIF_VERSION_STEP       0
-#define BM_SPDIF_VERSION_STEP       0xffff
-#define BF_SPDIF_VERSION_STEP(v)    (((v) << 0) & 0xffff)
-
-#endif /* __HEADERGEN__IMX233__SPDIF__H__ */
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-ssp.h b/firmware/target/arm/imx233/regs/imx233/regs-ssp.h
deleted file mode 100644
index d4da0523bc..0000000000
--- a/firmware/target/arm/imx233/regs/imx233/regs-ssp.h
+++ /dev/null
@@ -1,576 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: imx233:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__IMX233__SSP__H__
-#define __HEADERGEN__IMX233__SSP__H__
-
-#define REGS_SSP_BASE(i) ((i) == 1 ? 0x80010000 : 0x80034000)
-
-#define REGS_SSP_VERSION "3.2.0"
-
-/**
- * Register: HW_SSP_CTRL0
- * Address: 0
- * SCT: yes
-*/
-#define HW_SSP_CTRL0(d)                     (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x0 + 0x0))
-#define HW_SSP_CTRL0_SET(d)                 (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x0 + 0x4))
-#define HW_SSP_CTRL0_CLR(d)                 (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x0 + 0x8))
-#define HW_SSP_CTRL0_TOG(d)                 (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x0 + 0xc))
-#define BP_SSP_CTRL0_SFTRST                 31
-#define BM_SSP_CTRL0_SFTRST                 0x80000000
-#define BF_SSP_CTRL0_SFTRST(v)              (((v) << 31) & 0x80000000)
-#define BP_SSP_CTRL0_CLKGATE                30
-#define BM_SSP_CTRL0_CLKGATE                0x40000000
-#define BF_SSP_CTRL0_CLKGATE(v)             (((v) << 30) & 0x40000000)
-#define BP_SSP_CTRL0_RUN                    29
-#define BM_SSP_CTRL0_RUN                    0x20000000
-#define BF_SSP_CTRL0_RUN(v)                 (((v) << 29) & 0x20000000)
-#define BP_SSP_CTRL0_SDIO_IRQ_CHECK         28
-#define BM_SSP_CTRL0_SDIO_IRQ_CHECK         0x10000000
-#define BF_SSP_CTRL0_SDIO_IRQ_CHECK(v)      (((v) << 28) & 0x10000000)
-#define BP_SSP_CTRL0_LOCK_CS                27
-#define BM_SSP_CTRL0_LOCK_CS                0x8000000
-#define BF_SSP_CTRL0_LOCK_CS(v)             (((v) << 27) & 0x8000000)
-#define BP_SSP_CTRL0_IGNORE_CRC             26
-#define BM_SSP_CTRL0_IGNORE_CRC             0x4000000
-#define BF_SSP_CTRL0_IGNORE_CRC(v)          (((v) << 26) & 0x4000000)
-#define BP_SSP_CTRL0_READ                   25
-#define BM_SSP_CTRL0_READ                   0x2000000
-#define BF_SSP_CTRL0_READ(v)                (((v) << 25) & 0x2000000)
-#define BP_SSP_CTRL0_DATA_XFER              24
-#define BM_SSP_CTRL0_DATA_XFER              0x1000000
-#define BF_SSP_CTRL0_DATA_XFER(v)           (((v) << 24) & 0x1000000)
-#define BP_SSP_CTRL0_BUS_WIDTH              22
-#define BM_SSP_CTRL0_BUS_WIDTH              0xc00000
-#define BV_SSP_CTRL0_BUS_WIDTH__ONE_BIT     0x0
-#define BV_SSP_CTRL0_BUS_WIDTH__FOUR_BIT    0x1
-#define BV_SSP_CTRL0_BUS_WIDTH__EIGHT_BIT   0x2
-#define BF_SSP_CTRL0_BUS_WIDTH(v)           (((v) << 22) & 0xc00000)
-#define BF_SSP_CTRL0_BUS_WIDTH_V(v)         ((BV_SSP_CTRL0_BUS_WIDTH__##v << 22) & 0xc00000)
-#define BP_SSP_CTRL0_WAIT_FOR_IRQ           21
-#define BM_SSP_CTRL0_WAIT_FOR_IRQ           0x200000
-#define BF_SSP_CTRL0_WAIT_FOR_IRQ(v)        (((v) << 21) & 0x200000)
-#define BP_SSP_CTRL0_WAIT_FOR_CMD           20
-#define BM_SSP_CTRL0_WAIT_FOR_CMD           0x100000
-#define BF_SSP_CTRL0_WAIT_FOR_CMD(v)        (((v) << 20) & 0x100000)
-#define BP_SSP_CTRL0_LONG_RESP              19
-#define BM_SSP_CTRL0_LONG_RESP              0x80000
-#define BF_SSP_CTRL0_LONG_RESP(v)           (((v) << 19) & 0x80000)
-#define BP_SSP_CTRL0_CHECK_RESP             18
-#define BM_SSP_CTRL0_CHECK_RESP             0x40000
-#define BF_SSP_CTRL0_CHECK_RESP(v)          (((v) << 18) & 0x40000)
-#define BP_SSP_CTRL0_GET_RESP               17
-#define BM_SSP_CTRL0_GET_RESP               0x20000
-#define BF_SSP_CTRL0_GET_RESP(v)            (((v) << 17) & 0x20000)
-#define BP_SSP_CTRL0_ENABLE                 16
-#define BM_SSP_CTRL0_ENABLE                 0x10000
-#define BF_SSP_CTRL0_ENABLE(v)              (((v) << 16) & 0x10000)
-#define BP_SSP_CTRL0_XFER_COUNT             0
-#define BM_SSP_CTRL0_XFER_COUNT             0xffff
-#define BF_SSP_CTRL0_XFER_COUNT(v)          (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_SSP_CMD0
- * Address: 0x10
- * SCT: yes
-*/
-#define HW_SSP_CMD0(d)                              (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x10 + 0x0))
-#define HW_SSP_CMD0_SET(d)                          (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x10 + 0x4))
-#define HW_SSP_CMD0_CLR(d)                          (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x10 + 0x8))
-#define HW_SSP_CMD0_TOG(d)                          (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x10 + 0xc))
-#define BP_SSP_CMD0_RSVD0                           23
-#define BM_SSP_CMD0_RSVD0                           0xff800000
-#define BF_SSP_CMD0_RSVD0(v)                        (((v) << 23) & 0xff800000)
-#define BP_SSP_CMD0_SLOW_CLKING_EN                  22
-#define BM_SSP_CMD0_SLOW_CLKING_EN                  0x400000
-#define BF_SSP_CMD0_SLOW_CLKING_EN(v)               (((v) << 22) & 0x400000)
-#define BP_SSP_CMD0_CONT_CLKING_EN                  21
-#define BM_SSP_CMD0_CONT_CLKING_EN                  0x200000
-#define BF_SSP_CMD0_CONT_CLKING_EN(v)               (((v) << 21) & 0x200000)
-#define BP_SSP_CMD0_APPEND_8CYC                     20
-#define BM_SSP_CMD0_APPEND_8CYC                     0x100000
-#define BF_SSP_CMD0_APPEND_8CYC(v)                  (((v) << 20) & 0x100000)
-#define BP_SSP_CMD0_BLOCK_SIZE                      16
-#define BM_SSP_CMD0_BLOCK_SIZE                      0xf0000
-#define BF_SSP_CMD0_BLOCK_SIZE(v)                   (((v) << 16) & 0xf0000)
-#define BP_SSP_CMD0_BLOCK_COUNT                     8
-#define BM_SSP_CMD0_BLOCK_COUNT                     0xff00
-#define BF_SSP_CMD0_BLOCK_COUNT(v)                  (((v) << 8) & 0xff00)
-#define BP_SSP_CMD0_CMD                             0
-#define BM_SSP_CMD0_CMD                             0xff
-#define BV_SSP_CMD0_CMD__MMC_GO_IDLE_STATE          0x0
-#define BV_SSP_CMD0_CMD__MMC_SEND_OP_COND           0x1
-#define BV_SSP_CMD0_CMD__MMC_ALL_SEND_CID           0x2
-#define BV_SSP_CMD0_CMD__MMC_SET_RELATIVE_ADDR      0x3
-#define BV_SSP_CMD0_CMD__MMC_SET_DSR                0x4
-#define BV_SSP_CMD0_CMD__MMC_RESERVED_5             0x5
-#define BV_SSP_CMD0_CMD__MMC_SWITCH                 0x6
-#define BV_SSP_CMD0_CMD__MMC_SELECT_DESELECT_CARD   0x7
-#define BV_SSP_CMD0_CMD__MMC_SEND_EXT_CSD           0x8
-#define BV_SSP_CMD0_CMD__MMC_SEND_CSD               0x9
-#define BV_SSP_CMD0_CMD__MMC_SEND_CID               0xa
-#define BV_SSP_CMD0_CMD__MMC_READ_DAT_UNTIL_STOP    0xb
-#define BV_SSP_CMD0_CMD__MMC_STOP_TRANSMISSION      0xc
-#define BV_SSP_CMD0_CMD__MMC_SEND_STATUS            0xd
-#define BV_SSP_CMD0_CMD__MMC_BUSTEST_R              0xe
-#define BV_SSP_CMD0_CMD__MMC_GO_INACTIVE_STATE      0xf
-#define BV_SSP_CMD0_CMD__MMC_SET_BLOCKLEN           0x10
-#define BV_SSP_CMD0_CMD__MMC_READ_SINGLE_BLOCK      0x11
-#define BV_SSP_CMD0_CMD__MMC_READ_MULTIPLE_BLOCK    0x12
-#define BV_SSP_CMD0_CMD__MMC_BUSTEST_W              0x13
-#define BV_SSP_CMD0_CMD__MMC_WRITE_DAT_UNTIL_STOP   0x14
-#define BV_SSP_CMD0_CMD__MMC_SET_BLOCK_COUNT        0x17
-#define BV_SSP_CMD0_CMD__MMC_WRITE_BLOCK            0x18
-#define BV_SSP_CMD0_CMD__MMC_WRITE_MULTIPLE_BLOCK   0x19
-#define BV_SSP_CMD0_CMD__MMC_PROGRAM_CID            0x1a
-#define BV_SSP_CMD0_CMD__MMC_PROGRAM_CSD            0x1b
-#define BV_SSP_CMD0_CMD__MMC_SET_WRITE_PROT         0x1c
-#define BV_SSP_CMD0_CMD__MMC_CLR_WRITE_PROT         0x1d
-#define BV_SSP_CMD0_CMD__MMC_SEND_WRITE_PROT        0x1e
-#define BV_SSP_CMD0_CMD__MMC_ERASE_GROUP_START      0x23
-#define BV_SSP_CMD0_CMD__MMC_ERASE_GROUP_END        0x24
-#define BV_SSP_CMD0_CMD__MMC_ERASE                  0x26
-#define BV_SSP_CMD0_CMD__MMC_FAST_IO                0x27
-#define BV_SSP_CMD0_CMD__MMC_GO_IRQ_STATE           0x28
-#define BV_SSP_CMD0_CMD__MMC_LOCK_UNLOCK            0x2a
-#define BV_SSP_CMD0_CMD__MMC_APP_CMD                0x37
-#define BV_SSP_CMD0_CMD__MMC_GEN_CMD                0x38
-#define BV_SSP_CMD0_CMD__SD_GO_IDLE_STATE           0x0
-#define BV_SSP_CMD0_CMD__SD_ALL_SEND_CID            0x2
-#define BV_SSP_CMD0_CMD__SD_SEND_RELATIVE_ADDR      0x3
-#define BV_SSP_CMD0_CMD__SD_SET_DSR                 0x4
-#define BV_SSP_CMD0_CMD__SD_IO_SEND_OP_COND         0x5
-#define BV_SSP_CMD0_CMD__SD_SELECT_DESELECT_CARD    0x7
-#define BV_SSP_CMD0_CMD__SD_SEND_CSD                0x9
-#define BV_SSP_CMD0_CMD__SD_SEND_CID                0xa
-#define BV_SSP_CMD0_CMD__SD_STOP_TRANSMISSION       0xc
-#define BV_SSP_CMD0_CMD__SD_SEND_STATUS             0xd
-#define BV_SSP_CMD0_CMD__SD_GO_INACTIVE_STATE       0xf
-#define BV_SSP_CMD0_CMD__SD_SET_BLOCKLEN            0x10
-#define BV_SSP_CMD0_CMD__SD_READ_SINGLE_BLOCK       0x11
-#define BV_SSP_CMD0_CMD__SD_READ_MULTIPLE_BLOCK     0x12
-#define BV_SSP_CMD0_CMD__SD_WRITE_BLOCK             0x18
-#define BV_SSP_CMD0_CMD__SD_WRITE_MULTIPLE_BLOCK    0x19
-#define BV_SSP_CMD0_CMD__SD_PROGRAM_CSD             0x1b
-#define BV_SSP_CMD0_CMD__SD_SET_WRITE_PROT          0x1c
-#define BV_SSP_CMD0_CMD__SD_CLR_WRITE_PROT          0x1d
-#define BV_SSP_CMD0_CMD__SD_SEND_WRITE_PROT         0x1e
-#define BV_SSP_CMD0_CMD__SD_ERASE_WR_BLK_START      0x20
-#define BV_SSP_CMD0_CMD__SD_ERASE_WR_BLK_END        0x21
-#define BV_SSP_CMD0_CMD__SD_ERASE_GROUP_START       0x23
-#define BV_SSP_CMD0_CMD__SD_ERASE_GROUP_END         0x24
-#define BV_SSP_CMD0_CMD__SD_ERASE                   0x26
-#define BV_SSP_CMD0_CMD__SD_LOCK_UNLOCK             0x2a
-#define BV_SSP_CMD0_CMD__SD_IO_RW_DIRECT            0x34
-#define BV_SSP_CMD0_CMD__SD_IO_RW_EXTENDED          0x35
-#define BV_SSP_CMD0_CMD__SD_APP_CMD                 0x37
-#define BV_SSP_CMD0_CMD__SD_GEN_CMD                 0x38
-#define BF_SSP_CMD0_CMD(v)                          (((v) << 0) & 0xff)
-#define BF_SSP_CMD0_CMD_V(v)                        ((BV_SSP_CMD0_CMD__##v << 0) & 0xff)
-
-/**
- * Register: HW_SSP_CMD1
- * Address: 0x20
- * SCT: no
-*/
-#define HW_SSP_CMD1(d)          (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x20))
-#define BP_SSP_CMD1_CMD_ARG     0
-#define BM_SSP_CMD1_CMD_ARG     0xffffffff
-#define BF_SSP_CMD1_CMD_ARG(v)  (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_SSP_COMPREF
- * Address: 0x30
- * SCT: no
-*/
-#define HW_SSP_COMPREF(d)           (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x30))
-#define BP_SSP_COMPREF_REFERENCE    0
-#define BM_SSP_COMPREF_REFERENCE    0xffffffff
-#define BF_SSP_COMPREF_REFERENCE(v) (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_SSP_COMPMASK
- * Address: 0x40
- * SCT: no
-*/
-#define HW_SSP_COMPMASK(d)      (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x40))
-#define BP_SSP_COMPMASK_MASK    0
-#define BM_SSP_COMPMASK_MASK    0xffffffff
-#define BF_SSP_COMPMASK_MASK(v) (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_SSP_TIMING
- * Address: 0x50
- * SCT: no
-*/
-#define HW_SSP_TIMING(d)                (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x50))
-#define BP_SSP_TIMING_TIMEOUT           16
-#define BM_SSP_TIMING_TIMEOUT           0xffff0000
-#define BF_SSP_TIMING_TIMEOUT(v)        (((v) << 16) & 0xffff0000)
-#define BP_SSP_TIMING_CLOCK_DIVIDE      8
-#define BM_SSP_TIMING_CLOCK_DIVIDE      0xff00
-#define BF_SSP_TIMING_CLOCK_DIVIDE(v)   (((v) << 8) & 0xff00)
-#define BP_SSP_TIMING_CLOCK_RATE        0
-#define BM_SSP_TIMING_CLOCK_RATE        0xff
-#define BF_SSP_TIMING_CLOCK_RATE(v)     (((v) << 0) & 0xff)
-
-/**
- * Register: HW_SSP_CTRL1
- * Address: 0x60
- * SCT: yes
-*/
-#define HW_SSP_CTRL1(d)                         (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x60 + 0x0))
-#define HW_SSP_CTRL1_SET(d)                     (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x60 + 0x4))
-#define HW_SSP_CTRL1_CLR(d)                     (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x60 + 0x8))
-#define HW_SSP_CTRL1_TOG(d)                     (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x60 + 0xc))
-#define BP_SSP_CTRL1_SDIO_IRQ                   31
-#define BM_SSP_CTRL1_SDIO_IRQ                   0x80000000
-#define BF_SSP_CTRL1_SDIO_IRQ(v)                (((v) << 31) & 0x80000000)
-#define BP_SSP_CTRL1_SDIO_IRQ_EN                30
-#define BM_SSP_CTRL1_SDIO_IRQ_EN                0x40000000
-#define BF_SSP_CTRL1_SDIO_IRQ_EN(v)             (((v) << 30) & 0x40000000)
-#define BP_SSP_CTRL1_RESP_ERR_IRQ               29
-#define BM_SSP_CTRL1_RESP_ERR_IRQ               0x20000000
-#define BF_SSP_CTRL1_RESP_ERR_IRQ(v)            (((v) << 29) & 0x20000000)
-#define BP_SSP_CTRL1_RESP_ERR_IRQ_EN            28
-#define BM_SSP_CTRL1_RESP_ERR_IRQ_EN            0x10000000
-#define BF_SSP_CTRL1_RESP_ERR_IRQ_EN(v)         (((v) << 28) & 0x10000000)
-#define BP_SSP_CTRL1_RESP_TIMEOUT_IRQ           27
-#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ           0x8000000
-#define BF_SSP_CTRL1_RESP_TIMEOUT_IRQ(v)        (((v) << 27) & 0x8000000)
-#define BP_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN        26
-#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN        0x4000000
-#define BF_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN(v)     (((v) << 26) & 0x4000000)
-#define BP_SSP_CTRL1_DATA_TIMEOUT_IRQ           25
-#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ           0x2000000
-#define BF_SSP_CTRL1_DATA_TIMEOUT_IRQ(v)        (((v) << 25) & 0x2000000)
-#define BP_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN        24
-#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN        0x1000000
-#define BF_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN(v)     (((v) << 24) & 0x1000000)
-#define BP_SSP_CTRL1_DATA_CRC_IRQ               23
-#define BM_SSP_CTRL1_DATA_CRC_IRQ               0x800000
-#define BF_SSP_CTRL1_DATA_CRC_IRQ(v)            (((v) << 23) & 0x800000)
-#define BP_SSP_CTRL1_DATA_CRC_IRQ_EN            22
-#define BM_SSP_CTRL1_DATA_CRC_IRQ_EN            0x400000
-#define BF_SSP_CTRL1_DATA_CRC_IRQ_EN(v)         (((v) << 22) & 0x400000)
-#define BP_SSP_CTRL1_FIFO_UNDERRUN_IRQ          21
-#define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ          0x200000
-#define BF_SSP_CTRL1_FIFO_UNDERRUN_IRQ(v)       (((v) << 21) & 0x200000)
-#define BP_SSP_CTRL1_FIFO_UNDERRUN_EN           20
-#define BM_SSP_CTRL1_FIFO_UNDERRUN_EN           0x100000
-#define BF_SSP_CTRL1_FIFO_UNDERRUN_EN(v)        (((v) << 20) & 0x100000)
-#define BP_SSP_CTRL1_CEATA_CCS_ERR_IRQ          19
-#define BM_SSP_CTRL1_CEATA_CCS_ERR_IRQ          0x80000
-#define BF_SSP_CTRL1_CEATA_CCS_ERR_IRQ(v)       (((v) << 19) & 0x80000)
-#define BP_SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN       18
-#define BM_SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN       0x40000
-#define BF_SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN(v)    (((v) << 18) & 0x40000)
-#define BP_SSP_CTRL1_RECV_TIMEOUT_IRQ           17
-#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ           0x20000
-#define BF_SSP_CTRL1_RECV_TIMEOUT_IRQ(v)        (((v) << 17) & 0x20000)
-#define BP_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN        16
-#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN        0x10000
-#define BF_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN(v)     (((v) << 16) & 0x10000)
-#define BP_SSP_CTRL1_FIFO_OVERRUN_IRQ           15
-#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ           0x8000
-#define BF_SSP_CTRL1_FIFO_OVERRUN_IRQ(v)        (((v) << 15) & 0x8000)
-#define BP_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN        14
-#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN        0x4000
-#define BF_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN(v)     (((v) << 14) & 0x4000)
-#define BP_SSP_CTRL1_DMA_ENABLE                 13
-#define BM_SSP_CTRL1_DMA_ENABLE                 0x2000
-#define BF_SSP_CTRL1_DMA_ENABLE(v)              (((v) << 13) & 0x2000)
-#define BP_SSP_CTRL1_CEATA_CCS_ERR_EN           12
-#define BM_SSP_CTRL1_CEATA_CCS_ERR_EN           0x1000
-#define BF_SSP_CTRL1_CEATA_CCS_ERR_EN(v)        (((v) << 12) & 0x1000)
-#define BP_SSP_CTRL1_SLAVE_OUT_DISABLE          11
-#define BM_SSP_CTRL1_SLAVE_OUT_DISABLE          0x800
-#define BF_SSP_CTRL1_SLAVE_OUT_DISABLE(v)       (((v) << 11) & 0x800)
-#define BP_SSP_CTRL1_PHASE                      10
-#define BM_SSP_CTRL1_PHASE                      0x400
-#define BF_SSP_CTRL1_PHASE(v)                   (((v) << 10) & 0x400)
-#define BP_SSP_CTRL1_POLARITY                   9
-#define BM_SSP_CTRL1_POLARITY                   0x200
-#define BF_SSP_CTRL1_POLARITY(v)                (((v) << 9) & 0x200)
-#define BP_SSP_CTRL1_SLAVE_MODE                 8
-#define BM_SSP_CTRL1_SLAVE_MODE                 0x100
-#define BF_SSP_CTRL1_SLAVE_MODE(v)              (((v) << 8) & 0x100)
-#define BP_SSP_CTRL1_WORD_LENGTH                4
-#define BM_SSP_CTRL1_WORD_LENGTH                0xf0
-#define BV_SSP_CTRL1_WORD_LENGTH__RESERVED0     0x0
-#define BV_SSP_CTRL1_WORD_LENGTH__RESERVED1     0x1
-#define BV_SSP_CTRL1_WORD_LENGTH__RESERVED2     0x2
-#define BV_SSP_CTRL1_WORD_LENGTH__FOUR_BITS     0x3
-#define BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS    0x7
-#define BV_SSP_CTRL1_WORD_LENGTH__SIXTEEN_BITS  0xf
-#define BF_SSP_CTRL1_WORD_LENGTH(v)             (((v) << 4) & 0xf0)
-#define BF_SSP_CTRL1_WORD_LENGTH_V(v)           ((BV_SSP_CTRL1_WORD_LENGTH__##v << 4) & 0xf0)
-#define BP_SSP_CTRL1_SSP_MODE                   0
-#define BM_SSP_CTRL1_SSP_MODE                   0xf
-#define BV_SSP_CTRL1_SSP_MODE__SPI              0x0
-#define BV_SSP_CTRL1_SSP_MODE__SSI              0x1
-#define BV_SSP_CTRL1_SSP_MODE__SD_MMC           0x3
-#define BV_SSP_CTRL1_SSP_MODE__MS               0x4
-#define BV_SSP_CTRL1_SSP_MODE__CE_ATA           0x7
-#define BF_SSP_CTRL1_SSP_MODE(v)                (((v) << 0) & 0xf)
-#define BF_SSP_CTRL1_SSP_MODE_V(v)              ((BV_SSP_CTRL1_SSP_MODE__##v << 0) & 0xf)
-
-/**
- * Register: HW_SSP_DATA
- * Address: 0x70
- * SCT: no
-*/
-#define HW_SSP_DATA(d)      (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x70))
-#define BP_SSP_DATA_DATA    0
-#define BM_SSP_DATA_DATA    0xffffffff
-#define BF_SSP_DATA_DATA(v) (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_SSP_SDRESP0
- * Address: 0x80
- * SCT: no
-*/
-#define HW_SSP_SDRESP0(d)       (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x80))
-#define BP_SSP_SDRESP0_RESP0    0
-#define BM_SSP_SDRESP0_RESP0    0xffffffff
-#define BF_SSP_SDRESP0_RESP0(v) (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_SSP_SDRESP1
- * Address: 0x90
- * SCT: no
-*/
-#define HW_SSP_SDRESP1(d)       (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x90))
-#define BP_SSP_SDRESP1_RESP1    0
-#define BM_SSP_SDRESP1_RESP1    0xffffffff
-#define BF_SSP_SDRESP1_RESP1(v) (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_SSP_SDRESP2
- * Address: 0xa0
- * SCT: no
-*/
-#define HW_SSP_SDRESP2(d)       (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0xa0))
-#define BP_SSP_SDRESP2_RESP2    0
-#define BM_SSP_SDRESP2_RESP2    0xffffffff
-#define BF_SSP_SDRESP2_RESP2(v) (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_SSP_SDRESP3
- * Address: 0xb0
- * SCT: no
-*/
-#define HW_SSP_SDRESP3(d)       (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0xb0))
-#define BP_SSP_SDRESP3_RESP3    0
-#define BM_SSP_SDRESP3_RESP3    0xffffffff
-#define BF_SSP_SDRESP3_RESP3(v) (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_SSP_STATUS
- * Address: 0xc0
- * SCT: no
-*/
-#define HW_SSP_STATUS(d)                    (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0xc0))
-#define BP_SSP_STATUS_PRESENT               31
-#define BM_SSP_STATUS_PRESENT               0x80000000
-#define BF_SSP_STATUS_PRESENT(v)            (((v) << 31) & 0x80000000)
-#define BP_SSP_STATUS_MS_PRESENT            30
-#define BM_SSP_STATUS_MS_PRESENT            0x40000000
-#define BF_SSP_STATUS_MS_PRESENT(v)         (((v) << 30) & 0x40000000)
-#define BP_SSP_STATUS_SD_PRESENT            29
-#define BM_SSP_STATUS_SD_PRESENT            0x20000000
-#define BF_SSP_STATUS_SD_PRESENT(v)         (((v) << 29) & 0x20000000)
-#define BP_SSP_STATUS_CARD_DETECT           28
-#define BM_SSP_STATUS_CARD_DETECT           0x10000000
-#define BF_SSP_STATUS_CARD_DETECT(v)        (((v) << 28) & 0x10000000)
-#define BP_SSP_STATUS_RSVD3                 22
-#define BM_SSP_STATUS_RSVD3                 0xfc00000
-#define BF_SSP_STATUS_RSVD3(v)              (((v) << 22) & 0xfc00000)
-#define BP_SSP_STATUS_DMASENSE              21
-#define BM_SSP_STATUS_DMASENSE              0x200000
-#define BF_SSP_STATUS_DMASENSE(v)           (((v) << 21) & 0x200000)
-#define BP_SSP_STATUS_DMATERM               20
-#define BM_SSP_STATUS_DMATERM               0x100000
-#define BF_SSP_STATUS_DMATERM(v)            (((v) << 20) & 0x100000)
-#define BP_SSP_STATUS_DMAREQ                19
-#define BM_SSP_STATUS_DMAREQ                0x80000
-#define BF_SSP_STATUS_DMAREQ(v)             (((v) << 19) & 0x80000)
-#define BP_SSP_STATUS_DMAEND                18
-#define BM_SSP_STATUS_DMAEND                0x40000
-#define BF_SSP_STATUS_DMAEND(v)             (((v) << 18) & 0x40000)
-#define BP_SSP_STATUS_SDIO_IRQ              17
-#define BM_SSP_STATUS_SDIO_IRQ              0x20000
-#define BF_SSP_STATUS_SDIO_IRQ(v)           (((v) << 17) & 0x20000)
-#define BP_SSP_STATUS_RESP_CRC_ERR          16
-#define BM_SSP_STATUS_RESP_CRC_ERR          0x10000
-#define BF_SSP_STATUS_RESP_CRC_ERR(v)       (((v) << 16) & 0x10000)
-#define BP_SSP_STATUS_RESP_ERR              15
-#define BM_SSP_STATUS_RESP_ERR              0x8000
-#define BF_SSP_STATUS_RESP_ERR(v)           (((v) << 15) & 0x8000)
-#define BP_SSP_STATUS_RESP_TIMEOUT          14
-#define BM_SSP_STATUS_RESP_TIMEOUT          0x4000
-#define BF_SSP_STATUS_RESP_TIMEOUT(v)       (((v) << 14) & 0x4000)
-#define BP_SSP_STATUS_DATA_CRC_ERR          13
-#define BM_SSP_STATUS_DATA_CRC_ERR          0x2000
-#define BF_SSP_STATUS_DATA_CRC_ERR(v)       (((v) << 13) & 0x2000)
-#define BP_SSP_STATUS_TIMEOUT               12
-#define BM_SSP_STATUS_TIMEOUT               0x1000
-#define BF_SSP_STATUS_TIMEOUT(v)            (((v) << 12) & 0x1000)
-#define BP_SSP_STATUS_RECV_TIMEOUT_STAT     11
-#define BM_SSP_STATUS_RECV_TIMEOUT_STAT     0x800
-#define BF_SSP_STATUS_RECV_TIMEOUT_STAT(v)  (((v) << 11) & 0x800)
-#define BP_SSP_STATUS_CEATA_CCS_ERR         10
-#define BM_SSP_STATUS_CEATA_CCS_ERR         0x400
-#define BF_SSP_STATUS_CEATA_CCS_ERR(v)      (((v) << 10) & 0x400)
-#define BP_SSP_STATUS_FIFO_OVRFLW           9
-#define BM_SSP_STATUS_FIFO_OVRFLW           0x200
-#define BF_SSP_STATUS_FIFO_OVRFLW(v)        (((v) << 9) & 0x200)
-#define BP_SSP_STATUS_FIFO_FULL             8
-#define BM_SSP_STATUS_FIFO_FULL             0x100
-#define BF_SSP_STATUS_FIFO_FULL(v)          (((v) << 8) & 0x100)
-#define BP_SSP_STATUS_RSVD1                 6
-#define BM_SSP_STATUS_RSVD1                 0xc0
-#define BF_SSP_STATUS_RSVD1(v)              (((v) << 6) & 0xc0)
-#define BP_SSP_STATUS_FIFO_EMPTY            5
-#define BM_SSP_STATUS_FIFO_EMPTY            0x20
-#define BF_SSP_STATUS_FIFO_EMPTY(v)         (((v) << 5) & 0x20)
-#define BP_SSP_STATUS_FIFO_UNDRFLW          4
-#define BM_SSP_STATUS_FIFO_UNDRFLW          0x10
-#define BF_SSP_STATUS_FIFO_UNDRFLW(v)       (((v) << 4) & 0x10)
-#define BP_SSP_STATUS_CMD_BUSY              3
-#define BM_SSP_STATUS_CMD_BUSY              0x8
-#define BF_SSP_STATUS_CMD_BUSY(v)           (((v) << 3) & 0x8)
-#define BP_SSP_STATUS_DATA_BUSY             2
-#define BM_SSP_STATUS_DATA_BUSY             0x4
-#define BF_SSP_STATUS_DATA_BUSY(v)          (((v) << 2) & 0x4)
-#define BP_SSP_STATUS_RSVD0                 1
-#define BM_SSP_STATUS_RSVD0                 0x2
-#define BF_SSP_STATUS_RSVD0(v)              (((v) << 1) & 0x2)
-#define BP_SSP_STATUS_BUSY                  0
-#define BM_SSP_STATUS_BUSY                  0x1
-#define BF_SSP_STATUS_BUSY(v)               (((v) << 0) & 0x1)
-
-/**
- * Register: HW_SSP_DEBUG
- * Address: 0x100
- * SCT: no
-*/
-#define HW_SSP_DEBUG(d)                     (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x100))
-#define BP_SSP_DEBUG_DATACRC_ERR            28
-#define BM_SSP_DEBUG_DATACRC_ERR            0xf0000000
-#define BF_SSP_DEBUG_DATACRC_ERR(v)         (((v) << 28) & 0xf0000000)
-#define BP_SSP_DEBUG_DATA_STALL             27
-#define BM_SSP_DEBUG_DATA_STALL             0x8000000
-#define BF_SSP_DEBUG_DATA_STALL(v)          (((v) << 27) & 0x8000000)
-#define BP_SSP_DEBUG_DAT_SM                 24
-#define BM_SSP_DEBUG_DAT_SM                 0x7000000
-#define BV_SSP_DEBUG_DAT_SM__DSM_IDLE       0x0
-#define BV_SSP_DEBUG_DAT_SM__DSM_WORD       0x2
-#define BV_SSP_DEBUG_DAT_SM__DSM_CRC1       0x3
-#define BV_SSP_DEBUG_DAT_SM__DSM_CRC2       0x4
-#define BV_SSP_DEBUG_DAT_SM__DSM_END        0x5
-#define BF_SSP_DEBUG_DAT_SM(v)              (((v) << 24) & 0x7000000)
-#define BF_SSP_DEBUG_DAT_SM_V(v)            ((BV_SSP_DEBUG_DAT_SM__##v << 24) & 0x7000000)
-#define BP_SSP_DEBUG_MSTK_SM                20
-#define BM_SSP_DEBUG_MSTK_SM                0xf00000
-#define BV_SSP_DEBUG_MSTK_SM__MSTK_IDLE     0x0
-#define BV_SSP_DEBUG_MSTK_SM__MSTK_CKON     0x1
-#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS1      0x2
-#define BV_SSP_DEBUG_MSTK_SM__MSTK_TPC      0x3
-#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS2      0x4
-#define BV_SSP_DEBUG_MSTK_SM__MSTK_HDSHK    0x5
-#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS3      0x6
-#define BV_SSP_DEBUG_MSTK_SM__MSTK_RW       0x7
-#define BV_SSP_DEBUG_MSTK_SM__MSTK_CRC1     0x8
-#define BV_SSP_DEBUG_MSTK_SM__MSTK_CRC2     0x9
-#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS0      0xa
-#define BV_SSP_DEBUG_MSTK_SM__MSTK_END1     0xb
-#define BV_SSP_DEBUG_MSTK_SM__MSTK_END2W    0xc
-#define BV_SSP_DEBUG_MSTK_SM__MSTK_END2R    0xd
-#define BV_SSP_DEBUG_MSTK_SM__MSTK_DONE     0xe
-#define BF_SSP_DEBUG_MSTK_SM(v)             (((v) << 20) & 0xf00000)
-#define BF_SSP_DEBUG_MSTK_SM_V(v)           ((BV_SSP_DEBUG_MSTK_SM__##v << 20) & 0xf00000)
-#define BP_SSP_DEBUG_CMD_OE                 19
-#define BM_SSP_DEBUG_CMD_OE                 0x80000
-#define BF_SSP_DEBUG_CMD_OE(v)              (((v) << 19) & 0x80000)
-#define BP_SSP_DEBUG_DMA_SM                 16
-#define BM_SSP_DEBUG_DMA_SM                 0x70000
-#define BV_SSP_DEBUG_DMA_SM__DMA_IDLE       0x0
-#define BV_SSP_DEBUG_DMA_SM__DMA_DMAREQ     0x1
-#define BV_SSP_DEBUG_DMA_SM__DMA_DMAACK     0x2
-#define BV_SSP_DEBUG_DMA_SM__DMA_STALL      0x3
-#define BV_SSP_DEBUG_DMA_SM__DMA_BUSY       0x4
-#define BV_SSP_DEBUG_DMA_SM__DMA_DONE       0x5
-#define BV_SSP_DEBUG_DMA_SM__DMA_COUNT      0x6
-#define BF_SSP_DEBUG_DMA_SM(v)              (((v) << 16) & 0x70000)
-#define BF_SSP_DEBUG_DMA_SM_V(v)            ((BV_SSP_DEBUG_DMA_SM__##v << 16) & 0x70000)
-#define BP_SSP_DEBUG_MMC_SM                 12
-#define BM_SSP_DEBUG_MMC_SM                 0xf000
-#define BV_SSP_DEBUG_MMC_SM__MMC_IDLE       0x0
-#define BV_SSP_DEBUG_MMC_SM__MMC_CMD        0x1
-#define BV_SSP_DEBUG_MMC_SM__MMC_TRC        0x2
-#define BV_SSP_DEBUG_MMC_SM__MMC_RESP       0x3
-#define BV_SSP_DEBUG_MMC_SM__MMC_RPRX       0x4
-#define BV_SSP_DEBUG_MMC_SM__MMC_TX         0x5
-#define BV_SSP_DEBUG_MMC_SM__MMC_CTOK       0x6
-#define BV_SSP_DEBUG_MMC_SM__MMC_RX         0x7
-#define BV_SSP_DEBUG_MMC_SM__MMC_CCS        0x8
-#define BV_SSP_DEBUG_MMC_SM__MMC_PUP        0x9
-#define BV_SSP_DEBUG_MMC_SM__MMC_WAIT       0xa
-#define BF_SSP_DEBUG_MMC_SM(v)              (((v) << 12) & 0xf000)
-#define BF_SSP_DEBUG_MMC_SM_V(v)            ((BV_SSP_DEBUG_MMC_SM__##v << 12) & 0xf000)
-#define BP_SSP_DEBUG_CMD_SM                 10
-#define BM_SSP_DEBUG_CMD_SM                 0xc00
-#define BV_SSP_DEBUG_CMD_SM__CSM_IDLE       0x0
-#define BV_SSP_DEBUG_CMD_SM__CSM_INDEX      0x1
-#define BV_SSP_DEBUG_CMD_SM__CSM_ARG        0x2
-#define BV_SSP_DEBUG_CMD_SM__CSM_CRC        0x3
-#define BF_SSP_DEBUG_CMD_SM(v)              (((v) << 10) & 0xc00)
-#define BF_SSP_DEBUG_CMD_SM_V(v)            ((BV_SSP_DEBUG_CMD_SM__##v << 10) & 0xc00)
-#define BP_SSP_DEBUG_SSP_CMD                9
-#define BM_SSP_DEBUG_SSP_CMD                0x200
-#define BF_SSP_DEBUG_SSP_CMD(v)             (((v) << 9) & 0x200)
-#define BP_SSP_DEBUG_SSP_RESP               8
-#define BM_SSP_DEBUG_SSP_RESP               0x100
-#define BF_SSP_DEBUG_SSP_RESP(v)            (((v) << 8) & 0x100)
-#define BP_SSP_DEBUG_SSP_RXD                0
-#define BM_SSP_DEBUG_SSP_RXD                0xff
-#define BF_SSP_DEBUG_SSP_RXD(v)             (((v) << 0) & 0xff)
-
-/**
- * Register: HW_SSP_VERSION
- * Address: 0x110
- * SCT: no
-*/
-#define HW_SSP_VERSION(d)       (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x110))
-#define BP_SSP_VERSION_MAJOR    24
-#define BM_SSP_VERSION_MAJOR    0xff000000
-#define BF_SSP_VERSION_MAJOR(v) (((v) << 24) & 0xff000000)
-#define BP_SSP_VERSION_MINOR    16
-#define BM_SSP_VERSION_MINOR    0xff0000
-#define BF_SSP_VERSION_MINOR(v) (((v) << 16) & 0xff0000)
-#define BP_SSP_VERSION_STEP     0
-#define BM_SSP_VERSION_STEP     0xffff
-#define BF_SSP_VERSION_STEP(v)  (((v) << 0) & 0xffff)
-
-#endif /* __HEADERGEN__IMX233__SSP__H__ */
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-sydma.h b/firmware/target/arm/imx233/regs/imx233/regs-sydma.h
deleted file mode 100644
index 7af7ac901a..0000000000
--- a/firmware/target/arm/imx233/regs/imx233/regs-sydma.h
+++ /dev/null
@@ -1,194 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: imx233:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__IMX233__SYDMA__H__
-#define __HEADERGEN__IMX233__SYDMA__H__
-
-#define REGS_SYDMA_BASE (0x80026000)
-
-#define REGS_SYDMA_VERSION "3.2.0"
-
-/**
- * Register: HW_SYDMA_CTRL
- * Address: 0
- * SCT: yes
-*/
-#define HW_SYDMA_CTRL                           (*(volatile unsigned long *)(REGS_SYDMA_BASE + 0x0 + 0x0))
-#define HW_SYDMA_CTRL_SET                       (*(volatile unsigned long *)(REGS_SYDMA_BASE + 0x0 + 0x4))
-#define HW_SYDMA_CTRL_CLR                       (*(volatile unsigned long *)(REGS_SYDMA_BASE + 0x0 + 0x8))
-#define HW_SYDMA_CTRL_TOG                       (*(volatile unsigned long *)(REGS_SYDMA_BASE + 0x0 + 0xc))
-#define BP_SYDMA_CTRL_SFTRST                    31
-#define BM_SYDMA_CTRL_SFTRST                    0x80000000
-#define BV_SYDMA_CTRL_SFTRST__RUN               0x0
-#define BV_SYDMA_CTRL_SFTRST__RESET             0x1
-#define BF_SYDMA_CTRL_SFTRST(v)                 (((v) << 31) & 0x80000000)
-#define BF_SYDMA_CTRL_SFTRST_V(v)               ((BV_SYDMA_CTRL_SFTRST__##v << 31) & 0x80000000)
-#define BP_SYDMA_CTRL_CLKGATE                   30
-#define BM_SYDMA_CTRL_CLKGATE                   0x40000000
-#define BV_SYDMA_CTRL_CLKGATE__RUN              0x0
-#define BV_SYDMA_CTRL_CLKGATE__NO_CLKS          0x1
-#define BF_SYDMA_CTRL_CLKGATE(v)                (((v) << 30) & 0x40000000)
-#define BF_SYDMA_CTRL_CLKGATE_V(v)              ((BV_SYDMA_CTRL_CLKGATE__##v << 30) & 0x40000000)
-#define BP_SYDMA_CTRL_RSVD1                     10
-#define BM_SYDMA_CTRL_RSVD1                     0x3ffffc00
-#define BF_SYDMA_CTRL_RSVD1(v)                  (((v) << 10) & 0x3ffffc00)
-#define BP_SYDMA_CTRL_COMPLETE_IRQ_EN           9
-#define BM_SYDMA_CTRL_COMPLETE_IRQ_EN           0x200
-#define BV_SYDMA_CTRL_COMPLETE_IRQ_EN__DISABLED 0x0
-#define BV_SYDMA_CTRL_COMPLETE_IRQ_EN__ENABLED  0x1
-#define BF_SYDMA_CTRL_COMPLETE_IRQ_EN(v)        (((v) << 9) & 0x200)
-#define BF_SYDMA_CTRL_COMPLETE_IRQ_EN_V(v)      ((BV_SYDMA_CTRL_COMPLETE_IRQ_EN__##v << 9) & 0x200)
-#define BP_SYDMA_CTRL_RSVD0                     3
-#define BM_SYDMA_CTRL_RSVD0                     0x1f8
-#define BF_SYDMA_CTRL_RSVD0(v)                  (((v) << 3) & 0x1f8)
-#define BP_SYDMA_CTRL_ERROR_IRQ                 2
-#define BM_SYDMA_CTRL_ERROR_IRQ                 0x4
-#define BF_SYDMA_CTRL_ERROR_IRQ(v)              (((v) << 2) & 0x4)
-#define BP_SYDMA_CTRL_COMPLETE_IRQ              1
-#define BM_SYDMA_CTRL_COMPLETE_IRQ              0x2
-#define BF_SYDMA_CTRL_COMPLETE_IRQ(v)           (((v) << 1) & 0x2)
-#define BP_SYDMA_CTRL_RUN                       0
-#define BM_SYDMA_CTRL_RUN                       0x1
-#define BV_SYDMA_CTRL_RUN__HALT                 0x0
-#define BV_SYDMA_CTRL_RUN__RUN                  0x1
-#define BF_SYDMA_CTRL_RUN(v)                    (((v) << 0) & 0x1)
-#define BF_SYDMA_CTRL_RUN_V(v)                  ((BV_SYDMA_CTRL_RUN__##v << 0) & 0x1)
-
-/**
- * Register: HW_SYDMA_RADDR
- * Address: 0x10
- * SCT: no
-*/
-#define HW_SYDMA_RADDR              (*(volatile unsigned long *)(REGS_SYDMA_BASE + 0x10))
-#define BP_SYDMA_RADDR_RSRC_ADDR    0
-#define BM_SYDMA_RADDR_RSRC_ADDR    0xffffffff
-#define BF_SYDMA_RADDR_RSRC_ADDR(v) (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_SYDMA_WADDR
- * Address: 0x20
- * SCT: no
-*/
-#define HW_SYDMA_WADDR              (*(volatile unsigned long *)(REGS_SYDMA_BASE + 0x20))
-#define BP_SYDMA_WADDR_WSRC_ADDR    0
-#define BM_SYDMA_WADDR_WSRC_ADDR    0xffffffff
-#define BF_SYDMA_WADDR_WSRC_ADDR(v) (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_SYDMA_XFER_COUNT
- * Address: 0x30
- * SCT: no
-*/
-#define HW_SYDMA_XFER_COUNT         (*(volatile unsigned long *)(REGS_SYDMA_BASE + 0x30))
-#define BP_SYDMA_XFER_COUNT_SIZE    0
-#define BM_SYDMA_XFER_COUNT_SIZE    0xffffffff
-#define BF_SYDMA_XFER_COUNT_SIZE(v) (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_SYDMA_BURST
- * Address: 0x40
- * SCT: no
-*/
-#define HW_SYDMA_BURST              (*(volatile unsigned long *)(REGS_SYDMA_BASE + 0x40))
-#define BP_SYDMA_BURST_RSVD0        4
-#define BM_SYDMA_BURST_RSVD0        0xfffffff0
-#define BF_SYDMA_BURST_RSVD0(v)     (((v) << 4) & 0xfffffff0)
-#define BP_SYDMA_BURST_WLEN         2
-#define BM_SYDMA_BURST_WLEN         0xc
-#define BV_SYDMA_BURST_WLEN__1      0x0
-#define BV_SYDMA_BURST_WLEN__2      0x1
-#define BV_SYDMA_BURST_WLEN__4      0x2
-#define BV_SYDMA_BURST_WLEN__8      0x3
-#define BF_SYDMA_BURST_WLEN(v)      (((v) << 2) & 0xc)
-#define BF_SYDMA_BURST_WLEN_V(v)    ((BV_SYDMA_BURST_WLEN__##v << 2) & 0xc)
-#define BP_SYDMA_BURST_RLEN         0
-#define BM_SYDMA_BURST_RLEN         0x3
-#define BV_SYDMA_BURST_RLEN__1      0x0
-#define BV_SYDMA_BURST_RLEN__2      0x1
-#define BV_SYDMA_BURST_RLEN__4      0x2
-#define BV_SYDMA_BURST_RLEN__8      0x3
-#define BF_SYDMA_BURST_RLEN(v)      (((v) << 0) & 0x3)
-#define BF_SYDMA_BURST_RLEN_V(v)    ((BV_SYDMA_BURST_RLEN__##v << 0) & 0x3)
-
-/**
- * Register: HW_SYDMA_DACK
- * Address: 0x50
- * SCT: no
-*/
-#define HW_SYDMA_DACK           (*(volatile unsigned long *)(REGS_SYDMA_BASE + 0x50))
-#define BP_SYDMA_DACK_RSVD0     8
-#define BM_SYDMA_DACK_RSVD0     0xffffff00
-#define BF_SYDMA_DACK_RSVD0(v)  (((v) << 8) & 0xffffff00)
-#define BP_SYDMA_DACK_WDELAY    4
-#define BM_SYDMA_DACK_WDELAY    0xf0
-#define BF_SYDMA_DACK_WDELAY(v) (((v) << 4) & 0xf0)
-#define BP_SYDMA_DACK_RDELAY    0
-#define BM_SYDMA_DACK_RDELAY    0xf
-#define BF_SYDMA_DACK_RDELAY(v) (((v) << 0) & 0xf)
-
-/**
- * Register: HW_SYDMA_DEBUG0
- * Address: 0x100
- * SCT: no
-*/
-#define HW_SYDMA_DEBUG0         (*(volatile unsigned long *)(REGS_SYDMA_BASE + 0x100))
-#define BP_SYDMA_DEBUG0_DATA    0
-#define BM_SYDMA_DEBUG0_DATA    0xffffffff
-#define BF_SYDMA_DEBUG0_DATA(v) (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_SYDMA_DEBUG1
- * Address: 0x110
- * SCT: no
-*/
-#define HW_SYDMA_DEBUG1         (*(volatile unsigned long *)(REGS_SYDMA_BASE + 0x110))
-#define BP_SYDMA_DEBUG1_DATA    0
-#define BM_SYDMA_DEBUG1_DATA    0xffffffff
-#define BF_SYDMA_DEBUG1_DATA(v) (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_SYDMA_DEBUG2
- * Address: 0x120
- * SCT: no
-*/
-#define HW_SYDMA_DEBUG2         (*(volatile unsigned long *)(REGS_SYDMA_BASE + 0x120))
-#define BP_SYDMA_DEBUG2_DATA    0
-#define BM_SYDMA_DEBUG2_DATA    0xffffffff
-#define BF_SYDMA_DEBUG2_DATA(v) (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_SYDMA_VERSION
- * Address: 0x130
- * SCT: no
-*/
-#define HW_SYDMA_VERSION            (*(volatile unsigned long *)(REGS_SYDMA_BASE + 0x130))
-#define BP_SYDMA_VERSION_MAJOR      24
-#define BM_SYDMA_VERSION_MAJOR      0xff000000
-#define BF_SYDMA_VERSION_MAJOR(v)   (((v) << 24) & 0xff000000)
-#define BP_SYDMA_VERSION_MINOR      16
-#define BM_SYDMA_VERSION_MINOR      0xff0000
-#define BF_SYDMA_VERSION_MINOR(v)   (((v) << 16) & 0xff0000)
-#define BP_SYDMA_VERSION_STEP       0
-#define BM_SYDMA_VERSION_STEP       0xffff
-#define BF_SYDMA_VERSION_STEP(v)    (((v) << 0) & 0xffff)
-
-#endif /* __HEADERGEN__IMX233__SYDMA__H__ */
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-timrot.h b/firmware/target/arm/imx233/regs/imx233/regs-timrot.h
deleted file mode 100644
index 0ef8b0d08e..0000000000
--- a/firmware/target/arm/imx233/regs/imx233/regs-timrot.h
+++ /dev/null
@@ -1,307 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: imx233:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__IMX233__TIMROT__H__
-#define __HEADERGEN__IMX233__TIMROT__H__
-
-#define REGS_TIMROT_BASE (0x80068000)
-
-#define REGS_TIMROT_VERSION "3.2.0"
-
-/**
- * Register: HW_TIMROT_ROTCTRL
- * Address: 0
- * SCT: yes
-*/
-#define HW_TIMROT_ROTCTRL                       (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x0 + 0x0))
-#define HW_TIMROT_ROTCTRL_SET                   (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x0 + 0x4))
-#define HW_TIMROT_ROTCTRL_CLR                   (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x0 + 0x8))
-#define HW_TIMROT_ROTCTRL_TOG                   (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x0 + 0xc))
-#define BP_TIMROT_ROTCTRL_SFTRST                31
-#define BM_TIMROT_ROTCTRL_SFTRST                0x80000000
-#define BF_TIMROT_ROTCTRL_SFTRST(v)             (((v) << 31) & 0x80000000)
-#define BP_TIMROT_ROTCTRL_CLKGATE               30
-#define BM_TIMROT_ROTCTRL_CLKGATE               0x40000000
-#define BF_TIMROT_ROTCTRL_CLKGATE(v)            (((v) << 30) & 0x40000000)
-#define BP_TIMROT_ROTCTRL_ROTARY_PRESENT        29
-#define BM_TIMROT_ROTCTRL_ROTARY_PRESENT        0x20000000
-#define BF_TIMROT_ROTCTRL_ROTARY_PRESENT(v)     (((v) << 29) & 0x20000000)
-#define BP_TIMROT_ROTCTRL_TIM3_PRESENT          28
-#define BM_TIMROT_ROTCTRL_TIM3_PRESENT          0x10000000
-#define BF_TIMROT_ROTCTRL_TIM3_PRESENT(v)       (((v) << 28) & 0x10000000)
-#define BP_TIMROT_ROTCTRL_TIM2_PRESENT          27
-#define BM_TIMROT_ROTCTRL_TIM2_PRESENT          0x8000000
-#define BF_TIMROT_ROTCTRL_TIM2_PRESENT(v)       (((v) << 27) & 0x8000000)
-#define BP_TIMROT_ROTCTRL_TIM1_PRESENT          26
-#define BM_TIMROT_ROTCTRL_TIM1_PRESENT          0x4000000
-#define BF_TIMROT_ROTCTRL_TIM1_PRESENT(v)       (((v) << 26) & 0x4000000)
-#define BP_TIMROT_ROTCTRL_TIM0_PRESENT          25
-#define BM_TIMROT_ROTCTRL_TIM0_PRESENT          0x2000000
-#define BF_TIMROT_ROTCTRL_TIM0_PRESENT(v)       (((v) << 25) & 0x2000000)
-#define BP_TIMROT_ROTCTRL_STATE                 22
-#define BM_TIMROT_ROTCTRL_STATE                 0x1c00000
-#define BF_TIMROT_ROTCTRL_STATE(v)              (((v) << 22) & 0x1c00000)
-#define BP_TIMROT_ROTCTRL_DIVIDER               16
-#define BM_TIMROT_ROTCTRL_DIVIDER               0x3f0000
-#define BF_TIMROT_ROTCTRL_DIVIDER(v)            (((v) << 16) & 0x3f0000)
-#define BP_TIMROT_ROTCTRL_RSRVD3                13
-#define BM_TIMROT_ROTCTRL_RSRVD3                0xe000
-#define BF_TIMROT_ROTCTRL_RSRVD3(v)             (((v) << 13) & 0xe000)
-#define BP_TIMROT_ROTCTRL_RELATIVE              12
-#define BM_TIMROT_ROTCTRL_RELATIVE              0x1000
-#define BF_TIMROT_ROTCTRL_RELATIVE(v)           (((v) << 12) & 0x1000)
-#define BP_TIMROT_ROTCTRL_OVERSAMPLE            10
-#define BM_TIMROT_ROTCTRL_OVERSAMPLE            0xc00
-#define BV_TIMROT_ROTCTRL_OVERSAMPLE__8X        0x0
-#define BV_TIMROT_ROTCTRL_OVERSAMPLE__4X        0x1
-#define BV_TIMROT_ROTCTRL_OVERSAMPLE__2X        0x2
-#define BV_TIMROT_ROTCTRL_OVERSAMPLE__1X        0x3
-#define BF_TIMROT_ROTCTRL_OVERSAMPLE(v)         (((v) << 10) & 0xc00)
-#define BF_TIMROT_ROTCTRL_OVERSAMPLE_V(v)       ((BV_TIMROT_ROTCTRL_OVERSAMPLE__##v << 10) & 0xc00)
-#define BP_TIMROT_ROTCTRL_POLARITY_B            9
-#define BM_TIMROT_ROTCTRL_POLARITY_B            0x200
-#define BF_TIMROT_ROTCTRL_POLARITY_B(v)         (((v) << 9) & 0x200)
-#define BP_TIMROT_ROTCTRL_POLARITY_A            8
-#define BM_TIMROT_ROTCTRL_POLARITY_A            0x100
-#define BF_TIMROT_ROTCTRL_POLARITY_A(v)         (((v) << 8) & 0x100)
-#define BP_TIMROT_ROTCTRL_RSRVD2                7
-#define BM_TIMROT_ROTCTRL_RSRVD2                0x80
-#define BF_TIMROT_ROTCTRL_RSRVD2(v)             (((v) << 7) & 0x80)
-#define BP_TIMROT_ROTCTRL_SELECT_B              4
-#define BM_TIMROT_ROTCTRL_SELECT_B              0x70
-#define BV_TIMROT_ROTCTRL_SELECT_B__NEVER_TICK  0x0
-#define BV_TIMROT_ROTCTRL_SELECT_B__PWM0        0x1
-#define BV_TIMROT_ROTCTRL_SELECT_B__PWM1        0x2
-#define BV_TIMROT_ROTCTRL_SELECT_B__PWM2        0x3
-#define BV_TIMROT_ROTCTRL_SELECT_B__PWM3        0x4
-#define BV_TIMROT_ROTCTRL_SELECT_B__PWM4        0x5
-#define BV_TIMROT_ROTCTRL_SELECT_B__ROTARYA     0x6
-#define BV_TIMROT_ROTCTRL_SELECT_B__ROTARYB     0x7
-#define BF_TIMROT_ROTCTRL_SELECT_B(v)           (((v) << 4) & 0x70)
-#define BF_TIMROT_ROTCTRL_SELECT_B_V(v)         ((BV_TIMROT_ROTCTRL_SELECT_B__##v << 4) & 0x70)
-#define BP_TIMROT_ROTCTRL_RSRVD1                3
-#define BM_TIMROT_ROTCTRL_RSRVD1                0x8
-#define BF_TIMROT_ROTCTRL_RSRVD1(v)             (((v) << 3) & 0x8)
-#define BP_TIMROT_ROTCTRL_SELECT_A              0
-#define BM_TIMROT_ROTCTRL_SELECT_A              0x7
-#define BV_TIMROT_ROTCTRL_SELECT_A__NEVER_TICK  0x0
-#define BV_TIMROT_ROTCTRL_SELECT_A__PWM0        0x1
-#define BV_TIMROT_ROTCTRL_SELECT_A__PWM1        0x2
-#define BV_TIMROT_ROTCTRL_SELECT_A__PWM2        0x3
-#define BV_TIMROT_ROTCTRL_SELECT_A__PWM3        0x4
-#define BV_TIMROT_ROTCTRL_SELECT_A__PWM4        0x5
-#define BV_TIMROT_ROTCTRL_SELECT_A__ROTARYA     0x6
-#define BV_TIMROT_ROTCTRL_SELECT_A__ROTARYB     0x7
-#define BF_TIMROT_ROTCTRL_SELECT_A(v)           (((v) << 0) & 0x7)
-#define BF_TIMROT_ROTCTRL_SELECT_A_V(v)         ((BV_TIMROT_ROTCTRL_SELECT_A__##v << 0) & 0x7)
-
-/**
- * Register: HW_TIMROT_ROTCOUNT
- * Address: 0x10
- * SCT: no
-*/
-#define HW_TIMROT_ROTCOUNT              (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x10))
-#define BP_TIMROT_ROTCOUNT_RSRVD1       16
-#define BM_TIMROT_ROTCOUNT_RSRVD1       0xffff0000
-#define BF_TIMROT_ROTCOUNT_RSRVD1(v)    (((v) << 16) & 0xffff0000)
-#define BP_TIMROT_ROTCOUNT_UPDOWN       0
-#define BM_TIMROT_ROTCOUNT_UPDOWN       0xffff
-#define BF_TIMROT_ROTCOUNT_UPDOWN(v)    (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_TIMROT_TIMCTRLn
- * Address: 0x20+n*0x20
- * SCT: yes
-*/
-#define HW_TIMROT_TIMCTRLn(n)                   (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x20+(n)*0x20 + 0x0))
-#define HW_TIMROT_TIMCTRLn_SET(n)               (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x20+(n)*0x20 + 0x4))
-#define HW_TIMROT_TIMCTRLn_CLR(n)               (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x20+(n)*0x20 + 0x8))
-#define HW_TIMROT_TIMCTRLn_TOG(n)               (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x20+(n)*0x20 + 0xc))
-#define BP_TIMROT_TIMCTRLn_RSRVD2               16
-#define BM_TIMROT_TIMCTRLn_RSRVD2               0xffff0000
-#define BF_TIMROT_TIMCTRLn_RSRVD2(v)            (((v) << 16) & 0xffff0000)
-#define BP_TIMROT_TIMCTRLn_IRQ                  15
-#define BM_TIMROT_TIMCTRLn_IRQ                  0x8000
-#define BF_TIMROT_TIMCTRLn_IRQ(v)               (((v) << 15) & 0x8000)
-#define BP_TIMROT_TIMCTRLn_IRQ_EN               14
-#define BM_TIMROT_TIMCTRLn_IRQ_EN               0x4000
-#define BF_TIMROT_TIMCTRLn_IRQ_EN(v)            (((v) << 14) & 0x4000)
-#define BP_TIMROT_TIMCTRLn_RSRVD1               9
-#define BM_TIMROT_TIMCTRLn_RSRVD1               0x3e00
-#define BF_TIMROT_TIMCTRLn_RSRVD1(v)            (((v) << 9) & 0x3e00)
-#define BP_TIMROT_TIMCTRLn_POLARITY             8
-#define BM_TIMROT_TIMCTRLn_POLARITY             0x100
-#define BF_TIMROT_TIMCTRLn_POLARITY(v)          (((v) << 8) & 0x100)
-#define BP_TIMROT_TIMCTRLn_UPDATE               7
-#define BM_TIMROT_TIMCTRLn_UPDATE               0x80
-#define BF_TIMROT_TIMCTRLn_UPDATE(v)            (((v) << 7) & 0x80)
-#define BP_TIMROT_TIMCTRLn_RELOAD               6
-#define BM_TIMROT_TIMCTRLn_RELOAD               0x40
-#define BF_TIMROT_TIMCTRLn_RELOAD(v)            (((v) << 6) & 0x40)
-#define BP_TIMROT_TIMCTRLn_PRESCALE             4
-#define BM_TIMROT_TIMCTRLn_PRESCALE             0x30
-#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_1   0x0
-#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_2   0x1
-#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_4   0x2
-#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_8   0x3
-#define BF_TIMROT_TIMCTRLn_PRESCALE(v)          (((v) << 4) & 0x30)
-#define BF_TIMROT_TIMCTRLn_PRESCALE_V(v)        ((BV_TIMROT_TIMCTRLn_PRESCALE__##v << 4) & 0x30)
-#define BP_TIMROT_TIMCTRLn_SELECT               0
-#define BM_TIMROT_TIMCTRLn_SELECT               0xf
-#define BV_TIMROT_TIMCTRLn_SELECT__NEVER_TICK   0x0
-#define BV_TIMROT_TIMCTRLn_SELECT__PWM0         0x1
-#define BV_TIMROT_TIMCTRLn_SELECT__PWM1         0x2
-#define BV_TIMROT_TIMCTRLn_SELECT__PWM2         0x3
-#define BV_TIMROT_TIMCTRLn_SELECT__PWM3         0x4
-#define BV_TIMROT_TIMCTRLn_SELECT__PWM4         0x5
-#define BV_TIMROT_TIMCTRLn_SELECT__ROTARYA      0x6
-#define BV_TIMROT_TIMCTRLn_SELECT__ROTARYB      0x7
-#define BV_TIMROT_TIMCTRLn_SELECT__32KHZ_XTAL   0x8
-#define BV_TIMROT_TIMCTRLn_SELECT__8KHZ_XTAL    0x9
-#define BV_TIMROT_TIMCTRLn_SELECT__4KHZ_XTAL    0xa
-#define BV_TIMROT_TIMCTRLn_SELECT__1KHZ_XTAL    0xb
-#define BV_TIMROT_TIMCTRLn_SELECT__TICK_ALWAYS  0xc
-#define BF_TIMROT_TIMCTRLn_SELECT(v)            (((v) << 0) & 0xf)
-#define BF_TIMROT_TIMCTRLn_SELECT_V(v)          ((BV_TIMROT_TIMCTRLn_SELECT__##v << 0) & 0xf)
-
-/**
- * Register: HW_TIMROT_TIMCOUNTn
- * Address: 0x30+n*0x20
- * SCT: no
-*/
-#define HW_TIMROT_TIMCOUNTn(n)                  (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x30+(n)*0x20))
-#define BP_TIMROT_TIMCOUNTn_RUNNING_COUNT       16
-#define BM_TIMROT_TIMCOUNTn_RUNNING_COUNT       0xffff0000
-#define BF_TIMROT_TIMCOUNTn_RUNNING_COUNT(v)    (((v) << 16) & 0xffff0000)
-#define BP_TIMROT_TIMCOUNTn_FIXED_COUNT         0
-#define BM_TIMROT_TIMCOUNTn_FIXED_COUNT         0xffff
-#define BF_TIMROT_TIMCOUNTn_FIXED_COUNT(v)      (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_TIMROT_TIMCTRL3
- * Address: 0x80
- * SCT: yes
-*/
-#define HW_TIMROT_TIMCTRL3                          (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x80 + 0x0))
-#define HW_TIMROT_TIMCTRL3_SET                      (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x80 + 0x4))
-#define HW_TIMROT_TIMCTRL3_CLR                      (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x80 + 0x8))
-#define HW_TIMROT_TIMCTRL3_TOG                      (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x80 + 0xc))
-#define BP_TIMROT_TIMCTRL3_RSRVD2                   20
-#define BM_TIMROT_TIMCTRL3_RSRVD2                   0xfff00000
-#define BF_TIMROT_TIMCTRL3_RSRVD2(v)                (((v) << 20) & 0xfff00000)
-#define BP_TIMROT_TIMCTRL3_TEST_SIGNAL              16
-#define BM_TIMROT_TIMCTRL3_TEST_SIGNAL              0xf0000
-#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__NEVER_TICK  0x0
-#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM0        0x1
-#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM1        0x2
-#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM2        0x3
-#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM3        0x4
-#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM4        0x5
-#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__ROTARYA     0x6
-#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__ROTARYB     0x7
-#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__32KHZ_XTAL  0x8
-#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__8KHZ_XTAL   0x9
-#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__4KHZ_XTAL   0xa
-#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__1KHZ_XTAL   0xb
-#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__TICK_ALWAYS 0xc
-#define BF_TIMROT_TIMCTRL3_TEST_SIGNAL(v)           (((v) << 16) & 0xf0000)
-#define BF_TIMROT_TIMCTRL3_TEST_SIGNAL_V(v)         ((BV_TIMROT_TIMCTRL3_TEST_SIGNAL__##v << 16) & 0xf0000)
-#define BP_TIMROT_TIMCTRL3_IRQ                      15
-#define BM_TIMROT_TIMCTRL3_IRQ                      0x8000
-#define BF_TIMROT_TIMCTRL3_IRQ(v)                   (((v) << 15) & 0x8000)
-#define BP_TIMROT_TIMCTRL3_IRQ_EN                   14
-#define BM_TIMROT_TIMCTRL3_IRQ_EN                   0x4000
-#define BF_TIMROT_TIMCTRL3_IRQ_EN(v)                (((v) << 14) & 0x4000)
-#define BP_TIMROT_TIMCTRL3_RSRVD1                   11
-#define BM_TIMROT_TIMCTRL3_RSRVD1                   0x3800
-#define BF_TIMROT_TIMCTRL3_RSRVD1(v)                (((v) << 11) & 0x3800)
-#define BP_TIMROT_TIMCTRL3_DUTY_VALID               10
-#define BM_TIMROT_TIMCTRL3_DUTY_VALID               0x400
-#define BF_TIMROT_TIMCTRL3_DUTY_VALID(v)            (((v) << 10) & 0x400)
-#define BP_TIMROT_TIMCTRL3_DUTY_CYCLE               9
-#define BM_TIMROT_TIMCTRL3_DUTY_CYCLE               0x200
-#define BF_TIMROT_TIMCTRL3_DUTY_CYCLE(v)            (((v) << 9) & 0x200)
-#define BP_TIMROT_TIMCTRL3_POLARITY                 8
-#define BM_TIMROT_TIMCTRL3_POLARITY                 0x100
-#define BF_TIMROT_TIMCTRL3_POLARITY(v)              (((v) << 8) & 0x100)
-#define BP_TIMROT_TIMCTRL3_UPDATE                   7
-#define BM_TIMROT_TIMCTRL3_UPDATE                   0x80
-#define BF_TIMROT_TIMCTRL3_UPDATE(v)                (((v) << 7) & 0x80)
-#define BP_TIMROT_TIMCTRL3_RELOAD                   6
-#define BM_TIMROT_TIMCTRL3_RELOAD                   0x40
-#define BF_TIMROT_TIMCTRL3_RELOAD(v)                (((v) << 6) & 0x40)
-#define BP_TIMROT_TIMCTRL3_PRESCALE                 4
-#define BM_TIMROT_TIMCTRL3_PRESCALE                 0x30
-#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_1       0x0
-#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_2       0x1
-#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_4       0x2
-#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_8       0x3
-#define BF_TIMROT_TIMCTRL3_PRESCALE(v)              (((v) << 4) & 0x30)
-#define BF_TIMROT_TIMCTRL3_PRESCALE_V(v)            ((BV_TIMROT_TIMCTRL3_PRESCALE__##v << 4) & 0x30)
-#define BP_TIMROT_TIMCTRL3_SELECT                   0
-#define BM_TIMROT_TIMCTRL3_SELECT                   0xf
-#define BV_TIMROT_TIMCTRL3_SELECT__NEVER_TICK       0x0
-#define BV_TIMROT_TIMCTRL3_SELECT__PWM0             0x1
-#define BV_TIMROT_TIMCTRL3_SELECT__PWM1             0x2
-#define BV_TIMROT_TIMCTRL3_SELECT__PWM2             0x3
-#define BV_TIMROT_TIMCTRL3_SELECT__PWM3             0x4
-#define BV_TIMROT_TIMCTRL3_SELECT__PWM4             0x5
-#define BV_TIMROT_TIMCTRL3_SELECT__ROTARYA          0x6
-#define BV_TIMROT_TIMCTRL3_SELECT__ROTARYB          0x7
-#define BV_TIMROT_TIMCTRL3_SELECT__32KHZ_XTAL       0x8
-#define BV_TIMROT_TIMCTRL3_SELECT__8KHZ_XTAL        0x9
-#define BV_TIMROT_TIMCTRL3_SELECT__4KHZ_XTAL        0xa
-#define BV_TIMROT_TIMCTRL3_SELECT__1KHZ_XTAL        0xb
-#define BV_TIMROT_TIMCTRL3_SELECT__TICK_ALWAYS      0xc
-#define BF_TIMROT_TIMCTRL3_SELECT(v)                (((v) << 0) & 0xf)
-#define BF_TIMROT_TIMCTRL3_SELECT_V(v)              ((BV_TIMROT_TIMCTRL3_SELECT__##v << 0) & 0xf)
-
-/**
- * Register: HW_TIMROT_TIMCOUNT3
- * Address: 0x90
- * SCT: no
-*/
-#define HW_TIMROT_TIMCOUNT3                         (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x90))
-#define BP_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT       16
-#define BM_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT       0xffff0000
-#define BF_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT(v)    (((v) << 16) & 0xffff0000)
-#define BP_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT        0
-#define BM_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT        0xffff
-#define BF_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT(v)     (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_TIMROT_VERSION
- * Address: 0xa0
- * SCT: no
-*/
-#define HW_TIMROT_VERSION           (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0xa0))
-#define BP_TIMROT_VERSION_MAJOR     24
-#define BM_TIMROT_VERSION_MAJOR     0xff000000
-#define BF_TIMROT_VERSION_MAJOR(v)  (((v) << 24) & 0xff000000)
-#define BP_TIMROT_VERSION_MINOR     16
-#define BM_TIMROT_VERSION_MINOR     0xff0000
-#define BF_TIMROT_VERSION_MINOR(v)  (((v) << 16) & 0xff0000)
-#define BP_TIMROT_VERSION_STEP      0
-#define BM_TIMROT_VERSION_STEP      0xffff
-#define BF_TIMROT_VERSION_STEP(v)   (((v) << 0) & 0xffff)
-
-#endif /* __HEADERGEN__IMX233__TIMROT__H__ */
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-tvenc.h b/firmware/target/arm/imx233/regs/imx233/regs-tvenc.h
deleted file mode 100644
index ff9de38631..0000000000
--- a/firmware/target/arm/imx233/regs/imx233/regs-tvenc.h
+++ /dev/null
@@ -1,776 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: imx233:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__IMX233__TVENC__H__
-#define __HEADERGEN__IMX233__TVENC__H__
-
-#define REGS_TVENC_BASE (0x80038000)
-
-#define REGS_TVENC_VERSION "3.2.0"
-
-/**
- * Register: HW_TVENC_CTRL
- * Address: 0
- * SCT: yes
-*/
-#define HW_TVENC_CTRL                               (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x0 + 0x0))
-#define HW_TVENC_CTRL_SET                           (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x0 + 0x4))
-#define HW_TVENC_CTRL_CLR                           (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x0 + 0x8))
-#define HW_TVENC_CTRL_TOG                           (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x0 + 0xc))
-#define BP_TVENC_CTRL_SFTRST                        31
-#define BM_TVENC_CTRL_SFTRST                        0x80000000
-#define BF_TVENC_CTRL_SFTRST(v)                     (((v) << 31) & 0x80000000)
-#define BP_TVENC_CTRL_CLKGATE                       30
-#define BM_TVENC_CTRL_CLKGATE                       0x40000000
-#define BF_TVENC_CTRL_CLKGATE(v)                    (((v) << 30) & 0x40000000)
-#define BP_TVENC_CTRL_TVENC_MACROVISION_PRESENT     29
-#define BM_TVENC_CTRL_TVENC_MACROVISION_PRESENT     0x20000000
-#define BF_TVENC_CTRL_TVENC_MACROVISION_PRESENT(v)  (((v) << 29) & 0x20000000)
-#define BP_TVENC_CTRL_TVENC_COMPOSITE_PRESENT       28
-#define BM_TVENC_CTRL_TVENC_COMPOSITE_PRESENT       0x10000000
-#define BF_TVENC_CTRL_TVENC_COMPOSITE_PRESENT(v)    (((v) << 28) & 0x10000000)
-#define BP_TVENC_CTRL_TVENC_SVIDEO_PRESENT          27
-#define BM_TVENC_CTRL_TVENC_SVIDEO_PRESENT          0x8000000
-#define BF_TVENC_CTRL_TVENC_SVIDEO_PRESENT(v)       (((v) << 27) & 0x8000000)
-#define BP_TVENC_CTRL_TVENC_COMPONENT_PRESENT       26
-#define BM_TVENC_CTRL_TVENC_COMPONENT_PRESENT       0x4000000
-#define BF_TVENC_CTRL_TVENC_COMPONENT_PRESENT(v)    (((v) << 26) & 0x4000000)
-#define BP_TVENC_CTRL_RSRVD1                        6
-#define BM_TVENC_CTRL_RSRVD1                        0x3ffffc0
-#define BF_TVENC_CTRL_RSRVD1(v)                     (((v) << 6) & 0x3ffffc0)
-#define BP_TVENC_CTRL_DAC_FIFO_NO_WRITE             5
-#define BM_TVENC_CTRL_DAC_FIFO_NO_WRITE             0x20
-#define BF_TVENC_CTRL_DAC_FIFO_NO_WRITE(v)          (((v) << 5) & 0x20)
-#define BP_TVENC_CTRL_DAC_FIFO_NO_READ              4
-#define BM_TVENC_CTRL_DAC_FIFO_NO_READ              0x10
-#define BF_TVENC_CTRL_DAC_FIFO_NO_READ(v)           (((v) << 4) & 0x10)
-#define BP_TVENC_CTRL_DAC_DATA_FIFO_RST             3
-#define BM_TVENC_CTRL_DAC_DATA_FIFO_RST             0x8
-#define BF_TVENC_CTRL_DAC_DATA_FIFO_RST(v)          (((v) << 3) & 0x8)
-#define BP_TVENC_CTRL_RSRVD2                        1
-#define BM_TVENC_CTRL_RSRVD2                        0x6
-#define BF_TVENC_CTRL_RSRVD2(v)                     (((v) << 1) & 0x6)
-#define BP_TVENC_CTRL_DAC_MUX_MODE                  0
-#define BM_TVENC_CTRL_DAC_MUX_MODE                  0x1
-#define BF_TVENC_CTRL_DAC_MUX_MODE(v)               (((v) << 0) & 0x1)
-
-/**
- * Register: HW_TVENC_CONFIG
- * Address: 0x10
- * SCT: yes
-*/
-#define HW_TVENC_CONFIG                     (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x10 + 0x0))
-#define HW_TVENC_CONFIG_SET                 (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x10 + 0x4))
-#define HW_TVENC_CONFIG_CLR                 (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x10 + 0x8))
-#define HW_TVENC_CONFIG_TOG                 (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x10 + 0xc))
-#define BP_TVENC_CONFIG_RSRVD5              28
-#define BM_TVENC_CONFIG_RSRVD5              0xf0000000
-#define BF_TVENC_CONFIG_RSRVD5(v)           (((v) << 28) & 0xf0000000)
-#define BP_TVENC_CONFIG_DEFAULT_PICFORM     27
-#define BM_TVENC_CONFIG_DEFAULT_PICFORM     0x8000000
-#define BF_TVENC_CONFIG_DEFAULT_PICFORM(v)  (((v) << 27) & 0x8000000)
-#define BP_TVENC_CONFIG_YDEL_ADJ            24
-#define BM_TVENC_CONFIG_YDEL_ADJ            0x7000000
-#define BF_TVENC_CONFIG_YDEL_ADJ(v)         (((v) << 24) & 0x7000000)
-#define BP_TVENC_CONFIG_RSRVD4              23
-#define BM_TVENC_CONFIG_RSRVD4              0x800000
-#define BF_TVENC_CONFIG_RSRVD4(v)           (((v) << 23) & 0x800000)
-#define BP_TVENC_CONFIG_RSRVD3              22
-#define BM_TVENC_CONFIG_RSRVD3              0x400000
-#define BF_TVENC_CONFIG_RSRVD3(v)           (((v) << 22) & 0x400000)
-#define BP_TVENC_CONFIG_ADD_YPBPR_PED       21
-#define BM_TVENC_CONFIG_ADD_YPBPR_PED       0x200000
-#define BF_TVENC_CONFIG_ADD_YPBPR_PED(v)    (((v) << 21) & 0x200000)
-#define BP_TVENC_CONFIG_PAL_SHAPE           20
-#define BM_TVENC_CONFIG_PAL_SHAPE           0x100000
-#define BF_TVENC_CONFIG_PAL_SHAPE(v)        (((v) << 20) & 0x100000)
-#define BP_TVENC_CONFIG_NO_PED              19
-#define BM_TVENC_CONFIG_NO_PED              0x80000
-#define BF_TVENC_CONFIG_NO_PED(v)           (((v) << 19) & 0x80000)
-#define BP_TVENC_CONFIG_COLOR_BAR_EN        18
-#define BM_TVENC_CONFIG_COLOR_BAR_EN        0x40000
-#define BF_TVENC_CONFIG_COLOR_BAR_EN(v)     (((v) << 18) & 0x40000)
-#define BP_TVENC_CONFIG_YGAIN_SEL           16
-#define BM_TVENC_CONFIG_YGAIN_SEL           0x30000
-#define BF_TVENC_CONFIG_YGAIN_SEL(v)        (((v) << 16) & 0x30000)
-#define BP_TVENC_CONFIG_CGAIN               14
-#define BM_TVENC_CONFIG_CGAIN               0xc000
-#define BF_TVENC_CONFIG_CGAIN(v)            (((v) << 14) & 0xc000)
-#define BP_TVENC_CONFIG_CLK_PHS             12
-#define BM_TVENC_CONFIG_CLK_PHS             0x3000
-#define BF_TVENC_CONFIG_CLK_PHS(v)          (((v) << 12) & 0x3000)
-#define BP_TVENC_CONFIG_RSRVD2              11
-#define BM_TVENC_CONFIG_RSRVD2              0x800
-#define BF_TVENC_CONFIG_RSRVD2(v)           (((v) << 11) & 0x800)
-#define BP_TVENC_CONFIG_FSYNC_ENBL          10
-#define BM_TVENC_CONFIG_FSYNC_ENBL          0x400
-#define BF_TVENC_CONFIG_FSYNC_ENBL(v)       (((v) << 10) & 0x400)
-#define BP_TVENC_CONFIG_FSYNC_PHS           9
-#define BM_TVENC_CONFIG_FSYNC_PHS           0x200
-#define BF_TVENC_CONFIG_FSYNC_PHS(v)        (((v) << 9) & 0x200)
-#define BP_TVENC_CONFIG_HSYNC_PHS           8
-#define BM_TVENC_CONFIG_HSYNC_PHS           0x100
-#define BF_TVENC_CONFIG_HSYNC_PHS(v)        (((v) << 8) & 0x100)
-#define BP_TVENC_CONFIG_VSYNC_PHS           7
-#define BM_TVENC_CONFIG_VSYNC_PHS           0x80
-#define BF_TVENC_CONFIG_VSYNC_PHS(v)        (((v) << 7) & 0x80)
-#define BP_TVENC_CONFIG_SYNC_MODE           4
-#define BM_TVENC_CONFIG_SYNC_MODE           0x70
-#define BF_TVENC_CONFIG_SYNC_MODE(v)        (((v) << 4) & 0x70)
-#define BP_TVENC_CONFIG_RSRVD1              3
-#define BM_TVENC_CONFIG_RSRVD1              0x8
-#define BF_TVENC_CONFIG_RSRVD1(v)           (((v) << 3) & 0x8)
-#define BP_TVENC_CONFIG_ENCD_MODE           0
-#define BM_TVENC_CONFIG_ENCD_MODE           0x7
-#define BF_TVENC_CONFIG_ENCD_MODE(v)        (((v) << 0) & 0x7)
-
-/**
- * Register: HW_TVENC_FILTCTRL
- * Address: 0x20
- * SCT: yes
-*/
-#define HW_TVENC_FILTCTRL                   (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x20 + 0x0))
-#define HW_TVENC_FILTCTRL_SET               (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x20 + 0x4))
-#define HW_TVENC_FILTCTRL_CLR               (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x20 + 0x8))
-#define HW_TVENC_FILTCTRL_TOG               (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x20 + 0xc))
-#define BP_TVENC_FILTCTRL_RSRVD1            20
-#define BM_TVENC_FILTCTRL_RSRVD1            0xfff00000
-#define BF_TVENC_FILTCTRL_RSRVD1(v)         (((v) << 20) & 0xfff00000)
-#define BP_TVENC_FILTCTRL_YSHARP_BW         19
-#define BM_TVENC_FILTCTRL_YSHARP_BW         0x80000
-#define BF_TVENC_FILTCTRL_YSHARP_BW(v)      (((v) << 19) & 0x80000)
-#define BP_TVENC_FILTCTRL_YD_OFFSETSEL      18
-#define BM_TVENC_FILTCTRL_YD_OFFSETSEL      0x40000
-#define BF_TVENC_FILTCTRL_YD_OFFSETSEL(v)   (((v) << 18) & 0x40000)
-#define BP_TVENC_FILTCTRL_SEL_YLPF          17
-#define BM_TVENC_FILTCTRL_SEL_YLPF          0x20000
-#define BF_TVENC_FILTCTRL_SEL_YLPF(v)       (((v) << 17) & 0x20000)
-#define BP_TVENC_FILTCTRL_SEL_CLPF          16
-#define BM_TVENC_FILTCTRL_SEL_CLPF          0x10000
-#define BF_TVENC_FILTCTRL_SEL_CLPF(v)       (((v) << 16) & 0x10000)
-#define BP_TVENC_FILTCTRL_SEL_YSHARP        15
-#define BM_TVENC_FILTCTRL_SEL_YSHARP        0x8000
-#define BF_TVENC_FILTCTRL_SEL_YSHARP(v)     (((v) << 15) & 0x8000)
-#define BP_TVENC_FILTCTRL_YLPF_COEFSEL      14
-#define BM_TVENC_FILTCTRL_YLPF_COEFSEL      0x4000
-#define BF_TVENC_FILTCTRL_YLPF_COEFSEL(v)   (((v) << 14) & 0x4000)
-#define BP_TVENC_FILTCTRL_COEFSEL_CLPF      13
-#define BM_TVENC_FILTCTRL_COEFSEL_CLPF      0x2000
-#define BF_TVENC_FILTCTRL_COEFSEL_CLPF(v)   (((v) << 13) & 0x2000)
-#define BP_TVENC_FILTCTRL_YS_GAINSGN        12
-#define BM_TVENC_FILTCTRL_YS_GAINSGN        0x1000
-#define BF_TVENC_FILTCTRL_YS_GAINSGN(v)     (((v) << 12) & 0x1000)
-#define BP_TVENC_FILTCTRL_YS_GAINSEL        10
-#define BM_TVENC_FILTCTRL_YS_GAINSEL        0xc00
-#define BF_TVENC_FILTCTRL_YS_GAINSEL(v)     (((v) << 10) & 0xc00)
-#define BP_TVENC_FILTCTRL_RSRVD2            9
-#define BM_TVENC_FILTCTRL_RSRVD2            0x200
-#define BF_TVENC_FILTCTRL_RSRVD2(v)         (((v) << 9) & 0x200)
-#define BP_TVENC_FILTCTRL_RSRVD3            8
-#define BM_TVENC_FILTCTRL_RSRVD3            0x100
-#define BF_TVENC_FILTCTRL_RSRVD3(v)         (((v) << 8) & 0x100)
-#define BP_TVENC_FILTCTRL_RSRVD4            0
-#define BM_TVENC_FILTCTRL_RSRVD4            0xff
-#define BF_TVENC_FILTCTRL_RSRVD4(v)         (((v) << 0) & 0xff)
-
-/**
- * Register: HW_TVENC_SYNCOFFSET
- * Address: 0x30
- * SCT: yes
-*/
-#define HW_TVENC_SYNCOFFSET             (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x30 + 0x0))
-#define HW_TVENC_SYNCOFFSET_SET         (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x30 + 0x4))
-#define HW_TVENC_SYNCOFFSET_CLR         (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x30 + 0x8))
-#define HW_TVENC_SYNCOFFSET_TOG         (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x30 + 0xc))
-#define BP_TVENC_SYNCOFFSET_RSRVD1      31
-#define BM_TVENC_SYNCOFFSET_RSRVD1      0x80000000
-#define BF_TVENC_SYNCOFFSET_RSRVD1(v)   (((v) << 31) & 0x80000000)
-#define BP_TVENC_SYNCOFFSET_HSO         20
-#define BM_TVENC_SYNCOFFSET_HSO         0x7ff00000
-#define BF_TVENC_SYNCOFFSET_HSO(v)      (((v) << 20) & 0x7ff00000)
-#define BP_TVENC_SYNCOFFSET_VSO         10
-#define BM_TVENC_SYNCOFFSET_VSO         0xffc00
-#define BF_TVENC_SYNCOFFSET_VSO(v)      (((v) << 10) & 0xffc00)
-#define BP_TVENC_SYNCOFFSET_HLC         0
-#define BM_TVENC_SYNCOFFSET_HLC         0x3ff
-#define BF_TVENC_SYNCOFFSET_HLC(v)      (((v) << 0) & 0x3ff)
-
-/**
- * Register: HW_TVENC_HTIMINGSYNC0
- * Address: 0x40
- * SCT: yes
-*/
-#define HW_TVENC_HTIMINGSYNC0               (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x40 + 0x0))
-#define HW_TVENC_HTIMINGSYNC0_SET           (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x40 + 0x4))
-#define HW_TVENC_HTIMINGSYNC0_CLR           (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x40 + 0x8))
-#define HW_TVENC_HTIMINGSYNC0_TOG           (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x40 + 0xc))
-#define BP_TVENC_HTIMINGSYNC0_RSRVD2        26
-#define BM_TVENC_HTIMINGSYNC0_RSRVD2        0xfc000000
-#define BF_TVENC_HTIMINGSYNC0_RSRVD2(v)     (((v) << 26) & 0xfc000000)
-#define BP_TVENC_HTIMINGSYNC0_SYNC_END      16
-#define BM_TVENC_HTIMINGSYNC0_SYNC_END      0x3ff0000
-#define BF_TVENC_HTIMINGSYNC0_SYNC_END(v)   (((v) << 16) & 0x3ff0000)
-#define BP_TVENC_HTIMINGSYNC0_RSRVD1        10
-#define BM_TVENC_HTIMINGSYNC0_RSRVD1        0xfc00
-#define BF_TVENC_HTIMINGSYNC0_RSRVD1(v)     (((v) << 10) & 0xfc00)
-#define BP_TVENC_HTIMINGSYNC0_SYNC_STRT     0
-#define BM_TVENC_HTIMINGSYNC0_SYNC_STRT     0x3ff
-#define BF_TVENC_HTIMINGSYNC0_SYNC_STRT(v)  (((v) << 0) & 0x3ff)
-
-/**
- * Register: HW_TVENC_HTIMINGSYNC1
- * Address: 0x50
- * SCT: yes
-*/
-#define HW_TVENC_HTIMINGSYNC1               (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x50 + 0x0))
-#define HW_TVENC_HTIMINGSYNC1_SET           (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x50 + 0x4))
-#define HW_TVENC_HTIMINGSYNC1_CLR           (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x50 + 0x8))
-#define HW_TVENC_HTIMINGSYNC1_TOG           (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x50 + 0xc))
-#define BP_TVENC_HTIMINGSYNC1_RSRVD2        26
-#define BM_TVENC_HTIMINGSYNC1_RSRVD2        0xfc000000
-#define BF_TVENC_HTIMINGSYNC1_RSRVD2(v)     (((v) << 26) & 0xfc000000)
-#define BP_TVENC_HTIMINGSYNC1_SYNC_EQEND    16
-#define BM_TVENC_HTIMINGSYNC1_SYNC_EQEND    0x3ff0000
-#define BF_TVENC_HTIMINGSYNC1_SYNC_EQEND(v) (((v) << 16) & 0x3ff0000)
-#define BP_TVENC_HTIMINGSYNC1_RSRVD1        10
-#define BM_TVENC_HTIMINGSYNC1_RSRVD1        0xfc00
-#define BF_TVENC_HTIMINGSYNC1_RSRVD1(v)     (((v) << 10) & 0xfc00)
-#define BP_TVENC_HTIMINGSYNC1_SYNC_SREND    0
-#define BM_TVENC_HTIMINGSYNC1_SYNC_SREND    0x3ff
-#define BF_TVENC_HTIMINGSYNC1_SYNC_SREND(v) (((v) << 0) & 0x3ff)
-
-/**
- * Register: HW_TVENC_HTIMINGACTIVE
- * Address: 0x60
- * SCT: yes
-*/
-#define HW_TVENC_HTIMINGACTIVE              (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x60 + 0x0))
-#define HW_TVENC_HTIMINGACTIVE_SET          (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x60 + 0x4))
-#define HW_TVENC_HTIMINGACTIVE_CLR          (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x60 + 0x8))
-#define HW_TVENC_HTIMINGACTIVE_TOG          (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x60 + 0xc))
-#define BP_TVENC_HTIMINGACTIVE_RSRVD2       26
-#define BM_TVENC_HTIMINGACTIVE_RSRVD2       0xfc000000
-#define BF_TVENC_HTIMINGACTIVE_RSRVD2(v)    (((v) << 26) & 0xfc000000)
-#define BP_TVENC_HTIMINGACTIVE_ACTV_END     16
-#define BM_TVENC_HTIMINGACTIVE_ACTV_END     0x3ff0000
-#define BF_TVENC_HTIMINGACTIVE_ACTV_END(v)  (((v) << 16) & 0x3ff0000)
-#define BP_TVENC_HTIMINGACTIVE_RSRVD1       10
-#define BM_TVENC_HTIMINGACTIVE_RSRVD1       0xfc00
-#define BF_TVENC_HTIMINGACTIVE_RSRVD1(v)    (((v) << 10) & 0xfc00)
-#define BP_TVENC_HTIMINGACTIVE_ACTV_STRT    0
-#define BM_TVENC_HTIMINGACTIVE_ACTV_STRT    0x3ff
-#define BF_TVENC_HTIMINGACTIVE_ACTV_STRT(v) (((v) << 0) & 0x3ff)
-
-/**
- * Register: HW_TVENC_HTIMINGBURST0
- * Address: 0x70
- * SCT: yes
-*/
-#define HW_TVENC_HTIMINGBURST0                  (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x70 + 0x0))
-#define HW_TVENC_HTIMINGBURST0_SET              (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x70 + 0x4))
-#define HW_TVENC_HTIMINGBURST0_CLR              (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x70 + 0x8))
-#define HW_TVENC_HTIMINGBURST0_TOG              (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x70 + 0xc))
-#define BP_TVENC_HTIMINGBURST0_RSRVD2           26
-#define BM_TVENC_HTIMINGBURST0_RSRVD2           0xfc000000
-#define BF_TVENC_HTIMINGBURST0_RSRVD2(v)        (((v) << 26) & 0xfc000000)
-#define BP_TVENC_HTIMINGBURST0_WBRST_STRT       16
-#define BM_TVENC_HTIMINGBURST0_WBRST_STRT       0x3ff0000
-#define BF_TVENC_HTIMINGBURST0_WBRST_STRT(v)    (((v) << 16) & 0x3ff0000)
-#define BP_TVENC_HTIMINGBURST0_RSRVD1           10
-#define BM_TVENC_HTIMINGBURST0_RSRVD1           0xfc00
-#define BF_TVENC_HTIMINGBURST0_RSRVD1(v)        (((v) << 10) & 0xfc00)
-#define BP_TVENC_HTIMINGBURST0_NBRST_STRT       0
-#define BM_TVENC_HTIMINGBURST0_NBRST_STRT       0x3ff
-#define BF_TVENC_HTIMINGBURST0_NBRST_STRT(v)    (((v) << 0) & 0x3ff)
-
-/**
- * Register: HW_TVENC_HTIMINGBURST1
- * Address: 0x80
- * SCT: yes
-*/
-#define HW_TVENC_HTIMINGBURST1              (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x80 + 0x0))
-#define HW_TVENC_HTIMINGBURST1_SET          (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x80 + 0x4))
-#define HW_TVENC_HTIMINGBURST1_CLR          (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x80 + 0x8))
-#define HW_TVENC_HTIMINGBURST1_TOG          (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x80 + 0xc))
-#define BP_TVENC_HTIMINGBURST1_RSRVD1       10
-#define BM_TVENC_HTIMINGBURST1_RSRVD1       0xfffffc00
-#define BF_TVENC_HTIMINGBURST1_RSRVD1(v)    (((v) << 10) & 0xfffffc00)
-#define BP_TVENC_HTIMINGBURST1_BRST_END     0
-#define BM_TVENC_HTIMINGBURST1_BRST_END     0x3ff
-#define BF_TVENC_HTIMINGBURST1_BRST_END(v)  (((v) << 0) & 0x3ff)
-
-/**
- * Register: HW_TVENC_VTIMING0
- * Address: 0x90
- * SCT: yes
-*/
-#define HW_TVENC_VTIMING0                   (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x90 + 0x0))
-#define HW_TVENC_VTIMING0_SET               (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x90 + 0x4))
-#define HW_TVENC_VTIMING0_CLR               (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x90 + 0x8))
-#define HW_TVENC_VTIMING0_TOG               (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x90 + 0xc))
-#define BP_TVENC_VTIMING0_RSRVD3            26
-#define BM_TVENC_VTIMING0_RSRVD3            0xfc000000
-#define BF_TVENC_VTIMING0_RSRVD3(v)         (((v) << 26) & 0xfc000000)
-#define BP_TVENC_VTIMING0_VSTRT_PREEQ       16
-#define BM_TVENC_VTIMING0_VSTRT_PREEQ       0x3ff0000
-#define BF_TVENC_VTIMING0_VSTRT_PREEQ(v)    (((v) << 16) & 0x3ff0000)
-#define BP_TVENC_VTIMING0_RSRVD2            14
-#define BM_TVENC_VTIMING0_RSRVD2            0xc000
-#define BF_TVENC_VTIMING0_RSRVD2(v)         (((v) << 14) & 0xc000)
-#define BP_TVENC_VTIMING0_VSTRT_ACTV        8
-#define BM_TVENC_VTIMING0_VSTRT_ACTV        0x3f00
-#define BF_TVENC_VTIMING0_VSTRT_ACTV(v)     (((v) << 8) & 0x3f00)
-#define BP_TVENC_VTIMING0_RSRVD1            6
-#define BM_TVENC_VTIMING0_RSRVD1            0xc0
-#define BF_TVENC_VTIMING0_RSRVD1(v)         (((v) << 6) & 0xc0)
-#define BP_TVENC_VTIMING0_VSTRT_SUBPH       0
-#define BM_TVENC_VTIMING0_VSTRT_SUBPH       0x3f
-#define BF_TVENC_VTIMING0_VSTRT_SUBPH(v)    (((v) << 0) & 0x3f)
-
-/**
- * Register: HW_TVENC_VTIMING1
- * Address: 0xa0
- * SCT: yes
-*/
-#define HW_TVENC_VTIMING1                   (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xa0 + 0x0))
-#define HW_TVENC_VTIMING1_SET               (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xa0 + 0x4))
-#define HW_TVENC_VTIMING1_CLR               (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xa0 + 0x8))
-#define HW_TVENC_VTIMING1_TOG               (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xa0 + 0xc))
-#define BP_TVENC_VTIMING1_RSRVD3            30
-#define BM_TVENC_VTIMING1_RSRVD3            0xc0000000
-#define BF_TVENC_VTIMING1_RSRVD3(v)         (((v) << 30) & 0xc0000000)
-#define BP_TVENC_VTIMING1_VSTRT_POSTEQ      24
-#define BM_TVENC_VTIMING1_VSTRT_POSTEQ      0x3f000000
-#define BF_TVENC_VTIMING1_VSTRT_POSTEQ(v)   (((v) << 24) & 0x3f000000)
-#define BP_TVENC_VTIMING1_RSRVD2            22
-#define BM_TVENC_VTIMING1_RSRVD2            0xc00000
-#define BF_TVENC_VTIMING1_RSRVD2(v)         (((v) << 22) & 0xc00000)
-#define BP_TVENC_VTIMING1_VSTRT_SERRA       16
-#define BM_TVENC_VTIMING1_VSTRT_SERRA       0x3f0000
-#define BF_TVENC_VTIMING1_VSTRT_SERRA(v)    (((v) << 16) & 0x3f0000)
-#define BP_TVENC_VTIMING1_RSRVD1            10
-#define BM_TVENC_VTIMING1_RSRVD1            0xfc00
-#define BF_TVENC_VTIMING1_RSRVD1(v)         (((v) << 10) & 0xfc00)
-#define BP_TVENC_VTIMING1_LAST_FLD_LN       0
-#define BM_TVENC_VTIMING1_LAST_FLD_LN       0x3ff
-#define BF_TVENC_VTIMING1_LAST_FLD_LN(v)    (((v) << 0) & 0x3ff)
-
-/**
- * Register: HW_TVENC_MISC
- * Address: 0xb0
- * SCT: yes
-*/
-#define HW_TVENC_MISC                       (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xb0 + 0x0))
-#define HW_TVENC_MISC_SET                   (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xb0 + 0x4))
-#define HW_TVENC_MISC_CLR                   (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xb0 + 0x8))
-#define HW_TVENC_MISC_TOG                   (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xb0 + 0xc))
-#define BP_TVENC_MISC_RSRVD3                25
-#define BM_TVENC_MISC_RSRVD3                0xfe000000
-#define BF_TVENC_MISC_RSRVD3(v)             (((v) << 25) & 0xfe000000)
-#define BP_TVENC_MISC_LPF_RST_OFF           16
-#define BM_TVENC_MISC_LPF_RST_OFF           0x1ff0000
-#define BF_TVENC_MISC_LPF_RST_OFF(v)        (((v) << 16) & 0x1ff0000)
-#define BP_TVENC_MISC_RSRVD2                12
-#define BM_TVENC_MISC_RSRVD2                0xf000
-#define BF_TVENC_MISC_RSRVD2(v)             (((v) << 12) & 0xf000)
-#define BP_TVENC_MISC_NTSC_LN_CNT           11
-#define BM_TVENC_MISC_NTSC_LN_CNT           0x800
-#define BF_TVENC_MISC_NTSC_LN_CNT(v)        (((v) << 11) & 0x800)
-#define BP_TVENC_MISC_PAL_FSC_PHASE_ALT     10
-#define BM_TVENC_MISC_PAL_FSC_PHASE_ALT     0x400
-#define BF_TVENC_MISC_PAL_FSC_PHASE_ALT(v)  (((v) << 10) & 0x400)
-#define BP_TVENC_MISC_FSC_PHASE_RST         8
-#define BM_TVENC_MISC_FSC_PHASE_RST         0x300
-#define BF_TVENC_MISC_FSC_PHASE_RST(v)      (((v) << 8) & 0x300)
-#define BP_TVENC_MISC_BRUCHB                6
-#define BM_TVENC_MISC_BRUCHB                0xc0
-#define BF_TVENC_MISC_BRUCHB(v)             (((v) << 6) & 0xc0)
-#define BP_TVENC_MISC_AGC_LVL_CTRL          4
-#define BM_TVENC_MISC_AGC_LVL_CTRL          0x30
-#define BF_TVENC_MISC_AGC_LVL_CTRL(v)       (((v) << 4) & 0x30)
-#define BP_TVENC_MISC_RSRVD1                3
-#define BM_TVENC_MISC_RSRVD1                0x8
-#define BF_TVENC_MISC_RSRVD1(v)             (((v) << 3) & 0x8)
-#define BP_TVENC_MISC_CS_INVERT_CTRL        2
-#define BM_TVENC_MISC_CS_INVERT_CTRL        0x4
-#define BF_TVENC_MISC_CS_INVERT_CTRL(v)     (((v) << 2) & 0x4)
-#define BP_TVENC_MISC_Y_BLANK_CTRL          0
-#define BM_TVENC_MISC_Y_BLANK_CTRL          0x3
-#define BF_TVENC_MISC_Y_BLANK_CTRL(v)       (((v) << 0) & 0x3)
-
-/**
- * Register: HW_TVENC_COLORSUB0
- * Address: 0xc0
- * SCT: yes
-*/
-#define HW_TVENC_COLORSUB0              (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xc0 + 0x0))
-#define HW_TVENC_COLORSUB0_SET          (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xc0 + 0x4))
-#define HW_TVENC_COLORSUB0_CLR          (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xc0 + 0x8))
-#define HW_TVENC_COLORSUB0_TOG          (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xc0 + 0xc))
-#define BP_TVENC_COLORSUB0_PHASE_INC    0
-#define BM_TVENC_COLORSUB0_PHASE_INC    0xffffffff
-#define BF_TVENC_COLORSUB0_PHASE_INC(v) (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_TVENC_COLORSUB1
- * Address: 0xd0
- * SCT: yes
-*/
-#define HW_TVENC_COLORSUB1                  (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xd0 + 0x0))
-#define HW_TVENC_COLORSUB1_SET              (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xd0 + 0x4))
-#define HW_TVENC_COLORSUB1_CLR              (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xd0 + 0x8))
-#define HW_TVENC_COLORSUB1_TOG              (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xd0 + 0xc))
-#define BP_TVENC_COLORSUB1_PHASE_OFFSET     0
-#define BM_TVENC_COLORSUB1_PHASE_OFFSET     0xffffffff
-#define BF_TVENC_COLORSUB1_PHASE_OFFSET(v)  (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_TVENC_COPYPROTECT
- * Address: 0xe0
- * SCT: yes
-*/
-#define HW_TVENC_COPYPROTECT                    (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xe0 + 0x0))
-#define HW_TVENC_COPYPROTECT_SET                (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xe0 + 0x4))
-#define HW_TVENC_COPYPROTECT_CLR                (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xe0 + 0x8))
-#define HW_TVENC_COPYPROTECT_TOG                (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xe0 + 0xc))
-#define BP_TVENC_COPYPROTECT_RSRVD1             16
-#define BM_TVENC_COPYPROTECT_RSRVD1             0xffff0000
-#define BF_TVENC_COPYPROTECT_RSRVD1(v)          (((v) << 16) & 0xffff0000)
-#define BP_TVENC_COPYPROTECT_WSS_ENBL           15
-#define BM_TVENC_COPYPROTECT_WSS_ENBL           0x8000
-#define BF_TVENC_COPYPROTECT_WSS_ENBL(v)        (((v) << 15) & 0x8000)
-#define BP_TVENC_COPYPROTECT_CGMS_ENBL          14
-#define BM_TVENC_COPYPROTECT_CGMS_ENBL          0x4000
-#define BF_TVENC_COPYPROTECT_CGMS_ENBL(v)       (((v) << 14) & 0x4000)
-#define BP_TVENC_COPYPROTECT_WSS_CGMS_DATA      0
-#define BM_TVENC_COPYPROTECT_WSS_CGMS_DATA      0x3fff
-#define BF_TVENC_COPYPROTECT_WSS_CGMS_DATA(v)   (((v) << 0) & 0x3fff)
-
-/**
- * Register: HW_TVENC_CLOSEDCAPTION
- * Address: 0xf0
- * SCT: yes
-*/
-#define HW_TVENC_CLOSEDCAPTION              (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xf0 + 0x0))
-#define HW_TVENC_CLOSEDCAPTION_SET          (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xf0 + 0x4))
-#define HW_TVENC_CLOSEDCAPTION_CLR          (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xf0 + 0x8))
-#define HW_TVENC_CLOSEDCAPTION_TOG          (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xf0 + 0xc))
-#define BP_TVENC_CLOSEDCAPTION_RSRVD1       20
-#define BM_TVENC_CLOSEDCAPTION_RSRVD1       0xfff00000
-#define BF_TVENC_CLOSEDCAPTION_RSRVD1(v)    (((v) << 20) & 0xfff00000)
-#define BP_TVENC_CLOSEDCAPTION_CC_ENBL      18
-#define BM_TVENC_CLOSEDCAPTION_CC_ENBL      0xc0000
-#define BF_TVENC_CLOSEDCAPTION_CC_ENBL(v)   (((v) << 18) & 0xc0000)
-#define BP_TVENC_CLOSEDCAPTION_CC_FILL      16
-#define BM_TVENC_CLOSEDCAPTION_CC_FILL      0x30000
-#define BF_TVENC_CLOSEDCAPTION_CC_FILL(v)   (((v) << 16) & 0x30000)
-#define BP_TVENC_CLOSEDCAPTION_CC_DATA      0
-#define BM_TVENC_CLOSEDCAPTION_CC_DATA      0xffff
-#define BF_TVENC_CLOSEDCAPTION_CC_DATA(v)   (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_TVENC_COLORBURST
- * Address: 0x140
- * SCT: yes
-*/
-#define HW_TVENC_COLORBURST             (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x140 + 0x0))
-#define HW_TVENC_COLORBURST_SET         (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x140 + 0x4))
-#define HW_TVENC_COLORBURST_CLR         (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x140 + 0x8))
-#define HW_TVENC_COLORBURST_TOG         (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x140 + 0xc))
-#define BP_TVENC_COLORBURST_NBA         24
-#define BM_TVENC_COLORBURST_NBA         0xff000000
-#define BF_TVENC_COLORBURST_NBA(v)      (((v) << 24) & 0xff000000)
-#define BP_TVENC_COLORBURST_PBA         16
-#define BM_TVENC_COLORBURST_PBA         0xff0000
-#define BF_TVENC_COLORBURST_PBA(v)      (((v) << 16) & 0xff0000)
-#define BP_TVENC_COLORBURST_RSRVD1      12
-#define BM_TVENC_COLORBURST_RSRVD1      0xf000
-#define BF_TVENC_COLORBURST_RSRVD1(v)   (((v) << 12) & 0xf000)
-#define BP_TVENC_COLORBURST_RSRVD2      0
-#define BM_TVENC_COLORBURST_RSRVD2      0xfff
-#define BF_TVENC_COLORBURST_RSRVD2(v)   (((v) << 0) & 0xfff)
-
-/**
- * Register: HW_TVENC_MACROVISION0
- * Address: 0x150
- * SCT: yes
-*/
-#define HW_TVENC_MACROVISION0           (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x150 + 0x0))
-#define HW_TVENC_MACROVISION0_SET       (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x150 + 0x4))
-#define HW_TVENC_MACROVISION0_CLR       (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x150 + 0x8))
-#define HW_TVENC_MACROVISION0_TOG       (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x150 + 0xc))
-#define BP_TVENC_MACROVISION0_DATA      0
-#define BM_TVENC_MACROVISION0_DATA      0xffffffff
-#define BF_TVENC_MACROVISION0_DATA(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_TVENC_MACROVISION1
- * Address: 0x160
- * SCT: yes
-*/
-#define HW_TVENC_MACROVISION1           (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x160 + 0x0))
-#define HW_TVENC_MACROVISION1_SET       (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x160 + 0x4))
-#define HW_TVENC_MACROVISION1_CLR       (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x160 + 0x8))
-#define HW_TVENC_MACROVISION1_TOG       (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x160 + 0xc))
-#define BP_TVENC_MACROVISION1_DATA      0
-#define BM_TVENC_MACROVISION1_DATA      0xffffffff
-#define BF_TVENC_MACROVISION1_DATA(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_TVENC_MACROVISION2
- * Address: 0x170
- * SCT: yes
-*/
-#define HW_TVENC_MACROVISION2           (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x170 + 0x0))
-#define HW_TVENC_MACROVISION2_SET       (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x170 + 0x4))
-#define HW_TVENC_MACROVISION2_CLR       (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x170 + 0x8))
-#define HW_TVENC_MACROVISION2_TOG       (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x170 + 0xc))
-#define BP_TVENC_MACROVISION2_DATA      0
-#define BM_TVENC_MACROVISION2_DATA      0xffffffff
-#define BF_TVENC_MACROVISION2_DATA(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_TVENC_MACROVISION3
- * Address: 0x180
- * SCT: yes
-*/
-#define HW_TVENC_MACROVISION3           (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x180 + 0x0))
-#define HW_TVENC_MACROVISION3_SET       (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x180 + 0x4))
-#define HW_TVENC_MACROVISION3_CLR       (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x180 + 0x8))
-#define HW_TVENC_MACROVISION3_TOG       (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x180 + 0xc))
-#define BP_TVENC_MACROVISION3_DATA      0
-#define BM_TVENC_MACROVISION3_DATA      0xffffffff
-#define BF_TVENC_MACROVISION3_DATA(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_TVENC_MACROVISION4
- * Address: 0x190
- * SCT: yes
-*/
-#define HW_TVENC_MACROVISION4               (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x190 + 0x0))
-#define HW_TVENC_MACROVISION4_SET           (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x190 + 0x4))
-#define HW_TVENC_MACROVISION4_CLR           (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x190 + 0x8))
-#define HW_TVENC_MACROVISION4_TOG           (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x190 + 0xc))
-#define BP_TVENC_MACROVISION4_RSRVD2        24
-#define BM_TVENC_MACROVISION4_RSRVD2        0xff000000
-#define BF_TVENC_MACROVISION4_RSRVD2(v)     (((v) << 24) & 0xff000000)
-#define BP_TVENC_MACROVISION4_MACV_TST      16
-#define BM_TVENC_MACROVISION4_MACV_TST      0xff0000
-#define BF_TVENC_MACROVISION4_MACV_TST(v)   (((v) << 16) & 0xff0000)
-#define BP_TVENC_MACROVISION4_RSRVD1        11
-#define BM_TVENC_MACROVISION4_RSRVD1        0xf800
-#define BF_TVENC_MACROVISION4_RSRVD1(v)     (((v) << 11) & 0xf800)
-#define BP_TVENC_MACROVISION4_DATA          0
-#define BM_TVENC_MACROVISION4_DATA          0x7ff
-#define BF_TVENC_MACROVISION4_DATA(v)       (((v) << 0) & 0x7ff)
-
-/**
- * Register: HW_TVENC_DACCTRL
- * Address: 0x1a0
- * SCT: yes
-*/
-#define HW_TVENC_DACCTRL                        (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x1a0 + 0x0))
-#define HW_TVENC_DACCTRL_SET                    (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x1a0 + 0x4))
-#define HW_TVENC_DACCTRL_CLR                    (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x1a0 + 0x8))
-#define HW_TVENC_DACCTRL_TOG                    (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x1a0 + 0xc))
-#define BP_TVENC_DACCTRL_TEST3                  31
-#define BM_TVENC_DACCTRL_TEST3                  0x80000000
-#define BF_TVENC_DACCTRL_TEST3(v)               (((v) << 31) & 0x80000000)
-#define BP_TVENC_DACCTRL_RSRVD1                 30
-#define BM_TVENC_DACCTRL_RSRVD1                 0x40000000
-#define BF_TVENC_DACCTRL_RSRVD1(v)              (((v) << 30) & 0x40000000)
-#define BP_TVENC_DACCTRL_RSRVD2                 29
-#define BM_TVENC_DACCTRL_RSRVD2                 0x20000000
-#define BF_TVENC_DACCTRL_RSRVD2(v)              (((v) << 29) & 0x20000000)
-#define BP_TVENC_DACCTRL_JACK1_DIS_DET_EN       28
-#define BM_TVENC_DACCTRL_JACK1_DIS_DET_EN       0x10000000
-#define BF_TVENC_DACCTRL_JACK1_DIS_DET_EN(v)    (((v) << 28) & 0x10000000)
-#define BP_TVENC_DACCTRL_TEST2                  27
-#define BM_TVENC_DACCTRL_TEST2                  0x8000000
-#define BF_TVENC_DACCTRL_TEST2(v)               (((v) << 27) & 0x8000000)
-#define BP_TVENC_DACCTRL_RSRVD3                 26
-#define BM_TVENC_DACCTRL_RSRVD3                 0x4000000
-#define BF_TVENC_DACCTRL_RSRVD3(v)              (((v) << 26) & 0x4000000)
-#define BP_TVENC_DACCTRL_RSRVD4                 25
-#define BM_TVENC_DACCTRL_RSRVD4                 0x2000000
-#define BF_TVENC_DACCTRL_RSRVD4(v)              (((v) << 25) & 0x2000000)
-#define BP_TVENC_DACCTRL_JACK1_DET_EN           24
-#define BM_TVENC_DACCTRL_JACK1_DET_EN           0x1000000
-#define BF_TVENC_DACCTRL_JACK1_DET_EN(v)        (((v) << 24) & 0x1000000)
-#define BP_TVENC_DACCTRL_TEST1                  23
-#define BM_TVENC_DACCTRL_TEST1                  0x800000
-#define BF_TVENC_DACCTRL_TEST1(v)               (((v) << 23) & 0x800000)
-#define BP_TVENC_DACCTRL_DISABLE_GND_DETECT     22
-#define BM_TVENC_DACCTRL_DISABLE_GND_DETECT     0x400000
-#define BF_TVENC_DACCTRL_DISABLE_GND_DETECT(v)  (((v) << 22) & 0x400000)
-#define BP_TVENC_DACCTRL_JACK_DIS_ADJ           20
-#define BM_TVENC_DACCTRL_JACK_DIS_ADJ           0x300000
-#define BF_TVENC_DACCTRL_JACK_DIS_ADJ(v)        (((v) << 20) & 0x300000)
-#define BP_TVENC_DACCTRL_GAINDN                 19
-#define BM_TVENC_DACCTRL_GAINDN                 0x80000
-#define BF_TVENC_DACCTRL_GAINDN(v)              (((v) << 19) & 0x80000)
-#define BP_TVENC_DACCTRL_GAINUP                 18
-#define BM_TVENC_DACCTRL_GAINUP                 0x40000
-#define BF_TVENC_DACCTRL_GAINUP(v)              (((v) << 18) & 0x40000)
-#define BP_TVENC_DACCTRL_INVERT_CLK             17
-#define BM_TVENC_DACCTRL_INVERT_CLK             0x20000
-#define BF_TVENC_DACCTRL_INVERT_CLK(v)          (((v) << 17) & 0x20000)
-#define BP_TVENC_DACCTRL_SELECT_CLK             16
-#define BM_TVENC_DACCTRL_SELECT_CLK             0x10000
-#define BF_TVENC_DACCTRL_SELECT_CLK(v)          (((v) << 16) & 0x10000)
-#define BP_TVENC_DACCTRL_BYPASS_ACT_CASCODE     15
-#define BM_TVENC_DACCTRL_BYPASS_ACT_CASCODE     0x8000
-#define BF_TVENC_DACCTRL_BYPASS_ACT_CASCODE(v)  (((v) << 15) & 0x8000)
-#define BP_TVENC_DACCTRL_RSRVD5                 14
-#define BM_TVENC_DACCTRL_RSRVD5                 0x4000
-#define BF_TVENC_DACCTRL_RSRVD5(v)              (((v) << 14) & 0x4000)
-#define BP_TVENC_DACCTRL_RSRVD6                 13
-#define BM_TVENC_DACCTRL_RSRVD6                 0x2000
-#define BF_TVENC_DACCTRL_RSRVD6(v)              (((v) << 13) & 0x2000)
-#define BP_TVENC_DACCTRL_PWRUP1                 12
-#define BM_TVENC_DACCTRL_PWRUP1                 0x1000
-#define BF_TVENC_DACCTRL_PWRUP1(v)              (((v) << 12) & 0x1000)
-#define BP_TVENC_DACCTRL_WELL_TOVDD             11
-#define BM_TVENC_DACCTRL_WELL_TOVDD             0x800
-#define BF_TVENC_DACCTRL_WELL_TOVDD(v)          (((v) << 11) & 0x800)
-#define BP_TVENC_DACCTRL_RSRVD7                 10
-#define BM_TVENC_DACCTRL_RSRVD7                 0x400
-#define BF_TVENC_DACCTRL_RSRVD7(v)              (((v) << 10) & 0x400)
-#define BP_TVENC_DACCTRL_RSRVD8                 9
-#define BM_TVENC_DACCTRL_RSRVD8                 0x200
-#define BF_TVENC_DACCTRL_RSRVD8(v)              (((v) << 9) & 0x200)
-#define BP_TVENC_DACCTRL_DUMP_TOVDD1            8
-#define BM_TVENC_DACCTRL_DUMP_TOVDD1            0x100
-#define BF_TVENC_DACCTRL_DUMP_TOVDD1(v)         (((v) << 8) & 0x100)
-#define BP_TVENC_DACCTRL_LOWER_SIGNAL           7
-#define BM_TVENC_DACCTRL_LOWER_SIGNAL           0x80
-#define BF_TVENC_DACCTRL_LOWER_SIGNAL(v)        (((v) << 7) & 0x80)
-#define BP_TVENC_DACCTRL_RVAL                   4
-#define BM_TVENC_DACCTRL_RVAL                   0x70
-#define BF_TVENC_DACCTRL_RVAL(v)                (((v) << 4) & 0x70)
-#define BP_TVENC_DACCTRL_NO_INTERNAL_TERM       3
-#define BM_TVENC_DACCTRL_NO_INTERNAL_TERM       0x8
-#define BF_TVENC_DACCTRL_NO_INTERNAL_TERM(v)    (((v) << 3) & 0x8)
-#define BP_TVENC_DACCTRL_HALF_CURRENT           2
-#define BM_TVENC_DACCTRL_HALF_CURRENT           0x4
-#define BF_TVENC_DACCTRL_HALF_CURRENT(v)        (((v) << 2) & 0x4)
-#define BP_TVENC_DACCTRL_CASC_ADJ               0
-#define BM_TVENC_DACCTRL_CASC_ADJ               0x3
-#define BF_TVENC_DACCTRL_CASC_ADJ(v)            (((v) << 0) & 0x3)
-
-/**
- * Register: HW_TVENC_DACSTATUS
- * Address: 0x1b0
- * SCT: yes
-*/
-#define HW_TVENC_DACSTATUS                      (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x1b0 + 0x0))
-#define HW_TVENC_DACSTATUS_SET                  (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x1b0 + 0x4))
-#define HW_TVENC_DACSTATUS_CLR                  (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x1b0 + 0x8))
-#define HW_TVENC_DACSTATUS_TOG                  (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x1b0 + 0xc))
-#define BP_TVENC_DACSTATUS_RSRVD1               13
-#define BM_TVENC_DACSTATUS_RSRVD1               0xffffe000
-#define BF_TVENC_DACSTATUS_RSRVD1(v)            (((v) << 13) & 0xffffe000)
-#define BP_TVENC_DACSTATUS_RSRVD2               12
-#define BM_TVENC_DACSTATUS_RSRVD2               0x1000
-#define BF_TVENC_DACSTATUS_RSRVD2(v)            (((v) << 12) & 0x1000)
-#define BP_TVENC_DACSTATUS_RSRVD3               11
-#define BM_TVENC_DACSTATUS_RSRVD3               0x800
-#define BF_TVENC_DACSTATUS_RSRVD3(v)            (((v) << 11) & 0x800)
-#define BP_TVENC_DACSTATUS_JACK1_DET_STATUS     10
-#define BM_TVENC_DACSTATUS_JACK1_DET_STATUS     0x400
-#define BF_TVENC_DACSTATUS_JACK1_DET_STATUS(v)  (((v) << 10) & 0x400)
-#define BP_TVENC_DACSTATUS_RSRVD4               9
-#define BM_TVENC_DACSTATUS_RSRVD4               0x200
-#define BF_TVENC_DACSTATUS_RSRVD4(v)            (((v) << 9) & 0x200)
-#define BP_TVENC_DACSTATUS_RSRVD5               8
-#define BM_TVENC_DACSTATUS_RSRVD5               0x100
-#define BF_TVENC_DACSTATUS_RSRVD5(v)            (((v) << 8) & 0x100)
-#define BP_TVENC_DACSTATUS_JACK1_GROUNDED       7
-#define BM_TVENC_DACSTATUS_JACK1_GROUNDED       0x80
-#define BF_TVENC_DACSTATUS_JACK1_GROUNDED(v)    (((v) << 7) & 0x80)
-#define BP_TVENC_DACSTATUS_RSRVD6               6
-#define BM_TVENC_DACSTATUS_RSRVD6               0x40
-#define BF_TVENC_DACSTATUS_RSRVD6(v)            (((v) << 6) & 0x40)
-#define BP_TVENC_DACSTATUS_RSRVD7               5
-#define BM_TVENC_DACSTATUS_RSRVD7               0x20
-#define BF_TVENC_DACSTATUS_RSRVD7(v)            (((v) << 5) & 0x20)
-#define BP_TVENC_DACSTATUS_JACK1_DIS_DET_IRQ    4
-#define BM_TVENC_DACSTATUS_JACK1_DIS_DET_IRQ    0x10
-#define BF_TVENC_DACSTATUS_JACK1_DIS_DET_IRQ(v) (((v) << 4) & 0x10)
-#define BP_TVENC_DACSTATUS_RSRVD8               3
-#define BM_TVENC_DACSTATUS_RSRVD8               0x8
-#define BF_TVENC_DACSTATUS_RSRVD8(v)            (((v) << 3) & 0x8)
-#define BP_TVENC_DACSTATUS_RSRVD9               2
-#define BM_TVENC_DACSTATUS_RSRVD9               0x4
-#define BF_TVENC_DACSTATUS_RSRVD9(v)            (((v) << 2) & 0x4)
-#define BP_TVENC_DACSTATUS_JACK1_DET_IRQ        1
-#define BM_TVENC_DACSTATUS_JACK1_DET_IRQ        0x2
-#define BF_TVENC_DACSTATUS_JACK1_DET_IRQ(v)     (((v) << 1) & 0x2)
-#define BP_TVENC_DACSTATUS_ENIRQ_JACK           0
-#define BM_TVENC_DACSTATUS_ENIRQ_JACK           0x1
-#define BF_TVENC_DACSTATUS_ENIRQ_JACK(v)        (((v) << 0) & 0x1)
-
-/**
- * Register: HW_TVENC_VDACTEST
- * Address: 0x1c0
- * SCT: yes
-*/
-#define HW_TVENC_VDACTEST                           (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x1c0 + 0x0))
-#define HW_TVENC_VDACTEST_SET                       (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x1c0 + 0x4))
-#define HW_TVENC_VDACTEST_CLR                       (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x1c0 + 0x8))
-#define HW_TVENC_VDACTEST_TOG                       (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x1c0 + 0xc))
-#define BP_TVENC_VDACTEST_RSRVD1                    14
-#define BM_TVENC_VDACTEST_RSRVD1                    0xffffc000
-#define BF_TVENC_VDACTEST_RSRVD1(v)                 (((v) << 14) & 0xffffc000)
-#define BP_TVENC_VDACTEST_ENABLE_PIX_INT_GAIN       13
-#define BM_TVENC_VDACTEST_ENABLE_PIX_INT_GAIN       0x2000
-#define BF_TVENC_VDACTEST_ENABLE_PIX_INT_GAIN(v)    (((v) << 13) & 0x2000)
-#define BP_TVENC_VDACTEST_BYPASS_PIX_INT            12
-#define BM_TVENC_VDACTEST_BYPASS_PIX_INT            0x1000
-#define BF_TVENC_VDACTEST_BYPASS_PIX_INT(v)         (((v) << 12) & 0x1000)
-#define BP_TVENC_VDACTEST_BYPASS_PIX_INT_DROOP      11
-#define BM_TVENC_VDACTEST_BYPASS_PIX_INT_DROOP      0x800
-#define BF_TVENC_VDACTEST_BYPASS_PIX_INT_DROOP(v)   (((v) << 11) & 0x800)
-#define BP_TVENC_VDACTEST_TEST_FIFO_FULL            10
-#define BM_TVENC_VDACTEST_TEST_FIFO_FULL            0x400
-#define BF_TVENC_VDACTEST_TEST_FIFO_FULL(v)         (((v) << 10) & 0x400)
-#define BP_TVENC_VDACTEST_DATA                      0
-#define BM_TVENC_VDACTEST_DATA                      0x3ff
-#define BF_TVENC_VDACTEST_DATA(v)                   (((v) << 0) & 0x3ff)
-
-/**
- * Register: HW_TVENC_VERSION
- * Address: 0x1d0
- * SCT: no
-*/
-#define HW_TVENC_VERSION            (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x1d0))
-#define BP_TVENC_VERSION_MAJOR      24
-#define BM_TVENC_VERSION_MAJOR      0xff000000
-#define BF_TVENC_VERSION_MAJOR(v)   (((v) << 24) & 0xff000000)
-#define BP_TVENC_VERSION_MINOR      16
-#define BM_TVENC_VERSION_MINOR      0xff0000
-#define BF_TVENC_VERSION_MINOR(v)   (((v) << 16) & 0xff0000)
-#define BP_TVENC_VERSION_STEP       0
-#define BM_TVENC_VERSION_STEP       0xffff
-#define BF_TVENC_VERSION_STEP(v)    (((v) << 0) & 0xffff)
-
-#endif /* __HEADERGEN__IMX233__TVENC__H__ */
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-uartapp.h b/firmware/target/arm/imx233/regs/imx233/regs-uartapp.h
deleted file mode 100644
index 80d8d8f041..0000000000
--- a/firmware/target/arm/imx233/regs/imx233/regs-uartapp.h
+++ /dev/null
@@ -1,497 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: imx233:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__IMX233__UARTAPP__H__
-#define __HEADERGEN__IMX233__UARTAPP__H__
-
-#define REGS_UARTAPP_BASE(i) ((i) == 1 ? 0x8006c000 : 0x8006e000)
-
-#define REGS_UARTAPP_VERSION "3.2.0"
-
-/**
- * Register: HW_UARTAPP_CTRL0
- * Address: 0
- * SCT: yes
-*/
-#define HW_UARTAPP_CTRL0(d)             (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x0 + 0x0))
-#define HW_UARTAPP_CTRL0_SET(d)         (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x0 + 0x4))
-#define HW_UARTAPP_CTRL0_CLR(d)         (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x0 + 0x8))
-#define HW_UARTAPP_CTRL0_TOG(d)         (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x0 + 0xc))
-#define BP_UARTAPP_CTRL0_SFTRST         31
-#define BM_UARTAPP_CTRL0_SFTRST         0x80000000
-#define BF_UARTAPP_CTRL0_SFTRST(v)      (((v) << 31) & 0x80000000)
-#define BP_UARTAPP_CTRL0_CLKGATE        30
-#define BM_UARTAPP_CTRL0_CLKGATE        0x40000000
-#define BF_UARTAPP_CTRL0_CLKGATE(v)     (((v) << 30) & 0x40000000)
-#define BP_UARTAPP_CTRL0_RUN            29
-#define BM_UARTAPP_CTRL0_RUN            0x20000000
-#define BF_UARTAPP_CTRL0_RUN(v)         (((v) << 29) & 0x20000000)
-#define BP_UARTAPP_CTRL0_RX_SOURCE      28
-#define BM_UARTAPP_CTRL0_RX_SOURCE      0x10000000
-#define BF_UARTAPP_CTRL0_RX_SOURCE(v)   (((v) << 28) & 0x10000000)
-#define BP_UARTAPP_CTRL0_RXTO_ENABLE    27
-#define BM_UARTAPP_CTRL0_RXTO_ENABLE    0x8000000
-#define BF_UARTAPP_CTRL0_RXTO_ENABLE(v) (((v) << 27) & 0x8000000)
-#define BP_UARTAPP_CTRL0_RXTIMEOUT      16
-#define BM_UARTAPP_CTRL0_RXTIMEOUT      0x7ff0000
-#define BF_UARTAPP_CTRL0_RXTIMEOUT(v)   (((v) << 16) & 0x7ff0000)
-#define BP_UARTAPP_CTRL0_XFER_COUNT     0
-#define BM_UARTAPP_CTRL0_XFER_COUNT     0xffff
-#define BF_UARTAPP_CTRL0_XFER_COUNT(v)  (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_UARTAPP_CTRL1
- * Address: 0x10
- * SCT: yes
-*/
-#define HW_UARTAPP_CTRL1(d)             (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x10 + 0x0))
-#define HW_UARTAPP_CTRL1_SET(d)         (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x10 + 0x4))
-#define HW_UARTAPP_CTRL1_CLR(d)         (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x10 + 0x8))
-#define HW_UARTAPP_CTRL1_TOG(d)         (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x10 + 0xc))
-#define BP_UARTAPP_CTRL1_RSVD2          29
-#define BM_UARTAPP_CTRL1_RSVD2          0xe0000000
-#define BF_UARTAPP_CTRL1_RSVD2(v)       (((v) << 29) & 0xe0000000)
-#define BP_UARTAPP_CTRL1_RUN            28
-#define BM_UARTAPP_CTRL1_RUN            0x10000000
-#define BF_UARTAPP_CTRL1_RUN(v)         (((v) << 28) & 0x10000000)
-#define BP_UARTAPP_CTRL1_RSVD1          16
-#define BM_UARTAPP_CTRL1_RSVD1          0xfff0000
-#define BF_UARTAPP_CTRL1_RSVD1(v)       (((v) << 16) & 0xfff0000)
-#define BP_UARTAPP_CTRL1_XFER_COUNT     0
-#define BM_UARTAPP_CTRL1_XFER_COUNT     0xffff
-#define BF_UARTAPP_CTRL1_XFER_COUNT(v)  (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_UARTAPP_CTRL2
- * Address: 0x20
- * SCT: yes
-*/
-#define HW_UARTAPP_CTRL2(d)                         (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x20 + 0x0))
-#define HW_UARTAPP_CTRL2_SET(d)                     (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x20 + 0x4))
-#define HW_UARTAPP_CTRL2_CLR(d)                     (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x20 + 0x8))
-#define HW_UARTAPP_CTRL2_TOG(d)                     (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x20 + 0xc))
-#define BP_UARTAPP_CTRL2_INVERT_RTS                 31
-#define BM_UARTAPP_CTRL2_INVERT_RTS                 0x80000000
-#define BF_UARTAPP_CTRL2_INVERT_RTS(v)              (((v) << 31) & 0x80000000)
-#define BP_UARTAPP_CTRL2_INVERT_CTS                 30
-#define BM_UARTAPP_CTRL2_INVERT_CTS                 0x40000000
-#define BF_UARTAPP_CTRL2_INVERT_CTS(v)              (((v) << 30) & 0x40000000)
-#define BP_UARTAPP_CTRL2_INVERT_TX                  29
-#define BM_UARTAPP_CTRL2_INVERT_TX                  0x20000000
-#define BF_UARTAPP_CTRL2_INVERT_TX(v)               (((v) << 29) & 0x20000000)
-#define BP_UARTAPP_CTRL2_INVERT_RX                  28
-#define BM_UARTAPP_CTRL2_INVERT_RX                  0x10000000
-#define BF_UARTAPP_CTRL2_INVERT_RX(v)               (((v) << 28) & 0x10000000)
-#define BP_UARTAPP_CTRL2_RTS_SEMAPHORE              27
-#define BM_UARTAPP_CTRL2_RTS_SEMAPHORE              0x8000000
-#define BF_UARTAPP_CTRL2_RTS_SEMAPHORE(v)           (((v) << 27) & 0x8000000)
-#define BP_UARTAPP_CTRL2_DMAONERR                   26
-#define BM_UARTAPP_CTRL2_DMAONERR                   0x4000000
-#define BF_UARTAPP_CTRL2_DMAONERR(v)                (((v) << 26) & 0x4000000)
-#define BP_UARTAPP_CTRL2_TXDMAE                     25
-#define BM_UARTAPP_CTRL2_TXDMAE                     0x2000000
-#define BF_UARTAPP_CTRL2_TXDMAE(v)                  (((v) << 25) & 0x2000000)
-#define BP_UARTAPP_CTRL2_RXDMAE                     24
-#define BM_UARTAPP_CTRL2_RXDMAE                     0x1000000
-#define BF_UARTAPP_CTRL2_RXDMAE(v)                  (((v) << 24) & 0x1000000)
-#define BP_UARTAPP_CTRL2_RSVD2                      23
-#define BM_UARTAPP_CTRL2_RSVD2                      0x800000
-#define BF_UARTAPP_CTRL2_RSVD2(v)                   (((v) << 23) & 0x800000)
-#define BP_UARTAPP_CTRL2_RXIFLSEL                   20
-#define BM_UARTAPP_CTRL2_RXIFLSEL                   0x700000
-#define BV_UARTAPP_CTRL2_RXIFLSEL__NOT_EMPTY        0x0
-#define BV_UARTAPP_CTRL2_RXIFLSEL__ONE_QUARTER      0x1
-#define BV_UARTAPP_CTRL2_RXIFLSEL__ONE_HALF         0x2
-#define BV_UARTAPP_CTRL2_RXIFLSEL__THREE_QUARTERS   0x3
-#define BV_UARTAPP_CTRL2_RXIFLSEL__SEVEN_EIGHTHS    0x4
-#define BV_UARTAPP_CTRL2_RXIFLSEL__INVALID5         0x5
-#define BV_UARTAPP_CTRL2_RXIFLSEL__INVALID6         0x6
-#define BV_UARTAPP_CTRL2_RXIFLSEL__INVALID7         0x7
-#define BF_UARTAPP_CTRL2_RXIFLSEL(v)                (((v) << 20) & 0x700000)
-#define BF_UARTAPP_CTRL2_RXIFLSEL_V(v)              ((BV_UARTAPP_CTRL2_RXIFLSEL__##v << 20) & 0x700000)
-#define BP_UARTAPP_CTRL2_RSVD3                      19
-#define BM_UARTAPP_CTRL2_RSVD3                      0x80000
-#define BF_UARTAPP_CTRL2_RSVD3(v)                   (((v) << 19) & 0x80000)
-#define BP_UARTAPP_CTRL2_TXIFLSEL                   16
-#define BM_UARTAPP_CTRL2_TXIFLSEL                   0x70000
-#define BV_UARTAPP_CTRL2_TXIFLSEL__EMPTY            0x0
-#define BV_UARTAPP_CTRL2_TXIFLSEL__ONE_QUARTER      0x1
-#define BV_UARTAPP_CTRL2_TXIFLSEL__ONE_HALF         0x2
-#define BV_UARTAPP_CTRL2_TXIFLSEL__THREE_QUARTERS   0x3
-#define BV_UARTAPP_CTRL2_TXIFLSEL__SEVEN_EIGHTHS    0x4
-#define BV_UARTAPP_CTRL2_TXIFLSEL__INVALID5         0x5
-#define BV_UARTAPP_CTRL2_TXIFLSEL__INVALID6         0x6
-#define BV_UARTAPP_CTRL2_TXIFLSEL__INVALID7         0x7
-#define BF_UARTAPP_CTRL2_TXIFLSEL(v)                (((v) << 16) & 0x70000)
-#define BF_UARTAPP_CTRL2_TXIFLSEL_V(v)              ((BV_UARTAPP_CTRL2_TXIFLSEL__##v << 16) & 0x70000)
-#define BP_UARTAPP_CTRL2_CTSEN                      15
-#define BM_UARTAPP_CTRL2_CTSEN                      0x8000
-#define BF_UARTAPP_CTRL2_CTSEN(v)                   (((v) << 15) & 0x8000)
-#define BP_UARTAPP_CTRL2_RTSEN                      14
-#define BM_UARTAPP_CTRL2_RTSEN                      0x4000
-#define BF_UARTAPP_CTRL2_RTSEN(v)                   (((v) << 14) & 0x4000)
-#define BP_UARTAPP_CTRL2_OUT2                       13
-#define BM_UARTAPP_CTRL2_OUT2                       0x2000
-#define BF_UARTAPP_CTRL2_OUT2(v)                    (((v) << 13) & 0x2000)
-#define BP_UARTAPP_CTRL2_OUT1                       12
-#define BM_UARTAPP_CTRL2_OUT1                       0x1000
-#define BF_UARTAPP_CTRL2_OUT1(v)                    (((v) << 12) & 0x1000)
-#define BP_UARTAPP_CTRL2_RTS                        11
-#define BM_UARTAPP_CTRL2_RTS                        0x800
-#define BF_UARTAPP_CTRL2_RTS(v)                     (((v) << 11) & 0x800)
-#define BP_UARTAPP_CTRL2_DTR                        10
-#define BM_UARTAPP_CTRL2_DTR                        0x400
-#define BF_UARTAPP_CTRL2_DTR(v)                     (((v) << 10) & 0x400)
-#define BP_UARTAPP_CTRL2_RXE                        9
-#define BM_UARTAPP_CTRL2_RXE                        0x200
-#define BF_UARTAPP_CTRL2_RXE(v)                     (((v) << 9) & 0x200)
-#define BP_UARTAPP_CTRL2_TXE                        8
-#define BM_UARTAPP_CTRL2_TXE                        0x100
-#define BF_UARTAPP_CTRL2_TXE(v)                     (((v) << 8) & 0x100)
-#define BP_UARTAPP_CTRL2_LBE                        7
-#define BM_UARTAPP_CTRL2_LBE                        0x80
-#define BF_UARTAPP_CTRL2_LBE(v)                     (((v) << 7) & 0x80)
-#define BP_UARTAPP_CTRL2_USE_LCR2                   6
-#define BM_UARTAPP_CTRL2_USE_LCR2                   0x40
-#define BF_UARTAPP_CTRL2_USE_LCR2(v)                (((v) << 6) & 0x40)
-#define BP_UARTAPP_CTRL2_RSVD4                      3
-#define BM_UARTAPP_CTRL2_RSVD4                      0x38
-#define BF_UARTAPP_CTRL2_RSVD4(v)                   (((v) << 3) & 0x38)
-#define BP_UARTAPP_CTRL2_SIRLP                      2
-#define BM_UARTAPP_CTRL2_SIRLP                      0x4
-#define BF_UARTAPP_CTRL2_SIRLP(v)                   (((v) << 2) & 0x4)
-#define BP_UARTAPP_CTRL2_SIREN                      1
-#define BM_UARTAPP_CTRL2_SIREN                      0x2
-#define BF_UARTAPP_CTRL2_SIREN(v)                   (((v) << 1) & 0x2)
-#define BP_UARTAPP_CTRL2_UARTEN                     0
-#define BM_UARTAPP_CTRL2_UARTEN                     0x1
-#define BF_UARTAPP_CTRL2_UARTEN(v)                  (((v) << 0) & 0x1)
-
-/**
- * Register: HW_UARTAPP_LINECTRL
- * Address: 0x30
- * SCT: yes
-*/
-#define HW_UARTAPP_LINECTRL(d)              (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x30 + 0x0))
-#define HW_UARTAPP_LINECTRL_SET(d)          (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x30 + 0x4))
-#define HW_UARTAPP_LINECTRL_CLR(d)          (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x30 + 0x8))
-#define HW_UARTAPP_LINECTRL_TOG(d)          (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x30 + 0xc))
-#define BP_UARTAPP_LINECTRL_BAUD_DIVINT     16
-#define BM_UARTAPP_LINECTRL_BAUD_DIVINT     0xffff0000
-#define BF_UARTAPP_LINECTRL_BAUD_DIVINT(v)  (((v) << 16) & 0xffff0000)
-#define BP_UARTAPP_LINECTRL_RSVD            14
-#define BM_UARTAPP_LINECTRL_RSVD            0xc000
-#define BF_UARTAPP_LINECTRL_RSVD(v)         (((v) << 14) & 0xc000)
-#define BP_UARTAPP_LINECTRL_BAUD_DIVFRAC    8
-#define BM_UARTAPP_LINECTRL_BAUD_DIVFRAC    0x3f00
-#define BF_UARTAPP_LINECTRL_BAUD_DIVFRAC(v) (((v) << 8) & 0x3f00)
-#define BP_UARTAPP_LINECTRL_SPS             7
-#define BM_UARTAPP_LINECTRL_SPS             0x80
-#define BF_UARTAPP_LINECTRL_SPS(v)          (((v) << 7) & 0x80)
-#define BP_UARTAPP_LINECTRL_WLEN            5
-#define BM_UARTAPP_LINECTRL_WLEN            0x60
-#define BF_UARTAPP_LINECTRL_WLEN(v)         (((v) << 5) & 0x60)
-#define BP_UARTAPP_LINECTRL_FEN             4
-#define BM_UARTAPP_LINECTRL_FEN             0x10
-#define BF_UARTAPP_LINECTRL_FEN(v)          (((v) << 4) & 0x10)
-#define BP_UARTAPP_LINECTRL_STP2            3
-#define BM_UARTAPP_LINECTRL_STP2            0x8
-#define BF_UARTAPP_LINECTRL_STP2(v)         (((v) << 3) & 0x8)
-#define BP_UARTAPP_LINECTRL_EPS             2
-#define BM_UARTAPP_LINECTRL_EPS             0x4
-#define BF_UARTAPP_LINECTRL_EPS(v)          (((v) << 2) & 0x4)
-#define BP_UARTAPP_LINECTRL_PEN             1
-#define BM_UARTAPP_LINECTRL_PEN             0x2
-#define BF_UARTAPP_LINECTRL_PEN(v)          (((v) << 1) & 0x2)
-#define BP_UARTAPP_LINECTRL_BRK             0
-#define BM_UARTAPP_LINECTRL_BRK             0x1
-#define BF_UARTAPP_LINECTRL_BRK(v)          (((v) << 0) & 0x1)
-
-/**
- * Register: HW_UARTAPP_LINECTRL2
- * Address: 0x40
- * SCT: yes
-*/
-#define HW_UARTAPP_LINECTRL2(d)                 (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x40 + 0x0))
-#define HW_UARTAPP_LINECTRL2_SET(d)             (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x40 + 0x4))
-#define HW_UARTAPP_LINECTRL2_CLR(d)             (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x40 + 0x8))
-#define HW_UARTAPP_LINECTRL2_TOG(d)             (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x40 + 0xc))
-#define BP_UARTAPP_LINECTRL2_BAUD_DIVINT        16
-#define BM_UARTAPP_LINECTRL2_BAUD_DIVINT        0xffff0000
-#define BF_UARTAPP_LINECTRL2_BAUD_DIVINT(v)     (((v) << 16) & 0xffff0000)
-#define BP_UARTAPP_LINECTRL2_RSVD               14
-#define BM_UARTAPP_LINECTRL2_RSVD               0xc000
-#define BF_UARTAPP_LINECTRL2_RSVD(v)            (((v) << 14) & 0xc000)
-#define BP_UARTAPP_LINECTRL2_BAUD_DIVFRAC       8
-#define BM_UARTAPP_LINECTRL2_BAUD_DIVFRAC       0x3f00
-#define BF_UARTAPP_LINECTRL2_BAUD_DIVFRAC(v)    (((v) << 8) & 0x3f00)
-#define BP_UARTAPP_LINECTRL2_SPS                7
-#define BM_UARTAPP_LINECTRL2_SPS                0x80
-#define BF_UARTAPP_LINECTRL2_SPS(v)             (((v) << 7) & 0x80)
-#define BP_UARTAPP_LINECTRL2_WLEN               5
-#define BM_UARTAPP_LINECTRL2_WLEN               0x60
-#define BF_UARTAPP_LINECTRL2_WLEN(v)            (((v) << 5) & 0x60)
-#define BP_UARTAPP_LINECTRL2_FEN                4
-#define BM_UARTAPP_LINECTRL2_FEN                0x10
-#define BF_UARTAPP_LINECTRL2_FEN(v)             (((v) << 4) & 0x10)
-#define BP_UARTAPP_LINECTRL2_STP2               3
-#define BM_UARTAPP_LINECTRL2_STP2               0x8
-#define BF_UARTAPP_LINECTRL2_STP2(v)            (((v) << 3) & 0x8)
-#define BP_UARTAPP_LINECTRL2_EPS                2
-#define BM_UARTAPP_LINECTRL2_EPS                0x4
-#define BF_UARTAPP_LINECTRL2_EPS(v)             (((v) << 2) & 0x4)
-#define BP_UARTAPP_LINECTRL2_PEN                1
-#define BM_UARTAPP_LINECTRL2_PEN                0x2
-#define BF_UARTAPP_LINECTRL2_PEN(v)             (((v) << 1) & 0x2)
-#define BP_UARTAPP_LINECTRL2_RSVD1              0
-#define BM_UARTAPP_LINECTRL2_RSVD1              0x1
-#define BF_UARTAPP_LINECTRL2_RSVD1(v)           (((v) << 0) & 0x1)
-
-/**
- * Register: HW_UARTAPP_INTR
- * Address: 0x50
- * SCT: yes
-*/
-#define HW_UARTAPP_INTR(d)          (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x50 + 0x0))
-#define HW_UARTAPP_INTR_SET(d)      (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x50 + 0x4))
-#define HW_UARTAPP_INTR_CLR(d)      (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x50 + 0x8))
-#define HW_UARTAPP_INTR_TOG(d)      (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x50 + 0xc))
-#define BP_UARTAPP_INTR_RSVD1       27
-#define BM_UARTAPP_INTR_RSVD1       0xf8000000
-#define BF_UARTAPP_INTR_RSVD1(v)    (((v) << 27) & 0xf8000000)
-#define BP_UARTAPP_INTR_OEIEN       26
-#define BM_UARTAPP_INTR_OEIEN       0x4000000
-#define BF_UARTAPP_INTR_OEIEN(v)    (((v) << 26) & 0x4000000)
-#define BP_UARTAPP_INTR_BEIEN       25
-#define BM_UARTAPP_INTR_BEIEN       0x2000000
-#define BF_UARTAPP_INTR_BEIEN(v)    (((v) << 25) & 0x2000000)
-#define BP_UARTAPP_INTR_PEIEN       24
-#define BM_UARTAPP_INTR_PEIEN       0x1000000
-#define BF_UARTAPP_INTR_PEIEN(v)    (((v) << 24) & 0x1000000)
-#define BP_UARTAPP_INTR_FEIEN       23
-#define BM_UARTAPP_INTR_FEIEN       0x800000
-#define BF_UARTAPP_INTR_FEIEN(v)    (((v) << 23) & 0x800000)
-#define BP_UARTAPP_INTR_RTIEN       22
-#define BM_UARTAPP_INTR_RTIEN       0x400000
-#define BF_UARTAPP_INTR_RTIEN(v)    (((v) << 22) & 0x400000)
-#define BP_UARTAPP_INTR_TXIEN       21
-#define BM_UARTAPP_INTR_TXIEN       0x200000
-#define BF_UARTAPP_INTR_TXIEN(v)    (((v) << 21) & 0x200000)
-#define BP_UARTAPP_INTR_RXIEN       20
-#define BM_UARTAPP_INTR_RXIEN       0x100000
-#define BF_UARTAPP_INTR_RXIEN(v)    (((v) << 20) & 0x100000)
-#define BP_UARTAPP_INTR_DSRMIEN     19
-#define BM_UARTAPP_INTR_DSRMIEN     0x80000
-#define BF_UARTAPP_INTR_DSRMIEN(v)  (((v) << 19) & 0x80000)
-#define BP_UARTAPP_INTR_DCDMIEN     18
-#define BM_UARTAPP_INTR_DCDMIEN     0x40000
-#define BF_UARTAPP_INTR_DCDMIEN(v)  (((v) << 18) & 0x40000)
-#define BP_UARTAPP_INTR_CTSMIEN     17
-#define BM_UARTAPP_INTR_CTSMIEN     0x20000
-#define BF_UARTAPP_INTR_CTSMIEN(v)  (((v) << 17) & 0x20000)
-#define BP_UARTAPP_INTR_RIMIEN      16
-#define BM_UARTAPP_INTR_RIMIEN      0x10000
-#define BF_UARTAPP_INTR_RIMIEN(v)   (((v) << 16) & 0x10000)
-#define BP_UARTAPP_INTR_RSVD2       11
-#define BM_UARTAPP_INTR_RSVD2       0xf800
-#define BF_UARTAPP_INTR_RSVD2(v)    (((v) << 11) & 0xf800)
-#define BP_UARTAPP_INTR_OEIS        10
-#define BM_UARTAPP_INTR_OEIS        0x400
-#define BF_UARTAPP_INTR_OEIS(v)     (((v) << 10) & 0x400)
-#define BP_UARTAPP_INTR_BEIS        9
-#define BM_UARTAPP_INTR_BEIS        0x200
-#define BF_UARTAPP_INTR_BEIS(v)     (((v) << 9) & 0x200)
-#define BP_UARTAPP_INTR_PEIS        8
-#define BM_UARTAPP_INTR_PEIS        0x100
-#define BF_UARTAPP_INTR_PEIS(v)     (((v) << 8) & 0x100)
-#define BP_UARTAPP_INTR_FEIS        7
-#define BM_UARTAPP_INTR_FEIS        0x80
-#define BF_UARTAPP_INTR_FEIS(v)     (((v) << 7) & 0x80)
-#define BP_UARTAPP_INTR_RTIS        6
-#define BM_UARTAPP_INTR_RTIS        0x40
-#define BF_UARTAPP_INTR_RTIS(v)     (((v) << 6) & 0x40)
-#define BP_UARTAPP_INTR_TXIS        5
-#define BM_UARTAPP_INTR_TXIS        0x20
-#define BF_UARTAPP_INTR_TXIS(v)     (((v) << 5) & 0x20)
-#define BP_UARTAPP_INTR_RXIS        4
-#define BM_UARTAPP_INTR_RXIS        0x10
-#define BF_UARTAPP_INTR_RXIS(v)     (((v) << 4) & 0x10)
-#define BP_UARTAPP_INTR_DSRMIS      3
-#define BM_UARTAPP_INTR_DSRMIS      0x8
-#define BF_UARTAPP_INTR_DSRMIS(v)   (((v) << 3) & 0x8)
-#define BP_UARTAPP_INTR_DCDMIS      2
-#define BM_UARTAPP_INTR_DCDMIS      0x4
-#define BF_UARTAPP_INTR_DCDMIS(v)   (((v) << 2) & 0x4)
-#define BP_UARTAPP_INTR_CTSMIS      1
-#define BM_UARTAPP_INTR_CTSMIS      0x2
-#define BF_UARTAPP_INTR_CTSMIS(v)   (((v) << 1) & 0x2)
-#define BP_UARTAPP_INTR_RIMIS       0
-#define BM_UARTAPP_INTR_RIMIS       0x1
-#define BF_UARTAPP_INTR_RIMIS(v)    (((v) << 0) & 0x1)
-
-/**
- * Register: HW_UARTAPP_DATA
- * Address: 0x60
- * SCT: no
-*/
-#define HW_UARTAPP_DATA(d)      (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x60))
-#define BP_UARTAPP_DATA_DATA    0
-#define BM_UARTAPP_DATA_DATA    0xffffffff
-#define BF_UARTAPP_DATA_DATA(v) (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_UARTAPP_STAT
- * Address: 0x70
- * SCT: no
-*/
-#define HW_UARTAPP_STAT(d)                      (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x70))
-#define BP_UARTAPP_STAT_PRESENT                 31
-#define BM_UARTAPP_STAT_PRESENT                 0x80000000
-#define BV_UARTAPP_STAT_PRESENT__UNAVAILABLE    0x0
-#define BV_UARTAPP_STAT_PRESENT__AVAILABLE      0x1
-#define BF_UARTAPP_STAT_PRESENT(v)              (((v) << 31) & 0x80000000)
-#define BF_UARTAPP_STAT_PRESENT_V(v)            ((BV_UARTAPP_STAT_PRESENT__##v << 31) & 0x80000000)
-#define BP_UARTAPP_STAT_HISPEED                 30
-#define BM_UARTAPP_STAT_HISPEED                 0x40000000
-#define BV_UARTAPP_STAT_HISPEED__UNAVAILABLE    0x0
-#define BV_UARTAPP_STAT_HISPEED__AVAILABLE      0x1
-#define BF_UARTAPP_STAT_HISPEED(v)              (((v) << 30) & 0x40000000)
-#define BF_UARTAPP_STAT_HISPEED_V(v)            ((BV_UARTAPP_STAT_HISPEED__##v << 30) & 0x40000000)
-#define BP_UARTAPP_STAT_BUSY                    29
-#define BM_UARTAPP_STAT_BUSY                    0x20000000
-#define BF_UARTAPP_STAT_BUSY(v)                 (((v) << 29) & 0x20000000)
-#define BP_UARTAPP_STAT_CTS                     28
-#define BM_UARTAPP_STAT_CTS                     0x10000000
-#define BF_UARTAPP_STAT_CTS(v)                  (((v) << 28) & 0x10000000)
-#define BP_UARTAPP_STAT_TXFE                    27
-#define BM_UARTAPP_STAT_TXFE                    0x8000000
-#define BF_UARTAPP_STAT_TXFE(v)                 (((v) << 27) & 0x8000000)
-#define BP_UARTAPP_STAT_RXFF                    26
-#define BM_UARTAPP_STAT_RXFF                    0x4000000
-#define BF_UARTAPP_STAT_RXFF(v)                 (((v) << 26) & 0x4000000)
-#define BP_UARTAPP_STAT_TXFF                    25
-#define BM_UARTAPP_STAT_TXFF                    0x2000000
-#define BF_UARTAPP_STAT_TXFF(v)                 (((v) << 25) & 0x2000000)
-#define BP_UARTAPP_STAT_RXFE                    24
-#define BM_UARTAPP_STAT_RXFE                    0x1000000
-#define BF_UARTAPP_STAT_RXFE(v)                 (((v) << 24) & 0x1000000)
-#define BP_UARTAPP_STAT_RXBYTE_INVALID          20
-#define BM_UARTAPP_STAT_RXBYTE_INVALID          0xf00000
-#define BF_UARTAPP_STAT_RXBYTE_INVALID(v)       (((v) << 20) & 0xf00000)
-#define BP_UARTAPP_STAT_OERR                    19
-#define BM_UARTAPP_STAT_OERR                    0x80000
-#define BF_UARTAPP_STAT_OERR(v)                 (((v) << 19) & 0x80000)
-#define BP_UARTAPP_STAT_BERR                    18
-#define BM_UARTAPP_STAT_BERR                    0x40000
-#define BF_UARTAPP_STAT_BERR(v)                 (((v) << 18) & 0x40000)
-#define BP_UARTAPP_STAT_PERR                    17
-#define BM_UARTAPP_STAT_PERR                    0x20000
-#define BF_UARTAPP_STAT_PERR(v)                 (((v) << 17) & 0x20000)
-#define BP_UARTAPP_STAT_FERR                    16
-#define BM_UARTAPP_STAT_FERR                    0x10000
-#define BF_UARTAPP_STAT_FERR(v)                 (((v) << 16) & 0x10000)
-#define BP_UARTAPP_STAT_RXCOUNT                 0
-#define BM_UARTAPP_STAT_RXCOUNT                 0xffff
-#define BF_UARTAPP_STAT_RXCOUNT(v)              (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_UARTAPP_DEBUG
- * Address: 0x80
- * SCT: no
-*/
-#define HW_UARTAPP_DEBUG(d)             (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x80))
-#define BP_UARTAPP_DEBUG_RXIBAUD_DIV    16
-#define BM_UARTAPP_DEBUG_RXIBAUD_DIV    0xffff0000
-#define BF_UARTAPP_DEBUG_RXIBAUD_DIV(v) (((v) << 16) & 0xffff0000)
-#define BP_UARTAPP_DEBUG_RXFBAUD_DIV    10
-#define BM_UARTAPP_DEBUG_RXFBAUD_DIV    0xfc00
-#define BF_UARTAPP_DEBUG_RXFBAUD_DIV(v) (((v) << 10) & 0xfc00)
-#define BP_UARTAPP_DEBUG_RSVD1          6
-#define BM_UARTAPP_DEBUG_RSVD1          0x3c0
-#define BF_UARTAPP_DEBUG_RSVD1(v)       (((v) << 6) & 0x3c0)
-#define BP_UARTAPP_DEBUG_TXDMARUN       5
-#define BM_UARTAPP_DEBUG_TXDMARUN       0x20
-#define BF_UARTAPP_DEBUG_TXDMARUN(v)    (((v) << 5) & 0x20)
-#define BP_UARTAPP_DEBUG_RXDMARUN       4
-#define BM_UARTAPP_DEBUG_RXDMARUN       0x10
-#define BF_UARTAPP_DEBUG_RXDMARUN(v)    (((v) << 4) & 0x10)
-#define BP_UARTAPP_DEBUG_TXCMDEND       3
-#define BM_UARTAPP_DEBUG_TXCMDEND       0x8
-#define BF_UARTAPP_DEBUG_TXCMDEND(v)    (((v) << 3) & 0x8)
-#define BP_UARTAPP_DEBUG_RXCMDEND       2
-#define BM_UARTAPP_DEBUG_RXCMDEND       0x4
-#define BF_UARTAPP_DEBUG_RXCMDEND(v)    (((v) << 2) & 0x4)
-#define BP_UARTAPP_DEBUG_TXDMARQ        1
-#define BM_UARTAPP_DEBUG_TXDMARQ        0x2
-#define BF_UARTAPP_DEBUG_TXDMARQ(v)     (((v) << 1) & 0x2)
-#define BP_UARTAPP_DEBUG_RXDMARQ        0
-#define BM_UARTAPP_DEBUG_RXDMARQ        0x1
-#define BF_UARTAPP_DEBUG_RXDMARQ(v)     (((v) << 0) & 0x1)
-
-/**
- * Register: HW_UARTAPP_VERSION
- * Address: 0x90
- * SCT: no
-*/
-#define HW_UARTAPP_VERSION(d)       (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x90))
-#define BP_UARTAPP_VERSION_MAJOR    24
-#define BM_UARTAPP_VERSION_MAJOR    0xff000000
-#define BF_UARTAPP_VERSION_MAJOR(v) (((v) << 24) & 0xff000000)
-#define BP_UARTAPP_VERSION_MINOR    16
-#define BM_UARTAPP_VERSION_MINOR    0xff0000
-#define BF_UARTAPP_VERSION_MINOR(v) (((v) << 16) & 0xff0000)
-#define BP_UARTAPP_VERSION_STEP     0
-#define BM_UARTAPP_VERSION_STEP     0xffff
-#define BF_UARTAPP_VERSION_STEP(v)  (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_UARTAPP_AUTOBAUD
- * Address: 0xa0
- * SCT: no
-*/
-#define HW_UARTAPP_AUTOBAUD(d)                      (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0xa0))
-#define BP_UARTAPP_AUTOBAUD_REFCHAR1                24
-#define BM_UARTAPP_AUTOBAUD_REFCHAR1                0xff000000
-#define BF_UARTAPP_AUTOBAUD_REFCHAR1(v)             (((v) << 24) & 0xff000000)
-#define BP_UARTAPP_AUTOBAUD_REFCHAR0                16
-#define BM_UARTAPP_AUTOBAUD_REFCHAR0                0xff0000
-#define BF_UARTAPP_AUTOBAUD_REFCHAR0(v)             (((v) << 16) & 0xff0000)
-#define BP_UARTAPP_AUTOBAUD_RSVD1                   5
-#define BM_UARTAPP_AUTOBAUD_RSVD1                   0xffe0
-#define BF_UARTAPP_AUTOBAUD_RSVD1(v)                (((v) << 5) & 0xffe0)
-#define BP_UARTAPP_AUTOBAUD_UPDATE_TX               4
-#define BM_UARTAPP_AUTOBAUD_UPDATE_TX               0x10
-#define BF_UARTAPP_AUTOBAUD_UPDATE_TX(v)            (((v) << 4) & 0x10)
-#define BP_UARTAPP_AUTOBAUD_TWO_REF_CHARS           3
-#define BM_UARTAPP_AUTOBAUD_TWO_REF_CHARS           0x8
-#define BF_UARTAPP_AUTOBAUD_TWO_REF_CHARS(v)        (((v) << 3) & 0x8)
-#define BP_UARTAPP_AUTOBAUD_START_WITH_RUNBIT       2
-#define BM_UARTAPP_AUTOBAUD_START_WITH_RUNBIT       0x4
-#define BF_UARTAPP_AUTOBAUD_START_WITH_RUNBIT(v)    (((v) << 2) & 0x4)
-#define BP_UARTAPP_AUTOBAUD_START_BAUD_DETECT       1
-#define BM_UARTAPP_AUTOBAUD_START_BAUD_DETECT       0x2
-#define BF_UARTAPP_AUTOBAUD_START_BAUD_DETECT(v)    (((v) << 1) & 0x2)
-#define BP_UARTAPP_AUTOBAUD_BAUD_DETECT_ENABLE      0
-#define BM_UARTAPP_AUTOBAUD_BAUD_DETECT_ENABLE      0x1
-#define BF_UARTAPP_AUTOBAUD_BAUD_DETECT_ENABLE(v)   (((v) << 0) & 0x1)
-
-#endif /* __HEADERGEN__IMX233__UARTAPP__H__ */
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-uartdbg.h b/firmware/target/arm/imx233/regs/imx233/regs-uartdbg.h
deleted file mode 100644
index ab9794d2cd..0000000000
--- a/firmware/target/arm/imx233/regs/imx233/regs-uartdbg.h
+++ /dev/null
@@ -1,491 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: imx233:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__IMX233__UARTDBG__H__
-#define __HEADERGEN__IMX233__UARTDBG__H__
-
-#define REGS_UARTDBG_BASE (0x80070000)
-
-#define REGS_UARTDBG_VERSION "3.2.0"
-
-/**
- * Register: HW_UARTDBG_DR
- * Address: 0
- * SCT: no
-*/
-#define HW_UARTDBG_DR                   (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x0))
-#define BP_UARTDBG_DR_UNAVAILABLE       16
-#define BM_UARTDBG_DR_UNAVAILABLE       0xffff0000
-#define BF_UARTDBG_DR_UNAVAILABLE(v)    (((v) << 16) & 0xffff0000)
-#define BP_UARTDBG_DR_RESERVED          12
-#define BM_UARTDBG_DR_RESERVED          0xf000
-#define BF_UARTDBG_DR_RESERVED(v)       (((v) << 12) & 0xf000)
-#define BP_UARTDBG_DR_OE                11
-#define BM_UARTDBG_DR_OE                0x800
-#define BF_UARTDBG_DR_OE(v)             (((v) << 11) & 0x800)
-#define BP_UARTDBG_DR_BE                10
-#define BM_UARTDBG_DR_BE                0x400
-#define BF_UARTDBG_DR_BE(v)             (((v) << 10) & 0x400)
-#define BP_UARTDBG_DR_PE                9
-#define BM_UARTDBG_DR_PE                0x200
-#define BF_UARTDBG_DR_PE(v)             (((v) << 9) & 0x200)
-#define BP_UARTDBG_DR_FE                8
-#define BM_UARTDBG_DR_FE                0x100
-#define BF_UARTDBG_DR_FE(v)             (((v) << 8) & 0x100)
-#define BP_UARTDBG_DR_DATA              0
-#define BM_UARTDBG_DR_DATA              0xff
-#define BF_UARTDBG_DR_DATA(v)           (((v) << 0) & 0xff)
-
-/**
- * Register: HW_UARTDBG_RSR_ECR
- * Address: 0x4
- * SCT: no
-*/
-#define HW_UARTDBG_RSR_ECR                  (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x4))
-#define BP_UARTDBG_RSR_ECR_UNAVAILABLE      8
-#define BM_UARTDBG_RSR_ECR_UNAVAILABLE      0xffffff00
-#define BF_UARTDBG_RSR_ECR_UNAVAILABLE(v)   (((v) << 8) & 0xffffff00)
-#define BP_UARTDBG_RSR_ECR_EC               4
-#define BM_UARTDBG_RSR_ECR_EC               0xf0
-#define BF_UARTDBG_RSR_ECR_EC(v)            (((v) << 4) & 0xf0)
-#define BP_UARTDBG_RSR_ECR_OE               3
-#define BM_UARTDBG_RSR_ECR_OE               0x8
-#define BF_UARTDBG_RSR_ECR_OE(v)            (((v) << 3) & 0x8)
-#define BP_UARTDBG_RSR_ECR_BE               2
-#define BM_UARTDBG_RSR_ECR_BE               0x4
-#define BF_UARTDBG_RSR_ECR_BE(v)            (((v) << 2) & 0x4)
-#define BP_UARTDBG_RSR_ECR_PE               1
-#define BM_UARTDBG_RSR_ECR_PE               0x2
-#define BF_UARTDBG_RSR_ECR_PE(v)            (((v) << 1) & 0x2)
-#define BP_UARTDBG_RSR_ECR_FE               0
-#define BM_UARTDBG_RSR_ECR_FE               0x1
-#define BF_UARTDBG_RSR_ECR_FE(v)            (((v) << 0) & 0x1)
-
-/**
- * Register: HW_UARTDBG_FR
- * Address: 0x18
- * SCT: no
-*/
-#define HW_UARTDBG_FR                   (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x18))
-#define BP_UARTDBG_FR_UNAVAILABLE       16
-#define BM_UARTDBG_FR_UNAVAILABLE       0xffff0000
-#define BF_UARTDBG_FR_UNAVAILABLE(v)    (((v) << 16) & 0xffff0000)
-#define BP_UARTDBG_FR_RESERVED          9
-#define BM_UARTDBG_FR_RESERVED          0xfe00
-#define BF_UARTDBG_FR_RESERVED(v)       (((v) << 9) & 0xfe00)
-#define BP_UARTDBG_FR_RI                8
-#define BM_UARTDBG_FR_RI                0x100
-#define BF_UARTDBG_FR_RI(v)             (((v) << 8) & 0x100)
-#define BP_UARTDBG_FR_TXFE              7
-#define BM_UARTDBG_FR_TXFE              0x80
-#define BF_UARTDBG_FR_TXFE(v)           (((v) << 7) & 0x80)
-#define BP_UARTDBG_FR_RXFF              6
-#define BM_UARTDBG_FR_RXFF              0x40
-#define BF_UARTDBG_FR_RXFF(v)           (((v) << 6) & 0x40)
-#define BP_UARTDBG_FR_TXFF              5
-#define BM_UARTDBG_FR_TXFF              0x20
-#define BF_UARTDBG_FR_TXFF(v)           (((v) << 5) & 0x20)
-#define BP_UARTDBG_FR_RXFE              4
-#define BM_UARTDBG_FR_RXFE              0x10
-#define BF_UARTDBG_FR_RXFE(v)           (((v) << 4) & 0x10)
-#define BP_UARTDBG_FR_BUSY              3
-#define BM_UARTDBG_FR_BUSY              0x8
-#define BF_UARTDBG_FR_BUSY(v)           (((v) << 3) & 0x8)
-#define BP_UARTDBG_FR_DCD               2
-#define BM_UARTDBG_FR_DCD               0x4
-#define BF_UARTDBG_FR_DCD(v)            (((v) << 2) & 0x4)
-#define BP_UARTDBG_FR_DSR               1
-#define BM_UARTDBG_FR_DSR               0x2
-#define BF_UARTDBG_FR_DSR(v)            (((v) << 1) & 0x2)
-#define BP_UARTDBG_FR_CTS               0
-#define BM_UARTDBG_FR_CTS               0x1
-#define BF_UARTDBG_FR_CTS(v)            (((v) << 0) & 0x1)
-
-/**
- * Register: HW_UARTDBG_ILPR
- * Address: 0x20
- * SCT: no
-*/
-#define HW_UARTDBG_ILPR                 (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x20))
-#define BP_UARTDBG_ILPR_UNAVAILABLE     8
-#define BM_UARTDBG_ILPR_UNAVAILABLE     0xffffff00
-#define BF_UARTDBG_ILPR_UNAVAILABLE(v)  (((v) << 8) & 0xffffff00)
-#define BP_UARTDBG_ILPR_ILPDVSR         0
-#define BM_UARTDBG_ILPR_ILPDVSR         0xff
-#define BF_UARTDBG_ILPR_ILPDVSR(v)      (((v) << 0) & 0xff)
-
-/**
- * Register: HW_UARTDBG_IBRD
- * Address: 0x24
- * SCT: no
-*/
-#define HW_UARTDBG_IBRD                 (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x24))
-#define BP_UARTDBG_IBRD_UNAVAILABLE     16
-#define BM_UARTDBG_IBRD_UNAVAILABLE     0xffff0000
-#define BF_UARTDBG_IBRD_UNAVAILABLE(v)  (((v) << 16) & 0xffff0000)
-#define BP_UARTDBG_IBRD_BAUD_DIVINT     0
-#define BM_UARTDBG_IBRD_BAUD_DIVINT     0xffff
-#define BF_UARTDBG_IBRD_BAUD_DIVINT(v)  (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_UARTDBG_FBRD
- * Address: 0x28
- * SCT: no
-*/
-#define HW_UARTDBG_FBRD                 (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x28))
-#define BP_UARTDBG_FBRD_UNAVAILABLE     8
-#define BM_UARTDBG_FBRD_UNAVAILABLE     0xffffff00
-#define BF_UARTDBG_FBRD_UNAVAILABLE(v)  (((v) << 8) & 0xffffff00)
-#define BP_UARTDBG_FBRD_RESERVED        6
-#define BM_UARTDBG_FBRD_RESERVED        0xc0
-#define BF_UARTDBG_FBRD_RESERVED(v)     (((v) << 6) & 0xc0)
-#define BP_UARTDBG_FBRD_BAUD_DIVFRAC    0
-#define BM_UARTDBG_FBRD_BAUD_DIVFRAC    0x3f
-#define BF_UARTDBG_FBRD_BAUD_DIVFRAC(v) (((v) << 0) & 0x3f)
-
-/**
- * Register: HW_UARTDBG_LCR_H
- * Address: 0x2c
- * SCT: no
-*/
-#define HW_UARTDBG_LCR_H                (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x2c))
-#define BP_UARTDBG_LCR_H_UNAVAILABLE    16
-#define BM_UARTDBG_LCR_H_UNAVAILABLE    0xffff0000
-#define BF_UARTDBG_LCR_H_UNAVAILABLE(v) (((v) << 16) & 0xffff0000)
-#define BP_UARTDBG_LCR_H_RESERVED       8
-#define BM_UARTDBG_LCR_H_RESERVED       0xff00
-#define BF_UARTDBG_LCR_H_RESERVED(v)    (((v) << 8) & 0xff00)
-#define BP_UARTDBG_LCR_H_SPS            7
-#define BM_UARTDBG_LCR_H_SPS            0x80
-#define BF_UARTDBG_LCR_H_SPS(v)         (((v) << 7) & 0x80)
-#define BP_UARTDBG_LCR_H_WLEN           5
-#define BM_UARTDBG_LCR_H_WLEN           0x60
-#define BF_UARTDBG_LCR_H_WLEN(v)        (((v) << 5) & 0x60)
-#define BP_UARTDBG_LCR_H_FEN            4
-#define BM_UARTDBG_LCR_H_FEN            0x10
-#define BF_UARTDBG_LCR_H_FEN(v)         (((v) << 4) & 0x10)
-#define BP_UARTDBG_LCR_H_STP2           3
-#define BM_UARTDBG_LCR_H_STP2           0x8
-#define BF_UARTDBG_LCR_H_STP2(v)        (((v) << 3) & 0x8)
-#define BP_UARTDBG_LCR_H_EPS            2
-#define BM_UARTDBG_LCR_H_EPS            0x4
-#define BF_UARTDBG_LCR_H_EPS(v)         (((v) << 2) & 0x4)
-#define BP_UARTDBG_LCR_H_PEN            1
-#define BM_UARTDBG_LCR_H_PEN            0x2
-#define BF_UARTDBG_LCR_H_PEN(v)         (((v) << 1) & 0x2)
-#define BP_UARTDBG_LCR_H_BRK            0
-#define BM_UARTDBG_LCR_H_BRK            0x1
-#define BF_UARTDBG_LCR_H_BRK(v)         (((v) << 0) & 0x1)
-
-/**
- * Register: HW_UARTDBG_CR
- * Address: 0x30
- * SCT: no
-*/
-#define HW_UARTDBG_CR                   (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x30))
-#define BP_UARTDBG_CR_UNAVAILABLE       16
-#define BM_UARTDBG_CR_UNAVAILABLE       0xffff0000
-#define BF_UARTDBG_CR_UNAVAILABLE(v)    (((v) << 16) & 0xffff0000)
-#define BP_UARTDBG_CR_CTSEN             15
-#define BM_UARTDBG_CR_CTSEN             0x8000
-#define BF_UARTDBG_CR_CTSEN(v)          (((v) << 15) & 0x8000)
-#define BP_UARTDBG_CR_RTSEN             14
-#define BM_UARTDBG_CR_RTSEN             0x4000
-#define BF_UARTDBG_CR_RTSEN(v)          (((v) << 14) & 0x4000)
-#define BP_UARTDBG_CR_OUT2              13
-#define BM_UARTDBG_CR_OUT2              0x2000
-#define BF_UARTDBG_CR_OUT2(v)           (((v) << 13) & 0x2000)
-#define BP_UARTDBG_CR_OUT1              12
-#define BM_UARTDBG_CR_OUT1              0x1000
-#define BF_UARTDBG_CR_OUT1(v)           (((v) << 12) & 0x1000)
-#define BP_UARTDBG_CR_RTS               11
-#define BM_UARTDBG_CR_RTS               0x800
-#define BF_UARTDBG_CR_RTS(v)            (((v) << 11) & 0x800)
-#define BP_UARTDBG_CR_DTR               10
-#define BM_UARTDBG_CR_DTR               0x400
-#define BF_UARTDBG_CR_DTR(v)            (((v) << 10) & 0x400)
-#define BP_UARTDBG_CR_RXE               9
-#define BM_UARTDBG_CR_RXE               0x200
-#define BF_UARTDBG_CR_RXE(v)            (((v) << 9) & 0x200)
-#define BP_UARTDBG_CR_TXE               8
-#define BM_UARTDBG_CR_TXE               0x100
-#define BF_UARTDBG_CR_TXE(v)            (((v) << 8) & 0x100)
-#define BP_UARTDBG_CR_LBE               7
-#define BM_UARTDBG_CR_LBE               0x80
-#define BF_UARTDBG_CR_LBE(v)            (((v) << 7) & 0x80)
-#define BP_UARTDBG_CR_RESERVED          3
-#define BM_UARTDBG_CR_RESERVED          0x78
-#define BF_UARTDBG_CR_RESERVED(v)       (((v) << 3) & 0x78)
-#define BP_UARTDBG_CR_SIRLP             2
-#define BM_UARTDBG_CR_SIRLP             0x4
-#define BF_UARTDBG_CR_SIRLP(v)          (((v) << 2) & 0x4)
-#define BP_UARTDBG_CR_SIREN             1
-#define BM_UARTDBG_CR_SIREN             0x2
-#define BF_UARTDBG_CR_SIREN(v)          (((v) << 1) & 0x2)
-#define BP_UARTDBG_CR_UARTEN            0
-#define BM_UARTDBG_CR_UARTEN            0x1
-#define BF_UARTDBG_CR_UARTEN(v)         (((v) << 0) & 0x1)
-
-/**
- * Register: HW_UARTDBG_IFLS
- * Address: 0x34
- * SCT: no
-*/
-#define HW_UARTDBG_IFLS                             (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x34))
-#define BP_UARTDBG_IFLS_UNAVAILABLE                 16
-#define BM_UARTDBG_IFLS_UNAVAILABLE                 0xffff0000
-#define BF_UARTDBG_IFLS_UNAVAILABLE(v)              (((v) << 16) & 0xffff0000)
-#define BP_UARTDBG_IFLS_RESERVED                    6
-#define BM_UARTDBG_IFLS_RESERVED                    0xffc0
-#define BF_UARTDBG_IFLS_RESERVED(v)                 (((v) << 6) & 0xffc0)
-#define BP_UARTDBG_IFLS_RXIFLSEL                    3
-#define BM_UARTDBG_IFLS_RXIFLSEL                    0x38
-#define BV_UARTDBG_IFLS_RXIFLSEL__NOT_EMPTY         0x0
-#define BV_UARTDBG_IFLS_RXIFLSEL__ONE_QUARTER       0x1
-#define BV_UARTDBG_IFLS_RXIFLSEL__ONE_HALF          0x2
-#define BV_UARTDBG_IFLS_RXIFLSEL__THREE_QUARTERS    0x3
-#define BV_UARTDBG_IFLS_RXIFLSEL__SEVEN_EIGHTHS     0x4
-#define BV_UARTDBG_IFLS_RXIFLSEL__INVALID5          0x5
-#define BV_UARTDBG_IFLS_RXIFLSEL__INVALID6          0x6
-#define BV_UARTDBG_IFLS_RXIFLSEL__INVALID7          0x7
-#define BF_UARTDBG_IFLS_RXIFLSEL(v)                 (((v) << 3) & 0x38)
-#define BF_UARTDBG_IFLS_RXIFLSEL_V(v)               ((BV_UARTDBG_IFLS_RXIFLSEL__##v << 3) & 0x38)
-#define BP_UARTDBG_IFLS_TXIFLSEL                    0
-#define BM_UARTDBG_IFLS_TXIFLSEL                    0x7
-#define BV_UARTDBG_IFLS_TXIFLSEL__EMPTY             0x0
-#define BV_UARTDBG_IFLS_TXIFLSEL__ONE_QUARTER       0x1
-#define BV_UARTDBG_IFLS_TXIFLSEL__ONE_HALF          0x2
-#define BV_UARTDBG_IFLS_TXIFLSEL__THREE_QUARTERS    0x3
-#define BV_UARTDBG_IFLS_TXIFLSEL__SEVEN_EIGHTHS     0x4
-#define BV_UARTDBG_IFLS_TXIFLSEL__INVALID5          0x5
-#define BV_UARTDBG_IFLS_TXIFLSEL__INVALID6          0x6
-#define BV_UARTDBG_IFLS_TXIFLSEL__INVALID7          0x7
-#define BF_UARTDBG_IFLS_TXIFLSEL(v)                 (((v) << 0) & 0x7)
-#define BF_UARTDBG_IFLS_TXIFLSEL_V(v)               ((BV_UARTDBG_IFLS_TXIFLSEL__##v << 0) & 0x7)
-
-/**
- * Register: HW_UARTDBG_IMSC
- * Address: 0x38
- * SCT: no
-*/
-#define HW_UARTDBG_IMSC                 (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x38))
-#define BP_UARTDBG_IMSC_UNAVAILABLE     16
-#define BM_UARTDBG_IMSC_UNAVAILABLE     0xffff0000
-#define BF_UARTDBG_IMSC_UNAVAILABLE(v)  (((v) << 16) & 0xffff0000)
-#define BP_UARTDBG_IMSC_RESERVED        11
-#define BM_UARTDBG_IMSC_RESERVED        0xf800
-#define BF_UARTDBG_IMSC_RESERVED(v)     (((v) << 11) & 0xf800)
-#define BP_UARTDBG_IMSC_OEIM            10
-#define BM_UARTDBG_IMSC_OEIM            0x400
-#define BF_UARTDBG_IMSC_OEIM(v)         (((v) << 10) & 0x400)
-#define BP_UARTDBG_IMSC_BEIM            9
-#define BM_UARTDBG_IMSC_BEIM            0x200
-#define BF_UARTDBG_IMSC_BEIM(v)         (((v) << 9) & 0x200)
-#define BP_UARTDBG_IMSC_PEIM            8
-#define BM_UARTDBG_IMSC_PEIM            0x100
-#define BF_UARTDBG_IMSC_PEIM(v)         (((v) << 8) & 0x100)
-#define BP_UARTDBG_IMSC_FEIM            7
-#define BM_UARTDBG_IMSC_FEIM            0x80
-#define BF_UARTDBG_IMSC_FEIM(v)         (((v) << 7) & 0x80)
-#define BP_UARTDBG_IMSC_RTIM            6
-#define BM_UARTDBG_IMSC_RTIM            0x40
-#define BF_UARTDBG_IMSC_RTIM(v)         (((v) << 6) & 0x40)
-#define BP_UARTDBG_IMSC_TXIM            5
-#define BM_UARTDBG_IMSC_TXIM            0x20
-#define BF_UARTDBG_IMSC_TXIM(v)         (((v) << 5) & 0x20)
-#define BP_UARTDBG_IMSC_RXIM            4
-#define BM_UARTDBG_IMSC_RXIM            0x10
-#define BF_UARTDBG_IMSC_RXIM(v)         (((v) << 4) & 0x10)
-#define BP_UARTDBG_IMSC_DSRMIM          3
-#define BM_UARTDBG_IMSC_DSRMIM          0x8
-#define BF_UARTDBG_IMSC_DSRMIM(v)       (((v) << 3) & 0x8)
-#define BP_UARTDBG_IMSC_DCDMIM          2
-#define BM_UARTDBG_IMSC_DCDMIM          0x4
-#define BF_UARTDBG_IMSC_DCDMIM(v)       (((v) << 2) & 0x4)
-#define BP_UARTDBG_IMSC_CTSMIM          1
-#define BM_UARTDBG_IMSC_CTSMIM          0x2
-#define BF_UARTDBG_IMSC_CTSMIM(v)       (((v) << 1) & 0x2)
-#define BP_UARTDBG_IMSC_RIMIM           0
-#define BM_UARTDBG_IMSC_RIMIM           0x1
-#define BF_UARTDBG_IMSC_RIMIM(v)        (((v) << 0) & 0x1)
-
-/**
- * Register: HW_UARTDBG_RIS
- * Address: 0x3c
- * SCT: no
-*/
-#define HW_UARTDBG_RIS                  (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x3c))
-#define BP_UARTDBG_RIS_UNAVAILABLE      16
-#define BM_UARTDBG_RIS_UNAVAILABLE      0xffff0000
-#define BF_UARTDBG_RIS_UNAVAILABLE(v)   (((v) << 16) & 0xffff0000)
-#define BP_UARTDBG_RIS_RESERVED         11
-#define BM_UARTDBG_RIS_RESERVED         0xf800
-#define BF_UARTDBG_RIS_RESERVED(v)      (((v) << 11) & 0xf800)
-#define BP_UARTDBG_RIS_OERIS            10
-#define BM_UARTDBG_RIS_OERIS            0x400
-#define BF_UARTDBG_RIS_OERIS(v)         (((v) << 10) & 0x400)
-#define BP_UARTDBG_RIS_BERIS            9
-#define BM_UARTDBG_RIS_BERIS            0x200
-#define BF_UARTDBG_RIS_BERIS(v)         (((v) << 9) & 0x200)
-#define BP_UARTDBG_RIS_PERIS            8
-#define BM_UARTDBG_RIS_PERIS            0x100
-#define BF_UARTDBG_RIS_PERIS(v)         (((v) << 8) & 0x100)
-#define BP_UARTDBG_RIS_FERIS            7
-#define BM_UARTDBG_RIS_FERIS            0x80
-#define BF_UARTDBG_RIS_FERIS(v)         (((v) << 7) & 0x80)
-#define BP_UARTDBG_RIS_RTRIS            6
-#define BM_UARTDBG_RIS_RTRIS            0x40
-#define BF_UARTDBG_RIS_RTRIS(v)         (((v) << 6) & 0x40)
-#define BP_UARTDBG_RIS_TXRIS            5
-#define BM_UARTDBG_RIS_TXRIS            0x20
-#define BF_UARTDBG_RIS_TXRIS(v)         (((v) << 5) & 0x20)
-#define BP_UARTDBG_RIS_RXRIS            4
-#define BM_UARTDBG_RIS_RXRIS            0x10
-#define BF_UARTDBG_RIS_RXRIS(v)         (((v) << 4) & 0x10)
-#define BP_UARTDBG_RIS_DSRRMIS          3
-#define BM_UARTDBG_RIS_DSRRMIS          0x8
-#define BF_UARTDBG_RIS_DSRRMIS(v)       (((v) << 3) & 0x8)
-#define BP_UARTDBG_RIS_DCDRMIS          2
-#define BM_UARTDBG_RIS_DCDRMIS          0x4
-#define BF_UARTDBG_RIS_DCDRMIS(v)       (((v) << 2) & 0x4)
-#define BP_UARTDBG_RIS_CTSRMIS          1
-#define BM_UARTDBG_RIS_CTSRMIS          0x2
-#define BF_UARTDBG_RIS_CTSRMIS(v)       (((v) << 1) & 0x2)
-#define BP_UARTDBG_RIS_RIRMIS           0
-#define BM_UARTDBG_RIS_RIRMIS           0x1
-#define BF_UARTDBG_RIS_RIRMIS(v)        (((v) << 0) & 0x1)
-
-/**
- * Register: HW_UARTDBG_MIS
- * Address: 0x40
- * SCT: no
-*/
-#define HW_UARTDBG_MIS                  (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x40))
-#define BP_UARTDBG_MIS_UNAVAILABLE      16
-#define BM_UARTDBG_MIS_UNAVAILABLE      0xffff0000
-#define BF_UARTDBG_MIS_UNAVAILABLE(v)   (((v) << 16) & 0xffff0000)
-#define BP_UARTDBG_MIS_RESERVED         11
-#define BM_UARTDBG_MIS_RESERVED         0xf800
-#define BF_UARTDBG_MIS_RESERVED(v)      (((v) << 11) & 0xf800)
-#define BP_UARTDBG_MIS_OEMIS            10
-#define BM_UARTDBG_MIS_OEMIS            0x400
-#define BF_UARTDBG_MIS_OEMIS(v)         (((v) << 10) & 0x400)
-#define BP_UARTDBG_MIS_BEMIS            9
-#define BM_UARTDBG_MIS_BEMIS            0x200
-#define BF_UARTDBG_MIS_BEMIS(v)         (((v) << 9) & 0x200)
-#define BP_UARTDBG_MIS_PEMIS            8
-#define BM_UARTDBG_MIS_PEMIS            0x100
-#define BF_UARTDBG_MIS_PEMIS(v)         (((v) << 8) & 0x100)
-#define BP_UARTDBG_MIS_FEMIS            7
-#define BM_UARTDBG_MIS_FEMIS            0x80
-#define BF_UARTDBG_MIS_FEMIS(v)         (((v) << 7) & 0x80)
-#define BP_UARTDBG_MIS_RTMIS            6
-#define BM_UARTDBG_MIS_RTMIS            0x40
-#define BF_UARTDBG_MIS_RTMIS(v)         (((v) << 6) & 0x40)
-#define BP_UARTDBG_MIS_TXMIS            5
-#define BM_UARTDBG_MIS_TXMIS            0x20
-#define BF_UARTDBG_MIS_TXMIS(v)         (((v) << 5) & 0x20)
-#define BP_UARTDBG_MIS_RXMIS            4
-#define BM_UARTDBG_MIS_RXMIS            0x10
-#define BF_UARTDBG_MIS_RXMIS(v)         (((v) << 4) & 0x10)
-#define BP_UARTDBG_MIS_DSRMMIS          3
-#define BM_UARTDBG_MIS_DSRMMIS          0x8
-#define BF_UARTDBG_MIS_DSRMMIS(v)       (((v) << 3) & 0x8)
-#define BP_UARTDBG_MIS_DCDMMIS          2
-#define BM_UARTDBG_MIS_DCDMMIS          0x4
-#define BF_UARTDBG_MIS_DCDMMIS(v)       (((v) << 2) & 0x4)
-#define BP_UARTDBG_MIS_CTSMMIS          1
-#define BM_UARTDBG_MIS_CTSMMIS          0x2
-#define BF_UARTDBG_MIS_CTSMMIS(v)       (((v) << 1) & 0x2)
-#define BP_UARTDBG_MIS_RIMMIS           0
-#define BM_UARTDBG_MIS_RIMMIS           0x1
-#define BF_UARTDBG_MIS_RIMMIS(v)        (((v) << 0) & 0x1)
-
-/**
- * Register: HW_UARTDBG_ICR
- * Address: 0x44
- * SCT: no
-*/
-#define HW_UARTDBG_ICR                  (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x44))
-#define BP_UARTDBG_ICR_UNAVAILABLE      16
-#define BM_UARTDBG_ICR_UNAVAILABLE      0xffff0000
-#define BF_UARTDBG_ICR_UNAVAILABLE(v)   (((v) << 16) & 0xffff0000)
-#define BP_UARTDBG_ICR_RESERVED         11
-#define BM_UARTDBG_ICR_RESERVED         0xf800
-#define BF_UARTDBG_ICR_RESERVED(v)      (((v) << 11) & 0xf800)
-#define BP_UARTDBG_ICR_OEIC             10
-#define BM_UARTDBG_ICR_OEIC             0x400
-#define BF_UARTDBG_ICR_OEIC(v)          (((v) << 10) & 0x400)
-#define BP_UARTDBG_ICR_BEIC             9
-#define BM_UARTDBG_ICR_BEIC             0x200
-#define BF_UARTDBG_ICR_BEIC(v)          (((v) << 9) & 0x200)
-#define BP_UARTDBG_ICR_PEIC             8
-#define BM_UARTDBG_ICR_PEIC             0x100
-#define BF_UARTDBG_ICR_PEIC(v)          (((v) << 8) & 0x100)
-#define BP_UARTDBG_ICR_FEIC             7
-#define BM_UARTDBG_ICR_FEIC             0x80
-#define BF_UARTDBG_ICR_FEIC(v)          (((v) << 7) & 0x80)
-#define BP_UARTDBG_ICR_RTIC             6
-#define BM_UARTDBG_ICR_RTIC             0x40
-#define BF_UARTDBG_ICR_RTIC(v)          (((v) << 6) & 0x40)
-#define BP_UARTDBG_ICR_TXIC             5
-#define BM_UARTDBG_ICR_TXIC             0x20
-#define BF_UARTDBG_ICR_TXIC(v)          (((v) << 5) & 0x20)
-#define BP_UARTDBG_ICR_RXIC             4
-#define BM_UARTDBG_ICR_RXIC             0x10
-#define BF_UARTDBG_ICR_RXIC(v)          (((v) << 4) & 0x10)
-#define BP_UARTDBG_ICR_DSRMIC           3
-#define BM_UARTDBG_ICR_DSRMIC           0x8
-#define BF_UARTDBG_ICR_DSRMIC(v)        (((v) << 3) & 0x8)
-#define BP_UARTDBG_ICR_DCDMIC           2
-#define BM_UARTDBG_ICR_DCDMIC           0x4
-#define BF_UARTDBG_ICR_DCDMIC(v)        (((v) << 2) & 0x4)
-#define BP_UARTDBG_ICR_CTSMIC           1
-#define BM_UARTDBG_ICR_CTSMIC           0x2
-#define BF_UARTDBG_ICR_CTSMIC(v)        (((v) << 1) & 0x2)
-#define BP_UARTDBG_ICR_RIMIC            0
-#define BM_UARTDBG_ICR_RIMIC            0x1
-#define BF_UARTDBG_ICR_RIMIC(v)         (((v) << 0) & 0x1)
-
-/**
- * Register: HW_UARTDBG_DMACR
- * Address: 0x48
- * SCT: no
-*/
-#define HW_UARTDBG_DMACR                (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x48))
-#define BP_UARTDBG_DMACR_UNAVAILABLE    16
-#define BM_UARTDBG_DMACR_UNAVAILABLE    0xffff0000
-#define BF_UARTDBG_DMACR_UNAVAILABLE(v) (((v) << 16) & 0xffff0000)
-#define BP_UARTDBG_DMACR_RESERVED       3
-#define BM_UARTDBG_DMACR_RESERVED       0xfff8
-#define BF_UARTDBG_DMACR_RESERVED(v)    (((v) << 3) & 0xfff8)
-#define BP_UARTDBG_DMACR_DMAONERR       2
-#define BM_UARTDBG_DMACR_DMAONERR       0x4
-#define BF_UARTDBG_DMACR_DMAONERR(v)    (((v) << 2) & 0x4)
-#define BP_UARTDBG_DMACR_TXDMAE         1
-#define BM_UARTDBG_DMACR_TXDMAE         0x2
-#define BF_UARTDBG_DMACR_TXDMAE(v)      (((v) << 1) & 0x2)
-#define BP_UARTDBG_DMACR_RXDMAE         0
-#define BM_UARTDBG_DMACR_RXDMAE         0x1
-#define BF_UARTDBG_DMACR_RXDMAE(v)      (((v) << 0) & 0x1)
-
-#endif /* __HEADERGEN__IMX233__UARTDBG__H__ */
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-usbctrl.h b/firmware/target/arm/imx233/regs/imx233/regs-usbctrl.h
deleted file mode 100644
index 371903c539..0000000000
--- a/firmware/target/arm/imx233/regs/imx233/regs-usbctrl.h
+++ /dev/null
@@ -1,1234 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: imx233:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__IMX233__USBCTRL__H__
-#define __HEADERGEN__IMX233__USBCTRL__H__
-
-#define REGS_USBCTRL_BASE (0x80080000)
-
-#define REGS_USBCTRL_VERSION "3.2.0"
-
-/**
- * Register: HW_USBCTRL_ID
- * Address: 0
- * SCT: no
-*/
-#define HW_USBCTRL_ID               (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x0))
-#define BP_USBCTRL_ID_CIVERSION     29
-#define BM_USBCTRL_ID_CIVERSION     0xe0000000
-#define BF_USBCTRL_ID_CIVERSION(v)  (((v) << 29) & 0xe0000000)
-#define BP_USBCTRL_ID_VERSION       25
-#define BM_USBCTRL_ID_VERSION       0x1e000000
-#define BF_USBCTRL_ID_VERSION(v)    (((v) << 25) & 0x1e000000)
-#define BP_USBCTRL_ID_REVISION      21
-#define BM_USBCTRL_ID_REVISION      0x1e00000
-#define BF_USBCTRL_ID_REVISION(v)   (((v) << 21) & 0x1e00000)
-#define BP_USBCTRL_ID_TAG           16
-#define BM_USBCTRL_ID_TAG           0x1f0000
-#define BF_USBCTRL_ID_TAG(v)        (((v) << 16) & 0x1f0000)
-#define BP_USBCTRL_ID_RSVD1         14
-#define BM_USBCTRL_ID_RSVD1         0xc000
-#define BF_USBCTRL_ID_RSVD1(v)      (((v) << 14) & 0xc000)
-#define BP_USBCTRL_ID_NID           8
-#define BM_USBCTRL_ID_NID           0x3f00
-#define BF_USBCTRL_ID_NID(v)        (((v) << 8) & 0x3f00)
-#define BP_USBCTRL_ID_RSVD0         6
-#define BM_USBCTRL_ID_RSVD0         0xc0
-#define BF_USBCTRL_ID_RSVD0(v)      (((v) << 6) & 0xc0)
-#define BP_USBCTRL_ID_ID            0
-#define BM_USBCTRL_ID_ID            0x3f
-#define BF_USBCTRL_ID_ID(v)         (((v) << 0) & 0x3f)
-
-/**
- * Register: HW_USBCTRL_HWGENERAL
- * Address: 0x4
- * SCT: no
-*/
-#define HW_USBCTRL_HWGENERAL            (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x4))
-#define BP_USBCTRL_HWGENERAL_RSVD       11
-#define BM_USBCTRL_HWGENERAL_RSVD       0xfffff800
-#define BF_USBCTRL_HWGENERAL_RSVD(v)    (((v) << 11) & 0xfffff800)
-#define BP_USBCTRL_HWGENERAL_SM         9
-#define BM_USBCTRL_HWGENERAL_SM         0x600
-#define BF_USBCTRL_HWGENERAL_SM(v)      (((v) << 9) & 0x600)
-#define BP_USBCTRL_HWGENERAL_PHYM       6
-#define BM_USBCTRL_HWGENERAL_PHYM       0x1c0
-#define BF_USBCTRL_HWGENERAL_PHYM(v)    (((v) << 6) & 0x1c0)
-#define BP_USBCTRL_HWGENERAL_PHYW       4
-#define BM_USBCTRL_HWGENERAL_PHYW       0x30
-#define BF_USBCTRL_HWGENERAL_PHYW(v)    (((v) << 4) & 0x30)
-#define BP_USBCTRL_HWGENERAL_BWT        3
-#define BM_USBCTRL_HWGENERAL_BWT        0x8
-#define BF_USBCTRL_HWGENERAL_BWT(v)     (((v) << 3) & 0x8)
-#define BP_USBCTRL_HWGENERAL_CLKC       1
-#define BM_USBCTRL_HWGENERAL_CLKC       0x6
-#define BF_USBCTRL_HWGENERAL_CLKC(v)    (((v) << 1) & 0x6)
-#define BP_USBCTRL_HWGENERAL_RT         0
-#define BM_USBCTRL_HWGENERAL_RT         0x1
-#define BF_USBCTRL_HWGENERAL_RT(v)      (((v) << 0) & 0x1)
-
-/**
- * Register: HW_USBCTRL_HWHOST
- * Address: 0x8
- * SCT: no
-*/
-#define HW_USBCTRL_HWHOST           (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x8))
-#define BP_USBCTRL_HWHOST_TTPER     24
-#define BM_USBCTRL_HWHOST_TTPER     0xff000000
-#define BF_USBCTRL_HWHOST_TTPER(v)  (((v) << 24) & 0xff000000)
-#define BP_USBCTRL_HWHOST_TTASY     16
-#define BM_USBCTRL_HWHOST_TTASY     0xff0000
-#define BF_USBCTRL_HWHOST_TTASY(v)  (((v) << 16) & 0xff0000)
-#define BP_USBCTRL_HWHOST_RSVD      4
-#define BM_USBCTRL_HWHOST_RSVD      0xfff0
-#define BF_USBCTRL_HWHOST_RSVD(v)   (((v) << 4) & 0xfff0)
-#define BP_USBCTRL_HWHOST_NPORT     1
-#define BM_USBCTRL_HWHOST_NPORT     0xe
-#define BF_USBCTRL_HWHOST_NPORT(v)  (((v) << 1) & 0xe)
-#define BP_USBCTRL_HWHOST_HC        0
-#define BM_USBCTRL_HWHOST_HC        0x1
-#define BF_USBCTRL_HWHOST_HC(v)     (((v) << 0) & 0x1)
-
-/**
- * Register: HW_USBCTRL_HWDEVICE
- * Address: 0xc
- * SCT: no
-*/
-#define HW_USBCTRL_HWDEVICE             (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0xc))
-#define BP_USBCTRL_HWDEVICE_RSVD        6
-#define BM_USBCTRL_HWDEVICE_RSVD        0xffffffc0
-#define BF_USBCTRL_HWDEVICE_RSVD(v)     (((v) << 6) & 0xffffffc0)
-#define BP_USBCTRL_HWDEVICE_DEVEP       1
-#define BM_USBCTRL_HWDEVICE_DEVEP       0x3e
-#define BF_USBCTRL_HWDEVICE_DEVEP(v)    (((v) << 1) & 0x3e)
-#define BP_USBCTRL_HWDEVICE_DC          0
-#define BM_USBCTRL_HWDEVICE_DC          0x1
-#define BF_USBCTRL_HWDEVICE_DC(v)       (((v) << 0) & 0x1)
-
-/**
- * Register: HW_USBCTRL_HWTXBUF
- * Address: 0x10
- * SCT: no
-*/
-#define HW_USBCTRL_HWTXBUF              (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x10))
-#define BP_USBCTRL_HWTXBUF_TXLCR        31
-#define BM_USBCTRL_HWTXBUF_TXLCR        0x80000000
-#define BF_USBCTRL_HWTXBUF_TXLCR(v)     (((v) << 31) & 0x80000000)
-#define BP_USBCTRL_HWTXBUF_RSVD         24
-#define BM_USBCTRL_HWTXBUF_RSVD         0x7f000000
-#define BF_USBCTRL_HWTXBUF_RSVD(v)      (((v) << 24) & 0x7f000000)
-#define BP_USBCTRL_HWTXBUF_TXCHANADD    16
-#define BM_USBCTRL_HWTXBUF_TXCHANADD    0xff0000
-#define BF_USBCTRL_HWTXBUF_TXCHANADD(v) (((v) << 16) & 0xff0000)
-#define BP_USBCTRL_HWTXBUF_TXADD        8
-#define BM_USBCTRL_HWTXBUF_TXADD        0xff00
-#define BF_USBCTRL_HWTXBUF_TXADD(v)     (((v) << 8) & 0xff00)
-#define BP_USBCTRL_HWTXBUF_TXBURST      0
-#define BM_USBCTRL_HWTXBUF_TXBURST      0xff
-#define BF_USBCTRL_HWTXBUF_TXBURST(v)   (((v) << 0) & 0xff)
-
-/**
- * Register: HW_USBCTRL_HWRXBUF
- * Address: 0x14
- * SCT: no
-*/
-#define HW_USBCTRL_HWRXBUF              (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x14))
-#define BP_USBCTRL_HWRXBUF_RSVD         16
-#define BM_USBCTRL_HWRXBUF_RSVD         0xffff0000
-#define BF_USBCTRL_HWRXBUF_RSVD(v)      (((v) << 16) & 0xffff0000)
-#define BP_USBCTRL_HWRXBUF_RXADD        8
-#define BM_USBCTRL_HWRXBUF_RXADD        0xff00
-#define BF_USBCTRL_HWRXBUF_RXADD(v)     (((v) << 8) & 0xff00)
-#define BP_USBCTRL_HWRXBUF_RXBURST      0
-#define BM_USBCTRL_HWRXBUF_RXBURST      0xff
-#define BF_USBCTRL_HWRXBUF_RXBURST(v)   (((v) << 0) & 0xff)
-
-/**
- * Register: HW_USBCTRL_GPTIMER0LD
- * Address: 0x80
- * SCT: no
-*/
-#define HW_USBCTRL_GPTIMER0LD           (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x80))
-#define BP_USBCTRL_GPTIMER0LD_RSVD0     24
-#define BM_USBCTRL_GPTIMER0LD_RSVD0     0xff000000
-#define BF_USBCTRL_GPTIMER0LD_RSVD0(v)  (((v) << 24) & 0xff000000)
-#define BP_USBCTRL_GPTIMER0LD_GPTLD     0
-#define BM_USBCTRL_GPTIMER0LD_GPTLD     0xffffff
-#define BF_USBCTRL_GPTIMER0LD_GPTLD(v)  (((v) << 0) & 0xffffff)
-
-/**
- * Register: HW_USBCTRL_GPTIMER0CTRL
- * Address: 0x84
- * SCT: no
-*/
-#define HW_USBCTRL_GPTIMER0CTRL                     (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x84))
-#define BP_USBCTRL_GPTIMER0CTRL_GPTRUN              31
-#define BM_USBCTRL_GPTIMER0CTRL_GPTRUN              0x80000000
-#define BV_USBCTRL_GPTIMER0CTRL_GPTRUN__STOP        0x0
-#define BV_USBCTRL_GPTIMER0CTRL_GPTRUN__RUN         0x1
-#define BF_USBCTRL_GPTIMER0CTRL_GPTRUN(v)           (((v) << 31) & 0x80000000)
-#define BF_USBCTRL_GPTIMER0CTRL_GPTRUN_V(v)         ((BV_USBCTRL_GPTIMER0CTRL_GPTRUN__##v << 31) & 0x80000000)
-#define BP_USBCTRL_GPTIMER0CTRL_GPTRST              30
-#define BM_USBCTRL_GPTIMER0CTRL_GPTRST              0x40000000
-#define BV_USBCTRL_GPTIMER0CTRL_GPTRST__NOACTION    0x0
-#define BV_USBCTRL_GPTIMER0CTRL_GPTRST__LOADCOUNTER 0x1
-#define BF_USBCTRL_GPTIMER0CTRL_GPTRST(v)           (((v) << 30) & 0x40000000)
-#define BF_USBCTRL_GPTIMER0CTRL_GPTRST_V(v)         ((BV_USBCTRL_GPTIMER0CTRL_GPTRST__##v << 30) & 0x40000000)
-#define BP_USBCTRL_GPTIMER0CTRL_RSVD0               25
-#define BM_USBCTRL_GPTIMER0CTRL_RSVD0               0x3e000000
-#define BF_USBCTRL_GPTIMER0CTRL_RSVD0(v)            (((v) << 25) & 0x3e000000)
-#define BP_USBCTRL_GPTIMER0CTRL_GPTMODE             24
-#define BM_USBCTRL_GPTIMER0CTRL_GPTMODE             0x1000000
-#define BV_USBCTRL_GPTIMER0CTRL_GPTMODE__ONESHOT    0x0
-#define BV_USBCTRL_GPTIMER0CTRL_GPTMODE__REPEAT     0x1
-#define BF_USBCTRL_GPTIMER0CTRL_GPTMODE(v)          (((v) << 24) & 0x1000000)
-#define BF_USBCTRL_GPTIMER0CTRL_GPTMODE_V(v)        ((BV_USBCTRL_GPTIMER0CTRL_GPTMODE__##v << 24) & 0x1000000)
-#define BP_USBCTRL_GPTIMER0CTRL_GPTCNT              0
-#define BM_USBCTRL_GPTIMER0CTRL_GPTCNT              0xffffff
-#define BF_USBCTRL_GPTIMER0CTRL_GPTCNT(v)           (((v) << 0) & 0xffffff)
-
-/**
- * Register: HW_USBCTRL_GPTIMER1LD
- * Address: 0x88
- * SCT: no
-*/
-#define HW_USBCTRL_GPTIMER1LD           (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x88))
-#define BP_USBCTRL_GPTIMER1LD_RSVD0     24
-#define BM_USBCTRL_GPTIMER1LD_RSVD0     0xff000000
-#define BF_USBCTRL_GPTIMER1LD_RSVD0(v)  (((v) << 24) & 0xff000000)
-#define BP_USBCTRL_GPTIMER1LD_GPTLD     0
-#define BM_USBCTRL_GPTIMER1LD_GPTLD     0xffffff
-#define BF_USBCTRL_GPTIMER1LD_GPTLD(v)  (((v) << 0) & 0xffffff)
-
-/**
- * Register: HW_USBCTRL_GPTIMER1CTRL
- * Address: 0x8c
- * SCT: no
-*/
-#define HW_USBCTRL_GPTIMER1CTRL                     (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x8c))
-#define BP_USBCTRL_GPTIMER1CTRL_GPTRUN              31
-#define BM_USBCTRL_GPTIMER1CTRL_GPTRUN              0x80000000
-#define BV_USBCTRL_GPTIMER1CTRL_GPTRUN__STOP        0x0
-#define BV_USBCTRL_GPTIMER1CTRL_GPTRUN__RUN         0x1
-#define BF_USBCTRL_GPTIMER1CTRL_GPTRUN(v)           (((v) << 31) & 0x80000000)
-#define BF_USBCTRL_GPTIMER1CTRL_GPTRUN_V(v)         ((BV_USBCTRL_GPTIMER1CTRL_GPTRUN__##v << 31) & 0x80000000)
-#define BP_USBCTRL_GPTIMER1CTRL_GPTRST              30
-#define BM_USBCTRL_GPTIMER1CTRL_GPTRST              0x40000000
-#define BV_USBCTRL_GPTIMER1CTRL_GPTRST__NOACTION    0x0
-#define BV_USBCTRL_GPTIMER1CTRL_GPTRST__LOADCOUNTER 0x1
-#define BF_USBCTRL_GPTIMER1CTRL_GPTRST(v)           (((v) << 30) & 0x40000000)
-#define BF_USBCTRL_GPTIMER1CTRL_GPTRST_V(v)         ((BV_USBCTRL_GPTIMER1CTRL_GPTRST__##v << 30) & 0x40000000)
-#define BP_USBCTRL_GPTIMER1CTRL_RSVD0               25
-#define BM_USBCTRL_GPTIMER1CTRL_RSVD0               0x3e000000
-#define BF_USBCTRL_GPTIMER1CTRL_RSVD0(v)            (((v) << 25) & 0x3e000000)
-#define BP_USBCTRL_GPTIMER1CTRL_GPTMODE             24
-#define BM_USBCTRL_GPTIMER1CTRL_GPTMODE             0x1000000
-#define BV_USBCTRL_GPTIMER1CTRL_GPTMODE__ONESHOT    0x0
-#define BV_USBCTRL_GPTIMER1CTRL_GPTMODE__REPEAT     0x1
-#define BF_USBCTRL_GPTIMER1CTRL_GPTMODE(v)          (((v) << 24) & 0x1000000)
-#define BF_USBCTRL_GPTIMER1CTRL_GPTMODE_V(v)        ((BV_USBCTRL_GPTIMER1CTRL_GPTMODE__##v << 24) & 0x1000000)
-#define BP_USBCTRL_GPTIMER1CTRL_GPTCNT              0
-#define BM_USBCTRL_GPTIMER1CTRL_GPTCNT              0xffffff
-#define BF_USBCTRL_GPTIMER1CTRL_GPTCNT(v)           (((v) << 0) & 0xffffff)
-
-/**
- * Register: HW_USBCTRL_SBUSCFG
- * Address: 0x90
- * SCT: no
-*/
-#define HW_USBCTRL_SBUSCFG                      (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x90))
-#define BP_USBCTRL_SBUSCFG_RSVD                 3
-#define BM_USBCTRL_SBUSCFG_RSVD                 0xfffffff8
-#define BF_USBCTRL_SBUSCFG_RSVD(v)              (((v) << 3) & 0xfffffff8)
-#define BP_USBCTRL_SBUSCFG_AHBBRST              0
-#define BM_USBCTRL_SBUSCFG_AHBBRST              0x7
-#define BV_USBCTRL_SBUSCFG_AHBBRST__U_INCR      0x0
-#define BV_USBCTRL_SBUSCFG_AHBBRST__S_INCR4     0x1
-#define BV_USBCTRL_SBUSCFG_AHBBRST__S_INCR8     0x2
-#define BV_USBCTRL_SBUSCFG_AHBBRST__S_INCR16    0x3
-#define BV_USBCTRL_SBUSCFG_AHBBRST__RESERVED    0x4
-#define BV_USBCTRL_SBUSCFG_AHBBRST__U_INCR4     0x5
-#define BV_USBCTRL_SBUSCFG_AHBBRST__U_INCR8     0x6
-#define BV_USBCTRL_SBUSCFG_AHBBRST__U_INCR16    0x7
-#define BF_USBCTRL_SBUSCFG_AHBBRST(v)           (((v) << 0) & 0x7)
-#define BF_USBCTRL_SBUSCFG_AHBBRST_V(v)         ((BV_USBCTRL_SBUSCFG_AHBBRST__##v << 0) & 0x7)
-
-/**
- * Register: HW_USBCTRL_CAPLENGTH
- * Address: 0x100
- * SCT: no
-*/
-#define HW_USBCTRL_CAPLENGTH                (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x100))
-#define BP_USBCTRL_CAPLENGTH_HCIVERSION     16
-#define BM_USBCTRL_CAPLENGTH_HCIVERSION     0xffff0000
-#define BF_USBCTRL_CAPLENGTH_HCIVERSION(v)  (((v) << 16) & 0xffff0000)
-#define BP_USBCTRL_CAPLENGTH_RSVD           8
-#define BM_USBCTRL_CAPLENGTH_RSVD           0xff00
-#define BF_USBCTRL_CAPLENGTH_RSVD(v)        (((v) << 8) & 0xff00)
-#define BP_USBCTRL_CAPLENGTH_CAPLENGTH      0
-#define BM_USBCTRL_CAPLENGTH_CAPLENGTH      0xff
-#define BF_USBCTRL_CAPLENGTH_CAPLENGTH(v)   (((v) << 0) & 0xff)
-
-/**
- * Register: HW_USBCTRL_HCSPARAMS
- * Address: 0x104
- * SCT: no
-*/
-#define HW_USBCTRL_HCSPARAMS            (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x104))
-#define BP_USBCTRL_HCSPARAMS_RSVD2      28
-#define BM_USBCTRL_HCSPARAMS_RSVD2      0xf0000000
-#define BF_USBCTRL_HCSPARAMS_RSVD2(v)   (((v) << 28) & 0xf0000000)
-#define BP_USBCTRL_HCSPARAMS_N_TT       24
-#define BM_USBCTRL_HCSPARAMS_N_TT       0xf000000
-#define BF_USBCTRL_HCSPARAMS_N_TT(v)    (((v) << 24) & 0xf000000)
-#define BP_USBCTRL_HCSPARAMS_N_PTT      20
-#define BM_USBCTRL_HCSPARAMS_N_PTT      0xf00000
-#define BF_USBCTRL_HCSPARAMS_N_PTT(v)   (((v) << 20) & 0xf00000)
-#define BP_USBCTRL_HCSPARAMS_RSVD1      17
-#define BM_USBCTRL_HCSPARAMS_RSVD1      0xe0000
-#define BF_USBCTRL_HCSPARAMS_RSVD1(v)   (((v) << 17) & 0xe0000)
-#define BP_USBCTRL_HCSPARAMS_PI         16
-#define BM_USBCTRL_HCSPARAMS_PI         0x10000
-#define BF_USBCTRL_HCSPARAMS_PI(v)      (((v) << 16) & 0x10000)
-#define BP_USBCTRL_HCSPARAMS_N_CC       12
-#define BM_USBCTRL_HCSPARAMS_N_CC       0xf000
-#define BF_USBCTRL_HCSPARAMS_N_CC(v)    (((v) << 12) & 0xf000)
-#define BP_USBCTRL_HCSPARAMS_N_PCC      8
-#define BM_USBCTRL_HCSPARAMS_N_PCC      0xf00
-#define BF_USBCTRL_HCSPARAMS_N_PCC(v)   (((v) << 8) & 0xf00)
-#define BP_USBCTRL_HCSPARAMS_RSVD0      5
-#define BM_USBCTRL_HCSPARAMS_RSVD0      0xe0
-#define BF_USBCTRL_HCSPARAMS_RSVD0(v)   (((v) << 5) & 0xe0)
-#define BP_USBCTRL_HCSPARAMS_PPC        4
-#define BM_USBCTRL_HCSPARAMS_PPC        0x10
-#define BF_USBCTRL_HCSPARAMS_PPC(v)     (((v) << 4) & 0x10)
-#define BP_USBCTRL_HCSPARAMS_N_PORTS    0
-#define BM_USBCTRL_HCSPARAMS_N_PORTS    0xf
-#define BF_USBCTRL_HCSPARAMS_N_PORTS(v) (((v) << 0) & 0xf)
-
-/**
- * Register: HW_USBCTRL_HCCPARAMS
- * Address: 0x108
- * SCT: no
-*/
-#define HW_USBCTRL_HCCPARAMS            (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x108))
-#define BP_USBCTRL_HCCPARAMS_RSVD2      16
-#define BM_USBCTRL_HCCPARAMS_RSVD2      0xffff0000
-#define BF_USBCTRL_HCCPARAMS_RSVD2(v)   (((v) << 16) & 0xffff0000)
-#define BP_USBCTRL_HCCPARAMS_EECP       8
-#define BM_USBCTRL_HCCPARAMS_EECP       0xff00
-#define BF_USBCTRL_HCCPARAMS_EECP(v)    (((v) << 8) & 0xff00)
-#define BP_USBCTRL_HCCPARAMS_IST        4
-#define BM_USBCTRL_HCCPARAMS_IST        0xf0
-#define BF_USBCTRL_HCCPARAMS_IST(v)     (((v) << 4) & 0xf0)
-#define BP_USBCTRL_HCCPARAMS_RSVD0      3
-#define BM_USBCTRL_HCCPARAMS_RSVD0      0x8
-#define BF_USBCTRL_HCCPARAMS_RSVD0(v)   (((v) << 3) & 0x8)
-#define BP_USBCTRL_HCCPARAMS_ASP        2
-#define BM_USBCTRL_HCCPARAMS_ASP        0x4
-#define BF_USBCTRL_HCCPARAMS_ASP(v)     (((v) << 2) & 0x4)
-#define BP_USBCTRL_HCCPARAMS_PFL        1
-#define BM_USBCTRL_HCCPARAMS_PFL        0x2
-#define BF_USBCTRL_HCCPARAMS_PFL(v)     (((v) << 1) & 0x2)
-#define BP_USBCTRL_HCCPARAMS_ADC        0
-#define BM_USBCTRL_HCCPARAMS_ADC        0x1
-#define BF_USBCTRL_HCCPARAMS_ADC(v)     (((v) << 0) & 0x1)
-
-/**
- * Register: HW_USBCTRL_DCIVERSION
- * Address: 0x120
- * SCT: no
-*/
-#define HW_USBCTRL_DCIVERSION               (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x120))
-#define BP_USBCTRL_DCIVERSION_RSVD          16
-#define BM_USBCTRL_DCIVERSION_RSVD          0xffff0000
-#define BF_USBCTRL_DCIVERSION_RSVD(v)       (((v) << 16) & 0xffff0000)
-#define BP_USBCTRL_DCIVERSION_DCIVERSION    0
-#define BM_USBCTRL_DCIVERSION_DCIVERSION    0xffff
-#define BF_USBCTRL_DCIVERSION_DCIVERSION(v) (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_USBCTRL_DCCPARAMS
- * Address: 0x124
- * SCT: no
-*/
-#define HW_USBCTRL_DCCPARAMS            (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x124))
-#define BP_USBCTRL_DCCPARAMS_RSVD1      9
-#define BM_USBCTRL_DCCPARAMS_RSVD1      0xfffffe00
-#define BF_USBCTRL_DCCPARAMS_RSVD1(v)   (((v) << 9) & 0xfffffe00)
-#define BP_USBCTRL_DCCPARAMS_HC         8
-#define BM_USBCTRL_DCCPARAMS_HC         0x100
-#define BF_USBCTRL_DCCPARAMS_HC(v)      (((v) << 8) & 0x100)
-#define BP_USBCTRL_DCCPARAMS_DC         7
-#define BM_USBCTRL_DCCPARAMS_DC         0x80
-#define BF_USBCTRL_DCCPARAMS_DC(v)      (((v) << 7) & 0x80)
-#define BP_USBCTRL_DCCPARAMS_RSVD2      5
-#define BM_USBCTRL_DCCPARAMS_RSVD2      0x60
-#define BF_USBCTRL_DCCPARAMS_RSVD2(v)   (((v) << 5) & 0x60)
-#define BP_USBCTRL_DCCPARAMS_DEN        0
-#define BM_USBCTRL_DCCPARAMS_DEN        0x1f
-#define BF_USBCTRL_DCCPARAMS_DEN(v)     (((v) << 0) & 0x1f)
-
-/**
- * Register: HW_USBCTRL_USBCMD
- * Address: 0x140
- * SCT: no
-*/
-#define HW_USBCTRL_USBCMD                       (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x140))
-#define BP_USBCTRL_USBCMD_RSVD3                 24
-#define BM_USBCTRL_USBCMD_RSVD3                 0xff000000
-#define BF_USBCTRL_USBCMD_RSVD3(v)              (((v) << 24) & 0xff000000)
-#define BP_USBCTRL_USBCMD_ITC                   16
-#define BM_USBCTRL_USBCMD_ITC                   0xff0000
-#define BV_USBCTRL_USBCMD_ITC__IMM              0x0
-#define BV_USBCTRL_USBCMD_ITC__1_MICROFRAME     0x1
-#define BV_USBCTRL_USBCMD_ITC__2_MICROFRAME     0x2
-#define BV_USBCTRL_USBCMD_ITC__4_MICROFRAME     0x4
-#define BV_USBCTRL_USBCMD_ITC__8_MICROFRAME     0x8
-#define BV_USBCTRL_USBCMD_ITC__16_MICROFRAME    0x10
-#define BV_USBCTRL_USBCMD_ITC__32_MICROFRAME    0x20
-#define BV_USBCTRL_USBCMD_ITC__64_MICROFRAME    0x40
-#define BF_USBCTRL_USBCMD_ITC(v)                (((v) << 16) & 0xff0000)
-#define BF_USBCTRL_USBCMD_ITC_V(v)              ((BV_USBCTRL_USBCMD_ITC__##v << 16) & 0xff0000)
-#define BP_USBCTRL_USBCMD_FS2                   15
-#define BM_USBCTRL_USBCMD_FS2                   0x8000
-#define BF_USBCTRL_USBCMD_FS2(v)                (((v) << 15) & 0x8000)
-#define BP_USBCTRL_USBCMD_ATDTW                 14
-#define BM_USBCTRL_USBCMD_ATDTW                 0x4000
-#define BF_USBCTRL_USBCMD_ATDTW(v)              (((v) << 14) & 0x4000)
-#define BP_USBCTRL_USBCMD_SUTW                  13
-#define BM_USBCTRL_USBCMD_SUTW                  0x2000
-#define BF_USBCTRL_USBCMD_SUTW(v)               (((v) << 13) & 0x2000)
-#define BP_USBCTRL_USBCMD_RSVD2                 12
-#define BM_USBCTRL_USBCMD_RSVD2                 0x1000
-#define BF_USBCTRL_USBCMD_RSVD2(v)              (((v) << 12) & 0x1000)
-#define BP_USBCTRL_USBCMD_ASPE                  11
-#define BM_USBCTRL_USBCMD_ASPE                  0x800
-#define BF_USBCTRL_USBCMD_ASPE(v)               (((v) << 11) & 0x800)
-#define BP_USBCTRL_USBCMD_RSVD1                 10
-#define BM_USBCTRL_USBCMD_RSVD1                 0x400
-#define BF_USBCTRL_USBCMD_RSVD1(v)              (((v) << 10) & 0x400)
-#define BP_USBCTRL_USBCMD_ASP                   8
-#define BM_USBCTRL_USBCMD_ASP                   0x300
-#define BF_USBCTRL_USBCMD_ASP(v)                (((v) << 8) & 0x300)
-#define BP_USBCTRL_USBCMD_LR                    7
-#define BM_USBCTRL_USBCMD_LR                    0x80
-#define BF_USBCTRL_USBCMD_LR(v)                 (((v) << 7) & 0x80)
-#define BP_USBCTRL_USBCMD_IAA                   6
-#define BM_USBCTRL_USBCMD_IAA                   0x40
-#define BF_USBCTRL_USBCMD_IAA(v)                (((v) << 6) & 0x40)
-#define BP_USBCTRL_USBCMD_ASE                   5
-#define BM_USBCTRL_USBCMD_ASE                   0x20
-#define BF_USBCTRL_USBCMD_ASE(v)                (((v) << 5) & 0x20)
-#define BP_USBCTRL_USBCMD_PSE                   4
-#define BM_USBCTRL_USBCMD_PSE                   0x10
-#define BF_USBCTRL_USBCMD_PSE(v)                (((v) << 4) & 0x10)
-#define BP_USBCTRL_USBCMD_FS1                   3
-#define BM_USBCTRL_USBCMD_FS1                   0x8
-#define BF_USBCTRL_USBCMD_FS1(v)                (((v) << 3) & 0x8)
-#define BP_USBCTRL_USBCMD_FS0                   2
-#define BM_USBCTRL_USBCMD_FS0                   0x4
-#define BF_USBCTRL_USBCMD_FS0(v)                (((v) << 2) & 0x4)
-#define BP_USBCTRL_USBCMD_RST                   1
-#define BM_USBCTRL_USBCMD_RST                   0x2
-#define BF_USBCTRL_USBCMD_RST(v)                (((v) << 1) & 0x2)
-#define BP_USBCTRL_USBCMD_RS                    0
-#define BM_USBCTRL_USBCMD_RS                    0x1
-#define BF_USBCTRL_USBCMD_RS(v)                 (((v) << 0) & 0x1)
-
-/**
- * Register: HW_USBCTRL_USBSTS
- * Address: 0x144
- * SCT: no
-*/
-#define HW_USBCTRL_USBSTS           (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x144))
-#define BP_USBCTRL_USBSTS_RSVD5     26
-#define BM_USBCTRL_USBSTS_RSVD5     0xfc000000
-#define BF_USBCTRL_USBSTS_RSVD5(v)  (((v) << 26) & 0xfc000000)
-#define BP_USBCTRL_USBSTS_TI1       25
-#define BM_USBCTRL_USBSTS_TI1       0x2000000
-#define BF_USBCTRL_USBSTS_TI1(v)    (((v) << 25) & 0x2000000)
-#define BP_USBCTRL_USBSTS_TI0       24
-#define BM_USBCTRL_USBSTS_TI0       0x1000000
-#define BF_USBCTRL_USBSTS_TI0(v)    (((v) << 24) & 0x1000000)
-#define BP_USBCTRL_USBSTS_RSVD4     20
-#define BM_USBCTRL_USBSTS_RSVD4     0xf00000
-#define BF_USBCTRL_USBSTS_RSVD4(v)  (((v) << 20) & 0xf00000)
-#define BP_USBCTRL_USBSTS_UPI       19
-#define BM_USBCTRL_USBSTS_UPI       0x80000
-#define BF_USBCTRL_USBSTS_UPI(v)    (((v) << 19) & 0x80000)
-#define BP_USBCTRL_USBSTS_UAI       18
-#define BM_USBCTRL_USBSTS_UAI       0x40000
-#define BF_USBCTRL_USBSTS_UAI(v)    (((v) << 18) & 0x40000)
-#define BP_USBCTRL_USBSTS_RSVD3     17
-#define BM_USBCTRL_USBSTS_RSVD3     0x20000
-#define BF_USBCTRL_USBSTS_RSVD3(v)  (((v) << 17) & 0x20000)
-#define BP_USBCTRL_USBSTS_NAKI      16
-#define BM_USBCTRL_USBSTS_NAKI      0x10000
-#define BF_USBCTRL_USBSTS_NAKI(v)   (((v) << 16) & 0x10000)
-#define BP_USBCTRL_USBSTS_AS        15
-#define BM_USBCTRL_USBSTS_AS        0x8000
-#define BF_USBCTRL_USBSTS_AS(v)     (((v) << 15) & 0x8000)
-#define BP_USBCTRL_USBSTS_PS        14
-#define BM_USBCTRL_USBSTS_PS        0x4000
-#define BF_USBCTRL_USBSTS_PS(v)     (((v) << 14) & 0x4000)
-#define BP_USBCTRL_USBSTS_RCL       13
-#define BM_USBCTRL_USBSTS_RCL       0x2000
-#define BF_USBCTRL_USBSTS_RCL(v)    (((v) << 13) & 0x2000)
-#define BP_USBCTRL_USBSTS_HCH       12
-#define BM_USBCTRL_USBSTS_HCH       0x1000
-#define BF_USBCTRL_USBSTS_HCH(v)    (((v) << 12) & 0x1000)
-#define BP_USBCTRL_USBSTS_RSVD2     11
-#define BM_USBCTRL_USBSTS_RSVD2     0x800
-#define BF_USBCTRL_USBSTS_RSVD2(v)  (((v) << 11) & 0x800)
-#define BP_USBCTRL_USBSTS_ULPII     10
-#define BM_USBCTRL_USBSTS_ULPII     0x400
-#define BF_USBCTRL_USBSTS_ULPII(v)  (((v) << 10) & 0x400)
-#define BP_USBCTRL_USBSTS_RSVD1     9
-#define BM_USBCTRL_USBSTS_RSVD1     0x200
-#define BF_USBCTRL_USBSTS_RSVD1(v)  (((v) << 9) & 0x200)
-#define BP_USBCTRL_USBSTS_SLI       8
-#define BM_USBCTRL_USBSTS_SLI       0x100
-#define BF_USBCTRL_USBSTS_SLI(v)    (((v) << 8) & 0x100)
-#define BP_USBCTRL_USBSTS_SRI       7
-#define BM_USBCTRL_USBSTS_SRI       0x80
-#define BF_USBCTRL_USBSTS_SRI(v)    (((v) << 7) & 0x80)
-#define BP_USBCTRL_USBSTS_URI       6
-#define BM_USBCTRL_USBSTS_URI       0x40
-#define BF_USBCTRL_USBSTS_URI(v)    (((v) << 6) & 0x40)
-#define BP_USBCTRL_USBSTS_AAI       5
-#define BM_USBCTRL_USBSTS_AAI       0x20
-#define BF_USBCTRL_USBSTS_AAI(v)    (((v) << 5) & 0x20)
-#define BP_USBCTRL_USBSTS_SEI       4
-#define BM_USBCTRL_USBSTS_SEI       0x10
-#define BF_USBCTRL_USBSTS_SEI(v)    (((v) << 4) & 0x10)
-#define BP_USBCTRL_USBSTS_FRI       3
-#define BM_USBCTRL_USBSTS_FRI       0x8
-#define BF_USBCTRL_USBSTS_FRI(v)    (((v) << 3) & 0x8)
-#define BP_USBCTRL_USBSTS_PCI       2
-#define BM_USBCTRL_USBSTS_PCI       0x4
-#define BF_USBCTRL_USBSTS_PCI(v)    (((v) << 2) & 0x4)
-#define BP_USBCTRL_USBSTS_UEI       1
-#define BM_USBCTRL_USBSTS_UEI       0x2
-#define BF_USBCTRL_USBSTS_UEI(v)    (((v) << 1) & 0x2)
-#define BP_USBCTRL_USBSTS_UI        0
-#define BM_USBCTRL_USBSTS_UI        0x1
-#define BF_USBCTRL_USBSTS_UI(v)     (((v) << 0) & 0x1)
-
-/**
- * Register: HW_USBCTRL_USBINTR
- * Address: 0x148
- * SCT: no
-*/
-#define HW_USBCTRL_USBINTR          (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x148))
-#define BP_USBCTRL_USBINTR_RSVD5    26
-#define BM_USBCTRL_USBINTR_RSVD5    0xfc000000
-#define BF_USBCTRL_USBINTR_RSVD5(v) (((v) << 26) & 0xfc000000)
-#define BP_USBCTRL_USBINTR_TIE1     25
-#define BM_USBCTRL_USBINTR_TIE1     0x2000000
-#define BF_USBCTRL_USBINTR_TIE1(v)  (((v) << 25) & 0x2000000)
-#define BP_USBCTRL_USBINTR_TIE0     24
-#define BM_USBCTRL_USBINTR_TIE0     0x1000000
-#define BF_USBCTRL_USBINTR_TIE0(v)  (((v) << 24) & 0x1000000)
-#define BP_USBCTRL_USBINTR_RSVD4    20
-#define BM_USBCTRL_USBINTR_RSVD4    0xf00000
-#define BF_USBCTRL_USBINTR_RSVD4(v) (((v) << 20) & 0xf00000)
-#define BP_USBCTRL_USBINTR_UPIE     19
-#define BM_USBCTRL_USBINTR_UPIE     0x80000
-#define BF_USBCTRL_USBINTR_UPIE(v)  (((v) << 19) & 0x80000)
-#define BP_USBCTRL_USBINTR_UAIE     18
-#define BM_USBCTRL_USBINTR_UAIE     0x40000
-#define BF_USBCTRL_USBINTR_UAIE(v)  (((v) << 18) & 0x40000)
-#define BP_USBCTRL_USBINTR_RSVD3    17
-#define BM_USBCTRL_USBINTR_RSVD3    0x20000
-#define BF_USBCTRL_USBINTR_RSVD3(v) (((v) << 17) & 0x20000)
-#define BP_USBCTRL_USBINTR_NAKE     16
-#define BM_USBCTRL_USBINTR_NAKE     0x10000
-#define BF_USBCTRL_USBINTR_NAKE(v)  (((v) << 16) & 0x10000)
-#define BP_USBCTRL_USBINTR_RSVD2    11
-#define BM_USBCTRL_USBINTR_RSVD2    0xf800
-#define BF_USBCTRL_USBINTR_RSVD2(v) (((v) << 11) & 0xf800)
-#define BP_USBCTRL_USBINTR_ULPIE    10
-#define BM_USBCTRL_USBINTR_ULPIE    0x400
-#define BF_USBCTRL_USBINTR_ULPIE(v) (((v) << 10) & 0x400)
-#define BP_USBCTRL_USBINTR_RSVD1    9
-#define BM_USBCTRL_USBINTR_RSVD1    0x200
-#define BF_USBCTRL_USBINTR_RSVD1(v) (((v) << 9) & 0x200)
-#define BP_USBCTRL_USBINTR_SLE      8
-#define BM_USBCTRL_USBINTR_SLE      0x100
-#define BF_USBCTRL_USBINTR_SLE(v)   (((v) << 8) & 0x100)
-#define BP_USBCTRL_USBINTR_SRE      7
-#define BM_USBCTRL_USBINTR_SRE      0x80
-#define BF_USBCTRL_USBINTR_SRE(v)   (((v) << 7) & 0x80)
-#define BP_USBCTRL_USBINTR_URE      6
-#define BM_USBCTRL_USBINTR_URE      0x40
-#define BF_USBCTRL_USBINTR_URE(v)   (((v) << 6) & 0x40)
-#define BP_USBCTRL_USBINTR_AAE      5
-#define BM_USBCTRL_USBINTR_AAE      0x20
-#define BF_USBCTRL_USBINTR_AAE(v)   (((v) << 5) & 0x20)
-#define BP_USBCTRL_USBINTR_SEE      4
-#define BM_USBCTRL_USBINTR_SEE      0x10
-#define BF_USBCTRL_USBINTR_SEE(v)   (((v) << 4) & 0x10)
-#define BP_USBCTRL_USBINTR_FRE      3
-#define BM_USBCTRL_USBINTR_FRE      0x8
-#define BF_USBCTRL_USBINTR_FRE(v)   (((v) << 3) & 0x8)
-#define BP_USBCTRL_USBINTR_PCE      2
-#define BM_USBCTRL_USBINTR_PCE      0x4
-#define BF_USBCTRL_USBINTR_PCE(v)   (((v) << 2) & 0x4)
-#define BP_USBCTRL_USBINTR_UEE      1
-#define BM_USBCTRL_USBINTR_UEE      0x2
-#define BF_USBCTRL_USBINTR_UEE(v)   (((v) << 1) & 0x2)
-#define BP_USBCTRL_USBINTR_UE       0
-#define BM_USBCTRL_USBINTR_UE       0x1
-#define BF_USBCTRL_USBINTR_UE(v)    (((v) << 0) & 0x1)
-
-/**
- * Register: HW_USBCTRL_FRINDEX
- * Address: 0x14c
- * SCT: no
-*/
-#define HW_USBCTRL_FRINDEX                  (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x14c))
-#define BP_USBCTRL_FRINDEX_RSVD             14
-#define BM_USBCTRL_FRINDEX_RSVD             0xffffc000
-#define BF_USBCTRL_FRINDEX_RSVD(v)          (((v) << 14) & 0xffffc000)
-#define BP_USBCTRL_FRINDEX_FRINDEX          3
-#define BM_USBCTRL_FRINDEX_FRINDEX          0x3ff8
-#define BV_USBCTRL_FRINDEX_FRINDEX__N_12    0xc
-#define BV_USBCTRL_FRINDEX_FRINDEX__N_11    0xb
-#define BV_USBCTRL_FRINDEX_FRINDEX__N_10    0xa
-#define BV_USBCTRL_FRINDEX_FRINDEX__N_9     0x9
-#define BV_USBCTRL_FRINDEX_FRINDEX__N_8     0x8
-#define BV_USBCTRL_FRINDEX_FRINDEX__N_7     0x7
-#define BV_USBCTRL_FRINDEX_FRINDEX__N_6     0x6
-#define BV_USBCTRL_FRINDEX_FRINDEX__N_5     0x5
-#define BF_USBCTRL_FRINDEX_FRINDEX(v)       (((v) << 3) & 0x3ff8)
-#define BF_USBCTRL_FRINDEX_FRINDEX_V(v)     ((BV_USBCTRL_FRINDEX_FRINDEX__##v << 3) & 0x3ff8)
-#define BP_USBCTRL_FRINDEX_UINDEX           0
-#define BM_USBCTRL_FRINDEX_UINDEX           0x7
-#define BF_USBCTRL_FRINDEX_UINDEX(v)        (((v) << 0) & 0x7)
-
-/**
- * Register: HW_USBCTRL_PERIODICLISTBASE
- * Address: 0x154
- * SCT: no
-*/
-#define HW_USBCTRL_PERIODICLISTBASE             (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x154))
-#define BP_USBCTRL_PERIODICLISTBASE_PERBASE     12
-#define BM_USBCTRL_PERIODICLISTBASE_PERBASE     0xfffff000
-#define BF_USBCTRL_PERIODICLISTBASE_PERBASE(v)  (((v) << 12) & 0xfffff000)
-#define BP_USBCTRL_PERIODICLISTBASE_RSVD        0
-#define BM_USBCTRL_PERIODICLISTBASE_RSVD        0xfff
-#define BF_USBCTRL_PERIODICLISTBASE_RSVD(v)     (((v) << 0) & 0xfff)
-
-/**
- * Register: HW_USBCTRL_DEVICEADDR
- * Address: 0x154
- * SCT: no
-*/
-#define HW_USBCTRL_DEVICEADDR               (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x154))
-#define BP_USBCTRL_DEVICEADDR_USBADR        25
-#define BM_USBCTRL_DEVICEADDR_USBADR        0xfe000000
-#define BF_USBCTRL_DEVICEADDR_USBADR(v)     (((v) << 25) & 0xfe000000)
-#define BP_USBCTRL_DEVICEADDR_USBADRA       24
-#define BM_USBCTRL_DEVICEADDR_USBADRA       0x1000000
-#define BF_USBCTRL_DEVICEADDR_USBADRA(v)    (((v) << 24) & 0x1000000)
-#define BP_USBCTRL_DEVICEADDR_RSVD          0
-#define BM_USBCTRL_DEVICEADDR_RSVD          0xffffff
-#define BF_USBCTRL_DEVICEADDR_RSVD(v)       (((v) << 0) & 0xffffff)
-
-/**
- * Register: HW_USBCTRL_ASYNCLISTADDR
- * Address: 0x158
- * SCT: no
-*/
-#define HW_USBCTRL_ASYNCLISTADDR            (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x158))
-#define BP_USBCTRL_ASYNCLISTADDR_ASYBASE    5
-#define BM_USBCTRL_ASYNCLISTADDR_ASYBASE    0xffffffe0
-#define BF_USBCTRL_ASYNCLISTADDR_ASYBASE(v) (((v) << 5) & 0xffffffe0)
-#define BP_USBCTRL_ASYNCLISTADDR_RSVD       0
-#define BM_USBCTRL_ASYNCLISTADDR_RSVD       0x1f
-#define BF_USBCTRL_ASYNCLISTADDR_RSVD(v)    (((v) << 0) & 0x1f)
-
-/**
- * Register: HW_USBCTRL_ENDPOINTLISTADDR
- * Address: 0x158
- * SCT: no
-*/
-#define HW_USBCTRL_ENDPOINTLISTADDR             (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x158))
-#define BP_USBCTRL_ENDPOINTLISTADDR_EPBASE      11
-#define BM_USBCTRL_ENDPOINTLISTADDR_EPBASE      0xfffff800
-#define BF_USBCTRL_ENDPOINTLISTADDR_EPBASE(v)   (((v) << 11) & 0xfffff800)
-#define BP_USBCTRL_ENDPOINTLISTADDR_RSVD        0
-#define BM_USBCTRL_ENDPOINTLISTADDR_RSVD        0x7ff
-#define BF_USBCTRL_ENDPOINTLISTADDR_RSVD(v)     (((v) << 0) & 0x7ff)
-
-/**
- * Register: HW_USBCTRL_TTCTRL
- * Address: 0x15c
- * SCT: no
-*/
-#define HW_USBCTRL_TTCTRL           (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x15c))
-#define BP_USBCTRL_TTCTRL_RSVD1     31
-#define BM_USBCTRL_TTCTRL_RSVD1     0x80000000
-#define BF_USBCTRL_TTCTRL_RSVD1(v)  (((v) << 31) & 0x80000000)
-#define BP_USBCTRL_TTCTRL_TTHA      24
-#define BM_USBCTRL_TTCTRL_TTHA      0x7f000000
-#define BF_USBCTRL_TTCTRL_TTHA(v)   (((v) << 24) & 0x7f000000)
-#define BP_USBCTRL_TTCTRL_RSVD2     0
-#define BM_USBCTRL_TTCTRL_RSVD2     0xffffff
-#define BF_USBCTRL_TTCTRL_RSVD2(v)  (((v) << 0) & 0xffffff)
-
-/**
- * Register: HW_USBCTRL_BURSTSIZE
- * Address: 0x160
- * SCT: no
-*/
-#define HW_USBCTRL_BURSTSIZE                (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x160))
-#define BP_USBCTRL_BURSTSIZE_RSVD           16
-#define BM_USBCTRL_BURSTSIZE_RSVD           0xffff0000
-#define BF_USBCTRL_BURSTSIZE_RSVD(v)        (((v) << 16) & 0xffff0000)
-#define BP_USBCTRL_BURSTSIZE_TXPBURST       8
-#define BM_USBCTRL_BURSTSIZE_TXPBURST       0xff00
-#define BF_USBCTRL_BURSTSIZE_TXPBURST(v)    (((v) << 8) & 0xff00)
-#define BP_USBCTRL_BURSTSIZE_RXPBURST       0
-#define BM_USBCTRL_BURSTSIZE_RXPBURST       0xff
-#define BF_USBCTRL_BURSTSIZE_RXPBURST(v)    (((v) << 0) & 0xff)
-
-/**
- * Register: HW_USBCTRL_TXFILLTUNING
- * Address: 0x164
- * SCT: no
-*/
-#define HW_USBCTRL_TXFILLTUNING                 (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x164))
-#define BP_USBCTRL_TXFILLTUNING_RSVD2           22
-#define BM_USBCTRL_TXFILLTUNING_RSVD2           0xffc00000
-#define BF_USBCTRL_TXFILLTUNING_RSVD2(v)        (((v) << 22) & 0xffc00000)
-#define BP_USBCTRL_TXFILLTUNING_TXFIFOTHRES     16
-#define BM_USBCTRL_TXFILLTUNING_TXFIFOTHRES     0x3f0000
-#define BF_USBCTRL_TXFILLTUNING_TXFIFOTHRES(v)  (((v) << 16) & 0x3f0000)
-#define BP_USBCTRL_TXFILLTUNING_RSVD1           13
-#define BM_USBCTRL_TXFILLTUNING_RSVD1           0xe000
-#define BF_USBCTRL_TXFILLTUNING_RSVD1(v)        (((v) << 13) & 0xe000)
-#define BP_USBCTRL_TXFILLTUNING_TXSCHEALTH      8
-#define BM_USBCTRL_TXFILLTUNING_TXSCHEALTH      0x1f00
-#define BF_USBCTRL_TXFILLTUNING_TXSCHEALTH(v)   (((v) << 8) & 0x1f00)
-#define BP_USBCTRL_TXFILLTUNING_RSVD0           7
-#define BM_USBCTRL_TXFILLTUNING_RSVD0           0x80
-#define BF_USBCTRL_TXFILLTUNING_RSVD0(v)        (((v) << 7) & 0x80)
-#define BP_USBCTRL_TXFILLTUNING_TXSCHOH         0
-#define BM_USBCTRL_TXFILLTUNING_TXSCHOH         0x7f
-#define BF_USBCTRL_TXFILLTUNING_TXSCHOH(v)      (((v) << 0) & 0x7f)
-
-/**
- * Register: HW_USBCTRL_IC_USB
- * Address: 0x16c
- * SCT: no
-*/
-#define HW_USBCTRL_IC_USB                       (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x16c))
-#define BP_USBCTRL_IC_USB_RSVD                  4
-#define BM_USBCTRL_IC_USB_RSVD                  0xfffffff0
-#define BF_USBCTRL_IC_USB_RSVD(v)               (((v) << 4) & 0xfffffff0)
-#define BP_USBCTRL_IC_USB_IC_ENABLE             3
-#define BM_USBCTRL_IC_USB_IC_ENABLE             0x8
-#define BF_USBCTRL_IC_USB_IC_ENABLE(v)          (((v) << 3) & 0x8)
-#define BP_USBCTRL_IC_USB_IC_VDD                0
-#define BM_USBCTRL_IC_USB_IC_VDD                0x7
-#define BV_USBCTRL_IC_USB_IC_VDD__VOLTAGE_NONE  0x0
-#define BV_USBCTRL_IC_USB_IC_VDD__VOLTAGE_1_0   0x1
-#define BV_USBCTRL_IC_USB_IC_VDD__VOLTAGE_1_2   0x2
-#define BV_USBCTRL_IC_USB_IC_VDD__VOLTAGE_1_5   0x3
-#define BV_USBCTRL_IC_USB_IC_VDD__VOLTAGE_1_8   0x4
-#define BV_USBCTRL_IC_USB_IC_VDD__VOLTAGE_3_0   0x5
-#define BV_USBCTRL_IC_USB_IC_VDD__RESERVED0     0x6
-#define BV_USBCTRL_IC_USB_IC_VDD__RESERVED1     0x7
-#define BF_USBCTRL_IC_USB_IC_VDD(v)             (((v) << 0) & 0x7)
-#define BF_USBCTRL_IC_USB_IC_VDD_V(v)           ((BV_USBCTRL_IC_USB_IC_VDD__##v << 0) & 0x7)
-
-/**
- * Register: HW_USBCTRL_ULPI
- * Address: 0x170
- * SCT: no
-*/
-#define HW_USBCTRL_ULPI                 (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x170))
-#define BP_USBCTRL_ULPI_ULPIWU          31
-#define BM_USBCTRL_ULPI_ULPIWU          0x80000000
-#define BF_USBCTRL_ULPI_ULPIWU(v)       (((v) << 31) & 0x80000000)
-#define BP_USBCTRL_ULPI_ULPIRUN         30
-#define BM_USBCTRL_ULPI_ULPIRUN         0x40000000
-#define BF_USBCTRL_ULPI_ULPIRUN(v)      (((v) << 30) & 0x40000000)
-#define BP_USBCTRL_ULPI_ULPIRW          29
-#define BM_USBCTRL_ULPI_ULPIRW          0x20000000
-#define BF_USBCTRL_ULPI_ULPIRW(v)       (((v) << 29) & 0x20000000)
-#define BP_USBCTRL_ULPI_RSVD0           28
-#define BM_USBCTRL_ULPI_RSVD0           0x10000000
-#define BF_USBCTRL_ULPI_RSVD0(v)        (((v) << 28) & 0x10000000)
-#define BP_USBCTRL_ULPI_ULPISS          27
-#define BM_USBCTRL_ULPI_ULPISS          0x8000000
-#define BF_USBCTRL_ULPI_ULPISS(v)       (((v) << 27) & 0x8000000)
-#define BP_USBCTRL_ULPI_ULPIPORT        24
-#define BM_USBCTRL_ULPI_ULPIPORT        0x7000000
-#define BF_USBCTRL_ULPI_ULPIPORT(v)     (((v) << 24) & 0x7000000)
-#define BP_USBCTRL_ULPI_ULPIADDR        16
-#define BM_USBCTRL_ULPI_ULPIADDR        0xff0000
-#define BF_USBCTRL_ULPI_ULPIADDR(v)     (((v) << 16) & 0xff0000)
-#define BP_USBCTRL_ULPI_ULPIDATRD       8
-#define BM_USBCTRL_ULPI_ULPIDATRD       0xff00
-#define BF_USBCTRL_ULPI_ULPIDATRD(v)    (((v) << 8) & 0xff00)
-#define BP_USBCTRL_ULPI_ULPIDATWR       0
-#define BM_USBCTRL_ULPI_ULPIDATWR       0xff
-#define BF_USBCTRL_ULPI_ULPIDATWR(v)    (((v) << 0) & 0xff)
-
-/**
- * Register: HW_USBCTRL_ENDPTNAK
- * Address: 0x178
- * SCT: no
-*/
-#define HW_USBCTRL_ENDPTNAK             (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x178))
-#define BP_USBCTRL_ENDPTNAK_RSVD1       21
-#define BM_USBCTRL_ENDPTNAK_RSVD1       0xffe00000
-#define BF_USBCTRL_ENDPTNAK_RSVD1(v)    (((v) << 21) & 0xffe00000)
-#define BP_USBCTRL_ENDPTNAK_EPTN        16
-#define BM_USBCTRL_ENDPTNAK_EPTN        0x1f0000
-#define BF_USBCTRL_ENDPTNAK_EPTN(v)     (((v) << 16) & 0x1f0000)
-#define BP_USBCTRL_ENDPTNAK_RSVD0       5
-#define BM_USBCTRL_ENDPTNAK_RSVD0       0xffe0
-#define BF_USBCTRL_ENDPTNAK_RSVD0(v)    (((v) << 5) & 0xffe0)
-#define BP_USBCTRL_ENDPTNAK_EPRN        0
-#define BM_USBCTRL_ENDPTNAK_EPRN        0x1f
-#define BF_USBCTRL_ENDPTNAK_EPRN(v)     (((v) << 0) & 0x1f)
-
-/**
- * Register: HW_USBCTRL_ENDPTNAKEN
- * Address: 0x17c
- * SCT: no
-*/
-#define HW_USBCTRL_ENDPTNAKEN           (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x17c))
-#define BP_USBCTRL_ENDPTNAKEN_RSVD1     21
-#define BM_USBCTRL_ENDPTNAKEN_RSVD1     0xffe00000
-#define BF_USBCTRL_ENDPTNAKEN_RSVD1(v)  (((v) << 21) & 0xffe00000)
-#define BP_USBCTRL_ENDPTNAKEN_EPTNE     16
-#define BM_USBCTRL_ENDPTNAKEN_EPTNE     0x1f0000
-#define BF_USBCTRL_ENDPTNAKEN_EPTNE(v)  (((v) << 16) & 0x1f0000)
-#define BP_USBCTRL_ENDPTNAKEN_RSVD0     5
-#define BM_USBCTRL_ENDPTNAKEN_RSVD0     0xffe0
-#define BF_USBCTRL_ENDPTNAKEN_RSVD0(v)  (((v) << 5) & 0xffe0)
-#define BP_USBCTRL_ENDPTNAKEN_EPRNE     0
-#define BM_USBCTRL_ENDPTNAKEN_EPRNE     0x1f
-#define BF_USBCTRL_ENDPTNAKEN_EPRNE(v)  (((v) << 0) & 0x1f)
-
-/**
- * Register: HW_USBCTRL_PORTSC1
- * Address: 0x184
- * SCT: no
-*/
-#define HW_USBCTRL_PORTSC1                              (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x184))
-#define BP_USBCTRL_PORTSC1_PTS                          30
-#define BM_USBCTRL_PORTSC1_PTS                          0xc0000000
-#define BV_USBCTRL_PORTSC1_PTS__UTMI                    0x0
-#define BV_USBCTRL_PORTSC1_PTS__PHIL                    0x1
-#define BV_USBCTRL_PORTSC1_PTS__ULPI                    0x2
-#define BV_USBCTRL_PORTSC1_PTS__SERIAL                  0x3
-#define BF_USBCTRL_PORTSC1_PTS(v)                       (((v) << 30) & 0xc0000000)
-#define BF_USBCTRL_PORTSC1_PTS_V(v)                     ((BV_USBCTRL_PORTSC1_PTS__##v << 30) & 0xc0000000)
-#define BP_USBCTRL_PORTSC1_STS                          29
-#define BM_USBCTRL_PORTSC1_STS                          0x20000000
-#define BF_USBCTRL_PORTSC1_STS(v)                       (((v) << 29) & 0x20000000)
-#define BP_USBCTRL_PORTSC1_PTW                          28
-#define BM_USBCTRL_PORTSC1_PTW                          0x10000000
-#define BF_USBCTRL_PORTSC1_PTW(v)                       (((v) << 28) & 0x10000000)
-#define BP_USBCTRL_PORTSC1_PSPD                         26
-#define BM_USBCTRL_PORTSC1_PSPD                         0xc000000
-#define BV_USBCTRL_PORTSC1_PSPD__FULL                   0x0
-#define BV_USBCTRL_PORTSC1_PSPD__LOW                    0x1
-#define BV_USBCTRL_PORTSC1_PSPD__HIGH                   0x2
-#define BF_USBCTRL_PORTSC1_PSPD(v)                      (((v) << 26) & 0xc000000)
-#define BF_USBCTRL_PORTSC1_PSPD_V(v)                    ((BV_USBCTRL_PORTSC1_PSPD__##v << 26) & 0xc000000)
-#define BP_USBCTRL_PORTSC1_SRT                          25
-#define BM_USBCTRL_PORTSC1_SRT                          0x2000000
-#define BF_USBCTRL_PORTSC1_SRT(v)                       (((v) << 25) & 0x2000000)
-#define BP_USBCTRL_PORTSC1_PFSC                         24
-#define BM_USBCTRL_PORTSC1_PFSC                         0x1000000
-#define BF_USBCTRL_PORTSC1_PFSC(v)                      (((v) << 24) & 0x1000000)
-#define BP_USBCTRL_PORTSC1_PHCD                         23
-#define BM_USBCTRL_PORTSC1_PHCD                         0x800000
-#define BF_USBCTRL_PORTSC1_PHCD(v)                      (((v) << 23) & 0x800000)
-#define BP_USBCTRL_PORTSC1_WKOC                         22
-#define BM_USBCTRL_PORTSC1_WKOC                         0x400000
-#define BF_USBCTRL_PORTSC1_WKOC(v)                      (((v) << 22) & 0x400000)
-#define BP_USBCTRL_PORTSC1_WKDS                         21
-#define BM_USBCTRL_PORTSC1_WKDS                         0x200000
-#define BF_USBCTRL_PORTSC1_WKDS(v)                      (((v) << 21) & 0x200000)
-#define BP_USBCTRL_PORTSC1_WKCN                         20
-#define BM_USBCTRL_PORTSC1_WKCN                         0x100000
-#define BF_USBCTRL_PORTSC1_WKCN(v)                      (((v) << 20) & 0x100000)
-#define BP_USBCTRL_PORTSC1_PTC                          16
-#define BM_USBCTRL_PORTSC1_PTC                          0xf0000
-#define BV_USBCTRL_PORTSC1_PTC__TEST_DISABLE            0x0
-#define BV_USBCTRL_PORTSC1_PTC__TEST_J_STATE            0x1
-#define BV_USBCTRL_PORTSC1_PTC__TEST_K_STATE            0x2
-#define BV_USBCTRL_PORTSC1_PTC__TEST_J_SE0_NAK          0x3
-#define BV_USBCTRL_PORTSC1_PTC__TEST_PACKET             0x4
-#define BV_USBCTRL_PORTSC1_PTC__TEST_FORCE_ENABLE_HS    0x5
-#define BV_USBCTRL_PORTSC1_PTC__TEST_FORCE_ENABLE_FS    0x6
-#define BV_USBCTRL_PORTSC1_PTC__TEST_FORCE_ENABLE_LS    0x7
-#define BF_USBCTRL_PORTSC1_PTC(v)                       (((v) << 16) & 0xf0000)
-#define BF_USBCTRL_PORTSC1_PTC_V(v)                     ((BV_USBCTRL_PORTSC1_PTC__##v << 16) & 0xf0000)
-#define BP_USBCTRL_PORTSC1_PIC                          14
-#define BM_USBCTRL_PORTSC1_PIC                          0xc000
-#define BV_USBCTRL_PORTSC1_PIC__OFF                     0x0
-#define BV_USBCTRL_PORTSC1_PIC__AMBER                   0x1
-#define BV_USBCTRL_PORTSC1_PIC__GREEN                   0x2
-#define BV_USBCTRL_PORTSC1_PIC__UNDEF                   0x3
-#define BF_USBCTRL_PORTSC1_PIC(v)                       (((v) << 14) & 0xc000)
-#define BF_USBCTRL_PORTSC1_PIC_V(v)                     ((BV_USBCTRL_PORTSC1_PIC__##v << 14) & 0xc000)
-#define BP_USBCTRL_PORTSC1_PO                           13
-#define BM_USBCTRL_PORTSC1_PO                           0x2000
-#define BF_USBCTRL_PORTSC1_PO(v)                        (((v) << 13) & 0x2000)
-#define BP_USBCTRL_PORTSC1_PP                           12
-#define BM_USBCTRL_PORTSC1_PP                           0x1000
-#define BF_USBCTRL_PORTSC1_PP(v)                        (((v) << 12) & 0x1000)
-#define BP_USBCTRL_PORTSC1_LS                           10
-#define BM_USBCTRL_PORTSC1_LS                           0xc00
-#define BV_USBCTRL_PORTSC1_LS__SE0                      0x0
-#define BV_USBCTRL_PORTSC1_LS__K_STATE                  0x1
-#define BV_USBCTRL_PORTSC1_LS__J_STATE                  0x2
-#define BV_USBCTRL_PORTSC1_LS__UNDEF                    0x3
-#define BF_USBCTRL_PORTSC1_LS(v)                        (((v) << 10) & 0xc00)
-#define BF_USBCTRL_PORTSC1_LS_V(v)                      ((BV_USBCTRL_PORTSC1_LS__##v << 10) & 0xc00)
-#define BP_USBCTRL_PORTSC1_HSP                          9
-#define BM_USBCTRL_PORTSC1_HSP                          0x200
-#define BF_USBCTRL_PORTSC1_HSP(v)                       (((v) << 9) & 0x200)
-#define BP_USBCTRL_PORTSC1_PR                           8
-#define BM_USBCTRL_PORTSC1_PR                           0x100
-#define BF_USBCTRL_PORTSC1_PR(v)                        (((v) << 8) & 0x100)
-#define BP_USBCTRL_PORTSC1_SUSP                         7
-#define BM_USBCTRL_PORTSC1_SUSP                         0x80
-#define BF_USBCTRL_PORTSC1_SUSP(v)                      (((v) << 7) & 0x80)
-#define BP_USBCTRL_PORTSC1_FPR                          6
-#define BM_USBCTRL_PORTSC1_FPR                          0x40
-#define BF_USBCTRL_PORTSC1_FPR(v)                       (((v) << 6) & 0x40)
-#define BP_USBCTRL_PORTSC1_OCC                          5
-#define BM_USBCTRL_PORTSC1_OCC                          0x20
-#define BF_USBCTRL_PORTSC1_OCC(v)                       (((v) << 5) & 0x20)
-#define BP_USBCTRL_PORTSC1_OCA                          4
-#define BM_USBCTRL_PORTSC1_OCA                          0x10
-#define BF_USBCTRL_PORTSC1_OCA(v)                       (((v) << 4) & 0x10)
-#define BP_USBCTRL_PORTSC1_PEC                          3
-#define BM_USBCTRL_PORTSC1_PEC                          0x8
-#define BF_USBCTRL_PORTSC1_PEC(v)                       (((v) << 3) & 0x8)
-#define BP_USBCTRL_PORTSC1_PE                           2
-#define BM_USBCTRL_PORTSC1_PE                           0x4
-#define BF_USBCTRL_PORTSC1_PE(v)                        (((v) << 2) & 0x4)
-#define BP_USBCTRL_PORTSC1_CSC                          1
-#define BM_USBCTRL_PORTSC1_CSC                          0x2
-#define BF_USBCTRL_PORTSC1_CSC(v)                       (((v) << 1) & 0x2)
-#define BP_USBCTRL_PORTSC1_CCS                          0
-#define BM_USBCTRL_PORTSC1_CCS                          0x1
-#define BF_USBCTRL_PORTSC1_CCS(v)                       (((v) << 0) & 0x1)
-
-/**
- * Register: HW_USBCTRL_OTGSC
- * Address: 0x1a4
- * SCT: no
-*/
-#define HW_USBCTRL_OTGSC            (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x1a4))
-#define BP_USBCTRL_OTGSC_RSVD2      31
-#define BM_USBCTRL_OTGSC_RSVD2      0x80000000
-#define BF_USBCTRL_OTGSC_RSVD2(v)   (((v) << 31) & 0x80000000)
-#define BP_USBCTRL_OTGSC_DPIE       30
-#define BM_USBCTRL_OTGSC_DPIE       0x40000000
-#define BF_USBCTRL_OTGSC_DPIE(v)    (((v) << 30) & 0x40000000)
-#define BP_USBCTRL_OTGSC_ONEMSE     29
-#define BM_USBCTRL_OTGSC_ONEMSE     0x20000000
-#define BF_USBCTRL_OTGSC_ONEMSE(v)  (((v) << 29) & 0x20000000)
-#define BP_USBCTRL_OTGSC_BSEIE      28
-#define BM_USBCTRL_OTGSC_BSEIE      0x10000000
-#define BF_USBCTRL_OTGSC_BSEIE(v)   (((v) << 28) & 0x10000000)
-#define BP_USBCTRL_OTGSC_BSVIE      27
-#define BM_USBCTRL_OTGSC_BSVIE      0x8000000
-#define BF_USBCTRL_OTGSC_BSVIE(v)   (((v) << 27) & 0x8000000)
-#define BP_USBCTRL_OTGSC_ASVIE      26
-#define BM_USBCTRL_OTGSC_ASVIE      0x4000000
-#define BF_USBCTRL_OTGSC_ASVIE(v)   (((v) << 26) & 0x4000000)
-#define BP_USBCTRL_OTGSC_AVVIE      25
-#define BM_USBCTRL_OTGSC_AVVIE      0x2000000
-#define BF_USBCTRL_OTGSC_AVVIE(v)   (((v) << 25) & 0x2000000)
-#define BP_USBCTRL_OTGSC_IDIE       24
-#define BM_USBCTRL_OTGSC_IDIE       0x1000000
-#define BF_USBCTRL_OTGSC_IDIE(v)    (((v) << 24) & 0x1000000)
-#define BP_USBCTRL_OTGSC_RSVD1      23
-#define BM_USBCTRL_OTGSC_RSVD1      0x800000
-#define BF_USBCTRL_OTGSC_RSVD1(v)   (((v) << 23) & 0x800000)
-#define BP_USBCTRL_OTGSC_DPIS       22
-#define BM_USBCTRL_OTGSC_DPIS       0x400000
-#define BF_USBCTRL_OTGSC_DPIS(v)    (((v) << 22) & 0x400000)
-#define BP_USBCTRL_OTGSC_ONEMSS     21
-#define BM_USBCTRL_OTGSC_ONEMSS     0x200000
-#define BF_USBCTRL_OTGSC_ONEMSS(v)  (((v) << 21) & 0x200000)
-#define BP_USBCTRL_OTGSC_BSEIS      20
-#define BM_USBCTRL_OTGSC_BSEIS      0x100000
-#define BF_USBCTRL_OTGSC_BSEIS(v)   (((v) << 20) & 0x100000)
-#define BP_USBCTRL_OTGSC_BSVIS      19
-#define BM_USBCTRL_OTGSC_BSVIS      0x80000
-#define BF_USBCTRL_OTGSC_BSVIS(v)   (((v) << 19) & 0x80000)
-#define BP_USBCTRL_OTGSC_ASVIS      18
-#define BM_USBCTRL_OTGSC_ASVIS      0x40000
-#define BF_USBCTRL_OTGSC_ASVIS(v)   (((v) << 18) & 0x40000)
-#define BP_USBCTRL_OTGSC_AVVIS      17
-#define BM_USBCTRL_OTGSC_AVVIS      0x20000
-#define BF_USBCTRL_OTGSC_AVVIS(v)   (((v) << 17) & 0x20000)
-#define BP_USBCTRL_OTGSC_IDIS       16
-#define BM_USBCTRL_OTGSC_IDIS       0x10000
-#define BF_USBCTRL_OTGSC_IDIS(v)    (((v) << 16) & 0x10000)
-#define BP_USBCTRL_OTGSC_RSVD0      15
-#define BM_USBCTRL_OTGSC_RSVD0      0x8000
-#define BF_USBCTRL_OTGSC_RSVD0(v)   (((v) << 15) & 0x8000)
-#define BP_USBCTRL_OTGSC_DPS        14
-#define BM_USBCTRL_OTGSC_DPS        0x4000
-#define BF_USBCTRL_OTGSC_DPS(v)     (((v) << 14) & 0x4000)
-#define BP_USBCTRL_OTGSC_ONEMST     13
-#define BM_USBCTRL_OTGSC_ONEMST     0x2000
-#define BF_USBCTRL_OTGSC_ONEMST(v)  (((v) << 13) & 0x2000)
-#define BP_USBCTRL_OTGSC_BSE        12
-#define BM_USBCTRL_OTGSC_BSE        0x1000
-#define BF_USBCTRL_OTGSC_BSE(v)     (((v) << 12) & 0x1000)
-#define BP_USBCTRL_OTGSC_BSV        11
-#define BM_USBCTRL_OTGSC_BSV        0x800
-#define BF_USBCTRL_OTGSC_BSV(v)     (((v) << 11) & 0x800)
-#define BP_USBCTRL_OTGSC_ASV        10
-#define BM_USBCTRL_OTGSC_ASV        0x400
-#define BF_USBCTRL_OTGSC_ASV(v)     (((v) << 10) & 0x400)
-#define BP_USBCTRL_OTGSC_AVV        9
-#define BM_USBCTRL_OTGSC_AVV        0x200
-#define BF_USBCTRL_OTGSC_AVV(v)     (((v) << 9) & 0x200)
-#define BP_USBCTRL_OTGSC_ID         8
-#define BM_USBCTRL_OTGSC_ID         0x100
-#define BF_USBCTRL_OTGSC_ID(v)      (((v) << 8) & 0x100)
-#define BP_USBCTRL_OTGSC_HABA       7
-#define BM_USBCTRL_OTGSC_HABA       0x80
-#define BF_USBCTRL_OTGSC_HABA(v)    (((v) << 7) & 0x80)
-#define BP_USBCTRL_OTGSC_HADP       6
-#define BM_USBCTRL_OTGSC_HADP       0x40
-#define BF_USBCTRL_OTGSC_HADP(v)    (((v) << 6) & 0x40)
-#define BP_USBCTRL_OTGSC_IDPU       5
-#define BM_USBCTRL_OTGSC_IDPU       0x20
-#define BF_USBCTRL_OTGSC_IDPU(v)    (((v) << 5) & 0x20)
-#define BP_USBCTRL_OTGSC_DP         4
-#define BM_USBCTRL_OTGSC_DP         0x10
-#define BF_USBCTRL_OTGSC_DP(v)      (((v) << 4) & 0x10)
-#define BP_USBCTRL_OTGSC_OT         3
-#define BM_USBCTRL_OTGSC_OT         0x8
-#define BF_USBCTRL_OTGSC_OT(v)      (((v) << 3) & 0x8)
-#define BP_USBCTRL_OTGSC_HAAR       2
-#define BM_USBCTRL_OTGSC_HAAR       0x4
-#define BF_USBCTRL_OTGSC_HAAR(v)    (((v) << 2) & 0x4)
-#define BP_USBCTRL_OTGSC_VC         1
-#define BM_USBCTRL_OTGSC_VC         0x2
-#define BF_USBCTRL_OTGSC_VC(v)      (((v) << 1) & 0x2)
-#define BP_USBCTRL_OTGSC_VD         0
-#define BM_USBCTRL_OTGSC_VD         0x1
-#define BF_USBCTRL_OTGSC_VD(v)      (((v) << 0) & 0x1)
-
-/**
- * Register: HW_USBCTRL_USBMODE
- * Address: 0x1a8
- * SCT: no
-*/
-#define HW_USBCTRL_USBMODE              (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x1a8))
-#define BP_USBCTRL_USBMODE_RSVD         6
-#define BM_USBCTRL_USBMODE_RSVD         0xffffffc0
-#define BF_USBCTRL_USBMODE_RSVD(v)      (((v) << 6) & 0xffffffc0)
-#define BP_USBCTRL_USBMODE_VBPS         5
-#define BM_USBCTRL_USBMODE_VBPS         0x20
-#define BF_USBCTRL_USBMODE_VBPS(v)      (((v) << 5) & 0x20)
-#define BP_USBCTRL_USBMODE_SDIS         4
-#define BM_USBCTRL_USBMODE_SDIS         0x10
-#define BF_USBCTRL_USBMODE_SDIS(v)      (((v) << 4) & 0x10)
-#define BP_USBCTRL_USBMODE_SLOM         3
-#define BM_USBCTRL_USBMODE_SLOM         0x8
-#define BF_USBCTRL_USBMODE_SLOM(v)      (((v) << 3) & 0x8)
-#define BP_USBCTRL_USBMODE_ES           2
-#define BM_USBCTRL_USBMODE_ES           0x4
-#define BF_USBCTRL_USBMODE_ES(v)        (((v) << 2) & 0x4)
-#define BP_USBCTRL_USBMODE_CM           0
-#define BM_USBCTRL_USBMODE_CM           0x3
-#define BV_USBCTRL_USBMODE_CM__IDLE     0x0
-#define BV_USBCTRL_USBMODE_CM__DEVICE   0x2
-#define BV_USBCTRL_USBMODE_CM__HOST     0x3
-#define BF_USBCTRL_USBMODE_CM(v)        (((v) << 0) & 0x3)
-#define BF_USBCTRL_USBMODE_CM_V(v)      ((BV_USBCTRL_USBMODE_CM__##v << 0) & 0x3)
-
-/**
- * Register: HW_USBCTRL_ENDPTSETUPSTAT
- * Address: 0x1ac
- * SCT: no
-*/
-#define HW_USBCTRL_ENDPTSETUPSTAT                   (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x1ac))
-#define BP_USBCTRL_ENDPTSETUPSTAT_RSVD              5
-#define BM_USBCTRL_ENDPTSETUPSTAT_RSVD              0xffffffe0
-#define BF_USBCTRL_ENDPTSETUPSTAT_RSVD(v)           (((v) << 5) & 0xffffffe0)
-#define BP_USBCTRL_ENDPTSETUPSTAT_ENDPTSETUPSTAT    0
-#define BM_USBCTRL_ENDPTSETUPSTAT_ENDPTSETUPSTAT    0x1f
-#define BF_USBCTRL_ENDPTSETUPSTAT_ENDPTSETUPSTAT(v) (((v) << 0) & 0x1f)
-
-/**
- * Register: HW_USBCTRL_ENDPTPRIME
- * Address: 0x1b0
- * SCT: no
-*/
-#define HW_USBCTRL_ENDPTPRIME           (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x1b0))
-#define BP_USBCTRL_ENDPTPRIME_RSVD1     21
-#define BM_USBCTRL_ENDPTPRIME_RSVD1     0xffe00000
-#define BF_USBCTRL_ENDPTPRIME_RSVD1(v)  (((v) << 21) & 0xffe00000)
-#define BP_USBCTRL_ENDPTPRIME_PETB      16
-#define BM_USBCTRL_ENDPTPRIME_PETB      0x1f0000
-#define BF_USBCTRL_ENDPTPRIME_PETB(v)   (((v) << 16) & 0x1f0000)
-#define BP_USBCTRL_ENDPTPRIME_RSVD0     5
-#define BM_USBCTRL_ENDPTPRIME_RSVD0     0xffe0
-#define BF_USBCTRL_ENDPTPRIME_RSVD0(v)  (((v) << 5) & 0xffe0)
-#define BP_USBCTRL_ENDPTPRIME_PERB      0
-#define BM_USBCTRL_ENDPTPRIME_PERB      0x1f
-#define BF_USBCTRL_ENDPTPRIME_PERB(v)   (((v) << 0) & 0x1f)
-
-/**
- * Register: HW_USBCTRL_ENDPTFLUSH
- * Address: 0x1b4
- * SCT: no
-*/
-#define HW_USBCTRL_ENDPTFLUSH           (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x1b4))
-#define BP_USBCTRL_ENDPTFLUSH_RSVD1     21
-#define BM_USBCTRL_ENDPTFLUSH_RSVD1     0xffe00000
-#define BF_USBCTRL_ENDPTFLUSH_RSVD1(v)  (((v) << 21) & 0xffe00000)
-#define BP_USBCTRL_ENDPTFLUSH_FETB      16
-#define BM_USBCTRL_ENDPTFLUSH_FETB      0x1f0000
-#define BF_USBCTRL_ENDPTFLUSH_FETB(v)   (((v) << 16) & 0x1f0000)
-#define BP_USBCTRL_ENDPTFLUSH_RSVD0     5
-#define BM_USBCTRL_ENDPTFLUSH_RSVD0     0xffe0
-#define BF_USBCTRL_ENDPTFLUSH_RSVD0(v)  (((v) << 5) & 0xffe0)
-#define BP_USBCTRL_ENDPTFLUSH_FERB      0
-#define BM_USBCTRL_ENDPTFLUSH_FERB      0x1f
-#define BF_USBCTRL_ENDPTFLUSH_FERB(v)   (((v) << 0) & 0x1f)
-
-/**
- * Register: HW_USBCTRL_ENDPTSTAT
- * Address: 0x1b8
- * SCT: no
-*/
-#define HW_USBCTRL_ENDPTSTAT            (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x1b8))
-#define BP_USBCTRL_ENDPTSTAT_RSVD1      21
-#define BM_USBCTRL_ENDPTSTAT_RSVD1      0xffe00000
-#define BF_USBCTRL_ENDPTSTAT_RSVD1(v)   (((v) << 21) & 0xffe00000)
-#define BP_USBCTRL_ENDPTSTAT_ETBR       16
-#define BM_USBCTRL_ENDPTSTAT_ETBR       0x1f0000
-#define BF_USBCTRL_ENDPTSTAT_ETBR(v)    (((v) << 16) & 0x1f0000)
-#define BP_USBCTRL_ENDPTSTAT_RSVD0      5
-#define BM_USBCTRL_ENDPTSTAT_RSVD0      0xffe0
-#define BF_USBCTRL_ENDPTSTAT_RSVD0(v)   (((v) << 5) & 0xffe0)
-#define BP_USBCTRL_ENDPTSTAT_ERBR       0
-#define BM_USBCTRL_ENDPTSTAT_ERBR       0x1f
-#define BF_USBCTRL_ENDPTSTAT_ERBR(v)    (((v) << 0) & 0x1f)
-
-/**
- * Register: HW_USBCTRL_ENDPTCOMPLETE
- * Address: 0x1bc
- * SCT: no
-*/
-#define HW_USBCTRL_ENDPTCOMPLETE            (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x1bc))
-#define BP_USBCTRL_ENDPTCOMPLETE_RSVD1      21
-#define BM_USBCTRL_ENDPTCOMPLETE_RSVD1      0xffe00000
-#define BF_USBCTRL_ENDPTCOMPLETE_RSVD1(v)   (((v) << 21) & 0xffe00000)
-#define BP_USBCTRL_ENDPTCOMPLETE_ETCE       16
-#define BM_USBCTRL_ENDPTCOMPLETE_ETCE       0x1f0000
-#define BF_USBCTRL_ENDPTCOMPLETE_ETCE(v)    (((v) << 16) & 0x1f0000)
-#define BP_USBCTRL_ENDPTCOMPLETE_RSVD0      5
-#define BM_USBCTRL_ENDPTCOMPLETE_RSVD0      0xffe0
-#define BF_USBCTRL_ENDPTCOMPLETE_RSVD0(v)   (((v) << 5) & 0xffe0)
-#define BP_USBCTRL_ENDPTCOMPLETE_ERCE       0
-#define BM_USBCTRL_ENDPTCOMPLETE_ERCE       0x1f
-#define BF_USBCTRL_ENDPTCOMPLETE_ERCE(v)    (((v) << 0) & 0x1f)
-
-/**
- * Register: HW_USBCTRL_ENDPTCTRLn
- * Address: 0x1c0+n*0x4
- * SCT: no
-*/
-#define HW_USBCTRL_ENDPTCTRLn(n)            (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x1c0+(n)*0x4))
-#define BP_USBCTRL_ENDPTCTRLn_RSVD6         24
-#define BM_USBCTRL_ENDPTCTRLn_RSVD6         0xff000000
-#define BF_USBCTRL_ENDPTCTRLn_RSVD6(v)      (((v) << 24) & 0xff000000)
-#define BP_USBCTRL_ENDPTCTRLn_TXE           23
-#define BM_USBCTRL_ENDPTCTRLn_TXE           0x800000
-#define BF_USBCTRL_ENDPTCTRLn_TXE(v)        (((v) << 23) & 0x800000)
-#define BP_USBCTRL_ENDPTCTRLn_TXR           22
-#define BM_USBCTRL_ENDPTCTRLn_TXR           0x400000
-#define BF_USBCTRL_ENDPTCTRLn_TXR(v)        (((v) << 22) & 0x400000)
-#define BP_USBCTRL_ENDPTCTRLn_TXI           21
-#define BM_USBCTRL_ENDPTCTRLn_TXI           0x200000
-#define BF_USBCTRL_ENDPTCTRLn_TXI(v)        (((v) << 21) & 0x200000)
-#define BP_USBCTRL_ENDPTCTRLn_RSVD5         20
-#define BM_USBCTRL_ENDPTCTRLn_RSVD5         0x100000
-#define BF_USBCTRL_ENDPTCTRLn_RSVD5(v)      (((v) << 20) & 0x100000)
-#define BP_USBCTRL_ENDPTCTRLn_TXT           18
-#define BM_USBCTRL_ENDPTCTRLn_TXT           0xc0000
-#define BV_USBCTRL_ENDPTCTRLn_TXT__CONTROL  0x0
-#define BV_USBCTRL_ENDPTCTRLn_TXT__ISO      0x1
-#define BV_USBCTRL_ENDPTCTRLn_TXT__BULK     0x2
-#define BV_USBCTRL_ENDPTCTRLn_TXT__INT      0x3
-#define BF_USBCTRL_ENDPTCTRLn_TXT(v)        (((v) << 18) & 0xc0000)
-#define BF_USBCTRL_ENDPTCTRLn_TXT_V(v)      ((BV_USBCTRL_ENDPTCTRLn_TXT__##v << 18) & 0xc0000)
-#define BP_USBCTRL_ENDPTCTRLn_TXD           17
-#define BM_USBCTRL_ENDPTCTRLn_TXD           0x20000
-#define BF_USBCTRL_ENDPTCTRLn_TXD(v)        (((v) << 17) & 0x20000)
-#define BP_USBCTRL_ENDPTCTRLn_TXS           16
-#define BM_USBCTRL_ENDPTCTRLn_TXS           0x10000
-#define BF_USBCTRL_ENDPTCTRLn_TXS(v)        (((v) << 16) & 0x10000)
-#define BP_USBCTRL_ENDPTCTRLn_RSVD3         8
-#define BM_USBCTRL_ENDPTCTRLn_RSVD3         0xff00
-#define BF_USBCTRL_ENDPTCTRLn_RSVD3(v)      (((v) << 8) & 0xff00)
-#define BP_USBCTRL_ENDPTCTRLn_RXE           7
-#define BM_USBCTRL_ENDPTCTRLn_RXE           0x80
-#define BF_USBCTRL_ENDPTCTRLn_RXE(v)        (((v) << 7) & 0x80)
-#define BP_USBCTRL_ENDPTCTRLn_RXR           6
-#define BM_USBCTRL_ENDPTCTRLn_RXR           0x40
-#define BF_USBCTRL_ENDPTCTRLn_RXR(v)        (((v) << 6) & 0x40)
-#define BP_USBCTRL_ENDPTCTRLn_RXI           5
-#define BM_USBCTRL_ENDPTCTRLn_RXI           0x20
-#define BF_USBCTRL_ENDPTCTRLn_RXI(v)        (((v) << 5) & 0x20)
-#define BP_USBCTRL_ENDPTCTRLn_RSVD2         4
-#define BM_USBCTRL_ENDPTCTRLn_RSVD2         0x10
-#define BF_USBCTRL_ENDPTCTRLn_RSVD2(v)      (((v) << 4) & 0x10)
-#define BP_USBCTRL_ENDPTCTRLn_RXT           2
-#define BM_USBCTRL_ENDPTCTRLn_RXT           0xc
-#define BV_USBCTRL_ENDPTCTRLn_RXT__CONTROL  0x0
-#define BV_USBCTRL_ENDPTCTRLn_RXT__ISO      0x1
-#define BV_USBCTRL_ENDPTCTRLn_RXT__BULK     0x2
-#define BV_USBCTRL_ENDPTCTRLn_RXT__INT      0x3
-#define BF_USBCTRL_ENDPTCTRLn_RXT(v)        (((v) << 2) & 0xc)
-#define BF_USBCTRL_ENDPTCTRLn_RXT_V(v)      ((BV_USBCTRL_ENDPTCTRLn_RXT__##v << 2) & 0xc)
-#define BP_USBCTRL_ENDPTCTRLn_RXD           1
-#define BM_USBCTRL_ENDPTCTRLn_RXD           0x2
-#define BF_USBCTRL_ENDPTCTRLn_RXD(v)        (((v) << 1) & 0x2)
-#define BP_USBCTRL_ENDPTCTRLn_RXS           0
-#define BM_USBCTRL_ENDPTCTRLn_RXS           0x1
-#define BF_USBCTRL_ENDPTCTRLn_RXS(v)        (((v) << 0) & 0x1)
-
-#endif /* __HEADERGEN__IMX233__USBCTRL__H__ */
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-usbphy.h b/firmware/target/arm/imx233/regs/imx233/regs-usbphy.h
deleted file mode 100644
index f1d2d5abf9..0000000000
--- a/firmware/target/arm/imx233/regs/imx233/regs-usbphy.h
+++ /dev/null
@@ -1,421 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: imx233:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__IMX233__USBPHY__H__
-#define __HEADERGEN__IMX233__USBPHY__H__
-
-#define REGS_USBPHY_BASE (0x8007c000)
-
-#define REGS_USBPHY_VERSION "3.2.0"
-
-/**
- * Register: HW_USBPHY_PWD
- * Address: 0
- * SCT: yes
-*/
-#define HW_USBPHY_PWD               (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x0 + 0x0))
-#define HW_USBPHY_PWD_SET           (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x0 + 0x4))
-#define HW_USBPHY_PWD_CLR           (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x0 + 0x8))
-#define HW_USBPHY_PWD_TOG           (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x0 + 0xc))
-#define BP_USBPHY_PWD_RSVD2         21
-#define BM_USBPHY_PWD_RSVD2         0xffe00000
-#define BF_USBPHY_PWD_RSVD2(v)      (((v) << 21) & 0xffe00000)
-#define BP_USBPHY_PWD_RXPWDRX       20
-#define BM_USBPHY_PWD_RXPWDRX       0x100000
-#define BF_USBPHY_PWD_RXPWDRX(v)    (((v) << 20) & 0x100000)
-#define BP_USBPHY_PWD_RXPWDDIFF     19
-#define BM_USBPHY_PWD_RXPWDDIFF     0x80000
-#define BF_USBPHY_PWD_RXPWDDIFF(v)  (((v) << 19) & 0x80000)
-#define BP_USBPHY_PWD_RXPWD1PT1     18
-#define BM_USBPHY_PWD_RXPWD1PT1     0x40000
-#define BF_USBPHY_PWD_RXPWD1PT1(v)  (((v) << 18) & 0x40000)
-#define BP_USBPHY_PWD_RXPWDENV      17
-#define BM_USBPHY_PWD_RXPWDENV      0x20000
-#define BF_USBPHY_PWD_RXPWDENV(v)   (((v) << 17) & 0x20000)
-#define BP_USBPHY_PWD_RSVD1         13
-#define BM_USBPHY_PWD_RSVD1         0x1e000
-#define BF_USBPHY_PWD_RSVD1(v)      (((v) << 13) & 0x1e000)
-#define BP_USBPHY_PWD_TXPWDV2I      12
-#define BM_USBPHY_PWD_TXPWDV2I      0x1000
-#define BF_USBPHY_PWD_TXPWDV2I(v)   (((v) << 12) & 0x1000)
-#define BP_USBPHY_PWD_TXPWDIBIAS    11
-#define BM_USBPHY_PWD_TXPWDIBIAS    0x800
-#define BF_USBPHY_PWD_TXPWDIBIAS(v) (((v) << 11) & 0x800)
-#define BP_USBPHY_PWD_TXPWDFS       10
-#define BM_USBPHY_PWD_TXPWDFS       0x400
-#define BF_USBPHY_PWD_TXPWDFS(v)    (((v) << 10) & 0x400)
-#define BP_USBPHY_PWD_RSVD0         0
-#define BM_USBPHY_PWD_RSVD0         0x3ff
-#define BF_USBPHY_PWD_RSVD0(v)      (((v) << 0) & 0x3ff)
-
-/**
- * Register: HW_USBPHY_TX
- * Address: 0x10
- * SCT: yes
-*/
-#define HW_USBPHY_TX                            (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x10 + 0x0))
-#define HW_USBPHY_TX_SET                        (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x10 + 0x4))
-#define HW_USBPHY_TX_CLR                        (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x10 + 0x8))
-#define HW_USBPHY_TX_TOG                        (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x10 + 0xc))
-#define BP_USBPHY_TX_RSVD5                      29
-#define BM_USBPHY_TX_RSVD5                      0xe0000000
-#define BF_USBPHY_TX_RSVD5(v)                   (((v) << 29) & 0xe0000000)
-#define BP_USBPHY_TX_USBPHY_TX_EDGECTRL         26
-#define BM_USBPHY_TX_USBPHY_TX_EDGECTRL         0x1c000000
-#define BF_USBPHY_TX_USBPHY_TX_EDGECTRL(v)      (((v) << 26) & 0x1c000000)
-#define BP_USBPHY_TX_USBPHY_TX_SYNC_INVERT      25
-#define BM_USBPHY_TX_USBPHY_TX_SYNC_INVERT      0x2000000
-#define BF_USBPHY_TX_USBPHY_TX_SYNC_INVERT(v)   (((v) << 25) & 0x2000000)
-#define BP_USBPHY_TX_USBPHY_TX_SYNC_MUX         24
-#define BM_USBPHY_TX_USBPHY_TX_SYNC_MUX         0x1000000
-#define BF_USBPHY_TX_USBPHY_TX_SYNC_MUX(v)      (((v) << 24) & 0x1000000)
-#define BP_USBPHY_TX_RSVD4                      22
-#define BM_USBPHY_TX_RSVD4                      0xc00000
-#define BF_USBPHY_TX_RSVD4(v)                   (((v) << 22) & 0xc00000)
-#define BP_USBPHY_TX_TXENCAL45DP                21
-#define BM_USBPHY_TX_TXENCAL45DP                0x200000
-#define BF_USBPHY_TX_TXENCAL45DP(v)             (((v) << 21) & 0x200000)
-#define BP_USBPHY_TX_RSVD3                      20
-#define BM_USBPHY_TX_RSVD3                      0x100000
-#define BF_USBPHY_TX_RSVD3(v)                   (((v) << 20) & 0x100000)
-#define BP_USBPHY_TX_TXCAL45DP                  16
-#define BM_USBPHY_TX_TXCAL45DP                  0xf0000
-#define BF_USBPHY_TX_TXCAL45DP(v)               (((v) << 16) & 0xf0000)
-#define BP_USBPHY_TX_RSVD2                      14
-#define BM_USBPHY_TX_RSVD2                      0xc000
-#define BF_USBPHY_TX_RSVD2(v)                   (((v) << 14) & 0xc000)
-#define BP_USBPHY_TX_TXENCAL45DN                13
-#define BM_USBPHY_TX_TXENCAL45DN                0x2000
-#define BF_USBPHY_TX_TXENCAL45DN(v)             (((v) << 13) & 0x2000)
-#define BP_USBPHY_TX_RSVD1                      12
-#define BM_USBPHY_TX_RSVD1                      0x1000
-#define BF_USBPHY_TX_RSVD1(v)                   (((v) << 12) & 0x1000)
-#define BP_USBPHY_TX_TXCAL45DN                  8
-#define BM_USBPHY_TX_TXCAL45DN                  0xf00
-#define BF_USBPHY_TX_TXCAL45DN(v)               (((v) << 8) & 0xf00)
-#define BP_USBPHY_TX_RSVD0                      4
-#define BM_USBPHY_TX_RSVD0                      0xf0
-#define BF_USBPHY_TX_RSVD0(v)                   (((v) << 4) & 0xf0)
-#define BP_USBPHY_TX_D_CAL                      0
-#define BM_USBPHY_TX_D_CAL                      0xf
-#define BF_USBPHY_TX_D_CAL(v)                   (((v) << 0) & 0xf)
-
-/**
- * Register: HW_USBPHY_RX
- * Address: 0x20
- * SCT: yes
-*/
-#define HW_USBPHY_RX                (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x20 + 0x0))
-#define HW_USBPHY_RX_SET            (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x20 + 0x4))
-#define HW_USBPHY_RX_CLR            (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x20 + 0x8))
-#define HW_USBPHY_RX_TOG            (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x20 + 0xc))
-#define BP_USBPHY_RX_RSVD2          23
-#define BM_USBPHY_RX_RSVD2          0xff800000
-#define BF_USBPHY_RX_RSVD2(v)       (((v) << 23) & 0xff800000)
-#define BP_USBPHY_RX_RXDBYPASS      22
-#define BM_USBPHY_RX_RXDBYPASS      0x400000
-#define BF_USBPHY_RX_RXDBYPASS(v)   (((v) << 22) & 0x400000)
-#define BP_USBPHY_RX_RSVD1          7
-#define BM_USBPHY_RX_RSVD1          0x3fff80
-#define BF_USBPHY_RX_RSVD1(v)       (((v) << 7) & 0x3fff80)
-#define BP_USBPHY_RX_DISCONADJ      4
-#define BM_USBPHY_RX_DISCONADJ      0x70
-#define BF_USBPHY_RX_DISCONADJ(v)   (((v) << 4) & 0x70)
-#define BP_USBPHY_RX_RSVD0          3
-#define BM_USBPHY_RX_RSVD0          0x8
-#define BF_USBPHY_RX_RSVD0(v)       (((v) << 3) & 0x8)
-#define BP_USBPHY_RX_ENVADJ         0
-#define BM_USBPHY_RX_ENVADJ         0x7
-#define BF_USBPHY_RX_ENVADJ(v)      (((v) << 0) & 0x7)
-
-/**
- * Register: HW_USBPHY_CTRL
- * Address: 0x30
- * SCT: yes
-*/
-#define HW_USBPHY_CTRL                          (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x30 + 0x0))
-#define HW_USBPHY_CTRL_SET                      (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x30 + 0x4))
-#define HW_USBPHY_CTRL_CLR                      (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x30 + 0x8))
-#define HW_USBPHY_CTRL_TOG                      (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x30 + 0xc))
-#define BP_USBPHY_CTRL_SFTRST                   31
-#define BM_USBPHY_CTRL_SFTRST                   0x80000000
-#define BF_USBPHY_CTRL_SFTRST(v)                (((v) << 31) & 0x80000000)
-#define BP_USBPHY_CTRL_CLKGATE                  30
-#define BM_USBPHY_CTRL_CLKGATE                  0x40000000
-#define BF_USBPHY_CTRL_CLKGATE(v)               (((v) << 30) & 0x40000000)
-#define BP_USBPHY_CTRL_UTMI_SUSPENDM            29
-#define BM_USBPHY_CTRL_UTMI_SUSPENDM            0x20000000
-#define BF_USBPHY_CTRL_UTMI_SUSPENDM(v)         (((v) << 29) & 0x20000000)
-#define BP_USBPHY_CTRL_HOST_FORCE_LS_SE0        28
-#define BM_USBPHY_CTRL_HOST_FORCE_LS_SE0        0x10000000
-#define BF_USBPHY_CTRL_HOST_FORCE_LS_SE0(v)     (((v) << 28) & 0x10000000)
-#define BP_USBPHY_CTRL_RSVD3                    14
-#define BM_USBPHY_CTRL_RSVD3                    0xfffc000
-#define BF_USBPHY_CTRL_RSVD3(v)                 (((v) << 14) & 0xfffc000)
-#define BP_USBPHY_CTRL_DATA_ON_LRADC            13
-#define BM_USBPHY_CTRL_DATA_ON_LRADC            0x2000
-#define BF_USBPHY_CTRL_DATA_ON_LRADC(v)         (((v) << 13) & 0x2000)
-#define BP_USBPHY_CTRL_DEVPLUGIN_IRQ            12
-#define BM_USBPHY_CTRL_DEVPLUGIN_IRQ            0x1000
-#define BF_USBPHY_CTRL_DEVPLUGIN_IRQ(v)         (((v) << 12) & 0x1000)
-#define BP_USBPHY_CTRL_ENIRQDEVPLUGIN           11
-#define BM_USBPHY_CTRL_ENIRQDEVPLUGIN           0x800
-#define BF_USBPHY_CTRL_ENIRQDEVPLUGIN(v)        (((v) << 11) & 0x800)
-#define BP_USBPHY_CTRL_RESUME_IRQ               10
-#define BM_USBPHY_CTRL_RESUME_IRQ               0x400
-#define BF_USBPHY_CTRL_RESUME_IRQ(v)            (((v) << 10) & 0x400)
-#define BP_USBPHY_CTRL_ENIRQRESUMEDETECT        9
-#define BM_USBPHY_CTRL_ENIRQRESUMEDETECT        0x200
-#define BF_USBPHY_CTRL_ENIRQRESUMEDETECT(v)     (((v) << 9) & 0x200)
-#define BP_USBPHY_CTRL_RSVD2                    8
-#define BM_USBPHY_CTRL_RSVD2                    0x100
-#define BF_USBPHY_CTRL_RSVD2(v)                 (((v) << 8) & 0x100)
-#define BP_USBPHY_CTRL_ENOTGIDDETECT            7
-#define BM_USBPHY_CTRL_ENOTGIDDETECT            0x80
-#define BF_USBPHY_CTRL_ENOTGIDDETECT(v)         (((v) << 7) & 0x80)
-#define BP_USBPHY_CTRL_RSVD1                    6
-#define BM_USBPHY_CTRL_RSVD1                    0x40
-#define BF_USBPHY_CTRL_RSVD1(v)                 (((v) << 6) & 0x40)
-#define BP_USBPHY_CTRL_DEVPLUGIN_POLARITY       5
-#define BM_USBPHY_CTRL_DEVPLUGIN_POLARITY       0x20
-#define BF_USBPHY_CTRL_DEVPLUGIN_POLARITY(v)    (((v) << 5) & 0x20)
-#define BP_USBPHY_CTRL_ENDEVPLUGINDETECT        4
-#define BM_USBPHY_CTRL_ENDEVPLUGINDETECT        0x10
-#define BF_USBPHY_CTRL_ENDEVPLUGINDETECT(v)     (((v) << 4) & 0x10)
-#define BP_USBPHY_CTRL_HOSTDISCONDETECT_IRQ     3
-#define BM_USBPHY_CTRL_HOSTDISCONDETECT_IRQ     0x8
-#define BF_USBPHY_CTRL_HOSTDISCONDETECT_IRQ(v)  (((v) << 3) & 0x8)
-#define BP_USBPHY_CTRL_ENIRQHOSTDISCON          2
-#define BM_USBPHY_CTRL_ENIRQHOSTDISCON          0x4
-#define BF_USBPHY_CTRL_ENIRQHOSTDISCON(v)       (((v) << 2) & 0x4)
-#define BP_USBPHY_CTRL_ENHOSTDISCONDETECT       1
-#define BM_USBPHY_CTRL_ENHOSTDISCONDETECT       0x2
-#define BF_USBPHY_CTRL_ENHOSTDISCONDETECT(v)    (((v) << 1) & 0x2)
-#define BP_USBPHY_CTRL_RSVD0                    0
-#define BM_USBPHY_CTRL_RSVD0                    0x1
-#define BF_USBPHY_CTRL_RSVD0(v)                 (((v) << 0) & 0x1)
-
-/**
- * Register: HW_USBPHY_STATUS
- * Address: 0x40
- * SCT: no
-*/
-#define HW_USBPHY_STATUS                            (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x40))
-#define BP_USBPHY_STATUS_RSVD4                      11
-#define BM_USBPHY_STATUS_RSVD4                      0xfffff800
-#define BF_USBPHY_STATUS_RSVD4(v)                   (((v) << 11) & 0xfffff800)
-#define BP_USBPHY_STATUS_RESUME_STATUS              10
-#define BM_USBPHY_STATUS_RESUME_STATUS              0x400
-#define BF_USBPHY_STATUS_RESUME_STATUS(v)           (((v) << 10) & 0x400)
-#define BP_USBPHY_STATUS_RSVD3                      9
-#define BM_USBPHY_STATUS_RSVD3                      0x200
-#define BF_USBPHY_STATUS_RSVD3(v)                   (((v) << 9) & 0x200)
-#define BP_USBPHY_STATUS_OTGID_STATUS               8
-#define BM_USBPHY_STATUS_OTGID_STATUS               0x100
-#define BF_USBPHY_STATUS_OTGID_STATUS(v)            (((v) << 8) & 0x100)
-#define BP_USBPHY_STATUS_RSVD2                      7
-#define BM_USBPHY_STATUS_RSVD2                      0x80
-#define BF_USBPHY_STATUS_RSVD2(v)                   (((v) << 7) & 0x80)
-#define BP_USBPHY_STATUS_DEVPLUGIN_STATUS           6
-#define BM_USBPHY_STATUS_DEVPLUGIN_STATUS           0x40
-#define BF_USBPHY_STATUS_DEVPLUGIN_STATUS(v)        (((v) << 6) & 0x40)
-#define BP_USBPHY_STATUS_RSVD1                      4
-#define BM_USBPHY_STATUS_RSVD1                      0x30
-#define BF_USBPHY_STATUS_RSVD1(v)                   (((v) << 4) & 0x30)
-#define BP_USBPHY_STATUS_HOSTDISCONDETECT_STATUS    3
-#define BM_USBPHY_STATUS_HOSTDISCONDETECT_STATUS    0x8
-#define BF_USBPHY_STATUS_HOSTDISCONDETECT_STATUS(v) (((v) << 3) & 0x8)
-#define BP_USBPHY_STATUS_RSVD0                      0
-#define BM_USBPHY_STATUS_RSVD0                      0x7
-#define BF_USBPHY_STATUS_RSVD0(v)                   (((v) << 0) & 0x7)
-
-/**
- * Register: HW_USBPHY_DEBUG
- * Address: 0x50
- * SCT: yes
-*/
-#define HW_USBPHY_DEBUG                         (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x50 + 0x0))
-#define HW_USBPHY_DEBUG_SET                     (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x50 + 0x4))
-#define HW_USBPHY_DEBUG_CLR                     (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x50 + 0x8))
-#define HW_USBPHY_DEBUG_TOG                     (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x50 + 0xc))
-#define BP_USBPHY_DEBUG_RSVD3                   31
-#define BM_USBPHY_DEBUG_RSVD3                   0x80000000
-#define BF_USBPHY_DEBUG_RSVD3(v)                (((v) << 31) & 0x80000000)
-#define BP_USBPHY_DEBUG_CLKGATE                 30
-#define BM_USBPHY_DEBUG_CLKGATE                 0x40000000
-#define BF_USBPHY_DEBUG_CLKGATE(v)              (((v) << 30) & 0x40000000)
-#define BP_USBPHY_DEBUG_HOST_RESUME_DEBUG       29
-#define BM_USBPHY_DEBUG_HOST_RESUME_DEBUG       0x20000000
-#define BF_USBPHY_DEBUG_HOST_RESUME_DEBUG(v)    (((v) << 29) & 0x20000000)
-#define BP_USBPHY_DEBUG_SQUELCHRESETLENGTH      25
-#define BM_USBPHY_DEBUG_SQUELCHRESETLENGTH      0x1e000000
-#define BF_USBPHY_DEBUG_SQUELCHRESETLENGTH(v)   (((v) << 25) & 0x1e000000)
-#define BP_USBPHY_DEBUG_ENSQUELCHRESET          24
-#define BM_USBPHY_DEBUG_ENSQUELCHRESET          0x1000000
-#define BF_USBPHY_DEBUG_ENSQUELCHRESET(v)       (((v) << 24) & 0x1000000)
-#define BP_USBPHY_DEBUG_RSVD2                   21
-#define BM_USBPHY_DEBUG_RSVD2                   0xe00000
-#define BF_USBPHY_DEBUG_RSVD2(v)                (((v) << 21) & 0xe00000)
-#define BP_USBPHY_DEBUG_SQUELCHRESETCOUNT       16
-#define BM_USBPHY_DEBUG_SQUELCHRESETCOUNT       0x1f0000
-#define BF_USBPHY_DEBUG_SQUELCHRESETCOUNT(v)    (((v) << 16) & 0x1f0000)
-#define BP_USBPHY_DEBUG_RSVD1                   13
-#define BM_USBPHY_DEBUG_RSVD1                   0xe000
-#define BF_USBPHY_DEBUG_RSVD1(v)                (((v) << 13) & 0xe000)
-#define BP_USBPHY_DEBUG_ENTX2RXCOUNT            12
-#define BM_USBPHY_DEBUG_ENTX2RXCOUNT            0x1000
-#define BF_USBPHY_DEBUG_ENTX2RXCOUNT(v)         (((v) << 12) & 0x1000)
-#define BP_USBPHY_DEBUG_TX2RXCOUNT              8
-#define BM_USBPHY_DEBUG_TX2RXCOUNT              0xf00
-#define BF_USBPHY_DEBUG_TX2RXCOUNT(v)           (((v) << 8) & 0xf00)
-#define BP_USBPHY_DEBUG_RSVD0                   6
-#define BM_USBPHY_DEBUG_RSVD0                   0xc0
-#define BF_USBPHY_DEBUG_RSVD0(v)                (((v) << 6) & 0xc0)
-#define BP_USBPHY_DEBUG_ENHSTPULLDOWN           4
-#define BM_USBPHY_DEBUG_ENHSTPULLDOWN           0x30
-#define BF_USBPHY_DEBUG_ENHSTPULLDOWN(v)        (((v) << 4) & 0x30)
-#define BP_USBPHY_DEBUG_HSTPULLDOWN             2
-#define BM_USBPHY_DEBUG_HSTPULLDOWN             0xc
-#define BF_USBPHY_DEBUG_HSTPULLDOWN(v)          (((v) << 2) & 0xc)
-#define BP_USBPHY_DEBUG_DEBUG_INTERFACE_HOLD    1
-#define BM_USBPHY_DEBUG_DEBUG_INTERFACE_HOLD    0x2
-#define BF_USBPHY_DEBUG_DEBUG_INTERFACE_HOLD(v) (((v) << 1) & 0x2)
-#define BP_USBPHY_DEBUG_OTGIDPIOLOCK            0
-#define BM_USBPHY_DEBUG_OTGIDPIOLOCK            0x1
-#define BF_USBPHY_DEBUG_OTGIDPIOLOCK(v)         (((v) << 0) & 0x1)
-
-/**
- * Register: HW_USBPHY_DEBUG0_STATUS
- * Address: 0x60
- * SCT: no
-*/
-#define HW_USBPHY_DEBUG0_STATUS                             (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x60))
-#define BP_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT               26
-#define BM_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT               0xfc000000
-#define BF_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT(v)            (((v) << 26) & 0xfc000000)
-#define BP_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT     16
-#define BM_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT     0x3ff0000
-#define BF_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT(v)  (((v) << 16) & 0x3ff0000)
-#define BP_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT        0
-#define BM_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT        0xffff
-#define BF_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT(v)     (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_USBPHY_DEBUG1
- * Address: 0x70
- * SCT: yes
-*/
-#define HW_USBPHY_DEBUG1                (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x70 + 0x0))
-#define HW_USBPHY_DEBUG1_SET            (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x70 + 0x4))
-#define HW_USBPHY_DEBUG1_CLR            (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x70 + 0x8))
-#define HW_USBPHY_DEBUG1_TOG            (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x70 + 0xc))
-#define BP_USBPHY_DEBUG1_RSVD1          15
-#define BM_USBPHY_DEBUG1_RSVD1          0xffff8000
-#define BF_USBPHY_DEBUG1_RSVD1(v)       (((v) << 15) & 0xffff8000)
-#define BP_USBPHY_DEBUG1_ENTAILADJVD    13
-#define BM_USBPHY_DEBUG1_ENTAILADJVD    0x6000
-#define BF_USBPHY_DEBUG1_ENTAILADJVD(v) (((v) << 13) & 0x6000)
-#define BP_USBPHY_DEBUG1_ENTX2TX        12
-#define BM_USBPHY_DEBUG1_ENTX2TX        0x1000
-#define BF_USBPHY_DEBUG1_ENTX2TX(v)     (((v) << 12) & 0x1000)
-#define BP_USBPHY_DEBUG1_RSVD0          4
-#define BM_USBPHY_DEBUG1_RSVD0          0xff0
-#define BF_USBPHY_DEBUG1_RSVD0(v)       (((v) << 4) & 0xff0)
-#define BP_USBPHY_DEBUG1_DBG_ADDRESS    0
-#define BM_USBPHY_DEBUG1_DBG_ADDRESS    0xf
-#define BF_USBPHY_DEBUG1_DBG_ADDRESS(v) (((v) << 0) & 0xf)
-
-/**
- * Register: HW_USBPHY_VERSION
- * Address: 0x80
- * SCT: no
-*/
-#define HW_USBPHY_VERSION           (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x80))
-#define BP_USBPHY_VERSION_MAJOR     24
-#define BM_USBPHY_VERSION_MAJOR     0xff000000
-#define BF_USBPHY_VERSION_MAJOR(v)  (((v) << 24) & 0xff000000)
-#define BP_USBPHY_VERSION_MINOR     16
-#define BM_USBPHY_VERSION_MINOR     0xff0000
-#define BF_USBPHY_VERSION_MINOR(v)  (((v) << 16) & 0xff0000)
-#define BP_USBPHY_VERSION_STEP      0
-#define BM_USBPHY_VERSION_STEP      0xffff
-#define BF_USBPHY_VERSION_STEP(v)   (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_USBPHY_IP
- * Address: 0x90
- * SCT: yes
-*/
-#define HW_USBPHY_IP                    (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x90 + 0x0))
-#define HW_USBPHY_IP_SET                (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x90 + 0x4))
-#define HW_USBPHY_IP_CLR                (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x90 + 0x8))
-#define HW_USBPHY_IP_TOG                (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x90 + 0xc))
-#define BP_USBPHY_IP_RSVD1              25
-#define BM_USBPHY_IP_RSVD1              0xfe000000
-#define BF_USBPHY_IP_RSVD1(v)           (((v) << 25) & 0xfe000000)
-#define BP_USBPHY_IP_DIV_SEL            23
-#define BM_USBPHY_IP_DIV_SEL            0x1800000
-#define BV_USBPHY_IP_DIV_SEL__DEFAULT   0x0
-#define BV_USBPHY_IP_DIV_SEL__LOWER     0x1
-#define BV_USBPHY_IP_DIV_SEL__LOWEST    0x2
-#define BV_USBPHY_IP_DIV_SEL__UNDEFINED 0x3
-#define BF_USBPHY_IP_DIV_SEL(v)         (((v) << 23) & 0x1800000)
-#define BF_USBPHY_IP_DIV_SEL_V(v)       ((BV_USBPHY_IP_DIV_SEL__##v << 23) & 0x1800000)
-#define BP_USBPHY_IP_LFR_SEL            21
-#define BM_USBPHY_IP_LFR_SEL            0x600000
-#define BV_USBPHY_IP_LFR_SEL__DEFAULT   0x0
-#define BV_USBPHY_IP_LFR_SEL__TIMES_2   0x1
-#define BV_USBPHY_IP_LFR_SEL__TIMES_05  0x2
-#define BV_USBPHY_IP_LFR_SEL__UNDEFINED 0x3
-#define BF_USBPHY_IP_LFR_SEL(v)         (((v) << 21) & 0x600000)
-#define BF_USBPHY_IP_LFR_SEL_V(v)       ((BV_USBPHY_IP_LFR_SEL__##v << 21) & 0x600000)
-#define BP_USBPHY_IP_CP_SEL             19
-#define BM_USBPHY_IP_CP_SEL             0x180000
-#define BV_USBPHY_IP_CP_SEL__DEFAULT    0x0
-#define BV_USBPHY_IP_CP_SEL__TIMES_2    0x1
-#define BV_USBPHY_IP_CP_SEL__TIMES_05   0x2
-#define BV_USBPHY_IP_CP_SEL__UNDEFINED  0x3
-#define BF_USBPHY_IP_CP_SEL(v)          (((v) << 19) & 0x180000)
-#define BF_USBPHY_IP_CP_SEL_V(v)        ((BV_USBPHY_IP_CP_SEL__##v << 19) & 0x180000)
-#define BP_USBPHY_IP_TSTI_TX_DP         18
-#define BM_USBPHY_IP_TSTI_TX_DP         0x40000
-#define BF_USBPHY_IP_TSTI_TX_DP(v)      (((v) << 18) & 0x40000)
-#define BP_USBPHY_IP_TSTI_TX_DM         17
-#define BM_USBPHY_IP_TSTI_TX_DM         0x20000
-#define BF_USBPHY_IP_TSTI_TX_DM(v)      (((v) << 17) & 0x20000)
-#define BP_USBPHY_IP_ANALOG_TESTMODE    16
-#define BM_USBPHY_IP_ANALOG_TESTMODE    0x10000
-#define BF_USBPHY_IP_ANALOG_TESTMODE(v) (((v) << 16) & 0x10000)
-#define BP_USBPHY_IP_RSVD0              3
-#define BM_USBPHY_IP_RSVD0              0xfff8
-#define BF_USBPHY_IP_RSVD0(v)           (((v) << 3) & 0xfff8)
-#define BP_USBPHY_IP_EN_USB_CLKS        2
-#define BM_USBPHY_IP_EN_USB_CLKS        0x4
-#define BF_USBPHY_IP_EN_USB_CLKS(v)     (((v) << 2) & 0x4)
-#define BP_USBPHY_IP_PLL_LOCKED         1
-#define BM_USBPHY_IP_PLL_LOCKED         0x2
-#define BF_USBPHY_IP_PLL_LOCKED(v)      (((v) << 1) & 0x2)
-#define BP_USBPHY_IP_PLL_POWER          0
-#define BM_USBPHY_IP_PLL_POWER          0x1
-#define BF_USBPHY_IP_PLL_POWER(v)       (((v) << 0) & 0x1)
-
-#endif /* __HEADERGEN__IMX233__USBPHY__H__ */
diff --git a/firmware/target/arm/imx233/regs/imx233/rtc.h b/firmware/target/arm/imx233/regs/imx233/rtc.h
new file mode 100644
index 0000000000..bd41bcbc39
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/imx233/rtc.h
@@ -0,0 +1,600 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * imx233 version: 2.4.0
+ * imx233 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_IMX233_RTC_H__
+#define __HEADERGEN_IMX233_RTC_H__
+
+#define HW_RTC_CTRL                             HW(RTC_CTRL)
+#define HWA_RTC_CTRL                            (0x8005c000 + 0x0)
+#define HWT_RTC_CTRL                            HWIO_32_RW
+#define HWN_RTC_CTRL                            RTC_CTRL
+#define HWI_RTC_CTRL                            
+#define HW_RTC_CTRL_SET                         HW(RTC_CTRL_SET)
+#define HWA_RTC_CTRL_SET                        (HWA_RTC_CTRL + 0x4)
+#define HWT_RTC_CTRL_SET                        HWIO_32_WO
+#define HWN_RTC_CTRL_SET                        RTC_CTRL
+#define HWI_RTC_CTRL_SET                        
+#define HW_RTC_CTRL_CLR                         HW(RTC_CTRL_CLR)
+#define HWA_RTC_CTRL_CLR                        (HWA_RTC_CTRL + 0x8)
+#define HWT_RTC_CTRL_CLR                        HWIO_32_WO
+#define HWN_RTC_CTRL_CLR                        RTC_CTRL
+#define HWI_RTC_CTRL_CLR                        
+#define HW_RTC_CTRL_TOG                         HW(RTC_CTRL_TOG)
+#define HWA_RTC_CTRL_TOG                        (HWA_RTC_CTRL + 0xc)
+#define HWT_RTC_CTRL_TOG                        HWIO_32_WO
+#define HWN_RTC_CTRL_TOG                        RTC_CTRL
+#define HWI_RTC_CTRL_TOG                        
+#define BP_RTC_CTRL_SFTRST                      31
+#define BM_RTC_CTRL_SFTRST                      0x80000000
+#define BF_RTC_CTRL_SFTRST(v)                   (((v) & 0x1) << 31)
+#define BFM_RTC_CTRL_SFTRST(v)                  BM_RTC_CTRL_SFTRST
+#define BF_RTC_CTRL_SFTRST_V(e)                 BF_RTC_CTRL_SFTRST(BV_RTC_CTRL_SFTRST__##e)
+#define BFM_RTC_CTRL_SFTRST_V(v)                BM_RTC_CTRL_SFTRST
+#define BP_RTC_CTRL_CLKGATE                     30
+#define BM_RTC_CTRL_CLKGATE                     0x40000000
+#define BF_RTC_CTRL_CLKGATE(v)                  (((v) & 0x1) << 30)
+#define BFM_RTC_CTRL_CLKGATE(v)                 BM_RTC_CTRL_CLKGATE
+#define BF_RTC_CTRL_CLKGATE_V(e)                BF_RTC_CTRL_CLKGATE(BV_RTC_CTRL_CLKGATE__##e)
+#define BFM_RTC_CTRL_CLKGATE_V(v)               BM_RTC_CTRL_CLKGATE
+#define BP_RTC_CTRL_RSVD0                       7
+#define BM_RTC_CTRL_RSVD0                       0x3fffff80
+#define BF_RTC_CTRL_RSVD0(v)                    (((v) & 0x7fffff) << 7)
+#define BFM_RTC_CTRL_RSVD0(v)                   BM_RTC_CTRL_RSVD0
+#define BF_RTC_CTRL_RSVD0_V(e)                  BF_RTC_CTRL_RSVD0(BV_RTC_CTRL_RSVD0__##e)
+#define BFM_RTC_CTRL_RSVD0_V(v)                 BM_RTC_CTRL_RSVD0
+#define BP_RTC_CTRL_SUPPRESS_COPY2ANALOG        6
+#define BM_RTC_CTRL_SUPPRESS_COPY2ANALOG        0x40
+#define BF_RTC_CTRL_SUPPRESS_COPY2ANALOG(v)     (((v) & 0x1) << 6)
+#define BFM_RTC_CTRL_SUPPRESS_COPY2ANALOG(v)    BM_RTC_CTRL_SUPPRESS_COPY2ANALOG
+#define BF_RTC_CTRL_SUPPRESS_COPY2ANALOG_V(e)   BF_RTC_CTRL_SUPPRESS_COPY2ANALOG(BV_RTC_CTRL_SUPPRESS_COPY2ANALOG__##e)
+#define BFM_RTC_CTRL_SUPPRESS_COPY2ANALOG_V(v)  BM_RTC_CTRL_SUPPRESS_COPY2ANALOG
+#define BP_RTC_CTRL_FORCE_UPDATE                5
+#define BM_RTC_CTRL_FORCE_UPDATE                0x20
+#define BF_RTC_CTRL_FORCE_UPDATE(v)             (((v) & 0x1) << 5)
+#define BFM_RTC_CTRL_FORCE_UPDATE(v)            BM_RTC_CTRL_FORCE_UPDATE
+#define BF_RTC_CTRL_FORCE_UPDATE_V(e)           BF_RTC_CTRL_FORCE_UPDATE(BV_RTC_CTRL_FORCE_UPDATE__##e)
+#define BFM_RTC_CTRL_FORCE_UPDATE_V(v)          BM_RTC_CTRL_FORCE_UPDATE
+#define BP_RTC_CTRL_WATCHDOGEN                  4
+#define BM_RTC_CTRL_WATCHDOGEN                  0x10
+#define BF_RTC_CTRL_WATCHDOGEN(v)               (((v) & 0x1) << 4)
+#define BFM_RTC_CTRL_WATCHDOGEN(v)              BM_RTC_CTRL_WATCHDOGEN
+#define BF_RTC_CTRL_WATCHDOGEN_V(e)             BF_RTC_CTRL_WATCHDOGEN(BV_RTC_CTRL_WATCHDOGEN__##e)
+#define BFM_RTC_CTRL_WATCHDOGEN_V(v)            BM_RTC_CTRL_WATCHDOGEN
+#define BP_RTC_CTRL_ONEMSEC_IRQ                 3
+#define BM_RTC_CTRL_ONEMSEC_IRQ                 0x8
+#define BF_RTC_CTRL_ONEMSEC_IRQ(v)              (((v) & 0x1) << 3)
+#define BFM_RTC_CTRL_ONEMSEC_IRQ(v)             BM_RTC_CTRL_ONEMSEC_IRQ
+#define BF_RTC_CTRL_ONEMSEC_IRQ_V(e)            BF_RTC_CTRL_ONEMSEC_IRQ(BV_RTC_CTRL_ONEMSEC_IRQ__##e)
+#define BFM_RTC_CTRL_ONEMSEC_IRQ_V(v)           BM_RTC_CTRL_ONEMSEC_IRQ
+#define BP_RTC_CTRL_ALARM_IRQ                   2
+#define BM_RTC_CTRL_ALARM_IRQ                   0x4
+#define BF_RTC_CTRL_ALARM_IRQ(v)                (((v) & 0x1) << 2)
+#define BFM_RTC_CTRL_ALARM_IRQ(v)               BM_RTC_CTRL_ALARM_IRQ
+#define BF_RTC_CTRL_ALARM_IRQ_V(e)              BF_RTC_CTRL_ALARM_IRQ(BV_RTC_CTRL_ALARM_IRQ__##e)
+#define BFM_RTC_CTRL_ALARM_IRQ_V(v)             BM_RTC_CTRL_ALARM_IRQ
+#define BP_RTC_CTRL_ONEMSEC_IRQ_EN              1
+#define BM_RTC_CTRL_ONEMSEC_IRQ_EN              0x2
+#define BF_RTC_CTRL_ONEMSEC_IRQ_EN(v)           (((v) & 0x1) << 1)
+#define BFM_RTC_CTRL_ONEMSEC_IRQ_EN(v)          BM_RTC_CTRL_ONEMSEC_IRQ_EN
+#define BF_RTC_CTRL_ONEMSEC_IRQ_EN_V(e)         BF_RTC_CTRL_ONEMSEC_IRQ_EN(BV_RTC_CTRL_ONEMSEC_IRQ_EN__##e)
+#define BFM_RTC_CTRL_ONEMSEC_IRQ_EN_V(v)        BM_RTC_CTRL_ONEMSEC_IRQ_EN
+#define BP_RTC_CTRL_ALARM_IRQ_EN                0
+#define BM_RTC_CTRL_ALARM_IRQ_EN                0x1
+#define BF_RTC_CTRL_ALARM_IRQ_EN(v)             (((v) & 0x1) << 0)
+#define BFM_RTC_CTRL_ALARM_IRQ_EN(v)            BM_RTC_CTRL_ALARM_IRQ_EN
+#define BF_RTC_CTRL_ALARM_IRQ_EN_V(e)           BF_RTC_CTRL_ALARM_IRQ_EN(BV_RTC_CTRL_ALARM_IRQ_EN__##e)
+#define BFM_RTC_CTRL_ALARM_IRQ_EN_V(v)          BM_RTC_CTRL_ALARM_IRQ_EN
+
+#define HW_RTC_STAT                         HW(RTC_STAT)
+#define HWA_RTC_STAT                        (0x8005c000 + 0x10)
+#define HWT_RTC_STAT                        HWIO_32_RW
+#define HWN_RTC_STAT                        RTC_STAT
+#define HWI_RTC_STAT                        
+#define HW_RTC_STAT_SET                     HW(RTC_STAT_SET)
+#define HWA_RTC_STAT_SET                    (HWA_RTC_STAT + 0x4)
+#define HWT_RTC_STAT_SET                    HWIO_32_WO
+#define HWN_RTC_STAT_SET                    RTC_STAT
+#define HWI_RTC_STAT_SET                    
+#define HW_RTC_STAT_CLR                     HW(RTC_STAT_CLR)
+#define HWA_RTC_STAT_CLR                    (HWA_RTC_STAT + 0x8)
+#define HWT_RTC_STAT_CLR                    HWIO_32_WO
+#define HWN_RTC_STAT_CLR                    RTC_STAT
+#define HWI_RTC_STAT_CLR                    
+#define HW_RTC_STAT_TOG                     HW(RTC_STAT_TOG)
+#define HWA_RTC_STAT_TOG                    (HWA_RTC_STAT + 0xc)
+#define HWT_RTC_STAT_TOG                    HWIO_32_WO
+#define HWN_RTC_STAT_TOG                    RTC_STAT
+#define HWI_RTC_STAT_TOG                    
+#define BP_RTC_STAT_RTC_PRESENT             31
+#define BM_RTC_STAT_RTC_PRESENT             0x80000000
+#define BF_RTC_STAT_RTC_PRESENT(v)          (((v) & 0x1) << 31)
+#define BFM_RTC_STAT_RTC_PRESENT(v)         BM_RTC_STAT_RTC_PRESENT
+#define BF_RTC_STAT_RTC_PRESENT_V(e)        BF_RTC_STAT_RTC_PRESENT(BV_RTC_STAT_RTC_PRESENT__##e)
+#define BFM_RTC_STAT_RTC_PRESENT_V(v)       BM_RTC_STAT_RTC_PRESENT
+#define BP_RTC_STAT_ALARM_PRESENT           30
+#define BM_RTC_STAT_ALARM_PRESENT           0x40000000
+#define BF_RTC_STAT_ALARM_PRESENT(v)        (((v) & 0x1) << 30)
+#define BFM_RTC_STAT_ALARM_PRESENT(v)       BM_RTC_STAT_ALARM_PRESENT
+#define BF_RTC_STAT_ALARM_PRESENT_V(e)      BF_RTC_STAT_ALARM_PRESENT(BV_RTC_STAT_ALARM_PRESENT__##e)
+#define BFM_RTC_STAT_ALARM_PRESENT_V(v)     BM_RTC_STAT_ALARM_PRESENT
+#define BP_RTC_STAT_WATCHDOG_PRESENT        29
+#define BM_RTC_STAT_WATCHDOG_PRESENT        0x20000000
+#define BF_RTC_STAT_WATCHDOG_PRESENT(v)     (((v) & 0x1) << 29)
+#define BFM_RTC_STAT_WATCHDOG_PRESENT(v)    BM_RTC_STAT_WATCHDOG_PRESENT
+#define BF_RTC_STAT_WATCHDOG_PRESENT_V(e)   BF_RTC_STAT_WATCHDOG_PRESENT(BV_RTC_STAT_WATCHDOG_PRESENT__##e)
+#define BFM_RTC_STAT_WATCHDOG_PRESENT_V(v)  BM_RTC_STAT_WATCHDOG_PRESENT
+#define BP_RTC_STAT_XTAL32000_PRESENT       28
+#define BM_RTC_STAT_XTAL32000_PRESENT       0x10000000
+#define BF_RTC_STAT_XTAL32000_PRESENT(v)    (((v) & 0x1) << 28)
+#define BFM_RTC_STAT_XTAL32000_PRESENT(v)   BM_RTC_STAT_XTAL32000_PRESENT
+#define BF_RTC_STAT_XTAL32000_PRESENT_V(e)  BF_RTC_STAT_XTAL32000_PRESENT(BV_RTC_STAT_XTAL32000_PRESENT__##e)
+#define BFM_RTC_STAT_XTAL32000_PRESENT_V(v) BM_RTC_STAT_XTAL32000_PRESENT
+#define BP_RTC_STAT_XTAL32768_PRESENT       27
+#define BM_RTC_STAT_XTAL32768_PRESENT       0x8000000
+#define BF_RTC_STAT_XTAL32768_PRESENT(v)    (((v) & 0x1) << 27)
+#define BFM_RTC_STAT_XTAL32768_PRESENT(v)   BM_RTC_STAT_XTAL32768_PRESENT
+#define BF_RTC_STAT_XTAL32768_PRESENT_V(e)  BF_RTC_STAT_XTAL32768_PRESENT(BV_RTC_STAT_XTAL32768_PRESENT__##e)
+#define BFM_RTC_STAT_XTAL32768_PRESENT_V(v) BM_RTC_STAT_XTAL32768_PRESENT
+#define BP_RTC_STAT_RSVD1                   24
+#define BM_RTC_STAT_RSVD1                   0x7000000
+#define BF_RTC_STAT_RSVD1(v)                (((v) & 0x7) << 24)
+#define BFM_RTC_STAT_RSVD1(v)               BM_RTC_STAT_RSVD1
+#define BF_RTC_STAT_RSVD1_V(e)              BF_RTC_STAT_RSVD1(BV_RTC_STAT_RSVD1__##e)
+#define BFM_RTC_STAT_RSVD1_V(v)             BM_RTC_STAT_RSVD1
+#define BP_RTC_STAT_STALE_REGS              16
+#define BM_RTC_STAT_STALE_REGS              0xff0000
+#define BF_RTC_STAT_STALE_REGS(v)           (((v) & 0xff) << 16)
+#define BFM_RTC_STAT_STALE_REGS(v)          BM_RTC_STAT_STALE_REGS
+#define BF_RTC_STAT_STALE_REGS_V(e)         BF_RTC_STAT_STALE_REGS(BV_RTC_STAT_STALE_REGS__##e)
+#define BFM_RTC_STAT_STALE_REGS_V(v)        BM_RTC_STAT_STALE_REGS
+#define BP_RTC_STAT_NEW_REGS                8
+#define BM_RTC_STAT_NEW_REGS                0xff00
+#define BF_RTC_STAT_NEW_REGS(v)             (((v) & 0xff) << 8)
+#define BFM_RTC_STAT_NEW_REGS(v)            BM_RTC_STAT_NEW_REGS
+#define BF_RTC_STAT_NEW_REGS_V(e)           BF_RTC_STAT_NEW_REGS(BV_RTC_STAT_NEW_REGS__##e)
+#define BFM_RTC_STAT_NEW_REGS_V(v)          BM_RTC_STAT_NEW_REGS
+#define BP_RTC_STAT_RSVD0                   0
+#define BM_RTC_STAT_RSVD0                   0xff
+#define BF_RTC_STAT_RSVD0(v)                (((v) & 0xff) << 0)
+#define BFM_RTC_STAT_RSVD0(v)               BM_RTC_STAT_RSVD0
+#define BF_RTC_STAT_RSVD0_V(e)              BF_RTC_STAT_RSVD0(BV_RTC_STAT_RSVD0__##e)
+#define BFM_RTC_STAT_RSVD0_V(v)             BM_RTC_STAT_RSVD0
+
+#define HW_RTC_MILLISECONDS             HW(RTC_MILLISECONDS)
+#define HWA_RTC_MILLISECONDS            (0x8005c000 + 0x20)
+#define HWT_RTC_MILLISECONDS            HWIO_32_RW
+#define HWN_RTC_MILLISECONDS            RTC_MILLISECONDS
+#define HWI_RTC_MILLISECONDS            
+#define HW_RTC_MILLISECONDS_SET         HW(RTC_MILLISECONDS_SET)
+#define HWA_RTC_MILLISECONDS_SET        (HWA_RTC_MILLISECONDS + 0x4)
+#define HWT_RTC_MILLISECONDS_SET        HWIO_32_WO
+#define HWN_RTC_MILLISECONDS_SET        RTC_MILLISECONDS
+#define HWI_RTC_MILLISECONDS_SET        
+#define HW_RTC_MILLISECONDS_CLR         HW(RTC_MILLISECONDS_CLR)
+#define HWA_RTC_MILLISECONDS_CLR        (HWA_RTC_MILLISECONDS + 0x8)
+#define HWT_RTC_MILLISECONDS_CLR        HWIO_32_WO
+#define HWN_RTC_MILLISECONDS_CLR        RTC_MILLISECONDS
+#define HWI_RTC_MILLISECONDS_CLR        
+#define HW_RTC_MILLISECONDS_TOG         HW(RTC_MILLISECONDS_TOG)
+#define HWA_RTC_MILLISECONDS_TOG        (HWA_RTC_MILLISECONDS + 0xc)
+#define HWT_RTC_MILLISECONDS_TOG        HWIO_32_WO
+#define HWN_RTC_MILLISECONDS_TOG        RTC_MILLISECONDS
+#define HWI_RTC_MILLISECONDS_TOG        
+#define BP_RTC_MILLISECONDS_COUNT       0
+#define BM_RTC_MILLISECONDS_COUNT       0xffffffff
+#define BF_RTC_MILLISECONDS_COUNT(v)    (((v) & 0xffffffff) << 0)
+#define BFM_RTC_MILLISECONDS_COUNT(v)   BM_RTC_MILLISECONDS_COUNT
+#define BF_RTC_MILLISECONDS_COUNT_V(e)  BF_RTC_MILLISECONDS_COUNT(BV_RTC_MILLISECONDS_COUNT__##e)
+#define BFM_RTC_MILLISECONDS_COUNT_V(v) BM_RTC_MILLISECONDS_COUNT
+
+#define HW_RTC_SECONDS              HW(RTC_SECONDS)
+#define HWA_RTC_SECONDS             (0x8005c000 + 0x30)
+#define HWT_RTC_SECONDS             HWIO_32_RW
+#define HWN_RTC_SECONDS             RTC_SECONDS
+#define HWI_RTC_SECONDS             
+#define HW_RTC_SECONDS_SET          HW(RTC_SECONDS_SET)
+#define HWA_RTC_SECONDS_SET         (HWA_RTC_SECONDS + 0x4)
+#define HWT_RTC_SECONDS_SET         HWIO_32_WO
+#define HWN_RTC_SECONDS_SET         RTC_SECONDS
+#define HWI_RTC_SECONDS_SET         
+#define HW_RTC_SECONDS_CLR          HW(RTC_SECONDS_CLR)
+#define HWA_RTC_SECONDS_CLR         (HWA_RTC_SECONDS + 0x8)
+#define HWT_RTC_SECONDS_CLR         HWIO_32_WO
+#define HWN_RTC_SECONDS_CLR         RTC_SECONDS
+#define HWI_RTC_SECONDS_CLR         
+#define HW_RTC_SECONDS_TOG          HW(RTC_SECONDS_TOG)
+#define HWA_RTC_SECONDS_TOG         (HWA_RTC_SECONDS + 0xc)
+#define HWT_RTC_SECONDS_TOG         HWIO_32_WO
+#define HWN_RTC_SECONDS_TOG         RTC_SECONDS
+#define HWI_RTC_SECONDS_TOG         
+#define BP_RTC_SECONDS_COUNT        0
+#define BM_RTC_SECONDS_COUNT        0xffffffff
+#define BF_RTC_SECONDS_COUNT(v)     (((v) & 0xffffffff) << 0)
+#define BFM_RTC_SECONDS_COUNT(v)    BM_RTC_SECONDS_COUNT
+#define BF_RTC_SECONDS_COUNT_V(e)   BF_RTC_SECONDS_COUNT(BV_RTC_SECONDS_COUNT__##e)
+#define BFM_RTC_SECONDS_COUNT_V(v)  BM_RTC_SECONDS_COUNT
+
+#define HW_RTC_ALARM                HW(RTC_ALARM)
+#define HWA_RTC_ALARM               (0x8005c000 + 0x40)
+#define HWT_RTC_ALARM               HWIO_32_RW
+#define HWN_RTC_ALARM               RTC_ALARM
+#define HWI_RTC_ALARM               
+#define HW_RTC_ALARM_SET            HW(RTC_ALARM_SET)
+#define HWA_RTC_ALARM_SET           (HWA_RTC_ALARM + 0x4)
+#define HWT_RTC_ALARM_SET           HWIO_32_WO
+#define HWN_RTC_ALARM_SET           RTC_ALARM
+#define HWI_RTC_ALARM_SET           
+#define HW_RTC_ALARM_CLR            HW(RTC_ALARM_CLR)
+#define HWA_RTC_ALARM_CLR           (HWA_RTC_ALARM + 0x8)
+#define HWT_RTC_ALARM_CLR           HWIO_32_WO
+#define HWN_RTC_ALARM_CLR           RTC_ALARM
+#define HWI_RTC_ALARM_CLR           
+#define HW_RTC_ALARM_TOG            HW(RTC_ALARM_TOG)
+#define HWA_RTC_ALARM_TOG           (HWA_RTC_ALARM + 0xc)
+#define HWT_RTC_ALARM_TOG           HWIO_32_WO
+#define HWN_RTC_ALARM_TOG           RTC_ALARM
+#define HWI_RTC_ALARM_TOG           
+#define BP_RTC_ALARM_VALUE          0
+#define BM_RTC_ALARM_VALUE          0xffffffff
+#define BF_RTC_ALARM_VALUE(v)       (((v) & 0xffffffff) << 0)
+#define BFM_RTC_ALARM_VALUE(v)      BM_RTC_ALARM_VALUE
+#define BF_RTC_ALARM_VALUE_V(e)     BF_RTC_ALARM_VALUE(BV_RTC_ALARM_VALUE__##e)
+#define BFM_RTC_ALARM_VALUE_V(v)    BM_RTC_ALARM_VALUE
+
+#define HW_RTC_WATCHDOG             HW(RTC_WATCHDOG)
+#define HWA_RTC_WATCHDOG            (0x8005c000 + 0x50)
+#define HWT_RTC_WATCHDOG            HWIO_32_RW
+#define HWN_RTC_WATCHDOG            RTC_WATCHDOG
+#define HWI_RTC_WATCHDOG            
+#define HW_RTC_WATCHDOG_SET         HW(RTC_WATCHDOG_SET)
+#define HWA_RTC_WATCHDOG_SET        (HWA_RTC_WATCHDOG + 0x4)
+#define HWT_RTC_WATCHDOG_SET        HWIO_32_WO
+#define HWN_RTC_WATCHDOG_SET        RTC_WATCHDOG
+#define HWI_RTC_WATCHDOG_SET        
+#define HW_RTC_WATCHDOG_CLR         HW(RTC_WATCHDOG_CLR)
+#define HWA_RTC_WATCHDOG_CLR        (HWA_RTC_WATCHDOG + 0x8)
+#define HWT_RTC_WATCHDOG_CLR        HWIO_32_WO
+#define HWN_RTC_WATCHDOG_CLR        RTC_WATCHDOG
+#define HWI_RTC_WATCHDOG_CLR        
+#define HW_RTC_WATCHDOG_TOG         HW(RTC_WATCHDOG_TOG)
+#define HWA_RTC_WATCHDOG_TOG        (HWA_RTC_WATCHDOG + 0xc)
+#define HWT_RTC_WATCHDOG_TOG        HWIO_32_WO
+#define HWN_RTC_WATCHDOG_TOG        RTC_WATCHDOG
+#define HWI_RTC_WATCHDOG_TOG        
+#define BP_RTC_WATCHDOG_COUNT       0
+#define BM_RTC_WATCHDOG_COUNT       0xffffffff
+#define BF_RTC_WATCHDOG_COUNT(v)    (((v) & 0xffffffff) << 0)
+#define BFM_RTC_WATCHDOG_COUNT(v)   BM_RTC_WATCHDOG_COUNT
+#define BF_RTC_WATCHDOG_COUNT_V(e)  BF_RTC_WATCHDOG_COUNT(BV_RTC_WATCHDOG_COUNT__##e)
+#define BFM_RTC_WATCHDOG_COUNT_V(v) BM_RTC_WATCHDOG_COUNT
+
+#define HW_RTC_PERSISTENT0                          HW(RTC_PERSISTENT0)
+#define HWA_RTC_PERSISTENT0                         (0x8005c000 + 0x60)
+#define HWT_RTC_PERSISTENT0                         HWIO_32_RW
+#define HWN_RTC_PERSISTENT0                         RTC_PERSISTENT0
+#define HWI_RTC_PERSISTENT0                         
+#define HW_RTC_PERSISTENT0_SET                      HW(RTC_PERSISTENT0_SET)
+#define HWA_RTC_PERSISTENT0_SET                     (HWA_RTC_PERSISTENT0 + 0x4)
+#define HWT_RTC_PERSISTENT0_SET                     HWIO_32_WO
+#define HWN_RTC_PERSISTENT0_SET                     RTC_PERSISTENT0
+#define HWI_RTC_PERSISTENT0_SET                     
+#define HW_RTC_PERSISTENT0_CLR                      HW(RTC_PERSISTENT0_CLR)
+#define HWA_RTC_PERSISTENT0_CLR                     (HWA_RTC_PERSISTENT0 + 0x8)
+#define HWT_RTC_PERSISTENT0_CLR                     HWIO_32_WO
+#define HWN_RTC_PERSISTENT0_CLR                     RTC_PERSISTENT0
+#define HWI_RTC_PERSISTENT0_CLR                     
+#define HW_RTC_PERSISTENT0_TOG                      HW(RTC_PERSISTENT0_TOG)
+#define HWA_RTC_PERSISTENT0_TOG                     (HWA_RTC_PERSISTENT0 + 0xc)
+#define HWT_RTC_PERSISTENT0_TOG                     HWIO_32_WO
+#define HWN_RTC_PERSISTENT0_TOG                     RTC_PERSISTENT0
+#define HWI_RTC_PERSISTENT0_TOG                     
+#define BP_RTC_PERSISTENT0_SPARE_ANALOG             18
+#define BM_RTC_PERSISTENT0_SPARE_ANALOG             0xfffc0000
+#define BF_RTC_PERSISTENT0_SPARE_ANALOG(v)          (((v) & 0x3fff) << 18)
+#define BFM_RTC_PERSISTENT0_SPARE_ANALOG(v)         BM_RTC_PERSISTENT0_SPARE_ANALOG
+#define BF_RTC_PERSISTENT0_SPARE_ANALOG_V(e)        BF_RTC_PERSISTENT0_SPARE_ANALOG(BV_RTC_PERSISTENT0_SPARE_ANALOG__##e)
+#define BFM_RTC_PERSISTENT0_SPARE_ANALOG_V(v)       BM_RTC_PERSISTENT0_SPARE_ANALOG
+#define BP_RTC_PERSISTENT0_AUTO_RESTART             17
+#define BM_RTC_PERSISTENT0_AUTO_RESTART             0x20000
+#define BF_RTC_PERSISTENT0_AUTO_RESTART(v)          (((v) & 0x1) << 17)
+#define BFM_RTC_PERSISTENT0_AUTO_RESTART(v)         BM_RTC_PERSISTENT0_AUTO_RESTART
+#define BF_RTC_PERSISTENT0_AUTO_RESTART_V(e)        BF_RTC_PERSISTENT0_AUTO_RESTART(BV_RTC_PERSISTENT0_AUTO_RESTART__##e)
+#define BFM_RTC_PERSISTENT0_AUTO_RESTART_V(v)       BM_RTC_PERSISTENT0_AUTO_RESTART
+#define BP_RTC_PERSISTENT0_DISABLE_PSWITCH          16
+#define BM_RTC_PERSISTENT0_DISABLE_PSWITCH          0x10000
+#define BF_RTC_PERSISTENT0_DISABLE_PSWITCH(v)       (((v) & 0x1) << 16)
+#define BFM_RTC_PERSISTENT0_DISABLE_PSWITCH(v)      BM_RTC_PERSISTENT0_DISABLE_PSWITCH
+#define BF_RTC_PERSISTENT0_DISABLE_PSWITCH_V(e)     BF_RTC_PERSISTENT0_DISABLE_PSWITCH(BV_RTC_PERSISTENT0_DISABLE_PSWITCH__##e)
+#define BFM_RTC_PERSISTENT0_DISABLE_PSWITCH_V(v)    BM_RTC_PERSISTENT0_DISABLE_PSWITCH
+#define BP_RTC_PERSISTENT0_LOWERBIAS                14
+#define BM_RTC_PERSISTENT0_LOWERBIAS                0xc000
+#define BF_RTC_PERSISTENT0_LOWERBIAS(v)             (((v) & 0x3) << 14)
+#define BFM_RTC_PERSISTENT0_LOWERBIAS(v)            BM_RTC_PERSISTENT0_LOWERBIAS
+#define BF_RTC_PERSISTENT0_LOWERBIAS_V(e)           BF_RTC_PERSISTENT0_LOWERBIAS(BV_RTC_PERSISTENT0_LOWERBIAS__##e)
+#define BFM_RTC_PERSISTENT0_LOWERBIAS_V(v)          BM_RTC_PERSISTENT0_LOWERBIAS
+#define BP_RTC_PERSISTENT0_DISABLE_XTALOK           13
+#define BM_RTC_PERSISTENT0_DISABLE_XTALOK           0x2000
+#define BF_RTC_PERSISTENT0_DISABLE_XTALOK(v)        (((v) & 0x1) << 13)
+#define BFM_RTC_PERSISTENT0_DISABLE_XTALOK(v)       BM_RTC_PERSISTENT0_DISABLE_XTALOK
+#define BF_RTC_PERSISTENT0_DISABLE_XTALOK_V(e)      BF_RTC_PERSISTENT0_DISABLE_XTALOK(BV_RTC_PERSISTENT0_DISABLE_XTALOK__##e)
+#define BFM_RTC_PERSISTENT0_DISABLE_XTALOK_V(v)     BM_RTC_PERSISTENT0_DISABLE_XTALOK
+#define BP_RTC_PERSISTENT0_MSEC_RES                 8
+#define BM_RTC_PERSISTENT0_MSEC_RES                 0x1f00
+#define BF_RTC_PERSISTENT0_MSEC_RES(v)              (((v) & 0x1f) << 8)
+#define BFM_RTC_PERSISTENT0_MSEC_RES(v)             BM_RTC_PERSISTENT0_MSEC_RES
+#define BF_RTC_PERSISTENT0_MSEC_RES_V(e)            BF_RTC_PERSISTENT0_MSEC_RES(BV_RTC_PERSISTENT0_MSEC_RES__##e)
+#define BFM_RTC_PERSISTENT0_MSEC_RES_V(v)           BM_RTC_PERSISTENT0_MSEC_RES
+#define BP_RTC_PERSISTENT0_ALARM_WAKE               7
+#define BM_RTC_PERSISTENT0_ALARM_WAKE               0x80
+#define BF_RTC_PERSISTENT0_ALARM_WAKE(v)            (((v) & 0x1) << 7)
+#define BFM_RTC_PERSISTENT0_ALARM_WAKE(v)           BM_RTC_PERSISTENT0_ALARM_WAKE
+#define BF_RTC_PERSISTENT0_ALARM_WAKE_V(e)          BF_RTC_PERSISTENT0_ALARM_WAKE(BV_RTC_PERSISTENT0_ALARM_WAKE__##e)
+#define BFM_RTC_PERSISTENT0_ALARM_WAKE_V(v)         BM_RTC_PERSISTENT0_ALARM_WAKE
+#define BP_RTC_PERSISTENT0_XTAL32_FREQ              6
+#define BM_RTC_PERSISTENT0_XTAL32_FREQ              0x40
+#define BF_RTC_PERSISTENT0_XTAL32_FREQ(v)           (((v) & 0x1) << 6)
+#define BFM_RTC_PERSISTENT0_XTAL32_FREQ(v)          BM_RTC_PERSISTENT0_XTAL32_FREQ
+#define BF_RTC_PERSISTENT0_XTAL32_FREQ_V(e)         BF_RTC_PERSISTENT0_XTAL32_FREQ(BV_RTC_PERSISTENT0_XTAL32_FREQ__##e)
+#define BFM_RTC_PERSISTENT0_XTAL32_FREQ_V(v)        BM_RTC_PERSISTENT0_XTAL32_FREQ
+#define BP_RTC_PERSISTENT0_XTAL32KHZ_PWRUP          5
+#define BM_RTC_PERSISTENT0_XTAL32KHZ_PWRUP          0x20
+#define BF_RTC_PERSISTENT0_XTAL32KHZ_PWRUP(v)       (((v) & 0x1) << 5)
+#define BFM_RTC_PERSISTENT0_XTAL32KHZ_PWRUP(v)      BM_RTC_PERSISTENT0_XTAL32KHZ_PWRUP
+#define BF_RTC_PERSISTENT0_XTAL32KHZ_PWRUP_V(e)     BF_RTC_PERSISTENT0_XTAL32KHZ_PWRUP(BV_RTC_PERSISTENT0_XTAL32KHZ_PWRUP__##e)
+#define BFM_RTC_PERSISTENT0_XTAL32KHZ_PWRUP_V(v)    BM_RTC_PERSISTENT0_XTAL32KHZ_PWRUP
+#define BP_RTC_PERSISTENT0_XTAL24MHZ_PWRUP          4
+#define BM_RTC_PERSISTENT0_XTAL24MHZ_PWRUP          0x10
+#define BF_RTC_PERSISTENT0_XTAL24MHZ_PWRUP(v)       (((v) & 0x1) << 4)
+#define BFM_RTC_PERSISTENT0_XTAL24MHZ_PWRUP(v)      BM_RTC_PERSISTENT0_XTAL24MHZ_PWRUP
+#define BF_RTC_PERSISTENT0_XTAL24MHZ_PWRUP_V(e)     BF_RTC_PERSISTENT0_XTAL24MHZ_PWRUP(BV_RTC_PERSISTENT0_XTAL24MHZ_PWRUP__##e)
+#define BFM_RTC_PERSISTENT0_XTAL24MHZ_PWRUP_V(v)    BM_RTC_PERSISTENT0_XTAL24MHZ_PWRUP
+#define BP_RTC_PERSISTENT0_LCK_SECS                 3
+#define BM_RTC_PERSISTENT0_LCK_SECS                 0x8
+#define BF_RTC_PERSISTENT0_LCK_SECS(v)              (((v) & 0x1) << 3)
+#define BFM_RTC_PERSISTENT0_LCK_SECS(v)             BM_RTC_PERSISTENT0_LCK_SECS
+#define BF_RTC_PERSISTENT0_LCK_SECS_V(e)            BF_RTC_PERSISTENT0_LCK_SECS(BV_RTC_PERSISTENT0_LCK_SECS__##e)
+#define BFM_RTC_PERSISTENT0_LCK_SECS_V(v)           BM_RTC_PERSISTENT0_LCK_SECS
+#define BP_RTC_PERSISTENT0_ALARM_EN                 2
+#define BM_RTC_PERSISTENT0_ALARM_EN                 0x4
+#define BF_RTC_PERSISTENT0_ALARM_EN(v)              (((v) & 0x1) << 2)
+#define BFM_RTC_PERSISTENT0_ALARM_EN(v)             BM_RTC_PERSISTENT0_ALARM_EN
+#define BF_RTC_PERSISTENT0_ALARM_EN_V(e)            BF_RTC_PERSISTENT0_ALARM_EN(BV_RTC_PERSISTENT0_ALARM_EN__##e)
+#define BFM_RTC_PERSISTENT0_ALARM_EN_V(v)           BM_RTC_PERSISTENT0_ALARM_EN
+#define BP_RTC_PERSISTENT0_ALARM_WAKE_EN            1
+#define BM_RTC_PERSISTENT0_ALARM_WAKE_EN            0x2
+#define BF_RTC_PERSISTENT0_ALARM_WAKE_EN(v)         (((v) & 0x1) << 1)
+#define BFM_RTC_PERSISTENT0_ALARM_WAKE_EN(v)        BM_RTC_PERSISTENT0_ALARM_WAKE_EN
+#define BF_RTC_PERSISTENT0_ALARM_WAKE_EN_V(e)       BF_RTC_PERSISTENT0_ALARM_WAKE_EN(BV_RTC_PERSISTENT0_ALARM_WAKE_EN__##e)
+#define BFM_RTC_PERSISTENT0_ALARM_WAKE_EN_V(v)      BM_RTC_PERSISTENT0_ALARM_WAKE_EN
+#define BP_RTC_PERSISTENT0_CLOCKSOURCE              0
+#define BM_RTC_PERSISTENT0_CLOCKSOURCE              0x1
+#define BF_RTC_PERSISTENT0_CLOCKSOURCE(v)           (((v) & 0x1) << 0)
+#define BFM_RTC_PERSISTENT0_CLOCKSOURCE(v)          BM_RTC_PERSISTENT0_CLOCKSOURCE
+#define BF_RTC_PERSISTENT0_CLOCKSOURCE_V(e)         BF_RTC_PERSISTENT0_CLOCKSOURCE(BV_RTC_PERSISTENT0_CLOCKSOURCE__##e)
+#define BFM_RTC_PERSISTENT0_CLOCKSOURCE_V(v)        BM_RTC_PERSISTENT0_CLOCKSOURCE
+
+#define HW_RTC_PERSISTENT1                                  HW(RTC_PERSISTENT1)
+#define HWA_RTC_PERSISTENT1                                 (0x8005c000 + 0x70)
+#define HWT_RTC_PERSISTENT1                                 HWIO_32_RW
+#define HWN_RTC_PERSISTENT1                                 RTC_PERSISTENT1
+#define HWI_RTC_PERSISTENT1                                 
+#define HW_RTC_PERSISTENT1_SET                              HW(RTC_PERSISTENT1_SET)
+#define HWA_RTC_PERSISTENT1_SET                             (HWA_RTC_PERSISTENT1 + 0x4)
+#define HWT_RTC_PERSISTENT1_SET                             HWIO_32_WO
+#define HWN_RTC_PERSISTENT1_SET                             RTC_PERSISTENT1
+#define HWI_RTC_PERSISTENT1_SET                             
+#define HW_RTC_PERSISTENT1_CLR                              HW(RTC_PERSISTENT1_CLR)
+#define HWA_RTC_PERSISTENT1_CLR                             (HWA_RTC_PERSISTENT1 + 0x8)
+#define HWT_RTC_PERSISTENT1_CLR                             HWIO_32_WO
+#define HWN_RTC_PERSISTENT1_CLR                             RTC_PERSISTENT1
+#define HWI_RTC_PERSISTENT1_CLR                             
+#define HW_RTC_PERSISTENT1_TOG                              HW(RTC_PERSISTENT1_TOG)
+#define HWA_RTC_PERSISTENT1_TOG                             (HWA_RTC_PERSISTENT1 + 0xc)
+#define HWT_RTC_PERSISTENT1_TOG                             HWIO_32_WO
+#define HWN_RTC_PERSISTENT1_TOG                             RTC_PERSISTENT1
+#define HWI_RTC_PERSISTENT1_TOG                             
+#define BP_RTC_PERSISTENT1_GENERAL                          0
+#define BM_RTC_PERSISTENT1_GENERAL                          0xffffffff
+#define BV_RTC_PERSISTENT1_GENERAL__ENUMERATE_500MA_TWICE   0x1000
+#define BV_RTC_PERSISTENT1_GENERAL__USB_BOOT_PLAYER_MODE    0x800
+#define BV_RTC_PERSISTENT1_GENERAL__SKIP_CHECKDISK          0x400
+#define BV_RTC_PERSISTENT1_GENERAL__USB_LOW_POWER_MODE      0x200
+#define BV_RTC_PERSISTENT1_GENERAL__OTG_HNP_BIT             0x100
+#define BV_RTC_PERSISTENT1_GENERAL__OTG_ATL_ROLE_BIT        0x80
+#define BF_RTC_PERSISTENT1_GENERAL(v)                       (((v) & 0xffffffff) << 0)
+#define BFM_RTC_PERSISTENT1_GENERAL(v)                      BM_RTC_PERSISTENT1_GENERAL
+#define BF_RTC_PERSISTENT1_GENERAL_V(e)                     BF_RTC_PERSISTENT1_GENERAL(BV_RTC_PERSISTENT1_GENERAL__##e)
+#define BFM_RTC_PERSISTENT1_GENERAL_V(v)                    BM_RTC_PERSISTENT1_GENERAL
+
+#define HW_RTC_PERSISTENT2                  HW(RTC_PERSISTENT2)
+#define HWA_RTC_PERSISTENT2                 (0x8005c000 + 0x80)
+#define HWT_RTC_PERSISTENT2                 HWIO_32_RW
+#define HWN_RTC_PERSISTENT2                 RTC_PERSISTENT2
+#define HWI_RTC_PERSISTENT2                 
+#define HW_RTC_PERSISTENT2_SET              HW(RTC_PERSISTENT2_SET)
+#define HWA_RTC_PERSISTENT2_SET             (HWA_RTC_PERSISTENT2 + 0x4)
+#define HWT_RTC_PERSISTENT2_SET             HWIO_32_WO
+#define HWN_RTC_PERSISTENT2_SET             RTC_PERSISTENT2
+#define HWI_RTC_PERSISTENT2_SET             
+#define HW_RTC_PERSISTENT2_CLR              HW(RTC_PERSISTENT2_CLR)
+#define HWA_RTC_PERSISTENT2_CLR             (HWA_RTC_PERSISTENT2 + 0x8)
+#define HWT_RTC_PERSISTENT2_CLR             HWIO_32_WO
+#define HWN_RTC_PERSISTENT2_CLR             RTC_PERSISTENT2
+#define HWI_RTC_PERSISTENT2_CLR             
+#define HW_RTC_PERSISTENT2_TOG              HW(RTC_PERSISTENT2_TOG)
+#define HWA_RTC_PERSISTENT2_TOG             (HWA_RTC_PERSISTENT2 + 0xc)
+#define HWT_RTC_PERSISTENT2_TOG             HWIO_32_WO
+#define HWN_RTC_PERSISTENT2_TOG             RTC_PERSISTENT2
+#define HWI_RTC_PERSISTENT2_TOG             
+#define BP_RTC_PERSISTENT2_GENERAL          0
+#define BM_RTC_PERSISTENT2_GENERAL          0xffffffff
+#define BF_RTC_PERSISTENT2_GENERAL(v)       (((v) & 0xffffffff) << 0)
+#define BFM_RTC_PERSISTENT2_GENERAL(v)      BM_RTC_PERSISTENT2_GENERAL
+#define BF_RTC_PERSISTENT2_GENERAL_V(e)     BF_RTC_PERSISTENT2_GENERAL(BV_RTC_PERSISTENT2_GENERAL__##e)
+#define BFM_RTC_PERSISTENT2_GENERAL_V(v)    BM_RTC_PERSISTENT2_GENERAL
+
+#define HW_RTC_PERSISTENT3                  HW(RTC_PERSISTENT3)
+#define HWA_RTC_PERSISTENT3                 (0x8005c000 + 0x90)
+#define HWT_RTC_PERSISTENT3                 HWIO_32_RW
+#define HWN_RTC_PERSISTENT3                 RTC_PERSISTENT3
+#define HWI_RTC_PERSISTENT3                 
+#define HW_RTC_PERSISTENT3_SET              HW(RTC_PERSISTENT3_SET)
+#define HWA_RTC_PERSISTENT3_SET             (HWA_RTC_PERSISTENT3 + 0x4)
+#define HWT_RTC_PERSISTENT3_SET             HWIO_32_WO
+#define HWN_RTC_PERSISTENT3_SET             RTC_PERSISTENT3
+#define HWI_RTC_PERSISTENT3_SET             
+#define HW_RTC_PERSISTENT3_CLR              HW(RTC_PERSISTENT3_CLR)
+#define HWA_RTC_PERSISTENT3_CLR             (HWA_RTC_PERSISTENT3 + 0x8)
+#define HWT_RTC_PERSISTENT3_CLR             HWIO_32_WO
+#define HWN_RTC_PERSISTENT3_CLR             RTC_PERSISTENT3
+#define HWI_RTC_PERSISTENT3_CLR             
+#define HW_RTC_PERSISTENT3_TOG              HW(RTC_PERSISTENT3_TOG)
+#define HWA_RTC_PERSISTENT3_TOG             (HWA_RTC_PERSISTENT3 + 0xc)
+#define HWT_RTC_PERSISTENT3_TOG             HWIO_32_WO
+#define HWN_RTC_PERSISTENT3_TOG             RTC_PERSISTENT3
+#define HWI_RTC_PERSISTENT3_TOG             
+#define BP_RTC_PERSISTENT3_GENERAL          0
+#define BM_RTC_PERSISTENT3_GENERAL          0xffffffff
+#define BF_RTC_PERSISTENT3_GENERAL(v)       (((v) & 0xffffffff) << 0)
+#define BFM_RTC_PERSISTENT3_GENERAL(v)      BM_RTC_PERSISTENT3_GENERAL
+#define BF_RTC_PERSISTENT3_GENERAL_V(e)     BF_RTC_PERSISTENT3_GENERAL(BV_RTC_PERSISTENT3_GENERAL__##e)
+#define BFM_RTC_PERSISTENT3_GENERAL_V(v)    BM_RTC_PERSISTENT3_GENERAL
+
+#define HW_RTC_PERSISTENT4                  HW(RTC_PERSISTENT4)
+#define HWA_RTC_PERSISTENT4                 (0x8005c000 + 0xa0)
+#define HWT_RTC_PERSISTENT4                 HWIO_32_RW
+#define HWN_RTC_PERSISTENT4                 RTC_PERSISTENT4
+#define HWI_RTC_PERSISTENT4                 
+#define HW_RTC_PERSISTENT4_SET              HW(RTC_PERSISTENT4_SET)
+#define HWA_RTC_PERSISTENT4_SET             (HWA_RTC_PERSISTENT4 + 0x4)
+#define HWT_RTC_PERSISTENT4_SET             HWIO_32_WO
+#define HWN_RTC_PERSISTENT4_SET             RTC_PERSISTENT4
+#define HWI_RTC_PERSISTENT4_SET             
+#define HW_RTC_PERSISTENT4_CLR              HW(RTC_PERSISTENT4_CLR)
+#define HWA_RTC_PERSISTENT4_CLR             (HWA_RTC_PERSISTENT4 + 0x8)
+#define HWT_RTC_PERSISTENT4_CLR             HWIO_32_WO
+#define HWN_RTC_PERSISTENT4_CLR             RTC_PERSISTENT4
+#define HWI_RTC_PERSISTENT4_CLR             
+#define HW_RTC_PERSISTENT4_TOG              HW(RTC_PERSISTENT4_TOG)
+#define HWA_RTC_PERSISTENT4_TOG             (HWA_RTC_PERSISTENT4 + 0xc)
+#define HWT_RTC_PERSISTENT4_TOG             HWIO_32_WO
+#define HWN_RTC_PERSISTENT4_TOG             RTC_PERSISTENT4
+#define HWI_RTC_PERSISTENT4_TOG             
+#define BP_RTC_PERSISTENT4_GENERAL          0
+#define BM_RTC_PERSISTENT4_GENERAL          0xffffffff
+#define BF_RTC_PERSISTENT4_GENERAL(v)       (((v) & 0xffffffff) << 0)
+#define BFM_RTC_PERSISTENT4_GENERAL(v)      BM_RTC_PERSISTENT4_GENERAL
+#define BF_RTC_PERSISTENT4_GENERAL_V(e)     BF_RTC_PERSISTENT4_GENERAL(BV_RTC_PERSISTENT4_GENERAL__##e)
+#define BFM_RTC_PERSISTENT4_GENERAL_V(v)    BM_RTC_PERSISTENT4_GENERAL
+
+#define HW_RTC_PERSISTENT5                  HW(RTC_PERSISTENT5)
+#define HWA_RTC_PERSISTENT5                 (0x8005c000 + 0xb0)
+#define HWT_RTC_PERSISTENT5                 HWIO_32_RW
+#define HWN_RTC_PERSISTENT5                 RTC_PERSISTENT5
+#define HWI_RTC_PERSISTENT5                 
+#define HW_RTC_PERSISTENT5_SET              HW(RTC_PERSISTENT5_SET)
+#define HWA_RTC_PERSISTENT5_SET             (HWA_RTC_PERSISTENT5 + 0x4)
+#define HWT_RTC_PERSISTENT5_SET             HWIO_32_WO
+#define HWN_RTC_PERSISTENT5_SET             RTC_PERSISTENT5
+#define HWI_RTC_PERSISTENT5_SET             
+#define HW_RTC_PERSISTENT5_CLR              HW(RTC_PERSISTENT5_CLR)
+#define HWA_RTC_PERSISTENT5_CLR             (HWA_RTC_PERSISTENT5 + 0x8)
+#define HWT_RTC_PERSISTENT5_CLR             HWIO_32_WO
+#define HWN_RTC_PERSISTENT5_CLR             RTC_PERSISTENT5
+#define HWI_RTC_PERSISTENT5_CLR             
+#define HW_RTC_PERSISTENT5_TOG              HW(RTC_PERSISTENT5_TOG)
+#define HWA_RTC_PERSISTENT5_TOG             (HWA_RTC_PERSISTENT5 + 0xc)
+#define HWT_RTC_PERSISTENT5_TOG             HWIO_32_WO
+#define HWN_RTC_PERSISTENT5_TOG             RTC_PERSISTENT5
+#define HWI_RTC_PERSISTENT5_TOG             
+#define BP_RTC_PERSISTENT5_GENERAL          0
+#define BM_RTC_PERSISTENT5_GENERAL          0xffffffff
+#define BF_RTC_PERSISTENT5_GENERAL(v)       (((v) & 0xffffffff) << 0)
+#define BFM_RTC_PERSISTENT5_GENERAL(v)      BM_RTC_PERSISTENT5_GENERAL
+#define BF_RTC_PERSISTENT5_GENERAL_V(e)     BF_RTC_PERSISTENT5_GENERAL(BV_RTC_PERSISTENT5_GENERAL__##e)
+#define BFM_RTC_PERSISTENT5_GENERAL_V(v)    BM_RTC_PERSISTENT5_GENERAL
+
+#define HW_RTC_DEBUG                            HW(RTC_DEBUG)
+#define HWA_RTC_DEBUG                           (0x8005c000 + 0xc0)
+#define HWT_RTC_DEBUG                           HWIO_32_RW
+#define HWN_RTC_DEBUG                           RTC_DEBUG
+#define HWI_RTC_DEBUG                           
+#define HW_RTC_DEBUG_SET                        HW(RTC_DEBUG_SET)
+#define HWA_RTC_DEBUG_SET                       (HWA_RTC_DEBUG + 0x4)
+#define HWT_RTC_DEBUG_SET                       HWIO_32_WO
+#define HWN_RTC_DEBUG_SET                       RTC_DEBUG
+#define HWI_RTC_DEBUG_SET                       
+#define HW_RTC_DEBUG_CLR                        HW(RTC_DEBUG_CLR)
+#define HWA_RTC_DEBUG_CLR                       (HWA_RTC_DEBUG + 0x8)
+#define HWT_RTC_DEBUG_CLR                       HWIO_32_WO
+#define HWN_RTC_DEBUG_CLR                       RTC_DEBUG
+#define HWI_RTC_DEBUG_CLR                       
+#define HW_RTC_DEBUG_TOG                        HW(RTC_DEBUG_TOG)
+#define HWA_RTC_DEBUG_TOG                       (HWA_RTC_DEBUG + 0xc)
+#define HWT_RTC_DEBUG_TOG                       HWIO_32_WO
+#define HWN_RTC_DEBUG_TOG                       RTC_DEBUG
+#define HWI_RTC_DEBUG_TOG                       
+#define BP_RTC_DEBUG_RSVD0                      2
+#define BM_RTC_DEBUG_RSVD0                      0xfffffffc
+#define BF_RTC_DEBUG_RSVD0(v)                   (((v) & 0x3fffffff) << 2)
+#define BFM_RTC_DEBUG_RSVD0(v)                  BM_RTC_DEBUG_RSVD0
+#define BF_RTC_DEBUG_RSVD0_V(e)                 BF_RTC_DEBUG_RSVD0(BV_RTC_DEBUG_RSVD0__##e)
+#define BFM_RTC_DEBUG_RSVD0_V(v)                BM_RTC_DEBUG_RSVD0
+#define BP_RTC_DEBUG_WATCHDOG_RESET_MASK        1
+#define BM_RTC_DEBUG_WATCHDOG_RESET_MASK        0x2
+#define BF_RTC_DEBUG_WATCHDOG_RESET_MASK(v)     (((v) & 0x1) << 1)
+#define BFM_RTC_DEBUG_WATCHDOG_RESET_MASK(v)    BM_RTC_DEBUG_WATCHDOG_RESET_MASK
+#define BF_RTC_DEBUG_WATCHDOG_RESET_MASK_V(e)   BF_RTC_DEBUG_WATCHDOG_RESET_MASK(BV_RTC_DEBUG_WATCHDOG_RESET_MASK__##e)
+#define BFM_RTC_DEBUG_WATCHDOG_RESET_MASK_V(v)  BM_RTC_DEBUG_WATCHDOG_RESET_MASK
+#define BP_RTC_DEBUG_WATCHDOG_RESET             0
+#define BM_RTC_DEBUG_WATCHDOG_RESET             0x1
+#define BF_RTC_DEBUG_WATCHDOG_RESET(v)          (((v) & 0x1) << 0)
+#define BFM_RTC_DEBUG_WATCHDOG_RESET(v)         BM_RTC_DEBUG_WATCHDOG_RESET
+#define BF_RTC_DEBUG_WATCHDOG_RESET_V(e)        BF_RTC_DEBUG_WATCHDOG_RESET(BV_RTC_DEBUG_WATCHDOG_RESET__##e)
+#define BFM_RTC_DEBUG_WATCHDOG_RESET_V(v)       BM_RTC_DEBUG_WATCHDOG_RESET
+
+#define HW_RTC_VERSION              HW(RTC_VERSION)
+#define HWA_RTC_VERSION             (0x8005c000 + 0xd0)
+#define HWT_RTC_VERSION             HWIO_32_RW
+#define HWN_RTC_VERSION             RTC_VERSION
+#define HWI_RTC_VERSION             
+#define BP_RTC_VERSION_MAJOR        24
+#define BM_RTC_VERSION_MAJOR        0xff000000
+#define BF_RTC_VERSION_MAJOR(v)     (((v) & 0xff) << 24)
+#define BFM_RTC_VERSION_MAJOR(v)    BM_RTC_VERSION_MAJOR
+#define BF_RTC_VERSION_MAJOR_V(e)   BF_RTC_VERSION_MAJOR(BV_RTC_VERSION_MAJOR__##e)
+#define BFM_RTC_VERSION_MAJOR_V(v)  BM_RTC_VERSION_MAJOR
+#define BP_RTC_VERSION_MINOR        16
+#define BM_RTC_VERSION_MINOR        0xff0000
+#define BF_RTC_VERSION_MINOR(v)     (((v) & 0xff) << 16)
+#define BFM_RTC_VERSION_MINOR(v)    BM_RTC_VERSION_MINOR
+#define BF_RTC_VERSION_MINOR_V(e)   BF_RTC_VERSION_MINOR(BV_RTC_VERSION_MINOR__##e)
+#define BFM_RTC_VERSION_MINOR_V(v)  BM_RTC_VERSION_MINOR
+#define BP_RTC_VERSION_STEP         0
+#define BM_RTC_VERSION_STEP         0xffff
+#define BF_RTC_VERSION_STEP(v)      (((v) & 0xffff) << 0)
+#define BFM_RTC_VERSION_STEP(v)     BM_RTC_VERSION_STEP
+#define BF_RTC_VERSION_STEP_V(e)    BF_RTC_VERSION_STEP(BV_RTC_VERSION_STEP__##e)
+#define BFM_RTC_VERSION_STEP_V(v)   BM_RTC_VERSION_STEP
+
+#endif /* __HEADERGEN_IMX233_RTC_H__*/
diff --git a/firmware/target/arm/imx233/regs/imx233/saif.h b/firmware/target/arm/imx233/regs/imx233/saif.h
new file mode 100644
index 0000000000..9388a554a3
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/imx233/saif.h
@@ -0,0 +1,300 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * imx233 version: 2.4.0
+ * imx233 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_IMX233_SAIF_H__
+#define __HEADERGEN_IMX233_SAIF_H__
+
+#define HW_SAIF_CTRL(_n1)                       HW(SAIF_CTRL(_n1))
+#define HWA_SAIF_CTRL(_n1)                      (((_n1) == 1 ? 0x80042000 : 0x80046000) + 0x0)
+#define HWT_SAIF_CTRL(_n1)                      HWIO_32_RW
+#define HWN_SAIF_CTRL(_n1)                      SAIF_CTRL
+#define HWI_SAIF_CTRL(_n1)                      (_n1)
+#define HW_SAIF_CTRL_SET(_n1)                   HW(SAIF_CTRL_SET(_n1))
+#define HWA_SAIF_CTRL_SET(_n1)                  (HWA_SAIF_CTRL(_n1) + 0x4)
+#define HWT_SAIF_CTRL_SET(_n1)                  HWIO_32_WO
+#define HWN_SAIF_CTRL_SET(_n1)                  SAIF_CTRL
+#define HWI_SAIF_CTRL_SET(_n1)                  (_n1)
+#define HW_SAIF_CTRL_CLR(_n1)                   HW(SAIF_CTRL_CLR(_n1))
+#define HWA_SAIF_CTRL_CLR(_n1)                  (HWA_SAIF_CTRL(_n1) + 0x8)
+#define HWT_SAIF_CTRL_CLR(_n1)                  HWIO_32_WO
+#define HWN_SAIF_CTRL_CLR(_n1)                  SAIF_CTRL
+#define HWI_SAIF_CTRL_CLR(_n1)                  (_n1)
+#define HW_SAIF_CTRL_TOG(_n1)                   HW(SAIF_CTRL_TOG(_n1))
+#define HWA_SAIF_CTRL_TOG(_n1)                  (HWA_SAIF_CTRL(_n1) + 0xc)
+#define HWT_SAIF_CTRL_TOG(_n1)                  HWIO_32_WO
+#define HWN_SAIF_CTRL_TOG(_n1)                  SAIF_CTRL
+#define HWI_SAIF_CTRL_TOG(_n1)                  (_n1)
+#define BP_SAIF_CTRL_SFTRST                     31
+#define BM_SAIF_CTRL_SFTRST                     0x80000000
+#define BF_SAIF_CTRL_SFTRST(v)                  (((v) & 0x1) << 31)
+#define BFM_SAIF_CTRL_SFTRST(v)                 BM_SAIF_CTRL_SFTRST
+#define BF_SAIF_CTRL_SFTRST_V(e)                BF_SAIF_CTRL_SFTRST(BV_SAIF_CTRL_SFTRST__##e)
+#define BFM_SAIF_CTRL_SFTRST_V(v)               BM_SAIF_CTRL_SFTRST
+#define BP_SAIF_CTRL_CLKGATE                    30
+#define BM_SAIF_CTRL_CLKGATE                    0x40000000
+#define BF_SAIF_CTRL_CLKGATE(v)                 (((v) & 0x1) << 30)
+#define BFM_SAIF_CTRL_CLKGATE(v)                BM_SAIF_CTRL_CLKGATE
+#define BF_SAIF_CTRL_CLKGATE_V(e)               BF_SAIF_CTRL_CLKGATE(BV_SAIF_CTRL_CLKGATE__##e)
+#define BFM_SAIF_CTRL_CLKGATE_V(v)              BM_SAIF_CTRL_CLKGATE
+#define BP_SAIF_CTRL_BITCLK_MULT_RATE           27
+#define BM_SAIF_CTRL_BITCLK_MULT_RATE           0x38000000
+#define BF_SAIF_CTRL_BITCLK_MULT_RATE(v)        (((v) & 0x7) << 27)
+#define BFM_SAIF_CTRL_BITCLK_MULT_RATE(v)       BM_SAIF_CTRL_BITCLK_MULT_RATE
+#define BF_SAIF_CTRL_BITCLK_MULT_RATE_V(e)      BF_SAIF_CTRL_BITCLK_MULT_RATE(BV_SAIF_CTRL_BITCLK_MULT_RATE__##e)
+#define BFM_SAIF_CTRL_BITCLK_MULT_RATE_V(v)     BM_SAIF_CTRL_BITCLK_MULT_RATE
+#define BP_SAIF_CTRL_BITCLK_BASE_RATE           26
+#define BM_SAIF_CTRL_BITCLK_BASE_RATE           0x4000000
+#define BF_SAIF_CTRL_BITCLK_BASE_RATE(v)        (((v) & 0x1) << 26)
+#define BFM_SAIF_CTRL_BITCLK_BASE_RATE(v)       BM_SAIF_CTRL_BITCLK_BASE_RATE
+#define BF_SAIF_CTRL_BITCLK_BASE_RATE_V(e)      BF_SAIF_CTRL_BITCLK_BASE_RATE(BV_SAIF_CTRL_BITCLK_BASE_RATE__##e)
+#define BFM_SAIF_CTRL_BITCLK_BASE_RATE_V(v)     BM_SAIF_CTRL_BITCLK_BASE_RATE
+#define BP_SAIF_CTRL_FIFO_ERROR_IRQ_EN          25
+#define BM_SAIF_CTRL_FIFO_ERROR_IRQ_EN          0x2000000
+#define BF_SAIF_CTRL_FIFO_ERROR_IRQ_EN(v)       (((v) & 0x1) << 25)
+#define BFM_SAIF_CTRL_FIFO_ERROR_IRQ_EN(v)      BM_SAIF_CTRL_FIFO_ERROR_IRQ_EN
+#define BF_SAIF_CTRL_FIFO_ERROR_IRQ_EN_V(e)     BF_SAIF_CTRL_FIFO_ERROR_IRQ_EN(BV_SAIF_CTRL_FIFO_ERROR_IRQ_EN__##e)
+#define BFM_SAIF_CTRL_FIFO_ERROR_IRQ_EN_V(v)    BM_SAIF_CTRL_FIFO_ERROR_IRQ_EN
+#define BP_SAIF_CTRL_FIFO_SERVICE_IRQ_EN        24
+#define BM_SAIF_CTRL_FIFO_SERVICE_IRQ_EN        0x1000000
+#define BF_SAIF_CTRL_FIFO_SERVICE_IRQ_EN(v)     (((v) & 0x1) << 24)
+#define BFM_SAIF_CTRL_FIFO_SERVICE_IRQ_EN(v)    BM_SAIF_CTRL_FIFO_SERVICE_IRQ_EN
+#define BF_SAIF_CTRL_FIFO_SERVICE_IRQ_EN_V(e)   BF_SAIF_CTRL_FIFO_SERVICE_IRQ_EN(BV_SAIF_CTRL_FIFO_SERVICE_IRQ_EN__##e)
+#define BFM_SAIF_CTRL_FIFO_SERVICE_IRQ_EN_V(v)  BM_SAIF_CTRL_FIFO_SERVICE_IRQ_EN
+#define BP_SAIF_CTRL_RSRVD2                     21
+#define BM_SAIF_CTRL_RSRVD2                     0xe00000
+#define BF_SAIF_CTRL_RSRVD2(v)                  (((v) & 0x7) << 21)
+#define BFM_SAIF_CTRL_RSRVD2(v)                 BM_SAIF_CTRL_RSRVD2
+#define BF_SAIF_CTRL_RSRVD2_V(e)                BF_SAIF_CTRL_RSRVD2(BV_SAIF_CTRL_RSRVD2__##e)
+#define BFM_SAIF_CTRL_RSRVD2_V(v)               BM_SAIF_CTRL_RSRVD2
+#define BP_SAIF_CTRL_DMAWAIT_COUNT              16
+#define BM_SAIF_CTRL_DMAWAIT_COUNT              0x1f0000
+#define BF_SAIF_CTRL_DMAWAIT_COUNT(v)           (((v) & 0x1f) << 16)
+#define BFM_SAIF_CTRL_DMAWAIT_COUNT(v)          BM_SAIF_CTRL_DMAWAIT_COUNT
+#define BF_SAIF_CTRL_DMAWAIT_COUNT_V(e)         BF_SAIF_CTRL_DMAWAIT_COUNT(BV_SAIF_CTRL_DMAWAIT_COUNT__##e)
+#define BFM_SAIF_CTRL_DMAWAIT_COUNT_V(v)        BM_SAIF_CTRL_DMAWAIT_COUNT
+#define BP_SAIF_CTRL_CHANNEL_NUM_SELECT         14
+#define BM_SAIF_CTRL_CHANNEL_NUM_SELECT         0xc000
+#define BF_SAIF_CTRL_CHANNEL_NUM_SELECT(v)      (((v) & 0x3) << 14)
+#define BFM_SAIF_CTRL_CHANNEL_NUM_SELECT(v)     BM_SAIF_CTRL_CHANNEL_NUM_SELECT
+#define BF_SAIF_CTRL_CHANNEL_NUM_SELECT_V(e)    BF_SAIF_CTRL_CHANNEL_NUM_SELECT(BV_SAIF_CTRL_CHANNEL_NUM_SELECT__##e)
+#define BFM_SAIF_CTRL_CHANNEL_NUM_SELECT_V(v)   BM_SAIF_CTRL_CHANNEL_NUM_SELECT
+#define BP_SAIF_CTRL_RSRVD1                     13
+#define BM_SAIF_CTRL_RSRVD1                     0x2000
+#define BF_SAIF_CTRL_RSRVD1(v)                  (((v) & 0x1) << 13)
+#define BFM_SAIF_CTRL_RSRVD1(v)                 BM_SAIF_CTRL_RSRVD1
+#define BF_SAIF_CTRL_RSRVD1_V(e)                BF_SAIF_CTRL_RSRVD1(BV_SAIF_CTRL_RSRVD1__##e)
+#define BFM_SAIF_CTRL_RSRVD1_V(v)               BM_SAIF_CTRL_RSRVD1
+#define BP_SAIF_CTRL_BIT_ORDER                  12
+#define BM_SAIF_CTRL_BIT_ORDER                  0x1000
+#define BF_SAIF_CTRL_BIT_ORDER(v)               (((v) & 0x1) << 12)
+#define BFM_SAIF_CTRL_BIT_ORDER(v)              BM_SAIF_CTRL_BIT_ORDER
+#define BF_SAIF_CTRL_BIT_ORDER_V(e)             BF_SAIF_CTRL_BIT_ORDER(BV_SAIF_CTRL_BIT_ORDER__##e)
+#define BFM_SAIF_CTRL_BIT_ORDER_V(v)            BM_SAIF_CTRL_BIT_ORDER
+#define BP_SAIF_CTRL_DELAY                      11
+#define BM_SAIF_CTRL_DELAY                      0x800
+#define BF_SAIF_CTRL_DELAY(v)                   (((v) & 0x1) << 11)
+#define BFM_SAIF_CTRL_DELAY(v)                  BM_SAIF_CTRL_DELAY
+#define BF_SAIF_CTRL_DELAY_V(e)                 BF_SAIF_CTRL_DELAY(BV_SAIF_CTRL_DELAY__##e)
+#define BFM_SAIF_CTRL_DELAY_V(v)                BM_SAIF_CTRL_DELAY
+#define BP_SAIF_CTRL_JUSTIFY                    10
+#define BM_SAIF_CTRL_JUSTIFY                    0x400
+#define BF_SAIF_CTRL_JUSTIFY(v)                 (((v) & 0x1) << 10)
+#define BFM_SAIF_CTRL_JUSTIFY(v)                BM_SAIF_CTRL_JUSTIFY
+#define BF_SAIF_CTRL_JUSTIFY_V(e)               BF_SAIF_CTRL_JUSTIFY(BV_SAIF_CTRL_JUSTIFY__##e)
+#define BFM_SAIF_CTRL_JUSTIFY_V(v)              BM_SAIF_CTRL_JUSTIFY
+#define BP_SAIF_CTRL_LRCLK_POLARITY             9
+#define BM_SAIF_CTRL_LRCLK_POLARITY             0x200
+#define BF_SAIF_CTRL_LRCLK_POLARITY(v)          (((v) & 0x1) << 9)
+#define BFM_SAIF_CTRL_LRCLK_POLARITY(v)         BM_SAIF_CTRL_LRCLK_POLARITY
+#define BF_SAIF_CTRL_LRCLK_POLARITY_V(e)        BF_SAIF_CTRL_LRCLK_POLARITY(BV_SAIF_CTRL_LRCLK_POLARITY__##e)
+#define BFM_SAIF_CTRL_LRCLK_POLARITY_V(v)       BM_SAIF_CTRL_LRCLK_POLARITY
+#define BP_SAIF_CTRL_BITCLK_EDGE                8
+#define BM_SAIF_CTRL_BITCLK_EDGE                0x100
+#define BF_SAIF_CTRL_BITCLK_EDGE(v)             (((v) & 0x1) << 8)
+#define BFM_SAIF_CTRL_BITCLK_EDGE(v)            BM_SAIF_CTRL_BITCLK_EDGE
+#define BF_SAIF_CTRL_BITCLK_EDGE_V(e)           BF_SAIF_CTRL_BITCLK_EDGE(BV_SAIF_CTRL_BITCLK_EDGE__##e)
+#define BFM_SAIF_CTRL_BITCLK_EDGE_V(v)          BM_SAIF_CTRL_BITCLK_EDGE
+#define BP_SAIF_CTRL_WORD_LENGTH                4
+#define BM_SAIF_CTRL_WORD_LENGTH                0xf0
+#define BF_SAIF_CTRL_WORD_LENGTH(v)             (((v) & 0xf) << 4)
+#define BFM_SAIF_CTRL_WORD_LENGTH(v)            BM_SAIF_CTRL_WORD_LENGTH
+#define BF_SAIF_CTRL_WORD_LENGTH_V(e)           BF_SAIF_CTRL_WORD_LENGTH(BV_SAIF_CTRL_WORD_LENGTH__##e)
+#define BFM_SAIF_CTRL_WORD_LENGTH_V(v)          BM_SAIF_CTRL_WORD_LENGTH
+#define BP_SAIF_CTRL_BITCLK_48XFS_ENABLE        3
+#define BM_SAIF_CTRL_BITCLK_48XFS_ENABLE        0x8
+#define BF_SAIF_CTRL_BITCLK_48XFS_ENABLE(v)     (((v) & 0x1) << 3)
+#define BFM_SAIF_CTRL_BITCLK_48XFS_ENABLE(v)    BM_SAIF_CTRL_BITCLK_48XFS_ENABLE
+#define BF_SAIF_CTRL_BITCLK_48XFS_ENABLE_V(e)   BF_SAIF_CTRL_BITCLK_48XFS_ENABLE(BV_SAIF_CTRL_BITCLK_48XFS_ENABLE__##e)
+#define BFM_SAIF_CTRL_BITCLK_48XFS_ENABLE_V(v)  BM_SAIF_CTRL_BITCLK_48XFS_ENABLE
+#define BP_SAIF_CTRL_SLAVE_MODE                 2
+#define BM_SAIF_CTRL_SLAVE_MODE                 0x4
+#define BF_SAIF_CTRL_SLAVE_MODE(v)              (((v) & 0x1) << 2)
+#define BFM_SAIF_CTRL_SLAVE_MODE(v)             BM_SAIF_CTRL_SLAVE_MODE
+#define BF_SAIF_CTRL_SLAVE_MODE_V(e)            BF_SAIF_CTRL_SLAVE_MODE(BV_SAIF_CTRL_SLAVE_MODE__##e)
+#define BFM_SAIF_CTRL_SLAVE_MODE_V(v)           BM_SAIF_CTRL_SLAVE_MODE
+#define BP_SAIF_CTRL_READ_MODE                  1
+#define BM_SAIF_CTRL_READ_MODE                  0x2
+#define BF_SAIF_CTRL_READ_MODE(v)               (((v) & 0x1) << 1)
+#define BFM_SAIF_CTRL_READ_MODE(v)              BM_SAIF_CTRL_READ_MODE
+#define BF_SAIF_CTRL_READ_MODE_V(e)             BF_SAIF_CTRL_READ_MODE(BV_SAIF_CTRL_READ_MODE__##e)
+#define BFM_SAIF_CTRL_READ_MODE_V(v)            BM_SAIF_CTRL_READ_MODE
+#define BP_SAIF_CTRL_RUN                        0
+#define BM_SAIF_CTRL_RUN                        0x1
+#define BF_SAIF_CTRL_RUN(v)                     (((v) & 0x1) << 0)
+#define BFM_SAIF_CTRL_RUN(v)                    BM_SAIF_CTRL_RUN
+#define BF_SAIF_CTRL_RUN_V(e)                   BF_SAIF_CTRL_RUN(BV_SAIF_CTRL_RUN__##e)
+#define BFM_SAIF_CTRL_RUN_V(v)                  BM_SAIF_CTRL_RUN
+
+#define HW_SAIF_STAT(_n1)                       HW(SAIF_STAT(_n1))
+#define HWA_SAIF_STAT(_n1)                      (((_n1) == 1 ? 0x80042000 : 0x80046000) + 0x10)
+#define HWT_SAIF_STAT(_n1)                      HWIO_32_RW
+#define HWN_SAIF_STAT(_n1)                      SAIF_STAT
+#define HWI_SAIF_STAT(_n1)                      (_n1)
+#define HW_SAIF_STAT_SET(_n1)                   HW(SAIF_STAT_SET(_n1))
+#define HWA_SAIF_STAT_SET(_n1)                  (HWA_SAIF_STAT(_n1) + 0x4)
+#define HWT_SAIF_STAT_SET(_n1)                  HWIO_32_WO
+#define HWN_SAIF_STAT_SET(_n1)                  SAIF_STAT
+#define HWI_SAIF_STAT_SET(_n1)                  (_n1)
+#define HW_SAIF_STAT_CLR(_n1)                   HW(SAIF_STAT_CLR(_n1))
+#define HWA_SAIF_STAT_CLR(_n1)                  (HWA_SAIF_STAT(_n1) + 0x8)
+#define HWT_SAIF_STAT_CLR(_n1)                  HWIO_32_WO
+#define HWN_SAIF_STAT_CLR(_n1)                  SAIF_STAT
+#define HWI_SAIF_STAT_CLR(_n1)                  (_n1)
+#define HW_SAIF_STAT_TOG(_n1)                   HW(SAIF_STAT_TOG(_n1))
+#define HWA_SAIF_STAT_TOG(_n1)                  (HWA_SAIF_STAT(_n1) + 0xc)
+#define HWT_SAIF_STAT_TOG(_n1)                  HWIO_32_WO
+#define HWN_SAIF_STAT_TOG(_n1)                  SAIF_STAT
+#define HWI_SAIF_STAT_TOG(_n1)                  (_n1)
+#define BP_SAIF_STAT_PRESENT                    31
+#define BM_SAIF_STAT_PRESENT                    0x80000000
+#define BF_SAIF_STAT_PRESENT(v)                 (((v) & 0x1) << 31)
+#define BFM_SAIF_STAT_PRESENT(v)                BM_SAIF_STAT_PRESENT
+#define BF_SAIF_STAT_PRESENT_V(e)               BF_SAIF_STAT_PRESENT(BV_SAIF_STAT_PRESENT__##e)
+#define BFM_SAIF_STAT_PRESENT_V(v)              BM_SAIF_STAT_PRESENT
+#define BP_SAIF_STAT_RSRVD2                     17
+#define BM_SAIF_STAT_RSRVD2                     0x7ffe0000
+#define BF_SAIF_STAT_RSRVD2(v)                  (((v) & 0x3fff) << 17)
+#define BFM_SAIF_STAT_RSRVD2(v)                 BM_SAIF_STAT_RSRVD2
+#define BF_SAIF_STAT_RSRVD2_V(e)                BF_SAIF_STAT_RSRVD2(BV_SAIF_STAT_RSRVD2__##e)
+#define BFM_SAIF_STAT_RSRVD2_V(v)               BM_SAIF_STAT_RSRVD2
+#define BP_SAIF_STAT_DMA_PREQ                   16
+#define BM_SAIF_STAT_DMA_PREQ                   0x10000
+#define BF_SAIF_STAT_DMA_PREQ(v)                (((v) & 0x1) << 16)
+#define BFM_SAIF_STAT_DMA_PREQ(v)               BM_SAIF_STAT_DMA_PREQ
+#define BF_SAIF_STAT_DMA_PREQ_V(e)              BF_SAIF_STAT_DMA_PREQ(BV_SAIF_STAT_DMA_PREQ__##e)
+#define BFM_SAIF_STAT_DMA_PREQ_V(v)             BM_SAIF_STAT_DMA_PREQ
+#define BP_SAIF_STAT_RSRVD1                     7
+#define BM_SAIF_STAT_RSRVD1                     0xff80
+#define BF_SAIF_STAT_RSRVD1(v)                  (((v) & 0x1ff) << 7)
+#define BFM_SAIF_STAT_RSRVD1(v)                 BM_SAIF_STAT_RSRVD1
+#define BF_SAIF_STAT_RSRVD1_V(e)                BF_SAIF_STAT_RSRVD1(BV_SAIF_STAT_RSRVD1__##e)
+#define BFM_SAIF_STAT_RSRVD1_V(v)               BM_SAIF_STAT_RSRVD1
+#define BP_SAIF_STAT_FIFO_UNDERFLOW_IRQ         6
+#define BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ         0x40
+#define BF_SAIF_STAT_FIFO_UNDERFLOW_IRQ(v)      (((v) & 0x1) << 6)
+#define BFM_SAIF_STAT_FIFO_UNDERFLOW_IRQ(v)     BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ
+#define BF_SAIF_STAT_FIFO_UNDERFLOW_IRQ_V(e)    BF_SAIF_STAT_FIFO_UNDERFLOW_IRQ(BV_SAIF_STAT_FIFO_UNDERFLOW_IRQ__##e)
+#define BFM_SAIF_STAT_FIFO_UNDERFLOW_IRQ_V(v)   BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ
+#define BP_SAIF_STAT_FIFO_OVERFLOW_IRQ          5
+#define BM_SAIF_STAT_FIFO_OVERFLOW_IRQ          0x20
+#define BF_SAIF_STAT_FIFO_OVERFLOW_IRQ(v)       (((v) & 0x1) << 5)
+#define BFM_SAIF_STAT_FIFO_OVERFLOW_IRQ(v)      BM_SAIF_STAT_FIFO_OVERFLOW_IRQ
+#define BF_SAIF_STAT_FIFO_OVERFLOW_IRQ_V(e)     BF_SAIF_STAT_FIFO_OVERFLOW_IRQ(BV_SAIF_STAT_FIFO_OVERFLOW_IRQ__##e)
+#define BFM_SAIF_STAT_FIFO_OVERFLOW_IRQ_V(v)    BM_SAIF_STAT_FIFO_OVERFLOW_IRQ
+#define BP_SAIF_STAT_FIFO_SERVICE_IRQ           4
+#define BM_SAIF_STAT_FIFO_SERVICE_IRQ           0x10
+#define BF_SAIF_STAT_FIFO_SERVICE_IRQ(v)        (((v) & 0x1) << 4)
+#define BFM_SAIF_STAT_FIFO_SERVICE_IRQ(v)       BM_SAIF_STAT_FIFO_SERVICE_IRQ
+#define BF_SAIF_STAT_FIFO_SERVICE_IRQ_V(e)      BF_SAIF_STAT_FIFO_SERVICE_IRQ(BV_SAIF_STAT_FIFO_SERVICE_IRQ__##e)
+#define BFM_SAIF_STAT_FIFO_SERVICE_IRQ_V(v)     BM_SAIF_STAT_FIFO_SERVICE_IRQ
+#define BP_SAIF_STAT_RSRVD0                     1
+#define BM_SAIF_STAT_RSRVD0                     0xe
+#define BF_SAIF_STAT_RSRVD0(v)                  (((v) & 0x7) << 1)
+#define BFM_SAIF_STAT_RSRVD0(v)                 BM_SAIF_STAT_RSRVD0
+#define BF_SAIF_STAT_RSRVD0_V(e)                BF_SAIF_STAT_RSRVD0(BV_SAIF_STAT_RSRVD0__##e)
+#define BFM_SAIF_STAT_RSRVD0_V(v)               BM_SAIF_STAT_RSRVD0
+#define BP_SAIF_STAT_BUSY                       0
+#define BM_SAIF_STAT_BUSY                       0x1
+#define BF_SAIF_STAT_BUSY(v)                    (((v) & 0x1) << 0)
+#define BFM_SAIF_STAT_BUSY(v)                   BM_SAIF_STAT_BUSY
+#define BF_SAIF_STAT_BUSY_V(e)                  BF_SAIF_STAT_BUSY(BV_SAIF_STAT_BUSY__##e)
+#define BFM_SAIF_STAT_BUSY_V(v)                 BM_SAIF_STAT_BUSY
+
+#define HW_SAIF_DATA(_n1)               HW(SAIF_DATA(_n1))
+#define HWA_SAIF_DATA(_n1)              (((_n1) == 1 ? 0x80042000 : 0x80046000) + 0x20)
+#define HWT_SAIF_DATA(_n1)              HWIO_32_RW
+#define HWN_SAIF_DATA(_n1)              SAIF_DATA
+#define HWI_SAIF_DATA(_n1)              (_n1)
+#define HW_SAIF_DATA_SET(_n1)           HW(SAIF_DATA_SET(_n1))
+#define HWA_SAIF_DATA_SET(_n1)          (HWA_SAIF_DATA(_n1) + 0x4)
+#define HWT_SAIF_DATA_SET(_n1)          HWIO_32_WO
+#define HWN_SAIF_DATA_SET(_n1)          SAIF_DATA
+#define HWI_SAIF_DATA_SET(_n1)          (_n1)
+#define HW_SAIF_DATA_CLR(_n1)           HW(SAIF_DATA_CLR(_n1))
+#define HWA_SAIF_DATA_CLR(_n1)          (HWA_SAIF_DATA(_n1) + 0x8)
+#define HWT_SAIF_DATA_CLR(_n1)          HWIO_32_WO
+#define HWN_SAIF_DATA_CLR(_n1)          SAIF_DATA
+#define HWI_SAIF_DATA_CLR(_n1)          (_n1)
+#define HW_SAIF_DATA_TOG(_n1)           HW(SAIF_DATA_TOG(_n1))
+#define HWA_SAIF_DATA_TOG(_n1)          (HWA_SAIF_DATA(_n1) + 0xc)
+#define HWT_SAIF_DATA_TOG(_n1)          HWIO_32_WO
+#define HWN_SAIF_DATA_TOG(_n1)          SAIF_DATA
+#define HWI_SAIF_DATA_TOG(_n1)          (_n1)
+#define BP_SAIF_DATA_PCM_RIGHT          16
+#define BM_SAIF_DATA_PCM_RIGHT          0xffff0000
+#define BF_SAIF_DATA_PCM_RIGHT(v)       (((v) & 0xffff) << 16)
+#define BFM_SAIF_DATA_PCM_RIGHT(v)      BM_SAIF_DATA_PCM_RIGHT
+#define BF_SAIF_DATA_PCM_RIGHT_V(e)     BF_SAIF_DATA_PCM_RIGHT(BV_SAIF_DATA_PCM_RIGHT__##e)
+#define BFM_SAIF_DATA_PCM_RIGHT_V(v)    BM_SAIF_DATA_PCM_RIGHT
+#define BP_SAIF_DATA_PCM_LEFT           0
+#define BM_SAIF_DATA_PCM_LEFT           0xffff
+#define BF_SAIF_DATA_PCM_LEFT(v)        (((v) & 0xffff) << 0)
+#define BFM_SAIF_DATA_PCM_LEFT(v)       BM_SAIF_DATA_PCM_LEFT
+#define BF_SAIF_DATA_PCM_LEFT_V(e)      BF_SAIF_DATA_PCM_LEFT(BV_SAIF_DATA_PCM_LEFT__##e)
+#define BFM_SAIF_DATA_PCM_LEFT_V(v)     BM_SAIF_DATA_PCM_LEFT
+
+#define HW_SAIF_VERSION(_n1)        HW(SAIF_VERSION(_n1))
+#define HWA_SAIF_VERSION(_n1)       (((_n1) == 1 ? 0x80042000 : 0x80046000) + 0x30)
+#define HWT_SAIF_VERSION(_n1)       HWIO_32_RW
+#define HWN_SAIF_VERSION(_n1)       SAIF_VERSION
+#define HWI_SAIF_VERSION(_n1)       (_n1)
+#define BP_SAIF_VERSION_MAJOR       24
+#define BM_SAIF_VERSION_MAJOR       0xff000000
+#define BF_SAIF_VERSION_MAJOR(v)    (((v) & 0xff) << 24)
+#define BFM_SAIF_VERSION_MAJOR(v)   BM_SAIF_VERSION_MAJOR
+#define BF_SAIF_VERSION_MAJOR_V(e)  BF_SAIF_VERSION_MAJOR(BV_SAIF_VERSION_MAJOR__##e)
+#define BFM_SAIF_VERSION_MAJOR_V(v) BM_SAIF_VERSION_MAJOR
+#define BP_SAIF_VERSION_MINOR       16
+#define BM_SAIF_VERSION_MINOR       0xff0000
+#define BF_SAIF_VERSION_MINOR(v)    (((v) & 0xff) << 16)
+#define BFM_SAIF_VERSION_MINOR(v)   BM_SAIF_VERSION_MINOR
+#define BF_SAIF_VERSION_MINOR_V(e)  BF_SAIF_VERSION_MINOR(BV_SAIF_VERSION_MINOR__##e)
+#define BFM_SAIF_VERSION_MINOR_V(v) BM_SAIF_VERSION_MINOR
+#define BP_SAIF_VERSION_STEP        0
+#define BM_SAIF_VERSION_STEP        0xffff
+#define BF_SAIF_VERSION_STEP(v)     (((v) & 0xffff) << 0)
+#define BFM_SAIF_VERSION_STEP(v)    BM_SAIF_VERSION_STEP
+#define BF_SAIF_VERSION_STEP_V(e)   BF_SAIF_VERSION_STEP(BV_SAIF_VERSION_STEP__##e)
+#define BFM_SAIF_VERSION_STEP_V(v)  BM_SAIF_VERSION_STEP
+
+#endif /* __HEADERGEN_IMX233_SAIF_H__*/
diff --git a/firmware/target/arm/imx233/regs/imx233/spdif.h b/firmware/target/arm/imx233/regs/imx233/spdif.h
new file mode 100644
index 0000000000..5b14185eab
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/imx233/spdif.h
@@ -0,0 +1,393 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * imx233 version: 2.4.0
+ * imx233 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_IMX233_SPDIF_H__
+#define __HEADERGEN_IMX233_SPDIF_H__
+
+#define HW_SPDIF_CTRL                           HW(SPDIF_CTRL)
+#define HWA_SPDIF_CTRL                          (0x80054000 + 0x0)
+#define HWT_SPDIF_CTRL                          HWIO_32_RW
+#define HWN_SPDIF_CTRL                          SPDIF_CTRL
+#define HWI_SPDIF_CTRL                          
+#define HW_SPDIF_CTRL_SET                       HW(SPDIF_CTRL_SET)
+#define HWA_SPDIF_CTRL_SET                      (HWA_SPDIF_CTRL + 0x4)
+#define HWT_SPDIF_CTRL_SET                      HWIO_32_WO
+#define HWN_SPDIF_CTRL_SET                      SPDIF_CTRL
+#define HWI_SPDIF_CTRL_SET                      
+#define HW_SPDIF_CTRL_CLR                       HW(SPDIF_CTRL_CLR)
+#define HWA_SPDIF_CTRL_CLR                      (HWA_SPDIF_CTRL + 0x8)
+#define HWT_SPDIF_CTRL_CLR                      HWIO_32_WO
+#define HWN_SPDIF_CTRL_CLR                      SPDIF_CTRL
+#define HWI_SPDIF_CTRL_CLR                      
+#define HW_SPDIF_CTRL_TOG                       HW(SPDIF_CTRL_TOG)
+#define HWA_SPDIF_CTRL_TOG                      (HWA_SPDIF_CTRL + 0xc)
+#define HWT_SPDIF_CTRL_TOG                      HWIO_32_WO
+#define HWN_SPDIF_CTRL_TOG                      SPDIF_CTRL
+#define HWI_SPDIF_CTRL_TOG                      
+#define BP_SPDIF_CTRL_SFTRST                    31
+#define BM_SPDIF_CTRL_SFTRST                    0x80000000
+#define BF_SPDIF_CTRL_SFTRST(v)                 (((v) & 0x1) << 31)
+#define BFM_SPDIF_CTRL_SFTRST(v)                BM_SPDIF_CTRL_SFTRST
+#define BF_SPDIF_CTRL_SFTRST_V(e)               BF_SPDIF_CTRL_SFTRST(BV_SPDIF_CTRL_SFTRST__##e)
+#define BFM_SPDIF_CTRL_SFTRST_V(v)              BM_SPDIF_CTRL_SFTRST
+#define BP_SPDIF_CTRL_CLKGATE                   30
+#define BM_SPDIF_CTRL_CLKGATE                   0x40000000
+#define BF_SPDIF_CTRL_CLKGATE(v)                (((v) & 0x1) << 30)
+#define BFM_SPDIF_CTRL_CLKGATE(v)               BM_SPDIF_CTRL_CLKGATE
+#define BF_SPDIF_CTRL_CLKGATE_V(e)              BF_SPDIF_CTRL_CLKGATE(BV_SPDIF_CTRL_CLKGATE__##e)
+#define BFM_SPDIF_CTRL_CLKGATE_V(v)             BM_SPDIF_CTRL_CLKGATE
+#define BP_SPDIF_CTRL_RSRVD1                    21
+#define BM_SPDIF_CTRL_RSRVD1                    0x3fe00000
+#define BF_SPDIF_CTRL_RSRVD1(v)                 (((v) & 0x1ff) << 21)
+#define BFM_SPDIF_CTRL_RSRVD1(v)                BM_SPDIF_CTRL_RSRVD1
+#define BF_SPDIF_CTRL_RSRVD1_V(e)               BF_SPDIF_CTRL_RSRVD1(BV_SPDIF_CTRL_RSRVD1__##e)
+#define BFM_SPDIF_CTRL_RSRVD1_V(v)              BM_SPDIF_CTRL_RSRVD1
+#define BP_SPDIF_CTRL_DMAWAIT_COUNT             16
+#define BM_SPDIF_CTRL_DMAWAIT_COUNT             0x1f0000
+#define BF_SPDIF_CTRL_DMAWAIT_COUNT(v)          (((v) & 0x1f) << 16)
+#define BFM_SPDIF_CTRL_DMAWAIT_COUNT(v)         BM_SPDIF_CTRL_DMAWAIT_COUNT
+#define BF_SPDIF_CTRL_DMAWAIT_COUNT_V(e)        BF_SPDIF_CTRL_DMAWAIT_COUNT(BV_SPDIF_CTRL_DMAWAIT_COUNT__##e)
+#define BFM_SPDIF_CTRL_DMAWAIT_COUNT_V(v)       BM_SPDIF_CTRL_DMAWAIT_COUNT
+#define BP_SPDIF_CTRL_RSRVD0                    6
+#define BM_SPDIF_CTRL_RSRVD0                    0xffc0
+#define BF_SPDIF_CTRL_RSRVD0(v)                 (((v) & 0x3ff) << 6)
+#define BFM_SPDIF_CTRL_RSRVD0(v)                BM_SPDIF_CTRL_RSRVD0
+#define BF_SPDIF_CTRL_RSRVD0_V(e)               BF_SPDIF_CTRL_RSRVD0(BV_SPDIF_CTRL_RSRVD0__##e)
+#define BFM_SPDIF_CTRL_RSRVD0_V(v)              BM_SPDIF_CTRL_RSRVD0
+#define BP_SPDIF_CTRL_WAIT_END_XFER             5
+#define BM_SPDIF_CTRL_WAIT_END_XFER             0x20
+#define BF_SPDIF_CTRL_WAIT_END_XFER(v)          (((v) & 0x1) << 5)
+#define BFM_SPDIF_CTRL_WAIT_END_XFER(v)         BM_SPDIF_CTRL_WAIT_END_XFER
+#define BF_SPDIF_CTRL_WAIT_END_XFER_V(e)        BF_SPDIF_CTRL_WAIT_END_XFER(BV_SPDIF_CTRL_WAIT_END_XFER__##e)
+#define BFM_SPDIF_CTRL_WAIT_END_XFER_V(v)       BM_SPDIF_CTRL_WAIT_END_XFER
+#define BP_SPDIF_CTRL_WORD_LENGTH               4
+#define BM_SPDIF_CTRL_WORD_LENGTH               0x10
+#define BF_SPDIF_CTRL_WORD_LENGTH(v)            (((v) & 0x1) << 4)
+#define BFM_SPDIF_CTRL_WORD_LENGTH(v)           BM_SPDIF_CTRL_WORD_LENGTH
+#define BF_SPDIF_CTRL_WORD_LENGTH_V(e)          BF_SPDIF_CTRL_WORD_LENGTH(BV_SPDIF_CTRL_WORD_LENGTH__##e)
+#define BFM_SPDIF_CTRL_WORD_LENGTH_V(v)         BM_SPDIF_CTRL_WORD_LENGTH
+#define BP_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ        3
+#define BM_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ        0x8
+#define BF_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ(v)     (((v) & 0x1) << 3)
+#define BFM_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ(v)    BM_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ
+#define BF_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ_V(e)   BF_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ(BV_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ__##e)
+#define BFM_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ_V(v)  BM_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ
+#define BP_SPDIF_CTRL_FIFO_OVERFLOW_IRQ         2
+#define BM_SPDIF_CTRL_FIFO_OVERFLOW_IRQ         0x4
+#define BF_SPDIF_CTRL_FIFO_OVERFLOW_IRQ(v)      (((v) & 0x1) << 2)
+#define BFM_SPDIF_CTRL_FIFO_OVERFLOW_IRQ(v)     BM_SPDIF_CTRL_FIFO_OVERFLOW_IRQ
+#define BF_SPDIF_CTRL_FIFO_OVERFLOW_IRQ_V(e)    BF_SPDIF_CTRL_FIFO_OVERFLOW_IRQ(BV_SPDIF_CTRL_FIFO_OVERFLOW_IRQ__##e)
+#define BFM_SPDIF_CTRL_FIFO_OVERFLOW_IRQ_V(v)   BM_SPDIF_CTRL_FIFO_OVERFLOW_IRQ
+#define BP_SPDIF_CTRL_FIFO_ERROR_IRQ_EN         1
+#define BM_SPDIF_CTRL_FIFO_ERROR_IRQ_EN         0x2
+#define BF_SPDIF_CTRL_FIFO_ERROR_IRQ_EN(v)      (((v) & 0x1) << 1)
+#define BFM_SPDIF_CTRL_FIFO_ERROR_IRQ_EN(v)     BM_SPDIF_CTRL_FIFO_ERROR_IRQ_EN
+#define BF_SPDIF_CTRL_FIFO_ERROR_IRQ_EN_V(e)    BF_SPDIF_CTRL_FIFO_ERROR_IRQ_EN(BV_SPDIF_CTRL_FIFO_ERROR_IRQ_EN__##e)
+#define BFM_SPDIF_CTRL_FIFO_ERROR_IRQ_EN_V(v)   BM_SPDIF_CTRL_FIFO_ERROR_IRQ_EN
+#define BP_SPDIF_CTRL_RUN                       0
+#define BM_SPDIF_CTRL_RUN                       0x1
+#define BF_SPDIF_CTRL_RUN(v)                    (((v) & 0x1) << 0)
+#define BFM_SPDIF_CTRL_RUN(v)                   BM_SPDIF_CTRL_RUN
+#define BF_SPDIF_CTRL_RUN_V(e)                  BF_SPDIF_CTRL_RUN(BV_SPDIF_CTRL_RUN__##e)
+#define BFM_SPDIF_CTRL_RUN_V(v)                 BM_SPDIF_CTRL_RUN
+
+#define HW_SPDIF_STAT                   HW(SPDIF_STAT)
+#define HWA_SPDIF_STAT                  (0x80054000 + 0x10)
+#define HWT_SPDIF_STAT                  HWIO_32_RW
+#define HWN_SPDIF_STAT                  SPDIF_STAT
+#define HWI_SPDIF_STAT                  
+#define HW_SPDIF_STAT_SET               HW(SPDIF_STAT_SET)
+#define HWA_SPDIF_STAT_SET              (HWA_SPDIF_STAT + 0x4)
+#define HWT_SPDIF_STAT_SET              HWIO_32_WO
+#define HWN_SPDIF_STAT_SET              SPDIF_STAT
+#define HWI_SPDIF_STAT_SET              
+#define HW_SPDIF_STAT_CLR               HW(SPDIF_STAT_CLR)
+#define HWA_SPDIF_STAT_CLR              (HWA_SPDIF_STAT + 0x8)
+#define HWT_SPDIF_STAT_CLR              HWIO_32_WO
+#define HWN_SPDIF_STAT_CLR              SPDIF_STAT
+#define HWI_SPDIF_STAT_CLR              
+#define HW_SPDIF_STAT_TOG               HW(SPDIF_STAT_TOG)
+#define HWA_SPDIF_STAT_TOG              (HWA_SPDIF_STAT + 0xc)
+#define HWT_SPDIF_STAT_TOG              HWIO_32_WO
+#define HWN_SPDIF_STAT_TOG              SPDIF_STAT
+#define HWI_SPDIF_STAT_TOG              
+#define BP_SPDIF_STAT_PRESENT           31
+#define BM_SPDIF_STAT_PRESENT           0x80000000
+#define BF_SPDIF_STAT_PRESENT(v)        (((v) & 0x1) << 31)
+#define BFM_SPDIF_STAT_PRESENT(v)       BM_SPDIF_STAT_PRESENT
+#define BF_SPDIF_STAT_PRESENT_V(e)      BF_SPDIF_STAT_PRESENT(BV_SPDIF_STAT_PRESENT__##e)
+#define BFM_SPDIF_STAT_PRESENT_V(v)     BM_SPDIF_STAT_PRESENT
+#define BP_SPDIF_STAT_RSRVD1            1
+#define BM_SPDIF_STAT_RSRVD1            0x7ffffffe
+#define BF_SPDIF_STAT_RSRVD1(v)         (((v) & 0x3fffffff) << 1)
+#define BFM_SPDIF_STAT_RSRVD1(v)        BM_SPDIF_STAT_RSRVD1
+#define BF_SPDIF_STAT_RSRVD1_V(e)       BF_SPDIF_STAT_RSRVD1(BV_SPDIF_STAT_RSRVD1__##e)
+#define BFM_SPDIF_STAT_RSRVD1_V(v)      BM_SPDIF_STAT_RSRVD1
+#define BP_SPDIF_STAT_END_XFER          0
+#define BM_SPDIF_STAT_END_XFER          0x1
+#define BF_SPDIF_STAT_END_XFER(v)       (((v) & 0x1) << 0)
+#define BFM_SPDIF_STAT_END_XFER(v)      BM_SPDIF_STAT_END_XFER
+#define BF_SPDIF_STAT_END_XFER_V(e)     BF_SPDIF_STAT_END_XFER(BV_SPDIF_STAT_END_XFER__##e)
+#define BFM_SPDIF_STAT_END_XFER_V(v)    BM_SPDIF_STAT_END_XFER
+
+#define HW_SPDIF_FRAMECTRL                  HW(SPDIF_FRAMECTRL)
+#define HWA_SPDIF_FRAMECTRL                 (0x80054000 + 0x20)
+#define HWT_SPDIF_FRAMECTRL                 HWIO_32_RW
+#define HWN_SPDIF_FRAMECTRL                 SPDIF_FRAMECTRL
+#define HWI_SPDIF_FRAMECTRL                 
+#define HW_SPDIF_FRAMECTRL_SET              HW(SPDIF_FRAMECTRL_SET)
+#define HWA_SPDIF_FRAMECTRL_SET             (HWA_SPDIF_FRAMECTRL + 0x4)
+#define HWT_SPDIF_FRAMECTRL_SET             HWIO_32_WO
+#define HWN_SPDIF_FRAMECTRL_SET             SPDIF_FRAMECTRL
+#define HWI_SPDIF_FRAMECTRL_SET             
+#define HW_SPDIF_FRAMECTRL_CLR              HW(SPDIF_FRAMECTRL_CLR)
+#define HWA_SPDIF_FRAMECTRL_CLR             (HWA_SPDIF_FRAMECTRL + 0x8)
+#define HWT_SPDIF_FRAMECTRL_CLR             HWIO_32_WO
+#define HWN_SPDIF_FRAMECTRL_CLR             SPDIF_FRAMECTRL
+#define HWI_SPDIF_FRAMECTRL_CLR             
+#define HW_SPDIF_FRAMECTRL_TOG              HW(SPDIF_FRAMECTRL_TOG)
+#define HWA_SPDIF_FRAMECTRL_TOG             (HWA_SPDIF_FRAMECTRL + 0xc)
+#define HWT_SPDIF_FRAMECTRL_TOG             HWIO_32_WO
+#define HWN_SPDIF_FRAMECTRL_TOG             SPDIF_FRAMECTRL
+#define HWI_SPDIF_FRAMECTRL_TOG             
+#define BP_SPDIF_FRAMECTRL_RSRVD2           18
+#define BM_SPDIF_FRAMECTRL_RSRVD2           0xfffc0000
+#define BF_SPDIF_FRAMECTRL_RSRVD2(v)        (((v) & 0x3fff) << 18)
+#define BFM_SPDIF_FRAMECTRL_RSRVD2(v)       BM_SPDIF_FRAMECTRL_RSRVD2
+#define BF_SPDIF_FRAMECTRL_RSRVD2_V(e)      BF_SPDIF_FRAMECTRL_RSRVD2(BV_SPDIF_FRAMECTRL_RSRVD2__##e)
+#define BFM_SPDIF_FRAMECTRL_RSRVD2_V(v)     BM_SPDIF_FRAMECTRL_RSRVD2
+#define BP_SPDIF_FRAMECTRL_V_CONFIG         17
+#define BM_SPDIF_FRAMECTRL_V_CONFIG         0x20000
+#define BF_SPDIF_FRAMECTRL_V_CONFIG(v)      (((v) & 0x1) << 17)
+#define BFM_SPDIF_FRAMECTRL_V_CONFIG(v)     BM_SPDIF_FRAMECTRL_V_CONFIG
+#define BF_SPDIF_FRAMECTRL_V_CONFIG_V(e)    BF_SPDIF_FRAMECTRL_V_CONFIG(BV_SPDIF_FRAMECTRL_V_CONFIG__##e)
+#define BFM_SPDIF_FRAMECTRL_V_CONFIG_V(v)   BM_SPDIF_FRAMECTRL_V_CONFIG
+#define BP_SPDIF_FRAMECTRL_AUTO_MUTE        16
+#define BM_SPDIF_FRAMECTRL_AUTO_MUTE        0x10000
+#define BF_SPDIF_FRAMECTRL_AUTO_MUTE(v)     (((v) & 0x1) << 16)
+#define BFM_SPDIF_FRAMECTRL_AUTO_MUTE(v)    BM_SPDIF_FRAMECTRL_AUTO_MUTE
+#define BF_SPDIF_FRAMECTRL_AUTO_MUTE_V(e)   BF_SPDIF_FRAMECTRL_AUTO_MUTE(BV_SPDIF_FRAMECTRL_AUTO_MUTE__##e)
+#define BFM_SPDIF_FRAMECTRL_AUTO_MUTE_V(v)  BM_SPDIF_FRAMECTRL_AUTO_MUTE
+#define BP_SPDIF_FRAMECTRL_RSRVD1           15
+#define BM_SPDIF_FRAMECTRL_RSRVD1           0x8000
+#define BF_SPDIF_FRAMECTRL_RSRVD1(v)        (((v) & 0x1) << 15)
+#define BFM_SPDIF_FRAMECTRL_RSRVD1(v)       BM_SPDIF_FRAMECTRL_RSRVD1
+#define BF_SPDIF_FRAMECTRL_RSRVD1_V(e)      BF_SPDIF_FRAMECTRL_RSRVD1(BV_SPDIF_FRAMECTRL_RSRVD1__##e)
+#define BFM_SPDIF_FRAMECTRL_RSRVD1_V(v)     BM_SPDIF_FRAMECTRL_RSRVD1
+#define BP_SPDIF_FRAMECTRL_USER_DATA        14
+#define BM_SPDIF_FRAMECTRL_USER_DATA        0x4000
+#define BF_SPDIF_FRAMECTRL_USER_DATA(v)     (((v) & 0x1) << 14)
+#define BFM_SPDIF_FRAMECTRL_USER_DATA(v)    BM_SPDIF_FRAMECTRL_USER_DATA
+#define BF_SPDIF_FRAMECTRL_USER_DATA_V(e)   BF_SPDIF_FRAMECTRL_USER_DATA(BV_SPDIF_FRAMECTRL_USER_DATA__##e)
+#define BFM_SPDIF_FRAMECTRL_USER_DATA_V(v)  BM_SPDIF_FRAMECTRL_USER_DATA
+#define BP_SPDIF_FRAMECTRL_V                13
+#define BM_SPDIF_FRAMECTRL_V                0x2000
+#define BF_SPDIF_FRAMECTRL_V(v)             (((v) & 0x1) << 13)
+#define BFM_SPDIF_FRAMECTRL_V(v)            BM_SPDIF_FRAMECTRL_V
+#define BF_SPDIF_FRAMECTRL_V_V(e)           BF_SPDIF_FRAMECTRL_V(BV_SPDIF_FRAMECTRL_V__##e)
+#define BFM_SPDIF_FRAMECTRL_V_V(v)          BM_SPDIF_FRAMECTRL_V
+#define BP_SPDIF_FRAMECTRL_L                12
+#define BM_SPDIF_FRAMECTRL_L                0x1000
+#define BF_SPDIF_FRAMECTRL_L(v)             (((v) & 0x1) << 12)
+#define BFM_SPDIF_FRAMECTRL_L(v)            BM_SPDIF_FRAMECTRL_L
+#define BF_SPDIF_FRAMECTRL_L_V(e)           BF_SPDIF_FRAMECTRL_L(BV_SPDIF_FRAMECTRL_L__##e)
+#define BFM_SPDIF_FRAMECTRL_L_V(v)          BM_SPDIF_FRAMECTRL_L
+#define BP_SPDIF_FRAMECTRL_RSRVD0           11
+#define BM_SPDIF_FRAMECTRL_RSRVD0           0x800
+#define BF_SPDIF_FRAMECTRL_RSRVD0(v)        (((v) & 0x1) << 11)
+#define BFM_SPDIF_FRAMECTRL_RSRVD0(v)       BM_SPDIF_FRAMECTRL_RSRVD0
+#define BF_SPDIF_FRAMECTRL_RSRVD0_V(e)      BF_SPDIF_FRAMECTRL_RSRVD0(BV_SPDIF_FRAMECTRL_RSRVD0__##e)
+#define BFM_SPDIF_FRAMECTRL_RSRVD0_V(v)     BM_SPDIF_FRAMECTRL_RSRVD0
+#define BP_SPDIF_FRAMECTRL_CC               4
+#define BM_SPDIF_FRAMECTRL_CC               0x7f0
+#define BF_SPDIF_FRAMECTRL_CC(v)            (((v) & 0x7f) << 4)
+#define BFM_SPDIF_FRAMECTRL_CC(v)           BM_SPDIF_FRAMECTRL_CC
+#define BF_SPDIF_FRAMECTRL_CC_V(e)          BF_SPDIF_FRAMECTRL_CC(BV_SPDIF_FRAMECTRL_CC__##e)
+#define BFM_SPDIF_FRAMECTRL_CC_V(v)         BM_SPDIF_FRAMECTRL_CC
+#define BP_SPDIF_FRAMECTRL_PRE              3
+#define BM_SPDIF_FRAMECTRL_PRE              0x8
+#define BF_SPDIF_FRAMECTRL_PRE(v)           (((v) & 0x1) << 3)
+#define BFM_SPDIF_FRAMECTRL_PRE(v)          BM_SPDIF_FRAMECTRL_PRE
+#define BF_SPDIF_FRAMECTRL_PRE_V(e)         BF_SPDIF_FRAMECTRL_PRE(BV_SPDIF_FRAMECTRL_PRE__##e)
+#define BFM_SPDIF_FRAMECTRL_PRE_V(v)        BM_SPDIF_FRAMECTRL_PRE
+#define BP_SPDIF_FRAMECTRL_COPY             2
+#define BM_SPDIF_FRAMECTRL_COPY             0x4
+#define BF_SPDIF_FRAMECTRL_COPY(v)          (((v) & 0x1) << 2)
+#define BFM_SPDIF_FRAMECTRL_COPY(v)         BM_SPDIF_FRAMECTRL_COPY
+#define BF_SPDIF_FRAMECTRL_COPY_V(e)        BF_SPDIF_FRAMECTRL_COPY(BV_SPDIF_FRAMECTRL_COPY__##e)
+#define BFM_SPDIF_FRAMECTRL_COPY_V(v)       BM_SPDIF_FRAMECTRL_COPY
+#define BP_SPDIF_FRAMECTRL_AUDIO            1
+#define BM_SPDIF_FRAMECTRL_AUDIO            0x2
+#define BF_SPDIF_FRAMECTRL_AUDIO(v)         (((v) & 0x1) << 1)
+#define BFM_SPDIF_FRAMECTRL_AUDIO(v)        BM_SPDIF_FRAMECTRL_AUDIO
+#define BF_SPDIF_FRAMECTRL_AUDIO_V(e)       BF_SPDIF_FRAMECTRL_AUDIO(BV_SPDIF_FRAMECTRL_AUDIO__##e)
+#define BFM_SPDIF_FRAMECTRL_AUDIO_V(v)      BM_SPDIF_FRAMECTRL_AUDIO
+#define BP_SPDIF_FRAMECTRL_PRO              0
+#define BM_SPDIF_FRAMECTRL_PRO              0x1
+#define BF_SPDIF_FRAMECTRL_PRO(v)           (((v) & 0x1) << 0)
+#define BFM_SPDIF_FRAMECTRL_PRO(v)          BM_SPDIF_FRAMECTRL_PRO
+#define BF_SPDIF_FRAMECTRL_PRO_V(e)         BF_SPDIF_FRAMECTRL_PRO(BV_SPDIF_FRAMECTRL_PRO__##e)
+#define BFM_SPDIF_FRAMECTRL_PRO_V(v)        BM_SPDIF_FRAMECTRL_PRO
+
+#define HW_SPDIF_SRR                HW(SPDIF_SRR)
+#define HWA_SPDIF_SRR               (0x80054000 + 0x30)
+#define HWT_SPDIF_SRR               HWIO_32_RW
+#define HWN_SPDIF_SRR               SPDIF_SRR
+#define HWI_SPDIF_SRR               
+#define HW_SPDIF_SRR_SET            HW(SPDIF_SRR_SET)
+#define HWA_SPDIF_SRR_SET           (HWA_SPDIF_SRR + 0x4)
+#define HWT_SPDIF_SRR_SET           HWIO_32_WO
+#define HWN_SPDIF_SRR_SET           SPDIF_SRR
+#define HWI_SPDIF_SRR_SET           
+#define HW_SPDIF_SRR_CLR            HW(SPDIF_SRR_CLR)
+#define HWA_SPDIF_SRR_CLR           (HWA_SPDIF_SRR + 0x8)
+#define HWT_SPDIF_SRR_CLR           HWIO_32_WO
+#define HWN_SPDIF_SRR_CLR           SPDIF_SRR
+#define HWI_SPDIF_SRR_CLR           
+#define HW_SPDIF_SRR_TOG            HW(SPDIF_SRR_TOG)
+#define HWA_SPDIF_SRR_TOG           (HWA_SPDIF_SRR + 0xc)
+#define HWT_SPDIF_SRR_TOG           HWIO_32_WO
+#define HWN_SPDIF_SRR_TOG           SPDIF_SRR
+#define HWI_SPDIF_SRR_TOG           
+#define BP_SPDIF_SRR_RSRVD1         31
+#define BM_SPDIF_SRR_RSRVD1         0x80000000
+#define BF_SPDIF_SRR_RSRVD1(v)      (((v) & 0x1) << 31)
+#define BFM_SPDIF_SRR_RSRVD1(v)     BM_SPDIF_SRR_RSRVD1
+#define BF_SPDIF_SRR_RSRVD1_V(e)    BF_SPDIF_SRR_RSRVD1(BV_SPDIF_SRR_RSRVD1__##e)
+#define BFM_SPDIF_SRR_RSRVD1_V(v)   BM_SPDIF_SRR_RSRVD1
+#define BP_SPDIF_SRR_BASEMULT       28
+#define BM_SPDIF_SRR_BASEMULT       0x70000000
+#define BF_SPDIF_SRR_BASEMULT(v)    (((v) & 0x7) << 28)
+#define BFM_SPDIF_SRR_BASEMULT(v)   BM_SPDIF_SRR_BASEMULT
+#define BF_SPDIF_SRR_BASEMULT_V(e)  BF_SPDIF_SRR_BASEMULT(BV_SPDIF_SRR_BASEMULT__##e)
+#define BFM_SPDIF_SRR_BASEMULT_V(v) BM_SPDIF_SRR_BASEMULT
+#define BP_SPDIF_SRR_RSRVD0         20
+#define BM_SPDIF_SRR_RSRVD0         0xff00000
+#define BF_SPDIF_SRR_RSRVD0(v)      (((v) & 0xff) << 20)
+#define BFM_SPDIF_SRR_RSRVD0(v)     BM_SPDIF_SRR_RSRVD0
+#define BF_SPDIF_SRR_RSRVD0_V(e)    BF_SPDIF_SRR_RSRVD0(BV_SPDIF_SRR_RSRVD0__##e)
+#define BFM_SPDIF_SRR_RSRVD0_V(v)   BM_SPDIF_SRR_RSRVD0
+#define BP_SPDIF_SRR_RATE           0
+#define BM_SPDIF_SRR_RATE           0xfffff
+#define BF_SPDIF_SRR_RATE(v)        (((v) & 0xfffff) << 0)
+#define BFM_SPDIF_SRR_RATE(v)       BM_SPDIF_SRR_RATE
+#define BF_SPDIF_SRR_RATE_V(e)      BF_SPDIF_SRR_RATE(BV_SPDIF_SRR_RATE__##e)
+#define BFM_SPDIF_SRR_RATE_V(v)     BM_SPDIF_SRR_RATE
+
+#define HW_SPDIF_DEBUG                      HW(SPDIF_DEBUG)
+#define HWA_SPDIF_DEBUG                     (0x80054000 + 0x40)
+#define HWT_SPDIF_DEBUG                     HWIO_32_RW
+#define HWN_SPDIF_DEBUG                     SPDIF_DEBUG
+#define HWI_SPDIF_DEBUG                     
+#define HW_SPDIF_DEBUG_SET                  HW(SPDIF_DEBUG_SET)
+#define HWA_SPDIF_DEBUG_SET                 (HWA_SPDIF_DEBUG + 0x4)
+#define HWT_SPDIF_DEBUG_SET                 HWIO_32_WO
+#define HWN_SPDIF_DEBUG_SET                 SPDIF_DEBUG
+#define HWI_SPDIF_DEBUG_SET                 
+#define HW_SPDIF_DEBUG_CLR                  HW(SPDIF_DEBUG_CLR)
+#define HWA_SPDIF_DEBUG_CLR                 (HWA_SPDIF_DEBUG + 0x8)
+#define HWT_SPDIF_DEBUG_CLR                 HWIO_32_WO
+#define HWN_SPDIF_DEBUG_CLR                 SPDIF_DEBUG
+#define HWI_SPDIF_DEBUG_CLR                 
+#define HW_SPDIF_DEBUG_TOG                  HW(SPDIF_DEBUG_TOG)
+#define HWA_SPDIF_DEBUG_TOG                 (HWA_SPDIF_DEBUG + 0xc)
+#define HWT_SPDIF_DEBUG_TOG                 HWIO_32_WO
+#define HWN_SPDIF_DEBUG_TOG                 SPDIF_DEBUG
+#define HWI_SPDIF_DEBUG_TOG                 
+#define BP_SPDIF_DEBUG_RSRVD1               2
+#define BM_SPDIF_DEBUG_RSRVD1               0xfffffffc
+#define BF_SPDIF_DEBUG_RSRVD1(v)            (((v) & 0x3fffffff) << 2)
+#define BFM_SPDIF_DEBUG_RSRVD1(v)           BM_SPDIF_DEBUG_RSRVD1
+#define BF_SPDIF_DEBUG_RSRVD1_V(e)          BF_SPDIF_DEBUG_RSRVD1(BV_SPDIF_DEBUG_RSRVD1__##e)
+#define BFM_SPDIF_DEBUG_RSRVD1_V(v)         BM_SPDIF_DEBUG_RSRVD1
+#define BP_SPDIF_DEBUG_DMA_PREQ             1
+#define BM_SPDIF_DEBUG_DMA_PREQ             0x2
+#define BF_SPDIF_DEBUG_DMA_PREQ(v)          (((v) & 0x1) << 1)
+#define BFM_SPDIF_DEBUG_DMA_PREQ(v)         BM_SPDIF_DEBUG_DMA_PREQ
+#define BF_SPDIF_DEBUG_DMA_PREQ_V(e)        BF_SPDIF_DEBUG_DMA_PREQ(BV_SPDIF_DEBUG_DMA_PREQ__##e)
+#define BFM_SPDIF_DEBUG_DMA_PREQ_V(v)       BM_SPDIF_DEBUG_DMA_PREQ
+#define BP_SPDIF_DEBUG_FIFO_STATUS          0
+#define BM_SPDIF_DEBUG_FIFO_STATUS          0x1
+#define BF_SPDIF_DEBUG_FIFO_STATUS(v)       (((v) & 0x1) << 0)
+#define BFM_SPDIF_DEBUG_FIFO_STATUS(v)      BM_SPDIF_DEBUG_FIFO_STATUS
+#define BF_SPDIF_DEBUG_FIFO_STATUS_V(e)     BF_SPDIF_DEBUG_FIFO_STATUS(BV_SPDIF_DEBUG_FIFO_STATUS__##e)
+#define BFM_SPDIF_DEBUG_FIFO_STATUS_V(v)    BM_SPDIF_DEBUG_FIFO_STATUS
+
+#define HW_SPDIF_DATA               HW(SPDIF_DATA)
+#define HWA_SPDIF_DATA              (0x80054000 + 0x50)
+#define HWT_SPDIF_DATA              HWIO_32_RW
+#define HWN_SPDIF_DATA              SPDIF_DATA
+#define HWI_SPDIF_DATA              
+#define HW_SPDIF_DATA_SET           HW(SPDIF_DATA_SET)
+#define HWA_SPDIF_DATA_SET          (HWA_SPDIF_DATA + 0x4)
+#define HWT_SPDIF_DATA_SET          HWIO_32_WO
+#define HWN_SPDIF_DATA_SET          SPDIF_DATA
+#define HWI_SPDIF_DATA_SET          
+#define HW_SPDIF_DATA_CLR           HW(SPDIF_DATA_CLR)
+#define HWA_SPDIF_DATA_CLR          (HWA_SPDIF_DATA + 0x8)
+#define HWT_SPDIF_DATA_CLR          HWIO_32_WO
+#define HWN_SPDIF_DATA_CLR          SPDIF_DATA
+#define HWI_SPDIF_DATA_CLR          
+#define HW_SPDIF_DATA_TOG           HW(SPDIF_DATA_TOG)
+#define HWA_SPDIF_DATA_TOG          (HWA_SPDIF_DATA + 0xc)
+#define HWT_SPDIF_DATA_TOG          HWIO_32_WO
+#define HWN_SPDIF_DATA_TOG          SPDIF_DATA
+#define HWI_SPDIF_DATA_TOG          
+#define BP_SPDIF_DATA_HIGH          16
+#define BM_SPDIF_DATA_HIGH          0xffff0000
+#define BF_SPDIF_DATA_HIGH(v)       (((v) & 0xffff) << 16)
+#define BFM_SPDIF_DATA_HIGH(v)      BM_SPDIF_DATA_HIGH
+#define BF_SPDIF_DATA_HIGH_V(e)     BF_SPDIF_DATA_HIGH(BV_SPDIF_DATA_HIGH__##e)
+#define BFM_SPDIF_DATA_HIGH_V(v)    BM_SPDIF_DATA_HIGH
+#define BP_SPDIF_DATA_LOW           0
+#define BM_SPDIF_DATA_LOW           0xffff
+#define BF_SPDIF_DATA_LOW(v)        (((v) & 0xffff) << 0)
+#define BFM_SPDIF_DATA_LOW(v)       BM_SPDIF_DATA_LOW
+#define BF_SPDIF_DATA_LOW_V(e)      BF_SPDIF_DATA_LOW(BV_SPDIF_DATA_LOW__##e)
+#define BFM_SPDIF_DATA_LOW_V(v)     BM_SPDIF_DATA_LOW
+
+#define HW_SPDIF_VERSION                HW(SPDIF_VERSION)
+#define HWA_SPDIF_VERSION               (0x80054000 + 0x60)
+#define HWT_SPDIF_VERSION               HWIO_32_RW
+#define HWN_SPDIF_VERSION               SPDIF_VERSION
+#define HWI_SPDIF_VERSION               
+#define BP_SPDIF_VERSION_MAJOR          24
+#define BM_SPDIF_VERSION_MAJOR          0xff000000
+#define BF_SPDIF_VERSION_MAJOR(v)       (((v) & 0xff) << 24)
+#define BFM_SPDIF_VERSION_MAJOR(v)      BM_SPDIF_VERSION_MAJOR
+#define BF_SPDIF_VERSION_MAJOR_V(e)     BF_SPDIF_VERSION_MAJOR(BV_SPDIF_VERSION_MAJOR__##e)
+#define BFM_SPDIF_VERSION_MAJOR_V(v)    BM_SPDIF_VERSION_MAJOR
+#define BP_SPDIF_VERSION_MINOR          16
+#define BM_SPDIF_VERSION_MINOR          0xff0000
+#define BF_SPDIF_VERSION_MINOR(v)       (((v) & 0xff) << 16)
+#define BFM_SPDIF_VERSION_MINOR(v)      BM_SPDIF_VERSION_MINOR
+#define BF_SPDIF_VERSION_MINOR_V(e)     BF_SPDIF_VERSION_MINOR(BV_SPDIF_VERSION_MINOR__##e)
+#define BFM_SPDIF_VERSION_MINOR_V(v)    BM_SPDIF_VERSION_MINOR
+#define BP_SPDIF_VERSION_STEP           0
+#define BM_SPDIF_VERSION_STEP           0xffff
+#define BF_SPDIF_VERSION_STEP(v)        (((v) & 0xffff) << 0)
+#define BFM_SPDIF_VERSION_STEP(v)       BM_SPDIF_VERSION_STEP
+#define BF_SPDIF_VERSION_STEP_V(e)      BF_SPDIF_VERSION_STEP(BV_SPDIF_VERSION_STEP__##e)
+#define BFM_SPDIF_VERSION_STEP_V(v)     BM_SPDIF_VERSION_STEP
+
+#endif /* __HEADERGEN_IMX233_SPDIF_H__*/
diff --git a/firmware/target/arm/imx233/regs/imx233/ssp.h b/firmware/target/arm/imx233/regs/imx233/ssp.h
new file mode 100644
index 0000000000..37e8fb65e4
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/imx233/ssp.h
@@ -0,0 +1,885 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * imx233 version: 2.4.0
+ * imx233 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_IMX233_SSP_H__
+#define __HEADERGEN_IMX233_SSP_H__
+
+#define HW_SSP_CTRL0(_n1)                   HW(SSP_CTRL0(_n1))
+#define HWA_SSP_CTRL0(_n1)                  (((_n1) == 1 ? 0x80010000 : 0x80034000) + 0x0)
+#define HWT_SSP_CTRL0(_n1)                  HWIO_32_RW
+#define HWN_SSP_CTRL0(_n1)                  SSP_CTRL0
+#define HWI_SSP_CTRL0(_n1)                  (_n1)
+#define HW_SSP_CTRL0_SET(_n1)               HW(SSP_CTRL0_SET(_n1))
+#define HWA_SSP_CTRL0_SET(_n1)              (HWA_SSP_CTRL0(_n1) + 0x4)
+#define HWT_SSP_CTRL0_SET(_n1)              HWIO_32_WO
+#define HWN_SSP_CTRL0_SET(_n1)              SSP_CTRL0
+#define HWI_SSP_CTRL0_SET(_n1)              (_n1)
+#define HW_SSP_CTRL0_CLR(_n1)               HW(SSP_CTRL0_CLR(_n1))
+#define HWA_SSP_CTRL0_CLR(_n1)              (HWA_SSP_CTRL0(_n1) + 0x8)
+#define HWT_SSP_CTRL0_CLR(_n1)              HWIO_32_WO
+#define HWN_SSP_CTRL0_CLR(_n1)              SSP_CTRL0
+#define HWI_SSP_CTRL0_CLR(_n1)              (_n1)
+#define HW_SSP_CTRL0_TOG(_n1)               HW(SSP_CTRL0_TOG(_n1))
+#define HWA_SSP_CTRL0_TOG(_n1)              (HWA_SSP_CTRL0(_n1) + 0xc)
+#define HWT_SSP_CTRL0_TOG(_n1)              HWIO_32_WO
+#define HWN_SSP_CTRL0_TOG(_n1)              SSP_CTRL0
+#define HWI_SSP_CTRL0_TOG(_n1)              (_n1)
+#define BP_SSP_CTRL0_SFTRST                 31
+#define BM_SSP_CTRL0_SFTRST                 0x80000000
+#define BF_SSP_CTRL0_SFTRST(v)              (((v) & 0x1) << 31)
+#define BFM_SSP_CTRL0_SFTRST(v)             BM_SSP_CTRL0_SFTRST
+#define BF_SSP_CTRL0_SFTRST_V(e)            BF_SSP_CTRL0_SFTRST(BV_SSP_CTRL0_SFTRST__##e)
+#define BFM_SSP_CTRL0_SFTRST_V(v)           BM_SSP_CTRL0_SFTRST
+#define BP_SSP_CTRL0_CLKGATE                30
+#define BM_SSP_CTRL0_CLKGATE                0x40000000
+#define BF_SSP_CTRL0_CLKGATE(v)             (((v) & 0x1) << 30)
+#define BFM_SSP_CTRL0_CLKGATE(v)            BM_SSP_CTRL0_CLKGATE
+#define BF_SSP_CTRL0_CLKGATE_V(e)           BF_SSP_CTRL0_CLKGATE(BV_SSP_CTRL0_CLKGATE__##e)
+#define BFM_SSP_CTRL0_CLKGATE_V(v)          BM_SSP_CTRL0_CLKGATE
+#define BP_SSP_CTRL0_RUN                    29
+#define BM_SSP_CTRL0_RUN                    0x20000000
+#define BF_SSP_CTRL0_RUN(v)                 (((v) & 0x1) << 29)
+#define BFM_SSP_CTRL0_RUN(v)                BM_SSP_CTRL0_RUN
+#define BF_SSP_CTRL0_RUN_V(e)               BF_SSP_CTRL0_RUN(BV_SSP_CTRL0_RUN__##e)
+#define BFM_SSP_CTRL0_RUN_V(v)              BM_SSP_CTRL0_RUN
+#define BP_SSP_CTRL0_SDIO_IRQ_CHECK         28
+#define BM_SSP_CTRL0_SDIO_IRQ_CHECK         0x10000000
+#define BF_SSP_CTRL0_SDIO_IRQ_CHECK(v)      (((v) & 0x1) << 28)
+#define BFM_SSP_CTRL0_SDIO_IRQ_CHECK(v)     BM_SSP_CTRL0_SDIO_IRQ_CHECK
+#define BF_SSP_CTRL0_SDIO_IRQ_CHECK_V(e)    BF_SSP_CTRL0_SDIO_IRQ_CHECK(BV_SSP_CTRL0_SDIO_IRQ_CHECK__##e)
+#define BFM_SSP_CTRL0_SDIO_IRQ_CHECK_V(v)   BM_SSP_CTRL0_SDIO_IRQ_CHECK
+#define BP_SSP_CTRL0_LOCK_CS                27
+#define BM_SSP_CTRL0_LOCK_CS                0x8000000
+#define BF_SSP_CTRL0_LOCK_CS(v)             (((v) & 0x1) << 27)
+#define BFM_SSP_CTRL0_LOCK_CS(v)            BM_SSP_CTRL0_LOCK_CS
+#define BF_SSP_CTRL0_LOCK_CS_V(e)           BF_SSP_CTRL0_LOCK_CS(BV_SSP_CTRL0_LOCK_CS__##e)
+#define BFM_SSP_CTRL0_LOCK_CS_V(v)          BM_SSP_CTRL0_LOCK_CS
+#define BP_SSP_CTRL0_IGNORE_CRC             26
+#define BM_SSP_CTRL0_IGNORE_CRC             0x4000000
+#define BF_SSP_CTRL0_IGNORE_CRC(v)          (((v) & 0x1) << 26)
+#define BFM_SSP_CTRL0_IGNORE_CRC(v)         BM_SSP_CTRL0_IGNORE_CRC
+#define BF_SSP_CTRL0_IGNORE_CRC_V(e)        BF_SSP_CTRL0_IGNORE_CRC(BV_SSP_CTRL0_IGNORE_CRC__##e)
+#define BFM_SSP_CTRL0_IGNORE_CRC_V(v)       BM_SSP_CTRL0_IGNORE_CRC
+#define BP_SSP_CTRL0_READ                   25
+#define BM_SSP_CTRL0_READ                   0x2000000
+#define BF_SSP_CTRL0_READ(v)                (((v) & 0x1) << 25)
+#define BFM_SSP_CTRL0_READ(v)               BM_SSP_CTRL0_READ
+#define BF_SSP_CTRL0_READ_V(e)              BF_SSP_CTRL0_READ(BV_SSP_CTRL0_READ__##e)
+#define BFM_SSP_CTRL0_READ_V(v)             BM_SSP_CTRL0_READ
+#define BP_SSP_CTRL0_DATA_XFER              24
+#define BM_SSP_CTRL0_DATA_XFER              0x1000000
+#define BF_SSP_CTRL0_DATA_XFER(v)           (((v) & 0x1) << 24)
+#define BFM_SSP_CTRL0_DATA_XFER(v)          BM_SSP_CTRL0_DATA_XFER
+#define BF_SSP_CTRL0_DATA_XFER_V(e)         BF_SSP_CTRL0_DATA_XFER(BV_SSP_CTRL0_DATA_XFER__##e)
+#define BFM_SSP_CTRL0_DATA_XFER_V(v)        BM_SSP_CTRL0_DATA_XFER
+#define BP_SSP_CTRL0_BUS_WIDTH              22
+#define BM_SSP_CTRL0_BUS_WIDTH              0xc00000
+#define BV_SSP_CTRL0_BUS_WIDTH__ONE_BIT     0x0
+#define BV_SSP_CTRL0_BUS_WIDTH__FOUR_BIT    0x1
+#define BV_SSP_CTRL0_BUS_WIDTH__EIGHT_BIT   0x2
+#define BF_SSP_CTRL0_BUS_WIDTH(v)           (((v) & 0x3) << 22)
+#define BFM_SSP_CTRL0_BUS_WIDTH(v)          BM_SSP_CTRL0_BUS_WIDTH
+#define BF_SSP_CTRL0_BUS_WIDTH_V(e)         BF_SSP_CTRL0_BUS_WIDTH(BV_SSP_CTRL0_BUS_WIDTH__##e)
+#define BFM_SSP_CTRL0_BUS_WIDTH_V(v)        BM_SSP_CTRL0_BUS_WIDTH
+#define BP_SSP_CTRL0_WAIT_FOR_IRQ           21
+#define BM_SSP_CTRL0_WAIT_FOR_IRQ           0x200000
+#define BF_SSP_CTRL0_WAIT_FOR_IRQ(v)        (((v) & 0x1) << 21)
+#define BFM_SSP_CTRL0_WAIT_FOR_IRQ(v)       BM_SSP_CTRL0_WAIT_FOR_IRQ
+#define BF_SSP_CTRL0_WAIT_FOR_IRQ_V(e)      BF_SSP_CTRL0_WAIT_FOR_IRQ(BV_SSP_CTRL0_WAIT_FOR_IRQ__##e)
+#define BFM_SSP_CTRL0_WAIT_FOR_IRQ_V(v)     BM_SSP_CTRL0_WAIT_FOR_IRQ
+#define BP_SSP_CTRL0_WAIT_FOR_CMD           20
+#define BM_SSP_CTRL0_WAIT_FOR_CMD           0x100000
+#define BF_SSP_CTRL0_WAIT_FOR_CMD(v)        (((v) & 0x1) << 20)
+#define BFM_SSP_CTRL0_WAIT_FOR_CMD(v)       BM_SSP_CTRL0_WAIT_FOR_CMD
+#define BF_SSP_CTRL0_WAIT_FOR_CMD_V(e)      BF_SSP_CTRL0_WAIT_FOR_CMD(BV_SSP_CTRL0_WAIT_FOR_CMD__##e)
+#define BFM_SSP_CTRL0_WAIT_FOR_CMD_V(v)     BM_SSP_CTRL0_WAIT_FOR_CMD
+#define BP_SSP_CTRL0_LONG_RESP              19
+#define BM_SSP_CTRL0_LONG_RESP              0x80000
+#define BF_SSP_CTRL0_LONG_RESP(v)           (((v) & 0x1) << 19)
+#define BFM_SSP_CTRL0_LONG_RESP(v)          BM_SSP_CTRL0_LONG_RESP
+#define BF_SSP_CTRL0_LONG_RESP_V(e)         BF_SSP_CTRL0_LONG_RESP(BV_SSP_CTRL0_LONG_RESP__##e)
+#define BFM_SSP_CTRL0_LONG_RESP_V(v)        BM_SSP_CTRL0_LONG_RESP
+#define BP_SSP_CTRL0_CHECK_RESP             18
+#define BM_SSP_CTRL0_CHECK_RESP             0x40000
+#define BF_SSP_CTRL0_CHECK_RESP(v)          (((v) & 0x1) << 18)
+#define BFM_SSP_CTRL0_CHECK_RESP(v)         BM_SSP_CTRL0_CHECK_RESP
+#define BF_SSP_CTRL0_CHECK_RESP_V(e)        BF_SSP_CTRL0_CHECK_RESP(BV_SSP_CTRL0_CHECK_RESP__##e)
+#define BFM_SSP_CTRL0_CHECK_RESP_V(v)       BM_SSP_CTRL0_CHECK_RESP
+#define BP_SSP_CTRL0_GET_RESP               17
+#define BM_SSP_CTRL0_GET_RESP               0x20000
+#define BF_SSP_CTRL0_GET_RESP(v)            (((v) & 0x1) << 17)
+#define BFM_SSP_CTRL0_GET_RESP(v)           BM_SSP_CTRL0_GET_RESP
+#define BF_SSP_CTRL0_GET_RESP_V(e)          BF_SSP_CTRL0_GET_RESP(BV_SSP_CTRL0_GET_RESP__##e)
+#define BFM_SSP_CTRL0_GET_RESP_V(v)         BM_SSP_CTRL0_GET_RESP
+#define BP_SSP_CTRL0_ENABLE                 16
+#define BM_SSP_CTRL0_ENABLE                 0x10000
+#define BF_SSP_CTRL0_ENABLE(v)              (((v) & 0x1) << 16)
+#define BFM_SSP_CTRL0_ENABLE(v)             BM_SSP_CTRL0_ENABLE
+#define BF_SSP_CTRL0_ENABLE_V(e)            BF_SSP_CTRL0_ENABLE(BV_SSP_CTRL0_ENABLE__##e)
+#define BFM_SSP_CTRL0_ENABLE_V(v)           BM_SSP_CTRL0_ENABLE
+#define BP_SSP_CTRL0_XFER_COUNT             0
+#define BM_SSP_CTRL0_XFER_COUNT             0xffff
+#define BF_SSP_CTRL0_XFER_COUNT(v)          (((v) & 0xffff) << 0)
+#define BFM_SSP_CTRL0_XFER_COUNT(v)         BM_SSP_CTRL0_XFER_COUNT
+#define BF_SSP_CTRL0_XFER_COUNT_V(e)        BF_SSP_CTRL0_XFER_COUNT(BV_SSP_CTRL0_XFER_COUNT__##e)
+#define BFM_SSP_CTRL0_XFER_COUNT_V(v)       BM_SSP_CTRL0_XFER_COUNT
+
+#define HW_SSP_CMD0(_n1)                            HW(SSP_CMD0(_n1))
+#define HWA_SSP_CMD0(_n1)                           (((_n1) == 1 ? 0x80010000 : 0x80034000) + 0x10)
+#define HWT_SSP_CMD0(_n1)                           HWIO_32_RW
+#define HWN_SSP_CMD0(_n1)                           SSP_CMD0
+#define HWI_SSP_CMD0(_n1)                           (_n1)
+#define HW_SSP_CMD0_SET(_n1)                        HW(SSP_CMD0_SET(_n1))
+#define HWA_SSP_CMD0_SET(_n1)                       (HWA_SSP_CMD0(_n1) + 0x4)
+#define HWT_SSP_CMD0_SET(_n1)                       HWIO_32_WO
+#define HWN_SSP_CMD0_SET(_n1)                       SSP_CMD0
+#define HWI_SSP_CMD0_SET(_n1)                       (_n1)
+#define HW_SSP_CMD0_CLR(_n1)                        HW(SSP_CMD0_CLR(_n1))
+#define HWA_SSP_CMD0_CLR(_n1)                       (HWA_SSP_CMD0(_n1) + 0x8)
+#define HWT_SSP_CMD0_CLR(_n1)                       HWIO_32_WO
+#define HWN_SSP_CMD0_CLR(_n1)                       SSP_CMD0
+#define HWI_SSP_CMD0_CLR(_n1)                       (_n1)
+#define HW_SSP_CMD0_TOG(_n1)                        HW(SSP_CMD0_TOG(_n1))
+#define HWA_SSP_CMD0_TOG(_n1)                       (HWA_SSP_CMD0(_n1) + 0xc)
+#define HWT_SSP_CMD0_TOG(_n1)                       HWIO_32_WO
+#define HWN_SSP_CMD0_TOG(_n1)                       SSP_CMD0
+#define HWI_SSP_CMD0_TOG(_n1)                       (_n1)
+#define BP_SSP_CMD0_RSVD0                           23
+#define BM_SSP_CMD0_RSVD0                           0xff800000
+#define BF_SSP_CMD0_RSVD0(v)                        (((v) & 0x1ff) << 23)
+#define BFM_SSP_CMD0_RSVD0(v)                       BM_SSP_CMD0_RSVD0
+#define BF_SSP_CMD0_RSVD0_V(e)                      BF_SSP_CMD0_RSVD0(BV_SSP_CMD0_RSVD0__##e)
+#define BFM_SSP_CMD0_RSVD0_V(v)                     BM_SSP_CMD0_RSVD0
+#define BP_SSP_CMD0_SLOW_CLKING_EN                  22
+#define BM_SSP_CMD0_SLOW_CLKING_EN                  0x400000
+#define BF_SSP_CMD0_SLOW_CLKING_EN(v)               (((v) & 0x1) << 22)
+#define BFM_SSP_CMD0_SLOW_CLKING_EN(v)              BM_SSP_CMD0_SLOW_CLKING_EN
+#define BF_SSP_CMD0_SLOW_CLKING_EN_V(e)             BF_SSP_CMD0_SLOW_CLKING_EN(BV_SSP_CMD0_SLOW_CLKING_EN__##e)
+#define BFM_SSP_CMD0_SLOW_CLKING_EN_V(v)            BM_SSP_CMD0_SLOW_CLKING_EN
+#define BP_SSP_CMD0_CONT_CLKING_EN                  21
+#define BM_SSP_CMD0_CONT_CLKING_EN                  0x200000
+#define BF_SSP_CMD0_CONT_CLKING_EN(v)               (((v) & 0x1) << 21)
+#define BFM_SSP_CMD0_CONT_CLKING_EN(v)              BM_SSP_CMD0_CONT_CLKING_EN
+#define BF_SSP_CMD0_CONT_CLKING_EN_V(e)             BF_SSP_CMD0_CONT_CLKING_EN(BV_SSP_CMD0_CONT_CLKING_EN__##e)
+#define BFM_SSP_CMD0_CONT_CLKING_EN_V(v)            BM_SSP_CMD0_CONT_CLKING_EN
+#define BP_SSP_CMD0_APPEND_8CYC                     20
+#define BM_SSP_CMD0_APPEND_8CYC                     0x100000
+#define BF_SSP_CMD0_APPEND_8CYC(v)                  (((v) & 0x1) << 20)
+#define BFM_SSP_CMD0_APPEND_8CYC(v)                 BM_SSP_CMD0_APPEND_8CYC
+#define BF_SSP_CMD0_APPEND_8CYC_V(e)                BF_SSP_CMD0_APPEND_8CYC(BV_SSP_CMD0_APPEND_8CYC__##e)
+#define BFM_SSP_CMD0_APPEND_8CYC_V(v)               BM_SSP_CMD0_APPEND_8CYC
+#define BP_SSP_CMD0_BLOCK_SIZE                      16
+#define BM_SSP_CMD0_BLOCK_SIZE                      0xf0000
+#define BF_SSP_CMD0_BLOCK_SIZE(v)                   (((v) & 0xf) << 16)
+#define BFM_SSP_CMD0_BLOCK_SIZE(v)                  BM_SSP_CMD0_BLOCK_SIZE
+#define BF_SSP_CMD0_BLOCK_SIZE_V(e)                 BF_SSP_CMD0_BLOCK_SIZE(BV_SSP_CMD0_BLOCK_SIZE__##e)
+#define BFM_SSP_CMD0_BLOCK_SIZE_V(v)                BM_SSP_CMD0_BLOCK_SIZE
+#define BP_SSP_CMD0_BLOCK_COUNT                     8
+#define BM_SSP_CMD0_BLOCK_COUNT                     0xff00
+#define BF_SSP_CMD0_BLOCK_COUNT(v)                  (((v) & 0xff) << 8)
+#define BFM_SSP_CMD0_BLOCK_COUNT(v)                 BM_SSP_CMD0_BLOCK_COUNT
+#define BF_SSP_CMD0_BLOCK_COUNT_V(e)                BF_SSP_CMD0_BLOCK_COUNT(BV_SSP_CMD0_BLOCK_COUNT__##e)
+#define BFM_SSP_CMD0_BLOCK_COUNT_V(v)               BM_SSP_CMD0_BLOCK_COUNT
+#define BP_SSP_CMD0_CMD                             0
+#define BM_SSP_CMD0_CMD                             0xff
+#define BV_SSP_CMD0_CMD__MMC_GO_IDLE_STATE          0x0
+#define BV_SSP_CMD0_CMD__MMC_SEND_OP_COND           0x1
+#define BV_SSP_CMD0_CMD__MMC_ALL_SEND_CID           0x2
+#define BV_SSP_CMD0_CMD__MMC_SET_RELATIVE_ADDR      0x3
+#define BV_SSP_CMD0_CMD__MMC_SET_DSR                0x4
+#define BV_SSP_CMD0_CMD__MMC_RESERVED_5             0x5
+#define BV_SSP_CMD0_CMD__MMC_SWITCH                 0x6
+#define BV_SSP_CMD0_CMD__MMC_SELECT_DESELECT_CARD   0x7
+#define BV_SSP_CMD0_CMD__MMC_SEND_EXT_CSD           0x8
+#define BV_SSP_CMD0_CMD__MMC_SEND_CSD               0x9
+#define BV_SSP_CMD0_CMD__MMC_SEND_CID               0xa
+#define BV_SSP_CMD0_CMD__MMC_READ_DAT_UNTIL_STOP    0xb
+#define BV_SSP_CMD0_CMD__MMC_STOP_TRANSMISSION      0xc
+#define BV_SSP_CMD0_CMD__MMC_SEND_STATUS            0xd
+#define BV_SSP_CMD0_CMD__MMC_BUSTEST_R              0xe
+#define BV_SSP_CMD0_CMD__MMC_GO_INACTIVE_STATE      0xf
+#define BV_SSP_CMD0_CMD__MMC_SET_BLOCKLEN           0x10
+#define BV_SSP_CMD0_CMD__MMC_READ_SINGLE_BLOCK      0x11
+#define BV_SSP_CMD0_CMD__MMC_READ_MULTIPLE_BLOCK    0x12
+#define BV_SSP_CMD0_CMD__MMC_BUSTEST_W              0x13
+#define BV_SSP_CMD0_CMD__MMC_WRITE_DAT_UNTIL_STOP   0x14
+#define BV_SSP_CMD0_CMD__MMC_SET_BLOCK_COUNT        0x17
+#define BV_SSP_CMD0_CMD__MMC_WRITE_BLOCK            0x18
+#define BV_SSP_CMD0_CMD__MMC_WRITE_MULTIPLE_BLOCK   0x19
+#define BV_SSP_CMD0_CMD__MMC_PROGRAM_CID            0x1a
+#define BV_SSP_CMD0_CMD__MMC_PROGRAM_CSD            0x1b
+#define BV_SSP_CMD0_CMD__MMC_SET_WRITE_PROT         0x1c
+#define BV_SSP_CMD0_CMD__MMC_CLR_WRITE_PROT         0x1d
+#define BV_SSP_CMD0_CMD__MMC_SEND_WRITE_PROT        0x1e
+#define BV_SSP_CMD0_CMD__MMC_ERASE_GROUP_START      0x23
+#define BV_SSP_CMD0_CMD__MMC_ERASE_GROUP_END        0x24
+#define BV_SSP_CMD0_CMD__MMC_ERASE                  0x26
+#define BV_SSP_CMD0_CMD__MMC_FAST_IO                0x27
+#define BV_SSP_CMD0_CMD__MMC_GO_IRQ_STATE           0x28
+#define BV_SSP_CMD0_CMD__MMC_LOCK_UNLOCK            0x2a
+#define BV_SSP_CMD0_CMD__MMC_APP_CMD                0x37
+#define BV_SSP_CMD0_CMD__MMC_GEN_CMD                0x38
+#define BV_SSP_CMD0_CMD__SD_GO_IDLE_STATE           0x0
+#define BV_SSP_CMD0_CMD__SD_ALL_SEND_CID            0x2
+#define BV_SSP_CMD0_CMD__SD_SEND_RELATIVE_ADDR      0x3
+#define BV_SSP_CMD0_CMD__SD_SET_DSR                 0x4
+#define BV_SSP_CMD0_CMD__SD_IO_SEND_OP_COND         0x5
+#define BV_SSP_CMD0_CMD__SD_SELECT_DESELECT_CARD    0x7
+#define BV_SSP_CMD0_CMD__SD_SEND_CSD                0x9
+#define BV_SSP_CMD0_CMD__SD_SEND_CID                0xa
+#define BV_SSP_CMD0_CMD__SD_STOP_TRANSMISSION       0xc
+#define BV_SSP_CMD0_CMD__SD_SEND_STATUS             0xd
+#define BV_SSP_CMD0_CMD__SD_GO_INACTIVE_STATE       0xf
+#define BV_SSP_CMD0_CMD__SD_SET_BLOCKLEN            0x10
+#define BV_SSP_CMD0_CMD__SD_READ_SINGLE_BLOCK       0x11
+#define BV_SSP_CMD0_CMD__SD_READ_MULTIPLE_BLOCK     0x12
+#define BV_SSP_CMD0_CMD__SD_WRITE_BLOCK             0x18
+#define BV_SSP_CMD0_CMD__SD_WRITE_MULTIPLE_BLOCK    0x19
+#define BV_SSP_CMD0_CMD__SD_PROGRAM_CSD             0x1b
+#define BV_SSP_CMD0_CMD__SD_SET_WRITE_PROT          0x1c
+#define BV_SSP_CMD0_CMD__SD_CLR_WRITE_PROT          0x1d
+#define BV_SSP_CMD0_CMD__SD_SEND_WRITE_PROT         0x1e
+#define BV_SSP_CMD0_CMD__SD_ERASE_WR_BLK_START      0x20
+#define BV_SSP_CMD0_CMD__SD_ERASE_WR_BLK_END        0x21
+#define BV_SSP_CMD0_CMD__SD_ERASE_GROUP_START       0x23
+#define BV_SSP_CMD0_CMD__SD_ERASE_GROUP_END         0x24
+#define BV_SSP_CMD0_CMD__SD_ERASE                   0x26
+#define BV_SSP_CMD0_CMD__SD_LOCK_UNLOCK             0x2a
+#define BV_SSP_CMD0_CMD__SD_IO_RW_DIRECT            0x34
+#define BV_SSP_CMD0_CMD__SD_IO_RW_EXTENDED          0x35
+#define BV_SSP_CMD0_CMD__SD_APP_CMD                 0x37
+#define BV_SSP_CMD0_CMD__SD_GEN_CMD                 0x38
+#define BF_SSP_CMD0_CMD(v)                          (((v) & 0xff) << 0)
+#define BFM_SSP_CMD0_CMD(v)                         BM_SSP_CMD0_CMD
+#define BF_SSP_CMD0_CMD_V(e)                        BF_SSP_CMD0_CMD(BV_SSP_CMD0_CMD__##e)
+#define BFM_SSP_CMD0_CMD_V(v)                       BM_SSP_CMD0_CMD
+
+#define HW_SSP_CMD1(_n1)            HW(SSP_CMD1(_n1))
+#define HWA_SSP_CMD1(_n1)           (((_n1) == 1 ? 0x80010000 : 0x80034000) + 0x20)
+#define HWT_SSP_CMD1(_n1)           HWIO_32_RW
+#define HWN_SSP_CMD1(_n1)           SSP_CMD1
+#define HWI_SSP_CMD1(_n1)           (_n1)
+#define BP_SSP_CMD1_CMD_ARG         0
+#define BM_SSP_CMD1_CMD_ARG         0xffffffff
+#define BF_SSP_CMD1_CMD_ARG(v)      (((v) & 0xffffffff) << 0)
+#define BFM_SSP_CMD1_CMD_ARG(v)     BM_SSP_CMD1_CMD_ARG
+#define BF_SSP_CMD1_CMD_ARG_V(e)    BF_SSP_CMD1_CMD_ARG(BV_SSP_CMD1_CMD_ARG__##e)
+#define BFM_SSP_CMD1_CMD_ARG_V(v)   BM_SSP_CMD1_CMD_ARG
+
+#define HW_SSP_COMPREF(_n1)             HW(SSP_COMPREF(_n1))
+#define HWA_SSP_COMPREF(_n1)            (((_n1) == 1 ? 0x80010000 : 0x80034000) + 0x30)
+#define HWT_SSP_COMPREF(_n1)            HWIO_32_RW
+#define HWN_SSP_COMPREF(_n1)            SSP_COMPREF
+#define HWI_SSP_COMPREF(_n1)            (_n1)
+#define BP_SSP_COMPREF_REFERENCE        0
+#define BM_SSP_COMPREF_REFERENCE        0xffffffff
+#define BF_SSP_COMPREF_REFERENCE(v)     (((v) & 0xffffffff) << 0)
+#define BFM_SSP_COMPREF_REFERENCE(v)    BM_SSP_COMPREF_REFERENCE
+#define BF_SSP_COMPREF_REFERENCE_V(e)   BF_SSP_COMPREF_REFERENCE(BV_SSP_COMPREF_REFERENCE__##e)
+#define BFM_SSP_COMPREF_REFERENCE_V(v)  BM_SSP_COMPREF_REFERENCE
+
+#define HW_SSP_COMPMASK(_n1)        HW(SSP_COMPMASK(_n1))
+#define HWA_SSP_COMPMASK(_n1)       (((_n1) == 1 ? 0x80010000 : 0x80034000) + 0x40)
+#define HWT_SSP_COMPMASK(_n1)       HWIO_32_RW
+#define HWN_SSP_COMPMASK(_n1)       SSP_COMPMASK
+#define HWI_SSP_COMPMASK(_n1)       (_n1)
+#define BP_SSP_COMPMASK_MASK        0
+#define BM_SSP_COMPMASK_MASK        0xffffffff
+#define BF_SSP_COMPMASK_MASK(v)     (((v) & 0xffffffff) << 0)
+#define BFM_SSP_COMPMASK_MASK(v)    BM_SSP_COMPMASK_MASK
+#define BF_SSP_COMPMASK_MASK_V(e)   BF_SSP_COMPMASK_MASK(BV_SSP_COMPMASK_MASK__##e)
+#define BFM_SSP_COMPMASK_MASK_V(v)  BM_SSP_COMPMASK_MASK
+
+#define HW_SSP_TIMING(_n1)                  HW(SSP_TIMING(_n1))
+#define HWA_SSP_TIMING(_n1)                 (((_n1) == 1 ? 0x80010000 : 0x80034000) + 0x50)
+#define HWT_SSP_TIMING(_n1)                 HWIO_32_RW
+#define HWN_SSP_TIMING(_n1)                 SSP_TIMING
+#define HWI_SSP_TIMING(_n1)                 (_n1)
+#define BP_SSP_TIMING_TIMEOUT               16
+#define BM_SSP_TIMING_TIMEOUT               0xffff0000
+#define BF_SSP_TIMING_TIMEOUT(v)            (((v) & 0xffff) << 16)
+#define BFM_SSP_TIMING_TIMEOUT(v)           BM_SSP_TIMING_TIMEOUT
+#define BF_SSP_TIMING_TIMEOUT_V(e)          BF_SSP_TIMING_TIMEOUT(BV_SSP_TIMING_TIMEOUT__##e)
+#define BFM_SSP_TIMING_TIMEOUT_V(v)         BM_SSP_TIMING_TIMEOUT
+#define BP_SSP_TIMING_CLOCK_DIVIDE          8
+#define BM_SSP_TIMING_CLOCK_DIVIDE          0xff00
+#define BF_SSP_TIMING_CLOCK_DIVIDE(v)       (((v) & 0xff) << 8)
+#define BFM_SSP_TIMING_CLOCK_DIVIDE(v)      BM_SSP_TIMING_CLOCK_DIVIDE
+#define BF_SSP_TIMING_CLOCK_DIVIDE_V(e)     BF_SSP_TIMING_CLOCK_DIVIDE(BV_SSP_TIMING_CLOCK_DIVIDE__##e)
+#define BFM_SSP_TIMING_CLOCK_DIVIDE_V(v)    BM_SSP_TIMING_CLOCK_DIVIDE
+#define BP_SSP_TIMING_CLOCK_RATE            0
+#define BM_SSP_TIMING_CLOCK_RATE            0xff
+#define BF_SSP_TIMING_CLOCK_RATE(v)         (((v) & 0xff) << 0)
+#define BFM_SSP_TIMING_CLOCK_RATE(v)        BM_SSP_TIMING_CLOCK_RATE
+#define BF_SSP_TIMING_CLOCK_RATE_V(e)       BF_SSP_TIMING_CLOCK_RATE(BV_SSP_TIMING_CLOCK_RATE__##e)
+#define BFM_SSP_TIMING_CLOCK_RATE_V(v)      BM_SSP_TIMING_CLOCK_RATE
+
+#define HW_SSP_CTRL1(_n1)                       HW(SSP_CTRL1(_n1))
+#define HWA_SSP_CTRL1(_n1)                      (((_n1) == 1 ? 0x80010000 : 0x80034000) + 0x60)
+#define HWT_SSP_CTRL1(_n1)                      HWIO_32_RW
+#define HWN_SSP_CTRL1(_n1)                      SSP_CTRL1
+#define HWI_SSP_CTRL1(_n1)                      (_n1)
+#define HW_SSP_CTRL1_SET(_n1)                   HW(SSP_CTRL1_SET(_n1))
+#define HWA_SSP_CTRL1_SET(_n1)                  (HWA_SSP_CTRL1(_n1) + 0x4)
+#define HWT_SSP_CTRL1_SET(_n1)                  HWIO_32_WO
+#define HWN_SSP_CTRL1_SET(_n1)                  SSP_CTRL1
+#define HWI_SSP_CTRL1_SET(_n1)                  (_n1)
+#define HW_SSP_CTRL1_CLR(_n1)                   HW(SSP_CTRL1_CLR(_n1))
+#define HWA_SSP_CTRL1_CLR(_n1)                  (HWA_SSP_CTRL1(_n1) + 0x8)
+#define HWT_SSP_CTRL1_CLR(_n1)                  HWIO_32_WO
+#define HWN_SSP_CTRL1_CLR(_n1)                  SSP_CTRL1
+#define HWI_SSP_CTRL1_CLR(_n1)                  (_n1)
+#define HW_SSP_CTRL1_TOG(_n1)                   HW(SSP_CTRL1_TOG(_n1))
+#define HWA_SSP_CTRL1_TOG(_n1)                  (HWA_SSP_CTRL1(_n1) + 0xc)
+#define HWT_SSP_CTRL1_TOG(_n1)                  HWIO_32_WO
+#define HWN_SSP_CTRL1_TOG(_n1)                  SSP_CTRL1
+#define HWI_SSP_CTRL1_TOG(_n1)                  (_n1)
+#define BP_SSP_CTRL1_SDIO_IRQ                   31
+#define BM_SSP_CTRL1_SDIO_IRQ                   0x80000000
+#define BF_SSP_CTRL1_SDIO_IRQ(v)                (((v) & 0x1) << 31)
+#define BFM_SSP_CTRL1_SDIO_IRQ(v)               BM_SSP_CTRL1_SDIO_IRQ
+#define BF_SSP_CTRL1_SDIO_IRQ_V(e)              BF_SSP_CTRL1_SDIO_IRQ(BV_SSP_CTRL1_SDIO_IRQ__##e)
+#define BFM_SSP_CTRL1_SDIO_IRQ_V(v)             BM_SSP_CTRL1_SDIO_IRQ
+#define BP_SSP_CTRL1_SDIO_IRQ_EN                30
+#define BM_SSP_CTRL1_SDIO_IRQ_EN                0x40000000
+#define BF_SSP_CTRL1_SDIO_IRQ_EN(v)             (((v) & 0x1) << 30)
+#define BFM_SSP_CTRL1_SDIO_IRQ_EN(v)            BM_SSP_CTRL1_SDIO_IRQ_EN
+#define BF_SSP_CTRL1_SDIO_IRQ_EN_V(e)           BF_SSP_CTRL1_SDIO_IRQ_EN(BV_SSP_CTRL1_SDIO_IRQ_EN__##e)
+#define BFM_SSP_CTRL1_SDIO_IRQ_EN_V(v)          BM_SSP_CTRL1_SDIO_IRQ_EN
+#define BP_SSP_CTRL1_RESP_ERR_IRQ               29
+#define BM_SSP_CTRL1_RESP_ERR_IRQ               0x20000000
+#define BF_SSP_CTRL1_RESP_ERR_IRQ(v)            (((v) & 0x1) << 29)
+#define BFM_SSP_CTRL1_RESP_ERR_IRQ(v)           BM_SSP_CTRL1_RESP_ERR_IRQ
+#define BF_SSP_CTRL1_RESP_ERR_IRQ_V(e)          BF_SSP_CTRL1_RESP_ERR_IRQ(BV_SSP_CTRL1_RESP_ERR_IRQ__##e)
+#define BFM_SSP_CTRL1_RESP_ERR_IRQ_V(v)         BM_SSP_CTRL1_RESP_ERR_IRQ
+#define BP_SSP_CTRL1_RESP_ERR_IRQ_EN            28
+#define BM_SSP_CTRL1_RESP_ERR_IRQ_EN            0x10000000
+#define BF_SSP_CTRL1_RESP_ERR_IRQ_EN(v)         (((v) & 0x1) << 28)
+#define BFM_SSP_CTRL1_RESP_ERR_IRQ_EN(v)        BM_SSP_CTRL1_RESP_ERR_IRQ_EN
+#define BF_SSP_CTRL1_RESP_ERR_IRQ_EN_V(e)       BF_SSP_CTRL1_RESP_ERR_IRQ_EN(BV_SSP_CTRL1_RESP_ERR_IRQ_EN__##e)
+#define BFM_SSP_CTRL1_RESP_ERR_IRQ_EN_V(v)      BM_SSP_CTRL1_RESP_ERR_IRQ_EN
+#define BP_SSP_CTRL1_RESP_TIMEOUT_IRQ           27
+#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ           0x8000000
+#define BF_SSP_CTRL1_RESP_TIMEOUT_IRQ(v)        (((v) & 0x1) << 27)
+#define BFM_SSP_CTRL1_RESP_TIMEOUT_IRQ(v)       BM_SSP_CTRL1_RESP_TIMEOUT_IRQ
+#define BF_SSP_CTRL1_RESP_TIMEOUT_IRQ_V(e)      BF_SSP_CTRL1_RESP_TIMEOUT_IRQ(BV_SSP_CTRL1_RESP_TIMEOUT_IRQ__##e)
+#define BFM_SSP_CTRL1_RESP_TIMEOUT_IRQ_V(v)     BM_SSP_CTRL1_RESP_TIMEOUT_IRQ
+#define BP_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN        26
+#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN        0x4000000
+#define BF_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN(v)     (((v) & 0x1) << 26)
+#define BFM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN(v)    BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN
+#define BF_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN_V(e)   BF_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN(BV_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN__##e)
+#define BFM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN_V(v)  BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN
+#define BP_SSP_CTRL1_DATA_TIMEOUT_IRQ           25
+#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ           0x2000000
+#define BF_SSP_CTRL1_DATA_TIMEOUT_IRQ(v)        (((v) & 0x1) << 25)
+#define BFM_SSP_CTRL1_DATA_TIMEOUT_IRQ(v)       BM_SSP_CTRL1_DATA_TIMEOUT_IRQ
+#define BF_SSP_CTRL1_DATA_TIMEOUT_IRQ_V(e)      BF_SSP_CTRL1_DATA_TIMEOUT_IRQ(BV_SSP_CTRL1_DATA_TIMEOUT_IRQ__##e)
+#define BFM_SSP_CTRL1_DATA_TIMEOUT_IRQ_V(v)     BM_SSP_CTRL1_DATA_TIMEOUT_IRQ
+#define BP_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN        24
+#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN        0x1000000
+#define BF_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN(v)     (((v) & 0x1) << 24)
+#define BFM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN(v)    BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN
+#define BF_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN_V(e)   BF_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN(BV_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN__##e)
+#define BFM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN_V(v)  BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN
+#define BP_SSP_CTRL1_DATA_CRC_IRQ               23
+#define BM_SSP_CTRL1_DATA_CRC_IRQ               0x800000
+#define BF_SSP_CTRL1_DATA_CRC_IRQ(v)            (((v) & 0x1) << 23)
+#define BFM_SSP_CTRL1_DATA_CRC_IRQ(v)           BM_SSP_CTRL1_DATA_CRC_IRQ
+#define BF_SSP_CTRL1_DATA_CRC_IRQ_V(e)          BF_SSP_CTRL1_DATA_CRC_IRQ(BV_SSP_CTRL1_DATA_CRC_IRQ__##e)
+#define BFM_SSP_CTRL1_DATA_CRC_IRQ_V(v)         BM_SSP_CTRL1_DATA_CRC_IRQ
+#define BP_SSP_CTRL1_DATA_CRC_IRQ_EN            22
+#define BM_SSP_CTRL1_DATA_CRC_IRQ_EN            0x400000
+#define BF_SSP_CTRL1_DATA_CRC_IRQ_EN(v)         (((v) & 0x1) << 22)
+#define BFM_SSP_CTRL1_DATA_CRC_IRQ_EN(v)        BM_SSP_CTRL1_DATA_CRC_IRQ_EN
+#define BF_SSP_CTRL1_DATA_CRC_IRQ_EN_V(e)       BF_SSP_CTRL1_DATA_CRC_IRQ_EN(BV_SSP_CTRL1_DATA_CRC_IRQ_EN__##e)
+#define BFM_SSP_CTRL1_DATA_CRC_IRQ_EN_V(v)      BM_SSP_CTRL1_DATA_CRC_IRQ_EN
+#define BP_SSP_CTRL1_FIFO_UNDERRUN_IRQ          21
+#define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ          0x200000
+#define BF_SSP_CTRL1_FIFO_UNDERRUN_IRQ(v)       (((v) & 0x1) << 21)
+#define BFM_SSP_CTRL1_FIFO_UNDERRUN_IRQ(v)      BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ
+#define BF_SSP_CTRL1_FIFO_UNDERRUN_IRQ_V(e)     BF_SSP_CTRL1_FIFO_UNDERRUN_IRQ(BV_SSP_CTRL1_FIFO_UNDERRUN_IRQ__##e)
+#define BFM_SSP_CTRL1_FIFO_UNDERRUN_IRQ_V(v)    BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ
+#define BP_SSP_CTRL1_FIFO_UNDERRUN_EN           20
+#define BM_SSP_CTRL1_FIFO_UNDERRUN_EN           0x100000
+#define BF_SSP_CTRL1_FIFO_UNDERRUN_EN(v)        (((v) & 0x1) << 20)
+#define BFM_SSP_CTRL1_FIFO_UNDERRUN_EN(v)       BM_SSP_CTRL1_FIFO_UNDERRUN_EN
+#define BF_SSP_CTRL1_FIFO_UNDERRUN_EN_V(e)      BF_SSP_CTRL1_FIFO_UNDERRUN_EN(BV_SSP_CTRL1_FIFO_UNDERRUN_EN__##e)
+#define BFM_SSP_CTRL1_FIFO_UNDERRUN_EN_V(v)     BM_SSP_CTRL1_FIFO_UNDERRUN_EN
+#define BP_SSP_CTRL1_CEATA_CCS_ERR_IRQ          19
+#define BM_SSP_CTRL1_CEATA_CCS_ERR_IRQ          0x80000
+#define BF_SSP_CTRL1_CEATA_CCS_ERR_IRQ(v)       (((v) & 0x1) << 19)
+#define BFM_SSP_CTRL1_CEATA_CCS_ERR_IRQ(v)      BM_SSP_CTRL1_CEATA_CCS_ERR_IRQ
+#define BF_SSP_CTRL1_CEATA_CCS_ERR_IRQ_V(e)     BF_SSP_CTRL1_CEATA_CCS_ERR_IRQ(BV_SSP_CTRL1_CEATA_CCS_ERR_IRQ__##e)
+#define BFM_SSP_CTRL1_CEATA_CCS_ERR_IRQ_V(v)    BM_SSP_CTRL1_CEATA_CCS_ERR_IRQ
+#define BP_SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN       18
+#define BM_SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN       0x40000
+#define BF_SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN(v)    (((v) & 0x1) << 18)
+#define BFM_SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN(v)   BM_SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN
+#define BF_SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN_V(e)  BF_SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN(BV_SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN__##e)
+#define BFM_SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN_V(v) BM_SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN
+#define BP_SSP_CTRL1_RECV_TIMEOUT_IRQ           17
+#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ           0x20000
+#define BF_SSP_CTRL1_RECV_TIMEOUT_IRQ(v)        (((v) & 0x1) << 17)
+#define BFM_SSP_CTRL1_RECV_TIMEOUT_IRQ(v)       BM_SSP_CTRL1_RECV_TIMEOUT_IRQ
+#define BF_SSP_CTRL1_RECV_TIMEOUT_IRQ_V(e)      BF_SSP_CTRL1_RECV_TIMEOUT_IRQ(BV_SSP_CTRL1_RECV_TIMEOUT_IRQ__##e)
+#define BFM_SSP_CTRL1_RECV_TIMEOUT_IRQ_V(v)     BM_SSP_CTRL1_RECV_TIMEOUT_IRQ
+#define BP_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN        16
+#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN        0x10000
+#define BF_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN(v)     (((v) & 0x1) << 16)
+#define BFM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN(v)    BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN
+#define BF_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN_V(e)   BF_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN(BV_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN__##e)
+#define BFM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN_V(v)  BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN
+#define BP_SSP_CTRL1_FIFO_OVERRUN_IRQ           15
+#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ           0x8000
+#define BF_SSP_CTRL1_FIFO_OVERRUN_IRQ(v)        (((v) & 0x1) << 15)
+#define BFM_SSP_CTRL1_FIFO_OVERRUN_IRQ(v)       BM_SSP_CTRL1_FIFO_OVERRUN_IRQ
+#define BF_SSP_CTRL1_FIFO_OVERRUN_IRQ_V(e)      BF_SSP_CTRL1_FIFO_OVERRUN_IRQ(BV_SSP_CTRL1_FIFO_OVERRUN_IRQ__##e)
+#define BFM_SSP_CTRL1_FIFO_OVERRUN_IRQ_V(v)     BM_SSP_CTRL1_FIFO_OVERRUN_IRQ
+#define BP_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN        14
+#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN        0x4000
+#define BF_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN(v)     (((v) & 0x1) << 14)
+#define BFM_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN(v)    BM_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN
+#define BF_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN_V(e)   BF_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN(BV_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN__##e)
+#define BFM_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN_V(v)  BM_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN
+#define BP_SSP_CTRL1_DMA_ENABLE                 13
+#define BM_SSP_CTRL1_DMA_ENABLE                 0x2000
+#define BF_SSP_CTRL1_DMA_ENABLE(v)              (((v) & 0x1) << 13)
+#define BFM_SSP_CTRL1_DMA_ENABLE(v)             BM_SSP_CTRL1_DMA_ENABLE
+#define BF_SSP_CTRL1_DMA_ENABLE_V(e)            BF_SSP_CTRL1_DMA_ENABLE(BV_SSP_CTRL1_DMA_ENABLE__##e)
+#define BFM_SSP_CTRL1_DMA_ENABLE_V(v)           BM_SSP_CTRL1_DMA_ENABLE
+#define BP_SSP_CTRL1_CEATA_CCS_ERR_EN           12
+#define BM_SSP_CTRL1_CEATA_CCS_ERR_EN           0x1000
+#define BF_SSP_CTRL1_CEATA_CCS_ERR_EN(v)        (((v) & 0x1) << 12)
+#define BFM_SSP_CTRL1_CEATA_CCS_ERR_EN(v)       BM_SSP_CTRL1_CEATA_CCS_ERR_EN
+#define BF_SSP_CTRL1_CEATA_CCS_ERR_EN_V(e)      BF_SSP_CTRL1_CEATA_CCS_ERR_EN(BV_SSP_CTRL1_CEATA_CCS_ERR_EN__##e)
+#define BFM_SSP_CTRL1_CEATA_CCS_ERR_EN_V(v)     BM_SSP_CTRL1_CEATA_CCS_ERR_EN
+#define BP_SSP_CTRL1_SLAVE_OUT_DISABLE          11
+#define BM_SSP_CTRL1_SLAVE_OUT_DISABLE          0x800
+#define BF_SSP_CTRL1_SLAVE_OUT_DISABLE(v)       (((v) & 0x1) << 11)
+#define BFM_SSP_CTRL1_SLAVE_OUT_DISABLE(v)      BM_SSP_CTRL1_SLAVE_OUT_DISABLE
+#define BF_SSP_CTRL1_SLAVE_OUT_DISABLE_V(e)     BF_SSP_CTRL1_SLAVE_OUT_DISABLE(BV_SSP_CTRL1_SLAVE_OUT_DISABLE__##e)
+#define BFM_SSP_CTRL1_SLAVE_OUT_DISABLE_V(v)    BM_SSP_CTRL1_SLAVE_OUT_DISABLE
+#define BP_SSP_CTRL1_PHASE                      10
+#define BM_SSP_CTRL1_PHASE                      0x400
+#define BF_SSP_CTRL1_PHASE(v)                   (((v) & 0x1) << 10)
+#define BFM_SSP_CTRL1_PHASE(v)                  BM_SSP_CTRL1_PHASE
+#define BF_SSP_CTRL1_PHASE_V(e)                 BF_SSP_CTRL1_PHASE(BV_SSP_CTRL1_PHASE__##e)
+#define BFM_SSP_CTRL1_PHASE_V(v)                BM_SSP_CTRL1_PHASE
+#define BP_SSP_CTRL1_POLARITY                   9
+#define BM_SSP_CTRL1_POLARITY                   0x200
+#define BF_SSP_CTRL1_POLARITY(v)                (((v) & 0x1) << 9)
+#define BFM_SSP_CTRL1_POLARITY(v)               BM_SSP_CTRL1_POLARITY
+#define BF_SSP_CTRL1_POLARITY_V(e)              BF_SSP_CTRL1_POLARITY(BV_SSP_CTRL1_POLARITY__##e)
+#define BFM_SSP_CTRL1_POLARITY_V(v)             BM_SSP_CTRL1_POLARITY
+#define BP_SSP_CTRL1_SLAVE_MODE                 8
+#define BM_SSP_CTRL1_SLAVE_MODE                 0x100
+#define BF_SSP_CTRL1_SLAVE_MODE(v)              (((v) & 0x1) << 8)
+#define BFM_SSP_CTRL1_SLAVE_MODE(v)             BM_SSP_CTRL1_SLAVE_MODE
+#define BF_SSP_CTRL1_SLAVE_MODE_V(e)            BF_SSP_CTRL1_SLAVE_MODE(BV_SSP_CTRL1_SLAVE_MODE__##e)
+#define BFM_SSP_CTRL1_SLAVE_MODE_V(v)           BM_SSP_CTRL1_SLAVE_MODE
+#define BP_SSP_CTRL1_WORD_LENGTH                4
+#define BM_SSP_CTRL1_WORD_LENGTH                0xf0
+#define BV_SSP_CTRL1_WORD_LENGTH__RESERVED0     0x0
+#define BV_SSP_CTRL1_WORD_LENGTH__RESERVED1     0x1
+#define BV_SSP_CTRL1_WORD_LENGTH__RESERVED2     0x2
+#define BV_SSP_CTRL1_WORD_LENGTH__FOUR_BITS     0x3
+#define BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS    0x7
+#define BV_SSP_CTRL1_WORD_LENGTH__SIXTEEN_BITS  0xf
+#define BF_SSP_CTRL1_WORD_LENGTH(v)             (((v) & 0xf) << 4)
+#define BFM_SSP_CTRL1_WORD_LENGTH(v)            BM_SSP_CTRL1_WORD_LENGTH
+#define BF_SSP_CTRL1_WORD_LENGTH_V(e)           BF_SSP_CTRL1_WORD_LENGTH(BV_SSP_CTRL1_WORD_LENGTH__##e)
+#define BFM_SSP_CTRL1_WORD_LENGTH_V(v)          BM_SSP_CTRL1_WORD_LENGTH
+#define BP_SSP_CTRL1_SSP_MODE                   0
+#define BM_SSP_CTRL1_SSP_MODE                   0xf
+#define BV_SSP_CTRL1_SSP_MODE__SPI              0x0
+#define BV_SSP_CTRL1_SSP_MODE__SSI              0x1
+#define BV_SSP_CTRL1_SSP_MODE__SD_MMC           0x3
+#define BV_SSP_CTRL1_SSP_MODE__MS               0x4
+#define BV_SSP_CTRL1_SSP_MODE__CE_ATA           0x7
+#define BF_SSP_CTRL1_SSP_MODE(v)                (((v) & 0xf) << 0)
+#define BFM_SSP_CTRL1_SSP_MODE(v)               BM_SSP_CTRL1_SSP_MODE
+#define BF_SSP_CTRL1_SSP_MODE_V(e)              BF_SSP_CTRL1_SSP_MODE(BV_SSP_CTRL1_SSP_MODE__##e)
+#define BFM_SSP_CTRL1_SSP_MODE_V(v)             BM_SSP_CTRL1_SSP_MODE
+
+#define HW_SSP_DATA(_n1)        HW(SSP_DATA(_n1))
+#define HWA_SSP_DATA(_n1)       (((_n1) == 1 ? 0x80010000 : 0x80034000) + 0x70)
+#define HWT_SSP_DATA(_n1)       HWIO_32_RW
+#define HWN_SSP_DATA(_n1)       SSP_DATA
+#define HWI_SSP_DATA(_n1)       (_n1)
+#define BP_SSP_DATA_DATA        0
+#define BM_SSP_DATA_DATA        0xffffffff
+#define BF_SSP_DATA_DATA(v)     (((v) & 0xffffffff) << 0)
+#define BFM_SSP_DATA_DATA(v)    BM_SSP_DATA_DATA
+#define BF_SSP_DATA_DATA_V(e)   BF_SSP_DATA_DATA(BV_SSP_DATA_DATA__##e)
+#define BFM_SSP_DATA_DATA_V(v)  BM_SSP_DATA_DATA
+
+#define HW_SSP_SDRESP0(_n1)         HW(SSP_SDRESP0(_n1))
+#define HWA_SSP_SDRESP0(_n1)        (((_n1) == 1 ? 0x80010000 : 0x80034000) + 0x80)
+#define HWT_SSP_SDRESP0(_n1)        HWIO_32_RW
+#define HWN_SSP_SDRESP0(_n1)        SSP_SDRESP0
+#define HWI_SSP_SDRESP0(_n1)        (_n1)
+#define BP_SSP_SDRESP0_RESP0        0
+#define BM_SSP_SDRESP0_RESP0        0xffffffff
+#define BF_SSP_SDRESP0_RESP0(v)     (((v) & 0xffffffff) << 0)
+#define BFM_SSP_SDRESP0_RESP0(v)    BM_SSP_SDRESP0_RESP0
+#define BF_SSP_SDRESP0_RESP0_V(e)   BF_SSP_SDRESP0_RESP0(BV_SSP_SDRESP0_RESP0__##e)
+#define BFM_SSP_SDRESP0_RESP0_V(v)  BM_SSP_SDRESP0_RESP0
+
+#define HW_SSP_SDRESP1(_n1)         HW(SSP_SDRESP1(_n1))
+#define HWA_SSP_SDRESP1(_n1)        (((_n1) == 1 ? 0x80010000 : 0x80034000) + 0x90)
+#define HWT_SSP_SDRESP1(_n1)        HWIO_32_RW
+#define HWN_SSP_SDRESP1(_n1)        SSP_SDRESP1
+#define HWI_SSP_SDRESP1(_n1)        (_n1)
+#define BP_SSP_SDRESP1_RESP1        0
+#define BM_SSP_SDRESP1_RESP1        0xffffffff
+#define BF_SSP_SDRESP1_RESP1(v)     (((v) & 0xffffffff) << 0)
+#define BFM_SSP_SDRESP1_RESP1(v)    BM_SSP_SDRESP1_RESP1
+#define BF_SSP_SDRESP1_RESP1_V(e)   BF_SSP_SDRESP1_RESP1(BV_SSP_SDRESP1_RESP1__##e)
+#define BFM_SSP_SDRESP1_RESP1_V(v)  BM_SSP_SDRESP1_RESP1
+
+#define HW_SSP_SDRESP2(_n1)         HW(SSP_SDRESP2(_n1))
+#define HWA_SSP_SDRESP2(_n1)        (((_n1) == 1 ? 0x80010000 : 0x80034000) + 0xa0)
+#define HWT_SSP_SDRESP2(_n1)        HWIO_32_RW
+#define HWN_SSP_SDRESP2(_n1)        SSP_SDRESP2
+#define HWI_SSP_SDRESP2(_n1)        (_n1)
+#define BP_SSP_SDRESP2_RESP2        0
+#define BM_SSP_SDRESP2_RESP2        0xffffffff
+#define BF_SSP_SDRESP2_RESP2(v)     (((v) & 0xffffffff) << 0)
+#define BFM_SSP_SDRESP2_RESP2(v)    BM_SSP_SDRESP2_RESP2
+#define BF_SSP_SDRESP2_RESP2_V(e)   BF_SSP_SDRESP2_RESP2(BV_SSP_SDRESP2_RESP2__##e)
+#define BFM_SSP_SDRESP2_RESP2_V(v)  BM_SSP_SDRESP2_RESP2
+
+#define HW_SSP_SDRESP3(_n1)         HW(SSP_SDRESP3(_n1))
+#define HWA_SSP_SDRESP3(_n1)        (((_n1) == 1 ? 0x80010000 : 0x80034000) + 0xb0)
+#define HWT_SSP_SDRESP3(_n1)        HWIO_32_RW
+#define HWN_SSP_SDRESP3(_n1)        SSP_SDRESP3
+#define HWI_SSP_SDRESP3(_n1)        (_n1)
+#define BP_SSP_SDRESP3_RESP3        0
+#define BM_SSP_SDRESP3_RESP3        0xffffffff
+#define BF_SSP_SDRESP3_RESP3(v)     (((v) & 0xffffffff) << 0)
+#define BFM_SSP_SDRESP3_RESP3(v)    BM_SSP_SDRESP3_RESP3
+#define BF_SSP_SDRESP3_RESP3_V(e)   BF_SSP_SDRESP3_RESP3(BV_SSP_SDRESP3_RESP3__##e)
+#define BFM_SSP_SDRESP3_RESP3_V(v)  BM_SSP_SDRESP3_RESP3
+
+#define HW_SSP_STATUS(_n1)                      HW(SSP_STATUS(_n1))
+#define HWA_SSP_STATUS(_n1)                     (((_n1) == 1 ? 0x80010000 : 0x80034000) + 0xc0)
+#define HWT_SSP_STATUS(_n1)                     HWIO_32_RW
+#define HWN_SSP_STATUS(_n1)                     SSP_STATUS
+#define HWI_SSP_STATUS(_n1)                     (_n1)
+#define BP_SSP_STATUS_PRESENT                   31
+#define BM_SSP_STATUS_PRESENT                   0x80000000
+#define BF_SSP_STATUS_PRESENT(v)                (((v) & 0x1) << 31)
+#define BFM_SSP_STATUS_PRESENT(v)               BM_SSP_STATUS_PRESENT
+#define BF_SSP_STATUS_PRESENT_V(e)              BF_SSP_STATUS_PRESENT(BV_SSP_STATUS_PRESENT__##e)
+#define BFM_SSP_STATUS_PRESENT_V(v)             BM_SSP_STATUS_PRESENT
+#define BP_SSP_STATUS_MS_PRESENT                30
+#define BM_SSP_STATUS_MS_PRESENT                0x40000000
+#define BF_SSP_STATUS_MS_PRESENT(v)             (((v) & 0x1) << 30)
+#define BFM_SSP_STATUS_MS_PRESENT(v)            BM_SSP_STATUS_MS_PRESENT
+#define BF_SSP_STATUS_MS_PRESENT_V(e)           BF_SSP_STATUS_MS_PRESENT(BV_SSP_STATUS_MS_PRESENT__##e)
+#define BFM_SSP_STATUS_MS_PRESENT_V(v)          BM_SSP_STATUS_MS_PRESENT
+#define BP_SSP_STATUS_SD_PRESENT                29
+#define BM_SSP_STATUS_SD_PRESENT                0x20000000
+#define BF_SSP_STATUS_SD_PRESENT(v)             (((v) & 0x1) << 29)
+#define BFM_SSP_STATUS_SD_PRESENT(v)            BM_SSP_STATUS_SD_PRESENT
+#define BF_SSP_STATUS_SD_PRESENT_V(e)           BF_SSP_STATUS_SD_PRESENT(BV_SSP_STATUS_SD_PRESENT__##e)
+#define BFM_SSP_STATUS_SD_PRESENT_V(v)          BM_SSP_STATUS_SD_PRESENT
+#define BP_SSP_STATUS_CARD_DETECT               28
+#define BM_SSP_STATUS_CARD_DETECT               0x10000000
+#define BF_SSP_STATUS_CARD_DETECT(v)            (((v) & 0x1) << 28)
+#define BFM_SSP_STATUS_CARD_DETECT(v)           BM_SSP_STATUS_CARD_DETECT
+#define BF_SSP_STATUS_CARD_DETECT_V(e)          BF_SSP_STATUS_CARD_DETECT(BV_SSP_STATUS_CARD_DETECT__##e)
+#define BFM_SSP_STATUS_CARD_DETECT_V(v)         BM_SSP_STATUS_CARD_DETECT
+#define BP_SSP_STATUS_RSVD3                     22
+#define BM_SSP_STATUS_RSVD3                     0xfc00000
+#define BF_SSP_STATUS_RSVD3(v)                  (((v) & 0x3f) << 22)
+#define BFM_SSP_STATUS_RSVD3(v)                 BM_SSP_STATUS_RSVD3
+#define BF_SSP_STATUS_RSVD3_V(e)                BF_SSP_STATUS_RSVD3(BV_SSP_STATUS_RSVD3__##e)
+#define BFM_SSP_STATUS_RSVD3_V(v)               BM_SSP_STATUS_RSVD3
+#define BP_SSP_STATUS_DMASENSE                  21
+#define BM_SSP_STATUS_DMASENSE                  0x200000
+#define BF_SSP_STATUS_DMASENSE(v)               (((v) & 0x1) << 21)
+#define BFM_SSP_STATUS_DMASENSE(v)              BM_SSP_STATUS_DMASENSE
+#define BF_SSP_STATUS_DMASENSE_V(e)             BF_SSP_STATUS_DMASENSE(BV_SSP_STATUS_DMASENSE__##e)
+#define BFM_SSP_STATUS_DMASENSE_V(v)            BM_SSP_STATUS_DMASENSE
+#define BP_SSP_STATUS_DMATERM                   20
+#define BM_SSP_STATUS_DMATERM                   0x100000
+#define BF_SSP_STATUS_DMATERM(v)                (((v) & 0x1) << 20)
+#define BFM_SSP_STATUS_DMATERM(v)               BM_SSP_STATUS_DMATERM
+#define BF_SSP_STATUS_DMATERM_V(e)              BF_SSP_STATUS_DMATERM(BV_SSP_STATUS_DMATERM__##e)
+#define BFM_SSP_STATUS_DMATERM_V(v)             BM_SSP_STATUS_DMATERM
+#define BP_SSP_STATUS_DMAREQ                    19
+#define BM_SSP_STATUS_DMAREQ                    0x80000
+#define BF_SSP_STATUS_DMAREQ(v)                 (((v) & 0x1) << 19)
+#define BFM_SSP_STATUS_DMAREQ(v)                BM_SSP_STATUS_DMAREQ
+#define BF_SSP_STATUS_DMAREQ_V(e)               BF_SSP_STATUS_DMAREQ(BV_SSP_STATUS_DMAREQ__##e)
+#define BFM_SSP_STATUS_DMAREQ_V(v)              BM_SSP_STATUS_DMAREQ
+#define BP_SSP_STATUS_DMAEND                    18
+#define BM_SSP_STATUS_DMAEND                    0x40000
+#define BF_SSP_STATUS_DMAEND(v)                 (((v) & 0x1) << 18)
+#define BFM_SSP_STATUS_DMAEND(v)                BM_SSP_STATUS_DMAEND
+#define BF_SSP_STATUS_DMAEND_V(e)               BF_SSP_STATUS_DMAEND(BV_SSP_STATUS_DMAEND__##e)
+#define BFM_SSP_STATUS_DMAEND_V(v)              BM_SSP_STATUS_DMAEND
+#define BP_SSP_STATUS_SDIO_IRQ                  17
+#define BM_SSP_STATUS_SDIO_IRQ                  0x20000
+#define BF_SSP_STATUS_SDIO_IRQ(v)               (((v) & 0x1) << 17)
+#define BFM_SSP_STATUS_SDIO_IRQ(v)              BM_SSP_STATUS_SDIO_IRQ
+#define BF_SSP_STATUS_SDIO_IRQ_V(e)             BF_SSP_STATUS_SDIO_IRQ(BV_SSP_STATUS_SDIO_IRQ__##e)
+#define BFM_SSP_STATUS_SDIO_IRQ_V(v)            BM_SSP_STATUS_SDIO_IRQ
+#define BP_SSP_STATUS_RESP_CRC_ERR              16
+#define BM_SSP_STATUS_RESP_CRC_ERR              0x10000
+#define BF_SSP_STATUS_RESP_CRC_ERR(v)           (((v) & 0x1) << 16)
+#define BFM_SSP_STATUS_RESP_CRC_ERR(v)          BM_SSP_STATUS_RESP_CRC_ERR
+#define BF_SSP_STATUS_RESP_CRC_ERR_V(e)         BF_SSP_STATUS_RESP_CRC_ERR(BV_SSP_STATUS_RESP_CRC_ERR__##e)
+#define BFM_SSP_STATUS_RESP_CRC_ERR_V(v)        BM_SSP_STATUS_RESP_CRC_ERR
+#define BP_SSP_STATUS_RESP_ERR                  15
+#define BM_SSP_STATUS_RESP_ERR                  0x8000
+#define BF_SSP_STATUS_RESP_ERR(v)               (((v) & 0x1) << 15)
+#define BFM_SSP_STATUS_RESP_ERR(v)              BM_SSP_STATUS_RESP_ERR
+#define BF_SSP_STATUS_RESP_ERR_V(e)             BF_SSP_STATUS_RESP_ERR(BV_SSP_STATUS_RESP_ERR__##e)
+#define BFM_SSP_STATUS_RESP_ERR_V(v)            BM_SSP_STATUS_RESP_ERR
+#define BP_SSP_STATUS_RESP_TIMEOUT              14
+#define BM_SSP_STATUS_RESP_TIMEOUT              0x4000
+#define BF_SSP_STATUS_RESP_TIMEOUT(v)           (((v) & 0x1) << 14)
+#define BFM_SSP_STATUS_RESP_TIMEOUT(v)          BM_SSP_STATUS_RESP_TIMEOUT
+#define BF_SSP_STATUS_RESP_TIMEOUT_V(e)         BF_SSP_STATUS_RESP_TIMEOUT(BV_SSP_STATUS_RESP_TIMEOUT__##e)
+#define BFM_SSP_STATUS_RESP_TIMEOUT_V(v)        BM_SSP_STATUS_RESP_TIMEOUT
+#define BP_SSP_STATUS_DATA_CRC_ERR              13
+#define BM_SSP_STATUS_DATA_CRC_ERR              0x2000
+#define BF_SSP_STATUS_DATA_CRC_ERR(v)           (((v) & 0x1) << 13)
+#define BFM_SSP_STATUS_DATA_CRC_ERR(v)          BM_SSP_STATUS_DATA_CRC_ERR
+#define BF_SSP_STATUS_DATA_CRC_ERR_V(e)         BF_SSP_STATUS_DATA_CRC_ERR(BV_SSP_STATUS_DATA_CRC_ERR__##e)
+#define BFM_SSP_STATUS_DATA_CRC_ERR_V(v)        BM_SSP_STATUS_DATA_CRC_ERR
+#define BP_SSP_STATUS_TIMEOUT                   12
+#define BM_SSP_STATUS_TIMEOUT                   0x1000
+#define BF_SSP_STATUS_TIMEOUT(v)                (((v) & 0x1) << 12)
+#define BFM_SSP_STATUS_TIMEOUT(v)               BM_SSP_STATUS_TIMEOUT
+#define BF_SSP_STATUS_TIMEOUT_V(e)              BF_SSP_STATUS_TIMEOUT(BV_SSP_STATUS_TIMEOUT__##e)
+#define BFM_SSP_STATUS_TIMEOUT_V(v)             BM_SSP_STATUS_TIMEOUT
+#define BP_SSP_STATUS_RECV_TIMEOUT_STAT         11
+#define BM_SSP_STATUS_RECV_TIMEOUT_STAT         0x800
+#define BF_SSP_STATUS_RECV_TIMEOUT_STAT(v)      (((v) & 0x1) << 11)
+#define BFM_SSP_STATUS_RECV_TIMEOUT_STAT(v)     BM_SSP_STATUS_RECV_TIMEOUT_STAT
+#define BF_SSP_STATUS_RECV_TIMEOUT_STAT_V(e)    BF_SSP_STATUS_RECV_TIMEOUT_STAT(BV_SSP_STATUS_RECV_TIMEOUT_STAT__##e)
+#define BFM_SSP_STATUS_RECV_TIMEOUT_STAT_V(v)   BM_SSP_STATUS_RECV_TIMEOUT_STAT
+#define BP_SSP_STATUS_CEATA_CCS_ERR             10
+#define BM_SSP_STATUS_CEATA_CCS_ERR             0x400
+#define BF_SSP_STATUS_CEATA_CCS_ERR(v)          (((v) & 0x1) << 10)
+#define BFM_SSP_STATUS_CEATA_CCS_ERR(v)         BM_SSP_STATUS_CEATA_CCS_ERR
+#define BF_SSP_STATUS_CEATA_CCS_ERR_V(e)        BF_SSP_STATUS_CEATA_CCS_ERR(BV_SSP_STATUS_CEATA_CCS_ERR__##e)
+#define BFM_SSP_STATUS_CEATA_CCS_ERR_V(v)       BM_SSP_STATUS_CEATA_CCS_ERR
+#define BP_SSP_STATUS_FIFO_OVRFLW               9
+#define BM_SSP_STATUS_FIFO_OVRFLW               0x200
+#define BF_SSP_STATUS_FIFO_OVRFLW(v)            (((v) & 0x1) << 9)
+#define BFM_SSP_STATUS_FIFO_OVRFLW(v)           BM_SSP_STATUS_FIFO_OVRFLW
+#define BF_SSP_STATUS_FIFO_OVRFLW_V(e)          BF_SSP_STATUS_FIFO_OVRFLW(BV_SSP_STATUS_FIFO_OVRFLW__##e)
+#define BFM_SSP_STATUS_FIFO_OVRFLW_V(v)         BM_SSP_STATUS_FIFO_OVRFLW
+#define BP_SSP_STATUS_FIFO_FULL                 8
+#define BM_SSP_STATUS_FIFO_FULL                 0x100
+#define BF_SSP_STATUS_FIFO_FULL(v)              (((v) & 0x1) << 8)
+#define BFM_SSP_STATUS_FIFO_FULL(v)             BM_SSP_STATUS_FIFO_FULL
+#define BF_SSP_STATUS_FIFO_FULL_V(e)            BF_SSP_STATUS_FIFO_FULL(BV_SSP_STATUS_FIFO_FULL__##e)
+#define BFM_SSP_STATUS_FIFO_FULL_V(v)           BM_SSP_STATUS_FIFO_FULL
+#define BP_SSP_STATUS_RSVD1                     6
+#define BM_SSP_STATUS_RSVD1                     0xc0
+#define BF_SSP_STATUS_RSVD1(v)                  (((v) & 0x3) << 6)
+#define BFM_SSP_STATUS_RSVD1(v)                 BM_SSP_STATUS_RSVD1
+#define BF_SSP_STATUS_RSVD1_V(e)                BF_SSP_STATUS_RSVD1(BV_SSP_STATUS_RSVD1__##e)
+#define BFM_SSP_STATUS_RSVD1_V(v)               BM_SSP_STATUS_RSVD1
+#define BP_SSP_STATUS_FIFO_EMPTY                5
+#define BM_SSP_STATUS_FIFO_EMPTY                0x20
+#define BF_SSP_STATUS_FIFO_EMPTY(v)             (((v) & 0x1) << 5)
+#define BFM_SSP_STATUS_FIFO_EMPTY(v)            BM_SSP_STATUS_FIFO_EMPTY
+#define BF_SSP_STATUS_FIFO_EMPTY_V(e)           BF_SSP_STATUS_FIFO_EMPTY(BV_SSP_STATUS_FIFO_EMPTY__##e)
+#define BFM_SSP_STATUS_FIFO_EMPTY_V(v)          BM_SSP_STATUS_FIFO_EMPTY
+#define BP_SSP_STATUS_FIFO_UNDRFLW              4
+#define BM_SSP_STATUS_FIFO_UNDRFLW              0x10
+#define BF_SSP_STATUS_FIFO_UNDRFLW(v)           (((v) & 0x1) << 4)
+#define BFM_SSP_STATUS_FIFO_UNDRFLW(v)          BM_SSP_STATUS_FIFO_UNDRFLW
+#define BF_SSP_STATUS_FIFO_UNDRFLW_V(e)         BF_SSP_STATUS_FIFO_UNDRFLW(BV_SSP_STATUS_FIFO_UNDRFLW__##e)
+#define BFM_SSP_STATUS_FIFO_UNDRFLW_V(v)        BM_SSP_STATUS_FIFO_UNDRFLW
+#define BP_SSP_STATUS_CMD_BUSY                  3
+#define BM_SSP_STATUS_CMD_BUSY                  0x8
+#define BF_SSP_STATUS_CMD_BUSY(v)               (((v) & 0x1) << 3)
+#define BFM_SSP_STATUS_CMD_BUSY(v)              BM_SSP_STATUS_CMD_BUSY
+#define BF_SSP_STATUS_CMD_BUSY_V(e)             BF_SSP_STATUS_CMD_BUSY(BV_SSP_STATUS_CMD_BUSY__##e)
+#define BFM_SSP_STATUS_CMD_BUSY_V(v)            BM_SSP_STATUS_CMD_BUSY
+#define BP_SSP_STATUS_DATA_BUSY                 2
+#define BM_SSP_STATUS_DATA_BUSY                 0x4
+#define BF_SSP_STATUS_DATA_BUSY(v)              (((v) & 0x1) << 2)
+#define BFM_SSP_STATUS_DATA_BUSY(v)             BM_SSP_STATUS_DATA_BUSY
+#define BF_SSP_STATUS_DATA_BUSY_V(e)            BF_SSP_STATUS_DATA_BUSY(BV_SSP_STATUS_DATA_BUSY__##e)
+#define BFM_SSP_STATUS_DATA_BUSY_V(v)           BM_SSP_STATUS_DATA_BUSY
+#define BP_SSP_STATUS_RSVD0                     1
+#define BM_SSP_STATUS_RSVD0                     0x2
+#define BF_SSP_STATUS_RSVD0(v)                  (((v) & 0x1) << 1)
+#define BFM_SSP_STATUS_RSVD0(v)                 BM_SSP_STATUS_RSVD0
+#define BF_SSP_STATUS_RSVD0_V(e)                BF_SSP_STATUS_RSVD0(BV_SSP_STATUS_RSVD0__##e)
+#define BFM_SSP_STATUS_RSVD0_V(v)               BM_SSP_STATUS_RSVD0
+#define BP_SSP_STATUS_BUSY                      0
+#define BM_SSP_STATUS_BUSY                      0x1
+#define BF_SSP_STATUS_BUSY(v)                   (((v) & 0x1) << 0)
+#define BFM_SSP_STATUS_BUSY(v)                  BM_SSP_STATUS_BUSY
+#define BF_SSP_STATUS_BUSY_V(e)                 BF_SSP_STATUS_BUSY(BV_SSP_STATUS_BUSY__##e)
+#define BFM_SSP_STATUS_BUSY_V(v)                BM_SSP_STATUS_BUSY
+
+#define HW_SSP_DEBUG(_n1)                   HW(SSP_DEBUG(_n1))
+#define HWA_SSP_DEBUG(_n1)                  (((_n1) == 1 ? 0x80010000 : 0x80034000) + 0x100)
+#define HWT_SSP_DEBUG(_n1)                  HWIO_32_RW
+#define HWN_SSP_DEBUG(_n1)                  SSP_DEBUG
+#define HWI_SSP_DEBUG(_n1)                  (_n1)
+#define BP_SSP_DEBUG_DATACRC_ERR            28
+#define BM_SSP_DEBUG_DATACRC_ERR            0xf0000000
+#define BF_SSP_DEBUG_DATACRC_ERR(v)         (((v) & 0xf) << 28)
+#define BFM_SSP_DEBUG_DATACRC_ERR(v)        BM_SSP_DEBUG_DATACRC_ERR
+#define BF_SSP_DEBUG_DATACRC_ERR_V(e)       BF_SSP_DEBUG_DATACRC_ERR(BV_SSP_DEBUG_DATACRC_ERR__##e)
+#define BFM_SSP_DEBUG_DATACRC_ERR_V(v)      BM_SSP_DEBUG_DATACRC_ERR
+#define BP_SSP_DEBUG_DATA_STALL             27
+#define BM_SSP_DEBUG_DATA_STALL             0x8000000
+#define BF_SSP_DEBUG_DATA_STALL(v)          (((v) & 0x1) << 27)
+#define BFM_SSP_DEBUG_DATA_STALL(v)         BM_SSP_DEBUG_DATA_STALL
+#define BF_SSP_DEBUG_DATA_STALL_V(e)        BF_SSP_DEBUG_DATA_STALL(BV_SSP_DEBUG_DATA_STALL__##e)
+#define BFM_SSP_DEBUG_DATA_STALL_V(v)       BM_SSP_DEBUG_DATA_STALL
+#define BP_SSP_DEBUG_DAT_SM                 24
+#define BM_SSP_DEBUG_DAT_SM                 0x7000000
+#define BV_SSP_DEBUG_DAT_SM__DSM_IDLE       0x0
+#define BV_SSP_DEBUG_DAT_SM__DSM_WORD       0x2
+#define BV_SSP_DEBUG_DAT_SM__DSM_CRC1       0x3
+#define BV_SSP_DEBUG_DAT_SM__DSM_CRC2       0x4
+#define BV_SSP_DEBUG_DAT_SM__DSM_END        0x5
+#define BF_SSP_DEBUG_DAT_SM(v)              (((v) & 0x7) << 24)
+#define BFM_SSP_DEBUG_DAT_SM(v)             BM_SSP_DEBUG_DAT_SM
+#define BF_SSP_DEBUG_DAT_SM_V(e)            BF_SSP_DEBUG_DAT_SM(BV_SSP_DEBUG_DAT_SM__##e)
+#define BFM_SSP_DEBUG_DAT_SM_V(v)           BM_SSP_DEBUG_DAT_SM
+#define BP_SSP_DEBUG_MSTK_SM                20
+#define BM_SSP_DEBUG_MSTK_SM                0xf00000
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_IDLE     0x0
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_CKON     0x1
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS1      0x2
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_TPC      0x3
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS2      0x4
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_HDSHK    0x5
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS3      0x6
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_RW       0x7
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_CRC1     0x8
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_CRC2     0x9
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS0      0xa
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_END1     0xb
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_END2W    0xc
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_END2R    0xd
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_DONE     0xe
+#define BF_SSP_DEBUG_MSTK_SM(v)             (((v) & 0xf) << 20)
+#define BFM_SSP_DEBUG_MSTK_SM(v)            BM_SSP_DEBUG_MSTK_SM
+#define BF_SSP_DEBUG_MSTK_SM_V(e)           BF_SSP_DEBUG_MSTK_SM(BV_SSP_DEBUG_MSTK_SM__##e)
+#define BFM_SSP_DEBUG_MSTK_SM_V(v)          BM_SSP_DEBUG_MSTK_SM
+#define BP_SSP_DEBUG_CMD_OE                 19
+#define BM_SSP_DEBUG_CMD_OE                 0x80000
+#define BF_SSP_DEBUG_CMD_OE(v)              (((v) & 0x1) << 19)
+#define BFM_SSP_DEBUG_CMD_OE(v)             BM_SSP_DEBUG_CMD_OE
+#define BF_SSP_DEBUG_CMD_OE_V(e)            BF_SSP_DEBUG_CMD_OE(BV_SSP_DEBUG_CMD_OE__##e)
+#define BFM_SSP_DEBUG_CMD_OE_V(v)           BM_SSP_DEBUG_CMD_OE
+#define BP_SSP_DEBUG_DMA_SM                 16
+#define BM_SSP_DEBUG_DMA_SM                 0x70000
+#define BV_SSP_DEBUG_DMA_SM__DMA_IDLE       0x0
+#define BV_SSP_DEBUG_DMA_SM__DMA_DMAREQ     0x1
+#define BV_SSP_DEBUG_DMA_SM__DMA_DMAACK     0x2
+#define BV_SSP_DEBUG_DMA_SM__DMA_STALL      0x3
+#define BV_SSP_DEBUG_DMA_SM__DMA_BUSY       0x4
+#define BV_SSP_DEBUG_DMA_SM__DMA_DONE       0x5
+#define BV_SSP_DEBUG_DMA_SM__DMA_COUNT      0x6
+#define BF_SSP_DEBUG_DMA_SM(v)              (((v) & 0x7) << 16)
+#define BFM_SSP_DEBUG_DMA_SM(v)             BM_SSP_DEBUG_DMA_SM
+#define BF_SSP_DEBUG_DMA_SM_V(e)            BF_SSP_DEBUG_DMA_SM(BV_SSP_DEBUG_DMA_SM__##e)
+#define BFM_SSP_DEBUG_DMA_SM_V(v)           BM_SSP_DEBUG_DMA_SM
+#define BP_SSP_DEBUG_MMC_SM                 12
+#define BM_SSP_DEBUG_MMC_SM                 0xf000
+#define BV_SSP_DEBUG_MMC_SM__MMC_IDLE       0x0
+#define BV_SSP_DEBUG_MMC_SM__MMC_CMD        0x1
+#define BV_SSP_DEBUG_MMC_SM__MMC_TRC        0x2
+#define BV_SSP_DEBUG_MMC_SM__MMC_RESP       0x3
+#define BV_SSP_DEBUG_MMC_SM__MMC_RPRX       0x4
+#define BV_SSP_DEBUG_MMC_SM__MMC_TX         0x5
+#define BV_SSP_DEBUG_MMC_SM__MMC_CTOK       0x6
+#define BV_SSP_DEBUG_MMC_SM__MMC_RX         0x7
+#define BV_SSP_DEBUG_MMC_SM__MMC_CCS        0x8
+#define BV_SSP_DEBUG_MMC_SM__MMC_PUP        0x9
+#define BV_SSP_DEBUG_MMC_SM__MMC_WAIT       0xa
+#define BF_SSP_DEBUG_MMC_SM(v)              (((v) & 0xf) << 12)
+#define BFM_SSP_DEBUG_MMC_SM(v)             BM_SSP_DEBUG_MMC_SM
+#define BF_SSP_DEBUG_MMC_SM_V(e)            BF_SSP_DEBUG_MMC_SM(BV_SSP_DEBUG_MMC_SM__##e)
+#define BFM_SSP_DEBUG_MMC_SM_V(v)           BM_SSP_DEBUG_MMC_SM
+#define BP_SSP_DEBUG_CMD_SM                 10
+#define BM_SSP_DEBUG_CMD_SM                 0xc00
+#define BV_SSP_DEBUG_CMD_SM__CSM_IDLE       0x0
+#define BV_SSP_DEBUG_CMD_SM__CSM_INDEX      0x1
+#define BV_SSP_DEBUG_CMD_SM__CSM_ARG        0x2
+#define BV_SSP_DEBUG_CMD_SM__CSM_CRC        0x3
+#define BF_SSP_DEBUG_CMD_SM(v)              (((v) & 0x3) << 10)
+#define BFM_SSP_DEBUG_CMD_SM(v)             BM_SSP_DEBUG_CMD_SM
+#define BF_SSP_DEBUG_CMD_SM_V(e)            BF_SSP_DEBUG_CMD_SM(BV_SSP_DEBUG_CMD_SM__##e)
+#define BFM_SSP_DEBUG_CMD_SM_V(v)           BM_SSP_DEBUG_CMD_SM
+#define BP_SSP_DEBUG_SSP_CMD                9
+#define BM_SSP_DEBUG_SSP_CMD                0x200
+#define BF_SSP_DEBUG_SSP_CMD(v)             (((v) & 0x1) << 9)
+#define BFM_SSP_DEBUG_SSP_CMD(v)            BM_SSP_DEBUG_SSP_CMD
+#define BF_SSP_DEBUG_SSP_CMD_V(e)           BF_SSP_DEBUG_SSP_CMD(BV_SSP_DEBUG_SSP_CMD__##e)
+#define BFM_SSP_DEBUG_SSP_CMD_V(v)          BM_SSP_DEBUG_SSP_CMD
+#define BP_SSP_DEBUG_SSP_RESP               8
+#define BM_SSP_DEBUG_SSP_RESP               0x100
+#define BF_SSP_DEBUG_SSP_RESP(v)            (((v) & 0x1) << 8)
+#define BFM_SSP_DEBUG_SSP_RESP(v)           BM_SSP_DEBUG_SSP_RESP
+#define BF_SSP_DEBUG_SSP_RESP_V(e)          BF_SSP_DEBUG_SSP_RESP(BV_SSP_DEBUG_SSP_RESP__##e)
+#define BFM_SSP_DEBUG_SSP_RESP_V(v)         BM_SSP_DEBUG_SSP_RESP
+#define BP_SSP_DEBUG_SSP_RXD                0
+#define BM_SSP_DEBUG_SSP_RXD                0xff
+#define BF_SSP_DEBUG_SSP_RXD(v)             (((v) & 0xff) << 0)
+#define BFM_SSP_DEBUG_SSP_RXD(v)            BM_SSP_DEBUG_SSP_RXD
+#define BF_SSP_DEBUG_SSP_RXD_V(e)           BF_SSP_DEBUG_SSP_RXD(BV_SSP_DEBUG_SSP_RXD__##e)
+#define BFM_SSP_DEBUG_SSP_RXD_V(v)          BM_SSP_DEBUG_SSP_RXD
+
+#define HW_SSP_VERSION(_n1)         HW(SSP_VERSION(_n1))
+#define HWA_SSP_VERSION(_n1)        (((_n1) == 1 ? 0x80010000 : 0x80034000) + 0x110)
+#define HWT_SSP_VERSION(_n1)        HWIO_32_RW
+#define HWN_SSP_VERSION(_n1)        SSP_VERSION
+#define HWI_SSP_VERSION(_n1)        (_n1)
+#define BP_SSP_VERSION_MAJOR        24
+#define BM_SSP_VERSION_MAJOR        0xff000000
+#define BF_SSP_VERSION_MAJOR(v)     (((v) & 0xff) << 24)
+#define BFM_SSP_VERSION_MAJOR(v)    BM_SSP_VERSION_MAJOR
+#define BF_SSP_VERSION_MAJOR_V(e)   BF_SSP_VERSION_MAJOR(BV_SSP_VERSION_MAJOR__##e)
+#define BFM_SSP_VERSION_MAJOR_V(v)  BM_SSP_VERSION_MAJOR
+#define BP_SSP_VERSION_MINOR        16
+#define BM_SSP_VERSION_MINOR        0xff0000
+#define BF_SSP_VERSION_MINOR(v)     (((v) & 0xff) << 16)
+#define BFM_SSP_VERSION_MINOR(v)    BM_SSP_VERSION_MINOR
+#define BF_SSP_VERSION_MINOR_V(e)   BF_SSP_VERSION_MINOR(BV_SSP_VERSION_MINOR__##e)
+#define BFM_SSP_VERSION_MINOR_V(v)  BM_SSP_VERSION_MINOR
+#define BP_SSP_VERSION_STEP         0
+#define BM_SSP_VERSION_STEP         0xffff
+#define BF_SSP_VERSION_STEP(v)      (((v) & 0xffff) << 0)
+#define BFM_SSP_VERSION_STEP(v)     BM_SSP_VERSION_STEP
+#define BF_SSP_VERSION_STEP_V(e)    BF_SSP_VERSION_STEP(BV_SSP_VERSION_STEP__##e)
+#define BFM_SSP_VERSION_STEP_V(v)   BM_SSP_VERSION_STEP
+
+#endif /* __HEADERGEN_IMX233_SSP_H__*/
diff --git a/firmware/target/arm/imx233/regs/imx233/sydma.h b/firmware/target/arm/imx233/regs/imx233/sydma.h
new file mode 100644
index 0000000000..6d5e94e247
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/imx233/sydma.h
@@ -0,0 +1,256 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * imx233 version: 2.4.0
+ * imx233 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_IMX233_SYDMA_H__
+#define __HEADERGEN_IMX233_SYDMA_H__
+
+#define HW_SYDMA_CTRL                           HW(SYDMA_CTRL)
+#define HWA_SYDMA_CTRL                          (0x80026000 + 0x0)
+#define HWT_SYDMA_CTRL                          HWIO_32_RW
+#define HWN_SYDMA_CTRL                          SYDMA_CTRL
+#define HWI_SYDMA_CTRL                          
+#define HW_SYDMA_CTRL_SET                       HW(SYDMA_CTRL_SET)
+#define HWA_SYDMA_CTRL_SET                      (HWA_SYDMA_CTRL + 0x4)
+#define HWT_SYDMA_CTRL_SET                      HWIO_32_WO
+#define HWN_SYDMA_CTRL_SET                      SYDMA_CTRL
+#define HWI_SYDMA_CTRL_SET                      
+#define HW_SYDMA_CTRL_CLR                       HW(SYDMA_CTRL_CLR)
+#define HWA_SYDMA_CTRL_CLR                      (HWA_SYDMA_CTRL + 0x8)
+#define HWT_SYDMA_CTRL_CLR                      HWIO_32_WO
+#define HWN_SYDMA_CTRL_CLR                      SYDMA_CTRL
+#define HWI_SYDMA_CTRL_CLR                      
+#define HW_SYDMA_CTRL_TOG                       HW(SYDMA_CTRL_TOG)
+#define HWA_SYDMA_CTRL_TOG                      (HWA_SYDMA_CTRL + 0xc)
+#define HWT_SYDMA_CTRL_TOG                      HWIO_32_WO
+#define HWN_SYDMA_CTRL_TOG                      SYDMA_CTRL
+#define HWI_SYDMA_CTRL_TOG                      
+#define BP_SYDMA_CTRL_SFTRST                    31
+#define BM_SYDMA_CTRL_SFTRST                    0x80000000
+#define BV_SYDMA_CTRL_SFTRST__RUN               0x0
+#define BV_SYDMA_CTRL_SFTRST__RESET             0x1
+#define BF_SYDMA_CTRL_SFTRST(v)                 (((v) & 0x1) << 31)
+#define BFM_SYDMA_CTRL_SFTRST(v)                BM_SYDMA_CTRL_SFTRST
+#define BF_SYDMA_CTRL_SFTRST_V(e)               BF_SYDMA_CTRL_SFTRST(BV_SYDMA_CTRL_SFTRST__##e)
+#define BFM_SYDMA_CTRL_SFTRST_V(v)              BM_SYDMA_CTRL_SFTRST
+#define BP_SYDMA_CTRL_CLKGATE                   30
+#define BM_SYDMA_CTRL_CLKGATE                   0x40000000
+#define BV_SYDMA_CTRL_CLKGATE__RUN              0x0
+#define BV_SYDMA_CTRL_CLKGATE__NO_CLKS          0x1
+#define BF_SYDMA_CTRL_CLKGATE(v)                (((v) & 0x1) << 30)
+#define BFM_SYDMA_CTRL_CLKGATE(v)               BM_SYDMA_CTRL_CLKGATE
+#define BF_SYDMA_CTRL_CLKGATE_V(e)              BF_SYDMA_CTRL_CLKGATE(BV_SYDMA_CTRL_CLKGATE__##e)
+#define BFM_SYDMA_CTRL_CLKGATE_V(v)             BM_SYDMA_CTRL_CLKGATE
+#define BP_SYDMA_CTRL_RSVD1                     10
+#define BM_SYDMA_CTRL_RSVD1                     0x3ffffc00
+#define BF_SYDMA_CTRL_RSVD1(v)                  (((v) & 0xfffff) << 10)
+#define BFM_SYDMA_CTRL_RSVD1(v)                 BM_SYDMA_CTRL_RSVD1
+#define BF_SYDMA_CTRL_RSVD1_V(e)                BF_SYDMA_CTRL_RSVD1(BV_SYDMA_CTRL_RSVD1__##e)
+#define BFM_SYDMA_CTRL_RSVD1_V(v)               BM_SYDMA_CTRL_RSVD1
+#define BP_SYDMA_CTRL_COMPLETE_IRQ_EN           9
+#define BM_SYDMA_CTRL_COMPLETE_IRQ_EN           0x200
+#define BV_SYDMA_CTRL_COMPLETE_IRQ_EN__DISABLED 0x0
+#define BV_SYDMA_CTRL_COMPLETE_IRQ_EN__ENABLED  0x1
+#define BF_SYDMA_CTRL_COMPLETE_IRQ_EN(v)        (((v) & 0x1) << 9)
+#define BFM_SYDMA_CTRL_COMPLETE_IRQ_EN(v)       BM_SYDMA_CTRL_COMPLETE_IRQ_EN
+#define BF_SYDMA_CTRL_COMPLETE_IRQ_EN_V(e)      BF_SYDMA_CTRL_COMPLETE_IRQ_EN(BV_SYDMA_CTRL_COMPLETE_IRQ_EN__##e)
+#define BFM_SYDMA_CTRL_COMPLETE_IRQ_EN_V(v)     BM_SYDMA_CTRL_COMPLETE_IRQ_EN
+#define BP_SYDMA_CTRL_RSVD0                     3
+#define BM_SYDMA_CTRL_RSVD0                     0x1f8
+#define BF_SYDMA_CTRL_RSVD0(v)                  (((v) & 0x3f) << 3)
+#define BFM_SYDMA_CTRL_RSVD0(v)                 BM_SYDMA_CTRL_RSVD0
+#define BF_SYDMA_CTRL_RSVD0_V(e)                BF_SYDMA_CTRL_RSVD0(BV_SYDMA_CTRL_RSVD0__##e)
+#define BFM_SYDMA_CTRL_RSVD0_V(v)               BM_SYDMA_CTRL_RSVD0
+#define BP_SYDMA_CTRL_ERROR_IRQ                 2
+#define BM_SYDMA_CTRL_ERROR_IRQ                 0x4
+#define BF_SYDMA_CTRL_ERROR_IRQ(v)              (((v) & 0x1) << 2)
+#define BFM_SYDMA_CTRL_ERROR_IRQ(v)             BM_SYDMA_CTRL_ERROR_IRQ
+#define BF_SYDMA_CTRL_ERROR_IRQ_V(e)            BF_SYDMA_CTRL_ERROR_IRQ(BV_SYDMA_CTRL_ERROR_IRQ__##e)
+#define BFM_SYDMA_CTRL_ERROR_IRQ_V(v)           BM_SYDMA_CTRL_ERROR_IRQ
+#define BP_SYDMA_CTRL_COMPLETE_IRQ              1
+#define BM_SYDMA_CTRL_COMPLETE_IRQ              0x2
+#define BF_SYDMA_CTRL_COMPLETE_IRQ(v)           (((v) & 0x1) << 1)
+#define BFM_SYDMA_CTRL_COMPLETE_IRQ(v)          BM_SYDMA_CTRL_COMPLETE_IRQ
+#define BF_SYDMA_CTRL_COMPLETE_IRQ_V(e)         BF_SYDMA_CTRL_COMPLETE_IRQ(BV_SYDMA_CTRL_COMPLETE_IRQ__##e)
+#define BFM_SYDMA_CTRL_COMPLETE_IRQ_V(v)        BM_SYDMA_CTRL_COMPLETE_IRQ
+#define BP_SYDMA_CTRL_RUN                       0
+#define BM_SYDMA_CTRL_RUN                       0x1
+#define BV_SYDMA_CTRL_RUN__HALT                 0x0
+#define BV_SYDMA_CTRL_RUN__RUN                  0x1
+#define BF_SYDMA_CTRL_RUN(v)                    (((v) & 0x1) << 0)
+#define BFM_SYDMA_CTRL_RUN(v)                   BM_SYDMA_CTRL_RUN
+#define BF_SYDMA_CTRL_RUN_V(e)                  BF_SYDMA_CTRL_RUN(BV_SYDMA_CTRL_RUN__##e)
+#define BFM_SYDMA_CTRL_RUN_V(v)                 BM_SYDMA_CTRL_RUN
+
+#define HW_SYDMA_RADDR                  HW(SYDMA_RADDR)
+#define HWA_SYDMA_RADDR                 (0x80026000 + 0x10)
+#define HWT_SYDMA_RADDR                 HWIO_32_RW
+#define HWN_SYDMA_RADDR                 SYDMA_RADDR
+#define HWI_SYDMA_RADDR                 
+#define BP_SYDMA_RADDR_RSRC_ADDR        0
+#define BM_SYDMA_RADDR_RSRC_ADDR        0xffffffff
+#define BF_SYDMA_RADDR_RSRC_ADDR(v)     (((v) & 0xffffffff) << 0)
+#define BFM_SYDMA_RADDR_RSRC_ADDR(v)    BM_SYDMA_RADDR_RSRC_ADDR
+#define BF_SYDMA_RADDR_RSRC_ADDR_V(e)   BF_SYDMA_RADDR_RSRC_ADDR(BV_SYDMA_RADDR_RSRC_ADDR__##e)
+#define BFM_SYDMA_RADDR_RSRC_ADDR_V(v)  BM_SYDMA_RADDR_RSRC_ADDR
+
+#define HW_SYDMA_WADDR                  HW(SYDMA_WADDR)
+#define HWA_SYDMA_WADDR                 (0x80026000 + 0x20)
+#define HWT_SYDMA_WADDR                 HWIO_32_RW
+#define HWN_SYDMA_WADDR                 SYDMA_WADDR
+#define HWI_SYDMA_WADDR                 
+#define BP_SYDMA_WADDR_WSRC_ADDR        0
+#define BM_SYDMA_WADDR_WSRC_ADDR        0xffffffff
+#define BF_SYDMA_WADDR_WSRC_ADDR(v)     (((v) & 0xffffffff) << 0)
+#define BFM_SYDMA_WADDR_WSRC_ADDR(v)    BM_SYDMA_WADDR_WSRC_ADDR
+#define BF_SYDMA_WADDR_WSRC_ADDR_V(e)   BF_SYDMA_WADDR_WSRC_ADDR(BV_SYDMA_WADDR_WSRC_ADDR__##e)
+#define BFM_SYDMA_WADDR_WSRC_ADDR_V(v)  BM_SYDMA_WADDR_WSRC_ADDR
+
+#define HW_SYDMA_XFER_COUNT             HW(SYDMA_XFER_COUNT)
+#define HWA_SYDMA_XFER_COUNT            (0x80026000 + 0x30)
+#define HWT_SYDMA_XFER_COUNT            HWIO_32_RW
+#define HWN_SYDMA_XFER_COUNT            SYDMA_XFER_COUNT
+#define HWI_SYDMA_XFER_COUNT            
+#define BP_SYDMA_XFER_COUNT_SIZE        0
+#define BM_SYDMA_XFER_COUNT_SIZE        0xffffffff
+#define BF_SYDMA_XFER_COUNT_SIZE(v)     (((v) & 0xffffffff) << 0)
+#define BFM_SYDMA_XFER_COUNT_SIZE(v)    BM_SYDMA_XFER_COUNT_SIZE
+#define BF_SYDMA_XFER_COUNT_SIZE_V(e)   BF_SYDMA_XFER_COUNT_SIZE(BV_SYDMA_XFER_COUNT_SIZE__##e)
+#define BFM_SYDMA_XFER_COUNT_SIZE_V(v)  BM_SYDMA_XFER_COUNT_SIZE
+
+#define HW_SYDMA_BURST              HW(SYDMA_BURST)
+#define HWA_SYDMA_BURST             (0x80026000 + 0x40)
+#define HWT_SYDMA_BURST             HWIO_32_RW
+#define HWN_SYDMA_BURST             SYDMA_BURST
+#define HWI_SYDMA_BURST             
+#define BP_SYDMA_BURST_RSVD0        4
+#define BM_SYDMA_BURST_RSVD0        0xfffffff0
+#define BF_SYDMA_BURST_RSVD0(v)     (((v) & 0xfffffff) << 4)
+#define BFM_SYDMA_BURST_RSVD0(v)    BM_SYDMA_BURST_RSVD0
+#define BF_SYDMA_BURST_RSVD0_V(e)   BF_SYDMA_BURST_RSVD0(BV_SYDMA_BURST_RSVD0__##e)
+#define BFM_SYDMA_BURST_RSVD0_V(v)  BM_SYDMA_BURST_RSVD0
+#define BP_SYDMA_BURST_WLEN         2
+#define BM_SYDMA_BURST_WLEN         0xc
+#define BV_SYDMA_BURST_WLEN__1      0x0
+#define BV_SYDMA_BURST_WLEN__2      0x1
+#define BV_SYDMA_BURST_WLEN__4      0x2
+#define BV_SYDMA_BURST_WLEN__8      0x3
+#define BF_SYDMA_BURST_WLEN(v)      (((v) & 0x3) << 2)
+#define BFM_SYDMA_BURST_WLEN(v)     BM_SYDMA_BURST_WLEN
+#define BF_SYDMA_BURST_WLEN_V(e)    BF_SYDMA_BURST_WLEN(BV_SYDMA_BURST_WLEN__##e)
+#define BFM_SYDMA_BURST_WLEN_V(v)   BM_SYDMA_BURST_WLEN
+#define BP_SYDMA_BURST_RLEN         0
+#define BM_SYDMA_BURST_RLEN         0x3
+#define BV_SYDMA_BURST_RLEN__1      0x0
+#define BV_SYDMA_BURST_RLEN__2      0x1
+#define BV_SYDMA_BURST_RLEN__4      0x2
+#define BV_SYDMA_BURST_RLEN__8      0x3
+#define BF_SYDMA_BURST_RLEN(v)      (((v) & 0x3) << 0)
+#define BFM_SYDMA_BURST_RLEN(v)     BM_SYDMA_BURST_RLEN
+#define BF_SYDMA_BURST_RLEN_V(e)    BF_SYDMA_BURST_RLEN(BV_SYDMA_BURST_RLEN__##e)
+#define BFM_SYDMA_BURST_RLEN_V(v)   BM_SYDMA_BURST_RLEN
+
+#define HW_SYDMA_DACK               HW(SYDMA_DACK)
+#define HWA_SYDMA_DACK              (0x80026000 + 0x50)
+#define HWT_SYDMA_DACK              HWIO_32_RW
+#define HWN_SYDMA_DACK              SYDMA_DACK
+#define HWI_SYDMA_DACK              
+#define BP_SYDMA_DACK_RSVD0         8
+#define BM_SYDMA_DACK_RSVD0         0xffffff00
+#define BF_SYDMA_DACK_RSVD0(v)      (((v) & 0xffffff) << 8)
+#define BFM_SYDMA_DACK_RSVD0(v)     BM_SYDMA_DACK_RSVD0
+#define BF_SYDMA_DACK_RSVD0_V(e)    BF_SYDMA_DACK_RSVD0(BV_SYDMA_DACK_RSVD0__##e)
+#define BFM_SYDMA_DACK_RSVD0_V(v)   BM_SYDMA_DACK_RSVD0
+#define BP_SYDMA_DACK_WDELAY        4
+#define BM_SYDMA_DACK_WDELAY        0xf0
+#define BF_SYDMA_DACK_WDELAY(v)     (((v) & 0xf) << 4)
+#define BFM_SYDMA_DACK_WDELAY(v)    BM_SYDMA_DACK_WDELAY
+#define BF_SYDMA_DACK_WDELAY_V(e)   BF_SYDMA_DACK_WDELAY(BV_SYDMA_DACK_WDELAY__##e)
+#define BFM_SYDMA_DACK_WDELAY_V(v)  BM_SYDMA_DACK_WDELAY
+#define BP_SYDMA_DACK_RDELAY        0
+#define BM_SYDMA_DACK_RDELAY        0xf
+#define BF_SYDMA_DACK_RDELAY(v)     (((v) & 0xf) << 0)
+#define BFM_SYDMA_DACK_RDELAY(v)    BM_SYDMA_DACK_RDELAY
+#define BF_SYDMA_DACK_RDELAY_V(e)   BF_SYDMA_DACK_RDELAY(BV_SYDMA_DACK_RDELAY__##e)
+#define BFM_SYDMA_DACK_RDELAY_V(v)  BM_SYDMA_DACK_RDELAY
+
+#define HW_SYDMA_DEBUG0             HW(SYDMA_DEBUG0)
+#define HWA_SYDMA_DEBUG0            (0x80026000 + 0x100)
+#define HWT_SYDMA_DEBUG0            HWIO_32_RW
+#define HWN_SYDMA_DEBUG0            SYDMA_DEBUG0
+#define HWI_SYDMA_DEBUG0            
+#define BP_SYDMA_DEBUG0_DATA        0
+#define BM_SYDMA_DEBUG0_DATA        0xffffffff
+#define BF_SYDMA_DEBUG0_DATA(v)     (((v) & 0xffffffff) << 0)
+#define BFM_SYDMA_DEBUG0_DATA(v)    BM_SYDMA_DEBUG0_DATA
+#define BF_SYDMA_DEBUG0_DATA_V(e)   BF_SYDMA_DEBUG0_DATA(BV_SYDMA_DEBUG0_DATA__##e)
+#define BFM_SYDMA_DEBUG0_DATA_V(v)  BM_SYDMA_DEBUG0_DATA
+
+#define HW_SYDMA_DEBUG1             HW(SYDMA_DEBUG1)
+#define HWA_SYDMA_DEBUG1            (0x80026000 + 0x110)
+#define HWT_SYDMA_DEBUG1            HWIO_32_RW
+#define HWN_SYDMA_DEBUG1            SYDMA_DEBUG1
+#define HWI_SYDMA_DEBUG1            
+#define BP_SYDMA_DEBUG1_DATA        0
+#define BM_SYDMA_DEBUG1_DATA        0xffffffff
+#define BF_SYDMA_DEBUG1_DATA(v)     (((v) & 0xffffffff) << 0)
+#define BFM_SYDMA_DEBUG1_DATA(v)    BM_SYDMA_DEBUG1_DATA
+#define BF_SYDMA_DEBUG1_DATA_V(e)   BF_SYDMA_DEBUG1_DATA(BV_SYDMA_DEBUG1_DATA__##e)
+#define BFM_SYDMA_DEBUG1_DATA_V(v)  BM_SYDMA_DEBUG1_DATA
+
+#define HW_SYDMA_DEBUG2             HW(SYDMA_DEBUG2)
+#define HWA_SYDMA_DEBUG2            (0x80026000 + 0x120)
+#define HWT_SYDMA_DEBUG2            HWIO_32_RW
+#define HWN_SYDMA_DEBUG2            SYDMA_DEBUG2
+#define HWI_SYDMA_DEBUG2            
+#define BP_SYDMA_DEBUG2_DATA        0
+#define BM_SYDMA_DEBUG2_DATA        0xffffffff
+#define BF_SYDMA_DEBUG2_DATA(v)     (((v) & 0xffffffff) << 0)
+#define BFM_SYDMA_DEBUG2_DATA(v)    BM_SYDMA_DEBUG2_DATA
+#define BF_SYDMA_DEBUG2_DATA_V(e)   BF_SYDMA_DEBUG2_DATA(BV_SYDMA_DEBUG2_DATA__##e)
+#define BFM_SYDMA_DEBUG2_DATA_V(v)  BM_SYDMA_DEBUG2_DATA
+
+#define HW_SYDMA_VERSION                HW(SYDMA_VERSION)
+#define HWA_SYDMA_VERSION               (0x80026000 + 0x130)
+#define HWT_SYDMA_VERSION               HWIO_32_RW
+#define HWN_SYDMA_VERSION               SYDMA_VERSION
+#define HWI_SYDMA_VERSION               
+#define BP_SYDMA_VERSION_MAJOR          24
+#define BM_SYDMA_VERSION_MAJOR          0xff000000
+#define BF_SYDMA_VERSION_MAJOR(v)       (((v) & 0xff) << 24)
+#define BFM_SYDMA_VERSION_MAJOR(v)      BM_SYDMA_VERSION_MAJOR
+#define BF_SYDMA_VERSION_MAJOR_V(e)     BF_SYDMA_VERSION_MAJOR(BV_SYDMA_VERSION_MAJOR__##e)
+#define BFM_SYDMA_VERSION_MAJOR_V(v)    BM_SYDMA_VERSION_MAJOR
+#define BP_SYDMA_VERSION_MINOR          16
+#define BM_SYDMA_VERSION_MINOR          0xff0000
+#define BF_SYDMA_VERSION_MINOR(v)       (((v) & 0xff) << 16)
+#define BFM_SYDMA_VERSION_MINOR(v)      BM_SYDMA_VERSION_MINOR
+#define BF_SYDMA_VERSION_MINOR_V(e)     BF_SYDMA_VERSION_MINOR(BV_SYDMA_VERSION_MINOR__##e)
+#define BFM_SYDMA_VERSION_MINOR_V(v)    BM_SYDMA_VERSION_MINOR
+#define BP_SYDMA_VERSION_STEP           0
+#define BM_SYDMA_VERSION_STEP           0xffff
+#define BF_SYDMA_VERSION_STEP(v)        (((v) & 0xffff) << 0)
+#define BFM_SYDMA_VERSION_STEP(v)       BM_SYDMA_VERSION_STEP
+#define BF_SYDMA_VERSION_STEP_V(e)      BF_SYDMA_VERSION_STEP(BV_SYDMA_VERSION_STEP__##e)
+#define BFM_SYDMA_VERSION_STEP_V(v)     BM_SYDMA_VERSION_STEP
+
+#endif /* __HEADERGEN_IMX233_SYDMA_H__*/
diff --git a/firmware/target/arm/imx233/regs/imx233/timrot.h b/firmware/target/arm/imx233/regs/imx233/timrot.h
new file mode 100644
index 0000000000..f7c65bde53
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/imx233/timrot.h
@@ -0,0 +1,469 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * imx233 version: 2.4.0
+ * imx233 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_IMX233_TIMROT_H__
+#define __HEADERGEN_IMX233_TIMROT_H__
+
+#define HW_TIMROT_ROTCTRL                       HW(TIMROT_ROTCTRL)
+#define HWA_TIMROT_ROTCTRL                      (0x80068000 + 0x0)
+#define HWT_TIMROT_ROTCTRL                      HWIO_32_RW
+#define HWN_TIMROT_ROTCTRL                      TIMROT_ROTCTRL
+#define HWI_TIMROT_ROTCTRL                      
+#define HW_TIMROT_ROTCTRL_SET                   HW(TIMROT_ROTCTRL_SET)
+#define HWA_TIMROT_ROTCTRL_SET                  (HWA_TIMROT_ROTCTRL + 0x4)
+#define HWT_TIMROT_ROTCTRL_SET                  HWIO_32_WO
+#define HWN_TIMROT_ROTCTRL_SET                  TIMROT_ROTCTRL
+#define HWI_TIMROT_ROTCTRL_SET                  
+#define HW_TIMROT_ROTCTRL_CLR                   HW(TIMROT_ROTCTRL_CLR)
+#define HWA_TIMROT_ROTCTRL_CLR                  (HWA_TIMROT_ROTCTRL + 0x8)
+#define HWT_TIMROT_ROTCTRL_CLR                  HWIO_32_WO
+#define HWN_TIMROT_ROTCTRL_CLR                  TIMROT_ROTCTRL
+#define HWI_TIMROT_ROTCTRL_CLR                  
+#define HW_TIMROT_ROTCTRL_TOG                   HW(TIMROT_ROTCTRL_TOG)
+#define HWA_TIMROT_ROTCTRL_TOG                  (HWA_TIMROT_ROTCTRL + 0xc)
+#define HWT_TIMROT_ROTCTRL_TOG                  HWIO_32_WO
+#define HWN_TIMROT_ROTCTRL_TOG                  TIMROT_ROTCTRL
+#define HWI_TIMROT_ROTCTRL_TOG                  
+#define BP_TIMROT_ROTCTRL_SFTRST                31
+#define BM_TIMROT_ROTCTRL_SFTRST                0x80000000
+#define BF_TIMROT_ROTCTRL_SFTRST(v)             (((v) & 0x1) << 31)
+#define BFM_TIMROT_ROTCTRL_SFTRST(v)            BM_TIMROT_ROTCTRL_SFTRST
+#define BF_TIMROT_ROTCTRL_SFTRST_V(e)           BF_TIMROT_ROTCTRL_SFTRST(BV_TIMROT_ROTCTRL_SFTRST__##e)
+#define BFM_TIMROT_ROTCTRL_SFTRST_V(v)          BM_TIMROT_ROTCTRL_SFTRST
+#define BP_TIMROT_ROTCTRL_CLKGATE               30
+#define BM_TIMROT_ROTCTRL_CLKGATE               0x40000000
+#define BF_TIMROT_ROTCTRL_CLKGATE(v)            (((v) & 0x1) << 30)
+#define BFM_TIMROT_ROTCTRL_CLKGATE(v)           BM_TIMROT_ROTCTRL_CLKGATE
+#define BF_TIMROT_ROTCTRL_CLKGATE_V(e)          BF_TIMROT_ROTCTRL_CLKGATE(BV_TIMROT_ROTCTRL_CLKGATE__##e)
+#define BFM_TIMROT_ROTCTRL_CLKGATE_V(v)         BM_TIMROT_ROTCTRL_CLKGATE
+#define BP_TIMROT_ROTCTRL_ROTARY_PRESENT        29
+#define BM_TIMROT_ROTCTRL_ROTARY_PRESENT        0x20000000
+#define BF_TIMROT_ROTCTRL_ROTARY_PRESENT(v)     (((v) & 0x1) << 29)
+#define BFM_TIMROT_ROTCTRL_ROTARY_PRESENT(v)    BM_TIMROT_ROTCTRL_ROTARY_PRESENT
+#define BF_TIMROT_ROTCTRL_ROTARY_PRESENT_V(e)   BF_TIMROT_ROTCTRL_ROTARY_PRESENT(BV_TIMROT_ROTCTRL_ROTARY_PRESENT__##e)
+#define BFM_TIMROT_ROTCTRL_ROTARY_PRESENT_V(v)  BM_TIMROT_ROTCTRL_ROTARY_PRESENT
+#define BP_TIMROT_ROTCTRL_TIM3_PRESENT          28
+#define BM_TIMROT_ROTCTRL_TIM3_PRESENT          0x10000000
+#define BF_TIMROT_ROTCTRL_TIM3_PRESENT(v)       (((v) & 0x1) << 28)
+#define BFM_TIMROT_ROTCTRL_TIM3_PRESENT(v)      BM_TIMROT_ROTCTRL_TIM3_PRESENT
+#define BF_TIMROT_ROTCTRL_TIM3_PRESENT_V(e)     BF_TIMROT_ROTCTRL_TIM3_PRESENT(BV_TIMROT_ROTCTRL_TIM3_PRESENT__##e)
+#define BFM_TIMROT_ROTCTRL_TIM3_PRESENT_V(v)    BM_TIMROT_ROTCTRL_TIM3_PRESENT
+#define BP_TIMROT_ROTCTRL_TIM2_PRESENT          27
+#define BM_TIMROT_ROTCTRL_TIM2_PRESENT          0x8000000
+#define BF_TIMROT_ROTCTRL_TIM2_PRESENT(v)       (((v) & 0x1) << 27)
+#define BFM_TIMROT_ROTCTRL_TIM2_PRESENT(v)      BM_TIMROT_ROTCTRL_TIM2_PRESENT
+#define BF_TIMROT_ROTCTRL_TIM2_PRESENT_V(e)     BF_TIMROT_ROTCTRL_TIM2_PRESENT(BV_TIMROT_ROTCTRL_TIM2_PRESENT__##e)
+#define BFM_TIMROT_ROTCTRL_TIM2_PRESENT_V(v)    BM_TIMROT_ROTCTRL_TIM2_PRESENT
+#define BP_TIMROT_ROTCTRL_TIM1_PRESENT          26
+#define BM_TIMROT_ROTCTRL_TIM1_PRESENT          0x4000000
+#define BF_TIMROT_ROTCTRL_TIM1_PRESENT(v)       (((v) & 0x1) << 26)
+#define BFM_TIMROT_ROTCTRL_TIM1_PRESENT(v)      BM_TIMROT_ROTCTRL_TIM1_PRESENT
+#define BF_TIMROT_ROTCTRL_TIM1_PRESENT_V(e)     BF_TIMROT_ROTCTRL_TIM1_PRESENT(BV_TIMROT_ROTCTRL_TIM1_PRESENT__##e)
+#define BFM_TIMROT_ROTCTRL_TIM1_PRESENT_V(v)    BM_TIMROT_ROTCTRL_TIM1_PRESENT
+#define BP_TIMROT_ROTCTRL_TIM0_PRESENT          25
+#define BM_TIMROT_ROTCTRL_TIM0_PRESENT          0x2000000
+#define BF_TIMROT_ROTCTRL_TIM0_PRESENT(v)       (((v) & 0x1) << 25)
+#define BFM_TIMROT_ROTCTRL_TIM0_PRESENT(v)      BM_TIMROT_ROTCTRL_TIM0_PRESENT
+#define BF_TIMROT_ROTCTRL_TIM0_PRESENT_V(e)     BF_TIMROT_ROTCTRL_TIM0_PRESENT(BV_TIMROT_ROTCTRL_TIM0_PRESENT__##e)
+#define BFM_TIMROT_ROTCTRL_TIM0_PRESENT_V(v)    BM_TIMROT_ROTCTRL_TIM0_PRESENT
+#define BP_TIMROT_ROTCTRL_STATE                 22
+#define BM_TIMROT_ROTCTRL_STATE                 0x1c00000
+#define BF_TIMROT_ROTCTRL_STATE(v)              (((v) & 0x7) << 22)
+#define BFM_TIMROT_ROTCTRL_STATE(v)             BM_TIMROT_ROTCTRL_STATE
+#define BF_TIMROT_ROTCTRL_STATE_V(e)            BF_TIMROT_ROTCTRL_STATE(BV_TIMROT_ROTCTRL_STATE__##e)
+#define BFM_TIMROT_ROTCTRL_STATE_V(v)           BM_TIMROT_ROTCTRL_STATE
+#define BP_TIMROT_ROTCTRL_DIVIDER               16
+#define BM_TIMROT_ROTCTRL_DIVIDER               0x3f0000
+#define BF_TIMROT_ROTCTRL_DIVIDER(v)            (((v) & 0x3f) << 16)
+#define BFM_TIMROT_ROTCTRL_DIVIDER(v)           BM_TIMROT_ROTCTRL_DIVIDER
+#define BF_TIMROT_ROTCTRL_DIVIDER_V(e)          BF_TIMROT_ROTCTRL_DIVIDER(BV_TIMROT_ROTCTRL_DIVIDER__##e)
+#define BFM_TIMROT_ROTCTRL_DIVIDER_V(v)         BM_TIMROT_ROTCTRL_DIVIDER
+#define BP_TIMROT_ROTCTRL_RSRVD3                13
+#define BM_TIMROT_ROTCTRL_RSRVD3                0xe000
+#define BF_TIMROT_ROTCTRL_RSRVD3(v)             (((v) & 0x7) << 13)
+#define BFM_TIMROT_ROTCTRL_RSRVD3(v)            BM_TIMROT_ROTCTRL_RSRVD3
+#define BF_TIMROT_ROTCTRL_RSRVD3_V(e)           BF_TIMROT_ROTCTRL_RSRVD3(BV_TIMROT_ROTCTRL_RSRVD3__##e)
+#define BFM_TIMROT_ROTCTRL_RSRVD3_V(v)          BM_TIMROT_ROTCTRL_RSRVD3
+#define BP_TIMROT_ROTCTRL_RELATIVE              12
+#define BM_TIMROT_ROTCTRL_RELATIVE              0x1000
+#define BF_TIMROT_ROTCTRL_RELATIVE(v)           (((v) & 0x1) << 12)
+#define BFM_TIMROT_ROTCTRL_RELATIVE(v)          BM_TIMROT_ROTCTRL_RELATIVE
+#define BF_TIMROT_ROTCTRL_RELATIVE_V(e)         BF_TIMROT_ROTCTRL_RELATIVE(BV_TIMROT_ROTCTRL_RELATIVE__##e)
+#define BFM_TIMROT_ROTCTRL_RELATIVE_V(v)        BM_TIMROT_ROTCTRL_RELATIVE
+#define BP_TIMROT_ROTCTRL_OVERSAMPLE            10
+#define BM_TIMROT_ROTCTRL_OVERSAMPLE            0xc00
+#define BV_TIMROT_ROTCTRL_OVERSAMPLE__8X        0x0
+#define BV_TIMROT_ROTCTRL_OVERSAMPLE__4X        0x1
+#define BV_TIMROT_ROTCTRL_OVERSAMPLE__2X        0x2
+#define BV_TIMROT_ROTCTRL_OVERSAMPLE__1X        0x3
+#define BF_TIMROT_ROTCTRL_OVERSAMPLE(v)         (((v) & 0x3) << 10)
+#define BFM_TIMROT_ROTCTRL_OVERSAMPLE(v)        BM_TIMROT_ROTCTRL_OVERSAMPLE
+#define BF_TIMROT_ROTCTRL_OVERSAMPLE_V(e)       BF_TIMROT_ROTCTRL_OVERSAMPLE(BV_TIMROT_ROTCTRL_OVERSAMPLE__##e)
+#define BFM_TIMROT_ROTCTRL_OVERSAMPLE_V(v)      BM_TIMROT_ROTCTRL_OVERSAMPLE
+#define BP_TIMROT_ROTCTRL_POLARITY_B            9
+#define BM_TIMROT_ROTCTRL_POLARITY_B            0x200
+#define BF_TIMROT_ROTCTRL_POLARITY_B(v)         (((v) & 0x1) << 9)
+#define BFM_TIMROT_ROTCTRL_POLARITY_B(v)        BM_TIMROT_ROTCTRL_POLARITY_B
+#define BF_TIMROT_ROTCTRL_POLARITY_B_V(e)       BF_TIMROT_ROTCTRL_POLARITY_B(BV_TIMROT_ROTCTRL_POLARITY_B__##e)
+#define BFM_TIMROT_ROTCTRL_POLARITY_B_V(v)      BM_TIMROT_ROTCTRL_POLARITY_B
+#define BP_TIMROT_ROTCTRL_POLARITY_A            8
+#define BM_TIMROT_ROTCTRL_POLARITY_A            0x100
+#define BF_TIMROT_ROTCTRL_POLARITY_A(v)         (((v) & 0x1) << 8)
+#define BFM_TIMROT_ROTCTRL_POLARITY_A(v)        BM_TIMROT_ROTCTRL_POLARITY_A
+#define BF_TIMROT_ROTCTRL_POLARITY_A_V(e)       BF_TIMROT_ROTCTRL_POLARITY_A(BV_TIMROT_ROTCTRL_POLARITY_A__##e)
+#define BFM_TIMROT_ROTCTRL_POLARITY_A_V(v)      BM_TIMROT_ROTCTRL_POLARITY_A
+#define BP_TIMROT_ROTCTRL_RSRVD2                7
+#define BM_TIMROT_ROTCTRL_RSRVD2                0x80
+#define BF_TIMROT_ROTCTRL_RSRVD2(v)             (((v) & 0x1) << 7)
+#define BFM_TIMROT_ROTCTRL_RSRVD2(v)            BM_TIMROT_ROTCTRL_RSRVD2
+#define BF_TIMROT_ROTCTRL_RSRVD2_V(e)           BF_TIMROT_ROTCTRL_RSRVD2(BV_TIMROT_ROTCTRL_RSRVD2__##e)
+#define BFM_TIMROT_ROTCTRL_RSRVD2_V(v)          BM_TIMROT_ROTCTRL_RSRVD2
+#define BP_TIMROT_ROTCTRL_SELECT_B              4
+#define BM_TIMROT_ROTCTRL_SELECT_B              0x70
+#define BV_TIMROT_ROTCTRL_SELECT_B__NEVER_TICK  0x0
+#define BV_TIMROT_ROTCTRL_SELECT_B__PWM0        0x1
+#define BV_TIMROT_ROTCTRL_SELECT_B__PWM1        0x2
+#define BV_TIMROT_ROTCTRL_SELECT_B__PWM2        0x3
+#define BV_TIMROT_ROTCTRL_SELECT_B__PWM3        0x4
+#define BV_TIMROT_ROTCTRL_SELECT_B__PWM4        0x5
+#define BV_TIMROT_ROTCTRL_SELECT_B__ROTARYA     0x6
+#define BV_TIMROT_ROTCTRL_SELECT_B__ROTARYB     0x7
+#define BF_TIMROT_ROTCTRL_SELECT_B(v)           (((v) & 0x7) << 4)
+#define BFM_TIMROT_ROTCTRL_SELECT_B(v)          BM_TIMROT_ROTCTRL_SELECT_B
+#define BF_TIMROT_ROTCTRL_SELECT_B_V(e)         BF_TIMROT_ROTCTRL_SELECT_B(BV_TIMROT_ROTCTRL_SELECT_B__##e)
+#define BFM_TIMROT_ROTCTRL_SELECT_B_V(v)        BM_TIMROT_ROTCTRL_SELECT_B
+#define BP_TIMROT_ROTCTRL_RSRVD1                3
+#define BM_TIMROT_ROTCTRL_RSRVD1                0x8
+#define BF_TIMROT_ROTCTRL_RSRVD1(v)             (((v) & 0x1) << 3)
+#define BFM_TIMROT_ROTCTRL_RSRVD1(v)            BM_TIMROT_ROTCTRL_RSRVD1
+#define BF_TIMROT_ROTCTRL_RSRVD1_V(e)           BF_TIMROT_ROTCTRL_RSRVD1(BV_TIMROT_ROTCTRL_RSRVD1__##e)
+#define BFM_TIMROT_ROTCTRL_RSRVD1_V(v)          BM_TIMROT_ROTCTRL_RSRVD1
+#define BP_TIMROT_ROTCTRL_SELECT_A              0
+#define BM_TIMROT_ROTCTRL_SELECT_A              0x7
+#define BV_TIMROT_ROTCTRL_SELECT_A__NEVER_TICK  0x0
+#define BV_TIMROT_ROTCTRL_SELECT_A__PWM0        0x1
+#define BV_TIMROT_ROTCTRL_SELECT_A__PWM1        0x2
+#define BV_TIMROT_ROTCTRL_SELECT_A__PWM2        0x3
+#define BV_TIMROT_ROTCTRL_SELECT_A__PWM3        0x4
+#define BV_TIMROT_ROTCTRL_SELECT_A__PWM4        0x5
+#define BV_TIMROT_ROTCTRL_SELECT_A__ROTARYA     0x6
+#define BV_TIMROT_ROTCTRL_SELECT_A__ROTARYB     0x7
+#define BF_TIMROT_ROTCTRL_SELECT_A(v)           (((v) & 0x7) << 0)
+#define BFM_TIMROT_ROTCTRL_SELECT_A(v)          BM_TIMROT_ROTCTRL_SELECT_A
+#define BF_TIMROT_ROTCTRL_SELECT_A_V(e)         BF_TIMROT_ROTCTRL_SELECT_A(BV_TIMROT_ROTCTRL_SELECT_A__##e)
+#define BFM_TIMROT_ROTCTRL_SELECT_A_V(v)        BM_TIMROT_ROTCTRL_SELECT_A
+
+#define HW_TIMROT_ROTCOUNT              HW(TIMROT_ROTCOUNT)
+#define HWA_TIMROT_ROTCOUNT             (0x80068000 + 0x10)
+#define HWT_TIMROT_ROTCOUNT             HWIO_32_RW
+#define HWN_TIMROT_ROTCOUNT             TIMROT_ROTCOUNT
+#define HWI_TIMROT_ROTCOUNT             
+#define BP_TIMROT_ROTCOUNT_RSRVD1       16
+#define BM_TIMROT_ROTCOUNT_RSRVD1       0xffff0000
+#define BF_TIMROT_ROTCOUNT_RSRVD1(v)    (((v) & 0xffff) << 16)
+#define BFM_TIMROT_ROTCOUNT_RSRVD1(v)   BM_TIMROT_ROTCOUNT_RSRVD1
+#define BF_TIMROT_ROTCOUNT_RSRVD1_V(e)  BF_TIMROT_ROTCOUNT_RSRVD1(BV_TIMROT_ROTCOUNT_RSRVD1__##e)
+#define BFM_TIMROT_ROTCOUNT_RSRVD1_V(v) BM_TIMROT_ROTCOUNT_RSRVD1
+#define BP_TIMROT_ROTCOUNT_UPDOWN       0
+#define BM_TIMROT_ROTCOUNT_UPDOWN       0xffff
+#define BF_TIMROT_ROTCOUNT_UPDOWN(v)    (((v) & 0xffff) << 0)
+#define BFM_TIMROT_ROTCOUNT_UPDOWN(v)   BM_TIMROT_ROTCOUNT_UPDOWN
+#define BF_TIMROT_ROTCOUNT_UPDOWN_V(e)  BF_TIMROT_ROTCOUNT_UPDOWN(BV_TIMROT_ROTCOUNT_UPDOWN__##e)
+#define BFM_TIMROT_ROTCOUNT_UPDOWN_V(v) BM_TIMROT_ROTCOUNT_UPDOWN
+
+#define HW_TIMROT_TIMCTRLn(_n1)                 HW(TIMROT_TIMCTRLn(_n1))
+#define HWA_TIMROT_TIMCTRLn(_n1)                (0x80068000 + 0x20 + (_n1) * 0x20)
+#define HWT_TIMROT_TIMCTRLn(_n1)                HWIO_32_RW
+#define HWN_TIMROT_TIMCTRLn(_n1)                TIMROT_TIMCTRLn
+#define HWI_TIMROT_TIMCTRLn(_n1)                (_n1)
+#define HW_TIMROT_TIMCTRLn_SET(_n1)             HW(TIMROT_TIMCTRLn_SET(_n1))
+#define HWA_TIMROT_TIMCTRLn_SET(_n1)            (HWA_TIMROT_TIMCTRLn(_n1) + 0x4)
+#define HWT_TIMROT_TIMCTRLn_SET(_n1)            HWIO_32_WO
+#define HWN_TIMROT_TIMCTRLn_SET(_n1)            TIMROT_TIMCTRLn
+#define HWI_TIMROT_TIMCTRLn_SET(_n1)            (_n1)
+#define HW_TIMROT_TIMCTRLn_CLR(_n1)             HW(TIMROT_TIMCTRLn_CLR(_n1))
+#define HWA_TIMROT_TIMCTRLn_CLR(_n1)            (HWA_TIMROT_TIMCTRLn(_n1) + 0x8)
+#define HWT_TIMROT_TIMCTRLn_CLR(_n1)            HWIO_32_WO
+#define HWN_TIMROT_TIMCTRLn_CLR(_n1)            TIMROT_TIMCTRLn
+#define HWI_TIMROT_TIMCTRLn_CLR(_n1)            (_n1)
+#define HW_TIMROT_TIMCTRLn_TOG(_n1)             HW(TIMROT_TIMCTRLn_TOG(_n1))
+#define HWA_TIMROT_TIMCTRLn_TOG(_n1)            (HWA_TIMROT_TIMCTRLn(_n1) + 0xc)
+#define HWT_TIMROT_TIMCTRLn_TOG(_n1)            HWIO_32_WO
+#define HWN_TIMROT_TIMCTRLn_TOG(_n1)            TIMROT_TIMCTRLn
+#define HWI_TIMROT_TIMCTRLn_TOG(_n1)            (_n1)
+#define BP_TIMROT_TIMCTRLn_RSRVD2               16
+#define BM_TIMROT_TIMCTRLn_RSRVD2               0xffff0000
+#define BF_TIMROT_TIMCTRLn_RSRVD2(v)            (((v) & 0xffff) << 16)
+#define BFM_TIMROT_TIMCTRLn_RSRVD2(v)           BM_TIMROT_TIMCTRLn_RSRVD2
+#define BF_TIMROT_TIMCTRLn_RSRVD2_V(e)          BF_TIMROT_TIMCTRLn_RSRVD2(BV_TIMROT_TIMCTRLn_RSRVD2__##e)
+#define BFM_TIMROT_TIMCTRLn_RSRVD2_V(v)         BM_TIMROT_TIMCTRLn_RSRVD2
+#define BP_TIMROT_TIMCTRLn_IRQ                  15
+#define BM_TIMROT_TIMCTRLn_IRQ                  0x8000
+#define BF_TIMROT_TIMCTRLn_IRQ(v)               (((v) & 0x1) << 15)
+#define BFM_TIMROT_TIMCTRLn_IRQ(v)              BM_TIMROT_TIMCTRLn_IRQ
+#define BF_TIMROT_TIMCTRLn_IRQ_V(e)             BF_TIMROT_TIMCTRLn_IRQ(BV_TIMROT_TIMCTRLn_IRQ__##e)
+#define BFM_TIMROT_TIMCTRLn_IRQ_V(v)            BM_TIMROT_TIMCTRLn_IRQ
+#define BP_TIMROT_TIMCTRLn_IRQ_EN               14
+#define BM_TIMROT_TIMCTRLn_IRQ_EN               0x4000
+#define BF_TIMROT_TIMCTRLn_IRQ_EN(v)            (((v) & 0x1) << 14)
+#define BFM_TIMROT_TIMCTRLn_IRQ_EN(v)           BM_TIMROT_TIMCTRLn_IRQ_EN
+#define BF_TIMROT_TIMCTRLn_IRQ_EN_V(e)          BF_TIMROT_TIMCTRLn_IRQ_EN(BV_TIMROT_TIMCTRLn_IRQ_EN__##e)
+#define BFM_TIMROT_TIMCTRLn_IRQ_EN_V(v)         BM_TIMROT_TIMCTRLn_IRQ_EN
+#define BP_TIMROT_TIMCTRLn_RSRVD1               9
+#define BM_TIMROT_TIMCTRLn_RSRVD1               0x3e00
+#define BF_TIMROT_TIMCTRLn_RSRVD1(v)            (((v) & 0x1f) << 9)
+#define BFM_TIMROT_TIMCTRLn_RSRVD1(v)           BM_TIMROT_TIMCTRLn_RSRVD1
+#define BF_TIMROT_TIMCTRLn_RSRVD1_V(e)          BF_TIMROT_TIMCTRLn_RSRVD1(BV_TIMROT_TIMCTRLn_RSRVD1__##e)
+#define BFM_TIMROT_TIMCTRLn_RSRVD1_V(v)         BM_TIMROT_TIMCTRLn_RSRVD1
+#define BP_TIMROT_TIMCTRLn_POLARITY             8
+#define BM_TIMROT_TIMCTRLn_POLARITY             0x100
+#define BF_TIMROT_TIMCTRLn_POLARITY(v)          (((v) & 0x1) << 8)
+#define BFM_TIMROT_TIMCTRLn_POLARITY(v)         BM_TIMROT_TIMCTRLn_POLARITY
+#define BF_TIMROT_TIMCTRLn_POLARITY_V(e)        BF_TIMROT_TIMCTRLn_POLARITY(BV_TIMROT_TIMCTRLn_POLARITY__##e)
+#define BFM_TIMROT_TIMCTRLn_POLARITY_V(v)       BM_TIMROT_TIMCTRLn_POLARITY
+#define BP_TIMROT_TIMCTRLn_UPDATE               7
+#define BM_TIMROT_TIMCTRLn_UPDATE               0x80
+#define BF_TIMROT_TIMCTRLn_UPDATE(v)            (((v) & 0x1) << 7)
+#define BFM_TIMROT_TIMCTRLn_UPDATE(v)           BM_TIMROT_TIMCTRLn_UPDATE
+#define BF_TIMROT_TIMCTRLn_UPDATE_V(e)          BF_TIMROT_TIMCTRLn_UPDATE(BV_TIMROT_TIMCTRLn_UPDATE__##e)
+#define BFM_TIMROT_TIMCTRLn_UPDATE_V(v)         BM_TIMROT_TIMCTRLn_UPDATE
+#define BP_TIMROT_TIMCTRLn_RELOAD               6
+#define BM_TIMROT_TIMCTRLn_RELOAD               0x40
+#define BF_TIMROT_TIMCTRLn_RELOAD(v)            (((v) & 0x1) << 6)
+#define BFM_TIMROT_TIMCTRLn_RELOAD(v)           BM_TIMROT_TIMCTRLn_RELOAD
+#define BF_TIMROT_TIMCTRLn_RELOAD_V(e)          BF_TIMROT_TIMCTRLn_RELOAD(BV_TIMROT_TIMCTRLn_RELOAD__##e)
+#define BFM_TIMROT_TIMCTRLn_RELOAD_V(v)         BM_TIMROT_TIMCTRLn_RELOAD
+#define BP_TIMROT_TIMCTRLn_PRESCALE             4
+#define BM_TIMROT_TIMCTRLn_PRESCALE             0x30
+#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_1   0x0
+#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_2   0x1
+#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_4   0x2
+#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_8   0x3
+#define BF_TIMROT_TIMCTRLn_PRESCALE(v)          (((v) & 0x3) << 4)
+#define BFM_TIMROT_TIMCTRLn_PRESCALE(v)         BM_TIMROT_TIMCTRLn_PRESCALE
+#define BF_TIMROT_TIMCTRLn_PRESCALE_V(e)        BF_TIMROT_TIMCTRLn_PRESCALE(BV_TIMROT_TIMCTRLn_PRESCALE__##e)
+#define BFM_TIMROT_TIMCTRLn_PRESCALE_V(v)       BM_TIMROT_TIMCTRLn_PRESCALE
+#define BP_TIMROT_TIMCTRLn_SELECT               0
+#define BM_TIMROT_TIMCTRLn_SELECT               0xf
+#define BV_TIMROT_TIMCTRLn_SELECT__NEVER_TICK   0x0
+#define BV_TIMROT_TIMCTRLn_SELECT__PWM0         0x1
+#define BV_TIMROT_TIMCTRLn_SELECT__PWM1         0x2
+#define BV_TIMROT_TIMCTRLn_SELECT__PWM2         0x3
+#define BV_TIMROT_TIMCTRLn_SELECT__PWM3         0x4
+#define BV_TIMROT_TIMCTRLn_SELECT__PWM4         0x5
+#define BV_TIMROT_TIMCTRLn_SELECT__ROTARYA      0x6
+#define BV_TIMROT_TIMCTRLn_SELECT__ROTARYB      0x7
+#define BV_TIMROT_TIMCTRLn_SELECT__32KHZ_XTAL   0x8
+#define BV_TIMROT_TIMCTRLn_SELECT__8KHZ_XTAL    0x9
+#define BV_TIMROT_TIMCTRLn_SELECT__4KHZ_XTAL    0xa
+#define BV_TIMROT_TIMCTRLn_SELECT__1KHZ_XTAL    0xb
+#define BV_TIMROT_TIMCTRLn_SELECT__TICK_ALWAYS  0xc
+#define BF_TIMROT_TIMCTRLn_SELECT(v)            (((v) & 0xf) << 0)
+#define BFM_TIMROT_TIMCTRLn_SELECT(v)           BM_TIMROT_TIMCTRLn_SELECT
+#define BF_TIMROT_TIMCTRLn_SELECT_V(e)          BF_TIMROT_TIMCTRLn_SELECT(BV_TIMROT_TIMCTRLn_SELECT__##e)
+#define BFM_TIMROT_TIMCTRLn_SELECT_V(v)         BM_TIMROT_TIMCTRLn_SELECT
+
+#define HW_TIMROT_TIMCOUNTn(_n1)                HW(TIMROT_TIMCOUNTn(_n1))
+#define HWA_TIMROT_TIMCOUNTn(_n1)               (0x80068000 + 0x30 + (_n1) * 0x20)
+#define HWT_TIMROT_TIMCOUNTn(_n1)               HWIO_32_RW
+#define HWN_TIMROT_TIMCOUNTn(_n1)               TIMROT_TIMCOUNTn
+#define HWI_TIMROT_TIMCOUNTn(_n1)               (_n1)
+#define BP_TIMROT_TIMCOUNTn_RUNNING_COUNT       16
+#define BM_TIMROT_TIMCOUNTn_RUNNING_COUNT       0xffff0000
+#define BF_TIMROT_TIMCOUNTn_RUNNING_COUNT(v)    (((v) & 0xffff) << 16)
+#define BFM_TIMROT_TIMCOUNTn_RUNNING_COUNT(v)   BM_TIMROT_TIMCOUNTn_RUNNING_COUNT
+#define BF_TIMROT_TIMCOUNTn_RUNNING_COUNT_V(e)  BF_TIMROT_TIMCOUNTn_RUNNING_COUNT(BV_TIMROT_TIMCOUNTn_RUNNING_COUNT__##e)
+#define BFM_TIMROT_TIMCOUNTn_RUNNING_COUNT_V(v) BM_TIMROT_TIMCOUNTn_RUNNING_COUNT
+#define BP_TIMROT_TIMCOUNTn_FIXED_COUNT         0
+#define BM_TIMROT_TIMCOUNTn_FIXED_COUNT         0xffff
+#define BF_TIMROT_TIMCOUNTn_FIXED_COUNT(v)      (((v) & 0xffff) << 0)
+#define BFM_TIMROT_TIMCOUNTn_FIXED_COUNT(v)     BM_TIMROT_TIMCOUNTn_FIXED_COUNT
+#define BF_TIMROT_TIMCOUNTn_FIXED_COUNT_V(e)    BF_TIMROT_TIMCOUNTn_FIXED_COUNT(BV_TIMROT_TIMCOUNTn_FIXED_COUNT__##e)
+#define BFM_TIMROT_TIMCOUNTn_FIXED_COUNT_V(v)   BM_TIMROT_TIMCOUNTn_FIXED_COUNT
+
+#define HW_TIMROT_TIMCTRL3                          HW(TIMROT_TIMCTRL3)
+#define HWA_TIMROT_TIMCTRL3                         (0x80068000 + 0x80)
+#define HWT_TIMROT_TIMCTRL3                         HWIO_32_RW
+#define HWN_TIMROT_TIMCTRL3                         TIMROT_TIMCTRL3
+#define HWI_TIMROT_TIMCTRL3                         
+#define HW_TIMROT_TIMCTRL3_SET                      HW(TIMROT_TIMCTRL3_SET)
+#define HWA_TIMROT_TIMCTRL3_SET                     (HWA_TIMROT_TIMCTRL3 + 0x4)
+#define HWT_TIMROT_TIMCTRL3_SET                     HWIO_32_WO
+#define HWN_TIMROT_TIMCTRL3_SET                     TIMROT_TIMCTRL3
+#define HWI_TIMROT_TIMCTRL3_SET                     
+#define HW_TIMROT_TIMCTRL3_CLR                      HW(TIMROT_TIMCTRL3_CLR)
+#define HWA_TIMROT_TIMCTRL3_CLR                     (HWA_TIMROT_TIMCTRL3 + 0x8)
+#define HWT_TIMROT_TIMCTRL3_CLR                     HWIO_32_WO
+#define HWN_TIMROT_TIMCTRL3_CLR                     TIMROT_TIMCTRL3
+#define HWI_TIMROT_TIMCTRL3_CLR                     
+#define HW_TIMROT_TIMCTRL3_TOG                      HW(TIMROT_TIMCTRL3_TOG)
+#define HWA_TIMROT_TIMCTRL3_TOG                     (HWA_TIMROT_TIMCTRL3 + 0xc)
+#define HWT_TIMROT_TIMCTRL3_TOG                     HWIO_32_WO
+#define HWN_TIMROT_TIMCTRL3_TOG                     TIMROT_TIMCTRL3
+#define HWI_TIMROT_TIMCTRL3_TOG                     
+#define BP_TIMROT_TIMCTRL3_RSRVD2                   20
+#define BM_TIMROT_TIMCTRL3_RSRVD2                   0xfff00000
+#define BF_TIMROT_TIMCTRL3_RSRVD2(v)                (((v) & 0xfff) << 20)
+#define BFM_TIMROT_TIMCTRL3_RSRVD2(v)               BM_TIMROT_TIMCTRL3_RSRVD2
+#define BF_TIMROT_TIMCTRL3_RSRVD2_V(e)              BF_TIMROT_TIMCTRL3_RSRVD2(BV_TIMROT_TIMCTRL3_RSRVD2__##e)
+#define BFM_TIMROT_TIMCTRL3_RSRVD2_V(v)             BM_TIMROT_TIMCTRL3_RSRVD2
+#define BP_TIMROT_TIMCTRL3_TEST_SIGNAL              16
+#define BM_TIMROT_TIMCTRL3_TEST_SIGNAL              0xf0000
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__NEVER_TICK  0x0
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM0        0x1
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM1        0x2
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM2        0x3
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM3        0x4
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM4        0x5
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__ROTARYA     0x6
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__ROTARYB     0x7
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__32KHZ_XTAL  0x8
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__8KHZ_XTAL   0x9
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__4KHZ_XTAL   0xa
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__1KHZ_XTAL   0xb
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__TICK_ALWAYS 0xc
+#define BF_TIMROT_TIMCTRL3_TEST_SIGNAL(v)           (((v) & 0xf) << 16)
+#define BFM_TIMROT_TIMCTRL3_TEST_SIGNAL(v)          BM_TIMROT_TIMCTRL3_TEST_SIGNAL
+#define BF_TIMROT_TIMCTRL3_TEST_SIGNAL_V(e)         BF_TIMROT_TIMCTRL3_TEST_SIGNAL(BV_TIMROT_TIMCTRL3_TEST_SIGNAL__##e)
+#define BFM_TIMROT_TIMCTRL3_TEST_SIGNAL_V(v)        BM_TIMROT_TIMCTRL3_TEST_SIGNAL
+#define BP_TIMROT_TIMCTRL3_IRQ                      15
+#define BM_TIMROT_TIMCTRL3_IRQ                      0x8000
+#define BF_TIMROT_TIMCTRL3_IRQ(v)                   (((v) & 0x1) << 15)
+#define BFM_TIMROT_TIMCTRL3_IRQ(v)                  BM_TIMROT_TIMCTRL3_IRQ
+#define BF_TIMROT_TIMCTRL3_IRQ_V(e)                 BF_TIMROT_TIMCTRL3_IRQ(BV_TIMROT_TIMCTRL3_IRQ__##e)
+#define BFM_TIMROT_TIMCTRL3_IRQ_V(v)                BM_TIMROT_TIMCTRL3_IRQ
+#define BP_TIMROT_TIMCTRL3_IRQ_EN                   14
+#define BM_TIMROT_TIMCTRL3_IRQ_EN                   0x4000
+#define BF_TIMROT_TIMCTRL3_IRQ_EN(v)                (((v) & 0x1) << 14)
+#define BFM_TIMROT_TIMCTRL3_IRQ_EN(v)               BM_TIMROT_TIMCTRL3_IRQ_EN
+#define BF_TIMROT_TIMCTRL3_IRQ_EN_V(e)              BF_TIMROT_TIMCTRL3_IRQ_EN(BV_TIMROT_TIMCTRL3_IRQ_EN__##e)
+#define BFM_TIMROT_TIMCTRL3_IRQ_EN_V(v)             BM_TIMROT_TIMCTRL3_IRQ_EN
+#define BP_TIMROT_TIMCTRL3_RSRVD1                   11
+#define BM_TIMROT_TIMCTRL3_RSRVD1                   0x3800
+#define BF_TIMROT_TIMCTRL3_RSRVD1(v)                (((v) & 0x7) << 11)
+#define BFM_TIMROT_TIMCTRL3_RSRVD1(v)               BM_TIMROT_TIMCTRL3_RSRVD1
+#define BF_TIMROT_TIMCTRL3_RSRVD1_V(e)              BF_TIMROT_TIMCTRL3_RSRVD1(BV_TIMROT_TIMCTRL3_RSRVD1__##e)
+#define BFM_TIMROT_TIMCTRL3_RSRVD1_V(v)             BM_TIMROT_TIMCTRL3_RSRVD1
+#define BP_TIMROT_TIMCTRL3_DUTY_VALID               10
+#define BM_TIMROT_TIMCTRL3_DUTY_VALID               0x400
+#define BF_TIMROT_TIMCTRL3_DUTY_VALID(v)            (((v) & 0x1) << 10)
+#define BFM_TIMROT_TIMCTRL3_DUTY_VALID(v)           BM_TIMROT_TIMCTRL3_DUTY_VALID
+#define BF_TIMROT_TIMCTRL3_DUTY_VALID_V(e)          BF_TIMROT_TIMCTRL3_DUTY_VALID(BV_TIMROT_TIMCTRL3_DUTY_VALID__##e)
+#define BFM_TIMROT_TIMCTRL3_DUTY_VALID_V(v)         BM_TIMROT_TIMCTRL3_DUTY_VALID
+#define BP_TIMROT_TIMCTRL3_DUTY_CYCLE               9
+#define BM_TIMROT_TIMCTRL3_DUTY_CYCLE               0x200
+#define BF_TIMROT_TIMCTRL3_DUTY_CYCLE(v)            (((v) & 0x1) << 9)
+#define BFM_TIMROT_TIMCTRL3_DUTY_CYCLE(v)           BM_TIMROT_TIMCTRL3_DUTY_CYCLE
+#define BF_TIMROT_TIMCTRL3_DUTY_CYCLE_V(e)          BF_TIMROT_TIMCTRL3_DUTY_CYCLE(BV_TIMROT_TIMCTRL3_DUTY_CYCLE__##e)
+#define BFM_TIMROT_TIMCTRL3_DUTY_CYCLE_V(v)         BM_TIMROT_TIMCTRL3_DUTY_CYCLE
+#define BP_TIMROT_TIMCTRL3_POLARITY                 8
+#define BM_TIMROT_TIMCTRL3_POLARITY                 0x100
+#define BF_TIMROT_TIMCTRL3_POLARITY(v)              (((v) & 0x1) << 8)
+#define BFM_TIMROT_TIMCTRL3_POLARITY(v)             BM_TIMROT_TIMCTRL3_POLARITY
+#define BF_TIMROT_TIMCTRL3_POLARITY_V(e)            BF_TIMROT_TIMCTRL3_POLARITY(BV_TIMROT_TIMCTRL3_POLARITY__##e)
+#define BFM_TIMROT_TIMCTRL3_POLARITY_V(v)           BM_TIMROT_TIMCTRL3_POLARITY
+#define BP_TIMROT_TIMCTRL3_UPDATE                   7
+#define BM_TIMROT_TIMCTRL3_UPDATE                   0x80
+#define BF_TIMROT_TIMCTRL3_UPDATE(v)                (((v) & 0x1) << 7)
+#define BFM_TIMROT_TIMCTRL3_UPDATE(v)               BM_TIMROT_TIMCTRL3_UPDATE
+#define BF_TIMROT_TIMCTRL3_UPDATE_V(e)              BF_TIMROT_TIMCTRL3_UPDATE(BV_TIMROT_TIMCTRL3_UPDATE__##e)
+#define BFM_TIMROT_TIMCTRL3_UPDATE_V(v)             BM_TIMROT_TIMCTRL3_UPDATE
+#define BP_TIMROT_TIMCTRL3_RELOAD                   6
+#define BM_TIMROT_TIMCTRL3_RELOAD                   0x40
+#define BF_TIMROT_TIMCTRL3_RELOAD(v)                (((v) & 0x1) << 6)
+#define BFM_TIMROT_TIMCTRL3_RELOAD(v)               BM_TIMROT_TIMCTRL3_RELOAD
+#define BF_TIMROT_TIMCTRL3_RELOAD_V(e)              BF_TIMROT_TIMCTRL3_RELOAD(BV_TIMROT_TIMCTRL3_RELOAD__##e)
+#define BFM_TIMROT_TIMCTRL3_RELOAD_V(v)             BM_TIMROT_TIMCTRL3_RELOAD
+#define BP_TIMROT_TIMCTRL3_PRESCALE                 4
+#define BM_TIMROT_TIMCTRL3_PRESCALE                 0x30
+#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_1       0x0
+#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_2       0x1
+#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_4       0x2
+#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_8       0x3
+#define BF_TIMROT_TIMCTRL3_PRESCALE(v)              (((v) & 0x3) << 4)
+#define BFM_TIMROT_TIMCTRL3_PRESCALE(v)             BM_TIMROT_TIMCTRL3_PRESCALE
+#define BF_TIMROT_TIMCTRL3_PRESCALE_V(e)            BF_TIMROT_TIMCTRL3_PRESCALE(BV_TIMROT_TIMCTRL3_PRESCALE__##e)
+#define BFM_TIMROT_TIMCTRL3_PRESCALE_V(v)           BM_TIMROT_TIMCTRL3_PRESCALE
+#define BP_TIMROT_TIMCTRL3_SELECT                   0
+#define BM_TIMROT_TIMCTRL3_SELECT                   0xf
+#define BV_TIMROT_TIMCTRL3_SELECT__NEVER_TICK       0x0
+#define BV_TIMROT_TIMCTRL3_SELECT__PWM0             0x1
+#define BV_TIMROT_TIMCTRL3_SELECT__PWM1             0x2
+#define BV_TIMROT_TIMCTRL3_SELECT__PWM2             0x3
+#define BV_TIMROT_TIMCTRL3_SELECT__PWM3             0x4
+#define BV_TIMROT_TIMCTRL3_SELECT__PWM4             0x5
+#define BV_TIMROT_TIMCTRL3_SELECT__ROTARYA          0x6
+#define BV_TIMROT_TIMCTRL3_SELECT__ROTARYB          0x7
+#define BV_TIMROT_TIMCTRL3_SELECT__32KHZ_XTAL       0x8
+#define BV_TIMROT_TIMCTRL3_SELECT__8KHZ_XTAL        0x9
+#define BV_TIMROT_TIMCTRL3_SELECT__4KHZ_XTAL        0xa
+#define BV_TIMROT_TIMCTRL3_SELECT__1KHZ_XTAL        0xb
+#define BV_TIMROT_TIMCTRL3_SELECT__TICK_ALWAYS      0xc
+#define BF_TIMROT_TIMCTRL3_SELECT(v)                (((v) & 0xf) << 0)
+#define BFM_TIMROT_TIMCTRL3_SELECT(v)               BM_TIMROT_TIMCTRL3_SELECT
+#define BF_TIMROT_TIMCTRL3_SELECT_V(e)              BF_TIMROT_TIMCTRL3_SELECT(BV_TIMROT_TIMCTRL3_SELECT__##e)
+#define BFM_TIMROT_TIMCTRL3_SELECT_V(v)             BM_TIMROT_TIMCTRL3_SELECT
+
+#define HW_TIMROT_TIMCOUNT3                         HW(TIMROT_TIMCOUNT3)
+#define HWA_TIMROT_TIMCOUNT3                        (0x80068000 + 0x90)
+#define HWT_TIMROT_TIMCOUNT3                        HWIO_32_RW
+#define HWN_TIMROT_TIMCOUNT3                        TIMROT_TIMCOUNT3
+#define HWI_TIMROT_TIMCOUNT3                        
+#define BP_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT       16
+#define BM_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT       0xffff0000
+#define BF_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT(v)    (((v) & 0xffff) << 16)
+#define BFM_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT(v)   BM_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT
+#define BF_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT_V(e)  BF_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT(BV_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT__##e)
+#define BFM_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT_V(v) BM_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT
+#define BP_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT        0
+#define BM_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT        0xffff
+#define BF_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT(v)     (((v) & 0xffff) << 0)
+#define BFM_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT(v)    BM_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT
+#define BF_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT_V(e)   BF_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT(BV_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT__##e)
+#define BFM_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT_V(v)  BM_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT
+
+#define HW_TIMROT_VERSION               HW(TIMROT_VERSION)
+#define HWA_TIMROT_VERSION              (0x80068000 + 0xa0)
+#define HWT_TIMROT_VERSION              HWIO_32_RW
+#define HWN_TIMROT_VERSION              TIMROT_VERSION
+#define HWI_TIMROT_VERSION              
+#define BP_TIMROT_VERSION_MAJOR         24
+#define BM_TIMROT_VERSION_MAJOR         0xff000000
+#define BF_TIMROT_VERSION_MAJOR(v)      (((v) & 0xff) << 24)
+#define BFM_TIMROT_VERSION_MAJOR(v)     BM_TIMROT_VERSION_MAJOR
+#define BF_TIMROT_VERSION_MAJOR_V(e)    BF_TIMROT_VERSION_MAJOR(BV_TIMROT_VERSION_MAJOR__##e)
+#define BFM_TIMROT_VERSION_MAJOR_V(v)   BM_TIMROT_VERSION_MAJOR
+#define BP_TIMROT_VERSION_MINOR         16
+#define BM_TIMROT_VERSION_MINOR         0xff0000
+#define BF_TIMROT_VERSION_MINOR(v)      (((v) & 0xff) << 16)
+#define BFM_TIMROT_VERSION_MINOR(v)     BM_TIMROT_VERSION_MINOR
+#define BF_TIMROT_VERSION_MINOR_V(e)    BF_TIMROT_VERSION_MINOR(BV_TIMROT_VERSION_MINOR__##e)
+#define BFM_TIMROT_VERSION_MINOR_V(v)   BM_TIMROT_VERSION_MINOR
+#define BP_TIMROT_VERSION_STEP          0
+#define BM_TIMROT_VERSION_STEP          0xffff
+#define BF_TIMROT_VERSION_STEP(v)       (((v) & 0xffff) << 0)
+#define BFM_TIMROT_VERSION_STEP(v)      BM_TIMROT_VERSION_STEP
+#define BF_TIMROT_VERSION_STEP_V(e)     BF_TIMROT_VERSION_STEP(BV_TIMROT_VERSION_STEP__##e)
+#define BFM_TIMROT_VERSION_STEP_V(v)    BM_TIMROT_VERSION_STEP
+
+#endif /* __HEADERGEN_IMX233_TIMROT_H__*/
diff --git a/firmware/target/arm/imx233/regs/imx233/tvenc.h b/firmware/target/arm/imx233/regs/imx233/tvenc.h
new file mode 100644
index 0000000000..8dd95688cf
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/imx233/tvenc.h
@@ -0,0 +1,1536 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * imx233 version: 2.4.0
+ * imx233 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_IMX233_TVENC_H__
+#define __HEADERGEN_IMX233_TVENC_H__
+
+#define HW_TVENC_CTRL                                   HW(TVENC_CTRL)
+#define HWA_TVENC_CTRL                                  (0x80038000 + 0x0)
+#define HWT_TVENC_CTRL                                  HWIO_32_RW
+#define HWN_TVENC_CTRL                                  TVENC_CTRL
+#define HWI_TVENC_CTRL                                  
+#define HW_TVENC_CTRL_SET                               HW(TVENC_CTRL_SET)
+#define HWA_TVENC_CTRL_SET                              (HWA_TVENC_CTRL + 0x4)
+#define HWT_TVENC_CTRL_SET                              HWIO_32_WO
+#define HWN_TVENC_CTRL_SET                              TVENC_CTRL
+#define HWI_TVENC_CTRL_SET                              
+#define HW_TVENC_CTRL_CLR                               HW(TVENC_CTRL_CLR)
+#define HWA_TVENC_CTRL_CLR                              (HWA_TVENC_CTRL + 0x8)
+#define HWT_TVENC_CTRL_CLR                              HWIO_32_WO
+#define HWN_TVENC_CTRL_CLR                              TVENC_CTRL
+#define HWI_TVENC_CTRL_CLR                              
+#define HW_TVENC_CTRL_TOG                               HW(TVENC_CTRL_TOG)
+#define HWA_TVENC_CTRL_TOG                              (HWA_TVENC_CTRL + 0xc)
+#define HWT_TVENC_CTRL_TOG                              HWIO_32_WO
+#define HWN_TVENC_CTRL_TOG                              TVENC_CTRL
+#define HWI_TVENC_CTRL_TOG                              
+#define BP_TVENC_CTRL_SFTRST                            31
+#define BM_TVENC_CTRL_SFTRST                            0x80000000
+#define BF_TVENC_CTRL_SFTRST(v)                         (((v) & 0x1) << 31)
+#define BFM_TVENC_CTRL_SFTRST(v)                        BM_TVENC_CTRL_SFTRST
+#define BF_TVENC_CTRL_SFTRST_V(e)                       BF_TVENC_CTRL_SFTRST(BV_TVENC_CTRL_SFTRST__##e)
+#define BFM_TVENC_CTRL_SFTRST_V(v)                      BM_TVENC_CTRL_SFTRST
+#define BP_TVENC_CTRL_CLKGATE                           30
+#define BM_TVENC_CTRL_CLKGATE                           0x40000000
+#define BF_TVENC_CTRL_CLKGATE(v)                        (((v) & 0x1) << 30)
+#define BFM_TVENC_CTRL_CLKGATE(v)                       BM_TVENC_CTRL_CLKGATE
+#define BF_TVENC_CTRL_CLKGATE_V(e)                      BF_TVENC_CTRL_CLKGATE(BV_TVENC_CTRL_CLKGATE__##e)
+#define BFM_TVENC_CTRL_CLKGATE_V(v)                     BM_TVENC_CTRL_CLKGATE
+#define BP_TVENC_CTRL_TVENC_MACROVISION_PRESENT         29
+#define BM_TVENC_CTRL_TVENC_MACROVISION_PRESENT         0x20000000
+#define BF_TVENC_CTRL_TVENC_MACROVISION_PRESENT(v)      (((v) & 0x1) << 29)
+#define BFM_TVENC_CTRL_TVENC_MACROVISION_PRESENT(v)     BM_TVENC_CTRL_TVENC_MACROVISION_PRESENT
+#define BF_TVENC_CTRL_TVENC_MACROVISION_PRESENT_V(e)    BF_TVENC_CTRL_TVENC_MACROVISION_PRESENT(BV_TVENC_CTRL_TVENC_MACROVISION_PRESENT__##e)
+#define BFM_TVENC_CTRL_TVENC_MACROVISION_PRESENT_V(v)   BM_TVENC_CTRL_TVENC_MACROVISION_PRESENT
+#define BP_TVENC_CTRL_TVENC_COMPOSITE_PRESENT           28
+#define BM_TVENC_CTRL_TVENC_COMPOSITE_PRESENT           0x10000000
+#define BF_TVENC_CTRL_TVENC_COMPOSITE_PRESENT(v)        (((v) & 0x1) << 28)
+#define BFM_TVENC_CTRL_TVENC_COMPOSITE_PRESENT(v)       BM_TVENC_CTRL_TVENC_COMPOSITE_PRESENT
+#define BF_TVENC_CTRL_TVENC_COMPOSITE_PRESENT_V(e)      BF_TVENC_CTRL_TVENC_COMPOSITE_PRESENT(BV_TVENC_CTRL_TVENC_COMPOSITE_PRESENT__##e)
+#define BFM_TVENC_CTRL_TVENC_COMPOSITE_PRESENT_V(v)     BM_TVENC_CTRL_TVENC_COMPOSITE_PRESENT
+#define BP_TVENC_CTRL_TVENC_SVIDEO_PRESENT              27
+#define BM_TVENC_CTRL_TVENC_SVIDEO_PRESENT              0x8000000
+#define BF_TVENC_CTRL_TVENC_SVIDEO_PRESENT(v)           (((v) & 0x1) << 27)
+#define BFM_TVENC_CTRL_TVENC_SVIDEO_PRESENT(v)          BM_TVENC_CTRL_TVENC_SVIDEO_PRESENT
+#define BF_TVENC_CTRL_TVENC_SVIDEO_PRESENT_V(e)         BF_TVENC_CTRL_TVENC_SVIDEO_PRESENT(BV_TVENC_CTRL_TVENC_SVIDEO_PRESENT__##e)
+#define BFM_TVENC_CTRL_TVENC_SVIDEO_PRESENT_V(v)        BM_TVENC_CTRL_TVENC_SVIDEO_PRESENT
+#define BP_TVENC_CTRL_TVENC_COMPONENT_PRESENT           26
+#define BM_TVENC_CTRL_TVENC_COMPONENT_PRESENT           0x4000000
+#define BF_TVENC_CTRL_TVENC_COMPONENT_PRESENT(v)        (((v) & 0x1) << 26)
+#define BFM_TVENC_CTRL_TVENC_COMPONENT_PRESENT(v)       BM_TVENC_CTRL_TVENC_COMPONENT_PRESENT
+#define BF_TVENC_CTRL_TVENC_COMPONENT_PRESENT_V(e)      BF_TVENC_CTRL_TVENC_COMPONENT_PRESENT(BV_TVENC_CTRL_TVENC_COMPONENT_PRESENT__##e)
+#define BFM_TVENC_CTRL_TVENC_COMPONENT_PRESENT_V(v)     BM_TVENC_CTRL_TVENC_COMPONENT_PRESENT
+#define BP_TVENC_CTRL_RSRVD1                            6
+#define BM_TVENC_CTRL_RSRVD1                            0x3ffffc0
+#define BF_TVENC_CTRL_RSRVD1(v)                         (((v) & 0xfffff) << 6)
+#define BFM_TVENC_CTRL_RSRVD1(v)                        BM_TVENC_CTRL_RSRVD1
+#define BF_TVENC_CTRL_RSRVD1_V(e)                       BF_TVENC_CTRL_RSRVD1(BV_TVENC_CTRL_RSRVD1__##e)
+#define BFM_TVENC_CTRL_RSRVD1_V(v)                      BM_TVENC_CTRL_RSRVD1
+#define BP_TVENC_CTRL_DAC_FIFO_NO_WRITE                 5
+#define BM_TVENC_CTRL_DAC_FIFO_NO_WRITE                 0x20
+#define BF_TVENC_CTRL_DAC_FIFO_NO_WRITE(v)              (((v) & 0x1) << 5)
+#define BFM_TVENC_CTRL_DAC_FIFO_NO_WRITE(v)             BM_TVENC_CTRL_DAC_FIFO_NO_WRITE
+#define BF_TVENC_CTRL_DAC_FIFO_NO_WRITE_V(e)            BF_TVENC_CTRL_DAC_FIFO_NO_WRITE(BV_TVENC_CTRL_DAC_FIFO_NO_WRITE__##e)
+#define BFM_TVENC_CTRL_DAC_FIFO_NO_WRITE_V(v)           BM_TVENC_CTRL_DAC_FIFO_NO_WRITE
+#define BP_TVENC_CTRL_DAC_FIFO_NO_READ                  4
+#define BM_TVENC_CTRL_DAC_FIFO_NO_READ                  0x10
+#define BF_TVENC_CTRL_DAC_FIFO_NO_READ(v)               (((v) & 0x1) << 4)
+#define BFM_TVENC_CTRL_DAC_FIFO_NO_READ(v)              BM_TVENC_CTRL_DAC_FIFO_NO_READ
+#define BF_TVENC_CTRL_DAC_FIFO_NO_READ_V(e)             BF_TVENC_CTRL_DAC_FIFO_NO_READ(BV_TVENC_CTRL_DAC_FIFO_NO_READ__##e)
+#define BFM_TVENC_CTRL_DAC_FIFO_NO_READ_V(v)            BM_TVENC_CTRL_DAC_FIFO_NO_READ
+#define BP_TVENC_CTRL_DAC_DATA_FIFO_RST                 3
+#define BM_TVENC_CTRL_DAC_DATA_FIFO_RST                 0x8
+#define BF_TVENC_CTRL_DAC_DATA_FIFO_RST(v)              (((v) & 0x1) << 3)
+#define BFM_TVENC_CTRL_DAC_DATA_FIFO_RST(v)             BM_TVENC_CTRL_DAC_DATA_FIFO_RST
+#define BF_TVENC_CTRL_DAC_DATA_FIFO_RST_V(e)            BF_TVENC_CTRL_DAC_DATA_FIFO_RST(BV_TVENC_CTRL_DAC_DATA_FIFO_RST__##e)
+#define BFM_TVENC_CTRL_DAC_DATA_FIFO_RST_V(v)           BM_TVENC_CTRL_DAC_DATA_FIFO_RST
+#define BP_TVENC_CTRL_RSRVD2                            1
+#define BM_TVENC_CTRL_RSRVD2                            0x6
+#define BF_TVENC_CTRL_RSRVD2(v)                         (((v) & 0x3) << 1)
+#define BFM_TVENC_CTRL_RSRVD2(v)                        BM_TVENC_CTRL_RSRVD2
+#define BF_TVENC_CTRL_RSRVD2_V(e)                       BF_TVENC_CTRL_RSRVD2(BV_TVENC_CTRL_RSRVD2__##e)
+#define BFM_TVENC_CTRL_RSRVD2_V(v)                      BM_TVENC_CTRL_RSRVD2
+#define BP_TVENC_CTRL_DAC_MUX_MODE                      0
+#define BM_TVENC_CTRL_DAC_MUX_MODE                      0x1
+#define BF_TVENC_CTRL_DAC_MUX_MODE(v)                   (((v) & 0x1) << 0)
+#define BFM_TVENC_CTRL_DAC_MUX_MODE(v)                  BM_TVENC_CTRL_DAC_MUX_MODE
+#define BF_TVENC_CTRL_DAC_MUX_MODE_V(e)                 BF_TVENC_CTRL_DAC_MUX_MODE(BV_TVENC_CTRL_DAC_MUX_MODE__##e)
+#define BFM_TVENC_CTRL_DAC_MUX_MODE_V(v)                BM_TVENC_CTRL_DAC_MUX_MODE
+
+#define HW_TVENC_CONFIG                         HW(TVENC_CONFIG)
+#define HWA_TVENC_CONFIG                        (0x80038000 + 0x10)
+#define HWT_TVENC_CONFIG                        HWIO_32_RW
+#define HWN_TVENC_CONFIG                        TVENC_CONFIG
+#define HWI_TVENC_CONFIG                        
+#define HW_TVENC_CONFIG_SET                     HW(TVENC_CONFIG_SET)
+#define HWA_TVENC_CONFIG_SET                    (HWA_TVENC_CONFIG + 0x4)
+#define HWT_TVENC_CONFIG_SET                    HWIO_32_WO
+#define HWN_TVENC_CONFIG_SET                    TVENC_CONFIG
+#define HWI_TVENC_CONFIG_SET                    
+#define HW_TVENC_CONFIG_CLR                     HW(TVENC_CONFIG_CLR)
+#define HWA_TVENC_CONFIG_CLR                    (HWA_TVENC_CONFIG + 0x8)
+#define HWT_TVENC_CONFIG_CLR                    HWIO_32_WO
+#define HWN_TVENC_CONFIG_CLR                    TVENC_CONFIG
+#define HWI_TVENC_CONFIG_CLR                    
+#define HW_TVENC_CONFIG_TOG                     HW(TVENC_CONFIG_TOG)
+#define HWA_TVENC_CONFIG_TOG                    (HWA_TVENC_CONFIG + 0xc)
+#define HWT_TVENC_CONFIG_TOG                    HWIO_32_WO
+#define HWN_TVENC_CONFIG_TOG                    TVENC_CONFIG
+#define HWI_TVENC_CONFIG_TOG                    
+#define BP_TVENC_CONFIG_RSRVD5                  28
+#define BM_TVENC_CONFIG_RSRVD5                  0xf0000000
+#define BF_TVENC_CONFIG_RSRVD5(v)               (((v) & 0xf) << 28)
+#define BFM_TVENC_CONFIG_RSRVD5(v)              BM_TVENC_CONFIG_RSRVD5
+#define BF_TVENC_CONFIG_RSRVD5_V(e)             BF_TVENC_CONFIG_RSRVD5(BV_TVENC_CONFIG_RSRVD5__##e)
+#define BFM_TVENC_CONFIG_RSRVD5_V(v)            BM_TVENC_CONFIG_RSRVD5
+#define BP_TVENC_CONFIG_DEFAULT_PICFORM         27
+#define BM_TVENC_CONFIG_DEFAULT_PICFORM         0x8000000
+#define BF_TVENC_CONFIG_DEFAULT_PICFORM(v)      (((v) & 0x1) << 27)
+#define BFM_TVENC_CONFIG_DEFAULT_PICFORM(v)     BM_TVENC_CONFIG_DEFAULT_PICFORM
+#define BF_TVENC_CONFIG_DEFAULT_PICFORM_V(e)    BF_TVENC_CONFIG_DEFAULT_PICFORM(BV_TVENC_CONFIG_DEFAULT_PICFORM__##e)
+#define BFM_TVENC_CONFIG_DEFAULT_PICFORM_V(v)   BM_TVENC_CONFIG_DEFAULT_PICFORM
+#define BP_TVENC_CONFIG_YDEL_ADJ                24
+#define BM_TVENC_CONFIG_YDEL_ADJ                0x7000000
+#define BF_TVENC_CONFIG_YDEL_ADJ(v)             (((v) & 0x7) << 24)
+#define BFM_TVENC_CONFIG_YDEL_ADJ(v)            BM_TVENC_CONFIG_YDEL_ADJ
+#define BF_TVENC_CONFIG_YDEL_ADJ_V(e)           BF_TVENC_CONFIG_YDEL_ADJ(BV_TVENC_CONFIG_YDEL_ADJ__##e)
+#define BFM_TVENC_CONFIG_YDEL_ADJ_V(v)          BM_TVENC_CONFIG_YDEL_ADJ
+#define BP_TVENC_CONFIG_RSRVD4                  23
+#define BM_TVENC_CONFIG_RSRVD4                  0x800000
+#define BF_TVENC_CONFIG_RSRVD4(v)               (((v) & 0x1) << 23)
+#define BFM_TVENC_CONFIG_RSRVD4(v)              BM_TVENC_CONFIG_RSRVD4
+#define BF_TVENC_CONFIG_RSRVD4_V(e)             BF_TVENC_CONFIG_RSRVD4(BV_TVENC_CONFIG_RSRVD4__##e)
+#define BFM_TVENC_CONFIG_RSRVD4_V(v)            BM_TVENC_CONFIG_RSRVD4
+#define BP_TVENC_CONFIG_RSRVD3                  22
+#define BM_TVENC_CONFIG_RSRVD3                  0x400000
+#define BF_TVENC_CONFIG_RSRVD3(v)               (((v) & 0x1) << 22)
+#define BFM_TVENC_CONFIG_RSRVD3(v)              BM_TVENC_CONFIG_RSRVD3
+#define BF_TVENC_CONFIG_RSRVD3_V(e)             BF_TVENC_CONFIG_RSRVD3(BV_TVENC_CONFIG_RSRVD3__##e)
+#define BFM_TVENC_CONFIG_RSRVD3_V(v)            BM_TVENC_CONFIG_RSRVD3
+#define BP_TVENC_CONFIG_ADD_YPBPR_PED           21
+#define BM_TVENC_CONFIG_ADD_YPBPR_PED           0x200000
+#define BF_TVENC_CONFIG_ADD_YPBPR_PED(v)        (((v) & 0x1) << 21)
+#define BFM_TVENC_CONFIG_ADD_YPBPR_PED(v)       BM_TVENC_CONFIG_ADD_YPBPR_PED
+#define BF_TVENC_CONFIG_ADD_YPBPR_PED_V(e)      BF_TVENC_CONFIG_ADD_YPBPR_PED(BV_TVENC_CONFIG_ADD_YPBPR_PED__##e)
+#define BFM_TVENC_CONFIG_ADD_YPBPR_PED_V(v)     BM_TVENC_CONFIG_ADD_YPBPR_PED
+#define BP_TVENC_CONFIG_PAL_SHAPE               20
+#define BM_TVENC_CONFIG_PAL_SHAPE               0x100000
+#define BF_TVENC_CONFIG_PAL_SHAPE(v)            (((v) & 0x1) << 20)
+#define BFM_TVENC_CONFIG_PAL_SHAPE(v)           BM_TVENC_CONFIG_PAL_SHAPE
+#define BF_TVENC_CONFIG_PAL_SHAPE_V(e)          BF_TVENC_CONFIG_PAL_SHAPE(BV_TVENC_CONFIG_PAL_SHAPE__##e)
+#define BFM_TVENC_CONFIG_PAL_SHAPE_V(v)         BM_TVENC_CONFIG_PAL_SHAPE
+#define BP_TVENC_CONFIG_NO_PED                  19
+#define BM_TVENC_CONFIG_NO_PED                  0x80000
+#define BF_TVENC_CONFIG_NO_PED(v)               (((v) & 0x1) << 19)
+#define BFM_TVENC_CONFIG_NO_PED(v)              BM_TVENC_CONFIG_NO_PED
+#define BF_TVENC_CONFIG_NO_PED_V(e)             BF_TVENC_CONFIG_NO_PED(BV_TVENC_CONFIG_NO_PED__##e)
+#define BFM_TVENC_CONFIG_NO_PED_V(v)            BM_TVENC_CONFIG_NO_PED
+#define BP_TVENC_CONFIG_COLOR_BAR_EN            18
+#define BM_TVENC_CONFIG_COLOR_BAR_EN            0x40000
+#define BF_TVENC_CONFIG_COLOR_BAR_EN(v)         (((v) & 0x1) << 18)
+#define BFM_TVENC_CONFIG_COLOR_BAR_EN(v)        BM_TVENC_CONFIG_COLOR_BAR_EN
+#define BF_TVENC_CONFIG_COLOR_BAR_EN_V(e)       BF_TVENC_CONFIG_COLOR_BAR_EN(BV_TVENC_CONFIG_COLOR_BAR_EN__##e)
+#define BFM_TVENC_CONFIG_COLOR_BAR_EN_V(v)      BM_TVENC_CONFIG_COLOR_BAR_EN
+#define BP_TVENC_CONFIG_YGAIN_SEL               16
+#define BM_TVENC_CONFIG_YGAIN_SEL               0x30000
+#define BF_TVENC_CONFIG_YGAIN_SEL(v)            (((v) & 0x3) << 16)
+#define BFM_TVENC_CONFIG_YGAIN_SEL(v)           BM_TVENC_CONFIG_YGAIN_SEL
+#define BF_TVENC_CONFIG_YGAIN_SEL_V(e)          BF_TVENC_CONFIG_YGAIN_SEL(BV_TVENC_CONFIG_YGAIN_SEL__##e)
+#define BFM_TVENC_CONFIG_YGAIN_SEL_V(v)         BM_TVENC_CONFIG_YGAIN_SEL
+#define BP_TVENC_CONFIG_CGAIN                   14
+#define BM_TVENC_CONFIG_CGAIN                   0xc000
+#define BF_TVENC_CONFIG_CGAIN(v)                (((v) & 0x3) << 14)
+#define BFM_TVENC_CONFIG_CGAIN(v)               BM_TVENC_CONFIG_CGAIN
+#define BF_TVENC_CONFIG_CGAIN_V(e)              BF_TVENC_CONFIG_CGAIN(BV_TVENC_CONFIG_CGAIN__##e)
+#define BFM_TVENC_CONFIG_CGAIN_V(v)             BM_TVENC_CONFIG_CGAIN
+#define BP_TVENC_CONFIG_CLK_PHS                 12
+#define BM_TVENC_CONFIG_CLK_PHS                 0x3000
+#define BF_TVENC_CONFIG_CLK_PHS(v)              (((v) & 0x3) << 12)
+#define BFM_TVENC_CONFIG_CLK_PHS(v)             BM_TVENC_CONFIG_CLK_PHS
+#define BF_TVENC_CONFIG_CLK_PHS_V(e)            BF_TVENC_CONFIG_CLK_PHS(BV_TVENC_CONFIG_CLK_PHS__##e)
+#define BFM_TVENC_CONFIG_CLK_PHS_V(v)           BM_TVENC_CONFIG_CLK_PHS
+#define BP_TVENC_CONFIG_RSRVD2                  11
+#define BM_TVENC_CONFIG_RSRVD2                  0x800
+#define BF_TVENC_CONFIG_RSRVD2(v)               (((v) & 0x1) << 11)
+#define BFM_TVENC_CONFIG_RSRVD2(v)              BM_TVENC_CONFIG_RSRVD2
+#define BF_TVENC_CONFIG_RSRVD2_V(e)             BF_TVENC_CONFIG_RSRVD2(BV_TVENC_CONFIG_RSRVD2__##e)
+#define BFM_TVENC_CONFIG_RSRVD2_V(v)            BM_TVENC_CONFIG_RSRVD2
+#define BP_TVENC_CONFIG_FSYNC_ENBL              10
+#define BM_TVENC_CONFIG_FSYNC_ENBL              0x400
+#define BF_TVENC_CONFIG_FSYNC_ENBL(v)           (((v) & 0x1) << 10)
+#define BFM_TVENC_CONFIG_FSYNC_ENBL(v)          BM_TVENC_CONFIG_FSYNC_ENBL
+#define BF_TVENC_CONFIG_FSYNC_ENBL_V(e)         BF_TVENC_CONFIG_FSYNC_ENBL(BV_TVENC_CONFIG_FSYNC_ENBL__##e)
+#define BFM_TVENC_CONFIG_FSYNC_ENBL_V(v)        BM_TVENC_CONFIG_FSYNC_ENBL
+#define BP_TVENC_CONFIG_FSYNC_PHS               9
+#define BM_TVENC_CONFIG_FSYNC_PHS               0x200
+#define BF_TVENC_CONFIG_FSYNC_PHS(v)            (((v) & 0x1) << 9)
+#define BFM_TVENC_CONFIG_FSYNC_PHS(v)           BM_TVENC_CONFIG_FSYNC_PHS
+#define BF_TVENC_CONFIG_FSYNC_PHS_V(e)          BF_TVENC_CONFIG_FSYNC_PHS(BV_TVENC_CONFIG_FSYNC_PHS__##e)
+#define BFM_TVENC_CONFIG_FSYNC_PHS_V(v)         BM_TVENC_CONFIG_FSYNC_PHS
+#define BP_TVENC_CONFIG_HSYNC_PHS               8
+#define BM_TVENC_CONFIG_HSYNC_PHS               0x100
+#define BF_TVENC_CONFIG_HSYNC_PHS(v)            (((v) & 0x1) << 8)
+#define BFM_TVENC_CONFIG_HSYNC_PHS(v)           BM_TVENC_CONFIG_HSYNC_PHS
+#define BF_TVENC_CONFIG_HSYNC_PHS_V(e)          BF_TVENC_CONFIG_HSYNC_PHS(BV_TVENC_CONFIG_HSYNC_PHS__##e)
+#define BFM_TVENC_CONFIG_HSYNC_PHS_V(v)         BM_TVENC_CONFIG_HSYNC_PHS
+#define BP_TVENC_CONFIG_VSYNC_PHS               7
+#define BM_TVENC_CONFIG_VSYNC_PHS               0x80
+#define BF_TVENC_CONFIG_VSYNC_PHS(v)            (((v) & 0x1) << 7)
+#define BFM_TVENC_CONFIG_VSYNC_PHS(v)           BM_TVENC_CONFIG_VSYNC_PHS
+#define BF_TVENC_CONFIG_VSYNC_PHS_V(e)          BF_TVENC_CONFIG_VSYNC_PHS(BV_TVENC_CONFIG_VSYNC_PHS__##e)
+#define BFM_TVENC_CONFIG_VSYNC_PHS_V(v)         BM_TVENC_CONFIG_VSYNC_PHS
+#define BP_TVENC_CONFIG_SYNC_MODE               4
+#define BM_TVENC_CONFIG_SYNC_MODE               0x70
+#define BF_TVENC_CONFIG_SYNC_MODE(v)            (((v) & 0x7) << 4)
+#define BFM_TVENC_CONFIG_SYNC_MODE(v)           BM_TVENC_CONFIG_SYNC_MODE
+#define BF_TVENC_CONFIG_SYNC_MODE_V(e)          BF_TVENC_CONFIG_SYNC_MODE(BV_TVENC_CONFIG_SYNC_MODE__##e)
+#define BFM_TVENC_CONFIG_SYNC_MODE_V(v)         BM_TVENC_CONFIG_SYNC_MODE
+#define BP_TVENC_CONFIG_RSRVD1                  3
+#define BM_TVENC_CONFIG_RSRVD1                  0x8
+#define BF_TVENC_CONFIG_RSRVD1(v)               (((v) & 0x1) << 3)
+#define BFM_TVENC_CONFIG_RSRVD1(v)              BM_TVENC_CONFIG_RSRVD1
+#define BF_TVENC_CONFIG_RSRVD1_V(e)             BF_TVENC_CONFIG_RSRVD1(BV_TVENC_CONFIG_RSRVD1__##e)
+#define BFM_TVENC_CONFIG_RSRVD1_V(v)            BM_TVENC_CONFIG_RSRVD1
+#define BP_TVENC_CONFIG_ENCD_MODE               0
+#define BM_TVENC_CONFIG_ENCD_MODE               0x7
+#define BF_TVENC_CONFIG_ENCD_MODE(v)            (((v) & 0x7) << 0)
+#define BFM_TVENC_CONFIG_ENCD_MODE(v)           BM_TVENC_CONFIG_ENCD_MODE
+#define BF_TVENC_CONFIG_ENCD_MODE_V(e)          BF_TVENC_CONFIG_ENCD_MODE(BV_TVENC_CONFIG_ENCD_MODE__##e)
+#define BFM_TVENC_CONFIG_ENCD_MODE_V(v)         BM_TVENC_CONFIG_ENCD_MODE
+
+#define HW_TVENC_FILTCTRL                       HW(TVENC_FILTCTRL)
+#define HWA_TVENC_FILTCTRL                      (0x80038000 + 0x20)
+#define HWT_TVENC_FILTCTRL                      HWIO_32_RW
+#define HWN_TVENC_FILTCTRL                      TVENC_FILTCTRL
+#define HWI_TVENC_FILTCTRL                      
+#define HW_TVENC_FILTCTRL_SET                   HW(TVENC_FILTCTRL_SET)
+#define HWA_TVENC_FILTCTRL_SET                  (HWA_TVENC_FILTCTRL + 0x4)
+#define HWT_TVENC_FILTCTRL_SET                  HWIO_32_WO
+#define HWN_TVENC_FILTCTRL_SET                  TVENC_FILTCTRL
+#define HWI_TVENC_FILTCTRL_SET                  
+#define HW_TVENC_FILTCTRL_CLR                   HW(TVENC_FILTCTRL_CLR)
+#define HWA_TVENC_FILTCTRL_CLR                  (HWA_TVENC_FILTCTRL + 0x8)
+#define HWT_TVENC_FILTCTRL_CLR                  HWIO_32_WO
+#define HWN_TVENC_FILTCTRL_CLR                  TVENC_FILTCTRL
+#define HWI_TVENC_FILTCTRL_CLR                  
+#define HW_TVENC_FILTCTRL_TOG                   HW(TVENC_FILTCTRL_TOG)
+#define HWA_TVENC_FILTCTRL_TOG                  (HWA_TVENC_FILTCTRL + 0xc)
+#define HWT_TVENC_FILTCTRL_TOG                  HWIO_32_WO
+#define HWN_TVENC_FILTCTRL_TOG                  TVENC_FILTCTRL
+#define HWI_TVENC_FILTCTRL_TOG                  
+#define BP_TVENC_FILTCTRL_RSRVD1                20
+#define BM_TVENC_FILTCTRL_RSRVD1                0xfff00000
+#define BF_TVENC_FILTCTRL_RSRVD1(v)             (((v) & 0xfff) << 20)
+#define BFM_TVENC_FILTCTRL_RSRVD1(v)            BM_TVENC_FILTCTRL_RSRVD1
+#define BF_TVENC_FILTCTRL_RSRVD1_V(e)           BF_TVENC_FILTCTRL_RSRVD1(BV_TVENC_FILTCTRL_RSRVD1__##e)
+#define BFM_TVENC_FILTCTRL_RSRVD1_V(v)          BM_TVENC_FILTCTRL_RSRVD1
+#define BP_TVENC_FILTCTRL_YSHARP_BW             19
+#define BM_TVENC_FILTCTRL_YSHARP_BW             0x80000
+#define BF_TVENC_FILTCTRL_YSHARP_BW(v)          (((v) & 0x1) << 19)
+#define BFM_TVENC_FILTCTRL_YSHARP_BW(v)         BM_TVENC_FILTCTRL_YSHARP_BW
+#define BF_TVENC_FILTCTRL_YSHARP_BW_V(e)        BF_TVENC_FILTCTRL_YSHARP_BW(BV_TVENC_FILTCTRL_YSHARP_BW__##e)
+#define BFM_TVENC_FILTCTRL_YSHARP_BW_V(v)       BM_TVENC_FILTCTRL_YSHARP_BW
+#define BP_TVENC_FILTCTRL_YD_OFFSETSEL          18
+#define BM_TVENC_FILTCTRL_YD_OFFSETSEL          0x40000
+#define BF_TVENC_FILTCTRL_YD_OFFSETSEL(v)       (((v) & 0x1) << 18)
+#define BFM_TVENC_FILTCTRL_YD_OFFSETSEL(v)      BM_TVENC_FILTCTRL_YD_OFFSETSEL
+#define BF_TVENC_FILTCTRL_YD_OFFSETSEL_V(e)     BF_TVENC_FILTCTRL_YD_OFFSETSEL(BV_TVENC_FILTCTRL_YD_OFFSETSEL__##e)
+#define BFM_TVENC_FILTCTRL_YD_OFFSETSEL_V(v)    BM_TVENC_FILTCTRL_YD_OFFSETSEL
+#define BP_TVENC_FILTCTRL_SEL_YLPF              17
+#define BM_TVENC_FILTCTRL_SEL_YLPF              0x20000
+#define BF_TVENC_FILTCTRL_SEL_YLPF(v)           (((v) & 0x1) << 17)
+#define BFM_TVENC_FILTCTRL_SEL_YLPF(v)          BM_TVENC_FILTCTRL_SEL_YLPF
+#define BF_TVENC_FILTCTRL_SEL_YLPF_V(e)         BF_TVENC_FILTCTRL_SEL_YLPF(BV_TVENC_FILTCTRL_SEL_YLPF__##e)
+#define BFM_TVENC_FILTCTRL_SEL_YLPF_V(v)        BM_TVENC_FILTCTRL_SEL_YLPF
+#define BP_TVENC_FILTCTRL_SEL_CLPF              16
+#define BM_TVENC_FILTCTRL_SEL_CLPF              0x10000
+#define BF_TVENC_FILTCTRL_SEL_CLPF(v)           (((v) & 0x1) << 16)
+#define BFM_TVENC_FILTCTRL_SEL_CLPF(v)          BM_TVENC_FILTCTRL_SEL_CLPF
+#define BF_TVENC_FILTCTRL_SEL_CLPF_V(e)         BF_TVENC_FILTCTRL_SEL_CLPF(BV_TVENC_FILTCTRL_SEL_CLPF__##e)
+#define BFM_TVENC_FILTCTRL_SEL_CLPF_V(v)        BM_TVENC_FILTCTRL_SEL_CLPF
+#define BP_TVENC_FILTCTRL_SEL_YSHARP            15
+#define BM_TVENC_FILTCTRL_SEL_YSHARP            0x8000
+#define BF_TVENC_FILTCTRL_SEL_YSHARP(v)         (((v) & 0x1) << 15)
+#define BFM_TVENC_FILTCTRL_SEL_YSHARP(v)        BM_TVENC_FILTCTRL_SEL_YSHARP
+#define BF_TVENC_FILTCTRL_SEL_YSHARP_V(e)       BF_TVENC_FILTCTRL_SEL_YSHARP(BV_TVENC_FILTCTRL_SEL_YSHARP__##e)
+#define BFM_TVENC_FILTCTRL_SEL_YSHARP_V(v)      BM_TVENC_FILTCTRL_SEL_YSHARP
+#define BP_TVENC_FILTCTRL_YLPF_COEFSEL          14
+#define BM_TVENC_FILTCTRL_YLPF_COEFSEL          0x4000
+#define BF_TVENC_FILTCTRL_YLPF_COEFSEL(v)       (((v) & 0x1) << 14)
+#define BFM_TVENC_FILTCTRL_YLPF_COEFSEL(v)      BM_TVENC_FILTCTRL_YLPF_COEFSEL
+#define BF_TVENC_FILTCTRL_YLPF_COEFSEL_V(e)     BF_TVENC_FILTCTRL_YLPF_COEFSEL(BV_TVENC_FILTCTRL_YLPF_COEFSEL__##e)
+#define BFM_TVENC_FILTCTRL_YLPF_COEFSEL_V(v)    BM_TVENC_FILTCTRL_YLPF_COEFSEL
+#define BP_TVENC_FILTCTRL_COEFSEL_CLPF          13
+#define BM_TVENC_FILTCTRL_COEFSEL_CLPF          0x2000
+#define BF_TVENC_FILTCTRL_COEFSEL_CLPF(v)       (((v) & 0x1) << 13)
+#define BFM_TVENC_FILTCTRL_COEFSEL_CLPF(v)      BM_TVENC_FILTCTRL_COEFSEL_CLPF
+#define BF_TVENC_FILTCTRL_COEFSEL_CLPF_V(e)     BF_TVENC_FILTCTRL_COEFSEL_CLPF(BV_TVENC_FILTCTRL_COEFSEL_CLPF__##e)
+#define BFM_TVENC_FILTCTRL_COEFSEL_CLPF_V(v)    BM_TVENC_FILTCTRL_COEFSEL_CLPF
+#define BP_TVENC_FILTCTRL_YS_GAINSGN            12
+#define BM_TVENC_FILTCTRL_YS_GAINSGN            0x1000
+#define BF_TVENC_FILTCTRL_YS_GAINSGN(v)         (((v) & 0x1) << 12)
+#define BFM_TVENC_FILTCTRL_YS_GAINSGN(v)        BM_TVENC_FILTCTRL_YS_GAINSGN
+#define BF_TVENC_FILTCTRL_YS_GAINSGN_V(e)       BF_TVENC_FILTCTRL_YS_GAINSGN(BV_TVENC_FILTCTRL_YS_GAINSGN__##e)
+#define BFM_TVENC_FILTCTRL_YS_GAINSGN_V(v)      BM_TVENC_FILTCTRL_YS_GAINSGN
+#define BP_TVENC_FILTCTRL_YS_GAINSEL            10
+#define BM_TVENC_FILTCTRL_YS_GAINSEL            0xc00
+#define BF_TVENC_FILTCTRL_YS_GAINSEL(v)         (((v) & 0x3) << 10)
+#define BFM_TVENC_FILTCTRL_YS_GAINSEL(v)        BM_TVENC_FILTCTRL_YS_GAINSEL
+#define BF_TVENC_FILTCTRL_YS_GAINSEL_V(e)       BF_TVENC_FILTCTRL_YS_GAINSEL(BV_TVENC_FILTCTRL_YS_GAINSEL__##e)
+#define BFM_TVENC_FILTCTRL_YS_GAINSEL_V(v)      BM_TVENC_FILTCTRL_YS_GAINSEL
+#define BP_TVENC_FILTCTRL_RSRVD2                9
+#define BM_TVENC_FILTCTRL_RSRVD2                0x200
+#define BF_TVENC_FILTCTRL_RSRVD2(v)             (((v) & 0x1) << 9)
+#define BFM_TVENC_FILTCTRL_RSRVD2(v)            BM_TVENC_FILTCTRL_RSRVD2
+#define BF_TVENC_FILTCTRL_RSRVD2_V(e)           BF_TVENC_FILTCTRL_RSRVD2(BV_TVENC_FILTCTRL_RSRVD2__##e)
+#define BFM_TVENC_FILTCTRL_RSRVD2_V(v)          BM_TVENC_FILTCTRL_RSRVD2
+#define BP_TVENC_FILTCTRL_RSRVD3                8
+#define BM_TVENC_FILTCTRL_RSRVD3                0x100
+#define BF_TVENC_FILTCTRL_RSRVD3(v)             (((v) & 0x1) << 8)
+#define BFM_TVENC_FILTCTRL_RSRVD3(v)            BM_TVENC_FILTCTRL_RSRVD3
+#define BF_TVENC_FILTCTRL_RSRVD3_V(e)           BF_TVENC_FILTCTRL_RSRVD3(BV_TVENC_FILTCTRL_RSRVD3__##e)
+#define BFM_TVENC_FILTCTRL_RSRVD3_V(v)          BM_TVENC_FILTCTRL_RSRVD3
+#define BP_TVENC_FILTCTRL_RSRVD4                0
+#define BM_TVENC_FILTCTRL_RSRVD4                0xff
+#define BF_TVENC_FILTCTRL_RSRVD4(v)             (((v) & 0xff) << 0)
+#define BFM_TVENC_FILTCTRL_RSRVD4(v)            BM_TVENC_FILTCTRL_RSRVD4
+#define BF_TVENC_FILTCTRL_RSRVD4_V(e)           BF_TVENC_FILTCTRL_RSRVD4(BV_TVENC_FILTCTRL_RSRVD4__##e)
+#define BFM_TVENC_FILTCTRL_RSRVD4_V(v)          BM_TVENC_FILTCTRL_RSRVD4
+
+#define HW_TVENC_SYNCOFFSET                 HW(TVENC_SYNCOFFSET)
+#define HWA_TVENC_SYNCOFFSET                (0x80038000 + 0x30)
+#define HWT_TVENC_SYNCOFFSET                HWIO_32_RW
+#define HWN_TVENC_SYNCOFFSET                TVENC_SYNCOFFSET
+#define HWI_TVENC_SYNCOFFSET                
+#define HW_TVENC_SYNCOFFSET_SET             HW(TVENC_SYNCOFFSET_SET)
+#define HWA_TVENC_SYNCOFFSET_SET            (HWA_TVENC_SYNCOFFSET + 0x4)
+#define HWT_TVENC_SYNCOFFSET_SET            HWIO_32_WO
+#define HWN_TVENC_SYNCOFFSET_SET            TVENC_SYNCOFFSET
+#define HWI_TVENC_SYNCOFFSET_SET            
+#define HW_TVENC_SYNCOFFSET_CLR             HW(TVENC_SYNCOFFSET_CLR)
+#define HWA_TVENC_SYNCOFFSET_CLR            (HWA_TVENC_SYNCOFFSET + 0x8)
+#define HWT_TVENC_SYNCOFFSET_CLR            HWIO_32_WO
+#define HWN_TVENC_SYNCOFFSET_CLR            TVENC_SYNCOFFSET
+#define HWI_TVENC_SYNCOFFSET_CLR            
+#define HW_TVENC_SYNCOFFSET_TOG             HW(TVENC_SYNCOFFSET_TOG)
+#define HWA_TVENC_SYNCOFFSET_TOG            (HWA_TVENC_SYNCOFFSET + 0xc)
+#define HWT_TVENC_SYNCOFFSET_TOG            HWIO_32_WO
+#define HWN_TVENC_SYNCOFFSET_TOG            TVENC_SYNCOFFSET
+#define HWI_TVENC_SYNCOFFSET_TOG            
+#define BP_TVENC_SYNCOFFSET_RSRVD1          31
+#define BM_TVENC_SYNCOFFSET_RSRVD1          0x80000000
+#define BF_TVENC_SYNCOFFSET_RSRVD1(v)       (((v) & 0x1) << 31)
+#define BFM_TVENC_SYNCOFFSET_RSRVD1(v)      BM_TVENC_SYNCOFFSET_RSRVD1
+#define BF_TVENC_SYNCOFFSET_RSRVD1_V(e)     BF_TVENC_SYNCOFFSET_RSRVD1(BV_TVENC_SYNCOFFSET_RSRVD1__##e)
+#define BFM_TVENC_SYNCOFFSET_RSRVD1_V(v)    BM_TVENC_SYNCOFFSET_RSRVD1
+#define BP_TVENC_SYNCOFFSET_HSO             20
+#define BM_TVENC_SYNCOFFSET_HSO             0x7ff00000
+#define BF_TVENC_SYNCOFFSET_HSO(v)          (((v) & 0x7ff) << 20)
+#define BFM_TVENC_SYNCOFFSET_HSO(v)         BM_TVENC_SYNCOFFSET_HSO
+#define BF_TVENC_SYNCOFFSET_HSO_V(e)        BF_TVENC_SYNCOFFSET_HSO(BV_TVENC_SYNCOFFSET_HSO__##e)
+#define BFM_TVENC_SYNCOFFSET_HSO_V(v)       BM_TVENC_SYNCOFFSET_HSO
+#define BP_TVENC_SYNCOFFSET_VSO             10
+#define BM_TVENC_SYNCOFFSET_VSO             0xffc00
+#define BF_TVENC_SYNCOFFSET_VSO(v)          (((v) & 0x3ff) << 10)
+#define BFM_TVENC_SYNCOFFSET_VSO(v)         BM_TVENC_SYNCOFFSET_VSO
+#define BF_TVENC_SYNCOFFSET_VSO_V(e)        BF_TVENC_SYNCOFFSET_VSO(BV_TVENC_SYNCOFFSET_VSO__##e)
+#define BFM_TVENC_SYNCOFFSET_VSO_V(v)       BM_TVENC_SYNCOFFSET_VSO
+#define BP_TVENC_SYNCOFFSET_HLC             0
+#define BM_TVENC_SYNCOFFSET_HLC             0x3ff
+#define BF_TVENC_SYNCOFFSET_HLC(v)          (((v) & 0x3ff) << 0)
+#define BFM_TVENC_SYNCOFFSET_HLC(v)         BM_TVENC_SYNCOFFSET_HLC
+#define BF_TVENC_SYNCOFFSET_HLC_V(e)        BF_TVENC_SYNCOFFSET_HLC(BV_TVENC_SYNCOFFSET_HLC__##e)
+#define BFM_TVENC_SYNCOFFSET_HLC_V(v)       BM_TVENC_SYNCOFFSET_HLC
+
+#define HW_TVENC_HTIMINGSYNC0                   HW(TVENC_HTIMINGSYNC0)
+#define HWA_TVENC_HTIMINGSYNC0                  (0x80038000 + 0x40)
+#define HWT_TVENC_HTIMINGSYNC0                  HWIO_32_RW
+#define HWN_TVENC_HTIMINGSYNC0                  TVENC_HTIMINGSYNC0
+#define HWI_TVENC_HTIMINGSYNC0                  
+#define HW_TVENC_HTIMINGSYNC0_SET               HW(TVENC_HTIMINGSYNC0_SET)
+#define HWA_TVENC_HTIMINGSYNC0_SET              (HWA_TVENC_HTIMINGSYNC0 + 0x4)
+#define HWT_TVENC_HTIMINGSYNC0_SET              HWIO_32_WO
+#define HWN_TVENC_HTIMINGSYNC0_SET              TVENC_HTIMINGSYNC0
+#define HWI_TVENC_HTIMINGSYNC0_SET              
+#define HW_TVENC_HTIMINGSYNC0_CLR               HW(TVENC_HTIMINGSYNC0_CLR)
+#define HWA_TVENC_HTIMINGSYNC0_CLR              (HWA_TVENC_HTIMINGSYNC0 + 0x8)
+#define HWT_TVENC_HTIMINGSYNC0_CLR              HWIO_32_WO
+#define HWN_TVENC_HTIMINGSYNC0_CLR              TVENC_HTIMINGSYNC0
+#define HWI_TVENC_HTIMINGSYNC0_CLR              
+#define HW_TVENC_HTIMINGSYNC0_TOG               HW(TVENC_HTIMINGSYNC0_TOG)
+#define HWA_TVENC_HTIMINGSYNC0_TOG              (HWA_TVENC_HTIMINGSYNC0 + 0xc)
+#define HWT_TVENC_HTIMINGSYNC0_TOG              HWIO_32_WO
+#define HWN_TVENC_HTIMINGSYNC0_TOG              TVENC_HTIMINGSYNC0
+#define HWI_TVENC_HTIMINGSYNC0_TOG              
+#define BP_TVENC_HTIMINGSYNC0_RSRVD2            26
+#define BM_TVENC_HTIMINGSYNC0_RSRVD2            0xfc000000
+#define BF_TVENC_HTIMINGSYNC0_RSRVD2(v)         (((v) & 0x3f) << 26)
+#define BFM_TVENC_HTIMINGSYNC0_RSRVD2(v)        BM_TVENC_HTIMINGSYNC0_RSRVD2
+#define BF_TVENC_HTIMINGSYNC0_RSRVD2_V(e)       BF_TVENC_HTIMINGSYNC0_RSRVD2(BV_TVENC_HTIMINGSYNC0_RSRVD2__##e)
+#define BFM_TVENC_HTIMINGSYNC0_RSRVD2_V(v)      BM_TVENC_HTIMINGSYNC0_RSRVD2
+#define BP_TVENC_HTIMINGSYNC0_SYNC_END          16
+#define BM_TVENC_HTIMINGSYNC0_SYNC_END          0x3ff0000
+#define BF_TVENC_HTIMINGSYNC0_SYNC_END(v)       (((v) & 0x3ff) << 16)
+#define BFM_TVENC_HTIMINGSYNC0_SYNC_END(v)      BM_TVENC_HTIMINGSYNC0_SYNC_END
+#define BF_TVENC_HTIMINGSYNC0_SYNC_END_V(e)     BF_TVENC_HTIMINGSYNC0_SYNC_END(BV_TVENC_HTIMINGSYNC0_SYNC_END__##e)
+#define BFM_TVENC_HTIMINGSYNC0_SYNC_END_V(v)    BM_TVENC_HTIMINGSYNC0_SYNC_END
+#define BP_TVENC_HTIMINGSYNC0_RSRVD1            10
+#define BM_TVENC_HTIMINGSYNC0_RSRVD1            0xfc00
+#define BF_TVENC_HTIMINGSYNC0_RSRVD1(v)         (((v) & 0x3f) << 10)
+#define BFM_TVENC_HTIMINGSYNC0_RSRVD1(v)        BM_TVENC_HTIMINGSYNC0_RSRVD1
+#define BF_TVENC_HTIMINGSYNC0_RSRVD1_V(e)       BF_TVENC_HTIMINGSYNC0_RSRVD1(BV_TVENC_HTIMINGSYNC0_RSRVD1__##e)
+#define BFM_TVENC_HTIMINGSYNC0_RSRVD1_V(v)      BM_TVENC_HTIMINGSYNC0_RSRVD1
+#define BP_TVENC_HTIMINGSYNC0_SYNC_STRT         0
+#define BM_TVENC_HTIMINGSYNC0_SYNC_STRT         0x3ff
+#define BF_TVENC_HTIMINGSYNC0_SYNC_STRT(v)      (((v) & 0x3ff) << 0)
+#define BFM_TVENC_HTIMINGSYNC0_SYNC_STRT(v)     BM_TVENC_HTIMINGSYNC0_SYNC_STRT
+#define BF_TVENC_HTIMINGSYNC0_SYNC_STRT_V(e)    BF_TVENC_HTIMINGSYNC0_SYNC_STRT(BV_TVENC_HTIMINGSYNC0_SYNC_STRT__##e)
+#define BFM_TVENC_HTIMINGSYNC0_SYNC_STRT_V(v)   BM_TVENC_HTIMINGSYNC0_SYNC_STRT
+
+#define HW_TVENC_HTIMINGSYNC1                   HW(TVENC_HTIMINGSYNC1)
+#define HWA_TVENC_HTIMINGSYNC1                  (0x80038000 + 0x50)
+#define HWT_TVENC_HTIMINGSYNC1                  HWIO_32_RW
+#define HWN_TVENC_HTIMINGSYNC1                  TVENC_HTIMINGSYNC1
+#define HWI_TVENC_HTIMINGSYNC1                  
+#define HW_TVENC_HTIMINGSYNC1_SET               HW(TVENC_HTIMINGSYNC1_SET)
+#define HWA_TVENC_HTIMINGSYNC1_SET              (HWA_TVENC_HTIMINGSYNC1 + 0x4)
+#define HWT_TVENC_HTIMINGSYNC1_SET              HWIO_32_WO
+#define HWN_TVENC_HTIMINGSYNC1_SET              TVENC_HTIMINGSYNC1
+#define HWI_TVENC_HTIMINGSYNC1_SET              
+#define HW_TVENC_HTIMINGSYNC1_CLR               HW(TVENC_HTIMINGSYNC1_CLR)
+#define HWA_TVENC_HTIMINGSYNC1_CLR              (HWA_TVENC_HTIMINGSYNC1 + 0x8)
+#define HWT_TVENC_HTIMINGSYNC1_CLR              HWIO_32_WO
+#define HWN_TVENC_HTIMINGSYNC1_CLR              TVENC_HTIMINGSYNC1
+#define HWI_TVENC_HTIMINGSYNC1_CLR              
+#define HW_TVENC_HTIMINGSYNC1_TOG               HW(TVENC_HTIMINGSYNC1_TOG)
+#define HWA_TVENC_HTIMINGSYNC1_TOG              (HWA_TVENC_HTIMINGSYNC1 + 0xc)
+#define HWT_TVENC_HTIMINGSYNC1_TOG              HWIO_32_WO
+#define HWN_TVENC_HTIMINGSYNC1_TOG              TVENC_HTIMINGSYNC1
+#define HWI_TVENC_HTIMINGSYNC1_TOG              
+#define BP_TVENC_HTIMINGSYNC1_RSRVD2            26
+#define BM_TVENC_HTIMINGSYNC1_RSRVD2            0xfc000000
+#define BF_TVENC_HTIMINGSYNC1_RSRVD2(v)         (((v) & 0x3f) << 26)
+#define BFM_TVENC_HTIMINGSYNC1_RSRVD2(v)        BM_TVENC_HTIMINGSYNC1_RSRVD2
+#define BF_TVENC_HTIMINGSYNC1_RSRVD2_V(e)       BF_TVENC_HTIMINGSYNC1_RSRVD2(BV_TVENC_HTIMINGSYNC1_RSRVD2__##e)
+#define BFM_TVENC_HTIMINGSYNC1_RSRVD2_V(v)      BM_TVENC_HTIMINGSYNC1_RSRVD2
+#define BP_TVENC_HTIMINGSYNC1_SYNC_EQEND        16
+#define BM_TVENC_HTIMINGSYNC1_SYNC_EQEND        0x3ff0000
+#define BF_TVENC_HTIMINGSYNC1_SYNC_EQEND(v)     (((v) & 0x3ff) << 16)
+#define BFM_TVENC_HTIMINGSYNC1_SYNC_EQEND(v)    BM_TVENC_HTIMINGSYNC1_SYNC_EQEND
+#define BF_TVENC_HTIMINGSYNC1_SYNC_EQEND_V(e)   BF_TVENC_HTIMINGSYNC1_SYNC_EQEND(BV_TVENC_HTIMINGSYNC1_SYNC_EQEND__##e)
+#define BFM_TVENC_HTIMINGSYNC1_SYNC_EQEND_V(v)  BM_TVENC_HTIMINGSYNC1_SYNC_EQEND
+#define BP_TVENC_HTIMINGSYNC1_RSRVD1            10
+#define BM_TVENC_HTIMINGSYNC1_RSRVD1            0xfc00
+#define BF_TVENC_HTIMINGSYNC1_RSRVD1(v)         (((v) & 0x3f) << 10)
+#define BFM_TVENC_HTIMINGSYNC1_RSRVD1(v)        BM_TVENC_HTIMINGSYNC1_RSRVD1
+#define BF_TVENC_HTIMINGSYNC1_RSRVD1_V(e)       BF_TVENC_HTIMINGSYNC1_RSRVD1(BV_TVENC_HTIMINGSYNC1_RSRVD1__##e)
+#define BFM_TVENC_HTIMINGSYNC1_RSRVD1_V(v)      BM_TVENC_HTIMINGSYNC1_RSRVD1
+#define BP_TVENC_HTIMINGSYNC1_SYNC_SREND        0
+#define BM_TVENC_HTIMINGSYNC1_SYNC_SREND        0x3ff
+#define BF_TVENC_HTIMINGSYNC1_SYNC_SREND(v)     (((v) & 0x3ff) << 0)
+#define BFM_TVENC_HTIMINGSYNC1_SYNC_SREND(v)    BM_TVENC_HTIMINGSYNC1_SYNC_SREND
+#define BF_TVENC_HTIMINGSYNC1_SYNC_SREND_V(e)   BF_TVENC_HTIMINGSYNC1_SYNC_SREND(BV_TVENC_HTIMINGSYNC1_SYNC_SREND__##e)
+#define BFM_TVENC_HTIMINGSYNC1_SYNC_SREND_V(v)  BM_TVENC_HTIMINGSYNC1_SYNC_SREND
+
+#define HW_TVENC_HTIMINGACTIVE                  HW(TVENC_HTIMINGACTIVE)
+#define HWA_TVENC_HTIMINGACTIVE                 (0x80038000 + 0x60)
+#define HWT_TVENC_HTIMINGACTIVE                 HWIO_32_RW
+#define HWN_TVENC_HTIMINGACTIVE                 TVENC_HTIMINGACTIVE
+#define HWI_TVENC_HTIMINGACTIVE                 
+#define HW_TVENC_HTIMINGACTIVE_SET              HW(TVENC_HTIMINGACTIVE_SET)
+#define HWA_TVENC_HTIMINGACTIVE_SET             (HWA_TVENC_HTIMINGACTIVE + 0x4)
+#define HWT_TVENC_HTIMINGACTIVE_SET             HWIO_32_WO
+#define HWN_TVENC_HTIMINGACTIVE_SET             TVENC_HTIMINGACTIVE
+#define HWI_TVENC_HTIMINGACTIVE_SET             
+#define HW_TVENC_HTIMINGACTIVE_CLR              HW(TVENC_HTIMINGACTIVE_CLR)
+#define HWA_TVENC_HTIMINGACTIVE_CLR             (HWA_TVENC_HTIMINGACTIVE + 0x8)
+#define HWT_TVENC_HTIMINGACTIVE_CLR             HWIO_32_WO
+#define HWN_TVENC_HTIMINGACTIVE_CLR             TVENC_HTIMINGACTIVE
+#define HWI_TVENC_HTIMINGACTIVE_CLR             
+#define HW_TVENC_HTIMINGACTIVE_TOG              HW(TVENC_HTIMINGACTIVE_TOG)
+#define HWA_TVENC_HTIMINGACTIVE_TOG             (HWA_TVENC_HTIMINGACTIVE + 0xc)
+#define HWT_TVENC_HTIMINGACTIVE_TOG             HWIO_32_WO
+#define HWN_TVENC_HTIMINGACTIVE_TOG             TVENC_HTIMINGACTIVE
+#define HWI_TVENC_HTIMINGACTIVE_TOG             
+#define BP_TVENC_HTIMINGACTIVE_RSRVD2           26
+#define BM_TVENC_HTIMINGACTIVE_RSRVD2           0xfc000000
+#define BF_TVENC_HTIMINGACTIVE_RSRVD2(v)        (((v) & 0x3f) << 26)
+#define BFM_TVENC_HTIMINGACTIVE_RSRVD2(v)       BM_TVENC_HTIMINGACTIVE_RSRVD2
+#define BF_TVENC_HTIMINGACTIVE_RSRVD2_V(e)      BF_TVENC_HTIMINGACTIVE_RSRVD2(BV_TVENC_HTIMINGACTIVE_RSRVD2__##e)
+#define BFM_TVENC_HTIMINGACTIVE_RSRVD2_V(v)     BM_TVENC_HTIMINGACTIVE_RSRVD2
+#define BP_TVENC_HTIMINGACTIVE_ACTV_END         16
+#define BM_TVENC_HTIMINGACTIVE_ACTV_END         0x3ff0000
+#define BF_TVENC_HTIMINGACTIVE_ACTV_END(v)      (((v) & 0x3ff) << 16)
+#define BFM_TVENC_HTIMINGACTIVE_ACTV_END(v)     BM_TVENC_HTIMINGACTIVE_ACTV_END
+#define BF_TVENC_HTIMINGACTIVE_ACTV_END_V(e)    BF_TVENC_HTIMINGACTIVE_ACTV_END(BV_TVENC_HTIMINGACTIVE_ACTV_END__##e)
+#define BFM_TVENC_HTIMINGACTIVE_ACTV_END_V(v)   BM_TVENC_HTIMINGACTIVE_ACTV_END
+#define BP_TVENC_HTIMINGACTIVE_RSRVD1           10
+#define BM_TVENC_HTIMINGACTIVE_RSRVD1           0xfc00
+#define BF_TVENC_HTIMINGACTIVE_RSRVD1(v)        (((v) & 0x3f) << 10)
+#define BFM_TVENC_HTIMINGACTIVE_RSRVD1(v)       BM_TVENC_HTIMINGACTIVE_RSRVD1
+#define BF_TVENC_HTIMINGACTIVE_RSRVD1_V(e)      BF_TVENC_HTIMINGACTIVE_RSRVD1(BV_TVENC_HTIMINGACTIVE_RSRVD1__##e)
+#define BFM_TVENC_HTIMINGACTIVE_RSRVD1_V(v)     BM_TVENC_HTIMINGACTIVE_RSRVD1
+#define BP_TVENC_HTIMINGACTIVE_ACTV_STRT        0
+#define BM_TVENC_HTIMINGACTIVE_ACTV_STRT        0x3ff
+#define BF_TVENC_HTIMINGACTIVE_ACTV_STRT(v)     (((v) & 0x3ff) << 0)
+#define BFM_TVENC_HTIMINGACTIVE_ACTV_STRT(v)    BM_TVENC_HTIMINGACTIVE_ACTV_STRT
+#define BF_TVENC_HTIMINGACTIVE_ACTV_STRT_V(e)   BF_TVENC_HTIMINGACTIVE_ACTV_STRT(BV_TVENC_HTIMINGACTIVE_ACTV_STRT__##e)
+#define BFM_TVENC_HTIMINGACTIVE_ACTV_STRT_V(v)  BM_TVENC_HTIMINGACTIVE_ACTV_STRT
+
+#define HW_TVENC_HTIMINGBURST0                  HW(TVENC_HTIMINGBURST0)
+#define HWA_TVENC_HTIMINGBURST0                 (0x80038000 + 0x70)
+#define HWT_TVENC_HTIMINGBURST0                 HWIO_32_RW
+#define HWN_TVENC_HTIMINGBURST0                 TVENC_HTIMINGBURST0
+#define HWI_TVENC_HTIMINGBURST0                 
+#define HW_TVENC_HTIMINGBURST0_SET              HW(TVENC_HTIMINGBURST0_SET)
+#define HWA_TVENC_HTIMINGBURST0_SET             (HWA_TVENC_HTIMINGBURST0 + 0x4)
+#define HWT_TVENC_HTIMINGBURST0_SET             HWIO_32_WO
+#define HWN_TVENC_HTIMINGBURST0_SET             TVENC_HTIMINGBURST0
+#define HWI_TVENC_HTIMINGBURST0_SET             
+#define HW_TVENC_HTIMINGBURST0_CLR              HW(TVENC_HTIMINGBURST0_CLR)
+#define HWA_TVENC_HTIMINGBURST0_CLR             (HWA_TVENC_HTIMINGBURST0 + 0x8)
+#define HWT_TVENC_HTIMINGBURST0_CLR             HWIO_32_WO
+#define HWN_TVENC_HTIMINGBURST0_CLR             TVENC_HTIMINGBURST0
+#define HWI_TVENC_HTIMINGBURST0_CLR             
+#define HW_TVENC_HTIMINGBURST0_TOG              HW(TVENC_HTIMINGBURST0_TOG)
+#define HWA_TVENC_HTIMINGBURST0_TOG             (HWA_TVENC_HTIMINGBURST0 + 0xc)
+#define HWT_TVENC_HTIMINGBURST0_TOG             HWIO_32_WO
+#define HWN_TVENC_HTIMINGBURST0_TOG             TVENC_HTIMINGBURST0
+#define HWI_TVENC_HTIMINGBURST0_TOG             
+#define BP_TVENC_HTIMINGBURST0_RSRVD2           26
+#define BM_TVENC_HTIMINGBURST0_RSRVD2           0xfc000000
+#define BF_TVENC_HTIMINGBURST0_RSRVD2(v)        (((v) & 0x3f) << 26)
+#define BFM_TVENC_HTIMINGBURST0_RSRVD2(v)       BM_TVENC_HTIMINGBURST0_RSRVD2
+#define BF_TVENC_HTIMINGBURST0_RSRVD2_V(e)      BF_TVENC_HTIMINGBURST0_RSRVD2(BV_TVENC_HTIMINGBURST0_RSRVD2__##e)
+#define BFM_TVENC_HTIMINGBURST0_RSRVD2_V(v)     BM_TVENC_HTIMINGBURST0_RSRVD2
+#define BP_TVENC_HTIMINGBURST0_WBRST_STRT       16
+#define BM_TVENC_HTIMINGBURST0_WBRST_STRT       0x3ff0000
+#define BF_TVENC_HTIMINGBURST0_WBRST_STRT(v)    (((v) & 0x3ff) << 16)
+#define BFM_TVENC_HTIMINGBURST0_WBRST_STRT(v)   BM_TVENC_HTIMINGBURST0_WBRST_STRT
+#define BF_TVENC_HTIMINGBURST0_WBRST_STRT_V(e)  BF_TVENC_HTIMINGBURST0_WBRST_STRT(BV_TVENC_HTIMINGBURST0_WBRST_STRT__##e)
+#define BFM_TVENC_HTIMINGBURST0_WBRST_STRT_V(v) BM_TVENC_HTIMINGBURST0_WBRST_STRT
+#define BP_TVENC_HTIMINGBURST0_RSRVD1           10
+#define BM_TVENC_HTIMINGBURST0_RSRVD1           0xfc00
+#define BF_TVENC_HTIMINGBURST0_RSRVD1(v)        (((v) & 0x3f) << 10)
+#define BFM_TVENC_HTIMINGBURST0_RSRVD1(v)       BM_TVENC_HTIMINGBURST0_RSRVD1
+#define BF_TVENC_HTIMINGBURST0_RSRVD1_V(e)      BF_TVENC_HTIMINGBURST0_RSRVD1(BV_TVENC_HTIMINGBURST0_RSRVD1__##e)
+#define BFM_TVENC_HTIMINGBURST0_RSRVD1_V(v)     BM_TVENC_HTIMINGBURST0_RSRVD1
+#define BP_TVENC_HTIMINGBURST0_NBRST_STRT       0
+#define BM_TVENC_HTIMINGBURST0_NBRST_STRT       0x3ff
+#define BF_TVENC_HTIMINGBURST0_NBRST_STRT(v)    (((v) & 0x3ff) << 0)
+#define BFM_TVENC_HTIMINGBURST0_NBRST_STRT(v)   BM_TVENC_HTIMINGBURST0_NBRST_STRT
+#define BF_TVENC_HTIMINGBURST0_NBRST_STRT_V(e)  BF_TVENC_HTIMINGBURST0_NBRST_STRT(BV_TVENC_HTIMINGBURST0_NBRST_STRT__##e)
+#define BFM_TVENC_HTIMINGBURST0_NBRST_STRT_V(v) BM_TVENC_HTIMINGBURST0_NBRST_STRT
+
+#define HW_TVENC_HTIMINGBURST1                  HW(TVENC_HTIMINGBURST1)
+#define HWA_TVENC_HTIMINGBURST1                 (0x80038000 + 0x80)
+#define HWT_TVENC_HTIMINGBURST1                 HWIO_32_RW
+#define HWN_TVENC_HTIMINGBURST1                 TVENC_HTIMINGBURST1
+#define HWI_TVENC_HTIMINGBURST1                 
+#define HW_TVENC_HTIMINGBURST1_SET              HW(TVENC_HTIMINGBURST1_SET)
+#define HWA_TVENC_HTIMINGBURST1_SET             (HWA_TVENC_HTIMINGBURST1 + 0x4)
+#define HWT_TVENC_HTIMINGBURST1_SET             HWIO_32_WO
+#define HWN_TVENC_HTIMINGBURST1_SET             TVENC_HTIMINGBURST1
+#define HWI_TVENC_HTIMINGBURST1_SET             
+#define HW_TVENC_HTIMINGBURST1_CLR              HW(TVENC_HTIMINGBURST1_CLR)
+#define HWA_TVENC_HTIMINGBURST1_CLR             (HWA_TVENC_HTIMINGBURST1 + 0x8)
+#define HWT_TVENC_HTIMINGBURST1_CLR             HWIO_32_WO
+#define HWN_TVENC_HTIMINGBURST1_CLR             TVENC_HTIMINGBURST1
+#define HWI_TVENC_HTIMINGBURST1_CLR             
+#define HW_TVENC_HTIMINGBURST1_TOG              HW(TVENC_HTIMINGBURST1_TOG)
+#define HWA_TVENC_HTIMINGBURST1_TOG             (HWA_TVENC_HTIMINGBURST1 + 0xc)
+#define HWT_TVENC_HTIMINGBURST1_TOG             HWIO_32_WO
+#define HWN_TVENC_HTIMINGBURST1_TOG             TVENC_HTIMINGBURST1
+#define HWI_TVENC_HTIMINGBURST1_TOG             
+#define BP_TVENC_HTIMINGBURST1_RSRVD1           10
+#define BM_TVENC_HTIMINGBURST1_RSRVD1           0xfffffc00
+#define BF_TVENC_HTIMINGBURST1_RSRVD1(v)        (((v) & 0x3fffff) << 10)
+#define BFM_TVENC_HTIMINGBURST1_RSRVD1(v)       BM_TVENC_HTIMINGBURST1_RSRVD1
+#define BF_TVENC_HTIMINGBURST1_RSRVD1_V(e)      BF_TVENC_HTIMINGBURST1_RSRVD1(BV_TVENC_HTIMINGBURST1_RSRVD1__##e)
+#define BFM_TVENC_HTIMINGBURST1_RSRVD1_V(v)     BM_TVENC_HTIMINGBURST1_RSRVD1
+#define BP_TVENC_HTIMINGBURST1_BRST_END         0
+#define BM_TVENC_HTIMINGBURST1_BRST_END         0x3ff
+#define BF_TVENC_HTIMINGBURST1_BRST_END(v)      (((v) & 0x3ff) << 0)
+#define BFM_TVENC_HTIMINGBURST1_BRST_END(v)     BM_TVENC_HTIMINGBURST1_BRST_END
+#define BF_TVENC_HTIMINGBURST1_BRST_END_V(e)    BF_TVENC_HTIMINGBURST1_BRST_END(BV_TVENC_HTIMINGBURST1_BRST_END__##e)
+#define BFM_TVENC_HTIMINGBURST1_BRST_END_V(v)   BM_TVENC_HTIMINGBURST1_BRST_END
+
+#define HW_TVENC_VTIMING0                   HW(TVENC_VTIMING0)
+#define HWA_TVENC_VTIMING0                  (0x80038000 + 0x90)
+#define HWT_TVENC_VTIMING0                  HWIO_32_RW
+#define HWN_TVENC_VTIMING0                  TVENC_VTIMING0
+#define HWI_TVENC_VTIMING0                  
+#define HW_TVENC_VTIMING0_SET               HW(TVENC_VTIMING0_SET)
+#define HWA_TVENC_VTIMING0_SET              (HWA_TVENC_VTIMING0 + 0x4)
+#define HWT_TVENC_VTIMING0_SET              HWIO_32_WO
+#define HWN_TVENC_VTIMING0_SET              TVENC_VTIMING0
+#define HWI_TVENC_VTIMING0_SET              
+#define HW_TVENC_VTIMING0_CLR               HW(TVENC_VTIMING0_CLR)
+#define HWA_TVENC_VTIMING0_CLR              (HWA_TVENC_VTIMING0 + 0x8)
+#define HWT_TVENC_VTIMING0_CLR              HWIO_32_WO
+#define HWN_TVENC_VTIMING0_CLR              TVENC_VTIMING0
+#define HWI_TVENC_VTIMING0_CLR              
+#define HW_TVENC_VTIMING0_TOG               HW(TVENC_VTIMING0_TOG)
+#define HWA_TVENC_VTIMING0_TOG              (HWA_TVENC_VTIMING0 + 0xc)
+#define HWT_TVENC_VTIMING0_TOG              HWIO_32_WO
+#define HWN_TVENC_VTIMING0_TOG              TVENC_VTIMING0
+#define HWI_TVENC_VTIMING0_TOG              
+#define BP_TVENC_VTIMING0_RSRVD3            26
+#define BM_TVENC_VTIMING0_RSRVD3            0xfc000000
+#define BF_TVENC_VTIMING0_RSRVD3(v)         (((v) & 0x3f) << 26)
+#define BFM_TVENC_VTIMING0_RSRVD3(v)        BM_TVENC_VTIMING0_RSRVD3
+#define BF_TVENC_VTIMING0_RSRVD3_V(e)       BF_TVENC_VTIMING0_RSRVD3(BV_TVENC_VTIMING0_RSRVD3__##e)
+#define BFM_TVENC_VTIMING0_RSRVD3_V(v)      BM_TVENC_VTIMING0_RSRVD3
+#define BP_TVENC_VTIMING0_VSTRT_PREEQ       16
+#define BM_TVENC_VTIMING0_VSTRT_PREEQ       0x3ff0000
+#define BF_TVENC_VTIMING0_VSTRT_PREEQ(v)    (((v) & 0x3ff) << 16)
+#define BFM_TVENC_VTIMING0_VSTRT_PREEQ(v)   BM_TVENC_VTIMING0_VSTRT_PREEQ
+#define BF_TVENC_VTIMING0_VSTRT_PREEQ_V(e)  BF_TVENC_VTIMING0_VSTRT_PREEQ(BV_TVENC_VTIMING0_VSTRT_PREEQ__##e)
+#define BFM_TVENC_VTIMING0_VSTRT_PREEQ_V(v) BM_TVENC_VTIMING0_VSTRT_PREEQ
+#define BP_TVENC_VTIMING0_RSRVD2            14
+#define BM_TVENC_VTIMING0_RSRVD2            0xc000
+#define BF_TVENC_VTIMING0_RSRVD2(v)         (((v) & 0x3) << 14)
+#define BFM_TVENC_VTIMING0_RSRVD2(v)        BM_TVENC_VTIMING0_RSRVD2
+#define BF_TVENC_VTIMING0_RSRVD2_V(e)       BF_TVENC_VTIMING0_RSRVD2(BV_TVENC_VTIMING0_RSRVD2__##e)
+#define BFM_TVENC_VTIMING0_RSRVD2_V(v)      BM_TVENC_VTIMING0_RSRVD2
+#define BP_TVENC_VTIMING0_VSTRT_ACTV        8
+#define BM_TVENC_VTIMING0_VSTRT_ACTV        0x3f00
+#define BF_TVENC_VTIMING0_VSTRT_ACTV(v)     (((v) & 0x3f) << 8)
+#define BFM_TVENC_VTIMING0_VSTRT_ACTV(v)    BM_TVENC_VTIMING0_VSTRT_ACTV
+#define BF_TVENC_VTIMING0_VSTRT_ACTV_V(e)   BF_TVENC_VTIMING0_VSTRT_ACTV(BV_TVENC_VTIMING0_VSTRT_ACTV__##e)
+#define BFM_TVENC_VTIMING0_VSTRT_ACTV_V(v)  BM_TVENC_VTIMING0_VSTRT_ACTV
+#define BP_TVENC_VTIMING0_RSRVD1            6
+#define BM_TVENC_VTIMING0_RSRVD1            0xc0
+#define BF_TVENC_VTIMING0_RSRVD1(v)         (((v) & 0x3) << 6)
+#define BFM_TVENC_VTIMING0_RSRVD1(v)        BM_TVENC_VTIMING0_RSRVD1
+#define BF_TVENC_VTIMING0_RSRVD1_V(e)       BF_TVENC_VTIMING0_RSRVD1(BV_TVENC_VTIMING0_RSRVD1__##e)
+#define BFM_TVENC_VTIMING0_RSRVD1_V(v)      BM_TVENC_VTIMING0_RSRVD1
+#define BP_TVENC_VTIMING0_VSTRT_SUBPH       0
+#define BM_TVENC_VTIMING0_VSTRT_SUBPH       0x3f
+#define BF_TVENC_VTIMING0_VSTRT_SUBPH(v)    (((v) & 0x3f) << 0)
+#define BFM_TVENC_VTIMING0_VSTRT_SUBPH(v)   BM_TVENC_VTIMING0_VSTRT_SUBPH
+#define BF_TVENC_VTIMING0_VSTRT_SUBPH_V(e)  BF_TVENC_VTIMING0_VSTRT_SUBPH(BV_TVENC_VTIMING0_VSTRT_SUBPH__##e)
+#define BFM_TVENC_VTIMING0_VSTRT_SUBPH_V(v) BM_TVENC_VTIMING0_VSTRT_SUBPH
+
+#define HW_TVENC_VTIMING1                       HW(TVENC_VTIMING1)
+#define HWA_TVENC_VTIMING1                      (0x80038000 + 0xa0)
+#define HWT_TVENC_VTIMING1                      HWIO_32_RW
+#define HWN_TVENC_VTIMING1                      TVENC_VTIMING1
+#define HWI_TVENC_VTIMING1                      
+#define HW_TVENC_VTIMING1_SET                   HW(TVENC_VTIMING1_SET)
+#define HWA_TVENC_VTIMING1_SET                  (HWA_TVENC_VTIMING1 + 0x4)
+#define HWT_TVENC_VTIMING1_SET                  HWIO_32_WO
+#define HWN_TVENC_VTIMING1_SET                  TVENC_VTIMING1
+#define HWI_TVENC_VTIMING1_SET                  
+#define HW_TVENC_VTIMING1_CLR                   HW(TVENC_VTIMING1_CLR)
+#define HWA_TVENC_VTIMING1_CLR                  (HWA_TVENC_VTIMING1 + 0x8)
+#define HWT_TVENC_VTIMING1_CLR                  HWIO_32_WO
+#define HWN_TVENC_VTIMING1_CLR                  TVENC_VTIMING1
+#define HWI_TVENC_VTIMING1_CLR                  
+#define HW_TVENC_VTIMING1_TOG                   HW(TVENC_VTIMING1_TOG)
+#define HWA_TVENC_VTIMING1_TOG                  (HWA_TVENC_VTIMING1 + 0xc)
+#define HWT_TVENC_VTIMING1_TOG                  HWIO_32_WO
+#define HWN_TVENC_VTIMING1_TOG                  TVENC_VTIMING1
+#define HWI_TVENC_VTIMING1_TOG                  
+#define BP_TVENC_VTIMING1_RSRVD3                30
+#define BM_TVENC_VTIMING1_RSRVD3                0xc0000000
+#define BF_TVENC_VTIMING1_RSRVD3(v)             (((v) & 0x3) << 30)
+#define BFM_TVENC_VTIMING1_RSRVD3(v)            BM_TVENC_VTIMING1_RSRVD3
+#define BF_TVENC_VTIMING1_RSRVD3_V(e)           BF_TVENC_VTIMING1_RSRVD3(BV_TVENC_VTIMING1_RSRVD3__##e)
+#define BFM_TVENC_VTIMING1_RSRVD3_V(v)          BM_TVENC_VTIMING1_RSRVD3
+#define BP_TVENC_VTIMING1_VSTRT_POSTEQ          24
+#define BM_TVENC_VTIMING1_VSTRT_POSTEQ          0x3f000000
+#define BF_TVENC_VTIMING1_VSTRT_POSTEQ(v)       (((v) & 0x3f) << 24)
+#define BFM_TVENC_VTIMING1_VSTRT_POSTEQ(v)      BM_TVENC_VTIMING1_VSTRT_POSTEQ
+#define BF_TVENC_VTIMING1_VSTRT_POSTEQ_V(e)     BF_TVENC_VTIMING1_VSTRT_POSTEQ(BV_TVENC_VTIMING1_VSTRT_POSTEQ__##e)
+#define BFM_TVENC_VTIMING1_VSTRT_POSTEQ_V(v)    BM_TVENC_VTIMING1_VSTRT_POSTEQ
+#define BP_TVENC_VTIMING1_RSRVD2                22
+#define BM_TVENC_VTIMING1_RSRVD2                0xc00000
+#define BF_TVENC_VTIMING1_RSRVD2(v)             (((v) & 0x3) << 22)
+#define BFM_TVENC_VTIMING1_RSRVD2(v)            BM_TVENC_VTIMING1_RSRVD2
+#define BF_TVENC_VTIMING1_RSRVD2_V(e)           BF_TVENC_VTIMING1_RSRVD2(BV_TVENC_VTIMING1_RSRVD2__##e)
+#define BFM_TVENC_VTIMING1_RSRVD2_V(v)          BM_TVENC_VTIMING1_RSRVD2
+#define BP_TVENC_VTIMING1_VSTRT_SERRA           16
+#define BM_TVENC_VTIMING1_VSTRT_SERRA           0x3f0000
+#define BF_TVENC_VTIMING1_VSTRT_SERRA(v)        (((v) & 0x3f) << 16)
+#define BFM_TVENC_VTIMING1_VSTRT_SERRA(v)       BM_TVENC_VTIMING1_VSTRT_SERRA
+#define BF_TVENC_VTIMING1_VSTRT_SERRA_V(e)      BF_TVENC_VTIMING1_VSTRT_SERRA(BV_TVENC_VTIMING1_VSTRT_SERRA__##e)
+#define BFM_TVENC_VTIMING1_VSTRT_SERRA_V(v)     BM_TVENC_VTIMING1_VSTRT_SERRA
+#define BP_TVENC_VTIMING1_RSRVD1                10
+#define BM_TVENC_VTIMING1_RSRVD1                0xfc00
+#define BF_TVENC_VTIMING1_RSRVD1(v)             (((v) & 0x3f) << 10)
+#define BFM_TVENC_VTIMING1_RSRVD1(v)            BM_TVENC_VTIMING1_RSRVD1
+#define BF_TVENC_VTIMING1_RSRVD1_V(e)           BF_TVENC_VTIMING1_RSRVD1(BV_TVENC_VTIMING1_RSRVD1__##e)
+#define BFM_TVENC_VTIMING1_RSRVD1_V(v)          BM_TVENC_VTIMING1_RSRVD1
+#define BP_TVENC_VTIMING1_LAST_FLD_LN           0
+#define BM_TVENC_VTIMING1_LAST_FLD_LN           0x3ff
+#define BF_TVENC_VTIMING1_LAST_FLD_LN(v)        (((v) & 0x3ff) << 0)
+#define BFM_TVENC_VTIMING1_LAST_FLD_LN(v)       BM_TVENC_VTIMING1_LAST_FLD_LN
+#define BF_TVENC_VTIMING1_LAST_FLD_LN_V(e)      BF_TVENC_VTIMING1_LAST_FLD_LN(BV_TVENC_VTIMING1_LAST_FLD_LN__##e)
+#define BFM_TVENC_VTIMING1_LAST_FLD_LN_V(v)     BM_TVENC_VTIMING1_LAST_FLD_LN
+
+#define HW_TVENC_MISC                           HW(TVENC_MISC)
+#define HWA_TVENC_MISC                          (0x80038000 + 0xb0)
+#define HWT_TVENC_MISC                          HWIO_32_RW
+#define HWN_TVENC_MISC                          TVENC_MISC
+#define HWI_TVENC_MISC                          
+#define HW_TVENC_MISC_SET                       HW(TVENC_MISC_SET)
+#define HWA_TVENC_MISC_SET                      (HWA_TVENC_MISC + 0x4)
+#define HWT_TVENC_MISC_SET                      HWIO_32_WO
+#define HWN_TVENC_MISC_SET                      TVENC_MISC
+#define HWI_TVENC_MISC_SET                      
+#define HW_TVENC_MISC_CLR                       HW(TVENC_MISC_CLR)
+#define HWA_TVENC_MISC_CLR                      (HWA_TVENC_MISC + 0x8)
+#define HWT_TVENC_MISC_CLR                      HWIO_32_WO
+#define HWN_TVENC_MISC_CLR                      TVENC_MISC
+#define HWI_TVENC_MISC_CLR                      
+#define HW_TVENC_MISC_TOG                       HW(TVENC_MISC_TOG)
+#define HWA_TVENC_MISC_TOG                      (HWA_TVENC_MISC + 0xc)
+#define HWT_TVENC_MISC_TOG                      HWIO_32_WO
+#define HWN_TVENC_MISC_TOG                      TVENC_MISC
+#define HWI_TVENC_MISC_TOG                      
+#define BP_TVENC_MISC_RSRVD3                    25
+#define BM_TVENC_MISC_RSRVD3                    0xfe000000
+#define BF_TVENC_MISC_RSRVD3(v)                 (((v) & 0x7f) << 25)
+#define BFM_TVENC_MISC_RSRVD3(v)                BM_TVENC_MISC_RSRVD3
+#define BF_TVENC_MISC_RSRVD3_V(e)               BF_TVENC_MISC_RSRVD3(BV_TVENC_MISC_RSRVD3__##e)
+#define BFM_TVENC_MISC_RSRVD3_V(v)              BM_TVENC_MISC_RSRVD3
+#define BP_TVENC_MISC_LPF_RST_OFF               16
+#define BM_TVENC_MISC_LPF_RST_OFF               0x1ff0000
+#define BF_TVENC_MISC_LPF_RST_OFF(v)            (((v) & 0x1ff) << 16)
+#define BFM_TVENC_MISC_LPF_RST_OFF(v)           BM_TVENC_MISC_LPF_RST_OFF
+#define BF_TVENC_MISC_LPF_RST_OFF_V(e)          BF_TVENC_MISC_LPF_RST_OFF(BV_TVENC_MISC_LPF_RST_OFF__##e)
+#define BFM_TVENC_MISC_LPF_RST_OFF_V(v)         BM_TVENC_MISC_LPF_RST_OFF
+#define BP_TVENC_MISC_RSRVD2                    12
+#define BM_TVENC_MISC_RSRVD2                    0xf000
+#define BF_TVENC_MISC_RSRVD2(v)                 (((v) & 0xf) << 12)
+#define BFM_TVENC_MISC_RSRVD2(v)                BM_TVENC_MISC_RSRVD2
+#define BF_TVENC_MISC_RSRVD2_V(e)               BF_TVENC_MISC_RSRVD2(BV_TVENC_MISC_RSRVD2__##e)
+#define BFM_TVENC_MISC_RSRVD2_V(v)              BM_TVENC_MISC_RSRVD2
+#define BP_TVENC_MISC_NTSC_LN_CNT               11
+#define BM_TVENC_MISC_NTSC_LN_CNT               0x800
+#define BF_TVENC_MISC_NTSC_LN_CNT(v)            (((v) & 0x1) << 11)
+#define BFM_TVENC_MISC_NTSC_LN_CNT(v)           BM_TVENC_MISC_NTSC_LN_CNT
+#define BF_TVENC_MISC_NTSC_LN_CNT_V(e)          BF_TVENC_MISC_NTSC_LN_CNT(BV_TVENC_MISC_NTSC_LN_CNT__##e)
+#define BFM_TVENC_MISC_NTSC_LN_CNT_V(v)         BM_TVENC_MISC_NTSC_LN_CNT
+#define BP_TVENC_MISC_PAL_FSC_PHASE_ALT         10
+#define BM_TVENC_MISC_PAL_FSC_PHASE_ALT         0x400
+#define BF_TVENC_MISC_PAL_FSC_PHASE_ALT(v)      (((v) & 0x1) << 10)
+#define BFM_TVENC_MISC_PAL_FSC_PHASE_ALT(v)     BM_TVENC_MISC_PAL_FSC_PHASE_ALT
+#define BF_TVENC_MISC_PAL_FSC_PHASE_ALT_V(e)    BF_TVENC_MISC_PAL_FSC_PHASE_ALT(BV_TVENC_MISC_PAL_FSC_PHASE_ALT__##e)
+#define BFM_TVENC_MISC_PAL_FSC_PHASE_ALT_V(v)   BM_TVENC_MISC_PAL_FSC_PHASE_ALT
+#define BP_TVENC_MISC_FSC_PHASE_RST             8
+#define BM_TVENC_MISC_FSC_PHASE_RST             0x300
+#define BF_TVENC_MISC_FSC_PHASE_RST(v)          (((v) & 0x3) << 8)
+#define BFM_TVENC_MISC_FSC_PHASE_RST(v)         BM_TVENC_MISC_FSC_PHASE_RST
+#define BF_TVENC_MISC_FSC_PHASE_RST_V(e)        BF_TVENC_MISC_FSC_PHASE_RST(BV_TVENC_MISC_FSC_PHASE_RST__##e)
+#define BFM_TVENC_MISC_FSC_PHASE_RST_V(v)       BM_TVENC_MISC_FSC_PHASE_RST
+#define BP_TVENC_MISC_BRUCHB                    6
+#define BM_TVENC_MISC_BRUCHB                    0xc0
+#define BF_TVENC_MISC_BRUCHB(v)                 (((v) & 0x3) << 6)
+#define BFM_TVENC_MISC_BRUCHB(v)                BM_TVENC_MISC_BRUCHB
+#define BF_TVENC_MISC_BRUCHB_V(e)               BF_TVENC_MISC_BRUCHB(BV_TVENC_MISC_BRUCHB__##e)
+#define BFM_TVENC_MISC_BRUCHB_V(v)              BM_TVENC_MISC_BRUCHB
+#define BP_TVENC_MISC_AGC_LVL_CTRL              4
+#define BM_TVENC_MISC_AGC_LVL_CTRL              0x30
+#define BF_TVENC_MISC_AGC_LVL_CTRL(v)           (((v) & 0x3) << 4)
+#define BFM_TVENC_MISC_AGC_LVL_CTRL(v)          BM_TVENC_MISC_AGC_LVL_CTRL
+#define BF_TVENC_MISC_AGC_LVL_CTRL_V(e)         BF_TVENC_MISC_AGC_LVL_CTRL(BV_TVENC_MISC_AGC_LVL_CTRL__##e)
+#define BFM_TVENC_MISC_AGC_LVL_CTRL_V(v)        BM_TVENC_MISC_AGC_LVL_CTRL
+#define BP_TVENC_MISC_RSRVD1                    3
+#define BM_TVENC_MISC_RSRVD1                    0x8
+#define BF_TVENC_MISC_RSRVD1(v)                 (((v) & 0x1) << 3)
+#define BFM_TVENC_MISC_RSRVD1(v)                BM_TVENC_MISC_RSRVD1
+#define BF_TVENC_MISC_RSRVD1_V(e)               BF_TVENC_MISC_RSRVD1(BV_TVENC_MISC_RSRVD1__##e)
+#define BFM_TVENC_MISC_RSRVD1_V(v)              BM_TVENC_MISC_RSRVD1
+#define BP_TVENC_MISC_CS_INVERT_CTRL            2
+#define BM_TVENC_MISC_CS_INVERT_CTRL            0x4
+#define BF_TVENC_MISC_CS_INVERT_CTRL(v)         (((v) & 0x1) << 2)
+#define BFM_TVENC_MISC_CS_INVERT_CTRL(v)        BM_TVENC_MISC_CS_INVERT_CTRL
+#define BF_TVENC_MISC_CS_INVERT_CTRL_V(e)       BF_TVENC_MISC_CS_INVERT_CTRL(BV_TVENC_MISC_CS_INVERT_CTRL__##e)
+#define BFM_TVENC_MISC_CS_INVERT_CTRL_V(v)      BM_TVENC_MISC_CS_INVERT_CTRL
+#define BP_TVENC_MISC_Y_BLANK_CTRL              0
+#define BM_TVENC_MISC_Y_BLANK_CTRL              0x3
+#define BF_TVENC_MISC_Y_BLANK_CTRL(v)           (((v) & 0x3) << 0)
+#define BFM_TVENC_MISC_Y_BLANK_CTRL(v)          BM_TVENC_MISC_Y_BLANK_CTRL
+#define BF_TVENC_MISC_Y_BLANK_CTRL_V(e)         BF_TVENC_MISC_Y_BLANK_CTRL(BV_TVENC_MISC_Y_BLANK_CTRL__##e)
+#define BFM_TVENC_MISC_Y_BLANK_CTRL_V(v)        BM_TVENC_MISC_Y_BLANK_CTRL
+
+#define HW_TVENC_COLORSUB0                  HW(TVENC_COLORSUB0)
+#define HWA_TVENC_COLORSUB0                 (0x80038000 + 0xc0)
+#define HWT_TVENC_COLORSUB0                 HWIO_32_RW
+#define HWN_TVENC_COLORSUB0                 TVENC_COLORSUB0
+#define HWI_TVENC_COLORSUB0                 
+#define HW_TVENC_COLORSUB0_SET              HW(TVENC_COLORSUB0_SET)
+#define HWA_TVENC_COLORSUB0_SET             (HWA_TVENC_COLORSUB0 + 0x4)
+#define HWT_TVENC_COLORSUB0_SET             HWIO_32_WO
+#define HWN_TVENC_COLORSUB0_SET             TVENC_COLORSUB0
+#define HWI_TVENC_COLORSUB0_SET             
+#define HW_TVENC_COLORSUB0_CLR              HW(TVENC_COLORSUB0_CLR)
+#define HWA_TVENC_COLORSUB0_CLR             (HWA_TVENC_COLORSUB0 + 0x8)
+#define HWT_TVENC_COLORSUB0_CLR             HWIO_32_WO
+#define HWN_TVENC_COLORSUB0_CLR             TVENC_COLORSUB0
+#define HWI_TVENC_COLORSUB0_CLR             
+#define HW_TVENC_COLORSUB0_TOG              HW(TVENC_COLORSUB0_TOG)
+#define HWA_TVENC_COLORSUB0_TOG             (HWA_TVENC_COLORSUB0 + 0xc)
+#define HWT_TVENC_COLORSUB0_TOG             HWIO_32_WO
+#define HWN_TVENC_COLORSUB0_TOG             TVENC_COLORSUB0
+#define HWI_TVENC_COLORSUB0_TOG             
+#define BP_TVENC_COLORSUB0_PHASE_INC        0
+#define BM_TVENC_COLORSUB0_PHASE_INC        0xffffffff
+#define BF_TVENC_COLORSUB0_PHASE_INC(v)     (((v) & 0xffffffff) << 0)
+#define BFM_TVENC_COLORSUB0_PHASE_INC(v)    BM_TVENC_COLORSUB0_PHASE_INC
+#define BF_TVENC_COLORSUB0_PHASE_INC_V(e)   BF_TVENC_COLORSUB0_PHASE_INC(BV_TVENC_COLORSUB0_PHASE_INC__##e)
+#define BFM_TVENC_COLORSUB0_PHASE_INC_V(v)  BM_TVENC_COLORSUB0_PHASE_INC
+
+#define HW_TVENC_COLORSUB1                      HW(TVENC_COLORSUB1)
+#define HWA_TVENC_COLORSUB1                     (0x80038000 + 0xd0)
+#define HWT_TVENC_COLORSUB1                     HWIO_32_RW
+#define HWN_TVENC_COLORSUB1                     TVENC_COLORSUB1
+#define HWI_TVENC_COLORSUB1                     
+#define HW_TVENC_COLORSUB1_SET                  HW(TVENC_COLORSUB1_SET)
+#define HWA_TVENC_COLORSUB1_SET                 (HWA_TVENC_COLORSUB1 + 0x4)
+#define HWT_TVENC_COLORSUB1_SET                 HWIO_32_WO
+#define HWN_TVENC_COLORSUB1_SET                 TVENC_COLORSUB1
+#define HWI_TVENC_COLORSUB1_SET                 
+#define HW_TVENC_COLORSUB1_CLR                  HW(TVENC_COLORSUB1_CLR)
+#define HWA_TVENC_COLORSUB1_CLR                 (HWA_TVENC_COLORSUB1 + 0x8)
+#define HWT_TVENC_COLORSUB1_CLR                 HWIO_32_WO
+#define HWN_TVENC_COLORSUB1_CLR                 TVENC_COLORSUB1
+#define HWI_TVENC_COLORSUB1_CLR                 
+#define HW_TVENC_COLORSUB1_TOG                  HW(TVENC_COLORSUB1_TOG)
+#define HWA_TVENC_COLORSUB1_TOG                 (HWA_TVENC_COLORSUB1 + 0xc)
+#define HWT_TVENC_COLORSUB1_TOG                 HWIO_32_WO
+#define HWN_TVENC_COLORSUB1_TOG                 TVENC_COLORSUB1
+#define HWI_TVENC_COLORSUB1_TOG                 
+#define BP_TVENC_COLORSUB1_PHASE_OFFSET         0
+#define BM_TVENC_COLORSUB1_PHASE_OFFSET         0xffffffff
+#define BF_TVENC_COLORSUB1_PHASE_OFFSET(v)      (((v) & 0xffffffff) << 0)
+#define BFM_TVENC_COLORSUB1_PHASE_OFFSET(v)     BM_TVENC_COLORSUB1_PHASE_OFFSET
+#define BF_TVENC_COLORSUB1_PHASE_OFFSET_V(e)    BF_TVENC_COLORSUB1_PHASE_OFFSET(BV_TVENC_COLORSUB1_PHASE_OFFSET__##e)
+#define BFM_TVENC_COLORSUB1_PHASE_OFFSET_V(v)   BM_TVENC_COLORSUB1_PHASE_OFFSET
+
+#define HW_TVENC_COPYPROTECT                        HW(TVENC_COPYPROTECT)
+#define HWA_TVENC_COPYPROTECT                       (0x80038000 + 0xe0)
+#define HWT_TVENC_COPYPROTECT                       HWIO_32_RW
+#define HWN_TVENC_COPYPROTECT                       TVENC_COPYPROTECT
+#define HWI_TVENC_COPYPROTECT                       
+#define HW_TVENC_COPYPROTECT_SET                    HW(TVENC_COPYPROTECT_SET)
+#define HWA_TVENC_COPYPROTECT_SET                   (HWA_TVENC_COPYPROTECT + 0x4)
+#define HWT_TVENC_COPYPROTECT_SET                   HWIO_32_WO
+#define HWN_TVENC_COPYPROTECT_SET                   TVENC_COPYPROTECT
+#define HWI_TVENC_COPYPROTECT_SET                   
+#define HW_TVENC_COPYPROTECT_CLR                    HW(TVENC_COPYPROTECT_CLR)
+#define HWA_TVENC_COPYPROTECT_CLR                   (HWA_TVENC_COPYPROTECT + 0x8)
+#define HWT_TVENC_COPYPROTECT_CLR                   HWIO_32_WO
+#define HWN_TVENC_COPYPROTECT_CLR                   TVENC_COPYPROTECT
+#define HWI_TVENC_COPYPROTECT_CLR                   
+#define HW_TVENC_COPYPROTECT_TOG                    HW(TVENC_COPYPROTECT_TOG)
+#define HWA_TVENC_COPYPROTECT_TOG                   (HWA_TVENC_COPYPROTECT + 0xc)
+#define HWT_TVENC_COPYPROTECT_TOG                   HWIO_32_WO
+#define HWN_TVENC_COPYPROTECT_TOG                   TVENC_COPYPROTECT
+#define HWI_TVENC_COPYPROTECT_TOG                   
+#define BP_TVENC_COPYPROTECT_RSRVD1                 16
+#define BM_TVENC_COPYPROTECT_RSRVD1                 0xffff0000
+#define BF_TVENC_COPYPROTECT_RSRVD1(v)              (((v) & 0xffff) << 16)
+#define BFM_TVENC_COPYPROTECT_RSRVD1(v)             BM_TVENC_COPYPROTECT_RSRVD1
+#define BF_TVENC_COPYPROTECT_RSRVD1_V(e)            BF_TVENC_COPYPROTECT_RSRVD1(BV_TVENC_COPYPROTECT_RSRVD1__##e)
+#define BFM_TVENC_COPYPROTECT_RSRVD1_V(v)           BM_TVENC_COPYPROTECT_RSRVD1
+#define BP_TVENC_COPYPROTECT_WSS_ENBL               15
+#define BM_TVENC_COPYPROTECT_WSS_ENBL               0x8000
+#define BF_TVENC_COPYPROTECT_WSS_ENBL(v)            (((v) & 0x1) << 15)
+#define BFM_TVENC_COPYPROTECT_WSS_ENBL(v)           BM_TVENC_COPYPROTECT_WSS_ENBL
+#define BF_TVENC_COPYPROTECT_WSS_ENBL_V(e)          BF_TVENC_COPYPROTECT_WSS_ENBL(BV_TVENC_COPYPROTECT_WSS_ENBL__##e)
+#define BFM_TVENC_COPYPROTECT_WSS_ENBL_V(v)         BM_TVENC_COPYPROTECT_WSS_ENBL
+#define BP_TVENC_COPYPROTECT_CGMS_ENBL              14
+#define BM_TVENC_COPYPROTECT_CGMS_ENBL              0x4000
+#define BF_TVENC_COPYPROTECT_CGMS_ENBL(v)           (((v) & 0x1) << 14)
+#define BFM_TVENC_COPYPROTECT_CGMS_ENBL(v)          BM_TVENC_COPYPROTECT_CGMS_ENBL
+#define BF_TVENC_COPYPROTECT_CGMS_ENBL_V(e)         BF_TVENC_COPYPROTECT_CGMS_ENBL(BV_TVENC_COPYPROTECT_CGMS_ENBL__##e)
+#define BFM_TVENC_COPYPROTECT_CGMS_ENBL_V(v)        BM_TVENC_COPYPROTECT_CGMS_ENBL
+#define BP_TVENC_COPYPROTECT_WSS_CGMS_DATA          0
+#define BM_TVENC_COPYPROTECT_WSS_CGMS_DATA          0x3fff
+#define BF_TVENC_COPYPROTECT_WSS_CGMS_DATA(v)       (((v) & 0x3fff) << 0)
+#define BFM_TVENC_COPYPROTECT_WSS_CGMS_DATA(v)      BM_TVENC_COPYPROTECT_WSS_CGMS_DATA
+#define BF_TVENC_COPYPROTECT_WSS_CGMS_DATA_V(e)     BF_TVENC_COPYPROTECT_WSS_CGMS_DATA(BV_TVENC_COPYPROTECT_WSS_CGMS_DATA__##e)
+#define BFM_TVENC_COPYPROTECT_WSS_CGMS_DATA_V(v)    BM_TVENC_COPYPROTECT_WSS_CGMS_DATA
+
+#define HW_TVENC_CLOSEDCAPTION                  HW(TVENC_CLOSEDCAPTION)
+#define HWA_TVENC_CLOSEDCAPTION                 (0x80038000 + 0xf0)
+#define HWT_TVENC_CLOSEDCAPTION                 HWIO_32_RW
+#define HWN_TVENC_CLOSEDCAPTION                 TVENC_CLOSEDCAPTION
+#define HWI_TVENC_CLOSEDCAPTION                 
+#define HW_TVENC_CLOSEDCAPTION_SET              HW(TVENC_CLOSEDCAPTION_SET)
+#define HWA_TVENC_CLOSEDCAPTION_SET             (HWA_TVENC_CLOSEDCAPTION + 0x4)
+#define HWT_TVENC_CLOSEDCAPTION_SET             HWIO_32_WO
+#define HWN_TVENC_CLOSEDCAPTION_SET             TVENC_CLOSEDCAPTION
+#define HWI_TVENC_CLOSEDCAPTION_SET             
+#define HW_TVENC_CLOSEDCAPTION_CLR              HW(TVENC_CLOSEDCAPTION_CLR)
+#define HWA_TVENC_CLOSEDCAPTION_CLR             (HWA_TVENC_CLOSEDCAPTION + 0x8)
+#define HWT_TVENC_CLOSEDCAPTION_CLR             HWIO_32_WO
+#define HWN_TVENC_CLOSEDCAPTION_CLR             TVENC_CLOSEDCAPTION
+#define HWI_TVENC_CLOSEDCAPTION_CLR             
+#define HW_TVENC_CLOSEDCAPTION_TOG              HW(TVENC_CLOSEDCAPTION_TOG)
+#define HWA_TVENC_CLOSEDCAPTION_TOG             (HWA_TVENC_CLOSEDCAPTION + 0xc)
+#define HWT_TVENC_CLOSEDCAPTION_TOG             HWIO_32_WO
+#define HWN_TVENC_CLOSEDCAPTION_TOG             TVENC_CLOSEDCAPTION
+#define HWI_TVENC_CLOSEDCAPTION_TOG             
+#define BP_TVENC_CLOSEDCAPTION_RSRVD1           20
+#define BM_TVENC_CLOSEDCAPTION_RSRVD1           0xfff00000
+#define BF_TVENC_CLOSEDCAPTION_RSRVD1(v)        (((v) & 0xfff) << 20)
+#define BFM_TVENC_CLOSEDCAPTION_RSRVD1(v)       BM_TVENC_CLOSEDCAPTION_RSRVD1
+#define BF_TVENC_CLOSEDCAPTION_RSRVD1_V(e)      BF_TVENC_CLOSEDCAPTION_RSRVD1(BV_TVENC_CLOSEDCAPTION_RSRVD1__##e)
+#define BFM_TVENC_CLOSEDCAPTION_RSRVD1_V(v)     BM_TVENC_CLOSEDCAPTION_RSRVD1
+#define BP_TVENC_CLOSEDCAPTION_CC_ENBL          18
+#define BM_TVENC_CLOSEDCAPTION_CC_ENBL          0xc0000
+#define BF_TVENC_CLOSEDCAPTION_CC_ENBL(v)       (((v) & 0x3) << 18)
+#define BFM_TVENC_CLOSEDCAPTION_CC_ENBL(v)      BM_TVENC_CLOSEDCAPTION_CC_ENBL
+#define BF_TVENC_CLOSEDCAPTION_CC_ENBL_V(e)     BF_TVENC_CLOSEDCAPTION_CC_ENBL(BV_TVENC_CLOSEDCAPTION_CC_ENBL__##e)
+#define BFM_TVENC_CLOSEDCAPTION_CC_ENBL_V(v)    BM_TVENC_CLOSEDCAPTION_CC_ENBL
+#define BP_TVENC_CLOSEDCAPTION_CC_FILL          16
+#define BM_TVENC_CLOSEDCAPTION_CC_FILL          0x30000
+#define BF_TVENC_CLOSEDCAPTION_CC_FILL(v)       (((v) & 0x3) << 16)
+#define BFM_TVENC_CLOSEDCAPTION_CC_FILL(v)      BM_TVENC_CLOSEDCAPTION_CC_FILL
+#define BF_TVENC_CLOSEDCAPTION_CC_FILL_V(e)     BF_TVENC_CLOSEDCAPTION_CC_FILL(BV_TVENC_CLOSEDCAPTION_CC_FILL__##e)
+#define BFM_TVENC_CLOSEDCAPTION_CC_FILL_V(v)    BM_TVENC_CLOSEDCAPTION_CC_FILL
+#define BP_TVENC_CLOSEDCAPTION_CC_DATA          0
+#define BM_TVENC_CLOSEDCAPTION_CC_DATA          0xffff
+#define BF_TVENC_CLOSEDCAPTION_CC_DATA(v)       (((v) & 0xffff) << 0)
+#define BFM_TVENC_CLOSEDCAPTION_CC_DATA(v)      BM_TVENC_CLOSEDCAPTION_CC_DATA
+#define BF_TVENC_CLOSEDCAPTION_CC_DATA_V(e)     BF_TVENC_CLOSEDCAPTION_CC_DATA(BV_TVENC_CLOSEDCAPTION_CC_DATA__##e)
+#define BFM_TVENC_CLOSEDCAPTION_CC_DATA_V(v)    BM_TVENC_CLOSEDCAPTION_CC_DATA
+
+#define HW_TVENC_COLORBURST                 HW(TVENC_COLORBURST)
+#define HWA_TVENC_COLORBURST                (0x80038000 + 0x140)
+#define HWT_TVENC_COLORBURST                HWIO_32_RW
+#define HWN_TVENC_COLORBURST                TVENC_COLORBURST
+#define HWI_TVENC_COLORBURST                
+#define HW_TVENC_COLORBURST_SET             HW(TVENC_COLORBURST_SET)
+#define HWA_TVENC_COLORBURST_SET            (HWA_TVENC_COLORBURST + 0x4)
+#define HWT_TVENC_COLORBURST_SET            HWIO_32_WO
+#define HWN_TVENC_COLORBURST_SET            TVENC_COLORBURST
+#define HWI_TVENC_COLORBURST_SET            
+#define HW_TVENC_COLORBURST_CLR             HW(TVENC_COLORBURST_CLR)
+#define HWA_TVENC_COLORBURST_CLR            (HWA_TVENC_COLORBURST + 0x8)
+#define HWT_TVENC_COLORBURST_CLR            HWIO_32_WO
+#define HWN_TVENC_COLORBURST_CLR            TVENC_COLORBURST
+#define HWI_TVENC_COLORBURST_CLR            
+#define HW_TVENC_COLORBURST_TOG             HW(TVENC_COLORBURST_TOG)
+#define HWA_TVENC_COLORBURST_TOG            (HWA_TVENC_COLORBURST + 0xc)
+#define HWT_TVENC_COLORBURST_TOG            HWIO_32_WO
+#define HWN_TVENC_COLORBURST_TOG            TVENC_COLORBURST
+#define HWI_TVENC_COLORBURST_TOG            
+#define BP_TVENC_COLORBURST_NBA             24
+#define BM_TVENC_COLORBURST_NBA             0xff000000
+#define BF_TVENC_COLORBURST_NBA(v)          (((v) & 0xff) << 24)
+#define BFM_TVENC_COLORBURST_NBA(v)         BM_TVENC_COLORBURST_NBA
+#define BF_TVENC_COLORBURST_NBA_V(e)        BF_TVENC_COLORBURST_NBA(BV_TVENC_COLORBURST_NBA__##e)
+#define BFM_TVENC_COLORBURST_NBA_V(v)       BM_TVENC_COLORBURST_NBA
+#define BP_TVENC_COLORBURST_PBA             16
+#define BM_TVENC_COLORBURST_PBA             0xff0000
+#define BF_TVENC_COLORBURST_PBA(v)          (((v) & 0xff) << 16)
+#define BFM_TVENC_COLORBURST_PBA(v)         BM_TVENC_COLORBURST_PBA
+#define BF_TVENC_COLORBURST_PBA_V(e)        BF_TVENC_COLORBURST_PBA(BV_TVENC_COLORBURST_PBA__##e)
+#define BFM_TVENC_COLORBURST_PBA_V(v)       BM_TVENC_COLORBURST_PBA
+#define BP_TVENC_COLORBURST_RSRVD1          12
+#define BM_TVENC_COLORBURST_RSRVD1          0xf000
+#define BF_TVENC_COLORBURST_RSRVD1(v)       (((v) & 0xf) << 12)
+#define BFM_TVENC_COLORBURST_RSRVD1(v)      BM_TVENC_COLORBURST_RSRVD1
+#define BF_TVENC_COLORBURST_RSRVD1_V(e)     BF_TVENC_COLORBURST_RSRVD1(BV_TVENC_COLORBURST_RSRVD1__##e)
+#define BFM_TVENC_COLORBURST_RSRVD1_V(v)    BM_TVENC_COLORBURST_RSRVD1
+#define BP_TVENC_COLORBURST_RSRVD2          0
+#define BM_TVENC_COLORBURST_RSRVD2          0xfff
+#define BF_TVENC_COLORBURST_RSRVD2(v)       (((v) & 0xfff) << 0)
+#define BFM_TVENC_COLORBURST_RSRVD2(v)      BM_TVENC_COLORBURST_RSRVD2
+#define BF_TVENC_COLORBURST_RSRVD2_V(e)     BF_TVENC_COLORBURST_RSRVD2(BV_TVENC_COLORBURST_RSRVD2__##e)
+#define BFM_TVENC_COLORBURST_RSRVD2_V(v)    BM_TVENC_COLORBURST_RSRVD2
+
+#define HW_TVENC_MACROVISION0               HW(TVENC_MACROVISION0)
+#define HWA_TVENC_MACROVISION0              (0x80038000 + 0x150)
+#define HWT_TVENC_MACROVISION0              HWIO_32_RW
+#define HWN_TVENC_MACROVISION0              TVENC_MACROVISION0
+#define HWI_TVENC_MACROVISION0              
+#define HW_TVENC_MACROVISION0_SET           HW(TVENC_MACROVISION0_SET)
+#define HWA_TVENC_MACROVISION0_SET          (HWA_TVENC_MACROVISION0 + 0x4)
+#define HWT_TVENC_MACROVISION0_SET          HWIO_32_WO
+#define HWN_TVENC_MACROVISION0_SET          TVENC_MACROVISION0
+#define HWI_TVENC_MACROVISION0_SET          
+#define HW_TVENC_MACROVISION0_CLR           HW(TVENC_MACROVISION0_CLR)
+#define HWA_TVENC_MACROVISION0_CLR          (HWA_TVENC_MACROVISION0 + 0x8)
+#define HWT_TVENC_MACROVISION0_CLR          HWIO_32_WO
+#define HWN_TVENC_MACROVISION0_CLR          TVENC_MACROVISION0
+#define HWI_TVENC_MACROVISION0_CLR          
+#define HW_TVENC_MACROVISION0_TOG           HW(TVENC_MACROVISION0_TOG)
+#define HWA_TVENC_MACROVISION0_TOG          (HWA_TVENC_MACROVISION0 + 0xc)
+#define HWT_TVENC_MACROVISION0_TOG          HWIO_32_WO
+#define HWN_TVENC_MACROVISION0_TOG          TVENC_MACROVISION0
+#define HWI_TVENC_MACROVISION0_TOG          
+#define BP_TVENC_MACROVISION0_DATA          0
+#define BM_TVENC_MACROVISION0_DATA          0xffffffff
+#define BF_TVENC_MACROVISION0_DATA(v)       (((v) & 0xffffffff) << 0)
+#define BFM_TVENC_MACROVISION0_DATA(v)      BM_TVENC_MACROVISION0_DATA
+#define BF_TVENC_MACROVISION0_DATA_V(e)     BF_TVENC_MACROVISION0_DATA(BV_TVENC_MACROVISION0_DATA__##e)
+#define BFM_TVENC_MACROVISION0_DATA_V(v)    BM_TVENC_MACROVISION0_DATA
+
+#define HW_TVENC_MACROVISION1               HW(TVENC_MACROVISION1)
+#define HWA_TVENC_MACROVISION1              (0x80038000 + 0x160)
+#define HWT_TVENC_MACROVISION1              HWIO_32_RW
+#define HWN_TVENC_MACROVISION1              TVENC_MACROVISION1
+#define HWI_TVENC_MACROVISION1              
+#define HW_TVENC_MACROVISION1_SET           HW(TVENC_MACROVISION1_SET)
+#define HWA_TVENC_MACROVISION1_SET          (HWA_TVENC_MACROVISION1 + 0x4)
+#define HWT_TVENC_MACROVISION1_SET          HWIO_32_WO
+#define HWN_TVENC_MACROVISION1_SET          TVENC_MACROVISION1
+#define HWI_TVENC_MACROVISION1_SET          
+#define HW_TVENC_MACROVISION1_CLR           HW(TVENC_MACROVISION1_CLR)
+#define HWA_TVENC_MACROVISION1_CLR          (HWA_TVENC_MACROVISION1 + 0x8)
+#define HWT_TVENC_MACROVISION1_CLR          HWIO_32_WO
+#define HWN_TVENC_MACROVISION1_CLR          TVENC_MACROVISION1
+#define HWI_TVENC_MACROVISION1_CLR          
+#define HW_TVENC_MACROVISION1_TOG           HW(TVENC_MACROVISION1_TOG)
+#define HWA_TVENC_MACROVISION1_TOG          (HWA_TVENC_MACROVISION1 + 0xc)
+#define HWT_TVENC_MACROVISION1_TOG          HWIO_32_WO
+#define HWN_TVENC_MACROVISION1_TOG          TVENC_MACROVISION1
+#define HWI_TVENC_MACROVISION1_TOG          
+#define BP_TVENC_MACROVISION1_DATA          0
+#define BM_TVENC_MACROVISION1_DATA          0xffffffff
+#define BF_TVENC_MACROVISION1_DATA(v)       (((v) & 0xffffffff) << 0)
+#define BFM_TVENC_MACROVISION1_DATA(v)      BM_TVENC_MACROVISION1_DATA
+#define BF_TVENC_MACROVISION1_DATA_V(e)     BF_TVENC_MACROVISION1_DATA(BV_TVENC_MACROVISION1_DATA__##e)
+#define BFM_TVENC_MACROVISION1_DATA_V(v)    BM_TVENC_MACROVISION1_DATA
+
+#define HW_TVENC_MACROVISION2               HW(TVENC_MACROVISION2)
+#define HWA_TVENC_MACROVISION2              (0x80038000 + 0x170)
+#define HWT_TVENC_MACROVISION2              HWIO_32_RW
+#define HWN_TVENC_MACROVISION2              TVENC_MACROVISION2
+#define HWI_TVENC_MACROVISION2              
+#define HW_TVENC_MACROVISION2_SET           HW(TVENC_MACROVISION2_SET)
+#define HWA_TVENC_MACROVISION2_SET          (HWA_TVENC_MACROVISION2 + 0x4)
+#define HWT_TVENC_MACROVISION2_SET          HWIO_32_WO
+#define HWN_TVENC_MACROVISION2_SET          TVENC_MACROVISION2
+#define HWI_TVENC_MACROVISION2_SET          
+#define HW_TVENC_MACROVISION2_CLR           HW(TVENC_MACROVISION2_CLR)
+#define HWA_TVENC_MACROVISION2_CLR          (HWA_TVENC_MACROVISION2 + 0x8)
+#define HWT_TVENC_MACROVISION2_CLR          HWIO_32_WO
+#define HWN_TVENC_MACROVISION2_CLR          TVENC_MACROVISION2
+#define HWI_TVENC_MACROVISION2_CLR          
+#define HW_TVENC_MACROVISION2_TOG           HW(TVENC_MACROVISION2_TOG)
+#define HWA_TVENC_MACROVISION2_TOG          (HWA_TVENC_MACROVISION2 + 0xc)
+#define HWT_TVENC_MACROVISION2_TOG          HWIO_32_WO
+#define HWN_TVENC_MACROVISION2_TOG          TVENC_MACROVISION2
+#define HWI_TVENC_MACROVISION2_TOG          
+#define BP_TVENC_MACROVISION2_DATA          0
+#define BM_TVENC_MACROVISION2_DATA          0xffffffff
+#define BF_TVENC_MACROVISION2_DATA(v)       (((v) & 0xffffffff) << 0)
+#define BFM_TVENC_MACROVISION2_DATA(v)      BM_TVENC_MACROVISION2_DATA
+#define BF_TVENC_MACROVISION2_DATA_V(e)     BF_TVENC_MACROVISION2_DATA(BV_TVENC_MACROVISION2_DATA__##e)
+#define BFM_TVENC_MACROVISION2_DATA_V(v)    BM_TVENC_MACROVISION2_DATA
+
+#define HW_TVENC_MACROVISION3               HW(TVENC_MACROVISION3)
+#define HWA_TVENC_MACROVISION3              (0x80038000 + 0x180)
+#define HWT_TVENC_MACROVISION3              HWIO_32_RW
+#define HWN_TVENC_MACROVISION3              TVENC_MACROVISION3
+#define HWI_TVENC_MACROVISION3              
+#define HW_TVENC_MACROVISION3_SET           HW(TVENC_MACROVISION3_SET)
+#define HWA_TVENC_MACROVISION3_SET          (HWA_TVENC_MACROVISION3 + 0x4)
+#define HWT_TVENC_MACROVISION3_SET          HWIO_32_WO
+#define HWN_TVENC_MACROVISION3_SET          TVENC_MACROVISION3
+#define HWI_TVENC_MACROVISION3_SET          
+#define HW_TVENC_MACROVISION3_CLR           HW(TVENC_MACROVISION3_CLR)
+#define HWA_TVENC_MACROVISION3_CLR          (HWA_TVENC_MACROVISION3 + 0x8)
+#define HWT_TVENC_MACROVISION3_CLR          HWIO_32_WO
+#define HWN_TVENC_MACROVISION3_CLR          TVENC_MACROVISION3
+#define HWI_TVENC_MACROVISION3_CLR          
+#define HW_TVENC_MACROVISION3_TOG           HW(TVENC_MACROVISION3_TOG)
+#define HWA_TVENC_MACROVISION3_TOG          (HWA_TVENC_MACROVISION3 + 0xc)
+#define HWT_TVENC_MACROVISION3_TOG          HWIO_32_WO
+#define HWN_TVENC_MACROVISION3_TOG          TVENC_MACROVISION3
+#define HWI_TVENC_MACROVISION3_TOG          
+#define BP_TVENC_MACROVISION3_DATA          0
+#define BM_TVENC_MACROVISION3_DATA          0xffffffff
+#define BF_TVENC_MACROVISION3_DATA(v)       (((v) & 0xffffffff) << 0)
+#define BFM_TVENC_MACROVISION3_DATA(v)      BM_TVENC_MACROVISION3_DATA
+#define BF_TVENC_MACROVISION3_DATA_V(e)     BF_TVENC_MACROVISION3_DATA(BV_TVENC_MACROVISION3_DATA__##e)
+#define BFM_TVENC_MACROVISION3_DATA_V(v)    BM_TVENC_MACROVISION3_DATA
+
+#define HW_TVENC_MACROVISION4                   HW(TVENC_MACROVISION4)
+#define HWA_TVENC_MACROVISION4                  (0x80038000 + 0x190)
+#define HWT_TVENC_MACROVISION4                  HWIO_32_RW
+#define HWN_TVENC_MACROVISION4                  TVENC_MACROVISION4
+#define HWI_TVENC_MACROVISION4                  
+#define HW_TVENC_MACROVISION4_SET               HW(TVENC_MACROVISION4_SET)
+#define HWA_TVENC_MACROVISION4_SET              (HWA_TVENC_MACROVISION4 + 0x4)
+#define HWT_TVENC_MACROVISION4_SET              HWIO_32_WO
+#define HWN_TVENC_MACROVISION4_SET              TVENC_MACROVISION4
+#define HWI_TVENC_MACROVISION4_SET              
+#define HW_TVENC_MACROVISION4_CLR               HW(TVENC_MACROVISION4_CLR)
+#define HWA_TVENC_MACROVISION4_CLR              (HWA_TVENC_MACROVISION4 + 0x8)
+#define HWT_TVENC_MACROVISION4_CLR              HWIO_32_WO
+#define HWN_TVENC_MACROVISION4_CLR              TVENC_MACROVISION4
+#define HWI_TVENC_MACROVISION4_CLR              
+#define HW_TVENC_MACROVISION4_TOG               HW(TVENC_MACROVISION4_TOG)
+#define HWA_TVENC_MACROVISION4_TOG              (HWA_TVENC_MACROVISION4 + 0xc)
+#define HWT_TVENC_MACROVISION4_TOG              HWIO_32_WO
+#define HWN_TVENC_MACROVISION4_TOG              TVENC_MACROVISION4
+#define HWI_TVENC_MACROVISION4_TOG              
+#define BP_TVENC_MACROVISION4_RSRVD2            24
+#define BM_TVENC_MACROVISION4_RSRVD2            0xff000000
+#define BF_TVENC_MACROVISION4_RSRVD2(v)         (((v) & 0xff) << 24)
+#define BFM_TVENC_MACROVISION4_RSRVD2(v)        BM_TVENC_MACROVISION4_RSRVD2
+#define BF_TVENC_MACROVISION4_RSRVD2_V(e)       BF_TVENC_MACROVISION4_RSRVD2(BV_TVENC_MACROVISION4_RSRVD2__##e)
+#define BFM_TVENC_MACROVISION4_RSRVD2_V(v)      BM_TVENC_MACROVISION4_RSRVD2
+#define BP_TVENC_MACROVISION4_MACV_TST          16
+#define BM_TVENC_MACROVISION4_MACV_TST          0xff0000
+#define BF_TVENC_MACROVISION4_MACV_TST(v)       (((v) & 0xff) << 16)
+#define BFM_TVENC_MACROVISION4_MACV_TST(v)      BM_TVENC_MACROVISION4_MACV_TST
+#define BF_TVENC_MACROVISION4_MACV_TST_V(e)     BF_TVENC_MACROVISION4_MACV_TST(BV_TVENC_MACROVISION4_MACV_TST__##e)
+#define BFM_TVENC_MACROVISION4_MACV_TST_V(v)    BM_TVENC_MACROVISION4_MACV_TST
+#define BP_TVENC_MACROVISION4_RSRVD1            11
+#define BM_TVENC_MACROVISION4_RSRVD1            0xf800
+#define BF_TVENC_MACROVISION4_RSRVD1(v)         (((v) & 0x1f) << 11)
+#define BFM_TVENC_MACROVISION4_RSRVD1(v)        BM_TVENC_MACROVISION4_RSRVD1
+#define BF_TVENC_MACROVISION4_RSRVD1_V(e)       BF_TVENC_MACROVISION4_RSRVD1(BV_TVENC_MACROVISION4_RSRVD1__##e)
+#define BFM_TVENC_MACROVISION4_RSRVD1_V(v)      BM_TVENC_MACROVISION4_RSRVD1
+#define BP_TVENC_MACROVISION4_DATA              0
+#define BM_TVENC_MACROVISION4_DATA              0x7ff
+#define BF_TVENC_MACROVISION4_DATA(v)           (((v) & 0x7ff) << 0)
+#define BFM_TVENC_MACROVISION4_DATA(v)          BM_TVENC_MACROVISION4_DATA
+#define BF_TVENC_MACROVISION4_DATA_V(e)         BF_TVENC_MACROVISION4_DATA(BV_TVENC_MACROVISION4_DATA__##e)
+#define BFM_TVENC_MACROVISION4_DATA_V(v)        BM_TVENC_MACROVISION4_DATA
+
+#define HW_TVENC_DACCTRL                            HW(TVENC_DACCTRL)
+#define HWA_TVENC_DACCTRL                           (0x80038000 + 0x1a0)
+#define HWT_TVENC_DACCTRL                           HWIO_32_RW
+#define HWN_TVENC_DACCTRL                           TVENC_DACCTRL
+#define HWI_TVENC_DACCTRL                           
+#define HW_TVENC_DACCTRL_SET                        HW(TVENC_DACCTRL_SET)
+#define HWA_TVENC_DACCTRL_SET                       (HWA_TVENC_DACCTRL + 0x4)
+#define HWT_TVENC_DACCTRL_SET                       HWIO_32_WO
+#define HWN_TVENC_DACCTRL_SET                       TVENC_DACCTRL
+#define HWI_TVENC_DACCTRL_SET                       
+#define HW_TVENC_DACCTRL_CLR                        HW(TVENC_DACCTRL_CLR)
+#define HWA_TVENC_DACCTRL_CLR                       (HWA_TVENC_DACCTRL + 0x8)
+#define HWT_TVENC_DACCTRL_CLR                       HWIO_32_WO
+#define HWN_TVENC_DACCTRL_CLR                       TVENC_DACCTRL
+#define HWI_TVENC_DACCTRL_CLR                       
+#define HW_TVENC_DACCTRL_TOG                        HW(TVENC_DACCTRL_TOG)
+#define HWA_TVENC_DACCTRL_TOG                       (HWA_TVENC_DACCTRL + 0xc)
+#define HWT_TVENC_DACCTRL_TOG                       HWIO_32_WO
+#define HWN_TVENC_DACCTRL_TOG                       TVENC_DACCTRL
+#define HWI_TVENC_DACCTRL_TOG                       
+#define BP_TVENC_DACCTRL_TEST3                      31
+#define BM_TVENC_DACCTRL_TEST3                      0x80000000
+#define BF_TVENC_DACCTRL_TEST3(v)                   (((v) & 0x1) << 31)
+#define BFM_TVENC_DACCTRL_TEST3(v)                  BM_TVENC_DACCTRL_TEST3
+#define BF_TVENC_DACCTRL_TEST3_V(e)                 BF_TVENC_DACCTRL_TEST3(BV_TVENC_DACCTRL_TEST3__##e)
+#define BFM_TVENC_DACCTRL_TEST3_V(v)                BM_TVENC_DACCTRL_TEST3
+#define BP_TVENC_DACCTRL_RSRVD1                     30
+#define BM_TVENC_DACCTRL_RSRVD1                     0x40000000
+#define BF_TVENC_DACCTRL_RSRVD1(v)                  (((v) & 0x1) << 30)
+#define BFM_TVENC_DACCTRL_RSRVD1(v)                 BM_TVENC_DACCTRL_RSRVD1
+#define BF_TVENC_DACCTRL_RSRVD1_V(e)                BF_TVENC_DACCTRL_RSRVD1(BV_TVENC_DACCTRL_RSRVD1__##e)
+#define BFM_TVENC_DACCTRL_RSRVD1_V(v)               BM_TVENC_DACCTRL_RSRVD1
+#define BP_TVENC_DACCTRL_RSRVD2                     29
+#define BM_TVENC_DACCTRL_RSRVD2                     0x20000000
+#define BF_TVENC_DACCTRL_RSRVD2(v)                  (((v) & 0x1) << 29)
+#define BFM_TVENC_DACCTRL_RSRVD2(v)                 BM_TVENC_DACCTRL_RSRVD2
+#define BF_TVENC_DACCTRL_RSRVD2_V(e)                BF_TVENC_DACCTRL_RSRVD2(BV_TVENC_DACCTRL_RSRVD2__##e)
+#define BFM_TVENC_DACCTRL_RSRVD2_V(v)               BM_TVENC_DACCTRL_RSRVD2
+#define BP_TVENC_DACCTRL_JACK1_DIS_DET_EN           28
+#define BM_TVENC_DACCTRL_JACK1_DIS_DET_EN           0x10000000
+#define BF_TVENC_DACCTRL_JACK1_DIS_DET_EN(v)        (((v) & 0x1) << 28)
+#define BFM_TVENC_DACCTRL_JACK1_DIS_DET_EN(v)       BM_TVENC_DACCTRL_JACK1_DIS_DET_EN
+#define BF_TVENC_DACCTRL_JACK1_DIS_DET_EN_V(e)      BF_TVENC_DACCTRL_JACK1_DIS_DET_EN(BV_TVENC_DACCTRL_JACK1_DIS_DET_EN__##e)
+#define BFM_TVENC_DACCTRL_JACK1_DIS_DET_EN_V(v)     BM_TVENC_DACCTRL_JACK1_DIS_DET_EN
+#define BP_TVENC_DACCTRL_TEST2                      27
+#define BM_TVENC_DACCTRL_TEST2                      0x8000000
+#define BF_TVENC_DACCTRL_TEST2(v)                   (((v) & 0x1) << 27)
+#define BFM_TVENC_DACCTRL_TEST2(v)                  BM_TVENC_DACCTRL_TEST2
+#define BF_TVENC_DACCTRL_TEST2_V(e)                 BF_TVENC_DACCTRL_TEST2(BV_TVENC_DACCTRL_TEST2__##e)
+#define BFM_TVENC_DACCTRL_TEST2_V(v)                BM_TVENC_DACCTRL_TEST2
+#define BP_TVENC_DACCTRL_RSRVD3                     26
+#define BM_TVENC_DACCTRL_RSRVD3                     0x4000000
+#define BF_TVENC_DACCTRL_RSRVD3(v)                  (((v) & 0x1) << 26)
+#define BFM_TVENC_DACCTRL_RSRVD3(v)                 BM_TVENC_DACCTRL_RSRVD3
+#define BF_TVENC_DACCTRL_RSRVD3_V(e)                BF_TVENC_DACCTRL_RSRVD3(BV_TVENC_DACCTRL_RSRVD3__##e)
+#define BFM_TVENC_DACCTRL_RSRVD3_V(v)               BM_TVENC_DACCTRL_RSRVD3
+#define BP_TVENC_DACCTRL_RSRVD4                     25
+#define BM_TVENC_DACCTRL_RSRVD4                     0x2000000
+#define BF_TVENC_DACCTRL_RSRVD4(v)                  (((v) & 0x1) << 25)
+#define BFM_TVENC_DACCTRL_RSRVD4(v)                 BM_TVENC_DACCTRL_RSRVD4
+#define BF_TVENC_DACCTRL_RSRVD4_V(e)                BF_TVENC_DACCTRL_RSRVD4(BV_TVENC_DACCTRL_RSRVD4__##e)
+#define BFM_TVENC_DACCTRL_RSRVD4_V(v)               BM_TVENC_DACCTRL_RSRVD4
+#define BP_TVENC_DACCTRL_JACK1_DET_EN               24
+#define BM_TVENC_DACCTRL_JACK1_DET_EN               0x1000000
+#define BF_TVENC_DACCTRL_JACK1_DET_EN(v)            (((v) & 0x1) << 24)
+#define BFM_TVENC_DACCTRL_JACK1_DET_EN(v)           BM_TVENC_DACCTRL_JACK1_DET_EN
+#define BF_TVENC_DACCTRL_JACK1_DET_EN_V(e)          BF_TVENC_DACCTRL_JACK1_DET_EN(BV_TVENC_DACCTRL_JACK1_DET_EN__##e)
+#define BFM_TVENC_DACCTRL_JACK1_DET_EN_V(v)         BM_TVENC_DACCTRL_JACK1_DET_EN
+#define BP_TVENC_DACCTRL_TEST1                      23
+#define BM_TVENC_DACCTRL_TEST1                      0x800000
+#define BF_TVENC_DACCTRL_TEST1(v)                   (((v) & 0x1) << 23)
+#define BFM_TVENC_DACCTRL_TEST1(v)                  BM_TVENC_DACCTRL_TEST1
+#define BF_TVENC_DACCTRL_TEST1_V(e)                 BF_TVENC_DACCTRL_TEST1(BV_TVENC_DACCTRL_TEST1__##e)
+#define BFM_TVENC_DACCTRL_TEST1_V(v)                BM_TVENC_DACCTRL_TEST1
+#define BP_TVENC_DACCTRL_DISABLE_GND_DETECT         22
+#define BM_TVENC_DACCTRL_DISABLE_GND_DETECT         0x400000
+#define BF_TVENC_DACCTRL_DISABLE_GND_DETECT(v)      (((v) & 0x1) << 22)
+#define BFM_TVENC_DACCTRL_DISABLE_GND_DETECT(v)     BM_TVENC_DACCTRL_DISABLE_GND_DETECT
+#define BF_TVENC_DACCTRL_DISABLE_GND_DETECT_V(e)    BF_TVENC_DACCTRL_DISABLE_GND_DETECT(BV_TVENC_DACCTRL_DISABLE_GND_DETECT__##e)
+#define BFM_TVENC_DACCTRL_DISABLE_GND_DETECT_V(v)   BM_TVENC_DACCTRL_DISABLE_GND_DETECT
+#define BP_TVENC_DACCTRL_JACK_DIS_ADJ               20
+#define BM_TVENC_DACCTRL_JACK_DIS_ADJ               0x300000
+#define BF_TVENC_DACCTRL_JACK_DIS_ADJ(v)            (((v) & 0x3) << 20)
+#define BFM_TVENC_DACCTRL_JACK_DIS_ADJ(v)           BM_TVENC_DACCTRL_JACK_DIS_ADJ
+#define BF_TVENC_DACCTRL_JACK_DIS_ADJ_V(e)          BF_TVENC_DACCTRL_JACK_DIS_ADJ(BV_TVENC_DACCTRL_JACK_DIS_ADJ__##e)
+#define BFM_TVENC_DACCTRL_JACK_DIS_ADJ_V(v)         BM_TVENC_DACCTRL_JACK_DIS_ADJ
+#define BP_TVENC_DACCTRL_GAINDN                     19
+#define BM_TVENC_DACCTRL_GAINDN                     0x80000
+#define BF_TVENC_DACCTRL_GAINDN(v)                  (((v) & 0x1) << 19)
+#define BFM_TVENC_DACCTRL_GAINDN(v)                 BM_TVENC_DACCTRL_GAINDN
+#define BF_TVENC_DACCTRL_GAINDN_V(e)                BF_TVENC_DACCTRL_GAINDN(BV_TVENC_DACCTRL_GAINDN__##e)
+#define BFM_TVENC_DACCTRL_GAINDN_V(v)               BM_TVENC_DACCTRL_GAINDN
+#define BP_TVENC_DACCTRL_GAINUP                     18
+#define BM_TVENC_DACCTRL_GAINUP                     0x40000
+#define BF_TVENC_DACCTRL_GAINUP(v)                  (((v) & 0x1) << 18)
+#define BFM_TVENC_DACCTRL_GAINUP(v)                 BM_TVENC_DACCTRL_GAINUP
+#define BF_TVENC_DACCTRL_GAINUP_V(e)                BF_TVENC_DACCTRL_GAINUP(BV_TVENC_DACCTRL_GAINUP__##e)
+#define BFM_TVENC_DACCTRL_GAINUP_V(v)               BM_TVENC_DACCTRL_GAINUP
+#define BP_TVENC_DACCTRL_INVERT_CLK                 17
+#define BM_TVENC_DACCTRL_INVERT_CLK                 0x20000
+#define BF_TVENC_DACCTRL_INVERT_CLK(v)              (((v) & 0x1) << 17)
+#define BFM_TVENC_DACCTRL_INVERT_CLK(v)             BM_TVENC_DACCTRL_INVERT_CLK
+#define BF_TVENC_DACCTRL_INVERT_CLK_V(e)            BF_TVENC_DACCTRL_INVERT_CLK(BV_TVENC_DACCTRL_INVERT_CLK__##e)
+#define BFM_TVENC_DACCTRL_INVERT_CLK_V(v)           BM_TVENC_DACCTRL_INVERT_CLK
+#define BP_TVENC_DACCTRL_SELECT_CLK                 16
+#define BM_TVENC_DACCTRL_SELECT_CLK                 0x10000
+#define BF_TVENC_DACCTRL_SELECT_CLK(v)              (((v) & 0x1) << 16)
+#define BFM_TVENC_DACCTRL_SELECT_CLK(v)             BM_TVENC_DACCTRL_SELECT_CLK
+#define BF_TVENC_DACCTRL_SELECT_CLK_V(e)            BF_TVENC_DACCTRL_SELECT_CLK(BV_TVENC_DACCTRL_SELECT_CLK__##e)
+#define BFM_TVENC_DACCTRL_SELECT_CLK_V(v)           BM_TVENC_DACCTRL_SELECT_CLK
+#define BP_TVENC_DACCTRL_BYPASS_ACT_CASCODE         15
+#define BM_TVENC_DACCTRL_BYPASS_ACT_CASCODE         0x8000
+#define BF_TVENC_DACCTRL_BYPASS_ACT_CASCODE(v)      (((v) & 0x1) << 15)
+#define BFM_TVENC_DACCTRL_BYPASS_ACT_CASCODE(v)     BM_TVENC_DACCTRL_BYPASS_ACT_CASCODE
+#define BF_TVENC_DACCTRL_BYPASS_ACT_CASCODE_V(e)    BF_TVENC_DACCTRL_BYPASS_ACT_CASCODE(BV_TVENC_DACCTRL_BYPASS_ACT_CASCODE__##e)
+#define BFM_TVENC_DACCTRL_BYPASS_ACT_CASCODE_V(v)   BM_TVENC_DACCTRL_BYPASS_ACT_CASCODE
+#define BP_TVENC_DACCTRL_RSRVD5                     14
+#define BM_TVENC_DACCTRL_RSRVD5                     0x4000
+#define BF_TVENC_DACCTRL_RSRVD5(v)                  (((v) & 0x1) << 14)
+#define BFM_TVENC_DACCTRL_RSRVD5(v)                 BM_TVENC_DACCTRL_RSRVD5
+#define BF_TVENC_DACCTRL_RSRVD5_V(e)                BF_TVENC_DACCTRL_RSRVD5(BV_TVENC_DACCTRL_RSRVD5__##e)
+#define BFM_TVENC_DACCTRL_RSRVD5_V(v)               BM_TVENC_DACCTRL_RSRVD5
+#define BP_TVENC_DACCTRL_RSRVD6                     13
+#define BM_TVENC_DACCTRL_RSRVD6                     0x2000
+#define BF_TVENC_DACCTRL_RSRVD6(v)                  (((v) & 0x1) << 13)
+#define BFM_TVENC_DACCTRL_RSRVD6(v)                 BM_TVENC_DACCTRL_RSRVD6
+#define BF_TVENC_DACCTRL_RSRVD6_V(e)                BF_TVENC_DACCTRL_RSRVD6(BV_TVENC_DACCTRL_RSRVD6__##e)
+#define BFM_TVENC_DACCTRL_RSRVD6_V(v)               BM_TVENC_DACCTRL_RSRVD6
+#define BP_TVENC_DACCTRL_PWRUP1                     12
+#define BM_TVENC_DACCTRL_PWRUP1                     0x1000
+#define BF_TVENC_DACCTRL_PWRUP1(v)                  (((v) & 0x1) << 12)
+#define BFM_TVENC_DACCTRL_PWRUP1(v)                 BM_TVENC_DACCTRL_PWRUP1
+#define BF_TVENC_DACCTRL_PWRUP1_V(e)                BF_TVENC_DACCTRL_PWRUP1(BV_TVENC_DACCTRL_PWRUP1__##e)
+#define BFM_TVENC_DACCTRL_PWRUP1_V(v)               BM_TVENC_DACCTRL_PWRUP1
+#define BP_TVENC_DACCTRL_WELL_TOVDD                 11
+#define BM_TVENC_DACCTRL_WELL_TOVDD                 0x800
+#define BF_TVENC_DACCTRL_WELL_TOVDD(v)              (((v) & 0x1) << 11)
+#define BFM_TVENC_DACCTRL_WELL_TOVDD(v)             BM_TVENC_DACCTRL_WELL_TOVDD
+#define BF_TVENC_DACCTRL_WELL_TOVDD_V(e)            BF_TVENC_DACCTRL_WELL_TOVDD(BV_TVENC_DACCTRL_WELL_TOVDD__##e)
+#define BFM_TVENC_DACCTRL_WELL_TOVDD_V(v)           BM_TVENC_DACCTRL_WELL_TOVDD
+#define BP_TVENC_DACCTRL_RSRVD7                     10
+#define BM_TVENC_DACCTRL_RSRVD7                     0x400
+#define BF_TVENC_DACCTRL_RSRVD7(v)                  (((v) & 0x1) << 10)
+#define BFM_TVENC_DACCTRL_RSRVD7(v)                 BM_TVENC_DACCTRL_RSRVD7
+#define BF_TVENC_DACCTRL_RSRVD7_V(e)                BF_TVENC_DACCTRL_RSRVD7(BV_TVENC_DACCTRL_RSRVD7__##e)
+#define BFM_TVENC_DACCTRL_RSRVD7_V(v)               BM_TVENC_DACCTRL_RSRVD7
+#define BP_TVENC_DACCTRL_RSRVD8                     9
+#define BM_TVENC_DACCTRL_RSRVD8                     0x200
+#define BF_TVENC_DACCTRL_RSRVD8(v)                  (((v) & 0x1) << 9)
+#define BFM_TVENC_DACCTRL_RSRVD8(v)                 BM_TVENC_DACCTRL_RSRVD8
+#define BF_TVENC_DACCTRL_RSRVD8_V(e)                BF_TVENC_DACCTRL_RSRVD8(BV_TVENC_DACCTRL_RSRVD8__##e)
+#define BFM_TVENC_DACCTRL_RSRVD8_V(v)               BM_TVENC_DACCTRL_RSRVD8
+#define BP_TVENC_DACCTRL_DUMP_TOVDD1                8
+#define BM_TVENC_DACCTRL_DUMP_TOVDD1                0x100
+#define BF_TVENC_DACCTRL_DUMP_TOVDD1(v)             (((v) & 0x1) << 8)
+#define BFM_TVENC_DACCTRL_DUMP_TOVDD1(v)            BM_TVENC_DACCTRL_DUMP_TOVDD1
+#define BF_TVENC_DACCTRL_DUMP_TOVDD1_V(e)           BF_TVENC_DACCTRL_DUMP_TOVDD1(BV_TVENC_DACCTRL_DUMP_TOVDD1__##e)
+#define BFM_TVENC_DACCTRL_DUMP_TOVDD1_V(v)          BM_TVENC_DACCTRL_DUMP_TOVDD1
+#define BP_TVENC_DACCTRL_LOWER_SIGNAL               7
+#define BM_TVENC_DACCTRL_LOWER_SIGNAL               0x80
+#define BF_TVENC_DACCTRL_LOWER_SIGNAL(v)            (((v) & 0x1) << 7)
+#define BFM_TVENC_DACCTRL_LOWER_SIGNAL(v)           BM_TVENC_DACCTRL_LOWER_SIGNAL
+#define BF_TVENC_DACCTRL_LOWER_SIGNAL_V(e)          BF_TVENC_DACCTRL_LOWER_SIGNAL(BV_TVENC_DACCTRL_LOWER_SIGNAL__##e)
+#define BFM_TVENC_DACCTRL_LOWER_SIGNAL_V(v)         BM_TVENC_DACCTRL_LOWER_SIGNAL
+#define BP_TVENC_DACCTRL_RVAL                       4
+#define BM_TVENC_DACCTRL_RVAL                       0x70
+#define BF_TVENC_DACCTRL_RVAL(v)                    (((v) & 0x7) << 4)
+#define BFM_TVENC_DACCTRL_RVAL(v)                   BM_TVENC_DACCTRL_RVAL
+#define BF_TVENC_DACCTRL_RVAL_V(e)                  BF_TVENC_DACCTRL_RVAL(BV_TVENC_DACCTRL_RVAL__##e)
+#define BFM_TVENC_DACCTRL_RVAL_V(v)                 BM_TVENC_DACCTRL_RVAL
+#define BP_TVENC_DACCTRL_NO_INTERNAL_TERM           3
+#define BM_TVENC_DACCTRL_NO_INTERNAL_TERM           0x8
+#define BF_TVENC_DACCTRL_NO_INTERNAL_TERM(v)        (((v) & 0x1) << 3)
+#define BFM_TVENC_DACCTRL_NO_INTERNAL_TERM(v)       BM_TVENC_DACCTRL_NO_INTERNAL_TERM
+#define BF_TVENC_DACCTRL_NO_INTERNAL_TERM_V(e)      BF_TVENC_DACCTRL_NO_INTERNAL_TERM(BV_TVENC_DACCTRL_NO_INTERNAL_TERM__##e)
+#define BFM_TVENC_DACCTRL_NO_INTERNAL_TERM_V(v)     BM_TVENC_DACCTRL_NO_INTERNAL_TERM
+#define BP_TVENC_DACCTRL_HALF_CURRENT               2
+#define BM_TVENC_DACCTRL_HALF_CURRENT               0x4
+#define BF_TVENC_DACCTRL_HALF_CURRENT(v)            (((v) & 0x1) << 2)
+#define BFM_TVENC_DACCTRL_HALF_CURRENT(v)           BM_TVENC_DACCTRL_HALF_CURRENT
+#define BF_TVENC_DACCTRL_HALF_CURRENT_V(e)          BF_TVENC_DACCTRL_HALF_CURRENT(BV_TVENC_DACCTRL_HALF_CURRENT__##e)
+#define BFM_TVENC_DACCTRL_HALF_CURRENT_V(v)         BM_TVENC_DACCTRL_HALF_CURRENT
+#define BP_TVENC_DACCTRL_CASC_ADJ                   0
+#define BM_TVENC_DACCTRL_CASC_ADJ                   0x3
+#define BF_TVENC_DACCTRL_CASC_ADJ(v)                (((v) & 0x3) << 0)
+#define BFM_TVENC_DACCTRL_CASC_ADJ(v)               BM_TVENC_DACCTRL_CASC_ADJ
+#define BF_TVENC_DACCTRL_CASC_ADJ_V(e)              BF_TVENC_DACCTRL_CASC_ADJ(BV_TVENC_DACCTRL_CASC_ADJ__##e)
+#define BFM_TVENC_DACCTRL_CASC_ADJ_V(v)             BM_TVENC_DACCTRL_CASC_ADJ
+
+#define HW_TVENC_DACSTATUS                          HW(TVENC_DACSTATUS)
+#define HWA_TVENC_DACSTATUS                         (0x80038000 + 0x1b0)
+#define HWT_TVENC_DACSTATUS                         HWIO_32_RW
+#define HWN_TVENC_DACSTATUS                         TVENC_DACSTATUS
+#define HWI_TVENC_DACSTATUS                         
+#define HW_TVENC_DACSTATUS_SET                      HW(TVENC_DACSTATUS_SET)
+#define HWA_TVENC_DACSTATUS_SET                     (HWA_TVENC_DACSTATUS + 0x4)
+#define HWT_TVENC_DACSTATUS_SET                     HWIO_32_WO
+#define HWN_TVENC_DACSTATUS_SET                     TVENC_DACSTATUS
+#define HWI_TVENC_DACSTATUS_SET                     
+#define HW_TVENC_DACSTATUS_CLR                      HW(TVENC_DACSTATUS_CLR)
+#define HWA_TVENC_DACSTATUS_CLR                     (HWA_TVENC_DACSTATUS + 0x8)
+#define HWT_TVENC_DACSTATUS_CLR                     HWIO_32_WO
+#define HWN_TVENC_DACSTATUS_CLR                     TVENC_DACSTATUS
+#define HWI_TVENC_DACSTATUS_CLR                     
+#define HW_TVENC_DACSTATUS_TOG                      HW(TVENC_DACSTATUS_TOG)
+#define HWA_TVENC_DACSTATUS_TOG                     (HWA_TVENC_DACSTATUS + 0xc)
+#define HWT_TVENC_DACSTATUS_TOG                     HWIO_32_WO
+#define HWN_TVENC_DACSTATUS_TOG                     TVENC_DACSTATUS
+#define HWI_TVENC_DACSTATUS_TOG                     
+#define BP_TVENC_DACSTATUS_RSRVD1                   13
+#define BM_TVENC_DACSTATUS_RSRVD1                   0xffffe000
+#define BF_TVENC_DACSTATUS_RSRVD1(v)                (((v) & 0x7ffff) << 13)
+#define BFM_TVENC_DACSTATUS_RSRVD1(v)               BM_TVENC_DACSTATUS_RSRVD1
+#define BF_TVENC_DACSTATUS_RSRVD1_V(e)              BF_TVENC_DACSTATUS_RSRVD1(BV_TVENC_DACSTATUS_RSRVD1__##e)
+#define BFM_TVENC_DACSTATUS_RSRVD1_V(v)             BM_TVENC_DACSTATUS_RSRVD1
+#define BP_TVENC_DACSTATUS_RSRVD2                   12
+#define BM_TVENC_DACSTATUS_RSRVD2                   0x1000
+#define BF_TVENC_DACSTATUS_RSRVD2(v)                (((v) & 0x1) << 12)
+#define BFM_TVENC_DACSTATUS_RSRVD2(v)               BM_TVENC_DACSTATUS_RSRVD2
+#define BF_TVENC_DACSTATUS_RSRVD2_V(e)              BF_TVENC_DACSTATUS_RSRVD2(BV_TVENC_DACSTATUS_RSRVD2__##e)
+#define BFM_TVENC_DACSTATUS_RSRVD2_V(v)             BM_TVENC_DACSTATUS_RSRVD2
+#define BP_TVENC_DACSTATUS_RSRVD3                   11
+#define BM_TVENC_DACSTATUS_RSRVD3                   0x800
+#define BF_TVENC_DACSTATUS_RSRVD3(v)                (((v) & 0x1) << 11)
+#define BFM_TVENC_DACSTATUS_RSRVD3(v)               BM_TVENC_DACSTATUS_RSRVD3
+#define BF_TVENC_DACSTATUS_RSRVD3_V(e)              BF_TVENC_DACSTATUS_RSRVD3(BV_TVENC_DACSTATUS_RSRVD3__##e)
+#define BFM_TVENC_DACSTATUS_RSRVD3_V(v)             BM_TVENC_DACSTATUS_RSRVD3
+#define BP_TVENC_DACSTATUS_JACK1_DET_STATUS         10
+#define BM_TVENC_DACSTATUS_JACK1_DET_STATUS         0x400
+#define BF_TVENC_DACSTATUS_JACK1_DET_STATUS(v)      (((v) & 0x1) << 10)
+#define BFM_TVENC_DACSTATUS_JACK1_DET_STATUS(v)     BM_TVENC_DACSTATUS_JACK1_DET_STATUS
+#define BF_TVENC_DACSTATUS_JACK1_DET_STATUS_V(e)    BF_TVENC_DACSTATUS_JACK1_DET_STATUS(BV_TVENC_DACSTATUS_JACK1_DET_STATUS__##e)
+#define BFM_TVENC_DACSTATUS_JACK1_DET_STATUS_V(v)   BM_TVENC_DACSTATUS_JACK1_DET_STATUS
+#define BP_TVENC_DACSTATUS_RSRVD4                   9
+#define BM_TVENC_DACSTATUS_RSRVD4                   0x200
+#define BF_TVENC_DACSTATUS_RSRVD4(v)                (((v) & 0x1) << 9)
+#define BFM_TVENC_DACSTATUS_RSRVD4(v)               BM_TVENC_DACSTATUS_RSRVD4
+#define BF_TVENC_DACSTATUS_RSRVD4_V(e)              BF_TVENC_DACSTATUS_RSRVD4(BV_TVENC_DACSTATUS_RSRVD4__##e)
+#define BFM_TVENC_DACSTATUS_RSRVD4_V(v)             BM_TVENC_DACSTATUS_RSRVD4
+#define BP_TVENC_DACSTATUS_RSRVD5                   8
+#define BM_TVENC_DACSTATUS_RSRVD5                   0x100
+#define BF_TVENC_DACSTATUS_RSRVD5(v)                (((v) & 0x1) << 8)
+#define BFM_TVENC_DACSTATUS_RSRVD5(v)               BM_TVENC_DACSTATUS_RSRVD5
+#define BF_TVENC_DACSTATUS_RSRVD5_V(e)              BF_TVENC_DACSTATUS_RSRVD5(BV_TVENC_DACSTATUS_RSRVD5__##e)
+#define BFM_TVENC_DACSTATUS_RSRVD5_V(v)             BM_TVENC_DACSTATUS_RSRVD5
+#define BP_TVENC_DACSTATUS_JACK1_GROUNDED           7
+#define BM_TVENC_DACSTATUS_JACK1_GROUNDED           0x80
+#define BF_TVENC_DACSTATUS_JACK1_GROUNDED(v)        (((v) & 0x1) << 7)
+#define BFM_TVENC_DACSTATUS_JACK1_GROUNDED(v)       BM_TVENC_DACSTATUS_JACK1_GROUNDED
+#define BF_TVENC_DACSTATUS_JACK1_GROUNDED_V(e)      BF_TVENC_DACSTATUS_JACK1_GROUNDED(BV_TVENC_DACSTATUS_JACK1_GROUNDED__##e)
+#define BFM_TVENC_DACSTATUS_JACK1_GROUNDED_V(v)     BM_TVENC_DACSTATUS_JACK1_GROUNDED
+#define BP_TVENC_DACSTATUS_RSRVD6                   6
+#define BM_TVENC_DACSTATUS_RSRVD6                   0x40
+#define BF_TVENC_DACSTATUS_RSRVD6(v)                (((v) & 0x1) << 6)
+#define BFM_TVENC_DACSTATUS_RSRVD6(v)               BM_TVENC_DACSTATUS_RSRVD6
+#define BF_TVENC_DACSTATUS_RSRVD6_V(e)              BF_TVENC_DACSTATUS_RSRVD6(BV_TVENC_DACSTATUS_RSRVD6__##e)
+#define BFM_TVENC_DACSTATUS_RSRVD6_V(v)             BM_TVENC_DACSTATUS_RSRVD6
+#define BP_TVENC_DACSTATUS_RSRVD7                   5
+#define BM_TVENC_DACSTATUS_RSRVD7                   0x20
+#define BF_TVENC_DACSTATUS_RSRVD7(v)                (((v) & 0x1) << 5)
+#define BFM_TVENC_DACSTATUS_RSRVD7(v)               BM_TVENC_DACSTATUS_RSRVD7
+#define BF_TVENC_DACSTATUS_RSRVD7_V(e)              BF_TVENC_DACSTATUS_RSRVD7(BV_TVENC_DACSTATUS_RSRVD7__##e)
+#define BFM_TVENC_DACSTATUS_RSRVD7_V(v)             BM_TVENC_DACSTATUS_RSRVD7
+#define BP_TVENC_DACSTATUS_JACK1_DIS_DET_IRQ        4
+#define BM_TVENC_DACSTATUS_JACK1_DIS_DET_IRQ        0x10
+#define BF_TVENC_DACSTATUS_JACK1_DIS_DET_IRQ(v)     (((v) & 0x1) << 4)
+#define BFM_TVENC_DACSTATUS_JACK1_DIS_DET_IRQ(v)    BM_TVENC_DACSTATUS_JACK1_DIS_DET_IRQ
+#define BF_TVENC_DACSTATUS_JACK1_DIS_DET_IRQ_V(e)   BF_TVENC_DACSTATUS_JACK1_DIS_DET_IRQ(BV_TVENC_DACSTATUS_JACK1_DIS_DET_IRQ__##e)
+#define BFM_TVENC_DACSTATUS_JACK1_DIS_DET_IRQ_V(v)  BM_TVENC_DACSTATUS_JACK1_DIS_DET_IRQ
+#define BP_TVENC_DACSTATUS_RSRVD8                   3
+#define BM_TVENC_DACSTATUS_RSRVD8                   0x8
+#define BF_TVENC_DACSTATUS_RSRVD8(v)                (((v) & 0x1) << 3)
+#define BFM_TVENC_DACSTATUS_RSRVD8(v)               BM_TVENC_DACSTATUS_RSRVD8
+#define BF_TVENC_DACSTATUS_RSRVD8_V(e)              BF_TVENC_DACSTATUS_RSRVD8(BV_TVENC_DACSTATUS_RSRVD8__##e)
+#define BFM_TVENC_DACSTATUS_RSRVD8_V(v)             BM_TVENC_DACSTATUS_RSRVD8
+#define BP_TVENC_DACSTATUS_RSRVD9                   2
+#define BM_TVENC_DACSTATUS_RSRVD9                   0x4
+#define BF_TVENC_DACSTATUS_RSRVD9(v)                (((v) & 0x1) << 2)
+#define BFM_TVENC_DACSTATUS_RSRVD9(v)               BM_TVENC_DACSTATUS_RSRVD9
+#define BF_TVENC_DACSTATUS_RSRVD9_V(e)              BF_TVENC_DACSTATUS_RSRVD9(BV_TVENC_DACSTATUS_RSRVD9__##e)
+#define BFM_TVENC_DACSTATUS_RSRVD9_V(v)             BM_TVENC_DACSTATUS_RSRVD9
+#define BP_TVENC_DACSTATUS_JACK1_DET_IRQ            1
+#define BM_TVENC_DACSTATUS_JACK1_DET_IRQ            0x2
+#define BF_TVENC_DACSTATUS_JACK1_DET_IRQ(v)         (((v) & 0x1) << 1)
+#define BFM_TVENC_DACSTATUS_JACK1_DET_IRQ(v)        BM_TVENC_DACSTATUS_JACK1_DET_IRQ
+#define BF_TVENC_DACSTATUS_JACK1_DET_IRQ_V(e)       BF_TVENC_DACSTATUS_JACK1_DET_IRQ(BV_TVENC_DACSTATUS_JACK1_DET_IRQ__##e)
+#define BFM_TVENC_DACSTATUS_JACK1_DET_IRQ_V(v)      BM_TVENC_DACSTATUS_JACK1_DET_IRQ
+#define BP_TVENC_DACSTATUS_ENIRQ_JACK               0
+#define BM_TVENC_DACSTATUS_ENIRQ_JACK               0x1
+#define BF_TVENC_DACSTATUS_ENIRQ_JACK(v)            (((v) & 0x1) << 0)
+#define BFM_TVENC_DACSTATUS_ENIRQ_JACK(v)           BM_TVENC_DACSTATUS_ENIRQ_JACK
+#define BF_TVENC_DACSTATUS_ENIRQ_JACK_V(e)          BF_TVENC_DACSTATUS_ENIRQ_JACK(BV_TVENC_DACSTATUS_ENIRQ_JACK__##e)
+#define BFM_TVENC_DACSTATUS_ENIRQ_JACK_V(v)         BM_TVENC_DACSTATUS_ENIRQ_JACK
+
+#define HW_TVENC_VDACTEST                               HW(TVENC_VDACTEST)
+#define HWA_TVENC_VDACTEST                              (0x80038000 + 0x1c0)
+#define HWT_TVENC_VDACTEST                              HWIO_32_RW
+#define HWN_TVENC_VDACTEST                              TVENC_VDACTEST
+#define HWI_TVENC_VDACTEST                              
+#define HW_TVENC_VDACTEST_SET                           HW(TVENC_VDACTEST_SET)
+#define HWA_TVENC_VDACTEST_SET                          (HWA_TVENC_VDACTEST + 0x4)
+#define HWT_TVENC_VDACTEST_SET                          HWIO_32_WO
+#define HWN_TVENC_VDACTEST_SET                          TVENC_VDACTEST
+#define HWI_TVENC_VDACTEST_SET                          
+#define HW_TVENC_VDACTEST_CLR                           HW(TVENC_VDACTEST_CLR)
+#define HWA_TVENC_VDACTEST_CLR                          (HWA_TVENC_VDACTEST + 0x8)
+#define HWT_TVENC_VDACTEST_CLR                          HWIO_32_WO
+#define HWN_TVENC_VDACTEST_CLR                          TVENC_VDACTEST
+#define HWI_TVENC_VDACTEST_CLR                          
+#define HW_TVENC_VDACTEST_TOG                           HW(TVENC_VDACTEST_TOG)
+#define HWA_TVENC_VDACTEST_TOG                          (HWA_TVENC_VDACTEST + 0xc)
+#define HWT_TVENC_VDACTEST_TOG                          HWIO_32_WO
+#define HWN_TVENC_VDACTEST_TOG                          TVENC_VDACTEST
+#define HWI_TVENC_VDACTEST_TOG                          
+#define BP_TVENC_VDACTEST_RSRVD1                        14
+#define BM_TVENC_VDACTEST_RSRVD1                        0xffffc000
+#define BF_TVENC_VDACTEST_RSRVD1(v)                     (((v) & 0x3ffff) << 14)
+#define BFM_TVENC_VDACTEST_RSRVD1(v)                    BM_TVENC_VDACTEST_RSRVD1
+#define BF_TVENC_VDACTEST_RSRVD1_V(e)                   BF_TVENC_VDACTEST_RSRVD1(BV_TVENC_VDACTEST_RSRVD1__##e)
+#define BFM_TVENC_VDACTEST_RSRVD1_V(v)                  BM_TVENC_VDACTEST_RSRVD1
+#define BP_TVENC_VDACTEST_ENABLE_PIX_INT_GAIN           13
+#define BM_TVENC_VDACTEST_ENABLE_PIX_INT_GAIN           0x2000
+#define BF_TVENC_VDACTEST_ENABLE_PIX_INT_GAIN(v)        (((v) & 0x1) << 13)
+#define BFM_TVENC_VDACTEST_ENABLE_PIX_INT_GAIN(v)       BM_TVENC_VDACTEST_ENABLE_PIX_INT_GAIN
+#define BF_TVENC_VDACTEST_ENABLE_PIX_INT_GAIN_V(e)      BF_TVENC_VDACTEST_ENABLE_PIX_INT_GAIN(BV_TVENC_VDACTEST_ENABLE_PIX_INT_GAIN__##e)
+#define BFM_TVENC_VDACTEST_ENABLE_PIX_INT_GAIN_V(v)     BM_TVENC_VDACTEST_ENABLE_PIX_INT_GAIN
+#define BP_TVENC_VDACTEST_BYPASS_PIX_INT                12
+#define BM_TVENC_VDACTEST_BYPASS_PIX_INT                0x1000
+#define BF_TVENC_VDACTEST_BYPASS_PIX_INT(v)             (((v) & 0x1) << 12)
+#define BFM_TVENC_VDACTEST_BYPASS_PIX_INT(v)            BM_TVENC_VDACTEST_BYPASS_PIX_INT
+#define BF_TVENC_VDACTEST_BYPASS_PIX_INT_V(e)           BF_TVENC_VDACTEST_BYPASS_PIX_INT(BV_TVENC_VDACTEST_BYPASS_PIX_INT__##e)
+#define BFM_TVENC_VDACTEST_BYPASS_PIX_INT_V(v)          BM_TVENC_VDACTEST_BYPASS_PIX_INT
+#define BP_TVENC_VDACTEST_BYPASS_PIX_INT_DROOP          11
+#define BM_TVENC_VDACTEST_BYPASS_PIX_INT_DROOP          0x800
+#define BF_TVENC_VDACTEST_BYPASS_PIX_INT_DROOP(v)       (((v) & 0x1) << 11)
+#define BFM_TVENC_VDACTEST_BYPASS_PIX_INT_DROOP(v)      BM_TVENC_VDACTEST_BYPASS_PIX_INT_DROOP
+#define BF_TVENC_VDACTEST_BYPASS_PIX_INT_DROOP_V(e)     BF_TVENC_VDACTEST_BYPASS_PIX_INT_DROOP(BV_TVENC_VDACTEST_BYPASS_PIX_INT_DROOP__##e)
+#define BFM_TVENC_VDACTEST_BYPASS_PIX_INT_DROOP_V(v)    BM_TVENC_VDACTEST_BYPASS_PIX_INT_DROOP
+#define BP_TVENC_VDACTEST_TEST_FIFO_FULL                10
+#define BM_TVENC_VDACTEST_TEST_FIFO_FULL                0x400
+#define BF_TVENC_VDACTEST_TEST_FIFO_FULL(v)             (((v) & 0x1) << 10)
+#define BFM_TVENC_VDACTEST_TEST_FIFO_FULL(v)            BM_TVENC_VDACTEST_TEST_FIFO_FULL
+#define BF_TVENC_VDACTEST_TEST_FIFO_FULL_V(e)           BF_TVENC_VDACTEST_TEST_FIFO_FULL(BV_TVENC_VDACTEST_TEST_FIFO_FULL__##e)
+#define BFM_TVENC_VDACTEST_TEST_FIFO_FULL_V(v)          BM_TVENC_VDACTEST_TEST_FIFO_FULL
+#define BP_TVENC_VDACTEST_DATA                          0
+#define BM_TVENC_VDACTEST_DATA                          0x3ff
+#define BF_TVENC_VDACTEST_DATA(v)                       (((v) & 0x3ff) << 0)
+#define BFM_TVENC_VDACTEST_DATA(v)                      BM_TVENC_VDACTEST_DATA
+#define BF_TVENC_VDACTEST_DATA_V(e)                     BF_TVENC_VDACTEST_DATA(BV_TVENC_VDACTEST_DATA__##e)
+#define BFM_TVENC_VDACTEST_DATA_V(v)                    BM_TVENC_VDACTEST_DATA
+
+#define HW_TVENC_VERSION                HW(TVENC_VERSION)
+#define HWA_TVENC_VERSION               (0x80038000 + 0x1d0)
+#define HWT_TVENC_VERSION               HWIO_32_RW
+#define HWN_TVENC_VERSION               TVENC_VERSION
+#define HWI_TVENC_VERSION               
+#define BP_TVENC_VERSION_MAJOR          24
+#define BM_TVENC_VERSION_MAJOR          0xff000000
+#define BF_TVENC_VERSION_MAJOR(v)       (((v) & 0xff) << 24)
+#define BFM_TVENC_VERSION_MAJOR(v)      BM_TVENC_VERSION_MAJOR
+#define BF_TVENC_VERSION_MAJOR_V(e)     BF_TVENC_VERSION_MAJOR(BV_TVENC_VERSION_MAJOR__##e)
+#define BFM_TVENC_VERSION_MAJOR_V(v)    BM_TVENC_VERSION_MAJOR
+#define BP_TVENC_VERSION_MINOR          16
+#define BM_TVENC_VERSION_MINOR          0xff0000
+#define BF_TVENC_VERSION_MINOR(v)       (((v) & 0xff) << 16)
+#define BFM_TVENC_VERSION_MINOR(v)      BM_TVENC_VERSION_MINOR
+#define BF_TVENC_VERSION_MINOR_V(e)     BF_TVENC_VERSION_MINOR(BV_TVENC_VERSION_MINOR__##e)
+#define BFM_TVENC_VERSION_MINOR_V(v)    BM_TVENC_VERSION_MINOR
+#define BP_TVENC_VERSION_STEP           0
+#define BM_TVENC_VERSION_STEP           0xffff
+#define BF_TVENC_VERSION_STEP(v)        (((v) & 0xffff) << 0)
+#define BFM_TVENC_VERSION_STEP(v)       BM_TVENC_VERSION_STEP
+#define BF_TVENC_VERSION_STEP_V(e)      BF_TVENC_VERSION_STEP(BV_TVENC_VERSION_STEP__##e)
+#define BFM_TVENC_VERSION_STEP_V(v)     BM_TVENC_VERSION_STEP
+
+#endif /* __HEADERGEN_IMX233_TVENC_H__*/
diff --git a/firmware/target/arm/imx233/regs/imx233/uartapp.h b/firmware/target/arm/imx233/regs/imx233/uartapp.h
new file mode 100644
index 0000000000..22ed7b61fc
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/imx233/uartapp.h
@@ -0,0 +1,899 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * imx233 version: 2.4.0
+ * imx233 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_IMX233_UARTAPP_H__
+#define __HEADERGEN_IMX233_UARTAPP_H__
+
+#define HW_UARTAPP_CTRL0(_n1)               HW(UARTAPP_CTRL0(_n1))
+#define HWA_UARTAPP_CTRL0(_n1)              (((_n1) == 1 ? 0x8006c000 : 0x8006e000) + 0x0)
+#define HWT_UARTAPP_CTRL0(_n1)              HWIO_32_RW
+#define HWN_UARTAPP_CTRL0(_n1)              UARTAPP_CTRL0
+#define HWI_UARTAPP_CTRL0(_n1)              (_n1)
+#define HW_UARTAPP_CTRL0_SET(_n1)           HW(UARTAPP_CTRL0_SET(_n1))
+#define HWA_UARTAPP_CTRL0_SET(_n1)          (HWA_UARTAPP_CTRL0(_n1) + 0x4)
+#define HWT_UARTAPP_CTRL0_SET(_n1)          HWIO_32_WO
+#define HWN_UARTAPP_CTRL0_SET(_n1)          UARTAPP_CTRL0
+#define HWI_UARTAPP_CTRL0_SET(_n1)          (_n1)
+#define HW_UARTAPP_CTRL0_CLR(_n1)           HW(UARTAPP_CTRL0_CLR(_n1))
+#define HWA_UARTAPP_CTRL0_CLR(_n1)          (HWA_UARTAPP_CTRL0(_n1) + 0x8)
+#define HWT_UARTAPP_CTRL0_CLR(_n1)          HWIO_32_WO
+#define HWN_UARTAPP_CTRL0_CLR(_n1)          UARTAPP_CTRL0
+#define HWI_UARTAPP_CTRL0_CLR(_n1)          (_n1)
+#define HW_UARTAPP_CTRL0_TOG(_n1)           HW(UARTAPP_CTRL0_TOG(_n1))
+#define HWA_UARTAPP_CTRL0_TOG(_n1)          (HWA_UARTAPP_CTRL0(_n1) + 0xc)
+#define HWT_UARTAPP_CTRL0_TOG(_n1)          HWIO_32_WO
+#define HWN_UARTAPP_CTRL0_TOG(_n1)          UARTAPP_CTRL0
+#define HWI_UARTAPP_CTRL0_TOG(_n1)          (_n1)
+#define BP_UARTAPP_CTRL0_SFTRST             31
+#define BM_UARTAPP_CTRL0_SFTRST             0x80000000
+#define BF_UARTAPP_CTRL0_SFTRST(v)          (((v) & 0x1) << 31)
+#define BFM_UARTAPP_CTRL0_SFTRST(v)         BM_UARTAPP_CTRL0_SFTRST
+#define BF_UARTAPP_CTRL0_SFTRST_V(e)        BF_UARTAPP_CTRL0_SFTRST(BV_UARTAPP_CTRL0_SFTRST__##e)
+#define BFM_UARTAPP_CTRL0_SFTRST_V(v)       BM_UARTAPP_CTRL0_SFTRST
+#define BP_UARTAPP_CTRL0_CLKGATE            30
+#define BM_UARTAPP_CTRL0_CLKGATE            0x40000000
+#define BF_UARTAPP_CTRL0_CLKGATE(v)         (((v) & 0x1) << 30)
+#define BFM_UARTAPP_CTRL0_CLKGATE(v)        BM_UARTAPP_CTRL0_CLKGATE
+#define BF_UARTAPP_CTRL0_CLKGATE_V(e)       BF_UARTAPP_CTRL0_CLKGATE(BV_UARTAPP_CTRL0_CLKGATE__##e)
+#define BFM_UARTAPP_CTRL0_CLKGATE_V(v)      BM_UARTAPP_CTRL0_CLKGATE
+#define BP_UARTAPP_CTRL0_RUN                29
+#define BM_UARTAPP_CTRL0_RUN                0x20000000
+#define BF_UARTAPP_CTRL0_RUN(v)             (((v) & 0x1) << 29)
+#define BFM_UARTAPP_CTRL0_RUN(v)            BM_UARTAPP_CTRL0_RUN
+#define BF_UARTAPP_CTRL0_RUN_V(e)           BF_UARTAPP_CTRL0_RUN(BV_UARTAPP_CTRL0_RUN__##e)
+#define BFM_UARTAPP_CTRL0_RUN_V(v)          BM_UARTAPP_CTRL0_RUN
+#define BP_UARTAPP_CTRL0_RX_SOURCE          28
+#define BM_UARTAPP_CTRL0_RX_SOURCE          0x10000000
+#define BF_UARTAPP_CTRL0_RX_SOURCE(v)       (((v) & 0x1) << 28)
+#define BFM_UARTAPP_CTRL0_RX_SOURCE(v)      BM_UARTAPP_CTRL0_RX_SOURCE
+#define BF_UARTAPP_CTRL0_RX_SOURCE_V(e)     BF_UARTAPP_CTRL0_RX_SOURCE(BV_UARTAPP_CTRL0_RX_SOURCE__##e)
+#define BFM_UARTAPP_CTRL0_RX_SOURCE_V(v)    BM_UARTAPP_CTRL0_RX_SOURCE
+#define BP_UARTAPP_CTRL0_RXTO_ENABLE        27
+#define BM_UARTAPP_CTRL0_RXTO_ENABLE        0x8000000
+#define BF_UARTAPP_CTRL0_RXTO_ENABLE(v)     (((v) & 0x1) << 27)
+#define BFM_UARTAPP_CTRL0_RXTO_ENABLE(v)    BM_UARTAPP_CTRL0_RXTO_ENABLE
+#define BF_UARTAPP_CTRL0_RXTO_ENABLE_V(e)   BF_UARTAPP_CTRL0_RXTO_ENABLE(BV_UARTAPP_CTRL0_RXTO_ENABLE__##e)
+#define BFM_UARTAPP_CTRL0_RXTO_ENABLE_V(v)  BM_UARTAPP_CTRL0_RXTO_ENABLE
+#define BP_UARTAPP_CTRL0_RXTIMEOUT          16
+#define BM_UARTAPP_CTRL0_RXTIMEOUT          0x7ff0000
+#define BF_UARTAPP_CTRL0_RXTIMEOUT(v)       (((v) & 0x7ff) << 16)
+#define BFM_UARTAPP_CTRL0_RXTIMEOUT(v)      BM_UARTAPP_CTRL0_RXTIMEOUT
+#define BF_UARTAPP_CTRL0_RXTIMEOUT_V(e)     BF_UARTAPP_CTRL0_RXTIMEOUT(BV_UARTAPP_CTRL0_RXTIMEOUT__##e)
+#define BFM_UARTAPP_CTRL0_RXTIMEOUT_V(v)    BM_UARTAPP_CTRL0_RXTIMEOUT
+#define BP_UARTAPP_CTRL0_XFER_COUNT         0
+#define BM_UARTAPP_CTRL0_XFER_COUNT         0xffff
+#define BF_UARTAPP_CTRL0_XFER_COUNT(v)      (((v) & 0xffff) << 0)
+#define BFM_UARTAPP_CTRL0_XFER_COUNT(v)     BM_UARTAPP_CTRL0_XFER_COUNT
+#define BF_UARTAPP_CTRL0_XFER_COUNT_V(e)    BF_UARTAPP_CTRL0_XFER_COUNT(BV_UARTAPP_CTRL0_XFER_COUNT__##e)
+#define BFM_UARTAPP_CTRL0_XFER_COUNT_V(v)   BM_UARTAPP_CTRL0_XFER_COUNT
+
+#define HW_UARTAPP_CTRL1(_n1)               HW(UARTAPP_CTRL1(_n1))
+#define HWA_UARTAPP_CTRL1(_n1)              (((_n1) == 1 ? 0x8006c000 : 0x8006e000) + 0x10)
+#define HWT_UARTAPP_CTRL1(_n1)              HWIO_32_RW
+#define HWN_UARTAPP_CTRL1(_n1)              UARTAPP_CTRL1
+#define HWI_UARTAPP_CTRL1(_n1)              (_n1)
+#define HW_UARTAPP_CTRL1_SET(_n1)           HW(UARTAPP_CTRL1_SET(_n1))
+#define HWA_UARTAPP_CTRL1_SET(_n1)          (HWA_UARTAPP_CTRL1(_n1) + 0x4)
+#define HWT_UARTAPP_CTRL1_SET(_n1)          HWIO_32_WO
+#define HWN_UARTAPP_CTRL1_SET(_n1)          UARTAPP_CTRL1
+#define HWI_UARTAPP_CTRL1_SET(_n1)          (_n1)
+#define HW_UARTAPP_CTRL1_CLR(_n1)           HW(UARTAPP_CTRL1_CLR(_n1))
+#define HWA_UARTAPP_CTRL1_CLR(_n1)          (HWA_UARTAPP_CTRL1(_n1) + 0x8)
+#define HWT_UARTAPP_CTRL1_CLR(_n1)          HWIO_32_WO
+#define HWN_UARTAPP_CTRL1_CLR(_n1)          UARTAPP_CTRL1
+#define HWI_UARTAPP_CTRL1_CLR(_n1)          (_n1)
+#define HW_UARTAPP_CTRL1_TOG(_n1)           HW(UARTAPP_CTRL1_TOG(_n1))
+#define HWA_UARTAPP_CTRL1_TOG(_n1)          (HWA_UARTAPP_CTRL1(_n1) + 0xc)
+#define HWT_UARTAPP_CTRL1_TOG(_n1)          HWIO_32_WO
+#define HWN_UARTAPP_CTRL1_TOG(_n1)          UARTAPP_CTRL1
+#define HWI_UARTAPP_CTRL1_TOG(_n1)          (_n1)
+#define BP_UARTAPP_CTRL1_RSVD2              29
+#define BM_UARTAPP_CTRL1_RSVD2              0xe0000000
+#define BF_UARTAPP_CTRL1_RSVD2(v)           (((v) & 0x7) << 29)
+#define BFM_UARTAPP_CTRL1_RSVD2(v)          BM_UARTAPP_CTRL1_RSVD2
+#define BF_UARTAPP_CTRL1_RSVD2_V(e)         BF_UARTAPP_CTRL1_RSVD2(BV_UARTAPP_CTRL1_RSVD2__##e)
+#define BFM_UARTAPP_CTRL1_RSVD2_V(v)        BM_UARTAPP_CTRL1_RSVD2
+#define BP_UARTAPP_CTRL1_RUN                28
+#define BM_UARTAPP_CTRL1_RUN                0x10000000
+#define BF_UARTAPP_CTRL1_RUN(v)             (((v) & 0x1) << 28)
+#define BFM_UARTAPP_CTRL1_RUN(v)            BM_UARTAPP_CTRL1_RUN
+#define BF_UARTAPP_CTRL1_RUN_V(e)           BF_UARTAPP_CTRL1_RUN(BV_UARTAPP_CTRL1_RUN__##e)
+#define BFM_UARTAPP_CTRL1_RUN_V(v)          BM_UARTAPP_CTRL1_RUN
+#define BP_UARTAPP_CTRL1_RSVD1              16
+#define BM_UARTAPP_CTRL1_RSVD1              0xfff0000
+#define BF_UARTAPP_CTRL1_RSVD1(v)           (((v) & 0xfff) << 16)
+#define BFM_UARTAPP_CTRL1_RSVD1(v)          BM_UARTAPP_CTRL1_RSVD1
+#define BF_UARTAPP_CTRL1_RSVD1_V(e)         BF_UARTAPP_CTRL1_RSVD1(BV_UARTAPP_CTRL1_RSVD1__##e)
+#define BFM_UARTAPP_CTRL1_RSVD1_V(v)        BM_UARTAPP_CTRL1_RSVD1
+#define BP_UARTAPP_CTRL1_XFER_COUNT         0
+#define BM_UARTAPP_CTRL1_XFER_COUNT         0xffff
+#define BF_UARTAPP_CTRL1_XFER_COUNT(v)      (((v) & 0xffff) << 0)
+#define BFM_UARTAPP_CTRL1_XFER_COUNT(v)     BM_UARTAPP_CTRL1_XFER_COUNT
+#define BF_UARTAPP_CTRL1_XFER_COUNT_V(e)    BF_UARTAPP_CTRL1_XFER_COUNT(BV_UARTAPP_CTRL1_XFER_COUNT__##e)
+#define BFM_UARTAPP_CTRL1_XFER_COUNT_V(v)   BM_UARTAPP_CTRL1_XFER_COUNT
+
+#define HW_UARTAPP_CTRL2(_n1)                       HW(UARTAPP_CTRL2(_n1))
+#define HWA_UARTAPP_CTRL2(_n1)                      (((_n1) == 1 ? 0x8006c000 : 0x8006e000) + 0x20)
+#define HWT_UARTAPP_CTRL2(_n1)                      HWIO_32_RW
+#define HWN_UARTAPP_CTRL2(_n1)                      UARTAPP_CTRL2
+#define HWI_UARTAPP_CTRL2(_n1)                      (_n1)
+#define HW_UARTAPP_CTRL2_SET(_n1)                   HW(UARTAPP_CTRL2_SET(_n1))
+#define HWA_UARTAPP_CTRL2_SET(_n1)                  (HWA_UARTAPP_CTRL2(_n1) + 0x4)
+#define HWT_UARTAPP_CTRL2_SET(_n1)                  HWIO_32_WO
+#define HWN_UARTAPP_CTRL2_SET(_n1)                  UARTAPP_CTRL2
+#define HWI_UARTAPP_CTRL2_SET(_n1)                  (_n1)
+#define HW_UARTAPP_CTRL2_CLR(_n1)                   HW(UARTAPP_CTRL2_CLR(_n1))
+#define HWA_UARTAPP_CTRL2_CLR(_n1)                  (HWA_UARTAPP_CTRL2(_n1) + 0x8)
+#define HWT_UARTAPP_CTRL2_CLR(_n1)                  HWIO_32_WO
+#define HWN_UARTAPP_CTRL2_CLR(_n1)                  UARTAPP_CTRL2
+#define HWI_UARTAPP_CTRL2_CLR(_n1)                  (_n1)
+#define HW_UARTAPP_CTRL2_TOG(_n1)                   HW(UARTAPP_CTRL2_TOG(_n1))
+#define HWA_UARTAPP_CTRL2_TOG(_n1)                  (HWA_UARTAPP_CTRL2(_n1) + 0xc)
+#define HWT_UARTAPP_CTRL2_TOG(_n1)                  HWIO_32_WO
+#define HWN_UARTAPP_CTRL2_TOG(_n1)                  UARTAPP_CTRL2
+#define HWI_UARTAPP_CTRL2_TOG(_n1)                  (_n1)
+#define BP_UARTAPP_CTRL2_INVERT_RTS                 31
+#define BM_UARTAPP_CTRL2_INVERT_RTS                 0x80000000
+#define BF_UARTAPP_CTRL2_INVERT_RTS(v)              (((v) & 0x1) << 31)
+#define BFM_UARTAPP_CTRL2_INVERT_RTS(v)             BM_UARTAPP_CTRL2_INVERT_RTS
+#define BF_UARTAPP_CTRL2_INVERT_RTS_V(e)            BF_UARTAPP_CTRL2_INVERT_RTS(BV_UARTAPP_CTRL2_INVERT_RTS__##e)
+#define BFM_UARTAPP_CTRL2_INVERT_RTS_V(v)           BM_UARTAPP_CTRL2_INVERT_RTS
+#define BP_UARTAPP_CTRL2_INVERT_CTS                 30
+#define BM_UARTAPP_CTRL2_INVERT_CTS                 0x40000000
+#define BF_UARTAPP_CTRL2_INVERT_CTS(v)              (((v) & 0x1) << 30)
+#define BFM_UARTAPP_CTRL2_INVERT_CTS(v)             BM_UARTAPP_CTRL2_INVERT_CTS
+#define BF_UARTAPP_CTRL2_INVERT_CTS_V(e)            BF_UARTAPP_CTRL2_INVERT_CTS(BV_UARTAPP_CTRL2_INVERT_CTS__##e)
+#define BFM_UARTAPP_CTRL2_INVERT_CTS_V(v)           BM_UARTAPP_CTRL2_INVERT_CTS
+#define BP_UARTAPP_CTRL2_INVERT_TX                  29
+#define BM_UARTAPP_CTRL2_INVERT_TX                  0x20000000
+#define BF_UARTAPP_CTRL2_INVERT_TX(v)               (((v) & 0x1) << 29)
+#define BFM_UARTAPP_CTRL2_INVERT_TX(v)              BM_UARTAPP_CTRL2_INVERT_TX
+#define BF_UARTAPP_CTRL2_INVERT_TX_V(e)             BF_UARTAPP_CTRL2_INVERT_TX(BV_UARTAPP_CTRL2_INVERT_TX__##e)
+#define BFM_UARTAPP_CTRL2_INVERT_TX_V(v)            BM_UARTAPP_CTRL2_INVERT_TX
+#define BP_UARTAPP_CTRL2_INVERT_RX                  28
+#define BM_UARTAPP_CTRL2_INVERT_RX                  0x10000000
+#define BF_UARTAPP_CTRL2_INVERT_RX(v)               (((v) & 0x1) << 28)
+#define BFM_UARTAPP_CTRL2_INVERT_RX(v)              BM_UARTAPP_CTRL2_INVERT_RX
+#define BF_UARTAPP_CTRL2_INVERT_RX_V(e)             BF_UARTAPP_CTRL2_INVERT_RX(BV_UARTAPP_CTRL2_INVERT_RX__##e)
+#define BFM_UARTAPP_CTRL2_INVERT_RX_V(v)            BM_UARTAPP_CTRL2_INVERT_RX
+#define BP_UARTAPP_CTRL2_RTS_SEMAPHORE              27
+#define BM_UARTAPP_CTRL2_RTS_SEMAPHORE              0x8000000
+#define BF_UARTAPP_CTRL2_RTS_SEMAPHORE(v)           (((v) & 0x1) << 27)
+#define BFM_UARTAPP_CTRL2_RTS_SEMAPHORE(v)          BM_UARTAPP_CTRL2_RTS_SEMAPHORE
+#define BF_UARTAPP_CTRL2_RTS_SEMAPHORE_V(e)         BF_UARTAPP_CTRL2_RTS_SEMAPHORE(BV_UARTAPP_CTRL2_RTS_SEMAPHORE__##e)
+#define BFM_UARTAPP_CTRL2_RTS_SEMAPHORE_V(v)        BM_UARTAPP_CTRL2_RTS_SEMAPHORE
+#define BP_UARTAPP_CTRL2_DMAONERR                   26
+#define BM_UARTAPP_CTRL2_DMAONERR                   0x4000000
+#define BF_UARTAPP_CTRL2_DMAONERR(v)                (((v) & 0x1) << 26)
+#define BFM_UARTAPP_CTRL2_DMAONERR(v)               BM_UARTAPP_CTRL2_DMAONERR
+#define BF_UARTAPP_CTRL2_DMAONERR_V(e)              BF_UARTAPP_CTRL2_DMAONERR(BV_UARTAPP_CTRL2_DMAONERR__##e)
+#define BFM_UARTAPP_CTRL2_DMAONERR_V(v)             BM_UARTAPP_CTRL2_DMAONERR
+#define BP_UARTAPP_CTRL2_TXDMAE                     25
+#define BM_UARTAPP_CTRL2_TXDMAE                     0x2000000
+#define BF_UARTAPP_CTRL2_TXDMAE(v)                  (((v) & 0x1) << 25)
+#define BFM_UARTAPP_CTRL2_TXDMAE(v)                 BM_UARTAPP_CTRL2_TXDMAE
+#define BF_UARTAPP_CTRL2_TXDMAE_V(e)                BF_UARTAPP_CTRL2_TXDMAE(BV_UARTAPP_CTRL2_TXDMAE__##e)
+#define BFM_UARTAPP_CTRL2_TXDMAE_V(v)               BM_UARTAPP_CTRL2_TXDMAE
+#define BP_UARTAPP_CTRL2_RXDMAE                     24
+#define BM_UARTAPP_CTRL2_RXDMAE                     0x1000000
+#define BF_UARTAPP_CTRL2_RXDMAE(v)                  (((v) & 0x1) << 24)
+#define BFM_UARTAPP_CTRL2_RXDMAE(v)                 BM_UARTAPP_CTRL2_RXDMAE
+#define BF_UARTAPP_CTRL2_RXDMAE_V(e)                BF_UARTAPP_CTRL2_RXDMAE(BV_UARTAPP_CTRL2_RXDMAE__##e)
+#define BFM_UARTAPP_CTRL2_RXDMAE_V(v)               BM_UARTAPP_CTRL2_RXDMAE
+#define BP_UARTAPP_CTRL2_RSVD2                      23
+#define BM_UARTAPP_CTRL2_RSVD2                      0x800000
+#define BF_UARTAPP_CTRL2_RSVD2(v)                   (((v) & 0x1) << 23)
+#define BFM_UARTAPP_CTRL2_RSVD2(v)                  BM_UARTAPP_CTRL2_RSVD2
+#define BF_UARTAPP_CTRL2_RSVD2_V(e)                 BF_UARTAPP_CTRL2_RSVD2(BV_UARTAPP_CTRL2_RSVD2__##e)
+#define BFM_UARTAPP_CTRL2_RSVD2_V(v)                BM_UARTAPP_CTRL2_RSVD2
+#define BP_UARTAPP_CTRL2_RXIFLSEL                   20
+#define BM_UARTAPP_CTRL2_RXIFLSEL                   0x700000
+#define BV_UARTAPP_CTRL2_RXIFLSEL__NOT_EMPTY        0x0
+#define BV_UARTAPP_CTRL2_RXIFLSEL__ONE_QUARTER      0x1
+#define BV_UARTAPP_CTRL2_RXIFLSEL__ONE_HALF         0x2
+#define BV_UARTAPP_CTRL2_RXIFLSEL__THREE_QUARTERS   0x3
+#define BV_UARTAPP_CTRL2_RXIFLSEL__SEVEN_EIGHTHS    0x4
+#define BV_UARTAPP_CTRL2_RXIFLSEL__INVALID5         0x5
+#define BV_UARTAPP_CTRL2_RXIFLSEL__INVALID6         0x6
+#define BV_UARTAPP_CTRL2_RXIFLSEL__INVALID7         0x7
+#define BF_UARTAPP_CTRL2_RXIFLSEL(v)                (((v) & 0x7) << 20)
+#define BFM_UARTAPP_CTRL2_RXIFLSEL(v)               BM_UARTAPP_CTRL2_RXIFLSEL
+#define BF_UARTAPP_CTRL2_RXIFLSEL_V(e)              BF_UARTAPP_CTRL2_RXIFLSEL(BV_UARTAPP_CTRL2_RXIFLSEL__##e)
+#define BFM_UARTAPP_CTRL2_RXIFLSEL_V(v)             BM_UARTAPP_CTRL2_RXIFLSEL
+#define BP_UARTAPP_CTRL2_RSVD3                      19
+#define BM_UARTAPP_CTRL2_RSVD3                      0x80000
+#define BF_UARTAPP_CTRL2_RSVD3(v)                   (((v) & 0x1) << 19)
+#define BFM_UARTAPP_CTRL2_RSVD3(v)                  BM_UARTAPP_CTRL2_RSVD3
+#define BF_UARTAPP_CTRL2_RSVD3_V(e)                 BF_UARTAPP_CTRL2_RSVD3(BV_UARTAPP_CTRL2_RSVD3__##e)
+#define BFM_UARTAPP_CTRL2_RSVD3_V(v)                BM_UARTAPP_CTRL2_RSVD3
+#define BP_UARTAPP_CTRL2_TXIFLSEL                   16
+#define BM_UARTAPP_CTRL2_TXIFLSEL                   0x70000
+#define BV_UARTAPP_CTRL2_TXIFLSEL__EMPTY            0x0
+#define BV_UARTAPP_CTRL2_TXIFLSEL__ONE_QUARTER      0x1
+#define BV_UARTAPP_CTRL2_TXIFLSEL__ONE_HALF         0x2
+#define BV_UARTAPP_CTRL2_TXIFLSEL__THREE_QUARTERS   0x3
+#define BV_UARTAPP_CTRL2_TXIFLSEL__SEVEN_EIGHTHS    0x4
+#define BV_UARTAPP_CTRL2_TXIFLSEL__INVALID5         0x5
+#define BV_UARTAPP_CTRL2_TXIFLSEL__INVALID6         0x6
+#define BV_UARTAPP_CTRL2_TXIFLSEL__INVALID7         0x7
+#define BF_UARTAPP_CTRL2_TXIFLSEL(v)                (((v) & 0x7) << 16)
+#define BFM_UARTAPP_CTRL2_TXIFLSEL(v)               BM_UARTAPP_CTRL2_TXIFLSEL
+#define BF_UARTAPP_CTRL2_TXIFLSEL_V(e)              BF_UARTAPP_CTRL2_TXIFLSEL(BV_UARTAPP_CTRL2_TXIFLSEL__##e)
+#define BFM_UARTAPP_CTRL2_TXIFLSEL_V(v)             BM_UARTAPP_CTRL2_TXIFLSEL
+#define BP_UARTAPP_CTRL2_CTSEN                      15
+#define BM_UARTAPP_CTRL2_CTSEN                      0x8000
+#define BF_UARTAPP_CTRL2_CTSEN(v)                   (((v) & 0x1) << 15)
+#define BFM_UARTAPP_CTRL2_CTSEN(v)                  BM_UARTAPP_CTRL2_CTSEN
+#define BF_UARTAPP_CTRL2_CTSEN_V(e)                 BF_UARTAPP_CTRL2_CTSEN(BV_UARTAPP_CTRL2_CTSEN__##e)
+#define BFM_UARTAPP_CTRL2_CTSEN_V(v)                BM_UARTAPP_CTRL2_CTSEN
+#define BP_UARTAPP_CTRL2_RTSEN                      14
+#define BM_UARTAPP_CTRL2_RTSEN                      0x4000
+#define BF_UARTAPP_CTRL2_RTSEN(v)                   (((v) & 0x1) << 14)
+#define BFM_UARTAPP_CTRL2_RTSEN(v)                  BM_UARTAPP_CTRL2_RTSEN
+#define BF_UARTAPP_CTRL2_RTSEN_V(e)                 BF_UARTAPP_CTRL2_RTSEN(BV_UARTAPP_CTRL2_RTSEN__##e)
+#define BFM_UARTAPP_CTRL2_RTSEN_V(v)                BM_UARTAPP_CTRL2_RTSEN
+#define BP_UARTAPP_CTRL2_OUT2                       13
+#define BM_UARTAPP_CTRL2_OUT2                       0x2000
+#define BF_UARTAPP_CTRL2_OUT2(v)                    (((v) & 0x1) << 13)
+#define BFM_UARTAPP_CTRL2_OUT2(v)                   BM_UARTAPP_CTRL2_OUT2
+#define BF_UARTAPP_CTRL2_OUT2_V(e)                  BF_UARTAPP_CTRL2_OUT2(BV_UARTAPP_CTRL2_OUT2__##e)
+#define BFM_UARTAPP_CTRL2_OUT2_V(v)                 BM_UARTAPP_CTRL2_OUT2
+#define BP_UARTAPP_CTRL2_OUT1                       12
+#define BM_UARTAPP_CTRL2_OUT1                       0x1000
+#define BF_UARTAPP_CTRL2_OUT1(v)                    (((v) & 0x1) << 12)
+#define BFM_UARTAPP_CTRL2_OUT1(v)                   BM_UARTAPP_CTRL2_OUT1
+#define BF_UARTAPP_CTRL2_OUT1_V(e)                  BF_UARTAPP_CTRL2_OUT1(BV_UARTAPP_CTRL2_OUT1__##e)
+#define BFM_UARTAPP_CTRL2_OUT1_V(v)                 BM_UARTAPP_CTRL2_OUT1
+#define BP_UARTAPP_CTRL2_RTS                        11
+#define BM_UARTAPP_CTRL2_RTS                        0x800
+#define BF_UARTAPP_CTRL2_RTS(v)                     (((v) & 0x1) << 11)
+#define BFM_UARTAPP_CTRL2_RTS(v)                    BM_UARTAPP_CTRL2_RTS
+#define BF_UARTAPP_CTRL2_RTS_V(e)                   BF_UARTAPP_CTRL2_RTS(BV_UARTAPP_CTRL2_RTS__##e)
+#define BFM_UARTAPP_CTRL2_RTS_V(v)                  BM_UARTAPP_CTRL2_RTS
+#define BP_UARTAPP_CTRL2_DTR                        10
+#define BM_UARTAPP_CTRL2_DTR                        0x400
+#define BF_UARTAPP_CTRL2_DTR(v)                     (((v) & 0x1) << 10)
+#define BFM_UARTAPP_CTRL2_DTR(v)                    BM_UARTAPP_CTRL2_DTR
+#define BF_UARTAPP_CTRL2_DTR_V(e)                   BF_UARTAPP_CTRL2_DTR(BV_UARTAPP_CTRL2_DTR__##e)
+#define BFM_UARTAPP_CTRL2_DTR_V(v)                  BM_UARTAPP_CTRL2_DTR
+#define BP_UARTAPP_CTRL2_RXE                        9
+#define BM_UARTAPP_CTRL2_RXE                        0x200
+#define BF_UARTAPP_CTRL2_RXE(v)                     (((v) & 0x1) << 9)
+#define BFM_UARTAPP_CTRL2_RXE(v)                    BM_UARTAPP_CTRL2_RXE
+#define BF_UARTAPP_CTRL2_RXE_V(e)                   BF_UARTAPP_CTRL2_RXE(BV_UARTAPP_CTRL2_RXE__##e)
+#define BFM_UARTAPP_CTRL2_RXE_V(v)                  BM_UARTAPP_CTRL2_RXE
+#define BP_UARTAPP_CTRL2_TXE                        8
+#define BM_UARTAPP_CTRL2_TXE                        0x100
+#define BF_UARTAPP_CTRL2_TXE(v)                     (((v) & 0x1) << 8)
+#define BFM_UARTAPP_CTRL2_TXE(v)                    BM_UARTAPP_CTRL2_TXE
+#define BF_UARTAPP_CTRL2_TXE_V(e)                   BF_UARTAPP_CTRL2_TXE(BV_UARTAPP_CTRL2_TXE__##e)
+#define BFM_UARTAPP_CTRL2_TXE_V(v)                  BM_UARTAPP_CTRL2_TXE
+#define BP_UARTAPP_CTRL2_LBE                        7
+#define BM_UARTAPP_CTRL2_LBE                        0x80
+#define BF_UARTAPP_CTRL2_LBE(v)                     (((v) & 0x1) << 7)
+#define BFM_UARTAPP_CTRL2_LBE(v)                    BM_UARTAPP_CTRL2_LBE
+#define BF_UARTAPP_CTRL2_LBE_V(e)                   BF_UARTAPP_CTRL2_LBE(BV_UARTAPP_CTRL2_LBE__##e)
+#define BFM_UARTAPP_CTRL2_LBE_V(v)                  BM_UARTAPP_CTRL2_LBE
+#define BP_UARTAPP_CTRL2_USE_LCR2                   6
+#define BM_UARTAPP_CTRL2_USE_LCR2                   0x40
+#define BF_UARTAPP_CTRL2_USE_LCR2(v)                (((v) & 0x1) << 6)
+#define BFM_UARTAPP_CTRL2_USE_LCR2(v)               BM_UARTAPP_CTRL2_USE_LCR2
+#define BF_UARTAPP_CTRL2_USE_LCR2_V(e)              BF_UARTAPP_CTRL2_USE_LCR2(BV_UARTAPP_CTRL2_USE_LCR2__##e)
+#define BFM_UARTAPP_CTRL2_USE_LCR2_V(v)             BM_UARTAPP_CTRL2_USE_LCR2
+#define BP_UARTAPP_CTRL2_RSVD4                      3
+#define BM_UARTAPP_CTRL2_RSVD4                      0x38
+#define BF_UARTAPP_CTRL2_RSVD4(v)                   (((v) & 0x7) << 3)
+#define BFM_UARTAPP_CTRL2_RSVD4(v)                  BM_UARTAPP_CTRL2_RSVD4
+#define BF_UARTAPP_CTRL2_RSVD4_V(e)                 BF_UARTAPP_CTRL2_RSVD4(BV_UARTAPP_CTRL2_RSVD4__##e)
+#define BFM_UARTAPP_CTRL2_RSVD4_V(v)                BM_UARTAPP_CTRL2_RSVD4
+#define BP_UARTAPP_CTRL2_SIRLP                      2
+#define BM_UARTAPP_CTRL2_SIRLP                      0x4
+#define BF_UARTAPP_CTRL2_SIRLP(v)                   (((v) & 0x1) << 2)
+#define BFM_UARTAPP_CTRL2_SIRLP(v)                  BM_UARTAPP_CTRL2_SIRLP
+#define BF_UARTAPP_CTRL2_SIRLP_V(e)                 BF_UARTAPP_CTRL2_SIRLP(BV_UARTAPP_CTRL2_SIRLP__##e)
+#define BFM_UARTAPP_CTRL2_SIRLP_V(v)                BM_UARTAPP_CTRL2_SIRLP
+#define BP_UARTAPP_CTRL2_SIREN                      1
+#define BM_UARTAPP_CTRL2_SIREN                      0x2
+#define BF_UARTAPP_CTRL2_SIREN(v)                   (((v) & 0x1) << 1)
+#define BFM_UARTAPP_CTRL2_SIREN(v)                  BM_UARTAPP_CTRL2_SIREN
+#define BF_UARTAPP_CTRL2_SIREN_V(e)                 BF_UARTAPP_CTRL2_SIREN(BV_UARTAPP_CTRL2_SIREN__##e)
+#define BFM_UARTAPP_CTRL2_SIREN_V(v)                BM_UARTAPP_CTRL2_SIREN
+#define BP_UARTAPP_CTRL2_UARTEN                     0
+#define BM_UARTAPP_CTRL2_UARTEN                     0x1
+#define BF_UARTAPP_CTRL2_UARTEN(v)                  (((v) & 0x1) << 0)
+#define BFM_UARTAPP_CTRL2_UARTEN(v)                 BM_UARTAPP_CTRL2_UARTEN
+#define BF_UARTAPP_CTRL2_UARTEN_V(e)                BF_UARTAPP_CTRL2_UARTEN(BV_UARTAPP_CTRL2_UARTEN__##e)
+#define BFM_UARTAPP_CTRL2_UARTEN_V(v)               BM_UARTAPP_CTRL2_UARTEN
+
+#define HW_UARTAPP_LINECTRL(_n1)                HW(UARTAPP_LINECTRL(_n1))
+#define HWA_UARTAPP_LINECTRL(_n1)               (((_n1) == 1 ? 0x8006c000 : 0x8006e000) + 0x30)
+#define HWT_UARTAPP_LINECTRL(_n1)               HWIO_32_RW
+#define HWN_UARTAPP_LINECTRL(_n1)               UARTAPP_LINECTRL
+#define HWI_UARTAPP_LINECTRL(_n1)               (_n1)
+#define HW_UARTAPP_LINECTRL_SET(_n1)            HW(UARTAPP_LINECTRL_SET(_n1))
+#define HWA_UARTAPP_LINECTRL_SET(_n1)           (HWA_UARTAPP_LINECTRL(_n1) + 0x4)
+#define HWT_UARTAPP_LINECTRL_SET(_n1)           HWIO_32_WO
+#define HWN_UARTAPP_LINECTRL_SET(_n1)           UARTAPP_LINECTRL
+#define HWI_UARTAPP_LINECTRL_SET(_n1)           (_n1)
+#define HW_UARTAPP_LINECTRL_CLR(_n1)            HW(UARTAPP_LINECTRL_CLR(_n1))
+#define HWA_UARTAPP_LINECTRL_CLR(_n1)           (HWA_UARTAPP_LINECTRL(_n1) + 0x8)
+#define HWT_UARTAPP_LINECTRL_CLR(_n1)           HWIO_32_WO
+#define HWN_UARTAPP_LINECTRL_CLR(_n1)           UARTAPP_LINECTRL
+#define HWI_UARTAPP_LINECTRL_CLR(_n1)           (_n1)
+#define HW_UARTAPP_LINECTRL_TOG(_n1)            HW(UARTAPP_LINECTRL_TOG(_n1))
+#define HWA_UARTAPP_LINECTRL_TOG(_n1)           (HWA_UARTAPP_LINECTRL(_n1) + 0xc)
+#define HWT_UARTAPP_LINECTRL_TOG(_n1)           HWIO_32_WO
+#define HWN_UARTAPP_LINECTRL_TOG(_n1)           UARTAPP_LINECTRL
+#define HWI_UARTAPP_LINECTRL_TOG(_n1)           (_n1)
+#define BP_UARTAPP_LINECTRL_BAUD_DIVINT         16
+#define BM_UARTAPP_LINECTRL_BAUD_DIVINT         0xffff0000
+#define BF_UARTAPP_LINECTRL_BAUD_DIVINT(v)      (((v) & 0xffff) << 16)
+#define BFM_UARTAPP_LINECTRL_BAUD_DIVINT(v)     BM_UARTAPP_LINECTRL_BAUD_DIVINT
+#define BF_UARTAPP_LINECTRL_BAUD_DIVINT_V(e)    BF_UARTAPP_LINECTRL_BAUD_DIVINT(BV_UARTAPP_LINECTRL_BAUD_DIVINT__##e)
+#define BFM_UARTAPP_LINECTRL_BAUD_DIVINT_V(v)   BM_UARTAPP_LINECTRL_BAUD_DIVINT
+#define BP_UARTAPP_LINECTRL_RSVD                14
+#define BM_UARTAPP_LINECTRL_RSVD                0xc000
+#define BF_UARTAPP_LINECTRL_RSVD(v)             (((v) & 0x3) << 14)
+#define BFM_UARTAPP_LINECTRL_RSVD(v)            BM_UARTAPP_LINECTRL_RSVD
+#define BF_UARTAPP_LINECTRL_RSVD_V(e)           BF_UARTAPP_LINECTRL_RSVD(BV_UARTAPP_LINECTRL_RSVD__##e)
+#define BFM_UARTAPP_LINECTRL_RSVD_V(v)          BM_UARTAPP_LINECTRL_RSVD
+#define BP_UARTAPP_LINECTRL_BAUD_DIVFRAC        8
+#define BM_UARTAPP_LINECTRL_BAUD_DIVFRAC        0x3f00
+#define BF_UARTAPP_LINECTRL_BAUD_DIVFRAC(v)     (((v) & 0x3f) << 8)
+#define BFM_UARTAPP_LINECTRL_BAUD_DIVFRAC(v)    BM_UARTAPP_LINECTRL_BAUD_DIVFRAC
+#define BF_UARTAPP_LINECTRL_BAUD_DIVFRAC_V(e)   BF_UARTAPP_LINECTRL_BAUD_DIVFRAC(BV_UARTAPP_LINECTRL_BAUD_DIVFRAC__##e)
+#define BFM_UARTAPP_LINECTRL_BAUD_DIVFRAC_V(v)  BM_UARTAPP_LINECTRL_BAUD_DIVFRAC
+#define BP_UARTAPP_LINECTRL_SPS                 7
+#define BM_UARTAPP_LINECTRL_SPS                 0x80
+#define BF_UARTAPP_LINECTRL_SPS(v)              (((v) & 0x1) << 7)
+#define BFM_UARTAPP_LINECTRL_SPS(v)             BM_UARTAPP_LINECTRL_SPS
+#define BF_UARTAPP_LINECTRL_SPS_V(e)            BF_UARTAPP_LINECTRL_SPS(BV_UARTAPP_LINECTRL_SPS__##e)
+#define BFM_UARTAPP_LINECTRL_SPS_V(v)           BM_UARTAPP_LINECTRL_SPS
+#define BP_UARTAPP_LINECTRL_WLEN                5
+#define BM_UARTAPP_LINECTRL_WLEN                0x60
+#define BF_UARTAPP_LINECTRL_WLEN(v)             (((v) & 0x3) << 5)
+#define BFM_UARTAPP_LINECTRL_WLEN(v)            BM_UARTAPP_LINECTRL_WLEN
+#define BF_UARTAPP_LINECTRL_WLEN_V(e)           BF_UARTAPP_LINECTRL_WLEN(BV_UARTAPP_LINECTRL_WLEN__##e)
+#define BFM_UARTAPP_LINECTRL_WLEN_V(v)          BM_UARTAPP_LINECTRL_WLEN
+#define BP_UARTAPP_LINECTRL_FEN                 4
+#define BM_UARTAPP_LINECTRL_FEN                 0x10
+#define BF_UARTAPP_LINECTRL_FEN(v)              (((v) & 0x1) << 4)
+#define BFM_UARTAPP_LINECTRL_FEN(v)             BM_UARTAPP_LINECTRL_FEN
+#define BF_UARTAPP_LINECTRL_FEN_V(e)            BF_UARTAPP_LINECTRL_FEN(BV_UARTAPP_LINECTRL_FEN__##e)
+#define BFM_UARTAPP_LINECTRL_FEN_V(v)           BM_UARTAPP_LINECTRL_FEN
+#define BP_UARTAPP_LINECTRL_STP2                3
+#define BM_UARTAPP_LINECTRL_STP2                0x8
+#define BF_UARTAPP_LINECTRL_STP2(v)             (((v) & 0x1) << 3)
+#define BFM_UARTAPP_LINECTRL_STP2(v)            BM_UARTAPP_LINECTRL_STP2
+#define BF_UARTAPP_LINECTRL_STP2_V(e)           BF_UARTAPP_LINECTRL_STP2(BV_UARTAPP_LINECTRL_STP2__##e)
+#define BFM_UARTAPP_LINECTRL_STP2_V(v)          BM_UARTAPP_LINECTRL_STP2
+#define BP_UARTAPP_LINECTRL_EPS                 2
+#define BM_UARTAPP_LINECTRL_EPS                 0x4
+#define BF_UARTAPP_LINECTRL_EPS(v)              (((v) & 0x1) << 2)
+#define BFM_UARTAPP_LINECTRL_EPS(v)             BM_UARTAPP_LINECTRL_EPS
+#define BF_UARTAPP_LINECTRL_EPS_V(e)            BF_UARTAPP_LINECTRL_EPS(BV_UARTAPP_LINECTRL_EPS__##e)
+#define BFM_UARTAPP_LINECTRL_EPS_V(v)           BM_UARTAPP_LINECTRL_EPS
+#define BP_UARTAPP_LINECTRL_PEN                 1
+#define BM_UARTAPP_LINECTRL_PEN                 0x2
+#define BF_UARTAPP_LINECTRL_PEN(v)              (((v) & 0x1) << 1)
+#define BFM_UARTAPP_LINECTRL_PEN(v)             BM_UARTAPP_LINECTRL_PEN
+#define BF_UARTAPP_LINECTRL_PEN_V(e)            BF_UARTAPP_LINECTRL_PEN(BV_UARTAPP_LINECTRL_PEN__##e)
+#define BFM_UARTAPP_LINECTRL_PEN_V(v)           BM_UARTAPP_LINECTRL_PEN
+#define BP_UARTAPP_LINECTRL_BRK                 0
+#define BM_UARTAPP_LINECTRL_BRK                 0x1
+#define BF_UARTAPP_LINECTRL_BRK(v)              (((v) & 0x1) << 0)
+#define BFM_UARTAPP_LINECTRL_BRK(v)             BM_UARTAPP_LINECTRL_BRK
+#define BF_UARTAPP_LINECTRL_BRK_V(e)            BF_UARTAPP_LINECTRL_BRK(BV_UARTAPP_LINECTRL_BRK__##e)
+#define BFM_UARTAPP_LINECTRL_BRK_V(v)           BM_UARTAPP_LINECTRL_BRK
+
+#define HW_UARTAPP_LINECTRL2(_n1)               HW(UARTAPP_LINECTRL2(_n1))
+#define HWA_UARTAPP_LINECTRL2(_n1)              (((_n1) == 1 ? 0x8006c000 : 0x8006e000) + 0x40)
+#define HWT_UARTAPP_LINECTRL2(_n1)              HWIO_32_RW
+#define HWN_UARTAPP_LINECTRL2(_n1)              UARTAPP_LINECTRL2
+#define HWI_UARTAPP_LINECTRL2(_n1)              (_n1)
+#define HW_UARTAPP_LINECTRL2_SET(_n1)           HW(UARTAPP_LINECTRL2_SET(_n1))
+#define HWA_UARTAPP_LINECTRL2_SET(_n1)          (HWA_UARTAPP_LINECTRL2(_n1) + 0x4)
+#define HWT_UARTAPP_LINECTRL2_SET(_n1)          HWIO_32_WO
+#define HWN_UARTAPP_LINECTRL2_SET(_n1)          UARTAPP_LINECTRL2
+#define HWI_UARTAPP_LINECTRL2_SET(_n1)          (_n1)
+#define HW_UARTAPP_LINECTRL2_CLR(_n1)           HW(UARTAPP_LINECTRL2_CLR(_n1))
+#define HWA_UARTAPP_LINECTRL2_CLR(_n1)          (HWA_UARTAPP_LINECTRL2(_n1) + 0x8)
+#define HWT_UARTAPP_LINECTRL2_CLR(_n1)          HWIO_32_WO
+#define HWN_UARTAPP_LINECTRL2_CLR(_n1)          UARTAPP_LINECTRL2
+#define HWI_UARTAPP_LINECTRL2_CLR(_n1)          (_n1)
+#define HW_UARTAPP_LINECTRL2_TOG(_n1)           HW(UARTAPP_LINECTRL2_TOG(_n1))
+#define HWA_UARTAPP_LINECTRL2_TOG(_n1)          (HWA_UARTAPP_LINECTRL2(_n1) + 0xc)
+#define HWT_UARTAPP_LINECTRL2_TOG(_n1)          HWIO_32_WO
+#define HWN_UARTAPP_LINECTRL2_TOG(_n1)          UARTAPP_LINECTRL2
+#define HWI_UARTAPP_LINECTRL2_TOG(_n1)          (_n1)
+#define BP_UARTAPP_LINECTRL2_BAUD_DIVINT        16
+#define BM_UARTAPP_LINECTRL2_BAUD_DIVINT        0xffff0000
+#define BF_UARTAPP_LINECTRL2_BAUD_DIVINT(v)     (((v) & 0xffff) << 16)
+#define BFM_UARTAPP_LINECTRL2_BAUD_DIVINT(v)    BM_UARTAPP_LINECTRL2_BAUD_DIVINT
+#define BF_UARTAPP_LINECTRL2_BAUD_DIVINT_V(e)   BF_UARTAPP_LINECTRL2_BAUD_DIVINT(BV_UARTAPP_LINECTRL2_BAUD_DIVINT__##e)
+#define BFM_UARTAPP_LINECTRL2_BAUD_DIVINT_V(v)  BM_UARTAPP_LINECTRL2_BAUD_DIVINT
+#define BP_UARTAPP_LINECTRL2_RSVD               14
+#define BM_UARTAPP_LINECTRL2_RSVD               0xc000
+#define BF_UARTAPP_LINECTRL2_RSVD(v)            (((v) & 0x3) << 14)
+#define BFM_UARTAPP_LINECTRL2_RSVD(v)           BM_UARTAPP_LINECTRL2_RSVD
+#define BF_UARTAPP_LINECTRL2_RSVD_V(e)          BF_UARTAPP_LINECTRL2_RSVD(BV_UARTAPP_LINECTRL2_RSVD__##e)
+#define BFM_UARTAPP_LINECTRL2_RSVD_V(v)         BM_UARTAPP_LINECTRL2_RSVD
+#define BP_UARTAPP_LINECTRL2_BAUD_DIVFRAC       8
+#define BM_UARTAPP_LINECTRL2_BAUD_DIVFRAC       0x3f00
+#define BF_UARTAPP_LINECTRL2_BAUD_DIVFRAC(v)    (((v) & 0x3f) << 8)
+#define BFM_UARTAPP_LINECTRL2_BAUD_DIVFRAC(v)   BM_UARTAPP_LINECTRL2_BAUD_DIVFRAC
+#define BF_UARTAPP_LINECTRL2_BAUD_DIVFRAC_V(e)  BF_UARTAPP_LINECTRL2_BAUD_DIVFRAC(BV_UARTAPP_LINECTRL2_BAUD_DIVFRAC__##e)
+#define BFM_UARTAPP_LINECTRL2_BAUD_DIVFRAC_V(v) BM_UARTAPP_LINECTRL2_BAUD_DIVFRAC
+#define BP_UARTAPP_LINECTRL2_SPS                7
+#define BM_UARTAPP_LINECTRL2_SPS                0x80
+#define BF_UARTAPP_LINECTRL2_SPS(v)             (((v) & 0x1) << 7)
+#define BFM_UARTAPP_LINECTRL2_SPS(v)            BM_UARTAPP_LINECTRL2_SPS
+#define BF_UARTAPP_LINECTRL2_SPS_V(e)           BF_UARTAPP_LINECTRL2_SPS(BV_UARTAPP_LINECTRL2_SPS__##e)
+#define BFM_UARTAPP_LINECTRL2_SPS_V(v)          BM_UARTAPP_LINECTRL2_SPS
+#define BP_UARTAPP_LINECTRL2_WLEN               5
+#define BM_UARTAPP_LINECTRL2_WLEN               0x60
+#define BF_UARTAPP_LINECTRL2_WLEN(v)            (((v) & 0x3) << 5)
+#define BFM_UARTAPP_LINECTRL2_WLEN(v)           BM_UARTAPP_LINECTRL2_WLEN
+#define BF_UARTAPP_LINECTRL2_WLEN_V(e)          BF_UARTAPP_LINECTRL2_WLEN(BV_UARTAPP_LINECTRL2_WLEN__##e)
+#define BFM_UARTAPP_LINECTRL2_WLEN_V(v)         BM_UARTAPP_LINECTRL2_WLEN
+#define BP_UARTAPP_LINECTRL2_FEN                4
+#define BM_UARTAPP_LINECTRL2_FEN                0x10
+#define BF_UARTAPP_LINECTRL2_FEN(v)             (((v) & 0x1) << 4)
+#define BFM_UARTAPP_LINECTRL2_FEN(v)            BM_UARTAPP_LINECTRL2_FEN
+#define BF_UARTAPP_LINECTRL2_FEN_V(e)           BF_UARTAPP_LINECTRL2_FEN(BV_UARTAPP_LINECTRL2_FEN__##e)
+#define BFM_UARTAPP_LINECTRL2_FEN_V(v)          BM_UARTAPP_LINECTRL2_FEN
+#define BP_UARTAPP_LINECTRL2_STP2               3
+#define BM_UARTAPP_LINECTRL2_STP2               0x8
+#define BF_UARTAPP_LINECTRL2_STP2(v)            (((v) & 0x1) << 3)
+#define BFM_UARTAPP_LINECTRL2_STP2(v)           BM_UARTAPP_LINECTRL2_STP2
+#define BF_UARTAPP_LINECTRL2_STP2_V(e)          BF_UARTAPP_LINECTRL2_STP2(BV_UARTAPP_LINECTRL2_STP2__##e)
+#define BFM_UARTAPP_LINECTRL2_STP2_V(v)         BM_UARTAPP_LINECTRL2_STP2
+#define BP_UARTAPP_LINECTRL2_EPS                2
+#define BM_UARTAPP_LINECTRL2_EPS                0x4
+#define BF_UARTAPP_LINECTRL2_EPS(v)             (((v) & 0x1) << 2)
+#define BFM_UARTAPP_LINECTRL2_EPS(v)            BM_UARTAPP_LINECTRL2_EPS
+#define BF_UARTAPP_LINECTRL2_EPS_V(e)           BF_UARTAPP_LINECTRL2_EPS(BV_UARTAPP_LINECTRL2_EPS__##e)
+#define BFM_UARTAPP_LINECTRL2_EPS_V(v)          BM_UARTAPP_LINECTRL2_EPS
+#define BP_UARTAPP_LINECTRL2_PEN                1
+#define BM_UARTAPP_LINECTRL2_PEN                0x2
+#define BF_UARTAPP_LINECTRL2_PEN(v)             (((v) & 0x1) << 1)
+#define BFM_UARTAPP_LINECTRL2_PEN(v)            BM_UARTAPP_LINECTRL2_PEN
+#define BF_UARTAPP_LINECTRL2_PEN_V(e)           BF_UARTAPP_LINECTRL2_PEN(BV_UARTAPP_LINECTRL2_PEN__##e)
+#define BFM_UARTAPP_LINECTRL2_PEN_V(v)          BM_UARTAPP_LINECTRL2_PEN
+#define BP_UARTAPP_LINECTRL2_RSVD1              0
+#define BM_UARTAPP_LINECTRL2_RSVD1              0x1
+#define BF_UARTAPP_LINECTRL2_RSVD1(v)           (((v) & 0x1) << 0)
+#define BFM_UARTAPP_LINECTRL2_RSVD1(v)          BM_UARTAPP_LINECTRL2_RSVD1
+#define BF_UARTAPP_LINECTRL2_RSVD1_V(e)         BF_UARTAPP_LINECTRL2_RSVD1(BV_UARTAPP_LINECTRL2_RSVD1__##e)
+#define BFM_UARTAPP_LINECTRL2_RSVD1_V(v)        BM_UARTAPP_LINECTRL2_RSVD1
+
+#define HW_UARTAPP_INTR(_n1)            HW(UARTAPP_INTR(_n1))
+#define HWA_UARTAPP_INTR(_n1)           (((_n1) == 1 ? 0x8006c000 : 0x8006e000) + 0x50)
+#define HWT_UARTAPP_INTR(_n1)           HWIO_32_RW
+#define HWN_UARTAPP_INTR(_n1)           UARTAPP_INTR
+#define HWI_UARTAPP_INTR(_n1)           (_n1)
+#define HW_UARTAPP_INTR_SET(_n1)        HW(UARTAPP_INTR_SET(_n1))
+#define HWA_UARTAPP_INTR_SET(_n1)       (HWA_UARTAPP_INTR(_n1) + 0x4)
+#define HWT_UARTAPP_INTR_SET(_n1)       HWIO_32_WO
+#define HWN_UARTAPP_INTR_SET(_n1)       UARTAPP_INTR
+#define HWI_UARTAPP_INTR_SET(_n1)       (_n1)
+#define HW_UARTAPP_INTR_CLR(_n1)        HW(UARTAPP_INTR_CLR(_n1))
+#define HWA_UARTAPP_INTR_CLR(_n1)       (HWA_UARTAPP_INTR(_n1) + 0x8)
+#define HWT_UARTAPP_INTR_CLR(_n1)       HWIO_32_WO
+#define HWN_UARTAPP_INTR_CLR(_n1)       UARTAPP_INTR
+#define HWI_UARTAPP_INTR_CLR(_n1)       (_n1)
+#define HW_UARTAPP_INTR_TOG(_n1)        HW(UARTAPP_INTR_TOG(_n1))
+#define HWA_UARTAPP_INTR_TOG(_n1)       (HWA_UARTAPP_INTR(_n1) + 0xc)
+#define HWT_UARTAPP_INTR_TOG(_n1)       HWIO_32_WO
+#define HWN_UARTAPP_INTR_TOG(_n1)       UARTAPP_INTR
+#define HWI_UARTAPP_INTR_TOG(_n1)       (_n1)
+#define BP_UARTAPP_INTR_RSVD1           27
+#define BM_UARTAPP_INTR_RSVD1           0xf8000000
+#define BF_UARTAPP_INTR_RSVD1(v)        (((v) & 0x1f) << 27)
+#define BFM_UARTAPP_INTR_RSVD1(v)       BM_UARTAPP_INTR_RSVD1
+#define BF_UARTAPP_INTR_RSVD1_V(e)      BF_UARTAPP_INTR_RSVD1(BV_UARTAPP_INTR_RSVD1__##e)
+#define BFM_UARTAPP_INTR_RSVD1_V(v)     BM_UARTAPP_INTR_RSVD1
+#define BP_UARTAPP_INTR_OEIEN           26
+#define BM_UARTAPP_INTR_OEIEN           0x4000000
+#define BF_UARTAPP_INTR_OEIEN(v)        (((v) & 0x1) << 26)
+#define BFM_UARTAPP_INTR_OEIEN(v)       BM_UARTAPP_INTR_OEIEN
+#define BF_UARTAPP_INTR_OEIEN_V(e)      BF_UARTAPP_INTR_OEIEN(BV_UARTAPP_INTR_OEIEN__##e)
+#define BFM_UARTAPP_INTR_OEIEN_V(v)     BM_UARTAPP_INTR_OEIEN
+#define BP_UARTAPP_INTR_BEIEN           25
+#define BM_UARTAPP_INTR_BEIEN           0x2000000
+#define BF_UARTAPP_INTR_BEIEN(v)        (((v) & 0x1) << 25)
+#define BFM_UARTAPP_INTR_BEIEN(v)       BM_UARTAPP_INTR_BEIEN
+#define BF_UARTAPP_INTR_BEIEN_V(e)      BF_UARTAPP_INTR_BEIEN(BV_UARTAPP_INTR_BEIEN__##e)
+#define BFM_UARTAPP_INTR_BEIEN_V(v)     BM_UARTAPP_INTR_BEIEN
+#define BP_UARTAPP_INTR_PEIEN           24
+#define BM_UARTAPP_INTR_PEIEN           0x1000000
+#define BF_UARTAPP_INTR_PEIEN(v)        (((v) & 0x1) << 24)
+#define BFM_UARTAPP_INTR_PEIEN(v)       BM_UARTAPP_INTR_PEIEN
+#define BF_UARTAPP_INTR_PEIEN_V(e)      BF_UARTAPP_INTR_PEIEN(BV_UARTAPP_INTR_PEIEN__##e)
+#define BFM_UARTAPP_INTR_PEIEN_V(v)     BM_UARTAPP_INTR_PEIEN
+#define BP_UARTAPP_INTR_FEIEN           23
+#define BM_UARTAPP_INTR_FEIEN           0x800000
+#define BF_UARTAPP_INTR_FEIEN(v)        (((v) & 0x1) << 23)
+#define BFM_UARTAPP_INTR_FEIEN(v)       BM_UARTAPP_INTR_FEIEN
+#define BF_UARTAPP_INTR_FEIEN_V(e)      BF_UARTAPP_INTR_FEIEN(BV_UARTAPP_INTR_FEIEN__##e)
+#define BFM_UARTAPP_INTR_FEIEN_V(v)     BM_UARTAPP_INTR_FEIEN
+#define BP_UARTAPP_INTR_RTIEN           22
+#define BM_UARTAPP_INTR_RTIEN           0x400000
+#define BF_UARTAPP_INTR_RTIEN(v)        (((v) & 0x1) << 22)
+#define BFM_UARTAPP_INTR_RTIEN(v)       BM_UARTAPP_INTR_RTIEN
+#define BF_UARTAPP_INTR_RTIEN_V(e)      BF_UARTAPP_INTR_RTIEN(BV_UARTAPP_INTR_RTIEN__##e)
+#define BFM_UARTAPP_INTR_RTIEN_V(v)     BM_UARTAPP_INTR_RTIEN
+#define BP_UARTAPP_INTR_TXIEN           21
+#define BM_UARTAPP_INTR_TXIEN           0x200000
+#define BF_UARTAPP_INTR_TXIEN(v)        (((v) & 0x1) << 21)
+#define BFM_UARTAPP_INTR_TXIEN(v)       BM_UARTAPP_INTR_TXIEN
+#define BF_UARTAPP_INTR_TXIEN_V(e)      BF_UARTAPP_INTR_TXIEN(BV_UARTAPP_INTR_TXIEN__##e)
+#define BFM_UARTAPP_INTR_TXIEN_V(v)     BM_UARTAPP_INTR_TXIEN
+#define BP_UARTAPP_INTR_RXIEN           20
+#define BM_UARTAPP_INTR_RXIEN           0x100000
+#define BF_UARTAPP_INTR_RXIEN(v)        (((v) & 0x1) << 20)
+#define BFM_UARTAPP_INTR_RXIEN(v)       BM_UARTAPP_INTR_RXIEN
+#define BF_UARTAPP_INTR_RXIEN_V(e)      BF_UARTAPP_INTR_RXIEN(BV_UARTAPP_INTR_RXIEN__##e)
+#define BFM_UARTAPP_INTR_RXIEN_V(v)     BM_UARTAPP_INTR_RXIEN
+#define BP_UARTAPP_INTR_DSRMIEN         19
+#define BM_UARTAPP_INTR_DSRMIEN         0x80000
+#define BF_UARTAPP_INTR_DSRMIEN(v)      (((v) & 0x1) << 19)
+#define BFM_UARTAPP_INTR_DSRMIEN(v)     BM_UARTAPP_INTR_DSRMIEN
+#define BF_UARTAPP_INTR_DSRMIEN_V(e)    BF_UARTAPP_INTR_DSRMIEN(BV_UARTAPP_INTR_DSRMIEN__##e)
+#define BFM_UARTAPP_INTR_DSRMIEN_V(v)   BM_UARTAPP_INTR_DSRMIEN
+#define BP_UARTAPP_INTR_DCDMIEN         18
+#define BM_UARTAPP_INTR_DCDMIEN         0x40000
+#define BF_UARTAPP_INTR_DCDMIEN(v)      (((v) & 0x1) << 18)
+#define BFM_UARTAPP_INTR_DCDMIEN(v)     BM_UARTAPP_INTR_DCDMIEN
+#define BF_UARTAPP_INTR_DCDMIEN_V(e)    BF_UARTAPP_INTR_DCDMIEN(BV_UARTAPP_INTR_DCDMIEN__##e)
+#define BFM_UARTAPP_INTR_DCDMIEN_V(v)   BM_UARTAPP_INTR_DCDMIEN
+#define BP_UARTAPP_INTR_CTSMIEN         17
+#define BM_UARTAPP_INTR_CTSMIEN         0x20000
+#define BF_UARTAPP_INTR_CTSMIEN(v)      (((v) & 0x1) << 17)
+#define BFM_UARTAPP_INTR_CTSMIEN(v)     BM_UARTAPP_INTR_CTSMIEN
+#define BF_UARTAPP_INTR_CTSMIEN_V(e)    BF_UARTAPP_INTR_CTSMIEN(BV_UARTAPP_INTR_CTSMIEN__##e)
+#define BFM_UARTAPP_INTR_CTSMIEN_V(v)   BM_UARTAPP_INTR_CTSMIEN
+#define BP_UARTAPP_INTR_RIMIEN          16
+#define BM_UARTAPP_INTR_RIMIEN          0x10000
+#define BF_UARTAPP_INTR_RIMIEN(v)       (((v) & 0x1) << 16)
+#define BFM_UARTAPP_INTR_RIMIEN(v)      BM_UARTAPP_INTR_RIMIEN
+#define BF_UARTAPP_INTR_RIMIEN_V(e)     BF_UARTAPP_INTR_RIMIEN(BV_UARTAPP_INTR_RIMIEN__##e)
+#define BFM_UARTAPP_INTR_RIMIEN_V(v)    BM_UARTAPP_INTR_RIMIEN
+#define BP_UARTAPP_INTR_RSVD2           11
+#define BM_UARTAPP_INTR_RSVD2           0xf800
+#define BF_UARTAPP_INTR_RSVD2(v)        (((v) & 0x1f) << 11)
+#define BFM_UARTAPP_INTR_RSVD2(v)       BM_UARTAPP_INTR_RSVD2
+#define BF_UARTAPP_INTR_RSVD2_V(e)      BF_UARTAPP_INTR_RSVD2(BV_UARTAPP_INTR_RSVD2__##e)
+#define BFM_UARTAPP_INTR_RSVD2_V(v)     BM_UARTAPP_INTR_RSVD2
+#define BP_UARTAPP_INTR_OEIS            10
+#define BM_UARTAPP_INTR_OEIS            0x400
+#define BF_UARTAPP_INTR_OEIS(v)         (((v) & 0x1) << 10)
+#define BFM_UARTAPP_INTR_OEIS(v)        BM_UARTAPP_INTR_OEIS
+#define BF_UARTAPP_INTR_OEIS_V(e)       BF_UARTAPP_INTR_OEIS(BV_UARTAPP_INTR_OEIS__##e)
+#define BFM_UARTAPP_INTR_OEIS_V(v)      BM_UARTAPP_INTR_OEIS
+#define BP_UARTAPP_INTR_BEIS            9
+#define BM_UARTAPP_INTR_BEIS            0x200
+#define BF_UARTAPP_INTR_BEIS(v)         (((v) & 0x1) << 9)
+#define BFM_UARTAPP_INTR_BEIS(v)        BM_UARTAPP_INTR_BEIS
+#define BF_UARTAPP_INTR_BEIS_V(e)       BF_UARTAPP_INTR_BEIS(BV_UARTAPP_INTR_BEIS__##e)
+#define BFM_UARTAPP_INTR_BEIS_V(v)      BM_UARTAPP_INTR_BEIS
+#define BP_UARTAPP_INTR_PEIS            8
+#define BM_UARTAPP_INTR_PEIS            0x100
+#define BF_UARTAPP_INTR_PEIS(v)         (((v) & 0x1) << 8)
+#define BFM_UARTAPP_INTR_PEIS(v)        BM_UARTAPP_INTR_PEIS
+#define BF_UARTAPP_INTR_PEIS_V(e)       BF_UARTAPP_INTR_PEIS(BV_UARTAPP_INTR_PEIS__##e)
+#define BFM_UARTAPP_INTR_PEIS_V(v)      BM_UARTAPP_INTR_PEIS
+#define BP_UARTAPP_INTR_FEIS            7
+#define BM_UARTAPP_INTR_FEIS            0x80
+#define BF_UARTAPP_INTR_FEIS(v)         (((v) & 0x1) << 7)
+#define BFM_UARTAPP_INTR_FEIS(v)        BM_UARTAPP_INTR_FEIS
+#define BF_UARTAPP_INTR_FEIS_V(e)       BF_UARTAPP_INTR_FEIS(BV_UARTAPP_INTR_FEIS__##e)
+#define BFM_UARTAPP_INTR_FEIS_V(v)      BM_UARTAPP_INTR_FEIS
+#define BP_UARTAPP_INTR_RTIS            6
+#define BM_UARTAPP_INTR_RTIS            0x40
+#define BF_UARTAPP_INTR_RTIS(v)         (((v) & 0x1) << 6)
+#define BFM_UARTAPP_INTR_RTIS(v)        BM_UARTAPP_INTR_RTIS
+#define BF_UARTAPP_INTR_RTIS_V(e)       BF_UARTAPP_INTR_RTIS(BV_UARTAPP_INTR_RTIS__##e)
+#define BFM_UARTAPP_INTR_RTIS_V(v)      BM_UARTAPP_INTR_RTIS
+#define BP_UARTAPP_INTR_TXIS            5
+#define BM_UARTAPP_INTR_TXIS            0x20
+#define BF_UARTAPP_INTR_TXIS(v)         (((v) & 0x1) << 5)
+#define BFM_UARTAPP_INTR_TXIS(v)        BM_UARTAPP_INTR_TXIS
+#define BF_UARTAPP_INTR_TXIS_V(e)       BF_UARTAPP_INTR_TXIS(BV_UARTAPP_INTR_TXIS__##e)
+#define BFM_UARTAPP_INTR_TXIS_V(v)      BM_UARTAPP_INTR_TXIS
+#define BP_UARTAPP_INTR_RXIS            4
+#define BM_UARTAPP_INTR_RXIS            0x10
+#define BF_UARTAPP_INTR_RXIS(v)         (((v) & 0x1) << 4)
+#define BFM_UARTAPP_INTR_RXIS(v)        BM_UARTAPP_INTR_RXIS
+#define BF_UARTAPP_INTR_RXIS_V(e)       BF_UARTAPP_INTR_RXIS(BV_UARTAPP_INTR_RXIS__##e)
+#define BFM_UARTAPP_INTR_RXIS_V(v)      BM_UARTAPP_INTR_RXIS
+#define BP_UARTAPP_INTR_DSRMIS          3
+#define BM_UARTAPP_INTR_DSRMIS          0x8
+#define BF_UARTAPP_INTR_DSRMIS(v)       (((v) & 0x1) << 3)
+#define BFM_UARTAPP_INTR_DSRMIS(v)      BM_UARTAPP_INTR_DSRMIS
+#define BF_UARTAPP_INTR_DSRMIS_V(e)     BF_UARTAPP_INTR_DSRMIS(BV_UARTAPP_INTR_DSRMIS__##e)
+#define BFM_UARTAPP_INTR_DSRMIS_V(v)    BM_UARTAPP_INTR_DSRMIS
+#define BP_UARTAPP_INTR_DCDMIS          2
+#define BM_UARTAPP_INTR_DCDMIS          0x4
+#define BF_UARTAPP_INTR_DCDMIS(v)       (((v) & 0x1) << 2)
+#define BFM_UARTAPP_INTR_DCDMIS(v)      BM_UARTAPP_INTR_DCDMIS
+#define BF_UARTAPP_INTR_DCDMIS_V(e)     BF_UARTAPP_INTR_DCDMIS(BV_UARTAPP_INTR_DCDMIS__##e)
+#define BFM_UARTAPP_INTR_DCDMIS_V(v)    BM_UARTAPP_INTR_DCDMIS
+#define BP_UARTAPP_INTR_CTSMIS          1
+#define BM_UARTAPP_INTR_CTSMIS          0x2
+#define BF_UARTAPP_INTR_CTSMIS(v)       (((v) & 0x1) << 1)
+#define BFM_UARTAPP_INTR_CTSMIS(v)      BM_UARTAPP_INTR_CTSMIS
+#define BF_UARTAPP_INTR_CTSMIS_V(e)     BF_UARTAPP_INTR_CTSMIS(BV_UARTAPP_INTR_CTSMIS__##e)
+#define BFM_UARTAPP_INTR_CTSMIS_V(v)    BM_UARTAPP_INTR_CTSMIS
+#define BP_UARTAPP_INTR_RIMIS           0
+#define BM_UARTAPP_INTR_RIMIS           0x1
+#define BF_UARTAPP_INTR_RIMIS(v)        (((v) & 0x1) << 0)
+#define BFM_UARTAPP_INTR_RIMIS(v)       BM_UARTAPP_INTR_RIMIS
+#define BF_UARTAPP_INTR_RIMIS_V(e)      BF_UARTAPP_INTR_RIMIS(BV_UARTAPP_INTR_RIMIS__##e)
+#define BFM_UARTAPP_INTR_RIMIS_V(v)     BM_UARTAPP_INTR_RIMIS
+
+#define HW_UARTAPP_DATA(_n1)        HW(UARTAPP_DATA(_n1))
+#define HWA_UARTAPP_DATA(_n1)       (((_n1) == 1 ? 0x8006c000 : 0x8006e000) + 0x60)
+#define HWT_UARTAPP_DATA(_n1)       HWIO_32_RW
+#define HWN_UARTAPP_DATA(_n1)       UARTAPP_DATA
+#define HWI_UARTAPP_DATA(_n1)       (_n1)
+#define BP_UARTAPP_DATA_DATA        0
+#define BM_UARTAPP_DATA_DATA        0xffffffff
+#define BF_UARTAPP_DATA_DATA(v)     (((v) & 0xffffffff) << 0)
+#define BFM_UARTAPP_DATA_DATA(v)    BM_UARTAPP_DATA_DATA
+#define BF_UARTAPP_DATA_DATA_V(e)   BF_UARTAPP_DATA_DATA(BV_UARTAPP_DATA_DATA__##e)
+#define BFM_UARTAPP_DATA_DATA_V(v)  BM_UARTAPP_DATA_DATA
+
+#define HW_UARTAPP_STAT(_n1)                    HW(UARTAPP_STAT(_n1))
+#define HWA_UARTAPP_STAT(_n1)                   (((_n1) == 1 ? 0x8006c000 : 0x8006e000) + 0x70)
+#define HWT_UARTAPP_STAT(_n1)                   HWIO_32_RW
+#define HWN_UARTAPP_STAT(_n1)                   UARTAPP_STAT
+#define HWI_UARTAPP_STAT(_n1)                   (_n1)
+#define BP_UARTAPP_STAT_PRESENT                 31
+#define BM_UARTAPP_STAT_PRESENT                 0x80000000
+#define BV_UARTAPP_STAT_PRESENT__UNAVAILABLE    0x0
+#define BV_UARTAPP_STAT_PRESENT__AVAILABLE      0x1
+#define BF_UARTAPP_STAT_PRESENT(v)              (((v) & 0x1) << 31)
+#define BFM_UARTAPP_STAT_PRESENT(v)             BM_UARTAPP_STAT_PRESENT
+#define BF_UARTAPP_STAT_PRESENT_V(e)            BF_UARTAPP_STAT_PRESENT(BV_UARTAPP_STAT_PRESENT__##e)
+#define BFM_UARTAPP_STAT_PRESENT_V(v)           BM_UARTAPP_STAT_PRESENT
+#define BP_UARTAPP_STAT_HISPEED                 30
+#define BM_UARTAPP_STAT_HISPEED                 0x40000000
+#define BV_UARTAPP_STAT_HISPEED__UNAVAILABLE    0x0
+#define BV_UARTAPP_STAT_HISPEED__AVAILABLE      0x1
+#define BF_UARTAPP_STAT_HISPEED(v)              (((v) & 0x1) << 30)
+#define BFM_UARTAPP_STAT_HISPEED(v)             BM_UARTAPP_STAT_HISPEED
+#define BF_UARTAPP_STAT_HISPEED_V(e)            BF_UARTAPP_STAT_HISPEED(BV_UARTAPP_STAT_HISPEED__##e)
+#define BFM_UARTAPP_STAT_HISPEED_V(v)           BM_UARTAPP_STAT_HISPEED
+#define BP_UARTAPP_STAT_BUSY                    29
+#define BM_UARTAPP_STAT_BUSY                    0x20000000
+#define BF_UARTAPP_STAT_BUSY(v)                 (((v) & 0x1) << 29)
+#define BFM_UARTAPP_STAT_BUSY(v)                BM_UARTAPP_STAT_BUSY
+#define BF_UARTAPP_STAT_BUSY_V(e)               BF_UARTAPP_STAT_BUSY(BV_UARTAPP_STAT_BUSY__##e)
+#define BFM_UARTAPP_STAT_BUSY_V(v)              BM_UARTAPP_STAT_BUSY
+#define BP_UARTAPP_STAT_CTS                     28
+#define BM_UARTAPP_STAT_CTS                     0x10000000
+#define BF_UARTAPP_STAT_CTS(v)                  (((v) & 0x1) << 28)
+#define BFM_UARTAPP_STAT_CTS(v)                 BM_UARTAPP_STAT_CTS
+#define BF_UARTAPP_STAT_CTS_V(e)                BF_UARTAPP_STAT_CTS(BV_UARTAPP_STAT_CTS__##e)
+#define BFM_UARTAPP_STAT_CTS_V(v)               BM_UARTAPP_STAT_CTS
+#define BP_UARTAPP_STAT_TXFE                    27
+#define BM_UARTAPP_STAT_TXFE                    0x8000000
+#define BF_UARTAPP_STAT_TXFE(v)                 (((v) & 0x1) << 27)
+#define BFM_UARTAPP_STAT_TXFE(v)                BM_UARTAPP_STAT_TXFE
+#define BF_UARTAPP_STAT_TXFE_V(e)               BF_UARTAPP_STAT_TXFE(BV_UARTAPP_STAT_TXFE__##e)
+#define BFM_UARTAPP_STAT_TXFE_V(v)              BM_UARTAPP_STAT_TXFE
+#define BP_UARTAPP_STAT_RXFF                    26
+#define BM_UARTAPP_STAT_RXFF                    0x4000000
+#define BF_UARTAPP_STAT_RXFF(v)                 (((v) & 0x1) << 26)
+#define BFM_UARTAPP_STAT_RXFF(v)                BM_UARTAPP_STAT_RXFF
+#define BF_UARTAPP_STAT_RXFF_V(e)               BF_UARTAPP_STAT_RXFF(BV_UARTAPP_STAT_RXFF__##e)
+#define BFM_UARTAPP_STAT_RXFF_V(v)              BM_UARTAPP_STAT_RXFF
+#define BP_UARTAPP_STAT_TXFF                    25
+#define BM_UARTAPP_STAT_TXFF                    0x2000000
+#define BF_UARTAPP_STAT_TXFF(v)                 (((v) & 0x1) << 25)
+#define BFM_UARTAPP_STAT_TXFF(v)                BM_UARTAPP_STAT_TXFF
+#define BF_UARTAPP_STAT_TXFF_V(e)               BF_UARTAPP_STAT_TXFF(BV_UARTAPP_STAT_TXFF__##e)
+#define BFM_UARTAPP_STAT_TXFF_V(v)              BM_UARTAPP_STAT_TXFF
+#define BP_UARTAPP_STAT_RXFE                    24
+#define BM_UARTAPP_STAT_RXFE                    0x1000000
+#define BF_UARTAPP_STAT_RXFE(v)                 (((v) & 0x1) << 24)
+#define BFM_UARTAPP_STAT_RXFE(v)                BM_UARTAPP_STAT_RXFE
+#define BF_UARTAPP_STAT_RXFE_V(e)               BF_UARTAPP_STAT_RXFE(BV_UARTAPP_STAT_RXFE__##e)
+#define BFM_UARTAPP_STAT_RXFE_V(v)              BM_UARTAPP_STAT_RXFE
+#define BP_UARTAPP_STAT_RXBYTE_INVALID          20
+#define BM_UARTAPP_STAT_RXBYTE_INVALID          0xf00000
+#define BF_UARTAPP_STAT_RXBYTE_INVALID(v)       (((v) & 0xf) << 20)
+#define BFM_UARTAPP_STAT_RXBYTE_INVALID(v)      BM_UARTAPP_STAT_RXBYTE_INVALID
+#define BF_UARTAPP_STAT_RXBYTE_INVALID_V(e)     BF_UARTAPP_STAT_RXBYTE_INVALID(BV_UARTAPP_STAT_RXBYTE_INVALID__##e)
+#define BFM_UARTAPP_STAT_RXBYTE_INVALID_V(v)    BM_UARTAPP_STAT_RXBYTE_INVALID
+#define BP_UARTAPP_STAT_OERR                    19
+#define BM_UARTAPP_STAT_OERR                    0x80000
+#define BF_UARTAPP_STAT_OERR(v)                 (((v) & 0x1) << 19)
+#define BFM_UARTAPP_STAT_OERR(v)                BM_UARTAPP_STAT_OERR
+#define BF_UARTAPP_STAT_OERR_V(e)               BF_UARTAPP_STAT_OERR(BV_UARTAPP_STAT_OERR__##e)
+#define BFM_UARTAPP_STAT_OERR_V(v)              BM_UARTAPP_STAT_OERR
+#define BP_UARTAPP_STAT_BERR                    18
+#define BM_UARTAPP_STAT_BERR                    0x40000
+#define BF_UARTAPP_STAT_BERR(v)                 (((v) & 0x1) << 18)
+#define BFM_UARTAPP_STAT_BERR(v)                BM_UARTAPP_STAT_BERR
+#define BF_UARTAPP_STAT_BERR_V(e)               BF_UARTAPP_STAT_BERR(BV_UARTAPP_STAT_BERR__##e)
+#define BFM_UARTAPP_STAT_BERR_V(v)              BM_UARTAPP_STAT_BERR
+#define BP_UARTAPP_STAT_PERR                    17
+#define BM_UARTAPP_STAT_PERR                    0x20000
+#define BF_UARTAPP_STAT_PERR(v)                 (((v) & 0x1) << 17)
+#define BFM_UARTAPP_STAT_PERR(v)                BM_UARTAPP_STAT_PERR
+#define BF_UARTAPP_STAT_PERR_V(e)               BF_UARTAPP_STAT_PERR(BV_UARTAPP_STAT_PERR__##e)
+#define BFM_UARTAPP_STAT_PERR_V(v)              BM_UARTAPP_STAT_PERR
+#define BP_UARTAPP_STAT_FERR                    16
+#define BM_UARTAPP_STAT_FERR                    0x10000
+#define BF_UARTAPP_STAT_FERR(v)                 (((v) & 0x1) << 16)
+#define BFM_UARTAPP_STAT_FERR(v)                BM_UARTAPP_STAT_FERR
+#define BF_UARTAPP_STAT_FERR_V(e)               BF_UARTAPP_STAT_FERR(BV_UARTAPP_STAT_FERR__##e)
+#define BFM_UARTAPP_STAT_FERR_V(v)              BM_UARTAPP_STAT_FERR
+#define BP_UARTAPP_STAT_RXCOUNT                 0
+#define BM_UARTAPP_STAT_RXCOUNT                 0xffff
+#define BF_UARTAPP_STAT_RXCOUNT(v)              (((v) & 0xffff) << 0)
+#define BFM_UARTAPP_STAT_RXCOUNT(v)             BM_UARTAPP_STAT_RXCOUNT
+#define BF_UARTAPP_STAT_RXCOUNT_V(e)            BF_UARTAPP_STAT_RXCOUNT(BV_UARTAPP_STAT_RXCOUNT__##e)
+#define BFM_UARTAPP_STAT_RXCOUNT_V(v)           BM_UARTAPP_STAT_RXCOUNT
+
+#define HW_UARTAPP_DEBUG(_n1)               HW(UARTAPP_DEBUG(_n1))
+#define HWA_UARTAPP_DEBUG(_n1)              (((_n1) == 1 ? 0x8006c000 : 0x8006e000) + 0x80)
+#define HWT_UARTAPP_DEBUG(_n1)              HWIO_32_RW
+#define HWN_UARTAPP_DEBUG(_n1)              UARTAPP_DEBUG
+#define HWI_UARTAPP_DEBUG(_n1)              (_n1)
+#define BP_UARTAPP_DEBUG_RXIBAUD_DIV        16
+#define BM_UARTAPP_DEBUG_RXIBAUD_DIV        0xffff0000
+#define BF_UARTAPP_DEBUG_RXIBAUD_DIV(v)     (((v) & 0xffff) << 16)
+#define BFM_UARTAPP_DEBUG_RXIBAUD_DIV(v)    BM_UARTAPP_DEBUG_RXIBAUD_DIV
+#define BF_UARTAPP_DEBUG_RXIBAUD_DIV_V(e)   BF_UARTAPP_DEBUG_RXIBAUD_DIV(BV_UARTAPP_DEBUG_RXIBAUD_DIV__##e)
+#define BFM_UARTAPP_DEBUG_RXIBAUD_DIV_V(v)  BM_UARTAPP_DEBUG_RXIBAUD_DIV
+#define BP_UARTAPP_DEBUG_RXFBAUD_DIV        10
+#define BM_UARTAPP_DEBUG_RXFBAUD_DIV        0xfc00
+#define BF_UARTAPP_DEBUG_RXFBAUD_DIV(v)     (((v) & 0x3f) << 10)
+#define BFM_UARTAPP_DEBUG_RXFBAUD_DIV(v)    BM_UARTAPP_DEBUG_RXFBAUD_DIV
+#define BF_UARTAPP_DEBUG_RXFBAUD_DIV_V(e)   BF_UARTAPP_DEBUG_RXFBAUD_DIV(BV_UARTAPP_DEBUG_RXFBAUD_DIV__##e)
+#define BFM_UARTAPP_DEBUG_RXFBAUD_DIV_V(v)  BM_UARTAPP_DEBUG_RXFBAUD_DIV
+#define BP_UARTAPP_DEBUG_RSVD1              6
+#define BM_UARTAPP_DEBUG_RSVD1              0x3c0
+#define BF_UARTAPP_DEBUG_RSVD1(v)           (((v) & 0xf) << 6)
+#define BFM_UARTAPP_DEBUG_RSVD1(v)          BM_UARTAPP_DEBUG_RSVD1
+#define BF_UARTAPP_DEBUG_RSVD1_V(e)         BF_UARTAPP_DEBUG_RSVD1(BV_UARTAPP_DEBUG_RSVD1__##e)
+#define BFM_UARTAPP_DEBUG_RSVD1_V(v)        BM_UARTAPP_DEBUG_RSVD1
+#define BP_UARTAPP_DEBUG_TXDMARUN           5
+#define BM_UARTAPP_DEBUG_TXDMARUN           0x20
+#define BF_UARTAPP_DEBUG_TXDMARUN(v)        (((v) & 0x1) << 5)
+#define BFM_UARTAPP_DEBUG_TXDMARUN(v)       BM_UARTAPP_DEBUG_TXDMARUN
+#define BF_UARTAPP_DEBUG_TXDMARUN_V(e)      BF_UARTAPP_DEBUG_TXDMARUN(BV_UARTAPP_DEBUG_TXDMARUN__##e)
+#define BFM_UARTAPP_DEBUG_TXDMARUN_V(v)     BM_UARTAPP_DEBUG_TXDMARUN
+#define BP_UARTAPP_DEBUG_RXDMARUN           4
+#define BM_UARTAPP_DEBUG_RXDMARUN           0x10
+#define BF_UARTAPP_DEBUG_RXDMARUN(v)        (((v) & 0x1) << 4)
+#define BFM_UARTAPP_DEBUG_RXDMARUN(v)       BM_UARTAPP_DEBUG_RXDMARUN
+#define BF_UARTAPP_DEBUG_RXDMARUN_V(e)      BF_UARTAPP_DEBUG_RXDMARUN(BV_UARTAPP_DEBUG_RXDMARUN__##e)
+#define BFM_UARTAPP_DEBUG_RXDMARUN_V(v)     BM_UARTAPP_DEBUG_RXDMARUN
+#define BP_UARTAPP_DEBUG_TXCMDEND           3
+#define BM_UARTAPP_DEBUG_TXCMDEND           0x8
+#define BF_UARTAPP_DEBUG_TXCMDEND(v)        (((v) & 0x1) << 3)
+#define BFM_UARTAPP_DEBUG_TXCMDEND(v)       BM_UARTAPP_DEBUG_TXCMDEND
+#define BF_UARTAPP_DEBUG_TXCMDEND_V(e)      BF_UARTAPP_DEBUG_TXCMDEND(BV_UARTAPP_DEBUG_TXCMDEND__##e)
+#define BFM_UARTAPP_DEBUG_TXCMDEND_V(v)     BM_UARTAPP_DEBUG_TXCMDEND
+#define BP_UARTAPP_DEBUG_RXCMDEND           2
+#define BM_UARTAPP_DEBUG_RXCMDEND           0x4
+#define BF_UARTAPP_DEBUG_RXCMDEND(v)        (((v) & 0x1) << 2)
+#define BFM_UARTAPP_DEBUG_RXCMDEND(v)       BM_UARTAPP_DEBUG_RXCMDEND
+#define BF_UARTAPP_DEBUG_RXCMDEND_V(e)      BF_UARTAPP_DEBUG_RXCMDEND(BV_UARTAPP_DEBUG_RXCMDEND__##e)
+#define BFM_UARTAPP_DEBUG_RXCMDEND_V(v)     BM_UARTAPP_DEBUG_RXCMDEND
+#define BP_UARTAPP_DEBUG_TXDMARQ            1
+#define BM_UARTAPP_DEBUG_TXDMARQ            0x2
+#define BF_UARTAPP_DEBUG_TXDMARQ(v)         (((v) & 0x1) << 1)
+#define BFM_UARTAPP_DEBUG_TXDMARQ(v)        BM_UARTAPP_DEBUG_TXDMARQ
+#define BF_UARTAPP_DEBUG_TXDMARQ_V(e)       BF_UARTAPP_DEBUG_TXDMARQ(BV_UARTAPP_DEBUG_TXDMARQ__##e)
+#define BFM_UARTAPP_DEBUG_TXDMARQ_V(v)      BM_UARTAPP_DEBUG_TXDMARQ
+#define BP_UARTAPP_DEBUG_RXDMARQ            0
+#define BM_UARTAPP_DEBUG_RXDMARQ            0x1
+#define BF_UARTAPP_DEBUG_RXDMARQ(v)         (((v) & 0x1) << 0)
+#define BFM_UARTAPP_DEBUG_RXDMARQ(v)        BM_UARTAPP_DEBUG_RXDMARQ
+#define BF_UARTAPP_DEBUG_RXDMARQ_V(e)       BF_UARTAPP_DEBUG_RXDMARQ(BV_UARTAPP_DEBUG_RXDMARQ__##e)
+#define BFM_UARTAPP_DEBUG_RXDMARQ_V(v)      BM_UARTAPP_DEBUG_RXDMARQ
+
+#define HW_UARTAPP_VERSION(_n1)         HW(UARTAPP_VERSION(_n1))
+#define HWA_UARTAPP_VERSION(_n1)        (((_n1) == 1 ? 0x8006c000 : 0x8006e000) + 0x90)
+#define HWT_UARTAPP_VERSION(_n1)        HWIO_32_RW
+#define HWN_UARTAPP_VERSION(_n1)        UARTAPP_VERSION
+#define HWI_UARTAPP_VERSION(_n1)        (_n1)
+#define BP_UARTAPP_VERSION_MAJOR        24
+#define BM_UARTAPP_VERSION_MAJOR        0xff000000
+#define BF_UARTAPP_VERSION_MAJOR(v)     (((v) & 0xff) << 24)
+#define BFM_UARTAPP_VERSION_MAJOR(v)    BM_UARTAPP_VERSION_MAJOR
+#define BF_UARTAPP_VERSION_MAJOR_V(e)   BF_UARTAPP_VERSION_MAJOR(BV_UARTAPP_VERSION_MAJOR__##e)
+#define BFM_UARTAPP_VERSION_MAJOR_V(v)  BM_UARTAPP_VERSION_MAJOR
+#define BP_UARTAPP_VERSION_MINOR        16
+#define BM_UARTAPP_VERSION_MINOR        0xff0000
+#define BF_UARTAPP_VERSION_MINOR(v)     (((v) & 0xff) << 16)
+#define BFM_UARTAPP_VERSION_MINOR(v)    BM_UARTAPP_VERSION_MINOR
+#define BF_UARTAPP_VERSION_MINOR_V(e)   BF_UARTAPP_VERSION_MINOR(BV_UARTAPP_VERSION_MINOR__##e)
+#define BFM_UARTAPP_VERSION_MINOR_V(v)  BM_UARTAPP_VERSION_MINOR
+#define BP_UARTAPP_VERSION_STEP         0
+#define BM_UARTAPP_VERSION_STEP         0xffff
+#define BF_UARTAPP_VERSION_STEP(v)      (((v) & 0xffff) << 0)
+#define BFM_UARTAPP_VERSION_STEP(v)     BM_UARTAPP_VERSION_STEP
+#define BF_UARTAPP_VERSION_STEP_V(e)    BF_UARTAPP_VERSION_STEP(BV_UARTAPP_VERSION_STEP__##e)
+#define BFM_UARTAPP_VERSION_STEP_V(v)   BM_UARTAPP_VERSION_STEP
+
+#define HW_UARTAPP_AUTOBAUD(_n1)                        HW(UARTAPP_AUTOBAUD(_n1))
+#define HWA_UARTAPP_AUTOBAUD(_n1)                       (((_n1) == 1 ? 0x8006c000 : 0x8006e000) + 0xa0)
+#define HWT_UARTAPP_AUTOBAUD(_n1)                       HWIO_32_RW
+#define HWN_UARTAPP_AUTOBAUD(_n1)                       UARTAPP_AUTOBAUD
+#define HWI_UARTAPP_AUTOBAUD(_n1)                       (_n1)
+#define BP_UARTAPP_AUTOBAUD_REFCHAR1                    24
+#define BM_UARTAPP_AUTOBAUD_REFCHAR1                    0xff000000
+#define BF_UARTAPP_AUTOBAUD_REFCHAR1(v)                 (((v) & 0xff) << 24)
+#define BFM_UARTAPP_AUTOBAUD_REFCHAR1(v)                BM_UARTAPP_AUTOBAUD_REFCHAR1
+#define BF_UARTAPP_AUTOBAUD_REFCHAR1_V(e)               BF_UARTAPP_AUTOBAUD_REFCHAR1(BV_UARTAPP_AUTOBAUD_REFCHAR1__##e)
+#define BFM_UARTAPP_AUTOBAUD_REFCHAR1_V(v)              BM_UARTAPP_AUTOBAUD_REFCHAR1
+#define BP_UARTAPP_AUTOBAUD_REFCHAR0                    16
+#define BM_UARTAPP_AUTOBAUD_REFCHAR0                    0xff0000
+#define BF_UARTAPP_AUTOBAUD_REFCHAR0(v)                 (((v) & 0xff) << 16)
+#define BFM_UARTAPP_AUTOBAUD_REFCHAR0(v)                BM_UARTAPP_AUTOBAUD_REFCHAR0
+#define BF_UARTAPP_AUTOBAUD_REFCHAR0_V(e)               BF_UARTAPP_AUTOBAUD_REFCHAR0(BV_UARTAPP_AUTOBAUD_REFCHAR0__##e)
+#define BFM_UARTAPP_AUTOBAUD_REFCHAR0_V(v)              BM_UARTAPP_AUTOBAUD_REFCHAR0
+#define BP_UARTAPP_AUTOBAUD_RSVD1                       5
+#define BM_UARTAPP_AUTOBAUD_RSVD1                       0xffe0
+#define BF_UARTAPP_AUTOBAUD_RSVD1(v)                    (((v) & 0x7ff) << 5)
+#define BFM_UARTAPP_AUTOBAUD_RSVD1(v)                   BM_UARTAPP_AUTOBAUD_RSVD1
+#define BF_UARTAPP_AUTOBAUD_RSVD1_V(e)                  BF_UARTAPP_AUTOBAUD_RSVD1(BV_UARTAPP_AUTOBAUD_RSVD1__##e)
+#define BFM_UARTAPP_AUTOBAUD_RSVD1_V(v)                 BM_UARTAPP_AUTOBAUD_RSVD1
+#define BP_UARTAPP_AUTOBAUD_UPDATE_TX                   4
+#define BM_UARTAPP_AUTOBAUD_UPDATE_TX                   0x10
+#define BF_UARTAPP_AUTOBAUD_UPDATE_TX(v)                (((v) & 0x1) << 4)
+#define BFM_UARTAPP_AUTOBAUD_UPDATE_TX(v)               BM_UARTAPP_AUTOBAUD_UPDATE_TX
+#define BF_UARTAPP_AUTOBAUD_UPDATE_TX_V(e)              BF_UARTAPP_AUTOBAUD_UPDATE_TX(BV_UARTAPP_AUTOBAUD_UPDATE_TX__##e)
+#define BFM_UARTAPP_AUTOBAUD_UPDATE_TX_V(v)             BM_UARTAPP_AUTOBAUD_UPDATE_TX
+#define BP_UARTAPP_AUTOBAUD_TWO_REF_CHARS               3
+#define BM_UARTAPP_AUTOBAUD_TWO_REF_CHARS               0x8
+#define BF_UARTAPP_AUTOBAUD_TWO_REF_CHARS(v)            (((v) & 0x1) << 3)
+#define BFM_UARTAPP_AUTOBAUD_TWO_REF_CHARS(v)           BM_UARTAPP_AUTOBAUD_TWO_REF_CHARS
+#define BF_UARTAPP_AUTOBAUD_TWO_REF_CHARS_V(e)          BF_UARTAPP_AUTOBAUD_TWO_REF_CHARS(BV_UARTAPP_AUTOBAUD_TWO_REF_CHARS__##e)
+#define BFM_UARTAPP_AUTOBAUD_TWO_REF_CHARS_V(v)         BM_UARTAPP_AUTOBAUD_TWO_REF_CHARS
+#define BP_UARTAPP_AUTOBAUD_START_WITH_RUNBIT           2
+#define BM_UARTAPP_AUTOBAUD_START_WITH_RUNBIT           0x4
+#define BF_UARTAPP_AUTOBAUD_START_WITH_RUNBIT(v)        (((v) & 0x1) << 2)
+#define BFM_UARTAPP_AUTOBAUD_START_WITH_RUNBIT(v)       BM_UARTAPP_AUTOBAUD_START_WITH_RUNBIT
+#define BF_UARTAPP_AUTOBAUD_START_WITH_RUNBIT_V(e)      BF_UARTAPP_AUTOBAUD_START_WITH_RUNBIT(BV_UARTAPP_AUTOBAUD_START_WITH_RUNBIT__##e)
+#define BFM_UARTAPP_AUTOBAUD_START_WITH_RUNBIT_V(v)     BM_UARTAPP_AUTOBAUD_START_WITH_RUNBIT
+#define BP_UARTAPP_AUTOBAUD_START_BAUD_DETECT           1
+#define BM_UARTAPP_AUTOBAUD_START_BAUD_DETECT           0x2
+#define BF_UARTAPP_AUTOBAUD_START_BAUD_DETECT(v)        (((v) & 0x1) << 1)
+#define BFM_UARTAPP_AUTOBAUD_START_BAUD_DETECT(v)       BM_UARTAPP_AUTOBAUD_START_BAUD_DETECT
+#define BF_UARTAPP_AUTOBAUD_START_BAUD_DETECT_V(e)      BF_UARTAPP_AUTOBAUD_START_BAUD_DETECT(BV_UARTAPP_AUTOBAUD_START_BAUD_DETECT__##e)
+#define BFM_UARTAPP_AUTOBAUD_START_BAUD_DETECT_V(v)     BM_UARTAPP_AUTOBAUD_START_BAUD_DETECT
+#define BP_UARTAPP_AUTOBAUD_BAUD_DETECT_ENABLE          0
+#define BM_UARTAPP_AUTOBAUD_BAUD_DETECT_ENABLE          0x1
+#define BF_UARTAPP_AUTOBAUD_BAUD_DETECT_ENABLE(v)       (((v) & 0x1) << 0)
+#define BFM_UARTAPP_AUTOBAUD_BAUD_DETECT_ENABLE(v)      BM_UARTAPP_AUTOBAUD_BAUD_DETECT_ENABLE
+#define BF_UARTAPP_AUTOBAUD_BAUD_DETECT_ENABLE_V(e)     BF_UARTAPP_AUTOBAUD_BAUD_DETECT_ENABLE(BV_UARTAPP_AUTOBAUD_BAUD_DETECT_ENABLE__##e)
+#define BFM_UARTAPP_AUTOBAUD_BAUD_DETECT_ENABLE_V(v)    BM_UARTAPP_AUTOBAUD_BAUD_DETECT_ENABLE
+
+#endif /* __HEADERGEN_IMX233_UARTAPP_H__*/
diff --git a/firmware/target/arm/imx233/regs/imx233/uartdbg.h b/firmware/target/arm/imx233/regs/imx233/uartdbg.h
new file mode 100644
index 0000000000..403550a59e
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/imx233/uartdbg.h
@@ -0,0 +1,817 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * imx233 version: 2.4.0
+ * imx233 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_IMX233_UARTDBG_H__
+#define __HEADERGEN_IMX233_UARTDBG_H__
+
+#define HW_UARTDBG_DR                   HW(UARTDBG_DR)
+#define HWA_UARTDBG_DR                  (0x80070000 + 0x0)
+#define HWT_UARTDBG_DR                  HWIO_32_RW
+#define HWN_UARTDBG_DR                  UARTDBG_DR
+#define HWI_UARTDBG_DR                  
+#define BP_UARTDBG_DR_UNAVAILABLE       16
+#define BM_UARTDBG_DR_UNAVAILABLE       0xffff0000
+#define BF_UARTDBG_DR_UNAVAILABLE(v)    (((v) & 0xffff) << 16)
+#define BFM_UARTDBG_DR_UNAVAILABLE(v)   BM_UARTDBG_DR_UNAVAILABLE
+#define BF_UARTDBG_DR_UNAVAILABLE_V(e)  BF_UARTDBG_DR_UNAVAILABLE(BV_UARTDBG_DR_UNAVAILABLE__##e)
+#define BFM_UARTDBG_DR_UNAVAILABLE_V(v) BM_UARTDBG_DR_UNAVAILABLE
+#define BP_UARTDBG_DR_RESERVED          12
+#define BM_UARTDBG_DR_RESERVED          0xf000
+#define BF_UARTDBG_DR_RESERVED(v)       (((v) & 0xf) << 12)
+#define BFM_UARTDBG_DR_RESERVED(v)      BM_UARTDBG_DR_RESERVED
+#define BF_UARTDBG_DR_RESERVED_V(e)     BF_UARTDBG_DR_RESERVED(BV_UARTDBG_DR_RESERVED__##e)
+#define BFM_UARTDBG_DR_RESERVED_V(v)    BM_UARTDBG_DR_RESERVED
+#define BP_UARTDBG_DR_OE                11
+#define BM_UARTDBG_DR_OE                0x800
+#define BF_UARTDBG_DR_OE(v)             (((v) & 0x1) << 11)
+#define BFM_UARTDBG_DR_OE(v)            BM_UARTDBG_DR_OE
+#define BF_UARTDBG_DR_OE_V(e)           BF_UARTDBG_DR_OE(BV_UARTDBG_DR_OE__##e)
+#define BFM_UARTDBG_DR_OE_V(v)          BM_UARTDBG_DR_OE
+#define BP_UARTDBG_DR_BE                10
+#define BM_UARTDBG_DR_BE                0x400
+#define BF_UARTDBG_DR_BE(v)             (((v) & 0x1) << 10)
+#define BFM_UARTDBG_DR_BE(v)            BM_UARTDBG_DR_BE
+#define BF_UARTDBG_DR_BE_V(e)           BF_UARTDBG_DR_BE(BV_UARTDBG_DR_BE__##e)
+#define BFM_UARTDBG_DR_BE_V(v)          BM_UARTDBG_DR_BE
+#define BP_UARTDBG_DR_PE                9
+#define BM_UARTDBG_DR_PE                0x200
+#define BF_UARTDBG_DR_PE(v)             (((v) & 0x1) << 9)
+#define BFM_UARTDBG_DR_PE(v)            BM_UARTDBG_DR_PE
+#define BF_UARTDBG_DR_PE_V(e)           BF_UARTDBG_DR_PE(BV_UARTDBG_DR_PE__##e)
+#define BFM_UARTDBG_DR_PE_V(v)          BM_UARTDBG_DR_PE
+#define BP_UARTDBG_DR_FE                8
+#define BM_UARTDBG_DR_FE                0x100
+#define BF_UARTDBG_DR_FE(v)             (((v) & 0x1) << 8)
+#define BFM_UARTDBG_DR_FE(v)            BM_UARTDBG_DR_FE
+#define BF_UARTDBG_DR_FE_V(e)           BF_UARTDBG_DR_FE(BV_UARTDBG_DR_FE__##e)
+#define BFM_UARTDBG_DR_FE_V(v)          BM_UARTDBG_DR_FE
+#define BP_UARTDBG_DR_DATA              0
+#define BM_UARTDBG_DR_DATA              0xff
+#define BF_UARTDBG_DR_DATA(v)           (((v) & 0xff) << 0)
+#define BFM_UARTDBG_DR_DATA(v)          BM_UARTDBG_DR_DATA
+#define BF_UARTDBG_DR_DATA_V(e)         BF_UARTDBG_DR_DATA(BV_UARTDBG_DR_DATA__##e)
+#define BFM_UARTDBG_DR_DATA_V(v)        BM_UARTDBG_DR_DATA
+
+#define HW_UARTDBG_RSR_ECR                      HW(UARTDBG_RSR_ECR)
+#define HWA_UARTDBG_RSR_ECR                     (0x80070000 + 0x4)
+#define HWT_UARTDBG_RSR_ECR                     HWIO_32_RW
+#define HWN_UARTDBG_RSR_ECR                     UARTDBG_RSR_ECR
+#define HWI_UARTDBG_RSR_ECR                     
+#define BP_UARTDBG_RSR_ECR_UNAVAILABLE          8
+#define BM_UARTDBG_RSR_ECR_UNAVAILABLE          0xffffff00
+#define BF_UARTDBG_RSR_ECR_UNAVAILABLE(v)       (((v) & 0xffffff) << 8)
+#define BFM_UARTDBG_RSR_ECR_UNAVAILABLE(v)      BM_UARTDBG_RSR_ECR_UNAVAILABLE
+#define BF_UARTDBG_RSR_ECR_UNAVAILABLE_V(e)     BF_UARTDBG_RSR_ECR_UNAVAILABLE(BV_UARTDBG_RSR_ECR_UNAVAILABLE__##e)
+#define BFM_UARTDBG_RSR_ECR_UNAVAILABLE_V(v)    BM_UARTDBG_RSR_ECR_UNAVAILABLE
+#define BP_UARTDBG_RSR_ECR_EC                   4
+#define BM_UARTDBG_RSR_ECR_EC                   0xf0
+#define BF_UARTDBG_RSR_ECR_EC(v)                (((v) & 0xf) << 4)
+#define BFM_UARTDBG_RSR_ECR_EC(v)               BM_UARTDBG_RSR_ECR_EC
+#define BF_UARTDBG_RSR_ECR_EC_V(e)              BF_UARTDBG_RSR_ECR_EC(BV_UARTDBG_RSR_ECR_EC__##e)
+#define BFM_UARTDBG_RSR_ECR_EC_V(v)             BM_UARTDBG_RSR_ECR_EC
+#define BP_UARTDBG_RSR_ECR_OE                   3
+#define BM_UARTDBG_RSR_ECR_OE                   0x8
+#define BF_UARTDBG_RSR_ECR_OE(v)                (((v) & 0x1) << 3)
+#define BFM_UARTDBG_RSR_ECR_OE(v)               BM_UARTDBG_RSR_ECR_OE
+#define BF_UARTDBG_RSR_ECR_OE_V(e)              BF_UARTDBG_RSR_ECR_OE(BV_UARTDBG_RSR_ECR_OE__##e)
+#define BFM_UARTDBG_RSR_ECR_OE_V(v)             BM_UARTDBG_RSR_ECR_OE
+#define BP_UARTDBG_RSR_ECR_BE                   2
+#define BM_UARTDBG_RSR_ECR_BE                   0x4
+#define BF_UARTDBG_RSR_ECR_BE(v)                (((v) & 0x1) << 2)
+#define BFM_UARTDBG_RSR_ECR_BE(v)               BM_UARTDBG_RSR_ECR_BE
+#define BF_UARTDBG_RSR_ECR_BE_V(e)              BF_UARTDBG_RSR_ECR_BE(BV_UARTDBG_RSR_ECR_BE__##e)
+#define BFM_UARTDBG_RSR_ECR_BE_V(v)             BM_UARTDBG_RSR_ECR_BE
+#define BP_UARTDBG_RSR_ECR_PE                   1
+#define BM_UARTDBG_RSR_ECR_PE                   0x2
+#define BF_UARTDBG_RSR_ECR_PE(v)                (((v) & 0x1) << 1)
+#define BFM_UARTDBG_RSR_ECR_PE(v)               BM_UARTDBG_RSR_ECR_PE
+#define BF_UARTDBG_RSR_ECR_PE_V(e)              BF_UARTDBG_RSR_ECR_PE(BV_UARTDBG_RSR_ECR_PE__##e)
+#define BFM_UARTDBG_RSR_ECR_PE_V(v)             BM_UARTDBG_RSR_ECR_PE
+#define BP_UARTDBG_RSR_ECR_FE                   0
+#define BM_UARTDBG_RSR_ECR_FE                   0x1
+#define BF_UARTDBG_RSR_ECR_FE(v)                (((v) & 0x1) << 0)
+#define BFM_UARTDBG_RSR_ECR_FE(v)               BM_UARTDBG_RSR_ECR_FE
+#define BF_UARTDBG_RSR_ECR_FE_V(e)              BF_UARTDBG_RSR_ECR_FE(BV_UARTDBG_RSR_ECR_FE__##e)
+#define BFM_UARTDBG_RSR_ECR_FE_V(v)             BM_UARTDBG_RSR_ECR_FE
+
+#define HW_UARTDBG_FR                   HW(UARTDBG_FR)
+#define HWA_UARTDBG_FR                  (0x80070000 + 0x18)
+#define HWT_UARTDBG_FR                  HWIO_32_RW
+#define HWN_UARTDBG_FR                  UARTDBG_FR
+#define HWI_UARTDBG_FR                  
+#define BP_UARTDBG_FR_UNAVAILABLE       16
+#define BM_UARTDBG_FR_UNAVAILABLE       0xffff0000
+#define BF_UARTDBG_FR_UNAVAILABLE(v)    (((v) & 0xffff) << 16)
+#define BFM_UARTDBG_FR_UNAVAILABLE(v)   BM_UARTDBG_FR_UNAVAILABLE
+#define BF_UARTDBG_FR_UNAVAILABLE_V(e)  BF_UARTDBG_FR_UNAVAILABLE(BV_UARTDBG_FR_UNAVAILABLE__##e)
+#define BFM_UARTDBG_FR_UNAVAILABLE_V(v) BM_UARTDBG_FR_UNAVAILABLE
+#define BP_UARTDBG_FR_RESERVED          9
+#define BM_UARTDBG_FR_RESERVED          0xfe00
+#define BF_UARTDBG_FR_RESERVED(v)       (((v) & 0x7f) << 9)
+#define BFM_UARTDBG_FR_RESERVED(v)      BM_UARTDBG_FR_RESERVED
+#define BF_UARTDBG_FR_RESERVED_V(e)     BF_UARTDBG_FR_RESERVED(BV_UARTDBG_FR_RESERVED__##e)
+#define BFM_UARTDBG_FR_RESERVED_V(v)    BM_UARTDBG_FR_RESERVED
+#define BP_UARTDBG_FR_RI                8
+#define BM_UARTDBG_FR_RI                0x100
+#define BF_UARTDBG_FR_RI(v)             (((v) & 0x1) << 8)
+#define BFM_UARTDBG_FR_RI(v)            BM_UARTDBG_FR_RI
+#define BF_UARTDBG_FR_RI_V(e)           BF_UARTDBG_FR_RI(BV_UARTDBG_FR_RI__##e)
+#define BFM_UARTDBG_FR_RI_V(v)          BM_UARTDBG_FR_RI
+#define BP_UARTDBG_FR_TXFE              7
+#define BM_UARTDBG_FR_TXFE              0x80
+#define BF_UARTDBG_FR_TXFE(v)           (((v) & 0x1) << 7)
+#define BFM_UARTDBG_FR_TXFE(v)          BM_UARTDBG_FR_TXFE
+#define BF_UARTDBG_FR_TXFE_V(e)         BF_UARTDBG_FR_TXFE(BV_UARTDBG_FR_TXFE__##e)
+#define BFM_UARTDBG_FR_TXFE_V(v)        BM_UARTDBG_FR_TXFE
+#define BP_UARTDBG_FR_RXFF              6
+#define BM_UARTDBG_FR_RXFF              0x40
+#define BF_UARTDBG_FR_RXFF(v)           (((v) & 0x1) << 6)
+#define BFM_UARTDBG_FR_RXFF(v)          BM_UARTDBG_FR_RXFF
+#define BF_UARTDBG_FR_RXFF_V(e)         BF_UARTDBG_FR_RXFF(BV_UARTDBG_FR_RXFF__##e)
+#define BFM_UARTDBG_FR_RXFF_V(v)        BM_UARTDBG_FR_RXFF
+#define BP_UARTDBG_FR_TXFF              5
+#define BM_UARTDBG_FR_TXFF              0x20
+#define BF_UARTDBG_FR_TXFF(v)           (((v) & 0x1) << 5)
+#define BFM_UARTDBG_FR_TXFF(v)          BM_UARTDBG_FR_TXFF
+#define BF_UARTDBG_FR_TXFF_V(e)         BF_UARTDBG_FR_TXFF(BV_UARTDBG_FR_TXFF__##e)
+#define BFM_UARTDBG_FR_TXFF_V(v)        BM_UARTDBG_FR_TXFF
+#define BP_UARTDBG_FR_RXFE              4
+#define BM_UARTDBG_FR_RXFE              0x10
+#define BF_UARTDBG_FR_RXFE(v)           (((v) & 0x1) << 4)
+#define BFM_UARTDBG_FR_RXFE(v)          BM_UARTDBG_FR_RXFE
+#define BF_UARTDBG_FR_RXFE_V(e)         BF_UARTDBG_FR_RXFE(BV_UARTDBG_FR_RXFE__##e)
+#define BFM_UARTDBG_FR_RXFE_V(v)        BM_UARTDBG_FR_RXFE
+#define BP_UARTDBG_FR_BUSY              3
+#define BM_UARTDBG_FR_BUSY              0x8
+#define BF_UARTDBG_FR_BUSY(v)           (((v) & 0x1) << 3)
+#define BFM_UARTDBG_FR_BUSY(v)          BM_UARTDBG_FR_BUSY
+#define BF_UARTDBG_FR_BUSY_V(e)         BF_UARTDBG_FR_BUSY(BV_UARTDBG_FR_BUSY__##e)
+#define BFM_UARTDBG_FR_BUSY_V(v)        BM_UARTDBG_FR_BUSY
+#define BP_UARTDBG_FR_DCD               2
+#define BM_UARTDBG_FR_DCD               0x4
+#define BF_UARTDBG_FR_DCD(v)            (((v) & 0x1) << 2)
+#define BFM_UARTDBG_FR_DCD(v)           BM_UARTDBG_FR_DCD
+#define BF_UARTDBG_FR_DCD_V(e)          BF_UARTDBG_FR_DCD(BV_UARTDBG_FR_DCD__##e)
+#define BFM_UARTDBG_FR_DCD_V(v)         BM_UARTDBG_FR_DCD
+#define BP_UARTDBG_FR_DSR               1
+#define BM_UARTDBG_FR_DSR               0x2
+#define BF_UARTDBG_FR_DSR(v)            (((v) & 0x1) << 1)
+#define BFM_UARTDBG_FR_DSR(v)           BM_UARTDBG_FR_DSR
+#define BF_UARTDBG_FR_DSR_V(e)          BF_UARTDBG_FR_DSR(BV_UARTDBG_FR_DSR__##e)
+#define BFM_UARTDBG_FR_DSR_V(v)         BM_UARTDBG_FR_DSR
+#define BP_UARTDBG_FR_CTS               0
+#define BM_UARTDBG_FR_CTS               0x1
+#define BF_UARTDBG_FR_CTS(v)            (((v) & 0x1) << 0)
+#define BFM_UARTDBG_FR_CTS(v)           BM_UARTDBG_FR_CTS
+#define BF_UARTDBG_FR_CTS_V(e)          BF_UARTDBG_FR_CTS(BV_UARTDBG_FR_CTS__##e)
+#define BFM_UARTDBG_FR_CTS_V(v)         BM_UARTDBG_FR_CTS
+
+#define HW_UARTDBG_ILPR                     HW(UARTDBG_ILPR)
+#define HWA_UARTDBG_ILPR                    (0x80070000 + 0x20)
+#define HWT_UARTDBG_ILPR                    HWIO_32_RW
+#define HWN_UARTDBG_ILPR                    UARTDBG_ILPR
+#define HWI_UARTDBG_ILPR                    
+#define BP_UARTDBG_ILPR_UNAVAILABLE         8
+#define BM_UARTDBG_ILPR_UNAVAILABLE         0xffffff00
+#define BF_UARTDBG_ILPR_UNAVAILABLE(v)      (((v) & 0xffffff) << 8)
+#define BFM_UARTDBG_ILPR_UNAVAILABLE(v)     BM_UARTDBG_ILPR_UNAVAILABLE
+#define BF_UARTDBG_ILPR_UNAVAILABLE_V(e)    BF_UARTDBG_ILPR_UNAVAILABLE(BV_UARTDBG_ILPR_UNAVAILABLE__##e)
+#define BFM_UARTDBG_ILPR_UNAVAILABLE_V(v)   BM_UARTDBG_ILPR_UNAVAILABLE
+#define BP_UARTDBG_ILPR_ILPDVSR             0
+#define BM_UARTDBG_ILPR_ILPDVSR             0xff
+#define BF_UARTDBG_ILPR_ILPDVSR(v)          (((v) & 0xff) << 0)
+#define BFM_UARTDBG_ILPR_ILPDVSR(v)         BM_UARTDBG_ILPR_ILPDVSR
+#define BF_UARTDBG_ILPR_ILPDVSR_V(e)        BF_UARTDBG_ILPR_ILPDVSR(BV_UARTDBG_ILPR_ILPDVSR__##e)
+#define BFM_UARTDBG_ILPR_ILPDVSR_V(v)       BM_UARTDBG_ILPR_ILPDVSR
+
+#define HW_UARTDBG_IBRD                     HW(UARTDBG_IBRD)
+#define HWA_UARTDBG_IBRD                    (0x80070000 + 0x24)
+#define HWT_UARTDBG_IBRD                    HWIO_32_RW
+#define HWN_UARTDBG_IBRD                    UARTDBG_IBRD
+#define HWI_UARTDBG_IBRD                    
+#define BP_UARTDBG_IBRD_UNAVAILABLE         16
+#define BM_UARTDBG_IBRD_UNAVAILABLE         0xffff0000
+#define BF_UARTDBG_IBRD_UNAVAILABLE(v)      (((v) & 0xffff) << 16)
+#define BFM_UARTDBG_IBRD_UNAVAILABLE(v)     BM_UARTDBG_IBRD_UNAVAILABLE
+#define BF_UARTDBG_IBRD_UNAVAILABLE_V(e)    BF_UARTDBG_IBRD_UNAVAILABLE(BV_UARTDBG_IBRD_UNAVAILABLE__##e)
+#define BFM_UARTDBG_IBRD_UNAVAILABLE_V(v)   BM_UARTDBG_IBRD_UNAVAILABLE
+#define BP_UARTDBG_IBRD_BAUD_DIVINT         0
+#define BM_UARTDBG_IBRD_BAUD_DIVINT         0xffff
+#define BF_UARTDBG_IBRD_BAUD_DIVINT(v)      (((v) & 0xffff) << 0)
+#define BFM_UARTDBG_IBRD_BAUD_DIVINT(v)     BM_UARTDBG_IBRD_BAUD_DIVINT
+#define BF_UARTDBG_IBRD_BAUD_DIVINT_V(e)    BF_UARTDBG_IBRD_BAUD_DIVINT(BV_UARTDBG_IBRD_BAUD_DIVINT__##e)
+#define BFM_UARTDBG_IBRD_BAUD_DIVINT_V(v)   BM_UARTDBG_IBRD_BAUD_DIVINT
+
+#define HW_UARTDBG_FBRD                     HW(UARTDBG_FBRD)
+#define HWA_UARTDBG_FBRD                    (0x80070000 + 0x28)
+#define HWT_UARTDBG_FBRD                    HWIO_32_RW
+#define HWN_UARTDBG_FBRD                    UARTDBG_FBRD
+#define HWI_UARTDBG_FBRD                    
+#define BP_UARTDBG_FBRD_UNAVAILABLE         8
+#define BM_UARTDBG_FBRD_UNAVAILABLE         0xffffff00
+#define BF_UARTDBG_FBRD_UNAVAILABLE(v)      (((v) & 0xffffff) << 8)
+#define BFM_UARTDBG_FBRD_UNAVAILABLE(v)     BM_UARTDBG_FBRD_UNAVAILABLE
+#define BF_UARTDBG_FBRD_UNAVAILABLE_V(e)    BF_UARTDBG_FBRD_UNAVAILABLE(BV_UARTDBG_FBRD_UNAVAILABLE__##e)
+#define BFM_UARTDBG_FBRD_UNAVAILABLE_V(v)   BM_UARTDBG_FBRD_UNAVAILABLE
+#define BP_UARTDBG_FBRD_RESERVED            6
+#define BM_UARTDBG_FBRD_RESERVED            0xc0
+#define BF_UARTDBG_FBRD_RESERVED(v)         (((v) & 0x3) << 6)
+#define BFM_UARTDBG_FBRD_RESERVED(v)        BM_UARTDBG_FBRD_RESERVED
+#define BF_UARTDBG_FBRD_RESERVED_V(e)       BF_UARTDBG_FBRD_RESERVED(BV_UARTDBG_FBRD_RESERVED__##e)
+#define BFM_UARTDBG_FBRD_RESERVED_V(v)      BM_UARTDBG_FBRD_RESERVED
+#define BP_UARTDBG_FBRD_BAUD_DIVFRAC        0
+#define BM_UARTDBG_FBRD_BAUD_DIVFRAC        0x3f
+#define BF_UARTDBG_FBRD_BAUD_DIVFRAC(v)     (((v) & 0x3f) << 0)
+#define BFM_UARTDBG_FBRD_BAUD_DIVFRAC(v)    BM_UARTDBG_FBRD_BAUD_DIVFRAC
+#define BF_UARTDBG_FBRD_BAUD_DIVFRAC_V(e)   BF_UARTDBG_FBRD_BAUD_DIVFRAC(BV_UARTDBG_FBRD_BAUD_DIVFRAC__##e)
+#define BFM_UARTDBG_FBRD_BAUD_DIVFRAC_V(v)  BM_UARTDBG_FBRD_BAUD_DIVFRAC
+
+#define HW_UARTDBG_LCR_H                    HW(UARTDBG_LCR_H)
+#define HWA_UARTDBG_LCR_H                   (0x80070000 + 0x2c)
+#define HWT_UARTDBG_LCR_H                   HWIO_32_RW
+#define HWN_UARTDBG_LCR_H                   UARTDBG_LCR_H
+#define HWI_UARTDBG_LCR_H                   
+#define BP_UARTDBG_LCR_H_UNAVAILABLE        16
+#define BM_UARTDBG_LCR_H_UNAVAILABLE        0xffff0000
+#define BF_UARTDBG_LCR_H_UNAVAILABLE(v)     (((v) & 0xffff) << 16)
+#define BFM_UARTDBG_LCR_H_UNAVAILABLE(v)    BM_UARTDBG_LCR_H_UNAVAILABLE
+#define BF_UARTDBG_LCR_H_UNAVAILABLE_V(e)   BF_UARTDBG_LCR_H_UNAVAILABLE(BV_UARTDBG_LCR_H_UNAVAILABLE__##e)
+#define BFM_UARTDBG_LCR_H_UNAVAILABLE_V(v)  BM_UARTDBG_LCR_H_UNAVAILABLE
+#define BP_UARTDBG_LCR_H_RESERVED           8
+#define BM_UARTDBG_LCR_H_RESERVED           0xff00
+#define BF_UARTDBG_LCR_H_RESERVED(v)        (((v) & 0xff) << 8)
+#define BFM_UARTDBG_LCR_H_RESERVED(v)       BM_UARTDBG_LCR_H_RESERVED
+#define BF_UARTDBG_LCR_H_RESERVED_V(e)      BF_UARTDBG_LCR_H_RESERVED(BV_UARTDBG_LCR_H_RESERVED__##e)
+#define BFM_UARTDBG_LCR_H_RESERVED_V(v)     BM_UARTDBG_LCR_H_RESERVED
+#define BP_UARTDBG_LCR_H_SPS                7
+#define BM_UARTDBG_LCR_H_SPS                0x80
+#define BF_UARTDBG_LCR_H_SPS(v)             (((v) & 0x1) << 7)
+#define BFM_UARTDBG_LCR_H_SPS(v)            BM_UARTDBG_LCR_H_SPS
+#define BF_UARTDBG_LCR_H_SPS_V(e)           BF_UARTDBG_LCR_H_SPS(BV_UARTDBG_LCR_H_SPS__##e)
+#define BFM_UARTDBG_LCR_H_SPS_V(v)          BM_UARTDBG_LCR_H_SPS
+#define BP_UARTDBG_LCR_H_WLEN               5
+#define BM_UARTDBG_LCR_H_WLEN               0x60
+#define BF_UARTDBG_LCR_H_WLEN(v)            (((v) & 0x3) << 5)
+#define BFM_UARTDBG_LCR_H_WLEN(v)           BM_UARTDBG_LCR_H_WLEN
+#define BF_UARTDBG_LCR_H_WLEN_V(e)          BF_UARTDBG_LCR_H_WLEN(BV_UARTDBG_LCR_H_WLEN__##e)
+#define BFM_UARTDBG_LCR_H_WLEN_V(v)         BM_UARTDBG_LCR_H_WLEN
+#define BP_UARTDBG_LCR_H_FEN                4
+#define BM_UARTDBG_LCR_H_FEN                0x10
+#define BF_UARTDBG_LCR_H_FEN(v)             (((v) & 0x1) << 4)
+#define BFM_UARTDBG_LCR_H_FEN(v)            BM_UARTDBG_LCR_H_FEN
+#define BF_UARTDBG_LCR_H_FEN_V(e)           BF_UARTDBG_LCR_H_FEN(BV_UARTDBG_LCR_H_FEN__##e)
+#define BFM_UARTDBG_LCR_H_FEN_V(v)          BM_UARTDBG_LCR_H_FEN
+#define BP_UARTDBG_LCR_H_STP2               3
+#define BM_UARTDBG_LCR_H_STP2               0x8
+#define BF_UARTDBG_LCR_H_STP2(v)            (((v) & 0x1) << 3)
+#define BFM_UARTDBG_LCR_H_STP2(v)           BM_UARTDBG_LCR_H_STP2
+#define BF_UARTDBG_LCR_H_STP2_V(e)          BF_UARTDBG_LCR_H_STP2(BV_UARTDBG_LCR_H_STP2__##e)
+#define BFM_UARTDBG_LCR_H_STP2_V(v)         BM_UARTDBG_LCR_H_STP2
+#define BP_UARTDBG_LCR_H_EPS                2
+#define BM_UARTDBG_LCR_H_EPS                0x4
+#define BF_UARTDBG_LCR_H_EPS(v)             (((v) & 0x1) << 2)
+#define BFM_UARTDBG_LCR_H_EPS(v)            BM_UARTDBG_LCR_H_EPS
+#define BF_UARTDBG_LCR_H_EPS_V(e)           BF_UARTDBG_LCR_H_EPS(BV_UARTDBG_LCR_H_EPS__##e)
+#define BFM_UARTDBG_LCR_H_EPS_V(v)          BM_UARTDBG_LCR_H_EPS
+#define BP_UARTDBG_LCR_H_PEN                1
+#define BM_UARTDBG_LCR_H_PEN                0x2
+#define BF_UARTDBG_LCR_H_PEN(v)             (((v) & 0x1) << 1)
+#define BFM_UARTDBG_LCR_H_PEN(v)            BM_UARTDBG_LCR_H_PEN
+#define BF_UARTDBG_LCR_H_PEN_V(e)           BF_UARTDBG_LCR_H_PEN(BV_UARTDBG_LCR_H_PEN__##e)
+#define BFM_UARTDBG_LCR_H_PEN_V(v)          BM_UARTDBG_LCR_H_PEN
+#define BP_UARTDBG_LCR_H_BRK                0
+#define BM_UARTDBG_LCR_H_BRK                0x1
+#define BF_UARTDBG_LCR_H_BRK(v)             (((v) & 0x1) << 0)
+#define BFM_UARTDBG_LCR_H_BRK(v)            BM_UARTDBG_LCR_H_BRK
+#define BF_UARTDBG_LCR_H_BRK_V(e)           BF_UARTDBG_LCR_H_BRK(BV_UARTDBG_LCR_H_BRK__##e)
+#define BFM_UARTDBG_LCR_H_BRK_V(v)          BM_UARTDBG_LCR_H_BRK
+
+#define HW_UARTDBG_CR                   HW(UARTDBG_CR)
+#define HWA_UARTDBG_CR                  (0x80070000 + 0x30)
+#define HWT_UARTDBG_CR                  HWIO_32_RW
+#define HWN_UARTDBG_CR                  UARTDBG_CR
+#define HWI_UARTDBG_CR                  
+#define BP_UARTDBG_CR_UNAVAILABLE       16
+#define BM_UARTDBG_CR_UNAVAILABLE       0xffff0000
+#define BF_UARTDBG_CR_UNAVAILABLE(v)    (((v) & 0xffff) << 16)
+#define BFM_UARTDBG_CR_UNAVAILABLE(v)   BM_UARTDBG_CR_UNAVAILABLE
+#define BF_UARTDBG_CR_UNAVAILABLE_V(e)  BF_UARTDBG_CR_UNAVAILABLE(BV_UARTDBG_CR_UNAVAILABLE__##e)
+#define BFM_UARTDBG_CR_UNAVAILABLE_V(v) BM_UARTDBG_CR_UNAVAILABLE
+#define BP_UARTDBG_CR_CTSEN             15
+#define BM_UARTDBG_CR_CTSEN             0x8000
+#define BF_UARTDBG_CR_CTSEN(v)          (((v) & 0x1) << 15)
+#define BFM_UARTDBG_CR_CTSEN(v)         BM_UARTDBG_CR_CTSEN
+#define BF_UARTDBG_CR_CTSEN_V(e)        BF_UARTDBG_CR_CTSEN(BV_UARTDBG_CR_CTSEN__##e)
+#define BFM_UARTDBG_CR_CTSEN_V(v)       BM_UARTDBG_CR_CTSEN
+#define BP_UARTDBG_CR_RTSEN             14
+#define BM_UARTDBG_CR_RTSEN             0x4000
+#define BF_UARTDBG_CR_RTSEN(v)          (((v) & 0x1) << 14)
+#define BFM_UARTDBG_CR_RTSEN(v)         BM_UARTDBG_CR_RTSEN
+#define BF_UARTDBG_CR_RTSEN_V(e)        BF_UARTDBG_CR_RTSEN(BV_UARTDBG_CR_RTSEN__##e)
+#define BFM_UARTDBG_CR_RTSEN_V(v)       BM_UARTDBG_CR_RTSEN
+#define BP_UARTDBG_CR_OUT2              13
+#define BM_UARTDBG_CR_OUT2              0x2000
+#define BF_UARTDBG_CR_OUT2(v)           (((v) & 0x1) << 13)
+#define BFM_UARTDBG_CR_OUT2(v)          BM_UARTDBG_CR_OUT2
+#define BF_UARTDBG_CR_OUT2_V(e)         BF_UARTDBG_CR_OUT2(BV_UARTDBG_CR_OUT2__##e)
+#define BFM_UARTDBG_CR_OUT2_V(v)        BM_UARTDBG_CR_OUT2
+#define BP_UARTDBG_CR_OUT1              12
+#define BM_UARTDBG_CR_OUT1              0x1000
+#define BF_UARTDBG_CR_OUT1(v)           (((v) & 0x1) << 12)
+#define BFM_UARTDBG_CR_OUT1(v)          BM_UARTDBG_CR_OUT1
+#define BF_UARTDBG_CR_OUT1_V(e)         BF_UARTDBG_CR_OUT1(BV_UARTDBG_CR_OUT1__##e)
+#define BFM_UARTDBG_CR_OUT1_V(v)        BM_UARTDBG_CR_OUT1
+#define BP_UARTDBG_CR_RTS               11
+#define BM_UARTDBG_CR_RTS               0x800
+#define BF_UARTDBG_CR_RTS(v)            (((v) & 0x1) << 11)
+#define BFM_UARTDBG_CR_RTS(v)           BM_UARTDBG_CR_RTS
+#define BF_UARTDBG_CR_RTS_V(e)          BF_UARTDBG_CR_RTS(BV_UARTDBG_CR_RTS__##e)
+#define BFM_UARTDBG_CR_RTS_V(v)         BM_UARTDBG_CR_RTS
+#define BP_UARTDBG_CR_DTR               10
+#define BM_UARTDBG_CR_DTR               0x400
+#define BF_UARTDBG_CR_DTR(v)            (((v) & 0x1) << 10)
+#define BFM_UARTDBG_CR_DTR(v)           BM_UARTDBG_CR_DTR
+#define BF_UARTDBG_CR_DTR_V(e)          BF_UARTDBG_CR_DTR(BV_UARTDBG_CR_DTR__##e)
+#define BFM_UARTDBG_CR_DTR_V(v)         BM_UARTDBG_CR_DTR
+#define BP_UARTDBG_CR_RXE               9
+#define BM_UARTDBG_CR_RXE               0x200
+#define BF_UARTDBG_CR_RXE(v)            (((v) & 0x1) << 9)
+#define BFM_UARTDBG_CR_RXE(v)           BM_UARTDBG_CR_RXE
+#define BF_UARTDBG_CR_RXE_V(e)          BF_UARTDBG_CR_RXE(BV_UARTDBG_CR_RXE__##e)
+#define BFM_UARTDBG_CR_RXE_V(v)         BM_UARTDBG_CR_RXE
+#define BP_UARTDBG_CR_TXE               8
+#define BM_UARTDBG_CR_TXE               0x100
+#define BF_UARTDBG_CR_TXE(v)            (((v) & 0x1) << 8)
+#define BFM_UARTDBG_CR_TXE(v)           BM_UARTDBG_CR_TXE
+#define BF_UARTDBG_CR_TXE_V(e)          BF_UARTDBG_CR_TXE(BV_UARTDBG_CR_TXE__##e)
+#define BFM_UARTDBG_CR_TXE_V(v)         BM_UARTDBG_CR_TXE
+#define BP_UARTDBG_CR_LBE               7
+#define BM_UARTDBG_CR_LBE               0x80
+#define BF_UARTDBG_CR_LBE(v)            (((v) & 0x1) << 7)
+#define BFM_UARTDBG_CR_LBE(v)           BM_UARTDBG_CR_LBE
+#define BF_UARTDBG_CR_LBE_V(e)          BF_UARTDBG_CR_LBE(BV_UARTDBG_CR_LBE__##e)
+#define BFM_UARTDBG_CR_LBE_V(v)         BM_UARTDBG_CR_LBE
+#define BP_UARTDBG_CR_RESERVED          3
+#define BM_UARTDBG_CR_RESERVED          0x78
+#define BF_UARTDBG_CR_RESERVED(v)       (((v) & 0xf) << 3)
+#define BFM_UARTDBG_CR_RESERVED(v)      BM_UARTDBG_CR_RESERVED
+#define BF_UARTDBG_CR_RESERVED_V(e)     BF_UARTDBG_CR_RESERVED(BV_UARTDBG_CR_RESERVED__##e)
+#define BFM_UARTDBG_CR_RESERVED_V(v)    BM_UARTDBG_CR_RESERVED
+#define BP_UARTDBG_CR_SIRLP             2
+#define BM_UARTDBG_CR_SIRLP             0x4
+#define BF_UARTDBG_CR_SIRLP(v)          (((v) & 0x1) << 2)
+#define BFM_UARTDBG_CR_SIRLP(v)         BM_UARTDBG_CR_SIRLP
+#define BF_UARTDBG_CR_SIRLP_V(e)        BF_UARTDBG_CR_SIRLP(BV_UARTDBG_CR_SIRLP__##e)
+#define BFM_UARTDBG_CR_SIRLP_V(v)       BM_UARTDBG_CR_SIRLP
+#define BP_UARTDBG_CR_SIREN             1
+#define BM_UARTDBG_CR_SIREN             0x2
+#define BF_UARTDBG_CR_SIREN(v)          (((v) & 0x1) << 1)
+#define BFM_UARTDBG_CR_SIREN(v)         BM_UARTDBG_CR_SIREN
+#define BF_UARTDBG_CR_SIREN_V(e)        BF_UARTDBG_CR_SIREN(BV_UARTDBG_CR_SIREN__##e)
+#define BFM_UARTDBG_CR_SIREN_V(v)       BM_UARTDBG_CR_SIREN
+#define BP_UARTDBG_CR_UARTEN            0
+#define BM_UARTDBG_CR_UARTEN            0x1
+#define BF_UARTDBG_CR_UARTEN(v)         (((v) & 0x1) << 0)
+#define BFM_UARTDBG_CR_UARTEN(v)        BM_UARTDBG_CR_UARTEN
+#define BF_UARTDBG_CR_UARTEN_V(e)       BF_UARTDBG_CR_UARTEN(BV_UARTDBG_CR_UARTEN__##e)
+#define BFM_UARTDBG_CR_UARTEN_V(v)      BM_UARTDBG_CR_UARTEN
+
+#define HW_UARTDBG_IFLS                             HW(UARTDBG_IFLS)
+#define HWA_UARTDBG_IFLS                            (0x80070000 + 0x34)
+#define HWT_UARTDBG_IFLS                            HWIO_32_RW
+#define HWN_UARTDBG_IFLS                            UARTDBG_IFLS
+#define HWI_UARTDBG_IFLS                            
+#define BP_UARTDBG_IFLS_UNAVAILABLE                 16
+#define BM_UARTDBG_IFLS_UNAVAILABLE                 0xffff0000
+#define BF_UARTDBG_IFLS_UNAVAILABLE(v)              (((v) & 0xffff) << 16)
+#define BFM_UARTDBG_IFLS_UNAVAILABLE(v)             BM_UARTDBG_IFLS_UNAVAILABLE
+#define BF_UARTDBG_IFLS_UNAVAILABLE_V(e)            BF_UARTDBG_IFLS_UNAVAILABLE(BV_UARTDBG_IFLS_UNAVAILABLE__##e)
+#define BFM_UARTDBG_IFLS_UNAVAILABLE_V(v)           BM_UARTDBG_IFLS_UNAVAILABLE
+#define BP_UARTDBG_IFLS_RESERVED                    6
+#define BM_UARTDBG_IFLS_RESERVED                    0xffc0
+#define BF_UARTDBG_IFLS_RESERVED(v)                 (((v) & 0x3ff) << 6)
+#define BFM_UARTDBG_IFLS_RESERVED(v)                BM_UARTDBG_IFLS_RESERVED
+#define BF_UARTDBG_IFLS_RESERVED_V(e)               BF_UARTDBG_IFLS_RESERVED(BV_UARTDBG_IFLS_RESERVED__##e)
+#define BFM_UARTDBG_IFLS_RESERVED_V(v)              BM_UARTDBG_IFLS_RESERVED
+#define BP_UARTDBG_IFLS_RXIFLSEL                    3
+#define BM_UARTDBG_IFLS_RXIFLSEL                    0x38
+#define BV_UARTDBG_IFLS_RXIFLSEL__NOT_EMPTY         0x0
+#define BV_UARTDBG_IFLS_RXIFLSEL__ONE_QUARTER       0x1
+#define BV_UARTDBG_IFLS_RXIFLSEL__ONE_HALF          0x2
+#define BV_UARTDBG_IFLS_RXIFLSEL__THREE_QUARTERS    0x3
+#define BV_UARTDBG_IFLS_RXIFLSEL__SEVEN_EIGHTHS     0x4
+#define BV_UARTDBG_IFLS_RXIFLSEL__INVALID5          0x5
+#define BV_UARTDBG_IFLS_RXIFLSEL__INVALID6          0x6
+#define BV_UARTDBG_IFLS_RXIFLSEL__INVALID7          0x7
+#define BF_UARTDBG_IFLS_RXIFLSEL(v)                 (((v) & 0x7) << 3)
+#define BFM_UARTDBG_IFLS_RXIFLSEL(v)                BM_UARTDBG_IFLS_RXIFLSEL
+#define BF_UARTDBG_IFLS_RXIFLSEL_V(e)               BF_UARTDBG_IFLS_RXIFLSEL(BV_UARTDBG_IFLS_RXIFLSEL__##e)
+#define BFM_UARTDBG_IFLS_RXIFLSEL_V(v)              BM_UARTDBG_IFLS_RXIFLSEL
+#define BP_UARTDBG_IFLS_TXIFLSEL                    0
+#define BM_UARTDBG_IFLS_TXIFLSEL                    0x7
+#define BV_UARTDBG_IFLS_TXIFLSEL__EMPTY             0x0
+#define BV_UARTDBG_IFLS_TXIFLSEL__ONE_QUARTER       0x1
+#define BV_UARTDBG_IFLS_TXIFLSEL__ONE_HALF          0x2
+#define BV_UARTDBG_IFLS_TXIFLSEL__THREE_QUARTERS    0x3
+#define BV_UARTDBG_IFLS_TXIFLSEL__SEVEN_EIGHTHS     0x4
+#define BV_UARTDBG_IFLS_TXIFLSEL__INVALID5          0x5
+#define BV_UARTDBG_IFLS_TXIFLSEL__INVALID6          0x6
+#define BV_UARTDBG_IFLS_TXIFLSEL__INVALID7          0x7
+#define BF_UARTDBG_IFLS_TXIFLSEL(v)                 (((v) & 0x7) << 0)
+#define BFM_UARTDBG_IFLS_TXIFLSEL(v)                BM_UARTDBG_IFLS_TXIFLSEL
+#define BF_UARTDBG_IFLS_TXIFLSEL_V(e)               BF_UARTDBG_IFLS_TXIFLSEL(BV_UARTDBG_IFLS_TXIFLSEL__##e)
+#define BFM_UARTDBG_IFLS_TXIFLSEL_V(v)              BM_UARTDBG_IFLS_TXIFLSEL
+
+#define HW_UARTDBG_IMSC                     HW(UARTDBG_IMSC)
+#define HWA_UARTDBG_IMSC                    (0x80070000 + 0x38)
+#define HWT_UARTDBG_IMSC                    HWIO_32_RW
+#define HWN_UARTDBG_IMSC                    UARTDBG_IMSC
+#define HWI_UARTDBG_IMSC                    
+#define BP_UARTDBG_IMSC_UNAVAILABLE         16
+#define BM_UARTDBG_IMSC_UNAVAILABLE         0xffff0000
+#define BF_UARTDBG_IMSC_UNAVAILABLE(v)      (((v) & 0xffff) << 16)
+#define BFM_UARTDBG_IMSC_UNAVAILABLE(v)     BM_UARTDBG_IMSC_UNAVAILABLE
+#define BF_UARTDBG_IMSC_UNAVAILABLE_V(e)    BF_UARTDBG_IMSC_UNAVAILABLE(BV_UARTDBG_IMSC_UNAVAILABLE__##e)
+#define BFM_UARTDBG_IMSC_UNAVAILABLE_V(v)   BM_UARTDBG_IMSC_UNAVAILABLE
+#define BP_UARTDBG_IMSC_RESERVED            11
+#define BM_UARTDBG_IMSC_RESERVED            0xf800
+#define BF_UARTDBG_IMSC_RESERVED(v)         (((v) & 0x1f) << 11)
+#define BFM_UARTDBG_IMSC_RESERVED(v)        BM_UARTDBG_IMSC_RESERVED
+#define BF_UARTDBG_IMSC_RESERVED_V(e)       BF_UARTDBG_IMSC_RESERVED(BV_UARTDBG_IMSC_RESERVED__##e)
+#define BFM_UARTDBG_IMSC_RESERVED_V(v)      BM_UARTDBG_IMSC_RESERVED
+#define BP_UARTDBG_IMSC_OEIM                10
+#define BM_UARTDBG_IMSC_OEIM                0x400
+#define BF_UARTDBG_IMSC_OEIM(v)             (((v) & 0x1) << 10)
+#define BFM_UARTDBG_IMSC_OEIM(v)            BM_UARTDBG_IMSC_OEIM
+#define BF_UARTDBG_IMSC_OEIM_V(e)           BF_UARTDBG_IMSC_OEIM(BV_UARTDBG_IMSC_OEIM__##e)
+#define BFM_UARTDBG_IMSC_OEIM_V(v)          BM_UARTDBG_IMSC_OEIM
+#define BP_UARTDBG_IMSC_BEIM                9
+#define BM_UARTDBG_IMSC_BEIM                0x200
+#define BF_UARTDBG_IMSC_BEIM(v)             (((v) & 0x1) << 9)
+#define BFM_UARTDBG_IMSC_BEIM(v)            BM_UARTDBG_IMSC_BEIM
+#define BF_UARTDBG_IMSC_BEIM_V(e)           BF_UARTDBG_IMSC_BEIM(BV_UARTDBG_IMSC_BEIM__##e)
+#define BFM_UARTDBG_IMSC_BEIM_V(v)          BM_UARTDBG_IMSC_BEIM
+#define BP_UARTDBG_IMSC_PEIM                8
+#define BM_UARTDBG_IMSC_PEIM                0x100
+#define BF_UARTDBG_IMSC_PEIM(v)             (((v) & 0x1) << 8)
+#define BFM_UARTDBG_IMSC_PEIM(v)            BM_UARTDBG_IMSC_PEIM
+#define BF_UARTDBG_IMSC_PEIM_V(e)           BF_UARTDBG_IMSC_PEIM(BV_UARTDBG_IMSC_PEIM__##e)
+#define BFM_UARTDBG_IMSC_PEIM_V(v)          BM_UARTDBG_IMSC_PEIM
+#define BP_UARTDBG_IMSC_FEIM                7
+#define BM_UARTDBG_IMSC_FEIM                0x80
+#define BF_UARTDBG_IMSC_FEIM(v)             (((v) & 0x1) << 7)
+#define BFM_UARTDBG_IMSC_FEIM(v)            BM_UARTDBG_IMSC_FEIM
+#define BF_UARTDBG_IMSC_FEIM_V(e)           BF_UARTDBG_IMSC_FEIM(BV_UARTDBG_IMSC_FEIM__##e)
+#define BFM_UARTDBG_IMSC_FEIM_V(v)          BM_UARTDBG_IMSC_FEIM
+#define BP_UARTDBG_IMSC_RTIM                6
+#define BM_UARTDBG_IMSC_RTIM                0x40
+#define BF_UARTDBG_IMSC_RTIM(v)             (((v) & 0x1) << 6)
+#define BFM_UARTDBG_IMSC_RTIM(v)            BM_UARTDBG_IMSC_RTIM
+#define BF_UARTDBG_IMSC_RTIM_V(e)           BF_UARTDBG_IMSC_RTIM(BV_UARTDBG_IMSC_RTIM__##e)
+#define BFM_UARTDBG_IMSC_RTIM_V(v)          BM_UARTDBG_IMSC_RTIM
+#define BP_UARTDBG_IMSC_TXIM                5
+#define BM_UARTDBG_IMSC_TXIM                0x20
+#define BF_UARTDBG_IMSC_TXIM(v)             (((v) & 0x1) << 5)
+#define BFM_UARTDBG_IMSC_TXIM(v)            BM_UARTDBG_IMSC_TXIM
+#define BF_UARTDBG_IMSC_TXIM_V(e)           BF_UARTDBG_IMSC_TXIM(BV_UARTDBG_IMSC_TXIM__##e)
+#define BFM_UARTDBG_IMSC_TXIM_V(v)          BM_UARTDBG_IMSC_TXIM
+#define BP_UARTDBG_IMSC_RXIM                4
+#define BM_UARTDBG_IMSC_RXIM                0x10
+#define BF_UARTDBG_IMSC_RXIM(v)             (((v) & 0x1) << 4)
+#define BFM_UARTDBG_IMSC_RXIM(v)            BM_UARTDBG_IMSC_RXIM
+#define BF_UARTDBG_IMSC_RXIM_V(e)           BF_UARTDBG_IMSC_RXIM(BV_UARTDBG_IMSC_RXIM__##e)
+#define BFM_UARTDBG_IMSC_RXIM_V(v)          BM_UARTDBG_IMSC_RXIM
+#define BP_UARTDBG_IMSC_DSRMIM              3
+#define BM_UARTDBG_IMSC_DSRMIM              0x8
+#define BF_UARTDBG_IMSC_DSRMIM(v)           (((v) & 0x1) << 3)
+#define BFM_UARTDBG_IMSC_DSRMIM(v)          BM_UARTDBG_IMSC_DSRMIM
+#define BF_UARTDBG_IMSC_DSRMIM_V(e)         BF_UARTDBG_IMSC_DSRMIM(BV_UARTDBG_IMSC_DSRMIM__##e)
+#define BFM_UARTDBG_IMSC_DSRMIM_V(v)        BM_UARTDBG_IMSC_DSRMIM
+#define BP_UARTDBG_IMSC_DCDMIM              2
+#define BM_UARTDBG_IMSC_DCDMIM              0x4
+#define BF_UARTDBG_IMSC_DCDMIM(v)           (((v) & 0x1) << 2)
+#define BFM_UARTDBG_IMSC_DCDMIM(v)          BM_UARTDBG_IMSC_DCDMIM
+#define BF_UARTDBG_IMSC_DCDMIM_V(e)         BF_UARTDBG_IMSC_DCDMIM(BV_UARTDBG_IMSC_DCDMIM__##e)
+#define BFM_UARTDBG_IMSC_DCDMIM_V(v)        BM_UARTDBG_IMSC_DCDMIM
+#define BP_UARTDBG_IMSC_CTSMIM              1
+#define BM_UARTDBG_IMSC_CTSMIM              0x2
+#define BF_UARTDBG_IMSC_CTSMIM(v)           (((v) & 0x1) << 1)
+#define BFM_UARTDBG_IMSC_CTSMIM(v)          BM_UARTDBG_IMSC_CTSMIM
+#define BF_UARTDBG_IMSC_CTSMIM_V(e)         BF_UARTDBG_IMSC_CTSMIM(BV_UARTDBG_IMSC_CTSMIM__##e)
+#define BFM_UARTDBG_IMSC_CTSMIM_V(v)        BM_UARTDBG_IMSC_CTSMIM
+#define BP_UARTDBG_IMSC_RIMIM               0
+#define BM_UARTDBG_IMSC_RIMIM               0x1
+#define BF_UARTDBG_IMSC_RIMIM(v)            (((v) & 0x1) << 0)
+#define BFM_UARTDBG_IMSC_RIMIM(v)           BM_UARTDBG_IMSC_RIMIM
+#define BF_UARTDBG_IMSC_RIMIM_V(e)          BF_UARTDBG_IMSC_RIMIM(BV_UARTDBG_IMSC_RIMIM__##e)
+#define BFM_UARTDBG_IMSC_RIMIM_V(v)         BM_UARTDBG_IMSC_RIMIM
+
+#define HW_UARTDBG_RIS                      HW(UARTDBG_RIS)
+#define HWA_UARTDBG_RIS                     (0x80070000 + 0x3c)
+#define HWT_UARTDBG_RIS                     HWIO_32_RW
+#define HWN_UARTDBG_RIS                     UARTDBG_RIS
+#define HWI_UARTDBG_RIS                     
+#define BP_UARTDBG_RIS_UNAVAILABLE          16
+#define BM_UARTDBG_RIS_UNAVAILABLE          0xffff0000
+#define BF_UARTDBG_RIS_UNAVAILABLE(v)       (((v) & 0xffff) << 16)
+#define BFM_UARTDBG_RIS_UNAVAILABLE(v)      BM_UARTDBG_RIS_UNAVAILABLE
+#define BF_UARTDBG_RIS_UNAVAILABLE_V(e)     BF_UARTDBG_RIS_UNAVAILABLE(BV_UARTDBG_RIS_UNAVAILABLE__##e)
+#define BFM_UARTDBG_RIS_UNAVAILABLE_V(v)    BM_UARTDBG_RIS_UNAVAILABLE
+#define BP_UARTDBG_RIS_RESERVED             11
+#define BM_UARTDBG_RIS_RESERVED             0xf800
+#define BF_UARTDBG_RIS_RESERVED(v)          (((v) & 0x1f) << 11)
+#define BFM_UARTDBG_RIS_RESERVED(v)         BM_UARTDBG_RIS_RESERVED
+#define BF_UARTDBG_RIS_RESERVED_V(e)        BF_UARTDBG_RIS_RESERVED(BV_UARTDBG_RIS_RESERVED__##e)
+#define BFM_UARTDBG_RIS_RESERVED_V(v)       BM_UARTDBG_RIS_RESERVED
+#define BP_UARTDBG_RIS_OERIS                10
+#define BM_UARTDBG_RIS_OERIS                0x400
+#define BF_UARTDBG_RIS_OERIS(v)             (((v) & 0x1) << 10)
+#define BFM_UARTDBG_RIS_OERIS(v)            BM_UARTDBG_RIS_OERIS
+#define BF_UARTDBG_RIS_OERIS_V(e)           BF_UARTDBG_RIS_OERIS(BV_UARTDBG_RIS_OERIS__##e)
+#define BFM_UARTDBG_RIS_OERIS_V(v)          BM_UARTDBG_RIS_OERIS
+#define BP_UARTDBG_RIS_BERIS                9
+#define BM_UARTDBG_RIS_BERIS                0x200
+#define BF_UARTDBG_RIS_BERIS(v)             (((v) & 0x1) << 9)
+#define BFM_UARTDBG_RIS_BERIS(v)            BM_UARTDBG_RIS_BERIS
+#define BF_UARTDBG_RIS_BERIS_V(e)           BF_UARTDBG_RIS_BERIS(BV_UARTDBG_RIS_BERIS__##e)
+#define BFM_UARTDBG_RIS_BERIS_V(v)          BM_UARTDBG_RIS_BERIS
+#define BP_UARTDBG_RIS_PERIS                8
+#define BM_UARTDBG_RIS_PERIS                0x100
+#define BF_UARTDBG_RIS_PERIS(v)             (((v) & 0x1) << 8)
+#define BFM_UARTDBG_RIS_PERIS(v)            BM_UARTDBG_RIS_PERIS
+#define BF_UARTDBG_RIS_PERIS_V(e)           BF_UARTDBG_RIS_PERIS(BV_UARTDBG_RIS_PERIS__##e)
+#define BFM_UARTDBG_RIS_PERIS_V(v)          BM_UARTDBG_RIS_PERIS
+#define BP_UARTDBG_RIS_FERIS                7
+#define BM_UARTDBG_RIS_FERIS                0x80
+#define BF_UARTDBG_RIS_FERIS(v)             (((v) & 0x1) << 7)
+#define BFM_UARTDBG_RIS_FERIS(v)            BM_UARTDBG_RIS_FERIS
+#define BF_UARTDBG_RIS_FERIS_V(e)           BF_UARTDBG_RIS_FERIS(BV_UARTDBG_RIS_FERIS__##e)
+#define BFM_UARTDBG_RIS_FERIS_V(v)          BM_UARTDBG_RIS_FERIS
+#define BP_UARTDBG_RIS_RTRIS                6
+#define BM_UARTDBG_RIS_RTRIS                0x40
+#define BF_UARTDBG_RIS_RTRIS(v)             (((v) & 0x1) << 6)
+#define BFM_UARTDBG_RIS_RTRIS(v)            BM_UARTDBG_RIS_RTRIS
+#define BF_UARTDBG_RIS_RTRIS_V(e)           BF_UARTDBG_RIS_RTRIS(BV_UARTDBG_RIS_RTRIS__##e)
+#define BFM_UARTDBG_RIS_RTRIS_V(v)          BM_UARTDBG_RIS_RTRIS
+#define BP_UARTDBG_RIS_TXRIS                5
+#define BM_UARTDBG_RIS_TXRIS                0x20
+#define BF_UARTDBG_RIS_TXRIS(v)             (((v) & 0x1) << 5)
+#define BFM_UARTDBG_RIS_TXRIS(v)            BM_UARTDBG_RIS_TXRIS
+#define BF_UARTDBG_RIS_TXRIS_V(e)           BF_UARTDBG_RIS_TXRIS(BV_UARTDBG_RIS_TXRIS__##e)
+#define BFM_UARTDBG_RIS_TXRIS_V(v)          BM_UARTDBG_RIS_TXRIS
+#define BP_UARTDBG_RIS_RXRIS                4
+#define BM_UARTDBG_RIS_RXRIS                0x10
+#define BF_UARTDBG_RIS_RXRIS(v)             (((v) & 0x1) << 4)
+#define BFM_UARTDBG_RIS_RXRIS(v)            BM_UARTDBG_RIS_RXRIS
+#define BF_UARTDBG_RIS_RXRIS_V(e)           BF_UARTDBG_RIS_RXRIS(BV_UARTDBG_RIS_RXRIS__##e)
+#define BFM_UARTDBG_RIS_RXRIS_V(v)          BM_UARTDBG_RIS_RXRIS
+#define BP_UARTDBG_RIS_DSRRMIS              3
+#define BM_UARTDBG_RIS_DSRRMIS              0x8
+#define BF_UARTDBG_RIS_DSRRMIS(v)           (((v) & 0x1) << 3)
+#define BFM_UARTDBG_RIS_DSRRMIS(v)          BM_UARTDBG_RIS_DSRRMIS
+#define BF_UARTDBG_RIS_DSRRMIS_V(e)         BF_UARTDBG_RIS_DSRRMIS(BV_UARTDBG_RIS_DSRRMIS__##e)
+#define BFM_UARTDBG_RIS_DSRRMIS_V(v)        BM_UARTDBG_RIS_DSRRMIS
+#define BP_UARTDBG_RIS_DCDRMIS              2
+#define BM_UARTDBG_RIS_DCDRMIS              0x4
+#define BF_UARTDBG_RIS_DCDRMIS(v)           (((v) & 0x1) << 2)
+#define BFM_UARTDBG_RIS_DCDRMIS(v)          BM_UARTDBG_RIS_DCDRMIS
+#define BF_UARTDBG_RIS_DCDRMIS_V(e)         BF_UARTDBG_RIS_DCDRMIS(BV_UARTDBG_RIS_DCDRMIS__##e)
+#define BFM_UARTDBG_RIS_DCDRMIS_V(v)        BM_UARTDBG_RIS_DCDRMIS
+#define BP_UARTDBG_RIS_CTSRMIS              1
+#define BM_UARTDBG_RIS_CTSRMIS              0x2
+#define BF_UARTDBG_RIS_CTSRMIS(v)           (((v) & 0x1) << 1)
+#define BFM_UARTDBG_RIS_CTSRMIS(v)          BM_UARTDBG_RIS_CTSRMIS
+#define BF_UARTDBG_RIS_CTSRMIS_V(e)         BF_UARTDBG_RIS_CTSRMIS(BV_UARTDBG_RIS_CTSRMIS__##e)
+#define BFM_UARTDBG_RIS_CTSRMIS_V(v)        BM_UARTDBG_RIS_CTSRMIS
+#define BP_UARTDBG_RIS_RIRMIS               0
+#define BM_UARTDBG_RIS_RIRMIS               0x1
+#define BF_UARTDBG_RIS_RIRMIS(v)            (((v) & 0x1) << 0)
+#define BFM_UARTDBG_RIS_RIRMIS(v)           BM_UARTDBG_RIS_RIRMIS
+#define BF_UARTDBG_RIS_RIRMIS_V(e)          BF_UARTDBG_RIS_RIRMIS(BV_UARTDBG_RIS_RIRMIS__##e)
+#define BFM_UARTDBG_RIS_RIRMIS_V(v)         BM_UARTDBG_RIS_RIRMIS
+
+#define HW_UARTDBG_MIS                      HW(UARTDBG_MIS)
+#define HWA_UARTDBG_MIS                     (0x80070000 + 0x40)
+#define HWT_UARTDBG_MIS                     HWIO_32_RW
+#define HWN_UARTDBG_MIS                     UARTDBG_MIS
+#define HWI_UARTDBG_MIS                     
+#define BP_UARTDBG_MIS_UNAVAILABLE          16
+#define BM_UARTDBG_MIS_UNAVAILABLE          0xffff0000
+#define BF_UARTDBG_MIS_UNAVAILABLE(v)       (((v) & 0xffff) << 16)
+#define BFM_UARTDBG_MIS_UNAVAILABLE(v)      BM_UARTDBG_MIS_UNAVAILABLE
+#define BF_UARTDBG_MIS_UNAVAILABLE_V(e)     BF_UARTDBG_MIS_UNAVAILABLE(BV_UARTDBG_MIS_UNAVAILABLE__##e)
+#define BFM_UARTDBG_MIS_UNAVAILABLE_V(v)    BM_UARTDBG_MIS_UNAVAILABLE
+#define BP_UARTDBG_MIS_RESERVED             11
+#define BM_UARTDBG_MIS_RESERVED             0xf800
+#define BF_UARTDBG_MIS_RESERVED(v)          (((v) & 0x1f) << 11)
+#define BFM_UARTDBG_MIS_RESERVED(v)         BM_UARTDBG_MIS_RESERVED
+#define BF_UARTDBG_MIS_RESERVED_V(e)        BF_UARTDBG_MIS_RESERVED(BV_UARTDBG_MIS_RESERVED__##e)
+#define BFM_UARTDBG_MIS_RESERVED_V(v)       BM_UARTDBG_MIS_RESERVED
+#define BP_UARTDBG_MIS_OEMIS                10
+#define BM_UARTDBG_MIS_OEMIS                0x400
+#define BF_UARTDBG_MIS_OEMIS(v)             (((v) & 0x1) << 10)
+#define BFM_UARTDBG_MIS_OEMIS(v)            BM_UARTDBG_MIS_OEMIS
+#define BF_UARTDBG_MIS_OEMIS_V(e)           BF_UARTDBG_MIS_OEMIS(BV_UARTDBG_MIS_OEMIS__##e)
+#define BFM_UARTDBG_MIS_OEMIS_V(v)          BM_UARTDBG_MIS_OEMIS
+#define BP_UARTDBG_MIS_BEMIS                9
+#define BM_UARTDBG_MIS_BEMIS                0x200
+#define BF_UARTDBG_MIS_BEMIS(v)             (((v) & 0x1) << 9)
+#define BFM_UARTDBG_MIS_BEMIS(v)            BM_UARTDBG_MIS_BEMIS
+#define BF_UARTDBG_MIS_BEMIS_V(e)           BF_UARTDBG_MIS_BEMIS(BV_UARTDBG_MIS_BEMIS__##e)
+#define BFM_UARTDBG_MIS_BEMIS_V(v)          BM_UARTDBG_MIS_BEMIS
+#define BP_UARTDBG_MIS_PEMIS                8
+#define BM_UARTDBG_MIS_PEMIS                0x100
+#define BF_UARTDBG_MIS_PEMIS(v)             (((v) & 0x1) << 8)
+#define BFM_UARTDBG_MIS_PEMIS(v)            BM_UARTDBG_MIS_PEMIS
+#define BF_UARTDBG_MIS_PEMIS_V(e)           BF_UARTDBG_MIS_PEMIS(BV_UARTDBG_MIS_PEMIS__##e)
+#define BFM_UARTDBG_MIS_PEMIS_V(v)          BM_UARTDBG_MIS_PEMIS
+#define BP_UARTDBG_MIS_FEMIS                7
+#define BM_UARTDBG_MIS_FEMIS                0x80
+#define BF_UARTDBG_MIS_FEMIS(v)             (((v) & 0x1) << 7)
+#define BFM_UARTDBG_MIS_FEMIS(v)            BM_UARTDBG_MIS_FEMIS
+#define BF_UARTDBG_MIS_FEMIS_V(e)           BF_UARTDBG_MIS_FEMIS(BV_UARTDBG_MIS_FEMIS__##e)
+#define BFM_UARTDBG_MIS_FEMIS_V(v)          BM_UARTDBG_MIS_FEMIS
+#define BP_UARTDBG_MIS_RTMIS                6
+#define BM_UARTDBG_MIS_RTMIS                0x40
+#define BF_UARTDBG_MIS_RTMIS(v)             (((v) & 0x1) << 6)
+#define BFM_UARTDBG_MIS_RTMIS(v)            BM_UARTDBG_MIS_RTMIS
+#define BF_UARTDBG_MIS_RTMIS_V(e)           BF_UARTDBG_MIS_RTMIS(BV_UARTDBG_MIS_RTMIS__##e)
+#define BFM_UARTDBG_MIS_RTMIS_V(v)          BM_UARTDBG_MIS_RTMIS
+#define BP_UARTDBG_MIS_TXMIS                5
+#define BM_UARTDBG_MIS_TXMIS                0x20
+#define BF_UARTDBG_MIS_TXMIS(v)             (((v) & 0x1) << 5)
+#define BFM_UARTDBG_MIS_TXMIS(v)            BM_UARTDBG_MIS_TXMIS
+#define BF_UARTDBG_MIS_TXMIS_V(e)           BF_UARTDBG_MIS_TXMIS(BV_UARTDBG_MIS_TXMIS__##e)
+#define BFM_UARTDBG_MIS_TXMIS_V(v)          BM_UARTDBG_MIS_TXMIS
+#define BP_UARTDBG_MIS_RXMIS                4
+#define BM_UARTDBG_MIS_RXMIS                0x10
+#define BF_UARTDBG_MIS_RXMIS(v)             (((v) & 0x1) << 4)
+#define BFM_UARTDBG_MIS_RXMIS(v)            BM_UARTDBG_MIS_RXMIS
+#define BF_UARTDBG_MIS_RXMIS_V(e)           BF_UARTDBG_MIS_RXMIS(BV_UARTDBG_MIS_RXMIS__##e)
+#define BFM_UARTDBG_MIS_RXMIS_V(v)          BM_UARTDBG_MIS_RXMIS
+#define BP_UARTDBG_MIS_DSRMMIS              3
+#define BM_UARTDBG_MIS_DSRMMIS              0x8
+#define BF_UARTDBG_MIS_DSRMMIS(v)           (((v) & 0x1) << 3)
+#define BFM_UARTDBG_MIS_DSRMMIS(v)          BM_UARTDBG_MIS_DSRMMIS
+#define BF_UARTDBG_MIS_DSRMMIS_V(e)         BF_UARTDBG_MIS_DSRMMIS(BV_UARTDBG_MIS_DSRMMIS__##e)
+#define BFM_UARTDBG_MIS_DSRMMIS_V(v)        BM_UARTDBG_MIS_DSRMMIS
+#define BP_UARTDBG_MIS_DCDMMIS              2
+#define BM_UARTDBG_MIS_DCDMMIS              0x4
+#define BF_UARTDBG_MIS_DCDMMIS(v)           (((v) & 0x1) << 2)
+#define BFM_UARTDBG_MIS_DCDMMIS(v)          BM_UARTDBG_MIS_DCDMMIS
+#define BF_UARTDBG_MIS_DCDMMIS_V(e)         BF_UARTDBG_MIS_DCDMMIS(BV_UARTDBG_MIS_DCDMMIS__##e)
+#define BFM_UARTDBG_MIS_DCDMMIS_V(v)        BM_UARTDBG_MIS_DCDMMIS
+#define BP_UARTDBG_MIS_CTSMMIS              1
+#define BM_UARTDBG_MIS_CTSMMIS              0x2
+#define BF_UARTDBG_MIS_CTSMMIS(v)           (((v) & 0x1) << 1)
+#define BFM_UARTDBG_MIS_CTSMMIS(v)          BM_UARTDBG_MIS_CTSMMIS
+#define BF_UARTDBG_MIS_CTSMMIS_V(e)         BF_UARTDBG_MIS_CTSMMIS(BV_UARTDBG_MIS_CTSMMIS__##e)
+#define BFM_UARTDBG_MIS_CTSMMIS_V(v)        BM_UARTDBG_MIS_CTSMMIS
+#define BP_UARTDBG_MIS_RIMMIS               0
+#define BM_UARTDBG_MIS_RIMMIS               0x1
+#define BF_UARTDBG_MIS_RIMMIS(v)            (((v) & 0x1) << 0)
+#define BFM_UARTDBG_MIS_RIMMIS(v)           BM_UARTDBG_MIS_RIMMIS
+#define BF_UARTDBG_MIS_RIMMIS_V(e)          BF_UARTDBG_MIS_RIMMIS(BV_UARTDBG_MIS_RIMMIS__##e)
+#define BFM_UARTDBG_MIS_RIMMIS_V(v)         BM_UARTDBG_MIS_RIMMIS
+
+#define HW_UARTDBG_ICR                      HW(UARTDBG_ICR)
+#define HWA_UARTDBG_ICR                     (0x80070000 + 0x44)
+#define HWT_UARTDBG_ICR                     HWIO_32_RW
+#define HWN_UARTDBG_ICR                     UARTDBG_ICR
+#define HWI_UARTDBG_ICR                     
+#define BP_UARTDBG_ICR_UNAVAILABLE          16
+#define BM_UARTDBG_ICR_UNAVAILABLE          0xffff0000
+#define BF_UARTDBG_ICR_UNAVAILABLE(v)       (((v) & 0xffff) << 16)
+#define BFM_UARTDBG_ICR_UNAVAILABLE(v)      BM_UARTDBG_ICR_UNAVAILABLE
+#define BF_UARTDBG_ICR_UNAVAILABLE_V(e)     BF_UARTDBG_ICR_UNAVAILABLE(BV_UARTDBG_ICR_UNAVAILABLE__##e)
+#define BFM_UARTDBG_ICR_UNAVAILABLE_V(v)    BM_UARTDBG_ICR_UNAVAILABLE
+#define BP_UARTDBG_ICR_RESERVED             11
+#define BM_UARTDBG_ICR_RESERVED             0xf800
+#define BF_UARTDBG_ICR_RESERVED(v)          (((v) & 0x1f) << 11)
+#define BFM_UARTDBG_ICR_RESERVED(v)         BM_UARTDBG_ICR_RESERVED
+#define BF_UARTDBG_ICR_RESERVED_V(e)        BF_UARTDBG_ICR_RESERVED(BV_UARTDBG_ICR_RESERVED__##e)
+#define BFM_UARTDBG_ICR_RESERVED_V(v)       BM_UARTDBG_ICR_RESERVED
+#define BP_UARTDBG_ICR_OEIC                 10
+#define BM_UARTDBG_ICR_OEIC                 0x400
+#define BF_UARTDBG_ICR_OEIC(v)              (((v) & 0x1) << 10)
+#define BFM_UARTDBG_ICR_OEIC(v)             BM_UARTDBG_ICR_OEIC
+#define BF_UARTDBG_ICR_OEIC_V(e)            BF_UARTDBG_ICR_OEIC(BV_UARTDBG_ICR_OEIC__##e)
+#define BFM_UARTDBG_ICR_OEIC_V(v)           BM_UARTDBG_ICR_OEIC
+#define BP_UARTDBG_ICR_BEIC                 9
+#define BM_UARTDBG_ICR_BEIC                 0x200
+#define BF_UARTDBG_ICR_BEIC(v)              (((v) & 0x1) << 9)
+#define BFM_UARTDBG_ICR_BEIC(v)             BM_UARTDBG_ICR_BEIC
+#define BF_UARTDBG_ICR_BEIC_V(e)            BF_UARTDBG_ICR_BEIC(BV_UARTDBG_ICR_BEIC__##e)
+#define BFM_UARTDBG_ICR_BEIC_V(v)           BM_UARTDBG_ICR_BEIC
+#define BP_UARTDBG_ICR_PEIC                 8
+#define BM_UARTDBG_ICR_PEIC                 0x100
+#define BF_UARTDBG_ICR_PEIC(v)              (((v) & 0x1) << 8)
+#define BFM_UARTDBG_ICR_PEIC(v)             BM_UARTDBG_ICR_PEIC
+#define BF_UARTDBG_ICR_PEIC_V(e)            BF_UARTDBG_ICR_PEIC(BV_UARTDBG_ICR_PEIC__##e)
+#define BFM_UARTDBG_ICR_PEIC_V(v)           BM_UARTDBG_ICR_PEIC
+#define BP_UARTDBG_ICR_FEIC                 7
+#define BM_UARTDBG_ICR_FEIC                 0x80
+#define BF_UARTDBG_ICR_FEIC(v)              (((v) & 0x1) << 7)
+#define BFM_UARTDBG_ICR_FEIC(v)             BM_UARTDBG_ICR_FEIC
+#define BF_UARTDBG_ICR_FEIC_V(e)            BF_UARTDBG_ICR_FEIC(BV_UARTDBG_ICR_FEIC__##e)
+#define BFM_UARTDBG_ICR_FEIC_V(v)           BM_UARTDBG_ICR_FEIC
+#define BP_UARTDBG_ICR_RTIC                 6
+#define BM_UARTDBG_ICR_RTIC                 0x40
+#define BF_UARTDBG_ICR_RTIC(v)              (((v) & 0x1) << 6)
+#define BFM_UARTDBG_ICR_RTIC(v)             BM_UARTDBG_ICR_RTIC
+#define BF_UARTDBG_ICR_RTIC_V(e)            BF_UARTDBG_ICR_RTIC(BV_UARTDBG_ICR_RTIC__##e)
+#define BFM_UARTDBG_ICR_RTIC_V(v)           BM_UARTDBG_ICR_RTIC
+#define BP_UARTDBG_ICR_TXIC                 5
+#define BM_UARTDBG_ICR_TXIC                 0x20
+#define BF_UARTDBG_ICR_TXIC(v)              (((v) & 0x1) << 5)
+#define BFM_UARTDBG_ICR_TXIC(v)             BM_UARTDBG_ICR_TXIC
+#define BF_UARTDBG_ICR_TXIC_V(e)            BF_UARTDBG_ICR_TXIC(BV_UARTDBG_ICR_TXIC__##e)
+#define BFM_UARTDBG_ICR_TXIC_V(v)           BM_UARTDBG_ICR_TXIC
+#define BP_UARTDBG_ICR_RXIC                 4
+#define BM_UARTDBG_ICR_RXIC                 0x10
+#define BF_UARTDBG_ICR_RXIC(v)              (((v) & 0x1) << 4)
+#define BFM_UARTDBG_ICR_RXIC(v)             BM_UARTDBG_ICR_RXIC
+#define BF_UARTDBG_ICR_RXIC_V(e)            BF_UARTDBG_ICR_RXIC(BV_UARTDBG_ICR_RXIC__##e)
+#define BFM_UARTDBG_ICR_RXIC_V(v)           BM_UARTDBG_ICR_RXIC
+#define BP_UARTDBG_ICR_DSRMIC               3
+#define BM_UARTDBG_ICR_DSRMIC               0x8
+#define BF_UARTDBG_ICR_DSRMIC(v)            (((v) & 0x1) << 3)
+#define BFM_UARTDBG_ICR_DSRMIC(v)           BM_UARTDBG_ICR_DSRMIC
+#define BF_UARTDBG_ICR_DSRMIC_V(e)          BF_UARTDBG_ICR_DSRMIC(BV_UARTDBG_ICR_DSRMIC__##e)
+#define BFM_UARTDBG_ICR_DSRMIC_V(v)         BM_UARTDBG_ICR_DSRMIC
+#define BP_UARTDBG_ICR_DCDMIC               2
+#define BM_UARTDBG_ICR_DCDMIC               0x4
+#define BF_UARTDBG_ICR_DCDMIC(v)            (((v) & 0x1) << 2)
+#define BFM_UARTDBG_ICR_DCDMIC(v)           BM_UARTDBG_ICR_DCDMIC
+#define BF_UARTDBG_ICR_DCDMIC_V(e)          BF_UARTDBG_ICR_DCDMIC(BV_UARTDBG_ICR_DCDMIC__##e)
+#define BFM_UARTDBG_ICR_DCDMIC_V(v)         BM_UARTDBG_ICR_DCDMIC
+#define BP_UARTDBG_ICR_CTSMIC               1
+#define BM_UARTDBG_ICR_CTSMIC               0x2
+#define BF_UARTDBG_ICR_CTSMIC(v)            (((v) & 0x1) << 1)
+#define BFM_UARTDBG_ICR_CTSMIC(v)           BM_UARTDBG_ICR_CTSMIC
+#define BF_UARTDBG_ICR_CTSMIC_V(e)          BF_UARTDBG_ICR_CTSMIC(BV_UARTDBG_ICR_CTSMIC__##e)
+#define BFM_UARTDBG_ICR_CTSMIC_V(v)         BM_UARTDBG_ICR_CTSMIC
+#define BP_UARTDBG_ICR_RIMIC                0
+#define BM_UARTDBG_ICR_RIMIC                0x1
+#define BF_UARTDBG_ICR_RIMIC(v)             (((v) & 0x1) << 0)
+#define BFM_UARTDBG_ICR_RIMIC(v)            BM_UARTDBG_ICR_RIMIC
+#define BF_UARTDBG_ICR_RIMIC_V(e)           BF_UARTDBG_ICR_RIMIC(BV_UARTDBG_ICR_RIMIC__##e)
+#define BFM_UARTDBG_ICR_RIMIC_V(v)          BM_UARTDBG_ICR_RIMIC
+
+#define HW_UARTDBG_DMACR                    HW(UARTDBG_DMACR)
+#define HWA_UARTDBG_DMACR                   (0x80070000 + 0x48)
+#define HWT_UARTDBG_DMACR                   HWIO_32_RW
+#define HWN_UARTDBG_DMACR                   UARTDBG_DMACR
+#define HWI_UARTDBG_DMACR                   
+#define BP_UARTDBG_DMACR_UNAVAILABLE        16
+#define BM_UARTDBG_DMACR_UNAVAILABLE        0xffff0000
+#define BF_UARTDBG_DMACR_UNAVAILABLE(v)     (((v) & 0xffff) << 16)
+#define BFM_UARTDBG_DMACR_UNAVAILABLE(v)    BM_UARTDBG_DMACR_UNAVAILABLE
+#define BF_UARTDBG_DMACR_UNAVAILABLE_V(e)   BF_UARTDBG_DMACR_UNAVAILABLE(BV_UARTDBG_DMACR_UNAVAILABLE__##e)
+#define BFM_UARTDBG_DMACR_UNAVAILABLE_V(v)  BM_UARTDBG_DMACR_UNAVAILABLE
+#define BP_UARTDBG_DMACR_RESERVED           3
+#define BM_UARTDBG_DMACR_RESERVED           0xfff8
+#define BF_UARTDBG_DMACR_RESERVED(v)        (((v) & 0x1fff) << 3)
+#define BFM_UARTDBG_DMACR_RESERVED(v)       BM_UARTDBG_DMACR_RESERVED
+#define BF_UARTDBG_DMACR_RESERVED_V(e)      BF_UARTDBG_DMACR_RESERVED(BV_UARTDBG_DMACR_RESERVED__##e)
+#define BFM_UARTDBG_DMACR_RESERVED_V(v)     BM_UARTDBG_DMACR_RESERVED
+#define BP_UARTDBG_DMACR_DMAONERR           2
+#define BM_UARTDBG_DMACR_DMAONERR           0x4
+#define BF_UARTDBG_DMACR_DMAONERR(v)        (((v) & 0x1) << 2)
+#define BFM_UARTDBG_DMACR_DMAONERR(v)       BM_UARTDBG_DMACR_DMAONERR
+#define BF_UARTDBG_DMACR_DMAONERR_V(e)      BF_UARTDBG_DMACR_DMAONERR(BV_UARTDBG_DMACR_DMAONERR__##e)
+#define BFM_UARTDBG_DMACR_DMAONERR_V(v)     BM_UARTDBG_DMACR_DMAONERR
+#define BP_UARTDBG_DMACR_TXDMAE             1
+#define BM_UARTDBG_DMACR_TXDMAE             0x2
+#define BF_UARTDBG_DMACR_TXDMAE(v)          (((v) & 0x1) << 1)
+#define BFM_UARTDBG_DMACR_TXDMAE(v)         BM_UARTDBG_DMACR_TXDMAE
+#define BF_UARTDBG_DMACR_TXDMAE_V(e)        BF_UARTDBG_DMACR_TXDMAE(BV_UARTDBG_DMACR_TXDMAE__##e)
+#define BFM_UARTDBG_DMACR_TXDMAE_V(v)       BM_UARTDBG_DMACR_TXDMAE
+#define BP_UARTDBG_DMACR_RXDMAE             0
+#define BM_UARTDBG_DMACR_RXDMAE             0x1
+#define BF_UARTDBG_DMACR_RXDMAE(v)          (((v) & 0x1) << 0)
+#define BFM_UARTDBG_DMACR_RXDMAE(v)         BM_UARTDBG_DMACR_RXDMAE
+#define BF_UARTDBG_DMACR_RXDMAE_V(e)        BF_UARTDBG_DMACR_RXDMAE(BV_UARTDBG_DMACR_RXDMAE__##e)
+#define BFM_UARTDBG_DMACR_RXDMAE_V(v)       BM_UARTDBG_DMACR_RXDMAE
+
+#endif /* __HEADERGEN_IMX233_UARTDBG_H__*/
diff --git a/firmware/target/arm/imx233/regs/imx233/usbctrl.h b/firmware/target/arm/imx233/regs/imx233/usbctrl.h
new file mode 100644
index 0000000000..2d51809ceb
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/imx233/usbctrl.h
@@ -0,0 +1,2001 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * imx233 version: 2.4.0
+ * imx233 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_IMX233_USBCTRL_H__
+#define __HEADERGEN_IMX233_USBCTRL_H__
+
+#define HW_USBCTRL_ID                   HW(USBCTRL_ID)
+#define HWA_USBCTRL_ID                  (0x80080000 + 0x0)
+#define HWT_USBCTRL_ID                  HWIO_32_RW
+#define HWN_USBCTRL_ID                  USBCTRL_ID
+#define HWI_USBCTRL_ID                  
+#define BP_USBCTRL_ID_CIVERSION         29
+#define BM_USBCTRL_ID_CIVERSION         0xe0000000
+#define BF_USBCTRL_ID_CIVERSION(v)      (((v) & 0x7) << 29)
+#define BFM_USBCTRL_ID_CIVERSION(v)     BM_USBCTRL_ID_CIVERSION
+#define BF_USBCTRL_ID_CIVERSION_V(e)    BF_USBCTRL_ID_CIVERSION(BV_USBCTRL_ID_CIVERSION__##e)
+#define BFM_USBCTRL_ID_CIVERSION_V(v)   BM_USBCTRL_ID_CIVERSION
+#define BP_USBCTRL_ID_VERSION           25
+#define BM_USBCTRL_ID_VERSION           0x1e000000
+#define BF_USBCTRL_ID_VERSION(v)        (((v) & 0xf) << 25)
+#define BFM_USBCTRL_ID_VERSION(v)       BM_USBCTRL_ID_VERSION
+#define BF_USBCTRL_ID_VERSION_V(e)      BF_USBCTRL_ID_VERSION(BV_USBCTRL_ID_VERSION__##e)
+#define BFM_USBCTRL_ID_VERSION_V(v)     BM_USBCTRL_ID_VERSION
+#define BP_USBCTRL_ID_REVISION          21
+#define BM_USBCTRL_ID_REVISION          0x1e00000
+#define BF_USBCTRL_ID_REVISION(v)       (((v) & 0xf) << 21)
+#define BFM_USBCTRL_ID_REVISION(v)      BM_USBCTRL_ID_REVISION
+#define BF_USBCTRL_ID_REVISION_V(e)     BF_USBCTRL_ID_REVISION(BV_USBCTRL_ID_REVISION__##e)
+#define BFM_USBCTRL_ID_REVISION_V(v)    BM_USBCTRL_ID_REVISION
+#define BP_USBCTRL_ID_TAG               16
+#define BM_USBCTRL_ID_TAG               0x1f0000
+#define BF_USBCTRL_ID_TAG(v)            (((v) & 0x1f) << 16)
+#define BFM_USBCTRL_ID_TAG(v)           BM_USBCTRL_ID_TAG
+#define BF_USBCTRL_ID_TAG_V(e)          BF_USBCTRL_ID_TAG(BV_USBCTRL_ID_TAG__##e)
+#define BFM_USBCTRL_ID_TAG_V(v)         BM_USBCTRL_ID_TAG
+#define BP_USBCTRL_ID_RSVD1             14
+#define BM_USBCTRL_ID_RSVD1             0xc000
+#define BF_USBCTRL_ID_RSVD1(v)          (((v) & 0x3) << 14)
+#define BFM_USBCTRL_ID_RSVD1(v)         BM_USBCTRL_ID_RSVD1
+#define BF_USBCTRL_ID_RSVD1_V(e)        BF_USBCTRL_ID_RSVD1(BV_USBCTRL_ID_RSVD1__##e)
+#define BFM_USBCTRL_ID_RSVD1_V(v)       BM_USBCTRL_ID_RSVD1
+#define BP_USBCTRL_ID_NID               8
+#define BM_USBCTRL_ID_NID               0x3f00
+#define BF_USBCTRL_ID_NID(v)            (((v) & 0x3f) << 8)
+#define BFM_USBCTRL_ID_NID(v)           BM_USBCTRL_ID_NID
+#define BF_USBCTRL_ID_NID_V(e)          BF_USBCTRL_ID_NID(BV_USBCTRL_ID_NID__##e)
+#define BFM_USBCTRL_ID_NID_V(v)         BM_USBCTRL_ID_NID
+#define BP_USBCTRL_ID_RSVD0             6
+#define BM_USBCTRL_ID_RSVD0             0xc0
+#define BF_USBCTRL_ID_RSVD0(v)          (((v) & 0x3) << 6)
+#define BFM_USBCTRL_ID_RSVD0(v)         BM_USBCTRL_ID_RSVD0
+#define BF_USBCTRL_ID_RSVD0_V(e)        BF_USBCTRL_ID_RSVD0(BV_USBCTRL_ID_RSVD0__##e)
+#define BFM_USBCTRL_ID_RSVD0_V(v)       BM_USBCTRL_ID_RSVD0
+#define BP_USBCTRL_ID_ID                0
+#define BM_USBCTRL_ID_ID                0x3f
+#define BF_USBCTRL_ID_ID(v)             (((v) & 0x3f) << 0)
+#define BFM_USBCTRL_ID_ID(v)            BM_USBCTRL_ID_ID
+#define BF_USBCTRL_ID_ID_V(e)           BF_USBCTRL_ID_ID(BV_USBCTRL_ID_ID__##e)
+#define BFM_USBCTRL_ID_ID_V(v)          BM_USBCTRL_ID_ID
+
+#define HW_USBCTRL_HWGENERAL            HW(USBCTRL_HWGENERAL)
+#define HWA_USBCTRL_HWGENERAL           (0x80080000 + 0x4)
+#define HWT_USBCTRL_HWGENERAL           HWIO_32_RW
+#define HWN_USBCTRL_HWGENERAL           USBCTRL_HWGENERAL
+#define HWI_USBCTRL_HWGENERAL           
+#define BP_USBCTRL_HWGENERAL_RSVD       11
+#define BM_USBCTRL_HWGENERAL_RSVD       0xfffff800
+#define BF_USBCTRL_HWGENERAL_RSVD(v)    (((v) & 0x1fffff) << 11)
+#define BFM_USBCTRL_HWGENERAL_RSVD(v)   BM_USBCTRL_HWGENERAL_RSVD
+#define BF_USBCTRL_HWGENERAL_RSVD_V(e)  BF_USBCTRL_HWGENERAL_RSVD(BV_USBCTRL_HWGENERAL_RSVD__##e)
+#define BFM_USBCTRL_HWGENERAL_RSVD_V(v) BM_USBCTRL_HWGENERAL_RSVD
+#define BP_USBCTRL_HWGENERAL_SM         9
+#define BM_USBCTRL_HWGENERAL_SM         0x600
+#define BF_USBCTRL_HWGENERAL_SM(v)      (((v) & 0x3) << 9)
+#define BFM_USBCTRL_HWGENERAL_SM(v)     BM_USBCTRL_HWGENERAL_SM
+#define BF_USBCTRL_HWGENERAL_SM_V(e)    BF_USBCTRL_HWGENERAL_SM(BV_USBCTRL_HWGENERAL_SM__##e)
+#define BFM_USBCTRL_HWGENERAL_SM_V(v)   BM_USBCTRL_HWGENERAL_SM
+#define BP_USBCTRL_HWGENERAL_PHYM       6
+#define BM_USBCTRL_HWGENERAL_PHYM       0x1c0
+#define BF_USBCTRL_HWGENERAL_PHYM(v)    (((v) & 0x7) << 6)
+#define BFM_USBCTRL_HWGENERAL_PHYM(v)   BM_USBCTRL_HWGENERAL_PHYM
+#define BF_USBCTRL_HWGENERAL_PHYM_V(e)  BF_USBCTRL_HWGENERAL_PHYM(BV_USBCTRL_HWGENERAL_PHYM__##e)
+#define BFM_USBCTRL_HWGENERAL_PHYM_V(v) BM_USBCTRL_HWGENERAL_PHYM
+#define BP_USBCTRL_HWGENERAL_PHYW       4
+#define BM_USBCTRL_HWGENERAL_PHYW       0x30
+#define BF_USBCTRL_HWGENERAL_PHYW(v)    (((v) & 0x3) << 4)
+#define BFM_USBCTRL_HWGENERAL_PHYW(v)   BM_USBCTRL_HWGENERAL_PHYW
+#define BF_USBCTRL_HWGENERAL_PHYW_V(e)  BF_USBCTRL_HWGENERAL_PHYW(BV_USBCTRL_HWGENERAL_PHYW__##e)
+#define BFM_USBCTRL_HWGENERAL_PHYW_V(v) BM_USBCTRL_HWGENERAL_PHYW
+#define BP_USBCTRL_HWGENERAL_BWT        3
+#define BM_USBCTRL_HWGENERAL_BWT        0x8
+#define BF_USBCTRL_HWGENERAL_BWT(v)     (((v) & 0x1) << 3)
+#define BFM_USBCTRL_HWGENERAL_BWT(v)    BM_USBCTRL_HWGENERAL_BWT
+#define BF_USBCTRL_HWGENERAL_BWT_V(e)   BF_USBCTRL_HWGENERAL_BWT(BV_USBCTRL_HWGENERAL_BWT__##e)
+#define BFM_USBCTRL_HWGENERAL_BWT_V(v)  BM_USBCTRL_HWGENERAL_BWT
+#define BP_USBCTRL_HWGENERAL_CLKC       1
+#define BM_USBCTRL_HWGENERAL_CLKC       0x6
+#define BF_USBCTRL_HWGENERAL_CLKC(v)    (((v) & 0x3) << 1)
+#define BFM_USBCTRL_HWGENERAL_CLKC(v)   BM_USBCTRL_HWGENERAL_CLKC
+#define BF_USBCTRL_HWGENERAL_CLKC_V(e)  BF_USBCTRL_HWGENERAL_CLKC(BV_USBCTRL_HWGENERAL_CLKC__##e)
+#define BFM_USBCTRL_HWGENERAL_CLKC_V(v) BM_USBCTRL_HWGENERAL_CLKC
+#define BP_USBCTRL_HWGENERAL_RT         0
+#define BM_USBCTRL_HWGENERAL_RT         0x1
+#define BF_USBCTRL_HWGENERAL_RT(v)      (((v) & 0x1) << 0)
+#define BFM_USBCTRL_HWGENERAL_RT(v)     BM_USBCTRL_HWGENERAL_RT
+#define BF_USBCTRL_HWGENERAL_RT_V(e)    BF_USBCTRL_HWGENERAL_RT(BV_USBCTRL_HWGENERAL_RT__##e)
+#define BFM_USBCTRL_HWGENERAL_RT_V(v)   BM_USBCTRL_HWGENERAL_RT
+
+#define HW_USBCTRL_HWHOST               HW(USBCTRL_HWHOST)
+#define HWA_USBCTRL_HWHOST              (0x80080000 + 0x8)
+#define HWT_USBCTRL_HWHOST              HWIO_32_RW
+#define HWN_USBCTRL_HWHOST              USBCTRL_HWHOST
+#define HWI_USBCTRL_HWHOST              
+#define BP_USBCTRL_HWHOST_TTPER         24
+#define BM_USBCTRL_HWHOST_TTPER         0xff000000
+#define BF_USBCTRL_HWHOST_TTPER(v)      (((v) & 0xff) << 24)
+#define BFM_USBCTRL_HWHOST_TTPER(v)     BM_USBCTRL_HWHOST_TTPER
+#define BF_USBCTRL_HWHOST_TTPER_V(e)    BF_USBCTRL_HWHOST_TTPER(BV_USBCTRL_HWHOST_TTPER__##e)
+#define BFM_USBCTRL_HWHOST_TTPER_V(v)   BM_USBCTRL_HWHOST_TTPER
+#define BP_USBCTRL_HWHOST_TTASY         16
+#define BM_USBCTRL_HWHOST_TTASY         0xff0000
+#define BF_USBCTRL_HWHOST_TTASY(v)      (((v) & 0xff) << 16)
+#define BFM_USBCTRL_HWHOST_TTASY(v)     BM_USBCTRL_HWHOST_TTASY
+#define BF_USBCTRL_HWHOST_TTASY_V(e)    BF_USBCTRL_HWHOST_TTASY(BV_USBCTRL_HWHOST_TTASY__##e)
+#define BFM_USBCTRL_HWHOST_TTASY_V(v)   BM_USBCTRL_HWHOST_TTASY
+#define BP_USBCTRL_HWHOST_RSVD          4
+#define BM_USBCTRL_HWHOST_RSVD          0xfff0
+#define BF_USBCTRL_HWHOST_RSVD(v)       (((v) & 0xfff) << 4)
+#define BFM_USBCTRL_HWHOST_RSVD(v)      BM_USBCTRL_HWHOST_RSVD
+#define BF_USBCTRL_HWHOST_RSVD_V(e)     BF_USBCTRL_HWHOST_RSVD(BV_USBCTRL_HWHOST_RSVD__##e)
+#define BFM_USBCTRL_HWHOST_RSVD_V(v)    BM_USBCTRL_HWHOST_RSVD
+#define BP_USBCTRL_HWHOST_NPORT         1
+#define BM_USBCTRL_HWHOST_NPORT         0xe
+#define BF_USBCTRL_HWHOST_NPORT(v)      (((v) & 0x7) << 1)
+#define BFM_USBCTRL_HWHOST_NPORT(v)     BM_USBCTRL_HWHOST_NPORT
+#define BF_USBCTRL_HWHOST_NPORT_V(e)    BF_USBCTRL_HWHOST_NPORT(BV_USBCTRL_HWHOST_NPORT__##e)
+#define BFM_USBCTRL_HWHOST_NPORT_V(v)   BM_USBCTRL_HWHOST_NPORT
+#define BP_USBCTRL_HWHOST_HC            0
+#define BM_USBCTRL_HWHOST_HC            0x1
+#define BF_USBCTRL_HWHOST_HC(v)         (((v) & 0x1) << 0)
+#define BFM_USBCTRL_HWHOST_HC(v)        BM_USBCTRL_HWHOST_HC
+#define BF_USBCTRL_HWHOST_HC_V(e)       BF_USBCTRL_HWHOST_HC(BV_USBCTRL_HWHOST_HC__##e)
+#define BFM_USBCTRL_HWHOST_HC_V(v)      BM_USBCTRL_HWHOST_HC
+
+#define HW_USBCTRL_HWDEVICE             HW(USBCTRL_HWDEVICE)
+#define HWA_USBCTRL_HWDEVICE            (0x80080000 + 0xc)
+#define HWT_USBCTRL_HWDEVICE            HWIO_32_RW
+#define HWN_USBCTRL_HWDEVICE            USBCTRL_HWDEVICE
+#define HWI_USBCTRL_HWDEVICE            
+#define BP_USBCTRL_HWDEVICE_RSVD        6
+#define BM_USBCTRL_HWDEVICE_RSVD        0xffffffc0
+#define BF_USBCTRL_HWDEVICE_RSVD(v)     (((v) & 0x3ffffff) << 6)
+#define BFM_USBCTRL_HWDEVICE_RSVD(v)    BM_USBCTRL_HWDEVICE_RSVD
+#define BF_USBCTRL_HWDEVICE_RSVD_V(e)   BF_USBCTRL_HWDEVICE_RSVD(BV_USBCTRL_HWDEVICE_RSVD__##e)
+#define BFM_USBCTRL_HWDEVICE_RSVD_V(v)  BM_USBCTRL_HWDEVICE_RSVD
+#define BP_USBCTRL_HWDEVICE_DEVEP       1
+#define BM_USBCTRL_HWDEVICE_DEVEP       0x3e
+#define BF_USBCTRL_HWDEVICE_DEVEP(v)    (((v) & 0x1f) << 1)
+#define BFM_USBCTRL_HWDEVICE_DEVEP(v)   BM_USBCTRL_HWDEVICE_DEVEP
+#define BF_USBCTRL_HWDEVICE_DEVEP_V(e)  BF_USBCTRL_HWDEVICE_DEVEP(BV_USBCTRL_HWDEVICE_DEVEP__##e)
+#define BFM_USBCTRL_HWDEVICE_DEVEP_V(v) BM_USBCTRL_HWDEVICE_DEVEP
+#define BP_USBCTRL_HWDEVICE_DC          0
+#define BM_USBCTRL_HWDEVICE_DC          0x1
+#define BF_USBCTRL_HWDEVICE_DC(v)       (((v) & 0x1) << 0)
+#define BFM_USBCTRL_HWDEVICE_DC(v)      BM_USBCTRL_HWDEVICE_DC
+#define BF_USBCTRL_HWDEVICE_DC_V(e)     BF_USBCTRL_HWDEVICE_DC(BV_USBCTRL_HWDEVICE_DC__##e)
+#define BFM_USBCTRL_HWDEVICE_DC_V(v)    BM_USBCTRL_HWDEVICE_DC
+
+#define HW_USBCTRL_HWTXBUF                  HW(USBCTRL_HWTXBUF)
+#define HWA_USBCTRL_HWTXBUF                 (0x80080000 + 0x10)
+#define HWT_USBCTRL_HWTXBUF                 HWIO_32_RW
+#define HWN_USBCTRL_HWTXBUF                 USBCTRL_HWTXBUF
+#define HWI_USBCTRL_HWTXBUF                 
+#define BP_USBCTRL_HWTXBUF_TXLCR            31
+#define BM_USBCTRL_HWTXBUF_TXLCR            0x80000000
+#define BF_USBCTRL_HWTXBUF_TXLCR(v)         (((v) & 0x1) << 31)
+#define BFM_USBCTRL_HWTXBUF_TXLCR(v)        BM_USBCTRL_HWTXBUF_TXLCR
+#define BF_USBCTRL_HWTXBUF_TXLCR_V(e)       BF_USBCTRL_HWTXBUF_TXLCR(BV_USBCTRL_HWTXBUF_TXLCR__##e)
+#define BFM_USBCTRL_HWTXBUF_TXLCR_V(v)      BM_USBCTRL_HWTXBUF_TXLCR
+#define BP_USBCTRL_HWTXBUF_RSVD             24
+#define BM_USBCTRL_HWTXBUF_RSVD             0x7f000000
+#define BF_USBCTRL_HWTXBUF_RSVD(v)          (((v) & 0x7f) << 24)
+#define BFM_USBCTRL_HWTXBUF_RSVD(v)         BM_USBCTRL_HWTXBUF_RSVD
+#define BF_USBCTRL_HWTXBUF_RSVD_V(e)        BF_USBCTRL_HWTXBUF_RSVD(BV_USBCTRL_HWTXBUF_RSVD__##e)
+#define BFM_USBCTRL_HWTXBUF_RSVD_V(v)       BM_USBCTRL_HWTXBUF_RSVD
+#define BP_USBCTRL_HWTXBUF_TXCHANADD        16
+#define BM_USBCTRL_HWTXBUF_TXCHANADD        0xff0000
+#define BF_USBCTRL_HWTXBUF_TXCHANADD(v)     (((v) & 0xff) << 16)
+#define BFM_USBCTRL_HWTXBUF_TXCHANADD(v)    BM_USBCTRL_HWTXBUF_TXCHANADD
+#define BF_USBCTRL_HWTXBUF_TXCHANADD_V(e)   BF_USBCTRL_HWTXBUF_TXCHANADD(BV_USBCTRL_HWTXBUF_TXCHANADD__##e)
+#define BFM_USBCTRL_HWTXBUF_TXCHANADD_V(v)  BM_USBCTRL_HWTXBUF_TXCHANADD
+#define BP_USBCTRL_HWTXBUF_TXADD            8
+#define BM_USBCTRL_HWTXBUF_TXADD            0xff00
+#define BF_USBCTRL_HWTXBUF_TXADD(v)         (((v) & 0xff) << 8)
+#define BFM_USBCTRL_HWTXBUF_TXADD(v)        BM_USBCTRL_HWTXBUF_TXADD
+#define BF_USBCTRL_HWTXBUF_TXADD_V(e)       BF_USBCTRL_HWTXBUF_TXADD(BV_USBCTRL_HWTXBUF_TXADD__##e)
+#define BFM_USBCTRL_HWTXBUF_TXADD_V(v)      BM_USBCTRL_HWTXBUF_TXADD
+#define BP_USBCTRL_HWTXBUF_TXBURST          0
+#define BM_USBCTRL_HWTXBUF_TXBURST          0xff
+#define BF_USBCTRL_HWTXBUF_TXBURST(v)       (((v) & 0xff) << 0)
+#define BFM_USBCTRL_HWTXBUF_TXBURST(v)      BM_USBCTRL_HWTXBUF_TXBURST
+#define BF_USBCTRL_HWTXBUF_TXBURST_V(e)     BF_USBCTRL_HWTXBUF_TXBURST(BV_USBCTRL_HWTXBUF_TXBURST__##e)
+#define BFM_USBCTRL_HWTXBUF_TXBURST_V(v)    BM_USBCTRL_HWTXBUF_TXBURST
+
+#define HW_USBCTRL_HWRXBUF                  HW(USBCTRL_HWRXBUF)
+#define HWA_USBCTRL_HWRXBUF                 (0x80080000 + 0x14)
+#define HWT_USBCTRL_HWRXBUF                 HWIO_32_RW
+#define HWN_USBCTRL_HWRXBUF                 USBCTRL_HWRXBUF
+#define HWI_USBCTRL_HWRXBUF                 
+#define BP_USBCTRL_HWRXBUF_RSVD             16
+#define BM_USBCTRL_HWRXBUF_RSVD             0xffff0000
+#define BF_USBCTRL_HWRXBUF_RSVD(v)          (((v) & 0xffff) << 16)
+#define BFM_USBCTRL_HWRXBUF_RSVD(v)         BM_USBCTRL_HWRXBUF_RSVD
+#define BF_USBCTRL_HWRXBUF_RSVD_V(e)        BF_USBCTRL_HWRXBUF_RSVD(BV_USBCTRL_HWRXBUF_RSVD__##e)
+#define BFM_USBCTRL_HWRXBUF_RSVD_V(v)       BM_USBCTRL_HWRXBUF_RSVD
+#define BP_USBCTRL_HWRXBUF_RXADD            8
+#define BM_USBCTRL_HWRXBUF_RXADD            0xff00
+#define BF_USBCTRL_HWRXBUF_RXADD(v)         (((v) & 0xff) << 8)
+#define BFM_USBCTRL_HWRXBUF_RXADD(v)        BM_USBCTRL_HWRXBUF_RXADD
+#define BF_USBCTRL_HWRXBUF_RXADD_V(e)       BF_USBCTRL_HWRXBUF_RXADD(BV_USBCTRL_HWRXBUF_RXADD__##e)
+#define BFM_USBCTRL_HWRXBUF_RXADD_V(v)      BM_USBCTRL_HWRXBUF_RXADD
+#define BP_USBCTRL_HWRXBUF_RXBURST          0
+#define BM_USBCTRL_HWRXBUF_RXBURST          0xff
+#define BF_USBCTRL_HWRXBUF_RXBURST(v)       (((v) & 0xff) << 0)
+#define BFM_USBCTRL_HWRXBUF_RXBURST(v)      BM_USBCTRL_HWRXBUF_RXBURST
+#define BF_USBCTRL_HWRXBUF_RXBURST_V(e)     BF_USBCTRL_HWRXBUF_RXBURST(BV_USBCTRL_HWRXBUF_RXBURST__##e)
+#define BFM_USBCTRL_HWRXBUF_RXBURST_V(v)    BM_USBCTRL_HWRXBUF_RXBURST
+
+#define HW_USBCTRL_GPTIMER0LD               HW(USBCTRL_GPTIMER0LD)
+#define HWA_USBCTRL_GPTIMER0LD              (0x80080000 + 0x80)
+#define HWT_USBCTRL_GPTIMER0LD              HWIO_32_RW
+#define HWN_USBCTRL_GPTIMER0LD              USBCTRL_GPTIMER0LD
+#define HWI_USBCTRL_GPTIMER0LD              
+#define BP_USBCTRL_GPTIMER0LD_RSVD0         24
+#define BM_USBCTRL_GPTIMER0LD_RSVD0         0xff000000
+#define BF_USBCTRL_GPTIMER0LD_RSVD0(v)      (((v) & 0xff) << 24)
+#define BFM_USBCTRL_GPTIMER0LD_RSVD0(v)     BM_USBCTRL_GPTIMER0LD_RSVD0
+#define BF_USBCTRL_GPTIMER0LD_RSVD0_V(e)    BF_USBCTRL_GPTIMER0LD_RSVD0(BV_USBCTRL_GPTIMER0LD_RSVD0__##e)
+#define BFM_USBCTRL_GPTIMER0LD_RSVD0_V(v)   BM_USBCTRL_GPTIMER0LD_RSVD0
+#define BP_USBCTRL_GPTIMER0LD_GPTLD         0
+#define BM_USBCTRL_GPTIMER0LD_GPTLD         0xffffff
+#define BF_USBCTRL_GPTIMER0LD_GPTLD(v)      (((v) & 0xffffff) << 0)
+#define BFM_USBCTRL_GPTIMER0LD_GPTLD(v)     BM_USBCTRL_GPTIMER0LD_GPTLD
+#define BF_USBCTRL_GPTIMER0LD_GPTLD_V(e)    BF_USBCTRL_GPTIMER0LD_GPTLD(BV_USBCTRL_GPTIMER0LD_GPTLD__##e)
+#define BFM_USBCTRL_GPTIMER0LD_GPTLD_V(v)   BM_USBCTRL_GPTIMER0LD_GPTLD
+
+#define HW_USBCTRL_GPTIMER0CTRL                     HW(USBCTRL_GPTIMER0CTRL)
+#define HWA_USBCTRL_GPTIMER0CTRL                    (0x80080000 + 0x84)
+#define HWT_USBCTRL_GPTIMER0CTRL                    HWIO_32_RW
+#define HWN_USBCTRL_GPTIMER0CTRL                    USBCTRL_GPTIMER0CTRL
+#define HWI_USBCTRL_GPTIMER0CTRL                    
+#define BP_USBCTRL_GPTIMER0CTRL_GPTRUN              31
+#define BM_USBCTRL_GPTIMER0CTRL_GPTRUN              0x80000000
+#define BV_USBCTRL_GPTIMER0CTRL_GPTRUN__STOP        0x0
+#define BV_USBCTRL_GPTIMER0CTRL_GPTRUN__RUN         0x1
+#define BF_USBCTRL_GPTIMER0CTRL_GPTRUN(v)           (((v) & 0x1) << 31)
+#define BFM_USBCTRL_GPTIMER0CTRL_GPTRUN(v)          BM_USBCTRL_GPTIMER0CTRL_GPTRUN
+#define BF_USBCTRL_GPTIMER0CTRL_GPTRUN_V(e)         BF_USBCTRL_GPTIMER0CTRL_GPTRUN(BV_USBCTRL_GPTIMER0CTRL_GPTRUN__##e)
+#define BFM_USBCTRL_GPTIMER0CTRL_GPTRUN_V(v)        BM_USBCTRL_GPTIMER0CTRL_GPTRUN
+#define BP_USBCTRL_GPTIMER0CTRL_GPTRST              30
+#define BM_USBCTRL_GPTIMER0CTRL_GPTRST              0x40000000
+#define BV_USBCTRL_GPTIMER0CTRL_GPTRST__NOACTION    0x0
+#define BV_USBCTRL_GPTIMER0CTRL_GPTRST__LOADCOUNTER 0x1
+#define BF_USBCTRL_GPTIMER0CTRL_GPTRST(v)           (((v) & 0x1) << 30)
+#define BFM_USBCTRL_GPTIMER0CTRL_GPTRST(v)          BM_USBCTRL_GPTIMER0CTRL_GPTRST
+#define BF_USBCTRL_GPTIMER0CTRL_GPTRST_V(e)         BF_USBCTRL_GPTIMER0CTRL_GPTRST(BV_USBCTRL_GPTIMER0CTRL_GPTRST__##e)
+#define BFM_USBCTRL_GPTIMER0CTRL_GPTRST_V(v)        BM_USBCTRL_GPTIMER0CTRL_GPTRST
+#define BP_USBCTRL_GPTIMER0CTRL_RSVD0               25
+#define BM_USBCTRL_GPTIMER0CTRL_RSVD0               0x3e000000
+#define BF_USBCTRL_GPTIMER0CTRL_RSVD0(v)            (((v) & 0x1f) << 25)
+#define BFM_USBCTRL_GPTIMER0CTRL_RSVD0(v)           BM_USBCTRL_GPTIMER0CTRL_RSVD0
+#define BF_USBCTRL_GPTIMER0CTRL_RSVD0_V(e)          BF_USBCTRL_GPTIMER0CTRL_RSVD0(BV_USBCTRL_GPTIMER0CTRL_RSVD0__##e)
+#define BFM_USBCTRL_GPTIMER0CTRL_RSVD0_V(v)         BM_USBCTRL_GPTIMER0CTRL_RSVD0
+#define BP_USBCTRL_GPTIMER0CTRL_GPTMODE             24
+#define BM_USBCTRL_GPTIMER0CTRL_GPTMODE             0x1000000
+#define BV_USBCTRL_GPTIMER0CTRL_GPTMODE__ONESHOT    0x0
+#define BV_USBCTRL_GPTIMER0CTRL_GPTMODE__REPEAT     0x1
+#define BF_USBCTRL_GPTIMER0CTRL_GPTMODE(v)          (((v) & 0x1) << 24)
+#define BFM_USBCTRL_GPTIMER0CTRL_GPTMODE(v)         BM_USBCTRL_GPTIMER0CTRL_GPTMODE
+#define BF_USBCTRL_GPTIMER0CTRL_GPTMODE_V(e)        BF_USBCTRL_GPTIMER0CTRL_GPTMODE(BV_USBCTRL_GPTIMER0CTRL_GPTMODE__##e)
+#define BFM_USBCTRL_GPTIMER0CTRL_GPTMODE_V(v)       BM_USBCTRL_GPTIMER0CTRL_GPTMODE
+#define BP_USBCTRL_GPTIMER0CTRL_GPTCNT              0
+#define BM_USBCTRL_GPTIMER0CTRL_GPTCNT              0xffffff
+#define BF_USBCTRL_GPTIMER0CTRL_GPTCNT(v)           (((v) & 0xffffff) << 0)
+#define BFM_USBCTRL_GPTIMER0CTRL_GPTCNT(v)          BM_USBCTRL_GPTIMER0CTRL_GPTCNT
+#define BF_USBCTRL_GPTIMER0CTRL_GPTCNT_V(e)         BF_USBCTRL_GPTIMER0CTRL_GPTCNT(BV_USBCTRL_GPTIMER0CTRL_GPTCNT__##e)
+#define BFM_USBCTRL_GPTIMER0CTRL_GPTCNT_V(v)        BM_USBCTRL_GPTIMER0CTRL_GPTCNT
+
+#define HW_USBCTRL_GPTIMER1LD               HW(USBCTRL_GPTIMER1LD)
+#define HWA_USBCTRL_GPTIMER1LD              (0x80080000 + 0x88)
+#define HWT_USBCTRL_GPTIMER1LD              HWIO_32_RW
+#define HWN_USBCTRL_GPTIMER1LD              USBCTRL_GPTIMER1LD
+#define HWI_USBCTRL_GPTIMER1LD              
+#define BP_USBCTRL_GPTIMER1LD_RSVD0         24
+#define BM_USBCTRL_GPTIMER1LD_RSVD0         0xff000000
+#define BF_USBCTRL_GPTIMER1LD_RSVD0(v)      (((v) & 0xff) << 24)
+#define BFM_USBCTRL_GPTIMER1LD_RSVD0(v)     BM_USBCTRL_GPTIMER1LD_RSVD0
+#define BF_USBCTRL_GPTIMER1LD_RSVD0_V(e)    BF_USBCTRL_GPTIMER1LD_RSVD0(BV_USBCTRL_GPTIMER1LD_RSVD0__##e)
+#define BFM_USBCTRL_GPTIMER1LD_RSVD0_V(v)   BM_USBCTRL_GPTIMER1LD_RSVD0
+#define BP_USBCTRL_GPTIMER1LD_GPTLD         0
+#define BM_USBCTRL_GPTIMER1LD_GPTLD         0xffffff
+#define BF_USBCTRL_GPTIMER1LD_GPTLD(v)      (((v) & 0xffffff) << 0)
+#define BFM_USBCTRL_GPTIMER1LD_GPTLD(v)     BM_USBCTRL_GPTIMER1LD_GPTLD
+#define BF_USBCTRL_GPTIMER1LD_GPTLD_V(e)    BF_USBCTRL_GPTIMER1LD_GPTLD(BV_USBCTRL_GPTIMER1LD_GPTLD__##e)
+#define BFM_USBCTRL_GPTIMER1LD_GPTLD_V(v)   BM_USBCTRL_GPTIMER1LD_GPTLD
+
+#define HW_USBCTRL_GPTIMER1CTRL                     HW(USBCTRL_GPTIMER1CTRL)
+#define HWA_USBCTRL_GPTIMER1CTRL                    (0x80080000 + 0x8c)
+#define HWT_USBCTRL_GPTIMER1CTRL                    HWIO_32_RW
+#define HWN_USBCTRL_GPTIMER1CTRL                    USBCTRL_GPTIMER1CTRL
+#define HWI_USBCTRL_GPTIMER1CTRL                    
+#define BP_USBCTRL_GPTIMER1CTRL_GPTRUN              31
+#define BM_USBCTRL_GPTIMER1CTRL_GPTRUN              0x80000000
+#define BV_USBCTRL_GPTIMER1CTRL_GPTRUN__STOP        0x0
+#define BV_USBCTRL_GPTIMER1CTRL_GPTRUN__RUN         0x1
+#define BF_USBCTRL_GPTIMER1CTRL_GPTRUN(v)           (((v) & 0x1) << 31)
+#define BFM_USBCTRL_GPTIMER1CTRL_GPTRUN(v)          BM_USBCTRL_GPTIMER1CTRL_GPTRUN
+#define BF_USBCTRL_GPTIMER1CTRL_GPTRUN_V(e)         BF_USBCTRL_GPTIMER1CTRL_GPTRUN(BV_USBCTRL_GPTIMER1CTRL_GPTRUN__##e)
+#define BFM_USBCTRL_GPTIMER1CTRL_GPTRUN_V(v)        BM_USBCTRL_GPTIMER1CTRL_GPTRUN
+#define BP_USBCTRL_GPTIMER1CTRL_GPTRST              30
+#define BM_USBCTRL_GPTIMER1CTRL_GPTRST              0x40000000
+#define BV_USBCTRL_GPTIMER1CTRL_GPTRST__NOACTION    0x0
+#define BV_USBCTRL_GPTIMER1CTRL_GPTRST__LOADCOUNTER 0x1
+#define BF_USBCTRL_GPTIMER1CTRL_GPTRST(v)           (((v) & 0x1) << 30)
+#define BFM_USBCTRL_GPTIMER1CTRL_GPTRST(v)          BM_USBCTRL_GPTIMER1CTRL_GPTRST
+#define BF_USBCTRL_GPTIMER1CTRL_GPTRST_V(e)         BF_USBCTRL_GPTIMER1CTRL_GPTRST(BV_USBCTRL_GPTIMER1CTRL_GPTRST__##e)
+#define BFM_USBCTRL_GPTIMER1CTRL_GPTRST_V(v)        BM_USBCTRL_GPTIMER1CTRL_GPTRST
+#define BP_USBCTRL_GPTIMER1CTRL_RSVD0               25
+#define BM_USBCTRL_GPTIMER1CTRL_RSVD0               0x3e000000
+#define BF_USBCTRL_GPTIMER1CTRL_RSVD0(v)            (((v) & 0x1f) << 25)
+#define BFM_USBCTRL_GPTIMER1CTRL_RSVD0(v)           BM_USBCTRL_GPTIMER1CTRL_RSVD0
+#define BF_USBCTRL_GPTIMER1CTRL_RSVD0_V(e)          BF_USBCTRL_GPTIMER1CTRL_RSVD0(BV_USBCTRL_GPTIMER1CTRL_RSVD0__##e)
+#define BFM_USBCTRL_GPTIMER1CTRL_RSVD0_V(v)         BM_USBCTRL_GPTIMER1CTRL_RSVD0
+#define BP_USBCTRL_GPTIMER1CTRL_GPTMODE             24
+#define BM_USBCTRL_GPTIMER1CTRL_GPTMODE             0x1000000
+#define BV_USBCTRL_GPTIMER1CTRL_GPTMODE__ONESHOT    0x0
+#define BV_USBCTRL_GPTIMER1CTRL_GPTMODE__REPEAT     0x1
+#define BF_USBCTRL_GPTIMER1CTRL_GPTMODE(v)          (((v) & 0x1) << 24)
+#define BFM_USBCTRL_GPTIMER1CTRL_GPTMODE(v)         BM_USBCTRL_GPTIMER1CTRL_GPTMODE
+#define BF_USBCTRL_GPTIMER1CTRL_GPTMODE_V(e)        BF_USBCTRL_GPTIMER1CTRL_GPTMODE(BV_USBCTRL_GPTIMER1CTRL_GPTMODE__##e)
+#define BFM_USBCTRL_GPTIMER1CTRL_GPTMODE_V(v)       BM_USBCTRL_GPTIMER1CTRL_GPTMODE
+#define BP_USBCTRL_GPTIMER1CTRL_GPTCNT              0
+#define BM_USBCTRL_GPTIMER1CTRL_GPTCNT              0xffffff
+#define BF_USBCTRL_GPTIMER1CTRL_GPTCNT(v)           (((v) & 0xffffff) << 0)
+#define BFM_USBCTRL_GPTIMER1CTRL_GPTCNT(v)          BM_USBCTRL_GPTIMER1CTRL_GPTCNT
+#define BF_USBCTRL_GPTIMER1CTRL_GPTCNT_V(e)         BF_USBCTRL_GPTIMER1CTRL_GPTCNT(BV_USBCTRL_GPTIMER1CTRL_GPTCNT__##e)
+#define BFM_USBCTRL_GPTIMER1CTRL_GPTCNT_V(v)        BM_USBCTRL_GPTIMER1CTRL_GPTCNT
+
+#define HW_USBCTRL_SBUSCFG                      HW(USBCTRL_SBUSCFG)
+#define HWA_USBCTRL_SBUSCFG                     (0x80080000 + 0x90)
+#define HWT_USBCTRL_SBUSCFG                     HWIO_32_RW
+#define HWN_USBCTRL_SBUSCFG                     USBCTRL_SBUSCFG
+#define HWI_USBCTRL_SBUSCFG                     
+#define BP_USBCTRL_SBUSCFG_RSVD                 3
+#define BM_USBCTRL_SBUSCFG_RSVD                 0xfffffff8
+#define BF_USBCTRL_SBUSCFG_RSVD(v)              (((v) & 0x1fffffff) << 3)
+#define BFM_USBCTRL_SBUSCFG_RSVD(v)             BM_USBCTRL_SBUSCFG_RSVD
+#define BF_USBCTRL_SBUSCFG_RSVD_V(e)            BF_USBCTRL_SBUSCFG_RSVD(BV_USBCTRL_SBUSCFG_RSVD__##e)
+#define BFM_USBCTRL_SBUSCFG_RSVD_V(v)           BM_USBCTRL_SBUSCFG_RSVD
+#define BP_USBCTRL_SBUSCFG_AHBBRST              0
+#define BM_USBCTRL_SBUSCFG_AHBBRST              0x7
+#define BV_USBCTRL_SBUSCFG_AHBBRST__U_INCR      0x0
+#define BV_USBCTRL_SBUSCFG_AHBBRST__S_INCR4     0x1
+#define BV_USBCTRL_SBUSCFG_AHBBRST__S_INCR8     0x2
+#define BV_USBCTRL_SBUSCFG_AHBBRST__S_INCR16    0x3
+#define BV_USBCTRL_SBUSCFG_AHBBRST__RESERVED    0x4
+#define BV_USBCTRL_SBUSCFG_AHBBRST__U_INCR4     0x5
+#define BV_USBCTRL_SBUSCFG_AHBBRST__U_INCR8     0x6
+#define BV_USBCTRL_SBUSCFG_AHBBRST__U_INCR16    0x7
+#define BF_USBCTRL_SBUSCFG_AHBBRST(v)           (((v) & 0x7) << 0)
+#define BFM_USBCTRL_SBUSCFG_AHBBRST(v)          BM_USBCTRL_SBUSCFG_AHBBRST
+#define BF_USBCTRL_SBUSCFG_AHBBRST_V(e)         BF_USBCTRL_SBUSCFG_AHBBRST(BV_USBCTRL_SBUSCFG_AHBBRST__##e)
+#define BFM_USBCTRL_SBUSCFG_AHBBRST_V(v)        BM_USBCTRL_SBUSCFG_AHBBRST
+
+#define HW_USBCTRL_CAPLENGTH                    HW(USBCTRL_CAPLENGTH)
+#define HWA_USBCTRL_CAPLENGTH                   (0x80080000 + 0x100)
+#define HWT_USBCTRL_CAPLENGTH                   HWIO_32_RW
+#define HWN_USBCTRL_CAPLENGTH                   USBCTRL_CAPLENGTH
+#define HWI_USBCTRL_CAPLENGTH                   
+#define BP_USBCTRL_CAPLENGTH_HCIVERSION         16
+#define BM_USBCTRL_CAPLENGTH_HCIVERSION         0xffff0000
+#define BF_USBCTRL_CAPLENGTH_HCIVERSION(v)      (((v) & 0xffff) << 16)
+#define BFM_USBCTRL_CAPLENGTH_HCIVERSION(v)     BM_USBCTRL_CAPLENGTH_HCIVERSION
+#define BF_USBCTRL_CAPLENGTH_HCIVERSION_V(e)    BF_USBCTRL_CAPLENGTH_HCIVERSION(BV_USBCTRL_CAPLENGTH_HCIVERSION__##e)
+#define BFM_USBCTRL_CAPLENGTH_HCIVERSION_V(v)   BM_USBCTRL_CAPLENGTH_HCIVERSION
+#define BP_USBCTRL_CAPLENGTH_RSVD               8
+#define BM_USBCTRL_CAPLENGTH_RSVD               0xff00
+#define BF_USBCTRL_CAPLENGTH_RSVD(v)            (((v) & 0xff) << 8)
+#define BFM_USBCTRL_CAPLENGTH_RSVD(v)           BM_USBCTRL_CAPLENGTH_RSVD
+#define BF_USBCTRL_CAPLENGTH_RSVD_V(e)          BF_USBCTRL_CAPLENGTH_RSVD(BV_USBCTRL_CAPLENGTH_RSVD__##e)
+#define BFM_USBCTRL_CAPLENGTH_RSVD_V(v)         BM_USBCTRL_CAPLENGTH_RSVD
+#define BP_USBCTRL_CAPLENGTH_CAPLENGTH          0
+#define BM_USBCTRL_CAPLENGTH_CAPLENGTH          0xff
+#define BF_USBCTRL_CAPLENGTH_CAPLENGTH(v)       (((v) & 0xff) << 0)
+#define BFM_USBCTRL_CAPLENGTH_CAPLENGTH(v)      BM_USBCTRL_CAPLENGTH_CAPLENGTH
+#define BF_USBCTRL_CAPLENGTH_CAPLENGTH_V(e)     BF_USBCTRL_CAPLENGTH_CAPLENGTH(BV_USBCTRL_CAPLENGTH_CAPLENGTH__##e)
+#define BFM_USBCTRL_CAPLENGTH_CAPLENGTH_V(v)    BM_USBCTRL_CAPLENGTH_CAPLENGTH
+
+#define HW_USBCTRL_HCSPARAMS                HW(USBCTRL_HCSPARAMS)
+#define HWA_USBCTRL_HCSPARAMS               (0x80080000 + 0x104)
+#define HWT_USBCTRL_HCSPARAMS               HWIO_32_RW
+#define HWN_USBCTRL_HCSPARAMS               USBCTRL_HCSPARAMS
+#define HWI_USBCTRL_HCSPARAMS               
+#define BP_USBCTRL_HCSPARAMS_RSVD2          28
+#define BM_USBCTRL_HCSPARAMS_RSVD2          0xf0000000
+#define BF_USBCTRL_HCSPARAMS_RSVD2(v)       (((v) & 0xf) << 28)
+#define BFM_USBCTRL_HCSPARAMS_RSVD2(v)      BM_USBCTRL_HCSPARAMS_RSVD2
+#define BF_USBCTRL_HCSPARAMS_RSVD2_V(e)     BF_USBCTRL_HCSPARAMS_RSVD2(BV_USBCTRL_HCSPARAMS_RSVD2__##e)
+#define BFM_USBCTRL_HCSPARAMS_RSVD2_V(v)    BM_USBCTRL_HCSPARAMS_RSVD2
+#define BP_USBCTRL_HCSPARAMS_N_TT           24
+#define BM_USBCTRL_HCSPARAMS_N_TT           0xf000000
+#define BF_USBCTRL_HCSPARAMS_N_TT(v)        (((v) & 0xf) << 24)
+#define BFM_USBCTRL_HCSPARAMS_N_TT(v)       BM_USBCTRL_HCSPARAMS_N_TT
+#define BF_USBCTRL_HCSPARAMS_N_TT_V(e)      BF_USBCTRL_HCSPARAMS_N_TT(BV_USBCTRL_HCSPARAMS_N_TT__##e)
+#define BFM_USBCTRL_HCSPARAMS_N_TT_V(v)     BM_USBCTRL_HCSPARAMS_N_TT
+#define BP_USBCTRL_HCSPARAMS_N_PTT          20
+#define BM_USBCTRL_HCSPARAMS_N_PTT          0xf00000
+#define BF_USBCTRL_HCSPARAMS_N_PTT(v)       (((v) & 0xf) << 20)
+#define BFM_USBCTRL_HCSPARAMS_N_PTT(v)      BM_USBCTRL_HCSPARAMS_N_PTT
+#define BF_USBCTRL_HCSPARAMS_N_PTT_V(e)     BF_USBCTRL_HCSPARAMS_N_PTT(BV_USBCTRL_HCSPARAMS_N_PTT__##e)
+#define BFM_USBCTRL_HCSPARAMS_N_PTT_V(v)    BM_USBCTRL_HCSPARAMS_N_PTT
+#define BP_USBCTRL_HCSPARAMS_RSVD1          17
+#define BM_USBCTRL_HCSPARAMS_RSVD1          0xe0000
+#define BF_USBCTRL_HCSPARAMS_RSVD1(v)       (((v) & 0x7) << 17)
+#define BFM_USBCTRL_HCSPARAMS_RSVD1(v)      BM_USBCTRL_HCSPARAMS_RSVD1
+#define BF_USBCTRL_HCSPARAMS_RSVD1_V(e)     BF_USBCTRL_HCSPARAMS_RSVD1(BV_USBCTRL_HCSPARAMS_RSVD1__##e)
+#define BFM_USBCTRL_HCSPARAMS_RSVD1_V(v)    BM_USBCTRL_HCSPARAMS_RSVD1
+#define BP_USBCTRL_HCSPARAMS_PI             16
+#define BM_USBCTRL_HCSPARAMS_PI             0x10000
+#define BF_USBCTRL_HCSPARAMS_PI(v)          (((v) & 0x1) << 16)
+#define BFM_USBCTRL_HCSPARAMS_PI(v)         BM_USBCTRL_HCSPARAMS_PI
+#define BF_USBCTRL_HCSPARAMS_PI_V(e)        BF_USBCTRL_HCSPARAMS_PI(BV_USBCTRL_HCSPARAMS_PI__##e)
+#define BFM_USBCTRL_HCSPARAMS_PI_V(v)       BM_USBCTRL_HCSPARAMS_PI
+#define BP_USBCTRL_HCSPARAMS_N_CC           12
+#define BM_USBCTRL_HCSPARAMS_N_CC           0xf000
+#define BF_USBCTRL_HCSPARAMS_N_CC(v)        (((v) & 0xf) << 12)
+#define BFM_USBCTRL_HCSPARAMS_N_CC(v)       BM_USBCTRL_HCSPARAMS_N_CC
+#define BF_USBCTRL_HCSPARAMS_N_CC_V(e)      BF_USBCTRL_HCSPARAMS_N_CC(BV_USBCTRL_HCSPARAMS_N_CC__##e)
+#define BFM_USBCTRL_HCSPARAMS_N_CC_V(v)     BM_USBCTRL_HCSPARAMS_N_CC
+#define BP_USBCTRL_HCSPARAMS_N_PCC          8
+#define BM_USBCTRL_HCSPARAMS_N_PCC          0xf00
+#define BF_USBCTRL_HCSPARAMS_N_PCC(v)       (((v) & 0xf) << 8)
+#define BFM_USBCTRL_HCSPARAMS_N_PCC(v)      BM_USBCTRL_HCSPARAMS_N_PCC
+#define BF_USBCTRL_HCSPARAMS_N_PCC_V(e)     BF_USBCTRL_HCSPARAMS_N_PCC(BV_USBCTRL_HCSPARAMS_N_PCC__##e)
+#define BFM_USBCTRL_HCSPARAMS_N_PCC_V(v)    BM_USBCTRL_HCSPARAMS_N_PCC
+#define BP_USBCTRL_HCSPARAMS_RSVD0          5
+#define BM_USBCTRL_HCSPARAMS_RSVD0          0xe0
+#define BF_USBCTRL_HCSPARAMS_RSVD0(v)       (((v) & 0x7) << 5)
+#define BFM_USBCTRL_HCSPARAMS_RSVD0(v)      BM_USBCTRL_HCSPARAMS_RSVD0
+#define BF_USBCTRL_HCSPARAMS_RSVD0_V(e)     BF_USBCTRL_HCSPARAMS_RSVD0(BV_USBCTRL_HCSPARAMS_RSVD0__##e)
+#define BFM_USBCTRL_HCSPARAMS_RSVD0_V(v)    BM_USBCTRL_HCSPARAMS_RSVD0
+#define BP_USBCTRL_HCSPARAMS_PPC            4
+#define BM_USBCTRL_HCSPARAMS_PPC            0x10
+#define BF_USBCTRL_HCSPARAMS_PPC(v)         (((v) & 0x1) << 4)
+#define BFM_USBCTRL_HCSPARAMS_PPC(v)        BM_USBCTRL_HCSPARAMS_PPC
+#define BF_USBCTRL_HCSPARAMS_PPC_V(e)       BF_USBCTRL_HCSPARAMS_PPC(BV_USBCTRL_HCSPARAMS_PPC__##e)
+#define BFM_USBCTRL_HCSPARAMS_PPC_V(v)      BM_USBCTRL_HCSPARAMS_PPC
+#define BP_USBCTRL_HCSPARAMS_N_PORTS        0
+#define BM_USBCTRL_HCSPARAMS_N_PORTS        0xf
+#define BF_USBCTRL_HCSPARAMS_N_PORTS(v)     (((v) & 0xf) << 0)
+#define BFM_USBCTRL_HCSPARAMS_N_PORTS(v)    BM_USBCTRL_HCSPARAMS_N_PORTS
+#define BF_USBCTRL_HCSPARAMS_N_PORTS_V(e)   BF_USBCTRL_HCSPARAMS_N_PORTS(BV_USBCTRL_HCSPARAMS_N_PORTS__##e)
+#define BFM_USBCTRL_HCSPARAMS_N_PORTS_V(v)  BM_USBCTRL_HCSPARAMS_N_PORTS
+
+#define HW_USBCTRL_HCCPARAMS                HW(USBCTRL_HCCPARAMS)
+#define HWA_USBCTRL_HCCPARAMS               (0x80080000 + 0x108)
+#define HWT_USBCTRL_HCCPARAMS               HWIO_32_RW
+#define HWN_USBCTRL_HCCPARAMS               USBCTRL_HCCPARAMS
+#define HWI_USBCTRL_HCCPARAMS               
+#define BP_USBCTRL_HCCPARAMS_RSVD2          16
+#define BM_USBCTRL_HCCPARAMS_RSVD2          0xffff0000
+#define BF_USBCTRL_HCCPARAMS_RSVD2(v)       (((v) & 0xffff) << 16)
+#define BFM_USBCTRL_HCCPARAMS_RSVD2(v)      BM_USBCTRL_HCCPARAMS_RSVD2
+#define BF_USBCTRL_HCCPARAMS_RSVD2_V(e)     BF_USBCTRL_HCCPARAMS_RSVD2(BV_USBCTRL_HCCPARAMS_RSVD2__##e)
+#define BFM_USBCTRL_HCCPARAMS_RSVD2_V(v)    BM_USBCTRL_HCCPARAMS_RSVD2
+#define BP_USBCTRL_HCCPARAMS_EECP           8
+#define BM_USBCTRL_HCCPARAMS_EECP           0xff00
+#define BF_USBCTRL_HCCPARAMS_EECP(v)        (((v) & 0xff) << 8)
+#define BFM_USBCTRL_HCCPARAMS_EECP(v)       BM_USBCTRL_HCCPARAMS_EECP
+#define BF_USBCTRL_HCCPARAMS_EECP_V(e)      BF_USBCTRL_HCCPARAMS_EECP(BV_USBCTRL_HCCPARAMS_EECP__##e)
+#define BFM_USBCTRL_HCCPARAMS_EECP_V(v)     BM_USBCTRL_HCCPARAMS_EECP
+#define BP_USBCTRL_HCCPARAMS_IST            4
+#define BM_USBCTRL_HCCPARAMS_IST            0xf0
+#define BF_USBCTRL_HCCPARAMS_IST(v)         (((v) & 0xf) << 4)
+#define BFM_USBCTRL_HCCPARAMS_IST(v)        BM_USBCTRL_HCCPARAMS_IST
+#define BF_USBCTRL_HCCPARAMS_IST_V(e)       BF_USBCTRL_HCCPARAMS_IST(BV_USBCTRL_HCCPARAMS_IST__##e)
+#define BFM_USBCTRL_HCCPARAMS_IST_V(v)      BM_USBCTRL_HCCPARAMS_IST
+#define BP_USBCTRL_HCCPARAMS_RSVD0          3
+#define BM_USBCTRL_HCCPARAMS_RSVD0          0x8
+#define BF_USBCTRL_HCCPARAMS_RSVD0(v)       (((v) & 0x1) << 3)
+#define BFM_USBCTRL_HCCPARAMS_RSVD0(v)      BM_USBCTRL_HCCPARAMS_RSVD0
+#define BF_USBCTRL_HCCPARAMS_RSVD0_V(e)     BF_USBCTRL_HCCPARAMS_RSVD0(BV_USBCTRL_HCCPARAMS_RSVD0__##e)
+#define BFM_USBCTRL_HCCPARAMS_RSVD0_V(v)    BM_USBCTRL_HCCPARAMS_RSVD0
+#define BP_USBCTRL_HCCPARAMS_ASP            2
+#define BM_USBCTRL_HCCPARAMS_ASP            0x4
+#define BF_USBCTRL_HCCPARAMS_ASP(v)         (((v) & 0x1) << 2)
+#define BFM_USBCTRL_HCCPARAMS_ASP(v)        BM_USBCTRL_HCCPARAMS_ASP
+#define BF_USBCTRL_HCCPARAMS_ASP_V(e)       BF_USBCTRL_HCCPARAMS_ASP(BV_USBCTRL_HCCPARAMS_ASP__##e)
+#define BFM_USBCTRL_HCCPARAMS_ASP_V(v)      BM_USBCTRL_HCCPARAMS_ASP
+#define BP_USBCTRL_HCCPARAMS_PFL            1
+#define BM_USBCTRL_HCCPARAMS_PFL            0x2
+#define BF_USBCTRL_HCCPARAMS_PFL(v)         (((v) & 0x1) << 1)
+#define BFM_USBCTRL_HCCPARAMS_PFL(v)        BM_USBCTRL_HCCPARAMS_PFL
+#define BF_USBCTRL_HCCPARAMS_PFL_V(e)       BF_USBCTRL_HCCPARAMS_PFL(BV_USBCTRL_HCCPARAMS_PFL__##e)
+#define BFM_USBCTRL_HCCPARAMS_PFL_V(v)      BM_USBCTRL_HCCPARAMS_PFL
+#define BP_USBCTRL_HCCPARAMS_ADC            0
+#define BM_USBCTRL_HCCPARAMS_ADC            0x1
+#define BF_USBCTRL_HCCPARAMS_ADC(v)         (((v) & 0x1) << 0)
+#define BFM_USBCTRL_HCCPARAMS_ADC(v)        BM_USBCTRL_HCCPARAMS_ADC
+#define BF_USBCTRL_HCCPARAMS_ADC_V(e)       BF_USBCTRL_HCCPARAMS_ADC(BV_USBCTRL_HCCPARAMS_ADC__##e)
+#define BFM_USBCTRL_HCCPARAMS_ADC_V(v)      BM_USBCTRL_HCCPARAMS_ADC
+
+#define HW_USBCTRL_DCIVERSION                   HW(USBCTRL_DCIVERSION)
+#define HWA_USBCTRL_DCIVERSION                  (0x80080000 + 0x120)
+#define HWT_USBCTRL_DCIVERSION                  HWIO_32_RW
+#define HWN_USBCTRL_DCIVERSION                  USBCTRL_DCIVERSION
+#define HWI_USBCTRL_DCIVERSION                  
+#define BP_USBCTRL_DCIVERSION_RSVD              16
+#define BM_USBCTRL_DCIVERSION_RSVD              0xffff0000
+#define BF_USBCTRL_DCIVERSION_RSVD(v)           (((v) & 0xffff) << 16)
+#define BFM_USBCTRL_DCIVERSION_RSVD(v)          BM_USBCTRL_DCIVERSION_RSVD
+#define BF_USBCTRL_DCIVERSION_RSVD_V(e)         BF_USBCTRL_DCIVERSION_RSVD(BV_USBCTRL_DCIVERSION_RSVD__##e)
+#define BFM_USBCTRL_DCIVERSION_RSVD_V(v)        BM_USBCTRL_DCIVERSION_RSVD
+#define BP_USBCTRL_DCIVERSION_DCIVERSION        0
+#define BM_USBCTRL_DCIVERSION_DCIVERSION        0xffff
+#define BF_USBCTRL_DCIVERSION_DCIVERSION(v)     (((v) & 0xffff) << 0)
+#define BFM_USBCTRL_DCIVERSION_DCIVERSION(v)    BM_USBCTRL_DCIVERSION_DCIVERSION
+#define BF_USBCTRL_DCIVERSION_DCIVERSION_V(e)   BF_USBCTRL_DCIVERSION_DCIVERSION(BV_USBCTRL_DCIVERSION_DCIVERSION__##e)
+#define BFM_USBCTRL_DCIVERSION_DCIVERSION_V(v)  BM_USBCTRL_DCIVERSION_DCIVERSION
+
+#define HW_USBCTRL_DCCPARAMS                HW(USBCTRL_DCCPARAMS)
+#define HWA_USBCTRL_DCCPARAMS               (0x80080000 + 0x124)
+#define HWT_USBCTRL_DCCPARAMS               HWIO_32_RW
+#define HWN_USBCTRL_DCCPARAMS               USBCTRL_DCCPARAMS
+#define HWI_USBCTRL_DCCPARAMS               
+#define BP_USBCTRL_DCCPARAMS_RSVD1          9
+#define BM_USBCTRL_DCCPARAMS_RSVD1          0xfffffe00
+#define BF_USBCTRL_DCCPARAMS_RSVD1(v)       (((v) & 0x7fffff) << 9)
+#define BFM_USBCTRL_DCCPARAMS_RSVD1(v)      BM_USBCTRL_DCCPARAMS_RSVD1
+#define BF_USBCTRL_DCCPARAMS_RSVD1_V(e)     BF_USBCTRL_DCCPARAMS_RSVD1(BV_USBCTRL_DCCPARAMS_RSVD1__##e)
+#define BFM_USBCTRL_DCCPARAMS_RSVD1_V(v)    BM_USBCTRL_DCCPARAMS_RSVD1
+#define BP_USBCTRL_DCCPARAMS_HC             8
+#define BM_USBCTRL_DCCPARAMS_HC             0x100
+#define BF_USBCTRL_DCCPARAMS_HC(v)          (((v) & 0x1) << 8)
+#define BFM_USBCTRL_DCCPARAMS_HC(v)         BM_USBCTRL_DCCPARAMS_HC
+#define BF_USBCTRL_DCCPARAMS_HC_V(e)        BF_USBCTRL_DCCPARAMS_HC(BV_USBCTRL_DCCPARAMS_HC__##e)
+#define BFM_USBCTRL_DCCPARAMS_HC_V(v)       BM_USBCTRL_DCCPARAMS_HC
+#define BP_USBCTRL_DCCPARAMS_DC             7
+#define BM_USBCTRL_DCCPARAMS_DC             0x80
+#define BF_USBCTRL_DCCPARAMS_DC(v)          (((v) & 0x1) << 7)
+#define BFM_USBCTRL_DCCPARAMS_DC(v)         BM_USBCTRL_DCCPARAMS_DC
+#define BF_USBCTRL_DCCPARAMS_DC_V(e)        BF_USBCTRL_DCCPARAMS_DC(BV_USBCTRL_DCCPARAMS_DC__##e)
+#define BFM_USBCTRL_DCCPARAMS_DC_V(v)       BM_USBCTRL_DCCPARAMS_DC
+#define BP_USBCTRL_DCCPARAMS_RSVD2          5
+#define BM_USBCTRL_DCCPARAMS_RSVD2          0x60
+#define BF_USBCTRL_DCCPARAMS_RSVD2(v)       (((v) & 0x3) << 5)
+#define BFM_USBCTRL_DCCPARAMS_RSVD2(v)      BM_USBCTRL_DCCPARAMS_RSVD2
+#define BF_USBCTRL_DCCPARAMS_RSVD2_V(e)     BF_USBCTRL_DCCPARAMS_RSVD2(BV_USBCTRL_DCCPARAMS_RSVD2__##e)
+#define BFM_USBCTRL_DCCPARAMS_RSVD2_V(v)    BM_USBCTRL_DCCPARAMS_RSVD2
+#define BP_USBCTRL_DCCPARAMS_DEN            0
+#define BM_USBCTRL_DCCPARAMS_DEN            0x1f
+#define BF_USBCTRL_DCCPARAMS_DEN(v)         (((v) & 0x1f) << 0)
+#define BFM_USBCTRL_DCCPARAMS_DEN(v)        BM_USBCTRL_DCCPARAMS_DEN
+#define BF_USBCTRL_DCCPARAMS_DEN_V(e)       BF_USBCTRL_DCCPARAMS_DEN(BV_USBCTRL_DCCPARAMS_DEN__##e)
+#define BFM_USBCTRL_DCCPARAMS_DEN_V(v)      BM_USBCTRL_DCCPARAMS_DEN
+
+#define HW_USBCTRL_USBCMD                       HW(USBCTRL_USBCMD)
+#define HWA_USBCTRL_USBCMD                      (0x80080000 + 0x140)
+#define HWT_USBCTRL_USBCMD                      HWIO_32_RW
+#define HWN_USBCTRL_USBCMD                      USBCTRL_USBCMD
+#define HWI_USBCTRL_USBCMD                      
+#define BP_USBCTRL_USBCMD_RSVD3                 24
+#define BM_USBCTRL_USBCMD_RSVD3                 0xff000000
+#define BF_USBCTRL_USBCMD_RSVD3(v)              (((v) & 0xff) << 24)
+#define BFM_USBCTRL_USBCMD_RSVD3(v)             BM_USBCTRL_USBCMD_RSVD3
+#define BF_USBCTRL_USBCMD_RSVD3_V(e)            BF_USBCTRL_USBCMD_RSVD3(BV_USBCTRL_USBCMD_RSVD3__##e)
+#define BFM_USBCTRL_USBCMD_RSVD3_V(v)           BM_USBCTRL_USBCMD_RSVD3
+#define BP_USBCTRL_USBCMD_ITC                   16
+#define BM_USBCTRL_USBCMD_ITC                   0xff0000
+#define BV_USBCTRL_USBCMD_ITC__IMM              0x0
+#define BV_USBCTRL_USBCMD_ITC__1_MICROFRAME     0x1
+#define BV_USBCTRL_USBCMD_ITC__2_MICROFRAME     0x2
+#define BV_USBCTRL_USBCMD_ITC__4_MICROFRAME     0x4
+#define BV_USBCTRL_USBCMD_ITC__8_MICROFRAME     0x8
+#define BV_USBCTRL_USBCMD_ITC__16_MICROFRAME    0x10
+#define BV_USBCTRL_USBCMD_ITC__32_MICROFRAME    0x20
+#define BV_USBCTRL_USBCMD_ITC__64_MICROFRAME    0x40
+#define BF_USBCTRL_USBCMD_ITC(v)                (((v) & 0xff) << 16)
+#define BFM_USBCTRL_USBCMD_ITC(v)               BM_USBCTRL_USBCMD_ITC
+#define BF_USBCTRL_USBCMD_ITC_V(e)              BF_USBCTRL_USBCMD_ITC(BV_USBCTRL_USBCMD_ITC__##e)
+#define BFM_USBCTRL_USBCMD_ITC_V(v)             BM_USBCTRL_USBCMD_ITC
+#define BP_USBCTRL_USBCMD_FS2                   15
+#define BM_USBCTRL_USBCMD_FS2                   0x8000
+#define BF_USBCTRL_USBCMD_FS2(v)                (((v) & 0x1) << 15)
+#define BFM_USBCTRL_USBCMD_FS2(v)               BM_USBCTRL_USBCMD_FS2
+#define BF_USBCTRL_USBCMD_FS2_V(e)              BF_USBCTRL_USBCMD_FS2(BV_USBCTRL_USBCMD_FS2__##e)
+#define BFM_USBCTRL_USBCMD_FS2_V(v)             BM_USBCTRL_USBCMD_FS2
+#define BP_USBCTRL_USBCMD_ATDTW                 14
+#define BM_USBCTRL_USBCMD_ATDTW                 0x4000
+#define BF_USBCTRL_USBCMD_ATDTW(v)              (((v) & 0x1) << 14)
+#define BFM_USBCTRL_USBCMD_ATDTW(v)             BM_USBCTRL_USBCMD_ATDTW
+#define BF_USBCTRL_USBCMD_ATDTW_V(e)            BF_USBCTRL_USBCMD_ATDTW(BV_USBCTRL_USBCMD_ATDTW__##e)
+#define BFM_USBCTRL_USBCMD_ATDTW_V(v)           BM_USBCTRL_USBCMD_ATDTW
+#define BP_USBCTRL_USBCMD_SUTW                  13
+#define BM_USBCTRL_USBCMD_SUTW                  0x2000
+#define BF_USBCTRL_USBCMD_SUTW(v)               (((v) & 0x1) << 13)
+#define BFM_USBCTRL_USBCMD_SUTW(v)              BM_USBCTRL_USBCMD_SUTW
+#define BF_USBCTRL_USBCMD_SUTW_V(e)             BF_USBCTRL_USBCMD_SUTW(BV_USBCTRL_USBCMD_SUTW__##e)
+#define BFM_USBCTRL_USBCMD_SUTW_V(v)            BM_USBCTRL_USBCMD_SUTW
+#define BP_USBCTRL_USBCMD_RSVD2                 12
+#define BM_USBCTRL_USBCMD_RSVD2                 0x1000
+#define BF_USBCTRL_USBCMD_RSVD2(v)              (((v) & 0x1) << 12)
+#define BFM_USBCTRL_USBCMD_RSVD2(v)             BM_USBCTRL_USBCMD_RSVD2
+#define BF_USBCTRL_USBCMD_RSVD2_V(e)            BF_USBCTRL_USBCMD_RSVD2(BV_USBCTRL_USBCMD_RSVD2__##e)
+#define BFM_USBCTRL_USBCMD_RSVD2_V(v)           BM_USBCTRL_USBCMD_RSVD2
+#define BP_USBCTRL_USBCMD_ASPE                  11
+#define BM_USBCTRL_USBCMD_ASPE                  0x800
+#define BF_USBCTRL_USBCMD_ASPE(v)               (((v) & 0x1) << 11)
+#define BFM_USBCTRL_USBCMD_ASPE(v)              BM_USBCTRL_USBCMD_ASPE
+#define BF_USBCTRL_USBCMD_ASPE_V(e)             BF_USBCTRL_USBCMD_ASPE(BV_USBCTRL_USBCMD_ASPE__##e)
+#define BFM_USBCTRL_USBCMD_ASPE_V(v)            BM_USBCTRL_USBCMD_ASPE
+#define BP_USBCTRL_USBCMD_RSVD1                 10
+#define BM_USBCTRL_USBCMD_RSVD1                 0x400
+#define BF_USBCTRL_USBCMD_RSVD1(v)              (((v) & 0x1) << 10)
+#define BFM_USBCTRL_USBCMD_RSVD1(v)             BM_USBCTRL_USBCMD_RSVD1
+#define BF_USBCTRL_USBCMD_RSVD1_V(e)            BF_USBCTRL_USBCMD_RSVD1(BV_USBCTRL_USBCMD_RSVD1__##e)
+#define BFM_USBCTRL_USBCMD_RSVD1_V(v)           BM_USBCTRL_USBCMD_RSVD1
+#define BP_USBCTRL_USBCMD_ASP                   8
+#define BM_USBCTRL_USBCMD_ASP                   0x300
+#define BF_USBCTRL_USBCMD_ASP(v)                (((v) & 0x3) << 8)
+#define BFM_USBCTRL_USBCMD_ASP(v)               BM_USBCTRL_USBCMD_ASP
+#define BF_USBCTRL_USBCMD_ASP_V(e)              BF_USBCTRL_USBCMD_ASP(BV_USBCTRL_USBCMD_ASP__##e)
+#define BFM_USBCTRL_USBCMD_ASP_V(v)             BM_USBCTRL_USBCMD_ASP
+#define BP_USBCTRL_USBCMD_LR                    7
+#define BM_USBCTRL_USBCMD_LR                    0x80
+#define BF_USBCTRL_USBCMD_LR(v)                 (((v) & 0x1) << 7)
+#define BFM_USBCTRL_USBCMD_LR(v)                BM_USBCTRL_USBCMD_LR
+#define BF_USBCTRL_USBCMD_LR_V(e)               BF_USBCTRL_USBCMD_LR(BV_USBCTRL_USBCMD_LR__##e)
+#define BFM_USBCTRL_USBCMD_LR_V(v)              BM_USBCTRL_USBCMD_LR
+#define BP_USBCTRL_USBCMD_IAA                   6
+#define BM_USBCTRL_USBCMD_IAA                   0x40
+#define BF_USBCTRL_USBCMD_IAA(v)                (((v) & 0x1) << 6)
+#define BFM_USBCTRL_USBCMD_IAA(v)               BM_USBCTRL_USBCMD_IAA
+#define BF_USBCTRL_USBCMD_IAA_V(e)              BF_USBCTRL_USBCMD_IAA(BV_USBCTRL_USBCMD_IAA__##e)
+#define BFM_USBCTRL_USBCMD_IAA_V(v)             BM_USBCTRL_USBCMD_IAA
+#define BP_USBCTRL_USBCMD_ASE                   5
+#define BM_USBCTRL_USBCMD_ASE                   0x20
+#define BF_USBCTRL_USBCMD_ASE(v)                (((v) & 0x1) << 5)
+#define BFM_USBCTRL_USBCMD_ASE(v)               BM_USBCTRL_USBCMD_ASE
+#define BF_USBCTRL_USBCMD_ASE_V(e)              BF_USBCTRL_USBCMD_ASE(BV_USBCTRL_USBCMD_ASE__##e)
+#define BFM_USBCTRL_USBCMD_ASE_V(v)             BM_USBCTRL_USBCMD_ASE
+#define BP_USBCTRL_USBCMD_PSE                   4
+#define BM_USBCTRL_USBCMD_PSE                   0x10
+#define BF_USBCTRL_USBCMD_PSE(v)                (((v) & 0x1) << 4)
+#define BFM_USBCTRL_USBCMD_PSE(v)               BM_USBCTRL_USBCMD_PSE
+#define BF_USBCTRL_USBCMD_PSE_V(e)              BF_USBCTRL_USBCMD_PSE(BV_USBCTRL_USBCMD_PSE__##e)
+#define BFM_USBCTRL_USBCMD_PSE_V(v)             BM_USBCTRL_USBCMD_PSE
+#define BP_USBCTRL_USBCMD_FS1                   3
+#define BM_USBCTRL_USBCMD_FS1                   0x8
+#define BF_USBCTRL_USBCMD_FS1(v)                (((v) & 0x1) << 3)
+#define BFM_USBCTRL_USBCMD_FS1(v)               BM_USBCTRL_USBCMD_FS1
+#define BF_USBCTRL_USBCMD_FS1_V(e)              BF_USBCTRL_USBCMD_FS1(BV_USBCTRL_USBCMD_FS1__##e)
+#define BFM_USBCTRL_USBCMD_FS1_V(v)             BM_USBCTRL_USBCMD_FS1
+#define BP_USBCTRL_USBCMD_FS0                   2
+#define BM_USBCTRL_USBCMD_FS0                   0x4
+#define BF_USBCTRL_USBCMD_FS0(v)                (((v) & 0x1) << 2)
+#define BFM_USBCTRL_USBCMD_FS0(v)               BM_USBCTRL_USBCMD_FS0
+#define BF_USBCTRL_USBCMD_FS0_V(e)              BF_USBCTRL_USBCMD_FS0(BV_USBCTRL_USBCMD_FS0__##e)
+#define BFM_USBCTRL_USBCMD_FS0_V(v)             BM_USBCTRL_USBCMD_FS0
+#define BP_USBCTRL_USBCMD_RST                   1
+#define BM_USBCTRL_USBCMD_RST                   0x2
+#define BF_USBCTRL_USBCMD_RST(v)                (((v) & 0x1) << 1)
+#define BFM_USBCTRL_USBCMD_RST(v)               BM_USBCTRL_USBCMD_RST
+#define BF_USBCTRL_USBCMD_RST_V(e)              BF_USBCTRL_USBCMD_RST(BV_USBCTRL_USBCMD_RST__##e)
+#define BFM_USBCTRL_USBCMD_RST_V(v)             BM_USBCTRL_USBCMD_RST
+#define BP_USBCTRL_USBCMD_RS                    0
+#define BM_USBCTRL_USBCMD_RS                    0x1
+#define BF_USBCTRL_USBCMD_RS(v)                 (((v) & 0x1) << 0)
+#define BFM_USBCTRL_USBCMD_RS(v)                BM_USBCTRL_USBCMD_RS
+#define BF_USBCTRL_USBCMD_RS_V(e)               BF_USBCTRL_USBCMD_RS(BV_USBCTRL_USBCMD_RS__##e)
+#define BFM_USBCTRL_USBCMD_RS_V(v)              BM_USBCTRL_USBCMD_RS
+
+#define HW_USBCTRL_USBSTS               HW(USBCTRL_USBSTS)
+#define HWA_USBCTRL_USBSTS              (0x80080000 + 0x144)
+#define HWT_USBCTRL_USBSTS              HWIO_32_RW
+#define HWN_USBCTRL_USBSTS              USBCTRL_USBSTS
+#define HWI_USBCTRL_USBSTS              
+#define BP_USBCTRL_USBSTS_RSVD5         26
+#define BM_USBCTRL_USBSTS_RSVD5         0xfc000000
+#define BF_USBCTRL_USBSTS_RSVD5(v)      (((v) & 0x3f) << 26)
+#define BFM_USBCTRL_USBSTS_RSVD5(v)     BM_USBCTRL_USBSTS_RSVD5
+#define BF_USBCTRL_USBSTS_RSVD5_V(e)    BF_USBCTRL_USBSTS_RSVD5(BV_USBCTRL_USBSTS_RSVD5__##e)
+#define BFM_USBCTRL_USBSTS_RSVD5_V(v)   BM_USBCTRL_USBSTS_RSVD5
+#define BP_USBCTRL_USBSTS_TI1           25
+#define BM_USBCTRL_USBSTS_TI1           0x2000000
+#define BF_USBCTRL_USBSTS_TI1(v)        (((v) & 0x1) << 25)
+#define BFM_USBCTRL_USBSTS_TI1(v)       BM_USBCTRL_USBSTS_TI1
+#define BF_USBCTRL_USBSTS_TI1_V(e)      BF_USBCTRL_USBSTS_TI1(BV_USBCTRL_USBSTS_TI1__##e)
+#define BFM_USBCTRL_USBSTS_TI1_V(v)     BM_USBCTRL_USBSTS_TI1
+#define BP_USBCTRL_USBSTS_TI0           24
+#define BM_USBCTRL_USBSTS_TI0           0x1000000
+#define BF_USBCTRL_USBSTS_TI0(v)        (((v) & 0x1) << 24)
+#define BFM_USBCTRL_USBSTS_TI0(v)       BM_USBCTRL_USBSTS_TI0
+#define BF_USBCTRL_USBSTS_TI0_V(e)      BF_USBCTRL_USBSTS_TI0(BV_USBCTRL_USBSTS_TI0__##e)
+#define BFM_USBCTRL_USBSTS_TI0_V(v)     BM_USBCTRL_USBSTS_TI0
+#define BP_USBCTRL_USBSTS_RSVD4         20
+#define BM_USBCTRL_USBSTS_RSVD4         0xf00000
+#define BF_USBCTRL_USBSTS_RSVD4(v)      (((v) & 0xf) << 20)
+#define BFM_USBCTRL_USBSTS_RSVD4(v)     BM_USBCTRL_USBSTS_RSVD4
+#define BF_USBCTRL_USBSTS_RSVD4_V(e)    BF_USBCTRL_USBSTS_RSVD4(BV_USBCTRL_USBSTS_RSVD4__##e)
+#define BFM_USBCTRL_USBSTS_RSVD4_V(v)   BM_USBCTRL_USBSTS_RSVD4
+#define BP_USBCTRL_USBSTS_UPI           19
+#define BM_USBCTRL_USBSTS_UPI           0x80000
+#define BF_USBCTRL_USBSTS_UPI(v)        (((v) & 0x1) << 19)
+#define BFM_USBCTRL_USBSTS_UPI(v)       BM_USBCTRL_USBSTS_UPI
+#define BF_USBCTRL_USBSTS_UPI_V(e)      BF_USBCTRL_USBSTS_UPI(BV_USBCTRL_USBSTS_UPI__##e)
+#define BFM_USBCTRL_USBSTS_UPI_V(v)     BM_USBCTRL_USBSTS_UPI
+#define BP_USBCTRL_USBSTS_UAI           18
+#define BM_USBCTRL_USBSTS_UAI           0x40000
+#define BF_USBCTRL_USBSTS_UAI(v)        (((v) & 0x1) << 18)
+#define BFM_USBCTRL_USBSTS_UAI(v)       BM_USBCTRL_USBSTS_UAI
+#define BF_USBCTRL_USBSTS_UAI_V(e)      BF_USBCTRL_USBSTS_UAI(BV_USBCTRL_USBSTS_UAI__##e)
+#define BFM_USBCTRL_USBSTS_UAI_V(v)     BM_USBCTRL_USBSTS_UAI
+#define BP_USBCTRL_USBSTS_RSVD3         17
+#define BM_USBCTRL_USBSTS_RSVD3         0x20000
+#define BF_USBCTRL_USBSTS_RSVD3(v)      (((v) & 0x1) << 17)
+#define BFM_USBCTRL_USBSTS_RSVD3(v)     BM_USBCTRL_USBSTS_RSVD3
+#define BF_USBCTRL_USBSTS_RSVD3_V(e)    BF_USBCTRL_USBSTS_RSVD3(BV_USBCTRL_USBSTS_RSVD3__##e)
+#define BFM_USBCTRL_USBSTS_RSVD3_V(v)   BM_USBCTRL_USBSTS_RSVD3
+#define BP_USBCTRL_USBSTS_NAKI          16
+#define BM_USBCTRL_USBSTS_NAKI          0x10000
+#define BF_USBCTRL_USBSTS_NAKI(v)       (((v) & 0x1) << 16)
+#define BFM_USBCTRL_USBSTS_NAKI(v)      BM_USBCTRL_USBSTS_NAKI
+#define BF_USBCTRL_USBSTS_NAKI_V(e)     BF_USBCTRL_USBSTS_NAKI(BV_USBCTRL_USBSTS_NAKI__##e)
+#define BFM_USBCTRL_USBSTS_NAKI_V(v)    BM_USBCTRL_USBSTS_NAKI
+#define BP_USBCTRL_USBSTS_AS            15
+#define BM_USBCTRL_USBSTS_AS            0x8000
+#define BF_USBCTRL_USBSTS_AS(v)         (((v) & 0x1) << 15)
+#define BFM_USBCTRL_USBSTS_AS(v)        BM_USBCTRL_USBSTS_AS
+#define BF_USBCTRL_USBSTS_AS_V(e)       BF_USBCTRL_USBSTS_AS(BV_USBCTRL_USBSTS_AS__##e)
+#define BFM_USBCTRL_USBSTS_AS_V(v)      BM_USBCTRL_USBSTS_AS
+#define BP_USBCTRL_USBSTS_PS            14
+#define BM_USBCTRL_USBSTS_PS            0x4000
+#define BF_USBCTRL_USBSTS_PS(v)         (((v) & 0x1) << 14)
+#define BFM_USBCTRL_USBSTS_PS(v)        BM_USBCTRL_USBSTS_PS
+#define BF_USBCTRL_USBSTS_PS_V(e)       BF_USBCTRL_USBSTS_PS(BV_USBCTRL_USBSTS_PS__##e)
+#define BFM_USBCTRL_USBSTS_PS_V(v)      BM_USBCTRL_USBSTS_PS
+#define BP_USBCTRL_USBSTS_RCL           13
+#define BM_USBCTRL_USBSTS_RCL           0x2000
+#define BF_USBCTRL_USBSTS_RCL(v)        (((v) & 0x1) << 13)
+#define BFM_USBCTRL_USBSTS_RCL(v)       BM_USBCTRL_USBSTS_RCL
+#define BF_USBCTRL_USBSTS_RCL_V(e)      BF_USBCTRL_USBSTS_RCL(BV_USBCTRL_USBSTS_RCL__##e)
+#define BFM_USBCTRL_USBSTS_RCL_V(v)     BM_USBCTRL_USBSTS_RCL
+#define BP_USBCTRL_USBSTS_HCH           12
+#define BM_USBCTRL_USBSTS_HCH           0x1000
+#define BF_USBCTRL_USBSTS_HCH(v)        (((v) & 0x1) << 12)
+#define BFM_USBCTRL_USBSTS_HCH(v)       BM_USBCTRL_USBSTS_HCH
+#define BF_USBCTRL_USBSTS_HCH_V(e)      BF_USBCTRL_USBSTS_HCH(BV_USBCTRL_USBSTS_HCH__##e)
+#define BFM_USBCTRL_USBSTS_HCH_V(v)     BM_USBCTRL_USBSTS_HCH
+#define BP_USBCTRL_USBSTS_RSVD2         11
+#define BM_USBCTRL_USBSTS_RSVD2         0x800
+#define BF_USBCTRL_USBSTS_RSVD2(v)      (((v) & 0x1) << 11)
+#define BFM_USBCTRL_USBSTS_RSVD2(v)     BM_USBCTRL_USBSTS_RSVD2
+#define BF_USBCTRL_USBSTS_RSVD2_V(e)    BF_USBCTRL_USBSTS_RSVD2(BV_USBCTRL_USBSTS_RSVD2__##e)
+#define BFM_USBCTRL_USBSTS_RSVD2_V(v)   BM_USBCTRL_USBSTS_RSVD2
+#define BP_USBCTRL_USBSTS_ULPII         10
+#define BM_USBCTRL_USBSTS_ULPII         0x400
+#define BF_USBCTRL_USBSTS_ULPII(v)      (((v) & 0x1) << 10)
+#define BFM_USBCTRL_USBSTS_ULPII(v)     BM_USBCTRL_USBSTS_ULPII
+#define BF_USBCTRL_USBSTS_ULPII_V(e)    BF_USBCTRL_USBSTS_ULPII(BV_USBCTRL_USBSTS_ULPII__##e)
+#define BFM_USBCTRL_USBSTS_ULPII_V(v)   BM_USBCTRL_USBSTS_ULPII
+#define BP_USBCTRL_USBSTS_RSVD1         9
+#define BM_USBCTRL_USBSTS_RSVD1         0x200
+#define BF_USBCTRL_USBSTS_RSVD1(v)      (((v) & 0x1) << 9)
+#define BFM_USBCTRL_USBSTS_RSVD1(v)     BM_USBCTRL_USBSTS_RSVD1
+#define BF_USBCTRL_USBSTS_RSVD1_V(e)    BF_USBCTRL_USBSTS_RSVD1(BV_USBCTRL_USBSTS_RSVD1__##e)
+#define BFM_USBCTRL_USBSTS_RSVD1_V(v)   BM_USBCTRL_USBSTS_RSVD1
+#define BP_USBCTRL_USBSTS_SLI           8
+#define BM_USBCTRL_USBSTS_SLI           0x100
+#define BF_USBCTRL_USBSTS_SLI(v)        (((v) & 0x1) << 8)
+#define BFM_USBCTRL_USBSTS_SLI(v)       BM_USBCTRL_USBSTS_SLI
+#define BF_USBCTRL_USBSTS_SLI_V(e)      BF_USBCTRL_USBSTS_SLI(BV_USBCTRL_USBSTS_SLI__##e)
+#define BFM_USBCTRL_USBSTS_SLI_V(v)     BM_USBCTRL_USBSTS_SLI
+#define BP_USBCTRL_USBSTS_SRI           7
+#define BM_USBCTRL_USBSTS_SRI           0x80
+#define BF_USBCTRL_USBSTS_SRI(v)        (((v) & 0x1) << 7)
+#define BFM_USBCTRL_USBSTS_SRI(v)       BM_USBCTRL_USBSTS_SRI
+#define BF_USBCTRL_USBSTS_SRI_V(e)      BF_USBCTRL_USBSTS_SRI(BV_USBCTRL_USBSTS_SRI__##e)
+#define BFM_USBCTRL_USBSTS_SRI_V(v)     BM_USBCTRL_USBSTS_SRI
+#define BP_USBCTRL_USBSTS_URI           6
+#define BM_USBCTRL_USBSTS_URI           0x40
+#define BF_USBCTRL_USBSTS_URI(v)        (((v) & 0x1) << 6)
+#define BFM_USBCTRL_USBSTS_URI(v)       BM_USBCTRL_USBSTS_URI
+#define BF_USBCTRL_USBSTS_URI_V(e)      BF_USBCTRL_USBSTS_URI(BV_USBCTRL_USBSTS_URI__##e)
+#define BFM_USBCTRL_USBSTS_URI_V(v)     BM_USBCTRL_USBSTS_URI
+#define BP_USBCTRL_USBSTS_AAI           5
+#define BM_USBCTRL_USBSTS_AAI           0x20
+#define BF_USBCTRL_USBSTS_AAI(v)        (((v) & 0x1) << 5)
+#define BFM_USBCTRL_USBSTS_AAI(v)       BM_USBCTRL_USBSTS_AAI
+#define BF_USBCTRL_USBSTS_AAI_V(e)      BF_USBCTRL_USBSTS_AAI(BV_USBCTRL_USBSTS_AAI__##e)
+#define BFM_USBCTRL_USBSTS_AAI_V(v)     BM_USBCTRL_USBSTS_AAI
+#define BP_USBCTRL_USBSTS_SEI           4
+#define BM_USBCTRL_USBSTS_SEI           0x10
+#define BF_USBCTRL_USBSTS_SEI(v)        (((v) & 0x1) << 4)
+#define BFM_USBCTRL_USBSTS_SEI(v)       BM_USBCTRL_USBSTS_SEI
+#define BF_USBCTRL_USBSTS_SEI_V(e)      BF_USBCTRL_USBSTS_SEI(BV_USBCTRL_USBSTS_SEI__##e)
+#define BFM_USBCTRL_USBSTS_SEI_V(v)     BM_USBCTRL_USBSTS_SEI
+#define BP_USBCTRL_USBSTS_FRI           3
+#define BM_USBCTRL_USBSTS_FRI           0x8
+#define BF_USBCTRL_USBSTS_FRI(v)        (((v) & 0x1) << 3)
+#define BFM_USBCTRL_USBSTS_FRI(v)       BM_USBCTRL_USBSTS_FRI
+#define BF_USBCTRL_USBSTS_FRI_V(e)      BF_USBCTRL_USBSTS_FRI(BV_USBCTRL_USBSTS_FRI__##e)
+#define BFM_USBCTRL_USBSTS_FRI_V(v)     BM_USBCTRL_USBSTS_FRI
+#define BP_USBCTRL_USBSTS_PCI           2
+#define BM_USBCTRL_USBSTS_PCI           0x4
+#define BF_USBCTRL_USBSTS_PCI(v)        (((v) & 0x1) << 2)
+#define BFM_USBCTRL_USBSTS_PCI(v)       BM_USBCTRL_USBSTS_PCI
+#define BF_USBCTRL_USBSTS_PCI_V(e)      BF_USBCTRL_USBSTS_PCI(BV_USBCTRL_USBSTS_PCI__##e)
+#define BFM_USBCTRL_USBSTS_PCI_V(v)     BM_USBCTRL_USBSTS_PCI
+#define BP_USBCTRL_USBSTS_UEI           1
+#define BM_USBCTRL_USBSTS_UEI           0x2
+#define BF_USBCTRL_USBSTS_UEI(v)        (((v) & 0x1) << 1)
+#define BFM_USBCTRL_USBSTS_UEI(v)       BM_USBCTRL_USBSTS_UEI
+#define BF_USBCTRL_USBSTS_UEI_V(e)      BF_USBCTRL_USBSTS_UEI(BV_USBCTRL_USBSTS_UEI__##e)
+#define BFM_USBCTRL_USBSTS_UEI_V(v)     BM_USBCTRL_USBSTS_UEI
+#define BP_USBCTRL_USBSTS_UI            0
+#define BM_USBCTRL_USBSTS_UI            0x1
+#define BF_USBCTRL_USBSTS_UI(v)         (((v) & 0x1) << 0)
+#define BFM_USBCTRL_USBSTS_UI(v)        BM_USBCTRL_USBSTS_UI
+#define BF_USBCTRL_USBSTS_UI_V(e)       BF_USBCTRL_USBSTS_UI(BV_USBCTRL_USBSTS_UI__##e)
+#define BFM_USBCTRL_USBSTS_UI_V(v)      BM_USBCTRL_USBSTS_UI
+
+#define HW_USBCTRL_USBINTR              HW(USBCTRL_USBINTR)
+#define HWA_USBCTRL_USBINTR             (0x80080000 + 0x148)
+#define HWT_USBCTRL_USBINTR             HWIO_32_RW
+#define HWN_USBCTRL_USBINTR             USBCTRL_USBINTR
+#define HWI_USBCTRL_USBINTR             
+#define BP_USBCTRL_USBINTR_RSVD5        26
+#define BM_USBCTRL_USBINTR_RSVD5        0xfc000000
+#define BF_USBCTRL_USBINTR_RSVD5(v)     (((v) & 0x3f) << 26)
+#define BFM_USBCTRL_USBINTR_RSVD5(v)    BM_USBCTRL_USBINTR_RSVD5
+#define BF_USBCTRL_USBINTR_RSVD5_V(e)   BF_USBCTRL_USBINTR_RSVD5(BV_USBCTRL_USBINTR_RSVD5__##e)
+#define BFM_USBCTRL_USBINTR_RSVD5_V(v)  BM_USBCTRL_USBINTR_RSVD5
+#define BP_USBCTRL_USBINTR_TIE1         25
+#define BM_USBCTRL_USBINTR_TIE1         0x2000000
+#define BF_USBCTRL_USBINTR_TIE1(v)      (((v) & 0x1) << 25)
+#define BFM_USBCTRL_USBINTR_TIE1(v)     BM_USBCTRL_USBINTR_TIE1
+#define BF_USBCTRL_USBINTR_TIE1_V(e)    BF_USBCTRL_USBINTR_TIE1(BV_USBCTRL_USBINTR_TIE1__##e)
+#define BFM_USBCTRL_USBINTR_TIE1_V(v)   BM_USBCTRL_USBINTR_TIE1
+#define BP_USBCTRL_USBINTR_TIE0         24
+#define BM_USBCTRL_USBINTR_TIE0         0x1000000
+#define BF_USBCTRL_USBINTR_TIE0(v)      (((v) & 0x1) << 24)
+#define BFM_USBCTRL_USBINTR_TIE0(v)     BM_USBCTRL_USBINTR_TIE0
+#define BF_USBCTRL_USBINTR_TIE0_V(e)    BF_USBCTRL_USBINTR_TIE0(BV_USBCTRL_USBINTR_TIE0__##e)
+#define BFM_USBCTRL_USBINTR_TIE0_V(v)   BM_USBCTRL_USBINTR_TIE0
+#define BP_USBCTRL_USBINTR_RSVD4        20
+#define BM_USBCTRL_USBINTR_RSVD4        0xf00000
+#define BF_USBCTRL_USBINTR_RSVD4(v)     (((v) & 0xf) << 20)
+#define BFM_USBCTRL_USBINTR_RSVD4(v)    BM_USBCTRL_USBINTR_RSVD4
+#define BF_USBCTRL_USBINTR_RSVD4_V(e)   BF_USBCTRL_USBINTR_RSVD4(BV_USBCTRL_USBINTR_RSVD4__##e)
+#define BFM_USBCTRL_USBINTR_RSVD4_V(v)  BM_USBCTRL_USBINTR_RSVD4
+#define BP_USBCTRL_USBINTR_UPIE         19
+#define BM_USBCTRL_USBINTR_UPIE         0x80000
+#define BF_USBCTRL_USBINTR_UPIE(v)      (((v) & 0x1) << 19)
+#define BFM_USBCTRL_USBINTR_UPIE(v)     BM_USBCTRL_USBINTR_UPIE
+#define BF_USBCTRL_USBINTR_UPIE_V(e)    BF_USBCTRL_USBINTR_UPIE(BV_USBCTRL_USBINTR_UPIE__##e)
+#define BFM_USBCTRL_USBINTR_UPIE_V(v)   BM_USBCTRL_USBINTR_UPIE
+#define BP_USBCTRL_USBINTR_UAIE         18
+#define BM_USBCTRL_USBINTR_UAIE         0x40000
+#define BF_USBCTRL_USBINTR_UAIE(v)      (((v) & 0x1) << 18)
+#define BFM_USBCTRL_USBINTR_UAIE(v)     BM_USBCTRL_USBINTR_UAIE
+#define BF_USBCTRL_USBINTR_UAIE_V(e)    BF_USBCTRL_USBINTR_UAIE(BV_USBCTRL_USBINTR_UAIE__##e)
+#define BFM_USBCTRL_USBINTR_UAIE_V(v)   BM_USBCTRL_USBINTR_UAIE
+#define BP_USBCTRL_USBINTR_RSVD3        17
+#define BM_USBCTRL_USBINTR_RSVD3        0x20000
+#define BF_USBCTRL_USBINTR_RSVD3(v)     (((v) & 0x1) << 17)
+#define BFM_USBCTRL_USBINTR_RSVD3(v)    BM_USBCTRL_USBINTR_RSVD3
+#define BF_USBCTRL_USBINTR_RSVD3_V(e)   BF_USBCTRL_USBINTR_RSVD3(BV_USBCTRL_USBINTR_RSVD3__##e)
+#define BFM_USBCTRL_USBINTR_RSVD3_V(v)  BM_USBCTRL_USBINTR_RSVD3
+#define BP_USBCTRL_USBINTR_NAKE         16
+#define BM_USBCTRL_USBINTR_NAKE         0x10000
+#define BF_USBCTRL_USBINTR_NAKE(v)      (((v) & 0x1) << 16)
+#define BFM_USBCTRL_USBINTR_NAKE(v)     BM_USBCTRL_USBINTR_NAKE
+#define BF_USBCTRL_USBINTR_NAKE_V(e)    BF_USBCTRL_USBINTR_NAKE(BV_USBCTRL_USBINTR_NAKE__##e)
+#define BFM_USBCTRL_USBINTR_NAKE_V(v)   BM_USBCTRL_USBINTR_NAKE
+#define BP_USBCTRL_USBINTR_RSVD2        11
+#define BM_USBCTRL_USBINTR_RSVD2        0xf800
+#define BF_USBCTRL_USBINTR_RSVD2(v)     (((v) & 0x1f) << 11)
+#define BFM_USBCTRL_USBINTR_RSVD2(v)    BM_USBCTRL_USBINTR_RSVD2
+#define BF_USBCTRL_USBINTR_RSVD2_V(e)   BF_USBCTRL_USBINTR_RSVD2(BV_USBCTRL_USBINTR_RSVD2__##e)
+#define BFM_USBCTRL_USBINTR_RSVD2_V(v)  BM_USBCTRL_USBINTR_RSVD2
+#define BP_USBCTRL_USBINTR_ULPIE        10
+#define BM_USBCTRL_USBINTR_ULPIE        0x400
+#define BF_USBCTRL_USBINTR_ULPIE(v)     (((v) & 0x1) << 10)
+#define BFM_USBCTRL_USBINTR_ULPIE(v)    BM_USBCTRL_USBINTR_ULPIE
+#define BF_USBCTRL_USBINTR_ULPIE_V(e)   BF_USBCTRL_USBINTR_ULPIE(BV_USBCTRL_USBINTR_ULPIE__##e)
+#define BFM_USBCTRL_USBINTR_ULPIE_V(v)  BM_USBCTRL_USBINTR_ULPIE
+#define BP_USBCTRL_USBINTR_RSVD1        9
+#define BM_USBCTRL_USBINTR_RSVD1        0x200
+#define BF_USBCTRL_USBINTR_RSVD1(v)     (((v) & 0x1) << 9)
+#define BFM_USBCTRL_USBINTR_RSVD1(v)    BM_USBCTRL_USBINTR_RSVD1
+#define BF_USBCTRL_USBINTR_RSVD1_V(e)   BF_USBCTRL_USBINTR_RSVD1(BV_USBCTRL_USBINTR_RSVD1__##e)
+#define BFM_USBCTRL_USBINTR_RSVD1_V(v)  BM_USBCTRL_USBINTR_RSVD1
+#define BP_USBCTRL_USBINTR_SLE          8
+#define BM_USBCTRL_USBINTR_SLE          0x100
+#define BF_USBCTRL_USBINTR_SLE(v)       (((v) & 0x1) << 8)
+#define BFM_USBCTRL_USBINTR_SLE(v)      BM_USBCTRL_USBINTR_SLE
+#define BF_USBCTRL_USBINTR_SLE_V(e)     BF_USBCTRL_USBINTR_SLE(BV_USBCTRL_USBINTR_SLE__##e)
+#define BFM_USBCTRL_USBINTR_SLE_V(v)    BM_USBCTRL_USBINTR_SLE
+#define BP_USBCTRL_USBINTR_SRE          7
+#define BM_USBCTRL_USBINTR_SRE          0x80
+#define BF_USBCTRL_USBINTR_SRE(v)       (((v) & 0x1) << 7)
+#define BFM_USBCTRL_USBINTR_SRE(v)      BM_USBCTRL_USBINTR_SRE
+#define BF_USBCTRL_USBINTR_SRE_V(e)     BF_USBCTRL_USBINTR_SRE(BV_USBCTRL_USBINTR_SRE__##e)
+#define BFM_USBCTRL_USBINTR_SRE_V(v)    BM_USBCTRL_USBINTR_SRE
+#define BP_USBCTRL_USBINTR_URE          6
+#define BM_USBCTRL_USBINTR_URE          0x40
+#define BF_USBCTRL_USBINTR_URE(v)       (((v) & 0x1) << 6)
+#define BFM_USBCTRL_USBINTR_URE(v)      BM_USBCTRL_USBINTR_URE
+#define BF_USBCTRL_USBINTR_URE_V(e)     BF_USBCTRL_USBINTR_URE(BV_USBCTRL_USBINTR_URE__##e)
+#define BFM_USBCTRL_USBINTR_URE_V(v)    BM_USBCTRL_USBINTR_URE
+#define BP_USBCTRL_USBINTR_AAE          5
+#define BM_USBCTRL_USBINTR_AAE          0x20
+#define BF_USBCTRL_USBINTR_AAE(v)       (((v) & 0x1) << 5)
+#define BFM_USBCTRL_USBINTR_AAE(v)      BM_USBCTRL_USBINTR_AAE
+#define BF_USBCTRL_USBINTR_AAE_V(e)     BF_USBCTRL_USBINTR_AAE(BV_USBCTRL_USBINTR_AAE__##e)
+#define BFM_USBCTRL_USBINTR_AAE_V(v)    BM_USBCTRL_USBINTR_AAE
+#define BP_USBCTRL_USBINTR_SEE          4
+#define BM_USBCTRL_USBINTR_SEE          0x10
+#define BF_USBCTRL_USBINTR_SEE(v)       (((v) & 0x1) << 4)
+#define BFM_USBCTRL_USBINTR_SEE(v)      BM_USBCTRL_USBINTR_SEE
+#define BF_USBCTRL_USBINTR_SEE_V(e)     BF_USBCTRL_USBINTR_SEE(BV_USBCTRL_USBINTR_SEE__##e)
+#define BFM_USBCTRL_USBINTR_SEE_V(v)    BM_USBCTRL_USBINTR_SEE
+#define BP_USBCTRL_USBINTR_FRE          3
+#define BM_USBCTRL_USBINTR_FRE          0x8
+#define BF_USBCTRL_USBINTR_FRE(v)       (((v) & 0x1) << 3)
+#define BFM_USBCTRL_USBINTR_FRE(v)      BM_USBCTRL_USBINTR_FRE
+#define BF_USBCTRL_USBINTR_FRE_V(e)     BF_USBCTRL_USBINTR_FRE(BV_USBCTRL_USBINTR_FRE__##e)
+#define BFM_USBCTRL_USBINTR_FRE_V(v)    BM_USBCTRL_USBINTR_FRE
+#define BP_USBCTRL_USBINTR_PCE          2
+#define BM_USBCTRL_USBINTR_PCE          0x4
+#define BF_USBCTRL_USBINTR_PCE(v)       (((v) & 0x1) << 2)
+#define BFM_USBCTRL_USBINTR_PCE(v)      BM_USBCTRL_USBINTR_PCE
+#define BF_USBCTRL_USBINTR_PCE_V(e)     BF_USBCTRL_USBINTR_PCE(BV_USBCTRL_USBINTR_PCE__##e)
+#define BFM_USBCTRL_USBINTR_PCE_V(v)    BM_USBCTRL_USBINTR_PCE
+#define BP_USBCTRL_USBINTR_UEE          1
+#define BM_USBCTRL_USBINTR_UEE          0x2
+#define BF_USBCTRL_USBINTR_UEE(v)       (((v) & 0x1) << 1)
+#define BFM_USBCTRL_USBINTR_UEE(v)      BM_USBCTRL_USBINTR_UEE
+#define BF_USBCTRL_USBINTR_UEE_V(e)     BF_USBCTRL_USBINTR_UEE(BV_USBCTRL_USBINTR_UEE__##e)
+#define BFM_USBCTRL_USBINTR_UEE_V(v)    BM_USBCTRL_USBINTR_UEE
+#define BP_USBCTRL_USBINTR_UE           0
+#define BM_USBCTRL_USBINTR_UE           0x1
+#define BF_USBCTRL_USBINTR_UE(v)        (((v) & 0x1) << 0)
+#define BFM_USBCTRL_USBINTR_UE(v)       BM_USBCTRL_USBINTR_UE
+#define BF_USBCTRL_USBINTR_UE_V(e)      BF_USBCTRL_USBINTR_UE(BV_USBCTRL_USBINTR_UE__##e)
+#define BFM_USBCTRL_USBINTR_UE_V(v)     BM_USBCTRL_USBINTR_UE
+
+#define HW_USBCTRL_FRINDEX                  HW(USBCTRL_FRINDEX)
+#define HWA_USBCTRL_FRINDEX                 (0x80080000 + 0x14c)
+#define HWT_USBCTRL_FRINDEX                 HWIO_32_RW
+#define HWN_USBCTRL_FRINDEX                 USBCTRL_FRINDEX
+#define HWI_USBCTRL_FRINDEX                 
+#define BP_USBCTRL_FRINDEX_RSVD             14
+#define BM_USBCTRL_FRINDEX_RSVD             0xffffc000
+#define BF_USBCTRL_FRINDEX_RSVD(v)          (((v) & 0x3ffff) << 14)
+#define BFM_USBCTRL_FRINDEX_RSVD(v)         BM_USBCTRL_FRINDEX_RSVD
+#define BF_USBCTRL_FRINDEX_RSVD_V(e)        BF_USBCTRL_FRINDEX_RSVD(BV_USBCTRL_FRINDEX_RSVD__##e)
+#define BFM_USBCTRL_FRINDEX_RSVD_V(v)       BM_USBCTRL_FRINDEX_RSVD
+#define BP_USBCTRL_FRINDEX_FRINDEX          3
+#define BM_USBCTRL_FRINDEX_FRINDEX          0x3ff8
+#define BV_USBCTRL_FRINDEX_FRINDEX__N_12    0xc
+#define BV_USBCTRL_FRINDEX_FRINDEX__N_11    0xb
+#define BV_USBCTRL_FRINDEX_FRINDEX__N_10    0xa
+#define BV_USBCTRL_FRINDEX_FRINDEX__N_9     0x9
+#define BV_USBCTRL_FRINDEX_FRINDEX__N_8     0x8
+#define BV_USBCTRL_FRINDEX_FRINDEX__N_7     0x7
+#define BV_USBCTRL_FRINDEX_FRINDEX__N_6     0x6
+#define BV_USBCTRL_FRINDEX_FRINDEX__N_5     0x5
+#define BF_USBCTRL_FRINDEX_FRINDEX(v)       (((v) & 0x7ff) << 3)
+#define BFM_USBCTRL_FRINDEX_FRINDEX(v)      BM_USBCTRL_FRINDEX_FRINDEX
+#define BF_USBCTRL_FRINDEX_FRINDEX_V(e)     BF_USBCTRL_FRINDEX_FRINDEX(BV_USBCTRL_FRINDEX_FRINDEX__##e)
+#define BFM_USBCTRL_FRINDEX_FRINDEX_V(v)    BM_USBCTRL_FRINDEX_FRINDEX
+#define BP_USBCTRL_FRINDEX_UINDEX           0
+#define BM_USBCTRL_FRINDEX_UINDEX           0x7
+#define BF_USBCTRL_FRINDEX_UINDEX(v)        (((v) & 0x7) << 0)
+#define BFM_USBCTRL_FRINDEX_UINDEX(v)       BM_USBCTRL_FRINDEX_UINDEX
+#define BF_USBCTRL_FRINDEX_UINDEX_V(e)      BF_USBCTRL_FRINDEX_UINDEX(BV_USBCTRL_FRINDEX_UINDEX__##e)
+#define BFM_USBCTRL_FRINDEX_UINDEX_V(v)     BM_USBCTRL_FRINDEX_UINDEX
+
+#define HW_USBCTRL_PERIODICLISTBASE                 HW(USBCTRL_PERIODICLISTBASE)
+#define HWA_USBCTRL_PERIODICLISTBASE                (0x80080000 + 0x154)
+#define HWT_USBCTRL_PERIODICLISTBASE                HWIO_32_RW
+#define HWN_USBCTRL_PERIODICLISTBASE                USBCTRL_PERIODICLISTBASE
+#define HWI_USBCTRL_PERIODICLISTBASE                
+#define BP_USBCTRL_PERIODICLISTBASE_PERBASE         12
+#define BM_USBCTRL_PERIODICLISTBASE_PERBASE         0xfffff000
+#define BF_USBCTRL_PERIODICLISTBASE_PERBASE(v)      (((v) & 0xfffff) << 12)
+#define BFM_USBCTRL_PERIODICLISTBASE_PERBASE(v)     BM_USBCTRL_PERIODICLISTBASE_PERBASE
+#define BF_USBCTRL_PERIODICLISTBASE_PERBASE_V(e)    BF_USBCTRL_PERIODICLISTBASE_PERBASE(BV_USBCTRL_PERIODICLISTBASE_PERBASE__##e)
+#define BFM_USBCTRL_PERIODICLISTBASE_PERBASE_V(v)   BM_USBCTRL_PERIODICLISTBASE_PERBASE
+#define BP_USBCTRL_PERIODICLISTBASE_RSVD            0
+#define BM_USBCTRL_PERIODICLISTBASE_RSVD            0xfff
+#define BF_USBCTRL_PERIODICLISTBASE_RSVD(v)         (((v) & 0xfff) << 0)
+#define BFM_USBCTRL_PERIODICLISTBASE_RSVD(v)        BM_USBCTRL_PERIODICLISTBASE_RSVD
+#define BF_USBCTRL_PERIODICLISTBASE_RSVD_V(e)       BF_USBCTRL_PERIODICLISTBASE_RSVD(BV_USBCTRL_PERIODICLISTBASE_RSVD__##e)
+#define BFM_USBCTRL_PERIODICLISTBASE_RSVD_V(v)      BM_USBCTRL_PERIODICLISTBASE_RSVD
+
+#define HW_USBCTRL_DEVICEADDR               HW(USBCTRL_DEVICEADDR)
+#define HWA_USBCTRL_DEVICEADDR              (0x80080000 + 0x154)
+#define HWT_USBCTRL_DEVICEADDR              HWIO_32_RW
+#define HWN_USBCTRL_DEVICEADDR              USBCTRL_DEVICEADDR
+#define HWI_USBCTRL_DEVICEADDR              
+#define BP_USBCTRL_DEVICEADDR_USBADR        25
+#define BM_USBCTRL_DEVICEADDR_USBADR        0xfe000000
+#define BF_USBCTRL_DEVICEADDR_USBADR(v)     (((v) & 0x7f) << 25)
+#define BFM_USBCTRL_DEVICEADDR_USBADR(v)    BM_USBCTRL_DEVICEADDR_USBADR
+#define BF_USBCTRL_DEVICEADDR_USBADR_V(e)   BF_USBCTRL_DEVICEADDR_USBADR(BV_USBCTRL_DEVICEADDR_USBADR__##e)
+#define BFM_USBCTRL_DEVICEADDR_USBADR_V(v)  BM_USBCTRL_DEVICEADDR_USBADR
+#define BP_USBCTRL_DEVICEADDR_USBADRA       24
+#define BM_USBCTRL_DEVICEADDR_USBADRA       0x1000000
+#define BF_USBCTRL_DEVICEADDR_USBADRA(v)    (((v) & 0x1) << 24)
+#define BFM_USBCTRL_DEVICEADDR_USBADRA(v)   BM_USBCTRL_DEVICEADDR_USBADRA
+#define BF_USBCTRL_DEVICEADDR_USBADRA_V(e)  BF_USBCTRL_DEVICEADDR_USBADRA(BV_USBCTRL_DEVICEADDR_USBADRA__##e)
+#define BFM_USBCTRL_DEVICEADDR_USBADRA_V(v) BM_USBCTRL_DEVICEADDR_USBADRA
+#define BP_USBCTRL_DEVICEADDR_RSVD          0
+#define BM_USBCTRL_DEVICEADDR_RSVD          0xffffff
+#define BF_USBCTRL_DEVICEADDR_RSVD(v)       (((v) & 0xffffff) << 0)
+#define BFM_USBCTRL_DEVICEADDR_RSVD(v)      BM_USBCTRL_DEVICEADDR_RSVD
+#define BF_USBCTRL_DEVICEADDR_RSVD_V(e)     BF_USBCTRL_DEVICEADDR_RSVD(BV_USBCTRL_DEVICEADDR_RSVD__##e)
+#define BFM_USBCTRL_DEVICEADDR_RSVD_V(v)    BM_USBCTRL_DEVICEADDR_RSVD
+
+#define HW_USBCTRL_ASYNCLISTADDR                HW(USBCTRL_ASYNCLISTADDR)
+#define HWA_USBCTRL_ASYNCLISTADDR               (0x80080000 + 0x158)
+#define HWT_USBCTRL_ASYNCLISTADDR               HWIO_32_RW
+#define HWN_USBCTRL_ASYNCLISTADDR               USBCTRL_ASYNCLISTADDR
+#define HWI_USBCTRL_ASYNCLISTADDR               
+#define BP_USBCTRL_ASYNCLISTADDR_ASYBASE        5
+#define BM_USBCTRL_ASYNCLISTADDR_ASYBASE        0xffffffe0
+#define BF_USBCTRL_ASYNCLISTADDR_ASYBASE(v)     (((v) & 0x7ffffff) << 5)
+#define BFM_USBCTRL_ASYNCLISTADDR_ASYBASE(v)    BM_USBCTRL_ASYNCLISTADDR_ASYBASE
+#define BF_USBCTRL_ASYNCLISTADDR_ASYBASE_V(e)   BF_USBCTRL_ASYNCLISTADDR_ASYBASE(BV_USBCTRL_ASYNCLISTADDR_ASYBASE__##e)
+#define BFM_USBCTRL_ASYNCLISTADDR_ASYBASE_V(v)  BM_USBCTRL_ASYNCLISTADDR_ASYBASE
+#define BP_USBCTRL_ASYNCLISTADDR_RSVD           0
+#define BM_USBCTRL_ASYNCLISTADDR_RSVD           0x1f
+#define BF_USBCTRL_ASYNCLISTADDR_RSVD(v)        (((v) & 0x1f) << 0)
+#define BFM_USBCTRL_ASYNCLISTADDR_RSVD(v)       BM_USBCTRL_ASYNCLISTADDR_RSVD
+#define BF_USBCTRL_ASYNCLISTADDR_RSVD_V(e)      BF_USBCTRL_ASYNCLISTADDR_RSVD(BV_USBCTRL_ASYNCLISTADDR_RSVD__##e)
+#define BFM_USBCTRL_ASYNCLISTADDR_RSVD_V(v)     BM_USBCTRL_ASYNCLISTADDR_RSVD
+
+#define HW_USBCTRL_ENDPOINTLISTADDR                 HW(USBCTRL_ENDPOINTLISTADDR)
+#define HWA_USBCTRL_ENDPOINTLISTADDR                (0x80080000 + 0x158)
+#define HWT_USBCTRL_ENDPOINTLISTADDR                HWIO_32_RW
+#define HWN_USBCTRL_ENDPOINTLISTADDR                USBCTRL_ENDPOINTLISTADDR
+#define HWI_USBCTRL_ENDPOINTLISTADDR                
+#define BP_USBCTRL_ENDPOINTLISTADDR_EPBASE          11
+#define BM_USBCTRL_ENDPOINTLISTADDR_EPBASE          0xfffff800
+#define BF_USBCTRL_ENDPOINTLISTADDR_EPBASE(v)       (((v) & 0x1fffff) << 11)
+#define BFM_USBCTRL_ENDPOINTLISTADDR_EPBASE(v)      BM_USBCTRL_ENDPOINTLISTADDR_EPBASE
+#define BF_USBCTRL_ENDPOINTLISTADDR_EPBASE_V(e)     BF_USBCTRL_ENDPOINTLISTADDR_EPBASE(BV_USBCTRL_ENDPOINTLISTADDR_EPBASE__##e)
+#define BFM_USBCTRL_ENDPOINTLISTADDR_EPBASE_V(v)    BM_USBCTRL_ENDPOINTLISTADDR_EPBASE
+#define BP_USBCTRL_ENDPOINTLISTADDR_RSVD            0
+#define BM_USBCTRL_ENDPOINTLISTADDR_RSVD            0x7ff
+#define BF_USBCTRL_ENDPOINTLISTADDR_RSVD(v)         (((v) & 0x7ff) << 0)
+#define BFM_USBCTRL_ENDPOINTLISTADDR_RSVD(v)        BM_USBCTRL_ENDPOINTLISTADDR_RSVD
+#define BF_USBCTRL_ENDPOINTLISTADDR_RSVD_V(e)       BF_USBCTRL_ENDPOINTLISTADDR_RSVD(BV_USBCTRL_ENDPOINTLISTADDR_RSVD__##e)
+#define BFM_USBCTRL_ENDPOINTLISTADDR_RSVD_V(v)      BM_USBCTRL_ENDPOINTLISTADDR_RSVD
+
+#define HW_USBCTRL_TTCTRL               HW(USBCTRL_TTCTRL)
+#define HWA_USBCTRL_TTCTRL              (0x80080000 + 0x15c)
+#define HWT_USBCTRL_TTCTRL              HWIO_32_RW
+#define HWN_USBCTRL_TTCTRL              USBCTRL_TTCTRL
+#define HWI_USBCTRL_TTCTRL              
+#define BP_USBCTRL_TTCTRL_RSVD1         31
+#define BM_USBCTRL_TTCTRL_RSVD1         0x80000000
+#define BF_USBCTRL_TTCTRL_RSVD1(v)      (((v) & 0x1) << 31)
+#define BFM_USBCTRL_TTCTRL_RSVD1(v)     BM_USBCTRL_TTCTRL_RSVD1
+#define BF_USBCTRL_TTCTRL_RSVD1_V(e)    BF_USBCTRL_TTCTRL_RSVD1(BV_USBCTRL_TTCTRL_RSVD1__##e)
+#define BFM_USBCTRL_TTCTRL_RSVD1_V(v)   BM_USBCTRL_TTCTRL_RSVD1
+#define BP_USBCTRL_TTCTRL_TTHA          24
+#define BM_USBCTRL_TTCTRL_TTHA          0x7f000000
+#define BF_USBCTRL_TTCTRL_TTHA(v)       (((v) & 0x7f) << 24)
+#define BFM_USBCTRL_TTCTRL_TTHA(v)      BM_USBCTRL_TTCTRL_TTHA
+#define BF_USBCTRL_TTCTRL_TTHA_V(e)     BF_USBCTRL_TTCTRL_TTHA(BV_USBCTRL_TTCTRL_TTHA__##e)
+#define BFM_USBCTRL_TTCTRL_TTHA_V(v)    BM_USBCTRL_TTCTRL_TTHA
+#define BP_USBCTRL_TTCTRL_RSVD2         0
+#define BM_USBCTRL_TTCTRL_RSVD2         0xffffff
+#define BF_USBCTRL_TTCTRL_RSVD2(v)      (((v) & 0xffffff) << 0)
+#define BFM_USBCTRL_TTCTRL_RSVD2(v)     BM_USBCTRL_TTCTRL_RSVD2
+#define BF_USBCTRL_TTCTRL_RSVD2_V(e)    BF_USBCTRL_TTCTRL_RSVD2(BV_USBCTRL_TTCTRL_RSVD2__##e)
+#define BFM_USBCTRL_TTCTRL_RSVD2_V(v)   BM_USBCTRL_TTCTRL_RSVD2
+
+#define HW_USBCTRL_BURSTSIZE                HW(USBCTRL_BURSTSIZE)
+#define HWA_USBCTRL_BURSTSIZE               (0x80080000 + 0x160)
+#define HWT_USBCTRL_BURSTSIZE               HWIO_32_RW
+#define HWN_USBCTRL_BURSTSIZE               USBCTRL_BURSTSIZE
+#define HWI_USBCTRL_BURSTSIZE               
+#define BP_USBCTRL_BURSTSIZE_RSVD           16
+#define BM_USBCTRL_BURSTSIZE_RSVD           0xffff0000
+#define BF_USBCTRL_BURSTSIZE_RSVD(v)        (((v) & 0xffff) << 16)
+#define BFM_USBCTRL_BURSTSIZE_RSVD(v)       BM_USBCTRL_BURSTSIZE_RSVD
+#define BF_USBCTRL_BURSTSIZE_RSVD_V(e)      BF_USBCTRL_BURSTSIZE_RSVD(BV_USBCTRL_BURSTSIZE_RSVD__##e)
+#define BFM_USBCTRL_BURSTSIZE_RSVD_V(v)     BM_USBCTRL_BURSTSIZE_RSVD
+#define BP_USBCTRL_BURSTSIZE_TXPBURST       8
+#define BM_USBCTRL_BURSTSIZE_TXPBURST       0xff00
+#define BF_USBCTRL_BURSTSIZE_TXPBURST(v)    (((v) & 0xff) << 8)
+#define BFM_USBCTRL_BURSTSIZE_TXPBURST(v)   BM_USBCTRL_BURSTSIZE_TXPBURST
+#define BF_USBCTRL_BURSTSIZE_TXPBURST_V(e)  BF_USBCTRL_BURSTSIZE_TXPBURST(BV_USBCTRL_BURSTSIZE_TXPBURST__##e)
+#define BFM_USBCTRL_BURSTSIZE_TXPBURST_V(v) BM_USBCTRL_BURSTSIZE_TXPBURST
+#define BP_USBCTRL_BURSTSIZE_RXPBURST       0
+#define BM_USBCTRL_BURSTSIZE_RXPBURST       0xff
+#define BF_USBCTRL_BURSTSIZE_RXPBURST(v)    (((v) & 0xff) << 0)
+#define BFM_USBCTRL_BURSTSIZE_RXPBURST(v)   BM_USBCTRL_BURSTSIZE_RXPBURST
+#define BF_USBCTRL_BURSTSIZE_RXPBURST_V(e)  BF_USBCTRL_BURSTSIZE_RXPBURST(BV_USBCTRL_BURSTSIZE_RXPBURST__##e)
+#define BFM_USBCTRL_BURSTSIZE_RXPBURST_V(v) BM_USBCTRL_BURSTSIZE_RXPBURST
+
+#define HW_USBCTRL_TXFILLTUNING                     HW(USBCTRL_TXFILLTUNING)
+#define HWA_USBCTRL_TXFILLTUNING                    (0x80080000 + 0x164)
+#define HWT_USBCTRL_TXFILLTUNING                    HWIO_32_RW
+#define HWN_USBCTRL_TXFILLTUNING                    USBCTRL_TXFILLTUNING
+#define HWI_USBCTRL_TXFILLTUNING                    
+#define BP_USBCTRL_TXFILLTUNING_RSVD2               22
+#define BM_USBCTRL_TXFILLTUNING_RSVD2               0xffc00000
+#define BF_USBCTRL_TXFILLTUNING_RSVD2(v)            (((v) & 0x3ff) << 22)
+#define BFM_USBCTRL_TXFILLTUNING_RSVD2(v)           BM_USBCTRL_TXFILLTUNING_RSVD2
+#define BF_USBCTRL_TXFILLTUNING_RSVD2_V(e)          BF_USBCTRL_TXFILLTUNING_RSVD2(BV_USBCTRL_TXFILLTUNING_RSVD2__##e)
+#define BFM_USBCTRL_TXFILLTUNING_RSVD2_V(v)         BM_USBCTRL_TXFILLTUNING_RSVD2
+#define BP_USBCTRL_TXFILLTUNING_TXFIFOTHRES         16
+#define BM_USBCTRL_TXFILLTUNING_TXFIFOTHRES         0x3f0000
+#define BF_USBCTRL_TXFILLTUNING_TXFIFOTHRES(v)      (((v) & 0x3f) << 16)
+#define BFM_USBCTRL_TXFILLTUNING_TXFIFOTHRES(v)     BM_USBCTRL_TXFILLTUNING_TXFIFOTHRES
+#define BF_USBCTRL_TXFILLTUNING_TXFIFOTHRES_V(e)    BF_USBCTRL_TXFILLTUNING_TXFIFOTHRES(BV_USBCTRL_TXFILLTUNING_TXFIFOTHRES__##e)
+#define BFM_USBCTRL_TXFILLTUNING_TXFIFOTHRES_V(v)   BM_USBCTRL_TXFILLTUNING_TXFIFOTHRES
+#define BP_USBCTRL_TXFILLTUNING_RSVD1               13
+#define BM_USBCTRL_TXFILLTUNING_RSVD1               0xe000
+#define BF_USBCTRL_TXFILLTUNING_RSVD1(v)            (((v) & 0x7) << 13)
+#define BFM_USBCTRL_TXFILLTUNING_RSVD1(v)           BM_USBCTRL_TXFILLTUNING_RSVD1
+#define BF_USBCTRL_TXFILLTUNING_RSVD1_V(e)          BF_USBCTRL_TXFILLTUNING_RSVD1(BV_USBCTRL_TXFILLTUNING_RSVD1__##e)
+#define BFM_USBCTRL_TXFILLTUNING_RSVD1_V(v)         BM_USBCTRL_TXFILLTUNING_RSVD1
+#define BP_USBCTRL_TXFILLTUNING_TXSCHEALTH          8
+#define BM_USBCTRL_TXFILLTUNING_TXSCHEALTH          0x1f00
+#define BF_USBCTRL_TXFILLTUNING_TXSCHEALTH(v)       (((v) & 0x1f) << 8)
+#define BFM_USBCTRL_TXFILLTUNING_TXSCHEALTH(v)      BM_USBCTRL_TXFILLTUNING_TXSCHEALTH
+#define BF_USBCTRL_TXFILLTUNING_TXSCHEALTH_V(e)     BF_USBCTRL_TXFILLTUNING_TXSCHEALTH(BV_USBCTRL_TXFILLTUNING_TXSCHEALTH__##e)
+#define BFM_USBCTRL_TXFILLTUNING_TXSCHEALTH_V(v)    BM_USBCTRL_TXFILLTUNING_TXSCHEALTH
+#define BP_USBCTRL_TXFILLTUNING_RSVD0               7
+#define BM_USBCTRL_TXFILLTUNING_RSVD0               0x80
+#define BF_USBCTRL_TXFILLTUNING_RSVD0(v)            (((v) & 0x1) << 7)
+#define BFM_USBCTRL_TXFILLTUNING_RSVD0(v)           BM_USBCTRL_TXFILLTUNING_RSVD0
+#define BF_USBCTRL_TXFILLTUNING_RSVD0_V(e)          BF_USBCTRL_TXFILLTUNING_RSVD0(BV_USBCTRL_TXFILLTUNING_RSVD0__##e)
+#define BFM_USBCTRL_TXFILLTUNING_RSVD0_V(v)         BM_USBCTRL_TXFILLTUNING_RSVD0
+#define BP_USBCTRL_TXFILLTUNING_TXSCHOH             0
+#define BM_USBCTRL_TXFILLTUNING_TXSCHOH             0x7f
+#define BF_USBCTRL_TXFILLTUNING_TXSCHOH(v)          (((v) & 0x7f) << 0)
+#define BFM_USBCTRL_TXFILLTUNING_TXSCHOH(v)         BM_USBCTRL_TXFILLTUNING_TXSCHOH
+#define BF_USBCTRL_TXFILLTUNING_TXSCHOH_V(e)        BF_USBCTRL_TXFILLTUNING_TXSCHOH(BV_USBCTRL_TXFILLTUNING_TXSCHOH__##e)
+#define BFM_USBCTRL_TXFILLTUNING_TXSCHOH_V(v)       BM_USBCTRL_TXFILLTUNING_TXSCHOH
+
+#define HW_USBCTRL_IC_USB                       HW(USBCTRL_IC_USB)
+#define HWA_USBCTRL_IC_USB                      (0x80080000 + 0x16c)
+#define HWT_USBCTRL_IC_USB                      HWIO_32_RW
+#define HWN_USBCTRL_IC_USB                      USBCTRL_IC_USB
+#define HWI_USBCTRL_IC_USB                      
+#define BP_USBCTRL_IC_USB_RSVD                  4
+#define BM_USBCTRL_IC_USB_RSVD                  0xfffffff0
+#define BF_USBCTRL_IC_USB_RSVD(v)               (((v) & 0xfffffff) << 4)
+#define BFM_USBCTRL_IC_USB_RSVD(v)              BM_USBCTRL_IC_USB_RSVD
+#define BF_USBCTRL_IC_USB_RSVD_V(e)             BF_USBCTRL_IC_USB_RSVD(BV_USBCTRL_IC_USB_RSVD__##e)
+#define BFM_USBCTRL_IC_USB_RSVD_V(v)            BM_USBCTRL_IC_USB_RSVD
+#define BP_USBCTRL_IC_USB_IC_ENABLE             3
+#define BM_USBCTRL_IC_USB_IC_ENABLE             0x8
+#define BF_USBCTRL_IC_USB_IC_ENABLE(v)          (((v) & 0x1) << 3)
+#define BFM_USBCTRL_IC_USB_IC_ENABLE(v)         BM_USBCTRL_IC_USB_IC_ENABLE
+#define BF_USBCTRL_IC_USB_IC_ENABLE_V(e)        BF_USBCTRL_IC_USB_IC_ENABLE(BV_USBCTRL_IC_USB_IC_ENABLE__##e)
+#define BFM_USBCTRL_IC_USB_IC_ENABLE_V(v)       BM_USBCTRL_IC_USB_IC_ENABLE
+#define BP_USBCTRL_IC_USB_IC_VDD                0
+#define BM_USBCTRL_IC_USB_IC_VDD                0x7
+#define BV_USBCTRL_IC_USB_IC_VDD__VOLTAGE_NONE  0x0
+#define BV_USBCTRL_IC_USB_IC_VDD__VOLTAGE_1_0   0x1
+#define BV_USBCTRL_IC_USB_IC_VDD__VOLTAGE_1_2   0x2
+#define BV_USBCTRL_IC_USB_IC_VDD__VOLTAGE_1_5   0x3
+#define BV_USBCTRL_IC_USB_IC_VDD__VOLTAGE_1_8   0x4
+#define BV_USBCTRL_IC_USB_IC_VDD__VOLTAGE_3_0   0x5
+#define BV_USBCTRL_IC_USB_IC_VDD__RESERVED0     0x6
+#define BV_USBCTRL_IC_USB_IC_VDD__RESERVED1     0x7
+#define BF_USBCTRL_IC_USB_IC_VDD(v)             (((v) & 0x7) << 0)
+#define BFM_USBCTRL_IC_USB_IC_VDD(v)            BM_USBCTRL_IC_USB_IC_VDD
+#define BF_USBCTRL_IC_USB_IC_VDD_V(e)           BF_USBCTRL_IC_USB_IC_VDD(BV_USBCTRL_IC_USB_IC_VDD__##e)
+#define BFM_USBCTRL_IC_USB_IC_VDD_V(v)          BM_USBCTRL_IC_USB_IC_VDD
+
+#define HW_USBCTRL_ULPI                 HW(USBCTRL_ULPI)
+#define HWA_USBCTRL_ULPI                (0x80080000 + 0x170)
+#define HWT_USBCTRL_ULPI                HWIO_32_RW
+#define HWN_USBCTRL_ULPI                USBCTRL_ULPI
+#define HWI_USBCTRL_ULPI                
+#define BP_USBCTRL_ULPI_ULPIWU          31
+#define BM_USBCTRL_ULPI_ULPIWU          0x80000000
+#define BF_USBCTRL_ULPI_ULPIWU(v)       (((v) & 0x1) << 31)
+#define BFM_USBCTRL_ULPI_ULPIWU(v)      BM_USBCTRL_ULPI_ULPIWU
+#define BF_USBCTRL_ULPI_ULPIWU_V(e)     BF_USBCTRL_ULPI_ULPIWU(BV_USBCTRL_ULPI_ULPIWU__##e)
+#define BFM_USBCTRL_ULPI_ULPIWU_V(v)    BM_USBCTRL_ULPI_ULPIWU
+#define BP_USBCTRL_ULPI_ULPIRUN         30
+#define BM_USBCTRL_ULPI_ULPIRUN         0x40000000
+#define BF_USBCTRL_ULPI_ULPIRUN(v)      (((v) & 0x1) << 30)
+#define BFM_USBCTRL_ULPI_ULPIRUN(v)     BM_USBCTRL_ULPI_ULPIRUN
+#define BF_USBCTRL_ULPI_ULPIRUN_V(e)    BF_USBCTRL_ULPI_ULPIRUN(BV_USBCTRL_ULPI_ULPIRUN__##e)
+#define BFM_USBCTRL_ULPI_ULPIRUN_V(v)   BM_USBCTRL_ULPI_ULPIRUN
+#define BP_USBCTRL_ULPI_ULPIRW          29
+#define BM_USBCTRL_ULPI_ULPIRW          0x20000000
+#define BF_USBCTRL_ULPI_ULPIRW(v)       (((v) & 0x1) << 29)
+#define BFM_USBCTRL_ULPI_ULPIRW(v)      BM_USBCTRL_ULPI_ULPIRW
+#define BF_USBCTRL_ULPI_ULPIRW_V(e)     BF_USBCTRL_ULPI_ULPIRW(BV_USBCTRL_ULPI_ULPIRW__##e)
+#define BFM_USBCTRL_ULPI_ULPIRW_V(v)    BM_USBCTRL_ULPI_ULPIRW
+#define BP_USBCTRL_ULPI_RSVD0           28
+#define BM_USBCTRL_ULPI_RSVD0           0x10000000
+#define BF_USBCTRL_ULPI_RSVD0(v)        (((v) & 0x1) << 28)
+#define BFM_USBCTRL_ULPI_RSVD0(v)       BM_USBCTRL_ULPI_RSVD0
+#define BF_USBCTRL_ULPI_RSVD0_V(e)      BF_USBCTRL_ULPI_RSVD0(BV_USBCTRL_ULPI_RSVD0__##e)
+#define BFM_USBCTRL_ULPI_RSVD0_V(v)     BM_USBCTRL_ULPI_RSVD0
+#define BP_USBCTRL_ULPI_ULPISS          27
+#define BM_USBCTRL_ULPI_ULPISS          0x8000000
+#define BF_USBCTRL_ULPI_ULPISS(v)       (((v) & 0x1) << 27)
+#define BFM_USBCTRL_ULPI_ULPISS(v)      BM_USBCTRL_ULPI_ULPISS
+#define BF_USBCTRL_ULPI_ULPISS_V(e)     BF_USBCTRL_ULPI_ULPISS(BV_USBCTRL_ULPI_ULPISS__##e)
+#define BFM_USBCTRL_ULPI_ULPISS_V(v)    BM_USBCTRL_ULPI_ULPISS
+#define BP_USBCTRL_ULPI_ULPIPORT        24
+#define BM_USBCTRL_ULPI_ULPIPORT        0x7000000
+#define BF_USBCTRL_ULPI_ULPIPORT(v)     (((v) & 0x7) << 24)
+#define BFM_USBCTRL_ULPI_ULPIPORT(v)    BM_USBCTRL_ULPI_ULPIPORT
+#define BF_USBCTRL_ULPI_ULPIPORT_V(e)   BF_USBCTRL_ULPI_ULPIPORT(BV_USBCTRL_ULPI_ULPIPORT__##e)
+#define BFM_USBCTRL_ULPI_ULPIPORT_V(v)  BM_USBCTRL_ULPI_ULPIPORT
+#define BP_USBCTRL_ULPI_ULPIADDR        16
+#define BM_USBCTRL_ULPI_ULPIADDR        0xff0000
+#define BF_USBCTRL_ULPI_ULPIADDR(v)     (((v) & 0xff) << 16)
+#define BFM_USBCTRL_ULPI_ULPIADDR(v)    BM_USBCTRL_ULPI_ULPIADDR
+#define BF_USBCTRL_ULPI_ULPIADDR_V(e)   BF_USBCTRL_ULPI_ULPIADDR(BV_USBCTRL_ULPI_ULPIADDR__##e)
+#define BFM_USBCTRL_ULPI_ULPIADDR_V(v)  BM_USBCTRL_ULPI_ULPIADDR
+#define BP_USBCTRL_ULPI_ULPIDATRD       8
+#define BM_USBCTRL_ULPI_ULPIDATRD       0xff00
+#define BF_USBCTRL_ULPI_ULPIDATRD(v)    (((v) & 0xff) << 8)
+#define BFM_USBCTRL_ULPI_ULPIDATRD(v)   BM_USBCTRL_ULPI_ULPIDATRD
+#define BF_USBCTRL_ULPI_ULPIDATRD_V(e)  BF_USBCTRL_ULPI_ULPIDATRD(BV_USBCTRL_ULPI_ULPIDATRD__##e)
+#define BFM_USBCTRL_ULPI_ULPIDATRD_V(v) BM_USBCTRL_ULPI_ULPIDATRD
+#define BP_USBCTRL_ULPI_ULPIDATWR       0
+#define BM_USBCTRL_ULPI_ULPIDATWR       0xff
+#define BF_USBCTRL_ULPI_ULPIDATWR(v)    (((v) & 0xff) << 0)
+#define BFM_USBCTRL_ULPI_ULPIDATWR(v)   BM_USBCTRL_ULPI_ULPIDATWR
+#define BF_USBCTRL_ULPI_ULPIDATWR_V(e)  BF_USBCTRL_ULPI_ULPIDATWR(BV_USBCTRL_ULPI_ULPIDATWR__##e)
+#define BFM_USBCTRL_ULPI_ULPIDATWR_V(v) BM_USBCTRL_ULPI_ULPIDATWR
+
+#define HW_USBCTRL_ENDPTNAK             HW(USBCTRL_ENDPTNAK)
+#define HWA_USBCTRL_ENDPTNAK            (0x80080000 + 0x178)
+#define HWT_USBCTRL_ENDPTNAK            HWIO_32_RW
+#define HWN_USBCTRL_ENDPTNAK            USBCTRL_ENDPTNAK
+#define HWI_USBCTRL_ENDPTNAK            
+#define BP_USBCTRL_ENDPTNAK_RSVD1       21
+#define BM_USBCTRL_ENDPTNAK_RSVD1       0xffe00000
+#define BF_USBCTRL_ENDPTNAK_RSVD1(v)    (((v) & 0x7ff) << 21)
+#define BFM_USBCTRL_ENDPTNAK_RSVD1(v)   BM_USBCTRL_ENDPTNAK_RSVD1
+#define BF_USBCTRL_ENDPTNAK_RSVD1_V(e)  BF_USBCTRL_ENDPTNAK_RSVD1(BV_USBCTRL_ENDPTNAK_RSVD1__##e)
+#define BFM_USBCTRL_ENDPTNAK_RSVD1_V(v) BM_USBCTRL_ENDPTNAK_RSVD1
+#define BP_USBCTRL_ENDPTNAK_EPTN        16
+#define BM_USBCTRL_ENDPTNAK_EPTN        0x1f0000
+#define BF_USBCTRL_ENDPTNAK_EPTN(v)     (((v) & 0x1f) << 16)
+#define BFM_USBCTRL_ENDPTNAK_EPTN(v)    BM_USBCTRL_ENDPTNAK_EPTN
+#define BF_USBCTRL_ENDPTNAK_EPTN_V(e)   BF_USBCTRL_ENDPTNAK_EPTN(BV_USBCTRL_ENDPTNAK_EPTN__##e)
+#define BFM_USBCTRL_ENDPTNAK_EPTN_V(v)  BM_USBCTRL_ENDPTNAK_EPTN
+#define BP_USBCTRL_ENDPTNAK_RSVD0       5
+#define BM_USBCTRL_ENDPTNAK_RSVD0       0xffe0
+#define BF_USBCTRL_ENDPTNAK_RSVD0(v)    (((v) & 0x7ff) << 5)
+#define BFM_USBCTRL_ENDPTNAK_RSVD0(v)   BM_USBCTRL_ENDPTNAK_RSVD0
+#define BF_USBCTRL_ENDPTNAK_RSVD0_V(e)  BF_USBCTRL_ENDPTNAK_RSVD0(BV_USBCTRL_ENDPTNAK_RSVD0__##e)
+#define BFM_USBCTRL_ENDPTNAK_RSVD0_V(v) BM_USBCTRL_ENDPTNAK_RSVD0
+#define BP_USBCTRL_ENDPTNAK_EPRN        0
+#define BM_USBCTRL_ENDPTNAK_EPRN        0x1f
+#define BF_USBCTRL_ENDPTNAK_EPRN(v)     (((v) & 0x1f) << 0)
+#define BFM_USBCTRL_ENDPTNAK_EPRN(v)    BM_USBCTRL_ENDPTNAK_EPRN
+#define BF_USBCTRL_ENDPTNAK_EPRN_V(e)   BF_USBCTRL_ENDPTNAK_EPRN(BV_USBCTRL_ENDPTNAK_EPRN__##e)
+#define BFM_USBCTRL_ENDPTNAK_EPRN_V(v)  BM_USBCTRL_ENDPTNAK_EPRN
+
+#define HW_USBCTRL_ENDPTNAKEN               HW(USBCTRL_ENDPTNAKEN)
+#define HWA_USBCTRL_ENDPTNAKEN              (0x80080000 + 0x17c)
+#define HWT_USBCTRL_ENDPTNAKEN              HWIO_32_RW
+#define HWN_USBCTRL_ENDPTNAKEN              USBCTRL_ENDPTNAKEN
+#define HWI_USBCTRL_ENDPTNAKEN              
+#define BP_USBCTRL_ENDPTNAKEN_RSVD1         21
+#define BM_USBCTRL_ENDPTNAKEN_RSVD1         0xffe00000
+#define BF_USBCTRL_ENDPTNAKEN_RSVD1(v)      (((v) & 0x7ff) << 21)
+#define BFM_USBCTRL_ENDPTNAKEN_RSVD1(v)     BM_USBCTRL_ENDPTNAKEN_RSVD1
+#define BF_USBCTRL_ENDPTNAKEN_RSVD1_V(e)    BF_USBCTRL_ENDPTNAKEN_RSVD1(BV_USBCTRL_ENDPTNAKEN_RSVD1__##e)
+#define BFM_USBCTRL_ENDPTNAKEN_RSVD1_V(v)   BM_USBCTRL_ENDPTNAKEN_RSVD1
+#define BP_USBCTRL_ENDPTNAKEN_EPTNE         16
+#define BM_USBCTRL_ENDPTNAKEN_EPTNE         0x1f0000
+#define BF_USBCTRL_ENDPTNAKEN_EPTNE(v)      (((v) & 0x1f) << 16)
+#define BFM_USBCTRL_ENDPTNAKEN_EPTNE(v)     BM_USBCTRL_ENDPTNAKEN_EPTNE
+#define BF_USBCTRL_ENDPTNAKEN_EPTNE_V(e)    BF_USBCTRL_ENDPTNAKEN_EPTNE(BV_USBCTRL_ENDPTNAKEN_EPTNE__##e)
+#define BFM_USBCTRL_ENDPTNAKEN_EPTNE_V(v)   BM_USBCTRL_ENDPTNAKEN_EPTNE
+#define BP_USBCTRL_ENDPTNAKEN_RSVD0         5
+#define BM_USBCTRL_ENDPTNAKEN_RSVD0         0xffe0
+#define BF_USBCTRL_ENDPTNAKEN_RSVD0(v)      (((v) & 0x7ff) << 5)
+#define BFM_USBCTRL_ENDPTNAKEN_RSVD0(v)     BM_USBCTRL_ENDPTNAKEN_RSVD0
+#define BF_USBCTRL_ENDPTNAKEN_RSVD0_V(e)    BF_USBCTRL_ENDPTNAKEN_RSVD0(BV_USBCTRL_ENDPTNAKEN_RSVD0__##e)
+#define BFM_USBCTRL_ENDPTNAKEN_RSVD0_V(v)   BM_USBCTRL_ENDPTNAKEN_RSVD0
+#define BP_USBCTRL_ENDPTNAKEN_EPRNE         0
+#define BM_USBCTRL_ENDPTNAKEN_EPRNE         0x1f
+#define BF_USBCTRL_ENDPTNAKEN_EPRNE(v)      (((v) & 0x1f) << 0)
+#define BFM_USBCTRL_ENDPTNAKEN_EPRNE(v)     BM_USBCTRL_ENDPTNAKEN_EPRNE
+#define BF_USBCTRL_ENDPTNAKEN_EPRNE_V(e)    BF_USBCTRL_ENDPTNAKEN_EPRNE(BV_USBCTRL_ENDPTNAKEN_EPRNE__##e)
+#define BFM_USBCTRL_ENDPTNAKEN_EPRNE_V(v)   BM_USBCTRL_ENDPTNAKEN_EPRNE
+
+#define HW_USBCTRL_PORTSC1                              HW(USBCTRL_PORTSC1)
+#define HWA_USBCTRL_PORTSC1                             (0x80080000 + 0x184)
+#define HWT_USBCTRL_PORTSC1                             HWIO_32_RW
+#define HWN_USBCTRL_PORTSC1                             USBCTRL_PORTSC1
+#define HWI_USBCTRL_PORTSC1                             
+#define BP_USBCTRL_PORTSC1_PTS                          30
+#define BM_USBCTRL_PORTSC1_PTS                          0xc0000000
+#define BV_USBCTRL_PORTSC1_PTS__UTMI                    0x0
+#define BV_USBCTRL_PORTSC1_PTS__PHIL                    0x1
+#define BV_USBCTRL_PORTSC1_PTS__ULPI                    0x2
+#define BV_USBCTRL_PORTSC1_PTS__SERIAL                  0x3
+#define BF_USBCTRL_PORTSC1_PTS(v)                       (((v) & 0x3) << 30)
+#define BFM_USBCTRL_PORTSC1_PTS(v)                      BM_USBCTRL_PORTSC1_PTS
+#define BF_USBCTRL_PORTSC1_PTS_V(e)                     BF_USBCTRL_PORTSC1_PTS(BV_USBCTRL_PORTSC1_PTS__##e)
+#define BFM_USBCTRL_PORTSC1_PTS_V(v)                    BM_USBCTRL_PORTSC1_PTS
+#define BP_USBCTRL_PORTSC1_STS                          29
+#define BM_USBCTRL_PORTSC1_STS                          0x20000000
+#define BF_USBCTRL_PORTSC1_STS(v)                       (((v) & 0x1) << 29)
+#define BFM_USBCTRL_PORTSC1_STS(v)                      BM_USBCTRL_PORTSC1_STS
+#define BF_USBCTRL_PORTSC1_STS_V(e)                     BF_USBCTRL_PORTSC1_STS(BV_USBCTRL_PORTSC1_STS__##e)
+#define BFM_USBCTRL_PORTSC1_STS_V(v)                    BM_USBCTRL_PORTSC1_STS
+#define BP_USBCTRL_PORTSC1_PTW                          28
+#define BM_USBCTRL_PORTSC1_PTW                          0x10000000
+#define BF_USBCTRL_PORTSC1_PTW(v)                       (((v) & 0x1) << 28)
+#define BFM_USBCTRL_PORTSC1_PTW(v)                      BM_USBCTRL_PORTSC1_PTW
+#define BF_USBCTRL_PORTSC1_PTW_V(e)                     BF_USBCTRL_PORTSC1_PTW(BV_USBCTRL_PORTSC1_PTW__##e)
+#define BFM_USBCTRL_PORTSC1_PTW_V(v)                    BM_USBCTRL_PORTSC1_PTW
+#define BP_USBCTRL_PORTSC1_PSPD                         26
+#define BM_USBCTRL_PORTSC1_PSPD                         0xc000000
+#define BV_USBCTRL_PORTSC1_PSPD__FULL                   0x0
+#define BV_USBCTRL_PORTSC1_PSPD__LOW                    0x1
+#define BV_USBCTRL_PORTSC1_PSPD__HIGH                   0x2
+#define BF_USBCTRL_PORTSC1_PSPD(v)                      (((v) & 0x3) << 26)
+#define BFM_USBCTRL_PORTSC1_PSPD(v)                     BM_USBCTRL_PORTSC1_PSPD
+#define BF_USBCTRL_PORTSC1_PSPD_V(e)                    BF_USBCTRL_PORTSC1_PSPD(BV_USBCTRL_PORTSC1_PSPD__##e)
+#define BFM_USBCTRL_PORTSC1_PSPD_V(v)                   BM_USBCTRL_PORTSC1_PSPD
+#define BP_USBCTRL_PORTSC1_SRT                          25
+#define BM_USBCTRL_PORTSC1_SRT                          0x2000000
+#define BF_USBCTRL_PORTSC1_SRT(v)                       (((v) & 0x1) << 25)
+#define BFM_USBCTRL_PORTSC1_SRT(v)                      BM_USBCTRL_PORTSC1_SRT
+#define BF_USBCTRL_PORTSC1_SRT_V(e)                     BF_USBCTRL_PORTSC1_SRT(BV_USBCTRL_PORTSC1_SRT__##e)
+#define BFM_USBCTRL_PORTSC1_SRT_V(v)                    BM_USBCTRL_PORTSC1_SRT
+#define BP_USBCTRL_PORTSC1_PFSC                         24
+#define BM_USBCTRL_PORTSC1_PFSC                         0x1000000
+#define BF_USBCTRL_PORTSC1_PFSC(v)                      (((v) & 0x1) << 24)
+#define BFM_USBCTRL_PORTSC1_PFSC(v)                     BM_USBCTRL_PORTSC1_PFSC
+#define BF_USBCTRL_PORTSC1_PFSC_V(e)                    BF_USBCTRL_PORTSC1_PFSC(BV_USBCTRL_PORTSC1_PFSC__##e)
+#define BFM_USBCTRL_PORTSC1_PFSC_V(v)                   BM_USBCTRL_PORTSC1_PFSC
+#define BP_USBCTRL_PORTSC1_PHCD                         23
+#define BM_USBCTRL_PORTSC1_PHCD                         0x800000
+#define BF_USBCTRL_PORTSC1_PHCD(v)                      (((v) & 0x1) << 23)
+#define BFM_USBCTRL_PORTSC1_PHCD(v)                     BM_USBCTRL_PORTSC1_PHCD
+#define BF_USBCTRL_PORTSC1_PHCD_V(e)                    BF_USBCTRL_PORTSC1_PHCD(BV_USBCTRL_PORTSC1_PHCD__##e)
+#define BFM_USBCTRL_PORTSC1_PHCD_V(v)                   BM_USBCTRL_PORTSC1_PHCD
+#define BP_USBCTRL_PORTSC1_WKOC                         22
+#define BM_USBCTRL_PORTSC1_WKOC                         0x400000
+#define BF_USBCTRL_PORTSC1_WKOC(v)                      (((v) & 0x1) << 22)
+#define BFM_USBCTRL_PORTSC1_WKOC(v)                     BM_USBCTRL_PORTSC1_WKOC
+#define BF_USBCTRL_PORTSC1_WKOC_V(e)                    BF_USBCTRL_PORTSC1_WKOC(BV_USBCTRL_PORTSC1_WKOC__##e)
+#define BFM_USBCTRL_PORTSC1_WKOC_V(v)                   BM_USBCTRL_PORTSC1_WKOC
+#define BP_USBCTRL_PORTSC1_WKDS                         21
+#define BM_USBCTRL_PORTSC1_WKDS                         0x200000
+#define BF_USBCTRL_PORTSC1_WKDS(v)                      (((v) & 0x1) << 21)
+#define BFM_USBCTRL_PORTSC1_WKDS(v)                     BM_USBCTRL_PORTSC1_WKDS
+#define BF_USBCTRL_PORTSC1_WKDS_V(e)                    BF_USBCTRL_PORTSC1_WKDS(BV_USBCTRL_PORTSC1_WKDS__##e)
+#define BFM_USBCTRL_PORTSC1_WKDS_V(v)                   BM_USBCTRL_PORTSC1_WKDS
+#define BP_USBCTRL_PORTSC1_WKCN                         20
+#define BM_USBCTRL_PORTSC1_WKCN                         0x100000
+#define BF_USBCTRL_PORTSC1_WKCN(v)                      (((v) & 0x1) << 20)
+#define BFM_USBCTRL_PORTSC1_WKCN(v)                     BM_USBCTRL_PORTSC1_WKCN
+#define BF_USBCTRL_PORTSC1_WKCN_V(e)                    BF_USBCTRL_PORTSC1_WKCN(BV_USBCTRL_PORTSC1_WKCN__##e)
+#define BFM_USBCTRL_PORTSC1_WKCN_V(v)                   BM_USBCTRL_PORTSC1_WKCN
+#define BP_USBCTRL_PORTSC1_PTC                          16
+#define BM_USBCTRL_PORTSC1_PTC                          0xf0000
+#define BV_USBCTRL_PORTSC1_PTC__TEST_DISABLE            0x0
+#define BV_USBCTRL_PORTSC1_PTC__TEST_J_STATE            0x1
+#define BV_USBCTRL_PORTSC1_PTC__TEST_K_STATE            0x2
+#define BV_USBCTRL_PORTSC1_PTC__TEST_J_SE0_NAK          0x3
+#define BV_USBCTRL_PORTSC1_PTC__TEST_PACKET             0x4
+#define BV_USBCTRL_PORTSC1_PTC__TEST_FORCE_ENABLE_HS    0x5
+#define BV_USBCTRL_PORTSC1_PTC__TEST_FORCE_ENABLE_FS    0x6
+#define BV_USBCTRL_PORTSC1_PTC__TEST_FORCE_ENABLE_LS    0x7
+#define BF_USBCTRL_PORTSC1_PTC(v)                       (((v) & 0xf) << 16)
+#define BFM_USBCTRL_PORTSC1_PTC(v)                      BM_USBCTRL_PORTSC1_PTC
+#define BF_USBCTRL_PORTSC1_PTC_V(e)                     BF_USBCTRL_PORTSC1_PTC(BV_USBCTRL_PORTSC1_PTC__##e)
+#define BFM_USBCTRL_PORTSC1_PTC_V(v)                    BM_USBCTRL_PORTSC1_PTC
+#define BP_USBCTRL_PORTSC1_PIC                          14
+#define BM_USBCTRL_PORTSC1_PIC                          0xc000
+#define BV_USBCTRL_PORTSC1_PIC__OFF                     0x0
+#define BV_USBCTRL_PORTSC1_PIC__AMBER                   0x1
+#define BV_USBCTRL_PORTSC1_PIC__GREEN                   0x2
+#define BV_USBCTRL_PORTSC1_PIC__UNDEF                   0x3
+#define BF_USBCTRL_PORTSC1_PIC(v)                       (((v) & 0x3) << 14)
+#define BFM_USBCTRL_PORTSC1_PIC(v)                      BM_USBCTRL_PORTSC1_PIC
+#define BF_USBCTRL_PORTSC1_PIC_V(e)                     BF_USBCTRL_PORTSC1_PIC(BV_USBCTRL_PORTSC1_PIC__##e)
+#define BFM_USBCTRL_PORTSC1_PIC_V(v)                    BM_USBCTRL_PORTSC1_PIC
+#define BP_USBCTRL_PORTSC1_PO                           13
+#define BM_USBCTRL_PORTSC1_PO                           0x2000
+#define BF_USBCTRL_PORTSC1_PO(v)                        (((v) & 0x1) << 13)
+#define BFM_USBCTRL_PORTSC1_PO(v)                       BM_USBCTRL_PORTSC1_PO
+#define BF_USBCTRL_PORTSC1_PO_V(e)                      BF_USBCTRL_PORTSC1_PO(BV_USBCTRL_PORTSC1_PO__##e)
+#define BFM_USBCTRL_PORTSC1_PO_V(v)                     BM_USBCTRL_PORTSC1_PO
+#define BP_USBCTRL_PORTSC1_PP                           12
+#define BM_USBCTRL_PORTSC1_PP                           0x1000
+#define BF_USBCTRL_PORTSC1_PP(v)                        (((v) & 0x1) << 12)
+#define BFM_USBCTRL_PORTSC1_PP(v)                       BM_USBCTRL_PORTSC1_PP
+#define BF_USBCTRL_PORTSC1_PP_V(e)                      BF_USBCTRL_PORTSC1_PP(BV_USBCTRL_PORTSC1_PP__##e)
+#define BFM_USBCTRL_PORTSC1_PP_V(v)                     BM_USBCTRL_PORTSC1_PP
+#define BP_USBCTRL_PORTSC1_LS                           10
+#define BM_USBCTRL_PORTSC1_LS                           0xc00
+#define BV_USBCTRL_PORTSC1_LS__SE0                      0x0
+#define BV_USBCTRL_PORTSC1_LS__K_STATE                  0x1
+#define BV_USBCTRL_PORTSC1_LS__J_STATE                  0x2
+#define BV_USBCTRL_PORTSC1_LS__UNDEF                    0x3
+#define BF_USBCTRL_PORTSC1_LS(v)                        (((v) & 0x3) << 10)
+#define BFM_USBCTRL_PORTSC1_LS(v)                       BM_USBCTRL_PORTSC1_LS
+#define BF_USBCTRL_PORTSC1_LS_V(e)                      BF_USBCTRL_PORTSC1_LS(BV_USBCTRL_PORTSC1_LS__##e)
+#define BFM_USBCTRL_PORTSC1_LS_V(v)                     BM_USBCTRL_PORTSC1_LS
+#define BP_USBCTRL_PORTSC1_HSP                          9
+#define BM_USBCTRL_PORTSC1_HSP                          0x200
+#define BF_USBCTRL_PORTSC1_HSP(v)                       (((v) & 0x1) << 9)
+#define BFM_USBCTRL_PORTSC1_HSP(v)                      BM_USBCTRL_PORTSC1_HSP
+#define BF_USBCTRL_PORTSC1_HSP_V(e)                     BF_USBCTRL_PORTSC1_HSP(BV_USBCTRL_PORTSC1_HSP__##e)
+#define BFM_USBCTRL_PORTSC1_HSP_V(v)                    BM_USBCTRL_PORTSC1_HSP
+#define BP_USBCTRL_PORTSC1_PR                           8
+#define BM_USBCTRL_PORTSC1_PR                           0x100
+#define BF_USBCTRL_PORTSC1_PR(v)                        (((v) & 0x1) << 8)
+#define BFM_USBCTRL_PORTSC1_PR(v)                       BM_USBCTRL_PORTSC1_PR
+#define BF_USBCTRL_PORTSC1_PR_V(e)                      BF_USBCTRL_PORTSC1_PR(BV_USBCTRL_PORTSC1_PR__##e)
+#define BFM_USBCTRL_PORTSC1_PR_V(v)                     BM_USBCTRL_PORTSC1_PR
+#define BP_USBCTRL_PORTSC1_SUSP                         7
+#define BM_USBCTRL_PORTSC1_SUSP                         0x80
+#define BF_USBCTRL_PORTSC1_SUSP(v)                      (((v) & 0x1) << 7)
+#define BFM_USBCTRL_PORTSC1_SUSP(v)                     BM_USBCTRL_PORTSC1_SUSP
+#define BF_USBCTRL_PORTSC1_SUSP_V(e)                    BF_USBCTRL_PORTSC1_SUSP(BV_USBCTRL_PORTSC1_SUSP__##e)
+#define BFM_USBCTRL_PORTSC1_SUSP_V(v)                   BM_USBCTRL_PORTSC1_SUSP
+#define BP_USBCTRL_PORTSC1_FPR                          6
+#define BM_USBCTRL_PORTSC1_FPR                          0x40
+#define BF_USBCTRL_PORTSC1_FPR(v)                       (((v) & 0x1) << 6)
+#define BFM_USBCTRL_PORTSC1_FPR(v)                      BM_USBCTRL_PORTSC1_FPR
+#define BF_USBCTRL_PORTSC1_FPR_V(e)                     BF_USBCTRL_PORTSC1_FPR(BV_USBCTRL_PORTSC1_FPR__##e)
+#define BFM_USBCTRL_PORTSC1_FPR_V(v)                    BM_USBCTRL_PORTSC1_FPR
+#define BP_USBCTRL_PORTSC1_OCC                          5
+#define BM_USBCTRL_PORTSC1_OCC                          0x20
+#define BF_USBCTRL_PORTSC1_OCC(v)                       (((v) & 0x1) << 5)
+#define BFM_USBCTRL_PORTSC1_OCC(v)                      BM_USBCTRL_PORTSC1_OCC
+#define BF_USBCTRL_PORTSC1_OCC_V(e)                     BF_USBCTRL_PORTSC1_OCC(BV_USBCTRL_PORTSC1_OCC__##e)
+#define BFM_USBCTRL_PORTSC1_OCC_V(v)                    BM_USBCTRL_PORTSC1_OCC
+#define BP_USBCTRL_PORTSC1_OCA                          4
+#define BM_USBCTRL_PORTSC1_OCA                          0x10
+#define BF_USBCTRL_PORTSC1_OCA(v)                       (((v) & 0x1) << 4)
+#define BFM_USBCTRL_PORTSC1_OCA(v)                      BM_USBCTRL_PORTSC1_OCA
+#define BF_USBCTRL_PORTSC1_OCA_V(e)                     BF_USBCTRL_PORTSC1_OCA(BV_USBCTRL_PORTSC1_OCA__##e)
+#define BFM_USBCTRL_PORTSC1_OCA_V(v)                    BM_USBCTRL_PORTSC1_OCA
+#define BP_USBCTRL_PORTSC1_PEC                          3
+#define BM_USBCTRL_PORTSC1_PEC                          0x8
+#define BF_USBCTRL_PORTSC1_PEC(v)                       (((v) & 0x1) << 3)
+#define BFM_USBCTRL_PORTSC1_PEC(v)                      BM_USBCTRL_PORTSC1_PEC
+#define BF_USBCTRL_PORTSC1_PEC_V(e)                     BF_USBCTRL_PORTSC1_PEC(BV_USBCTRL_PORTSC1_PEC__##e)
+#define BFM_USBCTRL_PORTSC1_PEC_V(v)                    BM_USBCTRL_PORTSC1_PEC
+#define BP_USBCTRL_PORTSC1_PE                           2
+#define BM_USBCTRL_PORTSC1_PE                           0x4
+#define BF_USBCTRL_PORTSC1_PE(v)                        (((v) & 0x1) << 2)
+#define BFM_USBCTRL_PORTSC1_PE(v)                       BM_USBCTRL_PORTSC1_PE
+#define BF_USBCTRL_PORTSC1_PE_V(e)                      BF_USBCTRL_PORTSC1_PE(BV_USBCTRL_PORTSC1_PE__##e)
+#define BFM_USBCTRL_PORTSC1_PE_V(v)                     BM_USBCTRL_PORTSC1_PE
+#define BP_USBCTRL_PORTSC1_CSC                          1
+#define BM_USBCTRL_PORTSC1_CSC                          0x2
+#define BF_USBCTRL_PORTSC1_CSC(v)                       (((v) & 0x1) << 1)
+#define BFM_USBCTRL_PORTSC1_CSC(v)                      BM_USBCTRL_PORTSC1_CSC
+#define BF_USBCTRL_PORTSC1_CSC_V(e)                     BF_USBCTRL_PORTSC1_CSC(BV_USBCTRL_PORTSC1_CSC__##e)
+#define BFM_USBCTRL_PORTSC1_CSC_V(v)                    BM_USBCTRL_PORTSC1_CSC
+#define BP_USBCTRL_PORTSC1_CCS                          0
+#define BM_USBCTRL_PORTSC1_CCS                          0x1
+#define BF_USBCTRL_PORTSC1_CCS(v)                       (((v) & 0x1) << 0)
+#define BFM_USBCTRL_PORTSC1_CCS(v)                      BM_USBCTRL_PORTSC1_CCS
+#define BF_USBCTRL_PORTSC1_CCS_V(e)                     BF_USBCTRL_PORTSC1_CCS(BV_USBCTRL_PORTSC1_CCS__##e)
+#define BFM_USBCTRL_PORTSC1_CCS_V(v)                    BM_USBCTRL_PORTSC1_CCS
+
+#define HW_USBCTRL_OTGSC                HW(USBCTRL_OTGSC)
+#define HWA_USBCTRL_OTGSC               (0x80080000 + 0x1a4)
+#define HWT_USBCTRL_OTGSC               HWIO_32_RW
+#define HWN_USBCTRL_OTGSC               USBCTRL_OTGSC
+#define HWI_USBCTRL_OTGSC               
+#define BP_USBCTRL_OTGSC_RSVD2          31
+#define BM_USBCTRL_OTGSC_RSVD2          0x80000000
+#define BF_USBCTRL_OTGSC_RSVD2(v)       (((v) & 0x1) << 31)
+#define BFM_USBCTRL_OTGSC_RSVD2(v)      BM_USBCTRL_OTGSC_RSVD2
+#define BF_USBCTRL_OTGSC_RSVD2_V(e)     BF_USBCTRL_OTGSC_RSVD2(BV_USBCTRL_OTGSC_RSVD2__##e)
+#define BFM_USBCTRL_OTGSC_RSVD2_V(v)    BM_USBCTRL_OTGSC_RSVD2
+#define BP_USBCTRL_OTGSC_DPIE           30
+#define BM_USBCTRL_OTGSC_DPIE           0x40000000
+#define BF_USBCTRL_OTGSC_DPIE(v)        (((v) & 0x1) << 30)
+#define BFM_USBCTRL_OTGSC_DPIE(v)       BM_USBCTRL_OTGSC_DPIE
+#define BF_USBCTRL_OTGSC_DPIE_V(e)      BF_USBCTRL_OTGSC_DPIE(BV_USBCTRL_OTGSC_DPIE__##e)
+#define BFM_USBCTRL_OTGSC_DPIE_V(v)     BM_USBCTRL_OTGSC_DPIE
+#define BP_USBCTRL_OTGSC_ONEMSE         29
+#define BM_USBCTRL_OTGSC_ONEMSE         0x20000000
+#define BF_USBCTRL_OTGSC_ONEMSE(v)      (((v) & 0x1) << 29)
+#define BFM_USBCTRL_OTGSC_ONEMSE(v)     BM_USBCTRL_OTGSC_ONEMSE
+#define BF_USBCTRL_OTGSC_ONEMSE_V(e)    BF_USBCTRL_OTGSC_ONEMSE(BV_USBCTRL_OTGSC_ONEMSE__##e)
+#define BFM_USBCTRL_OTGSC_ONEMSE_V(v)   BM_USBCTRL_OTGSC_ONEMSE
+#define BP_USBCTRL_OTGSC_BSEIE          28
+#define BM_USBCTRL_OTGSC_BSEIE          0x10000000
+#define BF_USBCTRL_OTGSC_BSEIE(v)       (((v) & 0x1) << 28)
+#define BFM_USBCTRL_OTGSC_BSEIE(v)      BM_USBCTRL_OTGSC_BSEIE
+#define BF_USBCTRL_OTGSC_BSEIE_V(e)     BF_USBCTRL_OTGSC_BSEIE(BV_USBCTRL_OTGSC_BSEIE__##e)
+#define BFM_USBCTRL_OTGSC_BSEIE_V(v)    BM_USBCTRL_OTGSC_BSEIE
+#define BP_USBCTRL_OTGSC_BSVIE          27
+#define BM_USBCTRL_OTGSC_BSVIE          0x8000000
+#define BF_USBCTRL_OTGSC_BSVIE(v)       (((v) & 0x1) << 27)
+#define BFM_USBCTRL_OTGSC_BSVIE(v)      BM_USBCTRL_OTGSC_BSVIE
+#define BF_USBCTRL_OTGSC_BSVIE_V(e)     BF_USBCTRL_OTGSC_BSVIE(BV_USBCTRL_OTGSC_BSVIE__##e)
+#define BFM_USBCTRL_OTGSC_BSVIE_V(v)    BM_USBCTRL_OTGSC_BSVIE
+#define BP_USBCTRL_OTGSC_ASVIE          26
+#define BM_USBCTRL_OTGSC_ASVIE          0x4000000
+#define BF_USBCTRL_OTGSC_ASVIE(v)       (((v) & 0x1) << 26)
+#define BFM_USBCTRL_OTGSC_ASVIE(v)      BM_USBCTRL_OTGSC_ASVIE
+#define BF_USBCTRL_OTGSC_ASVIE_V(e)     BF_USBCTRL_OTGSC_ASVIE(BV_USBCTRL_OTGSC_ASVIE__##e)
+#define BFM_USBCTRL_OTGSC_ASVIE_V(v)    BM_USBCTRL_OTGSC_ASVIE
+#define BP_USBCTRL_OTGSC_AVVIE          25
+#define BM_USBCTRL_OTGSC_AVVIE          0x2000000
+#define BF_USBCTRL_OTGSC_AVVIE(v)       (((v) & 0x1) << 25)
+#define BFM_USBCTRL_OTGSC_AVVIE(v)      BM_USBCTRL_OTGSC_AVVIE
+#define BF_USBCTRL_OTGSC_AVVIE_V(e)     BF_USBCTRL_OTGSC_AVVIE(BV_USBCTRL_OTGSC_AVVIE__##e)
+#define BFM_USBCTRL_OTGSC_AVVIE_V(v)    BM_USBCTRL_OTGSC_AVVIE
+#define BP_USBCTRL_OTGSC_IDIE           24
+#define BM_USBCTRL_OTGSC_IDIE           0x1000000
+#define BF_USBCTRL_OTGSC_IDIE(v)        (((v) & 0x1) << 24)
+#define BFM_USBCTRL_OTGSC_IDIE(v)       BM_USBCTRL_OTGSC_IDIE
+#define BF_USBCTRL_OTGSC_IDIE_V(e)      BF_USBCTRL_OTGSC_IDIE(BV_USBCTRL_OTGSC_IDIE__##e)
+#define BFM_USBCTRL_OTGSC_IDIE_V(v)     BM_USBCTRL_OTGSC_IDIE
+#define BP_USBCTRL_OTGSC_RSVD1          23
+#define BM_USBCTRL_OTGSC_RSVD1          0x800000
+#define BF_USBCTRL_OTGSC_RSVD1(v)       (((v) & 0x1) << 23)
+#define BFM_USBCTRL_OTGSC_RSVD1(v)      BM_USBCTRL_OTGSC_RSVD1
+#define BF_USBCTRL_OTGSC_RSVD1_V(e)     BF_USBCTRL_OTGSC_RSVD1(BV_USBCTRL_OTGSC_RSVD1__##e)
+#define BFM_USBCTRL_OTGSC_RSVD1_V(v)    BM_USBCTRL_OTGSC_RSVD1
+#define BP_USBCTRL_OTGSC_DPIS           22
+#define BM_USBCTRL_OTGSC_DPIS           0x400000
+#define BF_USBCTRL_OTGSC_DPIS(v)        (((v) & 0x1) << 22)
+#define BFM_USBCTRL_OTGSC_DPIS(v)       BM_USBCTRL_OTGSC_DPIS
+#define BF_USBCTRL_OTGSC_DPIS_V(e)      BF_USBCTRL_OTGSC_DPIS(BV_USBCTRL_OTGSC_DPIS__##e)
+#define BFM_USBCTRL_OTGSC_DPIS_V(v)     BM_USBCTRL_OTGSC_DPIS
+#define BP_USBCTRL_OTGSC_ONEMSS         21
+#define BM_USBCTRL_OTGSC_ONEMSS         0x200000
+#define BF_USBCTRL_OTGSC_ONEMSS(v)      (((v) & 0x1) << 21)
+#define BFM_USBCTRL_OTGSC_ONEMSS(v)     BM_USBCTRL_OTGSC_ONEMSS
+#define BF_USBCTRL_OTGSC_ONEMSS_V(e)    BF_USBCTRL_OTGSC_ONEMSS(BV_USBCTRL_OTGSC_ONEMSS__##e)
+#define BFM_USBCTRL_OTGSC_ONEMSS_V(v)   BM_USBCTRL_OTGSC_ONEMSS
+#define BP_USBCTRL_OTGSC_BSEIS          20
+#define BM_USBCTRL_OTGSC_BSEIS          0x100000
+#define BF_USBCTRL_OTGSC_BSEIS(v)       (((v) & 0x1) << 20)
+#define BFM_USBCTRL_OTGSC_BSEIS(v)      BM_USBCTRL_OTGSC_BSEIS
+#define BF_USBCTRL_OTGSC_BSEIS_V(e)     BF_USBCTRL_OTGSC_BSEIS(BV_USBCTRL_OTGSC_BSEIS__##e)
+#define BFM_USBCTRL_OTGSC_BSEIS_V(v)    BM_USBCTRL_OTGSC_BSEIS
+#define BP_USBCTRL_OTGSC_BSVIS          19
+#define BM_USBCTRL_OTGSC_BSVIS          0x80000
+#define BF_USBCTRL_OTGSC_BSVIS(v)       (((v) & 0x1) << 19)
+#define BFM_USBCTRL_OTGSC_BSVIS(v)      BM_USBCTRL_OTGSC_BSVIS
+#define BF_USBCTRL_OTGSC_BSVIS_V(e)     BF_USBCTRL_OTGSC_BSVIS(BV_USBCTRL_OTGSC_BSVIS__##e)
+#define BFM_USBCTRL_OTGSC_BSVIS_V(v)    BM_USBCTRL_OTGSC_BSVIS
+#define BP_USBCTRL_OTGSC_ASVIS          18
+#define BM_USBCTRL_OTGSC_ASVIS          0x40000
+#define BF_USBCTRL_OTGSC_ASVIS(v)       (((v) & 0x1) << 18)
+#define BFM_USBCTRL_OTGSC_ASVIS(v)      BM_USBCTRL_OTGSC_ASVIS
+#define BF_USBCTRL_OTGSC_ASVIS_V(e)     BF_USBCTRL_OTGSC_ASVIS(BV_USBCTRL_OTGSC_ASVIS__##e)
+#define BFM_USBCTRL_OTGSC_ASVIS_V(v)    BM_USBCTRL_OTGSC_ASVIS
+#define BP_USBCTRL_OTGSC_AVVIS          17
+#define BM_USBCTRL_OTGSC_AVVIS          0x20000
+#define BF_USBCTRL_OTGSC_AVVIS(v)       (((v) & 0x1) << 17)
+#define BFM_USBCTRL_OTGSC_AVVIS(v)      BM_USBCTRL_OTGSC_AVVIS
+#define BF_USBCTRL_OTGSC_AVVIS_V(e)     BF_USBCTRL_OTGSC_AVVIS(BV_USBCTRL_OTGSC_AVVIS__##e)
+#define BFM_USBCTRL_OTGSC_AVVIS_V(v)    BM_USBCTRL_OTGSC_AVVIS
+#define BP_USBCTRL_OTGSC_IDIS           16
+#define BM_USBCTRL_OTGSC_IDIS           0x10000
+#define BF_USBCTRL_OTGSC_IDIS(v)        (((v) & 0x1) << 16)
+#define BFM_USBCTRL_OTGSC_IDIS(v)       BM_USBCTRL_OTGSC_IDIS
+#define BF_USBCTRL_OTGSC_IDIS_V(e)      BF_USBCTRL_OTGSC_IDIS(BV_USBCTRL_OTGSC_IDIS__##e)
+#define BFM_USBCTRL_OTGSC_IDIS_V(v)     BM_USBCTRL_OTGSC_IDIS
+#define BP_USBCTRL_OTGSC_RSVD0          15
+#define BM_USBCTRL_OTGSC_RSVD0          0x8000
+#define BF_USBCTRL_OTGSC_RSVD0(v)       (((v) & 0x1) << 15)
+#define BFM_USBCTRL_OTGSC_RSVD0(v)      BM_USBCTRL_OTGSC_RSVD0
+#define BF_USBCTRL_OTGSC_RSVD0_V(e)     BF_USBCTRL_OTGSC_RSVD0(BV_USBCTRL_OTGSC_RSVD0__##e)
+#define BFM_USBCTRL_OTGSC_RSVD0_V(v)    BM_USBCTRL_OTGSC_RSVD0
+#define BP_USBCTRL_OTGSC_DPS            14
+#define BM_USBCTRL_OTGSC_DPS            0x4000
+#define BF_USBCTRL_OTGSC_DPS(v)         (((v) & 0x1) << 14)
+#define BFM_USBCTRL_OTGSC_DPS(v)        BM_USBCTRL_OTGSC_DPS
+#define BF_USBCTRL_OTGSC_DPS_V(e)       BF_USBCTRL_OTGSC_DPS(BV_USBCTRL_OTGSC_DPS__##e)
+#define BFM_USBCTRL_OTGSC_DPS_V(v)      BM_USBCTRL_OTGSC_DPS
+#define BP_USBCTRL_OTGSC_ONEMST         13
+#define BM_USBCTRL_OTGSC_ONEMST         0x2000
+#define BF_USBCTRL_OTGSC_ONEMST(v)      (((v) & 0x1) << 13)
+#define BFM_USBCTRL_OTGSC_ONEMST(v)     BM_USBCTRL_OTGSC_ONEMST
+#define BF_USBCTRL_OTGSC_ONEMST_V(e)    BF_USBCTRL_OTGSC_ONEMST(BV_USBCTRL_OTGSC_ONEMST__##e)
+#define BFM_USBCTRL_OTGSC_ONEMST_V(v)   BM_USBCTRL_OTGSC_ONEMST
+#define BP_USBCTRL_OTGSC_BSE            12
+#define BM_USBCTRL_OTGSC_BSE            0x1000
+#define BF_USBCTRL_OTGSC_BSE(v)         (((v) & 0x1) << 12)
+#define BFM_USBCTRL_OTGSC_BSE(v)        BM_USBCTRL_OTGSC_BSE
+#define BF_USBCTRL_OTGSC_BSE_V(e)       BF_USBCTRL_OTGSC_BSE(BV_USBCTRL_OTGSC_BSE__##e)
+#define BFM_USBCTRL_OTGSC_BSE_V(v)      BM_USBCTRL_OTGSC_BSE
+#define BP_USBCTRL_OTGSC_BSV            11
+#define BM_USBCTRL_OTGSC_BSV            0x800
+#define BF_USBCTRL_OTGSC_BSV(v)         (((v) & 0x1) << 11)
+#define BFM_USBCTRL_OTGSC_BSV(v)        BM_USBCTRL_OTGSC_BSV
+#define BF_USBCTRL_OTGSC_BSV_V(e)       BF_USBCTRL_OTGSC_BSV(BV_USBCTRL_OTGSC_BSV__##e)
+#define BFM_USBCTRL_OTGSC_BSV_V(v)      BM_USBCTRL_OTGSC_BSV
+#define BP_USBCTRL_OTGSC_ASV            10
+#define BM_USBCTRL_OTGSC_ASV            0x400
+#define BF_USBCTRL_OTGSC_ASV(v)         (((v) & 0x1) << 10)
+#define BFM_USBCTRL_OTGSC_ASV(v)        BM_USBCTRL_OTGSC_ASV
+#define BF_USBCTRL_OTGSC_ASV_V(e)       BF_USBCTRL_OTGSC_ASV(BV_USBCTRL_OTGSC_ASV__##e)
+#define BFM_USBCTRL_OTGSC_ASV_V(v)      BM_USBCTRL_OTGSC_ASV
+#define BP_USBCTRL_OTGSC_AVV            9
+#define BM_USBCTRL_OTGSC_AVV            0x200
+#define BF_USBCTRL_OTGSC_AVV(v)         (((v) & 0x1) << 9)
+#define BFM_USBCTRL_OTGSC_AVV(v)        BM_USBCTRL_OTGSC_AVV
+#define BF_USBCTRL_OTGSC_AVV_V(e)       BF_USBCTRL_OTGSC_AVV(BV_USBCTRL_OTGSC_AVV__##e)
+#define BFM_USBCTRL_OTGSC_AVV_V(v)      BM_USBCTRL_OTGSC_AVV
+#define BP_USBCTRL_OTGSC_ID             8
+#define BM_USBCTRL_OTGSC_ID             0x100
+#define BF_USBCTRL_OTGSC_ID(v)          (((v) & 0x1) << 8)
+#define BFM_USBCTRL_OTGSC_ID(v)         BM_USBCTRL_OTGSC_ID
+#define BF_USBCTRL_OTGSC_ID_V(e)        BF_USBCTRL_OTGSC_ID(BV_USBCTRL_OTGSC_ID__##e)
+#define BFM_USBCTRL_OTGSC_ID_V(v)       BM_USBCTRL_OTGSC_ID
+#define BP_USBCTRL_OTGSC_HABA           7
+#define BM_USBCTRL_OTGSC_HABA           0x80
+#define BF_USBCTRL_OTGSC_HABA(v)        (((v) & 0x1) << 7)
+#define BFM_USBCTRL_OTGSC_HABA(v)       BM_USBCTRL_OTGSC_HABA
+#define BF_USBCTRL_OTGSC_HABA_V(e)      BF_USBCTRL_OTGSC_HABA(BV_USBCTRL_OTGSC_HABA__##e)
+#define BFM_USBCTRL_OTGSC_HABA_V(v)     BM_USBCTRL_OTGSC_HABA
+#define BP_USBCTRL_OTGSC_HADP           6
+#define BM_USBCTRL_OTGSC_HADP           0x40
+#define BF_USBCTRL_OTGSC_HADP(v)        (((v) & 0x1) << 6)
+#define BFM_USBCTRL_OTGSC_HADP(v)       BM_USBCTRL_OTGSC_HADP
+#define BF_USBCTRL_OTGSC_HADP_V(e)      BF_USBCTRL_OTGSC_HADP(BV_USBCTRL_OTGSC_HADP__##e)
+#define BFM_USBCTRL_OTGSC_HADP_V(v)     BM_USBCTRL_OTGSC_HADP
+#define BP_USBCTRL_OTGSC_IDPU           5
+#define BM_USBCTRL_OTGSC_IDPU           0x20
+#define BF_USBCTRL_OTGSC_IDPU(v)        (((v) & 0x1) << 5)
+#define BFM_USBCTRL_OTGSC_IDPU(v)       BM_USBCTRL_OTGSC_IDPU
+#define BF_USBCTRL_OTGSC_IDPU_V(e)      BF_USBCTRL_OTGSC_IDPU(BV_USBCTRL_OTGSC_IDPU__##e)
+#define BFM_USBCTRL_OTGSC_IDPU_V(v)     BM_USBCTRL_OTGSC_IDPU
+#define BP_USBCTRL_OTGSC_DP             4
+#define BM_USBCTRL_OTGSC_DP             0x10
+#define BF_USBCTRL_OTGSC_DP(v)          (((v) & 0x1) << 4)
+#define BFM_USBCTRL_OTGSC_DP(v)         BM_USBCTRL_OTGSC_DP
+#define BF_USBCTRL_OTGSC_DP_V(e)        BF_USBCTRL_OTGSC_DP(BV_USBCTRL_OTGSC_DP__##e)
+#define BFM_USBCTRL_OTGSC_DP_V(v)       BM_USBCTRL_OTGSC_DP
+#define BP_USBCTRL_OTGSC_OT             3
+#define BM_USBCTRL_OTGSC_OT             0x8
+#define BF_USBCTRL_OTGSC_OT(v)          (((v) & 0x1) << 3)
+#define BFM_USBCTRL_OTGSC_OT(v)         BM_USBCTRL_OTGSC_OT
+#define BF_USBCTRL_OTGSC_OT_V(e)        BF_USBCTRL_OTGSC_OT(BV_USBCTRL_OTGSC_OT__##e)
+#define BFM_USBCTRL_OTGSC_OT_V(v)       BM_USBCTRL_OTGSC_OT
+#define BP_USBCTRL_OTGSC_HAAR           2
+#define BM_USBCTRL_OTGSC_HAAR           0x4
+#define BF_USBCTRL_OTGSC_HAAR(v)        (((v) & 0x1) << 2)
+#define BFM_USBCTRL_OTGSC_HAAR(v)       BM_USBCTRL_OTGSC_HAAR
+#define BF_USBCTRL_OTGSC_HAAR_V(e)      BF_USBCTRL_OTGSC_HAAR(BV_USBCTRL_OTGSC_HAAR__##e)
+#define BFM_USBCTRL_OTGSC_HAAR_V(v)     BM_USBCTRL_OTGSC_HAAR
+#define BP_USBCTRL_OTGSC_VC             1
+#define BM_USBCTRL_OTGSC_VC             0x2
+#define BF_USBCTRL_OTGSC_VC(v)          (((v) & 0x1) << 1)
+#define BFM_USBCTRL_OTGSC_VC(v)         BM_USBCTRL_OTGSC_VC
+#define BF_USBCTRL_OTGSC_VC_V(e)        BF_USBCTRL_OTGSC_VC(BV_USBCTRL_OTGSC_VC__##e)
+#define BFM_USBCTRL_OTGSC_VC_V(v)       BM_USBCTRL_OTGSC_VC
+#define BP_USBCTRL_OTGSC_VD             0
+#define BM_USBCTRL_OTGSC_VD             0x1
+#define BF_USBCTRL_OTGSC_VD(v)          (((v) & 0x1) << 0)
+#define BFM_USBCTRL_OTGSC_VD(v)         BM_USBCTRL_OTGSC_VD
+#define BF_USBCTRL_OTGSC_VD_V(e)        BF_USBCTRL_OTGSC_VD(BV_USBCTRL_OTGSC_VD__##e)
+#define BFM_USBCTRL_OTGSC_VD_V(v)       BM_USBCTRL_OTGSC_VD
+
+#define HW_USBCTRL_USBMODE              HW(USBCTRL_USBMODE)
+#define HWA_USBCTRL_USBMODE             (0x80080000 + 0x1a8)
+#define HWT_USBCTRL_USBMODE             HWIO_32_RW
+#define HWN_USBCTRL_USBMODE             USBCTRL_USBMODE
+#define HWI_USBCTRL_USBMODE             
+#define BP_USBCTRL_USBMODE_RSVD         6
+#define BM_USBCTRL_USBMODE_RSVD         0xffffffc0
+#define BF_USBCTRL_USBMODE_RSVD(v)      (((v) & 0x3ffffff) << 6)
+#define BFM_USBCTRL_USBMODE_RSVD(v)     BM_USBCTRL_USBMODE_RSVD
+#define BF_USBCTRL_USBMODE_RSVD_V(e)    BF_USBCTRL_USBMODE_RSVD(BV_USBCTRL_USBMODE_RSVD__##e)
+#define BFM_USBCTRL_USBMODE_RSVD_V(v)   BM_USBCTRL_USBMODE_RSVD
+#define BP_USBCTRL_USBMODE_VBPS         5
+#define BM_USBCTRL_USBMODE_VBPS         0x20
+#define BF_USBCTRL_USBMODE_VBPS(v)      (((v) & 0x1) << 5)
+#define BFM_USBCTRL_USBMODE_VBPS(v)     BM_USBCTRL_USBMODE_VBPS
+#define BF_USBCTRL_USBMODE_VBPS_V(e)    BF_USBCTRL_USBMODE_VBPS(BV_USBCTRL_USBMODE_VBPS__##e)
+#define BFM_USBCTRL_USBMODE_VBPS_V(v)   BM_USBCTRL_USBMODE_VBPS
+#define BP_USBCTRL_USBMODE_SDIS         4
+#define BM_USBCTRL_USBMODE_SDIS         0x10
+#define BF_USBCTRL_USBMODE_SDIS(v)      (((v) & 0x1) << 4)
+#define BFM_USBCTRL_USBMODE_SDIS(v)     BM_USBCTRL_USBMODE_SDIS
+#define BF_USBCTRL_USBMODE_SDIS_V(e)    BF_USBCTRL_USBMODE_SDIS(BV_USBCTRL_USBMODE_SDIS__##e)
+#define BFM_USBCTRL_USBMODE_SDIS_V(v)   BM_USBCTRL_USBMODE_SDIS
+#define BP_USBCTRL_USBMODE_SLOM         3
+#define BM_USBCTRL_USBMODE_SLOM         0x8
+#define BF_USBCTRL_USBMODE_SLOM(v)      (((v) & 0x1) << 3)
+#define BFM_USBCTRL_USBMODE_SLOM(v)     BM_USBCTRL_USBMODE_SLOM
+#define BF_USBCTRL_USBMODE_SLOM_V(e)    BF_USBCTRL_USBMODE_SLOM(BV_USBCTRL_USBMODE_SLOM__##e)
+#define BFM_USBCTRL_USBMODE_SLOM_V(v)   BM_USBCTRL_USBMODE_SLOM
+#define BP_USBCTRL_USBMODE_ES           2
+#define BM_USBCTRL_USBMODE_ES           0x4
+#define BF_USBCTRL_USBMODE_ES(v)        (((v) & 0x1) << 2)
+#define BFM_USBCTRL_USBMODE_ES(v)       BM_USBCTRL_USBMODE_ES
+#define BF_USBCTRL_USBMODE_ES_V(e)      BF_USBCTRL_USBMODE_ES(BV_USBCTRL_USBMODE_ES__##e)
+#define BFM_USBCTRL_USBMODE_ES_V(v)     BM_USBCTRL_USBMODE_ES
+#define BP_USBCTRL_USBMODE_CM           0
+#define BM_USBCTRL_USBMODE_CM           0x3
+#define BV_USBCTRL_USBMODE_CM__IDLE     0x0
+#define BV_USBCTRL_USBMODE_CM__DEVICE   0x2
+#define BV_USBCTRL_USBMODE_CM__HOST     0x3
+#define BF_USBCTRL_USBMODE_CM(v)        (((v) & 0x3) << 0)
+#define BFM_USBCTRL_USBMODE_CM(v)       BM_USBCTRL_USBMODE_CM
+#define BF_USBCTRL_USBMODE_CM_V(e)      BF_USBCTRL_USBMODE_CM(BV_USBCTRL_USBMODE_CM__##e)
+#define BFM_USBCTRL_USBMODE_CM_V(v)     BM_USBCTRL_USBMODE_CM
+
+#define HW_USBCTRL_ENDPTSETUPSTAT                       HW(USBCTRL_ENDPTSETUPSTAT)
+#define HWA_USBCTRL_ENDPTSETUPSTAT                      (0x80080000 + 0x1ac)
+#define HWT_USBCTRL_ENDPTSETUPSTAT                      HWIO_32_RW
+#define HWN_USBCTRL_ENDPTSETUPSTAT                      USBCTRL_ENDPTSETUPSTAT
+#define HWI_USBCTRL_ENDPTSETUPSTAT                      
+#define BP_USBCTRL_ENDPTSETUPSTAT_RSVD                  5
+#define BM_USBCTRL_ENDPTSETUPSTAT_RSVD                  0xffffffe0
+#define BF_USBCTRL_ENDPTSETUPSTAT_RSVD(v)               (((v) & 0x7ffffff) << 5)
+#define BFM_USBCTRL_ENDPTSETUPSTAT_RSVD(v)              BM_USBCTRL_ENDPTSETUPSTAT_RSVD
+#define BF_USBCTRL_ENDPTSETUPSTAT_RSVD_V(e)             BF_USBCTRL_ENDPTSETUPSTAT_RSVD(BV_USBCTRL_ENDPTSETUPSTAT_RSVD__##e)
+#define BFM_USBCTRL_ENDPTSETUPSTAT_RSVD_V(v)            BM_USBCTRL_ENDPTSETUPSTAT_RSVD
+#define BP_USBCTRL_ENDPTSETUPSTAT_ENDPTSETUPSTAT        0
+#define BM_USBCTRL_ENDPTSETUPSTAT_ENDPTSETUPSTAT        0x1f
+#define BF_USBCTRL_ENDPTSETUPSTAT_ENDPTSETUPSTAT(v)     (((v) & 0x1f) << 0)
+#define BFM_USBCTRL_ENDPTSETUPSTAT_ENDPTSETUPSTAT(v)    BM_USBCTRL_ENDPTSETUPSTAT_ENDPTSETUPSTAT
+#define BF_USBCTRL_ENDPTSETUPSTAT_ENDPTSETUPSTAT_V(e)   BF_USBCTRL_ENDPTSETUPSTAT_ENDPTSETUPSTAT(BV_USBCTRL_ENDPTSETUPSTAT_ENDPTSETUPSTAT__##e)
+#define BFM_USBCTRL_ENDPTSETUPSTAT_ENDPTSETUPSTAT_V(v)  BM_USBCTRL_ENDPTSETUPSTAT_ENDPTSETUPSTAT
+
+#define HW_USBCTRL_ENDPTPRIME               HW(USBCTRL_ENDPTPRIME)
+#define HWA_USBCTRL_ENDPTPRIME              (0x80080000 + 0x1b0)
+#define HWT_USBCTRL_ENDPTPRIME              HWIO_32_RW
+#define HWN_USBCTRL_ENDPTPRIME              USBCTRL_ENDPTPRIME
+#define HWI_USBCTRL_ENDPTPRIME              
+#define BP_USBCTRL_ENDPTPRIME_RSVD1         21
+#define BM_USBCTRL_ENDPTPRIME_RSVD1         0xffe00000
+#define BF_USBCTRL_ENDPTPRIME_RSVD1(v)      (((v) & 0x7ff) << 21)
+#define BFM_USBCTRL_ENDPTPRIME_RSVD1(v)     BM_USBCTRL_ENDPTPRIME_RSVD1
+#define BF_USBCTRL_ENDPTPRIME_RSVD1_V(e)    BF_USBCTRL_ENDPTPRIME_RSVD1(BV_USBCTRL_ENDPTPRIME_RSVD1__##e)
+#define BFM_USBCTRL_ENDPTPRIME_RSVD1_V(v)   BM_USBCTRL_ENDPTPRIME_RSVD1
+#define BP_USBCTRL_ENDPTPRIME_PETB          16
+#define BM_USBCTRL_ENDPTPRIME_PETB          0x1f0000
+#define BF_USBCTRL_ENDPTPRIME_PETB(v)       (((v) & 0x1f) << 16)
+#define BFM_USBCTRL_ENDPTPRIME_PETB(v)      BM_USBCTRL_ENDPTPRIME_PETB
+#define BF_USBCTRL_ENDPTPRIME_PETB_V(e)     BF_USBCTRL_ENDPTPRIME_PETB(BV_USBCTRL_ENDPTPRIME_PETB__##e)
+#define BFM_USBCTRL_ENDPTPRIME_PETB_V(v)    BM_USBCTRL_ENDPTPRIME_PETB
+#define BP_USBCTRL_ENDPTPRIME_RSVD0         5
+#define BM_USBCTRL_ENDPTPRIME_RSVD0         0xffe0
+#define BF_USBCTRL_ENDPTPRIME_RSVD0(v)      (((v) & 0x7ff) << 5)
+#define BFM_USBCTRL_ENDPTPRIME_RSVD0(v)     BM_USBCTRL_ENDPTPRIME_RSVD0
+#define BF_USBCTRL_ENDPTPRIME_RSVD0_V(e)    BF_USBCTRL_ENDPTPRIME_RSVD0(BV_USBCTRL_ENDPTPRIME_RSVD0__##e)
+#define BFM_USBCTRL_ENDPTPRIME_RSVD0_V(v)   BM_USBCTRL_ENDPTPRIME_RSVD0
+#define BP_USBCTRL_ENDPTPRIME_PERB          0
+#define BM_USBCTRL_ENDPTPRIME_PERB          0x1f
+#define BF_USBCTRL_ENDPTPRIME_PERB(v)       (((v) & 0x1f) << 0)
+#define BFM_USBCTRL_ENDPTPRIME_PERB(v)      BM_USBCTRL_ENDPTPRIME_PERB
+#define BF_USBCTRL_ENDPTPRIME_PERB_V(e)     BF_USBCTRL_ENDPTPRIME_PERB(BV_USBCTRL_ENDPTPRIME_PERB__##e)
+#define BFM_USBCTRL_ENDPTPRIME_PERB_V(v)    BM_USBCTRL_ENDPTPRIME_PERB
+
+#define HW_USBCTRL_ENDPTFLUSH               HW(USBCTRL_ENDPTFLUSH)
+#define HWA_USBCTRL_ENDPTFLUSH              (0x80080000 + 0x1b4)
+#define HWT_USBCTRL_ENDPTFLUSH              HWIO_32_RW
+#define HWN_USBCTRL_ENDPTFLUSH              USBCTRL_ENDPTFLUSH
+#define HWI_USBCTRL_ENDPTFLUSH              
+#define BP_USBCTRL_ENDPTFLUSH_RSVD1         21
+#define BM_USBCTRL_ENDPTFLUSH_RSVD1         0xffe00000
+#define BF_USBCTRL_ENDPTFLUSH_RSVD1(v)      (((v) & 0x7ff) << 21)
+#define BFM_USBCTRL_ENDPTFLUSH_RSVD1(v)     BM_USBCTRL_ENDPTFLUSH_RSVD1
+#define BF_USBCTRL_ENDPTFLUSH_RSVD1_V(e)    BF_USBCTRL_ENDPTFLUSH_RSVD1(BV_USBCTRL_ENDPTFLUSH_RSVD1__##e)
+#define BFM_USBCTRL_ENDPTFLUSH_RSVD1_V(v)   BM_USBCTRL_ENDPTFLUSH_RSVD1
+#define BP_USBCTRL_ENDPTFLUSH_FETB          16
+#define BM_USBCTRL_ENDPTFLUSH_FETB          0x1f0000
+#define BF_USBCTRL_ENDPTFLUSH_FETB(v)       (((v) & 0x1f) << 16)
+#define BFM_USBCTRL_ENDPTFLUSH_FETB(v)      BM_USBCTRL_ENDPTFLUSH_FETB
+#define BF_USBCTRL_ENDPTFLUSH_FETB_V(e)     BF_USBCTRL_ENDPTFLUSH_FETB(BV_USBCTRL_ENDPTFLUSH_FETB__##e)
+#define BFM_USBCTRL_ENDPTFLUSH_FETB_V(v)    BM_USBCTRL_ENDPTFLUSH_FETB
+#define BP_USBCTRL_ENDPTFLUSH_RSVD0         5
+#define BM_USBCTRL_ENDPTFLUSH_RSVD0         0xffe0
+#define BF_USBCTRL_ENDPTFLUSH_RSVD0(v)      (((v) & 0x7ff) << 5)
+#define BFM_USBCTRL_ENDPTFLUSH_RSVD0(v)     BM_USBCTRL_ENDPTFLUSH_RSVD0
+#define BF_USBCTRL_ENDPTFLUSH_RSVD0_V(e)    BF_USBCTRL_ENDPTFLUSH_RSVD0(BV_USBCTRL_ENDPTFLUSH_RSVD0__##e)
+#define BFM_USBCTRL_ENDPTFLUSH_RSVD0_V(v)   BM_USBCTRL_ENDPTFLUSH_RSVD0
+#define BP_USBCTRL_ENDPTFLUSH_FERB          0
+#define BM_USBCTRL_ENDPTFLUSH_FERB          0x1f
+#define BF_USBCTRL_ENDPTFLUSH_FERB(v)       (((v) & 0x1f) << 0)
+#define BFM_USBCTRL_ENDPTFLUSH_FERB(v)      BM_USBCTRL_ENDPTFLUSH_FERB
+#define BF_USBCTRL_ENDPTFLUSH_FERB_V(e)     BF_USBCTRL_ENDPTFLUSH_FERB(BV_USBCTRL_ENDPTFLUSH_FERB__##e)
+#define BFM_USBCTRL_ENDPTFLUSH_FERB_V(v)    BM_USBCTRL_ENDPTFLUSH_FERB
+
+#define HW_USBCTRL_ENDPTSTAT                HW(USBCTRL_ENDPTSTAT)
+#define HWA_USBCTRL_ENDPTSTAT               (0x80080000 + 0x1b8)
+#define HWT_USBCTRL_ENDPTSTAT               HWIO_32_RW
+#define HWN_USBCTRL_ENDPTSTAT               USBCTRL_ENDPTSTAT
+#define HWI_USBCTRL_ENDPTSTAT               
+#define BP_USBCTRL_ENDPTSTAT_RSVD1          21
+#define BM_USBCTRL_ENDPTSTAT_RSVD1          0xffe00000
+#define BF_USBCTRL_ENDPTSTAT_RSVD1(v)       (((v) & 0x7ff) << 21)
+#define BFM_USBCTRL_ENDPTSTAT_RSVD1(v)      BM_USBCTRL_ENDPTSTAT_RSVD1
+#define BF_USBCTRL_ENDPTSTAT_RSVD1_V(e)     BF_USBCTRL_ENDPTSTAT_RSVD1(BV_USBCTRL_ENDPTSTAT_RSVD1__##e)
+#define BFM_USBCTRL_ENDPTSTAT_RSVD1_V(v)    BM_USBCTRL_ENDPTSTAT_RSVD1
+#define BP_USBCTRL_ENDPTSTAT_ETBR           16
+#define BM_USBCTRL_ENDPTSTAT_ETBR           0x1f0000
+#define BF_USBCTRL_ENDPTSTAT_ETBR(v)        (((v) & 0x1f) << 16)
+#define BFM_USBCTRL_ENDPTSTAT_ETBR(v)       BM_USBCTRL_ENDPTSTAT_ETBR
+#define BF_USBCTRL_ENDPTSTAT_ETBR_V(e)      BF_USBCTRL_ENDPTSTAT_ETBR(BV_USBCTRL_ENDPTSTAT_ETBR__##e)
+#define BFM_USBCTRL_ENDPTSTAT_ETBR_V(v)     BM_USBCTRL_ENDPTSTAT_ETBR
+#define BP_USBCTRL_ENDPTSTAT_RSVD0          5
+#define BM_USBCTRL_ENDPTSTAT_RSVD0          0xffe0
+#define BF_USBCTRL_ENDPTSTAT_RSVD0(v)       (((v) & 0x7ff) << 5)
+#define BFM_USBCTRL_ENDPTSTAT_RSVD0(v)      BM_USBCTRL_ENDPTSTAT_RSVD0
+#define BF_USBCTRL_ENDPTSTAT_RSVD0_V(e)     BF_USBCTRL_ENDPTSTAT_RSVD0(BV_USBCTRL_ENDPTSTAT_RSVD0__##e)
+#define BFM_USBCTRL_ENDPTSTAT_RSVD0_V(v)    BM_USBCTRL_ENDPTSTAT_RSVD0
+#define BP_USBCTRL_ENDPTSTAT_ERBR           0
+#define BM_USBCTRL_ENDPTSTAT_ERBR           0x1f
+#define BF_USBCTRL_ENDPTSTAT_ERBR(v)        (((v) & 0x1f) << 0)
+#define BFM_USBCTRL_ENDPTSTAT_ERBR(v)       BM_USBCTRL_ENDPTSTAT_ERBR
+#define BF_USBCTRL_ENDPTSTAT_ERBR_V(e)      BF_USBCTRL_ENDPTSTAT_ERBR(BV_USBCTRL_ENDPTSTAT_ERBR__##e)
+#define BFM_USBCTRL_ENDPTSTAT_ERBR_V(v)     BM_USBCTRL_ENDPTSTAT_ERBR
+
+#define HW_USBCTRL_ENDPTCOMPLETE                HW(USBCTRL_ENDPTCOMPLETE)
+#define HWA_USBCTRL_ENDPTCOMPLETE               (0x80080000 + 0x1bc)
+#define HWT_USBCTRL_ENDPTCOMPLETE               HWIO_32_RW
+#define HWN_USBCTRL_ENDPTCOMPLETE               USBCTRL_ENDPTCOMPLETE
+#define HWI_USBCTRL_ENDPTCOMPLETE               
+#define BP_USBCTRL_ENDPTCOMPLETE_RSVD1          21
+#define BM_USBCTRL_ENDPTCOMPLETE_RSVD1          0xffe00000
+#define BF_USBCTRL_ENDPTCOMPLETE_RSVD1(v)       (((v) & 0x7ff) << 21)
+#define BFM_USBCTRL_ENDPTCOMPLETE_RSVD1(v)      BM_USBCTRL_ENDPTCOMPLETE_RSVD1
+#define BF_USBCTRL_ENDPTCOMPLETE_RSVD1_V(e)     BF_USBCTRL_ENDPTCOMPLETE_RSVD1(BV_USBCTRL_ENDPTCOMPLETE_RSVD1__##e)
+#define BFM_USBCTRL_ENDPTCOMPLETE_RSVD1_V(v)    BM_USBCTRL_ENDPTCOMPLETE_RSVD1
+#define BP_USBCTRL_ENDPTCOMPLETE_ETCE           16
+#define BM_USBCTRL_ENDPTCOMPLETE_ETCE           0x1f0000
+#define BF_USBCTRL_ENDPTCOMPLETE_ETCE(v)        (((v) & 0x1f) << 16)
+#define BFM_USBCTRL_ENDPTCOMPLETE_ETCE(v)       BM_USBCTRL_ENDPTCOMPLETE_ETCE
+#define BF_USBCTRL_ENDPTCOMPLETE_ETCE_V(e)      BF_USBCTRL_ENDPTCOMPLETE_ETCE(BV_USBCTRL_ENDPTCOMPLETE_ETCE__##e)
+#define BFM_USBCTRL_ENDPTCOMPLETE_ETCE_V(v)     BM_USBCTRL_ENDPTCOMPLETE_ETCE
+#define BP_USBCTRL_ENDPTCOMPLETE_RSVD0          5
+#define BM_USBCTRL_ENDPTCOMPLETE_RSVD0          0xffe0
+#define BF_USBCTRL_ENDPTCOMPLETE_RSVD0(v)       (((v) & 0x7ff) << 5)
+#define BFM_USBCTRL_ENDPTCOMPLETE_RSVD0(v)      BM_USBCTRL_ENDPTCOMPLETE_RSVD0
+#define BF_USBCTRL_ENDPTCOMPLETE_RSVD0_V(e)     BF_USBCTRL_ENDPTCOMPLETE_RSVD0(BV_USBCTRL_ENDPTCOMPLETE_RSVD0__##e)
+#define BFM_USBCTRL_ENDPTCOMPLETE_RSVD0_V(v)    BM_USBCTRL_ENDPTCOMPLETE_RSVD0
+#define BP_USBCTRL_ENDPTCOMPLETE_ERCE           0
+#define BM_USBCTRL_ENDPTCOMPLETE_ERCE           0x1f
+#define BF_USBCTRL_ENDPTCOMPLETE_ERCE(v)        (((v) & 0x1f) << 0)
+#define BFM_USBCTRL_ENDPTCOMPLETE_ERCE(v)       BM_USBCTRL_ENDPTCOMPLETE_ERCE
+#define BF_USBCTRL_ENDPTCOMPLETE_ERCE_V(e)      BF_USBCTRL_ENDPTCOMPLETE_ERCE(BV_USBCTRL_ENDPTCOMPLETE_ERCE__##e)
+#define BFM_USBCTRL_ENDPTCOMPLETE_ERCE_V(v)     BM_USBCTRL_ENDPTCOMPLETE_ERCE
+
+#define HW_USBCTRL_ENDPTCTRLn(_n1)          HW(USBCTRL_ENDPTCTRLn(_n1))
+#define HWA_USBCTRL_ENDPTCTRLn(_n1)         (0x80080000 + 0x1c0 + (_n1) * 0x4)
+#define HWT_USBCTRL_ENDPTCTRLn(_n1)         HWIO_32_RW
+#define HWN_USBCTRL_ENDPTCTRLn(_n1)         USBCTRL_ENDPTCTRLn
+#define HWI_USBCTRL_ENDPTCTRLn(_n1)         (_n1)
+#define BP_USBCTRL_ENDPTCTRLn_RSVD6         24
+#define BM_USBCTRL_ENDPTCTRLn_RSVD6         0xff000000
+#define BF_USBCTRL_ENDPTCTRLn_RSVD6(v)      (((v) & 0xff) << 24)
+#define BFM_USBCTRL_ENDPTCTRLn_RSVD6(v)     BM_USBCTRL_ENDPTCTRLn_RSVD6
+#define BF_USBCTRL_ENDPTCTRLn_RSVD6_V(e)    BF_USBCTRL_ENDPTCTRLn_RSVD6(BV_USBCTRL_ENDPTCTRLn_RSVD6__##e)
+#define BFM_USBCTRL_ENDPTCTRLn_RSVD6_V(v)   BM_USBCTRL_ENDPTCTRLn_RSVD6
+#define BP_USBCTRL_ENDPTCTRLn_TXE           23
+#define BM_USBCTRL_ENDPTCTRLn_TXE           0x800000
+#define BF_USBCTRL_ENDPTCTRLn_TXE(v)        (((v) & 0x1) << 23)
+#define BFM_USBCTRL_ENDPTCTRLn_TXE(v)       BM_USBCTRL_ENDPTCTRLn_TXE
+#define BF_USBCTRL_ENDPTCTRLn_TXE_V(e)      BF_USBCTRL_ENDPTCTRLn_TXE(BV_USBCTRL_ENDPTCTRLn_TXE__##e)
+#define BFM_USBCTRL_ENDPTCTRLn_TXE_V(v)     BM_USBCTRL_ENDPTCTRLn_TXE
+#define BP_USBCTRL_ENDPTCTRLn_TXR           22
+#define BM_USBCTRL_ENDPTCTRLn_TXR           0x400000
+#define BF_USBCTRL_ENDPTCTRLn_TXR(v)        (((v) & 0x1) << 22)
+#define BFM_USBCTRL_ENDPTCTRLn_TXR(v)       BM_USBCTRL_ENDPTCTRLn_TXR
+#define BF_USBCTRL_ENDPTCTRLn_TXR_V(e)      BF_USBCTRL_ENDPTCTRLn_TXR(BV_USBCTRL_ENDPTCTRLn_TXR__##e)
+#define BFM_USBCTRL_ENDPTCTRLn_TXR_V(v)     BM_USBCTRL_ENDPTCTRLn_TXR
+#define BP_USBCTRL_ENDPTCTRLn_TXI           21
+#define BM_USBCTRL_ENDPTCTRLn_TXI           0x200000
+#define BF_USBCTRL_ENDPTCTRLn_TXI(v)        (((v) & 0x1) << 21)
+#define BFM_USBCTRL_ENDPTCTRLn_TXI(v)       BM_USBCTRL_ENDPTCTRLn_TXI
+#define BF_USBCTRL_ENDPTCTRLn_TXI_V(e)      BF_USBCTRL_ENDPTCTRLn_TXI(BV_USBCTRL_ENDPTCTRLn_TXI__##e)
+#define BFM_USBCTRL_ENDPTCTRLn_TXI_V(v)     BM_USBCTRL_ENDPTCTRLn_TXI
+#define BP_USBCTRL_ENDPTCTRLn_RSVD5         20
+#define BM_USBCTRL_ENDPTCTRLn_RSVD5         0x100000
+#define BF_USBCTRL_ENDPTCTRLn_RSVD5(v)      (((v) & 0x1) << 20)
+#define BFM_USBCTRL_ENDPTCTRLn_RSVD5(v)     BM_USBCTRL_ENDPTCTRLn_RSVD5
+#define BF_USBCTRL_ENDPTCTRLn_RSVD5_V(e)    BF_USBCTRL_ENDPTCTRLn_RSVD5(BV_USBCTRL_ENDPTCTRLn_RSVD5__##e)
+#define BFM_USBCTRL_ENDPTCTRLn_RSVD5_V(v)   BM_USBCTRL_ENDPTCTRLn_RSVD5
+#define BP_USBCTRL_ENDPTCTRLn_TXT           18
+#define BM_USBCTRL_ENDPTCTRLn_TXT           0xc0000
+#define BV_USBCTRL_ENDPTCTRLn_TXT__CONTROL  0x0
+#define BV_USBCTRL_ENDPTCTRLn_TXT__ISO      0x1
+#define BV_USBCTRL_ENDPTCTRLn_TXT__BULK     0x2
+#define BV_USBCTRL_ENDPTCTRLn_TXT__INT      0x3
+#define BF_USBCTRL_ENDPTCTRLn_TXT(v)        (((v) & 0x3) << 18)
+#define BFM_USBCTRL_ENDPTCTRLn_TXT(v)       BM_USBCTRL_ENDPTCTRLn_TXT
+#define BF_USBCTRL_ENDPTCTRLn_TXT_V(e)      BF_USBCTRL_ENDPTCTRLn_TXT(BV_USBCTRL_ENDPTCTRLn_TXT__##e)
+#define BFM_USBCTRL_ENDPTCTRLn_TXT_V(v)     BM_USBCTRL_ENDPTCTRLn_TXT
+#define BP_USBCTRL_ENDPTCTRLn_TXD           17
+#define BM_USBCTRL_ENDPTCTRLn_TXD           0x20000
+#define BF_USBCTRL_ENDPTCTRLn_TXD(v)        (((v) & 0x1) << 17)
+#define BFM_USBCTRL_ENDPTCTRLn_TXD(v)       BM_USBCTRL_ENDPTCTRLn_TXD
+#define BF_USBCTRL_ENDPTCTRLn_TXD_V(e)      BF_USBCTRL_ENDPTCTRLn_TXD(BV_USBCTRL_ENDPTCTRLn_TXD__##e)
+#define BFM_USBCTRL_ENDPTCTRLn_TXD_V(v)     BM_USBCTRL_ENDPTCTRLn_TXD
+#define BP_USBCTRL_ENDPTCTRLn_TXS           16
+#define BM_USBCTRL_ENDPTCTRLn_TXS           0x10000
+#define BF_USBCTRL_ENDPTCTRLn_TXS(v)        (((v) & 0x1) << 16)
+#define BFM_USBCTRL_ENDPTCTRLn_TXS(v)       BM_USBCTRL_ENDPTCTRLn_TXS
+#define BF_USBCTRL_ENDPTCTRLn_TXS_V(e)      BF_USBCTRL_ENDPTCTRLn_TXS(BV_USBCTRL_ENDPTCTRLn_TXS__##e)
+#define BFM_USBCTRL_ENDPTCTRLn_TXS_V(v)     BM_USBCTRL_ENDPTCTRLn_TXS
+#define BP_USBCTRL_ENDPTCTRLn_RSVD3         8
+#define BM_USBCTRL_ENDPTCTRLn_RSVD3         0xff00
+#define BF_USBCTRL_ENDPTCTRLn_RSVD3(v)      (((v) & 0xff) << 8)
+#define BFM_USBCTRL_ENDPTCTRLn_RSVD3(v)     BM_USBCTRL_ENDPTCTRLn_RSVD3
+#define BF_USBCTRL_ENDPTCTRLn_RSVD3_V(e)    BF_USBCTRL_ENDPTCTRLn_RSVD3(BV_USBCTRL_ENDPTCTRLn_RSVD3__##e)
+#define BFM_USBCTRL_ENDPTCTRLn_RSVD3_V(v)   BM_USBCTRL_ENDPTCTRLn_RSVD3
+#define BP_USBCTRL_ENDPTCTRLn_RXE           7
+#define BM_USBCTRL_ENDPTCTRLn_RXE           0x80
+#define BF_USBCTRL_ENDPTCTRLn_RXE(v)        (((v) & 0x1) << 7)
+#define BFM_USBCTRL_ENDPTCTRLn_RXE(v)       BM_USBCTRL_ENDPTCTRLn_RXE
+#define BF_USBCTRL_ENDPTCTRLn_RXE_V(e)      BF_USBCTRL_ENDPTCTRLn_RXE(BV_USBCTRL_ENDPTCTRLn_RXE__##e)
+#define BFM_USBCTRL_ENDPTCTRLn_RXE_V(v)     BM_USBCTRL_ENDPTCTRLn_RXE
+#define BP_USBCTRL_ENDPTCTRLn_RXR           6
+#define BM_USBCTRL_ENDPTCTRLn_RXR           0x40
+#define BF_USBCTRL_ENDPTCTRLn_RXR(v)        (((v) & 0x1) << 6)
+#define BFM_USBCTRL_ENDPTCTRLn_RXR(v)       BM_USBCTRL_ENDPTCTRLn_RXR
+#define BF_USBCTRL_ENDPTCTRLn_RXR_V(e)      BF_USBCTRL_ENDPTCTRLn_RXR(BV_USBCTRL_ENDPTCTRLn_RXR__##e)
+#define BFM_USBCTRL_ENDPTCTRLn_RXR_V(v)     BM_USBCTRL_ENDPTCTRLn_RXR
+#define BP_USBCTRL_ENDPTCTRLn_RXI           5
+#define BM_USBCTRL_ENDPTCTRLn_RXI           0x20
+#define BF_USBCTRL_ENDPTCTRLn_RXI(v)        (((v) & 0x1) << 5)
+#define BFM_USBCTRL_ENDPTCTRLn_RXI(v)       BM_USBCTRL_ENDPTCTRLn_RXI
+#define BF_USBCTRL_ENDPTCTRLn_RXI_V(e)      BF_USBCTRL_ENDPTCTRLn_RXI(BV_USBCTRL_ENDPTCTRLn_RXI__##e)
+#define BFM_USBCTRL_ENDPTCTRLn_RXI_V(v)     BM_USBCTRL_ENDPTCTRLn_RXI
+#define BP_USBCTRL_ENDPTCTRLn_RSVD2         4
+#define BM_USBCTRL_ENDPTCTRLn_RSVD2         0x10
+#define BF_USBCTRL_ENDPTCTRLn_RSVD2(v)      (((v) & 0x1) << 4)
+#define BFM_USBCTRL_ENDPTCTRLn_RSVD2(v)     BM_USBCTRL_ENDPTCTRLn_RSVD2
+#define BF_USBCTRL_ENDPTCTRLn_RSVD2_V(e)    BF_USBCTRL_ENDPTCTRLn_RSVD2(BV_USBCTRL_ENDPTCTRLn_RSVD2__##e)
+#define BFM_USBCTRL_ENDPTCTRLn_RSVD2_V(v)   BM_USBCTRL_ENDPTCTRLn_RSVD2
+#define BP_USBCTRL_ENDPTCTRLn_RXT           2
+#define BM_USBCTRL_ENDPTCTRLn_RXT           0xc
+#define BV_USBCTRL_ENDPTCTRLn_RXT__CONTROL  0x0
+#define BV_USBCTRL_ENDPTCTRLn_RXT__ISO      0x1
+#define BV_USBCTRL_ENDPTCTRLn_RXT__BULK     0x2
+#define BV_USBCTRL_ENDPTCTRLn_RXT__INT      0x3
+#define BF_USBCTRL_ENDPTCTRLn_RXT(v)        (((v) & 0x3) << 2)
+#define BFM_USBCTRL_ENDPTCTRLn_RXT(v)       BM_USBCTRL_ENDPTCTRLn_RXT
+#define BF_USBCTRL_ENDPTCTRLn_RXT_V(e)      BF_USBCTRL_ENDPTCTRLn_RXT(BV_USBCTRL_ENDPTCTRLn_RXT__##e)
+#define BFM_USBCTRL_ENDPTCTRLn_RXT_V(v)     BM_USBCTRL_ENDPTCTRLn_RXT
+#define BP_USBCTRL_ENDPTCTRLn_RXD           1
+#define BM_USBCTRL_ENDPTCTRLn_RXD           0x2
+#define BF_USBCTRL_ENDPTCTRLn_RXD(v)        (((v) & 0x1) << 1)
+#define BFM_USBCTRL_ENDPTCTRLn_RXD(v)       BM_USBCTRL_ENDPTCTRLn_RXD
+#define BF_USBCTRL_ENDPTCTRLn_RXD_V(e)      BF_USBCTRL_ENDPTCTRLn_RXD(BV_USBCTRL_ENDPTCTRLn_RXD__##e)
+#define BFM_USBCTRL_ENDPTCTRLn_RXD_V(v)     BM_USBCTRL_ENDPTCTRLn_RXD
+#define BP_USBCTRL_ENDPTCTRLn_RXS           0
+#define BM_USBCTRL_ENDPTCTRLn_RXS           0x1
+#define BF_USBCTRL_ENDPTCTRLn_RXS(v)        (((v) & 0x1) << 0)
+#define BFM_USBCTRL_ENDPTCTRLn_RXS(v)       BM_USBCTRL_ENDPTCTRLn_RXS
+#define BF_USBCTRL_ENDPTCTRLn_RXS_V(e)      BF_USBCTRL_ENDPTCTRLn_RXS(BV_USBCTRL_ENDPTCTRLn_RXS__##e)
+#define BFM_USBCTRL_ENDPTCTRLn_RXS_V(v)     BM_USBCTRL_ENDPTCTRLn_RXS
+
+#endif /* __HEADERGEN_IMX233_USBCTRL_H__*/
diff --git a/firmware/target/arm/imx233/regs/imx233/usbphy.h b/firmware/target/arm/imx233/regs/imx233/usbphy.h
new file mode 100644
index 0000000000..3a79aee667
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/imx233/usbphy.h
@@ -0,0 +1,774 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * imx233 version: 2.4.0
+ * imx233 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_IMX233_USBPHY_H__
+#define __HEADERGEN_IMX233_USBPHY_H__
+
+#define HW_USBPHY_PWD                   HW(USBPHY_PWD)
+#define HWA_USBPHY_PWD                  (0x8007c000 + 0x0)
+#define HWT_USBPHY_PWD                  HWIO_32_RW
+#define HWN_USBPHY_PWD                  USBPHY_PWD
+#define HWI_USBPHY_PWD                  
+#define HW_USBPHY_PWD_SET               HW(USBPHY_PWD_SET)
+#define HWA_USBPHY_PWD_SET              (HWA_USBPHY_PWD + 0x4)
+#define HWT_USBPHY_PWD_SET              HWIO_32_WO
+#define HWN_USBPHY_PWD_SET              USBPHY_PWD
+#define HWI_USBPHY_PWD_SET              
+#define HW_USBPHY_PWD_CLR               HW(USBPHY_PWD_CLR)
+#define HWA_USBPHY_PWD_CLR              (HWA_USBPHY_PWD + 0x8)
+#define HWT_USBPHY_PWD_CLR              HWIO_32_WO
+#define HWN_USBPHY_PWD_CLR              USBPHY_PWD
+#define HWI_USBPHY_PWD_CLR              
+#define HW_USBPHY_PWD_TOG               HW(USBPHY_PWD_TOG)
+#define HWA_USBPHY_PWD_TOG              (HWA_USBPHY_PWD + 0xc)
+#define HWT_USBPHY_PWD_TOG              HWIO_32_WO
+#define HWN_USBPHY_PWD_TOG              USBPHY_PWD
+#define HWI_USBPHY_PWD_TOG              
+#define BP_USBPHY_PWD_RSVD2             21
+#define BM_USBPHY_PWD_RSVD2             0xffe00000
+#define BF_USBPHY_PWD_RSVD2(v)          (((v) & 0x7ff) << 21)
+#define BFM_USBPHY_PWD_RSVD2(v)         BM_USBPHY_PWD_RSVD2
+#define BF_USBPHY_PWD_RSVD2_V(e)        BF_USBPHY_PWD_RSVD2(BV_USBPHY_PWD_RSVD2__##e)
+#define BFM_USBPHY_PWD_RSVD2_V(v)       BM_USBPHY_PWD_RSVD2
+#define BP_USBPHY_PWD_RXPWDRX           20
+#define BM_USBPHY_PWD_RXPWDRX           0x100000
+#define BF_USBPHY_PWD_RXPWDRX(v)        (((v) & 0x1) << 20)
+#define BFM_USBPHY_PWD_RXPWDRX(v)       BM_USBPHY_PWD_RXPWDRX
+#define BF_USBPHY_PWD_RXPWDRX_V(e)      BF_USBPHY_PWD_RXPWDRX(BV_USBPHY_PWD_RXPWDRX__##e)
+#define BFM_USBPHY_PWD_RXPWDRX_V(v)     BM_USBPHY_PWD_RXPWDRX
+#define BP_USBPHY_PWD_RXPWDDIFF         19
+#define BM_USBPHY_PWD_RXPWDDIFF         0x80000
+#define BF_USBPHY_PWD_RXPWDDIFF(v)      (((v) & 0x1) << 19)
+#define BFM_USBPHY_PWD_RXPWDDIFF(v)     BM_USBPHY_PWD_RXPWDDIFF
+#define BF_USBPHY_PWD_RXPWDDIFF_V(e)    BF_USBPHY_PWD_RXPWDDIFF(BV_USBPHY_PWD_RXPWDDIFF__##e)
+#define BFM_USBPHY_PWD_RXPWDDIFF_V(v)   BM_USBPHY_PWD_RXPWDDIFF
+#define BP_USBPHY_PWD_RXPWD1PT1         18
+#define BM_USBPHY_PWD_RXPWD1PT1         0x40000
+#define BF_USBPHY_PWD_RXPWD1PT1(v)      (((v) & 0x1) << 18)
+#define BFM_USBPHY_PWD_RXPWD1PT1(v)     BM_USBPHY_PWD_RXPWD1PT1
+#define BF_USBPHY_PWD_RXPWD1PT1_V(e)    BF_USBPHY_PWD_RXPWD1PT1(BV_USBPHY_PWD_RXPWD1PT1__##e)
+#define BFM_USBPHY_PWD_RXPWD1PT1_V(v)   BM_USBPHY_PWD_RXPWD1PT1
+#define BP_USBPHY_PWD_RXPWDENV          17
+#define BM_USBPHY_PWD_RXPWDENV          0x20000
+#define BF_USBPHY_PWD_RXPWDENV(v)       (((v) & 0x1) << 17)
+#define BFM_USBPHY_PWD_RXPWDENV(v)      BM_USBPHY_PWD_RXPWDENV
+#define BF_USBPHY_PWD_RXPWDENV_V(e)     BF_USBPHY_PWD_RXPWDENV(BV_USBPHY_PWD_RXPWDENV__##e)
+#define BFM_USBPHY_PWD_RXPWDENV_V(v)    BM_USBPHY_PWD_RXPWDENV
+#define BP_USBPHY_PWD_RSVD1             13
+#define BM_USBPHY_PWD_RSVD1             0x1e000
+#define BF_USBPHY_PWD_RSVD1(v)          (((v) & 0xf) << 13)
+#define BFM_USBPHY_PWD_RSVD1(v)         BM_USBPHY_PWD_RSVD1
+#define BF_USBPHY_PWD_RSVD1_V(e)        BF_USBPHY_PWD_RSVD1(BV_USBPHY_PWD_RSVD1__##e)
+#define BFM_USBPHY_PWD_RSVD1_V(v)       BM_USBPHY_PWD_RSVD1
+#define BP_USBPHY_PWD_TXPWDV2I          12
+#define BM_USBPHY_PWD_TXPWDV2I          0x1000
+#define BF_USBPHY_PWD_TXPWDV2I(v)       (((v) & 0x1) << 12)
+#define BFM_USBPHY_PWD_TXPWDV2I(v)      BM_USBPHY_PWD_TXPWDV2I
+#define BF_USBPHY_PWD_TXPWDV2I_V(e)     BF_USBPHY_PWD_TXPWDV2I(BV_USBPHY_PWD_TXPWDV2I__##e)
+#define BFM_USBPHY_PWD_TXPWDV2I_V(v)    BM_USBPHY_PWD_TXPWDV2I
+#define BP_USBPHY_PWD_TXPWDIBIAS        11
+#define BM_USBPHY_PWD_TXPWDIBIAS        0x800
+#define BF_USBPHY_PWD_TXPWDIBIAS(v)     (((v) & 0x1) << 11)
+#define BFM_USBPHY_PWD_TXPWDIBIAS(v)    BM_USBPHY_PWD_TXPWDIBIAS
+#define BF_USBPHY_PWD_TXPWDIBIAS_V(e)   BF_USBPHY_PWD_TXPWDIBIAS(BV_USBPHY_PWD_TXPWDIBIAS__##e)
+#define BFM_USBPHY_PWD_TXPWDIBIAS_V(v)  BM_USBPHY_PWD_TXPWDIBIAS
+#define BP_USBPHY_PWD_TXPWDFS           10
+#define BM_USBPHY_PWD_TXPWDFS           0x400
+#define BF_USBPHY_PWD_TXPWDFS(v)        (((v) & 0x1) << 10)
+#define BFM_USBPHY_PWD_TXPWDFS(v)       BM_USBPHY_PWD_TXPWDFS
+#define BF_USBPHY_PWD_TXPWDFS_V(e)      BF_USBPHY_PWD_TXPWDFS(BV_USBPHY_PWD_TXPWDFS__##e)
+#define BFM_USBPHY_PWD_TXPWDFS_V(v)     BM_USBPHY_PWD_TXPWDFS
+#define BP_USBPHY_PWD_RSVD0             0
+#define BM_USBPHY_PWD_RSVD0             0x3ff
+#define BF_USBPHY_PWD_RSVD0(v)          (((v) & 0x3ff) << 0)
+#define BFM_USBPHY_PWD_RSVD0(v)         BM_USBPHY_PWD_RSVD0
+#define BF_USBPHY_PWD_RSVD0_V(e)        BF_USBPHY_PWD_RSVD0(BV_USBPHY_PWD_RSVD0__##e)
+#define BFM_USBPHY_PWD_RSVD0_V(v)       BM_USBPHY_PWD_RSVD0
+
+#define HW_USBPHY_TX                                HW(USBPHY_TX)
+#define HWA_USBPHY_TX                               (0x8007c000 + 0x10)
+#define HWT_USBPHY_TX                               HWIO_32_RW
+#define HWN_USBPHY_TX                               USBPHY_TX
+#define HWI_USBPHY_TX                               
+#define HW_USBPHY_TX_SET                            HW(USBPHY_TX_SET)
+#define HWA_USBPHY_TX_SET                           (HWA_USBPHY_TX + 0x4)
+#define HWT_USBPHY_TX_SET                           HWIO_32_WO
+#define HWN_USBPHY_TX_SET                           USBPHY_TX
+#define HWI_USBPHY_TX_SET                           
+#define HW_USBPHY_TX_CLR                            HW(USBPHY_TX_CLR)
+#define HWA_USBPHY_TX_CLR                           (HWA_USBPHY_TX + 0x8)
+#define HWT_USBPHY_TX_CLR                           HWIO_32_WO
+#define HWN_USBPHY_TX_CLR                           USBPHY_TX
+#define HWI_USBPHY_TX_CLR                           
+#define HW_USBPHY_TX_TOG                            HW(USBPHY_TX_TOG)
+#define HWA_USBPHY_TX_TOG                           (HWA_USBPHY_TX + 0xc)
+#define HWT_USBPHY_TX_TOG                           HWIO_32_WO
+#define HWN_USBPHY_TX_TOG                           USBPHY_TX
+#define HWI_USBPHY_TX_TOG                           
+#define BP_USBPHY_TX_RSVD5                          29
+#define BM_USBPHY_TX_RSVD5                          0xe0000000
+#define BF_USBPHY_TX_RSVD5(v)                       (((v) & 0x7) << 29)
+#define BFM_USBPHY_TX_RSVD5(v)                      BM_USBPHY_TX_RSVD5
+#define BF_USBPHY_TX_RSVD5_V(e)                     BF_USBPHY_TX_RSVD5(BV_USBPHY_TX_RSVD5__##e)
+#define BFM_USBPHY_TX_RSVD5_V(v)                    BM_USBPHY_TX_RSVD5
+#define BP_USBPHY_TX_USBPHY_TX_EDGECTRL             26
+#define BM_USBPHY_TX_USBPHY_TX_EDGECTRL             0x1c000000
+#define BF_USBPHY_TX_USBPHY_TX_EDGECTRL(v)          (((v) & 0x7) << 26)
+#define BFM_USBPHY_TX_USBPHY_TX_EDGECTRL(v)         BM_USBPHY_TX_USBPHY_TX_EDGECTRL
+#define BF_USBPHY_TX_USBPHY_TX_EDGECTRL_V(e)        BF_USBPHY_TX_USBPHY_TX_EDGECTRL(BV_USBPHY_TX_USBPHY_TX_EDGECTRL__##e)
+#define BFM_USBPHY_TX_USBPHY_TX_EDGECTRL_V(v)       BM_USBPHY_TX_USBPHY_TX_EDGECTRL
+#define BP_USBPHY_TX_USBPHY_TX_SYNC_INVERT          25
+#define BM_USBPHY_TX_USBPHY_TX_SYNC_INVERT          0x2000000
+#define BF_USBPHY_TX_USBPHY_TX_SYNC_INVERT(v)       (((v) & 0x1) << 25)
+#define BFM_USBPHY_TX_USBPHY_TX_SYNC_INVERT(v)      BM_USBPHY_TX_USBPHY_TX_SYNC_INVERT
+#define BF_USBPHY_TX_USBPHY_TX_SYNC_INVERT_V(e)     BF_USBPHY_TX_USBPHY_TX_SYNC_INVERT(BV_USBPHY_TX_USBPHY_TX_SYNC_INVERT__##e)
+#define BFM_USBPHY_TX_USBPHY_TX_SYNC_INVERT_V(v)    BM_USBPHY_TX_USBPHY_TX_SYNC_INVERT
+#define BP_USBPHY_TX_USBPHY_TX_SYNC_MUX             24
+#define BM_USBPHY_TX_USBPHY_TX_SYNC_MUX             0x1000000
+#define BF_USBPHY_TX_USBPHY_TX_SYNC_MUX(v)          (((v) & 0x1) << 24)
+#define BFM_USBPHY_TX_USBPHY_TX_SYNC_MUX(v)         BM_USBPHY_TX_USBPHY_TX_SYNC_MUX
+#define BF_USBPHY_TX_USBPHY_TX_SYNC_MUX_V(e)        BF_USBPHY_TX_USBPHY_TX_SYNC_MUX(BV_USBPHY_TX_USBPHY_TX_SYNC_MUX__##e)
+#define BFM_USBPHY_TX_USBPHY_TX_SYNC_MUX_V(v)       BM_USBPHY_TX_USBPHY_TX_SYNC_MUX
+#define BP_USBPHY_TX_RSVD4                          22
+#define BM_USBPHY_TX_RSVD4                          0xc00000
+#define BF_USBPHY_TX_RSVD4(v)                       (((v) & 0x3) << 22)
+#define BFM_USBPHY_TX_RSVD4(v)                      BM_USBPHY_TX_RSVD4
+#define BF_USBPHY_TX_RSVD4_V(e)                     BF_USBPHY_TX_RSVD4(BV_USBPHY_TX_RSVD4__##e)
+#define BFM_USBPHY_TX_RSVD4_V(v)                    BM_USBPHY_TX_RSVD4
+#define BP_USBPHY_TX_TXENCAL45DP                    21
+#define BM_USBPHY_TX_TXENCAL45DP                    0x200000
+#define BF_USBPHY_TX_TXENCAL45DP(v)                 (((v) & 0x1) << 21)
+#define BFM_USBPHY_TX_TXENCAL45DP(v)                BM_USBPHY_TX_TXENCAL45DP
+#define BF_USBPHY_TX_TXENCAL45DP_V(e)               BF_USBPHY_TX_TXENCAL45DP(BV_USBPHY_TX_TXENCAL45DP__##e)
+#define BFM_USBPHY_TX_TXENCAL45DP_V(v)              BM_USBPHY_TX_TXENCAL45DP
+#define BP_USBPHY_TX_RSVD3                          20
+#define BM_USBPHY_TX_RSVD3                          0x100000
+#define BF_USBPHY_TX_RSVD3(v)                       (((v) & 0x1) << 20)
+#define BFM_USBPHY_TX_RSVD3(v)                      BM_USBPHY_TX_RSVD3
+#define BF_USBPHY_TX_RSVD3_V(e)                     BF_USBPHY_TX_RSVD3(BV_USBPHY_TX_RSVD3__##e)
+#define BFM_USBPHY_TX_RSVD3_V(v)                    BM_USBPHY_TX_RSVD3
+#define BP_USBPHY_TX_TXCAL45DP                      16
+#define BM_USBPHY_TX_TXCAL45DP                      0xf0000
+#define BF_USBPHY_TX_TXCAL45DP(v)                   (((v) & 0xf) << 16)
+#define BFM_USBPHY_TX_TXCAL45DP(v)                  BM_USBPHY_TX_TXCAL45DP
+#define BF_USBPHY_TX_TXCAL45DP_V(e)                 BF_USBPHY_TX_TXCAL45DP(BV_USBPHY_TX_TXCAL45DP__##e)
+#define BFM_USBPHY_TX_TXCAL45DP_V(v)                BM_USBPHY_TX_TXCAL45DP
+#define BP_USBPHY_TX_RSVD2                          14
+#define BM_USBPHY_TX_RSVD2                          0xc000
+#define BF_USBPHY_TX_RSVD2(v)                       (((v) & 0x3) << 14)
+#define BFM_USBPHY_TX_RSVD2(v)                      BM_USBPHY_TX_RSVD2
+#define BF_USBPHY_TX_RSVD2_V(e)                     BF_USBPHY_TX_RSVD2(BV_USBPHY_TX_RSVD2__##e)
+#define BFM_USBPHY_TX_RSVD2_V(v)                    BM_USBPHY_TX_RSVD2
+#define BP_USBPHY_TX_TXENCAL45DN                    13
+#define BM_USBPHY_TX_TXENCAL45DN                    0x2000
+#define BF_USBPHY_TX_TXENCAL45DN(v)                 (((v) & 0x1) << 13)
+#define BFM_USBPHY_TX_TXENCAL45DN(v)                BM_USBPHY_TX_TXENCAL45DN
+#define BF_USBPHY_TX_TXENCAL45DN_V(e)               BF_USBPHY_TX_TXENCAL45DN(BV_USBPHY_TX_TXENCAL45DN__##e)
+#define BFM_USBPHY_TX_TXENCAL45DN_V(v)              BM_USBPHY_TX_TXENCAL45DN
+#define BP_USBPHY_TX_RSVD1                          12
+#define BM_USBPHY_TX_RSVD1                          0x1000
+#define BF_USBPHY_TX_RSVD1(v)                       (((v) & 0x1) << 12)
+#define BFM_USBPHY_TX_RSVD1(v)                      BM_USBPHY_TX_RSVD1
+#define BF_USBPHY_TX_RSVD1_V(e)                     BF_USBPHY_TX_RSVD1(BV_USBPHY_TX_RSVD1__##e)
+#define BFM_USBPHY_TX_RSVD1_V(v)                    BM_USBPHY_TX_RSVD1
+#define BP_USBPHY_TX_TXCAL45DN                      8
+#define BM_USBPHY_TX_TXCAL45DN                      0xf00
+#define BF_USBPHY_TX_TXCAL45DN(v)                   (((v) & 0xf) << 8)
+#define BFM_USBPHY_TX_TXCAL45DN(v)                  BM_USBPHY_TX_TXCAL45DN
+#define BF_USBPHY_TX_TXCAL45DN_V(e)                 BF_USBPHY_TX_TXCAL45DN(BV_USBPHY_TX_TXCAL45DN__##e)
+#define BFM_USBPHY_TX_TXCAL45DN_V(v)                BM_USBPHY_TX_TXCAL45DN
+#define BP_USBPHY_TX_RSVD0                          4
+#define BM_USBPHY_TX_RSVD0                          0xf0
+#define BF_USBPHY_TX_RSVD0(v)                       (((v) & 0xf) << 4)
+#define BFM_USBPHY_TX_RSVD0(v)                      BM_USBPHY_TX_RSVD0
+#define BF_USBPHY_TX_RSVD0_V(e)                     BF_USBPHY_TX_RSVD0(BV_USBPHY_TX_RSVD0__##e)
+#define BFM_USBPHY_TX_RSVD0_V(v)                    BM_USBPHY_TX_RSVD0
+#define BP_USBPHY_TX_D_CAL                          0
+#define BM_USBPHY_TX_D_CAL                          0xf
+#define BF_USBPHY_TX_D_CAL(v)                       (((v) & 0xf) << 0)
+#define BFM_USBPHY_TX_D_CAL(v)                      BM_USBPHY_TX_D_CAL
+#define BF_USBPHY_TX_D_CAL_V(e)                     BF_USBPHY_TX_D_CAL(BV_USBPHY_TX_D_CAL__##e)
+#define BFM_USBPHY_TX_D_CAL_V(v)                    BM_USBPHY_TX_D_CAL
+
+#define HW_USBPHY_RX                    HW(USBPHY_RX)
+#define HWA_USBPHY_RX                   (0x8007c000 + 0x20)
+#define HWT_USBPHY_RX                   HWIO_32_RW
+#define HWN_USBPHY_RX                   USBPHY_RX
+#define HWI_USBPHY_RX                   
+#define HW_USBPHY_RX_SET                HW(USBPHY_RX_SET)
+#define HWA_USBPHY_RX_SET               (HWA_USBPHY_RX + 0x4)
+#define HWT_USBPHY_RX_SET               HWIO_32_WO
+#define HWN_USBPHY_RX_SET               USBPHY_RX
+#define HWI_USBPHY_RX_SET               
+#define HW_USBPHY_RX_CLR                HW(USBPHY_RX_CLR)
+#define HWA_USBPHY_RX_CLR               (HWA_USBPHY_RX + 0x8)
+#define HWT_USBPHY_RX_CLR               HWIO_32_WO
+#define HWN_USBPHY_RX_CLR               USBPHY_RX
+#define HWI_USBPHY_RX_CLR               
+#define HW_USBPHY_RX_TOG                HW(USBPHY_RX_TOG)
+#define HWA_USBPHY_RX_TOG               (HWA_USBPHY_RX + 0xc)
+#define HWT_USBPHY_RX_TOG               HWIO_32_WO
+#define HWN_USBPHY_RX_TOG               USBPHY_RX
+#define HWI_USBPHY_RX_TOG               
+#define BP_USBPHY_RX_RSVD2              23
+#define BM_USBPHY_RX_RSVD2              0xff800000
+#define BF_USBPHY_RX_RSVD2(v)           (((v) & 0x1ff) << 23)
+#define BFM_USBPHY_RX_RSVD2(v)          BM_USBPHY_RX_RSVD2
+#define BF_USBPHY_RX_RSVD2_V(e)         BF_USBPHY_RX_RSVD2(BV_USBPHY_RX_RSVD2__##e)
+#define BFM_USBPHY_RX_RSVD2_V(v)        BM_USBPHY_RX_RSVD2
+#define BP_USBPHY_RX_RXDBYPASS          22
+#define BM_USBPHY_RX_RXDBYPASS          0x400000
+#define BF_USBPHY_RX_RXDBYPASS(v)       (((v) & 0x1) << 22)
+#define BFM_USBPHY_RX_RXDBYPASS(v)      BM_USBPHY_RX_RXDBYPASS
+#define BF_USBPHY_RX_RXDBYPASS_V(e)     BF_USBPHY_RX_RXDBYPASS(BV_USBPHY_RX_RXDBYPASS__##e)
+#define BFM_USBPHY_RX_RXDBYPASS_V(v)    BM_USBPHY_RX_RXDBYPASS
+#define BP_USBPHY_RX_RSVD1              7
+#define BM_USBPHY_RX_RSVD1              0x3fff80
+#define BF_USBPHY_RX_RSVD1(v)           (((v) & 0x7fff) << 7)
+#define BFM_USBPHY_RX_RSVD1(v)          BM_USBPHY_RX_RSVD1
+#define BF_USBPHY_RX_RSVD1_V(e)         BF_USBPHY_RX_RSVD1(BV_USBPHY_RX_RSVD1__##e)
+#define BFM_USBPHY_RX_RSVD1_V(v)        BM_USBPHY_RX_RSVD1
+#define BP_USBPHY_RX_DISCONADJ          4
+#define BM_USBPHY_RX_DISCONADJ          0x70
+#define BF_USBPHY_RX_DISCONADJ(v)       (((v) & 0x7) << 4)
+#define BFM_USBPHY_RX_DISCONADJ(v)      BM_USBPHY_RX_DISCONADJ
+#define BF_USBPHY_RX_DISCONADJ_V(e)     BF_USBPHY_RX_DISCONADJ(BV_USBPHY_RX_DISCONADJ__##e)
+#define BFM_USBPHY_RX_DISCONADJ_V(v)    BM_USBPHY_RX_DISCONADJ
+#define BP_USBPHY_RX_RSVD0              3
+#define BM_USBPHY_RX_RSVD0              0x8
+#define BF_USBPHY_RX_RSVD0(v)           (((v) & 0x1) << 3)
+#define BFM_USBPHY_RX_RSVD0(v)          BM_USBPHY_RX_RSVD0
+#define BF_USBPHY_RX_RSVD0_V(e)         BF_USBPHY_RX_RSVD0(BV_USBPHY_RX_RSVD0__##e)
+#define BFM_USBPHY_RX_RSVD0_V(v)        BM_USBPHY_RX_RSVD0
+#define BP_USBPHY_RX_ENVADJ             0
+#define BM_USBPHY_RX_ENVADJ             0x7
+#define BF_USBPHY_RX_ENVADJ(v)          (((v) & 0x7) << 0)
+#define BFM_USBPHY_RX_ENVADJ(v)         BM_USBPHY_RX_ENVADJ
+#define BF_USBPHY_RX_ENVADJ_V(e)        BF_USBPHY_RX_ENVADJ(BV_USBPHY_RX_ENVADJ__##e)
+#define BFM_USBPHY_RX_ENVADJ_V(v)       BM_USBPHY_RX_ENVADJ
+
+#define HW_USBPHY_CTRL                              HW(USBPHY_CTRL)
+#define HWA_USBPHY_CTRL                             (0x8007c000 + 0x30)
+#define HWT_USBPHY_CTRL                             HWIO_32_RW
+#define HWN_USBPHY_CTRL                             USBPHY_CTRL
+#define HWI_USBPHY_CTRL                             
+#define HW_USBPHY_CTRL_SET                          HW(USBPHY_CTRL_SET)
+#define HWA_USBPHY_CTRL_SET                         (HWA_USBPHY_CTRL + 0x4)
+#define HWT_USBPHY_CTRL_SET                         HWIO_32_WO
+#define HWN_USBPHY_CTRL_SET                         USBPHY_CTRL
+#define HWI_USBPHY_CTRL_SET                         
+#define HW_USBPHY_CTRL_CLR                          HW(USBPHY_CTRL_CLR)
+#define HWA_USBPHY_CTRL_CLR                         (HWA_USBPHY_CTRL + 0x8)
+#define HWT_USBPHY_CTRL_CLR                         HWIO_32_WO
+#define HWN_USBPHY_CTRL_CLR                         USBPHY_CTRL
+#define HWI_USBPHY_CTRL_CLR                         
+#define HW_USBPHY_CTRL_TOG                          HW(USBPHY_CTRL_TOG)
+#define HWA_USBPHY_CTRL_TOG                         (HWA_USBPHY_CTRL + 0xc)
+#define HWT_USBPHY_CTRL_TOG                         HWIO_32_WO
+#define HWN_USBPHY_CTRL_TOG                         USBPHY_CTRL
+#define HWI_USBPHY_CTRL_TOG                         
+#define BP_USBPHY_CTRL_SFTRST                       31
+#define BM_USBPHY_CTRL_SFTRST                       0x80000000
+#define BF_USBPHY_CTRL_SFTRST(v)                    (((v) & 0x1) << 31)
+#define BFM_USBPHY_CTRL_SFTRST(v)                   BM_USBPHY_CTRL_SFTRST
+#define BF_USBPHY_CTRL_SFTRST_V(e)                  BF_USBPHY_CTRL_SFTRST(BV_USBPHY_CTRL_SFTRST__##e)
+#define BFM_USBPHY_CTRL_SFTRST_V(v)                 BM_USBPHY_CTRL_SFTRST
+#define BP_USBPHY_CTRL_CLKGATE                      30
+#define BM_USBPHY_CTRL_CLKGATE                      0x40000000
+#define BF_USBPHY_CTRL_CLKGATE(v)                   (((v) & 0x1) << 30)
+#define BFM_USBPHY_CTRL_CLKGATE(v)                  BM_USBPHY_CTRL_CLKGATE
+#define BF_USBPHY_CTRL_CLKGATE_V(e)                 BF_USBPHY_CTRL_CLKGATE(BV_USBPHY_CTRL_CLKGATE__##e)
+#define BFM_USBPHY_CTRL_CLKGATE_V(v)                BM_USBPHY_CTRL_CLKGATE
+#define BP_USBPHY_CTRL_UTMI_SUSPENDM                29
+#define BM_USBPHY_CTRL_UTMI_SUSPENDM                0x20000000
+#define BF_USBPHY_CTRL_UTMI_SUSPENDM(v)             (((v) & 0x1) << 29)
+#define BFM_USBPHY_CTRL_UTMI_SUSPENDM(v)            BM_USBPHY_CTRL_UTMI_SUSPENDM
+#define BF_USBPHY_CTRL_UTMI_SUSPENDM_V(e)           BF_USBPHY_CTRL_UTMI_SUSPENDM(BV_USBPHY_CTRL_UTMI_SUSPENDM__##e)
+#define BFM_USBPHY_CTRL_UTMI_SUSPENDM_V(v)          BM_USBPHY_CTRL_UTMI_SUSPENDM
+#define BP_USBPHY_CTRL_HOST_FORCE_LS_SE0            28
+#define BM_USBPHY_CTRL_HOST_FORCE_LS_SE0            0x10000000
+#define BF_USBPHY_CTRL_HOST_FORCE_LS_SE0(v)         (((v) & 0x1) << 28)
+#define BFM_USBPHY_CTRL_HOST_FORCE_LS_SE0(v)        BM_USBPHY_CTRL_HOST_FORCE_LS_SE0
+#define BF_USBPHY_CTRL_HOST_FORCE_LS_SE0_V(e)       BF_USBPHY_CTRL_HOST_FORCE_LS_SE0(BV_USBPHY_CTRL_HOST_FORCE_LS_SE0__##e)
+#define BFM_USBPHY_CTRL_HOST_FORCE_LS_SE0_V(v)      BM_USBPHY_CTRL_HOST_FORCE_LS_SE0
+#define BP_USBPHY_CTRL_RSVD3                        14
+#define BM_USBPHY_CTRL_RSVD3                        0xfffc000
+#define BF_USBPHY_CTRL_RSVD3(v)                     (((v) & 0x3fff) << 14)
+#define BFM_USBPHY_CTRL_RSVD3(v)                    BM_USBPHY_CTRL_RSVD3
+#define BF_USBPHY_CTRL_RSVD3_V(e)                   BF_USBPHY_CTRL_RSVD3(BV_USBPHY_CTRL_RSVD3__##e)
+#define BFM_USBPHY_CTRL_RSVD3_V(v)                  BM_USBPHY_CTRL_RSVD3
+#define BP_USBPHY_CTRL_DATA_ON_LRADC                13
+#define BM_USBPHY_CTRL_DATA_ON_LRADC                0x2000
+#define BF_USBPHY_CTRL_DATA_ON_LRADC(v)             (((v) & 0x1) << 13)
+#define BFM_USBPHY_CTRL_DATA_ON_LRADC(v)            BM_USBPHY_CTRL_DATA_ON_LRADC
+#define BF_USBPHY_CTRL_DATA_ON_LRADC_V(e)           BF_USBPHY_CTRL_DATA_ON_LRADC(BV_USBPHY_CTRL_DATA_ON_LRADC__##e)
+#define BFM_USBPHY_CTRL_DATA_ON_LRADC_V(v)          BM_USBPHY_CTRL_DATA_ON_LRADC
+#define BP_USBPHY_CTRL_DEVPLUGIN_IRQ                12
+#define BM_USBPHY_CTRL_DEVPLUGIN_IRQ                0x1000
+#define BF_USBPHY_CTRL_DEVPLUGIN_IRQ(v)             (((v) & 0x1) << 12)
+#define BFM_USBPHY_CTRL_DEVPLUGIN_IRQ(v)            BM_USBPHY_CTRL_DEVPLUGIN_IRQ
+#define BF_USBPHY_CTRL_DEVPLUGIN_IRQ_V(e)           BF_USBPHY_CTRL_DEVPLUGIN_IRQ(BV_USBPHY_CTRL_DEVPLUGIN_IRQ__##e)
+#define BFM_USBPHY_CTRL_DEVPLUGIN_IRQ_V(v)          BM_USBPHY_CTRL_DEVPLUGIN_IRQ
+#define BP_USBPHY_CTRL_ENIRQDEVPLUGIN               11
+#define BM_USBPHY_CTRL_ENIRQDEVPLUGIN               0x800
+#define BF_USBPHY_CTRL_ENIRQDEVPLUGIN(v)            (((v) & 0x1) << 11)
+#define BFM_USBPHY_CTRL_ENIRQDEVPLUGIN(v)           BM_USBPHY_CTRL_ENIRQDEVPLUGIN
+#define BF_USBPHY_CTRL_ENIRQDEVPLUGIN_V(e)          BF_USBPHY_CTRL_ENIRQDEVPLUGIN(BV_USBPHY_CTRL_ENIRQDEVPLUGIN__##e)
+#define BFM_USBPHY_CTRL_ENIRQDEVPLUGIN_V(v)         BM_USBPHY_CTRL_ENIRQDEVPLUGIN
+#define BP_USBPHY_CTRL_RESUME_IRQ                   10
+#define BM_USBPHY_CTRL_RESUME_IRQ                   0x400
+#define BF_USBPHY_CTRL_RESUME_IRQ(v)                (((v) & 0x1) << 10)
+#define BFM_USBPHY_CTRL_RESUME_IRQ(v)               BM_USBPHY_CTRL_RESUME_IRQ
+#define BF_USBPHY_CTRL_RESUME_IRQ_V(e)              BF_USBPHY_CTRL_RESUME_IRQ(BV_USBPHY_CTRL_RESUME_IRQ__##e)
+#define BFM_USBPHY_CTRL_RESUME_IRQ_V(v)             BM_USBPHY_CTRL_RESUME_IRQ
+#define BP_USBPHY_CTRL_ENIRQRESUMEDETECT            9
+#define BM_USBPHY_CTRL_ENIRQRESUMEDETECT            0x200
+#define BF_USBPHY_CTRL_ENIRQRESUMEDETECT(v)         (((v) & 0x1) << 9)
+#define BFM_USBPHY_CTRL_ENIRQRESUMEDETECT(v)        BM_USBPHY_CTRL_ENIRQRESUMEDETECT
+#define BF_USBPHY_CTRL_ENIRQRESUMEDETECT_V(e)       BF_USBPHY_CTRL_ENIRQRESUMEDETECT(BV_USBPHY_CTRL_ENIRQRESUMEDETECT__##e)
+#define BFM_USBPHY_CTRL_ENIRQRESUMEDETECT_V(v)      BM_USBPHY_CTRL_ENIRQRESUMEDETECT
+#define BP_USBPHY_CTRL_RSVD2                        8
+#define BM_USBPHY_CTRL_RSVD2                        0x100
+#define BF_USBPHY_CTRL_RSVD2(v)                     (((v) & 0x1) << 8)
+#define BFM_USBPHY_CTRL_RSVD2(v)                    BM_USBPHY_CTRL_RSVD2
+#define BF_USBPHY_CTRL_RSVD2_V(e)                   BF_USBPHY_CTRL_RSVD2(BV_USBPHY_CTRL_RSVD2__##e)
+#define BFM_USBPHY_CTRL_RSVD2_V(v)                  BM_USBPHY_CTRL_RSVD2
+#define BP_USBPHY_CTRL_ENOTGIDDETECT                7
+#define BM_USBPHY_CTRL_ENOTGIDDETECT                0x80
+#define BF_USBPHY_CTRL_ENOTGIDDETECT(v)             (((v) & 0x1) << 7)
+#define BFM_USBPHY_CTRL_ENOTGIDDETECT(v)            BM_USBPHY_CTRL_ENOTGIDDETECT
+#define BF_USBPHY_CTRL_ENOTGIDDETECT_V(e)           BF_USBPHY_CTRL_ENOTGIDDETECT(BV_USBPHY_CTRL_ENOTGIDDETECT__##e)
+#define BFM_USBPHY_CTRL_ENOTGIDDETECT_V(v)          BM_USBPHY_CTRL_ENOTGIDDETECT
+#define BP_USBPHY_CTRL_RSVD1                        6
+#define BM_USBPHY_CTRL_RSVD1                        0x40
+#define BF_USBPHY_CTRL_RSVD1(v)                     (((v) & 0x1) << 6)
+#define BFM_USBPHY_CTRL_RSVD1(v)                    BM_USBPHY_CTRL_RSVD1
+#define BF_USBPHY_CTRL_RSVD1_V(e)                   BF_USBPHY_CTRL_RSVD1(BV_USBPHY_CTRL_RSVD1__##e)
+#define BFM_USBPHY_CTRL_RSVD1_V(v)                  BM_USBPHY_CTRL_RSVD1
+#define BP_USBPHY_CTRL_DEVPLUGIN_POLARITY           5
+#define BM_USBPHY_CTRL_DEVPLUGIN_POLARITY           0x20
+#define BF_USBPHY_CTRL_DEVPLUGIN_POLARITY(v)        (((v) & 0x1) << 5)
+#define BFM_USBPHY_CTRL_DEVPLUGIN_POLARITY(v)       BM_USBPHY_CTRL_DEVPLUGIN_POLARITY
+#define BF_USBPHY_CTRL_DEVPLUGIN_POLARITY_V(e)      BF_USBPHY_CTRL_DEVPLUGIN_POLARITY(BV_USBPHY_CTRL_DEVPLUGIN_POLARITY__##e)
+#define BFM_USBPHY_CTRL_DEVPLUGIN_POLARITY_V(v)     BM_USBPHY_CTRL_DEVPLUGIN_POLARITY
+#define BP_USBPHY_CTRL_ENDEVPLUGINDETECT            4
+#define BM_USBPHY_CTRL_ENDEVPLUGINDETECT            0x10
+#define BF_USBPHY_CTRL_ENDEVPLUGINDETECT(v)         (((v) & 0x1) << 4)
+#define BFM_USBPHY_CTRL_ENDEVPLUGINDETECT(v)        BM_USBPHY_CTRL_ENDEVPLUGINDETECT
+#define BF_USBPHY_CTRL_ENDEVPLUGINDETECT_V(e)       BF_USBPHY_CTRL_ENDEVPLUGINDETECT(BV_USBPHY_CTRL_ENDEVPLUGINDETECT__##e)
+#define BFM_USBPHY_CTRL_ENDEVPLUGINDETECT_V(v)      BM_USBPHY_CTRL_ENDEVPLUGINDETECT
+#define BP_USBPHY_CTRL_HOSTDISCONDETECT_IRQ         3
+#define BM_USBPHY_CTRL_HOSTDISCONDETECT_IRQ         0x8
+#define BF_USBPHY_CTRL_HOSTDISCONDETECT_IRQ(v)      (((v) & 0x1) << 3)
+#define BFM_USBPHY_CTRL_HOSTDISCONDETECT_IRQ(v)     BM_USBPHY_CTRL_HOSTDISCONDETECT_IRQ
+#define BF_USBPHY_CTRL_HOSTDISCONDETECT_IRQ_V(e)    BF_USBPHY_CTRL_HOSTDISCONDETECT_IRQ(BV_USBPHY_CTRL_HOSTDISCONDETECT_IRQ__##e)
+#define BFM_USBPHY_CTRL_HOSTDISCONDETECT_IRQ_V(v)   BM_USBPHY_CTRL_HOSTDISCONDETECT_IRQ
+#define BP_USBPHY_CTRL_ENIRQHOSTDISCON              2
+#define BM_USBPHY_CTRL_ENIRQHOSTDISCON              0x4
+#define BF_USBPHY_CTRL_ENIRQHOSTDISCON(v)           (((v) & 0x1) << 2)
+#define BFM_USBPHY_CTRL_ENIRQHOSTDISCON(v)          BM_USBPHY_CTRL_ENIRQHOSTDISCON
+#define BF_USBPHY_CTRL_ENIRQHOSTDISCON_V(e)         BF_USBPHY_CTRL_ENIRQHOSTDISCON(BV_USBPHY_CTRL_ENIRQHOSTDISCON__##e)
+#define BFM_USBPHY_CTRL_ENIRQHOSTDISCON_V(v)        BM_USBPHY_CTRL_ENIRQHOSTDISCON
+#define BP_USBPHY_CTRL_ENHOSTDISCONDETECT           1
+#define BM_USBPHY_CTRL_ENHOSTDISCONDETECT           0x2
+#define BF_USBPHY_CTRL_ENHOSTDISCONDETECT(v)        (((v) & 0x1) << 1)
+#define BFM_USBPHY_CTRL_ENHOSTDISCONDETECT(v)       BM_USBPHY_CTRL_ENHOSTDISCONDETECT
+#define BF_USBPHY_CTRL_ENHOSTDISCONDETECT_V(e)      BF_USBPHY_CTRL_ENHOSTDISCONDETECT(BV_USBPHY_CTRL_ENHOSTDISCONDETECT__##e)
+#define BFM_USBPHY_CTRL_ENHOSTDISCONDETECT_V(v)     BM_USBPHY_CTRL_ENHOSTDISCONDETECT
+#define BP_USBPHY_CTRL_RSVD0                        0
+#define BM_USBPHY_CTRL_RSVD0                        0x1
+#define BF_USBPHY_CTRL_RSVD0(v)                     (((v) & 0x1) << 0)
+#define BFM_USBPHY_CTRL_RSVD0(v)                    BM_USBPHY_CTRL_RSVD0
+#define BF_USBPHY_CTRL_RSVD0_V(e)                   BF_USBPHY_CTRL_RSVD0(BV_USBPHY_CTRL_RSVD0__##e)
+#define BFM_USBPHY_CTRL_RSVD0_V(v)                  BM_USBPHY_CTRL_RSVD0
+
+#define HW_USBPHY_STATUS                                HW(USBPHY_STATUS)
+#define HWA_USBPHY_STATUS                               (0x8007c000 + 0x40)
+#define HWT_USBPHY_STATUS                               HWIO_32_RW
+#define HWN_USBPHY_STATUS                               USBPHY_STATUS
+#define HWI_USBPHY_STATUS                               
+#define BP_USBPHY_STATUS_RSVD4                          11
+#define BM_USBPHY_STATUS_RSVD4                          0xfffff800
+#define BF_USBPHY_STATUS_RSVD4(v)                       (((v) & 0x1fffff) << 11)
+#define BFM_USBPHY_STATUS_RSVD4(v)                      BM_USBPHY_STATUS_RSVD4
+#define BF_USBPHY_STATUS_RSVD4_V(e)                     BF_USBPHY_STATUS_RSVD4(BV_USBPHY_STATUS_RSVD4__##e)
+#define BFM_USBPHY_STATUS_RSVD4_V(v)                    BM_USBPHY_STATUS_RSVD4
+#define BP_USBPHY_STATUS_RESUME_STATUS                  10
+#define BM_USBPHY_STATUS_RESUME_STATUS                  0x400
+#define BF_USBPHY_STATUS_RESUME_STATUS(v)               (((v) & 0x1) << 10)
+#define BFM_USBPHY_STATUS_RESUME_STATUS(v)              BM_USBPHY_STATUS_RESUME_STATUS
+#define BF_USBPHY_STATUS_RESUME_STATUS_V(e)             BF_USBPHY_STATUS_RESUME_STATUS(BV_USBPHY_STATUS_RESUME_STATUS__##e)
+#define BFM_USBPHY_STATUS_RESUME_STATUS_V(v)            BM_USBPHY_STATUS_RESUME_STATUS
+#define BP_USBPHY_STATUS_RSVD3                          9
+#define BM_USBPHY_STATUS_RSVD3                          0x200
+#define BF_USBPHY_STATUS_RSVD3(v)                       (((v) & 0x1) << 9)
+#define BFM_USBPHY_STATUS_RSVD3(v)                      BM_USBPHY_STATUS_RSVD3
+#define BF_USBPHY_STATUS_RSVD3_V(e)                     BF_USBPHY_STATUS_RSVD3(BV_USBPHY_STATUS_RSVD3__##e)
+#define BFM_USBPHY_STATUS_RSVD3_V(v)                    BM_USBPHY_STATUS_RSVD3
+#define BP_USBPHY_STATUS_OTGID_STATUS                   8
+#define BM_USBPHY_STATUS_OTGID_STATUS                   0x100
+#define BF_USBPHY_STATUS_OTGID_STATUS(v)                (((v) & 0x1) << 8)
+#define BFM_USBPHY_STATUS_OTGID_STATUS(v)               BM_USBPHY_STATUS_OTGID_STATUS
+#define BF_USBPHY_STATUS_OTGID_STATUS_V(e)              BF_USBPHY_STATUS_OTGID_STATUS(BV_USBPHY_STATUS_OTGID_STATUS__##e)
+#define BFM_USBPHY_STATUS_OTGID_STATUS_V(v)             BM_USBPHY_STATUS_OTGID_STATUS
+#define BP_USBPHY_STATUS_RSVD2                          7
+#define BM_USBPHY_STATUS_RSVD2                          0x80
+#define BF_USBPHY_STATUS_RSVD2(v)                       (((v) & 0x1) << 7)
+#define BFM_USBPHY_STATUS_RSVD2(v)                      BM_USBPHY_STATUS_RSVD2
+#define BF_USBPHY_STATUS_RSVD2_V(e)                     BF_USBPHY_STATUS_RSVD2(BV_USBPHY_STATUS_RSVD2__##e)
+#define BFM_USBPHY_STATUS_RSVD2_V(v)                    BM_USBPHY_STATUS_RSVD2
+#define BP_USBPHY_STATUS_DEVPLUGIN_STATUS               6
+#define BM_USBPHY_STATUS_DEVPLUGIN_STATUS               0x40
+#define BF_USBPHY_STATUS_DEVPLUGIN_STATUS(v)            (((v) & 0x1) << 6)
+#define BFM_USBPHY_STATUS_DEVPLUGIN_STATUS(v)           BM_USBPHY_STATUS_DEVPLUGIN_STATUS
+#define BF_USBPHY_STATUS_DEVPLUGIN_STATUS_V(e)          BF_USBPHY_STATUS_DEVPLUGIN_STATUS(BV_USBPHY_STATUS_DEVPLUGIN_STATUS__##e)
+#define BFM_USBPHY_STATUS_DEVPLUGIN_STATUS_V(v)         BM_USBPHY_STATUS_DEVPLUGIN_STATUS
+#define BP_USBPHY_STATUS_RSVD1                          4
+#define BM_USBPHY_STATUS_RSVD1                          0x30
+#define BF_USBPHY_STATUS_RSVD1(v)                       (((v) & 0x3) << 4)
+#define BFM_USBPHY_STATUS_RSVD1(v)                      BM_USBPHY_STATUS_RSVD1
+#define BF_USBPHY_STATUS_RSVD1_V(e)                     BF_USBPHY_STATUS_RSVD1(BV_USBPHY_STATUS_RSVD1__##e)
+#define BFM_USBPHY_STATUS_RSVD1_V(v)                    BM_USBPHY_STATUS_RSVD1
+#define BP_USBPHY_STATUS_HOSTDISCONDETECT_STATUS        3
+#define BM_USBPHY_STATUS_HOSTDISCONDETECT_STATUS        0x8
+#define BF_USBPHY_STATUS_HOSTDISCONDETECT_STATUS(v)     (((v) & 0x1) << 3)
+#define BFM_USBPHY_STATUS_HOSTDISCONDETECT_STATUS(v)    BM_USBPHY_STATUS_HOSTDISCONDETECT_STATUS
+#define BF_USBPHY_STATUS_HOSTDISCONDETECT_STATUS_V(e)   BF_USBPHY_STATUS_HOSTDISCONDETECT_STATUS(BV_USBPHY_STATUS_HOSTDISCONDETECT_STATUS__##e)
+#define BFM_USBPHY_STATUS_HOSTDISCONDETECT_STATUS_V(v)  BM_USBPHY_STATUS_HOSTDISCONDETECT_STATUS
+#define BP_USBPHY_STATUS_RSVD0                          0
+#define BM_USBPHY_STATUS_RSVD0                          0x7
+#define BF_USBPHY_STATUS_RSVD0(v)                       (((v) & 0x7) << 0)
+#define BFM_USBPHY_STATUS_RSVD0(v)                      BM_USBPHY_STATUS_RSVD0
+#define BF_USBPHY_STATUS_RSVD0_V(e)                     BF_USBPHY_STATUS_RSVD0(BV_USBPHY_STATUS_RSVD0__##e)
+#define BFM_USBPHY_STATUS_RSVD0_V(v)                    BM_USBPHY_STATUS_RSVD0
+
+#define HW_USBPHY_DEBUG                             HW(USBPHY_DEBUG)
+#define HWA_USBPHY_DEBUG                            (0x8007c000 + 0x50)
+#define HWT_USBPHY_DEBUG                            HWIO_32_RW
+#define HWN_USBPHY_DEBUG                            USBPHY_DEBUG
+#define HWI_USBPHY_DEBUG                            
+#define HW_USBPHY_DEBUG_SET                         HW(USBPHY_DEBUG_SET)
+#define HWA_USBPHY_DEBUG_SET                        (HWA_USBPHY_DEBUG + 0x4)
+#define HWT_USBPHY_DEBUG_SET                        HWIO_32_WO
+#define HWN_USBPHY_DEBUG_SET                        USBPHY_DEBUG
+#define HWI_USBPHY_DEBUG_SET                        
+#define HW_USBPHY_DEBUG_CLR                         HW(USBPHY_DEBUG_CLR)
+#define HWA_USBPHY_DEBUG_CLR                        (HWA_USBPHY_DEBUG + 0x8)
+#define HWT_USBPHY_DEBUG_CLR                        HWIO_32_WO
+#define HWN_USBPHY_DEBUG_CLR                        USBPHY_DEBUG
+#define HWI_USBPHY_DEBUG_CLR                        
+#define HW_USBPHY_DEBUG_TOG                         HW(USBPHY_DEBUG_TOG)
+#define HWA_USBPHY_DEBUG_TOG                        (HWA_USBPHY_DEBUG + 0xc)
+#define HWT_USBPHY_DEBUG_TOG                        HWIO_32_WO
+#define HWN_USBPHY_DEBUG_TOG                        USBPHY_DEBUG
+#define HWI_USBPHY_DEBUG_TOG                        
+#define BP_USBPHY_DEBUG_RSVD3                       31
+#define BM_USBPHY_DEBUG_RSVD3                       0x80000000
+#define BF_USBPHY_DEBUG_RSVD3(v)                    (((v) & 0x1) << 31)
+#define BFM_USBPHY_DEBUG_RSVD3(v)                   BM_USBPHY_DEBUG_RSVD3
+#define BF_USBPHY_DEBUG_RSVD3_V(e)                  BF_USBPHY_DEBUG_RSVD3(BV_USBPHY_DEBUG_RSVD3__##e)
+#define BFM_USBPHY_DEBUG_RSVD3_V(v)                 BM_USBPHY_DEBUG_RSVD3
+#define BP_USBPHY_DEBUG_CLKGATE                     30
+#define BM_USBPHY_DEBUG_CLKGATE                     0x40000000
+#define BF_USBPHY_DEBUG_CLKGATE(v)                  (((v) & 0x1) << 30)
+#define BFM_USBPHY_DEBUG_CLKGATE(v)                 BM_USBPHY_DEBUG_CLKGATE
+#define BF_USBPHY_DEBUG_CLKGATE_V(e)                BF_USBPHY_DEBUG_CLKGATE(BV_USBPHY_DEBUG_CLKGATE__##e)
+#define BFM_USBPHY_DEBUG_CLKGATE_V(v)               BM_USBPHY_DEBUG_CLKGATE
+#define BP_USBPHY_DEBUG_HOST_RESUME_DEBUG           29
+#define BM_USBPHY_DEBUG_HOST_RESUME_DEBUG           0x20000000
+#define BF_USBPHY_DEBUG_HOST_RESUME_DEBUG(v)        (((v) & 0x1) << 29)
+#define BFM_USBPHY_DEBUG_HOST_RESUME_DEBUG(v)       BM_USBPHY_DEBUG_HOST_RESUME_DEBUG
+#define BF_USBPHY_DEBUG_HOST_RESUME_DEBUG_V(e)      BF_USBPHY_DEBUG_HOST_RESUME_DEBUG(BV_USBPHY_DEBUG_HOST_RESUME_DEBUG__##e)
+#define BFM_USBPHY_DEBUG_HOST_RESUME_DEBUG_V(v)     BM_USBPHY_DEBUG_HOST_RESUME_DEBUG
+#define BP_USBPHY_DEBUG_SQUELCHRESETLENGTH          25
+#define BM_USBPHY_DEBUG_SQUELCHRESETLENGTH          0x1e000000
+#define BF_USBPHY_DEBUG_SQUELCHRESETLENGTH(v)       (((v) & 0xf) << 25)
+#define BFM_USBPHY_DEBUG_SQUELCHRESETLENGTH(v)      BM_USBPHY_DEBUG_SQUELCHRESETLENGTH
+#define BF_USBPHY_DEBUG_SQUELCHRESETLENGTH_V(e)     BF_USBPHY_DEBUG_SQUELCHRESETLENGTH(BV_USBPHY_DEBUG_SQUELCHRESETLENGTH__##e)
+#define BFM_USBPHY_DEBUG_SQUELCHRESETLENGTH_V(v)    BM_USBPHY_DEBUG_SQUELCHRESETLENGTH
+#define BP_USBPHY_DEBUG_ENSQUELCHRESET              24
+#define BM_USBPHY_DEBUG_ENSQUELCHRESET              0x1000000
+#define BF_USBPHY_DEBUG_ENSQUELCHRESET(v)           (((v) & 0x1) << 24)
+#define BFM_USBPHY_DEBUG_ENSQUELCHRESET(v)          BM_USBPHY_DEBUG_ENSQUELCHRESET
+#define BF_USBPHY_DEBUG_ENSQUELCHRESET_V(e)         BF_USBPHY_DEBUG_ENSQUELCHRESET(BV_USBPHY_DEBUG_ENSQUELCHRESET__##e)
+#define BFM_USBPHY_DEBUG_ENSQUELCHRESET_V(v)        BM_USBPHY_DEBUG_ENSQUELCHRESET
+#define BP_USBPHY_DEBUG_RSVD2                       21
+#define BM_USBPHY_DEBUG_RSVD2                       0xe00000
+#define BF_USBPHY_DEBUG_RSVD2(v)                    (((v) & 0x7) << 21)
+#define BFM_USBPHY_DEBUG_RSVD2(v)                   BM_USBPHY_DEBUG_RSVD2
+#define BF_USBPHY_DEBUG_RSVD2_V(e)                  BF_USBPHY_DEBUG_RSVD2(BV_USBPHY_DEBUG_RSVD2__##e)
+#define BFM_USBPHY_DEBUG_RSVD2_V(v)                 BM_USBPHY_DEBUG_RSVD2
+#define BP_USBPHY_DEBUG_SQUELCHRESETCOUNT           16
+#define BM_USBPHY_DEBUG_SQUELCHRESETCOUNT           0x1f0000
+#define BF_USBPHY_DEBUG_SQUELCHRESETCOUNT(v)        (((v) & 0x1f) << 16)
+#define BFM_USBPHY_DEBUG_SQUELCHRESETCOUNT(v)       BM_USBPHY_DEBUG_SQUELCHRESETCOUNT
+#define BF_USBPHY_DEBUG_SQUELCHRESETCOUNT_V(e)      BF_USBPHY_DEBUG_SQUELCHRESETCOUNT(BV_USBPHY_DEBUG_SQUELCHRESETCOUNT__##e)
+#define BFM_USBPHY_DEBUG_SQUELCHRESETCOUNT_V(v)     BM_USBPHY_DEBUG_SQUELCHRESETCOUNT
+#define BP_USBPHY_DEBUG_RSVD1                       13
+#define BM_USBPHY_DEBUG_RSVD1                       0xe000
+#define BF_USBPHY_DEBUG_RSVD1(v)                    (((v) & 0x7) << 13)
+#define BFM_USBPHY_DEBUG_RSVD1(v)                   BM_USBPHY_DEBUG_RSVD1
+#define BF_USBPHY_DEBUG_RSVD1_V(e)                  BF_USBPHY_DEBUG_RSVD1(BV_USBPHY_DEBUG_RSVD1__##e)
+#define BFM_USBPHY_DEBUG_RSVD1_V(v)                 BM_USBPHY_DEBUG_RSVD1
+#define BP_USBPHY_DEBUG_ENTX2RXCOUNT                12
+#define BM_USBPHY_DEBUG_ENTX2RXCOUNT                0x1000
+#define BF_USBPHY_DEBUG_ENTX2RXCOUNT(v)             (((v) & 0x1) << 12)
+#define BFM_USBPHY_DEBUG_ENTX2RXCOUNT(v)            BM_USBPHY_DEBUG_ENTX2RXCOUNT
+#define BF_USBPHY_DEBUG_ENTX2RXCOUNT_V(e)           BF_USBPHY_DEBUG_ENTX2RXCOUNT(BV_USBPHY_DEBUG_ENTX2RXCOUNT__##e)
+#define BFM_USBPHY_DEBUG_ENTX2RXCOUNT_V(v)          BM_USBPHY_DEBUG_ENTX2RXCOUNT
+#define BP_USBPHY_DEBUG_TX2RXCOUNT                  8
+#define BM_USBPHY_DEBUG_TX2RXCOUNT                  0xf00
+#define BF_USBPHY_DEBUG_TX2RXCOUNT(v)               (((v) & 0xf) << 8)
+#define BFM_USBPHY_DEBUG_TX2RXCOUNT(v)              BM_USBPHY_DEBUG_TX2RXCOUNT
+#define BF_USBPHY_DEBUG_TX2RXCOUNT_V(e)             BF_USBPHY_DEBUG_TX2RXCOUNT(BV_USBPHY_DEBUG_TX2RXCOUNT__##e)
+#define BFM_USBPHY_DEBUG_TX2RXCOUNT_V(v)            BM_USBPHY_DEBUG_TX2RXCOUNT
+#define BP_USBPHY_DEBUG_RSVD0                       6
+#define BM_USBPHY_DEBUG_RSVD0                       0xc0
+#define BF_USBPHY_DEBUG_RSVD0(v)                    (((v) & 0x3) << 6)
+#define BFM_USBPHY_DEBUG_RSVD0(v)                   BM_USBPHY_DEBUG_RSVD0
+#define BF_USBPHY_DEBUG_RSVD0_V(e)                  BF_USBPHY_DEBUG_RSVD0(BV_USBPHY_DEBUG_RSVD0__##e)
+#define BFM_USBPHY_DEBUG_RSVD0_V(v)                 BM_USBPHY_DEBUG_RSVD0
+#define BP_USBPHY_DEBUG_ENHSTPULLDOWN               4
+#define BM_USBPHY_DEBUG_ENHSTPULLDOWN               0x30
+#define BF_USBPHY_DEBUG_ENHSTPULLDOWN(v)            (((v) & 0x3) << 4)
+#define BFM_USBPHY_DEBUG_ENHSTPULLDOWN(v)           BM_USBPHY_DEBUG_ENHSTPULLDOWN
+#define BF_USBPHY_DEBUG_ENHSTPULLDOWN_V(e)          BF_USBPHY_DEBUG_ENHSTPULLDOWN(BV_USBPHY_DEBUG_ENHSTPULLDOWN__##e)
+#define BFM_USBPHY_DEBUG_ENHSTPULLDOWN_V(v)         BM_USBPHY_DEBUG_ENHSTPULLDOWN
+#define BP_USBPHY_DEBUG_HSTPULLDOWN                 2
+#define BM_USBPHY_DEBUG_HSTPULLDOWN                 0xc
+#define BF_USBPHY_DEBUG_HSTPULLDOWN(v)              (((v) & 0x3) << 2)
+#define BFM_USBPHY_DEBUG_HSTPULLDOWN(v)             BM_USBPHY_DEBUG_HSTPULLDOWN
+#define BF_USBPHY_DEBUG_HSTPULLDOWN_V(e)            BF_USBPHY_DEBUG_HSTPULLDOWN(BV_USBPHY_DEBUG_HSTPULLDOWN__##e)
+#define BFM_USBPHY_DEBUG_HSTPULLDOWN_V(v)           BM_USBPHY_DEBUG_HSTPULLDOWN
+#define BP_USBPHY_DEBUG_DEBUG_INTERFACE_HOLD        1
+#define BM_USBPHY_DEBUG_DEBUG_INTERFACE_HOLD        0x2
+#define BF_USBPHY_DEBUG_DEBUG_INTERFACE_HOLD(v)     (((v) & 0x1) << 1)
+#define BFM_USBPHY_DEBUG_DEBUG_INTERFACE_HOLD(v)    BM_USBPHY_DEBUG_DEBUG_INTERFACE_HOLD
+#define BF_USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_V(e)   BF_USBPHY_DEBUG_DEBUG_INTERFACE_HOLD(BV_USBPHY_DEBUG_DEBUG_INTERFACE_HOLD__##e)
+#define BFM_USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_V(v)  BM_USBPHY_DEBUG_DEBUG_INTERFACE_HOLD
+#define BP_USBPHY_DEBUG_OTGIDPIOLOCK                0
+#define BM_USBPHY_DEBUG_OTGIDPIOLOCK                0x1
+#define BF_USBPHY_DEBUG_OTGIDPIOLOCK(v)             (((v) & 0x1) << 0)
+#define BFM_USBPHY_DEBUG_OTGIDPIOLOCK(v)            BM_USBPHY_DEBUG_OTGIDPIOLOCK
+#define BF_USBPHY_DEBUG_OTGIDPIOLOCK_V(e)           BF_USBPHY_DEBUG_OTGIDPIOLOCK(BV_USBPHY_DEBUG_OTGIDPIOLOCK__##e)
+#define BFM_USBPHY_DEBUG_OTGIDPIOLOCK_V(v)          BM_USBPHY_DEBUG_OTGIDPIOLOCK
+
+#define HW_USBPHY_DEBUG0_STATUS                                 HW(USBPHY_DEBUG0_STATUS)
+#define HWA_USBPHY_DEBUG0_STATUS                                (0x8007c000 + 0x60)
+#define HWT_USBPHY_DEBUG0_STATUS                                HWIO_32_RW
+#define HWN_USBPHY_DEBUG0_STATUS                                USBPHY_DEBUG0_STATUS
+#define HWI_USBPHY_DEBUG0_STATUS                                
+#define BP_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT                   26
+#define BM_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT                   0xfc000000
+#define BF_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT(v)                (((v) & 0x3f) << 26)
+#define BFM_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT(v)               BM_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT
+#define BF_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_V(e)              BF_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT(BV_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT__##e)
+#define BFM_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_V(v)             BM_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT
+#define BP_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT         16
+#define BM_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT         0x3ff0000
+#define BF_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT(v)      (((v) & 0x3ff) << 16)
+#define BFM_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT(v)     BM_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT
+#define BF_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_V(e)    BF_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT(BV_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT__##e)
+#define BFM_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_V(v)   BM_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT
+#define BP_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT            0
+#define BM_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT            0xffff
+#define BF_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT(v)         (((v) & 0xffff) << 0)
+#define BFM_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT(v)        BM_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT
+#define BF_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_V(e)       BF_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT(BV_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT__##e)
+#define BFM_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_V(v)      BM_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT
+
+#define HW_USBPHY_DEBUG1                    HW(USBPHY_DEBUG1)
+#define HWA_USBPHY_DEBUG1                   (0x8007c000 + 0x70)
+#define HWT_USBPHY_DEBUG1                   HWIO_32_RW
+#define HWN_USBPHY_DEBUG1                   USBPHY_DEBUG1
+#define HWI_USBPHY_DEBUG1                   
+#define HW_USBPHY_DEBUG1_SET                HW(USBPHY_DEBUG1_SET)
+#define HWA_USBPHY_DEBUG1_SET               (HWA_USBPHY_DEBUG1 + 0x4)
+#define HWT_USBPHY_DEBUG1_SET               HWIO_32_WO
+#define HWN_USBPHY_DEBUG1_SET               USBPHY_DEBUG1
+#define HWI_USBPHY_DEBUG1_SET               
+#define HW_USBPHY_DEBUG1_CLR                HW(USBPHY_DEBUG1_CLR)
+#define HWA_USBPHY_DEBUG1_CLR               (HWA_USBPHY_DEBUG1 + 0x8)
+#define HWT_USBPHY_DEBUG1_CLR               HWIO_32_WO
+#define HWN_USBPHY_DEBUG1_CLR               USBPHY_DEBUG1
+#define HWI_USBPHY_DEBUG1_CLR               
+#define HW_USBPHY_DEBUG1_TOG                HW(USBPHY_DEBUG1_TOG)
+#define HWA_USBPHY_DEBUG1_TOG               (HWA_USBPHY_DEBUG1 + 0xc)
+#define HWT_USBPHY_DEBUG1_TOG               HWIO_32_WO
+#define HWN_USBPHY_DEBUG1_TOG               USBPHY_DEBUG1
+#define HWI_USBPHY_DEBUG1_TOG               
+#define BP_USBPHY_DEBUG1_RSVD1              15
+#define BM_USBPHY_DEBUG1_RSVD1              0xffff8000
+#define BF_USBPHY_DEBUG1_RSVD1(v)           (((v) & 0x1ffff) << 15)
+#define BFM_USBPHY_DEBUG1_RSVD1(v)          BM_USBPHY_DEBUG1_RSVD1
+#define BF_USBPHY_DEBUG1_RSVD1_V(e)         BF_USBPHY_DEBUG1_RSVD1(BV_USBPHY_DEBUG1_RSVD1__##e)
+#define BFM_USBPHY_DEBUG1_RSVD1_V(v)        BM_USBPHY_DEBUG1_RSVD1
+#define BP_USBPHY_DEBUG1_ENTAILADJVD        13
+#define BM_USBPHY_DEBUG1_ENTAILADJVD        0x6000
+#define BF_USBPHY_DEBUG1_ENTAILADJVD(v)     (((v) & 0x3) << 13)
+#define BFM_USBPHY_DEBUG1_ENTAILADJVD(v)    BM_USBPHY_DEBUG1_ENTAILADJVD
+#define BF_USBPHY_DEBUG1_ENTAILADJVD_V(e)   BF_USBPHY_DEBUG1_ENTAILADJVD(BV_USBPHY_DEBUG1_ENTAILADJVD__##e)
+#define BFM_USBPHY_DEBUG1_ENTAILADJVD_V(v)  BM_USBPHY_DEBUG1_ENTAILADJVD
+#define BP_USBPHY_DEBUG1_ENTX2TX            12
+#define BM_USBPHY_DEBUG1_ENTX2TX            0x1000
+#define BF_USBPHY_DEBUG1_ENTX2TX(v)         (((v) & 0x1) << 12)
+#define BFM_USBPHY_DEBUG1_ENTX2TX(v)        BM_USBPHY_DEBUG1_ENTX2TX
+#define BF_USBPHY_DEBUG1_ENTX2TX_V(e)       BF_USBPHY_DEBUG1_ENTX2TX(BV_USBPHY_DEBUG1_ENTX2TX__##e)
+#define BFM_USBPHY_DEBUG1_ENTX2TX_V(v)      BM_USBPHY_DEBUG1_ENTX2TX
+#define BP_USBPHY_DEBUG1_RSVD0              4
+#define BM_USBPHY_DEBUG1_RSVD0              0xff0
+#define BF_USBPHY_DEBUG1_RSVD0(v)           (((v) & 0xff) << 4)
+#define BFM_USBPHY_DEBUG1_RSVD0(v)          BM_USBPHY_DEBUG1_RSVD0
+#define BF_USBPHY_DEBUG1_RSVD0_V(e)         BF_USBPHY_DEBUG1_RSVD0(BV_USBPHY_DEBUG1_RSVD0__##e)
+#define BFM_USBPHY_DEBUG1_RSVD0_V(v)        BM_USBPHY_DEBUG1_RSVD0
+#define BP_USBPHY_DEBUG1_DBG_ADDRESS        0
+#define BM_USBPHY_DEBUG1_DBG_ADDRESS        0xf
+#define BF_USBPHY_DEBUG1_DBG_ADDRESS(v)     (((v) & 0xf) << 0)
+#define BFM_USBPHY_DEBUG1_DBG_ADDRESS(v)    BM_USBPHY_DEBUG1_DBG_ADDRESS
+#define BF_USBPHY_DEBUG1_DBG_ADDRESS_V(e)   BF_USBPHY_DEBUG1_DBG_ADDRESS(BV_USBPHY_DEBUG1_DBG_ADDRESS__##e)
+#define BFM_USBPHY_DEBUG1_DBG_ADDRESS_V(v)  BM_USBPHY_DEBUG1_DBG_ADDRESS
+
+#define HW_USBPHY_VERSION               HW(USBPHY_VERSION)
+#define HWA_USBPHY_VERSION              (0x8007c000 + 0x80)
+#define HWT_USBPHY_VERSION              HWIO_32_RW
+#define HWN_USBPHY_VERSION              USBPHY_VERSION
+#define HWI_USBPHY_VERSION              
+#define BP_USBPHY_VERSION_MAJOR         24
+#define BM_USBPHY_VERSION_MAJOR         0xff000000
+#define BF_USBPHY_VERSION_MAJOR(v)      (((v) & 0xff) << 24)
+#define BFM_USBPHY_VERSION_MAJOR(v)     BM_USBPHY_VERSION_MAJOR
+#define BF_USBPHY_VERSION_MAJOR_V(e)    BF_USBPHY_VERSION_MAJOR(BV_USBPHY_VERSION_MAJOR__##e)
+#define BFM_USBPHY_VERSION_MAJOR_V(v)   BM_USBPHY_VERSION_MAJOR
+#define BP_USBPHY_VERSION_MINOR         16
+#define BM_USBPHY_VERSION_MINOR         0xff0000
+#define BF_USBPHY_VERSION_MINOR(v)      (((v) & 0xff) << 16)
+#define BFM_USBPHY_VERSION_MINOR(v)     BM_USBPHY_VERSION_MINOR
+#define BF_USBPHY_VERSION_MINOR_V(e)    BF_USBPHY_VERSION_MINOR(BV_USBPHY_VERSION_MINOR__##e)
+#define BFM_USBPHY_VERSION_MINOR_V(v)   BM_USBPHY_VERSION_MINOR
+#define BP_USBPHY_VERSION_STEP          0
+#define BM_USBPHY_VERSION_STEP          0xffff
+#define BF_USBPHY_VERSION_STEP(v)       (((v) & 0xffff) << 0)
+#define BFM_USBPHY_VERSION_STEP(v)      BM_USBPHY_VERSION_STEP
+#define BF_USBPHY_VERSION_STEP_V(e)     BF_USBPHY_VERSION_STEP(BV_USBPHY_VERSION_STEP__##e)
+#define BFM_USBPHY_VERSION_STEP_V(v)    BM_USBPHY_VERSION_STEP
+
+#define HW_USBPHY_IP                        HW(USBPHY_IP)
+#define HWA_USBPHY_IP                       (0x8007c000 + 0x90)
+#define HWT_USBPHY_IP                       HWIO_32_RW
+#define HWN_USBPHY_IP                       USBPHY_IP
+#define HWI_USBPHY_IP                       
+#define HW_USBPHY_IP_SET                    HW(USBPHY_IP_SET)
+#define HWA_USBPHY_IP_SET                   (HWA_USBPHY_IP + 0x4)
+#define HWT_USBPHY_IP_SET                   HWIO_32_WO
+#define HWN_USBPHY_IP_SET                   USBPHY_IP
+#define HWI_USBPHY_IP_SET                   
+#define HW_USBPHY_IP_CLR                    HW(USBPHY_IP_CLR)
+#define HWA_USBPHY_IP_CLR                   (HWA_USBPHY_IP + 0x8)
+#define HWT_USBPHY_IP_CLR                   HWIO_32_WO
+#define HWN_USBPHY_IP_CLR                   USBPHY_IP
+#define HWI_USBPHY_IP_CLR                   
+#define HW_USBPHY_IP_TOG                    HW(USBPHY_IP_TOG)
+#define HWA_USBPHY_IP_TOG                   (HWA_USBPHY_IP + 0xc)
+#define HWT_USBPHY_IP_TOG                   HWIO_32_WO
+#define HWN_USBPHY_IP_TOG                   USBPHY_IP
+#define HWI_USBPHY_IP_TOG                   
+#define BP_USBPHY_IP_RSVD1                  25
+#define BM_USBPHY_IP_RSVD1                  0xfe000000
+#define BF_USBPHY_IP_RSVD1(v)               (((v) & 0x7f) << 25)
+#define BFM_USBPHY_IP_RSVD1(v)              BM_USBPHY_IP_RSVD1
+#define BF_USBPHY_IP_RSVD1_V(e)             BF_USBPHY_IP_RSVD1(BV_USBPHY_IP_RSVD1__##e)
+#define BFM_USBPHY_IP_RSVD1_V(v)            BM_USBPHY_IP_RSVD1
+#define BP_USBPHY_IP_DIV_SEL                23
+#define BM_USBPHY_IP_DIV_SEL                0x1800000
+#define BV_USBPHY_IP_DIV_SEL__DEFAULT       0x0
+#define BV_USBPHY_IP_DIV_SEL__LOWER         0x1
+#define BV_USBPHY_IP_DIV_SEL__LOWEST        0x2
+#define BV_USBPHY_IP_DIV_SEL__UNDEFINED     0x3
+#define BF_USBPHY_IP_DIV_SEL(v)             (((v) & 0x3) << 23)
+#define BFM_USBPHY_IP_DIV_SEL(v)            BM_USBPHY_IP_DIV_SEL
+#define BF_USBPHY_IP_DIV_SEL_V(e)           BF_USBPHY_IP_DIV_SEL(BV_USBPHY_IP_DIV_SEL__##e)
+#define BFM_USBPHY_IP_DIV_SEL_V(v)          BM_USBPHY_IP_DIV_SEL
+#define BP_USBPHY_IP_LFR_SEL                21
+#define BM_USBPHY_IP_LFR_SEL                0x600000
+#define BV_USBPHY_IP_LFR_SEL__DEFAULT       0x0
+#define BV_USBPHY_IP_LFR_SEL__TIMES_2       0x1
+#define BV_USBPHY_IP_LFR_SEL__TIMES_05      0x2
+#define BV_USBPHY_IP_LFR_SEL__UNDEFINED     0x3
+#define BF_USBPHY_IP_LFR_SEL(v)             (((v) & 0x3) << 21)
+#define BFM_USBPHY_IP_LFR_SEL(v)            BM_USBPHY_IP_LFR_SEL
+#define BF_USBPHY_IP_LFR_SEL_V(e)           BF_USBPHY_IP_LFR_SEL(BV_USBPHY_IP_LFR_SEL__##e)
+#define BFM_USBPHY_IP_LFR_SEL_V(v)          BM_USBPHY_IP_LFR_SEL
+#define BP_USBPHY_IP_CP_SEL                 19
+#define BM_USBPHY_IP_CP_SEL                 0x180000
+#define BV_USBPHY_IP_CP_SEL__DEFAULT        0x0
+#define BV_USBPHY_IP_CP_SEL__TIMES_2        0x1
+#define BV_USBPHY_IP_CP_SEL__TIMES_05       0x2
+#define BV_USBPHY_IP_CP_SEL__UNDEFINED      0x3
+#define BF_USBPHY_IP_CP_SEL(v)              (((v) & 0x3) << 19)
+#define BFM_USBPHY_IP_CP_SEL(v)             BM_USBPHY_IP_CP_SEL
+#define BF_USBPHY_IP_CP_SEL_V(e)            BF_USBPHY_IP_CP_SEL(BV_USBPHY_IP_CP_SEL__##e)
+#define BFM_USBPHY_IP_CP_SEL_V(v)           BM_USBPHY_IP_CP_SEL
+#define BP_USBPHY_IP_TSTI_TX_DP             18
+#define BM_USBPHY_IP_TSTI_TX_DP             0x40000
+#define BF_USBPHY_IP_TSTI_TX_DP(v)          (((v) & 0x1) << 18)
+#define BFM_USBPHY_IP_TSTI_TX_DP(v)         BM_USBPHY_IP_TSTI_TX_DP
+#define BF_USBPHY_IP_TSTI_TX_DP_V(e)        BF_USBPHY_IP_TSTI_TX_DP(BV_USBPHY_IP_TSTI_TX_DP__##e)
+#define BFM_USBPHY_IP_TSTI_TX_DP_V(v)       BM_USBPHY_IP_TSTI_TX_DP
+#define BP_USBPHY_IP_TSTI_TX_DM             17
+#define BM_USBPHY_IP_TSTI_TX_DM             0x20000
+#define BF_USBPHY_IP_TSTI_TX_DM(v)          (((v) & 0x1) << 17)
+#define BFM_USBPHY_IP_TSTI_TX_DM(v)         BM_USBPHY_IP_TSTI_TX_DM
+#define BF_USBPHY_IP_TSTI_TX_DM_V(e)        BF_USBPHY_IP_TSTI_TX_DM(BV_USBPHY_IP_TSTI_TX_DM__##e)
+#define BFM_USBPHY_IP_TSTI_TX_DM_V(v)       BM_USBPHY_IP_TSTI_TX_DM
+#define BP_USBPHY_IP_ANALOG_TESTMODE        16
+#define BM_USBPHY_IP_ANALOG_TESTMODE        0x10000
+#define BF_USBPHY_IP_ANALOG_TESTMODE(v)     (((v) & 0x1) << 16)
+#define BFM_USBPHY_IP_ANALOG_TESTMODE(v)    BM_USBPHY_IP_ANALOG_TESTMODE
+#define BF_USBPHY_IP_ANALOG_TESTMODE_V(e)   BF_USBPHY_IP_ANALOG_TESTMODE(BV_USBPHY_IP_ANALOG_TESTMODE__##e)
+#define BFM_USBPHY_IP_ANALOG_TESTMODE_V(v)  BM_USBPHY_IP_ANALOG_TESTMODE
+#define BP_USBPHY_IP_RSVD0                  3
+#define BM_USBPHY_IP_RSVD0                  0xfff8
+#define BF_USBPHY_IP_RSVD0(v)               (((v) & 0x1fff) << 3)
+#define BFM_USBPHY_IP_RSVD0(v)              BM_USBPHY_IP_RSVD0
+#define BF_USBPHY_IP_RSVD0_V(e)             BF_USBPHY_IP_RSVD0(BV_USBPHY_IP_RSVD0__##e)
+#define BFM_USBPHY_IP_RSVD0_V(v)            BM_USBPHY_IP_RSVD0
+#define BP_USBPHY_IP_EN_USB_CLKS            2
+#define BM_USBPHY_IP_EN_USB_CLKS            0x4
+#define BF_USBPHY_IP_EN_USB_CLKS(v)         (((v) & 0x1) << 2)
+#define BFM_USBPHY_IP_EN_USB_CLKS(v)        BM_USBPHY_IP_EN_USB_CLKS
+#define BF_USBPHY_IP_EN_USB_CLKS_V(e)       BF_USBPHY_IP_EN_USB_CLKS(BV_USBPHY_IP_EN_USB_CLKS__##e)
+#define BFM_USBPHY_IP_EN_USB_CLKS_V(v)      BM_USBPHY_IP_EN_USB_CLKS
+#define BP_USBPHY_IP_PLL_LOCKED             1
+#define BM_USBPHY_IP_PLL_LOCKED             0x2
+#define BF_USBPHY_IP_PLL_LOCKED(v)          (((v) & 0x1) << 1)
+#define BFM_USBPHY_IP_PLL_LOCKED(v)         BM_USBPHY_IP_PLL_LOCKED
+#define BF_USBPHY_IP_PLL_LOCKED_V(e)        BF_USBPHY_IP_PLL_LOCKED(BV_USBPHY_IP_PLL_LOCKED__##e)
+#define BFM_USBPHY_IP_PLL_LOCKED_V(v)       BM_USBPHY_IP_PLL_LOCKED
+#define BP_USBPHY_IP_PLL_POWER              0
+#define BM_USBPHY_IP_PLL_POWER              0x1
+#define BF_USBPHY_IP_PLL_POWER(v)           (((v) & 0x1) << 0)
+#define BFM_USBPHY_IP_PLL_POWER(v)          BM_USBPHY_IP_PLL_POWER
+#define BF_USBPHY_IP_PLL_POWER_V(e)         BF_USBPHY_IP_PLL_POWER(BV_USBPHY_IP_PLL_POWER__##e)
+#define BFM_USBPHY_IP_PLL_POWER_V(v)        BM_USBPHY_IP_PLL_POWER
+
+#endif /* __HEADERGEN_IMX233_USBPHY_H__*/
diff --git a/firmware/target/arm/imx233/regs/regs-dcp.h b/firmware/target/arm/imx233/regs/ir.h
index add950fa16..61ef9d6b9d 100644
--- a/firmware/target/arm/imx233/regs/regs-dcp.h
+++ b/firmware/target/arm/imx233/regs/ir.h
@@ -6,10 +6,9 @@
  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
  *                     \/            \/     \/    \/            \/
  * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3700:3.2.0 imx233:3.2.0
+ * headergen version: 3.0.0
  *
- * Copyright (C) 2013 by Amaury Pouly
+ * Copyright (C) 2015 by the authors
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
@@ -20,16 +19,19 @@
  * KIND, either express or implied.
  *
  ****************************************************************************/
-#ifndef __SELECT__DCP__H__
-#define __SELECT__DCP__H__
-#include "regs-macro.h"
+#ifndef __HEADERGEN_IR_H__
+#define __HEADERGEN_IR_H__
 
-#define STMP3700_INCLUDE "stmp3700/regs-dcp.h"
-#define IMX233_INCLUDE "imx233/regs-dcp.h"
+#include "macro.h"
 
-#include "regs-select.h"
+#define STMP3600_INCLUDE    "stmp3600/ir.h"
+#define STMP3700_INCLUDE    "stmp3700/ir.h"
+#define IMX233_INCLUDE      "imx233/ir.h"
 
+#include "select.h"
+
+#undef STMP3600_INCLUDE
 #undef STMP3700_INCLUDE
 #undef IMX233_INCLUDE
 
-#endif /* __SELECT__DCP__H__ */
+#endif /* __HEADERGEN_IR_H__*/
diff --git a/firmware/target/arm/imx233/regs/lcdif.h b/firmware/target/arm/imx233/regs/lcdif.h
new file mode 100644
index 0000000000..506a9f4fac
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/lcdif.h
@@ -0,0 +1,37 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_LCDIF_H__
+#define __HEADERGEN_LCDIF_H__
+
+#include "macro.h"
+
+#define STMP3600_INCLUDE    "stmp3600/lcdif.h"
+#define STMP3700_INCLUDE    "stmp3700/lcdif.h"
+#define IMX233_INCLUDE      "imx233/lcdif.h"
+
+#include "select.h"
+
+#undef STMP3600_INCLUDE
+#undef STMP3700_INCLUDE
+#undef IMX233_INCLUDE
+
+#endif /* __HEADERGEN_LCDIF_H__*/
diff --git a/firmware/target/arm/imx233/regs/lradc.h b/firmware/target/arm/imx233/regs/lradc.h
new file mode 100644
index 0000000000..9680720de2
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/lradc.h
@@ -0,0 +1,37 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_LRADC_H__
+#define __HEADERGEN_LRADC_H__
+
+#include "macro.h"
+
+#define STMP3600_INCLUDE    "stmp3600/lradc.h"
+#define STMP3700_INCLUDE    "stmp3700/lradc.h"
+#define IMX233_INCLUDE      "imx233/lradc.h"
+
+#include "select.h"
+
+#undef STMP3600_INCLUDE
+#undef STMP3700_INCLUDE
+#undef IMX233_INCLUDE
+
+#endif /* __HEADERGEN_LRADC_H__*/
diff --git a/firmware/target/arm/imx233/regs/macro.h b/firmware/target/arm/imx233/regs/macro.h
new file mode 100644
index 0000000000..3e656dfad6
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/macro.h
@@ -0,0 +1,328 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_MACRO_H__
+#define __HEADERGEN_MACRO_H__
+
+#define __VAR_OR1(prefix, suffix) \
+    (prefix##suffix)
+#define __VAR_OR2(pre, s1, s2) \
+    (__VAR_OR1(pre, s1) | __VAR_OR1(pre, s2))
+#define __VAR_OR3(pre, s1, s2, s3) \
+    (__VAR_OR1(pre, s1) | __VAR_OR2(pre, s2, s3))
+#define __VAR_OR4(pre, s1, s2, s3, s4) \
+    (__VAR_OR2(pre, s1, s2) | __VAR_OR2(pre, s3, s4))
+#define __VAR_OR5(pre, s1, s2, s3, s4, s5) \
+    (__VAR_OR2(pre, s1, s2) | __VAR_OR3(pre, s3, s4, s5))
+#define __VAR_OR6(pre, s1, s2, s3, s4, s5, s6) \
+    (__VAR_OR3(pre, s1, s2, s3) | __VAR_OR3(pre, s4, s5, s6))
+#define __VAR_OR7(pre, s1, s2, s3, s4, s5, s6, s7) \
+    (__VAR_OR3(pre, s1, s2, s3) | __VAR_OR4(pre, s4, s5, s6, s7))
+#define __VAR_OR8(pre, s1, s2, s3, s4, s5, s6, s7, s8) \
+    (__VAR_OR4(pre, s1, s2, s3, s4) | __VAR_OR4(pre, s5, s6, s7, s8))
+#define __VAR_OR9(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9) \
+    (__VAR_OR4(pre, s1, s2, s3, s4) | __VAR_OR5(pre, s5, s6, s7, s8, s9))
+#define __VAR_OR10(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10) \
+    (__VAR_OR5(pre, s1, s2, s3, s4, s5) | __VAR_OR5(pre, s6, s7, s8, s9, s10))
+#define __VAR_OR11(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11) \
+    (__VAR_OR5(pre, s1, s2, s3, s4, s5) | __VAR_OR6(pre, s6, s7, s8, s9, s10, s11))
+#define __VAR_OR12(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12) \
+    (__VAR_OR6(pre, s1, s2, s3, s4, s5, s6) | __VAR_OR6(pre, s7, s8, s9, s10, s11, s12))
+#define __VAR_OR13(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13) \
+    (__VAR_OR6(pre, s1, s2, s3, s4, s5, s6) | __VAR_OR7(pre, s7, s8, s9, s10, s11, s12, s13))
+
+#define __VAR_NARGS(...) __VAR_NARGS_(__VA_ARGS__, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1)
+#define __VAR_NARGS_(_1, _2, _3, _4, _5, _6, _7, _8, _9, _10, _11, _12, _13, N, ...) N
+
+#define __VAR_EXPAND(macro, prefix, ...) __VAR_EXPAND_(macro, __VAR_NARGS(__VA_ARGS__), prefix, __VA_ARGS__)
+#define __VAR_EXPAND_(macro, cnt, prefix, ...) __VAR_EXPAND__(macro, cnt, prefix, __VA_ARGS__)
+#define __VAR_EXPAND__(macro, cnt, prefix, ...) __VAR_EXPAND___(macro##cnt, prefix, __VA_ARGS__)
+#define __VAR_EXPAND___(macro, prefix, ...) macro(prefix, __VA_ARGS__)
+
+#define HWIO_8_RO(op, name, ...)        HWIO_8_RO_##op(name, __VA_ARGS__)
+#define HWIO_8_RO_RD(name, ...)         (*(const volatile uint8_t *)(HWA_##name))
+#define HWIO_8_RO_WR(name, val)         _Static_assert(0, #name " is read-only")
+#define HWIO_8_RO_RMW(name, vand, vor)  _Static_assert(0, #name " is read-only")
+#define HWIO_8_RO_VAR(name, ...)        (*(const volatile uint8_t *)(HWA_##name))
+
+#define HWIO_16_RO(op, name, ...)       HWIO_16_RO_##op(name, __VA_ARGS__)
+#define HWIO_16_RO_RD(name, ...)        (*(const volatile uint16_t *)(HWA_##name))
+#define HWIO_16_RO_WR(name, val)        _Static_assert(0, #name " is read-only")
+#define HWIO_16_RO_RMW(name, vand, vor) _Static_assert(0, #name " is read-only")
+#define HWIO_16_RO_VAR(name, ...)       (*(const volatile uint16_t *)(HWA_##name))
+
+#define HWIO_32_RO(op, name, ...)       HWIO_32_RO_##op(name, __VA_ARGS__)
+#define HWIO_32_RO_RD(name, ...)        (*(const volatile uint32_t *)(HWA_##name))
+#define HWIO_32_RO_WR(name, val)        _Static_assert(0, #name " is read-only")
+#define HWIO_32_RO_RMW(name, vand, vor) _Static_assert(0, #name " is read-only")
+#define HWIO_32_RO_VAR(name, ...)       (*(const volatile uint32_t *)(HWA_##name))
+
+#define HWIO_8_RW(op, name, ...)        HWIO_8_RW_##op(name, __VA_ARGS__)
+#define HWIO_8_RW_RD(name, ...)         (*(volatile uint8_t *)(HWA_##name))
+#define HWIO_8_RW_WR(name, val)         (*(volatile uint8_t *)(HWA_##name)) = (val)
+#define HWIO_8_RW_RMW(name, vand, vor)  HWIO_8_RW_WR(name, (HWIO_8_RW_RD(name) & (vand)) | (vor))
+#define HWIO_8_RW_VAR(name, ...)        (*(volatile uint8_t *)(HWA_##name))
+
+#define HWIO_16_RW(op, name, ...)       HWIO_16_RW_##op(name, __VA_ARGS__)
+#define HWIO_16_RW_RD(name, ...)        (*(volatile uint16_t *)(HWA_##name))
+#define HWIO_16_RW_WR(name, val)        (*(volatile uint16_t *)(HWA_##name)) = (val)
+#define HWIO_16_RW_RMW(name, vand, vor) HWIO_16_RW_WR(name, (HWIO_16_RW_RD(name) & (vand)) | (vor))
+#define HWIO_16_RW_VAR(name, ...)       (*(volatile uint16_t *)(HWA_##name))
+
+#define HWIO_32_RW(op, name, ...)       HWIO_32_RW_##op(name, __VA_ARGS__)
+#define HWIO_32_RW_RD(name, ...)        (*(volatile uint32_t *)(HWA_##name))
+#define HWIO_32_RW_WR(name, val)        (*(volatile uint32_t *)(HWA_##name)) = (val)
+#define HWIO_32_RW_RMW(name, vand, vor) HWIO_32_RW_WR(name, (HWIO_32_RW_RD(name) & (vand)) | (vor))
+#define HWIO_32_RW_VAR(name, ...)       (*(volatile uint32_t *)(HWA_##name))
+
+#define HWIO_8_WO(op, name, ...)        HWIO_8_WO_##op(name, __VA_ARGS__)
+#define HWIO_8_WO_RD(name, ...)         ({_Static_assert(0, #name " is write-only"); 0;})
+#define HWIO_8_WO_WR(name, val)         (*(volatile uint8_t *)(HWA_##name)) = (val)
+#define HWIO_8_WO_RMW(name, vand, vor)  HWIO_8_WO_WR(name, vor)
+#define HWIO_8_WO_VAR(name, ...)        (*(volatile uint8_t *)(HWA_##name))
+
+#define HWIO_16_WO(op, name, ...)       HWIO_16_WO_##op(name, __VA_ARGS__)
+#define HWIO_16_WO_RD(name, ...)        ({_Static_assert(0, #name " is write-only"); 0;})
+#define HWIO_16_WO_WR(name, val)        (*(volatile uint16_t *)(HWA_##name)) = (val)
+#define HWIO_16_WO_RMW(name, vand, vor) HWIO_16_WO_WR(name, vor)
+#define HWIO_16_WO_VAR(name, ...)       (*(volatile uint16_t *)(HWA_##name))
+
+#define HWIO_32_WO(op, name, ...)       HWIO_32_WO_##op(name, __VA_ARGS__)
+#define HWIO_32_WO_RD(name, ...)        ({_Static_assert(0, #name " is write-only"); 0;})
+#define HWIO_32_WO_WR(name, val)        (*(volatile uint32_t *)(HWA_##name)) = (val)
+#define HWIO_32_WO_RMW(name, vand, vor) HWIO_32_WO_WR(name, vor)
+#define HWIO_32_WO_VAR(name, ...)       (*(volatile uint32_t *)(HWA_##name))
+
+
+/** __REG_VARIANT
+ *
+ * usage: __REG_VARIANT(register, variant_prefix, variant_postfix)
+ *
+ * effect: expands to register variant given as argument
+ * note: internal usage
+ * note: register must be fully qualified if indexed
+ *
+ * example: __REG_VARIANT(ICOLL_CTRL, , _SET)
+ * example: __REG_VARIANT(ICOLL_ENABLE(3), , _CLR)
+ */
+#define __REG_VARIANT(name, varp, vars) __REG_VARIANT_(HWN_##name, HWI_##name, varp, vars)
+#define __REG_VARIANT_(...) __REG_VARIANT__(__VA_ARGS__)
+#define __REG_VARIANT__(name, index, varp, vars) varp##name##vars index
+
+/** BF_OR
+ *
+ * usage: BF_OR(register, f1(v1), f2(v2), ...)
+ *
+ * effect: expands to the register value where each field fi has value vi.
+ *         Informally: reg_f1(v1) | reg_f2(v2) | ...
+ * note: enumerated values for fields can be obtained by using the syntax:
+ *          f1_V(name)
+ *
+ * example: BF_OR(ICOLL_CTRL, SFTRST(1), CLKGATE(0), TZ_LOCK_V(UNLOCKED))
+ */
+#define BF_OR(reg, ...) __VAR_EXPAND(__VAR_OR, BF_##reg##_, __VA_ARGS__)
+
+/** __BFM_OR
+ *
+ * usage: __BFM_OR(register, f1(v1), f2(v2), ...)
+ *
+ * effect: expands to the register value where each field fi has maximum value (vi is ignored).
+ * note: internal usage
+ *
+ * example: __BFM_OR(ICOLL_CTRL, SFTRST(1), CLKGATE(0), TZ_LOCK_V(UNLOCKED))
+ */
+#define __BFM_OR(reg, ...) __VAR_EXPAND(__VAR_OR, BFM_##reg##_, __VA_ARGS__)
+
+/** BM_OR
+ *
+ * usage: BM_OR(register, f1, f2, ...)
+ *
+ * effect: expands to the register value where each field fi is set to its maximum value.
+ *         Informally: reg_f1_mask | reg_f2_mask | ...
+ *
+ * example: BM_OR(ICOLL_CTRL, SFTRST, CLKGATE)
+ */
+#define BM_OR(reg, ...) __VAR_EXPAND(__VAR_OR, BM_##reg##_, __VA_ARGS__)
+
+
+/** REG_RD
+ *
+ * usage: REG_RD(register)
+ *
+ * effect: read a register and return its value
+ * note: register must be fully qualified if indexed
+ *
+ * example: REG_RD(ICOLL_STATUS)
+ *          REG_RD(ICOLL_ENABLE(42))
+ */
+#define REG_RD(name) HWT_##name(RD, name)
+
+/** BF_RDX
+ *
+ * usage: BF_RDX(value, register, field)
+ *
+ * effect: given a register value, return the value of a particular field
+ * note: this macro does NOT read any register
+ *
+ * example: BF_RDX(0xc0000000, ICOLL_CTRL, SFTRST)
+ *          BF_RDX(0x46ff, ICOLL_ENABLE, CPU0_PRIO)
+ */
+#define BF_RDX(val, name, field) (((val) & BM_##name##_##field) >> BP_##name##_##field)
+
+/** BF_RD
+ *
+ * usage: BF_RD(register, field)
+ *
+ * effect: read a register and return the value of a particular field
+ * note: register must be fully qualified if indexed
+ *
+ * example: BF_RD(ICOLL_CTRL, SFTRST)
+ *          BF_RD(ICOLL_ENABLE(3), CPU0_PRIO)
+ */
+#define BF_RD(name, field) BF_RD_(REG_RD(name), HWN_##name, field)
+#define BF_RD_(...) BF_RDX(__VA_ARGS__)
+
+/** REG_WR
+ *
+ * usage: REG_WR(register, value)
+ *
+ * effect: write a register
+ * note: register must be fully qualified if indexed
+ *
+ * example: REG_WR(ICOLL_CTRL, 0x42)
+ *          REG_WR(ICOLL_ENABLE_SET(3), 0x37)
+ */
+#define REG_WR(name, val) HWT_##name(WR, name, val)
+
+/** BF_WR
+ *
+ * usage: BF_WR(register, f1(v1), f2(v2), ...)
+ *
+ * effect: change the register value so that field fi has value vi
+ * note: register must be fully qualified if indexed
+ * note: this macro may perform a read-modify-write
+ *
+ * example: BF_WR(ICOLL_CTRL, SFTRST(1), CLKGATE(0), TZ_LOCK_V(UNLOCKED))
+ *          BF_WR(ICOLL_ENABLE(3), CPU0_PRIO(1), CPU0_TYPE_V(FIQ))
+ */
+#define BF_WR(name, ...) BF_WR_(name, HWN_##name, __VA_ARGS__)
+#define BF_WR_(name, name2, ...) HWT_##name(RMW, name, ~__BFM_OR(name2, __VA_ARGS__), BF_OR(name2, __VA_ARGS__))
+
+/** BF_WR_ALL
+ *
+ * usage: BF_WR_ALL(register, f1(v1), f2(v2), ...)
+ *
+ * effect: change the register value so that field fi has value vi and other fields have value zero
+ *         thus this macro is equivalent to:
+ *         REG_WR(register, BF_OR(register, f1(v1), ...))
+ * note: register must be fully qualified if indexed
+ * note: this macro will overwrite the register (it is NOT a read-modify-write)
+ *
+ * example: BF_WR_ALL(ICOLL_CTRL, SFTRST(1), CLKGATE(0), TZ_LOCK_V(UNLOCKED))
+ *          BF_WR_ALL(ICOLL_ENABLE(3), CPU0_PRIO(1), CPU0_TYPE_V(FIQ))
+ */
+#define BF_WR_ALL(name, ...) BF_WR_ALL_(name, HWN_##name, __VA_ARGS__)
+#define BF_WR_ALL_(name, name2, ...) HWT_##name(WR, name, BF_OR(name2, __VA_ARGS__))
+
+/** BF_WRX
+ *
+ * usage: BF_WRX(var, register, f1(v1), f2(v2), ...)
+ *
+ * effect: change the variable value so that field fi has value vi
+ * note: this macro will perform a read-modify-write
+ *
+ * example: BF_WRX(var, ICOLL_CTRL, SFTRST(1), CLKGATE(0), TZ_LOCK_V(UNLOCKED))
+ *          BF_WRX(var, ICOLL_ENABLE, CPU0_PRIO(1), CPU0_TYPE_V(FIQ))
+ */
+#define BF_WRX(var, name, ...) (var) = BF_OR(name, __VA_ARGS__) | (~__BFM_OR(name, __VA_ARGS__) & (var))
+
+/** BF_SET
+ *
+ * usage: BF_SET(register, f1, f2, ...)
+ *
+ * effect: change the register value so that field fi has maximum value
+ * IMPORTANT: this macro performs a write to the set variant of the register
+ * note: register must be fully qualified if indexed
+ *
+ * example: BF_SET(ICOLL_CTRL, SFTRST, CLKGATE)
+ *          BF_SET(ICOLL_ENABLE(3), CPU0_PRIO, CPU0_TYPE)
+ */
+#define BF_SET(name, ...) BF_SET_(__REG_VARIANT(name, , _SET), HWN_##name, __VA_ARGS__)
+#define BF_SET_(name, name2, ...) REG_WR(name, BM_OR(name2, __VA_ARGS__))
+
+/** BF_CLR
+ *
+ * usage: BF_CLR(register, f1, f2, ...)
+ *
+ * effect: change the register value so that field fi has value zero
+ * IMPORTANT: this macro performs a write to the clr variant of the register
+ * note: register must be fully qualified if indexed
+ *
+ * example: BF_CLR(ICOLL_CTRL, SFTRST, CLKGATE)
+ *          BF_CLR(ICOLL_ENABLE(3), CPU0_PRIO, CPU0_TYPE)
+ */
+#define BF_CLR(name, ...) BF_CLR_(__REG_VARIANT(name, , _CLR), HWN_##name, __VA_ARGS__)
+#define BF_CLR_(name, name2, ...) REG_WR(name, BM_OR(name2, __VA_ARGS__))
+
+/** REG_CS
+ *
+ * usage: REG_CS(register, clear_value, set_value)
+ *
+ * effect: clear some bits using set variant and then set some using set variant
+ * note: register must be fully qualified if indexed
+ *
+ * example: REG_CS(ICOLL_CTRL, 0xff, 0x42)
+ *          REG_CS(ICOLL_ENABLE(3), 0xff, 0x37)
+ */
+#define REG_CS(name, cval, sval) REG_CS_(__REG_VARIANT(name, , _CLR), __REG_VARIANT(name, , _SET), cval, sval)
+#define REG_CS_(cname, sname, cval, sval) do { REG_WR(cname, cval); REG_WR(sname, sval); } while(0)
+
+/** BF_CS
+ *
+ * usage: BF_CS(register, f1(v1), f2(v2), ...)
+ *
+ * effect: change the register value so that field fi has value vi using clr and set variants
+ * note: register must be fully qualified if indexed
+ * note: this macro will NOT perform a read-modify-write and is thus safer
+ * IMPORTANT: this macro will set some fields to 0 temporarily, make sure this is acceptable
+ *
+ * example: BF_CS(ICOLL_CTRL, SFTRST(1), CLKGATE(0), TZ_LOCK_V(UNLOCKED))
+ *          BF_CS(ICOLL_ENABLE(3), CPU0_PRIO(1), CPU0_TYPE_V(FIQ))
+ */
+#define BF_CS(name, ...) BF_CS_(name, HWN_##name, __VA_ARGS__)
+#define BF_CS_(name, name2, ...) REG_CS(name, __BFM_OR(name2, __VA_ARGS__), BF_OR(name2, __VA_ARGS__))
+
+/** HW
+ *
+ * usage: HW(register)
+ *
+ * effect: return a variable-like expression that can be read/written
+ * note: register must be fully qualified if indexed
+ * note: read-only registers will yield a constant expression
+ *
+ * example: unsigned x = HW(ICOLL_STATUS)
+ *          unsigned x = HW(ICOLL_ENABLE(42))
+ *          HW(ICOLL_ENABLE(42)) = 64
+ */
+#define HW(name) HWT_##name(VAR, name)
+
+
+#endif /* __HEADERGEN_MACRO_H__*/
diff --git a/firmware/target/arm/imx233/regs/memcpy.h b/firmware/target/arm/imx233/regs/memcpy.h
new file mode 100644
index 0000000000..2229ca7750
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/memcpy.h
@@ -0,0 +1,33 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_MEMCPY_H__
+#define __HEADERGEN_MEMCPY_H__
+
+#include "macro.h"
+
+#define STMP3600_INCLUDE    "stmp3600/memcpy.h"
+
+#include "select.h"
+
+#undef STMP3600_INCLUDE
+
+#endif /* __HEADERGEN_MEMCPY_H__*/
diff --git a/firmware/target/arm/imx233/regs/ocotp.h b/firmware/target/arm/imx233/regs/ocotp.h
new file mode 100644
index 0000000000..3ef3b5688b
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/ocotp.h
@@ -0,0 +1,35 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_OCOTP_H__
+#define __HEADERGEN_OCOTP_H__
+
+#include "macro.h"
+
+#define STMP3700_INCLUDE    "stmp3700/ocotp.h"
+#define IMX233_INCLUDE      "imx233/ocotp.h"
+
+#include "select.h"
+
+#undef STMP3700_INCLUDE
+#undef IMX233_INCLUDE
+
+#endif /* __HEADERGEN_OCOTP_H__*/
diff --git a/firmware/target/arm/imx233/regs/pinctrl.h b/firmware/target/arm/imx233/regs/pinctrl.h
new file mode 100644
index 0000000000..7af323d6ac
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/pinctrl.h
@@ -0,0 +1,37 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_PINCTRL_H__
+#define __HEADERGEN_PINCTRL_H__
+
+#include "macro.h"
+
+#define STMP3600_INCLUDE    "stmp3600/pinctrl.h"
+#define STMP3700_INCLUDE    "stmp3700/pinctrl.h"
+#define IMX233_INCLUDE      "imx233/pinctrl.h"
+
+#include "select.h"
+
+#undef STMP3600_INCLUDE
+#undef STMP3700_INCLUDE
+#undef IMX233_INCLUDE
+
+#endif /* __HEADERGEN_PINCTRL_H__*/
diff --git a/firmware/target/arm/imx233/regs/power.h b/firmware/target/arm/imx233/regs/power.h
new file mode 100644
index 0000000000..d30cff186c
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/power.h
@@ -0,0 +1,37 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_POWER_H__
+#define __HEADERGEN_POWER_H__
+
+#include "macro.h"
+
+#define STMP3600_INCLUDE    "stmp3600/power.h"
+#define STMP3700_INCLUDE    "stmp3700/power.h"
+#define IMX233_INCLUDE      "imx233/power.h"
+
+#include "select.h"
+
+#undef STMP3600_INCLUDE
+#undef STMP3700_INCLUDE
+#undef IMX233_INCLUDE
+
+#endif /* __HEADERGEN_POWER_H__*/
diff --git a/firmware/target/arm/imx233/regs/pwm.h b/firmware/target/arm/imx233/regs/pwm.h
new file mode 100644
index 0000000000..f77072878f
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/pwm.h
@@ -0,0 +1,37 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_PWM_H__
+#define __HEADERGEN_PWM_H__
+
+#include "macro.h"
+
+#define STMP3600_INCLUDE    "stmp3600/pwm.h"
+#define STMP3700_INCLUDE    "stmp3700/pwm.h"
+#define IMX233_INCLUDE      "imx233/pwm.h"
+
+#include "select.h"
+
+#undef STMP3600_INCLUDE
+#undef STMP3700_INCLUDE
+#undef IMX233_INCLUDE
+
+#endif /* __HEADERGEN_PWM_H__*/
diff --git a/firmware/target/arm/imx233/regs/regs-pxp.h b/firmware/target/arm/imx233/regs/pxp.h
index ff04e32197..f0a0492461 100644
--- a/firmware/target/arm/imx233/regs/regs-pxp.h
+++ b/firmware/target/arm/imx233/regs/pxp.h
@@ -6,10 +6,9 @@
  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
  *                     \/            \/     \/    \/            \/
  * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: imx233:3.2.0
+ * headergen version: 3.0.0
  *
- * Copyright (C) 2013 by Amaury Pouly
+ * Copyright (C) 2015 by the authors
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
@@ -20,14 +19,15 @@
  * KIND, either express or implied.
  *
  ****************************************************************************/
-#ifndef __SELECT__PXP__H__
-#define __SELECT__PXP__H__
-#include "regs-macro.h"
+#ifndef __HEADERGEN_PXP_H__
+#define __HEADERGEN_PXP_H__
 
-#define IMX233_INCLUDE "imx233/regs-pxp.h"
+#include "macro.h"
 
-#include "regs-select.h"
+#define IMX233_INCLUDE  "imx233/pxp.h"
+
+#include "select.h"
 
 #undef IMX233_INCLUDE
 
-#endif /* __SELECT__PXP__H__ */
+#endif /* __HEADERGEN_PXP_H__*/
diff --git a/firmware/target/arm/imx233/regs/regs-apbh.h b/firmware/target/arm/imx233/regs/regs-apbh.h
deleted file mode 100644
index afc12bd351..0000000000
--- a/firmware/target/arm/imx233/regs/regs-apbh.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3600:2.4.0 stmp3700:3.2.0 imx233:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __SELECT__APBH__H__
-#define __SELECT__APBH__H__
-#include "regs-macro.h"
-
-#define STMP3600_INCLUDE "stmp3600/regs-apbh.h"
-#define STMP3700_INCLUDE "stmp3700/regs-apbh.h"
-#define IMX233_INCLUDE "imx233/regs-apbh.h"
-
-#include "regs-select.h"
-
-#undef STMP3600_INCLUDE
-#undef STMP3700_INCLUDE
-#undef IMX233_INCLUDE
-
-#endif /* __SELECT__APBH__H__ */
diff --git a/firmware/target/arm/imx233/regs/regs-apbx.h b/firmware/target/arm/imx233/regs/regs-apbx.h
deleted file mode 100644
index 4118eb07da..0000000000
--- a/firmware/target/arm/imx233/regs/regs-apbx.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3600:2.4.0 stmp3700:3.2.0 imx233:3.2.1
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __SELECT__APBX__H__
-#define __SELECT__APBX__H__
-#include "regs-macro.h"
-
-#define STMP3600_INCLUDE "stmp3600/regs-apbx.h"
-#define STMP3700_INCLUDE "stmp3700/regs-apbx.h"
-#define IMX233_INCLUDE "imx233/regs-apbx.h"
-
-#include "regs-select.h"
-
-#undef STMP3600_INCLUDE
-#undef STMP3700_INCLUDE
-#undef IMX233_INCLUDE
-
-#endif /* __SELECT__APBX__H__ */
diff --git a/firmware/target/arm/imx233/regs/regs-audioin.h b/firmware/target/arm/imx233/regs/regs-audioin.h
deleted file mode 100644
index b1c9df11ff..0000000000
--- a/firmware/target/arm/imx233/regs/regs-audioin.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3600:2.5.0 stmp3700:3.4.0 imx233:3.4.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __SELECT__AUDIOIN__H__
-#define __SELECT__AUDIOIN__H__
-#include "regs-macro.h"
-
-#define STMP3600_INCLUDE "stmp3600/regs-audioin.h"
-#define STMP3700_INCLUDE "stmp3700/regs-audioin.h"
-#define IMX233_INCLUDE "imx233/regs-audioin.h"
-
-#include "regs-select.h"
-
-#undef STMP3600_INCLUDE
-#undef STMP3700_INCLUDE
-#undef IMX233_INCLUDE
-
-#endif /* __SELECT__AUDIOIN__H__ */
diff --git a/firmware/target/arm/imx233/regs/regs-audioout.h b/firmware/target/arm/imx233/regs/regs-audioout.h
deleted file mode 100644
index 995a9fd0b4..0000000000
--- a/firmware/target/arm/imx233/regs/regs-audioout.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3600:2.3.0 stmp3700:3.2.0 imx233:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __SELECT__AUDIOOUT__H__
-#define __SELECT__AUDIOOUT__H__
-#include "regs-macro.h"
-
-#define STMP3600_INCLUDE "stmp3600/regs-audioout.h"
-#define STMP3700_INCLUDE "stmp3700/regs-audioout.h"
-#define IMX233_INCLUDE "imx233/regs-audioout.h"
-
-#include "regs-select.h"
-
-#undef STMP3600_INCLUDE
-#undef STMP3700_INCLUDE
-#undef IMX233_INCLUDE
-
-#endif /* __SELECT__AUDIOOUT__H__ */
diff --git a/firmware/target/arm/imx233/regs/regs-brazoiocsr.h b/firmware/target/arm/imx233/regs/regs-brazoiocsr.h
deleted file mode 100644
index 1b3af34340..0000000000
--- a/firmware/target/arm/imx233/regs/regs-brazoiocsr.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3600:2.3.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __SELECT__BRAZOIOCSR__H__
-#define __SELECT__BRAZOIOCSR__H__
-#include "regs-macro.h"
-
-#define STMP3600_INCLUDE "stmp3600/regs-brazoiocsr.h"
-
-#include "regs-select.h"
-
-#undef STMP3600_INCLUDE
-
-#endif /* __SELECT__BRAZOIOCSR__H__ */
diff --git a/firmware/target/arm/imx233/regs/regs-clkctrl.h b/firmware/target/arm/imx233/regs/regs-clkctrl.h
deleted file mode 100644
index dbc3a2e4dd..0000000000
--- a/firmware/target/arm/imx233/regs/regs-clkctrl.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3600:2.4.0 stmp3700:3.2.0 imx233:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __SELECT__CLKCTRL__H__
-#define __SELECT__CLKCTRL__H__
-#include "regs-macro.h"
-
-#define STMP3600_INCLUDE "stmp3600/regs-clkctrl.h"
-#define STMP3700_INCLUDE "stmp3700/regs-clkctrl.h"
-#define IMX233_INCLUDE "imx233/regs-clkctrl.h"
-
-#include "regs-select.h"
-
-#undef STMP3600_INCLUDE
-#undef STMP3700_INCLUDE
-#undef IMX233_INCLUDE
-
-#endif /* __SELECT__CLKCTRL__H__ */
diff --git a/firmware/target/arm/imx233/regs/regs-digctl.h b/firmware/target/arm/imx233/regs/regs-digctl.h
deleted file mode 100644
index d5474b2623..0000000000
--- a/firmware/target/arm/imx233/regs/regs-digctl.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3600:2.3.0 stmp3700:3.2.0 imx233:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __SELECT__DIGCTL__H__
-#define __SELECT__DIGCTL__H__
-#include "regs-macro.h"
-
-#define STMP3600_INCLUDE "stmp3600/regs-digctl.h"
-#define STMP3700_INCLUDE "stmp3700/regs-digctl.h"
-#define IMX233_INCLUDE "imx233/regs-digctl.h"
-
-#include "regs-select.h"
-
-#undef STMP3600_INCLUDE
-#undef STMP3700_INCLUDE
-#undef IMX233_INCLUDE
-
-#endif /* __SELECT__DIGCTL__H__ */
diff --git a/firmware/target/arm/imx233/regs/regs-dri.h b/firmware/target/arm/imx233/regs/regs-dri.h
deleted file mode 100644
index e7e6450507..0000000000
--- a/firmware/target/arm/imx233/regs/regs-dri.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3600:2.3.0 stmp3700:3.2.0 imx233:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __SELECT__DRI__H__
-#define __SELECT__DRI__H__
-#include "regs-macro.h"
-
-#define STMP3600_INCLUDE "stmp3600/regs-dri.h"
-#define STMP3700_INCLUDE "stmp3700/regs-dri.h"
-#define IMX233_INCLUDE "imx233/regs-dri.h"
-
-#include "regs-select.h"
-
-#undef STMP3600_INCLUDE
-#undef STMP3700_INCLUDE
-#undef IMX233_INCLUDE
-
-#endif /* __SELECT__DRI__H__ */
diff --git a/firmware/target/arm/imx233/regs/regs-emi.h b/firmware/target/arm/imx233/regs/regs-emi.h
deleted file mode 100644
index 80829e0d43..0000000000
--- a/firmware/target/arm/imx233/regs/regs-emi.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3600:2.4.0 stmp3700:3.2.0 imx233:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __SELECT__EMI__H__
-#define __SELECT__EMI__H__
-#include "regs-macro.h"
-
-#define STMP3600_INCLUDE "stmp3600/regs-emi.h"
-#define STMP3700_INCLUDE "stmp3700/regs-emi.h"
-#define IMX233_INCLUDE "imx233/regs-emi.h"
-
-#include "regs-select.h"
-
-#undef STMP3600_INCLUDE
-#undef STMP3700_INCLUDE
-#undef IMX233_INCLUDE
-
-#endif /* __SELECT__EMI__H__ */
diff --git a/firmware/target/arm/imx233/regs/regs-gpmi.h b/firmware/target/arm/imx233/regs/regs-gpmi.h
deleted file mode 100644
index e0d5e2ab51..0000000000
--- a/firmware/target/arm/imx233/regs/regs-gpmi.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3600:2.3.0 stmp3700:3.2.0 imx233:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __SELECT__GPMI__H__
-#define __SELECT__GPMI__H__
-#include "regs-macro.h"
-
-#define STMP3600_INCLUDE "stmp3600/regs-gpmi.h"
-#define STMP3700_INCLUDE "stmp3700/regs-gpmi.h"
-#define IMX233_INCLUDE "imx233/regs-gpmi.h"
-
-#include "regs-select.h"
-
-#undef STMP3600_INCLUDE
-#undef STMP3700_INCLUDE
-#undef IMX233_INCLUDE
-
-#endif /* __SELECT__GPMI__H__ */
diff --git a/firmware/target/arm/imx233/regs/regs-i2c.h b/firmware/target/arm/imx233/regs/regs-i2c.h
deleted file mode 100644
index cc75912352..0000000000
--- a/firmware/target/arm/imx233/regs/regs-i2c.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3600:2.3.0 stmp3700:3.2.0 imx233:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __SELECT__I2C__H__
-#define __SELECT__I2C__H__
-#include "regs-macro.h"
-
-#define STMP3600_INCLUDE "stmp3600/regs-i2c.h"
-#define STMP3700_INCLUDE "stmp3700/regs-i2c.h"
-#define IMX233_INCLUDE "imx233/regs-i2c.h"
-
-#include "regs-select.h"
-
-#undef STMP3600_INCLUDE
-#undef STMP3700_INCLUDE
-#undef IMX233_INCLUDE
-
-#endif /* __SELECT__I2C__H__ */
diff --git a/firmware/target/arm/imx233/regs/regs-icoll.h b/firmware/target/arm/imx233/regs/regs-icoll.h
deleted file mode 100644
index 0b31594ab5..0000000000
--- a/firmware/target/arm/imx233/regs/regs-icoll.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3600:2.3.0 stmp3700:3.2.0 imx233:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __SELECT__ICOLL__H__
-#define __SELECT__ICOLL__H__
-#include "regs-macro.h"
-
-#define STMP3600_INCLUDE "stmp3600/regs-icoll.h"
-#define STMP3700_INCLUDE "stmp3700/regs-icoll.h"
-#define IMX233_INCLUDE "imx233/regs-icoll.h"
-
-#include "regs-select.h"
-
-#undef STMP3600_INCLUDE
-#undef STMP3700_INCLUDE
-#undef IMX233_INCLUDE
-
-#endif /* __SELECT__ICOLL__H__ */
diff --git a/firmware/target/arm/imx233/regs/regs-ir.h b/firmware/target/arm/imx233/regs/regs-ir.h
deleted file mode 100644
index 422fb7abb3..0000000000
--- a/firmware/target/arm/imx233/regs/regs-ir.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3600:2.3.0 stmp3700:3.2.0 imx233:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __SELECT__IR__H__
-#define __SELECT__IR__H__
-#include "regs-macro.h"
-
-#define STMP3600_INCLUDE "stmp3600/regs-ir.h"
-#define STMP3700_INCLUDE "stmp3700/regs-ir.h"
-#define IMX233_INCLUDE "imx233/regs-ir.h"
-
-#include "regs-select.h"
-
-#undef STMP3600_INCLUDE
-#undef STMP3700_INCLUDE
-#undef IMX233_INCLUDE
-
-#endif /* __SELECT__IR__H__ */
diff --git a/firmware/target/arm/imx233/regs/regs-lcdif.h b/firmware/target/arm/imx233/regs/regs-lcdif.h
deleted file mode 100644
index be347eeaa6..0000000000
--- a/firmware/target/arm/imx233/regs/regs-lcdif.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3600:2.3.0 stmp3700:3.2.0 imx233:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __SELECT__LCDIF__H__
-#define __SELECT__LCDIF__H__
-#include "regs-macro.h"
-
-#define STMP3600_INCLUDE "stmp3600/regs-lcdif.h"
-#define STMP3700_INCLUDE "stmp3700/regs-lcdif.h"
-#define IMX233_INCLUDE "imx233/regs-lcdif.h"
-
-#include "regs-select.h"
-
-#undef STMP3600_INCLUDE
-#undef STMP3700_INCLUDE
-#undef IMX233_INCLUDE
-
-#endif /* __SELECT__LCDIF__H__ */
diff --git a/firmware/target/arm/imx233/regs/regs-lradc.h b/firmware/target/arm/imx233/regs/regs-lradc.h
deleted file mode 100644
index 495ff14455..0000000000
--- a/firmware/target/arm/imx233/regs/regs-lradc.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3600:2.3.0 stmp3700:3.2.0 imx233:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __SELECT__LRADC__H__
-#define __SELECT__LRADC__H__
-#include "regs-macro.h"
-
-#define STMP3600_INCLUDE "stmp3600/regs-lradc.h"
-#define STMP3700_INCLUDE "stmp3700/regs-lradc.h"
-#define IMX233_INCLUDE "imx233/regs-lradc.h"
-
-#include "regs-select.h"
-
-#undef STMP3600_INCLUDE
-#undef STMP3700_INCLUDE
-#undef IMX233_INCLUDE
-
-#endif /* __SELECT__LRADC__H__ */
diff --git a/firmware/target/arm/imx233/regs/regs-macro.h b/firmware/target/arm/imx233/regs/regs-macro.h
deleted file mode 100644
index 971ebb514d..0000000000
--- a/firmware/target/arm/imx233/regs/regs-macro.h
+++ /dev/null
@@ -1,496 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __REGS__MACRO__H__
-#define __REGS__MACRO__H__
-
-#ifndef REG_WRITE
-#define REG_WRITE(var,value) ((var) = (value))
-#endif /* REG_WRITE */
-
-#ifndef REG_READ
-#define REG_READ(var) (var)
-#endif /* REG_READ */
-
-#define BF_SET(reg, field)              REG_WRITE(HW_##reg##_SET, BM_##reg##_##field)
-#define BF_CLR(reg, field)              REG_WRITE(HW_##reg##_CLR, BM_##reg##_##field)
-#define BF_TOG(reg, field)              REG_WRITE(HW_##reg##_TOG, BM_##reg##_##field)
-
-#define BF_SETV(reg, field, v)          REG_WRITE(HW_##reg##_SET, BF_##reg##_##field(v))
-#define BF_CLRV(reg, field, v)          REG_WRITE(HW_##reg##_CLR, BF_##reg##_##field(v))
-#define BF_TOGV(reg, field, v)          REG_WRITE(HW_##reg##_TOG, BF_##reg##_##field(v))
-
-#define BF_RDX(val, reg, field)         ((REG_READ(val) & BM_##reg##_##field) >> BP_##reg##_##field)
-#define BF_RD(reg, field)               BF_RDX(REG_READ(HW_##reg), reg, field)
-#define BF_WRX(val, reg, field, v)      REG_WRITE(val, (REG_READ(val) & ~BM_##reg##_##field) | (((v) << BP_##reg##_##field) & BM_##reg##_##field))
-#define BF_WR(reg, field, v)            BF_WRX(HW_##reg, reg, field, v)
-#define BF_WR_V(reg, field, sy)         BF_WR(reg, field, BV_##reg##_##field##__##sy)
-#define BF_WR_VX(val, reg, field, sy)   BF_WRX(val, reg, field, BV_##reg##_##field##__##sy)
-
-#define BF_SETn(reg, n, field)          REG_WRITE(HW_##reg##_SET(n), BM_##reg##_##field)
-#define BF_CLRn(reg, n, field)          REG_WRITE(HW_##reg##_CLR(n), BM_##reg##_##field)
-#define BF_TOGn(reg, n, field)          REG_WRITE(HW_##reg##_TOG(n), BM_##reg##_##field)
-
-#define BF_SETVn(reg, n, field, v)      REG_WRITE(HW_##reg##_SET(n), BF_##reg##_##field(v))
-#define BF_CLRVn(reg, n, field, v)      REG_WRITE(HW_##reg##_CLR(n), BF_##reg##_##field(v))
-#define BF_TOGVn(reg, n, field, v)      REG_WRITE(HW_##reg##_TOG(n), BF_##reg##_##field(v))
-
-#define BF_RDn(reg, n, field)           BF_RDX(HW_##reg(n), reg, field)
-#define BF_WRn(reg, n, field, v)        BF_WRX(HW_##reg(n), reg, field, v)
-#define BF_WRn_V(reg, n, field, sy)     BF_WRn(reg, n, field, BV_##reg##_##field##__##sy)
-
-#define BM_OR1(reg, f01) \
-    (BM_##reg##_##f01)
-#define BM_OR2(reg, f01, f02) \
-    (BM_##reg##_##f01 | BM_##reg##_##f02)
-#define BM_OR3(reg, f01, f02, f03) \
-    (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03)
-#define BM_OR4(reg, f01, f02, f03, f04) \
-    (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04)
-#define BM_OR5(reg, f01, f02, f03, f04, f05) \
-    (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \
-     BM_##reg##_##f05)
-#define BM_OR6(reg, f01, f02, f03, f04, f05, f06) \
-    (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \
-     BM_##reg##_##f05 | BM_##reg##_##f06)
-#define BM_OR7(reg, f01, f02, f03, f04, f05, f06, f07) \
-    (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \
-     BM_##reg##_##f05 | BM_##reg##_##f06 | BM_##reg##_##f07)
-#define BM_OR8(reg, f01, f02, f03, f04, f05, f06, f07, f08) \
-    (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \
-     BM_##reg##_##f05 | BM_##reg##_##f06 | BM_##reg##_##f07 | BM_##reg##_##f08)
-#define BM_OR9(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09) \
-    (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \
-     BM_##reg##_##f05 | BM_##reg##_##f06 | BM_##reg##_##f07 | BM_##reg##_##f08 | \
-     BM_##reg##_##f09)
-#define BM_OR10(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10) \
-    (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \
-     BM_##reg##_##f05 | BM_##reg##_##f06 | BM_##reg##_##f07 | BM_##reg##_##f08 | \
-     BM_##reg##_##f09 | BM_##reg##_##f10)
-#define BM_OR11(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
-        f11) \
-    (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \
-     BM_##reg##_##f05 | BM_##reg##_##f06 | BM_##reg##_##f07 | BM_##reg##_##f08 | \
-     BM_##reg##_##f09 | BM_##reg##_##f10 | BM_##reg##_##f11)
-#define BM_OR12(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
-        f11, f12) \
-    (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \
-     BM_##reg##_##f05 | BM_##reg##_##f06 | BM_##reg##_##f07 | BM_##reg##_##f08 | \
-     BM_##reg##_##f09 | BM_##reg##_##f10 | BM_##reg##_##f11 | BM_##reg##_##f12)
-#define BM_OR13(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
-        f11, f12, f13) \
-    (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \
-     BM_##reg##_##f05 | BM_##reg##_##f06 | BM_##reg##_##f07 | BM_##reg##_##f08 | \
-     BM_##reg##_##f09 | BM_##reg##_##f10 | BM_##reg##_##f11 | BM_##reg##_##f12 | \
-     BM_##reg##_##f13)
-#define BM_OR14(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
-        f11, f12, f13, f14) \
-    (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \
-     BM_##reg##_##f05 | BM_##reg##_##f06 | BM_##reg##_##f07 | BM_##reg##_##f08 | \
-     BM_##reg##_##f09 | BM_##reg##_##f10 | BM_##reg##_##f11 | BM_##reg##_##f12 | \
-     BM_##reg##_##f13 | BM_##reg##_##f14)
-#define BM_OR15(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
-        f11, f12, f13, f14, f15) \
-    (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \
-     BM_##reg##_##f05 | BM_##reg##_##f06 | BM_##reg##_##f07 | BM_##reg##_##f08 | \
-     BM_##reg##_##f09 | BM_##reg##_##f10 | BM_##reg##_##f11 | BM_##reg##_##f12 | \
-     BM_##reg##_##f13 | BM_##reg##_##f14 | BM_##reg##_##f15)
-#define BM_OR16(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
-        f11, f12, f13, f14, f15, f16) \
-    (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \
-     BM_##reg##_##f05 | BM_##reg##_##f06 | BM_##reg##_##f07 | BM_##reg##_##f08 | \
-     BM_##reg##_##f09 | BM_##reg##_##f10 | BM_##reg##_##f11 | BM_##reg##_##f12 | \
-     BM_##reg##_##f13 | BM_##reg##_##f14 | BM_##reg##_##f15 | BM_##reg##_##f16)
-#define BM_OR17(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
-        f11, f12, f13, f14, f15, f16, f17) \
-    (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \
-     BM_##reg##_##f05 | BM_##reg##_##f06 | BM_##reg##_##f07 | BM_##reg##_##f08 | \
-     BM_##reg##_##f09 | BM_##reg##_##f10 | BM_##reg##_##f11 | BM_##reg##_##f12 | \
-     BM_##reg##_##f13 | BM_##reg##_##f14 | BM_##reg##_##f15 | BM_##reg##_##f16 | \
-     BM_##reg##_##f17)
-#define BM_OR18(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
-        f11, f12, f13, f14, f15, f16, f17, f18) \
-    (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \
-     BM_##reg##_##f05 | BM_##reg##_##f06 | BM_##reg##_##f07 | BM_##reg##_##f08 | \
-     BM_##reg##_##f09 | BM_##reg##_##f10 | BM_##reg##_##f11 | BM_##reg##_##f12 | \
-     BM_##reg##_##f13 | BM_##reg##_##f14 | BM_##reg##_##f15 | BM_##reg##_##f16 | \
-     BM_##reg##_##f17 | BM_##reg##_##f18)
-#define BM_OR19(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
-        f11, f12, f13, f14, f15, f16, f17, f18, f19) \
-    (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \
-     BM_##reg##_##f05 | BM_##reg##_##f06 | BM_##reg##_##f07 | BM_##reg##_##f08 | \
-     BM_##reg##_##f09 | BM_##reg##_##f10 | BM_##reg##_##f11 | BM_##reg##_##f12 | \
-     BM_##reg##_##f13 | BM_##reg##_##f14 | BM_##reg##_##f15 | BM_##reg##_##f16 | \
-     BM_##reg##_##f17 | BM_##reg##_##f18 | BM_##reg##_##f19)
-#define BM_OR20(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
-        f11, f12, f13, f14, f15, f16, f17, f18, f19, f20) \
-    (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \
-     BM_##reg##_##f05 | BM_##reg##_##f06 | BM_##reg##_##f07 | BM_##reg##_##f08 | \
-     BM_##reg##_##f09 | BM_##reg##_##f10 | BM_##reg##_##f11 | BM_##reg##_##f12 | \
-     BM_##reg##_##f13 | BM_##reg##_##f14 | BM_##reg##_##f15 | BM_##reg##_##f16 | \
-     BM_##reg##_##f17 | BM_##reg##_##f18 | BM_##reg##_##f19 | BM_##reg##_##f20)
-#define BM_OR21(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
-        f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, \
-        f21) \
-    (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \
-     BM_##reg##_##f05 | BM_##reg##_##f06 | BM_##reg##_##f07 | BM_##reg##_##f08 | \
-     BM_##reg##_##f09 | BM_##reg##_##f10 | BM_##reg##_##f11 | BM_##reg##_##f12 | \
-     BM_##reg##_##f13 | BM_##reg##_##f14 | BM_##reg##_##f15 | BM_##reg##_##f16 | \
-     BM_##reg##_##f17 | BM_##reg##_##f18 | BM_##reg##_##f19 | BM_##reg##_##f20 | \
-     BM_##reg##_##f21)
-#define BM_OR22(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
-        f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, \
-        f21, f22) \
-    (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \
-     BM_##reg##_##f05 | BM_##reg##_##f06 | BM_##reg##_##f07 | BM_##reg##_##f08 | \
-     BM_##reg##_##f09 | BM_##reg##_##f10 | BM_##reg##_##f11 | BM_##reg##_##f12 | \
-     BM_##reg##_##f13 | BM_##reg##_##f14 | BM_##reg##_##f15 | BM_##reg##_##f16 | \
-     BM_##reg##_##f17 | BM_##reg##_##f18 | BM_##reg##_##f19 | BM_##reg##_##f20 | \
-     BM_##reg##_##f21 | BM_##reg##_##f22)
-#define BM_OR23(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
-        f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, \
-        f21, f22, f23) \
-    (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \
-     BM_##reg##_##f05 | BM_##reg##_##f06 | BM_##reg##_##f07 | BM_##reg##_##f08 | \
-     BM_##reg##_##f09 | BM_##reg##_##f10 | BM_##reg##_##f11 | BM_##reg##_##f12 | \
-     BM_##reg##_##f13 | BM_##reg##_##f14 | BM_##reg##_##f15 | BM_##reg##_##f16 | \
-     BM_##reg##_##f17 | BM_##reg##_##f18 | BM_##reg##_##f19 | BM_##reg##_##f20 | \
-     BM_##reg##_##f21 | BM_##reg##_##f22 | BM_##reg##_##f23)
-#define BM_OR24(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
-        f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, \
-        f21, f22, f23, f24) \
-    (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \
-     BM_##reg##_##f05 | BM_##reg##_##f06 | BM_##reg##_##f07 | BM_##reg##_##f08 | \
-     BM_##reg##_##f09 | BM_##reg##_##f10 | BM_##reg##_##f11 | BM_##reg##_##f12 | \
-     BM_##reg##_##f13 | BM_##reg##_##f14 | BM_##reg##_##f15 | BM_##reg##_##f16 | \
-     BM_##reg##_##f17 | BM_##reg##_##f18 | BM_##reg##_##f19 | BM_##reg##_##f20 | \
-     BM_##reg##_##f21 | BM_##reg##_##f22 | BM_##reg##_##f23 | BM_##reg##_##f24)
-#define BM_OR25(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
-        f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, \
-        f21, f22, f23, f24, f25) \
-    (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \
-     BM_##reg##_##f05 | BM_##reg##_##f06 | BM_##reg##_##f07 | BM_##reg##_##f08 | \
-     BM_##reg##_##f09 | BM_##reg##_##f10 | BM_##reg##_##f11 | BM_##reg##_##f12 | \
-     BM_##reg##_##f13 | BM_##reg##_##f14 | BM_##reg##_##f15 | BM_##reg##_##f16 | \
-     BM_##reg##_##f17 | BM_##reg##_##f18 | BM_##reg##_##f19 | BM_##reg##_##f20 | \
-     BM_##reg##_##f21 | BM_##reg##_##f22 | BM_##reg##_##f23 | BM_##reg##_##f24 | \
-     BM_##reg##_##f25)
-#define BM_OR26(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
-        f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, \
-        f21, f22, f23, f24, f25, f26) \
-    (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \
-     BM_##reg##_##f05 | BM_##reg##_##f06 | BM_##reg##_##f07 | BM_##reg##_##f08 | \
-     BM_##reg##_##f09 | BM_##reg##_##f10 | BM_##reg##_##f11 | BM_##reg##_##f12 | \
-     BM_##reg##_##f13 | BM_##reg##_##f14 | BM_##reg##_##f15 | BM_##reg##_##f16 | \
-     BM_##reg##_##f17 | BM_##reg##_##f18 | BM_##reg##_##f19 | BM_##reg##_##f20 | \
-     BM_##reg##_##f21 | BM_##reg##_##f22 | BM_##reg##_##f23 | BM_##reg##_##f24 | \
-     BM_##reg##_##f25 | BM_##reg##_##f26)
-#define BM_OR27(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
-        f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, \
-        f21, f22, f23, f24, f25, f26, f27) \
-    (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \
-     BM_##reg##_##f05 | BM_##reg##_##f06 | BM_##reg##_##f07 | BM_##reg##_##f08 | \
-     BM_##reg##_##f09 | BM_##reg##_##f10 | BM_##reg##_##f11 | BM_##reg##_##f12 | \
-     BM_##reg##_##f13 | BM_##reg##_##f14 | BM_##reg##_##f15 | BM_##reg##_##f16 | \
-     BM_##reg##_##f17 | BM_##reg##_##f18 | BM_##reg##_##f19 | BM_##reg##_##f20 | \
-     BM_##reg##_##f21 | BM_##reg##_##f22 | BM_##reg##_##f23 | BM_##reg##_##f24 | \
-     BM_##reg##_##f25 | BM_##reg##_##f26 | BM_##reg##_##f27)
-#define BM_OR28(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
-        f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, \
-        f21, f22, f23, f24, f25, f26, f27, f28) \
-    (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \
-     BM_##reg##_##f05 | BM_##reg##_##f06 | BM_##reg##_##f07 | BM_##reg##_##f08 | \
-     BM_##reg##_##f09 | BM_##reg##_##f10 | BM_##reg##_##f11 | BM_##reg##_##f12 | \
-     BM_##reg##_##f13 | BM_##reg##_##f14 | BM_##reg##_##f15 | BM_##reg##_##f16 | \
-     BM_##reg##_##f17 | BM_##reg##_##f18 | BM_##reg##_##f19 | BM_##reg##_##f20 | \
-     BM_##reg##_##f21 | BM_##reg##_##f22 | BM_##reg##_##f23 | BM_##reg##_##f24 | \
-     BM_##reg##_##f25 | BM_##reg##_##f26 | BM_##reg##_##f27 | BM_##reg##_##f28)
-#define BM_OR29(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
-        f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, \
-        f21, f22, f23, f24, f25, f26, f27, f28, f29) \
-    (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \
-     BM_##reg##_##f05 | BM_##reg##_##f06 | BM_##reg##_##f07 | BM_##reg##_##f08 | \
-     BM_##reg##_##f09 | BM_##reg##_##f10 | BM_##reg##_##f11 | BM_##reg##_##f12 | \
-     BM_##reg##_##f13 | BM_##reg##_##f14 | BM_##reg##_##f15 | BM_##reg##_##f16 | \
-     BM_##reg##_##f17 | BM_##reg##_##f18 | BM_##reg##_##f19 | BM_##reg##_##f20 | \
-     BM_##reg##_##f21 | BM_##reg##_##f22 | BM_##reg##_##f23 | BM_##reg##_##f24 | \
-     BM_##reg##_##f25 | BM_##reg##_##f26 | BM_##reg##_##f27 | BM_##reg##_##f28 | \
-     BM_##reg##_##f29)
-#define BM_OR30(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
-        f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, \
-        f21, f22, f23, f24, f25, f26, f27, f28, f29, f30) \
-    (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \
-     BM_##reg##_##f05 | BM_##reg##_##f06 | BM_##reg##_##f07 | BM_##reg##_##f08 | \
-     BM_##reg##_##f09 | BM_##reg##_##f10 | BM_##reg##_##f11 | BM_##reg##_##f12 | \
-     BM_##reg##_##f13 | BM_##reg##_##f14 | BM_##reg##_##f15 | BM_##reg##_##f16 | \
-     BM_##reg##_##f17 | BM_##reg##_##f18 | BM_##reg##_##f19 | BM_##reg##_##f20 | \
-     BM_##reg##_##f21 | BM_##reg##_##f22 | BM_##reg##_##f23 | BM_##reg##_##f24 | \
-     BM_##reg##_##f25 | BM_##reg##_##f26 | BM_##reg##_##f27 | BM_##reg##_##f28 | \
-     BM_##reg##_##f29 | BM_##reg##_##f30)
-#define BM_OR31(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
-        f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, \
-        f21, f22, f23, f24, f25, f26, f27, f28, f29, f30, \
-        f31) \
-    (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \
-     BM_##reg##_##f05 | BM_##reg##_##f06 | BM_##reg##_##f07 | BM_##reg##_##f08 | \
-     BM_##reg##_##f09 | BM_##reg##_##f10 | BM_##reg##_##f11 | BM_##reg##_##f12 | \
-     BM_##reg##_##f13 | BM_##reg##_##f14 | BM_##reg##_##f15 | BM_##reg##_##f16 | \
-     BM_##reg##_##f17 | BM_##reg##_##f18 | BM_##reg##_##f19 | BM_##reg##_##f20 | \
-     BM_##reg##_##f21 | BM_##reg##_##f22 | BM_##reg##_##f23 | BM_##reg##_##f24 | \
-     BM_##reg##_##f25 | BM_##reg##_##f26 | BM_##reg##_##f27 | BM_##reg##_##f28 | \
-     BM_##reg##_##f29 | BM_##reg##_##f30 | BM_##reg##_##f31)
-#define BM_OR32(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
-        f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, \
-        f21, f22, f23, f24, f25, f26, f27, f28, f29, f30, \
-        f31, f32) \
-    (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \
-     BM_##reg##_##f05 | BM_##reg##_##f06 | BM_##reg##_##f07 | BM_##reg##_##f08 | \
-     BM_##reg##_##f09 | BM_##reg##_##f10 | BM_##reg##_##f11 | BM_##reg##_##f12 | \
-     BM_##reg##_##f13 | BM_##reg##_##f14 | BM_##reg##_##f15 | BM_##reg##_##f16 | \
-     BM_##reg##_##f17 | BM_##reg##_##f18 | BM_##reg##_##f19 | BM_##reg##_##f20 | \
-     BM_##reg##_##f21 | BM_##reg##_##f22 | BM_##reg##_##f23 | BM_##reg##_##f24 | \
-     BM_##reg##_##f25 | BM_##reg##_##f26 | BM_##reg##_##f27 | BM_##reg##_##f28 | \
-     BM_##reg##_##f29 | BM_##reg##_##f30 | BM_##reg##_##f31 | BM_##reg##_##f32)
-
-#define BF_OR1(reg, f01) \
-    (BF_##reg##_##f01)
-#define BF_OR2(reg, f01, f02) \
-    (BF_##reg##_##f01 | BF_##reg##_##f02)
-#define BF_OR3(reg, f01, f02, f03) \
-    (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03)
-#define BF_OR4(reg, f01, f02, f03, f04) \
-    (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04)
-#define BF_OR5(reg, f01, f02, f03, f04, f05) \
-    (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \
-     BF_##reg##_##f05)
-#define BF_OR6(reg, f01, f02, f03, f04, f05, f06) \
-    (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \
-     BF_##reg##_##f05 | BF_##reg##_##f06)
-#define BF_OR7(reg, f01, f02, f03, f04, f05, f06, f07) \
-    (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \
-     BF_##reg##_##f05 | BF_##reg##_##f06 | BF_##reg##_##f07)
-#define BF_OR8(reg, f01, f02, f03, f04, f05, f06, f07, f08) \
-    (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \
-     BF_##reg##_##f05 | BF_##reg##_##f06 | BF_##reg##_##f07 | BF_##reg##_##f08)
-#define BF_OR9(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09) \
-    (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \
-     BF_##reg##_##f05 | BF_##reg##_##f06 | BF_##reg##_##f07 | BF_##reg##_##f08 | \
-     BF_##reg##_##f09)
-#define BF_OR10(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10) \
-    (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \
-     BF_##reg##_##f05 | BF_##reg##_##f06 | BF_##reg##_##f07 | BF_##reg##_##f08 | \
-     BF_##reg##_##f09 | BF_##reg##_##f10)
-#define BF_OR11(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
-        f11) \
-    (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \
-     BF_##reg##_##f05 | BF_##reg##_##f06 | BF_##reg##_##f07 | BF_##reg##_##f08 | \
-     BF_##reg##_##f09 | BF_##reg##_##f10 | BF_##reg##_##f11)
-#define BF_OR12(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
-        f11, f12) \
-    (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \
-     BF_##reg##_##f05 | BF_##reg##_##f06 | BF_##reg##_##f07 | BF_##reg##_##f08 | \
-     BF_##reg##_##f09 | BF_##reg##_##f10 | BF_##reg##_##f11 | BF_##reg##_##f12)
-#define BF_OR13(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
-        f11, f12, f13) \
-    (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \
-     BF_##reg##_##f05 | BF_##reg##_##f06 | BF_##reg##_##f07 | BF_##reg##_##f08 | \
-     BF_##reg##_##f09 | BF_##reg##_##f10 | BF_##reg##_##f11 | BF_##reg##_##f12 | \
-     BF_##reg##_##f13)
-#define BF_OR14(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
-        f11, f12, f13, f14) \
-    (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \
-     BF_##reg##_##f05 | BF_##reg##_##f06 | BF_##reg##_##f07 | BF_##reg##_##f08 | \
-     BF_##reg##_##f09 | BF_##reg##_##f10 | BF_##reg##_##f11 | BF_##reg##_##f12 | \
-     BF_##reg##_##f13 | BF_##reg##_##f14)
-#define BF_OR15(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
-        f11, f12, f13, f14, f15) \
-    (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \
-     BF_##reg##_##f05 | BF_##reg##_##f06 | BF_##reg##_##f07 | BF_##reg##_##f08 | \
-     BF_##reg##_##f09 | BF_##reg##_##f10 | BF_##reg##_##f11 | BF_##reg##_##f12 | \
-     BF_##reg##_##f13 | BF_##reg##_##f14 | BF_##reg##_##f15)
-#define BF_OR16(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
-        f11, f12, f13, f14, f15, f16) \
-    (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \
-     BF_##reg##_##f05 | BF_##reg##_##f06 | BF_##reg##_##f07 | BF_##reg##_##f08 | \
-     BF_##reg##_##f09 | BF_##reg##_##f10 | BF_##reg##_##f11 | BF_##reg##_##f12 | \
-     BF_##reg##_##f13 | BF_##reg##_##f14 | BF_##reg##_##f15 | BF_##reg##_##f16)
-#define BF_OR17(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
-        f11, f12, f13, f14, f15, f16, f17) \
-    (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \
-     BF_##reg##_##f05 | BF_##reg##_##f06 | BF_##reg##_##f07 | BF_##reg##_##f08 | \
-     BF_##reg##_##f09 | BF_##reg##_##f10 | BF_##reg##_##f11 | BF_##reg##_##f12 | \
-     BF_##reg##_##f13 | BF_##reg##_##f14 | BF_##reg##_##f15 | BF_##reg##_##f16 | \
-     BF_##reg##_##f17)
-#define BF_OR18(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
-        f11, f12, f13, f14, f15, f16, f17, f18) \
-    (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \
-     BF_##reg##_##f05 | BF_##reg##_##f06 | BF_##reg##_##f07 | BF_##reg##_##f08 | \
-     BF_##reg##_##f09 | BF_##reg##_##f10 | BF_##reg##_##f11 | BF_##reg##_##f12 | \
-     BF_##reg##_##f13 | BF_##reg##_##f14 | BF_##reg##_##f15 | BF_##reg##_##f16 | \
-     BF_##reg##_##f17 | BF_##reg##_##f18)
-#define BF_OR19(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
-        f11, f12, f13, f14, f15, f16, f17, f18, f19) \
-    (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \
-     BF_##reg##_##f05 | BF_##reg##_##f06 | BF_##reg##_##f07 | BF_##reg##_##f08 | \
-     BF_##reg##_##f09 | BF_##reg##_##f10 | BF_##reg##_##f11 | BF_##reg##_##f12 | \
-     BF_##reg##_##f13 | BF_##reg##_##f14 | BF_##reg##_##f15 | BF_##reg##_##f16 | \
-     BF_##reg##_##f17 | BF_##reg##_##f18 | BF_##reg##_##f19)
-#define BF_OR20(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
-        f11, f12, f13, f14, f15, f16, f17, f18, f19, f20) \
-    (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \
-     BF_##reg##_##f05 | BF_##reg##_##f06 | BF_##reg##_##f07 | BF_##reg##_##f08 | \
-     BF_##reg##_##f09 | BF_##reg##_##f10 | BF_##reg##_##f11 | BF_##reg##_##f12 | \
-     BF_##reg##_##f13 | BF_##reg##_##f14 | BF_##reg##_##f15 | BF_##reg##_##f16 | \
-     BF_##reg##_##f17 | BF_##reg##_##f18 | BF_##reg##_##f19 | BF_##reg##_##f20)
-#define BF_OR21(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
-        f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, \
-        f21) \
-    (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \
-     BF_##reg##_##f05 | BF_##reg##_##f06 | BF_##reg##_##f07 | BF_##reg##_##f08 | \
-     BF_##reg##_##f09 | BF_##reg##_##f10 | BF_##reg##_##f11 | BF_##reg##_##f12 | \
-     BF_##reg##_##f13 | BF_##reg##_##f14 | BF_##reg##_##f15 | BF_##reg##_##f16 | \
-     BF_##reg##_##f17 | BF_##reg##_##f18 | BF_##reg##_##f19 | BF_##reg##_##f20 | \
-     BF_##reg##_##f21)
-#define BF_OR22(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
-        f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, \
-        f21, f22) \
-    (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \
-     BF_##reg##_##f05 | BF_##reg##_##f06 | BF_##reg##_##f07 | BF_##reg##_##f08 | \
-     BF_##reg##_##f09 | BF_##reg##_##f10 | BF_##reg##_##f11 | BF_##reg##_##f12 | \
-     BF_##reg##_##f13 | BF_##reg##_##f14 | BF_##reg##_##f15 | BF_##reg##_##f16 | \
-     BF_##reg##_##f17 | BF_##reg##_##f18 | BF_##reg##_##f19 | BF_##reg##_##f20 | \
-     BF_##reg##_##f21 | BF_##reg##_##f22)
-#define BF_OR23(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
-        f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, \
-        f21, f22, f23) \
-    (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \
-     BF_##reg##_##f05 | BF_##reg##_##f06 | BF_##reg##_##f07 | BF_##reg##_##f08 | \
-     BF_##reg##_##f09 | BF_##reg##_##f10 | BF_##reg##_##f11 | BF_##reg##_##f12 | \
-     BF_##reg##_##f13 | BF_##reg##_##f14 | BF_##reg##_##f15 | BF_##reg##_##f16 | \
-     BF_##reg##_##f17 | BF_##reg##_##f18 | BF_##reg##_##f19 | BF_##reg##_##f20 | \
-     BF_##reg##_##f21 | BF_##reg##_##f22 | BF_##reg##_##f23)
-#define BF_OR24(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
-        f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, \
-        f21, f22, f23, f24) \
-    (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \
-     BF_##reg##_##f05 | BF_##reg##_##f06 | BF_##reg##_##f07 | BF_##reg##_##f08 | \
-     BF_##reg##_##f09 | BF_##reg##_##f10 | BF_##reg##_##f11 | BF_##reg##_##f12 | \
-     BF_##reg##_##f13 | BF_##reg##_##f14 | BF_##reg##_##f15 | BF_##reg##_##f16 | \
-     BF_##reg##_##f17 | BF_##reg##_##f18 | BF_##reg##_##f19 | BF_##reg##_##f20 | \
-     BF_##reg##_##f21 | BF_##reg##_##f22 | BF_##reg##_##f23 | BF_##reg##_##f24)
-#define BF_OR25(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
-        f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, \
-        f21, f22, f23, f24, f25) \
-    (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \
-     BF_##reg##_##f05 | BF_##reg##_##f06 | BF_##reg##_##f07 | BF_##reg##_##f08 | \
-     BF_##reg##_##f09 | BF_##reg##_##f10 | BF_##reg##_##f11 | BF_##reg##_##f12 | \
-     BF_##reg##_##f13 | BF_##reg##_##f14 | BF_##reg##_##f15 | BF_##reg##_##f16 | \
-     BF_##reg##_##f17 | BF_##reg##_##f18 | BF_##reg##_##f19 | BF_##reg##_##f20 | \
-     BF_##reg##_##f21 | BF_##reg##_##f22 | BF_##reg##_##f23 | BF_##reg##_##f24 | \
-     BF_##reg##_##f25)
-#define BF_OR26(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
-        f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, \
-        f21, f22, f23, f24, f25, f26) \
-    (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \
-     BF_##reg##_##f05 | BF_##reg##_##f06 | BF_##reg##_##f07 | BF_##reg##_##f08 | \
-     BF_##reg##_##f09 | BF_##reg##_##f10 | BF_##reg##_##f11 | BF_##reg##_##f12 | \
-     BF_##reg##_##f13 | BF_##reg##_##f14 | BF_##reg##_##f15 | BF_##reg##_##f16 | \
-     BF_##reg##_##f17 | BF_##reg##_##f18 | BF_##reg##_##f19 | BF_##reg##_##f20 | \
-     BF_##reg##_##f21 | BF_##reg##_##f22 | BF_##reg##_##f23 | BF_##reg##_##f24 | \
-     BF_##reg##_##f25 | BF_##reg##_##f26)
-#define BF_OR27(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
-        f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, \
-        f21, f22, f23, f24, f25, f26, f27) \
-    (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \
-     BF_##reg##_##f05 | BF_##reg##_##f06 | BF_##reg##_##f07 | BF_##reg##_##f08 | \
-     BF_##reg##_##f09 | BF_##reg##_##f10 | BF_##reg##_##f11 | BF_##reg##_##f12 | \
-     BF_##reg##_##f13 | BF_##reg##_##f14 | BF_##reg##_##f15 | BF_##reg##_##f16 | \
-     BF_##reg##_##f17 | BF_##reg##_##f18 | BF_##reg##_##f19 | BF_##reg##_##f20 | \
-     BF_##reg##_##f21 | BF_##reg##_##f22 | BF_##reg##_##f23 | BF_##reg##_##f24 | \
-     BF_##reg##_##f25 | BF_##reg##_##f26 | BF_##reg##_##f27)
-#define BF_OR28(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
-        f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, \
-        f21, f22, f23, f24, f25, f26, f27, f28) \
-    (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \
-     BF_##reg##_##f05 | BF_##reg##_##f06 | BF_##reg##_##f07 | BF_##reg##_##f08 | \
-     BF_##reg##_##f09 | BF_##reg##_##f10 | BF_##reg##_##f11 | BF_##reg##_##f12 | \
-     BF_##reg##_##f13 | BF_##reg##_##f14 | BF_##reg##_##f15 | BF_##reg##_##f16 | \
-     BF_##reg##_##f17 | BF_##reg##_##f18 | BF_##reg##_##f19 | BF_##reg##_##f20 | \
-     BF_##reg##_##f21 | BF_##reg##_##f22 | BF_##reg##_##f23 | BF_##reg##_##f24 | \
-     BF_##reg##_##f25 | BF_##reg##_##f26 | BF_##reg##_##f27 | BF_##reg##_##f28)
-#define BF_OR29(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
-        f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, \
-        f21, f22, f23, f24, f25, f26, f27, f28, f29) \
-    (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \
-     BF_##reg##_##f05 | BF_##reg##_##f06 | BF_##reg##_##f07 | BF_##reg##_##f08 | \
-     BF_##reg##_##f09 | BF_##reg##_##f10 | BF_##reg##_##f11 | BF_##reg##_##f12 | \
-     BF_##reg##_##f13 | BF_##reg##_##f14 | BF_##reg##_##f15 | BF_##reg##_##f16 | \
-     BF_##reg##_##f17 | BF_##reg##_##f18 | BF_##reg##_##f19 | BF_##reg##_##f20 | \
-     BF_##reg##_##f21 | BF_##reg##_##f22 | BF_##reg##_##f23 | BF_##reg##_##f24 | \
-     BF_##reg##_##f25 | BF_##reg##_##f26 | BF_##reg##_##f27 | BF_##reg##_##f28 | \
-     BF_##reg##_##f29)
-#define BF_OR30(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
-        f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, \
-        f21, f22, f23, f24, f25, f26, f27, f28, f29, f30) \
-    (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \
-     BF_##reg##_##f05 | BF_##reg##_##f06 | BF_##reg##_##f07 | BF_##reg##_##f08 | \
-     BF_##reg##_##f09 | BF_##reg##_##f10 | BF_##reg##_##f11 | BF_##reg##_##f12 | \
-     BF_##reg##_##f13 | BF_##reg##_##f14 | BF_##reg##_##f15 | BF_##reg##_##f16 | \
-     BF_##reg##_##f17 | BF_##reg##_##f18 | BF_##reg##_##f19 | BF_##reg##_##f20 | \
-     BF_##reg##_##f21 | BF_##reg##_##f22 | BF_##reg##_##f23 | BF_##reg##_##f24 | \
-     BF_##reg##_##f25 | BF_##reg##_##f26 | BF_##reg##_##f27 | BF_##reg##_##f28 | \
-     BF_##reg##_##f29 | BF_##reg##_##f30)
-#define BF_OR31(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
-        f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, \
-        f21, f22, f23, f24, f25, f26, f27, f28, f29, f30, \
-        f31) \
-    (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \
-     BF_##reg##_##f05 | BF_##reg##_##f06 | BF_##reg##_##f07 | BF_##reg##_##f08 | \
-     BF_##reg##_##f09 | BF_##reg##_##f10 | BF_##reg##_##f11 | BF_##reg##_##f12 | \
-     BF_##reg##_##f13 | BF_##reg##_##f14 | BF_##reg##_##f15 | BF_##reg##_##f16 | \
-     BF_##reg##_##f17 | BF_##reg##_##f18 | BF_##reg##_##f19 | BF_##reg##_##f20 | \
-     BF_##reg##_##f21 | BF_##reg##_##f22 | BF_##reg##_##f23 | BF_##reg##_##f24 | \
-     BF_##reg##_##f25 | BF_##reg##_##f26 | BF_##reg##_##f27 | BF_##reg##_##f28 | \
-     BF_##reg##_##f29 | BF_##reg##_##f30 | BF_##reg##_##f31)
-#define BF_OR32(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
-        f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, \
-        f21, f22, f23, f24, f25, f26, f27, f28, f29, f30, \
-        f31, f32) \
-    (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \
-     BF_##reg##_##f05 | BF_##reg##_##f06 | BF_##reg##_##f07 | BF_##reg##_##f08 | \
-     BF_##reg##_##f09 | BF_##reg##_##f10 | BF_##reg##_##f11 | BF_##reg##_##f12 | \
-     BF_##reg##_##f13 | BF_##reg##_##f14 | BF_##reg##_##f15 | BF_##reg##_##f16 | \
-     BF_##reg##_##f17 | BF_##reg##_##f18 | BF_##reg##_##f19 | BF_##reg##_##f20 | \
-     BF_##reg##_##f21 | BF_##reg##_##f22 | BF_##reg##_##f23 | BF_##reg##_##f24 | \
-     BF_##reg##_##f25 | BF_##reg##_##f26 | BF_##reg##_##f27 | BF_##reg##_##f28 | \
-     BF_##reg##_##f29 | BF_##reg##_##f30 | BF_##reg##_##f31 | BF_##reg##_##f32)
-
-#define REG_NARG(...) REG_NARGS_(__VA_ARGS__, 32, 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1)
-#define REG_NARGS_(_1, _2, _3, _4, _5, _6, _7, _8, _9, _10, _11, _12, _13, _14, _15, _16, _17, _18, _19, _20, _21, _22, _23, _24, _25, _26, _27, _28, _29, _30, _31, _32, N, ...) N
-
-#define REG_VARIADIC(macro, reg, ...) REG_VARIADIC_(macro, REG_NARG(__VA_ARGS__), reg, __VA_ARGS__)
-#define REG_VARIADIC_(macro, cnt, reg, ...) REG_VARIADIC__(macro, cnt, reg, __VA_ARGS__)
-#define REG_VARIADIC__(macro, cnt, reg, ...) REG_VARIADIC___(macro##cnt, reg, __VA_ARGS__)
-#define REG_VARIADIC___(macro, reg, ...) macro(reg, __VA_ARGS__)
-
-#define BM_OR(reg, ...) REG_VARIADIC(BM_OR, reg, __VA_ARGS__)
-#define BF_OR(reg, ...) REG_VARIADIC(BF_OR, reg, __VA_ARGS__)
-#endif /* __REGS__MACRO__H__ */
diff --git a/firmware/target/arm/imx233/regs/regs-memcpy.h b/firmware/target/arm/imx233/regs/regs-memcpy.h
deleted file mode 100644
index 08968d7de5..0000000000
--- a/firmware/target/arm/imx233/regs/regs-memcpy.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3600:2.3.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __SELECT__MEMCPY__H__
-#define __SELECT__MEMCPY__H__
-#include "regs-macro.h"
-
-#define STMP3600_INCLUDE "stmp3600/regs-memcpy.h"
-
-#include "regs-select.h"
-
-#undef STMP3600_INCLUDE
-
-#endif /* __SELECT__MEMCPY__H__ */
diff --git a/firmware/target/arm/imx233/regs/regs-pinctrl.h b/firmware/target/arm/imx233/regs/regs-pinctrl.h
deleted file mode 100644
index cc3de37899..0000000000
--- a/firmware/target/arm/imx233/regs/regs-pinctrl.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3600:2.3.0 stmp3700:3.2.0 imx233:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __SELECT__PINCTRL__H__
-#define __SELECT__PINCTRL__H__
-#include "regs-macro.h"
-
-#define STMP3600_INCLUDE "stmp3600/regs-pinctrl.h"
-#define STMP3700_INCLUDE "stmp3700/regs-pinctrl.h"
-#define IMX233_INCLUDE "imx233/regs-pinctrl.h"
-
-#include "regs-select.h"
-
-#undef STMP3600_INCLUDE
-#undef STMP3700_INCLUDE
-#undef IMX233_INCLUDE
-
-#endif /* __SELECT__PINCTRL__H__ */
diff --git a/firmware/target/arm/imx233/regs/regs-power.h b/firmware/target/arm/imx233/regs/regs-power.h
deleted file mode 100644
index 0ce92a0233..0000000000
--- a/firmware/target/arm/imx233/regs/regs-power.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3600:2.3.0 stmp3700:3.2.0 imx233:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __SELECT__POWER__H__
-#define __SELECT__POWER__H__
-#include "regs-macro.h"
-
-#define STMP3600_INCLUDE "stmp3600/regs-power.h"
-#define STMP3700_INCLUDE "stmp3700/regs-power.h"
-#define IMX233_INCLUDE "imx233/regs-power.h"
-
-#include "regs-select.h"
-
-#undef STMP3600_INCLUDE
-#undef STMP3700_INCLUDE
-#undef IMX233_INCLUDE
-
-#endif /* __SELECT__POWER__H__ */
diff --git a/firmware/target/arm/imx233/regs/regs-pwm.h b/firmware/target/arm/imx233/regs/regs-pwm.h
deleted file mode 100644
index 563fdb8fa6..0000000000
--- a/firmware/target/arm/imx233/regs/regs-pwm.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3600:2.3.0 stmp3700:3.2.0 imx233:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __SELECT__PWM__H__
-#define __SELECT__PWM__H__
-#include "regs-macro.h"
-
-#define STMP3600_INCLUDE "stmp3600/regs-pwm.h"
-#define STMP3700_INCLUDE "stmp3700/regs-pwm.h"
-#define IMX233_INCLUDE "imx233/regs-pwm.h"
-
-#include "regs-select.h"
-
-#undef STMP3600_INCLUDE
-#undef STMP3700_INCLUDE
-#undef IMX233_INCLUDE
-
-#endif /* __SELECT__PWM__H__ */
diff --git a/firmware/target/arm/imx233/regs/regs-rtc.h b/firmware/target/arm/imx233/regs/regs-rtc.h
deleted file mode 100644
index 01effef0a2..0000000000
--- a/firmware/target/arm/imx233/regs/regs-rtc.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3600:2.3.0 stmp3700:3.2.0 imx233:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __SELECT__RTC__H__
-#define __SELECT__RTC__H__
-#include "regs-macro.h"
-
-#define STMP3600_INCLUDE "stmp3600/regs-rtc.h"
-#define STMP3700_INCLUDE "stmp3700/regs-rtc.h"
-#define IMX233_INCLUDE "imx233/regs-rtc.h"
-
-#include "regs-select.h"
-
-#undef STMP3600_INCLUDE
-#undef STMP3700_INCLUDE
-#undef IMX233_INCLUDE
-
-#endif /* __SELECT__RTC__H__ */
diff --git a/firmware/target/arm/imx233/regs/regs-saif.h b/firmware/target/arm/imx233/regs/regs-saif.h
deleted file mode 100644
index 5b4fd6d8ae..0000000000
--- a/firmware/target/arm/imx233/regs/regs-saif.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3700:3.2.0 imx233:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __SELECT__SAIF__H__
-#define __SELECT__SAIF__H__
-#include "regs-macro.h"
-
-#define STMP3700_INCLUDE "stmp3700/regs-saif.h"
-#define IMX233_INCLUDE "imx233/regs-saif.h"
-
-#include "regs-select.h"
-
-#undef STMP3700_INCLUDE
-#undef IMX233_INCLUDE
-
-#endif /* __SELECT__SAIF__H__ */
diff --git a/firmware/target/arm/imx233/regs/regs-spdif.h b/firmware/target/arm/imx233/regs/regs-spdif.h
deleted file mode 100644
index 7e07e4691b..0000000000
--- a/firmware/target/arm/imx233/regs/regs-spdif.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3600:2.3.0 stmp3700:3.2.0 imx233:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __SELECT__SPDIF__H__
-#define __SELECT__SPDIF__H__
-#include "regs-macro.h"
-
-#define STMP3600_INCLUDE "stmp3600/regs-spdif.h"
-#define STMP3700_INCLUDE "stmp3700/regs-spdif.h"
-#define IMX233_INCLUDE "imx233/regs-spdif.h"
-
-#include "regs-select.h"
-
-#undef STMP3600_INCLUDE
-#undef STMP3700_INCLUDE
-#undef IMX233_INCLUDE
-
-#endif /* __SELECT__SPDIF__H__ */
diff --git a/firmware/target/arm/imx233/regs/regs-ssp.h b/firmware/target/arm/imx233/regs/regs-ssp.h
deleted file mode 100644
index 66752997af..0000000000
--- a/firmware/target/arm/imx233/regs/regs-ssp.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3600:2.3.0 stmp3700:3.2.0 imx233:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __SELECT__SSP__H__
-#define __SELECT__SSP__H__
-#include "regs-macro.h"
-
-#define STMP3600_INCLUDE "stmp3600/regs-ssp.h"
-#define STMP3700_INCLUDE "stmp3700/regs-ssp.h"
-#define IMX233_INCLUDE "imx233/regs-ssp.h"
-
-#include "regs-select.h"
-
-#undef STMP3600_INCLUDE
-#undef STMP3700_INCLUDE
-#undef IMX233_INCLUDE
-
-#endif /* __SELECT__SSP__H__ */
diff --git a/firmware/target/arm/imx233/regs/regs-timrot.h b/firmware/target/arm/imx233/regs/regs-timrot.h
deleted file mode 100644
index c03b8ca108..0000000000
--- a/firmware/target/arm/imx233/regs/regs-timrot.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3600:2.3.0 stmp3700:3.2.0 imx233:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __SELECT__TIMROT__H__
-#define __SELECT__TIMROT__H__
-#include "regs-macro.h"
-
-#define STMP3600_INCLUDE "stmp3600/regs-timrot.h"
-#define STMP3700_INCLUDE "stmp3700/regs-timrot.h"
-#define IMX233_INCLUDE "imx233/regs-timrot.h"
-
-#include "regs-select.h"
-
-#undef STMP3600_INCLUDE
-#undef STMP3700_INCLUDE
-#undef IMX233_INCLUDE
-
-#endif /* __SELECT__TIMROT__H__ */
diff --git a/firmware/target/arm/imx233/regs/regs-uartapp.h b/firmware/target/arm/imx233/regs/regs-uartapp.h
deleted file mode 100644
index d698e6c3ff..0000000000
--- a/firmware/target/arm/imx233/regs/regs-uartapp.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3600:2.3.0 stmp3700:3.2.0 imx233:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __SELECT__UARTAPP__H__
-#define __SELECT__UARTAPP__H__
-#include "regs-macro.h"
-
-#define STMP3600_INCLUDE "stmp3600/regs-uartapp.h"
-#define STMP3700_INCLUDE "stmp3700/regs-uartapp.h"
-#define IMX233_INCLUDE "imx233/regs-uartapp.h"
-
-#include "regs-select.h"
-
-#undef STMP3600_INCLUDE
-#undef STMP3700_INCLUDE
-#undef IMX233_INCLUDE
-
-#endif /* __SELECT__UARTAPP__H__ */
diff --git a/firmware/target/arm/imx233/regs/regs-uartdbg.h b/firmware/target/arm/imx233/regs/regs-uartdbg.h
deleted file mode 100644
index 1487bf7759..0000000000
--- a/firmware/target/arm/imx233/regs/regs-uartdbg.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3600:2.3.0 stmp3700:3.2.0 imx233:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __SELECT__UARTDBG__H__
-#define __SELECT__UARTDBG__H__
-#include "regs-macro.h"
-
-#define STMP3600_INCLUDE "stmp3600/regs-uartdbg.h"
-#define STMP3700_INCLUDE "stmp3700/regs-uartdbg.h"
-#define IMX233_INCLUDE "imx233/regs-uartdbg.h"
-
-#include "regs-select.h"
-
-#undef STMP3600_INCLUDE
-#undef STMP3700_INCLUDE
-#undef IMX233_INCLUDE
-
-#endif /* __SELECT__UARTDBG__H__ */
diff --git a/firmware/target/arm/imx233/regs/regs-usbctrl.h b/firmware/target/arm/imx233/regs/regs-usbctrl.h
deleted file mode 100644
index 2e9493c852..0000000000
--- a/firmware/target/arm/imx233/regs/regs-usbctrl.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3700:3.2.0 imx233:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __SELECT__USBCTRL__H__
-#define __SELECT__USBCTRL__H__
-#include "regs-macro.h"
-
-#define STMP3700_INCLUDE "stmp3700/regs-usbctrl.h"
-#define IMX233_INCLUDE "imx233/regs-usbctrl.h"
-
-#include "regs-select.h"
-
-#undef STMP3700_INCLUDE
-#undef IMX233_INCLUDE
-
-#endif /* __SELECT__USBCTRL__H__ */
diff --git a/firmware/target/arm/imx233/regs/regs-usbphy.h b/firmware/target/arm/imx233/regs/regs-usbphy.h
deleted file mode 100644
index 7cc2f83d1c..0000000000
--- a/firmware/target/arm/imx233/regs/regs-usbphy.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3600:2.3.0 stmp3700:3.2.0 imx233:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __SELECT__USBPHY__H__
-#define __SELECT__USBPHY__H__
-#include "regs-macro.h"
-
-#define STMP3600_INCLUDE "stmp3600/regs-usbphy.h"
-#define STMP3700_INCLUDE "stmp3700/regs-usbphy.h"
-#define IMX233_INCLUDE "imx233/regs-usbphy.h"
-
-#include "regs-select.h"
-
-#undef STMP3600_INCLUDE
-#undef STMP3700_INCLUDE
-#undef IMX233_INCLUDE
-
-#endif /* __SELECT__USBPHY__H__ */
diff --git a/firmware/target/arm/imx233/regs/rtc.h b/firmware/target/arm/imx233/regs/rtc.h
new file mode 100644
index 0000000000..c7acce14d8
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/rtc.h
@@ -0,0 +1,37 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_RTC_H__
+#define __HEADERGEN_RTC_H__
+
+#include "macro.h"
+
+#define STMP3600_INCLUDE    "stmp3600/rtc.h"
+#define STMP3700_INCLUDE    "stmp3700/rtc.h"
+#define IMX233_INCLUDE      "imx233/rtc.h"
+
+#include "select.h"
+
+#undef STMP3600_INCLUDE
+#undef STMP3700_INCLUDE
+#undef IMX233_INCLUDE
+
+#endif /* __HEADERGEN_RTC_H__*/
diff --git a/firmware/target/arm/imx233/regs/saif.h b/firmware/target/arm/imx233/regs/saif.h
new file mode 100644
index 0000000000..1e4f7cf234
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/saif.h
@@ -0,0 +1,35 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_SAIF_H__
+#define __HEADERGEN_SAIF_H__
+
+#include "macro.h"
+
+#define STMP3700_INCLUDE    "stmp3700/saif.h"
+#define IMX233_INCLUDE      "imx233/saif.h"
+
+#include "select.h"
+
+#undef STMP3700_INCLUDE
+#undef IMX233_INCLUDE
+
+#endif /* __HEADERGEN_SAIF_H__*/
diff --git a/firmware/target/arm/imx233/regs/regs-select.h b/firmware/target/arm/imx233/regs/select.h
index fa944bd6ad..fa944bd6ad 100644
--- a/firmware/target/arm/imx233/regs/regs-select.h
+++ b/firmware/target/arm/imx233/regs/select.h
diff --git a/firmware/target/arm/imx233/regs/spdif.h b/firmware/target/arm/imx233/regs/spdif.h
new file mode 100644
index 0000000000..0db5d2dee7
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/spdif.h
@@ -0,0 +1,37 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_SPDIF_H__
+#define __HEADERGEN_SPDIF_H__
+
+#include "macro.h"
+
+#define STMP3600_INCLUDE    "stmp3600/spdif.h"
+#define STMP3700_INCLUDE    "stmp3700/spdif.h"
+#define IMX233_INCLUDE      "imx233/spdif.h"
+
+#include "select.h"
+
+#undef STMP3600_INCLUDE
+#undef STMP3700_INCLUDE
+#undef IMX233_INCLUDE
+
+#endif /* __HEADERGEN_SPDIF_H__*/
diff --git a/firmware/target/arm/imx233/regs/ssp.h b/firmware/target/arm/imx233/regs/ssp.h
new file mode 100644
index 0000000000..c9d6aa61f9
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/ssp.h
@@ -0,0 +1,37 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_SSP_H__
+#define __HEADERGEN_SSP_H__
+
+#include "macro.h"
+
+#define STMP3600_INCLUDE    "stmp3600/ssp.h"
+#define STMP3700_INCLUDE    "stmp3700/ssp.h"
+#define IMX233_INCLUDE      "imx233/ssp.h"
+
+#include "select.h"
+
+#undef STMP3600_INCLUDE
+#undef STMP3700_INCLUDE
+#undef IMX233_INCLUDE
+
+#endif /* __HEADERGEN_SSP_H__*/
diff --git a/firmware/target/arm/imx233/regs/stmp3600/anatop.h b/firmware/target/arm/imx233/regs/stmp3600/anatop.h
new file mode 100644
index 0000000000..749e9f352c
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3600/anatop.h
@@ -0,0 +1,135 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * stmp3600 version: 2.4.0
+ * stmp3600 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_STMP3600_ANATOP_H__
+#define __HEADERGEN_STMP3600_ANATOP_H__
+
+#define HW_ANATOP_PROBE_OUTPUT_SELECT                       HW(ANATOP_PROBE_OUTPUT_SELECT)
+#define HWA_ANATOP_PROBE_OUTPUT_SELECT                      (0x8003c200 + 0x0)
+#define HWT_ANATOP_PROBE_OUTPUT_SELECT                      HWIO_32_RW
+#define HWN_ANATOP_PROBE_OUTPUT_SELECT                      ANATOP_PROBE_OUTPUT_SELECT
+#define HWI_ANATOP_PROBE_OUTPUT_SELECT                      
+#define HW_ANATOP_PROBE_OUTPUT_SELECT_SET                   HW(ANATOP_PROBE_OUTPUT_SELECT_SET)
+#define HWA_ANATOP_PROBE_OUTPUT_SELECT_SET                  (HWA_ANATOP_PROBE_OUTPUT_SELECT + 0x4)
+#define HWT_ANATOP_PROBE_OUTPUT_SELECT_SET                  HWIO_32_WO
+#define HWN_ANATOP_PROBE_OUTPUT_SELECT_SET                  ANATOP_PROBE_OUTPUT_SELECT
+#define HWI_ANATOP_PROBE_OUTPUT_SELECT_SET                  
+#define HW_ANATOP_PROBE_OUTPUT_SELECT_CLR                   HW(ANATOP_PROBE_OUTPUT_SELECT_CLR)
+#define HWA_ANATOP_PROBE_OUTPUT_SELECT_CLR                  (HWA_ANATOP_PROBE_OUTPUT_SELECT + 0x8)
+#define HWT_ANATOP_PROBE_OUTPUT_SELECT_CLR                  HWIO_32_WO
+#define HWN_ANATOP_PROBE_OUTPUT_SELECT_CLR                  ANATOP_PROBE_OUTPUT_SELECT
+#define HWI_ANATOP_PROBE_OUTPUT_SELECT_CLR                  
+#define HW_ANATOP_PROBE_OUTPUT_SELECT_TOG                   HW(ANATOP_PROBE_OUTPUT_SELECT_TOG)
+#define HWA_ANATOP_PROBE_OUTPUT_SELECT_TOG                  (HWA_ANATOP_PROBE_OUTPUT_SELECT + 0xc)
+#define HWT_ANATOP_PROBE_OUTPUT_SELECT_TOG                  HWIO_32_WO
+#define HWN_ANATOP_PROBE_OUTPUT_SELECT_TOG                  ANATOP_PROBE_OUTPUT_SELECT
+#define HWI_ANATOP_PROBE_OUTPUT_SELECT_TOG                  
+#define BP_ANATOP_PROBE_OUTPUT_SELECT_OUTPUT_SELECT         0
+#define BM_ANATOP_PROBE_OUTPUT_SELECT_OUTPUT_SELECT         0xffffffff
+#define BF_ANATOP_PROBE_OUTPUT_SELECT_OUTPUT_SELECT(v)      (((v) & 0xffffffff) << 0)
+#define BFM_ANATOP_PROBE_OUTPUT_SELECT_OUTPUT_SELECT(v)     BM_ANATOP_PROBE_OUTPUT_SELECT_OUTPUT_SELECT
+#define BF_ANATOP_PROBE_OUTPUT_SELECT_OUTPUT_SELECT_V(e)    BF_ANATOP_PROBE_OUTPUT_SELECT_OUTPUT_SELECT(BV_ANATOP_PROBE_OUTPUT_SELECT_OUTPUT_SELECT__##e)
+#define BFM_ANATOP_PROBE_OUTPUT_SELECT_OUTPUT_SELECT_V(v)   BM_ANATOP_PROBE_OUTPUT_SELECT_OUTPUT_SELECT
+
+#define HW_ANATOP_PROBE_INPUT_SELECT                    HW(ANATOP_PROBE_INPUT_SELECT)
+#define HWA_ANATOP_PROBE_INPUT_SELECT                   (0x8003c200 + 0x10)
+#define HWT_ANATOP_PROBE_INPUT_SELECT                   HWIO_32_RW
+#define HWN_ANATOP_PROBE_INPUT_SELECT                   ANATOP_PROBE_INPUT_SELECT
+#define HWI_ANATOP_PROBE_INPUT_SELECT                   
+#define HW_ANATOP_PROBE_INPUT_SELECT_SET                HW(ANATOP_PROBE_INPUT_SELECT_SET)
+#define HWA_ANATOP_PROBE_INPUT_SELECT_SET               (HWA_ANATOP_PROBE_INPUT_SELECT + 0x4)
+#define HWT_ANATOP_PROBE_INPUT_SELECT_SET               HWIO_32_WO
+#define HWN_ANATOP_PROBE_INPUT_SELECT_SET               ANATOP_PROBE_INPUT_SELECT
+#define HWI_ANATOP_PROBE_INPUT_SELECT_SET               
+#define HW_ANATOP_PROBE_INPUT_SELECT_CLR                HW(ANATOP_PROBE_INPUT_SELECT_CLR)
+#define HWA_ANATOP_PROBE_INPUT_SELECT_CLR               (HWA_ANATOP_PROBE_INPUT_SELECT + 0x8)
+#define HWT_ANATOP_PROBE_INPUT_SELECT_CLR               HWIO_32_WO
+#define HWN_ANATOP_PROBE_INPUT_SELECT_CLR               ANATOP_PROBE_INPUT_SELECT
+#define HWI_ANATOP_PROBE_INPUT_SELECT_CLR               
+#define HW_ANATOP_PROBE_INPUT_SELECT_TOG                HW(ANATOP_PROBE_INPUT_SELECT_TOG)
+#define HWA_ANATOP_PROBE_INPUT_SELECT_TOG               (HWA_ANATOP_PROBE_INPUT_SELECT + 0xc)
+#define HWT_ANATOP_PROBE_INPUT_SELECT_TOG               HWIO_32_WO
+#define HWN_ANATOP_PROBE_INPUT_SELECT_TOG               ANATOP_PROBE_INPUT_SELECT
+#define HWI_ANATOP_PROBE_INPUT_SELECT_TOG               
+#define BP_ANATOP_PROBE_INPUT_SELECT_INPUT_SELECT       0
+#define BM_ANATOP_PROBE_INPUT_SELECT_INPUT_SELECT       0xffffffff
+#define BF_ANATOP_PROBE_INPUT_SELECT_INPUT_SELECT(v)    (((v) & 0xffffffff) << 0)
+#define BFM_ANATOP_PROBE_INPUT_SELECT_INPUT_SELECT(v)   BM_ANATOP_PROBE_INPUT_SELECT_INPUT_SELECT
+#define BF_ANATOP_PROBE_INPUT_SELECT_INPUT_SELECT_V(e)  BF_ANATOP_PROBE_INPUT_SELECT_INPUT_SELECT(BV_ANATOP_PROBE_INPUT_SELECT_INPUT_SELECT__##e)
+#define BFM_ANATOP_PROBE_INPUT_SELECT_INPUT_SELECT_V(v) BM_ANATOP_PROBE_INPUT_SELECT_INPUT_SELECT
+
+#define HW_ANATOP_PROBE_DATA            HW(ANATOP_PROBE_DATA)
+#define HWA_ANATOP_PROBE_DATA           (0x8003c200 + 0x20)
+#define HWT_ANATOP_PROBE_DATA           HWIO_32_RW
+#define HWN_ANATOP_PROBE_DATA           ANATOP_PROBE_DATA
+#define HWI_ANATOP_PROBE_DATA           
+#define HW_ANATOP_PROBE_DATA_SET        HW(ANATOP_PROBE_DATA_SET)
+#define HWA_ANATOP_PROBE_DATA_SET       (HWA_ANATOP_PROBE_DATA + 0x4)
+#define HWT_ANATOP_PROBE_DATA_SET       HWIO_32_WO
+#define HWN_ANATOP_PROBE_DATA_SET       ANATOP_PROBE_DATA
+#define HWI_ANATOP_PROBE_DATA_SET       
+#define HW_ANATOP_PROBE_DATA_CLR        HW(ANATOP_PROBE_DATA_CLR)
+#define HWA_ANATOP_PROBE_DATA_CLR       (HWA_ANATOP_PROBE_DATA + 0x8)
+#define HWT_ANATOP_PROBE_DATA_CLR       HWIO_32_WO
+#define HWN_ANATOP_PROBE_DATA_CLR       ANATOP_PROBE_DATA
+#define HWI_ANATOP_PROBE_DATA_CLR       
+#define HW_ANATOP_PROBE_DATA_TOG        HW(ANATOP_PROBE_DATA_TOG)
+#define HWA_ANATOP_PROBE_DATA_TOG       (HWA_ANATOP_PROBE_DATA + 0xc)
+#define HWT_ANATOP_PROBE_DATA_TOG       HWIO_32_WO
+#define HWN_ANATOP_PROBE_DATA_TOG       ANATOP_PROBE_DATA
+#define HWI_ANATOP_PROBE_DATA_TOG       
+#define BP_ANATOP_PROBE_DATA_DATA       0
+#define BM_ANATOP_PROBE_DATA_DATA       0xffffffff
+#define BF_ANATOP_PROBE_DATA_DATA(v)    (((v) & 0xffffffff) << 0)
+#define BFM_ANATOP_PROBE_DATA_DATA(v)   BM_ANATOP_PROBE_DATA_DATA
+#define BF_ANATOP_PROBE_DATA_DATA_V(e)  BF_ANATOP_PROBE_DATA_DATA(BV_ANATOP_PROBE_DATA_DATA__##e)
+#define BFM_ANATOP_PROBE_DATA_DATA_V(v) BM_ANATOP_PROBE_DATA_DATA
+
+#define HW_ANATOP_PROBE_DIGTOP_SELECT                       HW(ANATOP_PROBE_DIGTOP_SELECT)
+#define HWA_ANATOP_PROBE_DIGTOP_SELECT                      (0x8003c200 + 0x30)
+#define HWT_ANATOP_PROBE_DIGTOP_SELECT                      HWIO_32_RW
+#define HWN_ANATOP_PROBE_DIGTOP_SELECT                      ANATOP_PROBE_DIGTOP_SELECT
+#define HWI_ANATOP_PROBE_DIGTOP_SELECT                      
+#define HW_ANATOP_PROBE_DIGTOP_SELECT_SET                   HW(ANATOP_PROBE_DIGTOP_SELECT_SET)
+#define HWA_ANATOP_PROBE_DIGTOP_SELECT_SET                  (HWA_ANATOP_PROBE_DIGTOP_SELECT + 0x4)
+#define HWT_ANATOP_PROBE_DIGTOP_SELECT_SET                  HWIO_32_WO
+#define HWN_ANATOP_PROBE_DIGTOP_SELECT_SET                  ANATOP_PROBE_DIGTOP_SELECT
+#define HWI_ANATOP_PROBE_DIGTOP_SELECT_SET                  
+#define HW_ANATOP_PROBE_DIGTOP_SELECT_CLR                   HW(ANATOP_PROBE_DIGTOP_SELECT_CLR)
+#define HWA_ANATOP_PROBE_DIGTOP_SELECT_CLR                  (HWA_ANATOP_PROBE_DIGTOP_SELECT + 0x8)
+#define HWT_ANATOP_PROBE_DIGTOP_SELECT_CLR                  HWIO_32_WO
+#define HWN_ANATOP_PROBE_DIGTOP_SELECT_CLR                  ANATOP_PROBE_DIGTOP_SELECT
+#define HWI_ANATOP_PROBE_DIGTOP_SELECT_CLR                  
+#define HW_ANATOP_PROBE_DIGTOP_SELECT_TOG                   HW(ANATOP_PROBE_DIGTOP_SELECT_TOG)
+#define HWA_ANATOP_PROBE_DIGTOP_SELECT_TOG                  (HWA_ANATOP_PROBE_DIGTOP_SELECT + 0xc)
+#define HWT_ANATOP_PROBE_DIGTOP_SELECT_TOG                  HWIO_32_WO
+#define HWN_ANATOP_PROBE_DIGTOP_SELECT_TOG                  ANATOP_PROBE_DIGTOP_SELECT
+#define HWI_ANATOP_PROBE_DIGTOP_SELECT_TOG                  
+#define BP_ANATOP_PROBE_DIGTOP_SELECT_DIGTOP_SELECT         0
+#define BM_ANATOP_PROBE_DIGTOP_SELECT_DIGTOP_SELECT         0xffffffff
+#define BF_ANATOP_PROBE_DIGTOP_SELECT_DIGTOP_SELECT(v)      (((v) & 0xffffffff) << 0)
+#define BFM_ANATOP_PROBE_DIGTOP_SELECT_DIGTOP_SELECT(v)     BM_ANATOP_PROBE_DIGTOP_SELECT_DIGTOP_SELECT
+#define BF_ANATOP_PROBE_DIGTOP_SELECT_DIGTOP_SELECT_V(e)    BF_ANATOP_PROBE_DIGTOP_SELECT_DIGTOP_SELECT(BV_ANATOP_PROBE_DIGTOP_SELECT_DIGTOP_SELECT__##e)
+#define BFM_ANATOP_PROBE_DIGTOP_SELECT_DIGTOP_SELECT_V(v)   BM_ANATOP_PROBE_DIGTOP_SELECT_DIGTOP_SELECT
+
+#endif /* __HEADERGEN_STMP3600_ANATOP_H__*/
diff --git a/firmware/target/arm/imx233/regs/stmp3600/apbh.h b/firmware/target/arm/imx233/regs/stmp3600/apbh.h
new file mode 100644
index 0000000000..2dff1bbc0a
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3600/apbh.h
@@ -0,0 +1,423 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * stmp3600 version: 2.4.0
+ * stmp3600 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_STMP3600_APBH_H__
+#define __HEADERGEN_STMP3600_APBH_H__
+
+#define HW_APBH_CTRL0                           HW(APBH_CTRL0)
+#define HWA_APBH_CTRL0                          (0x80004000 + 0x0)
+#define HWT_APBH_CTRL0                          HWIO_32_RW
+#define HWN_APBH_CTRL0                          APBH_CTRL0
+#define HWI_APBH_CTRL0                          
+#define HW_APBH_CTRL0_SET                       HW(APBH_CTRL0_SET)
+#define HWA_APBH_CTRL0_SET                      (HWA_APBH_CTRL0 + 0x4)
+#define HWT_APBH_CTRL0_SET                      HWIO_32_WO
+#define HWN_APBH_CTRL0_SET                      APBH_CTRL0
+#define HWI_APBH_CTRL0_SET                      
+#define HW_APBH_CTRL0_CLR                       HW(APBH_CTRL0_CLR)
+#define HWA_APBH_CTRL0_CLR                      (HWA_APBH_CTRL0 + 0x8)
+#define HWT_APBH_CTRL0_CLR                      HWIO_32_WO
+#define HWN_APBH_CTRL0_CLR                      APBH_CTRL0
+#define HWI_APBH_CTRL0_CLR                      
+#define HW_APBH_CTRL0_TOG                       HW(APBH_CTRL0_TOG)
+#define HWA_APBH_CTRL0_TOG                      (HWA_APBH_CTRL0 + 0xc)
+#define HWT_APBH_CTRL0_TOG                      HWIO_32_WO
+#define HWN_APBH_CTRL0_TOG                      APBH_CTRL0
+#define HWI_APBH_CTRL0_TOG                      
+#define BP_APBH_CTRL0_SFTRST                    31
+#define BM_APBH_CTRL0_SFTRST                    0x80000000
+#define BF_APBH_CTRL0_SFTRST(v)                 (((v) & 0x1) << 31)
+#define BFM_APBH_CTRL0_SFTRST(v)                BM_APBH_CTRL0_SFTRST
+#define BF_APBH_CTRL0_SFTRST_V(e)               BF_APBH_CTRL0_SFTRST(BV_APBH_CTRL0_SFTRST__##e)
+#define BFM_APBH_CTRL0_SFTRST_V(v)              BM_APBH_CTRL0_SFTRST
+#define BP_APBH_CTRL0_CLKGATE                   30
+#define BM_APBH_CTRL0_CLKGATE                   0x40000000
+#define BF_APBH_CTRL0_CLKGATE(v)                (((v) & 0x1) << 30)
+#define BFM_APBH_CTRL0_CLKGATE(v)               BM_APBH_CTRL0_CLKGATE
+#define BF_APBH_CTRL0_CLKGATE_V(e)              BF_APBH_CTRL0_CLKGATE(BV_APBH_CTRL0_CLKGATE__##e)
+#define BFM_APBH_CTRL0_CLKGATE_V(v)             BM_APBH_CTRL0_CLKGATE
+#define BP_APBH_CTRL0_RESET_CHANNEL             16
+#define BM_APBH_CTRL0_RESET_CHANNEL             0xff0000
+#define BV_APBH_CTRL0_RESET_CHANNEL__HWECC      0x1
+#define BV_APBH_CTRL0_RESET_CHANNEL__SSP        0x2
+#define BV_APBH_CTRL0_RESET_CHANNEL__SRC        0x4
+#define BV_APBH_CTRL0_RESET_CHANNEL__DEST       0x8
+#define BV_APBH_CTRL0_RESET_CHANNEL__ATA        0x10
+#define BV_APBH_CTRL0_RESET_CHANNEL__NAND0      0x10
+#define BV_APBH_CTRL0_RESET_CHANNEL__NAND1      0x20
+#define BV_APBH_CTRL0_RESET_CHANNEL__NAND2      0x30
+#define BV_APBH_CTRL0_RESET_CHANNEL__NAND3      0x40
+#define BF_APBH_CTRL0_RESET_CHANNEL(v)          (((v) & 0xff) << 16)
+#define BFM_APBH_CTRL0_RESET_CHANNEL(v)         BM_APBH_CTRL0_RESET_CHANNEL
+#define BF_APBH_CTRL0_RESET_CHANNEL_V(e)        BF_APBH_CTRL0_RESET_CHANNEL(BV_APBH_CTRL0_RESET_CHANNEL__##e)
+#define BFM_APBH_CTRL0_RESET_CHANNEL_V(v)       BM_APBH_CTRL0_RESET_CHANNEL
+#define BP_APBH_CTRL0_CLKGATE_CHANNEL           8
+#define BM_APBH_CTRL0_CLKGATE_CHANNEL           0xff00
+#define BV_APBH_CTRL0_CLKGATE_CHANNEL__HWECC    0x1
+#define BV_APBH_CTRL0_CLKGATE_CHANNEL__SSP      0x2
+#define BV_APBH_CTRL0_CLKGATE_CHANNEL__SRC      0x4
+#define BV_APBH_CTRL0_CLKGATE_CHANNEL__DEST     0x8
+#define BV_APBH_CTRL0_CLKGATE_CHANNEL__ATA      0x10
+#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND0    0x10
+#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND1    0x20
+#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND2    0x30
+#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND3    0x40
+#define BF_APBH_CTRL0_CLKGATE_CHANNEL(v)        (((v) & 0xff) << 8)
+#define BFM_APBH_CTRL0_CLKGATE_CHANNEL(v)       BM_APBH_CTRL0_CLKGATE_CHANNEL
+#define BF_APBH_CTRL0_CLKGATE_CHANNEL_V(e)      BF_APBH_CTRL0_CLKGATE_CHANNEL(BV_APBH_CTRL0_CLKGATE_CHANNEL__##e)
+#define BFM_APBH_CTRL0_CLKGATE_CHANNEL_V(v)     BM_APBH_CTRL0_CLKGATE_CHANNEL
+#define BP_APBH_CTRL0_FREEZE_CHANNEL            0
+#define BM_APBH_CTRL0_FREEZE_CHANNEL            0xff
+#define BV_APBH_CTRL0_FREEZE_CHANNEL__HWECC     0x1
+#define BV_APBH_CTRL0_FREEZE_CHANNEL__SSP       0x2
+#define BV_APBH_CTRL0_FREEZE_CHANNEL__SRC       0x4
+#define BV_APBH_CTRL0_FREEZE_CHANNEL__DEST      0x8
+#define BV_APBH_CTRL0_FREEZE_CHANNEL__ATA       0x10
+#define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND0     0x10
+#define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND1     0x20
+#define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND2     0x30
+#define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND3     0x40
+#define BF_APBH_CTRL0_FREEZE_CHANNEL(v)         (((v) & 0xff) << 0)
+#define BFM_APBH_CTRL0_FREEZE_CHANNEL(v)        BM_APBH_CTRL0_FREEZE_CHANNEL
+#define BF_APBH_CTRL0_FREEZE_CHANNEL_V(e)       BF_APBH_CTRL0_FREEZE_CHANNEL(BV_APBH_CTRL0_FREEZE_CHANNEL__##e)
+#define BFM_APBH_CTRL0_FREEZE_CHANNEL_V(v)      BM_APBH_CTRL0_FREEZE_CHANNEL
+
+#define HW_APBH_CTRL1                           HW(APBH_CTRL1)
+#define HWA_APBH_CTRL1                          (0x80004000 + 0x10)
+#define HWT_APBH_CTRL1                          HWIO_32_RW
+#define HWN_APBH_CTRL1                          APBH_CTRL1
+#define HWI_APBH_CTRL1                          
+#define HW_APBH_CTRL1_SET                       HW(APBH_CTRL1_SET)
+#define HWA_APBH_CTRL1_SET                      (HWA_APBH_CTRL1 + 0x4)
+#define HWT_APBH_CTRL1_SET                      HWIO_32_WO
+#define HWN_APBH_CTRL1_SET                      APBH_CTRL1
+#define HWI_APBH_CTRL1_SET                      
+#define HW_APBH_CTRL1_CLR                       HW(APBH_CTRL1_CLR)
+#define HWA_APBH_CTRL1_CLR                      (HWA_APBH_CTRL1 + 0x8)
+#define HWT_APBH_CTRL1_CLR                      HWIO_32_WO
+#define HWN_APBH_CTRL1_CLR                      APBH_CTRL1
+#define HWI_APBH_CTRL1_CLR                      
+#define HW_APBH_CTRL1_TOG                       HW(APBH_CTRL1_TOG)
+#define HWA_APBH_CTRL1_TOG                      (HWA_APBH_CTRL1 + 0xc)
+#define HWT_APBH_CTRL1_TOG                      HWIO_32_WO
+#define HWN_APBH_CTRL1_TOG                      APBH_CTRL1
+#define HWI_APBH_CTRL1_TOG                      
+#define BP_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN        16
+#define BM_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN        0xff0000
+#define BF_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN(v)     (((v) & 0xff) << 16)
+#define BFM_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN(v)    BM_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN
+#define BF_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_V(e)   BF_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN(BV_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN__##e)
+#define BFM_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_V(v)  BM_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN
+#define BP_APBH_CTRL1_CH_CMDCMPLT_IRQ           0
+#define BM_APBH_CTRL1_CH_CMDCMPLT_IRQ           0xff
+#define BF_APBH_CTRL1_CH_CMDCMPLT_IRQ(v)        (((v) & 0xff) << 0)
+#define BFM_APBH_CTRL1_CH_CMDCMPLT_IRQ(v)       BM_APBH_CTRL1_CH_CMDCMPLT_IRQ
+#define BF_APBH_CTRL1_CH_CMDCMPLT_IRQ_V(e)      BF_APBH_CTRL1_CH_CMDCMPLT_IRQ(BV_APBH_CTRL1_CH_CMDCMPLT_IRQ__##e)
+#define BFM_APBH_CTRL1_CH_CMDCMPLT_IRQ_V(v)     BM_APBH_CTRL1_CH_CMDCMPLT_IRQ
+
+#define HW_APBH_DEVSEL              HW(APBH_DEVSEL)
+#define HWA_APBH_DEVSEL             (0x80004000 + 0x20)
+#define HWT_APBH_DEVSEL             HWIO_32_RW
+#define HWN_APBH_DEVSEL             APBH_DEVSEL
+#define HWI_APBH_DEVSEL             
+#define BP_APBH_DEVSEL_CH7          28
+#define BM_APBH_DEVSEL_CH7          0xf0000000
+#define BF_APBH_DEVSEL_CH7(v)       (((v) & 0xf) << 28)
+#define BFM_APBH_DEVSEL_CH7(v)      BM_APBH_DEVSEL_CH7
+#define BF_APBH_DEVSEL_CH7_V(e)     BF_APBH_DEVSEL_CH7(BV_APBH_DEVSEL_CH7__##e)
+#define BFM_APBH_DEVSEL_CH7_V(v)    BM_APBH_DEVSEL_CH7
+#define BP_APBH_DEVSEL_CH6          24
+#define BM_APBH_DEVSEL_CH6          0xf000000
+#define BF_APBH_DEVSEL_CH6(v)       (((v) & 0xf) << 24)
+#define BFM_APBH_DEVSEL_CH6(v)      BM_APBH_DEVSEL_CH6
+#define BF_APBH_DEVSEL_CH6_V(e)     BF_APBH_DEVSEL_CH6(BV_APBH_DEVSEL_CH6__##e)
+#define BFM_APBH_DEVSEL_CH6_V(v)    BM_APBH_DEVSEL_CH6
+#define BP_APBH_DEVSEL_CH5          20
+#define BM_APBH_DEVSEL_CH5          0xf00000
+#define BF_APBH_DEVSEL_CH5(v)       (((v) & 0xf) << 20)
+#define BFM_APBH_DEVSEL_CH5(v)      BM_APBH_DEVSEL_CH5
+#define BF_APBH_DEVSEL_CH5_V(e)     BF_APBH_DEVSEL_CH5(BV_APBH_DEVSEL_CH5__##e)
+#define BFM_APBH_DEVSEL_CH5_V(v)    BM_APBH_DEVSEL_CH5
+#define BP_APBH_DEVSEL_CH4          16
+#define BM_APBH_DEVSEL_CH4          0xf0000
+#define BF_APBH_DEVSEL_CH4(v)       (((v) & 0xf) << 16)
+#define BFM_APBH_DEVSEL_CH4(v)      BM_APBH_DEVSEL_CH4
+#define BF_APBH_DEVSEL_CH4_V(e)     BF_APBH_DEVSEL_CH4(BV_APBH_DEVSEL_CH4__##e)
+#define BFM_APBH_DEVSEL_CH4_V(v)    BM_APBH_DEVSEL_CH4
+#define BP_APBH_DEVSEL_CH3          12
+#define BM_APBH_DEVSEL_CH3          0xf000
+#define BF_APBH_DEVSEL_CH3(v)       (((v) & 0xf) << 12)
+#define BFM_APBH_DEVSEL_CH3(v)      BM_APBH_DEVSEL_CH3
+#define BF_APBH_DEVSEL_CH3_V(e)     BF_APBH_DEVSEL_CH3(BV_APBH_DEVSEL_CH3__##e)
+#define BFM_APBH_DEVSEL_CH3_V(v)    BM_APBH_DEVSEL_CH3
+#define BP_APBH_DEVSEL_CH2          8
+#define BM_APBH_DEVSEL_CH2          0xf00
+#define BF_APBH_DEVSEL_CH2(v)       (((v) & 0xf) << 8)
+#define BFM_APBH_DEVSEL_CH2(v)      BM_APBH_DEVSEL_CH2
+#define BF_APBH_DEVSEL_CH2_V(e)     BF_APBH_DEVSEL_CH2(BV_APBH_DEVSEL_CH2__##e)
+#define BFM_APBH_DEVSEL_CH2_V(v)    BM_APBH_DEVSEL_CH2
+#define BP_APBH_DEVSEL_CH1          4
+#define BM_APBH_DEVSEL_CH1          0xf0
+#define BF_APBH_DEVSEL_CH1(v)       (((v) & 0xf) << 4)
+#define BFM_APBH_DEVSEL_CH1(v)      BM_APBH_DEVSEL_CH1
+#define BF_APBH_DEVSEL_CH1_V(e)     BF_APBH_DEVSEL_CH1(BV_APBH_DEVSEL_CH1__##e)
+#define BFM_APBH_DEVSEL_CH1_V(v)    BM_APBH_DEVSEL_CH1
+#define BP_APBH_DEVSEL_CH0          0
+#define BM_APBH_DEVSEL_CH0          0xf
+#define BF_APBH_DEVSEL_CH0(v)       (((v) & 0xf) << 0)
+#define BFM_APBH_DEVSEL_CH0(v)      BM_APBH_DEVSEL_CH0
+#define BF_APBH_DEVSEL_CH0_V(e)     BF_APBH_DEVSEL_CH0(BV_APBH_DEVSEL_CH0__##e)
+#define BFM_APBH_DEVSEL_CH0_V(v)    BM_APBH_DEVSEL_CH0
+
+#define HW_APBH_CHn_DEBUG2(_n1)             HW(APBH_CHn_DEBUG2(_n1))
+#define HWA_APBH_CHn_DEBUG2(_n1)            (0x80004000 + 0x90 + (_n1) * 0x70)
+#define HWT_APBH_CHn_DEBUG2(_n1)            HWIO_32_RW
+#define HWN_APBH_CHn_DEBUG2(_n1)            APBH_CHn_DEBUG2
+#define HWI_APBH_CHn_DEBUG2(_n1)            (_n1)
+#define BP_APBH_CHn_DEBUG2_APB_BYTES        16
+#define BM_APBH_CHn_DEBUG2_APB_BYTES        0xffff0000
+#define BF_APBH_CHn_DEBUG2_APB_BYTES(v)     (((v) & 0xffff) << 16)
+#define BFM_APBH_CHn_DEBUG2_APB_BYTES(v)    BM_APBH_CHn_DEBUG2_APB_BYTES
+#define BF_APBH_CHn_DEBUG2_APB_BYTES_V(e)   BF_APBH_CHn_DEBUG2_APB_BYTES(BV_APBH_CHn_DEBUG2_APB_BYTES__##e)
+#define BFM_APBH_CHn_DEBUG2_APB_BYTES_V(v)  BM_APBH_CHn_DEBUG2_APB_BYTES
+#define BP_APBH_CHn_DEBUG2_AHB_BYTES        0
+#define BM_APBH_CHn_DEBUG2_AHB_BYTES        0xffff
+#define BF_APBH_CHn_DEBUG2_AHB_BYTES(v)     (((v) & 0xffff) << 0)
+#define BFM_APBH_CHn_DEBUG2_AHB_BYTES(v)    BM_APBH_CHn_DEBUG2_AHB_BYTES
+#define BF_APBH_CHn_DEBUG2_AHB_BYTES_V(e)   BF_APBH_CHn_DEBUG2_AHB_BYTES(BV_APBH_CHn_DEBUG2_AHB_BYTES__##e)
+#define BFM_APBH_CHn_DEBUG2_AHB_BYTES_V(v)  BM_APBH_CHn_DEBUG2_AHB_BYTES
+
+#define HW_APBH_CHn_CURCMDAR(_n1)           HW(APBH_CHn_CURCMDAR(_n1))
+#define HWA_APBH_CHn_CURCMDAR(_n1)          (0x80004000 + 0x30 + (_n1) * 0x70)
+#define HWT_APBH_CHn_CURCMDAR(_n1)          HWIO_32_RW
+#define HWN_APBH_CHn_CURCMDAR(_n1)          APBH_CHn_CURCMDAR
+#define HWI_APBH_CHn_CURCMDAR(_n1)          (_n1)
+#define BP_APBH_CHn_CURCMDAR_CMD_ADDR       0
+#define BM_APBH_CHn_CURCMDAR_CMD_ADDR       0xffffffff
+#define BF_APBH_CHn_CURCMDAR_CMD_ADDR(v)    (((v) & 0xffffffff) << 0)
+#define BFM_APBH_CHn_CURCMDAR_CMD_ADDR(v)   BM_APBH_CHn_CURCMDAR_CMD_ADDR
+#define BF_APBH_CHn_CURCMDAR_CMD_ADDR_V(e)  BF_APBH_CHn_CURCMDAR_CMD_ADDR(BV_APBH_CHn_CURCMDAR_CMD_ADDR__##e)
+#define BFM_APBH_CHn_CURCMDAR_CMD_ADDR_V(v) BM_APBH_CHn_CURCMDAR_CMD_ADDR
+
+#define HW_APBH_CHn_BAR(_n1)            HW(APBH_CHn_BAR(_n1))
+#define HWA_APBH_CHn_BAR(_n1)           (0x80004000 + 0x60 + (_n1) * 0x70)
+#define HWT_APBH_CHn_BAR(_n1)           HWIO_32_RW
+#define HWN_APBH_CHn_BAR(_n1)           APBH_CHn_BAR
+#define HWI_APBH_CHn_BAR(_n1)           (_n1)
+#define BP_APBH_CHn_BAR_ADDRESS         0
+#define BM_APBH_CHn_BAR_ADDRESS         0xffffffff
+#define BF_APBH_CHn_BAR_ADDRESS(v)      (((v) & 0xffffffff) << 0)
+#define BFM_APBH_CHn_BAR_ADDRESS(v)     BM_APBH_CHn_BAR_ADDRESS
+#define BF_APBH_CHn_BAR_ADDRESS_V(e)    BF_APBH_CHn_BAR_ADDRESS(BV_APBH_CHn_BAR_ADDRESS__##e)
+#define BFM_APBH_CHn_BAR_ADDRESS_V(v)   BM_APBH_CHn_BAR_ADDRESS
+
+#define HW_APBH_CHn_CMD(_n1)                    HW(APBH_CHn_CMD(_n1))
+#define HWA_APBH_CHn_CMD(_n1)                   (0x80004000 + 0x50 + (_n1) * 0x70)
+#define HWT_APBH_CHn_CMD(_n1)                   HWIO_32_RW
+#define HWN_APBH_CHn_CMD(_n1)                   APBH_CHn_CMD
+#define HWI_APBH_CHn_CMD(_n1)                   (_n1)
+#define BP_APBH_CHn_CMD_XFER_COUNT              16
+#define BM_APBH_CHn_CMD_XFER_COUNT              0xffff0000
+#define BF_APBH_CHn_CMD_XFER_COUNT(v)           (((v) & 0xffff) << 16)
+#define BFM_APBH_CHn_CMD_XFER_COUNT(v)          BM_APBH_CHn_CMD_XFER_COUNT
+#define BF_APBH_CHn_CMD_XFER_COUNT_V(e)         BF_APBH_CHn_CMD_XFER_COUNT(BV_APBH_CHn_CMD_XFER_COUNT__##e)
+#define BFM_APBH_CHn_CMD_XFER_COUNT_V(v)        BM_APBH_CHn_CMD_XFER_COUNT
+#define BP_APBH_CHn_CMD_CMDWORDS                12
+#define BM_APBH_CHn_CMD_CMDWORDS                0xf000
+#define BF_APBH_CHn_CMD_CMDWORDS(v)             (((v) & 0xf) << 12)
+#define BFM_APBH_CHn_CMD_CMDWORDS(v)            BM_APBH_CHn_CMD_CMDWORDS
+#define BF_APBH_CHn_CMD_CMDWORDS_V(e)           BF_APBH_CHn_CMD_CMDWORDS(BV_APBH_CHn_CMD_CMDWORDS__##e)
+#define BFM_APBH_CHn_CMD_CMDWORDS_V(v)          BM_APBH_CHn_CMD_CMDWORDS
+#define BP_APBH_CHn_CMD_WAIT4ENDCMD             7
+#define BM_APBH_CHn_CMD_WAIT4ENDCMD             0x80
+#define BF_APBH_CHn_CMD_WAIT4ENDCMD(v)          (((v) & 0x1) << 7)
+#define BFM_APBH_CHn_CMD_WAIT4ENDCMD(v)         BM_APBH_CHn_CMD_WAIT4ENDCMD
+#define BF_APBH_CHn_CMD_WAIT4ENDCMD_V(e)        BF_APBH_CHn_CMD_WAIT4ENDCMD(BV_APBH_CHn_CMD_WAIT4ENDCMD__##e)
+#define BFM_APBH_CHn_CMD_WAIT4ENDCMD_V(v)       BM_APBH_CHn_CMD_WAIT4ENDCMD
+#define BP_APBH_CHn_CMD_SEMAPHORE               6
+#define BM_APBH_CHn_CMD_SEMAPHORE               0x40
+#define BF_APBH_CHn_CMD_SEMAPHORE(v)            (((v) & 0x1) << 6)
+#define BFM_APBH_CHn_CMD_SEMAPHORE(v)           BM_APBH_CHn_CMD_SEMAPHORE
+#define BF_APBH_CHn_CMD_SEMAPHORE_V(e)          BF_APBH_CHn_CMD_SEMAPHORE(BV_APBH_CHn_CMD_SEMAPHORE__##e)
+#define BFM_APBH_CHn_CMD_SEMAPHORE_V(v)         BM_APBH_CHn_CMD_SEMAPHORE
+#define BP_APBH_CHn_CMD_NANDWAIT4READY          5
+#define BM_APBH_CHn_CMD_NANDWAIT4READY          0x20
+#define BF_APBH_CHn_CMD_NANDWAIT4READY(v)       (((v) & 0x1) << 5)
+#define BFM_APBH_CHn_CMD_NANDWAIT4READY(v)      BM_APBH_CHn_CMD_NANDWAIT4READY
+#define BF_APBH_CHn_CMD_NANDWAIT4READY_V(e)     BF_APBH_CHn_CMD_NANDWAIT4READY(BV_APBH_CHn_CMD_NANDWAIT4READY__##e)
+#define BFM_APBH_CHn_CMD_NANDWAIT4READY_V(v)    BM_APBH_CHn_CMD_NANDWAIT4READY
+#define BP_APBH_CHn_CMD_NANDLOCK                4
+#define BM_APBH_CHn_CMD_NANDLOCK                0x10
+#define BF_APBH_CHn_CMD_NANDLOCK(v)             (((v) & 0x1) << 4)
+#define BFM_APBH_CHn_CMD_NANDLOCK(v)            BM_APBH_CHn_CMD_NANDLOCK
+#define BF_APBH_CHn_CMD_NANDLOCK_V(e)           BF_APBH_CHn_CMD_NANDLOCK(BV_APBH_CHn_CMD_NANDLOCK__##e)
+#define BFM_APBH_CHn_CMD_NANDLOCK_V(v)          BM_APBH_CHn_CMD_NANDLOCK
+#define BP_APBH_CHn_CMD_IRQONCMPLT              3
+#define BM_APBH_CHn_CMD_IRQONCMPLT              0x8
+#define BF_APBH_CHn_CMD_IRQONCMPLT(v)           (((v) & 0x1) << 3)
+#define BFM_APBH_CHn_CMD_IRQONCMPLT(v)          BM_APBH_CHn_CMD_IRQONCMPLT
+#define BF_APBH_CHn_CMD_IRQONCMPLT_V(e)         BF_APBH_CHn_CMD_IRQONCMPLT(BV_APBH_CHn_CMD_IRQONCMPLT__##e)
+#define BFM_APBH_CHn_CMD_IRQONCMPLT_V(v)        BM_APBH_CHn_CMD_IRQONCMPLT
+#define BP_APBH_CHn_CMD_CHAIN                   2
+#define BM_APBH_CHn_CMD_CHAIN                   0x4
+#define BF_APBH_CHn_CMD_CHAIN(v)                (((v) & 0x1) << 2)
+#define BFM_APBH_CHn_CMD_CHAIN(v)               BM_APBH_CHn_CMD_CHAIN
+#define BF_APBH_CHn_CMD_CHAIN_V(e)              BF_APBH_CHn_CMD_CHAIN(BV_APBH_CHn_CMD_CHAIN__##e)
+#define BFM_APBH_CHn_CMD_CHAIN_V(v)             BM_APBH_CHn_CMD_CHAIN
+#define BP_APBH_CHn_CMD_COMMAND                 0
+#define BM_APBH_CHn_CMD_COMMAND                 0x3
+#define BV_APBH_CHn_CMD_COMMAND__NO_DMA_XFER    0x0
+#define BV_APBH_CHn_CMD_COMMAND__DMA_WRITE      0x1
+#define BV_APBH_CHn_CMD_COMMAND__DMA_READ       0x2
+#define BV_APBH_CHn_CMD_COMMAND__DMA_SENSE      0x3
+#define BF_APBH_CHn_CMD_COMMAND(v)              (((v) & 0x3) << 0)
+#define BFM_APBH_CHn_CMD_COMMAND(v)             BM_APBH_CHn_CMD_COMMAND
+#define BF_APBH_CHn_CMD_COMMAND_V(e)            BF_APBH_CHn_CMD_COMMAND(BV_APBH_CHn_CMD_COMMAND__##e)
+#define BFM_APBH_CHn_CMD_COMMAND_V(v)           BM_APBH_CHn_CMD_COMMAND
+
+#define HW_APBH_CHn_NXTCMDAR(_n1)           HW(APBH_CHn_NXTCMDAR(_n1))
+#define HWA_APBH_CHn_NXTCMDAR(_n1)          (0x80004000 + 0x40 + (_n1) * 0x70)
+#define HWT_APBH_CHn_NXTCMDAR(_n1)          HWIO_32_RW
+#define HWN_APBH_CHn_NXTCMDAR(_n1)          APBH_CHn_NXTCMDAR
+#define HWI_APBH_CHn_NXTCMDAR(_n1)          (_n1)
+#define BP_APBH_CHn_NXTCMDAR_CMD_ADDR       0
+#define BM_APBH_CHn_NXTCMDAR_CMD_ADDR       0xffffffff
+#define BF_APBH_CHn_NXTCMDAR_CMD_ADDR(v)    (((v) & 0xffffffff) << 0)
+#define BFM_APBH_CHn_NXTCMDAR_CMD_ADDR(v)   BM_APBH_CHn_NXTCMDAR_CMD_ADDR
+#define BF_APBH_CHn_NXTCMDAR_CMD_ADDR_V(e)  BF_APBH_CHn_NXTCMDAR_CMD_ADDR(BV_APBH_CHn_NXTCMDAR_CMD_ADDR__##e)
+#define BFM_APBH_CHn_NXTCMDAR_CMD_ADDR_V(v) BM_APBH_CHn_NXTCMDAR_CMD_ADDR
+
+#define HW_APBH_CHn_SEMA(_n1)                   HW(APBH_CHn_SEMA(_n1))
+#define HWA_APBH_CHn_SEMA(_n1)                  (0x80004000 + 0x70 + (_n1) * 0x70)
+#define HWT_APBH_CHn_SEMA(_n1)                  HWIO_32_RW
+#define HWN_APBH_CHn_SEMA(_n1)                  APBH_CHn_SEMA
+#define HWI_APBH_CHn_SEMA(_n1)                  (_n1)
+#define BP_APBH_CHn_SEMA_PHORE                  16
+#define BM_APBH_CHn_SEMA_PHORE                  0xff0000
+#define BF_APBH_CHn_SEMA_PHORE(v)               (((v) & 0xff) << 16)
+#define BFM_APBH_CHn_SEMA_PHORE(v)              BM_APBH_CHn_SEMA_PHORE
+#define BF_APBH_CHn_SEMA_PHORE_V(e)             BF_APBH_CHn_SEMA_PHORE(BV_APBH_CHn_SEMA_PHORE__##e)
+#define BFM_APBH_CHn_SEMA_PHORE_V(v)            BM_APBH_CHn_SEMA_PHORE
+#define BP_APBH_CHn_SEMA_INCREMENT_SEMA         0
+#define BM_APBH_CHn_SEMA_INCREMENT_SEMA         0xff
+#define BF_APBH_CHn_SEMA_INCREMENT_SEMA(v)      (((v) & 0xff) << 0)
+#define BFM_APBH_CHn_SEMA_INCREMENT_SEMA(v)     BM_APBH_CHn_SEMA_INCREMENT_SEMA
+#define BF_APBH_CHn_SEMA_INCREMENT_SEMA_V(e)    BF_APBH_CHn_SEMA_INCREMENT_SEMA(BV_APBH_CHn_SEMA_INCREMENT_SEMA__##e)
+#define BFM_APBH_CHn_SEMA_INCREMENT_SEMA_V(v)   BM_APBH_CHn_SEMA_INCREMENT_SEMA
+
+#define HW_APBH_CHn_DEBUG1(_n1)                         HW(APBH_CHn_DEBUG1(_n1))
+#define HWA_APBH_CHn_DEBUG1(_n1)                        (0x80004000 + 0x80 + (_n1) * 0x70)
+#define HWT_APBH_CHn_DEBUG1(_n1)                        HWIO_32_RW
+#define HWN_APBH_CHn_DEBUG1(_n1)                        APBH_CHn_DEBUG1
+#define HWI_APBH_CHn_DEBUG1(_n1)                        (_n1)
+#define BP_APBH_CHn_DEBUG1_REQ                          31
+#define BM_APBH_CHn_DEBUG1_REQ                          0x80000000
+#define BF_APBH_CHn_DEBUG1_REQ(v)                       (((v) & 0x1) << 31)
+#define BFM_APBH_CHn_DEBUG1_REQ(v)                      BM_APBH_CHn_DEBUG1_REQ
+#define BF_APBH_CHn_DEBUG1_REQ_V(e)                     BF_APBH_CHn_DEBUG1_REQ(BV_APBH_CHn_DEBUG1_REQ__##e)
+#define BFM_APBH_CHn_DEBUG1_REQ_V(v)                    BM_APBH_CHn_DEBUG1_REQ
+#define BP_APBH_CHn_DEBUG1_BURST                        30
+#define BM_APBH_CHn_DEBUG1_BURST                        0x40000000
+#define BF_APBH_CHn_DEBUG1_BURST(v)                     (((v) & 0x1) << 30)
+#define BFM_APBH_CHn_DEBUG1_BURST(v)                    BM_APBH_CHn_DEBUG1_BURST
+#define BF_APBH_CHn_DEBUG1_BURST_V(e)                   BF_APBH_CHn_DEBUG1_BURST(BV_APBH_CHn_DEBUG1_BURST__##e)
+#define BFM_APBH_CHn_DEBUG1_BURST_V(v)                  BM_APBH_CHn_DEBUG1_BURST
+#define BP_APBH_CHn_DEBUG1_KICK                         29
+#define BM_APBH_CHn_DEBUG1_KICK                         0x20000000
+#define BF_APBH_CHn_DEBUG1_KICK(v)                      (((v) & 0x1) << 29)
+#define BFM_APBH_CHn_DEBUG1_KICK(v)                     BM_APBH_CHn_DEBUG1_KICK
+#define BF_APBH_CHn_DEBUG1_KICK_V(e)                    BF_APBH_CHn_DEBUG1_KICK(BV_APBH_CHn_DEBUG1_KICK__##e)
+#define BFM_APBH_CHn_DEBUG1_KICK_V(v)                   BM_APBH_CHn_DEBUG1_KICK
+#define BP_APBH_CHn_DEBUG1_END                          28
+#define BM_APBH_CHn_DEBUG1_END                          0x10000000
+#define BF_APBH_CHn_DEBUG1_END(v)                       (((v) & 0x1) << 28)
+#define BFM_APBH_CHn_DEBUG1_END(v)                      BM_APBH_CHn_DEBUG1_END
+#define BF_APBH_CHn_DEBUG1_END_V(e)                     BF_APBH_CHn_DEBUG1_END(BV_APBH_CHn_DEBUG1_END__##e)
+#define BFM_APBH_CHn_DEBUG1_END_V(v)                    BM_APBH_CHn_DEBUG1_END
+#define BP_APBH_CHn_DEBUG1_RSVD2                        25
+#define BM_APBH_CHn_DEBUG1_RSVD2                        0xe000000
+#define BF_APBH_CHn_DEBUG1_RSVD2(v)                     (((v) & 0x7) << 25)
+#define BFM_APBH_CHn_DEBUG1_RSVD2(v)                    BM_APBH_CHn_DEBUG1_RSVD2
+#define BF_APBH_CHn_DEBUG1_RSVD2_V(e)                   BF_APBH_CHn_DEBUG1_RSVD2(BV_APBH_CHn_DEBUG1_RSVD2__##e)
+#define BFM_APBH_CHn_DEBUG1_RSVD2_V(v)                  BM_APBH_CHn_DEBUG1_RSVD2
+#define BP_APBH_CHn_DEBUG1_NEXTCMDADDRVALID             24
+#define BM_APBH_CHn_DEBUG1_NEXTCMDADDRVALID             0x1000000
+#define BF_APBH_CHn_DEBUG1_NEXTCMDADDRVALID(v)          (((v) & 0x1) << 24)
+#define BFM_APBH_CHn_DEBUG1_NEXTCMDADDRVALID(v)         BM_APBH_CHn_DEBUG1_NEXTCMDADDRVALID
+#define BF_APBH_CHn_DEBUG1_NEXTCMDADDRVALID_V(e)        BF_APBH_CHn_DEBUG1_NEXTCMDADDRVALID(BV_APBH_CHn_DEBUG1_NEXTCMDADDRVALID__##e)
+#define BFM_APBH_CHn_DEBUG1_NEXTCMDADDRVALID_V(v)       BM_APBH_CHn_DEBUG1_NEXTCMDADDRVALID
+#define BP_APBH_CHn_DEBUG1_RD_FIFO_EMPTY                23
+#define BM_APBH_CHn_DEBUG1_RD_FIFO_EMPTY                0x800000
+#define BF_APBH_CHn_DEBUG1_RD_FIFO_EMPTY(v)             (((v) & 0x1) << 23)
+#define BFM_APBH_CHn_DEBUG1_RD_FIFO_EMPTY(v)            BM_APBH_CHn_DEBUG1_RD_FIFO_EMPTY
+#define BF_APBH_CHn_DEBUG1_RD_FIFO_EMPTY_V(e)           BF_APBH_CHn_DEBUG1_RD_FIFO_EMPTY(BV_APBH_CHn_DEBUG1_RD_FIFO_EMPTY__##e)
+#define BFM_APBH_CHn_DEBUG1_RD_FIFO_EMPTY_V(v)          BM_APBH_CHn_DEBUG1_RD_FIFO_EMPTY
+#define BP_APBH_CHn_DEBUG1_RD_FIFO_FULL                 22
+#define BM_APBH_CHn_DEBUG1_RD_FIFO_FULL                 0x400000
+#define BF_APBH_CHn_DEBUG1_RD_FIFO_FULL(v)              (((v) & 0x1) << 22)
+#define BFM_APBH_CHn_DEBUG1_RD_FIFO_FULL(v)             BM_APBH_CHn_DEBUG1_RD_FIFO_FULL
+#define BF_APBH_CHn_DEBUG1_RD_FIFO_FULL_V(e)            BF_APBH_CHn_DEBUG1_RD_FIFO_FULL(BV_APBH_CHn_DEBUG1_RD_FIFO_FULL__##e)
+#define BFM_APBH_CHn_DEBUG1_RD_FIFO_FULL_V(v)           BM_APBH_CHn_DEBUG1_RD_FIFO_FULL
+#define BP_APBH_CHn_DEBUG1_WR_FIFO_EMPTY                21
+#define BM_APBH_CHn_DEBUG1_WR_FIFO_EMPTY                0x200000
+#define BF_APBH_CHn_DEBUG1_WR_FIFO_EMPTY(v)             (((v) & 0x1) << 21)
+#define BFM_APBH_CHn_DEBUG1_WR_FIFO_EMPTY(v)            BM_APBH_CHn_DEBUG1_WR_FIFO_EMPTY
+#define BF_APBH_CHn_DEBUG1_WR_FIFO_EMPTY_V(e)           BF_APBH_CHn_DEBUG1_WR_FIFO_EMPTY(BV_APBH_CHn_DEBUG1_WR_FIFO_EMPTY__##e)
+#define BFM_APBH_CHn_DEBUG1_WR_FIFO_EMPTY_V(v)          BM_APBH_CHn_DEBUG1_WR_FIFO_EMPTY
+#define BP_APBH_CHn_DEBUG1_WR_FIFO_FULL                 20
+#define BM_APBH_CHn_DEBUG1_WR_FIFO_FULL                 0x100000
+#define BF_APBH_CHn_DEBUG1_WR_FIFO_FULL(v)              (((v) & 0x1) << 20)
+#define BFM_APBH_CHn_DEBUG1_WR_FIFO_FULL(v)             BM_APBH_CHn_DEBUG1_WR_FIFO_FULL
+#define BF_APBH_CHn_DEBUG1_WR_FIFO_FULL_V(e)            BF_APBH_CHn_DEBUG1_WR_FIFO_FULL(BV_APBH_CHn_DEBUG1_WR_FIFO_FULL__##e)
+#define BFM_APBH_CHn_DEBUG1_WR_FIFO_FULL_V(v)           BM_APBH_CHn_DEBUG1_WR_FIFO_FULL
+#define BP_APBH_CHn_DEBUG1_RSVD1                        5
+#define BM_APBH_CHn_DEBUG1_RSVD1                        0xfffe0
+#define BF_APBH_CHn_DEBUG1_RSVD1(v)                     (((v) & 0x7fff) << 5)
+#define BFM_APBH_CHn_DEBUG1_RSVD1(v)                    BM_APBH_CHn_DEBUG1_RSVD1
+#define BF_APBH_CHn_DEBUG1_RSVD1_V(e)                   BF_APBH_CHn_DEBUG1_RSVD1(BV_APBH_CHn_DEBUG1_RSVD1__##e)
+#define BFM_APBH_CHn_DEBUG1_RSVD1_V(v)                  BM_APBH_CHn_DEBUG1_RSVD1
+#define BP_APBH_CHn_DEBUG1_STATEMACHINE                 0
+#define BM_APBH_CHn_DEBUG1_STATEMACHINE                 0x1f
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__IDLE           0x0
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD1       0x1
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD3       0x2
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD2       0x3
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__XFER_DECODE    0x4
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_WAIT       0x5
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD4       0x6
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__PIO_REQ        0x7
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_FLUSH     0x8
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_WAIT      0x9
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__WRITE          0xc
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_REQ       0xd
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__CHECK_CHAIN    0xe
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__XFER_COMPLETE  0xf
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__WAIT_END       0x15
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__WRITE_WAIT     0x1c
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__CHECK_WAIT     0x1e
+#define BF_APBH_CHn_DEBUG1_STATEMACHINE(v)              (((v) & 0x1f) << 0)
+#define BFM_APBH_CHn_DEBUG1_STATEMACHINE(v)             BM_APBH_CHn_DEBUG1_STATEMACHINE
+#define BF_APBH_CHn_DEBUG1_STATEMACHINE_V(e)            BF_APBH_CHn_DEBUG1_STATEMACHINE(BV_APBH_CHn_DEBUG1_STATEMACHINE__##e)
+#define BFM_APBH_CHn_DEBUG1_STATEMACHINE_V(v)           BM_APBH_CHn_DEBUG1_STATEMACHINE
+
+#endif /* __HEADERGEN_STMP3600_APBH_H__*/
diff --git a/firmware/target/arm/imx233/regs/stmp3600/apbx.h b/firmware/target/arm/imx233/regs/stmp3600/apbx.h
new file mode 100644
index 0000000000..8ceeefe202
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3600/apbx.h
@@ -0,0 +1,401 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * stmp3600 version: 2.4.0
+ * stmp3600 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_STMP3600_APBX_H__
+#define __HEADERGEN_STMP3600_APBX_H__
+
+#define HW_APBX_CTRL0                           HW(APBX_CTRL0)
+#define HWA_APBX_CTRL0                          (0x80024000 + 0x0)
+#define HWT_APBX_CTRL0                          HWIO_32_RW
+#define HWN_APBX_CTRL0                          APBX_CTRL0
+#define HWI_APBX_CTRL0                          
+#define HW_APBX_CTRL0_SET                       HW(APBX_CTRL0_SET)
+#define HWA_APBX_CTRL0_SET                      (HWA_APBX_CTRL0 + 0x4)
+#define HWT_APBX_CTRL0_SET                      HWIO_32_WO
+#define HWN_APBX_CTRL0_SET                      APBX_CTRL0
+#define HWI_APBX_CTRL0_SET                      
+#define HW_APBX_CTRL0_CLR                       HW(APBX_CTRL0_CLR)
+#define HWA_APBX_CTRL0_CLR                      (HWA_APBX_CTRL0 + 0x8)
+#define HWT_APBX_CTRL0_CLR                      HWIO_32_WO
+#define HWN_APBX_CTRL0_CLR                      APBX_CTRL0
+#define HWI_APBX_CTRL0_CLR                      
+#define HW_APBX_CTRL0_TOG                       HW(APBX_CTRL0_TOG)
+#define HWA_APBX_CTRL0_TOG                      (HWA_APBX_CTRL0 + 0xc)
+#define HWT_APBX_CTRL0_TOG                      HWIO_32_WO
+#define HWN_APBX_CTRL0_TOG                      APBX_CTRL0
+#define HWI_APBX_CTRL0_TOG                      
+#define BP_APBX_CTRL0_SFTRST                    31
+#define BM_APBX_CTRL0_SFTRST                    0x80000000
+#define BF_APBX_CTRL0_SFTRST(v)                 (((v) & 0x1) << 31)
+#define BFM_APBX_CTRL0_SFTRST(v)                BM_APBX_CTRL0_SFTRST
+#define BF_APBX_CTRL0_SFTRST_V(e)               BF_APBX_CTRL0_SFTRST(BV_APBX_CTRL0_SFTRST__##e)
+#define BFM_APBX_CTRL0_SFTRST_V(v)              BM_APBX_CTRL0_SFTRST
+#define BP_APBX_CTRL0_CLKGATE                   30
+#define BM_APBX_CTRL0_CLKGATE                   0x40000000
+#define BF_APBX_CTRL0_CLKGATE(v)                (((v) & 0x1) << 30)
+#define BFM_APBX_CTRL0_CLKGATE(v)               BM_APBX_CTRL0_CLKGATE
+#define BF_APBX_CTRL0_CLKGATE_V(e)              BF_APBX_CTRL0_CLKGATE(BV_APBX_CTRL0_CLKGATE__##e)
+#define BFM_APBX_CTRL0_CLKGATE_V(v)             BM_APBX_CTRL0_CLKGATE
+#define BP_APBX_CTRL0_RESET_CHANNEL             16
+#define BM_APBX_CTRL0_RESET_CHANNEL             0xff0000
+#define BV_APBX_CTRL0_RESET_CHANNEL__AUDIOIN    0x1
+#define BV_APBX_CTRL0_RESET_CHANNEL__AUDIOOUT   0x2
+#define BV_APBX_CTRL0_RESET_CHANNEL__SPDIF_TX   0x4
+#define BV_APBX_CTRL0_RESET_CHANNEL__I2C        0x8
+#define BV_APBX_CTRL0_RESET_CHANNEL__LCDIF      0x10
+#define BV_APBX_CTRL0_RESET_CHANNEL__DRI        0x20
+#define BV_APBX_CTRL0_RESET_CHANNEL__UART_RX    0x30
+#define BV_APBX_CTRL0_RESET_CHANNEL__IRDA_RX    0x30
+#define BV_APBX_CTRL0_RESET_CHANNEL__UART_TX    0x40
+#define BV_APBX_CTRL0_RESET_CHANNEL__IRDA_TX    0x40
+#define BF_APBX_CTRL0_RESET_CHANNEL(v)          (((v) & 0xff) << 16)
+#define BFM_APBX_CTRL0_RESET_CHANNEL(v)         BM_APBX_CTRL0_RESET_CHANNEL
+#define BF_APBX_CTRL0_RESET_CHANNEL_V(e)        BF_APBX_CTRL0_RESET_CHANNEL(BV_APBX_CTRL0_RESET_CHANNEL__##e)
+#define BFM_APBX_CTRL0_RESET_CHANNEL_V(v)       BM_APBX_CTRL0_RESET_CHANNEL
+#define BP_APBX_CTRL0_FREEZE_CHANNEL            0
+#define BM_APBX_CTRL0_FREEZE_CHANNEL            0xff
+#define BV_APBX_CTRL0_FREEZE_CHANNEL__AUDIOIN   0x1
+#define BV_APBX_CTRL0_FREEZE_CHANNEL__AUDIOOUT  0x2
+#define BV_APBX_CTRL0_FREEZE_CHANNEL__SPDIF_TX  0x4
+#define BV_APBX_CTRL0_FREEZE_CHANNEL__I2C       0x8
+#define BV_APBX_CTRL0_FREEZE_CHANNEL__LCDIF     0x10
+#define BV_APBX_CTRL0_FREEZE_CHANNEL__DRI       0x20
+#define BV_APBX_CTRL0_FREEZE_CHANNEL__UART_RX   0x30
+#define BV_APBX_CTRL0_FREEZE_CHANNEL__IRDA_RX   0x30
+#define BV_APBX_CTRL0_FREEZE_CHANNEL__UART_TX   0x40
+#define BV_APBX_CTRL0_FREEZE_CHANNEL__IRDA_TX   0x40
+#define BF_APBX_CTRL0_FREEZE_CHANNEL(v)         (((v) & 0xff) << 0)
+#define BFM_APBX_CTRL0_FREEZE_CHANNEL(v)        BM_APBX_CTRL0_FREEZE_CHANNEL
+#define BF_APBX_CTRL0_FREEZE_CHANNEL_V(e)       BF_APBX_CTRL0_FREEZE_CHANNEL(BV_APBX_CTRL0_FREEZE_CHANNEL__##e)
+#define BFM_APBX_CTRL0_FREEZE_CHANNEL_V(v)      BM_APBX_CTRL0_FREEZE_CHANNEL
+
+#define HW_APBX_CTRL1                           HW(APBX_CTRL1)
+#define HWA_APBX_CTRL1                          (0x80024000 + 0x10)
+#define HWT_APBX_CTRL1                          HWIO_32_RW
+#define HWN_APBX_CTRL1                          APBX_CTRL1
+#define HWI_APBX_CTRL1                          
+#define HW_APBX_CTRL1_SET                       HW(APBX_CTRL1_SET)
+#define HWA_APBX_CTRL1_SET                      (HWA_APBX_CTRL1 + 0x4)
+#define HWT_APBX_CTRL1_SET                      HWIO_32_WO
+#define HWN_APBX_CTRL1_SET                      APBX_CTRL1
+#define HWI_APBX_CTRL1_SET                      
+#define HW_APBX_CTRL1_CLR                       HW(APBX_CTRL1_CLR)
+#define HWA_APBX_CTRL1_CLR                      (HWA_APBX_CTRL1 + 0x8)
+#define HWT_APBX_CTRL1_CLR                      HWIO_32_WO
+#define HWN_APBX_CTRL1_CLR                      APBX_CTRL1
+#define HWI_APBX_CTRL1_CLR                      
+#define HW_APBX_CTRL1_TOG                       HW(APBX_CTRL1_TOG)
+#define HWA_APBX_CTRL1_TOG                      (HWA_APBX_CTRL1 + 0xc)
+#define HWT_APBX_CTRL1_TOG                      HWIO_32_WO
+#define HWN_APBX_CTRL1_TOG                      APBX_CTRL1
+#define HWI_APBX_CTRL1_TOG                      
+#define BP_APBX_CTRL1_CH_CMDCMPLT_IRQ_EN        16
+#define BM_APBX_CTRL1_CH_CMDCMPLT_IRQ_EN        0xff0000
+#define BF_APBX_CTRL1_CH_CMDCMPLT_IRQ_EN(v)     (((v) & 0xff) << 16)
+#define BFM_APBX_CTRL1_CH_CMDCMPLT_IRQ_EN(v)    BM_APBX_CTRL1_CH_CMDCMPLT_IRQ_EN
+#define BF_APBX_CTRL1_CH_CMDCMPLT_IRQ_EN_V(e)   BF_APBX_CTRL1_CH_CMDCMPLT_IRQ_EN(BV_APBX_CTRL1_CH_CMDCMPLT_IRQ_EN__##e)
+#define BFM_APBX_CTRL1_CH_CMDCMPLT_IRQ_EN_V(v)  BM_APBX_CTRL1_CH_CMDCMPLT_IRQ_EN
+#define BP_APBX_CTRL1_CH_CMDCMPLT_IRQ           0
+#define BM_APBX_CTRL1_CH_CMDCMPLT_IRQ           0xff
+#define BF_APBX_CTRL1_CH_CMDCMPLT_IRQ(v)        (((v) & 0xff) << 0)
+#define BFM_APBX_CTRL1_CH_CMDCMPLT_IRQ(v)       BM_APBX_CTRL1_CH_CMDCMPLT_IRQ
+#define BF_APBX_CTRL1_CH_CMDCMPLT_IRQ_V(e)      BF_APBX_CTRL1_CH_CMDCMPLT_IRQ(BV_APBX_CTRL1_CH_CMDCMPLT_IRQ__##e)
+#define BFM_APBX_CTRL1_CH_CMDCMPLT_IRQ_V(v)     BM_APBX_CTRL1_CH_CMDCMPLT_IRQ
+
+#define HW_APBX_DEVSEL                  HW(APBX_DEVSEL)
+#define HWA_APBX_DEVSEL                 (0x80024000 + 0x20)
+#define HWT_APBX_DEVSEL                 HWIO_32_RW
+#define HWN_APBX_DEVSEL                 APBX_DEVSEL
+#define HWI_APBX_DEVSEL                 
+#define BP_APBX_DEVSEL_CH7              28
+#define BM_APBX_DEVSEL_CH7              0xf0000000
+#define BV_APBX_DEVSEL_CH7__USE_UART    0x0
+#define BV_APBX_DEVSEL_CH7__USE_IRDA    0x1
+#define BF_APBX_DEVSEL_CH7(v)           (((v) & 0xf) << 28)
+#define BFM_APBX_DEVSEL_CH7(v)          BM_APBX_DEVSEL_CH7
+#define BF_APBX_DEVSEL_CH7_V(e)         BF_APBX_DEVSEL_CH7(BV_APBX_DEVSEL_CH7__##e)
+#define BFM_APBX_DEVSEL_CH7_V(v)        BM_APBX_DEVSEL_CH7
+#define BP_APBX_DEVSEL_CH6              24
+#define BM_APBX_DEVSEL_CH6              0xf000000
+#define BV_APBX_DEVSEL_CH6__USE_UART    0x0
+#define BV_APBX_DEVSEL_CH6__USE_IRDA    0x1
+#define BF_APBX_DEVSEL_CH6(v)           (((v) & 0xf) << 24)
+#define BFM_APBX_DEVSEL_CH6(v)          BM_APBX_DEVSEL_CH6
+#define BF_APBX_DEVSEL_CH6_V(e)         BF_APBX_DEVSEL_CH6(BV_APBX_DEVSEL_CH6__##e)
+#define BFM_APBX_DEVSEL_CH6_V(v)        BM_APBX_DEVSEL_CH6
+#define BP_APBX_DEVSEL_CH5              20
+#define BM_APBX_DEVSEL_CH5              0xf00000
+#define BF_APBX_DEVSEL_CH5(v)           (((v) & 0xf) << 20)
+#define BFM_APBX_DEVSEL_CH5(v)          BM_APBX_DEVSEL_CH5
+#define BF_APBX_DEVSEL_CH5_V(e)         BF_APBX_DEVSEL_CH5(BV_APBX_DEVSEL_CH5__##e)
+#define BFM_APBX_DEVSEL_CH5_V(v)        BM_APBX_DEVSEL_CH5
+#define BP_APBX_DEVSEL_CH4              16
+#define BM_APBX_DEVSEL_CH4              0xf0000
+#define BF_APBX_DEVSEL_CH4(v)           (((v) & 0xf) << 16)
+#define BFM_APBX_DEVSEL_CH4(v)          BM_APBX_DEVSEL_CH4
+#define BF_APBX_DEVSEL_CH4_V(e)         BF_APBX_DEVSEL_CH4(BV_APBX_DEVSEL_CH4__##e)
+#define BFM_APBX_DEVSEL_CH4_V(v)        BM_APBX_DEVSEL_CH4
+#define BP_APBX_DEVSEL_CH3              12
+#define BM_APBX_DEVSEL_CH3              0xf000
+#define BF_APBX_DEVSEL_CH3(v)           (((v) & 0xf) << 12)
+#define BFM_APBX_DEVSEL_CH3(v)          BM_APBX_DEVSEL_CH3
+#define BF_APBX_DEVSEL_CH3_V(e)         BF_APBX_DEVSEL_CH3(BV_APBX_DEVSEL_CH3__##e)
+#define BFM_APBX_DEVSEL_CH3_V(v)        BM_APBX_DEVSEL_CH3
+#define BP_APBX_DEVSEL_CH2              8
+#define BM_APBX_DEVSEL_CH2              0xf00
+#define BF_APBX_DEVSEL_CH2(v)           (((v) & 0xf) << 8)
+#define BFM_APBX_DEVSEL_CH2(v)          BM_APBX_DEVSEL_CH2
+#define BF_APBX_DEVSEL_CH2_V(e)         BF_APBX_DEVSEL_CH2(BV_APBX_DEVSEL_CH2__##e)
+#define BFM_APBX_DEVSEL_CH2_V(v)        BM_APBX_DEVSEL_CH2
+#define BP_APBX_DEVSEL_CH1              4
+#define BM_APBX_DEVSEL_CH1              0xf0
+#define BF_APBX_DEVSEL_CH1(v)           (((v) & 0xf) << 4)
+#define BFM_APBX_DEVSEL_CH1(v)          BM_APBX_DEVSEL_CH1
+#define BF_APBX_DEVSEL_CH1_V(e)         BF_APBX_DEVSEL_CH1(BV_APBX_DEVSEL_CH1__##e)
+#define BFM_APBX_DEVSEL_CH1_V(v)        BM_APBX_DEVSEL_CH1
+#define BP_APBX_DEVSEL_CH0              0
+#define BM_APBX_DEVSEL_CH0              0xf
+#define BF_APBX_DEVSEL_CH0(v)           (((v) & 0xf) << 0)
+#define BFM_APBX_DEVSEL_CH0(v)          BM_APBX_DEVSEL_CH0
+#define BF_APBX_DEVSEL_CH0_V(e)         BF_APBX_DEVSEL_CH0(BV_APBX_DEVSEL_CH0__##e)
+#define BFM_APBX_DEVSEL_CH0_V(v)        BM_APBX_DEVSEL_CH0
+
+#define HW_APBX_CHn_NXTCMDAR(_n1)           HW(APBX_CHn_NXTCMDAR(_n1))
+#define HWA_APBX_CHn_NXTCMDAR(_n1)          (0x80024000 + 0x40 + (_n1) * 0x70)
+#define HWT_APBX_CHn_NXTCMDAR(_n1)          HWIO_32_RW
+#define HWN_APBX_CHn_NXTCMDAR(_n1)          APBX_CHn_NXTCMDAR
+#define HWI_APBX_CHn_NXTCMDAR(_n1)          (_n1)
+#define BP_APBX_CHn_NXTCMDAR_CMD_ADDR       0
+#define BM_APBX_CHn_NXTCMDAR_CMD_ADDR       0xffffffff
+#define BF_APBX_CHn_NXTCMDAR_CMD_ADDR(v)    (((v) & 0xffffffff) << 0)
+#define BFM_APBX_CHn_NXTCMDAR_CMD_ADDR(v)   BM_APBX_CHn_NXTCMDAR_CMD_ADDR
+#define BF_APBX_CHn_NXTCMDAR_CMD_ADDR_V(e)  BF_APBX_CHn_NXTCMDAR_CMD_ADDR(BV_APBX_CHn_NXTCMDAR_CMD_ADDR__##e)
+#define BFM_APBX_CHn_NXTCMDAR_CMD_ADDR_V(v) BM_APBX_CHn_NXTCMDAR_CMD_ADDR
+
+#define HW_APBX_CHn_DEBUG2(_n1)             HW(APBX_CHn_DEBUG2(_n1))
+#define HWA_APBX_CHn_DEBUG2(_n1)            (0x80024000 + 0x90 + (_n1) * 0x70)
+#define HWT_APBX_CHn_DEBUG2(_n1)            HWIO_32_RW
+#define HWN_APBX_CHn_DEBUG2(_n1)            APBX_CHn_DEBUG2
+#define HWI_APBX_CHn_DEBUG2(_n1)            (_n1)
+#define BP_APBX_CHn_DEBUG2_APB_BYTES        16
+#define BM_APBX_CHn_DEBUG2_APB_BYTES        0xffff0000
+#define BF_APBX_CHn_DEBUG2_APB_BYTES(v)     (((v) & 0xffff) << 16)
+#define BFM_APBX_CHn_DEBUG2_APB_BYTES(v)    BM_APBX_CHn_DEBUG2_APB_BYTES
+#define BF_APBX_CHn_DEBUG2_APB_BYTES_V(e)   BF_APBX_CHn_DEBUG2_APB_BYTES(BV_APBX_CHn_DEBUG2_APB_BYTES__##e)
+#define BFM_APBX_CHn_DEBUG2_APB_BYTES_V(v)  BM_APBX_CHn_DEBUG2_APB_BYTES
+#define BP_APBX_CHn_DEBUG2_AHB_BYTES        0
+#define BM_APBX_CHn_DEBUG2_AHB_BYTES        0xffff
+#define BF_APBX_CHn_DEBUG2_AHB_BYTES(v)     (((v) & 0xffff) << 0)
+#define BFM_APBX_CHn_DEBUG2_AHB_BYTES(v)    BM_APBX_CHn_DEBUG2_AHB_BYTES
+#define BF_APBX_CHn_DEBUG2_AHB_BYTES_V(e)   BF_APBX_CHn_DEBUG2_AHB_BYTES(BV_APBX_CHn_DEBUG2_AHB_BYTES__##e)
+#define BFM_APBX_CHn_DEBUG2_AHB_BYTES_V(v)  BM_APBX_CHn_DEBUG2_AHB_BYTES
+
+#define HW_APBX_CHn_BAR(_n1)            HW(APBX_CHn_BAR(_n1))
+#define HWA_APBX_CHn_BAR(_n1)           (0x80024000 + 0x60 + (_n1) * 0x70)
+#define HWT_APBX_CHn_BAR(_n1)           HWIO_32_RW
+#define HWN_APBX_CHn_BAR(_n1)           APBX_CHn_BAR
+#define HWI_APBX_CHn_BAR(_n1)           (_n1)
+#define BP_APBX_CHn_BAR_ADDRESS         0
+#define BM_APBX_CHn_BAR_ADDRESS         0xffffffff
+#define BF_APBX_CHn_BAR_ADDRESS(v)      (((v) & 0xffffffff) << 0)
+#define BFM_APBX_CHn_BAR_ADDRESS(v)     BM_APBX_CHn_BAR_ADDRESS
+#define BF_APBX_CHn_BAR_ADDRESS_V(e)    BF_APBX_CHn_BAR_ADDRESS(BV_APBX_CHn_BAR_ADDRESS__##e)
+#define BFM_APBX_CHn_BAR_ADDRESS_V(v)   BM_APBX_CHn_BAR_ADDRESS
+
+#define HW_APBX_CHn_CMD(_n1)                    HW(APBX_CHn_CMD(_n1))
+#define HWA_APBX_CHn_CMD(_n1)                   (0x80024000 + 0x50 + (_n1) * 0x70)
+#define HWT_APBX_CHn_CMD(_n1)                   HWIO_32_RW
+#define HWN_APBX_CHn_CMD(_n1)                   APBX_CHn_CMD
+#define HWI_APBX_CHn_CMD(_n1)                   (_n1)
+#define BP_APBX_CHn_CMD_XFER_COUNT              16
+#define BM_APBX_CHn_CMD_XFER_COUNT              0xffff0000
+#define BF_APBX_CHn_CMD_XFER_COUNT(v)           (((v) & 0xffff) << 16)
+#define BFM_APBX_CHn_CMD_XFER_COUNT(v)          BM_APBX_CHn_CMD_XFER_COUNT
+#define BF_APBX_CHn_CMD_XFER_COUNT_V(e)         BF_APBX_CHn_CMD_XFER_COUNT(BV_APBX_CHn_CMD_XFER_COUNT__##e)
+#define BFM_APBX_CHn_CMD_XFER_COUNT_V(v)        BM_APBX_CHn_CMD_XFER_COUNT
+#define BP_APBX_CHn_CMD_CMDWORDS                12
+#define BM_APBX_CHn_CMD_CMDWORDS                0xf000
+#define BF_APBX_CHn_CMD_CMDWORDS(v)             (((v) & 0xf) << 12)
+#define BFM_APBX_CHn_CMD_CMDWORDS(v)            BM_APBX_CHn_CMD_CMDWORDS
+#define BF_APBX_CHn_CMD_CMDWORDS_V(e)           BF_APBX_CHn_CMD_CMDWORDS(BV_APBX_CHn_CMD_CMDWORDS__##e)
+#define BFM_APBX_CHn_CMD_CMDWORDS_V(v)          BM_APBX_CHn_CMD_CMDWORDS
+#define BP_APBX_CHn_CMD_WAIT4ENDCMD             7
+#define BM_APBX_CHn_CMD_WAIT4ENDCMD             0x80
+#define BF_APBX_CHn_CMD_WAIT4ENDCMD(v)          (((v) & 0x1) << 7)
+#define BFM_APBX_CHn_CMD_WAIT4ENDCMD(v)         BM_APBX_CHn_CMD_WAIT4ENDCMD
+#define BF_APBX_CHn_CMD_WAIT4ENDCMD_V(e)        BF_APBX_CHn_CMD_WAIT4ENDCMD(BV_APBX_CHn_CMD_WAIT4ENDCMD__##e)
+#define BFM_APBX_CHn_CMD_WAIT4ENDCMD_V(v)       BM_APBX_CHn_CMD_WAIT4ENDCMD
+#define BP_APBX_CHn_CMD_SEMAPHORE               6
+#define BM_APBX_CHn_CMD_SEMAPHORE               0x40
+#define BF_APBX_CHn_CMD_SEMAPHORE(v)            (((v) & 0x1) << 6)
+#define BFM_APBX_CHn_CMD_SEMAPHORE(v)           BM_APBX_CHn_CMD_SEMAPHORE
+#define BF_APBX_CHn_CMD_SEMAPHORE_V(e)          BF_APBX_CHn_CMD_SEMAPHORE(BV_APBX_CHn_CMD_SEMAPHORE__##e)
+#define BFM_APBX_CHn_CMD_SEMAPHORE_V(v)         BM_APBX_CHn_CMD_SEMAPHORE
+#define BP_APBX_CHn_CMD_IRQONCMPLT              3
+#define BM_APBX_CHn_CMD_IRQONCMPLT              0x8
+#define BF_APBX_CHn_CMD_IRQONCMPLT(v)           (((v) & 0x1) << 3)
+#define BFM_APBX_CHn_CMD_IRQONCMPLT(v)          BM_APBX_CHn_CMD_IRQONCMPLT
+#define BF_APBX_CHn_CMD_IRQONCMPLT_V(e)         BF_APBX_CHn_CMD_IRQONCMPLT(BV_APBX_CHn_CMD_IRQONCMPLT__##e)
+#define BFM_APBX_CHn_CMD_IRQONCMPLT_V(v)        BM_APBX_CHn_CMD_IRQONCMPLT
+#define BP_APBX_CHn_CMD_CHAIN                   2
+#define BM_APBX_CHn_CMD_CHAIN                   0x4
+#define BF_APBX_CHn_CMD_CHAIN(v)                (((v) & 0x1) << 2)
+#define BFM_APBX_CHn_CMD_CHAIN(v)               BM_APBX_CHn_CMD_CHAIN
+#define BF_APBX_CHn_CMD_CHAIN_V(e)              BF_APBX_CHn_CMD_CHAIN(BV_APBX_CHn_CMD_CHAIN__##e)
+#define BFM_APBX_CHn_CMD_CHAIN_V(v)             BM_APBX_CHn_CMD_CHAIN
+#define BP_APBX_CHn_CMD_COMMAND                 0
+#define BM_APBX_CHn_CMD_COMMAND                 0x3
+#define BV_APBX_CHn_CMD_COMMAND__NO_DMA_XFER    0x0
+#define BV_APBX_CHn_CMD_COMMAND__DMA_WRITE      0x1
+#define BV_APBX_CHn_CMD_COMMAND__DMA_READ       0x2
+#define BF_APBX_CHn_CMD_COMMAND(v)              (((v) & 0x3) << 0)
+#define BFM_APBX_CHn_CMD_COMMAND(v)             BM_APBX_CHn_CMD_COMMAND
+#define BF_APBX_CHn_CMD_COMMAND_V(e)            BF_APBX_CHn_CMD_COMMAND(BV_APBX_CHn_CMD_COMMAND__##e)
+#define BFM_APBX_CHn_CMD_COMMAND_V(v)           BM_APBX_CHn_CMD_COMMAND
+
+#define HW_APBX_CHn_DEBUG1(_n1)                         HW(APBX_CHn_DEBUG1(_n1))
+#define HWA_APBX_CHn_DEBUG1(_n1)                        (0x80024000 + 0x80 + (_n1) * 0x70)
+#define HWT_APBX_CHn_DEBUG1(_n1)                        HWIO_32_RW
+#define HWN_APBX_CHn_DEBUG1(_n1)                        APBX_CHn_DEBUG1
+#define HWI_APBX_CHn_DEBUG1(_n1)                        (_n1)
+#define BP_APBX_CHn_DEBUG1_REQ                          31
+#define BM_APBX_CHn_DEBUG1_REQ                          0x80000000
+#define BF_APBX_CHn_DEBUG1_REQ(v)                       (((v) & 0x1) << 31)
+#define BFM_APBX_CHn_DEBUG1_REQ(v)                      BM_APBX_CHn_DEBUG1_REQ
+#define BF_APBX_CHn_DEBUG1_REQ_V(e)                     BF_APBX_CHn_DEBUG1_REQ(BV_APBX_CHn_DEBUG1_REQ__##e)
+#define BFM_APBX_CHn_DEBUG1_REQ_V(v)                    BM_APBX_CHn_DEBUG1_REQ
+#define BP_APBX_CHn_DEBUG1_BURST                        30
+#define BM_APBX_CHn_DEBUG1_BURST                        0x40000000
+#define BF_APBX_CHn_DEBUG1_BURST(v)                     (((v) & 0x1) << 30)
+#define BFM_APBX_CHn_DEBUG1_BURST(v)                    BM_APBX_CHn_DEBUG1_BURST
+#define BF_APBX_CHn_DEBUG1_BURST_V(e)                   BF_APBX_CHn_DEBUG1_BURST(BV_APBX_CHn_DEBUG1_BURST__##e)
+#define BFM_APBX_CHn_DEBUG1_BURST_V(v)                  BM_APBX_CHn_DEBUG1_BURST
+#define BP_APBX_CHn_DEBUG1_KICK                         29
+#define BM_APBX_CHn_DEBUG1_KICK                         0x20000000
+#define BF_APBX_CHn_DEBUG1_KICK(v)                      (((v) & 0x1) << 29)
+#define BFM_APBX_CHn_DEBUG1_KICK(v)                     BM_APBX_CHn_DEBUG1_KICK
+#define BF_APBX_CHn_DEBUG1_KICK_V(e)                    BF_APBX_CHn_DEBUG1_KICK(BV_APBX_CHn_DEBUG1_KICK__##e)
+#define BFM_APBX_CHn_DEBUG1_KICK_V(v)                   BM_APBX_CHn_DEBUG1_KICK
+#define BP_APBX_CHn_DEBUG1_END                          28
+#define BM_APBX_CHn_DEBUG1_END                          0x10000000
+#define BF_APBX_CHn_DEBUG1_END(v)                       (((v) & 0x1) << 28)
+#define BFM_APBX_CHn_DEBUG1_END(v)                      BM_APBX_CHn_DEBUG1_END
+#define BF_APBX_CHn_DEBUG1_END_V(e)                     BF_APBX_CHn_DEBUG1_END(BV_APBX_CHn_DEBUG1_END__##e)
+#define BFM_APBX_CHn_DEBUG1_END_V(v)                    BM_APBX_CHn_DEBUG1_END
+#define BP_APBX_CHn_DEBUG1_RSVD2                        25
+#define BM_APBX_CHn_DEBUG1_RSVD2                        0xe000000
+#define BF_APBX_CHn_DEBUG1_RSVD2(v)                     (((v) & 0x7) << 25)
+#define BFM_APBX_CHn_DEBUG1_RSVD2(v)                    BM_APBX_CHn_DEBUG1_RSVD2
+#define BF_APBX_CHn_DEBUG1_RSVD2_V(e)                   BF_APBX_CHn_DEBUG1_RSVD2(BV_APBX_CHn_DEBUG1_RSVD2__##e)
+#define BFM_APBX_CHn_DEBUG1_RSVD2_V(v)                  BM_APBX_CHn_DEBUG1_RSVD2
+#define BP_APBX_CHn_DEBUG1_NEXTCMDADDRVALID             24
+#define BM_APBX_CHn_DEBUG1_NEXTCMDADDRVALID             0x1000000
+#define BF_APBX_CHn_DEBUG1_NEXTCMDADDRVALID(v)          (((v) & 0x1) << 24)
+#define BFM_APBX_CHn_DEBUG1_NEXTCMDADDRVALID(v)         BM_APBX_CHn_DEBUG1_NEXTCMDADDRVALID
+#define BF_APBX_CHn_DEBUG1_NEXTCMDADDRVALID_V(e)        BF_APBX_CHn_DEBUG1_NEXTCMDADDRVALID(BV_APBX_CHn_DEBUG1_NEXTCMDADDRVALID__##e)
+#define BFM_APBX_CHn_DEBUG1_NEXTCMDADDRVALID_V(v)       BM_APBX_CHn_DEBUG1_NEXTCMDADDRVALID
+#define BP_APBX_CHn_DEBUG1_RD_FIFO_EMPTY                23
+#define BM_APBX_CHn_DEBUG1_RD_FIFO_EMPTY                0x800000
+#define BF_APBX_CHn_DEBUG1_RD_FIFO_EMPTY(v)             (((v) & 0x1) << 23)
+#define BFM_APBX_CHn_DEBUG1_RD_FIFO_EMPTY(v)            BM_APBX_CHn_DEBUG1_RD_FIFO_EMPTY
+#define BF_APBX_CHn_DEBUG1_RD_FIFO_EMPTY_V(e)           BF_APBX_CHn_DEBUG1_RD_FIFO_EMPTY(BV_APBX_CHn_DEBUG1_RD_FIFO_EMPTY__##e)
+#define BFM_APBX_CHn_DEBUG1_RD_FIFO_EMPTY_V(v)          BM_APBX_CHn_DEBUG1_RD_FIFO_EMPTY
+#define BP_APBX_CHn_DEBUG1_RD_FIFO_FULL                 22
+#define BM_APBX_CHn_DEBUG1_RD_FIFO_FULL                 0x400000
+#define BF_APBX_CHn_DEBUG1_RD_FIFO_FULL(v)              (((v) & 0x1) << 22)
+#define BFM_APBX_CHn_DEBUG1_RD_FIFO_FULL(v)             BM_APBX_CHn_DEBUG1_RD_FIFO_FULL
+#define BF_APBX_CHn_DEBUG1_RD_FIFO_FULL_V(e)            BF_APBX_CHn_DEBUG1_RD_FIFO_FULL(BV_APBX_CHn_DEBUG1_RD_FIFO_FULL__##e)
+#define BFM_APBX_CHn_DEBUG1_RD_FIFO_FULL_V(v)           BM_APBX_CHn_DEBUG1_RD_FIFO_FULL
+#define BP_APBX_CHn_DEBUG1_WR_FIFO_EMPTY                21
+#define BM_APBX_CHn_DEBUG1_WR_FIFO_EMPTY                0x200000
+#define BF_APBX_CHn_DEBUG1_WR_FIFO_EMPTY(v)             (((v) & 0x1) << 21)
+#define BFM_APBX_CHn_DEBUG1_WR_FIFO_EMPTY(v)            BM_APBX_CHn_DEBUG1_WR_FIFO_EMPTY
+#define BF_APBX_CHn_DEBUG1_WR_FIFO_EMPTY_V(e)           BF_APBX_CHn_DEBUG1_WR_FIFO_EMPTY(BV_APBX_CHn_DEBUG1_WR_FIFO_EMPTY__##e)
+#define BFM_APBX_CHn_DEBUG1_WR_FIFO_EMPTY_V(v)          BM_APBX_CHn_DEBUG1_WR_FIFO_EMPTY
+#define BP_APBX_CHn_DEBUG1_WR_FIFO_FULL                 20
+#define BM_APBX_CHn_DEBUG1_WR_FIFO_FULL                 0x100000
+#define BF_APBX_CHn_DEBUG1_WR_FIFO_FULL(v)              (((v) & 0x1) << 20)
+#define BFM_APBX_CHn_DEBUG1_WR_FIFO_FULL(v)             BM_APBX_CHn_DEBUG1_WR_FIFO_FULL
+#define BF_APBX_CHn_DEBUG1_WR_FIFO_FULL_V(e)            BF_APBX_CHn_DEBUG1_WR_FIFO_FULL(BV_APBX_CHn_DEBUG1_WR_FIFO_FULL__##e)
+#define BFM_APBX_CHn_DEBUG1_WR_FIFO_FULL_V(v)           BM_APBX_CHn_DEBUG1_WR_FIFO_FULL
+#define BP_APBX_CHn_DEBUG1_RSVD1                        5
+#define BM_APBX_CHn_DEBUG1_RSVD1                        0xfffe0
+#define BF_APBX_CHn_DEBUG1_RSVD1(v)                     (((v) & 0x7fff) << 5)
+#define BFM_APBX_CHn_DEBUG1_RSVD1(v)                    BM_APBX_CHn_DEBUG1_RSVD1
+#define BF_APBX_CHn_DEBUG1_RSVD1_V(e)                   BF_APBX_CHn_DEBUG1_RSVD1(BV_APBX_CHn_DEBUG1_RSVD1__##e)
+#define BFM_APBX_CHn_DEBUG1_RSVD1_V(v)                  BM_APBX_CHn_DEBUG1_RSVD1
+#define BP_APBX_CHn_DEBUG1_STATEMACHINE                 0
+#define BM_APBX_CHn_DEBUG1_STATEMACHINE                 0x1f
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__IDLE           0x0
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD1       0x1
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD3       0x2
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD2       0x3
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__XFER_DECODE    0x4
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_WAIT       0x5
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD4       0x6
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__PIO_REQ        0x7
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__READ_FLUSH     0x8
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__READ_WAIT      0x9
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__WRITE          0xc
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__READ_REQ       0xd
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__CHECK_CHAIN    0xe
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__XFER_COMPLETE  0xf
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__WAIT_END       0x15
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__WRITE_WAIT     0x1c
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__CHECK_WAIT     0x1e
+#define BF_APBX_CHn_DEBUG1_STATEMACHINE(v)              (((v) & 0x1f) << 0)
+#define BFM_APBX_CHn_DEBUG1_STATEMACHINE(v)             BM_APBX_CHn_DEBUG1_STATEMACHINE
+#define BF_APBX_CHn_DEBUG1_STATEMACHINE_V(e)            BF_APBX_CHn_DEBUG1_STATEMACHINE(BV_APBX_CHn_DEBUG1_STATEMACHINE__##e)
+#define BFM_APBX_CHn_DEBUG1_STATEMACHINE_V(v)           BM_APBX_CHn_DEBUG1_STATEMACHINE
+
+#define HW_APBX_CHn_SEMA(_n1)                   HW(APBX_CHn_SEMA(_n1))
+#define HWA_APBX_CHn_SEMA(_n1)                  (0x80024000 + 0x70 + (_n1) * 0x70)
+#define HWT_APBX_CHn_SEMA(_n1)                  HWIO_32_RW
+#define HWN_APBX_CHn_SEMA(_n1)                  APBX_CHn_SEMA
+#define HWI_APBX_CHn_SEMA(_n1)                  (_n1)
+#define BP_APBX_CHn_SEMA_PHORE                  16
+#define BM_APBX_CHn_SEMA_PHORE                  0xff0000
+#define BF_APBX_CHn_SEMA_PHORE(v)               (((v) & 0xff) << 16)
+#define BFM_APBX_CHn_SEMA_PHORE(v)              BM_APBX_CHn_SEMA_PHORE
+#define BF_APBX_CHn_SEMA_PHORE_V(e)             BF_APBX_CHn_SEMA_PHORE(BV_APBX_CHn_SEMA_PHORE__##e)
+#define BFM_APBX_CHn_SEMA_PHORE_V(v)            BM_APBX_CHn_SEMA_PHORE
+#define BP_APBX_CHn_SEMA_INCREMENT_SEMA         0
+#define BM_APBX_CHn_SEMA_INCREMENT_SEMA         0xff
+#define BF_APBX_CHn_SEMA_INCREMENT_SEMA(v)      (((v) & 0xff) << 0)
+#define BFM_APBX_CHn_SEMA_INCREMENT_SEMA(v)     BM_APBX_CHn_SEMA_INCREMENT_SEMA
+#define BF_APBX_CHn_SEMA_INCREMENT_SEMA_V(e)    BF_APBX_CHn_SEMA_INCREMENT_SEMA(BV_APBX_CHn_SEMA_INCREMENT_SEMA__##e)
+#define BFM_APBX_CHn_SEMA_INCREMENT_SEMA_V(v)   BM_APBX_CHn_SEMA_INCREMENT_SEMA
+
+#define HW_APBX_CHn_CURCMDAR(_n1)           HW(APBX_CHn_CURCMDAR(_n1))
+#define HWA_APBX_CHn_CURCMDAR(_n1)          (0x80024000 + 0x30 + (_n1) * 0x70)
+#define HWT_APBX_CHn_CURCMDAR(_n1)          HWIO_32_RW
+#define HWN_APBX_CHn_CURCMDAR(_n1)          APBX_CHn_CURCMDAR
+#define HWI_APBX_CHn_CURCMDAR(_n1)          (_n1)
+#define BP_APBX_CHn_CURCMDAR_CMD_ADDR       0
+#define BM_APBX_CHn_CURCMDAR_CMD_ADDR       0xffffffff
+#define BF_APBX_CHn_CURCMDAR_CMD_ADDR(v)    (((v) & 0xffffffff) << 0)
+#define BFM_APBX_CHn_CURCMDAR_CMD_ADDR(v)   BM_APBX_CHn_CURCMDAR_CMD_ADDR
+#define BF_APBX_CHn_CURCMDAR_CMD_ADDR_V(e)  BF_APBX_CHn_CURCMDAR_CMD_ADDR(BV_APBX_CHn_CURCMDAR_CMD_ADDR__##e)
+#define BFM_APBX_CHn_CURCMDAR_CMD_ADDR_V(v) BM_APBX_CHn_CURCMDAR_CMD_ADDR
+
+#endif /* __HEADERGEN_STMP3600_APBX_H__*/
diff --git a/firmware/target/arm/imx233/regs/stmp3600/arc.h b/firmware/target/arm/imx233/regs/stmp3600/arc.h
new file mode 100644
index 0000000000..1942e85a9a
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3600/arc.h
@@ -0,0 +1,231 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * stmp3600 version: 2.4.0
+ * stmp3600 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_STMP3600_ARC_H__
+#define __HEADERGEN_STMP3600_ARC_H__
+
+#define HW_ARC_BASE     HW(ARC_BASE)
+#define HWA_ARC_BASE    (0x80080000 + 0x0)
+#define HWT_ARC_BASE    HWIO_32_RW
+#define HWN_ARC_BASE    ARC_BASE
+#define HWI_ARC_BASE    
+
+#define HW_ARC_ID   HW(ARC_ID)
+#define HWA_ARC_ID  (0x80080000 + 0x0)
+#define HWT_ARC_ID  HWIO_32_RW
+#define HWN_ARC_ID  ARC_ID
+#define HWI_ARC_ID  
+
+#define HW_ARC_HCSPARAMS    HW(ARC_HCSPARAMS)
+#define HWA_ARC_HCSPARAMS   (0x80080000 + 0x104)
+#define HWT_ARC_HCSPARAMS   HWIO_32_RW
+#define HWN_ARC_HCSPARAMS   ARC_HCSPARAMS
+#define HWI_ARC_HCSPARAMS   
+
+#define HW_ARC_USBCMD   HW(ARC_USBCMD)
+#define HWA_ARC_USBCMD  (0x80080000 + 0x140)
+#define HWT_ARC_USBCMD  HWIO_32_RW
+#define HWN_ARC_USBCMD  ARC_USBCMD
+#define HWI_ARC_USBCMD  
+
+#define HW_ARC_USBSTS   HW(ARC_USBSTS)
+#define HWA_ARC_USBSTS  (0x80080000 + 0x144)
+#define HWT_ARC_USBSTS  HWIO_32_RW
+#define HWN_ARC_USBSTS  ARC_USBSTS
+#define HWI_ARC_USBSTS  
+
+#define HW_ARC_USBINTR  HW(ARC_USBINTR)
+#define HWA_ARC_USBINTR (0x80080000 + 0x148)
+#define HWT_ARC_USBINTR HWIO_32_RW
+#define HWN_ARC_USBINTR ARC_USBINTR
+#define HWI_ARC_USBINTR 
+
+#define HW_ARC_FRINDEX  HW(ARC_FRINDEX)
+#define HWA_ARC_FRINDEX (0x80080000 + 0x14c)
+#define HWT_ARC_FRINDEX HWIO_32_RW
+#define HWN_ARC_FRINDEX ARC_FRINDEX
+#define HWI_ARC_FRINDEX 
+
+#define HW_ARC_DEVADDR  HW(ARC_DEVADDR)
+#define HWA_ARC_DEVADDR (0x80080000 + 0x154)
+#define HWT_ARC_DEVADDR HWIO_32_RW
+#define HWN_ARC_DEVADDR ARC_DEVADDR
+#define HWI_ARC_DEVADDR 
+
+#define HW_ARC_ENDPTLISTADDR    HW(ARC_ENDPTLISTADDR)
+#define HWA_ARC_ENDPTLISTADDR   (0x80080000 + 0x158)
+#define HWT_ARC_ENDPTLISTADDR   HWIO_32_RW
+#define HWN_ARC_ENDPTLISTADDR   ARC_ENDPTLISTADDR
+#define HWI_ARC_ENDPTLISTADDR   
+
+#define HW_ARC_PORTSC1  HW(ARC_PORTSC1)
+#define HWA_ARC_PORTSC1 (0x80080000 + 0x184)
+#define HWT_ARC_PORTSC1 HWIO_32_RW
+#define HWN_ARC_PORTSC1 ARC_PORTSC1
+#define HWI_ARC_PORTSC1 
+
+#define HW_ARC_OTGSC    HW(ARC_OTGSC)
+#define HWA_ARC_OTGSC   (0x80080000 + 0x1a4)
+#define HWT_ARC_OTGSC   HWIO_32_RW
+#define HWN_ARC_OTGSC   ARC_OTGSC
+#define HWI_ARC_OTGSC   
+
+#define HW_ARC_USBMODE  HW(ARC_USBMODE)
+#define HWA_ARC_USBMODE (0x80080000 + 0x1a8)
+#define HWT_ARC_USBMODE HWIO_32_RW
+#define HWN_ARC_USBMODE ARC_USBMODE
+#define HWI_ARC_USBMODE 
+
+#define HW_ARC_ENDPTSETUPSTAT   HW(ARC_ENDPTSETUPSTAT)
+#define HWA_ARC_ENDPTSETUPSTAT  (0x80080000 + 0x1ac)
+#define HWT_ARC_ENDPTSETUPSTAT  HWIO_32_RW
+#define HWN_ARC_ENDPTSETUPSTAT  ARC_ENDPTSETUPSTAT
+#define HWI_ARC_ENDPTSETUPSTAT  
+
+#define HW_ARC_ENDPTPRIME   HW(ARC_ENDPTPRIME)
+#define HWA_ARC_ENDPTPRIME  (0x80080000 + 0x1b0)
+#define HWT_ARC_ENDPTPRIME  HWIO_32_RW
+#define HWN_ARC_ENDPTPRIME  ARC_ENDPTPRIME
+#define HWI_ARC_ENDPTPRIME  
+
+#define HW_ARC_ENDPTFLUSH   HW(ARC_ENDPTFLUSH)
+#define HWA_ARC_ENDPTFLUSH  (0x80080000 + 0x1b4)
+#define HWT_ARC_ENDPTFLUSH  HWIO_32_RW
+#define HWN_ARC_ENDPTFLUSH  ARC_ENDPTFLUSH
+#define HWI_ARC_ENDPTFLUSH  
+
+#define HW_ARC_ENDPTSTATUS  HW(ARC_ENDPTSTATUS)
+#define HWA_ARC_ENDPTSTATUS (0x80080000 + 0x1b8)
+#define HWT_ARC_ENDPTSTATUS HWIO_32_RW
+#define HWN_ARC_ENDPTSTATUS ARC_ENDPTSTATUS
+#define HWI_ARC_ENDPTSTATUS 
+
+#define HW_ARC_ENDPTCOMPLETE    HW(ARC_ENDPTCOMPLETE)
+#define HWA_ARC_ENDPTCOMPLETE   (0x80080000 + 0x1bc)
+#define HWT_ARC_ENDPTCOMPLETE   HWIO_32_RW
+#define HWN_ARC_ENDPTCOMPLETE   ARC_ENDPTCOMPLETE
+#define HWI_ARC_ENDPTCOMPLETE   
+
+#define HW_ARC_ENDPTCTRL0   HW(ARC_ENDPTCTRL0)
+#define HWA_ARC_ENDPTCTRL0  (0x80080000 + 0x1c0)
+#define HWT_ARC_ENDPTCTRL0  HWIO_32_RW
+#define HWN_ARC_ENDPTCTRL0  ARC_ENDPTCTRL0
+#define HWI_ARC_ENDPTCTRL0  
+
+#define HW_ARC_ENDPTCTRL1   HW(ARC_ENDPTCTRL1)
+#define HWA_ARC_ENDPTCTRL1  (0x80080000 + 0x1c4)
+#define HWT_ARC_ENDPTCTRL1  HWIO_32_RW
+#define HWN_ARC_ENDPTCTRL1  ARC_ENDPTCTRL1
+#define HWI_ARC_ENDPTCTRL1  
+
+#define HW_ARC_ENDPTCTRL2   HW(ARC_ENDPTCTRL2)
+#define HWA_ARC_ENDPTCTRL2  (0x80080000 + 0x1c8)
+#define HWT_ARC_ENDPTCTRL2  HWIO_32_RW
+#define HWN_ARC_ENDPTCTRL2  ARC_ENDPTCTRL2
+#define HWI_ARC_ENDPTCTRL2  
+
+#define HW_ARC_ENDPTCTRL3   HW(ARC_ENDPTCTRL3)
+#define HWA_ARC_ENDPTCTRL3  (0x80080000 + 0x1cc)
+#define HWT_ARC_ENDPTCTRL3  HWIO_32_RW
+#define HWN_ARC_ENDPTCTRL3  ARC_ENDPTCTRL3
+#define HWI_ARC_ENDPTCTRL3  
+
+#define HW_ARC_ENDPTCTRL4   HW(ARC_ENDPTCTRL4)
+#define HWA_ARC_ENDPTCTRL4  (0x80080000 + 0x1d0)
+#define HWT_ARC_ENDPTCTRL4  HWIO_32_RW
+#define HWN_ARC_ENDPTCTRL4  ARC_ENDPTCTRL4
+#define HWI_ARC_ENDPTCTRL4  
+
+#define HW_ARC_ENDPTCTRL5   HW(ARC_ENDPTCTRL5)
+#define HWA_ARC_ENDPTCTRL5  (0x80080000 + 0x1d4)
+#define HWT_ARC_ENDPTCTRL5  HWIO_32_RW
+#define HWN_ARC_ENDPTCTRL5  ARC_ENDPTCTRL5
+#define HWI_ARC_ENDPTCTRL5  
+
+#define HW_ARC_ENDPTCTRL6   HW(ARC_ENDPTCTRL6)
+#define HWA_ARC_ENDPTCTRL6  (0x80080000 + 0x1d8)
+#define HWT_ARC_ENDPTCTRL6  HWIO_32_RW
+#define HWN_ARC_ENDPTCTRL6  ARC_ENDPTCTRL6
+#define HWI_ARC_ENDPTCTRL6  
+
+#define HW_ARC_ENDPTCTRL7   HW(ARC_ENDPTCTRL7)
+#define HWA_ARC_ENDPTCTRL7  (0x80080000 + 0x1dc)
+#define HWT_ARC_ENDPTCTRL7  HWIO_32_RW
+#define HWN_ARC_ENDPTCTRL7  ARC_ENDPTCTRL7
+#define HWI_ARC_ENDPTCTRL7  
+
+#define HW_ARC_ENDPTCTRL8   HW(ARC_ENDPTCTRL8)
+#define HWA_ARC_ENDPTCTRL8  (0x80080000 + 0x1e0)
+#define HWT_ARC_ENDPTCTRL8  HWIO_32_RW
+#define HWN_ARC_ENDPTCTRL8  ARC_ENDPTCTRL8
+#define HWI_ARC_ENDPTCTRL8  
+
+#define HW_ARC_ENDPTCTRL9   HW(ARC_ENDPTCTRL9)
+#define HWA_ARC_ENDPTCTRL9  (0x80080000 + 0x1e4)
+#define HWT_ARC_ENDPTCTRL9  HWIO_32_RW
+#define HWN_ARC_ENDPTCTRL9  ARC_ENDPTCTRL9
+#define HWI_ARC_ENDPTCTRL9  
+
+#define HW_ARC_ENDPTCTRL10  HW(ARC_ENDPTCTRL10)
+#define HWA_ARC_ENDPTCTRL10 (0x80080000 + 0x1e8)
+#define HWT_ARC_ENDPTCTRL10 HWIO_32_RW
+#define HWN_ARC_ENDPTCTRL10 ARC_ENDPTCTRL10
+#define HWI_ARC_ENDPTCTRL10 
+
+#define HW_ARC_ENDPTCTRL11  HW(ARC_ENDPTCTRL11)
+#define HWA_ARC_ENDPTCTRL11 (0x80080000 + 0x1ec)
+#define HWT_ARC_ENDPTCTRL11 HWIO_32_RW
+#define HWN_ARC_ENDPTCTRL11 ARC_ENDPTCTRL11
+#define HWI_ARC_ENDPTCTRL11 
+
+#define HW_ARC_ENDPTCTRL12  HW(ARC_ENDPTCTRL12)
+#define HWA_ARC_ENDPTCTRL12 (0x80080000 + 0x1f0)
+#define HWT_ARC_ENDPTCTRL12 HWIO_32_RW
+#define HWN_ARC_ENDPTCTRL12 ARC_ENDPTCTRL12
+#define HWI_ARC_ENDPTCTRL12 
+
+#define HW_ARC_ENDPTCTRL13  HW(ARC_ENDPTCTRL13)
+#define HWA_ARC_ENDPTCTRL13 (0x80080000 + 0x1f4)
+#define HWT_ARC_ENDPTCTRL13 HWIO_32_RW
+#define HWN_ARC_ENDPTCTRL13 ARC_ENDPTCTRL13
+#define HWI_ARC_ENDPTCTRL13 
+
+#define HW_ARC_ENDPTCTRL14  HW(ARC_ENDPTCTRL14)
+#define HWA_ARC_ENDPTCTRL14 (0x80080000 + 0x1f8)
+#define HWT_ARC_ENDPTCTRL14 HWIO_32_RW
+#define HWN_ARC_ENDPTCTRL14 ARC_ENDPTCTRL14
+#define HWI_ARC_ENDPTCTRL14 
+
+#define HW_ARC_ENDPTCTRL15  HW(ARC_ENDPTCTRL15)
+#define HWA_ARC_ENDPTCTRL15 (0x80080000 + 0x1fc)
+#define HWT_ARC_ENDPTCTRL15 HWIO_32_RW
+#define HWN_ARC_ENDPTCTRL15 ARC_ENDPTCTRL15
+#define HWI_ARC_ENDPTCTRL15 
+
+#define HW_ARC_ENDPTCTRLn(_n1)  HW(ARC_ENDPTCTRLn(_n1))
+#define HWA_ARC_ENDPTCTRLn(_n1) (0x80080000 + 0x1c0 + (_n1) * 0x4)
+#define HWT_ARC_ENDPTCTRLn(_n1) HWIO_32_RW
+#define HWN_ARC_ENDPTCTRLn(_n1) ARC_ENDPTCTRLn
+#define HWI_ARC_ENDPTCTRLn(_n1) (_n1)
+
+#endif /* __HEADERGEN_STMP3600_ARC_H__*/
diff --git a/firmware/target/arm/imx233/regs/stmp3600/audioin.h b/firmware/target/arm/imx233/regs/stmp3600/audioin.h
new file mode 100644
index 0000000000..050131f51a
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3600/audioin.h
@@ -0,0 +1,499 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * stmp3600 version: 2.4.0
+ * stmp3600 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_STMP3600_AUDIOIN_H__
+#define __HEADERGEN_STMP3600_AUDIOIN_H__
+
+#define HW_AUDIOIN_CTRL                             HW(AUDIOIN_CTRL)
+#define HWA_AUDIOIN_CTRL                            (0x8004c000 + 0x0)
+#define HWT_AUDIOIN_CTRL                            HWIO_32_RW
+#define HWN_AUDIOIN_CTRL                            AUDIOIN_CTRL
+#define HWI_AUDIOIN_CTRL                            
+#define HW_AUDIOIN_CTRL_SET                         HW(AUDIOIN_CTRL_SET)
+#define HWA_AUDIOIN_CTRL_SET                        (HWA_AUDIOIN_CTRL + 0x4)
+#define HWT_AUDIOIN_CTRL_SET                        HWIO_32_WO
+#define HWN_AUDIOIN_CTRL_SET                        AUDIOIN_CTRL
+#define HWI_AUDIOIN_CTRL_SET                        
+#define HW_AUDIOIN_CTRL_CLR                         HW(AUDIOIN_CTRL_CLR)
+#define HWA_AUDIOIN_CTRL_CLR                        (HWA_AUDIOIN_CTRL + 0x8)
+#define HWT_AUDIOIN_CTRL_CLR                        HWIO_32_WO
+#define HWN_AUDIOIN_CTRL_CLR                        AUDIOIN_CTRL
+#define HWI_AUDIOIN_CTRL_CLR                        
+#define HW_AUDIOIN_CTRL_TOG                         HW(AUDIOIN_CTRL_TOG)
+#define HWA_AUDIOIN_CTRL_TOG                        (HWA_AUDIOIN_CTRL + 0xc)
+#define HWT_AUDIOIN_CTRL_TOG                        HWIO_32_WO
+#define HWN_AUDIOIN_CTRL_TOG                        AUDIOIN_CTRL
+#define HWI_AUDIOIN_CTRL_TOG                        
+#define BP_AUDIOIN_CTRL_SFTRST                      31
+#define BM_AUDIOIN_CTRL_SFTRST                      0x80000000
+#define BF_AUDIOIN_CTRL_SFTRST(v)                   (((v) & 0x1) << 31)
+#define BFM_AUDIOIN_CTRL_SFTRST(v)                  BM_AUDIOIN_CTRL_SFTRST
+#define BF_AUDIOIN_CTRL_SFTRST_V(e)                 BF_AUDIOIN_CTRL_SFTRST(BV_AUDIOIN_CTRL_SFTRST__##e)
+#define BFM_AUDIOIN_CTRL_SFTRST_V(v)                BM_AUDIOIN_CTRL_SFTRST
+#define BP_AUDIOIN_CTRL_CLKGATE                     30
+#define BM_AUDIOIN_CTRL_CLKGATE                     0x40000000
+#define BF_AUDIOIN_CTRL_CLKGATE(v)                  (((v) & 0x1) << 30)
+#define BFM_AUDIOIN_CTRL_CLKGATE(v)                 BM_AUDIOIN_CTRL_CLKGATE
+#define BF_AUDIOIN_CTRL_CLKGATE_V(e)                BF_AUDIOIN_CTRL_CLKGATE(BV_AUDIOIN_CTRL_CLKGATE__##e)
+#define BFM_AUDIOIN_CTRL_CLKGATE_V(v)               BM_AUDIOIN_CTRL_CLKGATE
+#define BP_AUDIOIN_CTRL_DMAWAIT_COUNT               16
+#define BM_AUDIOIN_CTRL_DMAWAIT_COUNT               0x1f0000
+#define BF_AUDIOIN_CTRL_DMAWAIT_COUNT(v)            (((v) & 0x1f) << 16)
+#define BFM_AUDIOIN_CTRL_DMAWAIT_COUNT(v)           BM_AUDIOIN_CTRL_DMAWAIT_COUNT
+#define BF_AUDIOIN_CTRL_DMAWAIT_COUNT_V(e)          BF_AUDIOIN_CTRL_DMAWAIT_COUNT(BV_AUDIOIN_CTRL_DMAWAIT_COUNT__##e)
+#define BFM_AUDIOIN_CTRL_DMAWAIT_COUNT_V(v)         BM_AUDIOIN_CTRL_DMAWAIT_COUNT
+#define BP_AUDIOIN_CTRL_LR_SWAP                     10
+#define BM_AUDIOIN_CTRL_LR_SWAP                     0x400
+#define BF_AUDIOIN_CTRL_LR_SWAP(v)                  (((v) & 0x1) << 10)
+#define BFM_AUDIOIN_CTRL_LR_SWAP(v)                 BM_AUDIOIN_CTRL_LR_SWAP
+#define BF_AUDIOIN_CTRL_LR_SWAP_V(e)                BF_AUDIOIN_CTRL_LR_SWAP(BV_AUDIOIN_CTRL_LR_SWAP__##e)
+#define BFM_AUDIOIN_CTRL_LR_SWAP_V(v)               BM_AUDIOIN_CTRL_LR_SWAP
+#define BP_AUDIOIN_CTRL_EDGE_SYNC                   9
+#define BM_AUDIOIN_CTRL_EDGE_SYNC                   0x200
+#define BF_AUDIOIN_CTRL_EDGE_SYNC(v)                (((v) & 0x1) << 9)
+#define BFM_AUDIOIN_CTRL_EDGE_SYNC(v)               BM_AUDIOIN_CTRL_EDGE_SYNC
+#define BF_AUDIOIN_CTRL_EDGE_SYNC_V(e)              BF_AUDIOIN_CTRL_EDGE_SYNC(BV_AUDIOIN_CTRL_EDGE_SYNC__##e)
+#define BFM_AUDIOIN_CTRL_EDGE_SYNC_V(v)             BM_AUDIOIN_CTRL_EDGE_SYNC
+#define BP_AUDIOIN_CTRL_INVERT_1BIT                 8
+#define BM_AUDIOIN_CTRL_INVERT_1BIT                 0x100
+#define BF_AUDIOIN_CTRL_INVERT_1BIT(v)              (((v) & 0x1) << 8)
+#define BFM_AUDIOIN_CTRL_INVERT_1BIT(v)             BM_AUDIOIN_CTRL_INVERT_1BIT
+#define BF_AUDIOIN_CTRL_INVERT_1BIT_V(e)            BF_AUDIOIN_CTRL_INVERT_1BIT(BV_AUDIOIN_CTRL_INVERT_1BIT__##e)
+#define BFM_AUDIOIN_CTRL_INVERT_1BIT_V(v)           BM_AUDIOIN_CTRL_INVERT_1BIT
+#define BP_AUDIOIN_CTRL_OFFSET_ENABLE               7
+#define BM_AUDIOIN_CTRL_OFFSET_ENABLE               0x80
+#define BF_AUDIOIN_CTRL_OFFSET_ENABLE(v)            (((v) & 0x1) << 7)
+#define BFM_AUDIOIN_CTRL_OFFSET_ENABLE(v)           BM_AUDIOIN_CTRL_OFFSET_ENABLE
+#define BF_AUDIOIN_CTRL_OFFSET_ENABLE_V(e)          BF_AUDIOIN_CTRL_OFFSET_ENABLE(BV_AUDIOIN_CTRL_OFFSET_ENABLE__##e)
+#define BFM_AUDIOIN_CTRL_OFFSET_ENABLE_V(v)         BM_AUDIOIN_CTRL_OFFSET_ENABLE
+#define BP_AUDIOIN_CTRL_HPF_ENABLE                  6
+#define BM_AUDIOIN_CTRL_HPF_ENABLE                  0x40
+#define BF_AUDIOIN_CTRL_HPF_ENABLE(v)               (((v) & 0x1) << 6)
+#define BFM_AUDIOIN_CTRL_HPF_ENABLE(v)              BM_AUDIOIN_CTRL_HPF_ENABLE
+#define BF_AUDIOIN_CTRL_HPF_ENABLE_V(e)             BF_AUDIOIN_CTRL_HPF_ENABLE(BV_AUDIOIN_CTRL_HPF_ENABLE__##e)
+#define BFM_AUDIOIN_CTRL_HPF_ENABLE_V(v)            BM_AUDIOIN_CTRL_HPF_ENABLE
+#define BP_AUDIOIN_CTRL_WORD_LENGTH                 5
+#define BM_AUDIOIN_CTRL_WORD_LENGTH                 0x20
+#define BF_AUDIOIN_CTRL_WORD_LENGTH(v)              (((v) & 0x1) << 5)
+#define BFM_AUDIOIN_CTRL_WORD_LENGTH(v)             BM_AUDIOIN_CTRL_WORD_LENGTH
+#define BF_AUDIOIN_CTRL_WORD_LENGTH_V(e)            BF_AUDIOIN_CTRL_WORD_LENGTH(BV_AUDIOIN_CTRL_WORD_LENGTH__##e)
+#define BFM_AUDIOIN_CTRL_WORD_LENGTH_V(v)           BM_AUDIOIN_CTRL_WORD_LENGTH
+#define BP_AUDIOIN_CTRL_LOOPBACK                    4
+#define BM_AUDIOIN_CTRL_LOOPBACK                    0x10
+#define BF_AUDIOIN_CTRL_LOOPBACK(v)                 (((v) & 0x1) << 4)
+#define BFM_AUDIOIN_CTRL_LOOPBACK(v)                BM_AUDIOIN_CTRL_LOOPBACK
+#define BF_AUDIOIN_CTRL_LOOPBACK_V(e)               BF_AUDIOIN_CTRL_LOOPBACK(BV_AUDIOIN_CTRL_LOOPBACK__##e)
+#define BFM_AUDIOIN_CTRL_LOOPBACK_V(v)              BM_AUDIOIN_CTRL_LOOPBACK
+#define BP_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ          3
+#define BM_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ          0x8
+#define BF_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ(v)       (((v) & 0x1) << 3)
+#define BFM_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ(v)      BM_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ
+#define BF_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ_V(e)     BF_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ(BV_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ__##e)
+#define BFM_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ_V(v)    BM_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ
+#define BP_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ           2
+#define BM_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ           0x4
+#define BF_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ(v)        (((v) & 0x1) << 2)
+#define BFM_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ(v)       BM_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ
+#define BF_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ_V(e)      BF_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ(BV_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ__##e)
+#define BFM_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ_V(v)     BM_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ
+#define BP_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN           1
+#define BM_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN           0x2
+#define BF_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN(v)        (((v) & 0x1) << 1)
+#define BFM_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN(v)       BM_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN
+#define BF_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN_V(e)      BF_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN(BV_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN__##e)
+#define BFM_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN_V(v)     BM_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN
+#define BP_AUDIOIN_CTRL_RUN                         0
+#define BM_AUDIOIN_CTRL_RUN                         0x1
+#define BF_AUDIOIN_CTRL_RUN(v)                      (((v) & 0x1) << 0)
+#define BFM_AUDIOIN_CTRL_RUN(v)                     BM_AUDIOIN_CTRL_RUN
+#define BF_AUDIOIN_CTRL_RUN_V(e)                    BF_AUDIOIN_CTRL_RUN(BV_AUDIOIN_CTRL_RUN__##e)
+#define BFM_AUDIOIN_CTRL_RUN_V(v)                   BM_AUDIOIN_CTRL_RUN
+
+#define HW_AUDIOIN_STAT                     HW(AUDIOIN_STAT)
+#define HWA_AUDIOIN_STAT                    (0x8004c000 + 0x10)
+#define HWT_AUDIOIN_STAT                    HWIO_32_RW
+#define HWN_AUDIOIN_STAT                    AUDIOIN_STAT
+#define HWI_AUDIOIN_STAT                    
+#define BP_AUDIOIN_STAT_ADC_PRESENT         31
+#define BM_AUDIOIN_STAT_ADC_PRESENT         0x80000000
+#define BF_AUDIOIN_STAT_ADC_PRESENT(v)      (((v) & 0x1) << 31)
+#define BFM_AUDIOIN_STAT_ADC_PRESENT(v)     BM_AUDIOIN_STAT_ADC_PRESENT
+#define BF_AUDIOIN_STAT_ADC_PRESENT_V(e)    BF_AUDIOIN_STAT_ADC_PRESENT(BV_AUDIOIN_STAT_ADC_PRESENT__##e)
+#define BFM_AUDIOIN_STAT_ADC_PRESENT_V(v)   BM_AUDIOIN_STAT_ADC_PRESENT
+
+#define HW_AUDIOIN_ADCSRR                       HW(AUDIOIN_ADCSRR)
+#define HWA_AUDIOIN_ADCSRR                      (0x8004c000 + 0x20)
+#define HWT_AUDIOIN_ADCSRR                      HWIO_32_RW
+#define HWN_AUDIOIN_ADCSRR                      AUDIOIN_ADCSRR
+#define HWI_AUDIOIN_ADCSRR                      
+#define HW_AUDIOIN_ADCSRR_SET                   HW(AUDIOIN_ADCSRR_SET)
+#define HWA_AUDIOIN_ADCSRR_SET                  (HWA_AUDIOIN_ADCSRR + 0x4)
+#define HWT_AUDIOIN_ADCSRR_SET                  HWIO_32_WO
+#define HWN_AUDIOIN_ADCSRR_SET                  AUDIOIN_ADCSRR
+#define HWI_AUDIOIN_ADCSRR_SET                  
+#define HW_AUDIOIN_ADCSRR_CLR                   HW(AUDIOIN_ADCSRR_CLR)
+#define HWA_AUDIOIN_ADCSRR_CLR                  (HWA_AUDIOIN_ADCSRR + 0x8)
+#define HWT_AUDIOIN_ADCSRR_CLR                  HWIO_32_WO
+#define HWN_AUDIOIN_ADCSRR_CLR                  AUDIOIN_ADCSRR
+#define HWI_AUDIOIN_ADCSRR_CLR                  
+#define HW_AUDIOIN_ADCSRR_TOG                   HW(AUDIOIN_ADCSRR_TOG)
+#define HWA_AUDIOIN_ADCSRR_TOG                  (HWA_AUDIOIN_ADCSRR + 0xc)
+#define HWT_AUDIOIN_ADCSRR_TOG                  HWIO_32_WO
+#define HWN_AUDIOIN_ADCSRR_TOG                  AUDIOIN_ADCSRR
+#define HWI_AUDIOIN_ADCSRR_TOG                  
+#define BP_AUDIOIN_ADCSRR_OSR                   31
+#define BM_AUDIOIN_ADCSRR_OSR                   0x80000000
+#define BV_AUDIOIN_ADCSRR_OSR__OSR6             0x0
+#define BV_AUDIOIN_ADCSRR_OSR__OSR12            0x1
+#define BF_AUDIOIN_ADCSRR_OSR(v)                (((v) & 0x1) << 31)
+#define BFM_AUDIOIN_ADCSRR_OSR(v)               BM_AUDIOIN_ADCSRR_OSR
+#define BF_AUDIOIN_ADCSRR_OSR_V(e)              BF_AUDIOIN_ADCSRR_OSR(BV_AUDIOIN_ADCSRR_OSR__##e)
+#define BFM_AUDIOIN_ADCSRR_OSR_V(v)             BM_AUDIOIN_ADCSRR_OSR
+#define BP_AUDIOIN_ADCSRR_BASEMULT              28
+#define BM_AUDIOIN_ADCSRR_BASEMULT              0x70000000
+#define BV_AUDIOIN_ADCSRR_BASEMULT__SINGLE_RATE 0x1
+#define BV_AUDIOIN_ADCSRR_BASEMULT__DOUBLE_RATE 0x2
+#define BV_AUDIOIN_ADCSRR_BASEMULT__QUAD_RATE   0x4
+#define BF_AUDIOIN_ADCSRR_BASEMULT(v)           (((v) & 0x7) << 28)
+#define BFM_AUDIOIN_ADCSRR_BASEMULT(v)          BM_AUDIOIN_ADCSRR_BASEMULT
+#define BF_AUDIOIN_ADCSRR_BASEMULT_V(e)         BF_AUDIOIN_ADCSRR_BASEMULT(BV_AUDIOIN_ADCSRR_BASEMULT__##e)
+#define BFM_AUDIOIN_ADCSRR_BASEMULT_V(v)        BM_AUDIOIN_ADCSRR_BASEMULT
+#define BP_AUDIOIN_ADCSRR_SRC_HOLD              24
+#define BM_AUDIOIN_ADCSRR_SRC_HOLD              0x7000000
+#define BF_AUDIOIN_ADCSRR_SRC_HOLD(v)           (((v) & 0x7) << 24)
+#define BFM_AUDIOIN_ADCSRR_SRC_HOLD(v)          BM_AUDIOIN_ADCSRR_SRC_HOLD
+#define BF_AUDIOIN_ADCSRR_SRC_HOLD_V(e)         BF_AUDIOIN_ADCSRR_SRC_HOLD(BV_AUDIOIN_ADCSRR_SRC_HOLD__##e)
+#define BFM_AUDIOIN_ADCSRR_SRC_HOLD_V(v)        BM_AUDIOIN_ADCSRR_SRC_HOLD
+#define BP_AUDIOIN_ADCSRR_SRC_INT               16
+#define BM_AUDIOIN_ADCSRR_SRC_INT               0x1f0000
+#define BF_AUDIOIN_ADCSRR_SRC_INT(v)            (((v) & 0x1f) << 16)
+#define BFM_AUDIOIN_ADCSRR_SRC_INT(v)           BM_AUDIOIN_ADCSRR_SRC_INT
+#define BF_AUDIOIN_ADCSRR_SRC_INT_V(e)          BF_AUDIOIN_ADCSRR_SRC_INT(BV_AUDIOIN_ADCSRR_SRC_INT__##e)
+#define BFM_AUDIOIN_ADCSRR_SRC_INT_V(v)         BM_AUDIOIN_ADCSRR_SRC_INT
+#define BP_AUDIOIN_ADCSRR_SRC_FRAC              0
+#define BM_AUDIOIN_ADCSRR_SRC_FRAC              0x1fff
+#define BF_AUDIOIN_ADCSRR_SRC_FRAC(v)           (((v) & 0x1fff) << 0)
+#define BFM_AUDIOIN_ADCSRR_SRC_FRAC(v)          BM_AUDIOIN_ADCSRR_SRC_FRAC
+#define BF_AUDIOIN_ADCSRR_SRC_FRAC_V(e)         BF_AUDIOIN_ADCSRR_SRC_FRAC(BV_AUDIOIN_ADCSRR_SRC_FRAC__##e)
+#define BFM_AUDIOIN_ADCSRR_SRC_FRAC_V(v)        BM_AUDIOIN_ADCSRR_SRC_FRAC
+
+#define HW_AUDIOIN_ADCVOLUME                            HW(AUDIOIN_ADCVOLUME)
+#define HWA_AUDIOIN_ADCVOLUME                           (0x8004c000 + 0x30)
+#define HWT_AUDIOIN_ADCVOLUME                           HWIO_32_RW
+#define HWN_AUDIOIN_ADCVOLUME                           AUDIOIN_ADCVOLUME
+#define HWI_AUDIOIN_ADCVOLUME                           
+#define HW_AUDIOIN_ADCVOLUME_SET                        HW(AUDIOIN_ADCVOLUME_SET)
+#define HWA_AUDIOIN_ADCVOLUME_SET                       (HWA_AUDIOIN_ADCVOLUME + 0x4)
+#define HWT_AUDIOIN_ADCVOLUME_SET                       HWIO_32_WO
+#define HWN_AUDIOIN_ADCVOLUME_SET                       AUDIOIN_ADCVOLUME
+#define HWI_AUDIOIN_ADCVOLUME_SET                       
+#define HW_AUDIOIN_ADCVOLUME_CLR                        HW(AUDIOIN_ADCVOLUME_CLR)
+#define HWA_AUDIOIN_ADCVOLUME_CLR                       (HWA_AUDIOIN_ADCVOLUME + 0x8)
+#define HWT_AUDIOIN_ADCVOLUME_CLR                       HWIO_32_WO
+#define HWN_AUDIOIN_ADCVOLUME_CLR                       AUDIOIN_ADCVOLUME
+#define HWI_AUDIOIN_ADCVOLUME_CLR                       
+#define HW_AUDIOIN_ADCVOLUME_TOG                        HW(AUDIOIN_ADCVOLUME_TOG)
+#define HWA_AUDIOIN_ADCVOLUME_TOG                       (HWA_AUDIOIN_ADCVOLUME + 0xc)
+#define HWT_AUDIOIN_ADCVOLUME_TOG                       HWIO_32_WO
+#define HWN_AUDIOIN_ADCVOLUME_TOG                       AUDIOIN_ADCVOLUME
+#define HWI_AUDIOIN_ADCVOLUME_TOG                       
+#define BP_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_LEFT         28
+#define BM_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_LEFT         0x10000000
+#define BF_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_LEFT(v)      (((v) & 0x1) << 28)
+#define BFM_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_LEFT(v)     BM_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_LEFT
+#define BF_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_LEFT_V(e)    BF_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_LEFT(BV_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_LEFT__##e)
+#define BFM_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_LEFT_V(v)   BM_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_LEFT
+#define BP_AUDIOIN_ADCVOLUME_EN_ZCD                     25
+#define BM_AUDIOIN_ADCVOLUME_EN_ZCD                     0x2000000
+#define BF_AUDIOIN_ADCVOLUME_EN_ZCD(v)                  (((v) & 0x1) << 25)
+#define BFM_AUDIOIN_ADCVOLUME_EN_ZCD(v)                 BM_AUDIOIN_ADCVOLUME_EN_ZCD
+#define BF_AUDIOIN_ADCVOLUME_EN_ZCD_V(e)                BF_AUDIOIN_ADCVOLUME_EN_ZCD(BV_AUDIOIN_ADCVOLUME_EN_ZCD__##e)
+#define BFM_AUDIOIN_ADCVOLUME_EN_ZCD_V(v)               BM_AUDIOIN_ADCVOLUME_EN_ZCD
+#define BP_AUDIOIN_ADCVOLUME_VOLUME_LEFT                16
+#define BM_AUDIOIN_ADCVOLUME_VOLUME_LEFT                0xff0000
+#define BF_AUDIOIN_ADCVOLUME_VOLUME_LEFT(v)             (((v) & 0xff) << 16)
+#define BFM_AUDIOIN_ADCVOLUME_VOLUME_LEFT(v)            BM_AUDIOIN_ADCVOLUME_VOLUME_LEFT
+#define BF_AUDIOIN_ADCVOLUME_VOLUME_LEFT_V(e)           BF_AUDIOIN_ADCVOLUME_VOLUME_LEFT(BV_AUDIOIN_ADCVOLUME_VOLUME_LEFT__##e)
+#define BFM_AUDIOIN_ADCVOLUME_VOLUME_LEFT_V(v)          BM_AUDIOIN_ADCVOLUME_VOLUME_LEFT
+#define BP_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_RIGHT        12
+#define BM_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_RIGHT        0x1000
+#define BF_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_RIGHT(v)     (((v) & 0x1) << 12)
+#define BFM_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_RIGHT(v)    BM_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_RIGHT
+#define BF_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_RIGHT_V(e)   BF_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_RIGHT(BV_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_RIGHT__##e)
+#define BFM_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_RIGHT_V(v)  BM_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_RIGHT
+#define BP_AUDIOIN_ADCVOLUME_VOLUME_RIGHT               0
+#define BM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT               0xff
+#define BF_AUDIOIN_ADCVOLUME_VOLUME_RIGHT(v)            (((v) & 0xff) << 0)
+#define BFM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT(v)           BM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT
+#define BF_AUDIOIN_ADCVOLUME_VOLUME_RIGHT_V(e)          BF_AUDIOIN_ADCVOLUME_VOLUME_RIGHT(BV_AUDIOIN_ADCVOLUME_VOLUME_RIGHT__##e)
+#define BFM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT_V(v)         BM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT
+
+#define HW_AUDIOIN_ADCDEBUG                                         HW(AUDIOIN_ADCDEBUG)
+#define HWA_AUDIOIN_ADCDEBUG                                        (0x8004c000 + 0x40)
+#define HWT_AUDIOIN_ADCDEBUG                                        HWIO_32_RW
+#define HWN_AUDIOIN_ADCDEBUG                                        AUDIOIN_ADCDEBUG
+#define HWI_AUDIOIN_ADCDEBUG                                        
+#define HW_AUDIOIN_ADCDEBUG_SET                                     HW(AUDIOIN_ADCDEBUG_SET)
+#define HWA_AUDIOIN_ADCDEBUG_SET                                    (HWA_AUDIOIN_ADCDEBUG + 0x4)
+#define HWT_AUDIOIN_ADCDEBUG_SET                                    HWIO_32_WO
+#define HWN_AUDIOIN_ADCDEBUG_SET                                    AUDIOIN_ADCDEBUG
+#define HWI_AUDIOIN_ADCDEBUG_SET                                    
+#define HW_AUDIOIN_ADCDEBUG_CLR                                     HW(AUDIOIN_ADCDEBUG_CLR)
+#define HWA_AUDIOIN_ADCDEBUG_CLR                                    (HWA_AUDIOIN_ADCDEBUG + 0x8)
+#define HWT_AUDIOIN_ADCDEBUG_CLR                                    HWIO_32_WO
+#define HWN_AUDIOIN_ADCDEBUG_CLR                                    AUDIOIN_ADCDEBUG
+#define HWI_AUDIOIN_ADCDEBUG_CLR                                    
+#define HW_AUDIOIN_ADCDEBUG_TOG                                     HW(AUDIOIN_ADCDEBUG_TOG)
+#define HWA_AUDIOIN_ADCDEBUG_TOG                                    (HWA_AUDIOIN_ADCDEBUG + 0xc)
+#define HWT_AUDIOIN_ADCDEBUG_TOG                                    HWIO_32_WO
+#define HWN_AUDIOIN_ADCDEBUG_TOG                                    AUDIOIN_ADCDEBUG
+#define HWI_AUDIOIN_ADCDEBUG_TOG                                    
+#define BP_AUDIOIN_ADCDEBUG_ENABLE_ADCDMA                           31
+#define BM_AUDIOIN_ADCDEBUG_ENABLE_ADCDMA                           0x80000000
+#define BF_AUDIOIN_ADCDEBUG_ENABLE_ADCDMA(v)                        (((v) & 0x1) << 31)
+#define BFM_AUDIOIN_ADCDEBUG_ENABLE_ADCDMA(v)                       BM_AUDIOIN_ADCDEBUG_ENABLE_ADCDMA
+#define BF_AUDIOIN_ADCDEBUG_ENABLE_ADCDMA_V(e)                      BF_AUDIOIN_ADCDEBUG_ENABLE_ADCDMA(BV_AUDIOIN_ADCDEBUG_ENABLE_ADCDMA__##e)
+#define BFM_AUDIOIN_ADCDEBUG_ENABLE_ADCDMA_V(v)                     BM_AUDIOIN_ADCDEBUG_ENABLE_ADCDMA
+#define BP_AUDIOIN_ADCDEBUG_ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS        3
+#define BM_AUDIOIN_ADCDEBUG_ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS        0x8
+#define BF_AUDIOIN_ADCDEBUG_ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS(v)     (((v) & 0x1) << 3)
+#define BFM_AUDIOIN_ADCDEBUG_ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS(v)    BM_AUDIOIN_ADCDEBUG_ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS
+#define BF_AUDIOIN_ADCDEBUG_ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS_V(e)   BF_AUDIOIN_ADCDEBUG_ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS(BV_AUDIOIN_ADCDEBUG_ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS__##e)
+#define BFM_AUDIOIN_ADCDEBUG_ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS_V(v)  BM_AUDIOIN_ADCDEBUG_ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS
+#define BP_AUDIOIN_ADCDEBUG_SET_INTERRUPT3_HAND_SHAKE               2
+#define BM_AUDIOIN_ADCDEBUG_SET_INTERRUPT3_HAND_SHAKE               0x4
+#define BF_AUDIOIN_ADCDEBUG_SET_INTERRUPT3_HAND_SHAKE(v)            (((v) & 0x1) << 2)
+#define BFM_AUDIOIN_ADCDEBUG_SET_INTERRUPT3_HAND_SHAKE(v)           BM_AUDIOIN_ADCDEBUG_SET_INTERRUPT3_HAND_SHAKE
+#define BF_AUDIOIN_ADCDEBUG_SET_INTERRUPT3_HAND_SHAKE_V(e)          BF_AUDIOIN_ADCDEBUG_SET_INTERRUPT3_HAND_SHAKE(BV_AUDIOIN_ADCDEBUG_SET_INTERRUPT3_HAND_SHAKE__##e)
+#define BFM_AUDIOIN_ADCDEBUG_SET_INTERRUPT3_HAND_SHAKE_V(v)         BM_AUDIOIN_ADCDEBUG_SET_INTERRUPT3_HAND_SHAKE
+#define BP_AUDIOIN_ADCDEBUG_DMA_PREQ                                1
+#define BM_AUDIOIN_ADCDEBUG_DMA_PREQ                                0x2
+#define BF_AUDIOIN_ADCDEBUG_DMA_PREQ(v)                             (((v) & 0x1) << 1)
+#define BFM_AUDIOIN_ADCDEBUG_DMA_PREQ(v)                            BM_AUDIOIN_ADCDEBUG_DMA_PREQ
+#define BF_AUDIOIN_ADCDEBUG_DMA_PREQ_V(e)                           BF_AUDIOIN_ADCDEBUG_DMA_PREQ(BV_AUDIOIN_ADCDEBUG_DMA_PREQ__##e)
+#define BFM_AUDIOIN_ADCDEBUG_DMA_PREQ_V(v)                          BM_AUDIOIN_ADCDEBUG_DMA_PREQ
+#define BP_AUDIOIN_ADCDEBUG_FIFO_STATUS                             0
+#define BM_AUDIOIN_ADCDEBUG_FIFO_STATUS                             0x1
+#define BF_AUDIOIN_ADCDEBUG_FIFO_STATUS(v)                          (((v) & 0x1) << 0)
+#define BFM_AUDIOIN_ADCDEBUG_FIFO_STATUS(v)                         BM_AUDIOIN_ADCDEBUG_FIFO_STATUS
+#define BF_AUDIOIN_ADCDEBUG_FIFO_STATUS_V(e)                        BF_AUDIOIN_ADCDEBUG_FIFO_STATUS(BV_AUDIOIN_ADCDEBUG_FIFO_STATUS__##e)
+#define BFM_AUDIOIN_ADCDEBUG_FIFO_STATUS_V(v)                       BM_AUDIOIN_ADCDEBUG_FIFO_STATUS
+
+#define HW_AUDIOIN_ADCVOL                       HW(AUDIOIN_ADCVOL)
+#define HWA_AUDIOIN_ADCVOL                      (0x8004c000 + 0x50)
+#define HWT_AUDIOIN_ADCVOL                      HWIO_32_RW
+#define HWN_AUDIOIN_ADCVOL                      AUDIOIN_ADCVOL
+#define HWI_AUDIOIN_ADCVOL                      
+#define HW_AUDIOIN_ADCVOL_SET                   HW(AUDIOIN_ADCVOL_SET)
+#define HWA_AUDIOIN_ADCVOL_SET                  (HWA_AUDIOIN_ADCVOL + 0x4)
+#define HWT_AUDIOIN_ADCVOL_SET                  HWIO_32_WO
+#define HWN_AUDIOIN_ADCVOL_SET                  AUDIOIN_ADCVOL
+#define HWI_AUDIOIN_ADCVOL_SET                  
+#define HW_AUDIOIN_ADCVOL_CLR                   HW(AUDIOIN_ADCVOL_CLR)
+#define HWA_AUDIOIN_ADCVOL_CLR                  (HWA_AUDIOIN_ADCVOL + 0x8)
+#define HWT_AUDIOIN_ADCVOL_CLR                  HWIO_32_WO
+#define HWN_AUDIOIN_ADCVOL_CLR                  AUDIOIN_ADCVOL
+#define HWI_AUDIOIN_ADCVOL_CLR                  
+#define HW_AUDIOIN_ADCVOL_TOG                   HW(AUDIOIN_ADCVOL_TOG)
+#define HWA_AUDIOIN_ADCVOL_TOG                  (HWA_AUDIOIN_ADCVOL + 0xc)
+#define HWT_AUDIOIN_ADCVOL_TOG                  HWIO_32_WO
+#define HWN_AUDIOIN_ADCVOL_TOG                  AUDIOIN_ADCVOL
+#define HWI_AUDIOIN_ADCVOL_TOG                  
+#define BP_AUDIOIN_ADCVOL_SELECT_LEFT           28
+#define BM_AUDIOIN_ADCVOL_SELECT_LEFT           0x30000000
+#define BF_AUDIOIN_ADCVOL_SELECT_LEFT(v)        (((v) & 0x3) << 28)
+#define BFM_AUDIOIN_ADCVOL_SELECT_LEFT(v)       BM_AUDIOIN_ADCVOL_SELECT_LEFT
+#define BF_AUDIOIN_ADCVOL_SELECT_LEFT_V(e)      BF_AUDIOIN_ADCVOL_SELECT_LEFT(BV_AUDIOIN_ADCVOL_SELECT_LEFT__##e)
+#define BFM_AUDIOIN_ADCVOL_SELECT_LEFT_V(v)     BM_AUDIOIN_ADCVOL_SELECT_LEFT
+#define BP_AUDIOIN_ADCVOL_SELECT_RIGHT          24
+#define BM_AUDIOIN_ADCVOL_SELECT_RIGHT          0x3000000
+#define BF_AUDIOIN_ADCVOL_SELECT_RIGHT(v)       (((v) & 0x3) << 24)
+#define BFM_AUDIOIN_ADCVOL_SELECT_RIGHT(v)      BM_AUDIOIN_ADCVOL_SELECT_RIGHT
+#define BF_AUDIOIN_ADCVOL_SELECT_RIGHT_V(e)     BF_AUDIOIN_ADCVOL_SELECT_RIGHT(BV_AUDIOIN_ADCVOL_SELECT_RIGHT__##e)
+#define BFM_AUDIOIN_ADCVOL_SELECT_RIGHT_V(v)    BM_AUDIOIN_ADCVOL_SELECT_RIGHT
+#define BP_AUDIOIN_ADCVOL_MUTE                  8
+#define BM_AUDIOIN_ADCVOL_MUTE                  0x100
+#define BF_AUDIOIN_ADCVOL_MUTE(v)               (((v) & 0x1) << 8)
+#define BFM_AUDIOIN_ADCVOL_MUTE(v)              BM_AUDIOIN_ADCVOL_MUTE
+#define BF_AUDIOIN_ADCVOL_MUTE_V(e)             BF_AUDIOIN_ADCVOL_MUTE(BV_AUDIOIN_ADCVOL_MUTE__##e)
+#define BFM_AUDIOIN_ADCVOL_MUTE_V(v)            BM_AUDIOIN_ADCVOL_MUTE
+#define BP_AUDIOIN_ADCVOL_GAIN_LEFT             4
+#define BM_AUDIOIN_ADCVOL_GAIN_LEFT             0xf0
+#define BF_AUDIOIN_ADCVOL_GAIN_LEFT(v)          (((v) & 0xf) << 4)
+#define BFM_AUDIOIN_ADCVOL_GAIN_LEFT(v)         BM_AUDIOIN_ADCVOL_GAIN_LEFT
+#define BF_AUDIOIN_ADCVOL_GAIN_LEFT_V(e)        BF_AUDIOIN_ADCVOL_GAIN_LEFT(BV_AUDIOIN_ADCVOL_GAIN_LEFT__##e)
+#define BFM_AUDIOIN_ADCVOL_GAIN_LEFT_V(v)       BM_AUDIOIN_ADCVOL_GAIN_LEFT
+#define BP_AUDIOIN_ADCVOL_GAIN_RIGHT            0
+#define BM_AUDIOIN_ADCVOL_GAIN_RIGHT            0xf
+#define BF_AUDIOIN_ADCVOL_GAIN_RIGHT(v)         (((v) & 0xf) << 0)
+#define BFM_AUDIOIN_ADCVOL_GAIN_RIGHT(v)        BM_AUDIOIN_ADCVOL_GAIN_RIGHT
+#define BF_AUDIOIN_ADCVOL_GAIN_RIGHT_V(e)       BF_AUDIOIN_ADCVOL_GAIN_RIGHT(BV_AUDIOIN_ADCVOL_GAIN_RIGHT__##e)
+#define BFM_AUDIOIN_ADCVOL_GAIN_RIGHT_V(v)      BM_AUDIOIN_ADCVOL_GAIN_RIGHT
+
+#define HW_AUDIOIN_MICLINE                          HW(AUDIOIN_MICLINE)
+#define HWA_AUDIOIN_MICLINE                         (0x8004c000 + 0x60)
+#define HWT_AUDIOIN_MICLINE                         HWIO_32_RW
+#define HWN_AUDIOIN_MICLINE                         AUDIOIN_MICLINE
+#define HWI_AUDIOIN_MICLINE                         
+#define HW_AUDIOIN_MICLINE_SET                      HW(AUDIOIN_MICLINE_SET)
+#define HWA_AUDIOIN_MICLINE_SET                     (HWA_AUDIOIN_MICLINE + 0x4)
+#define HWT_AUDIOIN_MICLINE_SET                     HWIO_32_WO
+#define HWN_AUDIOIN_MICLINE_SET                     AUDIOIN_MICLINE
+#define HWI_AUDIOIN_MICLINE_SET                     
+#define HW_AUDIOIN_MICLINE_CLR                      HW(AUDIOIN_MICLINE_CLR)
+#define HWA_AUDIOIN_MICLINE_CLR                     (HWA_AUDIOIN_MICLINE + 0x8)
+#define HWT_AUDIOIN_MICLINE_CLR                     HWIO_32_WO
+#define HWN_AUDIOIN_MICLINE_CLR                     AUDIOIN_MICLINE
+#define HWI_AUDIOIN_MICLINE_CLR                     
+#define HW_AUDIOIN_MICLINE_TOG                      HW(AUDIOIN_MICLINE_TOG)
+#define HWA_AUDIOIN_MICLINE_TOG                     (HWA_AUDIOIN_MICLINE + 0xc)
+#define HWT_AUDIOIN_MICLINE_TOG                     HWIO_32_WO
+#define HWN_AUDIOIN_MICLINE_TOG                     AUDIOIN_MICLINE
+#define HWI_AUDIOIN_MICLINE_TOG                     
+#define BP_AUDIOIN_MICLINE_ATTEN_LINE               30
+#define BM_AUDIOIN_MICLINE_ATTEN_LINE               0x40000000
+#define BF_AUDIOIN_MICLINE_ATTEN_LINE(v)            (((v) & 0x1) << 30)
+#define BFM_AUDIOIN_MICLINE_ATTEN_LINE(v)           BM_AUDIOIN_MICLINE_ATTEN_LINE
+#define BF_AUDIOIN_MICLINE_ATTEN_LINE_V(e)          BF_AUDIOIN_MICLINE_ATTEN_LINE(BV_AUDIOIN_MICLINE_ATTEN_LINE__##e)
+#define BFM_AUDIOIN_MICLINE_ATTEN_LINE_V(v)         BM_AUDIOIN_MICLINE_ATTEN_LINE
+#define BP_AUDIOIN_MICLINE_DIVIDE_LINE1             29
+#define BM_AUDIOIN_MICLINE_DIVIDE_LINE1             0x20000000
+#define BF_AUDIOIN_MICLINE_DIVIDE_LINE1(v)          (((v) & 0x1) << 29)
+#define BFM_AUDIOIN_MICLINE_DIVIDE_LINE1(v)         BM_AUDIOIN_MICLINE_DIVIDE_LINE1
+#define BF_AUDIOIN_MICLINE_DIVIDE_LINE1_V(e)        BF_AUDIOIN_MICLINE_DIVIDE_LINE1(BV_AUDIOIN_MICLINE_DIVIDE_LINE1__##e)
+#define BFM_AUDIOIN_MICLINE_DIVIDE_LINE1_V(v)       BM_AUDIOIN_MICLINE_DIVIDE_LINE1
+#define BP_AUDIOIN_MICLINE_DIVIDE_LINE2             28
+#define BM_AUDIOIN_MICLINE_DIVIDE_LINE2             0x10000000
+#define BF_AUDIOIN_MICLINE_DIVIDE_LINE2(v)          (((v) & 0x1) << 28)
+#define BFM_AUDIOIN_MICLINE_DIVIDE_LINE2(v)         BM_AUDIOIN_MICLINE_DIVIDE_LINE2
+#define BF_AUDIOIN_MICLINE_DIVIDE_LINE2_V(e)        BF_AUDIOIN_MICLINE_DIVIDE_LINE2(BV_AUDIOIN_MICLINE_DIVIDE_LINE2__##e)
+#define BFM_AUDIOIN_MICLINE_DIVIDE_LINE2_V(v)       BM_AUDIOIN_MICLINE_DIVIDE_LINE2
+#define BP_AUDIOIN_MICLINE_MIC_SELECT               24
+#define BM_AUDIOIN_MICLINE_MIC_SELECT               0x1000000
+#define BF_AUDIOIN_MICLINE_MIC_SELECT(v)            (((v) & 0x1) << 24)
+#define BFM_AUDIOIN_MICLINE_MIC_SELECT(v)           BM_AUDIOIN_MICLINE_MIC_SELECT
+#define BF_AUDIOIN_MICLINE_MIC_SELECT_V(e)          BF_AUDIOIN_MICLINE_MIC_SELECT(BV_AUDIOIN_MICLINE_MIC_SELECT__##e)
+#define BFM_AUDIOIN_MICLINE_MIC_SELECT_V(v)         BM_AUDIOIN_MICLINE_MIC_SELECT
+#define BP_AUDIOIN_MICLINE_MIC_RESISTOR             20
+#define BM_AUDIOIN_MICLINE_MIC_RESISTOR             0x300000
+#define BV_AUDIOIN_MICLINE_MIC_RESISTOR__Off        0x0
+#define BV_AUDIOIN_MICLINE_MIC_RESISTOR__2KOhm      0x1
+#define BV_AUDIOIN_MICLINE_MIC_RESISTOR__4KOhm      0x2
+#define BV_AUDIOIN_MICLINE_MIC_RESISTOR__8KOhm      0x3
+#define BF_AUDIOIN_MICLINE_MIC_RESISTOR(v)          (((v) & 0x3) << 20)
+#define BFM_AUDIOIN_MICLINE_MIC_RESISTOR(v)         BM_AUDIOIN_MICLINE_MIC_RESISTOR
+#define BF_AUDIOIN_MICLINE_MIC_RESISTOR_V(e)        BF_AUDIOIN_MICLINE_MIC_RESISTOR(BV_AUDIOIN_MICLINE_MIC_RESISTOR__##e)
+#define BFM_AUDIOIN_MICLINE_MIC_RESISTOR_V(v)       BM_AUDIOIN_MICLINE_MIC_RESISTOR
+#define BP_AUDIOIN_MICLINE_MIC_BIAS                 16
+#define BM_AUDIOIN_MICLINE_MIC_BIAS                 0x70000
+#define BF_AUDIOIN_MICLINE_MIC_BIAS(v)              (((v) & 0x7) << 16)
+#define BFM_AUDIOIN_MICLINE_MIC_BIAS(v)             BM_AUDIOIN_MICLINE_MIC_BIAS
+#define BF_AUDIOIN_MICLINE_MIC_BIAS_V(e)            BF_AUDIOIN_MICLINE_MIC_BIAS(BV_AUDIOIN_MICLINE_MIC_BIAS__##e)
+#define BFM_AUDIOIN_MICLINE_MIC_BIAS_V(v)           BM_AUDIOIN_MICLINE_MIC_BIAS
+#define BP_AUDIOIN_MICLINE_FORCE_MICAMP_PWRUP       8
+#define BM_AUDIOIN_MICLINE_FORCE_MICAMP_PWRUP       0x100
+#define BF_AUDIOIN_MICLINE_FORCE_MICAMP_PWRUP(v)    (((v) & 0x1) << 8)
+#define BFM_AUDIOIN_MICLINE_FORCE_MICAMP_PWRUP(v)   BM_AUDIOIN_MICLINE_FORCE_MICAMP_PWRUP
+#define BF_AUDIOIN_MICLINE_FORCE_MICAMP_PWRUP_V(e)  BF_AUDIOIN_MICLINE_FORCE_MICAMP_PWRUP(BV_AUDIOIN_MICLINE_FORCE_MICAMP_PWRUP__##e)
+#define BFM_AUDIOIN_MICLINE_FORCE_MICAMP_PWRUP_V(v) BM_AUDIOIN_MICLINE_FORCE_MICAMP_PWRUP
+#define BP_AUDIOIN_MICLINE_MIC_GAIN                 0
+#define BM_AUDIOIN_MICLINE_MIC_GAIN                 0x3
+#define BV_AUDIOIN_MICLINE_MIC_GAIN__0dB            0x0
+#define BV_AUDIOIN_MICLINE_MIC_GAIN__20dB           0x1
+#define BV_AUDIOIN_MICLINE_MIC_GAIN__30dB           0x2
+#define BV_AUDIOIN_MICLINE_MIC_GAIN__40dB           0x3
+#define BF_AUDIOIN_MICLINE_MIC_GAIN(v)              (((v) & 0x3) << 0)
+#define BFM_AUDIOIN_MICLINE_MIC_GAIN(v)             BM_AUDIOIN_MICLINE_MIC_GAIN
+#define BF_AUDIOIN_MICLINE_MIC_GAIN_V(e)            BF_AUDIOIN_MICLINE_MIC_GAIN(BV_AUDIOIN_MICLINE_MIC_GAIN__##e)
+#define BFM_AUDIOIN_MICLINE_MIC_GAIN_V(v)           BM_AUDIOIN_MICLINE_MIC_GAIN
+
+#define HW_AUDIOIN_ANACLKCTRL                       HW(AUDIOIN_ANACLKCTRL)
+#define HWA_AUDIOIN_ANACLKCTRL                      (0x8004c000 + 0x70)
+#define HWT_AUDIOIN_ANACLKCTRL                      HWIO_32_RW
+#define HWN_AUDIOIN_ANACLKCTRL                      AUDIOIN_ANACLKCTRL
+#define HWI_AUDIOIN_ANACLKCTRL                      
+#define HW_AUDIOIN_ANACLKCTRL_SET                   HW(AUDIOIN_ANACLKCTRL_SET)
+#define HWA_AUDIOIN_ANACLKCTRL_SET                  (HWA_AUDIOIN_ANACLKCTRL + 0x4)
+#define HWT_AUDIOIN_ANACLKCTRL_SET                  HWIO_32_WO
+#define HWN_AUDIOIN_ANACLKCTRL_SET                  AUDIOIN_ANACLKCTRL
+#define HWI_AUDIOIN_ANACLKCTRL_SET                  
+#define HW_AUDIOIN_ANACLKCTRL_CLR                   HW(AUDIOIN_ANACLKCTRL_CLR)
+#define HWA_AUDIOIN_ANACLKCTRL_CLR                  (HWA_AUDIOIN_ANACLKCTRL + 0x8)
+#define HWT_AUDIOIN_ANACLKCTRL_CLR                  HWIO_32_WO
+#define HWN_AUDIOIN_ANACLKCTRL_CLR                  AUDIOIN_ANACLKCTRL
+#define HWI_AUDIOIN_ANACLKCTRL_CLR                  
+#define HW_AUDIOIN_ANACLKCTRL_TOG                   HW(AUDIOIN_ANACLKCTRL_TOG)
+#define HWA_AUDIOIN_ANACLKCTRL_TOG                  (HWA_AUDIOIN_ANACLKCTRL + 0xc)
+#define HWT_AUDIOIN_ANACLKCTRL_TOG                  HWIO_32_WO
+#define HWN_AUDIOIN_ANACLKCTRL_TOG                  AUDIOIN_ANACLKCTRL
+#define HWI_AUDIOIN_ANACLKCTRL_TOG                  
+#define BP_AUDIOIN_ANACLKCTRL_CLKGATE               31
+#define BM_AUDIOIN_ANACLKCTRL_CLKGATE               0x80000000
+#define BF_AUDIOIN_ANACLKCTRL_CLKGATE(v)            (((v) & 0x1) << 31)
+#define BFM_AUDIOIN_ANACLKCTRL_CLKGATE(v)           BM_AUDIOIN_ANACLKCTRL_CLKGATE
+#define BF_AUDIOIN_ANACLKCTRL_CLKGATE_V(e)          BF_AUDIOIN_ANACLKCTRL_CLKGATE(BV_AUDIOIN_ANACLKCTRL_CLKGATE__##e)
+#define BFM_AUDIOIN_ANACLKCTRL_CLKGATE_V(v)         BM_AUDIOIN_ANACLKCTRL_CLKGATE
+#define BP_AUDIOIN_ANACLKCTRL_DITHER_ENABLE         6
+#define BM_AUDIOIN_ANACLKCTRL_DITHER_ENABLE         0x40
+#define BF_AUDIOIN_ANACLKCTRL_DITHER_ENABLE(v)      (((v) & 0x1) << 6)
+#define BFM_AUDIOIN_ANACLKCTRL_DITHER_ENABLE(v)     BM_AUDIOIN_ANACLKCTRL_DITHER_ENABLE
+#define BF_AUDIOIN_ANACLKCTRL_DITHER_ENABLE_V(e)    BF_AUDIOIN_ANACLKCTRL_DITHER_ENABLE(BV_AUDIOIN_ANACLKCTRL_DITHER_ENABLE__##e)
+#define BFM_AUDIOIN_ANACLKCTRL_DITHER_ENABLE_V(v)   BM_AUDIOIN_ANACLKCTRL_DITHER_ENABLE
+#define BP_AUDIOIN_ANACLKCTRL_SLOW_DITHER           5
+#define BM_AUDIOIN_ANACLKCTRL_SLOW_DITHER           0x20
+#define BF_AUDIOIN_ANACLKCTRL_SLOW_DITHER(v)        (((v) & 0x1) << 5)
+#define BFM_AUDIOIN_ANACLKCTRL_SLOW_DITHER(v)       BM_AUDIOIN_ANACLKCTRL_SLOW_DITHER
+#define BF_AUDIOIN_ANACLKCTRL_SLOW_DITHER_V(e)      BF_AUDIOIN_ANACLKCTRL_SLOW_DITHER(BV_AUDIOIN_ANACLKCTRL_SLOW_DITHER__##e)
+#define BFM_AUDIOIN_ANACLKCTRL_SLOW_DITHER_V(v)     BM_AUDIOIN_ANACLKCTRL_SLOW_DITHER
+#define BP_AUDIOIN_ANACLKCTRL_INVERT_ADCCLK         4
+#define BM_AUDIOIN_ANACLKCTRL_INVERT_ADCCLK         0x10
+#define BF_AUDIOIN_ANACLKCTRL_INVERT_ADCCLK(v)      (((v) & 0x1) << 4)
+#define BFM_AUDIOIN_ANACLKCTRL_INVERT_ADCCLK(v)     BM_AUDIOIN_ANACLKCTRL_INVERT_ADCCLK
+#define BF_AUDIOIN_ANACLKCTRL_INVERT_ADCCLK_V(e)    BF_AUDIOIN_ANACLKCTRL_INVERT_ADCCLK(BV_AUDIOIN_ANACLKCTRL_INVERT_ADCCLK__##e)
+#define BFM_AUDIOIN_ANACLKCTRL_INVERT_ADCCLK_V(v)   BM_AUDIOIN_ANACLKCTRL_INVERT_ADCCLK
+#define BP_AUDIOIN_ANACLKCTRL_ADCDIV                0
+#define BM_AUDIOIN_ANACLKCTRL_ADCDIV                0x7
+#define BF_AUDIOIN_ANACLKCTRL_ADCDIV(v)             (((v) & 0x7) << 0)
+#define BFM_AUDIOIN_ANACLKCTRL_ADCDIV(v)            BM_AUDIOIN_ANACLKCTRL_ADCDIV
+#define BF_AUDIOIN_ANACLKCTRL_ADCDIV_V(e)           BF_AUDIOIN_ANACLKCTRL_ADCDIV(BV_AUDIOIN_ANACLKCTRL_ADCDIV__##e)
+#define BFM_AUDIOIN_ANACLKCTRL_ADCDIV_V(v)          BM_AUDIOIN_ANACLKCTRL_ADCDIV
+
+#define HW_AUDIOIN_DATA             HW(AUDIOIN_DATA)
+#define HWA_AUDIOIN_DATA            (0x8004c000 + 0x80)
+#define HWT_AUDIOIN_DATA            HWIO_32_RW
+#define HWN_AUDIOIN_DATA            AUDIOIN_DATA
+#define HWI_AUDIOIN_DATA            
+#define BP_AUDIOIN_DATA_HIGH        16
+#define BM_AUDIOIN_DATA_HIGH        0xffff0000
+#define BF_AUDIOIN_DATA_HIGH(v)     (((v) & 0xffff) << 16)
+#define BFM_AUDIOIN_DATA_HIGH(v)    BM_AUDIOIN_DATA_HIGH
+#define BF_AUDIOIN_DATA_HIGH_V(e)   BF_AUDIOIN_DATA_HIGH(BV_AUDIOIN_DATA_HIGH__##e)
+#define BFM_AUDIOIN_DATA_HIGH_V(v)  BM_AUDIOIN_DATA_HIGH
+#define BP_AUDIOIN_DATA_LOW         0
+#define BM_AUDIOIN_DATA_LOW         0xffff
+#define BF_AUDIOIN_DATA_LOW(v)      (((v) & 0xffff) << 0)
+#define BFM_AUDIOIN_DATA_LOW(v)     BM_AUDIOIN_DATA_LOW
+#define BF_AUDIOIN_DATA_LOW_V(e)    BF_AUDIOIN_DATA_LOW(BV_AUDIOIN_DATA_LOW__##e)
+#define BFM_AUDIOIN_DATA_LOW_V(v)   BM_AUDIOIN_DATA_LOW
+
+#endif /* __HEADERGEN_STMP3600_AUDIOIN_H__*/
diff --git a/firmware/target/arm/imx233/regs/stmp3600/audioout.h b/firmware/target/arm/imx233/regs/stmp3600/audioout.h
new file mode 100644
index 0000000000..13da63bc0a
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3600/audioout.h
@@ -0,0 +1,893 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * stmp3600 version: 2.4.0
+ * stmp3600 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_STMP3600_AUDIOOUT_H__
+#define __HEADERGEN_STMP3600_AUDIOOUT_H__
+
+#define HW_AUDIOOUT_CTRL                            HW(AUDIOOUT_CTRL)
+#define HWA_AUDIOOUT_CTRL                           (0x80048000 + 0x0)
+#define HWT_AUDIOOUT_CTRL                           HWIO_32_RW
+#define HWN_AUDIOOUT_CTRL                           AUDIOOUT_CTRL
+#define HWI_AUDIOOUT_CTRL                           
+#define HW_AUDIOOUT_CTRL_SET                        HW(AUDIOOUT_CTRL_SET)
+#define HWA_AUDIOOUT_CTRL_SET                       (HWA_AUDIOOUT_CTRL + 0x4)
+#define HWT_AUDIOOUT_CTRL_SET                       HWIO_32_WO
+#define HWN_AUDIOOUT_CTRL_SET                       AUDIOOUT_CTRL
+#define HWI_AUDIOOUT_CTRL_SET                       
+#define HW_AUDIOOUT_CTRL_CLR                        HW(AUDIOOUT_CTRL_CLR)
+#define HWA_AUDIOOUT_CTRL_CLR                       (HWA_AUDIOOUT_CTRL + 0x8)
+#define HWT_AUDIOOUT_CTRL_CLR                       HWIO_32_WO
+#define HWN_AUDIOOUT_CTRL_CLR                       AUDIOOUT_CTRL
+#define HWI_AUDIOOUT_CTRL_CLR                       
+#define HW_AUDIOOUT_CTRL_TOG                        HW(AUDIOOUT_CTRL_TOG)
+#define HWA_AUDIOOUT_CTRL_TOG                       (HWA_AUDIOOUT_CTRL + 0xc)
+#define HWT_AUDIOOUT_CTRL_TOG                       HWIO_32_WO
+#define HWN_AUDIOOUT_CTRL_TOG                       AUDIOOUT_CTRL
+#define HWI_AUDIOOUT_CTRL_TOG                       
+#define BP_AUDIOOUT_CTRL_SFTRST                     31
+#define BM_AUDIOOUT_CTRL_SFTRST                     0x80000000
+#define BF_AUDIOOUT_CTRL_SFTRST(v)                  (((v) & 0x1) << 31)
+#define BFM_AUDIOOUT_CTRL_SFTRST(v)                 BM_AUDIOOUT_CTRL_SFTRST
+#define BF_AUDIOOUT_CTRL_SFTRST_V(e)                BF_AUDIOOUT_CTRL_SFTRST(BV_AUDIOOUT_CTRL_SFTRST__##e)
+#define BFM_AUDIOOUT_CTRL_SFTRST_V(v)               BM_AUDIOOUT_CTRL_SFTRST
+#define BP_AUDIOOUT_CTRL_CLKGATE                    30
+#define BM_AUDIOOUT_CTRL_CLKGATE                    0x40000000
+#define BF_AUDIOOUT_CTRL_CLKGATE(v)                 (((v) & 0x1) << 30)
+#define BFM_AUDIOOUT_CTRL_CLKGATE(v)                BM_AUDIOOUT_CTRL_CLKGATE
+#define BF_AUDIOOUT_CTRL_CLKGATE_V(e)               BF_AUDIOOUT_CTRL_CLKGATE(BV_AUDIOOUT_CTRL_CLKGATE__##e)
+#define BFM_AUDIOOUT_CTRL_CLKGATE_V(v)              BM_AUDIOOUT_CTRL_CLKGATE
+#define BP_AUDIOOUT_CTRL_DMAWAIT_COUNT              16
+#define BM_AUDIOOUT_CTRL_DMAWAIT_COUNT              0x1f0000
+#define BF_AUDIOOUT_CTRL_DMAWAIT_COUNT(v)           (((v) & 0x1f) << 16)
+#define BFM_AUDIOOUT_CTRL_DMAWAIT_COUNT(v)          BM_AUDIOOUT_CTRL_DMAWAIT_COUNT
+#define BF_AUDIOOUT_CTRL_DMAWAIT_COUNT_V(e)         BF_AUDIOOUT_CTRL_DMAWAIT_COUNT(BV_AUDIOOUT_CTRL_DMAWAIT_COUNT__##e)
+#define BFM_AUDIOOUT_CTRL_DMAWAIT_COUNT_V(v)        BM_AUDIOOUT_CTRL_DMAWAIT_COUNT
+#define BP_AUDIOOUT_CTRL_LR_SWAP                    14
+#define BM_AUDIOOUT_CTRL_LR_SWAP                    0x4000
+#define BF_AUDIOOUT_CTRL_LR_SWAP(v)                 (((v) & 0x1) << 14)
+#define BFM_AUDIOOUT_CTRL_LR_SWAP(v)                BM_AUDIOOUT_CTRL_LR_SWAP
+#define BF_AUDIOOUT_CTRL_LR_SWAP_V(e)               BF_AUDIOOUT_CTRL_LR_SWAP(BV_AUDIOOUT_CTRL_LR_SWAP__##e)
+#define BFM_AUDIOOUT_CTRL_LR_SWAP_V(v)              BM_AUDIOOUT_CTRL_LR_SWAP
+#define BP_AUDIOOUT_CTRL_EDGE_SYNC                  13
+#define BM_AUDIOOUT_CTRL_EDGE_SYNC                  0x2000
+#define BF_AUDIOOUT_CTRL_EDGE_SYNC(v)               (((v) & 0x1) << 13)
+#define BFM_AUDIOOUT_CTRL_EDGE_SYNC(v)              BM_AUDIOOUT_CTRL_EDGE_SYNC
+#define BF_AUDIOOUT_CTRL_EDGE_SYNC_V(e)             BF_AUDIOOUT_CTRL_EDGE_SYNC(BV_AUDIOOUT_CTRL_EDGE_SYNC__##e)
+#define BFM_AUDIOOUT_CTRL_EDGE_SYNC_V(v)            BM_AUDIOOUT_CTRL_EDGE_SYNC
+#define BP_AUDIOOUT_CTRL_INVERT_1BIT                12
+#define BM_AUDIOOUT_CTRL_INVERT_1BIT                0x1000
+#define BF_AUDIOOUT_CTRL_INVERT_1BIT(v)             (((v) & 0x1) << 12)
+#define BFM_AUDIOOUT_CTRL_INVERT_1BIT(v)            BM_AUDIOOUT_CTRL_INVERT_1BIT
+#define BF_AUDIOOUT_CTRL_INVERT_1BIT_V(e)           BF_AUDIOOUT_CTRL_INVERT_1BIT(BV_AUDIOOUT_CTRL_INVERT_1BIT__##e)
+#define BFM_AUDIOOUT_CTRL_INVERT_1BIT_V(v)          BM_AUDIOOUT_CTRL_INVERT_1BIT
+#define BP_AUDIOOUT_CTRL_SS3D_EFFECT                8
+#define BM_AUDIOOUT_CTRL_SS3D_EFFECT                0x300
+#define BF_AUDIOOUT_CTRL_SS3D_EFFECT(v)             (((v) & 0x3) << 8)
+#define BFM_AUDIOOUT_CTRL_SS3D_EFFECT(v)            BM_AUDIOOUT_CTRL_SS3D_EFFECT
+#define BF_AUDIOOUT_CTRL_SS3D_EFFECT_V(e)           BF_AUDIOOUT_CTRL_SS3D_EFFECT(BV_AUDIOOUT_CTRL_SS3D_EFFECT__##e)
+#define BFM_AUDIOOUT_CTRL_SS3D_EFFECT_V(v)          BM_AUDIOOUT_CTRL_SS3D_EFFECT
+#define BP_AUDIOOUT_CTRL_WORD_LENGTH                6
+#define BM_AUDIOOUT_CTRL_WORD_LENGTH                0x40
+#define BF_AUDIOOUT_CTRL_WORD_LENGTH(v)             (((v) & 0x1) << 6)
+#define BFM_AUDIOOUT_CTRL_WORD_LENGTH(v)            BM_AUDIOOUT_CTRL_WORD_LENGTH
+#define BF_AUDIOOUT_CTRL_WORD_LENGTH_V(e)           BF_AUDIOOUT_CTRL_WORD_LENGTH(BV_AUDIOOUT_CTRL_WORD_LENGTH__##e)
+#define BFM_AUDIOOUT_CTRL_WORD_LENGTH_V(v)          BM_AUDIOOUT_CTRL_WORD_LENGTH
+#define BP_AUDIOOUT_CTRL_DAC_ZERO_ENABLE            5
+#define BM_AUDIOOUT_CTRL_DAC_ZERO_ENABLE            0x20
+#define BF_AUDIOOUT_CTRL_DAC_ZERO_ENABLE(v)         (((v) & 0x1) << 5)
+#define BFM_AUDIOOUT_CTRL_DAC_ZERO_ENABLE(v)        BM_AUDIOOUT_CTRL_DAC_ZERO_ENABLE
+#define BF_AUDIOOUT_CTRL_DAC_ZERO_ENABLE_V(e)       BF_AUDIOOUT_CTRL_DAC_ZERO_ENABLE(BV_AUDIOOUT_CTRL_DAC_ZERO_ENABLE__##e)
+#define BFM_AUDIOOUT_CTRL_DAC_ZERO_ENABLE_V(v)      BM_AUDIOOUT_CTRL_DAC_ZERO_ENABLE
+#define BP_AUDIOOUT_CTRL_LOOPBACK                   4
+#define BM_AUDIOOUT_CTRL_LOOPBACK                   0x10
+#define BF_AUDIOOUT_CTRL_LOOPBACK(v)                (((v) & 0x1) << 4)
+#define BFM_AUDIOOUT_CTRL_LOOPBACK(v)               BM_AUDIOOUT_CTRL_LOOPBACK
+#define BF_AUDIOOUT_CTRL_LOOPBACK_V(e)              BF_AUDIOOUT_CTRL_LOOPBACK(BV_AUDIOOUT_CTRL_LOOPBACK__##e)
+#define BFM_AUDIOOUT_CTRL_LOOPBACK_V(v)             BM_AUDIOOUT_CTRL_LOOPBACK
+#define BP_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ         3
+#define BM_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ         0x8
+#define BF_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ(v)      (((v) & 0x1) << 3)
+#define BFM_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ(v)     BM_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ
+#define BF_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ_V(e)    BF_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ(BV_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ__##e)
+#define BFM_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ_V(v)   BM_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ
+#define BP_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ          2
+#define BM_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ          0x4
+#define BF_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ(v)       (((v) & 0x1) << 2)
+#define BFM_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ(v)      BM_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ
+#define BF_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ_V(e)     BF_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ(BV_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ__##e)
+#define BFM_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ_V(v)    BM_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ
+#define BP_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN          1
+#define BM_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN          0x2
+#define BF_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN(v)       (((v) & 0x1) << 1)
+#define BFM_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN(v)      BM_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN
+#define BF_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN_V(e)     BF_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN(BV_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN__##e)
+#define BFM_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN_V(v)    BM_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN
+#define BP_AUDIOOUT_CTRL_RUN                        0
+#define BM_AUDIOOUT_CTRL_RUN                        0x1
+#define BF_AUDIOOUT_CTRL_RUN(v)                     (((v) & 0x1) << 0)
+#define BFM_AUDIOOUT_CTRL_RUN(v)                    BM_AUDIOOUT_CTRL_RUN
+#define BF_AUDIOOUT_CTRL_RUN_V(e)                   BF_AUDIOOUT_CTRL_RUN(BV_AUDIOOUT_CTRL_RUN__##e)
+#define BFM_AUDIOOUT_CTRL_RUN_V(v)                  BM_AUDIOOUT_CTRL_RUN
+
+#define HW_AUDIOOUT_STAT                    HW(AUDIOOUT_STAT)
+#define HWA_AUDIOOUT_STAT                   (0x80048000 + 0x10)
+#define HWT_AUDIOOUT_STAT                   HWIO_32_RW
+#define HWN_AUDIOOUT_STAT                   AUDIOOUT_STAT
+#define HWI_AUDIOOUT_STAT                   
+#define BP_AUDIOOUT_STAT_DAC_PRESENT        31
+#define BM_AUDIOOUT_STAT_DAC_PRESENT        0x80000000
+#define BF_AUDIOOUT_STAT_DAC_PRESENT(v)     (((v) & 0x1) << 31)
+#define BFM_AUDIOOUT_STAT_DAC_PRESENT(v)    BM_AUDIOOUT_STAT_DAC_PRESENT
+#define BF_AUDIOOUT_STAT_DAC_PRESENT_V(e)   BF_AUDIOOUT_STAT_DAC_PRESENT(BV_AUDIOOUT_STAT_DAC_PRESENT__##e)
+#define BFM_AUDIOOUT_STAT_DAC_PRESENT_V(v)  BM_AUDIOOUT_STAT_DAC_PRESENT
+
+#define HW_AUDIOOUT_DACSRR                          HW(AUDIOOUT_DACSRR)
+#define HWA_AUDIOOUT_DACSRR                         (0x80048000 + 0x20)
+#define HWT_AUDIOOUT_DACSRR                         HWIO_32_RW
+#define HWN_AUDIOOUT_DACSRR                         AUDIOOUT_DACSRR
+#define HWI_AUDIOOUT_DACSRR                         
+#define HW_AUDIOOUT_DACSRR_SET                      HW(AUDIOOUT_DACSRR_SET)
+#define HWA_AUDIOOUT_DACSRR_SET                     (HWA_AUDIOOUT_DACSRR + 0x4)
+#define HWT_AUDIOOUT_DACSRR_SET                     HWIO_32_WO
+#define HWN_AUDIOOUT_DACSRR_SET                     AUDIOOUT_DACSRR
+#define HWI_AUDIOOUT_DACSRR_SET                     
+#define HW_AUDIOOUT_DACSRR_CLR                      HW(AUDIOOUT_DACSRR_CLR)
+#define HWA_AUDIOOUT_DACSRR_CLR                     (HWA_AUDIOOUT_DACSRR + 0x8)
+#define HWT_AUDIOOUT_DACSRR_CLR                     HWIO_32_WO
+#define HWN_AUDIOOUT_DACSRR_CLR                     AUDIOOUT_DACSRR
+#define HWI_AUDIOOUT_DACSRR_CLR                     
+#define HW_AUDIOOUT_DACSRR_TOG                      HW(AUDIOOUT_DACSRR_TOG)
+#define HWA_AUDIOOUT_DACSRR_TOG                     (HWA_AUDIOOUT_DACSRR + 0xc)
+#define HWT_AUDIOOUT_DACSRR_TOG                     HWIO_32_WO
+#define HWN_AUDIOOUT_DACSRR_TOG                     AUDIOOUT_DACSRR
+#define HWI_AUDIOOUT_DACSRR_TOG                     
+#define BP_AUDIOOUT_DACSRR_OSR                      31
+#define BM_AUDIOOUT_DACSRR_OSR                      0x80000000
+#define BV_AUDIOOUT_DACSRR_OSR__OSR6                0x0
+#define BV_AUDIOOUT_DACSRR_OSR__OSR12               0x1
+#define BF_AUDIOOUT_DACSRR_OSR(v)                   (((v) & 0x1) << 31)
+#define BFM_AUDIOOUT_DACSRR_OSR(v)                  BM_AUDIOOUT_DACSRR_OSR
+#define BF_AUDIOOUT_DACSRR_OSR_V(e)                 BF_AUDIOOUT_DACSRR_OSR(BV_AUDIOOUT_DACSRR_OSR__##e)
+#define BFM_AUDIOOUT_DACSRR_OSR_V(v)                BM_AUDIOOUT_DACSRR_OSR
+#define BP_AUDIOOUT_DACSRR_BASEMULT                 28
+#define BM_AUDIOOUT_DACSRR_BASEMULT                 0x70000000
+#define BV_AUDIOOUT_DACSRR_BASEMULT__SINGLE_RATE    0x1
+#define BV_AUDIOOUT_DACSRR_BASEMULT__DOUBLE_RATE    0x2
+#define BV_AUDIOOUT_DACSRR_BASEMULT__QUAD_RATE      0x4
+#define BF_AUDIOOUT_DACSRR_BASEMULT(v)              (((v) & 0x7) << 28)
+#define BFM_AUDIOOUT_DACSRR_BASEMULT(v)             BM_AUDIOOUT_DACSRR_BASEMULT
+#define BF_AUDIOOUT_DACSRR_BASEMULT_V(e)            BF_AUDIOOUT_DACSRR_BASEMULT(BV_AUDIOOUT_DACSRR_BASEMULT__##e)
+#define BFM_AUDIOOUT_DACSRR_BASEMULT_V(v)           BM_AUDIOOUT_DACSRR_BASEMULT
+#define BP_AUDIOOUT_DACSRR_SRC_HOLD                 24
+#define BM_AUDIOOUT_DACSRR_SRC_HOLD                 0x7000000
+#define BF_AUDIOOUT_DACSRR_SRC_HOLD(v)              (((v) & 0x7) << 24)
+#define BFM_AUDIOOUT_DACSRR_SRC_HOLD(v)             BM_AUDIOOUT_DACSRR_SRC_HOLD
+#define BF_AUDIOOUT_DACSRR_SRC_HOLD_V(e)            BF_AUDIOOUT_DACSRR_SRC_HOLD(BV_AUDIOOUT_DACSRR_SRC_HOLD__##e)
+#define BFM_AUDIOOUT_DACSRR_SRC_HOLD_V(v)           BM_AUDIOOUT_DACSRR_SRC_HOLD
+#define BP_AUDIOOUT_DACSRR_SRC_INT                  16
+#define BM_AUDIOOUT_DACSRR_SRC_INT                  0x1f0000
+#define BF_AUDIOOUT_DACSRR_SRC_INT(v)               (((v) & 0x1f) << 16)
+#define BFM_AUDIOOUT_DACSRR_SRC_INT(v)              BM_AUDIOOUT_DACSRR_SRC_INT
+#define BF_AUDIOOUT_DACSRR_SRC_INT_V(e)             BF_AUDIOOUT_DACSRR_SRC_INT(BV_AUDIOOUT_DACSRR_SRC_INT__##e)
+#define BFM_AUDIOOUT_DACSRR_SRC_INT_V(v)            BM_AUDIOOUT_DACSRR_SRC_INT
+#define BP_AUDIOOUT_DACSRR_SRC_FRAC                 0
+#define BM_AUDIOOUT_DACSRR_SRC_FRAC                 0x1fff
+#define BF_AUDIOOUT_DACSRR_SRC_FRAC(v)              (((v) & 0x1fff) << 0)
+#define BFM_AUDIOOUT_DACSRR_SRC_FRAC(v)             BM_AUDIOOUT_DACSRR_SRC_FRAC
+#define BF_AUDIOOUT_DACSRR_SRC_FRAC_V(e)            BF_AUDIOOUT_DACSRR_SRC_FRAC(BV_AUDIOOUT_DACSRR_SRC_FRAC__##e)
+#define BFM_AUDIOOUT_DACSRR_SRC_FRAC_V(v)           BM_AUDIOOUT_DACSRR_SRC_FRAC
+
+#define HW_AUDIOOUT_DACVOLUME                           HW(AUDIOOUT_DACVOLUME)
+#define HWA_AUDIOOUT_DACVOLUME                          (0x80048000 + 0x30)
+#define HWT_AUDIOOUT_DACVOLUME                          HWIO_32_RW
+#define HWN_AUDIOOUT_DACVOLUME                          AUDIOOUT_DACVOLUME
+#define HWI_AUDIOOUT_DACVOLUME                          
+#define HW_AUDIOOUT_DACVOLUME_SET                       HW(AUDIOOUT_DACVOLUME_SET)
+#define HWA_AUDIOOUT_DACVOLUME_SET                      (HWA_AUDIOOUT_DACVOLUME + 0x4)
+#define HWT_AUDIOOUT_DACVOLUME_SET                      HWIO_32_WO
+#define HWN_AUDIOOUT_DACVOLUME_SET                      AUDIOOUT_DACVOLUME
+#define HWI_AUDIOOUT_DACVOLUME_SET                      
+#define HW_AUDIOOUT_DACVOLUME_CLR                       HW(AUDIOOUT_DACVOLUME_CLR)
+#define HWA_AUDIOOUT_DACVOLUME_CLR                      (HWA_AUDIOOUT_DACVOLUME + 0x8)
+#define HWT_AUDIOOUT_DACVOLUME_CLR                      HWIO_32_WO
+#define HWN_AUDIOOUT_DACVOLUME_CLR                      AUDIOOUT_DACVOLUME
+#define HWI_AUDIOOUT_DACVOLUME_CLR                      
+#define HW_AUDIOOUT_DACVOLUME_TOG                       HW(AUDIOOUT_DACVOLUME_TOG)
+#define HWA_AUDIOOUT_DACVOLUME_TOG                      (HWA_AUDIOOUT_DACVOLUME + 0xc)
+#define HWT_AUDIOOUT_DACVOLUME_TOG                      HWIO_32_WO
+#define HWN_AUDIOOUT_DACVOLUME_TOG                      AUDIOOUT_DACVOLUME
+#define HWI_AUDIOOUT_DACVOLUME_TOG                      
+#define BP_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT        28
+#define BM_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT        0x10000000
+#define BF_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT(v)     (((v) & 0x1) << 28)
+#define BFM_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT(v)    BM_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT
+#define BF_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT_V(e)   BF_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT(BV_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT__##e)
+#define BFM_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT_V(v)  BM_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT
+#define BP_AUDIOOUT_DACVOLUME_EN_ZCD                    25
+#define BM_AUDIOOUT_DACVOLUME_EN_ZCD                    0x2000000
+#define BF_AUDIOOUT_DACVOLUME_EN_ZCD(v)                 (((v) & 0x1) << 25)
+#define BFM_AUDIOOUT_DACVOLUME_EN_ZCD(v)                BM_AUDIOOUT_DACVOLUME_EN_ZCD
+#define BF_AUDIOOUT_DACVOLUME_EN_ZCD_V(e)               BF_AUDIOOUT_DACVOLUME_EN_ZCD(BV_AUDIOOUT_DACVOLUME_EN_ZCD__##e)
+#define BFM_AUDIOOUT_DACVOLUME_EN_ZCD_V(v)              BM_AUDIOOUT_DACVOLUME_EN_ZCD
+#define BP_AUDIOOUT_DACVOLUME_MUTE_LEFT                 24
+#define BM_AUDIOOUT_DACVOLUME_MUTE_LEFT                 0x1000000
+#define BF_AUDIOOUT_DACVOLUME_MUTE_LEFT(v)              (((v) & 0x1) << 24)
+#define BFM_AUDIOOUT_DACVOLUME_MUTE_LEFT(v)             BM_AUDIOOUT_DACVOLUME_MUTE_LEFT
+#define BF_AUDIOOUT_DACVOLUME_MUTE_LEFT_V(e)            BF_AUDIOOUT_DACVOLUME_MUTE_LEFT(BV_AUDIOOUT_DACVOLUME_MUTE_LEFT__##e)
+#define BFM_AUDIOOUT_DACVOLUME_MUTE_LEFT_V(v)           BM_AUDIOOUT_DACVOLUME_MUTE_LEFT
+#define BP_AUDIOOUT_DACVOLUME_VOLUME_LEFT               16
+#define BM_AUDIOOUT_DACVOLUME_VOLUME_LEFT               0xff0000
+#define BF_AUDIOOUT_DACVOLUME_VOLUME_LEFT(v)            (((v) & 0xff) << 16)
+#define BFM_AUDIOOUT_DACVOLUME_VOLUME_LEFT(v)           BM_AUDIOOUT_DACVOLUME_VOLUME_LEFT
+#define BF_AUDIOOUT_DACVOLUME_VOLUME_LEFT_V(e)          BF_AUDIOOUT_DACVOLUME_VOLUME_LEFT(BV_AUDIOOUT_DACVOLUME_VOLUME_LEFT__##e)
+#define BFM_AUDIOOUT_DACVOLUME_VOLUME_LEFT_V(v)         BM_AUDIOOUT_DACVOLUME_VOLUME_LEFT
+#define BP_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT       12
+#define BM_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT       0x1000
+#define BF_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT(v)    (((v) & 0x1) << 12)
+#define BFM_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT(v)   BM_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT
+#define BF_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT_V(e)  BF_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT(BV_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT__##e)
+#define BFM_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT_V(v) BM_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT
+#define BP_AUDIOOUT_DACVOLUME_MUTE_RIGHT                8
+#define BM_AUDIOOUT_DACVOLUME_MUTE_RIGHT                0x100
+#define BF_AUDIOOUT_DACVOLUME_MUTE_RIGHT(v)             (((v) & 0x1) << 8)
+#define BFM_AUDIOOUT_DACVOLUME_MUTE_RIGHT(v)            BM_AUDIOOUT_DACVOLUME_MUTE_RIGHT
+#define BF_AUDIOOUT_DACVOLUME_MUTE_RIGHT_V(e)           BF_AUDIOOUT_DACVOLUME_MUTE_RIGHT(BV_AUDIOOUT_DACVOLUME_MUTE_RIGHT__##e)
+#define BFM_AUDIOOUT_DACVOLUME_MUTE_RIGHT_V(v)          BM_AUDIOOUT_DACVOLUME_MUTE_RIGHT
+#define BP_AUDIOOUT_DACVOLUME_VOLUME_RIGHT              0
+#define BM_AUDIOOUT_DACVOLUME_VOLUME_RIGHT              0xff
+#define BF_AUDIOOUT_DACVOLUME_VOLUME_RIGHT(v)           (((v) & 0xff) << 0)
+#define BFM_AUDIOOUT_DACVOLUME_VOLUME_RIGHT(v)          BM_AUDIOOUT_DACVOLUME_VOLUME_RIGHT
+#define BF_AUDIOOUT_DACVOLUME_VOLUME_RIGHT_V(e)         BF_AUDIOOUT_DACVOLUME_VOLUME_RIGHT(BV_AUDIOOUT_DACVOLUME_VOLUME_RIGHT__##e)
+#define BFM_AUDIOOUT_DACVOLUME_VOLUME_RIGHT_V(v)        BM_AUDIOOUT_DACVOLUME_VOLUME_RIGHT
+
+#define HW_AUDIOOUT_DACDEBUG                                    HW(AUDIOOUT_DACDEBUG)
+#define HWA_AUDIOOUT_DACDEBUG                                   (0x80048000 + 0x40)
+#define HWT_AUDIOOUT_DACDEBUG                                   HWIO_32_RW
+#define HWN_AUDIOOUT_DACDEBUG                                   AUDIOOUT_DACDEBUG
+#define HWI_AUDIOOUT_DACDEBUG                                   
+#define HW_AUDIOOUT_DACDEBUG_SET                                HW(AUDIOOUT_DACDEBUG_SET)
+#define HWA_AUDIOOUT_DACDEBUG_SET                               (HWA_AUDIOOUT_DACDEBUG + 0x4)
+#define HWT_AUDIOOUT_DACDEBUG_SET                               HWIO_32_WO
+#define HWN_AUDIOOUT_DACDEBUG_SET                               AUDIOOUT_DACDEBUG
+#define HWI_AUDIOOUT_DACDEBUG_SET                               
+#define HW_AUDIOOUT_DACDEBUG_CLR                                HW(AUDIOOUT_DACDEBUG_CLR)
+#define HWA_AUDIOOUT_DACDEBUG_CLR                               (HWA_AUDIOOUT_DACDEBUG + 0x8)
+#define HWT_AUDIOOUT_DACDEBUG_CLR                               HWIO_32_WO
+#define HWN_AUDIOOUT_DACDEBUG_CLR                               AUDIOOUT_DACDEBUG
+#define HWI_AUDIOOUT_DACDEBUG_CLR                               
+#define HW_AUDIOOUT_DACDEBUG_TOG                                HW(AUDIOOUT_DACDEBUG_TOG)
+#define HWA_AUDIOOUT_DACDEBUG_TOG                               (HWA_AUDIOOUT_DACDEBUG + 0xc)
+#define HWT_AUDIOOUT_DACDEBUG_TOG                               HWIO_32_WO
+#define HWN_AUDIOOUT_DACDEBUG_TOG                               AUDIOOUT_DACDEBUG
+#define HWI_AUDIOOUT_DACDEBUG_TOG                               
+#define BP_AUDIOOUT_DACDEBUG_ENABLE_DACDMA                      31
+#define BM_AUDIOOUT_DACDEBUG_ENABLE_DACDMA                      0x80000000
+#define BF_AUDIOOUT_DACDEBUG_ENABLE_DACDMA(v)                   (((v) & 0x1) << 31)
+#define BFM_AUDIOOUT_DACDEBUG_ENABLE_DACDMA(v)                  BM_AUDIOOUT_DACDEBUG_ENABLE_DACDMA
+#define BF_AUDIOOUT_DACDEBUG_ENABLE_DACDMA_V(e)                 BF_AUDIOOUT_DACDEBUG_ENABLE_DACDMA(BV_AUDIOOUT_DACDEBUG_ENABLE_DACDMA__##e)
+#define BFM_AUDIOOUT_DACDEBUG_ENABLE_DACDMA_V(v)                BM_AUDIOOUT_DACDEBUG_ENABLE_DACDMA
+#define BP_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS           5
+#define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS           0x20
+#define BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS(v)        (((v) & 0x1) << 5)
+#define BFM_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS(v)       BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS
+#define BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS_V(e)      BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS(BV_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS__##e)
+#define BFM_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS_V(v)     BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS
+#define BP_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS           4
+#define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS           0x10
+#define BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS(v)        (((v) & 0x1) << 4)
+#define BFM_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS(v)       BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS
+#define BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS_V(e)      BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS(BV_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS__##e)
+#define BFM_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS_V(v)     BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS
+#define BP_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE          3
+#define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE          0x8
+#define BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE(v)       (((v) & 0x1) << 3)
+#define BFM_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE(v)      BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE
+#define BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE_V(e)     BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE(BV_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE__##e)
+#define BFM_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE_V(v)    BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE
+#define BP_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE          2
+#define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE          0x4
+#define BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE(v)       (((v) & 0x1) << 2)
+#define BFM_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE(v)      BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE
+#define BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE_V(e)     BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE(BV_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE__##e)
+#define BFM_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE_V(v)    BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE
+#define BP_AUDIOOUT_DACDEBUG_DMA_PREQ                           1
+#define BM_AUDIOOUT_DACDEBUG_DMA_PREQ                           0x2
+#define BF_AUDIOOUT_DACDEBUG_DMA_PREQ(v)                        (((v) & 0x1) << 1)
+#define BFM_AUDIOOUT_DACDEBUG_DMA_PREQ(v)                       BM_AUDIOOUT_DACDEBUG_DMA_PREQ
+#define BF_AUDIOOUT_DACDEBUG_DMA_PREQ_V(e)                      BF_AUDIOOUT_DACDEBUG_DMA_PREQ(BV_AUDIOOUT_DACDEBUG_DMA_PREQ__##e)
+#define BFM_AUDIOOUT_DACDEBUG_DMA_PREQ_V(v)                     BM_AUDIOOUT_DACDEBUG_DMA_PREQ
+#define BP_AUDIOOUT_DACDEBUG_FIFO_STATUS                        0
+#define BM_AUDIOOUT_DACDEBUG_FIFO_STATUS                        0x1
+#define BF_AUDIOOUT_DACDEBUG_FIFO_STATUS(v)                     (((v) & 0x1) << 0)
+#define BFM_AUDIOOUT_DACDEBUG_FIFO_STATUS(v)                    BM_AUDIOOUT_DACDEBUG_FIFO_STATUS
+#define BF_AUDIOOUT_DACDEBUG_FIFO_STATUS_V(e)                   BF_AUDIOOUT_DACDEBUG_FIFO_STATUS(BV_AUDIOOUT_DACDEBUG_FIFO_STATUS__##e)
+#define BFM_AUDIOOUT_DACDEBUG_FIFO_STATUS_V(v)                  BM_AUDIOOUT_DACDEBUG_FIFO_STATUS
+
+#define HW_AUDIOOUT_HPVOL                   HW(AUDIOOUT_HPVOL)
+#define HWA_AUDIOOUT_HPVOL                  (0x80048000 + 0x50)
+#define HWT_AUDIOOUT_HPVOL                  HWIO_32_RW
+#define HWN_AUDIOOUT_HPVOL                  AUDIOOUT_HPVOL
+#define HWI_AUDIOOUT_HPVOL                  
+#define HW_AUDIOOUT_HPVOL_SET               HW(AUDIOOUT_HPVOL_SET)
+#define HWA_AUDIOOUT_HPVOL_SET              (HWA_AUDIOOUT_HPVOL + 0x4)
+#define HWT_AUDIOOUT_HPVOL_SET              HWIO_32_WO
+#define HWN_AUDIOOUT_HPVOL_SET              AUDIOOUT_HPVOL
+#define HWI_AUDIOOUT_HPVOL_SET              
+#define HW_AUDIOOUT_HPVOL_CLR               HW(AUDIOOUT_HPVOL_CLR)
+#define HWA_AUDIOOUT_HPVOL_CLR              (HWA_AUDIOOUT_HPVOL + 0x8)
+#define HWT_AUDIOOUT_HPVOL_CLR              HWIO_32_WO
+#define HWN_AUDIOOUT_HPVOL_CLR              AUDIOOUT_HPVOL
+#define HWI_AUDIOOUT_HPVOL_CLR              
+#define HW_AUDIOOUT_HPVOL_TOG               HW(AUDIOOUT_HPVOL_TOG)
+#define HWA_AUDIOOUT_HPVOL_TOG              (HWA_AUDIOOUT_HPVOL + 0xc)
+#define HWT_AUDIOOUT_HPVOL_TOG              HWIO_32_WO
+#define HWN_AUDIOOUT_HPVOL_TOG              AUDIOOUT_HPVOL
+#define HWI_AUDIOOUT_HPVOL_TOG              
+#define BP_AUDIOOUT_HPVOL_SELECT            24
+#define BM_AUDIOOUT_HPVOL_SELECT            0x3000000
+#define BF_AUDIOOUT_HPVOL_SELECT(v)         (((v) & 0x3) << 24)
+#define BFM_AUDIOOUT_HPVOL_SELECT(v)        BM_AUDIOOUT_HPVOL_SELECT
+#define BF_AUDIOOUT_HPVOL_SELECT_V(e)       BF_AUDIOOUT_HPVOL_SELECT(BV_AUDIOOUT_HPVOL_SELECT__##e)
+#define BFM_AUDIOOUT_HPVOL_SELECT_V(v)      BM_AUDIOOUT_HPVOL_SELECT
+#define BP_AUDIOOUT_HPVOL_MUTE              16
+#define BM_AUDIOOUT_HPVOL_MUTE              0x10000
+#define BF_AUDIOOUT_HPVOL_MUTE(v)           (((v) & 0x1) << 16)
+#define BFM_AUDIOOUT_HPVOL_MUTE(v)          BM_AUDIOOUT_HPVOL_MUTE
+#define BF_AUDIOOUT_HPVOL_MUTE_V(e)         BF_AUDIOOUT_HPVOL_MUTE(BV_AUDIOOUT_HPVOL_MUTE__##e)
+#define BFM_AUDIOOUT_HPVOL_MUTE_V(v)        BM_AUDIOOUT_HPVOL_MUTE
+#define BP_AUDIOOUT_HPVOL_VOL_LEFT          8
+#define BM_AUDIOOUT_HPVOL_VOL_LEFT          0x1f00
+#define BF_AUDIOOUT_HPVOL_VOL_LEFT(v)       (((v) & 0x1f) << 8)
+#define BFM_AUDIOOUT_HPVOL_VOL_LEFT(v)      BM_AUDIOOUT_HPVOL_VOL_LEFT
+#define BF_AUDIOOUT_HPVOL_VOL_LEFT_V(e)     BF_AUDIOOUT_HPVOL_VOL_LEFT(BV_AUDIOOUT_HPVOL_VOL_LEFT__##e)
+#define BFM_AUDIOOUT_HPVOL_VOL_LEFT_V(v)    BM_AUDIOOUT_HPVOL_VOL_LEFT
+#define BP_AUDIOOUT_HPVOL_VOL_RIGHT         0
+#define BM_AUDIOOUT_HPVOL_VOL_RIGHT         0x1f
+#define BF_AUDIOOUT_HPVOL_VOL_RIGHT(v)      (((v) & 0x1f) << 0)
+#define BFM_AUDIOOUT_HPVOL_VOL_RIGHT(v)     BM_AUDIOOUT_HPVOL_VOL_RIGHT
+#define BF_AUDIOOUT_HPVOL_VOL_RIGHT_V(e)    BF_AUDIOOUT_HPVOL_VOL_RIGHT(BV_AUDIOOUT_HPVOL_VOL_RIGHT__##e)
+#define BFM_AUDIOOUT_HPVOL_VOL_RIGHT_V(v)   BM_AUDIOOUT_HPVOL_VOL_RIGHT
+
+#define HW_AUDIOOUT_SPKRVOL             HW(AUDIOOUT_SPKRVOL)
+#define HWA_AUDIOOUT_SPKRVOL            (0x80048000 + 0x60)
+#define HWT_AUDIOOUT_SPKRVOL            HWIO_32_RW
+#define HWN_AUDIOOUT_SPKRVOL            AUDIOOUT_SPKRVOL
+#define HWI_AUDIOOUT_SPKRVOL            
+#define HW_AUDIOOUT_SPKRVOL_SET         HW(AUDIOOUT_SPKRVOL_SET)
+#define HWA_AUDIOOUT_SPKRVOL_SET        (HWA_AUDIOOUT_SPKRVOL + 0x4)
+#define HWT_AUDIOOUT_SPKRVOL_SET        HWIO_32_WO
+#define HWN_AUDIOOUT_SPKRVOL_SET        AUDIOOUT_SPKRVOL
+#define HWI_AUDIOOUT_SPKRVOL_SET        
+#define HW_AUDIOOUT_SPKRVOL_CLR         HW(AUDIOOUT_SPKRVOL_CLR)
+#define HWA_AUDIOOUT_SPKRVOL_CLR        (HWA_AUDIOOUT_SPKRVOL + 0x8)
+#define HWT_AUDIOOUT_SPKRVOL_CLR        HWIO_32_WO
+#define HWN_AUDIOOUT_SPKRVOL_CLR        AUDIOOUT_SPKRVOL
+#define HWI_AUDIOOUT_SPKRVOL_CLR        
+#define HW_AUDIOOUT_SPKRVOL_TOG         HW(AUDIOOUT_SPKRVOL_TOG)
+#define HWA_AUDIOOUT_SPKRVOL_TOG        (HWA_AUDIOOUT_SPKRVOL + 0xc)
+#define HWT_AUDIOOUT_SPKRVOL_TOG        HWIO_32_WO
+#define HWN_AUDIOOUT_SPKRVOL_TOG        AUDIOOUT_SPKRVOL
+#define HWI_AUDIOOUT_SPKRVOL_TOG        
+#define BP_AUDIOOUT_SPKRVOL_MUTE        16
+#define BM_AUDIOOUT_SPKRVOL_MUTE        0x10000
+#define BF_AUDIOOUT_SPKRVOL_MUTE(v)     (((v) & 0x1) << 16)
+#define BFM_AUDIOOUT_SPKRVOL_MUTE(v)    BM_AUDIOOUT_SPKRVOL_MUTE
+#define BF_AUDIOOUT_SPKRVOL_MUTE_V(e)   BF_AUDIOOUT_SPKRVOL_MUTE(BV_AUDIOOUT_SPKRVOL_MUTE__##e)
+#define BFM_AUDIOOUT_SPKRVOL_MUTE_V(v)  BM_AUDIOOUT_SPKRVOL_MUTE
+#define BP_AUDIOOUT_SPKRVOL_VOL         0
+#define BM_AUDIOOUT_SPKRVOL_VOL         0xf
+#define BF_AUDIOOUT_SPKRVOL_VOL(v)      (((v) & 0xf) << 0)
+#define BFM_AUDIOOUT_SPKRVOL_VOL(v)     BM_AUDIOOUT_SPKRVOL_VOL
+#define BF_AUDIOOUT_SPKRVOL_VOL_V(e)    BF_AUDIOOUT_SPKRVOL_VOL(BV_AUDIOOUT_SPKRVOL_VOL__##e)
+#define BFM_AUDIOOUT_SPKRVOL_VOL_V(v)   BM_AUDIOOUT_SPKRVOL_VOL
+
+#define HW_AUDIOOUT_PWRDN                   HW(AUDIOOUT_PWRDN)
+#define HWA_AUDIOOUT_PWRDN                  (0x80048000 + 0x70)
+#define HWT_AUDIOOUT_PWRDN                  HWIO_32_RW
+#define HWN_AUDIOOUT_PWRDN                  AUDIOOUT_PWRDN
+#define HWI_AUDIOOUT_PWRDN                  
+#define HW_AUDIOOUT_PWRDN_SET               HW(AUDIOOUT_PWRDN_SET)
+#define HWA_AUDIOOUT_PWRDN_SET              (HWA_AUDIOOUT_PWRDN + 0x4)
+#define HWT_AUDIOOUT_PWRDN_SET              HWIO_32_WO
+#define HWN_AUDIOOUT_PWRDN_SET              AUDIOOUT_PWRDN
+#define HWI_AUDIOOUT_PWRDN_SET              
+#define HW_AUDIOOUT_PWRDN_CLR               HW(AUDIOOUT_PWRDN_CLR)
+#define HWA_AUDIOOUT_PWRDN_CLR              (HWA_AUDIOOUT_PWRDN + 0x8)
+#define HWT_AUDIOOUT_PWRDN_CLR              HWIO_32_WO
+#define HWN_AUDIOOUT_PWRDN_CLR              AUDIOOUT_PWRDN
+#define HWI_AUDIOOUT_PWRDN_CLR              
+#define HW_AUDIOOUT_PWRDN_TOG               HW(AUDIOOUT_PWRDN_TOG)
+#define HWA_AUDIOOUT_PWRDN_TOG              (HWA_AUDIOOUT_PWRDN + 0xc)
+#define HWT_AUDIOOUT_PWRDN_TOG              HWIO_32_WO
+#define HWN_AUDIOOUT_PWRDN_TOG              AUDIOOUT_PWRDN
+#define HWI_AUDIOOUT_PWRDN_TOG              
+#define BP_AUDIOOUT_PWRDN_SPEAKER           24
+#define BM_AUDIOOUT_PWRDN_SPEAKER           0x1000000
+#define BF_AUDIOOUT_PWRDN_SPEAKER(v)        (((v) & 0x1) << 24)
+#define BFM_AUDIOOUT_PWRDN_SPEAKER(v)       BM_AUDIOOUT_PWRDN_SPEAKER
+#define BF_AUDIOOUT_PWRDN_SPEAKER_V(e)      BF_AUDIOOUT_PWRDN_SPEAKER(BV_AUDIOOUT_PWRDN_SPEAKER__##e)
+#define BFM_AUDIOOUT_PWRDN_SPEAKER_V(v)     BM_AUDIOOUT_PWRDN_SPEAKER
+#define BP_AUDIOOUT_PWRDN_SELFBIAS          20
+#define BM_AUDIOOUT_PWRDN_SELFBIAS          0x100000
+#define BF_AUDIOOUT_PWRDN_SELFBIAS(v)       (((v) & 0x1) << 20)
+#define BFM_AUDIOOUT_PWRDN_SELFBIAS(v)      BM_AUDIOOUT_PWRDN_SELFBIAS
+#define BF_AUDIOOUT_PWRDN_SELFBIAS_V(e)     BF_AUDIOOUT_PWRDN_SELFBIAS(BV_AUDIOOUT_PWRDN_SELFBIAS__##e)
+#define BFM_AUDIOOUT_PWRDN_SELFBIAS_V(v)    BM_AUDIOOUT_PWRDN_SELFBIAS
+#define BP_AUDIOOUT_PWRDN_RIGHT_ADC         16
+#define BM_AUDIOOUT_PWRDN_RIGHT_ADC         0x10000
+#define BF_AUDIOOUT_PWRDN_RIGHT_ADC(v)      (((v) & 0x1) << 16)
+#define BFM_AUDIOOUT_PWRDN_RIGHT_ADC(v)     BM_AUDIOOUT_PWRDN_RIGHT_ADC
+#define BF_AUDIOOUT_PWRDN_RIGHT_ADC_V(e)    BF_AUDIOOUT_PWRDN_RIGHT_ADC(BV_AUDIOOUT_PWRDN_RIGHT_ADC__##e)
+#define BFM_AUDIOOUT_PWRDN_RIGHT_ADC_V(v)   BM_AUDIOOUT_PWRDN_RIGHT_ADC
+#define BP_AUDIOOUT_PWRDN_DAC               12
+#define BM_AUDIOOUT_PWRDN_DAC               0x1000
+#define BF_AUDIOOUT_PWRDN_DAC(v)            (((v) & 0x1) << 12)
+#define BFM_AUDIOOUT_PWRDN_DAC(v)           BM_AUDIOOUT_PWRDN_DAC
+#define BF_AUDIOOUT_PWRDN_DAC_V(e)          BF_AUDIOOUT_PWRDN_DAC(BV_AUDIOOUT_PWRDN_DAC__##e)
+#define BFM_AUDIOOUT_PWRDN_DAC_V(v)         BM_AUDIOOUT_PWRDN_DAC
+#define BP_AUDIOOUT_PWRDN_ADC               8
+#define BM_AUDIOOUT_PWRDN_ADC               0x100
+#define BF_AUDIOOUT_PWRDN_ADC(v)            (((v) & 0x1) << 8)
+#define BFM_AUDIOOUT_PWRDN_ADC(v)           BM_AUDIOOUT_PWRDN_ADC
+#define BF_AUDIOOUT_PWRDN_ADC_V(e)          BF_AUDIOOUT_PWRDN_ADC(BV_AUDIOOUT_PWRDN_ADC__##e)
+#define BFM_AUDIOOUT_PWRDN_ADC_V(v)         BM_AUDIOOUT_PWRDN_ADC
+#define BP_AUDIOOUT_PWRDN_CAPLESS           4
+#define BM_AUDIOOUT_PWRDN_CAPLESS           0x10
+#define BF_AUDIOOUT_PWRDN_CAPLESS(v)        (((v) & 0x1) << 4)
+#define BFM_AUDIOOUT_PWRDN_CAPLESS(v)       BM_AUDIOOUT_PWRDN_CAPLESS
+#define BF_AUDIOOUT_PWRDN_CAPLESS_V(e)      BF_AUDIOOUT_PWRDN_CAPLESS(BV_AUDIOOUT_PWRDN_CAPLESS__##e)
+#define BFM_AUDIOOUT_PWRDN_CAPLESS_V(v)     BM_AUDIOOUT_PWRDN_CAPLESS
+#define BP_AUDIOOUT_PWRDN_HEADPHONE         0
+#define BM_AUDIOOUT_PWRDN_HEADPHONE         0x1
+#define BF_AUDIOOUT_PWRDN_HEADPHONE(v)      (((v) & 0x1) << 0)
+#define BFM_AUDIOOUT_PWRDN_HEADPHONE(v)     BM_AUDIOOUT_PWRDN_HEADPHONE
+#define BF_AUDIOOUT_PWRDN_HEADPHONE_V(e)    BF_AUDIOOUT_PWRDN_HEADPHONE(BV_AUDIOOUT_PWRDN_HEADPHONE__##e)
+#define BFM_AUDIOOUT_PWRDN_HEADPHONE_V(v)   BM_AUDIOOUT_PWRDN_HEADPHONE
+
+#define HW_AUDIOOUT_REFCTRL                     HW(AUDIOOUT_REFCTRL)
+#define HWA_AUDIOOUT_REFCTRL                    (0x80048000 + 0x80)
+#define HWT_AUDIOOUT_REFCTRL                    HWIO_32_RW
+#define HWN_AUDIOOUT_REFCTRL                    AUDIOOUT_REFCTRL
+#define HWI_AUDIOOUT_REFCTRL                    
+#define HW_AUDIOOUT_REFCTRL_SET                 HW(AUDIOOUT_REFCTRL_SET)
+#define HWA_AUDIOOUT_REFCTRL_SET                (HWA_AUDIOOUT_REFCTRL + 0x4)
+#define HWT_AUDIOOUT_REFCTRL_SET                HWIO_32_WO
+#define HWN_AUDIOOUT_REFCTRL_SET                AUDIOOUT_REFCTRL
+#define HWI_AUDIOOUT_REFCTRL_SET                
+#define HW_AUDIOOUT_REFCTRL_CLR                 HW(AUDIOOUT_REFCTRL_CLR)
+#define HWA_AUDIOOUT_REFCTRL_CLR                (HWA_AUDIOOUT_REFCTRL + 0x8)
+#define HWT_AUDIOOUT_REFCTRL_CLR                HWIO_32_WO
+#define HWN_AUDIOOUT_REFCTRL_CLR                AUDIOOUT_REFCTRL
+#define HWI_AUDIOOUT_REFCTRL_CLR                
+#define HW_AUDIOOUT_REFCTRL_TOG                 HW(AUDIOOUT_REFCTRL_TOG)
+#define HWA_AUDIOOUT_REFCTRL_TOG                (HWA_AUDIOOUT_REFCTRL + 0xc)
+#define HWT_AUDIOOUT_REFCTRL_TOG                HWIO_32_WO
+#define HWN_AUDIOOUT_REFCTRL_TOG                AUDIOOUT_REFCTRL
+#define HWI_AUDIOOUT_REFCTRL_TOG                
+#define BP_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS       24
+#define BM_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS       0x1000000
+#define BF_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS(v)    (((v) & 0x1) << 24)
+#define BFM_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS(v)   BM_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS
+#define BF_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS_V(e)  BF_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS(BV_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS__##e)
+#define BFM_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS_V(v) BM_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS
+#define BP_AUDIOOUT_REFCTRL_VBG_ADJ             20
+#define BM_AUDIOOUT_REFCTRL_VBG_ADJ             0x700000
+#define BF_AUDIOOUT_REFCTRL_VBG_ADJ(v)          (((v) & 0x7) << 20)
+#define BFM_AUDIOOUT_REFCTRL_VBG_ADJ(v)         BM_AUDIOOUT_REFCTRL_VBG_ADJ
+#define BF_AUDIOOUT_REFCTRL_VBG_ADJ_V(e)        BF_AUDIOOUT_REFCTRL_VBG_ADJ(BV_AUDIOOUT_REFCTRL_VBG_ADJ__##e)
+#define BFM_AUDIOOUT_REFCTRL_VBG_ADJ_V(v)       BM_AUDIOOUT_REFCTRL_VBG_ADJ
+#define BP_AUDIOOUT_REFCTRL_LOW_PWR             19
+#define BM_AUDIOOUT_REFCTRL_LOW_PWR             0x80000
+#define BF_AUDIOOUT_REFCTRL_LOW_PWR(v)          (((v) & 0x1) << 19)
+#define BFM_AUDIOOUT_REFCTRL_LOW_PWR(v)         BM_AUDIOOUT_REFCTRL_LOW_PWR
+#define BF_AUDIOOUT_REFCTRL_LOW_PWR_V(e)        BF_AUDIOOUT_REFCTRL_LOW_PWR(BV_AUDIOOUT_REFCTRL_LOW_PWR__##e)
+#define BFM_AUDIOOUT_REFCTRL_LOW_PWR_V(v)       BM_AUDIOOUT_REFCTRL_LOW_PWR
+#define BP_AUDIOOUT_REFCTRL_LW_REF              18
+#define BM_AUDIOOUT_REFCTRL_LW_REF              0x40000
+#define BF_AUDIOOUT_REFCTRL_LW_REF(v)           (((v) & 0x1) << 18)
+#define BFM_AUDIOOUT_REFCTRL_LW_REF(v)          BM_AUDIOOUT_REFCTRL_LW_REF
+#define BF_AUDIOOUT_REFCTRL_LW_REF_V(e)         BF_AUDIOOUT_REFCTRL_LW_REF(BV_AUDIOOUT_REFCTRL_LW_REF__##e)
+#define BFM_AUDIOOUT_REFCTRL_LW_REF_V(v)        BM_AUDIOOUT_REFCTRL_LW_REF
+#define BP_AUDIOOUT_REFCTRL_BIAS_CTRL           16
+#define BM_AUDIOOUT_REFCTRL_BIAS_CTRL           0x30000
+#define BF_AUDIOOUT_REFCTRL_BIAS_CTRL(v)        (((v) & 0x3) << 16)
+#define BFM_AUDIOOUT_REFCTRL_BIAS_CTRL(v)       BM_AUDIOOUT_REFCTRL_BIAS_CTRL
+#define BF_AUDIOOUT_REFCTRL_BIAS_CTRL_V(e)      BF_AUDIOOUT_REFCTRL_BIAS_CTRL(BV_AUDIOOUT_REFCTRL_BIAS_CTRL__##e)
+#define BFM_AUDIOOUT_REFCTRL_BIAS_CTRL_V(v)     BM_AUDIOOUT_REFCTRL_BIAS_CTRL
+#define BP_AUDIOOUT_REFCTRL_ADJ_ADC             13
+#define BM_AUDIOOUT_REFCTRL_ADJ_ADC             0x2000
+#define BF_AUDIOOUT_REFCTRL_ADJ_ADC(v)          (((v) & 0x1) << 13)
+#define BFM_AUDIOOUT_REFCTRL_ADJ_ADC(v)         BM_AUDIOOUT_REFCTRL_ADJ_ADC
+#define BF_AUDIOOUT_REFCTRL_ADJ_ADC_V(e)        BF_AUDIOOUT_REFCTRL_ADJ_ADC(BV_AUDIOOUT_REFCTRL_ADJ_ADC__##e)
+#define BFM_AUDIOOUT_REFCTRL_ADJ_ADC_V(v)       BM_AUDIOOUT_REFCTRL_ADJ_ADC
+#define BP_AUDIOOUT_REFCTRL_ADJ_VAG             12
+#define BM_AUDIOOUT_REFCTRL_ADJ_VAG             0x1000
+#define BF_AUDIOOUT_REFCTRL_ADJ_VAG(v)          (((v) & 0x1) << 12)
+#define BFM_AUDIOOUT_REFCTRL_ADJ_VAG(v)         BM_AUDIOOUT_REFCTRL_ADJ_VAG
+#define BF_AUDIOOUT_REFCTRL_ADJ_VAG_V(e)        BF_AUDIOOUT_REFCTRL_ADJ_VAG(BV_AUDIOOUT_REFCTRL_ADJ_VAG__##e)
+#define BFM_AUDIOOUT_REFCTRL_ADJ_VAG_V(v)       BM_AUDIOOUT_REFCTRL_ADJ_VAG
+#define BP_AUDIOOUT_REFCTRL_ADC_REFVAL          8
+#define BM_AUDIOOUT_REFCTRL_ADC_REFVAL          0xf00
+#define BF_AUDIOOUT_REFCTRL_ADC_REFVAL(v)       (((v) & 0xf) << 8)
+#define BFM_AUDIOOUT_REFCTRL_ADC_REFVAL(v)      BM_AUDIOOUT_REFCTRL_ADC_REFVAL
+#define BF_AUDIOOUT_REFCTRL_ADC_REFVAL_V(e)     BF_AUDIOOUT_REFCTRL_ADC_REFVAL(BV_AUDIOOUT_REFCTRL_ADC_REFVAL__##e)
+#define BFM_AUDIOOUT_REFCTRL_ADC_REFVAL_V(v)    BM_AUDIOOUT_REFCTRL_ADC_REFVAL
+#define BP_AUDIOOUT_REFCTRL_VAG_VAL             4
+#define BM_AUDIOOUT_REFCTRL_VAG_VAL             0xf0
+#define BF_AUDIOOUT_REFCTRL_VAG_VAL(v)          (((v) & 0xf) << 4)
+#define BFM_AUDIOOUT_REFCTRL_VAG_VAL(v)         BM_AUDIOOUT_REFCTRL_VAG_VAL
+#define BF_AUDIOOUT_REFCTRL_VAG_VAL_V(e)        BF_AUDIOOUT_REFCTRL_VAG_VAL(BV_AUDIOOUT_REFCTRL_VAG_VAL__##e)
+#define BFM_AUDIOOUT_REFCTRL_VAG_VAL_V(v)       BM_AUDIOOUT_REFCTRL_VAG_VAL
+#define BP_AUDIOOUT_REFCTRL_DAC_ADJ             0
+#define BM_AUDIOOUT_REFCTRL_DAC_ADJ             0x7
+#define BF_AUDIOOUT_REFCTRL_DAC_ADJ(v)          (((v) & 0x7) << 0)
+#define BFM_AUDIOOUT_REFCTRL_DAC_ADJ(v)         BM_AUDIOOUT_REFCTRL_DAC_ADJ
+#define BF_AUDIOOUT_REFCTRL_DAC_ADJ_V(e)        BF_AUDIOOUT_REFCTRL_DAC_ADJ(BV_AUDIOOUT_REFCTRL_DAC_ADJ__##e)
+#define BFM_AUDIOOUT_REFCTRL_DAC_ADJ_V(v)       BM_AUDIOOUT_REFCTRL_DAC_ADJ
+
+#define HW_AUDIOOUT_ANACTRL                     HW(AUDIOOUT_ANACTRL)
+#define HWA_AUDIOOUT_ANACTRL                    (0x80048000 + 0x90)
+#define HWT_AUDIOOUT_ANACTRL                    HWIO_32_RW
+#define HWN_AUDIOOUT_ANACTRL                    AUDIOOUT_ANACTRL
+#define HWI_AUDIOOUT_ANACTRL                    
+#define HW_AUDIOOUT_ANACTRL_SET                 HW(AUDIOOUT_ANACTRL_SET)
+#define HWA_AUDIOOUT_ANACTRL_SET                (HWA_AUDIOOUT_ANACTRL + 0x4)
+#define HWT_AUDIOOUT_ANACTRL_SET                HWIO_32_WO
+#define HWN_AUDIOOUT_ANACTRL_SET                AUDIOOUT_ANACTRL
+#define HWI_AUDIOOUT_ANACTRL_SET                
+#define HW_AUDIOOUT_ANACTRL_CLR                 HW(AUDIOOUT_ANACTRL_CLR)
+#define HWA_AUDIOOUT_ANACTRL_CLR                (HWA_AUDIOOUT_ANACTRL + 0x8)
+#define HWT_AUDIOOUT_ANACTRL_CLR                HWIO_32_WO
+#define HWN_AUDIOOUT_ANACTRL_CLR                AUDIOOUT_ANACTRL
+#define HWI_AUDIOOUT_ANACTRL_CLR                
+#define HW_AUDIOOUT_ANACTRL_TOG                 HW(AUDIOOUT_ANACTRL_TOG)
+#define HWA_AUDIOOUT_ANACTRL_TOG                (HWA_AUDIOOUT_ANACTRL + 0xc)
+#define HWT_AUDIOOUT_ANACTRL_TOG                HWIO_32_WO
+#define HWN_AUDIOOUT_ANACTRL_TOG                AUDIOOUT_ANACTRL
+#define HWI_AUDIOOUT_ANACTRL_TOG                
+#define BP_AUDIOOUT_ANACTRL_SHORT_CM_STS        28
+#define BM_AUDIOOUT_ANACTRL_SHORT_CM_STS        0x10000000
+#define BF_AUDIOOUT_ANACTRL_SHORT_CM_STS(v)     (((v) & 0x1) << 28)
+#define BFM_AUDIOOUT_ANACTRL_SHORT_CM_STS(v)    BM_AUDIOOUT_ANACTRL_SHORT_CM_STS
+#define BF_AUDIOOUT_ANACTRL_SHORT_CM_STS_V(e)   BF_AUDIOOUT_ANACTRL_SHORT_CM_STS(BV_AUDIOOUT_ANACTRL_SHORT_CM_STS__##e)
+#define BFM_AUDIOOUT_ANACTRL_SHORT_CM_STS_V(v)  BM_AUDIOOUT_ANACTRL_SHORT_CM_STS
+#define BP_AUDIOOUT_ANACTRL_SHORT_LR_STS        24
+#define BM_AUDIOOUT_ANACTRL_SHORT_LR_STS        0x1000000
+#define BF_AUDIOOUT_ANACTRL_SHORT_LR_STS(v)     (((v) & 0x1) << 24)
+#define BFM_AUDIOOUT_ANACTRL_SHORT_LR_STS(v)    BM_AUDIOOUT_ANACTRL_SHORT_LR_STS
+#define BF_AUDIOOUT_ANACTRL_SHORT_LR_STS_V(e)   BF_AUDIOOUT_ANACTRL_SHORT_LR_STS(BV_AUDIOOUT_ANACTRL_SHORT_LR_STS__##e)
+#define BFM_AUDIOOUT_ANACTRL_SHORT_LR_STS_V(v)  BM_AUDIOOUT_ANACTRL_SHORT_LR_STS
+#define BP_AUDIOOUT_ANACTRL_SHORTMODE_CM        20
+#define BM_AUDIOOUT_ANACTRL_SHORTMODE_CM        0x300000
+#define BF_AUDIOOUT_ANACTRL_SHORTMODE_CM(v)     (((v) & 0x3) << 20)
+#define BFM_AUDIOOUT_ANACTRL_SHORTMODE_CM(v)    BM_AUDIOOUT_ANACTRL_SHORTMODE_CM
+#define BF_AUDIOOUT_ANACTRL_SHORTMODE_CM_V(e)   BF_AUDIOOUT_ANACTRL_SHORTMODE_CM(BV_AUDIOOUT_ANACTRL_SHORTMODE_CM__##e)
+#define BFM_AUDIOOUT_ANACTRL_SHORTMODE_CM_V(v)  BM_AUDIOOUT_ANACTRL_SHORTMODE_CM
+#define BP_AUDIOOUT_ANACTRL_SHORTMODE_LR        17
+#define BM_AUDIOOUT_ANACTRL_SHORTMODE_LR        0x60000
+#define BF_AUDIOOUT_ANACTRL_SHORTMODE_LR(v)     (((v) & 0x3) << 17)
+#define BFM_AUDIOOUT_ANACTRL_SHORTMODE_LR(v)    BM_AUDIOOUT_ANACTRL_SHORTMODE_LR
+#define BF_AUDIOOUT_ANACTRL_SHORTMODE_LR_V(e)   BF_AUDIOOUT_ANACTRL_SHORTMODE_LR(BV_AUDIOOUT_ANACTRL_SHORTMODE_LR__##e)
+#define BFM_AUDIOOUT_ANACTRL_SHORTMODE_LR_V(v)  BM_AUDIOOUT_ANACTRL_SHORTMODE_LR
+#define BP_AUDIOOUT_ANACTRL_SHORT_LVLADJL       12
+#define BM_AUDIOOUT_ANACTRL_SHORT_LVLADJL       0x7000
+#define BF_AUDIOOUT_ANACTRL_SHORT_LVLADJL(v)    (((v) & 0x7) << 12)
+#define BFM_AUDIOOUT_ANACTRL_SHORT_LVLADJL(v)   BM_AUDIOOUT_ANACTRL_SHORT_LVLADJL
+#define BF_AUDIOOUT_ANACTRL_SHORT_LVLADJL_V(e)  BF_AUDIOOUT_ANACTRL_SHORT_LVLADJL(BV_AUDIOOUT_ANACTRL_SHORT_LVLADJL__##e)
+#define BFM_AUDIOOUT_ANACTRL_SHORT_LVLADJL_V(v) BM_AUDIOOUT_ANACTRL_SHORT_LVLADJL
+#define BP_AUDIOOUT_ANACTRL_SHORT_LVLADJR       8
+#define BM_AUDIOOUT_ANACTRL_SHORT_LVLADJR       0x700
+#define BF_AUDIOOUT_ANACTRL_SHORT_LVLADJR(v)    (((v) & 0x7) << 8)
+#define BFM_AUDIOOUT_ANACTRL_SHORT_LVLADJR(v)   BM_AUDIOOUT_ANACTRL_SHORT_LVLADJR
+#define BF_AUDIOOUT_ANACTRL_SHORT_LVLADJR_V(e)  BF_AUDIOOUT_ANACTRL_SHORT_LVLADJR(BV_AUDIOOUT_ANACTRL_SHORT_LVLADJR__##e)
+#define BFM_AUDIOOUT_ANACTRL_SHORT_LVLADJR_V(v) BM_AUDIOOUT_ANACTRL_SHORT_LVLADJR
+#define BP_AUDIOOUT_ANACTRL_HP_HOLD_GND         5
+#define BM_AUDIOOUT_ANACTRL_HP_HOLD_GND         0x20
+#define BF_AUDIOOUT_ANACTRL_HP_HOLD_GND(v)      (((v) & 0x1) << 5)
+#define BFM_AUDIOOUT_ANACTRL_HP_HOLD_GND(v)     BM_AUDIOOUT_ANACTRL_HP_HOLD_GND
+#define BF_AUDIOOUT_ANACTRL_HP_HOLD_GND_V(e)    BF_AUDIOOUT_ANACTRL_HP_HOLD_GND(BV_AUDIOOUT_ANACTRL_HP_HOLD_GND__##e)
+#define BFM_AUDIOOUT_ANACTRL_HP_HOLD_GND_V(v)   BM_AUDIOOUT_ANACTRL_HP_HOLD_GND
+#define BP_AUDIOOUT_ANACTRL_HP_CLASSAB          4
+#define BM_AUDIOOUT_ANACTRL_HP_CLASSAB          0x10
+#define BF_AUDIOOUT_ANACTRL_HP_CLASSAB(v)       (((v) & 0x1) << 4)
+#define BFM_AUDIOOUT_ANACTRL_HP_CLASSAB(v)      BM_AUDIOOUT_ANACTRL_HP_CLASSAB
+#define BF_AUDIOOUT_ANACTRL_HP_CLASSAB_V(e)     BF_AUDIOOUT_ANACTRL_HP_CLASSAB(BV_AUDIOOUT_ANACTRL_HP_CLASSAB__##e)
+#define BFM_AUDIOOUT_ANACTRL_HP_CLASSAB_V(v)    BM_AUDIOOUT_ANACTRL_HP_CLASSAB
+#define BP_AUDIOOUT_ANACTRL_EN_SPKR_ZCD         2
+#define BM_AUDIOOUT_ANACTRL_EN_SPKR_ZCD         0x4
+#define BF_AUDIOOUT_ANACTRL_EN_SPKR_ZCD(v)      (((v) & 0x1) << 2)
+#define BFM_AUDIOOUT_ANACTRL_EN_SPKR_ZCD(v)     BM_AUDIOOUT_ANACTRL_EN_SPKR_ZCD
+#define BF_AUDIOOUT_ANACTRL_EN_SPKR_ZCD_V(e)    BF_AUDIOOUT_ANACTRL_EN_SPKR_ZCD(BV_AUDIOOUT_ANACTRL_EN_SPKR_ZCD__##e)
+#define BFM_AUDIOOUT_ANACTRL_EN_SPKR_ZCD_V(v)   BM_AUDIOOUT_ANACTRL_EN_SPKR_ZCD
+#define BP_AUDIOOUT_ANACTRL_ZCD_SELECTADC       1
+#define BM_AUDIOOUT_ANACTRL_ZCD_SELECTADC       0x2
+#define BF_AUDIOOUT_ANACTRL_ZCD_SELECTADC(v)    (((v) & 0x1) << 1)
+#define BFM_AUDIOOUT_ANACTRL_ZCD_SELECTADC(v)   BM_AUDIOOUT_ANACTRL_ZCD_SELECTADC
+#define BF_AUDIOOUT_ANACTRL_ZCD_SELECTADC_V(e)  BF_AUDIOOUT_ANACTRL_ZCD_SELECTADC(BV_AUDIOOUT_ANACTRL_ZCD_SELECTADC__##e)
+#define BFM_AUDIOOUT_ANACTRL_ZCD_SELECTADC_V(v) BM_AUDIOOUT_ANACTRL_ZCD_SELECTADC
+#define BP_AUDIOOUT_ANACTRL_EN_ZCD              0
+#define BM_AUDIOOUT_ANACTRL_EN_ZCD              0x1
+#define BF_AUDIOOUT_ANACTRL_EN_ZCD(v)           (((v) & 0x1) << 0)
+#define BFM_AUDIOOUT_ANACTRL_EN_ZCD(v)          BM_AUDIOOUT_ANACTRL_EN_ZCD
+#define BF_AUDIOOUT_ANACTRL_EN_ZCD_V(e)         BF_AUDIOOUT_ANACTRL_EN_ZCD(BV_AUDIOOUT_ANACTRL_EN_ZCD__##e)
+#define BFM_AUDIOOUT_ANACTRL_EN_ZCD_V(v)        BM_AUDIOOUT_ANACTRL_EN_ZCD
+
+#define HW_AUDIOOUT_TEST                        HW(AUDIOOUT_TEST)
+#define HWA_AUDIOOUT_TEST                       (0x80048000 + 0xa0)
+#define HWT_AUDIOOUT_TEST                       HWIO_32_RW
+#define HWN_AUDIOOUT_TEST                       AUDIOOUT_TEST
+#define HWI_AUDIOOUT_TEST                       
+#define HW_AUDIOOUT_TEST_SET                    HW(AUDIOOUT_TEST_SET)
+#define HWA_AUDIOOUT_TEST_SET                   (HWA_AUDIOOUT_TEST + 0x4)
+#define HWT_AUDIOOUT_TEST_SET                   HWIO_32_WO
+#define HWN_AUDIOOUT_TEST_SET                   AUDIOOUT_TEST
+#define HWI_AUDIOOUT_TEST_SET                   
+#define HW_AUDIOOUT_TEST_CLR                    HW(AUDIOOUT_TEST_CLR)
+#define HWA_AUDIOOUT_TEST_CLR                   (HWA_AUDIOOUT_TEST + 0x8)
+#define HWT_AUDIOOUT_TEST_CLR                   HWIO_32_WO
+#define HWN_AUDIOOUT_TEST_CLR                   AUDIOOUT_TEST
+#define HWI_AUDIOOUT_TEST_CLR                   
+#define HW_AUDIOOUT_TEST_TOG                    HW(AUDIOOUT_TEST_TOG)
+#define HWA_AUDIOOUT_TEST_TOG                   (HWA_AUDIOOUT_TEST + 0xc)
+#define HWT_AUDIOOUT_TEST_TOG                   HWIO_32_WO
+#define HWN_AUDIOOUT_TEST_TOG                   AUDIOOUT_TEST
+#define HWI_AUDIOOUT_TEST_TOG                   
+#define BP_AUDIOOUT_TEST_HP_ANTIPOP             28
+#define BM_AUDIOOUT_TEST_HP_ANTIPOP             0x70000000
+#define BF_AUDIOOUT_TEST_HP_ANTIPOP(v)          (((v) & 0x7) << 28)
+#define BFM_AUDIOOUT_TEST_HP_ANTIPOP(v)         BM_AUDIOOUT_TEST_HP_ANTIPOP
+#define BF_AUDIOOUT_TEST_HP_ANTIPOP_V(e)        BF_AUDIOOUT_TEST_HP_ANTIPOP(BV_AUDIOOUT_TEST_HP_ANTIPOP__##e)
+#define BFM_AUDIOOUT_TEST_HP_ANTIPOP_V(v)       BM_AUDIOOUT_TEST_HP_ANTIPOP
+#define BP_AUDIOOUT_TEST_TM_ADCIN_TOHP          26
+#define BM_AUDIOOUT_TEST_TM_ADCIN_TOHP          0x4000000
+#define BF_AUDIOOUT_TEST_TM_ADCIN_TOHP(v)       (((v) & 0x1) << 26)
+#define BFM_AUDIOOUT_TEST_TM_ADCIN_TOHP(v)      BM_AUDIOOUT_TEST_TM_ADCIN_TOHP
+#define BF_AUDIOOUT_TEST_TM_ADCIN_TOHP_V(e)     BF_AUDIOOUT_TEST_TM_ADCIN_TOHP(BV_AUDIOOUT_TEST_TM_ADCIN_TOHP__##e)
+#define BFM_AUDIOOUT_TEST_TM_ADCIN_TOHP_V(v)    BM_AUDIOOUT_TEST_TM_ADCIN_TOHP
+#define BP_AUDIOOUT_TEST_TM_SPEAKER             25
+#define BM_AUDIOOUT_TEST_TM_SPEAKER             0x2000000
+#define BF_AUDIOOUT_TEST_TM_SPEAKER(v)          (((v) & 0x1) << 25)
+#define BFM_AUDIOOUT_TEST_TM_SPEAKER(v)         BM_AUDIOOUT_TEST_TM_SPEAKER
+#define BF_AUDIOOUT_TEST_TM_SPEAKER_V(e)        BF_AUDIOOUT_TEST_TM_SPEAKER(BV_AUDIOOUT_TEST_TM_SPEAKER__##e)
+#define BFM_AUDIOOUT_TEST_TM_SPEAKER_V(v)       BM_AUDIOOUT_TEST_TM_SPEAKER
+#define BP_AUDIOOUT_TEST_TM_HPCOMMON            24
+#define BM_AUDIOOUT_TEST_TM_HPCOMMON            0x1000000
+#define BF_AUDIOOUT_TEST_TM_HPCOMMON(v)         (((v) & 0x1) << 24)
+#define BFM_AUDIOOUT_TEST_TM_HPCOMMON(v)        BM_AUDIOOUT_TEST_TM_HPCOMMON
+#define BF_AUDIOOUT_TEST_TM_HPCOMMON_V(e)       BF_AUDIOOUT_TEST_TM_HPCOMMON(BV_AUDIOOUT_TEST_TM_HPCOMMON__##e)
+#define BFM_AUDIOOUT_TEST_TM_HPCOMMON_V(v)      BM_AUDIOOUT_TEST_TM_HPCOMMON
+#define BP_AUDIOOUT_TEST_HP_I1_ADJ              22
+#define BM_AUDIOOUT_TEST_HP_I1_ADJ              0xc00000
+#define BF_AUDIOOUT_TEST_HP_I1_ADJ(v)           (((v) & 0x3) << 22)
+#define BFM_AUDIOOUT_TEST_HP_I1_ADJ(v)          BM_AUDIOOUT_TEST_HP_I1_ADJ
+#define BF_AUDIOOUT_TEST_HP_I1_ADJ_V(e)         BF_AUDIOOUT_TEST_HP_I1_ADJ(BV_AUDIOOUT_TEST_HP_I1_ADJ__##e)
+#define BFM_AUDIOOUT_TEST_HP_I1_ADJ_V(v)        BM_AUDIOOUT_TEST_HP_I1_ADJ
+#define BP_AUDIOOUT_TEST_HP_IALL_ADJ            20
+#define BM_AUDIOOUT_TEST_HP_IALL_ADJ            0x300000
+#define BF_AUDIOOUT_TEST_HP_IALL_ADJ(v)         (((v) & 0x3) << 20)
+#define BFM_AUDIOOUT_TEST_HP_IALL_ADJ(v)        BM_AUDIOOUT_TEST_HP_IALL_ADJ
+#define BF_AUDIOOUT_TEST_HP_IALL_ADJ_V(e)       BF_AUDIOOUT_TEST_HP_IALL_ADJ(BV_AUDIOOUT_TEST_HP_IALL_ADJ__##e)
+#define BFM_AUDIOOUT_TEST_HP_IALL_ADJ_V(v)      BM_AUDIOOUT_TEST_HP_IALL_ADJ
+#define BP_AUDIOOUT_TEST_SPKR_I1_ADJ            18
+#define BM_AUDIOOUT_TEST_SPKR_I1_ADJ            0xc0000
+#define BF_AUDIOOUT_TEST_SPKR_I1_ADJ(v)         (((v) & 0x3) << 18)
+#define BFM_AUDIOOUT_TEST_SPKR_I1_ADJ(v)        BM_AUDIOOUT_TEST_SPKR_I1_ADJ
+#define BF_AUDIOOUT_TEST_SPKR_I1_ADJ_V(e)       BF_AUDIOOUT_TEST_SPKR_I1_ADJ(BV_AUDIOOUT_TEST_SPKR_I1_ADJ__##e)
+#define BFM_AUDIOOUT_TEST_SPKR_I1_ADJ_V(v)      BM_AUDIOOUT_TEST_SPKR_I1_ADJ
+#define BP_AUDIOOUT_TEST_SPKR_IALL_ADJ          16
+#define BM_AUDIOOUT_TEST_SPKR_IALL_ADJ          0x30000
+#define BF_AUDIOOUT_TEST_SPKR_IALL_ADJ(v)       (((v) & 0x3) << 16)
+#define BFM_AUDIOOUT_TEST_SPKR_IALL_ADJ(v)      BM_AUDIOOUT_TEST_SPKR_IALL_ADJ
+#define BF_AUDIOOUT_TEST_SPKR_IALL_ADJ_V(e)     BF_AUDIOOUT_TEST_SPKR_IALL_ADJ(BV_AUDIOOUT_TEST_SPKR_IALL_ADJ__##e)
+#define BFM_AUDIOOUT_TEST_SPKR_IALL_ADJ_V(v)    BM_AUDIOOUT_TEST_SPKR_IALL_ADJ
+#define BP_AUDIOOUT_TEST_VAG_CLASSA             13
+#define BM_AUDIOOUT_TEST_VAG_CLASSA             0x2000
+#define BF_AUDIOOUT_TEST_VAG_CLASSA(v)          (((v) & 0x1) << 13)
+#define BFM_AUDIOOUT_TEST_VAG_CLASSA(v)         BM_AUDIOOUT_TEST_VAG_CLASSA
+#define BF_AUDIOOUT_TEST_VAG_CLASSA_V(e)        BF_AUDIOOUT_TEST_VAG_CLASSA(BV_AUDIOOUT_TEST_VAG_CLASSA__##e)
+#define BFM_AUDIOOUT_TEST_VAG_CLASSA_V(v)       BM_AUDIOOUT_TEST_VAG_CLASSA
+#define BP_AUDIOOUT_TEST_VAG_DOUBLE_I           12
+#define BM_AUDIOOUT_TEST_VAG_DOUBLE_I           0x1000
+#define BF_AUDIOOUT_TEST_VAG_DOUBLE_I(v)        (((v) & 0x1) << 12)
+#define BFM_AUDIOOUT_TEST_VAG_DOUBLE_I(v)       BM_AUDIOOUT_TEST_VAG_DOUBLE_I
+#define BF_AUDIOOUT_TEST_VAG_DOUBLE_I_V(e)      BF_AUDIOOUT_TEST_VAG_DOUBLE_I(BV_AUDIOOUT_TEST_VAG_DOUBLE_I__##e)
+#define BFM_AUDIOOUT_TEST_VAG_DOUBLE_I_V(v)     BM_AUDIOOUT_TEST_VAG_DOUBLE_I
+#define BP_AUDIOOUT_TEST_HP_CHOPCLK             8
+#define BM_AUDIOOUT_TEST_HP_CHOPCLK             0x300
+#define BF_AUDIOOUT_TEST_HP_CHOPCLK(v)          (((v) & 0x3) << 8)
+#define BFM_AUDIOOUT_TEST_HP_CHOPCLK(v)         BM_AUDIOOUT_TEST_HP_CHOPCLK
+#define BF_AUDIOOUT_TEST_HP_CHOPCLK_V(e)        BF_AUDIOOUT_TEST_HP_CHOPCLK(BV_AUDIOOUT_TEST_HP_CHOPCLK__##e)
+#define BFM_AUDIOOUT_TEST_HP_CHOPCLK_V(v)       BM_AUDIOOUT_TEST_HP_CHOPCLK
+#define BP_AUDIOOUT_TEST_DAC_CHOPCLK            4
+#define BM_AUDIOOUT_TEST_DAC_CHOPCLK            0x30
+#define BF_AUDIOOUT_TEST_DAC_CHOPCLK(v)         (((v) & 0x3) << 4)
+#define BFM_AUDIOOUT_TEST_DAC_CHOPCLK(v)        BM_AUDIOOUT_TEST_DAC_CHOPCLK
+#define BF_AUDIOOUT_TEST_DAC_CHOPCLK_V(e)       BF_AUDIOOUT_TEST_DAC_CHOPCLK(BV_AUDIOOUT_TEST_DAC_CHOPCLK__##e)
+#define BFM_AUDIOOUT_TEST_DAC_CHOPCLK_V(v)      BM_AUDIOOUT_TEST_DAC_CHOPCLK
+#define BP_AUDIOOUT_TEST_DAC_CLASSA             2
+#define BM_AUDIOOUT_TEST_DAC_CLASSA             0x4
+#define BF_AUDIOOUT_TEST_DAC_CLASSA(v)          (((v) & 0x1) << 2)
+#define BFM_AUDIOOUT_TEST_DAC_CLASSA(v)         BM_AUDIOOUT_TEST_DAC_CLASSA
+#define BF_AUDIOOUT_TEST_DAC_CLASSA_V(e)        BF_AUDIOOUT_TEST_DAC_CLASSA(BV_AUDIOOUT_TEST_DAC_CLASSA__##e)
+#define BFM_AUDIOOUT_TEST_DAC_CLASSA_V(v)       BM_AUDIOOUT_TEST_DAC_CLASSA
+#define BP_AUDIOOUT_TEST_DAC_DOUBLE_I           1
+#define BM_AUDIOOUT_TEST_DAC_DOUBLE_I           0x2
+#define BF_AUDIOOUT_TEST_DAC_DOUBLE_I(v)        (((v) & 0x1) << 1)
+#define BFM_AUDIOOUT_TEST_DAC_DOUBLE_I(v)       BM_AUDIOOUT_TEST_DAC_DOUBLE_I
+#define BF_AUDIOOUT_TEST_DAC_DOUBLE_I_V(e)      BF_AUDIOOUT_TEST_DAC_DOUBLE_I(BV_AUDIOOUT_TEST_DAC_DOUBLE_I__##e)
+#define BFM_AUDIOOUT_TEST_DAC_DOUBLE_I_V(v)     BM_AUDIOOUT_TEST_DAC_DOUBLE_I
+#define BP_AUDIOOUT_TEST_DAC_DIS_RTZ            0
+#define BM_AUDIOOUT_TEST_DAC_DIS_RTZ            0x1
+#define BF_AUDIOOUT_TEST_DAC_DIS_RTZ(v)         (((v) & 0x1) << 0)
+#define BFM_AUDIOOUT_TEST_DAC_DIS_RTZ(v)        BM_AUDIOOUT_TEST_DAC_DIS_RTZ
+#define BF_AUDIOOUT_TEST_DAC_DIS_RTZ_V(e)       BF_AUDIOOUT_TEST_DAC_DIS_RTZ(BV_AUDIOOUT_TEST_DAC_DIS_RTZ__##e)
+#define BFM_AUDIOOUT_TEST_DAC_DIS_RTZ_V(v)      BM_AUDIOOUT_TEST_DAC_DIS_RTZ
+
+#define HW_AUDIOOUT_BISTCTRL                HW(AUDIOOUT_BISTCTRL)
+#define HWA_AUDIOOUT_BISTCTRL               (0x80048000 + 0xb0)
+#define HWT_AUDIOOUT_BISTCTRL               HWIO_32_RW
+#define HWN_AUDIOOUT_BISTCTRL               AUDIOOUT_BISTCTRL
+#define HWI_AUDIOOUT_BISTCTRL               
+#define HW_AUDIOOUT_BISTCTRL_SET            HW(AUDIOOUT_BISTCTRL_SET)
+#define HWA_AUDIOOUT_BISTCTRL_SET           (HWA_AUDIOOUT_BISTCTRL + 0x4)
+#define HWT_AUDIOOUT_BISTCTRL_SET           HWIO_32_WO
+#define HWN_AUDIOOUT_BISTCTRL_SET           AUDIOOUT_BISTCTRL
+#define HWI_AUDIOOUT_BISTCTRL_SET           
+#define HW_AUDIOOUT_BISTCTRL_CLR            HW(AUDIOOUT_BISTCTRL_CLR)
+#define HWA_AUDIOOUT_BISTCTRL_CLR           (HWA_AUDIOOUT_BISTCTRL + 0x8)
+#define HWT_AUDIOOUT_BISTCTRL_CLR           HWIO_32_WO
+#define HWN_AUDIOOUT_BISTCTRL_CLR           AUDIOOUT_BISTCTRL
+#define HWI_AUDIOOUT_BISTCTRL_CLR           
+#define HW_AUDIOOUT_BISTCTRL_TOG            HW(AUDIOOUT_BISTCTRL_TOG)
+#define HWA_AUDIOOUT_BISTCTRL_TOG           (HWA_AUDIOOUT_BISTCTRL + 0xc)
+#define HWT_AUDIOOUT_BISTCTRL_TOG           HWIO_32_WO
+#define HWN_AUDIOOUT_BISTCTRL_TOG           AUDIOOUT_BISTCTRL
+#define HWI_AUDIOOUT_BISTCTRL_TOG           
+#define BP_AUDIOOUT_BISTCTRL_FAIL           3
+#define BM_AUDIOOUT_BISTCTRL_FAIL           0x8
+#define BF_AUDIOOUT_BISTCTRL_FAIL(v)        (((v) & 0x1) << 3)
+#define BFM_AUDIOOUT_BISTCTRL_FAIL(v)       BM_AUDIOOUT_BISTCTRL_FAIL
+#define BF_AUDIOOUT_BISTCTRL_FAIL_V(e)      BF_AUDIOOUT_BISTCTRL_FAIL(BV_AUDIOOUT_BISTCTRL_FAIL__##e)
+#define BFM_AUDIOOUT_BISTCTRL_FAIL_V(v)     BM_AUDIOOUT_BISTCTRL_FAIL
+#define BP_AUDIOOUT_BISTCTRL_PASS           2
+#define BM_AUDIOOUT_BISTCTRL_PASS           0x4
+#define BF_AUDIOOUT_BISTCTRL_PASS(v)        (((v) & 0x1) << 2)
+#define BFM_AUDIOOUT_BISTCTRL_PASS(v)       BM_AUDIOOUT_BISTCTRL_PASS
+#define BF_AUDIOOUT_BISTCTRL_PASS_V(e)      BF_AUDIOOUT_BISTCTRL_PASS(BV_AUDIOOUT_BISTCTRL_PASS__##e)
+#define BFM_AUDIOOUT_BISTCTRL_PASS_V(v)     BM_AUDIOOUT_BISTCTRL_PASS
+#define BP_AUDIOOUT_BISTCTRL_DONE           1
+#define BM_AUDIOOUT_BISTCTRL_DONE           0x2
+#define BF_AUDIOOUT_BISTCTRL_DONE(v)        (((v) & 0x1) << 1)
+#define BFM_AUDIOOUT_BISTCTRL_DONE(v)       BM_AUDIOOUT_BISTCTRL_DONE
+#define BF_AUDIOOUT_BISTCTRL_DONE_V(e)      BF_AUDIOOUT_BISTCTRL_DONE(BV_AUDIOOUT_BISTCTRL_DONE__##e)
+#define BFM_AUDIOOUT_BISTCTRL_DONE_V(v)     BM_AUDIOOUT_BISTCTRL_DONE
+#define BP_AUDIOOUT_BISTCTRL_START          0
+#define BM_AUDIOOUT_BISTCTRL_START          0x1
+#define BF_AUDIOOUT_BISTCTRL_START(v)       (((v) & 0x1) << 0)
+#define BFM_AUDIOOUT_BISTCTRL_START(v)      BM_AUDIOOUT_BISTCTRL_START
+#define BF_AUDIOOUT_BISTCTRL_START_V(e)     BF_AUDIOOUT_BISTCTRL_START(BV_AUDIOOUT_BISTCTRL_START__##e)
+#define BFM_AUDIOOUT_BISTCTRL_START_V(v)    BM_AUDIOOUT_BISTCTRL_START
+
+#define HW_AUDIOOUT_BISTSTAT0               HW(AUDIOOUT_BISTSTAT0)
+#define HWA_AUDIOOUT_BISTSTAT0              (0x80048000 + 0xc0)
+#define HWT_AUDIOOUT_BISTSTAT0              HWIO_32_RW
+#define HWN_AUDIOOUT_BISTSTAT0              AUDIOOUT_BISTSTAT0
+#define HWI_AUDIOOUT_BISTSTAT0              
+#define BP_AUDIOOUT_BISTSTAT0_DATA          0
+#define BM_AUDIOOUT_BISTSTAT0_DATA          0xffffff
+#define BF_AUDIOOUT_BISTSTAT0_DATA(v)       (((v) & 0xffffff) << 0)
+#define BFM_AUDIOOUT_BISTSTAT0_DATA(v)      BM_AUDIOOUT_BISTSTAT0_DATA
+#define BF_AUDIOOUT_BISTSTAT0_DATA_V(e)     BF_AUDIOOUT_BISTSTAT0_DATA(BV_AUDIOOUT_BISTSTAT0_DATA__##e)
+#define BFM_AUDIOOUT_BISTSTAT0_DATA_V(v)    BM_AUDIOOUT_BISTSTAT0_DATA
+
+#define HW_AUDIOOUT_BISTSTAT1               HW(AUDIOOUT_BISTSTAT1)
+#define HWA_AUDIOOUT_BISTSTAT1              (0x80048000 + 0xd0)
+#define HWT_AUDIOOUT_BISTSTAT1              HWIO_32_RW
+#define HWN_AUDIOOUT_BISTSTAT1              AUDIOOUT_BISTSTAT1
+#define HWI_AUDIOOUT_BISTSTAT1              
+#define BP_AUDIOOUT_BISTSTAT1_STATE         24
+#define BM_AUDIOOUT_BISTSTAT1_STATE         0x1f000000
+#define BF_AUDIOOUT_BISTSTAT1_STATE(v)      (((v) & 0x1f) << 24)
+#define BFM_AUDIOOUT_BISTSTAT1_STATE(v)     BM_AUDIOOUT_BISTSTAT1_STATE
+#define BF_AUDIOOUT_BISTSTAT1_STATE_V(e)    BF_AUDIOOUT_BISTSTAT1_STATE(BV_AUDIOOUT_BISTSTAT1_STATE__##e)
+#define BFM_AUDIOOUT_BISTSTAT1_STATE_V(v)   BM_AUDIOOUT_BISTSTAT1_STATE
+#define BP_AUDIOOUT_BISTSTAT1_ADDR          0
+#define BM_AUDIOOUT_BISTSTAT1_ADDR          0xff
+#define BF_AUDIOOUT_BISTSTAT1_ADDR(v)       (((v) & 0xff) << 0)
+#define BFM_AUDIOOUT_BISTSTAT1_ADDR(v)      BM_AUDIOOUT_BISTSTAT1_ADDR
+#define BF_AUDIOOUT_BISTSTAT1_ADDR_V(e)     BF_AUDIOOUT_BISTSTAT1_ADDR(BV_AUDIOOUT_BISTSTAT1_ADDR__##e)
+#define BFM_AUDIOOUT_BISTSTAT1_ADDR_V(v)    BM_AUDIOOUT_BISTSTAT1_ADDR
+
+#define HW_AUDIOOUT_ANACLKCTRL                      HW(AUDIOOUT_ANACLKCTRL)
+#define HWA_AUDIOOUT_ANACLKCTRL                     (0x80048000 + 0xe0)
+#define HWT_AUDIOOUT_ANACLKCTRL                     HWIO_32_RW
+#define HWN_AUDIOOUT_ANACLKCTRL                     AUDIOOUT_ANACLKCTRL
+#define HWI_AUDIOOUT_ANACLKCTRL                     
+#define HW_AUDIOOUT_ANACLKCTRL_SET                  HW(AUDIOOUT_ANACLKCTRL_SET)
+#define HWA_AUDIOOUT_ANACLKCTRL_SET                 (HWA_AUDIOOUT_ANACLKCTRL + 0x4)
+#define HWT_AUDIOOUT_ANACLKCTRL_SET                 HWIO_32_WO
+#define HWN_AUDIOOUT_ANACLKCTRL_SET                 AUDIOOUT_ANACLKCTRL
+#define HWI_AUDIOOUT_ANACLKCTRL_SET                 
+#define HW_AUDIOOUT_ANACLKCTRL_CLR                  HW(AUDIOOUT_ANACLKCTRL_CLR)
+#define HWA_AUDIOOUT_ANACLKCTRL_CLR                 (HWA_AUDIOOUT_ANACLKCTRL + 0x8)
+#define HWT_AUDIOOUT_ANACLKCTRL_CLR                 HWIO_32_WO
+#define HWN_AUDIOOUT_ANACLKCTRL_CLR                 AUDIOOUT_ANACLKCTRL
+#define HWI_AUDIOOUT_ANACLKCTRL_CLR                 
+#define HW_AUDIOOUT_ANACLKCTRL_TOG                  HW(AUDIOOUT_ANACLKCTRL_TOG)
+#define HWA_AUDIOOUT_ANACLKCTRL_TOG                 (HWA_AUDIOOUT_ANACLKCTRL + 0xc)
+#define HWT_AUDIOOUT_ANACLKCTRL_TOG                 HWIO_32_WO
+#define HWN_AUDIOOUT_ANACLKCTRL_TOG                 AUDIOOUT_ANACLKCTRL
+#define HWI_AUDIOOUT_ANACLKCTRL_TOG                 
+#define BP_AUDIOOUT_ANACLKCTRL_CLKGATE              31
+#define BM_AUDIOOUT_ANACLKCTRL_CLKGATE              0x80000000
+#define BF_AUDIOOUT_ANACLKCTRL_CLKGATE(v)           (((v) & 0x1) << 31)
+#define BFM_AUDIOOUT_ANACLKCTRL_CLKGATE(v)          BM_AUDIOOUT_ANACLKCTRL_CLKGATE
+#define BF_AUDIOOUT_ANACLKCTRL_CLKGATE_V(e)         BF_AUDIOOUT_ANACLKCTRL_CLKGATE(BV_AUDIOOUT_ANACLKCTRL_CLKGATE__##e)
+#define BFM_AUDIOOUT_ANACLKCTRL_CLKGATE_V(v)        BM_AUDIOOUT_ANACLKCTRL_CLKGATE
+#define BP_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK        4
+#define BM_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK        0x10
+#define BF_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK(v)     (((v) & 0x1) << 4)
+#define BFM_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK(v)    BM_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK
+#define BF_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK_V(e)   BF_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK(BV_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK__##e)
+#define BFM_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK_V(v)  BM_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK
+#define BP_AUDIOOUT_ANACLKCTRL_DACDIV               0
+#define BM_AUDIOOUT_ANACLKCTRL_DACDIV               0x7
+#define BF_AUDIOOUT_ANACLKCTRL_DACDIV(v)            (((v) & 0x7) << 0)
+#define BFM_AUDIOOUT_ANACLKCTRL_DACDIV(v)           BM_AUDIOOUT_ANACLKCTRL_DACDIV
+#define BF_AUDIOOUT_ANACLKCTRL_DACDIV_V(e)          BF_AUDIOOUT_ANACLKCTRL_DACDIV(BV_AUDIOOUT_ANACLKCTRL_DACDIV__##e)
+#define BFM_AUDIOOUT_ANACLKCTRL_DACDIV_V(v)         BM_AUDIOOUT_ANACLKCTRL_DACDIV
+
+#define HW_AUDIOOUT_DATA            HW(AUDIOOUT_DATA)
+#define HWA_AUDIOOUT_DATA           (0x80048000 + 0xf0)
+#define HWT_AUDIOOUT_DATA           HWIO_32_RW
+#define HWN_AUDIOOUT_DATA           AUDIOOUT_DATA
+#define HWI_AUDIOOUT_DATA           
+#define HW_AUDIOOUT_DATA_SET        HW(AUDIOOUT_DATA_SET)
+#define HWA_AUDIOOUT_DATA_SET       (HWA_AUDIOOUT_DATA + 0x4)
+#define HWT_AUDIOOUT_DATA_SET       HWIO_32_WO
+#define HWN_AUDIOOUT_DATA_SET       AUDIOOUT_DATA
+#define HWI_AUDIOOUT_DATA_SET       
+#define HW_AUDIOOUT_DATA_CLR        HW(AUDIOOUT_DATA_CLR)
+#define HWA_AUDIOOUT_DATA_CLR       (HWA_AUDIOOUT_DATA + 0x8)
+#define HWT_AUDIOOUT_DATA_CLR       HWIO_32_WO
+#define HWN_AUDIOOUT_DATA_CLR       AUDIOOUT_DATA
+#define HWI_AUDIOOUT_DATA_CLR       
+#define HW_AUDIOOUT_DATA_TOG        HW(AUDIOOUT_DATA_TOG)
+#define HWA_AUDIOOUT_DATA_TOG       (HWA_AUDIOOUT_DATA + 0xc)
+#define HWT_AUDIOOUT_DATA_TOG       HWIO_32_WO
+#define HWN_AUDIOOUT_DATA_TOG       AUDIOOUT_DATA
+#define HWI_AUDIOOUT_DATA_TOG       
+#define BP_AUDIOOUT_DATA_HIGH       16
+#define BM_AUDIOOUT_DATA_HIGH       0xffff0000
+#define BF_AUDIOOUT_DATA_HIGH(v)    (((v) & 0xffff) << 16)
+#define BFM_AUDIOOUT_DATA_HIGH(v)   BM_AUDIOOUT_DATA_HIGH
+#define BF_AUDIOOUT_DATA_HIGH_V(e)  BF_AUDIOOUT_DATA_HIGH(BV_AUDIOOUT_DATA_HIGH__##e)
+#define BFM_AUDIOOUT_DATA_HIGH_V(v) BM_AUDIOOUT_DATA_HIGH
+#define BP_AUDIOOUT_DATA_LOW        0
+#define BM_AUDIOOUT_DATA_LOW        0xffff
+#define BF_AUDIOOUT_DATA_LOW(v)     (((v) & 0xffff) << 0)
+#define BFM_AUDIOOUT_DATA_LOW(v)    BM_AUDIOOUT_DATA_LOW
+#define BF_AUDIOOUT_DATA_LOW_V(e)   BF_AUDIOOUT_DATA_LOW(BV_AUDIOOUT_DATA_LOW__##e)
+#define BFM_AUDIOOUT_DATA_LOW_V(v)  BM_AUDIOOUT_DATA_LOW
+
+#endif /* __HEADERGEN_STMP3600_AUDIOOUT_H__*/
diff --git a/firmware/target/arm/imx233/regs/stmp3600/clkctrl.h b/firmware/target/arm/imx233/regs/stmp3600/clkctrl.h
new file mode 100644
index 0000000000..9f6c8bc904
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3600/clkctrl.h
@@ -0,0 +1,546 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * stmp3600 version: 2.4.0
+ * stmp3600 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_STMP3600_CLKCTRL_H__
+#define __HEADERGEN_STMP3600_CLKCTRL_H__
+
+#define HW_CLKCTRL_PLLCTRL0                                     HW(CLKCTRL_PLLCTRL0)
+#define HWA_CLKCTRL_PLLCTRL0                                    (0x80040000 + 0x0)
+#define HWT_CLKCTRL_PLLCTRL0                                    HWIO_32_RW
+#define HWN_CLKCTRL_PLLCTRL0                                    CLKCTRL_PLLCTRL0
+#define HWI_CLKCTRL_PLLCTRL0                                    
+#define HW_CLKCTRL_PLLCTRL0_SET                                 HW(CLKCTRL_PLLCTRL0_SET)
+#define HWA_CLKCTRL_PLLCTRL0_SET                                (HWA_CLKCTRL_PLLCTRL0 + 0x4)
+#define HWT_CLKCTRL_PLLCTRL0_SET                                HWIO_32_WO
+#define HWN_CLKCTRL_PLLCTRL0_SET                                CLKCTRL_PLLCTRL0
+#define HWI_CLKCTRL_PLLCTRL0_SET                                
+#define HW_CLKCTRL_PLLCTRL0_CLR                                 HW(CLKCTRL_PLLCTRL0_CLR)
+#define HWA_CLKCTRL_PLLCTRL0_CLR                                (HWA_CLKCTRL_PLLCTRL0 + 0x8)
+#define HWT_CLKCTRL_PLLCTRL0_CLR                                HWIO_32_WO
+#define HWN_CLKCTRL_PLLCTRL0_CLR                                CLKCTRL_PLLCTRL0
+#define HWI_CLKCTRL_PLLCTRL0_CLR                                
+#define HW_CLKCTRL_PLLCTRL0_TOG                                 HW(CLKCTRL_PLLCTRL0_TOG)
+#define HWA_CLKCTRL_PLLCTRL0_TOG                                (HWA_CLKCTRL_PLLCTRL0 + 0xc)
+#define HWT_CLKCTRL_PLLCTRL0_TOG                                HWIO_32_WO
+#define HWN_CLKCTRL_PLLCTRL0_TOG                                CLKCTRL_PLLCTRL0
+#define HWI_CLKCTRL_PLLCTRL0_TOG                                
+#define BP_CLKCTRL_PLLCTRL0_PLLVCOKSTART                        30
+#define BM_CLKCTRL_PLLCTRL0_PLLVCOKSTART                        0x40000000
+#define BF_CLKCTRL_PLLCTRL0_PLLVCOKSTART(v)                     (((v) & 0x1) << 30)
+#define BFM_CLKCTRL_PLLCTRL0_PLLVCOKSTART(v)                    BM_CLKCTRL_PLLCTRL0_PLLVCOKSTART
+#define BF_CLKCTRL_PLLCTRL0_PLLVCOKSTART_V(e)                   BF_CLKCTRL_PLLCTRL0_PLLVCOKSTART(BV_CLKCTRL_PLLCTRL0_PLLVCOKSTART__##e)
+#define BFM_CLKCTRL_PLLCTRL0_PLLVCOKSTART_V(v)                  BM_CLKCTRL_PLLCTRL0_PLLVCOKSTART
+#define BP_CLKCTRL_PLLCTRL0_PLLCPSHORTLFR                       29
+#define BM_CLKCTRL_PLLCTRL0_PLLCPSHORTLFR                       0x20000000
+#define BF_CLKCTRL_PLLCTRL0_PLLCPSHORTLFR(v)                    (((v) & 0x1) << 29)
+#define BFM_CLKCTRL_PLLCTRL0_PLLCPSHORTLFR(v)                   BM_CLKCTRL_PLLCTRL0_PLLCPSHORTLFR
+#define BF_CLKCTRL_PLLCTRL0_PLLCPSHORTLFR_V(e)                  BF_CLKCTRL_PLLCTRL0_PLLCPSHORTLFR(BV_CLKCTRL_PLLCTRL0_PLLCPSHORTLFR__##e)
+#define BFM_CLKCTRL_PLLCTRL0_PLLCPSHORTLFR_V(v)                 BM_CLKCTRL_PLLCTRL0_PLLCPSHORTLFR
+#define BP_CLKCTRL_PLLCTRL0_PLLCPDBLIP                          28
+#define BM_CLKCTRL_PLLCTRL0_PLLCPDBLIP                          0x10000000
+#define BF_CLKCTRL_PLLCTRL0_PLLCPDBLIP(v)                       (((v) & 0x1) << 28)
+#define BFM_CLKCTRL_PLLCTRL0_PLLCPDBLIP(v)                      BM_CLKCTRL_PLLCTRL0_PLLCPDBLIP
+#define BF_CLKCTRL_PLLCTRL0_PLLCPDBLIP_V(e)                     BF_CLKCTRL_PLLCTRL0_PLLCPDBLIP(BV_CLKCTRL_PLLCTRL0_PLLCPDBLIP__##e)
+#define BFM_CLKCTRL_PLLCTRL0_PLLCPDBLIP_V(v)                    BM_CLKCTRL_PLLCTRL0_PLLCPDBLIP
+#define BP_CLKCTRL_PLLCTRL0_PLLCPNSEL                           24
+#define BM_CLKCTRL_PLLCTRL0_PLLCPNSEL                           0x7000000
+#define BV_CLKCTRL_PLLCTRL0_PLLCPNSEL__DEFAULT                  0x0
+#define BV_CLKCTRL_PLLCTRL0_PLLCPNSEL__TIMES_15                 0x2
+#define BV_CLKCTRL_PLLCTRL0_PLLCPNSEL__TIMES_075                0x3
+#define BV_CLKCTRL_PLLCTRL0_PLLCPNSEL__TIMES_05                 0x4
+#define BV_CLKCTRL_PLLCTRL0_PLLCPNSEL__TIMES_04                 0x7
+#define BF_CLKCTRL_PLLCTRL0_PLLCPNSEL(v)                        (((v) & 0x7) << 24)
+#define BFM_CLKCTRL_PLLCTRL0_PLLCPNSEL(v)                       BM_CLKCTRL_PLLCTRL0_PLLCPNSEL
+#define BF_CLKCTRL_PLLCTRL0_PLLCPNSEL_V(e)                      BF_CLKCTRL_PLLCTRL0_PLLCPNSEL(BV_CLKCTRL_PLLCTRL0_PLLCPNSEL__##e)
+#define BFM_CLKCTRL_PLLCTRL0_PLLCPNSEL_V(v)                     BM_CLKCTRL_PLLCTRL0_PLLCPNSEL
+#define BP_CLKCTRL_PLLCTRL0_PLLV2ISEL                           20
+#define BM_CLKCTRL_PLLCTRL0_PLLV2ISEL                           0x300000
+#define BV_CLKCTRL_PLLCTRL0_PLLV2ISEL__NORMAL                   0x0
+#define BV_CLKCTRL_PLLCTRL0_PLLV2ISEL__LOWER                    0x1
+#define BV_CLKCTRL_PLLCTRL0_PLLV2ISEL__LOWEST                   0x2
+#define BV_CLKCTRL_PLLCTRL0_PLLV2ISEL__HIGHEST                  0x3
+#define BF_CLKCTRL_PLLCTRL0_PLLV2ISEL(v)                        (((v) & 0x3) << 20)
+#define BFM_CLKCTRL_PLLCTRL0_PLLV2ISEL(v)                       BM_CLKCTRL_PLLCTRL0_PLLV2ISEL
+#define BF_CLKCTRL_PLLCTRL0_PLLV2ISEL_V(e)                      BF_CLKCTRL_PLLCTRL0_PLLV2ISEL(BV_CLKCTRL_PLLCTRL0_PLLV2ISEL__##e)
+#define BFM_CLKCTRL_PLLCTRL0_PLLV2ISEL_V(v)                     BM_CLKCTRL_PLLCTRL0_PLLV2ISEL
+#define BP_CLKCTRL_PLLCTRL0_FORCE_FREQ                          19
+#define BM_CLKCTRL_PLLCTRL0_FORCE_FREQ                          0x80000
+#define BV_CLKCTRL_PLLCTRL0_FORCE_FREQ__FORCE_SAME_FREQ         0x1
+#define BV_CLKCTRL_PLLCTRL0_FORCE_FREQ__HONOR_SAME_FREQ_RULE    0x0
+#define BF_CLKCTRL_PLLCTRL0_FORCE_FREQ(v)                       (((v) & 0x1) << 19)
+#define BFM_CLKCTRL_PLLCTRL0_FORCE_FREQ(v)                      BM_CLKCTRL_PLLCTRL0_FORCE_FREQ
+#define BF_CLKCTRL_PLLCTRL0_FORCE_FREQ_V(e)                     BF_CLKCTRL_PLLCTRL0_FORCE_FREQ(BV_CLKCTRL_PLLCTRL0_FORCE_FREQ__##e)
+#define BFM_CLKCTRL_PLLCTRL0_FORCE_FREQ_V(v)                    BM_CLKCTRL_PLLCTRL0_FORCE_FREQ
+#define BP_CLKCTRL_PLLCTRL0_EN_USB_CLKS                         18
+#define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS                         0x40000
+#define BF_CLKCTRL_PLLCTRL0_EN_USB_CLKS(v)                      (((v) & 0x1) << 18)
+#define BFM_CLKCTRL_PLLCTRL0_EN_USB_CLKS(v)                     BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS
+#define BF_CLKCTRL_PLLCTRL0_EN_USB_CLKS_V(e)                    BF_CLKCTRL_PLLCTRL0_EN_USB_CLKS(BV_CLKCTRL_PLLCTRL0_EN_USB_CLKS__##e)
+#define BFM_CLKCTRL_PLLCTRL0_EN_USB_CLKS_V(v)                   BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS
+#define BP_CLKCTRL_PLLCTRL0_BYPASS                              17
+#define BM_CLKCTRL_PLLCTRL0_BYPASS                              0x20000
+#define BF_CLKCTRL_PLLCTRL0_BYPASS(v)                           (((v) & 0x1) << 17)
+#define BFM_CLKCTRL_PLLCTRL0_BYPASS(v)                          BM_CLKCTRL_PLLCTRL0_BYPASS
+#define BF_CLKCTRL_PLLCTRL0_BYPASS_V(e)                         BF_CLKCTRL_PLLCTRL0_BYPASS(BV_CLKCTRL_PLLCTRL0_BYPASS__##e)
+#define BFM_CLKCTRL_PLLCTRL0_BYPASS_V(v)                        BM_CLKCTRL_PLLCTRL0_BYPASS
+#define BP_CLKCTRL_PLLCTRL0_POWER                               16
+#define BM_CLKCTRL_PLLCTRL0_POWER                               0x10000
+#define BF_CLKCTRL_PLLCTRL0_POWER(v)                            (((v) & 0x1) << 16)
+#define BFM_CLKCTRL_PLLCTRL0_POWER(v)                           BM_CLKCTRL_PLLCTRL0_POWER
+#define BF_CLKCTRL_PLLCTRL0_POWER_V(e)                          BF_CLKCTRL_PLLCTRL0_POWER(BV_CLKCTRL_PLLCTRL0_POWER__##e)
+#define BFM_CLKCTRL_PLLCTRL0_POWER_V(v)                         BM_CLKCTRL_PLLCTRL0_POWER
+#define BP_CLKCTRL_PLLCTRL0_FREQ                                0
+#define BM_CLKCTRL_PLLCTRL0_FREQ                                0x1ff
+#define BF_CLKCTRL_PLLCTRL0_FREQ(v)                             (((v) & 0x1ff) << 0)
+#define BFM_CLKCTRL_PLLCTRL0_FREQ(v)                            BM_CLKCTRL_PLLCTRL0_FREQ
+#define BF_CLKCTRL_PLLCTRL0_FREQ_V(e)                           BF_CLKCTRL_PLLCTRL0_FREQ(BV_CLKCTRL_PLLCTRL0_FREQ__##e)
+#define BFM_CLKCTRL_PLLCTRL0_FREQ_V(v)                          BM_CLKCTRL_PLLCTRL0_FREQ
+
+#define HW_CLKCTRL_PLLCTRL1                     HW(CLKCTRL_PLLCTRL1)
+#define HWA_CLKCTRL_PLLCTRL1                    (0x80040000 + 0x10)
+#define HWT_CLKCTRL_PLLCTRL1                    HWIO_32_RW
+#define HWN_CLKCTRL_PLLCTRL1                    CLKCTRL_PLLCTRL1
+#define HWI_CLKCTRL_PLLCTRL1                    
+#define HW_CLKCTRL_PLLCTRL1_SET                 HW(CLKCTRL_PLLCTRL1_SET)
+#define HWA_CLKCTRL_PLLCTRL1_SET                (HWA_CLKCTRL_PLLCTRL1 + 0x4)
+#define HWT_CLKCTRL_PLLCTRL1_SET                HWIO_32_WO
+#define HWN_CLKCTRL_PLLCTRL1_SET                CLKCTRL_PLLCTRL1
+#define HWI_CLKCTRL_PLLCTRL1_SET                
+#define HW_CLKCTRL_PLLCTRL1_CLR                 HW(CLKCTRL_PLLCTRL1_CLR)
+#define HWA_CLKCTRL_PLLCTRL1_CLR                (HWA_CLKCTRL_PLLCTRL1 + 0x8)
+#define HWT_CLKCTRL_PLLCTRL1_CLR                HWIO_32_WO
+#define HWN_CLKCTRL_PLLCTRL1_CLR                CLKCTRL_PLLCTRL1
+#define HWI_CLKCTRL_PLLCTRL1_CLR                
+#define HW_CLKCTRL_PLLCTRL1_TOG                 HW(CLKCTRL_PLLCTRL1_TOG)
+#define HWA_CLKCTRL_PLLCTRL1_TOG                (HWA_CLKCTRL_PLLCTRL1 + 0xc)
+#define HWT_CLKCTRL_PLLCTRL1_TOG                HWIO_32_WO
+#define HWN_CLKCTRL_PLLCTRL1_TOG                CLKCTRL_PLLCTRL1
+#define HWI_CLKCTRL_PLLCTRL1_TOG                
+#define BP_CLKCTRL_PLLCTRL1_LOCK                31
+#define BM_CLKCTRL_PLLCTRL1_LOCK                0x80000000
+#define BF_CLKCTRL_PLLCTRL1_LOCK(v)             (((v) & 0x1) << 31)
+#define BFM_CLKCTRL_PLLCTRL1_LOCK(v)            BM_CLKCTRL_PLLCTRL1_LOCK
+#define BF_CLKCTRL_PLLCTRL1_LOCK_V(e)           BF_CLKCTRL_PLLCTRL1_LOCK(BV_CLKCTRL_PLLCTRL1_LOCK__##e)
+#define BFM_CLKCTRL_PLLCTRL1_LOCK_V(v)          BM_CLKCTRL_PLLCTRL1_LOCK
+#define BP_CLKCTRL_PLLCTRL1_FORCE_LOCK          30
+#define BM_CLKCTRL_PLLCTRL1_FORCE_LOCK          0x40000000
+#define BF_CLKCTRL_PLLCTRL1_FORCE_LOCK(v)       (((v) & 0x1) << 30)
+#define BFM_CLKCTRL_PLLCTRL1_FORCE_LOCK(v)      BM_CLKCTRL_PLLCTRL1_FORCE_LOCK
+#define BF_CLKCTRL_PLLCTRL1_FORCE_LOCK_V(e)     BF_CLKCTRL_PLLCTRL1_FORCE_LOCK(BV_CLKCTRL_PLLCTRL1_FORCE_LOCK__##e)
+#define BFM_CLKCTRL_PLLCTRL1_FORCE_LOCK_V(v)    BM_CLKCTRL_PLLCTRL1_FORCE_LOCK
+#define BP_CLKCTRL_PLLCTRL1_LOCK_COUNT          0
+#define BM_CLKCTRL_PLLCTRL1_LOCK_COUNT          0xffff
+#define BF_CLKCTRL_PLLCTRL1_LOCK_COUNT(v)       (((v) & 0xffff) << 0)
+#define BFM_CLKCTRL_PLLCTRL1_LOCK_COUNT(v)      BM_CLKCTRL_PLLCTRL1_LOCK_COUNT
+#define BF_CLKCTRL_PLLCTRL1_LOCK_COUNT_V(e)     BF_CLKCTRL_PLLCTRL1_LOCK_COUNT(BV_CLKCTRL_PLLCTRL1_LOCK_COUNT__##e)
+#define BFM_CLKCTRL_PLLCTRL1_LOCK_COUNT_V(v)    BM_CLKCTRL_PLLCTRL1_LOCK_COUNT
+
+#define HW_CLKCTRL_CPU                      HW(CLKCTRL_CPU)
+#define HWA_CLKCTRL_CPU                     (0x80040000 + 0x20)
+#define HWT_CLKCTRL_CPU                     HWIO_32_RW
+#define HWN_CLKCTRL_CPU                     CLKCTRL_CPU
+#define HWI_CLKCTRL_CPU                     
+#define BP_CLKCTRL_CPU_WAIT_PLL_LOCK        30
+#define BM_CLKCTRL_CPU_WAIT_PLL_LOCK        0x40000000
+#define BF_CLKCTRL_CPU_WAIT_PLL_LOCK(v)     (((v) & 0x1) << 30)
+#define BFM_CLKCTRL_CPU_WAIT_PLL_LOCK(v)    BM_CLKCTRL_CPU_WAIT_PLL_LOCK
+#define BF_CLKCTRL_CPU_WAIT_PLL_LOCK_V(e)   BF_CLKCTRL_CPU_WAIT_PLL_LOCK(BV_CLKCTRL_CPU_WAIT_PLL_LOCK__##e)
+#define BFM_CLKCTRL_CPU_WAIT_PLL_LOCK_V(v)  BM_CLKCTRL_CPU_WAIT_PLL_LOCK
+#define BP_CLKCTRL_CPU_BUSY                 29
+#define BM_CLKCTRL_CPU_BUSY                 0x20000000
+#define BF_CLKCTRL_CPU_BUSY(v)              (((v) & 0x1) << 29)
+#define BFM_CLKCTRL_CPU_BUSY(v)             BM_CLKCTRL_CPU_BUSY
+#define BF_CLKCTRL_CPU_BUSY_V(e)            BF_CLKCTRL_CPU_BUSY(BV_CLKCTRL_CPU_BUSY__##e)
+#define BFM_CLKCTRL_CPU_BUSY_V(v)           BM_CLKCTRL_CPU_BUSY
+#define BP_CLKCTRL_CPU_INTERRUPT_WAIT       12
+#define BM_CLKCTRL_CPU_INTERRUPT_WAIT       0x1000
+#define BF_CLKCTRL_CPU_INTERRUPT_WAIT(v)    (((v) & 0x1) << 12)
+#define BFM_CLKCTRL_CPU_INTERRUPT_WAIT(v)   BM_CLKCTRL_CPU_INTERRUPT_WAIT
+#define BF_CLKCTRL_CPU_INTERRUPT_WAIT_V(e)  BF_CLKCTRL_CPU_INTERRUPT_WAIT(BV_CLKCTRL_CPU_INTERRUPT_WAIT__##e)
+#define BFM_CLKCTRL_CPU_INTERRUPT_WAIT_V(v) BM_CLKCTRL_CPU_INTERRUPT_WAIT
+#define BP_CLKCTRL_CPU_DIV                  0
+#define BM_CLKCTRL_CPU_DIV                  0x3ff
+#define BF_CLKCTRL_CPU_DIV(v)               (((v) & 0x3ff) << 0)
+#define BFM_CLKCTRL_CPU_DIV(v)              BM_CLKCTRL_CPU_DIV
+#define BF_CLKCTRL_CPU_DIV_V(e)             BF_CLKCTRL_CPU_DIV(BV_CLKCTRL_CPU_DIV__##e)
+#define BFM_CLKCTRL_CPU_DIV_V(v)            BM_CLKCTRL_CPU_DIV
+
+#define HW_CLKCTRL_HBUS                         HW(CLKCTRL_HBUS)
+#define HWA_CLKCTRL_HBUS                        (0x80040000 + 0x30)
+#define HWT_CLKCTRL_HBUS                        HWIO_32_RW
+#define HWN_CLKCTRL_HBUS                        CLKCTRL_HBUS
+#define HWI_CLKCTRL_HBUS                        
+#define BP_CLKCTRL_HBUS_WAIT_PLL_LOCK           30
+#define BM_CLKCTRL_HBUS_WAIT_PLL_LOCK           0x40000000
+#define BF_CLKCTRL_HBUS_WAIT_PLL_LOCK(v)        (((v) & 0x1) << 30)
+#define BFM_CLKCTRL_HBUS_WAIT_PLL_LOCK(v)       BM_CLKCTRL_HBUS_WAIT_PLL_LOCK
+#define BF_CLKCTRL_HBUS_WAIT_PLL_LOCK_V(e)      BF_CLKCTRL_HBUS_WAIT_PLL_LOCK(BV_CLKCTRL_HBUS_WAIT_PLL_LOCK__##e)
+#define BFM_CLKCTRL_HBUS_WAIT_PLL_LOCK_V(v)     BM_CLKCTRL_HBUS_WAIT_PLL_LOCK
+#define BP_CLKCTRL_HBUS_BUSY                    29
+#define BM_CLKCTRL_HBUS_BUSY                    0x20000000
+#define BF_CLKCTRL_HBUS_BUSY(v)                 (((v) & 0x1) << 29)
+#define BFM_CLKCTRL_HBUS_BUSY(v)                BM_CLKCTRL_HBUS_BUSY
+#define BF_CLKCTRL_HBUS_BUSY_V(e)               BF_CLKCTRL_HBUS_BUSY(BV_CLKCTRL_HBUS_BUSY__##e)
+#define BFM_CLKCTRL_HBUS_BUSY_V(v)              BM_CLKCTRL_HBUS_BUSY
+#define BP_CLKCTRL_HBUS_EMI_BUSY_FAST           27
+#define BM_CLKCTRL_HBUS_EMI_BUSY_FAST           0x8000000
+#define BF_CLKCTRL_HBUS_EMI_BUSY_FAST(v)        (((v) & 0x1) << 27)
+#define BFM_CLKCTRL_HBUS_EMI_BUSY_FAST(v)       BM_CLKCTRL_HBUS_EMI_BUSY_FAST
+#define BF_CLKCTRL_HBUS_EMI_BUSY_FAST_V(e)      BF_CLKCTRL_HBUS_EMI_BUSY_FAST(BV_CLKCTRL_HBUS_EMI_BUSY_FAST__##e)
+#define BFM_CLKCTRL_HBUS_EMI_BUSY_FAST_V(v)     BM_CLKCTRL_HBUS_EMI_BUSY_FAST
+#define BP_CLKCTRL_HBUS_APBHDMA_BUSY_FAST       26
+#define BM_CLKCTRL_HBUS_APBHDMA_BUSY_FAST       0x4000000
+#define BF_CLKCTRL_HBUS_APBHDMA_BUSY_FAST(v)    (((v) & 0x1) << 26)
+#define BFM_CLKCTRL_HBUS_APBHDMA_BUSY_FAST(v)   BM_CLKCTRL_HBUS_APBHDMA_BUSY_FAST
+#define BF_CLKCTRL_HBUS_APBHDMA_BUSY_FAST_V(e)  BF_CLKCTRL_HBUS_APBHDMA_BUSY_FAST(BV_CLKCTRL_HBUS_APBHDMA_BUSY_FAST__##e)
+#define BFM_CLKCTRL_HBUS_APBHDMA_BUSY_FAST_V(v) BM_CLKCTRL_HBUS_APBHDMA_BUSY_FAST
+#define BP_CLKCTRL_HBUS_APBXDMA_BUSY_FAST       25
+#define BM_CLKCTRL_HBUS_APBXDMA_BUSY_FAST       0x2000000
+#define BF_CLKCTRL_HBUS_APBXDMA_BUSY_FAST(v)    (((v) & 0x1) << 25)
+#define BFM_CLKCTRL_HBUS_APBXDMA_BUSY_FAST(v)   BM_CLKCTRL_HBUS_APBXDMA_BUSY_FAST
+#define BF_CLKCTRL_HBUS_APBXDMA_BUSY_FAST_V(e)  BF_CLKCTRL_HBUS_APBXDMA_BUSY_FAST(BV_CLKCTRL_HBUS_APBXDMA_BUSY_FAST__##e)
+#define BFM_CLKCTRL_HBUS_APBXDMA_BUSY_FAST_V(v) BM_CLKCTRL_HBUS_APBXDMA_BUSY_FAST
+#define BP_CLKCTRL_HBUS_TRAFFIC_JAM_FAST        24
+#define BM_CLKCTRL_HBUS_TRAFFIC_JAM_FAST        0x1000000
+#define BF_CLKCTRL_HBUS_TRAFFIC_JAM_FAST(v)     (((v) & 0x1) << 24)
+#define BFM_CLKCTRL_HBUS_TRAFFIC_JAM_FAST(v)    BM_CLKCTRL_HBUS_TRAFFIC_JAM_FAST
+#define BF_CLKCTRL_HBUS_TRAFFIC_JAM_FAST_V(e)   BF_CLKCTRL_HBUS_TRAFFIC_JAM_FAST(BV_CLKCTRL_HBUS_TRAFFIC_JAM_FAST__##e)
+#define BFM_CLKCTRL_HBUS_TRAFFIC_JAM_FAST_V(v)  BM_CLKCTRL_HBUS_TRAFFIC_JAM_FAST
+#define BP_CLKCTRL_HBUS_TRAFFIC_FAST            23
+#define BM_CLKCTRL_HBUS_TRAFFIC_FAST            0x800000
+#define BF_CLKCTRL_HBUS_TRAFFIC_FAST(v)         (((v) & 0x1) << 23)
+#define BFM_CLKCTRL_HBUS_TRAFFIC_FAST(v)        BM_CLKCTRL_HBUS_TRAFFIC_FAST
+#define BF_CLKCTRL_HBUS_TRAFFIC_FAST_V(e)       BF_CLKCTRL_HBUS_TRAFFIC_FAST(BV_CLKCTRL_HBUS_TRAFFIC_FAST__##e)
+#define BFM_CLKCTRL_HBUS_TRAFFIC_FAST_V(v)      BM_CLKCTRL_HBUS_TRAFFIC_FAST
+#define BP_CLKCTRL_HBUS_CPU_DATA_FAST           22
+#define BM_CLKCTRL_HBUS_CPU_DATA_FAST           0x400000
+#define BF_CLKCTRL_HBUS_CPU_DATA_FAST(v)        (((v) & 0x1) << 22)
+#define BFM_CLKCTRL_HBUS_CPU_DATA_FAST(v)       BM_CLKCTRL_HBUS_CPU_DATA_FAST
+#define BF_CLKCTRL_HBUS_CPU_DATA_FAST_V(e)      BF_CLKCTRL_HBUS_CPU_DATA_FAST(BV_CLKCTRL_HBUS_CPU_DATA_FAST__##e)
+#define BFM_CLKCTRL_HBUS_CPU_DATA_FAST_V(v)     BM_CLKCTRL_HBUS_CPU_DATA_FAST
+#define BP_CLKCTRL_HBUS_CPU_INSTR_FAST          21
+#define BM_CLKCTRL_HBUS_CPU_INSTR_FAST          0x200000
+#define BF_CLKCTRL_HBUS_CPU_INSTR_FAST(v)       (((v) & 0x1) << 21)
+#define BFM_CLKCTRL_HBUS_CPU_INSTR_FAST(v)      BM_CLKCTRL_HBUS_CPU_INSTR_FAST
+#define BF_CLKCTRL_HBUS_CPU_INSTR_FAST_V(e)     BF_CLKCTRL_HBUS_CPU_INSTR_FAST(BV_CLKCTRL_HBUS_CPU_INSTR_FAST__##e)
+#define BFM_CLKCTRL_HBUS_CPU_INSTR_FAST_V(v)    BM_CLKCTRL_HBUS_CPU_INSTR_FAST
+#define BP_CLKCTRL_HBUS_AUTO_SLOW_MODE          20
+#define BM_CLKCTRL_HBUS_AUTO_SLOW_MODE          0x100000
+#define BF_CLKCTRL_HBUS_AUTO_SLOW_MODE(v)       (((v) & 0x1) << 20)
+#define BFM_CLKCTRL_HBUS_AUTO_SLOW_MODE(v)      BM_CLKCTRL_HBUS_AUTO_SLOW_MODE
+#define BF_CLKCTRL_HBUS_AUTO_SLOW_MODE_V(e)     BF_CLKCTRL_HBUS_AUTO_SLOW_MODE(BV_CLKCTRL_HBUS_AUTO_SLOW_MODE__##e)
+#define BFM_CLKCTRL_HBUS_AUTO_SLOW_MODE_V(v)    BM_CLKCTRL_HBUS_AUTO_SLOW_MODE
+#define BP_CLKCTRL_HBUS_SLOW_DIV                16
+#define BM_CLKCTRL_HBUS_SLOW_DIV                0x30000
+#define BV_CLKCTRL_HBUS_SLOW_DIV__BY1           0x0
+#define BV_CLKCTRL_HBUS_SLOW_DIV__BY2           0x1
+#define BV_CLKCTRL_HBUS_SLOW_DIV__BY4           0x2
+#define BV_CLKCTRL_HBUS_SLOW_DIV__BY8           0x3
+#define BF_CLKCTRL_HBUS_SLOW_DIV(v)             (((v) & 0x3) << 16)
+#define BFM_CLKCTRL_HBUS_SLOW_DIV(v)            BM_CLKCTRL_HBUS_SLOW_DIV
+#define BF_CLKCTRL_HBUS_SLOW_DIV_V(e)           BF_CLKCTRL_HBUS_SLOW_DIV(BV_CLKCTRL_HBUS_SLOW_DIV__##e)
+#define BFM_CLKCTRL_HBUS_SLOW_DIV_V(v)          BM_CLKCTRL_HBUS_SLOW_DIV
+#define BP_CLKCTRL_HBUS_DIV                     0
+#define BM_CLKCTRL_HBUS_DIV                     0x1f
+#define BF_CLKCTRL_HBUS_DIV(v)                  (((v) & 0x1f) << 0)
+#define BFM_CLKCTRL_HBUS_DIV(v)                 BM_CLKCTRL_HBUS_DIV
+#define BF_CLKCTRL_HBUS_DIV_V(e)                BF_CLKCTRL_HBUS_DIV(BV_CLKCTRL_HBUS_DIV__##e)
+#define BFM_CLKCTRL_HBUS_DIV_V(v)               BM_CLKCTRL_HBUS_DIV
+
+#define HW_CLKCTRL_XBUS             HW(CLKCTRL_XBUS)
+#define HWA_CLKCTRL_XBUS            (0x80040000 + 0x40)
+#define HWT_CLKCTRL_XBUS            HWIO_32_RW
+#define HWN_CLKCTRL_XBUS            CLKCTRL_XBUS
+#define HWI_CLKCTRL_XBUS            
+#define BP_CLKCTRL_XBUS_BUSY        31
+#define BM_CLKCTRL_XBUS_BUSY        0x80000000
+#define BF_CLKCTRL_XBUS_BUSY(v)     (((v) & 0x1) << 31)
+#define BFM_CLKCTRL_XBUS_BUSY(v)    BM_CLKCTRL_XBUS_BUSY
+#define BF_CLKCTRL_XBUS_BUSY_V(e)   BF_CLKCTRL_XBUS_BUSY(BV_CLKCTRL_XBUS_BUSY__##e)
+#define BFM_CLKCTRL_XBUS_BUSY_V(v)  BM_CLKCTRL_XBUS_BUSY
+#define BP_CLKCTRL_XBUS_DIV         0
+#define BM_CLKCTRL_XBUS_DIV         0x3ff
+#define BF_CLKCTRL_XBUS_DIV(v)      (((v) & 0x3ff) << 0)
+#define BFM_CLKCTRL_XBUS_DIV(v)     BM_CLKCTRL_XBUS_DIV
+#define BF_CLKCTRL_XBUS_DIV_V(e)    BF_CLKCTRL_XBUS_DIV(BV_CLKCTRL_XBUS_DIV__##e)
+#define BFM_CLKCTRL_XBUS_DIV_V(v)   BM_CLKCTRL_XBUS_DIV
+
+#define HW_CLKCTRL_XTAL                             HW(CLKCTRL_XTAL)
+#define HWA_CLKCTRL_XTAL                            (0x80040000 + 0x50)
+#define HWT_CLKCTRL_XTAL                            HWIO_32_RW
+#define HWN_CLKCTRL_XTAL                            CLKCTRL_XTAL
+#define HWI_CLKCTRL_XTAL                            
+#define BP_CLKCTRL_XTAL_UART_CLK_GATE               31
+#define BM_CLKCTRL_XTAL_UART_CLK_GATE               0x80000000
+#define BF_CLKCTRL_XTAL_UART_CLK_GATE(v)            (((v) & 0x1) << 31)
+#define BFM_CLKCTRL_XTAL_UART_CLK_GATE(v)           BM_CLKCTRL_XTAL_UART_CLK_GATE
+#define BF_CLKCTRL_XTAL_UART_CLK_GATE_V(e)          BF_CLKCTRL_XTAL_UART_CLK_GATE(BV_CLKCTRL_XTAL_UART_CLK_GATE__##e)
+#define BFM_CLKCTRL_XTAL_UART_CLK_GATE_V(v)         BM_CLKCTRL_XTAL_UART_CLK_GATE
+#define BP_CLKCTRL_XTAL_FILT_CLK24M_GATE            30
+#define BM_CLKCTRL_XTAL_FILT_CLK24M_GATE            0x40000000
+#define BF_CLKCTRL_XTAL_FILT_CLK24M_GATE(v)         (((v) & 0x1) << 30)
+#define BFM_CLKCTRL_XTAL_FILT_CLK24M_GATE(v)        BM_CLKCTRL_XTAL_FILT_CLK24M_GATE
+#define BF_CLKCTRL_XTAL_FILT_CLK24M_GATE_V(e)       BF_CLKCTRL_XTAL_FILT_CLK24M_GATE(BV_CLKCTRL_XTAL_FILT_CLK24M_GATE__##e)
+#define BFM_CLKCTRL_XTAL_FILT_CLK24M_GATE_V(v)      BM_CLKCTRL_XTAL_FILT_CLK24M_GATE
+#define BP_CLKCTRL_XTAL_PWM_CLK24M_GATE             29
+#define BM_CLKCTRL_XTAL_PWM_CLK24M_GATE             0x20000000
+#define BF_CLKCTRL_XTAL_PWM_CLK24M_GATE(v)          (((v) & 0x1) << 29)
+#define BFM_CLKCTRL_XTAL_PWM_CLK24M_GATE(v)         BM_CLKCTRL_XTAL_PWM_CLK24M_GATE
+#define BF_CLKCTRL_XTAL_PWM_CLK24M_GATE_V(e)        BF_CLKCTRL_XTAL_PWM_CLK24M_GATE(BV_CLKCTRL_XTAL_PWM_CLK24M_GATE__##e)
+#define BFM_CLKCTRL_XTAL_PWM_CLK24M_GATE_V(v)       BM_CLKCTRL_XTAL_PWM_CLK24M_GATE
+#define BP_CLKCTRL_XTAL_DRI_CLK24M_GATE             28
+#define BM_CLKCTRL_XTAL_DRI_CLK24M_GATE             0x10000000
+#define BF_CLKCTRL_XTAL_DRI_CLK24M_GATE(v)          (((v) & 0x1) << 28)
+#define BFM_CLKCTRL_XTAL_DRI_CLK24M_GATE(v)         BM_CLKCTRL_XTAL_DRI_CLK24M_GATE
+#define BF_CLKCTRL_XTAL_DRI_CLK24M_GATE_V(e)        BF_CLKCTRL_XTAL_DRI_CLK24M_GATE(BV_CLKCTRL_XTAL_DRI_CLK24M_GATE__##e)
+#define BFM_CLKCTRL_XTAL_DRI_CLK24M_GATE_V(v)       BM_CLKCTRL_XTAL_DRI_CLK24M_GATE
+#define BP_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE          27
+#define BM_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE          0x8000000
+#define BF_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE(v)       (((v) & 0x1) << 27)
+#define BFM_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE(v)      BM_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE
+#define BF_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE_V(e)     BF_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE(BV_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE__##e)
+#define BFM_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE_V(v)    BM_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE
+#define BP_CLKCTRL_XTAL_TIMROT_CLK32K_GATE          26
+#define BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE          0x4000000
+#define BF_CLKCTRL_XTAL_TIMROT_CLK32K_GATE(v)       (((v) & 0x1) << 26)
+#define BFM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE(v)      BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE
+#define BF_CLKCTRL_XTAL_TIMROT_CLK32K_GATE_V(e)     BF_CLKCTRL_XTAL_TIMROT_CLK32K_GATE(BV_CLKCTRL_XTAL_TIMROT_CLK32K_GATE__##e)
+#define BFM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE_V(v)    BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE
+#define BP_CLKCTRL_XTAL_EXRAM_CLK16K_GATE           25
+#define BM_CLKCTRL_XTAL_EXRAM_CLK16K_GATE           0x2000000
+#define BF_CLKCTRL_XTAL_EXRAM_CLK16K_GATE(v)        (((v) & 0x1) << 25)
+#define BFM_CLKCTRL_XTAL_EXRAM_CLK16K_GATE(v)       BM_CLKCTRL_XTAL_EXRAM_CLK16K_GATE
+#define BF_CLKCTRL_XTAL_EXRAM_CLK16K_GATE_V(e)      BF_CLKCTRL_XTAL_EXRAM_CLK16K_GATE(BV_CLKCTRL_XTAL_EXRAM_CLK16K_GATE__##e)
+#define BFM_CLKCTRL_XTAL_EXRAM_CLK16K_GATE_V(v)     BM_CLKCTRL_XTAL_EXRAM_CLK16K_GATE
+#define BP_CLKCTRL_XTAL_LRADC_CLK2K_GATE            24
+#define BM_CLKCTRL_XTAL_LRADC_CLK2K_GATE            0x1000000
+#define BF_CLKCTRL_XTAL_LRADC_CLK2K_GATE(v)         (((v) & 0x1) << 24)
+#define BFM_CLKCTRL_XTAL_LRADC_CLK2K_GATE(v)        BM_CLKCTRL_XTAL_LRADC_CLK2K_GATE
+#define BF_CLKCTRL_XTAL_LRADC_CLK2K_GATE_V(e)       BF_CLKCTRL_XTAL_LRADC_CLK2K_GATE(BV_CLKCTRL_XTAL_LRADC_CLK2K_GATE__##e)
+#define BFM_CLKCTRL_XTAL_LRADC_CLK2K_GATE_V(v)      BM_CLKCTRL_XTAL_LRADC_CLK2K_GATE
+
+#define HW_CLKCTRL_OCRAM                HW(CLKCTRL_OCRAM)
+#define HWA_CLKCTRL_OCRAM               (0x80040000 + 0x60)
+#define HWT_CLKCTRL_OCRAM               HWIO_32_RW
+#define HWN_CLKCTRL_OCRAM               CLKCTRL_OCRAM
+#define HWI_CLKCTRL_OCRAM               
+#define BP_CLKCTRL_OCRAM_CLKGATE        31
+#define BM_CLKCTRL_OCRAM_CLKGATE        0x80000000
+#define BF_CLKCTRL_OCRAM_CLKGATE(v)     (((v) & 0x1) << 31)
+#define BFM_CLKCTRL_OCRAM_CLKGATE(v)    BM_CLKCTRL_OCRAM_CLKGATE
+#define BF_CLKCTRL_OCRAM_CLKGATE_V(e)   BF_CLKCTRL_OCRAM_CLKGATE(BV_CLKCTRL_OCRAM_CLKGATE__##e)
+#define BFM_CLKCTRL_OCRAM_CLKGATE_V(v)  BM_CLKCTRL_OCRAM_CLKGATE
+#define BP_CLKCTRL_OCRAM_BUSY           30
+#define BM_CLKCTRL_OCRAM_BUSY           0x40000000
+#define BF_CLKCTRL_OCRAM_BUSY(v)        (((v) & 0x1) << 30)
+#define BFM_CLKCTRL_OCRAM_BUSY(v)       BM_CLKCTRL_OCRAM_BUSY
+#define BF_CLKCTRL_OCRAM_BUSY_V(e)      BF_CLKCTRL_OCRAM_BUSY(BV_CLKCTRL_OCRAM_BUSY__##e)
+#define BFM_CLKCTRL_OCRAM_BUSY_V(v)     BM_CLKCTRL_OCRAM_BUSY
+#define BP_CLKCTRL_OCRAM_DIV            0
+#define BM_CLKCTRL_OCRAM_DIV            0x3ff
+#define BF_CLKCTRL_OCRAM_DIV(v)         (((v) & 0x3ff) << 0)
+#define BFM_CLKCTRL_OCRAM_DIV(v)        BM_CLKCTRL_OCRAM_DIV
+#define BF_CLKCTRL_OCRAM_DIV_V(e)       BF_CLKCTRL_OCRAM_DIV(BV_CLKCTRL_OCRAM_DIV__##e)
+#define BFM_CLKCTRL_OCRAM_DIV_V(v)      BM_CLKCTRL_OCRAM_DIV
+
+#define HW_CLKCTRL_UTMI                         HW(CLKCTRL_UTMI)
+#define HWA_CLKCTRL_UTMI                        (0x80040000 + 0x70)
+#define HWT_CLKCTRL_UTMI                        HWIO_32_RW
+#define HWN_CLKCTRL_UTMI                        CLKCTRL_UTMI
+#define HWI_CLKCTRL_UTMI                        
+#define BP_CLKCTRL_UTMI_UTMI_CLK120M_GATE       31
+#define BM_CLKCTRL_UTMI_UTMI_CLK120M_GATE       0x80000000
+#define BF_CLKCTRL_UTMI_UTMI_CLK120M_GATE(v)    (((v) & 0x1) << 31)
+#define BFM_CLKCTRL_UTMI_UTMI_CLK120M_GATE(v)   BM_CLKCTRL_UTMI_UTMI_CLK120M_GATE
+#define BF_CLKCTRL_UTMI_UTMI_CLK120M_GATE_V(e)  BF_CLKCTRL_UTMI_UTMI_CLK120M_GATE(BV_CLKCTRL_UTMI_UTMI_CLK120M_GATE__##e)
+#define BFM_CLKCTRL_UTMI_UTMI_CLK120M_GATE_V(v) BM_CLKCTRL_UTMI_UTMI_CLK120M_GATE
+#define BP_CLKCTRL_UTMI_UTMI_CLK30M_GATE        30
+#define BM_CLKCTRL_UTMI_UTMI_CLK30M_GATE        0x40000000
+#define BF_CLKCTRL_UTMI_UTMI_CLK30M_GATE(v)     (((v) & 0x1) << 30)
+#define BFM_CLKCTRL_UTMI_UTMI_CLK30M_GATE(v)    BM_CLKCTRL_UTMI_UTMI_CLK30M_GATE
+#define BF_CLKCTRL_UTMI_UTMI_CLK30M_GATE_V(e)   BF_CLKCTRL_UTMI_UTMI_CLK30M_GATE(BV_CLKCTRL_UTMI_UTMI_CLK30M_GATE__##e)
+#define BFM_CLKCTRL_UTMI_UTMI_CLK30M_GATE_V(v)  BM_CLKCTRL_UTMI_UTMI_CLK30M_GATE
+
+#define HW_CLKCTRL_SSP                      HW(CLKCTRL_SSP)
+#define HWA_CLKCTRL_SSP                     (0x80040000 + 0x80)
+#define HWT_CLKCTRL_SSP                     HWIO_32_RW
+#define HWN_CLKCTRL_SSP                     CLKCTRL_SSP
+#define HWI_CLKCTRL_SSP                     
+#define BP_CLKCTRL_SSP_CLKGATE              31
+#define BM_CLKCTRL_SSP_CLKGATE              0x80000000
+#define BF_CLKCTRL_SSP_CLKGATE(v)           (((v) & 0x1) << 31)
+#define BFM_CLKCTRL_SSP_CLKGATE(v)          BM_CLKCTRL_SSP_CLKGATE
+#define BF_CLKCTRL_SSP_CLKGATE_V(e)         BF_CLKCTRL_SSP_CLKGATE(BV_CLKCTRL_SSP_CLKGATE__##e)
+#define BFM_CLKCTRL_SSP_CLKGATE_V(v)        BM_CLKCTRL_SSP_CLKGATE
+#define BP_CLKCTRL_SSP_WAIT_PLL_LOCK        30
+#define BM_CLKCTRL_SSP_WAIT_PLL_LOCK        0x40000000
+#define BF_CLKCTRL_SSP_WAIT_PLL_LOCK(v)     (((v) & 0x1) << 30)
+#define BFM_CLKCTRL_SSP_WAIT_PLL_LOCK(v)    BM_CLKCTRL_SSP_WAIT_PLL_LOCK
+#define BF_CLKCTRL_SSP_WAIT_PLL_LOCK_V(e)   BF_CLKCTRL_SSP_WAIT_PLL_LOCK(BV_CLKCTRL_SSP_WAIT_PLL_LOCK__##e)
+#define BFM_CLKCTRL_SSP_WAIT_PLL_LOCK_V(v)  BM_CLKCTRL_SSP_WAIT_PLL_LOCK
+#define BP_CLKCTRL_SSP_BUSY                 29
+#define BM_CLKCTRL_SSP_BUSY                 0x20000000
+#define BF_CLKCTRL_SSP_BUSY(v)              (((v) & 0x1) << 29)
+#define BFM_CLKCTRL_SSP_BUSY(v)             BM_CLKCTRL_SSP_BUSY
+#define BF_CLKCTRL_SSP_BUSY_V(e)            BF_CLKCTRL_SSP_BUSY(BV_CLKCTRL_SSP_BUSY__##e)
+#define BFM_CLKCTRL_SSP_BUSY_V(v)           BM_CLKCTRL_SSP_BUSY
+#define BP_CLKCTRL_SSP_DIV                  0
+#define BM_CLKCTRL_SSP_DIV                  0x1ff
+#define BF_CLKCTRL_SSP_DIV(v)               (((v) & 0x1ff) << 0)
+#define BFM_CLKCTRL_SSP_DIV(v)              BM_CLKCTRL_SSP_DIV
+#define BF_CLKCTRL_SSP_DIV_V(e)             BF_CLKCTRL_SSP_DIV(BV_CLKCTRL_SSP_DIV__##e)
+#define BFM_CLKCTRL_SSP_DIV_V(v)            BM_CLKCTRL_SSP_DIV
+
+#define HW_CLKCTRL_GPMI                     HW(CLKCTRL_GPMI)
+#define HWA_CLKCTRL_GPMI                    (0x80040000 + 0x90)
+#define HWT_CLKCTRL_GPMI                    HWIO_32_RW
+#define HWN_CLKCTRL_GPMI                    CLKCTRL_GPMI
+#define HWI_CLKCTRL_GPMI                    
+#define BP_CLKCTRL_GPMI_CLKGATE             31
+#define BM_CLKCTRL_GPMI_CLKGATE             0x80000000
+#define BF_CLKCTRL_GPMI_CLKGATE(v)          (((v) & 0x1) << 31)
+#define BFM_CLKCTRL_GPMI_CLKGATE(v)         BM_CLKCTRL_GPMI_CLKGATE
+#define BF_CLKCTRL_GPMI_CLKGATE_V(e)        BF_CLKCTRL_GPMI_CLKGATE(BV_CLKCTRL_GPMI_CLKGATE__##e)
+#define BFM_CLKCTRL_GPMI_CLKGATE_V(v)       BM_CLKCTRL_GPMI_CLKGATE
+#define BP_CLKCTRL_GPMI_WAIT_PLL_LOCK       30
+#define BM_CLKCTRL_GPMI_WAIT_PLL_LOCK       0x40000000
+#define BF_CLKCTRL_GPMI_WAIT_PLL_LOCK(v)    (((v) & 0x1) << 30)
+#define BFM_CLKCTRL_GPMI_WAIT_PLL_LOCK(v)   BM_CLKCTRL_GPMI_WAIT_PLL_LOCK
+#define BF_CLKCTRL_GPMI_WAIT_PLL_LOCK_V(e)  BF_CLKCTRL_GPMI_WAIT_PLL_LOCK(BV_CLKCTRL_GPMI_WAIT_PLL_LOCK__##e)
+#define BFM_CLKCTRL_GPMI_WAIT_PLL_LOCK_V(v) BM_CLKCTRL_GPMI_WAIT_PLL_LOCK
+#define BP_CLKCTRL_GPMI_BUSY                29
+#define BM_CLKCTRL_GPMI_BUSY                0x20000000
+#define BF_CLKCTRL_GPMI_BUSY(v)             (((v) & 0x1) << 29)
+#define BFM_CLKCTRL_GPMI_BUSY(v)            BM_CLKCTRL_GPMI_BUSY
+#define BF_CLKCTRL_GPMI_BUSY_V(e)           BF_CLKCTRL_GPMI_BUSY(BV_CLKCTRL_GPMI_BUSY__##e)
+#define BFM_CLKCTRL_GPMI_BUSY_V(v)          BM_CLKCTRL_GPMI_BUSY
+#define BP_CLKCTRL_GPMI_DIV                 0
+#define BM_CLKCTRL_GPMI_DIV                 0x3ff
+#define BF_CLKCTRL_GPMI_DIV(v)              (((v) & 0x3ff) << 0)
+#define BFM_CLKCTRL_GPMI_DIV(v)             BM_CLKCTRL_GPMI_DIV
+#define BF_CLKCTRL_GPMI_DIV_V(e)            BF_CLKCTRL_GPMI_DIV(BV_CLKCTRL_GPMI_DIV__##e)
+#define BFM_CLKCTRL_GPMI_DIV_V(v)           BM_CLKCTRL_GPMI_DIV
+
+#define HW_CLKCTRL_SPDIF                HW(CLKCTRL_SPDIF)
+#define HWA_CLKCTRL_SPDIF               (0x80040000 + 0xa0)
+#define HWT_CLKCTRL_SPDIF               HWIO_32_RW
+#define HWN_CLKCTRL_SPDIF               CLKCTRL_SPDIF
+#define HWI_CLKCTRL_SPDIF               
+#define BP_CLKCTRL_SPDIF_CLKGATE        31
+#define BM_CLKCTRL_SPDIF_CLKGATE        0x80000000
+#define BF_CLKCTRL_SPDIF_CLKGATE(v)     (((v) & 0x1) << 31)
+#define BFM_CLKCTRL_SPDIF_CLKGATE(v)    BM_CLKCTRL_SPDIF_CLKGATE
+#define BF_CLKCTRL_SPDIF_CLKGATE_V(e)   BF_CLKCTRL_SPDIF_CLKGATE(BV_CLKCTRL_SPDIF_CLKGATE__##e)
+#define BFM_CLKCTRL_SPDIF_CLKGATE_V(v)  BM_CLKCTRL_SPDIF_CLKGATE
+#define BP_CLKCTRL_SPDIF_BUSY           30
+#define BM_CLKCTRL_SPDIF_BUSY           0x40000000
+#define BF_CLKCTRL_SPDIF_BUSY(v)        (((v) & 0x1) << 30)
+#define BFM_CLKCTRL_SPDIF_BUSY(v)       BM_CLKCTRL_SPDIF_BUSY
+#define BF_CLKCTRL_SPDIF_BUSY_V(e)      BF_CLKCTRL_SPDIF_BUSY(BV_CLKCTRL_SPDIF_BUSY__##e)
+#define BFM_CLKCTRL_SPDIF_BUSY_V(v)     BM_CLKCTRL_SPDIF_BUSY
+#define BP_CLKCTRL_SPDIF_DIV            0
+#define BM_CLKCTRL_SPDIF_DIV            0x7
+#define BF_CLKCTRL_SPDIF_DIV(v)         (((v) & 0x7) << 0)
+#define BFM_CLKCTRL_SPDIF_DIV(v)        BM_CLKCTRL_SPDIF_DIV
+#define BF_CLKCTRL_SPDIF_DIV_V(e)       BF_CLKCTRL_SPDIF_DIV(BV_CLKCTRL_SPDIF_DIV__##e)
+#define BFM_CLKCTRL_SPDIF_DIV_V(v)      BM_CLKCTRL_SPDIF_DIV
+
+#define HW_CLKCTRL_EMI                      HW(CLKCTRL_EMI)
+#define HWA_CLKCTRL_EMI                     (0x80040000 + 0xb0)
+#define HWT_CLKCTRL_EMI                     HWIO_32_RW
+#define HWN_CLKCTRL_EMI                     CLKCTRL_EMI
+#define HWI_CLKCTRL_EMI                     
+#define BP_CLKCTRL_EMI_CLKGATE              31
+#define BM_CLKCTRL_EMI_CLKGATE              0x80000000
+#define BF_CLKCTRL_EMI_CLKGATE(v)           (((v) & 0x1) << 31)
+#define BFM_CLKCTRL_EMI_CLKGATE(v)          BM_CLKCTRL_EMI_CLKGATE
+#define BF_CLKCTRL_EMI_CLKGATE_V(e)         BF_CLKCTRL_EMI_CLKGATE(BV_CLKCTRL_EMI_CLKGATE__##e)
+#define BFM_CLKCTRL_EMI_CLKGATE_V(v)        BM_CLKCTRL_EMI_CLKGATE
+#define BP_CLKCTRL_EMI_WAIT_PLL_LOCK        30
+#define BM_CLKCTRL_EMI_WAIT_PLL_LOCK        0x40000000
+#define BF_CLKCTRL_EMI_WAIT_PLL_LOCK(v)     (((v) & 0x1) << 30)
+#define BFM_CLKCTRL_EMI_WAIT_PLL_LOCK(v)    BM_CLKCTRL_EMI_WAIT_PLL_LOCK
+#define BF_CLKCTRL_EMI_WAIT_PLL_LOCK_V(e)   BF_CLKCTRL_EMI_WAIT_PLL_LOCK(BV_CLKCTRL_EMI_WAIT_PLL_LOCK__##e)
+#define BFM_CLKCTRL_EMI_WAIT_PLL_LOCK_V(v)  BM_CLKCTRL_EMI_WAIT_PLL_LOCK
+#define BP_CLKCTRL_EMI_BUSY                 29
+#define BM_CLKCTRL_EMI_BUSY                 0x20000000
+#define BF_CLKCTRL_EMI_BUSY(v)              (((v) & 0x1) << 29)
+#define BFM_CLKCTRL_EMI_BUSY(v)             BM_CLKCTRL_EMI_BUSY
+#define BF_CLKCTRL_EMI_BUSY_V(e)            BF_CLKCTRL_EMI_BUSY(BV_CLKCTRL_EMI_BUSY__##e)
+#define BFM_CLKCTRL_EMI_BUSY_V(v)           BM_CLKCTRL_EMI_BUSY
+#define BP_CLKCTRL_EMI_DIV                  0
+#define BM_CLKCTRL_EMI_DIV                  0x7
+#define BF_CLKCTRL_EMI_DIV(v)               (((v) & 0x7) << 0)
+#define BFM_CLKCTRL_EMI_DIV(v)              BM_CLKCTRL_EMI_DIV
+#define BF_CLKCTRL_EMI_DIV_V(e)             BF_CLKCTRL_EMI_DIV(BV_CLKCTRL_EMI_DIV__##e)
+#define BFM_CLKCTRL_EMI_DIV_V(v)            BM_CLKCTRL_EMI_DIV
+
+#define HW_CLKCTRL_IR                       HW(CLKCTRL_IR)
+#define HWA_CLKCTRL_IR                      (0x80040000 + 0xc0)
+#define HWT_CLKCTRL_IR                      HWIO_32_RW
+#define HWN_CLKCTRL_IR                      CLKCTRL_IR
+#define HWI_CLKCTRL_IR                      
+#define BP_CLKCTRL_IR_CLKGATE               31
+#define BM_CLKCTRL_IR_CLKGATE               0x80000000
+#define BF_CLKCTRL_IR_CLKGATE(v)            (((v) & 0x1) << 31)
+#define BFM_CLKCTRL_IR_CLKGATE(v)           BM_CLKCTRL_IR_CLKGATE
+#define BF_CLKCTRL_IR_CLKGATE_V(e)          BF_CLKCTRL_IR_CLKGATE(BV_CLKCTRL_IR_CLKGATE__##e)
+#define BFM_CLKCTRL_IR_CLKGATE_V(v)         BM_CLKCTRL_IR_CLKGATE
+#define BP_CLKCTRL_IR_WAIT_PLL_LOCK         30
+#define BM_CLKCTRL_IR_WAIT_PLL_LOCK         0x40000000
+#define BF_CLKCTRL_IR_WAIT_PLL_LOCK(v)      (((v) & 0x1) << 30)
+#define BFM_CLKCTRL_IR_WAIT_PLL_LOCK(v)     BM_CLKCTRL_IR_WAIT_PLL_LOCK
+#define BF_CLKCTRL_IR_WAIT_PLL_LOCK_V(e)    BF_CLKCTRL_IR_WAIT_PLL_LOCK(BV_CLKCTRL_IR_WAIT_PLL_LOCK__##e)
+#define BFM_CLKCTRL_IR_WAIT_PLL_LOCK_V(v)   BM_CLKCTRL_IR_WAIT_PLL_LOCK
+#define BP_CLKCTRL_IR_AUTO_DIV              29
+#define BM_CLKCTRL_IR_AUTO_DIV              0x20000000
+#define BF_CLKCTRL_IR_AUTO_DIV(v)           (((v) & 0x1) << 29)
+#define BFM_CLKCTRL_IR_AUTO_DIV(v)          BM_CLKCTRL_IR_AUTO_DIV
+#define BF_CLKCTRL_IR_AUTO_DIV_V(e)         BF_CLKCTRL_IR_AUTO_DIV(BV_CLKCTRL_IR_AUTO_DIV__##e)
+#define BFM_CLKCTRL_IR_AUTO_DIV_V(v)        BM_CLKCTRL_IR_AUTO_DIV
+#define BP_CLKCTRL_IR_IR_BUSY               28
+#define BM_CLKCTRL_IR_IR_BUSY               0x10000000
+#define BF_CLKCTRL_IR_IR_BUSY(v)            (((v) & 0x1) << 28)
+#define BFM_CLKCTRL_IR_IR_BUSY(v)           BM_CLKCTRL_IR_IR_BUSY
+#define BF_CLKCTRL_IR_IR_BUSY_V(e)          BF_CLKCTRL_IR_IR_BUSY(BV_CLKCTRL_IR_IR_BUSY__##e)
+#define BFM_CLKCTRL_IR_IR_BUSY_V(v)         BM_CLKCTRL_IR_IR_BUSY
+#define BP_CLKCTRL_IR_IROV_BUSY             27
+#define BM_CLKCTRL_IR_IROV_BUSY             0x8000000
+#define BF_CLKCTRL_IR_IROV_BUSY(v)          (((v) & 0x1) << 27)
+#define BFM_CLKCTRL_IR_IROV_BUSY(v)         BM_CLKCTRL_IR_IROV_BUSY
+#define BF_CLKCTRL_IR_IROV_BUSY_V(e)        BF_CLKCTRL_IR_IROV_BUSY(BV_CLKCTRL_IR_IROV_BUSY__##e)
+#define BFM_CLKCTRL_IR_IROV_BUSY_V(v)       BM_CLKCTRL_IR_IROV_BUSY
+#define BP_CLKCTRL_IR_IROV_DIV              16
+#define BM_CLKCTRL_IR_IROV_DIV              0x1ff0000
+#define BF_CLKCTRL_IR_IROV_DIV(v)           (((v) & 0x1ff) << 16)
+#define BFM_CLKCTRL_IR_IROV_DIV(v)          BM_CLKCTRL_IR_IROV_DIV
+#define BF_CLKCTRL_IR_IROV_DIV_V(e)         BF_CLKCTRL_IR_IROV_DIV(BV_CLKCTRL_IR_IROV_DIV__##e)
+#define BFM_CLKCTRL_IR_IROV_DIV_V(v)        BM_CLKCTRL_IR_IROV_DIV
+#define BP_CLKCTRL_IR_IR_DIV                0
+#define BM_CLKCTRL_IR_IR_DIV                0x3ff
+#define BF_CLKCTRL_IR_IR_DIV(v)             (((v) & 0x3ff) << 0)
+#define BFM_CLKCTRL_IR_IR_DIV(v)            BM_CLKCTRL_IR_IR_DIV
+#define BF_CLKCTRL_IR_IR_DIV_V(e)           BF_CLKCTRL_IR_IR_DIV(BV_CLKCTRL_IR_IR_DIV__##e)
+#define BFM_CLKCTRL_IR_IR_DIV_V(v)          BM_CLKCTRL_IR_IR_DIV
+
+#endif /* __HEADERGEN_STMP3600_CLKCTRL_H__*/
diff --git a/firmware/target/arm/imx233/regs/stmp3600/dacdma.h b/firmware/target/arm/imx233/regs/stmp3600/dacdma.h
new file mode 100644
index 0000000000..61b6c35d9c
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3600/dacdma.h
@@ -0,0 +1,84 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * stmp3600 version: 2.4.0
+ * stmp3600 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_STMP3600_DACDMA_H__
+#define __HEADERGEN_STMP3600_DACDMA_H__
+
+#define HW_DACDMA_CTRL                  HW(DACDMA_CTRL)
+#define HWA_DACDMA_CTRL                 (0x8004c000 + 0x0)
+#define HWT_DACDMA_CTRL                 HWIO_32_RW
+#define HWN_DACDMA_CTRL                 DACDMA_CTRL
+#define HWI_DACDMA_CTRL                 
+#define HW_DACDMA_CTRL_SET              HW(DACDMA_CTRL_SET)
+#define HWA_DACDMA_CTRL_SET             (HWA_DACDMA_CTRL + 0x4)
+#define HWT_DACDMA_CTRL_SET             HWIO_32_WO
+#define HWN_DACDMA_CTRL_SET             DACDMA_CTRL
+#define HWI_DACDMA_CTRL_SET             
+#define HW_DACDMA_CTRL_CLR              HW(DACDMA_CTRL_CLR)
+#define HWA_DACDMA_CTRL_CLR             (HWA_DACDMA_CTRL + 0x8)
+#define HWT_DACDMA_CTRL_CLR             HWIO_32_WO
+#define HWN_DACDMA_CTRL_CLR             DACDMA_CTRL
+#define HWI_DACDMA_CTRL_CLR             
+#define HW_DACDMA_CTRL_TOG              HW(DACDMA_CTRL_TOG)
+#define HWA_DACDMA_CTRL_TOG             (HWA_DACDMA_CTRL + 0xc)
+#define HWT_DACDMA_CTRL_TOG             HWIO_32_WO
+#define HWN_DACDMA_CTRL_TOG             DACDMA_CTRL
+#define HWI_DACDMA_CTRL_TOG             
+#define BP_DACDMA_CTRL_SFTRST           31
+#define BM_DACDMA_CTRL_SFTRST           0x80000000
+#define BF_DACDMA_CTRL_SFTRST(v)        (((v) & 0x1) << 31)
+#define BFM_DACDMA_CTRL_SFTRST(v)       BM_DACDMA_CTRL_SFTRST
+#define BF_DACDMA_CTRL_SFTRST_V(e)      BF_DACDMA_CTRL_SFTRST(BV_DACDMA_CTRL_SFTRST__##e)
+#define BFM_DACDMA_CTRL_SFTRST_V(v)     BM_DACDMA_CTRL_SFTRST
+#define BP_DACDMA_CTRL_CLKGATE          30
+#define BM_DACDMA_CTRL_CLKGATE          0x40000000
+#define BF_DACDMA_CTRL_CLKGATE(v)       (((v) & 0x1) << 30)
+#define BFM_DACDMA_CTRL_CLKGATE(v)      BM_DACDMA_CTRL_CLKGATE
+#define BF_DACDMA_CTRL_CLKGATE_V(e)     BF_DACDMA_CTRL_CLKGATE(BV_DACDMA_CTRL_CLKGATE__##e)
+#define BFM_DACDMA_CTRL_CLKGATE_V(v)    BM_DACDMA_CTRL_CLKGATE
+#define BP_DACDMA_CTRL_RUN              0
+#define BM_DACDMA_CTRL_RUN              0x1
+#define BF_DACDMA_CTRL_RUN(v)           (((v) & 0x1) << 0)
+#define BFM_DACDMA_CTRL_RUN(v)          BM_DACDMA_CTRL_RUN
+#define BF_DACDMA_CTRL_RUN_V(e)         BF_DACDMA_CTRL_RUN(BV_DACDMA_CTRL_RUN__##e)
+#define BFM_DACDMA_CTRL_RUN_V(v)        BM_DACDMA_CTRL_RUN
+
+#define HW_DACDMA_DATA              HW(DACDMA_DATA)
+#define HWA_DACDMA_DATA             (0x8004c000 + 0x80)
+#define HWT_DACDMA_DATA             HWIO_32_RW
+#define HWN_DACDMA_DATA             DACDMA_DATA
+#define HWI_DACDMA_DATA             
+#define BP_DACDMA_DATA_HIGH         16
+#define BM_DACDMA_DATA_HIGH         0xffff0000
+#define BF_DACDMA_DATA_HIGH(v)      (((v) & 0xffff) << 16)
+#define BFM_DACDMA_DATA_HIGH(v)     BM_DACDMA_DATA_HIGH
+#define BF_DACDMA_DATA_HIGH_V(e)    BF_DACDMA_DATA_HIGH(BV_DACDMA_DATA_HIGH__##e)
+#define BFM_DACDMA_DATA_HIGH_V(v)   BM_DACDMA_DATA_HIGH
+#define BP_DACDMA_DATA_LOW          0
+#define BM_DACDMA_DATA_LOW          0xffff
+#define BF_DACDMA_DATA_LOW(v)       (((v) & 0xffff) << 0)
+#define BFM_DACDMA_DATA_LOW(v)      BM_DACDMA_DATA_LOW
+#define BF_DACDMA_DATA_LOW_V(e)     BF_DACDMA_DATA_LOW(BV_DACDMA_DATA_LOW__##e)
+#define BFM_DACDMA_DATA_LOW_V(v)    BM_DACDMA_DATA_LOW
+
+#endif /* __HEADERGEN_STMP3600_DACDMA_H__*/
diff --git a/firmware/target/arm/imx233/regs/stmp3600/digctl.h b/firmware/target/arm/imx233/regs/stmp3600/digctl.h
new file mode 100644
index 0000000000..6623785603
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3600/digctl.h
@@ -0,0 +1,855 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * stmp3600 version: 2.4.0
+ * stmp3600 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_STMP3600_DIGCTL_H__
+#define __HEADERGEN_STMP3600_DIGCTL_H__
+
+#define HW_DIGCTL_CTRL                                  HW(DIGCTL_CTRL)
+#define HWA_DIGCTL_CTRL                                 (0x8001c000 + 0x0)
+#define HWT_DIGCTL_CTRL                                 HWIO_32_RW
+#define HWN_DIGCTL_CTRL                                 DIGCTL_CTRL
+#define HWI_DIGCTL_CTRL                                 
+#define HW_DIGCTL_CTRL_SET                              HW(DIGCTL_CTRL_SET)
+#define HWA_DIGCTL_CTRL_SET                             (HWA_DIGCTL_CTRL + 0x4)
+#define HWT_DIGCTL_CTRL_SET                             HWIO_32_WO
+#define HWN_DIGCTL_CTRL_SET                             DIGCTL_CTRL
+#define HWI_DIGCTL_CTRL_SET                             
+#define HW_DIGCTL_CTRL_CLR                              HW(DIGCTL_CTRL_CLR)
+#define HWA_DIGCTL_CTRL_CLR                             (HWA_DIGCTL_CTRL + 0x8)
+#define HWT_DIGCTL_CTRL_CLR                             HWIO_32_WO
+#define HWN_DIGCTL_CTRL_CLR                             DIGCTL_CTRL
+#define HWI_DIGCTL_CTRL_CLR                             
+#define HW_DIGCTL_CTRL_TOG                              HW(DIGCTL_CTRL_TOG)
+#define HWA_DIGCTL_CTRL_TOG                             (HWA_DIGCTL_CTRL + 0xc)
+#define HWT_DIGCTL_CTRL_TOG                             HWIO_32_WO
+#define HWN_DIGCTL_CTRL_TOG                             DIGCTL_CTRL
+#define HWI_DIGCTL_CTRL_TOG                             
+#define BP_DIGCTL_CTRL_MASTER_SELECT                    24
+#define BM_DIGCTL_CTRL_MASTER_SELECT                    0x1f000000
+#define BV_DIGCTL_CTRL_MASTER_SELECT__ARM_I             0x1
+#define BV_DIGCTL_CTRL_MASTER_SELECT__ARM_D             0x2
+#define BV_DIGCTL_CTRL_MASTER_SELECT__USB               0x4
+#define BV_DIGCTL_CTRL_MASTER_SELECT__APBH              0x8
+#define BV_DIGCTL_CTRL_MASTER_SELECT__APBX              0x10
+#define BF_DIGCTL_CTRL_MASTER_SELECT(v)                 (((v) & 0x1f) << 24)
+#define BFM_DIGCTL_CTRL_MASTER_SELECT(v)                BM_DIGCTL_CTRL_MASTER_SELECT
+#define BF_DIGCTL_CTRL_MASTER_SELECT_V(e)               BF_DIGCTL_CTRL_MASTER_SELECT(BV_DIGCTL_CTRL_MASTER_SELECT__##e)
+#define BFM_DIGCTL_CTRL_MASTER_SELECT_V(v)              BM_DIGCTL_CTRL_MASTER_SELECT
+#define BP_DIGCTL_CTRL_USB_TESTMODE                     20
+#define BM_DIGCTL_CTRL_USB_TESTMODE                     0x100000
+#define BF_DIGCTL_CTRL_USB_TESTMODE(v)                  (((v) & 0x1) << 20)
+#define BFM_DIGCTL_CTRL_USB_TESTMODE(v)                 BM_DIGCTL_CTRL_USB_TESTMODE
+#define BF_DIGCTL_CTRL_USB_TESTMODE_V(e)                BF_DIGCTL_CTRL_USB_TESTMODE(BV_DIGCTL_CTRL_USB_TESTMODE__##e)
+#define BFM_DIGCTL_CTRL_USB_TESTMODE_V(v)               BM_DIGCTL_CTRL_USB_TESTMODE
+#define BP_DIGCTL_CTRL_ANALOG_TESTMODE                  19
+#define BM_DIGCTL_CTRL_ANALOG_TESTMODE                  0x80000
+#define BF_DIGCTL_CTRL_ANALOG_TESTMODE(v)               (((v) & 0x1) << 19)
+#define BFM_DIGCTL_CTRL_ANALOG_TESTMODE(v)              BM_DIGCTL_CTRL_ANALOG_TESTMODE
+#define BF_DIGCTL_CTRL_ANALOG_TESTMODE_V(e)             BF_DIGCTL_CTRL_ANALOG_TESTMODE(BV_DIGCTL_CTRL_ANALOG_TESTMODE__##e)
+#define BFM_DIGCTL_CTRL_ANALOG_TESTMODE_V(v)            BM_DIGCTL_CTRL_ANALOG_TESTMODE
+#define BP_DIGCTL_CTRL_DIGITAL_TESTMODE                 18
+#define BM_DIGCTL_CTRL_DIGITAL_TESTMODE                 0x40000
+#define BF_DIGCTL_CTRL_DIGITAL_TESTMODE(v)              (((v) & 0x1) << 18)
+#define BFM_DIGCTL_CTRL_DIGITAL_TESTMODE(v)             BM_DIGCTL_CTRL_DIGITAL_TESTMODE
+#define BF_DIGCTL_CTRL_DIGITAL_TESTMODE_V(e)            BF_DIGCTL_CTRL_DIGITAL_TESTMODE(BV_DIGCTL_CTRL_DIGITAL_TESTMODE__##e)
+#define BFM_DIGCTL_CTRL_DIGITAL_TESTMODE_V(v)           BM_DIGCTL_CTRL_DIGITAL_TESTMODE
+#define BP_DIGCTL_CTRL_UTMI_TESTMODE                    17
+#define BM_DIGCTL_CTRL_UTMI_TESTMODE                    0x20000
+#define BF_DIGCTL_CTRL_UTMI_TESTMODE(v)                 (((v) & 0x1) << 17)
+#define BFM_DIGCTL_CTRL_UTMI_TESTMODE(v)                BM_DIGCTL_CTRL_UTMI_TESTMODE
+#define BF_DIGCTL_CTRL_UTMI_TESTMODE_V(e)               BF_DIGCTL_CTRL_UTMI_TESTMODE(BV_DIGCTL_CTRL_UTMI_TESTMODE__##e)
+#define BFM_DIGCTL_CTRL_UTMI_TESTMODE_V(v)              BM_DIGCTL_CTRL_UTMI_TESTMODE
+#define BP_DIGCTL_CTRL_UART_LOOPBACK                    16
+#define BM_DIGCTL_CTRL_UART_LOOPBACK                    0x10000
+#define BV_DIGCTL_CTRL_UART_LOOPBACK__NORMAL            0x0
+#define BV_DIGCTL_CTRL_UART_LOOPBACK__LOOPIT            0x1
+#define BF_DIGCTL_CTRL_UART_LOOPBACK(v)                 (((v) & 0x1) << 16)
+#define BFM_DIGCTL_CTRL_UART_LOOPBACK(v)                BM_DIGCTL_CTRL_UART_LOOPBACK
+#define BF_DIGCTL_CTRL_UART_LOOPBACK_V(e)               BF_DIGCTL_CTRL_UART_LOOPBACK(BV_DIGCTL_CTRL_UART_LOOPBACK__##e)
+#define BFM_DIGCTL_CTRL_UART_LOOPBACK_V(v)              BM_DIGCTL_CTRL_UART_LOOPBACK
+#define BP_DIGCTL_CTRL_DEBUG_DISABLE                    3
+#define BM_DIGCTL_CTRL_DEBUG_DISABLE                    0x8
+#define BF_DIGCTL_CTRL_DEBUG_DISABLE(v)                 (((v) & 0x1) << 3)
+#define BFM_DIGCTL_CTRL_DEBUG_DISABLE(v)                BM_DIGCTL_CTRL_DEBUG_DISABLE
+#define BF_DIGCTL_CTRL_DEBUG_DISABLE_V(e)               BF_DIGCTL_CTRL_DEBUG_DISABLE(BV_DIGCTL_CTRL_DEBUG_DISABLE__##e)
+#define BFM_DIGCTL_CTRL_DEBUG_DISABLE_V(v)              BM_DIGCTL_CTRL_DEBUG_DISABLE
+#define BP_DIGCTL_CTRL_USB_CLKGATE                      2
+#define BM_DIGCTL_CTRL_USB_CLKGATE                      0x4
+#define BV_DIGCTL_CTRL_USB_CLKGATE__RUN                 0x0
+#define BV_DIGCTL_CTRL_USB_CLKGATE__NO_CLKS             0x1
+#define BF_DIGCTL_CTRL_USB_CLKGATE(v)                   (((v) & 0x1) << 2)
+#define BFM_DIGCTL_CTRL_USB_CLKGATE(v)                  BM_DIGCTL_CTRL_USB_CLKGATE
+#define BF_DIGCTL_CTRL_USB_CLKGATE_V(e)                 BF_DIGCTL_CTRL_USB_CLKGATE(BV_DIGCTL_CTRL_USB_CLKGATE__##e)
+#define BFM_DIGCTL_CTRL_USB_CLKGATE_V(v)                BM_DIGCTL_CTRL_USB_CLKGATE
+#define BP_DIGCTL_CTRL_JTAG_SHIELD                      1
+#define BM_DIGCTL_CTRL_JTAG_SHIELD                      0x2
+#define BV_DIGCTL_CTRL_JTAG_SHIELD__NORMAL              0x0
+#define BV_DIGCTL_CTRL_JTAG_SHIELD__SHIELDS_UP          0x1
+#define BF_DIGCTL_CTRL_JTAG_SHIELD(v)                   (((v) & 0x1) << 1)
+#define BFM_DIGCTL_CTRL_JTAG_SHIELD(v)                  BM_DIGCTL_CTRL_JTAG_SHIELD
+#define BF_DIGCTL_CTRL_JTAG_SHIELD_V(e)                 BF_DIGCTL_CTRL_JTAG_SHIELD(BV_DIGCTL_CTRL_JTAG_SHIELD__##e)
+#define BFM_DIGCTL_CTRL_JTAG_SHIELD_V(v)                BM_DIGCTL_CTRL_JTAG_SHIELD
+#define BP_DIGCTL_CTRL_PACKAGE_SENSE_ENABLE             0
+#define BM_DIGCTL_CTRL_PACKAGE_SENSE_ENABLE             0x1
+#define BV_DIGCTL_CTRL_PACKAGE_SENSE_ENABLE__DISABLE    0x0
+#define BV_DIGCTL_CTRL_PACKAGE_SENSE_ENABLE__ENABLE     0x1
+#define BF_DIGCTL_CTRL_PACKAGE_SENSE_ENABLE(v)          (((v) & 0x1) << 0)
+#define BFM_DIGCTL_CTRL_PACKAGE_SENSE_ENABLE(v)         BM_DIGCTL_CTRL_PACKAGE_SENSE_ENABLE
+#define BF_DIGCTL_CTRL_PACKAGE_SENSE_ENABLE_V(e)        BF_DIGCTL_CTRL_PACKAGE_SENSE_ENABLE(BV_DIGCTL_CTRL_PACKAGE_SENSE_ENABLE__##e)
+#define BFM_DIGCTL_CTRL_PACKAGE_SENSE_ENABLE_V(v)       BM_DIGCTL_CTRL_PACKAGE_SENSE_ENABLE
+
+#define HW_DIGCTL_STATUS                            HW(DIGCTL_STATUS)
+#define HWA_DIGCTL_STATUS                           (0x8001c000 + 0x10)
+#define HWT_DIGCTL_STATUS                           HWIO_32_RW
+#define HWN_DIGCTL_STATUS                           DIGCTL_STATUS
+#define HWI_DIGCTL_STATUS                           
+#define BP_DIGCTL_STATUS_ROM_KEYS_PRESENT           31
+#define BM_DIGCTL_STATUS_ROM_KEYS_PRESENT           0x80000000
+#define BF_DIGCTL_STATUS_ROM_KEYS_PRESENT(v)        (((v) & 0x1) << 31)
+#define BFM_DIGCTL_STATUS_ROM_KEYS_PRESENT(v)       BM_DIGCTL_STATUS_ROM_KEYS_PRESENT
+#define BF_DIGCTL_STATUS_ROM_KEYS_PRESENT_V(e)      BF_DIGCTL_STATUS_ROM_KEYS_PRESENT(BV_DIGCTL_STATUS_ROM_KEYS_PRESENT__##e)
+#define BFM_DIGCTL_STATUS_ROM_KEYS_PRESENT_V(v)     BM_DIGCTL_STATUS_ROM_KEYS_PRESENT
+#define BP_DIGCTL_STATUS_JTAG_SHIELD_DEFAULT        6
+#define BM_DIGCTL_STATUS_JTAG_SHIELD_DEFAULT        0x40
+#define BF_DIGCTL_STATUS_JTAG_SHIELD_DEFAULT(v)     (((v) & 0x1) << 6)
+#define BFM_DIGCTL_STATUS_JTAG_SHIELD_DEFAULT(v)    BM_DIGCTL_STATUS_JTAG_SHIELD_DEFAULT
+#define BF_DIGCTL_STATUS_JTAG_SHIELD_DEFAULT_V(e)   BF_DIGCTL_STATUS_JTAG_SHIELD_DEFAULT(BV_DIGCTL_STATUS_JTAG_SHIELD_DEFAULT__##e)
+#define BFM_DIGCTL_STATUS_JTAG_SHIELD_DEFAULT_V(v)  BM_DIGCTL_STATUS_JTAG_SHIELD_DEFAULT
+#define BP_DIGCTL_STATUS_ROM_SHIELDED               5
+#define BM_DIGCTL_STATUS_ROM_SHIELDED               0x20
+#define BF_DIGCTL_STATUS_ROM_SHIELDED(v)            (((v) & 0x1) << 5)
+#define BFM_DIGCTL_STATUS_ROM_SHIELDED(v)           BM_DIGCTL_STATUS_ROM_SHIELDED
+#define BF_DIGCTL_STATUS_ROM_SHIELDED_V(e)          BF_DIGCTL_STATUS_ROM_SHIELDED(BV_DIGCTL_STATUS_ROM_SHIELDED__##e)
+#define BFM_DIGCTL_STATUS_ROM_SHIELDED_V(v)         BM_DIGCTL_STATUS_ROM_SHIELDED
+#define BP_DIGCTL_STATUS_JTAG_IN_USE                4
+#define BM_DIGCTL_STATUS_JTAG_IN_USE                0x10
+#define BF_DIGCTL_STATUS_JTAG_IN_USE(v)             (((v) & 0x1) << 4)
+#define BFM_DIGCTL_STATUS_JTAG_IN_USE(v)            BM_DIGCTL_STATUS_JTAG_IN_USE
+#define BF_DIGCTL_STATUS_JTAG_IN_USE_V(e)           BF_DIGCTL_STATUS_JTAG_IN_USE(BV_DIGCTL_STATUS_JTAG_IN_USE__##e)
+#define BFM_DIGCTL_STATUS_JTAG_IN_USE_V(v)          BM_DIGCTL_STATUS_JTAG_IN_USE
+#define BP_DIGCTL_STATUS_PSWITCH                    2
+#define BM_DIGCTL_STATUS_PSWITCH                    0xc
+#define BF_DIGCTL_STATUS_PSWITCH(v)                 (((v) & 0x3) << 2)
+#define BFM_DIGCTL_STATUS_PSWITCH(v)                BM_DIGCTL_STATUS_PSWITCH
+#define BF_DIGCTL_STATUS_PSWITCH_V(e)               BF_DIGCTL_STATUS_PSWITCH(BV_DIGCTL_STATUS_PSWITCH__##e)
+#define BFM_DIGCTL_STATUS_PSWITCH_V(v)              BM_DIGCTL_STATUS_PSWITCH
+#define BP_DIGCTL_STATUS_PACKAGE_TYPE               1
+#define BM_DIGCTL_STATUS_PACKAGE_TYPE               0x2
+#define BF_DIGCTL_STATUS_PACKAGE_TYPE(v)            (((v) & 0x1) << 1)
+#define BFM_DIGCTL_STATUS_PACKAGE_TYPE(v)           BM_DIGCTL_STATUS_PACKAGE_TYPE
+#define BF_DIGCTL_STATUS_PACKAGE_TYPE_V(e)          BF_DIGCTL_STATUS_PACKAGE_TYPE(BV_DIGCTL_STATUS_PACKAGE_TYPE__##e)
+#define BFM_DIGCTL_STATUS_PACKAGE_TYPE_V(v)         BM_DIGCTL_STATUS_PACKAGE_TYPE
+#define BP_DIGCTL_STATUS_WRITTEN                    0
+#define BM_DIGCTL_STATUS_WRITTEN                    0x1
+#define BF_DIGCTL_STATUS_WRITTEN(v)                 (((v) & 0x1) << 0)
+#define BFM_DIGCTL_STATUS_WRITTEN(v)                BM_DIGCTL_STATUS_WRITTEN
+#define BF_DIGCTL_STATUS_WRITTEN_V(e)               BF_DIGCTL_STATUS_WRITTEN(BV_DIGCTL_STATUS_WRITTEN__##e)
+#define BFM_DIGCTL_STATUS_WRITTEN_V(v)              BM_DIGCTL_STATUS_WRITTEN
+
+#define HW_DIGCTL_HCLKCOUNT             HW(DIGCTL_HCLKCOUNT)
+#define HWA_DIGCTL_HCLKCOUNT            (0x8001c000 + 0x20)
+#define HWT_DIGCTL_HCLKCOUNT            HWIO_32_RW
+#define HWN_DIGCTL_HCLKCOUNT            DIGCTL_HCLKCOUNT
+#define HWI_DIGCTL_HCLKCOUNT            
+#define BP_DIGCTL_HCLKCOUNT_COUNT       0
+#define BM_DIGCTL_HCLKCOUNT_COUNT       0xffffffff
+#define BF_DIGCTL_HCLKCOUNT_COUNT(v)    (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_HCLKCOUNT_COUNT(v)   BM_DIGCTL_HCLKCOUNT_COUNT
+#define BF_DIGCTL_HCLKCOUNT_COUNT_V(e)  BF_DIGCTL_HCLKCOUNT_COUNT(BV_DIGCTL_HCLKCOUNT_COUNT__##e)
+#define BFM_DIGCTL_HCLKCOUNT_COUNT_V(v) BM_DIGCTL_HCLKCOUNT_COUNT
+
+#define HW_DIGCTL_RAMCTRL                           HW(DIGCTL_RAMCTRL)
+#define HWA_DIGCTL_RAMCTRL                          (0x8001c000 + 0x30)
+#define HWT_DIGCTL_RAMCTRL                          HWIO_32_RW
+#define HWN_DIGCTL_RAMCTRL                          DIGCTL_RAMCTRL
+#define HWI_DIGCTL_RAMCTRL                          
+#define HW_DIGCTL_RAMCTRL_SET                       HW(DIGCTL_RAMCTRL_SET)
+#define HWA_DIGCTL_RAMCTRL_SET                      (HWA_DIGCTL_RAMCTRL + 0x4)
+#define HWT_DIGCTL_RAMCTRL_SET                      HWIO_32_WO
+#define HWN_DIGCTL_RAMCTRL_SET                      DIGCTL_RAMCTRL
+#define HWI_DIGCTL_RAMCTRL_SET                      
+#define HW_DIGCTL_RAMCTRL_CLR                       HW(DIGCTL_RAMCTRL_CLR)
+#define HWA_DIGCTL_RAMCTRL_CLR                      (HWA_DIGCTL_RAMCTRL + 0x8)
+#define HWT_DIGCTL_RAMCTRL_CLR                      HWIO_32_WO
+#define HWN_DIGCTL_RAMCTRL_CLR                      DIGCTL_RAMCTRL
+#define HWI_DIGCTL_RAMCTRL_CLR                      
+#define HW_DIGCTL_RAMCTRL_TOG                       HW(DIGCTL_RAMCTRL_TOG)
+#define HWA_DIGCTL_RAMCTRL_TOG                      (HWA_DIGCTL_RAMCTRL + 0xc)
+#define HWT_DIGCTL_RAMCTRL_TOG                      HWIO_32_WO
+#define HWN_DIGCTL_RAMCTRL_TOG                      DIGCTL_RAMCTRL
+#define HWI_DIGCTL_RAMCTRL_TOG                      
+#define BP_DIGCTL_RAMCTRL_TEST_MARGIN               28
+#define BM_DIGCTL_RAMCTRL_TEST_MARGIN               0x70000000
+#define BV_DIGCTL_RAMCTRL_TEST_MARGIN__NORMAL       0x0
+#define BV_DIGCTL_RAMCTRL_TEST_MARGIN__LEVEL1       0x1
+#define BV_DIGCTL_RAMCTRL_TEST_MARGIN__LEVEL2       0x2
+#define BV_DIGCTL_RAMCTRL_TEST_MARGIN__LEVEL3       0x3
+#define BV_DIGCTL_RAMCTRL_TEST_MARGIN__LEVEL4       0x4
+#define BV_DIGCTL_RAMCTRL_TEST_MARGIN__LEVEL5       0x5
+#define BV_DIGCTL_RAMCTRL_TEST_MARGIN__LEVEL6       0x6
+#define BV_DIGCTL_RAMCTRL_TEST_MARGIN__LEVEL7       0x7
+#define BF_DIGCTL_RAMCTRL_TEST_MARGIN(v)            (((v) & 0x7) << 28)
+#define BFM_DIGCTL_RAMCTRL_TEST_MARGIN(v)           BM_DIGCTL_RAMCTRL_TEST_MARGIN
+#define BF_DIGCTL_RAMCTRL_TEST_MARGIN_V(e)          BF_DIGCTL_RAMCTRL_TEST_MARGIN(BV_DIGCTL_RAMCTRL_TEST_MARGIN__##e)
+#define BFM_DIGCTL_RAMCTRL_TEST_MARGIN_V(v)         BM_DIGCTL_RAMCTRL_TEST_MARGIN
+#define BP_DIGCTL_RAMCTRL_PWDN_BANKS                24
+#define BM_DIGCTL_RAMCTRL_PWDN_BANKS                0xf000000
+#define BV_DIGCTL_RAMCTRL_PWDN_BANKS__PWDN_BANK3    0x8
+#define BV_DIGCTL_RAMCTRL_PWDN_BANKS__PWDN_BANK2    0x4
+#define BV_DIGCTL_RAMCTRL_PWDN_BANKS__PWDN_BANK1    0x2
+#define BV_DIGCTL_RAMCTRL_PWDN_BANKS__PWDN_BANK0    0x1
+#define BF_DIGCTL_RAMCTRL_PWDN_BANKS(v)             (((v) & 0xf) << 24)
+#define BFM_DIGCTL_RAMCTRL_PWDN_BANKS(v)            BM_DIGCTL_RAMCTRL_PWDN_BANKS
+#define BF_DIGCTL_RAMCTRL_PWDN_BANKS_V(e)           BF_DIGCTL_RAMCTRL_PWDN_BANKS(BV_DIGCTL_RAMCTRL_PWDN_BANKS__##e)
+#define BFM_DIGCTL_RAMCTRL_PWDN_BANKS_V(v)          BM_DIGCTL_RAMCTRL_PWDN_BANKS
+#define BP_DIGCTL_RAMCTRL_TEMP_SENSOR               20
+#define BM_DIGCTL_RAMCTRL_TEMP_SENSOR               0x700000
+#define BF_DIGCTL_RAMCTRL_TEMP_SENSOR(v)            (((v) & 0x7) << 20)
+#define BFM_DIGCTL_RAMCTRL_TEMP_SENSOR(v)           BM_DIGCTL_RAMCTRL_TEMP_SENSOR
+#define BF_DIGCTL_RAMCTRL_TEMP_SENSOR_V(e)          BF_DIGCTL_RAMCTRL_TEMP_SENSOR(BV_DIGCTL_RAMCTRL_TEMP_SENSOR__##e)
+#define BFM_DIGCTL_RAMCTRL_TEMP_SENSOR_V(v)         BM_DIGCTL_RAMCTRL_TEMP_SENSOR
+#define BP_DIGCTL_RAMCTRL_TEST_TEMP_COMP            16
+#define BM_DIGCTL_RAMCTRL_TEST_TEMP_COMP            0x70000
+#define BV_DIGCTL_RAMCTRL_TEST_TEMP_COMP__LOW_TEMP  0x1
+#define BV_DIGCTL_RAMCTRL_TEST_TEMP_COMP__RANGE_A   0x2
+#define BV_DIGCTL_RAMCTRL_TEST_TEMP_COMP__RANGE_B   0x3
+#define BV_DIGCTL_RAMCTRL_TEST_TEMP_COMP__RANGE_C   0x4
+#define BV_DIGCTL_RAMCTRL_TEST_TEMP_COMP__RANGE_D   0x5
+#define BV_DIGCTL_RAMCTRL_TEST_TEMP_COMP__RANGE_E   0x6
+#define BV_DIGCTL_RAMCTRL_TEST_TEMP_COMP__RANGE_F   0x7
+#define BF_DIGCTL_RAMCTRL_TEST_TEMP_COMP(v)         (((v) & 0x7) << 16)
+#define BFM_DIGCTL_RAMCTRL_TEST_TEMP_COMP(v)        BM_DIGCTL_RAMCTRL_TEST_TEMP_COMP
+#define BF_DIGCTL_RAMCTRL_TEST_TEMP_COMP_V(e)       BF_DIGCTL_RAMCTRL_TEST_TEMP_COMP(BV_DIGCTL_RAMCTRL_TEST_TEMP_COMP__##e)
+#define BFM_DIGCTL_RAMCTRL_TEST_TEMP_COMP_V(v)      BM_DIGCTL_RAMCTRL_TEST_TEMP_COMP
+#define BP_DIGCTL_RAMCTRL_SHIFT_COUNT               8
+#define BM_DIGCTL_RAMCTRL_SHIFT_COUNT               0x7f00
+#define BF_DIGCTL_RAMCTRL_SHIFT_COUNT(v)            (((v) & 0x7f) << 8)
+#define BFM_DIGCTL_RAMCTRL_SHIFT_COUNT(v)           BM_DIGCTL_RAMCTRL_SHIFT_COUNT
+#define BF_DIGCTL_RAMCTRL_SHIFT_COUNT_V(e)          BF_DIGCTL_RAMCTRL_SHIFT_COUNT(BV_DIGCTL_RAMCTRL_SHIFT_COUNT__##e)
+#define BFM_DIGCTL_RAMCTRL_SHIFT_COUNT_V(v)         BM_DIGCTL_RAMCTRL_SHIFT_COUNT
+#define BP_DIGCTL_RAMCTRL_FLIP_CLK                  7
+#define BM_DIGCTL_RAMCTRL_FLIP_CLK                  0x80
+#define BV_DIGCTL_RAMCTRL_FLIP_CLK__NORMAL          0x0
+#define BV_DIGCTL_RAMCTRL_FLIP_CLK__INVERT          0x1
+#define BF_DIGCTL_RAMCTRL_FLIP_CLK(v)               (((v) & 0x1) << 7)
+#define BFM_DIGCTL_RAMCTRL_FLIP_CLK(v)              BM_DIGCTL_RAMCTRL_FLIP_CLK
+#define BF_DIGCTL_RAMCTRL_FLIP_CLK_V(e)             BF_DIGCTL_RAMCTRL_FLIP_CLK(BV_DIGCTL_RAMCTRL_FLIP_CLK__##e)
+#define BFM_DIGCTL_RAMCTRL_FLIP_CLK_V(v)            BM_DIGCTL_RAMCTRL_FLIP_CLK
+#define BP_DIGCTL_RAMCTRL_OVER_RIDE_TEMP            3
+#define BM_DIGCTL_RAMCTRL_OVER_RIDE_TEMP            0x8
+#define BV_DIGCTL_RAMCTRL_OVER_RIDE_TEMP__NORMAL    0x0
+#define BV_DIGCTL_RAMCTRL_OVER_RIDE_TEMP__OVER_RIDE 0x1
+#define BF_DIGCTL_RAMCTRL_OVER_RIDE_TEMP(v)         (((v) & 0x1) << 3)
+#define BFM_DIGCTL_RAMCTRL_OVER_RIDE_TEMP(v)        BM_DIGCTL_RAMCTRL_OVER_RIDE_TEMP
+#define BF_DIGCTL_RAMCTRL_OVER_RIDE_TEMP_V(e)       BF_DIGCTL_RAMCTRL_OVER_RIDE_TEMP(BV_DIGCTL_RAMCTRL_OVER_RIDE_TEMP__##e)
+#define BFM_DIGCTL_RAMCTRL_OVER_RIDE_TEMP_V(v)      BM_DIGCTL_RAMCTRL_OVER_RIDE_TEMP
+#define BP_DIGCTL_RAMCTRL_REF_CLK_GATE              2
+#define BM_DIGCTL_RAMCTRL_REF_CLK_GATE              0x4
+#define BV_DIGCTL_RAMCTRL_REF_CLK_GATE__NORMAL      0x0
+#define BV_DIGCTL_RAMCTRL_REF_CLK_GATE__OFF         0x1
+#define BF_DIGCTL_RAMCTRL_REF_CLK_GATE(v)           (((v) & 0x1) << 2)
+#define BFM_DIGCTL_RAMCTRL_REF_CLK_GATE(v)          BM_DIGCTL_RAMCTRL_REF_CLK_GATE
+#define BF_DIGCTL_RAMCTRL_REF_CLK_GATE_V(e)         BF_DIGCTL_RAMCTRL_REF_CLK_GATE(BV_DIGCTL_RAMCTRL_REF_CLK_GATE__##e)
+#define BFM_DIGCTL_RAMCTRL_REF_CLK_GATE_V(v)        BM_DIGCTL_RAMCTRL_REF_CLK_GATE
+#define BP_DIGCTL_RAMCTRL_REPAIR_STATUS             1
+#define BM_DIGCTL_RAMCTRL_REPAIR_STATUS             0x2
+#define BV_DIGCTL_RAMCTRL_REPAIR_STATUS__IDLE       0x0
+#define BV_DIGCTL_RAMCTRL_REPAIR_STATUS__BUSY       0x1
+#define BF_DIGCTL_RAMCTRL_REPAIR_STATUS(v)          (((v) & 0x1) << 1)
+#define BFM_DIGCTL_RAMCTRL_REPAIR_STATUS(v)         BM_DIGCTL_RAMCTRL_REPAIR_STATUS
+#define BF_DIGCTL_RAMCTRL_REPAIR_STATUS_V(e)        BF_DIGCTL_RAMCTRL_REPAIR_STATUS(BV_DIGCTL_RAMCTRL_REPAIR_STATUS__##e)
+#define BFM_DIGCTL_RAMCTRL_REPAIR_STATUS_V(v)       BM_DIGCTL_RAMCTRL_REPAIR_STATUS
+#define BP_DIGCTL_RAMCTRL_REPAIR_TRANSMIT           0
+#define BM_DIGCTL_RAMCTRL_REPAIR_TRANSMIT           0x1
+#define BV_DIGCTL_RAMCTRL_REPAIR_TRANSMIT__IDLE     0x0
+#define BV_DIGCTL_RAMCTRL_REPAIR_TRANSMIT__SEND     0x1
+#define BF_DIGCTL_RAMCTRL_REPAIR_TRANSMIT(v)        (((v) & 0x1) << 0)
+#define BFM_DIGCTL_RAMCTRL_REPAIR_TRANSMIT(v)       BM_DIGCTL_RAMCTRL_REPAIR_TRANSMIT
+#define BF_DIGCTL_RAMCTRL_REPAIR_TRANSMIT_V(e)      BF_DIGCTL_RAMCTRL_REPAIR_TRANSMIT(BV_DIGCTL_RAMCTRL_REPAIR_TRANSMIT__##e)
+#define BFM_DIGCTL_RAMCTRL_REPAIR_TRANSMIT_V(v)     BM_DIGCTL_RAMCTRL_REPAIR_TRANSMIT
+
+#define HW_DIGCTL_RAMREPAIR0                HW(DIGCTL_RAMREPAIR0)
+#define HWA_DIGCTL_RAMREPAIR0               (0x8001c000 + 0x40)
+#define HWT_DIGCTL_RAMREPAIR0               HWIO_32_RW
+#define HWN_DIGCTL_RAMREPAIR0               DIGCTL_RAMREPAIR0
+#define HWI_DIGCTL_RAMREPAIR0               
+#define HW_DIGCTL_RAMREPAIR0_SET            HW(DIGCTL_RAMREPAIR0_SET)
+#define HWA_DIGCTL_RAMREPAIR0_SET           (HWA_DIGCTL_RAMREPAIR0 + 0x4)
+#define HWT_DIGCTL_RAMREPAIR0_SET           HWIO_32_WO
+#define HWN_DIGCTL_RAMREPAIR0_SET           DIGCTL_RAMREPAIR0
+#define HWI_DIGCTL_RAMREPAIR0_SET           
+#define HW_DIGCTL_RAMREPAIR0_CLR            HW(DIGCTL_RAMREPAIR0_CLR)
+#define HWA_DIGCTL_RAMREPAIR0_CLR           (HWA_DIGCTL_RAMREPAIR0 + 0x8)
+#define HWT_DIGCTL_RAMREPAIR0_CLR           HWIO_32_WO
+#define HWN_DIGCTL_RAMREPAIR0_CLR           DIGCTL_RAMREPAIR0
+#define HWI_DIGCTL_RAMREPAIR0_CLR           
+#define HW_DIGCTL_RAMREPAIR0_TOG            HW(DIGCTL_RAMREPAIR0_TOG)
+#define HWA_DIGCTL_RAMREPAIR0_TOG           (HWA_DIGCTL_RAMREPAIR0 + 0xc)
+#define HWT_DIGCTL_RAMREPAIR0_TOG           HWIO_32_WO
+#define HWN_DIGCTL_RAMREPAIR0_TOG           DIGCTL_RAMREPAIR0
+#define HWI_DIGCTL_RAMREPAIR0_TOG           
+#define BP_DIGCTL_RAMREPAIR0_EFUSE3         24
+#define BM_DIGCTL_RAMREPAIR0_EFUSE3         0x7f000000
+#define BF_DIGCTL_RAMREPAIR0_EFUSE3(v)      (((v) & 0x7f) << 24)
+#define BFM_DIGCTL_RAMREPAIR0_EFUSE3(v)     BM_DIGCTL_RAMREPAIR0_EFUSE3
+#define BF_DIGCTL_RAMREPAIR0_EFUSE3_V(e)    BF_DIGCTL_RAMREPAIR0_EFUSE3(BV_DIGCTL_RAMREPAIR0_EFUSE3__##e)
+#define BFM_DIGCTL_RAMREPAIR0_EFUSE3_V(v)   BM_DIGCTL_RAMREPAIR0_EFUSE3
+#define BP_DIGCTL_RAMREPAIR0_EFUSE2         16
+#define BM_DIGCTL_RAMREPAIR0_EFUSE2         0x7f0000
+#define BF_DIGCTL_RAMREPAIR0_EFUSE2(v)      (((v) & 0x7f) << 16)
+#define BFM_DIGCTL_RAMREPAIR0_EFUSE2(v)     BM_DIGCTL_RAMREPAIR0_EFUSE2
+#define BF_DIGCTL_RAMREPAIR0_EFUSE2_V(e)    BF_DIGCTL_RAMREPAIR0_EFUSE2(BV_DIGCTL_RAMREPAIR0_EFUSE2__##e)
+#define BFM_DIGCTL_RAMREPAIR0_EFUSE2_V(v)   BM_DIGCTL_RAMREPAIR0_EFUSE2
+#define BP_DIGCTL_RAMREPAIR0_EFUSE1         8
+#define BM_DIGCTL_RAMREPAIR0_EFUSE1         0x7f00
+#define BF_DIGCTL_RAMREPAIR0_EFUSE1(v)      (((v) & 0x7f) << 8)
+#define BFM_DIGCTL_RAMREPAIR0_EFUSE1(v)     BM_DIGCTL_RAMREPAIR0_EFUSE1
+#define BF_DIGCTL_RAMREPAIR0_EFUSE1_V(e)    BF_DIGCTL_RAMREPAIR0_EFUSE1(BV_DIGCTL_RAMREPAIR0_EFUSE1__##e)
+#define BFM_DIGCTL_RAMREPAIR0_EFUSE1_V(v)   BM_DIGCTL_RAMREPAIR0_EFUSE1
+#define BP_DIGCTL_RAMREPAIR0_EFUSE0         0
+#define BM_DIGCTL_RAMREPAIR0_EFUSE0         0x7f
+#define BF_DIGCTL_RAMREPAIR0_EFUSE0(v)      (((v) & 0x7f) << 0)
+#define BFM_DIGCTL_RAMREPAIR0_EFUSE0(v)     BM_DIGCTL_RAMREPAIR0_EFUSE0
+#define BF_DIGCTL_RAMREPAIR0_EFUSE0_V(e)    BF_DIGCTL_RAMREPAIR0_EFUSE0(BV_DIGCTL_RAMREPAIR0_EFUSE0__##e)
+#define BFM_DIGCTL_RAMREPAIR0_EFUSE0_V(v)   BM_DIGCTL_RAMREPAIR0_EFUSE0
+
+#define HW_DIGCTL_RAMREPAIR1                HW(DIGCTL_RAMREPAIR1)
+#define HWA_DIGCTL_RAMREPAIR1               (0x8001c000 + 0x50)
+#define HWT_DIGCTL_RAMREPAIR1               HWIO_32_RW
+#define HWN_DIGCTL_RAMREPAIR1               DIGCTL_RAMREPAIR1
+#define HWI_DIGCTL_RAMREPAIR1               
+#define HW_DIGCTL_RAMREPAIR1_SET            HW(DIGCTL_RAMREPAIR1_SET)
+#define HWA_DIGCTL_RAMREPAIR1_SET           (HWA_DIGCTL_RAMREPAIR1 + 0x4)
+#define HWT_DIGCTL_RAMREPAIR1_SET           HWIO_32_WO
+#define HWN_DIGCTL_RAMREPAIR1_SET           DIGCTL_RAMREPAIR1
+#define HWI_DIGCTL_RAMREPAIR1_SET           
+#define HW_DIGCTL_RAMREPAIR1_CLR            HW(DIGCTL_RAMREPAIR1_CLR)
+#define HWA_DIGCTL_RAMREPAIR1_CLR           (HWA_DIGCTL_RAMREPAIR1 + 0x8)
+#define HWT_DIGCTL_RAMREPAIR1_CLR           HWIO_32_WO
+#define HWN_DIGCTL_RAMREPAIR1_CLR           DIGCTL_RAMREPAIR1
+#define HWI_DIGCTL_RAMREPAIR1_CLR           
+#define HW_DIGCTL_RAMREPAIR1_TOG            HW(DIGCTL_RAMREPAIR1_TOG)
+#define HWA_DIGCTL_RAMREPAIR1_TOG           (HWA_DIGCTL_RAMREPAIR1 + 0xc)
+#define HWT_DIGCTL_RAMREPAIR1_TOG           HWIO_32_WO
+#define HWN_DIGCTL_RAMREPAIR1_TOG           DIGCTL_RAMREPAIR1
+#define HWI_DIGCTL_RAMREPAIR1_TOG           
+#define BP_DIGCTL_RAMREPAIR1_EFUSE3         24
+#define BM_DIGCTL_RAMREPAIR1_EFUSE3         0x7f000000
+#define BF_DIGCTL_RAMREPAIR1_EFUSE3(v)      (((v) & 0x7f) << 24)
+#define BFM_DIGCTL_RAMREPAIR1_EFUSE3(v)     BM_DIGCTL_RAMREPAIR1_EFUSE3
+#define BF_DIGCTL_RAMREPAIR1_EFUSE3_V(e)    BF_DIGCTL_RAMREPAIR1_EFUSE3(BV_DIGCTL_RAMREPAIR1_EFUSE3__##e)
+#define BFM_DIGCTL_RAMREPAIR1_EFUSE3_V(v)   BM_DIGCTL_RAMREPAIR1_EFUSE3
+#define BP_DIGCTL_RAMREPAIR1_EFUSE2         16
+#define BM_DIGCTL_RAMREPAIR1_EFUSE2         0x7f0000
+#define BF_DIGCTL_RAMREPAIR1_EFUSE2(v)      (((v) & 0x7f) << 16)
+#define BFM_DIGCTL_RAMREPAIR1_EFUSE2(v)     BM_DIGCTL_RAMREPAIR1_EFUSE2
+#define BF_DIGCTL_RAMREPAIR1_EFUSE2_V(e)    BF_DIGCTL_RAMREPAIR1_EFUSE2(BV_DIGCTL_RAMREPAIR1_EFUSE2__##e)
+#define BFM_DIGCTL_RAMREPAIR1_EFUSE2_V(v)   BM_DIGCTL_RAMREPAIR1_EFUSE2
+#define BP_DIGCTL_RAMREPAIR1_EFUSE1         8
+#define BM_DIGCTL_RAMREPAIR1_EFUSE1         0x7f00
+#define BF_DIGCTL_RAMREPAIR1_EFUSE1(v)      (((v) & 0x7f) << 8)
+#define BFM_DIGCTL_RAMREPAIR1_EFUSE1(v)     BM_DIGCTL_RAMREPAIR1_EFUSE1
+#define BF_DIGCTL_RAMREPAIR1_EFUSE1_V(e)    BF_DIGCTL_RAMREPAIR1_EFUSE1(BV_DIGCTL_RAMREPAIR1_EFUSE1__##e)
+#define BFM_DIGCTL_RAMREPAIR1_EFUSE1_V(v)   BM_DIGCTL_RAMREPAIR1_EFUSE1
+#define BP_DIGCTL_RAMREPAIR1_EFUSE0         0
+#define BM_DIGCTL_RAMREPAIR1_EFUSE0         0x7f
+#define BF_DIGCTL_RAMREPAIR1_EFUSE0(v)      (((v) & 0x7f) << 0)
+#define BFM_DIGCTL_RAMREPAIR1_EFUSE0(v)     BM_DIGCTL_RAMREPAIR1_EFUSE0
+#define BF_DIGCTL_RAMREPAIR1_EFUSE0_V(e)    BF_DIGCTL_RAMREPAIR1_EFUSE0(BV_DIGCTL_RAMREPAIR1_EFUSE0__##e)
+#define BFM_DIGCTL_RAMREPAIR1_EFUSE0_V(v)   BM_DIGCTL_RAMREPAIR1_EFUSE0
+
+#define HW_DIGCTL_WRITEONCE             HW(DIGCTL_WRITEONCE)
+#define HWA_DIGCTL_WRITEONCE            (0x8001c000 + 0x60)
+#define HWT_DIGCTL_WRITEONCE            HWIO_32_RW
+#define HWN_DIGCTL_WRITEONCE            DIGCTL_WRITEONCE
+#define HWI_DIGCTL_WRITEONCE            
+#define BP_DIGCTL_WRITEONCE_BITS        0
+#define BM_DIGCTL_WRITEONCE_BITS        0xffffffff
+#define BF_DIGCTL_WRITEONCE_BITS(v)     (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_WRITEONCE_BITS(v)    BM_DIGCTL_WRITEONCE_BITS
+#define BF_DIGCTL_WRITEONCE_BITS_V(e)   BF_DIGCTL_WRITEONCE_BITS(BV_DIGCTL_WRITEONCE_BITS__##e)
+#define BFM_DIGCTL_WRITEONCE_BITS_V(v)  BM_DIGCTL_WRITEONCE_BITS
+
+#define HW_DIGCTL_AHBCYCLES             HW(DIGCTL_AHBCYCLES)
+#define HWA_DIGCTL_AHBCYCLES            (0x8001c000 + 0x70)
+#define HWT_DIGCTL_AHBCYCLES            HWIO_32_RW
+#define HWN_DIGCTL_AHBCYCLES            DIGCTL_AHBCYCLES
+#define HWI_DIGCTL_AHBCYCLES            
+#define BP_DIGCTL_AHBCYCLES_COUNT       0
+#define BM_DIGCTL_AHBCYCLES_COUNT       0xffffffff
+#define BF_DIGCTL_AHBCYCLES_COUNT(v)    (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_AHBCYCLES_COUNT(v)   BM_DIGCTL_AHBCYCLES_COUNT
+#define BF_DIGCTL_AHBCYCLES_COUNT_V(e)  BF_DIGCTL_AHBCYCLES_COUNT(BV_DIGCTL_AHBCYCLES_COUNT__##e)
+#define BFM_DIGCTL_AHBCYCLES_COUNT_V(v) BM_DIGCTL_AHBCYCLES_COUNT
+
+#define HW_DIGCTL_AHBSTALLED                HW(DIGCTL_AHBSTALLED)
+#define HWA_DIGCTL_AHBSTALLED               (0x8001c000 + 0x80)
+#define HWT_DIGCTL_AHBSTALLED               HWIO_32_RW
+#define HWN_DIGCTL_AHBSTALLED               DIGCTL_AHBSTALLED
+#define HWI_DIGCTL_AHBSTALLED               
+#define BP_DIGCTL_AHBSTALLED_COUNT          0
+#define BM_DIGCTL_AHBSTALLED_COUNT          0xffffffff
+#define BF_DIGCTL_AHBSTALLED_COUNT(v)       (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_AHBSTALLED_COUNT(v)      BM_DIGCTL_AHBSTALLED_COUNT
+#define BF_DIGCTL_AHBSTALLED_COUNT_V(e)     BF_DIGCTL_AHBSTALLED_COUNT(BV_DIGCTL_AHBSTALLED_COUNT__##e)
+#define BFM_DIGCTL_AHBSTALLED_COUNT_V(v)    BM_DIGCTL_AHBSTALLED_COUNT
+
+#define HW_DIGCTL_ENTROPY               HW(DIGCTL_ENTROPY)
+#define HWA_DIGCTL_ENTROPY              (0x8001c000 + 0x90)
+#define HWT_DIGCTL_ENTROPY              HWIO_32_RW
+#define HWN_DIGCTL_ENTROPY              DIGCTL_ENTROPY
+#define HWI_DIGCTL_ENTROPY              
+#define BP_DIGCTL_ENTROPY_VALUE         0
+#define BM_DIGCTL_ENTROPY_VALUE         0xffffffff
+#define BF_DIGCTL_ENTROPY_VALUE(v)      (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_ENTROPY_VALUE(v)     BM_DIGCTL_ENTROPY_VALUE
+#define BF_DIGCTL_ENTROPY_VALUE_V(e)    BF_DIGCTL_ENTROPY_VALUE(BV_DIGCTL_ENTROPY_VALUE__##e)
+#define BFM_DIGCTL_ENTROPY_VALUE_V(v)   BM_DIGCTL_ENTROPY_VALUE
+
+#define HW_DIGCTL_ROMSHIELD                     HW(DIGCTL_ROMSHIELD)
+#define HWA_DIGCTL_ROMSHIELD                    (0x8001c000 + 0xa0)
+#define HWT_DIGCTL_ROMSHIELD                    HWIO_32_RW
+#define HWN_DIGCTL_ROMSHIELD                    DIGCTL_ROMSHIELD
+#define HWI_DIGCTL_ROMSHIELD                    
+#define BP_DIGCTL_ROMSHIELD_WRITE_ONCE          0
+#define BM_DIGCTL_ROMSHIELD_WRITE_ONCE          0x1
+#define BF_DIGCTL_ROMSHIELD_WRITE_ONCE(v)       (((v) & 0x1) << 0)
+#define BFM_DIGCTL_ROMSHIELD_WRITE_ONCE(v)      BM_DIGCTL_ROMSHIELD_WRITE_ONCE
+#define BF_DIGCTL_ROMSHIELD_WRITE_ONCE_V(e)     BF_DIGCTL_ROMSHIELD_WRITE_ONCE(BV_DIGCTL_ROMSHIELD_WRITE_ONCE__##e)
+#define BFM_DIGCTL_ROMSHIELD_WRITE_ONCE_V(v)    BM_DIGCTL_ROMSHIELD_WRITE_ONCE
+
+#define HW_DIGCTL_MICROSECONDS              HW(DIGCTL_MICROSECONDS)
+#define HWA_DIGCTL_MICROSECONDS             (0x8001c000 + 0xb0)
+#define HWT_DIGCTL_MICROSECONDS             HWIO_32_RW
+#define HWN_DIGCTL_MICROSECONDS             DIGCTL_MICROSECONDS
+#define HWI_DIGCTL_MICROSECONDS             
+#define HW_DIGCTL_MICROSECONDS_SET          HW(DIGCTL_MICROSECONDS_SET)
+#define HWA_DIGCTL_MICROSECONDS_SET         (HWA_DIGCTL_MICROSECONDS + 0x4)
+#define HWT_DIGCTL_MICROSECONDS_SET         HWIO_32_WO
+#define HWN_DIGCTL_MICROSECONDS_SET         DIGCTL_MICROSECONDS
+#define HWI_DIGCTL_MICROSECONDS_SET         
+#define HW_DIGCTL_MICROSECONDS_CLR          HW(DIGCTL_MICROSECONDS_CLR)
+#define HWA_DIGCTL_MICROSECONDS_CLR         (HWA_DIGCTL_MICROSECONDS + 0x8)
+#define HWT_DIGCTL_MICROSECONDS_CLR         HWIO_32_WO
+#define HWN_DIGCTL_MICROSECONDS_CLR         DIGCTL_MICROSECONDS
+#define HWI_DIGCTL_MICROSECONDS_CLR         
+#define HW_DIGCTL_MICROSECONDS_TOG          HW(DIGCTL_MICROSECONDS_TOG)
+#define HWA_DIGCTL_MICROSECONDS_TOG         (HWA_DIGCTL_MICROSECONDS + 0xc)
+#define HWT_DIGCTL_MICROSECONDS_TOG         HWIO_32_WO
+#define HWN_DIGCTL_MICROSECONDS_TOG         DIGCTL_MICROSECONDS
+#define HWI_DIGCTL_MICROSECONDS_TOG         
+#define BP_DIGCTL_MICROSECONDS_VALUE        0
+#define BM_DIGCTL_MICROSECONDS_VALUE        0xffffffff
+#define BF_DIGCTL_MICROSECONDS_VALUE(v)     (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_MICROSECONDS_VALUE(v)    BM_DIGCTL_MICROSECONDS_VALUE
+#define BF_DIGCTL_MICROSECONDS_VALUE_V(e)   BF_DIGCTL_MICROSECONDS_VALUE(BV_DIGCTL_MICROSECONDS_VALUE__##e)
+#define BFM_DIGCTL_MICROSECONDS_VALUE_V(v)  BM_DIGCTL_MICROSECONDS_VALUE
+
+#define HW_DIGCTL_DBGRD                     HW(DIGCTL_DBGRD)
+#define HWA_DIGCTL_DBGRD                    (0x8001c000 + 0xc0)
+#define HWT_DIGCTL_DBGRD                    HWIO_32_RW
+#define HWN_DIGCTL_DBGRD                    DIGCTL_DBGRD
+#define HWI_DIGCTL_DBGRD                    
+#define BP_DIGCTL_DBGRD_COMPLEMENT          0
+#define BM_DIGCTL_DBGRD_COMPLEMENT          0xffffffff
+#define BF_DIGCTL_DBGRD_COMPLEMENT(v)       (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_DBGRD_COMPLEMENT(v)      BM_DIGCTL_DBGRD_COMPLEMENT
+#define BF_DIGCTL_DBGRD_COMPLEMENT_V(e)     BF_DIGCTL_DBGRD_COMPLEMENT(BV_DIGCTL_DBGRD_COMPLEMENT__##e)
+#define BFM_DIGCTL_DBGRD_COMPLEMENT_V(v)    BM_DIGCTL_DBGRD_COMPLEMENT
+
+#define HW_DIGCTL_DBG               HW(DIGCTL_DBG)
+#define HWA_DIGCTL_DBG              (0x8001c000 + 0xd0)
+#define HWT_DIGCTL_DBG              HWIO_32_RW
+#define HWN_DIGCTL_DBG              DIGCTL_DBG
+#define HWI_DIGCTL_DBG              
+#define BP_DIGCTL_DBG_VALUE         0
+#define BM_DIGCTL_DBG_VALUE         0xffffffff
+#define BF_DIGCTL_DBG_VALUE(v)      (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_DBG_VALUE(v)     BM_DIGCTL_DBG_VALUE
+#define BF_DIGCTL_DBG_VALUE_V(e)    BF_DIGCTL_DBG_VALUE(BV_DIGCTL_DBG_VALUE__##e)
+#define BFM_DIGCTL_DBG_VALUE_V(v)   BM_DIGCTL_DBG_VALUE
+
+#define HW_DIGCTL_1TRAM_BIST_CSR                HW(DIGCTL_1TRAM_BIST_CSR)
+#define HWA_DIGCTL_1TRAM_BIST_CSR               (0x8001c000 + 0xe0)
+#define HWT_DIGCTL_1TRAM_BIST_CSR               HWIO_32_RW
+#define HWN_DIGCTL_1TRAM_BIST_CSR               DIGCTL_1TRAM_BIST_CSR
+#define HWI_DIGCTL_1TRAM_BIST_CSR               
+#define HW_DIGCTL_1TRAM_BIST_CSR_SET            HW(DIGCTL_1TRAM_BIST_CSR_SET)
+#define HWA_DIGCTL_1TRAM_BIST_CSR_SET           (HWA_DIGCTL_1TRAM_BIST_CSR + 0x4)
+#define HWT_DIGCTL_1TRAM_BIST_CSR_SET           HWIO_32_WO
+#define HWN_DIGCTL_1TRAM_BIST_CSR_SET           DIGCTL_1TRAM_BIST_CSR
+#define HWI_DIGCTL_1TRAM_BIST_CSR_SET           
+#define HW_DIGCTL_1TRAM_BIST_CSR_CLR            HW(DIGCTL_1TRAM_BIST_CSR_CLR)
+#define HWA_DIGCTL_1TRAM_BIST_CSR_CLR           (HWA_DIGCTL_1TRAM_BIST_CSR + 0x8)
+#define HWT_DIGCTL_1TRAM_BIST_CSR_CLR           HWIO_32_WO
+#define HWN_DIGCTL_1TRAM_BIST_CSR_CLR           DIGCTL_1TRAM_BIST_CSR
+#define HWI_DIGCTL_1TRAM_BIST_CSR_CLR           
+#define HW_DIGCTL_1TRAM_BIST_CSR_TOG            HW(DIGCTL_1TRAM_BIST_CSR_TOG)
+#define HWA_DIGCTL_1TRAM_BIST_CSR_TOG           (HWA_DIGCTL_1TRAM_BIST_CSR + 0xc)
+#define HWT_DIGCTL_1TRAM_BIST_CSR_TOG           HWIO_32_WO
+#define HWN_DIGCTL_1TRAM_BIST_CSR_TOG           DIGCTL_1TRAM_BIST_CSR
+#define HWI_DIGCTL_1TRAM_BIST_CSR_TOG           
+#define BP_DIGCTL_1TRAM_BIST_CSR_FAIL           3
+#define BM_DIGCTL_1TRAM_BIST_CSR_FAIL           0x8
+#define BF_DIGCTL_1TRAM_BIST_CSR_FAIL(v)        (((v) & 0x1) << 3)
+#define BFM_DIGCTL_1TRAM_BIST_CSR_FAIL(v)       BM_DIGCTL_1TRAM_BIST_CSR_FAIL
+#define BF_DIGCTL_1TRAM_BIST_CSR_FAIL_V(e)      BF_DIGCTL_1TRAM_BIST_CSR_FAIL(BV_DIGCTL_1TRAM_BIST_CSR_FAIL__##e)
+#define BFM_DIGCTL_1TRAM_BIST_CSR_FAIL_V(v)     BM_DIGCTL_1TRAM_BIST_CSR_FAIL
+#define BP_DIGCTL_1TRAM_BIST_CSR_PASS           2
+#define BM_DIGCTL_1TRAM_BIST_CSR_PASS           0x4
+#define BF_DIGCTL_1TRAM_BIST_CSR_PASS(v)        (((v) & 0x1) << 2)
+#define BFM_DIGCTL_1TRAM_BIST_CSR_PASS(v)       BM_DIGCTL_1TRAM_BIST_CSR_PASS
+#define BF_DIGCTL_1TRAM_BIST_CSR_PASS_V(e)      BF_DIGCTL_1TRAM_BIST_CSR_PASS(BV_DIGCTL_1TRAM_BIST_CSR_PASS__##e)
+#define BFM_DIGCTL_1TRAM_BIST_CSR_PASS_V(v)     BM_DIGCTL_1TRAM_BIST_CSR_PASS
+#define BP_DIGCTL_1TRAM_BIST_CSR_DONE           1
+#define BM_DIGCTL_1TRAM_BIST_CSR_DONE           0x2
+#define BF_DIGCTL_1TRAM_BIST_CSR_DONE(v)        (((v) & 0x1) << 1)
+#define BFM_DIGCTL_1TRAM_BIST_CSR_DONE(v)       BM_DIGCTL_1TRAM_BIST_CSR_DONE
+#define BF_DIGCTL_1TRAM_BIST_CSR_DONE_V(e)      BF_DIGCTL_1TRAM_BIST_CSR_DONE(BV_DIGCTL_1TRAM_BIST_CSR_DONE__##e)
+#define BFM_DIGCTL_1TRAM_BIST_CSR_DONE_V(v)     BM_DIGCTL_1TRAM_BIST_CSR_DONE
+#define BP_DIGCTL_1TRAM_BIST_CSR_START          0
+#define BM_DIGCTL_1TRAM_BIST_CSR_START          0x1
+#define BF_DIGCTL_1TRAM_BIST_CSR_START(v)       (((v) & 0x1) << 0)
+#define BFM_DIGCTL_1TRAM_BIST_CSR_START(v)      BM_DIGCTL_1TRAM_BIST_CSR_START
+#define BF_DIGCTL_1TRAM_BIST_CSR_START_V(e)     BF_DIGCTL_1TRAM_BIST_CSR_START(BV_DIGCTL_1TRAM_BIST_CSR_START__##e)
+#define BFM_DIGCTL_1TRAM_BIST_CSR_START_V(v)    BM_DIGCTL_1TRAM_BIST_CSR_START
+
+#define HW_DIGCTL_1TRAM_BIST_REPAIR0    HW(DIGCTL_1TRAM_BIST_REPAIR0)
+#define HWA_DIGCTL_1TRAM_BIST_REPAIR0   (0x8001c000 + 0xf0)
+#define HWT_DIGCTL_1TRAM_BIST_REPAIR0   HWIO_32_RW
+#define HWN_DIGCTL_1TRAM_BIST_REPAIR0   DIGCTL_1TRAM_BIST_REPAIR0
+#define HWI_DIGCTL_1TRAM_BIST_REPAIR0   
+
+#define HW_DIGCTL_1TRAM_BIST_REPAIR1    HW(DIGCTL_1TRAM_BIST_REPAIR1)
+#define HWA_DIGCTL_1TRAM_BIST_REPAIR1   (0x8001c000 + 0x100)
+#define HWT_DIGCTL_1TRAM_BIST_REPAIR1   HWIO_32_RW
+#define HWN_DIGCTL_1TRAM_BIST_REPAIR1   DIGCTL_1TRAM_BIST_REPAIR1
+#define HWI_DIGCTL_1TRAM_BIST_REPAIR1   
+
+#define HW_DIGCTL_1TRAM_STATUS0                     HW(DIGCTL_1TRAM_STATUS0)
+#define HWA_DIGCTL_1TRAM_STATUS0                    (0x8001c000 + 0x110)
+#define HWT_DIGCTL_1TRAM_STATUS0                    HWIO_32_RW
+#define HWN_DIGCTL_1TRAM_STATUS0                    DIGCTL_1TRAM_STATUS0
+#define HWI_DIGCTL_1TRAM_STATUS0                    
+#define BP_DIGCTL_1TRAM_STATUS0_FAILDATA00          0
+#define BM_DIGCTL_1TRAM_STATUS0_FAILDATA00          0xffffffff
+#define BF_DIGCTL_1TRAM_STATUS0_FAILDATA00(v)       (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_1TRAM_STATUS0_FAILDATA00(v)      BM_DIGCTL_1TRAM_STATUS0_FAILDATA00
+#define BF_DIGCTL_1TRAM_STATUS0_FAILDATA00_V(e)     BF_DIGCTL_1TRAM_STATUS0_FAILDATA00(BV_DIGCTL_1TRAM_STATUS0_FAILDATA00__##e)
+#define BFM_DIGCTL_1TRAM_STATUS0_FAILDATA00_V(v)    BM_DIGCTL_1TRAM_STATUS0_FAILDATA00
+
+#define HW_DIGCTL_1TRAM_STATUS1                     HW(DIGCTL_1TRAM_STATUS1)
+#define HWA_DIGCTL_1TRAM_STATUS1                    (0x8001c000 + 0x120)
+#define HWT_DIGCTL_1TRAM_STATUS1                    HWIO_32_RW
+#define HWN_DIGCTL_1TRAM_STATUS1                    DIGCTL_1TRAM_STATUS1
+#define HWI_DIGCTL_1TRAM_STATUS1                    
+#define BP_DIGCTL_1TRAM_STATUS1_FAILDATA01          0
+#define BM_DIGCTL_1TRAM_STATUS1_FAILDATA01          0xffffffff
+#define BF_DIGCTL_1TRAM_STATUS1_FAILDATA01(v)       (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_1TRAM_STATUS1_FAILDATA01(v)      BM_DIGCTL_1TRAM_STATUS1_FAILDATA01
+#define BF_DIGCTL_1TRAM_STATUS1_FAILDATA01_V(e)     BF_DIGCTL_1TRAM_STATUS1_FAILDATA01(BV_DIGCTL_1TRAM_STATUS1_FAILDATA01__##e)
+#define BFM_DIGCTL_1TRAM_STATUS1_FAILDATA01_V(v)    BM_DIGCTL_1TRAM_STATUS1_FAILDATA01
+
+#define HW_DIGCTL_1TRAM_STATUS2                     HW(DIGCTL_1TRAM_STATUS2)
+#define HWA_DIGCTL_1TRAM_STATUS2                    (0x8001c000 + 0x130)
+#define HWT_DIGCTL_1TRAM_STATUS2                    HWIO_32_RW
+#define HWN_DIGCTL_1TRAM_STATUS2                    DIGCTL_1TRAM_STATUS2
+#define HWI_DIGCTL_1TRAM_STATUS2                    
+#define BP_DIGCTL_1TRAM_STATUS2_FAILDATA10          0
+#define BM_DIGCTL_1TRAM_STATUS2_FAILDATA10          0xffffffff
+#define BF_DIGCTL_1TRAM_STATUS2_FAILDATA10(v)       (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_1TRAM_STATUS2_FAILDATA10(v)      BM_DIGCTL_1TRAM_STATUS2_FAILDATA10
+#define BF_DIGCTL_1TRAM_STATUS2_FAILDATA10_V(e)     BF_DIGCTL_1TRAM_STATUS2_FAILDATA10(BV_DIGCTL_1TRAM_STATUS2_FAILDATA10__##e)
+#define BFM_DIGCTL_1TRAM_STATUS2_FAILDATA10_V(v)    BM_DIGCTL_1TRAM_STATUS2_FAILDATA10
+
+#define HW_DIGCTL_1TRAM_STATUS3                     HW(DIGCTL_1TRAM_STATUS3)
+#define HWA_DIGCTL_1TRAM_STATUS3                    (0x8001c000 + 0x140)
+#define HWT_DIGCTL_1TRAM_STATUS3                    HWIO_32_RW
+#define HWN_DIGCTL_1TRAM_STATUS3                    DIGCTL_1TRAM_STATUS3
+#define HWI_DIGCTL_1TRAM_STATUS3                    
+#define BP_DIGCTL_1TRAM_STATUS3_FAILDATA11          0
+#define BM_DIGCTL_1TRAM_STATUS3_FAILDATA11          0xffffffff
+#define BF_DIGCTL_1TRAM_STATUS3_FAILDATA11(v)       (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_1TRAM_STATUS3_FAILDATA11(v)      BM_DIGCTL_1TRAM_STATUS3_FAILDATA11
+#define BF_DIGCTL_1TRAM_STATUS3_FAILDATA11_V(e)     BF_DIGCTL_1TRAM_STATUS3_FAILDATA11(BV_DIGCTL_1TRAM_STATUS3_FAILDATA11__##e)
+#define BFM_DIGCTL_1TRAM_STATUS3_FAILDATA11_V(v)    BM_DIGCTL_1TRAM_STATUS3_FAILDATA11
+
+#define HW_DIGCTL_1TRAM_STATUS4                     HW(DIGCTL_1TRAM_STATUS4)
+#define HWA_DIGCTL_1TRAM_STATUS4                    (0x8001c000 + 0x150)
+#define HWT_DIGCTL_1TRAM_STATUS4                    HWIO_32_RW
+#define HWN_DIGCTL_1TRAM_STATUS4                    DIGCTL_1TRAM_STATUS4
+#define HWI_DIGCTL_1TRAM_STATUS4                    
+#define BP_DIGCTL_1TRAM_STATUS4_FAILDATA20          0
+#define BM_DIGCTL_1TRAM_STATUS4_FAILDATA20          0xffffffff
+#define BF_DIGCTL_1TRAM_STATUS4_FAILDATA20(v)       (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_1TRAM_STATUS4_FAILDATA20(v)      BM_DIGCTL_1TRAM_STATUS4_FAILDATA20
+#define BF_DIGCTL_1TRAM_STATUS4_FAILDATA20_V(e)     BF_DIGCTL_1TRAM_STATUS4_FAILDATA20(BV_DIGCTL_1TRAM_STATUS4_FAILDATA20__##e)
+#define BFM_DIGCTL_1TRAM_STATUS4_FAILDATA20_V(v)    BM_DIGCTL_1TRAM_STATUS4_FAILDATA20
+
+#define HW_DIGCTL_1TRAM_STATUS5                     HW(DIGCTL_1TRAM_STATUS5)
+#define HWA_DIGCTL_1TRAM_STATUS5                    (0x8001c000 + 0x160)
+#define HWT_DIGCTL_1TRAM_STATUS5                    HWIO_32_RW
+#define HWN_DIGCTL_1TRAM_STATUS5                    DIGCTL_1TRAM_STATUS5
+#define HWI_DIGCTL_1TRAM_STATUS5                    
+#define BP_DIGCTL_1TRAM_STATUS5_FAILDATA21          0
+#define BM_DIGCTL_1TRAM_STATUS5_FAILDATA21          0xffffffff
+#define BF_DIGCTL_1TRAM_STATUS5_FAILDATA21(v)       (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_1TRAM_STATUS5_FAILDATA21(v)      BM_DIGCTL_1TRAM_STATUS5_FAILDATA21
+#define BF_DIGCTL_1TRAM_STATUS5_FAILDATA21_V(e)     BF_DIGCTL_1TRAM_STATUS5_FAILDATA21(BV_DIGCTL_1TRAM_STATUS5_FAILDATA21__##e)
+#define BFM_DIGCTL_1TRAM_STATUS5_FAILDATA21_V(v)    BM_DIGCTL_1TRAM_STATUS5_FAILDATA21
+
+#define HW_DIGCTL_1TRAM_STATUS6                     HW(DIGCTL_1TRAM_STATUS6)
+#define HWA_DIGCTL_1TRAM_STATUS6                    (0x8001c000 + 0x170)
+#define HWT_DIGCTL_1TRAM_STATUS6                    HWIO_32_RW
+#define HWN_DIGCTL_1TRAM_STATUS6                    DIGCTL_1TRAM_STATUS6
+#define HWI_DIGCTL_1TRAM_STATUS6                    
+#define BP_DIGCTL_1TRAM_STATUS6_FAILDATA30          0
+#define BM_DIGCTL_1TRAM_STATUS6_FAILDATA30          0xffffffff
+#define BF_DIGCTL_1TRAM_STATUS6_FAILDATA30(v)       (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_1TRAM_STATUS6_FAILDATA30(v)      BM_DIGCTL_1TRAM_STATUS6_FAILDATA30
+#define BF_DIGCTL_1TRAM_STATUS6_FAILDATA30_V(e)     BF_DIGCTL_1TRAM_STATUS6_FAILDATA30(BV_DIGCTL_1TRAM_STATUS6_FAILDATA30__##e)
+#define BFM_DIGCTL_1TRAM_STATUS6_FAILDATA30_V(v)    BM_DIGCTL_1TRAM_STATUS6_FAILDATA30
+
+#define HW_DIGCTL_1TRAM_STATUS7                     HW(DIGCTL_1TRAM_STATUS7)
+#define HWA_DIGCTL_1TRAM_STATUS7                    (0x8001c000 + 0x180)
+#define HWT_DIGCTL_1TRAM_STATUS7                    HWIO_32_RW
+#define HWN_DIGCTL_1TRAM_STATUS7                    DIGCTL_1TRAM_STATUS7
+#define HWI_DIGCTL_1TRAM_STATUS7                    
+#define BP_DIGCTL_1TRAM_STATUS7_FAILDATA31          0
+#define BM_DIGCTL_1TRAM_STATUS7_FAILDATA31          0xffffffff
+#define BF_DIGCTL_1TRAM_STATUS7_FAILDATA31(v)       (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_1TRAM_STATUS7_FAILDATA31(v)      BM_DIGCTL_1TRAM_STATUS7_FAILDATA31
+#define BF_DIGCTL_1TRAM_STATUS7_FAILDATA31_V(e)     BF_DIGCTL_1TRAM_STATUS7_FAILDATA31(BV_DIGCTL_1TRAM_STATUS7_FAILDATA31__##e)
+#define BFM_DIGCTL_1TRAM_STATUS7_FAILDATA31_V(v)    BM_DIGCTL_1TRAM_STATUS7_FAILDATA31
+
+#define HW_DIGCTL_1TRAM_STATUS8                     HW(DIGCTL_1TRAM_STATUS8)
+#define HWA_DIGCTL_1TRAM_STATUS8                    (0x8001c000 + 0x190)
+#define HWT_DIGCTL_1TRAM_STATUS8                    HWIO_32_RW
+#define HWN_DIGCTL_1TRAM_STATUS8                    DIGCTL_1TRAM_STATUS8
+#define HWI_DIGCTL_1TRAM_STATUS8                    
+#define BP_DIGCTL_1TRAM_STATUS8_FAILADDR01          16
+#define BM_DIGCTL_1TRAM_STATUS8_FAILADDR01          0xffff0000
+#define BF_DIGCTL_1TRAM_STATUS8_FAILADDR01(v)       (((v) & 0xffff) << 16)
+#define BFM_DIGCTL_1TRAM_STATUS8_FAILADDR01(v)      BM_DIGCTL_1TRAM_STATUS8_FAILADDR01
+#define BF_DIGCTL_1TRAM_STATUS8_FAILADDR01_V(e)     BF_DIGCTL_1TRAM_STATUS8_FAILADDR01(BV_DIGCTL_1TRAM_STATUS8_FAILADDR01__##e)
+#define BFM_DIGCTL_1TRAM_STATUS8_FAILADDR01_V(v)    BM_DIGCTL_1TRAM_STATUS8_FAILADDR01
+#define BP_DIGCTL_1TRAM_STATUS8_FAILADDR00          0
+#define BM_DIGCTL_1TRAM_STATUS8_FAILADDR00          0xffff
+#define BF_DIGCTL_1TRAM_STATUS8_FAILADDR00(v)       (((v) & 0xffff) << 0)
+#define BFM_DIGCTL_1TRAM_STATUS8_FAILADDR00(v)      BM_DIGCTL_1TRAM_STATUS8_FAILADDR00
+#define BF_DIGCTL_1TRAM_STATUS8_FAILADDR00_V(e)     BF_DIGCTL_1TRAM_STATUS8_FAILADDR00(BV_DIGCTL_1TRAM_STATUS8_FAILADDR00__##e)
+#define BFM_DIGCTL_1TRAM_STATUS8_FAILADDR00_V(v)    BM_DIGCTL_1TRAM_STATUS8_FAILADDR00
+
+#define HW_DIGCTL_1TRAM_STATUS9                     HW(DIGCTL_1TRAM_STATUS9)
+#define HWA_DIGCTL_1TRAM_STATUS9                    (0x8001c000 + 0x1a0)
+#define HWT_DIGCTL_1TRAM_STATUS9                    HWIO_32_RW
+#define HWN_DIGCTL_1TRAM_STATUS9                    DIGCTL_1TRAM_STATUS9
+#define HWI_DIGCTL_1TRAM_STATUS9                    
+#define BP_DIGCTL_1TRAM_STATUS9_FAILADDR11          16
+#define BM_DIGCTL_1TRAM_STATUS9_FAILADDR11          0xffff0000
+#define BF_DIGCTL_1TRAM_STATUS9_FAILADDR11(v)       (((v) & 0xffff) << 16)
+#define BFM_DIGCTL_1TRAM_STATUS9_FAILADDR11(v)      BM_DIGCTL_1TRAM_STATUS9_FAILADDR11
+#define BF_DIGCTL_1TRAM_STATUS9_FAILADDR11_V(e)     BF_DIGCTL_1TRAM_STATUS9_FAILADDR11(BV_DIGCTL_1TRAM_STATUS9_FAILADDR11__##e)
+#define BFM_DIGCTL_1TRAM_STATUS9_FAILADDR11_V(v)    BM_DIGCTL_1TRAM_STATUS9_FAILADDR11
+#define BP_DIGCTL_1TRAM_STATUS9_FAILADDR10          0
+#define BM_DIGCTL_1TRAM_STATUS9_FAILADDR10          0xffff
+#define BF_DIGCTL_1TRAM_STATUS9_FAILADDR10(v)       (((v) & 0xffff) << 0)
+#define BFM_DIGCTL_1TRAM_STATUS9_FAILADDR10(v)      BM_DIGCTL_1TRAM_STATUS9_FAILADDR10
+#define BF_DIGCTL_1TRAM_STATUS9_FAILADDR10_V(e)     BF_DIGCTL_1TRAM_STATUS9_FAILADDR10(BV_DIGCTL_1TRAM_STATUS9_FAILADDR10__##e)
+#define BFM_DIGCTL_1TRAM_STATUS9_FAILADDR10_V(v)    BM_DIGCTL_1TRAM_STATUS9_FAILADDR10
+
+#define HW_DIGCTL_1TRAM_STATUS10                    HW(DIGCTL_1TRAM_STATUS10)
+#define HWA_DIGCTL_1TRAM_STATUS10                   (0x8001c000 + 0x1b0)
+#define HWT_DIGCTL_1TRAM_STATUS10                   HWIO_32_RW
+#define HWN_DIGCTL_1TRAM_STATUS10                   DIGCTL_1TRAM_STATUS10
+#define HWI_DIGCTL_1TRAM_STATUS10                   
+#define BP_DIGCTL_1TRAM_STATUS10_FAILADDR21         16
+#define BM_DIGCTL_1TRAM_STATUS10_FAILADDR21         0xffff0000
+#define BF_DIGCTL_1TRAM_STATUS10_FAILADDR21(v)      (((v) & 0xffff) << 16)
+#define BFM_DIGCTL_1TRAM_STATUS10_FAILADDR21(v)     BM_DIGCTL_1TRAM_STATUS10_FAILADDR21
+#define BF_DIGCTL_1TRAM_STATUS10_FAILADDR21_V(e)    BF_DIGCTL_1TRAM_STATUS10_FAILADDR21(BV_DIGCTL_1TRAM_STATUS10_FAILADDR21__##e)
+#define BFM_DIGCTL_1TRAM_STATUS10_FAILADDR21_V(v)   BM_DIGCTL_1TRAM_STATUS10_FAILADDR21
+#define BP_DIGCTL_1TRAM_STATUS10_FAILADDR20         0
+#define BM_DIGCTL_1TRAM_STATUS10_FAILADDR20         0xffff
+#define BF_DIGCTL_1TRAM_STATUS10_FAILADDR20(v)      (((v) & 0xffff) << 0)
+#define BFM_DIGCTL_1TRAM_STATUS10_FAILADDR20(v)     BM_DIGCTL_1TRAM_STATUS10_FAILADDR20
+#define BF_DIGCTL_1TRAM_STATUS10_FAILADDR20_V(e)    BF_DIGCTL_1TRAM_STATUS10_FAILADDR20(BV_DIGCTL_1TRAM_STATUS10_FAILADDR20__##e)
+#define BFM_DIGCTL_1TRAM_STATUS10_FAILADDR20_V(v)   BM_DIGCTL_1TRAM_STATUS10_FAILADDR20
+
+#define HW_DIGCTL_1TRAM_STATUS11                    HW(DIGCTL_1TRAM_STATUS11)
+#define HWA_DIGCTL_1TRAM_STATUS11                   (0x8001c000 + 0x1c0)
+#define HWT_DIGCTL_1TRAM_STATUS11                   HWIO_32_RW
+#define HWN_DIGCTL_1TRAM_STATUS11                   DIGCTL_1TRAM_STATUS11
+#define HWI_DIGCTL_1TRAM_STATUS11                   
+#define BP_DIGCTL_1TRAM_STATUS11_FAILADDR31         16
+#define BM_DIGCTL_1TRAM_STATUS11_FAILADDR31         0xffff0000
+#define BF_DIGCTL_1TRAM_STATUS11_FAILADDR31(v)      (((v) & 0xffff) << 16)
+#define BFM_DIGCTL_1TRAM_STATUS11_FAILADDR31(v)     BM_DIGCTL_1TRAM_STATUS11_FAILADDR31
+#define BF_DIGCTL_1TRAM_STATUS11_FAILADDR31_V(e)    BF_DIGCTL_1TRAM_STATUS11_FAILADDR31(BV_DIGCTL_1TRAM_STATUS11_FAILADDR31__##e)
+#define BFM_DIGCTL_1TRAM_STATUS11_FAILADDR31_V(v)   BM_DIGCTL_1TRAM_STATUS11_FAILADDR31
+#define BP_DIGCTL_1TRAM_STATUS11_FAILADDR30         0
+#define BM_DIGCTL_1TRAM_STATUS11_FAILADDR30         0xffff
+#define BF_DIGCTL_1TRAM_STATUS11_FAILADDR30(v)      (((v) & 0xffff) << 0)
+#define BFM_DIGCTL_1TRAM_STATUS11_FAILADDR30(v)     BM_DIGCTL_1TRAM_STATUS11_FAILADDR30
+#define BF_DIGCTL_1TRAM_STATUS11_FAILADDR30_V(e)    BF_DIGCTL_1TRAM_STATUS11_FAILADDR30(BV_DIGCTL_1TRAM_STATUS11_FAILADDR30__##e)
+#define BFM_DIGCTL_1TRAM_STATUS11_FAILADDR30_V(v)   BM_DIGCTL_1TRAM_STATUS11_FAILADDR30
+
+#define HW_DIGCTL_1TRAM_STATUS12                    HW(DIGCTL_1TRAM_STATUS12)
+#define HWA_DIGCTL_1TRAM_STATUS12                   (0x8001c000 + 0x1d0)
+#define HWT_DIGCTL_1TRAM_STATUS12                   HWIO_32_RW
+#define HWN_DIGCTL_1TRAM_STATUS12                   DIGCTL_1TRAM_STATUS12
+#define HWI_DIGCTL_1TRAM_STATUS12                   
+#define BP_DIGCTL_1TRAM_STATUS12_FAILSTATE11        24
+#define BM_DIGCTL_1TRAM_STATUS12_FAILSTATE11        0x1f000000
+#define BF_DIGCTL_1TRAM_STATUS12_FAILSTATE11(v)     (((v) & 0x1f) << 24)
+#define BFM_DIGCTL_1TRAM_STATUS12_FAILSTATE11(v)    BM_DIGCTL_1TRAM_STATUS12_FAILSTATE11
+#define BF_DIGCTL_1TRAM_STATUS12_FAILSTATE11_V(e)   BF_DIGCTL_1TRAM_STATUS12_FAILSTATE11(BV_DIGCTL_1TRAM_STATUS12_FAILSTATE11__##e)
+#define BFM_DIGCTL_1TRAM_STATUS12_FAILSTATE11_V(v)  BM_DIGCTL_1TRAM_STATUS12_FAILSTATE11
+#define BP_DIGCTL_1TRAM_STATUS12_FAILSTATE10        16
+#define BM_DIGCTL_1TRAM_STATUS12_FAILSTATE10        0x1f0000
+#define BF_DIGCTL_1TRAM_STATUS12_FAILSTATE10(v)     (((v) & 0x1f) << 16)
+#define BFM_DIGCTL_1TRAM_STATUS12_FAILSTATE10(v)    BM_DIGCTL_1TRAM_STATUS12_FAILSTATE10
+#define BF_DIGCTL_1TRAM_STATUS12_FAILSTATE10_V(e)   BF_DIGCTL_1TRAM_STATUS12_FAILSTATE10(BV_DIGCTL_1TRAM_STATUS12_FAILSTATE10__##e)
+#define BFM_DIGCTL_1TRAM_STATUS12_FAILSTATE10_V(v)  BM_DIGCTL_1TRAM_STATUS12_FAILSTATE10
+#define BP_DIGCTL_1TRAM_STATUS12_FAILSTATE01        8
+#define BM_DIGCTL_1TRAM_STATUS12_FAILSTATE01        0x1f00
+#define BF_DIGCTL_1TRAM_STATUS12_FAILSTATE01(v)     (((v) & 0x1f) << 8)
+#define BFM_DIGCTL_1TRAM_STATUS12_FAILSTATE01(v)    BM_DIGCTL_1TRAM_STATUS12_FAILSTATE01
+#define BF_DIGCTL_1TRAM_STATUS12_FAILSTATE01_V(e)   BF_DIGCTL_1TRAM_STATUS12_FAILSTATE01(BV_DIGCTL_1TRAM_STATUS12_FAILSTATE01__##e)
+#define BFM_DIGCTL_1TRAM_STATUS12_FAILSTATE01_V(v)  BM_DIGCTL_1TRAM_STATUS12_FAILSTATE01
+#define BP_DIGCTL_1TRAM_STATUS12_FAILSTATE00        0
+#define BM_DIGCTL_1TRAM_STATUS12_FAILSTATE00        0x1f
+#define BF_DIGCTL_1TRAM_STATUS12_FAILSTATE00(v)     (((v) & 0x1f) << 0)
+#define BFM_DIGCTL_1TRAM_STATUS12_FAILSTATE00(v)    BM_DIGCTL_1TRAM_STATUS12_FAILSTATE00
+#define BF_DIGCTL_1TRAM_STATUS12_FAILSTATE00_V(e)   BF_DIGCTL_1TRAM_STATUS12_FAILSTATE00(BV_DIGCTL_1TRAM_STATUS12_FAILSTATE00__##e)
+#define BFM_DIGCTL_1TRAM_STATUS12_FAILSTATE00_V(v)  BM_DIGCTL_1TRAM_STATUS12_FAILSTATE00
+
+#define HW_DIGCTL_1TRAM_STATUS13                    HW(DIGCTL_1TRAM_STATUS13)
+#define HWA_DIGCTL_1TRAM_STATUS13                   (0x8001c000 + 0x1e0)
+#define HWT_DIGCTL_1TRAM_STATUS13                   HWIO_32_RW
+#define HWN_DIGCTL_1TRAM_STATUS13                   DIGCTL_1TRAM_STATUS13
+#define HWI_DIGCTL_1TRAM_STATUS13                   
+#define BP_DIGCTL_1TRAM_STATUS13_FAILSTATE31        24
+#define BM_DIGCTL_1TRAM_STATUS13_FAILSTATE31        0x1f000000
+#define BF_DIGCTL_1TRAM_STATUS13_FAILSTATE31(v)     (((v) & 0x1f) << 24)
+#define BFM_DIGCTL_1TRAM_STATUS13_FAILSTATE31(v)    BM_DIGCTL_1TRAM_STATUS13_FAILSTATE31
+#define BF_DIGCTL_1TRAM_STATUS13_FAILSTATE31_V(e)   BF_DIGCTL_1TRAM_STATUS13_FAILSTATE31(BV_DIGCTL_1TRAM_STATUS13_FAILSTATE31__##e)
+#define BFM_DIGCTL_1TRAM_STATUS13_FAILSTATE31_V(v)  BM_DIGCTL_1TRAM_STATUS13_FAILSTATE31
+#define BP_DIGCTL_1TRAM_STATUS13_FAILSTATE30        16
+#define BM_DIGCTL_1TRAM_STATUS13_FAILSTATE30        0x1f0000
+#define BF_DIGCTL_1TRAM_STATUS13_FAILSTATE30(v)     (((v) & 0x1f) << 16)
+#define BFM_DIGCTL_1TRAM_STATUS13_FAILSTATE30(v)    BM_DIGCTL_1TRAM_STATUS13_FAILSTATE30
+#define BF_DIGCTL_1TRAM_STATUS13_FAILSTATE30_V(e)   BF_DIGCTL_1TRAM_STATUS13_FAILSTATE30(BV_DIGCTL_1TRAM_STATUS13_FAILSTATE30__##e)
+#define BFM_DIGCTL_1TRAM_STATUS13_FAILSTATE30_V(v)  BM_DIGCTL_1TRAM_STATUS13_FAILSTATE30
+#define BP_DIGCTL_1TRAM_STATUS13_FAILSTATE21        8
+#define BM_DIGCTL_1TRAM_STATUS13_FAILSTATE21        0x1f00
+#define BF_DIGCTL_1TRAM_STATUS13_FAILSTATE21(v)     (((v) & 0x1f) << 8)
+#define BFM_DIGCTL_1TRAM_STATUS13_FAILSTATE21(v)    BM_DIGCTL_1TRAM_STATUS13_FAILSTATE21
+#define BF_DIGCTL_1TRAM_STATUS13_FAILSTATE21_V(e)   BF_DIGCTL_1TRAM_STATUS13_FAILSTATE21(BV_DIGCTL_1TRAM_STATUS13_FAILSTATE21__##e)
+#define BFM_DIGCTL_1TRAM_STATUS13_FAILSTATE21_V(v)  BM_DIGCTL_1TRAM_STATUS13_FAILSTATE21
+#define BP_DIGCTL_1TRAM_STATUS13_FAILSTATE20        0
+#define BM_DIGCTL_1TRAM_STATUS13_FAILSTATE20        0x1f
+#define BF_DIGCTL_1TRAM_STATUS13_FAILSTATE20(v)     (((v) & 0x1f) << 0)
+#define BFM_DIGCTL_1TRAM_STATUS13_FAILSTATE20(v)    BM_DIGCTL_1TRAM_STATUS13_FAILSTATE20
+#define BF_DIGCTL_1TRAM_STATUS13_FAILSTATE20_V(e)   BF_DIGCTL_1TRAM_STATUS13_FAILSTATE20(BV_DIGCTL_1TRAM_STATUS13_FAILSTATE20__##e)
+#define BFM_DIGCTL_1TRAM_STATUS13_FAILSTATE20_V(v)  BM_DIGCTL_1TRAM_STATUS13_FAILSTATE20
+
+#define HW_DIGCTL_SCRATCH0              HW(DIGCTL_SCRATCH0)
+#define HWA_DIGCTL_SCRATCH0             (0x8001c000 + 0x290)
+#define HWT_DIGCTL_SCRATCH0             HWIO_32_RW
+#define HWN_DIGCTL_SCRATCH0             DIGCTL_SCRATCH0
+#define HWI_DIGCTL_SCRATCH0             
+#define BP_DIGCTL_SCRATCH0_PTR          0
+#define BM_DIGCTL_SCRATCH0_PTR          0xffffffff
+#define BF_DIGCTL_SCRATCH0_PTR(v)       (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_SCRATCH0_PTR(v)      BM_DIGCTL_SCRATCH0_PTR
+#define BF_DIGCTL_SCRATCH0_PTR_V(e)     BF_DIGCTL_SCRATCH0_PTR(BV_DIGCTL_SCRATCH0_PTR__##e)
+#define BFM_DIGCTL_SCRATCH0_PTR_V(v)    BM_DIGCTL_SCRATCH0_PTR
+
+#define HW_DIGCTL_SCRATCH1              HW(DIGCTL_SCRATCH1)
+#define HWA_DIGCTL_SCRATCH1             (0x8001c000 + 0x2a0)
+#define HWT_DIGCTL_SCRATCH1             HWIO_32_RW
+#define HWN_DIGCTL_SCRATCH1             DIGCTL_SCRATCH1
+#define HWI_DIGCTL_SCRATCH1             
+#define BP_DIGCTL_SCRATCH1_PTR          0
+#define BM_DIGCTL_SCRATCH1_PTR          0xffffffff
+#define BF_DIGCTL_SCRATCH1_PTR(v)       (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_SCRATCH1_PTR(v)      BM_DIGCTL_SCRATCH1_PTR
+#define BF_DIGCTL_SCRATCH1_PTR_V(e)     BF_DIGCTL_SCRATCH1_PTR(BV_DIGCTL_SCRATCH1_PTR__##e)
+#define BFM_DIGCTL_SCRATCH1_PTR_V(v)    BM_DIGCTL_SCRATCH1_PTR
+
+#define HW_DIGCTL_ARMCACHE                  HW(DIGCTL_ARMCACHE)
+#define HWA_DIGCTL_ARMCACHE                 (0x8001c000 + 0x2b0)
+#define HWT_DIGCTL_ARMCACHE                 HWIO_32_RW
+#define HWN_DIGCTL_ARMCACHE                 DIGCTL_ARMCACHE
+#define HWI_DIGCTL_ARMCACHE                 
+#define BP_DIGCTL_ARMCACHE_CACHE_SS         8
+#define BM_DIGCTL_ARMCACHE_CACHE_SS         0x300
+#define BF_DIGCTL_ARMCACHE_CACHE_SS(v)      (((v) & 0x3) << 8)
+#define BFM_DIGCTL_ARMCACHE_CACHE_SS(v)     BM_DIGCTL_ARMCACHE_CACHE_SS
+#define BF_DIGCTL_ARMCACHE_CACHE_SS_V(e)    BF_DIGCTL_ARMCACHE_CACHE_SS(BV_DIGCTL_ARMCACHE_CACHE_SS__##e)
+#define BFM_DIGCTL_ARMCACHE_CACHE_SS_V(v)   BM_DIGCTL_ARMCACHE_CACHE_SS
+#define BP_DIGCTL_ARMCACHE_DTAG_SS          4
+#define BM_DIGCTL_ARMCACHE_DTAG_SS          0x30
+#define BF_DIGCTL_ARMCACHE_DTAG_SS(v)       (((v) & 0x3) << 4)
+#define BFM_DIGCTL_ARMCACHE_DTAG_SS(v)      BM_DIGCTL_ARMCACHE_DTAG_SS
+#define BF_DIGCTL_ARMCACHE_DTAG_SS_V(e)     BF_DIGCTL_ARMCACHE_DTAG_SS(BV_DIGCTL_ARMCACHE_DTAG_SS__##e)
+#define BFM_DIGCTL_ARMCACHE_DTAG_SS_V(v)    BM_DIGCTL_ARMCACHE_DTAG_SS
+#define BP_DIGCTL_ARMCACHE_ITAG_SS          0
+#define BM_DIGCTL_ARMCACHE_ITAG_SS          0x3
+#define BF_DIGCTL_ARMCACHE_ITAG_SS(v)       (((v) & 0x3) << 0)
+#define BFM_DIGCTL_ARMCACHE_ITAG_SS(v)      BM_DIGCTL_ARMCACHE_ITAG_SS
+#define BF_DIGCTL_ARMCACHE_ITAG_SS_V(e)     BF_DIGCTL_ARMCACHE_ITAG_SS(BV_DIGCTL_ARMCACHE_ITAG_SS__##e)
+#define BFM_DIGCTL_ARMCACHE_ITAG_SS_V(v)    BM_DIGCTL_ARMCACHE_ITAG_SS
+
+#define HW_DIGCTL_SGTL                  HW(DIGCTL_SGTL)
+#define HWA_DIGCTL_SGTL                 (0x8001c000 + 0x300)
+#define HWT_DIGCTL_SGTL                 HWIO_32_RW
+#define HWN_DIGCTL_SGTL                 DIGCTL_SGTL
+#define HWI_DIGCTL_SGTL                 
+#define BP_DIGCTL_SGTL_COPYRIGHT        0
+#define BM_DIGCTL_SGTL_COPYRIGHT        0xffffffff
+#define BF_DIGCTL_SGTL_COPYRIGHT(v)     (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_SGTL_COPYRIGHT(v)    BM_DIGCTL_SGTL_COPYRIGHT
+#define BF_DIGCTL_SGTL_COPYRIGHT_V(e)   BF_DIGCTL_SGTL_COPYRIGHT(BV_DIGCTL_SGTL_COPYRIGHT__##e)
+#define BFM_DIGCTL_SGTL_COPYRIGHT_V(v)  BM_DIGCTL_SGTL_COPYRIGHT
+
+#define HW_DIGCTL_CHIPID                    HW(DIGCTL_CHIPID)
+#define HWA_DIGCTL_CHIPID                   (0x8001c000 + 0x310)
+#define HWT_DIGCTL_CHIPID                   HWIO_32_RW
+#define HWN_DIGCTL_CHIPID                   DIGCTL_CHIPID
+#define HWI_DIGCTL_CHIPID                   
+#define BP_DIGCTL_CHIPID_PRODUCT_CODE       16
+#define BM_DIGCTL_CHIPID_PRODUCT_CODE       0xffff0000
+#define BF_DIGCTL_CHIPID_PRODUCT_CODE(v)    (((v) & 0xffff) << 16)
+#define BFM_DIGCTL_CHIPID_PRODUCT_CODE(v)   BM_DIGCTL_CHIPID_PRODUCT_CODE
+#define BF_DIGCTL_CHIPID_PRODUCT_CODE_V(e)  BF_DIGCTL_CHIPID_PRODUCT_CODE(BV_DIGCTL_CHIPID_PRODUCT_CODE__##e)
+#define BFM_DIGCTL_CHIPID_PRODUCT_CODE_V(v) BM_DIGCTL_CHIPID_PRODUCT_CODE
+#define BP_DIGCTL_CHIPID_REVISION           0
+#define BM_DIGCTL_CHIPID_REVISION           0xff
+#define BF_DIGCTL_CHIPID_REVISION(v)        (((v) & 0xff) << 0)
+#define BFM_DIGCTL_CHIPID_REVISION(v)       BM_DIGCTL_CHIPID_REVISION
+#define BF_DIGCTL_CHIPID_REVISION_V(e)      BF_DIGCTL_CHIPID_REVISION(BV_DIGCTL_CHIPID_REVISION__##e)
+#define BFM_DIGCTL_CHIPID_REVISION_V(v)     BM_DIGCTL_CHIPID_REVISION
+
+#endif /* __HEADERGEN_STMP3600_DIGCTL_H__*/
diff --git a/firmware/target/arm/imx233/regs/stmp3600/dri.h b/firmware/target/arm/imx233/regs/stmp3600/dri.h
new file mode 100644
index 0000000000..a57f405715
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3600/dri.h
@@ -0,0 +1,370 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * stmp3600 version: 2.4.0
+ * stmp3600 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_STMP3600_DRI_H__
+#define __HEADERGEN_STMP3600_DRI_H__
+
+#define HW_DRI_CTRL                                     HW(DRI_CTRL)
+#define HWA_DRI_CTRL                                    (0x80074000 + 0x0)
+#define HWT_DRI_CTRL                                    HWIO_32_RW
+#define HWN_DRI_CTRL                                    DRI_CTRL
+#define HWI_DRI_CTRL                                    
+#define HW_DRI_CTRL_SET                                 HW(DRI_CTRL_SET)
+#define HWA_DRI_CTRL_SET                                (HWA_DRI_CTRL + 0x4)
+#define HWT_DRI_CTRL_SET                                HWIO_32_WO
+#define HWN_DRI_CTRL_SET                                DRI_CTRL
+#define HWI_DRI_CTRL_SET                                
+#define HW_DRI_CTRL_CLR                                 HW(DRI_CTRL_CLR)
+#define HWA_DRI_CTRL_CLR                                (HWA_DRI_CTRL + 0x8)
+#define HWT_DRI_CTRL_CLR                                HWIO_32_WO
+#define HWN_DRI_CTRL_CLR                                DRI_CTRL
+#define HWI_DRI_CTRL_CLR                                
+#define HW_DRI_CTRL_TOG                                 HW(DRI_CTRL_TOG)
+#define HWA_DRI_CTRL_TOG                                (HWA_DRI_CTRL + 0xc)
+#define HWT_DRI_CTRL_TOG                                HWIO_32_WO
+#define HWN_DRI_CTRL_TOG                                DRI_CTRL
+#define HWI_DRI_CTRL_TOG                                
+#define BP_DRI_CTRL_SFTRST                              31
+#define BM_DRI_CTRL_SFTRST                              0x80000000
+#define BV_DRI_CTRL_SFTRST__RUN                         0x0
+#define BV_DRI_CTRL_SFTRST__RESET                       0x1
+#define BF_DRI_CTRL_SFTRST(v)                           (((v) & 0x1) << 31)
+#define BFM_DRI_CTRL_SFTRST(v)                          BM_DRI_CTRL_SFTRST
+#define BF_DRI_CTRL_SFTRST_V(e)                         BF_DRI_CTRL_SFTRST(BV_DRI_CTRL_SFTRST__##e)
+#define BFM_DRI_CTRL_SFTRST_V(v)                        BM_DRI_CTRL_SFTRST
+#define BP_DRI_CTRL_CLKGATE                             30
+#define BM_DRI_CTRL_CLKGATE                             0x40000000
+#define BV_DRI_CTRL_CLKGATE__RUN                        0x0
+#define BV_DRI_CTRL_CLKGATE__NO_CLKS                    0x1
+#define BF_DRI_CTRL_CLKGATE(v)                          (((v) & 0x1) << 30)
+#define BFM_DRI_CTRL_CLKGATE(v)                         BM_DRI_CTRL_CLKGATE
+#define BF_DRI_CTRL_CLKGATE_V(e)                        BF_DRI_CTRL_CLKGATE(BV_DRI_CTRL_CLKGATE__##e)
+#define BFM_DRI_CTRL_CLKGATE_V(v)                       BM_DRI_CTRL_CLKGATE
+#define BP_DRI_CTRL_ENABLE_INPUTS                       29
+#define BM_DRI_CTRL_ENABLE_INPUTS                       0x20000000
+#define BV_DRI_CTRL_ENABLE_INPUTS__ANALOG_LINE_IN       0x0
+#define BV_DRI_CTRL_ENABLE_INPUTS__DRI_DIGITAL_IN       0x1
+#define BF_DRI_CTRL_ENABLE_INPUTS(v)                    (((v) & 0x1) << 29)
+#define BFM_DRI_CTRL_ENABLE_INPUTS(v)                   BM_DRI_CTRL_ENABLE_INPUTS
+#define BF_DRI_CTRL_ENABLE_INPUTS_V(e)                  BF_DRI_CTRL_ENABLE_INPUTS(BV_DRI_CTRL_ENABLE_INPUTS__##e)
+#define BFM_DRI_CTRL_ENABLE_INPUTS_V(v)                 BM_DRI_CTRL_ENABLE_INPUTS
+#define BP_DRI_CTRL_STOP_ON_OFLOW_ERROR                 26
+#define BM_DRI_CTRL_STOP_ON_OFLOW_ERROR                 0x4000000
+#define BV_DRI_CTRL_STOP_ON_OFLOW_ERROR__IGNORE         0x0
+#define BV_DRI_CTRL_STOP_ON_OFLOW_ERROR__STOP           0x1
+#define BF_DRI_CTRL_STOP_ON_OFLOW_ERROR(v)              (((v) & 0x1) << 26)
+#define BFM_DRI_CTRL_STOP_ON_OFLOW_ERROR(v)             BM_DRI_CTRL_STOP_ON_OFLOW_ERROR
+#define BF_DRI_CTRL_STOP_ON_OFLOW_ERROR_V(e)            BF_DRI_CTRL_STOP_ON_OFLOW_ERROR(BV_DRI_CTRL_STOP_ON_OFLOW_ERROR__##e)
+#define BFM_DRI_CTRL_STOP_ON_OFLOW_ERROR_V(v)           BM_DRI_CTRL_STOP_ON_OFLOW_ERROR
+#define BP_DRI_CTRL_STOP_ON_PILOT_ERROR                 25
+#define BM_DRI_CTRL_STOP_ON_PILOT_ERROR                 0x2000000
+#define BV_DRI_CTRL_STOP_ON_PILOT_ERROR__IGNORE         0x0
+#define BV_DRI_CTRL_STOP_ON_PILOT_ERROR__STOP           0x1
+#define BF_DRI_CTRL_STOP_ON_PILOT_ERROR(v)              (((v) & 0x1) << 25)
+#define BFM_DRI_CTRL_STOP_ON_PILOT_ERROR(v)             BM_DRI_CTRL_STOP_ON_PILOT_ERROR
+#define BF_DRI_CTRL_STOP_ON_PILOT_ERROR_V(e)            BF_DRI_CTRL_STOP_ON_PILOT_ERROR(BV_DRI_CTRL_STOP_ON_PILOT_ERROR__##e)
+#define BFM_DRI_CTRL_STOP_ON_PILOT_ERROR_V(v)           BM_DRI_CTRL_STOP_ON_PILOT_ERROR
+#define BP_DRI_CTRL_DMA_DELAY_COUNT                     16
+#define BM_DRI_CTRL_DMA_DELAY_COUNT                     0x1f0000
+#define BF_DRI_CTRL_DMA_DELAY_COUNT(v)                  (((v) & 0x1f) << 16)
+#define BFM_DRI_CTRL_DMA_DELAY_COUNT(v)                 BM_DRI_CTRL_DMA_DELAY_COUNT
+#define BF_DRI_CTRL_DMA_DELAY_COUNT_V(e)                BF_DRI_CTRL_DMA_DELAY_COUNT(BV_DRI_CTRL_DMA_DELAY_COUNT__##e)
+#define BFM_DRI_CTRL_DMA_DELAY_COUNT_V(v)               BM_DRI_CTRL_DMA_DELAY_COUNT
+#define BP_DRI_CTRL_REACQUIRE_PHASE                     15
+#define BM_DRI_CTRL_REACQUIRE_PHASE                     0x8000
+#define BV_DRI_CTRL_REACQUIRE_PHASE__NORMAL             0x0
+#define BV_DRI_CTRL_REACQUIRE_PHASE__NEW_PHASE          0x1
+#define BF_DRI_CTRL_REACQUIRE_PHASE(v)                  (((v) & 0x1) << 15)
+#define BFM_DRI_CTRL_REACQUIRE_PHASE(v)                 BM_DRI_CTRL_REACQUIRE_PHASE
+#define BF_DRI_CTRL_REACQUIRE_PHASE_V(e)                BF_DRI_CTRL_REACQUIRE_PHASE(BV_DRI_CTRL_REACQUIRE_PHASE__##e)
+#define BFM_DRI_CTRL_REACQUIRE_PHASE_V(v)               BM_DRI_CTRL_REACQUIRE_PHASE
+#define BP_DRI_CTRL_OVERFLOW_IRQ_EN                     11
+#define BM_DRI_CTRL_OVERFLOW_IRQ_EN                     0x800
+#define BV_DRI_CTRL_OVERFLOW_IRQ_EN__DISABLED           0x0
+#define BV_DRI_CTRL_OVERFLOW_IRQ_EN__ENABLED            0x1
+#define BF_DRI_CTRL_OVERFLOW_IRQ_EN(v)                  (((v) & 0x1) << 11)
+#define BFM_DRI_CTRL_OVERFLOW_IRQ_EN(v)                 BM_DRI_CTRL_OVERFLOW_IRQ_EN
+#define BF_DRI_CTRL_OVERFLOW_IRQ_EN_V(e)                BF_DRI_CTRL_OVERFLOW_IRQ_EN(BV_DRI_CTRL_OVERFLOW_IRQ_EN__##e)
+#define BFM_DRI_CTRL_OVERFLOW_IRQ_EN_V(v)               BM_DRI_CTRL_OVERFLOW_IRQ_EN
+#define BP_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN              10
+#define BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN              0x400
+#define BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN__DISABLED    0x0
+#define BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN__ENABLED     0x1
+#define BF_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN(v)           (((v) & 0x1) << 10)
+#define BFM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN(v)          BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN
+#define BF_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN_V(e)         BF_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN(BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN__##e)
+#define BFM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN_V(v)        BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN
+#define BP_DRI_CTRL_ATTENTION_IRQ_EN                    9
+#define BM_DRI_CTRL_ATTENTION_IRQ_EN                    0x200
+#define BV_DRI_CTRL_ATTENTION_IRQ_EN__DISABLED          0x0
+#define BV_DRI_CTRL_ATTENTION_IRQ_EN__ENABLED           0x1
+#define BF_DRI_CTRL_ATTENTION_IRQ_EN(v)                 (((v) & 0x1) << 9)
+#define BFM_DRI_CTRL_ATTENTION_IRQ_EN(v)                BM_DRI_CTRL_ATTENTION_IRQ_EN
+#define BF_DRI_CTRL_ATTENTION_IRQ_EN_V(e)               BF_DRI_CTRL_ATTENTION_IRQ_EN(BV_DRI_CTRL_ATTENTION_IRQ_EN__##e)
+#define BFM_DRI_CTRL_ATTENTION_IRQ_EN_V(v)              BM_DRI_CTRL_ATTENTION_IRQ_EN
+#define BP_DRI_CTRL_OVERFLOW_IRQ                        3
+#define BM_DRI_CTRL_OVERFLOW_IRQ                        0x8
+#define BV_DRI_CTRL_OVERFLOW_IRQ__NO_REQUEST            0x0
+#define BV_DRI_CTRL_OVERFLOW_IRQ__REQUEST               0x1
+#define BF_DRI_CTRL_OVERFLOW_IRQ(v)                     (((v) & 0x1) << 3)
+#define BFM_DRI_CTRL_OVERFLOW_IRQ(v)                    BM_DRI_CTRL_OVERFLOW_IRQ
+#define BF_DRI_CTRL_OVERFLOW_IRQ_V(e)                   BF_DRI_CTRL_OVERFLOW_IRQ(BV_DRI_CTRL_OVERFLOW_IRQ__##e)
+#define BFM_DRI_CTRL_OVERFLOW_IRQ_V(v)                  BM_DRI_CTRL_OVERFLOW_IRQ
+#define BP_DRI_CTRL_PILOT_SYNC_LOSS_IRQ                 2
+#define BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ                 0x4
+#define BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ__NO_REQUEST     0x0
+#define BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ__REQUEST        0x1
+#define BF_DRI_CTRL_PILOT_SYNC_LOSS_IRQ(v)              (((v) & 0x1) << 2)
+#define BFM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ(v)             BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ
+#define BF_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_V(e)            BF_DRI_CTRL_PILOT_SYNC_LOSS_IRQ(BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ__##e)
+#define BFM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_V(v)           BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ
+#define BP_DRI_CTRL_ATTENTION_IRQ                       1
+#define BM_DRI_CTRL_ATTENTION_IRQ                       0x2
+#define BV_DRI_CTRL_ATTENTION_IRQ__NO_REQUEST           0x0
+#define BV_DRI_CTRL_ATTENTION_IRQ__REQUEST              0x1
+#define BF_DRI_CTRL_ATTENTION_IRQ(v)                    (((v) & 0x1) << 1)
+#define BFM_DRI_CTRL_ATTENTION_IRQ(v)                   BM_DRI_CTRL_ATTENTION_IRQ
+#define BF_DRI_CTRL_ATTENTION_IRQ_V(e)                  BF_DRI_CTRL_ATTENTION_IRQ(BV_DRI_CTRL_ATTENTION_IRQ__##e)
+#define BFM_DRI_CTRL_ATTENTION_IRQ_V(v)                 BM_DRI_CTRL_ATTENTION_IRQ
+#define BP_DRI_CTRL_RUN                                 0
+#define BM_DRI_CTRL_RUN                                 0x1
+#define BV_DRI_CTRL_RUN__HALT                           0x0
+#define BV_DRI_CTRL_RUN__RUN                            0x1
+#define BF_DRI_CTRL_RUN(v)                              (((v) & 0x1) << 0)
+#define BFM_DRI_CTRL_RUN(v)                             BM_DRI_CTRL_RUN
+#define BF_DRI_CTRL_RUN_V(e)                            BF_DRI_CTRL_RUN(BV_DRI_CTRL_RUN__##e)
+#define BFM_DRI_CTRL_RUN_V(v)                           BM_DRI_CTRL_RUN
+
+#define HW_DRI_TIMING                               HW(DRI_TIMING)
+#define HWA_DRI_TIMING                              (0x80074000 + 0x10)
+#define HWT_DRI_TIMING                              HWIO_32_RW
+#define HWN_DRI_TIMING                              DRI_TIMING
+#define HWI_DRI_TIMING                              
+#define BP_DRI_TIMING_PILOT_REP_RATE                16
+#define BM_DRI_TIMING_PILOT_REP_RATE                0xf0000
+#define BF_DRI_TIMING_PILOT_REP_RATE(v)             (((v) & 0xf) << 16)
+#define BFM_DRI_TIMING_PILOT_REP_RATE(v)            BM_DRI_TIMING_PILOT_REP_RATE
+#define BF_DRI_TIMING_PILOT_REP_RATE_V(e)           BF_DRI_TIMING_PILOT_REP_RATE(BV_DRI_TIMING_PILOT_REP_RATE__##e)
+#define BFM_DRI_TIMING_PILOT_REP_RATE_V(v)          BM_DRI_TIMING_PILOT_REP_RATE
+#define BP_DRI_TIMING_GAP_DETECTION_INTERVAL        0
+#define BM_DRI_TIMING_GAP_DETECTION_INTERVAL        0xff
+#define BF_DRI_TIMING_GAP_DETECTION_INTERVAL(v)     (((v) & 0xff) << 0)
+#define BFM_DRI_TIMING_GAP_DETECTION_INTERVAL(v)    BM_DRI_TIMING_GAP_DETECTION_INTERVAL
+#define BF_DRI_TIMING_GAP_DETECTION_INTERVAL_V(e)   BF_DRI_TIMING_GAP_DETECTION_INTERVAL(BV_DRI_TIMING_GAP_DETECTION_INTERVAL__##e)
+#define BFM_DRI_TIMING_GAP_DETECTION_INTERVAL_V(v)  BM_DRI_TIMING_GAP_DETECTION_INTERVAL
+
+#define HW_DRI_STAT                                         HW(DRI_STAT)
+#define HWA_DRI_STAT                                        (0x80074000 + 0x20)
+#define HWT_DRI_STAT                                        HWIO_32_RW
+#define HWN_DRI_STAT                                        DRI_STAT
+#define HWI_DRI_STAT                                        
+#define BP_DRI_STAT_DRI_PRESENT                             31
+#define BM_DRI_STAT_DRI_PRESENT                             0x80000000
+#define BV_DRI_STAT_DRI_PRESENT__UNAVAILABLE                0x0
+#define BV_DRI_STAT_DRI_PRESENT__AVAILABLE                  0x1
+#define BF_DRI_STAT_DRI_PRESENT(v)                          (((v) & 0x1) << 31)
+#define BFM_DRI_STAT_DRI_PRESENT(v)                         BM_DRI_STAT_DRI_PRESENT
+#define BF_DRI_STAT_DRI_PRESENT_V(e)                        BF_DRI_STAT_DRI_PRESENT(BV_DRI_STAT_DRI_PRESENT__##e)
+#define BFM_DRI_STAT_DRI_PRESENT_V(v)                       BM_DRI_STAT_DRI_PRESENT
+#define BP_DRI_STAT_PILOT_PHASE                             16
+#define BM_DRI_STAT_PILOT_PHASE                             0xf0000
+#define BF_DRI_STAT_PILOT_PHASE(v)                          (((v) & 0xf) << 16)
+#define BFM_DRI_STAT_PILOT_PHASE(v)                         BM_DRI_STAT_PILOT_PHASE
+#define BF_DRI_STAT_PILOT_PHASE_V(e)                        BF_DRI_STAT_PILOT_PHASE(BV_DRI_STAT_PILOT_PHASE__##e)
+#define BFM_DRI_STAT_PILOT_PHASE_V(v)                       BM_DRI_STAT_PILOT_PHASE
+#define BP_DRI_STAT_OVERFLOW_IRQ_SUMMARY                    3
+#define BM_DRI_STAT_OVERFLOW_IRQ_SUMMARY                    0x8
+#define BV_DRI_STAT_OVERFLOW_IRQ_SUMMARY__NO_REQUEST        0x0
+#define BV_DRI_STAT_OVERFLOW_IRQ_SUMMARY__REQUEST           0x1
+#define BF_DRI_STAT_OVERFLOW_IRQ_SUMMARY(v)                 (((v) & 0x1) << 3)
+#define BFM_DRI_STAT_OVERFLOW_IRQ_SUMMARY(v)                BM_DRI_STAT_OVERFLOW_IRQ_SUMMARY
+#define BF_DRI_STAT_OVERFLOW_IRQ_SUMMARY_V(e)               BF_DRI_STAT_OVERFLOW_IRQ_SUMMARY(BV_DRI_STAT_OVERFLOW_IRQ_SUMMARY__##e)
+#define BFM_DRI_STAT_OVERFLOW_IRQ_SUMMARY_V(v)              BM_DRI_STAT_OVERFLOW_IRQ_SUMMARY
+#define BP_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY             2
+#define BM_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY             0x4
+#define BV_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY__NO_REQUEST 0x0
+#define BV_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY__REQUEST    0x1
+#define BF_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY(v)          (((v) & 0x1) << 2)
+#define BFM_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY(v)         BM_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY
+#define BF_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY_V(e)        BF_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY(BV_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY__##e)
+#define BFM_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY_V(v)       BM_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY
+#define BP_DRI_STAT_ATTENTION_IRQ_SUMMARY                   1
+#define BM_DRI_STAT_ATTENTION_IRQ_SUMMARY                   0x2
+#define BV_DRI_STAT_ATTENTION_IRQ_SUMMARY__NO_REQUEST       0x0
+#define BV_DRI_STAT_ATTENTION_IRQ_SUMMARY__REQUEST          0x1
+#define BF_DRI_STAT_ATTENTION_IRQ_SUMMARY(v)                (((v) & 0x1) << 1)
+#define BFM_DRI_STAT_ATTENTION_IRQ_SUMMARY(v)               BM_DRI_STAT_ATTENTION_IRQ_SUMMARY
+#define BF_DRI_STAT_ATTENTION_IRQ_SUMMARY_V(e)              BF_DRI_STAT_ATTENTION_IRQ_SUMMARY(BV_DRI_STAT_ATTENTION_IRQ_SUMMARY__##e)
+#define BFM_DRI_STAT_ATTENTION_IRQ_SUMMARY_V(v)             BM_DRI_STAT_ATTENTION_IRQ_SUMMARY
+
+#define HW_DRI_DATA             HW(DRI_DATA)
+#define HWA_DRI_DATA            (0x80074000 + 0x30)
+#define HWT_DRI_DATA            HWIO_32_RW
+#define HWN_DRI_DATA            DRI_DATA
+#define HWI_DRI_DATA            
+#define BP_DRI_DATA_DATA        0
+#define BM_DRI_DATA_DATA        0xffffffff
+#define BF_DRI_DATA_DATA(v)     (((v) & 0xffffffff) << 0)
+#define BFM_DRI_DATA_DATA(v)    BM_DRI_DATA_DATA
+#define BF_DRI_DATA_DATA_V(e)   BF_DRI_DATA_DATA(BV_DRI_DATA_DATA__##e)
+#define BFM_DRI_DATA_DATA_V(v)  BM_DRI_DATA_DATA
+
+#define HW_DRI_DEBUG0                               HW(DRI_DEBUG0)
+#define HWA_DRI_DEBUG0                              (0x80074000 + 0x40)
+#define HWT_DRI_DEBUG0                              HWIO_32_RW
+#define HWN_DRI_DEBUG0                              DRI_DEBUG0
+#define HWI_DRI_DEBUG0                              
+#define HW_DRI_DEBUG0_SET                           HW(DRI_DEBUG0_SET)
+#define HWA_DRI_DEBUG0_SET                          (HWA_DRI_DEBUG0 + 0x4)
+#define HWT_DRI_DEBUG0_SET                          HWIO_32_WO
+#define HWN_DRI_DEBUG0_SET                          DRI_DEBUG0
+#define HWI_DRI_DEBUG0_SET                          
+#define HW_DRI_DEBUG0_CLR                           HW(DRI_DEBUG0_CLR)
+#define HWA_DRI_DEBUG0_CLR                          (HWA_DRI_DEBUG0 + 0x8)
+#define HWT_DRI_DEBUG0_CLR                          HWIO_32_WO
+#define HWN_DRI_DEBUG0_CLR                          DRI_DEBUG0
+#define HWI_DRI_DEBUG0_CLR                          
+#define HW_DRI_DEBUG0_TOG                           HW(DRI_DEBUG0_TOG)
+#define HWA_DRI_DEBUG0_TOG                          (HWA_DRI_DEBUG0 + 0xc)
+#define HWT_DRI_DEBUG0_TOG                          HWIO_32_WO
+#define HWN_DRI_DEBUG0_TOG                          DRI_DEBUG0
+#define HWI_DRI_DEBUG0_TOG                          
+#define BP_DRI_DEBUG0_DMAREQ                        31
+#define BM_DRI_DEBUG0_DMAREQ                        0x80000000
+#define BF_DRI_DEBUG0_DMAREQ(v)                     (((v) & 0x1) << 31)
+#define BFM_DRI_DEBUG0_DMAREQ(v)                    BM_DRI_DEBUG0_DMAREQ
+#define BF_DRI_DEBUG0_DMAREQ_V(e)                   BF_DRI_DEBUG0_DMAREQ(BV_DRI_DEBUG0_DMAREQ__##e)
+#define BFM_DRI_DEBUG0_DMAREQ_V(v)                  BM_DRI_DEBUG0_DMAREQ
+#define BP_DRI_DEBUG0_DMACMDKICK                    30
+#define BM_DRI_DEBUG0_DMACMDKICK                    0x40000000
+#define BF_DRI_DEBUG0_DMACMDKICK(v)                 (((v) & 0x1) << 30)
+#define BFM_DRI_DEBUG0_DMACMDKICK(v)                BM_DRI_DEBUG0_DMACMDKICK
+#define BF_DRI_DEBUG0_DMACMDKICK_V(e)               BF_DRI_DEBUG0_DMACMDKICK(BV_DRI_DEBUG0_DMACMDKICK__##e)
+#define BFM_DRI_DEBUG0_DMACMDKICK_V(v)              BM_DRI_DEBUG0_DMACMDKICK
+#define BP_DRI_DEBUG0_DRI_CLK_INPUT                 29
+#define BM_DRI_DEBUG0_DRI_CLK_INPUT                 0x20000000
+#define BF_DRI_DEBUG0_DRI_CLK_INPUT(v)              (((v) & 0x1) << 29)
+#define BFM_DRI_DEBUG0_DRI_CLK_INPUT(v)             BM_DRI_DEBUG0_DRI_CLK_INPUT
+#define BF_DRI_DEBUG0_DRI_CLK_INPUT_V(e)            BF_DRI_DEBUG0_DRI_CLK_INPUT(BV_DRI_DEBUG0_DRI_CLK_INPUT__##e)
+#define BFM_DRI_DEBUG0_DRI_CLK_INPUT_V(v)           BM_DRI_DEBUG0_DRI_CLK_INPUT
+#define BP_DRI_DEBUG0_DRI_DATA_INPUT                28
+#define BM_DRI_DEBUG0_DRI_DATA_INPUT                0x10000000
+#define BF_DRI_DEBUG0_DRI_DATA_INPUT(v)             (((v) & 0x1) << 28)
+#define BFM_DRI_DEBUG0_DRI_DATA_INPUT(v)            BM_DRI_DEBUG0_DRI_DATA_INPUT
+#define BF_DRI_DEBUG0_DRI_DATA_INPUT_V(e)           BF_DRI_DEBUG0_DRI_DATA_INPUT(BV_DRI_DEBUG0_DRI_DATA_INPUT__##e)
+#define BFM_DRI_DEBUG0_DRI_DATA_INPUT_V(v)          BM_DRI_DEBUG0_DRI_DATA_INPUT
+#define BP_DRI_DEBUG0_TEST_MODE                     27
+#define BM_DRI_DEBUG0_TEST_MODE                     0x8000000
+#define BF_DRI_DEBUG0_TEST_MODE(v)                  (((v) & 0x1) << 27)
+#define BFM_DRI_DEBUG0_TEST_MODE(v)                 BM_DRI_DEBUG0_TEST_MODE
+#define BF_DRI_DEBUG0_TEST_MODE_V(e)                BF_DRI_DEBUG0_TEST_MODE(BV_DRI_DEBUG0_TEST_MODE__##e)
+#define BFM_DRI_DEBUG0_TEST_MODE_V(v)               BM_DRI_DEBUG0_TEST_MODE
+#define BP_DRI_DEBUG0_PILOT_REP_RATE                26
+#define BM_DRI_DEBUG0_PILOT_REP_RATE                0x4000000
+#define BV_DRI_DEBUG0_PILOT_REP_RATE__8_AT_4MHZ     0x0
+#define BV_DRI_DEBUG0_PILOT_REP_RATE__12_AT_6MHZ    0x1
+#define BF_DRI_DEBUG0_PILOT_REP_RATE(v)             (((v) & 0x1) << 26)
+#define BFM_DRI_DEBUG0_PILOT_REP_RATE(v)            BM_DRI_DEBUG0_PILOT_REP_RATE
+#define BF_DRI_DEBUG0_PILOT_REP_RATE_V(e)           BF_DRI_DEBUG0_PILOT_REP_RATE(BV_DRI_DEBUG0_PILOT_REP_RATE__##e)
+#define BFM_DRI_DEBUG0_PILOT_REP_RATE_V(v)          BM_DRI_DEBUG0_PILOT_REP_RATE
+#define BP_DRI_DEBUG0_SPARE                         18
+#define BM_DRI_DEBUG0_SPARE                         0x3fc0000
+#define BF_DRI_DEBUG0_SPARE(v)                      (((v) & 0xff) << 18)
+#define BFM_DRI_DEBUG0_SPARE(v)                     BM_DRI_DEBUG0_SPARE
+#define BF_DRI_DEBUG0_SPARE_V(e)                    BF_DRI_DEBUG0_SPARE(BV_DRI_DEBUG0_SPARE__##e)
+#define BFM_DRI_DEBUG0_SPARE_V(v)                   BM_DRI_DEBUG0_SPARE
+#define BP_DRI_DEBUG0_FRAME                         0
+#define BM_DRI_DEBUG0_FRAME                         0x3ffff
+#define BF_DRI_DEBUG0_FRAME(v)                      (((v) & 0x3ffff) << 0)
+#define BFM_DRI_DEBUG0_FRAME(v)                     BM_DRI_DEBUG0_FRAME
+#define BF_DRI_DEBUG0_FRAME_V(e)                    BF_DRI_DEBUG0_FRAME(BV_DRI_DEBUG0_FRAME__##e)
+#define BFM_DRI_DEBUG0_FRAME_V(v)                   BM_DRI_DEBUG0_FRAME
+
+#define HW_DRI_DEBUG1                               HW(DRI_DEBUG1)
+#define HWA_DRI_DEBUG1                              (0x80074000 + 0x50)
+#define HWT_DRI_DEBUG1                              HWIO_32_RW
+#define HWN_DRI_DEBUG1                              DRI_DEBUG1
+#define HWI_DRI_DEBUG1                              
+#define HW_DRI_DEBUG1_SET                           HW(DRI_DEBUG1_SET)
+#define HWA_DRI_DEBUG1_SET                          (HWA_DRI_DEBUG1 + 0x4)
+#define HWT_DRI_DEBUG1_SET                          HWIO_32_WO
+#define HWN_DRI_DEBUG1_SET                          DRI_DEBUG1
+#define HWI_DRI_DEBUG1_SET                          
+#define HW_DRI_DEBUG1_CLR                           HW(DRI_DEBUG1_CLR)
+#define HWA_DRI_DEBUG1_CLR                          (HWA_DRI_DEBUG1 + 0x8)
+#define HWT_DRI_DEBUG1_CLR                          HWIO_32_WO
+#define HWN_DRI_DEBUG1_CLR                          DRI_DEBUG1
+#define HWI_DRI_DEBUG1_CLR                          
+#define HW_DRI_DEBUG1_TOG                           HW(DRI_DEBUG1_TOG)
+#define HWA_DRI_DEBUG1_TOG                          (HWA_DRI_DEBUG1 + 0xc)
+#define HWT_DRI_DEBUG1_TOG                          HWIO_32_WO
+#define HWN_DRI_DEBUG1_TOG                          DRI_DEBUG1
+#define HWI_DRI_DEBUG1_TOG                          
+#define BP_DRI_DEBUG1_INVERT_PILOT                  31
+#define BM_DRI_DEBUG1_INVERT_PILOT                  0x80000000
+#define BV_DRI_DEBUG1_INVERT_PILOT__NORMAL          0x0
+#define BV_DRI_DEBUG1_INVERT_PILOT__INVERTED        0x1
+#define BF_DRI_DEBUG1_INVERT_PILOT(v)               (((v) & 0x1) << 31)
+#define BFM_DRI_DEBUG1_INVERT_PILOT(v)              BM_DRI_DEBUG1_INVERT_PILOT
+#define BF_DRI_DEBUG1_INVERT_PILOT_V(e)             BF_DRI_DEBUG1_INVERT_PILOT(BV_DRI_DEBUG1_INVERT_PILOT__##e)
+#define BFM_DRI_DEBUG1_INVERT_PILOT_V(v)            BM_DRI_DEBUG1_INVERT_PILOT
+#define BP_DRI_DEBUG1_INVERT_ATTENTION              30
+#define BM_DRI_DEBUG1_INVERT_ATTENTION              0x40000000
+#define BV_DRI_DEBUG1_INVERT_ATTENTION__NORMAL      0x0
+#define BV_DRI_DEBUG1_INVERT_ATTENTION__INVERTED    0x1
+#define BF_DRI_DEBUG1_INVERT_ATTENTION(v)           (((v) & 0x1) << 30)
+#define BFM_DRI_DEBUG1_INVERT_ATTENTION(v)          BM_DRI_DEBUG1_INVERT_ATTENTION
+#define BF_DRI_DEBUG1_INVERT_ATTENTION_V(e)         BF_DRI_DEBUG1_INVERT_ATTENTION(BV_DRI_DEBUG1_INVERT_ATTENTION__##e)
+#define BFM_DRI_DEBUG1_INVERT_ATTENTION_V(v)        BM_DRI_DEBUG1_INVERT_ATTENTION
+#define BP_DRI_DEBUG1_INVERT_DRI_DATA               29
+#define BM_DRI_DEBUG1_INVERT_DRI_DATA               0x20000000
+#define BV_DRI_DEBUG1_INVERT_DRI_DATA__NORMAL       0x0
+#define BV_DRI_DEBUG1_INVERT_DRI_DATA__INVERTED     0x1
+#define BF_DRI_DEBUG1_INVERT_DRI_DATA(v)            (((v) & 0x1) << 29)
+#define BFM_DRI_DEBUG1_INVERT_DRI_DATA(v)           BM_DRI_DEBUG1_INVERT_DRI_DATA
+#define BF_DRI_DEBUG1_INVERT_DRI_DATA_V(e)          BF_DRI_DEBUG1_INVERT_DRI_DATA(BV_DRI_DEBUG1_INVERT_DRI_DATA__##e)
+#define BFM_DRI_DEBUG1_INVERT_DRI_DATA_V(v)         BM_DRI_DEBUG1_INVERT_DRI_DATA
+#define BP_DRI_DEBUG1_INVERT_DRI_CLOCK              28
+#define BM_DRI_DEBUG1_INVERT_DRI_CLOCK              0x10000000
+#define BV_DRI_DEBUG1_INVERT_DRI_CLOCK__NORMAL      0x0
+#define BV_DRI_DEBUG1_INVERT_DRI_CLOCK__INVERTED    0x1
+#define BF_DRI_DEBUG1_INVERT_DRI_CLOCK(v)           (((v) & 0x1) << 28)
+#define BFM_DRI_DEBUG1_INVERT_DRI_CLOCK(v)          BM_DRI_DEBUG1_INVERT_DRI_CLOCK
+#define BF_DRI_DEBUG1_INVERT_DRI_CLOCK_V(e)         BF_DRI_DEBUG1_INVERT_DRI_CLOCK(BV_DRI_DEBUG1_INVERT_DRI_CLOCK__##e)
+#define BFM_DRI_DEBUG1_INVERT_DRI_CLOCK_V(v)        BM_DRI_DEBUG1_INVERT_DRI_CLOCK
+#define BP_DRI_DEBUG1_REVERSE_FRAME                 27
+#define BM_DRI_DEBUG1_REVERSE_FRAME                 0x8000000
+#define BV_DRI_DEBUG1_REVERSE_FRAME__NORMAL         0x0
+#define BV_DRI_DEBUG1_REVERSE_FRAME__REVERSED       0x1
+#define BF_DRI_DEBUG1_REVERSE_FRAME(v)              (((v) & 0x1) << 27)
+#define BFM_DRI_DEBUG1_REVERSE_FRAME(v)             BM_DRI_DEBUG1_REVERSE_FRAME
+#define BF_DRI_DEBUG1_REVERSE_FRAME_V(e)            BF_DRI_DEBUG1_REVERSE_FRAME(BV_DRI_DEBUG1_REVERSE_FRAME__##e)
+#define BFM_DRI_DEBUG1_REVERSE_FRAME_V(v)           BM_DRI_DEBUG1_REVERSE_FRAME
+#define BP_DRI_DEBUG1_SWIZZLED_FRAME                0
+#define BM_DRI_DEBUG1_SWIZZLED_FRAME                0x3ffff
+#define BF_DRI_DEBUG1_SWIZZLED_FRAME(v)             (((v) & 0x3ffff) << 0)
+#define BFM_DRI_DEBUG1_SWIZZLED_FRAME(v)            BM_DRI_DEBUG1_SWIZZLED_FRAME
+#define BF_DRI_DEBUG1_SWIZZLED_FRAME_V(e)           BF_DRI_DEBUG1_SWIZZLED_FRAME(BV_DRI_DEBUG1_SWIZZLED_FRAME__##e)
+#define BFM_DRI_DEBUG1_SWIZZLED_FRAME_V(v)          BM_DRI_DEBUG1_SWIZZLED_FRAME
+
+#endif /* __HEADERGEN_STMP3600_DRI_H__*/
diff --git a/firmware/target/arm/imx233/regs/stmp3600/emi.h b/firmware/target/arm/imx233/regs/stmp3600/emi.h
new file mode 100644
index 0000000000..d0dde33336
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3600/emi.h
@@ -0,0 +1,472 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * stmp3600 version: 2.4.0
+ * stmp3600 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_STMP3600_EMI_H__
+#define __HEADERGEN_STMP3600_EMI_H__
+
+#define HW_EMI_CTRL                     HW(EMI_CTRL)
+#define HWA_EMI_CTRL                    (0x80020000 + 0x0)
+#define HWT_EMI_CTRL                    HWIO_32_RW
+#define HWN_EMI_CTRL                    EMI_CTRL
+#define HWI_EMI_CTRL                    
+#define HW_EMI_CTRL_SET                 HW(EMI_CTRL_SET)
+#define HWA_EMI_CTRL_SET                (HWA_EMI_CTRL + 0x4)
+#define HWT_EMI_CTRL_SET                HWIO_32_WO
+#define HWN_EMI_CTRL_SET                EMI_CTRL
+#define HWI_EMI_CTRL_SET                
+#define HW_EMI_CTRL_CLR                 HW(EMI_CTRL_CLR)
+#define HWA_EMI_CTRL_CLR                (HWA_EMI_CTRL + 0x8)
+#define HWT_EMI_CTRL_CLR                HWIO_32_WO
+#define HWN_EMI_CTRL_CLR                EMI_CTRL
+#define HWI_EMI_CTRL_CLR                
+#define HW_EMI_CTRL_TOG                 HW(EMI_CTRL_TOG)
+#define HWA_EMI_CTRL_TOG                (HWA_EMI_CTRL + 0xc)
+#define HWT_EMI_CTRL_TOG                HWIO_32_WO
+#define HWN_EMI_CTRL_TOG                EMI_CTRL
+#define HWI_EMI_CTRL_TOG                
+#define BP_EMI_CTRL_SFTRST              31
+#define BM_EMI_CTRL_SFTRST              0x80000000
+#define BF_EMI_CTRL_SFTRST(v)           (((v) & 0x1) << 31)
+#define BFM_EMI_CTRL_SFTRST(v)          BM_EMI_CTRL_SFTRST
+#define BF_EMI_CTRL_SFTRST_V(e)         BF_EMI_CTRL_SFTRST(BV_EMI_CTRL_SFTRST__##e)
+#define BFM_EMI_CTRL_SFTRST_V(v)        BM_EMI_CTRL_SFTRST
+#define BP_EMI_CTRL_CLKGATE             30
+#define BM_EMI_CTRL_CLKGATE             0x40000000
+#define BF_EMI_CTRL_CLKGATE(v)          (((v) & 0x1) << 30)
+#define BFM_EMI_CTRL_CLKGATE(v)         BM_EMI_CTRL_CLKGATE
+#define BF_EMI_CTRL_CLKGATE_V(e)        BF_EMI_CTRL_CLKGATE(BV_EMI_CTRL_CLKGATE__##e)
+#define BFM_EMI_CTRL_CLKGATE_V(v)       BM_EMI_CTRL_CLKGATE
+#define BP_EMI_CTRL_CE3_MODE            3
+#define BM_EMI_CTRL_CE3_MODE            0x8
+#define BV_EMI_CTRL_CE3_MODE__STATIC    0x0
+#define BV_EMI_CTRL_CE3_MODE__DRAM      0x1
+#define BF_EMI_CTRL_CE3_MODE(v)         (((v) & 0x1) << 3)
+#define BFM_EMI_CTRL_CE3_MODE(v)        BM_EMI_CTRL_CE3_MODE
+#define BF_EMI_CTRL_CE3_MODE_V(e)       BF_EMI_CTRL_CE3_MODE(BV_EMI_CTRL_CE3_MODE__##e)
+#define BFM_EMI_CTRL_CE3_MODE_V(v)      BM_EMI_CTRL_CE3_MODE
+#define BP_EMI_CTRL_CE2_MODE            2
+#define BM_EMI_CTRL_CE2_MODE            0x4
+#define BV_EMI_CTRL_CE2_MODE__STATIC    0x0
+#define BV_EMI_CTRL_CE2_MODE__DRAM      0x1
+#define BF_EMI_CTRL_CE2_MODE(v)         (((v) & 0x1) << 2)
+#define BFM_EMI_CTRL_CE2_MODE(v)        BM_EMI_CTRL_CE2_MODE
+#define BF_EMI_CTRL_CE2_MODE_V(e)       BF_EMI_CTRL_CE2_MODE(BV_EMI_CTRL_CE2_MODE__##e)
+#define BFM_EMI_CTRL_CE2_MODE_V(v)      BM_EMI_CTRL_CE2_MODE
+#define BP_EMI_CTRL_CE1_MODE            1
+#define BM_EMI_CTRL_CE1_MODE            0x2
+#define BV_EMI_CTRL_CE1_MODE__STATIC    0x0
+#define BV_EMI_CTRL_CE1_MODE__DRAM      0x1
+#define BF_EMI_CTRL_CE1_MODE(v)         (((v) & 0x1) << 1)
+#define BFM_EMI_CTRL_CE1_MODE(v)        BM_EMI_CTRL_CE1_MODE
+#define BF_EMI_CTRL_CE1_MODE_V(e)       BF_EMI_CTRL_CE1_MODE(BV_EMI_CTRL_CE1_MODE__##e)
+#define BFM_EMI_CTRL_CE1_MODE_V(v)      BM_EMI_CTRL_CE1_MODE
+#define BP_EMI_CTRL_CE0_MODE            0
+#define BM_EMI_CTRL_CE0_MODE            0x1
+#define BV_EMI_CTRL_CE0_MODE__STATIC    0x0
+#define BV_EMI_CTRL_CE0_MODE__DRAM      0x1
+#define BF_EMI_CTRL_CE0_MODE(v)         (((v) & 0x1) << 0)
+#define BFM_EMI_CTRL_CE0_MODE(v)        BM_EMI_CTRL_CE0_MODE
+#define BF_EMI_CTRL_CE0_MODE_V(e)       BF_EMI_CTRL_CE0_MODE(BV_EMI_CTRL_CE0_MODE__##e)
+#define BFM_EMI_CTRL_CE0_MODE_V(v)      BM_EMI_CTRL_CE0_MODE
+
+#define HW_EMI_STAT                                 HW(EMI_STAT)
+#define HWA_EMI_STAT                                (0x80020000 + 0x10)
+#define HWT_EMI_STAT                                HWIO_32_RW
+#define HWN_EMI_STAT                                EMI_STAT
+#define HWI_EMI_STAT                                
+#define BP_EMI_STAT_DRAM_PRESENT                    31
+#define BM_EMI_STAT_DRAM_PRESENT                    0x80000000
+#define BF_EMI_STAT_DRAM_PRESENT(v)                 (((v) & 0x1) << 31)
+#define BFM_EMI_STAT_DRAM_PRESENT(v)                BM_EMI_STAT_DRAM_PRESENT
+#define BF_EMI_STAT_DRAM_PRESENT_V(e)               BF_EMI_STAT_DRAM_PRESENT(BV_EMI_STAT_DRAM_PRESENT__##e)
+#define BFM_EMI_STAT_DRAM_PRESENT_V(v)              BM_EMI_STAT_DRAM_PRESENT
+#define BP_EMI_STAT_STATIC_PRESENT                  30
+#define BM_EMI_STAT_STATIC_PRESENT                  0x40000000
+#define BF_EMI_STAT_STATIC_PRESENT(v)               (((v) & 0x1) << 30)
+#define BFM_EMI_STAT_STATIC_PRESENT(v)              BM_EMI_STAT_STATIC_PRESENT
+#define BF_EMI_STAT_STATIC_PRESENT_V(e)             BF_EMI_STAT_STATIC_PRESENT(BV_EMI_STAT_STATIC_PRESENT__##e)
+#define BFM_EMI_STAT_STATIC_PRESENT_V(v)            BM_EMI_STAT_STATIC_PRESENT
+#define BP_EMI_STAT_LARGE_DRAM_ENABLED              29
+#define BM_EMI_STAT_LARGE_DRAM_ENABLED              0x20000000
+#define BF_EMI_STAT_LARGE_DRAM_ENABLED(v)           (((v) & 0x1) << 29)
+#define BFM_EMI_STAT_LARGE_DRAM_ENABLED(v)          BM_EMI_STAT_LARGE_DRAM_ENABLED
+#define BF_EMI_STAT_LARGE_DRAM_ENABLED_V(e)         BF_EMI_STAT_LARGE_DRAM_ENABLED(BV_EMI_STAT_LARGE_DRAM_ENABLED__##e)
+#define BFM_EMI_STAT_LARGE_DRAM_ENABLED_V(v)        BM_EMI_STAT_LARGE_DRAM_ENABLED
+#define BP_EMI_STAT_WRITE_BUFFER_DATA               1
+#define BM_EMI_STAT_WRITE_BUFFER_DATA               0x2
+#define BV_EMI_STAT_WRITE_BUFFER_DATA__EMPTY        0x0
+#define BV_EMI_STAT_WRITE_BUFFER_DATA__NOT_EMPTY    0x1
+#define BF_EMI_STAT_WRITE_BUFFER_DATA(v)            (((v) & 0x1) << 1)
+#define BFM_EMI_STAT_WRITE_BUFFER_DATA(v)           BM_EMI_STAT_WRITE_BUFFER_DATA
+#define BF_EMI_STAT_WRITE_BUFFER_DATA_V(e)          BF_EMI_STAT_WRITE_BUFFER_DATA(BV_EMI_STAT_WRITE_BUFFER_DATA__##e)
+#define BFM_EMI_STAT_WRITE_BUFFER_DATA_V(v)         BM_EMI_STAT_WRITE_BUFFER_DATA
+#define BP_EMI_STAT_BUSY                            0
+#define BM_EMI_STAT_BUSY                            0x1
+#define BV_EMI_STAT_BUSY__NOT_BUSY                  0x0
+#define BV_EMI_STAT_BUSY__BUSY                      0x1
+#define BF_EMI_STAT_BUSY(v)                         (((v) & 0x1) << 0)
+#define BFM_EMI_STAT_BUSY(v)                        BM_EMI_STAT_BUSY
+#define BF_EMI_STAT_BUSY_V(e)                       BF_EMI_STAT_BUSY(BV_EMI_STAT_BUSY__##e)
+#define BFM_EMI_STAT_BUSY_V(v)                      BM_EMI_STAT_BUSY
+
+#define HW_EMI_DEBUG                    HW(EMI_DEBUG)
+#define HWA_EMI_DEBUG                   (0x80020000 + 0x20)
+#define HWT_EMI_DEBUG                   HWIO_32_RW
+#define HWN_EMI_DEBUG                   EMI_DEBUG
+#define HWI_EMI_DEBUG                   
+#define BP_EMI_DEBUG_STATIC_STATE       16
+#define BM_EMI_DEBUG_STATIC_STATE       0x70000
+#define BF_EMI_DEBUG_STATIC_STATE(v)    (((v) & 0x7) << 16)
+#define BFM_EMI_DEBUG_STATIC_STATE(v)   BM_EMI_DEBUG_STATIC_STATE
+#define BF_EMI_DEBUG_STATIC_STATE_V(e)  BF_EMI_DEBUG_STATIC_STATE(BV_EMI_DEBUG_STATIC_STATE__##e)
+#define BFM_EMI_DEBUG_STATIC_STATE_V(v) BM_EMI_DEBUG_STATIC_STATE
+#define BP_EMI_DEBUG_DRAM_STATE         0
+#define BM_EMI_DEBUG_DRAM_STATE         0x1f
+#define BF_EMI_DEBUG_DRAM_STATE(v)      (((v) & 0x1f) << 0)
+#define BFM_EMI_DEBUG_DRAM_STATE(v)     BM_EMI_DEBUG_DRAM_STATE
+#define BF_EMI_DEBUG_DRAM_STATE_V(e)    BF_EMI_DEBUG_DRAM_STATE(BV_EMI_DEBUG_DRAM_STATE__##e)
+#define BFM_EMI_DEBUG_DRAM_STATE_V(v)   BM_EMI_DEBUG_DRAM_STATE
+
+#define HW_EMI_DRAMSTAT                         HW(EMI_DRAMSTAT)
+#define HWA_EMI_DRAMSTAT                        (0x80020000 + 0x80)
+#define HWT_EMI_DRAMSTAT                        HWIO_32_RW
+#define HWN_EMI_DRAMSTAT                        EMI_DRAMSTAT
+#define HWI_EMI_DRAMSTAT                        
+#define BP_EMI_DRAMSTAT_SELF_REFRESH_ACK        2
+#define BM_EMI_DRAMSTAT_SELF_REFRESH_ACK        0x4
+#define BF_EMI_DRAMSTAT_SELF_REFRESH_ACK(v)     (((v) & 0x1) << 2)
+#define BFM_EMI_DRAMSTAT_SELF_REFRESH_ACK(v)    BM_EMI_DRAMSTAT_SELF_REFRESH_ACK
+#define BF_EMI_DRAMSTAT_SELF_REFRESH_ACK_V(e)   BF_EMI_DRAMSTAT_SELF_REFRESH_ACK(BV_EMI_DRAMSTAT_SELF_REFRESH_ACK__##e)
+#define BFM_EMI_DRAMSTAT_SELF_REFRESH_ACK_V(v)  BM_EMI_DRAMSTAT_SELF_REFRESH_ACK
+#define BP_EMI_DRAMSTAT_BUSY                    1
+#define BM_EMI_DRAMSTAT_BUSY                    0x2
+#define BF_EMI_DRAMSTAT_BUSY(v)                 (((v) & 0x1) << 1)
+#define BFM_EMI_DRAMSTAT_BUSY(v)                BM_EMI_DRAMSTAT_BUSY
+#define BF_EMI_DRAMSTAT_BUSY_V(e)               BF_EMI_DRAMSTAT_BUSY(BV_EMI_DRAMSTAT_BUSY__##e)
+#define BFM_EMI_DRAMSTAT_BUSY_V(v)              BM_EMI_DRAMSTAT_BUSY
+#define BP_EMI_DRAMSTAT_READY                   0
+#define BM_EMI_DRAMSTAT_READY                   0x1
+#define BF_EMI_DRAMSTAT_READY(v)                (((v) & 0x1) << 0)
+#define BFM_EMI_DRAMSTAT_READY(v)               BM_EMI_DRAMSTAT_READY
+#define BF_EMI_DRAMSTAT_READY_V(e)              BF_EMI_DRAMSTAT_READY(BV_EMI_DRAMSTAT_READY__##e)
+#define BFM_EMI_DRAMSTAT_READY_V(v)             BM_EMI_DRAMSTAT_READY
+
+#define HW_EMI_DRAMCTRL                         HW(EMI_DRAMCTRL)
+#define HWA_EMI_DRAMCTRL                        (0x80020000 + 0x90)
+#define HWT_EMI_DRAMCTRL                        HWIO_32_RW
+#define HWN_EMI_DRAMCTRL                        EMI_DRAMCTRL
+#define HWI_EMI_DRAMCTRL                        
+#define HW_EMI_DRAMCTRL_SET                     HW(EMI_DRAMCTRL_SET)
+#define HWA_EMI_DRAMCTRL_SET                    (HWA_EMI_DRAMCTRL + 0x4)
+#define HWT_EMI_DRAMCTRL_SET                    HWIO_32_WO
+#define HWN_EMI_DRAMCTRL_SET                    EMI_DRAMCTRL
+#define HWI_EMI_DRAMCTRL_SET                    
+#define HW_EMI_DRAMCTRL_CLR                     HW(EMI_DRAMCTRL_CLR)
+#define HWA_EMI_DRAMCTRL_CLR                    (HWA_EMI_DRAMCTRL + 0x8)
+#define HWT_EMI_DRAMCTRL_CLR                    HWIO_32_WO
+#define HWN_EMI_DRAMCTRL_CLR                    EMI_DRAMCTRL
+#define HWI_EMI_DRAMCTRL_CLR                    
+#define HW_EMI_DRAMCTRL_TOG                     HW(EMI_DRAMCTRL_TOG)
+#define HWA_EMI_DRAMCTRL_TOG                    (HWA_EMI_DRAMCTRL + 0xc)
+#define HWT_EMI_DRAMCTRL_TOG                    HWIO_32_WO
+#define HWN_EMI_DRAMCTRL_TOG                    EMI_DRAMCTRL
+#define HWI_EMI_DRAMCTRL_TOG                    
+#define BP_EMI_DRAMCTRL_EMICLK_DIVIDE           24
+#define BM_EMI_DRAMCTRL_EMICLK_DIVIDE           0x7000000
+#define BF_EMI_DRAMCTRL_EMICLK_DIVIDE(v)        (((v) & 0x7) << 24)
+#define BFM_EMI_DRAMCTRL_EMICLK_DIVIDE(v)       BM_EMI_DRAMCTRL_EMICLK_DIVIDE
+#define BF_EMI_DRAMCTRL_EMICLK_DIVIDE_V(e)      BF_EMI_DRAMCTRL_EMICLK_DIVIDE(BV_EMI_DRAMCTRL_EMICLK_DIVIDE__##e)
+#define BFM_EMI_DRAMCTRL_EMICLK_DIVIDE_V(v)     BM_EMI_DRAMCTRL_EMICLK_DIVIDE
+#define BP_EMI_DRAMCTRL_AUTO_EMICLK_GATE        23
+#define BM_EMI_DRAMCTRL_AUTO_EMICLK_GATE        0x800000
+#define BF_EMI_DRAMCTRL_AUTO_EMICLK_GATE(v)     (((v) & 0x1) << 23)
+#define BFM_EMI_DRAMCTRL_AUTO_EMICLK_GATE(v)    BM_EMI_DRAMCTRL_AUTO_EMICLK_GATE
+#define BF_EMI_DRAMCTRL_AUTO_EMICLK_GATE_V(e)   BF_EMI_DRAMCTRL_AUTO_EMICLK_GATE(BV_EMI_DRAMCTRL_AUTO_EMICLK_GATE__##e)
+#define BFM_EMI_DRAMCTRL_AUTO_EMICLK_GATE_V(v)  BM_EMI_DRAMCTRL_AUTO_EMICLK_GATE
+#define BP_EMI_DRAMCTRL_EMICLK_ENABLE           21
+#define BM_EMI_DRAMCTRL_EMICLK_ENABLE           0x200000
+#define BF_EMI_DRAMCTRL_EMICLK_ENABLE(v)        (((v) & 0x1) << 21)
+#define BFM_EMI_DRAMCTRL_EMICLK_ENABLE(v)       BM_EMI_DRAMCTRL_EMICLK_ENABLE
+#define BF_EMI_DRAMCTRL_EMICLK_ENABLE_V(e)      BF_EMI_DRAMCTRL_EMICLK_ENABLE(BV_EMI_DRAMCTRL_EMICLK_ENABLE__##e)
+#define BFM_EMI_DRAMCTRL_EMICLK_ENABLE_V(v)     BM_EMI_DRAMCTRL_EMICLK_ENABLE
+#define BP_EMI_DRAMCTRL_EMICLKEN_ENABLE         20
+#define BM_EMI_DRAMCTRL_EMICLKEN_ENABLE         0x100000
+#define BF_EMI_DRAMCTRL_EMICLKEN_ENABLE(v)      (((v) & 0x1) << 20)
+#define BFM_EMI_DRAMCTRL_EMICLKEN_ENABLE(v)     BM_EMI_DRAMCTRL_EMICLKEN_ENABLE
+#define BF_EMI_DRAMCTRL_EMICLKEN_ENABLE_V(e)    BF_EMI_DRAMCTRL_EMICLKEN_ENABLE(BV_EMI_DRAMCTRL_EMICLKEN_ENABLE__##e)
+#define BFM_EMI_DRAMCTRL_EMICLKEN_ENABLE_V(v)   BM_EMI_DRAMCTRL_EMICLKEN_ENABLE
+#define BP_EMI_DRAMCTRL_DRAM_TYPE               16
+#define BM_EMI_DRAMCTRL_DRAM_TYPE               0xf0000
+#define BF_EMI_DRAMCTRL_DRAM_TYPE(v)            (((v) & 0xf) << 16)
+#define BFM_EMI_DRAMCTRL_DRAM_TYPE(v)           BM_EMI_DRAMCTRL_DRAM_TYPE
+#define BF_EMI_DRAMCTRL_DRAM_TYPE_V(e)          BF_EMI_DRAMCTRL_DRAM_TYPE(BV_EMI_DRAMCTRL_DRAM_TYPE__##e)
+#define BFM_EMI_DRAMCTRL_DRAM_TYPE_V(v)         BM_EMI_DRAMCTRL_DRAM_TYPE
+#define BP_EMI_DRAMCTRL_PRECHARGE               2
+#define BM_EMI_DRAMCTRL_PRECHARGE               0x4
+#define BF_EMI_DRAMCTRL_PRECHARGE(v)            (((v) & 0x1) << 2)
+#define BFM_EMI_DRAMCTRL_PRECHARGE(v)           BM_EMI_DRAMCTRL_PRECHARGE
+#define BF_EMI_DRAMCTRL_PRECHARGE_V(e)          BF_EMI_DRAMCTRL_PRECHARGE(BV_EMI_DRAMCTRL_PRECHARGE__##e)
+#define BFM_EMI_DRAMCTRL_PRECHARGE_V(v)         BM_EMI_DRAMCTRL_PRECHARGE
+#define BP_EMI_DRAMCTRL_SELF_REFRESH            1
+#define BM_EMI_DRAMCTRL_SELF_REFRESH            0x2
+#define BF_EMI_DRAMCTRL_SELF_REFRESH(v)         (((v) & 0x1) << 1)
+#define BFM_EMI_DRAMCTRL_SELF_REFRESH(v)        BM_EMI_DRAMCTRL_SELF_REFRESH
+#define BF_EMI_DRAMCTRL_SELF_REFRESH_V(e)       BF_EMI_DRAMCTRL_SELF_REFRESH(BV_EMI_DRAMCTRL_SELF_REFRESH__##e)
+#define BFM_EMI_DRAMCTRL_SELF_REFRESH_V(v)      BM_EMI_DRAMCTRL_SELF_REFRESH
+
+#define HW_EMI_DRAMADDR                     HW(EMI_DRAMADDR)
+#define HWA_EMI_DRAMADDR                    (0x80020000 + 0xa0)
+#define HWT_EMI_DRAMADDR                    HWIO_32_RW
+#define HWN_EMI_DRAMADDR                    EMI_DRAMADDR
+#define HWI_EMI_DRAMADDR                    
+#define HW_EMI_DRAMADDR_SET                 HW(EMI_DRAMADDR_SET)
+#define HWA_EMI_DRAMADDR_SET                (HWA_EMI_DRAMADDR + 0x4)
+#define HWT_EMI_DRAMADDR_SET                HWIO_32_WO
+#define HWN_EMI_DRAMADDR_SET                EMI_DRAMADDR
+#define HWI_EMI_DRAMADDR_SET                
+#define HW_EMI_DRAMADDR_CLR                 HW(EMI_DRAMADDR_CLR)
+#define HWA_EMI_DRAMADDR_CLR                (HWA_EMI_DRAMADDR + 0x8)
+#define HWT_EMI_DRAMADDR_CLR                HWIO_32_WO
+#define HWN_EMI_DRAMADDR_CLR                EMI_DRAMADDR
+#define HWI_EMI_DRAMADDR_CLR                
+#define HW_EMI_DRAMADDR_TOG                 HW(EMI_DRAMADDR_TOG)
+#define HWA_EMI_DRAMADDR_TOG                (HWA_EMI_DRAMADDR + 0xc)
+#define HWT_EMI_DRAMADDR_TOG                HWIO_32_WO
+#define HWN_EMI_DRAMADDR_TOG                EMI_DRAMADDR
+#define HWI_EMI_DRAMADDR_TOG                
+#define BP_EMI_DRAMADDR_MODE                8
+#define BM_EMI_DRAMADDR_MODE                0x100
+#define BV_EMI_DRAMADDR_MODE__RBC           0x0
+#define BV_EMI_DRAMADDR_MODE__BRC           0x1
+#define BF_EMI_DRAMADDR_MODE(v)             (((v) & 0x1) << 8)
+#define BFM_EMI_DRAMADDR_MODE(v)            BM_EMI_DRAMADDR_MODE
+#define BF_EMI_DRAMADDR_MODE_V(e)           BF_EMI_DRAMADDR_MODE(BV_EMI_DRAMADDR_MODE__##e)
+#define BFM_EMI_DRAMADDR_MODE_V(v)          BM_EMI_DRAMADDR_MODE
+#define BP_EMI_DRAMADDR_ROW_BITS            4
+#define BM_EMI_DRAMADDR_ROW_BITS            0xf0
+#define BF_EMI_DRAMADDR_ROW_BITS(v)         (((v) & 0xf) << 4)
+#define BFM_EMI_DRAMADDR_ROW_BITS(v)        BM_EMI_DRAMADDR_ROW_BITS
+#define BF_EMI_DRAMADDR_ROW_BITS_V(e)       BF_EMI_DRAMADDR_ROW_BITS(BV_EMI_DRAMADDR_ROW_BITS__##e)
+#define BFM_EMI_DRAMADDR_ROW_BITS_V(v)      BM_EMI_DRAMADDR_ROW_BITS
+#define BP_EMI_DRAMADDR_COLUMN_BITS         0
+#define BM_EMI_DRAMADDR_COLUMN_BITS         0xf
+#define BF_EMI_DRAMADDR_COLUMN_BITS(v)      (((v) & 0xf) << 0)
+#define BFM_EMI_DRAMADDR_COLUMN_BITS(v)     BM_EMI_DRAMADDR_COLUMN_BITS
+#define BF_EMI_DRAMADDR_COLUMN_BITS_V(e)    BF_EMI_DRAMADDR_COLUMN_BITS(BV_EMI_DRAMADDR_COLUMN_BITS__##e)
+#define BFM_EMI_DRAMADDR_COLUMN_BITS_V(v)   BM_EMI_DRAMADDR_COLUMN_BITS
+
+#define HW_EMI_DRAMMODE                         HW(EMI_DRAMMODE)
+#define HWA_EMI_DRAMMODE                        (0x80020000 + 0xb0)
+#define HWT_EMI_DRAMMODE                        HWIO_32_RW
+#define HWN_EMI_DRAMMODE                        EMI_DRAMMODE
+#define HWI_EMI_DRAMMODE                        
+#define BP_EMI_DRAMMODE_CAS_LATENCY             4
+#define BM_EMI_DRAMMODE_CAS_LATENCY             0x70
+#define BV_EMI_DRAMMODE_CAS_LATENCY__RESERVED0  0x0
+#define BV_EMI_DRAMMODE_CAS_LATENCY__RESERVED1  0x1
+#define BV_EMI_DRAMMODE_CAS_LATENCY__CAS2       0x2
+#define BV_EMI_DRAMMODE_CAS_LATENCY__CAS3       0x3
+#define BV_EMI_DRAMMODE_CAS_LATENCY__RESERVED4  0x4
+#define BV_EMI_DRAMMODE_CAS_LATENCY__RESERVED5  0x5
+#define BV_EMI_DRAMMODE_CAS_LATENCY__RESERVED6  0x6
+#define BV_EMI_DRAMMODE_CAS_LATENCY__RESERVED7  0x7
+#define BF_EMI_DRAMMODE_CAS_LATENCY(v)          (((v) & 0x7) << 4)
+#define BFM_EMI_DRAMMODE_CAS_LATENCY(v)         BM_EMI_DRAMMODE_CAS_LATENCY
+#define BF_EMI_DRAMMODE_CAS_LATENCY_V(e)        BF_EMI_DRAMMODE_CAS_LATENCY(BV_EMI_DRAMMODE_CAS_LATENCY__##e)
+#define BFM_EMI_DRAMMODE_CAS_LATENCY_V(v)       BM_EMI_DRAMMODE_CAS_LATENCY
+
+#define HW_EMI_DRAMTIME                         HW(EMI_DRAMTIME)
+#define HWA_EMI_DRAMTIME                        (0x80020000 + 0xc0)
+#define HWT_EMI_DRAMTIME                        HWIO_32_RW
+#define HWN_EMI_DRAMTIME                        EMI_DRAMTIME
+#define HWI_EMI_DRAMTIME                        
+#define HW_EMI_DRAMTIME_SET                     HW(EMI_DRAMTIME_SET)
+#define HWA_EMI_DRAMTIME_SET                    (HWA_EMI_DRAMTIME + 0x4)
+#define HWT_EMI_DRAMTIME_SET                    HWIO_32_WO
+#define HWN_EMI_DRAMTIME_SET                    EMI_DRAMTIME
+#define HWI_EMI_DRAMTIME_SET                    
+#define HW_EMI_DRAMTIME_CLR                     HW(EMI_DRAMTIME_CLR)
+#define HWA_EMI_DRAMTIME_CLR                    (HWA_EMI_DRAMTIME + 0x8)
+#define HWT_EMI_DRAMTIME_CLR                    HWIO_32_WO
+#define HWN_EMI_DRAMTIME_CLR                    EMI_DRAMTIME
+#define HWI_EMI_DRAMTIME_CLR                    
+#define HW_EMI_DRAMTIME_TOG                     HW(EMI_DRAMTIME_TOG)
+#define HWA_EMI_DRAMTIME_TOG                    (HWA_EMI_DRAMTIME + 0xc)
+#define HWT_EMI_DRAMTIME_TOG                    HWIO_32_WO
+#define HWN_EMI_DRAMTIME_TOG                    EMI_DRAMTIME
+#define HWI_EMI_DRAMTIME_TOG                    
+#define BP_EMI_DRAMTIME_TRFC                    24
+#define BM_EMI_DRAMTIME_TRFC                    0xf000000
+#define BF_EMI_DRAMTIME_TRFC(v)                 (((v) & 0xf) << 24)
+#define BFM_EMI_DRAMTIME_TRFC(v)                BM_EMI_DRAMTIME_TRFC
+#define BF_EMI_DRAMTIME_TRFC_V(e)               BF_EMI_DRAMTIME_TRFC(BV_EMI_DRAMTIME_TRFC__##e)
+#define BFM_EMI_DRAMTIME_TRFC_V(v)              BM_EMI_DRAMTIME_TRFC
+#define BP_EMI_DRAMTIME_TRC                     20
+#define BM_EMI_DRAMTIME_TRC                     0xf00000
+#define BF_EMI_DRAMTIME_TRC(v)                  (((v) & 0xf) << 20)
+#define BFM_EMI_DRAMTIME_TRC(v)                 BM_EMI_DRAMTIME_TRC
+#define BF_EMI_DRAMTIME_TRC_V(e)                BF_EMI_DRAMTIME_TRC(BV_EMI_DRAMTIME_TRC__##e)
+#define BFM_EMI_DRAMTIME_TRC_V(v)               BM_EMI_DRAMTIME_TRC
+#define BP_EMI_DRAMTIME_TRAS                    16
+#define BM_EMI_DRAMTIME_TRAS                    0xf0000
+#define BF_EMI_DRAMTIME_TRAS(v)                 (((v) & 0xf) << 16)
+#define BFM_EMI_DRAMTIME_TRAS(v)                BM_EMI_DRAMTIME_TRAS
+#define BF_EMI_DRAMTIME_TRAS_V(e)               BF_EMI_DRAMTIME_TRAS(BV_EMI_DRAMTIME_TRAS__##e)
+#define BFM_EMI_DRAMTIME_TRAS_V(v)              BM_EMI_DRAMTIME_TRAS
+#define BP_EMI_DRAMTIME_TRCD                    12
+#define BM_EMI_DRAMTIME_TRCD                    0xf000
+#define BF_EMI_DRAMTIME_TRCD(v)                 (((v) & 0xf) << 12)
+#define BFM_EMI_DRAMTIME_TRCD(v)                BM_EMI_DRAMTIME_TRCD
+#define BF_EMI_DRAMTIME_TRCD_V(e)               BF_EMI_DRAMTIME_TRCD(BV_EMI_DRAMTIME_TRCD__##e)
+#define BFM_EMI_DRAMTIME_TRCD_V(v)              BM_EMI_DRAMTIME_TRCD
+#define BP_EMI_DRAMTIME_TRP                     8
+#define BM_EMI_DRAMTIME_TRP                     0x300
+#define BF_EMI_DRAMTIME_TRP(v)                  (((v) & 0x3) << 8)
+#define BFM_EMI_DRAMTIME_TRP(v)                 BM_EMI_DRAMTIME_TRP
+#define BF_EMI_DRAMTIME_TRP_V(e)                BF_EMI_DRAMTIME_TRP(BV_EMI_DRAMTIME_TRP__##e)
+#define BFM_EMI_DRAMTIME_TRP_V(v)               BM_EMI_DRAMTIME_TRP
+#define BP_EMI_DRAMTIME_TXSR                    4
+#define BM_EMI_DRAMTIME_TXSR                    0xf0
+#define BF_EMI_DRAMTIME_TXSR(v)                 (((v) & 0xf) << 4)
+#define BFM_EMI_DRAMTIME_TXSR(v)                BM_EMI_DRAMTIME_TXSR
+#define BF_EMI_DRAMTIME_TXSR_V(e)               BF_EMI_DRAMTIME_TXSR(BV_EMI_DRAMTIME_TXSR__##e)
+#define BFM_EMI_DRAMTIME_TXSR_V(v)              BM_EMI_DRAMTIME_TXSR
+#define BP_EMI_DRAMTIME_REFRESH_COUNTER         0
+#define BM_EMI_DRAMTIME_REFRESH_COUNTER         0xf
+#define BF_EMI_DRAMTIME_REFRESH_COUNTER(v)      (((v) & 0xf) << 0)
+#define BFM_EMI_DRAMTIME_REFRESH_COUNTER(v)     BM_EMI_DRAMTIME_REFRESH_COUNTER
+#define BF_EMI_DRAMTIME_REFRESH_COUNTER_V(e)    BF_EMI_DRAMTIME_REFRESH_COUNTER(BV_EMI_DRAMTIME_REFRESH_COUNTER__##e)
+#define BFM_EMI_DRAMTIME_REFRESH_COUNTER_V(v)   BM_EMI_DRAMTIME_REFRESH_COUNTER
+
+#define HW_EMI_DRAMTIME2                        HW(EMI_DRAMTIME2)
+#define HWA_EMI_DRAMTIME2                       (0x80020000 + 0xd0)
+#define HWT_EMI_DRAMTIME2                       HWIO_32_RW
+#define HWN_EMI_DRAMTIME2                       EMI_DRAMTIME2
+#define HWI_EMI_DRAMTIME2                       
+#define HW_EMI_DRAMTIME2_SET                    HW(EMI_DRAMTIME2_SET)
+#define HWA_EMI_DRAMTIME2_SET                   (HWA_EMI_DRAMTIME2 + 0x4)
+#define HWT_EMI_DRAMTIME2_SET                   HWIO_32_WO
+#define HWN_EMI_DRAMTIME2_SET                   EMI_DRAMTIME2
+#define HWI_EMI_DRAMTIME2_SET                   
+#define HW_EMI_DRAMTIME2_CLR                    HW(EMI_DRAMTIME2_CLR)
+#define HWA_EMI_DRAMTIME2_CLR                   (HWA_EMI_DRAMTIME2 + 0x8)
+#define HWT_EMI_DRAMTIME2_CLR                   HWIO_32_WO
+#define HWN_EMI_DRAMTIME2_CLR                   EMI_DRAMTIME2
+#define HWI_EMI_DRAMTIME2_CLR                   
+#define HW_EMI_DRAMTIME2_TOG                    HW(EMI_DRAMTIME2_TOG)
+#define HWA_EMI_DRAMTIME2_TOG                   (HWA_EMI_DRAMTIME2 + 0xc)
+#define HWT_EMI_DRAMTIME2_TOG                   HWIO_32_WO
+#define HWN_EMI_DRAMTIME2_TOG                   EMI_DRAMTIME2
+#define HWI_EMI_DRAMTIME2_TOG                   
+#define BP_EMI_DRAMTIME2_PRECHARGE_COUNT        0
+#define BM_EMI_DRAMTIME2_PRECHARGE_COUNT        0xffff
+#define BF_EMI_DRAMTIME2_PRECHARGE_COUNT(v)     (((v) & 0xffff) << 0)
+#define BFM_EMI_DRAMTIME2_PRECHARGE_COUNT(v)    BM_EMI_DRAMTIME2_PRECHARGE_COUNT
+#define BF_EMI_DRAMTIME2_PRECHARGE_COUNT_V(e)   BF_EMI_DRAMTIME2_PRECHARGE_COUNT(BV_EMI_DRAMTIME2_PRECHARGE_COUNT__##e)
+#define BFM_EMI_DRAMTIME2_PRECHARGE_COUNT_V(v)  BM_EMI_DRAMTIME2_PRECHARGE_COUNT
+
+#define HW_EMI_STATICCTRL                       HW(EMI_STATICCTRL)
+#define HWA_EMI_STATICCTRL                      (0x80020000 + 0x100)
+#define HWT_EMI_STATICCTRL                      HWIO_32_RW
+#define HWN_EMI_STATICCTRL                      EMI_STATICCTRL
+#define HWI_EMI_STATICCTRL                      
+#define HW_EMI_STATICCTRL_SET                   HW(EMI_STATICCTRL_SET)
+#define HWA_EMI_STATICCTRL_SET                  (HWA_EMI_STATICCTRL + 0x4)
+#define HWT_EMI_STATICCTRL_SET                  HWIO_32_WO
+#define HWN_EMI_STATICCTRL_SET                  EMI_STATICCTRL
+#define HWI_EMI_STATICCTRL_SET                  
+#define HW_EMI_STATICCTRL_CLR                   HW(EMI_STATICCTRL_CLR)
+#define HWA_EMI_STATICCTRL_CLR                  (HWA_EMI_STATICCTRL + 0x8)
+#define HWT_EMI_STATICCTRL_CLR                  HWIO_32_WO
+#define HWN_EMI_STATICCTRL_CLR                  EMI_STATICCTRL
+#define HWI_EMI_STATICCTRL_CLR                  
+#define HW_EMI_STATICCTRL_TOG                   HW(EMI_STATICCTRL_TOG)
+#define HWA_EMI_STATICCTRL_TOG                  (HWA_EMI_STATICCTRL + 0xc)
+#define HWT_EMI_STATICCTRL_TOG                  HWIO_32_WO
+#define HWN_EMI_STATICCTRL_TOG                  EMI_STATICCTRL
+#define HWI_EMI_STATICCTRL_TOG                  
+#define BP_EMI_STATICCTRL_MEM_WIDTH             2
+#define BM_EMI_STATICCTRL_MEM_WIDTH             0x4
+#define BF_EMI_STATICCTRL_MEM_WIDTH(v)          (((v) & 0x1) << 2)
+#define BFM_EMI_STATICCTRL_MEM_WIDTH(v)         BM_EMI_STATICCTRL_MEM_WIDTH
+#define BF_EMI_STATICCTRL_MEM_WIDTH_V(e)        BF_EMI_STATICCTRL_MEM_WIDTH(BV_EMI_STATICCTRL_MEM_WIDTH__##e)
+#define BFM_EMI_STATICCTRL_MEM_WIDTH_V(v)       BM_EMI_STATICCTRL_MEM_WIDTH
+#define BP_EMI_STATICCTRL_WRITE_PROTECT         1
+#define BM_EMI_STATICCTRL_WRITE_PROTECT         0x2
+#define BF_EMI_STATICCTRL_WRITE_PROTECT(v)      (((v) & 0x1) << 1)
+#define BFM_EMI_STATICCTRL_WRITE_PROTECT(v)     BM_EMI_STATICCTRL_WRITE_PROTECT
+#define BF_EMI_STATICCTRL_WRITE_PROTECT_V(e)    BF_EMI_STATICCTRL_WRITE_PROTECT(BV_EMI_STATICCTRL_WRITE_PROTECT__##e)
+#define BFM_EMI_STATICCTRL_WRITE_PROTECT_V(v)   BM_EMI_STATICCTRL_WRITE_PROTECT
+#define BP_EMI_STATICCTRL_RESET_OUT             0
+#define BM_EMI_STATICCTRL_RESET_OUT             0x1
+#define BF_EMI_STATICCTRL_RESET_OUT(v)          (((v) & 0x1) << 0)
+#define BFM_EMI_STATICCTRL_RESET_OUT(v)         BM_EMI_STATICCTRL_RESET_OUT
+#define BF_EMI_STATICCTRL_RESET_OUT_V(e)        BF_EMI_STATICCTRL_RESET_OUT(BV_EMI_STATICCTRL_RESET_OUT__##e)
+#define BFM_EMI_STATICCTRL_RESET_OUT_V(v)       BM_EMI_STATICCTRL_RESET_OUT
+
+#define HW_EMI_STATICTIME           HW(EMI_STATICTIME)
+#define HWA_EMI_STATICTIME          (0x80020000 + 0x110)
+#define HWT_EMI_STATICTIME          HWIO_32_RW
+#define HWN_EMI_STATICTIME          EMI_STATICTIME
+#define HWI_EMI_STATICTIME          
+#define HW_EMI_STATICTIME_SET       HW(EMI_STATICTIME_SET)
+#define HWA_EMI_STATICTIME_SET      (HWA_EMI_STATICTIME + 0x4)
+#define HWT_EMI_STATICTIME_SET      HWIO_32_WO
+#define HWN_EMI_STATICTIME_SET      EMI_STATICTIME
+#define HWI_EMI_STATICTIME_SET      
+#define HW_EMI_STATICTIME_CLR       HW(EMI_STATICTIME_CLR)
+#define HWA_EMI_STATICTIME_CLR      (HWA_EMI_STATICTIME + 0x8)
+#define HWT_EMI_STATICTIME_CLR      HWIO_32_WO
+#define HWN_EMI_STATICTIME_CLR      EMI_STATICTIME
+#define HWI_EMI_STATICTIME_CLR      
+#define HW_EMI_STATICTIME_TOG       HW(EMI_STATICTIME_TOG)
+#define HWA_EMI_STATICTIME_TOG      (HWA_EMI_STATICTIME + 0xc)
+#define HWT_EMI_STATICTIME_TOG      HWIO_32_WO
+#define HWN_EMI_STATICTIME_TOG      EMI_STATICTIME
+#define HWI_EMI_STATICTIME_TOG      
+#define BP_EMI_STATICTIME_THZ       24
+#define BM_EMI_STATICTIME_THZ       0xf000000
+#define BF_EMI_STATICTIME_THZ(v)    (((v) & 0xf) << 24)
+#define BFM_EMI_STATICTIME_THZ(v)   BM_EMI_STATICTIME_THZ
+#define BF_EMI_STATICTIME_THZ_V(e)  BF_EMI_STATICTIME_THZ(BV_EMI_STATICTIME_THZ__##e)
+#define BFM_EMI_STATICTIME_THZ_V(v) BM_EMI_STATICTIME_THZ
+#define BP_EMI_STATICTIME_TDH       16
+#define BM_EMI_STATICTIME_TDH       0xf0000
+#define BF_EMI_STATICTIME_TDH(v)    (((v) & 0xf) << 16)
+#define BFM_EMI_STATICTIME_TDH(v)   BM_EMI_STATICTIME_TDH
+#define BF_EMI_STATICTIME_TDH_V(e)  BF_EMI_STATICTIME_TDH(BV_EMI_STATICTIME_TDH__##e)
+#define BFM_EMI_STATICTIME_TDH_V(v) BM_EMI_STATICTIME_TDH
+#define BP_EMI_STATICTIME_TDS       8
+#define BM_EMI_STATICTIME_TDS       0xf00
+#define BF_EMI_STATICTIME_TDS(v)    (((v) & 0xf) << 8)
+#define BFM_EMI_STATICTIME_TDS(v)   BM_EMI_STATICTIME_TDS
+#define BF_EMI_STATICTIME_TDS_V(e)  BF_EMI_STATICTIME_TDS(BV_EMI_STATICTIME_TDS__##e)
+#define BFM_EMI_STATICTIME_TDS_V(v) BM_EMI_STATICTIME_TDS
+#define BP_EMI_STATICTIME_TAS       0
+#define BM_EMI_STATICTIME_TAS       0xf
+#define BF_EMI_STATICTIME_TAS(v)    (((v) & 0xf) << 0)
+#define BFM_EMI_STATICTIME_TAS(v)   BM_EMI_STATICTIME_TAS
+#define BF_EMI_STATICTIME_TAS_V(e)  BF_EMI_STATICTIME_TAS(BV_EMI_STATICTIME_TAS__##e)
+#define BFM_EMI_STATICTIME_TAS_V(v) BM_EMI_STATICTIME_TAS
+
+#endif /* __HEADERGEN_STMP3600_EMI_H__*/
diff --git a/firmware/target/arm/imx233/regs/stmp3600/gpmi.h b/firmware/target/arm/imx233/regs/stmp3600/gpmi.h
new file mode 100644
index 0000000000..0d798a81b6
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3600/gpmi.h
@@ -0,0 +1,567 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * stmp3600 version: 2.4.0
+ * stmp3600 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_STMP3600_GPMI_H__
+#define __HEADERGEN_STMP3600_GPMI_H__
+
+#define HW_GPMI_CTRL0                                   HW(GPMI_CTRL0)
+#define HWA_GPMI_CTRL0                                  (0x8000c000 + 0x0)
+#define HWT_GPMI_CTRL0                                  HWIO_32_RW
+#define HWN_GPMI_CTRL0                                  GPMI_CTRL0
+#define HWI_GPMI_CTRL0                                  
+#define HW_GPMI_CTRL0_SET                               HW(GPMI_CTRL0_SET)
+#define HWA_GPMI_CTRL0_SET                              (HWA_GPMI_CTRL0 + 0x4)
+#define HWT_GPMI_CTRL0_SET                              HWIO_32_WO
+#define HWN_GPMI_CTRL0_SET                              GPMI_CTRL0
+#define HWI_GPMI_CTRL0_SET                              
+#define HW_GPMI_CTRL0_CLR                               HW(GPMI_CTRL0_CLR)
+#define HWA_GPMI_CTRL0_CLR                              (HWA_GPMI_CTRL0 + 0x8)
+#define HWT_GPMI_CTRL0_CLR                              HWIO_32_WO
+#define HWN_GPMI_CTRL0_CLR                              GPMI_CTRL0
+#define HWI_GPMI_CTRL0_CLR                              
+#define HW_GPMI_CTRL0_TOG                               HW(GPMI_CTRL0_TOG)
+#define HWA_GPMI_CTRL0_TOG                              (HWA_GPMI_CTRL0 + 0xc)
+#define HWT_GPMI_CTRL0_TOG                              HWIO_32_WO
+#define HWN_GPMI_CTRL0_TOG                              GPMI_CTRL0
+#define HWI_GPMI_CTRL0_TOG                              
+#define BP_GPMI_CTRL0_SFTRST                            31
+#define BM_GPMI_CTRL0_SFTRST                            0x80000000
+#define BV_GPMI_CTRL0_SFTRST__RUN                       0x0
+#define BV_GPMI_CTRL0_SFTRST__RESET                     0x1
+#define BF_GPMI_CTRL0_SFTRST(v)                         (((v) & 0x1) << 31)
+#define BFM_GPMI_CTRL0_SFTRST(v)                        BM_GPMI_CTRL0_SFTRST
+#define BF_GPMI_CTRL0_SFTRST_V(e)                       BF_GPMI_CTRL0_SFTRST(BV_GPMI_CTRL0_SFTRST__##e)
+#define BFM_GPMI_CTRL0_SFTRST_V(v)                      BM_GPMI_CTRL0_SFTRST
+#define BP_GPMI_CTRL0_CLKGATE                           30
+#define BM_GPMI_CTRL0_CLKGATE                           0x40000000
+#define BV_GPMI_CTRL0_CLKGATE__RUN                      0x0
+#define BV_GPMI_CTRL0_CLKGATE__NO_CLKS                  0x1
+#define BF_GPMI_CTRL0_CLKGATE(v)                        (((v) & 0x1) << 30)
+#define BFM_GPMI_CTRL0_CLKGATE(v)                       BM_GPMI_CTRL0_CLKGATE
+#define BF_GPMI_CTRL0_CLKGATE_V(e)                      BF_GPMI_CTRL0_CLKGATE(BV_GPMI_CTRL0_CLKGATE__##e)
+#define BFM_GPMI_CTRL0_CLKGATE_V(v)                     BM_GPMI_CTRL0_CLKGATE
+#define BP_GPMI_CTRL0_RUN                               29
+#define BM_GPMI_CTRL0_RUN                               0x20000000
+#define BV_GPMI_CTRL0_RUN__IDLE                         0x0
+#define BV_GPMI_CTRL0_RUN__BUSY                         0x1
+#define BF_GPMI_CTRL0_RUN(v)                            (((v) & 0x1) << 29)
+#define BFM_GPMI_CTRL0_RUN(v)                           BM_GPMI_CTRL0_RUN
+#define BF_GPMI_CTRL0_RUN_V(e)                          BF_GPMI_CTRL0_RUN(BV_GPMI_CTRL0_RUN__##e)
+#define BFM_GPMI_CTRL0_RUN_V(v)                         BM_GPMI_CTRL0_RUN
+#define BP_GPMI_CTRL0_DEV_IRQ_EN                        28
+#define BM_GPMI_CTRL0_DEV_IRQ_EN                        0x10000000
+#define BF_GPMI_CTRL0_DEV_IRQ_EN(v)                     (((v) & 0x1) << 28)
+#define BFM_GPMI_CTRL0_DEV_IRQ_EN(v)                    BM_GPMI_CTRL0_DEV_IRQ_EN
+#define BF_GPMI_CTRL0_DEV_IRQ_EN_V(e)                   BF_GPMI_CTRL0_DEV_IRQ_EN(BV_GPMI_CTRL0_DEV_IRQ_EN__##e)
+#define BFM_GPMI_CTRL0_DEV_IRQ_EN_V(v)                  BM_GPMI_CTRL0_DEV_IRQ_EN
+#define BP_GPMI_CTRL0_TIMEOUT_IRQ_EN                    27
+#define BM_GPMI_CTRL0_TIMEOUT_IRQ_EN                    0x8000000
+#define BF_GPMI_CTRL0_TIMEOUT_IRQ_EN(v)                 (((v) & 0x1) << 27)
+#define BFM_GPMI_CTRL0_TIMEOUT_IRQ_EN(v)                BM_GPMI_CTRL0_TIMEOUT_IRQ_EN
+#define BF_GPMI_CTRL0_TIMEOUT_IRQ_EN_V(e)               BF_GPMI_CTRL0_TIMEOUT_IRQ_EN(BV_GPMI_CTRL0_TIMEOUT_IRQ_EN__##e)
+#define BFM_GPMI_CTRL0_TIMEOUT_IRQ_EN_V(v)              BM_GPMI_CTRL0_TIMEOUT_IRQ_EN
+#define BP_GPMI_CTRL0_UDMA                              26
+#define BM_GPMI_CTRL0_UDMA                              0x4000000
+#define BV_GPMI_CTRL0_UDMA__DISABLED                    0x0
+#define BV_GPMI_CTRL0_UDMA__ENABLED                     0x1
+#define BF_GPMI_CTRL0_UDMA(v)                           (((v) & 0x1) << 26)
+#define BFM_GPMI_CTRL0_UDMA(v)                          BM_GPMI_CTRL0_UDMA
+#define BF_GPMI_CTRL0_UDMA_V(e)                         BF_GPMI_CTRL0_UDMA(BV_GPMI_CTRL0_UDMA__##e)
+#define BFM_GPMI_CTRL0_UDMA_V(v)                        BM_GPMI_CTRL0_UDMA
+#define BP_GPMI_CTRL0_COMMAND_MODE                      24
+#define BM_GPMI_CTRL0_COMMAND_MODE                      0x3000000
+#define BV_GPMI_CTRL0_COMMAND_MODE__WRITE               0x0
+#define BV_GPMI_CTRL0_COMMAND_MODE__READ                0x1
+#define BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE    0x2
+#define BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY      0x3
+#define BF_GPMI_CTRL0_COMMAND_MODE(v)                   (((v) & 0x3) << 24)
+#define BFM_GPMI_CTRL0_COMMAND_MODE(v)                  BM_GPMI_CTRL0_COMMAND_MODE
+#define BF_GPMI_CTRL0_COMMAND_MODE_V(e)                 BF_GPMI_CTRL0_COMMAND_MODE(BV_GPMI_CTRL0_COMMAND_MODE__##e)
+#define BFM_GPMI_CTRL0_COMMAND_MODE_V(v)                BM_GPMI_CTRL0_COMMAND_MODE
+#define BP_GPMI_CTRL0_WORD_LENGTH                       23
+#define BM_GPMI_CTRL0_WORD_LENGTH                       0x800000
+#define BV_GPMI_CTRL0_WORD_LENGTH__16_BIT               0x0
+#define BV_GPMI_CTRL0_WORD_LENGTH__8_BIT                0x1
+#define BF_GPMI_CTRL0_WORD_LENGTH(v)                    (((v) & 0x1) << 23)
+#define BFM_GPMI_CTRL0_WORD_LENGTH(v)                   BM_GPMI_CTRL0_WORD_LENGTH
+#define BF_GPMI_CTRL0_WORD_LENGTH_V(e)                  BF_GPMI_CTRL0_WORD_LENGTH(BV_GPMI_CTRL0_WORD_LENGTH__##e)
+#define BFM_GPMI_CTRL0_WORD_LENGTH_V(v)                 BM_GPMI_CTRL0_WORD_LENGTH
+#define BP_GPMI_CTRL0_LOCK_CS                           22
+#define BM_GPMI_CTRL0_LOCK_CS                           0x400000
+#define BV_GPMI_CTRL0_LOCK_CS__DISABLED                 0x0
+#define BV_GPMI_CTRL0_LOCK_CS__ENABLED                  0x1
+#define BF_GPMI_CTRL0_LOCK_CS(v)                        (((v) & 0x1) << 22)
+#define BFM_GPMI_CTRL0_LOCK_CS(v)                       BM_GPMI_CTRL0_LOCK_CS
+#define BF_GPMI_CTRL0_LOCK_CS_V(e)                      BF_GPMI_CTRL0_LOCK_CS(BV_GPMI_CTRL0_LOCK_CS__##e)
+#define BFM_GPMI_CTRL0_LOCK_CS_V(v)                     BM_GPMI_CTRL0_LOCK_CS
+#define BP_GPMI_CTRL0_CS                                20
+#define BM_GPMI_CTRL0_CS                                0x300000
+#define BF_GPMI_CTRL0_CS(v)                             (((v) & 0x3) << 20)
+#define BFM_GPMI_CTRL0_CS(v)                            BM_GPMI_CTRL0_CS
+#define BF_GPMI_CTRL0_CS_V(e)                           BF_GPMI_CTRL0_CS(BV_GPMI_CTRL0_CS__##e)
+#define BFM_GPMI_CTRL0_CS_V(v)                          BM_GPMI_CTRL0_CS
+#define BP_GPMI_CTRL0_ADDRESS                           17
+#define BM_GPMI_CTRL0_ADDRESS                           0xe0000
+#define BV_GPMI_CTRL0_ADDRESS__NAND_DATA                0x0
+#define BV_GPMI_CTRL0_ADDRESS__NAND_CLE                 0x1
+#define BV_GPMI_CTRL0_ADDRESS__NAND_ALE                 0x2
+#define BF_GPMI_CTRL0_ADDRESS(v)                        (((v) & 0x7) << 17)
+#define BFM_GPMI_CTRL0_ADDRESS(v)                       BM_GPMI_CTRL0_ADDRESS
+#define BF_GPMI_CTRL0_ADDRESS_V(e)                      BF_GPMI_CTRL0_ADDRESS(BV_GPMI_CTRL0_ADDRESS__##e)
+#define BFM_GPMI_CTRL0_ADDRESS_V(v)                     BM_GPMI_CTRL0_ADDRESS
+#define BP_GPMI_CTRL0_ADDRESS_INCREMENT                 16
+#define BM_GPMI_CTRL0_ADDRESS_INCREMENT                 0x10000
+#define BV_GPMI_CTRL0_ADDRESS_INCREMENT__DISABLED       0x0
+#define BV_GPMI_CTRL0_ADDRESS_INCREMENT__ENABLED        0x1
+#define BF_GPMI_CTRL0_ADDRESS_INCREMENT(v)              (((v) & 0x1) << 16)
+#define BFM_GPMI_CTRL0_ADDRESS_INCREMENT(v)             BM_GPMI_CTRL0_ADDRESS_INCREMENT
+#define BF_GPMI_CTRL0_ADDRESS_INCREMENT_V(e)            BF_GPMI_CTRL0_ADDRESS_INCREMENT(BV_GPMI_CTRL0_ADDRESS_INCREMENT__##e)
+#define BFM_GPMI_CTRL0_ADDRESS_INCREMENT_V(v)           BM_GPMI_CTRL0_ADDRESS_INCREMENT
+#define BP_GPMI_CTRL0_XFER_COUNT                        0
+#define BM_GPMI_CTRL0_XFER_COUNT                        0xffff
+#define BF_GPMI_CTRL0_XFER_COUNT(v)                     (((v) & 0xffff) << 0)
+#define BFM_GPMI_CTRL0_XFER_COUNT(v)                    BM_GPMI_CTRL0_XFER_COUNT
+#define BF_GPMI_CTRL0_XFER_COUNT_V(e)                   BF_GPMI_CTRL0_XFER_COUNT(BV_GPMI_CTRL0_XFER_COUNT__##e)
+#define BFM_GPMI_CTRL0_XFER_COUNT_V(v)                  BM_GPMI_CTRL0_XFER_COUNT
+
+#define HW_GPMI_COMPARE                 HW(GPMI_COMPARE)
+#define HWA_GPMI_COMPARE                (0x8000c000 + 0x10)
+#define HWT_GPMI_COMPARE                HWIO_32_RW
+#define HWN_GPMI_COMPARE                GPMI_COMPARE
+#define HWI_GPMI_COMPARE                
+#define BP_GPMI_COMPARE_MASK            16
+#define BM_GPMI_COMPARE_MASK            0xffff0000
+#define BF_GPMI_COMPARE_MASK(v)         (((v) & 0xffff) << 16)
+#define BFM_GPMI_COMPARE_MASK(v)        BM_GPMI_COMPARE_MASK
+#define BF_GPMI_COMPARE_MASK_V(e)       BF_GPMI_COMPARE_MASK(BV_GPMI_COMPARE_MASK__##e)
+#define BFM_GPMI_COMPARE_MASK_V(v)      BM_GPMI_COMPARE_MASK
+#define BP_GPMI_COMPARE_REFERENCE       0
+#define BM_GPMI_COMPARE_REFERENCE       0xffff
+#define BF_GPMI_COMPARE_REFERENCE(v)    (((v) & 0xffff) << 0)
+#define BFM_GPMI_COMPARE_REFERENCE(v)   BM_GPMI_COMPARE_REFERENCE
+#define BF_GPMI_COMPARE_REFERENCE_V(e)  BF_GPMI_COMPARE_REFERENCE(BV_GPMI_COMPARE_REFERENCE__##e)
+#define BFM_GPMI_COMPARE_REFERENCE_V(v) BM_GPMI_COMPARE_REFERENCE
+
+#define HW_GPMI_CTRL1                                   HW(GPMI_CTRL1)
+#define HWA_GPMI_CTRL1                                  (0x8000c000 + 0x20)
+#define HWT_GPMI_CTRL1                                  HWIO_32_RW
+#define HWN_GPMI_CTRL1                                  GPMI_CTRL1
+#define HWI_GPMI_CTRL1                                  
+#define HW_GPMI_CTRL1_SET                               HW(GPMI_CTRL1_SET)
+#define HWA_GPMI_CTRL1_SET                              (HWA_GPMI_CTRL1 + 0x4)
+#define HWT_GPMI_CTRL1_SET                              HWIO_32_WO
+#define HWN_GPMI_CTRL1_SET                              GPMI_CTRL1
+#define HWI_GPMI_CTRL1_SET                              
+#define HW_GPMI_CTRL1_CLR                               HW(GPMI_CTRL1_CLR)
+#define HWA_GPMI_CTRL1_CLR                              (HWA_GPMI_CTRL1 + 0x8)
+#define HWT_GPMI_CTRL1_CLR                              HWIO_32_WO
+#define HWN_GPMI_CTRL1_CLR                              GPMI_CTRL1
+#define HWI_GPMI_CTRL1_CLR                              
+#define HW_GPMI_CTRL1_TOG                               HW(GPMI_CTRL1_TOG)
+#define HWA_GPMI_CTRL1_TOG                              (HWA_GPMI_CTRL1 + 0xc)
+#define HWT_GPMI_CTRL1_TOG                              HWIO_32_WO
+#define HWN_GPMI_CTRL1_TOG                              GPMI_CTRL1
+#define HWI_GPMI_CTRL1_TOG                              
+#define BP_GPMI_CTRL1_DSAMPLE_TIME                      12
+#define BM_GPMI_CTRL1_DSAMPLE_TIME                      0x3000
+#define BF_GPMI_CTRL1_DSAMPLE_TIME(v)                   (((v) & 0x3) << 12)
+#define BFM_GPMI_CTRL1_DSAMPLE_TIME(v)                  BM_GPMI_CTRL1_DSAMPLE_TIME
+#define BF_GPMI_CTRL1_DSAMPLE_TIME_V(e)                 BF_GPMI_CTRL1_DSAMPLE_TIME(BV_GPMI_CTRL1_DSAMPLE_TIME__##e)
+#define BFM_GPMI_CTRL1_DSAMPLE_TIME_V(v)                BM_GPMI_CTRL1_DSAMPLE_TIME
+#define BP_GPMI_CTRL1_DEV_IRQ                           10
+#define BM_GPMI_CTRL1_DEV_IRQ                           0x400
+#define BF_GPMI_CTRL1_DEV_IRQ(v)                        (((v) & 0x1) << 10)
+#define BFM_GPMI_CTRL1_DEV_IRQ(v)                       BM_GPMI_CTRL1_DEV_IRQ
+#define BF_GPMI_CTRL1_DEV_IRQ_V(e)                      BF_GPMI_CTRL1_DEV_IRQ(BV_GPMI_CTRL1_DEV_IRQ__##e)
+#define BFM_GPMI_CTRL1_DEV_IRQ_V(v)                     BM_GPMI_CTRL1_DEV_IRQ
+#define BP_GPMI_CTRL1_TIMEOUT_IRQ                       9
+#define BM_GPMI_CTRL1_TIMEOUT_IRQ                       0x200
+#define BF_GPMI_CTRL1_TIMEOUT_IRQ(v)                    (((v) & 0x1) << 9)
+#define BFM_GPMI_CTRL1_TIMEOUT_IRQ(v)                   BM_GPMI_CTRL1_TIMEOUT_IRQ
+#define BF_GPMI_CTRL1_TIMEOUT_IRQ_V(e)                  BF_GPMI_CTRL1_TIMEOUT_IRQ(BV_GPMI_CTRL1_TIMEOUT_IRQ__##e)
+#define BFM_GPMI_CTRL1_TIMEOUT_IRQ_V(v)                 BM_GPMI_CTRL1_TIMEOUT_IRQ
+#define BP_GPMI_CTRL1_BURST_EN                          8
+#define BM_GPMI_CTRL1_BURST_EN                          0x100
+#define BF_GPMI_CTRL1_BURST_EN(v)                       (((v) & 0x1) << 8)
+#define BFM_GPMI_CTRL1_BURST_EN(v)                      BM_GPMI_CTRL1_BURST_EN
+#define BF_GPMI_CTRL1_BURST_EN_V(e)                     BF_GPMI_CTRL1_BURST_EN(BV_GPMI_CTRL1_BURST_EN__##e)
+#define BFM_GPMI_CTRL1_BURST_EN_V(v)                    BM_GPMI_CTRL1_BURST_EN
+#define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY3             7
+#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY3             0x80
+#define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY3(v)          (((v) & 0x1) << 7)
+#define BFM_GPMI_CTRL1_ABORT_WAIT_FOR_READY3(v)         BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY3
+#define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY3_V(e)        BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY3(BV_GPMI_CTRL1_ABORT_WAIT_FOR_READY3__##e)
+#define BFM_GPMI_CTRL1_ABORT_WAIT_FOR_READY3_V(v)       BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY3
+#define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY2             6
+#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY2             0x40
+#define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY2(v)          (((v) & 0x1) << 6)
+#define BFM_GPMI_CTRL1_ABORT_WAIT_FOR_READY2(v)         BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY2
+#define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY2_V(e)        BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY2(BV_GPMI_CTRL1_ABORT_WAIT_FOR_READY2__##e)
+#define BFM_GPMI_CTRL1_ABORT_WAIT_FOR_READY2_V(v)       BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY2
+#define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY1             5
+#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY1             0x20
+#define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY1(v)          (((v) & 0x1) << 5)
+#define BFM_GPMI_CTRL1_ABORT_WAIT_FOR_READY1(v)         BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY1
+#define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY1_V(e)        BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY1(BV_GPMI_CTRL1_ABORT_WAIT_FOR_READY1__##e)
+#define BFM_GPMI_CTRL1_ABORT_WAIT_FOR_READY1_V(v)       BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY1
+#define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY0             4
+#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY0             0x10
+#define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY0(v)          (((v) & 0x1) << 4)
+#define BFM_GPMI_CTRL1_ABORT_WAIT_FOR_READY0(v)         BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY0
+#define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY0_V(e)        BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY0(BV_GPMI_CTRL1_ABORT_WAIT_FOR_READY0__##e)
+#define BFM_GPMI_CTRL1_ABORT_WAIT_FOR_READY0_V(v)       BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY0
+#define BP_GPMI_CTRL1_DEV_RESET                         3
+#define BM_GPMI_CTRL1_DEV_RESET                         0x8
+#define BV_GPMI_CTRL1_DEV_RESET__ENABLED                0x0
+#define BV_GPMI_CTRL1_DEV_RESET__DISABLED               0x1
+#define BF_GPMI_CTRL1_DEV_RESET(v)                      (((v) & 0x1) << 3)
+#define BFM_GPMI_CTRL1_DEV_RESET(v)                     BM_GPMI_CTRL1_DEV_RESET
+#define BF_GPMI_CTRL1_DEV_RESET_V(e)                    BF_GPMI_CTRL1_DEV_RESET(BV_GPMI_CTRL1_DEV_RESET__##e)
+#define BFM_GPMI_CTRL1_DEV_RESET_V(v)                   BM_GPMI_CTRL1_DEV_RESET
+#define BP_GPMI_CTRL1_ATA_IRQRDY_POLARITY               2
+#define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY               0x4
+#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVELOW    0x0
+#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVEHIGH   0x1
+#define BF_GPMI_CTRL1_ATA_IRQRDY_POLARITY(v)            (((v) & 0x1) << 2)
+#define BFM_GPMI_CTRL1_ATA_IRQRDY_POLARITY(v)           BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY
+#define BF_GPMI_CTRL1_ATA_IRQRDY_POLARITY_V(e)          BF_GPMI_CTRL1_ATA_IRQRDY_POLARITY(BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__##e)
+#define BFM_GPMI_CTRL1_ATA_IRQRDY_POLARITY_V(v)         BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY
+#define BP_GPMI_CTRL1_CAMERA_MODE                       1
+#define BM_GPMI_CTRL1_CAMERA_MODE                       0x2
+#define BF_GPMI_CTRL1_CAMERA_MODE(v)                    (((v) & 0x1) << 1)
+#define BFM_GPMI_CTRL1_CAMERA_MODE(v)                   BM_GPMI_CTRL1_CAMERA_MODE
+#define BF_GPMI_CTRL1_CAMERA_MODE_V(e)                  BF_GPMI_CTRL1_CAMERA_MODE(BV_GPMI_CTRL1_CAMERA_MODE__##e)
+#define BFM_GPMI_CTRL1_CAMERA_MODE_V(v)                 BM_GPMI_CTRL1_CAMERA_MODE
+#define BP_GPMI_CTRL1_GPMI_MODE                         0
+#define BM_GPMI_CTRL1_GPMI_MODE                         0x1
+#define BV_GPMI_CTRL1_GPMI_MODE__NAND                   0x0
+#define BV_GPMI_CTRL1_GPMI_MODE__ATA                    0x1
+#define BF_GPMI_CTRL1_GPMI_MODE(v)                      (((v) & 0x1) << 0)
+#define BFM_GPMI_CTRL1_GPMI_MODE(v)                     BM_GPMI_CTRL1_GPMI_MODE
+#define BF_GPMI_CTRL1_GPMI_MODE_V(e)                    BF_GPMI_CTRL1_GPMI_MODE(BV_GPMI_CTRL1_GPMI_MODE__##e)
+#define BFM_GPMI_CTRL1_GPMI_MODE_V(v)                   BM_GPMI_CTRL1_GPMI_MODE
+
+#define HW_GPMI_TIMING0                     HW(GPMI_TIMING0)
+#define HWA_GPMI_TIMING0                    (0x8000c000 + 0x30)
+#define HWT_GPMI_TIMING0                    HWIO_32_RW
+#define HWN_GPMI_TIMING0                    GPMI_TIMING0
+#define HWI_GPMI_TIMING0                    
+#define BP_GPMI_TIMING0_ADDRESS_SETUP       16
+#define BM_GPMI_TIMING0_ADDRESS_SETUP       0xff0000
+#define BF_GPMI_TIMING0_ADDRESS_SETUP(v)    (((v) & 0xff) << 16)
+#define BFM_GPMI_TIMING0_ADDRESS_SETUP(v)   BM_GPMI_TIMING0_ADDRESS_SETUP
+#define BF_GPMI_TIMING0_ADDRESS_SETUP_V(e)  BF_GPMI_TIMING0_ADDRESS_SETUP(BV_GPMI_TIMING0_ADDRESS_SETUP__##e)
+#define BFM_GPMI_TIMING0_ADDRESS_SETUP_V(v) BM_GPMI_TIMING0_ADDRESS_SETUP
+#define BP_GPMI_TIMING0_DATA_HOLD           8
+#define BM_GPMI_TIMING0_DATA_HOLD           0xff00
+#define BF_GPMI_TIMING0_DATA_HOLD(v)        (((v) & 0xff) << 8)
+#define BFM_GPMI_TIMING0_DATA_HOLD(v)       BM_GPMI_TIMING0_DATA_HOLD
+#define BF_GPMI_TIMING0_DATA_HOLD_V(e)      BF_GPMI_TIMING0_DATA_HOLD(BV_GPMI_TIMING0_DATA_HOLD__##e)
+#define BFM_GPMI_TIMING0_DATA_HOLD_V(v)     BM_GPMI_TIMING0_DATA_HOLD
+#define BP_GPMI_TIMING0_DATA_SETUP          0
+#define BM_GPMI_TIMING0_DATA_SETUP          0xff
+#define BF_GPMI_TIMING0_DATA_SETUP(v)       (((v) & 0xff) << 0)
+#define BFM_GPMI_TIMING0_DATA_SETUP(v)      BM_GPMI_TIMING0_DATA_SETUP
+#define BF_GPMI_TIMING0_DATA_SETUP_V(e)     BF_GPMI_TIMING0_DATA_SETUP(BV_GPMI_TIMING0_DATA_SETUP__##e)
+#define BFM_GPMI_TIMING0_DATA_SETUP_V(v)    BM_GPMI_TIMING0_DATA_SETUP
+
+#define HW_GPMI_TIMING1                             HW(GPMI_TIMING1)
+#define HWA_GPMI_TIMING1                            (0x8000c000 + 0x40)
+#define HWT_GPMI_TIMING1                            HWIO_32_RW
+#define HWN_GPMI_TIMING1                            GPMI_TIMING1
+#define HWI_GPMI_TIMING1                            
+#define BP_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT         16
+#define BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT         0xffff0000
+#define BF_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(v)      (((v) & 0xffff) << 16)
+#define BFM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(v)     BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT
+#define BF_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_V(e)    BF_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(BV_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT__##e)
+#define BFM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_V(v)   BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT
+#define BP_GPMI_TIMING1_ATA_READY_TIMEOUT           0
+#define BM_GPMI_TIMING1_ATA_READY_TIMEOUT           0xffff
+#define BF_GPMI_TIMING1_ATA_READY_TIMEOUT(v)        (((v) & 0xffff) << 0)
+#define BFM_GPMI_TIMING1_ATA_READY_TIMEOUT(v)       BM_GPMI_TIMING1_ATA_READY_TIMEOUT
+#define BF_GPMI_TIMING1_ATA_READY_TIMEOUT_V(e)      BF_GPMI_TIMING1_ATA_READY_TIMEOUT(BV_GPMI_TIMING1_ATA_READY_TIMEOUT__##e)
+#define BFM_GPMI_TIMING1_ATA_READY_TIMEOUT_V(v)     BM_GPMI_TIMING1_ATA_READY_TIMEOUT
+
+#define HW_GPMI_TIMING2                     HW(GPMI_TIMING2)
+#define HWA_GPMI_TIMING2                    (0x8000c000 + 0x50)
+#define HWT_GPMI_TIMING2                    HWIO_32_RW
+#define HWN_GPMI_TIMING2                    GPMI_TIMING2
+#define HWI_GPMI_TIMING2                    
+#define BP_GPMI_TIMING2_UDMA_TRP            24
+#define BM_GPMI_TIMING2_UDMA_TRP            0xff000000
+#define BF_GPMI_TIMING2_UDMA_TRP(v)         (((v) & 0xff) << 24)
+#define BFM_GPMI_TIMING2_UDMA_TRP(v)        BM_GPMI_TIMING2_UDMA_TRP
+#define BF_GPMI_TIMING2_UDMA_TRP_V(e)       BF_GPMI_TIMING2_UDMA_TRP(BV_GPMI_TIMING2_UDMA_TRP__##e)
+#define BFM_GPMI_TIMING2_UDMA_TRP_V(v)      BM_GPMI_TIMING2_UDMA_TRP
+#define BP_GPMI_TIMING2_UDMA_ENV            16
+#define BM_GPMI_TIMING2_UDMA_ENV            0xff0000
+#define BF_GPMI_TIMING2_UDMA_ENV(v)         (((v) & 0xff) << 16)
+#define BFM_GPMI_TIMING2_UDMA_ENV(v)        BM_GPMI_TIMING2_UDMA_ENV
+#define BF_GPMI_TIMING2_UDMA_ENV_V(e)       BF_GPMI_TIMING2_UDMA_ENV(BV_GPMI_TIMING2_UDMA_ENV__##e)
+#define BFM_GPMI_TIMING2_UDMA_ENV_V(v)      BM_GPMI_TIMING2_UDMA_ENV
+#define BP_GPMI_TIMING2_UDMA_HOLD           8
+#define BM_GPMI_TIMING2_UDMA_HOLD           0xff00
+#define BF_GPMI_TIMING2_UDMA_HOLD(v)        (((v) & 0xff) << 8)
+#define BFM_GPMI_TIMING2_UDMA_HOLD(v)       BM_GPMI_TIMING2_UDMA_HOLD
+#define BF_GPMI_TIMING2_UDMA_HOLD_V(e)      BF_GPMI_TIMING2_UDMA_HOLD(BV_GPMI_TIMING2_UDMA_HOLD__##e)
+#define BFM_GPMI_TIMING2_UDMA_HOLD_V(v)     BM_GPMI_TIMING2_UDMA_HOLD
+#define BP_GPMI_TIMING2_UDMA_SETUP          0
+#define BM_GPMI_TIMING2_UDMA_SETUP          0xff
+#define BF_GPMI_TIMING2_UDMA_SETUP(v)       (((v) & 0xff) << 0)
+#define BFM_GPMI_TIMING2_UDMA_SETUP(v)      BM_GPMI_TIMING2_UDMA_SETUP
+#define BF_GPMI_TIMING2_UDMA_SETUP_V(e)     BF_GPMI_TIMING2_UDMA_SETUP(BV_GPMI_TIMING2_UDMA_SETUP__##e)
+#define BFM_GPMI_TIMING2_UDMA_SETUP_V(v)    BM_GPMI_TIMING2_UDMA_SETUP
+
+#define HW_GPMI_DATA            HW(GPMI_DATA)
+#define HWA_GPMI_DATA           (0x8000c000 + 0x60)
+#define HWT_GPMI_DATA           HWIO_32_RW
+#define HWN_GPMI_DATA           GPMI_DATA
+#define HWI_GPMI_DATA           
+#define BP_GPMI_DATA_DATA       0
+#define BM_GPMI_DATA_DATA       0xffffffff
+#define BF_GPMI_DATA_DATA(v)    (((v) & 0xffffffff) << 0)
+#define BFM_GPMI_DATA_DATA(v)   BM_GPMI_DATA_DATA
+#define BF_GPMI_DATA_DATA_V(e)  BF_GPMI_DATA_DATA(BV_GPMI_DATA_DATA__##e)
+#define BFM_GPMI_DATA_DATA_V(v) BM_GPMI_DATA_DATA
+
+#define HW_GPMI_STAT                        HW(GPMI_STAT)
+#define HWA_GPMI_STAT                       (0x8000c000 + 0x70)
+#define HWT_GPMI_STAT                       HWIO_32_RW
+#define HWN_GPMI_STAT                       GPMI_STAT
+#define HWI_GPMI_STAT                       
+#define BP_GPMI_STAT_PRESENT                31
+#define BM_GPMI_STAT_PRESENT                0x80000000
+#define BV_GPMI_STAT_PRESENT__UNAVAILABLE   0x0
+#define BV_GPMI_STAT_PRESENT__AVAILABLE     0x1
+#define BF_GPMI_STAT_PRESENT(v)             (((v) & 0x1) << 31)
+#define BFM_GPMI_STAT_PRESENT(v)            BM_GPMI_STAT_PRESENT
+#define BF_GPMI_STAT_PRESENT_V(e)           BF_GPMI_STAT_PRESENT(BV_GPMI_STAT_PRESENT__##e)
+#define BFM_GPMI_STAT_PRESENT_V(v)          BM_GPMI_STAT_PRESENT
+#define BP_GPMI_STAT_RDY_TIMEOUT            8
+#define BM_GPMI_STAT_RDY_TIMEOUT            0xf00
+#define BF_GPMI_STAT_RDY_TIMEOUT(v)         (((v) & 0xf) << 8)
+#define BFM_GPMI_STAT_RDY_TIMEOUT(v)        BM_GPMI_STAT_RDY_TIMEOUT
+#define BF_GPMI_STAT_RDY_TIMEOUT_V(e)       BF_GPMI_STAT_RDY_TIMEOUT(BV_GPMI_STAT_RDY_TIMEOUT__##e)
+#define BFM_GPMI_STAT_RDY_TIMEOUT_V(v)      BM_GPMI_STAT_RDY_TIMEOUT
+#define BP_GPMI_STAT_ATA_IRQ                7
+#define BM_GPMI_STAT_ATA_IRQ                0x80
+#define BF_GPMI_STAT_ATA_IRQ(v)             (((v) & 0x1) << 7)
+#define BFM_GPMI_STAT_ATA_IRQ(v)            BM_GPMI_STAT_ATA_IRQ
+#define BF_GPMI_STAT_ATA_IRQ_V(e)           BF_GPMI_STAT_ATA_IRQ(BV_GPMI_STAT_ATA_IRQ__##e)
+#define BFM_GPMI_STAT_ATA_IRQ_V(v)          BM_GPMI_STAT_ATA_IRQ
+#define BP_GPMI_STAT_FIFO_EMPTY             5
+#define BM_GPMI_STAT_FIFO_EMPTY             0x20
+#define BV_GPMI_STAT_FIFO_EMPTY__NOT_EMPTY  0x0
+#define BV_GPMI_STAT_FIFO_EMPTY__EMPTY      0x1
+#define BF_GPMI_STAT_FIFO_EMPTY(v)          (((v) & 0x1) << 5)
+#define BFM_GPMI_STAT_FIFO_EMPTY(v)         BM_GPMI_STAT_FIFO_EMPTY
+#define BF_GPMI_STAT_FIFO_EMPTY_V(e)        BF_GPMI_STAT_FIFO_EMPTY(BV_GPMI_STAT_FIFO_EMPTY__##e)
+#define BFM_GPMI_STAT_FIFO_EMPTY_V(v)       BM_GPMI_STAT_FIFO_EMPTY
+#define BP_GPMI_STAT_FIFO_FULL              4
+#define BM_GPMI_STAT_FIFO_FULL              0x10
+#define BV_GPMI_STAT_FIFO_FULL__NOT_FULL    0x0
+#define BV_GPMI_STAT_FIFO_FULL__FULL        0x1
+#define BF_GPMI_STAT_FIFO_FULL(v)           (((v) & 0x1) << 4)
+#define BFM_GPMI_STAT_FIFO_FULL(v)          BM_GPMI_STAT_FIFO_FULL
+#define BF_GPMI_STAT_FIFO_FULL_V(e)         BF_GPMI_STAT_FIFO_FULL(BV_GPMI_STAT_FIFO_FULL__##e)
+#define BFM_GPMI_STAT_FIFO_FULL_V(v)        BM_GPMI_STAT_FIFO_FULL
+#define BP_GPMI_STAT_DEV3_ERROR             3
+#define BM_GPMI_STAT_DEV3_ERROR             0x8
+#define BF_GPMI_STAT_DEV3_ERROR(v)          (((v) & 0x1) << 3)
+#define BFM_GPMI_STAT_DEV3_ERROR(v)         BM_GPMI_STAT_DEV3_ERROR
+#define BF_GPMI_STAT_DEV3_ERROR_V(e)        BF_GPMI_STAT_DEV3_ERROR(BV_GPMI_STAT_DEV3_ERROR__##e)
+#define BFM_GPMI_STAT_DEV3_ERROR_V(v)       BM_GPMI_STAT_DEV3_ERROR
+#define BP_GPMI_STAT_DEV2_ERROR             2
+#define BM_GPMI_STAT_DEV2_ERROR             0x4
+#define BF_GPMI_STAT_DEV2_ERROR(v)          (((v) & 0x1) << 2)
+#define BFM_GPMI_STAT_DEV2_ERROR(v)         BM_GPMI_STAT_DEV2_ERROR
+#define BF_GPMI_STAT_DEV2_ERROR_V(e)        BF_GPMI_STAT_DEV2_ERROR(BV_GPMI_STAT_DEV2_ERROR__##e)
+#define BFM_GPMI_STAT_DEV2_ERROR_V(v)       BM_GPMI_STAT_DEV2_ERROR
+#define BP_GPMI_STAT_DEV1_ERROR             1
+#define BM_GPMI_STAT_DEV1_ERROR             0x2
+#define BF_GPMI_STAT_DEV1_ERROR(v)          (((v) & 0x1) << 1)
+#define BFM_GPMI_STAT_DEV1_ERROR(v)         BM_GPMI_STAT_DEV1_ERROR
+#define BF_GPMI_STAT_DEV1_ERROR_V(e)        BF_GPMI_STAT_DEV1_ERROR(BV_GPMI_STAT_DEV1_ERROR__##e)
+#define BFM_GPMI_STAT_DEV1_ERROR_V(v)       BM_GPMI_STAT_DEV1_ERROR
+#define BP_GPMI_STAT_DEV0_ERROR             0
+#define BM_GPMI_STAT_DEV0_ERROR             0x1
+#define BF_GPMI_STAT_DEV0_ERROR(v)          (((v) & 0x1) << 0)
+#define BFM_GPMI_STAT_DEV0_ERROR(v)         BM_GPMI_STAT_DEV0_ERROR
+#define BF_GPMI_STAT_DEV0_ERROR_V(e)        BF_GPMI_STAT_DEV0_ERROR(BV_GPMI_STAT_DEV0_ERROR__##e)
+#define BFM_GPMI_STAT_DEV0_ERROR_V(v)       BM_GPMI_STAT_DEV0_ERROR
+
+#define HW_GPMI_DEBUG                           HW(GPMI_DEBUG)
+#define HWA_GPMI_DEBUG                          (0x8000c000 + 0x80)
+#define HWT_GPMI_DEBUG                          HWIO_32_RW
+#define HWN_GPMI_DEBUG                          GPMI_DEBUG
+#define HWI_GPMI_DEBUG                          
+#define BP_GPMI_DEBUG_READY3                    31
+#define BM_GPMI_DEBUG_READY3                    0x80000000
+#define BF_GPMI_DEBUG_READY3(v)                 (((v) & 0x1) << 31)
+#define BFM_GPMI_DEBUG_READY3(v)                BM_GPMI_DEBUG_READY3
+#define BF_GPMI_DEBUG_READY3_V(e)               BF_GPMI_DEBUG_READY3(BV_GPMI_DEBUG_READY3__##e)
+#define BFM_GPMI_DEBUG_READY3_V(v)              BM_GPMI_DEBUG_READY3
+#define BP_GPMI_DEBUG_READY2                    30
+#define BM_GPMI_DEBUG_READY2                    0x40000000
+#define BF_GPMI_DEBUG_READY2(v)                 (((v) & 0x1) << 30)
+#define BFM_GPMI_DEBUG_READY2(v)                BM_GPMI_DEBUG_READY2
+#define BF_GPMI_DEBUG_READY2_V(e)               BF_GPMI_DEBUG_READY2(BV_GPMI_DEBUG_READY2__##e)
+#define BFM_GPMI_DEBUG_READY2_V(v)              BM_GPMI_DEBUG_READY2
+#define BP_GPMI_DEBUG_READY1                    29
+#define BM_GPMI_DEBUG_READY1                    0x20000000
+#define BF_GPMI_DEBUG_READY1(v)                 (((v) & 0x1) << 29)
+#define BFM_GPMI_DEBUG_READY1(v)                BM_GPMI_DEBUG_READY1
+#define BF_GPMI_DEBUG_READY1_V(e)               BF_GPMI_DEBUG_READY1(BV_GPMI_DEBUG_READY1__##e)
+#define BFM_GPMI_DEBUG_READY1_V(v)              BM_GPMI_DEBUG_READY1
+#define BP_GPMI_DEBUG_READY0                    28
+#define BM_GPMI_DEBUG_READY0                    0x10000000
+#define BF_GPMI_DEBUG_READY0(v)                 (((v) & 0x1) << 28)
+#define BFM_GPMI_DEBUG_READY0(v)                BM_GPMI_DEBUG_READY0
+#define BF_GPMI_DEBUG_READY0_V(e)               BF_GPMI_DEBUG_READY0(BV_GPMI_DEBUG_READY0__##e)
+#define BFM_GPMI_DEBUG_READY0_V(v)              BM_GPMI_DEBUG_READY0
+#define BP_GPMI_DEBUG_WAIT_FOR_READY_END3       27
+#define BM_GPMI_DEBUG_WAIT_FOR_READY_END3       0x8000000
+#define BF_GPMI_DEBUG_WAIT_FOR_READY_END3(v)    (((v) & 0x1) << 27)
+#define BFM_GPMI_DEBUG_WAIT_FOR_READY_END3(v)   BM_GPMI_DEBUG_WAIT_FOR_READY_END3
+#define BF_GPMI_DEBUG_WAIT_FOR_READY_END3_V(e)  BF_GPMI_DEBUG_WAIT_FOR_READY_END3(BV_GPMI_DEBUG_WAIT_FOR_READY_END3__##e)
+#define BFM_GPMI_DEBUG_WAIT_FOR_READY_END3_V(v) BM_GPMI_DEBUG_WAIT_FOR_READY_END3
+#define BP_GPMI_DEBUG_WAIT_FOR_READY_END2       26
+#define BM_GPMI_DEBUG_WAIT_FOR_READY_END2       0x4000000
+#define BF_GPMI_DEBUG_WAIT_FOR_READY_END2(v)    (((v) & 0x1) << 26)
+#define BFM_GPMI_DEBUG_WAIT_FOR_READY_END2(v)   BM_GPMI_DEBUG_WAIT_FOR_READY_END2
+#define BF_GPMI_DEBUG_WAIT_FOR_READY_END2_V(e)  BF_GPMI_DEBUG_WAIT_FOR_READY_END2(BV_GPMI_DEBUG_WAIT_FOR_READY_END2__##e)
+#define BFM_GPMI_DEBUG_WAIT_FOR_READY_END2_V(v) BM_GPMI_DEBUG_WAIT_FOR_READY_END2
+#define BP_GPMI_DEBUG_WAIT_FOR_READY_END1       25
+#define BM_GPMI_DEBUG_WAIT_FOR_READY_END1       0x2000000
+#define BF_GPMI_DEBUG_WAIT_FOR_READY_END1(v)    (((v) & 0x1) << 25)
+#define BFM_GPMI_DEBUG_WAIT_FOR_READY_END1(v)   BM_GPMI_DEBUG_WAIT_FOR_READY_END1
+#define BF_GPMI_DEBUG_WAIT_FOR_READY_END1_V(e)  BF_GPMI_DEBUG_WAIT_FOR_READY_END1(BV_GPMI_DEBUG_WAIT_FOR_READY_END1__##e)
+#define BFM_GPMI_DEBUG_WAIT_FOR_READY_END1_V(v) BM_GPMI_DEBUG_WAIT_FOR_READY_END1
+#define BP_GPMI_DEBUG_WAIT_FOR_READY_END0       24
+#define BM_GPMI_DEBUG_WAIT_FOR_READY_END0       0x1000000
+#define BF_GPMI_DEBUG_WAIT_FOR_READY_END0(v)    (((v) & 0x1) << 24)
+#define BFM_GPMI_DEBUG_WAIT_FOR_READY_END0(v)   BM_GPMI_DEBUG_WAIT_FOR_READY_END0
+#define BF_GPMI_DEBUG_WAIT_FOR_READY_END0_V(e)  BF_GPMI_DEBUG_WAIT_FOR_READY_END0(BV_GPMI_DEBUG_WAIT_FOR_READY_END0__##e)
+#define BFM_GPMI_DEBUG_WAIT_FOR_READY_END0_V(v) BM_GPMI_DEBUG_WAIT_FOR_READY_END0
+#define BP_GPMI_DEBUG_SENSE3                    23
+#define BM_GPMI_DEBUG_SENSE3                    0x800000
+#define BF_GPMI_DEBUG_SENSE3(v)                 (((v) & 0x1) << 23)
+#define BFM_GPMI_DEBUG_SENSE3(v)                BM_GPMI_DEBUG_SENSE3
+#define BF_GPMI_DEBUG_SENSE3_V(e)               BF_GPMI_DEBUG_SENSE3(BV_GPMI_DEBUG_SENSE3__##e)
+#define BFM_GPMI_DEBUG_SENSE3_V(v)              BM_GPMI_DEBUG_SENSE3
+#define BP_GPMI_DEBUG_SENSE2                    22
+#define BM_GPMI_DEBUG_SENSE2                    0x400000
+#define BF_GPMI_DEBUG_SENSE2(v)                 (((v) & 0x1) << 22)
+#define BFM_GPMI_DEBUG_SENSE2(v)                BM_GPMI_DEBUG_SENSE2
+#define BF_GPMI_DEBUG_SENSE2_V(e)               BF_GPMI_DEBUG_SENSE2(BV_GPMI_DEBUG_SENSE2__##e)
+#define BFM_GPMI_DEBUG_SENSE2_V(v)              BM_GPMI_DEBUG_SENSE2
+#define BP_GPMI_DEBUG_SENSE1                    21
+#define BM_GPMI_DEBUG_SENSE1                    0x200000
+#define BF_GPMI_DEBUG_SENSE1(v)                 (((v) & 0x1) << 21)
+#define BFM_GPMI_DEBUG_SENSE1(v)                BM_GPMI_DEBUG_SENSE1
+#define BF_GPMI_DEBUG_SENSE1_V(e)               BF_GPMI_DEBUG_SENSE1(BV_GPMI_DEBUG_SENSE1__##e)
+#define BFM_GPMI_DEBUG_SENSE1_V(v)              BM_GPMI_DEBUG_SENSE1
+#define BP_GPMI_DEBUG_SENSE0                    20
+#define BM_GPMI_DEBUG_SENSE0                    0x100000
+#define BF_GPMI_DEBUG_SENSE0(v)                 (((v) & 0x1) << 20)
+#define BFM_GPMI_DEBUG_SENSE0(v)                BM_GPMI_DEBUG_SENSE0
+#define BF_GPMI_DEBUG_SENSE0_V(e)               BF_GPMI_DEBUG_SENSE0(BV_GPMI_DEBUG_SENSE0__##e)
+#define BFM_GPMI_DEBUG_SENSE0_V(v)              BM_GPMI_DEBUG_SENSE0
+#define BP_GPMI_DEBUG_DMAREQ3                   19
+#define BM_GPMI_DEBUG_DMAREQ3                   0x80000
+#define BF_GPMI_DEBUG_DMAREQ3(v)                (((v) & 0x1) << 19)
+#define BFM_GPMI_DEBUG_DMAREQ3(v)               BM_GPMI_DEBUG_DMAREQ3
+#define BF_GPMI_DEBUG_DMAREQ3_V(e)              BF_GPMI_DEBUG_DMAREQ3(BV_GPMI_DEBUG_DMAREQ3__##e)
+#define BFM_GPMI_DEBUG_DMAREQ3_V(v)             BM_GPMI_DEBUG_DMAREQ3
+#define BP_GPMI_DEBUG_DMAREQ2                   18
+#define BM_GPMI_DEBUG_DMAREQ2                   0x40000
+#define BF_GPMI_DEBUG_DMAREQ2(v)                (((v) & 0x1) << 18)
+#define BFM_GPMI_DEBUG_DMAREQ2(v)               BM_GPMI_DEBUG_DMAREQ2
+#define BF_GPMI_DEBUG_DMAREQ2_V(e)              BF_GPMI_DEBUG_DMAREQ2(BV_GPMI_DEBUG_DMAREQ2__##e)
+#define BFM_GPMI_DEBUG_DMAREQ2_V(v)             BM_GPMI_DEBUG_DMAREQ2
+#define BP_GPMI_DEBUG_DMAREQ1                   17
+#define BM_GPMI_DEBUG_DMAREQ1                   0x20000
+#define BF_GPMI_DEBUG_DMAREQ1(v)                (((v) & 0x1) << 17)
+#define BFM_GPMI_DEBUG_DMAREQ1(v)               BM_GPMI_DEBUG_DMAREQ1
+#define BF_GPMI_DEBUG_DMAREQ1_V(e)              BF_GPMI_DEBUG_DMAREQ1(BV_GPMI_DEBUG_DMAREQ1__##e)
+#define BFM_GPMI_DEBUG_DMAREQ1_V(v)             BM_GPMI_DEBUG_DMAREQ1
+#define BP_GPMI_DEBUG_DMAREQ0                   16
+#define BM_GPMI_DEBUG_DMAREQ0                   0x10000
+#define BF_GPMI_DEBUG_DMAREQ0(v)                (((v) & 0x1) << 16)
+#define BFM_GPMI_DEBUG_DMAREQ0(v)               BM_GPMI_DEBUG_DMAREQ0
+#define BF_GPMI_DEBUG_DMAREQ0_V(e)              BF_GPMI_DEBUG_DMAREQ0(BV_GPMI_DEBUG_DMAREQ0__##e)
+#define BFM_GPMI_DEBUG_DMAREQ0_V(v)             BM_GPMI_DEBUG_DMAREQ0
+#define BP_GPMI_DEBUG_CMD_END                   12
+#define BM_GPMI_DEBUG_CMD_END                   0xf000
+#define BF_GPMI_DEBUG_CMD_END(v)                (((v) & 0xf) << 12)
+#define BFM_GPMI_DEBUG_CMD_END(v)               BM_GPMI_DEBUG_CMD_END
+#define BF_GPMI_DEBUG_CMD_END_V(e)              BF_GPMI_DEBUG_CMD_END(BV_GPMI_DEBUG_CMD_END__##e)
+#define BFM_GPMI_DEBUG_CMD_END_V(v)             BM_GPMI_DEBUG_CMD_END
+#define BP_GPMI_DEBUG_UDMA_STATE                8
+#define BM_GPMI_DEBUG_UDMA_STATE                0xf00
+#define BF_GPMI_DEBUG_UDMA_STATE(v)             (((v) & 0xf) << 8)
+#define BFM_GPMI_DEBUG_UDMA_STATE(v)            BM_GPMI_DEBUG_UDMA_STATE
+#define BF_GPMI_DEBUG_UDMA_STATE_V(e)           BF_GPMI_DEBUG_UDMA_STATE(BV_GPMI_DEBUG_UDMA_STATE__##e)
+#define BFM_GPMI_DEBUG_UDMA_STATE_V(v)          BM_GPMI_DEBUG_UDMA_STATE
+#define BP_GPMI_DEBUG_BUSY                      7
+#define BM_GPMI_DEBUG_BUSY                      0x80
+#define BV_GPMI_DEBUG_BUSY__DISABLED            0x0
+#define BV_GPMI_DEBUG_BUSY__ENABLED             0x1
+#define BF_GPMI_DEBUG_BUSY(v)                   (((v) & 0x1) << 7)
+#define BFM_GPMI_DEBUG_BUSY(v)                  BM_GPMI_DEBUG_BUSY
+#define BF_GPMI_DEBUG_BUSY_V(e)                 BF_GPMI_DEBUG_BUSY(BV_GPMI_DEBUG_BUSY__##e)
+#define BFM_GPMI_DEBUG_BUSY_V(v)                BM_GPMI_DEBUG_BUSY
+#define BP_GPMI_DEBUG_PIN_STATE                 4
+#define BM_GPMI_DEBUG_PIN_STATE                 0x70
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_IDLE       0x0
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_BYTCNT     0x1
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_ADDR       0x2
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_STALL      0x3
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_STROBE     0x4
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_ATARDY     0x5
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_DHOLD      0x6
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_DONE       0x7
+#define BF_GPMI_DEBUG_PIN_STATE(v)              (((v) & 0x7) << 4)
+#define BFM_GPMI_DEBUG_PIN_STATE(v)             BM_GPMI_DEBUG_PIN_STATE
+#define BF_GPMI_DEBUG_PIN_STATE_V(e)            BF_GPMI_DEBUG_PIN_STATE(BV_GPMI_DEBUG_PIN_STATE__##e)
+#define BFM_GPMI_DEBUG_PIN_STATE_V(v)           BM_GPMI_DEBUG_PIN_STATE
+#define BP_GPMI_DEBUG_MAIN_STATE                0
+#define BM_GPMI_DEBUG_MAIN_STATE                0xf
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_IDLE      0x0
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_BYTCNT    0x1
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFE    0x2
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFR    0x3
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_DMAREQ    0x4
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_DMAACK    0x5
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFF    0x6
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_LDFIFO    0x7
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_LDDMAR    0x8
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_RDCMP     0x9
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_DONE      0xa
+#define BF_GPMI_DEBUG_MAIN_STATE(v)             (((v) & 0xf) << 0)
+#define BFM_GPMI_DEBUG_MAIN_STATE(v)            BM_GPMI_DEBUG_MAIN_STATE
+#define BF_GPMI_DEBUG_MAIN_STATE_V(e)           BF_GPMI_DEBUG_MAIN_STATE(BV_GPMI_DEBUG_MAIN_STATE__##e)
+#define BFM_GPMI_DEBUG_MAIN_STATE_V(v)          BM_GPMI_DEBUG_MAIN_STATE
+
+#endif /* __HEADERGEN_STMP3600_GPMI_H__*/
diff --git a/firmware/target/arm/imx233/regs/stmp3600/hwecc.h b/firmware/target/arm/imx233/regs/stmp3600/hwecc.h
new file mode 100644
index 0000000000..f67dae55a5
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3600/hwecc.h
@@ -0,0 +1,351 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * stmp3600 version: 2.4.0
+ * stmp3600 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_STMP3600_HWECC_H__
+#define __HEADERGEN_STMP3600_HWECC_H__
+
+#define HW_HWECC_CTRL                       HW(HWECC_CTRL)
+#define HWA_HWECC_CTRL                      (0x80008000 + 0x0)
+#define HWT_HWECC_CTRL                      HWIO_32_RW
+#define HWN_HWECC_CTRL                      HWECC_CTRL
+#define HWI_HWECC_CTRL                      
+#define HW_HWECC_CTRL_SET                   HW(HWECC_CTRL_SET)
+#define HWA_HWECC_CTRL_SET                  (HWA_HWECC_CTRL + 0x4)
+#define HWT_HWECC_CTRL_SET                  HWIO_32_WO
+#define HWN_HWECC_CTRL_SET                  HWECC_CTRL
+#define HWI_HWECC_CTRL_SET                  
+#define HW_HWECC_CTRL_CLR                   HW(HWECC_CTRL_CLR)
+#define HWA_HWECC_CTRL_CLR                  (HWA_HWECC_CTRL + 0x8)
+#define HWT_HWECC_CTRL_CLR                  HWIO_32_WO
+#define HWN_HWECC_CTRL_CLR                  HWECC_CTRL
+#define HWI_HWECC_CTRL_CLR                  
+#define HW_HWECC_CTRL_TOG                   HW(HWECC_CTRL_TOG)
+#define HWA_HWECC_CTRL_TOG                  (HWA_HWECC_CTRL + 0xc)
+#define HWT_HWECC_CTRL_TOG                  HWIO_32_WO
+#define HWN_HWECC_CTRL_TOG                  HWECC_CTRL
+#define HWI_HWECC_CTRL_TOG                  
+#define BP_HWECC_CTRL_SFTRST                31
+#define BM_HWECC_CTRL_SFTRST                0x80000000
+#define BF_HWECC_CTRL_SFTRST(v)             (((v) & 0x1) << 31)
+#define BFM_HWECC_CTRL_SFTRST(v)            BM_HWECC_CTRL_SFTRST
+#define BF_HWECC_CTRL_SFTRST_V(e)           BF_HWECC_CTRL_SFTRST(BV_HWECC_CTRL_SFTRST__##e)
+#define BFM_HWECC_CTRL_SFTRST_V(v)          BM_HWECC_CTRL_SFTRST
+#define BP_HWECC_CTRL_CLKGATE               30
+#define BM_HWECC_CTRL_CLKGATE               0x40000000
+#define BF_HWECC_CTRL_CLKGATE(v)            (((v) & 0x1) << 30)
+#define BFM_HWECC_CTRL_CLKGATE(v)           BM_HWECC_CTRL_CLKGATE
+#define BF_HWECC_CTRL_CLKGATE_V(e)          BF_HWECC_CTRL_CLKGATE(BV_HWECC_CTRL_CLKGATE__##e)
+#define BFM_HWECC_CTRL_CLKGATE_V(v)         BM_HWECC_CTRL_CLKGATE
+#define BP_HWECC_CTRL_NUM_SYMBOLS           16
+#define BM_HWECC_CTRL_NUM_SYMBOLS           0x1ff0000
+#define BF_HWECC_CTRL_NUM_SYMBOLS(v)        (((v) & 0x1ff) << 16)
+#define BFM_HWECC_CTRL_NUM_SYMBOLS(v)       BM_HWECC_CTRL_NUM_SYMBOLS
+#define BF_HWECC_CTRL_NUM_SYMBOLS_V(e)      BF_HWECC_CTRL_NUM_SYMBOLS(BV_HWECC_CTRL_NUM_SYMBOLS__##e)
+#define BFM_HWECC_CTRL_NUM_SYMBOLS_V(v)     BM_HWECC_CTRL_NUM_SYMBOLS
+#define BP_HWECC_CTRL_DMAWAIT_COUNT         8
+#define BM_HWECC_CTRL_DMAWAIT_COUNT         0x1f00
+#define BF_HWECC_CTRL_DMAWAIT_COUNT(v)      (((v) & 0x1f) << 8)
+#define BFM_HWECC_CTRL_DMAWAIT_COUNT(v)     BM_HWECC_CTRL_DMAWAIT_COUNT
+#define BF_HWECC_CTRL_DMAWAIT_COUNT_V(e)    BF_HWECC_CTRL_DMAWAIT_COUNT(BV_HWECC_CTRL_DMAWAIT_COUNT__##e)
+#define BFM_HWECC_CTRL_DMAWAIT_COUNT_V(v)   BM_HWECC_CTRL_DMAWAIT_COUNT
+#define BP_HWECC_CTRL_BYTE_ENABLE           6
+#define BM_HWECC_CTRL_BYTE_ENABLE           0x40
+#define BF_HWECC_CTRL_BYTE_ENABLE(v)        (((v) & 0x1) << 6)
+#define BFM_HWECC_CTRL_BYTE_ENABLE(v)       BM_HWECC_CTRL_BYTE_ENABLE
+#define BF_HWECC_CTRL_BYTE_ENABLE_V(e)      BF_HWECC_CTRL_BYTE_ENABLE(BV_HWECC_CTRL_BYTE_ENABLE__##e)
+#define BFM_HWECC_CTRL_BYTE_ENABLE_V(v)     BM_HWECC_CTRL_BYTE_ENABLE
+#define BP_HWECC_CTRL_ECC_SEL               5
+#define BM_HWECC_CTRL_ECC_SEL               0x20
+#define BF_HWECC_CTRL_ECC_SEL(v)            (((v) & 0x1) << 5)
+#define BFM_HWECC_CTRL_ECC_SEL(v)           BM_HWECC_CTRL_ECC_SEL
+#define BF_HWECC_CTRL_ECC_SEL_V(e)          BF_HWECC_CTRL_ECC_SEL(BV_HWECC_CTRL_ECC_SEL__##e)
+#define BFM_HWECC_CTRL_ECC_SEL_V(v)         BM_HWECC_CTRL_ECC_SEL
+#define BP_HWECC_CTRL_ENC_SEL               4
+#define BM_HWECC_CTRL_ENC_SEL               0x10
+#define BF_HWECC_CTRL_ENC_SEL(v)            (((v) & 0x1) << 4)
+#define BFM_HWECC_CTRL_ENC_SEL(v)           BM_HWECC_CTRL_ENC_SEL
+#define BF_HWECC_CTRL_ENC_SEL_V(e)          BF_HWECC_CTRL_ENC_SEL(BV_HWECC_CTRL_ENC_SEL__##e)
+#define BFM_HWECC_CTRL_ENC_SEL_V(v)         BM_HWECC_CTRL_ENC_SEL
+#define BP_HWECC_CTRL_UNCORR_IRQ            2
+#define BM_HWECC_CTRL_UNCORR_IRQ            0x4
+#define BF_HWECC_CTRL_UNCORR_IRQ(v)         (((v) & 0x1) << 2)
+#define BFM_HWECC_CTRL_UNCORR_IRQ(v)        BM_HWECC_CTRL_UNCORR_IRQ
+#define BF_HWECC_CTRL_UNCORR_IRQ_V(e)       BF_HWECC_CTRL_UNCORR_IRQ(BV_HWECC_CTRL_UNCORR_IRQ__##e)
+#define BFM_HWECC_CTRL_UNCORR_IRQ_V(v)      BM_HWECC_CTRL_UNCORR_IRQ
+#define BP_HWECC_CTRL_UNCORR_IRQ_EN         1
+#define BM_HWECC_CTRL_UNCORR_IRQ_EN         0x2
+#define BF_HWECC_CTRL_UNCORR_IRQ_EN(v)      (((v) & 0x1) << 1)
+#define BFM_HWECC_CTRL_UNCORR_IRQ_EN(v)     BM_HWECC_CTRL_UNCORR_IRQ_EN
+#define BF_HWECC_CTRL_UNCORR_IRQ_EN_V(e)    BF_HWECC_CTRL_UNCORR_IRQ_EN(BV_HWECC_CTRL_UNCORR_IRQ_EN__##e)
+#define BFM_HWECC_CTRL_UNCORR_IRQ_EN_V(v)   BM_HWECC_CTRL_UNCORR_IRQ_EN
+#define BP_HWECC_CTRL_RUN                   0
+#define BM_HWECC_CTRL_RUN                   0x1
+#define BF_HWECC_CTRL_RUN(v)                (((v) & 0x1) << 0)
+#define BFM_HWECC_CTRL_RUN(v)               BM_HWECC_CTRL_RUN
+#define BF_HWECC_CTRL_RUN_V(e)              BF_HWECC_CTRL_RUN(BV_HWECC_CTRL_RUN__##e)
+#define BFM_HWECC_CTRL_RUN_V(v)             BM_HWECC_CTRL_RUN
+
+#define HW_HWECC_STAT                       HW(HWECC_STAT)
+#define HWA_HWECC_STAT                      (0x80008000 + 0x10)
+#define HWT_HWECC_STAT                      HWIO_32_RW
+#define HWN_HWECC_STAT                      HWECC_STAT
+#define HWI_HWECC_STAT                      
+#define BP_HWECC_STAT_RSDEC_PRESENT         31
+#define BM_HWECC_STAT_RSDEC_PRESENT         0x80000000
+#define BF_HWECC_STAT_RSDEC_PRESENT(v)      (((v) & 0x1) << 31)
+#define BFM_HWECC_STAT_RSDEC_PRESENT(v)     BM_HWECC_STAT_RSDEC_PRESENT
+#define BF_HWECC_STAT_RSDEC_PRESENT_V(e)    BF_HWECC_STAT_RSDEC_PRESENT(BV_HWECC_STAT_RSDEC_PRESENT__##e)
+#define BFM_HWECC_STAT_RSDEC_PRESENT_V(v)   BM_HWECC_STAT_RSDEC_PRESENT
+#define BP_HWECC_STAT_RSENC_PRESENT         30
+#define BM_HWECC_STAT_RSENC_PRESENT         0x40000000
+#define BF_HWECC_STAT_RSENC_PRESENT(v)      (((v) & 0x1) << 30)
+#define BFM_HWECC_STAT_RSENC_PRESENT(v)     BM_HWECC_STAT_RSENC_PRESENT
+#define BF_HWECC_STAT_RSENC_PRESENT_V(e)    BF_HWECC_STAT_RSENC_PRESENT(BV_HWECC_STAT_RSENC_PRESENT__##e)
+#define BFM_HWECC_STAT_RSENC_PRESENT_V(v)   BM_HWECC_STAT_RSENC_PRESENT
+#define BP_HWECC_STAT_SSDEC_PRESENT         29
+#define BM_HWECC_STAT_SSDEC_PRESENT         0x20000000
+#define BF_HWECC_STAT_SSDEC_PRESENT(v)      (((v) & 0x1) << 29)
+#define BFM_HWECC_STAT_SSDEC_PRESENT(v)     BM_HWECC_STAT_SSDEC_PRESENT
+#define BF_HWECC_STAT_SSDEC_PRESENT_V(e)    BF_HWECC_STAT_SSDEC_PRESENT(BV_HWECC_STAT_SSDEC_PRESENT__##e)
+#define BFM_HWECC_STAT_SSDEC_PRESENT_V(v)   BM_HWECC_STAT_SSDEC_PRESENT
+#define BP_HWECC_STAT_SSENC_PRESENT         28
+#define BM_HWECC_STAT_SSENC_PRESENT         0x10000000
+#define BF_HWECC_STAT_SSENC_PRESENT(v)      (((v) & 0x1) << 28)
+#define BFM_HWECC_STAT_SSENC_PRESENT(v)     BM_HWECC_STAT_SSENC_PRESENT
+#define BF_HWECC_STAT_SSENC_PRESENT_V(e)    BF_HWECC_STAT_SSENC_PRESENT(BV_HWECC_STAT_SSENC_PRESENT__##e)
+#define BFM_HWECC_STAT_SSENC_PRESENT_V(v)   BM_HWECC_STAT_SSENC_PRESENT
+
+#define HW_HWECC_DEBUG0                         HW(HWECC_DEBUG0)
+#define HWA_HWECC_DEBUG0                        (0x80008000 + 0x20)
+#define HWT_HWECC_DEBUG0                        HWIO_32_RW
+#define HWN_HWECC_DEBUG0                        HWECC_DEBUG0
+#define HWI_HWECC_DEBUG0                        
+#define BP_HWECC_DEBUG0_DMA_PENDCMD             29
+#define BM_HWECC_DEBUG0_DMA_PENDCMD             0x20000000
+#define BF_HWECC_DEBUG0_DMA_PENDCMD(v)          (((v) & 0x1) << 29)
+#define BFM_HWECC_DEBUG0_DMA_PENDCMD(v)         BM_HWECC_DEBUG0_DMA_PENDCMD
+#define BF_HWECC_DEBUG0_DMA_PENDCMD_V(e)        BF_HWECC_DEBUG0_DMA_PENDCMD(BV_HWECC_DEBUG0_DMA_PENDCMD__##e)
+#define BFM_HWECC_DEBUG0_DMA_PENDCMD_V(v)       BM_HWECC_DEBUG0_DMA_PENDCMD
+#define BP_HWECC_DEBUG0_DMA_PREQ                28
+#define BM_HWECC_DEBUG0_DMA_PREQ                0x10000000
+#define BF_HWECC_DEBUG0_DMA_PREQ(v)             (((v) & 0x1) << 28)
+#define BFM_HWECC_DEBUG0_DMA_PREQ(v)            BM_HWECC_DEBUG0_DMA_PREQ
+#define BF_HWECC_DEBUG0_DMA_PREQ_V(e)           BF_HWECC_DEBUG0_DMA_PREQ(BV_HWECC_DEBUG0_DMA_PREQ__##e)
+#define BFM_HWECC_DEBUG0_DMA_PREQ_V(v)          BM_HWECC_DEBUG0_DMA_PREQ
+#define BP_HWECC_DEBUG0_SYMBOL_STATE            24
+#define BM_HWECC_DEBUG0_SYMBOL_STATE            0xf000000
+#define BF_HWECC_DEBUG0_SYMBOL_STATE(v)         (((v) & 0xf) << 24)
+#define BFM_HWECC_DEBUG0_SYMBOL_STATE(v)        BM_HWECC_DEBUG0_SYMBOL_STATE
+#define BF_HWECC_DEBUG0_SYMBOL_STATE_V(e)       BF_HWECC_DEBUG0_SYMBOL_STATE(BV_HWECC_DEBUG0_SYMBOL_STATE__##e)
+#define BFM_HWECC_DEBUG0_SYMBOL_STATE_V(v)      BM_HWECC_DEBUG0_SYMBOL_STATE
+#define BP_HWECC_DEBUG0_CTRL_STATE              16
+#define BM_HWECC_DEBUG0_CTRL_STATE              0x3f0000
+#define BF_HWECC_DEBUG0_CTRL_STATE(v)           (((v) & 0x3f) << 16)
+#define BFM_HWECC_DEBUG0_CTRL_STATE(v)          BM_HWECC_DEBUG0_CTRL_STATE
+#define BF_HWECC_DEBUG0_CTRL_STATE_V(e)         BF_HWECC_DEBUG0_CTRL_STATE(BV_HWECC_DEBUG0_CTRL_STATE__##e)
+#define BFM_HWECC_DEBUG0_CTRL_STATE_V(v)        BM_HWECC_DEBUG0_CTRL_STATE
+#define BP_HWECC_DEBUG0_ECC_EXCEPTION           12
+#define BM_HWECC_DEBUG0_ECC_EXCEPTION           0xf000
+#define BF_HWECC_DEBUG0_ECC_EXCEPTION(v)        (((v) & 0xf) << 12)
+#define BFM_HWECC_DEBUG0_ECC_EXCEPTION(v)       BM_HWECC_DEBUG0_ECC_EXCEPTION
+#define BF_HWECC_DEBUG0_ECC_EXCEPTION_V(e)      BF_HWECC_DEBUG0_ECC_EXCEPTION(BV_HWECC_DEBUG0_ECC_EXCEPTION__##e)
+#define BFM_HWECC_DEBUG0_ECC_EXCEPTION_V(v)     BM_HWECC_DEBUG0_ECC_EXCEPTION
+#define BP_HWECC_DEBUG0_NUM_BIT_ERRORS          4
+#define BM_HWECC_DEBUG0_NUM_BIT_ERRORS          0x3f0
+#define BF_HWECC_DEBUG0_NUM_BIT_ERRORS(v)       (((v) & 0x3f) << 4)
+#define BFM_HWECC_DEBUG0_NUM_BIT_ERRORS(v)      BM_HWECC_DEBUG0_NUM_BIT_ERRORS
+#define BF_HWECC_DEBUG0_NUM_BIT_ERRORS_V(e)     BF_HWECC_DEBUG0_NUM_BIT_ERRORS(BV_HWECC_DEBUG0_NUM_BIT_ERRORS__##e)
+#define BFM_HWECC_DEBUG0_NUM_BIT_ERRORS_V(v)    BM_HWECC_DEBUG0_NUM_BIT_ERRORS
+#define BP_HWECC_DEBUG0_NUM_SYMBOL_ERRORS       0
+#define BM_HWECC_DEBUG0_NUM_SYMBOL_ERRORS       0x7
+#define BF_HWECC_DEBUG0_NUM_SYMBOL_ERRORS(v)    (((v) & 0x7) << 0)
+#define BFM_HWECC_DEBUG0_NUM_SYMBOL_ERRORS(v)   BM_HWECC_DEBUG0_NUM_SYMBOL_ERRORS
+#define BF_HWECC_DEBUG0_NUM_SYMBOL_ERRORS_V(e)  BF_HWECC_DEBUG0_NUM_SYMBOL_ERRORS(BV_HWECC_DEBUG0_NUM_SYMBOL_ERRORS__##e)
+#define BFM_HWECC_DEBUG0_NUM_SYMBOL_ERRORS_V(v) BM_HWECC_DEBUG0_NUM_SYMBOL_ERRORS
+
+#define HW_HWECC_DEBUG1                 HW(HWECC_DEBUG1)
+#define HWA_HWECC_DEBUG1                (0x80008000 + 0x30)
+#define HWT_HWECC_DEBUG1                HWIO_32_RW
+#define HWN_HWECC_DEBUG1                HWECC_DEBUG1
+#define HWI_HWECC_DEBUG1                
+#define BP_HWECC_DEBUG1_SYNDROME2       18
+#define BM_HWECC_DEBUG1_SYNDROME2       0x7fc0000
+#define BF_HWECC_DEBUG1_SYNDROME2(v)    (((v) & 0x1ff) << 18)
+#define BFM_HWECC_DEBUG1_SYNDROME2(v)   BM_HWECC_DEBUG1_SYNDROME2
+#define BF_HWECC_DEBUG1_SYNDROME2_V(e)  BF_HWECC_DEBUG1_SYNDROME2(BV_HWECC_DEBUG1_SYNDROME2__##e)
+#define BFM_HWECC_DEBUG1_SYNDROME2_V(v) BM_HWECC_DEBUG1_SYNDROME2
+#define BP_HWECC_DEBUG1_SYNDROME1       9
+#define BM_HWECC_DEBUG1_SYNDROME1       0x3fe00
+#define BF_HWECC_DEBUG1_SYNDROME1(v)    (((v) & 0x1ff) << 9)
+#define BFM_HWECC_DEBUG1_SYNDROME1(v)   BM_HWECC_DEBUG1_SYNDROME1
+#define BF_HWECC_DEBUG1_SYNDROME1_V(e)  BF_HWECC_DEBUG1_SYNDROME1(BV_HWECC_DEBUG1_SYNDROME1__##e)
+#define BFM_HWECC_DEBUG1_SYNDROME1_V(v) BM_HWECC_DEBUG1_SYNDROME1
+#define BP_HWECC_DEBUG1_SYNDROME0       0
+#define BM_HWECC_DEBUG1_SYNDROME0       0x1ff
+#define BF_HWECC_DEBUG1_SYNDROME0(v)    (((v) & 0x1ff) << 0)
+#define BFM_HWECC_DEBUG1_SYNDROME0(v)   BM_HWECC_DEBUG1_SYNDROME0
+#define BF_HWECC_DEBUG1_SYNDROME0_V(e)  BF_HWECC_DEBUG1_SYNDROME0(BV_HWECC_DEBUG1_SYNDROME0__##e)
+#define BFM_HWECC_DEBUG1_SYNDROME0_V(v) BM_HWECC_DEBUG1_SYNDROME0
+
+#define HW_HWECC_DEBUG2                 HW(HWECC_DEBUG2)
+#define HWA_HWECC_DEBUG2                (0x80008000 + 0x40)
+#define HWT_HWECC_DEBUG2                HWIO_32_RW
+#define HWN_HWECC_DEBUG2                HWECC_DEBUG2
+#define HWI_HWECC_DEBUG2                
+#define BP_HWECC_DEBUG2_SYNDROME5       18
+#define BM_HWECC_DEBUG2_SYNDROME5       0x7fc0000
+#define BF_HWECC_DEBUG2_SYNDROME5(v)    (((v) & 0x1ff) << 18)
+#define BFM_HWECC_DEBUG2_SYNDROME5(v)   BM_HWECC_DEBUG2_SYNDROME5
+#define BF_HWECC_DEBUG2_SYNDROME5_V(e)  BF_HWECC_DEBUG2_SYNDROME5(BV_HWECC_DEBUG2_SYNDROME5__##e)
+#define BFM_HWECC_DEBUG2_SYNDROME5_V(v) BM_HWECC_DEBUG2_SYNDROME5
+#define BP_HWECC_DEBUG2_SYNDROME4       9
+#define BM_HWECC_DEBUG2_SYNDROME4       0x3fe00
+#define BF_HWECC_DEBUG2_SYNDROME4(v)    (((v) & 0x1ff) << 9)
+#define BFM_HWECC_DEBUG2_SYNDROME4(v)   BM_HWECC_DEBUG2_SYNDROME4
+#define BF_HWECC_DEBUG2_SYNDROME4_V(e)  BF_HWECC_DEBUG2_SYNDROME4(BV_HWECC_DEBUG2_SYNDROME4__##e)
+#define BFM_HWECC_DEBUG2_SYNDROME4_V(v) BM_HWECC_DEBUG2_SYNDROME4
+#define BP_HWECC_DEBUG2_SYNDROME3       0
+#define BM_HWECC_DEBUG2_SYNDROME3       0x1ff
+#define BF_HWECC_DEBUG2_SYNDROME3(v)    (((v) & 0x1ff) << 0)
+#define BFM_HWECC_DEBUG2_SYNDROME3(v)   BM_HWECC_DEBUG2_SYNDROME3
+#define BF_HWECC_DEBUG2_SYNDROME3_V(e)  BF_HWECC_DEBUG2_SYNDROME3(BV_HWECC_DEBUG2_SYNDROME3__##e)
+#define BFM_HWECC_DEBUG2_SYNDROME3_V(v) BM_HWECC_DEBUG2_SYNDROME3
+
+#define HW_HWECC_DEBUG3                 HW(HWECC_DEBUG3)
+#define HWA_HWECC_DEBUG3                (0x80008000 + 0x50)
+#define HWT_HWECC_DEBUG3                HWIO_32_RW
+#define HWN_HWECC_DEBUG3                HWECC_DEBUG3
+#define HWI_HWECC_DEBUG3                
+#define BP_HWECC_DEBUG3_OMEGA0          18
+#define BM_HWECC_DEBUG3_OMEGA0          0x7fc0000
+#define BF_HWECC_DEBUG3_OMEGA0(v)       (((v) & 0x1ff) << 18)
+#define BFM_HWECC_DEBUG3_OMEGA0(v)      BM_HWECC_DEBUG3_OMEGA0
+#define BF_HWECC_DEBUG3_OMEGA0_V(e)     BF_HWECC_DEBUG3_OMEGA0(BV_HWECC_DEBUG3_OMEGA0__##e)
+#define BFM_HWECC_DEBUG3_OMEGA0_V(v)    BM_HWECC_DEBUG3_OMEGA0
+#define BP_HWECC_DEBUG3_SYNDROME7       9
+#define BM_HWECC_DEBUG3_SYNDROME7       0x3fe00
+#define BF_HWECC_DEBUG3_SYNDROME7(v)    (((v) & 0x1ff) << 9)
+#define BFM_HWECC_DEBUG3_SYNDROME7(v)   BM_HWECC_DEBUG3_SYNDROME7
+#define BF_HWECC_DEBUG3_SYNDROME7_V(e)  BF_HWECC_DEBUG3_SYNDROME7(BV_HWECC_DEBUG3_SYNDROME7__##e)
+#define BFM_HWECC_DEBUG3_SYNDROME7_V(v) BM_HWECC_DEBUG3_SYNDROME7
+#define BP_HWECC_DEBUG3_SYNDROME6       0
+#define BM_HWECC_DEBUG3_SYNDROME6       0x1ff
+#define BF_HWECC_DEBUG3_SYNDROME6(v)    (((v) & 0x1ff) << 0)
+#define BFM_HWECC_DEBUG3_SYNDROME6(v)   BM_HWECC_DEBUG3_SYNDROME6
+#define BF_HWECC_DEBUG3_SYNDROME6_V(e)  BF_HWECC_DEBUG3_SYNDROME6(BV_HWECC_DEBUG3_SYNDROME6__##e)
+#define BFM_HWECC_DEBUG3_SYNDROME6_V(v) BM_HWECC_DEBUG3_SYNDROME6
+
+#define HW_HWECC_DEBUG4                 HW(HWECC_DEBUG4)
+#define HWA_HWECC_DEBUG4                (0x80008000 + 0x60)
+#define HWT_HWECC_DEBUG4                HWIO_32_RW
+#define HWN_HWECC_DEBUG4                HWECC_DEBUG4
+#define HWI_HWECC_DEBUG4                
+#define BP_HWECC_DEBUG4_OMEGA3          18
+#define BM_HWECC_DEBUG4_OMEGA3          0x7fc0000
+#define BF_HWECC_DEBUG4_OMEGA3(v)       (((v) & 0x1ff) << 18)
+#define BFM_HWECC_DEBUG4_OMEGA3(v)      BM_HWECC_DEBUG4_OMEGA3
+#define BF_HWECC_DEBUG4_OMEGA3_V(e)     BF_HWECC_DEBUG4_OMEGA3(BV_HWECC_DEBUG4_OMEGA3__##e)
+#define BFM_HWECC_DEBUG4_OMEGA3_V(v)    BM_HWECC_DEBUG4_OMEGA3
+#define BP_HWECC_DEBUG4_OMEGA2          9
+#define BM_HWECC_DEBUG4_OMEGA2          0x3fe00
+#define BF_HWECC_DEBUG4_OMEGA2(v)       (((v) & 0x1ff) << 9)
+#define BFM_HWECC_DEBUG4_OMEGA2(v)      BM_HWECC_DEBUG4_OMEGA2
+#define BF_HWECC_DEBUG4_OMEGA2_V(e)     BF_HWECC_DEBUG4_OMEGA2(BV_HWECC_DEBUG4_OMEGA2__##e)
+#define BFM_HWECC_DEBUG4_OMEGA2_V(v)    BM_HWECC_DEBUG4_OMEGA2
+#define BP_HWECC_DEBUG4_OMEGA1          0
+#define BM_HWECC_DEBUG4_OMEGA1          0x1ff
+#define BF_HWECC_DEBUG4_OMEGA1(v)       (((v) & 0x1ff) << 0)
+#define BFM_HWECC_DEBUG4_OMEGA1(v)      BM_HWECC_DEBUG4_OMEGA1
+#define BF_HWECC_DEBUG4_OMEGA1_V(e)     BF_HWECC_DEBUG4_OMEGA1(BV_HWECC_DEBUG4_OMEGA1__##e)
+#define BFM_HWECC_DEBUG4_OMEGA1_V(v)    BM_HWECC_DEBUG4_OMEGA1
+
+#define HW_HWECC_DEBUG5                 HW(HWECC_DEBUG5)
+#define HWA_HWECC_DEBUG5                (0x80008000 + 0x70)
+#define HWT_HWECC_DEBUG5                HWIO_32_RW
+#define HWN_HWECC_DEBUG5                HWECC_DEBUG5
+#define HWI_HWECC_DEBUG5                
+#define BP_HWECC_DEBUG5_LAMBDA2         18
+#define BM_HWECC_DEBUG5_LAMBDA2         0x7fc0000
+#define BF_HWECC_DEBUG5_LAMBDA2(v)      (((v) & 0x1ff) << 18)
+#define BFM_HWECC_DEBUG5_LAMBDA2(v)     BM_HWECC_DEBUG5_LAMBDA2
+#define BF_HWECC_DEBUG5_LAMBDA2_V(e)    BF_HWECC_DEBUG5_LAMBDA2(BV_HWECC_DEBUG5_LAMBDA2__##e)
+#define BFM_HWECC_DEBUG5_LAMBDA2_V(v)   BM_HWECC_DEBUG5_LAMBDA2
+#define BP_HWECC_DEBUG5_LAMBDA1         9
+#define BM_HWECC_DEBUG5_LAMBDA1         0x3fe00
+#define BF_HWECC_DEBUG5_LAMBDA1(v)      (((v) & 0x1ff) << 9)
+#define BFM_HWECC_DEBUG5_LAMBDA1(v)     BM_HWECC_DEBUG5_LAMBDA1
+#define BF_HWECC_DEBUG5_LAMBDA1_V(e)    BF_HWECC_DEBUG5_LAMBDA1(BV_HWECC_DEBUG5_LAMBDA1__##e)
+#define BFM_HWECC_DEBUG5_LAMBDA1_V(v)   BM_HWECC_DEBUG5_LAMBDA1
+#define BP_HWECC_DEBUG5_LAMBDA0         0
+#define BM_HWECC_DEBUG5_LAMBDA0         0x1ff
+#define BF_HWECC_DEBUG5_LAMBDA0(v)      (((v) & 0x1ff) << 0)
+#define BFM_HWECC_DEBUG5_LAMBDA0(v)     BM_HWECC_DEBUG5_LAMBDA0
+#define BF_HWECC_DEBUG5_LAMBDA0_V(e)    BF_HWECC_DEBUG5_LAMBDA0(BV_HWECC_DEBUG5_LAMBDA0__##e)
+#define BFM_HWECC_DEBUG5_LAMBDA0_V(v)   BM_HWECC_DEBUG5_LAMBDA0
+
+#define HW_HWECC_DEBUG6                 HW(HWECC_DEBUG6)
+#define HWA_HWECC_DEBUG6                (0x80008000 + 0x80)
+#define HWT_HWECC_DEBUG6                HWIO_32_RW
+#define HWN_HWECC_DEBUG6                HWECC_DEBUG6
+#define HWI_HWECC_DEBUG6                
+#define BP_HWECC_DEBUG6_LAMBDA4         9
+#define BM_HWECC_DEBUG6_LAMBDA4         0x3fe00
+#define BF_HWECC_DEBUG6_LAMBDA4(v)      (((v) & 0x1ff) << 9)
+#define BFM_HWECC_DEBUG6_LAMBDA4(v)     BM_HWECC_DEBUG6_LAMBDA4
+#define BF_HWECC_DEBUG6_LAMBDA4_V(e)    BF_HWECC_DEBUG6_LAMBDA4(BV_HWECC_DEBUG6_LAMBDA4__##e)
+#define BFM_HWECC_DEBUG6_LAMBDA4_V(v)   BM_HWECC_DEBUG6_LAMBDA4
+#define BP_HWECC_DEBUG6_LAMBDA3         0
+#define BM_HWECC_DEBUG6_LAMBDA3         0x1ff
+#define BF_HWECC_DEBUG6_LAMBDA3(v)      (((v) & 0x1ff) << 0)
+#define BFM_HWECC_DEBUG6_LAMBDA3(v)     BM_HWECC_DEBUG6_LAMBDA3
+#define BF_HWECC_DEBUG6_LAMBDA3_V(e)    BF_HWECC_DEBUG6_LAMBDA3(BV_HWECC_DEBUG6_LAMBDA3__##e)
+#define BFM_HWECC_DEBUG6_LAMBDA3_V(v)   BM_HWECC_DEBUG6_LAMBDA3
+
+#define HW_HWECC_DATA               HW(HWECC_DATA)
+#define HWA_HWECC_DATA              (0x80008000 + 0x90)
+#define HWT_HWECC_DATA              HWIO_32_RW
+#define HWN_HWECC_DATA              HWECC_DATA
+#define HWI_HWECC_DATA              
+#define HW_HWECC_DATA_SET           HW(HWECC_DATA_SET)
+#define HWA_HWECC_DATA_SET          (HWA_HWECC_DATA + 0x4)
+#define HWT_HWECC_DATA_SET          HWIO_32_WO
+#define HWN_HWECC_DATA_SET          HWECC_DATA
+#define HWI_HWECC_DATA_SET          
+#define HW_HWECC_DATA_CLR           HW(HWECC_DATA_CLR)
+#define HWA_HWECC_DATA_CLR          (HWA_HWECC_DATA + 0x8)
+#define HWT_HWECC_DATA_CLR          HWIO_32_WO
+#define HWN_HWECC_DATA_CLR          HWECC_DATA
+#define HWI_HWECC_DATA_CLR          
+#define HW_HWECC_DATA_TOG           HW(HWECC_DATA_TOG)
+#define HWA_HWECC_DATA_TOG          (HWA_HWECC_DATA + 0xc)
+#define HWT_HWECC_DATA_TOG          HWIO_32_WO
+#define HWN_HWECC_DATA_TOG          HWECC_DATA
+#define HWI_HWECC_DATA_TOG          
+#define BP_HWECC_DATA_DATA          0
+#define BM_HWECC_DATA_DATA          0xffffffff
+#define BF_HWECC_DATA_DATA(v)       (((v) & 0xffffffff) << 0)
+#define BFM_HWECC_DATA_DATA(v)      BM_HWECC_DATA_DATA
+#define BF_HWECC_DATA_DATA_V(e)     BF_HWECC_DATA_DATA(BV_HWECC_DATA_DATA__##e)
+#define BFM_HWECC_DATA_DATA_V(v)    BM_HWECC_DATA_DATA
+
+#endif /* __HEADERGEN_STMP3600_HWECC_H__*/
diff --git a/firmware/target/arm/imx233/regs/stmp3600/i2c.h b/firmware/target/arm/imx233/regs/stmp3600/i2c.h
new file mode 100644
index 0000000000..62a8802107
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3600/i2c.h
@@ -0,0 +1,798 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * stmp3600 version: 2.4.0
+ * stmp3600 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_STMP3600_I2C_H__
+#define __HEADERGEN_STMP3600_I2C_H__
+
+#define HW_I2C_CTRL0                                HW(I2C_CTRL0)
+#define HWA_I2C_CTRL0                               (0x80058000 + 0x0)
+#define HWT_I2C_CTRL0                               HWIO_32_RW
+#define HWN_I2C_CTRL0                               I2C_CTRL0
+#define HWI_I2C_CTRL0                               
+#define HW_I2C_CTRL0_SET                            HW(I2C_CTRL0_SET)
+#define HWA_I2C_CTRL0_SET                           (HWA_I2C_CTRL0 + 0x4)
+#define HWT_I2C_CTRL0_SET                           HWIO_32_WO
+#define HWN_I2C_CTRL0_SET                           I2C_CTRL0
+#define HWI_I2C_CTRL0_SET                           
+#define HW_I2C_CTRL0_CLR                            HW(I2C_CTRL0_CLR)
+#define HWA_I2C_CTRL0_CLR                           (HWA_I2C_CTRL0 + 0x8)
+#define HWT_I2C_CTRL0_CLR                           HWIO_32_WO
+#define HWN_I2C_CTRL0_CLR                           I2C_CTRL0
+#define HWI_I2C_CTRL0_CLR                           
+#define HW_I2C_CTRL0_TOG                            HW(I2C_CTRL0_TOG)
+#define HWA_I2C_CTRL0_TOG                           (HWA_I2C_CTRL0 + 0xc)
+#define HWT_I2C_CTRL0_TOG                           HWIO_32_WO
+#define HWN_I2C_CTRL0_TOG                           I2C_CTRL0
+#define HWI_I2C_CTRL0_TOG                           
+#define BP_I2C_CTRL0_SFTRST                         31
+#define BM_I2C_CTRL0_SFTRST                         0x80000000
+#define BV_I2C_CTRL0_SFTRST__RUN                    0x0
+#define BV_I2C_CTRL0_SFTRST__RESET                  0x1
+#define BF_I2C_CTRL0_SFTRST(v)                      (((v) & 0x1) << 31)
+#define BFM_I2C_CTRL0_SFTRST(v)                     BM_I2C_CTRL0_SFTRST
+#define BF_I2C_CTRL0_SFTRST_V(e)                    BF_I2C_CTRL0_SFTRST(BV_I2C_CTRL0_SFTRST__##e)
+#define BFM_I2C_CTRL0_SFTRST_V(v)                   BM_I2C_CTRL0_SFTRST
+#define BP_I2C_CTRL0_CLKGATE                        30
+#define BM_I2C_CTRL0_CLKGATE                        0x40000000
+#define BV_I2C_CTRL0_CLKGATE__RUN                   0x0
+#define BV_I2C_CTRL0_CLKGATE__NO_CLKS               0x1
+#define BF_I2C_CTRL0_CLKGATE(v)                     (((v) & 0x1) << 30)
+#define BFM_I2C_CTRL0_CLKGATE(v)                    BM_I2C_CTRL0_CLKGATE
+#define BF_I2C_CTRL0_CLKGATE_V(e)                   BF_I2C_CTRL0_CLKGATE(BV_I2C_CTRL0_CLKGATE__##e)
+#define BFM_I2C_CTRL0_CLKGATE_V(v)                  BM_I2C_CTRL0_CLKGATE
+#define BP_I2C_CTRL0_RUN                            29
+#define BM_I2C_CTRL0_RUN                            0x20000000
+#define BV_I2C_CTRL0_RUN__HALT                      0x0
+#define BV_I2C_CTRL0_RUN__RUN                       0x1
+#define BF_I2C_CTRL0_RUN(v)                         (((v) & 0x1) << 29)
+#define BFM_I2C_CTRL0_RUN(v)                        BM_I2C_CTRL0_RUN
+#define BF_I2C_CTRL0_RUN_V(e)                       BF_I2C_CTRL0_RUN(BV_I2C_CTRL0_RUN__##e)
+#define BFM_I2C_CTRL0_RUN_V(v)                      BM_I2C_CTRL0_RUN
+#define BP_I2C_CTRL0_PRE_ACK                        27
+#define BM_I2C_CTRL0_PRE_ACK                        0x8000000
+#define BF_I2C_CTRL0_PRE_ACK(v)                     (((v) & 0x1) << 27)
+#define BFM_I2C_CTRL0_PRE_ACK(v)                    BM_I2C_CTRL0_PRE_ACK
+#define BF_I2C_CTRL0_PRE_ACK_V(e)                   BF_I2C_CTRL0_PRE_ACK(BV_I2C_CTRL0_PRE_ACK__##e)
+#define BFM_I2C_CTRL0_PRE_ACK_V(v)                  BM_I2C_CTRL0_PRE_ACK
+#define BP_I2C_CTRL0_ACKNOWLEDGE                    26
+#define BM_I2C_CTRL0_ACKNOWLEDGE                    0x4000000
+#define BV_I2C_CTRL0_ACKNOWLEDGE__SNAK              0x0
+#define BV_I2C_CTRL0_ACKNOWLEDGE__ACK               0x1
+#define BF_I2C_CTRL0_ACKNOWLEDGE(v)                 (((v) & 0x1) << 26)
+#define BFM_I2C_CTRL0_ACKNOWLEDGE(v)                BM_I2C_CTRL0_ACKNOWLEDGE
+#define BF_I2C_CTRL0_ACKNOWLEDGE_V(e)               BF_I2C_CTRL0_ACKNOWLEDGE(BV_I2C_CTRL0_ACKNOWLEDGE__##e)
+#define BFM_I2C_CTRL0_ACKNOWLEDGE_V(v)              BM_I2C_CTRL0_ACKNOWLEDGE
+#define BP_I2C_CTRL0_SEND_NAK_ON_LAST               25
+#define BM_I2C_CTRL0_SEND_NAK_ON_LAST               0x2000000
+#define BV_I2C_CTRL0_SEND_NAK_ON_LAST__ACK_IT       0x0
+#define BV_I2C_CTRL0_SEND_NAK_ON_LAST__NAK_IT       0x1
+#define BF_I2C_CTRL0_SEND_NAK_ON_LAST(v)            (((v) & 0x1) << 25)
+#define BFM_I2C_CTRL0_SEND_NAK_ON_LAST(v)           BM_I2C_CTRL0_SEND_NAK_ON_LAST
+#define BF_I2C_CTRL0_SEND_NAK_ON_LAST_V(e)          BF_I2C_CTRL0_SEND_NAK_ON_LAST(BV_I2C_CTRL0_SEND_NAK_ON_LAST__##e)
+#define BFM_I2C_CTRL0_SEND_NAK_ON_LAST_V(v)         BM_I2C_CTRL0_SEND_NAK_ON_LAST
+#define BP_I2C_CTRL0_PIO_MODE                       24
+#define BM_I2C_CTRL0_PIO_MODE                       0x1000000
+#define BF_I2C_CTRL0_PIO_MODE(v)                    (((v) & 0x1) << 24)
+#define BFM_I2C_CTRL0_PIO_MODE(v)                   BM_I2C_CTRL0_PIO_MODE
+#define BF_I2C_CTRL0_PIO_MODE_V(e)                  BF_I2C_CTRL0_PIO_MODE(BV_I2C_CTRL0_PIO_MODE__##e)
+#define BFM_I2C_CTRL0_PIO_MODE_V(v)                 BM_I2C_CTRL0_PIO_MODE
+#define BP_I2C_CTRL0_MULTI_MASTER                   23
+#define BM_I2C_CTRL0_MULTI_MASTER                   0x800000
+#define BV_I2C_CTRL0_MULTI_MASTER__SINGLE           0x0
+#define BV_I2C_CTRL0_MULTI_MASTER__MULTIPLE         0x1
+#define BF_I2C_CTRL0_MULTI_MASTER(v)                (((v) & 0x1) << 23)
+#define BFM_I2C_CTRL0_MULTI_MASTER(v)               BM_I2C_CTRL0_MULTI_MASTER
+#define BF_I2C_CTRL0_MULTI_MASTER_V(e)              BF_I2C_CTRL0_MULTI_MASTER(BV_I2C_CTRL0_MULTI_MASTER__##e)
+#define BFM_I2C_CTRL0_MULTI_MASTER_V(v)             BM_I2C_CTRL0_MULTI_MASTER
+#define BP_I2C_CTRL0_CLOCK_HELD                     22
+#define BM_I2C_CTRL0_CLOCK_HELD                     0x400000
+#define BV_I2C_CTRL0_CLOCK_HELD__RELEASE            0x0
+#define BV_I2C_CTRL0_CLOCK_HELD__HELD_LOW           0x1
+#define BF_I2C_CTRL0_CLOCK_HELD(v)                  (((v) & 0x1) << 22)
+#define BFM_I2C_CTRL0_CLOCK_HELD(v)                 BM_I2C_CTRL0_CLOCK_HELD
+#define BF_I2C_CTRL0_CLOCK_HELD_V(e)                BF_I2C_CTRL0_CLOCK_HELD(BV_I2C_CTRL0_CLOCK_HELD__##e)
+#define BFM_I2C_CTRL0_CLOCK_HELD_V(v)               BM_I2C_CTRL0_CLOCK_HELD
+#define BP_I2C_CTRL0_RETAIN_CLOCK                   21
+#define BM_I2C_CTRL0_RETAIN_CLOCK                   0x200000
+#define BV_I2C_CTRL0_RETAIN_CLOCK__RELEASE          0x0
+#define BV_I2C_CTRL0_RETAIN_CLOCK__HOLD_LOW         0x1
+#define BF_I2C_CTRL0_RETAIN_CLOCK(v)                (((v) & 0x1) << 21)
+#define BFM_I2C_CTRL0_RETAIN_CLOCK(v)               BM_I2C_CTRL0_RETAIN_CLOCK
+#define BF_I2C_CTRL0_RETAIN_CLOCK_V(e)              BF_I2C_CTRL0_RETAIN_CLOCK(BV_I2C_CTRL0_RETAIN_CLOCK__##e)
+#define BFM_I2C_CTRL0_RETAIN_CLOCK_V(v)             BM_I2C_CTRL0_RETAIN_CLOCK
+#define BP_I2C_CTRL0_POST_SEND_STOP                 20
+#define BM_I2C_CTRL0_POST_SEND_STOP                 0x100000
+#define BV_I2C_CTRL0_POST_SEND_STOP__NO_STOP        0x0
+#define BV_I2C_CTRL0_POST_SEND_STOP__SEND_STOP      0x1
+#define BF_I2C_CTRL0_POST_SEND_STOP(v)              (((v) & 0x1) << 20)
+#define BFM_I2C_CTRL0_POST_SEND_STOP(v)             BM_I2C_CTRL0_POST_SEND_STOP
+#define BF_I2C_CTRL0_POST_SEND_STOP_V(e)            BF_I2C_CTRL0_POST_SEND_STOP(BV_I2C_CTRL0_POST_SEND_STOP__##e)
+#define BFM_I2C_CTRL0_POST_SEND_STOP_V(v)           BM_I2C_CTRL0_POST_SEND_STOP
+#define BP_I2C_CTRL0_PRE_SEND_START                 19
+#define BM_I2C_CTRL0_PRE_SEND_START                 0x80000
+#define BV_I2C_CTRL0_PRE_SEND_START__NO_START       0x0
+#define BV_I2C_CTRL0_PRE_SEND_START__SEND_START     0x1
+#define BF_I2C_CTRL0_PRE_SEND_START(v)              (((v) & 0x1) << 19)
+#define BFM_I2C_CTRL0_PRE_SEND_START(v)             BM_I2C_CTRL0_PRE_SEND_START
+#define BF_I2C_CTRL0_PRE_SEND_START_V(e)            BF_I2C_CTRL0_PRE_SEND_START(BV_I2C_CTRL0_PRE_SEND_START__##e)
+#define BFM_I2C_CTRL0_PRE_SEND_START_V(v)           BM_I2C_CTRL0_PRE_SEND_START
+#define BP_I2C_CTRL0_SLAVE_ADDRESS_ENABLE           18
+#define BM_I2C_CTRL0_SLAVE_ADDRESS_ENABLE           0x40000
+#define BV_I2C_CTRL0_SLAVE_ADDRESS_ENABLE__DISABLED 0x0
+#define BV_I2C_CTRL0_SLAVE_ADDRESS_ENABLE__ENABLED  0x1
+#define BF_I2C_CTRL0_SLAVE_ADDRESS_ENABLE(v)        (((v) & 0x1) << 18)
+#define BFM_I2C_CTRL0_SLAVE_ADDRESS_ENABLE(v)       BM_I2C_CTRL0_SLAVE_ADDRESS_ENABLE
+#define BF_I2C_CTRL0_SLAVE_ADDRESS_ENABLE_V(e)      BF_I2C_CTRL0_SLAVE_ADDRESS_ENABLE(BV_I2C_CTRL0_SLAVE_ADDRESS_ENABLE__##e)
+#define BFM_I2C_CTRL0_SLAVE_ADDRESS_ENABLE_V(v)     BM_I2C_CTRL0_SLAVE_ADDRESS_ENABLE
+#define BP_I2C_CTRL0_MASTER_MODE                    17
+#define BM_I2C_CTRL0_MASTER_MODE                    0x20000
+#define BV_I2C_CTRL0_MASTER_MODE__SLAVE             0x0
+#define BV_I2C_CTRL0_MASTER_MODE__MASTER            0x1
+#define BF_I2C_CTRL0_MASTER_MODE(v)                 (((v) & 0x1) << 17)
+#define BFM_I2C_CTRL0_MASTER_MODE(v)                BM_I2C_CTRL0_MASTER_MODE
+#define BF_I2C_CTRL0_MASTER_MODE_V(e)               BF_I2C_CTRL0_MASTER_MODE(BV_I2C_CTRL0_MASTER_MODE__##e)
+#define BFM_I2C_CTRL0_MASTER_MODE_V(v)              BM_I2C_CTRL0_MASTER_MODE
+#define BP_I2C_CTRL0_DIRECTION                      16
+#define BM_I2C_CTRL0_DIRECTION                      0x10000
+#define BV_I2C_CTRL0_DIRECTION__RECEIVE             0x0
+#define BV_I2C_CTRL0_DIRECTION__TRANSMIT            0x1
+#define BF_I2C_CTRL0_DIRECTION(v)                   (((v) & 0x1) << 16)
+#define BFM_I2C_CTRL0_DIRECTION(v)                  BM_I2C_CTRL0_DIRECTION
+#define BF_I2C_CTRL0_DIRECTION_V(e)                 BF_I2C_CTRL0_DIRECTION(BV_I2C_CTRL0_DIRECTION__##e)
+#define BFM_I2C_CTRL0_DIRECTION_V(v)                BM_I2C_CTRL0_DIRECTION
+#define BP_I2C_CTRL0_XFER_COUNT                     0
+#define BM_I2C_CTRL0_XFER_COUNT                     0xffff
+#define BF_I2C_CTRL0_XFER_COUNT(v)                  (((v) & 0xffff) << 0)
+#define BFM_I2C_CTRL0_XFER_COUNT(v)                 BM_I2C_CTRL0_XFER_COUNT
+#define BF_I2C_CTRL0_XFER_COUNT_V(e)                BF_I2C_CTRL0_XFER_COUNT(BV_I2C_CTRL0_XFER_COUNT__##e)
+#define BFM_I2C_CTRL0_XFER_COUNT_V(v)               BM_I2C_CTRL0_XFER_COUNT
+
+#define HW_I2C_TIMING0                  HW(I2C_TIMING0)
+#define HWA_I2C_TIMING0                 (0x80058000 + 0x10)
+#define HWT_I2C_TIMING0                 HWIO_32_RW
+#define HWN_I2C_TIMING0                 I2C_TIMING0
+#define HWI_I2C_TIMING0                 
+#define HW_I2C_TIMING0_SET              HW(I2C_TIMING0_SET)
+#define HWA_I2C_TIMING0_SET             (HWA_I2C_TIMING0 + 0x4)
+#define HWT_I2C_TIMING0_SET             HWIO_32_WO
+#define HWN_I2C_TIMING0_SET             I2C_TIMING0
+#define HWI_I2C_TIMING0_SET             
+#define HW_I2C_TIMING0_CLR              HW(I2C_TIMING0_CLR)
+#define HWA_I2C_TIMING0_CLR             (HWA_I2C_TIMING0 + 0x8)
+#define HWT_I2C_TIMING0_CLR             HWIO_32_WO
+#define HWN_I2C_TIMING0_CLR             I2C_TIMING0
+#define HWI_I2C_TIMING0_CLR             
+#define HW_I2C_TIMING0_TOG              HW(I2C_TIMING0_TOG)
+#define HWA_I2C_TIMING0_TOG             (HWA_I2C_TIMING0 + 0xc)
+#define HWT_I2C_TIMING0_TOG             HWIO_32_WO
+#define HWN_I2C_TIMING0_TOG             I2C_TIMING0
+#define HWI_I2C_TIMING0_TOG             
+#define BP_I2C_TIMING0_HIGH_COUNT       16
+#define BM_I2C_TIMING0_HIGH_COUNT       0x3ff0000
+#define BF_I2C_TIMING0_HIGH_COUNT(v)    (((v) & 0x3ff) << 16)
+#define BFM_I2C_TIMING0_HIGH_COUNT(v)   BM_I2C_TIMING0_HIGH_COUNT
+#define BF_I2C_TIMING0_HIGH_COUNT_V(e)  BF_I2C_TIMING0_HIGH_COUNT(BV_I2C_TIMING0_HIGH_COUNT__##e)
+#define BFM_I2C_TIMING0_HIGH_COUNT_V(v) BM_I2C_TIMING0_HIGH_COUNT
+#define BP_I2C_TIMING0_RCV_COUNT        0
+#define BM_I2C_TIMING0_RCV_COUNT        0x3ff
+#define BF_I2C_TIMING0_RCV_COUNT(v)     (((v) & 0x3ff) << 0)
+#define BFM_I2C_TIMING0_RCV_COUNT(v)    BM_I2C_TIMING0_RCV_COUNT
+#define BF_I2C_TIMING0_RCV_COUNT_V(e)   BF_I2C_TIMING0_RCV_COUNT(BV_I2C_TIMING0_RCV_COUNT__##e)
+#define BFM_I2C_TIMING0_RCV_COUNT_V(v)  BM_I2C_TIMING0_RCV_COUNT
+
+#define HW_I2C_TIMING1                  HW(I2C_TIMING1)
+#define HWA_I2C_TIMING1                 (0x80058000 + 0x20)
+#define HWT_I2C_TIMING1                 HWIO_32_RW
+#define HWN_I2C_TIMING1                 I2C_TIMING1
+#define HWI_I2C_TIMING1                 
+#define HW_I2C_TIMING1_SET              HW(I2C_TIMING1_SET)
+#define HWA_I2C_TIMING1_SET             (HWA_I2C_TIMING1 + 0x4)
+#define HWT_I2C_TIMING1_SET             HWIO_32_WO
+#define HWN_I2C_TIMING1_SET             I2C_TIMING1
+#define HWI_I2C_TIMING1_SET             
+#define HW_I2C_TIMING1_CLR              HW(I2C_TIMING1_CLR)
+#define HWA_I2C_TIMING1_CLR             (HWA_I2C_TIMING1 + 0x8)
+#define HWT_I2C_TIMING1_CLR             HWIO_32_WO
+#define HWN_I2C_TIMING1_CLR             I2C_TIMING1
+#define HWI_I2C_TIMING1_CLR             
+#define HW_I2C_TIMING1_TOG              HW(I2C_TIMING1_TOG)
+#define HWA_I2C_TIMING1_TOG             (HWA_I2C_TIMING1 + 0xc)
+#define HWT_I2C_TIMING1_TOG             HWIO_32_WO
+#define HWN_I2C_TIMING1_TOG             I2C_TIMING1
+#define HWI_I2C_TIMING1_TOG             
+#define BP_I2C_TIMING1_LOW_COUNT        16
+#define BM_I2C_TIMING1_LOW_COUNT        0x3ff0000
+#define BF_I2C_TIMING1_LOW_COUNT(v)     (((v) & 0x3ff) << 16)
+#define BFM_I2C_TIMING1_LOW_COUNT(v)    BM_I2C_TIMING1_LOW_COUNT
+#define BF_I2C_TIMING1_LOW_COUNT_V(e)   BF_I2C_TIMING1_LOW_COUNT(BV_I2C_TIMING1_LOW_COUNT__##e)
+#define BFM_I2C_TIMING1_LOW_COUNT_V(v)  BM_I2C_TIMING1_LOW_COUNT
+#define BP_I2C_TIMING1_XMIT_COUNT       0
+#define BM_I2C_TIMING1_XMIT_COUNT       0x3ff
+#define BF_I2C_TIMING1_XMIT_COUNT(v)    (((v) & 0x3ff) << 0)
+#define BFM_I2C_TIMING1_XMIT_COUNT(v)   BM_I2C_TIMING1_XMIT_COUNT
+#define BF_I2C_TIMING1_XMIT_COUNT_V(e)  BF_I2C_TIMING1_XMIT_COUNT(BV_I2C_TIMING1_XMIT_COUNT__##e)
+#define BFM_I2C_TIMING1_XMIT_COUNT_V(v) BM_I2C_TIMING1_XMIT_COUNT
+
+#define HW_I2C_TIMING2                      HW(I2C_TIMING2)
+#define HWA_I2C_TIMING2                     (0x80058000 + 0x30)
+#define HWT_I2C_TIMING2                     HWIO_32_RW
+#define HWN_I2C_TIMING2                     I2C_TIMING2
+#define HWI_I2C_TIMING2                     
+#define HW_I2C_TIMING2_SET                  HW(I2C_TIMING2_SET)
+#define HWA_I2C_TIMING2_SET                 (HWA_I2C_TIMING2 + 0x4)
+#define HWT_I2C_TIMING2_SET                 HWIO_32_WO
+#define HWN_I2C_TIMING2_SET                 I2C_TIMING2
+#define HWI_I2C_TIMING2_SET                 
+#define HW_I2C_TIMING2_CLR                  HW(I2C_TIMING2_CLR)
+#define HWA_I2C_TIMING2_CLR                 (HWA_I2C_TIMING2 + 0x8)
+#define HWT_I2C_TIMING2_CLR                 HWIO_32_WO
+#define HWN_I2C_TIMING2_CLR                 I2C_TIMING2
+#define HWI_I2C_TIMING2_CLR                 
+#define HW_I2C_TIMING2_TOG                  HW(I2C_TIMING2_TOG)
+#define HWA_I2C_TIMING2_TOG                 (HWA_I2C_TIMING2 + 0xc)
+#define HWT_I2C_TIMING2_TOG                 HWIO_32_WO
+#define HWN_I2C_TIMING2_TOG                 I2C_TIMING2
+#define HWI_I2C_TIMING2_TOG                 
+#define BP_I2C_TIMING2_BUS_FREE             16
+#define BM_I2C_TIMING2_BUS_FREE             0x3ff0000
+#define BF_I2C_TIMING2_BUS_FREE(v)          (((v) & 0x3ff) << 16)
+#define BFM_I2C_TIMING2_BUS_FREE(v)         BM_I2C_TIMING2_BUS_FREE
+#define BF_I2C_TIMING2_BUS_FREE_V(e)        BF_I2C_TIMING2_BUS_FREE(BV_I2C_TIMING2_BUS_FREE__##e)
+#define BFM_I2C_TIMING2_BUS_FREE_V(v)       BM_I2C_TIMING2_BUS_FREE
+#define BP_I2C_TIMING2_LEADIN_COUNT         0
+#define BM_I2C_TIMING2_LEADIN_COUNT         0x3ff
+#define BF_I2C_TIMING2_LEADIN_COUNT(v)      (((v) & 0x3ff) << 0)
+#define BFM_I2C_TIMING2_LEADIN_COUNT(v)     BM_I2C_TIMING2_LEADIN_COUNT
+#define BF_I2C_TIMING2_LEADIN_COUNT_V(e)    BF_I2C_TIMING2_LEADIN_COUNT(BV_I2C_TIMING2_LEADIN_COUNT__##e)
+#define BFM_I2C_TIMING2_LEADIN_COUNT_V(v)   BM_I2C_TIMING2_LEADIN_COUNT
+
+#define HW_I2C_CTRL1                                        HW(I2C_CTRL1)
+#define HWA_I2C_CTRL1                                       (0x80058000 + 0x40)
+#define HWT_I2C_CTRL1                                       HWIO_32_RW
+#define HWN_I2C_CTRL1                                       I2C_CTRL1
+#define HWI_I2C_CTRL1                                       
+#define HW_I2C_CTRL1_SET                                    HW(I2C_CTRL1_SET)
+#define HWA_I2C_CTRL1_SET                                   (HWA_I2C_CTRL1 + 0x4)
+#define HWT_I2C_CTRL1_SET                                   HWIO_32_WO
+#define HWN_I2C_CTRL1_SET                                   I2C_CTRL1
+#define HWI_I2C_CTRL1_SET                                   
+#define HW_I2C_CTRL1_CLR                                    HW(I2C_CTRL1_CLR)
+#define HWA_I2C_CTRL1_CLR                                   (HWA_I2C_CTRL1 + 0x8)
+#define HWT_I2C_CTRL1_CLR                                   HWIO_32_WO
+#define HWN_I2C_CTRL1_CLR                                   I2C_CTRL1
+#define HWI_I2C_CTRL1_CLR                                   
+#define HW_I2C_CTRL1_TOG                                    HW(I2C_CTRL1_TOG)
+#define HWA_I2C_CTRL1_TOG                                   (HWA_I2C_CTRL1 + 0xc)
+#define HWT_I2C_CTRL1_TOG                                   HWIO_32_WO
+#define HWN_I2C_CTRL1_TOG                                   I2C_CTRL1
+#define HWI_I2C_CTRL1_TOG                                   
+#define BP_I2C_CTRL1_BCAST_SLAVE_EN                         24
+#define BM_I2C_CTRL1_BCAST_SLAVE_EN                         0x1000000
+#define BV_I2C_CTRL1_BCAST_SLAVE_EN__NO_BCAST               0x0
+#define BV_I2C_CTRL1_BCAST_SLAVE_EN__WATCH_BCAST            0x1
+#define BF_I2C_CTRL1_BCAST_SLAVE_EN(v)                      (((v) & 0x1) << 24)
+#define BFM_I2C_CTRL1_BCAST_SLAVE_EN(v)                     BM_I2C_CTRL1_BCAST_SLAVE_EN
+#define BF_I2C_CTRL1_BCAST_SLAVE_EN_V(e)                    BF_I2C_CTRL1_BCAST_SLAVE_EN(BV_I2C_CTRL1_BCAST_SLAVE_EN__##e)
+#define BFM_I2C_CTRL1_BCAST_SLAVE_EN_V(v)                   BM_I2C_CTRL1_BCAST_SLAVE_EN
+#define BP_I2C_CTRL1_SLAVE_ADDRESS_BYTE                     16
+#define BM_I2C_CTRL1_SLAVE_ADDRESS_BYTE                     0xff0000
+#define BF_I2C_CTRL1_SLAVE_ADDRESS_BYTE(v)                  (((v) & 0xff) << 16)
+#define BFM_I2C_CTRL1_SLAVE_ADDRESS_BYTE(v)                 BM_I2C_CTRL1_SLAVE_ADDRESS_BYTE
+#define BF_I2C_CTRL1_SLAVE_ADDRESS_BYTE_V(e)                BF_I2C_CTRL1_SLAVE_ADDRESS_BYTE(BV_I2C_CTRL1_SLAVE_ADDRESS_BYTE__##e)
+#define BFM_I2C_CTRL1_SLAVE_ADDRESS_BYTE_V(v)               BM_I2C_CTRL1_SLAVE_ADDRESS_BYTE
+#define BP_I2C_CTRL1_BUS_FREE_IRQ_EN                        15
+#define BM_I2C_CTRL1_BUS_FREE_IRQ_EN                        0x8000
+#define BV_I2C_CTRL1_BUS_FREE_IRQ_EN__DISABLED              0x0
+#define BV_I2C_CTRL1_BUS_FREE_IRQ_EN__ENABLED               0x1
+#define BF_I2C_CTRL1_BUS_FREE_IRQ_EN(v)                     (((v) & 0x1) << 15)
+#define BFM_I2C_CTRL1_BUS_FREE_IRQ_EN(v)                    BM_I2C_CTRL1_BUS_FREE_IRQ_EN
+#define BF_I2C_CTRL1_BUS_FREE_IRQ_EN_V(e)                   BF_I2C_CTRL1_BUS_FREE_IRQ_EN(BV_I2C_CTRL1_BUS_FREE_IRQ_EN__##e)
+#define BFM_I2C_CTRL1_BUS_FREE_IRQ_EN_V(v)                  BM_I2C_CTRL1_BUS_FREE_IRQ_EN
+#define BP_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN               14
+#define BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN               0x4000
+#define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN__DISABLED     0x0
+#define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN__ENABLED      0x1
+#define BF_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN(v)            (((v) & 0x1) << 14)
+#define BFM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN(v)           BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN
+#define BF_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN_V(e)          BF_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN(BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN__##e)
+#define BFM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN_V(v)         BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN
+#define BP_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN                    13
+#define BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN                    0x2000
+#define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN__DISABLED          0x0
+#define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN__ENABLED           0x1
+#define BF_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN(v)                 (((v) & 0x1) << 13)
+#define BFM_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN(v)                BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN
+#define BF_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN_V(e)               BF_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN(BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN__##e)
+#define BFM_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN_V(v)              BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN
+#define BP_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN              12
+#define BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN              0x1000
+#define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN__DISABLED    0x0
+#define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN__ENABLED     0x1
+#define BF_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN(v)           (((v) & 0x1) << 12)
+#define BFM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN(v)          BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN
+#define BF_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN_V(e)         BF_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN(BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN__##e)
+#define BFM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN_V(v)        BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN
+#define BP_I2C_CTRL1_EARLY_TERM_IRQ_EN                      11
+#define BM_I2C_CTRL1_EARLY_TERM_IRQ_EN                      0x800
+#define BV_I2C_CTRL1_EARLY_TERM_IRQ_EN__DISABLED            0x0
+#define BV_I2C_CTRL1_EARLY_TERM_IRQ_EN__ENABLED             0x1
+#define BF_I2C_CTRL1_EARLY_TERM_IRQ_EN(v)                   (((v) & 0x1) << 11)
+#define BFM_I2C_CTRL1_EARLY_TERM_IRQ_EN(v)                  BM_I2C_CTRL1_EARLY_TERM_IRQ_EN
+#define BF_I2C_CTRL1_EARLY_TERM_IRQ_EN_V(e)                 BF_I2C_CTRL1_EARLY_TERM_IRQ_EN(BV_I2C_CTRL1_EARLY_TERM_IRQ_EN__##e)
+#define BFM_I2C_CTRL1_EARLY_TERM_IRQ_EN_V(v)                BM_I2C_CTRL1_EARLY_TERM_IRQ_EN
+#define BP_I2C_CTRL1_MASTER_LOSS_IRQ_EN                     10
+#define BM_I2C_CTRL1_MASTER_LOSS_IRQ_EN                     0x400
+#define BV_I2C_CTRL1_MASTER_LOSS_IRQ_EN__DISABLED           0x0
+#define BV_I2C_CTRL1_MASTER_LOSS_IRQ_EN__ENABLED            0x1
+#define BF_I2C_CTRL1_MASTER_LOSS_IRQ_EN(v)                  (((v) & 0x1) << 10)
+#define BFM_I2C_CTRL1_MASTER_LOSS_IRQ_EN(v)                 BM_I2C_CTRL1_MASTER_LOSS_IRQ_EN
+#define BF_I2C_CTRL1_MASTER_LOSS_IRQ_EN_V(e)                BF_I2C_CTRL1_MASTER_LOSS_IRQ_EN(BV_I2C_CTRL1_MASTER_LOSS_IRQ_EN__##e)
+#define BFM_I2C_CTRL1_MASTER_LOSS_IRQ_EN_V(v)               BM_I2C_CTRL1_MASTER_LOSS_IRQ_EN
+#define BP_I2C_CTRL1_SLAVE_STOP_IRQ_EN                      9
+#define BM_I2C_CTRL1_SLAVE_STOP_IRQ_EN                      0x200
+#define BV_I2C_CTRL1_SLAVE_STOP_IRQ_EN__DISABLED            0x0
+#define BV_I2C_CTRL1_SLAVE_STOP_IRQ_EN__ENABLED             0x1
+#define BF_I2C_CTRL1_SLAVE_STOP_IRQ_EN(v)                   (((v) & 0x1) << 9)
+#define BFM_I2C_CTRL1_SLAVE_STOP_IRQ_EN(v)                  BM_I2C_CTRL1_SLAVE_STOP_IRQ_EN
+#define BF_I2C_CTRL1_SLAVE_STOP_IRQ_EN_V(e)                 BF_I2C_CTRL1_SLAVE_STOP_IRQ_EN(BV_I2C_CTRL1_SLAVE_STOP_IRQ_EN__##e)
+#define BFM_I2C_CTRL1_SLAVE_STOP_IRQ_EN_V(v)                BM_I2C_CTRL1_SLAVE_STOP_IRQ_EN
+#define BP_I2C_CTRL1_SLAVE_IRQ_EN                           8
+#define BM_I2C_CTRL1_SLAVE_IRQ_EN                           0x100
+#define BV_I2C_CTRL1_SLAVE_IRQ_EN__DISABLED                 0x0
+#define BV_I2C_CTRL1_SLAVE_IRQ_EN__ENABLED                  0x1
+#define BF_I2C_CTRL1_SLAVE_IRQ_EN(v)                        (((v) & 0x1) << 8)
+#define BFM_I2C_CTRL1_SLAVE_IRQ_EN(v)                       BM_I2C_CTRL1_SLAVE_IRQ_EN
+#define BF_I2C_CTRL1_SLAVE_IRQ_EN_V(e)                      BF_I2C_CTRL1_SLAVE_IRQ_EN(BV_I2C_CTRL1_SLAVE_IRQ_EN__##e)
+#define BFM_I2C_CTRL1_SLAVE_IRQ_EN_V(v)                     BM_I2C_CTRL1_SLAVE_IRQ_EN
+#define BP_I2C_CTRL1_BUS_FREE_IRQ                           7
+#define BM_I2C_CTRL1_BUS_FREE_IRQ                           0x80
+#define BV_I2C_CTRL1_BUS_FREE_IRQ__NO_REQUEST               0x0
+#define BV_I2C_CTRL1_BUS_FREE_IRQ__REQUEST                  0x1
+#define BF_I2C_CTRL1_BUS_FREE_IRQ(v)                        (((v) & 0x1) << 7)
+#define BFM_I2C_CTRL1_BUS_FREE_IRQ(v)                       BM_I2C_CTRL1_BUS_FREE_IRQ
+#define BF_I2C_CTRL1_BUS_FREE_IRQ_V(e)                      BF_I2C_CTRL1_BUS_FREE_IRQ(BV_I2C_CTRL1_BUS_FREE_IRQ__##e)
+#define BFM_I2C_CTRL1_BUS_FREE_IRQ_V(v)                     BM_I2C_CTRL1_BUS_FREE_IRQ
+#define BP_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ                  6
+#define BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ                  0x40
+#define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ__NO_REQUEST      0x0
+#define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ__REQUEST         0x1
+#define BF_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ(v)               (((v) & 0x1) << 6)
+#define BFM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ(v)              BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ
+#define BF_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_V(e)             BF_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ(BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ__##e)
+#define BFM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_V(v)            BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ
+#define BP_I2C_CTRL1_NO_SLAVE_ACK_IRQ                       5
+#define BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ                       0x20
+#define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ__NO_REQUEST           0x0
+#define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ__REQUEST              0x1
+#define BF_I2C_CTRL1_NO_SLAVE_ACK_IRQ(v)                    (((v) & 0x1) << 5)
+#define BFM_I2C_CTRL1_NO_SLAVE_ACK_IRQ(v)                   BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ
+#define BF_I2C_CTRL1_NO_SLAVE_ACK_IRQ_V(e)                  BF_I2C_CTRL1_NO_SLAVE_ACK_IRQ(BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ__##e)
+#define BFM_I2C_CTRL1_NO_SLAVE_ACK_IRQ_V(v)                 BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ
+#define BP_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ                 4
+#define BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ                 0x10
+#define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ__NO_REQUEST     0x0
+#define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ__REQUEST        0x1
+#define BF_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ(v)              (((v) & 0x1) << 4)
+#define BFM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ(v)             BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ
+#define BF_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_V(e)            BF_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ(BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ__##e)
+#define BFM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_V(v)           BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ
+#define BP_I2C_CTRL1_EARLY_TERM_IRQ                         3
+#define BM_I2C_CTRL1_EARLY_TERM_IRQ                         0x8
+#define BV_I2C_CTRL1_EARLY_TERM_IRQ__NO_REQUEST             0x0
+#define BV_I2C_CTRL1_EARLY_TERM_IRQ__REQUEST                0x1
+#define BF_I2C_CTRL1_EARLY_TERM_IRQ(v)                      (((v) & 0x1) << 3)
+#define BFM_I2C_CTRL1_EARLY_TERM_IRQ(v)                     BM_I2C_CTRL1_EARLY_TERM_IRQ
+#define BF_I2C_CTRL1_EARLY_TERM_IRQ_V(e)                    BF_I2C_CTRL1_EARLY_TERM_IRQ(BV_I2C_CTRL1_EARLY_TERM_IRQ__##e)
+#define BFM_I2C_CTRL1_EARLY_TERM_IRQ_V(v)                   BM_I2C_CTRL1_EARLY_TERM_IRQ
+#define BP_I2C_CTRL1_MASTER_LOSS_IRQ                        2
+#define BM_I2C_CTRL1_MASTER_LOSS_IRQ                        0x4
+#define BV_I2C_CTRL1_MASTER_LOSS_IRQ__NO_REQUEST            0x0
+#define BV_I2C_CTRL1_MASTER_LOSS_IRQ__REQUEST               0x1
+#define BF_I2C_CTRL1_MASTER_LOSS_IRQ(v)                     (((v) & 0x1) << 2)
+#define BFM_I2C_CTRL1_MASTER_LOSS_IRQ(v)                    BM_I2C_CTRL1_MASTER_LOSS_IRQ
+#define BF_I2C_CTRL1_MASTER_LOSS_IRQ_V(e)                   BF_I2C_CTRL1_MASTER_LOSS_IRQ(BV_I2C_CTRL1_MASTER_LOSS_IRQ__##e)
+#define BFM_I2C_CTRL1_MASTER_LOSS_IRQ_V(v)                  BM_I2C_CTRL1_MASTER_LOSS_IRQ
+#define BP_I2C_CTRL1_SLAVE_STOP_IRQ                         1
+#define BM_I2C_CTRL1_SLAVE_STOP_IRQ                         0x2
+#define BV_I2C_CTRL1_SLAVE_STOP_IRQ__NO_REQUEST             0x0
+#define BV_I2C_CTRL1_SLAVE_STOP_IRQ__REQUEST                0x1
+#define BF_I2C_CTRL1_SLAVE_STOP_IRQ(v)                      (((v) & 0x1) << 1)
+#define BFM_I2C_CTRL1_SLAVE_STOP_IRQ(v)                     BM_I2C_CTRL1_SLAVE_STOP_IRQ
+#define BF_I2C_CTRL1_SLAVE_STOP_IRQ_V(e)                    BF_I2C_CTRL1_SLAVE_STOP_IRQ(BV_I2C_CTRL1_SLAVE_STOP_IRQ__##e)
+#define BFM_I2C_CTRL1_SLAVE_STOP_IRQ_V(v)                   BM_I2C_CTRL1_SLAVE_STOP_IRQ
+#define BP_I2C_CTRL1_SLAVE_IRQ                              0
+#define BM_I2C_CTRL1_SLAVE_IRQ                              0x1
+#define BV_I2C_CTRL1_SLAVE_IRQ__NO_REQUEST                  0x0
+#define BV_I2C_CTRL1_SLAVE_IRQ__REQUEST                     0x1
+#define BF_I2C_CTRL1_SLAVE_IRQ(v)                           (((v) & 0x1) << 0)
+#define BFM_I2C_CTRL1_SLAVE_IRQ(v)                          BM_I2C_CTRL1_SLAVE_IRQ
+#define BF_I2C_CTRL1_SLAVE_IRQ_V(e)                         BF_I2C_CTRL1_SLAVE_IRQ(BV_I2C_CTRL1_SLAVE_IRQ__##e)
+#define BFM_I2C_CTRL1_SLAVE_IRQ_V(v)                        BM_I2C_CTRL1_SLAVE_IRQ
+
+#define HW_I2C_STAT                                             HW(I2C_STAT)
+#define HWA_I2C_STAT                                            (0x80058000 + 0x50)
+#define HWT_I2C_STAT                                            HWIO_32_RW
+#define HWN_I2C_STAT                                            I2C_STAT
+#define HWI_I2C_STAT                                            
+#define BP_I2C_STAT_MASTER_PRESENT                              31
+#define BM_I2C_STAT_MASTER_PRESENT                              0x80000000
+#define BV_I2C_STAT_MASTER_PRESENT__UNAVAILABLE                 0x0
+#define BV_I2C_STAT_MASTER_PRESENT__AVAILABLE                   0x1
+#define BF_I2C_STAT_MASTER_PRESENT(v)                           (((v) & 0x1) << 31)
+#define BFM_I2C_STAT_MASTER_PRESENT(v)                          BM_I2C_STAT_MASTER_PRESENT
+#define BF_I2C_STAT_MASTER_PRESENT_V(e)                         BF_I2C_STAT_MASTER_PRESENT(BV_I2C_STAT_MASTER_PRESENT__##e)
+#define BFM_I2C_STAT_MASTER_PRESENT_V(v)                        BM_I2C_STAT_MASTER_PRESENT
+#define BP_I2C_STAT_SLAVE_PRESENT                               30
+#define BM_I2C_STAT_SLAVE_PRESENT                               0x40000000
+#define BV_I2C_STAT_SLAVE_PRESENT__UNAVAILABLE                  0x0
+#define BV_I2C_STAT_SLAVE_PRESENT__AVAILABLE                    0x1
+#define BF_I2C_STAT_SLAVE_PRESENT(v)                            (((v) & 0x1) << 30)
+#define BFM_I2C_STAT_SLAVE_PRESENT(v)                           BM_I2C_STAT_SLAVE_PRESENT
+#define BF_I2C_STAT_SLAVE_PRESENT_V(e)                          BF_I2C_STAT_SLAVE_PRESENT(BV_I2C_STAT_SLAVE_PRESENT__##e)
+#define BFM_I2C_STAT_SLAVE_PRESENT_V(v)                         BM_I2C_STAT_SLAVE_PRESENT
+#define BP_I2C_STAT_ANY_ENABLED_IRQ                             29
+#define BM_I2C_STAT_ANY_ENABLED_IRQ                             0x20000000
+#define BV_I2C_STAT_ANY_ENABLED_IRQ__NO_REQUESTS                0x0
+#define BV_I2C_STAT_ANY_ENABLED_IRQ__AT_LEAST_ONE_REQUEST       0x1
+#define BF_I2C_STAT_ANY_ENABLED_IRQ(v)                          (((v) & 0x1) << 29)
+#define BFM_I2C_STAT_ANY_ENABLED_IRQ(v)                         BM_I2C_STAT_ANY_ENABLED_IRQ
+#define BF_I2C_STAT_ANY_ENABLED_IRQ_V(e)                        BF_I2C_STAT_ANY_ENABLED_IRQ(BV_I2C_STAT_ANY_ENABLED_IRQ__##e)
+#define BFM_I2C_STAT_ANY_ENABLED_IRQ_V(v)                       BM_I2C_STAT_ANY_ENABLED_IRQ
+#define BP_I2C_STAT_RCVD_SLAVE_ADDR                             16
+#define BM_I2C_STAT_RCVD_SLAVE_ADDR                             0xff0000
+#define BF_I2C_STAT_RCVD_SLAVE_ADDR(v)                          (((v) & 0xff) << 16)
+#define BFM_I2C_STAT_RCVD_SLAVE_ADDR(v)                         BM_I2C_STAT_RCVD_SLAVE_ADDR
+#define BF_I2C_STAT_RCVD_SLAVE_ADDR_V(e)                        BF_I2C_STAT_RCVD_SLAVE_ADDR(BV_I2C_STAT_RCVD_SLAVE_ADDR__##e)
+#define BFM_I2C_STAT_RCVD_SLAVE_ADDR_V(v)                       BM_I2C_STAT_RCVD_SLAVE_ADDR
+#define BP_I2C_STAT_SLAVE_ADDR_EQ_ZERO                          15
+#define BM_I2C_STAT_SLAVE_ADDR_EQ_ZERO                          0x8000
+#define BV_I2C_STAT_SLAVE_ADDR_EQ_ZERO__ZERO_NOT_MATCHED        0x0
+#define BV_I2C_STAT_SLAVE_ADDR_EQ_ZERO__WAS_ZERO                0x1
+#define BF_I2C_STAT_SLAVE_ADDR_EQ_ZERO(v)                       (((v) & 0x1) << 15)
+#define BFM_I2C_STAT_SLAVE_ADDR_EQ_ZERO(v)                      BM_I2C_STAT_SLAVE_ADDR_EQ_ZERO
+#define BF_I2C_STAT_SLAVE_ADDR_EQ_ZERO_V(e)                     BF_I2C_STAT_SLAVE_ADDR_EQ_ZERO(BV_I2C_STAT_SLAVE_ADDR_EQ_ZERO__##e)
+#define BFM_I2C_STAT_SLAVE_ADDR_EQ_ZERO_V(v)                    BM_I2C_STAT_SLAVE_ADDR_EQ_ZERO
+#define BP_I2C_STAT_SLAVE_FOUND                                 14
+#define BM_I2C_STAT_SLAVE_FOUND                                 0x4000
+#define BV_I2C_STAT_SLAVE_FOUND__IDLE                           0x0
+#define BV_I2C_STAT_SLAVE_FOUND__WAITING                        0x1
+#define BF_I2C_STAT_SLAVE_FOUND(v)                              (((v) & 0x1) << 14)
+#define BFM_I2C_STAT_SLAVE_FOUND(v)                             BM_I2C_STAT_SLAVE_FOUND
+#define BF_I2C_STAT_SLAVE_FOUND_V(e)                            BF_I2C_STAT_SLAVE_FOUND(BV_I2C_STAT_SLAVE_FOUND__##e)
+#define BFM_I2C_STAT_SLAVE_FOUND_V(v)                           BM_I2C_STAT_SLAVE_FOUND
+#define BP_I2C_STAT_SLAVE_SEARCHING                             13
+#define BM_I2C_STAT_SLAVE_SEARCHING                             0x2000
+#define BV_I2C_STAT_SLAVE_SEARCHING__IDLE                       0x0
+#define BV_I2C_STAT_SLAVE_SEARCHING__ACTIVE                     0x1
+#define BF_I2C_STAT_SLAVE_SEARCHING(v)                          (((v) & 0x1) << 13)
+#define BFM_I2C_STAT_SLAVE_SEARCHING(v)                         BM_I2C_STAT_SLAVE_SEARCHING
+#define BF_I2C_STAT_SLAVE_SEARCHING_V(e)                        BF_I2C_STAT_SLAVE_SEARCHING(BV_I2C_STAT_SLAVE_SEARCHING__##e)
+#define BFM_I2C_STAT_SLAVE_SEARCHING_V(v)                       BM_I2C_STAT_SLAVE_SEARCHING
+#define BP_I2C_STAT_DATA_ENGINE_DMA_WAIT                        12
+#define BM_I2C_STAT_DATA_ENGINE_DMA_WAIT                        0x1000
+#define BV_I2C_STAT_DATA_ENGINE_DMA_WAIT__CONTINUE              0x0
+#define BV_I2C_STAT_DATA_ENGINE_DMA_WAIT__WAITING               0x1
+#define BF_I2C_STAT_DATA_ENGINE_DMA_WAIT(v)                     (((v) & 0x1) << 12)
+#define BFM_I2C_STAT_DATA_ENGINE_DMA_WAIT(v)                    BM_I2C_STAT_DATA_ENGINE_DMA_WAIT
+#define BF_I2C_STAT_DATA_ENGINE_DMA_WAIT_V(e)                   BF_I2C_STAT_DATA_ENGINE_DMA_WAIT(BV_I2C_STAT_DATA_ENGINE_DMA_WAIT__##e)
+#define BFM_I2C_STAT_DATA_ENGINE_DMA_WAIT_V(v)                  BM_I2C_STAT_DATA_ENGINE_DMA_WAIT
+#define BP_I2C_STAT_BUS_BUSY                                    11
+#define BM_I2C_STAT_BUS_BUSY                                    0x800
+#define BV_I2C_STAT_BUS_BUSY__IDLE                              0x0
+#define BV_I2C_STAT_BUS_BUSY__BUSY                              0x1
+#define BF_I2C_STAT_BUS_BUSY(v)                                 (((v) & 0x1) << 11)
+#define BFM_I2C_STAT_BUS_BUSY(v)                                BM_I2C_STAT_BUS_BUSY
+#define BF_I2C_STAT_BUS_BUSY_V(e)                               BF_I2C_STAT_BUS_BUSY(BV_I2C_STAT_BUS_BUSY__##e)
+#define BFM_I2C_STAT_BUS_BUSY_V(v)                              BM_I2C_STAT_BUS_BUSY
+#define BP_I2C_STAT_CLK_GEN_BUSY                                10
+#define BM_I2C_STAT_CLK_GEN_BUSY                                0x400
+#define BV_I2C_STAT_CLK_GEN_BUSY__IDLE                          0x0
+#define BV_I2C_STAT_CLK_GEN_BUSY__BUSY                          0x1
+#define BF_I2C_STAT_CLK_GEN_BUSY(v)                             (((v) & 0x1) << 10)
+#define BFM_I2C_STAT_CLK_GEN_BUSY(v)                            BM_I2C_STAT_CLK_GEN_BUSY
+#define BF_I2C_STAT_CLK_GEN_BUSY_V(e)                           BF_I2C_STAT_CLK_GEN_BUSY(BV_I2C_STAT_CLK_GEN_BUSY__##e)
+#define BFM_I2C_STAT_CLK_GEN_BUSY_V(v)                          BM_I2C_STAT_CLK_GEN_BUSY
+#define BP_I2C_STAT_DATA_ENGINE_BUSY                            9
+#define BM_I2C_STAT_DATA_ENGINE_BUSY                            0x200
+#define BV_I2C_STAT_DATA_ENGINE_BUSY__IDLE                      0x0
+#define BV_I2C_STAT_DATA_ENGINE_BUSY__BUSY                      0x1
+#define BF_I2C_STAT_DATA_ENGINE_BUSY(v)                         (((v) & 0x1) << 9)
+#define BFM_I2C_STAT_DATA_ENGINE_BUSY(v)                        BM_I2C_STAT_DATA_ENGINE_BUSY
+#define BF_I2C_STAT_DATA_ENGINE_BUSY_V(e)                       BF_I2C_STAT_DATA_ENGINE_BUSY(BV_I2C_STAT_DATA_ENGINE_BUSY__##e)
+#define BFM_I2C_STAT_DATA_ENGINE_BUSY_V(v)                      BM_I2C_STAT_DATA_ENGINE_BUSY
+#define BP_I2C_STAT_SLAVE_BUSY                                  8
+#define BM_I2C_STAT_SLAVE_BUSY                                  0x100
+#define BV_I2C_STAT_SLAVE_BUSY__IDLE                            0x0
+#define BV_I2C_STAT_SLAVE_BUSY__BUSY                            0x1
+#define BF_I2C_STAT_SLAVE_BUSY(v)                               (((v) & 0x1) << 8)
+#define BFM_I2C_STAT_SLAVE_BUSY(v)                              BM_I2C_STAT_SLAVE_BUSY
+#define BF_I2C_STAT_SLAVE_BUSY_V(e)                             BF_I2C_STAT_SLAVE_BUSY(BV_I2C_STAT_SLAVE_BUSY__##e)
+#define BFM_I2C_STAT_SLAVE_BUSY_V(v)                            BM_I2C_STAT_SLAVE_BUSY
+#define BP_I2C_STAT_BUS_FREE_IRQ_SUMMARY                        7
+#define BM_I2C_STAT_BUS_FREE_IRQ_SUMMARY                        0x80
+#define BV_I2C_STAT_BUS_FREE_IRQ_SUMMARY__NO_REQUEST            0x0
+#define BV_I2C_STAT_BUS_FREE_IRQ_SUMMARY__REQUEST               0x1
+#define BF_I2C_STAT_BUS_FREE_IRQ_SUMMARY(v)                     (((v) & 0x1) << 7)
+#define BFM_I2C_STAT_BUS_FREE_IRQ_SUMMARY(v)                    BM_I2C_STAT_BUS_FREE_IRQ_SUMMARY
+#define BF_I2C_STAT_BUS_FREE_IRQ_SUMMARY_V(e)                   BF_I2C_STAT_BUS_FREE_IRQ_SUMMARY(BV_I2C_STAT_BUS_FREE_IRQ_SUMMARY__##e)
+#define BFM_I2C_STAT_BUS_FREE_IRQ_SUMMARY_V(v)                  BM_I2C_STAT_BUS_FREE_IRQ_SUMMARY
+#define BP_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY               6
+#define BM_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY               0x40
+#define BV_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY__NO_REQUEST   0x0
+#define BV_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY__REQUEST      0x1
+#define BF_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY(v)            (((v) & 0x1) << 6)
+#define BFM_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY(v)           BM_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY
+#define BF_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY_V(e)          BF_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY(BV_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY__##e)
+#define BFM_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY_V(v)         BM_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY
+#define BP_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY                    5
+#define BM_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY                    0x20
+#define BV_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY__NO_REQUEST        0x0
+#define BV_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY__REQUEST           0x1
+#define BF_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY(v)                 (((v) & 0x1) << 5)
+#define BFM_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY(v)                BM_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY
+#define BF_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY_V(e)               BF_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY(BV_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY__##e)
+#define BFM_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY_V(v)              BM_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY
+#define BP_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY              4
+#define BM_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY              0x10
+#define BV_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY__NO_REQUEST  0x0
+#define BV_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY__REQUEST     0x1
+#define BF_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY(v)           (((v) & 0x1) << 4)
+#define BFM_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY(v)          BM_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY
+#define BF_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY_V(e)         BF_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY(BV_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY__##e)
+#define BFM_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY_V(v)        BM_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY
+#define BP_I2C_STAT_EARLY_TERM_IRQ_SUMMARY                      3
+#define BM_I2C_STAT_EARLY_TERM_IRQ_SUMMARY                      0x8
+#define BV_I2C_STAT_EARLY_TERM_IRQ_SUMMARY__NO_REQUEST          0x0
+#define BV_I2C_STAT_EARLY_TERM_IRQ_SUMMARY__REQUEST             0x1
+#define BF_I2C_STAT_EARLY_TERM_IRQ_SUMMARY(v)                   (((v) & 0x1) << 3)
+#define BFM_I2C_STAT_EARLY_TERM_IRQ_SUMMARY(v)                  BM_I2C_STAT_EARLY_TERM_IRQ_SUMMARY
+#define BF_I2C_STAT_EARLY_TERM_IRQ_SUMMARY_V(e)                 BF_I2C_STAT_EARLY_TERM_IRQ_SUMMARY(BV_I2C_STAT_EARLY_TERM_IRQ_SUMMARY__##e)
+#define BFM_I2C_STAT_EARLY_TERM_IRQ_SUMMARY_V(v)                BM_I2C_STAT_EARLY_TERM_IRQ_SUMMARY
+#define BP_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY                     2
+#define BM_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY                     0x4
+#define BV_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY__NO_REQUEST         0x0
+#define BV_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY__REQUEST            0x1
+#define BF_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY(v)                  (((v) & 0x1) << 2)
+#define BFM_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY(v)                 BM_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY
+#define BF_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY_V(e)                BF_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY(BV_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY__##e)
+#define BFM_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY_V(v)               BM_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY
+#define BP_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY                      1
+#define BM_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY                      0x2
+#define BV_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY__NO_REQUEST          0x0
+#define BV_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY__REQUEST             0x1
+#define BF_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY(v)                   (((v) & 0x1) << 1)
+#define BFM_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY(v)                  BM_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY
+#define BF_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY_V(e)                 BF_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY(BV_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY__##e)
+#define BFM_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY_V(v)                BM_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY
+#define BP_I2C_STAT_SLAVE_IRQ_SUMMARY                           0
+#define BM_I2C_STAT_SLAVE_IRQ_SUMMARY                           0x1
+#define BV_I2C_STAT_SLAVE_IRQ_SUMMARY__NO_REQUEST               0x0
+#define BV_I2C_STAT_SLAVE_IRQ_SUMMARY__REQUEST                  0x1
+#define BF_I2C_STAT_SLAVE_IRQ_SUMMARY(v)                        (((v) & 0x1) << 0)
+#define BFM_I2C_STAT_SLAVE_IRQ_SUMMARY(v)                       BM_I2C_STAT_SLAVE_IRQ_SUMMARY
+#define BF_I2C_STAT_SLAVE_IRQ_SUMMARY_V(e)                      BF_I2C_STAT_SLAVE_IRQ_SUMMARY(BV_I2C_STAT_SLAVE_IRQ_SUMMARY__##e)
+#define BFM_I2C_STAT_SLAVE_IRQ_SUMMARY_V(v)                     BM_I2C_STAT_SLAVE_IRQ_SUMMARY
+
+#define HW_I2C_DATA             HW(I2C_DATA)
+#define HWA_I2C_DATA            (0x80058000 + 0x60)
+#define HWT_I2C_DATA            HWIO_32_RW
+#define HWN_I2C_DATA            I2C_DATA
+#define HWI_I2C_DATA            
+#define BP_I2C_DATA_DATA        0
+#define BM_I2C_DATA_DATA        0xffffffff
+#define BF_I2C_DATA_DATA(v)     (((v) & 0xffffffff) << 0)
+#define BFM_I2C_DATA_DATA(v)    BM_I2C_DATA_DATA
+#define BF_I2C_DATA_DATA_V(e)   BF_I2C_DATA_DATA(BV_I2C_DATA_DATA__##e)
+#define BFM_I2C_DATA_DATA_V(v)  BM_I2C_DATA_DATA
+
+#define HW_I2C_DEBUG0                       HW(I2C_DEBUG0)
+#define HWA_I2C_DEBUG0                      (0x80058000 + 0x70)
+#define HWT_I2C_DEBUG0                      HWIO_32_RW
+#define HWN_I2C_DEBUG0                      I2C_DEBUG0
+#define HWI_I2C_DEBUG0                      
+#define HW_I2C_DEBUG0_SET                   HW(I2C_DEBUG0_SET)
+#define HWA_I2C_DEBUG0_SET                  (HWA_I2C_DEBUG0 + 0x4)
+#define HWT_I2C_DEBUG0_SET                  HWIO_32_WO
+#define HWN_I2C_DEBUG0_SET                  I2C_DEBUG0
+#define HWI_I2C_DEBUG0_SET                  
+#define HW_I2C_DEBUG0_CLR                   HW(I2C_DEBUG0_CLR)
+#define HWA_I2C_DEBUG0_CLR                  (HWA_I2C_DEBUG0 + 0x8)
+#define HWT_I2C_DEBUG0_CLR                  HWIO_32_WO
+#define HWN_I2C_DEBUG0_CLR                  I2C_DEBUG0
+#define HWI_I2C_DEBUG0_CLR                  
+#define HW_I2C_DEBUG0_TOG                   HW(I2C_DEBUG0_TOG)
+#define HWA_I2C_DEBUG0_TOG                  (HWA_I2C_DEBUG0 + 0xc)
+#define HWT_I2C_DEBUG0_TOG                  HWIO_32_WO
+#define HWN_I2C_DEBUG0_TOG                  I2C_DEBUG0
+#define HWI_I2C_DEBUG0_TOG                  
+#define BP_I2C_DEBUG0_DMAREQ                31
+#define BM_I2C_DEBUG0_DMAREQ                0x80000000
+#define BF_I2C_DEBUG0_DMAREQ(v)             (((v) & 0x1) << 31)
+#define BFM_I2C_DEBUG0_DMAREQ(v)            BM_I2C_DEBUG0_DMAREQ
+#define BF_I2C_DEBUG0_DMAREQ_V(e)           BF_I2C_DEBUG0_DMAREQ(BV_I2C_DEBUG0_DMAREQ__##e)
+#define BFM_I2C_DEBUG0_DMAREQ_V(v)          BM_I2C_DEBUG0_DMAREQ
+#define BP_I2C_DEBUG0_DMAENDCMD             30
+#define BM_I2C_DEBUG0_DMAENDCMD             0x40000000
+#define BF_I2C_DEBUG0_DMAENDCMD(v)          (((v) & 0x1) << 30)
+#define BFM_I2C_DEBUG0_DMAENDCMD(v)         BM_I2C_DEBUG0_DMAENDCMD
+#define BF_I2C_DEBUG0_DMAENDCMD_V(e)        BF_I2C_DEBUG0_DMAENDCMD(BV_I2C_DEBUG0_DMAENDCMD__##e)
+#define BFM_I2C_DEBUG0_DMAENDCMD_V(v)       BM_I2C_DEBUG0_DMAENDCMD
+#define BP_I2C_DEBUG0_DMAKICK               29
+#define BM_I2C_DEBUG0_DMAKICK               0x20000000
+#define BF_I2C_DEBUG0_DMAKICK(v)            (((v) & 0x1) << 29)
+#define BFM_I2C_DEBUG0_DMAKICK(v)           BM_I2C_DEBUG0_DMAKICK
+#define BF_I2C_DEBUG0_DMAKICK_V(e)          BF_I2C_DEBUG0_DMAKICK(BV_I2C_DEBUG0_DMAKICK__##e)
+#define BFM_I2C_DEBUG0_DMAKICK_V(v)         BM_I2C_DEBUG0_DMAKICK
+#define BP_I2C_DEBUG0_TBD                   26
+#define BM_I2C_DEBUG0_TBD                   0x1c000000
+#define BF_I2C_DEBUG0_TBD(v)                (((v) & 0x7) << 26)
+#define BFM_I2C_DEBUG0_TBD(v)               BM_I2C_DEBUG0_TBD
+#define BF_I2C_DEBUG0_TBD_V(e)              BF_I2C_DEBUG0_TBD(BV_I2C_DEBUG0_TBD__##e)
+#define BFM_I2C_DEBUG0_TBD_V(v)             BM_I2C_DEBUG0_TBD
+#define BP_I2C_DEBUG0_DMA_STATE             16
+#define BM_I2C_DEBUG0_DMA_STATE             0x3ff0000
+#define BF_I2C_DEBUG0_DMA_STATE(v)          (((v) & 0x3ff) << 16)
+#define BFM_I2C_DEBUG0_DMA_STATE(v)         BM_I2C_DEBUG0_DMA_STATE
+#define BF_I2C_DEBUG0_DMA_STATE_V(e)        BF_I2C_DEBUG0_DMA_STATE(BV_I2C_DEBUG0_DMA_STATE__##e)
+#define BFM_I2C_DEBUG0_DMA_STATE_V(v)       BM_I2C_DEBUG0_DMA_STATE
+#define BP_I2C_DEBUG0_START_TOGGLE          15
+#define BM_I2C_DEBUG0_START_TOGGLE          0x8000
+#define BF_I2C_DEBUG0_START_TOGGLE(v)       (((v) & 0x1) << 15)
+#define BFM_I2C_DEBUG0_START_TOGGLE(v)      BM_I2C_DEBUG0_START_TOGGLE
+#define BF_I2C_DEBUG0_START_TOGGLE_V(e)     BF_I2C_DEBUG0_START_TOGGLE(BV_I2C_DEBUG0_START_TOGGLE__##e)
+#define BFM_I2C_DEBUG0_START_TOGGLE_V(v)    BM_I2C_DEBUG0_START_TOGGLE
+#define BP_I2C_DEBUG0_STOP_TOGGLE           14
+#define BM_I2C_DEBUG0_STOP_TOGGLE           0x4000
+#define BF_I2C_DEBUG0_STOP_TOGGLE(v)        (((v) & 0x1) << 14)
+#define BFM_I2C_DEBUG0_STOP_TOGGLE(v)       BM_I2C_DEBUG0_STOP_TOGGLE
+#define BF_I2C_DEBUG0_STOP_TOGGLE_V(e)      BF_I2C_DEBUG0_STOP_TOGGLE(BV_I2C_DEBUG0_STOP_TOGGLE__##e)
+#define BFM_I2C_DEBUG0_STOP_TOGGLE_V(v)     BM_I2C_DEBUG0_STOP_TOGGLE
+#define BP_I2C_DEBUG0_GRAB_TOGGLE           13
+#define BM_I2C_DEBUG0_GRAB_TOGGLE           0x2000
+#define BF_I2C_DEBUG0_GRAB_TOGGLE(v)        (((v) & 0x1) << 13)
+#define BFM_I2C_DEBUG0_GRAB_TOGGLE(v)       BM_I2C_DEBUG0_GRAB_TOGGLE
+#define BF_I2C_DEBUG0_GRAB_TOGGLE_V(e)      BF_I2C_DEBUG0_GRAB_TOGGLE(BV_I2C_DEBUG0_GRAB_TOGGLE__##e)
+#define BFM_I2C_DEBUG0_GRAB_TOGGLE_V(v)     BM_I2C_DEBUG0_GRAB_TOGGLE
+#define BP_I2C_DEBUG0_CHANGE_TOGGLE         12
+#define BM_I2C_DEBUG0_CHANGE_TOGGLE         0x1000
+#define BF_I2C_DEBUG0_CHANGE_TOGGLE(v)      (((v) & 0x1) << 12)
+#define BFM_I2C_DEBUG0_CHANGE_TOGGLE(v)     BM_I2C_DEBUG0_CHANGE_TOGGLE
+#define BF_I2C_DEBUG0_CHANGE_TOGGLE_V(e)    BF_I2C_DEBUG0_CHANGE_TOGGLE(BV_I2C_DEBUG0_CHANGE_TOGGLE__##e)
+#define BFM_I2C_DEBUG0_CHANGE_TOGGLE_V(v)   BM_I2C_DEBUG0_CHANGE_TOGGLE
+#define BP_I2C_DEBUG0_TESTMODE              11
+#define BM_I2C_DEBUG0_TESTMODE              0x800
+#define BF_I2C_DEBUG0_TESTMODE(v)           (((v) & 0x1) << 11)
+#define BFM_I2C_DEBUG0_TESTMODE(v)          BM_I2C_DEBUG0_TESTMODE
+#define BF_I2C_DEBUG0_TESTMODE_V(e)         BF_I2C_DEBUG0_TESTMODE(BV_I2C_DEBUG0_TESTMODE__##e)
+#define BFM_I2C_DEBUG0_TESTMODE_V(v)        BM_I2C_DEBUG0_TESTMODE
+#define BP_I2C_DEBUG0_SLAVE_HOLD_CLK        10
+#define BM_I2C_DEBUG0_SLAVE_HOLD_CLK        0x400
+#define BF_I2C_DEBUG0_SLAVE_HOLD_CLK(v)     (((v) & 0x1) << 10)
+#define BFM_I2C_DEBUG0_SLAVE_HOLD_CLK(v)    BM_I2C_DEBUG0_SLAVE_HOLD_CLK
+#define BF_I2C_DEBUG0_SLAVE_HOLD_CLK_V(e)   BF_I2C_DEBUG0_SLAVE_HOLD_CLK(BV_I2C_DEBUG0_SLAVE_HOLD_CLK__##e)
+#define BFM_I2C_DEBUG0_SLAVE_HOLD_CLK_V(v)  BM_I2C_DEBUG0_SLAVE_HOLD_CLK
+#define BP_I2C_DEBUG0_SLAVE_STATE           0
+#define BM_I2C_DEBUG0_SLAVE_STATE           0x3ff
+#define BF_I2C_DEBUG0_SLAVE_STATE(v)        (((v) & 0x3ff) << 0)
+#define BFM_I2C_DEBUG0_SLAVE_STATE(v)       BM_I2C_DEBUG0_SLAVE_STATE
+#define BF_I2C_DEBUG0_SLAVE_STATE_V(e)      BF_I2C_DEBUG0_SLAVE_STATE(BV_I2C_DEBUG0_SLAVE_STATE__##e)
+#define BFM_I2C_DEBUG0_SLAVE_STATE_V(v)     BM_I2C_DEBUG0_SLAVE_STATE
+
+#define HW_I2C_DEBUG1                           HW(I2C_DEBUG1)
+#define HWA_I2C_DEBUG1                          (0x80058000 + 0x80)
+#define HWT_I2C_DEBUG1                          HWIO_32_RW
+#define HWN_I2C_DEBUG1                          I2C_DEBUG1
+#define HWI_I2C_DEBUG1                          
+#define HW_I2C_DEBUG1_SET                       HW(I2C_DEBUG1_SET)
+#define HWA_I2C_DEBUG1_SET                      (HWA_I2C_DEBUG1 + 0x4)
+#define HWT_I2C_DEBUG1_SET                      HWIO_32_WO
+#define HWN_I2C_DEBUG1_SET                      I2C_DEBUG1
+#define HWI_I2C_DEBUG1_SET                      
+#define HW_I2C_DEBUG1_CLR                       HW(I2C_DEBUG1_CLR)
+#define HWA_I2C_DEBUG1_CLR                      (HWA_I2C_DEBUG1 + 0x8)
+#define HWT_I2C_DEBUG1_CLR                      HWIO_32_WO
+#define HWN_I2C_DEBUG1_CLR                      I2C_DEBUG1
+#define HWI_I2C_DEBUG1_CLR                      
+#define HW_I2C_DEBUG1_TOG                       HW(I2C_DEBUG1_TOG)
+#define HWA_I2C_DEBUG1_TOG                      (HWA_I2C_DEBUG1 + 0xc)
+#define HWT_I2C_DEBUG1_TOG                      HWIO_32_WO
+#define HWN_I2C_DEBUG1_TOG                      I2C_DEBUG1
+#define HWI_I2C_DEBUG1_TOG                      
+#define BP_I2C_DEBUG1_I2C_CLK_IN                31
+#define BM_I2C_DEBUG1_I2C_CLK_IN                0x80000000
+#define BF_I2C_DEBUG1_I2C_CLK_IN(v)             (((v) & 0x1) << 31)
+#define BFM_I2C_DEBUG1_I2C_CLK_IN(v)            BM_I2C_DEBUG1_I2C_CLK_IN
+#define BF_I2C_DEBUG1_I2C_CLK_IN_V(e)           BF_I2C_DEBUG1_I2C_CLK_IN(BV_I2C_DEBUG1_I2C_CLK_IN__##e)
+#define BFM_I2C_DEBUG1_I2C_CLK_IN_V(v)          BM_I2C_DEBUG1_I2C_CLK_IN
+#define BP_I2C_DEBUG1_I2C_DATA_IN               30
+#define BM_I2C_DEBUG1_I2C_DATA_IN               0x40000000
+#define BF_I2C_DEBUG1_I2C_DATA_IN(v)            (((v) & 0x1) << 30)
+#define BFM_I2C_DEBUG1_I2C_DATA_IN(v)           BM_I2C_DEBUG1_I2C_DATA_IN
+#define BF_I2C_DEBUG1_I2C_DATA_IN_V(e)          BF_I2C_DEBUG1_I2C_DATA_IN(BV_I2C_DEBUG1_I2C_DATA_IN__##e)
+#define BFM_I2C_DEBUG1_I2C_DATA_IN_V(v)         BM_I2C_DEBUG1_I2C_DATA_IN
+#define BP_I2C_DEBUG1_DMA_BYTE_ENABLES          24
+#define BM_I2C_DEBUG1_DMA_BYTE_ENABLES          0xf000000
+#define BF_I2C_DEBUG1_DMA_BYTE_ENABLES(v)       (((v) & 0xf) << 24)
+#define BFM_I2C_DEBUG1_DMA_BYTE_ENABLES(v)      BM_I2C_DEBUG1_DMA_BYTE_ENABLES
+#define BF_I2C_DEBUG1_DMA_BYTE_ENABLES_V(e)     BF_I2C_DEBUG1_DMA_BYTE_ENABLES(BV_I2C_DEBUG1_DMA_BYTE_ENABLES__##e)
+#define BFM_I2C_DEBUG1_DMA_BYTE_ENABLES_V(v)    BM_I2C_DEBUG1_DMA_BYTE_ENABLES
+#define BP_I2C_DEBUG1_CLK_GEN_STATE             16
+#define BM_I2C_DEBUG1_CLK_GEN_STATE             0x7f0000
+#define BF_I2C_DEBUG1_CLK_GEN_STATE(v)          (((v) & 0x7f) << 16)
+#define BFM_I2C_DEBUG1_CLK_GEN_STATE(v)         BM_I2C_DEBUG1_CLK_GEN_STATE
+#define BF_I2C_DEBUG1_CLK_GEN_STATE_V(e)        BF_I2C_DEBUG1_CLK_GEN_STATE(BV_I2C_DEBUG1_CLK_GEN_STATE__##e)
+#define BFM_I2C_DEBUG1_CLK_GEN_STATE_V(v)       BM_I2C_DEBUG1_CLK_GEN_STATE
+#define BP_I2C_DEBUG1_LST_MODE                  9
+#define BM_I2C_DEBUG1_LST_MODE                  0x600
+#define BV_I2C_DEBUG1_LST_MODE__BCAST           0x0
+#define BV_I2C_DEBUG1_LST_MODE__MY_WRITE        0x1
+#define BV_I2C_DEBUG1_LST_MODE__MY_READ         0x2
+#define BV_I2C_DEBUG1_LST_MODE__NOT_ME          0x3
+#define BF_I2C_DEBUG1_LST_MODE(v)               (((v) & 0x3) << 9)
+#define BFM_I2C_DEBUG1_LST_MODE(v)              BM_I2C_DEBUG1_LST_MODE
+#define BF_I2C_DEBUG1_LST_MODE_V(e)             BF_I2C_DEBUG1_LST_MODE(BV_I2C_DEBUG1_LST_MODE__##e)
+#define BFM_I2C_DEBUG1_LST_MODE_V(v)            BM_I2C_DEBUG1_LST_MODE
+#define BP_I2C_DEBUG1_LOCAL_SLAVE_TEST          8
+#define BM_I2C_DEBUG1_LOCAL_SLAVE_TEST          0x100
+#define BF_I2C_DEBUG1_LOCAL_SLAVE_TEST(v)       (((v) & 0x1) << 8)
+#define BFM_I2C_DEBUG1_LOCAL_SLAVE_TEST(v)      BM_I2C_DEBUG1_LOCAL_SLAVE_TEST
+#define BF_I2C_DEBUG1_LOCAL_SLAVE_TEST_V(e)     BF_I2C_DEBUG1_LOCAL_SLAVE_TEST(BV_I2C_DEBUG1_LOCAL_SLAVE_TEST__##e)
+#define BFM_I2C_DEBUG1_LOCAL_SLAVE_TEST_V(v)    BM_I2C_DEBUG1_LOCAL_SLAVE_TEST
+#define BP_I2C_DEBUG1_FORCE_CLK_ON              5
+#define BM_I2C_DEBUG1_FORCE_CLK_ON              0x20
+#define BF_I2C_DEBUG1_FORCE_CLK_ON(v)           (((v) & 0x1) << 5)
+#define BFM_I2C_DEBUG1_FORCE_CLK_ON(v)          BM_I2C_DEBUG1_FORCE_CLK_ON
+#define BF_I2C_DEBUG1_FORCE_CLK_ON_V(e)         BF_I2C_DEBUG1_FORCE_CLK_ON(BV_I2C_DEBUG1_FORCE_CLK_ON__##e)
+#define BFM_I2C_DEBUG1_FORCE_CLK_ON_V(v)        BM_I2C_DEBUG1_FORCE_CLK_ON
+#define BP_I2C_DEBUG1_FORCE_CLK_IDLE            4
+#define BM_I2C_DEBUG1_FORCE_CLK_IDLE            0x10
+#define BF_I2C_DEBUG1_FORCE_CLK_IDLE(v)         (((v) & 0x1) << 4)
+#define BFM_I2C_DEBUG1_FORCE_CLK_IDLE(v)        BM_I2C_DEBUG1_FORCE_CLK_IDLE
+#define BF_I2C_DEBUG1_FORCE_CLK_IDLE_V(e)       BF_I2C_DEBUG1_FORCE_CLK_IDLE(BV_I2C_DEBUG1_FORCE_CLK_IDLE__##e)
+#define BFM_I2C_DEBUG1_FORCE_CLK_IDLE_V(v)      BM_I2C_DEBUG1_FORCE_CLK_IDLE
+#define BP_I2C_DEBUG1_FORCE_ARB_LOSS            3
+#define BM_I2C_DEBUG1_FORCE_ARB_LOSS            0x8
+#define BF_I2C_DEBUG1_FORCE_ARB_LOSS(v)         (((v) & 0x1) << 3)
+#define BFM_I2C_DEBUG1_FORCE_ARB_LOSS(v)        BM_I2C_DEBUG1_FORCE_ARB_LOSS
+#define BF_I2C_DEBUG1_FORCE_ARB_LOSS_V(e)       BF_I2C_DEBUG1_FORCE_ARB_LOSS(BV_I2C_DEBUG1_FORCE_ARB_LOSS__##e)
+#define BFM_I2C_DEBUG1_FORCE_ARB_LOSS_V(v)      BM_I2C_DEBUG1_FORCE_ARB_LOSS
+#define BP_I2C_DEBUG1_FORCE_RCV_ACK             2
+#define BM_I2C_DEBUG1_FORCE_RCV_ACK             0x4
+#define BF_I2C_DEBUG1_FORCE_RCV_ACK(v)          (((v) & 0x1) << 2)
+#define BFM_I2C_DEBUG1_FORCE_RCV_ACK(v)         BM_I2C_DEBUG1_FORCE_RCV_ACK
+#define BF_I2C_DEBUG1_FORCE_RCV_ACK_V(e)        BF_I2C_DEBUG1_FORCE_RCV_ACK(BV_I2C_DEBUG1_FORCE_RCV_ACK__##e)
+#define BFM_I2C_DEBUG1_FORCE_RCV_ACK_V(v)       BM_I2C_DEBUG1_FORCE_RCV_ACK
+#define BP_I2C_DEBUG1_FORCE_I2C_DATA_OE         1
+#define BM_I2C_DEBUG1_FORCE_I2C_DATA_OE         0x2
+#define BF_I2C_DEBUG1_FORCE_I2C_DATA_OE(v)      (((v) & 0x1) << 1)
+#define BFM_I2C_DEBUG1_FORCE_I2C_DATA_OE(v)     BM_I2C_DEBUG1_FORCE_I2C_DATA_OE
+#define BF_I2C_DEBUG1_FORCE_I2C_DATA_OE_V(e)    BF_I2C_DEBUG1_FORCE_I2C_DATA_OE(BV_I2C_DEBUG1_FORCE_I2C_DATA_OE__##e)
+#define BFM_I2C_DEBUG1_FORCE_I2C_DATA_OE_V(v)   BM_I2C_DEBUG1_FORCE_I2C_DATA_OE
+#define BP_I2C_DEBUG1_FORCE_I2C_CLK_OE          0
+#define BM_I2C_DEBUG1_FORCE_I2C_CLK_OE          0x1
+#define BF_I2C_DEBUG1_FORCE_I2C_CLK_OE(v)       (((v) & 0x1) << 0)
+#define BFM_I2C_DEBUG1_FORCE_I2C_CLK_OE(v)      BM_I2C_DEBUG1_FORCE_I2C_CLK_OE
+#define BF_I2C_DEBUG1_FORCE_I2C_CLK_OE_V(e)     BF_I2C_DEBUG1_FORCE_I2C_CLK_OE(BV_I2C_DEBUG1_FORCE_I2C_CLK_OE__##e)
+#define BFM_I2C_DEBUG1_FORCE_I2C_CLK_OE_V(v)    BM_I2C_DEBUG1_FORCE_I2C_CLK_OE
+
+#endif /* __HEADERGEN_STMP3600_I2C_H__*/
diff --git a/firmware/target/arm/imx233/regs/stmp3600/icoll.h b/firmware/target/arm/imx233/regs/stmp3600/icoll.h
new file mode 100644
index 0000000000..b948a5b205
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3600/icoll.h
@@ -0,0 +1,475 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * stmp3600 version: 2.4.0
+ * stmp3600 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_STMP3600_ICOLL_H__
+#define __HEADERGEN_STMP3600_ICOLL_H__
+
+#define HW_ICOLL_VECTOR                 HW(ICOLL_VECTOR)
+#define HWA_ICOLL_VECTOR                (0x80000000 + 0x0)
+#define HWT_ICOLL_VECTOR                HWIO_32_RW
+#define HWN_ICOLL_VECTOR                ICOLL_VECTOR
+#define HWI_ICOLL_VECTOR                
+#define HW_ICOLL_VECTOR_SET             HW(ICOLL_VECTOR_SET)
+#define HWA_ICOLL_VECTOR_SET            (HWA_ICOLL_VECTOR + 0x4)
+#define HWT_ICOLL_VECTOR_SET            HWIO_32_WO
+#define HWN_ICOLL_VECTOR_SET            ICOLL_VECTOR
+#define HWI_ICOLL_VECTOR_SET            
+#define HW_ICOLL_VECTOR_CLR             HW(ICOLL_VECTOR_CLR)
+#define HWA_ICOLL_VECTOR_CLR            (HWA_ICOLL_VECTOR + 0x8)
+#define HWT_ICOLL_VECTOR_CLR            HWIO_32_WO
+#define HWN_ICOLL_VECTOR_CLR            ICOLL_VECTOR
+#define HWI_ICOLL_VECTOR_CLR            
+#define HW_ICOLL_VECTOR_TOG             HW(ICOLL_VECTOR_TOG)
+#define HWA_ICOLL_VECTOR_TOG            (HWA_ICOLL_VECTOR + 0xc)
+#define HWT_ICOLL_VECTOR_TOG            HWIO_32_WO
+#define HWN_ICOLL_VECTOR_TOG            ICOLL_VECTOR
+#define HWI_ICOLL_VECTOR_TOG            
+#define BP_ICOLL_VECTOR_IRQVECTOR       2
+#define BM_ICOLL_VECTOR_IRQVECTOR       0xfffffffc
+#define BF_ICOLL_VECTOR_IRQVECTOR(v)    (((v) & 0x3fffffff) << 2)
+#define BFM_ICOLL_VECTOR_IRQVECTOR(v)   BM_ICOLL_VECTOR_IRQVECTOR
+#define BF_ICOLL_VECTOR_IRQVECTOR_V(e)  BF_ICOLL_VECTOR_IRQVECTOR(BV_ICOLL_VECTOR_IRQVECTOR__##e)
+#define BFM_ICOLL_VECTOR_IRQVECTOR_V(v) BM_ICOLL_VECTOR_IRQVECTOR
+
+#define HW_ICOLL_LEVELACK                       HW(ICOLL_LEVELACK)
+#define HWA_ICOLL_LEVELACK                      (0x80000000 + 0x10)
+#define HWT_ICOLL_LEVELACK                      HWIO_32_RW
+#define HWN_ICOLL_LEVELACK                      ICOLL_LEVELACK
+#define HWI_ICOLL_LEVELACK                      
+#define BP_ICOLL_LEVELACK_IRQLEVELACK           0
+#define BM_ICOLL_LEVELACK_IRQLEVELACK           0xf
+#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0   0x1
+#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL1   0x2
+#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL2   0x4
+#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL3   0x8
+#define BF_ICOLL_LEVELACK_IRQLEVELACK(v)        (((v) & 0xf) << 0)
+#define BFM_ICOLL_LEVELACK_IRQLEVELACK(v)       BM_ICOLL_LEVELACK_IRQLEVELACK
+#define BF_ICOLL_LEVELACK_IRQLEVELACK_V(e)      BF_ICOLL_LEVELACK_IRQLEVELACK(BV_ICOLL_LEVELACK_IRQLEVELACK__##e)
+#define BFM_ICOLL_LEVELACK_IRQLEVELACK_V(v)     BM_ICOLL_LEVELACK_IRQLEVELACK
+
+#define HW_ICOLL_CTRL                                   HW(ICOLL_CTRL)
+#define HWA_ICOLL_CTRL                                  (0x80000000 + 0x20)
+#define HWT_ICOLL_CTRL                                  HWIO_32_RW
+#define HWN_ICOLL_CTRL                                  ICOLL_CTRL
+#define HWI_ICOLL_CTRL                                  
+#define HW_ICOLL_CTRL_SET                               HW(ICOLL_CTRL_SET)
+#define HWA_ICOLL_CTRL_SET                              (HWA_ICOLL_CTRL + 0x4)
+#define HWT_ICOLL_CTRL_SET                              HWIO_32_WO
+#define HWN_ICOLL_CTRL_SET                              ICOLL_CTRL
+#define HWI_ICOLL_CTRL_SET                              
+#define HW_ICOLL_CTRL_CLR                               HW(ICOLL_CTRL_CLR)
+#define HWA_ICOLL_CTRL_CLR                              (HWA_ICOLL_CTRL + 0x8)
+#define HWT_ICOLL_CTRL_CLR                              HWIO_32_WO
+#define HWN_ICOLL_CTRL_CLR                              ICOLL_CTRL
+#define HWI_ICOLL_CTRL_CLR                              
+#define HW_ICOLL_CTRL_TOG                               HW(ICOLL_CTRL_TOG)
+#define HWA_ICOLL_CTRL_TOG                              (HWA_ICOLL_CTRL + 0xc)
+#define HWT_ICOLL_CTRL_TOG                              HWIO_32_WO
+#define HWN_ICOLL_CTRL_TOG                              ICOLL_CTRL
+#define HWI_ICOLL_CTRL_TOG                              
+#define BP_ICOLL_CTRL_SFTRST                            31
+#define BM_ICOLL_CTRL_SFTRST                            0x80000000
+#define BV_ICOLL_CTRL_SFTRST__RUN                       0x0
+#define BV_ICOLL_CTRL_SFTRST__IN_RESET                  0x1
+#define BF_ICOLL_CTRL_SFTRST(v)                         (((v) & 0x1) << 31)
+#define BFM_ICOLL_CTRL_SFTRST(v)                        BM_ICOLL_CTRL_SFTRST
+#define BF_ICOLL_CTRL_SFTRST_V(e)                       BF_ICOLL_CTRL_SFTRST(BV_ICOLL_CTRL_SFTRST__##e)
+#define BFM_ICOLL_CTRL_SFTRST_V(v)                      BM_ICOLL_CTRL_SFTRST
+#define BP_ICOLL_CTRL_CLKGATE                           30
+#define BM_ICOLL_CTRL_CLKGATE                           0x40000000
+#define BV_ICOLL_CTRL_CLKGATE__RUN                      0x0
+#define BV_ICOLL_CTRL_CLKGATE__NO_CLOCKS                0x1
+#define BF_ICOLL_CTRL_CLKGATE(v)                        (((v) & 0x1) << 30)
+#define BFM_ICOLL_CTRL_CLKGATE(v)                       BM_ICOLL_CTRL_CLKGATE
+#define BF_ICOLL_CTRL_CLKGATE_V(e)                      BF_ICOLL_CTRL_CLKGATE(BV_ICOLL_CTRL_CLKGATE__##e)
+#define BFM_ICOLL_CTRL_CLKGATE_V(v)                     BM_ICOLL_CTRL_CLKGATE
+#define BP_ICOLL_CTRL_ENABLE2FIQ35                      27
+#define BM_ICOLL_CTRL_ENABLE2FIQ35                      0x8000000
+#define BV_ICOLL_CTRL_ENABLE2FIQ35__DISABLE             0x0
+#define BV_ICOLL_CTRL_ENABLE2FIQ35__ENABLE              0x1
+#define BF_ICOLL_CTRL_ENABLE2FIQ35(v)                   (((v) & 0x1) << 27)
+#define BFM_ICOLL_CTRL_ENABLE2FIQ35(v)                  BM_ICOLL_CTRL_ENABLE2FIQ35
+#define BF_ICOLL_CTRL_ENABLE2FIQ35_V(e)                 BF_ICOLL_CTRL_ENABLE2FIQ35(BV_ICOLL_CTRL_ENABLE2FIQ35__##e)
+#define BFM_ICOLL_CTRL_ENABLE2FIQ35_V(v)                BM_ICOLL_CTRL_ENABLE2FIQ35
+#define BP_ICOLL_CTRL_ENABLE2FIQ34                      26
+#define BM_ICOLL_CTRL_ENABLE2FIQ34                      0x4000000
+#define BV_ICOLL_CTRL_ENABLE2FIQ34__DISABLE             0x0
+#define BV_ICOLL_CTRL_ENABLE2FIQ34__ENABLE              0x1
+#define BF_ICOLL_CTRL_ENABLE2FIQ34(v)                   (((v) & 0x1) << 26)
+#define BFM_ICOLL_CTRL_ENABLE2FIQ34(v)                  BM_ICOLL_CTRL_ENABLE2FIQ34
+#define BF_ICOLL_CTRL_ENABLE2FIQ34_V(e)                 BF_ICOLL_CTRL_ENABLE2FIQ34(BV_ICOLL_CTRL_ENABLE2FIQ34__##e)
+#define BFM_ICOLL_CTRL_ENABLE2FIQ34_V(v)                BM_ICOLL_CTRL_ENABLE2FIQ34
+#define BP_ICOLL_CTRL_ENABLE2FIQ33                      25
+#define BM_ICOLL_CTRL_ENABLE2FIQ33                      0x2000000
+#define BV_ICOLL_CTRL_ENABLE2FIQ33__DISABLE             0x0
+#define BV_ICOLL_CTRL_ENABLE2FIQ33__ENABLE              0x1
+#define BF_ICOLL_CTRL_ENABLE2FIQ33(v)                   (((v) & 0x1) << 25)
+#define BFM_ICOLL_CTRL_ENABLE2FIQ33(v)                  BM_ICOLL_CTRL_ENABLE2FIQ33
+#define BF_ICOLL_CTRL_ENABLE2FIQ33_V(e)                 BF_ICOLL_CTRL_ENABLE2FIQ33(BV_ICOLL_CTRL_ENABLE2FIQ33__##e)
+#define BFM_ICOLL_CTRL_ENABLE2FIQ33_V(v)                BM_ICOLL_CTRL_ENABLE2FIQ33
+#define BP_ICOLL_CTRL_ENABLE2FIQ32                      24
+#define BM_ICOLL_CTRL_ENABLE2FIQ32                      0x1000000
+#define BV_ICOLL_CTRL_ENABLE2FIQ32__DISABLE             0x0
+#define BV_ICOLL_CTRL_ENABLE2FIQ32__ENABLE              0x1
+#define BF_ICOLL_CTRL_ENABLE2FIQ32(v)                   (((v) & 0x1) << 24)
+#define BFM_ICOLL_CTRL_ENABLE2FIQ32(v)                  BM_ICOLL_CTRL_ENABLE2FIQ32
+#define BF_ICOLL_CTRL_ENABLE2FIQ32_V(e)                 BF_ICOLL_CTRL_ENABLE2FIQ32(BV_ICOLL_CTRL_ENABLE2FIQ32__##e)
+#define BFM_ICOLL_CTRL_ENABLE2FIQ32_V(v)                BM_ICOLL_CTRL_ENABLE2FIQ32
+#define BP_ICOLL_CTRL_BYPASS_FSM                        20
+#define BM_ICOLL_CTRL_BYPASS_FSM                        0x100000
+#define BV_ICOLL_CTRL_BYPASS_FSM__NORMAL                0x0
+#define BV_ICOLL_CTRL_BYPASS_FSM__BYPASS                0x1
+#define BF_ICOLL_CTRL_BYPASS_FSM(v)                     (((v) & 0x1) << 20)
+#define BFM_ICOLL_CTRL_BYPASS_FSM(v)                    BM_ICOLL_CTRL_BYPASS_FSM
+#define BF_ICOLL_CTRL_BYPASS_FSM_V(e)                   BF_ICOLL_CTRL_BYPASS_FSM(BV_ICOLL_CTRL_BYPASS_FSM__##e)
+#define BFM_ICOLL_CTRL_BYPASS_FSM_V(v)                  BM_ICOLL_CTRL_BYPASS_FSM
+#define BP_ICOLL_CTRL_NO_NESTING                        19
+#define BM_ICOLL_CTRL_NO_NESTING                        0x80000
+#define BV_ICOLL_CTRL_NO_NESTING__NORMAL                0x0
+#define BV_ICOLL_CTRL_NO_NESTING__NO_NEST               0x1
+#define BF_ICOLL_CTRL_NO_NESTING(v)                     (((v) & 0x1) << 19)
+#define BFM_ICOLL_CTRL_NO_NESTING(v)                    BM_ICOLL_CTRL_NO_NESTING
+#define BF_ICOLL_CTRL_NO_NESTING_V(e)                   BF_ICOLL_CTRL_NO_NESTING(BV_ICOLL_CTRL_NO_NESTING__##e)
+#define BFM_ICOLL_CTRL_NO_NESTING_V(v)                  BM_ICOLL_CTRL_NO_NESTING
+#define BP_ICOLL_CTRL_ARM_RSE_MODE                      18
+#define BM_ICOLL_CTRL_ARM_RSE_MODE                      0x40000
+#define BV_ICOLL_CTRL_ARM_RSE_MODE__MUST_WRITE          0x0
+#define BV_ICOLL_CTRL_ARM_RSE_MODE__READ_SIDE_EFFECT    0x1
+#define BF_ICOLL_CTRL_ARM_RSE_MODE(v)                   (((v) & 0x1) << 18)
+#define BFM_ICOLL_CTRL_ARM_RSE_MODE(v)                  BM_ICOLL_CTRL_ARM_RSE_MODE
+#define BF_ICOLL_CTRL_ARM_RSE_MODE_V(e)                 BF_ICOLL_CTRL_ARM_RSE_MODE(BV_ICOLL_CTRL_ARM_RSE_MODE__##e)
+#define BFM_ICOLL_CTRL_ARM_RSE_MODE_V(v)                BM_ICOLL_CTRL_ARM_RSE_MODE
+#define BP_ICOLL_CTRL_FIQ_FINAL_ENABLE                  17
+#define BM_ICOLL_CTRL_FIQ_FINAL_ENABLE                  0x20000
+#define BV_ICOLL_CTRL_FIQ_FINAL_ENABLE__DISABLE         0x0
+#define BV_ICOLL_CTRL_FIQ_FINAL_ENABLE__ENABLE          0x1
+#define BF_ICOLL_CTRL_FIQ_FINAL_ENABLE(v)               (((v) & 0x1) << 17)
+#define BFM_ICOLL_CTRL_FIQ_FINAL_ENABLE(v)              BM_ICOLL_CTRL_FIQ_FINAL_ENABLE
+#define BF_ICOLL_CTRL_FIQ_FINAL_ENABLE_V(e)             BF_ICOLL_CTRL_FIQ_FINAL_ENABLE(BV_ICOLL_CTRL_FIQ_FINAL_ENABLE__##e)
+#define BFM_ICOLL_CTRL_FIQ_FINAL_ENABLE_V(v)            BM_ICOLL_CTRL_FIQ_FINAL_ENABLE
+#define BP_ICOLL_CTRL_IRQ_FINAL_ENABLE                  16
+#define BM_ICOLL_CTRL_IRQ_FINAL_ENABLE                  0x10000
+#define BV_ICOLL_CTRL_IRQ_FINAL_ENABLE__DISABLE         0x0
+#define BV_ICOLL_CTRL_IRQ_FINAL_ENABLE__ENABLE          0x1
+#define BF_ICOLL_CTRL_IRQ_FINAL_ENABLE(v)               (((v) & 0x1) << 16)
+#define BFM_ICOLL_CTRL_IRQ_FINAL_ENABLE(v)              BM_ICOLL_CTRL_IRQ_FINAL_ENABLE
+#define BF_ICOLL_CTRL_IRQ_FINAL_ENABLE_V(e)             BF_ICOLL_CTRL_IRQ_FINAL_ENABLE(BV_ICOLL_CTRL_IRQ_FINAL_ENABLE__##e)
+#define BFM_ICOLL_CTRL_IRQ_FINAL_ENABLE_V(v)            BM_ICOLL_CTRL_IRQ_FINAL_ENABLE
+
+#define HW_ICOLL_STAT                       HW(ICOLL_STAT)
+#define HWA_ICOLL_STAT                      (0x80000000 + 0x30)
+#define HWT_ICOLL_STAT                      HWIO_32_RW
+#define HWN_ICOLL_STAT                      ICOLL_STAT
+#define HWI_ICOLL_STAT                      
+#define BP_ICOLL_STAT_VECTOR_NUMBER         0
+#define BM_ICOLL_STAT_VECTOR_NUMBER         0x3f
+#define BF_ICOLL_STAT_VECTOR_NUMBER(v)      (((v) & 0x3f) << 0)
+#define BFM_ICOLL_STAT_VECTOR_NUMBER(v)     BM_ICOLL_STAT_VECTOR_NUMBER
+#define BF_ICOLL_STAT_VECTOR_NUMBER_V(e)    BF_ICOLL_STAT_VECTOR_NUMBER(BV_ICOLL_STAT_VECTOR_NUMBER__##e)
+#define BFM_ICOLL_STAT_VECTOR_NUMBER_V(v)   BM_ICOLL_STAT_VECTOR_NUMBER
+
+#define HW_ICOLL_VBASE                      HW(ICOLL_VBASE)
+#define HWA_ICOLL_VBASE                     (0x80000000 + 0x160)
+#define HWT_ICOLL_VBASE                     HWIO_32_RW
+#define HWN_ICOLL_VBASE                     ICOLL_VBASE
+#define HWI_ICOLL_VBASE                     
+#define HW_ICOLL_VBASE_SET                  HW(ICOLL_VBASE_SET)
+#define HWA_ICOLL_VBASE_SET                 (HWA_ICOLL_VBASE + 0x4)
+#define HWT_ICOLL_VBASE_SET                 HWIO_32_WO
+#define HWN_ICOLL_VBASE_SET                 ICOLL_VBASE
+#define HWI_ICOLL_VBASE_SET                 
+#define HW_ICOLL_VBASE_CLR                  HW(ICOLL_VBASE_CLR)
+#define HWA_ICOLL_VBASE_CLR                 (HWA_ICOLL_VBASE + 0x8)
+#define HWT_ICOLL_VBASE_CLR                 HWIO_32_WO
+#define HWN_ICOLL_VBASE_CLR                 ICOLL_VBASE
+#define HWI_ICOLL_VBASE_CLR                 
+#define HW_ICOLL_VBASE_TOG                  HW(ICOLL_VBASE_TOG)
+#define HWA_ICOLL_VBASE_TOG                 (HWA_ICOLL_VBASE + 0xc)
+#define HWT_ICOLL_VBASE_TOG                 HWIO_32_WO
+#define HWN_ICOLL_VBASE_TOG                 ICOLL_VBASE
+#define HWI_ICOLL_VBASE_TOG                 
+#define BP_ICOLL_VBASE_TABLE_ADDRESS        2
+#define BM_ICOLL_VBASE_TABLE_ADDRESS        0xfffffffc
+#define BF_ICOLL_VBASE_TABLE_ADDRESS(v)     (((v) & 0x3fffffff) << 2)
+#define BFM_ICOLL_VBASE_TABLE_ADDRESS(v)    BM_ICOLL_VBASE_TABLE_ADDRESS
+#define BF_ICOLL_VBASE_TABLE_ADDRESS_V(e)   BF_ICOLL_VBASE_TABLE_ADDRESS(BV_ICOLL_VBASE_TABLE_ADDRESS__##e)
+#define BFM_ICOLL_VBASE_TABLE_ADDRESS_V(v)  BM_ICOLL_VBASE_TABLE_ADDRESS
+
+#define HW_ICOLL_DEBUG                              HW(ICOLL_DEBUG)
+#define HWA_ICOLL_DEBUG                             (0x80000000 + 0x170)
+#define HWT_ICOLL_DEBUG                             HWIO_32_RW
+#define HWN_ICOLL_DEBUG                             ICOLL_DEBUG
+#define HWI_ICOLL_DEBUG                             
+#define BP_ICOLL_DEBUG_INSERVICE                    28
+#define BM_ICOLL_DEBUG_INSERVICE                    0xf0000000
+#define BV_ICOLL_DEBUG_INSERVICE__LEVEL0            0x1
+#define BV_ICOLL_DEBUG_INSERVICE__LEVEL1            0x2
+#define BV_ICOLL_DEBUG_INSERVICE__LEVEL2            0x4
+#define BV_ICOLL_DEBUG_INSERVICE__LEVEL3            0x8
+#define BF_ICOLL_DEBUG_INSERVICE(v)                 (((v) & 0xf) << 28)
+#define BFM_ICOLL_DEBUG_INSERVICE(v)                BM_ICOLL_DEBUG_INSERVICE
+#define BF_ICOLL_DEBUG_INSERVICE_V(e)               BF_ICOLL_DEBUG_INSERVICE(BV_ICOLL_DEBUG_INSERVICE__##e)
+#define BFM_ICOLL_DEBUG_INSERVICE_V(v)              BM_ICOLL_DEBUG_INSERVICE
+#define BP_ICOLL_DEBUG_LEVEL_REQUESTS               24
+#define BM_ICOLL_DEBUG_LEVEL_REQUESTS               0xf000000
+#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL0       0x1
+#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL1       0x2
+#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL2       0x4
+#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL3       0x8
+#define BF_ICOLL_DEBUG_LEVEL_REQUESTS(v)            (((v) & 0xf) << 24)
+#define BFM_ICOLL_DEBUG_LEVEL_REQUESTS(v)           BM_ICOLL_DEBUG_LEVEL_REQUESTS
+#define BF_ICOLL_DEBUG_LEVEL_REQUESTS_V(e)          BF_ICOLL_DEBUG_LEVEL_REQUESTS(BV_ICOLL_DEBUG_LEVEL_REQUESTS__##e)
+#define BFM_ICOLL_DEBUG_LEVEL_REQUESTS_V(v)         BM_ICOLL_DEBUG_LEVEL_REQUESTS
+#define BP_ICOLL_DEBUG_REQUESTS_BY_LEVEL            20
+#define BM_ICOLL_DEBUG_REQUESTS_BY_LEVEL            0xf00000
+#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL0    0x1
+#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL1    0x2
+#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL2    0x4
+#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL3    0x8
+#define BF_ICOLL_DEBUG_REQUESTS_BY_LEVEL(v)         (((v) & 0xf) << 20)
+#define BFM_ICOLL_DEBUG_REQUESTS_BY_LEVEL(v)        BM_ICOLL_DEBUG_REQUESTS_BY_LEVEL
+#define BF_ICOLL_DEBUG_REQUESTS_BY_LEVEL_V(e)       BF_ICOLL_DEBUG_REQUESTS_BY_LEVEL(BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__##e)
+#define BFM_ICOLL_DEBUG_REQUESTS_BY_LEVEL_V(v)      BM_ICOLL_DEBUG_REQUESTS_BY_LEVEL
+#define BP_ICOLL_DEBUG_FIQ                          17
+#define BM_ICOLL_DEBUG_FIQ                          0x20000
+#define BV_ICOLL_DEBUG_FIQ__NO_FIQ_REQUESTED        0x0
+#define BV_ICOLL_DEBUG_FIQ__FIQ_REQUESTED           0x1
+#define BF_ICOLL_DEBUG_FIQ(v)                       (((v) & 0x1) << 17)
+#define BFM_ICOLL_DEBUG_FIQ(v)                      BM_ICOLL_DEBUG_FIQ
+#define BF_ICOLL_DEBUG_FIQ_V(e)                     BF_ICOLL_DEBUG_FIQ(BV_ICOLL_DEBUG_FIQ__##e)
+#define BFM_ICOLL_DEBUG_FIQ_V(v)                    BM_ICOLL_DEBUG_FIQ
+#define BP_ICOLL_DEBUG_IRQ                          16
+#define BM_ICOLL_DEBUG_IRQ                          0x10000
+#define BV_ICOLL_DEBUG_IRQ__NO_IRQ_REQUESTED        0x0
+#define BV_ICOLL_DEBUG_IRQ__IRQ_REQUESTED           0x1
+#define BF_ICOLL_DEBUG_IRQ(v)                       (((v) & 0x1) << 16)
+#define BFM_ICOLL_DEBUG_IRQ(v)                      BM_ICOLL_DEBUG_IRQ
+#define BF_ICOLL_DEBUG_IRQ_V(e)                     BF_ICOLL_DEBUG_IRQ(BV_ICOLL_DEBUG_IRQ__##e)
+#define BFM_ICOLL_DEBUG_IRQ_V(v)                    BM_ICOLL_DEBUG_IRQ
+#define BP_ICOLL_DEBUG_VECTOR_FSM                   0
+#define BM_ICOLL_DEBUG_VECTOR_FSM                   0x3ff
+#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_IDLE         0x0
+#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE1  0x1
+#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE2  0x2
+#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_PENDING      0x4
+#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE3  0x8
+#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE4  0x10
+#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING1 0x20
+#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING2 0x40
+#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING3 0x80
+#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE5  0x100
+#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE6  0x200
+#define BF_ICOLL_DEBUG_VECTOR_FSM(v)                (((v) & 0x3ff) << 0)
+#define BFM_ICOLL_DEBUG_VECTOR_FSM(v)               BM_ICOLL_DEBUG_VECTOR_FSM
+#define BF_ICOLL_DEBUG_VECTOR_FSM_V(e)              BF_ICOLL_DEBUG_VECTOR_FSM(BV_ICOLL_DEBUG_VECTOR_FSM__##e)
+#define BFM_ICOLL_DEBUG_VECTOR_FSM_V(v)             BM_ICOLL_DEBUG_VECTOR_FSM
+
+#define HW_ICOLL_DBGFLAG            HW(ICOLL_DBGFLAG)
+#define HWA_ICOLL_DBGFLAG           (0x80000000 + 0x1a0)
+#define HWT_ICOLL_DBGFLAG           HWIO_32_RW
+#define HWN_ICOLL_DBGFLAG           ICOLL_DBGFLAG
+#define HWI_ICOLL_DBGFLAG           
+#define HW_ICOLL_DBGFLAG_SET        HW(ICOLL_DBGFLAG_SET)
+#define HWA_ICOLL_DBGFLAG_SET       (HWA_ICOLL_DBGFLAG + 0x4)
+#define HWT_ICOLL_DBGFLAG_SET       HWIO_32_WO
+#define HWN_ICOLL_DBGFLAG_SET       ICOLL_DBGFLAG
+#define HWI_ICOLL_DBGFLAG_SET       
+#define HW_ICOLL_DBGFLAG_CLR        HW(ICOLL_DBGFLAG_CLR)
+#define HWA_ICOLL_DBGFLAG_CLR       (HWA_ICOLL_DBGFLAG + 0x8)
+#define HWT_ICOLL_DBGFLAG_CLR       HWIO_32_WO
+#define HWN_ICOLL_DBGFLAG_CLR       ICOLL_DBGFLAG
+#define HWI_ICOLL_DBGFLAG_CLR       
+#define HW_ICOLL_DBGFLAG_TOG        HW(ICOLL_DBGFLAG_TOG)
+#define HWA_ICOLL_DBGFLAG_TOG       (HWA_ICOLL_DBGFLAG + 0xc)
+#define HWT_ICOLL_DBGFLAG_TOG       HWIO_32_WO
+#define HWN_ICOLL_DBGFLAG_TOG       ICOLL_DBGFLAG
+#define HWI_ICOLL_DBGFLAG_TOG       
+#define BP_ICOLL_DBGFLAG_FLAG       0
+#define BM_ICOLL_DBGFLAG_FLAG       0xffff
+#define BF_ICOLL_DBGFLAG_FLAG(v)    (((v) & 0xffff) << 0)
+#define BFM_ICOLL_DBGFLAG_FLAG(v)   BM_ICOLL_DBGFLAG_FLAG
+#define BF_ICOLL_DBGFLAG_FLAG_V(e)  BF_ICOLL_DBGFLAG_FLAG(BV_ICOLL_DBGFLAG_FLAG__##e)
+#define BFM_ICOLL_DBGFLAG_FLAG_V(v) BM_ICOLL_DBGFLAG_FLAG
+
+#define HW_ICOLL_DBGREQUESTn(_n1)       HW(ICOLL_DBGREQUESTn(_n1))
+#define HWA_ICOLL_DBGREQUESTn(_n1)      (0x80000000 + 0x1b0 + (_n1) * 0x10)
+#define HWT_ICOLL_DBGREQUESTn(_n1)      HWIO_32_RW
+#define HWN_ICOLL_DBGREQUESTn(_n1)      ICOLL_DBGREQUESTn
+#define HWI_ICOLL_DBGREQUESTn(_n1)      (_n1)
+#define BP_ICOLL_DBGREQUESTn_BITS       0
+#define BM_ICOLL_DBGREQUESTn_BITS       0xffffffff
+#define BF_ICOLL_DBGREQUESTn_BITS(v)    (((v) & 0xffffffff) << 0)
+#define BFM_ICOLL_DBGREQUESTn_BITS(v)   BM_ICOLL_DBGREQUESTn_BITS
+#define BF_ICOLL_DBGREQUESTn_BITS_V(e)  BF_ICOLL_DBGREQUESTn_BITS(BV_ICOLL_DBGREQUESTn_BITS__##e)
+#define BFM_ICOLL_DBGREQUESTn_BITS_V(v) BM_ICOLL_DBGREQUESTn_BITS
+
+#define HW_ICOLL_RAWn(_n1)              HW(ICOLL_RAWn(_n1))
+#define HWA_ICOLL_RAWn(_n1)             (0x80000000 + 0x40 + (_n1) * 0x10)
+#define HWT_ICOLL_RAWn(_n1)             HWIO_32_RW
+#define HWN_ICOLL_RAWn(_n1)             ICOLL_RAWn
+#define HWI_ICOLL_RAWn(_n1)             (_n1)
+#define BP_ICOLL_RAWn_RAW_IRQS          0
+#define BM_ICOLL_RAWn_RAW_IRQS          0xffffffff
+#define BF_ICOLL_RAWn_RAW_IRQS(v)       (((v) & 0xffffffff) << 0)
+#define BFM_ICOLL_RAWn_RAW_IRQS(v)      BM_ICOLL_RAWn_RAW_IRQS
+#define BF_ICOLL_RAWn_RAW_IRQS_V(e)     BF_ICOLL_RAWn_RAW_IRQS(BV_ICOLL_RAWn_RAW_IRQS__##e)
+#define BFM_ICOLL_RAWn_RAW_IRQS_V(v)    BM_ICOLL_RAWn_RAW_IRQS
+
+#define HW_ICOLL_DBGREADn(_n1)          HW(ICOLL_DBGREADn(_n1))
+#define HWA_ICOLL_DBGREADn(_n1)         (0x80000000 + 0x180 + (_n1) * 0x10)
+#define HWT_ICOLL_DBGREADn(_n1)         HWIO_32_RW
+#define HWN_ICOLL_DBGREADn(_n1)         ICOLL_DBGREADn
+#define HWI_ICOLL_DBGREADn(_n1)         (_n1)
+#define BP_ICOLL_DBGREADn_VALUE         0
+#define BM_ICOLL_DBGREADn_VALUE         0xffffffff
+#define BF_ICOLL_DBGREADn_VALUE(v)      (((v) & 0xffffffff) << 0)
+#define BFM_ICOLL_DBGREADn_VALUE(v)     BM_ICOLL_DBGREADn_VALUE
+#define BF_ICOLL_DBGREADn_VALUE_V(e)    BF_ICOLL_DBGREADn_VALUE(BV_ICOLL_DBGREADn_VALUE__##e)
+#define BFM_ICOLL_DBGREADn_VALUE_V(v)   BM_ICOLL_DBGREADn_VALUE
+
+#define HW_ICOLL_PRIORITYn(_n1)                         HW(ICOLL_PRIORITYn(_n1))
+#define HWA_ICOLL_PRIORITYn(_n1)                        (0x80000000 + 0x60 + (_n1) * 0x10)
+#define HWT_ICOLL_PRIORITYn(_n1)                        HWIO_32_RW
+#define HWN_ICOLL_PRIORITYn(_n1)                        ICOLL_PRIORITYn
+#define HWI_ICOLL_PRIORITYn(_n1)                        (_n1)
+#define HW_ICOLL_PRIORITYn_SET(_n1)                     HW(ICOLL_PRIORITYn_SET(_n1))
+#define HWA_ICOLL_PRIORITYn_SET(_n1)                    (HWA_ICOLL_PRIORITYn(_n1) + 0x4)
+#define HWT_ICOLL_PRIORITYn_SET(_n1)                    HWIO_32_WO
+#define HWN_ICOLL_PRIORITYn_SET(_n1)                    ICOLL_PRIORITYn
+#define HWI_ICOLL_PRIORITYn_SET(_n1)                    (_n1)
+#define HW_ICOLL_PRIORITYn_CLR(_n1)                     HW(ICOLL_PRIORITYn_CLR(_n1))
+#define HWA_ICOLL_PRIORITYn_CLR(_n1)                    (HWA_ICOLL_PRIORITYn(_n1) + 0x8)
+#define HWT_ICOLL_PRIORITYn_CLR(_n1)                    HWIO_32_WO
+#define HWN_ICOLL_PRIORITYn_CLR(_n1)                    ICOLL_PRIORITYn
+#define HWI_ICOLL_PRIORITYn_CLR(_n1)                    (_n1)
+#define HW_ICOLL_PRIORITYn_TOG(_n1)                     HW(ICOLL_PRIORITYn_TOG(_n1))
+#define HWA_ICOLL_PRIORITYn_TOG(_n1)                    (HWA_ICOLL_PRIORITYn(_n1) + 0xc)
+#define HWT_ICOLL_PRIORITYn_TOG(_n1)                    HWIO_32_WO
+#define HWN_ICOLL_PRIORITYn_TOG(_n1)                    ICOLL_PRIORITYn
+#define HWI_ICOLL_PRIORITYn_TOG(_n1)                    (_n1)
+#define BP_ICOLL_PRIORITYn_SOFTIRQ3                     27
+#define BM_ICOLL_PRIORITYn_SOFTIRQ3                     0x8000000
+#define BV_ICOLL_PRIORITYn_SOFTIRQ3__NO_INTERRUPT       0x0
+#define BV_ICOLL_PRIORITYn_SOFTIRQ3__FORCE_INTERRUPT    0x1
+#define BF_ICOLL_PRIORITYn_SOFTIRQ3(v)                  (((v) & 0x1) << 27)
+#define BFM_ICOLL_PRIORITYn_SOFTIRQ3(v)                 BM_ICOLL_PRIORITYn_SOFTIRQ3
+#define BF_ICOLL_PRIORITYn_SOFTIRQ3_V(e)                BF_ICOLL_PRIORITYn_SOFTIRQ3(BV_ICOLL_PRIORITYn_SOFTIRQ3__##e)
+#define BFM_ICOLL_PRIORITYn_SOFTIRQ3_V(v)               BM_ICOLL_PRIORITYn_SOFTIRQ3
+#define BP_ICOLL_PRIORITYn_ENABLE3                      26
+#define BM_ICOLL_PRIORITYn_ENABLE3                      0x4000000
+#define BV_ICOLL_PRIORITYn_ENABLE3__DISABLE             0x0
+#define BV_ICOLL_PRIORITYn_ENABLE3__ENABLE              0x1
+#define BF_ICOLL_PRIORITYn_ENABLE3(v)                   (((v) & 0x1) << 26)
+#define BFM_ICOLL_PRIORITYn_ENABLE3(v)                  BM_ICOLL_PRIORITYn_ENABLE3
+#define BF_ICOLL_PRIORITYn_ENABLE3_V(e)                 BF_ICOLL_PRIORITYn_ENABLE3(BV_ICOLL_PRIORITYn_ENABLE3__##e)
+#define BFM_ICOLL_PRIORITYn_ENABLE3_V(v)                BM_ICOLL_PRIORITYn_ENABLE3
+#define BP_ICOLL_PRIORITYn_PRIORITY3                    24
+#define BM_ICOLL_PRIORITYn_PRIORITY3                    0x3000000
+#define BV_ICOLL_PRIORITYn_PRIORITY3__LEVEL0            0x0
+#define BV_ICOLL_PRIORITYn_PRIORITY3__LEVEL1            0x1
+#define BV_ICOLL_PRIORITYn_PRIORITY3__LEVEL2            0x2
+#define BV_ICOLL_PRIORITYn_PRIORITY3__LEVEL3            0x3
+#define BF_ICOLL_PRIORITYn_PRIORITY3(v)                 (((v) & 0x3) << 24)
+#define BFM_ICOLL_PRIORITYn_PRIORITY3(v)                BM_ICOLL_PRIORITYn_PRIORITY3
+#define BF_ICOLL_PRIORITYn_PRIORITY3_V(e)               BF_ICOLL_PRIORITYn_PRIORITY3(BV_ICOLL_PRIORITYn_PRIORITY3__##e)
+#define BFM_ICOLL_PRIORITYn_PRIORITY3_V(v)              BM_ICOLL_PRIORITYn_PRIORITY3
+#define BP_ICOLL_PRIORITYn_SOFTIRQ2                     19
+#define BM_ICOLL_PRIORITYn_SOFTIRQ2                     0x80000
+#define BV_ICOLL_PRIORITYn_SOFTIRQ2__NO_INTERRUPT       0x0
+#define BV_ICOLL_PRIORITYn_SOFTIRQ2__FORCE_INTERRUPT    0x1
+#define BF_ICOLL_PRIORITYn_SOFTIRQ2(v)                  (((v) & 0x1) << 19)
+#define BFM_ICOLL_PRIORITYn_SOFTIRQ2(v)                 BM_ICOLL_PRIORITYn_SOFTIRQ2
+#define BF_ICOLL_PRIORITYn_SOFTIRQ2_V(e)                BF_ICOLL_PRIORITYn_SOFTIRQ2(BV_ICOLL_PRIORITYn_SOFTIRQ2__##e)
+#define BFM_ICOLL_PRIORITYn_SOFTIRQ2_V(v)               BM_ICOLL_PRIORITYn_SOFTIRQ2
+#define BP_ICOLL_PRIORITYn_ENABLE2                      18
+#define BM_ICOLL_PRIORITYn_ENABLE2                      0x40000
+#define BV_ICOLL_PRIORITYn_ENABLE2__DISABLE             0x0
+#define BV_ICOLL_PRIORITYn_ENABLE2__ENABLE              0x1
+#define BF_ICOLL_PRIORITYn_ENABLE2(v)                   (((v) & 0x1) << 18)
+#define BFM_ICOLL_PRIORITYn_ENABLE2(v)                  BM_ICOLL_PRIORITYn_ENABLE2
+#define BF_ICOLL_PRIORITYn_ENABLE2_V(e)                 BF_ICOLL_PRIORITYn_ENABLE2(BV_ICOLL_PRIORITYn_ENABLE2__##e)
+#define BFM_ICOLL_PRIORITYn_ENABLE2_V(v)                BM_ICOLL_PRIORITYn_ENABLE2
+#define BP_ICOLL_PRIORITYn_PRIORITY2                    16
+#define BM_ICOLL_PRIORITYn_PRIORITY2                    0x30000
+#define BV_ICOLL_PRIORITYn_PRIORITY2__LEVEL0            0x0
+#define BV_ICOLL_PRIORITYn_PRIORITY2__LEVEL1            0x1
+#define BV_ICOLL_PRIORITYn_PRIORITY2__LEVEL2            0x2
+#define BV_ICOLL_PRIORITYn_PRIORITY2__LEVEL3            0x3
+#define BF_ICOLL_PRIORITYn_PRIORITY2(v)                 (((v) & 0x3) << 16)
+#define BFM_ICOLL_PRIORITYn_PRIORITY2(v)                BM_ICOLL_PRIORITYn_PRIORITY2
+#define BF_ICOLL_PRIORITYn_PRIORITY2_V(e)               BF_ICOLL_PRIORITYn_PRIORITY2(BV_ICOLL_PRIORITYn_PRIORITY2__##e)
+#define BFM_ICOLL_PRIORITYn_PRIORITY2_V(v)              BM_ICOLL_PRIORITYn_PRIORITY2
+#define BP_ICOLL_PRIORITYn_SOFTIRQ1                     11
+#define BM_ICOLL_PRIORITYn_SOFTIRQ1                     0x800
+#define BV_ICOLL_PRIORITYn_SOFTIRQ1__NO_INTERRUPT       0x0
+#define BV_ICOLL_PRIORITYn_SOFTIRQ1__FORCE_INTERRUPT    0x1
+#define BF_ICOLL_PRIORITYn_SOFTIRQ1(v)                  (((v) & 0x1) << 11)
+#define BFM_ICOLL_PRIORITYn_SOFTIRQ1(v)                 BM_ICOLL_PRIORITYn_SOFTIRQ1
+#define BF_ICOLL_PRIORITYn_SOFTIRQ1_V(e)                BF_ICOLL_PRIORITYn_SOFTIRQ1(BV_ICOLL_PRIORITYn_SOFTIRQ1__##e)
+#define BFM_ICOLL_PRIORITYn_SOFTIRQ1_V(v)               BM_ICOLL_PRIORITYn_SOFTIRQ1
+#define BP_ICOLL_PRIORITYn_ENABLE1                      10
+#define BM_ICOLL_PRIORITYn_ENABLE1                      0x400
+#define BV_ICOLL_PRIORITYn_ENABLE1__DISABLE             0x0
+#define BV_ICOLL_PRIORITYn_ENABLE1__ENABLE              0x1
+#define BF_ICOLL_PRIORITYn_ENABLE1(v)                   (((v) & 0x1) << 10)
+#define BFM_ICOLL_PRIORITYn_ENABLE1(v)                  BM_ICOLL_PRIORITYn_ENABLE1
+#define BF_ICOLL_PRIORITYn_ENABLE1_V(e)                 BF_ICOLL_PRIORITYn_ENABLE1(BV_ICOLL_PRIORITYn_ENABLE1__##e)
+#define BFM_ICOLL_PRIORITYn_ENABLE1_V(v)                BM_ICOLL_PRIORITYn_ENABLE1
+#define BP_ICOLL_PRIORITYn_PRIORITY1                    8
+#define BM_ICOLL_PRIORITYn_PRIORITY1                    0x300
+#define BV_ICOLL_PRIORITYn_PRIORITY1__LEVEL0            0x0
+#define BV_ICOLL_PRIORITYn_PRIORITY1__LEVEL1            0x1
+#define BV_ICOLL_PRIORITYn_PRIORITY1__LEVEL2            0x2
+#define BV_ICOLL_PRIORITYn_PRIORITY1__LEVEL3            0x3
+#define BF_ICOLL_PRIORITYn_PRIORITY1(v)                 (((v) & 0x3) << 8)
+#define BFM_ICOLL_PRIORITYn_PRIORITY1(v)                BM_ICOLL_PRIORITYn_PRIORITY1
+#define BF_ICOLL_PRIORITYn_PRIORITY1_V(e)               BF_ICOLL_PRIORITYn_PRIORITY1(BV_ICOLL_PRIORITYn_PRIORITY1__##e)
+#define BFM_ICOLL_PRIORITYn_PRIORITY1_V(v)              BM_ICOLL_PRIORITYn_PRIORITY1
+#define BP_ICOLL_PRIORITYn_SOFTIRQ0                     3
+#define BM_ICOLL_PRIORITYn_SOFTIRQ0                     0x8
+#define BV_ICOLL_PRIORITYn_SOFTIRQ0__NO_INTERRUPT       0x0
+#define BV_ICOLL_PRIORITYn_SOFTIRQ0__FORCE_INTERRUPT    0x1
+#define BF_ICOLL_PRIORITYn_SOFTIRQ0(v)                  (((v) & 0x1) << 3)
+#define BFM_ICOLL_PRIORITYn_SOFTIRQ0(v)                 BM_ICOLL_PRIORITYn_SOFTIRQ0
+#define BF_ICOLL_PRIORITYn_SOFTIRQ0_V(e)                BF_ICOLL_PRIORITYn_SOFTIRQ0(BV_ICOLL_PRIORITYn_SOFTIRQ0__##e)
+#define BFM_ICOLL_PRIORITYn_SOFTIRQ0_V(v)               BM_ICOLL_PRIORITYn_SOFTIRQ0
+#define BP_ICOLL_PRIORITYn_ENABLE0                      2
+#define BM_ICOLL_PRIORITYn_ENABLE0                      0x4
+#define BV_ICOLL_PRIORITYn_ENABLE0__DISABLE             0x0
+#define BV_ICOLL_PRIORITYn_ENABLE0__ENABLE              0x1
+#define BF_ICOLL_PRIORITYn_ENABLE0(v)                   (((v) & 0x1) << 2)
+#define BFM_ICOLL_PRIORITYn_ENABLE0(v)                  BM_ICOLL_PRIORITYn_ENABLE0
+#define BF_ICOLL_PRIORITYn_ENABLE0_V(e)                 BF_ICOLL_PRIORITYn_ENABLE0(BV_ICOLL_PRIORITYn_ENABLE0__##e)
+#define BFM_ICOLL_PRIORITYn_ENABLE0_V(v)                BM_ICOLL_PRIORITYn_ENABLE0
+#define BP_ICOLL_PRIORITYn_PRIORITY0                    0
+#define BM_ICOLL_PRIORITYn_PRIORITY0                    0x3
+#define BV_ICOLL_PRIORITYn_PRIORITY0__LEVEL0            0x0
+#define BV_ICOLL_PRIORITYn_PRIORITY0__LEVEL1            0x1
+#define BV_ICOLL_PRIORITYn_PRIORITY0__LEVEL2            0x2
+#define BV_ICOLL_PRIORITYn_PRIORITY0__LEVEL3            0x3
+#define BF_ICOLL_PRIORITYn_PRIORITY0(v)                 (((v) & 0x3) << 0)
+#define BFM_ICOLL_PRIORITYn_PRIORITY0(v)                BM_ICOLL_PRIORITYn_PRIORITY0
+#define BF_ICOLL_PRIORITYn_PRIORITY0_V(e)               BF_ICOLL_PRIORITYn_PRIORITY0(BV_ICOLL_PRIORITYn_PRIORITY0__##e)
+#define BFM_ICOLL_PRIORITYn_PRIORITY0_V(v)              BM_ICOLL_PRIORITYn_PRIORITY0
+
+#endif /* __HEADERGEN_STMP3600_ICOLL_H__*/
diff --git a/firmware/target/arm/imx233/regs/stmp3600/ir.h b/firmware/target/arm/imx233/regs/stmp3600/ir.h
new file mode 100644
index 0000000000..644e78e5f1
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3600/ir.h
@@ -0,0 +1,751 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * stmp3600 version: 2.4.0
+ * stmp3600 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_STMP3600_IR_H__
+#define __HEADERGEN_STMP3600_IR_H__
+
+#define HW_IR_CTRL                      HW(IR_CTRL)
+#define HWA_IR_CTRL                     (0x80078000 + 0x0)
+#define HWT_IR_CTRL                     HWIO_32_RW
+#define HWN_IR_CTRL                     IR_CTRL
+#define HWI_IR_CTRL                     
+#define HW_IR_CTRL_SET                  HW(IR_CTRL_SET)
+#define HWA_IR_CTRL_SET                 (HWA_IR_CTRL + 0x4)
+#define HWT_IR_CTRL_SET                 HWIO_32_WO
+#define HWN_IR_CTRL_SET                 IR_CTRL
+#define HWI_IR_CTRL_SET                 
+#define HW_IR_CTRL_CLR                  HW(IR_CTRL_CLR)
+#define HWA_IR_CTRL_CLR                 (HWA_IR_CTRL + 0x8)
+#define HWT_IR_CTRL_CLR                 HWIO_32_WO
+#define HWN_IR_CTRL_CLR                 IR_CTRL
+#define HWI_IR_CTRL_CLR                 
+#define HW_IR_CTRL_TOG                  HW(IR_CTRL_TOG)
+#define HWA_IR_CTRL_TOG                 (HWA_IR_CTRL + 0xc)
+#define HWT_IR_CTRL_TOG                 HWIO_32_WO
+#define HWN_IR_CTRL_TOG                 IR_CTRL
+#define HWI_IR_CTRL_TOG                 
+#define BP_IR_CTRL_SFTRST               31
+#define BM_IR_CTRL_SFTRST               0x80000000
+#define BV_IR_CTRL_SFTRST__RUN          0x0
+#define BV_IR_CTRL_SFTRST__RESET        0x1
+#define BF_IR_CTRL_SFTRST(v)            (((v) & 0x1) << 31)
+#define BFM_IR_CTRL_SFTRST(v)           BM_IR_CTRL_SFTRST
+#define BF_IR_CTRL_SFTRST_V(e)          BF_IR_CTRL_SFTRST(BV_IR_CTRL_SFTRST__##e)
+#define BFM_IR_CTRL_SFTRST_V(v)         BM_IR_CTRL_SFTRST
+#define BP_IR_CTRL_CLKGATE              30
+#define BM_IR_CTRL_CLKGATE              0x40000000
+#define BF_IR_CTRL_CLKGATE(v)           (((v) & 0x1) << 30)
+#define BFM_IR_CTRL_CLKGATE(v)          BM_IR_CTRL_CLKGATE
+#define BF_IR_CTRL_CLKGATE_V(e)         BF_IR_CTRL_CLKGATE(BV_IR_CTRL_CLKGATE__##e)
+#define BFM_IR_CTRL_CLKGATE_V(v)        BM_IR_CTRL_CLKGATE
+#define BP_IR_CTRL_MTA                  24
+#define BM_IR_CTRL_MTA                  0x7000000
+#define BV_IR_CTRL_MTA__MTA_10MS        0x0
+#define BV_IR_CTRL_MTA__MTA_5MS         0x1
+#define BV_IR_CTRL_MTA__MTA_1MS         0x2
+#define BV_IR_CTRL_MTA__MTA_500US       0x3
+#define BV_IR_CTRL_MTA__MTA_100US       0x4
+#define BV_IR_CTRL_MTA__MTA_50US        0x5
+#define BV_IR_CTRL_MTA__MTA_10US        0x6
+#define BV_IR_CTRL_MTA__MTA_0           0x7
+#define BF_IR_CTRL_MTA(v)               (((v) & 0x7) << 24)
+#define BFM_IR_CTRL_MTA(v)              BM_IR_CTRL_MTA
+#define BF_IR_CTRL_MTA_V(e)             BF_IR_CTRL_MTA(BV_IR_CTRL_MTA__##e)
+#define BFM_IR_CTRL_MTA_V(v)            BM_IR_CTRL_MTA
+#define BP_IR_CTRL_MODE                 22
+#define BM_IR_CTRL_MODE                 0xc00000
+#define BV_IR_CTRL_MODE__SIR            0x0
+#define BV_IR_CTRL_MODE__MIR            0x1
+#define BV_IR_CTRL_MODE__FIR            0x2
+#define BV_IR_CTRL_MODE__VFIR           0x3
+#define BF_IR_CTRL_MODE(v)              (((v) & 0x3) << 22)
+#define BFM_IR_CTRL_MODE(v)             BM_IR_CTRL_MODE
+#define BF_IR_CTRL_MODE_V(e)            BF_IR_CTRL_MODE(BV_IR_CTRL_MODE__##e)
+#define BFM_IR_CTRL_MODE_V(v)           BM_IR_CTRL_MODE
+#define BP_IR_CTRL_SPEED                19
+#define BM_IR_CTRL_SPEED                0x380000
+#define BV_IR_CTRL_SPEED__SPD000        0x0
+#define BV_IR_CTRL_SPEED__SPD001        0x1
+#define BV_IR_CTRL_SPEED__SPD010        0x2
+#define BV_IR_CTRL_SPEED__SPD011        0x3
+#define BV_IR_CTRL_SPEED__SPD100        0x4
+#define BV_IR_CTRL_SPEED__SPD101        0x5
+#define BF_IR_CTRL_SPEED(v)             (((v) & 0x7) << 19)
+#define BFM_IR_CTRL_SPEED(v)            BM_IR_CTRL_SPEED
+#define BF_IR_CTRL_SPEED_V(e)           BF_IR_CTRL_SPEED(BV_IR_CTRL_SPEED__##e)
+#define BFM_IR_CTRL_SPEED_V(v)          BM_IR_CTRL_SPEED
+#define BP_IR_CTRL_TC_TIME_DIV          8
+#define BM_IR_CTRL_TC_TIME_DIV          0x3f00
+#define BF_IR_CTRL_TC_TIME_DIV(v)       (((v) & 0x3f) << 8)
+#define BFM_IR_CTRL_TC_TIME_DIV(v)      BM_IR_CTRL_TC_TIME_DIV
+#define BF_IR_CTRL_TC_TIME_DIV_V(e)     BF_IR_CTRL_TC_TIME_DIV(BV_IR_CTRL_TC_TIME_DIV__##e)
+#define BFM_IR_CTRL_TC_TIME_DIV_V(v)    BM_IR_CTRL_TC_TIME_DIV
+#define BP_IR_CTRL_TC_TYPE              7
+#define BM_IR_CTRL_TC_TYPE              0x80
+#define BF_IR_CTRL_TC_TYPE(v)           (((v) & 0x1) << 7)
+#define BFM_IR_CTRL_TC_TYPE(v)          BM_IR_CTRL_TC_TYPE
+#define BF_IR_CTRL_TC_TYPE_V(e)         BF_IR_CTRL_TC_TYPE(BV_IR_CTRL_TC_TYPE__##e)
+#define BFM_IR_CTRL_TC_TYPE_V(v)        BM_IR_CTRL_TC_TYPE
+#define BP_IR_CTRL_SIR_GAP              4
+#define BM_IR_CTRL_SIR_GAP              0x70
+#define BV_IR_CTRL_SIR_GAP__GAP_10K     0x0
+#define BV_IR_CTRL_SIR_GAP__GAP_5K      0x1
+#define BV_IR_CTRL_SIR_GAP__GAP_1K      0x2
+#define BV_IR_CTRL_SIR_GAP__GAP_500     0x3
+#define BV_IR_CTRL_SIR_GAP__GAP_100     0x4
+#define BV_IR_CTRL_SIR_GAP__GAP_50      0x5
+#define BV_IR_CTRL_SIR_GAP__GAP_10      0x6
+#define BV_IR_CTRL_SIR_GAP__GAP_0       0x7
+#define BF_IR_CTRL_SIR_GAP(v)           (((v) & 0x7) << 4)
+#define BFM_IR_CTRL_SIR_GAP(v)          BM_IR_CTRL_SIR_GAP
+#define BF_IR_CTRL_SIR_GAP_V(e)         BF_IR_CTRL_SIR_GAP(BV_IR_CTRL_SIR_GAP__##e)
+#define BFM_IR_CTRL_SIR_GAP_V(v)        BM_IR_CTRL_SIR_GAP
+#define BP_IR_CTRL_SIPEN                3
+#define BM_IR_CTRL_SIPEN                0x8
+#define BF_IR_CTRL_SIPEN(v)             (((v) & 0x1) << 3)
+#define BFM_IR_CTRL_SIPEN(v)            BM_IR_CTRL_SIPEN
+#define BF_IR_CTRL_SIPEN_V(e)           BF_IR_CTRL_SIPEN(BV_IR_CTRL_SIPEN__##e)
+#define BFM_IR_CTRL_SIPEN_V(v)          BM_IR_CTRL_SIPEN
+#define BP_IR_CTRL_TCEN                 2
+#define BM_IR_CTRL_TCEN                 0x4
+#define BF_IR_CTRL_TCEN(v)              (((v) & 0x1) << 2)
+#define BFM_IR_CTRL_TCEN(v)             BM_IR_CTRL_TCEN
+#define BF_IR_CTRL_TCEN_V(e)            BF_IR_CTRL_TCEN(BV_IR_CTRL_TCEN__##e)
+#define BFM_IR_CTRL_TCEN_V(v)           BM_IR_CTRL_TCEN
+#define BP_IR_CTRL_TXEN                 1
+#define BM_IR_CTRL_TXEN                 0x2
+#define BF_IR_CTRL_TXEN(v)              (((v) & 0x1) << 1)
+#define BFM_IR_CTRL_TXEN(v)             BM_IR_CTRL_TXEN
+#define BF_IR_CTRL_TXEN_V(e)            BF_IR_CTRL_TXEN(BV_IR_CTRL_TXEN__##e)
+#define BFM_IR_CTRL_TXEN_V(v)           BM_IR_CTRL_TXEN
+#define BP_IR_CTRL_RXEN                 0
+#define BM_IR_CTRL_RXEN                 0x1
+#define BF_IR_CTRL_RXEN(v)              (((v) & 0x1) << 0)
+#define BFM_IR_CTRL_RXEN(v)             BM_IR_CTRL_RXEN
+#define BF_IR_CTRL_RXEN_V(e)            BF_IR_CTRL_RXEN(BV_IR_CTRL_RXEN__##e)
+#define BFM_IR_CTRL_RXEN_V(v)           BM_IR_CTRL_RXEN
+
+#define HW_IR_TXDMA                     HW(IR_TXDMA)
+#define HWA_IR_TXDMA                    (0x80078000 + 0x10)
+#define HWT_IR_TXDMA                    HWIO_32_RW
+#define HWN_IR_TXDMA                    IR_TXDMA
+#define HWI_IR_TXDMA                    
+#define HW_IR_TXDMA_SET                 HW(IR_TXDMA_SET)
+#define HWA_IR_TXDMA_SET                (HWA_IR_TXDMA + 0x4)
+#define HWT_IR_TXDMA_SET                HWIO_32_WO
+#define HWN_IR_TXDMA_SET                IR_TXDMA
+#define HWI_IR_TXDMA_SET                
+#define HW_IR_TXDMA_CLR                 HW(IR_TXDMA_CLR)
+#define HWA_IR_TXDMA_CLR                (HWA_IR_TXDMA + 0x8)
+#define HWT_IR_TXDMA_CLR                HWIO_32_WO
+#define HWN_IR_TXDMA_CLR                IR_TXDMA
+#define HWI_IR_TXDMA_CLR                
+#define HW_IR_TXDMA_TOG                 HW(IR_TXDMA_TOG)
+#define HWA_IR_TXDMA_TOG                (HWA_IR_TXDMA + 0xc)
+#define HWT_IR_TXDMA_TOG                HWIO_32_WO
+#define HWN_IR_TXDMA_TOG                IR_TXDMA
+#define HWI_IR_TXDMA_TOG                
+#define BP_IR_TXDMA_RUN                 31
+#define BM_IR_TXDMA_RUN                 0x80000000
+#define BF_IR_TXDMA_RUN(v)              (((v) & 0x1) << 31)
+#define BFM_IR_TXDMA_RUN(v)             BM_IR_TXDMA_RUN
+#define BF_IR_TXDMA_RUN_V(e)            BF_IR_TXDMA_RUN(BV_IR_TXDMA_RUN__##e)
+#define BFM_IR_TXDMA_RUN_V(v)           BM_IR_TXDMA_RUN
+#define BP_IR_TXDMA_EMPTY               29
+#define BM_IR_TXDMA_EMPTY               0x20000000
+#define BF_IR_TXDMA_EMPTY(v)            (((v) & 0x1) << 29)
+#define BFM_IR_TXDMA_EMPTY(v)           BM_IR_TXDMA_EMPTY
+#define BF_IR_TXDMA_EMPTY_V(e)          BF_IR_TXDMA_EMPTY(BV_IR_TXDMA_EMPTY__##e)
+#define BFM_IR_TXDMA_EMPTY_V(v)         BM_IR_TXDMA_EMPTY
+#define BP_IR_TXDMA_INT                 28
+#define BM_IR_TXDMA_INT                 0x10000000
+#define BF_IR_TXDMA_INT(v)              (((v) & 0x1) << 28)
+#define BFM_IR_TXDMA_INT(v)             BM_IR_TXDMA_INT
+#define BF_IR_TXDMA_INT_V(e)            BF_IR_TXDMA_INT(BV_IR_TXDMA_INT__##e)
+#define BFM_IR_TXDMA_INT_V(v)           BM_IR_TXDMA_INT
+#define BP_IR_TXDMA_CHANGE              27
+#define BM_IR_TXDMA_CHANGE              0x8000000
+#define BF_IR_TXDMA_CHANGE(v)           (((v) & 0x1) << 27)
+#define BFM_IR_TXDMA_CHANGE(v)          BM_IR_TXDMA_CHANGE
+#define BF_IR_TXDMA_CHANGE_V(e)         BF_IR_TXDMA_CHANGE(BV_IR_TXDMA_CHANGE__##e)
+#define BFM_IR_TXDMA_CHANGE_V(v)        BM_IR_TXDMA_CHANGE
+#define BP_IR_TXDMA_NEW_MTA             24
+#define BM_IR_TXDMA_NEW_MTA             0x7000000
+#define BF_IR_TXDMA_NEW_MTA(v)          (((v) & 0x7) << 24)
+#define BFM_IR_TXDMA_NEW_MTA(v)         BM_IR_TXDMA_NEW_MTA
+#define BF_IR_TXDMA_NEW_MTA_V(e)        BF_IR_TXDMA_NEW_MTA(BV_IR_TXDMA_NEW_MTA__##e)
+#define BFM_IR_TXDMA_NEW_MTA_V(v)       BM_IR_TXDMA_NEW_MTA
+#define BP_IR_TXDMA_NEW_MODE            22
+#define BM_IR_TXDMA_NEW_MODE            0xc00000
+#define BF_IR_TXDMA_NEW_MODE(v)         (((v) & 0x3) << 22)
+#define BFM_IR_TXDMA_NEW_MODE(v)        BM_IR_TXDMA_NEW_MODE
+#define BF_IR_TXDMA_NEW_MODE_V(e)       BF_IR_TXDMA_NEW_MODE(BV_IR_TXDMA_NEW_MODE__##e)
+#define BFM_IR_TXDMA_NEW_MODE_V(v)      BM_IR_TXDMA_NEW_MODE
+#define BP_IR_TXDMA_NEW_SPEED           19
+#define BM_IR_TXDMA_NEW_SPEED           0x380000
+#define BF_IR_TXDMA_NEW_SPEED(v)        (((v) & 0x7) << 19)
+#define BFM_IR_TXDMA_NEW_SPEED(v)       BM_IR_TXDMA_NEW_SPEED
+#define BF_IR_TXDMA_NEW_SPEED_V(e)      BF_IR_TXDMA_NEW_SPEED(BV_IR_TXDMA_NEW_SPEED__##e)
+#define BFM_IR_TXDMA_NEW_SPEED_V(v)     BM_IR_TXDMA_NEW_SPEED
+#define BP_IR_TXDMA_BOF_TYPE            18
+#define BM_IR_TXDMA_BOF_TYPE            0x40000
+#define BF_IR_TXDMA_BOF_TYPE(v)         (((v) & 0x1) << 18)
+#define BFM_IR_TXDMA_BOF_TYPE(v)        BM_IR_TXDMA_BOF_TYPE
+#define BF_IR_TXDMA_BOF_TYPE_V(e)       BF_IR_TXDMA_BOF_TYPE(BV_IR_TXDMA_BOF_TYPE__##e)
+#define BFM_IR_TXDMA_BOF_TYPE_V(v)      BM_IR_TXDMA_BOF_TYPE
+#define BP_IR_TXDMA_XBOFS               12
+#define BM_IR_TXDMA_XBOFS               0x3f000
+#define BF_IR_TXDMA_XBOFS(v)            (((v) & 0x3f) << 12)
+#define BFM_IR_TXDMA_XBOFS(v)           BM_IR_TXDMA_XBOFS
+#define BF_IR_TXDMA_XBOFS_V(e)          BF_IR_TXDMA_XBOFS(BV_IR_TXDMA_XBOFS__##e)
+#define BFM_IR_TXDMA_XBOFS_V(v)         BM_IR_TXDMA_XBOFS
+#define BP_IR_TXDMA_XFER_COUNT          0
+#define BM_IR_TXDMA_XFER_COUNT          0xfff
+#define BF_IR_TXDMA_XFER_COUNT(v)       (((v) & 0xfff) << 0)
+#define BFM_IR_TXDMA_XFER_COUNT(v)      BM_IR_TXDMA_XFER_COUNT
+#define BF_IR_TXDMA_XFER_COUNT_V(e)     BF_IR_TXDMA_XFER_COUNT(BV_IR_TXDMA_XFER_COUNT__##e)
+#define BFM_IR_TXDMA_XFER_COUNT_V(v)    BM_IR_TXDMA_XFER_COUNT
+
+#define HW_IR_RXDMA                     HW(IR_RXDMA)
+#define HWA_IR_RXDMA                    (0x80078000 + 0x20)
+#define HWT_IR_RXDMA                    HWIO_32_RW
+#define HWN_IR_RXDMA                    IR_RXDMA
+#define HWI_IR_RXDMA                    
+#define HW_IR_RXDMA_SET                 HW(IR_RXDMA_SET)
+#define HWA_IR_RXDMA_SET                (HWA_IR_RXDMA + 0x4)
+#define HWT_IR_RXDMA_SET                HWIO_32_WO
+#define HWN_IR_RXDMA_SET                IR_RXDMA
+#define HWI_IR_RXDMA_SET                
+#define HW_IR_RXDMA_CLR                 HW(IR_RXDMA_CLR)
+#define HWA_IR_RXDMA_CLR                (HWA_IR_RXDMA + 0x8)
+#define HWT_IR_RXDMA_CLR                HWIO_32_WO
+#define HWN_IR_RXDMA_CLR                IR_RXDMA
+#define HWI_IR_RXDMA_CLR                
+#define HW_IR_RXDMA_TOG                 HW(IR_RXDMA_TOG)
+#define HWA_IR_RXDMA_TOG                (HWA_IR_RXDMA + 0xc)
+#define HWT_IR_RXDMA_TOG                HWIO_32_WO
+#define HWN_IR_RXDMA_TOG                IR_RXDMA
+#define HWI_IR_RXDMA_TOG                
+#define BP_IR_RXDMA_RUN                 31
+#define BM_IR_RXDMA_RUN                 0x80000000
+#define BF_IR_RXDMA_RUN(v)              (((v) & 0x1) << 31)
+#define BFM_IR_RXDMA_RUN(v)             BM_IR_RXDMA_RUN
+#define BF_IR_RXDMA_RUN_V(e)            BF_IR_RXDMA_RUN(BV_IR_RXDMA_RUN__##e)
+#define BFM_IR_RXDMA_RUN_V(v)           BM_IR_RXDMA_RUN
+#define BP_IR_RXDMA_XFER_COUNT          0
+#define BM_IR_RXDMA_XFER_COUNT          0x3ff
+#define BF_IR_RXDMA_XFER_COUNT(v)       (((v) & 0x3ff) << 0)
+#define BFM_IR_RXDMA_XFER_COUNT(v)      BM_IR_RXDMA_XFER_COUNT
+#define BF_IR_RXDMA_XFER_COUNT_V(e)     BF_IR_RXDMA_XFER_COUNT(BV_IR_RXDMA_XFER_COUNT__##e)
+#define BFM_IR_RXDMA_XFER_COUNT_V(v)    BM_IR_RXDMA_XFER_COUNT
+
+#define HW_IR_DBGCTRL                   HW(IR_DBGCTRL)
+#define HWA_IR_DBGCTRL                  (0x80078000 + 0x30)
+#define HWT_IR_DBGCTRL                  HWIO_32_RW
+#define HWN_IR_DBGCTRL                  IR_DBGCTRL
+#define HWI_IR_DBGCTRL                  
+#define HW_IR_DBGCTRL_SET               HW(IR_DBGCTRL_SET)
+#define HWA_IR_DBGCTRL_SET              (HWA_IR_DBGCTRL + 0x4)
+#define HWT_IR_DBGCTRL_SET              HWIO_32_WO
+#define HWN_IR_DBGCTRL_SET              IR_DBGCTRL
+#define HWI_IR_DBGCTRL_SET              
+#define HW_IR_DBGCTRL_CLR               HW(IR_DBGCTRL_CLR)
+#define HWA_IR_DBGCTRL_CLR              (HWA_IR_DBGCTRL + 0x8)
+#define HWT_IR_DBGCTRL_CLR              HWIO_32_WO
+#define HWN_IR_DBGCTRL_CLR              IR_DBGCTRL
+#define HWI_IR_DBGCTRL_CLR              
+#define HW_IR_DBGCTRL_TOG               HW(IR_DBGCTRL_TOG)
+#define HWA_IR_DBGCTRL_TOG              (HWA_IR_DBGCTRL + 0xc)
+#define HWT_IR_DBGCTRL_TOG              HWIO_32_WO
+#define HWN_IR_DBGCTRL_TOG              IR_DBGCTRL
+#define HWI_IR_DBGCTRL_TOG              
+#define BP_IR_DBGCTRL_VFIRSWZ           12
+#define BM_IR_DBGCTRL_VFIRSWZ           0x1000
+#define BV_IR_DBGCTRL_VFIRSWZ__NORMAL   0x0
+#define BV_IR_DBGCTRL_VFIRSWZ__SWAP     0x1
+#define BF_IR_DBGCTRL_VFIRSWZ(v)        (((v) & 0x1) << 12)
+#define BFM_IR_DBGCTRL_VFIRSWZ(v)       BM_IR_DBGCTRL_VFIRSWZ
+#define BF_IR_DBGCTRL_VFIRSWZ_V(e)      BF_IR_DBGCTRL_VFIRSWZ(BV_IR_DBGCTRL_VFIRSWZ__##e)
+#define BFM_IR_DBGCTRL_VFIRSWZ_V(v)     BM_IR_DBGCTRL_VFIRSWZ
+#define BP_IR_DBGCTRL_RXFRMOFF          11
+#define BM_IR_DBGCTRL_RXFRMOFF          0x800
+#define BF_IR_DBGCTRL_RXFRMOFF(v)       (((v) & 0x1) << 11)
+#define BFM_IR_DBGCTRL_RXFRMOFF(v)      BM_IR_DBGCTRL_RXFRMOFF
+#define BF_IR_DBGCTRL_RXFRMOFF_V(e)     BF_IR_DBGCTRL_RXFRMOFF(BV_IR_DBGCTRL_RXFRMOFF__##e)
+#define BFM_IR_DBGCTRL_RXFRMOFF_V(v)    BM_IR_DBGCTRL_RXFRMOFF
+#define BP_IR_DBGCTRL_RXCRCOFF          10
+#define BM_IR_DBGCTRL_RXCRCOFF          0x400
+#define BF_IR_DBGCTRL_RXCRCOFF(v)       (((v) & 0x1) << 10)
+#define BFM_IR_DBGCTRL_RXCRCOFF(v)      BM_IR_DBGCTRL_RXCRCOFF
+#define BF_IR_DBGCTRL_RXCRCOFF_V(e)     BF_IR_DBGCTRL_RXCRCOFF(BV_IR_DBGCTRL_RXCRCOFF__##e)
+#define BFM_IR_DBGCTRL_RXCRCOFF_V(v)    BM_IR_DBGCTRL_RXCRCOFF
+#define BP_IR_DBGCTRL_RXINVERT          9
+#define BM_IR_DBGCTRL_RXINVERT          0x200
+#define BF_IR_DBGCTRL_RXINVERT(v)       (((v) & 0x1) << 9)
+#define BFM_IR_DBGCTRL_RXINVERT(v)      BM_IR_DBGCTRL_RXINVERT
+#define BF_IR_DBGCTRL_RXINVERT_V(e)     BF_IR_DBGCTRL_RXINVERT(BV_IR_DBGCTRL_RXINVERT__##e)
+#define BFM_IR_DBGCTRL_RXINVERT_V(v)    BM_IR_DBGCTRL_RXINVERT
+#define BP_IR_DBGCTRL_TXFRMOFF          8
+#define BM_IR_DBGCTRL_TXFRMOFF          0x100
+#define BF_IR_DBGCTRL_TXFRMOFF(v)       (((v) & 0x1) << 8)
+#define BFM_IR_DBGCTRL_TXFRMOFF(v)      BM_IR_DBGCTRL_TXFRMOFF
+#define BF_IR_DBGCTRL_TXFRMOFF_V(e)     BF_IR_DBGCTRL_TXFRMOFF(BV_IR_DBGCTRL_TXFRMOFF__##e)
+#define BFM_IR_DBGCTRL_TXFRMOFF_V(v)    BM_IR_DBGCTRL_TXFRMOFF
+#define BP_IR_DBGCTRL_TXCRCOFF          7
+#define BM_IR_DBGCTRL_TXCRCOFF          0x80
+#define BF_IR_DBGCTRL_TXCRCOFF(v)       (((v) & 0x1) << 7)
+#define BFM_IR_DBGCTRL_TXCRCOFF(v)      BM_IR_DBGCTRL_TXCRCOFF
+#define BF_IR_DBGCTRL_TXCRCOFF_V(e)     BF_IR_DBGCTRL_TXCRCOFF(BV_IR_DBGCTRL_TXCRCOFF__##e)
+#define BFM_IR_DBGCTRL_TXCRCOFF_V(v)    BM_IR_DBGCTRL_TXCRCOFF
+#define BP_IR_DBGCTRL_TXINVERT          6
+#define BM_IR_DBGCTRL_TXINVERT          0x40
+#define BF_IR_DBGCTRL_TXINVERT(v)       (((v) & 0x1) << 6)
+#define BFM_IR_DBGCTRL_TXINVERT(v)      BM_IR_DBGCTRL_TXINVERT
+#define BF_IR_DBGCTRL_TXINVERT_V(e)     BF_IR_DBGCTRL_TXINVERT(BV_IR_DBGCTRL_TXINVERT__##e)
+#define BFM_IR_DBGCTRL_TXINVERT_V(v)    BM_IR_DBGCTRL_TXINVERT
+#define BP_IR_DBGCTRL_INTLOOPBACK       5
+#define BM_IR_DBGCTRL_INTLOOPBACK       0x20
+#define BF_IR_DBGCTRL_INTLOOPBACK(v)    (((v) & 0x1) << 5)
+#define BFM_IR_DBGCTRL_INTLOOPBACK(v)   BM_IR_DBGCTRL_INTLOOPBACK
+#define BF_IR_DBGCTRL_INTLOOPBACK_V(e)  BF_IR_DBGCTRL_INTLOOPBACK(BV_IR_DBGCTRL_INTLOOPBACK__##e)
+#define BFM_IR_DBGCTRL_INTLOOPBACK_V(v) BM_IR_DBGCTRL_INTLOOPBACK
+#define BP_IR_DBGCTRL_DUPLEX            4
+#define BM_IR_DBGCTRL_DUPLEX            0x10
+#define BF_IR_DBGCTRL_DUPLEX(v)         (((v) & 0x1) << 4)
+#define BFM_IR_DBGCTRL_DUPLEX(v)        BM_IR_DBGCTRL_DUPLEX
+#define BF_IR_DBGCTRL_DUPLEX_V(e)       BF_IR_DBGCTRL_DUPLEX(BV_IR_DBGCTRL_DUPLEX__##e)
+#define BFM_IR_DBGCTRL_DUPLEX_V(v)      BM_IR_DBGCTRL_DUPLEX
+#define BP_IR_DBGCTRL_MIO_RX            3
+#define BM_IR_DBGCTRL_MIO_RX            0x8
+#define BF_IR_DBGCTRL_MIO_RX(v)         (((v) & 0x1) << 3)
+#define BFM_IR_DBGCTRL_MIO_RX(v)        BM_IR_DBGCTRL_MIO_RX
+#define BF_IR_DBGCTRL_MIO_RX_V(e)       BF_IR_DBGCTRL_MIO_RX(BV_IR_DBGCTRL_MIO_RX__##e)
+#define BFM_IR_DBGCTRL_MIO_RX_V(v)      BM_IR_DBGCTRL_MIO_RX
+#define BP_IR_DBGCTRL_MIO_TX            2
+#define BM_IR_DBGCTRL_MIO_TX            0x4
+#define BF_IR_DBGCTRL_MIO_TX(v)         (((v) & 0x1) << 2)
+#define BFM_IR_DBGCTRL_MIO_TX(v)        BM_IR_DBGCTRL_MIO_TX
+#define BF_IR_DBGCTRL_MIO_TX_V(e)       BF_IR_DBGCTRL_MIO_TX(BV_IR_DBGCTRL_MIO_TX__##e)
+#define BFM_IR_DBGCTRL_MIO_TX_V(v)      BM_IR_DBGCTRL_MIO_TX
+#define BP_IR_DBGCTRL_MIO_SCLK          1
+#define BM_IR_DBGCTRL_MIO_SCLK          0x2
+#define BF_IR_DBGCTRL_MIO_SCLK(v)       (((v) & 0x1) << 1)
+#define BFM_IR_DBGCTRL_MIO_SCLK(v)      BM_IR_DBGCTRL_MIO_SCLK
+#define BF_IR_DBGCTRL_MIO_SCLK_V(e)     BF_IR_DBGCTRL_MIO_SCLK(BV_IR_DBGCTRL_MIO_SCLK__##e)
+#define BFM_IR_DBGCTRL_MIO_SCLK_V(v)    BM_IR_DBGCTRL_MIO_SCLK
+#define BP_IR_DBGCTRL_MIO_EN            0
+#define BM_IR_DBGCTRL_MIO_EN            0x1
+#define BF_IR_DBGCTRL_MIO_EN(v)         (((v) & 0x1) << 0)
+#define BFM_IR_DBGCTRL_MIO_EN(v)        BM_IR_DBGCTRL_MIO_EN
+#define BF_IR_DBGCTRL_MIO_EN_V(e)       BF_IR_DBGCTRL_MIO_EN(BV_IR_DBGCTRL_MIO_EN__##e)
+#define BFM_IR_DBGCTRL_MIO_EN_V(v)      BM_IR_DBGCTRL_MIO_EN
+
+#define HW_IR_INTR                          HW(IR_INTR)
+#define HWA_IR_INTR                         (0x80078000 + 0x40)
+#define HWT_IR_INTR                         HWIO_32_RW
+#define HWN_IR_INTR                         IR_INTR
+#define HWI_IR_INTR                         
+#define HW_IR_INTR_SET                      HW(IR_INTR_SET)
+#define HWA_IR_INTR_SET                     (HWA_IR_INTR + 0x4)
+#define HWT_IR_INTR_SET                     HWIO_32_WO
+#define HWN_IR_INTR_SET                     IR_INTR
+#define HWI_IR_INTR_SET                     
+#define HW_IR_INTR_CLR                      HW(IR_INTR_CLR)
+#define HWA_IR_INTR_CLR                     (HWA_IR_INTR + 0x8)
+#define HWT_IR_INTR_CLR                     HWIO_32_WO
+#define HWN_IR_INTR_CLR                     IR_INTR
+#define HWI_IR_INTR_CLR                     
+#define HW_IR_INTR_TOG                      HW(IR_INTR_TOG)
+#define HWA_IR_INTR_TOG                     (HWA_IR_INTR + 0xc)
+#define HWT_IR_INTR_TOG                     HWIO_32_WO
+#define HWN_IR_INTR_TOG                     IR_INTR
+#define HWI_IR_INTR_TOG                     
+#define BP_IR_INTR_RXABORT_IRQ_EN           22
+#define BM_IR_INTR_RXABORT_IRQ_EN           0x400000
+#define BV_IR_INTR_RXABORT_IRQ_EN__DISABLED 0x0
+#define BV_IR_INTR_RXABORT_IRQ_EN__ENABLED  0x1
+#define BF_IR_INTR_RXABORT_IRQ_EN(v)        (((v) & 0x1) << 22)
+#define BFM_IR_INTR_RXABORT_IRQ_EN(v)       BM_IR_INTR_RXABORT_IRQ_EN
+#define BF_IR_INTR_RXABORT_IRQ_EN_V(e)      BF_IR_INTR_RXABORT_IRQ_EN(BV_IR_INTR_RXABORT_IRQ_EN__##e)
+#define BFM_IR_INTR_RXABORT_IRQ_EN_V(v)     BM_IR_INTR_RXABORT_IRQ_EN
+#define BP_IR_INTR_SPEED_IRQ_EN             21
+#define BM_IR_INTR_SPEED_IRQ_EN             0x200000
+#define BV_IR_INTR_SPEED_IRQ_EN__DISABLED   0x0
+#define BV_IR_INTR_SPEED_IRQ_EN__ENABLED    0x1
+#define BF_IR_INTR_SPEED_IRQ_EN(v)          (((v) & 0x1) << 21)
+#define BFM_IR_INTR_SPEED_IRQ_EN(v)         BM_IR_INTR_SPEED_IRQ_EN
+#define BF_IR_INTR_SPEED_IRQ_EN_V(e)        BF_IR_INTR_SPEED_IRQ_EN(BV_IR_INTR_SPEED_IRQ_EN__##e)
+#define BFM_IR_INTR_SPEED_IRQ_EN_V(v)       BM_IR_INTR_SPEED_IRQ_EN
+#define BP_IR_INTR_RXOF_IRQ_EN              20
+#define BM_IR_INTR_RXOF_IRQ_EN              0x100000
+#define BV_IR_INTR_RXOF_IRQ_EN__DISABLED    0x0
+#define BV_IR_INTR_RXOF_IRQ_EN__ENABLED     0x1
+#define BF_IR_INTR_RXOF_IRQ_EN(v)           (((v) & 0x1) << 20)
+#define BFM_IR_INTR_RXOF_IRQ_EN(v)          BM_IR_INTR_RXOF_IRQ_EN
+#define BF_IR_INTR_RXOF_IRQ_EN_V(e)         BF_IR_INTR_RXOF_IRQ_EN(BV_IR_INTR_RXOF_IRQ_EN__##e)
+#define BFM_IR_INTR_RXOF_IRQ_EN_V(v)        BM_IR_INTR_RXOF_IRQ_EN
+#define BP_IR_INTR_TXUF_IRQ_EN              19
+#define BM_IR_INTR_TXUF_IRQ_EN              0x80000
+#define BV_IR_INTR_TXUF_IRQ_EN__DISABLED    0x0
+#define BV_IR_INTR_TXUF_IRQ_EN__ENABLED     0x1
+#define BF_IR_INTR_TXUF_IRQ_EN(v)           (((v) & 0x1) << 19)
+#define BFM_IR_INTR_TXUF_IRQ_EN(v)          BM_IR_INTR_TXUF_IRQ_EN
+#define BF_IR_INTR_TXUF_IRQ_EN_V(e)         BF_IR_INTR_TXUF_IRQ_EN(BV_IR_INTR_TXUF_IRQ_EN__##e)
+#define BFM_IR_INTR_TXUF_IRQ_EN_V(v)        BM_IR_INTR_TXUF_IRQ_EN
+#define BP_IR_INTR_TC_IRQ_EN                18
+#define BM_IR_INTR_TC_IRQ_EN                0x40000
+#define BV_IR_INTR_TC_IRQ_EN__DISABLED      0x0
+#define BV_IR_INTR_TC_IRQ_EN__ENABLED       0x1
+#define BF_IR_INTR_TC_IRQ_EN(v)             (((v) & 0x1) << 18)
+#define BFM_IR_INTR_TC_IRQ_EN(v)            BM_IR_INTR_TC_IRQ_EN
+#define BF_IR_INTR_TC_IRQ_EN_V(e)           BF_IR_INTR_TC_IRQ_EN(BV_IR_INTR_TC_IRQ_EN__##e)
+#define BFM_IR_INTR_TC_IRQ_EN_V(v)          BM_IR_INTR_TC_IRQ_EN
+#define BP_IR_INTR_RX_IRQ_EN                17
+#define BM_IR_INTR_RX_IRQ_EN                0x20000
+#define BV_IR_INTR_RX_IRQ_EN__DISABLED      0x0
+#define BV_IR_INTR_RX_IRQ_EN__ENABLED       0x1
+#define BF_IR_INTR_RX_IRQ_EN(v)             (((v) & 0x1) << 17)
+#define BFM_IR_INTR_RX_IRQ_EN(v)            BM_IR_INTR_RX_IRQ_EN
+#define BF_IR_INTR_RX_IRQ_EN_V(e)           BF_IR_INTR_RX_IRQ_EN(BV_IR_INTR_RX_IRQ_EN__##e)
+#define BFM_IR_INTR_RX_IRQ_EN_V(v)          BM_IR_INTR_RX_IRQ_EN
+#define BP_IR_INTR_TX_IRQ_EN                16
+#define BM_IR_INTR_TX_IRQ_EN                0x10000
+#define BV_IR_INTR_TX_IRQ_EN__DISABLED      0x0
+#define BV_IR_INTR_TX_IRQ_EN__ENABLED       0x1
+#define BF_IR_INTR_TX_IRQ_EN(v)             (((v) & 0x1) << 16)
+#define BFM_IR_INTR_TX_IRQ_EN(v)            BM_IR_INTR_TX_IRQ_EN
+#define BF_IR_INTR_TX_IRQ_EN_V(e)           BF_IR_INTR_TX_IRQ_EN(BV_IR_INTR_TX_IRQ_EN__##e)
+#define BFM_IR_INTR_TX_IRQ_EN_V(v)          BM_IR_INTR_TX_IRQ_EN
+#define BP_IR_INTR_RXABORT_IRQ              6
+#define BM_IR_INTR_RXABORT_IRQ              0x40
+#define BV_IR_INTR_RXABORT_IRQ__NO_REQUEST  0x0
+#define BV_IR_INTR_RXABORT_IRQ__REQUEST     0x1
+#define BF_IR_INTR_RXABORT_IRQ(v)           (((v) & 0x1) << 6)
+#define BFM_IR_INTR_RXABORT_IRQ(v)          BM_IR_INTR_RXABORT_IRQ
+#define BF_IR_INTR_RXABORT_IRQ_V(e)         BF_IR_INTR_RXABORT_IRQ(BV_IR_INTR_RXABORT_IRQ__##e)
+#define BFM_IR_INTR_RXABORT_IRQ_V(v)        BM_IR_INTR_RXABORT_IRQ
+#define BP_IR_INTR_SPEED_IRQ                5
+#define BM_IR_INTR_SPEED_IRQ                0x20
+#define BV_IR_INTR_SPEED_IRQ__NO_REQUEST    0x0
+#define BV_IR_INTR_SPEED_IRQ__REQUEST       0x1
+#define BF_IR_INTR_SPEED_IRQ(v)             (((v) & 0x1) << 5)
+#define BFM_IR_INTR_SPEED_IRQ(v)            BM_IR_INTR_SPEED_IRQ
+#define BF_IR_INTR_SPEED_IRQ_V(e)           BF_IR_INTR_SPEED_IRQ(BV_IR_INTR_SPEED_IRQ__##e)
+#define BFM_IR_INTR_SPEED_IRQ_V(v)          BM_IR_INTR_SPEED_IRQ
+#define BP_IR_INTR_RXOF_IRQ                 4
+#define BM_IR_INTR_RXOF_IRQ                 0x10
+#define BV_IR_INTR_RXOF_IRQ__NO_REQUEST     0x0
+#define BV_IR_INTR_RXOF_IRQ__REQUEST        0x1
+#define BF_IR_INTR_RXOF_IRQ(v)              (((v) & 0x1) << 4)
+#define BFM_IR_INTR_RXOF_IRQ(v)             BM_IR_INTR_RXOF_IRQ
+#define BF_IR_INTR_RXOF_IRQ_V(e)            BF_IR_INTR_RXOF_IRQ(BV_IR_INTR_RXOF_IRQ__##e)
+#define BFM_IR_INTR_RXOF_IRQ_V(v)           BM_IR_INTR_RXOF_IRQ
+#define BP_IR_INTR_TXUF_IRQ                 3
+#define BM_IR_INTR_TXUF_IRQ                 0x8
+#define BV_IR_INTR_TXUF_IRQ__NO_REQUEST     0x0
+#define BV_IR_INTR_TXUF_IRQ__REQUEST        0x1
+#define BF_IR_INTR_TXUF_IRQ(v)              (((v) & 0x1) << 3)
+#define BFM_IR_INTR_TXUF_IRQ(v)             BM_IR_INTR_TXUF_IRQ
+#define BF_IR_INTR_TXUF_IRQ_V(e)            BF_IR_INTR_TXUF_IRQ(BV_IR_INTR_TXUF_IRQ__##e)
+#define BFM_IR_INTR_TXUF_IRQ_V(v)           BM_IR_INTR_TXUF_IRQ
+#define BP_IR_INTR_TC_IRQ                   2
+#define BM_IR_INTR_TC_IRQ                   0x4
+#define BV_IR_INTR_TC_IRQ__NO_REQUEST       0x0
+#define BV_IR_INTR_TC_IRQ__REQUEST          0x1
+#define BF_IR_INTR_TC_IRQ(v)                (((v) & 0x1) << 2)
+#define BFM_IR_INTR_TC_IRQ(v)               BM_IR_INTR_TC_IRQ
+#define BF_IR_INTR_TC_IRQ_V(e)              BF_IR_INTR_TC_IRQ(BV_IR_INTR_TC_IRQ__##e)
+#define BFM_IR_INTR_TC_IRQ_V(v)             BM_IR_INTR_TC_IRQ
+#define BP_IR_INTR_RX_IRQ                   1
+#define BM_IR_INTR_RX_IRQ                   0x2
+#define BV_IR_INTR_RX_IRQ__NO_REQUEST       0x0
+#define BV_IR_INTR_RX_IRQ__REQUEST          0x1
+#define BF_IR_INTR_RX_IRQ(v)                (((v) & 0x1) << 1)
+#define BFM_IR_INTR_RX_IRQ(v)               BM_IR_INTR_RX_IRQ
+#define BF_IR_INTR_RX_IRQ_V(e)              BF_IR_INTR_RX_IRQ(BV_IR_INTR_RX_IRQ__##e)
+#define BFM_IR_INTR_RX_IRQ_V(v)             BM_IR_INTR_RX_IRQ
+#define BP_IR_INTR_TX_IRQ                   0
+#define BM_IR_INTR_TX_IRQ                   0x1
+#define BV_IR_INTR_TX_IRQ__NO_REQUEST       0x0
+#define BV_IR_INTR_TX_IRQ__REQUEST          0x1
+#define BF_IR_INTR_TX_IRQ(v)                (((v) & 0x1) << 0)
+#define BFM_IR_INTR_TX_IRQ(v)               BM_IR_INTR_TX_IRQ
+#define BF_IR_INTR_TX_IRQ_V(e)              BF_IR_INTR_TX_IRQ(BV_IR_INTR_TX_IRQ__##e)
+#define BFM_IR_INTR_TX_IRQ_V(v)             BM_IR_INTR_TX_IRQ
+
+#define HW_IR_DATA              HW(IR_DATA)
+#define HWA_IR_DATA             (0x80078000 + 0x50)
+#define HWT_IR_DATA             HWIO_32_RW
+#define HWN_IR_DATA             IR_DATA
+#define HWI_IR_DATA             
+#define BP_IR_DATA_DATA         0
+#define BM_IR_DATA_DATA         0xffffffff
+#define BF_IR_DATA_DATA(v)      (((v) & 0xffffffff) << 0)
+#define BFM_IR_DATA_DATA(v)     BM_IR_DATA_DATA
+#define BF_IR_DATA_DATA_V(e)    BF_IR_DATA_DATA(BV_IR_DATA_DATA__##e)
+#define BFM_IR_DATA_DATA_V(v)   BM_IR_DATA_DATA
+
+#define HW_IR_STAT                              HW(IR_STAT)
+#define HWA_IR_STAT                             (0x80078000 + 0x60)
+#define HWT_IR_STAT                             HWIO_32_RW
+#define HWN_IR_STAT                             IR_STAT
+#define HWI_IR_STAT                             
+#define BP_IR_STAT_PRESENT                      31
+#define BM_IR_STAT_PRESENT                      0x80000000
+#define BV_IR_STAT_PRESENT__UNAVAILABLE         0x0
+#define BV_IR_STAT_PRESENT__AVAILABLE           0x1
+#define BF_IR_STAT_PRESENT(v)                   (((v) & 0x1) << 31)
+#define BFM_IR_STAT_PRESENT(v)                  BM_IR_STAT_PRESENT
+#define BF_IR_STAT_PRESENT_V(e)                 BF_IR_STAT_PRESENT(BV_IR_STAT_PRESENT__##e)
+#define BFM_IR_STAT_PRESENT_V(v)                BM_IR_STAT_PRESENT
+#define BP_IR_STAT_MODE_ALLOWED                 29
+#define BM_IR_STAT_MODE_ALLOWED                 0x60000000
+#define BV_IR_STAT_MODE_ALLOWED__VFIR           0x0
+#define BV_IR_STAT_MODE_ALLOWED__FIR            0x1
+#define BV_IR_STAT_MODE_ALLOWED__MIR            0x2
+#define BV_IR_STAT_MODE_ALLOWED__SIR            0x3
+#define BF_IR_STAT_MODE_ALLOWED(v)              (((v) & 0x3) << 29)
+#define BFM_IR_STAT_MODE_ALLOWED(v)             BM_IR_STAT_MODE_ALLOWED
+#define BF_IR_STAT_MODE_ALLOWED_V(e)            BF_IR_STAT_MODE_ALLOWED(BV_IR_STAT_MODE_ALLOWED__##e)
+#define BFM_IR_STAT_MODE_ALLOWED_V(v)           BM_IR_STAT_MODE_ALLOWED
+#define BP_IR_STAT_ANY_IRQ                      28
+#define BM_IR_STAT_ANY_IRQ                      0x10000000
+#define BV_IR_STAT_ANY_IRQ__NO_REQUEST          0x0
+#define BV_IR_STAT_ANY_IRQ__REQUEST             0x1
+#define BF_IR_STAT_ANY_IRQ(v)                   (((v) & 0x1) << 28)
+#define BFM_IR_STAT_ANY_IRQ(v)                  BM_IR_STAT_ANY_IRQ
+#define BF_IR_STAT_ANY_IRQ_V(e)                 BF_IR_STAT_ANY_IRQ(BV_IR_STAT_ANY_IRQ__##e)
+#define BFM_IR_STAT_ANY_IRQ_V(v)                BM_IR_STAT_ANY_IRQ
+#define BP_IR_STAT_RXABORT_SUMMARY              22
+#define BM_IR_STAT_RXABORT_SUMMARY              0x400000
+#define BV_IR_STAT_RXABORT_SUMMARY__NO_REQUEST  0x0
+#define BV_IR_STAT_RXABORT_SUMMARY__REQUEST     0x1
+#define BF_IR_STAT_RXABORT_SUMMARY(v)           (((v) & 0x1) << 22)
+#define BFM_IR_STAT_RXABORT_SUMMARY(v)          BM_IR_STAT_RXABORT_SUMMARY
+#define BF_IR_STAT_RXABORT_SUMMARY_V(e)         BF_IR_STAT_RXABORT_SUMMARY(BV_IR_STAT_RXABORT_SUMMARY__##e)
+#define BFM_IR_STAT_RXABORT_SUMMARY_V(v)        BM_IR_STAT_RXABORT_SUMMARY
+#define BP_IR_STAT_SPEED_SUMMARY                21
+#define BM_IR_STAT_SPEED_SUMMARY                0x200000
+#define BV_IR_STAT_SPEED_SUMMARY__NO_REQUEST    0x0
+#define BV_IR_STAT_SPEED_SUMMARY__REQUEST       0x1
+#define BF_IR_STAT_SPEED_SUMMARY(v)             (((v) & 0x1) << 21)
+#define BFM_IR_STAT_SPEED_SUMMARY(v)            BM_IR_STAT_SPEED_SUMMARY
+#define BF_IR_STAT_SPEED_SUMMARY_V(e)           BF_IR_STAT_SPEED_SUMMARY(BV_IR_STAT_SPEED_SUMMARY__##e)
+#define BFM_IR_STAT_SPEED_SUMMARY_V(v)          BM_IR_STAT_SPEED_SUMMARY
+#define BP_IR_STAT_RXOF_SUMMARY                 20
+#define BM_IR_STAT_RXOF_SUMMARY                 0x100000
+#define BV_IR_STAT_RXOF_SUMMARY__NO_REQUEST     0x0
+#define BV_IR_STAT_RXOF_SUMMARY__REQUEST        0x1
+#define BF_IR_STAT_RXOF_SUMMARY(v)              (((v) & 0x1) << 20)
+#define BFM_IR_STAT_RXOF_SUMMARY(v)             BM_IR_STAT_RXOF_SUMMARY
+#define BF_IR_STAT_RXOF_SUMMARY_V(e)            BF_IR_STAT_RXOF_SUMMARY(BV_IR_STAT_RXOF_SUMMARY__##e)
+#define BFM_IR_STAT_RXOF_SUMMARY_V(v)           BM_IR_STAT_RXOF_SUMMARY
+#define BP_IR_STAT_TXUF_SUMMARY                 19
+#define BM_IR_STAT_TXUF_SUMMARY                 0x80000
+#define BV_IR_STAT_TXUF_SUMMARY__NO_REQUEST     0x0
+#define BV_IR_STAT_TXUF_SUMMARY__REQUEST        0x1
+#define BF_IR_STAT_TXUF_SUMMARY(v)              (((v) & 0x1) << 19)
+#define BFM_IR_STAT_TXUF_SUMMARY(v)             BM_IR_STAT_TXUF_SUMMARY
+#define BF_IR_STAT_TXUF_SUMMARY_V(e)            BF_IR_STAT_TXUF_SUMMARY(BV_IR_STAT_TXUF_SUMMARY__##e)
+#define BFM_IR_STAT_TXUF_SUMMARY_V(v)           BM_IR_STAT_TXUF_SUMMARY
+#define BP_IR_STAT_TC_SUMMARY                   18
+#define BM_IR_STAT_TC_SUMMARY                   0x40000
+#define BV_IR_STAT_TC_SUMMARY__NO_REQUEST       0x0
+#define BV_IR_STAT_TC_SUMMARY__REQUEST          0x1
+#define BF_IR_STAT_TC_SUMMARY(v)                (((v) & 0x1) << 18)
+#define BFM_IR_STAT_TC_SUMMARY(v)               BM_IR_STAT_TC_SUMMARY
+#define BF_IR_STAT_TC_SUMMARY_V(e)              BF_IR_STAT_TC_SUMMARY(BV_IR_STAT_TC_SUMMARY__##e)
+#define BFM_IR_STAT_TC_SUMMARY_V(v)             BM_IR_STAT_TC_SUMMARY
+#define BP_IR_STAT_RX_SUMMARY                   17
+#define BM_IR_STAT_RX_SUMMARY                   0x20000
+#define BV_IR_STAT_RX_SUMMARY__NO_REQUEST       0x0
+#define BV_IR_STAT_RX_SUMMARY__REQUEST          0x1
+#define BF_IR_STAT_RX_SUMMARY(v)                (((v) & 0x1) << 17)
+#define BFM_IR_STAT_RX_SUMMARY(v)               BM_IR_STAT_RX_SUMMARY
+#define BF_IR_STAT_RX_SUMMARY_V(e)              BF_IR_STAT_RX_SUMMARY(BV_IR_STAT_RX_SUMMARY__##e)
+#define BFM_IR_STAT_RX_SUMMARY_V(v)             BM_IR_STAT_RX_SUMMARY
+#define BP_IR_STAT_TX_SUMMARY                   16
+#define BM_IR_STAT_TX_SUMMARY                   0x10000
+#define BV_IR_STAT_TX_SUMMARY__NO_REQUEST       0x0
+#define BV_IR_STAT_TX_SUMMARY__REQUEST          0x1
+#define BF_IR_STAT_TX_SUMMARY(v)                (((v) & 0x1) << 16)
+#define BFM_IR_STAT_TX_SUMMARY(v)               BM_IR_STAT_TX_SUMMARY
+#define BF_IR_STAT_TX_SUMMARY_V(e)              BF_IR_STAT_TX_SUMMARY(BV_IR_STAT_TX_SUMMARY__##e)
+#define BFM_IR_STAT_TX_SUMMARY_V(v)             BM_IR_STAT_TX_SUMMARY
+#define BP_IR_STAT_MEDIA_BUSY                   2
+#define BM_IR_STAT_MEDIA_BUSY                   0x4
+#define BF_IR_STAT_MEDIA_BUSY(v)                (((v) & 0x1) << 2)
+#define BFM_IR_STAT_MEDIA_BUSY(v)               BM_IR_STAT_MEDIA_BUSY
+#define BF_IR_STAT_MEDIA_BUSY_V(e)              BF_IR_STAT_MEDIA_BUSY(BV_IR_STAT_MEDIA_BUSY__##e)
+#define BFM_IR_STAT_MEDIA_BUSY_V(v)             BM_IR_STAT_MEDIA_BUSY
+#define BP_IR_STAT_RX_ACTIVE                    1
+#define BM_IR_STAT_RX_ACTIVE                    0x2
+#define BF_IR_STAT_RX_ACTIVE(v)                 (((v) & 0x1) << 1)
+#define BFM_IR_STAT_RX_ACTIVE(v)                BM_IR_STAT_RX_ACTIVE
+#define BF_IR_STAT_RX_ACTIVE_V(e)               BF_IR_STAT_RX_ACTIVE(BV_IR_STAT_RX_ACTIVE__##e)
+#define BFM_IR_STAT_RX_ACTIVE_V(v)              BM_IR_STAT_RX_ACTIVE
+#define BP_IR_STAT_TX_ACTIVE                    0
+#define BM_IR_STAT_TX_ACTIVE                    0x1
+#define BF_IR_STAT_TX_ACTIVE(v)                 (((v) & 0x1) << 0)
+#define BFM_IR_STAT_TX_ACTIVE(v)                BM_IR_STAT_TX_ACTIVE
+#define BF_IR_STAT_TX_ACTIVE_V(e)               BF_IR_STAT_TX_ACTIVE(BV_IR_STAT_TX_ACTIVE__##e)
+#define BFM_IR_STAT_TX_ACTIVE_V(v)              BM_IR_STAT_TX_ACTIVE
+
+#define HW_IR_TCCTRL                HW(IR_TCCTRL)
+#define HWA_IR_TCCTRL               (0x80078000 + 0x70)
+#define HWT_IR_TCCTRL               HWIO_32_RW
+#define HWN_IR_TCCTRL               IR_TCCTRL
+#define HWI_IR_TCCTRL               
+#define HW_IR_TCCTRL_SET            HW(IR_TCCTRL_SET)
+#define HWA_IR_TCCTRL_SET           (HWA_IR_TCCTRL + 0x4)
+#define HWT_IR_TCCTRL_SET           HWIO_32_WO
+#define HWN_IR_TCCTRL_SET           IR_TCCTRL
+#define HWI_IR_TCCTRL_SET           
+#define HW_IR_TCCTRL_CLR            HW(IR_TCCTRL_CLR)
+#define HWA_IR_TCCTRL_CLR           (HWA_IR_TCCTRL + 0x8)
+#define HWT_IR_TCCTRL_CLR           HWIO_32_WO
+#define HWN_IR_TCCTRL_CLR           IR_TCCTRL
+#define HWI_IR_TCCTRL_CLR           
+#define HW_IR_TCCTRL_TOG            HW(IR_TCCTRL_TOG)
+#define HWA_IR_TCCTRL_TOG           (HWA_IR_TCCTRL + 0xc)
+#define HWT_IR_TCCTRL_TOG           HWIO_32_WO
+#define HWN_IR_TCCTRL_TOG           IR_TCCTRL
+#define HWI_IR_TCCTRL_TOG           
+#define BP_IR_TCCTRL_INIT           31
+#define BM_IR_TCCTRL_INIT           0x80000000
+#define BF_IR_TCCTRL_INIT(v)        (((v) & 0x1) << 31)
+#define BFM_IR_TCCTRL_INIT(v)       BM_IR_TCCTRL_INIT
+#define BF_IR_TCCTRL_INIT_V(e)      BF_IR_TCCTRL_INIT(BV_IR_TCCTRL_INIT__##e)
+#define BFM_IR_TCCTRL_INIT_V(v)     BM_IR_TCCTRL_INIT
+#define BP_IR_TCCTRL_GO             30
+#define BM_IR_TCCTRL_GO             0x40000000
+#define BF_IR_TCCTRL_GO(v)          (((v) & 0x1) << 30)
+#define BFM_IR_TCCTRL_GO(v)         BM_IR_TCCTRL_GO
+#define BF_IR_TCCTRL_GO_V(e)        BF_IR_TCCTRL_GO(BV_IR_TCCTRL_GO__##e)
+#define BFM_IR_TCCTRL_GO_V(v)       BM_IR_TCCTRL_GO
+#define BP_IR_TCCTRL_BUSY           29
+#define BM_IR_TCCTRL_BUSY           0x20000000
+#define BF_IR_TCCTRL_BUSY(v)        (((v) & 0x1) << 29)
+#define BFM_IR_TCCTRL_BUSY(v)       BM_IR_TCCTRL_BUSY
+#define BF_IR_TCCTRL_BUSY_V(e)      BF_IR_TCCTRL_BUSY(BV_IR_TCCTRL_BUSY__##e)
+#define BFM_IR_TCCTRL_BUSY_V(v)     BM_IR_TCCTRL_BUSY
+#define BP_IR_TCCTRL_TEMIC          24
+#define BM_IR_TCCTRL_TEMIC          0x1000000
+#define BV_IR_TCCTRL_TEMIC__LOW     0x0
+#define BV_IR_TCCTRL_TEMIC__HIGH    0x1
+#define BF_IR_TCCTRL_TEMIC(v)       (((v) & 0x1) << 24)
+#define BFM_IR_TCCTRL_TEMIC(v)      BM_IR_TCCTRL_TEMIC
+#define BF_IR_TCCTRL_TEMIC_V(e)     BF_IR_TCCTRL_TEMIC(BV_IR_TCCTRL_TEMIC__##e)
+#define BFM_IR_TCCTRL_TEMIC_V(v)    BM_IR_TCCTRL_TEMIC
+#define BP_IR_TCCTRL_EXT_DATA       16
+#define BM_IR_TCCTRL_EXT_DATA       0xff0000
+#define BF_IR_TCCTRL_EXT_DATA(v)    (((v) & 0xff) << 16)
+#define BFM_IR_TCCTRL_EXT_DATA(v)   BM_IR_TCCTRL_EXT_DATA
+#define BF_IR_TCCTRL_EXT_DATA_V(e)  BF_IR_TCCTRL_EXT_DATA(BV_IR_TCCTRL_EXT_DATA__##e)
+#define BFM_IR_TCCTRL_EXT_DATA_V(v) BM_IR_TCCTRL_EXT_DATA
+#define BP_IR_TCCTRL_DATA           8
+#define BM_IR_TCCTRL_DATA           0xff00
+#define BF_IR_TCCTRL_DATA(v)        (((v) & 0xff) << 8)
+#define BFM_IR_TCCTRL_DATA(v)       BM_IR_TCCTRL_DATA
+#define BF_IR_TCCTRL_DATA_V(e)      BF_IR_TCCTRL_DATA(BV_IR_TCCTRL_DATA__##e)
+#define BFM_IR_TCCTRL_DATA_V(v)     BM_IR_TCCTRL_DATA
+#define BP_IR_TCCTRL_ADDR           5
+#define BM_IR_TCCTRL_ADDR           0xe0
+#define BF_IR_TCCTRL_ADDR(v)        (((v) & 0x7) << 5)
+#define BFM_IR_TCCTRL_ADDR(v)       BM_IR_TCCTRL_ADDR
+#define BF_IR_TCCTRL_ADDR_V(e)      BF_IR_TCCTRL_ADDR(BV_IR_TCCTRL_ADDR__##e)
+#define BFM_IR_TCCTRL_ADDR_V(v)     BM_IR_TCCTRL_ADDR
+#define BP_IR_TCCTRL_INDX           1
+#define BM_IR_TCCTRL_INDX           0x1e
+#define BF_IR_TCCTRL_INDX(v)        (((v) & 0xf) << 1)
+#define BFM_IR_TCCTRL_INDX(v)       BM_IR_TCCTRL_INDX
+#define BF_IR_TCCTRL_INDX_V(e)      BF_IR_TCCTRL_INDX(BV_IR_TCCTRL_INDX__##e)
+#define BFM_IR_TCCTRL_INDX_V(v)     BM_IR_TCCTRL_INDX
+#define BP_IR_TCCTRL_C              0
+#define BM_IR_TCCTRL_C              0x1
+#define BF_IR_TCCTRL_C(v)           (((v) & 0x1) << 0)
+#define BFM_IR_TCCTRL_C(v)          BM_IR_TCCTRL_C
+#define BF_IR_TCCTRL_C_V(e)         BF_IR_TCCTRL_C(BV_IR_TCCTRL_C__##e)
+#define BFM_IR_TCCTRL_C_V(v)        BM_IR_TCCTRL_C
+
+#define HW_IR_SI_READ               HW(IR_SI_READ)
+#define HWA_IR_SI_READ              (0x80078000 + 0x80)
+#define HWT_IR_SI_READ              HWIO_32_RW
+#define HWN_IR_SI_READ              IR_SI_READ
+#define HWI_IR_SI_READ              
+#define BP_IR_SI_READ_ABORT         8
+#define BM_IR_SI_READ_ABORT         0x100
+#define BF_IR_SI_READ_ABORT(v)      (((v) & 0x1) << 8)
+#define BFM_IR_SI_READ_ABORT(v)     BM_IR_SI_READ_ABORT
+#define BF_IR_SI_READ_ABORT_V(e)    BF_IR_SI_READ_ABORT(BV_IR_SI_READ_ABORT__##e)
+#define BFM_IR_SI_READ_ABORT_V(v)   BM_IR_SI_READ_ABORT
+#define BP_IR_SI_READ_DATA          0
+#define BM_IR_SI_READ_DATA          0xff
+#define BF_IR_SI_READ_DATA(v)       (((v) & 0xff) << 0)
+#define BFM_IR_SI_READ_DATA(v)      BM_IR_SI_READ_DATA
+#define BF_IR_SI_READ_DATA_V(e)     BF_IR_SI_READ_DATA(BV_IR_SI_READ_DATA__##e)
+#define BFM_IR_SI_READ_DATA_V(v)    BM_IR_SI_READ_DATA
+
+#define HW_IR_DEBUG                 HW(IR_DEBUG)
+#define HWA_IR_DEBUG                (0x80078000 + 0x90)
+#define HWT_IR_DEBUG                HWIO_32_RW
+#define HWN_IR_DEBUG                IR_DEBUG
+#define HWI_IR_DEBUG                
+#define BP_IR_DEBUG_TXDMAKICK       5
+#define BM_IR_DEBUG_TXDMAKICK       0x20
+#define BF_IR_DEBUG_TXDMAKICK(v)    (((v) & 0x1) << 5)
+#define BFM_IR_DEBUG_TXDMAKICK(v)   BM_IR_DEBUG_TXDMAKICK
+#define BF_IR_DEBUG_TXDMAKICK_V(e)  BF_IR_DEBUG_TXDMAKICK(BV_IR_DEBUG_TXDMAKICK__##e)
+#define BFM_IR_DEBUG_TXDMAKICK_V(v) BM_IR_DEBUG_TXDMAKICK
+#define BP_IR_DEBUG_RXDMAKICK       4
+#define BM_IR_DEBUG_RXDMAKICK       0x10
+#define BF_IR_DEBUG_RXDMAKICK(v)    (((v) & 0x1) << 4)
+#define BFM_IR_DEBUG_RXDMAKICK(v)   BM_IR_DEBUG_RXDMAKICK
+#define BF_IR_DEBUG_RXDMAKICK_V(e)  BF_IR_DEBUG_RXDMAKICK(BV_IR_DEBUG_RXDMAKICK__##e)
+#define BFM_IR_DEBUG_RXDMAKICK_V(v) BM_IR_DEBUG_RXDMAKICK
+#define BP_IR_DEBUG_TXDMAEND        3
+#define BM_IR_DEBUG_TXDMAEND        0x8
+#define BF_IR_DEBUG_TXDMAEND(v)     (((v) & 0x1) << 3)
+#define BFM_IR_DEBUG_TXDMAEND(v)    BM_IR_DEBUG_TXDMAEND
+#define BF_IR_DEBUG_TXDMAEND_V(e)   BF_IR_DEBUG_TXDMAEND(BV_IR_DEBUG_TXDMAEND__##e)
+#define BFM_IR_DEBUG_TXDMAEND_V(v)  BM_IR_DEBUG_TXDMAEND
+#define BP_IR_DEBUG_RXDMAEND        2
+#define BM_IR_DEBUG_RXDMAEND        0x4
+#define BF_IR_DEBUG_RXDMAEND(v)     (((v) & 0x1) << 2)
+#define BFM_IR_DEBUG_RXDMAEND(v)    BM_IR_DEBUG_RXDMAEND
+#define BF_IR_DEBUG_RXDMAEND_V(e)   BF_IR_DEBUG_RXDMAEND(BV_IR_DEBUG_RXDMAEND__##e)
+#define BFM_IR_DEBUG_RXDMAEND_V(v)  BM_IR_DEBUG_RXDMAEND
+#define BP_IR_DEBUG_TXDMAREQ        1
+#define BM_IR_DEBUG_TXDMAREQ        0x2
+#define BF_IR_DEBUG_TXDMAREQ(v)     (((v) & 0x1) << 1)
+#define BFM_IR_DEBUG_TXDMAREQ(v)    BM_IR_DEBUG_TXDMAREQ
+#define BF_IR_DEBUG_TXDMAREQ_V(e)   BF_IR_DEBUG_TXDMAREQ(BV_IR_DEBUG_TXDMAREQ__##e)
+#define BFM_IR_DEBUG_TXDMAREQ_V(v)  BM_IR_DEBUG_TXDMAREQ
+#define BP_IR_DEBUG_RXDMAREQ        0
+#define BM_IR_DEBUG_RXDMAREQ        0x1
+#define BF_IR_DEBUG_RXDMAREQ(v)     (((v) & 0x1) << 0)
+#define BFM_IR_DEBUG_RXDMAREQ(v)    BM_IR_DEBUG_RXDMAREQ
+#define BF_IR_DEBUG_RXDMAREQ_V(e)   BF_IR_DEBUG_RXDMAREQ(BV_IR_DEBUG_RXDMAREQ__##e)
+#define BFM_IR_DEBUG_RXDMAREQ_V(v)  BM_IR_DEBUG_RXDMAREQ
+
+#endif /* __HEADERGEN_STMP3600_IR_H__*/
diff --git a/firmware/target/arm/imx233/regs/stmp3600/lcdif.h b/firmware/target/arm/imx233/regs/stmp3600/lcdif.h
new file mode 100644
index 0000000000..f157b8eb55
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3600/lcdif.h
@@ -0,0 +1,246 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * stmp3600 version: 2.4.0
+ * stmp3600 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_STMP3600_LCDIF_H__
+#define __HEADERGEN_STMP3600_LCDIF_H__
+
+#define HW_LCDIF_CTRL                               HW(LCDIF_CTRL)
+#define HWA_LCDIF_CTRL                              (0x80060000 + 0x0)
+#define HWT_LCDIF_CTRL                              HWIO_32_RW
+#define HWN_LCDIF_CTRL                              LCDIF_CTRL
+#define HWI_LCDIF_CTRL                              
+#define HW_LCDIF_CTRL_SET                           HW(LCDIF_CTRL_SET)
+#define HWA_LCDIF_CTRL_SET                          (HWA_LCDIF_CTRL + 0x4)
+#define HWT_LCDIF_CTRL_SET                          HWIO_32_WO
+#define HWN_LCDIF_CTRL_SET                          LCDIF_CTRL
+#define HWI_LCDIF_CTRL_SET                          
+#define HW_LCDIF_CTRL_CLR                           HW(LCDIF_CTRL_CLR)
+#define HWA_LCDIF_CTRL_CLR                          (HWA_LCDIF_CTRL + 0x8)
+#define HWT_LCDIF_CTRL_CLR                          HWIO_32_WO
+#define HWN_LCDIF_CTRL_CLR                          LCDIF_CTRL
+#define HWI_LCDIF_CTRL_CLR                          
+#define HW_LCDIF_CTRL_TOG                           HW(LCDIF_CTRL_TOG)
+#define HWA_LCDIF_CTRL_TOG                          (HWA_LCDIF_CTRL + 0xc)
+#define HWT_LCDIF_CTRL_TOG                          HWIO_32_WO
+#define HWN_LCDIF_CTRL_TOG                          LCDIF_CTRL
+#define HWI_LCDIF_CTRL_TOG                          
+#define BP_LCDIF_CTRL_SFTRST                        31
+#define BM_LCDIF_CTRL_SFTRST                        0x80000000
+#define BF_LCDIF_CTRL_SFTRST(v)                     (((v) & 0x1) << 31)
+#define BFM_LCDIF_CTRL_SFTRST(v)                    BM_LCDIF_CTRL_SFTRST
+#define BF_LCDIF_CTRL_SFTRST_V(e)                   BF_LCDIF_CTRL_SFTRST(BV_LCDIF_CTRL_SFTRST__##e)
+#define BFM_LCDIF_CTRL_SFTRST_V(v)                  BM_LCDIF_CTRL_SFTRST
+#define BP_LCDIF_CTRL_CLKGATE                       30
+#define BM_LCDIF_CTRL_CLKGATE                       0x40000000
+#define BF_LCDIF_CTRL_CLKGATE(v)                    (((v) & 0x1) << 30)
+#define BFM_LCDIF_CTRL_CLKGATE(v)                   BM_LCDIF_CTRL_CLKGATE
+#define BF_LCDIF_CTRL_CLKGATE_V(e)                  BF_LCDIF_CTRL_CLKGATE(BV_LCDIF_CTRL_CLKGATE__##e)
+#define BFM_LCDIF_CTRL_CLKGATE_V(v)                 BM_LCDIF_CTRL_CLKGATE
+#define BP_LCDIF_CTRL_PRESENT                       29
+#define BM_LCDIF_CTRL_PRESENT                       0x20000000
+#define BF_LCDIF_CTRL_PRESENT(v)                    (((v) & 0x1) << 29)
+#define BFM_LCDIF_CTRL_PRESENT(v)                   BM_LCDIF_CTRL_PRESENT
+#define BF_LCDIF_CTRL_PRESENT_V(e)                  BF_LCDIF_CTRL_PRESENT(BV_LCDIF_CTRL_PRESENT__##e)
+#define BFM_LCDIF_CTRL_PRESENT_V(v)                 BM_LCDIF_CTRL_PRESENT
+#define BP_LCDIF_CTRL_BUSY_ENABLE                   25
+#define BM_LCDIF_CTRL_BUSY_ENABLE                   0x2000000
+#define BV_LCDIF_CTRL_BUSY_ENABLE__BUSY_DISABLED    0x0
+#define BV_LCDIF_CTRL_BUSY_ENABLE__BUSY_ENABLED     0x1
+#define BF_LCDIF_CTRL_BUSY_ENABLE(v)                (((v) & 0x1) << 25)
+#define BFM_LCDIF_CTRL_BUSY_ENABLE(v)               BM_LCDIF_CTRL_BUSY_ENABLE
+#define BF_LCDIF_CTRL_BUSY_ENABLE_V(e)              BF_LCDIF_CTRL_BUSY_ENABLE(BV_LCDIF_CTRL_BUSY_ENABLE__##e)
+#define BFM_LCDIF_CTRL_BUSY_ENABLE_V(v)             BM_LCDIF_CTRL_BUSY_ENABLE
+#define BP_LCDIF_CTRL_FIFO_STATUS                   24
+#define BM_LCDIF_CTRL_FIFO_STATUS                   0x1000000
+#define BV_LCDIF_CTRL_FIFO_STATUS__FIFO_FULL        0x0
+#define BV_LCDIF_CTRL_FIFO_STATUS__FIFO_OK          0x1
+#define BF_LCDIF_CTRL_FIFO_STATUS(v)                (((v) & 0x1) << 24)
+#define BFM_LCDIF_CTRL_FIFO_STATUS(v)               BM_LCDIF_CTRL_FIFO_STATUS
+#define BF_LCDIF_CTRL_FIFO_STATUS_V(e)              BF_LCDIF_CTRL_FIFO_STATUS(BV_LCDIF_CTRL_FIFO_STATUS__##e)
+#define BFM_LCDIF_CTRL_FIFO_STATUS_V(v)             BM_LCDIF_CTRL_FIFO_STATUS
+#define BP_LCDIF_CTRL_DMA_REQ                       23
+#define BM_LCDIF_CTRL_DMA_REQ                       0x800000
+#define BF_LCDIF_CTRL_DMA_REQ(v)                    (((v) & 0x1) << 23)
+#define BFM_LCDIF_CTRL_DMA_REQ(v)                   BM_LCDIF_CTRL_DMA_REQ
+#define BF_LCDIF_CTRL_DMA_REQ_V(e)                  BF_LCDIF_CTRL_DMA_REQ(BV_LCDIF_CTRL_DMA_REQ__##e)
+#define BFM_LCDIF_CTRL_DMA_REQ_V(v)                 BM_LCDIF_CTRL_DMA_REQ
+#define BP_LCDIF_CTRL_DATA_SWIZZLE                  21
+#define BM_LCDIF_CTRL_DATA_SWIZZLE                  0x600000
+#define BV_LCDIF_CTRL_DATA_SWIZZLE__NO_SWAP         0x0
+#define BV_LCDIF_CTRL_DATA_SWIZZLE__LITTLE_ENDIAN   0x0
+#define BV_LCDIF_CTRL_DATA_SWIZZLE__BIG_ENDIAN_SWAP 0x1
+#define BV_LCDIF_CTRL_DATA_SWIZZLE__SWAP_ALL_BYTES  0x1
+#define BV_LCDIF_CTRL_DATA_SWIZZLE__HWD_SWAP        0x2
+#define BV_LCDIF_CTRL_DATA_SWIZZLE__HWD_BYTE_SWAP   0x3
+#define BF_LCDIF_CTRL_DATA_SWIZZLE(v)               (((v) & 0x3) << 21)
+#define BFM_LCDIF_CTRL_DATA_SWIZZLE(v)              BM_LCDIF_CTRL_DATA_SWIZZLE
+#define BF_LCDIF_CTRL_DATA_SWIZZLE_V(e)             BF_LCDIF_CTRL_DATA_SWIZZLE(BV_LCDIF_CTRL_DATA_SWIZZLE__##e)
+#define BFM_LCDIF_CTRL_DATA_SWIZZLE_V(v)            BM_LCDIF_CTRL_DATA_SWIZZLE
+#define BP_LCDIF_CTRL_RESET                         20
+#define BM_LCDIF_CTRL_RESET                         0x100000
+#define BV_LCDIF_CTRL_RESET__LCDRESET_LOW           0x0
+#define BV_LCDIF_CTRL_RESET__LCDRESET_HIGH          0x1
+#define BF_LCDIF_CTRL_RESET(v)                      (((v) & 0x1) << 20)
+#define BFM_LCDIF_CTRL_RESET(v)                     BM_LCDIF_CTRL_RESET
+#define BF_LCDIF_CTRL_RESET_V(e)                    BF_LCDIF_CTRL_RESET(BV_LCDIF_CTRL_RESET__##e)
+#define BFM_LCDIF_CTRL_RESET_V(v)                   BM_LCDIF_CTRL_RESET
+#define BP_LCDIF_CTRL_MODE86                        19
+#define BM_LCDIF_CTRL_MODE86                        0x80000
+#define BV_LCDIF_CTRL_MODE86__8080_MODE             0x0
+#define BV_LCDIF_CTRL_MODE86__6800_MODE             0x1
+#define BF_LCDIF_CTRL_MODE86(v)                     (((v) & 0x1) << 19)
+#define BFM_LCDIF_CTRL_MODE86(v)                    BM_LCDIF_CTRL_MODE86
+#define BF_LCDIF_CTRL_MODE86_V(e)                   BF_LCDIF_CTRL_MODE86(BV_LCDIF_CTRL_MODE86__##e)
+#define BFM_LCDIF_CTRL_MODE86_V(v)                  BM_LCDIF_CTRL_MODE86
+#define BP_LCDIF_CTRL_DATA_SELECT                   18
+#define BM_LCDIF_CTRL_DATA_SELECT                   0x40000
+#define BV_LCDIF_CTRL_DATA_SELECT__CMD_MODE         0x0
+#define BV_LCDIF_CTRL_DATA_SELECT__DATA_MODE        0x1
+#define BF_LCDIF_CTRL_DATA_SELECT(v)                (((v) & 0x1) << 18)
+#define BFM_LCDIF_CTRL_DATA_SELECT(v)               BM_LCDIF_CTRL_DATA_SELECT
+#define BF_LCDIF_CTRL_DATA_SELECT_V(e)              BF_LCDIF_CTRL_DATA_SELECT(BV_LCDIF_CTRL_DATA_SELECT__##e)
+#define BFM_LCDIF_CTRL_DATA_SELECT_V(v)             BM_LCDIF_CTRL_DATA_SELECT
+#define BP_LCDIF_CTRL_WORD_LENGTH                   17
+#define BM_LCDIF_CTRL_WORD_LENGTH                   0x20000
+#define BV_LCDIF_CTRL_WORD_LENGTH__16_BIT           0x0
+#define BV_LCDIF_CTRL_WORD_LENGTH__8_BIT            0x1
+#define BF_LCDIF_CTRL_WORD_LENGTH(v)                (((v) & 0x1) << 17)
+#define BFM_LCDIF_CTRL_WORD_LENGTH(v)               BM_LCDIF_CTRL_WORD_LENGTH
+#define BF_LCDIF_CTRL_WORD_LENGTH_V(e)              BF_LCDIF_CTRL_WORD_LENGTH(BV_LCDIF_CTRL_WORD_LENGTH__##e)
+#define BFM_LCDIF_CTRL_WORD_LENGTH_V(v)             BM_LCDIF_CTRL_WORD_LENGTH
+#define BP_LCDIF_CTRL_RUN                           16
+#define BM_LCDIF_CTRL_RUN                           0x10000
+#define BF_LCDIF_CTRL_RUN(v)                        (((v) & 0x1) << 16)
+#define BFM_LCDIF_CTRL_RUN(v)                       BM_LCDIF_CTRL_RUN
+#define BF_LCDIF_CTRL_RUN_V(e)                      BF_LCDIF_CTRL_RUN(BV_LCDIF_CTRL_RUN__##e)
+#define BFM_LCDIF_CTRL_RUN_V(v)                     BM_LCDIF_CTRL_RUN
+#define BP_LCDIF_CTRL_COUNT                         0
+#define BM_LCDIF_CTRL_COUNT                         0xffff
+#define BF_LCDIF_CTRL_COUNT(v)                      (((v) & 0xffff) << 0)
+#define BFM_LCDIF_CTRL_COUNT(v)                     BM_LCDIF_CTRL_COUNT
+#define BF_LCDIF_CTRL_COUNT_V(e)                    BF_LCDIF_CTRL_COUNT(BV_LCDIF_CTRL_COUNT__##e)
+#define BFM_LCDIF_CTRL_COUNT_V(v)                   BM_LCDIF_CTRL_COUNT
+
+#define HW_LCDIF_TIMING                     HW(LCDIF_TIMING)
+#define HWA_LCDIF_TIMING                    (0x80060000 + 0x10)
+#define HWT_LCDIF_TIMING                    HWIO_32_RW
+#define HWN_LCDIF_TIMING                    LCDIF_TIMING
+#define HWI_LCDIF_TIMING                    
+#define BP_LCDIF_TIMING_CMD_HOLD            24
+#define BM_LCDIF_TIMING_CMD_HOLD            0xff000000
+#define BF_LCDIF_TIMING_CMD_HOLD(v)         (((v) & 0xff) << 24)
+#define BFM_LCDIF_TIMING_CMD_HOLD(v)        BM_LCDIF_TIMING_CMD_HOLD
+#define BF_LCDIF_TIMING_CMD_HOLD_V(e)       BF_LCDIF_TIMING_CMD_HOLD(BV_LCDIF_TIMING_CMD_HOLD__##e)
+#define BFM_LCDIF_TIMING_CMD_HOLD_V(v)      BM_LCDIF_TIMING_CMD_HOLD
+#define BP_LCDIF_TIMING_CMD_SETUP           16
+#define BM_LCDIF_TIMING_CMD_SETUP           0xff0000
+#define BF_LCDIF_TIMING_CMD_SETUP(v)        (((v) & 0xff) << 16)
+#define BFM_LCDIF_TIMING_CMD_SETUP(v)       BM_LCDIF_TIMING_CMD_SETUP
+#define BF_LCDIF_TIMING_CMD_SETUP_V(e)      BF_LCDIF_TIMING_CMD_SETUP(BV_LCDIF_TIMING_CMD_SETUP__##e)
+#define BFM_LCDIF_TIMING_CMD_SETUP_V(v)     BM_LCDIF_TIMING_CMD_SETUP
+#define BP_LCDIF_TIMING_DATA_HOLD           8
+#define BM_LCDIF_TIMING_DATA_HOLD           0xff00
+#define BF_LCDIF_TIMING_DATA_HOLD(v)        (((v) & 0xff) << 8)
+#define BFM_LCDIF_TIMING_DATA_HOLD(v)       BM_LCDIF_TIMING_DATA_HOLD
+#define BF_LCDIF_TIMING_DATA_HOLD_V(e)      BF_LCDIF_TIMING_DATA_HOLD(BV_LCDIF_TIMING_DATA_HOLD__##e)
+#define BFM_LCDIF_TIMING_DATA_HOLD_V(v)     BM_LCDIF_TIMING_DATA_HOLD
+#define BP_LCDIF_TIMING_DATA_SETUP          0
+#define BM_LCDIF_TIMING_DATA_SETUP          0xff
+#define BF_LCDIF_TIMING_DATA_SETUP(v)       (((v) & 0xff) << 0)
+#define BFM_LCDIF_TIMING_DATA_SETUP(v)      BM_LCDIF_TIMING_DATA_SETUP
+#define BF_LCDIF_TIMING_DATA_SETUP_V(e)     BF_LCDIF_TIMING_DATA_SETUP(BV_LCDIF_TIMING_DATA_SETUP__##e)
+#define BFM_LCDIF_TIMING_DATA_SETUP_V(v)    BM_LCDIF_TIMING_DATA_SETUP
+
+#define HW_LCDIF_DATA                   HW(LCDIF_DATA)
+#define HWA_LCDIF_DATA                  (0x80060000 + 0x20)
+#define HWT_LCDIF_DATA                  HWIO_32_RW
+#define HWN_LCDIF_DATA                  LCDIF_DATA
+#define HWI_LCDIF_DATA                  
+#define BP_LCDIF_DATA_DATA_THREE        24
+#define BM_LCDIF_DATA_DATA_THREE        0xff000000
+#define BF_LCDIF_DATA_DATA_THREE(v)     (((v) & 0xff) << 24)
+#define BFM_LCDIF_DATA_DATA_THREE(v)    BM_LCDIF_DATA_DATA_THREE
+#define BF_LCDIF_DATA_DATA_THREE_V(e)   BF_LCDIF_DATA_DATA_THREE(BV_LCDIF_DATA_DATA_THREE__##e)
+#define BFM_LCDIF_DATA_DATA_THREE_V(v)  BM_LCDIF_DATA_DATA_THREE
+#define BP_LCDIF_DATA_DATA_TWO          16
+#define BM_LCDIF_DATA_DATA_TWO          0xff0000
+#define BF_LCDIF_DATA_DATA_TWO(v)       (((v) & 0xff) << 16)
+#define BFM_LCDIF_DATA_DATA_TWO(v)      BM_LCDIF_DATA_DATA_TWO
+#define BF_LCDIF_DATA_DATA_TWO_V(e)     BF_LCDIF_DATA_DATA_TWO(BV_LCDIF_DATA_DATA_TWO__##e)
+#define BFM_LCDIF_DATA_DATA_TWO_V(v)    BM_LCDIF_DATA_DATA_TWO
+#define BP_LCDIF_DATA_DATA_ONE          8
+#define BM_LCDIF_DATA_DATA_ONE          0xff00
+#define BF_LCDIF_DATA_DATA_ONE(v)       (((v) & 0xff) << 8)
+#define BFM_LCDIF_DATA_DATA_ONE(v)      BM_LCDIF_DATA_DATA_ONE
+#define BF_LCDIF_DATA_DATA_ONE_V(e)     BF_LCDIF_DATA_DATA_ONE(BV_LCDIF_DATA_DATA_ONE__##e)
+#define BFM_LCDIF_DATA_DATA_ONE_V(v)    BM_LCDIF_DATA_DATA_ONE
+#define BP_LCDIF_DATA_DATA_ZERO         0
+#define BM_LCDIF_DATA_DATA_ZERO         0xff
+#define BF_LCDIF_DATA_DATA_ZERO(v)      (((v) & 0xff) << 0)
+#define BFM_LCDIF_DATA_DATA_ZERO(v)     BM_LCDIF_DATA_DATA_ZERO
+#define BF_LCDIF_DATA_DATA_ZERO_V(e)    BF_LCDIF_DATA_DATA_ZERO(BV_LCDIF_DATA_DATA_ZERO__##e)
+#define BFM_LCDIF_DATA_DATA_ZERO_V(v)   BM_LCDIF_DATA_DATA_ZERO
+
+#define HW_LCDIF_DEBUG                          HW(LCDIF_DEBUG)
+#define HWA_LCDIF_DEBUG                         (0x80060000 + 0x30)
+#define HWT_LCDIF_DEBUG                         HWIO_32_RW
+#define HWN_LCDIF_DEBUG                         LCDIF_DEBUG
+#define HWI_LCDIF_DEBUG                         
+#define BP_LCDIF_DEBUG_BUSY                     27
+#define BM_LCDIF_DEBUG_BUSY                     0x8000000
+#define BF_LCDIF_DEBUG_BUSY(v)                  (((v) & 0x1) << 27)
+#define BFM_LCDIF_DEBUG_BUSY(v)                 BM_LCDIF_DEBUG_BUSY
+#define BF_LCDIF_DEBUG_BUSY_V(e)                BF_LCDIF_DEBUG_BUSY(BV_LCDIF_DEBUG_BUSY__##e)
+#define BFM_LCDIF_DEBUG_BUSY_V(v)               BM_LCDIF_DEBUG_BUSY
+#define BP_LCDIF_DEBUG_LAST_SUBWORD             26
+#define BM_LCDIF_DEBUG_LAST_SUBWORD             0x4000000
+#define BF_LCDIF_DEBUG_LAST_SUBWORD(v)          (((v) & 0x1) << 26)
+#define BFM_LCDIF_DEBUG_LAST_SUBWORD(v)         BM_LCDIF_DEBUG_LAST_SUBWORD
+#define BF_LCDIF_DEBUG_LAST_SUBWORD_V(e)        BF_LCDIF_DEBUG_LAST_SUBWORD(BV_LCDIF_DEBUG_LAST_SUBWORD__##e)
+#define BFM_LCDIF_DEBUG_LAST_SUBWORD_V(v)       BM_LCDIF_DEBUG_LAST_SUBWORD
+#define BP_LCDIF_DEBUG_SUBWORD_POSITION         24
+#define BM_LCDIF_DEBUG_SUBWORD_POSITION         0x3000000
+#define BF_LCDIF_DEBUG_SUBWORD_POSITION(v)      (((v) & 0x3) << 24)
+#define BFM_LCDIF_DEBUG_SUBWORD_POSITION(v)     BM_LCDIF_DEBUG_SUBWORD_POSITION
+#define BF_LCDIF_DEBUG_SUBWORD_POSITION_V(e)    BF_LCDIF_DEBUG_SUBWORD_POSITION(BV_LCDIF_DEBUG_SUBWORD_POSITION__##e)
+#define BFM_LCDIF_DEBUG_SUBWORD_POSITION_V(v)   BM_LCDIF_DEBUG_SUBWORD_POSITION
+#define BP_LCDIF_DEBUG_EMPTY_WORD               23
+#define BM_LCDIF_DEBUG_EMPTY_WORD               0x800000
+#define BF_LCDIF_DEBUG_EMPTY_WORD(v)            (((v) & 0x1) << 23)
+#define BFM_LCDIF_DEBUG_EMPTY_WORD(v)           BM_LCDIF_DEBUG_EMPTY_WORD
+#define BF_LCDIF_DEBUG_EMPTY_WORD_V(e)          BF_LCDIF_DEBUG_EMPTY_WORD(BV_LCDIF_DEBUG_EMPTY_WORD__##e)
+#define BFM_LCDIF_DEBUG_EMPTY_WORD_V(v)         BM_LCDIF_DEBUG_EMPTY_WORD
+#define BP_LCDIF_DEBUG_STATE                    16
+#define BM_LCDIF_DEBUG_STATE                    0x7f0000
+#define BF_LCDIF_DEBUG_STATE(v)                 (((v) & 0x7f) << 16)
+#define BFM_LCDIF_DEBUG_STATE(v)                BM_LCDIF_DEBUG_STATE
+#define BF_LCDIF_DEBUG_STATE_V(e)               BF_LCDIF_DEBUG_STATE(BV_LCDIF_DEBUG_STATE__##e)
+#define BFM_LCDIF_DEBUG_STATE_V(v)              BM_LCDIF_DEBUG_STATE
+#define BP_LCDIF_DEBUG_DATA_COUNT               0
+#define BM_LCDIF_DEBUG_DATA_COUNT               0xffff
+#define BF_LCDIF_DEBUG_DATA_COUNT(v)            (((v) & 0xffff) << 0)
+#define BFM_LCDIF_DEBUG_DATA_COUNT(v)           BM_LCDIF_DEBUG_DATA_COUNT
+#define BF_LCDIF_DEBUG_DATA_COUNT_V(e)          BF_LCDIF_DEBUG_DATA_COUNT(BV_LCDIF_DEBUG_DATA_COUNT__##e)
+#define BFM_LCDIF_DEBUG_DATA_COUNT_V(v)         BM_LCDIF_DEBUG_DATA_COUNT
+
+#endif /* __HEADERGEN_STMP3600_LCDIF_H__*/
diff --git a/firmware/target/arm/imx233/regs/stmp3600/lradc.h b/firmware/target/arm/imx233/regs/stmp3600/lradc.h
new file mode 100644
index 0000000000..2be16a9be9
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3600/lradc.h
@@ -0,0 +1,840 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * stmp3600 version: 2.4.0
+ * stmp3600 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_STMP3600_LRADC_H__
+#define __HEADERGEN_STMP3600_LRADC_H__
+
+#define HW_LRADC_CTRL0                              HW(LRADC_CTRL0)
+#define HWA_LRADC_CTRL0                             (0x80050000 + 0x0)
+#define HWT_LRADC_CTRL0                             HWIO_32_RW
+#define HWN_LRADC_CTRL0                             LRADC_CTRL0
+#define HWI_LRADC_CTRL0                             
+#define HW_LRADC_CTRL0_SET                          HW(LRADC_CTRL0_SET)
+#define HWA_LRADC_CTRL0_SET                         (HWA_LRADC_CTRL0 + 0x4)
+#define HWT_LRADC_CTRL0_SET                         HWIO_32_WO
+#define HWN_LRADC_CTRL0_SET                         LRADC_CTRL0
+#define HWI_LRADC_CTRL0_SET                         
+#define HW_LRADC_CTRL0_CLR                          HW(LRADC_CTRL0_CLR)
+#define HWA_LRADC_CTRL0_CLR                         (HWA_LRADC_CTRL0 + 0x8)
+#define HWT_LRADC_CTRL0_CLR                         HWIO_32_WO
+#define HWN_LRADC_CTRL0_CLR                         LRADC_CTRL0
+#define HWI_LRADC_CTRL0_CLR                         
+#define HW_LRADC_CTRL0_TOG                          HW(LRADC_CTRL0_TOG)
+#define HWA_LRADC_CTRL0_TOG                         (HWA_LRADC_CTRL0 + 0xc)
+#define HWT_LRADC_CTRL0_TOG                         HWIO_32_WO
+#define HWN_LRADC_CTRL0_TOG                         LRADC_CTRL0
+#define HWI_LRADC_CTRL0_TOG                         
+#define BP_LRADC_CTRL0_SFTRST                       31
+#define BM_LRADC_CTRL0_SFTRST                       0x80000000
+#define BF_LRADC_CTRL0_SFTRST(v)                    (((v) & 0x1) << 31)
+#define BFM_LRADC_CTRL0_SFTRST(v)                   BM_LRADC_CTRL0_SFTRST
+#define BF_LRADC_CTRL0_SFTRST_V(e)                  BF_LRADC_CTRL0_SFTRST(BV_LRADC_CTRL0_SFTRST__##e)
+#define BFM_LRADC_CTRL0_SFTRST_V(v)                 BM_LRADC_CTRL0_SFTRST
+#define BP_LRADC_CTRL0_CLKGATE                      30
+#define BM_LRADC_CTRL0_CLKGATE                      0x40000000
+#define BF_LRADC_CTRL0_CLKGATE(v)                   (((v) & 0x1) << 30)
+#define BFM_LRADC_CTRL0_CLKGATE(v)                  BM_LRADC_CTRL0_CLKGATE
+#define BF_LRADC_CTRL0_CLKGATE_V(e)                 BF_LRADC_CTRL0_CLKGATE(BV_LRADC_CTRL0_CLKGATE__##e)
+#define BFM_LRADC_CTRL0_CLKGATE_V(v)                BM_LRADC_CTRL0_CLKGATE
+#define BP_LRADC_CTRL0_ONCHIP_GROUNDREF             21
+#define BM_LRADC_CTRL0_ONCHIP_GROUNDREF             0x200000
+#define BV_LRADC_CTRL0_ONCHIP_GROUNDREF__OFF        0x0
+#define BV_LRADC_CTRL0_ONCHIP_GROUNDREF__ON         0x1
+#define BF_LRADC_CTRL0_ONCHIP_GROUNDREF(v)          (((v) & 0x1) << 21)
+#define BFM_LRADC_CTRL0_ONCHIP_GROUNDREF(v)         BM_LRADC_CTRL0_ONCHIP_GROUNDREF
+#define BF_LRADC_CTRL0_ONCHIP_GROUNDREF_V(e)        BF_LRADC_CTRL0_ONCHIP_GROUNDREF(BV_LRADC_CTRL0_ONCHIP_GROUNDREF__##e)
+#define BFM_LRADC_CTRL0_ONCHIP_GROUNDREF_V(v)       BM_LRADC_CTRL0_ONCHIP_GROUNDREF
+#define BP_LRADC_CTRL0_TOUCH_DETECT_ENABLE          20
+#define BM_LRADC_CTRL0_TOUCH_DETECT_ENABLE          0x100000
+#define BV_LRADC_CTRL0_TOUCH_DETECT_ENABLE__OFF     0x0
+#define BV_LRADC_CTRL0_TOUCH_DETECT_ENABLE__ON      0x1
+#define BF_LRADC_CTRL0_TOUCH_DETECT_ENABLE(v)       (((v) & 0x1) << 20)
+#define BFM_LRADC_CTRL0_TOUCH_DETECT_ENABLE(v)      BM_LRADC_CTRL0_TOUCH_DETECT_ENABLE
+#define BF_LRADC_CTRL0_TOUCH_DETECT_ENABLE_V(e)     BF_LRADC_CTRL0_TOUCH_DETECT_ENABLE(BV_LRADC_CTRL0_TOUCH_DETECT_ENABLE__##e)
+#define BFM_LRADC_CTRL0_TOUCH_DETECT_ENABLE_V(v)    BM_LRADC_CTRL0_TOUCH_DETECT_ENABLE
+#define BP_LRADC_CTRL0_YMINUS_ENABLE                19
+#define BM_LRADC_CTRL0_YMINUS_ENABLE                0x80000
+#define BV_LRADC_CTRL0_YMINUS_ENABLE__OFF           0x0
+#define BV_LRADC_CTRL0_YMINUS_ENABLE__ON            0x1
+#define BF_LRADC_CTRL0_YMINUS_ENABLE(v)             (((v) & 0x1) << 19)
+#define BFM_LRADC_CTRL0_YMINUS_ENABLE(v)            BM_LRADC_CTRL0_YMINUS_ENABLE
+#define BF_LRADC_CTRL0_YMINUS_ENABLE_V(e)           BF_LRADC_CTRL0_YMINUS_ENABLE(BV_LRADC_CTRL0_YMINUS_ENABLE__##e)
+#define BFM_LRADC_CTRL0_YMINUS_ENABLE_V(v)          BM_LRADC_CTRL0_YMINUS_ENABLE
+#define BP_LRADC_CTRL0_XMINUS_ENABLE                18
+#define BM_LRADC_CTRL0_XMINUS_ENABLE                0x40000
+#define BV_LRADC_CTRL0_XMINUS_ENABLE__OFF           0x0
+#define BV_LRADC_CTRL0_XMINUS_ENABLE__ON            0x1
+#define BF_LRADC_CTRL0_XMINUS_ENABLE(v)             (((v) & 0x1) << 18)
+#define BFM_LRADC_CTRL0_XMINUS_ENABLE(v)            BM_LRADC_CTRL0_XMINUS_ENABLE
+#define BF_LRADC_CTRL0_XMINUS_ENABLE_V(e)           BF_LRADC_CTRL0_XMINUS_ENABLE(BV_LRADC_CTRL0_XMINUS_ENABLE__##e)
+#define BFM_LRADC_CTRL0_XMINUS_ENABLE_V(v)          BM_LRADC_CTRL0_XMINUS_ENABLE
+#define BP_LRADC_CTRL0_YPLUS_ENABLE                 17
+#define BM_LRADC_CTRL0_YPLUS_ENABLE                 0x20000
+#define BV_LRADC_CTRL0_YPLUS_ENABLE__OFF            0x0
+#define BV_LRADC_CTRL0_YPLUS_ENABLE__ON             0x1
+#define BF_LRADC_CTRL0_YPLUS_ENABLE(v)              (((v) & 0x1) << 17)
+#define BFM_LRADC_CTRL0_YPLUS_ENABLE(v)             BM_LRADC_CTRL0_YPLUS_ENABLE
+#define BF_LRADC_CTRL0_YPLUS_ENABLE_V(e)            BF_LRADC_CTRL0_YPLUS_ENABLE(BV_LRADC_CTRL0_YPLUS_ENABLE__##e)
+#define BFM_LRADC_CTRL0_YPLUS_ENABLE_V(v)           BM_LRADC_CTRL0_YPLUS_ENABLE
+#define BP_LRADC_CTRL0_XPLUS_ENABLE                 16
+#define BM_LRADC_CTRL0_XPLUS_ENABLE                 0x10000
+#define BV_LRADC_CTRL0_XPLUS_ENABLE__OFF            0x0
+#define BV_LRADC_CTRL0_XPLUS_ENABLE__ON             0x1
+#define BF_LRADC_CTRL0_XPLUS_ENABLE(v)              (((v) & 0x1) << 16)
+#define BFM_LRADC_CTRL0_XPLUS_ENABLE(v)             BM_LRADC_CTRL0_XPLUS_ENABLE
+#define BF_LRADC_CTRL0_XPLUS_ENABLE_V(e)            BF_LRADC_CTRL0_XPLUS_ENABLE(BV_LRADC_CTRL0_XPLUS_ENABLE__##e)
+#define BFM_LRADC_CTRL0_XPLUS_ENABLE_V(v)           BM_LRADC_CTRL0_XPLUS_ENABLE
+#define BP_LRADC_CTRL0_SCHEDULE                     0
+#define BM_LRADC_CTRL0_SCHEDULE                     0xff
+#define BF_LRADC_CTRL0_SCHEDULE(v)                  (((v) & 0xff) << 0)
+#define BFM_LRADC_CTRL0_SCHEDULE(v)                 BM_LRADC_CTRL0_SCHEDULE
+#define BF_LRADC_CTRL0_SCHEDULE_V(e)                BF_LRADC_CTRL0_SCHEDULE(BV_LRADC_CTRL0_SCHEDULE__##e)
+#define BFM_LRADC_CTRL0_SCHEDULE_V(v)               BM_LRADC_CTRL0_SCHEDULE
+
+#define HW_LRADC_CTRL1                              HW(LRADC_CTRL1)
+#define HWA_LRADC_CTRL1                             (0x80050000 + 0x10)
+#define HWT_LRADC_CTRL1                             HWIO_32_RW
+#define HWN_LRADC_CTRL1                             LRADC_CTRL1
+#define HWI_LRADC_CTRL1                             
+#define HW_LRADC_CTRL1_SET                          HW(LRADC_CTRL1_SET)
+#define HWA_LRADC_CTRL1_SET                         (HWA_LRADC_CTRL1 + 0x4)
+#define HWT_LRADC_CTRL1_SET                         HWIO_32_WO
+#define HWN_LRADC_CTRL1_SET                         LRADC_CTRL1
+#define HWI_LRADC_CTRL1_SET                         
+#define HW_LRADC_CTRL1_CLR                          HW(LRADC_CTRL1_CLR)
+#define HWA_LRADC_CTRL1_CLR                         (HWA_LRADC_CTRL1 + 0x8)
+#define HWT_LRADC_CTRL1_CLR                         HWIO_32_WO
+#define HWN_LRADC_CTRL1_CLR                         LRADC_CTRL1
+#define HWI_LRADC_CTRL1_CLR                         
+#define HW_LRADC_CTRL1_TOG                          HW(LRADC_CTRL1_TOG)
+#define HWA_LRADC_CTRL1_TOG                         (HWA_LRADC_CTRL1 + 0xc)
+#define HWT_LRADC_CTRL1_TOG                         HWIO_32_WO
+#define HWN_LRADC_CTRL1_TOG                         LRADC_CTRL1
+#define HWI_LRADC_CTRL1_TOG                         
+#define BP_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN          24
+#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN          0x1000000
+#define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN__DISABLE 0x0
+#define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN__ENABLE  0x1
+#define BF_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN(v)       (((v) & 0x1) << 24)
+#define BFM_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN(v)      BM_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN
+#define BF_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN_V(e)     BF_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN(BV_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN__##e)
+#define BFM_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN_V(v)    BM_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN
+#define BP_LRADC_CTRL1_LRADC7_IRQ_EN                23
+#define BM_LRADC_CTRL1_LRADC7_IRQ_EN                0x800000
+#define BV_LRADC_CTRL1_LRADC7_IRQ_EN__DISABLE       0x0
+#define BV_LRADC_CTRL1_LRADC7_IRQ_EN__ENABLE        0x1
+#define BF_LRADC_CTRL1_LRADC7_IRQ_EN(v)             (((v) & 0x1) << 23)
+#define BFM_LRADC_CTRL1_LRADC7_IRQ_EN(v)            BM_LRADC_CTRL1_LRADC7_IRQ_EN
+#define BF_LRADC_CTRL1_LRADC7_IRQ_EN_V(e)           BF_LRADC_CTRL1_LRADC7_IRQ_EN(BV_LRADC_CTRL1_LRADC7_IRQ_EN__##e)
+#define BFM_LRADC_CTRL1_LRADC7_IRQ_EN_V(v)          BM_LRADC_CTRL1_LRADC7_IRQ_EN
+#define BP_LRADC_CTRL1_LRADC6_IRQ_EN                22
+#define BM_LRADC_CTRL1_LRADC6_IRQ_EN                0x400000
+#define BV_LRADC_CTRL1_LRADC6_IRQ_EN__DISABLE       0x0
+#define BV_LRADC_CTRL1_LRADC6_IRQ_EN__ENABLE        0x1
+#define BF_LRADC_CTRL1_LRADC6_IRQ_EN(v)             (((v) & 0x1) << 22)
+#define BFM_LRADC_CTRL1_LRADC6_IRQ_EN(v)            BM_LRADC_CTRL1_LRADC6_IRQ_EN
+#define BF_LRADC_CTRL1_LRADC6_IRQ_EN_V(e)           BF_LRADC_CTRL1_LRADC6_IRQ_EN(BV_LRADC_CTRL1_LRADC6_IRQ_EN__##e)
+#define BFM_LRADC_CTRL1_LRADC6_IRQ_EN_V(v)          BM_LRADC_CTRL1_LRADC6_IRQ_EN
+#define BP_LRADC_CTRL1_LRADC5_IRQ_EN                21
+#define BM_LRADC_CTRL1_LRADC5_IRQ_EN                0x200000
+#define BV_LRADC_CTRL1_LRADC5_IRQ_EN__DISABLE       0x0
+#define BV_LRADC_CTRL1_LRADC5_IRQ_EN__ENABLE        0x1
+#define BF_LRADC_CTRL1_LRADC5_IRQ_EN(v)             (((v) & 0x1) << 21)
+#define BFM_LRADC_CTRL1_LRADC5_IRQ_EN(v)            BM_LRADC_CTRL1_LRADC5_IRQ_EN
+#define BF_LRADC_CTRL1_LRADC5_IRQ_EN_V(e)           BF_LRADC_CTRL1_LRADC5_IRQ_EN(BV_LRADC_CTRL1_LRADC5_IRQ_EN__##e)
+#define BFM_LRADC_CTRL1_LRADC5_IRQ_EN_V(v)          BM_LRADC_CTRL1_LRADC5_IRQ_EN
+#define BP_LRADC_CTRL1_LRADC4_IRQ_EN                20
+#define BM_LRADC_CTRL1_LRADC4_IRQ_EN                0x100000
+#define BV_LRADC_CTRL1_LRADC4_IRQ_EN__DISABLE       0x0
+#define BV_LRADC_CTRL1_LRADC4_IRQ_EN__ENABLE        0x1
+#define BF_LRADC_CTRL1_LRADC4_IRQ_EN(v)             (((v) & 0x1) << 20)
+#define BFM_LRADC_CTRL1_LRADC4_IRQ_EN(v)            BM_LRADC_CTRL1_LRADC4_IRQ_EN
+#define BF_LRADC_CTRL1_LRADC4_IRQ_EN_V(e)           BF_LRADC_CTRL1_LRADC4_IRQ_EN(BV_LRADC_CTRL1_LRADC4_IRQ_EN__##e)
+#define BFM_LRADC_CTRL1_LRADC4_IRQ_EN_V(v)          BM_LRADC_CTRL1_LRADC4_IRQ_EN
+#define BP_LRADC_CTRL1_LRADC3_IRQ_EN                19
+#define BM_LRADC_CTRL1_LRADC3_IRQ_EN                0x80000
+#define BV_LRADC_CTRL1_LRADC3_IRQ_EN__DISABLE       0x0
+#define BV_LRADC_CTRL1_LRADC3_IRQ_EN__ENABLE        0x1
+#define BF_LRADC_CTRL1_LRADC3_IRQ_EN(v)             (((v) & 0x1) << 19)
+#define BFM_LRADC_CTRL1_LRADC3_IRQ_EN(v)            BM_LRADC_CTRL1_LRADC3_IRQ_EN
+#define BF_LRADC_CTRL1_LRADC3_IRQ_EN_V(e)           BF_LRADC_CTRL1_LRADC3_IRQ_EN(BV_LRADC_CTRL1_LRADC3_IRQ_EN__##e)
+#define BFM_LRADC_CTRL1_LRADC3_IRQ_EN_V(v)          BM_LRADC_CTRL1_LRADC3_IRQ_EN
+#define BP_LRADC_CTRL1_LRADC2_IRQ_EN                18
+#define BM_LRADC_CTRL1_LRADC2_IRQ_EN                0x40000
+#define BV_LRADC_CTRL1_LRADC2_IRQ_EN__DISABLE       0x0
+#define BV_LRADC_CTRL1_LRADC2_IRQ_EN__ENABLE        0x1
+#define BF_LRADC_CTRL1_LRADC2_IRQ_EN(v)             (((v) & 0x1) << 18)
+#define BFM_LRADC_CTRL1_LRADC2_IRQ_EN(v)            BM_LRADC_CTRL1_LRADC2_IRQ_EN
+#define BF_LRADC_CTRL1_LRADC2_IRQ_EN_V(e)           BF_LRADC_CTRL1_LRADC2_IRQ_EN(BV_LRADC_CTRL1_LRADC2_IRQ_EN__##e)
+#define BFM_LRADC_CTRL1_LRADC2_IRQ_EN_V(v)          BM_LRADC_CTRL1_LRADC2_IRQ_EN
+#define BP_LRADC_CTRL1_LRADC1_IRQ_EN                17
+#define BM_LRADC_CTRL1_LRADC1_IRQ_EN                0x20000
+#define BV_LRADC_CTRL1_LRADC1_IRQ_EN__DISABLE       0x0
+#define BV_LRADC_CTRL1_LRADC1_IRQ_EN__ENABLE        0x1
+#define BF_LRADC_CTRL1_LRADC1_IRQ_EN(v)             (((v) & 0x1) << 17)
+#define BFM_LRADC_CTRL1_LRADC1_IRQ_EN(v)            BM_LRADC_CTRL1_LRADC1_IRQ_EN
+#define BF_LRADC_CTRL1_LRADC1_IRQ_EN_V(e)           BF_LRADC_CTRL1_LRADC1_IRQ_EN(BV_LRADC_CTRL1_LRADC1_IRQ_EN__##e)
+#define BFM_LRADC_CTRL1_LRADC1_IRQ_EN_V(v)          BM_LRADC_CTRL1_LRADC1_IRQ_EN
+#define BP_LRADC_CTRL1_LRADC0_IRQ_EN                16
+#define BM_LRADC_CTRL1_LRADC0_IRQ_EN                0x10000
+#define BV_LRADC_CTRL1_LRADC0_IRQ_EN__DISABLE       0x0
+#define BV_LRADC_CTRL1_LRADC0_IRQ_EN__ENABLE        0x1
+#define BF_LRADC_CTRL1_LRADC0_IRQ_EN(v)             (((v) & 0x1) << 16)
+#define BFM_LRADC_CTRL1_LRADC0_IRQ_EN(v)            BM_LRADC_CTRL1_LRADC0_IRQ_EN
+#define BF_LRADC_CTRL1_LRADC0_IRQ_EN_V(e)           BF_LRADC_CTRL1_LRADC0_IRQ_EN(BV_LRADC_CTRL1_LRADC0_IRQ_EN__##e)
+#define BFM_LRADC_CTRL1_LRADC0_IRQ_EN_V(v)          BM_LRADC_CTRL1_LRADC0_IRQ_EN
+#define BP_LRADC_CTRL1_TOUCH_DETECT_IRQ             8
+#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ             0x100
+#define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ__CLEAR      0x0
+#define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ__PENDING    0x1
+#define BF_LRADC_CTRL1_TOUCH_DETECT_IRQ(v)          (((v) & 0x1) << 8)
+#define BFM_LRADC_CTRL1_TOUCH_DETECT_IRQ(v)         BM_LRADC_CTRL1_TOUCH_DETECT_IRQ
+#define BF_LRADC_CTRL1_TOUCH_DETECT_IRQ_V(e)        BF_LRADC_CTRL1_TOUCH_DETECT_IRQ(BV_LRADC_CTRL1_TOUCH_DETECT_IRQ__##e)
+#define BFM_LRADC_CTRL1_TOUCH_DETECT_IRQ_V(v)       BM_LRADC_CTRL1_TOUCH_DETECT_IRQ
+#define BP_LRADC_CTRL1_LRADC7_IRQ                   7
+#define BM_LRADC_CTRL1_LRADC7_IRQ                   0x80
+#define BV_LRADC_CTRL1_LRADC7_IRQ__CLEAR            0x0
+#define BV_LRADC_CTRL1_LRADC7_IRQ__PENDING          0x1
+#define BF_LRADC_CTRL1_LRADC7_IRQ(v)                (((v) & 0x1) << 7)
+#define BFM_LRADC_CTRL1_LRADC7_IRQ(v)               BM_LRADC_CTRL1_LRADC7_IRQ
+#define BF_LRADC_CTRL1_LRADC7_IRQ_V(e)              BF_LRADC_CTRL1_LRADC7_IRQ(BV_LRADC_CTRL1_LRADC7_IRQ__##e)
+#define BFM_LRADC_CTRL1_LRADC7_IRQ_V(v)             BM_LRADC_CTRL1_LRADC7_IRQ
+#define BP_LRADC_CTRL1_LRADC6_IRQ                   6
+#define BM_LRADC_CTRL1_LRADC6_IRQ                   0x40
+#define BV_LRADC_CTRL1_LRADC6_IRQ__CLEAR            0x0
+#define BV_LRADC_CTRL1_LRADC6_IRQ__PENDING          0x1
+#define BF_LRADC_CTRL1_LRADC6_IRQ(v)                (((v) & 0x1) << 6)
+#define BFM_LRADC_CTRL1_LRADC6_IRQ(v)               BM_LRADC_CTRL1_LRADC6_IRQ
+#define BF_LRADC_CTRL1_LRADC6_IRQ_V(e)              BF_LRADC_CTRL1_LRADC6_IRQ(BV_LRADC_CTRL1_LRADC6_IRQ__##e)
+#define BFM_LRADC_CTRL1_LRADC6_IRQ_V(v)             BM_LRADC_CTRL1_LRADC6_IRQ
+#define BP_LRADC_CTRL1_LRADC5_IRQ                   5
+#define BM_LRADC_CTRL1_LRADC5_IRQ                   0x20
+#define BV_LRADC_CTRL1_LRADC5_IRQ__CLEAR            0x0
+#define BV_LRADC_CTRL1_LRADC5_IRQ__PENDING          0x1
+#define BF_LRADC_CTRL1_LRADC5_IRQ(v)                (((v) & 0x1) << 5)
+#define BFM_LRADC_CTRL1_LRADC5_IRQ(v)               BM_LRADC_CTRL1_LRADC5_IRQ
+#define BF_LRADC_CTRL1_LRADC5_IRQ_V(e)              BF_LRADC_CTRL1_LRADC5_IRQ(BV_LRADC_CTRL1_LRADC5_IRQ__##e)
+#define BFM_LRADC_CTRL1_LRADC5_IRQ_V(v)             BM_LRADC_CTRL1_LRADC5_IRQ
+#define BP_LRADC_CTRL1_LRADC4_IRQ                   4
+#define BM_LRADC_CTRL1_LRADC4_IRQ                   0x10
+#define BV_LRADC_CTRL1_LRADC4_IRQ__CLEAR            0x0
+#define BV_LRADC_CTRL1_LRADC4_IRQ__PENDING          0x1
+#define BF_LRADC_CTRL1_LRADC4_IRQ(v)                (((v) & 0x1) << 4)
+#define BFM_LRADC_CTRL1_LRADC4_IRQ(v)               BM_LRADC_CTRL1_LRADC4_IRQ
+#define BF_LRADC_CTRL1_LRADC4_IRQ_V(e)              BF_LRADC_CTRL1_LRADC4_IRQ(BV_LRADC_CTRL1_LRADC4_IRQ__##e)
+#define BFM_LRADC_CTRL1_LRADC4_IRQ_V(v)             BM_LRADC_CTRL1_LRADC4_IRQ
+#define BP_LRADC_CTRL1_LRADC3_IRQ                   3
+#define BM_LRADC_CTRL1_LRADC3_IRQ                   0x8
+#define BV_LRADC_CTRL1_LRADC3_IRQ__CLEAR            0x0
+#define BV_LRADC_CTRL1_LRADC3_IRQ__PENDING          0x1
+#define BF_LRADC_CTRL1_LRADC3_IRQ(v)                (((v) & 0x1) << 3)
+#define BFM_LRADC_CTRL1_LRADC3_IRQ(v)               BM_LRADC_CTRL1_LRADC3_IRQ
+#define BF_LRADC_CTRL1_LRADC3_IRQ_V(e)              BF_LRADC_CTRL1_LRADC3_IRQ(BV_LRADC_CTRL1_LRADC3_IRQ__##e)
+#define BFM_LRADC_CTRL1_LRADC3_IRQ_V(v)             BM_LRADC_CTRL1_LRADC3_IRQ
+#define BP_LRADC_CTRL1_LRADC2_IRQ                   2
+#define BM_LRADC_CTRL1_LRADC2_IRQ                   0x4
+#define BV_LRADC_CTRL1_LRADC2_IRQ__CLEAR            0x0
+#define BV_LRADC_CTRL1_LRADC2_IRQ__PENDING          0x1
+#define BF_LRADC_CTRL1_LRADC2_IRQ(v)                (((v) & 0x1) << 2)
+#define BFM_LRADC_CTRL1_LRADC2_IRQ(v)               BM_LRADC_CTRL1_LRADC2_IRQ
+#define BF_LRADC_CTRL1_LRADC2_IRQ_V(e)              BF_LRADC_CTRL1_LRADC2_IRQ(BV_LRADC_CTRL1_LRADC2_IRQ__##e)
+#define BFM_LRADC_CTRL1_LRADC2_IRQ_V(v)             BM_LRADC_CTRL1_LRADC2_IRQ
+#define BP_LRADC_CTRL1_LRADC1_IRQ                   1
+#define BM_LRADC_CTRL1_LRADC1_IRQ                   0x2
+#define BV_LRADC_CTRL1_LRADC1_IRQ__CLEAR            0x0
+#define BV_LRADC_CTRL1_LRADC1_IRQ__PENDING          0x1
+#define BF_LRADC_CTRL1_LRADC1_IRQ(v)                (((v) & 0x1) << 1)
+#define BFM_LRADC_CTRL1_LRADC1_IRQ(v)               BM_LRADC_CTRL1_LRADC1_IRQ
+#define BF_LRADC_CTRL1_LRADC1_IRQ_V(e)              BF_LRADC_CTRL1_LRADC1_IRQ(BV_LRADC_CTRL1_LRADC1_IRQ__##e)
+#define BFM_LRADC_CTRL1_LRADC1_IRQ_V(v)             BM_LRADC_CTRL1_LRADC1_IRQ
+#define BP_LRADC_CTRL1_LRADC0_IRQ                   0
+#define BM_LRADC_CTRL1_LRADC0_IRQ                   0x1
+#define BV_LRADC_CTRL1_LRADC0_IRQ__CLEAR            0x0
+#define BV_LRADC_CTRL1_LRADC0_IRQ__PENDING          0x1
+#define BF_LRADC_CTRL1_LRADC0_IRQ(v)                (((v) & 0x1) << 0)
+#define BFM_LRADC_CTRL1_LRADC0_IRQ(v)               BM_LRADC_CTRL1_LRADC0_IRQ
+#define BF_LRADC_CTRL1_LRADC0_IRQ_V(e)              BF_LRADC_CTRL1_LRADC0_IRQ(BV_LRADC_CTRL1_LRADC0_IRQ__##e)
+#define BFM_LRADC_CTRL1_LRADC0_IRQ_V(v)             BM_LRADC_CTRL1_LRADC0_IRQ
+
+#define HW_LRADC_CTRL2                                  HW(LRADC_CTRL2)
+#define HWA_LRADC_CTRL2                                 (0x80050000 + 0x20)
+#define HWT_LRADC_CTRL2                                 HWIO_32_RW
+#define HWN_LRADC_CTRL2                                 LRADC_CTRL2
+#define HWI_LRADC_CTRL2                                 
+#define HW_LRADC_CTRL2_SET                              HW(LRADC_CTRL2_SET)
+#define HWA_LRADC_CTRL2_SET                             (HWA_LRADC_CTRL2 + 0x4)
+#define HWT_LRADC_CTRL2_SET                             HWIO_32_WO
+#define HWN_LRADC_CTRL2_SET                             LRADC_CTRL2
+#define HWI_LRADC_CTRL2_SET                             
+#define HW_LRADC_CTRL2_CLR                              HW(LRADC_CTRL2_CLR)
+#define HWA_LRADC_CTRL2_CLR                             (HWA_LRADC_CTRL2 + 0x8)
+#define HWT_LRADC_CTRL2_CLR                             HWIO_32_WO
+#define HWN_LRADC_CTRL2_CLR                             LRADC_CTRL2
+#define HWI_LRADC_CTRL2_CLR                             
+#define HW_LRADC_CTRL2_TOG                              HW(LRADC_CTRL2_TOG)
+#define HWA_LRADC_CTRL2_TOG                             (HWA_LRADC_CTRL2 + 0xc)
+#define HWT_LRADC_CTRL2_TOG                             HWIO_32_WO
+#define HWN_LRADC_CTRL2_TOG                             LRADC_CTRL2
+#define HWI_LRADC_CTRL2_TOG                             
+#define BP_LRADC_CTRL2_DIVIDE_BY_TWO                    24
+#define BM_LRADC_CTRL2_DIVIDE_BY_TWO                    0xff000000
+#define BF_LRADC_CTRL2_DIVIDE_BY_TWO(v)                 (((v) & 0xff) << 24)
+#define BFM_LRADC_CTRL2_DIVIDE_BY_TWO(v)                BM_LRADC_CTRL2_DIVIDE_BY_TWO
+#define BF_LRADC_CTRL2_DIVIDE_BY_TWO_V(e)               BF_LRADC_CTRL2_DIVIDE_BY_TWO(BV_LRADC_CTRL2_DIVIDE_BY_TWO__##e)
+#define BFM_LRADC_CTRL2_DIVIDE_BY_TWO_V(v)              BM_LRADC_CTRL2_DIVIDE_BY_TWO
+#define BP_LRADC_CTRL2_LRADC6SELECT                     20
+#define BM_LRADC_CTRL2_LRADC6SELECT                     0xf00000
+#define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL0           0x0
+#define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL1           0x1
+#define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL2           0x2
+#define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL3           0x3
+#define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL4           0x4
+#define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL5           0x5
+#define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL6           0x6
+#define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL7           0x7
+#define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL8           0x8
+#define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL9           0x9
+#define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL10          0xa
+#define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL11          0xb
+#define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL12          0xc
+#define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL13          0xd
+#define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL14          0xe
+#define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL15          0xf
+#define BF_LRADC_CTRL2_LRADC6SELECT(v)                  (((v) & 0xf) << 20)
+#define BFM_LRADC_CTRL2_LRADC6SELECT(v)                 BM_LRADC_CTRL2_LRADC6SELECT
+#define BF_LRADC_CTRL2_LRADC6SELECT_V(e)                BF_LRADC_CTRL2_LRADC6SELECT(BV_LRADC_CTRL2_LRADC6SELECT__##e)
+#define BFM_LRADC_CTRL2_LRADC6SELECT_V(v)               BM_LRADC_CTRL2_LRADC6SELECT
+#define BP_LRADC_CTRL2_LRADC7SELECT                     16
+#define BM_LRADC_CTRL2_LRADC7SELECT                     0xf0000
+#define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL0           0x0
+#define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL1           0x1
+#define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL2           0x2
+#define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL3           0x3
+#define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL4           0x4
+#define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL5           0x5
+#define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL6           0x6
+#define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL7           0x7
+#define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL8           0x8
+#define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL9           0x9
+#define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL10          0xa
+#define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL11          0xb
+#define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL12          0xc
+#define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL13          0xd
+#define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL14          0xe
+#define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL15          0xf
+#define BF_LRADC_CTRL2_LRADC7SELECT(v)                  (((v) & 0xf) << 16)
+#define BFM_LRADC_CTRL2_LRADC7SELECT(v)                 BM_LRADC_CTRL2_LRADC7SELECT
+#define BF_LRADC_CTRL2_LRADC7SELECT_V(e)                BF_LRADC_CTRL2_LRADC7SELECT(BV_LRADC_CTRL2_LRADC7SELECT__##e)
+#define BFM_LRADC_CTRL2_LRADC7SELECT_V(v)               BM_LRADC_CTRL2_LRADC7SELECT
+#define BP_LRADC_CTRL2_TEMP_SENSOR_IENABLE1             9
+#define BM_LRADC_CTRL2_TEMP_SENSOR_IENABLE1             0x200
+#define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE1__DISABLE    0x0
+#define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE1__ENABLE     0x1
+#define BF_LRADC_CTRL2_TEMP_SENSOR_IENABLE1(v)          (((v) & 0x1) << 9)
+#define BFM_LRADC_CTRL2_TEMP_SENSOR_IENABLE1(v)         BM_LRADC_CTRL2_TEMP_SENSOR_IENABLE1
+#define BF_LRADC_CTRL2_TEMP_SENSOR_IENABLE1_V(e)        BF_LRADC_CTRL2_TEMP_SENSOR_IENABLE1(BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE1__##e)
+#define BFM_LRADC_CTRL2_TEMP_SENSOR_IENABLE1_V(v)       BM_LRADC_CTRL2_TEMP_SENSOR_IENABLE1
+#define BP_LRADC_CTRL2_TEMP_SENSOR_IENABLE0             8
+#define BM_LRADC_CTRL2_TEMP_SENSOR_IENABLE0             0x100
+#define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE0__DISABLE    0x0
+#define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE0__ENABLE     0x1
+#define BF_LRADC_CTRL2_TEMP_SENSOR_IENABLE0(v)          (((v) & 0x1) << 8)
+#define BFM_LRADC_CTRL2_TEMP_SENSOR_IENABLE0(v)         BM_LRADC_CTRL2_TEMP_SENSOR_IENABLE0
+#define BF_LRADC_CTRL2_TEMP_SENSOR_IENABLE0_V(e)        BF_LRADC_CTRL2_TEMP_SENSOR_IENABLE0(BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE0__##e)
+#define BFM_LRADC_CTRL2_TEMP_SENSOR_IENABLE0_V(v)       BM_LRADC_CTRL2_TEMP_SENSOR_IENABLE0
+#define BP_LRADC_CTRL2_TEMP_ISRC1                       4
+#define BM_LRADC_CTRL2_TEMP_ISRC1                       0xf0
+#define BV_LRADC_CTRL2_TEMP_ISRC1__300                  0xf
+#define BV_LRADC_CTRL2_TEMP_ISRC1__280                  0xe
+#define BV_LRADC_CTRL2_TEMP_ISRC1__260                  0xd
+#define BV_LRADC_CTRL2_TEMP_ISRC1__240                  0xc
+#define BV_LRADC_CTRL2_TEMP_ISRC1__220                  0xb
+#define BV_LRADC_CTRL2_TEMP_ISRC1__200                  0xa
+#define BV_LRADC_CTRL2_TEMP_ISRC1__180                  0x9
+#define BV_LRADC_CTRL2_TEMP_ISRC1__160                  0x8
+#define BV_LRADC_CTRL2_TEMP_ISRC1__140                  0x7
+#define BV_LRADC_CTRL2_TEMP_ISRC1__120                  0x6
+#define BV_LRADC_CTRL2_TEMP_ISRC1__100                  0x5
+#define BV_LRADC_CTRL2_TEMP_ISRC1__80                   0x4
+#define BV_LRADC_CTRL2_TEMP_ISRC1__60                   0x3
+#define BV_LRADC_CTRL2_TEMP_ISRC1__40                   0x2
+#define BV_LRADC_CTRL2_TEMP_ISRC1__20                   0x1
+#define BV_LRADC_CTRL2_TEMP_ISRC1__ZERO                 0x0
+#define BF_LRADC_CTRL2_TEMP_ISRC1(v)                    (((v) & 0xf) << 4)
+#define BFM_LRADC_CTRL2_TEMP_ISRC1(v)                   BM_LRADC_CTRL2_TEMP_ISRC1
+#define BF_LRADC_CTRL2_TEMP_ISRC1_V(e)                  BF_LRADC_CTRL2_TEMP_ISRC1(BV_LRADC_CTRL2_TEMP_ISRC1__##e)
+#define BFM_LRADC_CTRL2_TEMP_ISRC1_V(v)                 BM_LRADC_CTRL2_TEMP_ISRC1
+#define BP_LRADC_CTRL2_TEMP_ISRC0                       0
+#define BM_LRADC_CTRL2_TEMP_ISRC0                       0xf
+#define BV_LRADC_CTRL2_TEMP_ISRC0__300                  0xf
+#define BV_LRADC_CTRL2_TEMP_ISRC0__280                  0xe
+#define BV_LRADC_CTRL2_TEMP_ISRC0__260                  0xd
+#define BV_LRADC_CTRL2_TEMP_ISRC0__240                  0xc
+#define BV_LRADC_CTRL2_TEMP_ISRC0__220                  0xb
+#define BV_LRADC_CTRL2_TEMP_ISRC0__200                  0xa
+#define BV_LRADC_CTRL2_TEMP_ISRC0__180                  0x9
+#define BV_LRADC_CTRL2_TEMP_ISRC0__160                  0x8
+#define BV_LRADC_CTRL2_TEMP_ISRC0__140                  0x7
+#define BV_LRADC_CTRL2_TEMP_ISRC0__120                  0x6
+#define BV_LRADC_CTRL2_TEMP_ISRC0__100                  0x5
+#define BV_LRADC_CTRL2_TEMP_ISRC0__80                   0x4
+#define BV_LRADC_CTRL2_TEMP_ISRC0__60                   0x3
+#define BV_LRADC_CTRL2_TEMP_ISRC0__40                   0x2
+#define BV_LRADC_CTRL2_TEMP_ISRC0__20                   0x1
+#define BV_LRADC_CTRL2_TEMP_ISRC0__ZERO                 0x0
+#define BF_LRADC_CTRL2_TEMP_ISRC0(v)                    (((v) & 0xf) << 0)
+#define BFM_LRADC_CTRL2_TEMP_ISRC0(v)                   BM_LRADC_CTRL2_TEMP_ISRC0
+#define BF_LRADC_CTRL2_TEMP_ISRC0_V(e)                  BF_LRADC_CTRL2_TEMP_ISRC0(BV_LRADC_CTRL2_TEMP_ISRC0__##e)
+#define BFM_LRADC_CTRL2_TEMP_ISRC0_V(v)                 BM_LRADC_CTRL2_TEMP_ISRC0
+
+#define HW_LRADC_CTRL3                          HW(LRADC_CTRL3)
+#define HWA_LRADC_CTRL3                         (0x80050000 + 0x30)
+#define HWT_LRADC_CTRL3                         HWIO_32_RW
+#define HWN_LRADC_CTRL3                         LRADC_CTRL3
+#define HWI_LRADC_CTRL3                         
+#define HW_LRADC_CTRL3_SET                      HW(LRADC_CTRL3_SET)
+#define HWA_LRADC_CTRL3_SET                     (HWA_LRADC_CTRL3 + 0x4)
+#define HWT_LRADC_CTRL3_SET                     HWIO_32_WO
+#define HWN_LRADC_CTRL3_SET                     LRADC_CTRL3
+#define HWI_LRADC_CTRL3_SET                     
+#define HW_LRADC_CTRL3_CLR                      HW(LRADC_CTRL3_CLR)
+#define HWA_LRADC_CTRL3_CLR                     (HWA_LRADC_CTRL3 + 0x8)
+#define HWT_LRADC_CTRL3_CLR                     HWIO_32_WO
+#define HWN_LRADC_CTRL3_CLR                     LRADC_CTRL3
+#define HWI_LRADC_CTRL3_CLR                     
+#define HW_LRADC_CTRL3_TOG                      HW(LRADC_CTRL3_TOG)
+#define HWA_LRADC_CTRL3_TOG                     (HWA_LRADC_CTRL3 + 0xc)
+#define HWT_LRADC_CTRL3_TOG                     HWIO_32_WO
+#define HWN_LRADC_CTRL3_TOG                     LRADC_CTRL3
+#define HWI_LRADC_CTRL3_TOG                     
+#define BP_LRADC_CTRL3_DISCARD                  24
+#define BM_LRADC_CTRL3_DISCARD                  0x3000000
+#define BV_LRADC_CTRL3_DISCARD__1_SAMPLE        0x1
+#define BV_LRADC_CTRL3_DISCARD__2_SAMPLES       0x2
+#define BV_LRADC_CTRL3_DISCARD__3_SAMPLES       0x3
+#define BF_LRADC_CTRL3_DISCARD(v)               (((v) & 0x3) << 24)
+#define BFM_LRADC_CTRL3_DISCARD(v)              BM_LRADC_CTRL3_DISCARD
+#define BF_LRADC_CTRL3_DISCARD_V(e)             BF_LRADC_CTRL3_DISCARD(BV_LRADC_CTRL3_DISCARD__##e)
+#define BFM_LRADC_CTRL3_DISCARD_V(v)            BM_LRADC_CTRL3_DISCARD
+#define BP_LRADC_CTRL3_FORCE_ANALOG_PWUP        23
+#define BM_LRADC_CTRL3_FORCE_ANALOG_PWUP        0x800000
+#define BV_LRADC_CTRL3_FORCE_ANALOG_PWUP__OFF   0x0
+#define BV_LRADC_CTRL3_FORCE_ANALOG_PWUP__ON    0x1
+#define BF_LRADC_CTRL3_FORCE_ANALOG_PWUP(v)     (((v) & 0x1) << 23)
+#define BFM_LRADC_CTRL3_FORCE_ANALOG_PWUP(v)    BM_LRADC_CTRL3_FORCE_ANALOG_PWUP
+#define BF_LRADC_CTRL3_FORCE_ANALOG_PWUP_V(e)   BF_LRADC_CTRL3_FORCE_ANALOG_PWUP(BV_LRADC_CTRL3_FORCE_ANALOG_PWUP__##e)
+#define BFM_LRADC_CTRL3_FORCE_ANALOG_PWUP_V(v)  BM_LRADC_CTRL3_FORCE_ANALOG_PWUP
+#define BP_LRADC_CTRL3_FORCE_ANALOG_PWDN        22
+#define BM_LRADC_CTRL3_FORCE_ANALOG_PWDN        0x400000
+#define BV_LRADC_CTRL3_FORCE_ANALOG_PWDN__ON    0x0
+#define BV_LRADC_CTRL3_FORCE_ANALOG_PWDN__OFF   0x1
+#define BF_LRADC_CTRL3_FORCE_ANALOG_PWDN(v)     (((v) & 0x1) << 22)
+#define BFM_LRADC_CTRL3_FORCE_ANALOG_PWDN(v)    BM_LRADC_CTRL3_FORCE_ANALOG_PWDN
+#define BF_LRADC_CTRL3_FORCE_ANALOG_PWDN_V(e)   BF_LRADC_CTRL3_FORCE_ANALOG_PWDN(BV_LRADC_CTRL3_FORCE_ANALOG_PWDN__##e)
+#define BFM_LRADC_CTRL3_FORCE_ANALOG_PWDN_V(v)  BM_LRADC_CTRL3_FORCE_ANALOG_PWDN
+#define BP_LRADC_CTRL3_FORCE_PWD40UA_PWUP       21
+#define BM_LRADC_CTRL3_FORCE_PWD40UA_PWUP       0x200000
+#define BV_LRADC_CTRL3_FORCE_PWD40UA_PWUP__OFF  0x0
+#define BV_LRADC_CTRL3_FORCE_PWD40UA_PWUP__ON   0x1
+#define BF_LRADC_CTRL3_FORCE_PWD40UA_PWUP(v)    (((v) & 0x1) << 21)
+#define BFM_LRADC_CTRL3_FORCE_PWD40UA_PWUP(v)   BM_LRADC_CTRL3_FORCE_PWD40UA_PWUP
+#define BF_LRADC_CTRL3_FORCE_PWD40UA_PWUP_V(e)  BF_LRADC_CTRL3_FORCE_PWD40UA_PWUP(BV_LRADC_CTRL3_FORCE_PWD40UA_PWUP__##e)
+#define BFM_LRADC_CTRL3_FORCE_PWD40UA_PWUP_V(v) BM_LRADC_CTRL3_FORCE_PWD40UA_PWUP
+#define BP_LRADC_CTRL3_FORCE_PWD40UA_PWDN       20
+#define BM_LRADC_CTRL3_FORCE_PWD40UA_PWDN       0x100000
+#define BV_LRADC_CTRL3_FORCE_PWD40UA_PWDN__ON   0x0
+#define BV_LRADC_CTRL3_FORCE_PWD40UA_PWDN__OFF  0x1
+#define BF_LRADC_CTRL3_FORCE_PWD40UA_PWDN(v)    (((v) & 0x1) << 20)
+#define BFM_LRADC_CTRL3_FORCE_PWD40UA_PWDN(v)   BM_LRADC_CTRL3_FORCE_PWD40UA_PWDN
+#define BF_LRADC_CTRL3_FORCE_PWD40UA_PWDN_V(e)  BF_LRADC_CTRL3_FORCE_PWD40UA_PWDN(BV_LRADC_CTRL3_FORCE_PWD40UA_PWDN__##e)
+#define BFM_LRADC_CTRL3_FORCE_PWD40UA_PWDN_V(v) BM_LRADC_CTRL3_FORCE_PWD40UA_PWDN
+#define BP_LRADC_CTRL3_VDD_FILTER               16
+#define BM_LRADC_CTRL3_VDD_FILTER               0x30000
+#define BV_LRADC_CTRL3_VDD_FILTER__0OHMS        0x0
+#define BV_LRADC_CTRL3_VDD_FILTER__100OHMS      0x1
+#define BV_LRADC_CTRL3_VDD_FILTER__250OHMS      0x2
+#define BV_LRADC_CTRL3_VDD_FILTER__5000OHMS     0x3
+#define BF_LRADC_CTRL3_VDD_FILTER(v)            (((v) & 0x3) << 16)
+#define BFM_LRADC_CTRL3_VDD_FILTER(v)           BM_LRADC_CTRL3_VDD_FILTER
+#define BF_LRADC_CTRL3_VDD_FILTER_V(e)          BF_LRADC_CTRL3_VDD_FILTER(BV_LRADC_CTRL3_VDD_FILTER__##e)
+#define BFM_LRADC_CTRL3_VDD_FILTER_V(v)         BM_LRADC_CTRL3_VDD_FILTER
+#define BP_LRADC_CTRL3_ADD_CAP2INPUTS           12
+#define BM_LRADC_CTRL3_ADD_CAP2INPUTS           0x3000
+#define BV_LRADC_CTRL3_ADD_CAP2INPUTS__0PF      0x0
+#define BV_LRADC_CTRL3_ADD_CAP2INPUTS__0_5PF    0x1
+#define BV_LRADC_CTRL3_ADD_CAP2INPUTS__1_0PF    0x2
+#define BV_LRADC_CTRL3_ADD_CAP2INPUTS__2_5PF    0x3
+#define BF_LRADC_CTRL3_ADD_CAP2INPUTS(v)        (((v) & 0x3) << 12)
+#define BFM_LRADC_CTRL3_ADD_CAP2INPUTS(v)       BM_LRADC_CTRL3_ADD_CAP2INPUTS
+#define BF_LRADC_CTRL3_ADD_CAP2INPUTS_V(e)      BF_LRADC_CTRL3_ADD_CAP2INPUTS(BV_LRADC_CTRL3_ADD_CAP2INPUTS__##e)
+#define BFM_LRADC_CTRL3_ADD_CAP2INPUTS_V(v)     BM_LRADC_CTRL3_ADD_CAP2INPUTS
+#define BP_LRADC_CTRL3_CYCLE_TIME               8
+#define BM_LRADC_CTRL3_CYCLE_TIME               0x300
+#define BV_LRADC_CTRL3_CYCLE_TIME__6MHZ         0x0
+#define BV_LRADC_CTRL3_CYCLE_TIME__4MHZ         0x1
+#define BV_LRADC_CTRL3_CYCLE_TIME__3MHZ         0x2
+#define BV_LRADC_CTRL3_CYCLE_TIME__2MHZ         0x3
+#define BF_LRADC_CTRL3_CYCLE_TIME(v)            (((v) & 0x3) << 8)
+#define BFM_LRADC_CTRL3_CYCLE_TIME(v)           BM_LRADC_CTRL3_CYCLE_TIME
+#define BF_LRADC_CTRL3_CYCLE_TIME_V(e)          BF_LRADC_CTRL3_CYCLE_TIME(BV_LRADC_CTRL3_CYCLE_TIME__##e)
+#define BFM_LRADC_CTRL3_CYCLE_TIME_V(v)         BM_LRADC_CTRL3_CYCLE_TIME
+#define BP_LRADC_CTRL3_HIGH_TIME                4
+#define BM_LRADC_CTRL3_HIGH_TIME                0x30
+#define BV_LRADC_CTRL3_HIGH_TIME__42NS          0x0
+#define BV_LRADC_CTRL3_HIGH_TIME__83NS          0x1
+#define BV_LRADC_CTRL3_HIGH_TIME__125NS         0x2
+#define BV_LRADC_CTRL3_HIGH_TIME__250NS         0x3
+#define BF_LRADC_CTRL3_HIGH_TIME(v)             (((v) & 0x3) << 4)
+#define BFM_LRADC_CTRL3_HIGH_TIME(v)            BM_LRADC_CTRL3_HIGH_TIME
+#define BF_LRADC_CTRL3_HIGH_TIME_V(e)           BF_LRADC_CTRL3_HIGH_TIME(BV_LRADC_CTRL3_HIGH_TIME__##e)
+#define BFM_LRADC_CTRL3_HIGH_TIME_V(v)          BM_LRADC_CTRL3_HIGH_TIME
+#define BP_LRADC_CTRL3_REMOVE_CFILT             3
+#define BM_LRADC_CTRL3_REMOVE_CFILT             0x8
+#define BV_LRADC_CTRL3_REMOVE_CFILT__OFF        0x0
+#define BV_LRADC_CTRL3_REMOVE_CFILT__ON         0x1
+#define BF_LRADC_CTRL3_REMOVE_CFILT(v)          (((v) & 0x1) << 3)
+#define BFM_LRADC_CTRL3_REMOVE_CFILT(v)         BM_LRADC_CTRL3_REMOVE_CFILT
+#define BF_LRADC_CTRL3_REMOVE_CFILT_V(e)        BF_LRADC_CTRL3_REMOVE_CFILT(BV_LRADC_CTRL3_REMOVE_CFILT__##e)
+#define BFM_LRADC_CTRL3_REMOVE_CFILT_V(v)       BM_LRADC_CTRL3_REMOVE_CFILT
+#define BP_LRADC_CTRL3_SHORT_RFILT              2
+#define BM_LRADC_CTRL3_SHORT_RFILT              0x4
+#define BV_LRADC_CTRL3_SHORT_RFILT__OFF         0x0
+#define BV_LRADC_CTRL3_SHORT_RFILT__ON          0x1
+#define BF_LRADC_CTRL3_SHORT_RFILT(v)           (((v) & 0x1) << 2)
+#define BFM_LRADC_CTRL3_SHORT_RFILT(v)          BM_LRADC_CTRL3_SHORT_RFILT
+#define BF_LRADC_CTRL3_SHORT_RFILT_V(e)         BF_LRADC_CTRL3_SHORT_RFILT(BV_LRADC_CTRL3_SHORT_RFILT__##e)
+#define BFM_LRADC_CTRL3_SHORT_RFILT_V(v)        BM_LRADC_CTRL3_SHORT_RFILT
+#define BP_LRADC_CTRL3_DELAY_CLOCK              1
+#define BM_LRADC_CTRL3_DELAY_CLOCK              0x2
+#define BV_LRADC_CTRL3_DELAY_CLOCK__NORMAL      0x0
+#define BV_LRADC_CTRL3_DELAY_CLOCK__DELAYED     0x1
+#define BF_LRADC_CTRL3_DELAY_CLOCK(v)           (((v) & 0x1) << 1)
+#define BFM_LRADC_CTRL3_DELAY_CLOCK(v)          BM_LRADC_CTRL3_DELAY_CLOCK
+#define BF_LRADC_CTRL3_DELAY_CLOCK_V(e)         BF_LRADC_CTRL3_DELAY_CLOCK(BV_LRADC_CTRL3_DELAY_CLOCK__##e)
+#define BFM_LRADC_CTRL3_DELAY_CLOCK_V(v)        BM_LRADC_CTRL3_DELAY_CLOCK
+#define BP_LRADC_CTRL3_INVERT_CLOCK             0
+#define BM_LRADC_CTRL3_INVERT_CLOCK             0x1
+#define BV_LRADC_CTRL3_INVERT_CLOCK__NORMAL     0x0
+#define BV_LRADC_CTRL3_INVERT_CLOCK__INVERT     0x1
+#define BF_LRADC_CTRL3_INVERT_CLOCK(v)          (((v) & 0x1) << 0)
+#define BFM_LRADC_CTRL3_INVERT_CLOCK(v)         BM_LRADC_CTRL3_INVERT_CLOCK
+#define BF_LRADC_CTRL3_INVERT_CLOCK_V(e)        BF_LRADC_CTRL3_INVERT_CLOCK(BV_LRADC_CTRL3_INVERT_CLOCK__##e)
+#define BFM_LRADC_CTRL3_INVERT_CLOCK_V(v)       BM_LRADC_CTRL3_INVERT_CLOCK
+
+#define HW_LRADC_STATUS                             HW(LRADC_STATUS)
+#define HWA_LRADC_STATUS                            (0x80050000 + 0x40)
+#define HWT_LRADC_STATUS                            HWIO_32_RW
+#define HWN_LRADC_STATUS                            LRADC_STATUS
+#define HWI_LRADC_STATUS                            
+#define BP_LRADC_STATUS_TEMP1_PRESENT               26
+#define BM_LRADC_STATUS_TEMP1_PRESENT               0x4000000
+#define BF_LRADC_STATUS_TEMP1_PRESENT(v)            (((v) & 0x1) << 26)
+#define BFM_LRADC_STATUS_TEMP1_PRESENT(v)           BM_LRADC_STATUS_TEMP1_PRESENT
+#define BF_LRADC_STATUS_TEMP1_PRESENT_V(e)          BF_LRADC_STATUS_TEMP1_PRESENT(BV_LRADC_STATUS_TEMP1_PRESENT__##e)
+#define BFM_LRADC_STATUS_TEMP1_PRESENT_V(v)         BM_LRADC_STATUS_TEMP1_PRESENT
+#define BP_LRADC_STATUS_TEMP0_PRESENT               25
+#define BM_LRADC_STATUS_TEMP0_PRESENT               0x2000000
+#define BF_LRADC_STATUS_TEMP0_PRESENT(v)            (((v) & 0x1) << 25)
+#define BFM_LRADC_STATUS_TEMP0_PRESENT(v)           BM_LRADC_STATUS_TEMP0_PRESENT
+#define BF_LRADC_STATUS_TEMP0_PRESENT_V(e)          BF_LRADC_STATUS_TEMP0_PRESENT(BV_LRADC_STATUS_TEMP0_PRESENT__##e)
+#define BFM_LRADC_STATUS_TEMP0_PRESENT_V(v)         BM_LRADC_STATUS_TEMP0_PRESENT
+#define BP_LRADC_STATUS_TOUCH_PANEL_PRESENT         24
+#define BM_LRADC_STATUS_TOUCH_PANEL_PRESENT         0x1000000
+#define BF_LRADC_STATUS_TOUCH_PANEL_PRESENT(v)      (((v) & 0x1) << 24)
+#define BFM_LRADC_STATUS_TOUCH_PANEL_PRESENT(v)     BM_LRADC_STATUS_TOUCH_PANEL_PRESENT
+#define BF_LRADC_STATUS_TOUCH_PANEL_PRESENT_V(e)    BF_LRADC_STATUS_TOUCH_PANEL_PRESENT(BV_LRADC_STATUS_TOUCH_PANEL_PRESENT__##e)
+#define BFM_LRADC_STATUS_TOUCH_PANEL_PRESENT_V(v)   BM_LRADC_STATUS_TOUCH_PANEL_PRESENT
+#define BP_LRADC_STATUS_CHANNEL7_PRESENT            23
+#define BM_LRADC_STATUS_CHANNEL7_PRESENT            0x800000
+#define BF_LRADC_STATUS_CHANNEL7_PRESENT(v)         (((v) & 0x1) << 23)
+#define BFM_LRADC_STATUS_CHANNEL7_PRESENT(v)        BM_LRADC_STATUS_CHANNEL7_PRESENT
+#define BF_LRADC_STATUS_CHANNEL7_PRESENT_V(e)       BF_LRADC_STATUS_CHANNEL7_PRESENT(BV_LRADC_STATUS_CHANNEL7_PRESENT__##e)
+#define BFM_LRADC_STATUS_CHANNEL7_PRESENT_V(v)      BM_LRADC_STATUS_CHANNEL7_PRESENT
+#define BP_LRADC_STATUS_CHANNEL6_PRESENT            22
+#define BM_LRADC_STATUS_CHANNEL6_PRESENT            0x400000
+#define BF_LRADC_STATUS_CHANNEL6_PRESENT(v)         (((v) & 0x1) << 22)
+#define BFM_LRADC_STATUS_CHANNEL6_PRESENT(v)        BM_LRADC_STATUS_CHANNEL6_PRESENT
+#define BF_LRADC_STATUS_CHANNEL6_PRESENT_V(e)       BF_LRADC_STATUS_CHANNEL6_PRESENT(BV_LRADC_STATUS_CHANNEL6_PRESENT__##e)
+#define BFM_LRADC_STATUS_CHANNEL6_PRESENT_V(v)      BM_LRADC_STATUS_CHANNEL6_PRESENT
+#define BP_LRADC_STATUS_CHANNEL5_PRESENT            21
+#define BM_LRADC_STATUS_CHANNEL5_PRESENT            0x200000
+#define BF_LRADC_STATUS_CHANNEL5_PRESENT(v)         (((v) & 0x1) << 21)
+#define BFM_LRADC_STATUS_CHANNEL5_PRESENT(v)        BM_LRADC_STATUS_CHANNEL5_PRESENT
+#define BF_LRADC_STATUS_CHANNEL5_PRESENT_V(e)       BF_LRADC_STATUS_CHANNEL5_PRESENT(BV_LRADC_STATUS_CHANNEL5_PRESENT__##e)
+#define BFM_LRADC_STATUS_CHANNEL5_PRESENT_V(v)      BM_LRADC_STATUS_CHANNEL5_PRESENT
+#define BP_LRADC_STATUS_CHANNEL4_PRESENT            20
+#define BM_LRADC_STATUS_CHANNEL4_PRESENT            0x100000
+#define BF_LRADC_STATUS_CHANNEL4_PRESENT(v)         (((v) & 0x1) << 20)
+#define BFM_LRADC_STATUS_CHANNEL4_PRESENT(v)        BM_LRADC_STATUS_CHANNEL4_PRESENT
+#define BF_LRADC_STATUS_CHANNEL4_PRESENT_V(e)       BF_LRADC_STATUS_CHANNEL4_PRESENT(BV_LRADC_STATUS_CHANNEL4_PRESENT__##e)
+#define BFM_LRADC_STATUS_CHANNEL4_PRESENT_V(v)      BM_LRADC_STATUS_CHANNEL4_PRESENT
+#define BP_LRADC_STATUS_CHANNEL3_PRESENT            19
+#define BM_LRADC_STATUS_CHANNEL3_PRESENT            0x80000
+#define BF_LRADC_STATUS_CHANNEL3_PRESENT(v)         (((v) & 0x1) << 19)
+#define BFM_LRADC_STATUS_CHANNEL3_PRESENT(v)        BM_LRADC_STATUS_CHANNEL3_PRESENT
+#define BF_LRADC_STATUS_CHANNEL3_PRESENT_V(e)       BF_LRADC_STATUS_CHANNEL3_PRESENT(BV_LRADC_STATUS_CHANNEL3_PRESENT__##e)
+#define BFM_LRADC_STATUS_CHANNEL3_PRESENT_V(v)      BM_LRADC_STATUS_CHANNEL3_PRESENT
+#define BP_LRADC_STATUS_CHANNEL2_PRESENT            18
+#define BM_LRADC_STATUS_CHANNEL2_PRESENT            0x40000
+#define BF_LRADC_STATUS_CHANNEL2_PRESENT(v)         (((v) & 0x1) << 18)
+#define BFM_LRADC_STATUS_CHANNEL2_PRESENT(v)        BM_LRADC_STATUS_CHANNEL2_PRESENT
+#define BF_LRADC_STATUS_CHANNEL2_PRESENT_V(e)       BF_LRADC_STATUS_CHANNEL2_PRESENT(BV_LRADC_STATUS_CHANNEL2_PRESENT__##e)
+#define BFM_LRADC_STATUS_CHANNEL2_PRESENT_V(v)      BM_LRADC_STATUS_CHANNEL2_PRESENT
+#define BP_LRADC_STATUS_CHANNEL1_PRESENT            17
+#define BM_LRADC_STATUS_CHANNEL1_PRESENT            0x20000
+#define BF_LRADC_STATUS_CHANNEL1_PRESENT(v)         (((v) & 0x1) << 17)
+#define BFM_LRADC_STATUS_CHANNEL1_PRESENT(v)        BM_LRADC_STATUS_CHANNEL1_PRESENT
+#define BF_LRADC_STATUS_CHANNEL1_PRESENT_V(e)       BF_LRADC_STATUS_CHANNEL1_PRESENT(BV_LRADC_STATUS_CHANNEL1_PRESENT__##e)
+#define BFM_LRADC_STATUS_CHANNEL1_PRESENT_V(v)      BM_LRADC_STATUS_CHANNEL1_PRESENT
+#define BP_LRADC_STATUS_CHANNEL0_PRESENT            16
+#define BM_LRADC_STATUS_CHANNEL0_PRESENT            0x10000
+#define BF_LRADC_STATUS_CHANNEL0_PRESENT(v)         (((v) & 0x1) << 16)
+#define BFM_LRADC_STATUS_CHANNEL0_PRESENT(v)        BM_LRADC_STATUS_CHANNEL0_PRESENT
+#define BF_LRADC_STATUS_CHANNEL0_PRESENT_V(e)       BF_LRADC_STATUS_CHANNEL0_PRESENT(BV_LRADC_STATUS_CHANNEL0_PRESENT__##e)
+#define BFM_LRADC_STATUS_CHANNEL0_PRESENT_V(v)      BM_LRADC_STATUS_CHANNEL0_PRESENT
+#define BP_LRADC_STATUS_TOUCH_DETECT_RAW            0
+#define BM_LRADC_STATUS_TOUCH_DETECT_RAW            0x1
+#define BV_LRADC_STATUS_TOUCH_DETECT_RAW__OPEN      0x0
+#define BV_LRADC_STATUS_TOUCH_DETECT_RAW__HIT       0x1
+#define BF_LRADC_STATUS_TOUCH_DETECT_RAW(v)         (((v) & 0x1) << 0)
+#define BFM_LRADC_STATUS_TOUCH_DETECT_RAW(v)        BM_LRADC_STATUS_TOUCH_DETECT_RAW
+#define BF_LRADC_STATUS_TOUCH_DETECT_RAW_V(e)       BF_LRADC_STATUS_TOUCH_DETECT_RAW(BV_LRADC_STATUS_TOUCH_DETECT_RAW__##e)
+#define BFM_LRADC_STATUS_TOUCH_DETECT_RAW_V(v)      BM_LRADC_STATUS_TOUCH_DETECT_RAW
+
+#define HW_LRADC_DEBUG0                 HW(LRADC_DEBUG0)
+#define HWA_LRADC_DEBUG0                (0x80050000 + 0x110)
+#define HWT_LRADC_DEBUG0                HWIO_32_RW
+#define HWN_LRADC_DEBUG0                LRADC_DEBUG0
+#define HWI_LRADC_DEBUG0                
+#define BP_LRADC_DEBUG0_READONLY        16
+#define BM_LRADC_DEBUG0_READONLY        0xffff0000
+#define BF_LRADC_DEBUG0_READONLY(v)     (((v) & 0xffff) << 16)
+#define BFM_LRADC_DEBUG0_READONLY(v)    BM_LRADC_DEBUG0_READONLY
+#define BF_LRADC_DEBUG0_READONLY_V(e)   BF_LRADC_DEBUG0_READONLY(BV_LRADC_DEBUG0_READONLY__##e)
+#define BFM_LRADC_DEBUG0_READONLY_V(v)  BM_LRADC_DEBUG0_READONLY
+#define BP_LRADC_DEBUG0_STATE           0
+#define BM_LRADC_DEBUG0_STATE           0xfff
+#define BF_LRADC_DEBUG0_STATE(v)        (((v) & 0xfff) << 0)
+#define BFM_LRADC_DEBUG0_STATE(v)       BM_LRADC_DEBUG0_STATE
+#define BF_LRADC_DEBUG0_STATE_V(e)      BF_LRADC_DEBUG0_STATE(BV_LRADC_DEBUG0_STATE__##e)
+#define BFM_LRADC_DEBUG0_STATE_V(v)     BM_LRADC_DEBUG0_STATE
+
+#define HW_LRADC_DEBUG1                         HW(LRADC_DEBUG1)
+#define HWA_LRADC_DEBUG1                        (0x80050000 + 0x120)
+#define HWT_LRADC_DEBUG1                        HWIO_32_RW
+#define HWN_LRADC_DEBUG1                        LRADC_DEBUG1
+#define HWI_LRADC_DEBUG1                        
+#define HW_LRADC_DEBUG1_SET                     HW(LRADC_DEBUG1_SET)
+#define HWA_LRADC_DEBUG1_SET                    (HWA_LRADC_DEBUG1 + 0x4)
+#define HWT_LRADC_DEBUG1_SET                    HWIO_32_WO
+#define HWN_LRADC_DEBUG1_SET                    LRADC_DEBUG1
+#define HWI_LRADC_DEBUG1_SET                    
+#define HW_LRADC_DEBUG1_CLR                     HW(LRADC_DEBUG1_CLR)
+#define HWA_LRADC_DEBUG1_CLR                    (HWA_LRADC_DEBUG1 + 0x8)
+#define HWT_LRADC_DEBUG1_CLR                    HWIO_32_WO
+#define HWN_LRADC_DEBUG1_CLR                    LRADC_DEBUG1
+#define HWI_LRADC_DEBUG1_CLR                    
+#define HW_LRADC_DEBUG1_TOG                     HW(LRADC_DEBUG1_TOG)
+#define HWA_LRADC_DEBUG1_TOG                    (HWA_LRADC_DEBUG1 + 0xc)
+#define HWT_LRADC_DEBUG1_TOG                    HWIO_32_WO
+#define HWN_LRADC_DEBUG1_TOG                    LRADC_DEBUG1
+#define HWI_LRADC_DEBUG1_TOG                    
+#define BP_LRADC_DEBUG1_REQUEST                 16
+#define BM_LRADC_DEBUG1_REQUEST                 0xff0000
+#define BF_LRADC_DEBUG1_REQUEST(v)              (((v) & 0xff) << 16)
+#define BFM_LRADC_DEBUG1_REQUEST(v)             BM_LRADC_DEBUG1_REQUEST
+#define BF_LRADC_DEBUG1_REQUEST_V(e)            BF_LRADC_DEBUG1_REQUEST(BV_LRADC_DEBUG1_REQUEST__##e)
+#define BFM_LRADC_DEBUG1_REQUEST_V(v)           BM_LRADC_DEBUG1_REQUEST
+#define BP_LRADC_DEBUG1_TESTMODE_COUNT          8
+#define BM_LRADC_DEBUG1_TESTMODE_COUNT          0x1f00
+#define BF_LRADC_DEBUG1_TESTMODE_COUNT(v)       (((v) & 0x1f) << 8)
+#define BFM_LRADC_DEBUG1_TESTMODE_COUNT(v)      BM_LRADC_DEBUG1_TESTMODE_COUNT
+#define BF_LRADC_DEBUG1_TESTMODE_COUNT_V(e)     BF_LRADC_DEBUG1_TESTMODE_COUNT(BV_LRADC_DEBUG1_TESTMODE_COUNT__##e)
+#define BFM_LRADC_DEBUG1_TESTMODE_COUNT_V(v)    BM_LRADC_DEBUG1_TESTMODE_COUNT
+#define BP_LRADC_DEBUG1_TESTMODE6               2
+#define BM_LRADC_DEBUG1_TESTMODE6               0x4
+#define BV_LRADC_DEBUG1_TESTMODE6__NORMAL       0x0
+#define BV_LRADC_DEBUG1_TESTMODE6__TEST         0x1
+#define BF_LRADC_DEBUG1_TESTMODE6(v)            (((v) & 0x1) << 2)
+#define BFM_LRADC_DEBUG1_TESTMODE6(v)           BM_LRADC_DEBUG1_TESTMODE6
+#define BF_LRADC_DEBUG1_TESTMODE6_V(e)          BF_LRADC_DEBUG1_TESTMODE6(BV_LRADC_DEBUG1_TESTMODE6__##e)
+#define BFM_LRADC_DEBUG1_TESTMODE6_V(v)         BM_LRADC_DEBUG1_TESTMODE6
+#define BP_LRADC_DEBUG1_TESTMODE5               1
+#define BM_LRADC_DEBUG1_TESTMODE5               0x2
+#define BV_LRADC_DEBUG1_TESTMODE5__NORMAL       0x0
+#define BV_LRADC_DEBUG1_TESTMODE5__TEST         0x1
+#define BF_LRADC_DEBUG1_TESTMODE5(v)            (((v) & 0x1) << 1)
+#define BFM_LRADC_DEBUG1_TESTMODE5(v)           BM_LRADC_DEBUG1_TESTMODE5
+#define BF_LRADC_DEBUG1_TESTMODE5_V(e)          BF_LRADC_DEBUG1_TESTMODE5(BV_LRADC_DEBUG1_TESTMODE5__##e)
+#define BFM_LRADC_DEBUG1_TESTMODE5_V(v)         BM_LRADC_DEBUG1_TESTMODE5
+#define BP_LRADC_DEBUG1_TESTMODE                0
+#define BM_LRADC_DEBUG1_TESTMODE                0x1
+#define BV_LRADC_DEBUG1_TESTMODE__NORMAL        0x0
+#define BV_LRADC_DEBUG1_TESTMODE__TEST          0x1
+#define BF_LRADC_DEBUG1_TESTMODE(v)             (((v) & 0x1) << 0)
+#define BFM_LRADC_DEBUG1_TESTMODE(v)            BM_LRADC_DEBUG1_TESTMODE
+#define BF_LRADC_DEBUG1_TESTMODE_V(e)           BF_LRADC_DEBUG1_TESTMODE(BV_LRADC_DEBUG1_TESTMODE__##e)
+#define BFM_LRADC_DEBUG1_TESTMODE_V(v)          BM_LRADC_DEBUG1_TESTMODE
+
+#define HW_LRADC_CONVERSION                             HW(LRADC_CONVERSION)
+#define HWA_LRADC_CONVERSION                            (0x80050000 + 0x130)
+#define HWT_LRADC_CONVERSION                            HWIO_32_RW
+#define HWN_LRADC_CONVERSION                            LRADC_CONVERSION
+#define HWI_LRADC_CONVERSION                            
+#define HW_LRADC_CONVERSION_SET                         HW(LRADC_CONVERSION_SET)
+#define HWA_LRADC_CONVERSION_SET                        (HWA_LRADC_CONVERSION + 0x4)
+#define HWT_LRADC_CONVERSION_SET                        HWIO_32_WO
+#define HWN_LRADC_CONVERSION_SET                        LRADC_CONVERSION
+#define HWI_LRADC_CONVERSION_SET                        
+#define HW_LRADC_CONVERSION_CLR                         HW(LRADC_CONVERSION_CLR)
+#define HWA_LRADC_CONVERSION_CLR                        (HWA_LRADC_CONVERSION + 0x8)
+#define HWT_LRADC_CONVERSION_CLR                        HWIO_32_WO
+#define HWN_LRADC_CONVERSION_CLR                        LRADC_CONVERSION
+#define HWI_LRADC_CONVERSION_CLR                        
+#define HW_LRADC_CONVERSION_TOG                         HW(LRADC_CONVERSION_TOG)
+#define HWA_LRADC_CONVERSION_TOG                        (HWA_LRADC_CONVERSION + 0xc)
+#define HWT_LRADC_CONVERSION_TOG                        HWIO_32_WO
+#define HWN_LRADC_CONVERSION_TOG                        LRADC_CONVERSION
+#define HWI_LRADC_CONVERSION_TOG                        
+#define BP_LRADC_CONVERSION_AUTOMATIC                   20
+#define BM_LRADC_CONVERSION_AUTOMATIC                   0x100000
+#define BV_LRADC_CONVERSION_AUTOMATIC__DISABLE          0x0
+#define BV_LRADC_CONVERSION_AUTOMATIC__ENABLE           0x1
+#define BF_LRADC_CONVERSION_AUTOMATIC(v)                (((v) & 0x1) << 20)
+#define BFM_LRADC_CONVERSION_AUTOMATIC(v)               BM_LRADC_CONVERSION_AUTOMATIC
+#define BF_LRADC_CONVERSION_AUTOMATIC_V(e)              BF_LRADC_CONVERSION_AUTOMATIC(BV_LRADC_CONVERSION_AUTOMATIC__##e)
+#define BFM_LRADC_CONVERSION_AUTOMATIC_V(v)             BM_LRADC_CONVERSION_AUTOMATIC
+#define BP_LRADC_CONVERSION_SCALE_FACTOR                16
+#define BM_LRADC_CONVERSION_SCALE_FACTOR                0x30000
+#define BV_LRADC_CONVERSION_SCALE_FACTOR__NIMH          0x0
+#define BV_LRADC_CONVERSION_SCALE_FACTOR__DUAL_NIMH     0x1
+#define BV_LRADC_CONVERSION_SCALE_FACTOR__LI_ION        0x2
+#define BV_LRADC_CONVERSION_SCALE_FACTOR__ALT_LI_ION    0x3
+#define BF_LRADC_CONVERSION_SCALE_FACTOR(v)             (((v) & 0x3) << 16)
+#define BFM_LRADC_CONVERSION_SCALE_FACTOR(v)            BM_LRADC_CONVERSION_SCALE_FACTOR
+#define BF_LRADC_CONVERSION_SCALE_FACTOR_V(e)           BF_LRADC_CONVERSION_SCALE_FACTOR(BV_LRADC_CONVERSION_SCALE_FACTOR__##e)
+#define BFM_LRADC_CONVERSION_SCALE_FACTOR_V(v)          BM_LRADC_CONVERSION_SCALE_FACTOR
+#define BP_LRADC_CONVERSION_SCALED_BATT_VOLTAGE         0
+#define BM_LRADC_CONVERSION_SCALED_BATT_VOLTAGE         0x3ff
+#define BF_LRADC_CONVERSION_SCALED_BATT_VOLTAGE(v)      (((v) & 0x3ff) << 0)
+#define BFM_LRADC_CONVERSION_SCALED_BATT_VOLTAGE(v)     BM_LRADC_CONVERSION_SCALED_BATT_VOLTAGE
+#define BF_LRADC_CONVERSION_SCALED_BATT_VOLTAGE_V(e)    BF_LRADC_CONVERSION_SCALED_BATT_VOLTAGE(BV_LRADC_CONVERSION_SCALED_BATT_VOLTAGE__##e)
+#define BFM_LRADC_CONVERSION_SCALED_BATT_VOLTAGE_V(v)   BM_LRADC_CONVERSION_SCALED_BATT_VOLTAGE
+
+#define HW_LRADC_DELAYn(_n1)                    HW(LRADC_DELAYn(_n1))
+#define HWA_LRADC_DELAYn(_n1)                   (0x80050000 + 0xd0 + (_n1) * 0x10)
+#define HWT_LRADC_DELAYn(_n1)                   HWIO_32_RW
+#define HWN_LRADC_DELAYn(_n1)                   LRADC_DELAYn
+#define HWI_LRADC_DELAYn(_n1)                   (_n1)
+#define HW_LRADC_DELAYn_SET(_n1)                HW(LRADC_DELAYn_SET(_n1))
+#define HWA_LRADC_DELAYn_SET(_n1)               (HWA_LRADC_DELAYn(_n1) + 0x4)
+#define HWT_LRADC_DELAYn_SET(_n1)               HWIO_32_WO
+#define HWN_LRADC_DELAYn_SET(_n1)               LRADC_DELAYn
+#define HWI_LRADC_DELAYn_SET(_n1)               (_n1)
+#define HW_LRADC_DELAYn_CLR(_n1)                HW(LRADC_DELAYn_CLR(_n1))
+#define HWA_LRADC_DELAYn_CLR(_n1)               (HWA_LRADC_DELAYn(_n1) + 0x8)
+#define HWT_LRADC_DELAYn_CLR(_n1)               HWIO_32_WO
+#define HWN_LRADC_DELAYn_CLR(_n1)               LRADC_DELAYn
+#define HWI_LRADC_DELAYn_CLR(_n1)               (_n1)
+#define HW_LRADC_DELAYn_TOG(_n1)                HW(LRADC_DELAYn_TOG(_n1))
+#define HWA_LRADC_DELAYn_TOG(_n1)               (HWA_LRADC_DELAYn(_n1) + 0xc)
+#define HWT_LRADC_DELAYn_TOG(_n1)               HWIO_32_WO
+#define HWN_LRADC_DELAYn_TOG(_n1)               LRADC_DELAYn
+#define HWI_LRADC_DELAYn_TOG(_n1)               (_n1)
+#define BP_LRADC_DELAYn_TRIGGER_LRADCS          24
+#define BM_LRADC_DELAYn_TRIGGER_LRADCS          0xff000000
+#define BF_LRADC_DELAYn_TRIGGER_LRADCS(v)       (((v) & 0xff) << 24)
+#define BFM_LRADC_DELAYn_TRIGGER_LRADCS(v)      BM_LRADC_DELAYn_TRIGGER_LRADCS
+#define BF_LRADC_DELAYn_TRIGGER_LRADCS_V(e)     BF_LRADC_DELAYn_TRIGGER_LRADCS(BV_LRADC_DELAYn_TRIGGER_LRADCS__##e)
+#define BFM_LRADC_DELAYn_TRIGGER_LRADCS_V(v)    BM_LRADC_DELAYn_TRIGGER_LRADCS
+#define BP_LRADC_DELAYn_KICK                    20
+#define BM_LRADC_DELAYn_KICK                    0x100000
+#define BF_LRADC_DELAYn_KICK(v)                 (((v) & 0x1) << 20)
+#define BFM_LRADC_DELAYn_KICK(v)                BM_LRADC_DELAYn_KICK
+#define BF_LRADC_DELAYn_KICK_V(e)               BF_LRADC_DELAYn_KICK(BV_LRADC_DELAYn_KICK__##e)
+#define BFM_LRADC_DELAYn_KICK_V(v)              BM_LRADC_DELAYn_KICK
+#define BP_LRADC_DELAYn_TRIGGER_DELAYS          16
+#define BM_LRADC_DELAYn_TRIGGER_DELAYS          0xf0000
+#define BF_LRADC_DELAYn_TRIGGER_DELAYS(v)       (((v) & 0xf) << 16)
+#define BFM_LRADC_DELAYn_TRIGGER_DELAYS(v)      BM_LRADC_DELAYn_TRIGGER_DELAYS
+#define BF_LRADC_DELAYn_TRIGGER_DELAYS_V(e)     BF_LRADC_DELAYn_TRIGGER_DELAYS(BV_LRADC_DELAYn_TRIGGER_DELAYS__##e)
+#define BFM_LRADC_DELAYn_TRIGGER_DELAYS_V(v)    BM_LRADC_DELAYn_TRIGGER_DELAYS
+#define BP_LRADC_DELAYn_LOOP_COUNT              11
+#define BM_LRADC_DELAYn_LOOP_COUNT              0xf800
+#define BF_LRADC_DELAYn_LOOP_COUNT(v)           (((v) & 0x1f) << 11)
+#define BFM_LRADC_DELAYn_LOOP_COUNT(v)          BM_LRADC_DELAYn_LOOP_COUNT
+#define BF_LRADC_DELAYn_LOOP_COUNT_V(e)         BF_LRADC_DELAYn_LOOP_COUNT(BV_LRADC_DELAYn_LOOP_COUNT__##e)
+#define BFM_LRADC_DELAYn_LOOP_COUNT_V(v)        BM_LRADC_DELAYn_LOOP_COUNT
+#define BP_LRADC_DELAYn_DELAY                   0
+#define BM_LRADC_DELAYn_DELAY                   0x7ff
+#define BF_LRADC_DELAYn_DELAY(v)                (((v) & 0x7ff) << 0)
+#define BFM_LRADC_DELAYn_DELAY(v)               BM_LRADC_DELAYn_DELAY
+#define BF_LRADC_DELAYn_DELAY_V(e)              BF_LRADC_DELAYn_DELAY(BV_LRADC_DELAYn_DELAY__##e)
+#define BFM_LRADC_DELAYn_DELAY_V(v)             BM_LRADC_DELAYn_DELAY
+
+#define HW_LRADC_CHn(_n1)               HW(LRADC_CHn(_n1))
+#define HWA_LRADC_CHn(_n1)              (0x80050000 + 0x50 + (_n1) * 0x10)
+#define HWT_LRADC_CHn(_n1)              HWIO_32_RW
+#define HWN_LRADC_CHn(_n1)              LRADC_CHn
+#define HWI_LRADC_CHn(_n1)              (_n1)
+#define HW_LRADC_CHn_SET(_n1)           HW(LRADC_CHn_SET(_n1))
+#define HWA_LRADC_CHn_SET(_n1)          (HWA_LRADC_CHn(_n1) + 0x4)
+#define HWT_LRADC_CHn_SET(_n1)          HWIO_32_WO
+#define HWN_LRADC_CHn_SET(_n1)          LRADC_CHn
+#define HWI_LRADC_CHn_SET(_n1)          (_n1)
+#define HW_LRADC_CHn_CLR(_n1)           HW(LRADC_CHn_CLR(_n1))
+#define HWA_LRADC_CHn_CLR(_n1)          (HWA_LRADC_CHn(_n1) + 0x8)
+#define HWT_LRADC_CHn_CLR(_n1)          HWIO_32_WO
+#define HWN_LRADC_CHn_CLR(_n1)          LRADC_CHn
+#define HWI_LRADC_CHn_CLR(_n1)          (_n1)
+#define HW_LRADC_CHn_TOG(_n1)           HW(LRADC_CHn_TOG(_n1))
+#define HWA_LRADC_CHn_TOG(_n1)          (HWA_LRADC_CHn(_n1) + 0xc)
+#define HWT_LRADC_CHn_TOG(_n1)          HWIO_32_WO
+#define HWN_LRADC_CHn_TOG(_n1)          LRADC_CHn
+#define HWI_LRADC_CHn_TOG(_n1)          (_n1)
+#define BP_LRADC_CHn_TOGGLE             31
+#define BM_LRADC_CHn_TOGGLE             0x80000000
+#define BF_LRADC_CHn_TOGGLE(v)          (((v) & 0x1) << 31)
+#define BFM_LRADC_CHn_TOGGLE(v)         BM_LRADC_CHn_TOGGLE
+#define BF_LRADC_CHn_TOGGLE_V(e)        BF_LRADC_CHn_TOGGLE(BV_LRADC_CHn_TOGGLE__##e)
+#define BFM_LRADC_CHn_TOGGLE_V(v)       BM_LRADC_CHn_TOGGLE
+#define BP_LRADC_CHn_ACCUMULATE         29
+#define BM_LRADC_CHn_ACCUMULATE         0x20000000
+#define BF_LRADC_CHn_ACCUMULATE(v)      (((v) & 0x1) << 29)
+#define BFM_LRADC_CHn_ACCUMULATE(v)     BM_LRADC_CHn_ACCUMULATE
+#define BF_LRADC_CHn_ACCUMULATE_V(e)    BF_LRADC_CHn_ACCUMULATE(BV_LRADC_CHn_ACCUMULATE__##e)
+#define BFM_LRADC_CHn_ACCUMULATE_V(v)   BM_LRADC_CHn_ACCUMULATE
+#define BP_LRADC_CHn_NUM_SAMPLES        24
+#define BM_LRADC_CHn_NUM_SAMPLES        0x1f000000
+#define BF_LRADC_CHn_NUM_SAMPLES(v)     (((v) & 0x1f) << 24)
+#define BFM_LRADC_CHn_NUM_SAMPLES(v)    BM_LRADC_CHn_NUM_SAMPLES
+#define BF_LRADC_CHn_NUM_SAMPLES_V(e)   BF_LRADC_CHn_NUM_SAMPLES(BV_LRADC_CHn_NUM_SAMPLES__##e)
+#define BFM_LRADC_CHn_NUM_SAMPLES_V(v)  BM_LRADC_CHn_NUM_SAMPLES
+#define BP_LRADC_CHn_VALUE              0
+#define BM_LRADC_CHn_VALUE              0x3ffff
+#define BF_LRADC_CHn_VALUE(v)           (((v) & 0x3ffff) << 0)
+#define BFM_LRADC_CHn_VALUE(v)          BM_LRADC_CHn_VALUE
+#define BF_LRADC_CHn_VALUE_V(e)         BF_LRADC_CHn_VALUE(BV_LRADC_CHn_VALUE__##e)
+#define BFM_LRADC_CHn_VALUE_V(v)        BM_LRADC_CHn_VALUE
+
+#endif /* __HEADERGEN_STMP3600_LRADC_H__*/
diff --git a/firmware/target/arm/imx233/regs/stmp3600/memcpy.h b/firmware/target/arm/imx233/regs/stmp3600/memcpy.h
new file mode 100644
index 0000000000..a65b4871a2
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3600/memcpy.h
@@ -0,0 +1,159 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * stmp3600 version: 2.4.0
+ * stmp3600 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_STMP3600_MEMCPY_H__
+#define __HEADERGEN_STMP3600_MEMCPY_H__
+
+#define HW_MEMCPY_CTRL                      HW(MEMCPY_CTRL)
+#define HWA_MEMCPY_CTRL                     (0x80014000 + 0x0)
+#define HWT_MEMCPY_CTRL                     HWIO_32_RW
+#define HWN_MEMCPY_CTRL                     MEMCPY_CTRL
+#define HWI_MEMCPY_CTRL                     
+#define HW_MEMCPY_CTRL_SET                  HW(MEMCPY_CTRL_SET)
+#define HWA_MEMCPY_CTRL_SET                 (HWA_MEMCPY_CTRL + 0x4)
+#define HWT_MEMCPY_CTRL_SET                 HWIO_32_WO
+#define HWN_MEMCPY_CTRL_SET                 MEMCPY_CTRL
+#define HWI_MEMCPY_CTRL_SET                 
+#define HW_MEMCPY_CTRL_CLR                  HW(MEMCPY_CTRL_CLR)
+#define HWA_MEMCPY_CTRL_CLR                 (HWA_MEMCPY_CTRL + 0x8)
+#define HWT_MEMCPY_CTRL_CLR                 HWIO_32_WO
+#define HWN_MEMCPY_CTRL_CLR                 MEMCPY_CTRL
+#define HWI_MEMCPY_CTRL_CLR                 
+#define HW_MEMCPY_CTRL_TOG                  HW(MEMCPY_CTRL_TOG)
+#define HWA_MEMCPY_CTRL_TOG                 (HWA_MEMCPY_CTRL + 0xc)
+#define HWT_MEMCPY_CTRL_TOG                 HWIO_32_WO
+#define HWN_MEMCPY_CTRL_TOG                 MEMCPY_CTRL
+#define HWI_MEMCPY_CTRL_TOG                 
+#define BP_MEMCPY_CTRL_SFTRST               31
+#define BM_MEMCPY_CTRL_SFTRST               0x80000000
+#define BV_MEMCPY_CTRL_SFTRST__RUN          0x0
+#define BV_MEMCPY_CTRL_SFTRST__RESET        0x1
+#define BF_MEMCPY_CTRL_SFTRST(v)            (((v) & 0x1) << 31)
+#define BFM_MEMCPY_CTRL_SFTRST(v)           BM_MEMCPY_CTRL_SFTRST
+#define BF_MEMCPY_CTRL_SFTRST_V(e)          BF_MEMCPY_CTRL_SFTRST(BV_MEMCPY_CTRL_SFTRST__##e)
+#define BFM_MEMCPY_CTRL_SFTRST_V(v)         BM_MEMCPY_CTRL_SFTRST
+#define BP_MEMCPY_CTRL_CLKGATE              30
+#define BM_MEMCPY_CTRL_CLKGATE              0x40000000
+#define BV_MEMCPY_CTRL_CLKGATE__RUN         0x0
+#define BV_MEMCPY_CTRL_CLKGATE__NO_CLKS     0x1
+#define BF_MEMCPY_CTRL_CLKGATE(v)           (((v) & 0x1) << 30)
+#define BFM_MEMCPY_CTRL_CLKGATE(v)          BM_MEMCPY_CTRL_CLKGATE
+#define BF_MEMCPY_CTRL_CLKGATE_V(e)         BF_MEMCPY_CTRL_CLKGATE(BV_MEMCPY_CTRL_CLKGATE__##e)
+#define BFM_MEMCPY_CTRL_CLKGATE_V(v)        BM_MEMCPY_CTRL_CLKGATE
+#define BP_MEMCPY_CTRL_PRESENT              29
+#define BM_MEMCPY_CTRL_PRESENT              0x20000000
+#define BV_MEMCPY_CTRL_PRESENT__UNAVAILABLE 0x0
+#define BV_MEMCPY_CTRL_PRESENT__AVAILABLE   0x1
+#define BF_MEMCPY_CTRL_PRESENT(v)           (((v) & 0x1) << 29)
+#define BFM_MEMCPY_CTRL_PRESENT(v)          BM_MEMCPY_CTRL_PRESENT
+#define BF_MEMCPY_CTRL_PRESENT_V(e)         BF_MEMCPY_CTRL_PRESENT(BV_MEMCPY_CTRL_PRESENT__##e)
+#define BFM_MEMCPY_CTRL_PRESENT_V(v)        BM_MEMCPY_CTRL_PRESENT
+#define BP_MEMCPY_CTRL_BURST                16
+#define BM_MEMCPY_CTRL_BURST                0x10000
+#define BF_MEMCPY_CTRL_BURST(v)             (((v) & 0x1) << 16)
+#define BFM_MEMCPY_CTRL_BURST(v)            BM_MEMCPY_CTRL_BURST
+#define BF_MEMCPY_CTRL_BURST_V(e)           BF_MEMCPY_CTRL_BURST(BV_MEMCPY_CTRL_BURST__##e)
+#define BFM_MEMCPY_CTRL_BURST_V(v)          BM_MEMCPY_CTRL_BURST
+#define BP_MEMCPY_CTRL_XFER_SIZE            0
+#define BM_MEMCPY_CTRL_XFER_SIZE            0xffff
+#define BF_MEMCPY_CTRL_XFER_SIZE(v)         (((v) & 0xffff) << 0)
+#define BFM_MEMCPY_CTRL_XFER_SIZE(v)        BM_MEMCPY_CTRL_XFER_SIZE
+#define BF_MEMCPY_CTRL_XFER_SIZE_V(e)       BF_MEMCPY_CTRL_XFER_SIZE(BV_MEMCPY_CTRL_XFER_SIZE__##e)
+#define BFM_MEMCPY_CTRL_XFER_SIZE_V(v)      BM_MEMCPY_CTRL_XFER_SIZE
+
+#define HW_MEMCPY_DATA              HW(MEMCPY_DATA)
+#define HWA_MEMCPY_DATA             (0x80014000 + 0x10)
+#define HWT_MEMCPY_DATA             HWIO_32_RW
+#define HWN_MEMCPY_DATA             MEMCPY_DATA
+#define HWI_MEMCPY_DATA             
+#define HW_MEMCPY_DATA_SET          HW(MEMCPY_DATA_SET)
+#define HWA_MEMCPY_DATA_SET         (HWA_MEMCPY_DATA + 0x4)
+#define HWT_MEMCPY_DATA_SET         HWIO_32_WO
+#define HWN_MEMCPY_DATA_SET         MEMCPY_DATA
+#define HWI_MEMCPY_DATA_SET         
+#define HW_MEMCPY_DATA_CLR          HW(MEMCPY_DATA_CLR)
+#define HWA_MEMCPY_DATA_CLR         (HWA_MEMCPY_DATA + 0x8)
+#define HWT_MEMCPY_DATA_CLR         HWIO_32_WO
+#define HWN_MEMCPY_DATA_CLR         MEMCPY_DATA
+#define HWI_MEMCPY_DATA_CLR         
+#define HW_MEMCPY_DATA_TOG          HW(MEMCPY_DATA_TOG)
+#define HWA_MEMCPY_DATA_TOG         (HWA_MEMCPY_DATA + 0xc)
+#define HWT_MEMCPY_DATA_TOG         HWIO_32_WO
+#define HWN_MEMCPY_DATA_TOG         MEMCPY_DATA
+#define HWI_MEMCPY_DATA_TOG         
+#define BP_MEMCPY_DATA_DATA         0
+#define BM_MEMCPY_DATA_DATA         0xffffffff
+#define BF_MEMCPY_DATA_DATA(v)      (((v) & 0xffffffff) << 0)
+#define BFM_MEMCPY_DATA_DATA(v)     BM_MEMCPY_DATA_DATA
+#define BF_MEMCPY_DATA_DATA_V(e)    BF_MEMCPY_DATA_DATA(BV_MEMCPY_DATA_DATA__##e)
+#define BFM_MEMCPY_DATA_DATA_V(v)   BM_MEMCPY_DATA_DATA
+
+#define HW_MEMCPY_DEBUG                     HW(MEMCPY_DEBUG)
+#define HWA_MEMCPY_DEBUG                    (0x80014000 + 0x20)
+#define HWT_MEMCPY_DEBUG                    HWIO_32_RW
+#define HWN_MEMCPY_DEBUG                    MEMCPY_DEBUG
+#define HWI_MEMCPY_DEBUG                    
+#define BP_MEMCPY_DEBUG_DST_END_CMD         30
+#define BM_MEMCPY_DEBUG_DST_END_CMD         0x40000000
+#define BF_MEMCPY_DEBUG_DST_END_CMD(v)      (((v) & 0x1) << 30)
+#define BFM_MEMCPY_DEBUG_DST_END_CMD(v)     BM_MEMCPY_DEBUG_DST_END_CMD
+#define BF_MEMCPY_DEBUG_DST_END_CMD_V(e)    BF_MEMCPY_DEBUG_DST_END_CMD(BV_MEMCPY_DEBUG_DST_END_CMD__##e)
+#define BFM_MEMCPY_DEBUG_DST_END_CMD_V(v)   BM_MEMCPY_DEBUG_DST_END_CMD
+#define BP_MEMCPY_DEBUG_DST_KICK            29
+#define BM_MEMCPY_DEBUG_DST_KICK            0x20000000
+#define BF_MEMCPY_DEBUG_DST_KICK(v)         (((v) & 0x1) << 29)
+#define BFM_MEMCPY_DEBUG_DST_KICK(v)        BM_MEMCPY_DEBUG_DST_KICK
+#define BF_MEMCPY_DEBUG_DST_KICK_V(e)       BF_MEMCPY_DEBUG_DST_KICK(BV_MEMCPY_DEBUG_DST_KICK__##e)
+#define BFM_MEMCPY_DEBUG_DST_KICK_V(v)      BM_MEMCPY_DEBUG_DST_KICK
+#define BP_MEMCPY_DEBUG_DST_DMA_REQ         28
+#define BM_MEMCPY_DEBUG_DST_DMA_REQ         0x10000000
+#define BF_MEMCPY_DEBUG_DST_DMA_REQ(v)      (((v) & 0x1) << 28)
+#define BFM_MEMCPY_DEBUG_DST_DMA_REQ(v)     BM_MEMCPY_DEBUG_DST_DMA_REQ
+#define BF_MEMCPY_DEBUG_DST_DMA_REQ_V(e)    BF_MEMCPY_DEBUG_DST_DMA_REQ(BV_MEMCPY_DEBUG_DST_DMA_REQ__##e)
+#define BFM_MEMCPY_DEBUG_DST_DMA_REQ_V(v)   BM_MEMCPY_DEBUG_DST_DMA_REQ
+#define BP_MEMCPY_DEBUG_SRC_KICK            25
+#define BM_MEMCPY_DEBUG_SRC_KICK            0x2000000
+#define BF_MEMCPY_DEBUG_SRC_KICK(v)         (((v) & 0x1) << 25)
+#define BFM_MEMCPY_DEBUG_SRC_KICK(v)        BM_MEMCPY_DEBUG_SRC_KICK
+#define BF_MEMCPY_DEBUG_SRC_KICK_V(e)       BF_MEMCPY_DEBUG_SRC_KICK(BV_MEMCPY_DEBUG_SRC_KICK__##e)
+#define BFM_MEMCPY_DEBUG_SRC_KICK_V(v)      BM_MEMCPY_DEBUG_SRC_KICK
+#define BP_MEMCPY_DEBUG_SRC_DMA_REQ         24
+#define BM_MEMCPY_DEBUG_SRC_DMA_REQ         0x1000000
+#define BF_MEMCPY_DEBUG_SRC_DMA_REQ(v)      (((v) & 0x1) << 24)
+#define BFM_MEMCPY_DEBUG_SRC_DMA_REQ(v)     BM_MEMCPY_DEBUG_SRC_DMA_REQ
+#define BF_MEMCPY_DEBUG_SRC_DMA_REQ_V(e)    BF_MEMCPY_DEBUG_SRC_DMA_REQ(BV_MEMCPY_DEBUG_SRC_DMA_REQ__##e)
+#define BFM_MEMCPY_DEBUG_SRC_DMA_REQ_V(v)   BM_MEMCPY_DEBUG_SRC_DMA_REQ
+#define BP_MEMCPY_DEBUG_WRITE_STATE         2
+#define BM_MEMCPY_DEBUG_WRITE_STATE         0xc
+#define BF_MEMCPY_DEBUG_WRITE_STATE(v)      (((v) & 0x3) << 2)
+#define BFM_MEMCPY_DEBUG_WRITE_STATE(v)     BM_MEMCPY_DEBUG_WRITE_STATE
+#define BF_MEMCPY_DEBUG_WRITE_STATE_V(e)    BF_MEMCPY_DEBUG_WRITE_STATE(BV_MEMCPY_DEBUG_WRITE_STATE__##e)
+#define BFM_MEMCPY_DEBUG_WRITE_STATE_V(v)   BM_MEMCPY_DEBUG_WRITE_STATE
+#define BP_MEMCPY_DEBUG_READ_STATE          0
+#define BM_MEMCPY_DEBUG_READ_STATE          0x3
+#define BF_MEMCPY_DEBUG_READ_STATE(v)       (((v) & 0x3) << 0)
+#define BFM_MEMCPY_DEBUG_READ_STATE(v)      BM_MEMCPY_DEBUG_READ_STATE
+#define BF_MEMCPY_DEBUG_READ_STATE_V(e)     BF_MEMCPY_DEBUG_READ_STATE(BV_MEMCPY_DEBUG_READ_STATE__##e)
+#define BFM_MEMCPY_DEBUG_READ_STATE_V(v)    BM_MEMCPY_DEBUG_READ_STATE
+
+#endif /* __HEADERGEN_STMP3600_MEMCPY_H__*/
diff --git a/firmware/target/arm/imx233/regs/stmp3600/pinctrl.h b/firmware/target/arm/imx233/regs/stmp3600/pinctrl.h
new file mode 100644
index 0000000000..244146569b
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3600/pinctrl.h
@@ -0,0 +1,405 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * stmp3600 version: 2.4.0
+ * stmp3600 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_STMP3600_PINCTRL_H__
+#define __HEADERGEN_STMP3600_PINCTRL_H__
+
+#define HW_PINCTRL_CTRL                 HW(PINCTRL_CTRL)
+#define HWA_PINCTRL_CTRL                (0x80018000 + 0x0)
+#define HWT_PINCTRL_CTRL                HWIO_32_RW
+#define HWN_PINCTRL_CTRL                PINCTRL_CTRL
+#define HWI_PINCTRL_CTRL                
+#define HW_PINCTRL_CTRL_SET             HW(PINCTRL_CTRL_SET)
+#define HWA_PINCTRL_CTRL_SET            (HWA_PINCTRL_CTRL + 0x4)
+#define HWT_PINCTRL_CTRL_SET            HWIO_32_WO
+#define HWN_PINCTRL_CTRL_SET            PINCTRL_CTRL
+#define HWI_PINCTRL_CTRL_SET            
+#define HW_PINCTRL_CTRL_CLR             HW(PINCTRL_CTRL_CLR)
+#define HWA_PINCTRL_CTRL_CLR            (HWA_PINCTRL_CTRL + 0x8)
+#define HWT_PINCTRL_CTRL_CLR            HWIO_32_WO
+#define HWN_PINCTRL_CTRL_CLR            PINCTRL_CTRL
+#define HWI_PINCTRL_CTRL_CLR            
+#define HW_PINCTRL_CTRL_TOG             HW(PINCTRL_CTRL_TOG)
+#define HWA_PINCTRL_CTRL_TOG            (HWA_PINCTRL_CTRL + 0xc)
+#define HWT_PINCTRL_CTRL_TOG            HWIO_32_WO
+#define HWN_PINCTRL_CTRL_TOG            PINCTRL_CTRL
+#define HWI_PINCTRL_CTRL_TOG            
+#define BP_PINCTRL_CTRL_SFTRST          31
+#define BM_PINCTRL_CTRL_SFTRST          0x80000000
+#define BF_PINCTRL_CTRL_SFTRST(v)       (((v) & 0x1) << 31)
+#define BFM_PINCTRL_CTRL_SFTRST(v)      BM_PINCTRL_CTRL_SFTRST
+#define BF_PINCTRL_CTRL_SFTRST_V(e)     BF_PINCTRL_CTRL_SFTRST(BV_PINCTRL_CTRL_SFTRST__##e)
+#define BFM_PINCTRL_CTRL_SFTRST_V(v)    BM_PINCTRL_CTRL_SFTRST
+#define BP_PINCTRL_CTRL_CLKGATE         30
+#define BM_PINCTRL_CTRL_CLKGATE         0x40000000
+#define BF_PINCTRL_CTRL_CLKGATE(v)      (((v) & 0x1) << 30)
+#define BFM_PINCTRL_CTRL_CLKGATE(v)     BM_PINCTRL_CTRL_CLKGATE
+#define BF_PINCTRL_CTRL_CLKGATE_V(e)    BF_PINCTRL_CTRL_CLKGATE(BV_PINCTRL_CTRL_CLKGATE__##e)
+#define BFM_PINCTRL_CTRL_CLKGATE_V(v)   BM_PINCTRL_CTRL_CLKGATE
+#define BP_PINCTRL_CTRL_PRESENT3        29
+#define BM_PINCTRL_CTRL_PRESENT3        0x20000000
+#define BF_PINCTRL_CTRL_PRESENT3(v)     (((v) & 0x1) << 29)
+#define BFM_PINCTRL_CTRL_PRESENT3(v)    BM_PINCTRL_CTRL_PRESENT3
+#define BF_PINCTRL_CTRL_PRESENT3_V(e)   BF_PINCTRL_CTRL_PRESENT3(BV_PINCTRL_CTRL_PRESENT3__##e)
+#define BFM_PINCTRL_CTRL_PRESENT3_V(v)  BM_PINCTRL_CTRL_PRESENT3
+#define BP_PINCTRL_CTRL_PRESENT2        28
+#define BM_PINCTRL_CTRL_PRESENT2        0x10000000
+#define BF_PINCTRL_CTRL_PRESENT2(v)     (((v) & 0x1) << 28)
+#define BFM_PINCTRL_CTRL_PRESENT2(v)    BM_PINCTRL_CTRL_PRESENT2
+#define BF_PINCTRL_CTRL_PRESENT2_V(e)   BF_PINCTRL_CTRL_PRESENT2(BV_PINCTRL_CTRL_PRESENT2__##e)
+#define BFM_PINCTRL_CTRL_PRESENT2_V(v)  BM_PINCTRL_CTRL_PRESENT2
+#define BP_PINCTRL_CTRL_PRESENT1        27
+#define BM_PINCTRL_CTRL_PRESENT1        0x8000000
+#define BF_PINCTRL_CTRL_PRESENT1(v)     (((v) & 0x1) << 27)
+#define BFM_PINCTRL_CTRL_PRESENT1(v)    BM_PINCTRL_CTRL_PRESENT1
+#define BF_PINCTRL_CTRL_PRESENT1_V(e)   BF_PINCTRL_CTRL_PRESENT1(BV_PINCTRL_CTRL_PRESENT1__##e)
+#define BFM_PINCTRL_CTRL_PRESENT1_V(v)  BM_PINCTRL_CTRL_PRESENT1
+#define BP_PINCTRL_CTRL_PRESENT0        26
+#define BM_PINCTRL_CTRL_PRESENT0        0x4000000
+#define BF_PINCTRL_CTRL_PRESENT0(v)     (((v) & 0x1) << 26)
+#define BFM_PINCTRL_CTRL_PRESENT0(v)    BM_PINCTRL_CTRL_PRESENT0
+#define BF_PINCTRL_CTRL_PRESENT0_V(e)   BF_PINCTRL_CTRL_PRESENT0(BV_PINCTRL_CTRL_PRESENT0__##e)
+#define BFM_PINCTRL_CTRL_PRESENT0_V(v)  BM_PINCTRL_CTRL_PRESENT0
+#define BP_PINCTRL_CTRL_IRQOUT3         3
+#define BM_PINCTRL_CTRL_IRQOUT3         0x8
+#define BF_PINCTRL_CTRL_IRQOUT3(v)      (((v) & 0x1) << 3)
+#define BFM_PINCTRL_CTRL_IRQOUT3(v)     BM_PINCTRL_CTRL_IRQOUT3
+#define BF_PINCTRL_CTRL_IRQOUT3_V(e)    BF_PINCTRL_CTRL_IRQOUT3(BV_PINCTRL_CTRL_IRQOUT3__##e)
+#define BFM_PINCTRL_CTRL_IRQOUT3_V(v)   BM_PINCTRL_CTRL_IRQOUT3
+#define BP_PINCTRL_CTRL_IRQOUT2         2
+#define BM_PINCTRL_CTRL_IRQOUT2         0x4
+#define BF_PINCTRL_CTRL_IRQOUT2(v)      (((v) & 0x1) << 2)
+#define BFM_PINCTRL_CTRL_IRQOUT2(v)     BM_PINCTRL_CTRL_IRQOUT2
+#define BF_PINCTRL_CTRL_IRQOUT2_V(e)    BF_PINCTRL_CTRL_IRQOUT2(BV_PINCTRL_CTRL_IRQOUT2__##e)
+#define BFM_PINCTRL_CTRL_IRQOUT2_V(v)   BM_PINCTRL_CTRL_IRQOUT2
+#define BP_PINCTRL_CTRL_IRQOUT1         1
+#define BM_PINCTRL_CTRL_IRQOUT1         0x2
+#define BF_PINCTRL_CTRL_IRQOUT1(v)      (((v) & 0x1) << 1)
+#define BFM_PINCTRL_CTRL_IRQOUT1(v)     BM_PINCTRL_CTRL_IRQOUT1
+#define BF_PINCTRL_CTRL_IRQOUT1_V(e)    BF_PINCTRL_CTRL_IRQOUT1(BV_PINCTRL_CTRL_IRQOUT1__##e)
+#define BFM_PINCTRL_CTRL_IRQOUT1_V(v)   BM_PINCTRL_CTRL_IRQOUT1
+#define BP_PINCTRL_CTRL_IRQOUT0         0
+#define BM_PINCTRL_CTRL_IRQOUT0         0x1
+#define BF_PINCTRL_CTRL_IRQOUT0(v)      (((v) & 0x1) << 0)
+#define BFM_PINCTRL_CTRL_IRQOUT0(v)     BM_PINCTRL_CTRL_IRQOUT0
+#define BF_PINCTRL_CTRL_IRQOUT0_V(e)    BF_PINCTRL_CTRL_IRQOUT0(BV_PINCTRL_CTRL_IRQOUT0__##e)
+#define BFM_PINCTRL_CTRL_IRQOUT0_V(v)   BM_PINCTRL_CTRL_IRQOUT0
+
+#define HW_PINCTRL_MUXSELLn(_n1)        HW(PINCTRL_MUXSELLn(_n1))
+#define HWA_PINCTRL_MUXSELLn(_n1)       (0x80018000 + 0x10 + (_n1) * 0x100)
+#define HWT_PINCTRL_MUXSELLn(_n1)       HWIO_32_RW
+#define HWN_PINCTRL_MUXSELLn(_n1)       PINCTRL_MUXSELLn
+#define HWI_PINCTRL_MUXSELLn(_n1)       (_n1)
+#define HW_PINCTRL_MUXSELLn_SET(_n1)    HW(PINCTRL_MUXSELLn_SET(_n1))
+#define HWA_PINCTRL_MUXSELLn_SET(_n1)   (HWA_PINCTRL_MUXSELLn(_n1) + 0x4)
+#define HWT_PINCTRL_MUXSELLn_SET(_n1)   HWIO_32_WO
+#define HWN_PINCTRL_MUXSELLn_SET(_n1)   PINCTRL_MUXSELLn
+#define HWI_PINCTRL_MUXSELLn_SET(_n1)   (_n1)
+#define HW_PINCTRL_MUXSELLn_CLR(_n1)    HW(PINCTRL_MUXSELLn_CLR(_n1))
+#define HWA_PINCTRL_MUXSELLn_CLR(_n1)   (HWA_PINCTRL_MUXSELLn(_n1) + 0x8)
+#define HWT_PINCTRL_MUXSELLn_CLR(_n1)   HWIO_32_WO
+#define HWN_PINCTRL_MUXSELLn_CLR(_n1)   PINCTRL_MUXSELLn
+#define HWI_PINCTRL_MUXSELLn_CLR(_n1)   (_n1)
+#define HW_PINCTRL_MUXSELLn_TOG(_n1)    HW(PINCTRL_MUXSELLn_TOG(_n1))
+#define HWA_PINCTRL_MUXSELLn_TOG(_n1)   (HWA_PINCTRL_MUXSELLn(_n1) + 0xc)
+#define HWT_PINCTRL_MUXSELLn_TOG(_n1)   HWIO_32_WO
+#define HWN_PINCTRL_MUXSELLn_TOG(_n1)   PINCTRL_MUXSELLn
+#define HWI_PINCTRL_MUXSELLn_TOG(_n1)   (_n1)
+#define BP_PINCTRL_MUXSELLn_BITS        0
+#define BM_PINCTRL_MUXSELLn_BITS        0xffffffff
+#define BF_PINCTRL_MUXSELLn_BITS(v)     (((v) & 0xffffffff) << 0)
+#define BFM_PINCTRL_MUXSELLn_BITS(v)    BM_PINCTRL_MUXSELLn_BITS
+#define BF_PINCTRL_MUXSELLn_BITS_V(e)   BF_PINCTRL_MUXSELLn_BITS(BV_PINCTRL_MUXSELLn_BITS__##e)
+#define BFM_PINCTRL_MUXSELLn_BITS_V(v)  BM_PINCTRL_MUXSELLn_BITS
+
+#define HW_PINCTRL_MUXSELHn(_n1)        HW(PINCTRL_MUXSELHn(_n1))
+#define HWA_PINCTRL_MUXSELHn(_n1)       (0x80018000 + 0x20 + (_n1) * 0x100)
+#define HWT_PINCTRL_MUXSELHn(_n1)       HWIO_32_RW
+#define HWN_PINCTRL_MUXSELHn(_n1)       PINCTRL_MUXSELHn
+#define HWI_PINCTRL_MUXSELHn(_n1)       (_n1)
+#define HW_PINCTRL_MUXSELHn_SET(_n1)    HW(PINCTRL_MUXSELHn_SET(_n1))
+#define HWA_PINCTRL_MUXSELHn_SET(_n1)   (HWA_PINCTRL_MUXSELHn(_n1) + 0x4)
+#define HWT_PINCTRL_MUXSELHn_SET(_n1)   HWIO_32_WO
+#define HWN_PINCTRL_MUXSELHn_SET(_n1)   PINCTRL_MUXSELHn
+#define HWI_PINCTRL_MUXSELHn_SET(_n1)   (_n1)
+#define HW_PINCTRL_MUXSELHn_CLR(_n1)    HW(PINCTRL_MUXSELHn_CLR(_n1))
+#define HWA_PINCTRL_MUXSELHn_CLR(_n1)   (HWA_PINCTRL_MUXSELHn(_n1) + 0x8)
+#define HWT_PINCTRL_MUXSELHn_CLR(_n1)   HWIO_32_WO
+#define HWN_PINCTRL_MUXSELHn_CLR(_n1)   PINCTRL_MUXSELHn
+#define HWI_PINCTRL_MUXSELHn_CLR(_n1)   (_n1)
+#define HW_PINCTRL_MUXSELHn_TOG(_n1)    HW(PINCTRL_MUXSELHn_TOG(_n1))
+#define HWA_PINCTRL_MUXSELHn_TOG(_n1)   (HWA_PINCTRL_MUXSELHn(_n1) + 0xc)
+#define HWT_PINCTRL_MUXSELHn_TOG(_n1)   HWIO_32_WO
+#define HWN_PINCTRL_MUXSELHn_TOG(_n1)   PINCTRL_MUXSELHn
+#define HWI_PINCTRL_MUXSELHn_TOG(_n1)   (_n1)
+#define BP_PINCTRL_MUXSELHn_BITS        0
+#define BM_PINCTRL_MUXSELHn_BITS        0xffffffff
+#define BF_PINCTRL_MUXSELHn_BITS(v)     (((v) & 0xffffffff) << 0)
+#define BFM_PINCTRL_MUXSELHn_BITS(v)    BM_PINCTRL_MUXSELHn_BITS
+#define BF_PINCTRL_MUXSELHn_BITS_V(e)   BF_PINCTRL_MUXSELHn_BITS(BV_PINCTRL_MUXSELHn_BITS__##e)
+#define BFM_PINCTRL_MUXSELHn_BITS_V(v)  BM_PINCTRL_MUXSELHn_BITS
+
+#define HW_PINCTRL_DRIVEn(_n1)          HW(PINCTRL_DRIVEn(_n1))
+#define HWA_PINCTRL_DRIVEn(_n1)         (0x80018000 + 0x30 + (_n1) * 0x100)
+#define HWT_PINCTRL_DRIVEn(_n1)         HWIO_32_RW
+#define HWN_PINCTRL_DRIVEn(_n1)         PINCTRL_DRIVEn
+#define HWI_PINCTRL_DRIVEn(_n1)         (_n1)
+#define HW_PINCTRL_DRIVEn_SET(_n1)      HW(PINCTRL_DRIVEn_SET(_n1))
+#define HWA_PINCTRL_DRIVEn_SET(_n1)     (HWA_PINCTRL_DRIVEn(_n1) + 0x4)
+#define HWT_PINCTRL_DRIVEn_SET(_n1)     HWIO_32_WO
+#define HWN_PINCTRL_DRIVEn_SET(_n1)     PINCTRL_DRIVEn
+#define HWI_PINCTRL_DRIVEn_SET(_n1)     (_n1)
+#define HW_PINCTRL_DRIVEn_CLR(_n1)      HW(PINCTRL_DRIVEn_CLR(_n1))
+#define HWA_PINCTRL_DRIVEn_CLR(_n1)     (HWA_PINCTRL_DRIVEn(_n1) + 0x8)
+#define HWT_PINCTRL_DRIVEn_CLR(_n1)     HWIO_32_WO
+#define HWN_PINCTRL_DRIVEn_CLR(_n1)     PINCTRL_DRIVEn
+#define HWI_PINCTRL_DRIVEn_CLR(_n1)     (_n1)
+#define HW_PINCTRL_DRIVEn_TOG(_n1)      HW(PINCTRL_DRIVEn_TOG(_n1))
+#define HWA_PINCTRL_DRIVEn_TOG(_n1)     (HWA_PINCTRL_DRIVEn(_n1) + 0xc)
+#define HWT_PINCTRL_DRIVEn_TOG(_n1)     HWIO_32_WO
+#define HWN_PINCTRL_DRIVEn_TOG(_n1)     PINCTRL_DRIVEn
+#define HWI_PINCTRL_DRIVEn_TOG(_n1)     (_n1)
+#define BP_PINCTRL_DRIVEn_BITS          0
+#define BM_PINCTRL_DRIVEn_BITS          0xffffffff
+#define BF_PINCTRL_DRIVEn_BITS(v)       (((v) & 0xffffffff) << 0)
+#define BFM_PINCTRL_DRIVEn_BITS(v)      BM_PINCTRL_DRIVEn_BITS
+#define BF_PINCTRL_DRIVEn_BITS_V(e)     BF_PINCTRL_DRIVEn_BITS(BV_PINCTRL_DRIVEn_BITS__##e)
+#define BFM_PINCTRL_DRIVEn_BITS_V(v)    BM_PINCTRL_DRIVEn_BITS
+
+#define HW_PINCTRL_DOUTn(_n1)       HW(PINCTRL_DOUTn(_n1))
+#define HWA_PINCTRL_DOUTn(_n1)      (0x80018000 + 0x50 + (_n1) * 0x100)
+#define HWT_PINCTRL_DOUTn(_n1)      HWIO_32_RW
+#define HWN_PINCTRL_DOUTn(_n1)      PINCTRL_DOUTn
+#define HWI_PINCTRL_DOUTn(_n1)      (_n1)
+#define HW_PINCTRL_DOUTn_SET(_n1)   HW(PINCTRL_DOUTn_SET(_n1))
+#define HWA_PINCTRL_DOUTn_SET(_n1)  (HWA_PINCTRL_DOUTn(_n1) + 0x4)
+#define HWT_PINCTRL_DOUTn_SET(_n1)  HWIO_32_WO
+#define HWN_PINCTRL_DOUTn_SET(_n1)  PINCTRL_DOUTn
+#define HWI_PINCTRL_DOUTn_SET(_n1)  (_n1)
+#define HW_PINCTRL_DOUTn_CLR(_n1)   HW(PINCTRL_DOUTn_CLR(_n1))
+#define HWA_PINCTRL_DOUTn_CLR(_n1)  (HWA_PINCTRL_DOUTn(_n1) + 0x8)
+#define HWT_PINCTRL_DOUTn_CLR(_n1)  HWIO_32_WO
+#define HWN_PINCTRL_DOUTn_CLR(_n1)  PINCTRL_DOUTn
+#define HWI_PINCTRL_DOUTn_CLR(_n1)  (_n1)
+#define HW_PINCTRL_DOUTn_TOG(_n1)   HW(PINCTRL_DOUTn_TOG(_n1))
+#define HWA_PINCTRL_DOUTn_TOG(_n1)  (HWA_PINCTRL_DOUTn(_n1) + 0xc)
+#define HWT_PINCTRL_DOUTn_TOG(_n1)  HWIO_32_WO
+#define HWN_PINCTRL_DOUTn_TOG(_n1)  PINCTRL_DOUTn
+#define HWI_PINCTRL_DOUTn_TOG(_n1)  (_n1)
+#define BP_PINCTRL_DOUTn_BITS       0
+#define BM_PINCTRL_DOUTn_BITS       0xffffffff
+#define BF_PINCTRL_DOUTn_BITS(v)    (((v) & 0xffffffff) << 0)
+#define BFM_PINCTRL_DOUTn_BITS(v)   BM_PINCTRL_DOUTn_BITS
+#define BF_PINCTRL_DOUTn_BITS_V(e)  BF_PINCTRL_DOUTn_BITS(BV_PINCTRL_DOUTn_BITS__##e)
+#define BFM_PINCTRL_DOUTn_BITS_V(v) BM_PINCTRL_DOUTn_BITS
+
+#define HW_PINCTRL_DINn(_n1)        HW(PINCTRL_DINn(_n1))
+#define HWA_PINCTRL_DINn(_n1)       (0x80018000 + 0x60 + (_n1) * 0x100)
+#define HWT_PINCTRL_DINn(_n1)       HWIO_32_RW
+#define HWN_PINCTRL_DINn(_n1)       PINCTRL_DINn
+#define HWI_PINCTRL_DINn(_n1)       (_n1)
+#define HW_PINCTRL_DINn_SET(_n1)    HW(PINCTRL_DINn_SET(_n1))
+#define HWA_PINCTRL_DINn_SET(_n1)   (HWA_PINCTRL_DINn(_n1) + 0x4)
+#define HWT_PINCTRL_DINn_SET(_n1)   HWIO_32_WO
+#define HWN_PINCTRL_DINn_SET(_n1)   PINCTRL_DINn
+#define HWI_PINCTRL_DINn_SET(_n1)   (_n1)
+#define HW_PINCTRL_DINn_CLR(_n1)    HW(PINCTRL_DINn_CLR(_n1))
+#define HWA_PINCTRL_DINn_CLR(_n1)   (HWA_PINCTRL_DINn(_n1) + 0x8)
+#define HWT_PINCTRL_DINn_CLR(_n1)   HWIO_32_WO
+#define HWN_PINCTRL_DINn_CLR(_n1)   PINCTRL_DINn
+#define HWI_PINCTRL_DINn_CLR(_n1)   (_n1)
+#define HW_PINCTRL_DINn_TOG(_n1)    HW(PINCTRL_DINn_TOG(_n1))
+#define HWA_PINCTRL_DINn_TOG(_n1)   (HWA_PINCTRL_DINn(_n1) + 0xc)
+#define HWT_PINCTRL_DINn_TOG(_n1)   HWIO_32_WO
+#define HWN_PINCTRL_DINn_TOG(_n1)   PINCTRL_DINn
+#define HWI_PINCTRL_DINn_TOG(_n1)   (_n1)
+#define BP_PINCTRL_DINn_BITS        0
+#define BM_PINCTRL_DINn_BITS        0xffffffff
+#define BF_PINCTRL_DINn_BITS(v)     (((v) & 0xffffffff) << 0)
+#define BFM_PINCTRL_DINn_BITS(v)    BM_PINCTRL_DINn_BITS
+#define BF_PINCTRL_DINn_BITS_V(e)   BF_PINCTRL_DINn_BITS(BV_PINCTRL_DINn_BITS__##e)
+#define BFM_PINCTRL_DINn_BITS_V(v)  BM_PINCTRL_DINn_BITS
+
+#define HW_PINCTRL_DOEn(_n1)        HW(PINCTRL_DOEn(_n1))
+#define HWA_PINCTRL_DOEn(_n1)       (0x80018000 + 0x70 + (_n1) * 0x100)
+#define HWT_PINCTRL_DOEn(_n1)       HWIO_32_RW
+#define HWN_PINCTRL_DOEn(_n1)       PINCTRL_DOEn
+#define HWI_PINCTRL_DOEn(_n1)       (_n1)
+#define HW_PINCTRL_DOEn_SET(_n1)    HW(PINCTRL_DOEn_SET(_n1))
+#define HWA_PINCTRL_DOEn_SET(_n1)   (HWA_PINCTRL_DOEn(_n1) + 0x4)
+#define HWT_PINCTRL_DOEn_SET(_n1)   HWIO_32_WO
+#define HWN_PINCTRL_DOEn_SET(_n1)   PINCTRL_DOEn
+#define HWI_PINCTRL_DOEn_SET(_n1)   (_n1)
+#define HW_PINCTRL_DOEn_CLR(_n1)    HW(PINCTRL_DOEn_CLR(_n1))
+#define HWA_PINCTRL_DOEn_CLR(_n1)   (HWA_PINCTRL_DOEn(_n1) + 0x8)
+#define HWT_PINCTRL_DOEn_CLR(_n1)   HWIO_32_WO
+#define HWN_PINCTRL_DOEn_CLR(_n1)   PINCTRL_DOEn
+#define HWI_PINCTRL_DOEn_CLR(_n1)   (_n1)
+#define HW_PINCTRL_DOEn_TOG(_n1)    HW(PINCTRL_DOEn_TOG(_n1))
+#define HWA_PINCTRL_DOEn_TOG(_n1)   (HWA_PINCTRL_DOEn(_n1) + 0xc)
+#define HWT_PINCTRL_DOEn_TOG(_n1)   HWIO_32_WO
+#define HWN_PINCTRL_DOEn_TOG(_n1)   PINCTRL_DOEn
+#define HWI_PINCTRL_DOEn_TOG(_n1)   (_n1)
+#define BP_PINCTRL_DOEn_BITS        0
+#define BM_PINCTRL_DOEn_BITS        0xffffffff
+#define BF_PINCTRL_DOEn_BITS(v)     (((v) & 0xffffffff) << 0)
+#define BFM_PINCTRL_DOEn_BITS(v)    BM_PINCTRL_DOEn_BITS
+#define BF_PINCTRL_DOEn_BITS_V(e)   BF_PINCTRL_DOEn_BITS(BV_PINCTRL_DOEn_BITS__##e)
+#define BFM_PINCTRL_DOEn_BITS_V(v)  BM_PINCTRL_DOEn_BITS
+
+#define HW_PINCTRL_PIN2IRQn(_n1)        HW(PINCTRL_PIN2IRQn(_n1))
+#define HWA_PINCTRL_PIN2IRQn(_n1)       (0x80018000 + 0x80 + (_n1) * 0x100)
+#define HWT_PINCTRL_PIN2IRQn(_n1)       HWIO_32_RW
+#define HWN_PINCTRL_PIN2IRQn(_n1)       PINCTRL_PIN2IRQn
+#define HWI_PINCTRL_PIN2IRQn(_n1)       (_n1)
+#define HW_PINCTRL_PIN2IRQn_SET(_n1)    HW(PINCTRL_PIN2IRQn_SET(_n1))
+#define HWA_PINCTRL_PIN2IRQn_SET(_n1)   (HWA_PINCTRL_PIN2IRQn(_n1) + 0x4)
+#define HWT_PINCTRL_PIN2IRQn_SET(_n1)   HWIO_32_WO
+#define HWN_PINCTRL_PIN2IRQn_SET(_n1)   PINCTRL_PIN2IRQn
+#define HWI_PINCTRL_PIN2IRQn_SET(_n1)   (_n1)
+#define HW_PINCTRL_PIN2IRQn_CLR(_n1)    HW(PINCTRL_PIN2IRQn_CLR(_n1))
+#define HWA_PINCTRL_PIN2IRQn_CLR(_n1)   (HWA_PINCTRL_PIN2IRQn(_n1) + 0x8)
+#define HWT_PINCTRL_PIN2IRQn_CLR(_n1)   HWIO_32_WO
+#define HWN_PINCTRL_PIN2IRQn_CLR(_n1)   PINCTRL_PIN2IRQn
+#define HWI_PINCTRL_PIN2IRQn_CLR(_n1)   (_n1)
+#define HW_PINCTRL_PIN2IRQn_TOG(_n1)    HW(PINCTRL_PIN2IRQn_TOG(_n1))
+#define HWA_PINCTRL_PIN2IRQn_TOG(_n1)   (HWA_PINCTRL_PIN2IRQn(_n1) + 0xc)
+#define HWT_PINCTRL_PIN2IRQn_TOG(_n1)   HWIO_32_WO
+#define HWN_PINCTRL_PIN2IRQn_TOG(_n1)   PINCTRL_PIN2IRQn
+#define HWI_PINCTRL_PIN2IRQn_TOG(_n1)   (_n1)
+#define BP_PINCTRL_PIN2IRQn_BITS        0
+#define BM_PINCTRL_PIN2IRQn_BITS        0xffffffff
+#define BF_PINCTRL_PIN2IRQn_BITS(v)     (((v) & 0xffffffff) << 0)
+#define BFM_PINCTRL_PIN2IRQn_BITS(v)    BM_PINCTRL_PIN2IRQn_BITS
+#define BF_PINCTRL_PIN2IRQn_BITS_V(e)   BF_PINCTRL_PIN2IRQn_BITS(BV_PINCTRL_PIN2IRQn_BITS__##e)
+#define BFM_PINCTRL_PIN2IRQn_BITS_V(v)  BM_PINCTRL_PIN2IRQn_BITS
+
+#define HW_PINCTRL_IRQENn(_n1)          HW(PINCTRL_IRQENn(_n1))
+#define HWA_PINCTRL_IRQENn(_n1)         (0x80018000 + 0x90 + (_n1) * 0x100)
+#define HWT_PINCTRL_IRQENn(_n1)         HWIO_32_RW
+#define HWN_PINCTRL_IRQENn(_n1)         PINCTRL_IRQENn
+#define HWI_PINCTRL_IRQENn(_n1)         (_n1)
+#define HW_PINCTRL_IRQENn_SET(_n1)      HW(PINCTRL_IRQENn_SET(_n1))
+#define HWA_PINCTRL_IRQENn_SET(_n1)     (HWA_PINCTRL_IRQENn(_n1) + 0x4)
+#define HWT_PINCTRL_IRQENn_SET(_n1)     HWIO_32_WO
+#define HWN_PINCTRL_IRQENn_SET(_n1)     PINCTRL_IRQENn
+#define HWI_PINCTRL_IRQENn_SET(_n1)     (_n1)
+#define HW_PINCTRL_IRQENn_CLR(_n1)      HW(PINCTRL_IRQENn_CLR(_n1))
+#define HWA_PINCTRL_IRQENn_CLR(_n1)     (HWA_PINCTRL_IRQENn(_n1) + 0x8)
+#define HWT_PINCTRL_IRQENn_CLR(_n1)     HWIO_32_WO
+#define HWN_PINCTRL_IRQENn_CLR(_n1)     PINCTRL_IRQENn
+#define HWI_PINCTRL_IRQENn_CLR(_n1)     (_n1)
+#define HW_PINCTRL_IRQENn_TOG(_n1)      HW(PINCTRL_IRQENn_TOG(_n1))
+#define HWA_PINCTRL_IRQENn_TOG(_n1)     (HWA_PINCTRL_IRQENn(_n1) + 0xc)
+#define HWT_PINCTRL_IRQENn_TOG(_n1)     HWIO_32_WO
+#define HWN_PINCTRL_IRQENn_TOG(_n1)     PINCTRL_IRQENn
+#define HWI_PINCTRL_IRQENn_TOG(_n1)     (_n1)
+#define BP_PINCTRL_IRQENn_BITS          0
+#define BM_PINCTRL_IRQENn_BITS          0xffffffff
+#define BF_PINCTRL_IRQENn_BITS(v)       (((v) & 0xffffffff) << 0)
+#define BFM_PINCTRL_IRQENn_BITS(v)      BM_PINCTRL_IRQENn_BITS
+#define BF_PINCTRL_IRQENn_BITS_V(e)     BF_PINCTRL_IRQENn_BITS(BV_PINCTRL_IRQENn_BITS__##e)
+#define BFM_PINCTRL_IRQENn_BITS_V(v)    BM_PINCTRL_IRQENn_BITS
+
+#define HW_PINCTRL_IRQLEVELn(_n1)       HW(PINCTRL_IRQLEVELn(_n1))
+#define HWA_PINCTRL_IRQLEVELn(_n1)      (0x80018000 + 0xa0 + (_n1) * 0x100)
+#define HWT_PINCTRL_IRQLEVELn(_n1)      HWIO_32_RW
+#define HWN_PINCTRL_IRQLEVELn(_n1)      PINCTRL_IRQLEVELn
+#define HWI_PINCTRL_IRQLEVELn(_n1)      (_n1)
+#define HW_PINCTRL_IRQLEVELn_SET(_n1)   HW(PINCTRL_IRQLEVELn_SET(_n1))
+#define HWA_PINCTRL_IRQLEVELn_SET(_n1)  (HWA_PINCTRL_IRQLEVELn(_n1) + 0x4)
+#define HWT_PINCTRL_IRQLEVELn_SET(_n1)  HWIO_32_WO
+#define HWN_PINCTRL_IRQLEVELn_SET(_n1)  PINCTRL_IRQLEVELn
+#define HWI_PINCTRL_IRQLEVELn_SET(_n1)  (_n1)
+#define HW_PINCTRL_IRQLEVELn_CLR(_n1)   HW(PINCTRL_IRQLEVELn_CLR(_n1))
+#define HWA_PINCTRL_IRQLEVELn_CLR(_n1)  (HWA_PINCTRL_IRQLEVELn(_n1) + 0x8)
+#define HWT_PINCTRL_IRQLEVELn_CLR(_n1)  HWIO_32_WO
+#define HWN_PINCTRL_IRQLEVELn_CLR(_n1)  PINCTRL_IRQLEVELn
+#define HWI_PINCTRL_IRQLEVELn_CLR(_n1)  (_n1)
+#define HW_PINCTRL_IRQLEVELn_TOG(_n1)   HW(PINCTRL_IRQLEVELn_TOG(_n1))
+#define HWA_PINCTRL_IRQLEVELn_TOG(_n1)  (HWA_PINCTRL_IRQLEVELn(_n1) + 0xc)
+#define HWT_PINCTRL_IRQLEVELn_TOG(_n1)  HWIO_32_WO
+#define HWN_PINCTRL_IRQLEVELn_TOG(_n1)  PINCTRL_IRQLEVELn
+#define HWI_PINCTRL_IRQLEVELn_TOG(_n1)  (_n1)
+#define BP_PINCTRL_IRQLEVELn_BITS       0
+#define BM_PINCTRL_IRQLEVELn_BITS       0xffffffff
+#define BF_PINCTRL_IRQLEVELn_BITS(v)    (((v) & 0xffffffff) << 0)
+#define BFM_PINCTRL_IRQLEVELn_BITS(v)   BM_PINCTRL_IRQLEVELn_BITS
+#define BF_PINCTRL_IRQLEVELn_BITS_V(e)  BF_PINCTRL_IRQLEVELn_BITS(BV_PINCTRL_IRQLEVELn_BITS__##e)
+#define BFM_PINCTRL_IRQLEVELn_BITS_V(v) BM_PINCTRL_IRQLEVELn_BITS
+
+#define HW_PINCTRL_IRQPOLn(_n1)         HW(PINCTRL_IRQPOLn(_n1))
+#define HWA_PINCTRL_IRQPOLn(_n1)        (0x80018000 + 0xb0 + (_n1) * 0x100)
+#define HWT_PINCTRL_IRQPOLn(_n1)        HWIO_32_RW
+#define HWN_PINCTRL_IRQPOLn(_n1)        PINCTRL_IRQPOLn
+#define HWI_PINCTRL_IRQPOLn(_n1)        (_n1)
+#define HW_PINCTRL_IRQPOLn_SET(_n1)     HW(PINCTRL_IRQPOLn_SET(_n1))
+#define HWA_PINCTRL_IRQPOLn_SET(_n1)    (HWA_PINCTRL_IRQPOLn(_n1) + 0x4)
+#define HWT_PINCTRL_IRQPOLn_SET(_n1)    HWIO_32_WO
+#define HWN_PINCTRL_IRQPOLn_SET(_n1)    PINCTRL_IRQPOLn
+#define HWI_PINCTRL_IRQPOLn_SET(_n1)    (_n1)
+#define HW_PINCTRL_IRQPOLn_CLR(_n1)     HW(PINCTRL_IRQPOLn_CLR(_n1))
+#define HWA_PINCTRL_IRQPOLn_CLR(_n1)    (HWA_PINCTRL_IRQPOLn(_n1) + 0x8)
+#define HWT_PINCTRL_IRQPOLn_CLR(_n1)    HWIO_32_WO
+#define HWN_PINCTRL_IRQPOLn_CLR(_n1)    PINCTRL_IRQPOLn
+#define HWI_PINCTRL_IRQPOLn_CLR(_n1)    (_n1)
+#define HW_PINCTRL_IRQPOLn_TOG(_n1)     HW(PINCTRL_IRQPOLn_TOG(_n1))
+#define HWA_PINCTRL_IRQPOLn_TOG(_n1)    (HWA_PINCTRL_IRQPOLn(_n1) + 0xc)
+#define HWT_PINCTRL_IRQPOLn_TOG(_n1)    HWIO_32_WO
+#define HWN_PINCTRL_IRQPOLn_TOG(_n1)    PINCTRL_IRQPOLn
+#define HWI_PINCTRL_IRQPOLn_TOG(_n1)    (_n1)
+#define BP_PINCTRL_IRQPOLn_BITS         0
+#define BM_PINCTRL_IRQPOLn_BITS         0xffffffff
+#define BF_PINCTRL_IRQPOLn_BITS(v)      (((v) & 0xffffffff) << 0)
+#define BFM_PINCTRL_IRQPOLn_BITS(v)     BM_PINCTRL_IRQPOLn_BITS
+#define BF_PINCTRL_IRQPOLn_BITS_V(e)    BF_PINCTRL_IRQPOLn_BITS(BV_PINCTRL_IRQPOLn_BITS__##e)
+#define BFM_PINCTRL_IRQPOLn_BITS_V(v)   BM_PINCTRL_IRQPOLn_BITS
+
+#define HW_PINCTRL_IRQSTATn(_n1)        HW(PINCTRL_IRQSTATn(_n1))
+#define HWA_PINCTRL_IRQSTATn(_n1)       (0x80018000 + 0xc0 + (_n1) * 0x100)
+#define HWT_PINCTRL_IRQSTATn(_n1)       HWIO_32_RW
+#define HWN_PINCTRL_IRQSTATn(_n1)       PINCTRL_IRQSTATn
+#define HWI_PINCTRL_IRQSTATn(_n1)       (_n1)
+#define HW_PINCTRL_IRQSTATn_SET(_n1)    HW(PINCTRL_IRQSTATn_SET(_n1))
+#define HWA_PINCTRL_IRQSTATn_SET(_n1)   (HWA_PINCTRL_IRQSTATn(_n1) + 0x4)
+#define HWT_PINCTRL_IRQSTATn_SET(_n1)   HWIO_32_WO
+#define HWN_PINCTRL_IRQSTATn_SET(_n1)   PINCTRL_IRQSTATn
+#define HWI_PINCTRL_IRQSTATn_SET(_n1)   (_n1)
+#define HW_PINCTRL_IRQSTATn_CLR(_n1)    HW(PINCTRL_IRQSTATn_CLR(_n1))
+#define HWA_PINCTRL_IRQSTATn_CLR(_n1)   (HWA_PINCTRL_IRQSTATn(_n1) + 0x8)
+#define HWT_PINCTRL_IRQSTATn_CLR(_n1)   HWIO_32_WO
+#define HWN_PINCTRL_IRQSTATn_CLR(_n1)   PINCTRL_IRQSTATn
+#define HWI_PINCTRL_IRQSTATn_CLR(_n1)   (_n1)
+#define HW_PINCTRL_IRQSTATn_TOG(_n1)    HW(PINCTRL_IRQSTATn_TOG(_n1))
+#define HWA_PINCTRL_IRQSTATn_TOG(_n1)   (HWA_PINCTRL_IRQSTATn(_n1) + 0xc)
+#define HWT_PINCTRL_IRQSTATn_TOG(_n1)   HWIO_32_WO
+#define HWN_PINCTRL_IRQSTATn_TOG(_n1)   PINCTRL_IRQSTATn
+#define HWI_PINCTRL_IRQSTATn_TOG(_n1)   (_n1)
+#define BP_PINCTRL_IRQSTATn_BITS        0
+#define BM_PINCTRL_IRQSTATn_BITS        0xffffffff
+#define BF_PINCTRL_IRQSTATn_BITS(v)     (((v) & 0xffffffff) << 0)
+#define BFM_PINCTRL_IRQSTATn_BITS(v)    BM_PINCTRL_IRQSTATn_BITS
+#define BF_PINCTRL_IRQSTATn_BITS_V(e)   BF_PINCTRL_IRQSTATn_BITS(BV_PINCTRL_IRQSTATn_BITS__##e)
+#define BFM_PINCTRL_IRQSTATn_BITS_V(v)  BM_PINCTRL_IRQSTATn_BITS
+
+#endif /* __HEADERGEN_STMP3600_PINCTRL_H__*/
diff --git a/firmware/target/arm/imx233/regs/stmp3600/power.h b/firmware/target/arm/imx233/regs/stmp3600/power.h
new file mode 100644
index 0000000000..765ff27df3
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3600/power.h
@@ -0,0 +1,892 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * stmp3600 version: 2.4.0
+ * stmp3600 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_STMP3600_POWER_H__
+#define __HEADERGEN_STMP3600_POWER_H__
+
+#define HW_POWER_CTRL                               HW(POWER_CTRL)
+#define HWA_POWER_CTRL                              (0x80044000 + 0x0)
+#define HWT_POWER_CTRL                              HWIO_32_RW
+#define HWN_POWER_CTRL                              POWER_CTRL
+#define HWI_POWER_CTRL                              
+#define HW_POWER_CTRL_SET                           HW(POWER_CTRL_SET)
+#define HWA_POWER_CTRL_SET                          (HWA_POWER_CTRL + 0x4)
+#define HWT_POWER_CTRL_SET                          HWIO_32_WO
+#define HWN_POWER_CTRL_SET                          POWER_CTRL
+#define HWI_POWER_CTRL_SET                          
+#define HW_POWER_CTRL_CLR                           HW(POWER_CTRL_CLR)
+#define HWA_POWER_CTRL_CLR                          (HWA_POWER_CTRL + 0x8)
+#define HWT_POWER_CTRL_CLR                          HWIO_32_WO
+#define HWN_POWER_CTRL_CLR                          POWER_CTRL
+#define HWI_POWER_CTRL_CLR                          
+#define HW_POWER_CTRL_TOG                           HW(POWER_CTRL_TOG)
+#define HWA_POWER_CTRL_TOG                          (HWA_POWER_CTRL + 0xc)
+#define HWT_POWER_CTRL_TOG                          HWIO_32_WO
+#define HWN_POWER_CTRL_TOG                          POWER_CTRL
+#define HWI_POWER_CTRL_TOG                          
+#define BP_POWER_CTRL_CLKGATE                       30
+#define BM_POWER_CTRL_CLKGATE                       0x40000000
+#define BF_POWER_CTRL_CLKGATE(v)                    (((v) & 0x1) << 30)
+#define BFM_POWER_CTRL_CLKGATE(v)                   BM_POWER_CTRL_CLKGATE
+#define BF_POWER_CTRL_CLKGATE_V(e)                  BF_POWER_CTRL_CLKGATE(BV_POWER_CTRL_CLKGATE__##e)
+#define BFM_POWER_CTRL_CLKGATE_V(v)                 BM_POWER_CTRL_CLKGATE
+#define BP_POWER_CTRL_BATT_BO_IRQ                   8
+#define BM_POWER_CTRL_BATT_BO_IRQ                   0x100
+#define BF_POWER_CTRL_BATT_BO_IRQ(v)                (((v) & 0x1) << 8)
+#define BFM_POWER_CTRL_BATT_BO_IRQ(v)               BM_POWER_CTRL_BATT_BO_IRQ
+#define BF_POWER_CTRL_BATT_BO_IRQ_V(e)              BF_POWER_CTRL_BATT_BO_IRQ(BV_POWER_CTRL_BATT_BO_IRQ__##e)
+#define BFM_POWER_CTRL_BATT_BO_IRQ_V(v)             BM_POWER_CTRL_BATT_BO_IRQ
+#define BP_POWER_CTRL_ENIRQBATT_BO                  7
+#define BM_POWER_CTRL_ENIRQBATT_BO                  0x80
+#define BF_POWER_CTRL_ENIRQBATT_BO(v)               (((v) & 0x1) << 7)
+#define BFM_POWER_CTRL_ENIRQBATT_BO(v)              BM_POWER_CTRL_ENIRQBATT_BO
+#define BF_POWER_CTRL_ENIRQBATT_BO_V(e)             BF_POWER_CTRL_ENIRQBATT_BO(BV_POWER_CTRL_ENIRQBATT_BO__##e)
+#define BFM_POWER_CTRL_ENIRQBATT_BO_V(v)            BM_POWER_CTRL_ENIRQBATT_BO
+#define BP_POWER_CTRL_VDDIO_BO_IRQ                  6
+#define BM_POWER_CTRL_VDDIO_BO_IRQ                  0x40
+#define BF_POWER_CTRL_VDDIO_BO_IRQ(v)               (((v) & 0x1) << 6)
+#define BFM_POWER_CTRL_VDDIO_BO_IRQ(v)              BM_POWER_CTRL_VDDIO_BO_IRQ
+#define BF_POWER_CTRL_VDDIO_BO_IRQ_V(e)             BF_POWER_CTRL_VDDIO_BO_IRQ(BV_POWER_CTRL_VDDIO_BO_IRQ__##e)
+#define BFM_POWER_CTRL_VDDIO_BO_IRQ_V(v)            BM_POWER_CTRL_VDDIO_BO_IRQ
+#define BP_POWER_CTRL_ENIRQVDDIO_BO                 5
+#define BM_POWER_CTRL_ENIRQVDDIO_BO                 0x20
+#define BF_POWER_CTRL_ENIRQVDDIO_BO(v)              (((v) & 0x1) << 5)
+#define BFM_POWER_CTRL_ENIRQVDDIO_BO(v)             BM_POWER_CTRL_ENIRQVDDIO_BO
+#define BF_POWER_CTRL_ENIRQVDDIO_BO_V(e)            BF_POWER_CTRL_ENIRQVDDIO_BO(BV_POWER_CTRL_ENIRQVDDIO_BO__##e)
+#define BFM_POWER_CTRL_ENIRQVDDIO_BO_V(v)           BM_POWER_CTRL_ENIRQVDDIO_BO
+#define BP_POWER_CTRL_VDDD_BO_IRQ                   4
+#define BM_POWER_CTRL_VDDD_BO_IRQ                   0x10
+#define BF_POWER_CTRL_VDDD_BO_IRQ(v)                (((v) & 0x1) << 4)
+#define BFM_POWER_CTRL_VDDD_BO_IRQ(v)               BM_POWER_CTRL_VDDD_BO_IRQ
+#define BF_POWER_CTRL_VDDD_BO_IRQ_V(e)              BF_POWER_CTRL_VDDD_BO_IRQ(BV_POWER_CTRL_VDDD_BO_IRQ__##e)
+#define BFM_POWER_CTRL_VDDD_BO_IRQ_V(v)             BM_POWER_CTRL_VDDD_BO_IRQ
+#define BP_POWER_CTRL_ENIRQVDDD_BO                  3
+#define BM_POWER_CTRL_ENIRQVDDD_BO                  0x8
+#define BF_POWER_CTRL_ENIRQVDDD_BO(v)               (((v) & 0x1) << 3)
+#define BFM_POWER_CTRL_ENIRQVDDD_BO(v)              BM_POWER_CTRL_ENIRQVDDD_BO
+#define BF_POWER_CTRL_ENIRQVDDD_BO_V(e)             BF_POWER_CTRL_ENIRQVDDD_BO(BV_POWER_CTRL_ENIRQVDDD_BO__##e)
+#define BFM_POWER_CTRL_ENIRQVDDD_BO_V(v)            BM_POWER_CTRL_ENIRQVDDD_BO
+#define BP_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO       2
+#define BM_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO       0x4
+#define BF_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO(v)    (((v) & 0x1) << 2)
+#define BFM_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO(v)   BM_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO
+#define BF_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO_V(e)  BF_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO(BV_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO__##e)
+#define BFM_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO_V(v) BM_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO
+#define BP_POWER_CTRL_VDD5V_GT_VDDIO_IRQ            1
+#define BM_POWER_CTRL_VDD5V_GT_VDDIO_IRQ            0x2
+#define BF_POWER_CTRL_VDD5V_GT_VDDIO_IRQ(v)         (((v) & 0x1) << 1)
+#define BFM_POWER_CTRL_VDD5V_GT_VDDIO_IRQ(v)        BM_POWER_CTRL_VDD5V_GT_VDDIO_IRQ
+#define BF_POWER_CTRL_VDD5V_GT_VDDIO_IRQ_V(e)       BF_POWER_CTRL_VDD5V_GT_VDDIO_IRQ(BV_POWER_CTRL_VDD5V_GT_VDDIO_IRQ__##e)
+#define BFM_POWER_CTRL_VDD5V_GT_VDDIO_IRQ_V(v)      BM_POWER_CTRL_VDD5V_GT_VDDIO_IRQ
+#define BP_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO          0
+#define BM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO          0x1
+#define BF_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO(v)       (((v) & 0x1) << 0)
+#define BFM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO(v)      BM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO
+#define BF_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO_V(e)     BF_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO(BV_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO__##e)
+#define BFM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO_V(v)    BM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO
+
+#define HW_POWER_5VCTRL                             HW(POWER_5VCTRL)
+#define HWA_POWER_5VCTRL                            (0x80044000 + 0x10)
+#define HWT_POWER_5VCTRL                            HWIO_32_RW
+#define HWN_POWER_5VCTRL                            POWER_5VCTRL
+#define HWI_POWER_5VCTRL                            
+#define HW_POWER_5VCTRL_SET                         HW(POWER_5VCTRL_SET)
+#define HWA_POWER_5VCTRL_SET                        (HWA_POWER_5VCTRL + 0x4)
+#define HWT_POWER_5VCTRL_SET                        HWIO_32_WO
+#define HWN_POWER_5VCTRL_SET                        POWER_5VCTRL
+#define HWI_POWER_5VCTRL_SET                        
+#define HW_POWER_5VCTRL_CLR                         HW(POWER_5VCTRL_CLR)
+#define HWA_POWER_5VCTRL_CLR                        (HWA_POWER_5VCTRL + 0x8)
+#define HWT_POWER_5VCTRL_CLR                        HWIO_32_WO
+#define HWN_POWER_5VCTRL_CLR                        POWER_5VCTRL
+#define HWI_POWER_5VCTRL_CLR                        
+#define HW_POWER_5VCTRL_TOG                         HW(POWER_5VCTRL_TOG)
+#define HWA_POWER_5VCTRL_TOG                        (HWA_POWER_5VCTRL + 0xc)
+#define HWT_POWER_5VCTRL_TOG                        HWIO_32_WO
+#define HWN_POWER_5VCTRL_TOG                        POWER_5VCTRL
+#define HWI_POWER_5VCTRL_TOG                        
+#define BP_POWER_5VCTRL_PWDN_5VBRNOUT               21
+#define BM_POWER_5VCTRL_PWDN_5VBRNOUT               0x200000
+#define BF_POWER_5VCTRL_PWDN_5VBRNOUT(v)            (((v) & 0x1) << 21)
+#define BFM_POWER_5VCTRL_PWDN_5VBRNOUT(v)           BM_POWER_5VCTRL_PWDN_5VBRNOUT
+#define BF_POWER_5VCTRL_PWDN_5VBRNOUT_V(e)          BF_POWER_5VCTRL_PWDN_5VBRNOUT(BV_POWER_5VCTRL_PWDN_5VBRNOUT__##e)
+#define BFM_POWER_5VCTRL_PWDN_5VBRNOUT_V(v)         BM_POWER_5VCTRL_PWDN_5VBRNOUT
+#define BP_POWER_5VCTRL_PWDN_IOBRNOUT               20
+#define BM_POWER_5VCTRL_PWDN_IOBRNOUT               0x100000
+#define BF_POWER_5VCTRL_PWDN_IOBRNOUT(v)            (((v) & 0x1) << 20)
+#define BFM_POWER_5VCTRL_PWDN_IOBRNOUT(v)           BM_POWER_5VCTRL_PWDN_IOBRNOUT
+#define BF_POWER_5VCTRL_PWDN_IOBRNOUT_V(e)          BF_POWER_5VCTRL_PWDN_IOBRNOUT(BV_POWER_5VCTRL_PWDN_IOBRNOUT__##e)
+#define BFM_POWER_5VCTRL_PWDN_IOBRNOUT_V(v)         BM_POWER_5VCTRL_PWDN_IOBRNOUT
+#define BP_POWER_5VCTRL_DISABLE_ILIMIT              19
+#define BM_POWER_5VCTRL_DISABLE_ILIMIT              0x80000
+#define BF_POWER_5VCTRL_DISABLE_ILIMIT(v)           (((v) & 0x1) << 19)
+#define BFM_POWER_5VCTRL_DISABLE_ILIMIT(v)          BM_POWER_5VCTRL_DISABLE_ILIMIT
+#define BF_POWER_5VCTRL_DISABLE_ILIMIT_V(e)         BF_POWER_5VCTRL_DISABLE_ILIMIT(BV_POWER_5VCTRL_DISABLE_ILIMIT__##e)
+#define BFM_POWER_5VCTRL_DISABLE_ILIMIT_V(v)        BM_POWER_5VCTRL_DISABLE_ILIMIT
+#define BP_POWER_5VCTRL_DCDC_XFER                   18
+#define BM_POWER_5VCTRL_DCDC_XFER                   0x40000
+#define BF_POWER_5VCTRL_DCDC_XFER(v)                (((v) & 0x1) << 18)
+#define BFM_POWER_5VCTRL_DCDC_XFER(v)               BM_POWER_5VCTRL_DCDC_XFER
+#define BF_POWER_5VCTRL_DCDC_XFER_V(e)              BF_POWER_5VCTRL_DCDC_XFER(BV_POWER_5VCTRL_DCDC_XFER__##e)
+#define BFM_POWER_5VCTRL_DCDC_XFER_V(v)             BM_POWER_5VCTRL_DCDC_XFER
+#define BP_POWER_5VCTRL_EN_BATT_PULLDN              17
+#define BM_POWER_5VCTRL_EN_BATT_PULLDN              0x20000
+#define BF_POWER_5VCTRL_EN_BATT_PULLDN(v)           (((v) & 0x1) << 17)
+#define BFM_POWER_5VCTRL_EN_BATT_PULLDN(v)          BM_POWER_5VCTRL_EN_BATT_PULLDN
+#define BF_POWER_5VCTRL_EN_BATT_PULLDN_V(e)         BF_POWER_5VCTRL_EN_BATT_PULLDN(BV_POWER_5VCTRL_EN_BATT_PULLDN__##e)
+#define BFM_POWER_5VCTRL_EN_BATT_PULLDN_V(v)        BM_POWER_5VCTRL_EN_BATT_PULLDN
+#define BP_POWER_5VCTRL_VBUSVALID_5VDETECT          16
+#define BM_POWER_5VCTRL_VBUSVALID_5VDETECT          0x10000
+#define BF_POWER_5VCTRL_VBUSVALID_5VDETECT(v)       (((v) & 0x1) << 16)
+#define BFM_POWER_5VCTRL_VBUSVALID_5VDETECT(v)      BM_POWER_5VCTRL_VBUSVALID_5VDETECT
+#define BF_POWER_5VCTRL_VBUSVALID_5VDETECT_V(e)     BF_POWER_5VCTRL_VBUSVALID_5VDETECT(BV_POWER_5VCTRL_VBUSVALID_5VDETECT__##e)
+#define BFM_POWER_5VCTRL_VBUSVALID_5VDETECT_V(v)    BM_POWER_5VCTRL_VBUSVALID_5VDETECT
+#define BP_POWER_5VCTRL_VBUSVALID_TRSH              8
+#define BM_POWER_5VCTRL_VBUSVALID_TRSH              0x300
+#define BF_POWER_5VCTRL_VBUSVALID_TRSH(v)           (((v) & 0x3) << 8)
+#define BFM_POWER_5VCTRL_VBUSVALID_TRSH(v)          BM_POWER_5VCTRL_VBUSVALID_TRSH
+#define BF_POWER_5VCTRL_VBUSVALID_TRSH_V(e)         BF_POWER_5VCTRL_VBUSVALID_TRSH(BV_POWER_5VCTRL_VBUSVALID_TRSH__##e)
+#define BFM_POWER_5VCTRL_VBUSVALID_TRSH_V(v)        BM_POWER_5VCTRL_VBUSVALID_TRSH
+#define BP_POWER_5VCTRL_USB_SUSPEND_I               7
+#define BM_POWER_5VCTRL_USB_SUSPEND_I               0x80
+#define BF_POWER_5VCTRL_USB_SUSPEND_I(v)            (((v) & 0x1) << 7)
+#define BFM_POWER_5VCTRL_USB_SUSPEND_I(v)           BM_POWER_5VCTRL_USB_SUSPEND_I
+#define BF_POWER_5VCTRL_USB_SUSPEND_I_V(e)          BF_POWER_5VCTRL_USB_SUSPEND_I(BV_POWER_5VCTRL_USB_SUSPEND_I__##e)
+#define BFM_POWER_5VCTRL_USB_SUSPEND_I_V(v)         BM_POWER_5VCTRL_USB_SUSPEND_I
+#define BP_POWER_5VCTRL_VBUSVALID_TO_B              6
+#define BM_POWER_5VCTRL_VBUSVALID_TO_B              0x40
+#define BF_POWER_5VCTRL_VBUSVALID_TO_B(v)           (((v) & 0x1) << 6)
+#define BFM_POWER_5VCTRL_VBUSVALID_TO_B(v)          BM_POWER_5VCTRL_VBUSVALID_TO_B
+#define BF_POWER_5VCTRL_VBUSVALID_TO_B_V(e)         BF_POWER_5VCTRL_VBUSVALID_TO_B(BV_POWER_5VCTRL_VBUSVALID_TO_B__##e)
+#define BFM_POWER_5VCTRL_VBUSVALID_TO_B_V(v)        BM_POWER_5VCTRL_VBUSVALID_TO_B
+#define BP_POWER_5VCTRL_ILIMIT_EQ_ZERO              5
+#define BM_POWER_5VCTRL_ILIMIT_EQ_ZERO              0x20
+#define BF_POWER_5VCTRL_ILIMIT_EQ_ZERO(v)           (((v) & 0x1) << 5)
+#define BFM_POWER_5VCTRL_ILIMIT_EQ_ZERO(v)          BM_POWER_5VCTRL_ILIMIT_EQ_ZERO
+#define BF_POWER_5VCTRL_ILIMIT_EQ_ZERO_V(e)         BF_POWER_5VCTRL_ILIMIT_EQ_ZERO(BV_POWER_5VCTRL_ILIMIT_EQ_ZERO__##e)
+#define BFM_POWER_5VCTRL_ILIMIT_EQ_ZERO_V(v)        BM_POWER_5VCTRL_ILIMIT_EQ_ZERO
+#define BP_POWER_5VCTRL_OTG_PWRUP_CMPS              4
+#define BM_POWER_5VCTRL_OTG_PWRUP_CMPS              0x10
+#define BF_POWER_5VCTRL_OTG_PWRUP_CMPS(v)           (((v) & 0x1) << 4)
+#define BFM_POWER_5VCTRL_OTG_PWRUP_CMPS(v)          BM_POWER_5VCTRL_OTG_PWRUP_CMPS
+#define BF_POWER_5VCTRL_OTG_PWRUP_CMPS_V(e)         BF_POWER_5VCTRL_OTG_PWRUP_CMPS(BV_POWER_5VCTRL_OTG_PWRUP_CMPS__##e)
+#define BFM_POWER_5VCTRL_OTG_PWRUP_CMPS_V(v)        BM_POWER_5VCTRL_OTG_PWRUP_CMPS
+#define BP_POWER_5VCTRL_EN_DCDC2                    3
+#define BM_POWER_5VCTRL_EN_DCDC2                    0x8
+#define BF_POWER_5VCTRL_EN_DCDC2(v)                 (((v) & 0x1) << 3)
+#define BFM_POWER_5VCTRL_EN_DCDC2(v)                BM_POWER_5VCTRL_EN_DCDC2
+#define BF_POWER_5VCTRL_EN_DCDC2_V(e)               BF_POWER_5VCTRL_EN_DCDC2(BV_POWER_5VCTRL_EN_DCDC2__##e)
+#define BFM_POWER_5VCTRL_EN_DCDC2_V(v)              BM_POWER_5VCTRL_EN_DCDC2
+#define BP_POWER_5VCTRL_PWD_VDDD_LINREG             2
+#define BM_POWER_5VCTRL_PWD_VDDD_LINREG             0x4
+#define BF_POWER_5VCTRL_PWD_VDDD_LINREG(v)          (((v) & 0x1) << 2)
+#define BFM_POWER_5VCTRL_PWD_VDDD_LINREG(v)         BM_POWER_5VCTRL_PWD_VDDD_LINREG
+#define BF_POWER_5VCTRL_PWD_VDDD_LINREG_V(e)        BF_POWER_5VCTRL_PWD_VDDD_LINREG(BV_POWER_5VCTRL_PWD_VDDD_LINREG__##e)
+#define BFM_POWER_5VCTRL_PWD_VDDD_LINREG_V(v)       BM_POWER_5VCTRL_PWD_VDDD_LINREG
+#define BP_POWER_5VCTRL_EN_DCDC1                    1
+#define BM_POWER_5VCTRL_EN_DCDC1                    0x2
+#define BF_POWER_5VCTRL_EN_DCDC1(v)                 (((v) & 0x1) << 1)
+#define BFM_POWER_5VCTRL_EN_DCDC1(v)                BM_POWER_5VCTRL_EN_DCDC1
+#define BF_POWER_5VCTRL_EN_DCDC1_V(e)               BF_POWER_5VCTRL_EN_DCDC1(BV_POWER_5VCTRL_EN_DCDC1__##e)
+#define BFM_POWER_5VCTRL_EN_DCDC1_V(v)              BM_POWER_5VCTRL_EN_DCDC1
+#define BP_POWER_5VCTRL_LINREG_OFFSET               0
+#define BM_POWER_5VCTRL_LINREG_OFFSET               0x1
+#define BF_POWER_5VCTRL_LINREG_OFFSET(v)            (((v) & 0x1) << 0)
+#define BFM_POWER_5VCTRL_LINREG_OFFSET(v)           BM_POWER_5VCTRL_LINREG_OFFSET
+#define BF_POWER_5VCTRL_LINREG_OFFSET_V(e)          BF_POWER_5VCTRL_LINREG_OFFSET(BV_POWER_5VCTRL_LINREG_OFFSET__##e)
+#define BFM_POWER_5VCTRL_LINREG_OFFSET_V(v)         BM_POWER_5VCTRL_LINREG_OFFSET
+
+#define HW_POWER_MINPWR                         HW(POWER_MINPWR)
+#define HWA_POWER_MINPWR                        (0x80044000 + 0x20)
+#define HWT_POWER_MINPWR                        HWIO_32_RW
+#define HWN_POWER_MINPWR                        POWER_MINPWR
+#define HWI_POWER_MINPWR                        
+#define HW_POWER_MINPWR_SET                     HW(POWER_MINPWR_SET)
+#define HWA_POWER_MINPWR_SET                    (HWA_POWER_MINPWR + 0x4)
+#define HWT_POWER_MINPWR_SET                    HWIO_32_WO
+#define HWN_POWER_MINPWR_SET                    POWER_MINPWR
+#define HWI_POWER_MINPWR_SET                    
+#define HW_POWER_MINPWR_CLR                     HW(POWER_MINPWR_CLR)
+#define HWA_POWER_MINPWR_CLR                    (HWA_POWER_MINPWR + 0x8)
+#define HWT_POWER_MINPWR_CLR                    HWIO_32_WO
+#define HWN_POWER_MINPWR_CLR                    POWER_MINPWR
+#define HWI_POWER_MINPWR_CLR                    
+#define HW_POWER_MINPWR_TOG                     HW(POWER_MINPWR_TOG)
+#define HWA_POWER_MINPWR_TOG                    (HWA_POWER_MINPWR + 0xc)
+#define HWT_POWER_MINPWR_TOG                    HWIO_32_WO
+#define HWN_POWER_MINPWR_TOG                    POWER_MINPWR
+#define HWI_POWER_MINPWR_TOG                    
+#define BP_POWER_MINPWR_TEST_DISCHRG_VBUS       23
+#define BM_POWER_MINPWR_TEST_DISCHRG_VBUS       0x800000
+#define BF_POWER_MINPWR_TEST_DISCHRG_VBUS(v)    (((v) & 0x1) << 23)
+#define BFM_POWER_MINPWR_TEST_DISCHRG_VBUS(v)   BM_POWER_MINPWR_TEST_DISCHRG_VBUS
+#define BF_POWER_MINPWR_TEST_DISCHRG_VBUS_V(e)  BF_POWER_MINPWR_TEST_DISCHRG_VBUS(BV_POWER_MINPWR_TEST_DISCHRG_VBUS__##e)
+#define BFM_POWER_MINPWR_TEST_DISCHRG_VBUS_V(v) BM_POWER_MINPWR_TEST_DISCHRG_VBUS
+#define BP_POWER_MINPWR_TEST_CHRG_VBUS          22
+#define BM_POWER_MINPWR_TEST_CHRG_VBUS          0x400000
+#define BF_POWER_MINPWR_TEST_CHRG_VBUS(v)       (((v) & 0x1) << 22)
+#define BFM_POWER_MINPWR_TEST_CHRG_VBUS(v)      BM_POWER_MINPWR_TEST_CHRG_VBUS
+#define BF_POWER_MINPWR_TEST_CHRG_VBUS_V(e)     BF_POWER_MINPWR_TEST_CHRG_VBUS(BV_POWER_MINPWR_TEST_CHRG_VBUS__##e)
+#define BFM_POWER_MINPWR_TEST_CHRG_VBUS_V(v)    BM_POWER_MINPWR_TEST_CHRG_VBUS
+#define BP_POWER_MINPWR_DC2_TST                 21
+#define BM_POWER_MINPWR_DC2_TST                 0x200000
+#define BF_POWER_MINPWR_DC2_TST(v)              (((v) & 0x1) << 21)
+#define BFM_POWER_MINPWR_DC2_TST(v)             BM_POWER_MINPWR_DC2_TST
+#define BF_POWER_MINPWR_DC2_TST_V(e)            BF_POWER_MINPWR_DC2_TST(BV_POWER_MINPWR_DC2_TST__##e)
+#define BFM_POWER_MINPWR_DC2_TST_V(v)           BM_POWER_MINPWR_DC2_TST
+#define BP_POWER_MINPWR_DC1_TST                 20
+#define BM_POWER_MINPWR_DC1_TST                 0x100000
+#define BF_POWER_MINPWR_DC1_TST(v)              (((v) & 0x1) << 20)
+#define BFM_POWER_MINPWR_DC1_TST(v)             BM_POWER_MINPWR_DC1_TST
+#define BF_POWER_MINPWR_DC1_TST_V(e)            BF_POWER_MINPWR_DC1_TST(BV_POWER_MINPWR_DC1_TST__##e)
+#define BFM_POWER_MINPWR_DC1_TST_V(v)           BM_POWER_MINPWR_DC1_TST
+#define BP_POWER_MINPWR_PERIPHERALSWOFF         19
+#define BM_POWER_MINPWR_PERIPHERALSWOFF         0x80000
+#define BF_POWER_MINPWR_PERIPHERALSWOFF(v)      (((v) & 0x1) << 19)
+#define BFM_POWER_MINPWR_PERIPHERALSWOFF(v)     BM_POWER_MINPWR_PERIPHERALSWOFF
+#define BF_POWER_MINPWR_PERIPHERALSWOFF_V(e)    BF_POWER_MINPWR_PERIPHERALSWOFF(BV_POWER_MINPWR_PERIPHERALSWOFF__##e)
+#define BFM_POWER_MINPWR_PERIPHERALSWOFF_V(v)   BM_POWER_MINPWR_PERIPHERALSWOFF
+#define BP_POWER_MINPWR_TOGGLE_DIF              18
+#define BM_POWER_MINPWR_TOGGLE_DIF              0x40000
+#define BF_POWER_MINPWR_TOGGLE_DIF(v)           (((v) & 0x1) << 18)
+#define BFM_POWER_MINPWR_TOGGLE_DIF(v)          BM_POWER_MINPWR_TOGGLE_DIF
+#define BF_POWER_MINPWR_TOGGLE_DIF_V(e)         BF_POWER_MINPWR_TOGGLE_DIF(BV_POWER_MINPWR_TOGGLE_DIF__##e)
+#define BFM_POWER_MINPWR_TOGGLE_DIF_V(v)        BM_POWER_MINPWR_TOGGLE_DIF
+#define BP_POWER_MINPWR_DISABLE_VDDIOSTEP       17
+#define BM_POWER_MINPWR_DISABLE_VDDIOSTEP       0x20000
+#define BF_POWER_MINPWR_DISABLE_VDDIOSTEP(v)    (((v) & 0x1) << 17)
+#define BFM_POWER_MINPWR_DISABLE_VDDIOSTEP(v)   BM_POWER_MINPWR_DISABLE_VDDIOSTEP
+#define BF_POWER_MINPWR_DISABLE_VDDIOSTEP_V(e)  BF_POWER_MINPWR_DISABLE_VDDIOSTEP(BV_POWER_MINPWR_DISABLE_VDDIOSTEP__##e)
+#define BFM_POWER_MINPWR_DISABLE_VDDIOSTEP_V(v) BM_POWER_MINPWR_DISABLE_VDDIOSTEP
+#define BP_POWER_MINPWR_DISABLE_VDDSTEP         16
+#define BM_POWER_MINPWR_DISABLE_VDDSTEP         0x10000
+#define BF_POWER_MINPWR_DISABLE_VDDSTEP(v)      (((v) & 0x1) << 16)
+#define BFM_POWER_MINPWR_DISABLE_VDDSTEP(v)     BM_POWER_MINPWR_DISABLE_VDDSTEP
+#define BF_POWER_MINPWR_DISABLE_VDDSTEP_V(e)    BF_POWER_MINPWR_DISABLE_VDDSTEP(BV_POWER_MINPWR_DISABLE_VDDSTEP__##e)
+#define BFM_POWER_MINPWR_DISABLE_VDDSTEP_V(v)   BM_POWER_MINPWR_DISABLE_VDDSTEP
+#define BP_POWER_MINPWR_SEL_PLLDIV16CLK         9
+#define BM_POWER_MINPWR_SEL_PLLDIV16CLK         0x200
+#define BF_POWER_MINPWR_SEL_PLLDIV16CLK(v)      (((v) & 0x1) << 9)
+#define BFM_POWER_MINPWR_SEL_PLLDIV16CLK(v)     BM_POWER_MINPWR_SEL_PLLDIV16CLK
+#define BF_POWER_MINPWR_SEL_PLLDIV16CLK_V(e)    BF_POWER_MINPWR_SEL_PLLDIV16CLK(BV_POWER_MINPWR_SEL_PLLDIV16CLK__##e)
+#define BFM_POWER_MINPWR_SEL_PLLDIV16CLK_V(v)   BM_POWER_MINPWR_SEL_PLLDIV16CLK
+#define BP_POWER_MINPWR_PWD_VDDIOBO             8
+#define BM_POWER_MINPWR_PWD_VDDIOBO             0x100
+#define BF_POWER_MINPWR_PWD_VDDIOBO(v)          (((v) & 0x1) << 8)
+#define BFM_POWER_MINPWR_PWD_VDDIOBO(v)         BM_POWER_MINPWR_PWD_VDDIOBO
+#define BF_POWER_MINPWR_PWD_VDDIOBO_V(e)        BF_POWER_MINPWR_PWD_VDDIOBO(BV_POWER_MINPWR_PWD_VDDIOBO__##e)
+#define BFM_POWER_MINPWR_PWD_VDDIOBO_V(v)       BM_POWER_MINPWR_PWD_VDDIOBO
+#define BP_POWER_MINPWR_LESSANA_I               7
+#define BM_POWER_MINPWR_LESSANA_I               0x80
+#define BF_POWER_MINPWR_LESSANA_I(v)            (((v) & 0x1) << 7)
+#define BFM_POWER_MINPWR_LESSANA_I(v)           BM_POWER_MINPWR_LESSANA_I
+#define BF_POWER_MINPWR_LESSANA_I_V(e)          BF_POWER_MINPWR_LESSANA_I(BV_POWER_MINPWR_LESSANA_I__##e)
+#define BFM_POWER_MINPWR_LESSANA_I_V(v)         BM_POWER_MINPWR_LESSANA_I
+#define BP_POWER_MINPWR_DC1_HALFFETS            6
+#define BM_POWER_MINPWR_DC1_HALFFETS            0x40
+#define BF_POWER_MINPWR_DC1_HALFFETS(v)         (((v) & 0x1) << 6)
+#define BFM_POWER_MINPWR_DC1_HALFFETS(v)        BM_POWER_MINPWR_DC1_HALFFETS
+#define BF_POWER_MINPWR_DC1_HALFFETS_V(e)       BF_POWER_MINPWR_DC1_HALFFETS(BV_POWER_MINPWR_DC1_HALFFETS__##e)
+#define BFM_POWER_MINPWR_DC1_HALFFETS_V(v)      BM_POWER_MINPWR_DC1_HALFFETS
+#define BP_POWER_MINPWR_DC2_STOPCLK             5
+#define BM_POWER_MINPWR_DC2_STOPCLK             0x20
+#define BF_POWER_MINPWR_DC2_STOPCLK(v)          (((v) & 0x1) << 5)
+#define BFM_POWER_MINPWR_DC2_STOPCLK(v)         BM_POWER_MINPWR_DC2_STOPCLK
+#define BF_POWER_MINPWR_DC2_STOPCLK_V(e)        BF_POWER_MINPWR_DC2_STOPCLK(BV_POWER_MINPWR_DC2_STOPCLK__##e)
+#define BFM_POWER_MINPWR_DC2_STOPCLK_V(v)       BM_POWER_MINPWR_DC2_STOPCLK
+#define BP_POWER_MINPWR_DC1_STOPCLK             4
+#define BM_POWER_MINPWR_DC1_STOPCLK             0x10
+#define BF_POWER_MINPWR_DC1_STOPCLK(v)          (((v) & 0x1) << 4)
+#define BFM_POWER_MINPWR_DC1_STOPCLK(v)         BM_POWER_MINPWR_DC1_STOPCLK
+#define BF_POWER_MINPWR_DC1_STOPCLK_V(e)        BF_POWER_MINPWR_DC1_STOPCLK(BV_POWER_MINPWR_DC1_STOPCLK__##e)
+#define BFM_POWER_MINPWR_DC1_STOPCLK_V(v)       BM_POWER_MINPWR_DC1_STOPCLK
+#define BP_POWER_MINPWR_EN_DC2_PFM              3
+#define BM_POWER_MINPWR_EN_DC2_PFM              0x8
+#define BF_POWER_MINPWR_EN_DC2_PFM(v)           (((v) & 0x1) << 3)
+#define BFM_POWER_MINPWR_EN_DC2_PFM(v)          BM_POWER_MINPWR_EN_DC2_PFM
+#define BF_POWER_MINPWR_EN_DC2_PFM_V(e)         BF_POWER_MINPWR_EN_DC2_PFM(BV_POWER_MINPWR_EN_DC2_PFM__##e)
+#define BFM_POWER_MINPWR_EN_DC2_PFM_V(v)        BM_POWER_MINPWR_EN_DC2_PFM
+#define BP_POWER_MINPWR_EN_DC1_PFM              2
+#define BM_POWER_MINPWR_EN_DC1_PFM              0x4
+#define BF_POWER_MINPWR_EN_DC1_PFM(v)           (((v) & 0x1) << 2)
+#define BFM_POWER_MINPWR_EN_DC1_PFM(v)          BM_POWER_MINPWR_EN_DC1_PFM
+#define BF_POWER_MINPWR_EN_DC1_PFM_V(e)         BF_POWER_MINPWR_EN_DC1_PFM(BV_POWER_MINPWR_EN_DC1_PFM__##e)
+#define BFM_POWER_MINPWR_EN_DC1_PFM_V(v)        BM_POWER_MINPWR_EN_DC1_PFM
+#define BP_POWER_MINPWR_DC2_HALFCLK             1
+#define BM_POWER_MINPWR_DC2_HALFCLK             0x2
+#define BF_POWER_MINPWR_DC2_HALFCLK(v)          (((v) & 0x1) << 1)
+#define BFM_POWER_MINPWR_DC2_HALFCLK(v)         BM_POWER_MINPWR_DC2_HALFCLK
+#define BF_POWER_MINPWR_DC2_HALFCLK_V(e)        BF_POWER_MINPWR_DC2_HALFCLK(BV_POWER_MINPWR_DC2_HALFCLK__##e)
+#define BFM_POWER_MINPWR_DC2_HALFCLK_V(v)       BM_POWER_MINPWR_DC2_HALFCLK
+#define BP_POWER_MINPWR_DC1_HALFCLK             0
+#define BM_POWER_MINPWR_DC1_HALFCLK             0x1
+#define BF_POWER_MINPWR_DC1_HALFCLK(v)          (((v) & 0x1) << 0)
+#define BFM_POWER_MINPWR_DC1_HALFCLK(v)         BM_POWER_MINPWR_DC1_HALFCLK
+#define BF_POWER_MINPWR_DC1_HALFCLK_V(e)        BF_POWER_MINPWR_DC1_HALFCLK(BV_POWER_MINPWR_DC1_HALFCLK__##e)
+#define BFM_POWER_MINPWR_DC1_HALFCLK_V(v)       BM_POWER_MINPWR_DC1_HALFCLK
+
+#define HW_POWER_BATTCHRG                       HW(POWER_BATTCHRG)
+#define HWA_POWER_BATTCHRG                      (0x80044000 + 0x30)
+#define HWT_POWER_BATTCHRG                      HWIO_32_RW
+#define HWN_POWER_BATTCHRG                      POWER_BATTCHRG
+#define HWI_POWER_BATTCHRG                      
+#define HW_POWER_BATTCHRG_SET                   HW(POWER_BATTCHRG_SET)
+#define HWA_POWER_BATTCHRG_SET                  (HWA_POWER_BATTCHRG + 0x4)
+#define HWT_POWER_BATTCHRG_SET                  HWIO_32_WO
+#define HWN_POWER_BATTCHRG_SET                  POWER_BATTCHRG
+#define HWI_POWER_BATTCHRG_SET                  
+#define HW_POWER_BATTCHRG_CLR                   HW(POWER_BATTCHRG_CLR)
+#define HWA_POWER_BATTCHRG_CLR                  (HWA_POWER_BATTCHRG + 0x8)
+#define HWT_POWER_BATTCHRG_CLR                  HWIO_32_WO
+#define HWN_POWER_BATTCHRG_CLR                  POWER_BATTCHRG
+#define HWI_POWER_BATTCHRG_CLR                  
+#define HW_POWER_BATTCHRG_TOG                   HW(POWER_BATTCHRG_TOG)
+#define HWA_POWER_BATTCHRG_TOG                  (HWA_POWER_BATTCHRG + 0xc)
+#define HWT_POWER_BATTCHRG_TOG                  HWIO_32_WO
+#define HWN_POWER_BATTCHRG_TOG                  POWER_BATTCHRG
+#define HWI_POWER_BATTCHRG_TOG                  
+#define BP_POWER_BATTCHRG_CHRG_STS_OFF          19
+#define BM_POWER_BATTCHRG_CHRG_STS_OFF          0x80000
+#define BF_POWER_BATTCHRG_CHRG_STS_OFF(v)       (((v) & 0x1) << 19)
+#define BFM_POWER_BATTCHRG_CHRG_STS_OFF(v)      BM_POWER_BATTCHRG_CHRG_STS_OFF
+#define BF_POWER_BATTCHRG_CHRG_STS_OFF_V(e)     BF_POWER_BATTCHRG_CHRG_STS_OFF(BV_POWER_BATTCHRG_CHRG_STS_OFF__##e)
+#define BFM_POWER_BATTCHRG_CHRG_STS_OFF_V(v)    BM_POWER_BATTCHRG_CHRG_STS_OFF
+#define BP_POWER_BATTCHRG_LIION_4P1             18
+#define BM_POWER_BATTCHRG_LIION_4P1             0x40000
+#define BF_POWER_BATTCHRG_LIION_4P1(v)          (((v) & 0x1) << 18)
+#define BFM_POWER_BATTCHRG_LIION_4P1(v)         BM_POWER_BATTCHRG_LIION_4P1
+#define BF_POWER_BATTCHRG_LIION_4P1_V(e)        BF_POWER_BATTCHRG_LIION_4P1(BV_POWER_BATTCHRG_LIION_4P1__##e)
+#define BFM_POWER_BATTCHRG_LIION_4P1_V(v)       BM_POWER_BATTCHRG_LIION_4P1
+#define BP_POWER_BATTCHRG_USE_EXTERN_R          17
+#define BM_POWER_BATTCHRG_USE_EXTERN_R          0x20000
+#define BF_POWER_BATTCHRG_USE_EXTERN_R(v)       (((v) & 0x1) << 17)
+#define BFM_POWER_BATTCHRG_USE_EXTERN_R(v)      BM_POWER_BATTCHRG_USE_EXTERN_R
+#define BF_POWER_BATTCHRG_USE_EXTERN_R_V(e)     BF_POWER_BATTCHRG_USE_EXTERN_R(BV_POWER_BATTCHRG_USE_EXTERN_R__##e)
+#define BFM_POWER_BATTCHRG_USE_EXTERN_R_V(v)    BM_POWER_BATTCHRG_USE_EXTERN_R
+#define BP_POWER_BATTCHRG_PWD_BATTCHRG          16
+#define BM_POWER_BATTCHRG_PWD_BATTCHRG          0x10000
+#define BF_POWER_BATTCHRG_PWD_BATTCHRG(v)       (((v) & 0x1) << 16)
+#define BFM_POWER_BATTCHRG_PWD_BATTCHRG(v)      BM_POWER_BATTCHRG_PWD_BATTCHRG
+#define BF_POWER_BATTCHRG_PWD_BATTCHRG_V(e)     BF_POWER_BATTCHRG_PWD_BATTCHRG(BV_POWER_BATTCHRG_PWD_BATTCHRG__##e)
+#define BFM_POWER_BATTCHRG_PWD_BATTCHRG_V(v)    BM_POWER_BATTCHRG_PWD_BATTCHRG
+#define BP_POWER_BATTCHRG_STOP_ILIMIT           8
+#define BM_POWER_BATTCHRG_STOP_ILIMIT           0xf00
+#define BF_POWER_BATTCHRG_STOP_ILIMIT(v)        (((v) & 0xf) << 8)
+#define BFM_POWER_BATTCHRG_STOP_ILIMIT(v)       BM_POWER_BATTCHRG_STOP_ILIMIT
+#define BF_POWER_BATTCHRG_STOP_ILIMIT_V(e)      BF_POWER_BATTCHRG_STOP_ILIMIT(BV_POWER_BATTCHRG_STOP_ILIMIT__##e)
+#define BFM_POWER_BATTCHRG_STOP_ILIMIT_V(v)     BM_POWER_BATTCHRG_STOP_ILIMIT
+#define BP_POWER_BATTCHRG_BATTCHRG_I            0
+#define BM_POWER_BATTCHRG_BATTCHRG_I            0x3f
+#define BF_POWER_BATTCHRG_BATTCHRG_I(v)         (((v) & 0x3f) << 0)
+#define BFM_POWER_BATTCHRG_BATTCHRG_I(v)        BM_POWER_BATTCHRG_BATTCHRG_I
+#define BF_POWER_BATTCHRG_BATTCHRG_I_V(e)       BF_POWER_BATTCHRG_BATTCHRG_I(BV_POWER_BATTCHRG_BATTCHRG_I__##e)
+#define BFM_POWER_BATTCHRG_BATTCHRG_I_V(v)      BM_POWER_BATTCHRG_BATTCHRG_I
+
+#define HW_POWER_VDDCTRL                    HW(POWER_VDDCTRL)
+#define HWA_POWER_VDDCTRL                   (0x80044000 + 0x40)
+#define HWT_POWER_VDDCTRL                   HWIO_32_RW
+#define HWN_POWER_VDDCTRL                   POWER_VDDCTRL
+#define HWI_POWER_VDDCTRL                   
+#define BP_POWER_VDDCTRL_VDDIO_BO           24
+#define BM_POWER_VDDCTRL_VDDIO_BO           0x1f000000
+#define BF_POWER_VDDCTRL_VDDIO_BO(v)        (((v) & 0x1f) << 24)
+#define BFM_POWER_VDDCTRL_VDDIO_BO(v)       BM_POWER_VDDCTRL_VDDIO_BO
+#define BF_POWER_VDDCTRL_VDDIO_BO_V(e)      BF_POWER_VDDCTRL_VDDIO_BO(BV_POWER_VDDCTRL_VDDIO_BO__##e)
+#define BFM_POWER_VDDCTRL_VDDIO_BO_V(v)     BM_POWER_VDDCTRL_VDDIO_BO
+#define BP_POWER_VDDCTRL_VDDIO_TRG          16
+#define BM_POWER_VDDCTRL_VDDIO_TRG          0x1f0000
+#define BF_POWER_VDDCTRL_VDDIO_TRG(v)       (((v) & 0x1f) << 16)
+#define BFM_POWER_VDDCTRL_VDDIO_TRG(v)      BM_POWER_VDDCTRL_VDDIO_TRG
+#define BF_POWER_VDDCTRL_VDDIO_TRG_V(e)     BF_POWER_VDDCTRL_VDDIO_TRG(BV_POWER_VDDCTRL_VDDIO_TRG__##e)
+#define BFM_POWER_VDDCTRL_VDDIO_TRG_V(v)    BM_POWER_VDDCTRL_VDDIO_TRG
+#define BP_POWER_VDDCTRL_VDDD_BO            8
+#define BM_POWER_VDDCTRL_VDDD_BO            0x1f00
+#define BF_POWER_VDDCTRL_VDDD_BO(v)         (((v) & 0x1f) << 8)
+#define BFM_POWER_VDDCTRL_VDDD_BO(v)        BM_POWER_VDDCTRL_VDDD_BO
+#define BF_POWER_VDDCTRL_VDDD_BO_V(e)       BF_POWER_VDDCTRL_VDDD_BO(BV_POWER_VDDCTRL_VDDD_BO__##e)
+#define BFM_POWER_VDDCTRL_VDDD_BO_V(v)      BM_POWER_VDDCTRL_VDDD_BO
+#define BP_POWER_VDDCTRL_VDDD_TRG           0
+#define BM_POWER_VDDCTRL_VDDD_TRG           0x1f
+#define BF_POWER_VDDCTRL_VDDD_TRG(v)        (((v) & 0x1f) << 0)
+#define BFM_POWER_VDDCTRL_VDDD_TRG(v)       BM_POWER_VDDCTRL_VDDD_TRG
+#define BF_POWER_VDDCTRL_VDDD_TRG_V(e)      BF_POWER_VDDCTRL_VDDD_TRG(BV_POWER_VDDCTRL_VDDD_TRG__##e)
+#define BFM_POWER_VDDCTRL_VDDD_TRG_V(v)     BM_POWER_VDDCTRL_VDDD_TRG
+
+#define HW_POWER_DC1MULTOUT                 HW(POWER_DC1MULTOUT)
+#define HWA_POWER_DC1MULTOUT                (0x80044000 + 0x50)
+#define HWT_POWER_DC1MULTOUT                HWIO_32_RW
+#define HWN_POWER_DC1MULTOUT                POWER_DC1MULTOUT
+#define HWI_POWER_DC1MULTOUT                
+#define BP_POWER_DC1MULTOUT_FUNCV           16
+#define BM_POWER_DC1MULTOUT_FUNCV           0x1ff0000
+#define BF_POWER_DC1MULTOUT_FUNCV(v)        (((v) & 0x1ff) << 16)
+#define BFM_POWER_DC1MULTOUT_FUNCV(v)       BM_POWER_DC1MULTOUT_FUNCV
+#define BF_POWER_DC1MULTOUT_FUNCV_V(e)      BF_POWER_DC1MULTOUT_FUNCV(BV_POWER_DC1MULTOUT_FUNCV__##e)
+#define BFM_POWER_DC1MULTOUT_FUNCV_V(v)     BM_POWER_DC1MULTOUT_FUNCV
+#define BP_POWER_DC1MULTOUT_EN_BATADJ       8
+#define BM_POWER_DC1MULTOUT_EN_BATADJ       0x100
+#define BF_POWER_DC1MULTOUT_EN_BATADJ(v)    (((v) & 0x1) << 8)
+#define BFM_POWER_DC1MULTOUT_EN_BATADJ(v)   BM_POWER_DC1MULTOUT_EN_BATADJ
+#define BF_POWER_DC1MULTOUT_EN_BATADJ_V(e)  BF_POWER_DC1MULTOUT_EN_BATADJ(BV_POWER_DC1MULTOUT_EN_BATADJ__##e)
+#define BFM_POWER_DC1MULTOUT_EN_BATADJ_V(v) BM_POWER_DC1MULTOUT_EN_BATADJ
+#define BP_POWER_DC1MULTOUT_ADJTN           0
+#define BM_POWER_DC1MULTOUT_ADJTN           0xf
+#define BF_POWER_DC1MULTOUT_ADJTN(v)        (((v) & 0xf) << 0)
+#define BFM_POWER_DC1MULTOUT_ADJTN(v)       BM_POWER_DC1MULTOUT_ADJTN
+#define BF_POWER_DC1MULTOUT_ADJTN_V(e)      BF_POWER_DC1MULTOUT_ADJTN(BV_POWER_DC1MULTOUT_ADJTN__##e)
+#define BFM_POWER_DC1MULTOUT_ADJTN_V(v)     BM_POWER_DC1MULTOUT_ADJTN
+
+#define HW_POWER_DC1LIMITS                      HW(POWER_DC1LIMITS)
+#define HWA_POWER_DC1LIMITS                     (0x80044000 + 0x60)
+#define HWT_POWER_DC1LIMITS                     HWIO_32_RW
+#define HWN_POWER_DC1LIMITS                     POWER_DC1LIMITS
+#define HWI_POWER_DC1LIMITS                     
+#define BP_POWER_DC1LIMITS_EN_PFETOFF           24
+#define BM_POWER_DC1LIMITS_EN_PFETOFF           0x1000000
+#define BF_POWER_DC1LIMITS_EN_PFETOFF(v)        (((v) & 0x1) << 24)
+#define BFM_POWER_DC1LIMITS_EN_PFETOFF(v)       BM_POWER_DC1LIMITS_EN_PFETOFF
+#define BF_POWER_DC1LIMITS_EN_PFETOFF_V(e)      BF_POWER_DC1LIMITS_EN_PFETOFF(BV_POWER_DC1LIMITS_EN_PFETOFF__##e)
+#define BFM_POWER_DC1LIMITS_EN_PFETOFF_V(v)     BM_POWER_DC1LIMITS_EN_PFETOFF
+#define BP_POWER_DC1LIMITS_POSLIMIT_BOOST       16
+#define BM_POWER_DC1LIMITS_POSLIMIT_BOOST       0x7f0000
+#define BF_POWER_DC1LIMITS_POSLIMIT_BOOST(v)    (((v) & 0x7f) << 16)
+#define BFM_POWER_DC1LIMITS_POSLIMIT_BOOST(v)   BM_POWER_DC1LIMITS_POSLIMIT_BOOST
+#define BF_POWER_DC1LIMITS_POSLIMIT_BOOST_V(e)  BF_POWER_DC1LIMITS_POSLIMIT_BOOST(BV_POWER_DC1LIMITS_POSLIMIT_BOOST__##e)
+#define BFM_POWER_DC1LIMITS_POSLIMIT_BOOST_V(v) BM_POWER_DC1LIMITS_POSLIMIT_BOOST
+#define BP_POWER_DC1LIMITS_POSLIMIT_BUCK        8
+#define BM_POWER_DC1LIMITS_POSLIMIT_BUCK        0x7f00
+#define BF_POWER_DC1LIMITS_POSLIMIT_BUCK(v)     (((v) & 0x7f) << 8)
+#define BFM_POWER_DC1LIMITS_POSLIMIT_BUCK(v)    BM_POWER_DC1LIMITS_POSLIMIT_BUCK
+#define BF_POWER_DC1LIMITS_POSLIMIT_BUCK_V(e)   BF_POWER_DC1LIMITS_POSLIMIT_BUCK(BV_POWER_DC1LIMITS_POSLIMIT_BUCK__##e)
+#define BFM_POWER_DC1LIMITS_POSLIMIT_BUCK_V(v)  BM_POWER_DC1LIMITS_POSLIMIT_BUCK
+#define BP_POWER_DC1LIMITS_NEGLIMIT             0
+#define BM_POWER_DC1LIMITS_NEGLIMIT             0x7f
+#define BF_POWER_DC1LIMITS_NEGLIMIT(v)          (((v) & 0x7f) << 0)
+#define BFM_POWER_DC1LIMITS_NEGLIMIT(v)         BM_POWER_DC1LIMITS_NEGLIMIT
+#define BF_POWER_DC1LIMITS_NEGLIMIT_V(e)        BF_POWER_DC1LIMITS_NEGLIMIT(BV_POWER_DC1LIMITS_NEGLIMIT__##e)
+#define BFM_POWER_DC1LIMITS_NEGLIMIT_V(v)       BM_POWER_DC1LIMITS_NEGLIMIT
+
+#define HW_POWER_DC2LIMITS                      HW(POWER_DC2LIMITS)
+#define HWA_POWER_DC2LIMITS                     (0x80044000 + 0x70)
+#define HWT_POWER_DC2LIMITS                     HWIO_32_RW
+#define HWN_POWER_DC2LIMITS                     POWER_DC2LIMITS
+#define HWI_POWER_DC2LIMITS                     
+#define BP_POWER_DC2LIMITS_EN_BOOST             24
+#define BM_POWER_DC2LIMITS_EN_BOOST             0x1000000
+#define BF_POWER_DC2LIMITS_EN_BOOST(v)          (((v) & 0x1) << 24)
+#define BFM_POWER_DC2LIMITS_EN_BOOST(v)         BM_POWER_DC2LIMITS_EN_BOOST
+#define BF_POWER_DC2LIMITS_EN_BOOST_V(e)        BF_POWER_DC2LIMITS_EN_BOOST(BV_POWER_DC2LIMITS_EN_BOOST__##e)
+#define BFM_POWER_DC2LIMITS_EN_BOOST_V(v)       BM_POWER_DC2LIMITS_EN_BOOST
+#define BP_POWER_DC2LIMITS_POSLIMIT_BOOST       16
+#define BM_POWER_DC2LIMITS_POSLIMIT_BOOST       0x7f0000
+#define BF_POWER_DC2LIMITS_POSLIMIT_BOOST(v)    (((v) & 0x7f) << 16)
+#define BFM_POWER_DC2LIMITS_POSLIMIT_BOOST(v)   BM_POWER_DC2LIMITS_POSLIMIT_BOOST
+#define BF_POWER_DC2LIMITS_POSLIMIT_BOOST_V(e)  BF_POWER_DC2LIMITS_POSLIMIT_BOOST(BV_POWER_DC2LIMITS_POSLIMIT_BOOST__##e)
+#define BFM_POWER_DC2LIMITS_POSLIMIT_BOOST_V(v) BM_POWER_DC2LIMITS_POSLIMIT_BOOST
+#define BP_POWER_DC2LIMITS_POSLIMIT_BUCK        8
+#define BM_POWER_DC2LIMITS_POSLIMIT_BUCK        0x7f00
+#define BF_POWER_DC2LIMITS_POSLIMIT_BUCK(v)     (((v) & 0x7f) << 8)
+#define BFM_POWER_DC2LIMITS_POSLIMIT_BUCK(v)    BM_POWER_DC2LIMITS_POSLIMIT_BUCK
+#define BF_POWER_DC2LIMITS_POSLIMIT_BUCK_V(e)   BF_POWER_DC2LIMITS_POSLIMIT_BUCK(BV_POWER_DC2LIMITS_POSLIMIT_BUCK__##e)
+#define BFM_POWER_DC2LIMITS_POSLIMIT_BUCK_V(v)  BM_POWER_DC2LIMITS_POSLIMIT_BUCK
+#define BP_POWER_DC2LIMITS_NEGLIMIT             0
+#define BM_POWER_DC2LIMITS_NEGLIMIT             0x7f
+#define BF_POWER_DC2LIMITS_NEGLIMIT(v)          (((v) & 0x7f) << 0)
+#define BFM_POWER_DC2LIMITS_NEGLIMIT(v)         BM_POWER_DC2LIMITS_NEGLIMIT
+#define BF_POWER_DC2LIMITS_NEGLIMIT_V(e)        BF_POWER_DC2LIMITS_NEGLIMIT(BV_POWER_DC2LIMITS_NEGLIMIT__##e)
+#define BFM_POWER_DC2LIMITS_NEGLIMIT_V(v)       BM_POWER_DC2LIMITS_NEGLIMIT
+
+#define HW_POWER_LOOPCTRL                       HW(POWER_LOOPCTRL)
+#define HWA_POWER_LOOPCTRL                      (0x80044000 + 0x80)
+#define HWT_POWER_LOOPCTRL                      HWIO_32_RW
+#define HWN_POWER_LOOPCTRL                      POWER_LOOPCTRL
+#define HWI_POWER_LOOPCTRL                      
+#define HW_POWER_LOOPCTRL_SET                   HW(POWER_LOOPCTRL_SET)
+#define HWA_POWER_LOOPCTRL_SET                  (HWA_POWER_LOOPCTRL + 0x4)
+#define HWT_POWER_LOOPCTRL_SET                  HWIO_32_WO
+#define HWN_POWER_LOOPCTRL_SET                  POWER_LOOPCTRL
+#define HWI_POWER_LOOPCTRL_SET                  
+#define HW_POWER_LOOPCTRL_CLR                   HW(POWER_LOOPCTRL_CLR)
+#define HWA_POWER_LOOPCTRL_CLR                  (HWA_POWER_LOOPCTRL + 0x8)
+#define HWT_POWER_LOOPCTRL_CLR                  HWIO_32_WO
+#define HWN_POWER_LOOPCTRL_CLR                  POWER_LOOPCTRL
+#define HWI_POWER_LOOPCTRL_CLR                  
+#define HW_POWER_LOOPCTRL_TOG                   HW(POWER_LOOPCTRL_TOG)
+#define HWA_POWER_LOOPCTRL_TOG                  (HWA_POWER_LOOPCTRL + 0xc)
+#define HWT_POWER_LOOPCTRL_TOG                  HWIO_32_WO
+#define HWN_POWER_LOOPCTRL_TOG                  POWER_LOOPCTRL
+#define HWI_POWER_LOOPCTRL_TOG                  
+#define BP_POWER_LOOPCTRL_TRAN_NOHYST           30
+#define BM_POWER_LOOPCTRL_TRAN_NOHYST           0x40000000
+#define BF_POWER_LOOPCTRL_TRAN_NOHYST(v)        (((v) & 0x1) << 30)
+#define BFM_POWER_LOOPCTRL_TRAN_NOHYST(v)       BM_POWER_LOOPCTRL_TRAN_NOHYST
+#define BF_POWER_LOOPCTRL_TRAN_NOHYST_V(e)      BF_POWER_LOOPCTRL_TRAN_NOHYST(BV_POWER_LOOPCTRL_TRAN_NOHYST__##e)
+#define BFM_POWER_LOOPCTRL_TRAN_NOHYST_V(v)     BM_POWER_LOOPCTRL_TRAN_NOHYST
+#define BP_POWER_LOOPCTRL_HYST_SIGN             29
+#define BM_POWER_LOOPCTRL_HYST_SIGN             0x20000000
+#define BF_POWER_LOOPCTRL_HYST_SIGN(v)          (((v) & 0x1) << 29)
+#define BFM_POWER_LOOPCTRL_HYST_SIGN(v)         BM_POWER_LOOPCTRL_HYST_SIGN
+#define BF_POWER_LOOPCTRL_HYST_SIGN_V(e)        BF_POWER_LOOPCTRL_HYST_SIGN(BV_POWER_LOOPCTRL_HYST_SIGN__##e)
+#define BFM_POWER_LOOPCTRL_HYST_SIGN_V(v)       BM_POWER_LOOPCTRL_HYST_SIGN
+#define BP_POWER_LOOPCTRL_EN_CMP_HYST           28
+#define BM_POWER_LOOPCTRL_EN_CMP_HYST           0x10000000
+#define BF_POWER_LOOPCTRL_EN_CMP_HYST(v)        (((v) & 0x1) << 28)
+#define BFM_POWER_LOOPCTRL_EN_CMP_HYST(v)       BM_POWER_LOOPCTRL_EN_CMP_HYST
+#define BF_POWER_LOOPCTRL_EN_CMP_HYST_V(e)      BF_POWER_LOOPCTRL_EN_CMP_HYST(BV_POWER_LOOPCTRL_EN_CMP_HYST__##e)
+#define BFM_POWER_LOOPCTRL_EN_CMP_HYST_V(v)     BM_POWER_LOOPCTRL_EN_CMP_HYST
+#define BP_POWER_LOOPCTRL_EN_DC2_RCSCALE        27
+#define BM_POWER_LOOPCTRL_EN_DC2_RCSCALE        0x8000000
+#define BF_POWER_LOOPCTRL_EN_DC2_RCSCALE(v)     (((v) & 0x1) << 27)
+#define BFM_POWER_LOOPCTRL_EN_DC2_RCSCALE(v)    BM_POWER_LOOPCTRL_EN_DC2_RCSCALE
+#define BF_POWER_LOOPCTRL_EN_DC2_RCSCALE_V(e)   BF_POWER_LOOPCTRL_EN_DC2_RCSCALE(BV_POWER_LOOPCTRL_EN_DC2_RCSCALE__##e)
+#define BFM_POWER_LOOPCTRL_EN_DC2_RCSCALE_V(v)  BM_POWER_LOOPCTRL_EN_DC2_RCSCALE
+#define BP_POWER_LOOPCTRL_EN_DC1_RCSCALE        26
+#define BM_POWER_LOOPCTRL_EN_DC1_RCSCALE        0x4000000
+#define BF_POWER_LOOPCTRL_EN_DC1_RCSCALE(v)     (((v) & 0x1) << 26)
+#define BFM_POWER_LOOPCTRL_EN_DC1_RCSCALE(v)    BM_POWER_LOOPCTRL_EN_DC1_RCSCALE
+#define BF_POWER_LOOPCTRL_EN_DC1_RCSCALE_V(e)   BF_POWER_LOOPCTRL_EN_DC1_RCSCALE(BV_POWER_LOOPCTRL_EN_DC1_RCSCALE__##e)
+#define BFM_POWER_LOOPCTRL_EN_DC1_RCSCALE_V(v)  BM_POWER_LOOPCTRL_EN_DC1_RCSCALE
+#define BP_POWER_LOOPCTRL_RC_SIGN               25
+#define BM_POWER_LOOPCTRL_RC_SIGN               0x2000000
+#define BF_POWER_LOOPCTRL_RC_SIGN(v)            (((v) & 0x1) << 25)
+#define BFM_POWER_LOOPCTRL_RC_SIGN(v)           BM_POWER_LOOPCTRL_RC_SIGN
+#define BF_POWER_LOOPCTRL_RC_SIGN_V(e)          BF_POWER_LOOPCTRL_RC_SIGN(BV_POWER_LOOPCTRL_RC_SIGN__##e)
+#define BFM_POWER_LOOPCTRL_RC_SIGN_V(v)         BM_POWER_LOOPCTRL_RC_SIGN
+#define BP_POWER_LOOPCTRL_EN_RCSCALE            24
+#define BM_POWER_LOOPCTRL_EN_RCSCALE            0x1000000
+#define BF_POWER_LOOPCTRL_EN_RCSCALE(v)         (((v) & 0x1) << 24)
+#define BFM_POWER_LOOPCTRL_EN_RCSCALE(v)        BM_POWER_LOOPCTRL_EN_RCSCALE
+#define BF_POWER_LOOPCTRL_EN_RCSCALE_V(e)       BF_POWER_LOOPCTRL_EN_RCSCALE(BV_POWER_LOOPCTRL_EN_RCSCALE__##e)
+#define BFM_POWER_LOOPCTRL_EN_RCSCALE_V(v)      BM_POWER_LOOPCTRL_EN_RCSCALE
+#define BP_POWER_LOOPCTRL_DC2_FF                20
+#define BM_POWER_LOOPCTRL_DC2_FF                0x700000
+#define BF_POWER_LOOPCTRL_DC2_FF(v)             (((v) & 0x7) << 20)
+#define BFM_POWER_LOOPCTRL_DC2_FF(v)            BM_POWER_LOOPCTRL_DC2_FF
+#define BF_POWER_LOOPCTRL_DC2_FF_V(e)           BF_POWER_LOOPCTRL_DC2_FF(BV_POWER_LOOPCTRL_DC2_FF__##e)
+#define BFM_POWER_LOOPCTRL_DC2_FF_V(v)          BM_POWER_LOOPCTRL_DC2_FF
+#define BP_POWER_LOOPCTRL_DC2_R                 16
+#define BM_POWER_LOOPCTRL_DC2_R                 0xf0000
+#define BF_POWER_LOOPCTRL_DC2_R(v)              (((v) & 0xf) << 16)
+#define BFM_POWER_LOOPCTRL_DC2_R(v)             BM_POWER_LOOPCTRL_DC2_R
+#define BF_POWER_LOOPCTRL_DC2_R_V(e)            BF_POWER_LOOPCTRL_DC2_R(BV_POWER_LOOPCTRL_DC2_R__##e)
+#define BFM_POWER_LOOPCTRL_DC2_R_V(v)           BM_POWER_LOOPCTRL_DC2_R
+#define BP_POWER_LOOPCTRL_DC2_C                 12
+#define BM_POWER_LOOPCTRL_DC2_C                 0x3000
+#define BF_POWER_LOOPCTRL_DC2_C(v)              (((v) & 0x3) << 12)
+#define BFM_POWER_LOOPCTRL_DC2_C(v)             BM_POWER_LOOPCTRL_DC2_C
+#define BF_POWER_LOOPCTRL_DC2_C_V(e)            BF_POWER_LOOPCTRL_DC2_C(BV_POWER_LOOPCTRL_DC2_C__##e)
+#define BFM_POWER_LOOPCTRL_DC2_C_V(v)           BM_POWER_LOOPCTRL_DC2_C
+#define BP_POWER_LOOPCTRL_DC1_FF                8
+#define BM_POWER_LOOPCTRL_DC1_FF                0x700
+#define BF_POWER_LOOPCTRL_DC1_FF(v)             (((v) & 0x7) << 8)
+#define BFM_POWER_LOOPCTRL_DC1_FF(v)            BM_POWER_LOOPCTRL_DC1_FF
+#define BF_POWER_LOOPCTRL_DC1_FF_V(e)           BF_POWER_LOOPCTRL_DC1_FF(BV_POWER_LOOPCTRL_DC1_FF__##e)
+#define BFM_POWER_LOOPCTRL_DC1_FF_V(v)          BM_POWER_LOOPCTRL_DC1_FF
+#define BP_POWER_LOOPCTRL_DC1_R                 4
+#define BM_POWER_LOOPCTRL_DC1_R                 0xf0
+#define BF_POWER_LOOPCTRL_DC1_R(v)              (((v) & 0xf) << 4)
+#define BFM_POWER_LOOPCTRL_DC1_R(v)             BM_POWER_LOOPCTRL_DC1_R
+#define BF_POWER_LOOPCTRL_DC1_R_V(e)            BF_POWER_LOOPCTRL_DC1_R(BV_POWER_LOOPCTRL_DC1_R__##e)
+#define BFM_POWER_LOOPCTRL_DC1_R_V(v)           BM_POWER_LOOPCTRL_DC1_R
+#define BP_POWER_LOOPCTRL_DC1_C                 0
+#define BM_POWER_LOOPCTRL_DC1_C                 0x3
+#define BF_POWER_LOOPCTRL_DC1_C(v)              (((v) & 0x3) << 0)
+#define BFM_POWER_LOOPCTRL_DC1_C(v)             BM_POWER_LOOPCTRL_DC1_C
+#define BF_POWER_LOOPCTRL_DC1_C_V(e)            BF_POWER_LOOPCTRL_DC1_C(BV_POWER_LOOPCTRL_DC1_C__##e)
+#define BFM_POWER_LOOPCTRL_DC1_C_V(v)           BM_POWER_LOOPCTRL_DC1_C
+
+#define HW_POWER_STS                            HW(POWER_STS)
+#define HWA_POWER_STS                           (0x80044000 + 0x90)
+#define HWT_POWER_STS                           HWIO_32_RW
+#define HWN_POWER_STS                           POWER_STS
+#define HWI_POWER_STS                           
+#define BP_POWER_STS_BATT_CHRG_PRESENT          31
+#define BM_POWER_STS_BATT_CHRG_PRESENT          0x80000000
+#define BF_POWER_STS_BATT_CHRG_PRESENT(v)       (((v) & 0x1) << 31)
+#define BFM_POWER_STS_BATT_CHRG_PRESENT(v)      BM_POWER_STS_BATT_CHRG_PRESENT
+#define BF_POWER_STS_BATT_CHRG_PRESENT_V(e)     BF_POWER_STS_BATT_CHRG_PRESENT(BV_POWER_STS_BATT_CHRG_PRESENT__##e)
+#define BFM_POWER_STS_BATT_CHRG_PRESENT_V(v)    BM_POWER_STS_BATT_CHRG_PRESENT
+#define BP_POWER_STS_MODE                       20
+#define BM_POWER_STS_MODE                       0x300000
+#define BF_POWER_STS_MODE(v)                    (((v) & 0x3) << 20)
+#define BFM_POWER_STS_MODE(v)                   BM_POWER_STS_MODE
+#define BF_POWER_STS_MODE_V(e)                  BF_POWER_STS_MODE(BV_POWER_STS_MODE__##e)
+#define BFM_POWER_STS_MODE_V(v)                 BM_POWER_STS_MODE
+#define BP_POWER_STS_BATT_BO                    16
+#define BM_POWER_STS_BATT_BO                    0x10000
+#define BF_POWER_STS_BATT_BO(v)                 (((v) & 0x1) << 16)
+#define BFM_POWER_STS_BATT_BO(v)                BM_POWER_STS_BATT_BO
+#define BF_POWER_STS_BATT_BO_V(e)               BF_POWER_STS_BATT_BO(BV_POWER_STS_BATT_BO__##e)
+#define BFM_POWER_STS_BATT_BO_V(v)              BM_POWER_STS_BATT_BO
+#define BP_POWER_STS_CHRGSTS                    14
+#define BM_POWER_STS_CHRGSTS                    0x4000
+#define BF_POWER_STS_CHRGSTS(v)                 (((v) & 0x1) << 14)
+#define BFM_POWER_STS_CHRGSTS(v)                BM_POWER_STS_CHRGSTS
+#define BF_POWER_STS_CHRGSTS_V(e)               BF_POWER_STS_CHRGSTS(BV_POWER_STS_CHRGSTS__##e)
+#define BFM_POWER_STS_CHRGSTS_V(v)              BM_POWER_STS_CHRGSTS
+#define BP_POWER_STS_DC2_OK                     13
+#define BM_POWER_STS_DC2_OK                     0x2000
+#define BF_POWER_STS_DC2_OK(v)                  (((v) & 0x1) << 13)
+#define BFM_POWER_STS_DC2_OK(v)                 BM_POWER_STS_DC2_OK
+#define BF_POWER_STS_DC2_OK_V(e)                BF_POWER_STS_DC2_OK(BV_POWER_STS_DC2_OK__##e)
+#define BFM_POWER_STS_DC2_OK_V(v)               BM_POWER_STS_DC2_OK
+#define BP_POWER_STS_DC1_OK                     12
+#define BM_POWER_STS_DC1_OK                     0x1000
+#define BF_POWER_STS_DC1_OK(v)                  (((v) & 0x1) << 12)
+#define BFM_POWER_STS_DC1_OK(v)                 BM_POWER_STS_DC1_OK
+#define BF_POWER_STS_DC1_OK_V(e)                BF_POWER_STS_DC1_OK(BV_POWER_STS_DC1_OK__##e)
+#define BFM_POWER_STS_DC1_OK_V(v)               BM_POWER_STS_DC1_OK
+#define BP_POWER_STS_VDDIO_BO                   9
+#define BM_POWER_STS_VDDIO_BO                   0x200
+#define BF_POWER_STS_VDDIO_BO(v)                (((v) & 0x1) << 9)
+#define BFM_POWER_STS_VDDIO_BO(v)               BM_POWER_STS_VDDIO_BO
+#define BF_POWER_STS_VDDIO_BO_V(e)              BF_POWER_STS_VDDIO_BO(BV_POWER_STS_VDDIO_BO__##e)
+#define BFM_POWER_STS_VDDIO_BO_V(v)             BM_POWER_STS_VDDIO_BO
+#define BP_POWER_STS_VDDD_BO                    8
+#define BM_POWER_STS_VDDD_BO                    0x100
+#define BF_POWER_STS_VDDD_BO(v)                 (((v) & 0x1) << 8)
+#define BFM_POWER_STS_VDDD_BO(v)                BM_POWER_STS_VDDD_BO
+#define BF_POWER_STS_VDDD_BO_V(e)               BF_POWER_STS_VDDD_BO(BV_POWER_STS_VDDD_BO__##e)
+#define BFM_POWER_STS_VDDD_BO_V(v)              BM_POWER_STS_VDDD_BO
+#define BP_POWER_STS_VDD5V_GT_VDDIO             4
+#define BM_POWER_STS_VDD5V_GT_VDDIO             0x10
+#define BF_POWER_STS_VDD5V_GT_VDDIO(v)          (((v) & 0x1) << 4)
+#define BFM_POWER_STS_VDD5V_GT_VDDIO(v)         BM_POWER_STS_VDD5V_GT_VDDIO
+#define BF_POWER_STS_VDD5V_GT_VDDIO_V(e)        BF_POWER_STS_VDD5V_GT_VDDIO(BV_POWER_STS_VDD5V_GT_VDDIO__##e)
+#define BFM_POWER_STS_VDD5V_GT_VDDIO_V(v)       BM_POWER_STS_VDD5V_GT_VDDIO
+#define BP_POWER_STS_AVALID                     3
+#define BM_POWER_STS_AVALID                     0x8
+#define BF_POWER_STS_AVALID(v)                  (((v) & 0x1) << 3)
+#define BFM_POWER_STS_AVALID(v)                 BM_POWER_STS_AVALID
+#define BF_POWER_STS_AVALID_V(e)                BF_POWER_STS_AVALID(BV_POWER_STS_AVALID__##e)
+#define BFM_POWER_STS_AVALID_V(v)               BM_POWER_STS_AVALID
+#define BP_POWER_STS_BVALID                     2
+#define BM_POWER_STS_BVALID                     0x4
+#define BF_POWER_STS_BVALID(v)                  (((v) & 0x1) << 2)
+#define BFM_POWER_STS_BVALID(v)                 BM_POWER_STS_BVALID
+#define BF_POWER_STS_BVALID_V(e)                BF_POWER_STS_BVALID(BV_POWER_STS_BVALID__##e)
+#define BFM_POWER_STS_BVALID_V(v)               BM_POWER_STS_BVALID
+#define BP_POWER_STS_VBUSVALID                  1
+#define BM_POWER_STS_VBUSVALID                  0x2
+#define BF_POWER_STS_VBUSVALID(v)               (((v) & 0x1) << 1)
+#define BFM_POWER_STS_VBUSVALID(v)              BM_POWER_STS_VBUSVALID
+#define BF_POWER_STS_VBUSVALID_V(e)             BF_POWER_STS_VBUSVALID(BV_POWER_STS_VBUSVALID__##e)
+#define BFM_POWER_STS_VBUSVALID_V(v)            BM_POWER_STS_VBUSVALID
+#define BP_POWER_STS_SESSEND                    0
+#define BM_POWER_STS_SESSEND                    0x1
+#define BF_POWER_STS_SESSEND(v)                 (((v) & 0x1) << 0)
+#define BFM_POWER_STS_SESSEND(v)                BM_POWER_STS_SESSEND
+#define BF_POWER_STS_SESSEND_V(e)               BF_POWER_STS_SESSEND(BV_POWER_STS_SESSEND__##e)
+#define BFM_POWER_STS_SESSEND_V(v)              BM_POWER_STS_SESSEND
+
+#define HW_POWER_SPEEDTEMP                  HW(POWER_SPEEDTEMP)
+#define HWA_POWER_SPEEDTEMP                 (0x80044000 + 0xa0)
+#define HWT_POWER_SPEEDTEMP                 HWIO_32_RW
+#define HWN_POWER_SPEEDTEMP                 POWER_SPEEDTEMP
+#define HWI_POWER_SPEEDTEMP                 
+#define HW_POWER_SPEEDTEMP_SET              HW(POWER_SPEEDTEMP_SET)
+#define HWA_POWER_SPEEDTEMP_SET             (HWA_POWER_SPEEDTEMP + 0x4)
+#define HWT_POWER_SPEEDTEMP_SET             HWIO_32_WO
+#define HWN_POWER_SPEEDTEMP_SET             POWER_SPEEDTEMP
+#define HWI_POWER_SPEEDTEMP_SET             
+#define HW_POWER_SPEEDTEMP_CLR              HW(POWER_SPEEDTEMP_CLR)
+#define HWA_POWER_SPEEDTEMP_CLR             (HWA_POWER_SPEEDTEMP + 0x8)
+#define HWT_POWER_SPEEDTEMP_CLR             HWIO_32_WO
+#define HWN_POWER_SPEEDTEMP_CLR             POWER_SPEEDTEMP
+#define HWI_POWER_SPEEDTEMP_CLR             
+#define HW_POWER_SPEEDTEMP_TOG              HW(POWER_SPEEDTEMP_TOG)
+#define HWA_POWER_SPEEDTEMP_TOG             (HWA_POWER_SPEEDTEMP + 0xc)
+#define HWT_POWER_SPEEDTEMP_TOG             HWIO_32_WO
+#define HWN_POWER_SPEEDTEMP_TOG             POWER_SPEEDTEMP
+#define HWI_POWER_SPEEDTEMP_TOG             
+#define BP_POWER_SPEEDTEMP_SPEED_STS1       24
+#define BM_POWER_SPEEDTEMP_SPEED_STS1       0xff000000
+#define BF_POWER_SPEEDTEMP_SPEED_STS1(v)    (((v) & 0xff) << 24)
+#define BFM_POWER_SPEEDTEMP_SPEED_STS1(v)   BM_POWER_SPEEDTEMP_SPEED_STS1
+#define BF_POWER_SPEEDTEMP_SPEED_STS1_V(e)  BF_POWER_SPEEDTEMP_SPEED_STS1(BV_POWER_SPEEDTEMP_SPEED_STS1__##e)
+#define BFM_POWER_SPEEDTEMP_SPEED_STS1_V(v) BM_POWER_SPEEDTEMP_SPEED_STS1
+#define BP_POWER_SPEEDTEMP_SPEED_STS2       16
+#define BM_POWER_SPEEDTEMP_SPEED_STS2       0xff0000
+#define BF_POWER_SPEEDTEMP_SPEED_STS2(v)    (((v) & 0xff) << 16)
+#define BFM_POWER_SPEEDTEMP_SPEED_STS2(v)   BM_POWER_SPEEDTEMP_SPEED_STS2
+#define BF_POWER_SPEEDTEMP_SPEED_STS2_V(e)  BF_POWER_SPEEDTEMP_SPEED_STS2(BV_POWER_SPEEDTEMP_SPEED_STS2__##e)
+#define BFM_POWER_SPEEDTEMP_SPEED_STS2_V(v) BM_POWER_SPEEDTEMP_SPEED_STS2
+#define BP_POWER_SPEEDTEMP_TEMP_STS         8
+#define BM_POWER_SPEEDTEMP_TEMP_STS         0xf00
+#define BF_POWER_SPEEDTEMP_TEMP_STS(v)      (((v) & 0xf) << 8)
+#define BFM_POWER_SPEEDTEMP_TEMP_STS(v)     BM_POWER_SPEEDTEMP_TEMP_STS
+#define BF_POWER_SPEEDTEMP_TEMP_STS_V(e)    BF_POWER_SPEEDTEMP_TEMP_STS(BV_POWER_SPEEDTEMP_TEMP_STS__##e)
+#define BFM_POWER_SPEEDTEMP_TEMP_STS_V(v)   BM_POWER_SPEEDTEMP_TEMP_STS
+#define BP_POWER_SPEEDTEMP_SPEED_CTRL       4
+#define BM_POWER_SPEEDTEMP_SPEED_CTRL       0x30
+#define BF_POWER_SPEEDTEMP_SPEED_CTRL(v)    (((v) & 0x3) << 4)
+#define BFM_POWER_SPEEDTEMP_SPEED_CTRL(v)   BM_POWER_SPEEDTEMP_SPEED_CTRL
+#define BF_POWER_SPEEDTEMP_SPEED_CTRL_V(e)  BF_POWER_SPEEDTEMP_SPEED_CTRL(BV_POWER_SPEEDTEMP_SPEED_CTRL__##e)
+#define BFM_POWER_SPEEDTEMP_SPEED_CTRL_V(v) BM_POWER_SPEEDTEMP_SPEED_CTRL
+#define BP_POWER_SPEEDTEMP_TEMP_CTRL        0
+#define BM_POWER_SPEEDTEMP_TEMP_CTRL        0xf
+#define BF_POWER_SPEEDTEMP_TEMP_CTRL(v)     (((v) & 0xf) << 0)
+#define BFM_POWER_SPEEDTEMP_TEMP_CTRL(v)    BM_POWER_SPEEDTEMP_TEMP_CTRL
+#define BF_POWER_SPEEDTEMP_TEMP_CTRL_V(e)   BF_POWER_SPEEDTEMP_TEMP_CTRL(BV_POWER_SPEEDTEMP_TEMP_CTRL__##e)
+#define BFM_POWER_SPEEDTEMP_TEMP_CTRL_V(v)  BM_POWER_SPEEDTEMP_TEMP_CTRL
+
+#define HW_POWER_BATTMONITOR                        HW(POWER_BATTMONITOR)
+#define HWA_POWER_BATTMONITOR                       (0x80044000 + 0xb0)
+#define HWT_POWER_BATTMONITOR                       HWIO_32_RW
+#define HWN_POWER_BATTMONITOR                       POWER_BATTMONITOR
+#define HWI_POWER_BATTMONITOR                       
+#define BP_POWER_BATTMONITOR_BATT_VAL               16
+#define BM_POWER_BATTMONITOR_BATT_VAL               0x3ff0000
+#define BF_POWER_BATTMONITOR_BATT_VAL(v)            (((v) & 0x3ff) << 16)
+#define BFM_POWER_BATTMONITOR_BATT_VAL(v)           BM_POWER_BATTMONITOR_BATT_VAL
+#define BF_POWER_BATTMONITOR_BATT_VAL_V(e)          BF_POWER_BATTMONITOR_BATT_VAL(BV_POWER_BATTMONITOR_BATT_VAL__##e)
+#define BFM_POWER_BATTMONITOR_BATT_VAL_V(v)         BM_POWER_BATTMONITOR_BATT_VAL
+#define BP_POWER_BATTMONITOR_PWDN_BATTBRNOUT        9
+#define BM_POWER_BATTMONITOR_PWDN_BATTBRNOUT        0x200
+#define BF_POWER_BATTMONITOR_PWDN_BATTBRNOUT(v)     (((v) & 0x1) << 9)
+#define BFM_POWER_BATTMONITOR_PWDN_BATTBRNOUT(v)    BM_POWER_BATTMONITOR_PWDN_BATTBRNOUT
+#define BF_POWER_BATTMONITOR_PWDN_BATTBRNOUT_V(e)   BF_POWER_BATTMONITOR_PWDN_BATTBRNOUT(BV_POWER_BATTMONITOR_PWDN_BATTBRNOUT__##e)
+#define BFM_POWER_BATTMONITOR_PWDN_BATTBRNOUT_V(v)  BM_POWER_BATTMONITOR_PWDN_BATTBRNOUT
+#define BP_POWER_BATTMONITOR_BRWNOUT_PWD            8
+#define BM_POWER_BATTMONITOR_BRWNOUT_PWD            0x100
+#define BF_POWER_BATTMONITOR_BRWNOUT_PWD(v)         (((v) & 0x1) << 8)
+#define BFM_POWER_BATTMONITOR_BRWNOUT_PWD(v)        BM_POWER_BATTMONITOR_BRWNOUT_PWD
+#define BF_POWER_BATTMONITOR_BRWNOUT_PWD_V(e)       BF_POWER_BATTMONITOR_BRWNOUT_PWD(BV_POWER_BATTMONITOR_BRWNOUT_PWD__##e)
+#define BFM_POWER_BATTMONITOR_BRWNOUT_PWD_V(v)      BM_POWER_BATTMONITOR_BRWNOUT_PWD
+#define BP_POWER_BATTMONITOR_BRWNOUT_LVL            0
+#define BM_POWER_BATTMONITOR_BRWNOUT_LVL            0xf
+#define BF_POWER_BATTMONITOR_BRWNOUT_LVL(v)         (((v) & 0xf) << 0)
+#define BFM_POWER_BATTMONITOR_BRWNOUT_LVL(v)        BM_POWER_BATTMONITOR_BRWNOUT_LVL
+#define BF_POWER_BATTMONITOR_BRWNOUT_LVL_V(e)       BF_POWER_BATTMONITOR_BRWNOUT_LVL(BV_POWER_BATTMONITOR_BRWNOUT_LVL__##e)
+#define BFM_POWER_BATTMONITOR_BRWNOUT_LVL_V(v)      BM_POWER_BATTMONITOR_BRWNOUT_LVL
+
+#define HW_POWER_RESET                  HW(POWER_RESET)
+#define HWA_POWER_RESET                 (0x80044000 + 0xc0)
+#define HWT_POWER_RESET                 HWIO_32_RW
+#define HWN_POWER_RESET                 POWER_RESET
+#define HWI_POWER_RESET                 
+#define HW_POWER_RESET_SET              HW(POWER_RESET_SET)
+#define HWA_POWER_RESET_SET             (HWA_POWER_RESET + 0x4)
+#define HWT_POWER_RESET_SET             HWIO_32_WO
+#define HWN_POWER_RESET_SET             POWER_RESET
+#define HWI_POWER_RESET_SET             
+#define HW_POWER_RESET_CLR              HW(POWER_RESET_CLR)
+#define HWA_POWER_RESET_CLR             (HWA_POWER_RESET + 0x8)
+#define HWT_POWER_RESET_CLR             HWIO_32_WO
+#define HWN_POWER_RESET_CLR             POWER_RESET
+#define HWI_POWER_RESET_CLR             
+#define HW_POWER_RESET_TOG              HW(POWER_RESET_TOG)
+#define HWA_POWER_RESET_TOG             (HWA_POWER_RESET + 0xc)
+#define HWT_POWER_RESET_TOG             HWIO_32_WO
+#define HWN_POWER_RESET_TOG             POWER_RESET
+#define HWI_POWER_RESET_TOG             
+#define BP_POWER_RESET_UNLOCK           16
+#define BM_POWER_RESET_UNLOCK           0xffff0000
+#define BV_POWER_RESET_UNLOCK__KEY      0x3e77
+#define BF_POWER_RESET_UNLOCK(v)        (((v) & 0xffff) << 16)
+#define BFM_POWER_RESET_UNLOCK(v)       BM_POWER_RESET_UNLOCK
+#define BF_POWER_RESET_UNLOCK_V(e)      BF_POWER_RESET_UNLOCK(BV_POWER_RESET_UNLOCK__##e)
+#define BFM_POWER_RESET_UNLOCK_V(v)     BM_POWER_RESET_UNLOCK
+#define BP_POWER_RESET_PWD_OFF          4
+#define BM_POWER_RESET_PWD_OFF          0x10
+#define BF_POWER_RESET_PWD_OFF(v)       (((v) & 0x1) << 4)
+#define BFM_POWER_RESET_PWD_OFF(v)      BM_POWER_RESET_PWD_OFF
+#define BF_POWER_RESET_PWD_OFF_V(e)     BF_POWER_RESET_PWD_OFF(BV_POWER_RESET_PWD_OFF__##e)
+#define BFM_POWER_RESET_PWD_OFF_V(v)    BM_POWER_RESET_PWD_OFF
+#define BP_POWER_RESET_POR              3
+#define BM_POWER_RESET_POR              0x8
+#define BF_POWER_RESET_POR(v)           (((v) & 0x1) << 3)
+#define BFM_POWER_RESET_POR(v)          BM_POWER_RESET_POR
+#define BF_POWER_RESET_POR_V(e)         BF_POWER_RESET_POR(BV_POWER_RESET_POR__##e)
+#define BFM_POWER_RESET_POR_V(v)        BM_POWER_RESET_POR
+#define BP_POWER_RESET_PWD              2
+#define BM_POWER_RESET_PWD              0x4
+#define BF_POWER_RESET_PWD(v)           (((v) & 0x1) << 2)
+#define BFM_POWER_RESET_PWD(v)          BM_POWER_RESET_PWD
+#define BF_POWER_RESET_PWD_V(e)         BF_POWER_RESET_PWD(BV_POWER_RESET_PWD__##e)
+#define BFM_POWER_RESET_PWD_V(v)        BM_POWER_RESET_PWD
+#define BP_POWER_RESET_RST_DIG          1
+#define BM_POWER_RESET_RST_DIG          0x2
+#define BF_POWER_RESET_RST_DIG(v)       (((v) & 0x1) << 1)
+#define BFM_POWER_RESET_RST_DIG(v)      BM_POWER_RESET_RST_DIG
+#define BF_POWER_RESET_RST_DIG_V(e)     BF_POWER_RESET_RST_DIG(BV_POWER_RESET_RST_DIG__##e)
+#define BFM_POWER_RESET_RST_DIG_V(v)    BM_POWER_RESET_RST_DIG
+#define BP_POWER_RESET_RST_ALL          0
+#define BM_POWER_RESET_RST_ALL          0x1
+#define BF_POWER_RESET_RST_ALL(v)       (((v) & 0x1) << 0)
+#define BFM_POWER_RESET_RST_ALL(v)      BM_POWER_RESET_RST_ALL
+#define BF_POWER_RESET_RST_ALL_V(e)     BF_POWER_RESET_RST_ALL(BV_POWER_RESET_RST_ALL__##e)
+#define BFM_POWER_RESET_RST_ALL_V(v)    BM_POWER_RESET_RST_ALL
+
+#define HW_POWER_DEBUG                          HW(POWER_DEBUG)
+#define HWA_POWER_DEBUG                         (0x80044000 + 0xd0)
+#define HWT_POWER_DEBUG                         HWIO_32_RW
+#define HWN_POWER_DEBUG                         POWER_DEBUG
+#define HWI_POWER_DEBUG                         
+#define HW_POWER_DEBUG_SET                      HW(POWER_DEBUG_SET)
+#define HWA_POWER_DEBUG_SET                     (HWA_POWER_DEBUG + 0x4)
+#define HWT_POWER_DEBUG_SET                     HWIO_32_WO
+#define HWN_POWER_DEBUG_SET                     POWER_DEBUG
+#define HWI_POWER_DEBUG_SET                     
+#define HW_POWER_DEBUG_CLR                      HW(POWER_DEBUG_CLR)
+#define HWA_POWER_DEBUG_CLR                     (HWA_POWER_DEBUG + 0x8)
+#define HWT_POWER_DEBUG_CLR                     HWIO_32_WO
+#define HWN_POWER_DEBUG_CLR                     POWER_DEBUG
+#define HWI_POWER_DEBUG_CLR                     
+#define HW_POWER_DEBUG_TOG                      HW(POWER_DEBUG_TOG)
+#define HWA_POWER_DEBUG_TOG                     (HWA_POWER_DEBUG + 0xc)
+#define HWT_POWER_DEBUG_TOG                     HWIO_32_WO
+#define HWN_POWER_DEBUG_TOG                     POWER_DEBUG
+#define HWI_POWER_DEBUG_TOG                     
+#define BP_POWER_DEBUG_ENCTRLVBUS               4
+#define BM_POWER_DEBUG_ENCTRLVBUS               0x10
+#define BF_POWER_DEBUG_ENCTRLVBUS(v)            (((v) & 0x1) << 4)
+#define BFM_POWER_DEBUG_ENCTRLVBUS(v)           BM_POWER_DEBUG_ENCTRLVBUS
+#define BF_POWER_DEBUG_ENCTRLVBUS_V(e)          BF_POWER_DEBUG_ENCTRLVBUS(BV_POWER_DEBUG_ENCTRLVBUS__##e)
+#define BFM_POWER_DEBUG_ENCTRLVBUS_V(v)         BM_POWER_DEBUG_ENCTRLVBUS
+#define BP_POWER_DEBUG_VBUSVALIDPIOLOCK         3
+#define BM_POWER_DEBUG_VBUSVALIDPIOLOCK         0x8
+#define BF_POWER_DEBUG_VBUSVALIDPIOLOCK(v)      (((v) & 0x1) << 3)
+#define BFM_POWER_DEBUG_VBUSVALIDPIOLOCK(v)     BM_POWER_DEBUG_VBUSVALIDPIOLOCK
+#define BF_POWER_DEBUG_VBUSVALIDPIOLOCK_V(e)    BF_POWER_DEBUG_VBUSVALIDPIOLOCK(BV_POWER_DEBUG_VBUSVALIDPIOLOCK__##e)
+#define BFM_POWER_DEBUG_VBUSVALIDPIOLOCK_V(v)   BM_POWER_DEBUG_VBUSVALIDPIOLOCK
+#define BP_POWER_DEBUG_AVALIDPIOLOCK            2
+#define BM_POWER_DEBUG_AVALIDPIOLOCK            0x4
+#define BF_POWER_DEBUG_AVALIDPIOLOCK(v)         (((v) & 0x1) << 2)
+#define BFM_POWER_DEBUG_AVALIDPIOLOCK(v)        BM_POWER_DEBUG_AVALIDPIOLOCK
+#define BF_POWER_DEBUG_AVALIDPIOLOCK_V(e)       BF_POWER_DEBUG_AVALIDPIOLOCK(BV_POWER_DEBUG_AVALIDPIOLOCK__##e)
+#define BFM_POWER_DEBUG_AVALIDPIOLOCK_V(v)      BM_POWER_DEBUG_AVALIDPIOLOCK
+#define BP_POWER_DEBUG_BVALIDPIOLOCK            1
+#define BM_POWER_DEBUG_BVALIDPIOLOCK            0x2
+#define BF_POWER_DEBUG_BVALIDPIOLOCK(v)         (((v) & 0x1) << 1)
+#define BFM_POWER_DEBUG_BVALIDPIOLOCK(v)        BM_POWER_DEBUG_BVALIDPIOLOCK
+#define BF_POWER_DEBUG_BVALIDPIOLOCK_V(e)       BF_POWER_DEBUG_BVALIDPIOLOCK(BV_POWER_DEBUG_BVALIDPIOLOCK__##e)
+#define BFM_POWER_DEBUG_BVALIDPIOLOCK_V(v)      BM_POWER_DEBUG_BVALIDPIOLOCK
+#define BP_POWER_DEBUG_SESSENDPIOLOCK           0
+#define BM_POWER_DEBUG_SESSENDPIOLOCK           0x1
+#define BF_POWER_DEBUG_SESSENDPIOLOCK(v)        (((v) & 0x1) << 0)
+#define BFM_POWER_DEBUG_SESSENDPIOLOCK(v)       BM_POWER_DEBUG_SESSENDPIOLOCK
+#define BF_POWER_DEBUG_SESSENDPIOLOCK_V(e)      BF_POWER_DEBUG_SESSENDPIOLOCK(BV_POWER_DEBUG_SESSENDPIOLOCK__##e)
+#define BFM_POWER_DEBUG_SESSENDPIOLOCK_V(v)     BM_POWER_DEBUG_SESSENDPIOLOCK
+
+#endif /* __HEADERGEN_STMP3600_POWER_H__*/
diff --git a/firmware/target/arm/imx233/regs/stmp3600/pwm.h b/firmware/target/arm/imx233/regs/stmp3600/pwm.h
new file mode 100644
index 0000000000..5f569df160
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3600/pwm.h
@@ -0,0 +1,218 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * stmp3600 version: 2.4.0
+ * stmp3600 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_STMP3600_PWM_H__
+#define __HEADERGEN_STMP3600_PWM_H__
+
+#define HW_PWM_CTRL                     HW(PWM_CTRL)
+#define HWA_PWM_CTRL                    (0x80064000 + 0x0)
+#define HWT_PWM_CTRL                    HWIO_32_RW
+#define HWN_PWM_CTRL                    PWM_CTRL
+#define HWI_PWM_CTRL                    
+#define HW_PWM_CTRL_SET                 HW(PWM_CTRL_SET)
+#define HWA_PWM_CTRL_SET                (HWA_PWM_CTRL + 0x4)
+#define HWT_PWM_CTRL_SET                HWIO_32_WO
+#define HWN_PWM_CTRL_SET                PWM_CTRL
+#define HWI_PWM_CTRL_SET                
+#define HW_PWM_CTRL_CLR                 HW(PWM_CTRL_CLR)
+#define HWA_PWM_CTRL_CLR                (HWA_PWM_CTRL + 0x8)
+#define HWT_PWM_CTRL_CLR                HWIO_32_WO
+#define HWN_PWM_CTRL_CLR                PWM_CTRL
+#define HWI_PWM_CTRL_CLR                
+#define HW_PWM_CTRL_TOG                 HW(PWM_CTRL_TOG)
+#define HWA_PWM_CTRL_TOG                (HWA_PWM_CTRL + 0xc)
+#define HWT_PWM_CTRL_TOG                HWIO_32_WO
+#define HWN_PWM_CTRL_TOG                PWM_CTRL
+#define HWI_PWM_CTRL_TOG                
+#define BP_PWM_CTRL_SFTRST              31
+#define BM_PWM_CTRL_SFTRST              0x80000000
+#define BF_PWM_CTRL_SFTRST(v)           (((v) & 0x1) << 31)
+#define BFM_PWM_CTRL_SFTRST(v)          BM_PWM_CTRL_SFTRST
+#define BF_PWM_CTRL_SFTRST_V(e)         BF_PWM_CTRL_SFTRST(BV_PWM_CTRL_SFTRST__##e)
+#define BFM_PWM_CTRL_SFTRST_V(v)        BM_PWM_CTRL_SFTRST
+#define BP_PWM_CTRL_CLKGATE             30
+#define BM_PWM_CTRL_CLKGATE             0x40000000
+#define BF_PWM_CTRL_CLKGATE(v)          (((v) & 0x1) << 30)
+#define BFM_PWM_CTRL_CLKGATE(v)         BM_PWM_CTRL_CLKGATE
+#define BF_PWM_CTRL_CLKGATE_V(e)        BF_PWM_CTRL_CLKGATE(BV_PWM_CTRL_CLKGATE__##e)
+#define BFM_PWM_CTRL_CLKGATE_V(v)       BM_PWM_CTRL_CLKGATE
+#define BP_PWM_CTRL_PWM4_PRESENT        29
+#define BM_PWM_CTRL_PWM4_PRESENT        0x20000000
+#define BF_PWM_CTRL_PWM4_PRESENT(v)     (((v) & 0x1) << 29)
+#define BFM_PWM_CTRL_PWM4_PRESENT(v)    BM_PWM_CTRL_PWM4_PRESENT
+#define BF_PWM_CTRL_PWM4_PRESENT_V(e)   BF_PWM_CTRL_PWM4_PRESENT(BV_PWM_CTRL_PWM4_PRESENT__##e)
+#define BFM_PWM_CTRL_PWM4_PRESENT_V(v)  BM_PWM_CTRL_PWM4_PRESENT
+#define BP_PWM_CTRL_PWM3_PRESENT        28
+#define BM_PWM_CTRL_PWM3_PRESENT        0x10000000
+#define BF_PWM_CTRL_PWM3_PRESENT(v)     (((v) & 0x1) << 28)
+#define BFM_PWM_CTRL_PWM3_PRESENT(v)    BM_PWM_CTRL_PWM3_PRESENT
+#define BF_PWM_CTRL_PWM3_PRESENT_V(e)   BF_PWM_CTRL_PWM3_PRESENT(BV_PWM_CTRL_PWM3_PRESENT__##e)
+#define BFM_PWM_CTRL_PWM3_PRESENT_V(v)  BM_PWM_CTRL_PWM3_PRESENT
+#define BP_PWM_CTRL_PWM2_PRESENT        27
+#define BM_PWM_CTRL_PWM2_PRESENT        0x8000000
+#define BF_PWM_CTRL_PWM2_PRESENT(v)     (((v) & 0x1) << 27)
+#define BFM_PWM_CTRL_PWM2_PRESENT(v)    BM_PWM_CTRL_PWM2_PRESENT
+#define BF_PWM_CTRL_PWM2_PRESENT_V(e)   BF_PWM_CTRL_PWM2_PRESENT(BV_PWM_CTRL_PWM2_PRESENT__##e)
+#define BFM_PWM_CTRL_PWM2_PRESENT_V(v)  BM_PWM_CTRL_PWM2_PRESENT
+#define BP_PWM_CTRL_PWM1_PRESENT        26
+#define BM_PWM_CTRL_PWM1_PRESENT        0x4000000
+#define BF_PWM_CTRL_PWM1_PRESENT(v)     (((v) & 0x1) << 26)
+#define BFM_PWM_CTRL_PWM1_PRESENT(v)    BM_PWM_CTRL_PWM1_PRESENT
+#define BF_PWM_CTRL_PWM1_PRESENT_V(e)   BF_PWM_CTRL_PWM1_PRESENT(BV_PWM_CTRL_PWM1_PRESENT__##e)
+#define BFM_PWM_CTRL_PWM1_PRESENT_V(v)  BM_PWM_CTRL_PWM1_PRESENT
+#define BP_PWM_CTRL_PWM0_PRESENT        25
+#define BM_PWM_CTRL_PWM0_PRESENT        0x2000000
+#define BF_PWM_CTRL_PWM0_PRESENT(v)     (((v) & 0x1) << 25)
+#define BFM_PWM_CTRL_PWM0_PRESENT(v)    BM_PWM_CTRL_PWM0_PRESENT
+#define BF_PWM_CTRL_PWM0_PRESENT_V(e)   BF_PWM_CTRL_PWM0_PRESENT(BV_PWM_CTRL_PWM0_PRESENT__##e)
+#define BFM_PWM_CTRL_PWM0_PRESENT_V(v)  BM_PWM_CTRL_PWM0_PRESENT
+#define BP_PWM_CTRL_PWM4_ENABLE         4
+#define BM_PWM_CTRL_PWM4_ENABLE         0x10
+#define BF_PWM_CTRL_PWM4_ENABLE(v)      (((v) & 0x1) << 4)
+#define BFM_PWM_CTRL_PWM4_ENABLE(v)     BM_PWM_CTRL_PWM4_ENABLE
+#define BF_PWM_CTRL_PWM4_ENABLE_V(e)    BF_PWM_CTRL_PWM4_ENABLE(BV_PWM_CTRL_PWM4_ENABLE__##e)
+#define BFM_PWM_CTRL_PWM4_ENABLE_V(v)   BM_PWM_CTRL_PWM4_ENABLE
+#define BP_PWM_CTRL_PWM3_ENABLE         3
+#define BM_PWM_CTRL_PWM3_ENABLE         0x8
+#define BF_PWM_CTRL_PWM3_ENABLE(v)      (((v) & 0x1) << 3)
+#define BFM_PWM_CTRL_PWM3_ENABLE(v)     BM_PWM_CTRL_PWM3_ENABLE
+#define BF_PWM_CTRL_PWM3_ENABLE_V(e)    BF_PWM_CTRL_PWM3_ENABLE(BV_PWM_CTRL_PWM3_ENABLE__##e)
+#define BFM_PWM_CTRL_PWM3_ENABLE_V(v)   BM_PWM_CTRL_PWM3_ENABLE
+#define BP_PWM_CTRL_PWM2_ENABLE         2
+#define BM_PWM_CTRL_PWM2_ENABLE         0x4
+#define BF_PWM_CTRL_PWM2_ENABLE(v)      (((v) & 0x1) << 2)
+#define BFM_PWM_CTRL_PWM2_ENABLE(v)     BM_PWM_CTRL_PWM2_ENABLE
+#define BF_PWM_CTRL_PWM2_ENABLE_V(e)    BF_PWM_CTRL_PWM2_ENABLE(BV_PWM_CTRL_PWM2_ENABLE__##e)
+#define BFM_PWM_CTRL_PWM2_ENABLE_V(v)   BM_PWM_CTRL_PWM2_ENABLE
+#define BP_PWM_CTRL_PWM1_ENABLE         1
+#define BM_PWM_CTRL_PWM1_ENABLE         0x2
+#define BF_PWM_CTRL_PWM1_ENABLE(v)      (((v) & 0x1) << 1)
+#define BFM_PWM_CTRL_PWM1_ENABLE(v)     BM_PWM_CTRL_PWM1_ENABLE
+#define BF_PWM_CTRL_PWM1_ENABLE_V(e)    BF_PWM_CTRL_PWM1_ENABLE(BV_PWM_CTRL_PWM1_ENABLE__##e)
+#define BFM_PWM_CTRL_PWM1_ENABLE_V(v)   BM_PWM_CTRL_PWM1_ENABLE
+#define BP_PWM_CTRL_PWM0_ENABLE         0
+#define BM_PWM_CTRL_PWM0_ENABLE         0x1
+#define BF_PWM_CTRL_PWM0_ENABLE(v)      (((v) & 0x1) << 0)
+#define BFM_PWM_CTRL_PWM0_ENABLE(v)     BM_PWM_CTRL_PWM0_ENABLE
+#define BF_PWM_CTRL_PWM0_ENABLE_V(e)    BF_PWM_CTRL_PWM0_ENABLE(BV_PWM_CTRL_PWM0_ENABLE__##e)
+#define BFM_PWM_CTRL_PWM0_ENABLE_V(v)   BM_PWM_CTRL_PWM0_ENABLE
+
+#define HW_PWM_ACTIVEn(_n1)             HW(PWM_ACTIVEn(_n1))
+#define HWA_PWM_ACTIVEn(_n1)            (0x80064000 + 0x10 + (_n1) * 0x20)
+#define HWT_PWM_ACTIVEn(_n1)            HWIO_32_RW
+#define HWN_PWM_ACTIVEn(_n1)            PWM_ACTIVEn
+#define HWI_PWM_ACTIVEn(_n1)            (_n1)
+#define HW_PWM_ACTIVEn_SET(_n1)         HW(PWM_ACTIVEn_SET(_n1))
+#define HWA_PWM_ACTIVEn_SET(_n1)        (HWA_PWM_ACTIVEn(_n1) + 0x4)
+#define HWT_PWM_ACTIVEn_SET(_n1)        HWIO_32_WO
+#define HWN_PWM_ACTIVEn_SET(_n1)        PWM_ACTIVEn
+#define HWI_PWM_ACTIVEn_SET(_n1)        (_n1)
+#define HW_PWM_ACTIVEn_CLR(_n1)         HW(PWM_ACTIVEn_CLR(_n1))
+#define HWA_PWM_ACTIVEn_CLR(_n1)        (HWA_PWM_ACTIVEn(_n1) + 0x8)
+#define HWT_PWM_ACTIVEn_CLR(_n1)        HWIO_32_WO
+#define HWN_PWM_ACTIVEn_CLR(_n1)        PWM_ACTIVEn
+#define HWI_PWM_ACTIVEn_CLR(_n1)        (_n1)
+#define HW_PWM_ACTIVEn_TOG(_n1)         HW(PWM_ACTIVEn_TOG(_n1))
+#define HWA_PWM_ACTIVEn_TOG(_n1)        (HWA_PWM_ACTIVEn(_n1) + 0xc)
+#define HWT_PWM_ACTIVEn_TOG(_n1)        HWIO_32_WO
+#define HWN_PWM_ACTIVEn_TOG(_n1)        PWM_ACTIVEn
+#define HWI_PWM_ACTIVEn_TOG(_n1)        (_n1)
+#define BP_PWM_ACTIVEn_INACTIVE         16
+#define BM_PWM_ACTIVEn_INACTIVE         0xffff0000
+#define BF_PWM_ACTIVEn_INACTIVE(v)      (((v) & 0xffff) << 16)
+#define BFM_PWM_ACTIVEn_INACTIVE(v)     BM_PWM_ACTIVEn_INACTIVE
+#define BF_PWM_ACTIVEn_INACTIVE_V(e)    BF_PWM_ACTIVEn_INACTIVE(BV_PWM_ACTIVEn_INACTIVE__##e)
+#define BFM_PWM_ACTIVEn_INACTIVE_V(v)   BM_PWM_ACTIVEn_INACTIVE
+#define BP_PWM_ACTIVEn_ACTIVE           0
+#define BM_PWM_ACTIVEn_ACTIVE           0xffff
+#define BF_PWM_ACTIVEn_ACTIVE(v)        (((v) & 0xffff) << 0)
+#define BFM_PWM_ACTIVEn_ACTIVE(v)       BM_PWM_ACTIVEn_ACTIVE
+#define BF_PWM_ACTIVEn_ACTIVE_V(e)      BF_PWM_ACTIVEn_ACTIVE(BV_PWM_ACTIVEn_ACTIVE__##e)
+#define BFM_PWM_ACTIVEn_ACTIVE_V(v)     BM_PWM_ACTIVEn_ACTIVE
+
+#define HW_PWM_PERIODn(_n1)                 HW(PWM_PERIODn(_n1))
+#define HWA_PWM_PERIODn(_n1)                (0x80064000 + 0x20 + (_n1) * 0x20)
+#define HWT_PWM_PERIODn(_n1)                HWIO_32_RW
+#define HWN_PWM_PERIODn(_n1)                PWM_PERIODn
+#define HWI_PWM_PERIODn(_n1)                (_n1)
+#define HW_PWM_PERIODn_SET(_n1)             HW(PWM_PERIODn_SET(_n1))
+#define HWA_PWM_PERIODn_SET(_n1)            (HWA_PWM_PERIODn(_n1) + 0x4)
+#define HWT_PWM_PERIODn_SET(_n1)            HWIO_32_WO
+#define HWN_PWM_PERIODn_SET(_n1)            PWM_PERIODn
+#define HWI_PWM_PERIODn_SET(_n1)            (_n1)
+#define HW_PWM_PERIODn_CLR(_n1)             HW(PWM_PERIODn_CLR(_n1))
+#define HWA_PWM_PERIODn_CLR(_n1)            (HWA_PWM_PERIODn(_n1) + 0x8)
+#define HWT_PWM_PERIODn_CLR(_n1)            HWIO_32_WO
+#define HWN_PWM_PERIODn_CLR(_n1)            PWM_PERIODn
+#define HWI_PWM_PERIODn_CLR(_n1)            (_n1)
+#define HW_PWM_PERIODn_TOG(_n1)             HW(PWM_PERIODn_TOG(_n1))
+#define HWA_PWM_PERIODn_TOG(_n1)            (HWA_PWM_PERIODn(_n1) + 0xc)
+#define HWT_PWM_PERIODn_TOG(_n1)            HWIO_32_WO
+#define HWN_PWM_PERIODn_TOG(_n1)            PWM_PERIODn
+#define HWI_PWM_PERIODn_TOG(_n1)            (_n1)
+#define BP_PWM_PERIODn_MATT                 23
+#define BM_PWM_PERIODn_MATT                 0x800000
+#define BF_PWM_PERIODn_MATT(v)              (((v) & 0x1) << 23)
+#define BFM_PWM_PERIODn_MATT(v)             BM_PWM_PERIODn_MATT
+#define BF_PWM_PERIODn_MATT_V(e)            BF_PWM_PERIODn_MATT(BV_PWM_PERIODn_MATT__##e)
+#define BFM_PWM_PERIODn_MATT_V(v)           BM_PWM_PERIODn_MATT
+#define BP_PWM_PERIODn_CDIV                 20
+#define BM_PWM_PERIODn_CDIV                 0x700000
+#define BV_PWM_PERIODn_CDIV__DIV_1          0x0
+#define BV_PWM_PERIODn_CDIV__DIV_2          0x1
+#define BV_PWM_PERIODn_CDIV__DIV_4          0x2
+#define BV_PWM_PERIODn_CDIV__DIV_8          0x3
+#define BV_PWM_PERIODn_CDIV__DIV_16         0x4
+#define BV_PWM_PERIODn_CDIV__DIV_64         0x5
+#define BV_PWM_PERIODn_CDIV__DIV_256        0x6
+#define BV_PWM_PERIODn_CDIV__DIV_1024       0x7
+#define BF_PWM_PERIODn_CDIV(v)              (((v) & 0x7) << 20)
+#define BFM_PWM_PERIODn_CDIV(v)             BM_PWM_PERIODn_CDIV
+#define BF_PWM_PERIODn_CDIV_V(e)            BF_PWM_PERIODn_CDIV(BV_PWM_PERIODn_CDIV__##e)
+#define BFM_PWM_PERIODn_CDIV_V(v)           BM_PWM_PERIODn_CDIV
+#define BP_PWM_PERIODn_INACTIVE_STATE       18
+#define BM_PWM_PERIODn_INACTIVE_STATE       0xc0000
+#define BV_PWM_PERIODn_INACTIVE_STATE__HI_Z 0x0
+#define BV_PWM_PERIODn_INACTIVE_STATE__0    0x2
+#define BV_PWM_PERIODn_INACTIVE_STATE__1    0x3
+#define BF_PWM_PERIODn_INACTIVE_STATE(v)    (((v) & 0x3) << 18)
+#define BFM_PWM_PERIODn_INACTIVE_STATE(v)   BM_PWM_PERIODn_INACTIVE_STATE
+#define BF_PWM_PERIODn_INACTIVE_STATE_V(e)  BF_PWM_PERIODn_INACTIVE_STATE(BV_PWM_PERIODn_INACTIVE_STATE__##e)
+#define BFM_PWM_PERIODn_INACTIVE_STATE_V(v) BM_PWM_PERIODn_INACTIVE_STATE
+#define BP_PWM_PERIODn_ACTIVE_STATE         16
+#define BM_PWM_PERIODn_ACTIVE_STATE         0x30000
+#define BV_PWM_PERIODn_ACTIVE_STATE__HI_Z   0x0
+#define BV_PWM_PERIODn_ACTIVE_STATE__0      0x2
+#define BV_PWM_PERIODn_ACTIVE_STATE__1      0x3
+#define BF_PWM_PERIODn_ACTIVE_STATE(v)      (((v) & 0x3) << 16)
+#define BFM_PWM_PERIODn_ACTIVE_STATE(v)     BM_PWM_PERIODn_ACTIVE_STATE
+#define BF_PWM_PERIODn_ACTIVE_STATE_V(e)    BF_PWM_PERIODn_ACTIVE_STATE(BV_PWM_PERIODn_ACTIVE_STATE__##e)
+#define BFM_PWM_PERIODn_ACTIVE_STATE_V(v)   BM_PWM_PERIODn_ACTIVE_STATE
+#define BP_PWM_PERIODn_PERIOD               0
+#define BM_PWM_PERIODn_PERIOD               0xffff
+#define BF_PWM_PERIODn_PERIOD(v)            (((v) & 0xffff) << 0)
+#define BFM_PWM_PERIODn_PERIOD(v)           BM_PWM_PERIODn_PERIOD
+#define BF_PWM_PERIODn_PERIOD_V(e)          BF_PWM_PERIODn_PERIOD(BV_PWM_PERIODn_PERIOD__##e)
+#define BFM_PWM_PERIODn_PERIOD_V(v)         BM_PWM_PERIODn_PERIOD
+
+#endif /* __HEADERGEN_STMP3600_PWM_H__*/
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-anatop.h b/firmware/target/arm/imx233/regs/stmp3600/regs-anatop.h
deleted file mode 100644
index 15780d6506..0000000000
--- a/firmware/target/arm/imx233/regs/stmp3600/regs-anatop.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3600:2.3.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__STMP3600__ANATOP__H__
-#define __HEADERGEN__STMP3600__ANATOP__H__
-
-#define REGS_ANATOP_BASE (0x8003c200)
-
-#define REGS_ANATOP_VERSION "2.3.0"
-
-/**
- * Register: HW_ANATOP_PROBE_OUTPUT_SELECT
- * Address: 0
- * SCT: yes
-*/
-#define HW_ANATOP_PROBE_OUTPUT_SELECT                   (*(volatile unsigned long *)(REGS_ANATOP_BASE + 0x0 + 0x0))
-#define HW_ANATOP_PROBE_OUTPUT_SELECT_SET               (*(volatile unsigned long *)(REGS_ANATOP_BASE + 0x0 + 0x4))
-#define HW_ANATOP_PROBE_OUTPUT_SELECT_CLR               (*(volatile unsigned long *)(REGS_ANATOP_BASE + 0x0 + 0x8))
-#define HW_ANATOP_PROBE_OUTPUT_SELECT_TOG               (*(volatile unsigned long *)(REGS_ANATOP_BASE + 0x0 + 0xc))
-#define BP_ANATOP_PROBE_OUTPUT_SELECT_OUTPUT_SELECT     0
-#define BM_ANATOP_PROBE_OUTPUT_SELECT_OUTPUT_SELECT     0xffffffff
-#define BF_ANATOP_PROBE_OUTPUT_SELECT_OUTPUT_SELECT(v)  (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_ANATOP_PROBE_INPUT_SELECT
- * Address: 0x10
- * SCT: yes
-*/
-#define HW_ANATOP_PROBE_INPUT_SELECT                    (*(volatile unsigned long *)(REGS_ANATOP_BASE + 0x10 + 0x0))
-#define HW_ANATOP_PROBE_INPUT_SELECT_SET                (*(volatile unsigned long *)(REGS_ANATOP_BASE + 0x10 + 0x4))
-#define HW_ANATOP_PROBE_INPUT_SELECT_CLR                (*(volatile unsigned long *)(REGS_ANATOP_BASE + 0x10 + 0x8))
-#define HW_ANATOP_PROBE_INPUT_SELECT_TOG                (*(volatile unsigned long *)(REGS_ANATOP_BASE + 0x10 + 0xc))
-#define BP_ANATOP_PROBE_INPUT_SELECT_INPUT_SELECT       0
-#define BM_ANATOP_PROBE_INPUT_SELECT_INPUT_SELECT       0xffffffff
-#define BF_ANATOP_PROBE_INPUT_SELECT_INPUT_SELECT(v)    (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_ANATOP_PROBE_DATA
- * Address: 0x20
- * SCT: yes
-*/
-#define HW_ANATOP_PROBE_DATA            (*(volatile unsigned long *)(REGS_ANATOP_BASE + 0x20 + 0x0))
-#define HW_ANATOP_PROBE_DATA_SET        (*(volatile unsigned long *)(REGS_ANATOP_BASE + 0x20 + 0x4))
-#define HW_ANATOP_PROBE_DATA_CLR        (*(volatile unsigned long *)(REGS_ANATOP_BASE + 0x20 + 0x8))
-#define HW_ANATOP_PROBE_DATA_TOG        (*(volatile unsigned long *)(REGS_ANATOP_BASE + 0x20 + 0xc))
-#define BP_ANATOP_PROBE_DATA_DATA       0
-#define BM_ANATOP_PROBE_DATA_DATA       0xffffffff
-#define BF_ANATOP_PROBE_DATA_DATA(v)    (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_ANATOP_PROBE_DIGTOP_SELECT
- * Address: 0x30
- * SCT: yes
-*/
-#define HW_ANATOP_PROBE_DIGTOP_SELECT                   (*(volatile unsigned long *)(REGS_ANATOP_BASE + 0x30 + 0x0))
-#define HW_ANATOP_PROBE_DIGTOP_SELECT_SET               (*(volatile unsigned long *)(REGS_ANATOP_BASE + 0x30 + 0x4))
-#define HW_ANATOP_PROBE_DIGTOP_SELECT_CLR               (*(volatile unsigned long *)(REGS_ANATOP_BASE + 0x30 + 0x8))
-#define HW_ANATOP_PROBE_DIGTOP_SELECT_TOG               (*(volatile unsigned long *)(REGS_ANATOP_BASE + 0x30 + 0xc))
-#define BP_ANATOP_PROBE_DIGTOP_SELECT_DIGTOP_SELECT     0
-#define BM_ANATOP_PROBE_DIGTOP_SELECT_DIGTOP_SELECT     0xffffffff
-#define BF_ANATOP_PROBE_DIGTOP_SELECT_DIGTOP_SELECT(v)  (((v) << 0) & 0xffffffff)
-
-#endif /* __HEADERGEN__STMP3600__ANATOP__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-apbh.h b/firmware/target/arm/imx233/regs/stmp3600/regs-apbh.h
deleted file mode 100644
index 74cf049c5b..0000000000
--- a/firmware/target/arm/imx233/regs/stmp3600/regs-apbh.h
+++ /dev/null
@@ -1,288 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3600:2.4.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__STMP3600__APBH__H__
-#define __HEADERGEN__STMP3600__APBH__H__
-
-#define REGS_APBH_BASE (0x80004000)
-
-#define REGS_APBH_VERSION "2.4.0"
-
-/**
- * Register: HW_APBH_CTRL0
- * Address: 0
- * SCT: yes
-*/
-#define HW_APBH_CTRL0                           (*(volatile unsigned long *)(REGS_APBH_BASE + 0x0 + 0x0))
-#define HW_APBH_CTRL0_SET                       (*(volatile unsigned long *)(REGS_APBH_BASE + 0x0 + 0x4))
-#define HW_APBH_CTRL0_CLR                       (*(volatile unsigned long *)(REGS_APBH_BASE + 0x0 + 0x8))
-#define HW_APBH_CTRL0_TOG                       (*(volatile unsigned long *)(REGS_APBH_BASE + 0x0 + 0xc))
-#define BP_APBH_CTRL0_SFTRST                    31
-#define BM_APBH_CTRL0_SFTRST                    0x80000000
-#define BF_APBH_CTRL0_SFTRST(v)                 (((v) << 31) & 0x80000000)
-#define BP_APBH_CTRL0_CLKGATE                   30
-#define BM_APBH_CTRL0_CLKGATE                   0x40000000
-#define BF_APBH_CTRL0_CLKGATE(v)                (((v) << 30) & 0x40000000)
-#define BP_APBH_CTRL0_RESET_CHANNEL             16
-#define BM_APBH_CTRL0_RESET_CHANNEL             0xff0000
-#define BV_APBH_CTRL0_RESET_CHANNEL__HWECC      0x1
-#define BV_APBH_CTRL0_RESET_CHANNEL__SSP        0x2
-#define BV_APBH_CTRL0_RESET_CHANNEL__SRC        0x4
-#define BV_APBH_CTRL0_RESET_CHANNEL__DEST       0x8
-#define BV_APBH_CTRL0_RESET_CHANNEL__ATA        0x10
-#define BV_APBH_CTRL0_RESET_CHANNEL__NAND0      0x10
-#define BV_APBH_CTRL0_RESET_CHANNEL__NAND1      0x20
-#define BV_APBH_CTRL0_RESET_CHANNEL__NAND2      0x30
-#define BV_APBH_CTRL0_RESET_CHANNEL__NAND3      0x40
-#define BF_APBH_CTRL0_RESET_CHANNEL(v)          (((v) << 16) & 0xff0000)
-#define BF_APBH_CTRL0_RESET_CHANNEL_V(v)        ((BV_APBH_CTRL0_RESET_CHANNEL__##v << 16) & 0xff0000)
-#define BP_APBH_CTRL0_CLKGATE_CHANNEL           8
-#define BM_APBH_CTRL0_CLKGATE_CHANNEL           0xff00
-#define BV_APBH_CTRL0_CLKGATE_CHANNEL__HWECC    0x1
-#define BV_APBH_CTRL0_CLKGATE_CHANNEL__SSP      0x2
-#define BV_APBH_CTRL0_CLKGATE_CHANNEL__SRC      0x4
-#define BV_APBH_CTRL0_CLKGATE_CHANNEL__DEST     0x8
-#define BV_APBH_CTRL0_CLKGATE_CHANNEL__ATA      0x10
-#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND0    0x10
-#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND1    0x20
-#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND2    0x30
-#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND3    0x40
-#define BF_APBH_CTRL0_CLKGATE_CHANNEL(v)        (((v) << 8) & 0xff00)
-#define BF_APBH_CTRL0_CLKGATE_CHANNEL_V(v)      ((BV_APBH_CTRL0_CLKGATE_CHANNEL__##v << 8) & 0xff00)
-#define BP_APBH_CTRL0_FREEZE_CHANNEL            0
-#define BM_APBH_CTRL0_FREEZE_CHANNEL            0xff
-#define BV_APBH_CTRL0_FREEZE_CHANNEL__HWECC     0x1
-#define BV_APBH_CTRL0_FREEZE_CHANNEL__SSP       0x2
-#define BV_APBH_CTRL0_FREEZE_CHANNEL__SRC       0x4
-#define BV_APBH_CTRL0_FREEZE_CHANNEL__DEST      0x8
-#define BV_APBH_CTRL0_FREEZE_CHANNEL__ATA       0x10
-#define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND0     0x10
-#define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND1     0x20
-#define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND2     0x30
-#define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND3     0x40
-#define BF_APBH_CTRL0_FREEZE_CHANNEL(v)         (((v) << 0) & 0xff)
-#define BF_APBH_CTRL0_FREEZE_CHANNEL_V(v)       ((BV_APBH_CTRL0_FREEZE_CHANNEL__##v << 0) & 0xff)
-
-/**
- * Register: HW_APBH_CTRL1
- * Address: 0x10
- * SCT: yes
-*/
-#define HW_APBH_CTRL1                       (*(volatile unsigned long *)(REGS_APBH_BASE + 0x10 + 0x0))
-#define HW_APBH_CTRL1_SET                   (*(volatile unsigned long *)(REGS_APBH_BASE + 0x10 + 0x4))
-#define HW_APBH_CTRL1_CLR                   (*(volatile unsigned long *)(REGS_APBH_BASE + 0x10 + 0x8))
-#define HW_APBH_CTRL1_TOG                   (*(volatile unsigned long *)(REGS_APBH_BASE + 0x10 + 0xc))
-#define BP_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN    16
-#define BM_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN    0xff0000
-#define BF_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN(v) (((v) << 16) & 0xff0000)
-#define BP_APBH_CTRL1_CH_CMDCMPLT_IRQ       0
-#define BM_APBH_CTRL1_CH_CMDCMPLT_IRQ       0xff
-#define BF_APBH_CTRL1_CH_CMDCMPLT_IRQ(v)    (((v) << 0) & 0xff)
-
-/**
- * Register: HW_APBH_DEVSEL
- * Address: 0x20
- * SCT: no
-*/
-#define HW_APBH_DEVSEL          (*(volatile unsigned long *)(REGS_APBH_BASE + 0x20))
-#define BP_APBH_DEVSEL_CH7      28
-#define BM_APBH_DEVSEL_CH7      0xf0000000
-#define BF_APBH_DEVSEL_CH7(v)   (((v) << 28) & 0xf0000000)
-#define BP_APBH_DEVSEL_CH6      24
-#define BM_APBH_DEVSEL_CH6      0xf000000
-#define BF_APBH_DEVSEL_CH6(v)   (((v) << 24) & 0xf000000)
-#define BP_APBH_DEVSEL_CH5      20
-#define BM_APBH_DEVSEL_CH5      0xf00000
-#define BF_APBH_DEVSEL_CH5(v)   (((v) << 20) & 0xf00000)
-#define BP_APBH_DEVSEL_CH4      16
-#define BM_APBH_DEVSEL_CH4      0xf0000
-#define BF_APBH_DEVSEL_CH4(v)   (((v) << 16) & 0xf0000)
-#define BP_APBH_DEVSEL_CH3      12
-#define BM_APBH_DEVSEL_CH3      0xf000
-#define BF_APBH_DEVSEL_CH3(v)   (((v) << 12) & 0xf000)
-#define BP_APBH_DEVSEL_CH2      8
-#define BM_APBH_DEVSEL_CH2      0xf00
-#define BF_APBH_DEVSEL_CH2(v)   (((v) << 8) & 0xf00)
-#define BP_APBH_DEVSEL_CH1      4
-#define BM_APBH_DEVSEL_CH1      0xf0
-#define BF_APBH_DEVSEL_CH1(v)   (((v) << 4) & 0xf0)
-#define BP_APBH_DEVSEL_CH0      0
-#define BM_APBH_DEVSEL_CH0      0xf
-#define BF_APBH_DEVSEL_CH0(v)   (((v) << 0) & 0xf)
-
-/**
- * Register: HW_APBH_CHn_DEBUG2
- * Address: 0x90+n*0x70
- * SCT: no
-*/
-#define HW_APBH_CHn_DEBUG2(n)           (*(volatile unsigned long *)(REGS_APBH_BASE + 0x90+(n)*0x70))
-#define BP_APBH_CHn_DEBUG2_APB_BYTES    16
-#define BM_APBH_CHn_DEBUG2_APB_BYTES    0xffff0000
-#define BF_APBH_CHn_DEBUG2_APB_BYTES(v) (((v) << 16) & 0xffff0000)
-#define BP_APBH_CHn_DEBUG2_AHB_BYTES    0
-#define BM_APBH_CHn_DEBUG2_AHB_BYTES    0xffff
-#define BF_APBH_CHn_DEBUG2_AHB_BYTES(v) (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_APBH_CHn_CURCMDAR
- * Address: 0x30+n*0x70
- * SCT: no
-*/
-#define HW_APBH_CHn_CURCMDAR(n)             (*(volatile unsigned long *)(REGS_APBH_BASE + 0x30+(n)*0x70))
-#define BP_APBH_CHn_CURCMDAR_CMD_ADDR       0
-#define BM_APBH_CHn_CURCMDAR_CMD_ADDR       0xffffffff
-#define BF_APBH_CHn_CURCMDAR_CMD_ADDR(v)    (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_APBH_CHn_BAR
- * Address: 0x60+n*0x70
- * SCT: no
-*/
-#define HW_APBH_CHn_BAR(n)          (*(volatile unsigned long *)(REGS_APBH_BASE + 0x60+(n)*0x70))
-#define BP_APBH_CHn_BAR_ADDRESS     0
-#define BM_APBH_CHn_BAR_ADDRESS     0xffffffff
-#define BF_APBH_CHn_BAR_ADDRESS(v)  (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_APBH_CHn_CMD
- * Address: 0x50+n*0x70
- * SCT: no
-*/
-#define HW_APBH_CHn_CMD(n)                      (*(volatile unsigned long *)(REGS_APBH_BASE + 0x50+(n)*0x70))
-#define BP_APBH_CHn_CMD_XFER_COUNT              16
-#define BM_APBH_CHn_CMD_XFER_COUNT              0xffff0000
-#define BF_APBH_CHn_CMD_XFER_COUNT(v)           (((v) << 16) & 0xffff0000)
-#define BP_APBH_CHn_CMD_CMDWORDS                12
-#define BM_APBH_CHn_CMD_CMDWORDS                0xf000
-#define BF_APBH_CHn_CMD_CMDWORDS(v)             (((v) << 12) & 0xf000)
-#define BP_APBH_CHn_CMD_WAIT4ENDCMD             7
-#define BM_APBH_CHn_CMD_WAIT4ENDCMD             0x80
-#define BF_APBH_CHn_CMD_WAIT4ENDCMD(v)          (((v) << 7) & 0x80)
-#define BP_APBH_CHn_CMD_SEMAPHORE               6
-#define BM_APBH_CHn_CMD_SEMAPHORE               0x40
-#define BF_APBH_CHn_CMD_SEMAPHORE(v)            (((v) << 6) & 0x40)
-#define BP_APBH_CHn_CMD_NANDWAIT4READY          5
-#define BM_APBH_CHn_CMD_NANDWAIT4READY          0x20
-#define BF_APBH_CHn_CMD_NANDWAIT4READY(v)       (((v) << 5) & 0x20)
-#define BP_APBH_CHn_CMD_NANDLOCK                4
-#define BM_APBH_CHn_CMD_NANDLOCK                0x10
-#define BF_APBH_CHn_CMD_NANDLOCK(v)             (((v) << 4) & 0x10)
-#define BP_APBH_CHn_CMD_IRQONCMPLT              3
-#define BM_APBH_CHn_CMD_IRQONCMPLT              0x8
-#define BF_APBH_CHn_CMD_IRQONCMPLT(v)           (((v) << 3) & 0x8)
-#define BP_APBH_CHn_CMD_CHAIN                   2
-#define BM_APBH_CHn_CMD_CHAIN                   0x4
-#define BF_APBH_CHn_CMD_CHAIN(v)                (((v) << 2) & 0x4)
-#define BP_APBH_CHn_CMD_COMMAND                 0
-#define BM_APBH_CHn_CMD_COMMAND                 0x3
-#define BV_APBH_CHn_CMD_COMMAND__NO_DMA_XFER    0x0
-#define BV_APBH_CHn_CMD_COMMAND__DMA_WRITE      0x1
-#define BV_APBH_CHn_CMD_COMMAND__DMA_READ       0x2
-#define BV_APBH_CHn_CMD_COMMAND__DMA_SENSE      0x3
-#define BF_APBH_CHn_CMD_COMMAND(v)              (((v) << 0) & 0x3)
-#define BF_APBH_CHn_CMD_COMMAND_V(v)            ((BV_APBH_CHn_CMD_COMMAND__##v << 0) & 0x3)
-
-/**
- * Register: HW_APBH_CHn_NXTCMDAR
- * Address: 0x40+n*0x70
- * SCT: no
-*/
-#define HW_APBH_CHn_NXTCMDAR(n)             (*(volatile unsigned long *)(REGS_APBH_BASE + 0x40+(n)*0x70))
-#define BP_APBH_CHn_NXTCMDAR_CMD_ADDR       0
-#define BM_APBH_CHn_NXTCMDAR_CMD_ADDR       0xffffffff
-#define BF_APBH_CHn_NXTCMDAR_CMD_ADDR(v)    (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_APBH_CHn_SEMA
- * Address: 0x70+n*0x70
- * SCT: no
-*/
-#define HW_APBH_CHn_SEMA(n)                 (*(volatile unsigned long *)(REGS_APBH_BASE + 0x70+(n)*0x70))
-#define BP_APBH_CHn_SEMA_PHORE              16
-#define BM_APBH_CHn_SEMA_PHORE              0xff0000
-#define BF_APBH_CHn_SEMA_PHORE(v)           (((v) << 16) & 0xff0000)
-#define BP_APBH_CHn_SEMA_INCREMENT_SEMA     0
-#define BM_APBH_CHn_SEMA_INCREMENT_SEMA     0xff
-#define BF_APBH_CHn_SEMA_INCREMENT_SEMA(v)  (((v) << 0) & 0xff)
-
-/**
- * Register: HW_APBH_CHn_DEBUG1
- * Address: 0x80+n*0x70
- * SCT: no
-*/
-#define HW_APBH_CHn_DEBUG1(n)                           (*(volatile unsigned long *)(REGS_APBH_BASE + 0x80+(n)*0x70))
-#define BP_APBH_CHn_DEBUG1_REQ                          31
-#define BM_APBH_CHn_DEBUG1_REQ                          0x80000000
-#define BF_APBH_CHn_DEBUG1_REQ(v)                       (((v) << 31) & 0x80000000)
-#define BP_APBH_CHn_DEBUG1_BURST                        30
-#define BM_APBH_CHn_DEBUG1_BURST                        0x40000000
-#define BF_APBH_CHn_DEBUG1_BURST(v)                     (((v) << 30) & 0x40000000)
-#define BP_APBH_CHn_DEBUG1_KICK                         29
-#define BM_APBH_CHn_DEBUG1_KICK                         0x20000000
-#define BF_APBH_CHn_DEBUG1_KICK(v)                      (((v) << 29) & 0x20000000)
-#define BP_APBH_CHn_DEBUG1_END                          28
-#define BM_APBH_CHn_DEBUG1_END                          0x10000000
-#define BF_APBH_CHn_DEBUG1_END(v)                       (((v) << 28) & 0x10000000)
-#define BP_APBH_CHn_DEBUG1_RSVD2                        25
-#define BM_APBH_CHn_DEBUG1_RSVD2                        0xe000000
-#define BF_APBH_CHn_DEBUG1_RSVD2(v)                     (((v) << 25) & 0xe000000)
-#define BP_APBH_CHn_DEBUG1_NEXTCMDADDRVALID             24
-#define BM_APBH_CHn_DEBUG1_NEXTCMDADDRVALID             0x1000000
-#define BF_APBH_CHn_DEBUG1_NEXTCMDADDRVALID(v)          (((v) << 24) & 0x1000000)
-#define BP_APBH_CHn_DEBUG1_RD_FIFO_EMPTY                23
-#define BM_APBH_CHn_DEBUG1_RD_FIFO_EMPTY                0x800000
-#define BF_APBH_CHn_DEBUG1_RD_FIFO_EMPTY(v)             (((v) << 23) & 0x800000)
-#define BP_APBH_CHn_DEBUG1_RD_FIFO_FULL                 22
-#define BM_APBH_CHn_DEBUG1_RD_FIFO_FULL                 0x400000
-#define BF_APBH_CHn_DEBUG1_RD_FIFO_FULL(v)              (((v) << 22) & 0x400000)
-#define BP_APBH_CHn_DEBUG1_WR_FIFO_EMPTY                21
-#define BM_APBH_CHn_DEBUG1_WR_FIFO_EMPTY                0x200000
-#define BF_APBH_CHn_DEBUG1_WR_FIFO_EMPTY(v)             (((v) << 21) & 0x200000)
-#define BP_APBH_CHn_DEBUG1_WR_FIFO_FULL                 20
-#define BM_APBH_CHn_DEBUG1_WR_FIFO_FULL                 0x100000
-#define BF_APBH_CHn_DEBUG1_WR_FIFO_FULL(v)              (((v) << 20) & 0x100000)
-#define BP_APBH_CHn_DEBUG1_RSVD1                        5
-#define BM_APBH_CHn_DEBUG1_RSVD1                        0xfffe0
-#define BF_APBH_CHn_DEBUG1_RSVD1(v)                     (((v) << 5) & 0xfffe0)
-#define BP_APBH_CHn_DEBUG1_STATEMACHINE                 0
-#define BM_APBH_CHn_DEBUG1_STATEMACHINE                 0x1f
-#define BV_APBH_CHn_DEBUG1_STATEMACHINE__IDLE           0x0
-#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD1       0x1
-#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD3       0x2
-#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD2       0x3
-#define BV_APBH_CHn_DEBUG1_STATEMACHINE__XFER_DECODE    0x4
-#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_WAIT       0x5
-#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD4       0x6
-#define BV_APBH_CHn_DEBUG1_STATEMACHINE__PIO_REQ        0x7
-#define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_FLUSH     0x8
-#define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_WAIT      0x9
-#define BV_APBH_CHn_DEBUG1_STATEMACHINE__WRITE          0xc
-#define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_REQ       0xd
-#define BV_APBH_CHn_DEBUG1_STATEMACHINE__CHECK_CHAIN    0xe
-#define BV_APBH_CHn_DEBUG1_STATEMACHINE__XFER_COMPLETE  0xf
-#define BV_APBH_CHn_DEBUG1_STATEMACHINE__WAIT_END       0x15
-#define BV_APBH_CHn_DEBUG1_STATEMACHINE__WRITE_WAIT     0x1c
-#define BV_APBH_CHn_DEBUG1_STATEMACHINE__CHECK_WAIT     0x1e
-#define BF_APBH_CHn_DEBUG1_STATEMACHINE(v)              (((v) << 0) & 0x1f)
-#define BF_APBH_CHn_DEBUG1_STATEMACHINE_V(v)            ((BV_APBH_CHn_DEBUG1_STATEMACHINE__##v << 0) & 0x1f)
-
-#endif /* __HEADERGEN__STMP3600__APBH__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-apbx.h b/firmware/target/arm/imx233/regs/stmp3600/regs-apbx.h
deleted file mode 100644
index 1b0cea7245..0000000000
--- a/firmware/target/arm/imx233/regs/stmp3600/regs-apbx.h
+++ /dev/null
@@ -1,276 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3600:2.4.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__STMP3600__APBX__H__
-#define __HEADERGEN__STMP3600__APBX__H__
-
-#define REGS_APBX_BASE (0x80024000)
-
-#define REGS_APBX_VERSION "2.4.0"
-
-/**
- * Register: HW_APBX_CTRL0
- * Address: 0
- * SCT: yes
-*/
-#define HW_APBX_CTRL0                           (*(volatile unsigned long *)(REGS_APBX_BASE + 0x0 + 0x0))
-#define HW_APBX_CTRL0_SET                       (*(volatile unsigned long *)(REGS_APBX_BASE + 0x0 + 0x4))
-#define HW_APBX_CTRL0_CLR                       (*(volatile unsigned long *)(REGS_APBX_BASE + 0x0 + 0x8))
-#define HW_APBX_CTRL0_TOG                       (*(volatile unsigned long *)(REGS_APBX_BASE + 0x0 + 0xc))
-#define BP_APBX_CTRL0_SFTRST                    31
-#define BM_APBX_CTRL0_SFTRST                    0x80000000
-#define BF_APBX_CTRL0_SFTRST(v)                 (((v) << 31) & 0x80000000)
-#define BP_APBX_CTRL0_CLKGATE                   30
-#define BM_APBX_CTRL0_CLKGATE                   0x40000000
-#define BF_APBX_CTRL0_CLKGATE(v)                (((v) << 30) & 0x40000000)
-#define BP_APBX_CTRL0_RESET_CHANNEL             16
-#define BM_APBX_CTRL0_RESET_CHANNEL             0xff0000
-#define BV_APBX_CTRL0_RESET_CHANNEL__AUDIOIN    0x1
-#define BV_APBX_CTRL0_RESET_CHANNEL__AUDIOOUT   0x2
-#define BV_APBX_CTRL0_RESET_CHANNEL__SPDIF_TX   0x4
-#define BV_APBX_CTRL0_RESET_CHANNEL__I2C        0x8
-#define BV_APBX_CTRL0_RESET_CHANNEL__LCDIF      0x10
-#define BV_APBX_CTRL0_RESET_CHANNEL__DRI        0x20
-#define BV_APBX_CTRL0_RESET_CHANNEL__UART_RX    0x30
-#define BV_APBX_CTRL0_RESET_CHANNEL__IRDA_RX    0x30
-#define BV_APBX_CTRL0_RESET_CHANNEL__UART_TX    0x40
-#define BV_APBX_CTRL0_RESET_CHANNEL__IRDA_TX    0x40
-#define BF_APBX_CTRL0_RESET_CHANNEL(v)          (((v) << 16) & 0xff0000)
-#define BF_APBX_CTRL0_RESET_CHANNEL_V(v)        ((BV_APBX_CTRL0_RESET_CHANNEL__##v << 16) & 0xff0000)
-#define BP_APBX_CTRL0_FREEZE_CHANNEL            0
-#define BM_APBX_CTRL0_FREEZE_CHANNEL            0xff
-#define BV_APBX_CTRL0_FREEZE_CHANNEL__AUDIOIN   0x1
-#define BV_APBX_CTRL0_FREEZE_CHANNEL__AUDIOOUT  0x2
-#define BV_APBX_CTRL0_FREEZE_CHANNEL__SPDIF_TX  0x4
-#define BV_APBX_CTRL0_FREEZE_CHANNEL__I2C       0x8
-#define BV_APBX_CTRL0_FREEZE_CHANNEL__LCDIF     0x10
-#define BV_APBX_CTRL0_FREEZE_CHANNEL__DRI       0x20
-#define BV_APBX_CTRL0_FREEZE_CHANNEL__UART_RX   0x30
-#define BV_APBX_CTRL0_FREEZE_CHANNEL__IRDA_RX   0x30
-#define BV_APBX_CTRL0_FREEZE_CHANNEL__UART_TX   0x40
-#define BV_APBX_CTRL0_FREEZE_CHANNEL__IRDA_TX   0x40
-#define BF_APBX_CTRL0_FREEZE_CHANNEL(v)         (((v) << 0) & 0xff)
-#define BF_APBX_CTRL0_FREEZE_CHANNEL_V(v)       ((BV_APBX_CTRL0_FREEZE_CHANNEL__##v << 0) & 0xff)
-
-/**
- * Register: HW_APBX_CTRL1
- * Address: 0x10
- * SCT: yes
-*/
-#define HW_APBX_CTRL1                       (*(volatile unsigned long *)(REGS_APBX_BASE + 0x10 + 0x0))
-#define HW_APBX_CTRL1_SET                   (*(volatile unsigned long *)(REGS_APBX_BASE + 0x10 + 0x4))
-#define HW_APBX_CTRL1_CLR                   (*(volatile unsigned long *)(REGS_APBX_BASE + 0x10 + 0x8))
-#define HW_APBX_CTRL1_TOG                   (*(volatile unsigned long *)(REGS_APBX_BASE + 0x10 + 0xc))
-#define BP_APBX_CTRL1_CH_CMDCMPLT_IRQ_EN    16
-#define BM_APBX_CTRL1_CH_CMDCMPLT_IRQ_EN    0xff0000
-#define BF_APBX_CTRL1_CH_CMDCMPLT_IRQ_EN(v) (((v) << 16) & 0xff0000)
-#define BP_APBX_CTRL1_CH_CMDCMPLT_IRQ       0
-#define BM_APBX_CTRL1_CH_CMDCMPLT_IRQ       0xff
-#define BF_APBX_CTRL1_CH_CMDCMPLT_IRQ(v)    (((v) << 0) & 0xff)
-
-/**
- * Register: HW_APBX_DEVSEL
- * Address: 0x20
- * SCT: no
-*/
-#define HW_APBX_DEVSEL                  (*(volatile unsigned long *)(REGS_APBX_BASE + 0x20))
-#define BP_APBX_DEVSEL_CH7              28
-#define BM_APBX_DEVSEL_CH7              0xf0000000
-#define BV_APBX_DEVSEL_CH7__USE_UART    0x0
-#define BV_APBX_DEVSEL_CH7__USE_IRDA    0x1
-#define BF_APBX_DEVSEL_CH7(v)           (((v) << 28) & 0xf0000000)
-#define BF_APBX_DEVSEL_CH7_V(v)         ((BV_APBX_DEVSEL_CH7__##v << 28) & 0xf0000000)
-#define BP_APBX_DEVSEL_CH6              24
-#define BM_APBX_DEVSEL_CH6              0xf000000
-#define BV_APBX_DEVSEL_CH6__USE_UART    0x0
-#define BV_APBX_DEVSEL_CH6__USE_IRDA    0x1
-#define BF_APBX_DEVSEL_CH6(v)           (((v) << 24) & 0xf000000)
-#define BF_APBX_DEVSEL_CH6_V(v)         ((BV_APBX_DEVSEL_CH6__##v << 24) & 0xf000000)
-#define BP_APBX_DEVSEL_CH5              20
-#define BM_APBX_DEVSEL_CH5              0xf00000
-#define BF_APBX_DEVSEL_CH5(v)           (((v) << 20) & 0xf00000)
-#define BP_APBX_DEVSEL_CH4              16
-#define BM_APBX_DEVSEL_CH4              0xf0000
-#define BF_APBX_DEVSEL_CH4(v)           (((v) << 16) & 0xf0000)
-#define BP_APBX_DEVSEL_CH3              12
-#define BM_APBX_DEVSEL_CH3              0xf000
-#define BF_APBX_DEVSEL_CH3(v)           (((v) << 12) & 0xf000)
-#define BP_APBX_DEVSEL_CH2              8
-#define BM_APBX_DEVSEL_CH2              0xf00
-#define BF_APBX_DEVSEL_CH2(v)           (((v) << 8) & 0xf00)
-#define BP_APBX_DEVSEL_CH1              4
-#define BM_APBX_DEVSEL_CH1              0xf0
-#define BF_APBX_DEVSEL_CH1(v)           (((v) << 4) & 0xf0)
-#define BP_APBX_DEVSEL_CH0              0
-#define BM_APBX_DEVSEL_CH0              0xf
-#define BF_APBX_DEVSEL_CH0(v)           (((v) << 0) & 0xf)
-
-/**
- * Register: HW_APBX_CHn_NXTCMDAR
- * Address: 0x40+n*0x70
- * SCT: no
-*/
-#define HW_APBX_CHn_NXTCMDAR(n)             (*(volatile unsigned long *)(REGS_APBX_BASE + 0x40+(n)*0x70))
-#define BP_APBX_CHn_NXTCMDAR_CMD_ADDR       0
-#define BM_APBX_CHn_NXTCMDAR_CMD_ADDR       0xffffffff
-#define BF_APBX_CHn_NXTCMDAR_CMD_ADDR(v)    (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_APBX_CHn_DEBUG2
- * Address: 0x90+n*0x70
- * SCT: no
-*/
-#define HW_APBX_CHn_DEBUG2(n)           (*(volatile unsigned long *)(REGS_APBX_BASE + 0x90+(n)*0x70))
-#define BP_APBX_CHn_DEBUG2_APB_BYTES    16
-#define BM_APBX_CHn_DEBUG2_APB_BYTES    0xffff0000
-#define BF_APBX_CHn_DEBUG2_APB_BYTES(v) (((v) << 16) & 0xffff0000)
-#define BP_APBX_CHn_DEBUG2_AHB_BYTES    0
-#define BM_APBX_CHn_DEBUG2_AHB_BYTES    0xffff
-#define BF_APBX_CHn_DEBUG2_AHB_BYTES(v) (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_APBX_CHn_BAR
- * Address: 0x60+n*0x70
- * SCT: no
-*/
-#define HW_APBX_CHn_BAR(n)          (*(volatile unsigned long *)(REGS_APBX_BASE + 0x60+(n)*0x70))
-#define BP_APBX_CHn_BAR_ADDRESS     0
-#define BM_APBX_CHn_BAR_ADDRESS     0xffffffff
-#define BF_APBX_CHn_BAR_ADDRESS(v)  (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_APBX_CHn_CMD
- * Address: 0x50+n*0x70
- * SCT: no
-*/
-#define HW_APBX_CHn_CMD(n)                      (*(volatile unsigned long *)(REGS_APBX_BASE + 0x50+(n)*0x70))
-#define BP_APBX_CHn_CMD_XFER_COUNT              16
-#define BM_APBX_CHn_CMD_XFER_COUNT              0xffff0000
-#define BF_APBX_CHn_CMD_XFER_COUNT(v)           (((v) << 16) & 0xffff0000)
-#define BP_APBX_CHn_CMD_CMDWORDS                12
-#define BM_APBX_CHn_CMD_CMDWORDS                0xf000
-#define BF_APBX_CHn_CMD_CMDWORDS(v)             (((v) << 12) & 0xf000)
-#define BP_APBX_CHn_CMD_WAIT4ENDCMD             7
-#define BM_APBX_CHn_CMD_WAIT4ENDCMD             0x80
-#define BF_APBX_CHn_CMD_WAIT4ENDCMD(v)          (((v) << 7) & 0x80)
-#define BP_APBX_CHn_CMD_SEMAPHORE               6
-#define BM_APBX_CHn_CMD_SEMAPHORE               0x40
-#define BF_APBX_CHn_CMD_SEMAPHORE(v)            (((v) << 6) & 0x40)
-#define BP_APBX_CHn_CMD_IRQONCMPLT              3
-#define BM_APBX_CHn_CMD_IRQONCMPLT              0x8
-#define BF_APBX_CHn_CMD_IRQONCMPLT(v)           (((v) << 3) & 0x8)
-#define BP_APBX_CHn_CMD_CHAIN                   2
-#define BM_APBX_CHn_CMD_CHAIN                   0x4
-#define BF_APBX_CHn_CMD_CHAIN(v)                (((v) << 2) & 0x4)
-#define BP_APBX_CHn_CMD_COMMAND                 0
-#define BM_APBX_CHn_CMD_COMMAND                 0x3
-#define BV_APBX_CHn_CMD_COMMAND__NO_DMA_XFER    0x0
-#define BV_APBX_CHn_CMD_COMMAND__DMA_WRITE      0x1
-#define BV_APBX_CHn_CMD_COMMAND__DMA_READ       0x2
-#define BF_APBX_CHn_CMD_COMMAND(v)              (((v) << 0) & 0x3)
-#define BF_APBX_CHn_CMD_COMMAND_V(v)            ((BV_APBX_CHn_CMD_COMMAND__##v << 0) & 0x3)
-
-/**
- * Register: HW_APBX_CHn_DEBUG1
- * Address: 0x80+n*0x70
- * SCT: no
-*/
-#define HW_APBX_CHn_DEBUG1(n)                           (*(volatile unsigned long *)(REGS_APBX_BASE + 0x80+(n)*0x70))
-#define BP_APBX_CHn_DEBUG1_REQ                          31
-#define BM_APBX_CHn_DEBUG1_REQ                          0x80000000
-#define BF_APBX_CHn_DEBUG1_REQ(v)                       (((v) << 31) & 0x80000000)
-#define BP_APBX_CHn_DEBUG1_BURST                        30
-#define BM_APBX_CHn_DEBUG1_BURST                        0x40000000
-#define BF_APBX_CHn_DEBUG1_BURST(v)                     (((v) << 30) & 0x40000000)
-#define BP_APBX_CHn_DEBUG1_KICK                         29
-#define BM_APBX_CHn_DEBUG1_KICK                         0x20000000
-#define BF_APBX_CHn_DEBUG1_KICK(v)                      (((v) << 29) & 0x20000000)
-#define BP_APBX_CHn_DEBUG1_END                          28
-#define BM_APBX_CHn_DEBUG1_END                          0x10000000
-#define BF_APBX_CHn_DEBUG1_END(v)                       (((v) << 28) & 0x10000000)
-#define BP_APBX_CHn_DEBUG1_RSVD2                        25
-#define BM_APBX_CHn_DEBUG1_RSVD2                        0xe000000
-#define BF_APBX_CHn_DEBUG1_RSVD2(v)                     (((v) << 25) & 0xe000000)
-#define BP_APBX_CHn_DEBUG1_NEXTCMDADDRVALID             24
-#define BM_APBX_CHn_DEBUG1_NEXTCMDADDRVALID             0x1000000
-#define BF_APBX_CHn_DEBUG1_NEXTCMDADDRVALID(v)          (((v) << 24) & 0x1000000)
-#define BP_APBX_CHn_DEBUG1_RD_FIFO_EMPTY                23
-#define BM_APBX_CHn_DEBUG1_RD_FIFO_EMPTY                0x800000
-#define BF_APBX_CHn_DEBUG1_RD_FIFO_EMPTY(v)             (((v) << 23) & 0x800000)
-#define BP_APBX_CHn_DEBUG1_RD_FIFO_FULL                 22
-#define BM_APBX_CHn_DEBUG1_RD_FIFO_FULL                 0x400000
-#define BF_APBX_CHn_DEBUG1_RD_FIFO_FULL(v)              (((v) << 22) & 0x400000)
-#define BP_APBX_CHn_DEBUG1_WR_FIFO_EMPTY                21
-#define BM_APBX_CHn_DEBUG1_WR_FIFO_EMPTY                0x200000
-#define BF_APBX_CHn_DEBUG1_WR_FIFO_EMPTY(v)             (((v) << 21) & 0x200000)
-#define BP_APBX_CHn_DEBUG1_WR_FIFO_FULL                 20
-#define BM_APBX_CHn_DEBUG1_WR_FIFO_FULL                 0x100000
-#define BF_APBX_CHn_DEBUG1_WR_FIFO_FULL(v)              (((v) << 20) & 0x100000)
-#define BP_APBX_CHn_DEBUG1_RSVD1                        5
-#define BM_APBX_CHn_DEBUG1_RSVD1                        0xfffe0
-#define BF_APBX_CHn_DEBUG1_RSVD1(v)                     (((v) << 5) & 0xfffe0)
-#define BP_APBX_CHn_DEBUG1_STATEMACHINE                 0
-#define BM_APBX_CHn_DEBUG1_STATEMACHINE                 0x1f
-#define BV_APBX_CHn_DEBUG1_STATEMACHINE__IDLE           0x0
-#define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD1       0x1
-#define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD3       0x2
-#define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD2       0x3
-#define BV_APBX_CHn_DEBUG1_STATEMACHINE__XFER_DECODE    0x4
-#define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_WAIT       0x5
-#define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD4       0x6
-#define BV_APBX_CHn_DEBUG1_STATEMACHINE__PIO_REQ        0x7
-#define BV_APBX_CHn_DEBUG1_STATEMACHINE__READ_FLUSH     0x8
-#define BV_APBX_CHn_DEBUG1_STATEMACHINE__READ_WAIT      0x9
-#define BV_APBX_CHn_DEBUG1_STATEMACHINE__WRITE          0xc
-#define BV_APBX_CHn_DEBUG1_STATEMACHINE__READ_REQ       0xd
-#define BV_APBX_CHn_DEBUG1_STATEMACHINE__CHECK_CHAIN    0xe
-#define BV_APBX_CHn_DEBUG1_STATEMACHINE__XFER_COMPLETE  0xf
-#define BV_APBX_CHn_DEBUG1_STATEMACHINE__WAIT_END       0x15
-#define BV_APBX_CHn_DEBUG1_STATEMACHINE__WRITE_WAIT     0x1c
-#define BV_APBX_CHn_DEBUG1_STATEMACHINE__CHECK_WAIT     0x1e
-#define BF_APBX_CHn_DEBUG1_STATEMACHINE(v)              (((v) << 0) & 0x1f)
-#define BF_APBX_CHn_DEBUG1_STATEMACHINE_V(v)            ((BV_APBX_CHn_DEBUG1_STATEMACHINE__##v << 0) & 0x1f)
-
-/**
- * Register: HW_APBX_CHn_SEMA
- * Address: 0x70+n*0x70
- * SCT: no
-*/
-#define HW_APBX_CHn_SEMA(n)                 (*(volatile unsigned long *)(REGS_APBX_BASE + 0x70+(n)*0x70))
-#define BP_APBX_CHn_SEMA_PHORE              16
-#define BM_APBX_CHn_SEMA_PHORE              0xff0000
-#define BF_APBX_CHn_SEMA_PHORE(v)           (((v) << 16) & 0xff0000)
-#define BP_APBX_CHn_SEMA_INCREMENT_SEMA     0
-#define BM_APBX_CHn_SEMA_INCREMENT_SEMA     0xff
-#define BF_APBX_CHn_SEMA_INCREMENT_SEMA(v)  (((v) << 0) & 0xff)
-
-/**
- * Register: HW_APBX_CHn_CURCMDAR
- * Address: 0x30+n*0x70
- * SCT: no
-*/
-#define HW_APBX_CHn_CURCMDAR(n)             (*(volatile unsigned long *)(REGS_APBX_BASE + 0x30+(n)*0x70))
-#define BP_APBX_CHn_CURCMDAR_CMD_ADDR       0
-#define BM_APBX_CHn_CURCMDAR_CMD_ADDR       0xffffffff
-#define BF_APBX_CHn_CURCMDAR_CMD_ADDR(v)    (((v) << 0) & 0xffffffff)
-
-#endif /* __HEADERGEN__STMP3600__APBX__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-arc.h b/firmware/target/arm/imx233/regs/stmp3600/regs-arc.h
deleted file mode 100644
index 9b0e22066c..0000000000
--- a/firmware/target/arm/imx233/regs/stmp3600/regs-arc.h
+++ /dev/null
@@ -1,268 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3600:2.3.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__STMP3600__ARC__H__
-#define __HEADERGEN__STMP3600__ARC__H__
-
-#define REGS_ARC_BASE (0x80080000)
-
-#define REGS_ARC_VERSION "2.3.0"
-
-/**
- * Register: HW_ARC_BASE
- * Address: 0
- * SCT: no
-*/
-#define HW_ARC_BASE (*(volatile unsigned long *)(REGS_ARC_BASE + 0x0))
-
-/**
- * Register: HW_ARC_ID
- * Address: 0
- * SCT: no
-*/
-#define HW_ARC_ID   (*(volatile unsigned long *)(REGS_ARC_BASE + 0x0))
-
-/**
- * Register: HW_ARC_HCSPARAMS
- * Address: 0x104
- * SCT: no
-*/
-#define HW_ARC_HCSPARAMS    (*(volatile unsigned long *)(REGS_ARC_BASE + 0x104))
-
-/**
- * Register: HW_ARC_USBCMD
- * Address: 0x140
- * SCT: no
-*/
-#define HW_ARC_USBCMD   (*(volatile unsigned long *)(REGS_ARC_BASE + 0x140))
-
-/**
- * Register: HW_ARC_USBSTS
- * Address: 0x144
- * SCT: no
-*/
-#define HW_ARC_USBSTS   (*(volatile unsigned long *)(REGS_ARC_BASE + 0x144))
-
-/**
- * Register: HW_ARC_USBINTR
- * Address: 0x148
- * SCT: no
-*/
-#define HW_ARC_USBINTR  (*(volatile unsigned long *)(REGS_ARC_BASE + 0x148))
-
-/**
- * Register: HW_ARC_FRINDEX
- * Address: 0x14c
- * SCT: no
-*/
-#define HW_ARC_FRINDEX  (*(volatile unsigned long *)(REGS_ARC_BASE + 0x14c))
-
-/**
- * Register: HW_ARC_DEVADDR
- * Address: 0x154
- * SCT: no
-*/
-#define HW_ARC_DEVADDR  (*(volatile unsigned long *)(REGS_ARC_BASE + 0x154))
-
-/**
- * Register: HW_ARC_ENDPTLISTADDR
- * Address: 0x158
- * SCT: no
-*/
-#define HW_ARC_ENDPTLISTADDR    (*(volatile unsigned long *)(REGS_ARC_BASE + 0x158))
-
-/**
- * Register: HW_ARC_PORTSC1
- * Address: 0x184
- * SCT: no
-*/
-#define HW_ARC_PORTSC1  (*(volatile unsigned long *)(REGS_ARC_BASE + 0x184))
-
-/**
- * Register: HW_ARC_OTGSC
- * Address: 0x1a4
- * SCT: no
-*/
-#define HW_ARC_OTGSC    (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1a4))
-
-/**
- * Register: HW_ARC_USBMODE
- * Address: 0x1a8
- * SCT: no
-*/
-#define HW_ARC_USBMODE  (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1a8))
-
-/**
- * Register: HW_ARC_ENDPTSETUPSTAT
- * Address: 0x1ac
- * SCT: no
-*/
-#define HW_ARC_ENDPTSETUPSTAT   (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1ac))
-
-/**
- * Register: HW_ARC_ENDPTPRIME
- * Address: 0x1b0
- * SCT: no
-*/
-#define HW_ARC_ENDPTPRIME   (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1b0))
-
-/**
- * Register: HW_ARC_ENDPTFLUSH
- * Address: 0x1b4
- * SCT: no
-*/
-#define HW_ARC_ENDPTFLUSH   (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1b4))
-
-/**
- * Register: HW_ARC_ENDPTSTATUS
- * Address: 0x1b8
- * SCT: no
-*/
-#define HW_ARC_ENDPTSTATUS  (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1b8))
-
-/**
- * Register: HW_ARC_ENDPTCOMPLETE
- * Address: 0x1bc
- * SCT: no
-*/
-#define HW_ARC_ENDPTCOMPLETE    (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1bc))
-
-/**
- * Register: HW_ARC_ENDPTCTRL0
- * Address: 0x1c0
- * SCT: no
-*/
-#define HW_ARC_ENDPTCTRL0   (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1c0))
-
-/**
- * Register: HW_ARC_ENDPTCTRL1
- * Address: 0x1c4
- * SCT: no
-*/
-#define HW_ARC_ENDPTCTRL1   (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1c4))
-
-/**
- * Register: HW_ARC_ENDPTCTRL2
- * Address: 0x1c8
- * SCT: no
-*/
-#define HW_ARC_ENDPTCTRL2   (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1c8))
-
-/**
- * Register: HW_ARC_ENDPTCTRL3
- * Address: 0x1cc
- * SCT: no
-*/
-#define HW_ARC_ENDPTCTRL3   (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1cc))
-
-/**
- * Register: HW_ARC_ENDPTCTRL4
- * Address: 0x1d0
- * SCT: no
-*/
-#define HW_ARC_ENDPTCTRL4   (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1d0))
-
-/**
- * Register: HW_ARC_ENDPTCTRL5
- * Address: 0x1d4
- * SCT: no
-*/
-#define HW_ARC_ENDPTCTRL5   (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1d4))
-
-/**
- * Register: HW_ARC_ENDPTCTRL6
- * Address: 0x1d8
- * SCT: no
-*/
-#define HW_ARC_ENDPTCTRL6   (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1d8))
-
-/**
- * Register: HW_ARC_ENDPTCTRL7
- * Address: 0x1dc
- * SCT: no
-*/
-#define HW_ARC_ENDPTCTRL7   (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1dc))
-
-/**
- * Register: HW_ARC_ENDPTCTRL8
- * Address: 0x1e0
- * SCT: no
-*/
-#define HW_ARC_ENDPTCTRL8   (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1e0))
-
-/**
- * Register: HW_ARC_ENDPTCTRL9
- * Address: 0x1e4
- * SCT: no
-*/
-#define HW_ARC_ENDPTCTRL9   (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1e4))
-
-/**
- * Register: HW_ARC_ENDPTCTRL10
- * Address: 0x1e8
- * SCT: no
-*/
-#define HW_ARC_ENDPTCTRL10  (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1e8))
-
-/**
- * Register: HW_ARC_ENDPTCTRL11
- * Address: 0x1ec
- * SCT: no
-*/
-#define HW_ARC_ENDPTCTRL11  (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1ec))
-
-/**
- * Register: HW_ARC_ENDPTCTRL12
- * Address: 0x1f0
- * SCT: no
-*/
-#define HW_ARC_ENDPTCTRL12  (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1f0))
-
-/**
- * Register: HW_ARC_ENDPTCTRL13
- * Address: 0x1f4
- * SCT: no
-*/
-#define HW_ARC_ENDPTCTRL13  (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1f4))
-
-/**
- * Register: HW_ARC_ENDPTCTRL14
- * Address: 0x1f8
- * SCT: no
-*/
-#define HW_ARC_ENDPTCTRL14  (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1f8))
-
-/**
- * Register: HW_ARC_ENDPTCTRL15
- * Address: 0x1fc
- * SCT: no
-*/
-#define HW_ARC_ENDPTCTRL15  (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1fc))
-
-/**
- * Register: HW_ARC_ENDPTCTRLn
- * Address: 0x1c0+n*0x4
- * SCT: no
-*/
-#define HW_ARC_ENDPTCTRLn(n)    (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1c0+(n)*0x4))
-
-#endif /* __HEADERGEN__STMP3600__ARC__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-audioin.h b/firmware/target/arm/imx233/regs/stmp3600/regs-audioin.h
deleted file mode 100644
index cea691f024..0000000000
--- a/firmware/target/arm/imx233/regs/stmp3600/regs-audioin.h
+++ /dev/null
@@ -1,281 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3600:2.5.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__STMP3600__AUDIOIN__H__
-#define __HEADERGEN__STMP3600__AUDIOIN__H__
-
-#define REGS_AUDIOIN_BASE (0x8004c000)
-
-#define REGS_AUDIOIN_VERSION "2.5.0"
-
-/**
- * Register: HW_AUDIOIN_CTRL
- * Address: 0
- * SCT: yes
-*/
-#define HW_AUDIOIN_CTRL                         (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x0 + 0x0))
-#define HW_AUDIOIN_CTRL_SET                     (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x0 + 0x4))
-#define HW_AUDIOIN_CTRL_CLR                     (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x0 + 0x8))
-#define HW_AUDIOIN_CTRL_TOG                     (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x0 + 0xc))
-#define BP_AUDIOIN_CTRL_SFTRST                  31
-#define BM_AUDIOIN_CTRL_SFTRST                  0x80000000
-#define BF_AUDIOIN_CTRL_SFTRST(v)               (((v) << 31) & 0x80000000)
-#define BP_AUDIOIN_CTRL_CLKGATE                 30
-#define BM_AUDIOIN_CTRL_CLKGATE                 0x40000000
-#define BF_AUDIOIN_CTRL_CLKGATE(v)              (((v) << 30) & 0x40000000)
-#define BP_AUDIOIN_CTRL_DMAWAIT_COUNT           16
-#define BM_AUDIOIN_CTRL_DMAWAIT_COUNT           0x1f0000
-#define BF_AUDIOIN_CTRL_DMAWAIT_COUNT(v)        (((v) << 16) & 0x1f0000)
-#define BP_AUDIOIN_CTRL_LR_SWAP                 10
-#define BM_AUDIOIN_CTRL_LR_SWAP                 0x400
-#define BF_AUDIOIN_CTRL_LR_SWAP(v)              (((v) << 10) & 0x400)
-#define BP_AUDIOIN_CTRL_EDGE_SYNC               9
-#define BM_AUDIOIN_CTRL_EDGE_SYNC               0x200
-#define BF_AUDIOIN_CTRL_EDGE_SYNC(v)            (((v) << 9) & 0x200)
-#define BP_AUDIOIN_CTRL_INVERT_1BIT             8
-#define BM_AUDIOIN_CTRL_INVERT_1BIT             0x100
-#define BF_AUDIOIN_CTRL_INVERT_1BIT(v)          (((v) << 8) & 0x100)
-#define BP_AUDIOIN_CTRL_OFFSET_ENABLE           7
-#define BM_AUDIOIN_CTRL_OFFSET_ENABLE           0x80
-#define BF_AUDIOIN_CTRL_OFFSET_ENABLE(v)        (((v) << 7) & 0x80)
-#define BP_AUDIOIN_CTRL_HPF_ENABLE              6
-#define BM_AUDIOIN_CTRL_HPF_ENABLE              0x40
-#define BF_AUDIOIN_CTRL_HPF_ENABLE(v)           (((v) << 6) & 0x40)
-#define BP_AUDIOIN_CTRL_WORD_LENGTH             5
-#define BM_AUDIOIN_CTRL_WORD_LENGTH             0x20
-#define BF_AUDIOIN_CTRL_WORD_LENGTH(v)          (((v) << 5) & 0x20)
-#define BP_AUDIOIN_CTRL_LOOPBACK                4
-#define BM_AUDIOIN_CTRL_LOOPBACK                0x10
-#define BF_AUDIOIN_CTRL_LOOPBACK(v)             (((v) << 4) & 0x10)
-#define BP_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ      3
-#define BM_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ      0x8
-#define BF_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ(v)   (((v) << 3) & 0x8)
-#define BP_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ       2
-#define BM_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ       0x4
-#define BF_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ(v)    (((v) << 2) & 0x4)
-#define BP_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN       1
-#define BM_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN       0x2
-#define BF_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN(v)    (((v) << 1) & 0x2)
-#define BP_AUDIOIN_CTRL_RUN                     0
-#define BM_AUDIOIN_CTRL_RUN                     0x1
-#define BF_AUDIOIN_CTRL_RUN(v)                  (((v) << 0) & 0x1)
-
-/**
- * Register: HW_AUDIOIN_STAT
- * Address: 0x10
- * SCT: no
-*/
-#define HW_AUDIOIN_STAT                 (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x10))
-#define BP_AUDIOIN_STAT_ADC_PRESENT     31
-#define BM_AUDIOIN_STAT_ADC_PRESENT     0x80000000
-#define BF_AUDIOIN_STAT_ADC_PRESENT(v)  (((v) << 31) & 0x80000000)
-
-/**
- * Register: HW_AUDIOIN_ADCSRR
- * Address: 0x20
- * SCT: yes
-*/
-#define HW_AUDIOIN_ADCSRR                       (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x20 + 0x0))
-#define HW_AUDIOIN_ADCSRR_SET                   (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x20 + 0x4))
-#define HW_AUDIOIN_ADCSRR_CLR                   (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x20 + 0x8))
-#define HW_AUDIOIN_ADCSRR_TOG                   (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x20 + 0xc))
-#define BP_AUDIOIN_ADCSRR_OSR                   31
-#define BM_AUDIOIN_ADCSRR_OSR                   0x80000000
-#define BV_AUDIOIN_ADCSRR_OSR__OSR6             0x0
-#define BV_AUDIOIN_ADCSRR_OSR__OSR12            0x1
-#define BF_AUDIOIN_ADCSRR_OSR(v)                (((v) << 31) & 0x80000000)
-#define BF_AUDIOIN_ADCSRR_OSR_V(v)              ((BV_AUDIOIN_ADCSRR_OSR__##v << 31) & 0x80000000)
-#define BP_AUDIOIN_ADCSRR_BASEMULT              28
-#define BM_AUDIOIN_ADCSRR_BASEMULT              0x70000000
-#define BV_AUDIOIN_ADCSRR_BASEMULT__SINGLE_RATE 0x1
-#define BV_AUDIOIN_ADCSRR_BASEMULT__DOUBLE_RATE 0x2
-#define BV_AUDIOIN_ADCSRR_BASEMULT__QUAD_RATE   0x4
-#define BF_AUDIOIN_ADCSRR_BASEMULT(v)           (((v) << 28) & 0x70000000)
-#define BF_AUDIOIN_ADCSRR_BASEMULT_V(v)         ((BV_AUDIOIN_ADCSRR_BASEMULT__##v << 28) & 0x70000000)
-#define BP_AUDIOIN_ADCSRR_SRC_HOLD              24
-#define BM_AUDIOIN_ADCSRR_SRC_HOLD              0x7000000
-#define BF_AUDIOIN_ADCSRR_SRC_HOLD(v)           (((v) << 24) & 0x7000000)
-#define BP_AUDIOIN_ADCSRR_SRC_INT               16
-#define BM_AUDIOIN_ADCSRR_SRC_INT               0x1f0000
-#define BF_AUDIOIN_ADCSRR_SRC_INT(v)            (((v) << 16) & 0x1f0000)
-#define BP_AUDIOIN_ADCSRR_SRC_FRAC              0
-#define BM_AUDIOIN_ADCSRR_SRC_FRAC              0x1fff
-#define BF_AUDIOIN_ADCSRR_SRC_FRAC(v)           (((v) << 0) & 0x1fff)
-
-/**
- * Register: HW_AUDIOIN_ADCVOLUME
- * Address: 0x30
- * SCT: yes
-*/
-#define HW_AUDIOIN_ADCVOLUME                        (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x30 + 0x0))
-#define HW_AUDIOIN_ADCVOLUME_SET                    (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x30 + 0x4))
-#define HW_AUDIOIN_ADCVOLUME_CLR                    (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x30 + 0x8))
-#define HW_AUDIOIN_ADCVOLUME_TOG                    (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x30 + 0xc))
-#define BP_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_LEFT     28
-#define BM_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_LEFT     0x10000000
-#define BF_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_LEFT(v)  (((v) << 28) & 0x10000000)
-#define BP_AUDIOIN_ADCVOLUME_EN_ZCD                 25
-#define BM_AUDIOIN_ADCVOLUME_EN_ZCD                 0x2000000
-#define BF_AUDIOIN_ADCVOLUME_EN_ZCD(v)              (((v) << 25) & 0x2000000)
-#define BP_AUDIOIN_ADCVOLUME_VOLUME_LEFT            16
-#define BM_AUDIOIN_ADCVOLUME_VOLUME_LEFT            0xff0000
-#define BF_AUDIOIN_ADCVOLUME_VOLUME_LEFT(v)         (((v) << 16) & 0xff0000)
-#define BP_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_RIGHT    12
-#define BM_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_RIGHT    0x1000
-#define BF_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_RIGHT(v) (((v) << 12) & 0x1000)
-#define BP_AUDIOIN_ADCVOLUME_VOLUME_RIGHT           0
-#define BM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT           0xff
-#define BF_AUDIOIN_ADCVOLUME_VOLUME_RIGHT(v)        (((v) << 0) & 0xff)
-
-/**
- * Register: HW_AUDIOIN_ADCDEBUG
- * Address: 0x40
- * SCT: yes
-*/
-#define HW_AUDIOIN_ADCDEBUG                                     (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x40 + 0x0))
-#define HW_AUDIOIN_ADCDEBUG_SET                                 (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x40 + 0x4))
-#define HW_AUDIOIN_ADCDEBUG_CLR                                 (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x40 + 0x8))
-#define HW_AUDIOIN_ADCDEBUG_TOG                                 (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x40 + 0xc))
-#define BP_AUDIOIN_ADCDEBUG_ENABLE_ADCDMA                       31
-#define BM_AUDIOIN_ADCDEBUG_ENABLE_ADCDMA                       0x80000000
-#define BF_AUDIOIN_ADCDEBUG_ENABLE_ADCDMA(v)                    (((v) << 31) & 0x80000000)
-#define BP_AUDIOIN_ADCDEBUG_ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS    3
-#define BM_AUDIOIN_ADCDEBUG_ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS    0x8
-#define BF_AUDIOIN_ADCDEBUG_ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS(v) (((v) << 3) & 0x8)
-#define BP_AUDIOIN_ADCDEBUG_SET_INTERRUPT3_HAND_SHAKE           2
-#define BM_AUDIOIN_ADCDEBUG_SET_INTERRUPT3_HAND_SHAKE           0x4
-#define BF_AUDIOIN_ADCDEBUG_SET_INTERRUPT3_HAND_SHAKE(v)        (((v) << 2) & 0x4)
-#define BP_AUDIOIN_ADCDEBUG_DMA_PREQ                            1
-#define BM_AUDIOIN_ADCDEBUG_DMA_PREQ                            0x2
-#define BF_AUDIOIN_ADCDEBUG_DMA_PREQ(v)                         (((v) << 1) & 0x2)
-#define BP_AUDIOIN_ADCDEBUG_FIFO_STATUS                         0
-#define BM_AUDIOIN_ADCDEBUG_FIFO_STATUS                         0x1
-#define BF_AUDIOIN_ADCDEBUG_FIFO_STATUS(v)                      (((v) << 0) & 0x1)
-
-/**
- * Register: HW_AUDIOIN_ADCVOL
- * Address: 0x50
- * SCT: yes
-*/
-#define HW_AUDIOIN_ADCVOL                   (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x50 + 0x0))
-#define HW_AUDIOIN_ADCVOL_SET               (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x50 + 0x4))
-#define HW_AUDIOIN_ADCVOL_CLR               (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x50 + 0x8))
-#define HW_AUDIOIN_ADCVOL_TOG               (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x50 + 0xc))
-#define BP_AUDIOIN_ADCVOL_SELECT_LEFT       28
-#define BM_AUDIOIN_ADCVOL_SELECT_LEFT       0x30000000
-#define BF_AUDIOIN_ADCVOL_SELECT_LEFT(v)    (((v) << 28) & 0x30000000)
-#define BP_AUDIOIN_ADCVOL_SELECT_RIGHT      24
-#define BM_AUDIOIN_ADCVOL_SELECT_RIGHT      0x3000000
-#define BF_AUDIOIN_ADCVOL_SELECT_RIGHT(v)   (((v) << 24) & 0x3000000)
-#define BP_AUDIOIN_ADCVOL_MUTE              8
-#define BM_AUDIOIN_ADCVOL_MUTE              0x100
-#define BF_AUDIOIN_ADCVOL_MUTE(v)           (((v) << 8) & 0x100)
-#define BP_AUDIOIN_ADCVOL_GAIN_LEFT         4
-#define BM_AUDIOIN_ADCVOL_GAIN_LEFT         0xf0
-#define BF_AUDIOIN_ADCVOL_GAIN_LEFT(v)      (((v) << 4) & 0xf0)
-#define BP_AUDIOIN_ADCVOL_GAIN_RIGHT        0
-#define BM_AUDIOIN_ADCVOL_GAIN_RIGHT        0xf
-#define BF_AUDIOIN_ADCVOL_GAIN_RIGHT(v)     (((v) << 0) & 0xf)
-
-/**
- * Register: HW_AUDIOIN_MICLINE
- * Address: 0x60
- * SCT: yes
-*/
-#define HW_AUDIOIN_MICLINE                          (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x60 + 0x0))
-#define HW_AUDIOIN_MICLINE_SET                      (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x60 + 0x4))
-#define HW_AUDIOIN_MICLINE_CLR                      (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x60 + 0x8))
-#define HW_AUDIOIN_MICLINE_TOG                      (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x60 + 0xc))
-#define BP_AUDIOIN_MICLINE_ATTEN_LINE               30
-#define BM_AUDIOIN_MICLINE_ATTEN_LINE               0x40000000
-#define BF_AUDIOIN_MICLINE_ATTEN_LINE(v)            (((v) << 30) & 0x40000000)
-#define BP_AUDIOIN_MICLINE_DIVIDE_LINE1             29
-#define BM_AUDIOIN_MICLINE_DIVIDE_LINE1             0x20000000
-#define BF_AUDIOIN_MICLINE_DIVIDE_LINE1(v)          (((v) << 29) & 0x20000000)
-#define BP_AUDIOIN_MICLINE_DIVIDE_LINE2             28
-#define BM_AUDIOIN_MICLINE_DIVIDE_LINE2             0x10000000
-#define BF_AUDIOIN_MICLINE_DIVIDE_LINE2(v)          (((v) << 28) & 0x10000000)
-#define BP_AUDIOIN_MICLINE_MIC_SELECT               24
-#define BM_AUDIOIN_MICLINE_MIC_SELECT               0x1000000
-#define BF_AUDIOIN_MICLINE_MIC_SELECT(v)            (((v) << 24) & 0x1000000)
-#define BP_AUDIOIN_MICLINE_MIC_RESISTOR             20
-#define BM_AUDIOIN_MICLINE_MIC_RESISTOR             0x300000
-#define BV_AUDIOIN_MICLINE_MIC_RESISTOR__Off        0x0
-#define BV_AUDIOIN_MICLINE_MIC_RESISTOR__2KOhm      0x1
-#define BV_AUDIOIN_MICLINE_MIC_RESISTOR__4KOhm      0x2
-#define BV_AUDIOIN_MICLINE_MIC_RESISTOR__8KOhm      0x3
-#define BF_AUDIOIN_MICLINE_MIC_RESISTOR(v)          (((v) << 20) & 0x300000)
-#define BF_AUDIOIN_MICLINE_MIC_RESISTOR_V(v)        ((BV_AUDIOIN_MICLINE_MIC_RESISTOR__##v << 20) & 0x300000)
-#define BP_AUDIOIN_MICLINE_MIC_BIAS                 16
-#define BM_AUDIOIN_MICLINE_MIC_BIAS                 0x70000
-#define BF_AUDIOIN_MICLINE_MIC_BIAS(v)              (((v) << 16) & 0x70000)
-#define BP_AUDIOIN_MICLINE_FORCE_MICAMP_PWRUP       8
-#define BM_AUDIOIN_MICLINE_FORCE_MICAMP_PWRUP       0x100
-#define BF_AUDIOIN_MICLINE_FORCE_MICAMP_PWRUP(v)    (((v) << 8) & 0x100)
-#define BP_AUDIOIN_MICLINE_MIC_GAIN                 0
-#define BM_AUDIOIN_MICLINE_MIC_GAIN                 0x3
-#define BV_AUDIOIN_MICLINE_MIC_GAIN__0dB            0x0
-#define BV_AUDIOIN_MICLINE_MIC_GAIN__20dB           0x1
-#define BV_AUDIOIN_MICLINE_MIC_GAIN__30dB           0x2
-#define BV_AUDIOIN_MICLINE_MIC_GAIN__40dB           0x3
-#define BF_AUDIOIN_MICLINE_MIC_GAIN(v)              (((v) << 0) & 0x3)
-#define BF_AUDIOIN_MICLINE_MIC_GAIN_V(v)            ((BV_AUDIOIN_MICLINE_MIC_GAIN__##v << 0) & 0x3)
-
-/**
- * Register: HW_AUDIOIN_ANACLKCTRL
- * Address: 0x70
- * SCT: yes
-*/
-#define HW_AUDIOIN_ANACLKCTRL                   (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x70 + 0x0))
-#define HW_AUDIOIN_ANACLKCTRL_SET               (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x70 + 0x4))
-#define HW_AUDIOIN_ANACLKCTRL_CLR               (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x70 + 0x8))
-#define HW_AUDIOIN_ANACLKCTRL_TOG               (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x70 + 0xc))
-#define BP_AUDIOIN_ANACLKCTRL_CLKGATE           31
-#define BM_AUDIOIN_ANACLKCTRL_CLKGATE           0x80000000
-#define BF_AUDIOIN_ANACLKCTRL_CLKGATE(v)        (((v) << 31) & 0x80000000)
-#define BP_AUDIOIN_ANACLKCTRL_DITHER_ENABLE     6
-#define BM_AUDIOIN_ANACLKCTRL_DITHER_ENABLE     0x40
-#define BF_AUDIOIN_ANACLKCTRL_DITHER_ENABLE(v)  (((v) << 6) & 0x40)
-#define BP_AUDIOIN_ANACLKCTRL_SLOW_DITHER       5
-#define BM_AUDIOIN_ANACLKCTRL_SLOW_DITHER       0x20
-#define BF_AUDIOIN_ANACLKCTRL_SLOW_DITHER(v)    (((v) << 5) & 0x20)
-#define BP_AUDIOIN_ANACLKCTRL_INVERT_ADCCLK     4
-#define BM_AUDIOIN_ANACLKCTRL_INVERT_ADCCLK     0x10
-#define BF_AUDIOIN_ANACLKCTRL_INVERT_ADCCLK(v)  (((v) << 4) & 0x10)
-#define BP_AUDIOIN_ANACLKCTRL_ADCDIV            0
-#define BM_AUDIOIN_ANACLKCTRL_ADCDIV            0x7
-#define BF_AUDIOIN_ANACLKCTRL_ADCDIV(v)         (((v) << 0) & 0x7)
-
-/**
- * Register: HW_AUDIOIN_DATA
- * Address: 0x80
- * SCT: no
-*/
-#define HW_AUDIOIN_DATA         (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x80))
-#define BP_AUDIOIN_DATA_HIGH    16
-#define BM_AUDIOIN_DATA_HIGH    0xffff0000
-#define BF_AUDIOIN_DATA_HIGH(v) (((v) << 16) & 0xffff0000)
-#define BP_AUDIOIN_DATA_LOW     0
-#define BM_AUDIOIN_DATA_LOW     0xffff
-#define BF_AUDIOIN_DATA_LOW(v)  (((v) << 0) & 0xffff)
-
-#endif /* __HEADERGEN__STMP3600__AUDIOIN__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-audioout.h b/firmware/target/arm/imx233/regs/stmp3600/regs-audioout.h
deleted file mode 100644
index abbf70706e..0000000000
--- a/firmware/target/arm/imx233/regs/stmp3600/regs-audioout.h
+++ /dev/null
@@ -1,473 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3600:2.3.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__STMP3600__AUDIOOUT__H__
-#define __HEADERGEN__STMP3600__AUDIOOUT__H__
-
-#define REGS_AUDIOOUT_BASE (0x80048000)
-
-#define REGS_AUDIOOUT_VERSION "2.3.0"
-
-/**
- * Register: HW_AUDIOOUT_CTRL
- * Address: 0
- * SCT: yes
-*/
-#define HW_AUDIOOUT_CTRL                        (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x0 + 0x0))
-#define HW_AUDIOOUT_CTRL_SET                    (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x0 + 0x4))
-#define HW_AUDIOOUT_CTRL_CLR                    (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x0 + 0x8))
-#define HW_AUDIOOUT_CTRL_TOG                    (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x0 + 0xc))
-#define BP_AUDIOOUT_CTRL_SFTRST                 31
-#define BM_AUDIOOUT_CTRL_SFTRST                 0x80000000
-#define BF_AUDIOOUT_CTRL_SFTRST(v)              (((v) << 31) & 0x80000000)
-#define BP_AUDIOOUT_CTRL_CLKGATE                30
-#define BM_AUDIOOUT_CTRL_CLKGATE                0x40000000
-#define BF_AUDIOOUT_CTRL_CLKGATE(v)             (((v) << 30) & 0x40000000)
-#define BP_AUDIOOUT_CTRL_DMAWAIT_COUNT          16
-#define BM_AUDIOOUT_CTRL_DMAWAIT_COUNT          0x1f0000
-#define BF_AUDIOOUT_CTRL_DMAWAIT_COUNT(v)       (((v) << 16) & 0x1f0000)
-#define BP_AUDIOOUT_CTRL_LR_SWAP                14
-#define BM_AUDIOOUT_CTRL_LR_SWAP                0x4000
-#define BF_AUDIOOUT_CTRL_LR_SWAP(v)             (((v) << 14) & 0x4000)
-#define BP_AUDIOOUT_CTRL_EDGE_SYNC              13
-#define BM_AUDIOOUT_CTRL_EDGE_SYNC              0x2000
-#define BF_AUDIOOUT_CTRL_EDGE_SYNC(v)           (((v) << 13) & 0x2000)
-#define BP_AUDIOOUT_CTRL_INVERT_1BIT            12
-#define BM_AUDIOOUT_CTRL_INVERT_1BIT            0x1000
-#define BF_AUDIOOUT_CTRL_INVERT_1BIT(v)         (((v) << 12) & 0x1000)
-#define BP_AUDIOOUT_CTRL_SS3D_EFFECT            8
-#define BM_AUDIOOUT_CTRL_SS3D_EFFECT            0x300
-#define BF_AUDIOOUT_CTRL_SS3D_EFFECT(v)         (((v) << 8) & 0x300)
-#define BP_AUDIOOUT_CTRL_WORD_LENGTH            6
-#define BM_AUDIOOUT_CTRL_WORD_LENGTH            0x40
-#define BF_AUDIOOUT_CTRL_WORD_LENGTH(v)         (((v) << 6) & 0x40)
-#define BP_AUDIOOUT_CTRL_DAC_ZERO_ENABLE        5
-#define BM_AUDIOOUT_CTRL_DAC_ZERO_ENABLE        0x20
-#define BF_AUDIOOUT_CTRL_DAC_ZERO_ENABLE(v)     (((v) << 5) & 0x20)
-#define BP_AUDIOOUT_CTRL_LOOPBACK               4
-#define BM_AUDIOOUT_CTRL_LOOPBACK               0x10
-#define BF_AUDIOOUT_CTRL_LOOPBACK(v)            (((v) << 4) & 0x10)
-#define BP_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ     3
-#define BM_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ     0x8
-#define BF_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ(v)  (((v) << 3) & 0x8)
-#define BP_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ      2
-#define BM_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ      0x4
-#define BF_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ(v)   (((v) << 2) & 0x4)
-#define BP_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN      1
-#define BM_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN      0x2
-#define BF_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN(v)   (((v) << 1) & 0x2)
-#define BP_AUDIOOUT_CTRL_RUN                    0
-#define BM_AUDIOOUT_CTRL_RUN                    0x1
-#define BF_AUDIOOUT_CTRL_RUN(v)                 (((v) << 0) & 0x1)
-
-/**
- * Register: HW_AUDIOOUT_STAT
- * Address: 0x10
- * SCT: no
-*/
-#define HW_AUDIOOUT_STAT                (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x10))
-#define BP_AUDIOOUT_STAT_DAC_PRESENT    31
-#define BM_AUDIOOUT_STAT_DAC_PRESENT    0x80000000
-#define BF_AUDIOOUT_STAT_DAC_PRESENT(v) (((v) << 31) & 0x80000000)
-
-/**
- * Register: HW_AUDIOOUT_DACSRR
- * Address: 0x20
- * SCT: yes
-*/
-#define HW_AUDIOOUT_DACSRR                          (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x20 + 0x0))
-#define HW_AUDIOOUT_DACSRR_SET                      (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x20 + 0x4))
-#define HW_AUDIOOUT_DACSRR_CLR                      (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x20 + 0x8))
-#define HW_AUDIOOUT_DACSRR_TOG                      (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x20 + 0xc))
-#define BP_AUDIOOUT_DACSRR_OSR                      31
-#define BM_AUDIOOUT_DACSRR_OSR                      0x80000000
-#define BV_AUDIOOUT_DACSRR_OSR__OSR6                0x0
-#define BV_AUDIOOUT_DACSRR_OSR__OSR12               0x1
-#define BF_AUDIOOUT_DACSRR_OSR(v)                   (((v) << 31) & 0x80000000)
-#define BF_AUDIOOUT_DACSRR_OSR_V(v)                 ((BV_AUDIOOUT_DACSRR_OSR__##v << 31) & 0x80000000)
-#define BP_AUDIOOUT_DACSRR_BASEMULT                 28
-#define BM_AUDIOOUT_DACSRR_BASEMULT                 0x70000000
-#define BV_AUDIOOUT_DACSRR_BASEMULT__SINGLE_RATE    0x1
-#define BV_AUDIOOUT_DACSRR_BASEMULT__DOUBLE_RATE    0x2
-#define BV_AUDIOOUT_DACSRR_BASEMULT__QUAD_RATE      0x4
-#define BF_AUDIOOUT_DACSRR_BASEMULT(v)              (((v) << 28) & 0x70000000)
-#define BF_AUDIOOUT_DACSRR_BASEMULT_V(v)            ((BV_AUDIOOUT_DACSRR_BASEMULT__##v << 28) & 0x70000000)
-#define BP_AUDIOOUT_DACSRR_SRC_HOLD                 24
-#define BM_AUDIOOUT_DACSRR_SRC_HOLD                 0x7000000
-#define BF_AUDIOOUT_DACSRR_SRC_HOLD(v)              (((v) << 24) & 0x7000000)
-#define BP_AUDIOOUT_DACSRR_SRC_INT                  16
-#define BM_AUDIOOUT_DACSRR_SRC_INT                  0x1f0000
-#define BF_AUDIOOUT_DACSRR_SRC_INT(v)               (((v) << 16) & 0x1f0000)
-#define BP_AUDIOOUT_DACSRR_SRC_FRAC                 0
-#define BM_AUDIOOUT_DACSRR_SRC_FRAC                 0x1fff
-#define BF_AUDIOOUT_DACSRR_SRC_FRAC(v)              (((v) << 0) & 0x1fff)
-
-/**
- * Register: HW_AUDIOOUT_DACVOLUME
- * Address: 0x30
- * SCT: yes
-*/
-#define HW_AUDIOOUT_DACVOLUME                           (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x30 + 0x0))
-#define HW_AUDIOOUT_DACVOLUME_SET                       (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x30 + 0x4))
-#define HW_AUDIOOUT_DACVOLUME_CLR                       (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x30 + 0x8))
-#define HW_AUDIOOUT_DACVOLUME_TOG                       (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x30 + 0xc))
-#define BP_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT        28
-#define BM_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT        0x10000000
-#define BF_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT(v)     (((v) << 28) & 0x10000000)
-#define BP_AUDIOOUT_DACVOLUME_EN_ZCD                    25
-#define BM_AUDIOOUT_DACVOLUME_EN_ZCD                    0x2000000
-#define BF_AUDIOOUT_DACVOLUME_EN_ZCD(v)                 (((v) << 25) & 0x2000000)
-#define BP_AUDIOOUT_DACVOLUME_MUTE_LEFT                 24
-#define BM_AUDIOOUT_DACVOLUME_MUTE_LEFT                 0x1000000
-#define BF_AUDIOOUT_DACVOLUME_MUTE_LEFT(v)              (((v) << 24) & 0x1000000)
-#define BP_AUDIOOUT_DACVOLUME_VOLUME_LEFT               16
-#define BM_AUDIOOUT_DACVOLUME_VOLUME_LEFT               0xff0000
-#define BF_AUDIOOUT_DACVOLUME_VOLUME_LEFT(v)            (((v) << 16) & 0xff0000)
-#define BP_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT       12
-#define BM_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT       0x1000
-#define BF_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT(v)    (((v) << 12) & 0x1000)
-#define BP_AUDIOOUT_DACVOLUME_MUTE_RIGHT                8
-#define BM_AUDIOOUT_DACVOLUME_MUTE_RIGHT                0x100
-#define BF_AUDIOOUT_DACVOLUME_MUTE_RIGHT(v)             (((v) << 8) & 0x100)
-#define BP_AUDIOOUT_DACVOLUME_VOLUME_RIGHT              0
-#define BM_AUDIOOUT_DACVOLUME_VOLUME_RIGHT              0xff
-#define BF_AUDIOOUT_DACVOLUME_VOLUME_RIGHT(v)           (((v) << 0) & 0xff)
-
-/**
- * Register: HW_AUDIOOUT_DACDEBUG
- * Address: 0x40
- * SCT: yes
-*/
-#define HW_AUDIOOUT_DACDEBUG                                (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x40 + 0x0))
-#define HW_AUDIOOUT_DACDEBUG_SET                            (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x40 + 0x4))
-#define HW_AUDIOOUT_DACDEBUG_CLR                            (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x40 + 0x8))
-#define HW_AUDIOOUT_DACDEBUG_TOG                            (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x40 + 0xc))
-#define BP_AUDIOOUT_DACDEBUG_ENABLE_DACDMA                  31
-#define BM_AUDIOOUT_DACDEBUG_ENABLE_DACDMA                  0x80000000
-#define BF_AUDIOOUT_DACDEBUG_ENABLE_DACDMA(v)               (((v) << 31) & 0x80000000)
-#define BP_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS       5
-#define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS       0x20
-#define BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS(v)    (((v) << 5) & 0x20)
-#define BP_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS       4
-#define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS       0x10
-#define BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS(v)    (((v) << 4) & 0x10)
-#define BP_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE      3
-#define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE      0x8
-#define BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE(v)   (((v) << 3) & 0x8)
-#define BP_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE      2
-#define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE      0x4
-#define BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE(v)   (((v) << 2) & 0x4)
-#define BP_AUDIOOUT_DACDEBUG_DMA_PREQ                       1
-#define BM_AUDIOOUT_DACDEBUG_DMA_PREQ                       0x2
-#define BF_AUDIOOUT_DACDEBUG_DMA_PREQ(v)                    (((v) << 1) & 0x2)
-#define BP_AUDIOOUT_DACDEBUG_FIFO_STATUS                    0
-#define BM_AUDIOOUT_DACDEBUG_FIFO_STATUS                    0x1
-#define BF_AUDIOOUT_DACDEBUG_FIFO_STATUS(v)                 (((v) << 0) & 0x1)
-
-/**
- * Register: HW_AUDIOOUT_HPVOL
- * Address: 0x50
- * SCT: yes
-*/
-#define HW_AUDIOOUT_HPVOL               (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x50 + 0x0))
-#define HW_AUDIOOUT_HPVOL_SET           (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x50 + 0x4))
-#define HW_AUDIOOUT_HPVOL_CLR           (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x50 + 0x8))
-#define HW_AUDIOOUT_HPVOL_TOG           (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x50 + 0xc))
-#define BP_AUDIOOUT_HPVOL_SELECT        24
-#define BM_AUDIOOUT_HPVOL_SELECT        0x3000000
-#define BF_AUDIOOUT_HPVOL_SELECT(v)     (((v) << 24) & 0x3000000)
-#define BP_AUDIOOUT_HPVOL_MUTE          16
-#define BM_AUDIOOUT_HPVOL_MUTE          0x10000
-#define BF_AUDIOOUT_HPVOL_MUTE(v)       (((v) << 16) & 0x10000)
-#define BP_AUDIOOUT_HPVOL_VOL_LEFT      8
-#define BM_AUDIOOUT_HPVOL_VOL_LEFT      0x1f00
-#define BF_AUDIOOUT_HPVOL_VOL_LEFT(v)   (((v) << 8) & 0x1f00)
-#define BP_AUDIOOUT_HPVOL_VOL_RIGHT     0
-#define BM_AUDIOOUT_HPVOL_VOL_RIGHT     0x1f
-#define BF_AUDIOOUT_HPVOL_VOL_RIGHT(v)  (((v) << 0) & 0x1f)
-
-/**
- * Register: HW_AUDIOOUT_SPKRVOL
- * Address: 0x60
- * SCT: yes
-*/
-#define HW_AUDIOOUT_SPKRVOL         (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x60 + 0x0))
-#define HW_AUDIOOUT_SPKRVOL_SET     (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x60 + 0x4))
-#define HW_AUDIOOUT_SPKRVOL_CLR     (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x60 + 0x8))
-#define HW_AUDIOOUT_SPKRVOL_TOG     (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x60 + 0xc))
-#define BP_AUDIOOUT_SPKRVOL_MUTE    16
-#define BM_AUDIOOUT_SPKRVOL_MUTE    0x10000
-#define BF_AUDIOOUT_SPKRVOL_MUTE(v) (((v) << 16) & 0x10000)
-#define BP_AUDIOOUT_SPKRVOL_VOL     0
-#define BM_AUDIOOUT_SPKRVOL_VOL     0xf
-#define BF_AUDIOOUT_SPKRVOL_VOL(v)  (((v) << 0) & 0xf)
-
-/**
- * Register: HW_AUDIOOUT_PWRDN
- * Address: 0x70
- * SCT: yes
-*/
-#define HW_AUDIOOUT_PWRDN               (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x70 + 0x0))
-#define HW_AUDIOOUT_PWRDN_SET           (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x70 + 0x4))
-#define HW_AUDIOOUT_PWRDN_CLR           (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x70 + 0x8))
-#define HW_AUDIOOUT_PWRDN_TOG           (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x70 + 0xc))
-#define BP_AUDIOOUT_PWRDN_SPEAKER       24
-#define BM_AUDIOOUT_PWRDN_SPEAKER       0x1000000
-#define BF_AUDIOOUT_PWRDN_SPEAKER(v)    (((v) << 24) & 0x1000000)
-#define BP_AUDIOOUT_PWRDN_SELFBIAS      20
-#define BM_AUDIOOUT_PWRDN_SELFBIAS      0x100000
-#define BF_AUDIOOUT_PWRDN_SELFBIAS(v)   (((v) << 20) & 0x100000)
-#define BP_AUDIOOUT_PWRDN_RIGHT_ADC     16
-#define BM_AUDIOOUT_PWRDN_RIGHT_ADC     0x10000
-#define BF_AUDIOOUT_PWRDN_RIGHT_ADC(v)  (((v) << 16) & 0x10000)
-#define BP_AUDIOOUT_PWRDN_DAC           12
-#define BM_AUDIOOUT_PWRDN_DAC           0x1000
-#define BF_AUDIOOUT_PWRDN_DAC(v)        (((v) << 12) & 0x1000)
-#define BP_AUDIOOUT_PWRDN_ADC           8
-#define BM_AUDIOOUT_PWRDN_ADC           0x100
-#define BF_AUDIOOUT_PWRDN_ADC(v)        (((v) << 8) & 0x100)
-#define BP_AUDIOOUT_PWRDN_CAPLESS       4
-#define BM_AUDIOOUT_PWRDN_CAPLESS       0x10
-#define BF_AUDIOOUT_PWRDN_CAPLESS(v)    (((v) << 4) & 0x10)
-#define BP_AUDIOOUT_PWRDN_HEADPHONE     0
-#define BM_AUDIOOUT_PWRDN_HEADPHONE     0x1
-#define BF_AUDIOOUT_PWRDN_HEADPHONE(v)  (((v) << 0) & 0x1)
-
-/**
- * Register: HW_AUDIOOUT_REFCTRL
- * Address: 0x80
- * SCT: yes
-*/
-#define HW_AUDIOOUT_REFCTRL                     (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x80 + 0x0))
-#define HW_AUDIOOUT_REFCTRL_SET                 (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x80 + 0x4))
-#define HW_AUDIOOUT_REFCTRL_CLR                 (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x80 + 0x8))
-#define HW_AUDIOOUT_REFCTRL_TOG                 (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x80 + 0xc))
-#define BP_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS       24
-#define BM_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS       0x1000000
-#define BF_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS(v)    (((v) << 24) & 0x1000000)
-#define BP_AUDIOOUT_REFCTRL_VBG_ADJ             20
-#define BM_AUDIOOUT_REFCTRL_VBG_ADJ             0x700000
-#define BF_AUDIOOUT_REFCTRL_VBG_ADJ(v)          (((v) << 20) & 0x700000)
-#define BP_AUDIOOUT_REFCTRL_LOW_PWR             19
-#define BM_AUDIOOUT_REFCTRL_LOW_PWR             0x80000
-#define BF_AUDIOOUT_REFCTRL_LOW_PWR(v)          (((v) << 19) & 0x80000)
-#define BP_AUDIOOUT_REFCTRL_LW_REF              18
-#define BM_AUDIOOUT_REFCTRL_LW_REF              0x40000
-#define BF_AUDIOOUT_REFCTRL_LW_REF(v)           (((v) << 18) & 0x40000)
-#define BP_AUDIOOUT_REFCTRL_BIAS_CTRL           16
-#define BM_AUDIOOUT_REFCTRL_BIAS_CTRL           0x30000
-#define BF_AUDIOOUT_REFCTRL_BIAS_CTRL(v)        (((v) << 16) & 0x30000)
-#define BP_AUDIOOUT_REFCTRL_ADJ_ADC             13
-#define BM_AUDIOOUT_REFCTRL_ADJ_ADC             0x2000
-#define BF_AUDIOOUT_REFCTRL_ADJ_ADC(v)          (((v) << 13) & 0x2000)
-#define BP_AUDIOOUT_REFCTRL_ADJ_VAG             12
-#define BM_AUDIOOUT_REFCTRL_ADJ_VAG             0x1000
-#define BF_AUDIOOUT_REFCTRL_ADJ_VAG(v)          (((v) << 12) & 0x1000)
-#define BP_AUDIOOUT_REFCTRL_ADC_REFVAL          8
-#define BM_AUDIOOUT_REFCTRL_ADC_REFVAL          0xf00
-#define BF_AUDIOOUT_REFCTRL_ADC_REFVAL(v)       (((v) << 8) & 0xf00)
-#define BP_AUDIOOUT_REFCTRL_VAG_VAL             4
-#define BM_AUDIOOUT_REFCTRL_VAG_VAL             0xf0
-#define BF_AUDIOOUT_REFCTRL_VAG_VAL(v)          (((v) << 4) & 0xf0)
-#define BP_AUDIOOUT_REFCTRL_DAC_ADJ             0
-#define BM_AUDIOOUT_REFCTRL_DAC_ADJ             0x7
-#define BF_AUDIOOUT_REFCTRL_DAC_ADJ(v)          (((v) << 0) & 0x7)
-
-/**
- * Register: HW_AUDIOOUT_ANACTRL
- * Address: 0x90
- * SCT: yes
-*/
-#define HW_AUDIOOUT_ANACTRL                     (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x90 + 0x0))
-#define HW_AUDIOOUT_ANACTRL_SET                 (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x90 + 0x4))
-#define HW_AUDIOOUT_ANACTRL_CLR                 (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x90 + 0x8))
-#define HW_AUDIOOUT_ANACTRL_TOG                 (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x90 + 0xc))
-#define BP_AUDIOOUT_ANACTRL_SHORT_CM_STS        28
-#define BM_AUDIOOUT_ANACTRL_SHORT_CM_STS        0x10000000
-#define BF_AUDIOOUT_ANACTRL_SHORT_CM_STS(v)     (((v) << 28) & 0x10000000)
-#define BP_AUDIOOUT_ANACTRL_SHORT_LR_STS        24
-#define BM_AUDIOOUT_ANACTRL_SHORT_LR_STS        0x1000000
-#define BF_AUDIOOUT_ANACTRL_SHORT_LR_STS(v)     (((v) << 24) & 0x1000000)
-#define BP_AUDIOOUT_ANACTRL_SHORTMODE_CM        20
-#define BM_AUDIOOUT_ANACTRL_SHORTMODE_CM        0x300000
-#define BF_AUDIOOUT_ANACTRL_SHORTMODE_CM(v)     (((v) << 20) & 0x300000)
-#define BP_AUDIOOUT_ANACTRL_SHORTMODE_LR        17
-#define BM_AUDIOOUT_ANACTRL_SHORTMODE_LR        0x60000
-#define BF_AUDIOOUT_ANACTRL_SHORTMODE_LR(v)     (((v) << 17) & 0x60000)
-#define BP_AUDIOOUT_ANACTRL_SHORT_LVLADJL       12
-#define BM_AUDIOOUT_ANACTRL_SHORT_LVLADJL       0x7000
-#define BF_AUDIOOUT_ANACTRL_SHORT_LVLADJL(v)    (((v) << 12) & 0x7000)
-#define BP_AUDIOOUT_ANACTRL_SHORT_LVLADJR       8
-#define BM_AUDIOOUT_ANACTRL_SHORT_LVLADJR       0x700
-#define BF_AUDIOOUT_ANACTRL_SHORT_LVLADJR(v)    (((v) << 8) & 0x700)
-#define BP_AUDIOOUT_ANACTRL_HP_HOLD_GND         5
-#define BM_AUDIOOUT_ANACTRL_HP_HOLD_GND         0x20
-#define BF_AUDIOOUT_ANACTRL_HP_HOLD_GND(v)      (((v) << 5) & 0x20)
-#define BP_AUDIOOUT_ANACTRL_HP_CLASSAB          4
-#define BM_AUDIOOUT_ANACTRL_HP_CLASSAB          0x10
-#define BF_AUDIOOUT_ANACTRL_HP_CLASSAB(v)       (((v) << 4) & 0x10)
-#define BP_AUDIOOUT_ANACTRL_EN_SPKR_ZCD         2
-#define BM_AUDIOOUT_ANACTRL_EN_SPKR_ZCD         0x4
-#define BF_AUDIOOUT_ANACTRL_EN_SPKR_ZCD(v)      (((v) << 2) & 0x4)
-#define BP_AUDIOOUT_ANACTRL_ZCD_SELECTADC       1
-#define BM_AUDIOOUT_ANACTRL_ZCD_SELECTADC       0x2
-#define BF_AUDIOOUT_ANACTRL_ZCD_SELECTADC(v)    (((v) << 1) & 0x2)
-#define BP_AUDIOOUT_ANACTRL_EN_ZCD              0
-#define BM_AUDIOOUT_ANACTRL_EN_ZCD              0x1
-#define BF_AUDIOOUT_ANACTRL_EN_ZCD(v)           (((v) << 0) & 0x1)
-
-/**
- * Register: HW_AUDIOOUT_TEST
- * Address: 0xa0
- * SCT: yes
-*/
-#define HW_AUDIOOUT_TEST                    (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xa0 + 0x0))
-#define HW_AUDIOOUT_TEST_SET                (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xa0 + 0x4))
-#define HW_AUDIOOUT_TEST_CLR                (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xa0 + 0x8))
-#define HW_AUDIOOUT_TEST_TOG                (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xa0 + 0xc))
-#define BP_AUDIOOUT_TEST_HP_ANTIPOP         28
-#define BM_AUDIOOUT_TEST_HP_ANTIPOP         0x70000000
-#define BF_AUDIOOUT_TEST_HP_ANTIPOP(v)      (((v) << 28) & 0x70000000)
-#define BP_AUDIOOUT_TEST_TM_ADCIN_TOHP      26
-#define BM_AUDIOOUT_TEST_TM_ADCIN_TOHP      0x4000000
-#define BF_AUDIOOUT_TEST_TM_ADCIN_TOHP(v)   (((v) << 26) & 0x4000000)
-#define BP_AUDIOOUT_TEST_TM_SPEAKER         25
-#define BM_AUDIOOUT_TEST_TM_SPEAKER         0x2000000
-#define BF_AUDIOOUT_TEST_TM_SPEAKER(v)      (((v) << 25) & 0x2000000)
-#define BP_AUDIOOUT_TEST_TM_HPCOMMON        24
-#define BM_AUDIOOUT_TEST_TM_HPCOMMON        0x1000000
-#define BF_AUDIOOUT_TEST_TM_HPCOMMON(v)     (((v) << 24) & 0x1000000)
-#define BP_AUDIOOUT_TEST_HP_I1_ADJ          22
-#define BM_AUDIOOUT_TEST_HP_I1_ADJ          0xc00000
-#define BF_AUDIOOUT_TEST_HP_I1_ADJ(v)       (((v) << 22) & 0xc00000)
-#define BP_AUDIOOUT_TEST_HP_IALL_ADJ        20
-#define BM_AUDIOOUT_TEST_HP_IALL_ADJ        0x300000
-#define BF_AUDIOOUT_TEST_HP_IALL_ADJ(v)     (((v) << 20) & 0x300000)
-#define BP_AUDIOOUT_TEST_SPKR_I1_ADJ        18
-#define BM_AUDIOOUT_TEST_SPKR_I1_ADJ        0xc0000
-#define BF_AUDIOOUT_TEST_SPKR_I1_ADJ(v)     (((v) << 18) & 0xc0000)
-#define BP_AUDIOOUT_TEST_SPKR_IALL_ADJ      16
-#define BM_AUDIOOUT_TEST_SPKR_IALL_ADJ      0x30000
-#define BF_AUDIOOUT_TEST_SPKR_IALL_ADJ(v)   (((v) << 16) & 0x30000)
-#define BP_AUDIOOUT_TEST_VAG_CLASSA         13
-#define BM_AUDIOOUT_TEST_VAG_CLASSA         0x2000
-#define BF_AUDIOOUT_TEST_VAG_CLASSA(v)      (((v) << 13) & 0x2000)
-#define BP_AUDIOOUT_TEST_VAG_DOUBLE_I       12
-#define BM_AUDIOOUT_TEST_VAG_DOUBLE_I       0x1000
-#define BF_AUDIOOUT_TEST_VAG_DOUBLE_I(v)    (((v) << 12) & 0x1000)
-#define BP_AUDIOOUT_TEST_HP_CHOPCLK         8
-#define BM_AUDIOOUT_TEST_HP_CHOPCLK         0x300
-#define BF_AUDIOOUT_TEST_HP_CHOPCLK(v)      (((v) << 8) & 0x300)
-#define BP_AUDIOOUT_TEST_DAC_CHOPCLK        4
-#define BM_AUDIOOUT_TEST_DAC_CHOPCLK        0x30
-#define BF_AUDIOOUT_TEST_DAC_CHOPCLK(v)     (((v) << 4) & 0x30)
-#define BP_AUDIOOUT_TEST_DAC_CLASSA         2
-#define BM_AUDIOOUT_TEST_DAC_CLASSA         0x4
-#define BF_AUDIOOUT_TEST_DAC_CLASSA(v)      (((v) << 2) & 0x4)
-#define BP_AUDIOOUT_TEST_DAC_DOUBLE_I       1
-#define BM_AUDIOOUT_TEST_DAC_DOUBLE_I       0x2
-#define BF_AUDIOOUT_TEST_DAC_DOUBLE_I(v)    (((v) << 1) & 0x2)
-#define BP_AUDIOOUT_TEST_DAC_DIS_RTZ        0
-#define BM_AUDIOOUT_TEST_DAC_DIS_RTZ        0x1
-#define BF_AUDIOOUT_TEST_DAC_DIS_RTZ(v)     (((v) << 0) & 0x1)
-
-/**
- * Register: HW_AUDIOOUT_BISTCTRL
- * Address: 0xb0
- * SCT: yes
-*/
-#define HW_AUDIOOUT_BISTCTRL            (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xb0 + 0x0))
-#define HW_AUDIOOUT_BISTCTRL_SET        (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xb0 + 0x4))
-#define HW_AUDIOOUT_BISTCTRL_CLR        (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xb0 + 0x8))
-#define HW_AUDIOOUT_BISTCTRL_TOG        (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xb0 + 0xc))
-#define BP_AUDIOOUT_BISTCTRL_FAIL       3
-#define BM_AUDIOOUT_BISTCTRL_FAIL       0x8
-#define BF_AUDIOOUT_BISTCTRL_FAIL(v)    (((v) << 3) & 0x8)
-#define BP_AUDIOOUT_BISTCTRL_PASS       2
-#define BM_AUDIOOUT_BISTCTRL_PASS       0x4
-#define BF_AUDIOOUT_BISTCTRL_PASS(v)    (((v) << 2) & 0x4)
-#define BP_AUDIOOUT_BISTCTRL_DONE       1
-#define BM_AUDIOOUT_BISTCTRL_DONE       0x2
-#define BF_AUDIOOUT_BISTCTRL_DONE(v)    (((v) << 1) & 0x2)
-#define BP_AUDIOOUT_BISTCTRL_START      0
-#define BM_AUDIOOUT_BISTCTRL_START      0x1
-#define BF_AUDIOOUT_BISTCTRL_START(v)   (((v) << 0) & 0x1)
-
-/**
- * Register: HW_AUDIOOUT_BISTSTAT0
- * Address: 0xc0
- * SCT: no
-*/
-#define HW_AUDIOOUT_BISTSTAT0           (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xc0))
-#define BP_AUDIOOUT_BISTSTAT0_DATA      0
-#define BM_AUDIOOUT_BISTSTAT0_DATA      0xffffff
-#define BF_AUDIOOUT_BISTSTAT0_DATA(v)   (((v) << 0) & 0xffffff)
-
-/**
- * Register: HW_AUDIOOUT_BISTSTAT1
- * Address: 0xd0
- * SCT: no
-*/
-#define HW_AUDIOOUT_BISTSTAT1           (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xd0))
-#define BP_AUDIOOUT_BISTSTAT1_STATE     24
-#define BM_AUDIOOUT_BISTSTAT1_STATE     0x1f000000
-#define BF_AUDIOOUT_BISTSTAT1_STATE(v)  (((v) << 24) & 0x1f000000)
-#define BP_AUDIOOUT_BISTSTAT1_ADDR      0
-#define BM_AUDIOOUT_BISTSTAT1_ADDR      0xff
-#define BF_AUDIOOUT_BISTSTAT1_ADDR(v)   (((v) << 0) & 0xff)
-
-/**
- * Register: HW_AUDIOOUT_ANACLKCTRL
- * Address: 0xe0
- * SCT: yes
-*/
-#define HW_AUDIOOUT_ANACLKCTRL                  (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xe0 + 0x0))
-#define HW_AUDIOOUT_ANACLKCTRL_SET              (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xe0 + 0x4))
-#define HW_AUDIOOUT_ANACLKCTRL_CLR              (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xe0 + 0x8))
-#define HW_AUDIOOUT_ANACLKCTRL_TOG              (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xe0 + 0xc))
-#define BP_AUDIOOUT_ANACLKCTRL_CLKGATE          31
-#define BM_AUDIOOUT_ANACLKCTRL_CLKGATE          0x80000000
-#define BF_AUDIOOUT_ANACLKCTRL_CLKGATE(v)       (((v) << 31) & 0x80000000)
-#define BP_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK    4
-#define BM_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK    0x10
-#define BF_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK(v) (((v) << 4) & 0x10)
-#define BP_AUDIOOUT_ANACLKCTRL_DACDIV           0
-#define BM_AUDIOOUT_ANACLKCTRL_DACDIV           0x7
-#define BF_AUDIOOUT_ANACLKCTRL_DACDIV(v)        (((v) << 0) & 0x7)
-
-/**
- * Register: HW_AUDIOOUT_DATA
- * Address: 0xf0
- * SCT: yes
-*/
-#define HW_AUDIOOUT_DATA            (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xf0 + 0x0))
-#define HW_AUDIOOUT_DATA_SET        (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xf0 + 0x4))
-#define HW_AUDIOOUT_DATA_CLR        (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xf0 + 0x8))
-#define HW_AUDIOOUT_DATA_TOG        (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xf0 + 0xc))
-#define BP_AUDIOOUT_DATA_HIGH       16
-#define BM_AUDIOOUT_DATA_HIGH       0xffff0000
-#define BF_AUDIOOUT_DATA_HIGH(v)    (((v) << 16) & 0xffff0000)
-#define BP_AUDIOOUT_DATA_LOW        0
-#define BM_AUDIOOUT_DATA_LOW        0xffff
-#define BF_AUDIOOUT_DATA_LOW(v)     (((v) << 0) & 0xffff)
-
-#endif /* __HEADERGEN__STMP3600__AUDIOOUT__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-brazoiocsr.h b/firmware/target/arm/imx233/regs/stmp3600/regs-brazoiocsr.h
deleted file mode 100644
index aaac0bd0e9..0000000000
--- a/firmware/target/arm/imx233/regs/stmp3600/regs-brazoiocsr.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3600:2.3.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__STMP3600__BRAZOIOCSR__H__
-#define __HEADERGEN__STMP3600__BRAZOIOCSR__H__
-
-#define REGS_BRAZOIOCSR_BASE (0x80038000)
-
-#define REGS_BRAZOIOCSR_VERSION "2.3.0"
-
-#endif /* __HEADERGEN__STMP3600__BRAZOIOCSR__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-clkctrl.h b/firmware/target/arm/imx233/regs/stmp3600/regs-clkctrl.h
deleted file mode 100644
index 095bf5a7bc..0000000000
--- a/firmware/target/arm/imx233/regs/stmp3600/regs-clkctrl.h
+++ /dev/null
@@ -1,344 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3600:2.4.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__STMP3600__CLKCTRL__H__
-#define __HEADERGEN__STMP3600__CLKCTRL__H__
-
-#define REGS_CLKCTRL_BASE (0x80040000)
-
-#define REGS_CLKCTRL_VERSION "2.4.0"
-
-/**
- * Register: HW_CLKCTRL_PLLCTRL0
- * Address: 0
- * SCT: yes
-*/
-#define HW_CLKCTRL_PLLCTRL0                                     (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x0 + 0x0))
-#define HW_CLKCTRL_PLLCTRL0_SET                                 (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x0 + 0x4))
-#define HW_CLKCTRL_PLLCTRL0_CLR                                 (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x0 + 0x8))
-#define HW_CLKCTRL_PLLCTRL0_TOG                                 (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x0 + 0xc))
-#define BP_CLKCTRL_PLLCTRL0_PLLVCOKSTART                        30
-#define BM_CLKCTRL_PLLCTRL0_PLLVCOKSTART                        0x40000000
-#define BF_CLKCTRL_PLLCTRL0_PLLVCOKSTART(v)                     (((v) << 30) & 0x40000000)
-#define BP_CLKCTRL_PLLCTRL0_PLLCPSHORTLFR                       29
-#define BM_CLKCTRL_PLLCTRL0_PLLCPSHORTLFR                       0x20000000
-#define BF_CLKCTRL_PLLCTRL0_PLLCPSHORTLFR(v)                    (((v) << 29) & 0x20000000)
-#define BP_CLKCTRL_PLLCTRL0_PLLCPDBLIP                          28
-#define BM_CLKCTRL_PLLCTRL0_PLLCPDBLIP                          0x10000000
-#define BF_CLKCTRL_PLLCTRL0_PLLCPDBLIP(v)                       (((v) << 28) & 0x10000000)
-#define BP_CLKCTRL_PLLCTRL0_PLLCPNSEL                           24
-#define BM_CLKCTRL_PLLCTRL0_PLLCPNSEL                           0x7000000
-#define BV_CLKCTRL_PLLCTRL0_PLLCPNSEL__DEFAULT                  0x0
-#define BV_CLKCTRL_PLLCTRL0_PLLCPNSEL__TIMES_15                 0x2
-#define BV_CLKCTRL_PLLCTRL0_PLLCPNSEL__TIMES_075                0x3
-#define BV_CLKCTRL_PLLCTRL0_PLLCPNSEL__TIMES_05                 0x4
-#define BV_CLKCTRL_PLLCTRL0_PLLCPNSEL__TIMES_04                 0x7
-#define BF_CLKCTRL_PLLCTRL0_PLLCPNSEL(v)                        (((v) << 24) & 0x7000000)
-#define BF_CLKCTRL_PLLCTRL0_PLLCPNSEL_V(v)                      ((BV_CLKCTRL_PLLCTRL0_PLLCPNSEL__##v << 24) & 0x7000000)
-#define BP_CLKCTRL_PLLCTRL0_PLLV2ISEL                           20
-#define BM_CLKCTRL_PLLCTRL0_PLLV2ISEL                           0x300000
-#define BV_CLKCTRL_PLLCTRL0_PLLV2ISEL__NORMAL                   0x0
-#define BV_CLKCTRL_PLLCTRL0_PLLV2ISEL__LOWER                    0x1
-#define BV_CLKCTRL_PLLCTRL0_PLLV2ISEL__LOWEST                   0x2
-#define BV_CLKCTRL_PLLCTRL0_PLLV2ISEL__HIGHEST                  0x3
-#define BF_CLKCTRL_PLLCTRL0_PLLV2ISEL(v)                        (((v) << 20) & 0x300000)
-#define BF_CLKCTRL_PLLCTRL0_PLLV2ISEL_V(v)                      ((BV_CLKCTRL_PLLCTRL0_PLLV2ISEL__##v << 20) & 0x300000)
-#define BP_CLKCTRL_PLLCTRL0_FORCE_FREQ                          19
-#define BM_CLKCTRL_PLLCTRL0_FORCE_FREQ                          0x80000
-#define BV_CLKCTRL_PLLCTRL0_FORCE_FREQ__FORCE_SAME_FREQ         0x1
-#define BV_CLKCTRL_PLLCTRL0_FORCE_FREQ__HONOR_SAME_FREQ_RULE    0x0
-#define BF_CLKCTRL_PLLCTRL0_FORCE_FREQ(v)                       (((v) << 19) & 0x80000)
-#define BF_CLKCTRL_PLLCTRL0_FORCE_FREQ_V(v)                     ((BV_CLKCTRL_PLLCTRL0_FORCE_FREQ__##v << 19) & 0x80000)
-#define BP_CLKCTRL_PLLCTRL0_EN_USB_CLKS                         18
-#define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS                         0x40000
-#define BF_CLKCTRL_PLLCTRL0_EN_USB_CLKS(v)                      (((v) << 18) & 0x40000)
-#define BP_CLKCTRL_PLLCTRL0_BYPASS                              17
-#define BM_CLKCTRL_PLLCTRL0_BYPASS                              0x20000
-#define BF_CLKCTRL_PLLCTRL0_BYPASS(v)                           (((v) << 17) & 0x20000)
-#define BP_CLKCTRL_PLLCTRL0_POWER                               16
-#define BM_CLKCTRL_PLLCTRL0_POWER                               0x10000
-#define BF_CLKCTRL_PLLCTRL0_POWER(v)                            (((v) << 16) & 0x10000)
-#define BP_CLKCTRL_PLLCTRL0_FREQ                                0
-#define BM_CLKCTRL_PLLCTRL0_FREQ                                0x1ff
-#define BF_CLKCTRL_PLLCTRL0_FREQ(v)                             (((v) << 0) & 0x1ff)
-
-/**
- * Register: HW_CLKCTRL_PLLCTRL1
- * Address: 0x10
- * SCT: yes
-*/
-#define HW_CLKCTRL_PLLCTRL1                 (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x10 + 0x0))
-#define HW_CLKCTRL_PLLCTRL1_SET             (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x10 + 0x4))
-#define HW_CLKCTRL_PLLCTRL1_CLR             (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x10 + 0x8))
-#define HW_CLKCTRL_PLLCTRL1_TOG             (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x10 + 0xc))
-#define BP_CLKCTRL_PLLCTRL1_LOCK            31
-#define BM_CLKCTRL_PLLCTRL1_LOCK            0x80000000
-#define BF_CLKCTRL_PLLCTRL1_LOCK(v)         (((v) << 31) & 0x80000000)
-#define BP_CLKCTRL_PLLCTRL1_FORCE_LOCK      30
-#define BM_CLKCTRL_PLLCTRL1_FORCE_LOCK      0x40000000
-#define BF_CLKCTRL_PLLCTRL1_FORCE_LOCK(v)   (((v) << 30) & 0x40000000)
-#define BP_CLKCTRL_PLLCTRL1_LOCK_COUNT      0
-#define BM_CLKCTRL_PLLCTRL1_LOCK_COUNT      0xffff
-#define BF_CLKCTRL_PLLCTRL1_LOCK_COUNT(v)   (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_CLKCTRL_CPU
- * Address: 0x20
- * SCT: no
-*/
-#define HW_CLKCTRL_CPU                      (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x20))
-#define BP_CLKCTRL_CPU_WAIT_PLL_LOCK        30
-#define BM_CLKCTRL_CPU_WAIT_PLL_LOCK        0x40000000
-#define BF_CLKCTRL_CPU_WAIT_PLL_LOCK(v)     (((v) << 30) & 0x40000000)
-#define BP_CLKCTRL_CPU_BUSY                 29
-#define BM_CLKCTRL_CPU_BUSY                 0x20000000
-#define BF_CLKCTRL_CPU_BUSY(v)              (((v) << 29) & 0x20000000)
-#define BP_CLKCTRL_CPU_INTERRUPT_WAIT       12
-#define BM_CLKCTRL_CPU_INTERRUPT_WAIT       0x1000
-#define BF_CLKCTRL_CPU_INTERRUPT_WAIT(v)    (((v) << 12) & 0x1000)
-#define BP_CLKCTRL_CPU_DIV                  0
-#define BM_CLKCTRL_CPU_DIV                  0x3ff
-#define BF_CLKCTRL_CPU_DIV(v)               (((v) << 0) & 0x3ff)
-
-/**
- * Register: HW_CLKCTRL_HBUS
- * Address: 0x30
- * SCT: no
-*/
-#define HW_CLKCTRL_HBUS                         (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x30))
-#define BP_CLKCTRL_HBUS_WAIT_PLL_LOCK           30
-#define BM_CLKCTRL_HBUS_WAIT_PLL_LOCK           0x40000000
-#define BF_CLKCTRL_HBUS_WAIT_PLL_LOCK(v)        (((v) << 30) & 0x40000000)
-#define BP_CLKCTRL_HBUS_BUSY                    29
-#define BM_CLKCTRL_HBUS_BUSY                    0x20000000
-#define BF_CLKCTRL_HBUS_BUSY(v)                 (((v) << 29) & 0x20000000)
-#define BP_CLKCTRL_HBUS_EMI_BUSY_FAST           27
-#define BM_CLKCTRL_HBUS_EMI_BUSY_FAST           0x8000000
-#define BF_CLKCTRL_HBUS_EMI_BUSY_FAST(v)        (((v) << 27) & 0x8000000)
-#define BP_CLKCTRL_HBUS_APBHDMA_BUSY_FAST       26
-#define BM_CLKCTRL_HBUS_APBHDMA_BUSY_FAST       0x4000000
-#define BF_CLKCTRL_HBUS_APBHDMA_BUSY_FAST(v)    (((v) << 26) & 0x4000000)
-#define BP_CLKCTRL_HBUS_APBXDMA_BUSY_FAST       25
-#define BM_CLKCTRL_HBUS_APBXDMA_BUSY_FAST       0x2000000
-#define BF_CLKCTRL_HBUS_APBXDMA_BUSY_FAST(v)    (((v) << 25) & 0x2000000)
-#define BP_CLKCTRL_HBUS_TRAFFIC_JAM_FAST        24
-#define BM_CLKCTRL_HBUS_TRAFFIC_JAM_FAST        0x1000000
-#define BF_CLKCTRL_HBUS_TRAFFIC_JAM_FAST(v)     (((v) << 24) & 0x1000000)
-#define BP_CLKCTRL_HBUS_TRAFFIC_FAST            23
-#define BM_CLKCTRL_HBUS_TRAFFIC_FAST            0x800000
-#define BF_CLKCTRL_HBUS_TRAFFIC_FAST(v)         (((v) << 23) & 0x800000)
-#define BP_CLKCTRL_HBUS_CPU_DATA_FAST           22
-#define BM_CLKCTRL_HBUS_CPU_DATA_FAST           0x400000
-#define BF_CLKCTRL_HBUS_CPU_DATA_FAST(v)        (((v) << 22) & 0x400000)
-#define BP_CLKCTRL_HBUS_CPU_INSTR_FAST          21
-#define BM_CLKCTRL_HBUS_CPU_INSTR_FAST          0x200000
-#define BF_CLKCTRL_HBUS_CPU_INSTR_FAST(v)       (((v) << 21) & 0x200000)
-#define BP_CLKCTRL_HBUS_AUTO_SLOW_MODE          20
-#define BM_CLKCTRL_HBUS_AUTO_SLOW_MODE          0x100000
-#define BF_CLKCTRL_HBUS_AUTO_SLOW_MODE(v)       (((v) << 20) & 0x100000)
-#define BP_CLKCTRL_HBUS_SLOW_DIV                16
-#define BM_CLKCTRL_HBUS_SLOW_DIV                0x30000
-#define BV_CLKCTRL_HBUS_SLOW_DIV__BY1           0x0
-#define BV_CLKCTRL_HBUS_SLOW_DIV__BY2           0x1
-#define BV_CLKCTRL_HBUS_SLOW_DIV__BY4           0x2
-#define BV_CLKCTRL_HBUS_SLOW_DIV__BY8           0x3
-#define BF_CLKCTRL_HBUS_SLOW_DIV(v)             (((v) << 16) & 0x30000)
-#define BF_CLKCTRL_HBUS_SLOW_DIV_V(v)           ((BV_CLKCTRL_HBUS_SLOW_DIV__##v << 16) & 0x30000)
-#define BP_CLKCTRL_HBUS_DIV                     0
-#define BM_CLKCTRL_HBUS_DIV                     0x1f
-#define BF_CLKCTRL_HBUS_DIV(v)                  (((v) << 0) & 0x1f)
-
-/**
- * Register: HW_CLKCTRL_XBUS
- * Address: 0x40
- * SCT: no
-*/
-#define HW_CLKCTRL_XBUS         (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x40))
-#define BP_CLKCTRL_XBUS_BUSY    31
-#define BM_CLKCTRL_XBUS_BUSY    0x80000000
-#define BF_CLKCTRL_XBUS_BUSY(v) (((v) << 31) & 0x80000000)
-#define BP_CLKCTRL_XBUS_DIV     0
-#define BM_CLKCTRL_XBUS_DIV     0x3ff
-#define BF_CLKCTRL_XBUS_DIV(v)  (((v) << 0) & 0x3ff)
-
-/**
- * Register: HW_CLKCTRL_XTAL
- * Address: 0x50
- * SCT: no
-*/
-#define HW_CLKCTRL_XTAL                         (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x50))
-#define BP_CLKCTRL_XTAL_UART_CLK_GATE           31
-#define BM_CLKCTRL_XTAL_UART_CLK_GATE           0x80000000
-#define BF_CLKCTRL_XTAL_UART_CLK_GATE(v)        (((v) << 31) & 0x80000000)
-#define BP_CLKCTRL_XTAL_FILT_CLK24M_GATE        30
-#define BM_CLKCTRL_XTAL_FILT_CLK24M_GATE        0x40000000
-#define BF_CLKCTRL_XTAL_FILT_CLK24M_GATE(v)     (((v) << 30) & 0x40000000)
-#define BP_CLKCTRL_XTAL_PWM_CLK24M_GATE         29
-#define BM_CLKCTRL_XTAL_PWM_CLK24M_GATE         0x20000000
-#define BF_CLKCTRL_XTAL_PWM_CLK24M_GATE(v)      (((v) << 29) & 0x20000000)
-#define BP_CLKCTRL_XTAL_DRI_CLK24M_GATE         28
-#define BM_CLKCTRL_XTAL_DRI_CLK24M_GATE         0x10000000
-#define BF_CLKCTRL_XTAL_DRI_CLK24M_GATE(v)      (((v) << 28) & 0x10000000)
-#define BP_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE      27
-#define BM_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE      0x8000000
-#define BF_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE(v)   (((v) << 27) & 0x8000000)
-#define BP_CLKCTRL_XTAL_TIMROT_CLK32K_GATE      26
-#define BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE      0x4000000
-#define BF_CLKCTRL_XTAL_TIMROT_CLK32K_GATE(v)   (((v) << 26) & 0x4000000)
-#define BP_CLKCTRL_XTAL_EXRAM_CLK16K_GATE       25
-#define BM_CLKCTRL_XTAL_EXRAM_CLK16K_GATE       0x2000000
-#define BF_CLKCTRL_XTAL_EXRAM_CLK16K_GATE(v)    (((v) << 25) & 0x2000000)
-#define BP_CLKCTRL_XTAL_LRADC_CLK2K_GATE        24
-#define BM_CLKCTRL_XTAL_LRADC_CLK2K_GATE        0x1000000
-#define BF_CLKCTRL_XTAL_LRADC_CLK2K_GATE(v)     (((v) << 24) & 0x1000000)
-
-/**
- * Register: HW_CLKCTRL_OCRAM
- * Address: 0x60
- * SCT: no
-*/
-#define HW_CLKCTRL_OCRAM            (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x60))
-#define BP_CLKCTRL_OCRAM_CLKGATE    31
-#define BM_CLKCTRL_OCRAM_CLKGATE    0x80000000
-#define BF_CLKCTRL_OCRAM_CLKGATE(v) (((v) << 31) & 0x80000000)
-#define BP_CLKCTRL_OCRAM_BUSY       30
-#define BM_CLKCTRL_OCRAM_BUSY       0x40000000
-#define BF_CLKCTRL_OCRAM_BUSY(v)    (((v) << 30) & 0x40000000)
-#define BP_CLKCTRL_OCRAM_DIV        0
-#define BM_CLKCTRL_OCRAM_DIV        0x3ff
-#define BF_CLKCTRL_OCRAM_DIV(v)     (((v) << 0) & 0x3ff)
-
-/**
- * Register: HW_CLKCTRL_UTMI
- * Address: 0x70
- * SCT: no
-*/
-#define HW_CLKCTRL_UTMI                         (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x70))
-#define BP_CLKCTRL_UTMI_UTMI_CLK120M_GATE       31
-#define BM_CLKCTRL_UTMI_UTMI_CLK120M_GATE       0x80000000
-#define BF_CLKCTRL_UTMI_UTMI_CLK120M_GATE(v)    (((v) << 31) & 0x80000000)
-#define BP_CLKCTRL_UTMI_UTMI_CLK30M_GATE        30
-#define BM_CLKCTRL_UTMI_UTMI_CLK30M_GATE        0x40000000
-#define BF_CLKCTRL_UTMI_UTMI_CLK30M_GATE(v)     (((v) << 30) & 0x40000000)
-
-/**
- * Register: HW_CLKCTRL_SSP
- * Address: 0x80
- * SCT: no
-*/
-#define HW_CLKCTRL_SSP                  (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x80))
-#define BP_CLKCTRL_SSP_CLKGATE          31
-#define BM_CLKCTRL_SSP_CLKGATE          0x80000000
-#define BF_CLKCTRL_SSP_CLKGATE(v)       (((v) << 31) & 0x80000000)
-#define BP_CLKCTRL_SSP_WAIT_PLL_LOCK    30
-#define BM_CLKCTRL_SSP_WAIT_PLL_LOCK    0x40000000
-#define BF_CLKCTRL_SSP_WAIT_PLL_LOCK(v) (((v) << 30) & 0x40000000)
-#define BP_CLKCTRL_SSP_BUSY             29
-#define BM_CLKCTRL_SSP_BUSY             0x20000000
-#define BF_CLKCTRL_SSP_BUSY(v)          (((v) << 29) & 0x20000000)
-#define BP_CLKCTRL_SSP_DIV              0
-#define BM_CLKCTRL_SSP_DIV              0x1ff
-#define BF_CLKCTRL_SSP_DIV(v)           (((v) << 0) & 0x1ff)
-
-/**
- * Register: HW_CLKCTRL_GPMI
- * Address: 0x90
- * SCT: no
-*/
-#define HW_CLKCTRL_GPMI                     (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x90))
-#define BP_CLKCTRL_GPMI_CLKGATE             31
-#define BM_CLKCTRL_GPMI_CLKGATE             0x80000000
-#define BF_CLKCTRL_GPMI_CLKGATE(v)          (((v) << 31) & 0x80000000)
-#define BP_CLKCTRL_GPMI_WAIT_PLL_LOCK       30
-#define BM_CLKCTRL_GPMI_WAIT_PLL_LOCK       0x40000000
-#define BF_CLKCTRL_GPMI_WAIT_PLL_LOCK(v)    (((v) << 30) & 0x40000000)
-#define BP_CLKCTRL_GPMI_BUSY                29
-#define BM_CLKCTRL_GPMI_BUSY                0x20000000
-#define BF_CLKCTRL_GPMI_BUSY(v)             (((v) << 29) & 0x20000000)
-#define BP_CLKCTRL_GPMI_DIV                 0
-#define BM_CLKCTRL_GPMI_DIV                 0x3ff
-#define BF_CLKCTRL_GPMI_DIV(v)              (((v) << 0) & 0x3ff)
-
-/**
- * Register: HW_CLKCTRL_SPDIF
- * Address: 0xa0
- * SCT: no
-*/
-#define HW_CLKCTRL_SPDIF            (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xa0))
-#define BP_CLKCTRL_SPDIF_CLKGATE    31
-#define BM_CLKCTRL_SPDIF_CLKGATE    0x80000000
-#define BF_CLKCTRL_SPDIF_CLKGATE(v) (((v) << 31) & 0x80000000)
-#define BP_CLKCTRL_SPDIF_BUSY       30
-#define BM_CLKCTRL_SPDIF_BUSY       0x40000000
-#define BF_CLKCTRL_SPDIF_BUSY(v)    (((v) << 30) & 0x40000000)
-#define BP_CLKCTRL_SPDIF_DIV        0
-#define BM_CLKCTRL_SPDIF_DIV        0x7
-#define BF_CLKCTRL_SPDIF_DIV(v)     (((v) << 0) & 0x7)
-
-/**
- * Register: HW_CLKCTRL_EMI
- * Address: 0xb0
- * SCT: no
-*/
-#define HW_CLKCTRL_EMI                  (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xb0))
-#define BP_CLKCTRL_EMI_CLKGATE          31
-#define BM_CLKCTRL_EMI_CLKGATE          0x80000000
-#define BF_CLKCTRL_EMI_CLKGATE(v)       (((v) << 31) & 0x80000000)
-#define BP_CLKCTRL_EMI_WAIT_PLL_LOCK    30
-#define BM_CLKCTRL_EMI_WAIT_PLL_LOCK    0x40000000
-#define BF_CLKCTRL_EMI_WAIT_PLL_LOCK(v) (((v) << 30) & 0x40000000)
-#define BP_CLKCTRL_EMI_BUSY             29
-#define BM_CLKCTRL_EMI_BUSY             0x20000000
-#define BF_CLKCTRL_EMI_BUSY(v)          (((v) << 29) & 0x20000000)
-#define BP_CLKCTRL_EMI_DIV              0
-#define BM_CLKCTRL_EMI_DIV              0x7
-#define BF_CLKCTRL_EMI_DIV(v)           (((v) << 0) & 0x7)
-
-/**
- * Register: HW_CLKCTRL_IR
- * Address: 0xc0
- * SCT: no
-*/
-#define HW_CLKCTRL_IR                   (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xc0))
-#define BP_CLKCTRL_IR_CLKGATE           31
-#define BM_CLKCTRL_IR_CLKGATE           0x80000000
-#define BF_CLKCTRL_IR_CLKGATE(v)        (((v) << 31) & 0x80000000)
-#define BP_CLKCTRL_IR_WAIT_PLL_LOCK     30
-#define BM_CLKCTRL_IR_WAIT_PLL_LOCK     0x40000000
-#define BF_CLKCTRL_IR_WAIT_PLL_LOCK(v)  (((v) << 30) & 0x40000000)
-#define BP_CLKCTRL_IR_AUTO_DIV          29
-#define BM_CLKCTRL_IR_AUTO_DIV          0x20000000
-#define BF_CLKCTRL_IR_AUTO_DIV(v)       (((v) << 29) & 0x20000000)
-#define BP_CLKCTRL_IR_IR_BUSY           28
-#define BM_CLKCTRL_IR_IR_BUSY           0x10000000
-#define BF_CLKCTRL_IR_IR_BUSY(v)        (((v) << 28) & 0x10000000)
-#define BP_CLKCTRL_IR_IROV_BUSY         27
-#define BM_CLKCTRL_IR_IROV_BUSY         0x8000000
-#define BF_CLKCTRL_IR_IROV_BUSY(v)      (((v) << 27) & 0x8000000)
-#define BP_CLKCTRL_IR_IROV_DIV          16
-#define BM_CLKCTRL_IR_IROV_DIV          0x1ff0000
-#define BF_CLKCTRL_IR_IROV_DIV(v)       (((v) << 16) & 0x1ff0000)
-#define BP_CLKCTRL_IR_IR_DIV            0
-#define BM_CLKCTRL_IR_IR_DIV            0x3ff
-#define BF_CLKCTRL_IR_IR_DIV(v)         (((v) << 0) & 0x3ff)
-
-#endif /* __HEADERGEN__STMP3600__CLKCTRL__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-dacdma.h b/firmware/target/arm/imx233/regs/stmp3600/regs-dacdma.h
deleted file mode 100644
index b1c37657b2..0000000000
--- a/firmware/target/arm/imx233/regs/stmp3600/regs-dacdma.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3600:2.3.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__STMP3600__DACDMA__H__
-#define __HEADERGEN__STMP3600__DACDMA__H__
-
-#define REGS_DACDMA_BASE (0x8004c000)
-
-#define REGS_DACDMA_VERSION "2.3.0"
-
-/**
- * Register: HW_DACDMA_CTRL
- * Address: 0
- * SCT: yes
-*/
-#define HW_DACDMA_CTRL              (*(volatile unsigned long *)(REGS_DACDMA_BASE + 0x0 + 0x0))
-#define HW_DACDMA_CTRL_SET          (*(volatile unsigned long *)(REGS_DACDMA_BASE + 0x0 + 0x4))
-#define HW_DACDMA_CTRL_CLR          (*(volatile unsigned long *)(REGS_DACDMA_BASE + 0x0 + 0x8))
-#define HW_DACDMA_CTRL_TOG          (*(volatile unsigned long *)(REGS_DACDMA_BASE + 0x0 + 0xc))
-#define BP_DACDMA_CTRL_SFTRST       31
-#define BM_DACDMA_CTRL_SFTRST       0x80000000
-#define BF_DACDMA_CTRL_SFTRST(v)    (((v) << 31) & 0x80000000)
-#define BP_DACDMA_CTRL_CLKGATE      30
-#define BM_DACDMA_CTRL_CLKGATE      0x40000000
-#define BF_DACDMA_CTRL_CLKGATE(v)   (((v) << 30) & 0x40000000)
-#define BP_DACDMA_CTRL_RUN          0
-#define BM_DACDMA_CTRL_RUN          0x1
-#define BF_DACDMA_CTRL_RUN(v)       (((v) << 0) & 0x1)
-
-/**
- * Register: HW_DACDMA_DATA
- * Address: 0x80
- * SCT: no
-*/
-#define HW_DACDMA_DATA          (*(volatile unsigned long *)(REGS_DACDMA_BASE + 0x80))
-#define BP_DACDMA_DATA_HIGH     16
-#define BM_DACDMA_DATA_HIGH     0xffff0000
-#define BF_DACDMA_DATA_HIGH(v)  (((v) << 16) & 0xffff0000)
-#define BP_DACDMA_DATA_LOW      0
-#define BM_DACDMA_DATA_LOW      0xffff
-#define BF_DACDMA_DATA_LOW(v)   (((v) << 0) & 0xffff)
-
-#endif /* __HEADERGEN__STMP3600__DACDMA__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-digctl.h b/firmware/target/arm/imx233/regs/stmp3600/regs-digctl.h
deleted file mode 100644
index 28f77ca0c0..0000000000
--- a/firmware/target/arm/imx233/regs/stmp3600/regs-digctl.h
+++ /dev/null
@@ -1,595 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3600:2.3.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__STMP3600__DIGCTL__H__
-#define __HEADERGEN__STMP3600__DIGCTL__H__
-
-#define REGS_DIGCTL_BASE (0x8001c000)
-
-#define REGS_DIGCTL_VERSION "2.3.0"
-
-/**
- * Register: HW_DIGCTL_CTRL
- * Address: 0
- * SCT: yes
-*/
-#define HW_DIGCTL_CTRL                                  (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x0 + 0x0))
-#define HW_DIGCTL_CTRL_SET                              (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x0 + 0x4))
-#define HW_DIGCTL_CTRL_CLR                              (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x0 + 0x8))
-#define HW_DIGCTL_CTRL_TOG                              (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x0 + 0xc))
-#define BP_DIGCTL_CTRL_MASTER_SELECT                    24
-#define BM_DIGCTL_CTRL_MASTER_SELECT                    0x1f000000
-#define BV_DIGCTL_CTRL_MASTER_SELECT__ARM_I             0x1
-#define BV_DIGCTL_CTRL_MASTER_SELECT__ARM_D             0x2
-#define BV_DIGCTL_CTRL_MASTER_SELECT__USB               0x4
-#define BV_DIGCTL_CTRL_MASTER_SELECT__APBH              0x8
-#define BV_DIGCTL_CTRL_MASTER_SELECT__APBX              0x10
-#define BF_DIGCTL_CTRL_MASTER_SELECT(v)                 (((v) << 24) & 0x1f000000)
-#define BF_DIGCTL_CTRL_MASTER_SELECT_V(v)               ((BV_DIGCTL_CTRL_MASTER_SELECT__##v << 24) & 0x1f000000)
-#define BP_DIGCTL_CTRL_USB_TESTMODE                     20
-#define BM_DIGCTL_CTRL_USB_TESTMODE                     0x100000
-#define BF_DIGCTL_CTRL_USB_TESTMODE(v)                  (((v) << 20) & 0x100000)
-#define BP_DIGCTL_CTRL_ANALOG_TESTMODE                  19
-#define BM_DIGCTL_CTRL_ANALOG_TESTMODE                  0x80000
-#define BF_DIGCTL_CTRL_ANALOG_TESTMODE(v)               (((v) << 19) & 0x80000)
-#define BP_DIGCTL_CTRL_DIGITAL_TESTMODE                 18
-#define BM_DIGCTL_CTRL_DIGITAL_TESTMODE                 0x40000
-#define BF_DIGCTL_CTRL_DIGITAL_TESTMODE(v)              (((v) << 18) & 0x40000)
-#define BP_DIGCTL_CTRL_UTMI_TESTMODE                    17
-#define BM_DIGCTL_CTRL_UTMI_TESTMODE                    0x20000
-#define BF_DIGCTL_CTRL_UTMI_TESTMODE(v)                 (((v) << 17) & 0x20000)
-#define BP_DIGCTL_CTRL_UART_LOOPBACK                    16
-#define BM_DIGCTL_CTRL_UART_LOOPBACK                    0x10000
-#define BV_DIGCTL_CTRL_UART_LOOPBACK__NORMAL            0x0
-#define BV_DIGCTL_CTRL_UART_LOOPBACK__LOOPIT            0x1
-#define BF_DIGCTL_CTRL_UART_LOOPBACK(v)                 (((v) << 16) & 0x10000)
-#define BF_DIGCTL_CTRL_UART_LOOPBACK_V(v)               ((BV_DIGCTL_CTRL_UART_LOOPBACK__##v << 16) & 0x10000)
-#define BP_DIGCTL_CTRL_DEBUG_DISABLE                    3
-#define BM_DIGCTL_CTRL_DEBUG_DISABLE                    0x8
-#define BF_DIGCTL_CTRL_DEBUG_DISABLE(v)                 (((v) << 3) & 0x8)
-#define BP_DIGCTL_CTRL_USB_CLKGATE                      2
-#define BM_DIGCTL_CTRL_USB_CLKGATE                      0x4
-#define BV_DIGCTL_CTRL_USB_CLKGATE__RUN                 0x0
-#define BV_DIGCTL_CTRL_USB_CLKGATE__NO_CLKS             0x1
-#define BF_DIGCTL_CTRL_USB_CLKGATE(v)                   (((v) << 2) & 0x4)
-#define BF_DIGCTL_CTRL_USB_CLKGATE_V(v)                 ((BV_DIGCTL_CTRL_USB_CLKGATE__##v << 2) & 0x4)
-#define BP_DIGCTL_CTRL_JTAG_SHIELD                      1
-#define BM_DIGCTL_CTRL_JTAG_SHIELD                      0x2
-#define BV_DIGCTL_CTRL_JTAG_SHIELD__NORMAL              0x0
-#define BV_DIGCTL_CTRL_JTAG_SHIELD__SHIELDS_UP          0x1
-#define BF_DIGCTL_CTRL_JTAG_SHIELD(v)                   (((v) << 1) & 0x2)
-#define BF_DIGCTL_CTRL_JTAG_SHIELD_V(v)                 ((BV_DIGCTL_CTRL_JTAG_SHIELD__##v << 1) & 0x2)
-#define BP_DIGCTL_CTRL_PACKAGE_SENSE_ENABLE             0
-#define BM_DIGCTL_CTRL_PACKAGE_SENSE_ENABLE             0x1
-#define BV_DIGCTL_CTRL_PACKAGE_SENSE_ENABLE__DISABLE    0x0
-#define BV_DIGCTL_CTRL_PACKAGE_SENSE_ENABLE__ENABLE     0x1
-#define BF_DIGCTL_CTRL_PACKAGE_SENSE_ENABLE(v)          (((v) << 0) & 0x1)
-#define BF_DIGCTL_CTRL_PACKAGE_SENSE_ENABLE_V(v)        ((BV_DIGCTL_CTRL_PACKAGE_SENSE_ENABLE__##v << 0) & 0x1)
-
-/**
- * Register: HW_DIGCTL_STATUS
- * Address: 0x10
- * SCT: no
-*/
-#define HW_DIGCTL_STATUS                        (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x10))
-#define BP_DIGCTL_STATUS_ROM_KEYS_PRESENT       31
-#define BM_DIGCTL_STATUS_ROM_KEYS_PRESENT       0x80000000
-#define BF_DIGCTL_STATUS_ROM_KEYS_PRESENT(v)    (((v) << 31) & 0x80000000)
-#define BP_DIGCTL_STATUS_JTAG_SHIELD_DEFAULT    6
-#define BM_DIGCTL_STATUS_JTAG_SHIELD_DEFAULT    0x40
-#define BF_DIGCTL_STATUS_JTAG_SHIELD_DEFAULT(v) (((v) << 6) & 0x40)
-#define BP_DIGCTL_STATUS_ROM_SHIELDED           5
-#define BM_DIGCTL_STATUS_ROM_SHIELDED           0x20
-#define BF_DIGCTL_STATUS_ROM_SHIELDED(v)        (((v) << 5) & 0x20)
-#define BP_DIGCTL_STATUS_JTAG_IN_USE            4
-#define BM_DIGCTL_STATUS_JTAG_IN_USE            0x10
-#define BF_DIGCTL_STATUS_JTAG_IN_USE(v)         (((v) << 4) & 0x10)
-#define BP_DIGCTL_STATUS_PSWITCH                2
-#define BM_DIGCTL_STATUS_PSWITCH                0xc
-#define BF_DIGCTL_STATUS_PSWITCH(v)             (((v) << 2) & 0xc)
-#define BP_DIGCTL_STATUS_PACKAGE_TYPE           1
-#define BM_DIGCTL_STATUS_PACKAGE_TYPE           0x2
-#define BF_DIGCTL_STATUS_PACKAGE_TYPE(v)        (((v) << 1) & 0x2)
-#define BP_DIGCTL_STATUS_WRITTEN                0
-#define BM_DIGCTL_STATUS_WRITTEN                0x1
-#define BF_DIGCTL_STATUS_WRITTEN(v)             (((v) << 0) & 0x1)
-
-/**
- * Register: HW_DIGCTL_HCLKCOUNT
- * Address: 0x20
- * SCT: no
-*/
-#define HW_DIGCTL_HCLKCOUNT             (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x20))
-#define BP_DIGCTL_HCLKCOUNT_COUNT       0
-#define BM_DIGCTL_HCLKCOUNT_COUNT       0xffffffff
-#define BF_DIGCTL_HCLKCOUNT_COUNT(v)    (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_RAMCTRL
- * Address: 0x30
- * SCT: yes
-*/
-#define HW_DIGCTL_RAMCTRL                           (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x30 + 0x0))
-#define HW_DIGCTL_RAMCTRL_SET                       (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x30 + 0x4))
-#define HW_DIGCTL_RAMCTRL_CLR                       (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x30 + 0x8))
-#define HW_DIGCTL_RAMCTRL_TOG                       (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x30 + 0xc))
-#define BP_DIGCTL_RAMCTRL_TEST_MARGIN               28
-#define BM_DIGCTL_RAMCTRL_TEST_MARGIN               0x70000000
-#define BV_DIGCTL_RAMCTRL_TEST_MARGIN__NORMAL       0x0
-#define BV_DIGCTL_RAMCTRL_TEST_MARGIN__LEVEL1       0x1
-#define BV_DIGCTL_RAMCTRL_TEST_MARGIN__LEVEL2       0x2
-#define BV_DIGCTL_RAMCTRL_TEST_MARGIN__LEVEL3       0x3
-#define BV_DIGCTL_RAMCTRL_TEST_MARGIN__LEVEL4       0x4
-#define BV_DIGCTL_RAMCTRL_TEST_MARGIN__LEVEL5       0x5
-#define BV_DIGCTL_RAMCTRL_TEST_MARGIN__LEVEL6       0x6
-#define BV_DIGCTL_RAMCTRL_TEST_MARGIN__LEVEL7       0x7
-#define BF_DIGCTL_RAMCTRL_TEST_MARGIN(v)            (((v) << 28) & 0x70000000)
-#define BF_DIGCTL_RAMCTRL_TEST_MARGIN_V(v)          ((BV_DIGCTL_RAMCTRL_TEST_MARGIN__##v << 28) & 0x70000000)
-#define BP_DIGCTL_RAMCTRL_PWDN_BANKS                24
-#define BM_DIGCTL_RAMCTRL_PWDN_BANKS                0xf000000
-#define BV_DIGCTL_RAMCTRL_PWDN_BANKS__PWDN_BANK3    0x8
-#define BV_DIGCTL_RAMCTRL_PWDN_BANKS__PWDN_BANK2    0x4
-#define BV_DIGCTL_RAMCTRL_PWDN_BANKS__PWDN_BANK1    0x2
-#define BV_DIGCTL_RAMCTRL_PWDN_BANKS__PWDN_BANK0    0x1
-#define BF_DIGCTL_RAMCTRL_PWDN_BANKS(v)             (((v) << 24) & 0xf000000)
-#define BF_DIGCTL_RAMCTRL_PWDN_BANKS_V(v)           ((BV_DIGCTL_RAMCTRL_PWDN_BANKS__##v << 24) & 0xf000000)
-#define BP_DIGCTL_RAMCTRL_TEMP_SENSOR               20
-#define BM_DIGCTL_RAMCTRL_TEMP_SENSOR               0x700000
-#define BF_DIGCTL_RAMCTRL_TEMP_SENSOR(v)            (((v) << 20) & 0x700000)
-#define BP_DIGCTL_RAMCTRL_TEST_TEMP_COMP            16
-#define BM_DIGCTL_RAMCTRL_TEST_TEMP_COMP            0x70000
-#define BV_DIGCTL_RAMCTRL_TEST_TEMP_COMP__LOW_TEMP  0x1
-#define BV_DIGCTL_RAMCTRL_TEST_TEMP_COMP__RANGE_A   0x2
-#define BV_DIGCTL_RAMCTRL_TEST_TEMP_COMP__RANGE_B   0x3
-#define BV_DIGCTL_RAMCTRL_TEST_TEMP_COMP__RANGE_C   0x4
-#define BV_DIGCTL_RAMCTRL_TEST_TEMP_COMP__RANGE_D   0x5
-#define BV_DIGCTL_RAMCTRL_TEST_TEMP_COMP__RANGE_E   0x6
-#define BV_DIGCTL_RAMCTRL_TEST_TEMP_COMP__RANGE_F   0x7
-#define BF_DIGCTL_RAMCTRL_TEST_TEMP_COMP(v)         (((v) << 16) & 0x70000)
-#define BF_DIGCTL_RAMCTRL_TEST_TEMP_COMP_V(v)       ((BV_DIGCTL_RAMCTRL_TEST_TEMP_COMP__##v << 16) & 0x70000)
-#define BP_DIGCTL_RAMCTRL_SHIFT_COUNT               8
-#define BM_DIGCTL_RAMCTRL_SHIFT_COUNT               0x7f00
-#define BF_DIGCTL_RAMCTRL_SHIFT_COUNT(v)            (((v) << 8) & 0x7f00)
-#define BP_DIGCTL_RAMCTRL_FLIP_CLK                  7
-#define BM_DIGCTL_RAMCTRL_FLIP_CLK                  0x80
-#define BV_DIGCTL_RAMCTRL_FLIP_CLK__NORMAL          0x0
-#define BV_DIGCTL_RAMCTRL_FLIP_CLK__INVERT          0x1
-#define BF_DIGCTL_RAMCTRL_FLIP_CLK(v)               (((v) << 7) & 0x80)
-#define BF_DIGCTL_RAMCTRL_FLIP_CLK_V(v)             ((BV_DIGCTL_RAMCTRL_FLIP_CLK__##v << 7) & 0x80)
-#define BP_DIGCTL_RAMCTRL_OVER_RIDE_TEMP            3
-#define BM_DIGCTL_RAMCTRL_OVER_RIDE_TEMP            0x8
-#define BV_DIGCTL_RAMCTRL_OVER_RIDE_TEMP__NORMAL    0x0
-#define BV_DIGCTL_RAMCTRL_OVER_RIDE_TEMP__OVER_RIDE 0x1
-#define BF_DIGCTL_RAMCTRL_OVER_RIDE_TEMP(v)         (((v) << 3) & 0x8)
-#define BF_DIGCTL_RAMCTRL_OVER_RIDE_TEMP_V(v)       ((BV_DIGCTL_RAMCTRL_OVER_RIDE_TEMP__##v << 3) & 0x8)
-#define BP_DIGCTL_RAMCTRL_REF_CLK_GATE              2
-#define BM_DIGCTL_RAMCTRL_REF_CLK_GATE              0x4
-#define BV_DIGCTL_RAMCTRL_REF_CLK_GATE__NORMAL      0x0
-#define BV_DIGCTL_RAMCTRL_REF_CLK_GATE__OFF         0x1
-#define BF_DIGCTL_RAMCTRL_REF_CLK_GATE(v)           (((v) << 2) & 0x4)
-#define BF_DIGCTL_RAMCTRL_REF_CLK_GATE_V(v)         ((BV_DIGCTL_RAMCTRL_REF_CLK_GATE__##v << 2) & 0x4)
-#define BP_DIGCTL_RAMCTRL_REPAIR_STATUS             1
-#define BM_DIGCTL_RAMCTRL_REPAIR_STATUS             0x2
-#define BV_DIGCTL_RAMCTRL_REPAIR_STATUS__IDLE       0x0
-#define BV_DIGCTL_RAMCTRL_REPAIR_STATUS__BUSY       0x1
-#define BF_DIGCTL_RAMCTRL_REPAIR_STATUS(v)          (((v) << 1) & 0x2)
-#define BF_DIGCTL_RAMCTRL_REPAIR_STATUS_V(v)        ((BV_DIGCTL_RAMCTRL_REPAIR_STATUS__##v << 1) & 0x2)
-#define BP_DIGCTL_RAMCTRL_REPAIR_TRANSMIT           0
-#define BM_DIGCTL_RAMCTRL_REPAIR_TRANSMIT           0x1
-#define BV_DIGCTL_RAMCTRL_REPAIR_TRANSMIT__IDLE     0x0
-#define BV_DIGCTL_RAMCTRL_REPAIR_TRANSMIT__SEND     0x1
-#define BF_DIGCTL_RAMCTRL_REPAIR_TRANSMIT(v)        (((v) << 0) & 0x1)
-#define BF_DIGCTL_RAMCTRL_REPAIR_TRANSMIT_V(v)      ((BV_DIGCTL_RAMCTRL_REPAIR_TRANSMIT__##v << 0) & 0x1)
-
-/**
- * Register: HW_DIGCTL_RAMREPAIR0
- * Address: 0x40
- * SCT: yes
-*/
-#define HW_DIGCTL_RAMREPAIR0            (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x40 + 0x0))
-#define HW_DIGCTL_RAMREPAIR0_SET        (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x40 + 0x4))
-#define HW_DIGCTL_RAMREPAIR0_CLR        (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x40 + 0x8))
-#define HW_DIGCTL_RAMREPAIR0_TOG        (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x40 + 0xc))
-#define BP_DIGCTL_RAMREPAIR0_EFUSE3     24
-#define BM_DIGCTL_RAMREPAIR0_EFUSE3     0x7f000000
-#define BF_DIGCTL_RAMREPAIR0_EFUSE3(v)  (((v) << 24) & 0x7f000000)
-#define BP_DIGCTL_RAMREPAIR0_EFUSE2     16
-#define BM_DIGCTL_RAMREPAIR0_EFUSE2     0x7f0000
-#define BF_DIGCTL_RAMREPAIR0_EFUSE2(v)  (((v) << 16) & 0x7f0000)
-#define BP_DIGCTL_RAMREPAIR0_EFUSE1     8
-#define BM_DIGCTL_RAMREPAIR0_EFUSE1     0x7f00
-#define BF_DIGCTL_RAMREPAIR0_EFUSE1(v)  (((v) << 8) & 0x7f00)
-#define BP_DIGCTL_RAMREPAIR0_EFUSE0     0
-#define BM_DIGCTL_RAMREPAIR0_EFUSE0     0x7f
-#define BF_DIGCTL_RAMREPAIR0_EFUSE0(v)  (((v) << 0) & 0x7f)
-
-/**
- * Register: HW_DIGCTL_RAMREPAIR1
- * Address: 0x50
- * SCT: yes
-*/
-#define HW_DIGCTL_RAMREPAIR1            (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x50 + 0x0))
-#define HW_DIGCTL_RAMREPAIR1_SET        (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x50 + 0x4))
-#define HW_DIGCTL_RAMREPAIR1_CLR        (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x50 + 0x8))
-#define HW_DIGCTL_RAMREPAIR1_TOG        (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x50 + 0xc))
-#define BP_DIGCTL_RAMREPAIR1_EFUSE3     24
-#define BM_DIGCTL_RAMREPAIR1_EFUSE3     0x7f000000
-#define BF_DIGCTL_RAMREPAIR1_EFUSE3(v)  (((v) << 24) & 0x7f000000)
-#define BP_DIGCTL_RAMREPAIR1_EFUSE2     16
-#define BM_DIGCTL_RAMREPAIR1_EFUSE2     0x7f0000
-#define BF_DIGCTL_RAMREPAIR1_EFUSE2(v)  (((v) << 16) & 0x7f0000)
-#define BP_DIGCTL_RAMREPAIR1_EFUSE1     8
-#define BM_DIGCTL_RAMREPAIR1_EFUSE1     0x7f00
-#define BF_DIGCTL_RAMREPAIR1_EFUSE1(v)  (((v) << 8) & 0x7f00)
-#define BP_DIGCTL_RAMREPAIR1_EFUSE0     0
-#define BM_DIGCTL_RAMREPAIR1_EFUSE0     0x7f
-#define BF_DIGCTL_RAMREPAIR1_EFUSE0(v)  (((v) << 0) & 0x7f)
-
-/**
- * Register: HW_DIGCTL_WRITEONCE
- * Address: 0x60
- * SCT: no
-*/
-#define HW_DIGCTL_WRITEONCE         (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x60))
-#define BP_DIGCTL_WRITEONCE_BITS    0
-#define BM_DIGCTL_WRITEONCE_BITS    0xffffffff
-#define BF_DIGCTL_WRITEONCE_BITS(v) (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_AHBCYCLES
- * Address: 0x70
- * SCT: no
-*/
-#define HW_DIGCTL_AHBCYCLES             (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x70))
-#define BP_DIGCTL_AHBCYCLES_COUNT       0
-#define BM_DIGCTL_AHBCYCLES_COUNT       0xffffffff
-#define BF_DIGCTL_AHBCYCLES_COUNT(v)    (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_AHBSTALLED
- * Address: 0x80
- * SCT: no
-*/
-#define HW_DIGCTL_AHBSTALLED            (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x80))
-#define BP_DIGCTL_AHBSTALLED_COUNT      0
-#define BM_DIGCTL_AHBSTALLED_COUNT      0xffffffff
-#define BF_DIGCTL_AHBSTALLED_COUNT(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_ENTROPY
- * Address: 0x90
- * SCT: no
-*/
-#define HW_DIGCTL_ENTROPY           (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x90))
-#define BP_DIGCTL_ENTROPY_VALUE     0
-#define BM_DIGCTL_ENTROPY_VALUE     0xffffffff
-#define BF_DIGCTL_ENTROPY_VALUE(v)  (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_ROMSHIELD
- * Address: 0xa0
- * SCT: no
-*/
-#define HW_DIGCTL_ROMSHIELD                 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xa0))
-#define BP_DIGCTL_ROMSHIELD_WRITE_ONCE      0
-#define BM_DIGCTL_ROMSHIELD_WRITE_ONCE      0x1
-#define BF_DIGCTL_ROMSHIELD_WRITE_ONCE(v)   (((v) << 0) & 0x1)
-
-/**
- * Register: HW_DIGCTL_MICROSECONDS
- * Address: 0xb0
- * SCT: yes
-*/
-#define HW_DIGCTL_MICROSECONDS          (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xb0 + 0x0))
-#define HW_DIGCTL_MICROSECONDS_SET      (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xb0 + 0x4))
-#define HW_DIGCTL_MICROSECONDS_CLR      (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xb0 + 0x8))
-#define HW_DIGCTL_MICROSECONDS_TOG      (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xb0 + 0xc))
-#define BP_DIGCTL_MICROSECONDS_VALUE    0
-#define BM_DIGCTL_MICROSECONDS_VALUE    0xffffffff
-#define BF_DIGCTL_MICROSECONDS_VALUE(v) (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_DBGRD
- * Address: 0xc0
- * SCT: no
-*/
-#define HW_DIGCTL_DBGRD                 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xc0))
-#define BP_DIGCTL_DBGRD_COMPLEMENT      0
-#define BM_DIGCTL_DBGRD_COMPLEMENT      0xffffffff
-#define BF_DIGCTL_DBGRD_COMPLEMENT(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_DBG
- * Address: 0xd0
- * SCT: no
-*/
-#define HW_DIGCTL_DBG           (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xd0))
-#define BP_DIGCTL_DBG_VALUE     0
-#define BM_DIGCTL_DBG_VALUE     0xffffffff
-#define BF_DIGCTL_DBG_VALUE(v)  (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_1TRAM_BIST_CSR
- * Address: 0xe0
- * SCT: yes
-*/
-#define HW_DIGCTL_1TRAM_BIST_CSR            (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xe0 + 0x0))
-#define HW_DIGCTL_1TRAM_BIST_CSR_SET        (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xe0 + 0x4))
-#define HW_DIGCTL_1TRAM_BIST_CSR_CLR        (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xe0 + 0x8))
-#define HW_DIGCTL_1TRAM_BIST_CSR_TOG        (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xe0 + 0xc))
-#define BP_DIGCTL_1TRAM_BIST_CSR_FAIL       3
-#define BM_DIGCTL_1TRAM_BIST_CSR_FAIL       0x8
-#define BF_DIGCTL_1TRAM_BIST_CSR_FAIL(v)    (((v) << 3) & 0x8)
-#define BP_DIGCTL_1TRAM_BIST_CSR_PASS       2
-#define BM_DIGCTL_1TRAM_BIST_CSR_PASS       0x4
-#define BF_DIGCTL_1TRAM_BIST_CSR_PASS(v)    (((v) << 2) & 0x4)
-#define BP_DIGCTL_1TRAM_BIST_CSR_DONE       1
-#define BM_DIGCTL_1TRAM_BIST_CSR_DONE       0x2
-#define BF_DIGCTL_1TRAM_BIST_CSR_DONE(v)    (((v) << 1) & 0x2)
-#define BP_DIGCTL_1TRAM_BIST_CSR_START      0
-#define BM_DIGCTL_1TRAM_BIST_CSR_START      0x1
-#define BF_DIGCTL_1TRAM_BIST_CSR_START(v)   (((v) << 0) & 0x1)
-
-/**
- * Register: HW_DIGCTL_1TRAM_BIST_REPAIR0
- * Address: 0xf0
- * SCT: no
-*/
-#define HW_DIGCTL_1TRAM_BIST_REPAIR0    (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xf0))
-
-/**
- * Register: HW_DIGCTL_1TRAM_BIST_REPAIR1
- * Address: 0x100
- * SCT: no
-*/
-#define HW_DIGCTL_1TRAM_BIST_REPAIR1    (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x100))
-
-/**
- * Register: HW_DIGCTL_1TRAM_STATUS0
- * Address: 0x110
- * SCT: no
-*/
-#define HW_DIGCTL_1TRAM_STATUS0                 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x110))
-#define BP_DIGCTL_1TRAM_STATUS0_FAILDATA00      0
-#define BM_DIGCTL_1TRAM_STATUS0_FAILDATA00      0xffffffff
-#define BF_DIGCTL_1TRAM_STATUS0_FAILDATA00(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_1TRAM_STATUS1
- * Address: 0x120
- * SCT: no
-*/
-#define HW_DIGCTL_1TRAM_STATUS1                 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x120))
-#define BP_DIGCTL_1TRAM_STATUS1_FAILDATA01      0
-#define BM_DIGCTL_1TRAM_STATUS1_FAILDATA01      0xffffffff
-#define BF_DIGCTL_1TRAM_STATUS1_FAILDATA01(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_1TRAM_STATUS2
- * Address: 0x130
- * SCT: no
-*/
-#define HW_DIGCTL_1TRAM_STATUS2                 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x130))
-#define BP_DIGCTL_1TRAM_STATUS2_FAILDATA10      0
-#define BM_DIGCTL_1TRAM_STATUS2_FAILDATA10      0xffffffff
-#define BF_DIGCTL_1TRAM_STATUS2_FAILDATA10(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_1TRAM_STATUS3
- * Address: 0x140
- * SCT: no
-*/
-#define HW_DIGCTL_1TRAM_STATUS3                 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x140))
-#define BP_DIGCTL_1TRAM_STATUS3_FAILDATA11      0
-#define BM_DIGCTL_1TRAM_STATUS3_FAILDATA11      0xffffffff
-#define BF_DIGCTL_1TRAM_STATUS3_FAILDATA11(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_1TRAM_STATUS4
- * Address: 0x150
- * SCT: no
-*/
-#define HW_DIGCTL_1TRAM_STATUS4                 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x150))
-#define BP_DIGCTL_1TRAM_STATUS4_FAILDATA20      0
-#define BM_DIGCTL_1TRAM_STATUS4_FAILDATA20      0xffffffff
-#define BF_DIGCTL_1TRAM_STATUS4_FAILDATA20(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_1TRAM_STATUS5
- * Address: 0x160
- * SCT: no
-*/
-#define HW_DIGCTL_1TRAM_STATUS5                 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x160))
-#define BP_DIGCTL_1TRAM_STATUS5_FAILDATA21      0
-#define BM_DIGCTL_1TRAM_STATUS5_FAILDATA21      0xffffffff
-#define BF_DIGCTL_1TRAM_STATUS5_FAILDATA21(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_1TRAM_STATUS6
- * Address: 0x170
- * SCT: no
-*/
-#define HW_DIGCTL_1TRAM_STATUS6                 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x170))
-#define BP_DIGCTL_1TRAM_STATUS6_FAILDATA30      0
-#define BM_DIGCTL_1TRAM_STATUS6_FAILDATA30      0xffffffff
-#define BF_DIGCTL_1TRAM_STATUS6_FAILDATA30(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_1TRAM_STATUS7
- * Address: 0x180
- * SCT: no
-*/
-#define HW_DIGCTL_1TRAM_STATUS7                 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x180))
-#define BP_DIGCTL_1TRAM_STATUS7_FAILDATA31      0
-#define BM_DIGCTL_1TRAM_STATUS7_FAILDATA31      0xffffffff
-#define BF_DIGCTL_1TRAM_STATUS7_FAILDATA31(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_1TRAM_STATUS8
- * Address: 0x190
- * SCT: no
-*/
-#define HW_DIGCTL_1TRAM_STATUS8                 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x190))
-#define BP_DIGCTL_1TRAM_STATUS8_FAILADDR01      16
-#define BM_DIGCTL_1TRAM_STATUS8_FAILADDR01      0xffff0000
-#define BF_DIGCTL_1TRAM_STATUS8_FAILADDR01(v)   (((v) << 16) & 0xffff0000)
-#define BP_DIGCTL_1TRAM_STATUS8_FAILADDR00      0
-#define BM_DIGCTL_1TRAM_STATUS8_FAILADDR00      0xffff
-#define BF_DIGCTL_1TRAM_STATUS8_FAILADDR00(v)   (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_DIGCTL_1TRAM_STATUS9
- * Address: 0x1a0
- * SCT: no
-*/
-#define HW_DIGCTL_1TRAM_STATUS9                 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1a0))
-#define BP_DIGCTL_1TRAM_STATUS9_FAILADDR11      16
-#define BM_DIGCTL_1TRAM_STATUS9_FAILADDR11      0xffff0000
-#define BF_DIGCTL_1TRAM_STATUS9_FAILADDR11(v)   (((v) << 16) & 0xffff0000)
-#define BP_DIGCTL_1TRAM_STATUS9_FAILADDR10      0
-#define BM_DIGCTL_1TRAM_STATUS9_FAILADDR10      0xffff
-#define BF_DIGCTL_1TRAM_STATUS9_FAILADDR10(v)   (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_DIGCTL_1TRAM_STATUS10
- * Address: 0x1b0
- * SCT: no
-*/
-#define HW_DIGCTL_1TRAM_STATUS10                (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1b0))
-#define BP_DIGCTL_1TRAM_STATUS10_FAILADDR21     16
-#define BM_DIGCTL_1TRAM_STATUS10_FAILADDR21     0xffff0000
-#define BF_DIGCTL_1TRAM_STATUS10_FAILADDR21(v)  (((v) << 16) & 0xffff0000)
-#define BP_DIGCTL_1TRAM_STATUS10_FAILADDR20     0
-#define BM_DIGCTL_1TRAM_STATUS10_FAILADDR20     0xffff
-#define BF_DIGCTL_1TRAM_STATUS10_FAILADDR20(v)  (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_DIGCTL_1TRAM_STATUS11
- * Address: 0x1c0
- * SCT: no
-*/
-#define HW_DIGCTL_1TRAM_STATUS11                (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1c0))
-#define BP_DIGCTL_1TRAM_STATUS11_FAILADDR31     16
-#define BM_DIGCTL_1TRAM_STATUS11_FAILADDR31     0xffff0000
-#define BF_DIGCTL_1TRAM_STATUS11_FAILADDR31(v)  (((v) << 16) & 0xffff0000)
-#define BP_DIGCTL_1TRAM_STATUS11_FAILADDR30     0
-#define BM_DIGCTL_1TRAM_STATUS11_FAILADDR30     0xffff
-#define BF_DIGCTL_1TRAM_STATUS11_FAILADDR30(v)  (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_DIGCTL_1TRAM_STATUS12
- * Address: 0x1d0
- * SCT: no
-*/
-#define HW_DIGCTL_1TRAM_STATUS12                (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1d0))
-#define BP_DIGCTL_1TRAM_STATUS12_FAILSTATE11    24
-#define BM_DIGCTL_1TRAM_STATUS12_FAILSTATE11    0x1f000000
-#define BF_DIGCTL_1TRAM_STATUS12_FAILSTATE11(v) (((v) << 24) & 0x1f000000)
-#define BP_DIGCTL_1TRAM_STATUS12_FAILSTATE10    16
-#define BM_DIGCTL_1TRAM_STATUS12_FAILSTATE10    0x1f0000
-#define BF_DIGCTL_1TRAM_STATUS12_FAILSTATE10(v) (((v) << 16) & 0x1f0000)
-#define BP_DIGCTL_1TRAM_STATUS12_FAILSTATE01    8
-#define BM_DIGCTL_1TRAM_STATUS12_FAILSTATE01    0x1f00
-#define BF_DIGCTL_1TRAM_STATUS12_FAILSTATE01(v) (((v) << 8) & 0x1f00)
-#define BP_DIGCTL_1TRAM_STATUS12_FAILSTATE00    0
-#define BM_DIGCTL_1TRAM_STATUS12_FAILSTATE00    0x1f
-#define BF_DIGCTL_1TRAM_STATUS12_FAILSTATE00(v) (((v) << 0) & 0x1f)
-
-/**
- * Register: HW_DIGCTL_1TRAM_STATUS13
- * Address: 0x1e0
- * SCT: no
-*/
-#define HW_DIGCTL_1TRAM_STATUS13                (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1e0))
-#define BP_DIGCTL_1TRAM_STATUS13_FAILSTATE31    24
-#define BM_DIGCTL_1TRAM_STATUS13_FAILSTATE31    0x1f000000
-#define BF_DIGCTL_1TRAM_STATUS13_FAILSTATE31(v) (((v) << 24) & 0x1f000000)
-#define BP_DIGCTL_1TRAM_STATUS13_FAILSTATE30    16
-#define BM_DIGCTL_1TRAM_STATUS13_FAILSTATE30    0x1f0000
-#define BF_DIGCTL_1TRAM_STATUS13_FAILSTATE30(v) (((v) << 16) & 0x1f0000)
-#define BP_DIGCTL_1TRAM_STATUS13_FAILSTATE21    8
-#define BM_DIGCTL_1TRAM_STATUS13_FAILSTATE21    0x1f00
-#define BF_DIGCTL_1TRAM_STATUS13_FAILSTATE21(v) (((v) << 8) & 0x1f00)
-#define BP_DIGCTL_1TRAM_STATUS13_FAILSTATE20    0
-#define BM_DIGCTL_1TRAM_STATUS13_FAILSTATE20    0x1f
-#define BF_DIGCTL_1TRAM_STATUS13_FAILSTATE20(v) (((v) << 0) & 0x1f)
-
-/**
- * Register: HW_DIGCTL_SCRATCH0
- * Address: 0x290
- * SCT: no
-*/
-#define HW_DIGCTL_SCRATCH0          (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x290))
-#define BP_DIGCTL_SCRATCH0_PTR      0
-#define BM_DIGCTL_SCRATCH0_PTR      0xffffffff
-#define BF_DIGCTL_SCRATCH0_PTR(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_SCRATCH1
- * Address: 0x2a0
- * SCT: no
-*/
-#define HW_DIGCTL_SCRATCH1          (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x2a0))
-#define BP_DIGCTL_SCRATCH1_PTR      0
-#define BM_DIGCTL_SCRATCH1_PTR      0xffffffff
-#define BF_DIGCTL_SCRATCH1_PTR(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_ARMCACHE
- * Address: 0x2b0
- * SCT: no
-*/
-#define HW_DIGCTL_ARMCACHE              (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x2b0))
-#define BP_DIGCTL_ARMCACHE_CACHE_SS     8
-#define BM_DIGCTL_ARMCACHE_CACHE_SS     0x300
-#define BF_DIGCTL_ARMCACHE_CACHE_SS(v)  (((v) << 8) & 0x300)
-#define BP_DIGCTL_ARMCACHE_DTAG_SS      4
-#define BM_DIGCTL_ARMCACHE_DTAG_SS      0x30
-#define BF_DIGCTL_ARMCACHE_DTAG_SS(v)   (((v) << 4) & 0x30)
-#define BP_DIGCTL_ARMCACHE_ITAG_SS      0
-#define BM_DIGCTL_ARMCACHE_ITAG_SS      0x3
-#define BF_DIGCTL_ARMCACHE_ITAG_SS(v)   (((v) << 0) & 0x3)
-
-/**
- * Register: HW_DIGCTL_SGTL
- * Address: 0x300
- * SCT: no
-*/
-#define HW_DIGCTL_SGTL              (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x300))
-#define BP_DIGCTL_SGTL_COPYRIGHT    0
-#define BM_DIGCTL_SGTL_COPYRIGHT    0xffffffff
-#define BF_DIGCTL_SGTL_COPYRIGHT(v) (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_CHIPID
- * Address: 0x310
- * SCT: no
-*/
-#define HW_DIGCTL_CHIPID                    (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x310))
-#define BP_DIGCTL_CHIPID_PRODUCT_CODE       16
-#define BM_DIGCTL_CHIPID_PRODUCT_CODE       0xffff0000
-#define BF_DIGCTL_CHIPID_PRODUCT_CODE(v)    (((v) << 16) & 0xffff0000)
-#define BP_DIGCTL_CHIPID_REVISION           0
-#define BM_DIGCTL_CHIPID_REVISION           0xff
-#define BF_DIGCTL_CHIPID_REVISION(v)        (((v) << 0) & 0xff)
-
-#endif /* __HEADERGEN__STMP3600__DIGCTL__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-dri.h b/firmware/target/arm/imx233/regs/stmp3600/regs-dri.h
deleted file mode 100644
index 482ac9dfe4..0000000000
--- a/firmware/target/arm/imx233/regs/stmp3600/regs-dri.h
+++ /dev/null
@@ -1,258 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3600:2.3.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__STMP3600__DRI__H__
-#define __HEADERGEN__STMP3600__DRI__H__
-
-#define REGS_DRI_BASE (0x80074000)
-
-#define REGS_DRI_VERSION "2.3.0"
-
-/**
- * Register: HW_DRI_CTRL
- * Address: 0
- * SCT: yes
-*/
-#define HW_DRI_CTRL                                     (*(volatile unsigned long *)(REGS_DRI_BASE + 0x0 + 0x0))
-#define HW_DRI_CTRL_SET                                 (*(volatile unsigned long *)(REGS_DRI_BASE + 0x0 + 0x4))
-#define HW_DRI_CTRL_CLR                                 (*(volatile unsigned long *)(REGS_DRI_BASE + 0x0 + 0x8))
-#define HW_DRI_CTRL_TOG                                 (*(volatile unsigned long *)(REGS_DRI_BASE + 0x0 + 0xc))
-#define BP_DRI_CTRL_SFTRST                              31
-#define BM_DRI_CTRL_SFTRST                              0x80000000
-#define BV_DRI_CTRL_SFTRST__RUN                         0x0
-#define BV_DRI_CTRL_SFTRST__RESET                       0x1
-#define BF_DRI_CTRL_SFTRST(v)                           (((v) << 31) & 0x80000000)
-#define BF_DRI_CTRL_SFTRST_V(v)                         ((BV_DRI_CTRL_SFTRST__##v << 31) & 0x80000000)
-#define BP_DRI_CTRL_CLKGATE                             30
-#define BM_DRI_CTRL_CLKGATE                             0x40000000
-#define BV_DRI_CTRL_CLKGATE__RUN                        0x0
-#define BV_DRI_CTRL_CLKGATE__NO_CLKS                    0x1
-#define BF_DRI_CTRL_CLKGATE(v)                          (((v) << 30) & 0x40000000)
-#define BF_DRI_CTRL_CLKGATE_V(v)                        ((BV_DRI_CTRL_CLKGATE__##v << 30) & 0x40000000)
-#define BP_DRI_CTRL_ENABLE_INPUTS                       29
-#define BM_DRI_CTRL_ENABLE_INPUTS                       0x20000000
-#define BV_DRI_CTRL_ENABLE_INPUTS__ANALOG_LINE_IN       0x0
-#define BV_DRI_CTRL_ENABLE_INPUTS__DRI_DIGITAL_IN       0x1
-#define BF_DRI_CTRL_ENABLE_INPUTS(v)                    (((v) << 29) & 0x20000000)
-#define BF_DRI_CTRL_ENABLE_INPUTS_V(v)                  ((BV_DRI_CTRL_ENABLE_INPUTS__##v << 29) & 0x20000000)
-#define BP_DRI_CTRL_STOP_ON_OFLOW_ERROR                 26
-#define BM_DRI_CTRL_STOP_ON_OFLOW_ERROR                 0x4000000
-#define BV_DRI_CTRL_STOP_ON_OFLOW_ERROR__IGNORE         0x0
-#define BV_DRI_CTRL_STOP_ON_OFLOW_ERROR__STOP           0x1
-#define BF_DRI_CTRL_STOP_ON_OFLOW_ERROR(v)              (((v) << 26) & 0x4000000)
-#define BF_DRI_CTRL_STOP_ON_OFLOW_ERROR_V(v)            ((BV_DRI_CTRL_STOP_ON_OFLOW_ERROR__##v << 26) & 0x4000000)
-#define BP_DRI_CTRL_STOP_ON_PILOT_ERROR                 25
-#define BM_DRI_CTRL_STOP_ON_PILOT_ERROR                 0x2000000
-#define BV_DRI_CTRL_STOP_ON_PILOT_ERROR__IGNORE         0x0
-#define BV_DRI_CTRL_STOP_ON_PILOT_ERROR__STOP           0x1
-#define BF_DRI_CTRL_STOP_ON_PILOT_ERROR(v)              (((v) << 25) & 0x2000000)
-#define BF_DRI_CTRL_STOP_ON_PILOT_ERROR_V(v)            ((BV_DRI_CTRL_STOP_ON_PILOT_ERROR__##v << 25) & 0x2000000)
-#define BP_DRI_CTRL_DMA_DELAY_COUNT                     16
-#define BM_DRI_CTRL_DMA_DELAY_COUNT                     0x1f0000
-#define BF_DRI_CTRL_DMA_DELAY_COUNT(v)                  (((v) << 16) & 0x1f0000)
-#define BP_DRI_CTRL_REACQUIRE_PHASE                     15
-#define BM_DRI_CTRL_REACQUIRE_PHASE                     0x8000
-#define BV_DRI_CTRL_REACQUIRE_PHASE__NORMAL             0x0
-#define BV_DRI_CTRL_REACQUIRE_PHASE__NEW_PHASE          0x1
-#define BF_DRI_CTRL_REACQUIRE_PHASE(v)                  (((v) << 15) & 0x8000)
-#define BF_DRI_CTRL_REACQUIRE_PHASE_V(v)                ((BV_DRI_CTRL_REACQUIRE_PHASE__##v << 15) & 0x8000)
-#define BP_DRI_CTRL_OVERFLOW_IRQ_EN                     11
-#define BM_DRI_CTRL_OVERFLOW_IRQ_EN                     0x800
-#define BV_DRI_CTRL_OVERFLOW_IRQ_EN__DISABLED           0x0
-#define BV_DRI_CTRL_OVERFLOW_IRQ_EN__ENABLED            0x1
-#define BF_DRI_CTRL_OVERFLOW_IRQ_EN(v)                  (((v) << 11) & 0x800)
-#define BF_DRI_CTRL_OVERFLOW_IRQ_EN_V(v)                ((BV_DRI_CTRL_OVERFLOW_IRQ_EN__##v << 11) & 0x800)
-#define BP_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN              10
-#define BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN              0x400
-#define BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN__DISABLED    0x0
-#define BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN__ENABLED     0x1
-#define BF_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN(v)           (((v) << 10) & 0x400)
-#define BF_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN_V(v)         ((BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN__##v << 10) & 0x400)
-#define BP_DRI_CTRL_ATTENTION_IRQ_EN                    9
-#define BM_DRI_CTRL_ATTENTION_IRQ_EN                    0x200
-#define BV_DRI_CTRL_ATTENTION_IRQ_EN__DISABLED          0x0
-#define BV_DRI_CTRL_ATTENTION_IRQ_EN__ENABLED           0x1
-#define BF_DRI_CTRL_ATTENTION_IRQ_EN(v)                 (((v) << 9) & 0x200)
-#define BF_DRI_CTRL_ATTENTION_IRQ_EN_V(v)               ((BV_DRI_CTRL_ATTENTION_IRQ_EN__##v << 9) & 0x200)
-#define BP_DRI_CTRL_OVERFLOW_IRQ                        3
-#define BM_DRI_CTRL_OVERFLOW_IRQ                        0x8
-#define BV_DRI_CTRL_OVERFLOW_IRQ__NO_REQUEST            0x0
-#define BV_DRI_CTRL_OVERFLOW_IRQ__REQUEST               0x1
-#define BF_DRI_CTRL_OVERFLOW_IRQ(v)                     (((v) << 3) & 0x8)
-#define BF_DRI_CTRL_OVERFLOW_IRQ_V(v)                   ((BV_DRI_CTRL_OVERFLOW_IRQ__##v << 3) & 0x8)
-#define BP_DRI_CTRL_PILOT_SYNC_LOSS_IRQ                 2
-#define BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ                 0x4
-#define BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ__NO_REQUEST     0x0
-#define BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ__REQUEST        0x1
-#define BF_DRI_CTRL_PILOT_SYNC_LOSS_IRQ(v)              (((v) << 2) & 0x4)
-#define BF_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_V(v)            ((BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ__##v << 2) & 0x4)
-#define BP_DRI_CTRL_ATTENTION_IRQ                       1
-#define BM_DRI_CTRL_ATTENTION_IRQ                       0x2
-#define BV_DRI_CTRL_ATTENTION_IRQ__NO_REQUEST           0x0
-#define BV_DRI_CTRL_ATTENTION_IRQ__REQUEST              0x1
-#define BF_DRI_CTRL_ATTENTION_IRQ(v)                    (((v) << 1) & 0x2)
-#define BF_DRI_CTRL_ATTENTION_IRQ_V(v)                  ((BV_DRI_CTRL_ATTENTION_IRQ__##v << 1) & 0x2)
-#define BP_DRI_CTRL_RUN                                 0
-#define BM_DRI_CTRL_RUN                                 0x1
-#define BV_DRI_CTRL_RUN__HALT                           0x0
-#define BV_DRI_CTRL_RUN__RUN                            0x1
-#define BF_DRI_CTRL_RUN(v)                              (((v) << 0) & 0x1)
-#define BF_DRI_CTRL_RUN_V(v)                            ((BV_DRI_CTRL_RUN__##v << 0) & 0x1)
-
-/**
- * Register: HW_DRI_TIMING
- * Address: 0x10
- * SCT: no
-*/
-#define HW_DRI_TIMING                           (*(volatile unsigned long *)(REGS_DRI_BASE + 0x10))
-#define BP_DRI_TIMING_PILOT_REP_RATE            16
-#define BM_DRI_TIMING_PILOT_REP_RATE            0xf0000
-#define BF_DRI_TIMING_PILOT_REP_RATE(v)         (((v) << 16) & 0xf0000)
-#define BP_DRI_TIMING_GAP_DETECTION_INTERVAL    0
-#define BM_DRI_TIMING_GAP_DETECTION_INTERVAL    0xff
-#define BF_DRI_TIMING_GAP_DETECTION_INTERVAL(v) (((v) << 0) & 0xff)
-
-/**
- * Register: HW_DRI_STAT
- * Address: 0x20
- * SCT: no
-*/
-#define HW_DRI_STAT                                         (*(volatile unsigned long *)(REGS_DRI_BASE + 0x20))
-#define BP_DRI_STAT_DRI_PRESENT                             31
-#define BM_DRI_STAT_DRI_PRESENT                             0x80000000
-#define BV_DRI_STAT_DRI_PRESENT__UNAVAILABLE                0x0
-#define BV_DRI_STAT_DRI_PRESENT__AVAILABLE                  0x1
-#define BF_DRI_STAT_DRI_PRESENT(v)                          (((v) << 31) & 0x80000000)
-#define BF_DRI_STAT_DRI_PRESENT_V(v)                        ((BV_DRI_STAT_DRI_PRESENT__##v << 31) & 0x80000000)
-#define BP_DRI_STAT_PILOT_PHASE                             16
-#define BM_DRI_STAT_PILOT_PHASE                             0xf0000
-#define BF_DRI_STAT_PILOT_PHASE(v)                          (((v) << 16) & 0xf0000)
-#define BP_DRI_STAT_OVERFLOW_IRQ_SUMMARY                    3
-#define BM_DRI_STAT_OVERFLOW_IRQ_SUMMARY                    0x8
-#define BV_DRI_STAT_OVERFLOW_IRQ_SUMMARY__NO_REQUEST        0x0
-#define BV_DRI_STAT_OVERFLOW_IRQ_SUMMARY__REQUEST           0x1
-#define BF_DRI_STAT_OVERFLOW_IRQ_SUMMARY(v)                 (((v) << 3) & 0x8)
-#define BF_DRI_STAT_OVERFLOW_IRQ_SUMMARY_V(v)               ((BV_DRI_STAT_OVERFLOW_IRQ_SUMMARY__##v << 3) & 0x8)
-#define BP_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY             2
-#define BM_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY             0x4
-#define BV_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY__NO_REQUEST 0x0
-#define BV_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY__REQUEST    0x1
-#define BF_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY(v)          (((v) << 2) & 0x4)
-#define BF_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY_V(v)        ((BV_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY__##v << 2) & 0x4)
-#define BP_DRI_STAT_ATTENTION_IRQ_SUMMARY                   1
-#define BM_DRI_STAT_ATTENTION_IRQ_SUMMARY                   0x2
-#define BV_DRI_STAT_ATTENTION_IRQ_SUMMARY__NO_REQUEST       0x0
-#define BV_DRI_STAT_ATTENTION_IRQ_SUMMARY__REQUEST          0x1
-#define BF_DRI_STAT_ATTENTION_IRQ_SUMMARY(v)                (((v) << 1) & 0x2)
-#define BF_DRI_STAT_ATTENTION_IRQ_SUMMARY_V(v)              ((BV_DRI_STAT_ATTENTION_IRQ_SUMMARY__##v << 1) & 0x2)
-
-/**
- * Register: HW_DRI_DATA
- * Address: 0x30
- * SCT: no
-*/
-#define HW_DRI_DATA         (*(volatile unsigned long *)(REGS_DRI_BASE + 0x30))
-#define BP_DRI_DATA_DATA    0
-#define BM_DRI_DATA_DATA    0xffffffff
-#define BF_DRI_DATA_DATA(v) (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DRI_DEBUG0
- * Address: 0x40
- * SCT: yes
-*/
-#define HW_DRI_DEBUG0                               (*(volatile unsigned long *)(REGS_DRI_BASE + 0x40 + 0x0))
-#define HW_DRI_DEBUG0_SET                           (*(volatile unsigned long *)(REGS_DRI_BASE + 0x40 + 0x4))
-#define HW_DRI_DEBUG0_CLR                           (*(volatile unsigned long *)(REGS_DRI_BASE + 0x40 + 0x8))
-#define HW_DRI_DEBUG0_TOG                           (*(volatile unsigned long *)(REGS_DRI_BASE + 0x40 + 0xc))
-#define BP_DRI_DEBUG0_DMAREQ                        31
-#define BM_DRI_DEBUG0_DMAREQ                        0x80000000
-#define BF_DRI_DEBUG0_DMAREQ(v)                     (((v) << 31) & 0x80000000)
-#define BP_DRI_DEBUG0_DMACMDKICK                    30
-#define BM_DRI_DEBUG0_DMACMDKICK                    0x40000000
-#define BF_DRI_DEBUG0_DMACMDKICK(v)                 (((v) << 30) & 0x40000000)
-#define BP_DRI_DEBUG0_DRI_CLK_INPUT                 29
-#define BM_DRI_DEBUG0_DRI_CLK_INPUT                 0x20000000
-#define BF_DRI_DEBUG0_DRI_CLK_INPUT(v)              (((v) << 29) & 0x20000000)
-#define BP_DRI_DEBUG0_DRI_DATA_INPUT                28
-#define BM_DRI_DEBUG0_DRI_DATA_INPUT                0x10000000
-#define BF_DRI_DEBUG0_DRI_DATA_INPUT(v)             (((v) << 28) & 0x10000000)
-#define BP_DRI_DEBUG0_TEST_MODE                     27
-#define BM_DRI_DEBUG0_TEST_MODE                     0x8000000
-#define BF_DRI_DEBUG0_TEST_MODE(v)                  (((v) << 27) & 0x8000000)
-#define BP_DRI_DEBUG0_PILOT_REP_RATE                26
-#define BM_DRI_DEBUG0_PILOT_REP_RATE                0x4000000
-#define BV_DRI_DEBUG0_PILOT_REP_RATE__8_AT_4MHZ     0x0
-#define BV_DRI_DEBUG0_PILOT_REP_RATE__12_AT_6MHZ    0x1
-#define BF_DRI_DEBUG0_PILOT_REP_RATE(v)             (((v) << 26) & 0x4000000)
-#define BF_DRI_DEBUG0_PILOT_REP_RATE_V(v)           ((BV_DRI_DEBUG0_PILOT_REP_RATE__##v << 26) & 0x4000000)
-#define BP_DRI_DEBUG0_SPARE                         18
-#define BM_DRI_DEBUG0_SPARE                         0x3fc0000
-#define BF_DRI_DEBUG0_SPARE(v)                      (((v) << 18) & 0x3fc0000)
-#define BP_DRI_DEBUG0_FRAME                         0
-#define BM_DRI_DEBUG0_FRAME                         0x3ffff
-#define BF_DRI_DEBUG0_FRAME(v)                      (((v) << 0) & 0x3ffff)
-
-/**
- * Register: HW_DRI_DEBUG1
- * Address: 0x50
- * SCT: yes
-*/
-#define HW_DRI_DEBUG1                               (*(volatile unsigned long *)(REGS_DRI_BASE + 0x50 + 0x0))
-#define HW_DRI_DEBUG1_SET                           (*(volatile unsigned long *)(REGS_DRI_BASE + 0x50 + 0x4))
-#define HW_DRI_DEBUG1_CLR                           (*(volatile unsigned long *)(REGS_DRI_BASE + 0x50 + 0x8))
-#define HW_DRI_DEBUG1_TOG                           (*(volatile unsigned long *)(REGS_DRI_BASE + 0x50 + 0xc))
-#define BP_DRI_DEBUG1_INVERT_PILOT                  31
-#define BM_DRI_DEBUG1_INVERT_PILOT                  0x80000000
-#define BV_DRI_DEBUG1_INVERT_PILOT__NORMAL          0x0
-#define BV_DRI_DEBUG1_INVERT_PILOT__INVERTED        0x1
-#define BF_DRI_DEBUG1_INVERT_PILOT(v)               (((v) << 31) & 0x80000000)
-#define BF_DRI_DEBUG1_INVERT_PILOT_V(v)             ((BV_DRI_DEBUG1_INVERT_PILOT__##v << 31) & 0x80000000)
-#define BP_DRI_DEBUG1_INVERT_ATTENTION              30
-#define BM_DRI_DEBUG1_INVERT_ATTENTION              0x40000000
-#define BV_DRI_DEBUG1_INVERT_ATTENTION__NORMAL      0x0
-#define BV_DRI_DEBUG1_INVERT_ATTENTION__INVERTED    0x1
-#define BF_DRI_DEBUG1_INVERT_ATTENTION(v)           (((v) << 30) & 0x40000000)
-#define BF_DRI_DEBUG1_INVERT_ATTENTION_V(v)         ((BV_DRI_DEBUG1_INVERT_ATTENTION__##v << 30) & 0x40000000)
-#define BP_DRI_DEBUG1_INVERT_DRI_DATA               29
-#define BM_DRI_DEBUG1_INVERT_DRI_DATA               0x20000000
-#define BV_DRI_DEBUG1_INVERT_DRI_DATA__NORMAL       0x0
-#define BV_DRI_DEBUG1_INVERT_DRI_DATA__INVERTED     0x1
-#define BF_DRI_DEBUG1_INVERT_DRI_DATA(v)            (((v) << 29) & 0x20000000)
-#define BF_DRI_DEBUG1_INVERT_DRI_DATA_V(v)          ((BV_DRI_DEBUG1_INVERT_DRI_DATA__##v << 29) & 0x20000000)
-#define BP_DRI_DEBUG1_INVERT_DRI_CLOCK              28
-#define BM_DRI_DEBUG1_INVERT_DRI_CLOCK              0x10000000
-#define BV_DRI_DEBUG1_INVERT_DRI_CLOCK__NORMAL      0x0
-#define BV_DRI_DEBUG1_INVERT_DRI_CLOCK__INVERTED    0x1
-#define BF_DRI_DEBUG1_INVERT_DRI_CLOCK(v)           (((v) << 28) & 0x10000000)
-#define BF_DRI_DEBUG1_INVERT_DRI_CLOCK_V(v)         ((BV_DRI_DEBUG1_INVERT_DRI_CLOCK__##v << 28) & 0x10000000)
-#define BP_DRI_DEBUG1_REVERSE_FRAME                 27
-#define BM_DRI_DEBUG1_REVERSE_FRAME                 0x8000000
-#define BV_DRI_DEBUG1_REVERSE_FRAME__NORMAL         0x0
-#define BV_DRI_DEBUG1_REVERSE_FRAME__REVERSED       0x1
-#define BF_DRI_DEBUG1_REVERSE_FRAME(v)              (((v) << 27) & 0x8000000)
-#define BF_DRI_DEBUG1_REVERSE_FRAME_V(v)            ((BV_DRI_DEBUG1_REVERSE_FRAME__##v << 27) & 0x8000000)
-#define BP_DRI_DEBUG1_SWIZZLED_FRAME                0
-#define BM_DRI_DEBUG1_SWIZZLED_FRAME                0x3ffff
-#define BF_DRI_DEBUG1_SWIZZLED_FRAME(v)             (((v) << 0) & 0x3ffff)
-
-#endif /* __HEADERGEN__STMP3600__DRI__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-emi.h b/firmware/target/arm/imx233/regs/stmp3600/regs-emi.h
deleted file mode 100644
index 7734cc05be..0000000000
--- a/firmware/target/arm/imx233/regs/stmp3600/regs-emi.h
+++ /dev/null
@@ -1,284 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3600:2.4.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__STMP3600__EMI__H__
-#define __HEADERGEN__STMP3600__EMI__H__
-
-#define REGS_EMI_BASE (0x80020000)
-
-#define REGS_EMI_VERSION "2.4.0"
-
-/**
- * Register: HW_EMI_CTRL
- * Address: 0
- * SCT: yes
-*/
-#define HW_EMI_CTRL                     (*(volatile unsigned long *)(REGS_EMI_BASE + 0x0 + 0x0))
-#define HW_EMI_CTRL_SET                 (*(volatile unsigned long *)(REGS_EMI_BASE + 0x0 + 0x4))
-#define HW_EMI_CTRL_CLR                 (*(volatile unsigned long *)(REGS_EMI_BASE + 0x0 + 0x8))
-#define HW_EMI_CTRL_TOG                 (*(volatile unsigned long *)(REGS_EMI_BASE + 0x0 + 0xc))
-#define BP_EMI_CTRL_SFTRST              31
-#define BM_EMI_CTRL_SFTRST              0x80000000
-#define BF_EMI_CTRL_SFTRST(v)           (((v) << 31) & 0x80000000)
-#define BP_EMI_CTRL_CLKGATE             30
-#define BM_EMI_CTRL_CLKGATE             0x40000000
-#define BF_EMI_CTRL_CLKGATE(v)          (((v) << 30) & 0x40000000)
-#define BP_EMI_CTRL_CE3_MODE            3
-#define BM_EMI_CTRL_CE3_MODE            0x8
-#define BV_EMI_CTRL_CE3_MODE__STATIC    0x0
-#define BV_EMI_CTRL_CE3_MODE__DRAM      0x1
-#define BF_EMI_CTRL_CE3_MODE(v)         (((v) << 3) & 0x8)
-#define BF_EMI_CTRL_CE3_MODE_V(v)       ((BV_EMI_CTRL_CE3_MODE__##v << 3) & 0x8)
-#define BP_EMI_CTRL_CE2_MODE            2
-#define BM_EMI_CTRL_CE2_MODE            0x4
-#define BV_EMI_CTRL_CE2_MODE__STATIC    0x0
-#define BV_EMI_CTRL_CE2_MODE__DRAM      0x1
-#define BF_EMI_CTRL_CE2_MODE(v)         (((v) << 2) & 0x4)
-#define BF_EMI_CTRL_CE2_MODE_V(v)       ((BV_EMI_CTRL_CE2_MODE__##v << 2) & 0x4)
-#define BP_EMI_CTRL_CE1_MODE            1
-#define BM_EMI_CTRL_CE1_MODE            0x2
-#define BV_EMI_CTRL_CE1_MODE__STATIC    0x0
-#define BV_EMI_CTRL_CE1_MODE__DRAM      0x1
-#define BF_EMI_CTRL_CE1_MODE(v)         (((v) << 1) & 0x2)
-#define BF_EMI_CTRL_CE1_MODE_V(v)       ((BV_EMI_CTRL_CE1_MODE__##v << 1) & 0x2)
-#define BP_EMI_CTRL_CE0_MODE            0
-#define BM_EMI_CTRL_CE0_MODE            0x1
-#define BV_EMI_CTRL_CE0_MODE__STATIC    0x0
-#define BV_EMI_CTRL_CE0_MODE__DRAM      0x1
-#define BF_EMI_CTRL_CE0_MODE(v)         (((v) << 0) & 0x1)
-#define BF_EMI_CTRL_CE0_MODE_V(v)       ((BV_EMI_CTRL_CE0_MODE__##v << 0) & 0x1)
-
-/**
- * Register: HW_EMI_STAT
- * Address: 0x10
- * SCT: no
-*/
-#define HW_EMI_STAT                                 (*(volatile unsigned long *)(REGS_EMI_BASE + 0x10))
-#define BP_EMI_STAT_DRAM_PRESENT                    31
-#define BM_EMI_STAT_DRAM_PRESENT                    0x80000000
-#define BF_EMI_STAT_DRAM_PRESENT(v)                 (((v) << 31) & 0x80000000)
-#define BP_EMI_STAT_STATIC_PRESENT                  30
-#define BM_EMI_STAT_STATIC_PRESENT                  0x40000000
-#define BF_EMI_STAT_STATIC_PRESENT(v)               (((v) << 30) & 0x40000000)
-#define BP_EMI_STAT_LARGE_DRAM_ENABLED              29
-#define BM_EMI_STAT_LARGE_DRAM_ENABLED              0x20000000
-#define BF_EMI_STAT_LARGE_DRAM_ENABLED(v)           (((v) << 29) & 0x20000000)
-#define BP_EMI_STAT_WRITE_BUFFER_DATA               1
-#define BM_EMI_STAT_WRITE_BUFFER_DATA               0x2
-#define BV_EMI_STAT_WRITE_BUFFER_DATA__EMPTY        0x0
-#define BV_EMI_STAT_WRITE_BUFFER_DATA__NOT_EMPTY    0x1
-#define BF_EMI_STAT_WRITE_BUFFER_DATA(v)            (((v) << 1) & 0x2)
-#define BF_EMI_STAT_WRITE_BUFFER_DATA_V(v)          ((BV_EMI_STAT_WRITE_BUFFER_DATA__##v << 1) & 0x2)
-#define BP_EMI_STAT_BUSY                            0
-#define BM_EMI_STAT_BUSY                            0x1
-#define BV_EMI_STAT_BUSY__NOT_BUSY                  0x0
-#define BV_EMI_STAT_BUSY__BUSY                      0x1
-#define BF_EMI_STAT_BUSY(v)                         (((v) << 0) & 0x1)
-#define BF_EMI_STAT_BUSY_V(v)                       ((BV_EMI_STAT_BUSY__##v << 0) & 0x1)
-
-/**
- * Register: HW_EMI_DEBUG
- * Address: 0x20
- * SCT: no
-*/
-#define HW_EMI_DEBUG                    (*(volatile unsigned long *)(REGS_EMI_BASE + 0x20))
-#define BP_EMI_DEBUG_STATIC_STATE       16
-#define BM_EMI_DEBUG_STATIC_STATE       0x70000
-#define BF_EMI_DEBUG_STATIC_STATE(v)    (((v) << 16) & 0x70000)
-#define BP_EMI_DEBUG_DRAM_STATE         0
-#define BM_EMI_DEBUG_DRAM_STATE         0x1f
-#define BF_EMI_DEBUG_DRAM_STATE(v)      (((v) << 0) & 0x1f)
-
-/**
- * Register: HW_EMI_DRAMSTAT
- * Address: 0x80
- * SCT: no
-*/
-#define HW_EMI_DRAMSTAT                     (*(volatile unsigned long *)(REGS_EMI_BASE + 0x80))
-#define BP_EMI_DRAMSTAT_SELF_REFRESH_ACK    2
-#define BM_EMI_DRAMSTAT_SELF_REFRESH_ACK    0x4
-#define BF_EMI_DRAMSTAT_SELF_REFRESH_ACK(v) (((v) << 2) & 0x4)
-#define BP_EMI_DRAMSTAT_BUSY                1
-#define BM_EMI_DRAMSTAT_BUSY                0x2
-#define BF_EMI_DRAMSTAT_BUSY(v)             (((v) << 1) & 0x2)
-#define BP_EMI_DRAMSTAT_READY               0
-#define BM_EMI_DRAMSTAT_READY               0x1
-#define BF_EMI_DRAMSTAT_READY(v)            (((v) << 0) & 0x1)
-
-/**
- * Register: HW_EMI_DRAMCTRL
- * Address: 0x90
- * SCT: yes
-*/
-#define HW_EMI_DRAMCTRL                     (*(volatile unsigned long *)(REGS_EMI_BASE + 0x90 + 0x0))
-#define HW_EMI_DRAMCTRL_SET                 (*(volatile unsigned long *)(REGS_EMI_BASE + 0x90 + 0x4))
-#define HW_EMI_DRAMCTRL_CLR                 (*(volatile unsigned long *)(REGS_EMI_BASE + 0x90 + 0x8))
-#define HW_EMI_DRAMCTRL_TOG                 (*(volatile unsigned long *)(REGS_EMI_BASE + 0x90 + 0xc))
-#define BP_EMI_DRAMCTRL_EMICLK_DIVIDE       24
-#define BM_EMI_DRAMCTRL_EMICLK_DIVIDE       0x7000000
-#define BF_EMI_DRAMCTRL_EMICLK_DIVIDE(v)    (((v) << 24) & 0x7000000)
-#define BP_EMI_DRAMCTRL_AUTO_EMICLK_GATE    23
-#define BM_EMI_DRAMCTRL_AUTO_EMICLK_GATE    0x800000
-#define BF_EMI_DRAMCTRL_AUTO_EMICLK_GATE(v) (((v) << 23) & 0x800000)
-#define BP_EMI_DRAMCTRL_EMICLK_ENABLE       21
-#define BM_EMI_DRAMCTRL_EMICLK_ENABLE       0x200000
-#define BF_EMI_DRAMCTRL_EMICLK_ENABLE(v)    (((v) << 21) & 0x200000)
-#define BP_EMI_DRAMCTRL_EMICLKEN_ENABLE     20
-#define BM_EMI_DRAMCTRL_EMICLKEN_ENABLE     0x100000
-#define BF_EMI_DRAMCTRL_EMICLKEN_ENABLE(v)  (((v) << 20) & 0x100000)
-#define BP_EMI_DRAMCTRL_DRAM_TYPE           16
-#define BM_EMI_DRAMCTRL_DRAM_TYPE           0xf0000
-#define BF_EMI_DRAMCTRL_DRAM_TYPE(v)        (((v) << 16) & 0xf0000)
-#define BP_EMI_DRAMCTRL_PRECHARGE           2
-#define BM_EMI_DRAMCTRL_PRECHARGE           0x4
-#define BF_EMI_DRAMCTRL_PRECHARGE(v)        (((v) << 2) & 0x4)
-#define BP_EMI_DRAMCTRL_SELF_REFRESH        1
-#define BM_EMI_DRAMCTRL_SELF_REFRESH        0x2
-#define BF_EMI_DRAMCTRL_SELF_REFRESH(v)     (((v) << 1) & 0x2)
-
-/**
- * Register: HW_EMI_DRAMADDR
- * Address: 0xa0
- * SCT: yes
-*/
-#define HW_EMI_DRAMADDR                 (*(volatile unsigned long *)(REGS_EMI_BASE + 0xa0 + 0x0))
-#define HW_EMI_DRAMADDR_SET             (*(volatile unsigned long *)(REGS_EMI_BASE + 0xa0 + 0x4))
-#define HW_EMI_DRAMADDR_CLR             (*(volatile unsigned long *)(REGS_EMI_BASE + 0xa0 + 0x8))
-#define HW_EMI_DRAMADDR_TOG             (*(volatile unsigned long *)(REGS_EMI_BASE + 0xa0 + 0xc))
-#define BP_EMI_DRAMADDR_MODE            8
-#define BM_EMI_DRAMADDR_MODE            0x100
-#define BV_EMI_DRAMADDR_MODE__RBC       0x0
-#define BV_EMI_DRAMADDR_MODE__BRC       0x1
-#define BF_EMI_DRAMADDR_MODE(v)         (((v) << 8) & 0x100)
-#define BF_EMI_DRAMADDR_MODE_V(v)       ((BV_EMI_DRAMADDR_MODE__##v << 8) & 0x100)
-#define BP_EMI_DRAMADDR_ROW_BITS        4
-#define BM_EMI_DRAMADDR_ROW_BITS        0xf0
-#define BF_EMI_DRAMADDR_ROW_BITS(v)     (((v) << 4) & 0xf0)
-#define BP_EMI_DRAMADDR_COLUMN_BITS     0
-#define BM_EMI_DRAMADDR_COLUMN_BITS     0xf
-#define BF_EMI_DRAMADDR_COLUMN_BITS(v)  (((v) << 0) & 0xf)
-
-/**
- * Register: HW_EMI_DRAMMODE
- * Address: 0xb0
- * SCT: no
-*/
-#define HW_EMI_DRAMMODE                         (*(volatile unsigned long *)(REGS_EMI_BASE + 0xb0))
-#define BP_EMI_DRAMMODE_CAS_LATENCY             4
-#define BM_EMI_DRAMMODE_CAS_LATENCY             0x70
-#define BV_EMI_DRAMMODE_CAS_LATENCY__RESERVED0  0x0
-#define BV_EMI_DRAMMODE_CAS_LATENCY__RESERVED1  0x1
-#define BV_EMI_DRAMMODE_CAS_LATENCY__CAS2       0x2
-#define BV_EMI_DRAMMODE_CAS_LATENCY__CAS3       0x3
-#define BV_EMI_DRAMMODE_CAS_LATENCY__RESERVED4  0x4
-#define BV_EMI_DRAMMODE_CAS_LATENCY__RESERVED5  0x5
-#define BV_EMI_DRAMMODE_CAS_LATENCY__RESERVED6  0x6
-#define BV_EMI_DRAMMODE_CAS_LATENCY__RESERVED7  0x7
-#define BF_EMI_DRAMMODE_CAS_LATENCY(v)          (((v) << 4) & 0x70)
-#define BF_EMI_DRAMMODE_CAS_LATENCY_V(v)        ((BV_EMI_DRAMMODE_CAS_LATENCY__##v << 4) & 0x70)
-
-/**
- * Register: HW_EMI_DRAMTIME
- * Address: 0xc0
- * SCT: yes
-*/
-#define HW_EMI_DRAMTIME                     (*(volatile unsigned long *)(REGS_EMI_BASE + 0xc0 + 0x0))
-#define HW_EMI_DRAMTIME_SET                 (*(volatile unsigned long *)(REGS_EMI_BASE + 0xc0 + 0x4))
-#define HW_EMI_DRAMTIME_CLR                 (*(volatile unsigned long *)(REGS_EMI_BASE + 0xc0 + 0x8))
-#define HW_EMI_DRAMTIME_TOG                 (*(volatile unsigned long *)(REGS_EMI_BASE + 0xc0 + 0xc))
-#define BP_EMI_DRAMTIME_TRFC                24
-#define BM_EMI_DRAMTIME_TRFC                0xf000000
-#define BF_EMI_DRAMTIME_TRFC(v)             (((v) << 24) & 0xf000000)
-#define BP_EMI_DRAMTIME_TRC                 20
-#define BM_EMI_DRAMTIME_TRC                 0xf00000
-#define BF_EMI_DRAMTIME_TRC(v)              (((v) << 20) & 0xf00000)
-#define BP_EMI_DRAMTIME_TRAS                16
-#define BM_EMI_DRAMTIME_TRAS                0xf0000
-#define BF_EMI_DRAMTIME_TRAS(v)             (((v) << 16) & 0xf0000)
-#define BP_EMI_DRAMTIME_TRCD                12
-#define BM_EMI_DRAMTIME_TRCD                0xf000
-#define BF_EMI_DRAMTIME_TRCD(v)             (((v) << 12) & 0xf000)
-#define BP_EMI_DRAMTIME_TRP                 8
-#define BM_EMI_DRAMTIME_TRP                 0x300
-#define BF_EMI_DRAMTIME_TRP(v)              (((v) << 8) & 0x300)
-#define BP_EMI_DRAMTIME_TXSR                4
-#define BM_EMI_DRAMTIME_TXSR                0xf0
-#define BF_EMI_DRAMTIME_TXSR(v)             (((v) << 4) & 0xf0)
-#define BP_EMI_DRAMTIME_REFRESH_COUNTER     0
-#define BM_EMI_DRAMTIME_REFRESH_COUNTER     0xf
-#define BF_EMI_DRAMTIME_REFRESH_COUNTER(v)  (((v) << 0) & 0xf)
-
-/**
- * Register: HW_EMI_DRAMTIME2
- * Address: 0xd0
- * SCT: yes
-*/
-#define HW_EMI_DRAMTIME2                    (*(volatile unsigned long *)(REGS_EMI_BASE + 0xd0 + 0x0))
-#define HW_EMI_DRAMTIME2_SET                (*(volatile unsigned long *)(REGS_EMI_BASE + 0xd0 + 0x4))
-#define HW_EMI_DRAMTIME2_CLR                (*(volatile unsigned long *)(REGS_EMI_BASE + 0xd0 + 0x8))
-#define HW_EMI_DRAMTIME2_TOG                (*(volatile unsigned long *)(REGS_EMI_BASE + 0xd0 + 0xc))
-#define BP_EMI_DRAMTIME2_PRECHARGE_COUNT    0
-#define BM_EMI_DRAMTIME2_PRECHARGE_COUNT    0xffff
-#define BF_EMI_DRAMTIME2_PRECHARGE_COUNT(v) (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_EMI_STATICCTRL
- * Address: 0x100
- * SCT: yes
-*/
-#define HW_EMI_STATICCTRL                   (*(volatile unsigned long *)(REGS_EMI_BASE + 0x100 + 0x0))
-#define HW_EMI_STATICCTRL_SET               (*(volatile unsigned long *)(REGS_EMI_BASE + 0x100 + 0x4))
-#define HW_EMI_STATICCTRL_CLR               (*(volatile unsigned long *)(REGS_EMI_BASE + 0x100 + 0x8))
-#define HW_EMI_STATICCTRL_TOG               (*(volatile unsigned long *)(REGS_EMI_BASE + 0x100 + 0xc))
-#define BP_EMI_STATICCTRL_MEM_WIDTH         2
-#define BM_EMI_STATICCTRL_MEM_WIDTH         0x4
-#define BF_EMI_STATICCTRL_MEM_WIDTH(v)      (((v) << 2) & 0x4)
-#define BP_EMI_STATICCTRL_WRITE_PROTECT     1
-#define BM_EMI_STATICCTRL_WRITE_PROTECT     0x2
-#define BF_EMI_STATICCTRL_WRITE_PROTECT(v)  (((v) << 1) & 0x2)
-#define BP_EMI_STATICCTRL_RESET_OUT         0
-#define BM_EMI_STATICCTRL_RESET_OUT         0x1
-#define BF_EMI_STATICCTRL_RESET_OUT(v)      (((v) << 0) & 0x1)
-
-/**
- * Register: HW_EMI_STATICTIME
- * Address: 0x110
- * SCT: yes
-*/
-#define HW_EMI_STATICTIME           (*(volatile unsigned long *)(REGS_EMI_BASE + 0x110 + 0x0))
-#define HW_EMI_STATICTIME_SET       (*(volatile unsigned long *)(REGS_EMI_BASE + 0x110 + 0x4))
-#define HW_EMI_STATICTIME_CLR       (*(volatile unsigned long *)(REGS_EMI_BASE + 0x110 + 0x8))
-#define HW_EMI_STATICTIME_TOG       (*(volatile unsigned long *)(REGS_EMI_BASE + 0x110 + 0xc))
-#define BP_EMI_STATICTIME_THZ       24
-#define BM_EMI_STATICTIME_THZ       0xf000000
-#define BF_EMI_STATICTIME_THZ(v)    (((v) << 24) & 0xf000000)
-#define BP_EMI_STATICTIME_TDH       16
-#define BM_EMI_STATICTIME_TDH       0xf0000
-#define BF_EMI_STATICTIME_TDH(v)    (((v) << 16) & 0xf0000)
-#define BP_EMI_STATICTIME_TDS       8
-#define BM_EMI_STATICTIME_TDS       0xf00
-#define BF_EMI_STATICTIME_TDS(v)    (((v) << 8) & 0xf00)
-#define BP_EMI_STATICTIME_TAS       0
-#define BM_EMI_STATICTIME_TAS       0xf
-#define BF_EMI_STATICTIME_TAS(v)    (((v) << 0) & 0xf)
-
-#endif /* __HEADERGEN__STMP3600__EMI__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-gpmi.h b/firmware/target/arm/imx233/regs/stmp3600/regs-gpmi.h
deleted file mode 100644
index e10517919e..0000000000
--- a/firmware/target/arm/imx233/regs/stmp3600/regs-gpmi.h
+++ /dev/null
@@ -1,372 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3600:2.3.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__STMP3600__GPMI__H__
-#define __HEADERGEN__STMP3600__GPMI__H__
-
-#define REGS_GPMI_BASE (0x8000c000)
-
-#define REGS_GPMI_VERSION "2.3.0"
-
-/**
- * Register: HW_GPMI_CTRL0
- * Address: 0
- * SCT: yes
-*/
-#define HW_GPMI_CTRL0                                   (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x0 + 0x0))
-#define HW_GPMI_CTRL0_SET                               (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x0 + 0x4))
-#define HW_GPMI_CTRL0_CLR                               (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x0 + 0x8))
-#define HW_GPMI_CTRL0_TOG                               (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x0 + 0xc))
-#define BP_GPMI_CTRL0_SFTRST                            31
-#define BM_GPMI_CTRL0_SFTRST                            0x80000000
-#define BV_GPMI_CTRL0_SFTRST__RUN                       0x0
-#define BV_GPMI_CTRL0_SFTRST__RESET                     0x1
-#define BF_GPMI_CTRL0_SFTRST(v)                         (((v) << 31) & 0x80000000)
-#define BF_GPMI_CTRL0_SFTRST_V(v)                       ((BV_GPMI_CTRL0_SFTRST__##v << 31) & 0x80000000)
-#define BP_GPMI_CTRL0_CLKGATE                           30
-#define BM_GPMI_CTRL0_CLKGATE                           0x40000000
-#define BV_GPMI_CTRL0_CLKGATE__RUN                      0x0
-#define BV_GPMI_CTRL0_CLKGATE__NO_CLKS                  0x1
-#define BF_GPMI_CTRL0_CLKGATE(v)                        (((v) << 30) & 0x40000000)
-#define BF_GPMI_CTRL0_CLKGATE_V(v)                      ((BV_GPMI_CTRL0_CLKGATE__##v << 30) & 0x40000000)
-#define BP_GPMI_CTRL0_RUN                               29
-#define BM_GPMI_CTRL0_RUN                               0x20000000
-#define BV_GPMI_CTRL0_RUN__IDLE                         0x0
-#define BV_GPMI_CTRL0_RUN__BUSY                         0x1
-#define BF_GPMI_CTRL0_RUN(v)                            (((v) << 29) & 0x20000000)
-#define BF_GPMI_CTRL0_RUN_V(v)                          ((BV_GPMI_CTRL0_RUN__##v << 29) & 0x20000000)
-#define BP_GPMI_CTRL0_DEV_IRQ_EN                        28
-#define BM_GPMI_CTRL0_DEV_IRQ_EN                        0x10000000
-#define BF_GPMI_CTRL0_DEV_IRQ_EN(v)                     (((v) << 28) & 0x10000000)
-#define BP_GPMI_CTRL0_TIMEOUT_IRQ_EN                    27
-#define BM_GPMI_CTRL0_TIMEOUT_IRQ_EN                    0x8000000
-#define BF_GPMI_CTRL0_TIMEOUT_IRQ_EN(v)                 (((v) << 27) & 0x8000000)
-#define BP_GPMI_CTRL0_UDMA                              26
-#define BM_GPMI_CTRL0_UDMA                              0x4000000
-#define BV_GPMI_CTRL0_UDMA__DISABLED                    0x0
-#define BV_GPMI_CTRL0_UDMA__ENABLED                     0x1
-#define BF_GPMI_CTRL0_UDMA(v)                           (((v) << 26) & 0x4000000)
-#define BF_GPMI_CTRL0_UDMA_V(v)                         ((BV_GPMI_CTRL0_UDMA__##v << 26) & 0x4000000)
-#define BP_GPMI_CTRL0_COMMAND_MODE                      24
-#define BM_GPMI_CTRL0_COMMAND_MODE                      0x3000000
-#define BV_GPMI_CTRL0_COMMAND_MODE__WRITE               0x0
-#define BV_GPMI_CTRL0_COMMAND_MODE__READ                0x1
-#define BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE    0x2
-#define BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY      0x3
-#define BF_GPMI_CTRL0_COMMAND_MODE(v)                   (((v) << 24) & 0x3000000)
-#define BF_GPMI_CTRL0_COMMAND_MODE_V(v)                 ((BV_GPMI_CTRL0_COMMAND_MODE__##v << 24) & 0x3000000)
-#define BP_GPMI_CTRL0_WORD_LENGTH                       23
-#define BM_GPMI_CTRL0_WORD_LENGTH                       0x800000
-#define BV_GPMI_CTRL0_WORD_LENGTH__16_BIT               0x0
-#define BV_GPMI_CTRL0_WORD_LENGTH__8_BIT                0x1
-#define BF_GPMI_CTRL0_WORD_LENGTH(v)                    (((v) << 23) & 0x800000)
-#define BF_GPMI_CTRL0_WORD_LENGTH_V(v)                  ((BV_GPMI_CTRL0_WORD_LENGTH__##v << 23) & 0x800000)
-#define BP_GPMI_CTRL0_LOCK_CS                           22
-#define BM_GPMI_CTRL0_LOCK_CS                           0x400000
-#define BV_GPMI_CTRL0_LOCK_CS__DISABLED                 0x0
-#define BV_GPMI_CTRL0_LOCK_CS__ENABLED                  0x1
-#define BF_GPMI_CTRL0_LOCK_CS(v)                        (((v) << 22) & 0x400000)
-#define BF_GPMI_CTRL0_LOCK_CS_V(v)                      ((BV_GPMI_CTRL0_LOCK_CS__##v << 22) & 0x400000)
-#define BP_GPMI_CTRL0_CS                                20
-#define BM_GPMI_CTRL0_CS                                0x300000
-#define BF_GPMI_CTRL0_CS(v)                             (((v) << 20) & 0x300000)
-#define BP_GPMI_CTRL0_ADDRESS                           17
-#define BM_GPMI_CTRL0_ADDRESS                           0xe0000
-#define BV_GPMI_CTRL0_ADDRESS__NAND_DATA                0x0
-#define BV_GPMI_CTRL0_ADDRESS__NAND_CLE                 0x1
-#define BV_GPMI_CTRL0_ADDRESS__NAND_ALE                 0x2
-#define BF_GPMI_CTRL0_ADDRESS(v)                        (((v) << 17) & 0xe0000)
-#define BF_GPMI_CTRL0_ADDRESS_V(v)                      ((BV_GPMI_CTRL0_ADDRESS__##v << 17) & 0xe0000)
-#define BP_GPMI_CTRL0_ADDRESS_INCREMENT                 16
-#define BM_GPMI_CTRL0_ADDRESS_INCREMENT                 0x10000
-#define BV_GPMI_CTRL0_ADDRESS_INCREMENT__DISABLED       0x0
-#define BV_GPMI_CTRL0_ADDRESS_INCREMENT__ENABLED        0x1
-#define BF_GPMI_CTRL0_ADDRESS_INCREMENT(v)              (((v) << 16) & 0x10000)
-#define BF_GPMI_CTRL0_ADDRESS_INCREMENT_V(v)            ((BV_GPMI_CTRL0_ADDRESS_INCREMENT__##v << 16) & 0x10000)
-#define BP_GPMI_CTRL0_XFER_COUNT                        0
-#define BM_GPMI_CTRL0_XFER_COUNT                        0xffff
-#define BF_GPMI_CTRL0_XFER_COUNT(v)                     (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_GPMI_COMPARE
- * Address: 0x10
- * SCT: no
-*/
-#define HW_GPMI_COMPARE                 (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x10))
-#define BP_GPMI_COMPARE_MASK            16
-#define BM_GPMI_COMPARE_MASK            0xffff0000
-#define BF_GPMI_COMPARE_MASK(v)         (((v) << 16) & 0xffff0000)
-#define BP_GPMI_COMPARE_REFERENCE       0
-#define BM_GPMI_COMPARE_REFERENCE       0xffff
-#define BF_GPMI_COMPARE_REFERENCE(v)    (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_GPMI_CTRL1
- * Address: 0x20
- * SCT: yes
-*/
-#define HW_GPMI_CTRL1                                   (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x20 + 0x0))
-#define HW_GPMI_CTRL1_SET                               (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x20 + 0x4))
-#define HW_GPMI_CTRL1_CLR                               (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x20 + 0x8))
-#define HW_GPMI_CTRL1_TOG                               (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x20 + 0xc))
-#define BP_GPMI_CTRL1_DSAMPLE_TIME                      12
-#define BM_GPMI_CTRL1_DSAMPLE_TIME                      0x3000
-#define BF_GPMI_CTRL1_DSAMPLE_TIME(v)                   (((v) << 12) & 0x3000)
-#define BP_GPMI_CTRL1_DEV_IRQ                           10
-#define BM_GPMI_CTRL1_DEV_IRQ                           0x400
-#define BF_GPMI_CTRL1_DEV_IRQ(v)                        (((v) << 10) & 0x400)
-#define BP_GPMI_CTRL1_TIMEOUT_IRQ                       9
-#define BM_GPMI_CTRL1_TIMEOUT_IRQ                       0x200
-#define BF_GPMI_CTRL1_TIMEOUT_IRQ(v)                    (((v) << 9) & 0x200)
-#define BP_GPMI_CTRL1_BURST_EN                          8
-#define BM_GPMI_CTRL1_BURST_EN                          0x100
-#define BF_GPMI_CTRL1_BURST_EN(v)                       (((v) << 8) & 0x100)
-#define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY3             7
-#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY3             0x80
-#define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY3(v)          (((v) << 7) & 0x80)
-#define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY2             6
-#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY2             0x40
-#define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY2(v)          (((v) << 6) & 0x40)
-#define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY1             5
-#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY1             0x20
-#define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY1(v)          (((v) << 5) & 0x20)
-#define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY0             4
-#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY0             0x10
-#define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY0(v)          (((v) << 4) & 0x10)
-#define BP_GPMI_CTRL1_DEV_RESET                         3
-#define BM_GPMI_CTRL1_DEV_RESET                         0x8
-#define BV_GPMI_CTRL1_DEV_RESET__ENABLED                0x0
-#define BV_GPMI_CTRL1_DEV_RESET__DISABLED               0x1
-#define BF_GPMI_CTRL1_DEV_RESET(v)                      (((v) << 3) & 0x8)
-#define BF_GPMI_CTRL1_DEV_RESET_V(v)                    ((BV_GPMI_CTRL1_DEV_RESET__##v << 3) & 0x8)
-#define BP_GPMI_CTRL1_ATA_IRQRDY_POLARITY               2
-#define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY               0x4
-#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVELOW    0x0
-#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVEHIGH   0x1
-#define BF_GPMI_CTRL1_ATA_IRQRDY_POLARITY(v)            (((v) << 2) & 0x4)
-#define BF_GPMI_CTRL1_ATA_IRQRDY_POLARITY_V(v)          ((BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__##v << 2) & 0x4)
-#define BP_GPMI_CTRL1_CAMERA_MODE                       1
-#define BM_GPMI_CTRL1_CAMERA_MODE                       0x2
-#define BF_GPMI_CTRL1_CAMERA_MODE(v)                    (((v) << 1) & 0x2)
-#define BP_GPMI_CTRL1_GPMI_MODE                         0
-#define BM_GPMI_CTRL1_GPMI_MODE                         0x1
-#define BV_GPMI_CTRL1_GPMI_MODE__NAND                   0x0
-#define BV_GPMI_CTRL1_GPMI_MODE__ATA                    0x1
-#define BF_GPMI_CTRL1_GPMI_MODE(v)                      (((v) << 0) & 0x1)
-#define BF_GPMI_CTRL1_GPMI_MODE_V(v)                    ((BV_GPMI_CTRL1_GPMI_MODE__##v << 0) & 0x1)
-
-/**
- * Register: HW_GPMI_TIMING0
- * Address: 0x30
- * SCT: no
-*/
-#define HW_GPMI_TIMING0                     (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x30))
-#define BP_GPMI_TIMING0_ADDRESS_SETUP       16
-#define BM_GPMI_TIMING0_ADDRESS_SETUP       0xff0000
-#define BF_GPMI_TIMING0_ADDRESS_SETUP(v)    (((v) << 16) & 0xff0000)
-#define BP_GPMI_TIMING0_DATA_HOLD           8
-#define BM_GPMI_TIMING0_DATA_HOLD           0xff00
-#define BF_GPMI_TIMING0_DATA_HOLD(v)        (((v) << 8) & 0xff00)
-#define BP_GPMI_TIMING0_DATA_SETUP          0
-#define BM_GPMI_TIMING0_DATA_SETUP          0xff
-#define BF_GPMI_TIMING0_DATA_SETUP(v)       (((v) << 0) & 0xff)
-
-/**
- * Register: HW_GPMI_TIMING1
- * Address: 0x40
- * SCT: no
-*/
-#define HW_GPMI_TIMING1                         (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x40))
-#define BP_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT     16
-#define BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT     0xffff0000
-#define BF_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(v)  (((v) << 16) & 0xffff0000)
-#define BP_GPMI_TIMING1_ATA_READY_TIMEOUT       0
-#define BM_GPMI_TIMING1_ATA_READY_TIMEOUT       0xffff
-#define BF_GPMI_TIMING1_ATA_READY_TIMEOUT(v)    (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_GPMI_TIMING2
- * Address: 0x50
- * SCT: no
-*/
-#define HW_GPMI_TIMING2                 (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x50))
-#define BP_GPMI_TIMING2_UDMA_TRP        24
-#define BM_GPMI_TIMING2_UDMA_TRP        0xff000000
-#define BF_GPMI_TIMING2_UDMA_TRP(v)     (((v) << 24) & 0xff000000)
-#define BP_GPMI_TIMING2_UDMA_ENV        16
-#define BM_GPMI_TIMING2_UDMA_ENV        0xff0000
-#define BF_GPMI_TIMING2_UDMA_ENV(v)     (((v) << 16) & 0xff0000)
-#define BP_GPMI_TIMING2_UDMA_HOLD       8
-#define BM_GPMI_TIMING2_UDMA_HOLD       0xff00
-#define BF_GPMI_TIMING2_UDMA_HOLD(v)    (((v) << 8) & 0xff00)
-#define BP_GPMI_TIMING2_UDMA_SETUP      0
-#define BM_GPMI_TIMING2_UDMA_SETUP      0xff
-#define BF_GPMI_TIMING2_UDMA_SETUP(v)   (((v) << 0) & 0xff)
-
-/**
- * Register: HW_GPMI_DATA
- * Address: 0x60
- * SCT: no
-*/
-#define HW_GPMI_DATA            (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x60))
-#define BP_GPMI_DATA_DATA       0
-#define BM_GPMI_DATA_DATA       0xffffffff
-#define BF_GPMI_DATA_DATA(v)    (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_GPMI_STAT
- * Address: 0x70
- * SCT: no
-*/
-#define HW_GPMI_STAT                        (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x70))
-#define BP_GPMI_STAT_PRESENT                31
-#define BM_GPMI_STAT_PRESENT                0x80000000
-#define BV_GPMI_STAT_PRESENT__UNAVAILABLE   0x0
-#define BV_GPMI_STAT_PRESENT__AVAILABLE     0x1
-#define BF_GPMI_STAT_PRESENT(v)             (((v) << 31) & 0x80000000)
-#define BF_GPMI_STAT_PRESENT_V(v)           ((BV_GPMI_STAT_PRESENT__##v << 31) & 0x80000000)
-#define BP_GPMI_STAT_RDY_TIMEOUT            8
-#define BM_GPMI_STAT_RDY_TIMEOUT            0xf00
-#define BF_GPMI_STAT_RDY_TIMEOUT(v)         (((v) << 8) & 0xf00)
-#define BP_GPMI_STAT_ATA_IRQ                7
-#define BM_GPMI_STAT_ATA_IRQ                0x80
-#define BF_GPMI_STAT_ATA_IRQ(v)             (((v) << 7) & 0x80)
-#define BP_GPMI_STAT_FIFO_EMPTY             5
-#define BM_GPMI_STAT_FIFO_EMPTY             0x20
-#define BV_GPMI_STAT_FIFO_EMPTY__NOT_EMPTY  0x0
-#define BV_GPMI_STAT_FIFO_EMPTY__EMPTY      0x1
-#define BF_GPMI_STAT_FIFO_EMPTY(v)          (((v) << 5) & 0x20)
-#define BF_GPMI_STAT_FIFO_EMPTY_V(v)        ((BV_GPMI_STAT_FIFO_EMPTY__##v << 5) & 0x20)
-#define BP_GPMI_STAT_FIFO_FULL              4
-#define BM_GPMI_STAT_FIFO_FULL              0x10
-#define BV_GPMI_STAT_FIFO_FULL__NOT_FULL    0x0
-#define BV_GPMI_STAT_FIFO_FULL__FULL        0x1
-#define BF_GPMI_STAT_FIFO_FULL(v)           (((v) << 4) & 0x10)
-#define BF_GPMI_STAT_FIFO_FULL_V(v)         ((BV_GPMI_STAT_FIFO_FULL__##v << 4) & 0x10)
-#define BP_GPMI_STAT_DEV3_ERROR             3
-#define BM_GPMI_STAT_DEV3_ERROR             0x8
-#define BF_GPMI_STAT_DEV3_ERROR(v)          (((v) << 3) & 0x8)
-#define BP_GPMI_STAT_DEV2_ERROR             2
-#define BM_GPMI_STAT_DEV2_ERROR             0x4
-#define BF_GPMI_STAT_DEV2_ERROR(v)          (((v) << 2) & 0x4)
-#define BP_GPMI_STAT_DEV1_ERROR             1
-#define BM_GPMI_STAT_DEV1_ERROR             0x2
-#define BF_GPMI_STAT_DEV1_ERROR(v)          (((v) << 1) & 0x2)
-#define BP_GPMI_STAT_DEV0_ERROR             0
-#define BM_GPMI_STAT_DEV0_ERROR             0x1
-#define BF_GPMI_STAT_DEV0_ERROR(v)          (((v) << 0) & 0x1)
-
-/**
- * Register: HW_GPMI_DEBUG
- * Address: 0x80
- * SCT: no
-*/
-#define HW_GPMI_DEBUG                           (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x80))
-#define BP_GPMI_DEBUG_READY3                    31
-#define BM_GPMI_DEBUG_READY3                    0x80000000
-#define BF_GPMI_DEBUG_READY3(v)                 (((v) << 31) & 0x80000000)
-#define BP_GPMI_DEBUG_READY2                    30
-#define BM_GPMI_DEBUG_READY2                    0x40000000
-#define BF_GPMI_DEBUG_READY2(v)                 (((v) << 30) & 0x40000000)
-#define BP_GPMI_DEBUG_READY1                    29
-#define BM_GPMI_DEBUG_READY1                    0x20000000
-#define BF_GPMI_DEBUG_READY1(v)                 (((v) << 29) & 0x20000000)
-#define BP_GPMI_DEBUG_READY0                    28
-#define BM_GPMI_DEBUG_READY0                    0x10000000
-#define BF_GPMI_DEBUG_READY0(v)                 (((v) << 28) & 0x10000000)
-#define BP_GPMI_DEBUG_WAIT_FOR_READY_END3       27
-#define BM_GPMI_DEBUG_WAIT_FOR_READY_END3       0x8000000
-#define BF_GPMI_DEBUG_WAIT_FOR_READY_END3(v)    (((v) << 27) & 0x8000000)
-#define BP_GPMI_DEBUG_WAIT_FOR_READY_END2       26
-#define BM_GPMI_DEBUG_WAIT_FOR_READY_END2       0x4000000
-#define BF_GPMI_DEBUG_WAIT_FOR_READY_END2(v)    (((v) << 26) & 0x4000000)
-#define BP_GPMI_DEBUG_WAIT_FOR_READY_END1       25
-#define BM_GPMI_DEBUG_WAIT_FOR_READY_END1       0x2000000
-#define BF_GPMI_DEBUG_WAIT_FOR_READY_END1(v)    (((v) << 25) & 0x2000000)
-#define BP_GPMI_DEBUG_WAIT_FOR_READY_END0       24
-#define BM_GPMI_DEBUG_WAIT_FOR_READY_END0       0x1000000
-#define BF_GPMI_DEBUG_WAIT_FOR_READY_END0(v)    (((v) << 24) & 0x1000000)
-#define BP_GPMI_DEBUG_SENSE3                    23
-#define BM_GPMI_DEBUG_SENSE3                    0x800000
-#define BF_GPMI_DEBUG_SENSE3(v)                 (((v) << 23) & 0x800000)
-#define BP_GPMI_DEBUG_SENSE2                    22
-#define BM_GPMI_DEBUG_SENSE2                    0x400000
-#define BF_GPMI_DEBUG_SENSE2(v)                 (((v) << 22) & 0x400000)
-#define BP_GPMI_DEBUG_SENSE1                    21
-#define BM_GPMI_DEBUG_SENSE1                    0x200000
-#define BF_GPMI_DEBUG_SENSE1(v)                 (((v) << 21) & 0x200000)
-#define BP_GPMI_DEBUG_SENSE0                    20
-#define BM_GPMI_DEBUG_SENSE0                    0x100000
-#define BF_GPMI_DEBUG_SENSE0(v)                 (((v) << 20) & 0x100000)
-#define BP_GPMI_DEBUG_DMAREQ3                   19
-#define BM_GPMI_DEBUG_DMAREQ3                   0x80000
-#define BF_GPMI_DEBUG_DMAREQ3(v)                (((v) << 19) & 0x80000)
-#define BP_GPMI_DEBUG_DMAREQ2                   18
-#define BM_GPMI_DEBUG_DMAREQ2                   0x40000
-#define BF_GPMI_DEBUG_DMAREQ2(v)                (((v) << 18) & 0x40000)
-#define BP_GPMI_DEBUG_DMAREQ1                   17
-#define BM_GPMI_DEBUG_DMAREQ1                   0x20000
-#define BF_GPMI_DEBUG_DMAREQ1(v)                (((v) << 17) & 0x20000)
-#define BP_GPMI_DEBUG_DMAREQ0                   16
-#define BM_GPMI_DEBUG_DMAREQ0                   0x10000
-#define BF_GPMI_DEBUG_DMAREQ0(v)                (((v) << 16) & 0x10000)
-#define BP_GPMI_DEBUG_CMD_END                   12
-#define BM_GPMI_DEBUG_CMD_END                   0xf000
-#define BF_GPMI_DEBUG_CMD_END(v)                (((v) << 12) & 0xf000)
-#define BP_GPMI_DEBUG_UDMA_STATE                8
-#define BM_GPMI_DEBUG_UDMA_STATE                0xf00
-#define BF_GPMI_DEBUG_UDMA_STATE(v)             (((v) << 8) & 0xf00)
-#define BP_GPMI_DEBUG_BUSY                      7
-#define BM_GPMI_DEBUG_BUSY                      0x80
-#define BV_GPMI_DEBUG_BUSY__DISABLED            0x0
-#define BV_GPMI_DEBUG_BUSY__ENABLED             0x1
-#define BF_GPMI_DEBUG_BUSY(v)                   (((v) << 7) & 0x80)
-#define BF_GPMI_DEBUG_BUSY_V(v)                 ((BV_GPMI_DEBUG_BUSY__##v << 7) & 0x80)
-#define BP_GPMI_DEBUG_PIN_STATE                 4
-#define BM_GPMI_DEBUG_PIN_STATE                 0x70
-#define BV_GPMI_DEBUG_PIN_STATE__PSM_IDLE       0x0
-#define BV_GPMI_DEBUG_PIN_STATE__PSM_BYTCNT     0x1
-#define BV_GPMI_DEBUG_PIN_STATE__PSM_ADDR       0x2
-#define BV_GPMI_DEBUG_PIN_STATE__PSM_STALL      0x3
-#define BV_GPMI_DEBUG_PIN_STATE__PSM_STROBE     0x4
-#define BV_GPMI_DEBUG_PIN_STATE__PSM_ATARDY     0x5
-#define BV_GPMI_DEBUG_PIN_STATE__PSM_DHOLD      0x6
-#define BV_GPMI_DEBUG_PIN_STATE__PSM_DONE       0x7
-#define BF_GPMI_DEBUG_PIN_STATE(v)              (((v) << 4) & 0x70)
-#define BF_GPMI_DEBUG_PIN_STATE_V(v)            ((BV_GPMI_DEBUG_PIN_STATE__##v << 4) & 0x70)
-#define BP_GPMI_DEBUG_MAIN_STATE                0
-#define BM_GPMI_DEBUG_MAIN_STATE                0xf
-#define BV_GPMI_DEBUG_MAIN_STATE__MSM_IDLE      0x0
-#define BV_GPMI_DEBUG_MAIN_STATE__MSM_BYTCNT    0x1
-#define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFE    0x2
-#define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFR    0x3
-#define BV_GPMI_DEBUG_MAIN_STATE__MSM_DMAREQ    0x4
-#define BV_GPMI_DEBUG_MAIN_STATE__MSM_DMAACK    0x5
-#define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFF    0x6
-#define BV_GPMI_DEBUG_MAIN_STATE__MSM_LDFIFO    0x7
-#define BV_GPMI_DEBUG_MAIN_STATE__MSM_LDDMAR    0x8
-#define BV_GPMI_DEBUG_MAIN_STATE__MSM_RDCMP     0x9
-#define BV_GPMI_DEBUG_MAIN_STATE__MSM_DONE      0xa
-#define BF_GPMI_DEBUG_MAIN_STATE(v)             (((v) << 0) & 0xf)
-#define BF_GPMI_DEBUG_MAIN_STATE_V(v)           ((BV_GPMI_DEBUG_MAIN_STATE__##v << 0) & 0xf)
-
-#endif /* __HEADERGEN__STMP3600__GPMI__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-hwecc.h b/firmware/target/arm/imx233/regs/stmp3600/regs-hwecc.h
deleted file mode 100644
index 6e0399cf49..0000000000
--- a/firmware/target/arm/imx233/regs/stmp3600/regs-hwecc.h
+++ /dev/null
@@ -1,223 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3600:2.3.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__STMP3600__HWECC__H__
-#define __HEADERGEN__STMP3600__HWECC__H__
-
-#define REGS_HWECC_BASE (0x80008000)
-
-#define REGS_HWECC_VERSION "2.3.0"
-
-/**
- * Register: HW_HWECC_CTRL
- * Address: 0
- * SCT: yes
-*/
-#define HW_HWECC_CTRL                   (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x0 + 0x0))
-#define HW_HWECC_CTRL_SET               (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x0 + 0x4))
-#define HW_HWECC_CTRL_CLR               (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x0 + 0x8))
-#define HW_HWECC_CTRL_TOG               (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x0 + 0xc))
-#define BP_HWECC_CTRL_SFTRST            31
-#define BM_HWECC_CTRL_SFTRST            0x80000000
-#define BF_HWECC_CTRL_SFTRST(v)         (((v) << 31) & 0x80000000)
-#define BP_HWECC_CTRL_CLKGATE           30
-#define BM_HWECC_CTRL_CLKGATE           0x40000000
-#define BF_HWECC_CTRL_CLKGATE(v)        (((v) << 30) & 0x40000000)
-#define BP_HWECC_CTRL_NUM_SYMBOLS       16
-#define BM_HWECC_CTRL_NUM_SYMBOLS       0x1ff0000
-#define BF_HWECC_CTRL_NUM_SYMBOLS(v)    (((v) << 16) & 0x1ff0000)
-#define BP_HWECC_CTRL_DMAWAIT_COUNT     8
-#define BM_HWECC_CTRL_DMAWAIT_COUNT     0x1f00
-#define BF_HWECC_CTRL_DMAWAIT_COUNT(v)  (((v) << 8) & 0x1f00)
-#define BP_HWECC_CTRL_BYTE_ENABLE       6
-#define BM_HWECC_CTRL_BYTE_ENABLE       0x40
-#define BF_HWECC_CTRL_BYTE_ENABLE(v)    (((v) << 6) & 0x40)
-#define BP_HWECC_CTRL_ECC_SEL           5
-#define BM_HWECC_CTRL_ECC_SEL           0x20
-#define BF_HWECC_CTRL_ECC_SEL(v)        (((v) << 5) & 0x20)
-#define BP_HWECC_CTRL_ENC_SEL           4
-#define BM_HWECC_CTRL_ENC_SEL           0x10
-#define BF_HWECC_CTRL_ENC_SEL(v)        (((v) << 4) & 0x10)
-#define BP_HWECC_CTRL_UNCORR_IRQ        2
-#define BM_HWECC_CTRL_UNCORR_IRQ        0x4
-#define BF_HWECC_CTRL_UNCORR_IRQ(v)     (((v) << 2) & 0x4)
-#define BP_HWECC_CTRL_UNCORR_IRQ_EN     1
-#define BM_HWECC_CTRL_UNCORR_IRQ_EN     0x2
-#define BF_HWECC_CTRL_UNCORR_IRQ_EN(v)  (((v) << 1) & 0x2)
-#define BP_HWECC_CTRL_RUN               0
-#define BM_HWECC_CTRL_RUN               0x1
-#define BF_HWECC_CTRL_RUN(v)            (((v) << 0) & 0x1)
-
-/**
- * Register: HW_HWECC_STAT
- * Address: 0x10
- * SCT: no
-*/
-#define HW_HWECC_STAT                   (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x10))
-#define BP_HWECC_STAT_RSDEC_PRESENT     31
-#define BM_HWECC_STAT_RSDEC_PRESENT     0x80000000
-#define BF_HWECC_STAT_RSDEC_PRESENT(v)  (((v) << 31) & 0x80000000)
-#define BP_HWECC_STAT_RSENC_PRESENT     30
-#define BM_HWECC_STAT_RSENC_PRESENT     0x40000000
-#define BF_HWECC_STAT_RSENC_PRESENT(v)  (((v) << 30) & 0x40000000)
-#define BP_HWECC_STAT_SSDEC_PRESENT     29
-#define BM_HWECC_STAT_SSDEC_PRESENT     0x20000000
-#define BF_HWECC_STAT_SSDEC_PRESENT(v)  (((v) << 29) & 0x20000000)
-#define BP_HWECC_STAT_SSENC_PRESENT     28
-#define BM_HWECC_STAT_SSENC_PRESENT     0x10000000
-#define BF_HWECC_STAT_SSENC_PRESENT(v)  (((v) << 28) & 0x10000000)
-
-/**
- * Register: HW_HWECC_DEBUG0
- * Address: 0x20
- * SCT: no
-*/
-#define HW_HWECC_DEBUG0                         (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x20))
-#define BP_HWECC_DEBUG0_DMA_PENDCMD             29
-#define BM_HWECC_DEBUG0_DMA_PENDCMD             0x20000000
-#define BF_HWECC_DEBUG0_DMA_PENDCMD(v)          (((v) << 29) & 0x20000000)
-#define BP_HWECC_DEBUG0_DMA_PREQ                28
-#define BM_HWECC_DEBUG0_DMA_PREQ                0x10000000
-#define BF_HWECC_DEBUG0_DMA_PREQ(v)             (((v) << 28) & 0x10000000)
-#define BP_HWECC_DEBUG0_SYMBOL_STATE            24
-#define BM_HWECC_DEBUG0_SYMBOL_STATE            0xf000000
-#define BF_HWECC_DEBUG0_SYMBOL_STATE(v)         (((v) << 24) & 0xf000000)
-#define BP_HWECC_DEBUG0_CTRL_STATE              16
-#define BM_HWECC_DEBUG0_CTRL_STATE              0x3f0000
-#define BF_HWECC_DEBUG0_CTRL_STATE(v)           (((v) << 16) & 0x3f0000)
-#define BP_HWECC_DEBUG0_ECC_EXCEPTION           12
-#define BM_HWECC_DEBUG0_ECC_EXCEPTION           0xf000
-#define BF_HWECC_DEBUG0_ECC_EXCEPTION(v)        (((v) << 12) & 0xf000)
-#define BP_HWECC_DEBUG0_NUM_BIT_ERRORS          4
-#define BM_HWECC_DEBUG0_NUM_BIT_ERRORS          0x3f0
-#define BF_HWECC_DEBUG0_NUM_BIT_ERRORS(v)       (((v) << 4) & 0x3f0)
-#define BP_HWECC_DEBUG0_NUM_SYMBOL_ERRORS       0
-#define BM_HWECC_DEBUG0_NUM_SYMBOL_ERRORS       0x7
-#define BF_HWECC_DEBUG0_NUM_SYMBOL_ERRORS(v)    (((v) << 0) & 0x7)
-
-/**
- * Register: HW_HWECC_DEBUG1
- * Address: 0x30
- * SCT: no
-*/
-#define HW_HWECC_DEBUG1                 (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x30))
-#define BP_HWECC_DEBUG1_SYNDROME2       18
-#define BM_HWECC_DEBUG1_SYNDROME2       0x7fc0000
-#define BF_HWECC_DEBUG1_SYNDROME2(v)    (((v) << 18) & 0x7fc0000)
-#define BP_HWECC_DEBUG1_SYNDROME1       9
-#define BM_HWECC_DEBUG1_SYNDROME1       0x3fe00
-#define BF_HWECC_DEBUG1_SYNDROME1(v)    (((v) << 9) & 0x3fe00)
-#define BP_HWECC_DEBUG1_SYNDROME0       0
-#define BM_HWECC_DEBUG1_SYNDROME0       0x1ff
-#define BF_HWECC_DEBUG1_SYNDROME0(v)    (((v) << 0) & 0x1ff)
-
-/**
- * Register: HW_HWECC_DEBUG2
- * Address: 0x40
- * SCT: no
-*/
-#define HW_HWECC_DEBUG2                 (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x40))
-#define BP_HWECC_DEBUG2_SYNDROME5       18
-#define BM_HWECC_DEBUG2_SYNDROME5       0x7fc0000
-#define BF_HWECC_DEBUG2_SYNDROME5(v)    (((v) << 18) & 0x7fc0000)
-#define BP_HWECC_DEBUG2_SYNDROME4       9
-#define BM_HWECC_DEBUG2_SYNDROME4       0x3fe00
-#define BF_HWECC_DEBUG2_SYNDROME4(v)    (((v) << 9) & 0x3fe00)
-#define BP_HWECC_DEBUG2_SYNDROME3       0
-#define BM_HWECC_DEBUG2_SYNDROME3       0x1ff
-#define BF_HWECC_DEBUG2_SYNDROME3(v)    (((v) << 0) & 0x1ff)
-
-/**
- * Register: HW_HWECC_DEBUG3
- * Address: 0x50
- * SCT: no
-*/
-#define HW_HWECC_DEBUG3                 (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x50))
-#define BP_HWECC_DEBUG3_OMEGA0          18
-#define BM_HWECC_DEBUG3_OMEGA0          0x7fc0000
-#define BF_HWECC_DEBUG3_OMEGA0(v)       (((v) << 18) & 0x7fc0000)
-#define BP_HWECC_DEBUG3_SYNDROME7       9
-#define BM_HWECC_DEBUG3_SYNDROME7       0x3fe00
-#define BF_HWECC_DEBUG3_SYNDROME7(v)    (((v) << 9) & 0x3fe00)
-#define BP_HWECC_DEBUG3_SYNDROME6       0
-#define BM_HWECC_DEBUG3_SYNDROME6       0x1ff
-#define BF_HWECC_DEBUG3_SYNDROME6(v)    (((v) << 0) & 0x1ff)
-
-/**
- * Register: HW_HWECC_DEBUG4
- * Address: 0x60
- * SCT: no
-*/
-#define HW_HWECC_DEBUG4             (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x60))
-#define BP_HWECC_DEBUG4_OMEGA3      18
-#define BM_HWECC_DEBUG4_OMEGA3      0x7fc0000
-#define BF_HWECC_DEBUG4_OMEGA3(v)   (((v) << 18) & 0x7fc0000)
-#define BP_HWECC_DEBUG4_OMEGA2      9
-#define BM_HWECC_DEBUG4_OMEGA2      0x3fe00
-#define BF_HWECC_DEBUG4_OMEGA2(v)   (((v) << 9) & 0x3fe00)
-#define BP_HWECC_DEBUG4_OMEGA1      0
-#define BM_HWECC_DEBUG4_OMEGA1      0x1ff
-#define BF_HWECC_DEBUG4_OMEGA1(v)   (((v) << 0) & 0x1ff)
-
-/**
- * Register: HW_HWECC_DEBUG5
- * Address: 0x70
- * SCT: no
-*/
-#define HW_HWECC_DEBUG5             (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x70))
-#define BP_HWECC_DEBUG5_LAMBDA2     18
-#define BM_HWECC_DEBUG5_LAMBDA2     0x7fc0000
-#define BF_HWECC_DEBUG5_LAMBDA2(v)  (((v) << 18) & 0x7fc0000)
-#define BP_HWECC_DEBUG5_LAMBDA1     9
-#define BM_HWECC_DEBUG5_LAMBDA1     0x3fe00
-#define BF_HWECC_DEBUG5_LAMBDA1(v)  (((v) << 9) & 0x3fe00)
-#define BP_HWECC_DEBUG5_LAMBDA0     0
-#define BM_HWECC_DEBUG5_LAMBDA0     0x1ff
-#define BF_HWECC_DEBUG5_LAMBDA0(v)  (((v) << 0) & 0x1ff)
-
-/**
- * Register: HW_HWECC_DEBUG6
- * Address: 0x80
- * SCT: no
-*/
-#define HW_HWECC_DEBUG6             (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x80))
-#define BP_HWECC_DEBUG6_LAMBDA4     9
-#define BM_HWECC_DEBUG6_LAMBDA4     0x3fe00
-#define BF_HWECC_DEBUG6_LAMBDA4(v)  (((v) << 9) & 0x3fe00)
-#define BP_HWECC_DEBUG6_LAMBDA3     0
-#define BM_HWECC_DEBUG6_LAMBDA3     0x1ff
-#define BF_HWECC_DEBUG6_LAMBDA3(v)  (((v) << 0) & 0x1ff)
-
-/**
- * Register: HW_HWECC_DATA
- * Address: 0x90
- * SCT: yes
-*/
-#define HW_HWECC_DATA           (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x90 + 0x0))
-#define HW_HWECC_DATA_SET       (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x90 + 0x4))
-#define HW_HWECC_DATA_CLR       (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x90 + 0x8))
-#define HW_HWECC_DATA_TOG       (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x90 + 0xc))
-#define BP_HWECC_DATA_DATA      0
-#define BM_HWECC_DATA_DATA      0xffffffff
-#define BF_HWECC_DATA_DATA(v)   (((v) << 0) & 0xffffffff)
-
-#endif /* __HEADERGEN__STMP3600__HWECC__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-i2c.h b/firmware/target/arm/imx233/regs/stmp3600/regs-i2c.h
deleted file mode 100644
index 2c5cf0e5a7..0000000000
--- a/firmware/target/arm/imx233/regs/stmp3600/regs-i2c.h
+++ /dev/null
@@ -1,521 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3600:2.3.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__STMP3600__I2C__H__
-#define __HEADERGEN__STMP3600__I2C__H__
-
-#define REGS_I2C_BASE (0x80058000)
-
-#define REGS_I2C_VERSION "2.3.0"
-
-/**
- * Register: HW_I2C_CTRL0
- * Address: 0
- * SCT: yes
-*/
-#define HW_I2C_CTRL0                                (*(volatile unsigned long *)(REGS_I2C_BASE + 0x0 + 0x0))
-#define HW_I2C_CTRL0_SET                            (*(volatile unsigned long *)(REGS_I2C_BASE + 0x0 + 0x4))
-#define HW_I2C_CTRL0_CLR                            (*(volatile unsigned long *)(REGS_I2C_BASE + 0x0 + 0x8))
-#define HW_I2C_CTRL0_TOG                            (*(volatile unsigned long *)(REGS_I2C_BASE + 0x0 + 0xc))
-#define BP_I2C_CTRL0_SFTRST                         31
-#define BM_I2C_CTRL0_SFTRST                         0x80000000
-#define BV_I2C_CTRL0_SFTRST__RUN                    0x0
-#define BV_I2C_CTRL0_SFTRST__RESET                  0x1
-#define BF_I2C_CTRL0_SFTRST(v)                      (((v) << 31) & 0x80000000)
-#define BF_I2C_CTRL0_SFTRST_V(v)                    ((BV_I2C_CTRL0_SFTRST__##v << 31) & 0x80000000)
-#define BP_I2C_CTRL0_CLKGATE                        30
-#define BM_I2C_CTRL0_CLKGATE                        0x40000000
-#define BV_I2C_CTRL0_CLKGATE__RUN                   0x0
-#define BV_I2C_CTRL0_CLKGATE__NO_CLKS               0x1
-#define BF_I2C_CTRL0_CLKGATE(v)                     (((v) << 30) & 0x40000000)
-#define BF_I2C_CTRL0_CLKGATE_V(v)                   ((BV_I2C_CTRL0_CLKGATE__##v << 30) & 0x40000000)
-#define BP_I2C_CTRL0_RUN                            29
-#define BM_I2C_CTRL0_RUN                            0x20000000
-#define BV_I2C_CTRL0_RUN__HALT                      0x0
-#define BV_I2C_CTRL0_RUN__RUN                       0x1
-#define BF_I2C_CTRL0_RUN(v)                         (((v) << 29) & 0x20000000)
-#define BF_I2C_CTRL0_RUN_V(v)                       ((BV_I2C_CTRL0_RUN__##v << 29) & 0x20000000)
-#define BP_I2C_CTRL0_PRE_ACK                        27
-#define BM_I2C_CTRL0_PRE_ACK                        0x8000000
-#define BF_I2C_CTRL0_PRE_ACK(v)                     (((v) << 27) & 0x8000000)
-#define BP_I2C_CTRL0_ACKNOWLEDGE                    26
-#define BM_I2C_CTRL0_ACKNOWLEDGE                    0x4000000
-#define BV_I2C_CTRL0_ACKNOWLEDGE__SNAK              0x0
-#define BV_I2C_CTRL0_ACKNOWLEDGE__ACK               0x1
-#define BF_I2C_CTRL0_ACKNOWLEDGE(v)                 (((v) << 26) & 0x4000000)
-#define BF_I2C_CTRL0_ACKNOWLEDGE_V(v)               ((BV_I2C_CTRL0_ACKNOWLEDGE__##v << 26) & 0x4000000)
-#define BP_I2C_CTRL0_SEND_NAK_ON_LAST               25
-#define BM_I2C_CTRL0_SEND_NAK_ON_LAST               0x2000000
-#define BV_I2C_CTRL0_SEND_NAK_ON_LAST__ACK_IT       0x0
-#define BV_I2C_CTRL0_SEND_NAK_ON_LAST__NAK_IT       0x1
-#define BF_I2C_CTRL0_SEND_NAK_ON_LAST(v)            (((v) << 25) & 0x2000000)
-#define BF_I2C_CTRL0_SEND_NAK_ON_LAST_V(v)          ((BV_I2C_CTRL0_SEND_NAK_ON_LAST__##v << 25) & 0x2000000)
-#define BP_I2C_CTRL0_PIO_MODE                       24
-#define BM_I2C_CTRL0_PIO_MODE                       0x1000000
-#define BF_I2C_CTRL0_PIO_MODE(v)                    (((v) << 24) & 0x1000000)
-#define BP_I2C_CTRL0_MULTI_MASTER                   23
-#define BM_I2C_CTRL0_MULTI_MASTER                   0x800000
-#define BV_I2C_CTRL0_MULTI_MASTER__SINGLE           0x0
-#define BV_I2C_CTRL0_MULTI_MASTER__MULTIPLE         0x1
-#define BF_I2C_CTRL0_MULTI_MASTER(v)                (((v) << 23) & 0x800000)
-#define BF_I2C_CTRL0_MULTI_MASTER_V(v)              ((BV_I2C_CTRL0_MULTI_MASTER__##v << 23) & 0x800000)
-#define BP_I2C_CTRL0_CLOCK_HELD                     22
-#define BM_I2C_CTRL0_CLOCK_HELD                     0x400000
-#define BV_I2C_CTRL0_CLOCK_HELD__RELEASE            0x0
-#define BV_I2C_CTRL0_CLOCK_HELD__HELD_LOW           0x1
-#define BF_I2C_CTRL0_CLOCK_HELD(v)                  (((v) << 22) & 0x400000)
-#define BF_I2C_CTRL0_CLOCK_HELD_V(v)                ((BV_I2C_CTRL0_CLOCK_HELD__##v << 22) & 0x400000)
-#define BP_I2C_CTRL0_RETAIN_CLOCK                   21
-#define BM_I2C_CTRL0_RETAIN_CLOCK                   0x200000
-#define BV_I2C_CTRL0_RETAIN_CLOCK__RELEASE          0x0
-#define BV_I2C_CTRL0_RETAIN_CLOCK__HOLD_LOW         0x1
-#define BF_I2C_CTRL0_RETAIN_CLOCK(v)                (((v) << 21) & 0x200000)
-#define BF_I2C_CTRL0_RETAIN_CLOCK_V(v)              ((BV_I2C_CTRL0_RETAIN_CLOCK__##v << 21) & 0x200000)
-#define BP_I2C_CTRL0_POST_SEND_STOP                 20
-#define BM_I2C_CTRL0_POST_SEND_STOP                 0x100000
-#define BV_I2C_CTRL0_POST_SEND_STOP__NO_STOP        0x0
-#define BV_I2C_CTRL0_POST_SEND_STOP__SEND_STOP      0x1
-#define BF_I2C_CTRL0_POST_SEND_STOP(v)              (((v) << 20) & 0x100000)
-#define BF_I2C_CTRL0_POST_SEND_STOP_V(v)            ((BV_I2C_CTRL0_POST_SEND_STOP__##v << 20) & 0x100000)
-#define BP_I2C_CTRL0_PRE_SEND_START                 19
-#define BM_I2C_CTRL0_PRE_SEND_START                 0x80000
-#define BV_I2C_CTRL0_PRE_SEND_START__NO_START       0x0
-#define BV_I2C_CTRL0_PRE_SEND_START__SEND_START     0x1
-#define BF_I2C_CTRL0_PRE_SEND_START(v)              (((v) << 19) & 0x80000)
-#define BF_I2C_CTRL0_PRE_SEND_START_V(v)            ((BV_I2C_CTRL0_PRE_SEND_START__##v << 19) & 0x80000)
-#define BP_I2C_CTRL0_SLAVE_ADDRESS_ENABLE           18
-#define BM_I2C_CTRL0_SLAVE_ADDRESS_ENABLE           0x40000
-#define BV_I2C_CTRL0_SLAVE_ADDRESS_ENABLE__DISABLED 0x0
-#define BV_I2C_CTRL0_SLAVE_ADDRESS_ENABLE__ENABLED  0x1
-#define BF_I2C_CTRL0_SLAVE_ADDRESS_ENABLE(v)        (((v) << 18) & 0x40000)
-#define BF_I2C_CTRL0_SLAVE_ADDRESS_ENABLE_V(v)      ((BV_I2C_CTRL0_SLAVE_ADDRESS_ENABLE__##v << 18) & 0x40000)
-#define BP_I2C_CTRL0_MASTER_MODE                    17
-#define BM_I2C_CTRL0_MASTER_MODE                    0x20000
-#define BV_I2C_CTRL0_MASTER_MODE__SLAVE             0x0
-#define BV_I2C_CTRL0_MASTER_MODE__MASTER            0x1
-#define BF_I2C_CTRL0_MASTER_MODE(v)                 (((v) << 17) & 0x20000)
-#define BF_I2C_CTRL0_MASTER_MODE_V(v)               ((BV_I2C_CTRL0_MASTER_MODE__##v << 17) & 0x20000)
-#define BP_I2C_CTRL0_DIRECTION                      16
-#define BM_I2C_CTRL0_DIRECTION                      0x10000
-#define BV_I2C_CTRL0_DIRECTION__RECEIVE             0x0
-#define BV_I2C_CTRL0_DIRECTION__TRANSMIT            0x1
-#define BF_I2C_CTRL0_DIRECTION(v)                   (((v) << 16) & 0x10000)
-#define BF_I2C_CTRL0_DIRECTION_V(v)                 ((BV_I2C_CTRL0_DIRECTION__##v << 16) & 0x10000)
-#define BP_I2C_CTRL0_XFER_COUNT                     0
-#define BM_I2C_CTRL0_XFER_COUNT                     0xffff
-#define BF_I2C_CTRL0_XFER_COUNT(v)                  (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_I2C_TIMING0
- * Address: 0x10
- * SCT: yes
-*/
-#define HW_I2C_TIMING0                  (*(volatile unsigned long *)(REGS_I2C_BASE + 0x10 + 0x0))
-#define HW_I2C_TIMING0_SET              (*(volatile unsigned long *)(REGS_I2C_BASE + 0x10 + 0x4))
-#define HW_I2C_TIMING0_CLR              (*(volatile unsigned long *)(REGS_I2C_BASE + 0x10 + 0x8))
-#define HW_I2C_TIMING0_TOG              (*(volatile unsigned long *)(REGS_I2C_BASE + 0x10 + 0xc))
-#define BP_I2C_TIMING0_HIGH_COUNT       16
-#define BM_I2C_TIMING0_HIGH_COUNT       0x3ff0000
-#define BF_I2C_TIMING0_HIGH_COUNT(v)    (((v) << 16) & 0x3ff0000)
-#define BP_I2C_TIMING0_RCV_COUNT        0
-#define BM_I2C_TIMING0_RCV_COUNT        0x3ff
-#define BF_I2C_TIMING0_RCV_COUNT(v)     (((v) << 0) & 0x3ff)
-
-/**
- * Register: HW_I2C_TIMING1
- * Address: 0x20
- * SCT: yes
-*/
-#define HW_I2C_TIMING1                  (*(volatile unsigned long *)(REGS_I2C_BASE + 0x20 + 0x0))
-#define HW_I2C_TIMING1_SET              (*(volatile unsigned long *)(REGS_I2C_BASE + 0x20 + 0x4))
-#define HW_I2C_TIMING1_CLR              (*(volatile unsigned long *)(REGS_I2C_BASE + 0x20 + 0x8))
-#define HW_I2C_TIMING1_TOG              (*(volatile unsigned long *)(REGS_I2C_BASE + 0x20 + 0xc))
-#define BP_I2C_TIMING1_LOW_COUNT        16
-#define BM_I2C_TIMING1_LOW_COUNT        0x3ff0000
-#define BF_I2C_TIMING1_LOW_COUNT(v)     (((v) << 16) & 0x3ff0000)
-#define BP_I2C_TIMING1_XMIT_COUNT       0
-#define BM_I2C_TIMING1_XMIT_COUNT       0x3ff
-#define BF_I2C_TIMING1_XMIT_COUNT(v)    (((v) << 0) & 0x3ff)
-
-/**
- * Register: HW_I2C_TIMING2
- * Address: 0x30
- * SCT: yes
-*/
-#define HW_I2C_TIMING2                  (*(volatile unsigned long *)(REGS_I2C_BASE + 0x30 + 0x0))
-#define HW_I2C_TIMING2_SET              (*(volatile unsigned long *)(REGS_I2C_BASE + 0x30 + 0x4))
-#define HW_I2C_TIMING2_CLR              (*(volatile unsigned long *)(REGS_I2C_BASE + 0x30 + 0x8))
-#define HW_I2C_TIMING2_TOG              (*(volatile unsigned long *)(REGS_I2C_BASE + 0x30 + 0xc))
-#define BP_I2C_TIMING2_BUS_FREE         16
-#define BM_I2C_TIMING2_BUS_FREE         0x3ff0000
-#define BF_I2C_TIMING2_BUS_FREE(v)      (((v) << 16) & 0x3ff0000)
-#define BP_I2C_TIMING2_LEADIN_COUNT     0
-#define BM_I2C_TIMING2_LEADIN_COUNT     0x3ff
-#define BF_I2C_TIMING2_LEADIN_COUNT(v)  (((v) << 0) & 0x3ff)
-
-/**
- * Register: HW_I2C_CTRL1
- * Address: 0x40
- * SCT: yes
-*/
-#define HW_I2C_CTRL1                                        (*(volatile unsigned long *)(REGS_I2C_BASE + 0x40 + 0x0))
-#define HW_I2C_CTRL1_SET                                    (*(volatile unsigned long *)(REGS_I2C_BASE + 0x40 + 0x4))
-#define HW_I2C_CTRL1_CLR                                    (*(volatile unsigned long *)(REGS_I2C_BASE + 0x40 + 0x8))
-#define HW_I2C_CTRL1_TOG                                    (*(volatile unsigned long *)(REGS_I2C_BASE + 0x40 + 0xc))
-#define BP_I2C_CTRL1_BCAST_SLAVE_EN                         24
-#define BM_I2C_CTRL1_BCAST_SLAVE_EN                         0x1000000
-#define BV_I2C_CTRL1_BCAST_SLAVE_EN__NO_BCAST               0x0
-#define BV_I2C_CTRL1_BCAST_SLAVE_EN__WATCH_BCAST            0x1
-#define BF_I2C_CTRL1_BCAST_SLAVE_EN(v)                      (((v) << 24) & 0x1000000)
-#define BF_I2C_CTRL1_BCAST_SLAVE_EN_V(v)                    ((BV_I2C_CTRL1_BCAST_SLAVE_EN__##v << 24) & 0x1000000)
-#define BP_I2C_CTRL1_SLAVE_ADDRESS_BYTE                     16
-#define BM_I2C_CTRL1_SLAVE_ADDRESS_BYTE                     0xff0000
-#define BF_I2C_CTRL1_SLAVE_ADDRESS_BYTE(v)                  (((v) << 16) & 0xff0000)
-#define BP_I2C_CTRL1_BUS_FREE_IRQ_EN                        15
-#define BM_I2C_CTRL1_BUS_FREE_IRQ_EN                        0x8000
-#define BV_I2C_CTRL1_BUS_FREE_IRQ_EN__DISABLED              0x0
-#define BV_I2C_CTRL1_BUS_FREE_IRQ_EN__ENABLED               0x1
-#define BF_I2C_CTRL1_BUS_FREE_IRQ_EN(v)                     (((v) << 15) & 0x8000)
-#define BF_I2C_CTRL1_BUS_FREE_IRQ_EN_V(v)                   ((BV_I2C_CTRL1_BUS_FREE_IRQ_EN__##v << 15) & 0x8000)
-#define BP_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN               14
-#define BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN               0x4000
-#define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN__DISABLED     0x0
-#define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN__ENABLED      0x1
-#define BF_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN(v)            (((v) << 14) & 0x4000)
-#define BF_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN_V(v)          ((BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN__##v << 14) & 0x4000)
-#define BP_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN                    13
-#define BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN                    0x2000
-#define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN__DISABLED          0x0
-#define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN__ENABLED           0x1
-#define BF_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN(v)                 (((v) << 13) & 0x2000)
-#define BF_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN_V(v)               ((BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN__##v << 13) & 0x2000)
-#define BP_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN              12
-#define BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN              0x1000
-#define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN__DISABLED    0x0
-#define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN__ENABLED     0x1
-#define BF_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN(v)           (((v) << 12) & 0x1000)
-#define BF_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN_V(v)         ((BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN__##v << 12) & 0x1000)
-#define BP_I2C_CTRL1_EARLY_TERM_IRQ_EN                      11
-#define BM_I2C_CTRL1_EARLY_TERM_IRQ_EN                      0x800
-#define BV_I2C_CTRL1_EARLY_TERM_IRQ_EN__DISABLED            0x0
-#define BV_I2C_CTRL1_EARLY_TERM_IRQ_EN__ENABLED             0x1
-#define BF_I2C_CTRL1_EARLY_TERM_IRQ_EN(v)                   (((v) << 11) & 0x800)
-#define BF_I2C_CTRL1_EARLY_TERM_IRQ_EN_V(v)                 ((BV_I2C_CTRL1_EARLY_TERM_IRQ_EN__##v << 11) & 0x800)
-#define BP_I2C_CTRL1_MASTER_LOSS_IRQ_EN                     10
-#define BM_I2C_CTRL1_MASTER_LOSS_IRQ_EN                     0x400
-#define BV_I2C_CTRL1_MASTER_LOSS_IRQ_EN__DISABLED           0x0
-#define BV_I2C_CTRL1_MASTER_LOSS_IRQ_EN__ENABLED            0x1
-#define BF_I2C_CTRL1_MASTER_LOSS_IRQ_EN(v)                  (((v) << 10) & 0x400)
-#define BF_I2C_CTRL1_MASTER_LOSS_IRQ_EN_V(v)                ((BV_I2C_CTRL1_MASTER_LOSS_IRQ_EN__##v << 10) & 0x400)
-#define BP_I2C_CTRL1_SLAVE_STOP_IRQ_EN                      9
-#define BM_I2C_CTRL1_SLAVE_STOP_IRQ_EN                      0x200
-#define BV_I2C_CTRL1_SLAVE_STOP_IRQ_EN__DISABLED            0x0
-#define BV_I2C_CTRL1_SLAVE_STOP_IRQ_EN__ENABLED             0x1
-#define BF_I2C_CTRL1_SLAVE_STOP_IRQ_EN(v)                   (((v) << 9) & 0x200)
-#define BF_I2C_CTRL1_SLAVE_STOP_IRQ_EN_V(v)                 ((BV_I2C_CTRL1_SLAVE_STOP_IRQ_EN__##v << 9) & 0x200)
-#define BP_I2C_CTRL1_SLAVE_IRQ_EN                           8
-#define BM_I2C_CTRL1_SLAVE_IRQ_EN                           0x100
-#define BV_I2C_CTRL1_SLAVE_IRQ_EN__DISABLED                 0x0
-#define BV_I2C_CTRL1_SLAVE_IRQ_EN__ENABLED                  0x1
-#define BF_I2C_CTRL1_SLAVE_IRQ_EN(v)                        (((v) << 8) & 0x100)
-#define BF_I2C_CTRL1_SLAVE_IRQ_EN_V(v)                      ((BV_I2C_CTRL1_SLAVE_IRQ_EN__##v << 8) & 0x100)
-#define BP_I2C_CTRL1_BUS_FREE_IRQ                           7
-#define BM_I2C_CTRL1_BUS_FREE_IRQ                           0x80
-#define BV_I2C_CTRL1_BUS_FREE_IRQ__NO_REQUEST               0x0
-#define BV_I2C_CTRL1_BUS_FREE_IRQ__REQUEST                  0x1
-#define BF_I2C_CTRL1_BUS_FREE_IRQ(v)                        (((v) << 7) & 0x80)
-#define BF_I2C_CTRL1_BUS_FREE_IRQ_V(v)                      ((BV_I2C_CTRL1_BUS_FREE_IRQ__##v << 7) & 0x80)
-#define BP_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ                  6
-#define BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ                  0x40
-#define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ__NO_REQUEST      0x0
-#define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ__REQUEST         0x1
-#define BF_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ(v)               (((v) << 6) & 0x40)
-#define BF_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_V(v)             ((BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ__##v << 6) & 0x40)
-#define BP_I2C_CTRL1_NO_SLAVE_ACK_IRQ                       5
-#define BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ                       0x20
-#define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ__NO_REQUEST           0x0
-#define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ__REQUEST              0x1
-#define BF_I2C_CTRL1_NO_SLAVE_ACK_IRQ(v)                    (((v) << 5) & 0x20)
-#define BF_I2C_CTRL1_NO_SLAVE_ACK_IRQ_V(v)                  ((BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ__##v << 5) & 0x20)
-#define BP_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ                 4
-#define BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ                 0x10
-#define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ__NO_REQUEST     0x0
-#define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ__REQUEST        0x1
-#define BF_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ(v)              (((v) << 4) & 0x10)
-#define BF_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_V(v)            ((BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ__##v << 4) & 0x10)
-#define BP_I2C_CTRL1_EARLY_TERM_IRQ                         3
-#define BM_I2C_CTRL1_EARLY_TERM_IRQ                         0x8
-#define BV_I2C_CTRL1_EARLY_TERM_IRQ__NO_REQUEST             0x0
-#define BV_I2C_CTRL1_EARLY_TERM_IRQ__REQUEST                0x1
-#define BF_I2C_CTRL1_EARLY_TERM_IRQ(v)                      (((v) << 3) & 0x8)
-#define BF_I2C_CTRL1_EARLY_TERM_IRQ_V(v)                    ((BV_I2C_CTRL1_EARLY_TERM_IRQ__##v << 3) & 0x8)
-#define BP_I2C_CTRL1_MASTER_LOSS_IRQ                        2
-#define BM_I2C_CTRL1_MASTER_LOSS_IRQ                        0x4
-#define BV_I2C_CTRL1_MASTER_LOSS_IRQ__NO_REQUEST            0x0
-#define BV_I2C_CTRL1_MASTER_LOSS_IRQ__REQUEST               0x1
-#define BF_I2C_CTRL1_MASTER_LOSS_IRQ(v)                     (((v) << 2) & 0x4)
-#define BF_I2C_CTRL1_MASTER_LOSS_IRQ_V(v)                   ((BV_I2C_CTRL1_MASTER_LOSS_IRQ__##v << 2) & 0x4)
-#define BP_I2C_CTRL1_SLAVE_STOP_IRQ                         1
-#define BM_I2C_CTRL1_SLAVE_STOP_IRQ                         0x2
-#define BV_I2C_CTRL1_SLAVE_STOP_IRQ__NO_REQUEST             0x0
-#define BV_I2C_CTRL1_SLAVE_STOP_IRQ__REQUEST                0x1
-#define BF_I2C_CTRL1_SLAVE_STOP_IRQ(v)                      (((v) << 1) & 0x2)
-#define BF_I2C_CTRL1_SLAVE_STOP_IRQ_V(v)                    ((BV_I2C_CTRL1_SLAVE_STOP_IRQ__##v << 1) & 0x2)
-#define BP_I2C_CTRL1_SLAVE_IRQ                              0
-#define BM_I2C_CTRL1_SLAVE_IRQ                              0x1
-#define BV_I2C_CTRL1_SLAVE_IRQ__NO_REQUEST                  0x0
-#define BV_I2C_CTRL1_SLAVE_IRQ__REQUEST                     0x1
-#define BF_I2C_CTRL1_SLAVE_IRQ(v)                           (((v) << 0) & 0x1)
-#define BF_I2C_CTRL1_SLAVE_IRQ_V(v)                         ((BV_I2C_CTRL1_SLAVE_IRQ__##v << 0) & 0x1)
-
-/**
- * Register: HW_I2C_STAT
- * Address: 0x50
- * SCT: no
-*/
-#define HW_I2C_STAT                                             (*(volatile unsigned long *)(REGS_I2C_BASE + 0x50))
-#define BP_I2C_STAT_MASTER_PRESENT                              31
-#define BM_I2C_STAT_MASTER_PRESENT                              0x80000000
-#define BV_I2C_STAT_MASTER_PRESENT__UNAVAILABLE                 0x0
-#define BV_I2C_STAT_MASTER_PRESENT__AVAILABLE                   0x1
-#define BF_I2C_STAT_MASTER_PRESENT(v)                           (((v) << 31) & 0x80000000)
-#define BF_I2C_STAT_MASTER_PRESENT_V(v)                         ((BV_I2C_STAT_MASTER_PRESENT__##v << 31) & 0x80000000)
-#define BP_I2C_STAT_SLAVE_PRESENT                               30
-#define BM_I2C_STAT_SLAVE_PRESENT                               0x40000000
-#define BV_I2C_STAT_SLAVE_PRESENT__UNAVAILABLE                  0x0
-#define BV_I2C_STAT_SLAVE_PRESENT__AVAILABLE                    0x1
-#define BF_I2C_STAT_SLAVE_PRESENT(v)                            (((v) << 30) & 0x40000000)
-#define BF_I2C_STAT_SLAVE_PRESENT_V(v)                          ((BV_I2C_STAT_SLAVE_PRESENT__##v << 30) & 0x40000000)
-#define BP_I2C_STAT_ANY_ENABLED_IRQ                             29
-#define BM_I2C_STAT_ANY_ENABLED_IRQ                             0x20000000
-#define BV_I2C_STAT_ANY_ENABLED_IRQ__NO_REQUESTS                0x0
-#define BV_I2C_STAT_ANY_ENABLED_IRQ__AT_LEAST_ONE_REQUEST       0x1
-#define BF_I2C_STAT_ANY_ENABLED_IRQ(v)                          (((v) << 29) & 0x20000000)
-#define BF_I2C_STAT_ANY_ENABLED_IRQ_V(v)                        ((BV_I2C_STAT_ANY_ENABLED_IRQ__##v << 29) & 0x20000000)
-#define BP_I2C_STAT_RCVD_SLAVE_ADDR                             16
-#define BM_I2C_STAT_RCVD_SLAVE_ADDR                             0xff0000
-#define BF_I2C_STAT_RCVD_SLAVE_ADDR(v)                          (((v) << 16) & 0xff0000)
-#define BP_I2C_STAT_SLAVE_ADDR_EQ_ZERO                          15
-#define BM_I2C_STAT_SLAVE_ADDR_EQ_ZERO                          0x8000
-#define BV_I2C_STAT_SLAVE_ADDR_EQ_ZERO__ZERO_NOT_MATCHED        0x0
-#define BV_I2C_STAT_SLAVE_ADDR_EQ_ZERO__WAS_ZERO                0x1
-#define BF_I2C_STAT_SLAVE_ADDR_EQ_ZERO(v)                       (((v) << 15) & 0x8000)
-#define BF_I2C_STAT_SLAVE_ADDR_EQ_ZERO_V(v)                     ((BV_I2C_STAT_SLAVE_ADDR_EQ_ZERO__##v << 15) & 0x8000)
-#define BP_I2C_STAT_SLAVE_FOUND                                 14
-#define BM_I2C_STAT_SLAVE_FOUND                                 0x4000
-#define BV_I2C_STAT_SLAVE_FOUND__IDLE                           0x0
-#define BV_I2C_STAT_SLAVE_FOUND__WAITING                        0x1
-#define BF_I2C_STAT_SLAVE_FOUND(v)                              (((v) << 14) & 0x4000)
-#define BF_I2C_STAT_SLAVE_FOUND_V(v)                            ((BV_I2C_STAT_SLAVE_FOUND__##v << 14) & 0x4000)
-#define BP_I2C_STAT_SLAVE_SEARCHING                             13
-#define BM_I2C_STAT_SLAVE_SEARCHING                             0x2000
-#define BV_I2C_STAT_SLAVE_SEARCHING__IDLE                       0x0
-#define BV_I2C_STAT_SLAVE_SEARCHING__ACTIVE                     0x1
-#define BF_I2C_STAT_SLAVE_SEARCHING(v)                          (((v) << 13) & 0x2000)
-#define BF_I2C_STAT_SLAVE_SEARCHING_V(v)                        ((BV_I2C_STAT_SLAVE_SEARCHING__##v << 13) & 0x2000)
-#define BP_I2C_STAT_DATA_ENGINE_DMA_WAIT                        12
-#define BM_I2C_STAT_DATA_ENGINE_DMA_WAIT                        0x1000
-#define BV_I2C_STAT_DATA_ENGINE_DMA_WAIT__CONTINUE              0x0
-#define BV_I2C_STAT_DATA_ENGINE_DMA_WAIT__WAITING               0x1
-#define BF_I2C_STAT_DATA_ENGINE_DMA_WAIT(v)                     (((v) << 12) & 0x1000)
-#define BF_I2C_STAT_DATA_ENGINE_DMA_WAIT_V(v)                   ((BV_I2C_STAT_DATA_ENGINE_DMA_WAIT__##v << 12) & 0x1000)
-#define BP_I2C_STAT_BUS_BUSY                                    11
-#define BM_I2C_STAT_BUS_BUSY                                    0x800
-#define BV_I2C_STAT_BUS_BUSY__IDLE                              0x0
-#define BV_I2C_STAT_BUS_BUSY__BUSY                              0x1
-#define BF_I2C_STAT_BUS_BUSY(v)                                 (((v) << 11) & 0x800)
-#define BF_I2C_STAT_BUS_BUSY_V(v)                               ((BV_I2C_STAT_BUS_BUSY__##v << 11) & 0x800)
-#define BP_I2C_STAT_CLK_GEN_BUSY                                10
-#define BM_I2C_STAT_CLK_GEN_BUSY                                0x400
-#define BV_I2C_STAT_CLK_GEN_BUSY__IDLE                          0x0
-#define BV_I2C_STAT_CLK_GEN_BUSY__BUSY                          0x1
-#define BF_I2C_STAT_CLK_GEN_BUSY(v)                             (((v) << 10) & 0x400)
-#define BF_I2C_STAT_CLK_GEN_BUSY_V(v)                           ((BV_I2C_STAT_CLK_GEN_BUSY__##v << 10) & 0x400)
-#define BP_I2C_STAT_DATA_ENGINE_BUSY                            9
-#define BM_I2C_STAT_DATA_ENGINE_BUSY                            0x200
-#define BV_I2C_STAT_DATA_ENGINE_BUSY__IDLE                      0x0
-#define BV_I2C_STAT_DATA_ENGINE_BUSY__BUSY                      0x1
-#define BF_I2C_STAT_DATA_ENGINE_BUSY(v)                         (((v) << 9) & 0x200)
-#define BF_I2C_STAT_DATA_ENGINE_BUSY_V(v)                       ((BV_I2C_STAT_DATA_ENGINE_BUSY__##v << 9) & 0x200)
-#define BP_I2C_STAT_SLAVE_BUSY                                  8
-#define BM_I2C_STAT_SLAVE_BUSY                                  0x100
-#define BV_I2C_STAT_SLAVE_BUSY__IDLE                            0x0
-#define BV_I2C_STAT_SLAVE_BUSY__BUSY                            0x1
-#define BF_I2C_STAT_SLAVE_BUSY(v)                               (((v) << 8) & 0x100)
-#define BF_I2C_STAT_SLAVE_BUSY_V(v)                             ((BV_I2C_STAT_SLAVE_BUSY__##v << 8) & 0x100)
-#define BP_I2C_STAT_BUS_FREE_IRQ_SUMMARY                        7
-#define BM_I2C_STAT_BUS_FREE_IRQ_SUMMARY                        0x80
-#define BV_I2C_STAT_BUS_FREE_IRQ_SUMMARY__NO_REQUEST            0x0
-#define BV_I2C_STAT_BUS_FREE_IRQ_SUMMARY__REQUEST               0x1
-#define BF_I2C_STAT_BUS_FREE_IRQ_SUMMARY(v)                     (((v) << 7) & 0x80)
-#define BF_I2C_STAT_BUS_FREE_IRQ_SUMMARY_V(v)                   ((BV_I2C_STAT_BUS_FREE_IRQ_SUMMARY__##v << 7) & 0x80)
-#define BP_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY               6
-#define BM_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY               0x40
-#define BV_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY__NO_REQUEST   0x0
-#define BV_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY__REQUEST      0x1
-#define BF_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY(v)            (((v) << 6) & 0x40)
-#define BF_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY_V(v)          ((BV_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY__##v << 6) & 0x40)
-#define BP_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY                    5
-#define BM_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY                    0x20
-#define BV_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY__NO_REQUEST        0x0
-#define BV_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY__REQUEST           0x1
-#define BF_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY(v)                 (((v) << 5) & 0x20)
-#define BF_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY_V(v)               ((BV_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY__##v << 5) & 0x20)
-#define BP_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY              4
-#define BM_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY              0x10
-#define BV_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY__NO_REQUEST  0x0
-#define BV_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY__REQUEST     0x1
-#define BF_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY(v)           (((v) << 4) & 0x10)
-#define BF_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY_V(v)         ((BV_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY__##v << 4) & 0x10)
-#define BP_I2C_STAT_EARLY_TERM_IRQ_SUMMARY                      3
-#define BM_I2C_STAT_EARLY_TERM_IRQ_SUMMARY                      0x8
-#define BV_I2C_STAT_EARLY_TERM_IRQ_SUMMARY__NO_REQUEST          0x0
-#define BV_I2C_STAT_EARLY_TERM_IRQ_SUMMARY__REQUEST             0x1
-#define BF_I2C_STAT_EARLY_TERM_IRQ_SUMMARY(v)                   (((v) << 3) & 0x8)
-#define BF_I2C_STAT_EARLY_TERM_IRQ_SUMMARY_V(v)                 ((BV_I2C_STAT_EARLY_TERM_IRQ_SUMMARY__##v << 3) & 0x8)
-#define BP_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY                     2
-#define BM_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY                     0x4
-#define BV_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY__NO_REQUEST         0x0
-#define BV_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY__REQUEST            0x1
-#define BF_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY(v)                  (((v) << 2) & 0x4)
-#define BF_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY_V(v)                ((BV_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY__##v << 2) & 0x4)
-#define BP_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY                      1
-#define BM_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY                      0x2
-#define BV_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY__NO_REQUEST          0x0
-#define BV_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY__REQUEST             0x1
-#define BF_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY(v)                   (((v) << 1) & 0x2)
-#define BF_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY_V(v)                 ((BV_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY__##v << 1) & 0x2)
-#define BP_I2C_STAT_SLAVE_IRQ_SUMMARY                           0
-#define BM_I2C_STAT_SLAVE_IRQ_SUMMARY                           0x1
-#define BV_I2C_STAT_SLAVE_IRQ_SUMMARY__NO_REQUEST               0x0
-#define BV_I2C_STAT_SLAVE_IRQ_SUMMARY__REQUEST                  0x1
-#define BF_I2C_STAT_SLAVE_IRQ_SUMMARY(v)                        (((v) << 0) & 0x1)
-#define BF_I2C_STAT_SLAVE_IRQ_SUMMARY_V(v)                      ((BV_I2C_STAT_SLAVE_IRQ_SUMMARY__##v << 0) & 0x1)
-
-/**
- * Register: HW_I2C_DATA
- * Address: 0x60
- * SCT: no
-*/
-#define HW_I2C_DATA         (*(volatile unsigned long *)(REGS_I2C_BASE + 0x60))
-#define BP_I2C_DATA_DATA    0
-#define BM_I2C_DATA_DATA    0xffffffff
-#define BF_I2C_DATA_DATA(v) (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_I2C_DEBUG0
- * Address: 0x70
- * SCT: yes
-*/
-#define HW_I2C_DEBUG0                   (*(volatile unsigned long *)(REGS_I2C_BASE + 0x70 + 0x0))
-#define HW_I2C_DEBUG0_SET               (*(volatile unsigned long *)(REGS_I2C_BASE + 0x70 + 0x4))
-#define HW_I2C_DEBUG0_CLR               (*(volatile unsigned long *)(REGS_I2C_BASE + 0x70 + 0x8))
-#define HW_I2C_DEBUG0_TOG               (*(volatile unsigned long *)(REGS_I2C_BASE + 0x70 + 0xc))
-#define BP_I2C_DEBUG0_DMAREQ            31
-#define BM_I2C_DEBUG0_DMAREQ            0x80000000
-#define BF_I2C_DEBUG0_DMAREQ(v)         (((v) << 31) & 0x80000000)
-#define BP_I2C_DEBUG0_DMAENDCMD         30
-#define BM_I2C_DEBUG0_DMAENDCMD         0x40000000
-#define BF_I2C_DEBUG0_DMAENDCMD(v)      (((v) << 30) & 0x40000000)
-#define BP_I2C_DEBUG0_DMAKICK           29
-#define BM_I2C_DEBUG0_DMAKICK           0x20000000
-#define BF_I2C_DEBUG0_DMAKICK(v)        (((v) << 29) & 0x20000000)
-#define BP_I2C_DEBUG0_TBD               26
-#define BM_I2C_DEBUG0_TBD               0x1c000000
-#define BF_I2C_DEBUG0_TBD(v)            (((v) << 26) & 0x1c000000)
-#define BP_I2C_DEBUG0_DMA_STATE         16
-#define BM_I2C_DEBUG0_DMA_STATE         0x3ff0000
-#define BF_I2C_DEBUG0_DMA_STATE(v)      (((v) << 16) & 0x3ff0000)
-#define BP_I2C_DEBUG0_START_TOGGLE      15
-#define BM_I2C_DEBUG0_START_TOGGLE      0x8000
-#define BF_I2C_DEBUG0_START_TOGGLE(v)   (((v) << 15) & 0x8000)
-#define BP_I2C_DEBUG0_STOP_TOGGLE       14
-#define BM_I2C_DEBUG0_STOP_TOGGLE       0x4000
-#define BF_I2C_DEBUG0_STOP_TOGGLE(v)    (((v) << 14) & 0x4000)
-#define BP_I2C_DEBUG0_GRAB_TOGGLE       13
-#define BM_I2C_DEBUG0_GRAB_TOGGLE       0x2000
-#define BF_I2C_DEBUG0_GRAB_TOGGLE(v)    (((v) << 13) & 0x2000)
-#define BP_I2C_DEBUG0_CHANGE_TOGGLE     12
-#define BM_I2C_DEBUG0_CHANGE_TOGGLE     0x1000
-#define BF_I2C_DEBUG0_CHANGE_TOGGLE(v)  (((v) << 12) & 0x1000)
-#define BP_I2C_DEBUG0_TESTMODE          11
-#define BM_I2C_DEBUG0_TESTMODE          0x800
-#define BF_I2C_DEBUG0_TESTMODE(v)       (((v) << 11) & 0x800)
-#define BP_I2C_DEBUG0_SLAVE_HOLD_CLK    10
-#define BM_I2C_DEBUG0_SLAVE_HOLD_CLK    0x400
-#define BF_I2C_DEBUG0_SLAVE_HOLD_CLK(v) (((v) << 10) & 0x400)
-#define BP_I2C_DEBUG0_SLAVE_STATE       0
-#define BM_I2C_DEBUG0_SLAVE_STATE       0x3ff
-#define BF_I2C_DEBUG0_SLAVE_STATE(v)    (((v) << 0) & 0x3ff)
-
-/**
- * Register: HW_I2C_DEBUG1
- * Address: 0x80
- * SCT: yes
-*/
-#define HW_I2C_DEBUG1                       (*(volatile unsigned long *)(REGS_I2C_BASE + 0x80 + 0x0))
-#define HW_I2C_DEBUG1_SET                   (*(volatile unsigned long *)(REGS_I2C_BASE + 0x80 + 0x4))
-#define HW_I2C_DEBUG1_CLR                   (*(volatile unsigned long *)(REGS_I2C_BASE + 0x80 + 0x8))
-#define HW_I2C_DEBUG1_TOG                   (*(volatile unsigned long *)(REGS_I2C_BASE + 0x80 + 0xc))
-#define BP_I2C_DEBUG1_I2C_CLK_IN            31
-#define BM_I2C_DEBUG1_I2C_CLK_IN            0x80000000
-#define BF_I2C_DEBUG1_I2C_CLK_IN(v)         (((v) << 31) & 0x80000000)
-#define BP_I2C_DEBUG1_I2C_DATA_IN           30
-#define BM_I2C_DEBUG1_I2C_DATA_IN           0x40000000
-#define BF_I2C_DEBUG1_I2C_DATA_IN(v)        (((v) << 30) & 0x40000000)
-#define BP_I2C_DEBUG1_DMA_BYTE_ENABLES      24
-#define BM_I2C_DEBUG1_DMA_BYTE_ENABLES      0xf000000
-#define BF_I2C_DEBUG1_DMA_BYTE_ENABLES(v)   (((v) << 24) & 0xf000000)
-#define BP_I2C_DEBUG1_CLK_GEN_STATE         16
-#define BM_I2C_DEBUG1_CLK_GEN_STATE         0x7f0000
-#define BF_I2C_DEBUG1_CLK_GEN_STATE(v)      (((v) << 16) & 0x7f0000)
-#define BP_I2C_DEBUG1_LST_MODE              9
-#define BM_I2C_DEBUG1_LST_MODE              0x600
-#define BV_I2C_DEBUG1_LST_MODE__BCAST       0x0
-#define BV_I2C_DEBUG1_LST_MODE__MY_WRITE    0x1
-#define BV_I2C_DEBUG1_LST_MODE__MY_READ     0x2
-#define BV_I2C_DEBUG1_LST_MODE__NOT_ME      0x3
-#define BF_I2C_DEBUG1_LST_MODE(v)           (((v) << 9) & 0x600)
-#define BF_I2C_DEBUG1_LST_MODE_V(v)         ((BV_I2C_DEBUG1_LST_MODE__##v << 9) & 0x600)
-#define BP_I2C_DEBUG1_LOCAL_SLAVE_TEST      8
-#define BM_I2C_DEBUG1_LOCAL_SLAVE_TEST      0x100
-#define BF_I2C_DEBUG1_LOCAL_SLAVE_TEST(v)   (((v) << 8) & 0x100)
-#define BP_I2C_DEBUG1_FORCE_CLK_ON          5
-#define BM_I2C_DEBUG1_FORCE_CLK_ON          0x20
-#define BF_I2C_DEBUG1_FORCE_CLK_ON(v)       (((v) << 5) & 0x20)
-#define BP_I2C_DEBUG1_FORCE_CLK_IDLE        4
-#define BM_I2C_DEBUG1_FORCE_CLK_IDLE        0x10
-#define BF_I2C_DEBUG1_FORCE_CLK_IDLE(v)     (((v) << 4) & 0x10)
-#define BP_I2C_DEBUG1_FORCE_ARB_LOSS        3
-#define BM_I2C_DEBUG1_FORCE_ARB_LOSS        0x8
-#define BF_I2C_DEBUG1_FORCE_ARB_LOSS(v)     (((v) << 3) & 0x8)
-#define BP_I2C_DEBUG1_FORCE_RCV_ACK         2
-#define BM_I2C_DEBUG1_FORCE_RCV_ACK         0x4
-#define BF_I2C_DEBUG1_FORCE_RCV_ACK(v)      (((v) << 2) & 0x4)
-#define BP_I2C_DEBUG1_FORCE_I2C_DATA_OE     1
-#define BM_I2C_DEBUG1_FORCE_I2C_DATA_OE     0x2
-#define BF_I2C_DEBUG1_FORCE_I2C_DATA_OE(v)  (((v) << 1) & 0x2)
-#define BP_I2C_DEBUG1_FORCE_I2C_CLK_OE      0
-#define BM_I2C_DEBUG1_FORCE_I2C_CLK_OE      0x1
-#define BF_I2C_DEBUG1_FORCE_I2C_CLK_OE(v)   (((v) << 0) & 0x1)
-
-#endif /* __HEADERGEN__STMP3600__I2C__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-icoll.h b/firmware/target/arm/imx233/regs/stmp3600/regs-icoll.h
deleted file mode 100644
index 4cf8cbd5c9..0000000000
--- a/firmware/target/arm/imx233/regs/stmp3600/regs-icoll.h
+++ /dev/null
@@ -1,348 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3600:2.3.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__STMP3600__ICOLL__H__
-#define __HEADERGEN__STMP3600__ICOLL__H__
-
-#define REGS_ICOLL_BASE (0x80000000)
-
-#define REGS_ICOLL_VERSION "2.3.0"
-
-/**
- * Register: HW_ICOLL_VECTOR
- * Address: 0
- * SCT: yes
-*/
-#define HW_ICOLL_VECTOR                 (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x0 + 0x0))
-#define HW_ICOLL_VECTOR_SET             (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x0 + 0x4))
-#define HW_ICOLL_VECTOR_CLR             (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x0 + 0x8))
-#define HW_ICOLL_VECTOR_TOG             (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x0 + 0xc))
-#define BP_ICOLL_VECTOR_IRQVECTOR       2
-#define BM_ICOLL_VECTOR_IRQVECTOR       0xfffffffc
-#define BF_ICOLL_VECTOR_IRQVECTOR(v)    (((v) << 2) & 0xfffffffc)
-
-/**
- * Register: HW_ICOLL_LEVELACK
- * Address: 0x10
- * SCT: no
-*/
-#define HW_ICOLL_LEVELACK                       (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x10))
-#define BP_ICOLL_LEVELACK_IRQLEVELACK           0
-#define BM_ICOLL_LEVELACK_IRQLEVELACK           0xf
-#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0   0x1
-#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL1   0x2
-#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL2   0x4
-#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL3   0x8
-#define BF_ICOLL_LEVELACK_IRQLEVELACK(v)        (((v) << 0) & 0xf)
-#define BF_ICOLL_LEVELACK_IRQLEVELACK_V(v)      ((BV_ICOLL_LEVELACK_IRQLEVELACK__##v << 0) & 0xf)
-
-/**
- * Register: HW_ICOLL_CTRL
- * Address: 0x20
- * SCT: yes
-*/
-#define HW_ICOLL_CTRL                                   (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x20 + 0x0))
-#define HW_ICOLL_CTRL_SET                               (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x20 + 0x4))
-#define HW_ICOLL_CTRL_CLR                               (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x20 + 0x8))
-#define HW_ICOLL_CTRL_TOG                               (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x20 + 0xc))
-#define BP_ICOLL_CTRL_SFTRST                            31
-#define BM_ICOLL_CTRL_SFTRST                            0x80000000
-#define BV_ICOLL_CTRL_SFTRST__RUN                       0x0
-#define BV_ICOLL_CTRL_SFTRST__IN_RESET                  0x1
-#define BF_ICOLL_CTRL_SFTRST(v)                         (((v) << 31) & 0x80000000)
-#define BF_ICOLL_CTRL_SFTRST_V(v)                       ((BV_ICOLL_CTRL_SFTRST__##v << 31) & 0x80000000)
-#define BP_ICOLL_CTRL_CLKGATE                           30
-#define BM_ICOLL_CTRL_CLKGATE                           0x40000000
-#define BV_ICOLL_CTRL_CLKGATE__RUN                      0x0
-#define BV_ICOLL_CTRL_CLKGATE__NO_CLOCKS                0x1
-#define BF_ICOLL_CTRL_CLKGATE(v)                        (((v) << 30) & 0x40000000)
-#define BF_ICOLL_CTRL_CLKGATE_V(v)                      ((BV_ICOLL_CTRL_CLKGATE__##v << 30) & 0x40000000)
-#define BP_ICOLL_CTRL_ENABLE2FIQ35                      27
-#define BM_ICOLL_CTRL_ENABLE2FIQ35                      0x8000000
-#define BV_ICOLL_CTRL_ENABLE2FIQ35__DISABLE             0x0
-#define BV_ICOLL_CTRL_ENABLE2FIQ35__ENABLE              0x1
-#define BF_ICOLL_CTRL_ENABLE2FIQ35(v)                   (((v) << 27) & 0x8000000)
-#define BF_ICOLL_CTRL_ENABLE2FIQ35_V(v)                 ((BV_ICOLL_CTRL_ENABLE2FIQ35__##v << 27) & 0x8000000)
-#define BP_ICOLL_CTRL_ENABLE2FIQ34                      26
-#define BM_ICOLL_CTRL_ENABLE2FIQ34                      0x4000000
-#define BV_ICOLL_CTRL_ENABLE2FIQ34__DISABLE             0x0
-#define BV_ICOLL_CTRL_ENABLE2FIQ34__ENABLE              0x1
-#define BF_ICOLL_CTRL_ENABLE2FIQ34(v)                   (((v) << 26) & 0x4000000)
-#define BF_ICOLL_CTRL_ENABLE2FIQ34_V(v)                 ((BV_ICOLL_CTRL_ENABLE2FIQ34__##v << 26) & 0x4000000)
-#define BP_ICOLL_CTRL_ENABLE2FIQ33                      25
-#define BM_ICOLL_CTRL_ENABLE2FIQ33                      0x2000000
-#define BV_ICOLL_CTRL_ENABLE2FIQ33__DISABLE             0x0
-#define BV_ICOLL_CTRL_ENABLE2FIQ33__ENABLE              0x1
-#define BF_ICOLL_CTRL_ENABLE2FIQ33(v)                   (((v) << 25) & 0x2000000)
-#define BF_ICOLL_CTRL_ENABLE2FIQ33_V(v)                 ((BV_ICOLL_CTRL_ENABLE2FIQ33__##v << 25) & 0x2000000)
-#define BP_ICOLL_CTRL_ENABLE2FIQ32                      24
-#define BM_ICOLL_CTRL_ENABLE2FIQ32                      0x1000000
-#define BV_ICOLL_CTRL_ENABLE2FIQ32__DISABLE             0x0
-#define BV_ICOLL_CTRL_ENABLE2FIQ32__ENABLE              0x1
-#define BF_ICOLL_CTRL_ENABLE2FIQ32(v)                   (((v) << 24) & 0x1000000)
-#define BF_ICOLL_CTRL_ENABLE2FIQ32_V(v)                 ((BV_ICOLL_CTRL_ENABLE2FIQ32__##v << 24) & 0x1000000)
-#define BP_ICOLL_CTRL_BYPASS_FSM                        20
-#define BM_ICOLL_CTRL_BYPASS_FSM                        0x100000
-#define BV_ICOLL_CTRL_BYPASS_FSM__NORMAL                0x0
-#define BV_ICOLL_CTRL_BYPASS_FSM__BYPASS                0x1
-#define BF_ICOLL_CTRL_BYPASS_FSM(v)                     (((v) << 20) & 0x100000)
-#define BF_ICOLL_CTRL_BYPASS_FSM_V(v)                   ((BV_ICOLL_CTRL_BYPASS_FSM__##v << 20) & 0x100000)
-#define BP_ICOLL_CTRL_NO_NESTING                        19
-#define BM_ICOLL_CTRL_NO_NESTING                        0x80000
-#define BV_ICOLL_CTRL_NO_NESTING__NORMAL                0x0
-#define BV_ICOLL_CTRL_NO_NESTING__NO_NEST               0x1
-#define BF_ICOLL_CTRL_NO_NESTING(v)                     (((v) << 19) & 0x80000)
-#define BF_ICOLL_CTRL_NO_NESTING_V(v)                   ((BV_ICOLL_CTRL_NO_NESTING__##v << 19) & 0x80000)
-#define BP_ICOLL_CTRL_ARM_RSE_MODE                      18
-#define BM_ICOLL_CTRL_ARM_RSE_MODE                      0x40000
-#define BV_ICOLL_CTRL_ARM_RSE_MODE__MUST_WRITE          0x0
-#define BV_ICOLL_CTRL_ARM_RSE_MODE__READ_SIDE_EFFECT    0x1
-#define BF_ICOLL_CTRL_ARM_RSE_MODE(v)                   (((v) << 18) & 0x40000)
-#define BF_ICOLL_CTRL_ARM_RSE_MODE_V(v)                 ((BV_ICOLL_CTRL_ARM_RSE_MODE__##v << 18) & 0x40000)
-#define BP_ICOLL_CTRL_FIQ_FINAL_ENABLE                  17
-#define BM_ICOLL_CTRL_FIQ_FINAL_ENABLE                  0x20000
-#define BV_ICOLL_CTRL_FIQ_FINAL_ENABLE__DISABLE         0x0
-#define BV_ICOLL_CTRL_FIQ_FINAL_ENABLE__ENABLE          0x1
-#define BF_ICOLL_CTRL_FIQ_FINAL_ENABLE(v)               (((v) << 17) & 0x20000)
-#define BF_ICOLL_CTRL_FIQ_FINAL_ENABLE_V(v)             ((BV_ICOLL_CTRL_FIQ_FINAL_ENABLE__##v << 17) & 0x20000)
-#define BP_ICOLL_CTRL_IRQ_FINAL_ENABLE                  16
-#define BM_ICOLL_CTRL_IRQ_FINAL_ENABLE                  0x10000
-#define BV_ICOLL_CTRL_IRQ_FINAL_ENABLE__DISABLE         0x0
-#define BV_ICOLL_CTRL_IRQ_FINAL_ENABLE__ENABLE          0x1
-#define BF_ICOLL_CTRL_IRQ_FINAL_ENABLE(v)               (((v) << 16) & 0x10000)
-#define BF_ICOLL_CTRL_IRQ_FINAL_ENABLE_V(v)             ((BV_ICOLL_CTRL_IRQ_FINAL_ENABLE__##v << 16) & 0x10000)
-
-/**
- * Register: HW_ICOLL_STAT
- * Address: 0x30
- * SCT: no
-*/
-#define HW_ICOLL_STAT                   (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x30))
-#define BP_ICOLL_STAT_VECTOR_NUMBER     0
-#define BM_ICOLL_STAT_VECTOR_NUMBER     0x3f
-#define BF_ICOLL_STAT_VECTOR_NUMBER(v)  (((v) << 0) & 0x3f)
-
-/**
- * Register: HW_ICOLL_VBASE
- * Address: 0x160
- * SCT: yes
-*/
-#define HW_ICOLL_VBASE                  (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x160 + 0x0))
-#define HW_ICOLL_VBASE_SET              (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x160 + 0x4))
-#define HW_ICOLL_VBASE_CLR              (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x160 + 0x8))
-#define HW_ICOLL_VBASE_TOG              (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x160 + 0xc))
-#define BP_ICOLL_VBASE_TABLE_ADDRESS    2
-#define BM_ICOLL_VBASE_TABLE_ADDRESS    0xfffffffc
-#define BF_ICOLL_VBASE_TABLE_ADDRESS(v) (((v) << 2) & 0xfffffffc)
-
-/**
- * Register: HW_ICOLL_DEBUG
- * Address: 0x170
- * SCT: no
-*/
-#define HW_ICOLL_DEBUG                              (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x170))
-#define BP_ICOLL_DEBUG_INSERVICE                    28
-#define BM_ICOLL_DEBUG_INSERVICE                    0xf0000000
-#define BV_ICOLL_DEBUG_INSERVICE__LEVEL0            0x1
-#define BV_ICOLL_DEBUG_INSERVICE__LEVEL1            0x2
-#define BV_ICOLL_DEBUG_INSERVICE__LEVEL2            0x4
-#define BV_ICOLL_DEBUG_INSERVICE__LEVEL3            0x8
-#define BF_ICOLL_DEBUG_INSERVICE(v)                 (((v) << 28) & 0xf0000000)
-#define BF_ICOLL_DEBUG_INSERVICE_V(v)               ((BV_ICOLL_DEBUG_INSERVICE__##v << 28) & 0xf0000000)
-#define BP_ICOLL_DEBUG_LEVEL_REQUESTS               24
-#define BM_ICOLL_DEBUG_LEVEL_REQUESTS               0xf000000
-#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL0       0x1
-#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL1       0x2
-#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL2       0x4
-#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL3       0x8
-#define BF_ICOLL_DEBUG_LEVEL_REQUESTS(v)            (((v) << 24) & 0xf000000)
-#define BF_ICOLL_DEBUG_LEVEL_REQUESTS_V(v)          ((BV_ICOLL_DEBUG_LEVEL_REQUESTS__##v << 24) & 0xf000000)
-#define BP_ICOLL_DEBUG_REQUESTS_BY_LEVEL            20
-#define BM_ICOLL_DEBUG_REQUESTS_BY_LEVEL            0xf00000
-#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL0    0x1
-#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL1    0x2
-#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL2    0x4
-#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL3    0x8
-#define BF_ICOLL_DEBUG_REQUESTS_BY_LEVEL(v)         (((v) << 20) & 0xf00000)
-#define BF_ICOLL_DEBUG_REQUESTS_BY_LEVEL_V(v)       ((BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__##v << 20) & 0xf00000)
-#define BP_ICOLL_DEBUG_FIQ                          17
-#define BM_ICOLL_DEBUG_FIQ                          0x20000
-#define BV_ICOLL_DEBUG_FIQ__NO_FIQ_REQUESTED        0x0
-#define BV_ICOLL_DEBUG_FIQ__FIQ_REQUESTED           0x1
-#define BF_ICOLL_DEBUG_FIQ(v)                       (((v) << 17) & 0x20000)
-#define BF_ICOLL_DEBUG_FIQ_V(v)                     ((BV_ICOLL_DEBUG_FIQ__##v << 17) & 0x20000)
-#define BP_ICOLL_DEBUG_IRQ                          16
-#define BM_ICOLL_DEBUG_IRQ                          0x10000
-#define BV_ICOLL_DEBUG_IRQ__NO_IRQ_REQUESTED        0x0
-#define BV_ICOLL_DEBUG_IRQ__IRQ_REQUESTED           0x1
-#define BF_ICOLL_DEBUG_IRQ(v)                       (((v) << 16) & 0x10000)
-#define BF_ICOLL_DEBUG_IRQ_V(v)                     ((BV_ICOLL_DEBUG_IRQ__##v << 16) & 0x10000)
-#define BP_ICOLL_DEBUG_VECTOR_FSM                   0
-#define BM_ICOLL_DEBUG_VECTOR_FSM                   0x3ff
-#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_IDLE         0x0
-#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE1  0x1
-#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE2  0x2
-#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_PENDING      0x4
-#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE3  0x8
-#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE4  0x10
-#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING1 0x20
-#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING2 0x40
-#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING3 0x80
-#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE5  0x100
-#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE6  0x200
-#define BF_ICOLL_DEBUG_VECTOR_FSM(v)                (((v) << 0) & 0x3ff)
-#define BF_ICOLL_DEBUG_VECTOR_FSM_V(v)              ((BV_ICOLL_DEBUG_VECTOR_FSM__##v << 0) & 0x3ff)
-
-/**
- * Register: HW_ICOLL_DBGFLAG
- * Address: 0x1a0
- * SCT: yes
-*/
-#define HW_ICOLL_DBGFLAG            (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1a0 + 0x0))
-#define HW_ICOLL_DBGFLAG_SET        (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1a0 + 0x4))
-#define HW_ICOLL_DBGFLAG_CLR        (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1a0 + 0x8))
-#define HW_ICOLL_DBGFLAG_TOG        (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1a0 + 0xc))
-#define BP_ICOLL_DBGFLAG_FLAG       0
-#define BM_ICOLL_DBGFLAG_FLAG       0xffff
-#define BF_ICOLL_DBGFLAG_FLAG(v)    (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_ICOLL_DBGREQUESTn
- * Address: 0x1b0+n*0x10
- * SCT: no
-*/
-#define HW_ICOLL_DBGREQUESTn(n)         (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1b0+(n)*0x10))
-#define BP_ICOLL_DBGREQUESTn_BITS       0
-#define BM_ICOLL_DBGREQUESTn_BITS       0xffffffff
-#define BF_ICOLL_DBGREQUESTn_BITS(v)    (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_ICOLL_RAWn
- * Address: 0x40+n*0x10
- * SCT: no
-*/
-#define HW_ICOLL_RAWn(n)            (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x40+(n)*0x10))
-#define BP_ICOLL_RAWn_RAW_IRQS      0
-#define BM_ICOLL_RAWn_RAW_IRQS      0xffffffff
-#define BF_ICOLL_RAWn_RAW_IRQS(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_ICOLL_DBGREADn
- * Address: 0x180+n*0x10
- * SCT: no
-*/
-#define HW_ICOLL_DBGREADn(n)        (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x180+(n)*0x10))
-#define BP_ICOLL_DBGREADn_VALUE     0
-#define BM_ICOLL_DBGREADn_VALUE     0xffffffff
-#define BF_ICOLL_DBGREADn_VALUE(v)  (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_ICOLL_PRIORITYn
- * Address: 0x60+n*0x10
- * SCT: yes
-*/
-#define HW_ICOLL_PRIORITYn(n)                           (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x60+(n)*0x10 + 0x0))
-#define HW_ICOLL_PRIORITYn_SET(n)                       (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x60+(n)*0x10 + 0x4))
-#define HW_ICOLL_PRIORITYn_CLR(n)                       (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x60+(n)*0x10 + 0x8))
-#define HW_ICOLL_PRIORITYn_TOG(n)                       (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x60+(n)*0x10 + 0xc))
-#define BP_ICOLL_PRIORITYn_SOFTIRQ3                     27
-#define BM_ICOLL_PRIORITYn_SOFTIRQ3                     0x8000000
-#define BV_ICOLL_PRIORITYn_SOFTIRQ3__NO_INTERRUPT       0x0
-#define BV_ICOLL_PRIORITYn_SOFTIRQ3__FORCE_INTERRUPT    0x1
-#define BF_ICOLL_PRIORITYn_SOFTIRQ3(v)                  (((v) << 27) & 0x8000000)
-#define BF_ICOLL_PRIORITYn_SOFTIRQ3_V(v)                ((BV_ICOLL_PRIORITYn_SOFTIRQ3__##v << 27) & 0x8000000)
-#define BP_ICOLL_PRIORITYn_ENABLE3                      26
-#define BM_ICOLL_PRIORITYn_ENABLE3                      0x4000000
-#define BV_ICOLL_PRIORITYn_ENABLE3__DISABLE             0x0
-#define BV_ICOLL_PRIORITYn_ENABLE3__ENABLE              0x1
-#define BF_ICOLL_PRIORITYn_ENABLE3(v)                   (((v) << 26) & 0x4000000)
-#define BF_ICOLL_PRIORITYn_ENABLE3_V(v)                 ((BV_ICOLL_PRIORITYn_ENABLE3__##v << 26) & 0x4000000)
-#define BP_ICOLL_PRIORITYn_PRIORITY3                    24
-#define BM_ICOLL_PRIORITYn_PRIORITY3                    0x3000000
-#define BV_ICOLL_PRIORITYn_PRIORITY3__LEVEL0            0x0
-#define BV_ICOLL_PRIORITYn_PRIORITY3__LEVEL1            0x1
-#define BV_ICOLL_PRIORITYn_PRIORITY3__LEVEL2            0x2
-#define BV_ICOLL_PRIORITYn_PRIORITY3__LEVEL3            0x3
-#define BF_ICOLL_PRIORITYn_PRIORITY3(v)                 (((v) << 24) & 0x3000000)
-#define BF_ICOLL_PRIORITYn_PRIORITY3_V(v)               ((BV_ICOLL_PRIORITYn_PRIORITY3__##v << 24) & 0x3000000)
-#define BP_ICOLL_PRIORITYn_SOFTIRQ2                     19
-#define BM_ICOLL_PRIORITYn_SOFTIRQ2                     0x80000
-#define BV_ICOLL_PRIORITYn_SOFTIRQ2__NO_INTERRUPT       0x0
-#define BV_ICOLL_PRIORITYn_SOFTIRQ2__FORCE_INTERRUPT    0x1
-#define BF_ICOLL_PRIORITYn_SOFTIRQ2(v)                  (((v) << 19) & 0x80000)
-#define BF_ICOLL_PRIORITYn_SOFTIRQ2_V(v)                ((BV_ICOLL_PRIORITYn_SOFTIRQ2__##v << 19) & 0x80000)
-#define BP_ICOLL_PRIORITYn_ENABLE2                      18
-#define BM_ICOLL_PRIORITYn_ENABLE2                      0x40000
-#define BV_ICOLL_PRIORITYn_ENABLE2__DISABLE             0x0
-#define BV_ICOLL_PRIORITYn_ENABLE2__ENABLE              0x1
-#define BF_ICOLL_PRIORITYn_ENABLE2(v)                   (((v) << 18) & 0x40000)
-#define BF_ICOLL_PRIORITYn_ENABLE2_V(v)                 ((BV_ICOLL_PRIORITYn_ENABLE2__##v << 18) & 0x40000)
-#define BP_ICOLL_PRIORITYn_PRIORITY2                    16
-#define BM_ICOLL_PRIORITYn_PRIORITY2                    0x30000
-#define BV_ICOLL_PRIORITYn_PRIORITY2__LEVEL0            0x0
-#define BV_ICOLL_PRIORITYn_PRIORITY2__LEVEL1            0x1
-#define BV_ICOLL_PRIORITYn_PRIORITY2__LEVEL2            0x2
-#define BV_ICOLL_PRIORITYn_PRIORITY2__LEVEL3            0x3
-#define BF_ICOLL_PRIORITYn_PRIORITY2(v)                 (((v) << 16) & 0x30000)
-#define BF_ICOLL_PRIORITYn_PRIORITY2_V(v)               ((BV_ICOLL_PRIORITYn_PRIORITY2__##v << 16) & 0x30000)
-#define BP_ICOLL_PRIORITYn_SOFTIRQ1                     11
-#define BM_ICOLL_PRIORITYn_SOFTIRQ1                     0x800
-#define BV_ICOLL_PRIORITYn_SOFTIRQ1__NO_INTERRUPT       0x0
-#define BV_ICOLL_PRIORITYn_SOFTIRQ1__FORCE_INTERRUPT    0x1
-#define BF_ICOLL_PRIORITYn_SOFTIRQ1(v)                  (((v) << 11) & 0x800)
-#define BF_ICOLL_PRIORITYn_SOFTIRQ1_V(v)                ((BV_ICOLL_PRIORITYn_SOFTIRQ1__##v << 11) & 0x800)
-#define BP_ICOLL_PRIORITYn_ENABLE1                      10
-#define BM_ICOLL_PRIORITYn_ENABLE1                      0x400
-#define BV_ICOLL_PRIORITYn_ENABLE1__DISABLE             0x0
-#define BV_ICOLL_PRIORITYn_ENABLE1__ENABLE              0x1
-#define BF_ICOLL_PRIORITYn_ENABLE1(v)                   (((v) << 10) & 0x400)
-#define BF_ICOLL_PRIORITYn_ENABLE1_V(v)                 ((BV_ICOLL_PRIORITYn_ENABLE1__##v << 10) & 0x400)
-#define BP_ICOLL_PRIORITYn_PRIORITY1                    8
-#define BM_ICOLL_PRIORITYn_PRIORITY1                    0x300
-#define BV_ICOLL_PRIORITYn_PRIORITY1__LEVEL0            0x0
-#define BV_ICOLL_PRIORITYn_PRIORITY1__LEVEL1            0x1
-#define BV_ICOLL_PRIORITYn_PRIORITY1__LEVEL2            0x2
-#define BV_ICOLL_PRIORITYn_PRIORITY1__LEVEL3            0x3
-#define BF_ICOLL_PRIORITYn_PRIORITY1(v)                 (((v) << 8) & 0x300)
-#define BF_ICOLL_PRIORITYn_PRIORITY1_V(v)               ((BV_ICOLL_PRIORITYn_PRIORITY1__##v << 8) & 0x300)
-#define BP_ICOLL_PRIORITYn_SOFTIRQ0                     3
-#define BM_ICOLL_PRIORITYn_SOFTIRQ0                     0x8
-#define BV_ICOLL_PRIORITYn_SOFTIRQ0__NO_INTERRUPT       0x0
-#define BV_ICOLL_PRIORITYn_SOFTIRQ0__FORCE_INTERRUPT    0x1
-#define BF_ICOLL_PRIORITYn_SOFTIRQ0(v)                  (((v) << 3) & 0x8)
-#define BF_ICOLL_PRIORITYn_SOFTIRQ0_V(v)                ((BV_ICOLL_PRIORITYn_SOFTIRQ0__##v << 3) & 0x8)
-#define BP_ICOLL_PRIORITYn_ENABLE0                      2
-#define BM_ICOLL_PRIORITYn_ENABLE0                      0x4
-#define BV_ICOLL_PRIORITYn_ENABLE0__DISABLE             0x0
-#define BV_ICOLL_PRIORITYn_ENABLE0__ENABLE              0x1
-#define BF_ICOLL_PRIORITYn_ENABLE0(v)                   (((v) << 2) & 0x4)
-#define BF_ICOLL_PRIORITYn_ENABLE0_V(v)                 ((BV_ICOLL_PRIORITYn_ENABLE0__##v << 2) & 0x4)
-#define BP_ICOLL_PRIORITYn_PRIORITY0                    0
-#define BM_ICOLL_PRIORITYn_PRIORITY0                    0x3
-#define BV_ICOLL_PRIORITYn_PRIORITY0__LEVEL0            0x0
-#define BV_ICOLL_PRIORITYn_PRIORITY0__LEVEL1            0x1
-#define BV_ICOLL_PRIORITYn_PRIORITY0__LEVEL2            0x2
-#define BV_ICOLL_PRIORITYn_PRIORITY0__LEVEL3            0x3
-#define BF_ICOLL_PRIORITYn_PRIORITY0(v)                 (((v) << 0) & 0x3)
-#define BF_ICOLL_PRIORITYn_PRIORITY0_V(v)               ((BV_ICOLL_PRIORITYn_PRIORITY0__##v << 0) & 0x3)
-
-#endif /* __HEADERGEN__STMP3600__ICOLL__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-ir.h b/firmware/target/arm/imx233/regs/stmp3600/regs-ir.h
deleted file mode 100644
index 778e2dcd16..0000000000
--- a/firmware/target/arm/imx233/regs/stmp3600/regs-ir.h
+++ /dev/null
@@ -1,477 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3600:2.3.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__STMP3600__IR__H__
-#define __HEADERGEN__STMP3600__IR__H__
-
-#define REGS_IR_BASE (0x80078000)
-
-#define REGS_IR_VERSION "2.3.0"
-
-/**
- * Register: HW_IR_CTRL
- * Address: 0
- * SCT: yes
-*/
-#define HW_IR_CTRL                  (*(volatile unsigned long *)(REGS_IR_BASE + 0x0 + 0x0))
-#define HW_IR_CTRL_SET              (*(volatile unsigned long *)(REGS_IR_BASE + 0x0 + 0x4))
-#define HW_IR_CTRL_CLR              (*(volatile unsigned long *)(REGS_IR_BASE + 0x0 + 0x8))
-#define HW_IR_CTRL_TOG              (*(volatile unsigned long *)(REGS_IR_BASE + 0x0 + 0xc))
-#define BP_IR_CTRL_SFTRST           31
-#define BM_IR_CTRL_SFTRST           0x80000000
-#define BV_IR_CTRL_SFTRST__RUN      0x0
-#define BV_IR_CTRL_SFTRST__RESET    0x1
-#define BF_IR_CTRL_SFTRST(v)        (((v) << 31) & 0x80000000)
-#define BF_IR_CTRL_SFTRST_V(v)      ((BV_IR_CTRL_SFTRST__##v << 31) & 0x80000000)
-#define BP_IR_CTRL_CLKGATE          30
-#define BM_IR_CTRL_CLKGATE          0x40000000
-#define BF_IR_CTRL_CLKGATE(v)       (((v) << 30) & 0x40000000)
-#define BP_IR_CTRL_MTA              24
-#define BM_IR_CTRL_MTA              0x7000000
-#define BV_IR_CTRL_MTA__MTA_10MS    0x0
-#define BV_IR_CTRL_MTA__MTA_5MS     0x1
-#define BV_IR_CTRL_MTA__MTA_1MS     0x2
-#define BV_IR_CTRL_MTA__MTA_500US   0x3
-#define BV_IR_CTRL_MTA__MTA_100US   0x4
-#define BV_IR_CTRL_MTA__MTA_50US    0x5
-#define BV_IR_CTRL_MTA__MTA_10US    0x6
-#define BV_IR_CTRL_MTA__MTA_0       0x7
-#define BF_IR_CTRL_MTA(v)           (((v) << 24) & 0x7000000)
-#define BF_IR_CTRL_MTA_V(v)         ((BV_IR_CTRL_MTA__##v << 24) & 0x7000000)
-#define BP_IR_CTRL_MODE             22
-#define BM_IR_CTRL_MODE             0xc00000
-#define BV_IR_CTRL_MODE__SIR        0x0
-#define BV_IR_CTRL_MODE__MIR        0x1
-#define BV_IR_CTRL_MODE__FIR        0x2
-#define BV_IR_CTRL_MODE__VFIR       0x3
-#define BF_IR_CTRL_MODE(v)          (((v) << 22) & 0xc00000)
-#define BF_IR_CTRL_MODE_V(v)        ((BV_IR_CTRL_MODE__##v << 22) & 0xc00000)
-#define BP_IR_CTRL_SPEED            19
-#define BM_IR_CTRL_SPEED            0x380000
-#define BV_IR_CTRL_SPEED__SPD000    0x0
-#define BV_IR_CTRL_SPEED__SPD001    0x1
-#define BV_IR_CTRL_SPEED__SPD010    0x2
-#define BV_IR_CTRL_SPEED__SPD011    0x3
-#define BV_IR_CTRL_SPEED__SPD100    0x4
-#define BV_IR_CTRL_SPEED__SPD101    0x5
-#define BF_IR_CTRL_SPEED(v)         (((v) << 19) & 0x380000)
-#define BF_IR_CTRL_SPEED_V(v)       ((BV_IR_CTRL_SPEED__##v << 19) & 0x380000)
-#define BP_IR_CTRL_TC_TIME_DIV      8
-#define BM_IR_CTRL_TC_TIME_DIV      0x3f00
-#define BF_IR_CTRL_TC_TIME_DIV(v)   (((v) << 8) & 0x3f00)
-#define BP_IR_CTRL_TC_TYPE          7
-#define BM_IR_CTRL_TC_TYPE          0x80
-#define BF_IR_CTRL_TC_TYPE(v)       (((v) << 7) & 0x80)
-#define BP_IR_CTRL_SIR_GAP          4
-#define BM_IR_CTRL_SIR_GAP          0x70
-#define BV_IR_CTRL_SIR_GAP__GAP_10K 0x0
-#define BV_IR_CTRL_SIR_GAP__GAP_5K  0x1
-#define BV_IR_CTRL_SIR_GAP__GAP_1K  0x2
-#define BV_IR_CTRL_SIR_GAP__GAP_500 0x3
-#define BV_IR_CTRL_SIR_GAP__GAP_100 0x4
-#define BV_IR_CTRL_SIR_GAP__GAP_50  0x5
-#define BV_IR_CTRL_SIR_GAP__GAP_10  0x6
-#define BV_IR_CTRL_SIR_GAP__GAP_0   0x7
-#define BF_IR_CTRL_SIR_GAP(v)       (((v) << 4) & 0x70)
-#define BF_IR_CTRL_SIR_GAP_V(v)     ((BV_IR_CTRL_SIR_GAP__##v << 4) & 0x70)
-#define BP_IR_CTRL_SIPEN            3
-#define BM_IR_CTRL_SIPEN            0x8
-#define BF_IR_CTRL_SIPEN(v)         (((v) << 3) & 0x8)
-#define BP_IR_CTRL_TCEN             2
-#define BM_IR_CTRL_TCEN             0x4
-#define BF_IR_CTRL_TCEN(v)          (((v) << 2) & 0x4)
-#define BP_IR_CTRL_TXEN             1
-#define BM_IR_CTRL_TXEN             0x2
-#define BF_IR_CTRL_TXEN(v)          (((v) << 1) & 0x2)
-#define BP_IR_CTRL_RXEN             0
-#define BM_IR_CTRL_RXEN             0x1
-#define BF_IR_CTRL_RXEN(v)          (((v) << 0) & 0x1)
-
-/**
- * Register: HW_IR_TXDMA
- * Address: 0x10
- * SCT: yes
-*/
-#define HW_IR_TXDMA                 (*(volatile unsigned long *)(REGS_IR_BASE + 0x10 + 0x0))
-#define HW_IR_TXDMA_SET             (*(volatile unsigned long *)(REGS_IR_BASE + 0x10 + 0x4))
-#define HW_IR_TXDMA_CLR             (*(volatile unsigned long *)(REGS_IR_BASE + 0x10 + 0x8))
-#define HW_IR_TXDMA_TOG             (*(volatile unsigned long *)(REGS_IR_BASE + 0x10 + 0xc))
-#define BP_IR_TXDMA_RUN             31
-#define BM_IR_TXDMA_RUN             0x80000000
-#define BF_IR_TXDMA_RUN(v)          (((v) << 31) & 0x80000000)
-#define BP_IR_TXDMA_EMPTY           29
-#define BM_IR_TXDMA_EMPTY           0x20000000
-#define BF_IR_TXDMA_EMPTY(v)        (((v) << 29) & 0x20000000)
-#define BP_IR_TXDMA_INT             28
-#define BM_IR_TXDMA_INT             0x10000000
-#define BF_IR_TXDMA_INT(v)          (((v) << 28) & 0x10000000)
-#define BP_IR_TXDMA_CHANGE          27
-#define BM_IR_TXDMA_CHANGE          0x8000000
-#define BF_IR_TXDMA_CHANGE(v)       (((v) << 27) & 0x8000000)
-#define BP_IR_TXDMA_NEW_MTA         24
-#define BM_IR_TXDMA_NEW_MTA         0x7000000
-#define BF_IR_TXDMA_NEW_MTA(v)      (((v) << 24) & 0x7000000)
-#define BP_IR_TXDMA_NEW_MODE        22
-#define BM_IR_TXDMA_NEW_MODE        0xc00000
-#define BF_IR_TXDMA_NEW_MODE(v)     (((v) << 22) & 0xc00000)
-#define BP_IR_TXDMA_NEW_SPEED       19
-#define BM_IR_TXDMA_NEW_SPEED       0x380000
-#define BF_IR_TXDMA_NEW_SPEED(v)    (((v) << 19) & 0x380000)
-#define BP_IR_TXDMA_BOF_TYPE        18
-#define BM_IR_TXDMA_BOF_TYPE        0x40000
-#define BF_IR_TXDMA_BOF_TYPE(v)     (((v) << 18) & 0x40000)
-#define BP_IR_TXDMA_XBOFS           12
-#define BM_IR_TXDMA_XBOFS           0x3f000
-#define BF_IR_TXDMA_XBOFS(v)        (((v) << 12) & 0x3f000)
-#define BP_IR_TXDMA_XFER_COUNT      0
-#define BM_IR_TXDMA_XFER_COUNT      0xfff
-#define BF_IR_TXDMA_XFER_COUNT(v)   (((v) << 0) & 0xfff)
-
-/**
- * Register: HW_IR_RXDMA
- * Address: 0x20
- * SCT: yes
-*/
-#define HW_IR_RXDMA                 (*(volatile unsigned long *)(REGS_IR_BASE + 0x20 + 0x0))
-#define HW_IR_RXDMA_SET             (*(volatile unsigned long *)(REGS_IR_BASE + 0x20 + 0x4))
-#define HW_IR_RXDMA_CLR             (*(volatile unsigned long *)(REGS_IR_BASE + 0x20 + 0x8))
-#define HW_IR_RXDMA_TOG             (*(volatile unsigned long *)(REGS_IR_BASE + 0x20 + 0xc))
-#define BP_IR_RXDMA_RUN             31
-#define BM_IR_RXDMA_RUN             0x80000000
-#define BF_IR_RXDMA_RUN(v)          (((v) << 31) & 0x80000000)
-#define BP_IR_RXDMA_XFER_COUNT      0
-#define BM_IR_RXDMA_XFER_COUNT      0x3ff
-#define BF_IR_RXDMA_XFER_COUNT(v)   (((v) << 0) & 0x3ff)
-
-/**
- * Register: HW_IR_DBGCTRL
- * Address: 0x30
- * SCT: yes
-*/
-#define HW_IR_DBGCTRL                   (*(volatile unsigned long *)(REGS_IR_BASE + 0x30 + 0x0))
-#define HW_IR_DBGCTRL_SET               (*(volatile unsigned long *)(REGS_IR_BASE + 0x30 + 0x4))
-#define HW_IR_DBGCTRL_CLR               (*(volatile unsigned long *)(REGS_IR_BASE + 0x30 + 0x8))
-#define HW_IR_DBGCTRL_TOG               (*(volatile unsigned long *)(REGS_IR_BASE + 0x30 + 0xc))
-#define BP_IR_DBGCTRL_VFIRSWZ           12
-#define BM_IR_DBGCTRL_VFIRSWZ           0x1000
-#define BV_IR_DBGCTRL_VFIRSWZ__NORMAL   0x0
-#define BV_IR_DBGCTRL_VFIRSWZ__SWAP     0x1
-#define BF_IR_DBGCTRL_VFIRSWZ(v)        (((v) << 12) & 0x1000)
-#define BF_IR_DBGCTRL_VFIRSWZ_V(v)      ((BV_IR_DBGCTRL_VFIRSWZ__##v << 12) & 0x1000)
-#define BP_IR_DBGCTRL_RXFRMOFF          11
-#define BM_IR_DBGCTRL_RXFRMOFF          0x800
-#define BF_IR_DBGCTRL_RXFRMOFF(v)       (((v) << 11) & 0x800)
-#define BP_IR_DBGCTRL_RXCRCOFF          10
-#define BM_IR_DBGCTRL_RXCRCOFF          0x400
-#define BF_IR_DBGCTRL_RXCRCOFF(v)       (((v) << 10) & 0x400)
-#define BP_IR_DBGCTRL_RXINVERT          9
-#define BM_IR_DBGCTRL_RXINVERT          0x200
-#define BF_IR_DBGCTRL_RXINVERT(v)       (((v) << 9) & 0x200)
-#define BP_IR_DBGCTRL_TXFRMOFF          8
-#define BM_IR_DBGCTRL_TXFRMOFF          0x100
-#define BF_IR_DBGCTRL_TXFRMOFF(v)       (((v) << 8) & 0x100)
-#define BP_IR_DBGCTRL_TXCRCOFF          7
-#define BM_IR_DBGCTRL_TXCRCOFF          0x80
-#define BF_IR_DBGCTRL_TXCRCOFF(v)       (((v) << 7) & 0x80)
-#define BP_IR_DBGCTRL_TXINVERT          6
-#define BM_IR_DBGCTRL_TXINVERT          0x40
-#define BF_IR_DBGCTRL_TXINVERT(v)       (((v) << 6) & 0x40)
-#define BP_IR_DBGCTRL_INTLOOPBACK       5
-#define BM_IR_DBGCTRL_INTLOOPBACK       0x20
-#define BF_IR_DBGCTRL_INTLOOPBACK(v)    (((v) << 5) & 0x20)
-#define BP_IR_DBGCTRL_DUPLEX            4
-#define BM_IR_DBGCTRL_DUPLEX            0x10
-#define BF_IR_DBGCTRL_DUPLEX(v)         (((v) << 4) & 0x10)
-#define BP_IR_DBGCTRL_MIO_RX            3
-#define BM_IR_DBGCTRL_MIO_RX            0x8
-#define BF_IR_DBGCTRL_MIO_RX(v)         (((v) << 3) & 0x8)
-#define BP_IR_DBGCTRL_MIO_TX            2
-#define BM_IR_DBGCTRL_MIO_TX            0x4
-#define BF_IR_DBGCTRL_MIO_TX(v)         (((v) << 2) & 0x4)
-#define BP_IR_DBGCTRL_MIO_SCLK          1
-#define BM_IR_DBGCTRL_MIO_SCLK          0x2
-#define BF_IR_DBGCTRL_MIO_SCLK(v)       (((v) << 1) & 0x2)
-#define BP_IR_DBGCTRL_MIO_EN            0
-#define BM_IR_DBGCTRL_MIO_EN            0x1
-#define BF_IR_DBGCTRL_MIO_EN(v)         (((v) << 0) & 0x1)
-
-/**
- * Register: HW_IR_INTR
- * Address: 0x40
- * SCT: yes
-*/
-#define HW_IR_INTR                          (*(volatile unsigned long *)(REGS_IR_BASE + 0x40 + 0x0))
-#define HW_IR_INTR_SET                      (*(volatile unsigned long *)(REGS_IR_BASE + 0x40 + 0x4))
-#define HW_IR_INTR_CLR                      (*(volatile unsigned long *)(REGS_IR_BASE + 0x40 + 0x8))
-#define HW_IR_INTR_TOG                      (*(volatile unsigned long *)(REGS_IR_BASE + 0x40 + 0xc))
-#define BP_IR_INTR_RXABORT_IRQ_EN           22
-#define BM_IR_INTR_RXABORT_IRQ_EN           0x400000
-#define BV_IR_INTR_RXABORT_IRQ_EN__DISABLED 0x0
-#define BV_IR_INTR_RXABORT_IRQ_EN__ENABLED  0x1
-#define BF_IR_INTR_RXABORT_IRQ_EN(v)        (((v) << 22) & 0x400000)
-#define BF_IR_INTR_RXABORT_IRQ_EN_V(v)      ((BV_IR_INTR_RXABORT_IRQ_EN__##v << 22) & 0x400000)
-#define BP_IR_INTR_SPEED_IRQ_EN             21
-#define BM_IR_INTR_SPEED_IRQ_EN             0x200000
-#define BV_IR_INTR_SPEED_IRQ_EN__DISABLED   0x0
-#define BV_IR_INTR_SPEED_IRQ_EN__ENABLED    0x1
-#define BF_IR_INTR_SPEED_IRQ_EN(v)          (((v) << 21) & 0x200000)
-#define BF_IR_INTR_SPEED_IRQ_EN_V(v)        ((BV_IR_INTR_SPEED_IRQ_EN__##v << 21) & 0x200000)
-#define BP_IR_INTR_RXOF_IRQ_EN              20
-#define BM_IR_INTR_RXOF_IRQ_EN              0x100000
-#define BV_IR_INTR_RXOF_IRQ_EN__DISABLED    0x0
-#define BV_IR_INTR_RXOF_IRQ_EN__ENABLED     0x1
-#define BF_IR_INTR_RXOF_IRQ_EN(v)           (((v) << 20) & 0x100000)
-#define BF_IR_INTR_RXOF_IRQ_EN_V(v)         ((BV_IR_INTR_RXOF_IRQ_EN__##v << 20) & 0x100000)
-#define BP_IR_INTR_TXUF_IRQ_EN              19
-#define BM_IR_INTR_TXUF_IRQ_EN              0x80000
-#define BV_IR_INTR_TXUF_IRQ_EN__DISABLED    0x0
-#define BV_IR_INTR_TXUF_IRQ_EN__ENABLED     0x1
-#define BF_IR_INTR_TXUF_IRQ_EN(v)           (((v) << 19) & 0x80000)
-#define BF_IR_INTR_TXUF_IRQ_EN_V(v)         ((BV_IR_INTR_TXUF_IRQ_EN__##v << 19) & 0x80000)
-#define BP_IR_INTR_TC_IRQ_EN                18
-#define BM_IR_INTR_TC_IRQ_EN                0x40000
-#define BV_IR_INTR_TC_IRQ_EN__DISABLED      0x0
-#define BV_IR_INTR_TC_IRQ_EN__ENABLED       0x1
-#define BF_IR_INTR_TC_IRQ_EN(v)             (((v) << 18) & 0x40000)
-#define BF_IR_INTR_TC_IRQ_EN_V(v)           ((BV_IR_INTR_TC_IRQ_EN__##v << 18) & 0x40000)
-#define BP_IR_INTR_RX_IRQ_EN                17
-#define BM_IR_INTR_RX_IRQ_EN                0x20000
-#define BV_IR_INTR_RX_IRQ_EN__DISABLED      0x0
-#define BV_IR_INTR_RX_IRQ_EN__ENABLED       0x1
-#define BF_IR_INTR_RX_IRQ_EN(v)             (((v) << 17) & 0x20000)
-#define BF_IR_INTR_RX_IRQ_EN_V(v)           ((BV_IR_INTR_RX_IRQ_EN__##v << 17) & 0x20000)
-#define BP_IR_INTR_TX_IRQ_EN                16
-#define BM_IR_INTR_TX_IRQ_EN                0x10000
-#define BV_IR_INTR_TX_IRQ_EN__DISABLED      0x0
-#define BV_IR_INTR_TX_IRQ_EN__ENABLED       0x1
-#define BF_IR_INTR_TX_IRQ_EN(v)             (((v) << 16) & 0x10000)
-#define BF_IR_INTR_TX_IRQ_EN_V(v)           ((BV_IR_INTR_TX_IRQ_EN__##v << 16) & 0x10000)
-#define BP_IR_INTR_RXABORT_IRQ              6
-#define BM_IR_INTR_RXABORT_IRQ              0x40
-#define BV_IR_INTR_RXABORT_IRQ__NO_REQUEST  0x0
-#define BV_IR_INTR_RXABORT_IRQ__REQUEST     0x1
-#define BF_IR_INTR_RXABORT_IRQ(v)           (((v) << 6) & 0x40)
-#define BF_IR_INTR_RXABORT_IRQ_V(v)         ((BV_IR_INTR_RXABORT_IRQ__##v << 6) & 0x40)
-#define BP_IR_INTR_SPEED_IRQ                5
-#define BM_IR_INTR_SPEED_IRQ                0x20
-#define BV_IR_INTR_SPEED_IRQ__NO_REQUEST    0x0
-#define BV_IR_INTR_SPEED_IRQ__REQUEST       0x1
-#define BF_IR_INTR_SPEED_IRQ(v)             (((v) << 5) & 0x20)
-#define BF_IR_INTR_SPEED_IRQ_V(v)           ((BV_IR_INTR_SPEED_IRQ__##v << 5) & 0x20)
-#define BP_IR_INTR_RXOF_IRQ                 4
-#define BM_IR_INTR_RXOF_IRQ                 0x10
-#define BV_IR_INTR_RXOF_IRQ__NO_REQUEST     0x0
-#define BV_IR_INTR_RXOF_IRQ__REQUEST        0x1
-#define BF_IR_INTR_RXOF_IRQ(v)              (((v) << 4) & 0x10)
-#define BF_IR_INTR_RXOF_IRQ_V(v)            ((BV_IR_INTR_RXOF_IRQ__##v << 4) & 0x10)
-#define BP_IR_INTR_TXUF_IRQ                 3
-#define BM_IR_INTR_TXUF_IRQ                 0x8
-#define BV_IR_INTR_TXUF_IRQ__NO_REQUEST     0x0
-#define BV_IR_INTR_TXUF_IRQ__REQUEST        0x1
-#define BF_IR_INTR_TXUF_IRQ(v)              (((v) << 3) & 0x8)
-#define BF_IR_INTR_TXUF_IRQ_V(v)            ((BV_IR_INTR_TXUF_IRQ__##v << 3) & 0x8)
-#define BP_IR_INTR_TC_IRQ                   2
-#define BM_IR_INTR_TC_IRQ                   0x4
-#define BV_IR_INTR_TC_IRQ__NO_REQUEST       0x0
-#define BV_IR_INTR_TC_IRQ__REQUEST          0x1
-#define BF_IR_INTR_TC_IRQ(v)                (((v) << 2) & 0x4)
-#define BF_IR_INTR_TC_IRQ_V(v)              ((BV_IR_INTR_TC_IRQ__##v << 2) & 0x4)
-#define BP_IR_INTR_RX_IRQ                   1
-#define BM_IR_INTR_RX_IRQ                   0x2
-#define BV_IR_INTR_RX_IRQ__NO_REQUEST       0x0
-#define BV_IR_INTR_RX_IRQ__REQUEST          0x1
-#define BF_IR_INTR_RX_IRQ(v)                (((v) << 1) & 0x2)
-#define BF_IR_INTR_RX_IRQ_V(v)              ((BV_IR_INTR_RX_IRQ__##v << 1) & 0x2)
-#define BP_IR_INTR_TX_IRQ                   0
-#define BM_IR_INTR_TX_IRQ                   0x1
-#define BV_IR_INTR_TX_IRQ__NO_REQUEST       0x0
-#define BV_IR_INTR_TX_IRQ__REQUEST          0x1
-#define BF_IR_INTR_TX_IRQ(v)                (((v) << 0) & 0x1)
-#define BF_IR_INTR_TX_IRQ_V(v)              ((BV_IR_INTR_TX_IRQ__##v << 0) & 0x1)
-
-/**
- * Register: HW_IR_DATA
- * Address: 0x50
- * SCT: no
-*/
-#define HW_IR_DATA          (*(volatile unsigned long *)(REGS_IR_BASE + 0x50))
-#define BP_IR_DATA_DATA     0
-#define BM_IR_DATA_DATA     0xffffffff
-#define BF_IR_DATA_DATA(v)  (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_IR_STAT
- * Address: 0x60
- * SCT: no
-*/
-#define HW_IR_STAT                              (*(volatile unsigned long *)(REGS_IR_BASE + 0x60))
-#define BP_IR_STAT_PRESENT                      31
-#define BM_IR_STAT_PRESENT                      0x80000000
-#define BV_IR_STAT_PRESENT__UNAVAILABLE         0x0
-#define BV_IR_STAT_PRESENT__AVAILABLE           0x1
-#define BF_IR_STAT_PRESENT(v)                   (((v) << 31) & 0x80000000)
-#define BF_IR_STAT_PRESENT_V(v)                 ((BV_IR_STAT_PRESENT__##v << 31) & 0x80000000)
-#define BP_IR_STAT_MODE_ALLOWED                 29
-#define BM_IR_STAT_MODE_ALLOWED                 0x60000000
-#define BV_IR_STAT_MODE_ALLOWED__VFIR           0x0
-#define BV_IR_STAT_MODE_ALLOWED__FIR            0x1
-#define BV_IR_STAT_MODE_ALLOWED__MIR            0x2
-#define BV_IR_STAT_MODE_ALLOWED__SIR            0x3
-#define BF_IR_STAT_MODE_ALLOWED(v)              (((v) << 29) & 0x60000000)
-#define BF_IR_STAT_MODE_ALLOWED_V(v)            ((BV_IR_STAT_MODE_ALLOWED__##v << 29) & 0x60000000)
-#define BP_IR_STAT_ANY_IRQ                      28
-#define BM_IR_STAT_ANY_IRQ                      0x10000000
-#define BV_IR_STAT_ANY_IRQ__NO_REQUEST          0x0
-#define BV_IR_STAT_ANY_IRQ__REQUEST             0x1
-#define BF_IR_STAT_ANY_IRQ(v)                   (((v) << 28) & 0x10000000)
-#define BF_IR_STAT_ANY_IRQ_V(v)                 ((BV_IR_STAT_ANY_IRQ__##v << 28) & 0x10000000)
-#define BP_IR_STAT_RXABORT_SUMMARY              22
-#define BM_IR_STAT_RXABORT_SUMMARY              0x400000
-#define BV_IR_STAT_RXABORT_SUMMARY__NO_REQUEST  0x0
-#define BV_IR_STAT_RXABORT_SUMMARY__REQUEST     0x1
-#define BF_IR_STAT_RXABORT_SUMMARY(v)           (((v) << 22) & 0x400000)
-#define BF_IR_STAT_RXABORT_SUMMARY_V(v)         ((BV_IR_STAT_RXABORT_SUMMARY__##v << 22) & 0x400000)
-#define BP_IR_STAT_SPEED_SUMMARY                21
-#define BM_IR_STAT_SPEED_SUMMARY                0x200000
-#define BV_IR_STAT_SPEED_SUMMARY__NO_REQUEST    0x0
-#define BV_IR_STAT_SPEED_SUMMARY__REQUEST       0x1
-#define BF_IR_STAT_SPEED_SUMMARY(v)             (((v) << 21) & 0x200000)
-#define BF_IR_STAT_SPEED_SUMMARY_V(v)           ((BV_IR_STAT_SPEED_SUMMARY__##v << 21) & 0x200000)
-#define BP_IR_STAT_RXOF_SUMMARY                 20
-#define BM_IR_STAT_RXOF_SUMMARY                 0x100000
-#define BV_IR_STAT_RXOF_SUMMARY__NO_REQUEST     0x0
-#define BV_IR_STAT_RXOF_SUMMARY__REQUEST        0x1
-#define BF_IR_STAT_RXOF_SUMMARY(v)              (((v) << 20) & 0x100000)
-#define BF_IR_STAT_RXOF_SUMMARY_V(v)            ((BV_IR_STAT_RXOF_SUMMARY__##v << 20) & 0x100000)
-#define BP_IR_STAT_TXUF_SUMMARY                 19
-#define BM_IR_STAT_TXUF_SUMMARY                 0x80000
-#define BV_IR_STAT_TXUF_SUMMARY__NO_REQUEST     0x0
-#define BV_IR_STAT_TXUF_SUMMARY__REQUEST        0x1
-#define BF_IR_STAT_TXUF_SUMMARY(v)              (((v) << 19) & 0x80000)
-#define BF_IR_STAT_TXUF_SUMMARY_V(v)            ((BV_IR_STAT_TXUF_SUMMARY__##v << 19) & 0x80000)
-#define BP_IR_STAT_TC_SUMMARY                   18
-#define BM_IR_STAT_TC_SUMMARY                   0x40000
-#define BV_IR_STAT_TC_SUMMARY__NO_REQUEST       0x0
-#define BV_IR_STAT_TC_SUMMARY__REQUEST          0x1
-#define BF_IR_STAT_TC_SUMMARY(v)                (((v) << 18) & 0x40000)
-#define BF_IR_STAT_TC_SUMMARY_V(v)              ((BV_IR_STAT_TC_SUMMARY__##v << 18) & 0x40000)
-#define BP_IR_STAT_RX_SUMMARY                   17
-#define BM_IR_STAT_RX_SUMMARY                   0x20000
-#define BV_IR_STAT_RX_SUMMARY__NO_REQUEST       0x0
-#define BV_IR_STAT_RX_SUMMARY__REQUEST          0x1
-#define BF_IR_STAT_RX_SUMMARY(v)                (((v) << 17) & 0x20000)
-#define BF_IR_STAT_RX_SUMMARY_V(v)              ((BV_IR_STAT_RX_SUMMARY__##v << 17) & 0x20000)
-#define BP_IR_STAT_TX_SUMMARY                   16
-#define BM_IR_STAT_TX_SUMMARY                   0x10000
-#define BV_IR_STAT_TX_SUMMARY__NO_REQUEST       0x0
-#define BV_IR_STAT_TX_SUMMARY__REQUEST          0x1
-#define BF_IR_STAT_TX_SUMMARY(v)                (((v) << 16) & 0x10000)
-#define BF_IR_STAT_TX_SUMMARY_V(v)              ((BV_IR_STAT_TX_SUMMARY__##v << 16) & 0x10000)
-#define BP_IR_STAT_MEDIA_BUSY                   2
-#define BM_IR_STAT_MEDIA_BUSY                   0x4
-#define BF_IR_STAT_MEDIA_BUSY(v)                (((v) << 2) & 0x4)
-#define BP_IR_STAT_RX_ACTIVE                    1
-#define BM_IR_STAT_RX_ACTIVE                    0x2
-#define BF_IR_STAT_RX_ACTIVE(v)                 (((v) << 1) & 0x2)
-#define BP_IR_STAT_TX_ACTIVE                    0
-#define BM_IR_STAT_TX_ACTIVE                    0x1
-#define BF_IR_STAT_TX_ACTIVE(v)                 (((v) << 0) & 0x1)
-
-/**
- * Register: HW_IR_TCCTRL
- * Address: 0x70
- * SCT: yes
-*/
-#define HW_IR_TCCTRL                (*(volatile unsigned long *)(REGS_IR_BASE + 0x70 + 0x0))
-#define HW_IR_TCCTRL_SET            (*(volatile unsigned long *)(REGS_IR_BASE + 0x70 + 0x4))
-#define HW_IR_TCCTRL_CLR            (*(volatile unsigned long *)(REGS_IR_BASE + 0x70 + 0x8))
-#define HW_IR_TCCTRL_TOG            (*(volatile unsigned long *)(REGS_IR_BASE + 0x70 + 0xc))
-#define BP_IR_TCCTRL_INIT           31
-#define BM_IR_TCCTRL_INIT           0x80000000
-#define BF_IR_TCCTRL_INIT(v)        (((v) << 31) & 0x80000000)
-#define BP_IR_TCCTRL_GO             30
-#define BM_IR_TCCTRL_GO             0x40000000
-#define BF_IR_TCCTRL_GO(v)          (((v) << 30) & 0x40000000)
-#define BP_IR_TCCTRL_BUSY           29
-#define BM_IR_TCCTRL_BUSY           0x20000000
-#define BF_IR_TCCTRL_BUSY(v)        (((v) << 29) & 0x20000000)
-#define BP_IR_TCCTRL_TEMIC          24
-#define BM_IR_TCCTRL_TEMIC          0x1000000
-#define BV_IR_TCCTRL_TEMIC__LOW     0x0
-#define BV_IR_TCCTRL_TEMIC__HIGH    0x1
-#define BF_IR_TCCTRL_TEMIC(v)       (((v) << 24) & 0x1000000)
-#define BF_IR_TCCTRL_TEMIC_V(v)     ((BV_IR_TCCTRL_TEMIC__##v << 24) & 0x1000000)
-#define BP_IR_TCCTRL_EXT_DATA       16
-#define BM_IR_TCCTRL_EXT_DATA       0xff0000
-#define BF_IR_TCCTRL_EXT_DATA(v)    (((v) << 16) & 0xff0000)
-#define BP_IR_TCCTRL_DATA           8
-#define BM_IR_TCCTRL_DATA           0xff00
-#define BF_IR_TCCTRL_DATA(v)        (((v) << 8) & 0xff00)
-#define BP_IR_TCCTRL_ADDR           5
-#define BM_IR_TCCTRL_ADDR           0xe0
-#define BF_IR_TCCTRL_ADDR(v)        (((v) << 5) & 0xe0)
-#define BP_IR_TCCTRL_INDX           1
-#define BM_IR_TCCTRL_INDX           0x1e
-#define BF_IR_TCCTRL_INDX(v)        (((v) << 1) & 0x1e)
-#define BP_IR_TCCTRL_C              0
-#define BM_IR_TCCTRL_C              0x1
-#define BF_IR_TCCTRL_C(v)           (((v) << 0) & 0x1)
-
-/**
- * Register: HW_IR_SI_READ
- * Address: 0x80
- * SCT: no
-*/
-#define HW_IR_SI_READ           (*(volatile unsigned long *)(REGS_IR_BASE + 0x80))
-#define BP_IR_SI_READ_ABORT     8
-#define BM_IR_SI_READ_ABORT     0x100
-#define BF_IR_SI_READ_ABORT(v)  (((v) << 8) & 0x100)
-#define BP_IR_SI_READ_DATA      0
-#define BM_IR_SI_READ_DATA      0xff
-#define BF_IR_SI_READ_DATA(v)   (((v) << 0) & 0xff)
-
-/**
- * Register: HW_IR_DEBUG
- * Address: 0x90
- * SCT: no
-*/
-#define HW_IR_DEBUG                 (*(volatile unsigned long *)(REGS_IR_BASE + 0x90))
-#define BP_IR_DEBUG_TXDMAKICK       5
-#define BM_IR_DEBUG_TXDMAKICK       0x20
-#define BF_IR_DEBUG_TXDMAKICK(v)    (((v) << 5) & 0x20)
-#define BP_IR_DEBUG_RXDMAKICK       4
-#define BM_IR_DEBUG_RXDMAKICK       0x10
-#define BF_IR_DEBUG_RXDMAKICK(v)    (((v) << 4) & 0x10)
-#define BP_IR_DEBUG_TXDMAEND        3
-#define BM_IR_DEBUG_TXDMAEND        0x8
-#define BF_IR_DEBUG_TXDMAEND(v)     (((v) << 3) & 0x8)
-#define BP_IR_DEBUG_RXDMAEND        2
-#define BM_IR_DEBUG_RXDMAEND        0x4
-#define BF_IR_DEBUG_RXDMAEND(v)     (((v) << 2) & 0x4)
-#define BP_IR_DEBUG_TXDMAREQ        1
-#define BM_IR_DEBUG_TXDMAREQ        0x2
-#define BF_IR_DEBUG_TXDMAREQ(v)     (((v) << 1) & 0x2)
-#define BP_IR_DEBUG_RXDMAREQ        0
-#define BM_IR_DEBUG_RXDMAREQ        0x1
-#define BF_IR_DEBUG_RXDMAREQ(v)     (((v) << 0) & 0x1)
-
-#endif /* __HEADERGEN__STMP3600__IR__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-lcdif.h b/firmware/target/arm/imx233/regs/stmp3600/regs-lcdif.h
deleted file mode 100644
index dc01144d28..0000000000
--- a/firmware/target/arm/imx233/regs/stmp3600/regs-lcdif.h
+++ /dev/null
@@ -1,167 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3600:2.3.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__STMP3600__LCDIF__H__
-#define __HEADERGEN__STMP3600__LCDIF__H__
-
-#define REGS_LCDIF_BASE (0x80060000)
-
-#define REGS_LCDIF_VERSION "2.3.0"
-
-/**
- * Register: HW_LCDIF_CTRL
- * Address: 0
- * SCT: yes
-*/
-#define HW_LCDIF_CTRL                               (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x0 + 0x0))
-#define HW_LCDIF_CTRL_SET                           (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x0 + 0x4))
-#define HW_LCDIF_CTRL_CLR                           (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x0 + 0x8))
-#define HW_LCDIF_CTRL_TOG                           (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x0 + 0xc))
-#define BP_LCDIF_CTRL_SFTRST                        31
-#define BM_LCDIF_CTRL_SFTRST                        0x80000000
-#define BF_LCDIF_CTRL_SFTRST(v)                     (((v) << 31) & 0x80000000)
-#define BP_LCDIF_CTRL_CLKGATE                       30
-#define BM_LCDIF_CTRL_CLKGATE                       0x40000000
-#define BF_LCDIF_CTRL_CLKGATE(v)                    (((v) << 30) & 0x40000000)
-#define BP_LCDIF_CTRL_PRESENT                       29
-#define BM_LCDIF_CTRL_PRESENT                       0x20000000
-#define BF_LCDIF_CTRL_PRESENT(v)                    (((v) << 29) & 0x20000000)
-#define BP_LCDIF_CTRL_BUSY_ENABLE                   25
-#define BM_LCDIF_CTRL_BUSY_ENABLE                   0x2000000
-#define BV_LCDIF_CTRL_BUSY_ENABLE__BUSY_DISABLED    0x0
-#define BV_LCDIF_CTRL_BUSY_ENABLE__BUSY_ENABLED     0x1
-#define BF_LCDIF_CTRL_BUSY_ENABLE(v)                (((v) << 25) & 0x2000000)
-#define BF_LCDIF_CTRL_BUSY_ENABLE_V(v)              ((BV_LCDIF_CTRL_BUSY_ENABLE__##v << 25) & 0x2000000)
-#define BP_LCDIF_CTRL_FIFO_STATUS                   24
-#define BM_LCDIF_CTRL_FIFO_STATUS                   0x1000000
-#define BV_LCDIF_CTRL_FIFO_STATUS__FIFO_FULL        0x0
-#define BV_LCDIF_CTRL_FIFO_STATUS__FIFO_OK          0x1
-#define BF_LCDIF_CTRL_FIFO_STATUS(v)                (((v) << 24) & 0x1000000)
-#define BF_LCDIF_CTRL_FIFO_STATUS_V(v)              ((BV_LCDIF_CTRL_FIFO_STATUS__##v << 24) & 0x1000000)
-#define BP_LCDIF_CTRL_DMA_REQ                       23
-#define BM_LCDIF_CTRL_DMA_REQ                       0x800000
-#define BF_LCDIF_CTRL_DMA_REQ(v)                    (((v) << 23) & 0x800000)
-#define BP_LCDIF_CTRL_DATA_SWIZZLE                  21
-#define BM_LCDIF_CTRL_DATA_SWIZZLE                  0x600000
-#define BV_LCDIF_CTRL_DATA_SWIZZLE__NO_SWAP         0x0
-#define BV_LCDIF_CTRL_DATA_SWIZZLE__LITTLE_ENDIAN   0x0
-#define BV_LCDIF_CTRL_DATA_SWIZZLE__BIG_ENDIAN_SWAP 0x1
-#define BV_LCDIF_CTRL_DATA_SWIZZLE__SWAP_ALL_BYTES  0x1
-#define BV_LCDIF_CTRL_DATA_SWIZZLE__HWD_SWAP        0x2
-#define BV_LCDIF_CTRL_DATA_SWIZZLE__HWD_BYTE_SWAP   0x3
-#define BF_LCDIF_CTRL_DATA_SWIZZLE(v)               (((v) << 21) & 0x600000)
-#define BF_LCDIF_CTRL_DATA_SWIZZLE_V(v)             ((BV_LCDIF_CTRL_DATA_SWIZZLE__##v << 21) & 0x600000)
-#define BP_LCDIF_CTRL_RESET                         20
-#define BM_LCDIF_CTRL_RESET                         0x100000
-#define BV_LCDIF_CTRL_RESET__LCDRESET_LOW           0x0
-#define BV_LCDIF_CTRL_RESET__LCDRESET_HIGH          0x1
-#define BF_LCDIF_CTRL_RESET(v)                      (((v) << 20) & 0x100000)
-#define BF_LCDIF_CTRL_RESET_V(v)                    ((BV_LCDIF_CTRL_RESET__##v << 20) & 0x100000)
-#define BP_LCDIF_CTRL_MODE86                        19
-#define BM_LCDIF_CTRL_MODE86                        0x80000
-#define BV_LCDIF_CTRL_MODE86__8080_MODE             0x0
-#define BV_LCDIF_CTRL_MODE86__6800_MODE             0x1
-#define BF_LCDIF_CTRL_MODE86(v)                     (((v) << 19) & 0x80000)
-#define BF_LCDIF_CTRL_MODE86_V(v)                   ((BV_LCDIF_CTRL_MODE86__##v << 19) & 0x80000)
-#define BP_LCDIF_CTRL_DATA_SELECT                   18
-#define BM_LCDIF_CTRL_DATA_SELECT                   0x40000
-#define BV_LCDIF_CTRL_DATA_SELECT__CMD_MODE         0x0
-#define BV_LCDIF_CTRL_DATA_SELECT__DATA_MODE        0x1
-#define BF_LCDIF_CTRL_DATA_SELECT(v)                (((v) << 18) & 0x40000)
-#define BF_LCDIF_CTRL_DATA_SELECT_V(v)              ((BV_LCDIF_CTRL_DATA_SELECT__##v << 18) & 0x40000)
-#define BP_LCDIF_CTRL_WORD_LENGTH                   17
-#define BM_LCDIF_CTRL_WORD_LENGTH                   0x20000
-#define BV_LCDIF_CTRL_WORD_LENGTH__16_BIT           0x0
-#define BV_LCDIF_CTRL_WORD_LENGTH__8_BIT            0x1
-#define BF_LCDIF_CTRL_WORD_LENGTH(v)                (((v) << 17) & 0x20000)
-#define BF_LCDIF_CTRL_WORD_LENGTH_V(v)              ((BV_LCDIF_CTRL_WORD_LENGTH__##v << 17) & 0x20000)
-#define BP_LCDIF_CTRL_RUN                           16
-#define BM_LCDIF_CTRL_RUN                           0x10000
-#define BF_LCDIF_CTRL_RUN(v)                        (((v) << 16) & 0x10000)
-#define BP_LCDIF_CTRL_COUNT                         0
-#define BM_LCDIF_CTRL_COUNT                         0xffff
-#define BF_LCDIF_CTRL_COUNT(v)                      (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_LCDIF_TIMING
- * Address: 0x10
- * SCT: no
-*/
-#define HW_LCDIF_TIMING                 (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x10))
-#define BP_LCDIF_TIMING_CMD_HOLD        24
-#define BM_LCDIF_TIMING_CMD_HOLD        0xff000000
-#define BF_LCDIF_TIMING_CMD_HOLD(v)     (((v) << 24) & 0xff000000)
-#define BP_LCDIF_TIMING_CMD_SETUP       16
-#define BM_LCDIF_TIMING_CMD_SETUP       0xff0000
-#define BF_LCDIF_TIMING_CMD_SETUP(v)    (((v) << 16) & 0xff0000)
-#define BP_LCDIF_TIMING_DATA_HOLD       8
-#define BM_LCDIF_TIMING_DATA_HOLD       0xff00
-#define BF_LCDIF_TIMING_DATA_HOLD(v)    (((v) << 8) & 0xff00)
-#define BP_LCDIF_TIMING_DATA_SETUP      0
-#define BM_LCDIF_TIMING_DATA_SETUP      0xff
-#define BF_LCDIF_TIMING_DATA_SETUP(v)   (((v) << 0) & 0xff)
-
-/**
- * Register: HW_LCDIF_DATA
- * Address: 0x20
- * SCT: no
-*/
-#define HW_LCDIF_DATA               (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x20))
-#define BP_LCDIF_DATA_DATA_THREE    24
-#define BM_LCDIF_DATA_DATA_THREE    0xff000000
-#define BF_LCDIF_DATA_DATA_THREE(v) (((v) << 24) & 0xff000000)
-#define BP_LCDIF_DATA_DATA_TWO      16
-#define BM_LCDIF_DATA_DATA_TWO      0xff0000
-#define BF_LCDIF_DATA_DATA_TWO(v)   (((v) << 16) & 0xff0000)
-#define BP_LCDIF_DATA_DATA_ONE      8
-#define BM_LCDIF_DATA_DATA_ONE      0xff00
-#define BF_LCDIF_DATA_DATA_ONE(v)   (((v) << 8) & 0xff00)
-#define BP_LCDIF_DATA_DATA_ZERO     0
-#define BM_LCDIF_DATA_DATA_ZERO     0xff
-#define BF_LCDIF_DATA_DATA_ZERO(v)  (((v) << 0) & 0xff)
-
-/**
- * Register: HW_LCDIF_DEBUG
- * Address: 0x30
- * SCT: no
-*/
-#define HW_LCDIF_DEBUG                      (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x30))
-#define BP_LCDIF_DEBUG_BUSY                 27
-#define BM_LCDIF_DEBUG_BUSY                 0x8000000
-#define BF_LCDIF_DEBUG_BUSY(v)              (((v) << 27) & 0x8000000)
-#define BP_LCDIF_DEBUG_LAST_SUBWORD         26
-#define BM_LCDIF_DEBUG_LAST_SUBWORD         0x4000000
-#define BF_LCDIF_DEBUG_LAST_SUBWORD(v)      (((v) << 26) & 0x4000000)
-#define BP_LCDIF_DEBUG_SUBWORD_POSITION     24
-#define BM_LCDIF_DEBUG_SUBWORD_POSITION     0x3000000
-#define BF_LCDIF_DEBUG_SUBWORD_POSITION(v)  (((v) << 24) & 0x3000000)
-#define BP_LCDIF_DEBUG_EMPTY_WORD           23
-#define BM_LCDIF_DEBUG_EMPTY_WORD           0x800000
-#define BF_LCDIF_DEBUG_EMPTY_WORD(v)        (((v) << 23) & 0x800000)
-#define BP_LCDIF_DEBUG_STATE                16
-#define BM_LCDIF_DEBUG_STATE                0x7f0000
-#define BF_LCDIF_DEBUG_STATE(v)             (((v) << 16) & 0x7f0000)
-#define BP_LCDIF_DEBUG_DATA_COUNT           0
-#define BM_LCDIF_DEBUG_DATA_COUNT           0xffff
-#define BF_LCDIF_DEBUG_DATA_COUNT(v)        (((v) << 0) & 0xffff)
-
-#endif /* __HEADERGEN__STMP3600__LCDIF__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-lradc.h b/firmware/target/arm/imx233/regs/stmp3600/regs-lradc.h
deleted file mode 100644
index 28113e296f..0000000000
--- a/firmware/target/arm/imx233/regs/stmp3600/regs-lradc.h
+++ /dev/null
@@ -1,572 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3600:2.3.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__STMP3600__LRADC__H__
-#define __HEADERGEN__STMP3600__LRADC__H__
-
-#define REGS_LRADC_BASE (0x80050000)
-
-#define REGS_LRADC_VERSION "2.3.0"
-
-/**
- * Register: HW_LRADC_CTRL0
- * Address: 0
- * SCT: yes
-*/
-#define HW_LRADC_CTRL0                          (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x0 + 0x0))
-#define HW_LRADC_CTRL0_SET                      (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x0 + 0x4))
-#define HW_LRADC_CTRL0_CLR                      (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x0 + 0x8))
-#define HW_LRADC_CTRL0_TOG                      (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x0 + 0xc))
-#define BP_LRADC_CTRL0_SFTRST                   31
-#define BM_LRADC_CTRL0_SFTRST                   0x80000000
-#define BF_LRADC_CTRL0_SFTRST(v)                (((v) << 31) & 0x80000000)
-#define BP_LRADC_CTRL0_CLKGATE                  30
-#define BM_LRADC_CTRL0_CLKGATE                  0x40000000
-#define BF_LRADC_CTRL0_CLKGATE(v)               (((v) << 30) & 0x40000000)
-#define BP_LRADC_CTRL0_ONCHIP_GROUNDREF         21
-#define BM_LRADC_CTRL0_ONCHIP_GROUNDREF         0x200000
-#define BV_LRADC_CTRL0_ONCHIP_GROUNDREF__OFF    0x0
-#define BV_LRADC_CTRL0_ONCHIP_GROUNDREF__ON     0x1
-#define BF_LRADC_CTRL0_ONCHIP_GROUNDREF(v)      (((v) << 21) & 0x200000)
-#define BF_LRADC_CTRL0_ONCHIP_GROUNDREF_V(v)    ((BV_LRADC_CTRL0_ONCHIP_GROUNDREF__##v << 21) & 0x200000)
-#define BP_LRADC_CTRL0_TOUCH_DETECT_ENABLE      20
-#define BM_LRADC_CTRL0_TOUCH_DETECT_ENABLE      0x100000
-#define BV_LRADC_CTRL0_TOUCH_DETECT_ENABLE__OFF 0x0
-#define BV_LRADC_CTRL0_TOUCH_DETECT_ENABLE__ON  0x1
-#define BF_LRADC_CTRL0_TOUCH_DETECT_ENABLE(v)   (((v) << 20) & 0x100000)
-#define BF_LRADC_CTRL0_TOUCH_DETECT_ENABLE_V(v) ((BV_LRADC_CTRL0_TOUCH_DETECT_ENABLE__##v << 20) & 0x100000)
-#define BP_LRADC_CTRL0_YMINUS_ENABLE            19
-#define BM_LRADC_CTRL0_YMINUS_ENABLE            0x80000
-#define BV_LRADC_CTRL0_YMINUS_ENABLE__OFF       0x0
-#define BV_LRADC_CTRL0_YMINUS_ENABLE__ON        0x1
-#define BF_LRADC_CTRL0_YMINUS_ENABLE(v)         (((v) << 19) & 0x80000)
-#define BF_LRADC_CTRL0_YMINUS_ENABLE_V(v)       ((BV_LRADC_CTRL0_YMINUS_ENABLE__##v << 19) & 0x80000)
-#define BP_LRADC_CTRL0_XMINUS_ENABLE            18
-#define BM_LRADC_CTRL0_XMINUS_ENABLE            0x40000
-#define BV_LRADC_CTRL0_XMINUS_ENABLE__OFF       0x0
-#define BV_LRADC_CTRL0_XMINUS_ENABLE__ON        0x1
-#define BF_LRADC_CTRL0_XMINUS_ENABLE(v)         (((v) << 18) & 0x40000)
-#define BF_LRADC_CTRL0_XMINUS_ENABLE_V(v)       ((BV_LRADC_CTRL0_XMINUS_ENABLE__##v << 18) & 0x40000)
-#define BP_LRADC_CTRL0_YPLUS_ENABLE             17
-#define BM_LRADC_CTRL0_YPLUS_ENABLE             0x20000
-#define BV_LRADC_CTRL0_YPLUS_ENABLE__OFF        0x0
-#define BV_LRADC_CTRL0_YPLUS_ENABLE__ON         0x1
-#define BF_LRADC_CTRL0_YPLUS_ENABLE(v)          (((v) << 17) & 0x20000)
-#define BF_LRADC_CTRL0_YPLUS_ENABLE_V(v)        ((BV_LRADC_CTRL0_YPLUS_ENABLE__##v << 17) & 0x20000)
-#define BP_LRADC_CTRL0_XPLUS_ENABLE             16
-#define BM_LRADC_CTRL0_XPLUS_ENABLE             0x10000
-#define BV_LRADC_CTRL0_XPLUS_ENABLE__OFF        0x0
-#define BV_LRADC_CTRL0_XPLUS_ENABLE__ON         0x1
-#define BF_LRADC_CTRL0_XPLUS_ENABLE(v)          (((v) << 16) & 0x10000)
-#define BF_LRADC_CTRL0_XPLUS_ENABLE_V(v)        ((BV_LRADC_CTRL0_XPLUS_ENABLE__##v << 16) & 0x10000)
-#define BP_LRADC_CTRL0_SCHEDULE                 0
-#define BM_LRADC_CTRL0_SCHEDULE                 0xff
-#define BF_LRADC_CTRL0_SCHEDULE(v)              (((v) << 0) & 0xff)
-
-/**
- * Register: HW_LRADC_CTRL1
- * Address: 0x10
- * SCT: yes
-*/
-#define HW_LRADC_CTRL1                              (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x10 + 0x0))
-#define HW_LRADC_CTRL1_SET                          (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x10 + 0x4))
-#define HW_LRADC_CTRL1_CLR                          (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x10 + 0x8))
-#define HW_LRADC_CTRL1_TOG                          (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x10 + 0xc))
-#define BP_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN          24
-#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN          0x1000000
-#define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN__DISABLE 0x0
-#define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN__ENABLE  0x1
-#define BF_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN(v)       (((v) << 24) & 0x1000000)
-#define BF_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN_V(v)     ((BV_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN__##v << 24) & 0x1000000)
-#define BP_LRADC_CTRL1_LRADC7_IRQ_EN                23
-#define BM_LRADC_CTRL1_LRADC7_IRQ_EN                0x800000
-#define BV_LRADC_CTRL1_LRADC7_IRQ_EN__DISABLE       0x0
-#define BV_LRADC_CTRL1_LRADC7_IRQ_EN__ENABLE        0x1
-#define BF_LRADC_CTRL1_LRADC7_IRQ_EN(v)             (((v) << 23) & 0x800000)
-#define BF_LRADC_CTRL1_LRADC7_IRQ_EN_V(v)           ((BV_LRADC_CTRL1_LRADC7_IRQ_EN__##v << 23) & 0x800000)
-#define BP_LRADC_CTRL1_LRADC6_IRQ_EN                22
-#define BM_LRADC_CTRL1_LRADC6_IRQ_EN                0x400000
-#define BV_LRADC_CTRL1_LRADC6_IRQ_EN__DISABLE       0x0
-#define BV_LRADC_CTRL1_LRADC6_IRQ_EN__ENABLE        0x1
-#define BF_LRADC_CTRL1_LRADC6_IRQ_EN(v)             (((v) << 22) & 0x400000)
-#define BF_LRADC_CTRL1_LRADC6_IRQ_EN_V(v)           ((BV_LRADC_CTRL1_LRADC6_IRQ_EN__##v << 22) & 0x400000)
-#define BP_LRADC_CTRL1_LRADC5_IRQ_EN                21
-#define BM_LRADC_CTRL1_LRADC5_IRQ_EN                0x200000
-#define BV_LRADC_CTRL1_LRADC5_IRQ_EN__DISABLE       0x0
-#define BV_LRADC_CTRL1_LRADC5_IRQ_EN__ENABLE        0x1
-#define BF_LRADC_CTRL1_LRADC5_IRQ_EN(v)             (((v) << 21) & 0x200000)
-#define BF_LRADC_CTRL1_LRADC5_IRQ_EN_V(v)           ((BV_LRADC_CTRL1_LRADC5_IRQ_EN__##v << 21) & 0x200000)
-#define BP_LRADC_CTRL1_LRADC4_IRQ_EN                20
-#define BM_LRADC_CTRL1_LRADC4_IRQ_EN                0x100000
-#define BV_LRADC_CTRL1_LRADC4_IRQ_EN__DISABLE       0x0
-#define BV_LRADC_CTRL1_LRADC4_IRQ_EN__ENABLE        0x1
-#define BF_LRADC_CTRL1_LRADC4_IRQ_EN(v)             (((v) << 20) & 0x100000)
-#define BF_LRADC_CTRL1_LRADC4_IRQ_EN_V(v)           ((BV_LRADC_CTRL1_LRADC4_IRQ_EN__##v << 20) & 0x100000)
-#define BP_LRADC_CTRL1_LRADC3_IRQ_EN                19
-#define BM_LRADC_CTRL1_LRADC3_IRQ_EN                0x80000
-#define BV_LRADC_CTRL1_LRADC3_IRQ_EN__DISABLE       0x0
-#define BV_LRADC_CTRL1_LRADC3_IRQ_EN__ENABLE        0x1
-#define BF_LRADC_CTRL1_LRADC3_IRQ_EN(v)             (((v) << 19) & 0x80000)
-#define BF_LRADC_CTRL1_LRADC3_IRQ_EN_V(v)           ((BV_LRADC_CTRL1_LRADC3_IRQ_EN__##v << 19) & 0x80000)
-#define BP_LRADC_CTRL1_LRADC2_IRQ_EN                18
-#define BM_LRADC_CTRL1_LRADC2_IRQ_EN                0x40000
-#define BV_LRADC_CTRL1_LRADC2_IRQ_EN__DISABLE       0x0
-#define BV_LRADC_CTRL1_LRADC2_IRQ_EN__ENABLE        0x1
-#define BF_LRADC_CTRL1_LRADC2_IRQ_EN(v)             (((v) << 18) & 0x40000)
-#define BF_LRADC_CTRL1_LRADC2_IRQ_EN_V(v)           ((BV_LRADC_CTRL1_LRADC2_IRQ_EN__##v << 18) & 0x40000)
-#define BP_LRADC_CTRL1_LRADC1_IRQ_EN                17
-#define BM_LRADC_CTRL1_LRADC1_IRQ_EN                0x20000
-#define BV_LRADC_CTRL1_LRADC1_IRQ_EN__DISABLE       0x0
-#define BV_LRADC_CTRL1_LRADC1_IRQ_EN__ENABLE        0x1
-#define BF_LRADC_CTRL1_LRADC1_IRQ_EN(v)             (((v) << 17) & 0x20000)
-#define BF_LRADC_CTRL1_LRADC1_IRQ_EN_V(v)           ((BV_LRADC_CTRL1_LRADC1_IRQ_EN__##v << 17) & 0x20000)
-#define BP_LRADC_CTRL1_LRADC0_IRQ_EN                16
-#define BM_LRADC_CTRL1_LRADC0_IRQ_EN                0x10000
-#define BV_LRADC_CTRL1_LRADC0_IRQ_EN__DISABLE       0x0
-#define BV_LRADC_CTRL1_LRADC0_IRQ_EN__ENABLE        0x1
-#define BF_LRADC_CTRL1_LRADC0_IRQ_EN(v)             (((v) << 16) & 0x10000)
-#define BF_LRADC_CTRL1_LRADC0_IRQ_EN_V(v)           ((BV_LRADC_CTRL1_LRADC0_IRQ_EN__##v << 16) & 0x10000)
-#define BP_LRADC_CTRL1_TOUCH_DETECT_IRQ             8
-#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ             0x100
-#define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ__CLEAR      0x0
-#define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ__PENDING    0x1
-#define BF_LRADC_CTRL1_TOUCH_DETECT_IRQ(v)          (((v) << 8) & 0x100)
-#define BF_LRADC_CTRL1_TOUCH_DETECT_IRQ_V(v)        ((BV_LRADC_CTRL1_TOUCH_DETECT_IRQ__##v << 8) & 0x100)
-#define BP_LRADC_CTRL1_LRADC7_IRQ                   7
-#define BM_LRADC_CTRL1_LRADC7_IRQ                   0x80
-#define BV_LRADC_CTRL1_LRADC7_IRQ__CLEAR            0x0
-#define BV_LRADC_CTRL1_LRADC7_IRQ__PENDING          0x1
-#define BF_LRADC_CTRL1_LRADC7_IRQ(v)                (((v) << 7) & 0x80)
-#define BF_LRADC_CTRL1_LRADC7_IRQ_V(v)              ((BV_LRADC_CTRL1_LRADC7_IRQ__##v << 7) & 0x80)
-#define BP_LRADC_CTRL1_LRADC6_IRQ                   6
-#define BM_LRADC_CTRL1_LRADC6_IRQ                   0x40
-#define BV_LRADC_CTRL1_LRADC6_IRQ__CLEAR            0x0
-#define BV_LRADC_CTRL1_LRADC6_IRQ__PENDING          0x1
-#define BF_LRADC_CTRL1_LRADC6_IRQ(v)                (((v) << 6) & 0x40)
-#define BF_LRADC_CTRL1_LRADC6_IRQ_V(v)              ((BV_LRADC_CTRL1_LRADC6_IRQ__##v << 6) & 0x40)
-#define BP_LRADC_CTRL1_LRADC5_IRQ                   5
-#define BM_LRADC_CTRL1_LRADC5_IRQ                   0x20
-#define BV_LRADC_CTRL1_LRADC5_IRQ__CLEAR            0x0
-#define BV_LRADC_CTRL1_LRADC5_IRQ__PENDING          0x1
-#define BF_LRADC_CTRL1_LRADC5_IRQ(v)                (((v) << 5) & 0x20)
-#define BF_LRADC_CTRL1_LRADC5_IRQ_V(v)              ((BV_LRADC_CTRL1_LRADC5_IRQ__##v << 5) & 0x20)
-#define BP_LRADC_CTRL1_LRADC4_IRQ                   4
-#define BM_LRADC_CTRL1_LRADC4_IRQ                   0x10
-#define BV_LRADC_CTRL1_LRADC4_IRQ__CLEAR            0x0
-#define BV_LRADC_CTRL1_LRADC4_IRQ__PENDING          0x1
-#define BF_LRADC_CTRL1_LRADC4_IRQ(v)                (((v) << 4) & 0x10)
-#define BF_LRADC_CTRL1_LRADC4_IRQ_V(v)              ((BV_LRADC_CTRL1_LRADC4_IRQ__##v << 4) & 0x10)
-#define BP_LRADC_CTRL1_LRADC3_IRQ                   3
-#define BM_LRADC_CTRL1_LRADC3_IRQ                   0x8
-#define BV_LRADC_CTRL1_LRADC3_IRQ__CLEAR            0x0
-#define BV_LRADC_CTRL1_LRADC3_IRQ__PENDING          0x1
-#define BF_LRADC_CTRL1_LRADC3_IRQ(v)                (((v) << 3) & 0x8)
-#define BF_LRADC_CTRL1_LRADC3_IRQ_V(v)              ((BV_LRADC_CTRL1_LRADC3_IRQ__##v << 3) & 0x8)
-#define BP_LRADC_CTRL1_LRADC2_IRQ                   2
-#define BM_LRADC_CTRL1_LRADC2_IRQ                   0x4
-#define BV_LRADC_CTRL1_LRADC2_IRQ__CLEAR            0x0
-#define BV_LRADC_CTRL1_LRADC2_IRQ__PENDING          0x1
-#define BF_LRADC_CTRL1_LRADC2_IRQ(v)                (((v) << 2) & 0x4)
-#define BF_LRADC_CTRL1_LRADC2_IRQ_V(v)              ((BV_LRADC_CTRL1_LRADC2_IRQ__##v << 2) & 0x4)
-#define BP_LRADC_CTRL1_LRADC1_IRQ                   1
-#define BM_LRADC_CTRL1_LRADC1_IRQ                   0x2
-#define BV_LRADC_CTRL1_LRADC1_IRQ__CLEAR            0x0
-#define BV_LRADC_CTRL1_LRADC1_IRQ__PENDING          0x1
-#define BF_LRADC_CTRL1_LRADC1_IRQ(v)                (((v) << 1) & 0x2)
-#define BF_LRADC_CTRL1_LRADC1_IRQ_V(v)              ((BV_LRADC_CTRL1_LRADC1_IRQ__##v << 1) & 0x2)
-#define BP_LRADC_CTRL1_LRADC0_IRQ                   0
-#define BM_LRADC_CTRL1_LRADC0_IRQ                   0x1
-#define BV_LRADC_CTRL1_LRADC0_IRQ__CLEAR            0x0
-#define BV_LRADC_CTRL1_LRADC0_IRQ__PENDING          0x1
-#define BF_LRADC_CTRL1_LRADC0_IRQ(v)                (((v) << 0) & 0x1)
-#define BF_LRADC_CTRL1_LRADC0_IRQ_V(v)              ((BV_LRADC_CTRL1_LRADC0_IRQ__##v << 0) & 0x1)
-
-/**
- * Register: HW_LRADC_CTRL2
- * Address: 0x20
- * SCT: yes
-*/
-#define HW_LRADC_CTRL2                                  (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x20 + 0x0))
-#define HW_LRADC_CTRL2_SET                              (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x20 + 0x4))
-#define HW_LRADC_CTRL2_CLR                              (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x20 + 0x8))
-#define HW_LRADC_CTRL2_TOG                              (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x20 + 0xc))
-#define BP_LRADC_CTRL2_DIVIDE_BY_TWO                    24
-#define BM_LRADC_CTRL2_DIVIDE_BY_TWO                    0xff000000
-#define BF_LRADC_CTRL2_DIVIDE_BY_TWO(v)                 (((v) << 24) & 0xff000000)
-#define BP_LRADC_CTRL2_LRADC6SELECT                     20
-#define BM_LRADC_CTRL2_LRADC6SELECT                     0xf00000
-#define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL0           0x0
-#define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL1           0x1
-#define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL2           0x2
-#define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL3           0x3
-#define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL4           0x4
-#define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL5           0x5
-#define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL6           0x6
-#define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL7           0x7
-#define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL8           0x8
-#define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL9           0x9
-#define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL10          0xa
-#define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL11          0xb
-#define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL12          0xc
-#define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL13          0xd
-#define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL14          0xe
-#define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL15          0xf
-#define BF_LRADC_CTRL2_LRADC6SELECT(v)                  (((v) << 20) & 0xf00000)
-#define BF_LRADC_CTRL2_LRADC6SELECT_V(v)                ((BV_LRADC_CTRL2_LRADC6SELECT__##v << 20) & 0xf00000)
-#define BP_LRADC_CTRL2_LRADC7SELECT                     16
-#define BM_LRADC_CTRL2_LRADC7SELECT                     0xf0000
-#define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL0           0x0
-#define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL1           0x1
-#define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL2           0x2
-#define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL3           0x3
-#define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL4           0x4
-#define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL5           0x5
-#define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL6           0x6
-#define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL7           0x7
-#define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL8           0x8
-#define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL9           0x9
-#define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL10          0xa
-#define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL11          0xb
-#define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL12          0xc
-#define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL13          0xd
-#define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL14          0xe
-#define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL15          0xf
-#define BF_LRADC_CTRL2_LRADC7SELECT(v)                  (((v) << 16) & 0xf0000)
-#define BF_LRADC_CTRL2_LRADC7SELECT_V(v)                ((BV_LRADC_CTRL2_LRADC7SELECT__##v << 16) & 0xf0000)
-#define BP_LRADC_CTRL2_TEMP_SENSOR_IENABLE1             9
-#define BM_LRADC_CTRL2_TEMP_SENSOR_IENABLE1             0x200
-#define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE1__DISABLE    0x0
-#define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE1__ENABLE     0x1
-#define BF_LRADC_CTRL2_TEMP_SENSOR_IENABLE1(v)          (((v) << 9) & 0x200)
-#define BF_LRADC_CTRL2_TEMP_SENSOR_IENABLE1_V(v)        ((BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE1__##v << 9) & 0x200)
-#define BP_LRADC_CTRL2_TEMP_SENSOR_IENABLE0             8
-#define BM_LRADC_CTRL2_TEMP_SENSOR_IENABLE0             0x100
-#define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE0__DISABLE    0x0
-#define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE0__ENABLE     0x1
-#define BF_LRADC_CTRL2_TEMP_SENSOR_IENABLE0(v)          (((v) << 8) & 0x100)
-#define BF_LRADC_CTRL2_TEMP_SENSOR_IENABLE0_V(v)        ((BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE0__##v << 8) & 0x100)
-#define BP_LRADC_CTRL2_TEMP_ISRC1                       4
-#define BM_LRADC_CTRL2_TEMP_ISRC1                       0xf0
-#define BV_LRADC_CTRL2_TEMP_ISRC1__300                  0xf
-#define BV_LRADC_CTRL2_TEMP_ISRC1__280                  0xe
-#define BV_LRADC_CTRL2_TEMP_ISRC1__260                  0xd
-#define BV_LRADC_CTRL2_TEMP_ISRC1__240                  0xc
-#define BV_LRADC_CTRL2_TEMP_ISRC1__220                  0xb
-#define BV_LRADC_CTRL2_TEMP_ISRC1__200                  0xa
-#define BV_LRADC_CTRL2_TEMP_ISRC1__180                  0x9
-#define BV_LRADC_CTRL2_TEMP_ISRC1__160                  0x8
-#define BV_LRADC_CTRL2_TEMP_ISRC1__140                  0x7
-#define BV_LRADC_CTRL2_TEMP_ISRC1__120                  0x6
-#define BV_LRADC_CTRL2_TEMP_ISRC1__100                  0x5
-#define BV_LRADC_CTRL2_TEMP_ISRC1__80                   0x4
-#define BV_LRADC_CTRL2_TEMP_ISRC1__60                   0x3
-#define BV_LRADC_CTRL2_TEMP_ISRC1__40                   0x2
-#define BV_LRADC_CTRL2_TEMP_ISRC1__20                   0x1
-#define BV_LRADC_CTRL2_TEMP_ISRC1__ZERO                 0x0
-#define BF_LRADC_CTRL2_TEMP_ISRC1(v)                    (((v) << 4) & 0xf0)
-#define BF_LRADC_CTRL2_TEMP_ISRC1_V(v)                  ((BV_LRADC_CTRL2_TEMP_ISRC1__##v << 4) & 0xf0)
-#define BP_LRADC_CTRL2_TEMP_ISRC0                       0
-#define BM_LRADC_CTRL2_TEMP_ISRC0                       0xf
-#define BV_LRADC_CTRL2_TEMP_ISRC0__300                  0xf
-#define BV_LRADC_CTRL2_TEMP_ISRC0__280                  0xe
-#define BV_LRADC_CTRL2_TEMP_ISRC0__260                  0xd
-#define BV_LRADC_CTRL2_TEMP_ISRC0__240                  0xc
-#define BV_LRADC_CTRL2_TEMP_ISRC0__220                  0xb
-#define BV_LRADC_CTRL2_TEMP_ISRC0__200                  0xa
-#define BV_LRADC_CTRL2_TEMP_ISRC0__180                  0x9
-#define BV_LRADC_CTRL2_TEMP_ISRC0__160                  0x8
-#define BV_LRADC_CTRL2_TEMP_ISRC0__140                  0x7
-#define BV_LRADC_CTRL2_TEMP_ISRC0__120                  0x6
-#define BV_LRADC_CTRL2_TEMP_ISRC0__100                  0x5
-#define BV_LRADC_CTRL2_TEMP_ISRC0__80                   0x4
-#define BV_LRADC_CTRL2_TEMP_ISRC0__60                   0x3
-#define BV_LRADC_CTRL2_TEMP_ISRC0__40                   0x2
-#define BV_LRADC_CTRL2_TEMP_ISRC0__20                   0x1
-#define BV_LRADC_CTRL2_TEMP_ISRC0__ZERO                 0x0
-#define BF_LRADC_CTRL2_TEMP_ISRC0(v)                    (((v) << 0) & 0xf)
-#define BF_LRADC_CTRL2_TEMP_ISRC0_V(v)                  ((BV_LRADC_CTRL2_TEMP_ISRC0__##v << 0) & 0xf)
-
-/**
- * Register: HW_LRADC_CTRL3
- * Address: 0x30
- * SCT: yes
-*/
-#define HW_LRADC_CTRL3                          (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x30 + 0x0))
-#define HW_LRADC_CTRL3_SET                      (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x30 + 0x4))
-#define HW_LRADC_CTRL3_CLR                      (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x30 + 0x8))
-#define HW_LRADC_CTRL3_TOG                      (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x30 + 0xc))
-#define BP_LRADC_CTRL3_DISCARD                  24
-#define BM_LRADC_CTRL3_DISCARD                  0x3000000
-#define BV_LRADC_CTRL3_DISCARD__1_SAMPLE        0x1
-#define BV_LRADC_CTRL3_DISCARD__2_SAMPLES       0x2
-#define BV_LRADC_CTRL3_DISCARD__3_SAMPLES       0x3
-#define BF_LRADC_CTRL3_DISCARD(v)               (((v) << 24) & 0x3000000)
-#define BF_LRADC_CTRL3_DISCARD_V(v)             ((BV_LRADC_CTRL3_DISCARD__##v << 24) & 0x3000000)
-#define BP_LRADC_CTRL3_FORCE_ANALOG_PWUP        23
-#define BM_LRADC_CTRL3_FORCE_ANALOG_PWUP        0x800000
-#define BV_LRADC_CTRL3_FORCE_ANALOG_PWUP__OFF   0x0
-#define BV_LRADC_CTRL3_FORCE_ANALOG_PWUP__ON    0x1
-#define BF_LRADC_CTRL3_FORCE_ANALOG_PWUP(v)     (((v) << 23) & 0x800000)
-#define BF_LRADC_CTRL3_FORCE_ANALOG_PWUP_V(v)   ((BV_LRADC_CTRL3_FORCE_ANALOG_PWUP__##v << 23) & 0x800000)
-#define BP_LRADC_CTRL3_FORCE_ANALOG_PWDN        22
-#define BM_LRADC_CTRL3_FORCE_ANALOG_PWDN        0x400000
-#define BV_LRADC_CTRL3_FORCE_ANALOG_PWDN__ON    0x0
-#define BV_LRADC_CTRL3_FORCE_ANALOG_PWDN__OFF   0x1
-#define BF_LRADC_CTRL3_FORCE_ANALOG_PWDN(v)     (((v) << 22) & 0x400000)
-#define BF_LRADC_CTRL3_FORCE_ANALOG_PWDN_V(v)   ((BV_LRADC_CTRL3_FORCE_ANALOG_PWDN__##v << 22) & 0x400000)
-#define BP_LRADC_CTRL3_FORCE_PWD40UA_PWUP       21
-#define BM_LRADC_CTRL3_FORCE_PWD40UA_PWUP       0x200000
-#define BV_LRADC_CTRL3_FORCE_PWD40UA_PWUP__OFF  0x0
-#define BV_LRADC_CTRL3_FORCE_PWD40UA_PWUP__ON   0x1
-#define BF_LRADC_CTRL3_FORCE_PWD40UA_PWUP(v)    (((v) << 21) & 0x200000)
-#define BF_LRADC_CTRL3_FORCE_PWD40UA_PWUP_V(v)  ((BV_LRADC_CTRL3_FORCE_PWD40UA_PWUP__##v << 21) & 0x200000)
-#define BP_LRADC_CTRL3_FORCE_PWD40UA_PWDN       20
-#define BM_LRADC_CTRL3_FORCE_PWD40UA_PWDN       0x100000
-#define BV_LRADC_CTRL3_FORCE_PWD40UA_PWDN__ON   0x0
-#define BV_LRADC_CTRL3_FORCE_PWD40UA_PWDN__OFF  0x1
-#define BF_LRADC_CTRL3_FORCE_PWD40UA_PWDN(v)    (((v) << 20) & 0x100000)
-#define BF_LRADC_CTRL3_FORCE_PWD40UA_PWDN_V(v)  ((BV_LRADC_CTRL3_FORCE_PWD40UA_PWDN__##v << 20) & 0x100000)
-#define BP_LRADC_CTRL3_VDD_FILTER               16
-#define BM_LRADC_CTRL3_VDD_FILTER               0x30000
-#define BV_LRADC_CTRL3_VDD_FILTER__0OHMS        0x0
-#define BV_LRADC_CTRL3_VDD_FILTER__100OHMS      0x1
-#define BV_LRADC_CTRL3_VDD_FILTER__250OHMS      0x2
-#define BV_LRADC_CTRL3_VDD_FILTER__5000OHMS     0x3
-#define BF_LRADC_CTRL3_VDD_FILTER(v)            (((v) << 16) & 0x30000)
-#define BF_LRADC_CTRL3_VDD_FILTER_V(v)          ((BV_LRADC_CTRL3_VDD_FILTER__##v << 16) & 0x30000)
-#define BP_LRADC_CTRL3_ADD_CAP2INPUTS           12
-#define BM_LRADC_CTRL3_ADD_CAP2INPUTS           0x3000
-#define BV_LRADC_CTRL3_ADD_CAP2INPUTS__0PF      0x0
-#define BV_LRADC_CTRL3_ADD_CAP2INPUTS__0_5PF    0x1
-#define BV_LRADC_CTRL3_ADD_CAP2INPUTS__1_0PF    0x2
-#define BV_LRADC_CTRL3_ADD_CAP2INPUTS__2_5PF    0x3
-#define BF_LRADC_CTRL3_ADD_CAP2INPUTS(v)        (((v) << 12) & 0x3000)
-#define BF_LRADC_CTRL3_ADD_CAP2INPUTS_V(v)      ((BV_LRADC_CTRL3_ADD_CAP2INPUTS__##v << 12) & 0x3000)
-#define BP_LRADC_CTRL3_CYCLE_TIME               8
-#define BM_LRADC_CTRL3_CYCLE_TIME               0x300
-#define BV_LRADC_CTRL3_CYCLE_TIME__6MHZ         0x0
-#define BV_LRADC_CTRL3_CYCLE_TIME__4MHZ         0x1
-#define BV_LRADC_CTRL3_CYCLE_TIME__3MHZ         0x2
-#define BV_LRADC_CTRL3_CYCLE_TIME__2MHZ         0x3
-#define BF_LRADC_CTRL3_CYCLE_TIME(v)            (((v) << 8) & 0x300)
-#define BF_LRADC_CTRL3_CYCLE_TIME_V(v)          ((BV_LRADC_CTRL3_CYCLE_TIME__##v << 8) & 0x300)
-#define BP_LRADC_CTRL3_HIGH_TIME                4
-#define BM_LRADC_CTRL3_HIGH_TIME                0x30
-#define BV_LRADC_CTRL3_HIGH_TIME__42NS          0x0
-#define BV_LRADC_CTRL3_HIGH_TIME__83NS          0x1
-#define BV_LRADC_CTRL3_HIGH_TIME__125NS         0x2
-#define BV_LRADC_CTRL3_HIGH_TIME__250NS         0x3
-#define BF_LRADC_CTRL3_HIGH_TIME(v)             (((v) << 4) & 0x30)
-#define BF_LRADC_CTRL3_HIGH_TIME_V(v)           ((BV_LRADC_CTRL3_HIGH_TIME__##v << 4) & 0x30)
-#define BP_LRADC_CTRL3_REMOVE_CFILT             3
-#define BM_LRADC_CTRL3_REMOVE_CFILT             0x8
-#define BV_LRADC_CTRL3_REMOVE_CFILT__OFF        0x0
-#define BV_LRADC_CTRL3_REMOVE_CFILT__ON         0x1
-#define BF_LRADC_CTRL3_REMOVE_CFILT(v)          (((v) << 3) & 0x8)
-#define BF_LRADC_CTRL3_REMOVE_CFILT_V(v)        ((BV_LRADC_CTRL3_REMOVE_CFILT__##v << 3) & 0x8)
-#define BP_LRADC_CTRL3_SHORT_RFILT              2
-#define BM_LRADC_CTRL3_SHORT_RFILT              0x4
-#define BV_LRADC_CTRL3_SHORT_RFILT__OFF         0x0
-#define BV_LRADC_CTRL3_SHORT_RFILT__ON          0x1
-#define BF_LRADC_CTRL3_SHORT_RFILT(v)           (((v) << 2) & 0x4)
-#define BF_LRADC_CTRL3_SHORT_RFILT_V(v)         ((BV_LRADC_CTRL3_SHORT_RFILT__##v << 2) & 0x4)
-#define BP_LRADC_CTRL3_DELAY_CLOCK              1
-#define BM_LRADC_CTRL3_DELAY_CLOCK              0x2
-#define BV_LRADC_CTRL3_DELAY_CLOCK__NORMAL      0x0
-#define BV_LRADC_CTRL3_DELAY_CLOCK__DELAYED     0x1
-#define BF_LRADC_CTRL3_DELAY_CLOCK(v)           (((v) << 1) & 0x2)
-#define BF_LRADC_CTRL3_DELAY_CLOCK_V(v)         ((BV_LRADC_CTRL3_DELAY_CLOCK__##v << 1) & 0x2)
-#define BP_LRADC_CTRL3_INVERT_CLOCK             0
-#define BM_LRADC_CTRL3_INVERT_CLOCK             0x1
-#define BV_LRADC_CTRL3_INVERT_CLOCK__NORMAL     0x0
-#define BV_LRADC_CTRL3_INVERT_CLOCK__INVERT     0x1
-#define BF_LRADC_CTRL3_INVERT_CLOCK(v)          (((v) << 0) & 0x1)
-#define BF_LRADC_CTRL3_INVERT_CLOCK_V(v)        ((BV_LRADC_CTRL3_INVERT_CLOCK__##v << 0) & 0x1)
-
-/**
- * Register: HW_LRADC_STATUS
- * Address: 0x40
- * SCT: no
-*/
-#define HW_LRADC_STATUS                         (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x40))
-#define BP_LRADC_STATUS_TEMP1_PRESENT           26
-#define BM_LRADC_STATUS_TEMP1_PRESENT           0x4000000
-#define BF_LRADC_STATUS_TEMP1_PRESENT(v)        (((v) << 26) & 0x4000000)
-#define BP_LRADC_STATUS_TEMP0_PRESENT           25
-#define BM_LRADC_STATUS_TEMP0_PRESENT           0x2000000
-#define BF_LRADC_STATUS_TEMP0_PRESENT(v)        (((v) << 25) & 0x2000000)
-#define BP_LRADC_STATUS_TOUCH_PANEL_PRESENT     24
-#define BM_LRADC_STATUS_TOUCH_PANEL_PRESENT     0x1000000
-#define BF_LRADC_STATUS_TOUCH_PANEL_PRESENT(v)  (((v) << 24) & 0x1000000)
-#define BP_LRADC_STATUS_CHANNEL7_PRESENT        23
-#define BM_LRADC_STATUS_CHANNEL7_PRESENT        0x800000
-#define BF_LRADC_STATUS_CHANNEL7_PRESENT(v)     (((v) << 23) & 0x800000)
-#define BP_LRADC_STATUS_CHANNEL6_PRESENT        22
-#define BM_LRADC_STATUS_CHANNEL6_PRESENT        0x400000
-#define BF_LRADC_STATUS_CHANNEL6_PRESENT(v)     (((v) << 22) & 0x400000)
-#define BP_LRADC_STATUS_CHANNEL5_PRESENT        21
-#define BM_LRADC_STATUS_CHANNEL5_PRESENT        0x200000
-#define BF_LRADC_STATUS_CHANNEL5_PRESENT(v)     (((v) << 21) & 0x200000)
-#define BP_LRADC_STATUS_CHANNEL4_PRESENT        20
-#define BM_LRADC_STATUS_CHANNEL4_PRESENT        0x100000
-#define BF_LRADC_STATUS_CHANNEL4_PRESENT(v)     (((v) << 20) & 0x100000)
-#define BP_LRADC_STATUS_CHANNEL3_PRESENT        19
-#define BM_LRADC_STATUS_CHANNEL3_PRESENT        0x80000
-#define BF_LRADC_STATUS_CHANNEL3_PRESENT(v)     (((v) << 19) & 0x80000)
-#define BP_LRADC_STATUS_CHANNEL2_PRESENT        18
-#define BM_LRADC_STATUS_CHANNEL2_PRESENT        0x40000
-#define BF_LRADC_STATUS_CHANNEL2_PRESENT(v)     (((v) << 18) & 0x40000)
-#define BP_LRADC_STATUS_CHANNEL1_PRESENT        17
-#define BM_LRADC_STATUS_CHANNEL1_PRESENT        0x20000
-#define BF_LRADC_STATUS_CHANNEL1_PRESENT(v)     (((v) << 17) & 0x20000)
-#define BP_LRADC_STATUS_CHANNEL0_PRESENT        16
-#define BM_LRADC_STATUS_CHANNEL0_PRESENT        0x10000
-#define BF_LRADC_STATUS_CHANNEL0_PRESENT(v)     (((v) << 16) & 0x10000)
-#define BP_LRADC_STATUS_TOUCH_DETECT_RAW        0
-#define BM_LRADC_STATUS_TOUCH_DETECT_RAW        0x1
-#define BV_LRADC_STATUS_TOUCH_DETECT_RAW__OPEN  0x0
-#define BV_LRADC_STATUS_TOUCH_DETECT_RAW__HIT   0x1
-#define BF_LRADC_STATUS_TOUCH_DETECT_RAW(v)     (((v) << 0) & 0x1)
-#define BF_LRADC_STATUS_TOUCH_DETECT_RAW_V(v)   ((BV_LRADC_STATUS_TOUCH_DETECT_RAW__##v << 0) & 0x1)
-
-/**
- * Register: HW_LRADC_DEBUG0
- * Address: 0x110
- * SCT: no
-*/
-#define HW_LRADC_DEBUG0             (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x110))
-#define BP_LRADC_DEBUG0_READONLY    16
-#define BM_LRADC_DEBUG0_READONLY    0xffff0000
-#define BF_LRADC_DEBUG0_READONLY(v) (((v) << 16) & 0xffff0000)
-#define BP_LRADC_DEBUG0_STATE       0
-#define BM_LRADC_DEBUG0_STATE       0xfff
-#define BF_LRADC_DEBUG0_STATE(v)    (((v) << 0) & 0xfff)
-
-/**
- * Register: HW_LRADC_DEBUG1
- * Address: 0x120
- * SCT: yes
-*/
-#define HW_LRADC_DEBUG1                     (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x120 + 0x0))
-#define HW_LRADC_DEBUG1_SET                 (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x120 + 0x4))
-#define HW_LRADC_DEBUG1_CLR                 (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x120 + 0x8))
-#define HW_LRADC_DEBUG1_TOG                 (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x120 + 0xc))
-#define BP_LRADC_DEBUG1_REQUEST             16
-#define BM_LRADC_DEBUG1_REQUEST             0xff0000
-#define BF_LRADC_DEBUG1_REQUEST(v)          (((v) << 16) & 0xff0000)
-#define BP_LRADC_DEBUG1_TESTMODE_COUNT      8
-#define BM_LRADC_DEBUG1_TESTMODE_COUNT      0x1f00
-#define BF_LRADC_DEBUG1_TESTMODE_COUNT(v)   (((v) << 8) & 0x1f00)
-#define BP_LRADC_DEBUG1_TESTMODE6           2
-#define BM_LRADC_DEBUG1_TESTMODE6           0x4
-#define BV_LRADC_DEBUG1_TESTMODE6__NORMAL   0x0
-#define BV_LRADC_DEBUG1_TESTMODE6__TEST     0x1
-#define BF_LRADC_DEBUG1_TESTMODE6(v)        (((v) << 2) & 0x4)
-#define BF_LRADC_DEBUG1_TESTMODE6_V(v)      ((BV_LRADC_DEBUG1_TESTMODE6__##v << 2) & 0x4)
-#define BP_LRADC_DEBUG1_TESTMODE5           1
-#define BM_LRADC_DEBUG1_TESTMODE5           0x2
-#define BV_LRADC_DEBUG1_TESTMODE5__NORMAL   0x0
-#define BV_LRADC_DEBUG1_TESTMODE5__TEST     0x1
-#define BF_LRADC_DEBUG1_TESTMODE5(v)        (((v) << 1) & 0x2)
-#define BF_LRADC_DEBUG1_TESTMODE5_V(v)      ((BV_LRADC_DEBUG1_TESTMODE5__##v << 1) & 0x2)
-#define BP_LRADC_DEBUG1_TESTMODE            0
-#define BM_LRADC_DEBUG1_TESTMODE            0x1
-#define BV_LRADC_DEBUG1_TESTMODE__NORMAL    0x0
-#define BV_LRADC_DEBUG1_TESTMODE__TEST      0x1
-#define BF_LRADC_DEBUG1_TESTMODE(v)         (((v) << 0) & 0x1)
-#define BF_LRADC_DEBUG1_TESTMODE_V(v)       ((BV_LRADC_DEBUG1_TESTMODE__##v << 0) & 0x1)
-
-/**
- * Register: HW_LRADC_CONVERSION
- * Address: 0x130
- * SCT: yes
-*/
-#define HW_LRADC_CONVERSION                             (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x130 + 0x0))
-#define HW_LRADC_CONVERSION_SET                         (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x130 + 0x4))
-#define HW_LRADC_CONVERSION_CLR                         (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x130 + 0x8))
-#define HW_LRADC_CONVERSION_TOG                         (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x130 + 0xc))
-#define BP_LRADC_CONVERSION_AUTOMATIC                   20
-#define BM_LRADC_CONVERSION_AUTOMATIC                   0x100000
-#define BV_LRADC_CONVERSION_AUTOMATIC__DISABLE          0x0
-#define BV_LRADC_CONVERSION_AUTOMATIC__ENABLE           0x1
-#define BF_LRADC_CONVERSION_AUTOMATIC(v)                (((v) << 20) & 0x100000)
-#define BF_LRADC_CONVERSION_AUTOMATIC_V(v)              ((BV_LRADC_CONVERSION_AUTOMATIC__##v << 20) & 0x100000)
-#define BP_LRADC_CONVERSION_SCALE_FACTOR                16
-#define BM_LRADC_CONVERSION_SCALE_FACTOR                0x30000
-#define BV_LRADC_CONVERSION_SCALE_FACTOR__NIMH          0x0
-#define BV_LRADC_CONVERSION_SCALE_FACTOR__DUAL_NIMH     0x1
-#define BV_LRADC_CONVERSION_SCALE_FACTOR__LI_ION        0x2
-#define BV_LRADC_CONVERSION_SCALE_FACTOR__ALT_LI_ION    0x3
-#define BF_LRADC_CONVERSION_SCALE_FACTOR(v)             (((v) << 16) & 0x30000)
-#define BF_LRADC_CONVERSION_SCALE_FACTOR_V(v)           ((BV_LRADC_CONVERSION_SCALE_FACTOR__##v << 16) & 0x30000)
-#define BP_LRADC_CONVERSION_SCALED_BATT_VOLTAGE         0
-#define BM_LRADC_CONVERSION_SCALED_BATT_VOLTAGE         0x3ff
-#define BF_LRADC_CONVERSION_SCALED_BATT_VOLTAGE(v)      (((v) << 0) & 0x3ff)
-
-/**
- * Register: HW_LRADC_DELAYn
- * Address: 0xd0+n*0x10
- * SCT: yes
-*/
-#define HW_LRADC_DELAYn(n)                  (*(volatile unsigned long *)(REGS_LRADC_BASE + 0xd0+(n)*0x10 + 0x0))
-#define HW_LRADC_DELAYn_SET(n)              (*(volatile unsigned long *)(REGS_LRADC_BASE + 0xd0+(n)*0x10 + 0x4))
-#define HW_LRADC_DELAYn_CLR(n)              (*(volatile unsigned long *)(REGS_LRADC_BASE + 0xd0+(n)*0x10 + 0x8))
-#define HW_LRADC_DELAYn_TOG(n)              (*(volatile unsigned long *)(REGS_LRADC_BASE + 0xd0+(n)*0x10 + 0xc))
-#define BP_LRADC_DELAYn_TRIGGER_LRADCS      24
-#define BM_LRADC_DELAYn_TRIGGER_LRADCS      0xff000000
-#define BF_LRADC_DELAYn_TRIGGER_LRADCS(v)   (((v) << 24) & 0xff000000)
-#define BP_LRADC_DELAYn_KICK                20
-#define BM_LRADC_DELAYn_KICK                0x100000
-#define BF_LRADC_DELAYn_KICK(v)             (((v) << 20) & 0x100000)
-#define BP_LRADC_DELAYn_TRIGGER_DELAYS      16
-#define BM_LRADC_DELAYn_TRIGGER_DELAYS      0xf0000
-#define BF_LRADC_DELAYn_TRIGGER_DELAYS(v)   (((v) << 16) & 0xf0000)
-#define BP_LRADC_DELAYn_LOOP_COUNT          11
-#define BM_LRADC_DELAYn_LOOP_COUNT          0xf800
-#define BF_LRADC_DELAYn_LOOP_COUNT(v)       (((v) << 11) & 0xf800)
-#define BP_LRADC_DELAYn_DELAY               0
-#define BM_LRADC_DELAYn_DELAY               0x7ff
-#define BF_LRADC_DELAYn_DELAY(v)            (((v) << 0) & 0x7ff)
-
-/**
- * Register: HW_LRADC_CHn
- * Address: 0x50+n*0x10
- * SCT: yes
-*/
-#define HW_LRADC_CHn(n)             (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x50+(n)*0x10 + 0x0))
-#define HW_LRADC_CHn_SET(n)         (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x50+(n)*0x10 + 0x4))
-#define HW_LRADC_CHn_CLR(n)         (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x50+(n)*0x10 + 0x8))
-#define HW_LRADC_CHn_TOG(n)         (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x50+(n)*0x10 + 0xc))
-#define BP_LRADC_CHn_TOGGLE         31
-#define BM_LRADC_CHn_TOGGLE         0x80000000
-#define BF_LRADC_CHn_TOGGLE(v)      (((v) << 31) & 0x80000000)
-#define BP_LRADC_CHn_ACCUMULATE     29
-#define BM_LRADC_CHn_ACCUMULATE     0x20000000
-#define BF_LRADC_CHn_ACCUMULATE(v)  (((v) << 29) & 0x20000000)
-#define BP_LRADC_CHn_NUM_SAMPLES    24
-#define BM_LRADC_CHn_NUM_SAMPLES    0x1f000000
-#define BF_LRADC_CHn_NUM_SAMPLES(v) (((v) << 24) & 0x1f000000)
-#define BP_LRADC_CHn_VALUE          0
-#define BM_LRADC_CHn_VALUE          0x3ffff
-#define BF_LRADC_CHn_VALUE(v)       (((v) << 0) & 0x3ffff)
-
-#endif /* __HEADERGEN__STMP3600__LRADC__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-memcpy.h b/firmware/target/arm/imx233/regs/stmp3600/regs-memcpy.h
deleted file mode 100644
index 87c4c5ce58..0000000000
--- a/firmware/target/arm/imx233/regs/stmp3600/regs-memcpy.h
+++ /dev/null
@@ -1,105 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3600:2.3.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__STMP3600__MEMCPY__H__
-#define __HEADERGEN__STMP3600__MEMCPY__H__
-
-#define REGS_MEMCPY_BASE (0x80014000)
-
-#define REGS_MEMCPY_VERSION "2.3.0"
-
-/**
- * Register: HW_MEMCPY_CTRL
- * Address: 0
- * SCT: yes
-*/
-#define HW_MEMCPY_CTRL                      (*(volatile unsigned long *)(REGS_MEMCPY_BASE + 0x0 + 0x0))
-#define HW_MEMCPY_CTRL_SET                  (*(volatile unsigned long *)(REGS_MEMCPY_BASE + 0x0 + 0x4))
-#define HW_MEMCPY_CTRL_CLR                  (*(volatile unsigned long *)(REGS_MEMCPY_BASE + 0x0 + 0x8))
-#define HW_MEMCPY_CTRL_TOG                  (*(volatile unsigned long *)(REGS_MEMCPY_BASE + 0x0 + 0xc))
-#define BP_MEMCPY_CTRL_SFTRST               31
-#define BM_MEMCPY_CTRL_SFTRST               0x80000000
-#define BV_MEMCPY_CTRL_SFTRST__RUN          0x0
-#define BV_MEMCPY_CTRL_SFTRST__RESET        0x1
-#define BF_MEMCPY_CTRL_SFTRST(v)            (((v) << 31) & 0x80000000)
-#define BF_MEMCPY_CTRL_SFTRST_V(v)          ((BV_MEMCPY_CTRL_SFTRST__##v << 31) & 0x80000000)
-#define BP_MEMCPY_CTRL_CLKGATE              30
-#define BM_MEMCPY_CTRL_CLKGATE              0x40000000
-#define BV_MEMCPY_CTRL_CLKGATE__RUN         0x0
-#define BV_MEMCPY_CTRL_CLKGATE__NO_CLKS     0x1
-#define BF_MEMCPY_CTRL_CLKGATE(v)           (((v) << 30) & 0x40000000)
-#define BF_MEMCPY_CTRL_CLKGATE_V(v)         ((BV_MEMCPY_CTRL_CLKGATE__##v << 30) & 0x40000000)
-#define BP_MEMCPY_CTRL_PRESENT              29
-#define BM_MEMCPY_CTRL_PRESENT              0x20000000
-#define BV_MEMCPY_CTRL_PRESENT__UNAVAILABLE 0x0
-#define BV_MEMCPY_CTRL_PRESENT__AVAILABLE   0x1
-#define BF_MEMCPY_CTRL_PRESENT(v)           (((v) << 29) & 0x20000000)
-#define BF_MEMCPY_CTRL_PRESENT_V(v)         ((BV_MEMCPY_CTRL_PRESENT__##v << 29) & 0x20000000)
-#define BP_MEMCPY_CTRL_BURST                16
-#define BM_MEMCPY_CTRL_BURST                0x10000
-#define BF_MEMCPY_CTRL_BURST(v)             (((v) << 16) & 0x10000)
-#define BP_MEMCPY_CTRL_XFER_SIZE            0
-#define BM_MEMCPY_CTRL_XFER_SIZE            0xffff
-#define BF_MEMCPY_CTRL_XFER_SIZE(v)         (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_MEMCPY_DATA
- * Address: 0x10
- * SCT: yes
-*/
-#define HW_MEMCPY_DATA          (*(volatile unsigned long *)(REGS_MEMCPY_BASE + 0x10 + 0x0))
-#define HW_MEMCPY_DATA_SET      (*(volatile unsigned long *)(REGS_MEMCPY_BASE + 0x10 + 0x4))
-#define HW_MEMCPY_DATA_CLR      (*(volatile unsigned long *)(REGS_MEMCPY_BASE + 0x10 + 0x8))
-#define HW_MEMCPY_DATA_TOG      (*(volatile unsigned long *)(REGS_MEMCPY_BASE + 0x10 + 0xc))
-#define BP_MEMCPY_DATA_DATA     0
-#define BM_MEMCPY_DATA_DATA     0xffffffff
-#define BF_MEMCPY_DATA_DATA(v)  (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_MEMCPY_DEBUG
- * Address: 0x20
- * SCT: no
-*/
-#define HW_MEMCPY_DEBUG                 (*(volatile unsigned long *)(REGS_MEMCPY_BASE + 0x20))
-#define BP_MEMCPY_DEBUG_DST_END_CMD     30
-#define BM_MEMCPY_DEBUG_DST_END_CMD     0x40000000
-#define BF_MEMCPY_DEBUG_DST_END_CMD(v)  (((v) << 30) & 0x40000000)
-#define BP_MEMCPY_DEBUG_DST_KICK        29
-#define BM_MEMCPY_DEBUG_DST_KICK        0x20000000
-#define BF_MEMCPY_DEBUG_DST_KICK(v)     (((v) << 29) & 0x20000000)
-#define BP_MEMCPY_DEBUG_DST_DMA_REQ     28
-#define BM_MEMCPY_DEBUG_DST_DMA_REQ     0x10000000
-#define BF_MEMCPY_DEBUG_DST_DMA_REQ(v)  (((v) << 28) & 0x10000000)
-#define BP_MEMCPY_DEBUG_SRC_KICK        25
-#define BM_MEMCPY_DEBUG_SRC_KICK        0x2000000
-#define BF_MEMCPY_DEBUG_SRC_KICK(v)     (((v) << 25) & 0x2000000)
-#define BP_MEMCPY_DEBUG_SRC_DMA_REQ     24
-#define BM_MEMCPY_DEBUG_SRC_DMA_REQ     0x1000000
-#define BF_MEMCPY_DEBUG_SRC_DMA_REQ(v)  (((v) << 24) & 0x1000000)
-#define BP_MEMCPY_DEBUG_WRITE_STATE     2
-#define BM_MEMCPY_DEBUG_WRITE_STATE     0xc
-#define BF_MEMCPY_DEBUG_WRITE_STATE(v)  (((v) << 2) & 0xc)
-#define BP_MEMCPY_DEBUG_READ_STATE      0
-#define BM_MEMCPY_DEBUG_READ_STATE      0x3
-#define BF_MEMCPY_DEBUG_READ_STATE(v)   (((v) << 0) & 0x3)
-
-#endif /* __HEADERGEN__STMP3600__MEMCPY__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-pinctrl.h b/firmware/target/arm/imx233/regs/stmp3600/regs-pinctrl.h
deleted file mode 100644
index 41486bc5c3..0000000000
--- a/firmware/target/arm/imx233/regs/stmp3600/regs-pinctrl.h
+++ /dev/null
@@ -1,213 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3600:2.3.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__STMP3600__PINCTRL__H__
-#define __HEADERGEN__STMP3600__PINCTRL__H__
-
-#define REGS_PINCTRL_BASE (0x80018000)
-
-#define REGS_PINCTRL_VERSION "2.3.0"
-
-/**
- * Register: HW_PINCTRL_CTRL
- * Address: 0
- * SCT: yes
-*/
-#define HW_PINCTRL_CTRL             (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x0 + 0x0))
-#define HW_PINCTRL_CTRL_SET         (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x0 + 0x4))
-#define HW_PINCTRL_CTRL_CLR         (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x0 + 0x8))
-#define HW_PINCTRL_CTRL_TOG         (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x0 + 0xc))
-#define BP_PINCTRL_CTRL_SFTRST      31
-#define BM_PINCTRL_CTRL_SFTRST      0x80000000
-#define BF_PINCTRL_CTRL_SFTRST(v)   (((v) << 31) & 0x80000000)
-#define BP_PINCTRL_CTRL_CLKGATE     30
-#define BM_PINCTRL_CTRL_CLKGATE     0x40000000
-#define BF_PINCTRL_CTRL_CLKGATE(v)  (((v) << 30) & 0x40000000)
-#define BP_PINCTRL_CTRL_PRESENT3    29
-#define BM_PINCTRL_CTRL_PRESENT3    0x20000000
-#define BF_PINCTRL_CTRL_PRESENT3(v) (((v) << 29) & 0x20000000)
-#define BP_PINCTRL_CTRL_PRESENT2    28
-#define BM_PINCTRL_CTRL_PRESENT2    0x10000000
-#define BF_PINCTRL_CTRL_PRESENT2(v) (((v) << 28) & 0x10000000)
-#define BP_PINCTRL_CTRL_PRESENT1    27
-#define BM_PINCTRL_CTRL_PRESENT1    0x8000000
-#define BF_PINCTRL_CTRL_PRESENT1(v) (((v) << 27) & 0x8000000)
-#define BP_PINCTRL_CTRL_PRESENT0    26
-#define BM_PINCTRL_CTRL_PRESENT0    0x4000000
-#define BF_PINCTRL_CTRL_PRESENT0(v) (((v) << 26) & 0x4000000)
-#define BP_PINCTRL_CTRL_IRQOUT3     3
-#define BM_PINCTRL_CTRL_IRQOUT3     0x8
-#define BF_PINCTRL_CTRL_IRQOUT3(v)  (((v) << 3) & 0x8)
-#define BP_PINCTRL_CTRL_IRQOUT2     2
-#define BM_PINCTRL_CTRL_IRQOUT2     0x4
-#define BF_PINCTRL_CTRL_IRQOUT2(v)  (((v) << 2) & 0x4)
-#define BP_PINCTRL_CTRL_IRQOUT1     1
-#define BM_PINCTRL_CTRL_IRQOUT1     0x2
-#define BF_PINCTRL_CTRL_IRQOUT1(v)  (((v) << 1) & 0x2)
-#define BP_PINCTRL_CTRL_IRQOUT0     0
-#define BM_PINCTRL_CTRL_IRQOUT0     0x1
-#define BF_PINCTRL_CTRL_IRQOUT0(v)  (((v) << 0) & 0x1)
-
-/**
- * Register: HW_PINCTRL_MUXSELLn
- * Address: 0x10+n*0x100
- * SCT: yes
-*/
-#define HW_PINCTRL_MUXSELLn(n)      (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x10+(n)*0x100 + 0x0))
-#define HW_PINCTRL_MUXSELLn_SET(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x10+(n)*0x100 + 0x4))
-#define HW_PINCTRL_MUXSELLn_CLR(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x10+(n)*0x100 + 0x8))
-#define HW_PINCTRL_MUXSELLn_TOG(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x10+(n)*0x100 + 0xc))
-#define BP_PINCTRL_MUXSELLn_BITS    0
-#define BM_PINCTRL_MUXSELLn_BITS    0xffffffff
-#define BF_PINCTRL_MUXSELLn_BITS(v) (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_PINCTRL_MUXSELHn
- * Address: 0x20+n*0x100
- * SCT: yes
-*/
-#define HW_PINCTRL_MUXSELHn(n)      (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x20+(n)*0x100 + 0x0))
-#define HW_PINCTRL_MUXSELHn_SET(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x20+(n)*0x100 + 0x4))
-#define HW_PINCTRL_MUXSELHn_CLR(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x20+(n)*0x100 + 0x8))
-#define HW_PINCTRL_MUXSELHn_TOG(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x20+(n)*0x100 + 0xc))
-#define BP_PINCTRL_MUXSELHn_BITS    0
-#define BM_PINCTRL_MUXSELHn_BITS    0xffffffff
-#define BF_PINCTRL_MUXSELHn_BITS(v) (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_PINCTRL_DRIVEn
- * Address: 0x30+n*0x100
- * SCT: yes
-*/
-#define HW_PINCTRL_DRIVEn(n)        (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x30+(n)*0x100 + 0x0))
-#define HW_PINCTRL_DRIVEn_SET(n)    (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x30+(n)*0x100 + 0x4))
-#define HW_PINCTRL_DRIVEn_CLR(n)    (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x30+(n)*0x100 + 0x8))
-#define HW_PINCTRL_DRIVEn_TOG(n)    (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x30+(n)*0x100 + 0xc))
-#define BP_PINCTRL_DRIVEn_BITS      0
-#define BM_PINCTRL_DRIVEn_BITS      0xffffffff
-#define BF_PINCTRL_DRIVEn_BITS(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_PINCTRL_DOUTn
- * Address: 0x50+n*0x100
- * SCT: yes
-*/
-#define HW_PINCTRL_DOUTn(n)         (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x50+(n)*0x100 + 0x0))
-#define HW_PINCTRL_DOUTn_SET(n)     (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x50+(n)*0x100 + 0x4))
-#define HW_PINCTRL_DOUTn_CLR(n)     (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x50+(n)*0x100 + 0x8))
-#define HW_PINCTRL_DOUTn_TOG(n)     (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x50+(n)*0x100 + 0xc))
-#define BP_PINCTRL_DOUTn_BITS       0
-#define BM_PINCTRL_DOUTn_BITS       0xffffffff
-#define BF_PINCTRL_DOUTn_BITS(v)    (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_PINCTRL_DINn
- * Address: 0x60+n*0x100
- * SCT: yes
-*/
-#define HW_PINCTRL_DINn(n)      (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x60+(n)*0x100 + 0x0))
-#define HW_PINCTRL_DINn_SET(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x60+(n)*0x100 + 0x4))
-#define HW_PINCTRL_DINn_CLR(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x60+(n)*0x100 + 0x8))
-#define HW_PINCTRL_DINn_TOG(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x60+(n)*0x100 + 0xc))
-#define BP_PINCTRL_DINn_BITS    0
-#define BM_PINCTRL_DINn_BITS    0xffffffff
-#define BF_PINCTRL_DINn_BITS(v) (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_PINCTRL_DOEn
- * Address: 0x70+n*0x100
- * SCT: yes
-*/
-#define HW_PINCTRL_DOEn(n)      (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x70+(n)*0x100 + 0x0))
-#define HW_PINCTRL_DOEn_SET(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x70+(n)*0x100 + 0x4))
-#define HW_PINCTRL_DOEn_CLR(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x70+(n)*0x100 + 0x8))
-#define HW_PINCTRL_DOEn_TOG(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x70+(n)*0x100 + 0xc))
-#define BP_PINCTRL_DOEn_BITS    0
-#define BM_PINCTRL_DOEn_BITS    0xffffffff
-#define BF_PINCTRL_DOEn_BITS(v) (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_PINCTRL_PIN2IRQn
- * Address: 0x80+n*0x100
- * SCT: yes
-*/
-#define HW_PINCTRL_PIN2IRQn(n)      (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x80+(n)*0x100 + 0x0))
-#define HW_PINCTRL_PIN2IRQn_SET(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x80+(n)*0x100 + 0x4))
-#define HW_PINCTRL_PIN2IRQn_CLR(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x80+(n)*0x100 + 0x8))
-#define HW_PINCTRL_PIN2IRQn_TOG(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x80+(n)*0x100 + 0xc))
-#define BP_PINCTRL_PIN2IRQn_BITS    0
-#define BM_PINCTRL_PIN2IRQn_BITS    0xffffffff
-#define BF_PINCTRL_PIN2IRQn_BITS(v) (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_PINCTRL_IRQENn
- * Address: 0x90+n*0x100
- * SCT: yes
-*/
-#define HW_PINCTRL_IRQENn(n)        (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x90+(n)*0x100 + 0x0))
-#define HW_PINCTRL_IRQENn_SET(n)    (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x90+(n)*0x100 + 0x4))
-#define HW_PINCTRL_IRQENn_CLR(n)    (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x90+(n)*0x100 + 0x8))
-#define HW_PINCTRL_IRQENn_TOG(n)    (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x90+(n)*0x100 + 0xc))
-#define BP_PINCTRL_IRQENn_BITS      0
-#define BM_PINCTRL_IRQENn_BITS      0xffffffff
-#define BF_PINCTRL_IRQENn_BITS(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_PINCTRL_IRQLEVELn
- * Address: 0xa0+n*0x100
- * SCT: yes
-*/
-#define HW_PINCTRL_IRQLEVELn(n)         (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xa0+(n)*0x100 + 0x0))
-#define HW_PINCTRL_IRQLEVELn_SET(n)     (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xa0+(n)*0x100 + 0x4))
-#define HW_PINCTRL_IRQLEVELn_CLR(n)     (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xa0+(n)*0x100 + 0x8))
-#define HW_PINCTRL_IRQLEVELn_TOG(n)     (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xa0+(n)*0x100 + 0xc))
-#define BP_PINCTRL_IRQLEVELn_BITS       0
-#define BM_PINCTRL_IRQLEVELn_BITS       0xffffffff
-#define BF_PINCTRL_IRQLEVELn_BITS(v)    (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_PINCTRL_IRQPOLn
- * Address: 0xb0+n*0x100
- * SCT: yes
-*/
-#define HW_PINCTRL_IRQPOLn(n)       (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xb0+(n)*0x100 + 0x0))
-#define HW_PINCTRL_IRQPOLn_SET(n)   (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xb0+(n)*0x100 + 0x4))
-#define HW_PINCTRL_IRQPOLn_CLR(n)   (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xb0+(n)*0x100 + 0x8))
-#define HW_PINCTRL_IRQPOLn_TOG(n)   (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xb0+(n)*0x100 + 0xc))
-#define BP_PINCTRL_IRQPOLn_BITS     0
-#define BM_PINCTRL_IRQPOLn_BITS     0xffffffff
-#define BF_PINCTRL_IRQPOLn_BITS(v)  (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_PINCTRL_IRQSTATn
- * Address: 0xc0+n*0x100
- * SCT: yes
-*/
-#define HW_PINCTRL_IRQSTATn(n)      (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xc0+(n)*0x100 + 0x0))
-#define HW_PINCTRL_IRQSTATn_SET(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xc0+(n)*0x100 + 0x4))
-#define HW_PINCTRL_IRQSTATn_CLR(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xc0+(n)*0x100 + 0x8))
-#define HW_PINCTRL_IRQSTATn_TOG(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xc0+(n)*0x100 + 0xc))
-#define BP_PINCTRL_IRQSTATn_BITS    0
-#define BM_PINCTRL_IRQSTATn_BITS    0xffffffff
-#define BF_PINCTRL_IRQSTATn_BITS(v) (((v) << 0) & 0xffffffff)
-
-#endif /* __HEADERGEN__STMP3600__PINCTRL__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-power.h b/firmware/target/arm/imx233/regs/stmp3600/regs-power.h
deleted file mode 100644
index 0245a54934..0000000000
--- a/firmware/target/arm/imx233/regs/stmp3600/regs-power.h
+++ /dev/null
@@ -1,484 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3600:2.3.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__STMP3600__POWER__H__
-#define __HEADERGEN__STMP3600__POWER__H__
-
-#define REGS_POWER_BASE (0x80044000)
-
-#define REGS_POWER_VERSION "2.3.0"
-
-/**
- * Register: HW_POWER_CTRL
- * Address: 0
- * SCT: yes
-*/
-#define HW_POWER_CTRL                               (*(volatile unsigned long *)(REGS_POWER_BASE + 0x0 + 0x0))
-#define HW_POWER_CTRL_SET                           (*(volatile unsigned long *)(REGS_POWER_BASE + 0x0 + 0x4))
-#define HW_POWER_CTRL_CLR                           (*(volatile unsigned long *)(REGS_POWER_BASE + 0x0 + 0x8))
-#define HW_POWER_CTRL_TOG                           (*(volatile unsigned long *)(REGS_POWER_BASE + 0x0 + 0xc))
-#define BP_POWER_CTRL_CLKGATE                       30
-#define BM_POWER_CTRL_CLKGATE                       0x40000000
-#define BF_POWER_CTRL_CLKGATE(v)                    (((v) << 30) & 0x40000000)
-#define BP_POWER_CTRL_BATT_BO_IRQ                   8
-#define BM_POWER_CTRL_BATT_BO_IRQ                   0x100
-#define BF_POWER_CTRL_BATT_BO_IRQ(v)                (((v) << 8) & 0x100)
-#define BP_POWER_CTRL_ENIRQBATT_BO                  7
-#define BM_POWER_CTRL_ENIRQBATT_BO                  0x80
-#define BF_POWER_CTRL_ENIRQBATT_BO(v)               (((v) << 7) & 0x80)
-#define BP_POWER_CTRL_VDDIO_BO_IRQ                  6
-#define BM_POWER_CTRL_VDDIO_BO_IRQ                  0x40
-#define BF_POWER_CTRL_VDDIO_BO_IRQ(v)               (((v) << 6) & 0x40)
-#define BP_POWER_CTRL_ENIRQVDDIO_BO                 5
-#define BM_POWER_CTRL_ENIRQVDDIO_BO                 0x20
-#define BF_POWER_CTRL_ENIRQVDDIO_BO(v)              (((v) << 5) & 0x20)
-#define BP_POWER_CTRL_VDDD_BO_IRQ                   4
-#define BM_POWER_CTRL_VDDD_BO_IRQ                   0x10
-#define BF_POWER_CTRL_VDDD_BO_IRQ(v)                (((v) << 4) & 0x10)
-#define BP_POWER_CTRL_ENIRQVDDD_BO                  3
-#define BM_POWER_CTRL_ENIRQVDDD_BO                  0x8
-#define BF_POWER_CTRL_ENIRQVDDD_BO(v)               (((v) << 3) & 0x8)
-#define BP_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO       2
-#define BM_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO       0x4
-#define BF_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO(v)    (((v) << 2) & 0x4)
-#define BP_POWER_CTRL_VDD5V_GT_VDDIO_IRQ            1
-#define BM_POWER_CTRL_VDD5V_GT_VDDIO_IRQ            0x2
-#define BF_POWER_CTRL_VDD5V_GT_VDDIO_IRQ(v)         (((v) << 1) & 0x2)
-#define BP_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO          0
-#define BM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO          0x1
-#define BF_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO(v)       (((v) << 0) & 0x1)
-
-/**
- * Register: HW_POWER_5VCTRL
- * Address: 0x10
- * SCT: yes
-*/
-#define HW_POWER_5VCTRL                         (*(volatile unsigned long *)(REGS_POWER_BASE + 0x10 + 0x0))
-#define HW_POWER_5VCTRL_SET                     (*(volatile unsigned long *)(REGS_POWER_BASE + 0x10 + 0x4))
-#define HW_POWER_5VCTRL_CLR                     (*(volatile unsigned long *)(REGS_POWER_BASE + 0x10 + 0x8))
-#define HW_POWER_5VCTRL_TOG                     (*(volatile unsigned long *)(REGS_POWER_BASE + 0x10 + 0xc))
-#define BP_POWER_5VCTRL_PWDN_5VBRNOUT           21
-#define BM_POWER_5VCTRL_PWDN_5VBRNOUT           0x200000
-#define BF_POWER_5VCTRL_PWDN_5VBRNOUT(v)        (((v) << 21) & 0x200000)
-#define BP_POWER_5VCTRL_PWDN_IOBRNOUT           20
-#define BM_POWER_5VCTRL_PWDN_IOBRNOUT           0x100000
-#define BF_POWER_5VCTRL_PWDN_IOBRNOUT(v)        (((v) << 20) & 0x100000)
-#define BP_POWER_5VCTRL_DISABLE_ILIMIT          19
-#define BM_POWER_5VCTRL_DISABLE_ILIMIT          0x80000
-#define BF_POWER_5VCTRL_DISABLE_ILIMIT(v)       (((v) << 19) & 0x80000)
-#define BP_POWER_5VCTRL_DCDC_XFER               18
-#define BM_POWER_5VCTRL_DCDC_XFER               0x40000
-#define BF_POWER_5VCTRL_DCDC_XFER(v)            (((v) << 18) & 0x40000)
-#define BP_POWER_5VCTRL_EN_BATT_PULLDN          17
-#define BM_POWER_5VCTRL_EN_BATT_PULLDN          0x20000
-#define BF_POWER_5VCTRL_EN_BATT_PULLDN(v)       (((v) << 17) & 0x20000)
-#define BP_POWER_5VCTRL_VBUSVALID_5VDETECT      16
-#define BM_POWER_5VCTRL_VBUSVALID_5VDETECT      0x10000
-#define BF_POWER_5VCTRL_VBUSVALID_5VDETECT(v)   (((v) << 16) & 0x10000)
-#define BP_POWER_5VCTRL_VBUSVALID_TRSH          8
-#define BM_POWER_5VCTRL_VBUSVALID_TRSH          0x300
-#define BF_POWER_5VCTRL_VBUSVALID_TRSH(v)       (((v) << 8) & 0x300)
-#define BP_POWER_5VCTRL_USB_SUSPEND_I           7
-#define BM_POWER_5VCTRL_USB_SUSPEND_I           0x80
-#define BF_POWER_5VCTRL_USB_SUSPEND_I(v)        (((v) << 7) & 0x80)
-#define BP_POWER_5VCTRL_VBUSVALID_TO_B          6
-#define BM_POWER_5VCTRL_VBUSVALID_TO_B          0x40
-#define BF_POWER_5VCTRL_VBUSVALID_TO_B(v)       (((v) << 6) & 0x40)
-#define BP_POWER_5VCTRL_ILIMIT_EQ_ZERO          5
-#define BM_POWER_5VCTRL_ILIMIT_EQ_ZERO          0x20
-#define BF_POWER_5VCTRL_ILIMIT_EQ_ZERO(v)       (((v) << 5) & 0x20)
-#define BP_POWER_5VCTRL_OTG_PWRUP_CMPS          4
-#define BM_POWER_5VCTRL_OTG_PWRUP_CMPS          0x10
-#define BF_POWER_5VCTRL_OTG_PWRUP_CMPS(v)       (((v) << 4) & 0x10)
-#define BP_POWER_5VCTRL_EN_DCDC2                3
-#define BM_POWER_5VCTRL_EN_DCDC2                0x8
-#define BF_POWER_5VCTRL_EN_DCDC2(v)             (((v) << 3) & 0x8)
-#define BP_POWER_5VCTRL_PWD_VDDD_LINREG         2
-#define BM_POWER_5VCTRL_PWD_VDDD_LINREG         0x4
-#define BF_POWER_5VCTRL_PWD_VDDD_LINREG(v)      (((v) << 2) & 0x4)
-#define BP_POWER_5VCTRL_EN_DCDC1                1
-#define BM_POWER_5VCTRL_EN_DCDC1                0x2
-#define BF_POWER_5VCTRL_EN_DCDC1(v)             (((v) << 1) & 0x2)
-#define BP_POWER_5VCTRL_LINREG_OFFSET           0
-#define BM_POWER_5VCTRL_LINREG_OFFSET           0x1
-#define BF_POWER_5VCTRL_LINREG_OFFSET(v)        (((v) << 0) & 0x1)
-
-/**
- * Register: HW_POWER_MINPWR
- * Address: 0x20
- * SCT: yes
-*/
-#define HW_POWER_MINPWR                         (*(volatile unsigned long *)(REGS_POWER_BASE + 0x20 + 0x0))
-#define HW_POWER_MINPWR_SET                     (*(volatile unsigned long *)(REGS_POWER_BASE + 0x20 + 0x4))
-#define HW_POWER_MINPWR_CLR                     (*(volatile unsigned long *)(REGS_POWER_BASE + 0x20 + 0x8))
-#define HW_POWER_MINPWR_TOG                     (*(volatile unsigned long *)(REGS_POWER_BASE + 0x20 + 0xc))
-#define BP_POWER_MINPWR_TEST_DISCHRG_VBUS       23
-#define BM_POWER_MINPWR_TEST_DISCHRG_VBUS       0x800000
-#define BF_POWER_MINPWR_TEST_DISCHRG_VBUS(v)    (((v) << 23) & 0x800000)
-#define BP_POWER_MINPWR_TEST_CHRG_VBUS          22
-#define BM_POWER_MINPWR_TEST_CHRG_VBUS          0x400000
-#define BF_POWER_MINPWR_TEST_CHRG_VBUS(v)       (((v) << 22) & 0x400000)
-#define BP_POWER_MINPWR_DC2_TST                 21
-#define BM_POWER_MINPWR_DC2_TST                 0x200000
-#define BF_POWER_MINPWR_DC2_TST(v)              (((v) << 21) & 0x200000)
-#define BP_POWER_MINPWR_DC1_TST                 20
-#define BM_POWER_MINPWR_DC1_TST                 0x100000
-#define BF_POWER_MINPWR_DC1_TST(v)              (((v) << 20) & 0x100000)
-#define BP_POWER_MINPWR_PERIPHERALSWOFF         19
-#define BM_POWER_MINPWR_PERIPHERALSWOFF         0x80000
-#define BF_POWER_MINPWR_PERIPHERALSWOFF(v)      (((v) << 19) & 0x80000)
-#define BP_POWER_MINPWR_TOGGLE_DIF              18
-#define BM_POWER_MINPWR_TOGGLE_DIF              0x40000
-#define BF_POWER_MINPWR_TOGGLE_DIF(v)           (((v) << 18) & 0x40000)
-#define BP_POWER_MINPWR_DISABLE_VDDIOSTEP       17
-#define BM_POWER_MINPWR_DISABLE_VDDIOSTEP       0x20000
-#define BF_POWER_MINPWR_DISABLE_VDDIOSTEP(v)    (((v) << 17) & 0x20000)
-#define BP_POWER_MINPWR_DISABLE_VDDSTEP         16
-#define BM_POWER_MINPWR_DISABLE_VDDSTEP         0x10000
-#define BF_POWER_MINPWR_DISABLE_VDDSTEP(v)      (((v) << 16) & 0x10000)
-#define BP_POWER_MINPWR_SEL_PLLDIV16CLK         9
-#define BM_POWER_MINPWR_SEL_PLLDIV16CLK         0x200
-#define BF_POWER_MINPWR_SEL_PLLDIV16CLK(v)      (((v) << 9) & 0x200)
-#define BP_POWER_MINPWR_PWD_VDDIOBO             8
-#define BM_POWER_MINPWR_PWD_VDDIOBO             0x100
-#define BF_POWER_MINPWR_PWD_VDDIOBO(v)          (((v) << 8) & 0x100)
-#define BP_POWER_MINPWR_LESSANA_I               7
-#define BM_POWER_MINPWR_LESSANA_I               0x80
-#define BF_POWER_MINPWR_LESSANA_I(v)            (((v) << 7) & 0x80)
-#define BP_POWER_MINPWR_DC1_HALFFETS            6
-#define BM_POWER_MINPWR_DC1_HALFFETS            0x40
-#define BF_POWER_MINPWR_DC1_HALFFETS(v)         (((v) << 6) & 0x40)
-#define BP_POWER_MINPWR_DC2_STOPCLK             5
-#define BM_POWER_MINPWR_DC2_STOPCLK             0x20
-#define BF_POWER_MINPWR_DC2_STOPCLK(v)          (((v) << 5) & 0x20)
-#define BP_POWER_MINPWR_DC1_STOPCLK             4
-#define BM_POWER_MINPWR_DC1_STOPCLK             0x10
-#define BF_POWER_MINPWR_DC1_STOPCLK(v)          (((v) << 4) & 0x10)
-#define BP_POWER_MINPWR_EN_DC2_PFM              3
-#define BM_POWER_MINPWR_EN_DC2_PFM              0x8
-#define BF_POWER_MINPWR_EN_DC2_PFM(v)           (((v) << 3) & 0x8)
-#define BP_POWER_MINPWR_EN_DC1_PFM              2
-#define BM_POWER_MINPWR_EN_DC1_PFM              0x4
-#define BF_POWER_MINPWR_EN_DC1_PFM(v)           (((v) << 2) & 0x4)
-#define BP_POWER_MINPWR_DC2_HALFCLK             1
-#define BM_POWER_MINPWR_DC2_HALFCLK             0x2
-#define BF_POWER_MINPWR_DC2_HALFCLK(v)          (((v) << 1) & 0x2)
-#define BP_POWER_MINPWR_DC1_HALFCLK             0
-#define BM_POWER_MINPWR_DC1_HALFCLK             0x1
-#define BF_POWER_MINPWR_DC1_HALFCLK(v)          (((v) << 0) & 0x1)
-
-/**
- * Register: HW_POWER_BATTCHRG
- * Address: 0x30
- * SCT: yes
-*/
-#define HW_POWER_BATTCHRG                   (*(volatile unsigned long *)(REGS_POWER_BASE + 0x30 + 0x0))
-#define HW_POWER_BATTCHRG_SET               (*(volatile unsigned long *)(REGS_POWER_BASE + 0x30 + 0x4))
-#define HW_POWER_BATTCHRG_CLR               (*(volatile unsigned long *)(REGS_POWER_BASE + 0x30 + 0x8))
-#define HW_POWER_BATTCHRG_TOG               (*(volatile unsigned long *)(REGS_POWER_BASE + 0x30 + 0xc))
-#define BP_POWER_BATTCHRG_CHRG_STS_OFF      19
-#define BM_POWER_BATTCHRG_CHRG_STS_OFF      0x80000
-#define BF_POWER_BATTCHRG_CHRG_STS_OFF(v)   (((v) << 19) & 0x80000)
-#define BP_POWER_BATTCHRG_LIION_4P1         18
-#define BM_POWER_BATTCHRG_LIION_4P1         0x40000
-#define BF_POWER_BATTCHRG_LIION_4P1(v)      (((v) << 18) & 0x40000)
-#define BP_POWER_BATTCHRG_USE_EXTERN_R      17
-#define BM_POWER_BATTCHRG_USE_EXTERN_R      0x20000
-#define BF_POWER_BATTCHRG_USE_EXTERN_R(v)   (((v) << 17) & 0x20000)
-#define BP_POWER_BATTCHRG_PWD_BATTCHRG      16
-#define BM_POWER_BATTCHRG_PWD_BATTCHRG      0x10000
-#define BF_POWER_BATTCHRG_PWD_BATTCHRG(v)   (((v) << 16) & 0x10000)
-#define BP_POWER_BATTCHRG_STOP_ILIMIT       8
-#define BM_POWER_BATTCHRG_STOP_ILIMIT       0xf00
-#define BF_POWER_BATTCHRG_STOP_ILIMIT(v)    (((v) << 8) & 0xf00)
-#define BP_POWER_BATTCHRG_BATTCHRG_I        0
-#define BM_POWER_BATTCHRG_BATTCHRG_I        0x3f
-#define BF_POWER_BATTCHRG_BATTCHRG_I(v)     (((v) << 0) & 0x3f)
-
-/**
- * Register: HW_POWER_VDDCTRL
- * Address: 0x40
- * SCT: no
-*/
-#define HW_POWER_VDDCTRL                (*(volatile unsigned long *)(REGS_POWER_BASE + 0x40))
-#define BP_POWER_VDDCTRL_VDDIO_BO       24
-#define BM_POWER_VDDCTRL_VDDIO_BO       0x1f000000
-#define BF_POWER_VDDCTRL_VDDIO_BO(v)    (((v) << 24) & 0x1f000000)
-#define BP_POWER_VDDCTRL_VDDIO_TRG      16
-#define BM_POWER_VDDCTRL_VDDIO_TRG      0x1f0000
-#define BF_POWER_VDDCTRL_VDDIO_TRG(v)   (((v) << 16) & 0x1f0000)
-#define BP_POWER_VDDCTRL_VDDD_BO        8
-#define BM_POWER_VDDCTRL_VDDD_BO        0x1f00
-#define BF_POWER_VDDCTRL_VDDD_BO(v)     (((v) << 8) & 0x1f00)
-#define BP_POWER_VDDCTRL_VDDD_TRG       0
-#define BM_POWER_VDDCTRL_VDDD_TRG       0x1f
-#define BF_POWER_VDDCTRL_VDDD_TRG(v)    (((v) << 0) & 0x1f)
-
-/**
- * Register: HW_POWER_DC1MULTOUT
- * Address: 0x50
- * SCT: no
-*/
-#define HW_POWER_DC1MULTOUT                 (*(volatile unsigned long *)(REGS_POWER_BASE + 0x50))
-#define BP_POWER_DC1MULTOUT_FUNCV           16
-#define BM_POWER_DC1MULTOUT_FUNCV           0x1ff0000
-#define BF_POWER_DC1MULTOUT_FUNCV(v)        (((v) << 16) & 0x1ff0000)
-#define BP_POWER_DC1MULTOUT_EN_BATADJ       8
-#define BM_POWER_DC1MULTOUT_EN_BATADJ       0x100
-#define BF_POWER_DC1MULTOUT_EN_BATADJ(v)    (((v) << 8) & 0x100)
-#define BP_POWER_DC1MULTOUT_ADJTN           0
-#define BM_POWER_DC1MULTOUT_ADJTN           0xf
-#define BF_POWER_DC1MULTOUT_ADJTN(v)        (((v) << 0) & 0xf)
-
-/**
- * Register: HW_POWER_DC1LIMITS
- * Address: 0x60
- * SCT: no
-*/
-#define HW_POWER_DC1LIMITS                      (*(volatile unsigned long *)(REGS_POWER_BASE + 0x60))
-#define BP_POWER_DC1LIMITS_EN_PFETOFF           24
-#define BM_POWER_DC1LIMITS_EN_PFETOFF           0x1000000
-#define BF_POWER_DC1LIMITS_EN_PFETOFF(v)        (((v) << 24) & 0x1000000)
-#define BP_POWER_DC1LIMITS_POSLIMIT_BOOST       16
-#define BM_POWER_DC1LIMITS_POSLIMIT_BOOST       0x7f0000
-#define BF_POWER_DC1LIMITS_POSLIMIT_BOOST(v)    (((v) << 16) & 0x7f0000)
-#define BP_POWER_DC1LIMITS_POSLIMIT_BUCK        8
-#define BM_POWER_DC1LIMITS_POSLIMIT_BUCK        0x7f00
-#define BF_POWER_DC1LIMITS_POSLIMIT_BUCK(v)     (((v) << 8) & 0x7f00)
-#define BP_POWER_DC1LIMITS_NEGLIMIT             0
-#define BM_POWER_DC1LIMITS_NEGLIMIT             0x7f
-#define BF_POWER_DC1LIMITS_NEGLIMIT(v)          (((v) << 0) & 0x7f)
-
-/**
- * Register: HW_POWER_DC2LIMITS
- * Address: 0x70
- * SCT: no
-*/
-#define HW_POWER_DC2LIMITS                      (*(volatile unsigned long *)(REGS_POWER_BASE + 0x70))
-#define BP_POWER_DC2LIMITS_EN_BOOST             24
-#define BM_POWER_DC2LIMITS_EN_BOOST             0x1000000
-#define BF_POWER_DC2LIMITS_EN_BOOST(v)          (((v) << 24) & 0x1000000)
-#define BP_POWER_DC2LIMITS_POSLIMIT_BOOST       16
-#define BM_POWER_DC2LIMITS_POSLIMIT_BOOST       0x7f0000
-#define BF_POWER_DC2LIMITS_POSLIMIT_BOOST(v)    (((v) << 16) & 0x7f0000)
-#define BP_POWER_DC2LIMITS_POSLIMIT_BUCK        8
-#define BM_POWER_DC2LIMITS_POSLIMIT_BUCK        0x7f00
-#define BF_POWER_DC2LIMITS_POSLIMIT_BUCK(v)     (((v) << 8) & 0x7f00)
-#define BP_POWER_DC2LIMITS_NEGLIMIT             0
-#define BM_POWER_DC2LIMITS_NEGLIMIT             0x7f
-#define BF_POWER_DC2LIMITS_NEGLIMIT(v)          (((v) << 0) & 0x7f)
-
-/**
- * Register: HW_POWER_LOOPCTRL
- * Address: 0x80
- * SCT: yes
-*/
-#define HW_POWER_LOOPCTRL                   (*(volatile unsigned long *)(REGS_POWER_BASE + 0x80 + 0x0))
-#define HW_POWER_LOOPCTRL_SET               (*(volatile unsigned long *)(REGS_POWER_BASE + 0x80 + 0x4))
-#define HW_POWER_LOOPCTRL_CLR               (*(volatile unsigned long *)(REGS_POWER_BASE + 0x80 + 0x8))
-#define HW_POWER_LOOPCTRL_TOG               (*(volatile unsigned long *)(REGS_POWER_BASE + 0x80 + 0xc))
-#define BP_POWER_LOOPCTRL_TRAN_NOHYST       30
-#define BM_POWER_LOOPCTRL_TRAN_NOHYST       0x40000000
-#define BF_POWER_LOOPCTRL_TRAN_NOHYST(v)    (((v) << 30) & 0x40000000)
-#define BP_POWER_LOOPCTRL_HYST_SIGN         29
-#define BM_POWER_LOOPCTRL_HYST_SIGN         0x20000000
-#define BF_POWER_LOOPCTRL_HYST_SIGN(v)      (((v) << 29) & 0x20000000)
-#define BP_POWER_LOOPCTRL_EN_CMP_HYST       28
-#define BM_POWER_LOOPCTRL_EN_CMP_HYST       0x10000000
-#define BF_POWER_LOOPCTRL_EN_CMP_HYST(v)    (((v) << 28) & 0x10000000)
-#define BP_POWER_LOOPCTRL_EN_DC2_RCSCALE    27
-#define BM_POWER_LOOPCTRL_EN_DC2_RCSCALE    0x8000000
-#define BF_POWER_LOOPCTRL_EN_DC2_RCSCALE(v) (((v) << 27) & 0x8000000)
-#define BP_POWER_LOOPCTRL_EN_DC1_RCSCALE    26
-#define BM_POWER_LOOPCTRL_EN_DC1_RCSCALE    0x4000000
-#define BF_POWER_LOOPCTRL_EN_DC1_RCSCALE(v) (((v) << 26) & 0x4000000)
-#define BP_POWER_LOOPCTRL_RC_SIGN           25
-#define BM_POWER_LOOPCTRL_RC_SIGN           0x2000000
-#define BF_POWER_LOOPCTRL_RC_SIGN(v)        (((v) << 25) & 0x2000000)
-#define BP_POWER_LOOPCTRL_EN_RCSCALE        24
-#define BM_POWER_LOOPCTRL_EN_RCSCALE        0x1000000
-#define BF_POWER_LOOPCTRL_EN_RCSCALE(v)     (((v) << 24) & 0x1000000)
-#define BP_POWER_LOOPCTRL_DC2_FF            20
-#define BM_POWER_LOOPCTRL_DC2_FF            0x700000
-#define BF_POWER_LOOPCTRL_DC2_FF(v)         (((v) << 20) & 0x700000)
-#define BP_POWER_LOOPCTRL_DC2_R             16
-#define BM_POWER_LOOPCTRL_DC2_R             0xf0000
-#define BF_POWER_LOOPCTRL_DC2_R(v)          (((v) << 16) & 0xf0000)
-#define BP_POWER_LOOPCTRL_DC2_C             12
-#define BM_POWER_LOOPCTRL_DC2_C             0x3000
-#define BF_POWER_LOOPCTRL_DC2_C(v)          (((v) << 12) & 0x3000)
-#define BP_POWER_LOOPCTRL_DC1_FF            8
-#define BM_POWER_LOOPCTRL_DC1_FF            0x700
-#define BF_POWER_LOOPCTRL_DC1_FF(v)         (((v) << 8) & 0x700)
-#define BP_POWER_LOOPCTRL_DC1_R             4
-#define BM_POWER_LOOPCTRL_DC1_R             0xf0
-#define BF_POWER_LOOPCTRL_DC1_R(v)          (((v) << 4) & 0xf0)
-#define BP_POWER_LOOPCTRL_DC1_C             0
-#define BM_POWER_LOOPCTRL_DC1_C             0x3
-#define BF_POWER_LOOPCTRL_DC1_C(v)          (((v) << 0) & 0x3)
-
-/**
- * Register: HW_POWER_STS
- * Address: 0x90
- * SCT: no
-*/
-#define HW_POWER_STS                        (*(volatile unsigned long *)(REGS_POWER_BASE + 0x90))
-#define BP_POWER_STS_BATT_CHRG_PRESENT      31
-#define BM_POWER_STS_BATT_CHRG_PRESENT      0x80000000
-#define BF_POWER_STS_BATT_CHRG_PRESENT(v)   (((v) << 31) & 0x80000000)
-#define BP_POWER_STS_MODE                   20
-#define BM_POWER_STS_MODE                   0x300000
-#define BF_POWER_STS_MODE(v)                (((v) << 20) & 0x300000)
-#define BP_POWER_STS_BATT_BO                16
-#define BM_POWER_STS_BATT_BO                0x10000
-#define BF_POWER_STS_BATT_BO(v)             (((v) << 16) & 0x10000)
-#define BP_POWER_STS_CHRGSTS                14
-#define BM_POWER_STS_CHRGSTS                0x4000
-#define BF_POWER_STS_CHRGSTS(v)             (((v) << 14) & 0x4000)
-#define BP_POWER_STS_DC2_OK                 13
-#define BM_POWER_STS_DC2_OK                 0x2000
-#define BF_POWER_STS_DC2_OK(v)              (((v) << 13) & 0x2000)
-#define BP_POWER_STS_DC1_OK                 12
-#define BM_POWER_STS_DC1_OK                 0x1000
-#define BF_POWER_STS_DC1_OK(v)              (((v) << 12) & 0x1000)
-#define BP_POWER_STS_VDDIO_BO               9
-#define BM_POWER_STS_VDDIO_BO               0x200
-#define BF_POWER_STS_VDDIO_BO(v)            (((v) << 9) & 0x200)
-#define BP_POWER_STS_VDDD_BO                8
-#define BM_POWER_STS_VDDD_BO                0x100
-#define BF_POWER_STS_VDDD_BO(v)             (((v) << 8) & 0x100)
-#define BP_POWER_STS_VDD5V_GT_VDDIO         4
-#define BM_POWER_STS_VDD5V_GT_VDDIO         0x10
-#define BF_POWER_STS_VDD5V_GT_VDDIO(v)      (((v) << 4) & 0x10)
-#define BP_POWER_STS_AVALID                 3
-#define BM_POWER_STS_AVALID                 0x8
-#define BF_POWER_STS_AVALID(v)              (((v) << 3) & 0x8)
-#define BP_POWER_STS_BVALID                 2
-#define BM_POWER_STS_BVALID                 0x4
-#define BF_POWER_STS_BVALID(v)              (((v) << 2) & 0x4)
-#define BP_POWER_STS_VBUSVALID              1
-#define BM_POWER_STS_VBUSVALID              0x2
-#define BF_POWER_STS_VBUSVALID(v)           (((v) << 1) & 0x2)
-#define BP_POWER_STS_SESSEND                0
-#define BM_POWER_STS_SESSEND                0x1
-#define BF_POWER_STS_SESSEND(v)             (((v) << 0) & 0x1)
-
-/**
- * Register: HW_POWER_SPEEDTEMP
- * Address: 0xa0
- * SCT: yes
-*/
-#define HW_POWER_SPEEDTEMP                  (*(volatile unsigned long *)(REGS_POWER_BASE + 0xa0 + 0x0))
-#define HW_POWER_SPEEDTEMP_SET              (*(volatile unsigned long *)(REGS_POWER_BASE + 0xa0 + 0x4))
-#define HW_POWER_SPEEDTEMP_CLR              (*(volatile unsigned long *)(REGS_POWER_BASE + 0xa0 + 0x8))
-#define HW_POWER_SPEEDTEMP_TOG              (*(volatile unsigned long *)(REGS_POWER_BASE + 0xa0 + 0xc))
-#define BP_POWER_SPEEDTEMP_SPEED_STS1       24
-#define BM_POWER_SPEEDTEMP_SPEED_STS1       0xff000000
-#define BF_POWER_SPEEDTEMP_SPEED_STS1(v)    (((v) << 24) & 0xff000000)
-#define BP_POWER_SPEEDTEMP_SPEED_STS2       16
-#define BM_POWER_SPEEDTEMP_SPEED_STS2       0xff0000
-#define BF_POWER_SPEEDTEMP_SPEED_STS2(v)    (((v) << 16) & 0xff0000)
-#define BP_POWER_SPEEDTEMP_TEMP_STS         8
-#define BM_POWER_SPEEDTEMP_TEMP_STS         0xf00
-#define BF_POWER_SPEEDTEMP_TEMP_STS(v)      (((v) << 8) & 0xf00)
-#define BP_POWER_SPEEDTEMP_SPEED_CTRL       4
-#define BM_POWER_SPEEDTEMP_SPEED_CTRL       0x30
-#define BF_POWER_SPEEDTEMP_SPEED_CTRL(v)    (((v) << 4) & 0x30)
-#define BP_POWER_SPEEDTEMP_TEMP_CTRL        0
-#define BM_POWER_SPEEDTEMP_TEMP_CTRL        0xf
-#define BF_POWER_SPEEDTEMP_TEMP_CTRL(v)     (((v) << 0) & 0xf)
-
-/**
- * Register: HW_POWER_BATTMONITOR
- * Address: 0xb0
- * SCT: no
-*/
-#define HW_POWER_BATTMONITOR                    (*(volatile unsigned long *)(REGS_POWER_BASE + 0xb0))
-#define BP_POWER_BATTMONITOR_BATT_VAL           16
-#define BM_POWER_BATTMONITOR_BATT_VAL           0x3ff0000
-#define BF_POWER_BATTMONITOR_BATT_VAL(v)        (((v) << 16) & 0x3ff0000)
-#define BP_POWER_BATTMONITOR_PWDN_BATTBRNOUT    9
-#define BM_POWER_BATTMONITOR_PWDN_BATTBRNOUT    0x200
-#define BF_POWER_BATTMONITOR_PWDN_BATTBRNOUT(v) (((v) << 9) & 0x200)
-#define BP_POWER_BATTMONITOR_BRWNOUT_PWD        8
-#define BM_POWER_BATTMONITOR_BRWNOUT_PWD        0x100
-#define BF_POWER_BATTMONITOR_BRWNOUT_PWD(v)     (((v) << 8) & 0x100)
-#define BP_POWER_BATTMONITOR_BRWNOUT_LVL        0
-#define BM_POWER_BATTMONITOR_BRWNOUT_LVL        0xf
-#define BF_POWER_BATTMONITOR_BRWNOUT_LVL(v)     (((v) << 0) & 0xf)
-
-/**
- * Register: HW_POWER_RESET
- * Address: 0xc0
- * SCT: yes
-*/
-#define HW_POWER_RESET              (*(volatile unsigned long *)(REGS_POWER_BASE + 0xc0 + 0x0))
-#define HW_POWER_RESET_SET          (*(volatile unsigned long *)(REGS_POWER_BASE + 0xc0 + 0x4))
-#define HW_POWER_RESET_CLR          (*(volatile unsigned long *)(REGS_POWER_BASE + 0xc0 + 0x8))
-#define HW_POWER_RESET_TOG          (*(volatile unsigned long *)(REGS_POWER_BASE + 0xc0 + 0xc))
-#define BP_POWER_RESET_UNLOCK       16
-#define BM_POWER_RESET_UNLOCK       0xffff0000
-#define BV_POWER_RESET_UNLOCK__KEY  0x3e77
-#define BF_POWER_RESET_UNLOCK(v)    (((v) << 16) & 0xffff0000)
-#define BF_POWER_RESET_UNLOCK_V(v)  ((BV_POWER_RESET_UNLOCK__##v << 16) & 0xffff0000)
-#define BP_POWER_RESET_PWD_OFF      4
-#define BM_POWER_RESET_PWD_OFF      0x10
-#define BF_POWER_RESET_PWD_OFF(v)   (((v) << 4) & 0x10)
-#define BP_POWER_RESET_POR          3
-#define BM_POWER_RESET_POR          0x8
-#define BF_POWER_RESET_POR(v)       (((v) << 3) & 0x8)
-#define BP_POWER_RESET_PWD          2
-#define BM_POWER_RESET_PWD          0x4
-#define BF_POWER_RESET_PWD(v)       (((v) << 2) & 0x4)
-#define BP_POWER_RESET_RST_DIG      1
-#define BM_POWER_RESET_RST_DIG      0x2
-#define BF_POWER_RESET_RST_DIG(v)   (((v) << 1) & 0x2)
-#define BP_POWER_RESET_RST_ALL      0
-#define BM_POWER_RESET_RST_ALL      0x1
-#define BF_POWER_RESET_RST_ALL(v)   (((v) << 0) & 0x1)
-
-/**
- * Register: HW_POWER_DEBUG
- * Address: 0xd0
- * SCT: yes
-*/
-#define HW_POWER_DEBUG                      (*(volatile unsigned long *)(REGS_POWER_BASE + 0xd0 + 0x0))
-#define HW_POWER_DEBUG_SET                  (*(volatile unsigned long *)(REGS_POWER_BASE + 0xd0 + 0x4))
-#define HW_POWER_DEBUG_CLR                  (*(volatile unsigned long *)(REGS_POWER_BASE + 0xd0 + 0x8))
-#define HW_POWER_DEBUG_TOG                  (*(volatile unsigned long *)(REGS_POWER_BASE + 0xd0 + 0xc))
-#define BP_POWER_DEBUG_ENCTRLVBUS           4
-#define BM_POWER_DEBUG_ENCTRLVBUS           0x10
-#define BF_POWER_DEBUG_ENCTRLVBUS(v)        (((v) << 4) & 0x10)
-#define BP_POWER_DEBUG_VBUSVALIDPIOLOCK     3
-#define BM_POWER_DEBUG_VBUSVALIDPIOLOCK     0x8
-#define BF_POWER_DEBUG_VBUSVALIDPIOLOCK(v)  (((v) << 3) & 0x8)
-#define BP_POWER_DEBUG_AVALIDPIOLOCK        2
-#define BM_POWER_DEBUG_AVALIDPIOLOCK        0x4
-#define BF_POWER_DEBUG_AVALIDPIOLOCK(v)     (((v) << 2) & 0x4)
-#define BP_POWER_DEBUG_BVALIDPIOLOCK        1
-#define BM_POWER_DEBUG_BVALIDPIOLOCK        0x2
-#define BF_POWER_DEBUG_BVALIDPIOLOCK(v)     (((v) << 1) & 0x2)
-#define BP_POWER_DEBUG_SESSENDPIOLOCK       0
-#define BM_POWER_DEBUG_SESSENDPIOLOCK       0x1
-#define BF_POWER_DEBUG_SESSENDPIOLOCK(v)    (((v) << 0) & 0x1)
-
-#endif /* __HEADERGEN__STMP3600__POWER__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-pwm.h b/firmware/target/arm/imx233/regs/stmp3600/regs-pwm.h
deleted file mode 100644
index 748f9159a9..0000000000
--- a/firmware/target/arm/imx233/regs/stmp3600/regs-pwm.h
+++ /dev/null
@@ -1,134 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3600:2.3.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__STMP3600__PWM__H__
-#define __HEADERGEN__STMP3600__PWM__H__
-
-#define REGS_PWM_BASE (0x80064000)
-
-#define REGS_PWM_VERSION "2.3.0"
-
-/**
- * Register: HW_PWM_CTRL
- * Address: 0
- * SCT: yes
-*/
-#define HW_PWM_CTRL                 (*(volatile unsigned long *)(REGS_PWM_BASE + 0x0 + 0x0))
-#define HW_PWM_CTRL_SET             (*(volatile unsigned long *)(REGS_PWM_BASE + 0x0 + 0x4))
-#define HW_PWM_CTRL_CLR             (*(volatile unsigned long *)(REGS_PWM_BASE + 0x0 + 0x8))
-#define HW_PWM_CTRL_TOG             (*(volatile unsigned long *)(REGS_PWM_BASE + 0x0 + 0xc))
-#define BP_PWM_CTRL_SFTRST          31
-#define BM_PWM_CTRL_SFTRST          0x80000000
-#define BF_PWM_CTRL_SFTRST(v)       (((v) << 31) & 0x80000000)
-#define BP_PWM_CTRL_CLKGATE         30
-#define BM_PWM_CTRL_CLKGATE         0x40000000
-#define BF_PWM_CTRL_CLKGATE(v)      (((v) << 30) & 0x40000000)
-#define BP_PWM_CTRL_PWM4_PRESENT    29
-#define BM_PWM_CTRL_PWM4_PRESENT    0x20000000
-#define BF_PWM_CTRL_PWM4_PRESENT(v) (((v) << 29) & 0x20000000)
-#define BP_PWM_CTRL_PWM3_PRESENT    28
-#define BM_PWM_CTRL_PWM3_PRESENT    0x10000000
-#define BF_PWM_CTRL_PWM3_PRESENT(v) (((v) << 28) & 0x10000000)
-#define BP_PWM_CTRL_PWM2_PRESENT    27
-#define BM_PWM_CTRL_PWM2_PRESENT    0x8000000
-#define BF_PWM_CTRL_PWM2_PRESENT(v) (((v) << 27) & 0x8000000)
-#define BP_PWM_CTRL_PWM1_PRESENT    26
-#define BM_PWM_CTRL_PWM1_PRESENT    0x4000000
-#define BF_PWM_CTRL_PWM1_PRESENT(v) (((v) << 26) & 0x4000000)
-#define BP_PWM_CTRL_PWM0_PRESENT    25
-#define BM_PWM_CTRL_PWM0_PRESENT    0x2000000
-#define BF_PWM_CTRL_PWM0_PRESENT(v) (((v) << 25) & 0x2000000)
-#define BP_PWM_CTRL_PWM4_ENABLE     4
-#define BM_PWM_CTRL_PWM4_ENABLE     0x10
-#define BF_PWM_CTRL_PWM4_ENABLE(v)  (((v) << 4) & 0x10)
-#define BP_PWM_CTRL_PWM3_ENABLE     3
-#define BM_PWM_CTRL_PWM3_ENABLE     0x8
-#define BF_PWM_CTRL_PWM3_ENABLE(v)  (((v) << 3) & 0x8)
-#define BP_PWM_CTRL_PWM2_ENABLE     2
-#define BM_PWM_CTRL_PWM2_ENABLE     0x4
-#define BF_PWM_CTRL_PWM2_ENABLE(v)  (((v) << 2) & 0x4)
-#define BP_PWM_CTRL_PWM1_ENABLE     1
-#define BM_PWM_CTRL_PWM1_ENABLE     0x2
-#define BF_PWM_CTRL_PWM1_ENABLE(v)  (((v) << 1) & 0x2)
-#define BP_PWM_CTRL_PWM0_ENABLE     0
-#define BM_PWM_CTRL_PWM0_ENABLE     0x1
-#define BF_PWM_CTRL_PWM0_ENABLE(v)  (((v) << 0) & 0x1)
-
-/**
- * Register: HW_PWM_ACTIVEn
- * Address: 0x10+n*0x20
- * SCT: yes
-*/
-#define HW_PWM_ACTIVEn(n)           (*(volatile unsigned long *)(REGS_PWM_BASE + 0x10+(n)*0x20 + 0x0))
-#define HW_PWM_ACTIVEn_SET(n)       (*(volatile unsigned long *)(REGS_PWM_BASE + 0x10+(n)*0x20 + 0x4))
-#define HW_PWM_ACTIVEn_CLR(n)       (*(volatile unsigned long *)(REGS_PWM_BASE + 0x10+(n)*0x20 + 0x8))
-#define HW_PWM_ACTIVEn_TOG(n)       (*(volatile unsigned long *)(REGS_PWM_BASE + 0x10+(n)*0x20 + 0xc))
-#define BP_PWM_ACTIVEn_INACTIVE     16
-#define BM_PWM_ACTIVEn_INACTIVE     0xffff0000
-#define BF_PWM_ACTIVEn_INACTIVE(v)  (((v) << 16) & 0xffff0000)
-#define BP_PWM_ACTIVEn_ACTIVE       0
-#define BM_PWM_ACTIVEn_ACTIVE       0xffff
-#define BF_PWM_ACTIVEn_ACTIVE(v)    (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_PWM_PERIODn
- * Address: 0x20+n*0x20
- * SCT: yes
-*/
-#define HW_PWM_PERIODn(n)                   (*(volatile unsigned long *)(REGS_PWM_BASE + 0x20+(n)*0x20 + 0x0))
-#define HW_PWM_PERIODn_SET(n)               (*(volatile unsigned long *)(REGS_PWM_BASE + 0x20+(n)*0x20 + 0x4))
-#define HW_PWM_PERIODn_CLR(n)               (*(volatile unsigned long *)(REGS_PWM_BASE + 0x20+(n)*0x20 + 0x8))
-#define HW_PWM_PERIODn_TOG(n)               (*(volatile unsigned long *)(REGS_PWM_BASE + 0x20+(n)*0x20 + 0xc))
-#define BP_PWM_PERIODn_MATT                 23
-#define BM_PWM_PERIODn_MATT                 0x800000
-#define BF_PWM_PERIODn_MATT(v)              (((v) << 23) & 0x800000)
-#define BP_PWM_PERIODn_CDIV                 20
-#define BM_PWM_PERIODn_CDIV                 0x700000
-#define BV_PWM_PERIODn_CDIV__DIV_1          0x0
-#define BV_PWM_PERIODn_CDIV__DIV_2          0x1
-#define BV_PWM_PERIODn_CDIV__DIV_4          0x2
-#define BV_PWM_PERIODn_CDIV__DIV_8          0x3
-#define BV_PWM_PERIODn_CDIV__DIV_16         0x4
-#define BV_PWM_PERIODn_CDIV__DIV_64         0x5
-#define BV_PWM_PERIODn_CDIV__DIV_256        0x6
-#define BV_PWM_PERIODn_CDIV__DIV_1024       0x7
-#define BF_PWM_PERIODn_CDIV(v)              (((v) << 20) & 0x700000)
-#define BF_PWM_PERIODn_CDIV_V(v)            ((BV_PWM_PERIODn_CDIV__##v << 20) & 0x700000)
-#define BP_PWM_PERIODn_INACTIVE_STATE       18
-#define BM_PWM_PERIODn_INACTIVE_STATE       0xc0000
-#define BV_PWM_PERIODn_INACTIVE_STATE__HI_Z 0x0
-#define BV_PWM_PERIODn_INACTIVE_STATE__0    0x2
-#define BV_PWM_PERIODn_INACTIVE_STATE__1    0x3
-#define BF_PWM_PERIODn_INACTIVE_STATE(v)    (((v) << 18) & 0xc0000)
-#define BF_PWM_PERIODn_INACTIVE_STATE_V(v)  ((BV_PWM_PERIODn_INACTIVE_STATE__##v << 18) & 0xc0000)
-#define BP_PWM_PERIODn_ACTIVE_STATE         16
-#define BM_PWM_PERIODn_ACTIVE_STATE         0x30000
-#define BV_PWM_PERIODn_ACTIVE_STATE__HI_Z   0x0
-#define BV_PWM_PERIODn_ACTIVE_STATE__0      0x2
-#define BV_PWM_PERIODn_ACTIVE_STATE__1      0x3
-#define BF_PWM_PERIODn_ACTIVE_STATE(v)      (((v) << 16) & 0x30000)
-#define BF_PWM_PERIODn_ACTIVE_STATE_V(v)    ((BV_PWM_PERIODn_ACTIVE_STATE__##v << 16) & 0x30000)
-#define BP_PWM_PERIODn_PERIOD               0
-#define BM_PWM_PERIODn_PERIOD               0xffff
-#define BF_PWM_PERIODn_PERIOD(v)            (((v) << 0) & 0xffff)
-
-#endif /* __HEADERGEN__STMP3600__PWM__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-rtc.h b/firmware/target/arm/imx233/regs/stmp3600/regs-rtc.h
deleted file mode 100644
index b83a5bd6c4..0000000000
--- a/firmware/target/arm/imx233/regs/stmp3600/regs-rtc.h
+++ /dev/null
@@ -1,304 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3600:2.3.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__STMP3600__RTC__H__
-#define __HEADERGEN__STMP3600__RTC__H__
-
-#define REGS_RTC_BASE (0x8005c000)
-
-#define REGS_RTC_VERSION "2.3.0"
-
-/**
- * Register: HW_RTC_CTRL
- * Address: 0
- * SCT: yes
-*/
-#define HW_RTC_CTRL                                 (*(volatile unsigned long *)(REGS_RTC_BASE + 0x0 + 0x0))
-#define HW_RTC_CTRL_SET                             (*(volatile unsigned long *)(REGS_RTC_BASE + 0x0 + 0x4))
-#define HW_RTC_CTRL_CLR                             (*(volatile unsigned long *)(REGS_RTC_BASE + 0x0 + 0x8))
-#define HW_RTC_CTRL_TOG                             (*(volatile unsigned long *)(REGS_RTC_BASE + 0x0 + 0xc))
-#define BP_RTC_CTRL_SFTRST                          31
-#define BM_RTC_CTRL_SFTRST                          0x80000000
-#define BF_RTC_CTRL_SFTRST(v)                       (((v) << 31) & 0x80000000)
-#define BP_RTC_CTRL_CLKGATE                         30
-#define BM_RTC_CTRL_CLKGATE                         0x40000000
-#define BF_RTC_CTRL_CLKGATE(v)                      (((v) << 30) & 0x40000000)
-#define BP_RTC_CTRL_CLKDIV                          24
-#define BM_RTC_CTRL_CLKDIV                          0xf000000
-#define BF_RTC_CTRL_CLKDIV(v)                       (((v) << 24) & 0xf000000)
-#define BP_RTC_CTRL_SUPPRESS_COPY2ANALOG            6
-#define BM_RTC_CTRL_SUPPRESS_COPY2ANALOG            0x40
-#define BV_RTC_CTRL_SUPPRESS_COPY2ANALOG__NORMAL    0x0
-#define BV_RTC_CTRL_SUPPRESS_COPY2ANALOG__NO_COPY   0x1
-#define BF_RTC_CTRL_SUPPRESS_COPY2ANALOG(v)         (((v) << 6) & 0x40)
-#define BF_RTC_CTRL_SUPPRESS_COPY2ANALOG_V(v)       ((BV_RTC_CTRL_SUPPRESS_COPY2ANALOG__##v << 6) & 0x40)
-#define BP_RTC_CTRL_FORCE_UPDATE                    5
-#define BM_RTC_CTRL_FORCE_UPDATE                    0x20
-#define BV_RTC_CTRL_FORCE_UPDATE__NORMAL            0x0
-#define BV_RTC_CTRL_FORCE_UPDATE__FORCE_COPY        0x1
-#define BF_RTC_CTRL_FORCE_UPDATE(v)                 (((v) << 5) & 0x20)
-#define BF_RTC_CTRL_FORCE_UPDATE_V(v)               ((BV_RTC_CTRL_FORCE_UPDATE__##v << 5) & 0x20)
-#define BP_RTC_CTRL_WATCHDOGEN                      4
-#define BM_RTC_CTRL_WATCHDOGEN                      0x10
-#define BF_RTC_CTRL_WATCHDOGEN(v)                   (((v) << 4) & 0x10)
-#define BP_RTC_CTRL_ONEMSEC_IRQ                     3
-#define BM_RTC_CTRL_ONEMSEC_IRQ                     0x8
-#define BF_RTC_CTRL_ONEMSEC_IRQ(v)                  (((v) << 3) & 0x8)
-#define BP_RTC_CTRL_ALARM_IRQ                       2
-#define BM_RTC_CTRL_ALARM_IRQ                       0x4
-#define BF_RTC_CTRL_ALARM_IRQ(v)                    (((v) << 2) & 0x4)
-#define BP_RTC_CTRL_ONEMSEC_IRQ_EN                  1
-#define BM_RTC_CTRL_ONEMSEC_IRQ_EN                  0x2
-#define BF_RTC_CTRL_ONEMSEC_IRQ_EN(v)               (((v) << 1) & 0x2)
-#define BP_RTC_CTRL_ALARM_IRQ_EN                    0
-#define BM_RTC_CTRL_ALARM_IRQ_EN                    0x1
-#define BF_RTC_CTRL_ALARM_IRQ_EN(v)                 (((v) << 0) & 0x1)
-
-/**
- * Register: HW_RTC_STAT
- * Address: 0x10
- * SCT: no
-*/
-#define HW_RTC_STAT                         (*(volatile unsigned long *)(REGS_RTC_BASE + 0x10))
-#define BP_RTC_STAT_RTC_PRESENT             31
-#define BM_RTC_STAT_RTC_PRESENT             0x80000000
-#define BF_RTC_STAT_RTC_PRESENT(v)          (((v) << 31) & 0x80000000)
-#define BP_RTC_STAT_ALARM_PRESENT           30
-#define BM_RTC_STAT_ALARM_PRESENT           0x40000000
-#define BF_RTC_STAT_ALARM_PRESENT(v)        (((v) << 30) & 0x40000000)
-#define BP_RTC_STAT_WATCHDOG_PRESENT        29
-#define BM_RTC_STAT_WATCHDOG_PRESENT        0x20000000
-#define BF_RTC_STAT_WATCHDOG_PRESENT(v)     (((v) << 29) & 0x20000000)
-#define BP_RTC_STAT_XTAL32768_PRESENT       28
-#define BM_RTC_STAT_XTAL32768_PRESENT       0x10000000
-#define BF_RTC_STAT_XTAL32768_PRESENT(v)    (((v) << 28) & 0x10000000)
-#define BP_RTC_STAT_STALE_REGS              16
-#define BM_RTC_STAT_STALE_REGS              0x3f0000
-#define BF_RTC_STAT_STALE_REGS(v)           (((v) << 16) & 0x3f0000)
-#define BP_RTC_STAT_NEW_REGS                8
-#define BM_RTC_STAT_NEW_REGS                0x3f00
-#define BF_RTC_STAT_NEW_REGS(v)             (((v) << 8) & 0x3f00)
-#define BP_RTC_STAT_FUSE_UNLOCK             1
-#define BM_RTC_STAT_FUSE_UNLOCK             0x2
-#define BF_RTC_STAT_FUSE_UNLOCK(v)          (((v) << 1) & 0x2)
-#define BP_RTC_STAT_FUSE_DONE               0
-#define BM_RTC_STAT_FUSE_DONE               0x1
-#define BF_RTC_STAT_FUSE_DONE(v)            (((v) << 0) & 0x1)
-
-/**
- * Register: HW_RTC_MILLISECONDS
- * Address: 0x20
- * SCT: yes
-*/
-#define HW_RTC_MILLISECONDS             (*(volatile unsigned long *)(REGS_RTC_BASE + 0x20 + 0x0))
-#define HW_RTC_MILLISECONDS_SET         (*(volatile unsigned long *)(REGS_RTC_BASE + 0x20 + 0x4))
-#define HW_RTC_MILLISECONDS_CLR         (*(volatile unsigned long *)(REGS_RTC_BASE + 0x20 + 0x8))
-#define HW_RTC_MILLISECONDS_TOG         (*(volatile unsigned long *)(REGS_RTC_BASE + 0x20 + 0xc))
-#define BP_RTC_MILLISECONDS_COUNT       0
-#define BM_RTC_MILLISECONDS_COUNT       0xffffffff
-#define BF_RTC_MILLISECONDS_COUNT(v)    (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_RTC_SECONDS
- * Address: 0x30
- * SCT: yes
-*/
-#define HW_RTC_SECONDS          (*(volatile unsigned long *)(REGS_RTC_BASE + 0x30 + 0x0))
-#define HW_RTC_SECONDS_SET      (*(volatile unsigned long *)(REGS_RTC_BASE + 0x30 + 0x4))
-#define HW_RTC_SECONDS_CLR      (*(volatile unsigned long *)(REGS_RTC_BASE + 0x30 + 0x8))
-#define HW_RTC_SECONDS_TOG      (*(volatile unsigned long *)(REGS_RTC_BASE + 0x30 + 0xc))
-#define BP_RTC_SECONDS_COUNT    0
-#define BM_RTC_SECONDS_COUNT    0xffffffff
-#define BF_RTC_SECONDS_COUNT(v) (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_RTC_ALARM
- * Address: 0x40
- * SCT: yes
-*/
-#define HW_RTC_ALARM            (*(volatile unsigned long *)(REGS_RTC_BASE + 0x40 + 0x0))
-#define HW_RTC_ALARM_SET        (*(volatile unsigned long *)(REGS_RTC_BASE + 0x40 + 0x4))
-#define HW_RTC_ALARM_CLR        (*(volatile unsigned long *)(REGS_RTC_BASE + 0x40 + 0x8))
-#define HW_RTC_ALARM_TOG        (*(volatile unsigned long *)(REGS_RTC_BASE + 0x40 + 0xc))
-#define BP_RTC_ALARM_VALUE      0
-#define BM_RTC_ALARM_VALUE      0xffffffff
-#define BF_RTC_ALARM_VALUE(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_RTC_WATCHDOG
- * Address: 0x50
- * SCT: yes
-*/
-#define HW_RTC_WATCHDOG             (*(volatile unsigned long *)(REGS_RTC_BASE + 0x50 + 0x0))
-#define HW_RTC_WATCHDOG_SET         (*(volatile unsigned long *)(REGS_RTC_BASE + 0x50 + 0x4))
-#define HW_RTC_WATCHDOG_CLR         (*(volatile unsigned long *)(REGS_RTC_BASE + 0x50 + 0x8))
-#define HW_RTC_WATCHDOG_TOG         (*(volatile unsigned long *)(REGS_RTC_BASE + 0x50 + 0xc))
-#define BP_RTC_WATCHDOG_COUNT       0
-#define BM_RTC_WATCHDOG_COUNT       0xffffffff
-#define BF_RTC_WATCHDOG_COUNT(v)    (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_RTC_PERSISTENT0
- * Address: 0x60
- * SCT: yes
-*/
-#define HW_RTC_PERSISTENT0                                  (*(volatile unsigned long *)(REGS_RTC_BASE + 0x60 + 0x0))
-#define HW_RTC_PERSISTENT0_SET                              (*(volatile unsigned long *)(REGS_RTC_BASE + 0x60 + 0x4))
-#define HW_RTC_PERSISTENT0_CLR                              (*(volatile unsigned long *)(REGS_RTC_BASE + 0x60 + 0x8))
-#define HW_RTC_PERSISTENT0_TOG                              (*(volatile unsigned long *)(REGS_RTC_BASE + 0x60 + 0xc))
-#define BP_RTC_PERSISTENT0_GENERAL                          16
-#define BM_RTC_PERSISTENT0_GENERAL                          0xffff0000
-#define BV_RTC_PERSISTENT0_GENERAL__SDRAM_BOOT              0x8000
-#define BV_RTC_PERSISTENT0_GENERAL__ENUMERATE_500MA_TWICE   0x4000
-#define BV_RTC_PERSISTENT0_GENERAL__USB_BOOT_PLAYER_MODE    0x2000
-#define BV_RTC_PERSISTENT0_GENERAL__SKIP_CHECKDISK          0x1000
-#define BV_RTC_PERSISTENT0_GENERAL__USB_LOW_POWER_MODE      0x800
-#define BV_RTC_PERSISTENT0_GENERAL__OTG_HNP_BIT             0x400
-#define BV_RTC_PERSISTENT0_GENERAL__OTG_ATL_ROLE_BIT        0x200
-#define BV_RTC_PERSISTENT0_GENERAL__SDRAM_CS_HI             0x100
-#define BV_RTC_PERSISTENT0_GENERAL__SDRAM_CS_LO             0x80
-#define BV_RTC_PERSISTENT0_GENERAL__SDRAM_NDX_3             0x40
-#define BV_RTC_PERSISTENT0_GENERAL__SDRAM_NDX_2             0x20
-#define BV_RTC_PERSISTENT0_GENERAL__SDRAM_NDX_1             0x10
-#define BV_RTC_PERSISTENT0_GENERAL__SDRAM_NDX_0             0x8
-#define BV_RTC_PERSISTENT0_GENERAL__ETM_ENABLE              0x4
-#define BF_RTC_PERSISTENT0_GENERAL(v)                       (((v) << 16) & 0xffff0000)
-#define BF_RTC_PERSISTENT0_GENERAL_V(v)                     ((BV_RTC_PERSISTENT0_GENERAL__##v << 16) & 0xffff0000)
-#define BP_RTC_PERSISTENT0_DCDC_CTRL                        6
-#define BM_RTC_PERSISTENT0_DCDC_CTRL                        0xffc0
-#define BV_RTC_PERSISTENT0_DCDC_CTRL__SD_PRESENT            0x200
-#define BV_RTC_PERSISTENT0_DCDC_CTRL__LOWBAT_3P0            0x100
-#define BV_RTC_PERSISTENT0_DCDC_CTRL__SELFBIAS_PWRUP        0x80
-#define BV_RTC_PERSISTENT0_DCDC_CTRL__AUTO_RESTART          0x40
-#define BV_RTC_PERSISTENT0_DCDC_CTRL__DETECT_LOWBAT         0x20
-#define BV_RTC_PERSISTENT0_DCDC_CTRL__DROP_BIAS1            0x10
-#define BV_RTC_PERSISTENT0_DCDC_CTRL__DROP_BIAS2            0x8
-#define BV_RTC_PERSISTENT0_DCDC_CTRL__SPARE                 0x4
-#define BV_RTC_PERSISTENT0_DCDC_CTRL__DISABLE_XTALSTOP      0x2
-#define BV_RTC_PERSISTENT0_DCDC_CTRL__SPARE2                0x1
-#define BF_RTC_PERSISTENT0_DCDC_CTRL(v)                     (((v) << 6) & 0xffc0)
-#define BF_RTC_PERSISTENT0_DCDC_CTRL_V(v)                   ((BV_RTC_PERSISTENT0_DCDC_CTRL__##v << 6) & 0xffc0)
-#define BP_RTC_PERSISTENT0_XTAL32_PDOWN                     5
-#define BM_RTC_PERSISTENT0_XTAL32_PDOWN                     0x20
-#define BF_RTC_PERSISTENT0_XTAL32_PDOWN(v)                  (((v) << 5) & 0x20)
-#define BP_RTC_PERSISTENT0_XTAL24_PDOWN                     4
-#define BM_RTC_PERSISTENT0_XTAL24_PDOWN                     0x10
-#define BF_RTC_PERSISTENT0_XTAL24_PDOWN(v)                  (((v) << 4) & 0x10)
-#define BP_RTC_PERSISTENT0_ALARM_WAKE_EN                    3
-#define BM_RTC_PERSISTENT0_ALARM_WAKE_EN                    0x8
-#define BF_RTC_PERSISTENT0_ALARM_WAKE_EN(v)                 (((v) << 3) & 0x8)
-#define BP_RTC_PERSISTENT0_ALARM_EN                         2
-#define BM_RTC_PERSISTENT0_ALARM_EN                         0x4
-#define BF_RTC_PERSISTENT0_ALARM_EN(v)                      (((v) << 2) & 0x4)
-#define BP_RTC_PERSISTENT0_ALARM_WAKE                       1
-#define BM_RTC_PERSISTENT0_ALARM_WAKE                       0x2
-#define BF_RTC_PERSISTENT0_ALARM_WAKE(v)                    (((v) << 1) & 0x2)
-#define BP_RTC_PERSISTENT0_CLOCKSOURCE                      0
-#define BM_RTC_PERSISTENT0_CLOCKSOURCE                      0x1
-#define BF_RTC_PERSISTENT0_CLOCKSOURCE(v)                   (((v) << 0) & 0x1)
-
-/**
- * Register: HW_RTC_PERSISTENT1
- * Address: 0x70
- * SCT: yes
-*/
-#define HW_RTC_PERSISTENT1              (*(volatile unsigned long *)(REGS_RTC_BASE + 0x70 + 0x0))
-#define HW_RTC_PERSISTENT1_SET          (*(volatile unsigned long *)(REGS_RTC_BASE + 0x70 + 0x4))
-#define HW_RTC_PERSISTENT1_CLR          (*(volatile unsigned long *)(REGS_RTC_BASE + 0x70 + 0x8))
-#define HW_RTC_PERSISTENT1_TOG          (*(volatile unsigned long *)(REGS_RTC_BASE + 0x70 + 0xc))
-#define BP_RTC_PERSISTENT1_GENERAL      0
-#define BM_RTC_PERSISTENT1_GENERAL      0xffffffff
-#define BF_RTC_PERSISTENT1_GENERAL(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_RTC_PERSISTENT2
- * Address: 0x80
- * SCT: yes
-*/
-#define HW_RTC_PERSISTENT2                      (*(volatile unsigned long *)(REGS_RTC_BASE + 0x80 + 0x0))
-#define HW_RTC_PERSISTENT2_SET                  (*(volatile unsigned long *)(REGS_RTC_BASE + 0x80 + 0x4))
-#define HW_RTC_PERSISTENT2_CLR                  (*(volatile unsigned long *)(REGS_RTC_BASE + 0x80 + 0x8))
-#define HW_RTC_PERSISTENT2_TOG                  (*(volatile unsigned long *)(REGS_RTC_BASE + 0x80 + 0xc))
-#define BP_RTC_PERSISTENT2_SRAM_LO              0
-#define BM_RTC_PERSISTENT2_SRAM_LO              0xffffffff
-#define BV_RTC_PERSISTENT2_SRAM_LO__WARM_BOOT   0x80000000
-#define BF_RTC_PERSISTENT2_SRAM_LO(v)           (((v) << 0) & 0xffffffff)
-#define BF_RTC_PERSISTENT2_SRAM_LO_V(v)         ((BV_RTC_PERSISTENT2_SRAM_LO__##v << 0) & 0xffffffff)
-
-/**
- * Register: HW_RTC_PERSISTENT3
- * Address: 0x90
- * SCT: yes
-*/
-#define HW_RTC_PERSISTENT3              (*(volatile unsigned long *)(REGS_RTC_BASE + 0x90 + 0x0))
-#define HW_RTC_PERSISTENT3_SET          (*(volatile unsigned long *)(REGS_RTC_BASE + 0x90 + 0x4))
-#define HW_RTC_PERSISTENT3_CLR          (*(volatile unsigned long *)(REGS_RTC_BASE + 0x90 + 0x8))
-#define HW_RTC_PERSISTENT3_TOG          (*(volatile unsigned long *)(REGS_RTC_BASE + 0x90 + 0xc))
-#define BP_RTC_PERSISTENT3_SRAM_HI      0
-#define BM_RTC_PERSISTENT3_SRAM_HI      0xffffffff
-#define BF_RTC_PERSISTENT3_SRAM_HI(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_RTC_DEBUG
- * Address: 0xa0
- * SCT: yes
-*/
-#define HW_RTC_DEBUG                        (*(volatile unsigned long *)(REGS_RTC_BASE + 0xa0 + 0x0))
-#define HW_RTC_DEBUG_SET                    (*(volatile unsigned long *)(REGS_RTC_BASE + 0xa0 + 0x4))
-#define HW_RTC_DEBUG_CLR                    (*(volatile unsigned long *)(REGS_RTC_BASE + 0xa0 + 0x8))
-#define HW_RTC_DEBUG_TOG                    (*(volatile unsigned long *)(REGS_RTC_BASE + 0xa0 + 0xc))
-#define BP_RTC_DEBUG_WATCHDOG_RESET_MASK    1
-#define BM_RTC_DEBUG_WATCHDOG_RESET_MASK    0x2
-#define BF_RTC_DEBUG_WATCHDOG_RESET_MASK(v) (((v) << 1) & 0x2)
-#define BP_RTC_DEBUG_WATCHDOG_RESET         0
-#define BM_RTC_DEBUG_WATCHDOG_RESET         0x1
-#define BF_RTC_DEBUG_WATCHDOG_RESET(v)      (((v) << 0) & 0x1)
-
-/**
- * Register: HW_RTC_UNLOCK
- * Address: 0x200
- * SCT: yes
-*/
-#define HW_RTC_UNLOCK           (*(volatile unsigned long *)(REGS_RTC_BASE + 0x200 + 0x0))
-#define HW_RTC_UNLOCK_SET       (*(volatile unsigned long *)(REGS_RTC_BASE + 0x200 + 0x4))
-#define HW_RTC_UNLOCK_CLR       (*(volatile unsigned long *)(REGS_RTC_BASE + 0x200 + 0x8))
-#define HW_RTC_UNLOCK_TOG       (*(volatile unsigned long *)(REGS_RTC_BASE + 0x200 + 0xc))
-#define BP_RTC_UNLOCK_KEY       0
-#define BM_RTC_UNLOCK_KEY       0xffffffff
-#define BV_RTC_UNLOCK_KEY__VAL  0xc6a83957
-#define BF_RTC_UNLOCK_KEY(v)    (((v) << 0) & 0xffffffff)
-#define BF_RTC_UNLOCK_KEY_V(v)  ((BV_RTC_UNLOCK_KEY__##v << 0) & 0xffffffff)
-
-/**
- * Register: HW_RTC_LASERFUSEn
- * Address: 0x300+n*0x10
- * SCT: yes
-*/
-#define HW_RTC_LASERFUSEn(n)        (*(volatile unsigned long *)(REGS_RTC_BASE + 0x300+(n)*0x10 + 0x0))
-#define HW_RTC_LASERFUSEn_SET(n)    (*(volatile unsigned long *)(REGS_RTC_BASE + 0x300+(n)*0x10 + 0x4))
-#define HW_RTC_LASERFUSEn_CLR(n)    (*(volatile unsigned long *)(REGS_RTC_BASE + 0x300+(n)*0x10 + 0x8))
-#define HW_RTC_LASERFUSEn_TOG(n)    (*(volatile unsigned long *)(REGS_RTC_BASE + 0x300+(n)*0x10 + 0xc))
-#define BP_RTC_LASERFUSEn_BITS      0
-#define BM_RTC_LASERFUSEn_BITS      0xffffffff
-#define BF_RTC_LASERFUSEn_BITS(v)   (((v) << 0) & 0xffffffff)
-
-#endif /* __HEADERGEN__STMP3600__RTC__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-spdif.h b/firmware/target/arm/imx233/regs/stmp3600/regs-spdif.h
deleted file mode 100644
index 54e1e697b8..0000000000
--- a/firmware/target/arm/imx233/regs/stmp3600/regs-spdif.h
+++ /dev/null
@@ -1,165 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3600:2.3.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__STMP3600__SPDIF__H__
-#define __HEADERGEN__STMP3600__SPDIF__H__
-
-#define REGS_SPDIF_BASE (0x80054000)
-
-#define REGS_SPDIF_VERSION "2.3.0"
-
-/**
- * Register: HW_SPDIF_CTRL
- * Address: 0
- * SCT: yes
-*/
-#define HW_SPDIF_CTRL                       (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x0 + 0x0))
-#define HW_SPDIF_CTRL_SET                   (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x0 + 0x4))
-#define HW_SPDIF_CTRL_CLR                   (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x0 + 0x8))
-#define HW_SPDIF_CTRL_TOG                   (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x0 + 0xc))
-#define BP_SPDIF_CTRL_SFTRST                31
-#define BM_SPDIF_CTRL_SFTRST                0x80000000
-#define BF_SPDIF_CTRL_SFTRST(v)             (((v) << 31) & 0x80000000)
-#define BP_SPDIF_CTRL_CLKGATE               30
-#define BM_SPDIF_CTRL_CLKGATE               0x40000000
-#define BF_SPDIF_CTRL_CLKGATE(v)            (((v) << 30) & 0x40000000)
-#define BP_SPDIF_CTRL_DMAWAIT_COUNT         16
-#define BM_SPDIF_CTRL_DMAWAIT_COUNT         0x1f0000
-#define BF_SPDIF_CTRL_DMAWAIT_COUNT(v)      (((v) << 16) & 0x1f0000)
-#define BP_SPDIF_CTRL_WAIT_END_XFER         5
-#define BM_SPDIF_CTRL_WAIT_END_XFER         0x20
-#define BF_SPDIF_CTRL_WAIT_END_XFER(v)      (((v) << 5) & 0x20)
-#define BP_SPDIF_CTRL_WORD_LENGTH           4
-#define BM_SPDIF_CTRL_WORD_LENGTH           0x10
-#define BF_SPDIF_CTRL_WORD_LENGTH(v)        (((v) << 4) & 0x10)
-#define BP_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ    3
-#define BM_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ    0x8
-#define BF_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ(v) (((v) << 3) & 0x8)
-#define BP_SPDIF_CTRL_FIFO_OVERFLOW_IRQ     2
-#define BM_SPDIF_CTRL_FIFO_OVERFLOW_IRQ     0x4
-#define BF_SPDIF_CTRL_FIFO_OVERFLOW_IRQ(v)  (((v) << 2) & 0x4)
-#define BP_SPDIF_CTRL_FIFO_ERROR_IRQ_EN     1
-#define BM_SPDIF_CTRL_FIFO_ERROR_IRQ_EN     0x2
-#define BF_SPDIF_CTRL_FIFO_ERROR_IRQ_EN(v)  (((v) << 1) & 0x2)
-#define BP_SPDIF_CTRL_RUN                   0
-#define BM_SPDIF_CTRL_RUN                   0x1
-#define BF_SPDIF_CTRL_RUN(v)                (((v) << 0) & 0x1)
-
-/**
- * Register: HW_SPDIF_STAT
- * Address: 0x10
- * SCT: no
-*/
-#define HW_SPDIF_STAT               (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x10))
-#define BP_SPDIF_STAT_PRESENT       31
-#define BM_SPDIF_STAT_PRESENT       0x80000000
-#define BF_SPDIF_STAT_PRESENT(v)    (((v) << 31) & 0x80000000)
-#define BP_SPDIF_STAT_END_XFER      0
-#define BM_SPDIF_STAT_END_XFER      0x1
-#define BF_SPDIF_STAT_END_XFER(v)   (((v) << 0) & 0x1)
-
-/**
- * Register: HW_SPDIF_FRAMECTRL
- * Address: 0x20
- * SCT: yes
-*/
-#define HW_SPDIF_FRAMECTRL              (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x20 + 0x0))
-#define HW_SPDIF_FRAMECTRL_SET          (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x20 + 0x4))
-#define HW_SPDIF_FRAMECTRL_CLR          (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x20 + 0x8))
-#define HW_SPDIF_FRAMECTRL_TOG          (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x20 + 0xc))
-#define BP_SPDIF_FRAMECTRL_V_CONFIG     17
-#define BM_SPDIF_FRAMECTRL_V_CONFIG     0x20000
-#define BF_SPDIF_FRAMECTRL_V_CONFIG(v)  (((v) << 17) & 0x20000)
-#define BP_SPDIF_FRAMECTRL_AUTO_MUTE    16
-#define BM_SPDIF_FRAMECTRL_AUTO_MUTE    0x10000
-#define BF_SPDIF_FRAMECTRL_AUTO_MUTE(v) (((v) << 16) & 0x10000)
-#define BP_SPDIF_FRAMECTRL_USER_DATA    14
-#define BM_SPDIF_FRAMECTRL_USER_DATA    0x4000
-#define BF_SPDIF_FRAMECTRL_USER_DATA(v) (((v) << 14) & 0x4000)
-#define BP_SPDIF_FRAMECTRL_V            13
-#define BM_SPDIF_FRAMECTRL_V            0x2000
-#define BF_SPDIF_FRAMECTRL_V(v)         (((v) << 13) & 0x2000)
-#define BP_SPDIF_FRAMECTRL_L            12
-#define BM_SPDIF_FRAMECTRL_L            0x1000
-#define BF_SPDIF_FRAMECTRL_L(v)         (((v) << 12) & 0x1000)
-#define BP_SPDIF_FRAMECTRL_CC           4
-#define BM_SPDIF_FRAMECTRL_CC           0x7f0
-#define BF_SPDIF_FRAMECTRL_CC(v)        (((v) << 4) & 0x7f0)
-#define BP_SPDIF_FRAMECTRL_PRE          3
-#define BM_SPDIF_FRAMECTRL_PRE          0x8
-#define BF_SPDIF_FRAMECTRL_PRE(v)       (((v) << 3) & 0x8)
-#define BP_SPDIF_FRAMECTRL_COPY         2
-#define BM_SPDIF_FRAMECTRL_COPY         0x4
-#define BF_SPDIF_FRAMECTRL_COPY(v)      (((v) << 2) & 0x4)
-#define BP_SPDIF_FRAMECTRL_AUDIO        1
-#define BM_SPDIF_FRAMECTRL_AUDIO        0x2
-#define BF_SPDIF_FRAMECTRL_AUDIO(v)     (((v) << 1) & 0x2)
-#define BP_SPDIF_FRAMECTRL_PRO          0
-#define BM_SPDIF_FRAMECTRL_PRO          0x1
-#define BF_SPDIF_FRAMECTRL_PRO(v)       (((v) << 0) & 0x1)
-
-/**
- * Register: HW_SPDIF_SRR
- * Address: 0x30
- * SCT: yes
-*/
-#define HW_SPDIF_SRR                (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x30 + 0x0))
-#define HW_SPDIF_SRR_SET            (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x30 + 0x4))
-#define HW_SPDIF_SRR_CLR            (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x30 + 0x8))
-#define HW_SPDIF_SRR_TOG            (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x30 + 0xc))
-#define BP_SPDIF_SRR_BASEMULT       28
-#define BM_SPDIF_SRR_BASEMULT       0x70000000
-#define BF_SPDIF_SRR_BASEMULT(v)    (((v) << 28) & 0x70000000)
-#define BP_SPDIF_SRR_RATE           0
-#define BM_SPDIF_SRR_RATE           0xfffff
-#define BF_SPDIF_SRR_RATE(v)        (((v) << 0) & 0xfffff)
-
-/**
- * Register: HW_SPDIF_DEBUG
- * Address: 0x40
- * SCT: no
-*/
-#define HW_SPDIF_DEBUG                  (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x40))
-#define BP_SPDIF_DEBUG_DMA_PREQ         1
-#define BM_SPDIF_DEBUG_DMA_PREQ         0x2
-#define BF_SPDIF_DEBUG_DMA_PREQ(v)      (((v) << 1) & 0x2)
-#define BP_SPDIF_DEBUG_FIFO_STATUS      0
-#define BM_SPDIF_DEBUG_FIFO_STATUS      0x1
-#define BF_SPDIF_DEBUG_FIFO_STATUS(v)   (((v) << 0) & 0x1)
-
-/**
- * Register: HW_SPDIF_DATA
- * Address: 0x50
- * SCT: yes
-*/
-#define HW_SPDIF_DATA           (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x50 + 0x0))
-#define HW_SPDIF_DATA_SET       (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x50 + 0x4))
-#define HW_SPDIF_DATA_CLR       (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x50 + 0x8))
-#define HW_SPDIF_DATA_TOG       (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x50 + 0xc))
-#define BP_SPDIF_DATA_HIGH      16
-#define BM_SPDIF_DATA_HIGH      0xffff0000
-#define BF_SPDIF_DATA_HIGH(v)   (((v) << 16) & 0xffff0000)
-#define BP_SPDIF_DATA_LOW       0
-#define BM_SPDIF_DATA_LOW       0xffff
-#define BF_SPDIF_DATA_LOW(v)    (((v) << 0) & 0xffff)
-
-#endif /* __HEADERGEN__STMP3600__SPDIF__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-ssp.h b/firmware/target/arm/imx233/regs/stmp3600/regs-ssp.h
deleted file mode 100644
index b3954101c4..0000000000
--- a/firmware/target/arm/imx233/regs/stmp3600/regs-ssp.h
+++ /dev/null
@@ -1,541 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3600:2.3.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__STMP3600__SSP__H__
-#define __HEADERGEN__STMP3600__SSP__H__
-
-#define REGS_SSP_BASE (0x80010000)
-
-#define REGS_SSP_VERSION "2.3.0"
-
-/**
- * Register: HW_SSP_CTRL0
- * Address: 0
- * SCT: yes
-*/
-#define HW_SSP_CTRL0                        (*(volatile unsigned long *)(REGS_SSP_BASE + 0x0 + 0x0))
-#define HW_SSP_CTRL0_SET                    (*(volatile unsigned long *)(REGS_SSP_BASE + 0x0 + 0x4))
-#define HW_SSP_CTRL0_CLR                    (*(volatile unsigned long *)(REGS_SSP_BASE + 0x0 + 0x8))
-#define HW_SSP_CTRL0_TOG                    (*(volatile unsigned long *)(REGS_SSP_BASE + 0x0 + 0xc))
-#define BP_SSP_CTRL0_SFTRST                 31
-#define BM_SSP_CTRL0_SFTRST                 0x80000000
-#define BF_SSP_CTRL0_SFTRST(v)              (((v) << 31) & 0x80000000)
-#define BP_SSP_CTRL0_CLKGATE                30
-#define BM_SSP_CTRL0_CLKGATE                0x40000000
-#define BF_SSP_CTRL0_CLKGATE(v)             (((v) << 30) & 0x40000000)
-#define BP_SSP_CTRL0_RUN                    29
-#define BM_SSP_CTRL0_RUN                    0x20000000
-#define BF_SSP_CTRL0_RUN(v)                 (((v) << 29) & 0x20000000)
-#define BP_SSP_CTRL0_HALF_DUPLEX            28
-#define BM_SSP_CTRL0_HALF_DUPLEX            0x10000000
-#define BF_SSP_CTRL0_HALF_DUPLEX(v)         (((v) << 28) & 0x10000000)
-#define BP_SSP_CTRL0_LOCK_CS                27
-#define BM_SSP_CTRL0_LOCK_CS                0x8000000
-#define BF_SSP_CTRL0_LOCK_CS(v)             (((v) << 27) & 0x8000000)
-#define BP_SSP_CTRL0_IGNORE_CRC             26
-#define BM_SSP_CTRL0_IGNORE_CRC             0x4000000
-#define BF_SSP_CTRL0_IGNORE_CRC(v)          (((v) << 26) & 0x4000000)
-#define BP_SSP_CTRL0_READ                   25
-#define BM_SSP_CTRL0_READ                   0x2000000
-#define BF_SSP_CTRL0_READ(v)                (((v) << 25) & 0x2000000)
-#define BP_SSP_CTRL0_DATA_XFER              24
-#define BM_SSP_CTRL0_DATA_XFER              0x1000000
-#define BF_SSP_CTRL0_DATA_XFER(v)           (((v) << 24) & 0x1000000)
-#define BP_SSP_CTRL0_SDIO_IRQ               23
-#define BM_SSP_CTRL0_SDIO_IRQ               0x800000
-#define BF_SSP_CTRL0_SDIO_IRQ(v)            (((v) << 23) & 0x800000)
-#define BP_SSP_CTRL0_BUS_WIDTH              22
-#define BM_SSP_CTRL0_BUS_WIDTH              0x400000
-#define BV_SSP_CTRL0_BUS_WIDTH__ONE_BIT     0x0
-#define BV_SSP_CTRL0_BUS_WIDTH__FOUR_BIT    0x1
-#define BF_SSP_CTRL0_BUS_WIDTH(v)           (((v) << 22) & 0x400000)
-#define BF_SSP_CTRL0_BUS_WIDTH_V(v)         ((BV_SSP_CTRL0_BUS_WIDTH__##v << 22) & 0x400000)
-#define BP_SSP_CTRL0_WAIT_FOR_IRQ           21
-#define BM_SSP_CTRL0_WAIT_FOR_IRQ           0x200000
-#define BF_SSP_CTRL0_WAIT_FOR_IRQ(v)        (((v) << 21) & 0x200000)
-#define BP_SSP_CTRL0_WAIT_FOR_CMD           20
-#define BM_SSP_CTRL0_WAIT_FOR_CMD           0x100000
-#define BF_SSP_CTRL0_WAIT_FOR_CMD(v)        (((v) << 20) & 0x100000)
-#define BP_SSP_CTRL0_LONG_RESP              19
-#define BM_SSP_CTRL0_LONG_RESP              0x80000
-#define BF_SSP_CTRL0_LONG_RESP(v)           (((v) << 19) & 0x80000)
-#define BP_SSP_CTRL0_CHECK_RESP             18
-#define BM_SSP_CTRL0_CHECK_RESP             0x40000
-#define BF_SSP_CTRL0_CHECK_RESP(v)          (((v) << 18) & 0x40000)
-#define BP_SSP_CTRL0_GET_RESP               17
-#define BM_SSP_CTRL0_GET_RESP               0x20000
-#define BF_SSP_CTRL0_GET_RESP(v)            (((v) << 17) & 0x20000)
-#define BP_SSP_CTRL0_ENABLE                 16
-#define BM_SSP_CTRL0_ENABLE                 0x10000
-#define BF_SSP_CTRL0_ENABLE(v)              (((v) << 16) & 0x10000)
-#define BP_SSP_CTRL0_XFER_COUNT             0
-#define BM_SSP_CTRL0_XFER_COUNT             0xffff
-#define BF_SSP_CTRL0_XFER_COUNT(v)          (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_SSP_CMD0
- * Address: 0x10
- * SCT: yes
-*/
-#define HW_SSP_CMD0                                 (*(volatile unsigned long *)(REGS_SSP_BASE + 0x10 + 0x0))
-#define HW_SSP_CMD0_SET                             (*(volatile unsigned long *)(REGS_SSP_BASE + 0x10 + 0x4))
-#define HW_SSP_CMD0_CLR                             (*(volatile unsigned long *)(REGS_SSP_BASE + 0x10 + 0x8))
-#define HW_SSP_CMD0_TOG                             (*(volatile unsigned long *)(REGS_SSP_BASE + 0x10 + 0xc))
-#define BP_SSP_CMD0_CMD                             0
-#define BM_SSP_CMD0_CMD                             0xff
-#define BV_SSP_CMD0_CMD__MMC_GO_IDLE_STATE          0x0
-#define BV_SSP_CMD0_CMD__MMC_SEND_OP_COND           0x1
-#define BV_SSP_CMD0_CMD__MMC_ALL_SEND_CID           0x2
-#define BV_SSP_CMD0_CMD__MMC_SET_RELATIVE_ADDR      0x3
-#define BV_SSP_CMD0_CMD__MMC_SET_DSR                0x4
-#define BV_SSP_CMD0_CMD__MMC_RESERVED_5             0x5
-#define BV_SSP_CMD0_CMD__MMC_SWITCH                 0x6
-#define BV_SSP_CMD0_CMD__MMC_SELECT_DESELECT_CARD   0x7
-#define BV_SSP_CMD0_CMD__MMC_SEND_EXT_CSD           0x8
-#define BV_SSP_CMD0_CMD__MMC_SEND_CSD               0x9
-#define BV_SSP_CMD0_CMD__MMC_SEND_CID               0xa
-#define BV_SSP_CMD0_CMD__MMC_READ_DAT_UNTIL_STOP    0xb
-#define BV_SSP_CMD0_CMD__MMC_STOP_TRANSMISSION      0xc
-#define BV_SSP_CMD0_CMD__MMC_SEND_STATUS            0xd
-#define BV_SSP_CMD0_CMD__MMC_BUSTEST_R              0xe
-#define BV_SSP_CMD0_CMD__MMC_GO_INACTIVE_STATE      0xf
-#define BV_SSP_CMD0_CMD__MMC_SET_BLOCKLEN           0x10
-#define BV_SSP_CMD0_CMD__MMC_READ_SINGLE_BLOCK      0x11
-#define BV_SSP_CMD0_CMD__MMC_READ_MULTIPLE_BLOCK    0x12
-#define BV_SSP_CMD0_CMD__MMC_BUSTEST_W              0x13
-#define BV_SSP_CMD0_CMD__MMC_WRITE_DAT_UNTIL_STOP   0x14
-#define BV_SSP_CMD0_CMD__MMC_SET_BLOCK_COUNT        0x17
-#define BV_SSP_CMD0_CMD__MMC_WRITE_BLOCK            0x18
-#define BV_SSP_CMD0_CMD__MMC_WRITE_MULTIPLE_BLOCK   0x19
-#define BV_SSP_CMD0_CMD__MMC_PROGRAM_CID            0x1a
-#define BV_SSP_CMD0_CMD__MMC_PROGRAM_CSD            0x1b
-#define BV_SSP_CMD0_CMD__MMC_SET_WRITE_PROT         0x1c
-#define BV_SSP_CMD0_CMD__MMC_CLR_WRITE_PROT         0x1d
-#define BV_SSP_CMD0_CMD__MMC_SEND_WRITE_PROT        0x1e
-#define BV_SSP_CMD0_CMD__MMC_ERASE_GROUP_START      0x23
-#define BV_SSP_CMD0_CMD__MMC_ERASE_GROUP_END        0x24
-#define BV_SSP_CMD0_CMD__MMC_ERASE                  0x26
-#define BV_SSP_CMD0_CMD__MMC_FAST_IO                0x27
-#define BV_SSP_CMD0_CMD__MMC_GO_IRQ_STATE           0x28
-#define BV_SSP_CMD0_CMD__MMC_LOCK_UNLOCK            0x2a
-#define BV_SSP_CMD0_CMD__MMC_APP_CMD                0x37
-#define BV_SSP_CMD0_CMD__MMC_GEN_CMD                0x38
-#define BV_SSP_CMD0_CMD__SD_GO_IDLE_STATE           0x0
-#define BV_SSP_CMD0_CMD__SD_ALL_SEND_CID            0x2
-#define BV_SSP_CMD0_CMD__SD_SEND_RELATIVE_ADDR      0x3
-#define BV_SSP_CMD0_CMD__SD_SET_DSR                 0x4
-#define BV_SSP_CMD0_CMD__SD_IO_SEND_OP_COND         0x5
-#define BV_SSP_CMD0_CMD__SD_SELECT_DESELECT_CARD    0x7
-#define BV_SSP_CMD0_CMD__SD_SEND_CSD                0x9
-#define BV_SSP_CMD0_CMD__SD_SEND_CID                0xa
-#define BV_SSP_CMD0_CMD__SD_STOP_TRANSMISSION       0xc
-#define BV_SSP_CMD0_CMD__SD_SEND_STATUS             0xd
-#define BV_SSP_CMD0_CMD__SD_GO_INACTIVE_STATE       0xf
-#define BV_SSP_CMD0_CMD__SD_SET_BLOCKLEN            0x10
-#define BV_SSP_CMD0_CMD__SD_READ_SINGLE_BLOCK       0x11
-#define BV_SSP_CMD0_CMD__SD_READ_MULTIPLE_BLOCK     0x12
-#define BV_SSP_CMD0_CMD__SD_WRITE_BLOCK             0x18
-#define BV_SSP_CMD0_CMD__SD_WRITE_MULTIPLE_BLOCK    0x19
-#define BV_SSP_CMD0_CMD__SD_PROGRAM_CSD             0x1b
-#define BV_SSP_CMD0_CMD__SD_SET_WRITE_PROT          0x1c
-#define BV_SSP_CMD0_CMD__SD_CLR_WRITE_PROT          0x1d
-#define BV_SSP_CMD0_CMD__SD_SEND_WRITE_PROT         0x1e
-#define BV_SSP_CMD0_CMD__SD_ERASE_WR_BLK_START      0x20
-#define BV_SSP_CMD0_CMD__SD_ERASE_WR_BLK_END        0x21
-#define BV_SSP_CMD0_CMD__SD_ERASE_GROUP_START       0x23
-#define BV_SSP_CMD0_CMD__SD_ERASE_GROUP_END         0x24
-#define BV_SSP_CMD0_CMD__SD_ERASE                   0x26
-#define BV_SSP_CMD0_CMD__SD_LOCK_UNLOCK             0x2a
-#define BV_SSP_CMD0_CMD__SD_IO_RW_DIRECT            0x34
-#define BV_SSP_CMD0_CMD__SD_IO_RW_EXTENDED          0x35
-#define BV_SSP_CMD0_CMD__SD_APP_CMD                 0x37
-#define BV_SSP_CMD0_CMD__SD_GEN_CMD                 0x38
-#define BF_SSP_CMD0_CMD(v)                          (((v) << 0) & 0xff)
-#define BF_SSP_CMD0_CMD_V(v)                        ((BV_SSP_CMD0_CMD__##v << 0) & 0xff)
-
-/**
- * Register: HW_SSP_CMD1
- * Address: 0x20
- * SCT: no
-*/
-#define HW_SSP_CMD1             (*(volatile unsigned long *)(REGS_SSP_BASE + 0x20))
-#define BP_SSP_CMD1_CMD_ARG     0
-#define BM_SSP_CMD1_CMD_ARG     0xffffffff
-#define BF_SSP_CMD1_CMD_ARG(v)  (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_SSP_COMPREF
- * Address: 0x30
- * SCT: no
-*/
-#define HW_SSP_COMPREF              (*(volatile unsigned long *)(REGS_SSP_BASE + 0x30))
-#define BP_SSP_COMPREF_REFERENCE    0
-#define BM_SSP_COMPREF_REFERENCE    0xffffffff
-#define BF_SSP_COMPREF_REFERENCE(v) (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_SSP_COMPMASK
- * Address: 0x40
- * SCT: no
-*/
-#define HW_SSP_COMPMASK         (*(volatile unsigned long *)(REGS_SSP_BASE + 0x40))
-#define BP_SSP_COMPMASK_MASK    0
-#define BM_SSP_COMPMASK_MASK    0xffffffff
-#define BF_SSP_COMPMASK_MASK(v) (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_SSP_TIMING
- * Address: 0x50
- * SCT: no
-*/
-#define HW_SSP_TIMING                   (*(volatile unsigned long *)(REGS_SSP_BASE + 0x50))
-#define BP_SSP_TIMING_TIMEOUT           16
-#define BM_SSP_TIMING_TIMEOUT           0xffff0000
-#define BF_SSP_TIMING_TIMEOUT(v)        (((v) << 16) & 0xffff0000)
-#define BP_SSP_TIMING_CLOCK_DIVIDE      8
-#define BM_SSP_TIMING_CLOCK_DIVIDE      0xff00
-#define BF_SSP_TIMING_CLOCK_DIVIDE(v)   (((v) << 8) & 0xff00)
-#define BP_SSP_TIMING_CLOCK_RATE        0
-#define BM_SSP_TIMING_CLOCK_RATE        0xff
-#define BF_SSP_TIMING_CLOCK_RATE(v)     (((v) << 0) & 0xff)
-
-/**
- * Register: HW_SSP_CTRL1
- * Address: 0x60
- * SCT: yes
-*/
-#define HW_SSP_CTRL1                            (*(volatile unsigned long *)(REGS_SSP_BASE + 0x60 + 0x0))
-#define HW_SSP_CTRL1_SET                        (*(volatile unsigned long *)(REGS_SSP_BASE + 0x60 + 0x4))
-#define HW_SSP_CTRL1_CLR                        (*(volatile unsigned long *)(REGS_SSP_BASE + 0x60 + 0x8))
-#define HW_SSP_CTRL1_TOG                        (*(volatile unsigned long *)(REGS_SSP_BASE + 0x60 + 0xc))
-#define BP_SSP_CTRL1_SDIO_IRQ                   31
-#define BM_SSP_CTRL1_SDIO_IRQ                   0x80000000
-#define BF_SSP_CTRL1_SDIO_IRQ(v)                (((v) << 31) & 0x80000000)
-#define BP_SSP_CTRL1_SDIO_IRQ_EN                30
-#define BM_SSP_CTRL1_SDIO_IRQ_EN                0x40000000
-#define BF_SSP_CTRL1_SDIO_IRQ_EN(v)             (((v) << 30) & 0x40000000)
-#define BP_SSP_CTRL1_RESP_ERR_IRQ               29
-#define BM_SSP_CTRL1_RESP_ERR_IRQ               0x20000000
-#define BF_SSP_CTRL1_RESP_ERR_IRQ(v)            (((v) << 29) & 0x20000000)
-#define BP_SSP_CTRL1_RESP_ERR_IRQ_EN            28
-#define BM_SSP_CTRL1_RESP_ERR_IRQ_EN            0x10000000
-#define BF_SSP_CTRL1_RESP_ERR_IRQ_EN(v)         (((v) << 28) & 0x10000000)
-#define BP_SSP_CTRL1_RESP_TIMEOUT_IRQ           27
-#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ           0x8000000
-#define BF_SSP_CTRL1_RESP_TIMEOUT_IRQ(v)        (((v) << 27) & 0x8000000)
-#define BP_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN        26
-#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN        0x4000000
-#define BF_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN(v)     (((v) << 26) & 0x4000000)
-#define BP_SSP_CTRL1_DATA_TIMEOUT_IRQ           25
-#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ           0x2000000
-#define BF_SSP_CTRL1_DATA_TIMEOUT_IRQ(v)        (((v) << 25) & 0x2000000)
-#define BP_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN        24
-#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN        0x1000000
-#define BF_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN(v)     (((v) << 24) & 0x1000000)
-#define BP_SSP_CTRL1_DATA_CRC_IRQ               23
-#define BM_SSP_CTRL1_DATA_CRC_IRQ               0x800000
-#define BF_SSP_CTRL1_DATA_CRC_IRQ(v)            (((v) << 23) & 0x800000)
-#define BP_SSP_CTRL1_DATA_CRC_IRQ_EN            22
-#define BM_SSP_CTRL1_DATA_CRC_IRQ_EN            0x400000
-#define BF_SSP_CTRL1_DATA_CRC_IRQ_EN(v)         (((v) << 22) & 0x400000)
-#define BP_SSP_CTRL1_XMIT_IRQ                   21
-#define BM_SSP_CTRL1_XMIT_IRQ                   0x200000
-#define BF_SSP_CTRL1_XMIT_IRQ(v)                (((v) << 21) & 0x200000)
-#define BP_SSP_CTRL1_XMIT_IRQ_EN                20
-#define BM_SSP_CTRL1_XMIT_IRQ_EN                0x100000
-#define BF_SSP_CTRL1_XMIT_IRQ_EN(v)             (((v) << 20) & 0x100000)
-#define BP_SSP_CTRL1_RECV_IRQ                   19
-#define BM_SSP_CTRL1_RECV_IRQ                   0x80000
-#define BF_SSP_CTRL1_RECV_IRQ(v)                (((v) << 19) & 0x80000)
-#define BP_SSP_CTRL1_RECV_IRQ_EN                18
-#define BM_SSP_CTRL1_RECV_IRQ_EN                0x40000
-#define BF_SSP_CTRL1_RECV_IRQ_EN(v)             (((v) << 18) & 0x40000)
-#define BP_SSP_CTRL1_RECV_TIMEOUT_IRQ           17
-#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ           0x20000
-#define BF_SSP_CTRL1_RECV_TIMEOUT_IRQ(v)        (((v) << 17) & 0x20000)
-#define BP_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN        16
-#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN        0x10000
-#define BF_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN(v)     (((v) << 16) & 0x10000)
-#define BP_SSP_CTRL1_RECV_OVRFLW_IRQ            15
-#define BM_SSP_CTRL1_RECV_OVRFLW_IRQ            0x8000
-#define BF_SSP_CTRL1_RECV_OVRFLW_IRQ(v)         (((v) << 15) & 0x8000)
-#define BP_SSP_CTRL1_RECV_OVRFLW_IRQ_EN         14
-#define BM_SSP_CTRL1_RECV_OVRFLW_IRQ_EN         0x4000
-#define BF_SSP_CTRL1_RECV_OVRFLW_IRQ_EN(v)      (((v) << 14) & 0x4000)
-#define BP_SSP_CTRL1_DMA_ENABLE                 13
-#define BM_SSP_CTRL1_DMA_ENABLE                 0x2000
-#define BF_SSP_CTRL1_DMA_ENABLE(v)              (((v) << 13) & 0x2000)
-#define BP_SSP_CTRL1_LOOPBACK                   12
-#define BM_SSP_CTRL1_LOOPBACK                   0x1000
-#define BF_SSP_CTRL1_LOOPBACK(v)                (((v) << 12) & 0x1000)
-#define BP_SSP_CTRL1_SLAVE_OUT_DISABLE          11
-#define BM_SSP_CTRL1_SLAVE_OUT_DISABLE          0x800
-#define BF_SSP_CTRL1_SLAVE_OUT_DISABLE(v)       (((v) << 11) & 0x800)
-#define BP_SSP_CTRL1_PHASE                      10
-#define BM_SSP_CTRL1_PHASE                      0x400
-#define BF_SSP_CTRL1_PHASE(v)                   (((v) << 10) & 0x400)
-#define BP_SSP_CTRL1_POLARITY                   9
-#define BM_SSP_CTRL1_POLARITY                   0x200
-#define BF_SSP_CTRL1_POLARITY(v)                (((v) << 9) & 0x200)
-#define BP_SSP_CTRL1_SLAVE_MODE                 8
-#define BM_SSP_CTRL1_SLAVE_MODE                 0x100
-#define BF_SSP_CTRL1_SLAVE_MODE(v)              (((v) << 8) & 0x100)
-#define BP_SSP_CTRL1_WORD_LENGTH                4
-#define BM_SSP_CTRL1_WORD_LENGTH                0xf0
-#define BV_SSP_CTRL1_WORD_LENGTH__RESERVED0     0x0
-#define BV_SSP_CTRL1_WORD_LENGTH__RESERVED1     0x1
-#define BV_SSP_CTRL1_WORD_LENGTH__RESERVED2     0x2
-#define BV_SSP_CTRL1_WORD_LENGTH__FOUR_BITS     0x3
-#define BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS    0x7
-#define BV_SSP_CTRL1_WORD_LENGTH__SIXTEEN_BITS  0xf
-#define BF_SSP_CTRL1_WORD_LENGTH(v)             (((v) << 4) & 0xf0)
-#define BF_SSP_CTRL1_WORD_LENGTH_V(v)           ((BV_SSP_CTRL1_WORD_LENGTH__##v << 4) & 0xf0)
-#define BP_SSP_CTRL1_SSP_MODE                   0
-#define BM_SSP_CTRL1_SSP_MODE                   0xf
-#define BV_SSP_CTRL1_SSP_MODE__SPI              0x0
-#define BV_SSP_CTRL1_SSP_MODE__SSI              0x1
-#define BV_SSP_CTRL1_SSP_MODE__MICROWIRE        0x2
-#define BV_SSP_CTRL1_SSP_MODE__SD_MMC           0x3
-#define BV_SSP_CTRL1_SSP_MODE__MS               0x4
-#define BF_SSP_CTRL1_SSP_MODE(v)                (((v) << 0) & 0xf)
-#define BF_SSP_CTRL1_SSP_MODE_V(v)              ((BV_SSP_CTRL1_SSP_MODE__##v << 0) & 0xf)
-
-/**
- * Register: HW_SSP_DATA
- * Address: 0x70
- * SCT: no
-*/
-#define HW_SSP_DATA         (*(volatile unsigned long *)(REGS_SSP_BASE + 0x70))
-#define BP_SSP_DATA_DATA    0
-#define BM_SSP_DATA_DATA    0xffffffff
-#define BF_SSP_DATA_DATA(v) (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_SSP_SDRESP0
- * Address: 0x80
- * SCT: no
-*/
-#define HW_SSP_SDRESP0          (*(volatile unsigned long *)(REGS_SSP_BASE + 0x80))
-#define BP_SSP_SDRESP0_RESP0    0
-#define BM_SSP_SDRESP0_RESP0    0xffffffff
-#define BF_SSP_SDRESP0_RESP0(v) (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_SSP_SDRESP1
- * Address: 0x90
- * SCT: no
-*/
-#define HW_SSP_SDRESP1          (*(volatile unsigned long *)(REGS_SSP_BASE + 0x90))
-#define BP_SSP_SDRESP1_RESP1    0
-#define BM_SSP_SDRESP1_RESP1    0xffffffff
-#define BF_SSP_SDRESP1_RESP1(v) (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_SSP_SDRESP2
- * Address: 0xa0
- * SCT: no
-*/
-#define HW_SSP_SDRESP2          (*(volatile unsigned long *)(REGS_SSP_BASE + 0xa0))
-#define BP_SSP_SDRESP2_RESP2    0
-#define BM_SSP_SDRESP2_RESP2    0xffffffff
-#define BF_SSP_SDRESP2_RESP2(v) (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_SSP_SDRESP3
- * Address: 0xb0
- * SCT: no
-*/
-#define HW_SSP_SDRESP3          (*(volatile unsigned long *)(REGS_SSP_BASE + 0xb0))
-#define BP_SSP_SDRESP3_RESP3    0
-#define BM_SSP_SDRESP3_RESP3    0xffffffff
-#define BF_SSP_SDRESP3_RESP3(v) (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_SSP_STATUS
- * Address: 0xc0
- * SCT: no
-*/
-#define HW_SSP_STATUS                       (*(volatile unsigned long *)(REGS_SSP_BASE + 0xc0))
-#define BP_SSP_STATUS_PRESENT               31
-#define BM_SSP_STATUS_PRESENT               0x80000000
-#define BF_SSP_STATUS_PRESENT(v)            (((v) << 31) & 0x80000000)
-#define BP_SSP_STATUS_MS_PRESENT            30
-#define BM_SSP_STATUS_MS_PRESENT            0x40000000
-#define BF_SSP_STATUS_MS_PRESENT(v)         (((v) << 30) & 0x40000000)
-#define BP_SSP_STATUS_SD_PRESENT            29
-#define BM_SSP_STATUS_SD_PRESENT            0x20000000
-#define BF_SSP_STATUS_SD_PRESENT(v)         (((v) << 29) & 0x20000000)
-#define BP_SSP_STATUS_CARD_DETECT           28
-#define BM_SSP_STATUS_CARD_DETECT           0x10000000
-#define BF_SSP_STATUS_CARD_DETECT(v)        (((v) << 28) & 0x10000000)
-#define BP_SSP_STATUS_RECV_COUNT            24
-#define BM_SSP_STATUS_RECV_COUNT            0xf000000
-#define BF_SSP_STATUS_RECV_COUNT(v)         (((v) << 24) & 0xf000000)
-#define BP_SSP_STATUS_XMIT_COUNT            20
-#define BM_SSP_STATUS_XMIT_COUNT            0xf00000
-#define BF_SSP_STATUS_XMIT_COUNT(v)         (((v) << 20) & 0xf00000)
-#define BP_SSP_STATUS_DMAREQ                19
-#define BM_SSP_STATUS_DMAREQ                0x80000
-#define BF_SSP_STATUS_DMAREQ(v)             (((v) << 19) & 0x80000)
-#define BP_SSP_STATUS_DMAEND                18
-#define BM_SSP_STATUS_DMAEND                0x40000
-#define BF_SSP_STATUS_DMAEND(v)             (((v) << 18) & 0x40000)
-#define BP_SSP_STATUS_SDIO_IRQ              17
-#define BM_SSP_STATUS_SDIO_IRQ              0x20000
-#define BF_SSP_STATUS_SDIO_IRQ(v)           (((v) << 17) & 0x20000)
-#define BP_SSP_STATUS_RESP_CRC_ERR          16
-#define BM_SSP_STATUS_RESP_CRC_ERR          0x10000
-#define BF_SSP_STATUS_RESP_CRC_ERR(v)       (((v) << 16) & 0x10000)
-#define BP_SSP_STATUS_RESP_ERR              15
-#define BM_SSP_STATUS_RESP_ERR              0x8000
-#define BF_SSP_STATUS_RESP_ERR(v)           (((v) << 15) & 0x8000)
-#define BP_SSP_STATUS_RESP_TIMEOUT          14
-#define BM_SSP_STATUS_RESP_TIMEOUT          0x4000
-#define BF_SSP_STATUS_RESP_TIMEOUT(v)       (((v) << 14) & 0x4000)
-#define BP_SSP_STATUS_DATA_CRC_ERR          13
-#define BM_SSP_STATUS_DATA_CRC_ERR          0x2000
-#define BF_SSP_STATUS_DATA_CRC_ERR(v)       (((v) << 13) & 0x2000)
-#define BP_SSP_STATUS_TIMEOUT               12
-#define BM_SSP_STATUS_TIMEOUT               0x1000
-#define BF_SSP_STATUS_TIMEOUT(v)            (((v) << 12) & 0x1000)
-#define BP_SSP_STATUS_RECV_TIMEOUT_STAT     11
-#define BM_SSP_STATUS_RECV_TIMEOUT_STAT     0x800
-#define BF_SSP_STATUS_RECV_TIMEOUT_STAT(v)  (((v) << 11) & 0x800)
-#define BP_SSP_STATUS_RECV_DATA_STAT        10
-#define BM_SSP_STATUS_RECV_DATA_STAT        0x400
-#define BF_SSP_STATUS_RECV_DATA_STAT(v)     (((v) << 10) & 0x400)
-#define BP_SSP_STATUS_RECV_OVRFLW           9
-#define BM_SSP_STATUS_RECV_OVRFLW           0x200
-#define BF_SSP_STATUS_RECV_OVRFLW(v)        (((v) << 9) & 0x200)
-#define BP_SSP_STATUS_RECV_FULL             8
-#define BM_SSP_STATUS_RECV_FULL             0x100
-#define BF_SSP_STATUS_RECV_FULL(v)          (((v) << 8) & 0x100)
-#define BP_SSP_STATUS_RECV_NOT_EMPTY        7
-#define BM_SSP_STATUS_RECV_NOT_EMPTY        0x80
-#define BF_SSP_STATUS_RECV_NOT_EMPTY(v)     (((v) << 7) & 0x80)
-#define BP_SSP_STATUS_XMIT_NOT_FULL         6
-#define BM_SSP_STATUS_XMIT_NOT_FULL         0x40
-#define BF_SSP_STATUS_XMIT_NOT_FULL(v)      (((v) << 6) & 0x40)
-#define BP_SSP_STATUS_XMIT_EMPTY            5
-#define BM_SSP_STATUS_XMIT_EMPTY            0x20
-#define BF_SSP_STATUS_XMIT_EMPTY(v)         (((v) << 5) & 0x20)
-#define BP_SSP_STATUS_XMIT_UNDRFLW          4
-#define BM_SSP_STATUS_XMIT_UNDRFLW          0x10
-#define BF_SSP_STATUS_XMIT_UNDRFLW(v)       (((v) << 4) & 0x10)
-#define BP_SSP_STATUS_CMD_BUSY              3
-#define BM_SSP_STATUS_CMD_BUSY              0x8
-#define BF_SSP_STATUS_CMD_BUSY(v)           (((v) << 3) & 0x8)
-#define BP_SSP_STATUS_DATA_BUSY             2
-#define BM_SSP_STATUS_DATA_BUSY             0x4
-#define BF_SSP_STATUS_DATA_BUSY(v)          (((v) << 2) & 0x4)
-#define BP_SSP_STATUS_DATA_XFER             1
-#define BM_SSP_STATUS_DATA_XFER             0x2
-#define BF_SSP_STATUS_DATA_XFER(v)          (((v) << 1) & 0x2)
-#define BP_SSP_STATUS_BUSY                  0
-#define BM_SSP_STATUS_BUSY                  0x1
-#define BF_SSP_STATUS_BUSY(v)               (((v) << 0) & 0x1)
-
-/**
- * Register: HW_SSP_DEBUG
- * Address: 0x100
- * SCT: no
-*/
-#define HW_SSP_DEBUG                        (*(volatile unsigned long *)(REGS_SSP_BASE + 0x100))
-#define BP_SSP_DEBUG_DATACRC_ERR            28
-#define BM_SSP_DEBUG_DATACRC_ERR            0xf0000000
-#define BF_SSP_DEBUG_DATACRC_ERR(v)         (((v) << 28) & 0xf0000000)
-#define BP_SSP_DEBUG_DATA_STALL             27
-#define BM_SSP_DEBUG_DATA_STALL             0x8000000
-#define BF_SSP_DEBUG_DATA_STALL(v)          (((v) << 27) & 0x8000000)
-#define BP_SSP_DEBUG_DAT_SM                 24
-#define BM_SSP_DEBUG_DAT_SM                 0x7000000
-#define BV_SSP_DEBUG_DAT_SM__DSM_IDLE       0x0
-#define BV_SSP_DEBUG_DAT_SM__DSM_START      0x1
-#define BV_SSP_DEBUG_DAT_SM__DSM_WORD       0x2
-#define BV_SSP_DEBUG_DAT_SM__DSM_CRC1       0x3
-#define BV_SSP_DEBUG_DAT_SM__DSM_CRC2       0x4
-#define BV_SSP_DEBUG_DAT_SM__DSM_END        0x5
-#define BV_SSP_DEBUG_DAT_SM__DSM_RXDLY      0x6
-#define BF_SSP_DEBUG_DAT_SM(v)              (((v) << 24) & 0x7000000)
-#define BF_SSP_DEBUG_DAT_SM_V(v)            ((BV_SSP_DEBUG_DAT_SM__##v << 24) & 0x7000000)
-#define BP_SSP_DEBUG_MSTK_SM                20
-#define BM_SSP_DEBUG_MSTK_SM                0xf00000
-#define BV_SSP_DEBUG_MSTK_SM__MSTK_IDLE     0x0
-#define BV_SSP_DEBUG_MSTK_SM__MSTK_CKON     0x1
-#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS1      0x2
-#define BV_SSP_DEBUG_MSTK_SM__MSTK_TPC      0x3
-#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS2      0x4
-#define BV_SSP_DEBUG_MSTK_SM__MSTK_HDSHK    0x5
-#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS3      0x6
-#define BV_SSP_DEBUG_MSTK_SM__MSTK_RW       0x7
-#define BV_SSP_DEBUG_MSTK_SM__MSTK_CRC1     0x8
-#define BV_SSP_DEBUG_MSTK_SM__MSTK_CRC2     0x9
-#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS0      0xa
-#define BV_SSP_DEBUG_MSTK_SM__MSTK_DONE     0xb
-#define BF_SSP_DEBUG_MSTK_SM(v)             (((v) << 20) & 0xf00000)
-#define BF_SSP_DEBUG_MSTK_SM_V(v)           ((BV_SSP_DEBUG_MSTK_SM__##v << 20) & 0xf00000)
-#define BP_SSP_DEBUG_CMD_OE                 19
-#define BM_SSP_DEBUG_CMD_OE                 0x80000
-#define BF_SSP_DEBUG_CMD_OE(v)              (((v) << 19) & 0x80000)
-#define BP_SSP_DEBUG_CMD_SM                 16
-#define BM_SSP_DEBUG_CMD_SM                 0x70000
-#define BV_SSP_DEBUG_CMD_SM__CSM_IDLE       0x0
-#define BV_SSP_DEBUG_CMD_SM__CSM_INDEX      0x1
-#define BV_SSP_DEBUG_CMD_SM__CSM_ARG        0x2
-#define BV_SSP_DEBUG_CMD_SM__CSM_CRC        0x3
-#define BF_SSP_DEBUG_CMD_SM(v)              (((v) << 16) & 0x70000)
-#define BF_SSP_DEBUG_CMD_SM_V(v)            ((BV_SSP_DEBUG_CMD_SM__##v << 16) & 0x70000)
-#define BP_SSP_DEBUG_CLK_OE                 15
-#define BM_SSP_DEBUG_CLK_OE                 0x8000
-#define BF_SSP_DEBUG_CLK_OE(v)              (((v) << 15) & 0x8000)
-#define BP_SSP_DEBUG_MMC_SM                 12
-#define BM_SSP_DEBUG_MMC_SM                 0x7000
-#define BV_SSP_DEBUG_MMC_SM__MMC_IDLE       0x0
-#define BV_SSP_DEBUG_MMC_SM__MMC_CMD        0x1
-#define BV_SSP_DEBUG_MMC_SM__MMC_TRC        0x2
-#define BV_SSP_DEBUG_MMC_SM__MMC_RESP       0x3
-#define BV_SSP_DEBUG_MMC_SM__MMC_RPRX       0x4
-#define BV_SSP_DEBUG_MMC_SM__MMC_TX         0x5
-#define BV_SSP_DEBUG_MMC_SM__MMC_CTOK       0x6
-#define BV_SSP_DEBUG_MMC_SM__MMC_RX         0x7
-#define BF_SSP_DEBUG_MMC_SM(v)              (((v) << 12) & 0x7000)
-#define BF_SSP_DEBUG_MMC_SM_V(v)            ((BV_SSP_DEBUG_MMC_SM__##v << 12) & 0x7000)
-#define BP_SSP_DEBUG_DAT0_OE                11
-#define BM_SSP_DEBUG_DAT0_OE                0x800
-#define BF_SSP_DEBUG_DAT0_OE(v)             (((v) << 11) & 0x800)
-#define BP_SSP_DEBUG_DAT321_OE              10
-#define BM_SSP_DEBUG_DAT321_OE              0x400
-#define BF_SSP_DEBUG_DAT321_OE(v)           (((v) << 10) & 0x400)
-#define BP_SSP_DEBUG_SSP_CMD                9
-#define BM_SSP_DEBUG_SSP_CMD                0x200
-#define BF_SSP_DEBUG_SSP_CMD(v)             (((v) << 9) & 0x200)
-#define BP_SSP_DEBUG_SSP_RESP               8
-#define BM_SSP_DEBUG_SSP_RESP               0x100
-#define BF_SSP_DEBUG_SSP_RESP(v)            (((v) << 8) & 0x100)
-#define BP_SSP_DEBUG_SSP_TXD                4
-#define BM_SSP_DEBUG_SSP_TXD                0xf0
-#define BF_SSP_DEBUG_SSP_TXD(v)             (((v) << 4) & 0xf0)
-#define BP_SSP_DEBUG_SSP_RXD                0
-#define BM_SSP_DEBUG_SSP_RXD                0xf
-#define BF_SSP_DEBUG_SSP_RXD(v)             (((v) << 0) & 0xf)
-
-#endif /* __HEADERGEN__STMP3600__SSP__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-timrot.h b/firmware/target/arm/imx233/regs/stmp3600/regs-timrot.h
deleted file mode 100644
index b537e45c0d..0000000000
--- a/firmware/target/arm/imx233/regs/stmp3600/regs-timrot.h
+++ /dev/null
@@ -1,267 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3600:2.3.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__STMP3600__TIMROT__H__
-#define __HEADERGEN__STMP3600__TIMROT__H__
-
-#define REGS_TIMROT_BASE (0x80068000)
-
-#define REGS_TIMROT_VERSION "2.3.0"
-
-/**
- * Register: HW_TIMROT_ROTCTRL
- * Address: 0
- * SCT: yes
-*/
-#define HW_TIMROT_ROTCTRL                       (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x0 + 0x0))
-#define HW_TIMROT_ROTCTRL_SET                   (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x0 + 0x4))
-#define HW_TIMROT_ROTCTRL_CLR                   (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x0 + 0x8))
-#define HW_TIMROT_ROTCTRL_TOG                   (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x0 + 0xc))
-#define BP_TIMROT_ROTCTRL_SFTRST                31
-#define BM_TIMROT_ROTCTRL_SFTRST                0x80000000
-#define BF_TIMROT_ROTCTRL_SFTRST(v)             (((v) << 31) & 0x80000000)
-#define BP_TIMROT_ROTCTRL_CLKGATE               30
-#define BM_TIMROT_ROTCTRL_CLKGATE               0x40000000
-#define BF_TIMROT_ROTCTRL_CLKGATE(v)            (((v) << 30) & 0x40000000)
-#define BP_TIMROT_ROTCTRL_ROTARY_PRESENT        29
-#define BM_TIMROT_ROTCTRL_ROTARY_PRESENT        0x20000000
-#define BF_TIMROT_ROTCTRL_ROTARY_PRESENT(v)     (((v) << 29) & 0x20000000)
-#define BP_TIMROT_ROTCTRL_TIM3_PRESENT          28
-#define BM_TIMROT_ROTCTRL_TIM3_PRESENT          0x10000000
-#define BF_TIMROT_ROTCTRL_TIM3_PRESENT(v)       (((v) << 28) & 0x10000000)
-#define BP_TIMROT_ROTCTRL_TIM2_PRESENT          27
-#define BM_TIMROT_ROTCTRL_TIM2_PRESENT          0x8000000
-#define BF_TIMROT_ROTCTRL_TIM2_PRESENT(v)       (((v) << 27) & 0x8000000)
-#define BP_TIMROT_ROTCTRL_TIM1_PRESENT          26
-#define BM_TIMROT_ROTCTRL_TIM1_PRESENT          0x4000000
-#define BF_TIMROT_ROTCTRL_TIM1_PRESENT(v)       (((v) << 26) & 0x4000000)
-#define BP_TIMROT_ROTCTRL_TIM0_PRESENT          25
-#define BM_TIMROT_ROTCTRL_TIM0_PRESENT          0x2000000
-#define BF_TIMROT_ROTCTRL_TIM0_PRESENT(v)       (((v) << 25) & 0x2000000)
-#define BP_TIMROT_ROTCTRL_STATE                 22
-#define BM_TIMROT_ROTCTRL_STATE                 0x1c00000
-#define BF_TIMROT_ROTCTRL_STATE(v)              (((v) << 22) & 0x1c00000)
-#define BP_TIMROT_ROTCTRL_DIVIDER               16
-#define BM_TIMROT_ROTCTRL_DIVIDER               0x3f0000
-#define BF_TIMROT_ROTCTRL_DIVIDER(v)            (((v) << 16) & 0x3f0000)
-#define BP_TIMROT_ROTCTRL_RELATIVE              12
-#define BM_TIMROT_ROTCTRL_RELATIVE              0x1000
-#define BF_TIMROT_ROTCTRL_RELATIVE(v)           (((v) << 12) & 0x1000)
-#define BP_TIMROT_ROTCTRL_OVERSAMPLE            10
-#define BM_TIMROT_ROTCTRL_OVERSAMPLE            0xc00
-#define BV_TIMROT_ROTCTRL_OVERSAMPLE__8X        0x0
-#define BV_TIMROT_ROTCTRL_OVERSAMPLE__4X        0x1
-#define BV_TIMROT_ROTCTRL_OVERSAMPLE__2X        0x2
-#define BV_TIMROT_ROTCTRL_OVERSAMPLE__1X        0x3
-#define BF_TIMROT_ROTCTRL_OVERSAMPLE(v)         (((v) << 10) & 0xc00)
-#define BF_TIMROT_ROTCTRL_OVERSAMPLE_V(v)       ((BV_TIMROT_ROTCTRL_OVERSAMPLE__##v << 10) & 0xc00)
-#define BP_TIMROT_ROTCTRL_POLARITY_B            9
-#define BM_TIMROT_ROTCTRL_POLARITY_B            0x200
-#define BF_TIMROT_ROTCTRL_POLARITY_B(v)         (((v) << 9) & 0x200)
-#define BP_TIMROT_ROTCTRL_POLARITY_A            8
-#define BM_TIMROT_ROTCTRL_POLARITY_A            0x100
-#define BF_TIMROT_ROTCTRL_POLARITY_A(v)         (((v) << 8) & 0x100)
-#define BP_TIMROT_ROTCTRL_SELECT_B              4
-#define BM_TIMROT_ROTCTRL_SELECT_B              0x70
-#define BV_TIMROT_ROTCTRL_SELECT_B__NEVER_TICK  0x0
-#define BV_TIMROT_ROTCTRL_SELECT_B__PWM0        0x1
-#define BV_TIMROT_ROTCTRL_SELECT_B__PWM1        0x2
-#define BV_TIMROT_ROTCTRL_SELECT_B__PWM2        0x3
-#define BV_TIMROT_ROTCTRL_SELECT_B__PWM3        0x4
-#define BV_TIMROT_ROTCTRL_SELECT_B__PWM4        0x5
-#define BV_TIMROT_ROTCTRL_SELECT_B__ROTARYA     0x6
-#define BV_TIMROT_ROTCTRL_SELECT_B__ROTARYB     0x7
-#define BF_TIMROT_ROTCTRL_SELECT_B(v)           (((v) << 4) & 0x70)
-#define BF_TIMROT_ROTCTRL_SELECT_B_V(v)         ((BV_TIMROT_ROTCTRL_SELECT_B__##v << 4) & 0x70)
-#define BP_TIMROT_ROTCTRL_SELECT_A              0
-#define BM_TIMROT_ROTCTRL_SELECT_A              0x7
-#define BV_TIMROT_ROTCTRL_SELECT_A__NEVER_TICK  0x0
-#define BV_TIMROT_ROTCTRL_SELECT_A__PWM0        0x1
-#define BV_TIMROT_ROTCTRL_SELECT_A__PWM1        0x2
-#define BV_TIMROT_ROTCTRL_SELECT_A__PWM2        0x3
-#define BV_TIMROT_ROTCTRL_SELECT_A__PWM3        0x4
-#define BV_TIMROT_ROTCTRL_SELECT_A__PWM4        0x5
-#define BV_TIMROT_ROTCTRL_SELECT_A__ROTARYA     0x6
-#define BV_TIMROT_ROTCTRL_SELECT_A__ROTARYB     0x7
-#define BF_TIMROT_ROTCTRL_SELECT_A(v)           (((v) << 0) & 0x7)
-#define BF_TIMROT_ROTCTRL_SELECT_A_V(v)         ((BV_TIMROT_ROTCTRL_SELECT_A__##v << 0) & 0x7)
-
-/**
- * Register: HW_TIMROT_ROTCOUNT
- * Address: 0x10
- * SCT: no
-*/
-#define HW_TIMROT_ROTCOUNT              (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x10))
-#define BP_TIMROT_ROTCOUNT_UPDOWN       0
-#define BM_TIMROT_ROTCOUNT_UPDOWN       0xffff
-#define BF_TIMROT_ROTCOUNT_UPDOWN(v)    (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_TIMROT_TIMCTRL3
- * Address: 0x80
- * SCT: yes
-*/
-#define HW_TIMROT_TIMCTRL3                          (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x80 + 0x0))
-#define HW_TIMROT_TIMCTRL3_SET                      (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x80 + 0x4))
-#define HW_TIMROT_TIMCTRL3_CLR                      (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x80 + 0x8))
-#define HW_TIMROT_TIMCTRL3_TOG                      (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x80 + 0xc))
-#define BP_TIMROT_TIMCTRL3_TEST_SIGNAL              16
-#define BM_TIMROT_TIMCTRL3_TEST_SIGNAL              0xf0000
-#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__NEVER_TICK  0x0
-#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM0        0x1
-#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM1        0x2
-#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM2        0x3
-#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM3        0x4
-#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM4        0x5
-#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__ROTARYA     0x6
-#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__ROTARYB     0x7
-#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__32KHZ_XTAL  0x8
-#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__8KHZ_XTAL   0x9
-#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__4KHZ_XTAL   0xa
-#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__1KHZ_XTAL   0xb
-#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__TICK_ALWAYS 0xc
-#define BF_TIMROT_TIMCTRL3_TEST_SIGNAL(v)           (((v) << 16) & 0xf0000)
-#define BF_TIMROT_TIMCTRL3_TEST_SIGNAL_V(v)         ((BV_TIMROT_TIMCTRL3_TEST_SIGNAL__##v << 16) & 0xf0000)
-#define BP_TIMROT_TIMCTRL3_IRQ                      15
-#define BM_TIMROT_TIMCTRL3_IRQ                      0x8000
-#define BF_TIMROT_TIMCTRL3_IRQ(v)                   (((v) << 15) & 0x8000)
-#define BP_TIMROT_TIMCTRL3_IRQ_EN                   14
-#define BM_TIMROT_TIMCTRL3_IRQ_EN                   0x4000
-#define BF_TIMROT_TIMCTRL3_IRQ_EN(v)                (((v) << 14) & 0x4000)
-#define BP_TIMROT_TIMCTRL3_DUTY_VALID               10
-#define BM_TIMROT_TIMCTRL3_DUTY_VALID               0x400
-#define BF_TIMROT_TIMCTRL3_DUTY_VALID(v)            (((v) << 10) & 0x400)
-#define BP_TIMROT_TIMCTRL3_DUTY_CYCLE               9
-#define BM_TIMROT_TIMCTRL3_DUTY_CYCLE               0x200
-#define BF_TIMROT_TIMCTRL3_DUTY_CYCLE(v)            (((v) << 9) & 0x200)
-#define BP_TIMROT_TIMCTRL3_POLARITY                 8
-#define BM_TIMROT_TIMCTRL3_POLARITY                 0x100
-#define BF_TIMROT_TIMCTRL3_POLARITY(v)              (((v) << 8) & 0x100)
-#define BP_TIMROT_TIMCTRL3_UPDATE                   7
-#define BM_TIMROT_TIMCTRL3_UPDATE                   0x80
-#define BF_TIMROT_TIMCTRL3_UPDATE(v)                (((v) << 7) & 0x80)
-#define BP_TIMROT_TIMCTRL3_RELOAD                   6
-#define BM_TIMROT_TIMCTRL3_RELOAD                   0x40
-#define BF_TIMROT_TIMCTRL3_RELOAD(v)                (((v) << 6) & 0x40)
-#define BP_TIMROT_TIMCTRL3_PRESCALE                 4
-#define BM_TIMROT_TIMCTRL3_PRESCALE                 0x30
-#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_1       0x0
-#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_2       0x1
-#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_4       0x2
-#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_8       0x3
-#define BF_TIMROT_TIMCTRL3_PRESCALE(v)              (((v) << 4) & 0x30)
-#define BF_TIMROT_TIMCTRL3_PRESCALE_V(v)            ((BV_TIMROT_TIMCTRL3_PRESCALE__##v << 4) & 0x30)
-#define BP_TIMROT_TIMCTRL3_SELECT                   0
-#define BM_TIMROT_TIMCTRL3_SELECT                   0xf
-#define BV_TIMROT_TIMCTRL3_SELECT__NEVER_TICK       0x0
-#define BV_TIMROT_TIMCTRL3_SELECT__PWM0             0x1
-#define BV_TIMROT_TIMCTRL3_SELECT__PWM1             0x2
-#define BV_TIMROT_TIMCTRL3_SELECT__PWM2             0x3
-#define BV_TIMROT_TIMCTRL3_SELECT__PWM3             0x4
-#define BV_TIMROT_TIMCTRL3_SELECT__PWM4             0x5
-#define BV_TIMROT_TIMCTRL3_SELECT__ROTARYA          0x6
-#define BV_TIMROT_TIMCTRL3_SELECT__ROTARYB          0x7
-#define BV_TIMROT_TIMCTRL3_SELECT__32KHZ_XTAL       0x8
-#define BV_TIMROT_TIMCTRL3_SELECT__8KHZ_XTAL        0x9
-#define BV_TIMROT_TIMCTRL3_SELECT__4KHZ_XTAL        0xa
-#define BV_TIMROT_TIMCTRL3_SELECT__1KHZ_XTAL        0xb
-#define BV_TIMROT_TIMCTRL3_SELECT__TICK_ALWAYS      0xc
-#define BF_TIMROT_TIMCTRL3_SELECT(v)                (((v) << 0) & 0xf)
-#define BF_TIMROT_TIMCTRL3_SELECT_V(v)              ((BV_TIMROT_TIMCTRL3_SELECT__##v << 0) & 0xf)
-
-/**
- * Register: HW_TIMROT_TIMCOUNT3
- * Address: 0x90
- * SCT: no
-*/
-#define HW_TIMROT_TIMCOUNT3                         (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x90))
-#define BP_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT       16
-#define BM_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT       0xffff0000
-#define BF_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT(v)    (((v) << 16) & 0xffff0000)
-#define BP_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT        0
-#define BM_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT        0xffff
-#define BF_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT(v)     (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_TIMROT_TIMCOUNTn
- * Address: 0x30+n*0x20
- * SCT: no
-*/
-#define HW_TIMROT_TIMCOUNTn(n)                  (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x30+(n)*0x20))
-#define BP_TIMROT_TIMCOUNTn_RUNNING_COUNT       16
-#define BM_TIMROT_TIMCOUNTn_RUNNING_COUNT       0xffff0000
-#define BF_TIMROT_TIMCOUNTn_RUNNING_COUNT(v)    (((v) << 16) & 0xffff0000)
-#define BP_TIMROT_TIMCOUNTn_FIXED_COUNT         0
-#define BM_TIMROT_TIMCOUNTn_FIXED_COUNT         0xffff
-#define BF_TIMROT_TIMCOUNTn_FIXED_COUNT(v)      (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_TIMROT_TIMCTRLn
- * Address: 0x20+n*0x20
- * SCT: yes
-*/
-#define HW_TIMROT_TIMCTRLn(n)                   (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x20+(n)*0x20 + 0x0))
-#define HW_TIMROT_TIMCTRLn_SET(n)               (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x20+(n)*0x20 + 0x4))
-#define HW_TIMROT_TIMCTRLn_CLR(n)               (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x20+(n)*0x20 + 0x8))
-#define HW_TIMROT_TIMCTRLn_TOG(n)               (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x20+(n)*0x20 + 0xc))
-#define BP_TIMROT_TIMCTRLn_IRQ                  15
-#define BM_TIMROT_TIMCTRLn_IRQ                  0x8000
-#define BF_TIMROT_TIMCTRLn_IRQ(v)               (((v) << 15) & 0x8000)
-#define BP_TIMROT_TIMCTRLn_IRQ_EN               14
-#define BM_TIMROT_TIMCTRLn_IRQ_EN               0x4000
-#define BF_TIMROT_TIMCTRLn_IRQ_EN(v)            (((v) << 14) & 0x4000)
-#define BP_TIMROT_TIMCTRLn_POLARITY             8
-#define BM_TIMROT_TIMCTRLn_POLARITY             0x100
-#define BF_TIMROT_TIMCTRLn_POLARITY(v)          (((v) << 8) & 0x100)
-#define BP_TIMROT_TIMCTRLn_UPDATE               7
-#define BM_TIMROT_TIMCTRLn_UPDATE               0x80
-#define BF_TIMROT_TIMCTRLn_UPDATE(v)            (((v) << 7) & 0x80)
-#define BP_TIMROT_TIMCTRLn_RELOAD               6
-#define BM_TIMROT_TIMCTRLn_RELOAD               0x40
-#define BF_TIMROT_TIMCTRLn_RELOAD(v)            (((v) << 6) & 0x40)
-#define BP_TIMROT_TIMCTRLn_PRESCALE             4
-#define BM_TIMROT_TIMCTRLn_PRESCALE             0x30
-#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_1   0x0
-#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_2   0x1
-#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_4   0x2
-#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_8   0x3
-#define BF_TIMROT_TIMCTRLn_PRESCALE(v)          (((v) << 4) & 0x30)
-#define BF_TIMROT_TIMCTRLn_PRESCALE_V(v)        ((BV_TIMROT_TIMCTRLn_PRESCALE__##v << 4) & 0x30)
-#define BP_TIMROT_TIMCTRLn_SELECT               0
-#define BM_TIMROT_TIMCTRLn_SELECT               0xf
-#define BV_TIMROT_TIMCTRLn_SELECT__NEVER_TICK   0x0
-#define BV_TIMROT_TIMCTRLn_SELECT__PWM0         0x1
-#define BV_TIMROT_TIMCTRLn_SELECT__PWM1         0x2
-#define BV_TIMROT_TIMCTRLn_SELECT__PWM2         0x3
-#define BV_TIMROT_TIMCTRLn_SELECT__PWM3         0x4
-#define BV_TIMROT_TIMCTRLn_SELECT__PWM4         0x5
-#define BV_TIMROT_TIMCTRLn_SELECT__ROTARYA      0x6
-#define BV_TIMROT_TIMCTRLn_SELECT__ROTARYB      0x7
-#define BV_TIMROT_TIMCTRLn_SELECT__32KHZ_XTAL   0x8
-#define BV_TIMROT_TIMCTRLn_SELECT__8KHZ_XTAL    0x9
-#define BV_TIMROT_TIMCTRLn_SELECT__4KHZ_XTAL    0xa
-#define BV_TIMROT_TIMCTRLn_SELECT__1KHZ_XTAL    0xb
-#define BV_TIMROT_TIMCTRLn_SELECT__TICK_ALWAYS  0xc
-#define BF_TIMROT_TIMCTRLn_SELECT(v)            (((v) << 0) & 0xf)
-#define BF_TIMROT_TIMCTRLn_SELECT_V(v)          ((BV_TIMROT_TIMCTRLn_SELECT__##v << 0) & 0xf)
-
-#endif /* __HEADERGEN__STMP3600__TIMROT__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-uartapp.h b/firmware/target/arm/imx233/regs/stmp3600/regs-uartapp.h
deleted file mode 100644
index c99d07c580..0000000000
--- a/firmware/target/arm/imx233/regs/stmp3600/regs-uartapp.h
+++ /dev/null
@@ -1,371 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3600:2.3.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__STMP3600__UARTAPP__H__
-#define __HEADERGEN__STMP3600__UARTAPP__H__
-
-#define REGS_UARTAPP_BASE (0x8006c000)
-
-#define REGS_UARTAPP_VERSION "2.3.0"
-
-/**
- * Register: HW_UARTAPP_CTRL0
- * Address: 0
- * SCT: yes
-*/
-#define HW_UARTAPP_CTRL0                (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x0 + 0x0))
-#define HW_UARTAPP_CTRL0_SET            (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x0 + 0x4))
-#define HW_UARTAPP_CTRL0_CLR            (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x0 + 0x8))
-#define HW_UARTAPP_CTRL0_TOG            (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x0 + 0xc))
-#define BP_UARTAPP_CTRL0_SFTRST         31
-#define BM_UARTAPP_CTRL0_SFTRST         0x80000000
-#define BF_UARTAPP_CTRL0_SFTRST(v)      (((v) << 31) & 0x80000000)
-#define BP_UARTAPP_CTRL0_CLKGATE        30
-#define BM_UARTAPP_CTRL0_CLKGATE        0x40000000
-#define BF_UARTAPP_CTRL0_CLKGATE(v)     (((v) << 30) & 0x40000000)
-#define BP_UARTAPP_CTRL0_RUN            28
-#define BM_UARTAPP_CTRL0_RUN            0x10000000
-#define BF_UARTAPP_CTRL0_RUN(v)         (((v) << 28) & 0x10000000)
-#define BP_UARTAPP_CTRL0_RX_SOURCE      25
-#define BM_UARTAPP_CTRL0_RX_SOURCE      0x2000000
-#define BF_UARTAPP_CTRL0_RX_SOURCE(v)   (((v) << 25) & 0x2000000)
-#define BP_UARTAPP_CTRL0_RXTO_ENABLE    24
-#define BM_UARTAPP_CTRL0_RXTO_ENABLE    0x1000000
-#define BF_UARTAPP_CTRL0_RXTO_ENABLE(v) (((v) << 24) & 0x1000000)
-#define BP_UARTAPP_CTRL0_RXTIMEOUT      16
-#define BM_UARTAPP_CTRL0_RXTIMEOUT      0xff0000
-#define BF_UARTAPP_CTRL0_RXTIMEOUT(v)   (((v) << 16) & 0xff0000)
-#define BP_UARTAPP_CTRL0_XFER_COUNT     0
-#define BM_UARTAPP_CTRL0_XFER_COUNT     0xffff
-#define BF_UARTAPP_CTRL0_XFER_COUNT(v)  (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_UARTAPP_CTRL1
- * Address: 0x10
- * SCT: yes
-*/
-#define HW_UARTAPP_CTRL1                (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x10 + 0x0))
-#define HW_UARTAPP_CTRL1_SET            (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x10 + 0x4))
-#define HW_UARTAPP_CTRL1_CLR            (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x10 + 0x8))
-#define HW_UARTAPP_CTRL1_TOG            (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x10 + 0xc))
-#define BP_UARTAPP_CTRL1_RUN            28
-#define BM_UARTAPP_CTRL1_RUN            0x10000000
-#define BF_UARTAPP_CTRL1_RUN(v)         (((v) << 28) & 0x10000000)
-#define BP_UARTAPP_CTRL1_XFER_COUNT     0
-#define BM_UARTAPP_CTRL1_XFER_COUNT     0xffff
-#define BF_UARTAPP_CTRL1_XFER_COUNT(v)  (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_UARTAPP_CTRL2
- * Address: 0x20
- * SCT: yes
-*/
-#define HW_UARTAPP_CTRL2                            (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x20 + 0x0))
-#define HW_UARTAPP_CTRL2_SET                        (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x20 + 0x4))
-#define HW_UARTAPP_CTRL2_CLR                        (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x20 + 0x8))
-#define HW_UARTAPP_CTRL2_TOG                        (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x20 + 0xc))
-#define BP_UARTAPP_CTRL2_INVERT_RTS                 31
-#define BM_UARTAPP_CTRL2_INVERT_RTS                 0x80000000
-#define BF_UARTAPP_CTRL2_INVERT_RTS(v)              (((v) << 31) & 0x80000000)
-#define BP_UARTAPP_CTRL2_INVERT_CTS                 30
-#define BM_UARTAPP_CTRL2_INVERT_CTS                 0x40000000
-#define BF_UARTAPP_CTRL2_INVERT_CTS(v)              (((v) << 30) & 0x40000000)
-#define BP_UARTAPP_CTRL2_INVERT_TX                  29
-#define BM_UARTAPP_CTRL2_INVERT_TX                  0x20000000
-#define BF_UARTAPP_CTRL2_INVERT_TX(v)               (((v) << 29) & 0x20000000)
-#define BP_UARTAPP_CTRL2_INVERT_RX                  28
-#define BM_UARTAPP_CTRL2_INVERT_RX                  0x10000000
-#define BF_UARTAPP_CTRL2_INVERT_RX(v)               (((v) << 28) & 0x10000000)
-#define BP_UARTAPP_CTRL2_DMAONERR                   26
-#define BM_UARTAPP_CTRL2_DMAONERR                   0x4000000
-#define BF_UARTAPP_CTRL2_DMAONERR(v)                (((v) << 26) & 0x4000000)
-#define BP_UARTAPP_CTRL2_TXDMAE                     25
-#define BM_UARTAPP_CTRL2_TXDMAE                     0x2000000
-#define BF_UARTAPP_CTRL2_TXDMAE(v)                  (((v) << 25) & 0x2000000)
-#define BP_UARTAPP_CTRL2_RXDMAE                     24
-#define BM_UARTAPP_CTRL2_RXDMAE                     0x1000000
-#define BF_UARTAPP_CTRL2_RXDMAE(v)                  (((v) << 24) & 0x1000000)
-#define BP_UARTAPP_CTRL2_RXIFLSEL                   20
-#define BM_UARTAPP_CTRL2_RXIFLSEL                   0x700000
-#define BV_UARTAPP_CTRL2_RXIFLSEL__NOT_EMPTY        0x0
-#define BV_UARTAPP_CTRL2_RXIFLSEL__ONE_QUARTER      0x1
-#define BV_UARTAPP_CTRL2_RXIFLSEL__ONE_HALF         0x2
-#define BV_UARTAPP_CTRL2_RXIFLSEL__THREE_QUARTERS   0x3
-#define BV_UARTAPP_CTRL2_RXIFLSEL__SEVEN_EIGHTHS    0x4
-#define BV_UARTAPP_CTRL2_RXIFLSEL__INVALID5         0x5
-#define BV_UARTAPP_CTRL2_RXIFLSEL__INVALID6         0x6
-#define BV_UARTAPP_CTRL2_RXIFLSEL__INVALID7         0x7
-#define BF_UARTAPP_CTRL2_RXIFLSEL(v)                (((v) << 20) & 0x700000)
-#define BF_UARTAPP_CTRL2_RXIFLSEL_V(v)              ((BV_UARTAPP_CTRL2_RXIFLSEL__##v << 20) & 0x700000)
-#define BP_UARTAPP_CTRL2_TXIFLSEL                   16
-#define BM_UARTAPP_CTRL2_TXIFLSEL                   0x70000
-#define BV_UARTAPP_CTRL2_TXIFLSEL__EMPTY            0x0
-#define BV_UARTAPP_CTRL2_TXIFLSEL__ONE_QUARTER      0x1
-#define BV_UARTAPP_CTRL2_TXIFLSEL__ONE_HALF         0x2
-#define BV_UARTAPP_CTRL2_TXIFLSEL__THREE_QUARTERS   0x3
-#define BV_UARTAPP_CTRL2_TXIFLSEL__SEVEN_EIGHTHS    0x4
-#define BV_UARTAPP_CTRL2_TXIFLSEL__INVALID5         0x5
-#define BV_UARTAPP_CTRL2_TXIFLSEL__INVALID6         0x6
-#define BV_UARTAPP_CTRL2_TXIFLSEL__INVALID7         0x7
-#define BF_UARTAPP_CTRL2_TXIFLSEL(v)                (((v) << 16) & 0x70000)
-#define BF_UARTAPP_CTRL2_TXIFLSEL_V(v)              ((BV_UARTAPP_CTRL2_TXIFLSEL__##v << 16) & 0x70000)
-#define BP_UARTAPP_CTRL2_CTSEN                      15
-#define BM_UARTAPP_CTRL2_CTSEN                      0x8000
-#define BF_UARTAPP_CTRL2_CTSEN(v)                   (((v) << 15) & 0x8000)
-#define BP_UARTAPP_CTRL2_RTSEN                      14
-#define BM_UARTAPP_CTRL2_RTSEN                      0x4000
-#define BF_UARTAPP_CTRL2_RTSEN(v)                   (((v) << 14) & 0x4000)
-#define BP_UARTAPP_CTRL2_OUT2                       13
-#define BM_UARTAPP_CTRL2_OUT2                       0x2000
-#define BF_UARTAPP_CTRL2_OUT2(v)                    (((v) << 13) & 0x2000)
-#define BP_UARTAPP_CTRL2_OUT1                       12
-#define BM_UARTAPP_CTRL2_OUT1                       0x1000
-#define BF_UARTAPP_CTRL2_OUT1(v)                    (((v) << 12) & 0x1000)
-#define BP_UARTAPP_CTRL2_RTS                        11
-#define BM_UARTAPP_CTRL2_RTS                        0x800
-#define BF_UARTAPP_CTRL2_RTS(v)                     (((v) << 11) & 0x800)
-#define BP_UARTAPP_CTRL2_DTR                        10
-#define BM_UARTAPP_CTRL2_DTR                        0x400
-#define BF_UARTAPP_CTRL2_DTR(v)                     (((v) << 10) & 0x400)
-#define BP_UARTAPP_CTRL2_RXE                        9
-#define BM_UARTAPP_CTRL2_RXE                        0x200
-#define BF_UARTAPP_CTRL2_RXE(v)                     (((v) << 9) & 0x200)
-#define BP_UARTAPP_CTRL2_TXE                        8
-#define BM_UARTAPP_CTRL2_TXE                        0x100
-#define BF_UARTAPP_CTRL2_TXE(v)                     (((v) << 8) & 0x100)
-#define BP_UARTAPP_CTRL2_LBE                        7
-#define BM_UARTAPP_CTRL2_LBE                        0x80
-#define BF_UARTAPP_CTRL2_LBE(v)                     (((v) << 7) & 0x80)
-#define BP_UARTAPP_CTRL2_SIRLP                      2
-#define BM_UARTAPP_CTRL2_SIRLP                      0x4
-#define BF_UARTAPP_CTRL2_SIRLP(v)                   (((v) << 2) & 0x4)
-#define BP_UARTAPP_CTRL2_SIREN                      1
-#define BM_UARTAPP_CTRL2_SIREN                      0x2
-#define BF_UARTAPP_CTRL2_SIREN(v)                   (((v) << 1) & 0x2)
-#define BP_UARTAPP_CTRL2_UARTEN                     0
-#define BM_UARTAPP_CTRL2_UARTEN                     0x1
-#define BF_UARTAPP_CTRL2_UARTEN(v)                  (((v) << 0) & 0x1)
-
-/**
- * Register: HW_UARTAPP_LINECTRL
- * Address: 0x30
- * SCT: yes
-*/
-#define HW_UARTAPP_LINECTRL                 (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x30 + 0x0))
-#define HW_UARTAPP_LINECTRL_SET             (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x30 + 0x4))
-#define HW_UARTAPP_LINECTRL_CLR             (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x30 + 0x8))
-#define HW_UARTAPP_LINECTRL_TOG             (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x30 + 0xc))
-#define BP_UARTAPP_LINECTRL_BAUD_DIVINT     16
-#define BM_UARTAPP_LINECTRL_BAUD_DIVINT     0xffff0000
-#define BF_UARTAPP_LINECTRL_BAUD_DIVINT(v)  (((v) << 16) & 0xffff0000)
-#define BP_UARTAPP_LINECTRL_BAUD_DIVFRAC    8
-#define BM_UARTAPP_LINECTRL_BAUD_DIVFRAC    0x3f00
-#define BF_UARTAPP_LINECTRL_BAUD_DIVFRAC(v) (((v) << 8) & 0x3f00)
-#define BP_UARTAPP_LINECTRL_SPS             7
-#define BM_UARTAPP_LINECTRL_SPS             0x80
-#define BF_UARTAPP_LINECTRL_SPS(v)          (((v) << 7) & 0x80)
-#define BP_UARTAPP_LINECTRL_WLEN            5
-#define BM_UARTAPP_LINECTRL_WLEN            0x60
-#define BF_UARTAPP_LINECTRL_WLEN(v)         (((v) << 5) & 0x60)
-#define BP_UARTAPP_LINECTRL_FEN             4
-#define BM_UARTAPP_LINECTRL_FEN             0x10
-#define BF_UARTAPP_LINECTRL_FEN(v)          (((v) << 4) & 0x10)
-#define BP_UARTAPP_LINECTRL_STP2            3
-#define BM_UARTAPP_LINECTRL_STP2            0x8
-#define BF_UARTAPP_LINECTRL_STP2(v)         (((v) << 3) & 0x8)
-#define BP_UARTAPP_LINECTRL_EPS             2
-#define BM_UARTAPP_LINECTRL_EPS             0x4
-#define BF_UARTAPP_LINECTRL_EPS(v)          (((v) << 2) & 0x4)
-#define BP_UARTAPP_LINECTRL_PEN             1
-#define BM_UARTAPP_LINECTRL_PEN             0x2
-#define BF_UARTAPP_LINECTRL_PEN(v)          (((v) << 1) & 0x2)
-#define BP_UARTAPP_LINECTRL_BRK             0
-#define BM_UARTAPP_LINECTRL_BRK             0x1
-#define BF_UARTAPP_LINECTRL_BRK(v)          (((v) << 0) & 0x1)
-
-/**
- * Register: HW_UARTAPP_INTR
- * Address: 0x40
- * SCT: yes
-*/
-#define HW_UARTAPP_INTR             (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x40 + 0x0))
-#define HW_UARTAPP_INTR_SET         (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x40 + 0x4))
-#define HW_UARTAPP_INTR_CLR         (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x40 + 0x8))
-#define HW_UARTAPP_INTR_TOG         (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x40 + 0xc))
-#define BP_UARTAPP_INTR_OEIEN       26
-#define BM_UARTAPP_INTR_OEIEN       0x4000000
-#define BF_UARTAPP_INTR_OEIEN(v)    (((v) << 26) & 0x4000000)
-#define BP_UARTAPP_INTR_BEIEN       25
-#define BM_UARTAPP_INTR_BEIEN       0x2000000
-#define BF_UARTAPP_INTR_BEIEN(v)    (((v) << 25) & 0x2000000)
-#define BP_UARTAPP_INTR_PEIEN       24
-#define BM_UARTAPP_INTR_PEIEN       0x1000000
-#define BF_UARTAPP_INTR_PEIEN(v)    (((v) << 24) & 0x1000000)
-#define BP_UARTAPP_INTR_FEIEN       23
-#define BM_UARTAPP_INTR_FEIEN       0x800000
-#define BF_UARTAPP_INTR_FEIEN(v)    (((v) << 23) & 0x800000)
-#define BP_UARTAPP_INTR_RTIEN       22
-#define BM_UARTAPP_INTR_RTIEN       0x400000
-#define BF_UARTAPP_INTR_RTIEN(v)    (((v) << 22) & 0x400000)
-#define BP_UARTAPP_INTR_TXIEN       21
-#define BM_UARTAPP_INTR_TXIEN       0x200000
-#define BF_UARTAPP_INTR_TXIEN(v)    (((v) << 21) & 0x200000)
-#define BP_UARTAPP_INTR_RXIEN       20
-#define BM_UARTAPP_INTR_RXIEN       0x100000
-#define BF_UARTAPP_INTR_RXIEN(v)    (((v) << 20) & 0x100000)
-#define BP_UARTAPP_INTR_DSRMIEN     19
-#define BM_UARTAPP_INTR_DSRMIEN     0x80000
-#define BF_UARTAPP_INTR_DSRMIEN(v)  (((v) << 19) & 0x80000)
-#define BP_UARTAPP_INTR_DCDMIEN     18
-#define BM_UARTAPP_INTR_DCDMIEN     0x40000
-#define BF_UARTAPP_INTR_DCDMIEN(v)  (((v) << 18) & 0x40000)
-#define BP_UARTAPP_INTR_CTSMIEN     17
-#define BM_UARTAPP_INTR_CTSMIEN     0x20000
-#define BF_UARTAPP_INTR_CTSMIEN(v)  (((v) << 17) & 0x20000)
-#define BP_UARTAPP_INTR_RIMIEN      16
-#define BM_UARTAPP_INTR_RIMIEN      0x10000
-#define BF_UARTAPP_INTR_RIMIEN(v)   (((v) << 16) & 0x10000)
-#define BP_UARTAPP_INTR_OEIS        10
-#define BM_UARTAPP_INTR_OEIS        0x400
-#define BF_UARTAPP_INTR_OEIS(v)     (((v) << 10) & 0x400)
-#define BP_UARTAPP_INTR_BEIS        9
-#define BM_UARTAPP_INTR_BEIS        0x200
-#define BF_UARTAPP_INTR_BEIS(v)     (((v) << 9) & 0x200)
-#define BP_UARTAPP_INTR_PEIS        8
-#define BM_UARTAPP_INTR_PEIS        0x100
-#define BF_UARTAPP_INTR_PEIS(v)     (((v) << 8) & 0x100)
-#define BP_UARTAPP_INTR_FEIS        7
-#define BM_UARTAPP_INTR_FEIS        0x80
-#define BF_UARTAPP_INTR_FEIS(v)     (((v) << 7) & 0x80)
-#define BP_UARTAPP_INTR_RTIS        6
-#define BM_UARTAPP_INTR_RTIS        0x40
-#define BF_UARTAPP_INTR_RTIS(v)     (((v) << 6) & 0x40)
-#define BP_UARTAPP_INTR_TXIS        5
-#define BM_UARTAPP_INTR_TXIS        0x20
-#define BF_UARTAPP_INTR_TXIS(v)     (((v) << 5) & 0x20)
-#define BP_UARTAPP_INTR_RXIS        4
-#define BM_UARTAPP_INTR_RXIS        0x10
-#define BF_UARTAPP_INTR_RXIS(v)     (((v) << 4) & 0x10)
-#define BP_UARTAPP_INTR_DSRMIS      3
-#define BM_UARTAPP_INTR_DSRMIS      0x8
-#define BF_UARTAPP_INTR_DSRMIS(v)   (((v) << 3) & 0x8)
-#define BP_UARTAPP_INTR_DCDMIS      2
-#define BM_UARTAPP_INTR_DCDMIS      0x4
-#define BF_UARTAPP_INTR_DCDMIS(v)   (((v) << 2) & 0x4)
-#define BP_UARTAPP_INTR_CTSMIS      1
-#define BM_UARTAPP_INTR_CTSMIS      0x2
-#define BF_UARTAPP_INTR_CTSMIS(v)   (((v) << 1) & 0x2)
-#define BP_UARTAPP_INTR_RIMIS       0
-#define BM_UARTAPP_INTR_RIMIS       0x1
-#define BF_UARTAPP_INTR_RIMIS(v)    (((v) << 0) & 0x1)
-
-/**
- * Register: HW_UARTAPP_DATA
- * Address: 0x50
- * SCT: no
-*/
-#define HW_UARTAPP_DATA         (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x50))
-#define BP_UARTAPP_DATA_DATA    0
-#define BM_UARTAPP_DATA_DATA    0xffffffff
-#define BF_UARTAPP_DATA_DATA(v) (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_UARTAPP_STAT
- * Address: 0x60
- * SCT: no
-*/
-#define HW_UARTAPP_STAT                         (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x60))
-#define BP_UARTAPP_STAT_PRESENT                 31
-#define BM_UARTAPP_STAT_PRESENT                 0x80000000
-#define BV_UARTAPP_STAT_PRESENT__UNAVAILABLE    0x0
-#define BV_UARTAPP_STAT_PRESENT__AVAILABLE      0x1
-#define BF_UARTAPP_STAT_PRESENT(v)              (((v) << 31) & 0x80000000)
-#define BF_UARTAPP_STAT_PRESENT_V(v)            ((BV_UARTAPP_STAT_PRESENT__##v << 31) & 0x80000000)
-#define BP_UARTAPP_STAT_HISPEED                 30
-#define BM_UARTAPP_STAT_HISPEED                 0x40000000
-#define BV_UARTAPP_STAT_HISPEED__UNAVAILABLE    0x0
-#define BV_UARTAPP_STAT_HISPEED__AVAILABLE      0x1
-#define BF_UARTAPP_STAT_HISPEED(v)              (((v) << 30) & 0x40000000)
-#define BF_UARTAPP_STAT_HISPEED_V(v)            ((BV_UARTAPP_STAT_HISPEED__##v << 30) & 0x40000000)
-#define BP_UARTAPP_STAT_BUSY                    29
-#define BM_UARTAPP_STAT_BUSY                    0x20000000
-#define BF_UARTAPP_STAT_BUSY(v)                 (((v) << 29) & 0x20000000)
-#define BP_UARTAPP_STAT_CTS                     28
-#define BM_UARTAPP_STAT_CTS                     0x10000000
-#define BF_UARTAPP_STAT_CTS(v)                  (((v) << 28) & 0x10000000)
-#define BP_UARTAPP_STAT_TXFE                    27
-#define BM_UARTAPP_STAT_TXFE                    0x8000000
-#define BF_UARTAPP_STAT_TXFE(v)                 (((v) << 27) & 0x8000000)
-#define BP_UARTAPP_STAT_RXFF                    26
-#define BM_UARTAPP_STAT_RXFF                    0x4000000
-#define BF_UARTAPP_STAT_RXFF(v)                 (((v) << 26) & 0x4000000)
-#define BP_UARTAPP_STAT_TXFF                    25
-#define BM_UARTAPP_STAT_TXFF                    0x2000000
-#define BF_UARTAPP_STAT_TXFF(v)                 (((v) << 25) & 0x2000000)
-#define BP_UARTAPP_STAT_RXFE                    24
-#define BM_UARTAPP_STAT_RXFE                    0x1000000
-#define BF_UARTAPP_STAT_RXFE(v)                 (((v) << 24) & 0x1000000)
-#define BP_UARTAPP_STAT_RXBYTE_INVALID          20
-#define BM_UARTAPP_STAT_RXBYTE_INVALID          0xf00000
-#define BF_UARTAPP_STAT_RXBYTE_INVALID(v)       (((v) << 20) & 0xf00000)
-#define BP_UARTAPP_STAT_OERR                    19
-#define BM_UARTAPP_STAT_OERR                    0x80000
-#define BF_UARTAPP_STAT_OERR(v)                 (((v) << 19) & 0x80000)
-#define BP_UARTAPP_STAT_BERR                    18
-#define BM_UARTAPP_STAT_BERR                    0x40000
-#define BF_UARTAPP_STAT_BERR(v)                 (((v) << 18) & 0x40000)
-#define BP_UARTAPP_STAT_PERR                    17
-#define BM_UARTAPP_STAT_PERR                    0x20000
-#define BF_UARTAPP_STAT_PERR(v)                 (((v) << 17) & 0x20000)
-#define BP_UARTAPP_STAT_FERR                    16
-#define BM_UARTAPP_STAT_FERR                    0x10000
-#define BF_UARTAPP_STAT_FERR(v)                 (((v) << 16) & 0x10000)
-#define BP_UARTAPP_STAT_RXCOUNT                 0
-#define BM_UARTAPP_STAT_RXCOUNT                 0xffff
-#define BF_UARTAPP_STAT_RXCOUNT(v)              (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_UARTAPP_DEBUG
- * Address: 0x70
- * SCT: no
-*/
-#define HW_UARTAPP_DEBUG                (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x70))
-#define BP_UARTAPP_DEBUG_TXDMARUN       5
-#define BM_UARTAPP_DEBUG_TXDMARUN       0x20
-#define BF_UARTAPP_DEBUG_TXDMARUN(v)    (((v) << 5) & 0x20)
-#define BP_UARTAPP_DEBUG_RXDMARUN       4
-#define BM_UARTAPP_DEBUG_RXDMARUN       0x10
-#define BF_UARTAPP_DEBUG_RXDMARUN(v)    (((v) << 4) & 0x10)
-#define BP_UARTAPP_DEBUG_TXCMDEND       3
-#define BM_UARTAPP_DEBUG_TXCMDEND       0x8
-#define BF_UARTAPP_DEBUG_TXCMDEND(v)    (((v) << 3) & 0x8)
-#define BP_UARTAPP_DEBUG_RXCMDEND       2
-#define BM_UARTAPP_DEBUG_RXCMDEND       0x4
-#define BF_UARTAPP_DEBUG_RXCMDEND(v)    (((v) << 2) & 0x4)
-#define BP_UARTAPP_DEBUG_TXDMARQ        1
-#define BM_UARTAPP_DEBUG_TXDMARQ        0x2
-#define BF_UARTAPP_DEBUG_TXDMARQ(v)     (((v) << 1) & 0x2)
-#define BP_UARTAPP_DEBUG_RXDMARQ        0
-#define BM_UARTAPP_DEBUG_RXDMARQ        0x1
-#define BF_UARTAPP_DEBUG_RXDMARQ(v)     (((v) << 0) & 0x1)
-
-#endif /* __HEADERGEN__STMP3600__UARTAPP__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-uartdbg.h b/firmware/target/arm/imx233/regs/stmp3600/regs-uartdbg.h
deleted file mode 100644
index 96491285e1..0000000000
--- a/firmware/target/arm/imx233/regs/stmp3600/regs-uartdbg.h
+++ /dev/null
@@ -1,491 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3600:2.3.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__STMP3600__UARTDBG__H__
-#define __HEADERGEN__STMP3600__UARTDBG__H__
-
-#define REGS_UARTDBG_BASE (0x80070000)
-
-#define REGS_UARTDBG_VERSION "2.3.0"
-
-/**
- * Register: HW_UARTDBG_DR
- * Address: 0
- * SCT: no
-*/
-#define HW_UARTDBG_DR                   (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x0))
-#define BP_UARTDBG_DR_UNAVAILABLE       16
-#define BM_UARTDBG_DR_UNAVAILABLE       0xffff0000
-#define BF_UARTDBG_DR_UNAVAILABLE(v)    (((v) << 16) & 0xffff0000)
-#define BP_UARTDBG_DR_RESERVED          12
-#define BM_UARTDBG_DR_RESERVED          0xf000
-#define BF_UARTDBG_DR_RESERVED(v)       (((v) << 12) & 0xf000)
-#define BP_UARTDBG_DR_OE                11
-#define BM_UARTDBG_DR_OE                0x800
-#define BF_UARTDBG_DR_OE(v)             (((v) << 11) & 0x800)
-#define BP_UARTDBG_DR_BE                10
-#define BM_UARTDBG_DR_BE                0x400
-#define BF_UARTDBG_DR_BE(v)             (((v) << 10) & 0x400)
-#define BP_UARTDBG_DR_PE                9
-#define BM_UARTDBG_DR_PE                0x200
-#define BF_UARTDBG_DR_PE(v)             (((v) << 9) & 0x200)
-#define BP_UARTDBG_DR_FE                8
-#define BM_UARTDBG_DR_FE                0x100
-#define BF_UARTDBG_DR_FE(v)             (((v) << 8) & 0x100)
-#define BP_UARTDBG_DR_DATA              0
-#define BM_UARTDBG_DR_DATA              0xff
-#define BF_UARTDBG_DR_DATA(v)           (((v) << 0) & 0xff)
-
-/**
- * Register: HW_UARTDBG_RSR_ECR
- * Address: 0x4
- * SCT: no
-*/
-#define HW_UARTDBG_RSR_ECR                  (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x4))
-#define BP_UARTDBG_RSR_ECR_UNAVAILABLE      8
-#define BM_UARTDBG_RSR_ECR_UNAVAILABLE      0xffffff00
-#define BF_UARTDBG_RSR_ECR_UNAVAILABLE(v)   (((v) << 8) & 0xffffff00)
-#define BP_UARTDBG_RSR_ECR_EC               4
-#define BM_UARTDBG_RSR_ECR_EC               0xf0
-#define BF_UARTDBG_RSR_ECR_EC(v)            (((v) << 4) & 0xf0)
-#define BP_UARTDBG_RSR_ECR_OE               3
-#define BM_UARTDBG_RSR_ECR_OE               0x8
-#define BF_UARTDBG_RSR_ECR_OE(v)            (((v) << 3) & 0x8)
-#define BP_UARTDBG_RSR_ECR_BE               2
-#define BM_UARTDBG_RSR_ECR_BE               0x4
-#define BF_UARTDBG_RSR_ECR_BE(v)            (((v) << 2) & 0x4)
-#define BP_UARTDBG_RSR_ECR_PE               1
-#define BM_UARTDBG_RSR_ECR_PE               0x2
-#define BF_UARTDBG_RSR_ECR_PE(v)            (((v) << 1) & 0x2)
-#define BP_UARTDBG_RSR_ECR_FE               0
-#define BM_UARTDBG_RSR_ECR_FE               0x1
-#define BF_UARTDBG_RSR_ECR_FE(v)            (((v) << 0) & 0x1)
-
-/**
- * Register: HW_UARTDBG_FR
- * Address: 0x18
- * SCT: no
-*/
-#define HW_UARTDBG_FR                   (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x18))
-#define BP_UARTDBG_FR_UNAVAILABLE       16
-#define BM_UARTDBG_FR_UNAVAILABLE       0xffff0000
-#define BF_UARTDBG_FR_UNAVAILABLE(v)    (((v) << 16) & 0xffff0000)
-#define BP_UARTDBG_FR_RESERVED          9
-#define BM_UARTDBG_FR_RESERVED          0xfe00
-#define BF_UARTDBG_FR_RESERVED(v)       (((v) << 9) & 0xfe00)
-#define BP_UARTDBG_FR_RI                8
-#define BM_UARTDBG_FR_RI                0x100
-#define BF_UARTDBG_FR_RI(v)             (((v) << 8) & 0x100)
-#define BP_UARTDBG_FR_TXFE              7
-#define BM_UARTDBG_FR_TXFE              0x80
-#define BF_UARTDBG_FR_TXFE(v)           (((v) << 7) & 0x80)
-#define BP_UARTDBG_FR_RXFF              6
-#define BM_UARTDBG_FR_RXFF              0x40
-#define BF_UARTDBG_FR_RXFF(v)           (((v) << 6) & 0x40)
-#define BP_UARTDBG_FR_TXFF              5
-#define BM_UARTDBG_FR_TXFF              0x20
-#define BF_UARTDBG_FR_TXFF(v)           (((v) << 5) & 0x20)
-#define BP_UARTDBG_FR_RXFE              4
-#define BM_UARTDBG_FR_RXFE              0x10
-#define BF_UARTDBG_FR_RXFE(v)           (((v) << 4) & 0x10)
-#define BP_UARTDBG_FR_BUSY              3
-#define BM_UARTDBG_FR_BUSY              0x8
-#define BF_UARTDBG_FR_BUSY(v)           (((v) << 3) & 0x8)
-#define BP_UARTDBG_FR_DCD               2
-#define BM_UARTDBG_FR_DCD               0x4
-#define BF_UARTDBG_FR_DCD(v)            (((v) << 2) & 0x4)
-#define BP_UARTDBG_FR_DSR               1
-#define BM_UARTDBG_FR_DSR               0x2
-#define BF_UARTDBG_FR_DSR(v)            (((v) << 1) & 0x2)
-#define BP_UARTDBG_FR_CTS               0
-#define BM_UARTDBG_FR_CTS               0x1
-#define BF_UARTDBG_FR_CTS(v)            (((v) << 0) & 0x1)
-
-/**
- * Register: HW_UARTDBG_ILPR
- * Address: 0x20
- * SCT: no
-*/
-#define HW_UARTDBG_ILPR                 (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x20))
-#define BP_UARTDBG_ILPR_UNAVAILABLE     8
-#define BM_UARTDBG_ILPR_UNAVAILABLE     0xffffff00
-#define BF_UARTDBG_ILPR_UNAVAILABLE(v)  (((v) << 8) & 0xffffff00)
-#define BP_UARTDBG_ILPR_ILPDVSR         0
-#define BM_UARTDBG_ILPR_ILPDVSR         0xff
-#define BF_UARTDBG_ILPR_ILPDVSR(v)      (((v) << 0) & 0xff)
-
-/**
- * Register: HW_UARTDBG_IBRD
- * Address: 0x24
- * SCT: no
-*/
-#define HW_UARTDBG_IBRD                 (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x24))
-#define BP_UARTDBG_IBRD_UNAVAILABLE     16
-#define BM_UARTDBG_IBRD_UNAVAILABLE     0xffff0000
-#define BF_UARTDBG_IBRD_UNAVAILABLE(v)  (((v) << 16) & 0xffff0000)
-#define BP_UARTDBG_IBRD_BAUD_DIVINT     0
-#define BM_UARTDBG_IBRD_BAUD_DIVINT     0xffff
-#define BF_UARTDBG_IBRD_BAUD_DIVINT(v)  (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_UARTDBG_FBRD
- * Address: 0x28
- * SCT: no
-*/
-#define HW_UARTDBG_FBRD                 (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x28))
-#define BP_UARTDBG_FBRD_UNAVAILABLE     8
-#define BM_UARTDBG_FBRD_UNAVAILABLE     0xffffff00
-#define BF_UARTDBG_FBRD_UNAVAILABLE(v)  (((v) << 8) & 0xffffff00)
-#define BP_UARTDBG_FBRD_RESERVED        6
-#define BM_UARTDBG_FBRD_RESERVED        0xc0
-#define BF_UARTDBG_FBRD_RESERVED(v)     (((v) << 6) & 0xc0)
-#define BP_UARTDBG_FBRD_BAUD_DIVFRAC    0
-#define BM_UARTDBG_FBRD_BAUD_DIVFRAC    0x3f
-#define BF_UARTDBG_FBRD_BAUD_DIVFRAC(v) (((v) << 0) & 0x3f)
-
-/**
- * Register: HW_UARTDBG_LCR_H
- * Address: 0x2c
- * SCT: no
-*/
-#define HW_UARTDBG_LCR_H                (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x2c))
-#define BP_UARTDBG_LCR_H_UNAVAILABLE    16
-#define BM_UARTDBG_LCR_H_UNAVAILABLE    0xffff0000
-#define BF_UARTDBG_LCR_H_UNAVAILABLE(v) (((v) << 16) & 0xffff0000)
-#define BP_UARTDBG_LCR_H_RESERVED       8
-#define BM_UARTDBG_LCR_H_RESERVED       0xff00
-#define BF_UARTDBG_LCR_H_RESERVED(v)    (((v) << 8) & 0xff00)
-#define BP_UARTDBG_LCR_H_SPS            7
-#define BM_UARTDBG_LCR_H_SPS            0x80
-#define BF_UARTDBG_LCR_H_SPS(v)         (((v) << 7) & 0x80)
-#define BP_UARTDBG_LCR_H_WLEN           5
-#define BM_UARTDBG_LCR_H_WLEN           0x60
-#define BF_UARTDBG_LCR_H_WLEN(v)        (((v) << 5) & 0x60)
-#define BP_UARTDBG_LCR_H_FEN            4
-#define BM_UARTDBG_LCR_H_FEN            0x10
-#define BF_UARTDBG_LCR_H_FEN(v)         (((v) << 4) & 0x10)
-#define BP_UARTDBG_LCR_H_STP2           3
-#define BM_UARTDBG_LCR_H_STP2           0x8
-#define BF_UARTDBG_LCR_H_STP2(v)        (((v) << 3) & 0x8)
-#define BP_UARTDBG_LCR_H_EPS            2
-#define BM_UARTDBG_LCR_H_EPS            0x4
-#define BF_UARTDBG_LCR_H_EPS(v)         (((v) << 2) & 0x4)
-#define BP_UARTDBG_LCR_H_PEN            1
-#define BM_UARTDBG_LCR_H_PEN            0x2
-#define BF_UARTDBG_LCR_H_PEN(v)         (((v) << 1) & 0x2)
-#define BP_UARTDBG_LCR_H_BRK            0
-#define BM_UARTDBG_LCR_H_BRK            0x1
-#define BF_UARTDBG_LCR_H_BRK(v)         (((v) << 0) & 0x1)
-
-/**
- * Register: HW_UARTDBG_CR
- * Address: 0x30
- * SCT: no
-*/
-#define HW_UARTDBG_CR                   (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x30))
-#define BP_UARTDBG_CR_UNAVAILABLE       16
-#define BM_UARTDBG_CR_UNAVAILABLE       0xffff0000
-#define BF_UARTDBG_CR_UNAVAILABLE(v)    (((v) << 16) & 0xffff0000)
-#define BP_UARTDBG_CR_CTSEN             15
-#define BM_UARTDBG_CR_CTSEN             0x8000
-#define BF_UARTDBG_CR_CTSEN(v)          (((v) << 15) & 0x8000)
-#define BP_UARTDBG_CR_RTSEN             14
-#define BM_UARTDBG_CR_RTSEN             0x4000
-#define BF_UARTDBG_CR_RTSEN(v)          (((v) << 14) & 0x4000)
-#define BP_UARTDBG_CR_OUT2              13
-#define BM_UARTDBG_CR_OUT2              0x2000
-#define BF_UARTDBG_CR_OUT2(v)           (((v) << 13) & 0x2000)
-#define BP_UARTDBG_CR_OUT1              12
-#define BM_UARTDBG_CR_OUT1              0x1000
-#define BF_UARTDBG_CR_OUT1(v)           (((v) << 12) & 0x1000)
-#define BP_UARTDBG_CR_RTS               11
-#define BM_UARTDBG_CR_RTS               0x800
-#define BF_UARTDBG_CR_RTS(v)            (((v) << 11) & 0x800)
-#define BP_UARTDBG_CR_DTR               10
-#define BM_UARTDBG_CR_DTR               0x400
-#define BF_UARTDBG_CR_DTR(v)            (((v) << 10) & 0x400)
-#define BP_UARTDBG_CR_RXE               9
-#define BM_UARTDBG_CR_RXE               0x200
-#define BF_UARTDBG_CR_RXE(v)            (((v) << 9) & 0x200)
-#define BP_UARTDBG_CR_TXE               8
-#define BM_UARTDBG_CR_TXE               0x100
-#define BF_UARTDBG_CR_TXE(v)            (((v) << 8) & 0x100)
-#define BP_UARTDBG_CR_LBE               7
-#define BM_UARTDBG_CR_LBE               0x80
-#define BF_UARTDBG_CR_LBE(v)            (((v) << 7) & 0x80)
-#define BP_UARTDBG_CR_RESERVED          3
-#define BM_UARTDBG_CR_RESERVED          0x78
-#define BF_UARTDBG_CR_RESERVED(v)       (((v) << 3) & 0x78)
-#define BP_UARTDBG_CR_SIRLP             2
-#define BM_UARTDBG_CR_SIRLP             0x4
-#define BF_UARTDBG_CR_SIRLP(v)          (((v) << 2) & 0x4)
-#define BP_UARTDBG_CR_SIREN             1
-#define BM_UARTDBG_CR_SIREN             0x2
-#define BF_UARTDBG_CR_SIREN(v)          (((v) << 1) & 0x2)
-#define BP_UARTDBG_CR_UARTEN            0
-#define BM_UARTDBG_CR_UARTEN            0x1
-#define BF_UARTDBG_CR_UARTEN(v)         (((v) << 0) & 0x1)
-
-/**
- * Register: HW_UARTDBG_IFLS
- * Address: 0x34
- * SCT: no
-*/
-#define HW_UARTDBG_IFLS                             (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x34))
-#define BP_UARTDBG_IFLS_UNAVAILABLE                 16
-#define BM_UARTDBG_IFLS_UNAVAILABLE                 0xffff0000
-#define BF_UARTDBG_IFLS_UNAVAILABLE(v)              (((v) << 16) & 0xffff0000)
-#define BP_UARTDBG_IFLS_RESERVED                    6
-#define BM_UARTDBG_IFLS_RESERVED                    0xffc0
-#define BF_UARTDBG_IFLS_RESERVED(v)                 (((v) << 6) & 0xffc0)
-#define BP_UARTDBG_IFLS_RXIFLSEL                    3
-#define BM_UARTDBG_IFLS_RXIFLSEL                    0x38
-#define BV_UARTDBG_IFLS_RXIFLSEL__NOT_EMPTY         0x0
-#define BV_UARTDBG_IFLS_RXIFLSEL__ONE_QUARTER       0x1
-#define BV_UARTDBG_IFLS_RXIFLSEL__ONE_HALF          0x2
-#define BV_UARTDBG_IFLS_RXIFLSEL__THREE_QUARTERS    0x3
-#define BV_UARTDBG_IFLS_RXIFLSEL__SEVEN_EIGHTHS     0x4
-#define BV_UARTDBG_IFLS_RXIFLSEL__INVALID5          0x5
-#define BV_UARTDBG_IFLS_RXIFLSEL__INVALID6          0x6
-#define BV_UARTDBG_IFLS_RXIFLSEL__INVALID7          0x7
-#define BF_UARTDBG_IFLS_RXIFLSEL(v)                 (((v) << 3) & 0x38)
-#define BF_UARTDBG_IFLS_RXIFLSEL_V(v)               ((BV_UARTDBG_IFLS_RXIFLSEL__##v << 3) & 0x38)
-#define BP_UARTDBG_IFLS_TXIFLSEL                    0
-#define BM_UARTDBG_IFLS_TXIFLSEL                    0x7
-#define BV_UARTDBG_IFLS_TXIFLSEL__EMPTY             0x0
-#define BV_UARTDBG_IFLS_TXIFLSEL__ONE_QUARTER       0x1
-#define BV_UARTDBG_IFLS_TXIFLSEL__ONE_HALF          0x2
-#define BV_UARTDBG_IFLS_TXIFLSEL__THREE_QUARTERS    0x3
-#define BV_UARTDBG_IFLS_TXIFLSEL__SEVEN_EIGHTHS     0x4
-#define BV_UARTDBG_IFLS_TXIFLSEL__INVALID5          0x5
-#define BV_UARTDBG_IFLS_TXIFLSEL__INVALID6          0x6
-#define BV_UARTDBG_IFLS_TXIFLSEL__INVALID7          0x7
-#define BF_UARTDBG_IFLS_TXIFLSEL(v)                 (((v) << 0) & 0x7)
-#define BF_UARTDBG_IFLS_TXIFLSEL_V(v)               ((BV_UARTDBG_IFLS_TXIFLSEL__##v << 0) & 0x7)
-
-/**
- * Register: HW_UARTDBG_IMSC
- * Address: 0x38
- * SCT: no
-*/
-#define HW_UARTDBG_IMSC                 (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x38))
-#define BP_UARTDBG_IMSC_UNAVAILABLE     16
-#define BM_UARTDBG_IMSC_UNAVAILABLE     0xffff0000
-#define BF_UARTDBG_IMSC_UNAVAILABLE(v)  (((v) << 16) & 0xffff0000)
-#define BP_UARTDBG_IMSC_RESERVED        11
-#define BM_UARTDBG_IMSC_RESERVED        0xf800
-#define BF_UARTDBG_IMSC_RESERVED(v)     (((v) << 11) & 0xf800)
-#define BP_UARTDBG_IMSC_OEIM            10
-#define BM_UARTDBG_IMSC_OEIM            0x400
-#define BF_UARTDBG_IMSC_OEIM(v)         (((v) << 10) & 0x400)
-#define BP_UARTDBG_IMSC_BEIM            9
-#define BM_UARTDBG_IMSC_BEIM            0x200
-#define BF_UARTDBG_IMSC_BEIM(v)         (((v) << 9) & 0x200)
-#define BP_UARTDBG_IMSC_PEIM            8
-#define BM_UARTDBG_IMSC_PEIM            0x100
-#define BF_UARTDBG_IMSC_PEIM(v)         (((v) << 8) & 0x100)
-#define BP_UARTDBG_IMSC_FEIM            7
-#define BM_UARTDBG_IMSC_FEIM            0x80
-#define BF_UARTDBG_IMSC_FEIM(v)         (((v) << 7) & 0x80)
-#define BP_UARTDBG_IMSC_RTIM            6
-#define BM_UARTDBG_IMSC_RTIM            0x40
-#define BF_UARTDBG_IMSC_RTIM(v)         (((v) << 6) & 0x40)
-#define BP_UARTDBG_IMSC_TXIM            5
-#define BM_UARTDBG_IMSC_TXIM            0x20
-#define BF_UARTDBG_IMSC_TXIM(v)         (((v) << 5) & 0x20)
-#define BP_UARTDBG_IMSC_RXIM            4
-#define BM_UARTDBG_IMSC_RXIM            0x10
-#define BF_UARTDBG_IMSC_RXIM(v)         (((v) << 4) & 0x10)
-#define BP_UARTDBG_IMSC_DSRMIM          3
-#define BM_UARTDBG_IMSC_DSRMIM          0x8
-#define BF_UARTDBG_IMSC_DSRMIM(v)       (((v) << 3) & 0x8)
-#define BP_UARTDBG_IMSC_DCDMIM          2
-#define BM_UARTDBG_IMSC_DCDMIM          0x4
-#define BF_UARTDBG_IMSC_DCDMIM(v)       (((v) << 2) & 0x4)
-#define BP_UARTDBG_IMSC_CTSMIM          1
-#define BM_UARTDBG_IMSC_CTSMIM          0x2
-#define BF_UARTDBG_IMSC_CTSMIM(v)       (((v) << 1) & 0x2)
-#define BP_UARTDBG_IMSC_RIMIM           0
-#define BM_UARTDBG_IMSC_RIMIM           0x1
-#define BF_UARTDBG_IMSC_RIMIM(v)        (((v) << 0) & 0x1)
-
-/**
- * Register: HW_UARTDBG_RIS
- * Address: 0x3c
- * SCT: no
-*/
-#define HW_UARTDBG_RIS                  (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x3c))
-#define BP_UARTDBG_RIS_UNAVAILABLE      16
-#define BM_UARTDBG_RIS_UNAVAILABLE      0xffff0000
-#define BF_UARTDBG_RIS_UNAVAILABLE(v)   (((v) << 16) & 0xffff0000)
-#define BP_UARTDBG_RIS_RESERVED         11
-#define BM_UARTDBG_RIS_RESERVED         0xf800
-#define BF_UARTDBG_RIS_RESERVED(v)      (((v) << 11) & 0xf800)
-#define BP_UARTDBG_RIS_OERIS            10
-#define BM_UARTDBG_RIS_OERIS            0x400
-#define BF_UARTDBG_RIS_OERIS(v)         (((v) << 10) & 0x400)
-#define BP_UARTDBG_RIS_BERIS            9
-#define BM_UARTDBG_RIS_BERIS            0x200
-#define BF_UARTDBG_RIS_BERIS(v)         (((v) << 9) & 0x200)
-#define BP_UARTDBG_RIS_PERIS            8
-#define BM_UARTDBG_RIS_PERIS            0x100
-#define BF_UARTDBG_RIS_PERIS(v)         (((v) << 8) & 0x100)
-#define BP_UARTDBG_RIS_FERIS            7
-#define BM_UARTDBG_RIS_FERIS            0x80
-#define BF_UARTDBG_RIS_FERIS(v)         (((v) << 7) & 0x80)
-#define BP_UARTDBG_RIS_RTRIS            6
-#define BM_UARTDBG_RIS_RTRIS            0x40
-#define BF_UARTDBG_RIS_RTRIS(v)         (((v) << 6) & 0x40)
-#define BP_UARTDBG_RIS_TXRIS            5
-#define BM_UARTDBG_RIS_TXRIS            0x20
-#define BF_UARTDBG_RIS_TXRIS(v)         (((v) << 5) & 0x20)
-#define BP_UARTDBG_RIS_RXRIS            4
-#define BM_UARTDBG_RIS_RXRIS            0x10
-#define BF_UARTDBG_RIS_RXRIS(v)         (((v) << 4) & 0x10)
-#define BP_UARTDBG_RIS_DSRRMIS          3
-#define BM_UARTDBG_RIS_DSRRMIS          0x8
-#define BF_UARTDBG_RIS_DSRRMIS(v)       (((v) << 3) & 0x8)
-#define BP_UARTDBG_RIS_DCDRMIS          2
-#define BM_UARTDBG_RIS_DCDRMIS          0x4
-#define BF_UARTDBG_RIS_DCDRMIS(v)       (((v) << 2) & 0x4)
-#define BP_UARTDBG_RIS_CTSRMIS          1
-#define BM_UARTDBG_RIS_CTSRMIS          0x2
-#define BF_UARTDBG_RIS_CTSRMIS(v)       (((v) << 1) & 0x2)
-#define BP_UARTDBG_RIS_RIRMIS           0
-#define BM_UARTDBG_RIS_RIRMIS           0x1
-#define BF_UARTDBG_RIS_RIRMIS(v)        (((v) << 0) & 0x1)
-
-/**
- * Register: HW_UARTDBG_MIS
- * Address: 0x40
- * SCT: no
-*/
-#define HW_UARTDBG_MIS                  (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x40))
-#define BP_UARTDBG_MIS_UNAVAILABLE      16
-#define BM_UARTDBG_MIS_UNAVAILABLE      0xffff0000
-#define BF_UARTDBG_MIS_UNAVAILABLE(v)   (((v) << 16) & 0xffff0000)
-#define BP_UARTDBG_MIS_RESERVED         11
-#define BM_UARTDBG_MIS_RESERVED         0xf800
-#define BF_UARTDBG_MIS_RESERVED(v)      (((v) << 11) & 0xf800)
-#define BP_UARTDBG_MIS_OEMIS            10
-#define BM_UARTDBG_MIS_OEMIS            0x400
-#define BF_UARTDBG_MIS_OEMIS(v)         (((v) << 10) & 0x400)
-#define BP_UARTDBG_MIS_BEMIS            9
-#define BM_UARTDBG_MIS_BEMIS            0x200
-#define BF_UARTDBG_MIS_BEMIS(v)         (((v) << 9) & 0x200)
-#define BP_UARTDBG_MIS_PEMIS            8
-#define BM_UARTDBG_MIS_PEMIS            0x100
-#define BF_UARTDBG_MIS_PEMIS(v)         (((v) << 8) & 0x100)
-#define BP_UARTDBG_MIS_FEMIS            7
-#define BM_UARTDBG_MIS_FEMIS            0x80
-#define BF_UARTDBG_MIS_FEMIS(v)         (((v) << 7) & 0x80)
-#define BP_UARTDBG_MIS_RTMIS            6
-#define BM_UARTDBG_MIS_RTMIS            0x40
-#define BF_UARTDBG_MIS_RTMIS(v)         (((v) << 6) & 0x40)
-#define BP_UARTDBG_MIS_TXMIS            5
-#define BM_UARTDBG_MIS_TXMIS            0x20
-#define BF_UARTDBG_MIS_TXMIS(v)         (((v) << 5) & 0x20)
-#define BP_UARTDBG_MIS_RXMIS            4
-#define BM_UARTDBG_MIS_RXMIS            0x10
-#define BF_UARTDBG_MIS_RXMIS(v)         (((v) << 4) & 0x10)
-#define BP_UARTDBG_MIS_DSRMMIS          3
-#define BM_UARTDBG_MIS_DSRMMIS          0x8
-#define BF_UARTDBG_MIS_DSRMMIS(v)       (((v) << 3) & 0x8)
-#define BP_UARTDBG_MIS_DCDMMIS          2
-#define BM_UARTDBG_MIS_DCDMMIS          0x4
-#define BF_UARTDBG_MIS_DCDMMIS(v)       (((v) << 2) & 0x4)
-#define BP_UARTDBG_MIS_CTSMMIS          1
-#define BM_UARTDBG_MIS_CTSMMIS          0x2
-#define BF_UARTDBG_MIS_CTSMMIS(v)       (((v) << 1) & 0x2)
-#define BP_UARTDBG_MIS_RIMMIS           0
-#define BM_UARTDBG_MIS_RIMMIS           0x1
-#define BF_UARTDBG_MIS_RIMMIS(v)        (((v) << 0) & 0x1)
-
-/**
- * Register: HW_UARTDBG_ICR
- * Address: 0x44
- * SCT: no
-*/
-#define HW_UARTDBG_ICR                  (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x44))
-#define BP_UARTDBG_ICR_UNAVAILABLE      16
-#define BM_UARTDBG_ICR_UNAVAILABLE      0xffff0000
-#define BF_UARTDBG_ICR_UNAVAILABLE(v)   (((v) << 16) & 0xffff0000)
-#define BP_UARTDBG_ICR_RESERVED         11
-#define BM_UARTDBG_ICR_RESERVED         0xf800
-#define BF_UARTDBG_ICR_RESERVED(v)      (((v) << 11) & 0xf800)
-#define BP_UARTDBG_ICR_OEIC             10
-#define BM_UARTDBG_ICR_OEIC             0x400
-#define BF_UARTDBG_ICR_OEIC(v)          (((v) << 10) & 0x400)
-#define BP_UARTDBG_ICR_BEIC             9
-#define BM_UARTDBG_ICR_BEIC             0x200
-#define BF_UARTDBG_ICR_BEIC(v)          (((v) << 9) & 0x200)
-#define BP_UARTDBG_ICR_PEIC             8
-#define BM_UARTDBG_ICR_PEIC             0x100
-#define BF_UARTDBG_ICR_PEIC(v)          (((v) << 8) & 0x100)
-#define BP_UARTDBG_ICR_FEIC             7
-#define BM_UARTDBG_ICR_FEIC             0x80
-#define BF_UARTDBG_ICR_FEIC(v)          (((v) << 7) & 0x80)
-#define BP_UARTDBG_ICR_RTIC             6
-#define BM_UARTDBG_ICR_RTIC             0x40
-#define BF_UARTDBG_ICR_RTIC(v)          (((v) << 6) & 0x40)
-#define BP_UARTDBG_ICR_TXIC             5
-#define BM_UARTDBG_ICR_TXIC             0x20
-#define BF_UARTDBG_ICR_TXIC(v)          (((v) << 5) & 0x20)
-#define BP_UARTDBG_ICR_RXIC             4
-#define BM_UARTDBG_ICR_RXIC             0x10
-#define BF_UARTDBG_ICR_RXIC(v)          (((v) << 4) & 0x10)
-#define BP_UARTDBG_ICR_DSRMIC           3
-#define BM_UARTDBG_ICR_DSRMIC           0x8
-#define BF_UARTDBG_ICR_DSRMIC(v)        (((v) << 3) & 0x8)
-#define BP_UARTDBG_ICR_DCDMIC           2
-#define BM_UARTDBG_ICR_DCDMIC           0x4
-#define BF_UARTDBG_ICR_DCDMIC(v)        (((v) << 2) & 0x4)
-#define BP_UARTDBG_ICR_CTSMIC           1
-#define BM_UARTDBG_ICR_CTSMIC           0x2
-#define BF_UARTDBG_ICR_CTSMIC(v)        (((v) << 1) & 0x2)
-#define BP_UARTDBG_ICR_RIMIC            0
-#define BM_UARTDBG_ICR_RIMIC            0x1
-#define BF_UARTDBG_ICR_RIMIC(v)         (((v) << 0) & 0x1)
-
-/**
- * Register: HW_UARTDBG_DMACR
- * Address: 0x48
- * SCT: no
-*/
-#define HW_UARTDBG_DMACR                (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x48))
-#define BP_UARTDBG_DMACR_UNAVAILABLE    16
-#define BM_UARTDBG_DMACR_UNAVAILABLE    0xffff0000
-#define BF_UARTDBG_DMACR_UNAVAILABLE(v) (((v) << 16) & 0xffff0000)
-#define BP_UARTDBG_DMACR_RESERVED       3
-#define BM_UARTDBG_DMACR_RESERVED       0xfff8
-#define BF_UARTDBG_DMACR_RESERVED(v)    (((v) << 3) & 0xfff8)
-#define BP_UARTDBG_DMACR_DMAONERR       2
-#define BM_UARTDBG_DMACR_DMAONERR       0x4
-#define BF_UARTDBG_DMACR_DMAONERR(v)    (((v) << 2) & 0x4)
-#define BP_UARTDBG_DMACR_TXDMAE         1
-#define BM_UARTDBG_DMACR_TXDMAE         0x2
-#define BF_UARTDBG_DMACR_TXDMAE(v)      (((v) << 1) & 0x2)
-#define BP_UARTDBG_DMACR_RXDMAE         0
-#define BM_UARTDBG_DMACR_RXDMAE         0x1
-#define BF_UARTDBG_DMACR_RXDMAE(v)      (((v) << 0) & 0x1)
-
-#endif /* __HEADERGEN__STMP3600__UARTDBG__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-usbphy.h b/firmware/target/arm/imx233/regs/stmp3600/regs-usbphy.h
deleted file mode 100644
index db27fc81ae..0000000000
--- a/firmware/target/arm/imx233/regs/stmp3600/regs-usbphy.h
+++ /dev/null
@@ -1,405 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3600:2.3.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__STMP3600__USBPHY__H__
-#define __HEADERGEN__STMP3600__USBPHY__H__
-
-#define REGS_USBPHY_BASE (0x8007c000)
-
-#define REGS_USBPHY_VERSION "2.3.0"
-
-/**
- * Register: HW_USBPHY_PWD
- * Address: 0
- * SCT: yes
-*/
-#define HW_USBPHY_PWD               (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x0 + 0x0))
-#define HW_USBPHY_PWD_SET           (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x0 + 0x4))
-#define HW_USBPHY_PWD_CLR           (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x0 + 0x8))
-#define HW_USBPHY_PWD_TOG           (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x0 + 0xc))
-#define BP_USBPHY_PWD_RXPWDRX       20
-#define BM_USBPHY_PWD_RXPWDRX       0x100000
-#define BF_USBPHY_PWD_RXPWDRX(v)    (((v) << 20) & 0x100000)
-#define BP_USBPHY_PWD_RXPWDDIFF     19
-#define BM_USBPHY_PWD_RXPWDDIFF     0x80000
-#define BF_USBPHY_PWD_RXPWDDIFF(v)  (((v) << 19) & 0x80000)
-#define BP_USBPHY_PWD_RXPWD1PT1     18
-#define BM_USBPHY_PWD_RXPWD1PT1     0x40000
-#define BF_USBPHY_PWD_RXPWD1PT1(v)  (((v) << 18) & 0x40000)
-#define BP_USBPHY_PWD_RXPWDENV      17
-#define BM_USBPHY_PWD_RXPWDENV      0x20000
-#define BF_USBPHY_PWD_RXPWDENV(v)   (((v) << 17) & 0x20000)
-#define BP_USBPHY_PWD_TXPWDCOMP     14
-#define BM_USBPHY_PWD_TXPWDCOMP     0x4000
-#define BF_USBPHY_PWD_TXPWDCOMP(v)  (((v) << 14) & 0x4000)
-#define BP_USBPHY_PWD_TXPWDVBG      13
-#define BM_USBPHY_PWD_TXPWDVBG      0x2000
-#define BF_USBPHY_PWD_TXPWDVBG(v)   (((v) << 13) & 0x2000)
-#define BP_USBPHY_PWD_TXPWDV2I      12
-#define BM_USBPHY_PWD_TXPWDV2I      0x1000
-#define BF_USBPHY_PWD_TXPWDV2I(v)   (((v) << 12) & 0x1000)
-#define BP_USBPHY_PWD_TXPWDIBIAS    11
-#define BM_USBPHY_PWD_TXPWDIBIAS    0x800
-#define BF_USBPHY_PWD_TXPWDIBIAS(v) (((v) << 11) & 0x800)
-#define BP_USBPHY_PWD_TXPWDFS       10
-#define BM_USBPHY_PWD_TXPWDFS       0x400
-#define BF_USBPHY_PWD_TXPWDFS(v)    (((v) << 10) & 0x400)
-
-/**
- * Register: HW_USBPHY_TX
- * Address: 0x10
- * SCT: yes
-*/
-#define HW_USBPHY_TX                    (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x10 + 0x0))
-#define HW_USBPHY_TX_SET                (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x10 + 0x4))
-#define HW_USBPHY_TX_CLR                (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x10 + 0x8))
-#define HW_USBPHY_TX_TOG                (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x10 + 0xc))
-#define BP_USBPHY_TX_TXCMPOUT_STATUS    23
-#define BM_USBPHY_TX_TXCMPOUT_STATUS    0x800000
-#define BF_USBPHY_TX_TXCMPOUT_STATUS(v) (((v) << 23) & 0x800000)
-#define BP_USBPHY_TX_TXENCAL45DP        21
-#define BM_USBPHY_TX_TXENCAL45DP        0x200000
-#define BF_USBPHY_TX_TXENCAL45DP(v)     (((v) << 21) & 0x200000)
-#define BP_USBPHY_TX_TXCAL45DP          16
-#define BM_USBPHY_TX_TXCAL45DP          0x1f0000
-#define BF_USBPHY_TX_TXCAL45DP(v)       (((v) << 16) & 0x1f0000)
-#define BP_USBPHY_TX_TXENCAL45DN        13
-#define BM_USBPHY_TX_TXENCAL45DN        0x2000
-#define BF_USBPHY_TX_TXENCAL45DN(v)     (((v) << 13) & 0x2000)
-#define BP_USBPHY_TX_TXCAL45DN          8
-#define BM_USBPHY_TX_TXCAL45DN          0x1f00
-#define BF_USBPHY_TX_TXCAL45DN(v)       (((v) << 8) & 0x1f00)
-#define BP_USBPHY_TX_TXCALIBRATE        7
-#define BM_USBPHY_TX_TXCALIBRATE        0x80
-#define BF_USBPHY_TX_TXCALIBRATE(v)     (((v) << 7) & 0x80)
-
-/**
- * Register: HW_USBPHY_RX
- * Address: 0x20
- * SCT: yes
-*/
-#define HW_USBPHY_RX                (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x20 + 0x0))
-#define HW_USBPHY_RX_SET            (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x20 + 0x4))
-#define HW_USBPHY_RX_CLR            (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x20 + 0x8))
-#define HW_USBPHY_RX_TOG            (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x20 + 0xc))
-#define BP_USBPHY_RX_RXDBYPASS      22
-#define BM_USBPHY_RX_RXDBYPASS      0x400000
-#define BF_USBPHY_RX_RXDBYPASS(v)   (((v) << 22) & 0x400000)
-#define BP_USBPHY_RX_DISCONADJ      4
-#define BM_USBPHY_RX_DISCONADJ      0x30
-#define BF_USBPHY_RX_DISCONADJ(v)   (((v) << 4) & 0x30)
-#define BP_USBPHY_RX_ENVADJ         0
-#define BM_USBPHY_RX_ENVADJ         0x3
-#define BF_USBPHY_RX_ENVADJ(v)      (((v) << 0) & 0x3)
-
-/**
- * Register: HW_USBPHY_CTRL
- * Address: 0x30
- * SCT: yes
-*/
-#define HW_USBPHY_CTRL                          (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x30 + 0x0))
-#define HW_USBPHY_CTRL_SET                      (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x30 + 0x4))
-#define HW_USBPHY_CTRL_CLR                      (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x30 + 0x8))
-#define HW_USBPHY_CTRL_TOG                      (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x30 + 0xc))
-#define BP_USBPHY_CTRL_SFTRST                   31
-#define BM_USBPHY_CTRL_SFTRST                   0x80000000
-#define BF_USBPHY_CTRL_SFTRST(v)                (((v) << 31) & 0x80000000)
-#define BP_USBPHY_CTRL_CLKGATE                  30
-#define BM_USBPHY_CTRL_CLKGATE                  0x40000000
-#define BF_USBPHY_CTRL_CLKGATE(v)               (((v) << 30) & 0x40000000)
-#define BP_USBPHY_CTRL_UTMI_SUSPENDM            29
-#define BM_USBPHY_CTRL_UTMI_SUSPENDM            0x20000000
-#define BF_USBPHY_CTRL_UTMI_SUSPENDM(v)         (((v) << 29) & 0x20000000)
-#define BP_USBPHY_CTRL_RESUME_IRQ               10
-#define BM_USBPHY_CTRL_RESUME_IRQ               0x400
-#define BF_USBPHY_CTRL_RESUME_IRQ(v)            (((v) << 10) & 0x400)
-#define BP_USBPHY_CTRL_ENIRQRESUMEDETECT        9
-#define BM_USBPHY_CTRL_ENIRQRESUMEDETECT        0x200
-#define BF_USBPHY_CTRL_ENIRQRESUMEDETECT(v)     (((v) << 9) & 0x200)
-#define BP_USBPHY_CTRL_ENOTGIDDETECT            7
-#define BM_USBPHY_CTRL_ENOTGIDDETECT            0x80
-#define BF_USBPHY_CTRL_ENOTGIDDETECT(v)         (((v) << 7) & 0x80)
-#define BP_USBPHY_CTRL_ENDEVPLUGINDETECT        4
-#define BM_USBPHY_CTRL_ENDEVPLUGINDETECT        0x10
-#define BF_USBPHY_CTRL_ENDEVPLUGINDETECT(v)     (((v) << 4) & 0x10)
-#define BP_USBPHY_CTRL_HOSTDISCONDETECT_IRQ     3
-#define BM_USBPHY_CTRL_HOSTDISCONDETECT_IRQ     0x8
-#define BF_USBPHY_CTRL_HOSTDISCONDETECT_IRQ(v)  (((v) << 3) & 0x8)
-#define BP_USBPHY_CTRL_ENIRQHOSTDISCON          2
-#define BM_USBPHY_CTRL_ENIRQHOSTDISCON          0x4
-#define BF_USBPHY_CTRL_ENIRQHOSTDISCON(v)       (((v) << 2) & 0x4)
-#define BP_USBPHY_CTRL_ENHOSTDISCONDETECT       1
-#define BM_USBPHY_CTRL_ENHOSTDISCONDETECT       0x2
-#define BF_USBPHY_CTRL_ENHOSTDISCONDETECT(v)    (((v) << 1) & 0x2)
-#define BP_USBPHY_CTRL_ENHSPRECHARGEXMIT        0
-#define BM_USBPHY_CTRL_ENHSPRECHARGEXMIT        0x1
-#define BF_USBPHY_CTRL_ENHSPRECHARGEXMIT(v)     (((v) << 0) & 0x1)
-
-/**
- * Register: HW_USBPHY_STATUS
- * Address: 0x40
- * SCT: no
-*/
-#define HW_USBPHY_STATUS                            (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x40))
-#define BP_USBPHY_STATUS_RESUME_STATUS              10
-#define BM_USBPHY_STATUS_RESUME_STATUS              0x400
-#define BF_USBPHY_STATUS_RESUME_STATUS(v)           (((v) << 10) & 0x400)
-#define BP_USBPHY_STATUS_OTGID_STATUS               8
-#define BM_USBPHY_STATUS_OTGID_STATUS               0x100
-#define BF_USBPHY_STATUS_OTGID_STATUS(v)            (((v) << 8) & 0x100)
-#define BP_USBPHY_STATUS_DEVPLUGIN_STATUS           6
-#define BM_USBPHY_STATUS_DEVPLUGIN_STATUS           0x40
-#define BF_USBPHY_STATUS_DEVPLUGIN_STATUS(v)        (((v) << 6) & 0x40)
-#define BP_USBPHY_STATUS_HOSTDISCONDETECT_STATUS    3
-#define BM_USBPHY_STATUS_HOSTDISCONDETECT_STATUS    0x8
-#define BF_USBPHY_STATUS_HOSTDISCONDETECT_STATUS(v) (((v) << 3) & 0x8)
-
-/**
- * Register: HW_USBPHY_DEBUG
- * Address: 0x50
- * SCT: yes
-*/
-#define HW_USBPHY_DEBUG                         (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x50 + 0x0))
-#define HW_USBPHY_DEBUG_SET                     (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x50 + 0x4))
-#define HW_USBPHY_DEBUG_CLR                     (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x50 + 0x8))
-#define HW_USBPHY_DEBUG_TOG                     (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x50 + 0xc))
-#define BP_USBPHY_DEBUG_CLKGATE                 30
-#define BM_USBPHY_DEBUG_CLKGATE                 0x40000000
-#define BF_USBPHY_DEBUG_CLKGATE(v)              (((v) << 30) & 0x40000000)
-#define BP_USBPHY_DEBUG_SQUELCHRESETLENGTH      25
-#define BM_USBPHY_DEBUG_SQUELCHRESETLENGTH      0x1e000000
-#define BF_USBPHY_DEBUG_SQUELCHRESETLENGTH(v)   (((v) << 25) & 0x1e000000)
-#define BP_USBPHY_DEBUG_ENSQUELCHRESET          24
-#define BM_USBPHY_DEBUG_ENSQUELCHRESET          0x1000000
-#define BF_USBPHY_DEBUG_ENSQUELCHRESET(v)       (((v) << 24) & 0x1000000)
-#define BP_USBPHY_DEBUG_SQUELCHRESETCOUNT       16
-#define BM_USBPHY_DEBUG_SQUELCHRESETCOUNT       0x1f0000
-#define BF_USBPHY_DEBUG_SQUELCHRESETCOUNT(v)    (((v) << 16) & 0x1f0000)
-#define BP_USBPHY_DEBUG_ENTX2RXCOUNT            12
-#define BM_USBPHY_DEBUG_ENTX2RXCOUNT            0x1000
-#define BF_USBPHY_DEBUG_ENTX2RXCOUNT(v)         (((v) << 12) & 0x1000)
-#define BP_USBPHY_DEBUG_TX2RXCOUNT              8
-#define BM_USBPHY_DEBUG_TX2RXCOUNT              0xf00
-#define BF_USBPHY_DEBUG_TX2RXCOUNT(v)           (((v) << 8) & 0xf00)
-#define BP_USBPHY_DEBUG_ENHSTPULLDOWN           4
-#define BM_USBPHY_DEBUG_ENHSTPULLDOWN           0x30
-#define BF_USBPHY_DEBUG_ENHSTPULLDOWN(v)        (((v) << 4) & 0x30)
-#define BP_USBPHY_DEBUG_HSTPULLDOWN             2
-#define BM_USBPHY_DEBUG_HSTPULLDOWN             0xc
-#define BF_USBPHY_DEBUG_HSTPULLDOWN(v)          (((v) << 2) & 0xc)
-#define BP_USBPHY_DEBUG_DEBUG_INTERFACE_HOLD    1
-#define BM_USBPHY_DEBUG_DEBUG_INTERFACE_HOLD    0x2
-#define BF_USBPHY_DEBUG_DEBUG_INTERFACE_HOLD(v) (((v) << 1) & 0x2)
-#define BP_USBPHY_DEBUG_OTGIDPIOLOCK            0
-#define BM_USBPHY_DEBUG_OTGIDPIOLOCK            0x1
-#define BF_USBPHY_DEBUG_OTGIDPIOLOCK(v)         (((v) << 0) & 0x1)
-
-/**
- * Register: HW_USBPHY_DEBUG0_STATUS
- * Address: 0x60
- * SCT: no
-*/
-#define HW_USBPHY_DEBUG0_STATUS                             (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x60))
-#define BP_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT               26
-#define BM_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT               0xfc000000
-#define BF_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT(v)            (((v) << 26) & 0xfc000000)
-#define BP_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT     16
-#define BM_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT     0x3ff0000
-#define BF_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT(v)  (((v) << 16) & 0x3ff0000)
-#define BP_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT        0
-#define BM_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT        0xffff
-#define BF_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT(v)     (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_USBPHY_DEBUG1_STATUS
- * Address: 0x70
- * SCT: no
-*/
-#define HW_USBPHY_DEBUG1_STATUS                 (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x70))
-#define BP_USBPHY_DEBUG1_STATUS_UTMI_TX_DATA    16
-#define BM_USBPHY_DEBUG1_STATUS_UTMI_TX_DATA    0xffff0000
-#define BF_USBPHY_DEBUG1_STATUS_UTMI_TX_DATA(v) (((v) << 16) & 0xffff0000)
-#define BP_USBPHY_DEBUG1_STATUS_UTMI_RX_DATA    0
-#define BM_USBPHY_DEBUG1_STATUS_UTMI_RX_DATA    0xffff
-#define BF_USBPHY_DEBUG1_STATUS_UTMI_RX_DATA(v) (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_USBPHY_DEBUG2_STATUS
- * Address: 0x80
- * SCT: no
-*/
-#define HW_USBPHY_DEBUG2_STATUS                     (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x80))
-#define BP_USBPHY_DEBUG2_STATUS_UTMI_TXVALIDH       22
-#define BM_USBPHY_DEBUG2_STATUS_UTMI_TXVALIDH       0x400000
-#define BF_USBPHY_DEBUG2_STATUS_UTMI_TXVALIDH(v)    (((v) << 22) & 0x400000)
-#define BP_USBPHY_DEBUG2_STATUS_UTMI_TXVALID        21
-#define BM_USBPHY_DEBUG2_STATUS_UTMI_TXVALID        0x200000
-#define BF_USBPHY_DEBUG2_STATUS_UTMI_TXVALID(v)     (((v) << 21) & 0x200000)
-#define BP_USBPHY_DEBUG2_STATUS_UTMI_TERMSELECT     20
-#define BM_USBPHY_DEBUG2_STATUS_UTMI_TERMSELECT     0x100000
-#define BF_USBPHY_DEBUG2_STATUS_UTMI_TERMSELECT(v)  (((v) << 20) & 0x100000)
-#define BP_USBPHY_DEBUG2_STATUS_UTMI_XCVRSELECT     18
-#define BM_USBPHY_DEBUG2_STATUS_UTMI_XCVRSELECT     0xc0000
-#define BF_USBPHY_DEBUG2_STATUS_UTMI_XCVRSELECT(v)  (((v) << 18) & 0xc0000)
-#define BP_USBPHY_DEBUG2_STATUS_UTMI_OPMODE         16
-#define BM_USBPHY_DEBUG2_STATUS_UTMI_OPMODE         0x30000
-#define BF_USBPHY_DEBUG2_STATUS_UTMI_OPMODE(v)      (((v) << 16) & 0x30000)
-#define BP_USBPHY_DEBUG2_STATUS_UTMI_LINESTATE      6
-#define BM_USBPHY_DEBUG2_STATUS_UTMI_LINESTATE      0xc0
-#define BF_USBPHY_DEBUG2_STATUS_UTMI_LINESTATE(v)   (((v) << 6) & 0xc0)
-#define BP_USBPHY_DEBUG2_STATUS_UTMI_SUSPENDM       5
-#define BM_USBPHY_DEBUG2_STATUS_UTMI_SUSPENDM       0x20
-#define BF_USBPHY_DEBUG2_STATUS_UTMI_SUSPENDM(v)    (((v) << 5) & 0x20)
-#define BP_USBPHY_DEBUG2_STATUS_UTMI_RXVALIDH       4
-#define BM_USBPHY_DEBUG2_STATUS_UTMI_RXVALIDH       0x10
-#define BF_USBPHY_DEBUG2_STATUS_UTMI_RXVALIDH(v)    (((v) << 4) & 0x10)
-#define BP_USBPHY_DEBUG2_STATUS_UTMI_RXVALID        3
-#define BM_USBPHY_DEBUG2_STATUS_UTMI_RXVALID        0x8
-#define BF_USBPHY_DEBUG2_STATUS_UTMI_RXVALID(v)     (((v) << 3) & 0x8)
-#define BP_USBPHY_DEBUG2_STATUS_UTMI_RXACTIVE       2
-#define BM_USBPHY_DEBUG2_STATUS_UTMI_RXACTIVE       0x4
-#define BF_USBPHY_DEBUG2_STATUS_UTMI_RXACTIVE(v)    (((v) << 2) & 0x4)
-#define BP_USBPHY_DEBUG2_STATUS_UTMI_RXERROR        1
-#define BM_USBPHY_DEBUG2_STATUS_UTMI_RXERROR        0x2
-#define BF_USBPHY_DEBUG2_STATUS_UTMI_RXERROR(v)     (((v) << 1) & 0x2)
-#define BP_USBPHY_DEBUG2_STATUS_UTMI_TXREADY        0
-#define BM_USBPHY_DEBUG2_STATUS_UTMI_TXREADY        0x1
-#define BF_USBPHY_DEBUG2_STATUS_UTMI_TXREADY(v)     (((v) << 0) & 0x1)
-
-/**
- * Register: HW_USBPHY_DEBUG3_STATUS
- * Address: 0x90
- * SCT: no
-*/
-#define HW_USBPHY_DEBUG3_STATUS                     (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x90))
-#define BP_USBPHY_DEBUG3_STATUS_B_CNT_FSM           28
-#define BM_USBPHY_DEBUG3_STATUS_B_CNT_FSM           0x70000000
-#define BF_USBPHY_DEBUG3_STATUS_B_CNT_FSM(v)        (((v) << 28) & 0x70000000)
-#define BP_USBPHY_DEBUG3_STATUS_SQ_UNLOCK_FSM       23
-#define BM_USBPHY_DEBUG3_STATUS_SQ_UNLOCK_FSM       0x3800000
-#define BF_USBPHY_DEBUG3_STATUS_SQ_UNLOCK_FSM(v)    (((v) << 23) & 0x3800000)
-#define BP_USBPHY_DEBUG3_STATUS_BIT_CNT             12
-#define BM_USBPHY_DEBUG3_STATUS_BIT_CNT             0x3ff000
-#define BF_USBPHY_DEBUG3_STATUS_BIT_CNT(v)          (((v) << 12) & 0x3ff000)
-#define BP_USBPHY_DEBUG3_STATUS_MAIN_HS_RX_FSM      8
-#define BM_USBPHY_DEBUG3_STATUS_MAIN_HS_RX_FSM      0xf00
-#define BF_USBPHY_DEBUG3_STATUS_MAIN_HS_RX_FSM(v)   (((v) << 8) & 0xf00)
-#define BP_USBPHY_DEBUG3_STATUS_UNSTUFF_BIT_CNT     0
-#define BM_USBPHY_DEBUG3_STATUS_UNSTUFF_BIT_CNT     0xff
-#define BF_USBPHY_DEBUG3_STATUS_UNSTUFF_BIT_CNT(v)  (((v) << 0) & 0xff)
-
-/**
- * Register: HW_USBPHY_DEBUG4_STATUS
- * Address: 0xa0
- * SCT: no
-*/
-#define HW_USBPHY_DEBUG4_STATUS             (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0xa0))
-#define BP_USBPHY_DEBUG4_STATUS_BYTE_FSM    16
-#define BM_USBPHY_DEBUG4_STATUS_BYTE_FSM    0x1fff0000
-#define BF_USBPHY_DEBUG4_STATUS_BYTE_FSM(v) (((v) << 16) & 0x1fff0000)
-#define BP_USBPHY_DEBUG4_STATUS_SND_FSM     0
-#define BM_USBPHY_DEBUG4_STATUS_SND_FSM     0x3fff
-#define BF_USBPHY_DEBUG4_STATUS_SND_FSM(v)  (((v) << 0) & 0x3fff)
-
-/**
- * Register: HW_USBPHY_DEBUG5_STATUS
- * Address: 0xb0
- * SCT: no
-*/
-#define HW_USBPHY_DEBUG5_STATUS                     (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0xb0))
-#define BP_USBPHY_DEBUG5_STATUS_MAIN_FSM            24
-#define BM_USBPHY_DEBUG5_STATUS_MAIN_FSM            0xf000000
-#define BF_USBPHY_DEBUG5_STATUS_MAIN_FSM(v)         (((v) << 24) & 0xf000000)
-#define BP_USBPHY_DEBUG5_STATUS_SYNC_FSM            16
-#define BM_USBPHY_DEBUG5_STATUS_SYNC_FSM            0x3f0000
-#define BF_USBPHY_DEBUG5_STATUS_SYNC_FSM(v)         (((v) << 16) & 0x3f0000)
-#define BP_USBPHY_DEBUG5_STATUS_PRECHARGE_FSM       12
-#define BM_USBPHY_DEBUG5_STATUS_PRECHARGE_FSM       0x7000
-#define BF_USBPHY_DEBUG5_STATUS_PRECHARGE_FSM(v)    (((v) << 12) & 0x7000)
-#define BP_USBPHY_DEBUG5_STATUS_SHIFT_FSM           8
-#define BM_USBPHY_DEBUG5_STATUS_SHIFT_FSM           0x700
-#define BF_USBPHY_DEBUG5_STATUS_SHIFT_FSM(v)        (((v) << 8) & 0x700)
-#define BP_USBPHY_DEBUG5_STATUS_SOF_FSM             0
-#define BM_USBPHY_DEBUG5_STATUS_SOF_FSM             0x1f
-#define BF_USBPHY_DEBUG5_STATUS_SOF_FSM(v)          (((v) << 0) & 0x1f)
-
-/**
- * Register: HW_USBPHY_DEBUG6_STATUS
- * Address: 0xc0
- * SCT: no
-*/
-#define HW_USBPHY_DEBUG6_STATUS                     (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0xc0))
-#define BP_USBPHY_DEBUG6_STATUS_FIRST_EOP_FSM       8
-#define BM_USBPHY_DEBUG6_STATUS_FIRST_EOP_FSM       0x700
-#define BF_USBPHY_DEBUG6_STATUS_FIRST_EOP_FSM(v)    (((v) << 8) & 0x700)
-#define BP_USBPHY_DEBUG6_STATUS_EOP_FSM             0
-#define BM_USBPHY_DEBUG6_STATUS_EOP_FSM             0xff
-#define BF_USBPHY_DEBUG6_STATUS_EOP_FSM(v)          (((v) << 0) & 0xff)
-
-/**
- * Register: HW_USBPHY_DEBUG7_STATUS
- * Address: 0xd0
- * SCT: no
-*/
-#define HW_USBPHY_DEBUG7_STATUS                     (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0xd0))
-#define BP_USBPHY_DEBUG7_STATUS_FIRST_DATA_FSM      28
-#define BM_USBPHY_DEBUG7_STATUS_FIRST_DATA_FSM      0x30000000
-#define BF_USBPHY_DEBUG7_STATUS_FIRST_DATA_FSM(v)   (((v) << 28) & 0x30000000)
-#define BP_USBPHY_DEBUG7_STATUS_BIT_CNT             24
-#define BM_USBPHY_DEBUG7_STATUS_BIT_CNT             0xf000000
-#define BF_USBPHY_DEBUG7_STATUS_BIT_CNT(v)          (((v) << 24) & 0xf000000)
-#define BP_USBPHY_DEBUG7_STATUS_UNSTUFF_CNT         20
-#define BM_USBPHY_DEBUG7_STATUS_UNSTUFF_CNT         0x700000
-#define BF_USBPHY_DEBUG7_STATUS_UNSTUFF_CNT(v)      (((v) << 20) & 0x700000)
-#define BP_USBPHY_DEBUG7_STATUS_LD_FSM              16
-#define BM_USBPHY_DEBUG7_STATUS_LD_FSM              0x30000
-#define BF_USBPHY_DEBUG7_STATUS_LD_FSM(v)           (((v) << 16) & 0x30000)
-#define BP_USBPHY_DEBUG7_STATUS_FIFO_FSM            8
-#define BM_USBPHY_DEBUG7_STATUS_FIFO_FSM            0x3f00
-#define BF_USBPHY_DEBUG7_STATUS_FIFO_FSM(v)         (((v) << 8) & 0x3f00)
-#define BP_USBPHY_DEBUG7_STATUS_MAIN_FSM            4
-#define BM_USBPHY_DEBUG7_STATUS_MAIN_FSM            0xf0
-#define BF_USBPHY_DEBUG7_STATUS_MAIN_FSM(v)         (((v) << 4) & 0xf0)
-#define BP_USBPHY_DEBUG7_STATUS_EOP_FSM             0
-#define BM_USBPHY_DEBUG7_STATUS_EOP_FSM             0xf
-#define BF_USBPHY_DEBUG7_STATUS_EOP_FSM(v)          (((v) << 0) & 0xf)
-
-/**
- * Register: HW_USBPHY_DEBUG8_STATUS
- * Address: 0xe0
- * SCT: no
-*/
-#define HW_USBPHY_DEBUG8_STATUS                     (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0xe0))
-#define BP_USBPHY_DEBUG8_STATUS_RX_SIE_FSM          28
-#define BM_USBPHY_DEBUG8_STATUS_RX_SIE_FSM          0xf0000000
-#define BF_USBPHY_DEBUG8_STATUS_RX_SIE_FSM(v)       (((v) << 28) & 0xf0000000)
-#define BP_USBPHY_DEBUG8_STATUS_TX_SIE_FSM          24
-#define BM_USBPHY_DEBUG8_STATUS_TX_SIE_FSM          0xf000000
-#define BF_USBPHY_DEBUG8_STATUS_TX_SIE_FSM(v)       (((v) << 24) & 0xf000000)
-#define BP_USBPHY_DEBUG8_STATUS_SHIFT_FSM           8
-#define BM_USBPHY_DEBUG8_STATUS_SHIFT_FSM           0x300
-#define BF_USBPHY_DEBUG8_STATUS_SHIFT_FSM(v)        (((v) << 8) & 0x300)
-#define BP_USBPHY_DEBUG8_STATUS_FS_TX_MAIN_FSM      0
-#define BM_USBPHY_DEBUG8_STATUS_FS_TX_MAIN_FSM      0x7f
-#define BF_USBPHY_DEBUG8_STATUS_FS_TX_MAIN_FSM(v)   (((v) << 0) & 0x7f)
-
-#endif /* __HEADERGEN__STMP3600__USBPHY__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3600/rtc.h b/firmware/target/arm/imx233/regs/stmp3600/rtc.h
new file mode 100644
index 0000000000..a27e15c896
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3600/rtc.h
@@ -0,0 +1,537 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * stmp3600 version: 2.4.0
+ * stmp3600 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_STMP3600_RTC_H__
+#define __HEADERGEN_STMP3600_RTC_H__
+
+#define HW_RTC_CTRL                                 HW(RTC_CTRL)
+#define HWA_RTC_CTRL                                (0x8005c000 + 0x0)
+#define HWT_RTC_CTRL                                HWIO_32_RW
+#define HWN_RTC_CTRL                                RTC_CTRL
+#define HWI_RTC_CTRL                                
+#define HW_RTC_CTRL_SET                             HW(RTC_CTRL_SET)
+#define HWA_RTC_CTRL_SET                            (HWA_RTC_CTRL + 0x4)
+#define HWT_RTC_CTRL_SET                            HWIO_32_WO
+#define HWN_RTC_CTRL_SET                            RTC_CTRL
+#define HWI_RTC_CTRL_SET                            
+#define HW_RTC_CTRL_CLR                             HW(RTC_CTRL_CLR)
+#define HWA_RTC_CTRL_CLR                            (HWA_RTC_CTRL + 0x8)
+#define HWT_RTC_CTRL_CLR                            HWIO_32_WO
+#define HWN_RTC_CTRL_CLR                            RTC_CTRL
+#define HWI_RTC_CTRL_CLR                            
+#define HW_RTC_CTRL_TOG                             HW(RTC_CTRL_TOG)
+#define HWA_RTC_CTRL_TOG                            (HWA_RTC_CTRL + 0xc)
+#define HWT_RTC_CTRL_TOG                            HWIO_32_WO
+#define HWN_RTC_CTRL_TOG                            RTC_CTRL
+#define HWI_RTC_CTRL_TOG                            
+#define BP_RTC_CTRL_SFTRST                          31
+#define BM_RTC_CTRL_SFTRST                          0x80000000
+#define BF_RTC_CTRL_SFTRST(v)                       (((v) & 0x1) << 31)
+#define BFM_RTC_CTRL_SFTRST(v)                      BM_RTC_CTRL_SFTRST
+#define BF_RTC_CTRL_SFTRST_V(e)                     BF_RTC_CTRL_SFTRST(BV_RTC_CTRL_SFTRST__##e)
+#define BFM_RTC_CTRL_SFTRST_V(v)                    BM_RTC_CTRL_SFTRST
+#define BP_RTC_CTRL_CLKGATE                         30
+#define BM_RTC_CTRL_CLKGATE                         0x40000000
+#define BF_RTC_CTRL_CLKGATE(v)                      (((v) & 0x1) << 30)
+#define BFM_RTC_CTRL_CLKGATE(v)                     BM_RTC_CTRL_CLKGATE
+#define BF_RTC_CTRL_CLKGATE_V(e)                    BF_RTC_CTRL_CLKGATE(BV_RTC_CTRL_CLKGATE__##e)
+#define BFM_RTC_CTRL_CLKGATE_V(v)                   BM_RTC_CTRL_CLKGATE
+#define BP_RTC_CTRL_CLKDIV                          24
+#define BM_RTC_CTRL_CLKDIV                          0xf000000
+#define BF_RTC_CTRL_CLKDIV(v)                       (((v) & 0xf) << 24)
+#define BFM_RTC_CTRL_CLKDIV(v)                      BM_RTC_CTRL_CLKDIV
+#define BF_RTC_CTRL_CLKDIV_V(e)                     BF_RTC_CTRL_CLKDIV(BV_RTC_CTRL_CLKDIV__##e)
+#define BFM_RTC_CTRL_CLKDIV_V(v)                    BM_RTC_CTRL_CLKDIV
+#define BP_RTC_CTRL_SUPPRESS_COPY2ANALOG            6
+#define BM_RTC_CTRL_SUPPRESS_COPY2ANALOG            0x40
+#define BV_RTC_CTRL_SUPPRESS_COPY2ANALOG__NORMAL    0x0
+#define BV_RTC_CTRL_SUPPRESS_COPY2ANALOG__NO_COPY   0x1
+#define BF_RTC_CTRL_SUPPRESS_COPY2ANALOG(v)         (((v) & 0x1) << 6)
+#define BFM_RTC_CTRL_SUPPRESS_COPY2ANALOG(v)        BM_RTC_CTRL_SUPPRESS_COPY2ANALOG
+#define BF_RTC_CTRL_SUPPRESS_COPY2ANALOG_V(e)       BF_RTC_CTRL_SUPPRESS_COPY2ANALOG(BV_RTC_CTRL_SUPPRESS_COPY2ANALOG__##e)
+#define BFM_RTC_CTRL_SUPPRESS_COPY2ANALOG_V(v)      BM_RTC_CTRL_SUPPRESS_COPY2ANALOG
+#define BP_RTC_CTRL_FORCE_UPDATE                    5
+#define BM_RTC_CTRL_FORCE_UPDATE                    0x20
+#define BV_RTC_CTRL_FORCE_UPDATE__NORMAL            0x0
+#define BV_RTC_CTRL_FORCE_UPDATE__FORCE_COPY        0x1
+#define BF_RTC_CTRL_FORCE_UPDATE(v)                 (((v) & 0x1) << 5)
+#define BFM_RTC_CTRL_FORCE_UPDATE(v)                BM_RTC_CTRL_FORCE_UPDATE
+#define BF_RTC_CTRL_FORCE_UPDATE_V(e)               BF_RTC_CTRL_FORCE_UPDATE(BV_RTC_CTRL_FORCE_UPDATE__##e)
+#define BFM_RTC_CTRL_FORCE_UPDATE_V(v)              BM_RTC_CTRL_FORCE_UPDATE
+#define BP_RTC_CTRL_WATCHDOGEN                      4
+#define BM_RTC_CTRL_WATCHDOGEN                      0x10
+#define BF_RTC_CTRL_WATCHDOGEN(v)                   (((v) & 0x1) << 4)
+#define BFM_RTC_CTRL_WATCHDOGEN(v)                  BM_RTC_CTRL_WATCHDOGEN
+#define BF_RTC_CTRL_WATCHDOGEN_V(e)                 BF_RTC_CTRL_WATCHDOGEN(BV_RTC_CTRL_WATCHDOGEN__##e)
+#define BFM_RTC_CTRL_WATCHDOGEN_V(v)                BM_RTC_CTRL_WATCHDOGEN
+#define BP_RTC_CTRL_ONEMSEC_IRQ                     3
+#define BM_RTC_CTRL_ONEMSEC_IRQ                     0x8
+#define BF_RTC_CTRL_ONEMSEC_IRQ(v)                  (((v) & 0x1) << 3)
+#define BFM_RTC_CTRL_ONEMSEC_IRQ(v)                 BM_RTC_CTRL_ONEMSEC_IRQ
+#define BF_RTC_CTRL_ONEMSEC_IRQ_V(e)                BF_RTC_CTRL_ONEMSEC_IRQ(BV_RTC_CTRL_ONEMSEC_IRQ__##e)
+#define BFM_RTC_CTRL_ONEMSEC_IRQ_V(v)               BM_RTC_CTRL_ONEMSEC_IRQ
+#define BP_RTC_CTRL_ALARM_IRQ                       2
+#define BM_RTC_CTRL_ALARM_IRQ                       0x4
+#define BF_RTC_CTRL_ALARM_IRQ(v)                    (((v) & 0x1) << 2)
+#define BFM_RTC_CTRL_ALARM_IRQ(v)                   BM_RTC_CTRL_ALARM_IRQ
+#define BF_RTC_CTRL_ALARM_IRQ_V(e)                  BF_RTC_CTRL_ALARM_IRQ(BV_RTC_CTRL_ALARM_IRQ__##e)
+#define BFM_RTC_CTRL_ALARM_IRQ_V(v)                 BM_RTC_CTRL_ALARM_IRQ
+#define BP_RTC_CTRL_ONEMSEC_IRQ_EN                  1
+#define BM_RTC_CTRL_ONEMSEC_IRQ_EN                  0x2
+#define BF_RTC_CTRL_ONEMSEC_IRQ_EN(v)               (((v) & 0x1) << 1)
+#define BFM_RTC_CTRL_ONEMSEC_IRQ_EN(v)              BM_RTC_CTRL_ONEMSEC_IRQ_EN
+#define BF_RTC_CTRL_ONEMSEC_IRQ_EN_V(e)             BF_RTC_CTRL_ONEMSEC_IRQ_EN(BV_RTC_CTRL_ONEMSEC_IRQ_EN__##e)
+#define BFM_RTC_CTRL_ONEMSEC_IRQ_EN_V(v)            BM_RTC_CTRL_ONEMSEC_IRQ_EN
+#define BP_RTC_CTRL_ALARM_IRQ_EN                    0
+#define BM_RTC_CTRL_ALARM_IRQ_EN                    0x1
+#define BF_RTC_CTRL_ALARM_IRQ_EN(v)                 (((v) & 0x1) << 0)
+#define BFM_RTC_CTRL_ALARM_IRQ_EN(v)                BM_RTC_CTRL_ALARM_IRQ_EN
+#define BF_RTC_CTRL_ALARM_IRQ_EN_V(e)               BF_RTC_CTRL_ALARM_IRQ_EN(BV_RTC_CTRL_ALARM_IRQ_EN__##e)
+#define BFM_RTC_CTRL_ALARM_IRQ_EN_V(v)              BM_RTC_CTRL_ALARM_IRQ_EN
+
+#define HW_RTC_STAT                         HW(RTC_STAT)
+#define HWA_RTC_STAT                        (0x8005c000 + 0x10)
+#define HWT_RTC_STAT                        HWIO_32_RW
+#define HWN_RTC_STAT                        RTC_STAT
+#define HWI_RTC_STAT                        
+#define BP_RTC_STAT_RTC_PRESENT             31
+#define BM_RTC_STAT_RTC_PRESENT             0x80000000
+#define BF_RTC_STAT_RTC_PRESENT(v)          (((v) & 0x1) << 31)
+#define BFM_RTC_STAT_RTC_PRESENT(v)         BM_RTC_STAT_RTC_PRESENT
+#define BF_RTC_STAT_RTC_PRESENT_V(e)        BF_RTC_STAT_RTC_PRESENT(BV_RTC_STAT_RTC_PRESENT__##e)
+#define BFM_RTC_STAT_RTC_PRESENT_V(v)       BM_RTC_STAT_RTC_PRESENT
+#define BP_RTC_STAT_ALARM_PRESENT           30
+#define BM_RTC_STAT_ALARM_PRESENT           0x40000000
+#define BF_RTC_STAT_ALARM_PRESENT(v)        (((v) & 0x1) << 30)
+#define BFM_RTC_STAT_ALARM_PRESENT(v)       BM_RTC_STAT_ALARM_PRESENT
+#define BF_RTC_STAT_ALARM_PRESENT_V(e)      BF_RTC_STAT_ALARM_PRESENT(BV_RTC_STAT_ALARM_PRESENT__##e)
+#define BFM_RTC_STAT_ALARM_PRESENT_V(v)     BM_RTC_STAT_ALARM_PRESENT
+#define BP_RTC_STAT_WATCHDOG_PRESENT        29
+#define BM_RTC_STAT_WATCHDOG_PRESENT        0x20000000
+#define BF_RTC_STAT_WATCHDOG_PRESENT(v)     (((v) & 0x1) << 29)
+#define BFM_RTC_STAT_WATCHDOG_PRESENT(v)    BM_RTC_STAT_WATCHDOG_PRESENT
+#define BF_RTC_STAT_WATCHDOG_PRESENT_V(e)   BF_RTC_STAT_WATCHDOG_PRESENT(BV_RTC_STAT_WATCHDOG_PRESENT__##e)
+#define BFM_RTC_STAT_WATCHDOG_PRESENT_V(v)  BM_RTC_STAT_WATCHDOG_PRESENT
+#define BP_RTC_STAT_XTAL32768_PRESENT       28
+#define BM_RTC_STAT_XTAL32768_PRESENT       0x10000000
+#define BF_RTC_STAT_XTAL32768_PRESENT(v)    (((v) & 0x1) << 28)
+#define BFM_RTC_STAT_XTAL32768_PRESENT(v)   BM_RTC_STAT_XTAL32768_PRESENT
+#define BF_RTC_STAT_XTAL32768_PRESENT_V(e)  BF_RTC_STAT_XTAL32768_PRESENT(BV_RTC_STAT_XTAL32768_PRESENT__##e)
+#define BFM_RTC_STAT_XTAL32768_PRESENT_V(v) BM_RTC_STAT_XTAL32768_PRESENT
+#define BP_RTC_STAT_STALE_REGS              16
+#define BM_RTC_STAT_STALE_REGS              0x3f0000
+#define BF_RTC_STAT_STALE_REGS(v)           (((v) & 0x3f) << 16)
+#define BFM_RTC_STAT_STALE_REGS(v)          BM_RTC_STAT_STALE_REGS
+#define BF_RTC_STAT_STALE_REGS_V(e)         BF_RTC_STAT_STALE_REGS(BV_RTC_STAT_STALE_REGS__##e)
+#define BFM_RTC_STAT_STALE_REGS_V(v)        BM_RTC_STAT_STALE_REGS
+#define BP_RTC_STAT_NEW_REGS                8
+#define BM_RTC_STAT_NEW_REGS                0x3f00
+#define BF_RTC_STAT_NEW_REGS(v)             (((v) & 0x3f) << 8)
+#define BFM_RTC_STAT_NEW_REGS(v)            BM_RTC_STAT_NEW_REGS
+#define BF_RTC_STAT_NEW_REGS_V(e)           BF_RTC_STAT_NEW_REGS(BV_RTC_STAT_NEW_REGS__##e)
+#define BFM_RTC_STAT_NEW_REGS_V(v)          BM_RTC_STAT_NEW_REGS
+#define BP_RTC_STAT_FUSE_UNLOCK             1
+#define BM_RTC_STAT_FUSE_UNLOCK             0x2
+#define BF_RTC_STAT_FUSE_UNLOCK(v)          (((v) & 0x1) << 1)
+#define BFM_RTC_STAT_FUSE_UNLOCK(v)         BM_RTC_STAT_FUSE_UNLOCK
+#define BF_RTC_STAT_FUSE_UNLOCK_V(e)        BF_RTC_STAT_FUSE_UNLOCK(BV_RTC_STAT_FUSE_UNLOCK__##e)
+#define BFM_RTC_STAT_FUSE_UNLOCK_V(v)       BM_RTC_STAT_FUSE_UNLOCK
+#define BP_RTC_STAT_FUSE_DONE               0
+#define BM_RTC_STAT_FUSE_DONE               0x1
+#define BF_RTC_STAT_FUSE_DONE(v)            (((v) & 0x1) << 0)
+#define BFM_RTC_STAT_FUSE_DONE(v)           BM_RTC_STAT_FUSE_DONE
+#define BF_RTC_STAT_FUSE_DONE_V(e)          BF_RTC_STAT_FUSE_DONE(BV_RTC_STAT_FUSE_DONE__##e)
+#define BFM_RTC_STAT_FUSE_DONE_V(v)         BM_RTC_STAT_FUSE_DONE
+
+#define HW_RTC_MILLISECONDS             HW(RTC_MILLISECONDS)
+#define HWA_RTC_MILLISECONDS            (0x8005c000 + 0x20)
+#define HWT_RTC_MILLISECONDS            HWIO_32_RW
+#define HWN_RTC_MILLISECONDS            RTC_MILLISECONDS
+#define HWI_RTC_MILLISECONDS            
+#define HW_RTC_MILLISECONDS_SET         HW(RTC_MILLISECONDS_SET)
+#define HWA_RTC_MILLISECONDS_SET        (HWA_RTC_MILLISECONDS + 0x4)
+#define HWT_RTC_MILLISECONDS_SET        HWIO_32_WO
+#define HWN_RTC_MILLISECONDS_SET        RTC_MILLISECONDS
+#define HWI_RTC_MILLISECONDS_SET        
+#define HW_RTC_MILLISECONDS_CLR         HW(RTC_MILLISECONDS_CLR)
+#define HWA_RTC_MILLISECONDS_CLR        (HWA_RTC_MILLISECONDS + 0x8)
+#define HWT_RTC_MILLISECONDS_CLR        HWIO_32_WO
+#define HWN_RTC_MILLISECONDS_CLR        RTC_MILLISECONDS
+#define HWI_RTC_MILLISECONDS_CLR        
+#define HW_RTC_MILLISECONDS_TOG         HW(RTC_MILLISECONDS_TOG)
+#define HWA_RTC_MILLISECONDS_TOG        (HWA_RTC_MILLISECONDS + 0xc)
+#define HWT_RTC_MILLISECONDS_TOG        HWIO_32_WO
+#define HWN_RTC_MILLISECONDS_TOG        RTC_MILLISECONDS
+#define HWI_RTC_MILLISECONDS_TOG        
+#define BP_RTC_MILLISECONDS_COUNT       0
+#define BM_RTC_MILLISECONDS_COUNT       0xffffffff
+#define BF_RTC_MILLISECONDS_COUNT(v)    (((v) & 0xffffffff) << 0)
+#define BFM_RTC_MILLISECONDS_COUNT(v)   BM_RTC_MILLISECONDS_COUNT
+#define BF_RTC_MILLISECONDS_COUNT_V(e)  BF_RTC_MILLISECONDS_COUNT(BV_RTC_MILLISECONDS_COUNT__##e)
+#define BFM_RTC_MILLISECONDS_COUNT_V(v) BM_RTC_MILLISECONDS_COUNT
+
+#define HW_RTC_SECONDS              HW(RTC_SECONDS)
+#define HWA_RTC_SECONDS             (0x8005c000 + 0x30)
+#define HWT_RTC_SECONDS             HWIO_32_RW
+#define HWN_RTC_SECONDS             RTC_SECONDS
+#define HWI_RTC_SECONDS             
+#define HW_RTC_SECONDS_SET          HW(RTC_SECONDS_SET)
+#define HWA_RTC_SECONDS_SET         (HWA_RTC_SECONDS + 0x4)
+#define HWT_RTC_SECONDS_SET         HWIO_32_WO
+#define HWN_RTC_SECONDS_SET         RTC_SECONDS
+#define HWI_RTC_SECONDS_SET         
+#define HW_RTC_SECONDS_CLR          HW(RTC_SECONDS_CLR)
+#define HWA_RTC_SECONDS_CLR         (HWA_RTC_SECONDS + 0x8)
+#define HWT_RTC_SECONDS_CLR         HWIO_32_WO
+#define HWN_RTC_SECONDS_CLR         RTC_SECONDS
+#define HWI_RTC_SECONDS_CLR         
+#define HW_RTC_SECONDS_TOG          HW(RTC_SECONDS_TOG)
+#define HWA_RTC_SECONDS_TOG         (HWA_RTC_SECONDS + 0xc)
+#define HWT_RTC_SECONDS_TOG         HWIO_32_WO
+#define HWN_RTC_SECONDS_TOG         RTC_SECONDS
+#define HWI_RTC_SECONDS_TOG         
+#define BP_RTC_SECONDS_COUNT        0
+#define BM_RTC_SECONDS_COUNT        0xffffffff
+#define BF_RTC_SECONDS_COUNT(v)     (((v) & 0xffffffff) << 0)
+#define BFM_RTC_SECONDS_COUNT(v)    BM_RTC_SECONDS_COUNT
+#define BF_RTC_SECONDS_COUNT_V(e)   BF_RTC_SECONDS_COUNT(BV_RTC_SECONDS_COUNT__##e)
+#define BFM_RTC_SECONDS_COUNT_V(v)  BM_RTC_SECONDS_COUNT
+
+#define HW_RTC_ALARM                HW(RTC_ALARM)
+#define HWA_RTC_ALARM               (0x8005c000 + 0x40)
+#define HWT_RTC_ALARM               HWIO_32_RW
+#define HWN_RTC_ALARM               RTC_ALARM
+#define HWI_RTC_ALARM               
+#define HW_RTC_ALARM_SET            HW(RTC_ALARM_SET)
+#define HWA_RTC_ALARM_SET           (HWA_RTC_ALARM + 0x4)
+#define HWT_RTC_ALARM_SET           HWIO_32_WO
+#define HWN_RTC_ALARM_SET           RTC_ALARM
+#define HWI_RTC_ALARM_SET           
+#define HW_RTC_ALARM_CLR            HW(RTC_ALARM_CLR)
+#define HWA_RTC_ALARM_CLR           (HWA_RTC_ALARM + 0x8)
+#define HWT_RTC_ALARM_CLR           HWIO_32_WO
+#define HWN_RTC_ALARM_CLR           RTC_ALARM
+#define HWI_RTC_ALARM_CLR           
+#define HW_RTC_ALARM_TOG            HW(RTC_ALARM_TOG)
+#define HWA_RTC_ALARM_TOG           (HWA_RTC_ALARM + 0xc)
+#define HWT_RTC_ALARM_TOG           HWIO_32_WO
+#define HWN_RTC_ALARM_TOG           RTC_ALARM
+#define HWI_RTC_ALARM_TOG           
+#define BP_RTC_ALARM_VALUE          0
+#define BM_RTC_ALARM_VALUE          0xffffffff
+#define BF_RTC_ALARM_VALUE(v)       (((v) & 0xffffffff) << 0)
+#define BFM_RTC_ALARM_VALUE(v)      BM_RTC_ALARM_VALUE
+#define BF_RTC_ALARM_VALUE_V(e)     BF_RTC_ALARM_VALUE(BV_RTC_ALARM_VALUE__##e)
+#define BFM_RTC_ALARM_VALUE_V(v)    BM_RTC_ALARM_VALUE
+
+#define HW_RTC_WATCHDOG             HW(RTC_WATCHDOG)
+#define HWA_RTC_WATCHDOG            (0x8005c000 + 0x50)
+#define HWT_RTC_WATCHDOG            HWIO_32_RW
+#define HWN_RTC_WATCHDOG            RTC_WATCHDOG
+#define HWI_RTC_WATCHDOG            
+#define HW_RTC_WATCHDOG_SET         HW(RTC_WATCHDOG_SET)
+#define HWA_RTC_WATCHDOG_SET        (HWA_RTC_WATCHDOG + 0x4)
+#define HWT_RTC_WATCHDOG_SET        HWIO_32_WO
+#define HWN_RTC_WATCHDOG_SET        RTC_WATCHDOG
+#define HWI_RTC_WATCHDOG_SET        
+#define HW_RTC_WATCHDOG_CLR         HW(RTC_WATCHDOG_CLR)
+#define HWA_RTC_WATCHDOG_CLR        (HWA_RTC_WATCHDOG + 0x8)
+#define HWT_RTC_WATCHDOG_CLR        HWIO_32_WO
+#define HWN_RTC_WATCHDOG_CLR        RTC_WATCHDOG
+#define HWI_RTC_WATCHDOG_CLR        
+#define HW_RTC_WATCHDOG_TOG         HW(RTC_WATCHDOG_TOG)
+#define HWA_RTC_WATCHDOG_TOG        (HWA_RTC_WATCHDOG + 0xc)
+#define HWT_RTC_WATCHDOG_TOG        HWIO_32_WO
+#define HWN_RTC_WATCHDOG_TOG        RTC_WATCHDOG
+#define HWI_RTC_WATCHDOG_TOG        
+#define BP_RTC_WATCHDOG_COUNT       0
+#define BM_RTC_WATCHDOG_COUNT       0xffffffff
+#define BF_RTC_WATCHDOG_COUNT(v)    (((v) & 0xffffffff) << 0)
+#define BFM_RTC_WATCHDOG_COUNT(v)   BM_RTC_WATCHDOG_COUNT
+#define BF_RTC_WATCHDOG_COUNT_V(e)  BF_RTC_WATCHDOG_COUNT(BV_RTC_WATCHDOG_COUNT__##e)
+#define BFM_RTC_WATCHDOG_COUNT_V(v) BM_RTC_WATCHDOG_COUNT
+
+#define HW_RTC_PERSISTENT0                                  HW(RTC_PERSISTENT0)
+#define HWA_RTC_PERSISTENT0                                 (0x8005c000 + 0x60)
+#define HWT_RTC_PERSISTENT0                                 HWIO_32_RW
+#define HWN_RTC_PERSISTENT0                                 RTC_PERSISTENT0
+#define HWI_RTC_PERSISTENT0                                 
+#define HW_RTC_PERSISTENT0_SET                              HW(RTC_PERSISTENT0_SET)
+#define HWA_RTC_PERSISTENT0_SET                             (HWA_RTC_PERSISTENT0 + 0x4)
+#define HWT_RTC_PERSISTENT0_SET                             HWIO_32_WO
+#define HWN_RTC_PERSISTENT0_SET                             RTC_PERSISTENT0
+#define HWI_RTC_PERSISTENT0_SET                             
+#define HW_RTC_PERSISTENT0_CLR                              HW(RTC_PERSISTENT0_CLR)
+#define HWA_RTC_PERSISTENT0_CLR                             (HWA_RTC_PERSISTENT0 + 0x8)
+#define HWT_RTC_PERSISTENT0_CLR                             HWIO_32_WO
+#define HWN_RTC_PERSISTENT0_CLR                             RTC_PERSISTENT0
+#define HWI_RTC_PERSISTENT0_CLR                             
+#define HW_RTC_PERSISTENT0_TOG                              HW(RTC_PERSISTENT0_TOG)
+#define HWA_RTC_PERSISTENT0_TOG                             (HWA_RTC_PERSISTENT0 + 0xc)
+#define HWT_RTC_PERSISTENT0_TOG                             HWIO_32_WO
+#define HWN_RTC_PERSISTENT0_TOG                             RTC_PERSISTENT0
+#define HWI_RTC_PERSISTENT0_TOG                             
+#define BP_RTC_PERSISTENT0_GENERAL                          16
+#define BM_RTC_PERSISTENT0_GENERAL                          0xffff0000
+#define BV_RTC_PERSISTENT0_GENERAL__SDRAM_BOOT              0x8000
+#define BV_RTC_PERSISTENT0_GENERAL__ENUMERATE_500MA_TWICE   0x4000
+#define BV_RTC_PERSISTENT0_GENERAL__USB_BOOT_PLAYER_MODE    0x2000
+#define BV_RTC_PERSISTENT0_GENERAL__SKIP_CHECKDISK          0x1000
+#define BV_RTC_PERSISTENT0_GENERAL__USB_LOW_POWER_MODE      0x800
+#define BV_RTC_PERSISTENT0_GENERAL__OTG_HNP_BIT             0x400
+#define BV_RTC_PERSISTENT0_GENERAL__OTG_ATL_ROLE_BIT        0x200
+#define BV_RTC_PERSISTENT0_GENERAL__SDRAM_CS_HI             0x100
+#define BV_RTC_PERSISTENT0_GENERAL__SDRAM_CS_LO             0x80
+#define BV_RTC_PERSISTENT0_GENERAL__SDRAM_NDX_3             0x40
+#define BV_RTC_PERSISTENT0_GENERAL__SDRAM_NDX_2             0x20
+#define BV_RTC_PERSISTENT0_GENERAL__SDRAM_NDX_1             0x10
+#define BV_RTC_PERSISTENT0_GENERAL__SDRAM_NDX_0             0x8
+#define BV_RTC_PERSISTENT0_GENERAL__ETM_ENABLE              0x4
+#define BF_RTC_PERSISTENT0_GENERAL(v)                       (((v) & 0xffff) << 16)
+#define BFM_RTC_PERSISTENT0_GENERAL(v)                      BM_RTC_PERSISTENT0_GENERAL
+#define BF_RTC_PERSISTENT0_GENERAL_V(e)                     BF_RTC_PERSISTENT0_GENERAL(BV_RTC_PERSISTENT0_GENERAL__##e)
+#define BFM_RTC_PERSISTENT0_GENERAL_V(v)                    BM_RTC_PERSISTENT0_GENERAL
+#define BP_RTC_PERSISTENT0_DCDC_CTRL                        6
+#define BM_RTC_PERSISTENT0_DCDC_CTRL                        0xffc0
+#define BV_RTC_PERSISTENT0_DCDC_CTRL__SD_PRESENT            0x200
+#define BV_RTC_PERSISTENT0_DCDC_CTRL__LOWBAT_3P0            0x100
+#define BV_RTC_PERSISTENT0_DCDC_CTRL__SELFBIAS_PWRUP        0x80
+#define BV_RTC_PERSISTENT0_DCDC_CTRL__AUTO_RESTART          0x40
+#define BV_RTC_PERSISTENT0_DCDC_CTRL__DETECT_LOWBAT         0x20
+#define BV_RTC_PERSISTENT0_DCDC_CTRL__DROP_BIAS1            0x10
+#define BV_RTC_PERSISTENT0_DCDC_CTRL__DROP_BIAS2            0x8
+#define BV_RTC_PERSISTENT0_DCDC_CTRL__SPARE                 0x4
+#define BV_RTC_PERSISTENT0_DCDC_CTRL__DISABLE_XTALSTOP      0x2
+#define BV_RTC_PERSISTENT0_DCDC_CTRL__SPARE2                0x1
+#define BF_RTC_PERSISTENT0_DCDC_CTRL(v)                     (((v) & 0x3ff) << 6)
+#define BFM_RTC_PERSISTENT0_DCDC_CTRL(v)                    BM_RTC_PERSISTENT0_DCDC_CTRL
+#define BF_RTC_PERSISTENT0_DCDC_CTRL_V(e)                   BF_RTC_PERSISTENT0_DCDC_CTRL(BV_RTC_PERSISTENT0_DCDC_CTRL__##e)
+#define BFM_RTC_PERSISTENT0_DCDC_CTRL_V(v)                  BM_RTC_PERSISTENT0_DCDC_CTRL
+#define BP_RTC_PERSISTENT0_XTAL32_PDOWN                     5
+#define BM_RTC_PERSISTENT0_XTAL32_PDOWN                     0x20
+#define BF_RTC_PERSISTENT0_XTAL32_PDOWN(v)                  (((v) & 0x1) << 5)
+#define BFM_RTC_PERSISTENT0_XTAL32_PDOWN(v)                 BM_RTC_PERSISTENT0_XTAL32_PDOWN
+#define BF_RTC_PERSISTENT0_XTAL32_PDOWN_V(e)                BF_RTC_PERSISTENT0_XTAL32_PDOWN(BV_RTC_PERSISTENT0_XTAL32_PDOWN__##e)
+#define BFM_RTC_PERSISTENT0_XTAL32_PDOWN_V(v)               BM_RTC_PERSISTENT0_XTAL32_PDOWN
+#define BP_RTC_PERSISTENT0_XTAL24_PDOWN                     4
+#define BM_RTC_PERSISTENT0_XTAL24_PDOWN                     0x10
+#define BF_RTC_PERSISTENT0_XTAL24_PDOWN(v)                  (((v) & 0x1) << 4)
+#define BFM_RTC_PERSISTENT0_XTAL24_PDOWN(v)                 BM_RTC_PERSISTENT0_XTAL24_PDOWN
+#define BF_RTC_PERSISTENT0_XTAL24_PDOWN_V(e)                BF_RTC_PERSISTENT0_XTAL24_PDOWN(BV_RTC_PERSISTENT0_XTAL24_PDOWN__##e)
+#define BFM_RTC_PERSISTENT0_XTAL24_PDOWN_V(v)               BM_RTC_PERSISTENT0_XTAL24_PDOWN
+#define BP_RTC_PERSISTENT0_ALARM_WAKE_EN                    3
+#define BM_RTC_PERSISTENT0_ALARM_WAKE_EN                    0x8
+#define BF_RTC_PERSISTENT0_ALARM_WAKE_EN(v)                 (((v) & 0x1) << 3)
+#define BFM_RTC_PERSISTENT0_ALARM_WAKE_EN(v)                BM_RTC_PERSISTENT0_ALARM_WAKE_EN
+#define BF_RTC_PERSISTENT0_ALARM_WAKE_EN_V(e)               BF_RTC_PERSISTENT0_ALARM_WAKE_EN(BV_RTC_PERSISTENT0_ALARM_WAKE_EN__##e)
+#define BFM_RTC_PERSISTENT0_ALARM_WAKE_EN_V(v)              BM_RTC_PERSISTENT0_ALARM_WAKE_EN
+#define BP_RTC_PERSISTENT0_ALARM_EN                         2
+#define BM_RTC_PERSISTENT0_ALARM_EN                         0x4
+#define BF_RTC_PERSISTENT0_ALARM_EN(v)                      (((v) & 0x1) << 2)
+#define BFM_RTC_PERSISTENT0_ALARM_EN(v)                     BM_RTC_PERSISTENT0_ALARM_EN
+#define BF_RTC_PERSISTENT0_ALARM_EN_V(e)                    BF_RTC_PERSISTENT0_ALARM_EN(BV_RTC_PERSISTENT0_ALARM_EN__##e)
+#define BFM_RTC_PERSISTENT0_ALARM_EN_V(v)                   BM_RTC_PERSISTENT0_ALARM_EN
+#define BP_RTC_PERSISTENT0_ALARM_WAKE                       1
+#define BM_RTC_PERSISTENT0_ALARM_WAKE                       0x2
+#define BF_RTC_PERSISTENT0_ALARM_WAKE(v)                    (((v) & 0x1) << 1)
+#define BFM_RTC_PERSISTENT0_ALARM_WAKE(v)                   BM_RTC_PERSISTENT0_ALARM_WAKE
+#define BF_RTC_PERSISTENT0_ALARM_WAKE_V(e)                  BF_RTC_PERSISTENT0_ALARM_WAKE(BV_RTC_PERSISTENT0_ALARM_WAKE__##e)
+#define BFM_RTC_PERSISTENT0_ALARM_WAKE_V(v)                 BM_RTC_PERSISTENT0_ALARM_WAKE
+#define BP_RTC_PERSISTENT0_CLOCKSOURCE                      0
+#define BM_RTC_PERSISTENT0_CLOCKSOURCE                      0x1
+#define BF_RTC_PERSISTENT0_CLOCKSOURCE(v)                   (((v) & 0x1) << 0)
+#define BFM_RTC_PERSISTENT0_CLOCKSOURCE(v)                  BM_RTC_PERSISTENT0_CLOCKSOURCE
+#define BF_RTC_PERSISTENT0_CLOCKSOURCE_V(e)                 BF_RTC_PERSISTENT0_CLOCKSOURCE(BV_RTC_PERSISTENT0_CLOCKSOURCE__##e)
+#define BFM_RTC_PERSISTENT0_CLOCKSOURCE_V(v)                BM_RTC_PERSISTENT0_CLOCKSOURCE
+
+#define HW_RTC_PERSISTENT1                  HW(RTC_PERSISTENT1)
+#define HWA_RTC_PERSISTENT1                 (0x8005c000 + 0x70)
+#define HWT_RTC_PERSISTENT1                 HWIO_32_RW
+#define HWN_RTC_PERSISTENT1                 RTC_PERSISTENT1
+#define HWI_RTC_PERSISTENT1                 
+#define HW_RTC_PERSISTENT1_SET              HW(RTC_PERSISTENT1_SET)
+#define HWA_RTC_PERSISTENT1_SET             (HWA_RTC_PERSISTENT1 + 0x4)
+#define HWT_RTC_PERSISTENT1_SET             HWIO_32_WO
+#define HWN_RTC_PERSISTENT1_SET             RTC_PERSISTENT1
+#define HWI_RTC_PERSISTENT1_SET             
+#define HW_RTC_PERSISTENT1_CLR              HW(RTC_PERSISTENT1_CLR)
+#define HWA_RTC_PERSISTENT1_CLR             (HWA_RTC_PERSISTENT1 + 0x8)
+#define HWT_RTC_PERSISTENT1_CLR             HWIO_32_WO
+#define HWN_RTC_PERSISTENT1_CLR             RTC_PERSISTENT1
+#define HWI_RTC_PERSISTENT1_CLR             
+#define HW_RTC_PERSISTENT1_TOG              HW(RTC_PERSISTENT1_TOG)
+#define HWA_RTC_PERSISTENT1_TOG             (HWA_RTC_PERSISTENT1 + 0xc)
+#define HWT_RTC_PERSISTENT1_TOG             HWIO_32_WO
+#define HWN_RTC_PERSISTENT1_TOG             RTC_PERSISTENT1
+#define HWI_RTC_PERSISTENT1_TOG             
+#define BP_RTC_PERSISTENT1_GENERAL          0
+#define BM_RTC_PERSISTENT1_GENERAL          0xffffffff
+#define BF_RTC_PERSISTENT1_GENERAL(v)       (((v) & 0xffffffff) << 0)
+#define BFM_RTC_PERSISTENT1_GENERAL(v)      BM_RTC_PERSISTENT1_GENERAL
+#define BF_RTC_PERSISTENT1_GENERAL_V(e)     BF_RTC_PERSISTENT1_GENERAL(BV_RTC_PERSISTENT1_GENERAL__##e)
+#define BFM_RTC_PERSISTENT1_GENERAL_V(v)    BM_RTC_PERSISTENT1_GENERAL
+
+#define HW_RTC_PERSISTENT2                      HW(RTC_PERSISTENT2)
+#define HWA_RTC_PERSISTENT2                     (0x8005c000 + 0x80)
+#define HWT_RTC_PERSISTENT2                     HWIO_32_RW
+#define HWN_RTC_PERSISTENT2                     RTC_PERSISTENT2
+#define HWI_RTC_PERSISTENT2                     
+#define HW_RTC_PERSISTENT2_SET                  HW(RTC_PERSISTENT2_SET)
+#define HWA_RTC_PERSISTENT2_SET                 (HWA_RTC_PERSISTENT2 + 0x4)
+#define HWT_RTC_PERSISTENT2_SET                 HWIO_32_WO
+#define HWN_RTC_PERSISTENT2_SET                 RTC_PERSISTENT2
+#define HWI_RTC_PERSISTENT2_SET                 
+#define HW_RTC_PERSISTENT2_CLR                  HW(RTC_PERSISTENT2_CLR)
+#define HWA_RTC_PERSISTENT2_CLR                 (HWA_RTC_PERSISTENT2 + 0x8)
+#define HWT_RTC_PERSISTENT2_CLR                 HWIO_32_WO
+#define HWN_RTC_PERSISTENT2_CLR                 RTC_PERSISTENT2
+#define HWI_RTC_PERSISTENT2_CLR                 
+#define HW_RTC_PERSISTENT2_TOG                  HW(RTC_PERSISTENT2_TOG)
+#define HWA_RTC_PERSISTENT2_TOG                 (HWA_RTC_PERSISTENT2 + 0xc)
+#define HWT_RTC_PERSISTENT2_TOG                 HWIO_32_WO
+#define HWN_RTC_PERSISTENT2_TOG                 RTC_PERSISTENT2
+#define HWI_RTC_PERSISTENT2_TOG                 
+#define BP_RTC_PERSISTENT2_SRAM_LO              0
+#define BM_RTC_PERSISTENT2_SRAM_LO              0xffffffff
+#define BV_RTC_PERSISTENT2_SRAM_LO__WARM_BOOT   0x80000000
+#define BF_RTC_PERSISTENT2_SRAM_LO(v)           (((v) & 0xffffffff) << 0)
+#define BFM_RTC_PERSISTENT2_SRAM_LO(v)          BM_RTC_PERSISTENT2_SRAM_LO
+#define BF_RTC_PERSISTENT2_SRAM_LO_V(e)         BF_RTC_PERSISTENT2_SRAM_LO(BV_RTC_PERSISTENT2_SRAM_LO__##e)
+#define BFM_RTC_PERSISTENT2_SRAM_LO_V(v)        BM_RTC_PERSISTENT2_SRAM_LO
+
+#define HW_RTC_PERSISTENT3                  HW(RTC_PERSISTENT3)
+#define HWA_RTC_PERSISTENT3                 (0x8005c000 + 0x90)
+#define HWT_RTC_PERSISTENT3                 HWIO_32_RW
+#define HWN_RTC_PERSISTENT3                 RTC_PERSISTENT3
+#define HWI_RTC_PERSISTENT3                 
+#define HW_RTC_PERSISTENT3_SET              HW(RTC_PERSISTENT3_SET)
+#define HWA_RTC_PERSISTENT3_SET             (HWA_RTC_PERSISTENT3 + 0x4)
+#define HWT_RTC_PERSISTENT3_SET             HWIO_32_WO
+#define HWN_RTC_PERSISTENT3_SET             RTC_PERSISTENT3
+#define HWI_RTC_PERSISTENT3_SET             
+#define HW_RTC_PERSISTENT3_CLR              HW(RTC_PERSISTENT3_CLR)
+#define HWA_RTC_PERSISTENT3_CLR             (HWA_RTC_PERSISTENT3 + 0x8)
+#define HWT_RTC_PERSISTENT3_CLR             HWIO_32_WO
+#define HWN_RTC_PERSISTENT3_CLR             RTC_PERSISTENT3
+#define HWI_RTC_PERSISTENT3_CLR             
+#define HW_RTC_PERSISTENT3_TOG              HW(RTC_PERSISTENT3_TOG)
+#define HWA_RTC_PERSISTENT3_TOG             (HWA_RTC_PERSISTENT3 + 0xc)
+#define HWT_RTC_PERSISTENT3_TOG             HWIO_32_WO
+#define HWN_RTC_PERSISTENT3_TOG             RTC_PERSISTENT3
+#define HWI_RTC_PERSISTENT3_TOG             
+#define BP_RTC_PERSISTENT3_SRAM_HI          0
+#define BM_RTC_PERSISTENT3_SRAM_HI          0xffffffff
+#define BF_RTC_PERSISTENT3_SRAM_HI(v)       (((v) & 0xffffffff) << 0)
+#define BFM_RTC_PERSISTENT3_SRAM_HI(v)      BM_RTC_PERSISTENT3_SRAM_HI
+#define BF_RTC_PERSISTENT3_SRAM_HI_V(e)     BF_RTC_PERSISTENT3_SRAM_HI(BV_RTC_PERSISTENT3_SRAM_HI__##e)
+#define BFM_RTC_PERSISTENT3_SRAM_HI_V(v)    BM_RTC_PERSISTENT3_SRAM_HI
+
+#define HW_RTC_DEBUG                            HW(RTC_DEBUG)
+#define HWA_RTC_DEBUG                           (0x8005c000 + 0xa0)
+#define HWT_RTC_DEBUG                           HWIO_32_RW
+#define HWN_RTC_DEBUG                           RTC_DEBUG
+#define HWI_RTC_DEBUG                           
+#define HW_RTC_DEBUG_SET                        HW(RTC_DEBUG_SET)
+#define HWA_RTC_DEBUG_SET                       (HWA_RTC_DEBUG + 0x4)
+#define HWT_RTC_DEBUG_SET                       HWIO_32_WO
+#define HWN_RTC_DEBUG_SET                       RTC_DEBUG
+#define HWI_RTC_DEBUG_SET                       
+#define HW_RTC_DEBUG_CLR                        HW(RTC_DEBUG_CLR)
+#define HWA_RTC_DEBUG_CLR                       (HWA_RTC_DEBUG + 0x8)
+#define HWT_RTC_DEBUG_CLR                       HWIO_32_WO
+#define HWN_RTC_DEBUG_CLR                       RTC_DEBUG
+#define HWI_RTC_DEBUG_CLR                       
+#define HW_RTC_DEBUG_TOG                        HW(RTC_DEBUG_TOG)
+#define HWA_RTC_DEBUG_TOG                       (HWA_RTC_DEBUG + 0xc)
+#define HWT_RTC_DEBUG_TOG                       HWIO_32_WO
+#define HWN_RTC_DEBUG_TOG                       RTC_DEBUG
+#define HWI_RTC_DEBUG_TOG                       
+#define BP_RTC_DEBUG_WATCHDOG_RESET_MASK        1
+#define BM_RTC_DEBUG_WATCHDOG_RESET_MASK        0x2
+#define BF_RTC_DEBUG_WATCHDOG_RESET_MASK(v)     (((v) & 0x1) << 1)
+#define BFM_RTC_DEBUG_WATCHDOG_RESET_MASK(v)    BM_RTC_DEBUG_WATCHDOG_RESET_MASK
+#define BF_RTC_DEBUG_WATCHDOG_RESET_MASK_V(e)   BF_RTC_DEBUG_WATCHDOG_RESET_MASK(BV_RTC_DEBUG_WATCHDOG_RESET_MASK__##e)
+#define BFM_RTC_DEBUG_WATCHDOG_RESET_MASK_V(v)  BM_RTC_DEBUG_WATCHDOG_RESET_MASK
+#define BP_RTC_DEBUG_WATCHDOG_RESET             0
+#define BM_RTC_DEBUG_WATCHDOG_RESET             0x1
+#define BF_RTC_DEBUG_WATCHDOG_RESET(v)          (((v) & 0x1) << 0)
+#define BFM_RTC_DEBUG_WATCHDOG_RESET(v)         BM_RTC_DEBUG_WATCHDOG_RESET
+#define BF_RTC_DEBUG_WATCHDOG_RESET_V(e)        BF_RTC_DEBUG_WATCHDOG_RESET(BV_RTC_DEBUG_WATCHDOG_RESET__##e)
+#define BFM_RTC_DEBUG_WATCHDOG_RESET_V(v)       BM_RTC_DEBUG_WATCHDOG_RESET
+
+#define HW_RTC_UNLOCK           HW(RTC_UNLOCK)
+#define HWA_RTC_UNLOCK          (0x8005c000 + 0x200)
+#define HWT_RTC_UNLOCK          HWIO_32_RW
+#define HWN_RTC_UNLOCK          RTC_UNLOCK
+#define HWI_RTC_UNLOCK          
+#define HW_RTC_UNLOCK_SET       HW(RTC_UNLOCK_SET)
+#define HWA_RTC_UNLOCK_SET      (HWA_RTC_UNLOCK + 0x4)
+#define HWT_RTC_UNLOCK_SET      HWIO_32_WO
+#define HWN_RTC_UNLOCK_SET      RTC_UNLOCK
+#define HWI_RTC_UNLOCK_SET      
+#define HW_RTC_UNLOCK_CLR       HW(RTC_UNLOCK_CLR)
+#define HWA_RTC_UNLOCK_CLR      (HWA_RTC_UNLOCK + 0x8)
+#define HWT_RTC_UNLOCK_CLR      HWIO_32_WO
+#define HWN_RTC_UNLOCK_CLR      RTC_UNLOCK
+#define HWI_RTC_UNLOCK_CLR      
+#define HW_RTC_UNLOCK_TOG       HW(RTC_UNLOCK_TOG)
+#define HWA_RTC_UNLOCK_TOG      (HWA_RTC_UNLOCK + 0xc)
+#define HWT_RTC_UNLOCK_TOG      HWIO_32_WO
+#define HWN_RTC_UNLOCK_TOG      RTC_UNLOCK
+#define HWI_RTC_UNLOCK_TOG      
+#define BP_RTC_UNLOCK_KEY       0
+#define BM_RTC_UNLOCK_KEY       0xffffffff
+#define BV_RTC_UNLOCK_KEY__VAL  0xc6a83957
+#define BF_RTC_UNLOCK_KEY(v)    (((v) & 0xffffffff) << 0)
+#define BFM_RTC_UNLOCK_KEY(v)   BM_RTC_UNLOCK_KEY
+#define BF_RTC_UNLOCK_KEY_V(e)  BF_RTC_UNLOCK_KEY(BV_RTC_UNLOCK_KEY__##e)
+#define BFM_RTC_UNLOCK_KEY_V(v) BM_RTC_UNLOCK_KEY
+
+#define HW_RTC_LASERFUSEn(_n1)          HW(RTC_LASERFUSEn(_n1))
+#define HWA_RTC_LASERFUSEn(_n1)         (0x8005c000 + 0x300 + (_n1) * 0x10)
+#define HWT_RTC_LASERFUSEn(_n1)         HWIO_32_RW
+#define HWN_RTC_LASERFUSEn(_n1)         RTC_LASERFUSEn
+#define HWI_RTC_LASERFUSEn(_n1)         (_n1)
+#define HW_RTC_LASERFUSEn_SET(_n1)      HW(RTC_LASERFUSEn_SET(_n1))
+#define HWA_RTC_LASERFUSEn_SET(_n1)     (HWA_RTC_LASERFUSEn(_n1) + 0x4)
+#define HWT_RTC_LASERFUSEn_SET(_n1)     HWIO_32_WO
+#define HWN_RTC_LASERFUSEn_SET(_n1)     RTC_LASERFUSEn
+#define HWI_RTC_LASERFUSEn_SET(_n1)     (_n1)
+#define HW_RTC_LASERFUSEn_CLR(_n1)      HW(RTC_LASERFUSEn_CLR(_n1))
+#define HWA_RTC_LASERFUSEn_CLR(_n1)     (HWA_RTC_LASERFUSEn(_n1) + 0x8)
+#define HWT_RTC_LASERFUSEn_CLR(_n1)     HWIO_32_WO
+#define HWN_RTC_LASERFUSEn_CLR(_n1)     RTC_LASERFUSEn
+#define HWI_RTC_LASERFUSEn_CLR(_n1)     (_n1)
+#define HW_RTC_LASERFUSEn_TOG(_n1)      HW(RTC_LASERFUSEn_TOG(_n1))
+#define HWA_RTC_LASERFUSEn_TOG(_n1)     (HWA_RTC_LASERFUSEn(_n1) + 0xc)
+#define HWT_RTC_LASERFUSEn_TOG(_n1)     HWIO_32_WO
+#define HWN_RTC_LASERFUSEn_TOG(_n1)     RTC_LASERFUSEn
+#define HWI_RTC_LASERFUSEn_TOG(_n1)     (_n1)
+#define BP_RTC_LASERFUSEn_BITS          0
+#define BM_RTC_LASERFUSEn_BITS          0xffffffff
+#define BF_RTC_LASERFUSEn_BITS(v)       (((v) & 0xffffffff) << 0)
+#define BFM_RTC_LASERFUSEn_BITS(v)      BM_RTC_LASERFUSEn_BITS
+#define BF_RTC_LASERFUSEn_BITS_V(e)     BF_RTC_LASERFUSEn_BITS(BV_RTC_LASERFUSEn_BITS__##e)
+#define BFM_RTC_LASERFUSEn_BITS_V(v)    BM_RTC_LASERFUSEn_BITS
+
+#endif /* __HEADERGEN_STMP3600_RTC_H__*/
diff --git a/firmware/target/arm/imx233/regs/stmp3600/spdif.h b/firmware/target/arm/imx233/regs/stmp3600/spdif.h
new file mode 100644
index 0000000000..5f1412e8bb
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3600/spdif.h
@@ -0,0 +1,285 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * stmp3600 version: 2.4.0
+ * stmp3600 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_STMP3600_SPDIF_H__
+#define __HEADERGEN_STMP3600_SPDIF_H__
+
+#define HW_SPDIF_CTRL                           HW(SPDIF_CTRL)
+#define HWA_SPDIF_CTRL                          (0x80054000 + 0x0)
+#define HWT_SPDIF_CTRL                          HWIO_32_RW
+#define HWN_SPDIF_CTRL                          SPDIF_CTRL
+#define HWI_SPDIF_CTRL                          
+#define HW_SPDIF_CTRL_SET                       HW(SPDIF_CTRL_SET)
+#define HWA_SPDIF_CTRL_SET                      (HWA_SPDIF_CTRL + 0x4)
+#define HWT_SPDIF_CTRL_SET                      HWIO_32_WO
+#define HWN_SPDIF_CTRL_SET                      SPDIF_CTRL
+#define HWI_SPDIF_CTRL_SET                      
+#define HW_SPDIF_CTRL_CLR                       HW(SPDIF_CTRL_CLR)
+#define HWA_SPDIF_CTRL_CLR                      (HWA_SPDIF_CTRL + 0x8)
+#define HWT_SPDIF_CTRL_CLR                      HWIO_32_WO
+#define HWN_SPDIF_CTRL_CLR                      SPDIF_CTRL
+#define HWI_SPDIF_CTRL_CLR                      
+#define HW_SPDIF_CTRL_TOG                       HW(SPDIF_CTRL_TOG)
+#define HWA_SPDIF_CTRL_TOG                      (HWA_SPDIF_CTRL + 0xc)
+#define HWT_SPDIF_CTRL_TOG                      HWIO_32_WO
+#define HWN_SPDIF_CTRL_TOG                      SPDIF_CTRL
+#define HWI_SPDIF_CTRL_TOG                      
+#define BP_SPDIF_CTRL_SFTRST                    31
+#define BM_SPDIF_CTRL_SFTRST                    0x80000000
+#define BF_SPDIF_CTRL_SFTRST(v)                 (((v) & 0x1) << 31)
+#define BFM_SPDIF_CTRL_SFTRST(v)                BM_SPDIF_CTRL_SFTRST
+#define BF_SPDIF_CTRL_SFTRST_V(e)               BF_SPDIF_CTRL_SFTRST(BV_SPDIF_CTRL_SFTRST__##e)
+#define BFM_SPDIF_CTRL_SFTRST_V(v)              BM_SPDIF_CTRL_SFTRST
+#define BP_SPDIF_CTRL_CLKGATE                   30
+#define BM_SPDIF_CTRL_CLKGATE                   0x40000000
+#define BF_SPDIF_CTRL_CLKGATE(v)                (((v) & 0x1) << 30)
+#define BFM_SPDIF_CTRL_CLKGATE(v)               BM_SPDIF_CTRL_CLKGATE
+#define BF_SPDIF_CTRL_CLKGATE_V(e)              BF_SPDIF_CTRL_CLKGATE(BV_SPDIF_CTRL_CLKGATE__##e)
+#define BFM_SPDIF_CTRL_CLKGATE_V(v)             BM_SPDIF_CTRL_CLKGATE
+#define BP_SPDIF_CTRL_DMAWAIT_COUNT             16
+#define BM_SPDIF_CTRL_DMAWAIT_COUNT             0x1f0000
+#define BF_SPDIF_CTRL_DMAWAIT_COUNT(v)          (((v) & 0x1f) << 16)
+#define BFM_SPDIF_CTRL_DMAWAIT_COUNT(v)         BM_SPDIF_CTRL_DMAWAIT_COUNT
+#define BF_SPDIF_CTRL_DMAWAIT_COUNT_V(e)        BF_SPDIF_CTRL_DMAWAIT_COUNT(BV_SPDIF_CTRL_DMAWAIT_COUNT__##e)
+#define BFM_SPDIF_CTRL_DMAWAIT_COUNT_V(v)       BM_SPDIF_CTRL_DMAWAIT_COUNT
+#define BP_SPDIF_CTRL_WAIT_END_XFER             5
+#define BM_SPDIF_CTRL_WAIT_END_XFER             0x20
+#define BF_SPDIF_CTRL_WAIT_END_XFER(v)          (((v) & 0x1) << 5)
+#define BFM_SPDIF_CTRL_WAIT_END_XFER(v)         BM_SPDIF_CTRL_WAIT_END_XFER
+#define BF_SPDIF_CTRL_WAIT_END_XFER_V(e)        BF_SPDIF_CTRL_WAIT_END_XFER(BV_SPDIF_CTRL_WAIT_END_XFER__##e)
+#define BFM_SPDIF_CTRL_WAIT_END_XFER_V(v)       BM_SPDIF_CTRL_WAIT_END_XFER
+#define BP_SPDIF_CTRL_WORD_LENGTH               4
+#define BM_SPDIF_CTRL_WORD_LENGTH               0x10
+#define BF_SPDIF_CTRL_WORD_LENGTH(v)            (((v) & 0x1) << 4)
+#define BFM_SPDIF_CTRL_WORD_LENGTH(v)           BM_SPDIF_CTRL_WORD_LENGTH
+#define BF_SPDIF_CTRL_WORD_LENGTH_V(e)          BF_SPDIF_CTRL_WORD_LENGTH(BV_SPDIF_CTRL_WORD_LENGTH__##e)
+#define BFM_SPDIF_CTRL_WORD_LENGTH_V(v)         BM_SPDIF_CTRL_WORD_LENGTH
+#define BP_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ        3
+#define BM_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ        0x8
+#define BF_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ(v)     (((v) & 0x1) << 3)
+#define BFM_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ(v)    BM_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ
+#define BF_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ_V(e)   BF_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ(BV_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ__##e)
+#define BFM_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ_V(v)  BM_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ
+#define BP_SPDIF_CTRL_FIFO_OVERFLOW_IRQ         2
+#define BM_SPDIF_CTRL_FIFO_OVERFLOW_IRQ         0x4
+#define BF_SPDIF_CTRL_FIFO_OVERFLOW_IRQ(v)      (((v) & 0x1) << 2)
+#define BFM_SPDIF_CTRL_FIFO_OVERFLOW_IRQ(v)     BM_SPDIF_CTRL_FIFO_OVERFLOW_IRQ
+#define BF_SPDIF_CTRL_FIFO_OVERFLOW_IRQ_V(e)    BF_SPDIF_CTRL_FIFO_OVERFLOW_IRQ(BV_SPDIF_CTRL_FIFO_OVERFLOW_IRQ__##e)
+#define BFM_SPDIF_CTRL_FIFO_OVERFLOW_IRQ_V(v)   BM_SPDIF_CTRL_FIFO_OVERFLOW_IRQ
+#define BP_SPDIF_CTRL_FIFO_ERROR_IRQ_EN         1
+#define BM_SPDIF_CTRL_FIFO_ERROR_IRQ_EN         0x2
+#define BF_SPDIF_CTRL_FIFO_ERROR_IRQ_EN(v)      (((v) & 0x1) << 1)
+#define BFM_SPDIF_CTRL_FIFO_ERROR_IRQ_EN(v)     BM_SPDIF_CTRL_FIFO_ERROR_IRQ_EN
+#define BF_SPDIF_CTRL_FIFO_ERROR_IRQ_EN_V(e)    BF_SPDIF_CTRL_FIFO_ERROR_IRQ_EN(BV_SPDIF_CTRL_FIFO_ERROR_IRQ_EN__##e)
+#define BFM_SPDIF_CTRL_FIFO_ERROR_IRQ_EN_V(v)   BM_SPDIF_CTRL_FIFO_ERROR_IRQ_EN
+#define BP_SPDIF_CTRL_RUN                       0
+#define BM_SPDIF_CTRL_RUN                       0x1
+#define BF_SPDIF_CTRL_RUN(v)                    (((v) & 0x1) << 0)
+#define BFM_SPDIF_CTRL_RUN(v)                   BM_SPDIF_CTRL_RUN
+#define BF_SPDIF_CTRL_RUN_V(e)                  BF_SPDIF_CTRL_RUN(BV_SPDIF_CTRL_RUN__##e)
+#define BFM_SPDIF_CTRL_RUN_V(v)                 BM_SPDIF_CTRL_RUN
+
+#define HW_SPDIF_STAT                   HW(SPDIF_STAT)
+#define HWA_SPDIF_STAT                  (0x80054000 + 0x10)
+#define HWT_SPDIF_STAT                  HWIO_32_RW
+#define HWN_SPDIF_STAT                  SPDIF_STAT
+#define HWI_SPDIF_STAT                  
+#define BP_SPDIF_STAT_PRESENT           31
+#define BM_SPDIF_STAT_PRESENT           0x80000000
+#define BF_SPDIF_STAT_PRESENT(v)        (((v) & 0x1) << 31)
+#define BFM_SPDIF_STAT_PRESENT(v)       BM_SPDIF_STAT_PRESENT
+#define BF_SPDIF_STAT_PRESENT_V(e)      BF_SPDIF_STAT_PRESENT(BV_SPDIF_STAT_PRESENT__##e)
+#define BFM_SPDIF_STAT_PRESENT_V(v)     BM_SPDIF_STAT_PRESENT
+#define BP_SPDIF_STAT_END_XFER          0
+#define BM_SPDIF_STAT_END_XFER          0x1
+#define BF_SPDIF_STAT_END_XFER(v)       (((v) & 0x1) << 0)
+#define BFM_SPDIF_STAT_END_XFER(v)      BM_SPDIF_STAT_END_XFER
+#define BF_SPDIF_STAT_END_XFER_V(e)     BF_SPDIF_STAT_END_XFER(BV_SPDIF_STAT_END_XFER__##e)
+#define BFM_SPDIF_STAT_END_XFER_V(v)    BM_SPDIF_STAT_END_XFER
+
+#define HW_SPDIF_FRAMECTRL                  HW(SPDIF_FRAMECTRL)
+#define HWA_SPDIF_FRAMECTRL                 (0x80054000 + 0x20)
+#define HWT_SPDIF_FRAMECTRL                 HWIO_32_RW
+#define HWN_SPDIF_FRAMECTRL                 SPDIF_FRAMECTRL
+#define HWI_SPDIF_FRAMECTRL                 
+#define HW_SPDIF_FRAMECTRL_SET              HW(SPDIF_FRAMECTRL_SET)
+#define HWA_SPDIF_FRAMECTRL_SET             (HWA_SPDIF_FRAMECTRL + 0x4)
+#define HWT_SPDIF_FRAMECTRL_SET             HWIO_32_WO
+#define HWN_SPDIF_FRAMECTRL_SET             SPDIF_FRAMECTRL
+#define HWI_SPDIF_FRAMECTRL_SET             
+#define HW_SPDIF_FRAMECTRL_CLR              HW(SPDIF_FRAMECTRL_CLR)
+#define HWA_SPDIF_FRAMECTRL_CLR             (HWA_SPDIF_FRAMECTRL + 0x8)
+#define HWT_SPDIF_FRAMECTRL_CLR             HWIO_32_WO
+#define HWN_SPDIF_FRAMECTRL_CLR             SPDIF_FRAMECTRL
+#define HWI_SPDIF_FRAMECTRL_CLR             
+#define HW_SPDIF_FRAMECTRL_TOG              HW(SPDIF_FRAMECTRL_TOG)
+#define HWA_SPDIF_FRAMECTRL_TOG             (HWA_SPDIF_FRAMECTRL + 0xc)
+#define HWT_SPDIF_FRAMECTRL_TOG             HWIO_32_WO
+#define HWN_SPDIF_FRAMECTRL_TOG             SPDIF_FRAMECTRL
+#define HWI_SPDIF_FRAMECTRL_TOG             
+#define BP_SPDIF_FRAMECTRL_V_CONFIG         17
+#define BM_SPDIF_FRAMECTRL_V_CONFIG         0x20000
+#define BF_SPDIF_FRAMECTRL_V_CONFIG(v)      (((v) & 0x1) << 17)
+#define BFM_SPDIF_FRAMECTRL_V_CONFIG(v)     BM_SPDIF_FRAMECTRL_V_CONFIG
+#define BF_SPDIF_FRAMECTRL_V_CONFIG_V(e)    BF_SPDIF_FRAMECTRL_V_CONFIG(BV_SPDIF_FRAMECTRL_V_CONFIG__##e)
+#define BFM_SPDIF_FRAMECTRL_V_CONFIG_V(v)   BM_SPDIF_FRAMECTRL_V_CONFIG
+#define BP_SPDIF_FRAMECTRL_AUTO_MUTE        16
+#define BM_SPDIF_FRAMECTRL_AUTO_MUTE        0x10000
+#define BF_SPDIF_FRAMECTRL_AUTO_MUTE(v)     (((v) & 0x1) << 16)
+#define BFM_SPDIF_FRAMECTRL_AUTO_MUTE(v)    BM_SPDIF_FRAMECTRL_AUTO_MUTE
+#define BF_SPDIF_FRAMECTRL_AUTO_MUTE_V(e)   BF_SPDIF_FRAMECTRL_AUTO_MUTE(BV_SPDIF_FRAMECTRL_AUTO_MUTE__##e)
+#define BFM_SPDIF_FRAMECTRL_AUTO_MUTE_V(v)  BM_SPDIF_FRAMECTRL_AUTO_MUTE
+#define BP_SPDIF_FRAMECTRL_USER_DATA        14
+#define BM_SPDIF_FRAMECTRL_USER_DATA        0x4000
+#define BF_SPDIF_FRAMECTRL_USER_DATA(v)     (((v) & 0x1) << 14)
+#define BFM_SPDIF_FRAMECTRL_USER_DATA(v)    BM_SPDIF_FRAMECTRL_USER_DATA
+#define BF_SPDIF_FRAMECTRL_USER_DATA_V(e)   BF_SPDIF_FRAMECTRL_USER_DATA(BV_SPDIF_FRAMECTRL_USER_DATA__##e)
+#define BFM_SPDIF_FRAMECTRL_USER_DATA_V(v)  BM_SPDIF_FRAMECTRL_USER_DATA
+#define BP_SPDIF_FRAMECTRL_V                13
+#define BM_SPDIF_FRAMECTRL_V                0x2000
+#define BF_SPDIF_FRAMECTRL_V(v)             (((v) & 0x1) << 13)
+#define BFM_SPDIF_FRAMECTRL_V(v)            BM_SPDIF_FRAMECTRL_V
+#define BF_SPDIF_FRAMECTRL_V_V(e)           BF_SPDIF_FRAMECTRL_V(BV_SPDIF_FRAMECTRL_V__##e)
+#define BFM_SPDIF_FRAMECTRL_V_V(v)          BM_SPDIF_FRAMECTRL_V
+#define BP_SPDIF_FRAMECTRL_L                12
+#define BM_SPDIF_FRAMECTRL_L                0x1000
+#define BF_SPDIF_FRAMECTRL_L(v)             (((v) & 0x1) << 12)
+#define BFM_SPDIF_FRAMECTRL_L(v)            BM_SPDIF_FRAMECTRL_L
+#define BF_SPDIF_FRAMECTRL_L_V(e)           BF_SPDIF_FRAMECTRL_L(BV_SPDIF_FRAMECTRL_L__##e)
+#define BFM_SPDIF_FRAMECTRL_L_V(v)          BM_SPDIF_FRAMECTRL_L
+#define BP_SPDIF_FRAMECTRL_CC               4
+#define BM_SPDIF_FRAMECTRL_CC               0x7f0
+#define BF_SPDIF_FRAMECTRL_CC(v)            (((v) & 0x7f) << 4)
+#define BFM_SPDIF_FRAMECTRL_CC(v)           BM_SPDIF_FRAMECTRL_CC
+#define BF_SPDIF_FRAMECTRL_CC_V(e)          BF_SPDIF_FRAMECTRL_CC(BV_SPDIF_FRAMECTRL_CC__##e)
+#define BFM_SPDIF_FRAMECTRL_CC_V(v)         BM_SPDIF_FRAMECTRL_CC
+#define BP_SPDIF_FRAMECTRL_PRE              3
+#define BM_SPDIF_FRAMECTRL_PRE              0x8
+#define BF_SPDIF_FRAMECTRL_PRE(v)           (((v) & 0x1) << 3)
+#define BFM_SPDIF_FRAMECTRL_PRE(v)          BM_SPDIF_FRAMECTRL_PRE
+#define BF_SPDIF_FRAMECTRL_PRE_V(e)         BF_SPDIF_FRAMECTRL_PRE(BV_SPDIF_FRAMECTRL_PRE__##e)
+#define BFM_SPDIF_FRAMECTRL_PRE_V(v)        BM_SPDIF_FRAMECTRL_PRE
+#define BP_SPDIF_FRAMECTRL_COPY             2
+#define BM_SPDIF_FRAMECTRL_COPY             0x4
+#define BF_SPDIF_FRAMECTRL_COPY(v)          (((v) & 0x1) << 2)
+#define BFM_SPDIF_FRAMECTRL_COPY(v)         BM_SPDIF_FRAMECTRL_COPY
+#define BF_SPDIF_FRAMECTRL_COPY_V(e)        BF_SPDIF_FRAMECTRL_COPY(BV_SPDIF_FRAMECTRL_COPY__##e)
+#define BFM_SPDIF_FRAMECTRL_COPY_V(v)       BM_SPDIF_FRAMECTRL_COPY
+#define BP_SPDIF_FRAMECTRL_AUDIO            1
+#define BM_SPDIF_FRAMECTRL_AUDIO            0x2
+#define BF_SPDIF_FRAMECTRL_AUDIO(v)         (((v) & 0x1) << 1)
+#define BFM_SPDIF_FRAMECTRL_AUDIO(v)        BM_SPDIF_FRAMECTRL_AUDIO
+#define BF_SPDIF_FRAMECTRL_AUDIO_V(e)       BF_SPDIF_FRAMECTRL_AUDIO(BV_SPDIF_FRAMECTRL_AUDIO__##e)
+#define BFM_SPDIF_FRAMECTRL_AUDIO_V(v)      BM_SPDIF_FRAMECTRL_AUDIO
+#define BP_SPDIF_FRAMECTRL_PRO              0
+#define BM_SPDIF_FRAMECTRL_PRO              0x1
+#define BF_SPDIF_FRAMECTRL_PRO(v)           (((v) & 0x1) << 0)
+#define BFM_SPDIF_FRAMECTRL_PRO(v)          BM_SPDIF_FRAMECTRL_PRO
+#define BF_SPDIF_FRAMECTRL_PRO_V(e)         BF_SPDIF_FRAMECTRL_PRO(BV_SPDIF_FRAMECTRL_PRO__##e)
+#define BFM_SPDIF_FRAMECTRL_PRO_V(v)        BM_SPDIF_FRAMECTRL_PRO
+
+#define HW_SPDIF_SRR                HW(SPDIF_SRR)
+#define HWA_SPDIF_SRR               (0x80054000 + 0x30)
+#define HWT_SPDIF_SRR               HWIO_32_RW
+#define HWN_SPDIF_SRR               SPDIF_SRR
+#define HWI_SPDIF_SRR               
+#define HW_SPDIF_SRR_SET            HW(SPDIF_SRR_SET)
+#define HWA_SPDIF_SRR_SET           (HWA_SPDIF_SRR + 0x4)
+#define HWT_SPDIF_SRR_SET           HWIO_32_WO
+#define HWN_SPDIF_SRR_SET           SPDIF_SRR
+#define HWI_SPDIF_SRR_SET           
+#define HW_SPDIF_SRR_CLR            HW(SPDIF_SRR_CLR)
+#define HWA_SPDIF_SRR_CLR           (HWA_SPDIF_SRR + 0x8)
+#define HWT_SPDIF_SRR_CLR           HWIO_32_WO
+#define HWN_SPDIF_SRR_CLR           SPDIF_SRR
+#define HWI_SPDIF_SRR_CLR           
+#define HW_SPDIF_SRR_TOG            HW(SPDIF_SRR_TOG)
+#define HWA_SPDIF_SRR_TOG           (HWA_SPDIF_SRR + 0xc)
+#define HWT_SPDIF_SRR_TOG           HWIO_32_WO
+#define HWN_SPDIF_SRR_TOG           SPDIF_SRR
+#define HWI_SPDIF_SRR_TOG           
+#define BP_SPDIF_SRR_BASEMULT       28
+#define BM_SPDIF_SRR_BASEMULT       0x70000000
+#define BF_SPDIF_SRR_BASEMULT(v)    (((v) & 0x7) << 28)
+#define BFM_SPDIF_SRR_BASEMULT(v)   BM_SPDIF_SRR_BASEMULT
+#define BF_SPDIF_SRR_BASEMULT_V(e)  BF_SPDIF_SRR_BASEMULT(BV_SPDIF_SRR_BASEMULT__##e)
+#define BFM_SPDIF_SRR_BASEMULT_V(v) BM_SPDIF_SRR_BASEMULT
+#define BP_SPDIF_SRR_RATE           0
+#define BM_SPDIF_SRR_RATE           0xfffff
+#define BF_SPDIF_SRR_RATE(v)        (((v) & 0xfffff) << 0)
+#define BFM_SPDIF_SRR_RATE(v)       BM_SPDIF_SRR_RATE
+#define BF_SPDIF_SRR_RATE_V(e)      BF_SPDIF_SRR_RATE(BV_SPDIF_SRR_RATE__##e)
+#define BFM_SPDIF_SRR_RATE_V(v)     BM_SPDIF_SRR_RATE
+
+#define HW_SPDIF_DEBUG                      HW(SPDIF_DEBUG)
+#define HWA_SPDIF_DEBUG                     (0x80054000 + 0x40)
+#define HWT_SPDIF_DEBUG                     HWIO_32_RW
+#define HWN_SPDIF_DEBUG                     SPDIF_DEBUG
+#define HWI_SPDIF_DEBUG                     
+#define BP_SPDIF_DEBUG_DMA_PREQ             1
+#define BM_SPDIF_DEBUG_DMA_PREQ             0x2
+#define BF_SPDIF_DEBUG_DMA_PREQ(v)          (((v) & 0x1) << 1)
+#define BFM_SPDIF_DEBUG_DMA_PREQ(v)         BM_SPDIF_DEBUG_DMA_PREQ
+#define BF_SPDIF_DEBUG_DMA_PREQ_V(e)        BF_SPDIF_DEBUG_DMA_PREQ(BV_SPDIF_DEBUG_DMA_PREQ__##e)
+#define BFM_SPDIF_DEBUG_DMA_PREQ_V(v)       BM_SPDIF_DEBUG_DMA_PREQ
+#define BP_SPDIF_DEBUG_FIFO_STATUS          0
+#define BM_SPDIF_DEBUG_FIFO_STATUS          0x1
+#define BF_SPDIF_DEBUG_FIFO_STATUS(v)       (((v) & 0x1) << 0)
+#define BFM_SPDIF_DEBUG_FIFO_STATUS(v)      BM_SPDIF_DEBUG_FIFO_STATUS
+#define BF_SPDIF_DEBUG_FIFO_STATUS_V(e)     BF_SPDIF_DEBUG_FIFO_STATUS(BV_SPDIF_DEBUG_FIFO_STATUS__##e)
+#define BFM_SPDIF_DEBUG_FIFO_STATUS_V(v)    BM_SPDIF_DEBUG_FIFO_STATUS
+
+#define HW_SPDIF_DATA               HW(SPDIF_DATA)
+#define HWA_SPDIF_DATA              (0x80054000 + 0x50)
+#define HWT_SPDIF_DATA              HWIO_32_RW
+#define HWN_SPDIF_DATA              SPDIF_DATA
+#define HWI_SPDIF_DATA              
+#define HW_SPDIF_DATA_SET           HW(SPDIF_DATA_SET)
+#define HWA_SPDIF_DATA_SET          (HWA_SPDIF_DATA + 0x4)
+#define HWT_SPDIF_DATA_SET          HWIO_32_WO
+#define HWN_SPDIF_DATA_SET          SPDIF_DATA
+#define HWI_SPDIF_DATA_SET          
+#define HW_SPDIF_DATA_CLR           HW(SPDIF_DATA_CLR)
+#define HWA_SPDIF_DATA_CLR          (HWA_SPDIF_DATA + 0x8)
+#define HWT_SPDIF_DATA_CLR          HWIO_32_WO
+#define HWN_SPDIF_DATA_CLR          SPDIF_DATA
+#define HWI_SPDIF_DATA_CLR          
+#define HW_SPDIF_DATA_TOG           HW(SPDIF_DATA_TOG)
+#define HWA_SPDIF_DATA_TOG          (HWA_SPDIF_DATA + 0xc)
+#define HWT_SPDIF_DATA_TOG          HWIO_32_WO
+#define HWN_SPDIF_DATA_TOG          SPDIF_DATA
+#define HWI_SPDIF_DATA_TOG          
+#define BP_SPDIF_DATA_HIGH          16
+#define BM_SPDIF_DATA_HIGH          0xffff0000
+#define BF_SPDIF_DATA_HIGH(v)       (((v) & 0xffff) << 16)
+#define BFM_SPDIF_DATA_HIGH(v)      BM_SPDIF_DATA_HIGH
+#define BF_SPDIF_DATA_HIGH_V(e)     BF_SPDIF_DATA_HIGH(BV_SPDIF_DATA_HIGH__##e)
+#define BFM_SPDIF_DATA_HIGH_V(v)    BM_SPDIF_DATA_HIGH
+#define BP_SPDIF_DATA_LOW           0
+#define BM_SPDIF_DATA_LOW           0xffff
+#define BF_SPDIF_DATA_LOW(v)        (((v) & 0xffff) << 0)
+#define BFM_SPDIF_DATA_LOW(v)       BM_SPDIF_DATA_LOW
+#define BF_SPDIF_DATA_LOW_V(e)      BF_SPDIF_DATA_LOW(BV_SPDIF_DATA_LOW__##e)
+#define BFM_SPDIF_DATA_LOW_V(v)     BM_SPDIF_DATA_LOW
+
+#endif /* __HEADERGEN_STMP3600_SPDIF_H__*/
diff --git a/firmware/target/arm/imx233/regs/stmp3600/ssp.h b/firmware/target/arm/imx233/regs/stmp3600/ssp.h
new file mode 100644
index 0000000000..01e96f0eb5
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3600/ssp.h
@@ -0,0 +1,837 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * stmp3600 version: 2.4.0
+ * stmp3600 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_STMP3600_SSP_H__
+#define __HEADERGEN_STMP3600_SSP_H__
+
+#define HW_SSP_CTRL0                        HW(SSP_CTRL0)
+#define HWA_SSP_CTRL0                       (0x80010000 + 0x0)
+#define HWT_SSP_CTRL0                       HWIO_32_RW
+#define HWN_SSP_CTRL0                       SSP_CTRL0
+#define HWI_SSP_CTRL0                       
+#define HW_SSP_CTRL0_SET                    HW(SSP_CTRL0_SET)
+#define HWA_SSP_CTRL0_SET                   (HWA_SSP_CTRL0 + 0x4)
+#define HWT_SSP_CTRL0_SET                   HWIO_32_WO
+#define HWN_SSP_CTRL0_SET                   SSP_CTRL0
+#define HWI_SSP_CTRL0_SET                   
+#define HW_SSP_CTRL0_CLR                    HW(SSP_CTRL0_CLR)
+#define HWA_SSP_CTRL0_CLR                   (HWA_SSP_CTRL0 + 0x8)
+#define HWT_SSP_CTRL0_CLR                   HWIO_32_WO
+#define HWN_SSP_CTRL0_CLR                   SSP_CTRL0
+#define HWI_SSP_CTRL0_CLR                   
+#define HW_SSP_CTRL0_TOG                    HW(SSP_CTRL0_TOG)
+#define HWA_SSP_CTRL0_TOG                   (HWA_SSP_CTRL0 + 0xc)
+#define HWT_SSP_CTRL0_TOG                   HWIO_32_WO
+#define HWN_SSP_CTRL0_TOG                   SSP_CTRL0
+#define HWI_SSP_CTRL0_TOG                   
+#define BP_SSP_CTRL0_SFTRST                 31
+#define BM_SSP_CTRL0_SFTRST                 0x80000000
+#define BF_SSP_CTRL0_SFTRST(v)              (((v) & 0x1) << 31)
+#define BFM_SSP_CTRL0_SFTRST(v)             BM_SSP_CTRL0_SFTRST
+#define BF_SSP_CTRL0_SFTRST_V(e)            BF_SSP_CTRL0_SFTRST(BV_SSP_CTRL0_SFTRST__##e)
+#define BFM_SSP_CTRL0_SFTRST_V(v)           BM_SSP_CTRL0_SFTRST
+#define BP_SSP_CTRL0_CLKGATE                30
+#define BM_SSP_CTRL0_CLKGATE                0x40000000
+#define BF_SSP_CTRL0_CLKGATE(v)             (((v) & 0x1) << 30)
+#define BFM_SSP_CTRL0_CLKGATE(v)            BM_SSP_CTRL0_CLKGATE
+#define BF_SSP_CTRL0_CLKGATE_V(e)           BF_SSP_CTRL0_CLKGATE(BV_SSP_CTRL0_CLKGATE__##e)
+#define BFM_SSP_CTRL0_CLKGATE_V(v)          BM_SSP_CTRL0_CLKGATE
+#define BP_SSP_CTRL0_RUN                    29
+#define BM_SSP_CTRL0_RUN                    0x20000000
+#define BF_SSP_CTRL0_RUN(v)                 (((v) & 0x1) << 29)
+#define BFM_SSP_CTRL0_RUN(v)                BM_SSP_CTRL0_RUN
+#define BF_SSP_CTRL0_RUN_V(e)               BF_SSP_CTRL0_RUN(BV_SSP_CTRL0_RUN__##e)
+#define BFM_SSP_CTRL0_RUN_V(v)              BM_SSP_CTRL0_RUN
+#define BP_SSP_CTRL0_HALF_DUPLEX            28
+#define BM_SSP_CTRL0_HALF_DUPLEX            0x10000000
+#define BF_SSP_CTRL0_HALF_DUPLEX(v)         (((v) & 0x1) << 28)
+#define BFM_SSP_CTRL0_HALF_DUPLEX(v)        BM_SSP_CTRL0_HALF_DUPLEX
+#define BF_SSP_CTRL0_HALF_DUPLEX_V(e)       BF_SSP_CTRL0_HALF_DUPLEX(BV_SSP_CTRL0_HALF_DUPLEX__##e)
+#define BFM_SSP_CTRL0_HALF_DUPLEX_V(v)      BM_SSP_CTRL0_HALF_DUPLEX
+#define BP_SSP_CTRL0_LOCK_CS                27
+#define BM_SSP_CTRL0_LOCK_CS                0x8000000
+#define BF_SSP_CTRL0_LOCK_CS(v)             (((v) & 0x1) << 27)
+#define BFM_SSP_CTRL0_LOCK_CS(v)            BM_SSP_CTRL0_LOCK_CS
+#define BF_SSP_CTRL0_LOCK_CS_V(e)           BF_SSP_CTRL0_LOCK_CS(BV_SSP_CTRL0_LOCK_CS__##e)
+#define BFM_SSP_CTRL0_LOCK_CS_V(v)          BM_SSP_CTRL0_LOCK_CS
+#define BP_SSP_CTRL0_IGNORE_CRC             26
+#define BM_SSP_CTRL0_IGNORE_CRC             0x4000000
+#define BF_SSP_CTRL0_IGNORE_CRC(v)          (((v) & 0x1) << 26)
+#define BFM_SSP_CTRL0_IGNORE_CRC(v)         BM_SSP_CTRL0_IGNORE_CRC
+#define BF_SSP_CTRL0_IGNORE_CRC_V(e)        BF_SSP_CTRL0_IGNORE_CRC(BV_SSP_CTRL0_IGNORE_CRC__##e)
+#define BFM_SSP_CTRL0_IGNORE_CRC_V(v)       BM_SSP_CTRL0_IGNORE_CRC
+#define BP_SSP_CTRL0_READ                   25
+#define BM_SSP_CTRL0_READ                   0x2000000
+#define BF_SSP_CTRL0_READ(v)                (((v) & 0x1) << 25)
+#define BFM_SSP_CTRL0_READ(v)               BM_SSP_CTRL0_READ
+#define BF_SSP_CTRL0_READ_V(e)              BF_SSP_CTRL0_READ(BV_SSP_CTRL0_READ__##e)
+#define BFM_SSP_CTRL0_READ_V(v)             BM_SSP_CTRL0_READ
+#define BP_SSP_CTRL0_DATA_XFER              24
+#define BM_SSP_CTRL0_DATA_XFER              0x1000000
+#define BF_SSP_CTRL0_DATA_XFER(v)           (((v) & 0x1) << 24)
+#define BFM_SSP_CTRL0_DATA_XFER(v)          BM_SSP_CTRL0_DATA_XFER
+#define BF_SSP_CTRL0_DATA_XFER_V(e)         BF_SSP_CTRL0_DATA_XFER(BV_SSP_CTRL0_DATA_XFER__##e)
+#define BFM_SSP_CTRL0_DATA_XFER_V(v)        BM_SSP_CTRL0_DATA_XFER
+#define BP_SSP_CTRL0_SDIO_IRQ               23
+#define BM_SSP_CTRL0_SDIO_IRQ               0x800000
+#define BF_SSP_CTRL0_SDIO_IRQ(v)            (((v) & 0x1) << 23)
+#define BFM_SSP_CTRL0_SDIO_IRQ(v)           BM_SSP_CTRL0_SDIO_IRQ
+#define BF_SSP_CTRL0_SDIO_IRQ_V(e)          BF_SSP_CTRL0_SDIO_IRQ(BV_SSP_CTRL0_SDIO_IRQ__##e)
+#define BFM_SSP_CTRL0_SDIO_IRQ_V(v)         BM_SSP_CTRL0_SDIO_IRQ
+#define BP_SSP_CTRL0_BUS_WIDTH              22
+#define BM_SSP_CTRL0_BUS_WIDTH              0x400000
+#define BV_SSP_CTRL0_BUS_WIDTH__ONE_BIT     0x0
+#define BV_SSP_CTRL0_BUS_WIDTH__FOUR_BIT    0x1
+#define BF_SSP_CTRL0_BUS_WIDTH(v)           (((v) & 0x1) << 22)
+#define BFM_SSP_CTRL0_BUS_WIDTH(v)          BM_SSP_CTRL0_BUS_WIDTH
+#define BF_SSP_CTRL0_BUS_WIDTH_V(e)         BF_SSP_CTRL0_BUS_WIDTH(BV_SSP_CTRL0_BUS_WIDTH__##e)
+#define BFM_SSP_CTRL0_BUS_WIDTH_V(v)        BM_SSP_CTRL0_BUS_WIDTH
+#define BP_SSP_CTRL0_WAIT_FOR_IRQ           21
+#define BM_SSP_CTRL0_WAIT_FOR_IRQ           0x200000
+#define BF_SSP_CTRL0_WAIT_FOR_IRQ(v)        (((v) & 0x1) << 21)
+#define BFM_SSP_CTRL0_WAIT_FOR_IRQ(v)       BM_SSP_CTRL0_WAIT_FOR_IRQ
+#define BF_SSP_CTRL0_WAIT_FOR_IRQ_V(e)      BF_SSP_CTRL0_WAIT_FOR_IRQ(BV_SSP_CTRL0_WAIT_FOR_IRQ__##e)
+#define BFM_SSP_CTRL0_WAIT_FOR_IRQ_V(v)     BM_SSP_CTRL0_WAIT_FOR_IRQ
+#define BP_SSP_CTRL0_WAIT_FOR_CMD           20
+#define BM_SSP_CTRL0_WAIT_FOR_CMD           0x100000
+#define BF_SSP_CTRL0_WAIT_FOR_CMD(v)        (((v) & 0x1) << 20)
+#define BFM_SSP_CTRL0_WAIT_FOR_CMD(v)       BM_SSP_CTRL0_WAIT_FOR_CMD
+#define BF_SSP_CTRL0_WAIT_FOR_CMD_V(e)      BF_SSP_CTRL0_WAIT_FOR_CMD(BV_SSP_CTRL0_WAIT_FOR_CMD__##e)
+#define BFM_SSP_CTRL0_WAIT_FOR_CMD_V(v)     BM_SSP_CTRL0_WAIT_FOR_CMD
+#define BP_SSP_CTRL0_LONG_RESP              19
+#define BM_SSP_CTRL0_LONG_RESP              0x80000
+#define BF_SSP_CTRL0_LONG_RESP(v)           (((v) & 0x1) << 19)
+#define BFM_SSP_CTRL0_LONG_RESP(v)          BM_SSP_CTRL0_LONG_RESP
+#define BF_SSP_CTRL0_LONG_RESP_V(e)         BF_SSP_CTRL0_LONG_RESP(BV_SSP_CTRL0_LONG_RESP__##e)
+#define BFM_SSP_CTRL0_LONG_RESP_V(v)        BM_SSP_CTRL0_LONG_RESP
+#define BP_SSP_CTRL0_CHECK_RESP             18
+#define BM_SSP_CTRL0_CHECK_RESP             0x40000
+#define BF_SSP_CTRL0_CHECK_RESP(v)          (((v) & 0x1) << 18)
+#define BFM_SSP_CTRL0_CHECK_RESP(v)         BM_SSP_CTRL0_CHECK_RESP
+#define BF_SSP_CTRL0_CHECK_RESP_V(e)        BF_SSP_CTRL0_CHECK_RESP(BV_SSP_CTRL0_CHECK_RESP__##e)
+#define BFM_SSP_CTRL0_CHECK_RESP_V(v)       BM_SSP_CTRL0_CHECK_RESP
+#define BP_SSP_CTRL0_GET_RESP               17
+#define BM_SSP_CTRL0_GET_RESP               0x20000
+#define BF_SSP_CTRL0_GET_RESP(v)            (((v) & 0x1) << 17)
+#define BFM_SSP_CTRL0_GET_RESP(v)           BM_SSP_CTRL0_GET_RESP
+#define BF_SSP_CTRL0_GET_RESP_V(e)          BF_SSP_CTRL0_GET_RESP(BV_SSP_CTRL0_GET_RESP__##e)
+#define BFM_SSP_CTRL0_GET_RESP_V(v)         BM_SSP_CTRL0_GET_RESP
+#define BP_SSP_CTRL0_ENABLE                 16
+#define BM_SSP_CTRL0_ENABLE                 0x10000
+#define BF_SSP_CTRL0_ENABLE(v)              (((v) & 0x1) << 16)
+#define BFM_SSP_CTRL0_ENABLE(v)             BM_SSP_CTRL0_ENABLE
+#define BF_SSP_CTRL0_ENABLE_V(e)            BF_SSP_CTRL0_ENABLE(BV_SSP_CTRL0_ENABLE__##e)
+#define BFM_SSP_CTRL0_ENABLE_V(v)           BM_SSP_CTRL0_ENABLE
+#define BP_SSP_CTRL0_XFER_COUNT             0
+#define BM_SSP_CTRL0_XFER_COUNT             0xffff
+#define BF_SSP_CTRL0_XFER_COUNT(v)          (((v) & 0xffff) << 0)
+#define BFM_SSP_CTRL0_XFER_COUNT(v)         BM_SSP_CTRL0_XFER_COUNT
+#define BF_SSP_CTRL0_XFER_COUNT_V(e)        BF_SSP_CTRL0_XFER_COUNT(BV_SSP_CTRL0_XFER_COUNT__##e)
+#define BFM_SSP_CTRL0_XFER_COUNT_V(v)       BM_SSP_CTRL0_XFER_COUNT
+
+#define HW_SSP_CMD0                                 HW(SSP_CMD0)
+#define HWA_SSP_CMD0                                (0x80010000 + 0x10)
+#define HWT_SSP_CMD0                                HWIO_32_RW
+#define HWN_SSP_CMD0                                SSP_CMD0
+#define HWI_SSP_CMD0                                
+#define HW_SSP_CMD0_SET                             HW(SSP_CMD0_SET)
+#define HWA_SSP_CMD0_SET                            (HWA_SSP_CMD0 + 0x4)
+#define HWT_SSP_CMD0_SET                            HWIO_32_WO
+#define HWN_SSP_CMD0_SET                            SSP_CMD0
+#define HWI_SSP_CMD0_SET                            
+#define HW_SSP_CMD0_CLR                             HW(SSP_CMD0_CLR)
+#define HWA_SSP_CMD0_CLR                            (HWA_SSP_CMD0 + 0x8)
+#define HWT_SSP_CMD0_CLR                            HWIO_32_WO
+#define HWN_SSP_CMD0_CLR                            SSP_CMD0
+#define HWI_SSP_CMD0_CLR                            
+#define HW_SSP_CMD0_TOG                             HW(SSP_CMD0_TOG)
+#define HWA_SSP_CMD0_TOG                            (HWA_SSP_CMD0 + 0xc)
+#define HWT_SSP_CMD0_TOG                            HWIO_32_WO
+#define HWN_SSP_CMD0_TOG                            SSP_CMD0
+#define HWI_SSP_CMD0_TOG                            
+#define BP_SSP_CMD0_CMD                             0
+#define BM_SSP_CMD0_CMD                             0xff
+#define BV_SSP_CMD0_CMD__MMC_GO_IDLE_STATE          0x0
+#define BV_SSP_CMD0_CMD__MMC_SEND_OP_COND           0x1
+#define BV_SSP_CMD0_CMD__MMC_ALL_SEND_CID           0x2
+#define BV_SSP_CMD0_CMD__MMC_SET_RELATIVE_ADDR      0x3
+#define BV_SSP_CMD0_CMD__MMC_SET_DSR                0x4
+#define BV_SSP_CMD0_CMD__MMC_RESERVED_5             0x5
+#define BV_SSP_CMD0_CMD__MMC_SWITCH                 0x6
+#define BV_SSP_CMD0_CMD__MMC_SELECT_DESELECT_CARD   0x7
+#define BV_SSP_CMD0_CMD__MMC_SEND_EXT_CSD           0x8
+#define BV_SSP_CMD0_CMD__MMC_SEND_CSD               0x9
+#define BV_SSP_CMD0_CMD__MMC_SEND_CID               0xa
+#define BV_SSP_CMD0_CMD__MMC_READ_DAT_UNTIL_STOP    0xb
+#define BV_SSP_CMD0_CMD__MMC_STOP_TRANSMISSION      0xc
+#define BV_SSP_CMD0_CMD__MMC_SEND_STATUS            0xd
+#define BV_SSP_CMD0_CMD__MMC_BUSTEST_R              0xe
+#define BV_SSP_CMD0_CMD__MMC_GO_INACTIVE_STATE      0xf
+#define BV_SSP_CMD0_CMD__MMC_SET_BLOCKLEN           0x10
+#define BV_SSP_CMD0_CMD__MMC_READ_SINGLE_BLOCK      0x11
+#define BV_SSP_CMD0_CMD__MMC_READ_MULTIPLE_BLOCK    0x12
+#define BV_SSP_CMD0_CMD__MMC_BUSTEST_W              0x13
+#define BV_SSP_CMD0_CMD__MMC_WRITE_DAT_UNTIL_STOP   0x14
+#define BV_SSP_CMD0_CMD__MMC_SET_BLOCK_COUNT        0x17
+#define BV_SSP_CMD0_CMD__MMC_WRITE_BLOCK            0x18
+#define BV_SSP_CMD0_CMD__MMC_WRITE_MULTIPLE_BLOCK   0x19
+#define BV_SSP_CMD0_CMD__MMC_PROGRAM_CID            0x1a
+#define BV_SSP_CMD0_CMD__MMC_PROGRAM_CSD            0x1b
+#define BV_SSP_CMD0_CMD__MMC_SET_WRITE_PROT         0x1c
+#define BV_SSP_CMD0_CMD__MMC_CLR_WRITE_PROT         0x1d
+#define BV_SSP_CMD0_CMD__MMC_SEND_WRITE_PROT        0x1e
+#define BV_SSP_CMD0_CMD__MMC_ERASE_GROUP_START      0x23
+#define BV_SSP_CMD0_CMD__MMC_ERASE_GROUP_END        0x24
+#define BV_SSP_CMD0_CMD__MMC_ERASE                  0x26
+#define BV_SSP_CMD0_CMD__MMC_FAST_IO                0x27
+#define BV_SSP_CMD0_CMD__MMC_GO_IRQ_STATE           0x28
+#define BV_SSP_CMD0_CMD__MMC_LOCK_UNLOCK            0x2a
+#define BV_SSP_CMD0_CMD__MMC_APP_CMD                0x37
+#define BV_SSP_CMD0_CMD__MMC_GEN_CMD                0x38
+#define BV_SSP_CMD0_CMD__SD_GO_IDLE_STATE           0x0
+#define BV_SSP_CMD0_CMD__SD_ALL_SEND_CID            0x2
+#define BV_SSP_CMD0_CMD__SD_SEND_RELATIVE_ADDR      0x3
+#define BV_SSP_CMD0_CMD__SD_SET_DSR                 0x4
+#define BV_SSP_CMD0_CMD__SD_IO_SEND_OP_COND         0x5
+#define BV_SSP_CMD0_CMD__SD_SELECT_DESELECT_CARD    0x7
+#define BV_SSP_CMD0_CMD__SD_SEND_CSD                0x9
+#define BV_SSP_CMD0_CMD__SD_SEND_CID                0xa
+#define BV_SSP_CMD0_CMD__SD_STOP_TRANSMISSION       0xc
+#define BV_SSP_CMD0_CMD__SD_SEND_STATUS             0xd
+#define BV_SSP_CMD0_CMD__SD_GO_INACTIVE_STATE       0xf
+#define BV_SSP_CMD0_CMD__SD_SET_BLOCKLEN            0x10
+#define BV_SSP_CMD0_CMD__SD_READ_SINGLE_BLOCK       0x11
+#define BV_SSP_CMD0_CMD__SD_READ_MULTIPLE_BLOCK     0x12
+#define BV_SSP_CMD0_CMD__SD_WRITE_BLOCK             0x18
+#define BV_SSP_CMD0_CMD__SD_WRITE_MULTIPLE_BLOCK    0x19
+#define BV_SSP_CMD0_CMD__SD_PROGRAM_CSD             0x1b
+#define BV_SSP_CMD0_CMD__SD_SET_WRITE_PROT          0x1c
+#define BV_SSP_CMD0_CMD__SD_CLR_WRITE_PROT          0x1d
+#define BV_SSP_CMD0_CMD__SD_SEND_WRITE_PROT         0x1e
+#define BV_SSP_CMD0_CMD__SD_ERASE_WR_BLK_START      0x20
+#define BV_SSP_CMD0_CMD__SD_ERASE_WR_BLK_END        0x21
+#define BV_SSP_CMD0_CMD__SD_ERASE_GROUP_START       0x23
+#define BV_SSP_CMD0_CMD__SD_ERASE_GROUP_END         0x24
+#define BV_SSP_CMD0_CMD__SD_ERASE                   0x26
+#define BV_SSP_CMD0_CMD__SD_LOCK_UNLOCK             0x2a
+#define BV_SSP_CMD0_CMD__SD_IO_RW_DIRECT            0x34
+#define BV_SSP_CMD0_CMD__SD_IO_RW_EXTENDED          0x35
+#define BV_SSP_CMD0_CMD__SD_APP_CMD                 0x37
+#define BV_SSP_CMD0_CMD__SD_GEN_CMD                 0x38
+#define BF_SSP_CMD0_CMD(v)                          (((v) & 0xff) << 0)
+#define BFM_SSP_CMD0_CMD(v)                         BM_SSP_CMD0_CMD
+#define BF_SSP_CMD0_CMD_V(e)                        BF_SSP_CMD0_CMD(BV_SSP_CMD0_CMD__##e)
+#define BFM_SSP_CMD0_CMD_V(v)                       BM_SSP_CMD0_CMD
+
+#define HW_SSP_CMD1                 HW(SSP_CMD1)
+#define HWA_SSP_CMD1                (0x80010000 + 0x20)
+#define HWT_SSP_CMD1                HWIO_32_RW
+#define HWN_SSP_CMD1                SSP_CMD1
+#define HWI_SSP_CMD1                
+#define BP_SSP_CMD1_CMD_ARG         0
+#define BM_SSP_CMD1_CMD_ARG         0xffffffff
+#define BF_SSP_CMD1_CMD_ARG(v)      (((v) & 0xffffffff) << 0)
+#define BFM_SSP_CMD1_CMD_ARG(v)     BM_SSP_CMD1_CMD_ARG
+#define BF_SSP_CMD1_CMD_ARG_V(e)    BF_SSP_CMD1_CMD_ARG(BV_SSP_CMD1_CMD_ARG__##e)
+#define BFM_SSP_CMD1_CMD_ARG_V(v)   BM_SSP_CMD1_CMD_ARG
+
+#define HW_SSP_COMPREF                  HW(SSP_COMPREF)
+#define HWA_SSP_COMPREF                 (0x80010000 + 0x30)
+#define HWT_SSP_COMPREF                 HWIO_32_RW
+#define HWN_SSP_COMPREF                 SSP_COMPREF
+#define HWI_SSP_COMPREF                 
+#define BP_SSP_COMPREF_REFERENCE        0
+#define BM_SSP_COMPREF_REFERENCE        0xffffffff
+#define BF_SSP_COMPREF_REFERENCE(v)     (((v) & 0xffffffff) << 0)
+#define BFM_SSP_COMPREF_REFERENCE(v)    BM_SSP_COMPREF_REFERENCE
+#define BF_SSP_COMPREF_REFERENCE_V(e)   BF_SSP_COMPREF_REFERENCE(BV_SSP_COMPREF_REFERENCE__##e)
+#define BFM_SSP_COMPREF_REFERENCE_V(v)  BM_SSP_COMPREF_REFERENCE
+
+#define HW_SSP_COMPMASK             HW(SSP_COMPMASK)
+#define HWA_SSP_COMPMASK            (0x80010000 + 0x40)
+#define HWT_SSP_COMPMASK            HWIO_32_RW
+#define HWN_SSP_COMPMASK            SSP_COMPMASK
+#define HWI_SSP_COMPMASK            
+#define BP_SSP_COMPMASK_MASK        0
+#define BM_SSP_COMPMASK_MASK        0xffffffff
+#define BF_SSP_COMPMASK_MASK(v)     (((v) & 0xffffffff) << 0)
+#define BFM_SSP_COMPMASK_MASK(v)    BM_SSP_COMPMASK_MASK
+#define BF_SSP_COMPMASK_MASK_V(e)   BF_SSP_COMPMASK_MASK(BV_SSP_COMPMASK_MASK__##e)
+#define BFM_SSP_COMPMASK_MASK_V(v)  BM_SSP_COMPMASK_MASK
+
+#define HW_SSP_TIMING                       HW(SSP_TIMING)
+#define HWA_SSP_TIMING                      (0x80010000 + 0x50)
+#define HWT_SSP_TIMING                      HWIO_32_RW
+#define HWN_SSP_TIMING                      SSP_TIMING
+#define HWI_SSP_TIMING                      
+#define BP_SSP_TIMING_TIMEOUT               16
+#define BM_SSP_TIMING_TIMEOUT               0xffff0000
+#define BF_SSP_TIMING_TIMEOUT(v)            (((v) & 0xffff) << 16)
+#define BFM_SSP_TIMING_TIMEOUT(v)           BM_SSP_TIMING_TIMEOUT
+#define BF_SSP_TIMING_TIMEOUT_V(e)          BF_SSP_TIMING_TIMEOUT(BV_SSP_TIMING_TIMEOUT__##e)
+#define BFM_SSP_TIMING_TIMEOUT_V(v)         BM_SSP_TIMING_TIMEOUT
+#define BP_SSP_TIMING_CLOCK_DIVIDE          8
+#define BM_SSP_TIMING_CLOCK_DIVIDE          0xff00
+#define BF_SSP_TIMING_CLOCK_DIVIDE(v)       (((v) & 0xff) << 8)
+#define BFM_SSP_TIMING_CLOCK_DIVIDE(v)      BM_SSP_TIMING_CLOCK_DIVIDE
+#define BF_SSP_TIMING_CLOCK_DIVIDE_V(e)     BF_SSP_TIMING_CLOCK_DIVIDE(BV_SSP_TIMING_CLOCK_DIVIDE__##e)
+#define BFM_SSP_TIMING_CLOCK_DIVIDE_V(v)    BM_SSP_TIMING_CLOCK_DIVIDE
+#define BP_SSP_TIMING_CLOCK_RATE            0
+#define BM_SSP_TIMING_CLOCK_RATE            0xff
+#define BF_SSP_TIMING_CLOCK_RATE(v)         (((v) & 0xff) << 0)
+#define BFM_SSP_TIMING_CLOCK_RATE(v)        BM_SSP_TIMING_CLOCK_RATE
+#define BF_SSP_TIMING_CLOCK_RATE_V(e)       BF_SSP_TIMING_CLOCK_RATE(BV_SSP_TIMING_CLOCK_RATE__##e)
+#define BFM_SSP_TIMING_CLOCK_RATE_V(v)      BM_SSP_TIMING_CLOCK_RATE
+
+#define HW_SSP_CTRL1                            HW(SSP_CTRL1)
+#define HWA_SSP_CTRL1                           (0x80010000 + 0x60)
+#define HWT_SSP_CTRL1                           HWIO_32_RW
+#define HWN_SSP_CTRL1                           SSP_CTRL1
+#define HWI_SSP_CTRL1                           
+#define HW_SSP_CTRL1_SET                        HW(SSP_CTRL1_SET)
+#define HWA_SSP_CTRL1_SET                       (HWA_SSP_CTRL1 + 0x4)
+#define HWT_SSP_CTRL1_SET                       HWIO_32_WO
+#define HWN_SSP_CTRL1_SET                       SSP_CTRL1
+#define HWI_SSP_CTRL1_SET                       
+#define HW_SSP_CTRL1_CLR                        HW(SSP_CTRL1_CLR)
+#define HWA_SSP_CTRL1_CLR                       (HWA_SSP_CTRL1 + 0x8)
+#define HWT_SSP_CTRL1_CLR                       HWIO_32_WO
+#define HWN_SSP_CTRL1_CLR                       SSP_CTRL1
+#define HWI_SSP_CTRL1_CLR                       
+#define HW_SSP_CTRL1_TOG                        HW(SSP_CTRL1_TOG)
+#define HWA_SSP_CTRL1_TOG                       (HWA_SSP_CTRL1 + 0xc)
+#define HWT_SSP_CTRL1_TOG                       HWIO_32_WO
+#define HWN_SSP_CTRL1_TOG                       SSP_CTRL1
+#define HWI_SSP_CTRL1_TOG                       
+#define BP_SSP_CTRL1_SDIO_IRQ                   31
+#define BM_SSP_CTRL1_SDIO_IRQ                   0x80000000
+#define BF_SSP_CTRL1_SDIO_IRQ(v)                (((v) & 0x1) << 31)
+#define BFM_SSP_CTRL1_SDIO_IRQ(v)               BM_SSP_CTRL1_SDIO_IRQ
+#define BF_SSP_CTRL1_SDIO_IRQ_V(e)              BF_SSP_CTRL1_SDIO_IRQ(BV_SSP_CTRL1_SDIO_IRQ__##e)
+#define BFM_SSP_CTRL1_SDIO_IRQ_V(v)             BM_SSP_CTRL1_SDIO_IRQ
+#define BP_SSP_CTRL1_SDIO_IRQ_EN                30
+#define BM_SSP_CTRL1_SDIO_IRQ_EN                0x40000000
+#define BF_SSP_CTRL1_SDIO_IRQ_EN(v)             (((v) & 0x1) << 30)
+#define BFM_SSP_CTRL1_SDIO_IRQ_EN(v)            BM_SSP_CTRL1_SDIO_IRQ_EN
+#define BF_SSP_CTRL1_SDIO_IRQ_EN_V(e)           BF_SSP_CTRL1_SDIO_IRQ_EN(BV_SSP_CTRL1_SDIO_IRQ_EN__##e)
+#define BFM_SSP_CTRL1_SDIO_IRQ_EN_V(v)          BM_SSP_CTRL1_SDIO_IRQ_EN
+#define BP_SSP_CTRL1_RESP_ERR_IRQ               29
+#define BM_SSP_CTRL1_RESP_ERR_IRQ               0x20000000
+#define BF_SSP_CTRL1_RESP_ERR_IRQ(v)            (((v) & 0x1) << 29)
+#define BFM_SSP_CTRL1_RESP_ERR_IRQ(v)           BM_SSP_CTRL1_RESP_ERR_IRQ
+#define BF_SSP_CTRL1_RESP_ERR_IRQ_V(e)          BF_SSP_CTRL1_RESP_ERR_IRQ(BV_SSP_CTRL1_RESP_ERR_IRQ__##e)
+#define BFM_SSP_CTRL1_RESP_ERR_IRQ_V(v)         BM_SSP_CTRL1_RESP_ERR_IRQ
+#define BP_SSP_CTRL1_RESP_ERR_IRQ_EN            28
+#define BM_SSP_CTRL1_RESP_ERR_IRQ_EN            0x10000000
+#define BF_SSP_CTRL1_RESP_ERR_IRQ_EN(v)         (((v) & 0x1) << 28)
+#define BFM_SSP_CTRL1_RESP_ERR_IRQ_EN(v)        BM_SSP_CTRL1_RESP_ERR_IRQ_EN
+#define BF_SSP_CTRL1_RESP_ERR_IRQ_EN_V(e)       BF_SSP_CTRL1_RESP_ERR_IRQ_EN(BV_SSP_CTRL1_RESP_ERR_IRQ_EN__##e)
+#define BFM_SSP_CTRL1_RESP_ERR_IRQ_EN_V(v)      BM_SSP_CTRL1_RESP_ERR_IRQ_EN
+#define BP_SSP_CTRL1_RESP_TIMEOUT_IRQ           27
+#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ           0x8000000
+#define BF_SSP_CTRL1_RESP_TIMEOUT_IRQ(v)        (((v) & 0x1) << 27)
+#define BFM_SSP_CTRL1_RESP_TIMEOUT_IRQ(v)       BM_SSP_CTRL1_RESP_TIMEOUT_IRQ
+#define BF_SSP_CTRL1_RESP_TIMEOUT_IRQ_V(e)      BF_SSP_CTRL1_RESP_TIMEOUT_IRQ(BV_SSP_CTRL1_RESP_TIMEOUT_IRQ__##e)
+#define BFM_SSP_CTRL1_RESP_TIMEOUT_IRQ_V(v)     BM_SSP_CTRL1_RESP_TIMEOUT_IRQ
+#define BP_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN        26
+#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN        0x4000000
+#define BF_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN(v)     (((v) & 0x1) << 26)
+#define BFM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN(v)    BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN
+#define BF_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN_V(e)   BF_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN(BV_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN__##e)
+#define BFM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN_V(v)  BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN
+#define BP_SSP_CTRL1_DATA_TIMEOUT_IRQ           25
+#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ           0x2000000
+#define BF_SSP_CTRL1_DATA_TIMEOUT_IRQ(v)        (((v) & 0x1) << 25)
+#define BFM_SSP_CTRL1_DATA_TIMEOUT_IRQ(v)       BM_SSP_CTRL1_DATA_TIMEOUT_IRQ
+#define BF_SSP_CTRL1_DATA_TIMEOUT_IRQ_V(e)      BF_SSP_CTRL1_DATA_TIMEOUT_IRQ(BV_SSP_CTRL1_DATA_TIMEOUT_IRQ__##e)
+#define BFM_SSP_CTRL1_DATA_TIMEOUT_IRQ_V(v)     BM_SSP_CTRL1_DATA_TIMEOUT_IRQ
+#define BP_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN        24
+#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN        0x1000000
+#define BF_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN(v)     (((v) & 0x1) << 24)
+#define BFM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN(v)    BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN
+#define BF_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN_V(e)   BF_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN(BV_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN__##e)
+#define BFM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN_V(v)  BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN
+#define BP_SSP_CTRL1_DATA_CRC_IRQ               23
+#define BM_SSP_CTRL1_DATA_CRC_IRQ               0x800000
+#define BF_SSP_CTRL1_DATA_CRC_IRQ(v)            (((v) & 0x1) << 23)
+#define BFM_SSP_CTRL1_DATA_CRC_IRQ(v)           BM_SSP_CTRL1_DATA_CRC_IRQ
+#define BF_SSP_CTRL1_DATA_CRC_IRQ_V(e)          BF_SSP_CTRL1_DATA_CRC_IRQ(BV_SSP_CTRL1_DATA_CRC_IRQ__##e)
+#define BFM_SSP_CTRL1_DATA_CRC_IRQ_V(v)         BM_SSP_CTRL1_DATA_CRC_IRQ
+#define BP_SSP_CTRL1_DATA_CRC_IRQ_EN            22
+#define BM_SSP_CTRL1_DATA_CRC_IRQ_EN            0x400000
+#define BF_SSP_CTRL1_DATA_CRC_IRQ_EN(v)         (((v) & 0x1) << 22)
+#define BFM_SSP_CTRL1_DATA_CRC_IRQ_EN(v)        BM_SSP_CTRL1_DATA_CRC_IRQ_EN
+#define BF_SSP_CTRL1_DATA_CRC_IRQ_EN_V(e)       BF_SSP_CTRL1_DATA_CRC_IRQ_EN(BV_SSP_CTRL1_DATA_CRC_IRQ_EN__##e)
+#define BFM_SSP_CTRL1_DATA_CRC_IRQ_EN_V(v)      BM_SSP_CTRL1_DATA_CRC_IRQ_EN
+#define BP_SSP_CTRL1_XMIT_IRQ                   21
+#define BM_SSP_CTRL1_XMIT_IRQ                   0x200000
+#define BF_SSP_CTRL1_XMIT_IRQ(v)                (((v) & 0x1) << 21)
+#define BFM_SSP_CTRL1_XMIT_IRQ(v)               BM_SSP_CTRL1_XMIT_IRQ
+#define BF_SSP_CTRL1_XMIT_IRQ_V(e)              BF_SSP_CTRL1_XMIT_IRQ(BV_SSP_CTRL1_XMIT_IRQ__##e)
+#define BFM_SSP_CTRL1_XMIT_IRQ_V(v)             BM_SSP_CTRL1_XMIT_IRQ
+#define BP_SSP_CTRL1_XMIT_IRQ_EN                20
+#define BM_SSP_CTRL1_XMIT_IRQ_EN                0x100000
+#define BF_SSP_CTRL1_XMIT_IRQ_EN(v)             (((v) & 0x1) << 20)
+#define BFM_SSP_CTRL1_XMIT_IRQ_EN(v)            BM_SSP_CTRL1_XMIT_IRQ_EN
+#define BF_SSP_CTRL1_XMIT_IRQ_EN_V(e)           BF_SSP_CTRL1_XMIT_IRQ_EN(BV_SSP_CTRL1_XMIT_IRQ_EN__##e)
+#define BFM_SSP_CTRL1_XMIT_IRQ_EN_V(v)          BM_SSP_CTRL1_XMIT_IRQ_EN
+#define BP_SSP_CTRL1_RECV_IRQ                   19
+#define BM_SSP_CTRL1_RECV_IRQ                   0x80000
+#define BF_SSP_CTRL1_RECV_IRQ(v)                (((v) & 0x1) << 19)
+#define BFM_SSP_CTRL1_RECV_IRQ(v)               BM_SSP_CTRL1_RECV_IRQ
+#define BF_SSP_CTRL1_RECV_IRQ_V(e)              BF_SSP_CTRL1_RECV_IRQ(BV_SSP_CTRL1_RECV_IRQ__##e)
+#define BFM_SSP_CTRL1_RECV_IRQ_V(v)             BM_SSP_CTRL1_RECV_IRQ
+#define BP_SSP_CTRL1_RECV_IRQ_EN                18
+#define BM_SSP_CTRL1_RECV_IRQ_EN                0x40000
+#define BF_SSP_CTRL1_RECV_IRQ_EN(v)             (((v) & 0x1) << 18)
+#define BFM_SSP_CTRL1_RECV_IRQ_EN(v)            BM_SSP_CTRL1_RECV_IRQ_EN
+#define BF_SSP_CTRL1_RECV_IRQ_EN_V(e)           BF_SSP_CTRL1_RECV_IRQ_EN(BV_SSP_CTRL1_RECV_IRQ_EN__##e)
+#define BFM_SSP_CTRL1_RECV_IRQ_EN_V(v)          BM_SSP_CTRL1_RECV_IRQ_EN
+#define BP_SSP_CTRL1_RECV_TIMEOUT_IRQ           17
+#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ           0x20000
+#define BF_SSP_CTRL1_RECV_TIMEOUT_IRQ(v)        (((v) & 0x1) << 17)
+#define BFM_SSP_CTRL1_RECV_TIMEOUT_IRQ(v)       BM_SSP_CTRL1_RECV_TIMEOUT_IRQ
+#define BF_SSP_CTRL1_RECV_TIMEOUT_IRQ_V(e)      BF_SSP_CTRL1_RECV_TIMEOUT_IRQ(BV_SSP_CTRL1_RECV_TIMEOUT_IRQ__##e)
+#define BFM_SSP_CTRL1_RECV_TIMEOUT_IRQ_V(v)     BM_SSP_CTRL1_RECV_TIMEOUT_IRQ
+#define BP_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN        16
+#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN        0x10000
+#define BF_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN(v)     (((v) & 0x1) << 16)
+#define BFM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN(v)    BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN
+#define BF_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN_V(e)   BF_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN(BV_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN__##e)
+#define BFM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN_V(v)  BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN
+#define BP_SSP_CTRL1_RECV_OVRFLW_IRQ            15
+#define BM_SSP_CTRL1_RECV_OVRFLW_IRQ            0x8000
+#define BF_SSP_CTRL1_RECV_OVRFLW_IRQ(v)         (((v) & 0x1) << 15)
+#define BFM_SSP_CTRL1_RECV_OVRFLW_IRQ(v)        BM_SSP_CTRL1_RECV_OVRFLW_IRQ
+#define BF_SSP_CTRL1_RECV_OVRFLW_IRQ_V(e)       BF_SSP_CTRL1_RECV_OVRFLW_IRQ(BV_SSP_CTRL1_RECV_OVRFLW_IRQ__##e)
+#define BFM_SSP_CTRL1_RECV_OVRFLW_IRQ_V(v)      BM_SSP_CTRL1_RECV_OVRFLW_IRQ
+#define BP_SSP_CTRL1_RECV_OVRFLW_IRQ_EN         14
+#define BM_SSP_CTRL1_RECV_OVRFLW_IRQ_EN         0x4000
+#define BF_SSP_CTRL1_RECV_OVRFLW_IRQ_EN(v)      (((v) & 0x1) << 14)
+#define BFM_SSP_CTRL1_RECV_OVRFLW_IRQ_EN(v)     BM_SSP_CTRL1_RECV_OVRFLW_IRQ_EN
+#define BF_SSP_CTRL1_RECV_OVRFLW_IRQ_EN_V(e)    BF_SSP_CTRL1_RECV_OVRFLW_IRQ_EN(BV_SSP_CTRL1_RECV_OVRFLW_IRQ_EN__##e)
+#define BFM_SSP_CTRL1_RECV_OVRFLW_IRQ_EN_V(v)   BM_SSP_CTRL1_RECV_OVRFLW_IRQ_EN
+#define BP_SSP_CTRL1_DMA_ENABLE                 13
+#define BM_SSP_CTRL1_DMA_ENABLE                 0x2000
+#define BF_SSP_CTRL1_DMA_ENABLE(v)              (((v) & 0x1) << 13)
+#define BFM_SSP_CTRL1_DMA_ENABLE(v)             BM_SSP_CTRL1_DMA_ENABLE
+#define BF_SSP_CTRL1_DMA_ENABLE_V(e)            BF_SSP_CTRL1_DMA_ENABLE(BV_SSP_CTRL1_DMA_ENABLE__##e)
+#define BFM_SSP_CTRL1_DMA_ENABLE_V(v)           BM_SSP_CTRL1_DMA_ENABLE
+#define BP_SSP_CTRL1_LOOPBACK                   12
+#define BM_SSP_CTRL1_LOOPBACK                   0x1000
+#define BF_SSP_CTRL1_LOOPBACK(v)                (((v) & 0x1) << 12)
+#define BFM_SSP_CTRL1_LOOPBACK(v)               BM_SSP_CTRL1_LOOPBACK
+#define BF_SSP_CTRL1_LOOPBACK_V(e)              BF_SSP_CTRL1_LOOPBACK(BV_SSP_CTRL1_LOOPBACK__##e)
+#define BFM_SSP_CTRL1_LOOPBACK_V(v)             BM_SSP_CTRL1_LOOPBACK
+#define BP_SSP_CTRL1_SLAVE_OUT_DISABLE          11
+#define BM_SSP_CTRL1_SLAVE_OUT_DISABLE          0x800
+#define BF_SSP_CTRL1_SLAVE_OUT_DISABLE(v)       (((v) & 0x1) << 11)
+#define BFM_SSP_CTRL1_SLAVE_OUT_DISABLE(v)      BM_SSP_CTRL1_SLAVE_OUT_DISABLE
+#define BF_SSP_CTRL1_SLAVE_OUT_DISABLE_V(e)     BF_SSP_CTRL1_SLAVE_OUT_DISABLE(BV_SSP_CTRL1_SLAVE_OUT_DISABLE__##e)
+#define BFM_SSP_CTRL1_SLAVE_OUT_DISABLE_V(v)    BM_SSP_CTRL1_SLAVE_OUT_DISABLE
+#define BP_SSP_CTRL1_PHASE                      10
+#define BM_SSP_CTRL1_PHASE                      0x400
+#define BF_SSP_CTRL1_PHASE(v)                   (((v) & 0x1) << 10)
+#define BFM_SSP_CTRL1_PHASE(v)                  BM_SSP_CTRL1_PHASE
+#define BF_SSP_CTRL1_PHASE_V(e)                 BF_SSP_CTRL1_PHASE(BV_SSP_CTRL1_PHASE__##e)
+#define BFM_SSP_CTRL1_PHASE_V(v)                BM_SSP_CTRL1_PHASE
+#define BP_SSP_CTRL1_POLARITY                   9
+#define BM_SSP_CTRL1_POLARITY                   0x200
+#define BF_SSP_CTRL1_POLARITY(v)                (((v) & 0x1) << 9)
+#define BFM_SSP_CTRL1_POLARITY(v)               BM_SSP_CTRL1_POLARITY
+#define BF_SSP_CTRL1_POLARITY_V(e)              BF_SSP_CTRL1_POLARITY(BV_SSP_CTRL1_POLARITY__##e)
+#define BFM_SSP_CTRL1_POLARITY_V(v)             BM_SSP_CTRL1_POLARITY
+#define BP_SSP_CTRL1_SLAVE_MODE                 8
+#define BM_SSP_CTRL1_SLAVE_MODE                 0x100
+#define BF_SSP_CTRL1_SLAVE_MODE(v)              (((v) & 0x1) << 8)
+#define BFM_SSP_CTRL1_SLAVE_MODE(v)             BM_SSP_CTRL1_SLAVE_MODE
+#define BF_SSP_CTRL1_SLAVE_MODE_V(e)            BF_SSP_CTRL1_SLAVE_MODE(BV_SSP_CTRL1_SLAVE_MODE__##e)
+#define BFM_SSP_CTRL1_SLAVE_MODE_V(v)           BM_SSP_CTRL1_SLAVE_MODE
+#define BP_SSP_CTRL1_WORD_LENGTH                4
+#define BM_SSP_CTRL1_WORD_LENGTH                0xf0
+#define BV_SSP_CTRL1_WORD_LENGTH__RESERVED0     0x0
+#define BV_SSP_CTRL1_WORD_LENGTH__RESERVED1     0x1
+#define BV_SSP_CTRL1_WORD_LENGTH__RESERVED2     0x2
+#define BV_SSP_CTRL1_WORD_LENGTH__FOUR_BITS     0x3
+#define BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS    0x7
+#define BV_SSP_CTRL1_WORD_LENGTH__SIXTEEN_BITS  0xf
+#define BF_SSP_CTRL1_WORD_LENGTH(v)             (((v) & 0xf) << 4)
+#define BFM_SSP_CTRL1_WORD_LENGTH(v)            BM_SSP_CTRL1_WORD_LENGTH
+#define BF_SSP_CTRL1_WORD_LENGTH_V(e)           BF_SSP_CTRL1_WORD_LENGTH(BV_SSP_CTRL1_WORD_LENGTH__##e)
+#define BFM_SSP_CTRL1_WORD_LENGTH_V(v)          BM_SSP_CTRL1_WORD_LENGTH
+#define BP_SSP_CTRL1_SSP_MODE                   0
+#define BM_SSP_CTRL1_SSP_MODE                   0xf
+#define BV_SSP_CTRL1_SSP_MODE__SPI              0x0
+#define BV_SSP_CTRL1_SSP_MODE__SSI              0x1
+#define BV_SSP_CTRL1_SSP_MODE__MICROWIRE        0x2
+#define BV_SSP_CTRL1_SSP_MODE__SD_MMC           0x3
+#define BV_SSP_CTRL1_SSP_MODE__MS               0x4
+#define BF_SSP_CTRL1_SSP_MODE(v)                (((v) & 0xf) << 0)
+#define BFM_SSP_CTRL1_SSP_MODE(v)               BM_SSP_CTRL1_SSP_MODE
+#define BF_SSP_CTRL1_SSP_MODE_V(e)              BF_SSP_CTRL1_SSP_MODE(BV_SSP_CTRL1_SSP_MODE__##e)
+#define BFM_SSP_CTRL1_SSP_MODE_V(v)             BM_SSP_CTRL1_SSP_MODE
+
+#define HW_SSP_DATA             HW(SSP_DATA)
+#define HWA_SSP_DATA            (0x80010000 + 0x70)
+#define HWT_SSP_DATA            HWIO_32_RW
+#define HWN_SSP_DATA            SSP_DATA
+#define HWI_SSP_DATA            
+#define BP_SSP_DATA_DATA        0
+#define BM_SSP_DATA_DATA        0xffffffff
+#define BF_SSP_DATA_DATA(v)     (((v) & 0xffffffff) << 0)
+#define BFM_SSP_DATA_DATA(v)    BM_SSP_DATA_DATA
+#define BF_SSP_DATA_DATA_V(e)   BF_SSP_DATA_DATA(BV_SSP_DATA_DATA__##e)
+#define BFM_SSP_DATA_DATA_V(v)  BM_SSP_DATA_DATA
+
+#define HW_SSP_SDRESP0              HW(SSP_SDRESP0)
+#define HWA_SSP_SDRESP0             (0x80010000 + 0x80)
+#define HWT_SSP_SDRESP0             HWIO_32_RW
+#define HWN_SSP_SDRESP0             SSP_SDRESP0
+#define HWI_SSP_SDRESP0             
+#define BP_SSP_SDRESP0_RESP0        0
+#define BM_SSP_SDRESP0_RESP0        0xffffffff
+#define BF_SSP_SDRESP0_RESP0(v)     (((v) & 0xffffffff) << 0)
+#define BFM_SSP_SDRESP0_RESP0(v)    BM_SSP_SDRESP0_RESP0
+#define BF_SSP_SDRESP0_RESP0_V(e)   BF_SSP_SDRESP0_RESP0(BV_SSP_SDRESP0_RESP0__##e)
+#define BFM_SSP_SDRESP0_RESP0_V(v)  BM_SSP_SDRESP0_RESP0
+
+#define HW_SSP_SDRESP1              HW(SSP_SDRESP1)
+#define HWA_SSP_SDRESP1             (0x80010000 + 0x90)
+#define HWT_SSP_SDRESP1             HWIO_32_RW
+#define HWN_SSP_SDRESP1             SSP_SDRESP1
+#define HWI_SSP_SDRESP1             
+#define BP_SSP_SDRESP1_RESP1        0
+#define BM_SSP_SDRESP1_RESP1        0xffffffff
+#define BF_SSP_SDRESP1_RESP1(v)     (((v) & 0xffffffff) << 0)
+#define BFM_SSP_SDRESP1_RESP1(v)    BM_SSP_SDRESP1_RESP1
+#define BF_SSP_SDRESP1_RESP1_V(e)   BF_SSP_SDRESP1_RESP1(BV_SSP_SDRESP1_RESP1__##e)
+#define BFM_SSP_SDRESP1_RESP1_V(v)  BM_SSP_SDRESP1_RESP1
+
+#define HW_SSP_SDRESP2              HW(SSP_SDRESP2)
+#define HWA_SSP_SDRESP2             (0x80010000 + 0xa0)
+#define HWT_SSP_SDRESP2             HWIO_32_RW
+#define HWN_SSP_SDRESP2             SSP_SDRESP2
+#define HWI_SSP_SDRESP2             
+#define BP_SSP_SDRESP2_RESP2        0
+#define BM_SSP_SDRESP2_RESP2        0xffffffff
+#define BF_SSP_SDRESP2_RESP2(v)     (((v) & 0xffffffff) << 0)
+#define BFM_SSP_SDRESP2_RESP2(v)    BM_SSP_SDRESP2_RESP2
+#define BF_SSP_SDRESP2_RESP2_V(e)   BF_SSP_SDRESP2_RESP2(BV_SSP_SDRESP2_RESP2__##e)
+#define BFM_SSP_SDRESP2_RESP2_V(v)  BM_SSP_SDRESP2_RESP2
+
+#define HW_SSP_SDRESP3              HW(SSP_SDRESP3)
+#define HWA_SSP_SDRESP3             (0x80010000 + 0xb0)
+#define HWT_SSP_SDRESP3             HWIO_32_RW
+#define HWN_SSP_SDRESP3             SSP_SDRESP3
+#define HWI_SSP_SDRESP3             
+#define BP_SSP_SDRESP3_RESP3        0
+#define BM_SSP_SDRESP3_RESP3        0xffffffff
+#define BF_SSP_SDRESP3_RESP3(v)     (((v) & 0xffffffff) << 0)
+#define BFM_SSP_SDRESP3_RESP3(v)    BM_SSP_SDRESP3_RESP3
+#define BF_SSP_SDRESP3_RESP3_V(e)   BF_SSP_SDRESP3_RESP3(BV_SSP_SDRESP3_RESP3__##e)
+#define BFM_SSP_SDRESP3_RESP3_V(v)  BM_SSP_SDRESP3_RESP3
+
+#define HW_SSP_STATUS                           HW(SSP_STATUS)
+#define HWA_SSP_STATUS                          (0x80010000 + 0xc0)
+#define HWT_SSP_STATUS                          HWIO_32_RW
+#define HWN_SSP_STATUS                          SSP_STATUS
+#define HWI_SSP_STATUS                          
+#define BP_SSP_STATUS_PRESENT                   31
+#define BM_SSP_STATUS_PRESENT                   0x80000000
+#define BF_SSP_STATUS_PRESENT(v)                (((v) & 0x1) << 31)
+#define BFM_SSP_STATUS_PRESENT(v)               BM_SSP_STATUS_PRESENT
+#define BF_SSP_STATUS_PRESENT_V(e)              BF_SSP_STATUS_PRESENT(BV_SSP_STATUS_PRESENT__##e)
+#define BFM_SSP_STATUS_PRESENT_V(v)             BM_SSP_STATUS_PRESENT
+#define BP_SSP_STATUS_MS_PRESENT                30
+#define BM_SSP_STATUS_MS_PRESENT                0x40000000
+#define BF_SSP_STATUS_MS_PRESENT(v)             (((v) & 0x1) << 30)
+#define BFM_SSP_STATUS_MS_PRESENT(v)            BM_SSP_STATUS_MS_PRESENT
+#define BF_SSP_STATUS_MS_PRESENT_V(e)           BF_SSP_STATUS_MS_PRESENT(BV_SSP_STATUS_MS_PRESENT__##e)
+#define BFM_SSP_STATUS_MS_PRESENT_V(v)          BM_SSP_STATUS_MS_PRESENT
+#define BP_SSP_STATUS_SD_PRESENT                29
+#define BM_SSP_STATUS_SD_PRESENT                0x20000000
+#define BF_SSP_STATUS_SD_PRESENT(v)             (((v) & 0x1) << 29)
+#define BFM_SSP_STATUS_SD_PRESENT(v)            BM_SSP_STATUS_SD_PRESENT
+#define BF_SSP_STATUS_SD_PRESENT_V(e)           BF_SSP_STATUS_SD_PRESENT(BV_SSP_STATUS_SD_PRESENT__##e)
+#define BFM_SSP_STATUS_SD_PRESENT_V(v)          BM_SSP_STATUS_SD_PRESENT
+#define BP_SSP_STATUS_CARD_DETECT               28
+#define BM_SSP_STATUS_CARD_DETECT               0x10000000
+#define BF_SSP_STATUS_CARD_DETECT(v)            (((v) & 0x1) << 28)
+#define BFM_SSP_STATUS_CARD_DETECT(v)           BM_SSP_STATUS_CARD_DETECT
+#define BF_SSP_STATUS_CARD_DETECT_V(e)          BF_SSP_STATUS_CARD_DETECT(BV_SSP_STATUS_CARD_DETECT__##e)
+#define BFM_SSP_STATUS_CARD_DETECT_V(v)         BM_SSP_STATUS_CARD_DETECT
+#define BP_SSP_STATUS_RECV_COUNT                24
+#define BM_SSP_STATUS_RECV_COUNT                0xf000000
+#define BF_SSP_STATUS_RECV_COUNT(v)             (((v) & 0xf) << 24)
+#define BFM_SSP_STATUS_RECV_COUNT(v)            BM_SSP_STATUS_RECV_COUNT
+#define BF_SSP_STATUS_RECV_COUNT_V(e)           BF_SSP_STATUS_RECV_COUNT(BV_SSP_STATUS_RECV_COUNT__##e)
+#define BFM_SSP_STATUS_RECV_COUNT_V(v)          BM_SSP_STATUS_RECV_COUNT
+#define BP_SSP_STATUS_XMIT_COUNT                20
+#define BM_SSP_STATUS_XMIT_COUNT                0xf00000
+#define BF_SSP_STATUS_XMIT_COUNT(v)             (((v) & 0xf) << 20)
+#define BFM_SSP_STATUS_XMIT_COUNT(v)            BM_SSP_STATUS_XMIT_COUNT
+#define BF_SSP_STATUS_XMIT_COUNT_V(e)           BF_SSP_STATUS_XMIT_COUNT(BV_SSP_STATUS_XMIT_COUNT__##e)
+#define BFM_SSP_STATUS_XMIT_COUNT_V(v)          BM_SSP_STATUS_XMIT_COUNT
+#define BP_SSP_STATUS_DMAREQ                    19
+#define BM_SSP_STATUS_DMAREQ                    0x80000
+#define BF_SSP_STATUS_DMAREQ(v)                 (((v) & 0x1) << 19)
+#define BFM_SSP_STATUS_DMAREQ(v)                BM_SSP_STATUS_DMAREQ
+#define BF_SSP_STATUS_DMAREQ_V(e)               BF_SSP_STATUS_DMAREQ(BV_SSP_STATUS_DMAREQ__##e)
+#define BFM_SSP_STATUS_DMAREQ_V(v)              BM_SSP_STATUS_DMAREQ
+#define BP_SSP_STATUS_DMAEND                    18
+#define BM_SSP_STATUS_DMAEND                    0x40000
+#define BF_SSP_STATUS_DMAEND(v)                 (((v) & 0x1) << 18)
+#define BFM_SSP_STATUS_DMAEND(v)                BM_SSP_STATUS_DMAEND
+#define BF_SSP_STATUS_DMAEND_V(e)               BF_SSP_STATUS_DMAEND(BV_SSP_STATUS_DMAEND__##e)
+#define BFM_SSP_STATUS_DMAEND_V(v)              BM_SSP_STATUS_DMAEND
+#define BP_SSP_STATUS_SDIO_IRQ                  17
+#define BM_SSP_STATUS_SDIO_IRQ                  0x20000
+#define BF_SSP_STATUS_SDIO_IRQ(v)               (((v) & 0x1) << 17)
+#define BFM_SSP_STATUS_SDIO_IRQ(v)              BM_SSP_STATUS_SDIO_IRQ
+#define BF_SSP_STATUS_SDIO_IRQ_V(e)             BF_SSP_STATUS_SDIO_IRQ(BV_SSP_STATUS_SDIO_IRQ__##e)
+#define BFM_SSP_STATUS_SDIO_IRQ_V(v)            BM_SSP_STATUS_SDIO_IRQ
+#define BP_SSP_STATUS_RESP_CRC_ERR              16
+#define BM_SSP_STATUS_RESP_CRC_ERR              0x10000
+#define BF_SSP_STATUS_RESP_CRC_ERR(v)           (((v) & 0x1) << 16)
+#define BFM_SSP_STATUS_RESP_CRC_ERR(v)          BM_SSP_STATUS_RESP_CRC_ERR
+#define BF_SSP_STATUS_RESP_CRC_ERR_V(e)         BF_SSP_STATUS_RESP_CRC_ERR(BV_SSP_STATUS_RESP_CRC_ERR__##e)
+#define BFM_SSP_STATUS_RESP_CRC_ERR_V(v)        BM_SSP_STATUS_RESP_CRC_ERR
+#define BP_SSP_STATUS_RESP_ERR                  15
+#define BM_SSP_STATUS_RESP_ERR                  0x8000
+#define BF_SSP_STATUS_RESP_ERR(v)               (((v) & 0x1) << 15)
+#define BFM_SSP_STATUS_RESP_ERR(v)              BM_SSP_STATUS_RESP_ERR
+#define BF_SSP_STATUS_RESP_ERR_V(e)             BF_SSP_STATUS_RESP_ERR(BV_SSP_STATUS_RESP_ERR__##e)
+#define BFM_SSP_STATUS_RESP_ERR_V(v)            BM_SSP_STATUS_RESP_ERR
+#define BP_SSP_STATUS_RESP_TIMEOUT              14
+#define BM_SSP_STATUS_RESP_TIMEOUT              0x4000
+#define BF_SSP_STATUS_RESP_TIMEOUT(v)           (((v) & 0x1) << 14)
+#define BFM_SSP_STATUS_RESP_TIMEOUT(v)          BM_SSP_STATUS_RESP_TIMEOUT
+#define BF_SSP_STATUS_RESP_TIMEOUT_V(e)         BF_SSP_STATUS_RESP_TIMEOUT(BV_SSP_STATUS_RESP_TIMEOUT__##e)
+#define BFM_SSP_STATUS_RESP_TIMEOUT_V(v)        BM_SSP_STATUS_RESP_TIMEOUT
+#define BP_SSP_STATUS_DATA_CRC_ERR              13
+#define BM_SSP_STATUS_DATA_CRC_ERR              0x2000
+#define BF_SSP_STATUS_DATA_CRC_ERR(v)           (((v) & 0x1) << 13)
+#define BFM_SSP_STATUS_DATA_CRC_ERR(v)          BM_SSP_STATUS_DATA_CRC_ERR
+#define BF_SSP_STATUS_DATA_CRC_ERR_V(e)         BF_SSP_STATUS_DATA_CRC_ERR(BV_SSP_STATUS_DATA_CRC_ERR__##e)
+#define BFM_SSP_STATUS_DATA_CRC_ERR_V(v)        BM_SSP_STATUS_DATA_CRC_ERR
+#define BP_SSP_STATUS_TIMEOUT                   12
+#define BM_SSP_STATUS_TIMEOUT                   0x1000
+#define BF_SSP_STATUS_TIMEOUT(v)                (((v) & 0x1) << 12)
+#define BFM_SSP_STATUS_TIMEOUT(v)               BM_SSP_STATUS_TIMEOUT
+#define BF_SSP_STATUS_TIMEOUT_V(e)              BF_SSP_STATUS_TIMEOUT(BV_SSP_STATUS_TIMEOUT__##e)
+#define BFM_SSP_STATUS_TIMEOUT_V(v)             BM_SSP_STATUS_TIMEOUT
+#define BP_SSP_STATUS_RECV_TIMEOUT_STAT         11
+#define BM_SSP_STATUS_RECV_TIMEOUT_STAT         0x800
+#define BF_SSP_STATUS_RECV_TIMEOUT_STAT(v)      (((v) & 0x1) << 11)
+#define BFM_SSP_STATUS_RECV_TIMEOUT_STAT(v)     BM_SSP_STATUS_RECV_TIMEOUT_STAT
+#define BF_SSP_STATUS_RECV_TIMEOUT_STAT_V(e)    BF_SSP_STATUS_RECV_TIMEOUT_STAT(BV_SSP_STATUS_RECV_TIMEOUT_STAT__##e)
+#define BFM_SSP_STATUS_RECV_TIMEOUT_STAT_V(v)   BM_SSP_STATUS_RECV_TIMEOUT_STAT
+#define BP_SSP_STATUS_RECV_DATA_STAT            10
+#define BM_SSP_STATUS_RECV_DATA_STAT            0x400
+#define BF_SSP_STATUS_RECV_DATA_STAT(v)         (((v) & 0x1) << 10)
+#define BFM_SSP_STATUS_RECV_DATA_STAT(v)        BM_SSP_STATUS_RECV_DATA_STAT
+#define BF_SSP_STATUS_RECV_DATA_STAT_V(e)       BF_SSP_STATUS_RECV_DATA_STAT(BV_SSP_STATUS_RECV_DATA_STAT__##e)
+#define BFM_SSP_STATUS_RECV_DATA_STAT_V(v)      BM_SSP_STATUS_RECV_DATA_STAT
+#define BP_SSP_STATUS_RECV_OVRFLW               9
+#define BM_SSP_STATUS_RECV_OVRFLW               0x200
+#define BF_SSP_STATUS_RECV_OVRFLW(v)            (((v) & 0x1) << 9)
+#define BFM_SSP_STATUS_RECV_OVRFLW(v)           BM_SSP_STATUS_RECV_OVRFLW
+#define BF_SSP_STATUS_RECV_OVRFLW_V(e)          BF_SSP_STATUS_RECV_OVRFLW(BV_SSP_STATUS_RECV_OVRFLW__##e)
+#define BFM_SSP_STATUS_RECV_OVRFLW_V(v)         BM_SSP_STATUS_RECV_OVRFLW
+#define BP_SSP_STATUS_RECV_FULL                 8
+#define BM_SSP_STATUS_RECV_FULL                 0x100
+#define BF_SSP_STATUS_RECV_FULL(v)              (((v) & 0x1) << 8)
+#define BFM_SSP_STATUS_RECV_FULL(v)             BM_SSP_STATUS_RECV_FULL
+#define BF_SSP_STATUS_RECV_FULL_V(e)            BF_SSP_STATUS_RECV_FULL(BV_SSP_STATUS_RECV_FULL__##e)
+#define BFM_SSP_STATUS_RECV_FULL_V(v)           BM_SSP_STATUS_RECV_FULL
+#define BP_SSP_STATUS_RECV_NOT_EMPTY            7
+#define BM_SSP_STATUS_RECV_NOT_EMPTY            0x80
+#define BF_SSP_STATUS_RECV_NOT_EMPTY(v)         (((v) & 0x1) << 7)
+#define BFM_SSP_STATUS_RECV_NOT_EMPTY(v)        BM_SSP_STATUS_RECV_NOT_EMPTY
+#define BF_SSP_STATUS_RECV_NOT_EMPTY_V(e)       BF_SSP_STATUS_RECV_NOT_EMPTY(BV_SSP_STATUS_RECV_NOT_EMPTY__##e)
+#define BFM_SSP_STATUS_RECV_NOT_EMPTY_V(v)      BM_SSP_STATUS_RECV_NOT_EMPTY
+#define BP_SSP_STATUS_XMIT_NOT_FULL             6
+#define BM_SSP_STATUS_XMIT_NOT_FULL             0x40
+#define BF_SSP_STATUS_XMIT_NOT_FULL(v)          (((v) & 0x1) << 6)
+#define BFM_SSP_STATUS_XMIT_NOT_FULL(v)         BM_SSP_STATUS_XMIT_NOT_FULL
+#define BF_SSP_STATUS_XMIT_NOT_FULL_V(e)        BF_SSP_STATUS_XMIT_NOT_FULL(BV_SSP_STATUS_XMIT_NOT_FULL__##e)
+#define BFM_SSP_STATUS_XMIT_NOT_FULL_V(v)       BM_SSP_STATUS_XMIT_NOT_FULL
+#define BP_SSP_STATUS_XMIT_EMPTY                5
+#define BM_SSP_STATUS_XMIT_EMPTY                0x20
+#define BF_SSP_STATUS_XMIT_EMPTY(v)             (((v) & 0x1) << 5)
+#define BFM_SSP_STATUS_XMIT_EMPTY(v)            BM_SSP_STATUS_XMIT_EMPTY
+#define BF_SSP_STATUS_XMIT_EMPTY_V(e)           BF_SSP_STATUS_XMIT_EMPTY(BV_SSP_STATUS_XMIT_EMPTY__##e)
+#define BFM_SSP_STATUS_XMIT_EMPTY_V(v)          BM_SSP_STATUS_XMIT_EMPTY
+#define BP_SSP_STATUS_XMIT_UNDRFLW              4
+#define BM_SSP_STATUS_XMIT_UNDRFLW              0x10
+#define BF_SSP_STATUS_XMIT_UNDRFLW(v)           (((v) & 0x1) << 4)
+#define BFM_SSP_STATUS_XMIT_UNDRFLW(v)          BM_SSP_STATUS_XMIT_UNDRFLW
+#define BF_SSP_STATUS_XMIT_UNDRFLW_V(e)         BF_SSP_STATUS_XMIT_UNDRFLW(BV_SSP_STATUS_XMIT_UNDRFLW__##e)
+#define BFM_SSP_STATUS_XMIT_UNDRFLW_V(v)        BM_SSP_STATUS_XMIT_UNDRFLW
+#define BP_SSP_STATUS_CMD_BUSY                  3
+#define BM_SSP_STATUS_CMD_BUSY                  0x8
+#define BF_SSP_STATUS_CMD_BUSY(v)               (((v) & 0x1) << 3)
+#define BFM_SSP_STATUS_CMD_BUSY(v)              BM_SSP_STATUS_CMD_BUSY
+#define BF_SSP_STATUS_CMD_BUSY_V(e)             BF_SSP_STATUS_CMD_BUSY(BV_SSP_STATUS_CMD_BUSY__##e)
+#define BFM_SSP_STATUS_CMD_BUSY_V(v)            BM_SSP_STATUS_CMD_BUSY
+#define BP_SSP_STATUS_DATA_BUSY                 2
+#define BM_SSP_STATUS_DATA_BUSY                 0x4
+#define BF_SSP_STATUS_DATA_BUSY(v)              (((v) & 0x1) << 2)
+#define BFM_SSP_STATUS_DATA_BUSY(v)             BM_SSP_STATUS_DATA_BUSY
+#define BF_SSP_STATUS_DATA_BUSY_V(e)            BF_SSP_STATUS_DATA_BUSY(BV_SSP_STATUS_DATA_BUSY__##e)
+#define BFM_SSP_STATUS_DATA_BUSY_V(v)           BM_SSP_STATUS_DATA_BUSY
+#define BP_SSP_STATUS_DATA_XFER                 1
+#define BM_SSP_STATUS_DATA_XFER                 0x2
+#define BF_SSP_STATUS_DATA_XFER(v)              (((v) & 0x1) << 1)
+#define BFM_SSP_STATUS_DATA_XFER(v)             BM_SSP_STATUS_DATA_XFER
+#define BF_SSP_STATUS_DATA_XFER_V(e)            BF_SSP_STATUS_DATA_XFER(BV_SSP_STATUS_DATA_XFER__##e)
+#define BFM_SSP_STATUS_DATA_XFER_V(v)           BM_SSP_STATUS_DATA_XFER
+#define BP_SSP_STATUS_BUSY                      0
+#define BM_SSP_STATUS_BUSY                      0x1
+#define BF_SSP_STATUS_BUSY(v)                   (((v) & 0x1) << 0)
+#define BFM_SSP_STATUS_BUSY(v)                  BM_SSP_STATUS_BUSY
+#define BF_SSP_STATUS_BUSY_V(e)                 BF_SSP_STATUS_BUSY(BV_SSP_STATUS_BUSY__##e)
+#define BFM_SSP_STATUS_BUSY_V(v)                BM_SSP_STATUS_BUSY
+
+#define HW_SSP_DEBUG                        HW(SSP_DEBUG)
+#define HWA_SSP_DEBUG                       (0x80010000 + 0x100)
+#define HWT_SSP_DEBUG                       HWIO_32_RW
+#define HWN_SSP_DEBUG                       SSP_DEBUG
+#define HWI_SSP_DEBUG                       
+#define BP_SSP_DEBUG_DATACRC_ERR            28
+#define BM_SSP_DEBUG_DATACRC_ERR            0xf0000000
+#define BF_SSP_DEBUG_DATACRC_ERR(v)         (((v) & 0xf) << 28)
+#define BFM_SSP_DEBUG_DATACRC_ERR(v)        BM_SSP_DEBUG_DATACRC_ERR
+#define BF_SSP_DEBUG_DATACRC_ERR_V(e)       BF_SSP_DEBUG_DATACRC_ERR(BV_SSP_DEBUG_DATACRC_ERR__##e)
+#define BFM_SSP_DEBUG_DATACRC_ERR_V(v)      BM_SSP_DEBUG_DATACRC_ERR
+#define BP_SSP_DEBUG_DATA_STALL             27
+#define BM_SSP_DEBUG_DATA_STALL             0x8000000
+#define BF_SSP_DEBUG_DATA_STALL(v)          (((v) & 0x1) << 27)
+#define BFM_SSP_DEBUG_DATA_STALL(v)         BM_SSP_DEBUG_DATA_STALL
+#define BF_SSP_DEBUG_DATA_STALL_V(e)        BF_SSP_DEBUG_DATA_STALL(BV_SSP_DEBUG_DATA_STALL__##e)
+#define BFM_SSP_DEBUG_DATA_STALL_V(v)       BM_SSP_DEBUG_DATA_STALL
+#define BP_SSP_DEBUG_DAT_SM                 24
+#define BM_SSP_DEBUG_DAT_SM                 0x7000000
+#define BV_SSP_DEBUG_DAT_SM__DSM_IDLE       0x0
+#define BV_SSP_DEBUG_DAT_SM__DSM_START      0x1
+#define BV_SSP_DEBUG_DAT_SM__DSM_WORD       0x2
+#define BV_SSP_DEBUG_DAT_SM__DSM_CRC1       0x3
+#define BV_SSP_DEBUG_DAT_SM__DSM_CRC2       0x4
+#define BV_SSP_DEBUG_DAT_SM__DSM_END        0x5
+#define BV_SSP_DEBUG_DAT_SM__DSM_RXDLY      0x6
+#define BF_SSP_DEBUG_DAT_SM(v)              (((v) & 0x7) << 24)
+#define BFM_SSP_DEBUG_DAT_SM(v)             BM_SSP_DEBUG_DAT_SM
+#define BF_SSP_DEBUG_DAT_SM_V(e)            BF_SSP_DEBUG_DAT_SM(BV_SSP_DEBUG_DAT_SM__##e)
+#define BFM_SSP_DEBUG_DAT_SM_V(v)           BM_SSP_DEBUG_DAT_SM
+#define BP_SSP_DEBUG_MSTK_SM                20
+#define BM_SSP_DEBUG_MSTK_SM                0xf00000
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_IDLE     0x0
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_CKON     0x1
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS1      0x2
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_TPC      0x3
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS2      0x4
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_HDSHK    0x5
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS3      0x6
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_RW       0x7
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_CRC1     0x8
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_CRC2     0x9
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS0      0xa
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_DONE     0xb
+#define BF_SSP_DEBUG_MSTK_SM(v)             (((v) & 0xf) << 20)
+#define BFM_SSP_DEBUG_MSTK_SM(v)            BM_SSP_DEBUG_MSTK_SM
+#define BF_SSP_DEBUG_MSTK_SM_V(e)           BF_SSP_DEBUG_MSTK_SM(BV_SSP_DEBUG_MSTK_SM__##e)
+#define BFM_SSP_DEBUG_MSTK_SM_V(v)          BM_SSP_DEBUG_MSTK_SM
+#define BP_SSP_DEBUG_CMD_OE                 19
+#define BM_SSP_DEBUG_CMD_OE                 0x80000
+#define BF_SSP_DEBUG_CMD_OE(v)              (((v) & 0x1) << 19)
+#define BFM_SSP_DEBUG_CMD_OE(v)             BM_SSP_DEBUG_CMD_OE
+#define BF_SSP_DEBUG_CMD_OE_V(e)            BF_SSP_DEBUG_CMD_OE(BV_SSP_DEBUG_CMD_OE__##e)
+#define BFM_SSP_DEBUG_CMD_OE_V(v)           BM_SSP_DEBUG_CMD_OE
+#define BP_SSP_DEBUG_CMD_SM                 16
+#define BM_SSP_DEBUG_CMD_SM                 0x70000
+#define BV_SSP_DEBUG_CMD_SM__CSM_IDLE       0x0
+#define BV_SSP_DEBUG_CMD_SM__CSM_INDEX      0x1
+#define BV_SSP_DEBUG_CMD_SM__CSM_ARG        0x2
+#define BV_SSP_DEBUG_CMD_SM__CSM_CRC        0x3
+#define BF_SSP_DEBUG_CMD_SM(v)              (((v) & 0x7) << 16)
+#define BFM_SSP_DEBUG_CMD_SM(v)             BM_SSP_DEBUG_CMD_SM
+#define BF_SSP_DEBUG_CMD_SM_V(e)            BF_SSP_DEBUG_CMD_SM(BV_SSP_DEBUG_CMD_SM__##e)
+#define BFM_SSP_DEBUG_CMD_SM_V(v)           BM_SSP_DEBUG_CMD_SM
+#define BP_SSP_DEBUG_CLK_OE                 15
+#define BM_SSP_DEBUG_CLK_OE                 0x8000
+#define BF_SSP_DEBUG_CLK_OE(v)              (((v) & 0x1) << 15)
+#define BFM_SSP_DEBUG_CLK_OE(v)             BM_SSP_DEBUG_CLK_OE
+#define BF_SSP_DEBUG_CLK_OE_V(e)            BF_SSP_DEBUG_CLK_OE(BV_SSP_DEBUG_CLK_OE__##e)
+#define BFM_SSP_DEBUG_CLK_OE_V(v)           BM_SSP_DEBUG_CLK_OE
+#define BP_SSP_DEBUG_MMC_SM                 12
+#define BM_SSP_DEBUG_MMC_SM                 0x7000
+#define BV_SSP_DEBUG_MMC_SM__MMC_IDLE       0x0
+#define BV_SSP_DEBUG_MMC_SM__MMC_CMD        0x1
+#define BV_SSP_DEBUG_MMC_SM__MMC_TRC        0x2
+#define BV_SSP_DEBUG_MMC_SM__MMC_RESP       0x3
+#define BV_SSP_DEBUG_MMC_SM__MMC_RPRX       0x4
+#define BV_SSP_DEBUG_MMC_SM__MMC_TX         0x5
+#define BV_SSP_DEBUG_MMC_SM__MMC_CTOK       0x6
+#define BV_SSP_DEBUG_MMC_SM__MMC_RX         0x7
+#define BF_SSP_DEBUG_MMC_SM(v)              (((v) & 0x7) << 12)
+#define BFM_SSP_DEBUG_MMC_SM(v)             BM_SSP_DEBUG_MMC_SM
+#define BF_SSP_DEBUG_MMC_SM_V(e)            BF_SSP_DEBUG_MMC_SM(BV_SSP_DEBUG_MMC_SM__##e)
+#define BFM_SSP_DEBUG_MMC_SM_V(v)           BM_SSP_DEBUG_MMC_SM
+#define BP_SSP_DEBUG_DAT0_OE                11
+#define BM_SSP_DEBUG_DAT0_OE                0x800
+#define BF_SSP_DEBUG_DAT0_OE(v)             (((v) & 0x1) << 11)
+#define BFM_SSP_DEBUG_DAT0_OE(v)            BM_SSP_DEBUG_DAT0_OE
+#define BF_SSP_DEBUG_DAT0_OE_V(e)           BF_SSP_DEBUG_DAT0_OE(BV_SSP_DEBUG_DAT0_OE__##e)
+#define BFM_SSP_DEBUG_DAT0_OE_V(v)          BM_SSP_DEBUG_DAT0_OE
+#define BP_SSP_DEBUG_DAT321_OE              10
+#define BM_SSP_DEBUG_DAT321_OE              0x400
+#define BF_SSP_DEBUG_DAT321_OE(v)           (((v) & 0x1) << 10)
+#define BFM_SSP_DEBUG_DAT321_OE(v)          BM_SSP_DEBUG_DAT321_OE
+#define BF_SSP_DEBUG_DAT321_OE_V(e)         BF_SSP_DEBUG_DAT321_OE(BV_SSP_DEBUG_DAT321_OE__##e)
+#define BFM_SSP_DEBUG_DAT321_OE_V(v)        BM_SSP_DEBUG_DAT321_OE
+#define BP_SSP_DEBUG_SSP_CMD                9
+#define BM_SSP_DEBUG_SSP_CMD                0x200
+#define BF_SSP_DEBUG_SSP_CMD(v)             (((v) & 0x1) << 9)
+#define BFM_SSP_DEBUG_SSP_CMD(v)            BM_SSP_DEBUG_SSP_CMD
+#define BF_SSP_DEBUG_SSP_CMD_V(e)           BF_SSP_DEBUG_SSP_CMD(BV_SSP_DEBUG_SSP_CMD__##e)
+#define BFM_SSP_DEBUG_SSP_CMD_V(v)          BM_SSP_DEBUG_SSP_CMD
+#define BP_SSP_DEBUG_SSP_RESP               8
+#define BM_SSP_DEBUG_SSP_RESP               0x100
+#define BF_SSP_DEBUG_SSP_RESP(v)            (((v) & 0x1) << 8)
+#define BFM_SSP_DEBUG_SSP_RESP(v)           BM_SSP_DEBUG_SSP_RESP
+#define BF_SSP_DEBUG_SSP_RESP_V(e)          BF_SSP_DEBUG_SSP_RESP(BV_SSP_DEBUG_SSP_RESP__##e)
+#define BFM_SSP_DEBUG_SSP_RESP_V(v)         BM_SSP_DEBUG_SSP_RESP
+#define BP_SSP_DEBUG_SSP_TXD                4
+#define BM_SSP_DEBUG_SSP_TXD                0xf0
+#define BF_SSP_DEBUG_SSP_TXD(v)             (((v) & 0xf) << 4)
+#define BFM_SSP_DEBUG_SSP_TXD(v)            BM_SSP_DEBUG_SSP_TXD
+#define BF_SSP_DEBUG_SSP_TXD_V(e)           BF_SSP_DEBUG_SSP_TXD(BV_SSP_DEBUG_SSP_TXD__##e)
+#define BFM_SSP_DEBUG_SSP_TXD_V(v)          BM_SSP_DEBUG_SSP_TXD
+#define BP_SSP_DEBUG_SSP_RXD                0
+#define BM_SSP_DEBUG_SSP_RXD                0xf
+#define BF_SSP_DEBUG_SSP_RXD(v)             (((v) & 0xf) << 0)
+#define BFM_SSP_DEBUG_SSP_RXD(v)            BM_SSP_DEBUG_SSP_RXD
+#define BF_SSP_DEBUG_SSP_RXD_V(e)           BF_SSP_DEBUG_SSP_RXD(BV_SSP_DEBUG_SSP_RXD__##e)
+#define BFM_SSP_DEBUG_SSP_RXD_V(v)          BM_SSP_DEBUG_SSP_RXD
+
+#endif /* __HEADERGEN_STMP3600_SSP_H__*/
diff --git a/firmware/target/arm/imx233/regs/stmp3600/timrot.h b/firmware/target/arm/imx233/regs/stmp3600/timrot.h
new file mode 100644
index 0000000000..bbe82dc4a7
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3600/timrot.h
@@ -0,0 +1,397 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * stmp3600 version: 2.4.0
+ * stmp3600 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_STMP3600_TIMROT_H__
+#define __HEADERGEN_STMP3600_TIMROT_H__
+
+#define HW_TIMROT_ROTCTRL                       HW(TIMROT_ROTCTRL)
+#define HWA_TIMROT_ROTCTRL                      (0x80068000 + 0x0)
+#define HWT_TIMROT_ROTCTRL                      HWIO_32_RW
+#define HWN_TIMROT_ROTCTRL                      TIMROT_ROTCTRL
+#define HWI_TIMROT_ROTCTRL                      
+#define HW_TIMROT_ROTCTRL_SET                   HW(TIMROT_ROTCTRL_SET)
+#define HWA_TIMROT_ROTCTRL_SET                  (HWA_TIMROT_ROTCTRL + 0x4)
+#define HWT_TIMROT_ROTCTRL_SET                  HWIO_32_WO
+#define HWN_TIMROT_ROTCTRL_SET                  TIMROT_ROTCTRL
+#define HWI_TIMROT_ROTCTRL_SET                  
+#define HW_TIMROT_ROTCTRL_CLR                   HW(TIMROT_ROTCTRL_CLR)
+#define HWA_TIMROT_ROTCTRL_CLR                  (HWA_TIMROT_ROTCTRL + 0x8)
+#define HWT_TIMROT_ROTCTRL_CLR                  HWIO_32_WO
+#define HWN_TIMROT_ROTCTRL_CLR                  TIMROT_ROTCTRL
+#define HWI_TIMROT_ROTCTRL_CLR                  
+#define HW_TIMROT_ROTCTRL_TOG                   HW(TIMROT_ROTCTRL_TOG)
+#define HWA_TIMROT_ROTCTRL_TOG                  (HWA_TIMROT_ROTCTRL + 0xc)
+#define HWT_TIMROT_ROTCTRL_TOG                  HWIO_32_WO
+#define HWN_TIMROT_ROTCTRL_TOG                  TIMROT_ROTCTRL
+#define HWI_TIMROT_ROTCTRL_TOG                  
+#define BP_TIMROT_ROTCTRL_SFTRST                31
+#define BM_TIMROT_ROTCTRL_SFTRST                0x80000000
+#define BF_TIMROT_ROTCTRL_SFTRST(v)             (((v) & 0x1) << 31)
+#define BFM_TIMROT_ROTCTRL_SFTRST(v)            BM_TIMROT_ROTCTRL_SFTRST
+#define BF_TIMROT_ROTCTRL_SFTRST_V(e)           BF_TIMROT_ROTCTRL_SFTRST(BV_TIMROT_ROTCTRL_SFTRST__##e)
+#define BFM_TIMROT_ROTCTRL_SFTRST_V(v)          BM_TIMROT_ROTCTRL_SFTRST
+#define BP_TIMROT_ROTCTRL_CLKGATE               30
+#define BM_TIMROT_ROTCTRL_CLKGATE               0x40000000
+#define BF_TIMROT_ROTCTRL_CLKGATE(v)            (((v) & 0x1) << 30)
+#define BFM_TIMROT_ROTCTRL_CLKGATE(v)           BM_TIMROT_ROTCTRL_CLKGATE
+#define BF_TIMROT_ROTCTRL_CLKGATE_V(e)          BF_TIMROT_ROTCTRL_CLKGATE(BV_TIMROT_ROTCTRL_CLKGATE__##e)
+#define BFM_TIMROT_ROTCTRL_CLKGATE_V(v)         BM_TIMROT_ROTCTRL_CLKGATE
+#define BP_TIMROT_ROTCTRL_ROTARY_PRESENT        29
+#define BM_TIMROT_ROTCTRL_ROTARY_PRESENT        0x20000000
+#define BF_TIMROT_ROTCTRL_ROTARY_PRESENT(v)     (((v) & 0x1) << 29)
+#define BFM_TIMROT_ROTCTRL_ROTARY_PRESENT(v)    BM_TIMROT_ROTCTRL_ROTARY_PRESENT
+#define BF_TIMROT_ROTCTRL_ROTARY_PRESENT_V(e)   BF_TIMROT_ROTCTRL_ROTARY_PRESENT(BV_TIMROT_ROTCTRL_ROTARY_PRESENT__##e)
+#define BFM_TIMROT_ROTCTRL_ROTARY_PRESENT_V(v)  BM_TIMROT_ROTCTRL_ROTARY_PRESENT
+#define BP_TIMROT_ROTCTRL_TIM3_PRESENT          28
+#define BM_TIMROT_ROTCTRL_TIM3_PRESENT          0x10000000
+#define BF_TIMROT_ROTCTRL_TIM3_PRESENT(v)       (((v) & 0x1) << 28)
+#define BFM_TIMROT_ROTCTRL_TIM3_PRESENT(v)      BM_TIMROT_ROTCTRL_TIM3_PRESENT
+#define BF_TIMROT_ROTCTRL_TIM3_PRESENT_V(e)     BF_TIMROT_ROTCTRL_TIM3_PRESENT(BV_TIMROT_ROTCTRL_TIM3_PRESENT__##e)
+#define BFM_TIMROT_ROTCTRL_TIM3_PRESENT_V(v)    BM_TIMROT_ROTCTRL_TIM3_PRESENT
+#define BP_TIMROT_ROTCTRL_TIM2_PRESENT          27
+#define BM_TIMROT_ROTCTRL_TIM2_PRESENT          0x8000000
+#define BF_TIMROT_ROTCTRL_TIM2_PRESENT(v)       (((v) & 0x1) << 27)
+#define BFM_TIMROT_ROTCTRL_TIM2_PRESENT(v)      BM_TIMROT_ROTCTRL_TIM2_PRESENT
+#define BF_TIMROT_ROTCTRL_TIM2_PRESENT_V(e)     BF_TIMROT_ROTCTRL_TIM2_PRESENT(BV_TIMROT_ROTCTRL_TIM2_PRESENT__##e)
+#define BFM_TIMROT_ROTCTRL_TIM2_PRESENT_V(v)    BM_TIMROT_ROTCTRL_TIM2_PRESENT
+#define BP_TIMROT_ROTCTRL_TIM1_PRESENT          26
+#define BM_TIMROT_ROTCTRL_TIM1_PRESENT          0x4000000
+#define BF_TIMROT_ROTCTRL_TIM1_PRESENT(v)       (((v) & 0x1) << 26)
+#define BFM_TIMROT_ROTCTRL_TIM1_PRESENT(v)      BM_TIMROT_ROTCTRL_TIM1_PRESENT
+#define BF_TIMROT_ROTCTRL_TIM1_PRESENT_V(e)     BF_TIMROT_ROTCTRL_TIM1_PRESENT(BV_TIMROT_ROTCTRL_TIM1_PRESENT__##e)
+#define BFM_TIMROT_ROTCTRL_TIM1_PRESENT_V(v)    BM_TIMROT_ROTCTRL_TIM1_PRESENT
+#define BP_TIMROT_ROTCTRL_TIM0_PRESENT          25
+#define BM_TIMROT_ROTCTRL_TIM0_PRESENT          0x2000000
+#define BF_TIMROT_ROTCTRL_TIM0_PRESENT(v)       (((v) & 0x1) << 25)
+#define BFM_TIMROT_ROTCTRL_TIM0_PRESENT(v)      BM_TIMROT_ROTCTRL_TIM0_PRESENT
+#define BF_TIMROT_ROTCTRL_TIM0_PRESENT_V(e)     BF_TIMROT_ROTCTRL_TIM0_PRESENT(BV_TIMROT_ROTCTRL_TIM0_PRESENT__##e)
+#define BFM_TIMROT_ROTCTRL_TIM0_PRESENT_V(v)    BM_TIMROT_ROTCTRL_TIM0_PRESENT
+#define BP_TIMROT_ROTCTRL_STATE                 22
+#define BM_TIMROT_ROTCTRL_STATE                 0x1c00000
+#define BF_TIMROT_ROTCTRL_STATE(v)              (((v) & 0x7) << 22)
+#define BFM_TIMROT_ROTCTRL_STATE(v)             BM_TIMROT_ROTCTRL_STATE
+#define BF_TIMROT_ROTCTRL_STATE_V(e)            BF_TIMROT_ROTCTRL_STATE(BV_TIMROT_ROTCTRL_STATE__##e)
+#define BFM_TIMROT_ROTCTRL_STATE_V(v)           BM_TIMROT_ROTCTRL_STATE
+#define BP_TIMROT_ROTCTRL_DIVIDER               16
+#define BM_TIMROT_ROTCTRL_DIVIDER               0x3f0000
+#define BF_TIMROT_ROTCTRL_DIVIDER(v)            (((v) & 0x3f) << 16)
+#define BFM_TIMROT_ROTCTRL_DIVIDER(v)           BM_TIMROT_ROTCTRL_DIVIDER
+#define BF_TIMROT_ROTCTRL_DIVIDER_V(e)          BF_TIMROT_ROTCTRL_DIVIDER(BV_TIMROT_ROTCTRL_DIVIDER__##e)
+#define BFM_TIMROT_ROTCTRL_DIVIDER_V(v)         BM_TIMROT_ROTCTRL_DIVIDER
+#define BP_TIMROT_ROTCTRL_RELATIVE              12
+#define BM_TIMROT_ROTCTRL_RELATIVE              0x1000
+#define BF_TIMROT_ROTCTRL_RELATIVE(v)           (((v) & 0x1) << 12)
+#define BFM_TIMROT_ROTCTRL_RELATIVE(v)          BM_TIMROT_ROTCTRL_RELATIVE
+#define BF_TIMROT_ROTCTRL_RELATIVE_V(e)         BF_TIMROT_ROTCTRL_RELATIVE(BV_TIMROT_ROTCTRL_RELATIVE__##e)
+#define BFM_TIMROT_ROTCTRL_RELATIVE_V(v)        BM_TIMROT_ROTCTRL_RELATIVE
+#define BP_TIMROT_ROTCTRL_OVERSAMPLE            10
+#define BM_TIMROT_ROTCTRL_OVERSAMPLE            0xc00
+#define BV_TIMROT_ROTCTRL_OVERSAMPLE__8X        0x0
+#define BV_TIMROT_ROTCTRL_OVERSAMPLE__4X        0x1
+#define BV_TIMROT_ROTCTRL_OVERSAMPLE__2X        0x2
+#define BV_TIMROT_ROTCTRL_OVERSAMPLE__1X        0x3
+#define BF_TIMROT_ROTCTRL_OVERSAMPLE(v)         (((v) & 0x3) << 10)
+#define BFM_TIMROT_ROTCTRL_OVERSAMPLE(v)        BM_TIMROT_ROTCTRL_OVERSAMPLE
+#define BF_TIMROT_ROTCTRL_OVERSAMPLE_V(e)       BF_TIMROT_ROTCTRL_OVERSAMPLE(BV_TIMROT_ROTCTRL_OVERSAMPLE__##e)
+#define BFM_TIMROT_ROTCTRL_OVERSAMPLE_V(v)      BM_TIMROT_ROTCTRL_OVERSAMPLE
+#define BP_TIMROT_ROTCTRL_POLARITY_B            9
+#define BM_TIMROT_ROTCTRL_POLARITY_B            0x200
+#define BF_TIMROT_ROTCTRL_POLARITY_B(v)         (((v) & 0x1) << 9)
+#define BFM_TIMROT_ROTCTRL_POLARITY_B(v)        BM_TIMROT_ROTCTRL_POLARITY_B
+#define BF_TIMROT_ROTCTRL_POLARITY_B_V(e)       BF_TIMROT_ROTCTRL_POLARITY_B(BV_TIMROT_ROTCTRL_POLARITY_B__##e)
+#define BFM_TIMROT_ROTCTRL_POLARITY_B_V(v)      BM_TIMROT_ROTCTRL_POLARITY_B
+#define BP_TIMROT_ROTCTRL_POLARITY_A            8
+#define BM_TIMROT_ROTCTRL_POLARITY_A            0x100
+#define BF_TIMROT_ROTCTRL_POLARITY_A(v)         (((v) & 0x1) << 8)
+#define BFM_TIMROT_ROTCTRL_POLARITY_A(v)        BM_TIMROT_ROTCTRL_POLARITY_A
+#define BF_TIMROT_ROTCTRL_POLARITY_A_V(e)       BF_TIMROT_ROTCTRL_POLARITY_A(BV_TIMROT_ROTCTRL_POLARITY_A__##e)
+#define BFM_TIMROT_ROTCTRL_POLARITY_A_V(v)      BM_TIMROT_ROTCTRL_POLARITY_A
+#define BP_TIMROT_ROTCTRL_SELECT_B              4
+#define BM_TIMROT_ROTCTRL_SELECT_B              0x70
+#define BV_TIMROT_ROTCTRL_SELECT_B__NEVER_TICK  0x0
+#define BV_TIMROT_ROTCTRL_SELECT_B__PWM0        0x1
+#define BV_TIMROT_ROTCTRL_SELECT_B__PWM1        0x2
+#define BV_TIMROT_ROTCTRL_SELECT_B__PWM2        0x3
+#define BV_TIMROT_ROTCTRL_SELECT_B__PWM3        0x4
+#define BV_TIMROT_ROTCTRL_SELECT_B__PWM4        0x5
+#define BV_TIMROT_ROTCTRL_SELECT_B__ROTARYA     0x6
+#define BV_TIMROT_ROTCTRL_SELECT_B__ROTARYB     0x7
+#define BF_TIMROT_ROTCTRL_SELECT_B(v)           (((v) & 0x7) << 4)
+#define BFM_TIMROT_ROTCTRL_SELECT_B(v)          BM_TIMROT_ROTCTRL_SELECT_B
+#define BF_TIMROT_ROTCTRL_SELECT_B_V(e)         BF_TIMROT_ROTCTRL_SELECT_B(BV_TIMROT_ROTCTRL_SELECT_B__##e)
+#define BFM_TIMROT_ROTCTRL_SELECT_B_V(v)        BM_TIMROT_ROTCTRL_SELECT_B
+#define BP_TIMROT_ROTCTRL_SELECT_A              0
+#define BM_TIMROT_ROTCTRL_SELECT_A              0x7
+#define BV_TIMROT_ROTCTRL_SELECT_A__NEVER_TICK  0x0
+#define BV_TIMROT_ROTCTRL_SELECT_A__PWM0        0x1
+#define BV_TIMROT_ROTCTRL_SELECT_A__PWM1        0x2
+#define BV_TIMROT_ROTCTRL_SELECT_A__PWM2        0x3
+#define BV_TIMROT_ROTCTRL_SELECT_A__PWM3        0x4
+#define BV_TIMROT_ROTCTRL_SELECT_A__PWM4        0x5
+#define BV_TIMROT_ROTCTRL_SELECT_A__ROTARYA     0x6
+#define BV_TIMROT_ROTCTRL_SELECT_A__ROTARYB     0x7
+#define BF_TIMROT_ROTCTRL_SELECT_A(v)           (((v) & 0x7) << 0)
+#define BFM_TIMROT_ROTCTRL_SELECT_A(v)          BM_TIMROT_ROTCTRL_SELECT_A
+#define BF_TIMROT_ROTCTRL_SELECT_A_V(e)         BF_TIMROT_ROTCTRL_SELECT_A(BV_TIMROT_ROTCTRL_SELECT_A__##e)
+#define BFM_TIMROT_ROTCTRL_SELECT_A_V(v)        BM_TIMROT_ROTCTRL_SELECT_A
+
+#define HW_TIMROT_ROTCOUNT              HW(TIMROT_ROTCOUNT)
+#define HWA_TIMROT_ROTCOUNT             (0x80068000 + 0x10)
+#define HWT_TIMROT_ROTCOUNT             HWIO_32_RW
+#define HWN_TIMROT_ROTCOUNT             TIMROT_ROTCOUNT
+#define HWI_TIMROT_ROTCOUNT             
+#define BP_TIMROT_ROTCOUNT_UPDOWN       0
+#define BM_TIMROT_ROTCOUNT_UPDOWN       0xffff
+#define BF_TIMROT_ROTCOUNT_UPDOWN(v)    (((v) & 0xffff) << 0)
+#define BFM_TIMROT_ROTCOUNT_UPDOWN(v)   BM_TIMROT_ROTCOUNT_UPDOWN
+#define BF_TIMROT_ROTCOUNT_UPDOWN_V(e)  BF_TIMROT_ROTCOUNT_UPDOWN(BV_TIMROT_ROTCOUNT_UPDOWN__##e)
+#define BFM_TIMROT_ROTCOUNT_UPDOWN_V(v) BM_TIMROT_ROTCOUNT_UPDOWN
+
+#define HW_TIMROT_TIMCTRL3                          HW(TIMROT_TIMCTRL3)
+#define HWA_TIMROT_TIMCTRL3                         (0x80068000 + 0x80)
+#define HWT_TIMROT_TIMCTRL3                         HWIO_32_RW
+#define HWN_TIMROT_TIMCTRL3                         TIMROT_TIMCTRL3
+#define HWI_TIMROT_TIMCTRL3                         
+#define HW_TIMROT_TIMCTRL3_SET                      HW(TIMROT_TIMCTRL3_SET)
+#define HWA_TIMROT_TIMCTRL3_SET                     (HWA_TIMROT_TIMCTRL3 + 0x4)
+#define HWT_TIMROT_TIMCTRL3_SET                     HWIO_32_WO
+#define HWN_TIMROT_TIMCTRL3_SET                     TIMROT_TIMCTRL3
+#define HWI_TIMROT_TIMCTRL3_SET                     
+#define HW_TIMROT_TIMCTRL3_CLR                      HW(TIMROT_TIMCTRL3_CLR)
+#define HWA_TIMROT_TIMCTRL3_CLR                     (HWA_TIMROT_TIMCTRL3 + 0x8)
+#define HWT_TIMROT_TIMCTRL3_CLR                     HWIO_32_WO
+#define HWN_TIMROT_TIMCTRL3_CLR                     TIMROT_TIMCTRL3
+#define HWI_TIMROT_TIMCTRL3_CLR                     
+#define HW_TIMROT_TIMCTRL3_TOG                      HW(TIMROT_TIMCTRL3_TOG)
+#define HWA_TIMROT_TIMCTRL3_TOG                     (HWA_TIMROT_TIMCTRL3 + 0xc)
+#define HWT_TIMROT_TIMCTRL3_TOG                     HWIO_32_WO
+#define HWN_TIMROT_TIMCTRL3_TOG                     TIMROT_TIMCTRL3
+#define HWI_TIMROT_TIMCTRL3_TOG                     
+#define BP_TIMROT_TIMCTRL3_TEST_SIGNAL              16
+#define BM_TIMROT_TIMCTRL3_TEST_SIGNAL              0xf0000
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__NEVER_TICK  0x0
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM0        0x1
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM1        0x2
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM2        0x3
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM3        0x4
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM4        0x5
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__ROTARYA     0x6
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__ROTARYB     0x7
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__32KHZ_XTAL  0x8
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__8KHZ_XTAL   0x9
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__4KHZ_XTAL   0xa
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__1KHZ_XTAL   0xb
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__TICK_ALWAYS 0xc
+#define BF_TIMROT_TIMCTRL3_TEST_SIGNAL(v)           (((v) & 0xf) << 16)
+#define BFM_TIMROT_TIMCTRL3_TEST_SIGNAL(v)          BM_TIMROT_TIMCTRL3_TEST_SIGNAL
+#define BF_TIMROT_TIMCTRL3_TEST_SIGNAL_V(e)         BF_TIMROT_TIMCTRL3_TEST_SIGNAL(BV_TIMROT_TIMCTRL3_TEST_SIGNAL__##e)
+#define BFM_TIMROT_TIMCTRL3_TEST_SIGNAL_V(v)        BM_TIMROT_TIMCTRL3_TEST_SIGNAL
+#define BP_TIMROT_TIMCTRL3_IRQ                      15
+#define BM_TIMROT_TIMCTRL3_IRQ                      0x8000
+#define BF_TIMROT_TIMCTRL3_IRQ(v)                   (((v) & 0x1) << 15)
+#define BFM_TIMROT_TIMCTRL3_IRQ(v)                  BM_TIMROT_TIMCTRL3_IRQ
+#define BF_TIMROT_TIMCTRL3_IRQ_V(e)                 BF_TIMROT_TIMCTRL3_IRQ(BV_TIMROT_TIMCTRL3_IRQ__##e)
+#define BFM_TIMROT_TIMCTRL3_IRQ_V(v)                BM_TIMROT_TIMCTRL3_IRQ
+#define BP_TIMROT_TIMCTRL3_IRQ_EN                   14
+#define BM_TIMROT_TIMCTRL3_IRQ_EN                   0x4000
+#define BF_TIMROT_TIMCTRL3_IRQ_EN(v)                (((v) & 0x1) << 14)
+#define BFM_TIMROT_TIMCTRL3_IRQ_EN(v)               BM_TIMROT_TIMCTRL3_IRQ_EN
+#define BF_TIMROT_TIMCTRL3_IRQ_EN_V(e)              BF_TIMROT_TIMCTRL3_IRQ_EN(BV_TIMROT_TIMCTRL3_IRQ_EN__##e)
+#define BFM_TIMROT_TIMCTRL3_IRQ_EN_V(v)             BM_TIMROT_TIMCTRL3_IRQ_EN
+#define BP_TIMROT_TIMCTRL3_DUTY_VALID               10
+#define BM_TIMROT_TIMCTRL3_DUTY_VALID               0x400
+#define BF_TIMROT_TIMCTRL3_DUTY_VALID(v)            (((v) & 0x1) << 10)
+#define BFM_TIMROT_TIMCTRL3_DUTY_VALID(v)           BM_TIMROT_TIMCTRL3_DUTY_VALID
+#define BF_TIMROT_TIMCTRL3_DUTY_VALID_V(e)          BF_TIMROT_TIMCTRL3_DUTY_VALID(BV_TIMROT_TIMCTRL3_DUTY_VALID__##e)
+#define BFM_TIMROT_TIMCTRL3_DUTY_VALID_V(v)         BM_TIMROT_TIMCTRL3_DUTY_VALID
+#define BP_TIMROT_TIMCTRL3_DUTY_CYCLE               9
+#define BM_TIMROT_TIMCTRL3_DUTY_CYCLE               0x200
+#define BF_TIMROT_TIMCTRL3_DUTY_CYCLE(v)            (((v) & 0x1) << 9)
+#define BFM_TIMROT_TIMCTRL3_DUTY_CYCLE(v)           BM_TIMROT_TIMCTRL3_DUTY_CYCLE
+#define BF_TIMROT_TIMCTRL3_DUTY_CYCLE_V(e)          BF_TIMROT_TIMCTRL3_DUTY_CYCLE(BV_TIMROT_TIMCTRL3_DUTY_CYCLE__##e)
+#define BFM_TIMROT_TIMCTRL3_DUTY_CYCLE_V(v)         BM_TIMROT_TIMCTRL3_DUTY_CYCLE
+#define BP_TIMROT_TIMCTRL3_POLARITY                 8
+#define BM_TIMROT_TIMCTRL3_POLARITY                 0x100
+#define BF_TIMROT_TIMCTRL3_POLARITY(v)              (((v) & 0x1) << 8)
+#define BFM_TIMROT_TIMCTRL3_POLARITY(v)             BM_TIMROT_TIMCTRL3_POLARITY
+#define BF_TIMROT_TIMCTRL3_POLARITY_V(e)            BF_TIMROT_TIMCTRL3_POLARITY(BV_TIMROT_TIMCTRL3_POLARITY__##e)
+#define BFM_TIMROT_TIMCTRL3_POLARITY_V(v)           BM_TIMROT_TIMCTRL3_POLARITY
+#define BP_TIMROT_TIMCTRL3_UPDATE                   7
+#define BM_TIMROT_TIMCTRL3_UPDATE                   0x80
+#define BF_TIMROT_TIMCTRL3_UPDATE(v)                (((v) & 0x1) << 7)
+#define BFM_TIMROT_TIMCTRL3_UPDATE(v)               BM_TIMROT_TIMCTRL3_UPDATE
+#define BF_TIMROT_TIMCTRL3_UPDATE_V(e)              BF_TIMROT_TIMCTRL3_UPDATE(BV_TIMROT_TIMCTRL3_UPDATE__##e)
+#define BFM_TIMROT_TIMCTRL3_UPDATE_V(v)             BM_TIMROT_TIMCTRL3_UPDATE
+#define BP_TIMROT_TIMCTRL3_RELOAD                   6
+#define BM_TIMROT_TIMCTRL3_RELOAD                   0x40
+#define BF_TIMROT_TIMCTRL3_RELOAD(v)                (((v) & 0x1) << 6)
+#define BFM_TIMROT_TIMCTRL3_RELOAD(v)               BM_TIMROT_TIMCTRL3_RELOAD
+#define BF_TIMROT_TIMCTRL3_RELOAD_V(e)              BF_TIMROT_TIMCTRL3_RELOAD(BV_TIMROT_TIMCTRL3_RELOAD__##e)
+#define BFM_TIMROT_TIMCTRL3_RELOAD_V(v)             BM_TIMROT_TIMCTRL3_RELOAD
+#define BP_TIMROT_TIMCTRL3_PRESCALE                 4
+#define BM_TIMROT_TIMCTRL3_PRESCALE                 0x30
+#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_1       0x0
+#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_2       0x1
+#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_4       0x2
+#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_8       0x3
+#define BF_TIMROT_TIMCTRL3_PRESCALE(v)              (((v) & 0x3) << 4)
+#define BFM_TIMROT_TIMCTRL3_PRESCALE(v)             BM_TIMROT_TIMCTRL3_PRESCALE
+#define BF_TIMROT_TIMCTRL3_PRESCALE_V(e)            BF_TIMROT_TIMCTRL3_PRESCALE(BV_TIMROT_TIMCTRL3_PRESCALE__##e)
+#define BFM_TIMROT_TIMCTRL3_PRESCALE_V(v)           BM_TIMROT_TIMCTRL3_PRESCALE
+#define BP_TIMROT_TIMCTRL3_SELECT                   0
+#define BM_TIMROT_TIMCTRL3_SELECT                   0xf
+#define BV_TIMROT_TIMCTRL3_SELECT__NEVER_TICK       0x0
+#define BV_TIMROT_TIMCTRL3_SELECT__PWM0             0x1
+#define BV_TIMROT_TIMCTRL3_SELECT__PWM1             0x2
+#define BV_TIMROT_TIMCTRL3_SELECT__PWM2             0x3
+#define BV_TIMROT_TIMCTRL3_SELECT__PWM3             0x4
+#define BV_TIMROT_TIMCTRL3_SELECT__PWM4             0x5
+#define BV_TIMROT_TIMCTRL3_SELECT__ROTARYA          0x6
+#define BV_TIMROT_TIMCTRL3_SELECT__ROTARYB          0x7
+#define BV_TIMROT_TIMCTRL3_SELECT__32KHZ_XTAL       0x8
+#define BV_TIMROT_TIMCTRL3_SELECT__8KHZ_XTAL        0x9
+#define BV_TIMROT_TIMCTRL3_SELECT__4KHZ_XTAL        0xa
+#define BV_TIMROT_TIMCTRL3_SELECT__1KHZ_XTAL        0xb
+#define BV_TIMROT_TIMCTRL3_SELECT__TICK_ALWAYS      0xc
+#define BF_TIMROT_TIMCTRL3_SELECT(v)                (((v) & 0xf) << 0)
+#define BFM_TIMROT_TIMCTRL3_SELECT(v)               BM_TIMROT_TIMCTRL3_SELECT
+#define BF_TIMROT_TIMCTRL3_SELECT_V(e)              BF_TIMROT_TIMCTRL3_SELECT(BV_TIMROT_TIMCTRL3_SELECT__##e)
+#define BFM_TIMROT_TIMCTRL3_SELECT_V(v)             BM_TIMROT_TIMCTRL3_SELECT
+
+#define HW_TIMROT_TIMCOUNT3                         HW(TIMROT_TIMCOUNT3)
+#define HWA_TIMROT_TIMCOUNT3                        (0x80068000 + 0x90)
+#define HWT_TIMROT_TIMCOUNT3                        HWIO_32_RW
+#define HWN_TIMROT_TIMCOUNT3                        TIMROT_TIMCOUNT3
+#define HWI_TIMROT_TIMCOUNT3                        
+#define BP_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT       16
+#define BM_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT       0xffff0000
+#define BF_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT(v)    (((v) & 0xffff) << 16)
+#define BFM_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT(v)   BM_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT
+#define BF_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT_V(e)  BF_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT(BV_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT__##e)
+#define BFM_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT_V(v) BM_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT
+#define BP_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT        0
+#define BM_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT        0xffff
+#define BF_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT(v)     (((v) & 0xffff) << 0)
+#define BFM_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT(v)    BM_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT
+#define BF_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT_V(e)   BF_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT(BV_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT__##e)
+#define BFM_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT_V(v)  BM_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT
+
+#define HW_TIMROT_TIMCOUNTn(_n1)                HW(TIMROT_TIMCOUNTn(_n1))
+#define HWA_TIMROT_TIMCOUNTn(_n1)               (0x80068000 + 0x30 + (_n1) * 0x20)
+#define HWT_TIMROT_TIMCOUNTn(_n1)               HWIO_32_RW
+#define HWN_TIMROT_TIMCOUNTn(_n1)               TIMROT_TIMCOUNTn
+#define HWI_TIMROT_TIMCOUNTn(_n1)               (_n1)
+#define BP_TIMROT_TIMCOUNTn_RUNNING_COUNT       16
+#define BM_TIMROT_TIMCOUNTn_RUNNING_COUNT       0xffff0000
+#define BF_TIMROT_TIMCOUNTn_RUNNING_COUNT(v)    (((v) & 0xffff) << 16)
+#define BFM_TIMROT_TIMCOUNTn_RUNNING_COUNT(v)   BM_TIMROT_TIMCOUNTn_RUNNING_COUNT
+#define BF_TIMROT_TIMCOUNTn_RUNNING_COUNT_V(e)  BF_TIMROT_TIMCOUNTn_RUNNING_COUNT(BV_TIMROT_TIMCOUNTn_RUNNING_COUNT__##e)
+#define BFM_TIMROT_TIMCOUNTn_RUNNING_COUNT_V(v) BM_TIMROT_TIMCOUNTn_RUNNING_COUNT
+#define BP_TIMROT_TIMCOUNTn_FIXED_COUNT         0
+#define BM_TIMROT_TIMCOUNTn_FIXED_COUNT         0xffff
+#define BF_TIMROT_TIMCOUNTn_FIXED_COUNT(v)      (((v) & 0xffff) << 0)
+#define BFM_TIMROT_TIMCOUNTn_FIXED_COUNT(v)     BM_TIMROT_TIMCOUNTn_FIXED_COUNT
+#define BF_TIMROT_TIMCOUNTn_FIXED_COUNT_V(e)    BF_TIMROT_TIMCOUNTn_FIXED_COUNT(BV_TIMROT_TIMCOUNTn_FIXED_COUNT__##e)
+#define BFM_TIMROT_TIMCOUNTn_FIXED_COUNT_V(v)   BM_TIMROT_TIMCOUNTn_FIXED_COUNT
+
+#define HW_TIMROT_TIMCTRLn(_n1)                 HW(TIMROT_TIMCTRLn(_n1))
+#define HWA_TIMROT_TIMCTRLn(_n1)                (0x80068000 + 0x20 + (_n1) * 0x20)
+#define HWT_TIMROT_TIMCTRLn(_n1)                HWIO_32_RW
+#define HWN_TIMROT_TIMCTRLn(_n1)                TIMROT_TIMCTRLn
+#define HWI_TIMROT_TIMCTRLn(_n1)                (_n1)
+#define HW_TIMROT_TIMCTRLn_SET(_n1)             HW(TIMROT_TIMCTRLn_SET(_n1))
+#define HWA_TIMROT_TIMCTRLn_SET(_n1)            (HWA_TIMROT_TIMCTRLn(_n1) + 0x4)
+#define HWT_TIMROT_TIMCTRLn_SET(_n1)            HWIO_32_WO
+#define HWN_TIMROT_TIMCTRLn_SET(_n1)            TIMROT_TIMCTRLn
+#define HWI_TIMROT_TIMCTRLn_SET(_n1)            (_n1)
+#define HW_TIMROT_TIMCTRLn_CLR(_n1)             HW(TIMROT_TIMCTRLn_CLR(_n1))
+#define HWA_TIMROT_TIMCTRLn_CLR(_n1)            (HWA_TIMROT_TIMCTRLn(_n1) + 0x8)
+#define HWT_TIMROT_TIMCTRLn_CLR(_n1)            HWIO_32_WO
+#define HWN_TIMROT_TIMCTRLn_CLR(_n1)            TIMROT_TIMCTRLn
+#define HWI_TIMROT_TIMCTRLn_CLR(_n1)            (_n1)
+#define HW_TIMROT_TIMCTRLn_TOG(_n1)             HW(TIMROT_TIMCTRLn_TOG(_n1))
+#define HWA_TIMROT_TIMCTRLn_TOG(_n1)            (HWA_TIMROT_TIMCTRLn(_n1) + 0xc)
+#define HWT_TIMROT_TIMCTRLn_TOG(_n1)            HWIO_32_WO
+#define HWN_TIMROT_TIMCTRLn_TOG(_n1)            TIMROT_TIMCTRLn
+#define HWI_TIMROT_TIMCTRLn_TOG(_n1)            (_n1)
+#define BP_TIMROT_TIMCTRLn_IRQ                  15
+#define BM_TIMROT_TIMCTRLn_IRQ                  0x8000
+#define BF_TIMROT_TIMCTRLn_IRQ(v)               (((v) & 0x1) << 15)
+#define BFM_TIMROT_TIMCTRLn_IRQ(v)              BM_TIMROT_TIMCTRLn_IRQ
+#define BF_TIMROT_TIMCTRLn_IRQ_V(e)             BF_TIMROT_TIMCTRLn_IRQ(BV_TIMROT_TIMCTRLn_IRQ__##e)
+#define BFM_TIMROT_TIMCTRLn_IRQ_V(v)            BM_TIMROT_TIMCTRLn_IRQ
+#define BP_TIMROT_TIMCTRLn_IRQ_EN               14
+#define BM_TIMROT_TIMCTRLn_IRQ_EN               0x4000
+#define BF_TIMROT_TIMCTRLn_IRQ_EN(v)            (((v) & 0x1) << 14)
+#define BFM_TIMROT_TIMCTRLn_IRQ_EN(v)           BM_TIMROT_TIMCTRLn_IRQ_EN
+#define BF_TIMROT_TIMCTRLn_IRQ_EN_V(e)          BF_TIMROT_TIMCTRLn_IRQ_EN(BV_TIMROT_TIMCTRLn_IRQ_EN__##e)
+#define BFM_TIMROT_TIMCTRLn_IRQ_EN_V(v)         BM_TIMROT_TIMCTRLn_IRQ_EN
+#define BP_TIMROT_TIMCTRLn_POLARITY             8
+#define BM_TIMROT_TIMCTRLn_POLARITY             0x100
+#define BF_TIMROT_TIMCTRLn_POLARITY(v)          (((v) & 0x1) << 8)
+#define BFM_TIMROT_TIMCTRLn_POLARITY(v)         BM_TIMROT_TIMCTRLn_POLARITY
+#define BF_TIMROT_TIMCTRLn_POLARITY_V(e)        BF_TIMROT_TIMCTRLn_POLARITY(BV_TIMROT_TIMCTRLn_POLARITY__##e)
+#define BFM_TIMROT_TIMCTRLn_POLARITY_V(v)       BM_TIMROT_TIMCTRLn_POLARITY
+#define BP_TIMROT_TIMCTRLn_UPDATE               7
+#define BM_TIMROT_TIMCTRLn_UPDATE               0x80
+#define BF_TIMROT_TIMCTRLn_UPDATE(v)            (((v) & 0x1) << 7)
+#define BFM_TIMROT_TIMCTRLn_UPDATE(v)           BM_TIMROT_TIMCTRLn_UPDATE
+#define BF_TIMROT_TIMCTRLn_UPDATE_V(e)          BF_TIMROT_TIMCTRLn_UPDATE(BV_TIMROT_TIMCTRLn_UPDATE__##e)
+#define BFM_TIMROT_TIMCTRLn_UPDATE_V(v)         BM_TIMROT_TIMCTRLn_UPDATE
+#define BP_TIMROT_TIMCTRLn_RELOAD               6
+#define BM_TIMROT_TIMCTRLn_RELOAD               0x40
+#define BF_TIMROT_TIMCTRLn_RELOAD(v)            (((v) & 0x1) << 6)
+#define BFM_TIMROT_TIMCTRLn_RELOAD(v)           BM_TIMROT_TIMCTRLn_RELOAD
+#define BF_TIMROT_TIMCTRLn_RELOAD_V(e)          BF_TIMROT_TIMCTRLn_RELOAD(BV_TIMROT_TIMCTRLn_RELOAD__##e)
+#define BFM_TIMROT_TIMCTRLn_RELOAD_V(v)         BM_TIMROT_TIMCTRLn_RELOAD
+#define BP_TIMROT_TIMCTRLn_PRESCALE             4
+#define BM_TIMROT_TIMCTRLn_PRESCALE             0x30
+#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_1   0x0
+#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_2   0x1
+#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_4   0x2
+#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_8   0x3
+#define BF_TIMROT_TIMCTRLn_PRESCALE(v)          (((v) & 0x3) << 4)
+#define BFM_TIMROT_TIMCTRLn_PRESCALE(v)         BM_TIMROT_TIMCTRLn_PRESCALE
+#define BF_TIMROT_TIMCTRLn_PRESCALE_V(e)        BF_TIMROT_TIMCTRLn_PRESCALE(BV_TIMROT_TIMCTRLn_PRESCALE__##e)
+#define BFM_TIMROT_TIMCTRLn_PRESCALE_V(v)       BM_TIMROT_TIMCTRLn_PRESCALE
+#define BP_TIMROT_TIMCTRLn_SELECT               0
+#define BM_TIMROT_TIMCTRLn_SELECT               0xf
+#define BV_TIMROT_TIMCTRLn_SELECT__NEVER_TICK   0x0
+#define BV_TIMROT_TIMCTRLn_SELECT__PWM0         0x1
+#define BV_TIMROT_TIMCTRLn_SELECT__PWM1         0x2
+#define BV_TIMROT_TIMCTRLn_SELECT__PWM2         0x3
+#define BV_TIMROT_TIMCTRLn_SELECT__PWM3         0x4
+#define BV_TIMROT_TIMCTRLn_SELECT__PWM4         0x5
+#define BV_TIMROT_TIMCTRLn_SELECT__ROTARYA      0x6
+#define BV_TIMROT_TIMCTRLn_SELECT__ROTARYB      0x7
+#define BV_TIMROT_TIMCTRLn_SELECT__32KHZ_XTAL   0x8
+#define BV_TIMROT_TIMCTRLn_SELECT__8KHZ_XTAL    0x9
+#define BV_TIMROT_TIMCTRLn_SELECT__4KHZ_XTAL    0xa
+#define BV_TIMROT_TIMCTRLn_SELECT__1KHZ_XTAL    0xb
+#define BV_TIMROT_TIMCTRLn_SELECT__TICK_ALWAYS  0xc
+#define BF_TIMROT_TIMCTRLn_SELECT(v)            (((v) & 0xf) << 0)
+#define BFM_TIMROT_TIMCTRLn_SELECT(v)           BM_TIMROT_TIMCTRLn_SELECT
+#define BF_TIMROT_TIMCTRLn_SELECT_V(e)          BF_TIMROT_TIMCTRLn_SELECT(BV_TIMROT_TIMCTRLn_SELECT__##e)
+#define BFM_TIMROT_TIMCTRLn_SELECT_V(v)         BM_TIMROT_TIMCTRLn_SELECT
+
+#endif /* __HEADERGEN_STMP3600_TIMROT_H__*/
diff --git a/firmware/target/arm/imx233/regs/stmp3600/uartapp.h b/firmware/target/arm/imx233/regs/stmp3600/uartapp.h
new file mode 100644
index 0000000000..b59363a9da
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3600/uartapp.h
@@ -0,0 +1,662 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * stmp3600 version: 2.4.0
+ * stmp3600 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_STMP3600_UARTAPP_H__
+#define __HEADERGEN_STMP3600_UARTAPP_H__
+
+#define HW_UARTAPP_CTRL0                    HW(UARTAPP_CTRL0)
+#define HWA_UARTAPP_CTRL0                   (0x8006c000 + 0x0)
+#define HWT_UARTAPP_CTRL0                   HWIO_32_RW
+#define HWN_UARTAPP_CTRL0                   UARTAPP_CTRL0
+#define HWI_UARTAPP_CTRL0                   
+#define HW_UARTAPP_CTRL0_SET                HW(UARTAPP_CTRL0_SET)
+#define HWA_UARTAPP_CTRL0_SET               (HWA_UARTAPP_CTRL0 + 0x4)
+#define HWT_UARTAPP_CTRL0_SET               HWIO_32_WO
+#define HWN_UARTAPP_CTRL0_SET               UARTAPP_CTRL0
+#define HWI_UARTAPP_CTRL0_SET               
+#define HW_UARTAPP_CTRL0_CLR                HW(UARTAPP_CTRL0_CLR)
+#define HWA_UARTAPP_CTRL0_CLR               (HWA_UARTAPP_CTRL0 + 0x8)
+#define HWT_UARTAPP_CTRL0_CLR               HWIO_32_WO
+#define HWN_UARTAPP_CTRL0_CLR               UARTAPP_CTRL0
+#define HWI_UARTAPP_CTRL0_CLR               
+#define HW_UARTAPP_CTRL0_TOG                HW(UARTAPP_CTRL0_TOG)
+#define HWA_UARTAPP_CTRL0_TOG               (HWA_UARTAPP_CTRL0 + 0xc)
+#define HWT_UARTAPP_CTRL0_TOG               HWIO_32_WO
+#define HWN_UARTAPP_CTRL0_TOG               UARTAPP_CTRL0
+#define HWI_UARTAPP_CTRL0_TOG               
+#define BP_UARTAPP_CTRL0_SFTRST             31
+#define BM_UARTAPP_CTRL0_SFTRST             0x80000000
+#define BF_UARTAPP_CTRL0_SFTRST(v)          (((v) & 0x1) << 31)
+#define BFM_UARTAPP_CTRL0_SFTRST(v)         BM_UARTAPP_CTRL0_SFTRST
+#define BF_UARTAPP_CTRL0_SFTRST_V(e)        BF_UARTAPP_CTRL0_SFTRST(BV_UARTAPP_CTRL0_SFTRST__##e)
+#define BFM_UARTAPP_CTRL0_SFTRST_V(v)       BM_UARTAPP_CTRL0_SFTRST
+#define BP_UARTAPP_CTRL0_CLKGATE            30
+#define BM_UARTAPP_CTRL0_CLKGATE            0x40000000
+#define BF_UARTAPP_CTRL0_CLKGATE(v)         (((v) & 0x1) << 30)
+#define BFM_UARTAPP_CTRL0_CLKGATE(v)        BM_UARTAPP_CTRL0_CLKGATE
+#define BF_UARTAPP_CTRL0_CLKGATE_V(e)       BF_UARTAPP_CTRL0_CLKGATE(BV_UARTAPP_CTRL0_CLKGATE__##e)
+#define BFM_UARTAPP_CTRL0_CLKGATE_V(v)      BM_UARTAPP_CTRL0_CLKGATE
+#define BP_UARTAPP_CTRL0_RUN                28
+#define BM_UARTAPP_CTRL0_RUN                0x10000000
+#define BF_UARTAPP_CTRL0_RUN(v)             (((v) & 0x1) << 28)
+#define BFM_UARTAPP_CTRL0_RUN(v)            BM_UARTAPP_CTRL0_RUN
+#define BF_UARTAPP_CTRL0_RUN_V(e)           BF_UARTAPP_CTRL0_RUN(BV_UARTAPP_CTRL0_RUN__##e)
+#define BFM_UARTAPP_CTRL0_RUN_V(v)          BM_UARTAPP_CTRL0_RUN
+#define BP_UARTAPP_CTRL0_RX_SOURCE          25
+#define BM_UARTAPP_CTRL0_RX_SOURCE          0x2000000
+#define BF_UARTAPP_CTRL0_RX_SOURCE(v)       (((v) & 0x1) << 25)
+#define BFM_UARTAPP_CTRL0_RX_SOURCE(v)      BM_UARTAPP_CTRL0_RX_SOURCE
+#define BF_UARTAPP_CTRL0_RX_SOURCE_V(e)     BF_UARTAPP_CTRL0_RX_SOURCE(BV_UARTAPP_CTRL0_RX_SOURCE__##e)
+#define BFM_UARTAPP_CTRL0_RX_SOURCE_V(v)    BM_UARTAPP_CTRL0_RX_SOURCE
+#define BP_UARTAPP_CTRL0_RXTO_ENABLE        24
+#define BM_UARTAPP_CTRL0_RXTO_ENABLE        0x1000000
+#define BF_UARTAPP_CTRL0_RXTO_ENABLE(v)     (((v) & 0x1) << 24)
+#define BFM_UARTAPP_CTRL0_RXTO_ENABLE(v)    BM_UARTAPP_CTRL0_RXTO_ENABLE
+#define BF_UARTAPP_CTRL0_RXTO_ENABLE_V(e)   BF_UARTAPP_CTRL0_RXTO_ENABLE(BV_UARTAPP_CTRL0_RXTO_ENABLE__##e)
+#define BFM_UARTAPP_CTRL0_RXTO_ENABLE_V(v)  BM_UARTAPP_CTRL0_RXTO_ENABLE
+#define BP_UARTAPP_CTRL0_RXTIMEOUT          16
+#define BM_UARTAPP_CTRL0_RXTIMEOUT          0xff0000
+#define BF_UARTAPP_CTRL0_RXTIMEOUT(v)       (((v) & 0xff) << 16)
+#define BFM_UARTAPP_CTRL0_RXTIMEOUT(v)      BM_UARTAPP_CTRL0_RXTIMEOUT
+#define BF_UARTAPP_CTRL0_RXTIMEOUT_V(e)     BF_UARTAPP_CTRL0_RXTIMEOUT(BV_UARTAPP_CTRL0_RXTIMEOUT__##e)
+#define BFM_UARTAPP_CTRL0_RXTIMEOUT_V(v)    BM_UARTAPP_CTRL0_RXTIMEOUT
+#define BP_UARTAPP_CTRL0_XFER_COUNT         0
+#define BM_UARTAPP_CTRL0_XFER_COUNT         0xffff
+#define BF_UARTAPP_CTRL0_XFER_COUNT(v)      (((v) & 0xffff) << 0)
+#define BFM_UARTAPP_CTRL0_XFER_COUNT(v)     BM_UARTAPP_CTRL0_XFER_COUNT
+#define BF_UARTAPP_CTRL0_XFER_COUNT_V(e)    BF_UARTAPP_CTRL0_XFER_COUNT(BV_UARTAPP_CTRL0_XFER_COUNT__##e)
+#define BFM_UARTAPP_CTRL0_XFER_COUNT_V(v)   BM_UARTAPP_CTRL0_XFER_COUNT
+
+#define HW_UARTAPP_CTRL1                    HW(UARTAPP_CTRL1)
+#define HWA_UARTAPP_CTRL1                   (0x8006c000 + 0x10)
+#define HWT_UARTAPP_CTRL1                   HWIO_32_RW
+#define HWN_UARTAPP_CTRL1                   UARTAPP_CTRL1
+#define HWI_UARTAPP_CTRL1                   
+#define HW_UARTAPP_CTRL1_SET                HW(UARTAPP_CTRL1_SET)
+#define HWA_UARTAPP_CTRL1_SET               (HWA_UARTAPP_CTRL1 + 0x4)
+#define HWT_UARTAPP_CTRL1_SET               HWIO_32_WO
+#define HWN_UARTAPP_CTRL1_SET               UARTAPP_CTRL1
+#define HWI_UARTAPP_CTRL1_SET               
+#define HW_UARTAPP_CTRL1_CLR                HW(UARTAPP_CTRL1_CLR)
+#define HWA_UARTAPP_CTRL1_CLR               (HWA_UARTAPP_CTRL1 + 0x8)
+#define HWT_UARTAPP_CTRL1_CLR               HWIO_32_WO
+#define HWN_UARTAPP_CTRL1_CLR               UARTAPP_CTRL1
+#define HWI_UARTAPP_CTRL1_CLR               
+#define HW_UARTAPP_CTRL1_TOG                HW(UARTAPP_CTRL1_TOG)
+#define HWA_UARTAPP_CTRL1_TOG               (HWA_UARTAPP_CTRL1 + 0xc)
+#define HWT_UARTAPP_CTRL1_TOG               HWIO_32_WO
+#define HWN_UARTAPP_CTRL1_TOG               UARTAPP_CTRL1
+#define HWI_UARTAPP_CTRL1_TOG               
+#define BP_UARTAPP_CTRL1_RUN                28
+#define BM_UARTAPP_CTRL1_RUN                0x10000000
+#define BF_UARTAPP_CTRL1_RUN(v)             (((v) & 0x1) << 28)
+#define BFM_UARTAPP_CTRL1_RUN(v)            BM_UARTAPP_CTRL1_RUN
+#define BF_UARTAPP_CTRL1_RUN_V(e)           BF_UARTAPP_CTRL1_RUN(BV_UARTAPP_CTRL1_RUN__##e)
+#define BFM_UARTAPP_CTRL1_RUN_V(v)          BM_UARTAPP_CTRL1_RUN
+#define BP_UARTAPP_CTRL1_XFER_COUNT         0
+#define BM_UARTAPP_CTRL1_XFER_COUNT         0xffff
+#define BF_UARTAPP_CTRL1_XFER_COUNT(v)      (((v) & 0xffff) << 0)
+#define BFM_UARTAPP_CTRL1_XFER_COUNT(v)     BM_UARTAPP_CTRL1_XFER_COUNT
+#define BF_UARTAPP_CTRL1_XFER_COUNT_V(e)    BF_UARTAPP_CTRL1_XFER_COUNT(BV_UARTAPP_CTRL1_XFER_COUNT__##e)
+#define BFM_UARTAPP_CTRL1_XFER_COUNT_V(v)   BM_UARTAPP_CTRL1_XFER_COUNT
+
+#define HW_UARTAPP_CTRL2                            HW(UARTAPP_CTRL2)
+#define HWA_UARTAPP_CTRL2                           (0x8006c000 + 0x20)
+#define HWT_UARTAPP_CTRL2                           HWIO_32_RW
+#define HWN_UARTAPP_CTRL2                           UARTAPP_CTRL2
+#define HWI_UARTAPP_CTRL2                           
+#define HW_UARTAPP_CTRL2_SET                        HW(UARTAPP_CTRL2_SET)
+#define HWA_UARTAPP_CTRL2_SET                       (HWA_UARTAPP_CTRL2 + 0x4)
+#define HWT_UARTAPP_CTRL2_SET                       HWIO_32_WO
+#define HWN_UARTAPP_CTRL2_SET                       UARTAPP_CTRL2
+#define HWI_UARTAPP_CTRL2_SET                       
+#define HW_UARTAPP_CTRL2_CLR                        HW(UARTAPP_CTRL2_CLR)
+#define HWA_UARTAPP_CTRL2_CLR                       (HWA_UARTAPP_CTRL2 + 0x8)
+#define HWT_UARTAPP_CTRL2_CLR                       HWIO_32_WO
+#define HWN_UARTAPP_CTRL2_CLR                       UARTAPP_CTRL2
+#define HWI_UARTAPP_CTRL2_CLR                       
+#define HW_UARTAPP_CTRL2_TOG                        HW(UARTAPP_CTRL2_TOG)
+#define HWA_UARTAPP_CTRL2_TOG                       (HWA_UARTAPP_CTRL2 + 0xc)
+#define HWT_UARTAPP_CTRL2_TOG                       HWIO_32_WO
+#define HWN_UARTAPP_CTRL2_TOG                       UARTAPP_CTRL2
+#define HWI_UARTAPP_CTRL2_TOG                       
+#define BP_UARTAPP_CTRL2_INVERT_RTS                 31
+#define BM_UARTAPP_CTRL2_INVERT_RTS                 0x80000000
+#define BF_UARTAPP_CTRL2_INVERT_RTS(v)              (((v) & 0x1) << 31)
+#define BFM_UARTAPP_CTRL2_INVERT_RTS(v)             BM_UARTAPP_CTRL2_INVERT_RTS
+#define BF_UARTAPP_CTRL2_INVERT_RTS_V(e)            BF_UARTAPP_CTRL2_INVERT_RTS(BV_UARTAPP_CTRL2_INVERT_RTS__##e)
+#define BFM_UARTAPP_CTRL2_INVERT_RTS_V(v)           BM_UARTAPP_CTRL2_INVERT_RTS
+#define BP_UARTAPP_CTRL2_INVERT_CTS                 30
+#define BM_UARTAPP_CTRL2_INVERT_CTS                 0x40000000
+#define BF_UARTAPP_CTRL2_INVERT_CTS(v)              (((v) & 0x1) << 30)
+#define BFM_UARTAPP_CTRL2_INVERT_CTS(v)             BM_UARTAPP_CTRL2_INVERT_CTS
+#define BF_UARTAPP_CTRL2_INVERT_CTS_V(e)            BF_UARTAPP_CTRL2_INVERT_CTS(BV_UARTAPP_CTRL2_INVERT_CTS__##e)
+#define BFM_UARTAPP_CTRL2_INVERT_CTS_V(v)           BM_UARTAPP_CTRL2_INVERT_CTS
+#define BP_UARTAPP_CTRL2_INVERT_TX                  29
+#define BM_UARTAPP_CTRL2_INVERT_TX                  0x20000000
+#define BF_UARTAPP_CTRL2_INVERT_TX(v)               (((v) & 0x1) << 29)
+#define BFM_UARTAPP_CTRL2_INVERT_TX(v)              BM_UARTAPP_CTRL2_INVERT_TX
+#define BF_UARTAPP_CTRL2_INVERT_TX_V(e)             BF_UARTAPP_CTRL2_INVERT_TX(BV_UARTAPP_CTRL2_INVERT_TX__##e)
+#define BFM_UARTAPP_CTRL2_INVERT_TX_V(v)            BM_UARTAPP_CTRL2_INVERT_TX
+#define BP_UARTAPP_CTRL2_INVERT_RX                  28
+#define BM_UARTAPP_CTRL2_INVERT_RX                  0x10000000
+#define BF_UARTAPP_CTRL2_INVERT_RX(v)               (((v) & 0x1) << 28)
+#define BFM_UARTAPP_CTRL2_INVERT_RX(v)              BM_UARTAPP_CTRL2_INVERT_RX
+#define BF_UARTAPP_CTRL2_INVERT_RX_V(e)             BF_UARTAPP_CTRL2_INVERT_RX(BV_UARTAPP_CTRL2_INVERT_RX__##e)
+#define BFM_UARTAPP_CTRL2_INVERT_RX_V(v)            BM_UARTAPP_CTRL2_INVERT_RX
+#define BP_UARTAPP_CTRL2_DMAONERR                   26
+#define BM_UARTAPP_CTRL2_DMAONERR                   0x4000000
+#define BF_UARTAPP_CTRL2_DMAONERR(v)                (((v) & 0x1) << 26)
+#define BFM_UARTAPP_CTRL2_DMAONERR(v)               BM_UARTAPP_CTRL2_DMAONERR
+#define BF_UARTAPP_CTRL2_DMAONERR_V(e)              BF_UARTAPP_CTRL2_DMAONERR(BV_UARTAPP_CTRL2_DMAONERR__##e)
+#define BFM_UARTAPP_CTRL2_DMAONERR_V(v)             BM_UARTAPP_CTRL2_DMAONERR
+#define BP_UARTAPP_CTRL2_TXDMAE                     25
+#define BM_UARTAPP_CTRL2_TXDMAE                     0x2000000
+#define BF_UARTAPP_CTRL2_TXDMAE(v)                  (((v) & 0x1) << 25)
+#define BFM_UARTAPP_CTRL2_TXDMAE(v)                 BM_UARTAPP_CTRL2_TXDMAE
+#define BF_UARTAPP_CTRL2_TXDMAE_V(e)                BF_UARTAPP_CTRL2_TXDMAE(BV_UARTAPP_CTRL2_TXDMAE__##e)
+#define BFM_UARTAPP_CTRL2_TXDMAE_V(v)               BM_UARTAPP_CTRL2_TXDMAE
+#define BP_UARTAPP_CTRL2_RXDMAE                     24
+#define BM_UARTAPP_CTRL2_RXDMAE                     0x1000000
+#define BF_UARTAPP_CTRL2_RXDMAE(v)                  (((v) & 0x1) << 24)
+#define BFM_UARTAPP_CTRL2_RXDMAE(v)                 BM_UARTAPP_CTRL2_RXDMAE
+#define BF_UARTAPP_CTRL2_RXDMAE_V(e)                BF_UARTAPP_CTRL2_RXDMAE(BV_UARTAPP_CTRL2_RXDMAE__##e)
+#define BFM_UARTAPP_CTRL2_RXDMAE_V(v)               BM_UARTAPP_CTRL2_RXDMAE
+#define BP_UARTAPP_CTRL2_RXIFLSEL                   20
+#define BM_UARTAPP_CTRL2_RXIFLSEL                   0x700000
+#define BV_UARTAPP_CTRL2_RXIFLSEL__NOT_EMPTY        0x0
+#define BV_UARTAPP_CTRL2_RXIFLSEL__ONE_QUARTER      0x1
+#define BV_UARTAPP_CTRL2_RXIFLSEL__ONE_HALF         0x2
+#define BV_UARTAPP_CTRL2_RXIFLSEL__THREE_QUARTERS   0x3
+#define BV_UARTAPP_CTRL2_RXIFLSEL__SEVEN_EIGHTHS    0x4
+#define BV_UARTAPP_CTRL2_RXIFLSEL__INVALID5         0x5
+#define BV_UARTAPP_CTRL2_RXIFLSEL__INVALID6         0x6
+#define BV_UARTAPP_CTRL2_RXIFLSEL__INVALID7         0x7
+#define BF_UARTAPP_CTRL2_RXIFLSEL(v)                (((v) & 0x7) << 20)
+#define BFM_UARTAPP_CTRL2_RXIFLSEL(v)               BM_UARTAPP_CTRL2_RXIFLSEL
+#define BF_UARTAPP_CTRL2_RXIFLSEL_V(e)              BF_UARTAPP_CTRL2_RXIFLSEL(BV_UARTAPP_CTRL2_RXIFLSEL__##e)
+#define BFM_UARTAPP_CTRL2_RXIFLSEL_V(v)             BM_UARTAPP_CTRL2_RXIFLSEL
+#define BP_UARTAPP_CTRL2_TXIFLSEL                   16
+#define BM_UARTAPP_CTRL2_TXIFLSEL                   0x70000
+#define BV_UARTAPP_CTRL2_TXIFLSEL__EMPTY            0x0
+#define BV_UARTAPP_CTRL2_TXIFLSEL__ONE_QUARTER      0x1
+#define BV_UARTAPP_CTRL2_TXIFLSEL__ONE_HALF         0x2
+#define BV_UARTAPP_CTRL2_TXIFLSEL__THREE_QUARTERS   0x3
+#define BV_UARTAPP_CTRL2_TXIFLSEL__SEVEN_EIGHTHS    0x4
+#define BV_UARTAPP_CTRL2_TXIFLSEL__INVALID5         0x5
+#define BV_UARTAPP_CTRL2_TXIFLSEL__INVALID6         0x6
+#define BV_UARTAPP_CTRL2_TXIFLSEL__INVALID7         0x7
+#define BF_UARTAPP_CTRL2_TXIFLSEL(v)                (((v) & 0x7) << 16)
+#define BFM_UARTAPP_CTRL2_TXIFLSEL(v)               BM_UARTAPP_CTRL2_TXIFLSEL
+#define BF_UARTAPP_CTRL2_TXIFLSEL_V(e)              BF_UARTAPP_CTRL2_TXIFLSEL(BV_UARTAPP_CTRL2_TXIFLSEL__##e)
+#define BFM_UARTAPP_CTRL2_TXIFLSEL_V(v)             BM_UARTAPP_CTRL2_TXIFLSEL
+#define BP_UARTAPP_CTRL2_CTSEN                      15
+#define BM_UARTAPP_CTRL2_CTSEN                      0x8000
+#define BF_UARTAPP_CTRL2_CTSEN(v)                   (((v) & 0x1) << 15)
+#define BFM_UARTAPP_CTRL2_CTSEN(v)                  BM_UARTAPP_CTRL2_CTSEN
+#define BF_UARTAPP_CTRL2_CTSEN_V(e)                 BF_UARTAPP_CTRL2_CTSEN(BV_UARTAPP_CTRL2_CTSEN__##e)
+#define BFM_UARTAPP_CTRL2_CTSEN_V(v)                BM_UARTAPP_CTRL2_CTSEN
+#define BP_UARTAPP_CTRL2_RTSEN                      14
+#define BM_UARTAPP_CTRL2_RTSEN                      0x4000
+#define BF_UARTAPP_CTRL2_RTSEN(v)                   (((v) & 0x1) << 14)
+#define BFM_UARTAPP_CTRL2_RTSEN(v)                  BM_UARTAPP_CTRL2_RTSEN
+#define BF_UARTAPP_CTRL2_RTSEN_V(e)                 BF_UARTAPP_CTRL2_RTSEN(BV_UARTAPP_CTRL2_RTSEN__##e)
+#define BFM_UARTAPP_CTRL2_RTSEN_V(v)                BM_UARTAPP_CTRL2_RTSEN
+#define BP_UARTAPP_CTRL2_OUT2                       13
+#define BM_UARTAPP_CTRL2_OUT2                       0x2000
+#define BF_UARTAPP_CTRL2_OUT2(v)                    (((v) & 0x1) << 13)
+#define BFM_UARTAPP_CTRL2_OUT2(v)                   BM_UARTAPP_CTRL2_OUT2
+#define BF_UARTAPP_CTRL2_OUT2_V(e)                  BF_UARTAPP_CTRL2_OUT2(BV_UARTAPP_CTRL2_OUT2__##e)
+#define BFM_UARTAPP_CTRL2_OUT2_V(v)                 BM_UARTAPP_CTRL2_OUT2
+#define BP_UARTAPP_CTRL2_OUT1                       12
+#define BM_UARTAPP_CTRL2_OUT1                       0x1000
+#define BF_UARTAPP_CTRL2_OUT1(v)                    (((v) & 0x1) << 12)
+#define BFM_UARTAPP_CTRL2_OUT1(v)                   BM_UARTAPP_CTRL2_OUT1
+#define BF_UARTAPP_CTRL2_OUT1_V(e)                  BF_UARTAPP_CTRL2_OUT1(BV_UARTAPP_CTRL2_OUT1__##e)
+#define BFM_UARTAPP_CTRL2_OUT1_V(v)                 BM_UARTAPP_CTRL2_OUT1
+#define BP_UARTAPP_CTRL2_RTS                        11
+#define BM_UARTAPP_CTRL2_RTS                        0x800
+#define BF_UARTAPP_CTRL2_RTS(v)                     (((v) & 0x1) << 11)
+#define BFM_UARTAPP_CTRL2_RTS(v)                    BM_UARTAPP_CTRL2_RTS
+#define BF_UARTAPP_CTRL2_RTS_V(e)                   BF_UARTAPP_CTRL2_RTS(BV_UARTAPP_CTRL2_RTS__##e)
+#define BFM_UARTAPP_CTRL2_RTS_V(v)                  BM_UARTAPP_CTRL2_RTS
+#define BP_UARTAPP_CTRL2_DTR                        10
+#define BM_UARTAPP_CTRL2_DTR                        0x400
+#define BF_UARTAPP_CTRL2_DTR(v)                     (((v) & 0x1) << 10)
+#define BFM_UARTAPP_CTRL2_DTR(v)                    BM_UARTAPP_CTRL2_DTR
+#define BF_UARTAPP_CTRL2_DTR_V(e)                   BF_UARTAPP_CTRL2_DTR(BV_UARTAPP_CTRL2_DTR__##e)
+#define BFM_UARTAPP_CTRL2_DTR_V(v)                  BM_UARTAPP_CTRL2_DTR
+#define BP_UARTAPP_CTRL2_RXE                        9
+#define BM_UARTAPP_CTRL2_RXE                        0x200
+#define BF_UARTAPP_CTRL2_RXE(v)                     (((v) & 0x1) << 9)
+#define BFM_UARTAPP_CTRL2_RXE(v)                    BM_UARTAPP_CTRL2_RXE
+#define BF_UARTAPP_CTRL2_RXE_V(e)                   BF_UARTAPP_CTRL2_RXE(BV_UARTAPP_CTRL2_RXE__##e)
+#define BFM_UARTAPP_CTRL2_RXE_V(v)                  BM_UARTAPP_CTRL2_RXE
+#define BP_UARTAPP_CTRL2_TXE                        8
+#define BM_UARTAPP_CTRL2_TXE                        0x100
+#define BF_UARTAPP_CTRL2_TXE(v)                     (((v) & 0x1) << 8)
+#define BFM_UARTAPP_CTRL2_TXE(v)                    BM_UARTAPP_CTRL2_TXE
+#define BF_UARTAPP_CTRL2_TXE_V(e)                   BF_UARTAPP_CTRL2_TXE(BV_UARTAPP_CTRL2_TXE__##e)
+#define BFM_UARTAPP_CTRL2_TXE_V(v)                  BM_UARTAPP_CTRL2_TXE
+#define BP_UARTAPP_CTRL2_LBE                        7
+#define BM_UARTAPP_CTRL2_LBE                        0x80
+#define BF_UARTAPP_CTRL2_LBE(v)                     (((v) & 0x1) << 7)
+#define BFM_UARTAPP_CTRL2_LBE(v)                    BM_UARTAPP_CTRL2_LBE
+#define BF_UARTAPP_CTRL2_LBE_V(e)                   BF_UARTAPP_CTRL2_LBE(BV_UARTAPP_CTRL2_LBE__##e)
+#define BFM_UARTAPP_CTRL2_LBE_V(v)                  BM_UARTAPP_CTRL2_LBE
+#define BP_UARTAPP_CTRL2_SIRLP                      2
+#define BM_UARTAPP_CTRL2_SIRLP                      0x4
+#define BF_UARTAPP_CTRL2_SIRLP(v)                   (((v) & 0x1) << 2)
+#define BFM_UARTAPP_CTRL2_SIRLP(v)                  BM_UARTAPP_CTRL2_SIRLP
+#define BF_UARTAPP_CTRL2_SIRLP_V(e)                 BF_UARTAPP_CTRL2_SIRLP(BV_UARTAPP_CTRL2_SIRLP__##e)
+#define BFM_UARTAPP_CTRL2_SIRLP_V(v)                BM_UARTAPP_CTRL2_SIRLP
+#define BP_UARTAPP_CTRL2_SIREN                      1
+#define BM_UARTAPP_CTRL2_SIREN                      0x2
+#define BF_UARTAPP_CTRL2_SIREN(v)                   (((v) & 0x1) << 1)
+#define BFM_UARTAPP_CTRL2_SIREN(v)                  BM_UARTAPP_CTRL2_SIREN
+#define BF_UARTAPP_CTRL2_SIREN_V(e)                 BF_UARTAPP_CTRL2_SIREN(BV_UARTAPP_CTRL2_SIREN__##e)
+#define BFM_UARTAPP_CTRL2_SIREN_V(v)                BM_UARTAPP_CTRL2_SIREN
+#define BP_UARTAPP_CTRL2_UARTEN                     0
+#define BM_UARTAPP_CTRL2_UARTEN                     0x1
+#define BF_UARTAPP_CTRL2_UARTEN(v)                  (((v) & 0x1) << 0)
+#define BFM_UARTAPP_CTRL2_UARTEN(v)                 BM_UARTAPP_CTRL2_UARTEN
+#define BF_UARTAPP_CTRL2_UARTEN_V(e)                BF_UARTAPP_CTRL2_UARTEN(BV_UARTAPP_CTRL2_UARTEN__##e)
+#define BFM_UARTAPP_CTRL2_UARTEN_V(v)               BM_UARTAPP_CTRL2_UARTEN
+
+#define HW_UARTAPP_LINECTRL                     HW(UARTAPP_LINECTRL)
+#define HWA_UARTAPP_LINECTRL                    (0x8006c000 + 0x30)
+#define HWT_UARTAPP_LINECTRL                    HWIO_32_RW
+#define HWN_UARTAPP_LINECTRL                    UARTAPP_LINECTRL
+#define HWI_UARTAPP_LINECTRL                    
+#define HW_UARTAPP_LINECTRL_SET                 HW(UARTAPP_LINECTRL_SET)
+#define HWA_UARTAPP_LINECTRL_SET                (HWA_UARTAPP_LINECTRL + 0x4)
+#define HWT_UARTAPP_LINECTRL_SET                HWIO_32_WO
+#define HWN_UARTAPP_LINECTRL_SET                UARTAPP_LINECTRL
+#define HWI_UARTAPP_LINECTRL_SET                
+#define HW_UARTAPP_LINECTRL_CLR                 HW(UARTAPP_LINECTRL_CLR)
+#define HWA_UARTAPP_LINECTRL_CLR                (HWA_UARTAPP_LINECTRL + 0x8)
+#define HWT_UARTAPP_LINECTRL_CLR                HWIO_32_WO
+#define HWN_UARTAPP_LINECTRL_CLR                UARTAPP_LINECTRL
+#define HWI_UARTAPP_LINECTRL_CLR                
+#define HW_UARTAPP_LINECTRL_TOG                 HW(UARTAPP_LINECTRL_TOG)
+#define HWA_UARTAPP_LINECTRL_TOG                (HWA_UARTAPP_LINECTRL + 0xc)
+#define HWT_UARTAPP_LINECTRL_TOG                HWIO_32_WO
+#define HWN_UARTAPP_LINECTRL_TOG                UARTAPP_LINECTRL
+#define HWI_UARTAPP_LINECTRL_TOG                
+#define BP_UARTAPP_LINECTRL_BAUD_DIVINT         16
+#define BM_UARTAPP_LINECTRL_BAUD_DIVINT         0xffff0000
+#define BF_UARTAPP_LINECTRL_BAUD_DIVINT(v)      (((v) & 0xffff) << 16)
+#define BFM_UARTAPP_LINECTRL_BAUD_DIVINT(v)     BM_UARTAPP_LINECTRL_BAUD_DIVINT
+#define BF_UARTAPP_LINECTRL_BAUD_DIVINT_V(e)    BF_UARTAPP_LINECTRL_BAUD_DIVINT(BV_UARTAPP_LINECTRL_BAUD_DIVINT__##e)
+#define BFM_UARTAPP_LINECTRL_BAUD_DIVINT_V(v)   BM_UARTAPP_LINECTRL_BAUD_DIVINT
+#define BP_UARTAPP_LINECTRL_BAUD_DIVFRAC        8
+#define BM_UARTAPP_LINECTRL_BAUD_DIVFRAC        0x3f00
+#define BF_UARTAPP_LINECTRL_BAUD_DIVFRAC(v)     (((v) & 0x3f) << 8)
+#define BFM_UARTAPP_LINECTRL_BAUD_DIVFRAC(v)    BM_UARTAPP_LINECTRL_BAUD_DIVFRAC
+#define BF_UARTAPP_LINECTRL_BAUD_DIVFRAC_V(e)   BF_UARTAPP_LINECTRL_BAUD_DIVFRAC(BV_UARTAPP_LINECTRL_BAUD_DIVFRAC__##e)
+#define BFM_UARTAPP_LINECTRL_BAUD_DIVFRAC_V(v)  BM_UARTAPP_LINECTRL_BAUD_DIVFRAC
+#define BP_UARTAPP_LINECTRL_SPS                 7
+#define BM_UARTAPP_LINECTRL_SPS                 0x80
+#define BF_UARTAPP_LINECTRL_SPS(v)              (((v) & 0x1) << 7)
+#define BFM_UARTAPP_LINECTRL_SPS(v)             BM_UARTAPP_LINECTRL_SPS
+#define BF_UARTAPP_LINECTRL_SPS_V(e)            BF_UARTAPP_LINECTRL_SPS(BV_UARTAPP_LINECTRL_SPS__##e)
+#define BFM_UARTAPP_LINECTRL_SPS_V(v)           BM_UARTAPP_LINECTRL_SPS
+#define BP_UARTAPP_LINECTRL_WLEN                5
+#define BM_UARTAPP_LINECTRL_WLEN                0x60
+#define BF_UARTAPP_LINECTRL_WLEN(v)             (((v) & 0x3) << 5)
+#define BFM_UARTAPP_LINECTRL_WLEN(v)            BM_UARTAPP_LINECTRL_WLEN
+#define BF_UARTAPP_LINECTRL_WLEN_V(e)           BF_UARTAPP_LINECTRL_WLEN(BV_UARTAPP_LINECTRL_WLEN__##e)
+#define BFM_UARTAPP_LINECTRL_WLEN_V(v)          BM_UARTAPP_LINECTRL_WLEN
+#define BP_UARTAPP_LINECTRL_FEN                 4
+#define BM_UARTAPP_LINECTRL_FEN                 0x10
+#define BF_UARTAPP_LINECTRL_FEN(v)              (((v) & 0x1) << 4)
+#define BFM_UARTAPP_LINECTRL_FEN(v)             BM_UARTAPP_LINECTRL_FEN
+#define BF_UARTAPP_LINECTRL_FEN_V(e)            BF_UARTAPP_LINECTRL_FEN(BV_UARTAPP_LINECTRL_FEN__##e)
+#define BFM_UARTAPP_LINECTRL_FEN_V(v)           BM_UARTAPP_LINECTRL_FEN
+#define BP_UARTAPP_LINECTRL_STP2                3
+#define BM_UARTAPP_LINECTRL_STP2                0x8
+#define BF_UARTAPP_LINECTRL_STP2(v)             (((v) & 0x1) << 3)
+#define BFM_UARTAPP_LINECTRL_STP2(v)            BM_UARTAPP_LINECTRL_STP2
+#define BF_UARTAPP_LINECTRL_STP2_V(e)           BF_UARTAPP_LINECTRL_STP2(BV_UARTAPP_LINECTRL_STP2__##e)
+#define BFM_UARTAPP_LINECTRL_STP2_V(v)          BM_UARTAPP_LINECTRL_STP2
+#define BP_UARTAPP_LINECTRL_EPS                 2
+#define BM_UARTAPP_LINECTRL_EPS                 0x4
+#define BF_UARTAPP_LINECTRL_EPS(v)              (((v) & 0x1) << 2)
+#define BFM_UARTAPP_LINECTRL_EPS(v)             BM_UARTAPP_LINECTRL_EPS
+#define BF_UARTAPP_LINECTRL_EPS_V(e)            BF_UARTAPP_LINECTRL_EPS(BV_UARTAPP_LINECTRL_EPS__##e)
+#define BFM_UARTAPP_LINECTRL_EPS_V(v)           BM_UARTAPP_LINECTRL_EPS
+#define BP_UARTAPP_LINECTRL_PEN                 1
+#define BM_UARTAPP_LINECTRL_PEN                 0x2
+#define BF_UARTAPP_LINECTRL_PEN(v)              (((v) & 0x1) << 1)
+#define BFM_UARTAPP_LINECTRL_PEN(v)             BM_UARTAPP_LINECTRL_PEN
+#define BF_UARTAPP_LINECTRL_PEN_V(e)            BF_UARTAPP_LINECTRL_PEN(BV_UARTAPP_LINECTRL_PEN__##e)
+#define BFM_UARTAPP_LINECTRL_PEN_V(v)           BM_UARTAPP_LINECTRL_PEN
+#define BP_UARTAPP_LINECTRL_BRK                 0
+#define BM_UARTAPP_LINECTRL_BRK                 0x1
+#define BF_UARTAPP_LINECTRL_BRK(v)              (((v) & 0x1) << 0)
+#define BFM_UARTAPP_LINECTRL_BRK(v)             BM_UARTAPP_LINECTRL_BRK
+#define BF_UARTAPP_LINECTRL_BRK_V(e)            BF_UARTAPP_LINECTRL_BRK(BV_UARTAPP_LINECTRL_BRK__##e)
+#define BFM_UARTAPP_LINECTRL_BRK_V(v)           BM_UARTAPP_LINECTRL_BRK
+
+#define HW_UARTAPP_INTR                 HW(UARTAPP_INTR)
+#define HWA_UARTAPP_INTR                (0x8006c000 + 0x40)
+#define HWT_UARTAPP_INTR                HWIO_32_RW
+#define HWN_UARTAPP_INTR                UARTAPP_INTR
+#define HWI_UARTAPP_INTR                
+#define HW_UARTAPP_INTR_SET             HW(UARTAPP_INTR_SET)
+#define HWA_UARTAPP_INTR_SET            (HWA_UARTAPP_INTR + 0x4)
+#define HWT_UARTAPP_INTR_SET            HWIO_32_WO
+#define HWN_UARTAPP_INTR_SET            UARTAPP_INTR
+#define HWI_UARTAPP_INTR_SET            
+#define HW_UARTAPP_INTR_CLR             HW(UARTAPP_INTR_CLR)
+#define HWA_UARTAPP_INTR_CLR            (HWA_UARTAPP_INTR + 0x8)
+#define HWT_UARTAPP_INTR_CLR            HWIO_32_WO
+#define HWN_UARTAPP_INTR_CLR            UARTAPP_INTR
+#define HWI_UARTAPP_INTR_CLR            
+#define HW_UARTAPP_INTR_TOG             HW(UARTAPP_INTR_TOG)
+#define HWA_UARTAPP_INTR_TOG            (HWA_UARTAPP_INTR + 0xc)
+#define HWT_UARTAPP_INTR_TOG            HWIO_32_WO
+#define HWN_UARTAPP_INTR_TOG            UARTAPP_INTR
+#define HWI_UARTAPP_INTR_TOG            
+#define BP_UARTAPP_INTR_OEIEN           26
+#define BM_UARTAPP_INTR_OEIEN           0x4000000
+#define BF_UARTAPP_INTR_OEIEN(v)        (((v) & 0x1) << 26)
+#define BFM_UARTAPP_INTR_OEIEN(v)       BM_UARTAPP_INTR_OEIEN
+#define BF_UARTAPP_INTR_OEIEN_V(e)      BF_UARTAPP_INTR_OEIEN(BV_UARTAPP_INTR_OEIEN__##e)
+#define BFM_UARTAPP_INTR_OEIEN_V(v)     BM_UARTAPP_INTR_OEIEN
+#define BP_UARTAPP_INTR_BEIEN           25
+#define BM_UARTAPP_INTR_BEIEN           0x2000000
+#define BF_UARTAPP_INTR_BEIEN(v)        (((v) & 0x1) << 25)
+#define BFM_UARTAPP_INTR_BEIEN(v)       BM_UARTAPP_INTR_BEIEN
+#define BF_UARTAPP_INTR_BEIEN_V(e)      BF_UARTAPP_INTR_BEIEN(BV_UARTAPP_INTR_BEIEN__##e)
+#define BFM_UARTAPP_INTR_BEIEN_V(v)     BM_UARTAPP_INTR_BEIEN
+#define BP_UARTAPP_INTR_PEIEN           24
+#define BM_UARTAPP_INTR_PEIEN           0x1000000
+#define BF_UARTAPP_INTR_PEIEN(v)        (((v) & 0x1) << 24)
+#define BFM_UARTAPP_INTR_PEIEN(v)       BM_UARTAPP_INTR_PEIEN
+#define BF_UARTAPP_INTR_PEIEN_V(e)      BF_UARTAPP_INTR_PEIEN(BV_UARTAPP_INTR_PEIEN__##e)
+#define BFM_UARTAPP_INTR_PEIEN_V(v)     BM_UARTAPP_INTR_PEIEN
+#define BP_UARTAPP_INTR_FEIEN           23
+#define BM_UARTAPP_INTR_FEIEN           0x800000
+#define BF_UARTAPP_INTR_FEIEN(v)        (((v) & 0x1) << 23)
+#define BFM_UARTAPP_INTR_FEIEN(v)       BM_UARTAPP_INTR_FEIEN
+#define BF_UARTAPP_INTR_FEIEN_V(e)      BF_UARTAPP_INTR_FEIEN(BV_UARTAPP_INTR_FEIEN__##e)
+#define BFM_UARTAPP_INTR_FEIEN_V(v)     BM_UARTAPP_INTR_FEIEN
+#define BP_UARTAPP_INTR_RTIEN           22
+#define BM_UARTAPP_INTR_RTIEN           0x400000
+#define BF_UARTAPP_INTR_RTIEN(v)        (((v) & 0x1) << 22)
+#define BFM_UARTAPP_INTR_RTIEN(v)       BM_UARTAPP_INTR_RTIEN
+#define BF_UARTAPP_INTR_RTIEN_V(e)      BF_UARTAPP_INTR_RTIEN(BV_UARTAPP_INTR_RTIEN__##e)
+#define BFM_UARTAPP_INTR_RTIEN_V(v)     BM_UARTAPP_INTR_RTIEN
+#define BP_UARTAPP_INTR_TXIEN           21
+#define BM_UARTAPP_INTR_TXIEN           0x200000
+#define BF_UARTAPP_INTR_TXIEN(v)        (((v) & 0x1) << 21)
+#define BFM_UARTAPP_INTR_TXIEN(v)       BM_UARTAPP_INTR_TXIEN
+#define BF_UARTAPP_INTR_TXIEN_V(e)      BF_UARTAPP_INTR_TXIEN(BV_UARTAPP_INTR_TXIEN__##e)
+#define BFM_UARTAPP_INTR_TXIEN_V(v)     BM_UARTAPP_INTR_TXIEN
+#define BP_UARTAPP_INTR_RXIEN           20
+#define BM_UARTAPP_INTR_RXIEN           0x100000
+#define BF_UARTAPP_INTR_RXIEN(v)        (((v) & 0x1) << 20)
+#define BFM_UARTAPP_INTR_RXIEN(v)       BM_UARTAPP_INTR_RXIEN
+#define BF_UARTAPP_INTR_RXIEN_V(e)      BF_UARTAPP_INTR_RXIEN(BV_UARTAPP_INTR_RXIEN__##e)
+#define BFM_UARTAPP_INTR_RXIEN_V(v)     BM_UARTAPP_INTR_RXIEN
+#define BP_UARTAPP_INTR_DSRMIEN         19
+#define BM_UARTAPP_INTR_DSRMIEN         0x80000
+#define BF_UARTAPP_INTR_DSRMIEN(v)      (((v) & 0x1) << 19)
+#define BFM_UARTAPP_INTR_DSRMIEN(v)     BM_UARTAPP_INTR_DSRMIEN
+#define BF_UARTAPP_INTR_DSRMIEN_V(e)    BF_UARTAPP_INTR_DSRMIEN(BV_UARTAPP_INTR_DSRMIEN__##e)
+#define BFM_UARTAPP_INTR_DSRMIEN_V(v)   BM_UARTAPP_INTR_DSRMIEN
+#define BP_UARTAPP_INTR_DCDMIEN         18
+#define BM_UARTAPP_INTR_DCDMIEN         0x40000
+#define BF_UARTAPP_INTR_DCDMIEN(v)      (((v) & 0x1) << 18)
+#define BFM_UARTAPP_INTR_DCDMIEN(v)     BM_UARTAPP_INTR_DCDMIEN
+#define BF_UARTAPP_INTR_DCDMIEN_V(e)    BF_UARTAPP_INTR_DCDMIEN(BV_UARTAPP_INTR_DCDMIEN__##e)
+#define BFM_UARTAPP_INTR_DCDMIEN_V(v)   BM_UARTAPP_INTR_DCDMIEN
+#define BP_UARTAPP_INTR_CTSMIEN         17
+#define BM_UARTAPP_INTR_CTSMIEN         0x20000
+#define BF_UARTAPP_INTR_CTSMIEN(v)      (((v) & 0x1) << 17)
+#define BFM_UARTAPP_INTR_CTSMIEN(v)     BM_UARTAPP_INTR_CTSMIEN
+#define BF_UARTAPP_INTR_CTSMIEN_V(e)    BF_UARTAPP_INTR_CTSMIEN(BV_UARTAPP_INTR_CTSMIEN__##e)
+#define BFM_UARTAPP_INTR_CTSMIEN_V(v)   BM_UARTAPP_INTR_CTSMIEN
+#define BP_UARTAPP_INTR_RIMIEN          16
+#define BM_UARTAPP_INTR_RIMIEN          0x10000
+#define BF_UARTAPP_INTR_RIMIEN(v)       (((v) & 0x1) << 16)
+#define BFM_UARTAPP_INTR_RIMIEN(v)      BM_UARTAPP_INTR_RIMIEN
+#define BF_UARTAPP_INTR_RIMIEN_V(e)     BF_UARTAPP_INTR_RIMIEN(BV_UARTAPP_INTR_RIMIEN__##e)
+#define BFM_UARTAPP_INTR_RIMIEN_V(v)    BM_UARTAPP_INTR_RIMIEN
+#define BP_UARTAPP_INTR_OEIS            10
+#define BM_UARTAPP_INTR_OEIS            0x400
+#define BF_UARTAPP_INTR_OEIS(v)         (((v) & 0x1) << 10)
+#define BFM_UARTAPP_INTR_OEIS(v)        BM_UARTAPP_INTR_OEIS
+#define BF_UARTAPP_INTR_OEIS_V(e)       BF_UARTAPP_INTR_OEIS(BV_UARTAPP_INTR_OEIS__##e)
+#define BFM_UARTAPP_INTR_OEIS_V(v)      BM_UARTAPP_INTR_OEIS
+#define BP_UARTAPP_INTR_BEIS            9
+#define BM_UARTAPP_INTR_BEIS            0x200
+#define BF_UARTAPP_INTR_BEIS(v)         (((v) & 0x1) << 9)
+#define BFM_UARTAPP_INTR_BEIS(v)        BM_UARTAPP_INTR_BEIS
+#define BF_UARTAPP_INTR_BEIS_V(e)       BF_UARTAPP_INTR_BEIS(BV_UARTAPP_INTR_BEIS__##e)
+#define BFM_UARTAPP_INTR_BEIS_V(v)      BM_UARTAPP_INTR_BEIS
+#define BP_UARTAPP_INTR_PEIS            8
+#define BM_UARTAPP_INTR_PEIS            0x100
+#define BF_UARTAPP_INTR_PEIS(v)         (((v) & 0x1) << 8)
+#define BFM_UARTAPP_INTR_PEIS(v)        BM_UARTAPP_INTR_PEIS
+#define BF_UARTAPP_INTR_PEIS_V(e)       BF_UARTAPP_INTR_PEIS(BV_UARTAPP_INTR_PEIS__##e)
+#define BFM_UARTAPP_INTR_PEIS_V(v)      BM_UARTAPP_INTR_PEIS
+#define BP_UARTAPP_INTR_FEIS            7
+#define BM_UARTAPP_INTR_FEIS            0x80
+#define BF_UARTAPP_INTR_FEIS(v)         (((v) & 0x1) << 7)
+#define BFM_UARTAPP_INTR_FEIS(v)        BM_UARTAPP_INTR_FEIS
+#define BF_UARTAPP_INTR_FEIS_V(e)       BF_UARTAPP_INTR_FEIS(BV_UARTAPP_INTR_FEIS__##e)
+#define BFM_UARTAPP_INTR_FEIS_V(v)      BM_UARTAPP_INTR_FEIS
+#define BP_UARTAPP_INTR_RTIS            6
+#define BM_UARTAPP_INTR_RTIS            0x40
+#define BF_UARTAPP_INTR_RTIS(v)         (((v) & 0x1) << 6)
+#define BFM_UARTAPP_INTR_RTIS(v)        BM_UARTAPP_INTR_RTIS
+#define BF_UARTAPP_INTR_RTIS_V(e)       BF_UARTAPP_INTR_RTIS(BV_UARTAPP_INTR_RTIS__##e)
+#define BFM_UARTAPP_INTR_RTIS_V(v)      BM_UARTAPP_INTR_RTIS
+#define BP_UARTAPP_INTR_TXIS            5
+#define BM_UARTAPP_INTR_TXIS            0x20
+#define BF_UARTAPP_INTR_TXIS(v)         (((v) & 0x1) << 5)
+#define BFM_UARTAPP_INTR_TXIS(v)        BM_UARTAPP_INTR_TXIS
+#define BF_UARTAPP_INTR_TXIS_V(e)       BF_UARTAPP_INTR_TXIS(BV_UARTAPP_INTR_TXIS__##e)
+#define BFM_UARTAPP_INTR_TXIS_V(v)      BM_UARTAPP_INTR_TXIS
+#define BP_UARTAPP_INTR_RXIS            4
+#define BM_UARTAPP_INTR_RXIS            0x10
+#define BF_UARTAPP_INTR_RXIS(v)         (((v) & 0x1) << 4)
+#define BFM_UARTAPP_INTR_RXIS(v)        BM_UARTAPP_INTR_RXIS
+#define BF_UARTAPP_INTR_RXIS_V(e)       BF_UARTAPP_INTR_RXIS(BV_UARTAPP_INTR_RXIS__##e)
+#define BFM_UARTAPP_INTR_RXIS_V(v)      BM_UARTAPP_INTR_RXIS
+#define BP_UARTAPP_INTR_DSRMIS          3
+#define BM_UARTAPP_INTR_DSRMIS          0x8
+#define BF_UARTAPP_INTR_DSRMIS(v)       (((v) & 0x1) << 3)
+#define BFM_UARTAPP_INTR_DSRMIS(v)      BM_UARTAPP_INTR_DSRMIS
+#define BF_UARTAPP_INTR_DSRMIS_V(e)     BF_UARTAPP_INTR_DSRMIS(BV_UARTAPP_INTR_DSRMIS__##e)
+#define BFM_UARTAPP_INTR_DSRMIS_V(v)    BM_UARTAPP_INTR_DSRMIS
+#define BP_UARTAPP_INTR_DCDMIS          2
+#define BM_UARTAPP_INTR_DCDMIS          0x4
+#define BF_UARTAPP_INTR_DCDMIS(v)       (((v) & 0x1) << 2)
+#define BFM_UARTAPP_INTR_DCDMIS(v)      BM_UARTAPP_INTR_DCDMIS
+#define BF_UARTAPP_INTR_DCDMIS_V(e)     BF_UARTAPP_INTR_DCDMIS(BV_UARTAPP_INTR_DCDMIS__##e)
+#define BFM_UARTAPP_INTR_DCDMIS_V(v)    BM_UARTAPP_INTR_DCDMIS
+#define BP_UARTAPP_INTR_CTSMIS          1
+#define BM_UARTAPP_INTR_CTSMIS          0x2
+#define BF_UARTAPP_INTR_CTSMIS(v)       (((v) & 0x1) << 1)
+#define BFM_UARTAPP_INTR_CTSMIS(v)      BM_UARTAPP_INTR_CTSMIS
+#define BF_UARTAPP_INTR_CTSMIS_V(e)     BF_UARTAPP_INTR_CTSMIS(BV_UARTAPP_INTR_CTSMIS__##e)
+#define BFM_UARTAPP_INTR_CTSMIS_V(v)    BM_UARTAPP_INTR_CTSMIS
+#define BP_UARTAPP_INTR_RIMIS           0
+#define BM_UARTAPP_INTR_RIMIS           0x1
+#define BF_UARTAPP_INTR_RIMIS(v)        (((v) & 0x1) << 0)
+#define BFM_UARTAPP_INTR_RIMIS(v)       BM_UARTAPP_INTR_RIMIS
+#define BF_UARTAPP_INTR_RIMIS_V(e)      BF_UARTAPP_INTR_RIMIS(BV_UARTAPP_INTR_RIMIS__##e)
+#define BFM_UARTAPP_INTR_RIMIS_V(v)     BM_UARTAPP_INTR_RIMIS
+
+#define HW_UARTAPP_DATA             HW(UARTAPP_DATA)
+#define HWA_UARTAPP_DATA            (0x8006c000 + 0x50)
+#define HWT_UARTAPP_DATA            HWIO_32_RW
+#define HWN_UARTAPP_DATA            UARTAPP_DATA
+#define HWI_UARTAPP_DATA            
+#define BP_UARTAPP_DATA_DATA        0
+#define BM_UARTAPP_DATA_DATA        0xffffffff
+#define BF_UARTAPP_DATA_DATA(v)     (((v) & 0xffffffff) << 0)
+#define BFM_UARTAPP_DATA_DATA(v)    BM_UARTAPP_DATA_DATA
+#define BF_UARTAPP_DATA_DATA_V(e)   BF_UARTAPP_DATA_DATA(BV_UARTAPP_DATA_DATA__##e)
+#define BFM_UARTAPP_DATA_DATA_V(v)  BM_UARTAPP_DATA_DATA
+
+#define HW_UARTAPP_STAT                         HW(UARTAPP_STAT)
+#define HWA_UARTAPP_STAT                        (0x8006c000 + 0x60)
+#define HWT_UARTAPP_STAT                        HWIO_32_RW
+#define HWN_UARTAPP_STAT                        UARTAPP_STAT
+#define HWI_UARTAPP_STAT                        
+#define BP_UARTAPP_STAT_PRESENT                 31
+#define BM_UARTAPP_STAT_PRESENT                 0x80000000
+#define BV_UARTAPP_STAT_PRESENT__UNAVAILABLE    0x0
+#define BV_UARTAPP_STAT_PRESENT__AVAILABLE      0x1
+#define BF_UARTAPP_STAT_PRESENT(v)              (((v) & 0x1) << 31)
+#define BFM_UARTAPP_STAT_PRESENT(v)             BM_UARTAPP_STAT_PRESENT
+#define BF_UARTAPP_STAT_PRESENT_V(e)            BF_UARTAPP_STAT_PRESENT(BV_UARTAPP_STAT_PRESENT__##e)
+#define BFM_UARTAPP_STAT_PRESENT_V(v)           BM_UARTAPP_STAT_PRESENT
+#define BP_UARTAPP_STAT_HISPEED                 30
+#define BM_UARTAPP_STAT_HISPEED                 0x40000000
+#define BV_UARTAPP_STAT_HISPEED__UNAVAILABLE    0x0
+#define BV_UARTAPP_STAT_HISPEED__AVAILABLE      0x1
+#define BF_UARTAPP_STAT_HISPEED(v)              (((v) & 0x1) << 30)
+#define BFM_UARTAPP_STAT_HISPEED(v)             BM_UARTAPP_STAT_HISPEED
+#define BF_UARTAPP_STAT_HISPEED_V(e)            BF_UARTAPP_STAT_HISPEED(BV_UARTAPP_STAT_HISPEED__##e)
+#define BFM_UARTAPP_STAT_HISPEED_V(v)           BM_UARTAPP_STAT_HISPEED
+#define BP_UARTAPP_STAT_BUSY                    29
+#define BM_UARTAPP_STAT_BUSY                    0x20000000
+#define BF_UARTAPP_STAT_BUSY(v)                 (((v) & 0x1) << 29)
+#define BFM_UARTAPP_STAT_BUSY(v)                BM_UARTAPP_STAT_BUSY
+#define BF_UARTAPP_STAT_BUSY_V(e)               BF_UARTAPP_STAT_BUSY(BV_UARTAPP_STAT_BUSY__##e)
+#define BFM_UARTAPP_STAT_BUSY_V(v)              BM_UARTAPP_STAT_BUSY
+#define BP_UARTAPP_STAT_CTS                     28
+#define BM_UARTAPP_STAT_CTS                     0x10000000
+#define BF_UARTAPP_STAT_CTS(v)                  (((v) & 0x1) << 28)
+#define BFM_UARTAPP_STAT_CTS(v)                 BM_UARTAPP_STAT_CTS
+#define BF_UARTAPP_STAT_CTS_V(e)                BF_UARTAPP_STAT_CTS(BV_UARTAPP_STAT_CTS__##e)
+#define BFM_UARTAPP_STAT_CTS_V(v)               BM_UARTAPP_STAT_CTS
+#define BP_UARTAPP_STAT_TXFE                    27
+#define BM_UARTAPP_STAT_TXFE                    0x8000000
+#define BF_UARTAPP_STAT_TXFE(v)                 (((v) & 0x1) << 27)
+#define BFM_UARTAPP_STAT_TXFE(v)                BM_UARTAPP_STAT_TXFE
+#define BF_UARTAPP_STAT_TXFE_V(e)               BF_UARTAPP_STAT_TXFE(BV_UARTAPP_STAT_TXFE__##e)
+#define BFM_UARTAPP_STAT_TXFE_V(v)              BM_UARTAPP_STAT_TXFE
+#define BP_UARTAPP_STAT_RXFF                    26
+#define BM_UARTAPP_STAT_RXFF                    0x4000000
+#define BF_UARTAPP_STAT_RXFF(v)                 (((v) & 0x1) << 26)
+#define BFM_UARTAPP_STAT_RXFF(v)                BM_UARTAPP_STAT_RXFF
+#define BF_UARTAPP_STAT_RXFF_V(e)               BF_UARTAPP_STAT_RXFF(BV_UARTAPP_STAT_RXFF__##e)
+#define BFM_UARTAPP_STAT_RXFF_V(v)              BM_UARTAPP_STAT_RXFF
+#define BP_UARTAPP_STAT_TXFF                    25
+#define BM_UARTAPP_STAT_TXFF                    0x2000000
+#define BF_UARTAPP_STAT_TXFF(v)                 (((v) & 0x1) << 25)
+#define BFM_UARTAPP_STAT_TXFF(v)                BM_UARTAPP_STAT_TXFF
+#define BF_UARTAPP_STAT_TXFF_V(e)               BF_UARTAPP_STAT_TXFF(BV_UARTAPP_STAT_TXFF__##e)
+#define BFM_UARTAPP_STAT_TXFF_V(v)              BM_UARTAPP_STAT_TXFF
+#define BP_UARTAPP_STAT_RXFE                    24
+#define BM_UARTAPP_STAT_RXFE                    0x1000000
+#define BF_UARTAPP_STAT_RXFE(v)                 (((v) & 0x1) << 24)
+#define BFM_UARTAPP_STAT_RXFE(v)                BM_UARTAPP_STAT_RXFE
+#define BF_UARTAPP_STAT_RXFE_V(e)               BF_UARTAPP_STAT_RXFE(BV_UARTAPP_STAT_RXFE__##e)
+#define BFM_UARTAPP_STAT_RXFE_V(v)              BM_UARTAPP_STAT_RXFE
+#define BP_UARTAPP_STAT_RXBYTE_INVALID          20
+#define BM_UARTAPP_STAT_RXBYTE_INVALID          0xf00000
+#define BF_UARTAPP_STAT_RXBYTE_INVALID(v)       (((v) & 0xf) << 20)
+#define BFM_UARTAPP_STAT_RXBYTE_INVALID(v)      BM_UARTAPP_STAT_RXBYTE_INVALID
+#define BF_UARTAPP_STAT_RXBYTE_INVALID_V(e)     BF_UARTAPP_STAT_RXBYTE_INVALID(BV_UARTAPP_STAT_RXBYTE_INVALID__##e)
+#define BFM_UARTAPP_STAT_RXBYTE_INVALID_V(v)    BM_UARTAPP_STAT_RXBYTE_INVALID
+#define BP_UARTAPP_STAT_OERR                    19
+#define BM_UARTAPP_STAT_OERR                    0x80000
+#define BF_UARTAPP_STAT_OERR(v)                 (((v) & 0x1) << 19)
+#define BFM_UARTAPP_STAT_OERR(v)                BM_UARTAPP_STAT_OERR
+#define BF_UARTAPP_STAT_OERR_V(e)               BF_UARTAPP_STAT_OERR(BV_UARTAPP_STAT_OERR__##e)
+#define BFM_UARTAPP_STAT_OERR_V(v)              BM_UARTAPP_STAT_OERR
+#define BP_UARTAPP_STAT_BERR                    18
+#define BM_UARTAPP_STAT_BERR                    0x40000
+#define BF_UARTAPP_STAT_BERR(v)                 (((v) & 0x1) << 18)
+#define BFM_UARTAPP_STAT_BERR(v)                BM_UARTAPP_STAT_BERR
+#define BF_UARTAPP_STAT_BERR_V(e)               BF_UARTAPP_STAT_BERR(BV_UARTAPP_STAT_BERR__##e)
+#define BFM_UARTAPP_STAT_BERR_V(v)              BM_UARTAPP_STAT_BERR
+#define BP_UARTAPP_STAT_PERR                    17
+#define BM_UARTAPP_STAT_PERR                    0x20000
+#define BF_UARTAPP_STAT_PERR(v)                 (((v) & 0x1) << 17)
+#define BFM_UARTAPP_STAT_PERR(v)                BM_UARTAPP_STAT_PERR
+#define BF_UARTAPP_STAT_PERR_V(e)               BF_UARTAPP_STAT_PERR(BV_UARTAPP_STAT_PERR__##e)
+#define BFM_UARTAPP_STAT_PERR_V(v)              BM_UARTAPP_STAT_PERR
+#define BP_UARTAPP_STAT_FERR                    16
+#define BM_UARTAPP_STAT_FERR                    0x10000
+#define BF_UARTAPP_STAT_FERR(v)                 (((v) & 0x1) << 16)
+#define BFM_UARTAPP_STAT_FERR(v)                BM_UARTAPP_STAT_FERR
+#define BF_UARTAPP_STAT_FERR_V(e)               BF_UARTAPP_STAT_FERR(BV_UARTAPP_STAT_FERR__##e)
+#define BFM_UARTAPP_STAT_FERR_V(v)              BM_UARTAPP_STAT_FERR
+#define BP_UARTAPP_STAT_RXCOUNT                 0
+#define BM_UARTAPP_STAT_RXCOUNT                 0xffff
+#define BF_UARTAPP_STAT_RXCOUNT(v)              (((v) & 0xffff) << 0)
+#define BFM_UARTAPP_STAT_RXCOUNT(v)             BM_UARTAPP_STAT_RXCOUNT
+#define BF_UARTAPP_STAT_RXCOUNT_V(e)            BF_UARTAPP_STAT_RXCOUNT(BV_UARTAPP_STAT_RXCOUNT__##e)
+#define BFM_UARTAPP_STAT_RXCOUNT_V(v)           BM_UARTAPP_STAT_RXCOUNT
+
+#define HW_UARTAPP_DEBUG                HW(UARTAPP_DEBUG)
+#define HWA_UARTAPP_DEBUG               (0x8006c000 + 0x70)
+#define HWT_UARTAPP_DEBUG               HWIO_32_RW
+#define HWN_UARTAPP_DEBUG               UARTAPP_DEBUG
+#define HWI_UARTAPP_DEBUG               
+#define BP_UARTAPP_DEBUG_TXDMARUN       5
+#define BM_UARTAPP_DEBUG_TXDMARUN       0x20
+#define BF_UARTAPP_DEBUG_TXDMARUN(v)    (((v) & 0x1) << 5)
+#define BFM_UARTAPP_DEBUG_TXDMARUN(v)   BM_UARTAPP_DEBUG_TXDMARUN
+#define BF_UARTAPP_DEBUG_TXDMARUN_V(e)  BF_UARTAPP_DEBUG_TXDMARUN(BV_UARTAPP_DEBUG_TXDMARUN__##e)
+#define BFM_UARTAPP_DEBUG_TXDMARUN_V(v) BM_UARTAPP_DEBUG_TXDMARUN
+#define BP_UARTAPP_DEBUG_RXDMARUN       4
+#define BM_UARTAPP_DEBUG_RXDMARUN       0x10
+#define BF_UARTAPP_DEBUG_RXDMARUN(v)    (((v) & 0x1) << 4)
+#define BFM_UARTAPP_DEBUG_RXDMARUN(v)   BM_UARTAPP_DEBUG_RXDMARUN
+#define BF_UARTAPP_DEBUG_RXDMARUN_V(e)  BF_UARTAPP_DEBUG_RXDMARUN(BV_UARTAPP_DEBUG_RXDMARUN__##e)
+#define BFM_UARTAPP_DEBUG_RXDMARUN_V(v) BM_UARTAPP_DEBUG_RXDMARUN
+#define BP_UARTAPP_DEBUG_TXCMDEND       3
+#define BM_UARTAPP_DEBUG_TXCMDEND       0x8
+#define BF_UARTAPP_DEBUG_TXCMDEND(v)    (((v) & 0x1) << 3)
+#define BFM_UARTAPP_DEBUG_TXCMDEND(v)   BM_UARTAPP_DEBUG_TXCMDEND
+#define BF_UARTAPP_DEBUG_TXCMDEND_V(e)  BF_UARTAPP_DEBUG_TXCMDEND(BV_UARTAPP_DEBUG_TXCMDEND__##e)
+#define BFM_UARTAPP_DEBUG_TXCMDEND_V(v) BM_UARTAPP_DEBUG_TXCMDEND
+#define BP_UARTAPP_DEBUG_RXCMDEND       2
+#define BM_UARTAPP_DEBUG_RXCMDEND       0x4
+#define BF_UARTAPP_DEBUG_RXCMDEND(v)    (((v) & 0x1) << 2)
+#define BFM_UARTAPP_DEBUG_RXCMDEND(v)   BM_UARTAPP_DEBUG_RXCMDEND
+#define BF_UARTAPP_DEBUG_RXCMDEND_V(e)  BF_UARTAPP_DEBUG_RXCMDEND(BV_UARTAPP_DEBUG_RXCMDEND__##e)
+#define BFM_UARTAPP_DEBUG_RXCMDEND_V(v) BM_UARTAPP_DEBUG_RXCMDEND
+#define BP_UARTAPP_DEBUG_TXDMARQ        1
+#define BM_UARTAPP_DEBUG_TXDMARQ        0x2
+#define BF_UARTAPP_DEBUG_TXDMARQ(v)     (((v) & 0x1) << 1)
+#define BFM_UARTAPP_DEBUG_TXDMARQ(v)    BM_UARTAPP_DEBUG_TXDMARQ
+#define BF_UARTAPP_DEBUG_TXDMARQ_V(e)   BF_UARTAPP_DEBUG_TXDMARQ(BV_UARTAPP_DEBUG_TXDMARQ__##e)
+#define BFM_UARTAPP_DEBUG_TXDMARQ_V(v)  BM_UARTAPP_DEBUG_TXDMARQ
+#define BP_UARTAPP_DEBUG_RXDMARQ        0
+#define BM_UARTAPP_DEBUG_RXDMARQ        0x1
+#define BF_UARTAPP_DEBUG_RXDMARQ(v)     (((v) & 0x1) << 0)
+#define BFM_UARTAPP_DEBUG_RXDMARQ(v)    BM_UARTAPP_DEBUG_RXDMARQ
+#define BF_UARTAPP_DEBUG_RXDMARQ_V(e)   BF_UARTAPP_DEBUG_RXDMARQ(BV_UARTAPP_DEBUG_RXDMARQ__##e)
+#define BFM_UARTAPP_DEBUG_RXDMARQ_V(v)  BM_UARTAPP_DEBUG_RXDMARQ
+
+#endif /* __HEADERGEN_STMP3600_UARTAPP_H__*/
diff --git a/firmware/target/arm/imx233/regs/stmp3600/uartdbg.h b/firmware/target/arm/imx233/regs/stmp3600/uartdbg.h
new file mode 100644
index 0000000000..99f7d649c3
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3600/uartdbg.h
@@ -0,0 +1,817 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * stmp3600 version: 2.4.0
+ * stmp3600 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_STMP3600_UARTDBG_H__
+#define __HEADERGEN_STMP3600_UARTDBG_H__
+
+#define HW_UARTDBG_DR                   HW(UARTDBG_DR)
+#define HWA_UARTDBG_DR                  (0x80070000 + 0x0)
+#define HWT_UARTDBG_DR                  HWIO_32_RW
+#define HWN_UARTDBG_DR                  UARTDBG_DR
+#define HWI_UARTDBG_DR                  
+#define BP_UARTDBG_DR_UNAVAILABLE       16
+#define BM_UARTDBG_DR_UNAVAILABLE       0xffff0000
+#define BF_UARTDBG_DR_UNAVAILABLE(v)    (((v) & 0xffff) << 16)
+#define BFM_UARTDBG_DR_UNAVAILABLE(v)   BM_UARTDBG_DR_UNAVAILABLE
+#define BF_UARTDBG_DR_UNAVAILABLE_V(e)  BF_UARTDBG_DR_UNAVAILABLE(BV_UARTDBG_DR_UNAVAILABLE__##e)
+#define BFM_UARTDBG_DR_UNAVAILABLE_V(v) BM_UARTDBG_DR_UNAVAILABLE
+#define BP_UARTDBG_DR_RESERVED          12
+#define BM_UARTDBG_DR_RESERVED          0xf000
+#define BF_UARTDBG_DR_RESERVED(v)       (((v) & 0xf) << 12)
+#define BFM_UARTDBG_DR_RESERVED(v)      BM_UARTDBG_DR_RESERVED
+#define BF_UARTDBG_DR_RESERVED_V(e)     BF_UARTDBG_DR_RESERVED(BV_UARTDBG_DR_RESERVED__##e)
+#define BFM_UARTDBG_DR_RESERVED_V(v)    BM_UARTDBG_DR_RESERVED
+#define BP_UARTDBG_DR_OE                11
+#define BM_UARTDBG_DR_OE                0x800
+#define BF_UARTDBG_DR_OE(v)             (((v) & 0x1) << 11)
+#define BFM_UARTDBG_DR_OE(v)            BM_UARTDBG_DR_OE
+#define BF_UARTDBG_DR_OE_V(e)           BF_UARTDBG_DR_OE(BV_UARTDBG_DR_OE__##e)
+#define BFM_UARTDBG_DR_OE_V(v)          BM_UARTDBG_DR_OE
+#define BP_UARTDBG_DR_BE                10
+#define BM_UARTDBG_DR_BE                0x400
+#define BF_UARTDBG_DR_BE(v)             (((v) & 0x1) << 10)
+#define BFM_UARTDBG_DR_BE(v)            BM_UARTDBG_DR_BE
+#define BF_UARTDBG_DR_BE_V(e)           BF_UARTDBG_DR_BE(BV_UARTDBG_DR_BE__##e)
+#define BFM_UARTDBG_DR_BE_V(v)          BM_UARTDBG_DR_BE
+#define BP_UARTDBG_DR_PE                9
+#define BM_UARTDBG_DR_PE                0x200
+#define BF_UARTDBG_DR_PE(v)             (((v) & 0x1) << 9)
+#define BFM_UARTDBG_DR_PE(v)            BM_UARTDBG_DR_PE
+#define BF_UARTDBG_DR_PE_V(e)           BF_UARTDBG_DR_PE(BV_UARTDBG_DR_PE__##e)
+#define BFM_UARTDBG_DR_PE_V(v)          BM_UARTDBG_DR_PE
+#define BP_UARTDBG_DR_FE                8
+#define BM_UARTDBG_DR_FE                0x100
+#define BF_UARTDBG_DR_FE(v)             (((v) & 0x1) << 8)
+#define BFM_UARTDBG_DR_FE(v)            BM_UARTDBG_DR_FE
+#define BF_UARTDBG_DR_FE_V(e)           BF_UARTDBG_DR_FE(BV_UARTDBG_DR_FE__##e)
+#define BFM_UARTDBG_DR_FE_V(v)          BM_UARTDBG_DR_FE
+#define BP_UARTDBG_DR_DATA              0
+#define BM_UARTDBG_DR_DATA              0xff
+#define BF_UARTDBG_DR_DATA(v)           (((v) & 0xff) << 0)
+#define BFM_UARTDBG_DR_DATA(v)          BM_UARTDBG_DR_DATA
+#define BF_UARTDBG_DR_DATA_V(e)         BF_UARTDBG_DR_DATA(BV_UARTDBG_DR_DATA__##e)
+#define BFM_UARTDBG_DR_DATA_V(v)        BM_UARTDBG_DR_DATA
+
+#define HW_UARTDBG_RSR_ECR                      HW(UARTDBG_RSR_ECR)
+#define HWA_UARTDBG_RSR_ECR                     (0x80070000 + 0x4)
+#define HWT_UARTDBG_RSR_ECR                     HWIO_32_RW
+#define HWN_UARTDBG_RSR_ECR                     UARTDBG_RSR_ECR
+#define HWI_UARTDBG_RSR_ECR                     
+#define BP_UARTDBG_RSR_ECR_UNAVAILABLE          8
+#define BM_UARTDBG_RSR_ECR_UNAVAILABLE          0xffffff00
+#define BF_UARTDBG_RSR_ECR_UNAVAILABLE(v)       (((v) & 0xffffff) << 8)
+#define BFM_UARTDBG_RSR_ECR_UNAVAILABLE(v)      BM_UARTDBG_RSR_ECR_UNAVAILABLE
+#define BF_UARTDBG_RSR_ECR_UNAVAILABLE_V(e)     BF_UARTDBG_RSR_ECR_UNAVAILABLE(BV_UARTDBG_RSR_ECR_UNAVAILABLE__##e)
+#define BFM_UARTDBG_RSR_ECR_UNAVAILABLE_V(v)    BM_UARTDBG_RSR_ECR_UNAVAILABLE
+#define BP_UARTDBG_RSR_ECR_EC                   4
+#define BM_UARTDBG_RSR_ECR_EC                   0xf0
+#define BF_UARTDBG_RSR_ECR_EC(v)                (((v) & 0xf) << 4)
+#define BFM_UARTDBG_RSR_ECR_EC(v)               BM_UARTDBG_RSR_ECR_EC
+#define BF_UARTDBG_RSR_ECR_EC_V(e)              BF_UARTDBG_RSR_ECR_EC(BV_UARTDBG_RSR_ECR_EC__##e)
+#define BFM_UARTDBG_RSR_ECR_EC_V(v)             BM_UARTDBG_RSR_ECR_EC
+#define BP_UARTDBG_RSR_ECR_OE                   3
+#define BM_UARTDBG_RSR_ECR_OE                   0x8
+#define BF_UARTDBG_RSR_ECR_OE(v)                (((v) & 0x1) << 3)
+#define BFM_UARTDBG_RSR_ECR_OE(v)               BM_UARTDBG_RSR_ECR_OE
+#define BF_UARTDBG_RSR_ECR_OE_V(e)              BF_UARTDBG_RSR_ECR_OE(BV_UARTDBG_RSR_ECR_OE__##e)
+#define BFM_UARTDBG_RSR_ECR_OE_V(v)             BM_UARTDBG_RSR_ECR_OE
+#define BP_UARTDBG_RSR_ECR_BE                   2
+#define BM_UARTDBG_RSR_ECR_BE                   0x4
+#define BF_UARTDBG_RSR_ECR_BE(v)                (((v) & 0x1) << 2)
+#define BFM_UARTDBG_RSR_ECR_BE(v)               BM_UARTDBG_RSR_ECR_BE
+#define BF_UARTDBG_RSR_ECR_BE_V(e)              BF_UARTDBG_RSR_ECR_BE(BV_UARTDBG_RSR_ECR_BE__##e)
+#define BFM_UARTDBG_RSR_ECR_BE_V(v)             BM_UARTDBG_RSR_ECR_BE
+#define BP_UARTDBG_RSR_ECR_PE                   1
+#define BM_UARTDBG_RSR_ECR_PE                   0x2
+#define BF_UARTDBG_RSR_ECR_PE(v)                (((v) & 0x1) << 1)
+#define BFM_UARTDBG_RSR_ECR_PE(v)               BM_UARTDBG_RSR_ECR_PE
+#define BF_UARTDBG_RSR_ECR_PE_V(e)              BF_UARTDBG_RSR_ECR_PE(BV_UARTDBG_RSR_ECR_PE__##e)
+#define BFM_UARTDBG_RSR_ECR_PE_V(v)             BM_UARTDBG_RSR_ECR_PE
+#define BP_UARTDBG_RSR_ECR_FE                   0
+#define BM_UARTDBG_RSR_ECR_FE                   0x1
+#define BF_UARTDBG_RSR_ECR_FE(v)                (((v) & 0x1) << 0)
+#define BFM_UARTDBG_RSR_ECR_FE(v)               BM_UARTDBG_RSR_ECR_FE
+#define BF_UARTDBG_RSR_ECR_FE_V(e)              BF_UARTDBG_RSR_ECR_FE(BV_UARTDBG_RSR_ECR_FE__##e)
+#define BFM_UARTDBG_RSR_ECR_FE_V(v)             BM_UARTDBG_RSR_ECR_FE
+
+#define HW_UARTDBG_FR                   HW(UARTDBG_FR)
+#define HWA_UARTDBG_FR                  (0x80070000 + 0x18)
+#define HWT_UARTDBG_FR                  HWIO_32_RW
+#define HWN_UARTDBG_FR                  UARTDBG_FR
+#define HWI_UARTDBG_FR                  
+#define BP_UARTDBG_FR_UNAVAILABLE       16
+#define BM_UARTDBG_FR_UNAVAILABLE       0xffff0000
+#define BF_UARTDBG_FR_UNAVAILABLE(v)    (((v) & 0xffff) << 16)
+#define BFM_UARTDBG_FR_UNAVAILABLE(v)   BM_UARTDBG_FR_UNAVAILABLE
+#define BF_UARTDBG_FR_UNAVAILABLE_V(e)  BF_UARTDBG_FR_UNAVAILABLE(BV_UARTDBG_FR_UNAVAILABLE__##e)
+#define BFM_UARTDBG_FR_UNAVAILABLE_V(v) BM_UARTDBG_FR_UNAVAILABLE
+#define BP_UARTDBG_FR_RESERVED          9
+#define BM_UARTDBG_FR_RESERVED          0xfe00
+#define BF_UARTDBG_FR_RESERVED(v)       (((v) & 0x7f) << 9)
+#define BFM_UARTDBG_FR_RESERVED(v)      BM_UARTDBG_FR_RESERVED
+#define BF_UARTDBG_FR_RESERVED_V(e)     BF_UARTDBG_FR_RESERVED(BV_UARTDBG_FR_RESERVED__##e)
+#define BFM_UARTDBG_FR_RESERVED_V(v)    BM_UARTDBG_FR_RESERVED
+#define BP_UARTDBG_FR_RI                8
+#define BM_UARTDBG_FR_RI                0x100
+#define BF_UARTDBG_FR_RI(v)             (((v) & 0x1) << 8)
+#define BFM_UARTDBG_FR_RI(v)            BM_UARTDBG_FR_RI
+#define BF_UARTDBG_FR_RI_V(e)           BF_UARTDBG_FR_RI(BV_UARTDBG_FR_RI__##e)
+#define BFM_UARTDBG_FR_RI_V(v)          BM_UARTDBG_FR_RI
+#define BP_UARTDBG_FR_TXFE              7
+#define BM_UARTDBG_FR_TXFE              0x80
+#define BF_UARTDBG_FR_TXFE(v)           (((v) & 0x1) << 7)
+#define BFM_UARTDBG_FR_TXFE(v)          BM_UARTDBG_FR_TXFE
+#define BF_UARTDBG_FR_TXFE_V(e)         BF_UARTDBG_FR_TXFE(BV_UARTDBG_FR_TXFE__##e)
+#define BFM_UARTDBG_FR_TXFE_V(v)        BM_UARTDBG_FR_TXFE
+#define BP_UARTDBG_FR_RXFF              6
+#define BM_UARTDBG_FR_RXFF              0x40
+#define BF_UARTDBG_FR_RXFF(v)           (((v) & 0x1) << 6)
+#define BFM_UARTDBG_FR_RXFF(v)          BM_UARTDBG_FR_RXFF
+#define BF_UARTDBG_FR_RXFF_V(e)         BF_UARTDBG_FR_RXFF(BV_UARTDBG_FR_RXFF__##e)
+#define BFM_UARTDBG_FR_RXFF_V(v)        BM_UARTDBG_FR_RXFF
+#define BP_UARTDBG_FR_TXFF              5
+#define BM_UARTDBG_FR_TXFF              0x20
+#define BF_UARTDBG_FR_TXFF(v)           (((v) & 0x1) << 5)
+#define BFM_UARTDBG_FR_TXFF(v)          BM_UARTDBG_FR_TXFF
+#define BF_UARTDBG_FR_TXFF_V(e)         BF_UARTDBG_FR_TXFF(BV_UARTDBG_FR_TXFF__##e)
+#define BFM_UARTDBG_FR_TXFF_V(v)        BM_UARTDBG_FR_TXFF
+#define BP_UARTDBG_FR_RXFE              4
+#define BM_UARTDBG_FR_RXFE              0x10
+#define BF_UARTDBG_FR_RXFE(v)           (((v) & 0x1) << 4)
+#define BFM_UARTDBG_FR_RXFE(v)          BM_UARTDBG_FR_RXFE
+#define BF_UARTDBG_FR_RXFE_V(e)         BF_UARTDBG_FR_RXFE(BV_UARTDBG_FR_RXFE__##e)
+#define BFM_UARTDBG_FR_RXFE_V(v)        BM_UARTDBG_FR_RXFE
+#define BP_UARTDBG_FR_BUSY              3
+#define BM_UARTDBG_FR_BUSY              0x8
+#define BF_UARTDBG_FR_BUSY(v)           (((v) & 0x1) << 3)
+#define BFM_UARTDBG_FR_BUSY(v)          BM_UARTDBG_FR_BUSY
+#define BF_UARTDBG_FR_BUSY_V(e)         BF_UARTDBG_FR_BUSY(BV_UARTDBG_FR_BUSY__##e)
+#define BFM_UARTDBG_FR_BUSY_V(v)        BM_UARTDBG_FR_BUSY
+#define BP_UARTDBG_FR_DCD               2
+#define BM_UARTDBG_FR_DCD               0x4
+#define BF_UARTDBG_FR_DCD(v)            (((v) & 0x1) << 2)
+#define BFM_UARTDBG_FR_DCD(v)           BM_UARTDBG_FR_DCD
+#define BF_UARTDBG_FR_DCD_V(e)          BF_UARTDBG_FR_DCD(BV_UARTDBG_FR_DCD__##e)
+#define BFM_UARTDBG_FR_DCD_V(v)         BM_UARTDBG_FR_DCD
+#define BP_UARTDBG_FR_DSR               1
+#define BM_UARTDBG_FR_DSR               0x2
+#define BF_UARTDBG_FR_DSR(v)            (((v) & 0x1) << 1)
+#define BFM_UARTDBG_FR_DSR(v)           BM_UARTDBG_FR_DSR
+#define BF_UARTDBG_FR_DSR_V(e)          BF_UARTDBG_FR_DSR(BV_UARTDBG_FR_DSR__##e)
+#define BFM_UARTDBG_FR_DSR_V(v)         BM_UARTDBG_FR_DSR
+#define BP_UARTDBG_FR_CTS               0
+#define BM_UARTDBG_FR_CTS               0x1
+#define BF_UARTDBG_FR_CTS(v)            (((v) & 0x1) << 0)
+#define BFM_UARTDBG_FR_CTS(v)           BM_UARTDBG_FR_CTS
+#define BF_UARTDBG_FR_CTS_V(e)          BF_UARTDBG_FR_CTS(BV_UARTDBG_FR_CTS__##e)
+#define BFM_UARTDBG_FR_CTS_V(v)         BM_UARTDBG_FR_CTS
+
+#define HW_UARTDBG_ILPR                     HW(UARTDBG_ILPR)
+#define HWA_UARTDBG_ILPR                    (0x80070000 + 0x20)
+#define HWT_UARTDBG_ILPR                    HWIO_32_RW
+#define HWN_UARTDBG_ILPR                    UARTDBG_ILPR
+#define HWI_UARTDBG_ILPR                    
+#define BP_UARTDBG_ILPR_UNAVAILABLE         8
+#define BM_UARTDBG_ILPR_UNAVAILABLE         0xffffff00
+#define BF_UARTDBG_ILPR_UNAVAILABLE(v)      (((v) & 0xffffff) << 8)
+#define BFM_UARTDBG_ILPR_UNAVAILABLE(v)     BM_UARTDBG_ILPR_UNAVAILABLE
+#define BF_UARTDBG_ILPR_UNAVAILABLE_V(e)    BF_UARTDBG_ILPR_UNAVAILABLE(BV_UARTDBG_ILPR_UNAVAILABLE__##e)
+#define BFM_UARTDBG_ILPR_UNAVAILABLE_V(v)   BM_UARTDBG_ILPR_UNAVAILABLE
+#define BP_UARTDBG_ILPR_ILPDVSR             0
+#define BM_UARTDBG_ILPR_ILPDVSR             0xff
+#define BF_UARTDBG_ILPR_ILPDVSR(v)          (((v) & 0xff) << 0)
+#define BFM_UARTDBG_ILPR_ILPDVSR(v)         BM_UARTDBG_ILPR_ILPDVSR
+#define BF_UARTDBG_ILPR_ILPDVSR_V(e)        BF_UARTDBG_ILPR_ILPDVSR(BV_UARTDBG_ILPR_ILPDVSR__##e)
+#define BFM_UARTDBG_ILPR_ILPDVSR_V(v)       BM_UARTDBG_ILPR_ILPDVSR
+
+#define HW_UARTDBG_IBRD                     HW(UARTDBG_IBRD)
+#define HWA_UARTDBG_IBRD                    (0x80070000 + 0x24)
+#define HWT_UARTDBG_IBRD                    HWIO_32_RW
+#define HWN_UARTDBG_IBRD                    UARTDBG_IBRD
+#define HWI_UARTDBG_IBRD                    
+#define BP_UARTDBG_IBRD_UNAVAILABLE         16
+#define BM_UARTDBG_IBRD_UNAVAILABLE         0xffff0000
+#define BF_UARTDBG_IBRD_UNAVAILABLE(v)      (((v) & 0xffff) << 16)
+#define BFM_UARTDBG_IBRD_UNAVAILABLE(v)     BM_UARTDBG_IBRD_UNAVAILABLE
+#define BF_UARTDBG_IBRD_UNAVAILABLE_V(e)    BF_UARTDBG_IBRD_UNAVAILABLE(BV_UARTDBG_IBRD_UNAVAILABLE__##e)
+#define BFM_UARTDBG_IBRD_UNAVAILABLE_V(v)   BM_UARTDBG_IBRD_UNAVAILABLE
+#define BP_UARTDBG_IBRD_BAUD_DIVINT         0
+#define BM_UARTDBG_IBRD_BAUD_DIVINT         0xffff
+#define BF_UARTDBG_IBRD_BAUD_DIVINT(v)      (((v) & 0xffff) << 0)
+#define BFM_UARTDBG_IBRD_BAUD_DIVINT(v)     BM_UARTDBG_IBRD_BAUD_DIVINT
+#define BF_UARTDBG_IBRD_BAUD_DIVINT_V(e)    BF_UARTDBG_IBRD_BAUD_DIVINT(BV_UARTDBG_IBRD_BAUD_DIVINT__##e)
+#define BFM_UARTDBG_IBRD_BAUD_DIVINT_V(v)   BM_UARTDBG_IBRD_BAUD_DIVINT
+
+#define HW_UARTDBG_FBRD                     HW(UARTDBG_FBRD)
+#define HWA_UARTDBG_FBRD                    (0x80070000 + 0x28)
+#define HWT_UARTDBG_FBRD                    HWIO_32_RW
+#define HWN_UARTDBG_FBRD                    UARTDBG_FBRD
+#define HWI_UARTDBG_FBRD                    
+#define BP_UARTDBG_FBRD_UNAVAILABLE         8
+#define BM_UARTDBG_FBRD_UNAVAILABLE         0xffffff00
+#define BF_UARTDBG_FBRD_UNAVAILABLE(v)      (((v) & 0xffffff) << 8)
+#define BFM_UARTDBG_FBRD_UNAVAILABLE(v)     BM_UARTDBG_FBRD_UNAVAILABLE
+#define BF_UARTDBG_FBRD_UNAVAILABLE_V(e)    BF_UARTDBG_FBRD_UNAVAILABLE(BV_UARTDBG_FBRD_UNAVAILABLE__##e)
+#define BFM_UARTDBG_FBRD_UNAVAILABLE_V(v)   BM_UARTDBG_FBRD_UNAVAILABLE
+#define BP_UARTDBG_FBRD_RESERVED            6
+#define BM_UARTDBG_FBRD_RESERVED            0xc0
+#define BF_UARTDBG_FBRD_RESERVED(v)         (((v) & 0x3) << 6)
+#define BFM_UARTDBG_FBRD_RESERVED(v)        BM_UARTDBG_FBRD_RESERVED
+#define BF_UARTDBG_FBRD_RESERVED_V(e)       BF_UARTDBG_FBRD_RESERVED(BV_UARTDBG_FBRD_RESERVED__##e)
+#define BFM_UARTDBG_FBRD_RESERVED_V(v)      BM_UARTDBG_FBRD_RESERVED
+#define BP_UARTDBG_FBRD_BAUD_DIVFRAC        0
+#define BM_UARTDBG_FBRD_BAUD_DIVFRAC        0x3f
+#define BF_UARTDBG_FBRD_BAUD_DIVFRAC(v)     (((v) & 0x3f) << 0)
+#define BFM_UARTDBG_FBRD_BAUD_DIVFRAC(v)    BM_UARTDBG_FBRD_BAUD_DIVFRAC
+#define BF_UARTDBG_FBRD_BAUD_DIVFRAC_V(e)   BF_UARTDBG_FBRD_BAUD_DIVFRAC(BV_UARTDBG_FBRD_BAUD_DIVFRAC__##e)
+#define BFM_UARTDBG_FBRD_BAUD_DIVFRAC_V(v)  BM_UARTDBG_FBRD_BAUD_DIVFRAC
+
+#define HW_UARTDBG_LCR_H                    HW(UARTDBG_LCR_H)
+#define HWA_UARTDBG_LCR_H                   (0x80070000 + 0x2c)
+#define HWT_UARTDBG_LCR_H                   HWIO_32_RW
+#define HWN_UARTDBG_LCR_H                   UARTDBG_LCR_H
+#define HWI_UARTDBG_LCR_H                   
+#define BP_UARTDBG_LCR_H_UNAVAILABLE        16
+#define BM_UARTDBG_LCR_H_UNAVAILABLE        0xffff0000
+#define BF_UARTDBG_LCR_H_UNAVAILABLE(v)     (((v) & 0xffff) << 16)
+#define BFM_UARTDBG_LCR_H_UNAVAILABLE(v)    BM_UARTDBG_LCR_H_UNAVAILABLE
+#define BF_UARTDBG_LCR_H_UNAVAILABLE_V(e)   BF_UARTDBG_LCR_H_UNAVAILABLE(BV_UARTDBG_LCR_H_UNAVAILABLE__##e)
+#define BFM_UARTDBG_LCR_H_UNAVAILABLE_V(v)  BM_UARTDBG_LCR_H_UNAVAILABLE
+#define BP_UARTDBG_LCR_H_RESERVED           8
+#define BM_UARTDBG_LCR_H_RESERVED           0xff00
+#define BF_UARTDBG_LCR_H_RESERVED(v)        (((v) & 0xff) << 8)
+#define BFM_UARTDBG_LCR_H_RESERVED(v)       BM_UARTDBG_LCR_H_RESERVED
+#define BF_UARTDBG_LCR_H_RESERVED_V(e)      BF_UARTDBG_LCR_H_RESERVED(BV_UARTDBG_LCR_H_RESERVED__##e)
+#define BFM_UARTDBG_LCR_H_RESERVED_V(v)     BM_UARTDBG_LCR_H_RESERVED
+#define BP_UARTDBG_LCR_H_SPS                7
+#define BM_UARTDBG_LCR_H_SPS                0x80
+#define BF_UARTDBG_LCR_H_SPS(v)             (((v) & 0x1) << 7)
+#define BFM_UARTDBG_LCR_H_SPS(v)            BM_UARTDBG_LCR_H_SPS
+#define BF_UARTDBG_LCR_H_SPS_V(e)           BF_UARTDBG_LCR_H_SPS(BV_UARTDBG_LCR_H_SPS__##e)
+#define BFM_UARTDBG_LCR_H_SPS_V(v)          BM_UARTDBG_LCR_H_SPS
+#define BP_UARTDBG_LCR_H_WLEN               5
+#define BM_UARTDBG_LCR_H_WLEN               0x60
+#define BF_UARTDBG_LCR_H_WLEN(v)            (((v) & 0x3) << 5)
+#define BFM_UARTDBG_LCR_H_WLEN(v)           BM_UARTDBG_LCR_H_WLEN
+#define BF_UARTDBG_LCR_H_WLEN_V(e)          BF_UARTDBG_LCR_H_WLEN(BV_UARTDBG_LCR_H_WLEN__##e)
+#define BFM_UARTDBG_LCR_H_WLEN_V(v)         BM_UARTDBG_LCR_H_WLEN
+#define BP_UARTDBG_LCR_H_FEN                4
+#define BM_UARTDBG_LCR_H_FEN                0x10
+#define BF_UARTDBG_LCR_H_FEN(v)             (((v) & 0x1) << 4)
+#define BFM_UARTDBG_LCR_H_FEN(v)            BM_UARTDBG_LCR_H_FEN
+#define BF_UARTDBG_LCR_H_FEN_V(e)           BF_UARTDBG_LCR_H_FEN(BV_UARTDBG_LCR_H_FEN__##e)
+#define BFM_UARTDBG_LCR_H_FEN_V(v)          BM_UARTDBG_LCR_H_FEN
+#define BP_UARTDBG_LCR_H_STP2               3
+#define BM_UARTDBG_LCR_H_STP2               0x8
+#define BF_UARTDBG_LCR_H_STP2(v)            (((v) & 0x1) << 3)
+#define BFM_UARTDBG_LCR_H_STP2(v)           BM_UARTDBG_LCR_H_STP2
+#define BF_UARTDBG_LCR_H_STP2_V(e)          BF_UARTDBG_LCR_H_STP2(BV_UARTDBG_LCR_H_STP2__##e)
+#define BFM_UARTDBG_LCR_H_STP2_V(v)         BM_UARTDBG_LCR_H_STP2
+#define BP_UARTDBG_LCR_H_EPS                2
+#define BM_UARTDBG_LCR_H_EPS                0x4
+#define BF_UARTDBG_LCR_H_EPS(v)             (((v) & 0x1) << 2)
+#define BFM_UARTDBG_LCR_H_EPS(v)            BM_UARTDBG_LCR_H_EPS
+#define BF_UARTDBG_LCR_H_EPS_V(e)           BF_UARTDBG_LCR_H_EPS(BV_UARTDBG_LCR_H_EPS__##e)
+#define BFM_UARTDBG_LCR_H_EPS_V(v)          BM_UARTDBG_LCR_H_EPS
+#define BP_UARTDBG_LCR_H_PEN                1
+#define BM_UARTDBG_LCR_H_PEN                0x2
+#define BF_UARTDBG_LCR_H_PEN(v)             (((v) & 0x1) << 1)
+#define BFM_UARTDBG_LCR_H_PEN(v)            BM_UARTDBG_LCR_H_PEN
+#define BF_UARTDBG_LCR_H_PEN_V(e)           BF_UARTDBG_LCR_H_PEN(BV_UARTDBG_LCR_H_PEN__##e)
+#define BFM_UARTDBG_LCR_H_PEN_V(v)          BM_UARTDBG_LCR_H_PEN
+#define BP_UARTDBG_LCR_H_BRK                0
+#define BM_UARTDBG_LCR_H_BRK                0x1
+#define BF_UARTDBG_LCR_H_BRK(v)             (((v) & 0x1) << 0)
+#define BFM_UARTDBG_LCR_H_BRK(v)            BM_UARTDBG_LCR_H_BRK
+#define BF_UARTDBG_LCR_H_BRK_V(e)           BF_UARTDBG_LCR_H_BRK(BV_UARTDBG_LCR_H_BRK__##e)
+#define BFM_UARTDBG_LCR_H_BRK_V(v)          BM_UARTDBG_LCR_H_BRK
+
+#define HW_UARTDBG_CR                   HW(UARTDBG_CR)
+#define HWA_UARTDBG_CR                  (0x80070000 + 0x30)
+#define HWT_UARTDBG_CR                  HWIO_32_RW
+#define HWN_UARTDBG_CR                  UARTDBG_CR
+#define HWI_UARTDBG_CR                  
+#define BP_UARTDBG_CR_UNAVAILABLE       16
+#define BM_UARTDBG_CR_UNAVAILABLE       0xffff0000
+#define BF_UARTDBG_CR_UNAVAILABLE(v)    (((v) & 0xffff) << 16)
+#define BFM_UARTDBG_CR_UNAVAILABLE(v)   BM_UARTDBG_CR_UNAVAILABLE
+#define BF_UARTDBG_CR_UNAVAILABLE_V(e)  BF_UARTDBG_CR_UNAVAILABLE(BV_UARTDBG_CR_UNAVAILABLE__##e)
+#define BFM_UARTDBG_CR_UNAVAILABLE_V(v) BM_UARTDBG_CR_UNAVAILABLE
+#define BP_UARTDBG_CR_CTSEN             15
+#define BM_UARTDBG_CR_CTSEN             0x8000
+#define BF_UARTDBG_CR_CTSEN(v)          (((v) & 0x1) << 15)
+#define BFM_UARTDBG_CR_CTSEN(v)         BM_UARTDBG_CR_CTSEN
+#define BF_UARTDBG_CR_CTSEN_V(e)        BF_UARTDBG_CR_CTSEN(BV_UARTDBG_CR_CTSEN__##e)
+#define BFM_UARTDBG_CR_CTSEN_V(v)       BM_UARTDBG_CR_CTSEN
+#define BP_UARTDBG_CR_RTSEN             14
+#define BM_UARTDBG_CR_RTSEN             0x4000
+#define BF_UARTDBG_CR_RTSEN(v)          (((v) & 0x1) << 14)
+#define BFM_UARTDBG_CR_RTSEN(v)         BM_UARTDBG_CR_RTSEN
+#define BF_UARTDBG_CR_RTSEN_V(e)        BF_UARTDBG_CR_RTSEN(BV_UARTDBG_CR_RTSEN__##e)
+#define BFM_UARTDBG_CR_RTSEN_V(v)       BM_UARTDBG_CR_RTSEN
+#define BP_UARTDBG_CR_OUT2              13
+#define BM_UARTDBG_CR_OUT2              0x2000
+#define BF_UARTDBG_CR_OUT2(v)           (((v) & 0x1) << 13)
+#define BFM_UARTDBG_CR_OUT2(v)          BM_UARTDBG_CR_OUT2
+#define BF_UARTDBG_CR_OUT2_V(e)         BF_UARTDBG_CR_OUT2(BV_UARTDBG_CR_OUT2__##e)
+#define BFM_UARTDBG_CR_OUT2_V(v)        BM_UARTDBG_CR_OUT2
+#define BP_UARTDBG_CR_OUT1              12
+#define BM_UARTDBG_CR_OUT1              0x1000
+#define BF_UARTDBG_CR_OUT1(v)           (((v) & 0x1) << 12)
+#define BFM_UARTDBG_CR_OUT1(v)          BM_UARTDBG_CR_OUT1
+#define BF_UARTDBG_CR_OUT1_V(e)         BF_UARTDBG_CR_OUT1(BV_UARTDBG_CR_OUT1__##e)
+#define BFM_UARTDBG_CR_OUT1_V(v)        BM_UARTDBG_CR_OUT1
+#define BP_UARTDBG_CR_RTS               11
+#define BM_UARTDBG_CR_RTS               0x800
+#define BF_UARTDBG_CR_RTS(v)            (((v) & 0x1) << 11)
+#define BFM_UARTDBG_CR_RTS(v)           BM_UARTDBG_CR_RTS
+#define BF_UARTDBG_CR_RTS_V(e)          BF_UARTDBG_CR_RTS(BV_UARTDBG_CR_RTS__##e)
+#define BFM_UARTDBG_CR_RTS_V(v)         BM_UARTDBG_CR_RTS
+#define BP_UARTDBG_CR_DTR               10
+#define BM_UARTDBG_CR_DTR               0x400
+#define BF_UARTDBG_CR_DTR(v)            (((v) & 0x1) << 10)
+#define BFM_UARTDBG_CR_DTR(v)           BM_UARTDBG_CR_DTR
+#define BF_UARTDBG_CR_DTR_V(e)          BF_UARTDBG_CR_DTR(BV_UARTDBG_CR_DTR__##e)
+#define BFM_UARTDBG_CR_DTR_V(v)         BM_UARTDBG_CR_DTR
+#define BP_UARTDBG_CR_RXE               9
+#define BM_UARTDBG_CR_RXE               0x200
+#define BF_UARTDBG_CR_RXE(v)            (((v) & 0x1) << 9)
+#define BFM_UARTDBG_CR_RXE(v)           BM_UARTDBG_CR_RXE
+#define BF_UARTDBG_CR_RXE_V(e)          BF_UARTDBG_CR_RXE(BV_UARTDBG_CR_RXE__##e)
+#define BFM_UARTDBG_CR_RXE_V(v)         BM_UARTDBG_CR_RXE
+#define BP_UARTDBG_CR_TXE               8
+#define BM_UARTDBG_CR_TXE               0x100
+#define BF_UARTDBG_CR_TXE(v)            (((v) & 0x1) << 8)
+#define BFM_UARTDBG_CR_TXE(v)           BM_UARTDBG_CR_TXE
+#define BF_UARTDBG_CR_TXE_V(e)          BF_UARTDBG_CR_TXE(BV_UARTDBG_CR_TXE__##e)
+#define BFM_UARTDBG_CR_TXE_V(v)         BM_UARTDBG_CR_TXE
+#define BP_UARTDBG_CR_LBE               7
+#define BM_UARTDBG_CR_LBE               0x80
+#define BF_UARTDBG_CR_LBE(v)            (((v) & 0x1) << 7)
+#define BFM_UARTDBG_CR_LBE(v)           BM_UARTDBG_CR_LBE
+#define BF_UARTDBG_CR_LBE_V(e)          BF_UARTDBG_CR_LBE(BV_UARTDBG_CR_LBE__##e)
+#define BFM_UARTDBG_CR_LBE_V(v)         BM_UARTDBG_CR_LBE
+#define BP_UARTDBG_CR_RESERVED          3
+#define BM_UARTDBG_CR_RESERVED          0x78
+#define BF_UARTDBG_CR_RESERVED(v)       (((v) & 0xf) << 3)
+#define BFM_UARTDBG_CR_RESERVED(v)      BM_UARTDBG_CR_RESERVED
+#define BF_UARTDBG_CR_RESERVED_V(e)     BF_UARTDBG_CR_RESERVED(BV_UARTDBG_CR_RESERVED__##e)
+#define BFM_UARTDBG_CR_RESERVED_V(v)    BM_UARTDBG_CR_RESERVED
+#define BP_UARTDBG_CR_SIRLP             2
+#define BM_UARTDBG_CR_SIRLP             0x4
+#define BF_UARTDBG_CR_SIRLP(v)          (((v) & 0x1) << 2)
+#define BFM_UARTDBG_CR_SIRLP(v)         BM_UARTDBG_CR_SIRLP
+#define BF_UARTDBG_CR_SIRLP_V(e)        BF_UARTDBG_CR_SIRLP(BV_UARTDBG_CR_SIRLP__##e)
+#define BFM_UARTDBG_CR_SIRLP_V(v)       BM_UARTDBG_CR_SIRLP
+#define BP_UARTDBG_CR_SIREN             1
+#define BM_UARTDBG_CR_SIREN             0x2
+#define BF_UARTDBG_CR_SIREN(v)          (((v) & 0x1) << 1)
+#define BFM_UARTDBG_CR_SIREN(v)         BM_UARTDBG_CR_SIREN
+#define BF_UARTDBG_CR_SIREN_V(e)        BF_UARTDBG_CR_SIREN(BV_UARTDBG_CR_SIREN__##e)
+#define BFM_UARTDBG_CR_SIREN_V(v)       BM_UARTDBG_CR_SIREN
+#define BP_UARTDBG_CR_UARTEN            0
+#define BM_UARTDBG_CR_UARTEN            0x1
+#define BF_UARTDBG_CR_UARTEN(v)         (((v) & 0x1) << 0)
+#define BFM_UARTDBG_CR_UARTEN(v)        BM_UARTDBG_CR_UARTEN
+#define BF_UARTDBG_CR_UARTEN_V(e)       BF_UARTDBG_CR_UARTEN(BV_UARTDBG_CR_UARTEN__##e)
+#define BFM_UARTDBG_CR_UARTEN_V(v)      BM_UARTDBG_CR_UARTEN
+
+#define HW_UARTDBG_IFLS                             HW(UARTDBG_IFLS)
+#define HWA_UARTDBG_IFLS                            (0x80070000 + 0x34)
+#define HWT_UARTDBG_IFLS                            HWIO_32_RW
+#define HWN_UARTDBG_IFLS                            UARTDBG_IFLS
+#define HWI_UARTDBG_IFLS                            
+#define BP_UARTDBG_IFLS_UNAVAILABLE                 16
+#define BM_UARTDBG_IFLS_UNAVAILABLE                 0xffff0000
+#define BF_UARTDBG_IFLS_UNAVAILABLE(v)              (((v) & 0xffff) << 16)
+#define BFM_UARTDBG_IFLS_UNAVAILABLE(v)             BM_UARTDBG_IFLS_UNAVAILABLE
+#define BF_UARTDBG_IFLS_UNAVAILABLE_V(e)            BF_UARTDBG_IFLS_UNAVAILABLE(BV_UARTDBG_IFLS_UNAVAILABLE__##e)
+#define BFM_UARTDBG_IFLS_UNAVAILABLE_V(v)           BM_UARTDBG_IFLS_UNAVAILABLE
+#define BP_UARTDBG_IFLS_RESERVED                    6
+#define BM_UARTDBG_IFLS_RESERVED                    0xffc0
+#define BF_UARTDBG_IFLS_RESERVED(v)                 (((v) & 0x3ff) << 6)
+#define BFM_UARTDBG_IFLS_RESERVED(v)                BM_UARTDBG_IFLS_RESERVED
+#define BF_UARTDBG_IFLS_RESERVED_V(e)               BF_UARTDBG_IFLS_RESERVED(BV_UARTDBG_IFLS_RESERVED__##e)
+#define BFM_UARTDBG_IFLS_RESERVED_V(v)              BM_UARTDBG_IFLS_RESERVED
+#define BP_UARTDBG_IFLS_RXIFLSEL                    3
+#define BM_UARTDBG_IFLS_RXIFLSEL                    0x38
+#define BV_UARTDBG_IFLS_RXIFLSEL__NOT_EMPTY         0x0
+#define BV_UARTDBG_IFLS_RXIFLSEL__ONE_QUARTER       0x1
+#define BV_UARTDBG_IFLS_RXIFLSEL__ONE_HALF          0x2
+#define BV_UARTDBG_IFLS_RXIFLSEL__THREE_QUARTERS    0x3
+#define BV_UARTDBG_IFLS_RXIFLSEL__SEVEN_EIGHTHS     0x4
+#define BV_UARTDBG_IFLS_RXIFLSEL__INVALID5          0x5
+#define BV_UARTDBG_IFLS_RXIFLSEL__INVALID6          0x6
+#define BV_UARTDBG_IFLS_RXIFLSEL__INVALID7          0x7
+#define BF_UARTDBG_IFLS_RXIFLSEL(v)                 (((v) & 0x7) << 3)
+#define BFM_UARTDBG_IFLS_RXIFLSEL(v)                BM_UARTDBG_IFLS_RXIFLSEL
+#define BF_UARTDBG_IFLS_RXIFLSEL_V(e)               BF_UARTDBG_IFLS_RXIFLSEL(BV_UARTDBG_IFLS_RXIFLSEL__##e)
+#define BFM_UARTDBG_IFLS_RXIFLSEL_V(v)              BM_UARTDBG_IFLS_RXIFLSEL
+#define BP_UARTDBG_IFLS_TXIFLSEL                    0
+#define BM_UARTDBG_IFLS_TXIFLSEL                    0x7
+#define BV_UARTDBG_IFLS_TXIFLSEL__EMPTY             0x0
+#define BV_UARTDBG_IFLS_TXIFLSEL__ONE_QUARTER       0x1
+#define BV_UARTDBG_IFLS_TXIFLSEL__ONE_HALF          0x2
+#define BV_UARTDBG_IFLS_TXIFLSEL__THREE_QUARTERS    0x3
+#define BV_UARTDBG_IFLS_TXIFLSEL__SEVEN_EIGHTHS     0x4
+#define BV_UARTDBG_IFLS_TXIFLSEL__INVALID5          0x5
+#define BV_UARTDBG_IFLS_TXIFLSEL__INVALID6          0x6
+#define BV_UARTDBG_IFLS_TXIFLSEL__INVALID7          0x7
+#define BF_UARTDBG_IFLS_TXIFLSEL(v)                 (((v) & 0x7) << 0)
+#define BFM_UARTDBG_IFLS_TXIFLSEL(v)                BM_UARTDBG_IFLS_TXIFLSEL
+#define BF_UARTDBG_IFLS_TXIFLSEL_V(e)               BF_UARTDBG_IFLS_TXIFLSEL(BV_UARTDBG_IFLS_TXIFLSEL__##e)
+#define BFM_UARTDBG_IFLS_TXIFLSEL_V(v)              BM_UARTDBG_IFLS_TXIFLSEL
+
+#define HW_UARTDBG_IMSC                     HW(UARTDBG_IMSC)
+#define HWA_UARTDBG_IMSC                    (0x80070000 + 0x38)
+#define HWT_UARTDBG_IMSC                    HWIO_32_RW
+#define HWN_UARTDBG_IMSC                    UARTDBG_IMSC
+#define HWI_UARTDBG_IMSC                    
+#define BP_UARTDBG_IMSC_UNAVAILABLE         16
+#define BM_UARTDBG_IMSC_UNAVAILABLE         0xffff0000
+#define BF_UARTDBG_IMSC_UNAVAILABLE(v)      (((v) & 0xffff) << 16)
+#define BFM_UARTDBG_IMSC_UNAVAILABLE(v)     BM_UARTDBG_IMSC_UNAVAILABLE
+#define BF_UARTDBG_IMSC_UNAVAILABLE_V(e)    BF_UARTDBG_IMSC_UNAVAILABLE(BV_UARTDBG_IMSC_UNAVAILABLE__##e)
+#define BFM_UARTDBG_IMSC_UNAVAILABLE_V(v)   BM_UARTDBG_IMSC_UNAVAILABLE
+#define BP_UARTDBG_IMSC_RESERVED            11
+#define BM_UARTDBG_IMSC_RESERVED            0xf800
+#define BF_UARTDBG_IMSC_RESERVED(v)         (((v) & 0x1f) << 11)
+#define BFM_UARTDBG_IMSC_RESERVED(v)        BM_UARTDBG_IMSC_RESERVED
+#define BF_UARTDBG_IMSC_RESERVED_V(e)       BF_UARTDBG_IMSC_RESERVED(BV_UARTDBG_IMSC_RESERVED__##e)
+#define BFM_UARTDBG_IMSC_RESERVED_V(v)      BM_UARTDBG_IMSC_RESERVED
+#define BP_UARTDBG_IMSC_OEIM                10
+#define BM_UARTDBG_IMSC_OEIM                0x400
+#define BF_UARTDBG_IMSC_OEIM(v)             (((v) & 0x1) << 10)
+#define BFM_UARTDBG_IMSC_OEIM(v)            BM_UARTDBG_IMSC_OEIM
+#define BF_UARTDBG_IMSC_OEIM_V(e)           BF_UARTDBG_IMSC_OEIM(BV_UARTDBG_IMSC_OEIM__##e)
+#define BFM_UARTDBG_IMSC_OEIM_V(v)          BM_UARTDBG_IMSC_OEIM
+#define BP_UARTDBG_IMSC_BEIM                9
+#define BM_UARTDBG_IMSC_BEIM                0x200
+#define BF_UARTDBG_IMSC_BEIM(v)             (((v) & 0x1) << 9)
+#define BFM_UARTDBG_IMSC_BEIM(v)            BM_UARTDBG_IMSC_BEIM
+#define BF_UARTDBG_IMSC_BEIM_V(e)           BF_UARTDBG_IMSC_BEIM(BV_UARTDBG_IMSC_BEIM__##e)
+#define BFM_UARTDBG_IMSC_BEIM_V(v)          BM_UARTDBG_IMSC_BEIM
+#define BP_UARTDBG_IMSC_PEIM                8
+#define BM_UARTDBG_IMSC_PEIM                0x100
+#define BF_UARTDBG_IMSC_PEIM(v)             (((v) & 0x1) << 8)
+#define BFM_UARTDBG_IMSC_PEIM(v)            BM_UARTDBG_IMSC_PEIM
+#define BF_UARTDBG_IMSC_PEIM_V(e)           BF_UARTDBG_IMSC_PEIM(BV_UARTDBG_IMSC_PEIM__##e)
+#define BFM_UARTDBG_IMSC_PEIM_V(v)          BM_UARTDBG_IMSC_PEIM
+#define BP_UARTDBG_IMSC_FEIM                7
+#define BM_UARTDBG_IMSC_FEIM                0x80
+#define BF_UARTDBG_IMSC_FEIM(v)             (((v) & 0x1) << 7)
+#define BFM_UARTDBG_IMSC_FEIM(v)            BM_UARTDBG_IMSC_FEIM
+#define BF_UARTDBG_IMSC_FEIM_V(e)           BF_UARTDBG_IMSC_FEIM(BV_UARTDBG_IMSC_FEIM__##e)
+#define BFM_UARTDBG_IMSC_FEIM_V(v)          BM_UARTDBG_IMSC_FEIM
+#define BP_UARTDBG_IMSC_RTIM                6
+#define BM_UARTDBG_IMSC_RTIM                0x40
+#define BF_UARTDBG_IMSC_RTIM(v)             (((v) & 0x1) << 6)
+#define BFM_UARTDBG_IMSC_RTIM(v)            BM_UARTDBG_IMSC_RTIM
+#define BF_UARTDBG_IMSC_RTIM_V(e)           BF_UARTDBG_IMSC_RTIM(BV_UARTDBG_IMSC_RTIM__##e)
+#define BFM_UARTDBG_IMSC_RTIM_V(v)          BM_UARTDBG_IMSC_RTIM
+#define BP_UARTDBG_IMSC_TXIM                5
+#define BM_UARTDBG_IMSC_TXIM                0x20
+#define BF_UARTDBG_IMSC_TXIM(v)             (((v) & 0x1) << 5)
+#define BFM_UARTDBG_IMSC_TXIM(v)            BM_UARTDBG_IMSC_TXIM
+#define BF_UARTDBG_IMSC_TXIM_V(e)           BF_UARTDBG_IMSC_TXIM(BV_UARTDBG_IMSC_TXIM__##e)
+#define BFM_UARTDBG_IMSC_TXIM_V(v)          BM_UARTDBG_IMSC_TXIM
+#define BP_UARTDBG_IMSC_RXIM                4
+#define BM_UARTDBG_IMSC_RXIM                0x10
+#define BF_UARTDBG_IMSC_RXIM(v)             (((v) & 0x1) << 4)
+#define BFM_UARTDBG_IMSC_RXIM(v)            BM_UARTDBG_IMSC_RXIM
+#define BF_UARTDBG_IMSC_RXIM_V(e)           BF_UARTDBG_IMSC_RXIM(BV_UARTDBG_IMSC_RXIM__##e)
+#define BFM_UARTDBG_IMSC_RXIM_V(v)          BM_UARTDBG_IMSC_RXIM
+#define BP_UARTDBG_IMSC_DSRMIM              3
+#define BM_UARTDBG_IMSC_DSRMIM              0x8
+#define BF_UARTDBG_IMSC_DSRMIM(v)           (((v) & 0x1) << 3)
+#define BFM_UARTDBG_IMSC_DSRMIM(v)          BM_UARTDBG_IMSC_DSRMIM
+#define BF_UARTDBG_IMSC_DSRMIM_V(e)         BF_UARTDBG_IMSC_DSRMIM(BV_UARTDBG_IMSC_DSRMIM__##e)
+#define BFM_UARTDBG_IMSC_DSRMIM_V(v)        BM_UARTDBG_IMSC_DSRMIM
+#define BP_UARTDBG_IMSC_DCDMIM              2
+#define BM_UARTDBG_IMSC_DCDMIM              0x4
+#define BF_UARTDBG_IMSC_DCDMIM(v)           (((v) & 0x1) << 2)
+#define BFM_UARTDBG_IMSC_DCDMIM(v)          BM_UARTDBG_IMSC_DCDMIM
+#define BF_UARTDBG_IMSC_DCDMIM_V(e)         BF_UARTDBG_IMSC_DCDMIM(BV_UARTDBG_IMSC_DCDMIM__##e)
+#define BFM_UARTDBG_IMSC_DCDMIM_V(v)        BM_UARTDBG_IMSC_DCDMIM
+#define BP_UARTDBG_IMSC_CTSMIM              1
+#define BM_UARTDBG_IMSC_CTSMIM              0x2
+#define BF_UARTDBG_IMSC_CTSMIM(v)           (((v) & 0x1) << 1)
+#define BFM_UARTDBG_IMSC_CTSMIM(v)          BM_UARTDBG_IMSC_CTSMIM
+#define BF_UARTDBG_IMSC_CTSMIM_V(e)         BF_UARTDBG_IMSC_CTSMIM(BV_UARTDBG_IMSC_CTSMIM__##e)
+#define BFM_UARTDBG_IMSC_CTSMIM_V(v)        BM_UARTDBG_IMSC_CTSMIM
+#define BP_UARTDBG_IMSC_RIMIM               0
+#define BM_UARTDBG_IMSC_RIMIM               0x1
+#define BF_UARTDBG_IMSC_RIMIM(v)            (((v) & 0x1) << 0)
+#define BFM_UARTDBG_IMSC_RIMIM(v)           BM_UARTDBG_IMSC_RIMIM
+#define BF_UARTDBG_IMSC_RIMIM_V(e)          BF_UARTDBG_IMSC_RIMIM(BV_UARTDBG_IMSC_RIMIM__##e)
+#define BFM_UARTDBG_IMSC_RIMIM_V(v)         BM_UARTDBG_IMSC_RIMIM
+
+#define HW_UARTDBG_RIS                      HW(UARTDBG_RIS)
+#define HWA_UARTDBG_RIS                     (0x80070000 + 0x3c)
+#define HWT_UARTDBG_RIS                     HWIO_32_RW
+#define HWN_UARTDBG_RIS                     UARTDBG_RIS
+#define HWI_UARTDBG_RIS                     
+#define BP_UARTDBG_RIS_UNAVAILABLE          16
+#define BM_UARTDBG_RIS_UNAVAILABLE          0xffff0000
+#define BF_UARTDBG_RIS_UNAVAILABLE(v)       (((v) & 0xffff) << 16)
+#define BFM_UARTDBG_RIS_UNAVAILABLE(v)      BM_UARTDBG_RIS_UNAVAILABLE
+#define BF_UARTDBG_RIS_UNAVAILABLE_V(e)     BF_UARTDBG_RIS_UNAVAILABLE(BV_UARTDBG_RIS_UNAVAILABLE__##e)
+#define BFM_UARTDBG_RIS_UNAVAILABLE_V(v)    BM_UARTDBG_RIS_UNAVAILABLE
+#define BP_UARTDBG_RIS_RESERVED             11
+#define BM_UARTDBG_RIS_RESERVED             0xf800
+#define BF_UARTDBG_RIS_RESERVED(v)          (((v) & 0x1f) << 11)
+#define BFM_UARTDBG_RIS_RESERVED(v)         BM_UARTDBG_RIS_RESERVED
+#define BF_UARTDBG_RIS_RESERVED_V(e)        BF_UARTDBG_RIS_RESERVED(BV_UARTDBG_RIS_RESERVED__##e)
+#define BFM_UARTDBG_RIS_RESERVED_V(v)       BM_UARTDBG_RIS_RESERVED
+#define BP_UARTDBG_RIS_OERIS                10
+#define BM_UARTDBG_RIS_OERIS                0x400
+#define BF_UARTDBG_RIS_OERIS(v)             (((v) & 0x1) << 10)
+#define BFM_UARTDBG_RIS_OERIS(v)            BM_UARTDBG_RIS_OERIS
+#define BF_UARTDBG_RIS_OERIS_V(e)           BF_UARTDBG_RIS_OERIS(BV_UARTDBG_RIS_OERIS__##e)
+#define BFM_UARTDBG_RIS_OERIS_V(v)          BM_UARTDBG_RIS_OERIS
+#define BP_UARTDBG_RIS_BERIS                9
+#define BM_UARTDBG_RIS_BERIS                0x200
+#define BF_UARTDBG_RIS_BERIS(v)             (((v) & 0x1) << 9)
+#define BFM_UARTDBG_RIS_BERIS(v)            BM_UARTDBG_RIS_BERIS
+#define BF_UARTDBG_RIS_BERIS_V(e)           BF_UARTDBG_RIS_BERIS(BV_UARTDBG_RIS_BERIS__##e)
+#define BFM_UARTDBG_RIS_BERIS_V(v)          BM_UARTDBG_RIS_BERIS
+#define BP_UARTDBG_RIS_PERIS                8
+#define BM_UARTDBG_RIS_PERIS                0x100
+#define BF_UARTDBG_RIS_PERIS(v)             (((v) & 0x1) << 8)
+#define BFM_UARTDBG_RIS_PERIS(v)            BM_UARTDBG_RIS_PERIS
+#define BF_UARTDBG_RIS_PERIS_V(e)           BF_UARTDBG_RIS_PERIS(BV_UARTDBG_RIS_PERIS__##e)
+#define BFM_UARTDBG_RIS_PERIS_V(v)          BM_UARTDBG_RIS_PERIS
+#define BP_UARTDBG_RIS_FERIS                7
+#define BM_UARTDBG_RIS_FERIS                0x80
+#define BF_UARTDBG_RIS_FERIS(v)             (((v) & 0x1) << 7)
+#define BFM_UARTDBG_RIS_FERIS(v)            BM_UARTDBG_RIS_FERIS
+#define BF_UARTDBG_RIS_FERIS_V(e)           BF_UARTDBG_RIS_FERIS(BV_UARTDBG_RIS_FERIS__##e)
+#define BFM_UARTDBG_RIS_FERIS_V(v)          BM_UARTDBG_RIS_FERIS
+#define BP_UARTDBG_RIS_RTRIS                6
+#define BM_UARTDBG_RIS_RTRIS                0x40
+#define BF_UARTDBG_RIS_RTRIS(v)             (((v) & 0x1) << 6)
+#define BFM_UARTDBG_RIS_RTRIS(v)            BM_UARTDBG_RIS_RTRIS
+#define BF_UARTDBG_RIS_RTRIS_V(e)           BF_UARTDBG_RIS_RTRIS(BV_UARTDBG_RIS_RTRIS__##e)
+#define BFM_UARTDBG_RIS_RTRIS_V(v)          BM_UARTDBG_RIS_RTRIS
+#define BP_UARTDBG_RIS_TXRIS                5
+#define BM_UARTDBG_RIS_TXRIS                0x20
+#define BF_UARTDBG_RIS_TXRIS(v)             (((v) & 0x1) << 5)
+#define BFM_UARTDBG_RIS_TXRIS(v)            BM_UARTDBG_RIS_TXRIS
+#define BF_UARTDBG_RIS_TXRIS_V(e)           BF_UARTDBG_RIS_TXRIS(BV_UARTDBG_RIS_TXRIS__##e)
+#define BFM_UARTDBG_RIS_TXRIS_V(v)          BM_UARTDBG_RIS_TXRIS
+#define BP_UARTDBG_RIS_RXRIS                4
+#define BM_UARTDBG_RIS_RXRIS                0x10
+#define BF_UARTDBG_RIS_RXRIS(v)             (((v) & 0x1) << 4)
+#define BFM_UARTDBG_RIS_RXRIS(v)            BM_UARTDBG_RIS_RXRIS
+#define BF_UARTDBG_RIS_RXRIS_V(e)           BF_UARTDBG_RIS_RXRIS(BV_UARTDBG_RIS_RXRIS__##e)
+#define BFM_UARTDBG_RIS_RXRIS_V(v)          BM_UARTDBG_RIS_RXRIS
+#define BP_UARTDBG_RIS_DSRRMIS              3
+#define BM_UARTDBG_RIS_DSRRMIS              0x8
+#define BF_UARTDBG_RIS_DSRRMIS(v)           (((v) & 0x1) << 3)
+#define BFM_UARTDBG_RIS_DSRRMIS(v)          BM_UARTDBG_RIS_DSRRMIS
+#define BF_UARTDBG_RIS_DSRRMIS_V(e)         BF_UARTDBG_RIS_DSRRMIS(BV_UARTDBG_RIS_DSRRMIS__##e)
+#define BFM_UARTDBG_RIS_DSRRMIS_V(v)        BM_UARTDBG_RIS_DSRRMIS
+#define BP_UARTDBG_RIS_DCDRMIS              2
+#define BM_UARTDBG_RIS_DCDRMIS              0x4
+#define BF_UARTDBG_RIS_DCDRMIS(v)           (((v) & 0x1) << 2)
+#define BFM_UARTDBG_RIS_DCDRMIS(v)          BM_UARTDBG_RIS_DCDRMIS
+#define BF_UARTDBG_RIS_DCDRMIS_V(e)         BF_UARTDBG_RIS_DCDRMIS(BV_UARTDBG_RIS_DCDRMIS__##e)
+#define BFM_UARTDBG_RIS_DCDRMIS_V(v)        BM_UARTDBG_RIS_DCDRMIS
+#define BP_UARTDBG_RIS_CTSRMIS              1
+#define BM_UARTDBG_RIS_CTSRMIS              0x2
+#define BF_UARTDBG_RIS_CTSRMIS(v)           (((v) & 0x1) << 1)
+#define BFM_UARTDBG_RIS_CTSRMIS(v)          BM_UARTDBG_RIS_CTSRMIS
+#define BF_UARTDBG_RIS_CTSRMIS_V(e)         BF_UARTDBG_RIS_CTSRMIS(BV_UARTDBG_RIS_CTSRMIS__##e)
+#define BFM_UARTDBG_RIS_CTSRMIS_V(v)        BM_UARTDBG_RIS_CTSRMIS
+#define BP_UARTDBG_RIS_RIRMIS               0
+#define BM_UARTDBG_RIS_RIRMIS               0x1
+#define BF_UARTDBG_RIS_RIRMIS(v)            (((v) & 0x1) << 0)
+#define BFM_UARTDBG_RIS_RIRMIS(v)           BM_UARTDBG_RIS_RIRMIS
+#define BF_UARTDBG_RIS_RIRMIS_V(e)          BF_UARTDBG_RIS_RIRMIS(BV_UARTDBG_RIS_RIRMIS__##e)
+#define BFM_UARTDBG_RIS_RIRMIS_V(v)         BM_UARTDBG_RIS_RIRMIS
+
+#define HW_UARTDBG_MIS                      HW(UARTDBG_MIS)
+#define HWA_UARTDBG_MIS                     (0x80070000 + 0x40)
+#define HWT_UARTDBG_MIS                     HWIO_32_RW
+#define HWN_UARTDBG_MIS                     UARTDBG_MIS
+#define HWI_UARTDBG_MIS                     
+#define BP_UARTDBG_MIS_UNAVAILABLE          16
+#define BM_UARTDBG_MIS_UNAVAILABLE          0xffff0000
+#define BF_UARTDBG_MIS_UNAVAILABLE(v)       (((v) & 0xffff) << 16)
+#define BFM_UARTDBG_MIS_UNAVAILABLE(v)      BM_UARTDBG_MIS_UNAVAILABLE
+#define BF_UARTDBG_MIS_UNAVAILABLE_V(e)     BF_UARTDBG_MIS_UNAVAILABLE(BV_UARTDBG_MIS_UNAVAILABLE__##e)
+#define BFM_UARTDBG_MIS_UNAVAILABLE_V(v)    BM_UARTDBG_MIS_UNAVAILABLE
+#define BP_UARTDBG_MIS_RESERVED             11
+#define BM_UARTDBG_MIS_RESERVED             0xf800
+#define BF_UARTDBG_MIS_RESERVED(v)          (((v) & 0x1f) << 11)
+#define BFM_UARTDBG_MIS_RESERVED(v)         BM_UARTDBG_MIS_RESERVED
+#define BF_UARTDBG_MIS_RESERVED_V(e)        BF_UARTDBG_MIS_RESERVED(BV_UARTDBG_MIS_RESERVED__##e)
+#define BFM_UARTDBG_MIS_RESERVED_V(v)       BM_UARTDBG_MIS_RESERVED
+#define BP_UARTDBG_MIS_OEMIS                10
+#define BM_UARTDBG_MIS_OEMIS                0x400
+#define BF_UARTDBG_MIS_OEMIS(v)             (((v) & 0x1) << 10)
+#define BFM_UARTDBG_MIS_OEMIS(v)            BM_UARTDBG_MIS_OEMIS
+#define BF_UARTDBG_MIS_OEMIS_V(e)           BF_UARTDBG_MIS_OEMIS(BV_UARTDBG_MIS_OEMIS__##e)
+#define BFM_UARTDBG_MIS_OEMIS_V(v)          BM_UARTDBG_MIS_OEMIS
+#define BP_UARTDBG_MIS_BEMIS                9
+#define BM_UARTDBG_MIS_BEMIS                0x200
+#define BF_UARTDBG_MIS_BEMIS(v)             (((v) & 0x1) << 9)
+#define BFM_UARTDBG_MIS_BEMIS(v)            BM_UARTDBG_MIS_BEMIS
+#define BF_UARTDBG_MIS_BEMIS_V(e)           BF_UARTDBG_MIS_BEMIS(BV_UARTDBG_MIS_BEMIS__##e)
+#define BFM_UARTDBG_MIS_BEMIS_V(v)          BM_UARTDBG_MIS_BEMIS
+#define BP_UARTDBG_MIS_PEMIS                8
+#define BM_UARTDBG_MIS_PEMIS                0x100
+#define BF_UARTDBG_MIS_PEMIS(v)             (((v) & 0x1) << 8)
+#define BFM_UARTDBG_MIS_PEMIS(v)            BM_UARTDBG_MIS_PEMIS
+#define BF_UARTDBG_MIS_PEMIS_V(e)           BF_UARTDBG_MIS_PEMIS(BV_UARTDBG_MIS_PEMIS__##e)
+#define BFM_UARTDBG_MIS_PEMIS_V(v)          BM_UARTDBG_MIS_PEMIS
+#define BP_UARTDBG_MIS_FEMIS                7
+#define BM_UARTDBG_MIS_FEMIS                0x80
+#define BF_UARTDBG_MIS_FEMIS(v)             (((v) & 0x1) << 7)
+#define BFM_UARTDBG_MIS_FEMIS(v)            BM_UARTDBG_MIS_FEMIS
+#define BF_UARTDBG_MIS_FEMIS_V(e)           BF_UARTDBG_MIS_FEMIS(BV_UARTDBG_MIS_FEMIS__##e)
+#define BFM_UARTDBG_MIS_FEMIS_V(v)          BM_UARTDBG_MIS_FEMIS
+#define BP_UARTDBG_MIS_RTMIS                6
+#define BM_UARTDBG_MIS_RTMIS                0x40
+#define BF_UARTDBG_MIS_RTMIS(v)             (((v) & 0x1) << 6)
+#define BFM_UARTDBG_MIS_RTMIS(v)            BM_UARTDBG_MIS_RTMIS
+#define BF_UARTDBG_MIS_RTMIS_V(e)           BF_UARTDBG_MIS_RTMIS(BV_UARTDBG_MIS_RTMIS__##e)
+#define BFM_UARTDBG_MIS_RTMIS_V(v)          BM_UARTDBG_MIS_RTMIS
+#define BP_UARTDBG_MIS_TXMIS                5
+#define BM_UARTDBG_MIS_TXMIS                0x20
+#define BF_UARTDBG_MIS_TXMIS(v)             (((v) & 0x1) << 5)
+#define BFM_UARTDBG_MIS_TXMIS(v)            BM_UARTDBG_MIS_TXMIS
+#define BF_UARTDBG_MIS_TXMIS_V(e)           BF_UARTDBG_MIS_TXMIS(BV_UARTDBG_MIS_TXMIS__##e)
+#define BFM_UARTDBG_MIS_TXMIS_V(v)          BM_UARTDBG_MIS_TXMIS
+#define BP_UARTDBG_MIS_RXMIS                4
+#define BM_UARTDBG_MIS_RXMIS                0x10
+#define BF_UARTDBG_MIS_RXMIS(v)             (((v) & 0x1) << 4)
+#define BFM_UARTDBG_MIS_RXMIS(v)            BM_UARTDBG_MIS_RXMIS
+#define BF_UARTDBG_MIS_RXMIS_V(e)           BF_UARTDBG_MIS_RXMIS(BV_UARTDBG_MIS_RXMIS__##e)
+#define BFM_UARTDBG_MIS_RXMIS_V(v)          BM_UARTDBG_MIS_RXMIS
+#define BP_UARTDBG_MIS_DSRMMIS              3
+#define BM_UARTDBG_MIS_DSRMMIS              0x8
+#define BF_UARTDBG_MIS_DSRMMIS(v)           (((v) & 0x1) << 3)
+#define BFM_UARTDBG_MIS_DSRMMIS(v)          BM_UARTDBG_MIS_DSRMMIS
+#define BF_UARTDBG_MIS_DSRMMIS_V(e)         BF_UARTDBG_MIS_DSRMMIS(BV_UARTDBG_MIS_DSRMMIS__##e)
+#define BFM_UARTDBG_MIS_DSRMMIS_V(v)        BM_UARTDBG_MIS_DSRMMIS
+#define BP_UARTDBG_MIS_DCDMMIS              2
+#define BM_UARTDBG_MIS_DCDMMIS              0x4
+#define BF_UARTDBG_MIS_DCDMMIS(v)           (((v) & 0x1) << 2)
+#define BFM_UARTDBG_MIS_DCDMMIS(v)          BM_UARTDBG_MIS_DCDMMIS
+#define BF_UARTDBG_MIS_DCDMMIS_V(e)         BF_UARTDBG_MIS_DCDMMIS(BV_UARTDBG_MIS_DCDMMIS__##e)
+#define BFM_UARTDBG_MIS_DCDMMIS_V(v)        BM_UARTDBG_MIS_DCDMMIS
+#define BP_UARTDBG_MIS_CTSMMIS              1
+#define BM_UARTDBG_MIS_CTSMMIS              0x2
+#define BF_UARTDBG_MIS_CTSMMIS(v)           (((v) & 0x1) << 1)
+#define BFM_UARTDBG_MIS_CTSMMIS(v)          BM_UARTDBG_MIS_CTSMMIS
+#define BF_UARTDBG_MIS_CTSMMIS_V(e)         BF_UARTDBG_MIS_CTSMMIS(BV_UARTDBG_MIS_CTSMMIS__##e)
+#define BFM_UARTDBG_MIS_CTSMMIS_V(v)        BM_UARTDBG_MIS_CTSMMIS
+#define BP_UARTDBG_MIS_RIMMIS               0
+#define BM_UARTDBG_MIS_RIMMIS               0x1
+#define BF_UARTDBG_MIS_RIMMIS(v)            (((v) & 0x1) << 0)
+#define BFM_UARTDBG_MIS_RIMMIS(v)           BM_UARTDBG_MIS_RIMMIS
+#define BF_UARTDBG_MIS_RIMMIS_V(e)          BF_UARTDBG_MIS_RIMMIS(BV_UARTDBG_MIS_RIMMIS__##e)
+#define BFM_UARTDBG_MIS_RIMMIS_V(v)         BM_UARTDBG_MIS_RIMMIS
+
+#define HW_UARTDBG_ICR                      HW(UARTDBG_ICR)
+#define HWA_UARTDBG_ICR                     (0x80070000 + 0x44)
+#define HWT_UARTDBG_ICR                     HWIO_32_RW
+#define HWN_UARTDBG_ICR                     UARTDBG_ICR
+#define HWI_UARTDBG_ICR                     
+#define BP_UARTDBG_ICR_UNAVAILABLE          16
+#define BM_UARTDBG_ICR_UNAVAILABLE          0xffff0000
+#define BF_UARTDBG_ICR_UNAVAILABLE(v)       (((v) & 0xffff) << 16)
+#define BFM_UARTDBG_ICR_UNAVAILABLE(v)      BM_UARTDBG_ICR_UNAVAILABLE
+#define BF_UARTDBG_ICR_UNAVAILABLE_V(e)     BF_UARTDBG_ICR_UNAVAILABLE(BV_UARTDBG_ICR_UNAVAILABLE__##e)
+#define BFM_UARTDBG_ICR_UNAVAILABLE_V(v)    BM_UARTDBG_ICR_UNAVAILABLE
+#define BP_UARTDBG_ICR_RESERVED             11
+#define BM_UARTDBG_ICR_RESERVED             0xf800
+#define BF_UARTDBG_ICR_RESERVED(v)          (((v) & 0x1f) << 11)
+#define BFM_UARTDBG_ICR_RESERVED(v)         BM_UARTDBG_ICR_RESERVED
+#define BF_UARTDBG_ICR_RESERVED_V(e)        BF_UARTDBG_ICR_RESERVED(BV_UARTDBG_ICR_RESERVED__##e)
+#define BFM_UARTDBG_ICR_RESERVED_V(v)       BM_UARTDBG_ICR_RESERVED
+#define BP_UARTDBG_ICR_OEIC                 10
+#define BM_UARTDBG_ICR_OEIC                 0x400
+#define BF_UARTDBG_ICR_OEIC(v)              (((v) & 0x1) << 10)
+#define BFM_UARTDBG_ICR_OEIC(v)             BM_UARTDBG_ICR_OEIC
+#define BF_UARTDBG_ICR_OEIC_V(e)            BF_UARTDBG_ICR_OEIC(BV_UARTDBG_ICR_OEIC__##e)
+#define BFM_UARTDBG_ICR_OEIC_V(v)           BM_UARTDBG_ICR_OEIC
+#define BP_UARTDBG_ICR_BEIC                 9
+#define BM_UARTDBG_ICR_BEIC                 0x200
+#define BF_UARTDBG_ICR_BEIC(v)              (((v) & 0x1) << 9)
+#define BFM_UARTDBG_ICR_BEIC(v)             BM_UARTDBG_ICR_BEIC
+#define BF_UARTDBG_ICR_BEIC_V(e)            BF_UARTDBG_ICR_BEIC(BV_UARTDBG_ICR_BEIC__##e)
+#define BFM_UARTDBG_ICR_BEIC_V(v)           BM_UARTDBG_ICR_BEIC
+#define BP_UARTDBG_ICR_PEIC                 8
+#define BM_UARTDBG_ICR_PEIC                 0x100
+#define BF_UARTDBG_ICR_PEIC(v)              (((v) & 0x1) << 8)
+#define BFM_UARTDBG_ICR_PEIC(v)             BM_UARTDBG_ICR_PEIC
+#define BF_UARTDBG_ICR_PEIC_V(e)            BF_UARTDBG_ICR_PEIC(BV_UARTDBG_ICR_PEIC__##e)
+#define BFM_UARTDBG_ICR_PEIC_V(v)           BM_UARTDBG_ICR_PEIC
+#define BP_UARTDBG_ICR_FEIC                 7
+#define BM_UARTDBG_ICR_FEIC                 0x80
+#define BF_UARTDBG_ICR_FEIC(v)              (((v) & 0x1) << 7)
+#define BFM_UARTDBG_ICR_FEIC(v)             BM_UARTDBG_ICR_FEIC
+#define BF_UARTDBG_ICR_FEIC_V(e)            BF_UARTDBG_ICR_FEIC(BV_UARTDBG_ICR_FEIC__##e)
+#define BFM_UARTDBG_ICR_FEIC_V(v)           BM_UARTDBG_ICR_FEIC
+#define BP_UARTDBG_ICR_RTIC                 6
+#define BM_UARTDBG_ICR_RTIC                 0x40
+#define BF_UARTDBG_ICR_RTIC(v)              (((v) & 0x1) << 6)
+#define BFM_UARTDBG_ICR_RTIC(v)             BM_UARTDBG_ICR_RTIC
+#define BF_UARTDBG_ICR_RTIC_V(e)            BF_UARTDBG_ICR_RTIC(BV_UARTDBG_ICR_RTIC__##e)
+#define BFM_UARTDBG_ICR_RTIC_V(v)           BM_UARTDBG_ICR_RTIC
+#define BP_UARTDBG_ICR_TXIC                 5
+#define BM_UARTDBG_ICR_TXIC                 0x20
+#define BF_UARTDBG_ICR_TXIC(v)              (((v) & 0x1) << 5)
+#define BFM_UARTDBG_ICR_TXIC(v)             BM_UARTDBG_ICR_TXIC
+#define BF_UARTDBG_ICR_TXIC_V(e)            BF_UARTDBG_ICR_TXIC(BV_UARTDBG_ICR_TXIC__##e)
+#define BFM_UARTDBG_ICR_TXIC_V(v)           BM_UARTDBG_ICR_TXIC
+#define BP_UARTDBG_ICR_RXIC                 4
+#define BM_UARTDBG_ICR_RXIC                 0x10
+#define BF_UARTDBG_ICR_RXIC(v)              (((v) & 0x1) << 4)
+#define BFM_UARTDBG_ICR_RXIC(v)             BM_UARTDBG_ICR_RXIC
+#define BF_UARTDBG_ICR_RXIC_V(e)            BF_UARTDBG_ICR_RXIC(BV_UARTDBG_ICR_RXIC__##e)
+#define BFM_UARTDBG_ICR_RXIC_V(v)           BM_UARTDBG_ICR_RXIC
+#define BP_UARTDBG_ICR_DSRMIC               3
+#define BM_UARTDBG_ICR_DSRMIC               0x8
+#define BF_UARTDBG_ICR_DSRMIC(v)            (((v) & 0x1) << 3)
+#define BFM_UARTDBG_ICR_DSRMIC(v)           BM_UARTDBG_ICR_DSRMIC
+#define BF_UARTDBG_ICR_DSRMIC_V(e)          BF_UARTDBG_ICR_DSRMIC(BV_UARTDBG_ICR_DSRMIC__##e)
+#define BFM_UARTDBG_ICR_DSRMIC_V(v)         BM_UARTDBG_ICR_DSRMIC
+#define BP_UARTDBG_ICR_DCDMIC               2
+#define BM_UARTDBG_ICR_DCDMIC               0x4
+#define BF_UARTDBG_ICR_DCDMIC(v)            (((v) & 0x1) << 2)
+#define BFM_UARTDBG_ICR_DCDMIC(v)           BM_UARTDBG_ICR_DCDMIC
+#define BF_UARTDBG_ICR_DCDMIC_V(e)          BF_UARTDBG_ICR_DCDMIC(BV_UARTDBG_ICR_DCDMIC__##e)
+#define BFM_UARTDBG_ICR_DCDMIC_V(v)         BM_UARTDBG_ICR_DCDMIC
+#define BP_UARTDBG_ICR_CTSMIC               1
+#define BM_UARTDBG_ICR_CTSMIC               0x2
+#define BF_UARTDBG_ICR_CTSMIC(v)            (((v) & 0x1) << 1)
+#define BFM_UARTDBG_ICR_CTSMIC(v)           BM_UARTDBG_ICR_CTSMIC
+#define BF_UARTDBG_ICR_CTSMIC_V(e)          BF_UARTDBG_ICR_CTSMIC(BV_UARTDBG_ICR_CTSMIC__##e)
+#define BFM_UARTDBG_ICR_CTSMIC_V(v)         BM_UARTDBG_ICR_CTSMIC
+#define BP_UARTDBG_ICR_RIMIC                0
+#define BM_UARTDBG_ICR_RIMIC                0x1
+#define BF_UARTDBG_ICR_RIMIC(v)             (((v) & 0x1) << 0)
+#define BFM_UARTDBG_ICR_RIMIC(v)            BM_UARTDBG_ICR_RIMIC
+#define BF_UARTDBG_ICR_RIMIC_V(e)           BF_UARTDBG_ICR_RIMIC(BV_UARTDBG_ICR_RIMIC__##e)
+#define BFM_UARTDBG_ICR_RIMIC_V(v)          BM_UARTDBG_ICR_RIMIC
+
+#define HW_UARTDBG_DMACR                    HW(UARTDBG_DMACR)
+#define HWA_UARTDBG_DMACR                   (0x80070000 + 0x48)
+#define HWT_UARTDBG_DMACR                   HWIO_32_RW
+#define HWN_UARTDBG_DMACR                   UARTDBG_DMACR
+#define HWI_UARTDBG_DMACR                   
+#define BP_UARTDBG_DMACR_UNAVAILABLE        16
+#define BM_UARTDBG_DMACR_UNAVAILABLE        0xffff0000
+#define BF_UARTDBG_DMACR_UNAVAILABLE(v)     (((v) & 0xffff) << 16)
+#define BFM_UARTDBG_DMACR_UNAVAILABLE(v)    BM_UARTDBG_DMACR_UNAVAILABLE
+#define BF_UARTDBG_DMACR_UNAVAILABLE_V(e)   BF_UARTDBG_DMACR_UNAVAILABLE(BV_UARTDBG_DMACR_UNAVAILABLE__##e)
+#define BFM_UARTDBG_DMACR_UNAVAILABLE_V(v)  BM_UARTDBG_DMACR_UNAVAILABLE
+#define BP_UARTDBG_DMACR_RESERVED           3
+#define BM_UARTDBG_DMACR_RESERVED           0xfff8
+#define BF_UARTDBG_DMACR_RESERVED(v)        (((v) & 0x1fff) << 3)
+#define BFM_UARTDBG_DMACR_RESERVED(v)       BM_UARTDBG_DMACR_RESERVED
+#define BF_UARTDBG_DMACR_RESERVED_V(e)      BF_UARTDBG_DMACR_RESERVED(BV_UARTDBG_DMACR_RESERVED__##e)
+#define BFM_UARTDBG_DMACR_RESERVED_V(v)     BM_UARTDBG_DMACR_RESERVED
+#define BP_UARTDBG_DMACR_DMAONERR           2
+#define BM_UARTDBG_DMACR_DMAONERR           0x4
+#define BF_UARTDBG_DMACR_DMAONERR(v)        (((v) & 0x1) << 2)
+#define BFM_UARTDBG_DMACR_DMAONERR(v)       BM_UARTDBG_DMACR_DMAONERR
+#define BF_UARTDBG_DMACR_DMAONERR_V(e)      BF_UARTDBG_DMACR_DMAONERR(BV_UARTDBG_DMACR_DMAONERR__##e)
+#define BFM_UARTDBG_DMACR_DMAONERR_V(v)     BM_UARTDBG_DMACR_DMAONERR
+#define BP_UARTDBG_DMACR_TXDMAE             1
+#define BM_UARTDBG_DMACR_TXDMAE             0x2
+#define BF_UARTDBG_DMACR_TXDMAE(v)          (((v) & 0x1) << 1)
+#define BFM_UARTDBG_DMACR_TXDMAE(v)         BM_UARTDBG_DMACR_TXDMAE
+#define BF_UARTDBG_DMACR_TXDMAE_V(e)        BF_UARTDBG_DMACR_TXDMAE(BV_UARTDBG_DMACR_TXDMAE__##e)
+#define BFM_UARTDBG_DMACR_TXDMAE_V(v)       BM_UARTDBG_DMACR_TXDMAE
+#define BP_UARTDBG_DMACR_RXDMAE             0
+#define BM_UARTDBG_DMACR_RXDMAE             0x1
+#define BF_UARTDBG_DMACR_RXDMAE(v)          (((v) & 0x1) << 0)
+#define BFM_UARTDBG_DMACR_RXDMAE(v)         BM_UARTDBG_DMACR_RXDMAE
+#define BF_UARTDBG_DMACR_RXDMAE_V(e)        BF_UARTDBG_DMACR_RXDMAE(BV_UARTDBG_DMACR_RXDMAE__##e)
+#define BFM_UARTDBG_DMACR_RXDMAE_V(v)       BM_UARTDBG_DMACR_RXDMAE
+
+#endif /* __HEADERGEN_STMP3600_UARTDBG_H__*/
diff --git a/firmware/target/arm/imx233/regs/stmp3600/usbphy.h b/firmware/target/arm/imx233/regs/stmp3600/usbphy.h
new file mode 100644
index 0000000000..c7d37c375c
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3600/usbphy.h
@@ -0,0 +1,702 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * stmp3600 version: 2.4.0
+ * stmp3600 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_STMP3600_USBPHY_H__
+#define __HEADERGEN_STMP3600_USBPHY_H__
+
+#define HW_USBPHY_PWD                   HW(USBPHY_PWD)
+#define HWA_USBPHY_PWD                  (0x8007c000 + 0x0)
+#define HWT_USBPHY_PWD                  HWIO_32_RW
+#define HWN_USBPHY_PWD                  USBPHY_PWD
+#define HWI_USBPHY_PWD                  
+#define HW_USBPHY_PWD_SET               HW(USBPHY_PWD_SET)
+#define HWA_USBPHY_PWD_SET              (HWA_USBPHY_PWD + 0x4)
+#define HWT_USBPHY_PWD_SET              HWIO_32_WO
+#define HWN_USBPHY_PWD_SET              USBPHY_PWD
+#define HWI_USBPHY_PWD_SET              
+#define HW_USBPHY_PWD_CLR               HW(USBPHY_PWD_CLR)
+#define HWA_USBPHY_PWD_CLR              (HWA_USBPHY_PWD + 0x8)
+#define HWT_USBPHY_PWD_CLR              HWIO_32_WO
+#define HWN_USBPHY_PWD_CLR              USBPHY_PWD
+#define HWI_USBPHY_PWD_CLR              
+#define HW_USBPHY_PWD_TOG               HW(USBPHY_PWD_TOG)
+#define HWA_USBPHY_PWD_TOG              (HWA_USBPHY_PWD + 0xc)
+#define HWT_USBPHY_PWD_TOG              HWIO_32_WO
+#define HWN_USBPHY_PWD_TOG              USBPHY_PWD
+#define HWI_USBPHY_PWD_TOG              
+#define BP_USBPHY_PWD_RXPWDRX           20
+#define BM_USBPHY_PWD_RXPWDRX           0x100000
+#define BF_USBPHY_PWD_RXPWDRX(v)        (((v) & 0x1) << 20)
+#define BFM_USBPHY_PWD_RXPWDRX(v)       BM_USBPHY_PWD_RXPWDRX
+#define BF_USBPHY_PWD_RXPWDRX_V(e)      BF_USBPHY_PWD_RXPWDRX(BV_USBPHY_PWD_RXPWDRX__##e)
+#define BFM_USBPHY_PWD_RXPWDRX_V(v)     BM_USBPHY_PWD_RXPWDRX
+#define BP_USBPHY_PWD_RXPWDDIFF         19
+#define BM_USBPHY_PWD_RXPWDDIFF         0x80000
+#define BF_USBPHY_PWD_RXPWDDIFF(v)      (((v) & 0x1) << 19)
+#define BFM_USBPHY_PWD_RXPWDDIFF(v)     BM_USBPHY_PWD_RXPWDDIFF
+#define BF_USBPHY_PWD_RXPWDDIFF_V(e)    BF_USBPHY_PWD_RXPWDDIFF(BV_USBPHY_PWD_RXPWDDIFF__##e)
+#define BFM_USBPHY_PWD_RXPWDDIFF_V(v)   BM_USBPHY_PWD_RXPWDDIFF
+#define BP_USBPHY_PWD_RXPWD1PT1         18
+#define BM_USBPHY_PWD_RXPWD1PT1         0x40000
+#define BF_USBPHY_PWD_RXPWD1PT1(v)      (((v) & 0x1) << 18)
+#define BFM_USBPHY_PWD_RXPWD1PT1(v)     BM_USBPHY_PWD_RXPWD1PT1
+#define BF_USBPHY_PWD_RXPWD1PT1_V(e)    BF_USBPHY_PWD_RXPWD1PT1(BV_USBPHY_PWD_RXPWD1PT1__##e)
+#define BFM_USBPHY_PWD_RXPWD1PT1_V(v)   BM_USBPHY_PWD_RXPWD1PT1
+#define BP_USBPHY_PWD_RXPWDENV          17
+#define BM_USBPHY_PWD_RXPWDENV          0x20000
+#define BF_USBPHY_PWD_RXPWDENV(v)       (((v) & 0x1) << 17)
+#define BFM_USBPHY_PWD_RXPWDENV(v)      BM_USBPHY_PWD_RXPWDENV
+#define BF_USBPHY_PWD_RXPWDENV_V(e)     BF_USBPHY_PWD_RXPWDENV(BV_USBPHY_PWD_RXPWDENV__##e)
+#define BFM_USBPHY_PWD_RXPWDENV_V(v)    BM_USBPHY_PWD_RXPWDENV
+#define BP_USBPHY_PWD_TXPWDCOMP         14
+#define BM_USBPHY_PWD_TXPWDCOMP         0x4000
+#define BF_USBPHY_PWD_TXPWDCOMP(v)      (((v) & 0x1) << 14)
+#define BFM_USBPHY_PWD_TXPWDCOMP(v)     BM_USBPHY_PWD_TXPWDCOMP
+#define BF_USBPHY_PWD_TXPWDCOMP_V(e)    BF_USBPHY_PWD_TXPWDCOMP(BV_USBPHY_PWD_TXPWDCOMP__##e)
+#define BFM_USBPHY_PWD_TXPWDCOMP_V(v)   BM_USBPHY_PWD_TXPWDCOMP
+#define BP_USBPHY_PWD_TXPWDVBG          13
+#define BM_USBPHY_PWD_TXPWDVBG          0x2000
+#define BF_USBPHY_PWD_TXPWDVBG(v)       (((v) & 0x1) << 13)
+#define BFM_USBPHY_PWD_TXPWDVBG(v)      BM_USBPHY_PWD_TXPWDVBG
+#define BF_USBPHY_PWD_TXPWDVBG_V(e)     BF_USBPHY_PWD_TXPWDVBG(BV_USBPHY_PWD_TXPWDVBG__##e)
+#define BFM_USBPHY_PWD_TXPWDVBG_V(v)    BM_USBPHY_PWD_TXPWDVBG
+#define BP_USBPHY_PWD_TXPWDV2I          12
+#define BM_USBPHY_PWD_TXPWDV2I          0x1000
+#define BF_USBPHY_PWD_TXPWDV2I(v)       (((v) & 0x1) << 12)
+#define BFM_USBPHY_PWD_TXPWDV2I(v)      BM_USBPHY_PWD_TXPWDV2I
+#define BF_USBPHY_PWD_TXPWDV2I_V(e)     BF_USBPHY_PWD_TXPWDV2I(BV_USBPHY_PWD_TXPWDV2I__##e)
+#define BFM_USBPHY_PWD_TXPWDV2I_V(v)    BM_USBPHY_PWD_TXPWDV2I
+#define BP_USBPHY_PWD_TXPWDIBIAS        11
+#define BM_USBPHY_PWD_TXPWDIBIAS        0x800
+#define BF_USBPHY_PWD_TXPWDIBIAS(v)     (((v) & 0x1) << 11)
+#define BFM_USBPHY_PWD_TXPWDIBIAS(v)    BM_USBPHY_PWD_TXPWDIBIAS
+#define BF_USBPHY_PWD_TXPWDIBIAS_V(e)   BF_USBPHY_PWD_TXPWDIBIAS(BV_USBPHY_PWD_TXPWDIBIAS__##e)
+#define BFM_USBPHY_PWD_TXPWDIBIAS_V(v)  BM_USBPHY_PWD_TXPWDIBIAS
+#define BP_USBPHY_PWD_TXPWDFS           10
+#define BM_USBPHY_PWD_TXPWDFS           0x400
+#define BF_USBPHY_PWD_TXPWDFS(v)        (((v) & 0x1) << 10)
+#define BFM_USBPHY_PWD_TXPWDFS(v)       BM_USBPHY_PWD_TXPWDFS
+#define BF_USBPHY_PWD_TXPWDFS_V(e)      BF_USBPHY_PWD_TXPWDFS(BV_USBPHY_PWD_TXPWDFS__##e)
+#define BFM_USBPHY_PWD_TXPWDFS_V(v)     BM_USBPHY_PWD_TXPWDFS
+
+#define HW_USBPHY_TX                        HW(USBPHY_TX)
+#define HWA_USBPHY_TX                       (0x8007c000 + 0x10)
+#define HWT_USBPHY_TX                       HWIO_32_RW
+#define HWN_USBPHY_TX                       USBPHY_TX
+#define HWI_USBPHY_TX                       
+#define HW_USBPHY_TX_SET                    HW(USBPHY_TX_SET)
+#define HWA_USBPHY_TX_SET                   (HWA_USBPHY_TX + 0x4)
+#define HWT_USBPHY_TX_SET                   HWIO_32_WO
+#define HWN_USBPHY_TX_SET                   USBPHY_TX
+#define HWI_USBPHY_TX_SET                   
+#define HW_USBPHY_TX_CLR                    HW(USBPHY_TX_CLR)
+#define HWA_USBPHY_TX_CLR                   (HWA_USBPHY_TX + 0x8)
+#define HWT_USBPHY_TX_CLR                   HWIO_32_WO
+#define HWN_USBPHY_TX_CLR                   USBPHY_TX
+#define HWI_USBPHY_TX_CLR                   
+#define HW_USBPHY_TX_TOG                    HW(USBPHY_TX_TOG)
+#define HWA_USBPHY_TX_TOG                   (HWA_USBPHY_TX + 0xc)
+#define HWT_USBPHY_TX_TOG                   HWIO_32_WO
+#define HWN_USBPHY_TX_TOG                   USBPHY_TX
+#define HWI_USBPHY_TX_TOG                   
+#define BP_USBPHY_TX_TXCMPOUT_STATUS        23
+#define BM_USBPHY_TX_TXCMPOUT_STATUS        0x800000
+#define BF_USBPHY_TX_TXCMPOUT_STATUS(v)     (((v) & 0x1) << 23)
+#define BFM_USBPHY_TX_TXCMPOUT_STATUS(v)    BM_USBPHY_TX_TXCMPOUT_STATUS
+#define BF_USBPHY_TX_TXCMPOUT_STATUS_V(e)   BF_USBPHY_TX_TXCMPOUT_STATUS(BV_USBPHY_TX_TXCMPOUT_STATUS__##e)
+#define BFM_USBPHY_TX_TXCMPOUT_STATUS_V(v)  BM_USBPHY_TX_TXCMPOUT_STATUS
+#define BP_USBPHY_TX_TXENCAL45DP            21
+#define BM_USBPHY_TX_TXENCAL45DP            0x200000
+#define BF_USBPHY_TX_TXENCAL45DP(v)         (((v) & 0x1) << 21)
+#define BFM_USBPHY_TX_TXENCAL45DP(v)        BM_USBPHY_TX_TXENCAL45DP
+#define BF_USBPHY_TX_TXENCAL45DP_V(e)       BF_USBPHY_TX_TXENCAL45DP(BV_USBPHY_TX_TXENCAL45DP__##e)
+#define BFM_USBPHY_TX_TXENCAL45DP_V(v)      BM_USBPHY_TX_TXENCAL45DP
+#define BP_USBPHY_TX_TXCAL45DP              16
+#define BM_USBPHY_TX_TXCAL45DP              0x1f0000
+#define BF_USBPHY_TX_TXCAL45DP(v)           (((v) & 0x1f) << 16)
+#define BFM_USBPHY_TX_TXCAL45DP(v)          BM_USBPHY_TX_TXCAL45DP
+#define BF_USBPHY_TX_TXCAL45DP_V(e)         BF_USBPHY_TX_TXCAL45DP(BV_USBPHY_TX_TXCAL45DP__##e)
+#define BFM_USBPHY_TX_TXCAL45DP_V(v)        BM_USBPHY_TX_TXCAL45DP
+#define BP_USBPHY_TX_TXENCAL45DN            13
+#define BM_USBPHY_TX_TXENCAL45DN            0x2000
+#define BF_USBPHY_TX_TXENCAL45DN(v)         (((v) & 0x1) << 13)
+#define BFM_USBPHY_TX_TXENCAL45DN(v)        BM_USBPHY_TX_TXENCAL45DN
+#define BF_USBPHY_TX_TXENCAL45DN_V(e)       BF_USBPHY_TX_TXENCAL45DN(BV_USBPHY_TX_TXENCAL45DN__##e)
+#define BFM_USBPHY_TX_TXENCAL45DN_V(v)      BM_USBPHY_TX_TXENCAL45DN
+#define BP_USBPHY_TX_TXCAL45DN              8
+#define BM_USBPHY_TX_TXCAL45DN              0x1f00
+#define BF_USBPHY_TX_TXCAL45DN(v)           (((v) & 0x1f) << 8)
+#define BFM_USBPHY_TX_TXCAL45DN(v)          BM_USBPHY_TX_TXCAL45DN
+#define BF_USBPHY_TX_TXCAL45DN_V(e)         BF_USBPHY_TX_TXCAL45DN(BV_USBPHY_TX_TXCAL45DN__##e)
+#define BFM_USBPHY_TX_TXCAL45DN_V(v)        BM_USBPHY_TX_TXCAL45DN
+#define BP_USBPHY_TX_TXCALIBRATE            7
+#define BM_USBPHY_TX_TXCALIBRATE            0x80
+#define BF_USBPHY_TX_TXCALIBRATE(v)         (((v) & 0x1) << 7)
+#define BFM_USBPHY_TX_TXCALIBRATE(v)        BM_USBPHY_TX_TXCALIBRATE
+#define BF_USBPHY_TX_TXCALIBRATE_V(e)       BF_USBPHY_TX_TXCALIBRATE(BV_USBPHY_TX_TXCALIBRATE__##e)
+#define BFM_USBPHY_TX_TXCALIBRATE_V(v)      BM_USBPHY_TX_TXCALIBRATE
+
+#define HW_USBPHY_RX                    HW(USBPHY_RX)
+#define HWA_USBPHY_RX                   (0x8007c000 + 0x20)
+#define HWT_USBPHY_RX                   HWIO_32_RW
+#define HWN_USBPHY_RX                   USBPHY_RX
+#define HWI_USBPHY_RX                   
+#define HW_USBPHY_RX_SET                HW(USBPHY_RX_SET)
+#define HWA_USBPHY_RX_SET               (HWA_USBPHY_RX + 0x4)
+#define HWT_USBPHY_RX_SET               HWIO_32_WO
+#define HWN_USBPHY_RX_SET               USBPHY_RX
+#define HWI_USBPHY_RX_SET               
+#define HW_USBPHY_RX_CLR                HW(USBPHY_RX_CLR)
+#define HWA_USBPHY_RX_CLR               (HWA_USBPHY_RX + 0x8)
+#define HWT_USBPHY_RX_CLR               HWIO_32_WO
+#define HWN_USBPHY_RX_CLR               USBPHY_RX
+#define HWI_USBPHY_RX_CLR               
+#define HW_USBPHY_RX_TOG                HW(USBPHY_RX_TOG)
+#define HWA_USBPHY_RX_TOG               (HWA_USBPHY_RX + 0xc)
+#define HWT_USBPHY_RX_TOG               HWIO_32_WO
+#define HWN_USBPHY_RX_TOG               USBPHY_RX
+#define HWI_USBPHY_RX_TOG               
+#define BP_USBPHY_RX_RXDBYPASS          22
+#define BM_USBPHY_RX_RXDBYPASS          0x400000
+#define BF_USBPHY_RX_RXDBYPASS(v)       (((v) & 0x1) << 22)
+#define BFM_USBPHY_RX_RXDBYPASS(v)      BM_USBPHY_RX_RXDBYPASS
+#define BF_USBPHY_RX_RXDBYPASS_V(e)     BF_USBPHY_RX_RXDBYPASS(BV_USBPHY_RX_RXDBYPASS__##e)
+#define BFM_USBPHY_RX_RXDBYPASS_V(v)    BM_USBPHY_RX_RXDBYPASS
+#define BP_USBPHY_RX_DISCONADJ          4
+#define BM_USBPHY_RX_DISCONADJ          0x30
+#define BF_USBPHY_RX_DISCONADJ(v)       (((v) & 0x3) << 4)
+#define BFM_USBPHY_RX_DISCONADJ(v)      BM_USBPHY_RX_DISCONADJ
+#define BF_USBPHY_RX_DISCONADJ_V(e)     BF_USBPHY_RX_DISCONADJ(BV_USBPHY_RX_DISCONADJ__##e)
+#define BFM_USBPHY_RX_DISCONADJ_V(v)    BM_USBPHY_RX_DISCONADJ
+#define BP_USBPHY_RX_ENVADJ             0
+#define BM_USBPHY_RX_ENVADJ             0x3
+#define BF_USBPHY_RX_ENVADJ(v)          (((v) & 0x3) << 0)
+#define BFM_USBPHY_RX_ENVADJ(v)         BM_USBPHY_RX_ENVADJ
+#define BF_USBPHY_RX_ENVADJ_V(e)        BF_USBPHY_RX_ENVADJ(BV_USBPHY_RX_ENVADJ__##e)
+#define BFM_USBPHY_RX_ENVADJ_V(v)       BM_USBPHY_RX_ENVADJ
+
+#define HW_USBPHY_CTRL                              HW(USBPHY_CTRL)
+#define HWA_USBPHY_CTRL                             (0x8007c000 + 0x30)
+#define HWT_USBPHY_CTRL                             HWIO_32_RW
+#define HWN_USBPHY_CTRL                             USBPHY_CTRL
+#define HWI_USBPHY_CTRL                             
+#define HW_USBPHY_CTRL_SET                          HW(USBPHY_CTRL_SET)
+#define HWA_USBPHY_CTRL_SET                         (HWA_USBPHY_CTRL + 0x4)
+#define HWT_USBPHY_CTRL_SET                         HWIO_32_WO
+#define HWN_USBPHY_CTRL_SET                         USBPHY_CTRL
+#define HWI_USBPHY_CTRL_SET                         
+#define HW_USBPHY_CTRL_CLR                          HW(USBPHY_CTRL_CLR)
+#define HWA_USBPHY_CTRL_CLR                         (HWA_USBPHY_CTRL + 0x8)
+#define HWT_USBPHY_CTRL_CLR                         HWIO_32_WO
+#define HWN_USBPHY_CTRL_CLR                         USBPHY_CTRL
+#define HWI_USBPHY_CTRL_CLR                         
+#define HW_USBPHY_CTRL_TOG                          HW(USBPHY_CTRL_TOG)
+#define HWA_USBPHY_CTRL_TOG                         (HWA_USBPHY_CTRL + 0xc)
+#define HWT_USBPHY_CTRL_TOG                         HWIO_32_WO
+#define HWN_USBPHY_CTRL_TOG                         USBPHY_CTRL
+#define HWI_USBPHY_CTRL_TOG                         
+#define BP_USBPHY_CTRL_SFTRST                       31
+#define BM_USBPHY_CTRL_SFTRST                       0x80000000
+#define BF_USBPHY_CTRL_SFTRST(v)                    (((v) & 0x1) << 31)
+#define BFM_USBPHY_CTRL_SFTRST(v)                   BM_USBPHY_CTRL_SFTRST
+#define BF_USBPHY_CTRL_SFTRST_V(e)                  BF_USBPHY_CTRL_SFTRST(BV_USBPHY_CTRL_SFTRST__##e)
+#define BFM_USBPHY_CTRL_SFTRST_V(v)                 BM_USBPHY_CTRL_SFTRST
+#define BP_USBPHY_CTRL_CLKGATE                      30
+#define BM_USBPHY_CTRL_CLKGATE                      0x40000000
+#define BF_USBPHY_CTRL_CLKGATE(v)                   (((v) & 0x1) << 30)
+#define BFM_USBPHY_CTRL_CLKGATE(v)                  BM_USBPHY_CTRL_CLKGATE
+#define BF_USBPHY_CTRL_CLKGATE_V(e)                 BF_USBPHY_CTRL_CLKGATE(BV_USBPHY_CTRL_CLKGATE__##e)
+#define BFM_USBPHY_CTRL_CLKGATE_V(v)                BM_USBPHY_CTRL_CLKGATE
+#define BP_USBPHY_CTRL_UTMI_SUSPENDM                29
+#define BM_USBPHY_CTRL_UTMI_SUSPENDM                0x20000000
+#define BF_USBPHY_CTRL_UTMI_SUSPENDM(v)             (((v) & 0x1) << 29)
+#define BFM_USBPHY_CTRL_UTMI_SUSPENDM(v)            BM_USBPHY_CTRL_UTMI_SUSPENDM
+#define BF_USBPHY_CTRL_UTMI_SUSPENDM_V(e)           BF_USBPHY_CTRL_UTMI_SUSPENDM(BV_USBPHY_CTRL_UTMI_SUSPENDM__##e)
+#define BFM_USBPHY_CTRL_UTMI_SUSPENDM_V(v)          BM_USBPHY_CTRL_UTMI_SUSPENDM
+#define BP_USBPHY_CTRL_RESUME_IRQ                   10
+#define BM_USBPHY_CTRL_RESUME_IRQ                   0x400
+#define BF_USBPHY_CTRL_RESUME_IRQ(v)                (((v) & 0x1) << 10)
+#define BFM_USBPHY_CTRL_RESUME_IRQ(v)               BM_USBPHY_CTRL_RESUME_IRQ
+#define BF_USBPHY_CTRL_RESUME_IRQ_V(e)              BF_USBPHY_CTRL_RESUME_IRQ(BV_USBPHY_CTRL_RESUME_IRQ__##e)
+#define BFM_USBPHY_CTRL_RESUME_IRQ_V(v)             BM_USBPHY_CTRL_RESUME_IRQ
+#define BP_USBPHY_CTRL_ENIRQRESUMEDETECT            9
+#define BM_USBPHY_CTRL_ENIRQRESUMEDETECT            0x200
+#define BF_USBPHY_CTRL_ENIRQRESUMEDETECT(v)         (((v) & 0x1) << 9)
+#define BFM_USBPHY_CTRL_ENIRQRESUMEDETECT(v)        BM_USBPHY_CTRL_ENIRQRESUMEDETECT
+#define BF_USBPHY_CTRL_ENIRQRESUMEDETECT_V(e)       BF_USBPHY_CTRL_ENIRQRESUMEDETECT(BV_USBPHY_CTRL_ENIRQRESUMEDETECT__##e)
+#define BFM_USBPHY_CTRL_ENIRQRESUMEDETECT_V(v)      BM_USBPHY_CTRL_ENIRQRESUMEDETECT
+#define BP_USBPHY_CTRL_ENOTGIDDETECT                7
+#define BM_USBPHY_CTRL_ENOTGIDDETECT                0x80
+#define BF_USBPHY_CTRL_ENOTGIDDETECT(v)             (((v) & 0x1) << 7)
+#define BFM_USBPHY_CTRL_ENOTGIDDETECT(v)            BM_USBPHY_CTRL_ENOTGIDDETECT
+#define BF_USBPHY_CTRL_ENOTGIDDETECT_V(e)           BF_USBPHY_CTRL_ENOTGIDDETECT(BV_USBPHY_CTRL_ENOTGIDDETECT__##e)
+#define BFM_USBPHY_CTRL_ENOTGIDDETECT_V(v)          BM_USBPHY_CTRL_ENOTGIDDETECT
+#define BP_USBPHY_CTRL_ENDEVPLUGINDETECT            4
+#define BM_USBPHY_CTRL_ENDEVPLUGINDETECT            0x10
+#define BF_USBPHY_CTRL_ENDEVPLUGINDETECT(v)         (((v) & 0x1) << 4)
+#define BFM_USBPHY_CTRL_ENDEVPLUGINDETECT(v)        BM_USBPHY_CTRL_ENDEVPLUGINDETECT
+#define BF_USBPHY_CTRL_ENDEVPLUGINDETECT_V(e)       BF_USBPHY_CTRL_ENDEVPLUGINDETECT(BV_USBPHY_CTRL_ENDEVPLUGINDETECT__##e)
+#define BFM_USBPHY_CTRL_ENDEVPLUGINDETECT_V(v)      BM_USBPHY_CTRL_ENDEVPLUGINDETECT
+#define BP_USBPHY_CTRL_HOSTDISCONDETECT_IRQ         3
+#define BM_USBPHY_CTRL_HOSTDISCONDETECT_IRQ         0x8
+#define BF_USBPHY_CTRL_HOSTDISCONDETECT_IRQ(v)      (((v) & 0x1) << 3)
+#define BFM_USBPHY_CTRL_HOSTDISCONDETECT_IRQ(v)     BM_USBPHY_CTRL_HOSTDISCONDETECT_IRQ
+#define BF_USBPHY_CTRL_HOSTDISCONDETECT_IRQ_V(e)    BF_USBPHY_CTRL_HOSTDISCONDETECT_IRQ(BV_USBPHY_CTRL_HOSTDISCONDETECT_IRQ__##e)
+#define BFM_USBPHY_CTRL_HOSTDISCONDETECT_IRQ_V(v)   BM_USBPHY_CTRL_HOSTDISCONDETECT_IRQ
+#define BP_USBPHY_CTRL_ENIRQHOSTDISCON              2
+#define BM_USBPHY_CTRL_ENIRQHOSTDISCON              0x4
+#define BF_USBPHY_CTRL_ENIRQHOSTDISCON(v)           (((v) & 0x1) << 2)
+#define BFM_USBPHY_CTRL_ENIRQHOSTDISCON(v)          BM_USBPHY_CTRL_ENIRQHOSTDISCON
+#define BF_USBPHY_CTRL_ENIRQHOSTDISCON_V(e)         BF_USBPHY_CTRL_ENIRQHOSTDISCON(BV_USBPHY_CTRL_ENIRQHOSTDISCON__##e)
+#define BFM_USBPHY_CTRL_ENIRQHOSTDISCON_V(v)        BM_USBPHY_CTRL_ENIRQHOSTDISCON
+#define BP_USBPHY_CTRL_ENHOSTDISCONDETECT           1
+#define BM_USBPHY_CTRL_ENHOSTDISCONDETECT           0x2
+#define BF_USBPHY_CTRL_ENHOSTDISCONDETECT(v)        (((v) & 0x1) << 1)
+#define BFM_USBPHY_CTRL_ENHOSTDISCONDETECT(v)       BM_USBPHY_CTRL_ENHOSTDISCONDETECT
+#define BF_USBPHY_CTRL_ENHOSTDISCONDETECT_V(e)      BF_USBPHY_CTRL_ENHOSTDISCONDETECT(BV_USBPHY_CTRL_ENHOSTDISCONDETECT__##e)
+#define BFM_USBPHY_CTRL_ENHOSTDISCONDETECT_V(v)     BM_USBPHY_CTRL_ENHOSTDISCONDETECT
+#define BP_USBPHY_CTRL_ENHSPRECHARGEXMIT            0
+#define BM_USBPHY_CTRL_ENHSPRECHARGEXMIT            0x1
+#define BF_USBPHY_CTRL_ENHSPRECHARGEXMIT(v)         (((v) & 0x1) << 0)
+#define BFM_USBPHY_CTRL_ENHSPRECHARGEXMIT(v)        BM_USBPHY_CTRL_ENHSPRECHARGEXMIT
+#define BF_USBPHY_CTRL_ENHSPRECHARGEXMIT_V(e)       BF_USBPHY_CTRL_ENHSPRECHARGEXMIT(BV_USBPHY_CTRL_ENHSPRECHARGEXMIT__##e)
+#define BFM_USBPHY_CTRL_ENHSPRECHARGEXMIT_V(v)      BM_USBPHY_CTRL_ENHSPRECHARGEXMIT
+
+#define HW_USBPHY_STATUS                                HW(USBPHY_STATUS)
+#define HWA_USBPHY_STATUS                               (0x8007c000 + 0x40)
+#define HWT_USBPHY_STATUS                               HWIO_32_RW
+#define HWN_USBPHY_STATUS                               USBPHY_STATUS
+#define HWI_USBPHY_STATUS                               
+#define BP_USBPHY_STATUS_RESUME_STATUS                  10
+#define BM_USBPHY_STATUS_RESUME_STATUS                  0x400
+#define BF_USBPHY_STATUS_RESUME_STATUS(v)               (((v) & 0x1) << 10)
+#define BFM_USBPHY_STATUS_RESUME_STATUS(v)              BM_USBPHY_STATUS_RESUME_STATUS
+#define BF_USBPHY_STATUS_RESUME_STATUS_V(e)             BF_USBPHY_STATUS_RESUME_STATUS(BV_USBPHY_STATUS_RESUME_STATUS__##e)
+#define BFM_USBPHY_STATUS_RESUME_STATUS_V(v)            BM_USBPHY_STATUS_RESUME_STATUS
+#define BP_USBPHY_STATUS_OTGID_STATUS                   8
+#define BM_USBPHY_STATUS_OTGID_STATUS                   0x100
+#define BF_USBPHY_STATUS_OTGID_STATUS(v)                (((v) & 0x1) << 8)
+#define BFM_USBPHY_STATUS_OTGID_STATUS(v)               BM_USBPHY_STATUS_OTGID_STATUS
+#define BF_USBPHY_STATUS_OTGID_STATUS_V(e)              BF_USBPHY_STATUS_OTGID_STATUS(BV_USBPHY_STATUS_OTGID_STATUS__##e)
+#define BFM_USBPHY_STATUS_OTGID_STATUS_V(v)             BM_USBPHY_STATUS_OTGID_STATUS
+#define BP_USBPHY_STATUS_DEVPLUGIN_STATUS               6
+#define BM_USBPHY_STATUS_DEVPLUGIN_STATUS               0x40
+#define BF_USBPHY_STATUS_DEVPLUGIN_STATUS(v)            (((v) & 0x1) << 6)
+#define BFM_USBPHY_STATUS_DEVPLUGIN_STATUS(v)           BM_USBPHY_STATUS_DEVPLUGIN_STATUS
+#define BF_USBPHY_STATUS_DEVPLUGIN_STATUS_V(e)          BF_USBPHY_STATUS_DEVPLUGIN_STATUS(BV_USBPHY_STATUS_DEVPLUGIN_STATUS__##e)
+#define BFM_USBPHY_STATUS_DEVPLUGIN_STATUS_V(v)         BM_USBPHY_STATUS_DEVPLUGIN_STATUS
+#define BP_USBPHY_STATUS_HOSTDISCONDETECT_STATUS        3
+#define BM_USBPHY_STATUS_HOSTDISCONDETECT_STATUS        0x8
+#define BF_USBPHY_STATUS_HOSTDISCONDETECT_STATUS(v)     (((v) & 0x1) << 3)
+#define BFM_USBPHY_STATUS_HOSTDISCONDETECT_STATUS(v)    BM_USBPHY_STATUS_HOSTDISCONDETECT_STATUS
+#define BF_USBPHY_STATUS_HOSTDISCONDETECT_STATUS_V(e)   BF_USBPHY_STATUS_HOSTDISCONDETECT_STATUS(BV_USBPHY_STATUS_HOSTDISCONDETECT_STATUS__##e)
+#define BFM_USBPHY_STATUS_HOSTDISCONDETECT_STATUS_V(v)  BM_USBPHY_STATUS_HOSTDISCONDETECT_STATUS
+
+#define HW_USBPHY_DEBUG                             HW(USBPHY_DEBUG)
+#define HWA_USBPHY_DEBUG                            (0x8007c000 + 0x50)
+#define HWT_USBPHY_DEBUG                            HWIO_32_RW
+#define HWN_USBPHY_DEBUG                            USBPHY_DEBUG
+#define HWI_USBPHY_DEBUG                            
+#define HW_USBPHY_DEBUG_SET                         HW(USBPHY_DEBUG_SET)
+#define HWA_USBPHY_DEBUG_SET                        (HWA_USBPHY_DEBUG + 0x4)
+#define HWT_USBPHY_DEBUG_SET                        HWIO_32_WO
+#define HWN_USBPHY_DEBUG_SET                        USBPHY_DEBUG
+#define HWI_USBPHY_DEBUG_SET                        
+#define HW_USBPHY_DEBUG_CLR                         HW(USBPHY_DEBUG_CLR)
+#define HWA_USBPHY_DEBUG_CLR                        (HWA_USBPHY_DEBUG + 0x8)
+#define HWT_USBPHY_DEBUG_CLR                        HWIO_32_WO
+#define HWN_USBPHY_DEBUG_CLR                        USBPHY_DEBUG
+#define HWI_USBPHY_DEBUG_CLR                        
+#define HW_USBPHY_DEBUG_TOG                         HW(USBPHY_DEBUG_TOG)
+#define HWA_USBPHY_DEBUG_TOG                        (HWA_USBPHY_DEBUG + 0xc)
+#define HWT_USBPHY_DEBUG_TOG                        HWIO_32_WO
+#define HWN_USBPHY_DEBUG_TOG                        USBPHY_DEBUG
+#define HWI_USBPHY_DEBUG_TOG                        
+#define BP_USBPHY_DEBUG_CLKGATE                     30
+#define BM_USBPHY_DEBUG_CLKGATE                     0x40000000
+#define BF_USBPHY_DEBUG_CLKGATE(v)                  (((v) & 0x1) << 30)
+#define BFM_USBPHY_DEBUG_CLKGATE(v)                 BM_USBPHY_DEBUG_CLKGATE
+#define BF_USBPHY_DEBUG_CLKGATE_V(e)                BF_USBPHY_DEBUG_CLKGATE(BV_USBPHY_DEBUG_CLKGATE__##e)
+#define BFM_USBPHY_DEBUG_CLKGATE_V(v)               BM_USBPHY_DEBUG_CLKGATE
+#define BP_USBPHY_DEBUG_SQUELCHRESETLENGTH          25
+#define BM_USBPHY_DEBUG_SQUELCHRESETLENGTH          0x1e000000
+#define BF_USBPHY_DEBUG_SQUELCHRESETLENGTH(v)       (((v) & 0xf) << 25)
+#define BFM_USBPHY_DEBUG_SQUELCHRESETLENGTH(v)      BM_USBPHY_DEBUG_SQUELCHRESETLENGTH
+#define BF_USBPHY_DEBUG_SQUELCHRESETLENGTH_V(e)     BF_USBPHY_DEBUG_SQUELCHRESETLENGTH(BV_USBPHY_DEBUG_SQUELCHRESETLENGTH__##e)
+#define BFM_USBPHY_DEBUG_SQUELCHRESETLENGTH_V(v)    BM_USBPHY_DEBUG_SQUELCHRESETLENGTH
+#define BP_USBPHY_DEBUG_ENSQUELCHRESET              24
+#define BM_USBPHY_DEBUG_ENSQUELCHRESET              0x1000000
+#define BF_USBPHY_DEBUG_ENSQUELCHRESET(v)           (((v) & 0x1) << 24)
+#define BFM_USBPHY_DEBUG_ENSQUELCHRESET(v)          BM_USBPHY_DEBUG_ENSQUELCHRESET
+#define BF_USBPHY_DEBUG_ENSQUELCHRESET_V(e)         BF_USBPHY_DEBUG_ENSQUELCHRESET(BV_USBPHY_DEBUG_ENSQUELCHRESET__##e)
+#define BFM_USBPHY_DEBUG_ENSQUELCHRESET_V(v)        BM_USBPHY_DEBUG_ENSQUELCHRESET
+#define BP_USBPHY_DEBUG_SQUELCHRESETCOUNT           16
+#define BM_USBPHY_DEBUG_SQUELCHRESETCOUNT           0x1f0000
+#define BF_USBPHY_DEBUG_SQUELCHRESETCOUNT(v)        (((v) & 0x1f) << 16)
+#define BFM_USBPHY_DEBUG_SQUELCHRESETCOUNT(v)       BM_USBPHY_DEBUG_SQUELCHRESETCOUNT
+#define BF_USBPHY_DEBUG_SQUELCHRESETCOUNT_V(e)      BF_USBPHY_DEBUG_SQUELCHRESETCOUNT(BV_USBPHY_DEBUG_SQUELCHRESETCOUNT__##e)
+#define BFM_USBPHY_DEBUG_SQUELCHRESETCOUNT_V(v)     BM_USBPHY_DEBUG_SQUELCHRESETCOUNT
+#define BP_USBPHY_DEBUG_ENTX2RXCOUNT                12
+#define BM_USBPHY_DEBUG_ENTX2RXCOUNT                0x1000
+#define BF_USBPHY_DEBUG_ENTX2RXCOUNT(v)             (((v) & 0x1) << 12)
+#define BFM_USBPHY_DEBUG_ENTX2RXCOUNT(v)            BM_USBPHY_DEBUG_ENTX2RXCOUNT
+#define BF_USBPHY_DEBUG_ENTX2RXCOUNT_V(e)           BF_USBPHY_DEBUG_ENTX2RXCOUNT(BV_USBPHY_DEBUG_ENTX2RXCOUNT__##e)
+#define BFM_USBPHY_DEBUG_ENTX2RXCOUNT_V(v)          BM_USBPHY_DEBUG_ENTX2RXCOUNT
+#define BP_USBPHY_DEBUG_TX2RXCOUNT                  8
+#define BM_USBPHY_DEBUG_TX2RXCOUNT                  0xf00
+#define BF_USBPHY_DEBUG_TX2RXCOUNT(v)               (((v) & 0xf) << 8)
+#define BFM_USBPHY_DEBUG_TX2RXCOUNT(v)              BM_USBPHY_DEBUG_TX2RXCOUNT
+#define BF_USBPHY_DEBUG_TX2RXCOUNT_V(e)             BF_USBPHY_DEBUG_TX2RXCOUNT(BV_USBPHY_DEBUG_TX2RXCOUNT__##e)
+#define BFM_USBPHY_DEBUG_TX2RXCOUNT_V(v)            BM_USBPHY_DEBUG_TX2RXCOUNT
+#define BP_USBPHY_DEBUG_ENHSTPULLDOWN               4
+#define BM_USBPHY_DEBUG_ENHSTPULLDOWN               0x30
+#define BF_USBPHY_DEBUG_ENHSTPULLDOWN(v)            (((v) & 0x3) << 4)
+#define BFM_USBPHY_DEBUG_ENHSTPULLDOWN(v)           BM_USBPHY_DEBUG_ENHSTPULLDOWN
+#define BF_USBPHY_DEBUG_ENHSTPULLDOWN_V(e)          BF_USBPHY_DEBUG_ENHSTPULLDOWN(BV_USBPHY_DEBUG_ENHSTPULLDOWN__##e)
+#define BFM_USBPHY_DEBUG_ENHSTPULLDOWN_V(v)         BM_USBPHY_DEBUG_ENHSTPULLDOWN
+#define BP_USBPHY_DEBUG_HSTPULLDOWN                 2
+#define BM_USBPHY_DEBUG_HSTPULLDOWN                 0xc
+#define BF_USBPHY_DEBUG_HSTPULLDOWN(v)              (((v) & 0x3) << 2)
+#define BFM_USBPHY_DEBUG_HSTPULLDOWN(v)             BM_USBPHY_DEBUG_HSTPULLDOWN
+#define BF_USBPHY_DEBUG_HSTPULLDOWN_V(e)            BF_USBPHY_DEBUG_HSTPULLDOWN(BV_USBPHY_DEBUG_HSTPULLDOWN__##e)
+#define BFM_USBPHY_DEBUG_HSTPULLDOWN_V(v)           BM_USBPHY_DEBUG_HSTPULLDOWN
+#define BP_USBPHY_DEBUG_DEBUG_INTERFACE_HOLD        1
+#define BM_USBPHY_DEBUG_DEBUG_INTERFACE_HOLD        0x2
+#define BF_USBPHY_DEBUG_DEBUG_INTERFACE_HOLD(v)     (((v) & 0x1) << 1)
+#define BFM_USBPHY_DEBUG_DEBUG_INTERFACE_HOLD(v)    BM_USBPHY_DEBUG_DEBUG_INTERFACE_HOLD
+#define BF_USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_V(e)   BF_USBPHY_DEBUG_DEBUG_INTERFACE_HOLD(BV_USBPHY_DEBUG_DEBUG_INTERFACE_HOLD__##e)
+#define BFM_USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_V(v)  BM_USBPHY_DEBUG_DEBUG_INTERFACE_HOLD
+#define BP_USBPHY_DEBUG_OTGIDPIOLOCK                0
+#define BM_USBPHY_DEBUG_OTGIDPIOLOCK                0x1
+#define BF_USBPHY_DEBUG_OTGIDPIOLOCK(v)             (((v) & 0x1) << 0)
+#define BFM_USBPHY_DEBUG_OTGIDPIOLOCK(v)            BM_USBPHY_DEBUG_OTGIDPIOLOCK
+#define BF_USBPHY_DEBUG_OTGIDPIOLOCK_V(e)           BF_USBPHY_DEBUG_OTGIDPIOLOCK(BV_USBPHY_DEBUG_OTGIDPIOLOCK__##e)
+#define BFM_USBPHY_DEBUG_OTGIDPIOLOCK_V(v)          BM_USBPHY_DEBUG_OTGIDPIOLOCK
+
+#define HW_USBPHY_DEBUG0_STATUS                                 HW(USBPHY_DEBUG0_STATUS)
+#define HWA_USBPHY_DEBUG0_STATUS                                (0x8007c000 + 0x60)
+#define HWT_USBPHY_DEBUG0_STATUS                                HWIO_32_RW
+#define HWN_USBPHY_DEBUG0_STATUS                                USBPHY_DEBUG0_STATUS
+#define HWI_USBPHY_DEBUG0_STATUS                                
+#define BP_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT                   26
+#define BM_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT                   0xfc000000
+#define BF_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT(v)                (((v) & 0x3f) << 26)
+#define BFM_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT(v)               BM_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT
+#define BF_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_V(e)              BF_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT(BV_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT__##e)
+#define BFM_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_V(v)             BM_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT
+#define BP_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT         16
+#define BM_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT         0x3ff0000
+#define BF_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT(v)      (((v) & 0x3ff) << 16)
+#define BFM_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT(v)     BM_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT
+#define BF_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_V(e)    BF_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT(BV_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT__##e)
+#define BFM_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_V(v)   BM_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT
+#define BP_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT            0
+#define BM_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT            0xffff
+#define BF_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT(v)         (((v) & 0xffff) << 0)
+#define BFM_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT(v)        BM_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT
+#define BF_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_V(e)       BF_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT(BV_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT__##e)
+#define BFM_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_V(v)      BM_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT
+
+#define HW_USBPHY_DEBUG1_STATUS                     HW(USBPHY_DEBUG1_STATUS)
+#define HWA_USBPHY_DEBUG1_STATUS                    (0x8007c000 + 0x70)
+#define HWT_USBPHY_DEBUG1_STATUS                    HWIO_32_RW
+#define HWN_USBPHY_DEBUG1_STATUS                    USBPHY_DEBUG1_STATUS
+#define HWI_USBPHY_DEBUG1_STATUS                    
+#define BP_USBPHY_DEBUG1_STATUS_UTMI_TX_DATA        16
+#define BM_USBPHY_DEBUG1_STATUS_UTMI_TX_DATA        0xffff0000
+#define BF_USBPHY_DEBUG1_STATUS_UTMI_TX_DATA(v)     (((v) & 0xffff) << 16)
+#define BFM_USBPHY_DEBUG1_STATUS_UTMI_TX_DATA(v)    BM_USBPHY_DEBUG1_STATUS_UTMI_TX_DATA
+#define BF_USBPHY_DEBUG1_STATUS_UTMI_TX_DATA_V(e)   BF_USBPHY_DEBUG1_STATUS_UTMI_TX_DATA(BV_USBPHY_DEBUG1_STATUS_UTMI_TX_DATA__##e)
+#define BFM_USBPHY_DEBUG1_STATUS_UTMI_TX_DATA_V(v)  BM_USBPHY_DEBUG1_STATUS_UTMI_TX_DATA
+#define BP_USBPHY_DEBUG1_STATUS_UTMI_RX_DATA        0
+#define BM_USBPHY_DEBUG1_STATUS_UTMI_RX_DATA        0xffff
+#define BF_USBPHY_DEBUG1_STATUS_UTMI_RX_DATA(v)     (((v) & 0xffff) << 0)
+#define BFM_USBPHY_DEBUG1_STATUS_UTMI_RX_DATA(v)    BM_USBPHY_DEBUG1_STATUS_UTMI_RX_DATA
+#define BF_USBPHY_DEBUG1_STATUS_UTMI_RX_DATA_V(e)   BF_USBPHY_DEBUG1_STATUS_UTMI_RX_DATA(BV_USBPHY_DEBUG1_STATUS_UTMI_RX_DATA__##e)
+#define BFM_USBPHY_DEBUG1_STATUS_UTMI_RX_DATA_V(v)  BM_USBPHY_DEBUG1_STATUS_UTMI_RX_DATA
+
+#define HW_USBPHY_DEBUG2_STATUS                         HW(USBPHY_DEBUG2_STATUS)
+#define HWA_USBPHY_DEBUG2_STATUS                        (0x8007c000 + 0x80)
+#define HWT_USBPHY_DEBUG2_STATUS                        HWIO_32_RW
+#define HWN_USBPHY_DEBUG2_STATUS                        USBPHY_DEBUG2_STATUS
+#define HWI_USBPHY_DEBUG2_STATUS                        
+#define BP_USBPHY_DEBUG2_STATUS_UTMI_TXVALIDH           22
+#define BM_USBPHY_DEBUG2_STATUS_UTMI_TXVALIDH           0x400000
+#define BF_USBPHY_DEBUG2_STATUS_UTMI_TXVALIDH(v)        (((v) & 0x1) << 22)
+#define BFM_USBPHY_DEBUG2_STATUS_UTMI_TXVALIDH(v)       BM_USBPHY_DEBUG2_STATUS_UTMI_TXVALIDH
+#define BF_USBPHY_DEBUG2_STATUS_UTMI_TXVALIDH_V(e)      BF_USBPHY_DEBUG2_STATUS_UTMI_TXVALIDH(BV_USBPHY_DEBUG2_STATUS_UTMI_TXVALIDH__##e)
+#define BFM_USBPHY_DEBUG2_STATUS_UTMI_TXVALIDH_V(v)     BM_USBPHY_DEBUG2_STATUS_UTMI_TXVALIDH
+#define BP_USBPHY_DEBUG2_STATUS_UTMI_TXVALID            21
+#define BM_USBPHY_DEBUG2_STATUS_UTMI_TXVALID            0x200000
+#define BF_USBPHY_DEBUG2_STATUS_UTMI_TXVALID(v)         (((v) & 0x1) << 21)
+#define BFM_USBPHY_DEBUG2_STATUS_UTMI_TXVALID(v)        BM_USBPHY_DEBUG2_STATUS_UTMI_TXVALID
+#define BF_USBPHY_DEBUG2_STATUS_UTMI_TXVALID_V(e)       BF_USBPHY_DEBUG2_STATUS_UTMI_TXVALID(BV_USBPHY_DEBUG2_STATUS_UTMI_TXVALID__##e)
+#define BFM_USBPHY_DEBUG2_STATUS_UTMI_TXVALID_V(v)      BM_USBPHY_DEBUG2_STATUS_UTMI_TXVALID
+#define BP_USBPHY_DEBUG2_STATUS_UTMI_TERMSELECT         20
+#define BM_USBPHY_DEBUG2_STATUS_UTMI_TERMSELECT         0x100000
+#define BF_USBPHY_DEBUG2_STATUS_UTMI_TERMSELECT(v)      (((v) & 0x1) << 20)
+#define BFM_USBPHY_DEBUG2_STATUS_UTMI_TERMSELECT(v)     BM_USBPHY_DEBUG2_STATUS_UTMI_TERMSELECT
+#define BF_USBPHY_DEBUG2_STATUS_UTMI_TERMSELECT_V(e)    BF_USBPHY_DEBUG2_STATUS_UTMI_TERMSELECT(BV_USBPHY_DEBUG2_STATUS_UTMI_TERMSELECT__##e)
+#define BFM_USBPHY_DEBUG2_STATUS_UTMI_TERMSELECT_V(v)   BM_USBPHY_DEBUG2_STATUS_UTMI_TERMSELECT
+#define BP_USBPHY_DEBUG2_STATUS_UTMI_XCVRSELECT         18
+#define BM_USBPHY_DEBUG2_STATUS_UTMI_XCVRSELECT         0xc0000
+#define BF_USBPHY_DEBUG2_STATUS_UTMI_XCVRSELECT(v)      (((v) & 0x3) << 18)
+#define BFM_USBPHY_DEBUG2_STATUS_UTMI_XCVRSELECT(v)     BM_USBPHY_DEBUG2_STATUS_UTMI_XCVRSELECT
+#define BF_USBPHY_DEBUG2_STATUS_UTMI_XCVRSELECT_V(e)    BF_USBPHY_DEBUG2_STATUS_UTMI_XCVRSELECT(BV_USBPHY_DEBUG2_STATUS_UTMI_XCVRSELECT__##e)
+#define BFM_USBPHY_DEBUG2_STATUS_UTMI_XCVRSELECT_V(v)   BM_USBPHY_DEBUG2_STATUS_UTMI_XCVRSELECT
+#define BP_USBPHY_DEBUG2_STATUS_UTMI_OPMODE             16
+#define BM_USBPHY_DEBUG2_STATUS_UTMI_OPMODE             0x30000
+#define BF_USBPHY_DEBUG2_STATUS_UTMI_OPMODE(v)          (((v) & 0x3) << 16)
+#define BFM_USBPHY_DEBUG2_STATUS_UTMI_OPMODE(v)         BM_USBPHY_DEBUG2_STATUS_UTMI_OPMODE
+#define BF_USBPHY_DEBUG2_STATUS_UTMI_OPMODE_V(e)        BF_USBPHY_DEBUG2_STATUS_UTMI_OPMODE(BV_USBPHY_DEBUG2_STATUS_UTMI_OPMODE__##e)
+#define BFM_USBPHY_DEBUG2_STATUS_UTMI_OPMODE_V(v)       BM_USBPHY_DEBUG2_STATUS_UTMI_OPMODE
+#define BP_USBPHY_DEBUG2_STATUS_UTMI_LINESTATE          6
+#define BM_USBPHY_DEBUG2_STATUS_UTMI_LINESTATE          0xc0
+#define BF_USBPHY_DEBUG2_STATUS_UTMI_LINESTATE(v)       (((v) & 0x3) << 6)
+#define BFM_USBPHY_DEBUG2_STATUS_UTMI_LINESTATE(v)      BM_USBPHY_DEBUG2_STATUS_UTMI_LINESTATE
+#define BF_USBPHY_DEBUG2_STATUS_UTMI_LINESTATE_V(e)     BF_USBPHY_DEBUG2_STATUS_UTMI_LINESTATE(BV_USBPHY_DEBUG2_STATUS_UTMI_LINESTATE__##e)
+#define BFM_USBPHY_DEBUG2_STATUS_UTMI_LINESTATE_V(v)    BM_USBPHY_DEBUG2_STATUS_UTMI_LINESTATE
+#define BP_USBPHY_DEBUG2_STATUS_UTMI_SUSPENDM           5
+#define BM_USBPHY_DEBUG2_STATUS_UTMI_SUSPENDM           0x20
+#define BF_USBPHY_DEBUG2_STATUS_UTMI_SUSPENDM(v)        (((v) & 0x1) << 5)
+#define BFM_USBPHY_DEBUG2_STATUS_UTMI_SUSPENDM(v)       BM_USBPHY_DEBUG2_STATUS_UTMI_SUSPENDM
+#define BF_USBPHY_DEBUG2_STATUS_UTMI_SUSPENDM_V(e)      BF_USBPHY_DEBUG2_STATUS_UTMI_SUSPENDM(BV_USBPHY_DEBUG2_STATUS_UTMI_SUSPENDM__##e)
+#define BFM_USBPHY_DEBUG2_STATUS_UTMI_SUSPENDM_V(v)     BM_USBPHY_DEBUG2_STATUS_UTMI_SUSPENDM
+#define BP_USBPHY_DEBUG2_STATUS_UTMI_RXVALIDH           4
+#define BM_USBPHY_DEBUG2_STATUS_UTMI_RXVALIDH           0x10
+#define BF_USBPHY_DEBUG2_STATUS_UTMI_RXVALIDH(v)        (((v) & 0x1) << 4)
+#define BFM_USBPHY_DEBUG2_STATUS_UTMI_RXVALIDH(v)       BM_USBPHY_DEBUG2_STATUS_UTMI_RXVALIDH
+#define BF_USBPHY_DEBUG2_STATUS_UTMI_RXVALIDH_V(e)      BF_USBPHY_DEBUG2_STATUS_UTMI_RXVALIDH(BV_USBPHY_DEBUG2_STATUS_UTMI_RXVALIDH__##e)
+#define BFM_USBPHY_DEBUG2_STATUS_UTMI_RXVALIDH_V(v)     BM_USBPHY_DEBUG2_STATUS_UTMI_RXVALIDH
+#define BP_USBPHY_DEBUG2_STATUS_UTMI_RXVALID            3
+#define BM_USBPHY_DEBUG2_STATUS_UTMI_RXVALID            0x8
+#define BF_USBPHY_DEBUG2_STATUS_UTMI_RXVALID(v)         (((v) & 0x1) << 3)
+#define BFM_USBPHY_DEBUG2_STATUS_UTMI_RXVALID(v)        BM_USBPHY_DEBUG2_STATUS_UTMI_RXVALID
+#define BF_USBPHY_DEBUG2_STATUS_UTMI_RXVALID_V(e)       BF_USBPHY_DEBUG2_STATUS_UTMI_RXVALID(BV_USBPHY_DEBUG2_STATUS_UTMI_RXVALID__##e)
+#define BFM_USBPHY_DEBUG2_STATUS_UTMI_RXVALID_V(v)      BM_USBPHY_DEBUG2_STATUS_UTMI_RXVALID
+#define BP_USBPHY_DEBUG2_STATUS_UTMI_RXACTIVE           2
+#define BM_USBPHY_DEBUG2_STATUS_UTMI_RXACTIVE           0x4
+#define BF_USBPHY_DEBUG2_STATUS_UTMI_RXACTIVE(v)        (((v) & 0x1) << 2)
+#define BFM_USBPHY_DEBUG2_STATUS_UTMI_RXACTIVE(v)       BM_USBPHY_DEBUG2_STATUS_UTMI_RXACTIVE
+#define BF_USBPHY_DEBUG2_STATUS_UTMI_RXACTIVE_V(e)      BF_USBPHY_DEBUG2_STATUS_UTMI_RXACTIVE(BV_USBPHY_DEBUG2_STATUS_UTMI_RXACTIVE__##e)
+#define BFM_USBPHY_DEBUG2_STATUS_UTMI_RXACTIVE_V(v)     BM_USBPHY_DEBUG2_STATUS_UTMI_RXACTIVE
+#define BP_USBPHY_DEBUG2_STATUS_UTMI_RXERROR            1
+#define BM_USBPHY_DEBUG2_STATUS_UTMI_RXERROR            0x2
+#define BF_USBPHY_DEBUG2_STATUS_UTMI_RXERROR(v)         (((v) & 0x1) << 1)
+#define BFM_USBPHY_DEBUG2_STATUS_UTMI_RXERROR(v)        BM_USBPHY_DEBUG2_STATUS_UTMI_RXERROR
+#define BF_USBPHY_DEBUG2_STATUS_UTMI_RXERROR_V(e)       BF_USBPHY_DEBUG2_STATUS_UTMI_RXERROR(BV_USBPHY_DEBUG2_STATUS_UTMI_RXERROR__##e)
+#define BFM_USBPHY_DEBUG2_STATUS_UTMI_RXERROR_V(v)      BM_USBPHY_DEBUG2_STATUS_UTMI_RXERROR
+#define BP_USBPHY_DEBUG2_STATUS_UTMI_TXREADY            0
+#define BM_USBPHY_DEBUG2_STATUS_UTMI_TXREADY            0x1
+#define BF_USBPHY_DEBUG2_STATUS_UTMI_TXREADY(v)         (((v) & 0x1) << 0)
+#define BFM_USBPHY_DEBUG2_STATUS_UTMI_TXREADY(v)        BM_USBPHY_DEBUG2_STATUS_UTMI_TXREADY
+#define BF_USBPHY_DEBUG2_STATUS_UTMI_TXREADY_V(e)       BF_USBPHY_DEBUG2_STATUS_UTMI_TXREADY(BV_USBPHY_DEBUG2_STATUS_UTMI_TXREADY__##e)
+#define BFM_USBPHY_DEBUG2_STATUS_UTMI_TXREADY_V(v)      BM_USBPHY_DEBUG2_STATUS_UTMI_TXREADY
+
+#define HW_USBPHY_DEBUG3_STATUS                         HW(USBPHY_DEBUG3_STATUS)
+#define HWA_USBPHY_DEBUG3_STATUS                        (0x8007c000 + 0x90)
+#define HWT_USBPHY_DEBUG3_STATUS                        HWIO_32_RW
+#define HWN_USBPHY_DEBUG3_STATUS                        USBPHY_DEBUG3_STATUS
+#define HWI_USBPHY_DEBUG3_STATUS                        
+#define BP_USBPHY_DEBUG3_STATUS_B_CNT_FSM               28
+#define BM_USBPHY_DEBUG3_STATUS_B_CNT_FSM               0x70000000
+#define BF_USBPHY_DEBUG3_STATUS_B_CNT_FSM(v)            (((v) & 0x7) << 28)
+#define BFM_USBPHY_DEBUG3_STATUS_B_CNT_FSM(v)           BM_USBPHY_DEBUG3_STATUS_B_CNT_FSM
+#define BF_USBPHY_DEBUG3_STATUS_B_CNT_FSM_V(e)          BF_USBPHY_DEBUG3_STATUS_B_CNT_FSM(BV_USBPHY_DEBUG3_STATUS_B_CNT_FSM__##e)
+#define BFM_USBPHY_DEBUG3_STATUS_B_CNT_FSM_V(v)         BM_USBPHY_DEBUG3_STATUS_B_CNT_FSM
+#define BP_USBPHY_DEBUG3_STATUS_SQ_UNLOCK_FSM           23
+#define BM_USBPHY_DEBUG3_STATUS_SQ_UNLOCK_FSM           0x3800000
+#define BF_USBPHY_DEBUG3_STATUS_SQ_UNLOCK_FSM(v)        (((v) & 0x7) << 23)
+#define BFM_USBPHY_DEBUG3_STATUS_SQ_UNLOCK_FSM(v)       BM_USBPHY_DEBUG3_STATUS_SQ_UNLOCK_FSM
+#define BF_USBPHY_DEBUG3_STATUS_SQ_UNLOCK_FSM_V(e)      BF_USBPHY_DEBUG3_STATUS_SQ_UNLOCK_FSM(BV_USBPHY_DEBUG3_STATUS_SQ_UNLOCK_FSM__##e)
+#define BFM_USBPHY_DEBUG3_STATUS_SQ_UNLOCK_FSM_V(v)     BM_USBPHY_DEBUG3_STATUS_SQ_UNLOCK_FSM
+#define BP_USBPHY_DEBUG3_STATUS_BIT_CNT                 12
+#define BM_USBPHY_DEBUG3_STATUS_BIT_CNT                 0x3ff000
+#define BF_USBPHY_DEBUG3_STATUS_BIT_CNT(v)              (((v) & 0x3ff) << 12)
+#define BFM_USBPHY_DEBUG3_STATUS_BIT_CNT(v)             BM_USBPHY_DEBUG3_STATUS_BIT_CNT
+#define BF_USBPHY_DEBUG3_STATUS_BIT_CNT_V(e)            BF_USBPHY_DEBUG3_STATUS_BIT_CNT(BV_USBPHY_DEBUG3_STATUS_BIT_CNT__##e)
+#define BFM_USBPHY_DEBUG3_STATUS_BIT_CNT_V(v)           BM_USBPHY_DEBUG3_STATUS_BIT_CNT
+#define BP_USBPHY_DEBUG3_STATUS_MAIN_HS_RX_FSM          8
+#define BM_USBPHY_DEBUG3_STATUS_MAIN_HS_RX_FSM          0xf00
+#define BF_USBPHY_DEBUG3_STATUS_MAIN_HS_RX_FSM(v)       (((v) & 0xf) << 8)
+#define BFM_USBPHY_DEBUG3_STATUS_MAIN_HS_RX_FSM(v)      BM_USBPHY_DEBUG3_STATUS_MAIN_HS_RX_FSM
+#define BF_USBPHY_DEBUG3_STATUS_MAIN_HS_RX_FSM_V(e)     BF_USBPHY_DEBUG3_STATUS_MAIN_HS_RX_FSM(BV_USBPHY_DEBUG3_STATUS_MAIN_HS_RX_FSM__##e)
+#define BFM_USBPHY_DEBUG3_STATUS_MAIN_HS_RX_FSM_V(v)    BM_USBPHY_DEBUG3_STATUS_MAIN_HS_RX_FSM
+#define BP_USBPHY_DEBUG3_STATUS_UNSTUFF_BIT_CNT         0
+#define BM_USBPHY_DEBUG3_STATUS_UNSTUFF_BIT_CNT         0xff
+#define BF_USBPHY_DEBUG3_STATUS_UNSTUFF_BIT_CNT(v)      (((v) & 0xff) << 0)
+#define BFM_USBPHY_DEBUG3_STATUS_UNSTUFF_BIT_CNT(v)     BM_USBPHY_DEBUG3_STATUS_UNSTUFF_BIT_CNT
+#define BF_USBPHY_DEBUG3_STATUS_UNSTUFF_BIT_CNT_V(e)    BF_USBPHY_DEBUG3_STATUS_UNSTUFF_BIT_CNT(BV_USBPHY_DEBUG3_STATUS_UNSTUFF_BIT_CNT__##e)
+#define BFM_USBPHY_DEBUG3_STATUS_UNSTUFF_BIT_CNT_V(v)   BM_USBPHY_DEBUG3_STATUS_UNSTUFF_BIT_CNT
+
+#define HW_USBPHY_DEBUG4_STATUS                 HW(USBPHY_DEBUG4_STATUS)
+#define HWA_USBPHY_DEBUG4_STATUS                (0x8007c000 + 0xa0)
+#define HWT_USBPHY_DEBUG4_STATUS                HWIO_32_RW
+#define HWN_USBPHY_DEBUG4_STATUS                USBPHY_DEBUG4_STATUS
+#define HWI_USBPHY_DEBUG4_STATUS                
+#define BP_USBPHY_DEBUG4_STATUS_BYTE_FSM        16
+#define BM_USBPHY_DEBUG4_STATUS_BYTE_FSM        0x1fff0000
+#define BF_USBPHY_DEBUG4_STATUS_BYTE_FSM(v)     (((v) & 0x1fff) << 16)
+#define BFM_USBPHY_DEBUG4_STATUS_BYTE_FSM(v)    BM_USBPHY_DEBUG4_STATUS_BYTE_FSM
+#define BF_USBPHY_DEBUG4_STATUS_BYTE_FSM_V(e)   BF_USBPHY_DEBUG4_STATUS_BYTE_FSM(BV_USBPHY_DEBUG4_STATUS_BYTE_FSM__##e)
+#define BFM_USBPHY_DEBUG4_STATUS_BYTE_FSM_V(v)  BM_USBPHY_DEBUG4_STATUS_BYTE_FSM
+#define BP_USBPHY_DEBUG4_STATUS_SND_FSM         0
+#define BM_USBPHY_DEBUG4_STATUS_SND_FSM         0x3fff
+#define BF_USBPHY_DEBUG4_STATUS_SND_FSM(v)      (((v) & 0x3fff) << 0)
+#define BFM_USBPHY_DEBUG4_STATUS_SND_FSM(v)     BM_USBPHY_DEBUG4_STATUS_SND_FSM
+#define BF_USBPHY_DEBUG4_STATUS_SND_FSM_V(e)    BF_USBPHY_DEBUG4_STATUS_SND_FSM(BV_USBPHY_DEBUG4_STATUS_SND_FSM__##e)
+#define BFM_USBPHY_DEBUG4_STATUS_SND_FSM_V(v)   BM_USBPHY_DEBUG4_STATUS_SND_FSM
+
+#define HW_USBPHY_DEBUG5_STATUS                     HW(USBPHY_DEBUG5_STATUS)
+#define HWA_USBPHY_DEBUG5_STATUS                    (0x8007c000 + 0xb0)
+#define HWT_USBPHY_DEBUG5_STATUS                    HWIO_32_RW
+#define HWN_USBPHY_DEBUG5_STATUS                    USBPHY_DEBUG5_STATUS
+#define HWI_USBPHY_DEBUG5_STATUS                    
+#define BP_USBPHY_DEBUG5_STATUS_MAIN_FSM            24
+#define BM_USBPHY_DEBUG5_STATUS_MAIN_FSM            0xf000000
+#define BF_USBPHY_DEBUG5_STATUS_MAIN_FSM(v)         (((v) & 0xf) << 24)
+#define BFM_USBPHY_DEBUG5_STATUS_MAIN_FSM(v)        BM_USBPHY_DEBUG5_STATUS_MAIN_FSM
+#define BF_USBPHY_DEBUG5_STATUS_MAIN_FSM_V(e)       BF_USBPHY_DEBUG5_STATUS_MAIN_FSM(BV_USBPHY_DEBUG5_STATUS_MAIN_FSM__##e)
+#define BFM_USBPHY_DEBUG5_STATUS_MAIN_FSM_V(v)      BM_USBPHY_DEBUG5_STATUS_MAIN_FSM
+#define BP_USBPHY_DEBUG5_STATUS_SYNC_FSM            16
+#define BM_USBPHY_DEBUG5_STATUS_SYNC_FSM            0x3f0000
+#define BF_USBPHY_DEBUG5_STATUS_SYNC_FSM(v)         (((v) & 0x3f) << 16)
+#define BFM_USBPHY_DEBUG5_STATUS_SYNC_FSM(v)        BM_USBPHY_DEBUG5_STATUS_SYNC_FSM
+#define BF_USBPHY_DEBUG5_STATUS_SYNC_FSM_V(e)       BF_USBPHY_DEBUG5_STATUS_SYNC_FSM(BV_USBPHY_DEBUG5_STATUS_SYNC_FSM__##e)
+#define BFM_USBPHY_DEBUG5_STATUS_SYNC_FSM_V(v)      BM_USBPHY_DEBUG5_STATUS_SYNC_FSM
+#define BP_USBPHY_DEBUG5_STATUS_PRECHARGE_FSM       12
+#define BM_USBPHY_DEBUG5_STATUS_PRECHARGE_FSM       0x7000
+#define BF_USBPHY_DEBUG5_STATUS_PRECHARGE_FSM(v)    (((v) & 0x7) << 12)
+#define BFM_USBPHY_DEBUG5_STATUS_PRECHARGE_FSM(v)   BM_USBPHY_DEBUG5_STATUS_PRECHARGE_FSM
+#define BF_USBPHY_DEBUG5_STATUS_PRECHARGE_FSM_V(e)  BF_USBPHY_DEBUG5_STATUS_PRECHARGE_FSM(BV_USBPHY_DEBUG5_STATUS_PRECHARGE_FSM__##e)
+#define BFM_USBPHY_DEBUG5_STATUS_PRECHARGE_FSM_V(v) BM_USBPHY_DEBUG5_STATUS_PRECHARGE_FSM
+#define BP_USBPHY_DEBUG5_STATUS_SHIFT_FSM           8
+#define BM_USBPHY_DEBUG5_STATUS_SHIFT_FSM           0x700
+#define BF_USBPHY_DEBUG5_STATUS_SHIFT_FSM(v)        (((v) & 0x7) << 8)
+#define BFM_USBPHY_DEBUG5_STATUS_SHIFT_FSM(v)       BM_USBPHY_DEBUG5_STATUS_SHIFT_FSM
+#define BF_USBPHY_DEBUG5_STATUS_SHIFT_FSM_V(e)      BF_USBPHY_DEBUG5_STATUS_SHIFT_FSM(BV_USBPHY_DEBUG5_STATUS_SHIFT_FSM__##e)
+#define BFM_USBPHY_DEBUG5_STATUS_SHIFT_FSM_V(v)     BM_USBPHY_DEBUG5_STATUS_SHIFT_FSM
+#define BP_USBPHY_DEBUG5_STATUS_SOF_FSM             0
+#define BM_USBPHY_DEBUG5_STATUS_SOF_FSM             0x1f
+#define BF_USBPHY_DEBUG5_STATUS_SOF_FSM(v)          (((v) & 0x1f) << 0)
+#define BFM_USBPHY_DEBUG5_STATUS_SOF_FSM(v)         BM_USBPHY_DEBUG5_STATUS_SOF_FSM
+#define BF_USBPHY_DEBUG5_STATUS_SOF_FSM_V(e)        BF_USBPHY_DEBUG5_STATUS_SOF_FSM(BV_USBPHY_DEBUG5_STATUS_SOF_FSM__##e)
+#define BFM_USBPHY_DEBUG5_STATUS_SOF_FSM_V(v)       BM_USBPHY_DEBUG5_STATUS_SOF_FSM
+
+#define HW_USBPHY_DEBUG6_STATUS                     HW(USBPHY_DEBUG6_STATUS)
+#define HWA_USBPHY_DEBUG6_STATUS                    (0x8007c000 + 0xc0)
+#define HWT_USBPHY_DEBUG6_STATUS                    HWIO_32_RW
+#define HWN_USBPHY_DEBUG6_STATUS                    USBPHY_DEBUG6_STATUS
+#define HWI_USBPHY_DEBUG6_STATUS                    
+#define BP_USBPHY_DEBUG6_STATUS_FIRST_EOP_FSM       8
+#define BM_USBPHY_DEBUG6_STATUS_FIRST_EOP_FSM       0x700
+#define BF_USBPHY_DEBUG6_STATUS_FIRST_EOP_FSM(v)    (((v) & 0x7) << 8)
+#define BFM_USBPHY_DEBUG6_STATUS_FIRST_EOP_FSM(v)   BM_USBPHY_DEBUG6_STATUS_FIRST_EOP_FSM
+#define BF_USBPHY_DEBUG6_STATUS_FIRST_EOP_FSM_V(e)  BF_USBPHY_DEBUG6_STATUS_FIRST_EOP_FSM(BV_USBPHY_DEBUG6_STATUS_FIRST_EOP_FSM__##e)
+#define BFM_USBPHY_DEBUG6_STATUS_FIRST_EOP_FSM_V(v) BM_USBPHY_DEBUG6_STATUS_FIRST_EOP_FSM
+#define BP_USBPHY_DEBUG6_STATUS_EOP_FSM             0
+#define BM_USBPHY_DEBUG6_STATUS_EOP_FSM             0xff
+#define BF_USBPHY_DEBUG6_STATUS_EOP_FSM(v)          (((v) & 0xff) << 0)
+#define BFM_USBPHY_DEBUG6_STATUS_EOP_FSM(v)         BM_USBPHY_DEBUG6_STATUS_EOP_FSM
+#define BF_USBPHY_DEBUG6_STATUS_EOP_FSM_V(e)        BF_USBPHY_DEBUG6_STATUS_EOP_FSM(BV_USBPHY_DEBUG6_STATUS_EOP_FSM__##e)
+#define BFM_USBPHY_DEBUG6_STATUS_EOP_FSM_V(v)       BM_USBPHY_DEBUG6_STATUS_EOP_FSM
+
+#define HW_USBPHY_DEBUG7_STATUS                         HW(USBPHY_DEBUG7_STATUS)
+#define HWA_USBPHY_DEBUG7_STATUS                        (0x8007c000 + 0xd0)
+#define HWT_USBPHY_DEBUG7_STATUS                        HWIO_32_RW
+#define HWN_USBPHY_DEBUG7_STATUS                        USBPHY_DEBUG7_STATUS
+#define HWI_USBPHY_DEBUG7_STATUS                        
+#define BP_USBPHY_DEBUG7_STATUS_FIRST_DATA_FSM          28
+#define BM_USBPHY_DEBUG7_STATUS_FIRST_DATA_FSM          0x30000000
+#define BF_USBPHY_DEBUG7_STATUS_FIRST_DATA_FSM(v)       (((v) & 0x3) << 28)
+#define BFM_USBPHY_DEBUG7_STATUS_FIRST_DATA_FSM(v)      BM_USBPHY_DEBUG7_STATUS_FIRST_DATA_FSM
+#define BF_USBPHY_DEBUG7_STATUS_FIRST_DATA_FSM_V(e)     BF_USBPHY_DEBUG7_STATUS_FIRST_DATA_FSM(BV_USBPHY_DEBUG7_STATUS_FIRST_DATA_FSM__##e)
+#define BFM_USBPHY_DEBUG7_STATUS_FIRST_DATA_FSM_V(v)    BM_USBPHY_DEBUG7_STATUS_FIRST_DATA_FSM
+#define BP_USBPHY_DEBUG7_STATUS_BIT_CNT                 24
+#define BM_USBPHY_DEBUG7_STATUS_BIT_CNT                 0xf000000
+#define BF_USBPHY_DEBUG7_STATUS_BIT_CNT(v)              (((v) & 0xf) << 24)
+#define BFM_USBPHY_DEBUG7_STATUS_BIT_CNT(v)             BM_USBPHY_DEBUG7_STATUS_BIT_CNT
+#define BF_USBPHY_DEBUG7_STATUS_BIT_CNT_V(e)            BF_USBPHY_DEBUG7_STATUS_BIT_CNT(BV_USBPHY_DEBUG7_STATUS_BIT_CNT__##e)
+#define BFM_USBPHY_DEBUG7_STATUS_BIT_CNT_V(v)           BM_USBPHY_DEBUG7_STATUS_BIT_CNT
+#define BP_USBPHY_DEBUG7_STATUS_UNSTUFF_CNT             20
+#define BM_USBPHY_DEBUG7_STATUS_UNSTUFF_CNT             0x700000
+#define BF_USBPHY_DEBUG7_STATUS_UNSTUFF_CNT(v)          (((v) & 0x7) << 20)
+#define BFM_USBPHY_DEBUG7_STATUS_UNSTUFF_CNT(v)         BM_USBPHY_DEBUG7_STATUS_UNSTUFF_CNT
+#define BF_USBPHY_DEBUG7_STATUS_UNSTUFF_CNT_V(e)        BF_USBPHY_DEBUG7_STATUS_UNSTUFF_CNT(BV_USBPHY_DEBUG7_STATUS_UNSTUFF_CNT__##e)
+#define BFM_USBPHY_DEBUG7_STATUS_UNSTUFF_CNT_V(v)       BM_USBPHY_DEBUG7_STATUS_UNSTUFF_CNT
+#define BP_USBPHY_DEBUG7_STATUS_LD_FSM                  16
+#define BM_USBPHY_DEBUG7_STATUS_LD_FSM                  0x30000
+#define BF_USBPHY_DEBUG7_STATUS_LD_FSM(v)               (((v) & 0x3) << 16)
+#define BFM_USBPHY_DEBUG7_STATUS_LD_FSM(v)              BM_USBPHY_DEBUG7_STATUS_LD_FSM
+#define BF_USBPHY_DEBUG7_STATUS_LD_FSM_V(e)             BF_USBPHY_DEBUG7_STATUS_LD_FSM(BV_USBPHY_DEBUG7_STATUS_LD_FSM__##e)
+#define BFM_USBPHY_DEBUG7_STATUS_LD_FSM_V(v)            BM_USBPHY_DEBUG7_STATUS_LD_FSM
+#define BP_USBPHY_DEBUG7_STATUS_FIFO_FSM                8
+#define BM_USBPHY_DEBUG7_STATUS_FIFO_FSM                0x3f00
+#define BF_USBPHY_DEBUG7_STATUS_FIFO_FSM(v)             (((v) & 0x3f) << 8)
+#define BFM_USBPHY_DEBUG7_STATUS_FIFO_FSM(v)            BM_USBPHY_DEBUG7_STATUS_FIFO_FSM
+#define BF_USBPHY_DEBUG7_STATUS_FIFO_FSM_V(e)           BF_USBPHY_DEBUG7_STATUS_FIFO_FSM(BV_USBPHY_DEBUG7_STATUS_FIFO_FSM__##e)
+#define BFM_USBPHY_DEBUG7_STATUS_FIFO_FSM_V(v)          BM_USBPHY_DEBUG7_STATUS_FIFO_FSM
+#define BP_USBPHY_DEBUG7_STATUS_MAIN_FSM                4
+#define BM_USBPHY_DEBUG7_STATUS_MAIN_FSM                0xf0
+#define BF_USBPHY_DEBUG7_STATUS_MAIN_FSM(v)             (((v) & 0xf) << 4)
+#define BFM_USBPHY_DEBUG7_STATUS_MAIN_FSM(v)            BM_USBPHY_DEBUG7_STATUS_MAIN_FSM
+#define BF_USBPHY_DEBUG7_STATUS_MAIN_FSM_V(e)           BF_USBPHY_DEBUG7_STATUS_MAIN_FSM(BV_USBPHY_DEBUG7_STATUS_MAIN_FSM__##e)
+#define BFM_USBPHY_DEBUG7_STATUS_MAIN_FSM_V(v)          BM_USBPHY_DEBUG7_STATUS_MAIN_FSM
+#define BP_USBPHY_DEBUG7_STATUS_EOP_FSM                 0
+#define BM_USBPHY_DEBUG7_STATUS_EOP_FSM                 0xf
+#define BF_USBPHY_DEBUG7_STATUS_EOP_FSM(v)              (((v) & 0xf) << 0)
+#define BFM_USBPHY_DEBUG7_STATUS_EOP_FSM(v)             BM_USBPHY_DEBUG7_STATUS_EOP_FSM
+#define BF_USBPHY_DEBUG7_STATUS_EOP_FSM_V(e)            BF_USBPHY_DEBUG7_STATUS_EOP_FSM(BV_USBPHY_DEBUG7_STATUS_EOP_FSM__##e)
+#define BFM_USBPHY_DEBUG7_STATUS_EOP_FSM_V(v)           BM_USBPHY_DEBUG7_STATUS_EOP_FSM
+
+#define HW_USBPHY_DEBUG8_STATUS                         HW(USBPHY_DEBUG8_STATUS)
+#define HWA_USBPHY_DEBUG8_STATUS                        (0x8007c000 + 0xe0)
+#define HWT_USBPHY_DEBUG8_STATUS                        HWIO_32_RW
+#define HWN_USBPHY_DEBUG8_STATUS                        USBPHY_DEBUG8_STATUS
+#define HWI_USBPHY_DEBUG8_STATUS                        
+#define BP_USBPHY_DEBUG8_STATUS_RX_SIE_FSM              28
+#define BM_USBPHY_DEBUG8_STATUS_RX_SIE_FSM              0xf0000000
+#define BF_USBPHY_DEBUG8_STATUS_RX_SIE_FSM(v)           (((v) & 0xf) << 28)
+#define BFM_USBPHY_DEBUG8_STATUS_RX_SIE_FSM(v)          BM_USBPHY_DEBUG8_STATUS_RX_SIE_FSM
+#define BF_USBPHY_DEBUG8_STATUS_RX_SIE_FSM_V(e)         BF_USBPHY_DEBUG8_STATUS_RX_SIE_FSM(BV_USBPHY_DEBUG8_STATUS_RX_SIE_FSM__##e)
+#define BFM_USBPHY_DEBUG8_STATUS_RX_SIE_FSM_V(v)        BM_USBPHY_DEBUG8_STATUS_RX_SIE_FSM
+#define BP_USBPHY_DEBUG8_STATUS_TX_SIE_FSM              24
+#define BM_USBPHY_DEBUG8_STATUS_TX_SIE_FSM              0xf000000
+#define BF_USBPHY_DEBUG8_STATUS_TX_SIE_FSM(v)           (((v) & 0xf) << 24)
+#define BFM_USBPHY_DEBUG8_STATUS_TX_SIE_FSM(v)          BM_USBPHY_DEBUG8_STATUS_TX_SIE_FSM
+#define BF_USBPHY_DEBUG8_STATUS_TX_SIE_FSM_V(e)         BF_USBPHY_DEBUG8_STATUS_TX_SIE_FSM(BV_USBPHY_DEBUG8_STATUS_TX_SIE_FSM__##e)
+#define BFM_USBPHY_DEBUG8_STATUS_TX_SIE_FSM_V(v)        BM_USBPHY_DEBUG8_STATUS_TX_SIE_FSM
+#define BP_USBPHY_DEBUG8_STATUS_SHIFT_FSM               8
+#define BM_USBPHY_DEBUG8_STATUS_SHIFT_FSM               0x300
+#define BF_USBPHY_DEBUG8_STATUS_SHIFT_FSM(v)            (((v) & 0x3) << 8)
+#define BFM_USBPHY_DEBUG8_STATUS_SHIFT_FSM(v)           BM_USBPHY_DEBUG8_STATUS_SHIFT_FSM
+#define BF_USBPHY_DEBUG8_STATUS_SHIFT_FSM_V(e)          BF_USBPHY_DEBUG8_STATUS_SHIFT_FSM(BV_USBPHY_DEBUG8_STATUS_SHIFT_FSM__##e)
+#define BFM_USBPHY_DEBUG8_STATUS_SHIFT_FSM_V(v)         BM_USBPHY_DEBUG8_STATUS_SHIFT_FSM
+#define BP_USBPHY_DEBUG8_STATUS_FS_TX_MAIN_FSM          0
+#define BM_USBPHY_DEBUG8_STATUS_FS_TX_MAIN_FSM          0x7f
+#define BF_USBPHY_DEBUG8_STATUS_FS_TX_MAIN_FSM(v)       (((v) & 0x7f) << 0)
+#define BFM_USBPHY_DEBUG8_STATUS_FS_TX_MAIN_FSM(v)      BM_USBPHY_DEBUG8_STATUS_FS_TX_MAIN_FSM
+#define BF_USBPHY_DEBUG8_STATUS_FS_TX_MAIN_FSM_V(e)     BF_USBPHY_DEBUG8_STATUS_FS_TX_MAIN_FSM(BV_USBPHY_DEBUG8_STATUS_FS_TX_MAIN_FSM__##e)
+#define BFM_USBPHY_DEBUG8_STATUS_FS_TX_MAIN_FSM_V(v)    BM_USBPHY_DEBUG8_STATUS_FS_TX_MAIN_FSM
+
+#endif /* __HEADERGEN_STMP3600_USBPHY_H__*/
diff --git a/firmware/target/arm/imx233/regs/stmp3700/apbh.h b/firmware/target/arm/imx233/regs/stmp3700/apbh.h
new file mode 100644
index 0000000000..0e13b92f6a
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3700/apbh.h
@@ -0,0 +1,444 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * stmp3700 version: 2.4.0
+ * stmp3700 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_STMP3700_APBH_H__
+#define __HEADERGEN_STMP3700_APBH_H__
+
+#define HW_APBH_CTRL0                           HW(APBH_CTRL0)
+#define HWA_APBH_CTRL0                          (0x80004000 + 0x0)
+#define HWT_APBH_CTRL0                          HWIO_32_RW
+#define HWN_APBH_CTRL0                          APBH_CTRL0
+#define HWI_APBH_CTRL0                          
+#define HW_APBH_CTRL0_SET                       HW(APBH_CTRL0_SET)
+#define HWA_APBH_CTRL0_SET                      (HWA_APBH_CTRL0 + 0x4)
+#define HWT_APBH_CTRL0_SET                      HWIO_32_WO
+#define HWN_APBH_CTRL0_SET                      APBH_CTRL0
+#define HWI_APBH_CTRL0_SET                      
+#define HW_APBH_CTRL0_CLR                       HW(APBH_CTRL0_CLR)
+#define HWA_APBH_CTRL0_CLR                      (HWA_APBH_CTRL0 + 0x8)
+#define HWT_APBH_CTRL0_CLR                      HWIO_32_WO
+#define HWN_APBH_CTRL0_CLR                      APBH_CTRL0
+#define HWI_APBH_CTRL0_CLR                      
+#define HW_APBH_CTRL0_TOG                       HW(APBH_CTRL0_TOG)
+#define HWA_APBH_CTRL0_TOG                      (HWA_APBH_CTRL0 + 0xc)
+#define HWT_APBH_CTRL0_TOG                      HWIO_32_WO
+#define HWN_APBH_CTRL0_TOG                      APBH_CTRL0
+#define HWI_APBH_CTRL0_TOG                      
+#define BP_APBH_CTRL0_SFTRST                    31
+#define BM_APBH_CTRL0_SFTRST                    0x80000000
+#define BF_APBH_CTRL0_SFTRST(v)                 (((v) & 0x1) << 31)
+#define BFM_APBH_CTRL0_SFTRST(v)                BM_APBH_CTRL0_SFTRST
+#define BF_APBH_CTRL0_SFTRST_V(e)               BF_APBH_CTRL0_SFTRST(BV_APBH_CTRL0_SFTRST__##e)
+#define BFM_APBH_CTRL0_SFTRST_V(v)              BM_APBH_CTRL0_SFTRST
+#define BP_APBH_CTRL0_CLKGATE                   30
+#define BM_APBH_CTRL0_CLKGATE                   0x40000000
+#define BF_APBH_CTRL0_CLKGATE(v)                (((v) & 0x1) << 30)
+#define BFM_APBH_CTRL0_CLKGATE(v)               BM_APBH_CTRL0_CLKGATE
+#define BF_APBH_CTRL0_CLKGATE_V(e)              BF_APBH_CTRL0_CLKGATE(BV_APBH_CTRL0_CLKGATE__##e)
+#define BFM_APBH_CTRL0_CLKGATE_V(v)             BM_APBH_CTRL0_CLKGATE
+#define BP_APBH_CTRL0_RESET_CHANNEL             16
+#define BM_APBH_CTRL0_RESET_CHANNEL             0xff0000
+#define BV_APBH_CTRL0_RESET_CHANNEL__SSP1       0x1
+#define BV_APBH_CTRL0_RESET_CHANNEL__SSP2       0x2
+#define BV_APBH_CTRL0_RESET_CHANNEL__LCDIF      0x4
+#define BV_APBH_CTRL0_RESET_CHANNEL__ATA        0x10
+#define BV_APBH_CTRL0_RESET_CHANNEL__NAND0      0x10
+#define BV_APBH_CTRL0_RESET_CHANNEL__NAND1      0x20
+#define BV_APBH_CTRL0_RESET_CHANNEL__NAND2      0x40
+#define BV_APBH_CTRL0_RESET_CHANNEL__NAND3      0x80
+#define BF_APBH_CTRL0_RESET_CHANNEL(v)          (((v) & 0xff) << 16)
+#define BFM_APBH_CTRL0_RESET_CHANNEL(v)         BM_APBH_CTRL0_RESET_CHANNEL
+#define BF_APBH_CTRL0_RESET_CHANNEL_V(e)        BF_APBH_CTRL0_RESET_CHANNEL(BV_APBH_CTRL0_RESET_CHANNEL__##e)
+#define BFM_APBH_CTRL0_RESET_CHANNEL_V(v)       BM_APBH_CTRL0_RESET_CHANNEL
+#define BP_APBH_CTRL0_CLKGATE_CHANNEL           8
+#define BM_APBH_CTRL0_CLKGATE_CHANNEL           0xff00
+#define BV_APBH_CTRL0_CLKGATE_CHANNEL__SSP1     0x1
+#define BV_APBH_CTRL0_CLKGATE_CHANNEL__SSP2     0x2
+#define BV_APBH_CTRL0_CLKGATE_CHANNEL__LCDIF    0x4
+#define BV_APBH_CTRL0_CLKGATE_CHANNEL__ATA      0x10
+#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND0    0x10
+#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND1    0x20
+#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND2    0x40
+#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND3    0x80
+#define BF_APBH_CTRL0_CLKGATE_CHANNEL(v)        (((v) & 0xff) << 8)
+#define BFM_APBH_CTRL0_CLKGATE_CHANNEL(v)       BM_APBH_CTRL0_CLKGATE_CHANNEL
+#define BF_APBH_CTRL0_CLKGATE_CHANNEL_V(e)      BF_APBH_CTRL0_CLKGATE_CHANNEL(BV_APBH_CTRL0_CLKGATE_CHANNEL__##e)
+#define BFM_APBH_CTRL0_CLKGATE_CHANNEL_V(v)     BM_APBH_CTRL0_CLKGATE_CHANNEL
+#define BP_APBH_CTRL0_FREEZE_CHANNEL            0
+#define BM_APBH_CTRL0_FREEZE_CHANNEL            0xff
+#define BV_APBH_CTRL0_FREEZE_CHANNEL__SSP1      0x1
+#define BV_APBH_CTRL0_FREEZE_CHANNEL__SSP2      0x2
+#define BV_APBH_CTRL0_FREEZE_CHANNEL__LCDIF     0x4
+#define BV_APBH_CTRL0_FREEZE_CHANNEL__ATA       0x10
+#define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND0     0x10
+#define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND1     0x20
+#define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND2     0x30
+#define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND3     0x40
+#define BF_APBH_CTRL0_FREEZE_CHANNEL(v)         (((v) & 0xff) << 0)
+#define BFM_APBH_CTRL0_FREEZE_CHANNEL(v)        BM_APBH_CTRL0_FREEZE_CHANNEL
+#define BF_APBH_CTRL0_FREEZE_CHANNEL_V(e)       BF_APBH_CTRL0_FREEZE_CHANNEL(BV_APBH_CTRL0_FREEZE_CHANNEL__##e)
+#define BFM_APBH_CTRL0_FREEZE_CHANNEL_V(v)      BM_APBH_CTRL0_FREEZE_CHANNEL
+
+#define HW_APBH_CTRL1                           HW(APBH_CTRL1)
+#define HWA_APBH_CTRL1                          (0x80004000 + 0x10)
+#define HWT_APBH_CTRL1                          HWIO_32_RW
+#define HWN_APBH_CTRL1                          APBH_CTRL1
+#define HWI_APBH_CTRL1                          
+#define HW_APBH_CTRL1_SET                       HW(APBH_CTRL1_SET)
+#define HWA_APBH_CTRL1_SET                      (HWA_APBH_CTRL1 + 0x4)
+#define HWT_APBH_CTRL1_SET                      HWIO_32_WO
+#define HWN_APBH_CTRL1_SET                      APBH_CTRL1
+#define HWI_APBH_CTRL1_SET                      
+#define HW_APBH_CTRL1_CLR                       HW(APBH_CTRL1_CLR)
+#define HWA_APBH_CTRL1_CLR                      (HWA_APBH_CTRL1 + 0x8)
+#define HWT_APBH_CTRL1_CLR                      HWIO_32_WO
+#define HWN_APBH_CTRL1_CLR                      APBH_CTRL1
+#define HWI_APBH_CTRL1_CLR                      
+#define HW_APBH_CTRL1_TOG                       HW(APBH_CTRL1_TOG)
+#define HWA_APBH_CTRL1_TOG                      (HWA_APBH_CTRL1 + 0xc)
+#define HWT_APBH_CTRL1_TOG                      HWIO_32_WO
+#define HWN_APBH_CTRL1_TOG                      APBH_CTRL1
+#define HWI_APBH_CTRL1_TOG                      
+#define BP_APBH_CTRL1_CH_AHB_ERROR_IRQ          16
+#define BM_APBH_CTRL1_CH_AHB_ERROR_IRQ          0xff0000
+#define BF_APBH_CTRL1_CH_AHB_ERROR_IRQ(v)       (((v) & 0xff) << 16)
+#define BFM_APBH_CTRL1_CH_AHB_ERROR_IRQ(v)      BM_APBH_CTRL1_CH_AHB_ERROR_IRQ
+#define BF_APBH_CTRL1_CH_AHB_ERROR_IRQ_V(e)     BF_APBH_CTRL1_CH_AHB_ERROR_IRQ(BV_APBH_CTRL1_CH_AHB_ERROR_IRQ__##e)
+#define BFM_APBH_CTRL1_CH_AHB_ERROR_IRQ_V(v)    BM_APBH_CTRL1_CH_AHB_ERROR_IRQ
+#define BP_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN        8
+#define BM_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN        0xff00
+#define BF_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN(v)     (((v) & 0xff) << 8)
+#define BFM_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN(v)    BM_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN
+#define BF_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_V(e)   BF_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN(BV_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN__##e)
+#define BFM_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_V(v)  BM_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN
+#define BP_APBH_CTRL1_CH_CMDCMPLT_IRQ           0
+#define BM_APBH_CTRL1_CH_CMDCMPLT_IRQ           0xff
+#define BF_APBH_CTRL1_CH_CMDCMPLT_IRQ(v)        (((v) & 0xff) << 0)
+#define BFM_APBH_CTRL1_CH_CMDCMPLT_IRQ(v)       BM_APBH_CTRL1_CH_CMDCMPLT_IRQ
+#define BF_APBH_CTRL1_CH_CMDCMPLT_IRQ_V(e)      BF_APBH_CTRL1_CH_CMDCMPLT_IRQ(BV_APBH_CTRL1_CH_CMDCMPLT_IRQ__##e)
+#define BFM_APBH_CTRL1_CH_CMDCMPLT_IRQ_V(v)     BM_APBH_CTRL1_CH_CMDCMPLT_IRQ
+
+#define HW_APBH_DEVSEL              HW(APBH_DEVSEL)
+#define HWA_APBH_DEVSEL             (0x80004000 + 0x20)
+#define HWT_APBH_DEVSEL             HWIO_32_RW
+#define HWN_APBH_DEVSEL             APBH_DEVSEL
+#define HWI_APBH_DEVSEL             
+#define BP_APBH_DEVSEL_CH7          28
+#define BM_APBH_DEVSEL_CH7          0xf0000000
+#define BF_APBH_DEVSEL_CH7(v)       (((v) & 0xf) << 28)
+#define BFM_APBH_DEVSEL_CH7(v)      BM_APBH_DEVSEL_CH7
+#define BF_APBH_DEVSEL_CH7_V(e)     BF_APBH_DEVSEL_CH7(BV_APBH_DEVSEL_CH7__##e)
+#define BFM_APBH_DEVSEL_CH7_V(v)    BM_APBH_DEVSEL_CH7
+#define BP_APBH_DEVSEL_CH6          24
+#define BM_APBH_DEVSEL_CH6          0xf000000
+#define BF_APBH_DEVSEL_CH6(v)       (((v) & 0xf) << 24)
+#define BFM_APBH_DEVSEL_CH6(v)      BM_APBH_DEVSEL_CH6
+#define BF_APBH_DEVSEL_CH6_V(e)     BF_APBH_DEVSEL_CH6(BV_APBH_DEVSEL_CH6__##e)
+#define BFM_APBH_DEVSEL_CH6_V(v)    BM_APBH_DEVSEL_CH6
+#define BP_APBH_DEVSEL_CH5          20
+#define BM_APBH_DEVSEL_CH5          0xf00000
+#define BF_APBH_DEVSEL_CH5(v)       (((v) & 0xf) << 20)
+#define BFM_APBH_DEVSEL_CH5(v)      BM_APBH_DEVSEL_CH5
+#define BF_APBH_DEVSEL_CH5_V(e)     BF_APBH_DEVSEL_CH5(BV_APBH_DEVSEL_CH5__##e)
+#define BFM_APBH_DEVSEL_CH5_V(v)    BM_APBH_DEVSEL_CH5
+#define BP_APBH_DEVSEL_CH4          16
+#define BM_APBH_DEVSEL_CH4          0xf0000
+#define BF_APBH_DEVSEL_CH4(v)       (((v) & 0xf) << 16)
+#define BFM_APBH_DEVSEL_CH4(v)      BM_APBH_DEVSEL_CH4
+#define BF_APBH_DEVSEL_CH4_V(e)     BF_APBH_DEVSEL_CH4(BV_APBH_DEVSEL_CH4__##e)
+#define BFM_APBH_DEVSEL_CH4_V(v)    BM_APBH_DEVSEL_CH4
+#define BP_APBH_DEVSEL_CH3          12
+#define BM_APBH_DEVSEL_CH3          0xf000
+#define BF_APBH_DEVSEL_CH3(v)       (((v) & 0xf) << 12)
+#define BFM_APBH_DEVSEL_CH3(v)      BM_APBH_DEVSEL_CH3
+#define BF_APBH_DEVSEL_CH3_V(e)     BF_APBH_DEVSEL_CH3(BV_APBH_DEVSEL_CH3__##e)
+#define BFM_APBH_DEVSEL_CH3_V(v)    BM_APBH_DEVSEL_CH3
+#define BP_APBH_DEVSEL_CH2          8
+#define BM_APBH_DEVSEL_CH2          0xf00
+#define BF_APBH_DEVSEL_CH2(v)       (((v) & 0xf) << 8)
+#define BFM_APBH_DEVSEL_CH2(v)      BM_APBH_DEVSEL_CH2
+#define BF_APBH_DEVSEL_CH2_V(e)     BF_APBH_DEVSEL_CH2(BV_APBH_DEVSEL_CH2__##e)
+#define BFM_APBH_DEVSEL_CH2_V(v)    BM_APBH_DEVSEL_CH2
+#define BP_APBH_DEVSEL_CH1          4
+#define BM_APBH_DEVSEL_CH1          0xf0
+#define BF_APBH_DEVSEL_CH1(v)       (((v) & 0xf) << 4)
+#define BFM_APBH_DEVSEL_CH1(v)      BM_APBH_DEVSEL_CH1
+#define BF_APBH_DEVSEL_CH1_V(e)     BF_APBH_DEVSEL_CH1(BV_APBH_DEVSEL_CH1__##e)
+#define BFM_APBH_DEVSEL_CH1_V(v)    BM_APBH_DEVSEL_CH1
+#define BP_APBH_DEVSEL_CH0          0
+#define BM_APBH_DEVSEL_CH0          0xf
+#define BF_APBH_DEVSEL_CH0(v)       (((v) & 0xf) << 0)
+#define BFM_APBH_DEVSEL_CH0(v)      BM_APBH_DEVSEL_CH0
+#define BF_APBH_DEVSEL_CH0_V(e)     BF_APBH_DEVSEL_CH0(BV_APBH_DEVSEL_CH0__##e)
+#define BFM_APBH_DEVSEL_CH0_V(v)    BM_APBH_DEVSEL_CH0
+
+#define HW_APBH_CHn_CURCMDAR(_n1)           HW(APBH_CHn_CURCMDAR(_n1))
+#define HWA_APBH_CHn_CURCMDAR(_n1)          (0x80004000 + 0x40 + (_n1) * 0x70)
+#define HWT_APBH_CHn_CURCMDAR(_n1)          HWIO_32_RW
+#define HWN_APBH_CHn_CURCMDAR(_n1)          APBH_CHn_CURCMDAR
+#define HWI_APBH_CHn_CURCMDAR(_n1)          (_n1)
+#define BP_APBH_CHn_CURCMDAR_CMD_ADDR       0
+#define BM_APBH_CHn_CURCMDAR_CMD_ADDR       0xffffffff
+#define BF_APBH_CHn_CURCMDAR_CMD_ADDR(v)    (((v) & 0xffffffff) << 0)
+#define BFM_APBH_CHn_CURCMDAR_CMD_ADDR(v)   BM_APBH_CHn_CURCMDAR_CMD_ADDR
+#define BF_APBH_CHn_CURCMDAR_CMD_ADDR_V(e)  BF_APBH_CHn_CURCMDAR_CMD_ADDR(BV_APBH_CHn_CURCMDAR_CMD_ADDR__##e)
+#define BFM_APBH_CHn_CURCMDAR_CMD_ADDR_V(v) BM_APBH_CHn_CURCMDAR_CMD_ADDR
+
+#define HW_APBH_CHn_NXTCMDAR(_n1)           HW(APBH_CHn_NXTCMDAR(_n1))
+#define HWA_APBH_CHn_NXTCMDAR(_n1)          (0x80004000 + 0x50 + (_n1) * 0x70)
+#define HWT_APBH_CHn_NXTCMDAR(_n1)          HWIO_32_RW
+#define HWN_APBH_CHn_NXTCMDAR(_n1)          APBH_CHn_NXTCMDAR
+#define HWI_APBH_CHn_NXTCMDAR(_n1)          (_n1)
+#define BP_APBH_CHn_NXTCMDAR_CMD_ADDR       0
+#define BM_APBH_CHn_NXTCMDAR_CMD_ADDR       0xffffffff
+#define BF_APBH_CHn_NXTCMDAR_CMD_ADDR(v)    (((v) & 0xffffffff) << 0)
+#define BFM_APBH_CHn_NXTCMDAR_CMD_ADDR(v)   BM_APBH_CHn_NXTCMDAR_CMD_ADDR
+#define BF_APBH_CHn_NXTCMDAR_CMD_ADDR_V(e)  BF_APBH_CHn_NXTCMDAR_CMD_ADDR(BV_APBH_CHn_NXTCMDAR_CMD_ADDR__##e)
+#define BFM_APBH_CHn_NXTCMDAR_CMD_ADDR_V(v) BM_APBH_CHn_NXTCMDAR_CMD_ADDR
+
+#define HW_APBH_CHn_CMD(_n1)                    HW(APBH_CHn_CMD(_n1))
+#define HWA_APBH_CHn_CMD(_n1)                   (0x80004000 + 0x60 + (_n1) * 0x70)
+#define HWT_APBH_CHn_CMD(_n1)                   HWIO_32_RW
+#define HWN_APBH_CHn_CMD(_n1)                   APBH_CHn_CMD
+#define HWI_APBH_CHn_CMD(_n1)                   (_n1)
+#define BP_APBH_CHn_CMD_XFER_COUNT              16
+#define BM_APBH_CHn_CMD_XFER_COUNT              0xffff0000
+#define BF_APBH_CHn_CMD_XFER_COUNT(v)           (((v) & 0xffff) << 16)
+#define BFM_APBH_CHn_CMD_XFER_COUNT(v)          BM_APBH_CHn_CMD_XFER_COUNT
+#define BF_APBH_CHn_CMD_XFER_COUNT_V(e)         BF_APBH_CHn_CMD_XFER_COUNT(BV_APBH_CHn_CMD_XFER_COUNT__##e)
+#define BFM_APBH_CHn_CMD_XFER_COUNT_V(v)        BM_APBH_CHn_CMD_XFER_COUNT
+#define BP_APBH_CHn_CMD_CMDWORDS                12
+#define BM_APBH_CHn_CMD_CMDWORDS                0xf000
+#define BF_APBH_CHn_CMD_CMDWORDS(v)             (((v) & 0xf) << 12)
+#define BFM_APBH_CHn_CMD_CMDWORDS(v)            BM_APBH_CHn_CMD_CMDWORDS
+#define BF_APBH_CHn_CMD_CMDWORDS_V(e)           BF_APBH_CHn_CMD_CMDWORDS(BV_APBH_CHn_CMD_CMDWORDS__##e)
+#define BFM_APBH_CHn_CMD_CMDWORDS_V(v)          BM_APBH_CHn_CMD_CMDWORDS
+#define BP_APBH_CHn_CMD_HALTONTERMINATE         8
+#define BM_APBH_CHn_CMD_HALTONTERMINATE         0x100
+#define BF_APBH_CHn_CMD_HALTONTERMINATE(v)      (((v) & 0x1) << 8)
+#define BFM_APBH_CHn_CMD_HALTONTERMINATE(v)     BM_APBH_CHn_CMD_HALTONTERMINATE
+#define BF_APBH_CHn_CMD_HALTONTERMINATE_V(e)    BF_APBH_CHn_CMD_HALTONTERMINATE(BV_APBH_CHn_CMD_HALTONTERMINATE__##e)
+#define BFM_APBH_CHn_CMD_HALTONTERMINATE_V(v)   BM_APBH_CHn_CMD_HALTONTERMINATE
+#define BP_APBH_CHn_CMD_WAIT4ENDCMD             7
+#define BM_APBH_CHn_CMD_WAIT4ENDCMD             0x80
+#define BF_APBH_CHn_CMD_WAIT4ENDCMD(v)          (((v) & 0x1) << 7)
+#define BFM_APBH_CHn_CMD_WAIT4ENDCMD(v)         BM_APBH_CHn_CMD_WAIT4ENDCMD
+#define BF_APBH_CHn_CMD_WAIT4ENDCMD_V(e)        BF_APBH_CHn_CMD_WAIT4ENDCMD(BV_APBH_CHn_CMD_WAIT4ENDCMD__##e)
+#define BFM_APBH_CHn_CMD_WAIT4ENDCMD_V(v)       BM_APBH_CHn_CMD_WAIT4ENDCMD
+#define BP_APBH_CHn_CMD_SEMAPHORE               6
+#define BM_APBH_CHn_CMD_SEMAPHORE               0x40
+#define BF_APBH_CHn_CMD_SEMAPHORE(v)            (((v) & 0x1) << 6)
+#define BFM_APBH_CHn_CMD_SEMAPHORE(v)           BM_APBH_CHn_CMD_SEMAPHORE
+#define BF_APBH_CHn_CMD_SEMAPHORE_V(e)          BF_APBH_CHn_CMD_SEMAPHORE(BV_APBH_CHn_CMD_SEMAPHORE__##e)
+#define BFM_APBH_CHn_CMD_SEMAPHORE_V(v)         BM_APBH_CHn_CMD_SEMAPHORE
+#define BP_APBH_CHn_CMD_NANDWAIT4READY          5
+#define BM_APBH_CHn_CMD_NANDWAIT4READY          0x20
+#define BF_APBH_CHn_CMD_NANDWAIT4READY(v)       (((v) & 0x1) << 5)
+#define BFM_APBH_CHn_CMD_NANDWAIT4READY(v)      BM_APBH_CHn_CMD_NANDWAIT4READY
+#define BF_APBH_CHn_CMD_NANDWAIT4READY_V(e)     BF_APBH_CHn_CMD_NANDWAIT4READY(BV_APBH_CHn_CMD_NANDWAIT4READY__##e)
+#define BFM_APBH_CHn_CMD_NANDWAIT4READY_V(v)    BM_APBH_CHn_CMD_NANDWAIT4READY
+#define BP_APBH_CHn_CMD_NANDLOCK                4
+#define BM_APBH_CHn_CMD_NANDLOCK                0x10
+#define BF_APBH_CHn_CMD_NANDLOCK(v)             (((v) & 0x1) << 4)
+#define BFM_APBH_CHn_CMD_NANDLOCK(v)            BM_APBH_CHn_CMD_NANDLOCK
+#define BF_APBH_CHn_CMD_NANDLOCK_V(e)           BF_APBH_CHn_CMD_NANDLOCK(BV_APBH_CHn_CMD_NANDLOCK__##e)
+#define BFM_APBH_CHn_CMD_NANDLOCK_V(v)          BM_APBH_CHn_CMD_NANDLOCK
+#define BP_APBH_CHn_CMD_IRQONCMPLT              3
+#define BM_APBH_CHn_CMD_IRQONCMPLT              0x8
+#define BF_APBH_CHn_CMD_IRQONCMPLT(v)           (((v) & 0x1) << 3)
+#define BFM_APBH_CHn_CMD_IRQONCMPLT(v)          BM_APBH_CHn_CMD_IRQONCMPLT
+#define BF_APBH_CHn_CMD_IRQONCMPLT_V(e)         BF_APBH_CHn_CMD_IRQONCMPLT(BV_APBH_CHn_CMD_IRQONCMPLT__##e)
+#define BFM_APBH_CHn_CMD_IRQONCMPLT_V(v)        BM_APBH_CHn_CMD_IRQONCMPLT
+#define BP_APBH_CHn_CMD_CHAIN                   2
+#define BM_APBH_CHn_CMD_CHAIN                   0x4
+#define BF_APBH_CHn_CMD_CHAIN(v)                (((v) & 0x1) << 2)
+#define BFM_APBH_CHn_CMD_CHAIN(v)               BM_APBH_CHn_CMD_CHAIN
+#define BF_APBH_CHn_CMD_CHAIN_V(e)              BF_APBH_CHn_CMD_CHAIN(BV_APBH_CHn_CMD_CHAIN__##e)
+#define BFM_APBH_CHn_CMD_CHAIN_V(v)             BM_APBH_CHn_CMD_CHAIN
+#define BP_APBH_CHn_CMD_COMMAND                 0
+#define BM_APBH_CHn_CMD_COMMAND                 0x3
+#define BV_APBH_CHn_CMD_COMMAND__NO_DMA_XFER    0x0
+#define BV_APBH_CHn_CMD_COMMAND__DMA_WRITE      0x1
+#define BV_APBH_CHn_CMD_COMMAND__DMA_READ       0x2
+#define BV_APBH_CHn_CMD_COMMAND__DMA_SENSE      0x3
+#define BF_APBH_CHn_CMD_COMMAND(v)              (((v) & 0x3) << 0)
+#define BFM_APBH_CHn_CMD_COMMAND(v)             BM_APBH_CHn_CMD_COMMAND
+#define BF_APBH_CHn_CMD_COMMAND_V(e)            BF_APBH_CHn_CMD_COMMAND(BV_APBH_CHn_CMD_COMMAND__##e)
+#define BFM_APBH_CHn_CMD_COMMAND_V(v)           BM_APBH_CHn_CMD_COMMAND
+
+#define HW_APBH_CHn_BAR(_n1)            HW(APBH_CHn_BAR(_n1))
+#define HWA_APBH_CHn_BAR(_n1)           (0x80004000 + 0x70 + (_n1) * 0x70)
+#define HWT_APBH_CHn_BAR(_n1)           HWIO_32_RW
+#define HWN_APBH_CHn_BAR(_n1)           APBH_CHn_BAR
+#define HWI_APBH_CHn_BAR(_n1)           (_n1)
+#define BP_APBH_CHn_BAR_ADDRESS         0
+#define BM_APBH_CHn_BAR_ADDRESS         0xffffffff
+#define BF_APBH_CHn_BAR_ADDRESS(v)      (((v) & 0xffffffff) << 0)
+#define BFM_APBH_CHn_BAR_ADDRESS(v)     BM_APBH_CHn_BAR_ADDRESS
+#define BF_APBH_CHn_BAR_ADDRESS_V(e)    BF_APBH_CHn_BAR_ADDRESS(BV_APBH_CHn_BAR_ADDRESS__##e)
+#define BFM_APBH_CHn_BAR_ADDRESS_V(v)   BM_APBH_CHn_BAR_ADDRESS
+
+#define HW_APBH_CHn_SEMA(_n1)                   HW(APBH_CHn_SEMA(_n1))
+#define HWA_APBH_CHn_SEMA(_n1)                  (0x80004000 + 0x80 + (_n1) * 0x70)
+#define HWT_APBH_CHn_SEMA(_n1)                  HWIO_32_RW
+#define HWN_APBH_CHn_SEMA(_n1)                  APBH_CHn_SEMA
+#define HWI_APBH_CHn_SEMA(_n1)                  (_n1)
+#define BP_APBH_CHn_SEMA_PHORE                  16
+#define BM_APBH_CHn_SEMA_PHORE                  0xff0000
+#define BF_APBH_CHn_SEMA_PHORE(v)               (((v) & 0xff) << 16)
+#define BFM_APBH_CHn_SEMA_PHORE(v)              BM_APBH_CHn_SEMA_PHORE
+#define BF_APBH_CHn_SEMA_PHORE_V(e)             BF_APBH_CHn_SEMA_PHORE(BV_APBH_CHn_SEMA_PHORE__##e)
+#define BFM_APBH_CHn_SEMA_PHORE_V(v)            BM_APBH_CHn_SEMA_PHORE
+#define BP_APBH_CHn_SEMA_INCREMENT_SEMA         0
+#define BM_APBH_CHn_SEMA_INCREMENT_SEMA         0xff
+#define BF_APBH_CHn_SEMA_INCREMENT_SEMA(v)      (((v) & 0xff) << 0)
+#define BFM_APBH_CHn_SEMA_INCREMENT_SEMA(v)     BM_APBH_CHn_SEMA_INCREMENT_SEMA
+#define BF_APBH_CHn_SEMA_INCREMENT_SEMA_V(e)    BF_APBH_CHn_SEMA_INCREMENT_SEMA(BV_APBH_CHn_SEMA_INCREMENT_SEMA__##e)
+#define BFM_APBH_CHn_SEMA_INCREMENT_SEMA_V(v)   BM_APBH_CHn_SEMA_INCREMENT_SEMA
+
+#define HW_APBH_CHn_DEBUG1(_n1)                         HW(APBH_CHn_DEBUG1(_n1))
+#define HWA_APBH_CHn_DEBUG1(_n1)                        (0x80004000 + 0x90 + (_n1) * 0x70)
+#define HWT_APBH_CHn_DEBUG1(_n1)                        HWIO_32_RW
+#define HWN_APBH_CHn_DEBUG1(_n1)                        APBH_CHn_DEBUG1
+#define HWI_APBH_CHn_DEBUG1(_n1)                        (_n1)
+#define BP_APBH_CHn_DEBUG1_REQ                          31
+#define BM_APBH_CHn_DEBUG1_REQ                          0x80000000
+#define BF_APBH_CHn_DEBUG1_REQ(v)                       (((v) & 0x1) << 31)
+#define BFM_APBH_CHn_DEBUG1_REQ(v)                      BM_APBH_CHn_DEBUG1_REQ
+#define BF_APBH_CHn_DEBUG1_REQ_V(e)                     BF_APBH_CHn_DEBUG1_REQ(BV_APBH_CHn_DEBUG1_REQ__##e)
+#define BFM_APBH_CHn_DEBUG1_REQ_V(v)                    BM_APBH_CHn_DEBUG1_REQ
+#define BP_APBH_CHn_DEBUG1_BURST                        30
+#define BM_APBH_CHn_DEBUG1_BURST                        0x40000000
+#define BF_APBH_CHn_DEBUG1_BURST(v)                     (((v) & 0x1) << 30)
+#define BFM_APBH_CHn_DEBUG1_BURST(v)                    BM_APBH_CHn_DEBUG1_BURST
+#define BF_APBH_CHn_DEBUG1_BURST_V(e)                   BF_APBH_CHn_DEBUG1_BURST(BV_APBH_CHn_DEBUG1_BURST__##e)
+#define BFM_APBH_CHn_DEBUG1_BURST_V(v)                  BM_APBH_CHn_DEBUG1_BURST
+#define BP_APBH_CHn_DEBUG1_KICK                         29
+#define BM_APBH_CHn_DEBUG1_KICK                         0x20000000
+#define BF_APBH_CHn_DEBUG1_KICK(v)                      (((v) & 0x1) << 29)
+#define BFM_APBH_CHn_DEBUG1_KICK(v)                     BM_APBH_CHn_DEBUG1_KICK
+#define BF_APBH_CHn_DEBUG1_KICK_V(e)                    BF_APBH_CHn_DEBUG1_KICK(BV_APBH_CHn_DEBUG1_KICK__##e)
+#define BFM_APBH_CHn_DEBUG1_KICK_V(v)                   BM_APBH_CHn_DEBUG1_KICK
+#define BP_APBH_CHn_DEBUG1_END                          28
+#define BM_APBH_CHn_DEBUG1_END                          0x10000000
+#define BF_APBH_CHn_DEBUG1_END(v)                       (((v) & 0x1) << 28)
+#define BFM_APBH_CHn_DEBUG1_END(v)                      BM_APBH_CHn_DEBUG1_END
+#define BF_APBH_CHn_DEBUG1_END_V(e)                     BF_APBH_CHn_DEBUG1_END(BV_APBH_CHn_DEBUG1_END__##e)
+#define BFM_APBH_CHn_DEBUG1_END_V(v)                    BM_APBH_CHn_DEBUG1_END
+#define BP_APBH_CHn_DEBUG1_NEXTCMDADDRVALID             24
+#define BM_APBH_CHn_DEBUG1_NEXTCMDADDRVALID             0x1000000
+#define BF_APBH_CHn_DEBUG1_NEXTCMDADDRVALID(v)          (((v) & 0x1) << 24)
+#define BFM_APBH_CHn_DEBUG1_NEXTCMDADDRVALID(v)         BM_APBH_CHn_DEBUG1_NEXTCMDADDRVALID
+#define BF_APBH_CHn_DEBUG1_NEXTCMDADDRVALID_V(e)        BF_APBH_CHn_DEBUG1_NEXTCMDADDRVALID(BV_APBH_CHn_DEBUG1_NEXTCMDADDRVALID__##e)
+#define BFM_APBH_CHn_DEBUG1_NEXTCMDADDRVALID_V(v)       BM_APBH_CHn_DEBUG1_NEXTCMDADDRVALID
+#define BP_APBH_CHn_DEBUG1_RD_FIFO_EMPTY                23
+#define BM_APBH_CHn_DEBUG1_RD_FIFO_EMPTY                0x800000
+#define BF_APBH_CHn_DEBUG1_RD_FIFO_EMPTY(v)             (((v) & 0x1) << 23)
+#define BFM_APBH_CHn_DEBUG1_RD_FIFO_EMPTY(v)            BM_APBH_CHn_DEBUG1_RD_FIFO_EMPTY
+#define BF_APBH_CHn_DEBUG1_RD_FIFO_EMPTY_V(e)           BF_APBH_CHn_DEBUG1_RD_FIFO_EMPTY(BV_APBH_CHn_DEBUG1_RD_FIFO_EMPTY__##e)
+#define BFM_APBH_CHn_DEBUG1_RD_FIFO_EMPTY_V(v)          BM_APBH_CHn_DEBUG1_RD_FIFO_EMPTY
+#define BP_APBH_CHn_DEBUG1_RD_FIFO_FULL                 22
+#define BM_APBH_CHn_DEBUG1_RD_FIFO_FULL                 0x400000
+#define BF_APBH_CHn_DEBUG1_RD_FIFO_FULL(v)              (((v) & 0x1) << 22)
+#define BFM_APBH_CHn_DEBUG1_RD_FIFO_FULL(v)             BM_APBH_CHn_DEBUG1_RD_FIFO_FULL
+#define BF_APBH_CHn_DEBUG1_RD_FIFO_FULL_V(e)            BF_APBH_CHn_DEBUG1_RD_FIFO_FULL(BV_APBH_CHn_DEBUG1_RD_FIFO_FULL__##e)
+#define BFM_APBH_CHn_DEBUG1_RD_FIFO_FULL_V(v)           BM_APBH_CHn_DEBUG1_RD_FIFO_FULL
+#define BP_APBH_CHn_DEBUG1_WR_FIFO_EMPTY                21
+#define BM_APBH_CHn_DEBUG1_WR_FIFO_EMPTY                0x200000
+#define BF_APBH_CHn_DEBUG1_WR_FIFO_EMPTY(v)             (((v) & 0x1) << 21)
+#define BFM_APBH_CHn_DEBUG1_WR_FIFO_EMPTY(v)            BM_APBH_CHn_DEBUG1_WR_FIFO_EMPTY
+#define BF_APBH_CHn_DEBUG1_WR_FIFO_EMPTY_V(e)           BF_APBH_CHn_DEBUG1_WR_FIFO_EMPTY(BV_APBH_CHn_DEBUG1_WR_FIFO_EMPTY__##e)
+#define BFM_APBH_CHn_DEBUG1_WR_FIFO_EMPTY_V(v)          BM_APBH_CHn_DEBUG1_WR_FIFO_EMPTY
+#define BP_APBH_CHn_DEBUG1_WR_FIFO_FULL                 20
+#define BM_APBH_CHn_DEBUG1_WR_FIFO_FULL                 0x100000
+#define BF_APBH_CHn_DEBUG1_WR_FIFO_FULL(v)              (((v) & 0x1) << 20)
+#define BFM_APBH_CHn_DEBUG1_WR_FIFO_FULL(v)             BM_APBH_CHn_DEBUG1_WR_FIFO_FULL
+#define BF_APBH_CHn_DEBUG1_WR_FIFO_FULL_V(e)            BF_APBH_CHn_DEBUG1_WR_FIFO_FULL(BV_APBH_CHn_DEBUG1_WR_FIFO_FULL__##e)
+#define BFM_APBH_CHn_DEBUG1_WR_FIFO_FULL_V(v)           BM_APBH_CHn_DEBUG1_WR_FIFO_FULL
+#define BP_APBH_CHn_DEBUG1_STATEMACHINE                 0
+#define BM_APBH_CHn_DEBUG1_STATEMACHINE                 0x1f
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__IDLE           0x0
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD1       0x1
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD3       0x2
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD2       0x3
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__XFER_DECODE    0x4
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_WAIT       0x5
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD4       0x6
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__PIO_REQ        0x7
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_FLUSH     0x8
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_WAIT      0x9
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__WRITE          0xc
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_REQ       0xd
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__CHECK_CHAIN    0xe
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__XFER_COMPLETE  0xf
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__WAIT_END       0x15
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__WRITE_WAIT     0x1c
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__CHECK_WAIT     0x1e
+#define BF_APBH_CHn_DEBUG1_STATEMACHINE(v)              (((v) & 0x1f) << 0)
+#define BFM_APBH_CHn_DEBUG1_STATEMACHINE(v)             BM_APBH_CHn_DEBUG1_STATEMACHINE
+#define BF_APBH_CHn_DEBUG1_STATEMACHINE_V(e)            BF_APBH_CHn_DEBUG1_STATEMACHINE(BV_APBH_CHn_DEBUG1_STATEMACHINE__##e)
+#define BFM_APBH_CHn_DEBUG1_STATEMACHINE_V(v)           BM_APBH_CHn_DEBUG1_STATEMACHINE
+
+#define HW_APBH_CHn_DEBUG2(_n1)             HW(APBH_CHn_DEBUG2(_n1))
+#define HWA_APBH_CHn_DEBUG2(_n1)            (0x80004000 + 0xa0 + (_n1) * 0x70)
+#define HWT_APBH_CHn_DEBUG2(_n1)            HWIO_32_RW
+#define HWN_APBH_CHn_DEBUG2(_n1)            APBH_CHn_DEBUG2
+#define HWI_APBH_CHn_DEBUG2(_n1)            (_n1)
+#define BP_APBH_CHn_DEBUG2_APB_BYTES        16
+#define BM_APBH_CHn_DEBUG2_APB_BYTES        0xffff0000
+#define BF_APBH_CHn_DEBUG2_APB_BYTES(v)     (((v) & 0xffff) << 16)
+#define BFM_APBH_CHn_DEBUG2_APB_BYTES(v)    BM_APBH_CHn_DEBUG2_APB_BYTES
+#define BF_APBH_CHn_DEBUG2_APB_BYTES_V(e)   BF_APBH_CHn_DEBUG2_APB_BYTES(BV_APBH_CHn_DEBUG2_APB_BYTES__##e)
+#define BFM_APBH_CHn_DEBUG2_APB_BYTES_V(v)  BM_APBH_CHn_DEBUG2_APB_BYTES
+#define BP_APBH_CHn_DEBUG2_AHB_BYTES        0
+#define BM_APBH_CHn_DEBUG2_AHB_BYTES        0xffff
+#define BF_APBH_CHn_DEBUG2_AHB_BYTES(v)     (((v) & 0xffff) << 0)
+#define BFM_APBH_CHn_DEBUG2_AHB_BYTES(v)    BM_APBH_CHn_DEBUG2_AHB_BYTES
+#define BF_APBH_CHn_DEBUG2_AHB_BYTES_V(e)   BF_APBH_CHn_DEBUG2_AHB_BYTES(BV_APBH_CHn_DEBUG2_AHB_BYTES__##e)
+#define BFM_APBH_CHn_DEBUG2_AHB_BYTES_V(v)  BM_APBH_CHn_DEBUG2_AHB_BYTES
+
+#define HW_APBH_VERSION             HW(APBH_VERSION)
+#define HWA_APBH_VERSION            (0x80004000 + 0x3f0)
+#define HWT_APBH_VERSION            HWIO_32_RW
+#define HWN_APBH_VERSION            APBH_VERSION
+#define HWI_APBH_VERSION            
+#define BP_APBH_VERSION_MAJOR       24
+#define BM_APBH_VERSION_MAJOR       0xff000000
+#define BF_APBH_VERSION_MAJOR(v)    (((v) & 0xff) << 24)
+#define BFM_APBH_VERSION_MAJOR(v)   BM_APBH_VERSION_MAJOR
+#define BF_APBH_VERSION_MAJOR_V(e)  BF_APBH_VERSION_MAJOR(BV_APBH_VERSION_MAJOR__##e)
+#define BFM_APBH_VERSION_MAJOR_V(v) BM_APBH_VERSION_MAJOR
+#define BP_APBH_VERSION_MINOR       16
+#define BM_APBH_VERSION_MINOR       0xff0000
+#define BF_APBH_VERSION_MINOR(v)    (((v) & 0xff) << 16)
+#define BFM_APBH_VERSION_MINOR(v)   BM_APBH_VERSION_MINOR
+#define BF_APBH_VERSION_MINOR_V(e)  BF_APBH_VERSION_MINOR(BV_APBH_VERSION_MINOR__##e)
+#define BFM_APBH_VERSION_MINOR_V(v) BM_APBH_VERSION_MINOR
+#define BP_APBH_VERSION_STEP        0
+#define BM_APBH_VERSION_STEP        0xffff
+#define BF_APBH_VERSION_STEP(v)     (((v) & 0xffff) << 0)
+#define BFM_APBH_VERSION_STEP(v)    BM_APBH_VERSION_STEP
+#define BF_APBH_VERSION_STEP_V(e)   BF_APBH_VERSION_STEP(BV_APBH_VERSION_STEP__##e)
+#define BFM_APBH_VERSION_STEP_V(v)  BM_APBH_VERSION_STEP
+
+#endif /* __HEADERGEN_STMP3700_APBH_H__*/
diff --git a/firmware/target/arm/imx233/regs/stmp3700/apbx.h b/firmware/target/arm/imx233/regs/stmp3700/apbx.h
new file mode 100644
index 0000000000..1232fc10f1
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3700/apbx.h
@@ -0,0 +1,423 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * stmp3700 version: 2.4.0
+ * stmp3700 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_STMP3700_APBX_H__
+#define __HEADERGEN_STMP3700_APBX_H__
+
+#define HW_APBX_CTRL0                           HW(APBX_CTRL0)
+#define HWA_APBX_CTRL0                          (0x80024000 + 0x0)
+#define HWT_APBX_CTRL0                          HWIO_32_RW
+#define HWN_APBX_CTRL0                          APBX_CTRL0
+#define HWI_APBX_CTRL0                          
+#define HW_APBX_CTRL0_SET                       HW(APBX_CTRL0_SET)
+#define HWA_APBX_CTRL0_SET                      (HWA_APBX_CTRL0 + 0x4)
+#define HWT_APBX_CTRL0_SET                      HWIO_32_WO
+#define HWN_APBX_CTRL0_SET                      APBX_CTRL0
+#define HWI_APBX_CTRL0_SET                      
+#define HW_APBX_CTRL0_CLR                       HW(APBX_CTRL0_CLR)
+#define HWA_APBX_CTRL0_CLR                      (HWA_APBX_CTRL0 + 0x8)
+#define HWT_APBX_CTRL0_CLR                      HWIO_32_WO
+#define HWN_APBX_CTRL0_CLR                      APBX_CTRL0
+#define HWI_APBX_CTRL0_CLR                      
+#define HW_APBX_CTRL0_TOG                       HW(APBX_CTRL0_TOG)
+#define HWA_APBX_CTRL0_TOG                      (HWA_APBX_CTRL0 + 0xc)
+#define HWT_APBX_CTRL0_TOG                      HWIO_32_WO
+#define HWN_APBX_CTRL0_TOG                      APBX_CTRL0
+#define HWI_APBX_CTRL0_TOG                      
+#define BP_APBX_CTRL0_SFTRST                    31
+#define BM_APBX_CTRL0_SFTRST                    0x80000000
+#define BF_APBX_CTRL0_SFTRST(v)                 (((v) & 0x1) << 31)
+#define BFM_APBX_CTRL0_SFTRST(v)                BM_APBX_CTRL0_SFTRST
+#define BF_APBX_CTRL0_SFTRST_V(e)               BF_APBX_CTRL0_SFTRST(BV_APBX_CTRL0_SFTRST__##e)
+#define BFM_APBX_CTRL0_SFTRST_V(v)              BM_APBX_CTRL0_SFTRST
+#define BP_APBX_CTRL0_CLKGATE                   30
+#define BM_APBX_CTRL0_CLKGATE                   0x40000000
+#define BF_APBX_CTRL0_CLKGATE(v)                (((v) & 0x1) << 30)
+#define BFM_APBX_CTRL0_CLKGATE(v)               BM_APBX_CTRL0_CLKGATE
+#define BF_APBX_CTRL0_CLKGATE_V(e)              BF_APBX_CTRL0_CLKGATE(BV_APBX_CTRL0_CLKGATE__##e)
+#define BFM_APBX_CTRL0_CLKGATE_V(v)             BM_APBX_CTRL0_CLKGATE
+#define BP_APBX_CTRL0_RESET_CHANNEL             16
+#define BM_APBX_CTRL0_RESET_CHANNEL             0xff0000
+#define BV_APBX_CTRL0_RESET_CHANNEL__AUDIOIN    0x1
+#define BV_APBX_CTRL0_RESET_CHANNEL__AUDIOOUT   0x2
+#define BV_APBX_CTRL0_RESET_CHANNEL__SPDIF_TX   0x4
+#define BV_APBX_CTRL0_RESET_CHANNEL__SAIF2      0x4
+#define BV_APBX_CTRL0_RESET_CHANNEL__I2C        0x8
+#define BV_APBX_CTRL0_RESET_CHANNEL__SAIF1      0x10
+#define BV_APBX_CTRL0_RESET_CHANNEL__DRI        0x20
+#define BV_APBX_CTRL0_RESET_CHANNEL__UART_RX    0x40
+#define BV_APBX_CTRL0_RESET_CHANNEL__IRDA_RX    0x40
+#define BV_APBX_CTRL0_RESET_CHANNEL__UART_TX    0x80
+#define BV_APBX_CTRL0_RESET_CHANNEL__IRDA_TX    0x80
+#define BF_APBX_CTRL0_RESET_CHANNEL(v)          (((v) & 0xff) << 16)
+#define BFM_APBX_CTRL0_RESET_CHANNEL(v)         BM_APBX_CTRL0_RESET_CHANNEL
+#define BF_APBX_CTRL0_RESET_CHANNEL_V(e)        BF_APBX_CTRL0_RESET_CHANNEL(BV_APBX_CTRL0_RESET_CHANNEL__##e)
+#define BFM_APBX_CTRL0_RESET_CHANNEL_V(v)       BM_APBX_CTRL0_RESET_CHANNEL
+#define BP_APBX_CTRL0_FREEZE_CHANNEL            0
+#define BM_APBX_CTRL0_FREEZE_CHANNEL            0xff
+#define BV_APBX_CTRL0_FREEZE_CHANNEL__AUDIOIN   0x1
+#define BV_APBX_CTRL0_FREEZE_CHANNEL__AUDIOOUT  0x2
+#define BV_APBX_CTRL0_FREEZE_CHANNEL__SPDIF_TX  0x4
+#define BV_APBX_CTRL0_FREEZE_CHANNEL__SAIF2     0x4
+#define BV_APBX_CTRL0_FREEZE_CHANNEL__I2C       0x8
+#define BV_APBX_CTRL0_FREEZE_CHANNEL__SAIF1     0x10
+#define BV_APBX_CTRL0_FREEZE_CHANNEL__DRI       0x20
+#define BV_APBX_CTRL0_FREEZE_CHANNEL__UART_RX   0x40
+#define BV_APBX_CTRL0_FREEZE_CHANNEL__IRDA_RX   0x40
+#define BV_APBX_CTRL0_FREEZE_CHANNEL__UART_TX   0x80
+#define BV_APBX_CTRL0_FREEZE_CHANNEL__IRDA_TX   0x80
+#define BF_APBX_CTRL0_FREEZE_CHANNEL(v)         (((v) & 0xff) << 0)
+#define BFM_APBX_CTRL0_FREEZE_CHANNEL(v)        BM_APBX_CTRL0_FREEZE_CHANNEL
+#define BF_APBX_CTRL0_FREEZE_CHANNEL_V(e)       BF_APBX_CTRL0_FREEZE_CHANNEL(BV_APBX_CTRL0_FREEZE_CHANNEL__##e)
+#define BFM_APBX_CTRL0_FREEZE_CHANNEL_V(v)      BM_APBX_CTRL0_FREEZE_CHANNEL
+
+#define HW_APBX_CTRL1                           HW(APBX_CTRL1)
+#define HWA_APBX_CTRL1                          (0x80024000 + 0x10)
+#define HWT_APBX_CTRL1                          HWIO_32_RW
+#define HWN_APBX_CTRL1                          APBX_CTRL1
+#define HWI_APBX_CTRL1                          
+#define HW_APBX_CTRL1_SET                       HW(APBX_CTRL1_SET)
+#define HWA_APBX_CTRL1_SET                      (HWA_APBX_CTRL1 + 0x4)
+#define HWT_APBX_CTRL1_SET                      HWIO_32_WO
+#define HWN_APBX_CTRL1_SET                      APBX_CTRL1
+#define HWI_APBX_CTRL1_SET                      
+#define HW_APBX_CTRL1_CLR                       HW(APBX_CTRL1_CLR)
+#define HWA_APBX_CTRL1_CLR                      (HWA_APBX_CTRL1 + 0x8)
+#define HWT_APBX_CTRL1_CLR                      HWIO_32_WO
+#define HWN_APBX_CTRL1_CLR                      APBX_CTRL1
+#define HWI_APBX_CTRL1_CLR                      
+#define HW_APBX_CTRL1_TOG                       HW(APBX_CTRL1_TOG)
+#define HWA_APBX_CTRL1_TOG                      (HWA_APBX_CTRL1 + 0xc)
+#define HWT_APBX_CTRL1_TOG                      HWIO_32_WO
+#define HWN_APBX_CTRL1_TOG                      APBX_CTRL1
+#define HWI_APBX_CTRL1_TOG                      
+#define BP_APBX_CTRL1_CH_AHB_ERROR_IRQ          16
+#define BM_APBX_CTRL1_CH_AHB_ERROR_IRQ          0xff0000
+#define BF_APBX_CTRL1_CH_AHB_ERROR_IRQ(v)       (((v) & 0xff) << 16)
+#define BFM_APBX_CTRL1_CH_AHB_ERROR_IRQ(v)      BM_APBX_CTRL1_CH_AHB_ERROR_IRQ
+#define BF_APBX_CTRL1_CH_AHB_ERROR_IRQ_V(e)     BF_APBX_CTRL1_CH_AHB_ERROR_IRQ(BV_APBX_CTRL1_CH_AHB_ERROR_IRQ__##e)
+#define BFM_APBX_CTRL1_CH_AHB_ERROR_IRQ_V(v)    BM_APBX_CTRL1_CH_AHB_ERROR_IRQ
+#define BP_APBX_CTRL1_CH_CMDCMPLT_IRQ_EN        8
+#define BM_APBX_CTRL1_CH_CMDCMPLT_IRQ_EN        0xff00
+#define BF_APBX_CTRL1_CH_CMDCMPLT_IRQ_EN(v)     (((v) & 0xff) << 8)
+#define BFM_APBX_CTRL1_CH_CMDCMPLT_IRQ_EN(v)    BM_APBX_CTRL1_CH_CMDCMPLT_IRQ_EN
+#define BF_APBX_CTRL1_CH_CMDCMPLT_IRQ_EN_V(e)   BF_APBX_CTRL1_CH_CMDCMPLT_IRQ_EN(BV_APBX_CTRL1_CH_CMDCMPLT_IRQ_EN__##e)
+#define BFM_APBX_CTRL1_CH_CMDCMPLT_IRQ_EN_V(v)  BM_APBX_CTRL1_CH_CMDCMPLT_IRQ_EN
+#define BP_APBX_CTRL1_CH_CMDCMPLT_IRQ           0
+#define BM_APBX_CTRL1_CH_CMDCMPLT_IRQ           0xff
+#define BF_APBX_CTRL1_CH_CMDCMPLT_IRQ(v)        (((v) & 0xff) << 0)
+#define BFM_APBX_CTRL1_CH_CMDCMPLT_IRQ(v)       BM_APBX_CTRL1_CH_CMDCMPLT_IRQ
+#define BF_APBX_CTRL1_CH_CMDCMPLT_IRQ_V(e)      BF_APBX_CTRL1_CH_CMDCMPLT_IRQ(BV_APBX_CTRL1_CH_CMDCMPLT_IRQ__##e)
+#define BFM_APBX_CTRL1_CH_CMDCMPLT_IRQ_V(v)     BM_APBX_CTRL1_CH_CMDCMPLT_IRQ
+
+#define HW_APBX_DEVSEL                  HW(APBX_DEVSEL)
+#define HWA_APBX_DEVSEL                 (0x80024000 + 0x20)
+#define HWT_APBX_DEVSEL                 HWIO_32_RW
+#define HWN_APBX_DEVSEL                 APBX_DEVSEL
+#define HWI_APBX_DEVSEL                 
+#define BP_APBX_DEVSEL_CH7              28
+#define BM_APBX_DEVSEL_CH7              0xf0000000
+#define BV_APBX_DEVSEL_CH7__USE_UART    0x0
+#define BV_APBX_DEVSEL_CH7__USE_IRDA    0x1
+#define BF_APBX_DEVSEL_CH7(v)           (((v) & 0xf) << 28)
+#define BFM_APBX_DEVSEL_CH7(v)          BM_APBX_DEVSEL_CH7
+#define BF_APBX_DEVSEL_CH7_V(e)         BF_APBX_DEVSEL_CH7(BV_APBX_DEVSEL_CH7__##e)
+#define BFM_APBX_DEVSEL_CH7_V(v)        BM_APBX_DEVSEL_CH7
+#define BP_APBX_DEVSEL_CH6              24
+#define BM_APBX_DEVSEL_CH6              0xf000000
+#define BV_APBX_DEVSEL_CH6__USE_UART    0x0
+#define BV_APBX_DEVSEL_CH6__USE_IRDA    0x1
+#define BF_APBX_DEVSEL_CH6(v)           (((v) & 0xf) << 24)
+#define BFM_APBX_DEVSEL_CH6(v)          BM_APBX_DEVSEL_CH6
+#define BF_APBX_DEVSEL_CH6_V(e)         BF_APBX_DEVSEL_CH6(BV_APBX_DEVSEL_CH6__##e)
+#define BFM_APBX_DEVSEL_CH6_V(v)        BM_APBX_DEVSEL_CH6
+#define BP_APBX_DEVSEL_CH5              20
+#define BM_APBX_DEVSEL_CH5              0xf00000
+#define BF_APBX_DEVSEL_CH5(v)           (((v) & 0xf) << 20)
+#define BFM_APBX_DEVSEL_CH5(v)          BM_APBX_DEVSEL_CH5
+#define BF_APBX_DEVSEL_CH5_V(e)         BF_APBX_DEVSEL_CH5(BV_APBX_DEVSEL_CH5__##e)
+#define BFM_APBX_DEVSEL_CH5_V(v)        BM_APBX_DEVSEL_CH5
+#define BP_APBX_DEVSEL_CH4              16
+#define BM_APBX_DEVSEL_CH4              0xf0000
+#define BF_APBX_DEVSEL_CH4(v)           (((v) & 0xf) << 16)
+#define BFM_APBX_DEVSEL_CH4(v)          BM_APBX_DEVSEL_CH4
+#define BF_APBX_DEVSEL_CH4_V(e)         BF_APBX_DEVSEL_CH4(BV_APBX_DEVSEL_CH4__##e)
+#define BFM_APBX_DEVSEL_CH4_V(v)        BM_APBX_DEVSEL_CH4
+#define BP_APBX_DEVSEL_CH3              12
+#define BM_APBX_DEVSEL_CH3              0xf000
+#define BF_APBX_DEVSEL_CH3(v)           (((v) & 0xf) << 12)
+#define BFM_APBX_DEVSEL_CH3(v)          BM_APBX_DEVSEL_CH3
+#define BF_APBX_DEVSEL_CH3_V(e)         BF_APBX_DEVSEL_CH3(BV_APBX_DEVSEL_CH3__##e)
+#define BFM_APBX_DEVSEL_CH3_V(v)        BM_APBX_DEVSEL_CH3
+#define BP_APBX_DEVSEL_CH2              8
+#define BM_APBX_DEVSEL_CH2              0xf00
+#define BV_APBX_DEVSEL_CH2__USE_SPDIF   0x0
+#define BV_APBX_DEVSEL_CH2__USE_SAIF2   0x1
+#define BF_APBX_DEVSEL_CH2(v)           (((v) & 0xf) << 8)
+#define BFM_APBX_DEVSEL_CH2(v)          BM_APBX_DEVSEL_CH2
+#define BF_APBX_DEVSEL_CH2_V(e)         BF_APBX_DEVSEL_CH2(BV_APBX_DEVSEL_CH2__##e)
+#define BFM_APBX_DEVSEL_CH2_V(v)        BM_APBX_DEVSEL_CH2
+#define BP_APBX_DEVSEL_CH1              4
+#define BM_APBX_DEVSEL_CH1              0xf0
+#define BF_APBX_DEVSEL_CH1(v)           (((v) & 0xf) << 4)
+#define BFM_APBX_DEVSEL_CH1(v)          BM_APBX_DEVSEL_CH1
+#define BF_APBX_DEVSEL_CH1_V(e)         BF_APBX_DEVSEL_CH1(BV_APBX_DEVSEL_CH1__##e)
+#define BFM_APBX_DEVSEL_CH1_V(v)        BM_APBX_DEVSEL_CH1
+#define BP_APBX_DEVSEL_CH0              0
+#define BM_APBX_DEVSEL_CH0              0xf
+#define BF_APBX_DEVSEL_CH0(v)           (((v) & 0xf) << 0)
+#define BFM_APBX_DEVSEL_CH0(v)          BM_APBX_DEVSEL_CH0
+#define BF_APBX_DEVSEL_CH0_V(e)         BF_APBX_DEVSEL_CH0(BV_APBX_DEVSEL_CH0__##e)
+#define BFM_APBX_DEVSEL_CH0_V(v)        BM_APBX_DEVSEL_CH0
+
+#define HW_APBX_CHn_CURCMDAR(_n1)           HW(APBX_CHn_CURCMDAR(_n1))
+#define HWA_APBX_CHn_CURCMDAR(_n1)          (0x80024000 + 0x40 + (_n1) * 0x70)
+#define HWT_APBX_CHn_CURCMDAR(_n1)          HWIO_32_RW
+#define HWN_APBX_CHn_CURCMDAR(_n1)          APBX_CHn_CURCMDAR
+#define HWI_APBX_CHn_CURCMDAR(_n1)          (_n1)
+#define BP_APBX_CHn_CURCMDAR_CMD_ADDR       0
+#define BM_APBX_CHn_CURCMDAR_CMD_ADDR       0xffffffff
+#define BF_APBX_CHn_CURCMDAR_CMD_ADDR(v)    (((v) & 0xffffffff) << 0)
+#define BFM_APBX_CHn_CURCMDAR_CMD_ADDR(v)   BM_APBX_CHn_CURCMDAR_CMD_ADDR
+#define BF_APBX_CHn_CURCMDAR_CMD_ADDR_V(e)  BF_APBX_CHn_CURCMDAR_CMD_ADDR(BV_APBX_CHn_CURCMDAR_CMD_ADDR__##e)
+#define BFM_APBX_CHn_CURCMDAR_CMD_ADDR_V(v) BM_APBX_CHn_CURCMDAR_CMD_ADDR
+
+#define HW_APBX_CHn_NXTCMDAR(_n1)           HW(APBX_CHn_NXTCMDAR(_n1))
+#define HWA_APBX_CHn_NXTCMDAR(_n1)          (0x80024000 + 0x50 + (_n1) * 0x70)
+#define HWT_APBX_CHn_NXTCMDAR(_n1)          HWIO_32_RW
+#define HWN_APBX_CHn_NXTCMDAR(_n1)          APBX_CHn_NXTCMDAR
+#define HWI_APBX_CHn_NXTCMDAR(_n1)          (_n1)
+#define BP_APBX_CHn_NXTCMDAR_CMD_ADDR       0
+#define BM_APBX_CHn_NXTCMDAR_CMD_ADDR       0xffffffff
+#define BF_APBX_CHn_NXTCMDAR_CMD_ADDR(v)    (((v) & 0xffffffff) << 0)
+#define BFM_APBX_CHn_NXTCMDAR_CMD_ADDR(v)   BM_APBX_CHn_NXTCMDAR_CMD_ADDR
+#define BF_APBX_CHn_NXTCMDAR_CMD_ADDR_V(e)  BF_APBX_CHn_NXTCMDAR_CMD_ADDR(BV_APBX_CHn_NXTCMDAR_CMD_ADDR__##e)
+#define BFM_APBX_CHn_NXTCMDAR_CMD_ADDR_V(v) BM_APBX_CHn_NXTCMDAR_CMD_ADDR
+
+#define HW_APBX_CHn_CMD(_n1)                    HW(APBX_CHn_CMD(_n1))
+#define HWA_APBX_CHn_CMD(_n1)                   (0x80024000 + 0x60 + (_n1) * 0x70)
+#define HWT_APBX_CHn_CMD(_n1)                   HWIO_32_RW
+#define HWN_APBX_CHn_CMD(_n1)                   APBX_CHn_CMD
+#define HWI_APBX_CHn_CMD(_n1)                   (_n1)
+#define BP_APBX_CHn_CMD_XFER_COUNT              16
+#define BM_APBX_CHn_CMD_XFER_COUNT              0xffff0000
+#define BF_APBX_CHn_CMD_XFER_COUNT(v)           (((v) & 0xffff) << 16)
+#define BFM_APBX_CHn_CMD_XFER_COUNT(v)          BM_APBX_CHn_CMD_XFER_COUNT
+#define BF_APBX_CHn_CMD_XFER_COUNT_V(e)         BF_APBX_CHn_CMD_XFER_COUNT(BV_APBX_CHn_CMD_XFER_COUNT__##e)
+#define BFM_APBX_CHn_CMD_XFER_COUNT_V(v)        BM_APBX_CHn_CMD_XFER_COUNT
+#define BP_APBX_CHn_CMD_CMDWORDS                12
+#define BM_APBX_CHn_CMD_CMDWORDS                0xf000
+#define BF_APBX_CHn_CMD_CMDWORDS(v)             (((v) & 0xf) << 12)
+#define BFM_APBX_CHn_CMD_CMDWORDS(v)            BM_APBX_CHn_CMD_CMDWORDS
+#define BF_APBX_CHn_CMD_CMDWORDS_V(e)           BF_APBX_CHn_CMD_CMDWORDS(BV_APBX_CHn_CMD_CMDWORDS__##e)
+#define BFM_APBX_CHn_CMD_CMDWORDS_V(v)          BM_APBX_CHn_CMD_CMDWORDS
+#define BP_APBX_CHn_CMD_WAIT4ENDCMD             7
+#define BM_APBX_CHn_CMD_WAIT4ENDCMD             0x80
+#define BF_APBX_CHn_CMD_WAIT4ENDCMD(v)          (((v) & 0x1) << 7)
+#define BFM_APBX_CHn_CMD_WAIT4ENDCMD(v)         BM_APBX_CHn_CMD_WAIT4ENDCMD
+#define BF_APBX_CHn_CMD_WAIT4ENDCMD_V(e)        BF_APBX_CHn_CMD_WAIT4ENDCMD(BV_APBX_CHn_CMD_WAIT4ENDCMD__##e)
+#define BFM_APBX_CHn_CMD_WAIT4ENDCMD_V(v)       BM_APBX_CHn_CMD_WAIT4ENDCMD
+#define BP_APBX_CHn_CMD_SEMAPHORE               6
+#define BM_APBX_CHn_CMD_SEMAPHORE               0x40
+#define BF_APBX_CHn_CMD_SEMAPHORE(v)            (((v) & 0x1) << 6)
+#define BFM_APBX_CHn_CMD_SEMAPHORE(v)           BM_APBX_CHn_CMD_SEMAPHORE
+#define BF_APBX_CHn_CMD_SEMAPHORE_V(e)          BF_APBX_CHn_CMD_SEMAPHORE(BV_APBX_CHn_CMD_SEMAPHORE__##e)
+#define BFM_APBX_CHn_CMD_SEMAPHORE_V(v)         BM_APBX_CHn_CMD_SEMAPHORE
+#define BP_APBX_CHn_CMD_IRQONCMPLT              3
+#define BM_APBX_CHn_CMD_IRQONCMPLT              0x8
+#define BF_APBX_CHn_CMD_IRQONCMPLT(v)           (((v) & 0x1) << 3)
+#define BFM_APBX_CHn_CMD_IRQONCMPLT(v)          BM_APBX_CHn_CMD_IRQONCMPLT
+#define BF_APBX_CHn_CMD_IRQONCMPLT_V(e)         BF_APBX_CHn_CMD_IRQONCMPLT(BV_APBX_CHn_CMD_IRQONCMPLT__##e)
+#define BFM_APBX_CHn_CMD_IRQONCMPLT_V(v)        BM_APBX_CHn_CMD_IRQONCMPLT
+#define BP_APBX_CHn_CMD_CHAIN                   2
+#define BM_APBX_CHn_CMD_CHAIN                   0x4
+#define BF_APBX_CHn_CMD_CHAIN(v)                (((v) & 0x1) << 2)
+#define BFM_APBX_CHn_CMD_CHAIN(v)               BM_APBX_CHn_CMD_CHAIN
+#define BF_APBX_CHn_CMD_CHAIN_V(e)              BF_APBX_CHn_CMD_CHAIN(BV_APBX_CHn_CMD_CHAIN__##e)
+#define BFM_APBX_CHn_CMD_CHAIN_V(v)             BM_APBX_CHn_CMD_CHAIN
+#define BP_APBX_CHn_CMD_COMMAND                 0
+#define BM_APBX_CHn_CMD_COMMAND                 0x3
+#define BV_APBX_CHn_CMD_COMMAND__NO_DMA_XFER    0x0
+#define BV_APBX_CHn_CMD_COMMAND__DMA_WRITE      0x1
+#define BV_APBX_CHn_CMD_COMMAND__DMA_READ       0x2
+#define BF_APBX_CHn_CMD_COMMAND(v)              (((v) & 0x3) << 0)
+#define BFM_APBX_CHn_CMD_COMMAND(v)             BM_APBX_CHn_CMD_COMMAND
+#define BF_APBX_CHn_CMD_COMMAND_V(e)            BF_APBX_CHn_CMD_COMMAND(BV_APBX_CHn_CMD_COMMAND__##e)
+#define BFM_APBX_CHn_CMD_COMMAND_V(v)           BM_APBX_CHn_CMD_COMMAND
+
+#define HW_APBX_CHn_BAR(_n1)            HW(APBX_CHn_BAR(_n1))
+#define HWA_APBX_CHn_BAR(_n1)           (0x80024000 + 0x70 + (_n1) * 0x70)
+#define HWT_APBX_CHn_BAR(_n1)           HWIO_32_RW
+#define HWN_APBX_CHn_BAR(_n1)           APBX_CHn_BAR
+#define HWI_APBX_CHn_BAR(_n1)           (_n1)
+#define BP_APBX_CHn_BAR_ADDRESS         0
+#define BM_APBX_CHn_BAR_ADDRESS         0xffffffff
+#define BF_APBX_CHn_BAR_ADDRESS(v)      (((v) & 0xffffffff) << 0)
+#define BFM_APBX_CHn_BAR_ADDRESS(v)     BM_APBX_CHn_BAR_ADDRESS
+#define BF_APBX_CHn_BAR_ADDRESS_V(e)    BF_APBX_CHn_BAR_ADDRESS(BV_APBX_CHn_BAR_ADDRESS__##e)
+#define BFM_APBX_CHn_BAR_ADDRESS_V(v)   BM_APBX_CHn_BAR_ADDRESS
+
+#define HW_APBX_CHn_SEMA(_n1)                   HW(APBX_CHn_SEMA(_n1))
+#define HWA_APBX_CHn_SEMA(_n1)                  (0x80024000 + 0x80 + (_n1) * 0x70)
+#define HWT_APBX_CHn_SEMA(_n1)                  HWIO_32_RW
+#define HWN_APBX_CHn_SEMA(_n1)                  APBX_CHn_SEMA
+#define HWI_APBX_CHn_SEMA(_n1)                  (_n1)
+#define BP_APBX_CHn_SEMA_PHORE                  16
+#define BM_APBX_CHn_SEMA_PHORE                  0xff0000
+#define BF_APBX_CHn_SEMA_PHORE(v)               (((v) & 0xff) << 16)
+#define BFM_APBX_CHn_SEMA_PHORE(v)              BM_APBX_CHn_SEMA_PHORE
+#define BF_APBX_CHn_SEMA_PHORE_V(e)             BF_APBX_CHn_SEMA_PHORE(BV_APBX_CHn_SEMA_PHORE__##e)
+#define BFM_APBX_CHn_SEMA_PHORE_V(v)            BM_APBX_CHn_SEMA_PHORE
+#define BP_APBX_CHn_SEMA_INCREMENT_SEMA         0
+#define BM_APBX_CHn_SEMA_INCREMENT_SEMA         0xff
+#define BF_APBX_CHn_SEMA_INCREMENT_SEMA(v)      (((v) & 0xff) << 0)
+#define BFM_APBX_CHn_SEMA_INCREMENT_SEMA(v)     BM_APBX_CHn_SEMA_INCREMENT_SEMA
+#define BF_APBX_CHn_SEMA_INCREMENT_SEMA_V(e)    BF_APBX_CHn_SEMA_INCREMENT_SEMA(BV_APBX_CHn_SEMA_INCREMENT_SEMA__##e)
+#define BFM_APBX_CHn_SEMA_INCREMENT_SEMA_V(v)   BM_APBX_CHn_SEMA_INCREMENT_SEMA
+
+#define HW_APBX_CHn_DEBUG1(_n1)                         HW(APBX_CHn_DEBUG1(_n1))
+#define HWA_APBX_CHn_DEBUG1(_n1)                        (0x80024000 + 0x90 + (_n1) * 0x70)
+#define HWT_APBX_CHn_DEBUG1(_n1)                        HWIO_32_RW
+#define HWN_APBX_CHn_DEBUG1(_n1)                        APBX_CHn_DEBUG1
+#define HWI_APBX_CHn_DEBUG1(_n1)                        (_n1)
+#define BP_APBX_CHn_DEBUG1_REQ                          31
+#define BM_APBX_CHn_DEBUG1_REQ                          0x80000000
+#define BF_APBX_CHn_DEBUG1_REQ(v)                       (((v) & 0x1) << 31)
+#define BFM_APBX_CHn_DEBUG1_REQ(v)                      BM_APBX_CHn_DEBUG1_REQ
+#define BF_APBX_CHn_DEBUG1_REQ_V(e)                     BF_APBX_CHn_DEBUG1_REQ(BV_APBX_CHn_DEBUG1_REQ__##e)
+#define BFM_APBX_CHn_DEBUG1_REQ_V(v)                    BM_APBX_CHn_DEBUG1_REQ
+#define BP_APBX_CHn_DEBUG1_BURST                        30
+#define BM_APBX_CHn_DEBUG1_BURST                        0x40000000
+#define BF_APBX_CHn_DEBUG1_BURST(v)                     (((v) & 0x1) << 30)
+#define BFM_APBX_CHn_DEBUG1_BURST(v)                    BM_APBX_CHn_DEBUG1_BURST
+#define BF_APBX_CHn_DEBUG1_BURST_V(e)                   BF_APBX_CHn_DEBUG1_BURST(BV_APBX_CHn_DEBUG1_BURST__##e)
+#define BFM_APBX_CHn_DEBUG1_BURST_V(v)                  BM_APBX_CHn_DEBUG1_BURST
+#define BP_APBX_CHn_DEBUG1_KICK                         29
+#define BM_APBX_CHn_DEBUG1_KICK                         0x20000000
+#define BF_APBX_CHn_DEBUG1_KICK(v)                      (((v) & 0x1) << 29)
+#define BFM_APBX_CHn_DEBUG1_KICK(v)                     BM_APBX_CHn_DEBUG1_KICK
+#define BF_APBX_CHn_DEBUG1_KICK_V(e)                    BF_APBX_CHn_DEBUG1_KICK(BV_APBX_CHn_DEBUG1_KICK__##e)
+#define BFM_APBX_CHn_DEBUG1_KICK_V(v)                   BM_APBX_CHn_DEBUG1_KICK
+#define BP_APBX_CHn_DEBUG1_END                          28
+#define BM_APBX_CHn_DEBUG1_END                          0x10000000
+#define BF_APBX_CHn_DEBUG1_END(v)                       (((v) & 0x1) << 28)
+#define BFM_APBX_CHn_DEBUG1_END(v)                      BM_APBX_CHn_DEBUG1_END
+#define BF_APBX_CHn_DEBUG1_END_V(e)                     BF_APBX_CHn_DEBUG1_END(BV_APBX_CHn_DEBUG1_END__##e)
+#define BFM_APBX_CHn_DEBUG1_END_V(v)                    BM_APBX_CHn_DEBUG1_END
+#define BP_APBX_CHn_DEBUG1_NEXTCMDADDRVALID             24
+#define BM_APBX_CHn_DEBUG1_NEXTCMDADDRVALID             0x1000000
+#define BF_APBX_CHn_DEBUG1_NEXTCMDADDRVALID(v)          (((v) & 0x1) << 24)
+#define BFM_APBX_CHn_DEBUG1_NEXTCMDADDRVALID(v)         BM_APBX_CHn_DEBUG1_NEXTCMDADDRVALID
+#define BF_APBX_CHn_DEBUG1_NEXTCMDADDRVALID_V(e)        BF_APBX_CHn_DEBUG1_NEXTCMDADDRVALID(BV_APBX_CHn_DEBUG1_NEXTCMDADDRVALID__##e)
+#define BFM_APBX_CHn_DEBUG1_NEXTCMDADDRVALID_V(v)       BM_APBX_CHn_DEBUG1_NEXTCMDADDRVALID
+#define BP_APBX_CHn_DEBUG1_RD_FIFO_EMPTY                23
+#define BM_APBX_CHn_DEBUG1_RD_FIFO_EMPTY                0x800000
+#define BF_APBX_CHn_DEBUG1_RD_FIFO_EMPTY(v)             (((v) & 0x1) << 23)
+#define BFM_APBX_CHn_DEBUG1_RD_FIFO_EMPTY(v)            BM_APBX_CHn_DEBUG1_RD_FIFO_EMPTY
+#define BF_APBX_CHn_DEBUG1_RD_FIFO_EMPTY_V(e)           BF_APBX_CHn_DEBUG1_RD_FIFO_EMPTY(BV_APBX_CHn_DEBUG1_RD_FIFO_EMPTY__##e)
+#define BFM_APBX_CHn_DEBUG1_RD_FIFO_EMPTY_V(v)          BM_APBX_CHn_DEBUG1_RD_FIFO_EMPTY
+#define BP_APBX_CHn_DEBUG1_RD_FIFO_FULL                 22
+#define BM_APBX_CHn_DEBUG1_RD_FIFO_FULL                 0x400000
+#define BF_APBX_CHn_DEBUG1_RD_FIFO_FULL(v)              (((v) & 0x1) << 22)
+#define BFM_APBX_CHn_DEBUG1_RD_FIFO_FULL(v)             BM_APBX_CHn_DEBUG1_RD_FIFO_FULL
+#define BF_APBX_CHn_DEBUG1_RD_FIFO_FULL_V(e)            BF_APBX_CHn_DEBUG1_RD_FIFO_FULL(BV_APBX_CHn_DEBUG1_RD_FIFO_FULL__##e)
+#define BFM_APBX_CHn_DEBUG1_RD_FIFO_FULL_V(v)           BM_APBX_CHn_DEBUG1_RD_FIFO_FULL
+#define BP_APBX_CHn_DEBUG1_WR_FIFO_EMPTY                21
+#define BM_APBX_CHn_DEBUG1_WR_FIFO_EMPTY                0x200000
+#define BF_APBX_CHn_DEBUG1_WR_FIFO_EMPTY(v)             (((v) & 0x1) << 21)
+#define BFM_APBX_CHn_DEBUG1_WR_FIFO_EMPTY(v)            BM_APBX_CHn_DEBUG1_WR_FIFO_EMPTY
+#define BF_APBX_CHn_DEBUG1_WR_FIFO_EMPTY_V(e)           BF_APBX_CHn_DEBUG1_WR_FIFO_EMPTY(BV_APBX_CHn_DEBUG1_WR_FIFO_EMPTY__##e)
+#define BFM_APBX_CHn_DEBUG1_WR_FIFO_EMPTY_V(v)          BM_APBX_CHn_DEBUG1_WR_FIFO_EMPTY
+#define BP_APBX_CHn_DEBUG1_WR_FIFO_FULL                 20
+#define BM_APBX_CHn_DEBUG1_WR_FIFO_FULL                 0x100000
+#define BF_APBX_CHn_DEBUG1_WR_FIFO_FULL(v)              (((v) & 0x1) << 20)
+#define BFM_APBX_CHn_DEBUG1_WR_FIFO_FULL(v)             BM_APBX_CHn_DEBUG1_WR_FIFO_FULL
+#define BF_APBX_CHn_DEBUG1_WR_FIFO_FULL_V(e)            BF_APBX_CHn_DEBUG1_WR_FIFO_FULL(BV_APBX_CHn_DEBUG1_WR_FIFO_FULL__##e)
+#define BFM_APBX_CHn_DEBUG1_WR_FIFO_FULL_V(v)           BM_APBX_CHn_DEBUG1_WR_FIFO_FULL
+#define BP_APBX_CHn_DEBUG1_STATEMACHINE                 0
+#define BM_APBX_CHn_DEBUG1_STATEMACHINE                 0x1f
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__IDLE           0x0
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD1       0x1
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD3       0x2
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD2       0x3
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__XFER_DECODE    0x4
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_WAIT       0x5
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD4       0x6
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__PIO_REQ        0x7
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__READ_FLUSH     0x8
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__READ_WAIT      0x9
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__WRITE          0xc
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__READ_REQ       0xd
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__CHECK_CHAIN    0xe
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__XFER_COMPLETE  0xf
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__WAIT_END       0x15
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__WRITE_WAIT     0x1c
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__CHECK_WAIT     0x1e
+#define BF_APBX_CHn_DEBUG1_STATEMACHINE(v)              (((v) & 0x1f) << 0)
+#define BFM_APBX_CHn_DEBUG1_STATEMACHINE(v)             BM_APBX_CHn_DEBUG1_STATEMACHINE
+#define BF_APBX_CHn_DEBUG1_STATEMACHINE_V(e)            BF_APBX_CHn_DEBUG1_STATEMACHINE(BV_APBX_CHn_DEBUG1_STATEMACHINE__##e)
+#define BFM_APBX_CHn_DEBUG1_STATEMACHINE_V(v)           BM_APBX_CHn_DEBUG1_STATEMACHINE
+
+#define HW_APBX_CHn_DEBUG2(_n1)             HW(APBX_CHn_DEBUG2(_n1))
+#define HWA_APBX_CHn_DEBUG2(_n1)            (0x80024000 + 0xa0 + (_n1) * 0x70)
+#define HWT_APBX_CHn_DEBUG2(_n1)            HWIO_32_RW
+#define HWN_APBX_CHn_DEBUG2(_n1)            APBX_CHn_DEBUG2
+#define HWI_APBX_CHn_DEBUG2(_n1)            (_n1)
+#define BP_APBX_CHn_DEBUG2_APB_BYTES        16
+#define BM_APBX_CHn_DEBUG2_APB_BYTES        0xffff0000
+#define BF_APBX_CHn_DEBUG2_APB_BYTES(v)     (((v) & 0xffff) << 16)
+#define BFM_APBX_CHn_DEBUG2_APB_BYTES(v)    BM_APBX_CHn_DEBUG2_APB_BYTES
+#define BF_APBX_CHn_DEBUG2_APB_BYTES_V(e)   BF_APBX_CHn_DEBUG2_APB_BYTES(BV_APBX_CHn_DEBUG2_APB_BYTES__##e)
+#define BFM_APBX_CHn_DEBUG2_APB_BYTES_V(v)  BM_APBX_CHn_DEBUG2_APB_BYTES
+#define BP_APBX_CHn_DEBUG2_AHB_BYTES        0
+#define BM_APBX_CHn_DEBUG2_AHB_BYTES        0xffff
+#define BF_APBX_CHn_DEBUG2_AHB_BYTES(v)     (((v) & 0xffff) << 0)
+#define BFM_APBX_CHn_DEBUG2_AHB_BYTES(v)    BM_APBX_CHn_DEBUG2_AHB_BYTES
+#define BF_APBX_CHn_DEBUG2_AHB_BYTES_V(e)   BF_APBX_CHn_DEBUG2_AHB_BYTES(BV_APBX_CHn_DEBUG2_AHB_BYTES__##e)
+#define BFM_APBX_CHn_DEBUG2_AHB_BYTES_V(v)  BM_APBX_CHn_DEBUG2_AHB_BYTES
+
+#define HW_APBX_VERSION             HW(APBX_VERSION)
+#define HWA_APBX_VERSION            (0x80024000 + 0x3f0)
+#define HWT_APBX_VERSION            HWIO_32_RW
+#define HWN_APBX_VERSION            APBX_VERSION
+#define HWI_APBX_VERSION            
+#define BP_APBX_VERSION_MAJOR       24
+#define BM_APBX_VERSION_MAJOR       0xff000000
+#define BF_APBX_VERSION_MAJOR(v)    (((v) & 0xff) << 24)
+#define BFM_APBX_VERSION_MAJOR(v)   BM_APBX_VERSION_MAJOR
+#define BF_APBX_VERSION_MAJOR_V(e)  BF_APBX_VERSION_MAJOR(BV_APBX_VERSION_MAJOR__##e)
+#define BFM_APBX_VERSION_MAJOR_V(v) BM_APBX_VERSION_MAJOR
+#define BP_APBX_VERSION_MINOR       16
+#define BM_APBX_VERSION_MINOR       0xff0000
+#define BF_APBX_VERSION_MINOR(v)    (((v) & 0xff) << 16)
+#define BFM_APBX_VERSION_MINOR(v)   BM_APBX_VERSION_MINOR
+#define BF_APBX_VERSION_MINOR_V(e)  BF_APBX_VERSION_MINOR(BV_APBX_VERSION_MINOR__##e)
+#define BFM_APBX_VERSION_MINOR_V(v) BM_APBX_VERSION_MINOR
+#define BP_APBX_VERSION_STEP        0
+#define BM_APBX_VERSION_STEP        0xffff
+#define BF_APBX_VERSION_STEP(v)     (((v) & 0xffff) << 0)
+#define BFM_APBX_VERSION_STEP(v)    BM_APBX_VERSION_STEP
+#define BF_APBX_VERSION_STEP_V(e)   BF_APBX_VERSION_STEP(BV_APBX_VERSION_STEP__##e)
+#define BFM_APBX_VERSION_STEP_V(v)  BM_APBX_VERSION_STEP
+
+#endif /* __HEADERGEN_STMP3700_APBX_H__*/
diff --git a/firmware/target/arm/imx233/regs/stmp3700/audioin.h b/firmware/target/arm/imx233/regs/stmp3700/audioin.h
new file mode 100644
index 0000000000..70e60a103a
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3700/audioin.h
@@ -0,0 +1,505 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * stmp3700 version: 2.4.0
+ * stmp3700 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_STMP3700_AUDIOIN_H__
+#define __HEADERGEN_STMP3700_AUDIOIN_H__
+
+#define HW_AUDIOIN_CTRL                             HW(AUDIOIN_CTRL)
+#define HWA_AUDIOIN_CTRL                            (0x8004c000 + 0x0)
+#define HWT_AUDIOIN_CTRL                            HWIO_32_RW
+#define HWN_AUDIOIN_CTRL                            AUDIOIN_CTRL
+#define HWI_AUDIOIN_CTRL                            
+#define HW_AUDIOIN_CTRL_SET                         HW(AUDIOIN_CTRL_SET)
+#define HWA_AUDIOIN_CTRL_SET                        (HWA_AUDIOIN_CTRL + 0x4)
+#define HWT_AUDIOIN_CTRL_SET                        HWIO_32_WO
+#define HWN_AUDIOIN_CTRL_SET                        AUDIOIN_CTRL
+#define HWI_AUDIOIN_CTRL_SET                        
+#define HW_AUDIOIN_CTRL_CLR                         HW(AUDIOIN_CTRL_CLR)
+#define HWA_AUDIOIN_CTRL_CLR                        (HWA_AUDIOIN_CTRL + 0x8)
+#define HWT_AUDIOIN_CTRL_CLR                        HWIO_32_WO
+#define HWN_AUDIOIN_CTRL_CLR                        AUDIOIN_CTRL
+#define HWI_AUDIOIN_CTRL_CLR                        
+#define HW_AUDIOIN_CTRL_TOG                         HW(AUDIOIN_CTRL_TOG)
+#define HWA_AUDIOIN_CTRL_TOG                        (HWA_AUDIOIN_CTRL + 0xc)
+#define HWT_AUDIOIN_CTRL_TOG                        HWIO_32_WO
+#define HWN_AUDIOIN_CTRL_TOG                        AUDIOIN_CTRL
+#define HWI_AUDIOIN_CTRL_TOG                        
+#define BP_AUDIOIN_CTRL_SFTRST                      31
+#define BM_AUDIOIN_CTRL_SFTRST                      0x80000000
+#define BF_AUDIOIN_CTRL_SFTRST(v)                   (((v) & 0x1) << 31)
+#define BFM_AUDIOIN_CTRL_SFTRST(v)                  BM_AUDIOIN_CTRL_SFTRST
+#define BF_AUDIOIN_CTRL_SFTRST_V(e)                 BF_AUDIOIN_CTRL_SFTRST(BV_AUDIOIN_CTRL_SFTRST__##e)
+#define BFM_AUDIOIN_CTRL_SFTRST_V(v)                BM_AUDIOIN_CTRL_SFTRST
+#define BP_AUDIOIN_CTRL_CLKGATE                     30
+#define BM_AUDIOIN_CTRL_CLKGATE                     0x40000000
+#define BF_AUDIOIN_CTRL_CLKGATE(v)                  (((v) & 0x1) << 30)
+#define BFM_AUDIOIN_CTRL_CLKGATE(v)                 BM_AUDIOIN_CTRL_CLKGATE
+#define BF_AUDIOIN_CTRL_CLKGATE_V(e)                BF_AUDIOIN_CTRL_CLKGATE(BV_AUDIOIN_CTRL_CLKGATE__##e)
+#define BFM_AUDIOIN_CTRL_CLKGATE_V(v)               BM_AUDIOIN_CTRL_CLKGATE
+#define BP_AUDIOIN_CTRL_DMAWAIT_COUNT               16
+#define BM_AUDIOIN_CTRL_DMAWAIT_COUNT               0x1f0000
+#define BF_AUDIOIN_CTRL_DMAWAIT_COUNT(v)            (((v) & 0x1f) << 16)
+#define BFM_AUDIOIN_CTRL_DMAWAIT_COUNT(v)           BM_AUDIOIN_CTRL_DMAWAIT_COUNT
+#define BF_AUDIOIN_CTRL_DMAWAIT_COUNT_V(e)          BF_AUDIOIN_CTRL_DMAWAIT_COUNT(BV_AUDIOIN_CTRL_DMAWAIT_COUNT__##e)
+#define BFM_AUDIOIN_CTRL_DMAWAIT_COUNT_V(v)         BM_AUDIOIN_CTRL_DMAWAIT_COUNT
+#define BP_AUDIOIN_CTRL_LR_SWAP                     10
+#define BM_AUDIOIN_CTRL_LR_SWAP                     0x400
+#define BF_AUDIOIN_CTRL_LR_SWAP(v)                  (((v) & 0x1) << 10)
+#define BFM_AUDIOIN_CTRL_LR_SWAP(v)                 BM_AUDIOIN_CTRL_LR_SWAP
+#define BF_AUDIOIN_CTRL_LR_SWAP_V(e)                BF_AUDIOIN_CTRL_LR_SWAP(BV_AUDIOIN_CTRL_LR_SWAP__##e)
+#define BFM_AUDIOIN_CTRL_LR_SWAP_V(v)               BM_AUDIOIN_CTRL_LR_SWAP
+#define BP_AUDIOIN_CTRL_EDGE_SYNC                   9
+#define BM_AUDIOIN_CTRL_EDGE_SYNC                   0x200
+#define BF_AUDIOIN_CTRL_EDGE_SYNC(v)                (((v) & 0x1) << 9)
+#define BFM_AUDIOIN_CTRL_EDGE_SYNC(v)               BM_AUDIOIN_CTRL_EDGE_SYNC
+#define BF_AUDIOIN_CTRL_EDGE_SYNC_V(e)              BF_AUDIOIN_CTRL_EDGE_SYNC(BV_AUDIOIN_CTRL_EDGE_SYNC__##e)
+#define BFM_AUDIOIN_CTRL_EDGE_SYNC_V(v)             BM_AUDIOIN_CTRL_EDGE_SYNC
+#define BP_AUDIOIN_CTRL_INVERT_1BIT                 8
+#define BM_AUDIOIN_CTRL_INVERT_1BIT                 0x100
+#define BF_AUDIOIN_CTRL_INVERT_1BIT(v)              (((v) & 0x1) << 8)
+#define BFM_AUDIOIN_CTRL_INVERT_1BIT(v)             BM_AUDIOIN_CTRL_INVERT_1BIT
+#define BF_AUDIOIN_CTRL_INVERT_1BIT_V(e)            BF_AUDIOIN_CTRL_INVERT_1BIT(BV_AUDIOIN_CTRL_INVERT_1BIT__##e)
+#define BFM_AUDIOIN_CTRL_INVERT_1BIT_V(v)           BM_AUDIOIN_CTRL_INVERT_1BIT
+#define BP_AUDIOIN_CTRL_OFFSET_ENABLE               7
+#define BM_AUDIOIN_CTRL_OFFSET_ENABLE               0x80
+#define BF_AUDIOIN_CTRL_OFFSET_ENABLE(v)            (((v) & 0x1) << 7)
+#define BFM_AUDIOIN_CTRL_OFFSET_ENABLE(v)           BM_AUDIOIN_CTRL_OFFSET_ENABLE
+#define BF_AUDIOIN_CTRL_OFFSET_ENABLE_V(e)          BF_AUDIOIN_CTRL_OFFSET_ENABLE(BV_AUDIOIN_CTRL_OFFSET_ENABLE__##e)
+#define BFM_AUDIOIN_CTRL_OFFSET_ENABLE_V(v)         BM_AUDIOIN_CTRL_OFFSET_ENABLE
+#define BP_AUDIOIN_CTRL_HPF_ENABLE                  6
+#define BM_AUDIOIN_CTRL_HPF_ENABLE                  0x40
+#define BF_AUDIOIN_CTRL_HPF_ENABLE(v)               (((v) & 0x1) << 6)
+#define BFM_AUDIOIN_CTRL_HPF_ENABLE(v)              BM_AUDIOIN_CTRL_HPF_ENABLE
+#define BF_AUDIOIN_CTRL_HPF_ENABLE_V(e)             BF_AUDIOIN_CTRL_HPF_ENABLE(BV_AUDIOIN_CTRL_HPF_ENABLE__##e)
+#define BFM_AUDIOIN_CTRL_HPF_ENABLE_V(v)            BM_AUDIOIN_CTRL_HPF_ENABLE
+#define BP_AUDIOIN_CTRL_WORD_LENGTH                 5
+#define BM_AUDIOIN_CTRL_WORD_LENGTH                 0x20
+#define BF_AUDIOIN_CTRL_WORD_LENGTH(v)              (((v) & 0x1) << 5)
+#define BFM_AUDIOIN_CTRL_WORD_LENGTH(v)             BM_AUDIOIN_CTRL_WORD_LENGTH
+#define BF_AUDIOIN_CTRL_WORD_LENGTH_V(e)            BF_AUDIOIN_CTRL_WORD_LENGTH(BV_AUDIOIN_CTRL_WORD_LENGTH__##e)
+#define BFM_AUDIOIN_CTRL_WORD_LENGTH_V(v)           BM_AUDIOIN_CTRL_WORD_LENGTH
+#define BP_AUDIOIN_CTRL_LOOPBACK                    4
+#define BM_AUDIOIN_CTRL_LOOPBACK                    0x10
+#define BF_AUDIOIN_CTRL_LOOPBACK(v)                 (((v) & 0x1) << 4)
+#define BFM_AUDIOIN_CTRL_LOOPBACK(v)                BM_AUDIOIN_CTRL_LOOPBACK
+#define BF_AUDIOIN_CTRL_LOOPBACK_V(e)               BF_AUDIOIN_CTRL_LOOPBACK(BV_AUDIOIN_CTRL_LOOPBACK__##e)
+#define BFM_AUDIOIN_CTRL_LOOPBACK_V(v)              BM_AUDIOIN_CTRL_LOOPBACK
+#define BP_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ          3
+#define BM_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ          0x8
+#define BF_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ(v)       (((v) & 0x1) << 3)
+#define BFM_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ(v)      BM_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ
+#define BF_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ_V(e)     BF_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ(BV_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ__##e)
+#define BFM_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ_V(v)    BM_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ
+#define BP_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ           2
+#define BM_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ           0x4
+#define BF_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ(v)        (((v) & 0x1) << 2)
+#define BFM_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ(v)       BM_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ
+#define BF_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ_V(e)      BF_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ(BV_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ__##e)
+#define BFM_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ_V(v)     BM_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ
+#define BP_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN           1
+#define BM_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN           0x2
+#define BF_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN(v)        (((v) & 0x1) << 1)
+#define BFM_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN(v)       BM_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN
+#define BF_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN_V(e)      BF_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN(BV_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN__##e)
+#define BFM_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN_V(v)     BM_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN
+#define BP_AUDIOIN_CTRL_RUN                         0
+#define BM_AUDIOIN_CTRL_RUN                         0x1
+#define BF_AUDIOIN_CTRL_RUN(v)                      (((v) & 0x1) << 0)
+#define BFM_AUDIOIN_CTRL_RUN(v)                     BM_AUDIOIN_CTRL_RUN
+#define BF_AUDIOIN_CTRL_RUN_V(e)                    BF_AUDIOIN_CTRL_RUN(BV_AUDIOIN_CTRL_RUN__##e)
+#define BFM_AUDIOIN_CTRL_RUN_V(v)                   BM_AUDIOIN_CTRL_RUN
+
+#define HW_AUDIOIN_STAT                     HW(AUDIOIN_STAT)
+#define HWA_AUDIOIN_STAT                    (0x8004c000 + 0x10)
+#define HWT_AUDIOIN_STAT                    HWIO_32_RW
+#define HWN_AUDIOIN_STAT                    AUDIOIN_STAT
+#define HWI_AUDIOIN_STAT                    
+#define BP_AUDIOIN_STAT_ADC_PRESENT         31
+#define BM_AUDIOIN_STAT_ADC_PRESENT         0x80000000
+#define BF_AUDIOIN_STAT_ADC_PRESENT(v)      (((v) & 0x1) << 31)
+#define BFM_AUDIOIN_STAT_ADC_PRESENT(v)     BM_AUDIOIN_STAT_ADC_PRESENT
+#define BF_AUDIOIN_STAT_ADC_PRESENT_V(e)    BF_AUDIOIN_STAT_ADC_PRESENT(BV_AUDIOIN_STAT_ADC_PRESENT__##e)
+#define BFM_AUDIOIN_STAT_ADC_PRESENT_V(v)   BM_AUDIOIN_STAT_ADC_PRESENT
+
+#define HW_AUDIOIN_ADCSRR                       HW(AUDIOIN_ADCSRR)
+#define HWA_AUDIOIN_ADCSRR                      (0x8004c000 + 0x20)
+#define HWT_AUDIOIN_ADCSRR                      HWIO_32_RW
+#define HWN_AUDIOIN_ADCSRR                      AUDIOIN_ADCSRR
+#define HWI_AUDIOIN_ADCSRR                      
+#define HW_AUDIOIN_ADCSRR_SET                   HW(AUDIOIN_ADCSRR_SET)
+#define HWA_AUDIOIN_ADCSRR_SET                  (HWA_AUDIOIN_ADCSRR + 0x4)
+#define HWT_AUDIOIN_ADCSRR_SET                  HWIO_32_WO
+#define HWN_AUDIOIN_ADCSRR_SET                  AUDIOIN_ADCSRR
+#define HWI_AUDIOIN_ADCSRR_SET                  
+#define HW_AUDIOIN_ADCSRR_CLR                   HW(AUDIOIN_ADCSRR_CLR)
+#define HWA_AUDIOIN_ADCSRR_CLR                  (HWA_AUDIOIN_ADCSRR + 0x8)
+#define HWT_AUDIOIN_ADCSRR_CLR                  HWIO_32_WO
+#define HWN_AUDIOIN_ADCSRR_CLR                  AUDIOIN_ADCSRR
+#define HWI_AUDIOIN_ADCSRR_CLR                  
+#define HW_AUDIOIN_ADCSRR_TOG                   HW(AUDIOIN_ADCSRR_TOG)
+#define HWA_AUDIOIN_ADCSRR_TOG                  (HWA_AUDIOIN_ADCSRR + 0xc)
+#define HWT_AUDIOIN_ADCSRR_TOG                  HWIO_32_WO
+#define HWN_AUDIOIN_ADCSRR_TOG                  AUDIOIN_ADCSRR
+#define HWI_AUDIOIN_ADCSRR_TOG                  
+#define BP_AUDIOIN_ADCSRR_OSR                   31
+#define BM_AUDIOIN_ADCSRR_OSR                   0x80000000
+#define BV_AUDIOIN_ADCSRR_OSR__OSR6             0x0
+#define BV_AUDIOIN_ADCSRR_OSR__OSR12            0x1
+#define BF_AUDIOIN_ADCSRR_OSR(v)                (((v) & 0x1) << 31)
+#define BFM_AUDIOIN_ADCSRR_OSR(v)               BM_AUDIOIN_ADCSRR_OSR
+#define BF_AUDIOIN_ADCSRR_OSR_V(e)              BF_AUDIOIN_ADCSRR_OSR(BV_AUDIOIN_ADCSRR_OSR__##e)
+#define BFM_AUDIOIN_ADCSRR_OSR_V(v)             BM_AUDIOIN_ADCSRR_OSR
+#define BP_AUDIOIN_ADCSRR_BASEMULT              28
+#define BM_AUDIOIN_ADCSRR_BASEMULT              0x70000000
+#define BV_AUDIOIN_ADCSRR_BASEMULT__SINGLE_RATE 0x1
+#define BV_AUDIOIN_ADCSRR_BASEMULT__DOUBLE_RATE 0x2
+#define BV_AUDIOIN_ADCSRR_BASEMULT__QUAD_RATE   0x4
+#define BF_AUDIOIN_ADCSRR_BASEMULT(v)           (((v) & 0x7) << 28)
+#define BFM_AUDIOIN_ADCSRR_BASEMULT(v)          BM_AUDIOIN_ADCSRR_BASEMULT
+#define BF_AUDIOIN_ADCSRR_BASEMULT_V(e)         BF_AUDIOIN_ADCSRR_BASEMULT(BV_AUDIOIN_ADCSRR_BASEMULT__##e)
+#define BFM_AUDIOIN_ADCSRR_BASEMULT_V(v)        BM_AUDIOIN_ADCSRR_BASEMULT
+#define BP_AUDIOIN_ADCSRR_SRC_HOLD              24
+#define BM_AUDIOIN_ADCSRR_SRC_HOLD              0x7000000
+#define BF_AUDIOIN_ADCSRR_SRC_HOLD(v)           (((v) & 0x7) << 24)
+#define BFM_AUDIOIN_ADCSRR_SRC_HOLD(v)          BM_AUDIOIN_ADCSRR_SRC_HOLD
+#define BF_AUDIOIN_ADCSRR_SRC_HOLD_V(e)         BF_AUDIOIN_ADCSRR_SRC_HOLD(BV_AUDIOIN_ADCSRR_SRC_HOLD__##e)
+#define BFM_AUDIOIN_ADCSRR_SRC_HOLD_V(v)        BM_AUDIOIN_ADCSRR_SRC_HOLD
+#define BP_AUDIOIN_ADCSRR_SRC_INT               16
+#define BM_AUDIOIN_ADCSRR_SRC_INT               0x1f0000
+#define BF_AUDIOIN_ADCSRR_SRC_INT(v)            (((v) & 0x1f) << 16)
+#define BFM_AUDIOIN_ADCSRR_SRC_INT(v)           BM_AUDIOIN_ADCSRR_SRC_INT
+#define BF_AUDIOIN_ADCSRR_SRC_INT_V(e)          BF_AUDIOIN_ADCSRR_SRC_INT(BV_AUDIOIN_ADCSRR_SRC_INT__##e)
+#define BFM_AUDIOIN_ADCSRR_SRC_INT_V(v)         BM_AUDIOIN_ADCSRR_SRC_INT
+#define BP_AUDIOIN_ADCSRR_SRC_FRAC              0
+#define BM_AUDIOIN_ADCSRR_SRC_FRAC              0x1fff
+#define BF_AUDIOIN_ADCSRR_SRC_FRAC(v)           (((v) & 0x1fff) << 0)
+#define BFM_AUDIOIN_ADCSRR_SRC_FRAC(v)          BM_AUDIOIN_ADCSRR_SRC_FRAC
+#define BF_AUDIOIN_ADCSRR_SRC_FRAC_V(e)         BF_AUDIOIN_ADCSRR_SRC_FRAC(BV_AUDIOIN_ADCSRR_SRC_FRAC__##e)
+#define BFM_AUDIOIN_ADCSRR_SRC_FRAC_V(v)        BM_AUDIOIN_ADCSRR_SRC_FRAC
+
+#define HW_AUDIOIN_ADCVOLUME                            HW(AUDIOIN_ADCVOLUME)
+#define HWA_AUDIOIN_ADCVOLUME                           (0x8004c000 + 0x30)
+#define HWT_AUDIOIN_ADCVOLUME                           HWIO_32_RW
+#define HWN_AUDIOIN_ADCVOLUME                           AUDIOIN_ADCVOLUME
+#define HWI_AUDIOIN_ADCVOLUME                           
+#define HW_AUDIOIN_ADCVOLUME_SET                        HW(AUDIOIN_ADCVOLUME_SET)
+#define HWA_AUDIOIN_ADCVOLUME_SET                       (HWA_AUDIOIN_ADCVOLUME + 0x4)
+#define HWT_AUDIOIN_ADCVOLUME_SET                       HWIO_32_WO
+#define HWN_AUDIOIN_ADCVOLUME_SET                       AUDIOIN_ADCVOLUME
+#define HWI_AUDIOIN_ADCVOLUME_SET                       
+#define HW_AUDIOIN_ADCVOLUME_CLR                        HW(AUDIOIN_ADCVOLUME_CLR)
+#define HWA_AUDIOIN_ADCVOLUME_CLR                       (HWA_AUDIOIN_ADCVOLUME + 0x8)
+#define HWT_AUDIOIN_ADCVOLUME_CLR                       HWIO_32_WO
+#define HWN_AUDIOIN_ADCVOLUME_CLR                       AUDIOIN_ADCVOLUME
+#define HWI_AUDIOIN_ADCVOLUME_CLR                       
+#define HW_AUDIOIN_ADCVOLUME_TOG                        HW(AUDIOIN_ADCVOLUME_TOG)
+#define HWA_AUDIOIN_ADCVOLUME_TOG                       (HWA_AUDIOIN_ADCVOLUME + 0xc)
+#define HWT_AUDIOIN_ADCVOLUME_TOG                       HWIO_32_WO
+#define HWN_AUDIOIN_ADCVOLUME_TOG                       AUDIOIN_ADCVOLUME
+#define HWI_AUDIOIN_ADCVOLUME_TOG                       
+#define BP_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_LEFT         28
+#define BM_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_LEFT         0x10000000
+#define BF_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_LEFT(v)      (((v) & 0x1) << 28)
+#define BFM_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_LEFT(v)     BM_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_LEFT
+#define BF_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_LEFT_V(e)    BF_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_LEFT(BV_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_LEFT__##e)
+#define BFM_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_LEFT_V(v)   BM_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_LEFT
+#define BP_AUDIOIN_ADCVOLUME_EN_ZCD                     25
+#define BM_AUDIOIN_ADCVOLUME_EN_ZCD                     0x2000000
+#define BF_AUDIOIN_ADCVOLUME_EN_ZCD(v)                  (((v) & 0x1) << 25)
+#define BFM_AUDIOIN_ADCVOLUME_EN_ZCD(v)                 BM_AUDIOIN_ADCVOLUME_EN_ZCD
+#define BF_AUDIOIN_ADCVOLUME_EN_ZCD_V(e)                BF_AUDIOIN_ADCVOLUME_EN_ZCD(BV_AUDIOIN_ADCVOLUME_EN_ZCD__##e)
+#define BFM_AUDIOIN_ADCVOLUME_EN_ZCD_V(v)               BM_AUDIOIN_ADCVOLUME_EN_ZCD
+#define BP_AUDIOIN_ADCVOLUME_VOLUME_LEFT                16
+#define BM_AUDIOIN_ADCVOLUME_VOLUME_LEFT                0xff0000
+#define BF_AUDIOIN_ADCVOLUME_VOLUME_LEFT(v)             (((v) & 0xff) << 16)
+#define BFM_AUDIOIN_ADCVOLUME_VOLUME_LEFT(v)            BM_AUDIOIN_ADCVOLUME_VOLUME_LEFT
+#define BF_AUDIOIN_ADCVOLUME_VOLUME_LEFT_V(e)           BF_AUDIOIN_ADCVOLUME_VOLUME_LEFT(BV_AUDIOIN_ADCVOLUME_VOLUME_LEFT__##e)
+#define BFM_AUDIOIN_ADCVOLUME_VOLUME_LEFT_V(v)          BM_AUDIOIN_ADCVOLUME_VOLUME_LEFT
+#define BP_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_RIGHT        12
+#define BM_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_RIGHT        0x1000
+#define BF_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_RIGHT(v)     (((v) & 0x1) << 12)
+#define BFM_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_RIGHT(v)    BM_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_RIGHT
+#define BF_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_RIGHT_V(e)   BF_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_RIGHT(BV_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_RIGHT__##e)
+#define BFM_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_RIGHT_V(v)  BM_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_RIGHT
+#define BP_AUDIOIN_ADCVOLUME_VOLUME_RIGHT               0
+#define BM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT               0xff
+#define BF_AUDIOIN_ADCVOLUME_VOLUME_RIGHT(v)            (((v) & 0xff) << 0)
+#define BFM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT(v)           BM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT
+#define BF_AUDIOIN_ADCVOLUME_VOLUME_RIGHT_V(e)          BF_AUDIOIN_ADCVOLUME_VOLUME_RIGHT(BV_AUDIOIN_ADCVOLUME_VOLUME_RIGHT__##e)
+#define BFM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT_V(v)         BM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT
+
+#define HW_AUDIOIN_ADCDEBUG                                         HW(AUDIOIN_ADCDEBUG)
+#define HWA_AUDIOIN_ADCDEBUG                                        (0x8004c000 + 0x40)
+#define HWT_AUDIOIN_ADCDEBUG                                        HWIO_32_RW
+#define HWN_AUDIOIN_ADCDEBUG                                        AUDIOIN_ADCDEBUG
+#define HWI_AUDIOIN_ADCDEBUG                                        
+#define HW_AUDIOIN_ADCDEBUG_SET                                     HW(AUDIOIN_ADCDEBUG_SET)
+#define HWA_AUDIOIN_ADCDEBUG_SET                                    (HWA_AUDIOIN_ADCDEBUG + 0x4)
+#define HWT_AUDIOIN_ADCDEBUG_SET                                    HWIO_32_WO
+#define HWN_AUDIOIN_ADCDEBUG_SET                                    AUDIOIN_ADCDEBUG
+#define HWI_AUDIOIN_ADCDEBUG_SET                                    
+#define HW_AUDIOIN_ADCDEBUG_CLR                                     HW(AUDIOIN_ADCDEBUG_CLR)
+#define HWA_AUDIOIN_ADCDEBUG_CLR                                    (HWA_AUDIOIN_ADCDEBUG + 0x8)
+#define HWT_AUDIOIN_ADCDEBUG_CLR                                    HWIO_32_WO
+#define HWN_AUDIOIN_ADCDEBUG_CLR                                    AUDIOIN_ADCDEBUG
+#define HWI_AUDIOIN_ADCDEBUG_CLR                                    
+#define HW_AUDIOIN_ADCDEBUG_TOG                                     HW(AUDIOIN_ADCDEBUG_TOG)
+#define HWA_AUDIOIN_ADCDEBUG_TOG                                    (HWA_AUDIOIN_ADCDEBUG + 0xc)
+#define HWT_AUDIOIN_ADCDEBUG_TOG                                    HWIO_32_WO
+#define HWN_AUDIOIN_ADCDEBUG_TOG                                    AUDIOIN_ADCDEBUG
+#define HWI_AUDIOIN_ADCDEBUG_TOG                                    
+#define BP_AUDIOIN_ADCDEBUG_ENABLE_ADCDMA                           31
+#define BM_AUDIOIN_ADCDEBUG_ENABLE_ADCDMA                           0x80000000
+#define BF_AUDIOIN_ADCDEBUG_ENABLE_ADCDMA(v)                        (((v) & 0x1) << 31)
+#define BFM_AUDIOIN_ADCDEBUG_ENABLE_ADCDMA(v)                       BM_AUDIOIN_ADCDEBUG_ENABLE_ADCDMA
+#define BF_AUDIOIN_ADCDEBUG_ENABLE_ADCDMA_V(e)                      BF_AUDIOIN_ADCDEBUG_ENABLE_ADCDMA(BV_AUDIOIN_ADCDEBUG_ENABLE_ADCDMA__##e)
+#define BFM_AUDIOIN_ADCDEBUG_ENABLE_ADCDMA_V(v)                     BM_AUDIOIN_ADCDEBUG_ENABLE_ADCDMA
+#define BP_AUDIOIN_ADCDEBUG_ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS        3
+#define BM_AUDIOIN_ADCDEBUG_ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS        0x8
+#define BF_AUDIOIN_ADCDEBUG_ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS(v)     (((v) & 0x1) << 3)
+#define BFM_AUDIOIN_ADCDEBUG_ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS(v)    BM_AUDIOIN_ADCDEBUG_ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS
+#define BF_AUDIOIN_ADCDEBUG_ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS_V(e)   BF_AUDIOIN_ADCDEBUG_ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS(BV_AUDIOIN_ADCDEBUG_ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS__##e)
+#define BFM_AUDIOIN_ADCDEBUG_ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS_V(v)  BM_AUDIOIN_ADCDEBUG_ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS
+#define BP_AUDIOIN_ADCDEBUG_SET_INTERRUPT3_HAND_SHAKE               2
+#define BM_AUDIOIN_ADCDEBUG_SET_INTERRUPT3_HAND_SHAKE               0x4
+#define BF_AUDIOIN_ADCDEBUG_SET_INTERRUPT3_HAND_SHAKE(v)            (((v) & 0x1) << 2)
+#define BFM_AUDIOIN_ADCDEBUG_SET_INTERRUPT3_HAND_SHAKE(v)           BM_AUDIOIN_ADCDEBUG_SET_INTERRUPT3_HAND_SHAKE
+#define BF_AUDIOIN_ADCDEBUG_SET_INTERRUPT3_HAND_SHAKE_V(e)          BF_AUDIOIN_ADCDEBUG_SET_INTERRUPT3_HAND_SHAKE(BV_AUDIOIN_ADCDEBUG_SET_INTERRUPT3_HAND_SHAKE__##e)
+#define BFM_AUDIOIN_ADCDEBUG_SET_INTERRUPT3_HAND_SHAKE_V(v)         BM_AUDIOIN_ADCDEBUG_SET_INTERRUPT3_HAND_SHAKE
+#define BP_AUDIOIN_ADCDEBUG_DMA_PREQ                                1
+#define BM_AUDIOIN_ADCDEBUG_DMA_PREQ                                0x2
+#define BF_AUDIOIN_ADCDEBUG_DMA_PREQ(v)                             (((v) & 0x1) << 1)
+#define BFM_AUDIOIN_ADCDEBUG_DMA_PREQ(v)                            BM_AUDIOIN_ADCDEBUG_DMA_PREQ
+#define BF_AUDIOIN_ADCDEBUG_DMA_PREQ_V(e)                           BF_AUDIOIN_ADCDEBUG_DMA_PREQ(BV_AUDIOIN_ADCDEBUG_DMA_PREQ__##e)
+#define BFM_AUDIOIN_ADCDEBUG_DMA_PREQ_V(v)                          BM_AUDIOIN_ADCDEBUG_DMA_PREQ
+#define BP_AUDIOIN_ADCDEBUG_FIFO_STATUS                             0
+#define BM_AUDIOIN_ADCDEBUG_FIFO_STATUS                             0x1
+#define BF_AUDIOIN_ADCDEBUG_FIFO_STATUS(v)                          (((v) & 0x1) << 0)
+#define BFM_AUDIOIN_ADCDEBUG_FIFO_STATUS(v)                         BM_AUDIOIN_ADCDEBUG_FIFO_STATUS
+#define BF_AUDIOIN_ADCDEBUG_FIFO_STATUS_V(e)                        BF_AUDIOIN_ADCDEBUG_FIFO_STATUS(BV_AUDIOIN_ADCDEBUG_FIFO_STATUS__##e)
+#define BFM_AUDIOIN_ADCDEBUG_FIFO_STATUS_V(v)                       BM_AUDIOIN_ADCDEBUG_FIFO_STATUS
+
+#define HW_AUDIOIN_ADCVOL                               HW(AUDIOIN_ADCVOL)
+#define HWA_AUDIOIN_ADCVOL                              (0x8004c000 + 0x50)
+#define HWT_AUDIOIN_ADCVOL                              HWIO_32_RW
+#define HWN_AUDIOIN_ADCVOL                              AUDIOIN_ADCVOL
+#define HWI_AUDIOIN_ADCVOL                              
+#define HW_AUDIOIN_ADCVOL_SET                           HW(AUDIOIN_ADCVOL_SET)
+#define HWA_AUDIOIN_ADCVOL_SET                          (HWA_AUDIOIN_ADCVOL + 0x4)
+#define HWT_AUDIOIN_ADCVOL_SET                          HWIO_32_WO
+#define HWN_AUDIOIN_ADCVOL_SET                          AUDIOIN_ADCVOL
+#define HWI_AUDIOIN_ADCVOL_SET                          
+#define HW_AUDIOIN_ADCVOL_CLR                           HW(AUDIOIN_ADCVOL_CLR)
+#define HWA_AUDIOIN_ADCVOL_CLR                          (HWA_AUDIOIN_ADCVOL + 0x8)
+#define HWT_AUDIOIN_ADCVOL_CLR                          HWIO_32_WO
+#define HWN_AUDIOIN_ADCVOL_CLR                          AUDIOIN_ADCVOL
+#define HWI_AUDIOIN_ADCVOL_CLR                          
+#define HW_AUDIOIN_ADCVOL_TOG                           HW(AUDIOIN_ADCVOL_TOG)
+#define HWA_AUDIOIN_ADCVOL_TOG                          (HWA_AUDIOIN_ADCVOL + 0xc)
+#define HWT_AUDIOIN_ADCVOL_TOG                          HWIO_32_WO
+#define HWN_AUDIOIN_ADCVOL_TOG                          AUDIOIN_ADCVOL
+#define HWI_AUDIOIN_ADCVOL_TOG                          
+#define BP_AUDIOIN_ADCVOL_VOLUME_UPDATE_PENDING         28
+#define BM_AUDIOIN_ADCVOL_VOLUME_UPDATE_PENDING         0x10000000
+#define BF_AUDIOIN_ADCVOL_VOLUME_UPDATE_PENDING(v)      (((v) & 0x1) << 28)
+#define BFM_AUDIOIN_ADCVOL_VOLUME_UPDATE_PENDING(v)     BM_AUDIOIN_ADCVOL_VOLUME_UPDATE_PENDING
+#define BF_AUDIOIN_ADCVOL_VOLUME_UPDATE_PENDING_V(e)    BF_AUDIOIN_ADCVOL_VOLUME_UPDATE_PENDING(BV_AUDIOIN_ADCVOL_VOLUME_UPDATE_PENDING__##e)
+#define BFM_AUDIOIN_ADCVOL_VOLUME_UPDATE_PENDING_V(v)   BM_AUDIOIN_ADCVOL_VOLUME_UPDATE_PENDING
+#define BP_AUDIOIN_ADCVOL_EN_ADC_ZCD                    25
+#define BM_AUDIOIN_ADCVOL_EN_ADC_ZCD                    0x2000000
+#define BF_AUDIOIN_ADCVOL_EN_ADC_ZCD(v)                 (((v) & 0x1) << 25)
+#define BFM_AUDIOIN_ADCVOL_EN_ADC_ZCD(v)                BM_AUDIOIN_ADCVOL_EN_ADC_ZCD
+#define BF_AUDIOIN_ADCVOL_EN_ADC_ZCD_V(e)               BF_AUDIOIN_ADCVOL_EN_ADC_ZCD(BV_AUDIOIN_ADCVOL_EN_ADC_ZCD__##e)
+#define BFM_AUDIOIN_ADCVOL_EN_ADC_ZCD_V(v)              BM_AUDIOIN_ADCVOL_EN_ADC_ZCD
+#define BP_AUDIOIN_ADCVOL_MUTE                          24
+#define BM_AUDIOIN_ADCVOL_MUTE                          0x1000000
+#define BF_AUDIOIN_ADCVOL_MUTE(v)                       (((v) & 0x1) << 24)
+#define BFM_AUDIOIN_ADCVOL_MUTE(v)                      BM_AUDIOIN_ADCVOL_MUTE
+#define BF_AUDIOIN_ADCVOL_MUTE_V(e)                     BF_AUDIOIN_ADCVOL_MUTE(BV_AUDIOIN_ADCVOL_MUTE__##e)
+#define BFM_AUDIOIN_ADCVOL_MUTE_V(v)                    BM_AUDIOIN_ADCVOL_MUTE
+#define BP_AUDIOIN_ADCVOL_SELECT_LEFT                   12
+#define BM_AUDIOIN_ADCVOL_SELECT_LEFT                   0x3000
+#define BF_AUDIOIN_ADCVOL_SELECT_LEFT(v)                (((v) & 0x3) << 12)
+#define BFM_AUDIOIN_ADCVOL_SELECT_LEFT(v)               BM_AUDIOIN_ADCVOL_SELECT_LEFT
+#define BF_AUDIOIN_ADCVOL_SELECT_LEFT_V(e)              BF_AUDIOIN_ADCVOL_SELECT_LEFT(BV_AUDIOIN_ADCVOL_SELECT_LEFT__##e)
+#define BFM_AUDIOIN_ADCVOL_SELECT_LEFT_V(v)             BM_AUDIOIN_ADCVOL_SELECT_LEFT
+#define BP_AUDIOIN_ADCVOL_GAIN_LEFT                     8
+#define BM_AUDIOIN_ADCVOL_GAIN_LEFT                     0xf00
+#define BF_AUDIOIN_ADCVOL_GAIN_LEFT(v)                  (((v) & 0xf) << 8)
+#define BFM_AUDIOIN_ADCVOL_GAIN_LEFT(v)                 BM_AUDIOIN_ADCVOL_GAIN_LEFT
+#define BF_AUDIOIN_ADCVOL_GAIN_LEFT_V(e)                BF_AUDIOIN_ADCVOL_GAIN_LEFT(BV_AUDIOIN_ADCVOL_GAIN_LEFT__##e)
+#define BFM_AUDIOIN_ADCVOL_GAIN_LEFT_V(v)               BM_AUDIOIN_ADCVOL_GAIN_LEFT
+#define BP_AUDIOIN_ADCVOL_SELECT_RIGHT                  4
+#define BM_AUDIOIN_ADCVOL_SELECT_RIGHT                  0x30
+#define BF_AUDIOIN_ADCVOL_SELECT_RIGHT(v)               (((v) & 0x3) << 4)
+#define BFM_AUDIOIN_ADCVOL_SELECT_RIGHT(v)              BM_AUDIOIN_ADCVOL_SELECT_RIGHT
+#define BF_AUDIOIN_ADCVOL_SELECT_RIGHT_V(e)             BF_AUDIOIN_ADCVOL_SELECT_RIGHT(BV_AUDIOIN_ADCVOL_SELECT_RIGHT__##e)
+#define BFM_AUDIOIN_ADCVOL_SELECT_RIGHT_V(v)            BM_AUDIOIN_ADCVOL_SELECT_RIGHT
+#define BP_AUDIOIN_ADCVOL_GAIN_RIGHT                    0
+#define BM_AUDIOIN_ADCVOL_GAIN_RIGHT                    0xf
+#define BF_AUDIOIN_ADCVOL_GAIN_RIGHT(v)                 (((v) & 0xf) << 0)
+#define BFM_AUDIOIN_ADCVOL_GAIN_RIGHT(v)                BM_AUDIOIN_ADCVOL_GAIN_RIGHT
+#define BF_AUDIOIN_ADCVOL_GAIN_RIGHT_V(e)               BF_AUDIOIN_ADCVOL_GAIN_RIGHT(BV_AUDIOIN_ADCVOL_GAIN_RIGHT__##e)
+#define BFM_AUDIOIN_ADCVOL_GAIN_RIGHT_V(v)              BM_AUDIOIN_ADCVOL_GAIN_RIGHT
+
+#define HW_AUDIOIN_MICLINE                      HW(AUDIOIN_MICLINE)
+#define HWA_AUDIOIN_MICLINE                     (0x8004c000 + 0x60)
+#define HWT_AUDIOIN_MICLINE                     HWIO_32_RW
+#define HWN_AUDIOIN_MICLINE                     AUDIOIN_MICLINE
+#define HWI_AUDIOIN_MICLINE                     
+#define HW_AUDIOIN_MICLINE_SET                  HW(AUDIOIN_MICLINE_SET)
+#define HWA_AUDIOIN_MICLINE_SET                 (HWA_AUDIOIN_MICLINE + 0x4)
+#define HWT_AUDIOIN_MICLINE_SET                 HWIO_32_WO
+#define HWN_AUDIOIN_MICLINE_SET                 AUDIOIN_MICLINE
+#define HWI_AUDIOIN_MICLINE_SET                 
+#define HW_AUDIOIN_MICLINE_CLR                  HW(AUDIOIN_MICLINE_CLR)
+#define HWA_AUDIOIN_MICLINE_CLR                 (HWA_AUDIOIN_MICLINE + 0x8)
+#define HWT_AUDIOIN_MICLINE_CLR                 HWIO_32_WO
+#define HWN_AUDIOIN_MICLINE_CLR                 AUDIOIN_MICLINE
+#define HWI_AUDIOIN_MICLINE_CLR                 
+#define HW_AUDIOIN_MICLINE_TOG                  HW(AUDIOIN_MICLINE_TOG)
+#define HWA_AUDIOIN_MICLINE_TOG                 (HWA_AUDIOIN_MICLINE + 0xc)
+#define HWT_AUDIOIN_MICLINE_TOG                 HWIO_32_WO
+#define HWN_AUDIOIN_MICLINE_TOG                 AUDIOIN_MICLINE
+#define HWI_AUDIOIN_MICLINE_TOG                 
+#define BP_AUDIOIN_MICLINE_DIVIDE_LINE1         29
+#define BM_AUDIOIN_MICLINE_DIVIDE_LINE1         0x20000000
+#define BF_AUDIOIN_MICLINE_DIVIDE_LINE1(v)      (((v) & 0x1) << 29)
+#define BFM_AUDIOIN_MICLINE_DIVIDE_LINE1(v)     BM_AUDIOIN_MICLINE_DIVIDE_LINE1
+#define BF_AUDIOIN_MICLINE_DIVIDE_LINE1_V(e)    BF_AUDIOIN_MICLINE_DIVIDE_LINE1(BV_AUDIOIN_MICLINE_DIVIDE_LINE1__##e)
+#define BFM_AUDIOIN_MICLINE_DIVIDE_LINE1_V(v)   BM_AUDIOIN_MICLINE_DIVIDE_LINE1
+#define BP_AUDIOIN_MICLINE_DIVIDE_LINE2         28
+#define BM_AUDIOIN_MICLINE_DIVIDE_LINE2         0x10000000
+#define BF_AUDIOIN_MICLINE_DIVIDE_LINE2(v)      (((v) & 0x1) << 28)
+#define BFM_AUDIOIN_MICLINE_DIVIDE_LINE2(v)     BM_AUDIOIN_MICLINE_DIVIDE_LINE2
+#define BF_AUDIOIN_MICLINE_DIVIDE_LINE2_V(e)    BF_AUDIOIN_MICLINE_DIVIDE_LINE2(BV_AUDIOIN_MICLINE_DIVIDE_LINE2__##e)
+#define BFM_AUDIOIN_MICLINE_DIVIDE_LINE2_V(v)   BM_AUDIOIN_MICLINE_DIVIDE_LINE2
+#define BP_AUDIOIN_MICLINE_MIC_SELECT           24
+#define BM_AUDIOIN_MICLINE_MIC_SELECT           0x1000000
+#define BF_AUDIOIN_MICLINE_MIC_SELECT(v)        (((v) & 0x1) << 24)
+#define BFM_AUDIOIN_MICLINE_MIC_SELECT(v)       BM_AUDIOIN_MICLINE_MIC_SELECT
+#define BF_AUDIOIN_MICLINE_MIC_SELECT_V(e)      BF_AUDIOIN_MICLINE_MIC_SELECT(BV_AUDIOIN_MICLINE_MIC_SELECT__##e)
+#define BFM_AUDIOIN_MICLINE_MIC_SELECT_V(v)     BM_AUDIOIN_MICLINE_MIC_SELECT
+#define BP_AUDIOIN_MICLINE_MIC_RESISTOR         20
+#define BM_AUDIOIN_MICLINE_MIC_RESISTOR         0x300000
+#define BV_AUDIOIN_MICLINE_MIC_RESISTOR__Off    0x0
+#define BV_AUDIOIN_MICLINE_MIC_RESISTOR__2KOhm  0x1
+#define BV_AUDIOIN_MICLINE_MIC_RESISTOR__4KOhm  0x2
+#define BV_AUDIOIN_MICLINE_MIC_RESISTOR__8KOhm  0x3
+#define BF_AUDIOIN_MICLINE_MIC_RESISTOR(v)      (((v) & 0x3) << 20)
+#define BFM_AUDIOIN_MICLINE_MIC_RESISTOR(v)     BM_AUDIOIN_MICLINE_MIC_RESISTOR
+#define BF_AUDIOIN_MICLINE_MIC_RESISTOR_V(e)    BF_AUDIOIN_MICLINE_MIC_RESISTOR(BV_AUDIOIN_MICLINE_MIC_RESISTOR__##e)
+#define BFM_AUDIOIN_MICLINE_MIC_RESISTOR_V(v)   BM_AUDIOIN_MICLINE_MIC_RESISTOR
+#define BP_AUDIOIN_MICLINE_MIC_BIAS             16
+#define BM_AUDIOIN_MICLINE_MIC_BIAS             0x70000
+#define BF_AUDIOIN_MICLINE_MIC_BIAS(v)          (((v) & 0x7) << 16)
+#define BFM_AUDIOIN_MICLINE_MIC_BIAS(v)         BM_AUDIOIN_MICLINE_MIC_BIAS
+#define BF_AUDIOIN_MICLINE_MIC_BIAS_V(e)        BF_AUDIOIN_MICLINE_MIC_BIAS(BV_AUDIOIN_MICLINE_MIC_BIAS__##e)
+#define BFM_AUDIOIN_MICLINE_MIC_BIAS_V(v)       BM_AUDIOIN_MICLINE_MIC_BIAS
+#define BP_AUDIOIN_MICLINE_MIC_CHOPCLK          4
+#define BM_AUDIOIN_MICLINE_MIC_CHOPCLK          0x30
+#define BF_AUDIOIN_MICLINE_MIC_CHOPCLK(v)       (((v) & 0x3) << 4)
+#define BFM_AUDIOIN_MICLINE_MIC_CHOPCLK(v)      BM_AUDIOIN_MICLINE_MIC_CHOPCLK
+#define BF_AUDIOIN_MICLINE_MIC_CHOPCLK_V(e)     BF_AUDIOIN_MICLINE_MIC_CHOPCLK(BV_AUDIOIN_MICLINE_MIC_CHOPCLK__##e)
+#define BFM_AUDIOIN_MICLINE_MIC_CHOPCLK_V(v)    BM_AUDIOIN_MICLINE_MIC_CHOPCLK
+#define BP_AUDIOIN_MICLINE_MIC_GAIN             0
+#define BM_AUDIOIN_MICLINE_MIC_GAIN             0x3
+#define BV_AUDIOIN_MICLINE_MIC_GAIN__0dB        0x0
+#define BV_AUDIOIN_MICLINE_MIC_GAIN__20dB       0x1
+#define BV_AUDIOIN_MICLINE_MIC_GAIN__30dB       0x2
+#define BV_AUDIOIN_MICLINE_MIC_GAIN__40dB       0x3
+#define BF_AUDIOIN_MICLINE_MIC_GAIN(v)          (((v) & 0x3) << 0)
+#define BFM_AUDIOIN_MICLINE_MIC_GAIN(v)         BM_AUDIOIN_MICLINE_MIC_GAIN
+#define BF_AUDIOIN_MICLINE_MIC_GAIN_V(e)        BF_AUDIOIN_MICLINE_MIC_GAIN(BV_AUDIOIN_MICLINE_MIC_GAIN__##e)
+#define BFM_AUDIOIN_MICLINE_MIC_GAIN_V(v)       BM_AUDIOIN_MICLINE_MIC_GAIN
+
+#define HW_AUDIOIN_ANACLKCTRL                       HW(AUDIOIN_ANACLKCTRL)
+#define HWA_AUDIOIN_ANACLKCTRL                      (0x8004c000 + 0x70)
+#define HWT_AUDIOIN_ANACLKCTRL                      HWIO_32_RW
+#define HWN_AUDIOIN_ANACLKCTRL                      AUDIOIN_ANACLKCTRL
+#define HWI_AUDIOIN_ANACLKCTRL                      
+#define HW_AUDIOIN_ANACLKCTRL_SET                   HW(AUDIOIN_ANACLKCTRL_SET)
+#define HWA_AUDIOIN_ANACLKCTRL_SET                  (HWA_AUDIOIN_ANACLKCTRL + 0x4)
+#define HWT_AUDIOIN_ANACLKCTRL_SET                  HWIO_32_WO
+#define HWN_AUDIOIN_ANACLKCTRL_SET                  AUDIOIN_ANACLKCTRL
+#define HWI_AUDIOIN_ANACLKCTRL_SET                  
+#define HW_AUDIOIN_ANACLKCTRL_CLR                   HW(AUDIOIN_ANACLKCTRL_CLR)
+#define HWA_AUDIOIN_ANACLKCTRL_CLR                  (HWA_AUDIOIN_ANACLKCTRL + 0x8)
+#define HWT_AUDIOIN_ANACLKCTRL_CLR                  HWIO_32_WO
+#define HWN_AUDIOIN_ANACLKCTRL_CLR                  AUDIOIN_ANACLKCTRL
+#define HWI_AUDIOIN_ANACLKCTRL_CLR                  
+#define HW_AUDIOIN_ANACLKCTRL_TOG                   HW(AUDIOIN_ANACLKCTRL_TOG)
+#define HWA_AUDIOIN_ANACLKCTRL_TOG                  (HWA_AUDIOIN_ANACLKCTRL + 0xc)
+#define HWT_AUDIOIN_ANACLKCTRL_TOG                  HWIO_32_WO
+#define HWN_AUDIOIN_ANACLKCTRL_TOG                  AUDIOIN_ANACLKCTRL
+#define HWI_AUDIOIN_ANACLKCTRL_TOG                  
+#define BP_AUDIOIN_ANACLKCTRL_CLKGATE               31
+#define BM_AUDIOIN_ANACLKCTRL_CLKGATE               0x80000000
+#define BF_AUDIOIN_ANACLKCTRL_CLKGATE(v)            (((v) & 0x1) << 31)
+#define BFM_AUDIOIN_ANACLKCTRL_CLKGATE(v)           BM_AUDIOIN_ANACLKCTRL_CLKGATE
+#define BF_AUDIOIN_ANACLKCTRL_CLKGATE_V(e)          BF_AUDIOIN_ANACLKCTRL_CLKGATE(BV_AUDIOIN_ANACLKCTRL_CLKGATE__##e)
+#define BFM_AUDIOIN_ANACLKCTRL_CLKGATE_V(v)         BM_AUDIOIN_ANACLKCTRL_CLKGATE
+#define BP_AUDIOIN_ANACLKCTRL_DITHER_OFF            6
+#define BM_AUDIOIN_ANACLKCTRL_DITHER_OFF            0x40
+#define BF_AUDIOIN_ANACLKCTRL_DITHER_OFF(v)         (((v) & 0x1) << 6)
+#define BFM_AUDIOIN_ANACLKCTRL_DITHER_OFF(v)        BM_AUDIOIN_ANACLKCTRL_DITHER_OFF
+#define BF_AUDIOIN_ANACLKCTRL_DITHER_OFF_V(e)       BF_AUDIOIN_ANACLKCTRL_DITHER_OFF(BV_AUDIOIN_ANACLKCTRL_DITHER_OFF__##e)
+#define BFM_AUDIOIN_ANACLKCTRL_DITHER_OFF_V(v)      BM_AUDIOIN_ANACLKCTRL_DITHER_OFF
+#define BP_AUDIOIN_ANACLKCTRL_SLOW_DITHER           5
+#define BM_AUDIOIN_ANACLKCTRL_SLOW_DITHER           0x20
+#define BF_AUDIOIN_ANACLKCTRL_SLOW_DITHER(v)        (((v) & 0x1) << 5)
+#define BFM_AUDIOIN_ANACLKCTRL_SLOW_DITHER(v)       BM_AUDIOIN_ANACLKCTRL_SLOW_DITHER
+#define BF_AUDIOIN_ANACLKCTRL_SLOW_DITHER_V(e)      BF_AUDIOIN_ANACLKCTRL_SLOW_DITHER(BV_AUDIOIN_ANACLKCTRL_SLOW_DITHER__##e)
+#define BFM_AUDIOIN_ANACLKCTRL_SLOW_DITHER_V(v)     BM_AUDIOIN_ANACLKCTRL_SLOW_DITHER
+#define BP_AUDIOIN_ANACLKCTRL_INVERT_ADCCLK         4
+#define BM_AUDIOIN_ANACLKCTRL_INVERT_ADCCLK         0x10
+#define BF_AUDIOIN_ANACLKCTRL_INVERT_ADCCLK(v)      (((v) & 0x1) << 4)
+#define BFM_AUDIOIN_ANACLKCTRL_INVERT_ADCCLK(v)     BM_AUDIOIN_ANACLKCTRL_INVERT_ADCCLK
+#define BF_AUDIOIN_ANACLKCTRL_INVERT_ADCCLK_V(e)    BF_AUDIOIN_ANACLKCTRL_INVERT_ADCCLK(BV_AUDIOIN_ANACLKCTRL_INVERT_ADCCLK__##e)
+#define BFM_AUDIOIN_ANACLKCTRL_INVERT_ADCCLK_V(v)   BM_AUDIOIN_ANACLKCTRL_INVERT_ADCCLK
+#define BP_AUDIOIN_ANACLKCTRL_ADCDIV                0
+#define BM_AUDIOIN_ANACLKCTRL_ADCDIV                0x7
+#define BF_AUDIOIN_ANACLKCTRL_ADCDIV(v)             (((v) & 0x7) << 0)
+#define BFM_AUDIOIN_ANACLKCTRL_ADCDIV(v)            BM_AUDIOIN_ANACLKCTRL_ADCDIV
+#define BF_AUDIOIN_ANACLKCTRL_ADCDIV_V(e)           BF_AUDIOIN_ANACLKCTRL_ADCDIV(BV_AUDIOIN_ANACLKCTRL_ADCDIV__##e)
+#define BFM_AUDIOIN_ANACLKCTRL_ADCDIV_V(v)          BM_AUDIOIN_ANACLKCTRL_ADCDIV
+
+#define HW_AUDIOIN_DATA             HW(AUDIOIN_DATA)
+#define HWA_AUDIOIN_DATA            (0x8004c000 + 0x80)
+#define HWT_AUDIOIN_DATA            HWIO_32_RW
+#define HWN_AUDIOIN_DATA            AUDIOIN_DATA
+#define HWI_AUDIOIN_DATA            
+#define BP_AUDIOIN_DATA_HIGH        16
+#define BM_AUDIOIN_DATA_HIGH        0xffff0000
+#define BF_AUDIOIN_DATA_HIGH(v)     (((v) & 0xffff) << 16)
+#define BFM_AUDIOIN_DATA_HIGH(v)    BM_AUDIOIN_DATA_HIGH
+#define BF_AUDIOIN_DATA_HIGH_V(e)   BF_AUDIOIN_DATA_HIGH(BV_AUDIOIN_DATA_HIGH__##e)
+#define BFM_AUDIOIN_DATA_HIGH_V(v)  BM_AUDIOIN_DATA_HIGH
+#define BP_AUDIOIN_DATA_LOW         0
+#define BM_AUDIOIN_DATA_LOW         0xffff
+#define BF_AUDIOIN_DATA_LOW(v)      (((v) & 0xffff) << 0)
+#define BFM_AUDIOIN_DATA_LOW(v)     BM_AUDIOIN_DATA_LOW
+#define BF_AUDIOIN_DATA_LOW_V(e)    BF_AUDIOIN_DATA_LOW(BV_AUDIOIN_DATA_LOW__##e)
+#define BFM_AUDIOIN_DATA_LOW_V(v)   BM_AUDIOIN_DATA_LOW
+
+#endif /* __HEADERGEN_STMP3700_AUDIOIN_H__*/
diff --git a/firmware/target/arm/imx233/regs/stmp3700/audioout.h b/firmware/target/arm/imx233/regs/stmp3700/audioout.h
new file mode 100644
index 0000000000..c8585562da
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3700/audioout.h
@@ -0,0 +1,953 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * stmp3700 version: 2.4.0
+ * stmp3700 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_STMP3700_AUDIOOUT_H__
+#define __HEADERGEN_STMP3700_AUDIOOUT_H__
+
+#define HW_AUDIOOUT_CTRL                            HW(AUDIOOUT_CTRL)
+#define HWA_AUDIOOUT_CTRL                           (0x80048000 + 0x0)
+#define HWT_AUDIOOUT_CTRL                           HWIO_32_RW
+#define HWN_AUDIOOUT_CTRL                           AUDIOOUT_CTRL
+#define HWI_AUDIOOUT_CTRL                           
+#define HW_AUDIOOUT_CTRL_SET                        HW(AUDIOOUT_CTRL_SET)
+#define HWA_AUDIOOUT_CTRL_SET                       (HWA_AUDIOOUT_CTRL + 0x4)
+#define HWT_AUDIOOUT_CTRL_SET                       HWIO_32_WO
+#define HWN_AUDIOOUT_CTRL_SET                       AUDIOOUT_CTRL
+#define HWI_AUDIOOUT_CTRL_SET                       
+#define HW_AUDIOOUT_CTRL_CLR                        HW(AUDIOOUT_CTRL_CLR)
+#define HWA_AUDIOOUT_CTRL_CLR                       (HWA_AUDIOOUT_CTRL + 0x8)
+#define HWT_AUDIOOUT_CTRL_CLR                       HWIO_32_WO
+#define HWN_AUDIOOUT_CTRL_CLR                       AUDIOOUT_CTRL
+#define HWI_AUDIOOUT_CTRL_CLR                       
+#define HW_AUDIOOUT_CTRL_TOG                        HW(AUDIOOUT_CTRL_TOG)
+#define HWA_AUDIOOUT_CTRL_TOG                       (HWA_AUDIOOUT_CTRL + 0xc)
+#define HWT_AUDIOOUT_CTRL_TOG                       HWIO_32_WO
+#define HWN_AUDIOOUT_CTRL_TOG                       AUDIOOUT_CTRL
+#define HWI_AUDIOOUT_CTRL_TOG                       
+#define BP_AUDIOOUT_CTRL_SFTRST                     31
+#define BM_AUDIOOUT_CTRL_SFTRST                     0x80000000
+#define BF_AUDIOOUT_CTRL_SFTRST(v)                  (((v) & 0x1) << 31)
+#define BFM_AUDIOOUT_CTRL_SFTRST(v)                 BM_AUDIOOUT_CTRL_SFTRST
+#define BF_AUDIOOUT_CTRL_SFTRST_V(e)                BF_AUDIOOUT_CTRL_SFTRST(BV_AUDIOOUT_CTRL_SFTRST__##e)
+#define BFM_AUDIOOUT_CTRL_SFTRST_V(v)               BM_AUDIOOUT_CTRL_SFTRST
+#define BP_AUDIOOUT_CTRL_CLKGATE                    30
+#define BM_AUDIOOUT_CTRL_CLKGATE                    0x40000000
+#define BF_AUDIOOUT_CTRL_CLKGATE(v)                 (((v) & 0x1) << 30)
+#define BFM_AUDIOOUT_CTRL_CLKGATE(v)                BM_AUDIOOUT_CTRL_CLKGATE
+#define BF_AUDIOOUT_CTRL_CLKGATE_V(e)               BF_AUDIOOUT_CTRL_CLKGATE(BV_AUDIOOUT_CTRL_CLKGATE__##e)
+#define BFM_AUDIOOUT_CTRL_CLKGATE_V(v)              BM_AUDIOOUT_CTRL_CLKGATE
+#define BP_AUDIOOUT_CTRL_DMAWAIT_COUNT              16
+#define BM_AUDIOOUT_CTRL_DMAWAIT_COUNT              0x1f0000
+#define BF_AUDIOOUT_CTRL_DMAWAIT_COUNT(v)           (((v) & 0x1f) << 16)
+#define BFM_AUDIOOUT_CTRL_DMAWAIT_COUNT(v)          BM_AUDIOOUT_CTRL_DMAWAIT_COUNT
+#define BF_AUDIOOUT_CTRL_DMAWAIT_COUNT_V(e)         BF_AUDIOOUT_CTRL_DMAWAIT_COUNT(BV_AUDIOOUT_CTRL_DMAWAIT_COUNT__##e)
+#define BFM_AUDIOOUT_CTRL_DMAWAIT_COUNT_V(v)        BM_AUDIOOUT_CTRL_DMAWAIT_COUNT
+#define BP_AUDIOOUT_CTRL_LR_SWAP                    14
+#define BM_AUDIOOUT_CTRL_LR_SWAP                    0x4000
+#define BF_AUDIOOUT_CTRL_LR_SWAP(v)                 (((v) & 0x1) << 14)
+#define BFM_AUDIOOUT_CTRL_LR_SWAP(v)                BM_AUDIOOUT_CTRL_LR_SWAP
+#define BF_AUDIOOUT_CTRL_LR_SWAP_V(e)               BF_AUDIOOUT_CTRL_LR_SWAP(BV_AUDIOOUT_CTRL_LR_SWAP__##e)
+#define BFM_AUDIOOUT_CTRL_LR_SWAP_V(v)              BM_AUDIOOUT_CTRL_LR_SWAP
+#define BP_AUDIOOUT_CTRL_EDGE_SYNC                  13
+#define BM_AUDIOOUT_CTRL_EDGE_SYNC                  0x2000
+#define BF_AUDIOOUT_CTRL_EDGE_SYNC(v)               (((v) & 0x1) << 13)
+#define BFM_AUDIOOUT_CTRL_EDGE_SYNC(v)              BM_AUDIOOUT_CTRL_EDGE_SYNC
+#define BF_AUDIOOUT_CTRL_EDGE_SYNC_V(e)             BF_AUDIOOUT_CTRL_EDGE_SYNC(BV_AUDIOOUT_CTRL_EDGE_SYNC__##e)
+#define BFM_AUDIOOUT_CTRL_EDGE_SYNC_V(v)            BM_AUDIOOUT_CTRL_EDGE_SYNC
+#define BP_AUDIOOUT_CTRL_INVERT_1BIT                12
+#define BM_AUDIOOUT_CTRL_INVERT_1BIT                0x1000
+#define BF_AUDIOOUT_CTRL_INVERT_1BIT(v)             (((v) & 0x1) << 12)
+#define BFM_AUDIOOUT_CTRL_INVERT_1BIT(v)            BM_AUDIOOUT_CTRL_INVERT_1BIT
+#define BF_AUDIOOUT_CTRL_INVERT_1BIT_V(e)           BF_AUDIOOUT_CTRL_INVERT_1BIT(BV_AUDIOOUT_CTRL_INVERT_1BIT__##e)
+#define BFM_AUDIOOUT_CTRL_INVERT_1BIT_V(v)          BM_AUDIOOUT_CTRL_INVERT_1BIT
+#define BP_AUDIOOUT_CTRL_SS3D_EFFECT                8
+#define BM_AUDIOOUT_CTRL_SS3D_EFFECT                0x300
+#define BF_AUDIOOUT_CTRL_SS3D_EFFECT(v)             (((v) & 0x3) << 8)
+#define BFM_AUDIOOUT_CTRL_SS3D_EFFECT(v)            BM_AUDIOOUT_CTRL_SS3D_EFFECT
+#define BF_AUDIOOUT_CTRL_SS3D_EFFECT_V(e)           BF_AUDIOOUT_CTRL_SS3D_EFFECT(BV_AUDIOOUT_CTRL_SS3D_EFFECT__##e)
+#define BFM_AUDIOOUT_CTRL_SS3D_EFFECT_V(v)          BM_AUDIOOUT_CTRL_SS3D_EFFECT
+#define BP_AUDIOOUT_CTRL_WORD_LENGTH                6
+#define BM_AUDIOOUT_CTRL_WORD_LENGTH                0x40
+#define BF_AUDIOOUT_CTRL_WORD_LENGTH(v)             (((v) & 0x1) << 6)
+#define BFM_AUDIOOUT_CTRL_WORD_LENGTH(v)            BM_AUDIOOUT_CTRL_WORD_LENGTH
+#define BF_AUDIOOUT_CTRL_WORD_LENGTH_V(e)           BF_AUDIOOUT_CTRL_WORD_LENGTH(BV_AUDIOOUT_CTRL_WORD_LENGTH__##e)
+#define BFM_AUDIOOUT_CTRL_WORD_LENGTH_V(v)          BM_AUDIOOUT_CTRL_WORD_LENGTH
+#define BP_AUDIOOUT_CTRL_DAC_ZERO_ENABLE            5
+#define BM_AUDIOOUT_CTRL_DAC_ZERO_ENABLE            0x20
+#define BF_AUDIOOUT_CTRL_DAC_ZERO_ENABLE(v)         (((v) & 0x1) << 5)
+#define BFM_AUDIOOUT_CTRL_DAC_ZERO_ENABLE(v)        BM_AUDIOOUT_CTRL_DAC_ZERO_ENABLE
+#define BF_AUDIOOUT_CTRL_DAC_ZERO_ENABLE_V(e)       BF_AUDIOOUT_CTRL_DAC_ZERO_ENABLE(BV_AUDIOOUT_CTRL_DAC_ZERO_ENABLE__##e)
+#define BFM_AUDIOOUT_CTRL_DAC_ZERO_ENABLE_V(v)      BM_AUDIOOUT_CTRL_DAC_ZERO_ENABLE
+#define BP_AUDIOOUT_CTRL_LOOPBACK                   4
+#define BM_AUDIOOUT_CTRL_LOOPBACK                   0x10
+#define BF_AUDIOOUT_CTRL_LOOPBACK(v)                (((v) & 0x1) << 4)
+#define BFM_AUDIOOUT_CTRL_LOOPBACK(v)               BM_AUDIOOUT_CTRL_LOOPBACK
+#define BF_AUDIOOUT_CTRL_LOOPBACK_V(e)              BF_AUDIOOUT_CTRL_LOOPBACK(BV_AUDIOOUT_CTRL_LOOPBACK__##e)
+#define BFM_AUDIOOUT_CTRL_LOOPBACK_V(v)             BM_AUDIOOUT_CTRL_LOOPBACK
+#define BP_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ         3
+#define BM_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ         0x8
+#define BF_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ(v)      (((v) & 0x1) << 3)
+#define BFM_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ(v)     BM_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ
+#define BF_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ_V(e)    BF_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ(BV_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ__##e)
+#define BFM_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ_V(v)   BM_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ
+#define BP_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ          2
+#define BM_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ          0x4
+#define BF_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ(v)       (((v) & 0x1) << 2)
+#define BFM_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ(v)      BM_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ
+#define BF_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ_V(e)     BF_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ(BV_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ__##e)
+#define BFM_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ_V(v)    BM_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ
+#define BP_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN          1
+#define BM_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN          0x2
+#define BF_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN(v)       (((v) & 0x1) << 1)
+#define BFM_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN(v)      BM_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN
+#define BF_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN_V(e)     BF_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN(BV_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN__##e)
+#define BFM_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN_V(v)    BM_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN
+#define BP_AUDIOOUT_CTRL_RUN                        0
+#define BM_AUDIOOUT_CTRL_RUN                        0x1
+#define BF_AUDIOOUT_CTRL_RUN(v)                     (((v) & 0x1) << 0)
+#define BFM_AUDIOOUT_CTRL_RUN(v)                    BM_AUDIOOUT_CTRL_RUN
+#define BF_AUDIOOUT_CTRL_RUN_V(e)                   BF_AUDIOOUT_CTRL_RUN(BV_AUDIOOUT_CTRL_RUN__##e)
+#define BFM_AUDIOOUT_CTRL_RUN_V(v)                  BM_AUDIOOUT_CTRL_RUN
+
+#define HW_AUDIOOUT_STAT                    HW(AUDIOOUT_STAT)
+#define HWA_AUDIOOUT_STAT                   (0x80048000 + 0x10)
+#define HWT_AUDIOOUT_STAT                   HWIO_32_RW
+#define HWN_AUDIOOUT_STAT                   AUDIOOUT_STAT
+#define HWI_AUDIOOUT_STAT                   
+#define BP_AUDIOOUT_STAT_DAC_PRESENT        31
+#define BM_AUDIOOUT_STAT_DAC_PRESENT        0x80000000
+#define BF_AUDIOOUT_STAT_DAC_PRESENT(v)     (((v) & 0x1) << 31)
+#define BFM_AUDIOOUT_STAT_DAC_PRESENT(v)    BM_AUDIOOUT_STAT_DAC_PRESENT
+#define BF_AUDIOOUT_STAT_DAC_PRESENT_V(e)   BF_AUDIOOUT_STAT_DAC_PRESENT(BV_AUDIOOUT_STAT_DAC_PRESENT__##e)
+#define BFM_AUDIOOUT_STAT_DAC_PRESENT_V(v)  BM_AUDIOOUT_STAT_DAC_PRESENT
+
+#define HW_AUDIOOUT_DACSRR                          HW(AUDIOOUT_DACSRR)
+#define HWA_AUDIOOUT_DACSRR                         (0x80048000 + 0x20)
+#define HWT_AUDIOOUT_DACSRR                         HWIO_32_RW
+#define HWN_AUDIOOUT_DACSRR                         AUDIOOUT_DACSRR
+#define HWI_AUDIOOUT_DACSRR                         
+#define HW_AUDIOOUT_DACSRR_SET                      HW(AUDIOOUT_DACSRR_SET)
+#define HWA_AUDIOOUT_DACSRR_SET                     (HWA_AUDIOOUT_DACSRR + 0x4)
+#define HWT_AUDIOOUT_DACSRR_SET                     HWIO_32_WO
+#define HWN_AUDIOOUT_DACSRR_SET                     AUDIOOUT_DACSRR
+#define HWI_AUDIOOUT_DACSRR_SET                     
+#define HW_AUDIOOUT_DACSRR_CLR                      HW(AUDIOOUT_DACSRR_CLR)
+#define HWA_AUDIOOUT_DACSRR_CLR                     (HWA_AUDIOOUT_DACSRR + 0x8)
+#define HWT_AUDIOOUT_DACSRR_CLR                     HWIO_32_WO
+#define HWN_AUDIOOUT_DACSRR_CLR                     AUDIOOUT_DACSRR
+#define HWI_AUDIOOUT_DACSRR_CLR                     
+#define HW_AUDIOOUT_DACSRR_TOG                      HW(AUDIOOUT_DACSRR_TOG)
+#define HWA_AUDIOOUT_DACSRR_TOG                     (HWA_AUDIOOUT_DACSRR + 0xc)
+#define HWT_AUDIOOUT_DACSRR_TOG                     HWIO_32_WO
+#define HWN_AUDIOOUT_DACSRR_TOG                     AUDIOOUT_DACSRR
+#define HWI_AUDIOOUT_DACSRR_TOG                     
+#define BP_AUDIOOUT_DACSRR_OSR                      31
+#define BM_AUDIOOUT_DACSRR_OSR                      0x80000000
+#define BV_AUDIOOUT_DACSRR_OSR__OSR6                0x0
+#define BV_AUDIOOUT_DACSRR_OSR__OSR12               0x1
+#define BF_AUDIOOUT_DACSRR_OSR(v)                   (((v) & 0x1) << 31)
+#define BFM_AUDIOOUT_DACSRR_OSR(v)                  BM_AUDIOOUT_DACSRR_OSR
+#define BF_AUDIOOUT_DACSRR_OSR_V(e)                 BF_AUDIOOUT_DACSRR_OSR(BV_AUDIOOUT_DACSRR_OSR__##e)
+#define BFM_AUDIOOUT_DACSRR_OSR_V(v)                BM_AUDIOOUT_DACSRR_OSR
+#define BP_AUDIOOUT_DACSRR_BASEMULT                 28
+#define BM_AUDIOOUT_DACSRR_BASEMULT                 0x70000000
+#define BV_AUDIOOUT_DACSRR_BASEMULT__SINGLE_RATE    0x1
+#define BV_AUDIOOUT_DACSRR_BASEMULT__DOUBLE_RATE    0x2
+#define BV_AUDIOOUT_DACSRR_BASEMULT__QUAD_RATE      0x4
+#define BF_AUDIOOUT_DACSRR_BASEMULT(v)              (((v) & 0x7) << 28)
+#define BFM_AUDIOOUT_DACSRR_BASEMULT(v)             BM_AUDIOOUT_DACSRR_BASEMULT
+#define BF_AUDIOOUT_DACSRR_BASEMULT_V(e)            BF_AUDIOOUT_DACSRR_BASEMULT(BV_AUDIOOUT_DACSRR_BASEMULT__##e)
+#define BFM_AUDIOOUT_DACSRR_BASEMULT_V(v)           BM_AUDIOOUT_DACSRR_BASEMULT
+#define BP_AUDIOOUT_DACSRR_SRC_HOLD                 24
+#define BM_AUDIOOUT_DACSRR_SRC_HOLD                 0x7000000
+#define BF_AUDIOOUT_DACSRR_SRC_HOLD(v)              (((v) & 0x7) << 24)
+#define BFM_AUDIOOUT_DACSRR_SRC_HOLD(v)             BM_AUDIOOUT_DACSRR_SRC_HOLD
+#define BF_AUDIOOUT_DACSRR_SRC_HOLD_V(e)            BF_AUDIOOUT_DACSRR_SRC_HOLD(BV_AUDIOOUT_DACSRR_SRC_HOLD__##e)
+#define BFM_AUDIOOUT_DACSRR_SRC_HOLD_V(v)           BM_AUDIOOUT_DACSRR_SRC_HOLD
+#define BP_AUDIOOUT_DACSRR_SRC_INT                  16
+#define BM_AUDIOOUT_DACSRR_SRC_INT                  0x1f0000
+#define BF_AUDIOOUT_DACSRR_SRC_INT(v)               (((v) & 0x1f) << 16)
+#define BFM_AUDIOOUT_DACSRR_SRC_INT(v)              BM_AUDIOOUT_DACSRR_SRC_INT
+#define BF_AUDIOOUT_DACSRR_SRC_INT_V(e)             BF_AUDIOOUT_DACSRR_SRC_INT(BV_AUDIOOUT_DACSRR_SRC_INT__##e)
+#define BFM_AUDIOOUT_DACSRR_SRC_INT_V(v)            BM_AUDIOOUT_DACSRR_SRC_INT
+#define BP_AUDIOOUT_DACSRR_SRC_FRAC                 0
+#define BM_AUDIOOUT_DACSRR_SRC_FRAC                 0x1fff
+#define BF_AUDIOOUT_DACSRR_SRC_FRAC(v)              (((v) & 0x1fff) << 0)
+#define BFM_AUDIOOUT_DACSRR_SRC_FRAC(v)             BM_AUDIOOUT_DACSRR_SRC_FRAC
+#define BF_AUDIOOUT_DACSRR_SRC_FRAC_V(e)            BF_AUDIOOUT_DACSRR_SRC_FRAC(BV_AUDIOOUT_DACSRR_SRC_FRAC__##e)
+#define BFM_AUDIOOUT_DACSRR_SRC_FRAC_V(v)           BM_AUDIOOUT_DACSRR_SRC_FRAC
+
+#define HW_AUDIOOUT_DACVOLUME                           HW(AUDIOOUT_DACVOLUME)
+#define HWA_AUDIOOUT_DACVOLUME                          (0x80048000 + 0x30)
+#define HWT_AUDIOOUT_DACVOLUME                          HWIO_32_RW
+#define HWN_AUDIOOUT_DACVOLUME                          AUDIOOUT_DACVOLUME
+#define HWI_AUDIOOUT_DACVOLUME                          
+#define HW_AUDIOOUT_DACVOLUME_SET                       HW(AUDIOOUT_DACVOLUME_SET)
+#define HWA_AUDIOOUT_DACVOLUME_SET                      (HWA_AUDIOOUT_DACVOLUME + 0x4)
+#define HWT_AUDIOOUT_DACVOLUME_SET                      HWIO_32_WO
+#define HWN_AUDIOOUT_DACVOLUME_SET                      AUDIOOUT_DACVOLUME
+#define HWI_AUDIOOUT_DACVOLUME_SET                      
+#define HW_AUDIOOUT_DACVOLUME_CLR                       HW(AUDIOOUT_DACVOLUME_CLR)
+#define HWA_AUDIOOUT_DACVOLUME_CLR                      (HWA_AUDIOOUT_DACVOLUME + 0x8)
+#define HWT_AUDIOOUT_DACVOLUME_CLR                      HWIO_32_WO
+#define HWN_AUDIOOUT_DACVOLUME_CLR                      AUDIOOUT_DACVOLUME
+#define HWI_AUDIOOUT_DACVOLUME_CLR                      
+#define HW_AUDIOOUT_DACVOLUME_TOG                       HW(AUDIOOUT_DACVOLUME_TOG)
+#define HWA_AUDIOOUT_DACVOLUME_TOG                      (HWA_AUDIOOUT_DACVOLUME + 0xc)
+#define HWT_AUDIOOUT_DACVOLUME_TOG                      HWIO_32_WO
+#define HWN_AUDIOOUT_DACVOLUME_TOG                      AUDIOOUT_DACVOLUME
+#define HWI_AUDIOOUT_DACVOLUME_TOG                      
+#define BP_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT        28
+#define BM_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT        0x10000000
+#define BF_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT(v)     (((v) & 0x1) << 28)
+#define BFM_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT(v)    BM_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT
+#define BF_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT_V(e)   BF_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT(BV_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT__##e)
+#define BFM_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT_V(v)  BM_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT
+#define BP_AUDIOOUT_DACVOLUME_EN_ZCD                    25
+#define BM_AUDIOOUT_DACVOLUME_EN_ZCD                    0x2000000
+#define BF_AUDIOOUT_DACVOLUME_EN_ZCD(v)                 (((v) & 0x1) << 25)
+#define BFM_AUDIOOUT_DACVOLUME_EN_ZCD(v)                BM_AUDIOOUT_DACVOLUME_EN_ZCD
+#define BF_AUDIOOUT_DACVOLUME_EN_ZCD_V(e)               BF_AUDIOOUT_DACVOLUME_EN_ZCD(BV_AUDIOOUT_DACVOLUME_EN_ZCD__##e)
+#define BFM_AUDIOOUT_DACVOLUME_EN_ZCD_V(v)              BM_AUDIOOUT_DACVOLUME_EN_ZCD
+#define BP_AUDIOOUT_DACVOLUME_MUTE_LEFT                 24
+#define BM_AUDIOOUT_DACVOLUME_MUTE_LEFT                 0x1000000
+#define BF_AUDIOOUT_DACVOLUME_MUTE_LEFT(v)              (((v) & 0x1) << 24)
+#define BFM_AUDIOOUT_DACVOLUME_MUTE_LEFT(v)             BM_AUDIOOUT_DACVOLUME_MUTE_LEFT
+#define BF_AUDIOOUT_DACVOLUME_MUTE_LEFT_V(e)            BF_AUDIOOUT_DACVOLUME_MUTE_LEFT(BV_AUDIOOUT_DACVOLUME_MUTE_LEFT__##e)
+#define BFM_AUDIOOUT_DACVOLUME_MUTE_LEFT_V(v)           BM_AUDIOOUT_DACVOLUME_MUTE_LEFT
+#define BP_AUDIOOUT_DACVOLUME_VOLUME_LEFT               16
+#define BM_AUDIOOUT_DACVOLUME_VOLUME_LEFT               0xff0000
+#define BF_AUDIOOUT_DACVOLUME_VOLUME_LEFT(v)            (((v) & 0xff) << 16)
+#define BFM_AUDIOOUT_DACVOLUME_VOLUME_LEFT(v)           BM_AUDIOOUT_DACVOLUME_VOLUME_LEFT
+#define BF_AUDIOOUT_DACVOLUME_VOLUME_LEFT_V(e)          BF_AUDIOOUT_DACVOLUME_VOLUME_LEFT(BV_AUDIOOUT_DACVOLUME_VOLUME_LEFT__##e)
+#define BFM_AUDIOOUT_DACVOLUME_VOLUME_LEFT_V(v)         BM_AUDIOOUT_DACVOLUME_VOLUME_LEFT
+#define BP_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT       12
+#define BM_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT       0x1000
+#define BF_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT(v)    (((v) & 0x1) << 12)
+#define BFM_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT(v)   BM_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT
+#define BF_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT_V(e)  BF_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT(BV_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT__##e)
+#define BFM_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT_V(v) BM_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT
+#define BP_AUDIOOUT_DACVOLUME_MUTE_RIGHT                8
+#define BM_AUDIOOUT_DACVOLUME_MUTE_RIGHT                0x100
+#define BF_AUDIOOUT_DACVOLUME_MUTE_RIGHT(v)             (((v) & 0x1) << 8)
+#define BFM_AUDIOOUT_DACVOLUME_MUTE_RIGHT(v)            BM_AUDIOOUT_DACVOLUME_MUTE_RIGHT
+#define BF_AUDIOOUT_DACVOLUME_MUTE_RIGHT_V(e)           BF_AUDIOOUT_DACVOLUME_MUTE_RIGHT(BV_AUDIOOUT_DACVOLUME_MUTE_RIGHT__##e)
+#define BFM_AUDIOOUT_DACVOLUME_MUTE_RIGHT_V(v)          BM_AUDIOOUT_DACVOLUME_MUTE_RIGHT
+#define BP_AUDIOOUT_DACVOLUME_VOLUME_RIGHT              0
+#define BM_AUDIOOUT_DACVOLUME_VOLUME_RIGHT              0xff
+#define BF_AUDIOOUT_DACVOLUME_VOLUME_RIGHT(v)           (((v) & 0xff) << 0)
+#define BFM_AUDIOOUT_DACVOLUME_VOLUME_RIGHT(v)          BM_AUDIOOUT_DACVOLUME_VOLUME_RIGHT
+#define BF_AUDIOOUT_DACVOLUME_VOLUME_RIGHT_V(e)         BF_AUDIOOUT_DACVOLUME_VOLUME_RIGHT(BV_AUDIOOUT_DACVOLUME_VOLUME_RIGHT__##e)
+#define BFM_AUDIOOUT_DACVOLUME_VOLUME_RIGHT_V(v)        BM_AUDIOOUT_DACVOLUME_VOLUME_RIGHT
+
+#define HW_AUDIOOUT_DACDEBUG                                    HW(AUDIOOUT_DACDEBUG)
+#define HWA_AUDIOOUT_DACDEBUG                                   (0x80048000 + 0x40)
+#define HWT_AUDIOOUT_DACDEBUG                                   HWIO_32_RW
+#define HWN_AUDIOOUT_DACDEBUG                                   AUDIOOUT_DACDEBUG
+#define HWI_AUDIOOUT_DACDEBUG                                   
+#define HW_AUDIOOUT_DACDEBUG_SET                                HW(AUDIOOUT_DACDEBUG_SET)
+#define HWA_AUDIOOUT_DACDEBUG_SET                               (HWA_AUDIOOUT_DACDEBUG + 0x4)
+#define HWT_AUDIOOUT_DACDEBUG_SET                               HWIO_32_WO
+#define HWN_AUDIOOUT_DACDEBUG_SET                               AUDIOOUT_DACDEBUG
+#define HWI_AUDIOOUT_DACDEBUG_SET                               
+#define HW_AUDIOOUT_DACDEBUG_CLR                                HW(AUDIOOUT_DACDEBUG_CLR)
+#define HWA_AUDIOOUT_DACDEBUG_CLR                               (HWA_AUDIOOUT_DACDEBUG + 0x8)
+#define HWT_AUDIOOUT_DACDEBUG_CLR                               HWIO_32_WO
+#define HWN_AUDIOOUT_DACDEBUG_CLR                               AUDIOOUT_DACDEBUG
+#define HWI_AUDIOOUT_DACDEBUG_CLR                               
+#define HW_AUDIOOUT_DACDEBUG_TOG                                HW(AUDIOOUT_DACDEBUG_TOG)
+#define HWA_AUDIOOUT_DACDEBUG_TOG                               (HWA_AUDIOOUT_DACDEBUG + 0xc)
+#define HWT_AUDIOOUT_DACDEBUG_TOG                               HWIO_32_WO
+#define HWN_AUDIOOUT_DACDEBUG_TOG                               AUDIOOUT_DACDEBUG
+#define HWI_AUDIOOUT_DACDEBUG_TOG                               
+#define BP_AUDIOOUT_DACDEBUG_ENABLE_DACDMA                      31
+#define BM_AUDIOOUT_DACDEBUG_ENABLE_DACDMA                      0x80000000
+#define BF_AUDIOOUT_DACDEBUG_ENABLE_DACDMA(v)                   (((v) & 0x1) << 31)
+#define BFM_AUDIOOUT_DACDEBUG_ENABLE_DACDMA(v)                  BM_AUDIOOUT_DACDEBUG_ENABLE_DACDMA
+#define BF_AUDIOOUT_DACDEBUG_ENABLE_DACDMA_V(e)                 BF_AUDIOOUT_DACDEBUG_ENABLE_DACDMA(BV_AUDIOOUT_DACDEBUG_ENABLE_DACDMA__##e)
+#define BFM_AUDIOOUT_DACDEBUG_ENABLE_DACDMA_V(v)                BM_AUDIOOUT_DACDEBUG_ENABLE_DACDMA
+#define BP_AUDIOOUT_DACDEBUG_RAM_SS                             8
+#define BM_AUDIOOUT_DACDEBUG_RAM_SS                             0xf00
+#define BF_AUDIOOUT_DACDEBUG_RAM_SS(v)                          (((v) & 0xf) << 8)
+#define BFM_AUDIOOUT_DACDEBUG_RAM_SS(v)                         BM_AUDIOOUT_DACDEBUG_RAM_SS
+#define BF_AUDIOOUT_DACDEBUG_RAM_SS_V(e)                        BF_AUDIOOUT_DACDEBUG_RAM_SS(BV_AUDIOOUT_DACDEBUG_RAM_SS__##e)
+#define BFM_AUDIOOUT_DACDEBUG_RAM_SS_V(v)                       BM_AUDIOOUT_DACDEBUG_RAM_SS
+#define BP_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS           5
+#define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS           0x20
+#define BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS(v)        (((v) & 0x1) << 5)
+#define BFM_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS(v)       BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS
+#define BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS_V(e)      BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS(BV_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS__##e)
+#define BFM_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS_V(v)     BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS
+#define BP_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS           4
+#define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS           0x10
+#define BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS(v)        (((v) & 0x1) << 4)
+#define BFM_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS(v)       BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS
+#define BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS_V(e)      BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS(BV_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS__##e)
+#define BFM_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS_V(v)     BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS
+#define BP_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE          3
+#define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE          0x8
+#define BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE(v)       (((v) & 0x1) << 3)
+#define BFM_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE(v)      BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE
+#define BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE_V(e)     BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE(BV_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE__##e)
+#define BFM_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE_V(v)    BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE
+#define BP_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE          2
+#define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE          0x4
+#define BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE(v)       (((v) & 0x1) << 2)
+#define BFM_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE(v)      BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE
+#define BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE_V(e)     BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE(BV_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE__##e)
+#define BFM_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE_V(v)    BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE
+#define BP_AUDIOOUT_DACDEBUG_DMA_PREQ                           1
+#define BM_AUDIOOUT_DACDEBUG_DMA_PREQ                           0x2
+#define BF_AUDIOOUT_DACDEBUG_DMA_PREQ(v)                        (((v) & 0x1) << 1)
+#define BFM_AUDIOOUT_DACDEBUG_DMA_PREQ(v)                       BM_AUDIOOUT_DACDEBUG_DMA_PREQ
+#define BF_AUDIOOUT_DACDEBUG_DMA_PREQ_V(e)                      BF_AUDIOOUT_DACDEBUG_DMA_PREQ(BV_AUDIOOUT_DACDEBUG_DMA_PREQ__##e)
+#define BFM_AUDIOOUT_DACDEBUG_DMA_PREQ_V(v)                     BM_AUDIOOUT_DACDEBUG_DMA_PREQ
+#define BP_AUDIOOUT_DACDEBUG_FIFO_STATUS                        0
+#define BM_AUDIOOUT_DACDEBUG_FIFO_STATUS                        0x1
+#define BF_AUDIOOUT_DACDEBUG_FIFO_STATUS(v)                     (((v) & 0x1) << 0)
+#define BFM_AUDIOOUT_DACDEBUG_FIFO_STATUS(v)                    BM_AUDIOOUT_DACDEBUG_FIFO_STATUS
+#define BF_AUDIOOUT_DACDEBUG_FIFO_STATUS_V(e)                   BF_AUDIOOUT_DACDEBUG_FIFO_STATUS(BV_AUDIOOUT_DACDEBUG_FIFO_STATUS__##e)
+#define BFM_AUDIOOUT_DACDEBUG_FIFO_STATUS_V(v)                  BM_AUDIOOUT_DACDEBUG_FIFO_STATUS
+
+#define HW_AUDIOOUT_HPVOL                               HW(AUDIOOUT_HPVOL)
+#define HWA_AUDIOOUT_HPVOL                              (0x80048000 + 0x50)
+#define HWT_AUDIOOUT_HPVOL                              HWIO_32_RW
+#define HWN_AUDIOOUT_HPVOL                              AUDIOOUT_HPVOL
+#define HWI_AUDIOOUT_HPVOL                              
+#define HW_AUDIOOUT_HPVOL_SET                           HW(AUDIOOUT_HPVOL_SET)
+#define HWA_AUDIOOUT_HPVOL_SET                          (HWA_AUDIOOUT_HPVOL + 0x4)
+#define HWT_AUDIOOUT_HPVOL_SET                          HWIO_32_WO
+#define HWN_AUDIOOUT_HPVOL_SET                          AUDIOOUT_HPVOL
+#define HWI_AUDIOOUT_HPVOL_SET                          
+#define HW_AUDIOOUT_HPVOL_CLR                           HW(AUDIOOUT_HPVOL_CLR)
+#define HWA_AUDIOOUT_HPVOL_CLR                          (HWA_AUDIOOUT_HPVOL + 0x8)
+#define HWT_AUDIOOUT_HPVOL_CLR                          HWIO_32_WO
+#define HWN_AUDIOOUT_HPVOL_CLR                          AUDIOOUT_HPVOL
+#define HWI_AUDIOOUT_HPVOL_CLR                          
+#define HW_AUDIOOUT_HPVOL_TOG                           HW(AUDIOOUT_HPVOL_TOG)
+#define HWA_AUDIOOUT_HPVOL_TOG                          (HWA_AUDIOOUT_HPVOL + 0xc)
+#define HWT_AUDIOOUT_HPVOL_TOG                          HWIO_32_WO
+#define HWN_AUDIOOUT_HPVOL_TOG                          AUDIOOUT_HPVOL
+#define HWI_AUDIOOUT_HPVOL_TOG                          
+#define BP_AUDIOOUT_HPVOL_VOLUME_UPDATE_PENDING         28
+#define BM_AUDIOOUT_HPVOL_VOLUME_UPDATE_PENDING         0x10000000
+#define BF_AUDIOOUT_HPVOL_VOLUME_UPDATE_PENDING(v)      (((v) & 0x1) << 28)
+#define BFM_AUDIOOUT_HPVOL_VOLUME_UPDATE_PENDING(v)     BM_AUDIOOUT_HPVOL_VOLUME_UPDATE_PENDING
+#define BF_AUDIOOUT_HPVOL_VOLUME_UPDATE_PENDING_V(e)    BF_AUDIOOUT_HPVOL_VOLUME_UPDATE_PENDING(BV_AUDIOOUT_HPVOL_VOLUME_UPDATE_PENDING__##e)
+#define BFM_AUDIOOUT_HPVOL_VOLUME_UPDATE_PENDING_V(v)   BM_AUDIOOUT_HPVOL_VOLUME_UPDATE_PENDING
+#define BP_AUDIOOUT_HPVOL_EN_MSTR_ZCD                   25
+#define BM_AUDIOOUT_HPVOL_EN_MSTR_ZCD                   0x2000000
+#define BF_AUDIOOUT_HPVOL_EN_MSTR_ZCD(v)                (((v) & 0x1) << 25)
+#define BFM_AUDIOOUT_HPVOL_EN_MSTR_ZCD(v)               BM_AUDIOOUT_HPVOL_EN_MSTR_ZCD
+#define BF_AUDIOOUT_HPVOL_EN_MSTR_ZCD_V(e)              BF_AUDIOOUT_HPVOL_EN_MSTR_ZCD(BV_AUDIOOUT_HPVOL_EN_MSTR_ZCD__##e)
+#define BFM_AUDIOOUT_HPVOL_EN_MSTR_ZCD_V(v)             BM_AUDIOOUT_HPVOL_EN_MSTR_ZCD
+#define BP_AUDIOOUT_HPVOL_MUTE                          24
+#define BM_AUDIOOUT_HPVOL_MUTE                          0x1000000
+#define BF_AUDIOOUT_HPVOL_MUTE(v)                       (((v) & 0x1) << 24)
+#define BFM_AUDIOOUT_HPVOL_MUTE(v)                      BM_AUDIOOUT_HPVOL_MUTE
+#define BF_AUDIOOUT_HPVOL_MUTE_V(e)                     BF_AUDIOOUT_HPVOL_MUTE(BV_AUDIOOUT_HPVOL_MUTE__##e)
+#define BFM_AUDIOOUT_HPVOL_MUTE_V(v)                    BM_AUDIOOUT_HPVOL_MUTE
+#define BP_AUDIOOUT_HPVOL_SELECT                        16
+#define BM_AUDIOOUT_HPVOL_SELECT                        0x10000
+#define BF_AUDIOOUT_HPVOL_SELECT(v)                     (((v) & 0x1) << 16)
+#define BFM_AUDIOOUT_HPVOL_SELECT(v)                    BM_AUDIOOUT_HPVOL_SELECT
+#define BF_AUDIOOUT_HPVOL_SELECT_V(e)                   BF_AUDIOOUT_HPVOL_SELECT(BV_AUDIOOUT_HPVOL_SELECT__##e)
+#define BFM_AUDIOOUT_HPVOL_SELECT_V(v)                  BM_AUDIOOUT_HPVOL_SELECT
+#define BP_AUDIOOUT_HPVOL_VOL_LEFT                      8
+#define BM_AUDIOOUT_HPVOL_VOL_LEFT                      0x7f00
+#define BF_AUDIOOUT_HPVOL_VOL_LEFT(v)                   (((v) & 0x7f) << 8)
+#define BFM_AUDIOOUT_HPVOL_VOL_LEFT(v)                  BM_AUDIOOUT_HPVOL_VOL_LEFT
+#define BF_AUDIOOUT_HPVOL_VOL_LEFT_V(e)                 BF_AUDIOOUT_HPVOL_VOL_LEFT(BV_AUDIOOUT_HPVOL_VOL_LEFT__##e)
+#define BFM_AUDIOOUT_HPVOL_VOL_LEFT_V(v)                BM_AUDIOOUT_HPVOL_VOL_LEFT
+#define BP_AUDIOOUT_HPVOL_VOL_RIGHT                     0
+#define BM_AUDIOOUT_HPVOL_VOL_RIGHT                     0x7f
+#define BF_AUDIOOUT_HPVOL_VOL_RIGHT(v)                  (((v) & 0x7f) << 0)
+#define BFM_AUDIOOUT_HPVOL_VOL_RIGHT(v)                 BM_AUDIOOUT_HPVOL_VOL_RIGHT
+#define BF_AUDIOOUT_HPVOL_VOL_RIGHT_V(e)                BF_AUDIOOUT_HPVOL_VOL_RIGHT(BV_AUDIOOUT_HPVOL_VOL_RIGHT__##e)
+#define BFM_AUDIOOUT_HPVOL_VOL_RIGHT_V(v)               BM_AUDIOOUT_HPVOL_VOL_RIGHT
+
+#define HW_AUDIOOUT_RESERVED    HW(AUDIOOUT_RESERVED)
+#define HWA_AUDIOOUT_RESERVED   (0x80048000 + 0x60)
+#define HWT_AUDIOOUT_RESERVED   HWIO_32_RW
+#define HWN_AUDIOOUT_RESERVED   AUDIOOUT_RESERVED
+#define HWI_AUDIOOUT_RESERVED   
+
+#define HW_AUDIOOUT_PWRDN                   HW(AUDIOOUT_PWRDN)
+#define HWA_AUDIOOUT_PWRDN                  (0x80048000 + 0x70)
+#define HWT_AUDIOOUT_PWRDN                  HWIO_32_RW
+#define HWN_AUDIOOUT_PWRDN                  AUDIOOUT_PWRDN
+#define HWI_AUDIOOUT_PWRDN                  
+#define HW_AUDIOOUT_PWRDN_SET               HW(AUDIOOUT_PWRDN_SET)
+#define HWA_AUDIOOUT_PWRDN_SET              (HWA_AUDIOOUT_PWRDN + 0x4)
+#define HWT_AUDIOOUT_PWRDN_SET              HWIO_32_WO
+#define HWN_AUDIOOUT_PWRDN_SET              AUDIOOUT_PWRDN
+#define HWI_AUDIOOUT_PWRDN_SET              
+#define HW_AUDIOOUT_PWRDN_CLR               HW(AUDIOOUT_PWRDN_CLR)
+#define HWA_AUDIOOUT_PWRDN_CLR              (HWA_AUDIOOUT_PWRDN + 0x8)
+#define HWT_AUDIOOUT_PWRDN_CLR              HWIO_32_WO
+#define HWN_AUDIOOUT_PWRDN_CLR              AUDIOOUT_PWRDN
+#define HWI_AUDIOOUT_PWRDN_CLR              
+#define HW_AUDIOOUT_PWRDN_TOG               HW(AUDIOOUT_PWRDN_TOG)
+#define HWA_AUDIOOUT_PWRDN_TOG              (HWA_AUDIOOUT_PWRDN + 0xc)
+#define HWT_AUDIOOUT_PWRDN_TOG              HWIO_32_WO
+#define HWN_AUDIOOUT_PWRDN_TOG              AUDIOOUT_PWRDN
+#define HWI_AUDIOOUT_PWRDN_TOG              
+#define BP_AUDIOOUT_PWRDN_LINEOUT           24
+#define BM_AUDIOOUT_PWRDN_LINEOUT           0x1000000
+#define BF_AUDIOOUT_PWRDN_LINEOUT(v)        (((v) & 0x1) << 24)
+#define BFM_AUDIOOUT_PWRDN_LINEOUT(v)       BM_AUDIOOUT_PWRDN_LINEOUT
+#define BF_AUDIOOUT_PWRDN_LINEOUT_V(e)      BF_AUDIOOUT_PWRDN_LINEOUT(BV_AUDIOOUT_PWRDN_LINEOUT__##e)
+#define BFM_AUDIOOUT_PWRDN_LINEOUT_V(v)     BM_AUDIOOUT_PWRDN_LINEOUT
+#define BP_AUDIOOUT_PWRDN_SELFBIAS          20
+#define BM_AUDIOOUT_PWRDN_SELFBIAS          0x100000
+#define BF_AUDIOOUT_PWRDN_SELFBIAS(v)       (((v) & 0x1) << 20)
+#define BFM_AUDIOOUT_PWRDN_SELFBIAS(v)      BM_AUDIOOUT_PWRDN_SELFBIAS
+#define BF_AUDIOOUT_PWRDN_SELFBIAS_V(e)     BF_AUDIOOUT_PWRDN_SELFBIAS(BV_AUDIOOUT_PWRDN_SELFBIAS__##e)
+#define BFM_AUDIOOUT_PWRDN_SELFBIAS_V(v)    BM_AUDIOOUT_PWRDN_SELFBIAS
+#define BP_AUDIOOUT_PWRDN_RIGHT_ADC         16
+#define BM_AUDIOOUT_PWRDN_RIGHT_ADC         0x10000
+#define BF_AUDIOOUT_PWRDN_RIGHT_ADC(v)      (((v) & 0x1) << 16)
+#define BFM_AUDIOOUT_PWRDN_RIGHT_ADC(v)     BM_AUDIOOUT_PWRDN_RIGHT_ADC
+#define BF_AUDIOOUT_PWRDN_RIGHT_ADC_V(e)    BF_AUDIOOUT_PWRDN_RIGHT_ADC(BV_AUDIOOUT_PWRDN_RIGHT_ADC__##e)
+#define BFM_AUDIOOUT_PWRDN_RIGHT_ADC_V(v)   BM_AUDIOOUT_PWRDN_RIGHT_ADC
+#define BP_AUDIOOUT_PWRDN_DAC               12
+#define BM_AUDIOOUT_PWRDN_DAC               0x1000
+#define BF_AUDIOOUT_PWRDN_DAC(v)            (((v) & 0x1) << 12)
+#define BFM_AUDIOOUT_PWRDN_DAC(v)           BM_AUDIOOUT_PWRDN_DAC
+#define BF_AUDIOOUT_PWRDN_DAC_V(e)          BF_AUDIOOUT_PWRDN_DAC(BV_AUDIOOUT_PWRDN_DAC__##e)
+#define BFM_AUDIOOUT_PWRDN_DAC_V(v)         BM_AUDIOOUT_PWRDN_DAC
+#define BP_AUDIOOUT_PWRDN_ADC               8
+#define BM_AUDIOOUT_PWRDN_ADC               0x100
+#define BF_AUDIOOUT_PWRDN_ADC(v)            (((v) & 0x1) << 8)
+#define BFM_AUDIOOUT_PWRDN_ADC(v)           BM_AUDIOOUT_PWRDN_ADC
+#define BF_AUDIOOUT_PWRDN_ADC_V(e)          BF_AUDIOOUT_PWRDN_ADC(BV_AUDIOOUT_PWRDN_ADC__##e)
+#define BFM_AUDIOOUT_PWRDN_ADC_V(v)         BM_AUDIOOUT_PWRDN_ADC
+#define BP_AUDIOOUT_PWRDN_CAPLESS           4
+#define BM_AUDIOOUT_PWRDN_CAPLESS           0x10
+#define BF_AUDIOOUT_PWRDN_CAPLESS(v)        (((v) & 0x1) << 4)
+#define BFM_AUDIOOUT_PWRDN_CAPLESS(v)       BM_AUDIOOUT_PWRDN_CAPLESS
+#define BF_AUDIOOUT_PWRDN_CAPLESS_V(e)      BF_AUDIOOUT_PWRDN_CAPLESS(BV_AUDIOOUT_PWRDN_CAPLESS__##e)
+#define BFM_AUDIOOUT_PWRDN_CAPLESS_V(v)     BM_AUDIOOUT_PWRDN_CAPLESS
+#define BP_AUDIOOUT_PWRDN_HEADPHONE         0
+#define BM_AUDIOOUT_PWRDN_HEADPHONE         0x1
+#define BF_AUDIOOUT_PWRDN_HEADPHONE(v)      (((v) & 0x1) << 0)
+#define BFM_AUDIOOUT_PWRDN_HEADPHONE(v)     BM_AUDIOOUT_PWRDN_HEADPHONE
+#define BF_AUDIOOUT_PWRDN_HEADPHONE_V(e)    BF_AUDIOOUT_PWRDN_HEADPHONE(BV_AUDIOOUT_PWRDN_HEADPHONE__##e)
+#define BFM_AUDIOOUT_PWRDN_HEADPHONE_V(v)   BM_AUDIOOUT_PWRDN_HEADPHONE
+
+#define HW_AUDIOOUT_REFCTRL                         HW(AUDIOOUT_REFCTRL)
+#define HWA_AUDIOOUT_REFCTRL                        (0x80048000 + 0x80)
+#define HWT_AUDIOOUT_REFCTRL                        HWIO_32_RW
+#define HWN_AUDIOOUT_REFCTRL                        AUDIOOUT_REFCTRL
+#define HWI_AUDIOOUT_REFCTRL                        
+#define HW_AUDIOOUT_REFCTRL_SET                     HW(AUDIOOUT_REFCTRL_SET)
+#define HWA_AUDIOOUT_REFCTRL_SET                    (HWA_AUDIOOUT_REFCTRL + 0x4)
+#define HWT_AUDIOOUT_REFCTRL_SET                    HWIO_32_WO
+#define HWN_AUDIOOUT_REFCTRL_SET                    AUDIOOUT_REFCTRL
+#define HWI_AUDIOOUT_REFCTRL_SET                    
+#define HW_AUDIOOUT_REFCTRL_CLR                     HW(AUDIOOUT_REFCTRL_CLR)
+#define HWA_AUDIOOUT_REFCTRL_CLR                    (HWA_AUDIOOUT_REFCTRL + 0x8)
+#define HWT_AUDIOOUT_REFCTRL_CLR                    HWIO_32_WO
+#define HWN_AUDIOOUT_REFCTRL_CLR                    AUDIOOUT_REFCTRL
+#define HWI_AUDIOOUT_REFCTRL_CLR                    
+#define HW_AUDIOOUT_REFCTRL_TOG                     HW(AUDIOOUT_REFCTRL_TOG)
+#define HWA_AUDIOOUT_REFCTRL_TOG                    (HWA_AUDIOOUT_REFCTRL + 0xc)
+#define HWT_AUDIOOUT_REFCTRL_TOG                    HWIO_32_WO
+#define HWN_AUDIOOUT_REFCTRL_TOG                    AUDIOOUT_REFCTRL
+#define HWI_AUDIOOUT_REFCTRL_TOG                    
+#define BP_AUDIOOUT_REFCTRL_FASTSETTLING            26
+#define BM_AUDIOOUT_REFCTRL_FASTSETTLING            0x4000000
+#define BF_AUDIOOUT_REFCTRL_FASTSETTLING(v)         (((v) & 0x1) << 26)
+#define BFM_AUDIOOUT_REFCTRL_FASTSETTLING(v)        BM_AUDIOOUT_REFCTRL_FASTSETTLING
+#define BF_AUDIOOUT_REFCTRL_FASTSETTLING_V(e)       BF_AUDIOOUT_REFCTRL_FASTSETTLING(BV_AUDIOOUT_REFCTRL_FASTSETTLING__##e)
+#define BFM_AUDIOOUT_REFCTRL_FASTSETTLING_V(v)      BM_AUDIOOUT_REFCTRL_FASTSETTLING
+#define BP_AUDIOOUT_REFCTRL_RAISE_REF               25
+#define BM_AUDIOOUT_REFCTRL_RAISE_REF               0x2000000
+#define BF_AUDIOOUT_REFCTRL_RAISE_REF(v)            (((v) & 0x1) << 25)
+#define BFM_AUDIOOUT_REFCTRL_RAISE_REF(v)           BM_AUDIOOUT_REFCTRL_RAISE_REF
+#define BF_AUDIOOUT_REFCTRL_RAISE_REF_V(e)          BF_AUDIOOUT_REFCTRL_RAISE_REF(BV_AUDIOOUT_REFCTRL_RAISE_REF__##e)
+#define BFM_AUDIOOUT_REFCTRL_RAISE_REF_V(v)         BM_AUDIOOUT_REFCTRL_RAISE_REF
+#define BP_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS           24
+#define BM_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS           0x1000000
+#define BF_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS(v)        (((v) & 0x1) << 24)
+#define BFM_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS(v)       BM_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS
+#define BF_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS_V(e)      BF_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS(BV_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS__##e)
+#define BFM_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS_V(v)     BM_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS
+#define BP_AUDIOOUT_REFCTRL_VBG_ADJ                 20
+#define BM_AUDIOOUT_REFCTRL_VBG_ADJ                 0x700000
+#define BF_AUDIOOUT_REFCTRL_VBG_ADJ(v)              (((v) & 0x7) << 20)
+#define BFM_AUDIOOUT_REFCTRL_VBG_ADJ(v)             BM_AUDIOOUT_REFCTRL_VBG_ADJ
+#define BF_AUDIOOUT_REFCTRL_VBG_ADJ_V(e)            BF_AUDIOOUT_REFCTRL_VBG_ADJ(BV_AUDIOOUT_REFCTRL_VBG_ADJ__##e)
+#define BFM_AUDIOOUT_REFCTRL_VBG_ADJ_V(v)           BM_AUDIOOUT_REFCTRL_VBG_ADJ
+#define BP_AUDIOOUT_REFCTRL_LOW_PWR                 19
+#define BM_AUDIOOUT_REFCTRL_LOW_PWR                 0x80000
+#define BF_AUDIOOUT_REFCTRL_LOW_PWR(v)              (((v) & 0x1) << 19)
+#define BFM_AUDIOOUT_REFCTRL_LOW_PWR(v)             BM_AUDIOOUT_REFCTRL_LOW_PWR
+#define BF_AUDIOOUT_REFCTRL_LOW_PWR_V(e)            BF_AUDIOOUT_REFCTRL_LOW_PWR(BV_AUDIOOUT_REFCTRL_LOW_PWR__##e)
+#define BFM_AUDIOOUT_REFCTRL_LOW_PWR_V(v)           BM_AUDIOOUT_REFCTRL_LOW_PWR
+#define BP_AUDIOOUT_REFCTRL_LW_REF                  18
+#define BM_AUDIOOUT_REFCTRL_LW_REF                  0x40000
+#define BF_AUDIOOUT_REFCTRL_LW_REF(v)               (((v) & 0x1) << 18)
+#define BFM_AUDIOOUT_REFCTRL_LW_REF(v)              BM_AUDIOOUT_REFCTRL_LW_REF
+#define BF_AUDIOOUT_REFCTRL_LW_REF_V(e)             BF_AUDIOOUT_REFCTRL_LW_REF(BV_AUDIOOUT_REFCTRL_LW_REF__##e)
+#define BFM_AUDIOOUT_REFCTRL_LW_REF_V(v)            BM_AUDIOOUT_REFCTRL_LW_REF
+#define BP_AUDIOOUT_REFCTRL_BIAS_CTRL               16
+#define BM_AUDIOOUT_REFCTRL_BIAS_CTRL               0x30000
+#define BF_AUDIOOUT_REFCTRL_BIAS_CTRL(v)            (((v) & 0x3) << 16)
+#define BFM_AUDIOOUT_REFCTRL_BIAS_CTRL(v)           BM_AUDIOOUT_REFCTRL_BIAS_CTRL
+#define BF_AUDIOOUT_REFCTRL_BIAS_CTRL_V(e)          BF_AUDIOOUT_REFCTRL_BIAS_CTRL(BV_AUDIOOUT_REFCTRL_BIAS_CTRL__##e)
+#define BFM_AUDIOOUT_REFCTRL_BIAS_CTRL_V(v)         BM_AUDIOOUT_REFCTRL_BIAS_CTRL
+#define BP_AUDIOOUT_REFCTRL_VDDXTAL_TO_VDDD         14
+#define BM_AUDIOOUT_REFCTRL_VDDXTAL_TO_VDDD         0x4000
+#define BF_AUDIOOUT_REFCTRL_VDDXTAL_TO_VDDD(v)      (((v) & 0x1) << 14)
+#define BFM_AUDIOOUT_REFCTRL_VDDXTAL_TO_VDDD(v)     BM_AUDIOOUT_REFCTRL_VDDXTAL_TO_VDDD
+#define BF_AUDIOOUT_REFCTRL_VDDXTAL_TO_VDDD_V(e)    BF_AUDIOOUT_REFCTRL_VDDXTAL_TO_VDDD(BV_AUDIOOUT_REFCTRL_VDDXTAL_TO_VDDD__##e)
+#define BFM_AUDIOOUT_REFCTRL_VDDXTAL_TO_VDDD_V(v)   BM_AUDIOOUT_REFCTRL_VDDXTAL_TO_VDDD
+#define BP_AUDIOOUT_REFCTRL_ADJ_ADC                 13
+#define BM_AUDIOOUT_REFCTRL_ADJ_ADC                 0x2000
+#define BF_AUDIOOUT_REFCTRL_ADJ_ADC(v)              (((v) & 0x1) << 13)
+#define BFM_AUDIOOUT_REFCTRL_ADJ_ADC(v)             BM_AUDIOOUT_REFCTRL_ADJ_ADC
+#define BF_AUDIOOUT_REFCTRL_ADJ_ADC_V(e)            BF_AUDIOOUT_REFCTRL_ADJ_ADC(BV_AUDIOOUT_REFCTRL_ADJ_ADC__##e)
+#define BFM_AUDIOOUT_REFCTRL_ADJ_ADC_V(v)           BM_AUDIOOUT_REFCTRL_ADJ_ADC
+#define BP_AUDIOOUT_REFCTRL_ADJ_VAG                 12
+#define BM_AUDIOOUT_REFCTRL_ADJ_VAG                 0x1000
+#define BF_AUDIOOUT_REFCTRL_ADJ_VAG(v)              (((v) & 0x1) << 12)
+#define BFM_AUDIOOUT_REFCTRL_ADJ_VAG(v)             BM_AUDIOOUT_REFCTRL_ADJ_VAG
+#define BF_AUDIOOUT_REFCTRL_ADJ_VAG_V(e)            BF_AUDIOOUT_REFCTRL_ADJ_VAG(BV_AUDIOOUT_REFCTRL_ADJ_VAG__##e)
+#define BFM_AUDIOOUT_REFCTRL_ADJ_VAG_V(v)           BM_AUDIOOUT_REFCTRL_ADJ_VAG
+#define BP_AUDIOOUT_REFCTRL_ADC_REFVAL              8
+#define BM_AUDIOOUT_REFCTRL_ADC_REFVAL              0xf00
+#define BF_AUDIOOUT_REFCTRL_ADC_REFVAL(v)           (((v) & 0xf) << 8)
+#define BFM_AUDIOOUT_REFCTRL_ADC_REFVAL(v)          BM_AUDIOOUT_REFCTRL_ADC_REFVAL
+#define BF_AUDIOOUT_REFCTRL_ADC_REFVAL_V(e)         BF_AUDIOOUT_REFCTRL_ADC_REFVAL(BV_AUDIOOUT_REFCTRL_ADC_REFVAL__##e)
+#define BFM_AUDIOOUT_REFCTRL_ADC_REFVAL_V(v)        BM_AUDIOOUT_REFCTRL_ADC_REFVAL
+#define BP_AUDIOOUT_REFCTRL_VAG_VAL                 4
+#define BM_AUDIOOUT_REFCTRL_VAG_VAL                 0xf0
+#define BF_AUDIOOUT_REFCTRL_VAG_VAL(v)              (((v) & 0xf) << 4)
+#define BFM_AUDIOOUT_REFCTRL_VAG_VAL(v)             BM_AUDIOOUT_REFCTRL_VAG_VAL
+#define BF_AUDIOOUT_REFCTRL_VAG_VAL_V(e)            BF_AUDIOOUT_REFCTRL_VAG_VAL(BV_AUDIOOUT_REFCTRL_VAG_VAL__##e)
+#define BFM_AUDIOOUT_REFCTRL_VAG_VAL_V(v)           BM_AUDIOOUT_REFCTRL_VAG_VAL
+#define BP_AUDIOOUT_REFCTRL_DAC_ADJ                 0
+#define BM_AUDIOOUT_REFCTRL_DAC_ADJ                 0x7
+#define BF_AUDIOOUT_REFCTRL_DAC_ADJ(v)              (((v) & 0x7) << 0)
+#define BFM_AUDIOOUT_REFCTRL_DAC_ADJ(v)             BM_AUDIOOUT_REFCTRL_DAC_ADJ
+#define BF_AUDIOOUT_REFCTRL_DAC_ADJ_V(e)            BF_AUDIOOUT_REFCTRL_DAC_ADJ(BV_AUDIOOUT_REFCTRL_DAC_ADJ__##e)
+#define BFM_AUDIOOUT_REFCTRL_DAC_ADJ_V(v)           BM_AUDIOOUT_REFCTRL_DAC_ADJ
+
+#define HW_AUDIOOUT_ANACTRL                     HW(AUDIOOUT_ANACTRL)
+#define HWA_AUDIOOUT_ANACTRL                    (0x80048000 + 0x90)
+#define HWT_AUDIOOUT_ANACTRL                    HWIO_32_RW
+#define HWN_AUDIOOUT_ANACTRL                    AUDIOOUT_ANACTRL
+#define HWI_AUDIOOUT_ANACTRL                    
+#define HW_AUDIOOUT_ANACTRL_SET                 HW(AUDIOOUT_ANACTRL_SET)
+#define HWA_AUDIOOUT_ANACTRL_SET                (HWA_AUDIOOUT_ANACTRL + 0x4)
+#define HWT_AUDIOOUT_ANACTRL_SET                HWIO_32_WO
+#define HWN_AUDIOOUT_ANACTRL_SET                AUDIOOUT_ANACTRL
+#define HWI_AUDIOOUT_ANACTRL_SET                
+#define HW_AUDIOOUT_ANACTRL_CLR                 HW(AUDIOOUT_ANACTRL_CLR)
+#define HWA_AUDIOOUT_ANACTRL_CLR                (HWA_AUDIOOUT_ANACTRL + 0x8)
+#define HWT_AUDIOOUT_ANACTRL_CLR                HWIO_32_WO
+#define HWN_AUDIOOUT_ANACTRL_CLR                AUDIOOUT_ANACTRL
+#define HWI_AUDIOOUT_ANACTRL_CLR                
+#define HW_AUDIOOUT_ANACTRL_TOG                 HW(AUDIOOUT_ANACTRL_TOG)
+#define HWA_AUDIOOUT_ANACTRL_TOG                (HWA_AUDIOOUT_ANACTRL + 0xc)
+#define HWT_AUDIOOUT_ANACTRL_TOG                HWIO_32_WO
+#define HWN_AUDIOOUT_ANACTRL_TOG                AUDIOOUT_ANACTRL
+#define HWI_AUDIOOUT_ANACTRL_TOG                
+#define BP_AUDIOOUT_ANACTRL_SHORT_CM_STS        28
+#define BM_AUDIOOUT_ANACTRL_SHORT_CM_STS        0x10000000
+#define BF_AUDIOOUT_ANACTRL_SHORT_CM_STS(v)     (((v) & 0x1) << 28)
+#define BFM_AUDIOOUT_ANACTRL_SHORT_CM_STS(v)    BM_AUDIOOUT_ANACTRL_SHORT_CM_STS
+#define BF_AUDIOOUT_ANACTRL_SHORT_CM_STS_V(e)   BF_AUDIOOUT_ANACTRL_SHORT_CM_STS(BV_AUDIOOUT_ANACTRL_SHORT_CM_STS__##e)
+#define BFM_AUDIOOUT_ANACTRL_SHORT_CM_STS_V(v)  BM_AUDIOOUT_ANACTRL_SHORT_CM_STS
+#define BP_AUDIOOUT_ANACTRL_SHORT_LR_STS        24
+#define BM_AUDIOOUT_ANACTRL_SHORT_LR_STS        0x1000000
+#define BF_AUDIOOUT_ANACTRL_SHORT_LR_STS(v)     (((v) & 0x1) << 24)
+#define BFM_AUDIOOUT_ANACTRL_SHORT_LR_STS(v)    BM_AUDIOOUT_ANACTRL_SHORT_LR_STS
+#define BF_AUDIOOUT_ANACTRL_SHORT_LR_STS_V(e)   BF_AUDIOOUT_ANACTRL_SHORT_LR_STS(BV_AUDIOOUT_ANACTRL_SHORT_LR_STS__##e)
+#define BFM_AUDIOOUT_ANACTRL_SHORT_LR_STS_V(v)  BM_AUDIOOUT_ANACTRL_SHORT_LR_STS
+#define BP_AUDIOOUT_ANACTRL_SHORTMODE_CM        20
+#define BM_AUDIOOUT_ANACTRL_SHORTMODE_CM        0x300000
+#define BF_AUDIOOUT_ANACTRL_SHORTMODE_CM(v)     (((v) & 0x3) << 20)
+#define BFM_AUDIOOUT_ANACTRL_SHORTMODE_CM(v)    BM_AUDIOOUT_ANACTRL_SHORTMODE_CM
+#define BF_AUDIOOUT_ANACTRL_SHORTMODE_CM_V(e)   BF_AUDIOOUT_ANACTRL_SHORTMODE_CM(BV_AUDIOOUT_ANACTRL_SHORTMODE_CM__##e)
+#define BFM_AUDIOOUT_ANACTRL_SHORTMODE_CM_V(v)  BM_AUDIOOUT_ANACTRL_SHORTMODE_CM
+#define BP_AUDIOOUT_ANACTRL_SHORTMODE_LR        17
+#define BM_AUDIOOUT_ANACTRL_SHORTMODE_LR        0x60000
+#define BF_AUDIOOUT_ANACTRL_SHORTMODE_LR(v)     (((v) & 0x3) << 17)
+#define BFM_AUDIOOUT_ANACTRL_SHORTMODE_LR(v)    BM_AUDIOOUT_ANACTRL_SHORTMODE_LR
+#define BF_AUDIOOUT_ANACTRL_SHORTMODE_LR_V(e)   BF_AUDIOOUT_ANACTRL_SHORTMODE_LR(BV_AUDIOOUT_ANACTRL_SHORTMODE_LR__##e)
+#define BFM_AUDIOOUT_ANACTRL_SHORTMODE_LR_V(v)  BM_AUDIOOUT_ANACTRL_SHORTMODE_LR
+#define BP_AUDIOOUT_ANACTRL_SHORT_LVLADJL       12
+#define BM_AUDIOOUT_ANACTRL_SHORT_LVLADJL       0x7000
+#define BF_AUDIOOUT_ANACTRL_SHORT_LVLADJL(v)    (((v) & 0x7) << 12)
+#define BFM_AUDIOOUT_ANACTRL_SHORT_LVLADJL(v)   BM_AUDIOOUT_ANACTRL_SHORT_LVLADJL
+#define BF_AUDIOOUT_ANACTRL_SHORT_LVLADJL_V(e)  BF_AUDIOOUT_ANACTRL_SHORT_LVLADJL(BV_AUDIOOUT_ANACTRL_SHORT_LVLADJL__##e)
+#define BFM_AUDIOOUT_ANACTRL_SHORT_LVLADJL_V(v) BM_AUDIOOUT_ANACTRL_SHORT_LVLADJL
+#define BP_AUDIOOUT_ANACTRL_SHORT_LVLADJR       8
+#define BM_AUDIOOUT_ANACTRL_SHORT_LVLADJR       0x700
+#define BF_AUDIOOUT_ANACTRL_SHORT_LVLADJR(v)    (((v) & 0x7) << 8)
+#define BFM_AUDIOOUT_ANACTRL_SHORT_LVLADJR(v)   BM_AUDIOOUT_ANACTRL_SHORT_LVLADJR
+#define BF_AUDIOOUT_ANACTRL_SHORT_LVLADJR_V(e)  BF_AUDIOOUT_ANACTRL_SHORT_LVLADJR(BV_AUDIOOUT_ANACTRL_SHORT_LVLADJR__##e)
+#define BFM_AUDIOOUT_ANACTRL_SHORT_LVLADJR_V(v) BM_AUDIOOUT_ANACTRL_SHORT_LVLADJR
+#define BP_AUDIOOUT_ANACTRL_HP_HOLD_GND         5
+#define BM_AUDIOOUT_ANACTRL_HP_HOLD_GND         0x20
+#define BF_AUDIOOUT_ANACTRL_HP_HOLD_GND(v)      (((v) & 0x1) << 5)
+#define BFM_AUDIOOUT_ANACTRL_HP_HOLD_GND(v)     BM_AUDIOOUT_ANACTRL_HP_HOLD_GND
+#define BF_AUDIOOUT_ANACTRL_HP_HOLD_GND_V(e)    BF_AUDIOOUT_ANACTRL_HP_HOLD_GND(BV_AUDIOOUT_ANACTRL_HP_HOLD_GND__##e)
+#define BFM_AUDIOOUT_ANACTRL_HP_HOLD_GND_V(v)   BM_AUDIOOUT_ANACTRL_HP_HOLD_GND
+#define BP_AUDIOOUT_ANACTRL_HP_CLASSAB          4
+#define BM_AUDIOOUT_ANACTRL_HP_CLASSAB          0x10
+#define BF_AUDIOOUT_ANACTRL_HP_CLASSAB(v)       (((v) & 0x1) << 4)
+#define BFM_AUDIOOUT_ANACTRL_HP_CLASSAB(v)      BM_AUDIOOUT_ANACTRL_HP_CLASSAB
+#define BF_AUDIOOUT_ANACTRL_HP_CLASSAB_V(e)     BF_AUDIOOUT_ANACTRL_HP_CLASSAB(BV_AUDIOOUT_ANACTRL_HP_CLASSAB__##e)
+#define BFM_AUDIOOUT_ANACTRL_HP_CLASSAB_V(v)    BM_AUDIOOUT_ANACTRL_HP_CLASSAB
+
+#define HW_AUDIOOUT_TEST                        HW(AUDIOOUT_TEST)
+#define HWA_AUDIOOUT_TEST                       (0x80048000 + 0xa0)
+#define HWT_AUDIOOUT_TEST                       HWIO_32_RW
+#define HWN_AUDIOOUT_TEST                       AUDIOOUT_TEST
+#define HWI_AUDIOOUT_TEST                       
+#define HW_AUDIOOUT_TEST_SET                    HW(AUDIOOUT_TEST_SET)
+#define HWA_AUDIOOUT_TEST_SET                   (HWA_AUDIOOUT_TEST + 0x4)
+#define HWT_AUDIOOUT_TEST_SET                   HWIO_32_WO
+#define HWN_AUDIOOUT_TEST_SET                   AUDIOOUT_TEST
+#define HWI_AUDIOOUT_TEST_SET                   
+#define HW_AUDIOOUT_TEST_CLR                    HW(AUDIOOUT_TEST_CLR)
+#define HWA_AUDIOOUT_TEST_CLR                   (HWA_AUDIOOUT_TEST + 0x8)
+#define HWT_AUDIOOUT_TEST_CLR                   HWIO_32_WO
+#define HWN_AUDIOOUT_TEST_CLR                   AUDIOOUT_TEST
+#define HWI_AUDIOOUT_TEST_CLR                   
+#define HW_AUDIOOUT_TEST_TOG                    HW(AUDIOOUT_TEST_TOG)
+#define HWA_AUDIOOUT_TEST_TOG                   (HWA_AUDIOOUT_TEST + 0xc)
+#define HWT_AUDIOOUT_TEST_TOG                   HWIO_32_WO
+#define HWN_AUDIOOUT_TEST_TOG                   AUDIOOUT_TEST
+#define HWI_AUDIOOUT_TEST_TOG                   
+#define BP_AUDIOOUT_TEST_HP_ANTIPOP             28
+#define BM_AUDIOOUT_TEST_HP_ANTIPOP             0x70000000
+#define BF_AUDIOOUT_TEST_HP_ANTIPOP(v)          (((v) & 0x7) << 28)
+#define BFM_AUDIOOUT_TEST_HP_ANTIPOP(v)         BM_AUDIOOUT_TEST_HP_ANTIPOP
+#define BF_AUDIOOUT_TEST_HP_ANTIPOP_V(e)        BF_AUDIOOUT_TEST_HP_ANTIPOP(BV_AUDIOOUT_TEST_HP_ANTIPOP__##e)
+#define BFM_AUDIOOUT_TEST_HP_ANTIPOP_V(v)       BM_AUDIOOUT_TEST_HP_ANTIPOP
+#define BP_AUDIOOUT_TEST_TM_ADCIN_TOHP          26
+#define BM_AUDIOOUT_TEST_TM_ADCIN_TOHP          0x4000000
+#define BF_AUDIOOUT_TEST_TM_ADCIN_TOHP(v)       (((v) & 0x1) << 26)
+#define BFM_AUDIOOUT_TEST_TM_ADCIN_TOHP(v)      BM_AUDIOOUT_TEST_TM_ADCIN_TOHP
+#define BF_AUDIOOUT_TEST_TM_ADCIN_TOHP_V(e)     BF_AUDIOOUT_TEST_TM_ADCIN_TOHP(BV_AUDIOOUT_TEST_TM_ADCIN_TOHP__##e)
+#define BFM_AUDIOOUT_TEST_TM_ADCIN_TOHP_V(v)    BM_AUDIOOUT_TEST_TM_ADCIN_TOHP
+#define BP_AUDIOOUT_TEST_TM_LINEOUT             25
+#define BM_AUDIOOUT_TEST_TM_LINEOUT             0x2000000
+#define BF_AUDIOOUT_TEST_TM_LINEOUT(v)          (((v) & 0x1) << 25)
+#define BFM_AUDIOOUT_TEST_TM_LINEOUT(v)         BM_AUDIOOUT_TEST_TM_LINEOUT
+#define BF_AUDIOOUT_TEST_TM_LINEOUT_V(e)        BF_AUDIOOUT_TEST_TM_LINEOUT(BV_AUDIOOUT_TEST_TM_LINEOUT__##e)
+#define BFM_AUDIOOUT_TEST_TM_LINEOUT_V(v)       BM_AUDIOOUT_TEST_TM_LINEOUT
+#define BP_AUDIOOUT_TEST_TM_HPCOMMON            24
+#define BM_AUDIOOUT_TEST_TM_HPCOMMON            0x1000000
+#define BF_AUDIOOUT_TEST_TM_HPCOMMON(v)         (((v) & 0x1) << 24)
+#define BFM_AUDIOOUT_TEST_TM_HPCOMMON(v)        BM_AUDIOOUT_TEST_TM_HPCOMMON
+#define BF_AUDIOOUT_TEST_TM_HPCOMMON_V(e)       BF_AUDIOOUT_TEST_TM_HPCOMMON(BV_AUDIOOUT_TEST_TM_HPCOMMON__##e)
+#define BFM_AUDIOOUT_TEST_TM_HPCOMMON_V(v)      BM_AUDIOOUT_TEST_TM_HPCOMMON
+#define BP_AUDIOOUT_TEST_HP_I1_ADJ              22
+#define BM_AUDIOOUT_TEST_HP_I1_ADJ              0xc00000
+#define BF_AUDIOOUT_TEST_HP_I1_ADJ(v)           (((v) & 0x3) << 22)
+#define BFM_AUDIOOUT_TEST_HP_I1_ADJ(v)          BM_AUDIOOUT_TEST_HP_I1_ADJ
+#define BF_AUDIOOUT_TEST_HP_I1_ADJ_V(e)         BF_AUDIOOUT_TEST_HP_I1_ADJ(BV_AUDIOOUT_TEST_HP_I1_ADJ__##e)
+#define BFM_AUDIOOUT_TEST_HP_I1_ADJ_V(v)        BM_AUDIOOUT_TEST_HP_I1_ADJ
+#define BP_AUDIOOUT_TEST_HP_IALL_ADJ            20
+#define BM_AUDIOOUT_TEST_HP_IALL_ADJ            0x300000
+#define BF_AUDIOOUT_TEST_HP_IALL_ADJ(v)         (((v) & 0x3) << 20)
+#define BFM_AUDIOOUT_TEST_HP_IALL_ADJ(v)        BM_AUDIOOUT_TEST_HP_IALL_ADJ
+#define BF_AUDIOOUT_TEST_HP_IALL_ADJ_V(e)       BF_AUDIOOUT_TEST_HP_IALL_ADJ(BV_AUDIOOUT_TEST_HP_IALL_ADJ__##e)
+#define BFM_AUDIOOUT_TEST_HP_IALL_ADJ_V(v)      BM_AUDIOOUT_TEST_HP_IALL_ADJ
+#define BP_AUDIOOUT_TEST_VAG_CLASSA             13
+#define BM_AUDIOOUT_TEST_VAG_CLASSA             0x2000
+#define BF_AUDIOOUT_TEST_VAG_CLASSA(v)          (((v) & 0x1) << 13)
+#define BFM_AUDIOOUT_TEST_VAG_CLASSA(v)         BM_AUDIOOUT_TEST_VAG_CLASSA
+#define BF_AUDIOOUT_TEST_VAG_CLASSA_V(e)        BF_AUDIOOUT_TEST_VAG_CLASSA(BV_AUDIOOUT_TEST_VAG_CLASSA__##e)
+#define BFM_AUDIOOUT_TEST_VAG_CLASSA_V(v)       BM_AUDIOOUT_TEST_VAG_CLASSA
+#define BP_AUDIOOUT_TEST_VAG_DOUBLE_I           12
+#define BM_AUDIOOUT_TEST_VAG_DOUBLE_I           0x1000
+#define BF_AUDIOOUT_TEST_VAG_DOUBLE_I(v)        (((v) & 0x1) << 12)
+#define BFM_AUDIOOUT_TEST_VAG_DOUBLE_I(v)       BM_AUDIOOUT_TEST_VAG_DOUBLE_I
+#define BF_AUDIOOUT_TEST_VAG_DOUBLE_I_V(e)      BF_AUDIOOUT_TEST_VAG_DOUBLE_I(BV_AUDIOOUT_TEST_VAG_DOUBLE_I__##e)
+#define BFM_AUDIOOUT_TEST_VAG_DOUBLE_I_V(v)     BM_AUDIOOUT_TEST_VAG_DOUBLE_I
+#define BP_AUDIOOUT_TEST_DAC_CLASSA             2
+#define BM_AUDIOOUT_TEST_DAC_CLASSA             0x4
+#define BF_AUDIOOUT_TEST_DAC_CLASSA(v)          (((v) & 0x1) << 2)
+#define BFM_AUDIOOUT_TEST_DAC_CLASSA(v)         BM_AUDIOOUT_TEST_DAC_CLASSA
+#define BF_AUDIOOUT_TEST_DAC_CLASSA_V(e)        BF_AUDIOOUT_TEST_DAC_CLASSA(BV_AUDIOOUT_TEST_DAC_CLASSA__##e)
+#define BFM_AUDIOOUT_TEST_DAC_CLASSA_V(v)       BM_AUDIOOUT_TEST_DAC_CLASSA
+#define BP_AUDIOOUT_TEST_DAC_DOUBLE_I           1
+#define BM_AUDIOOUT_TEST_DAC_DOUBLE_I           0x2
+#define BF_AUDIOOUT_TEST_DAC_DOUBLE_I(v)        (((v) & 0x1) << 1)
+#define BFM_AUDIOOUT_TEST_DAC_DOUBLE_I(v)       BM_AUDIOOUT_TEST_DAC_DOUBLE_I
+#define BF_AUDIOOUT_TEST_DAC_DOUBLE_I_V(e)      BF_AUDIOOUT_TEST_DAC_DOUBLE_I(BV_AUDIOOUT_TEST_DAC_DOUBLE_I__##e)
+#define BFM_AUDIOOUT_TEST_DAC_DOUBLE_I_V(v)     BM_AUDIOOUT_TEST_DAC_DOUBLE_I
+#define BP_AUDIOOUT_TEST_DAC_DIS_RTZ            0
+#define BM_AUDIOOUT_TEST_DAC_DIS_RTZ            0x1
+#define BF_AUDIOOUT_TEST_DAC_DIS_RTZ(v)         (((v) & 0x1) << 0)
+#define BFM_AUDIOOUT_TEST_DAC_DIS_RTZ(v)        BM_AUDIOOUT_TEST_DAC_DIS_RTZ
+#define BF_AUDIOOUT_TEST_DAC_DIS_RTZ_V(e)       BF_AUDIOOUT_TEST_DAC_DIS_RTZ(BV_AUDIOOUT_TEST_DAC_DIS_RTZ__##e)
+#define BFM_AUDIOOUT_TEST_DAC_DIS_RTZ_V(v)      BM_AUDIOOUT_TEST_DAC_DIS_RTZ
+
+#define HW_AUDIOOUT_BISTCTRL                HW(AUDIOOUT_BISTCTRL)
+#define HWA_AUDIOOUT_BISTCTRL               (0x80048000 + 0xb0)
+#define HWT_AUDIOOUT_BISTCTRL               HWIO_32_RW
+#define HWN_AUDIOOUT_BISTCTRL               AUDIOOUT_BISTCTRL
+#define HWI_AUDIOOUT_BISTCTRL               
+#define HW_AUDIOOUT_BISTCTRL_SET            HW(AUDIOOUT_BISTCTRL_SET)
+#define HWA_AUDIOOUT_BISTCTRL_SET           (HWA_AUDIOOUT_BISTCTRL + 0x4)
+#define HWT_AUDIOOUT_BISTCTRL_SET           HWIO_32_WO
+#define HWN_AUDIOOUT_BISTCTRL_SET           AUDIOOUT_BISTCTRL
+#define HWI_AUDIOOUT_BISTCTRL_SET           
+#define HW_AUDIOOUT_BISTCTRL_CLR            HW(AUDIOOUT_BISTCTRL_CLR)
+#define HWA_AUDIOOUT_BISTCTRL_CLR           (HWA_AUDIOOUT_BISTCTRL + 0x8)
+#define HWT_AUDIOOUT_BISTCTRL_CLR           HWIO_32_WO
+#define HWN_AUDIOOUT_BISTCTRL_CLR           AUDIOOUT_BISTCTRL
+#define HWI_AUDIOOUT_BISTCTRL_CLR           
+#define HW_AUDIOOUT_BISTCTRL_TOG            HW(AUDIOOUT_BISTCTRL_TOG)
+#define HWA_AUDIOOUT_BISTCTRL_TOG           (HWA_AUDIOOUT_BISTCTRL + 0xc)
+#define HWT_AUDIOOUT_BISTCTRL_TOG           HWIO_32_WO
+#define HWN_AUDIOOUT_BISTCTRL_TOG           AUDIOOUT_BISTCTRL
+#define HWI_AUDIOOUT_BISTCTRL_TOG           
+#define BP_AUDIOOUT_BISTCTRL_FAIL           3
+#define BM_AUDIOOUT_BISTCTRL_FAIL           0x8
+#define BF_AUDIOOUT_BISTCTRL_FAIL(v)        (((v) & 0x1) << 3)
+#define BFM_AUDIOOUT_BISTCTRL_FAIL(v)       BM_AUDIOOUT_BISTCTRL_FAIL
+#define BF_AUDIOOUT_BISTCTRL_FAIL_V(e)      BF_AUDIOOUT_BISTCTRL_FAIL(BV_AUDIOOUT_BISTCTRL_FAIL__##e)
+#define BFM_AUDIOOUT_BISTCTRL_FAIL_V(v)     BM_AUDIOOUT_BISTCTRL_FAIL
+#define BP_AUDIOOUT_BISTCTRL_PASS           2
+#define BM_AUDIOOUT_BISTCTRL_PASS           0x4
+#define BF_AUDIOOUT_BISTCTRL_PASS(v)        (((v) & 0x1) << 2)
+#define BFM_AUDIOOUT_BISTCTRL_PASS(v)       BM_AUDIOOUT_BISTCTRL_PASS
+#define BF_AUDIOOUT_BISTCTRL_PASS_V(e)      BF_AUDIOOUT_BISTCTRL_PASS(BV_AUDIOOUT_BISTCTRL_PASS__##e)
+#define BFM_AUDIOOUT_BISTCTRL_PASS_V(v)     BM_AUDIOOUT_BISTCTRL_PASS
+#define BP_AUDIOOUT_BISTCTRL_DONE           1
+#define BM_AUDIOOUT_BISTCTRL_DONE           0x2
+#define BF_AUDIOOUT_BISTCTRL_DONE(v)        (((v) & 0x1) << 1)
+#define BFM_AUDIOOUT_BISTCTRL_DONE(v)       BM_AUDIOOUT_BISTCTRL_DONE
+#define BF_AUDIOOUT_BISTCTRL_DONE_V(e)      BF_AUDIOOUT_BISTCTRL_DONE(BV_AUDIOOUT_BISTCTRL_DONE__##e)
+#define BFM_AUDIOOUT_BISTCTRL_DONE_V(v)     BM_AUDIOOUT_BISTCTRL_DONE
+#define BP_AUDIOOUT_BISTCTRL_START          0
+#define BM_AUDIOOUT_BISTCTRL_START          0x1
+#define BF_AUDIOOUT_BISTCTRL_START(v)       (((v) & 0x1) << 0)
+#define BFM_AUDIOOUT_BISTCTRL_START(v)      BM_AUDIOOUT_BISTCTRL_START
+#define BF_AUDIOOUT_BISTCTRL_START_V(e)     BF_AUDIOOUT_BISTCTRL_START(BV_AUDIOOUT_BISTCTRL_START__##e)
+#define BFM_AUDIOOUT_BISTCTRL_START_V(v)    BM_AUDIOOUT_BISTCTRL_START
+
+#define HW_AUDIOOUT_BISTSTAT0               HW(AUDIOOUT_BISTSTAT0)
+#define HWA_AUDIOOUT_BISTSTAT0              (0x80048000 + 0xc0)
+#define HWT_AUDIOOUT_BISTSTAT0              HWIO_32_RW
+#define HWN_AUDIOOUT_BISTSTAT0              AUDIOOUT_BISTSTAT0
+#define HWI_AUDIOOUT_BISTSTAT0              
+#define BP_AUDIOOUT_BISTSTAT0_DATA          0
+#define BM_AUDIOOUT_BISTSTAT0_DATA          0xffffff
+#define BF_AUDIOOUT_BISTSTAT0_DATA(v)       (((v) & 0xffffff) << 0)
+#define BFM_AUDIOOUT_BISTSTAT0_DATA(v)      BM_AUDIOOUT_BISTSTAT0_DATA
+#define BF_AUDIOOUT_BISTSTAT0_DATA_V(e)     BF_AUDIOOUT_BISTSTAT0_DATA(BV_AUDIOOUT_BISTSTAT0_DATA__##e)
+#define BFM_AUDIOOUT_BISTSTAT0_DATA_V(v)    BM_AUDIOOUT_BISTSTAT0_DATA
+
+#define HW_AUDIOOUT_BISTSTAT1               HW(AUDIOOUT_BISTSTAT1)
+#define HWA_AUDIOOUT_BISTSTAT1              (0x80048000 + 0xd0)
+#define HWT_AUDIOOUT_BISTSTAT1              HWIO_32_RW
+#define HWN_AUDIOOUT_BISTSTAT1              AUDIOOUT_BISTSTAT1
+#define HWI_AUDIOOUT_BISTSTAT1              
+#define BP_AUDIOOUT_BISTSTAT1_STATE         24
+#define BM_AUDIOOUT_BISTSTAT1_STATE         0x1f000000
+#define BF_AUDIOOUT_BISTSTAT1_STATE(v)      (((v) & 0x1f) << 24)
+#define BFM_AUDIOOUT_BISTSTAT1_STATE(v)     BM_AUDIOOUT_BISTSTAT1_STATE
+#define BF_AUDIOOUT_BISTSTAT1_STATE_V(e)    BF_AUDIOOUT_BISTSTAT1_STATE(BV_AUDIOOUT_BISTSTAT1_STATE__##e)
+#define BFM_AUDIOOUT_BISTSTAT1_STATE_V(v)   BM_AUDIOOUT_BISTSTAT1_STATE
+#define BP_AUDIOOUT_BISTSTAT1_ADDR          0
+#define BM_AUDIOOUT_BISTSTAT1_ADDR          0xff
+#define BF_AUDIOOUT_BISTSTAT1_ADDR(v)       (((v) & 0xff) << 0)
+#define BFM_AUDIOOUT_BISTSTAT1_ADDR(v)      BM_AUDIOOUT_BISTSTAT1_ADDR
+#define BF_AUDIOOUT_BISTSTAT1_ADDR_V(e)     BF_AUDIOOUT_BISTSTAT1_ADDR(BV_AUDIOOUT_BISTSTAT1_ADDR__##e)
+#define BFM_AUDIOOUT_BISTSTAT1_ADDR_V(v)    BM_AUDIOOUT_BISTSTAT1_ADDR
+
+#define HW_AUDIOOUT_ANACLKCTRL                      HW(AUDIOOUT_ANACLKCTRL)
+#define HWA_AUDIOOUT_ANACLKCTRL                     (0x80048000 + 0xe0)
+#define HWT_AUDIOOUT_ANACLKCTRL                     HWIO_32_RW
+#define HWN_AUDIOOUT_ANACLKCTRL                     AUDIOOUT_ANACLKCTRL
+#define HWI_AUDIOOUT_ANACLKCTRL                     
+#define HW_AUDIOOUT_ANACLKCTRL_SET                  HW(AUDIOOUT_ANACLKCTRL_SET)
+#define HWA_AUDIOOUT_ANACLKCTRL_SET                 (HWA_AUDIOOUT_ANACLKCTRL + 0x4)
+#define HWT_AUDIOOUT_ANACLKCTRL_SET                 HWIO_32_WO
+#define HWN_AUDIOOUT_ANACLKCTRL_SET                 AUDIOOUT_ANACLKCTRL
+#define HWI_AUDIOOUT_ANACLKCTRL_SET                 
+#define HW_AUDIOOUT_ANACLKCTRL_CLR                  HW(AUDIOOUT_ANACLKCTRL_CLR)
+#define HWA_AUDIOOUT_ANACLKCTRL_CLR                 (HWA_AUDIOOUT_ANACLKCTRL + 0x8)
+#define HWT_AUDIOOUT_ANACLKCTRL_CLR                 HWIO_32_WO
+#define HWN_AUDIOOUT_ANACLKCTRL_CLR                 AUDIOOUT_ANACLKCTRL
+#define HWI_AUDIOOUT_ANACLKCTRL_CLR                 
+#define HW_AUDIOOUT_ANACLKCTRL_TOG                  HW(AUDIOOUT_ANACLKCTRL_TOG)
+#define HWA_AUDIOOUT_ANACLKCTRL_TOG                 (HWA_AUDIOOUT_ANACLKCTRL + 0xc)
+#define HWT_AUDIOOUT_ANACLKCTRL_TOG                 HWIO_32_WO
+#define HWN_AUDIOOUT_ANACLKCTRL_TOG                 AUDIOOUT_ANACLKCTRL
+#define HWI_AUDIOOUT_ANACLKCTRL_TOG                 
+#define BP_AUDIOOUT_ANACLKCTRL_CLKGATE              31
+#define BM_AUDIOOUT_ANACLKCTRL_CLKGATE              0x80000000
+#define BF_AUDIOOUT_ANACLKCTRL_CLKGATE(v)           (((v) & 0x1) << 31)
+#define BFM_AUDIOOUT_ANACLKCTRL_CLKGATE(v)          BM_AUDIOOUT_ANACLKCTRL_CLKGATE
+#define BF_AUDIOOUT_ANACLKCTRL_CLKGATE_V(e)         BF_AUDIOOUT_ANACLKCTRL_CLKGATE(BV_AUDIOOUT_ANACLKCTRL_CLKGATE__##e)
+#define BFM_AUDIOOUT_ANACLKCTRL_CLKGATE_V(v)        BM_AUDIOOUT_ANACLKCTRL_CLKGATE
+#define BP_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK        4
+#define BM_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK        0x10
+#define BF_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK(v)     (((v) & 0x1) << 4)
+#define BFM_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK(v)    BM_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK
+#define BF_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK_V(e)   BF_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK(BV_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK__##e)
+#define BFM_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK_V(v)  BM_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK
+#define BP_AUDIOOUT_ANACLKCTRL_DACDIV               0
+#define BM_AUDIOOUT_ANACLKCTRL_DACDIV               0x7
+#define BF_AUDIOOUT_ANACLKCTRL_DACDIV(v)            (((v) & 0x7) << 0)
+#define BFM_AUDIOOUT_ANACLKCTRL_DACDIV(v)           BM_AUDIOOUT_ANACLKCTRL_DACDIV
+#define BF_AUDIOOUT_ANACLKCTRL_DACDIV_V(e)          BF_AUDIOOUT_ANACLKCTRL_DACDIV(BV_AUDIOOUT_ANACLKCTRL_DACDIV__##e)
+#define BFM_AUDIOOUT_ANACLKCTRL_DACDIV_V(v)         BM_AUDIOOUT_ANACLKCTRL_DACDIV
+
+#define HW_AUDIOOUT_DATA            HW(AUDIOOUT_DATA)
+#define HWA_AUDIOOUT_DATA           (0x80048000 + 0xf0)
+#define HWT_AUDIOOUT_DATA           HWIO_32_RW
+#define HWN_AUDIOOUT_DATA           AUDIOOUT_DATA
+#define HWI_AUDIOOUT_DATA           
+#define HW_AUDIOOUT_DATA_SET        HW(AUDIOOUT_DATA_SET)
+#define HWA_AUDIOOUT_DATA_SET       (HWA_AUDIOOUT_DATA + 0x4)
+#define HWT_AUDIOOUT_DATA_SET       HWIO_32_WO
+#define HWN_AUDIOOUT_DATA_SET       AUDIOOUT_DATA
+#define HWI_AUDIOOUT_DATA_SET       
+#define HW_AUDIOOUT_DATA_CLR        HW(AUDIOOUT_DATA_CLR)
+#define HWA_AUDIOOUT_DATA_CLR       (HWA_AUDIOOUT_DATA + 0x8)
+#define HWT_AUDIOOUT_DATA_CLR       HWIO_32_WO
+#define HWN_AUDIOOUT_DATA_CLR       AUDIOOUT_DATA
+#define HWI_AUDIOOUT_DATA_CLR       
+#define HW_AUDIOOUT_DATA_TOG        HW(AUDIOOUT_DATA_TOG)
+#define HWA_AUDIOOUT_DATA_TOG       (HWA_AUDIOOUT_DATA + 0xc)
+#define HWT_AUDIOOUT_DATA_TOG       HWIO_32_WO
+#define HWN_AUDIOOUT_DATA_TOG       AUDIOOUT_DATA
+#define HWI_AUDIOOUT_DATA_TOG       
+#define BP_AUDIOOUT_DATA_HIGH       16
+#define BM_AUDIOOUT_DATA_HIGH       0xffff0000
+#define BF_AUDIOOUT_DATA_HIGH(v)    (((v) & 0xffff) << 16)
+#define BFM_AUDIOOUT_DATA_HIGH(v)   BM_AUDIOOUT_DATA_HIGH
+#define BF_AUDIOOUT_DATA_HIGH_V(e)  BF_AUDIOOUT_DATA_HIGH(BV_AUDIOOUT_DATA_HIGH__##e)
+#define BFM_AUDIOOUT_DATA_HIGH_V(v) BM_AUDIOOUT_DATA_HIGH
+#define BP_AUDIOOUT_DATA_LOW        0
+#define BM_AUDIOOUT_DATA_LOW        0xffff
+#define BF_AUDIOOUT_DATA_LOW(v)     (((v) & 0xffff) << 0)
+#define BFM_AUDIOOUT_DATA_LOW(v)    BM_AUDIOOUT_DATA_LOW
+#define BF_AUDIOOUT_DATA_LOW_V(e)   BF_AUDIOOUT_DATA_LOW(BV_AUDIOOUT_DATA_LOW__##e)
+#define BFM_AUDIOOUT_DATA_LOW_V(v)  BM_AUDIOOUT_DATA_LOW
+
+#define HW_AUDIOOUT_LINEOUTCTRL                             HW(AUDIOOUT_LINEOUTCTRL)
+#define HWA_AUDIOOUT_LINEOUTCTRL                            (0x80048000 + 0x100)
+#define HWT_AUDIOOUT_LINEOUTCTRL                            HWIO_32_RW
+#define HWN_AUDIOOUT_LINEOUTCTRL                            AUDIOOUT_LINEOUTCTRL
+#define HWI_AUDIOOUT_LINEOUTCTRL                            
+#define HW_AUDIOOUT_LINEOUTCTRL_SET                         HW(AUDIOOUT_LINEOUTCTRL_SET)
+#define HWA_AUDIOOUT_LINEOUTCTRL_SET                        (HWA_AUDIOOUT_LINEOUTCTRL + 0x4)
+#define HWT_AUDIOOUT_LINEOUTCTRL_SET                        HWIO_32_WO
+#define HWN_AUDIOOUT_LINEOUTCTRL_SET                        AUDIOOUT_LINEOUTCTRL
+#define HWI_AUDIOOUT_LINEOUTCTRL_SET                        
+#define HW_AUDIOOUT_LINEOUTCTRL_CLR                         HW(AUDIOOUT_LINEOUTCTRL_CLR)
+#define HWA_AUDIOOUT_LINEOUTCTRL_CLR                        (HWA_AUDIOOUT_LINEOUTCTRL + 0x8)
+#define HWT_AUDIOOUT_LINEOUTCTRL_CLR                        HWIO_32_WO
+#define HWN_AUDIOOUT_LINEOUTCTRL_CLR                        AUDIOOUT_LINEOUTCTRL
+#define HWI_AUDIOOUT_LINEOUTCTRL_CLR                        
+#define HW_AUDIOOUT_LINEOUTCTRL_TOG                         HW(AUDIOOUT_LINEOUTCTRL_TOG)
+#define HWA_AUDIOOUT_LINEOUTCTRL_TOG                        (HWA_AUDIOOUT_LINEOUTCTRL + 0xc)
+#define HWT_AUDIOOUT_LINEOUTCTRL_TOG                        HWIO_32_WO
+#define HWN_AUDIOOUT_LINEOUTCTRL_TOG                        AUDIOOUT_LINEOUTCTRL
+#define HWI_AUDIOOUT_LINEOUTCTRL_TOG                        
+#define BP_AUDIOOUT_LINEOUTCTRL_VOLUME_UPDATE_PENDING       28
+#define BM_AUDIOOUT_LINEOUTCTRL_VOLUME_UPDATE_PENDING       0x10000000
+#define BF_AUDIOOUT_LINEOUTCTRL_VOLUME_UPDATE_PENDING(v)    (((v) & 0x1) << 28)
+#define BFM_AUDIOOUT_LINEOUTCTRL_VOLUME_UPDATE_PENDING(v)   BM_AUDIOOUT_LINEOUTCTRL_VOLUME_UPDATE_PENDING
+#define BF_AUDIOOUT_LINEOUTCTRL_VOLUME_UPDATE_PENDING_V(e)  BF_AUDIOOUT_LINEOUTCTRL_VOLUME_UPDATE_PENDING(BV_AUDIOOUT_LINEOUTCTRL_VOLUME_UPDATE_PENDING__##e)
+#define BFM_AUDIOOUT_LINEOUTCTRL_VOLUME_UPDATE_PENDING_V(v) BM_AUDIOOUT_LINEOUTCTRL_VOLUME_UPDATE_PENDING
+#define BP_AUDIOOUT_LINEOUTCTRL_EN_LINEOUT_ZCD              25
+#define BM_AUDIOOUT_LINEOUTCTRL_EN_LINEOUT_ZCD              0x2000000
+#define BF_AUDIOOUT_LINEOUTCTRL_EN_LINEOUT_ZCD(v)           (((v) & 0x1) << 25)
+#define BFM_AUDIOOUT_LINEOUTCTRL_EN_LINEOUT_ZCD(v)          BM_AUDIOOUT_LINEOUTCTRL_EN_LINEOUT_ZCD
+#define BF_AUDIOOUT_LINEOUTCTRL_EN_LINEOUT_ZCD_V(e)         BF_AUDIOOUT_LINEOUTCTRL_EN_LINEOUT_ZCD(BV_AUDIOOUT_LINEOUTCTRL_EN_LINEOUT_ZCD__##e)
+#define BFM_AUDIOOUT_LINEOUTCTRL_EN_LINEOUT_ZCD_V(v)        BM_AUDIOOUT_LINEOUTCTRL_EN_LINEOUT_ZCD
+#define BP_AUDIOOUT_LINEOUTCTRL_MUTE                        24
+#define BM_AUDIOOUT_LINEOUTCTRL_MUTE                        0x1000000
+#define BF_AUDIOOUT_LINEOUTCTRL_MUTE(v)                     (((v) & 0x1) << 24)
+#define BFM_AUDIOOUT_LINEOUTCTRL_MUTE(v)                    BM_AUDIOOUT_LINEOUTCTRL_MUTE
+#define BF_AUDIOOUT_LINEOUTCTRL_MUTE_V(e)                   BF_AUDIOOUT_LINEOUTCTRL_MUTE(BV_AUDIOOUT_LINEOUTCTRL_MUTE__##e)
+#define BFM_AUDIOOUT_LINEOUTCTRL_MUTE_V(v)                  BM_AUDIOOUT_LINEOUTCTRL_MUTE
+#define BP_AUDIOOUT_LINEOUTCTRL_VAG_CTRL                    20
+#define BM_AUDIOOUT_LINEOUTCTRL_VAG_CTRL                    0xf00000
+#define BF_AUDIOOUT_LINEOUTCTRL_VAG_CTRL(v)                 (((v) & 0xf) << 20)
+#define BFM_AUDIOOUT_LINEOUTCTRL_VAG_CTRL(v)                BM_AUDIOOUT_LINEOUTCTRL_VAG_CTRL
+#define BF_AUDIOOUT_LINEOUTCTRL_VAG_CTRL_V(e)               BF_AUDIOOUT_LINEOUTCTRL_VAG_CTRL(BV_AUDIOOUT_LINEOUTCTRL_VAG_CTRL__##e)
+#define BFM_AUDIOOUT_LINEOUTCTRL_VAG_CTRL_V(v)              BM_AUDIOOUT_LINEOUTCTRL_VAG_CTRL
+#define BP_AUDIOOUT_LINEOUTCTRL_OUT_CURRENT                 16
+#define BM_AUDIOOUT_LINEOUTCTRL_OUT_CURRENT                 0xf0000
+#define BF_AUDIOOUT_LINEOUTCTRL_OUT_CURRENT(v)              (((v) & 0xf) << 16)
+#define BFM_AUDIOOUT_LINEOUTCTRL_OUT_CURRENT(v)             BM_AUDIOOUT_LINEOUTCTRL_OUT_CURRENT
+#define BF_AUDIOOUT_LINEOUTCTRL_OUT_CURRENT_V(e)            BF_AUDIOOUT_LINEOUTCTRL_OUT_CURRENT(BV_AUDIOOUT_LINEOUTCTRL_OUT_CURRENT__##e)
+#define BFM_AUDIOOUT_LINEOUTCTRL_OUT_CURRENT_V(v)           BM_AUDIOOUT_LINEOUTCTRL_OUT_CURRENT
+#define BP_AUDIOOUT_LINEOUTCTRL_CHARGE_CAP                  13
+#define BM_AUDIOOUT_LINEOUTCTRL_CHARGE_CAP                  0xe000
+#define BF_AUDIOOUT_LINEOUTCTRL_CHARGE_CAP(v)               (((v) & 0x7) << 13)
+#define BFM_AUDIOOUT_LINEOUTCTRL_CHARGE_CAP(v)              BM_AUDIOOUT_LINEOUTCTRL_CHARGE_CAP
+#define BF_AUDIOOUT_LINEOUTCTRL_CHARGE_CAP_V(e)             BF_AUDIOOUT_LINEOUTCTRL_CHARGE_CAP(BV_AUDIOOUT_LINEOUTCTRL_CHARGE_CAP__##e)
+#define BFM_AUDIOOUT_LINEOUTCTRL_CHARGE_CAP_V(v)            BM_AUDIOOUT_LINEOUTCTRL_CHARGE_CAP
+#define BP_AUDIOOUT_LINEOUTCTRL_VOLUME_LEFT                 8
+#define BM_AUDIOOUT_LINEOUTCTRL_VOLUME_LEFT                 0x1f00
+#define BF_AUDIOOUT_LINEOUTCTRL_VOLUME_LEFT(v)              (((v) & 0x1f) << 8)
+#define BFM_AUDIOOUT_LINEOUTCTRL_VOLUME_LEFT(v)             BM_AUDIOOUT_LINEOUTCTRL_VOLUME_LEFT
+#define BF_AUDIOOUT_LINEOUTCTRL_VOLUME_LEFT_V(e)            BF_AUDIOOUT_LINEOUTCTRL_VOLUME_LEFT(BV_AUDIOOUT_LINEOUTCTRL_VOLUME_LEFT__##e)
+#define BFM_AUDIOOUT_LINEOUTCTRL_VOLUME_LEFT_V(v)           BM_AUDIOOUT_LINEOUTCTRL_VOLUME_LEFT
+#define BP_AUDIOOUT_LINEOUTCTRL_VOLUME_RIGHT                0
+#define BM_AUDIOOUT_LINEOUTCTRL_VOLUME_RIGHT                0x1f
+#define BF_AUDIOOUT_LINEOUTCTRL_VOLUME_RIGHT(v)             (((v) & 0x1f) << 0)
+#define BFM_AUDIOOUT_LINEOUTCTRL_VOLUME_RIGHT(v)            BM_AUDIOOUT_LINEOUTCTRL_VOLUME_RIGHT
+#define BF_AUDIOOUT_LINEOUTCTRL_VOLUME_RIGHT_V(e)           BF_AUDIOOUT_LINEOUTCTRL_VOLUME_RIGHT(BV_AUDIOOUT_LINEOUTCTRL_VOLUME_RIGHT__##e)
+#define BFM_AUDIOOUT_LINEOUTCTRL_VOLUME_RIGHT_V(v)          BM_AUDIOOUT_LINEOUTCTRL_VOLUME_RIGHT
+
+#define HW_AUDIOOUT_VERSION             HW(AUDIOOUT_VERSION)
+#define HWA_AUDIOOUT_VERSION            (0x80048000 + 0x200)
+#define HWT_AUDIOOUT_VERSION            HWIO_32_RW
+#define HWN_AUDIOOUT_VERSION            AUDIOOUT_VERSION
+#define HWI_AUDIOOUT_VERSION            
+#define BP_AUDIOOUT_VERSION_MAJOR       24
+#define BM_AUDIOOUT_VERSION_MAJOR       0xff000000
+#define BF_AUDIOOUT_VERSION_MAJOR(v)    (((v) & 0xff) << 24)
+#define BFM_AUDIOOUT_VERSION_MAJOR(v)   BM_AUDIOOUT_VERSION_MAJOR
+#define BF_AUDIOOUT_VERSION_MAJOR_V(e)  BF_AUDIOOUT_VERSION_MAJOR(BV_AUDIOOUT_VERSION_MAJOR__##e)
+#define BFM_AUDIOOUT_VERSION_MAJOR_V(v) BM_AUDIOOUT_VERSION_MAJOR
+#define BP_AUDIOOUT_VERSION_MINOR       16
+#define BM_AUDIOOUT_VERSION_MINOR       0xff0000
+#define BF_AUDIOOUT_VERSION_MINOR(v)    (((v) & 0xff) << 16)
+#define BFM_AUDIOOUT_VERSION_MINOR(v)   BM_AUDIOOUT_VERSION_MINOR
+#define BF_AUDIOOUT_VERSION_MINOR_V(e)  BF_AUDIOOUT_VERSION_MINOR(BV_AUDIOOUT_VERSION_MINOR__##e)
+#define BFM_AUDIOOUT_VERSION_MINOR_V(v) BM_AUDIOOUT_VERSION_MINOR
+#define BP_AUDIOOUT_VERSION_STEP        0
+#define BM_AUDIOOUT_VERSION_STEP        0xffff
+#define BF_AUDIOOUT_VERSION_STEP(v)     (((v) & 0xffff) << 0)
+#define BFM_AUDIOOUT_VERSION_STEP(v)    BM_AUDIOOUT_VERSION_STEP
+#define BF_AUDIOOUT_VERSION_STEP_V(e)   BF_AUDIOOUT_VERSION_STEP(BV_AUDIOOUT_VERSION_STEP__##e)
+#define BFM_AUDIOOUT_VERSION_STEP_V(v)  BM_AUDIOOUT_VERSION_STEP
+
+#endif /* __HEADERGEN_STMP3700_AUDIOOUT_H__*/
diff --git a/firmware/target/arm/imx233/regs/stmp3700/clkctrl.h b/firmware/target/arm/imx233/regs/stmp3700/clkctrl.h
new file mode 100644
index 0000000000..5be87c8b8f
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3700/clkctrl.h
@@ -0,0 +1,777 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * stmp3700 version: 2.4.0
+ * stmp3700 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_STMP3700_CLKCTRL_H__
+#define __HEADERGEN_STMP3700_CLKCTRL_H__
+
+#define HW_CLKCTRL_PLLCTRL0                     HW(CLKCTRL_PLLCTRL0)
+#define HWA_CLKCTRL_PLLCTRL0                    (0x80040000 + 0x0)
+#define HWT_CLKCTRL_PLLCTRL0                    HWIO_32_RW
+#define HWN_CLKCTRL_PLLCTRL0                    CLKCTRL_PLLCTRL0
+#define HWI_CLKCTRL_PLLCTRL0                    
+#define HW_CLKCTRL_PLLCTRL0_SET                 HW(CLKCTRL_PLLCTRL0_SET)
+#define HWA_CLKCTRL_PLLCTRL0_SET                (HWA_CLKCTRL_PLLCTRL0 + 0x4)
+#define HWT_CLKCTRL_PLLCTRL0_SET                HWIO_32_WO
+#define HWN_CLKCTRL_PLLCTRL0_SET                CLKCTRL_PLLCTRL0
+#define HWI_CLKCTRL_PLLCTRL0_SET                
+#define HW_CLKCTRL_PLLCTRL0_CLR                 HW(CLKCTRL_PLLCTRL0_CLR)
+#define HWA_CLKCTRL_PLLCTRL0_CLR                (HWA_CLKCTRL_PLLCTRL0 + 0x8)
+#define HWT_CLKCTRL_PLLCTRL0_CLR                HWIO_32_WO
+#define HWN_CLKCTRL_PLLCTRL0_CLR                CLKCTRL_PLLCTRL0
+#define HWI_CLKCTRL_PLLCTRL0_CLR                
+#define HW_CLKCTRL_PLLCTRL0_TOG                 HW(CLKCTRL_PLLCTRL0_TOG)
+#define HWA_CLKCTRL_PLLCTRL0_TOG                (HWA_CLKCTRL_PLLCTRL0 + 0xc)
+#define HWT_CLKCTRL_PLLCTRL0_TOG                HWIO_32_WO
+#define HWN_CLKCTRL_PLLCTRL0_TOG                CLKCTRL_PLLCTRL0
+#define HWI_CLKCTRL_PLLCTRL0_TOG                
+#define BP_CLKCTRL_PLLCTRL0_LFR_SEL             28
+#define BM_CLKCTRL_PLLCTRL0_LFR_SEL             0x30000000
+#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__DEFAULT    0x0
+#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_2    0x1
+#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_05   0x2
+#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__UNDEFINED  0x3
+#define BF_CLKCTRL_PLLCTRL0_LFR_SEL(v)          (((v) & 0x3) << 28)
+#define BFM_CLKCTRL_PLLCTRL0_LFR_SEL(v)         BM_CLKCTRL_PLLCTRL0_LFR_SEL
+#define BF_CLKCTRL_PLLCTRL0_LFR_SEL_V(e)        BF_CLKCTRL_PLLCTRL0_LFR_SEL(BV_CLKCTRL_PLLCTRL0_LFR_SEL__##e)
+#define BFM_CLKCTRL_PLLCTRL0_LFR_SEL_V(v)       BM_CLKCTRL_PLLCTRL0_LFR_SEL
+#define BP_CLKCTRL_PLLCTRL0_CP_SEL              24
+#define BM_CLKCTRL_PLLCTRL0_CP_SEL              0x3000000
+#define BV_CLKCTRL_PLLCTRL0_CP_SEL__DEFAULT     0x0
+#define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_2     0x1
+#define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_05    0x2
+#define BV_CLKCTRL_PLLCTRL0_CP_SEL__UNDEFINED   0x3
+#define BF_CLKCTRL_PLLCTRL0_CP_SEL(v)           (((v) & 0x3) << 24)
+#define BFM_CLKCTRL_PLLCTRL0_CP_SEL(v)          BM_CLKCTRL_PLLCTRL0_CP_SEL
+#define BF_CLKCTRL_PLLCTRL0_CP_SEL_V(e)         BF_CLKCTRL_PLLCTRL0_CP_SEL(BV_CLKCTRL_PLLCTRL0_CP_SEL__##e)
+#define BFM_CLKCTRL_PLLCTRL0_CP_SEL_V(v)        BM_CLKCTRL_PLLCTRL0_CP_SEL
+#define BP_CLKCTRL_PLLCTRL0_DIV_SEL             20
+#define BM_CLKCTRL_PLLCTRL0_DIV_SEL             0x300000
+#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__DEFAULT    0x0
+#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWER      0x1
+#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWEST     0x2
+#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__UNDEFINED  0x3
+#define BF_CLKCTRL_PLLCTRL0_DIV_SEL(v)          (((v) & 0x3) << 20)
+#define BFM_CLKCTRL_PLLCTRL0_DIV_SEL(v)         BM_CLKCTRL_PLLCTRL0_DIV_SEL
+#define BF_CLKCTRL_PLLCTRL0_DIV_SEL_V(e)        BF_CLKCTRL_PLLCTRL0_DIV_SEL(BV_CLKCTRL_PLLCTRL0_DIV_SEL__##e)
+#define BFM_CLKCTRL_PLLCTRL0_DIV_SEL_V(v)       BM_CLKCTRL_PLLCTRL0_DIV_SEL
+#define BP_CLKCTRL_PLLCTRL0_EN_USB_CLKS         18
+#define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS         0x40000
+#define BF_CLKCTRL_PLLCTRL0_EN_USB_CLKS(v)      (((v) & 0x1) << 18)
+#define BFM_CLKCTRL_PLLCTRL0_EN_USB_CLKS(v)     BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS
+#define BF_CLKCTRL_PLLCTRL0_EN_USB_CLKS_V(e)    BF_CLKCTRL_PLLCTRL0_EN_USB_CLKS(BV_CLKCTRL_PLLCTRL0_EN_USB_CLKS__##e)
+#define BFM_CLKCTRL_PLLCTRL0_EN_USB_CLKS_V(v)   BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS
+#define BP_CLKCTRL_PLLCTRL0_POWER               16
+#define BM_CLKCTRL_PLLCTRL0_POWER               0x10000
+#define BF_CLKCTRL_PLLCTRL0_POWER(v)            (((v) & 0x1) << 16)
+#define BFM_CLKCTRL_PLLCTRL0_POWER(v)           BM_CLKCTRL_PLLCTRL0_POWER
+#define BF_CLKCTRL_PLLCTRL0_POWER_V(e)          BF_CLKCTRL_PLLCTRL0_POWER(BV_CLKCTRL_PLLCTRL0_POWER__##e)
+#define BFM_CLKCTRL_PLLCTRL0_POWER_V(v)         BM_CLKCTRL_PLLCTRL0_POWER
+
+#define HW_CLKCTRL_PLLCTRL1                     HW(CLKCTRL_PLLCTRL1)
+#define HWA_CLKCTRL_PLLCTRL1                    (0x80040000 + 0x10)
+#define HWT_CLKCTRL_PLLCTRL1                    HWIO_32_RW
+#define HWN_CLKCTRL_PLLCTRL1                    CLKCTRL_PLLCTRL1
+#define HWI_CLKCTRL_PLLCTRL1                    
+#define BP_CLKCTRL_PLLCTRL1_LOCK                31
+#define BM_CLKCTRL_PLLCTRL1_LOCK                0x80000000
+#define BF_CLKCTRL_PLLCTRL1_LOCK(v)             (((v) & 0x1) << 31)
+#define BFM_CLKCTRL_PLLCTRL1_LOCK(v)            BM_CLKCTRL_PLLCTRL1_LOCK
+#define BF_CLKCTRL_PLLCTRL1_LOCK_V(e)           BF_CLKCTRL_PLLCTRL1_LOCK(BV_CLKCTRL_PLLCTRL1_LOCK__##e)
+#define BFM_CLKCTRL_PLLCTRL1_LOCK_V(v)          BM_CLKCTRL_PLLCTRL1_LOCK
+#define BP_CLKCTRL_PLLCTRL1_FORCE_LOCK          30
+#define BM_CLKCTRL_PLLCTRL1_FORCE_LOCK          0x40000000
+#define BF_CLKCTRL_PLLCTRL1_FORCE_LOCK(v)       (((v) & 0x1) << 30)
+#define BFM_CLKCTRL_PLLCTRL1_FORCE_LOCK(v)      BM_CLKCTRL_PLLCTRL1_FORCE_LOCK
+#define BF_CLKCTRL_PLLCTRL1_FORCE_LOCK_V(e)     BF_CLKCTRL_PLLCTRL1_FORCE_LOCK(BV_CLKCTRL_PLLCTRL1_FORCE_LOCK__##e)
+#define BFM_CLKCTRL_PLLCTRL1_FORCE_LOCK_V(v)    BM_CLKCTRL_PLLCTRL1_FORCE_LOCK
+#define BP_CLKCTRL_PLLCTRL1_LOCK_COUNT          0
+#define BM_CLKCTRL_PLLCTRL1_LOCK_COUNT          0xffff
+#define BF_CLKCTRL_PLLCTRL1_LOCK_COUNT(v)       (((v) & 0xffff) << 0)
+#define BFM_CLKCTRL_PLLCTRL1_LOCK_COUNT(v)      BM_CLKCTRL_PLLCTRL1_LOCK_COUNT
+#define BF_CLKCTRL_PLLCTRL1_LOCK_COUNT_V(e)     BF_CLKCTRL_PLLCTRL1_LOCK_COUNT(BV_CLKCTRL_PLLCTRL1_LOCK_COUNT__##e)
+#define BFM_CLKCTRL_PLLCTRL1_LOCK_COUNT_V(v)    BM_CLKCTRL_PLLCTRL1_LOCK_COUNT
+
+#define HW_CLKCTRL_CPU                          HW(CLKCTRL_CPU)
+#define HWA_CLKCTRL_CPU                         (0x80040000 + 0x20)
+#define HWT_CLKCTRL_CPU                         HWIO_32_RW
+#define HWN_CLKCTRL_CPU                         CLKCTRL_CPU
+#define HWI_CLKCTRL_CPU                         
+#define HW_CLKCTRL_CPU_SET                      HW(CLKCTRL_CPU_SET)
+#define HWA_CLKCTRL_CPU_SET                     (HWA_CLKCTRL_CPU + 0x4)
+#define HWT_CLKCTRL_CPU_SET                     HWIO_32_WO
+#define HWN_CLKCTRL_CPU_SET                     CLKCTRL_CPU
+#define HWI_CLKCTRL_CPU_SET                     
+#define HW_CLKCTRL_CPU_CLR                      HW(CLKCTRL_CPU_CLR)
+#define HWA_CLKCTRL_CPU_CLR                     (HWA_CLKCTRL_CPU + 0x8)
+#define HWT_CLKCTRL_CPU_CLR                     HWIO_32_WO
+#define HWN_CLKCTRL_CPU_CLR                     CLKCTRL_CPU
+#define HWI_CLKCTRL_CPU_CLR                     
+#define HW_CLKCTRL_CPU_TOG                      HW(CLKCTRL_CPU_TOG)
+#define HWA_CLKCTRL_CPU_TOG                     (HWA_CLKCTRL_CPU + 0xc)
+#define HWT_CLKCTRL_CPU_TOG                     HWIO_32_WO
+#define HWN_CLKCTRL_CPU_TOG                     CLKCTRL_CPU
+#define HWI_CLKCTRL_CPU_TOG                     
+#define BP_CLKCTRL_CPU_BUSY_REF_XTAL            29
+#define BM_CLKCTRL_CPU_BUSY_REF_XTAL            0x20000000
+#define BF_CLKCTRL_CPU_BUSY_REF_XTAL(v)         (((v) & 0x1) << 29)
+#define BFM_CLKCTRL_CPU_BUSY_REF_XTAL(v)        BM_CLKCTRL_CPU_BUSY_REF_XTAL
+#define BF_CLKCTRL_CPU_BUSY_REF_XTAL_V(e)       BF_CLKCTRL_CPU_BUSY_REF_XTAL(BV_CLKCTRL_CPU_BUSY_REF_XTAL__##e)
+#define BFM_CLKCTRL_CPU_BUSY_REF_XTAL_V(v)      BM_CLKCTRL_CPU_BUSY_REF_XTAL
+#define BP_CLKCTRL_CPU_BUSY_REF_CPU             28
+#define BM_CLKCTRL_CPU_BUSY_REF_CPU             0x10000000
+#define BF_CLKCTRL_CPU_BUSY_REF_CPU(v)          (((v) & 0x1) << 28)
+#define BFM_CLKCTRL_CPU_BUSY_REF_CPU(v)         BM_CLKCTRL_CPU_BUSY_REF_CPU
+#define BF_CLKCTRL_CPU_BUSY_REF_CPU_V(e)        BF_CLKCTRL_CPU_BUSY_REF_CPU(BV_CLKCTRL_CPU_BUSY_REF_CPU__##e)
+#define BFM_CLKCTRL_CPU_BUSY_REF_CPU_V(v)       BM_CLKCTRL_CPU_BUSY_REF_CPU
+#define BP_CLKCTRL_CPU_DIV_XTAL_FRAC_EN         26
+#define BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN         0x4000000
+#define BF_CLKCTRL_CPU_DIV_XTAL_FRAC_EN(v)      (((v) & 0x1) << 26)
+#define BFM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN(v)     BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN
+#define BF_CLKCTRL_CPU_DIV_XTAL_FRAC_EN_V(e)    BF_CLKCTRL_CPU_DIV_XTAL_FRAC_EN(BV_CLKCTRL_CPU_DIV_XTAL_FRAC_EN__##e)
+#define BFM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN_V(v)   BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN
+#define BP_CLKCTRL_CPU_DIV_XTAL                 16
+#define BM_CLKCTRL_CPU_DIV_XTAL                 0x3ff0000
+#define BF_CLKCTRL_CPU_DIV_XTAL(v)              (((v) & 0x3ff) << 16)
+#define BFM_CLKCTRL_CPU_DIV_XTAL(v)             BM_CLKCTRL_CPU_DIV_XTAL
+#define BF_CLKCTRL_CPU_DIV_XTAL_V(e)            BF_CLKCTRL_CPU_DIV_XTAL(BV_CLKCTRL_CPU_DIV_XTAL__##e)
+#define BFM_CLKCTRL_CPU_DIV_XTAL_V(v)           BM_CLKCTRL_CPU_DIV_XTAL
+#define BP_CLKCTRL_CPU_INTERRUPT_WAIT           12
+#define BM_CLKCTRL_CPU_INTERRUPT_WAIT           0x1000
+#define BF_CLKCTRL_CPU_INTERRUPT_WAIT(v)        (((v) & 0x1) << 12)
+#define BFM_CLKCTRL_CPU_INTERRUPT_WAIT(v)       BM_CLKCTRL_CPU_INTERRUPT_WAIT
+#define BF_CLKCTRL_CPU_INTERRUPT_WAIT_V(e)      BF_CLKCTRL_CPU_INTERRUPT_WAIT(BV_CLKCTRL_CPU_INTERRUPT_WAIT__##e)
+#define BFM_CLKCTRL_CPU_INTERRUPT_WAIT_V(v)     BM_CLKCTRL_CPU_INTERRUPT_WAIT
+#define BP_CLKCTRL_CPU_DIV_CPU_FRAC_EN          10
+#define BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN          0x400
+#define BF_CLKCTRL_CPU_DIV_CPU_FRAC_EN(v)       (((v) & 0x1) << 10)
+#define BFM_CLKCTRL_CPU_DIV_CPU_FRAC_EN(v)      BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN
+#define BF_CLKCTRL_CPU_DIV_CPU_FRAC_EN_V(e)     BF_CLKCTRL_CPU_DIV_CPU_FRAC_EN(BV_CLKCTRL_CPU_DIV_CPU_FRAC_EN__##e)
+#define BFM_CLKCTRL_CPU_DIV_CPU_FRAC_EN_V(v)    BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN
+#define BP_CLKCTRL_CPU_DIV_CPU                  0
+#define BM_CLKCTRL_CPU_DIV_CPU                  0x3ff
+#define BF_CLKCTRL_CPU_DIV_CPU(v)               (((v) & 0x3ff) << 0)
+#define BFM_CLKCTRL_CPU_DIV_CPU(v)              BM_CLKCTRL_CPU_DIV_CPU
+#define BF_CLKCTRL_CPU_DIV_CPU_V(e)             BF_CLKCTRL_CPU_DIV_CPU(BV_CLKCTRL_CPU_DIV_CPU__##e)
+#define BFM_CLKCTRL_CPU_DIV_CPU_V(v)            BM_CLKCTRL_CPU_DIV_CPU
+
+#define HW_CLKCTRL_HBUS                             HW(CLKCTRL_HBUS)
+#define HWA_CLKCTRL_HBUS                            (0x80040000 + 0x30)
+#define HWT_CLKCTRL_HBUS                            HWIO_32_RW
+#define HWN_CLKCTRL_HBUS                            CLKCTRL_HBUS
+#define HWI_CLKCTRL_HBUS                            
+#define HW_CLKCTRL_HBUS_SET                         HW(CLKCTRL_HBUS_SET)
+#define HWA_CLKCTRL_HBUS_SET                        (HWA_CLKCTRL_HBUS + 0x4)
+#define HWT_CLKCTRL_HBUS_SET                        HWIO_32_WO
+#define HWN_CLKCTRL_HBUS_SET                        CLKCTRL_HBUS
+#define HWI_CLKCTRL_HBUS_SET                        
+#define HW_CLKCTRL_HBUS_CLR                         HW(CLKCTRL_HBUS_CLR)
+#define HWA_CLKCTRL_HBUS_CLR                        (HWA_CLKCTRL_HBUS + 0x8)
+#define HWT_CLKCTRL_HBUS_CLR                        HWIO_32_WO
+#define HWN_CLKCTRL_HBUS_CLR                        CLKCTRL_HBUS
+#define HWI_CLKCTRL_HBUS_CLR                        
+#define HW_CLKCTRL_HBUS_TOG                         HW(CLKCTRL_HBUS_TOG)
+#define HWA_CLKCTRL_HBUS_TOG                        (HWA_CLKCTRL_HBUS + 0xc)
+#define HWT_CLKCTRL_HBUS_TOG                        HWIO_32_WO
+#define HWN_CLKCTRL_HBUS_TOG                        CLKCTRL_HBUS
+#define HWI_CLKCTRL_HBUS_TOG                        
+#define BP_CLKCTRL_HBUS_BUSY                        29
+#define BM_CLKCTRL_HBUS_BUSY                        0x20000000
+#define BF_CLKCTRL_HBUS_BUSY(v)                     (((v) & 0x1) << 29)
+#define BFM_CLKCTRL_HBUS_BUSY(v)                    BM_CLKCTRL_HBUS_BUSY
+#define BF_CLKCTRL_HBUS_BUSY_V(e)                   BF_CLKCTRL_HBUS_BUSY(BV_CLKCTRL_HBUS_BUSY__##e)
+#define BFM_CLKCTRL_HBUS_BUSY_V(v)                  BM_CLKCTRL_HBUS_BUSY
+#define BP_CLKCTRL_HBUS_APBHDMA_AS_ENABLE           26
+#define BM_CLKCTRL_HBUS_APBHDMA_AS_ENABLE           0x4000000
+#define BF_CLKCTRL_HBUS_APBHDMA_AS_ENABLE(v)        (((v) & 0x1) << 26)
+#define BFM_CLKCTRL_HBUS_APBHDMA_AS_ENABLE(v)       BM_CLKCTRL_HBUS_APBHDMA_AS_ENABLE
+#define BF_CLKCTRL_HBUS_APBHDMA_AS_ENABLE_V(e)      BF_CLKCTRL_HBUS_APBHDMA_AS_ENABLE(BV_CLKCTRL_HBUS_APBHDMA_AS_ENABLE__##e)
+#define BFM_CLKCTRL_HBUS_APBHDMA_AS_ENABLE_V(v)     BM_CLKCTRL_HBUS_APBHDMA_AS_ENABLE
+#define BP_CLKCTRL_HBUS_APBXDMA_AS_ENABLE           25
+#define BM_CLKCTRL_HBUS_APBXDMA_AS_ENABLE           0x2000000
+#define BF_CLKCTRL_HBUS_APBXDMA_AS_ENABLE(v)        (((v) & 0x1) << 25)
+#define BFM_CLKCTRL_HBUS_APBXDMA_AS_ENABLE(v)       BM_CLKCTRL_HBUS_APBXDMA_AS_ENABLE
+#define BF_CLKCTRL_HBUS_APBXDMA_AS_ENABLE_V(e)      BF_CLKCTRL_HBUS_APBXDMA_AS_ENABLE(BV_CLKCTRL_HBUS_APBXDMA_AS_ENABLE__##e)
+#define BFM_CLKCTRL_HBUS_APBXDMA_AS_ENABLE_V(v)     BM_CLKCTRL_HBUS_APBXDMA_AS_ENABLE
+#define BP_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE       24
+#define BM_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE       0x1000000
+#define BF_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE(v)    (((v) & 0x1) << 24)
+#define BFM_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE(v)   BM_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE
+#define BF_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE_V(e)  BF_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE(BV_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE__##e)
+#define BFM_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE_V(v) BM_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE
+#define BP_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE           23
+#define BM_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE           0x800000
+#define BF_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE(v)        (((v) & 0x1) << 23)
+#define BFM_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE(v)       BM_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE
+#define BF_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE_V(e)      BF_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE(BV_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE__##e)
+#define BFM_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE_V(v)     BM_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE
+#define BP_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE          22
+#define BM_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE          0x400000
+#define BF_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE(v)       (((v) & 0x1) << 22)
+#define BFM_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE(v)      BM_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE
+#define BF_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE_V(e)     BF_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE(BV_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE__##e)
+#define BFM_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE_V(v)    BM_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE
+#define BP_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE         21
+#define BM_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE         0x200000
+#define BF_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE(v)      (((v) & 0x1) << 21)
+#define BFM_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE(v)     BM_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE
+#define BF_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE_V(e)    BF_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE(BV_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE__##e)
+#define BFM_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE_V(v)   BM_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE
+#define BP_CLKCTRL_HBUS_AUTO_SLOW_MODE              20
+#define BM_CLKCTRL_HBUS_AUTO_SLOW_MODE              0x100000
+#define BF_CLKCTRL_HBUS_AUTO_SLOW_MODE(v)           (((v) & 0x1) << 20)
+#define BFM_CLKCTRL_HBUS_AUTO_SLOW_MODE(v)          BM_CLKCTRL_HBUS_AUTO_SLOW_MODE
+#define BF_CLKCTRL_HBUS_AUTO_SLOW_MODE_V(e)         BF_CLKCTRL_HBUS_AUTO_SLOW_MODE(BV_CLKCTRL_HBUS_AUTO_SLOW_MODE__##e)
+#define BFM_CLKCTRL_HBUS_AUTO_SLOW_MODE_V(v)        BM_CLKCTRL_HBUS_AUTO_SLOW_MODE
+#define BP_CLKCTRL_HBUS_SLOW_DIV                    16
+#define BM_CLKCTRL_HBUS_SLOW_DIV                    0x70000
+#define BV_CLKCTRL_HBUS_SLOW_DIV__BY1               0x0
+#define BV_CLKCTRL_HBUS_SLOW_DIV__BY2               0x1
+#define BV_CLKCTRL_HBUS_SLOW_DIV__BY4               0x2
+#define BV_CLKCTRL_HBUS_SLOW_DIV__BY8               0x3
+#define BV_CLKCTRL_HBUS_SLOW_DIV__BY16              0x4
+#define BV_CLKCTRL_HBUS_SLOW_DIV__BY32              0x5
+#define BF_CLKCTRL_HBUS_SLOW_DIV(v)                 (((v) & 0x7) << 16)
+#define BFM_CLKCTRL_HBUS_SLOW_DIV(v)                BM_CLKCTRL_HBUS_SLOW_DIV
+#define BF_CLKCTRL_HBUS_SLOW_DIV_V(e)               BF_CLKCTRL_HBUS_SLOW_DIV(BV_CLKCTRL_HBUS_SLOW_DIV__##e)
+#define BFM_CLKCTRL_HBUS_SLOW_DIV_V(v)              BM_CLKCTRL_HBUS_SLOW_DIV
+#define BP_CLKCTRL_HBUS_DIV_FRAC_EN                 5
+#define BM_CLKCTRL_HBUS_DIV_FRAC_EN                 0x20
+#define BF_CLKCTRL_HBUS_DIV_FRAC_EN(v)              (((v) & 0x1) << 5)
+#define BFM_CLKCTRL_HBUS_DIV_FRAC_EN(v)             BM_CLKCTRL_HBUS_DIV_FRAC_EN
+#define BF_CLKCTRL_HBUS_DIV_FRAC_EN_V(e)            BF_CLKCTRL_HBUS_DIV_FRAC_EN(BV_CLKCTRL_HBUS_DIV_FRAC_EN__##e)
+#define BFM_CLKCTRL_HBUS_DIV_FRAC_EN_V(v)           BM_CLKCTRL_HBUS_DIV_FRAC_EN
+#define BP_CLKCTRL_HBUS_DIV                         0
+#define BM_CLKCTRL_HBUS_DIV                         0x1f
+#define BF_CLKCTRL_HBUS_DIV(v)                      (((v) & 0x1f) << 0)
+#define BFM_CLKCTRL_HBUS_DIV(v)                     BM_CLKCTRL_HBUS_DIV
+#define BF_CLKCTRL_HBUS_DIV_V(e)                    BF_CLKCTRL_HBUS_DIV(BV_CLKCTRL_HBUS_DIV__##e)
+#define BFM_CLKCTRL_HBUS_DIV_V(v)                   BM_CLKCTRL_HBUS_DIV
+
+#define HW_CLKCTRL_XBUS                     HW(CLKCTRL_XBUS)
+#define HWA_CLKCTRL_XBUS                    (0x80040000 + 0x40)
+#define HWT_CLKCTRL_XBUS                    HWIO_32_RW
+#define HWN_CLKCTRL_XBUS                    CLKCTRL_XBUS
+#define HWI_CLKCTRL_XBUS                    
+#define BP_CLKCTRL_XBUS_BUSY                31
+#define BM_CLKCTRL_XBUS_BUSY                0x80000000
+#define BF_CLKCTRL_XBUS_BUSY(v)             (((v) & 0x1) << 31)
+#define BFM_CLKCTRL_XBUS_BUSY(v)            BM_CLKCTRL_XBUS_BUSY
+#define BF_CLKCTRL_XBUS_BUSY_V(e)           BF_CLKCTRL_XBUS_BUSY(BV_CLKCTRL_XBUS_BUSY__##e)
+#define BFM_CLKCTRL_XBUS_BUSY_V(v)          BM_CLKCTRL_XBUS_BUSY
+#define BP_CLKCTRL_XBUS_DIV_FRAC_EN         10
+#define BM_CLKCTRL_XBUS_DIV_FRAC_EN         0x400
+#define BF_CLKCTRL_XBUS_DIV_FRAC_EN(v)      (((v) & 0x1) << 10)
+#define BFM_CLKCTRL_XBUS_DIV_FRAC_EN(v)     BM_CLKCTRL_XBUS_DIV_FRAC_EN
+#define BF_CLKCTRL_XBUS_DIV_FRAC_EN_V(e)    BF_CLKCTRL_XBUS_DIV_FRAC_EN(BV_CLKCTRL_XBUS_DIV_FRAC_EN__##e)
+#define BFM_CLKCTRL_XBUS_DIV_FRAC_EN_V(v)   BM_CLKCTRL_XBUS_DIV_FRAC_EN
+#define BP_CLKCTRL_XBUS_DIV                 0
+#define BM_CLKCTRL_XBUS_DIV                 0x3ff
+#define BF_CLKCTRL_XBUS_DIV(v)              (((v) & 0x3ff) << 0)
+#define BFM_CLKCTRL_XBUS_DIV(v)             BM_CLKCTRL_XBUS_DIV
+#define BF_CLKCTRL_XBUS_DIV_V(e)            BF_CLKCTRL_XBUS_DIV(BV_CLKCTRL_XBUS_DIV__##e)
+#define BFM_CLKCTRL_XBUS_DIV_V(v)           BM_CLKCTRL_XBUS_DIV
+
+#define HW_CLKCTRL_XTAL                             HW(CLKCTRL_XTAL)
+#define HWA_CLKCTRL_XTAL                            (0x80040000 + 0x50)
+#define HWT_CLKCTRL_XTAL                            HWIO_32_RW
+#define HWN_CLKCTRL_XTAL                            CLKCTRL_XTAL
+#define HWI_CLKCTRL_XTAL                            
+#define HW_CLKCTRL_XTAL_SET                         HW(CLKCTRL_XTAL_SET)
+#define HWA_CLKCTRL_XTAL_SET                        (HWA_CLKCTRL_XTAL + 0x4)
+#define HWT_CLKCTRL_XTAL_SET                        HWIO_32_WO
+#define HWN_CLKCTRL_XTAL_SET                        CLKCTRL_XTAL
+#define HWI_CLKCTRL_XTAL_SET                        
+#define HW_CLKCTRL_XTAL_CLR                         HW(CLKCTRL_XTAL_CLR)
+#define HWA_CLKCTRL_XTAL_CLR                        (HWA_CLKCTRL_XTAL + 0x8)
+#define HWT_CLKCTRL_XTAL_CLR                        HWIO_32_WO
+#define HWN_CLKCTRL_XTAL_CLR                        CLKCTRL_XTAL
+#define HWI_CLKCTRL_XTAL_CLR                        
+#define HW_CLKCTRL_XTAL_TOG                         HW(CLKCTRL_XTAL_TOG)
+#define HWA_CLKCTRL_XTAL_TOG                        (HWA_CLKCTRL_XTAL + 0xc)
+#define HWT_CLKCTRL_XTAL_TOG                        HWIO_32_WO
+#define HWN_CLKCTRL_XTAL_TOG                        CLKCTRL_XTAL
+#define HWI_CLKCTRL_XTAL_TOG                        
+#define BP_CLKCTRL_XTAL_UART_CLK_GATE               31
+#define BM_CLKCTRL_XTAL_UART_CLK_GATE               0x80000000
+#define BF_CLKCTRL_XTAL_UART_CLK_GATE(v)            (((v) & 0x1) << 31)
+#define BFM_CLKCTRL_XTAL_UART_CLK_GATE(v)           BM_CLKCTRL_XTAL_UART_CLK_GATE
+#define BF_CLKCTRL_XTAL_UART_CLK_GATE_V(e)          BF_CLKCTRL_XTAL_UART_CLK_GATE(BV_CLKCTRL_XTAL_UART_CLK_GATE__##e)
+#define BFM_CLKCTRL_XTAL_UART_CLK_GATE_V(v)         BM_CLKCTRL_XTAL_UART_CLK_GATE
+#define BP_CLKCTRL_XTAL_FILT_CLK24M_GATE            30
+#define BM_CLKCTRL_XTAL_FILT_CLK24M_GATE            0x40000000
+#define BF_CLKCTRL_XTAL_FILT_CLK24M_GATE(v)         (((v) & 0x1) << 30)
+#define BFM_CLKCTRL_XTAL_FILT_CLK24M_GATE(v)        BM_CLKCTRL_XTAL_FILT_CLK24M_GATE
+#define BF_CLKCTRL_XTAL_FILT_CLK24M_GATE_V(e)       BF_CLKCTRL_XTAL_FILT_CLK24M_GATE(BV_CLKCTRL_XTAL_FILT_CLK24M_GATE__##e)
+#define BFM_CLKCTRL_XTAL_FILT_CLK24M_GATE_V(v)      BM_CLKCTRL_XTAL_FILT_CLK24M_GATE
+#define BP_CLKCTRL_XTAL_PWM_CLK24M_GATE             29
+#define BM_CLKCTRL_XTAL_PWM_CLK24M_GATE             0x20000000
+#define BF_CLKCTRL_XTAL_PWM_CLK24M_GATE(v)          (((v) & 0x1) << 29)
+#define BFM_CLKCTRL_XTAL_PWM_CLK24M_GATE(v)         BM_CLKCTRL_XTAL_PWM_CLK24M_GATE
+#define BF_CLKCTRL_XTAL_PWM_CLK24M_GATE_V(e)        BF_CLKCTRL_XTAL_PWM_CLK24M_GATE(BV_CLKCTRL_XTAL_PWM_CLK24M_GATE__##e)
+#define BFM_CLKCTRL_XTAL_PWM_CLK24M_GATE_V(v)       BM_CLKCTRL_XTAL_PWM_CLK24M_GATE
+#define BP_CLKCTRL_XTAL_DRI_CLK24M_GATE             28
+#define BM_CLKCTRL_XTAL_DRI_CLK24M_GATE             0x10000000
+#define BF_CLKCTRL_XTAL_DRI_CLK24M_GATE(v)          (((v) & 0x1) << 28)
+#define BFM_CLKCTRL_XTAL_DRI_CLK24M_GATE(v)         BM_CLKCTRL_XTAL_DRI_CLK24M_GATE
+#define BF_CLKCTRL_XTAL_DRI_CLK24M_GATE_V(e)        BF_CLKCTRL_XTAL_DRI_CLK24M_GATE(BV_CLKCTRL_XTAL_DRI_CLK24M_GATE__##e)
+#define BFM_CLKCTRL_XTAL_DRI_CLK24M_GATE_V(v)       BM_CLKCTRL_XTAL_DRI_CLK24M_GATE
+#define BP_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE          27
+#define BM_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE          0x8000000
+#define BF_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE(v)       (((v) & 0x1) << 27)
+#define BFM_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE(v)      BM_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE
+#define BF_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE_V(e)     BF_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE(BV_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE__##e)
+#define BFM_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE_V(v)    BM_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE
+#define BP_CLKCTRL_XTAL_TIMROT_CLK32K_GATE          26
+#define BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE          0x4000000
+#define BF_CLKCTRL_XTAL_TIMROT_CLK32K_GATE(v)       (((v) & 0x1) << 26)
+#define BFM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE(v)      BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE
+#define BF_CLKCTRL_XTAL_TIMROT_CLK32K_GATE_V(e)     BF_CLKCTRL_XTAL_TIMROT_CLK32K_GATE(BV_CLKCTRL_XTAL_TIMROT_CLK32K_GATE__##e)
+#define BFM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE_V(v)    BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE
+#define BP_CLKCTRL_XTAL_DIV_UART                    0
+#define BM_CLKCTRL_XTAL_DIV_UART                    0x3
+#define BF_CLKCTRL_XTAL_DIV_UART(v)                 (((v) & 0x3) << 0)
+#define BFM_CLKCTRL_XTAL_DIV_UART(v)                BM_CLKCTRL_XTAL_DIV_UART
+#define BF_CLKCTRL_XTAL_DIV_UART_V(e)               BF_CLKCTRL_XTAL_DIV_UART(BV_CLKCTRL_XTAL_DIV_UART__##e)
+#define BFM_CLKCTRL_XTAL_DIV_UART_V(v)              BM_CLKCTRL_XTAL_DIV_UART
+
+#define HW_CLKCTRL_PIX                      HW(CLKCTRL_PIX)
+#define HWA_CLKCTRL_PIX                     (0x80040000 + 0x60)
+#define HWT_CLKCTRL_PIX                     HWIO_32_RW
+#define HWN_CLKCTRL_PIX                     CLKCTRL_PIX
+#define HWI_CLKCTRL_PIX                     
+#define BP_CLKCTRL_PIX_CLKGATE              31
+#define BM_CLKCTRL_PIX_CLKGATE              0x80000000
+#define BF_CLKCTRL_PIX_CLKGATE(v)           (((v) & 0x1) << 31)
+#define BFM_CLKCTRL_PIX_CLKGATE(v)          BM_CLKCTRL_PIX_CLKGATE
+#define BF_CLKCTRL_PIX_CLKGATE_V(e)         BF_CLKCTRL_PIX_CLKGATE(BV_CLKCTRL_PIX_CLKGATE__##e)
+#define BFM_CLKCTRL_PIX_CLKGATE_V(v)        BM_CLKCTRL_PIX_CLKGATE
+#define BP_CLKCTRL_PIX_BUSY                 29
+#define BM_CLKCTRL_PIX_BUSY                 0x20000000
+#define BF_CLKCTRL_PIX_BUSY(v)              (((v) & 0x1) << 29)
+#define BFM_CLKCTRL_PIX_BUSY(v)             BM_CLKCTRL_PIX_BUSY
+#define BF_CLKCTRL_PIX_BUSY_V(e)            BF_CLKCTRL_PIX_BUSY(BV_CLKCTRL_PIX_BUSY__##e)
+#define BFM_CLKCTRL_PIX_BUSY_V(v)           BM_CLKCTRL_PIX_BUSY
+#define BP_CLKCTRL_PIX_DIV_FRAC_EN          15
+#define BM_CLKCTRL_PIX_DIV_FRAC_EN          0x8000
+#define BF_CLKCTRL_PIX_DIV_FRAC_EN(v)       (((v) & 0x1) << 15)
+#define BFM_CLKCTRL_PIX_DIV_FRAC_EN(v)      BM_CLKCTRL_PIX_DIV_FRAC_EN
+#define BF_CLKCTRL_PIX_DIV_FRAC_EN_V(e)     BF_CLKCTRL_PIX_DIV_FRAC_EN(BV_CLKCTRL_PIX_DIV_FRAC_EN__##e)
+#define BFM_CLKCTRL_PIX_DIV_FRAC_EN_V(v)    BM_CLKCTRL_PIX_DIV_FRAC_EN
+#define BP_CLKCTRL_PIX_DIV                  0
+#define BM_CLKCTRL_PIX_DIV                  0x7fff
+#define BF_CLKCTRL_PIX_DIV(v)               (((v) & 0x7fff) << 0)
+#define BFM_CLKCTRL_PIX_DIV(v)              BM_CLKCTRL_PIX_DIV
+#define BF_CLKCTRL_PIX_DIV_V(e)             BF_CLKCTRL_PIX_DIV(BV_CLKCTRL_PIX_DIV__##e)
+#define BFM_CLKCTRL_PIX_DIV_V(v)            BM_CLKCTRL_PIX_DIV
+
+#define HW_CLKCTRL_SSP                      HW(CLKCTRL_SSP)
+#define HWA_CLKCTRL_SSP                     (0x80040000 + 0x70)
+#define HWT_CLKCTRL_SSP                     HWIO_32_RW
+#define HWN_CLKCTRL_SSP                     CLKCTRL_SSP
+#define HWI_CLKCTRL_SSP                     
+#define BP_CLKCTRL_SSP_CLKGATE              31
+#define BM_CLKCTRL_SSP_CLKGATE              0x80000000
+#define BF_CLKCTRL_SSP_CLKGATE(v)           (((v) & 0x1) << 31)
+#define BFM_CLKCTRL_SSP_CLKGATE(v)          BM_CLKCTRL_SSP_CLKGATE
+#define BF_CLKCTRL_SSP_CLKGATE_V(e)         BF_CLKCTRL_SSP_CLKGATE(BV_CLKCTRL_SSP_CLKGATE__##e)
+#define BFM_CLKCTRL_SSP_CLKGATE_V(v)        BM_CLKCTRL_SSP_CLKGATE
+#define BP_CLKCTRL_SSP_BUSY                 29
+#define BM_CLKCTRL_SSP_BUSY                 0x20000000
+#define BF_CLKCTRL_SSP_BUSY(v)              (((v) & 0x1) << 29)
+#define BFM_CLKCTRL_SSP_BUSY(v)             BM_CLKCTRL_SSP_BUSY
+#define BF_CLKCTRL_SSP_BUSY_V(e)            BF_CLKCTRL_SSP_BUSY(BV_CLKCTRL_SSP_BUSY__##e)
+#define BFM_CLKCTRL_SSP_BUSY_V(v)           BM_CLKCTRL_SSP_BUSY
+#define BP_CLKCTRL_SSP_DIV_FRAC_EN          9
+#define BM_CLKCTRL_SSP_DIV_FRAC_EN          0x200
+#define BF_CLKCTRL_SSP_DIV_FRAC_EN(v)       (((v) & 0x1) << 9)
+#define BFM_CLKCTRL_SSP_DIV_FRAC_EN(v)      BM_CLKCTRL_SSP_DIV_FRAC_EN
+#define BF_CLKCTRL_SSP_DIV_FRAC_EN_V(e)     BF_CLKCTRL_SSP_DIV_FRAC_EN(BV_CLKCTRL_SSP_DIV_FRAC_EN__##e)
+#define BFM_CLKCTRL_SSP_DIV_FRAC_EN_V(v)    BM_CLKCTRL_SSP_DIV_FRAC_EN
+#define BP_CLKCTRL_SSP_DIV                  0
+#define BM_CLKCTRL_SSP_DIV                  0x1ff
+#define BF_CLKCTRL_SSP_DIV(v)               (((v) & 0x1ff) << 0)
+#define BFM_CLKCTRL_SSP_DIV(v)              BM_CLKCTRL_SSP_DIV
+#define BF_CLKCTRL_SSP_DIV_V(e)             BF_CLKCTRL_SSP_DIV(BV_CLKCTRL_SSP_DIV__##e)
+#define BFM_CLKCTRL_SSP_DIV_V(v)            BM_CLKCTRL_SSP_DIV
+
+#define HW_CLKCTRL_GPMI                     HW(CLKCTRL_GPMI)
+#define HWA_CLKCTRL_GPMI                    (0x80040000 + 0x80)
+#define HWT_CLKCTRL_GPMI                    HWIO_32_RW
+#define HWN_CLKCTRL_GPMI                    CLKCTRL_GPMI
+#define HWI_CLKCTRL_GPMI                    
+#define BP_CLKCTRL_GPMI_CLKGATE             31
+#define BM_CLKCTRL_GPMI_CLKGATE             0x80000000
+#define BF_CLKCTRL_GPMI_CLKGATE(v)          (((v) & 0x1) << 31)
+#define BFM_CLKCTRL_GPMI_CLKGATE(v)         BM_CLKCTRL_GPMI_CLKGATE
+#define BF_CLKCTRL_GPMI_CLKGATE_V(e)        BF_CLKCTRL_GPMI_CLKGATE(BV_CLKCTRL_GPMI_CLKGATE__##e)
+#define BFM_CLKCTRL_GPMI_CLKGATE_V(v)       BM_CLKCTRL_GPMI_CLKGATE
+#define BP_CLKCTRL_GPMI_BUSY                29
+#define BM_CLKCTRL_GPMI_BUSY                0x20000000
+#define BF_CLKCTRL_GPMI_BUSY(v)             (((v) & 0x1) << 29)
+#define BFM_CLKCTRL_GPMI_BUSY(v)            BM_CLKCTRL_GPMI_BUSY
+#define BF_CLKCTRL_GPMI_BUSY_V(e)           BF_CLKCTRL_GPMI_BUSY(BV_CLKCTRL_GPMI_BUSY__##e)
+#define BFM_CLKCTRL_GPMI_BUSY_V(v)          BM_CLKCTRL_GPMI_BUSY
+#define BP_CLKCTRL_GPMI_DIV_FRAC_EN         10
+#define BM_CLKCTRL_GPMI_DIV_FRAC_EN         0x400
+#define BF_CLKCTRL_GPMI_DIV_FRAC_EN(v)      (((v) & 0x1) << 10)
+#define BFM_CLKCTRL_GPMI_DIV_FRAC_EN(v)     BM_CLKCTRL_GPMI_DIV_FRAC_EN
+#define BF_CLKCTRL_GPMI_DIV_FRAC_EN_V(e)    BF_CLKCTRL_GPMI_DIV_FRAC_EN(BV_CLKCTRL_GPMI_DIV_FRAC_EN__##e)
+#define BFM_CLKCTRL_GPMI_DIV_FRAC_EN_V(v)   BM_CLKCTRL_GPMI_DIV_FRAC_EN
+#define BP_CLKCTRL_GPMI_DIV                 0
+#define BM_CLKCTRL_GPMI_DIV                 0x3ff
+#define BF_CLKCTRL_GPMI_DIV(v)              (((v) & 0x3ff) << 0)
+#define BFM_CLKCTRL_GPMI_DIV(v)             BM_CLKCTRL_GPMI_DIV
+#define BF_CLKCTRL_GPMI_DIV_V(e)            BF_CLKCTRL_GPMI_DIV(BV_CLKCTRL_GPMI_DIV__##e)
+#define BFM_CLKCTRL_GPMI_DIV_V(v)           BM_CLKCTRL_GPMI_DIV
+
+#define HW_CLKCTRL_SPDIF                HW(CLKCTRL_SPDIF)
+#define HWA_CLKCTRL_SPDIF               (0x80040000 + 0x90)
+#define HWT_CLKCTRL_SPDIF               HWIO_32_RW
+#define HWN_CLKCTRL_SPDIF               CLKCTRL_SPDIF
+#define HWI_CLKCTRL_SPDIF               
+#define BP_CLKCTRL_SPDIF_CLKGATE        31
+#define BM_CLKCTRL_SPDIF_CLKGATE        0x80000000
+#define BF_CLKCTRL_SPDIF_CLKGATE(v)     (((v) & 0x1) << 31)
+#define BFM_CLKCTRL_SPDIF_CLKGATE(v)    BM_CLKCTRL_SPDIF_CLKGATE
+#define BF_CLKCTRL_SPDIF_CLKGATE_V(e)   BF_CLKCTRL_SPDIF_CLKGATE(BV_CLKCTRL_SPDIF_CLKGATE__##e)
+#define BFM_CLKCTRL_SPDIF_CLKGATE_V(v)  BM_CLKCTRL_SPDIF_CLKGATE
+
+#define HW_CLKCTRL_EMI                          HW(CLKCTRL_EMI)
+#define HWA_CLKCTRL_EMI                         (0x80040000 + 0xa0)
+#define HWT_CLKCTRL_EMI                         HWIO_32_RW
+#define HWN_CLKCTRL_EMI                         CLKCTRL_EMI
+#define HWI_CLKCTRL_EMI                         
+#define BP_CLKCTRL_EMI_CLKGATE                  31
+#define BM_CLKCTRL_EMI_CLKGATE                  0x80000000
+#define BF_CLKCTRL_EMI_CLKGATE(v)               (((v) & 0x1) << 31)
+#define BFM_CLKCTRL_EMI_CLKGATE(v)              BM_CLKCTRL_EMI_CLKGATE
+#define BF_CLKCTRL_EMI_CLKGATE_V(e)             BF_CLKCTRL_EMI_CLKGATE(BV_CLKCTRL_EMI_CLKGATE__##e)
+#define BFM_CLKCTRL_EMI_CLKGATE_V(v)            BM_CLKCTRL_EMI_CLKGATE
+#define BP_CLKCTRL_EMI_BUSY_REF_XTAL            29
+#define BM_CLKCTRL_EMI_BUSY_REF_XTAL            0x20000000
+#define BF_CLKCTRL_EMI_BUSY_REF_XTAL(v)         (((v) & 0x1) << 29)
+#define BFM_CLKCTRL_EMI_BUSY_REF_XTAL(v)        BM_CLKCTRL_EMI_BUSY_REF_XTAL
+#define BF_CLKCTRL_EMI_BUSY_REF_XTAL_V(e)       BF_CLKCTRL_EMI_BUSY_REF_XTAL(BV_CLKCTRL_EMI_BUSY_REF_XTAL__##e)
+#define BFM_CLKCTRL_EMI_BUSY_REF_XTAL_V(v)      BM_CLKCTRL_EMI_BUSY_REF_XTAL
+#define BP_CLKCTRL_EMI_BUSY_REF_EMI             28
+#define BM_CLKCTRL_EMI_BUSY_REF_EMI             0x10000000
+#define BF_CLKCTRL_EMI_BUSY_REF_EMI(v)          (((v) & 0x1) << 28)
+#define BFM_CLKCTRL_EMI_BUSY_REF_EMI(v)         BM_CLKCTRL_EMI_BUSY_REF_EMI
+#define BF_CLKCTRL_EMI_BUSY_REF_EMI_V(e)        BF_CLKCTRL_EMI_BUSY_REF_EMI(BV_CLKCTRL_EMI_BUSY_REF_EMI__##e)
+#define BFM_CLKCTRL_EMI_BUSY_REF_EMI_V(v)       BM_CLKCTRL_EMI_BUSY_REF_EMI
+#define BP_CLKCTRL_EMI_BUSY_DCC_RESYNC          17
+#define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC          0x20000
+#define BF_CLKCTRL_EMI_BUSY_DCC_RESYNC(v)       (((v) & 0x1) << 17)
+#define BFM_CLKCTRL_EMI_BUSY_DCC_RESYNC(v)      BM_CLKCTRL_EMI_BUSY_DCC_RESYNC
+#define BF_CLKCTRL_EMI_BUSY_DCC_RESYNC_V(e)     BF_CLKCTRL_EMI_BUSY_DCC_RESYNC(BV_CLKCTRL_EMI_BUSY_DCC_RESYNC__##e)
+#define BFM_CLKCTRL_EMI_BUSY_DCC_RESYNC_V(v)    BM_CLKCTRL_EMI_BUSY_DCC_RESYNC
+#define BP_CLKCTRL_EMI_DCC_RESYNC_ENABLE        16
+#define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE        0x10000
+#define BF_CLKCTRL_EMI_DCC_RESYNC_ENABLE(v)     (((v) & 0x1) << 16)
+#define BFM_CLKCTRL_EMI_DCC_RESYNC_ENABLE(v)    BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE
+#define BF_CLKCTRL_EMI_DCC_RESYNC_ENABLE_V(e)   BF_CLKCTRL_EMI_DCC_RESYNC_ENABLE(BV_CLKCTRL_EMI_DCC_RESYNC_ENABLE__##e)
+#define BFM_CLKCTRL_EMI_DCC_RESYNC_ENABLE_V(v)  BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE
+#define BP_CLKCTRL_EMI_DIV_XTAL                 8
+#define BM_CLKCTRL_EMI_DIV_XTAL                 0xf00
+#define BF_CLKCTRL_EMI_DIV_XTAL(v)              (((v) & 0xf) << 8)
+#define BFM_CLKCTRL_EMI_DIV_XTAL(v)             BM_CLKCTRL_EMI_DIV_XTAL
+#define BF_CLKCTRL_EMI_DIV_XTAL_V(e)            BF_CLKCTRL_EMI_DIV_XTAL(BV_CLKCTRL_EMI_DIV_XTAL__##e)
+#define BFM_CLKCTRL_EMI_DIV_XTAL_V(v)           BM_CLKCTRL_EMI_DIV_XTAL
+#define BP_CLKCTRL_EMI_DIV_EMI                  0
+#define BM_CLKCTRL_EMI_DIV_EMI                  0x3f
+#define BF_CLKCTRL_EMI_DIV_EMI(v)               (((v) & 0x3f) << 0)
+#define BFM_CLKCTRL_EMI_DIV_EMI(v)              BM_CLKCTRL_EMI_DIV_EMI
+#define BF_CLKCTRL_EMI_DIV_EMI_V(e)             BF_CLKCTRL_EMI_DIV_EMI(BV_CLKCTRL_EMI_DIV_EMI__##e)
+#define BFM_CLKCTRL_EMI_DIV_EMI_V(v)            BM_CLKCTRL_EMI_DIV_EMI
+
+#define HW_CLKCTRL_IR                   HW(CLKCTRL_IR)
+#define HWA_CLKCTRL_IR                  (0x80040000 + 0xb0)
+#define HWT_CLKCTRL_IR                  HWIO_32_RW
+#define HWN_CLKCTRL_IR                  CLKCTRL_IR
+#define HWI_CLKCTRL_IR                  
+#define BP_CLKCTRL_IR_CLKGATE           31
+#define BM_CLKCTRL_IR_CLKGATE           0x80000000
+#define BF_CLKCTRL_IR_CLKGATE(v)        (((v) & 0x1) << 31)
+#define BFM_CLKCTRL_IR_CLKGATE(v)       BM_CLKCTRL_IR_CLKGATE
+#define BF_CLKCTRL_IR_CLKGATE_V(e)      BF_CLKCTRL_IR_CLKGATE(BV_CLKCTRL_IR_CLKGATE__##e)
+#define BFM_CLKCTRL_IR_CLKGATE_V(v)     BM_CLKCTRL_IR_CLKGATE
+#define BP_CLKCTRL_IR_AUTO_DIV          29
+#define BM_CLKCTRL_IR_AUTO_DIV          0x20000000
+#define BF_CLKCTRL_IR_AUTO_DIV(v)       (((v) & 0x1) << 29)
+#define BFM_CLKCTRL_IR_AUTO_DIV(v)      BM_CLKCTRL_IR_AUTO_DIV
+#define BF_CLKCTRL_IR_AUTO_DIV_V(e)     BF_CLKCTRL_IR_AUTO_DIV(BV_CLKCTRL_IR_AUTO_DIV__##e)
+#define BFM_CLKCTRL_IR_AUTO_DIV_V(v)    BM_CLKCTRL_IR_AUTO_DIV
+#define BP_CLKCTRL_IR_IR_BUSY           28
+#define BM_CLKCTRL_IR_IR_BUSY           0x10000000
+#define BF_CLKCTRL_IR_IR_BUSY(v)        (((v) & 0x1) << 28)
+#define BFM_CLKCTRL_IR_IR_BUSY(v)       BM_CLKCTRL_IR_IR_BUSY
+#define BF_CLKCTRL_IR_IR_BUSY_V(e)      BF_CLKCTRL_IR_IR_BUSY(BV_CLKCTRL_IR_IR_BUSY__##e)
+#define BFM_CLKCTRL_IR_IR_BUSY_V(v)     BM_CLKCTRL_IR_IR_BUSY
+#define BP_CLKCTRL_IR_IROV_BUSY         27
+#define BM_CLKCTRL_IR_IROV_BUSY         0x8000000
+#define BF_CLKCTRL_IR_IROV_BUSY(v)      (((v) & 0x1) << 27)
+#define BFM_CLKCTRL_IR_IROV_BUSY(v)     BM_CLKCTRL_IR_IROV_BUSY
+#define BF_CLKCTRL_IR_IROV_BUSY_V(e)    BF_CLKCTRL_IR_IROV_BUSY(BV_CLKCTRL_IR_IROV_BUSY__##e)
+#define BFM_CLKCTRL_IR_IROV_BUSY_V(v)   BM_CLKCTRL_IR_IROV_BUSY
+#define BP_CLKCTRL_IR_IROV_DIV          16
+#define BM_CLKCTRL_IR_IROV_DIV          0x1ff0000
+#define BF_CLKCTRL_IR_IROV_DIV(v)       (((v) & 0x1ff) << 16)
+#define BFM_CLKCTRL_IR_IROV_DIV(v)      BM_CLKCTRL_IR_IROV_DIV
+#define BF_CLKCTRL_IR_IROV_DIV_V(e)     BF_CLKCTRL_IR_IROV_DIV(BV_CLKCTRL_IR_IROV_DIV__##e)
+#define BFM_CLKCTRL_IR_IROV_DIV_V(v)    BM_CLKCTRL_IR_IROV_DIV
+#define BP_CLKCTRL_IR_IR_DIV            0
+#define BM_CLKCTRL_IR_IR_DIV            0x3ff
+#define BF_CLKCTRL_IR_IR_DIV(v)         (((v) & 0x3ff) << 0)
+#define BFM_CLKCTRL_IR_IR_DIV(v)        BM_CLKCTRL_IR_IR_DIV
+#define BF_CLKCTRL_IR_IR_DIV_V(e)       BF_CLKCTRL_IR_IR_DIV(BV_CLKCTRL_IR_IR_DIV__##e)
+#define BFM_CLKCTRL_IR_IR_DIV_V(v)      BM_CLKCTRL_IR_IR_DIV
+
+#define HW_CLKCTRL_SAIF                     HW(CLKCTRL_SAIF)
+#define HWA_CLKCTRL_SAIF                    (0x80040000 + 0xc0)
+#define HWT_CLKCTRL_SAIF                    HWIO_32_RW
+#define HWN_CLKCTRL_SAIF                    CLKCTRL_SAIF
+#define HWI_CLKCTRL_SAIF                    
+#define BP_CLKCTRL_SAIF_CLKGATE             31
+#define BM_CLKCTRL_SAIF_CLKGATE             0x80000000
+#define BF_CLKCTRL_SAIF_CLKGATE(v)          (((v) & 0x1) << 31)
+#define BFM_CLKCTRL_SAIF_CLKGATE(v)         BM_CLKCTRL_SAIF_CLKGATE
+#define BF_CLKCTRL_SAIF_CLKGATE_V(e)        BF_CLKCTRL_SAIF_CLKGATE(BV_CLKCTRL_SAIF_CLKGATE__##e)
+#define BFM_CLKCTRL_SAIF_CLKGATE_V(v)       BM_CLKCTRL_SAIF_CLKGATE
+#define BP_CLKCTRL_SAIF_BUSY                29
+#define BM_CLKCTRL_SAIF_BUSY                0x20000000
+#define BF_CLKCTRL_SAIF_BUSY(v)             (((v) & 0x1) << 29)
+#define BFM_CLKCTRL_SAIF_BUSY(v)            BM_CLKCTRL_SAIF_BUSY
+#define BF_CLKCTRL_SAIF_BUSY_V(e)           BF_CLKCTRL_SAIF_BUSY(BV_CLKCTRL_SAIF_BUSY__##e)
+#define BFM_CLKCTRL_SAIF_BUSY_V(v)          BM_CLKCTRL_SAIF_BUSY
+#define BP_CLKCTRL_SAIF_DIV_FRAC_EN         16
+#define BM_CLKCTRL_SAIF_DIV_FRAC_EN         0x10000
+#define BF_CLKCTRL_SAIF_DIV_FRAC_EN(v)      (((v) & 0x1) << 16)
+#define BFM_CLKCTRL_SAIF_DIV_FRAC_EN(v)     BM_CLKCTRL_SAIF_DIV_FRAC_EN
+#define BF_CLKCTRL_SAIF_DIV_FRAC_EN_V(e)    BF_CLKCTRL_SAIF_DIV_FRAC_EN(BV_CLKCTRL_SAIF_DIV_FRAC_EN__##e)
+#define BFM_CLKCTRL_SAIF_DIV_FRAC_EN_V(v)   BM_CLKCTRL_SAIF_DIV_FRAC_EN
+#define BP_CLKCTRL_SAIF_DIV                 0
+#define BM_CLKCTRL_SAIF_DIV                 0xffff
+#define BF_CLKCTRL_SAIF_DIV(v)              (((v) & 0xffff) << 0)
+#define BFM_CLKCTRL_SAIF_DIV(v)             BM_CLKCTRL_SAIF_DIV
+#define BF_CLKCTRL_SAIF_DIV_V(e)            BF_CLKCTRL_SAIF_DIV(BV_CLKCTRL_SAIF_DIV__##e)
+#define BFM_CLKCTRL_SAIF_DIV_V(v)           BM_CLKCTRL_SAIF_DIV
+
+#define HW_CLKCTRL_FRAC                     HW(CLKCTRL_FRAC)
+#define HWA_CLKCTRL_FRAC                    (0x80040000 + 0xd0)
+#define HWT_CLKCTRL_FRAC                    HWIO_32_RW
+#define HWN_CLKCTRL_FRAC                    CLKCTRL_FRAC
+#define HWI_CLKCTRL_FRAC                    
+#define HW_CLKCTRL_FRAC_SET                 HW(CLKCTRL_FRAC_SET)
+#define HWA_CLKCTRL_FRAC_SET                (HWA_CLKCTRL_FRAC + 0x4)
+#define HWT_CLKCTRL_FRAC_SET                HWIO_32_WO
+#define HWN_CLKCTRL_FRAC_SET                CLKCTRL_FRAC
+#define HWI_CLKCTRL_FRAC_SET                
+#define HW_CLKCTRL_FRAC_CLR                 HW(CLKCTRL_FRAC_CLR)
+#define HWA_CLKCTRL_FRAC_CLR                (HWA_CLKCTRL_FRAC + 0x8)
+#define HWT_CLKCTRL_FRAC_CLR                HWIO_32_WO
+#define HWN_CLKCTRL_FRAC_CLR                CLKCTRL_FRAC
+#define HWI_CLKCTRL_FRAC_CLR                
+#define HW_CLKCTRL_FRAC_TOG                 HW(CLKCTRL_FRAC_TOG)
+#define HWA_CLKCTRL_FRAC_TOG                (HWA_CLKCTRL_FRAC + 0xc)
+#define HWT_CLKCTRL_FRAC_TOG                HWIO_32_WO
+#define HWN_CLKCTRL_FRAC_TOG                CLKCTRL_FRAC
+#define HWI_CLKCTRL_FRAC_TOG                
+#define BP_CLKCTRL_FRAC_CLKGATEIO           31
+#define BM_CLKCTRL_FRAC_CLKGATEIO           0x80000000
+#define BF_CLKCTRL_FRAC_CLKGATEIO(v)        (((v) & 0x1) << 31)
+#define BFM_CLKCTRL_FRAC_CLKGATEIO(v)       BM_CLKCTRL_FRAC_CLKGATEIO
+#define BF_CLKCTRL_FRAC_CLKGATEIO_V(e)      BF_CLKCTRL_FRAC_CLKGATEIO(BV_CLKCTRL_FRAC_CLKGATEIO__##e)
+#define BFM_CLKCTRL_FRAC_CLKGATEIO_V(v)     BM_CLKCTRL_FRAC_CLKGATEIO
+#define BP_CLKCTRL_FRAC_IO_STABLE           30
+#define BM_CLKCTRL_FRAC_IO_STABLE           0x40000000
+#define BF_CLKCTRL_FRAC_IO_STABLE(v)        (((v) & 0x1) << 30)
+#define BFM_CLKCTRL_FRAC_IO_STABLE(v)       BM_CLKCTRL_FRAC_IO_STABLE
+#define BF_CLKCTRL_FRAC_IO_STABLE_V(e)      BF_CLKCTRL_FRAC_IO_STABLE(BV_CLKCTRL_FRAC_IO_STABLE__##e)
+#define BFM_CLKCTRL_FRAC_IO_STABLE_V(v)     BM_CLKCTRL_FRAC_IO_STABLE
+#define BP_CLKCTRL_FRAC_IOFRAC              24
+#define BM_CLKCTRL_FRAC_IOFRAC              0x3f000000
+#define BF_CLKCTRL_FRAC_IOFRAC(v)           (((v) & 0x3f) << 24)
+#define BFM_CLKCTRL_FRAC_IOFRAC(v)          BM_CLKCTRL_FRAC_IOFRAC
+#define BF_CLKCTRL_FRAC_IOFRAC_V(e)         BF_CLKCTRL_FRAC_IOFRAC(BV_CLKCTRL_FRAC_IOFRAC__##e)
+#define BFM_CLKCTRL_FRAC_IOFRAC_V(v)        BM_CLKCTRL_FRAC_IOFRAC
+#define BP_CLKCTRL_FRAC_CLKGATEPIX          23
+#define BM_CLKCTRL_FRAC_CLKGATEPIX          0x800000
+#define BF_CLKCTRL_FRAC_CLKGATEPIX(v)       (((v) & 0x1) << 23)
+#define BFM_CLKCTRL_FRAC_CLKGATEPIX(v)      BM_CLKCTRL_FRAC_CLKGATEPIX
+#define BF_CLKCTRL_FRAC_CLKGATEPIX_V(e)     BF_CLKCTRL_FRAC_CLKGATEPIX(BV_CLKCTRL_FRAC_CLKGATEPIX__##e)
+#define BFM_CLKCTRL_FRAC_CLKGATEPIX_V(v)    BM_CLKCTRL_FRAC_CLKGATEPIX
+#define BP_CLKCTRL_FRAC_PIX_STABLE          22
+#define BM_CLKCTRL_FRAC_PIX_STABLE          0x400000
+#define BF_CLKCTRL_FRAC_PIX_STABLE(v)       (((v) & 0x1) << 22)
+#define BFM_CLKCTRL_FRAC_PIX_STABLE(v)      BM_CLKCTRL_FRAC_PIX_STABLE
+#define BF_CLKCTRL_FRAC_PIX_STABLE_V(e)     BF_CLKCTRL_FRAC_PIX_STABLE(BV_CLKCTRL_FRAC_PIX_STABLE__##e)
+#define BFM_CLKCTRL_FRAC_PIX_STABLE_V(v)    BM_CLKCTRL_FRAC_PIX_STABLE
+#define BP_CLKCTRL_FRAC_PIXFRAC             16
+#define BM_CLKCTRL_FRAC_PIXFRAC             0x3f0000
+#define BF_CLKCTRL_FRAC_PIXFRAC(v)          (((v) & 0x3f) << 16)
+#define BFM_CLKCTRL_FRAC_PIXFRAC(v)         BM_CLKCTRL_FRAC_PIXFRAC
+#define BF_CLKCTRL_FRAC_PIXFRAC_V(e)        BF_CLKCTRL_FRAC_PIXFRAC(BV_CLKCTRL_FRAC_PIXFRAC__##e)
+#define BFM_CLKCTRL_FRAC_PIXFRAC_V(v)       BM_CLKCTRL_FRAC_PIXFRAC
+#define BP_CLKCTRL_FRAC_CLKGATEEMI          15
+#define BM_CLKCTRL_FRAC_CLKGATEEMI          0x8000
+#define BF_CLKCTRL_FRAC_CLKGATEEMI(v)       (((v) & 0x1) << 15)
+#define BFM_CLKCTRL_FRAC_CLKGATEEMI(v)      BM_CLKCTRL_FRAC_CLKGATEEMI
+#define BF_CLKCTRL_FRAC_CLKGATEEMI_V(e)     BF_CLKCTRL_FRAC_CLKGATEEMI(BV_CLKCTRL_FRAC_CLKGATEEMI__##e)
+#define BFM_CLKCTRL_FRAC_CLKGATEEMI_V(v)    BM_CLKCTRL_FRAC_CLKGATEEMI
+#define BP_CLKCTRL_FRAC_EMI_STABLE          14
+#define BM_CLKCTRL_FRAC_EMI_STABLE          0x4000
+#define BF_CLKCTRL_FRAC_EMI_STABLE(v)       (((v) & 0x1) << 14)
+#define BFM_CLKCTRL_FRAC_EMI_STABLE(v)      BM_CLKCTRL_FRAC_EMI_STABLE
+#define BF_CLKCTRL_FRAC_EMI_STABLE_V(e)     BF_CLKCTRL_FRAC_EMI_STABLE(BV_CLKCTRL_FRAC_EMI_STABLE__##e)
+#define BFM_CLKCTRL_FRAC_EMI_STABLE_V(v)    BM_CLKCTRL_FRAC_EMI_STABLE
+#define BP_CLKCTRL_FRAC_EMIFRAC             8
+#define BM_CLKCTRL_FRAC_EMIFRAC             0x3f00
+#define BF_CLKCTRL_FRAC_EMIFRAC(v)          (((v) & 0x3f) << 8)
+#define BFM_CLKCTRL_FRAC_EMIFRAC(v)         BM_CLKCTRL_FRAC_EMIFRAC
+#define BF_CLKCTRL_FRAC_EMIFRAC_V(e)        BF_CLKCTRL_FRAC_EMIFRAC(BV_CLKCTRL_FRAC_EMIFRAC__##e)
+#define BFM_CLKCTRL_FRAC_EMIFRAC_V(v)       BM_CLKCTRL_FRAC_EMIFRAC
+#define BP_CLKCTRL_FRAC_CLKGATECPU          7
+#define BM_CLKCTRL_FRAC_CLKGATECPU          0x80
+#define BF_CLKCTRL_FRAC_CLKGATECPU(v)       (((v) & 0x1) << 7)
+#define BFM_CLKCTRL_FRAC_CLKGATECPU(v)      BM_CLKCTRL_FRAC_CLKGATECPU
+#define BF_CLKCTRL_FRAC_CLKGATECPU_V(e)     BF_CLKCTRL_FRAC_CLKGATECPU(BV_CLKCTRL_FRAC_CLKGATECPU__##e)
+#define BFM_CLKCTRL_FRAC_CLKGATECPU_V(v)    BM_CLKCTRL_FRAC_CLKGATECPU
+#define BP_CLKCTRL_FRAC_CPU_STABLE          6
+#define BM_CLKCTRL_FRAC_CPU_STABLE          0x40
+#define BF_CLKCTRL_FRAC_CPU_STABLE(v)       (((v) & 0x1) << 6)
+#define BFM_CLKCTRL_FRAC_CPU_STABLE(v)      BM_CLKCTRL_FRAC_CPU_STABLE
+#define BF_CLKCTRL_FRAC_CPU_STABLE_V(e)     BF_CLKCTRL_FRAC_CPU_STABLE(BV_CLKCTRL_FRAC_CPU_STABLE__##e)
+#define BFM_CLKCTRL_FRAC_CPU_STABLE_V(v)    BM_CLKCTRL_FRAC_CPU_STABLE
+#define BP_CLKCTRL_FRAC_CPUFRAC             0
+#define BM_CLKCTRL_FRAC_CPUFRAC             0x3f
+#define BF_CLKCTRL_FRAC_CPUFRAC(v)          (((v) & 0x3f) << 0)
+#define BFM_CLKCTRL_FRAC_CPUFRAC(v)         BM_CLKCTRL_FRAC_CPUFRAC
+#define BF_CLKCTRL_FRAC_CPUFRAC_V(e)        BF_CLKCTRL_FRAC_CPUFRAC(BV_CLKCTRL_FRAC_CPUFRAC__##e)
+#define BFM_CLKCTRL_FRAC_CPUFRAC_V(v)       BM_CLKCTRL_FRAC_CPUFRAC
+
+#define HW_CLKCTRL_CLKSEQ                   HW(CLKCTRL_CLKSEQ)
+#define HWA_CLKCTRL_CLKSEQ                  (0x80040000 + 0xe0)
+#define HWT_CLKCTRL_CLKSEQ                  HWIO_32_RW
+#define HWN_CLKCTRL_CLKSEQ                  CLKCTRL_CLKSEQ
+#define HWI_CLKCTRL_CLKSEQ                  
+#define HW_CLKCTRL_CLKSEQ_SET               HW(CLKCTRL_CLKSEQ_SET)
+#define HWA_CLKCTRL_CLKSEQ_SET              (HWA_CLKCTRL_CLKSEQ + 0x4)
+#define HWT_CLKCTRL_CLKSEQ_SET              HWIO_32_WO
+#define HWN_CLKCTRL_CLKSEQ_SET              CLKCTRL_CLKSEQ
+#define HWI_CLKCTRL_CLKSEQ_SET              
+#define HW_CLKCTRL_CLKSEQ_CLR               HW(CLKCTRL_CLKSEQ_CLR)
+#define HWA_CLKCTRL_CLKSEQ_CLR              (HWA_CLKCTRL_CLKSEQ + 0x8)
+#define HWT_CLKCTRL_CLKSEQ_CLR              HWIO_32_WO
+#define HWN_CLKCTRL_CLKSEQ_CLR              CLKCTRL_CLKSEQ
+#define HWI_CLKCTRL_CLKSEQ_CLR              
+#define HW_CLKCTRL_CLKSEQ_TOG               HW(CLKCTRL_CLKSEQ_TOG)
+#define HWA_CLKCTRL_CLKSEQ_TOG              (HWA_CLKCTRL_CLKSEQ + 0xc)
+#define HWT_CLKCTRL_CLKSEQ_TOG              HWIO_32_WO
+#define HWN_CLKCTRL_CLKSEQ_TOG              CLKCTRL_CLKSEQ
+#define HWI_CLKCTRL_CLKSEQ_TOG              
+#define BP_CLKCTRL_CLKSEQ_BYPASS_CPU        7
+#define BM_CLKCTRL_CLKSEQ_BYPASS_CPU        0x80
+#define BF_CLKCTRL_CLKSEQ_BYPASS_CPU(v)     (((v) & 0x1) << 7)
+#define BFM_CLKCTRL_CLKSEQ_BYPASS_CPU(v)    BM_CLKCTRL_CLKSEQ_BYPASS_CPU
+#define BF_CLKCTRL_CLKSEQ_BYPASS_CPU_V(e)   BF_CLKCTRL_CLKSEQ_BYPASS_CPU(BV_CLKCTRL_CLKSEQ_BYPASS_CPU__##e)
+#define BFM_CLKCTRL_CLKSEQ_BYPASS_CPU_V(v)  BM_CLKCTRL_CLKSEQ_BYPASS_CPU
+#define BP_CLKCTRL_CLKSEQ_BYPASS_EMI        6
+#define BM_CLKCTRL_CLKSEQ_BYPASS_EMI        0x40
+#define BF_CLKCTRL_CLKSEQ_BYPASS_EMI(v)     (((v) & 0x1) << 6)
+#define BFM_CLKCTRL_CLKSEQ_BYPASS_EMI(v)    BM_CLKCTRL_CLKSEQ_BYPASS_EMI
+#define BF_CLKCTRL_CLKSEQ_BYPASS_EMI_V(e)   BF_CLKCTRL_CLKSEQ_BYPASS_EMI(BV_CLKCTRL_CLKSEQ_BYPASS_EMI__##e)
+#define BFM_CLKCTRL_CLKSEQ_BYPASS_EMI_V(v)  BM_CLKCTRL_CLKSEQ_BYPASS_EMI
+#define BP_CLKCTRL_CLKSEQ_BYPASS_SSP        5
+#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP        0x20
+#define BF_CLKCTRL_CLKSEQ_BYPASS_SSP(v)     (((v) & 0x1) << 5)
+#define BFM_CLKCTRL_CLKSEQ_BYPASS_SSP(v)    BM_CLKCTRL_CLKSEQ_BYPASS_SSP
+#define BF_CLKCTRL_CLKSEQ_BYPASS_SSP_V(e)   BF_CLKCTRL_CLKSEQ_BYPASS_SSP(BV_CLKCTRL_CLKSEQ_BYPASS_SSP__##e)
+#define BFM_CLKCTRL_CLKSEQ_BYPASS_SSP_V(v)  BM_CLKCTRL_CLKSEQ_BYPASS_SSP
+#define BP_CLKCTRL_CLKSEQ_BYPASS_GPMI       4
+#define BM_CLKCTRL_CLKSEQ_BYPASS_GPMI       0x10
+#define BF_CLKCTRL_CLKSEQ_BYPASS_GPMI(v)    (((v) & 0x1) << 4)
+#define BFM_CLKCTRL_CLKSEQ_BYPASS_GPMI(v)   BM_CLKCTRL_CLKSEQ_BYPASS_GPMI
+#define BF_CLKCTRL_CLKSEQ_BYPASS_GPMI_V(e)  BF_CLKCTRL_CLKSEQ_BYPASS_GPMI(BV_CLKCTRL_CLKSEQ_BYPASS_GPMI__##e)
+#define BFM_CLKCTRL_CLKSEQ_BYPASS_GPMI_V(v) BM_CLKCTRL_CLKSEQ_BYPASS_GPMI
+#define BP_CLKCTRL_CLKSEQ_BYPASS_IR         3
+#define BM_CLKCTRL_CLKSEQ_BYPASS_IR         0x8
+#define BF_CLKCTRL_CLKSEQ_BYPASS_IR(v)      (((v) & 0x1) << 3)
+#define BFM_CLKCTRL_CLKSEQ_BYPASS_IR(v)     BM_CLKCTRL_CLKSEQ_BYPASS_IR
+#define BF_CLKCTRL_CLKSEQ_BYPASS_IR_V(e)    BF_CLKCTRL_CLKSEQ_BYPASS_IR(BV_CLKCTRL_CLKSEQ_BYPASS_IR__##e)
+#define BFM_CLKCTRL_CLKSEQ_BYPASS_IR_V(v)   BM_CLKCTRL_CLKSEQ_BYPASS_IR
+#define BP_CLKCTRL_CLKSEQ_BYPASS_PIX        1
+#define BM_CLKCTRL_CLKSEQ_BYPASS_PIX        0x2
+#define BF_CLKCTRL_CLKSEQ_BYPASS_PIX(v)     (((v) & 0x1) << 1)
+#define BFM_CLKCTRL_CLKSEQ_BYPASS_PIX(v)    BM_CLKCTRL_CLKSEQ_BYPASS_PIX
+#define BF_CLKCTRL_CLKSEQ_BYPASS_PIX_V(e)   BF_CLKCTRL_CLKSEQ_BYPASS_PIX(BV_CLKCTRL_CLKSEQ_BYPASS_PIX__##e)
+#define BFM_CLKCTRL_CLKSEQ_BYPASS_PIX_V(v)  BM_CLKCTRL_CLKSEQ_BYPASS_PIX
+#define BP_CLKCTRL_CLKSEQ_BYPASS_SAIF       0
+#define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF       0x1
+#define BF_CLKCTRL_CLKSEQ_BYPASS_SAIF(v)    (((v) & 0x1) << 0)
+#define BFM_CLKCTRL_CLKSEQ_BYPASS_SAIF(v)   BM_CLKCTRL_CLKSEQ_BYPASS_SAIF
+#define BF_CLKCTRL_CLKSEQ_BYPASS_SAIF_V(e)  BF_CLKCTRL_CLKSEQ_BYPASS_SAIF(BV_CLKCTRL_CLKSEQ_BYPASS_SAIF__##e)
+#define BFM_CLKCTRL_CLKSEQ_BYPASS_SAIF_V(v) BM_CLKCTRL_CLKSEQ_BYPASS_SAIF
+
+#define HW_CLKCTRL_RESET            HW(CLKCTRL_RESET)
+#define HWA_CLKCTRL_RESET           (0x80040000 + 0xf0)
+#define HWT_CLKCTRL_RESET           HWIO_32_RW
+#define HWN_CLKCTRL_RESET           CLKCTRL_RESET
+#define HWI_CLKCTRL_RESET           
+#define BP_CLKCTRL_RESET_CHIP       1
+#define BM_CLKCTRL_RESET_CHIP       0x2
+#define BF_CLKCTRL_RESET_CHIP(v)    (((v) & 0x1) << 1)
+#define BFM_CLKCTRL_RESET_CHIP(v)   BM_CLKCTRL_RESET_CHIP
+#define BF_CLKCTRL_RESET_CHIP_V(e)  BF_CLKCTRL_RESET_CHIP(BV_CLKCTRL_RESET_CHIP__##e)
+#define BFM_CLKCTRL_RESET_CHIP_V(v) BM_CLKCTRL_RESET_CHIP
+#define BP_CLKCTRL_RESET_DIG        0
+#define BM_CLKCTRL_RESET_DIG        0x1
+#define BF_CLKCTRL_RESET_DIG(v)     (((v) & 0x1) << 0)
+#define BFM_CLKCTRL_RESET_DIG(v)    BM_CLKCTRL_RESET_DIG
+#define BF_CLKCTRL_RESET_DIG_V(e)   BF_CLKCTRL_RESET_DIG(BV_CLKCTRL_RESET_DIG__##e)
+#define BFM_CLKCTRL_RESET_DIG_V(v)  BM_CLKCTRL_RESET_DIG
+
+#define HW_CLKCTRL_VERSION              HW(CLKCTRL_VERSION)
+#define HWA_CLKCTRL_VERSION             (0x80040000 + 0x100)
+#define HWT_CLKCTRL_VERSION             HWIO_32_RW
+#define HWN_CLKCTRL_VERSION             CLKCTRL_VERSION
+#define HWI_CLKCTRL_VERSION             
+#define BP_CLKCTRL_VERSION_MAJOR        24
+#define BM_CLKCTRL_VERSION_MAJOR        0xff000000
+#define BF_CLKCTRL_VERSION_MAJOR(v)     (((v) & 0xff) << 24)
+#define BFM_CLKCTRL_VERSION_MAJOR(v)    BM_CLKCTRL_VERSION_MAJOR
+#define BF_CLKCTRL_VERSION_MAJOR_V(e)   BF_CLKCTRL_VERSION_MAJOR(BV_CLKCTRL_VERSION_MAJOR__##e)
+#define BFM_CLKCTRL_VERSION_MAJOR_V(v)  BM_CLKCTRL_VERSION_MAJOR
+#define BP_CLKCTRL_VERSION_MINOR        16
+#define BM_CLKCTRL_VERSION_MINOR        0xff0000
+#define BF_CLKCTRL_VERSION_MINOR(v)     (((v) & 0xff) << 16)
+#define BFM_CLKCTRL_VERSION_MINOR(v)    BM_CLKCTRL_VERSION_MINOR
+#define BF_CLKCTRL_VERSION_MINOR_V(e)   BF_CLKCTRL_VERSION_MINOR(BV_CLKCTRL_VERSION_MINOR__##e)
+#define BFM_CLKCTRL_VERSION_MINOR_V(v)  BM_CLKCTRL_VERSION_MINOR
+#define BP_CLKCTRL_VERSION_STEP         0
+#define BM_CLKCTRL_VERSION_STEP         0xffff
+#define BF_CLKCTRL_VERSION_STEP(v)      (((v) & 0xffff) << 0)
+#define BFM_CLKCTRL_VERSION_STEP(v)     BM_CLKCTRL_VERSION_STEP
+#define BF_CLKCTRL_VERSION_STEP_V(e)    BF_CLKCTRL_VERSION_STEP(BV_CLKCTRL_VERSION_STEP__##e)
+#define BFM_CLKCTRL_VERSION_STEP_V(v)   BM_CLKCTRL_VERSION_STEP
+
+#endif /* __HEADERGEN_STMP3700_CLKCTRL_H__*/
diff --git a/firmware/target/arm/imx233/regs/stmp3700/dcp.h b/firmware/target/arm/imx233/regs/stmp3700/dcp.h
new file mode 100644
index 0000000000..beaedb329a
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3700/dcp.h
@@ -0,0 +1,1063 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * stmp3700 version: 2.4.0
+ * stmp3700 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_STMP3700_DCP_H__
+#define __HEADERGEN_STMP3700_DCP_H__
+
+#define HW_DCP_CTRL                                 HW(DCP_CTRL)
+#define HWA_DCP_CTRL                                (0x80028000 + 0x0)
+#define HWT_DCP_CTRL                                HWIO_32_RW
+#define HWN_DCP_CTRL                                DCP_CTRL
+#define HWI_DCP_CTRL                                
+#define HW_DCP_CTRL_SET                             HW(DCP_CTRL_SET)
+#define HWA_DCP_CTRL_SET                            (HWA_DCP_CTRL + 0x4)
+#define HWT_DCP_CTRL_SET                            HWIO_32_WO
+#define HWN_DCP_CTRL_SET                            DCP_CTRL
+#define HWI_DCP_CTRL_SET                            
+#define HW_DCP_CTRL_CLR                             HW(DCP_CTRL_CLR)
+#define HWA_DCP_CTRL_CLR                            (HWA_DCP_CTRL + 0x8)
+#define HWT_DCP_CTRL_CLR                            HWIO_32_WO
+#define HWN_DCP_CTRL_CLR                            DCP_CTRL
+#define HWI_DCP_CTRL_CLR                            
+#define HW_DCP_CTRL_TOG                             HW(DCP_CTRL_TOG)
+#define HWA_DCP_CTRL_TOG                            (HWA_DCP_CTRL + 0xc)
+#define HWT_DCP_CTRL_TOG                            HWIO_32_WO
+#define HWN_DCP_CTRL_TOG                            DCP_CTRL
+#define HWI_DCP_CTRL_TOG                            
+#define BP_DCP_CTRL_SFTRST                          31
+#define BM_DCP_CTRL_SFTRST                          0x80000000
+#define BF_DCP_CTRL_SFTRST(v)                       (((v) & 0x1) << 31)
+#define BFM_DCP_CTRL_SFTRST(v)                      BM_DCP_CTRL_SFTRST
+#define BF_DCP_CTRL_SFTRST_V(e)                     BF_DCP_CTRL_SFTRST(BV_DCP_CTRL_SFTRST__##e)
+#define BFM_DCP_CTRL_SFTRST_V(v)                    BM_DCP_CTRL_SFTRST
+#define BP_DCP_CTRL_CLKGATE                         30
+#define BM_DCP_CTRL_CLKGATE                         0x40000000
+#define BF_DCP_CTRL_CLKGATE(v)                      (((v) & 0x1) << 30)
+#define BFM_DCP_CTRL_CLKGATE(v)                     BM_DCP_CTRL_CLKGATE
+#define BF_DCP_CTRL_CLKGATE_V(e)                    BF_DCP_CTRL_CLKGATE(BV_DCP_CTRL_CLKGATE__##e)
+#define BFM_DCP_CTRL_CLKGATE_V(v)                   BM_DCP_CTRL_CLKGATE
+#define BP_DCP_CTRL_PRESENT_CRYPTO                  29
+#define BM_DCP_CTRL_PRESENT_CRYPTO                  0x20000000
+#define BV_DCP_CTRL_PRESENT_CRYPTO__Present         0x1
+#define BV_DCP_CTRL_PRESENT_CRYPTO__Absent          0x0
+#define BF_DCP_CTRL_PRESENT_CRYPTO(v)               (((v) & 0x1) << 29)
+#define BFM_DCP_CTRL_PRESENT_CRYPTO(v)              BM_DCP_CTRL_PRESENT_CRYPTO
+#define BF_DCP_CTRL_PRESENT_CRYPTO_V(e)             BF_DCP_CTRL_PRESENT_CRYPTO(BV_DCP_CTRL_PRESENT_CRYPTO__##e)
+#define BFM_DCP_CTRL_PRESENT_CRYPTO_V(v)            BM_DCP_CTRL_PRESENT_CRYPTO
+#define BP_DCP_CTRL_PRESENT_CSC                     28
+#define BM_DCP_CTRL_PRESENT_CSC                     0x10000000
+#define BV_DCP_CTRL_PRESENT_CSC__Present            0x1
+#define BV_DCP_CTRL_PRESENT_CSC__Absent             0x0
+#define BF_DCP_CTRL_PRESENT_CSC(v)                  (((v) & 0x1) << 28)
+#define BFM_DCP_CTRL_PRESENT_CSC(v)                 BM_DCP_CTRL_PRESENT_CSC
+#define BF_DCP_CTRL_PRESENT_CSC_V(e)                BF_DCP_CTRL_PRESENT_CSC(BV_DCP_CTRL_PRESENT_CSC__##e)
+#define BFM_DCP_CTRL_PRESENT_CSC_V(v)               BM_DCP_CTRL_PRESENT_CSC
+#define BP_DCP_CTRL_GATHER_RESIDUAL_WRITES          23
+#define BM_DCP_CTRL_GATHER_RESIDUAL_WRITES          0x800000
+#define BF_DCP_CTRL_GATHER_RESIDUAL_WRITES(v)       (((v) & 0x1) << 23)
+#define BFM_DCP_CTRL_GATHER_RESIDUAL_WRITES(v)      BM_DCP_CTRL_GATHER_RESIDUAL_WRITES
+#define BF_DCP_CTRL_GATHER_RESIDUAL_WRITES_V(e)     BF_DCP_CTRL_GATHER_RESIDUAL_WRITES(BV_DCP_CTRL_GATHER_RESIDUAL_WRITES__##e)
+#define BFM_DCP_CTRL_GATHER_RESIDUAL_WRITES_V(v)    BM_DCP_CTRL_GATHER_RESIDUAL_WRITES
+#define BP_DCP_CTRL_ENABLE_CONTEXT_CACHING          22
+#define BM_DCP_CTRL_ENABLE_CONTEXT_CACHING          0x400000
+#define BF_DCP_CTRL_ENABLE_CONTEXT_CACHING(v)       (((v) & 0x1) << 22)
+#define BFM_DCP_CTRL_ENABLE_CONTEXT_CACHING(v)      BM_DCP_CTRL_ENABLE_CONTEXT_CACHING
+#define BF_DCP_CTRL_ENABLE_CONTEXT_CACHING_V(e)     BF_DCP_CTRL_ENABLE_CONTEXT_CACHING(BV_DCP_CTRL_ENABLE_CONTEXT_CACHING__##e)
+#define BFM_DCP_CTRL_ENABLE_CONTEXT_CACHING_V(v)    BM_DCP_CTRL_ENABLE_CONTEXT_CACHING
+#define BP_DCP_CTRL_ENABLE_CONTEXT_SWITCHING        21
+#define BM_DCP_CTRL_ENABLE_CONTEXT_SWITCHING        0x200000
+#define BF_DCP_CTRL_ENABLE_CONTEXT_SWITCHING(v)     (((v) & 0x1) << 21)
+#define BFM_DCP_CTRL_ENABLE_CONTEXT_SWITCHING(v)    BM_DCP_CTRL_ENABLE_CONTEXT_SWITCHING
+#define BF_DCP_CTRL_ENABLE_CONTEXT_SWITCHING_V(e)   BF_DCP_CTRL_ENABLE_CONTEXT_SWITCHING(BV_DCP_CTRL_ENABLE_CONTEXT_SWITCHING__##e)
+#define BFM_DCP_CTRL_ENABLE_CONTEXT_SWITCHING_V(v)  BM_DCP_CTRL_ENABLE_CONTEXT_SWITCHING
+#define BP_DCP_CTRL_CSC_INTERRUPT_ENABLE            8
+#define BM_DCP_CTRL_CSC_INTERRUPT_ENABLE            0x100
+#define BF_DCP_CTRL_CSC_INTERRUPT_ENABLE(v)         (((v) & 0x1) << 8)
+#define BFM_DCP_CTRL_CSC_INTERRUPT_ENABLE(v)        BM_DCP_CTRL_CSC_INTERRUPT_ENABLE
+#define BF_DCP_CTRL_CSC_INTERRUPT_ENABLE_V(e)       BF_DCP_CTRL_CSC_INTERRUPT_ENABLE(BV_DCP_CTRL_CSC_INTERRUPT_ENABLE__##e)
+#define BFM_DCP_CTRL_CSC_INTERRUPT_ENABLE_V(v)      BM_DCP_CTRL_CSC_INTERRUPT_ENABLE
+#define BP_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE        0
+#define BM_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE        0xff
+#define BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__CH0   0x1
+#define BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__CH1   0x2
+#define BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__CH2   0x4
+#define BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__CH3   0x8
+#define BF_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE(v)     (((v) & 0xff) << 0)
+#define BFM_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE(v)    BM_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE
+#define BF_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_V(e)   BF_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE(BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__##e)
+#define BFM_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_V(v)  BM_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE
+
+#define HW_DCP_STAT                         HW(DCP_STAT)
+#define HWA_DCP_STAT                        (0x80028000 + 0x10)
+#define HWT_DCP_STAT                        HWIO_32_RW
+#define HWN_DCP_STAT                        DCP_STAT
+#define HWI_DCP_STAT                        
+#define HW_DCP_STAT_SET                     HW(DCP_STAT_SET)
+#define HWA_DCP_STAT_SET                    (HWA_DCP_STAT + 0x4)
+#define HWT_DCP_STAT_SET                    HWIO_32_WO
+#define HWN_DCP_STAT_SET                    DCP_STAT
+#define HWI_DCP_STAT_SET                    
+#define HW_DCP_STAT_CLR                     HW(DCP_STAT_CLR)
+#define HWA_DCP_STAT_CLR                    (HWA_DCP_STAT + 0x8)
+#define HWT_DCP_STAT_CLR                    HWIO_32_WO
+#define HWN_DCP_STAT_CLR                    DCP_STAT
+#define HWI_DCP_STAT_CLR                    
+#define HW_DCP_STAT_TOG                     HW(DCP_STAT_TOG)
+#define HWA_DCP_STAT_TOG                    (HWA_DCP_STAT + 0xc)
+#define HWT_DCP_STAT_TOG                    HWIO_32_WO
+#define HWN_DCP_STAT_TOG                    DCP_STAT
+#define HWI_DCP_STAT_TOG                    
+#define BP_DCP_STAT_OTP_KEY_READY           28
+#define BM_DCP_STAT_OTP_KEY_READY           0x10000000
+#define BF_DCP_STAT_OTP_KEY_READY(v)        (((v) & 0x1) << 28)
+#define BFM_DCP_STAT_OTP_KEY_READY(v)       BM_DCP_STAT_OTP_KEY_READY
+#define BF_DCP_STAT_OTP_KEY_READY_V(e)      BF_DCP_STAT_OTP_KEY_READY(BV_DCP_STAT_OTP_KEY_READY__##e)
+#define BFM_DCP_STAT_OTP_KEY_READY_V(v)     BM_DCP_STAT_OTP_KEY_READY
+#define BP_DCP_STAT_CUR_CHANNEL             24
+#define BM_DCP_STAT_CUR_CHANNEL             0xf000000
+#define BV_DCP_STAT_CUR_CHANNEL__None       0x0
+#define BV_DCP_STAT_CUR_CHANNEL__CH0        0x1
+#define BV_DCP_STAT_CUR_CHANNEL__CH1        0x2
+#define BV_DCP_STAT_CUR_CHANNEL__CH2        0x3
+#define BV_DCP_STAT_CUR_CHANNEL__CH3        0x4
+#define BV_DCP_STAT_CUR_CHANNEL__CSC        0x8
+#define BF_DCP_STAT_CUR_CHANNEL(v)          (((v) & 0xf) << 24)
+#define BFM_DCP_STAT_CUR_CHANNEL(v)         BM_DCP_STAT_CUR_CHANNEL
+#define BF_DCP_STAT_CUR_CHANNEL_V(e)        BF_DCP_STAT_CUR_CHANNEL(BV_DCP_STAT_CUR_CHANNEL__##e)
+#define BFM_DCP_STAT_CUR_CHANNEL_V(v)       BM_DCP_STAT_CUR_CHANNEL
+#define BP_DCP_STAT_READY_CHANNELS          16
+#define BM_DCP_STAT_READY_CHANNELS          0xff0000
+#define BV_DCP_STAT_READY_CHANNELS__CH0     0x1
+#define BV_DCP_STAT_READY_CHANNELS__CH1     0x2
+#define BV_DCP_STAT_READY_CHANNELS__CH2     0x4
+#define BV_DCP_STAT_READY_CHANNELS__CH3     0x8
+#define BF_DCP_STAT_READY_CHANNELS(v)       (((v) & 0xff) << 16)
+#define BFM_DCP_STAT_READY_CHANNELS(v)      BM_DCP_STAT_READY_CHANNELS
+#define BF_DCP_STAT_READY_CHANNELS_V(e)     BF_DCP_STAT_READY_CHANNELS(BV_DCP_STAT_READY_CHANNELS__##e)
+#define BFM_DCP_STAT_READY_CHANNELS_V(v)    BM_DCP_STAT_READY_CHANNELS
+#define BP_DCP_STAT_CSCIRQ                  8
+#define BM_DCP_STAT_CSCIRQ                  0x100
+#define BF_DCP_STAT_CSCIRQ(v)               (((v) & 0x1) << 8)
+#define BFM_DCP_STAT_CSCIRQ(v)              BM_DCP_STAT_CSCIRQ
+#define BF_DCP_STAT_CSCIRQ_V(e)             BF_DCP_STAT_CSCIRQ(BV_DCP_STAT_CSCIRQ__##e)
+#define BFM_DCP_STAT_CSCIRQ_V(v)            BM_DCP_STAT_CSCIRQ
+#define BP_DCP_STAT_IRQ                     0
+#define BM_DCP_STAT_IRQ                     0xf
+#define BF_DCP_STAT_IRQ(v)                  (((v) & 0xf) << 0)
+#define BFM_DCP_STAT_IRQ(v)                 BM_DCP_STAT_IRQ
+#define BF_DCP_STAT_IRQ_V(e)                BF_DCP_STAT_IRQ(BV_DCP_STAT_IRQ__##e)
+#define BFM_DCP_STAT_IRQ_V(v)               BM_DCP_STAT_IRQ
+
+#define HW_DCP_CHANNELCTRL                              HW(DCP_CHANNELCTRL)
+#define HWA_DCP_CHANNELCTRL                             (0x80028000 + 0x20)
+#define HWT_DCP_CHANNELCTRL                             HWIO_32_RW
+#define HWN_DCP_CHANNELCTRL                             DCP_CHANNELCTRL
+#define HWI_DCP_CHANNELCTRL                             
+#define HW_DCP_CHANNELCTRL_SET                          HW(DCP_CHANNELCTRL_SET)
+#define HWA_DCP_CHANNELCTRL_SET                         (HWA_DCP_CHANNELCTRL + 0x4)
+#define HWT_DCP_CHANNELCTRL_SET                         HWIO_32_WO
+#define HWN_DCP_CHANNELCTRL_SET                         DCP_CHANNELCTRL
+#define HWI_DCP_CHANNELCTRL_SET                         
+#define HW_DCP_CHANNELCTRL_CLR                          HW(DCP_CHANNELCTRL_CLR)
+#define HWA_DCP_CHANNELCTRL_CLR                         (HWA_DCP_CHANNELCTRL + 0x8)
+#define HWT_DCP_CHANNELCTRL_CLR                         HWIO_32_WO
+#define HWN_DCP_CHANNELCTRL_CLR                         DCP_CHANNELCTRL
+#define HWI_DCP_CHANNELCTRL_CLR                         
+#define HW_DCP_CHANNELCTRL_TOG                          HW(DCP_CHANNELCTRL_TOG)
+#define HWA_DCP_CHANNELCTRL_TOG                         (HWA_DCP_CHANNELCTRL + 0xc)
+#define HWT_DCP_CHANNELCTRL_TOG                         HWIO_32_WO
+#define HWN_DCP_CHANNELCTRL_TOG                         DCP_CHANNELCTRL
+#define HWI_DCP_CHANNELCTRL_TOG                         
+#define BP_DCP_CHANNELCTRL_CSC_PRIORITY                 17
+#define BM_DCP_CHANNELCTRL_CSC_PRIORITY                 0x60000
+#define BV_DCP_CHANNELCTRL_CSC_PRIORITY__HIGH           0x3
+#define BV_DCP_CHANNELCTRL_CSC_PRIORITY__MED            0x2
+#define BV_DCP_CHANNELCTRL_CSC_PRIORITY__LOW            0x1
+#define BV_DCP_CHANNELCTRL_CSC_PRIORITY__BACKGROUND     0x0
+#define BF_DCP_CHANNELCTRL_CSC_PRIORITY(v)              (((v) & 0x3) << 17)
+#define BFM_DCP_CHANNELCTRL_CSC_PRIORITY(v)             BM_DCP_CHANNELCTRL_CSC_PRIORITY
+#define BF_DCP_CHANNELCTRL_CSC_PRIORITY_V(e)            BF_DCP_CHANNELCTRL_CSC_PRIORITY(BV_DCP_CHANNELCTRL_CSC_PRIORITY__##e)
+#define BFM_DCP_CHANNELCTRL_CSC_PRIORITY_V(v)           BM_DCP_CHANNELCTRL_CSC_PRIORITY
+#define BP_DCP_CHANNELCTRL_CH0_IRQ_MERGED               16
+#define BM_DCP_CHANNELCTRL_CH0_IRQ_MERGED               0x10000
+#define BF_DCP_CHANNELCTRL_CH0_IRQ_MERGED(v)            (((v) & 0x1) << 16)
+#define BFM_DCP_CHANNELCTRL_CH0_IRQ_MERGED(v)           BM_DCP_CHANNELCTRL_CH0_IRQ_MERGED
+#define BF_DCP_CHANNELCTRL_CH0_IRQ_MERGED_V(e)          BF_DCP_CHANNELCTRL_CH0_IRQ_MERGED(BV_DCP_CHANNELCTRL_CH0_IRQ_MERGED__##e)
+#define BFM_DCP_CHANNELCTRL_CH0_IRQ_MERGED_V(v)         BM_DCP_CHANNELCTRL_CH0_IRQ_MERGED
+#define BP_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL        8
+#define BM_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL        0xff00
+#define BV_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL__CH0   0x1
+#define BV_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL__CH1   0x2
+#define BV_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL__CH2   0x4
+#define BV_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL__CH3   0x8
+#define BF_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL(v)     (((v) & 0xff) << 8)
+#define BFM_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL(v)    BM_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL
+#define BF_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_V(e)   BF_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL(BV_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL__##e)
+#define BFM_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_V(v)  BM_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL
+#define BP_DCP_CHANNELCTRL_ENABLE_CHANNEL               0
+#define BM_DCP_CHANNELCTRL_ENABLE_CHANNEL               0xff
+#define BV_DCP_CHANNELCTRL_ENABLE_CHANNEL__CH0          0x1
+#define BV_DCP_CHANNELCTRL_ENABLE_CHANNEL__CH1          0x2
+#define BV_DCP_CHANNELCTRL_ENABLE_CHANNEL__CH2          0x4
+#define BV_DCP_CHANNELCTRL_ENABLE_CHANNEL__CH3          0x8
+#define BF_DCP_CHANNELCTRL_ENABLE_CHANNEL(v)            (((v) & 0xff) << 0)
+#define BFM_DCP_CHANNELCTRL_ENABLE_CHANNEL(v)           BM_DCP_CHANNELCTRL_ENABLE_CHANNEL
+#define BF_DCP_CHANNELCTRL_ENABLE_CHANNEL_V(e)          BF_DCP_CHANNELCTRL_ENABLE_CHANNEL(BV_DCP_CHANNELCTRL_ENABLE_CHANNEL__##e)
+#define BFM_DCP_CHANNELCTRL_ENABLE_CHANNEL_V(v)         BM_DCP_CHANNELCTRL_ENABLE_CHANNEL
+
+#define HW_DCP_CAPABILITY0                      HW(DCP_CAPABILITY0)
+#define HWA_DCP_CAPABILITY0                     (0x80028000 + 0x30)
+#define HWT_DCP_CAPABILITY0                     HWIO_32_RW
+#define HWN_DCP_CAPABILITY0                     DCP_CAPABILITY0
+#define HWI_DCP_CAPABILITY0                     
+#define BP_DCP_CAPABILITY0_NUM_CHANNELS         8
+#define BM_DCP_CAPABILITY0_NUM_CHANNELS         0xf00
+#define BF_DCP_CAPABILITY0_NUM_CHANNELS(v)      (((v) & 0xf) << 8)
+#define BFM_DCP_CAPABILITY0_NUM_CHANNELS(v)     BM_DCP_CAPABILITY0_NUM_CHANNELS
+#define BF_DCP_CAPABILITY0_NUM_CHANNELS_V(e)    BF_DCP_CAPABILITY0_NUM_CHANNELS(BV_DCP_CAPABILITY0_NUM_CHANNELS__##e)
+#define BFM_DCP_CAPABILITY0_NUM_CHANNELS_V(v)   BM_DCP_CAPABILITY0_NUM_CHANNELS
+#define BP_DCP_CAPABILITY0_NUM_KEYS             0
+#define BM_DCP_CAPABILITY0_NUM_KEYS             0xff
+#define BF_DCP_CAPABILITY0_NUM_KEYS(v)          (((v) & 0xff) << 0)
+#define BFM_DCP_CAPABILITY0_NUM_KEYS(v)         BM_DCP_CAPABILITY0_NUM_KEYS
+#define BF_DCP_CAPABILITY0_NUM_KEYS_V(e)        BF_DCP_CAPABILITY0_NUM_KEYS(BV_DCP_CAPABILITY0_NUM_KEYS__##e)
+#define BFM_DCP_CAPABILITY0_NUM_KEYS_V(v)       BM_DCP_CAPABILITY0_NUM_KEYS
+
+#define HW_DCP_CAPABILITY1                              HW(DCP_CAPABILITY1)
+#define HWA_DCP_CAPABILITY1                             (0x80028000 + 0x40)
+#define HWT_DCP_CAPABILITY1                             HWIO_32_RW
+#define HWN_DCP_CAPABILITY1                             DCP_CAPABILITY1
+#define HWI_DCP_CAPABILITY1                             
+#define BP_DCP_CAPABILITY1_HASH_ALGORITHMS              16
+#define BM_DCP_CAPABILITY1_HASH_ALGORITHMS              0xffff0000
+#define BV_DCP_CAPABILITY1_HASH_ALGORITHMS__SHA1        0x1
+#define BV_DCP_CAPABILITY1_HASH_ALGORITHMS__CRC32       0x2
+#define BF_DCP_CAPABILITY1_HASH_ALGORITHMS(v)           (((v) & 0xffff) << 16)
+#define BFM_DCP_CAPABILITY1_HASH_ALGORITHMS(v)          BM_DCP_CAPABILITY1_HASH_ALGORITHMS
+#define BF_DCP_CAPABILITY1_HASH_ALGORITHMS_V(e)         BF_DCP_CAPABILITY1_HASH_ALGORITHMS(BV_DCP_CAPABILITY1_HASH_ALGORITHMS__##e)
+#define BFM_DCP_CAPABILITY1_HASH_ALGORITHMS_V(v)        BM_DCP_CAPABILITY1_HASH_ALGORITHMS
+#define BP_DCP_CAPABILITY1_CIPHER_ALGORITHMS            0
+#define BM_DCP_CAPABILITY1_CIPHER_ALGORITHMS            0xffff
+#define BV_DCP_CAPABILITY1_CIPHER_ALGORITHMS__AES128    0x1
+#define BF_DCP_CAPABILITY1_CIPHER_ALGORITHMS(v)         (((v) & 0xffff) << 0)
+#define BFM_DCP_CAPABILITY1_CIPHER_ALGORITHMS(v)        BM_DCP_CAPABILITY1_CIPHER_ALGORITHMS
+#define BF_DCP_CAPABILITY1_CIPHER_ALGORITHMS_V(e)       BF_DCP_CAPABILITY1_CIPHER_ALGORITHMS(BV_DCP_CAPABILITY1_CIPHER_ALGORITHMS__##e)
+#define BFM_DCP_CAPABILITY1_CIPHER_ALGORITHMS_V(v)      BM_DCP_CAPABILITY1_CIPHER_ALGORITHMS
+
+#define HW_DCP_CONTEXT              HW(DCP_CONTEXT)
+#define HWA_DCP_CONTEXT             (0x80028000 + 0x50)
+#define HWT_DCP_CONTEXT             HWIO_32_RW
+#define HWN_DCP_CONTEXT             DCP_CONTEXT
+#define HWI_DCP_CONTEXT             
+#define BP_DCP_CONTEXT_ADDR         0
+#define BM_DCP_CONTEXT_ADDR         0xffffffff
+#define BF_DCP_CONTEXT_ADDR(v)      (((v) & 0xffffffff) << 0)
+#define BFM_DCP_CONTEXT_ADDR(v)     BM_DCP_CONTEXT_ADDR
+#define BF_DCP_CONTEXT_ADDR_V(e)    BF_DCP_CONTEXT_ADDR(BV_DCP_CONTEXT_ADDR__##e)
+#define BFM_DCP_CONTEXT_ADDR_V(v)   BM_DCP_CONTEXT_ADDR
+
+#define HW_DCP_KEY                  HW(DCP_KEY)
+#define HWA_DCP_KEY                 (0x80028000 + 0x60)
+#define HWT_DCP_KEY                 HWIO_32_RW
+#define HWN_DCP_KEY                 DCP_KEY
+#define HWI_DCP_KEY                 
+#define BP_DCP_KEY_INDEX            4
+#define BM_DCP_KEY_INDEX            0x30
+#define BF_DCP_KEY_INDEX(v)         (((v) & 0x3) << 4)
+#define BFM_DCP_KEY_INDEX(v)        BM_DCP_KEY_INDEX
+#define BF_DCP_KEY_INDEX_V(e)       BF_DCP_KEY_INDEX(BV_DCP_KEY_INDEX__##e)
+#define BFM_DCP_KEY_INDEX_V(v)      BM_DCP_KEY_INDEX
+#define BP_DCP_KEY_SUBWORD          0
+#define BM_DCP_KEY_SUBWORD          0x3
+#define BF_DCP_KEY_SUBWORD(v)       (((v) & 0x3) << 0)
+#define BFM_DCP_KEY_SUBWORD(v)      BM_DCP_KEY_SUBWORD
+#define BF_DCP_KEY_SUBWORD_V(e)     BF_DCP_KEY_SUBWORD(BV_DCP_KEY_SUBWORD__##e)
+#define BFM_DCP_KEY_SUBWORD_V(v)    BM_DCP_KEY_SUBWORD
+
+#define HW_DCP_KEYDATA              HW(DCP_KEYDATA)
+#define HWA_DCP_KEYDATA             (0x80028000 + 0x70)
+#define HWT_DCP_KEYDATA             HWIO_32_RW
+#define HWN_DCP_KEYDATA             DCP_KEYDATA
+#define HWI_DCP_KEYDATA             
+#define BP_DCP_KEYDATA_DATA         0
+#define BM_DCP_KEYDATA_DATA         0xffffffff
+#define BF_DCP_KEYDATA_DATA(v)      (((v) & 0xffffffff) << 0)
+#define BFM_DCP_KEYDATA_DATA(v)     BM_DCP_KEYDATA_DATA
+#define BF_DCP_KEYDATA_DATA_V(e)    BF_DCP_KEYDATA_DATA(BV_DCP_KEYDATA_DATA__##e)
+#define BFM_DCP_KEYDATA_DATA_V(v)   BM_DCP_KEYDATA_DATA
+
+#define HW_DCP_PACKET0              HW(DCP_PACKET0)
+#define HWA_DCP_PACKET0             (0x80028000 + 0x80)
+#define HWT_DCP_PACKET0             HWIO_32_RW
+#define HWN_DCP_PACKET0             DCP_PACKET0
+#define HWI_DCP_PACKET0             
+#define BP_DCP_PACKET0_ADDR         0
+#define BM_DCP_PACKET0_ADDR         0xffffffff
+#define BF_DCP_PACKET0_ADDR(v)      (((v) & 0xffffffff) << 0)
+#define BFM_DCP_PACKET0_ADDR(v)     BM_DCP_PACKET0_ADDR
+#define BF_DCP_PACKET0_ADDR_V(e)    BF_DCP_PACKET0_ADDR(BV_DCP_PACKET0_ADDR__##e)
+#define BFM_DCP_PACKET0_ADDR_V(v)   BM_DCP_PACKET0_ADDR
+
+#define HW_DCP_PACKET1                          HW(DCP_PACKET1)
+#define HWA_DCP_PACKET1                         (0x80028000 + 0x90)
+#define HWT_DCP_PACKET1                         HWIO_32_RW
+#define HWN_DCP_PACKET1                         DCP_PACKET1
+#define HWI_DCP_PACKET1                         
+#define BP_DCP_PACKET1_TAG                      24
+#define BM_DCP_PACKET1_TAG                      0xff000000
+#define BF_DCP_PACKET1_TAG(v)                   (((v) & 0xff) << 24)
+#define BFM_DCP_PACKET1_TAG(v)                  BM_DCP_PACKET1_TAG
+#define BF_DCP_PACKET1_TAG_V(e)                 BF_DCP_PACKET1_TAG(BV_DCP_PACKET1_TAG__##e)
+#define BFM_DCP_PACKET1_TAG_V(v)                BM_DCP_PACKET1_TAG
+#define BP_DCP_PACKET1_OUTPUT_WORDSWAP          23
+#define BM_DCP_PACKET1_OUTPUT_WORDSWAP          0x800000
+#define BF_DCP_PACKET1_OUTPUT_WORDSWAP(v)       (((v) & 0x1) << 23)
+#define BFM_DCP_PACKET1_OUTPUT_WORDSWAP(v)      BM_DCP_PACKET1_OUTPUT_WORDSWAP
+#define BF_DCP_PACKET1_OUTPUT_WORDSWAP_V(e)     BF_DCP_PACKET1_OUTPUT_WORDSWAP(BV_DCP_PACKET1_OUTPUT_WORDSWAP__##e)
+#define BFM_DCP_PACKET1_OUTPUT_WORDSWAP_V(v)    BM_DCP_PACKET1_OUTPUT_WORDSWAP
+#define BP_DCP_PACKET1_OUTPUT_BYTESWAP          22
+#define BM_DCP_PACKET1_OUTPUT_BYTESWAP          0x400000
+#define BF_DCP_PACKET1_OUTPUT_BYTESWAP(v)       (((v) & 0x1) << 22)
+#define BFM_DCP_PACKET1_OUTPUT_BYTESWAP(v)      BM_DCP_PACKET1_OUTPUT_BYTESWAP
+#define BF_DCP_PACKET1_OUTPUT_BYTESWAP_V(e)     BF_DCP_PACKET1_OUTPUT_BYTESWAP(BV_DCP_PACKET1_OUTPUT_BYTESWAP__##e)
+#define BFM_DCP_PACKET1_OUTPUT_BYTESWAP_V(v)    BM_DCP_PACKET1_OUTPUT_BYTESWAP
+#define BP_DCP_PACKET1_INPUT_WORDSWAP           21
+#define BM_DCP_PACKET1_INPUT_WORDSWAP           0x200000
+#define BF_DCP_PACKET1_INPUT_WORDSWAP(v)        (((v) & 0x1) << 21)
+#define BFM_DCP_PACKET1_INPUT_WORDSWAP(v)       BM_DCP_PACKET1_INPUT_WORDSWAP
+#define BF_DCP_PACKET1_INPUT_WORDSWAP_V(e)      BF_DCP_PACKET1_INPUT_WORDSWAP(BV_DCP_PACKET1_INPUT_WORDSWAP__##e)
+#define BFM_DCP_PACKET1_INPUT_WORDSWAP_V(v)     BM_DCP_PACKET1_INPUT_WORDSWAP
+#define BP_DCP_PACKET1_INPUT_BYTESWAP           20
+#define BM_DCP_PACKET1_INPUT_BYTESWAP           0x100000
+#define BF_DCP_PACKET1_INPUT_BYTESWAP(v)        (((v) & 0x1) << 20)
+#define BFM_DCP_PACKET1_INPUT_BYTESWAP(v)       BM_DCP_PACKET1_INPUT_BYTESWAP
+#define BF_DCP_PACKET1_INPUT_BYTESWAP_V(e)      BF_DCP_PACKET1_INPUT_BYTESWAP(BV_DCP_PACKET1_INPUT_BYTESWAP__##e)
+#define BFM_DCP_PACKET1_INPUT_BYTESWAP_V(v)     BM_DCP_PACKET1_INPUT_BYTESWAP
+#define BP_DCP_PACKET1_KEY_WORDSWAP             19
+#define BM_DCP_PACKET1_KEY_WORDSWAP             0x80000
+#define BF_DCP_PACKET1_KEY_WORDSWAP(v)          (((v) & 0x1) << 19)
+#define BFM_DCP_PACKET1_KEY_WORDSWAP(v)         BM_DCP_PACKET1_KEY_WORDSWAP
+#define BF_DCP_PACKET1_KEY_WORDSWAP_V(e)        BF_DCP_PACKET1_KEY_WORDSWAP(BV_DCP_PACKET1_KEY_WORDSWAP__##e)
+#define BFM_DCP_PACKET1_KEY_WORDSWAP_V(v)       BM_DCP_PACKET1_KEY_WORDSWAP
+#define BP_DCP_PACKET1_KEY_BYTESWAP             18
+#define BM_DCP_PACKET1_KEY_BYTESWAP             0x40000
+#define BF_DCP_PACKET1_KEY_BYTESWAP(v)          (((v) & 0x1) << 18)
+#define BFM_DCP_PACKET1_KEY_BYTESWAP(v)         BM_DCP_PACKET1_KEY_BYTESWAP
+#define BF_DCP_PACKET1_KEY_BYTESWAP_V(e)        BF_DCP_PACKET1_KEY_BYTESWAP(BV_DCP_PACKET1_KEY_BYTESWAP__##e)
+#define BFM_DCP_PACKET1_KEY_BYTESWAP_V(v)       BM_DCP_PACKET1_KEY_BYTESWAP
+#define BP_DCP_PACKET1_TEST_SEMA_IRQ            17
+#define BM_DCP_PACKET1_TEST_SEMA_IRQ            0x20000
+#define BF_DCP_PACKET1_TEST_SEMA_IRQ(v)         (((v) & 0x1) << 17)
+#define BFM_DCP_PACKET1_TEST_SEMA_IRQ(v)        BM_DCP_PACKET1_TEST_SEMA_IRQ
+#define BF_DCP_PACKET1_TEST_SEMA_IRQ_V(e)       BF_DCP_PACKET1_TEST_SEMA_IRQ(BV_DCP_PACKET1_TEST_SEMA_IRQ__##e)
+#define BFM_DCP_PACKET1_TEST_SEMA_IRQ_V(v)      BM_DCP_PACKET1_TEST_SEMA_IRQ
+#define BP_DCP_PACKET1_CONSTANT_FILL            16
+#define BM_DCP_PACKET1_CONSTANT_FILL            0x10000
+#define BF_DCP_PACKET1_CONSTANT_FILL(v)         (((v) & 0x1) << 16)
+#define BFM_DCP_PACKET1_CONSTANT_FILL(v)        BM_DCP_PACKET1_CONSTANT_FILL
+#define BF_DCP_PACKET1_CONSTANT_FILL_V(e)       BF_DCP_PACKET1_CONSTANT_FILL(BV_DCP_PACKET1_CONSTANT_FILL__##e)
+#define BFM_DCP_PACKET1_CONSTANT_FILL_V(v)      BM_DCP_PACKET1_CONSTANT_FILL
+#define BP_DCP_PACKET1_HASH_OUTPUT              15
+#define BM_DCP_PACKET1_HASH_OUTPUT              0x8000
+#define BV_DCP_PACKET1_HASH_OUTPUT__INPUT       0x0
+#define BV_DCP_PACKET1_HASH_OUTPUT__OUTPUT      0x1
+#define BF_DCP_PACKET1_HASH_OUTPUT(v)           (((v) & 0x1) << 15)
+#define BFM_DCP_PACKET1_HASH_OUTPUT(v)          BM_DCP_PACKET1_HASH_OUTPUT
+#define BF_DCP_PACKET1_HASH_OUTPUT_V(e)         BF_DCP_PACKET1_HASH_OUTPUT(BV_DCP_PACKET1_HASH_OUTPUT__##e)
+#define BFM_DCP_PACKET1_HASH_OUTPUT_V(v)        BM_DCP_PACKET1_HASH_OUTPUT
+#define BP_DCP_PACKET1_CHECK_HASH               14
+#define BM_DCP_PACKET1_CHECK_HASH               0x4000
+#define BF_DCP_PACKET1_CHECK_HASH(v)            (((v) & 0x1) << 14)
+#define BFM_DCP_PACKET1_CHECK_HASH(v)           BM_DCP_PACKET1_CHECK_HASH
+#define BF_DCP_PACKET1_CHECK_HASH_V(e)          BF_DCP_PACKET1_CHECK_HASH(BV_DCP_PACKET1_CHECK_HASH__##e)
+#define BFM_DCP_PACKET1_CHECK_HASH_V(v)         BM_DCP_PACKET1_CHECK_HASH
+#define BP_DCP_PACKET1_HASH_TERM                13
+#define BM_DCP_PACKET1_HASH_TERM                0x2000
+#define BF_DCP_PACKET1_HASH_TERM(v)             (((v) & 0x1) << 13)
+#define BFM_DCP_PACKET1_HASH_TERM(v)            BM_DCP_PACKET1_HASH_TERM
+#define BF_DCP_PACKET1_HASH_TERM_V(e)           BF_DCP_PACKET1_HASH_TERM(BV_DCP_PACKET1_HASH_TERM__##e)
+#define BFM_DCP_PACKET1_HASH_TERM_V(v)          BM_DCP_PACKET1_HASH_TERM
+#define BP_DCP_PACKET1_HASH_INIT                12
+#define BM_DCP_PACKET1_HASH_INIT                0x1000
+#define BF_DCP_PACKET1_HASH_INIT(v)             (((v) & 0x1) << 12)
+#define BFM_DCP_PACKET1_HASH_INIT(v)            BM_DCP_PACKET1_HASH_INIT
+#define BF_DCP_PACKET1_HASH_INIT_V(e)           BF_DCP_PACKET1_HASH_INIT(BV_DCP_PACKET1_HASH_INIT__##e)
+#define BFM_DCP_PACKET1_HASH_INIT_V(v)          BM_DCP_PACKET1_HASH_INIT
+#define BP_DCP_PACKET1_PAYLOAD_KEY              11
+#define BM_DCP_PACKET1_PAYLOAD_KEY              0x800
+#define BF_DCP_PACKET1_PAYLOAD_KEY(v)           (((v) & 0x1) << 11)
+#define BFM_DCP_PACKET1_PAYLOAD_KEY(v)          BM_DCP_PACKET1_PAYLOAD_KEY
+#define BF_DCP_PACKET1_PAYLOAD_KEY_V(e)         BF_DCP_PACKET1_PAYLOAD_KEY(BV_DCP_PACKET1_PAYLOAD_KEY__##e)
+#define BFM_DCP_PACKET1_PAYLOAD_KEY_V(v)        BM_DCP_PACKET1_PAYLOAD_KEY
+#define BP_DCP_PACKET1_OTP_KEY                  10
+#define BM_DCP_PACKET1_OTP_KEY                  0x400
+#define BF_DCP_PACKET1_OTP_KEY(v)               (((v) & 0x1) << 10)
+#define BFM_DCP_PACKET1_OTP_KEY(v)              BM_DCP_PACKET1_OTP_KEY
+#define BF_DCP_PACKET1_OTP_KEY_V(e)             BF_DCP_PACKET1_OTP_KEY(BV_DCP_PACKET1_OTP_KEY__##e)
+#define BFM_DCP_PACKET1_OTP_KEY_V(v)            BM_DCP_PACKET1_OTP_KEY
+#define BP_DCP_PACKET1_CIPHER_INIT              9
+#define BM_DCP_PACKET1_CIPHER_INIT              0x200
+#define BF_DCP_PACKET1_CIPHER_INIT(v)           (((v) & 0x1) << 9)
+#define BFM_DCP_PACKET1_CIPHER_INIT(v)          BM_DCP_PACKET1_CIPHER_INIT
+#define BF_DCP_PACKET1_CIPHER_INIT_V(e)         BF_DCP_PACKET1_CIPHER_INIT(BV_DCP_PACKET1_CIPHER_INIT__##e)
+#define BFM_DCP_PACKET1_CIPHER_INIT_V(v)        BM_DCP_PACKET1_CIPHER_INIT
+#define BP_DCP_PACKET1_CIPHER_ENCRYPT           8
+#define BM_DCP_PACKET1_CIPHER_ENCRYPT           0x100
+#define BV_DCP_PACKET1_CIPHER_ENCRYPT__ENCRYPT  0x1
+#define BV_DCP_PACKET1_CIPHER_ENCRYPT__DECRYPT  0x0
+#define BF_DCP_PACKET1_CIPHER_ENCRYPT(v)        (((v) & 0x1) << 8)
+#define BFM_DCP_PACKET1_CIPHER_ENCRYPT(v)       BM_DCP_PACKET1_CIPHER_ENCRYPT
+#define BF_DCP_PACKET1_CIPHER_ENCRYPT_V(e)      BF_DCP_PACKET1_CIPHER_ENCRYPT(BV_DCP_PACKET1_CIPHER_ENCRYPT__##e)
+#define BFM_DCP_PACKET1_CIPHER_ENCRYPT_V(v)     BM_DCP_PACKET1_CIPHER_ENCRYPT
+#define BP_DCP_PACKET1_ENABLE_BLIT              7
+#define BM_DCP_PACKET1_ENABLE_BLIT              0x80
+#define BF_DCP_PACKET1_ENABLE_BLIT(v)           (((v) & 0x1) << 7)
+#define BFM_DCP_PACKET1_ENABLE_BLIT(v)          BM_DCP_PACKET1_ENABLE_BLIT
+#define BF_DCP_PACKET1_ENABLE_BLIT_V(e)         BF_DCP_PACKET1_ENABLE_BLIT(BV_DCP_PACKET1_ENABLE_BLIT__##e)
+#define BFM_DCP_PACKET1_ENABLE_BLIT_V(v)        BM_DCP_PACKET1_ENABLE_BLIT
+#define BP_DCP_PACKET1_ENABLE_HASH              6
+#define BM_DCP_PACKET1_ENABLE_HASH              0x40
+#define BF_DCP_PACKET1_ENABLE_HASH(v)           (((v) & 0x1) << 6)
+#define BFM_DCP_PACKET1_ENABLE_HASH(v)          BM_DCP_PACKET1_ENABLE_HASH
+#define BF_DCP_PACKET1_ENABLE_HASH_V(e)         BF_DCP_PACKET1_ENABLE_HASH(BV_DCP_PACKET1_ENABLE_HASH__##e)
+#define BFM_DCP_PACKET1_ENABLE_HASH_V(v)        BM_DCP_PACKET1_ENABLE_HASH
+#define BP_DCP_PACKET1_ENABLE_CIPHER            5
+#define BM_DCP_PACKET1_ENABLE_CIPHER            0x20
+#define BF_DCP_PACKET1_ENABLE_CIPHER(v)         (((v) & 0x1) << 5)
+#define BFM_DCP_PACKET1_ENABLE_CIPHER(v)        BM_DCP_PACKET1_ENABLE_CIPHER
+#define BF_DCP_PACKET1_ENABLE_CIPHER_V(e)       BF_DCP_PACKET1_ENABLE_CIPHER(BV_DCP_PACKET1_ENABLE_CIPHER__##e)
+#define BFM_DCP_PACKET1_ENABLE_CIPHER_V(v)      BM_DCP_PACKET1_ENABLE_CIPHER
+#define BP_DCP_PACKET1_ENABLE_MEMCOPY           4
+#define BM_DCP_PACKET1_ENABLE_MEMCOPY           0x10
+#define BF_DCP_PACKET1_ENABLE_MEMCOPY(v)        (((v) & 0x1) << 4)
+#define BFM_DCP_PACKET1_ENABLE_MEMCOPY(v)       BM_DCP_PACKET1_ENABLE_MEMCOPY
+#define BF_DCP_PACKET1_ENABLE_MEMCOPY_V(e)      BF_DCP_PACKET1_ENABLE_MEMCOPY(BV_DCP_PACKET1_ENABLE_MEMCOPY__##e)
+#define BFM_DCP_PACKET1_ENABLE_MEMCOPY_V(v)     BM_DCP_PACKET1_ENABLE_MEMCOPY
+#define BP_DCP_PACKET1_CHAIN_CONTIGUOUS         3
+#define BM_DCP_PACKET1_CHAIN_CONTIGUOUS         0x8
+#define BF_DCP_PACKET1_CHAIN_CONTIGUOUS(v)      (((v) & 0x1) << 3)
+#define BFM_DCP_PACKET1_CHAIN_CONTIGUOUS(v)     BM_DCP_PACKET1_CHAIN_CONTIGUOUS
+#define BF_DCP_PACKET1_CHAIN_CONTIGUOUS_V(e)    BF_DCP_PACKET1_CHAIN_CONTIGUOUS(BV_DCP_PACKET1_CHAIN_CONTIGUOUS__##e)
+#define BFM_DCP_PACKET1_CHAIN_CONTIGUOUS_V(v)   BM_DCP_PACKET1_CHAIN_CONTIGUOUS
+#define BP_DCP_PACKET1_CHAIN                    2
+#define BM_DCP_PACKET1_CHAIN                    0x4
+#define BF_DCP_PACKET1_CHAIN(v)                 (((v) & 0x1) << 2)
+#define BFM_DCP_PACKET1_CHAIN(v)                BM_DCP_PACKET1_CHAIN
+#define BF_DCP_PACKET1_CHAIN_V(e)               BF_DCP_PACKET1_CHAIN(BV_DCP_PACKET1_CHAIN__##e)
+#define BFM_DCP_PACKET1_CHAIN_V(v)              BM_DCP_PACKET1_CHAIN
+#define BP_DCP_PACKET1_DECR_SEMAPHORE           1
+#define BM_DCP_PACKET1_DECR_SEMAPHORE           0x2
+#define BF_DCP_PACKET1_DECR_SEMAPHORE(v)        (((v) & 0x1) << 1)
+#define BFM_DCP_PACKET1_DECR_SEMAPHORE(v)       BM_DCP_PACKET1_DECR_SEMAPHORE
+#define BF_DCP_PACKET1_DECR_SEMAPHORE_V(e)      BF_DCP_PACKET1_DECR_SEMAPHORE(BV_DCP_PACKET1_DECR_SEMAPHORE__##e)
+#define BFM_DCP_PACKET1_DECR_SEMAPHORE_V(v)     BM_DCP_PACKET1_DECR_SEMAPHORE
+#define BP_DCP_PACKET1_INTERRUPT                0
+#define BM_DCP_PACKET1_INTERRUPT                0x1
+#define BF_DCP_PACKET1_INTERRUPT(v)             (((v) & 0x1) << 0)
+#define BFM_DCP_PACKET1_INTERRUPT(v)            BM_DCP_PACKET1_INTERRUPT
+#define BF_DCP_PACKET1_INTERRUPT_V(e)           BF_DCP_PACKET1_INTERRUPT(BV_DCP_PACKET1_INTERRUPT__##e)
+#define BFM_DCP_PACKET1_INTERRUPT_V(v)          BM_DCP_PACKET1_INTERRUPT
+
+#define HW_DCP_PACKET2                          HW(DCP_PACKET2)
+#define HWA_DCP_PACKET2                         (0x80028000 + 0xa0)
+#define HWT_DCP_PACKET2                         HWIO_32_RW
+#define HWN_DCP_PACKET2                         DCP_PACKET2
+#define HWI_DCP_PACKET2                         
+#define BP_DCP_PACKET2_CIPHER_CFG               24
+#define BM_DCP_PACKET2_CIPHER_CFG               0xff000000
+#define BF_DCP_PACKET2_CIPHER_CFG(v)            (((v) & 0xff) << 24)
+#define BFM_DCP_PACKET2_CIPHER_CFG(v)           BM_DCP_PACKET2_CIPHER_CFG
+#define BF_DCP_PACKET2_CIPHER_CFG_V(e)          BF_DCP_PACKET2_CIPHER_CFG(BV_DCP_PACKET2_CIPHER_CFG__##e)
+#define BFM_DCP_PACKET2_CIPHER_CFG_V(v)         BM_DCP_PACKET2_CIPHER_CFG
+#define BP_DCP_PACKET2_HASH_SELECT              16
+#define BM_DCP_PACKET2_HASH_SELECT              0xf0000
+#define BV_DCP_PACKET2_HASH_SELECT__SHA1        0x0
+#define BV_DCP_PACKET2_HASH_SELECT__CRC32       0x1
+#define BF_DCP_PACKET2_HASH_SELECT(v)           (((v) & 0xf) << 16)
+#define BFM_DCP_PACKET2_HASH_SELECT(v)          BM_DCP_PACKET2_HASH_SELECT
+#define BF_DCP_PACKET2_HASH_SELECT_V(e)         BF_DCP_PACKET2_HASH_SELECT(BV_DCP_PACKET2_HASH_SELECT__##e)
+#define BFM_DCP_PACKET2_HASH_SELECT_V(v)        BM_DCP_PACKET2_HASH_SELECT
+#define BP_DCP_PACKET2_KEY_SELECT               8
+#define BM_DCP_PACKET2_KEY_SELECT               0xff00
+#define BF_DCP_PACKET2_KEY_SELECT(v)            (((v) & 0xff) << 8)
+#define BFM_DCP_PACKET2_KEY_SELECT(v)           BM_DCP_PACKET2_KEY_SELECT
+#define BF_DCP_PACKET2_KEY_SELECT_V(e)          BF_DCP_PACKET2_KEY_SELECT(BV_DCP_PACKET2_KEY_SELECT__##e)
+#define BFM_DCP_PACKET2_KEY_SELECT_V(v)         BM_DCP_PACKET2_KEY_SELECT
+#define BP_DCP_PACKET2_CIPHER_MODE              4
+#define BM_DCP_PACKET2_CIPHER_MODE              0xf0
+#define BV_DCP_PACKET2_CIPHER_MODE__ECB         0x0
+#define BV_DCP_PACKET2_CIPHER_MODE__CCB         0x1
+#define BF_DCP_PACKET2_CIPHER_MODE(v)           (((v) & 0xf) << 4)
+#define BFM_DCP_PACKET2_CIPHER_MODE(v)          BM_DCP_PACKET2_CIPHER_MODE
+#define BF_DCP_PACKET2_CIPHER_MODE_V(e)         BF_DCP_PACKET2_CIPHER_MODE(BV_DCP_PACKET2_CIPHER_MODE__##e)
+#define BFM_DCP_PACKET2_CIPHER_MODE_V(v)        BM_DCP_PACKET2_CIPHER_MODE
+#define BP_DCP_PACKET2_CIPHER_SELECT            0
+#define BM_DCP_PACKET2_CIPHER_SELECT            0xf
+#define BV_DCP_PACKET2_CIPHER_SELECT__AES128    0x0
+#define BF_DCP_PACKET2_CIPHER_SELECT(v)         (((v) & 0xf) << 0)
+#define BFM_DCP_PACKET2_CIPHER_SELECT(v)        BM_DCP_PACKET2_CIPHER_SELECT
+#define BF_DCP_PACKET2_CIPHER_SELECT_V(e)       BF_DCP_PACKET2_CIPHER_SELECT(BV_DCP_PACKET2_CIPHER_SELECT__##e)
+#define BFM_DCP_PACKET2_CIPHER_SELECT_V(v)      BM_DCP_PACKET2_CIPHER_SELECT
+
+#define HW_DCP_PACKET3              HW(DCP_PACKET3)
+#define HWA_DCP_PACKET3             (0x80028000 + 0xb0)
+#define HWT_DCP_PACKET3             HWIO_32_RW
+#define HWN_DCP_PACKET3             DCP_PACKET3
+#define HWI_DCP_PACKET3             
+#define BP_DCP_PACKET3_ADDR         0
+#define BM_DCP_PACKET3_ADDR         0xffffffff
+#define BF_DCP_PACKET3_ADDR(v)      (((v) & 0xffffffff) << 0)
+#define BFM_DCP_PACKET3_ADDR(v)     BM_DCP_PACKET3_ADDR
+#define BF_DCP_PACKET3_ADDR_V(e)    BF_DCP_PACKET3_ADDR(BV_DCP_PACKET3_ADDR__##e)
+#define BFM_DCP_PACKET3_ADDR_V(v)   BM_DCP_PACKET3_ADDR
+
+#define HW_DCP_PACKET4              HW(DCP_PACKET4)
+#define HWA_DCP_PACKET4             (0x80028000 + 0xc0)
+#define HWT_DCP_PACKET4             HWIO_32_RW
+#define HWN_DCP_PACKET4             DCP_PACKET4
+#define HWI_DCP_PACKET4             
+#define BP_DCP_PACKET4_ADDR         0
+#define BM_DCP_PACKET4_ADDR         0xffffffff
+#define BF_DCP_PACKET4_ADDR(v)      (((v) & 0xffffffff) << 0)
+#define BFM_DCP_PACKET4_ADDR(v)     BM_DCP_PACKET4_ADDR
+#define BF_DCP_PACKET4_ADDR_V(e)    BF_DCP_PACKET4_ADDR(BV_DCP_PACKET4_ADDR__##e)
+#define BFM_DCP_PACKET4_ADDR_V(v)   BM_DCP_PACKET4_ADDR
+
+#define HW_DCP_PACKET5              HW(DCP_PACKET5)
+#define HWA_DCP_PACKET5             (0x80028000 + 0xd0)
+#define HWT_DCP_PACKET5             HWIO_32_RW
+#define HWN_DCP_PACKET5             DCP_PACKET5
+#define HWI_DCP_PACKET5             
+#define BP_DCP_PACKET5_COUNT        0
+#define BM_DCP_PACKET5_COUNT        0xffffffff
+#define BF_DCP_PACKET5_COUNT(v)     (((v) & 0xffffffff) << 0)
+#define BFM_DCP_PACKET5_COUNT(v)    BM_DCP_PACKET5_COUNT
+#define BF_DCP_PACKET5_COUNT_V(e)   BF_DCP_PACKET5_COUNT(BV_DCP_PACKET5_COUNT__##e)
+#define BFM_DCP_PACKET5_COUNT_V(v)  BM_DCP_PACKET5_COUNT
+
+#define HW_DCP_PACKET6              HW(DCP_PACKET6)
+#define HWA_DCP_PACKET6             (0x80028000 + 0xe0)
+#define HWT_DCP_PACKET6             HWIO_32_RW
+#define HWN_DCP_PACKET6             DCP_PACKET6
+#define HWI_DCP_PACKET6             
+#define BP_DCP_PACKET6_ADDR         0
+#define BM_DCP_PACKET6_ADDR         0xffffffff
+#define BF_DCP_PACKET6_ADDR(v)      (((v) & 0xffffffff) << 0)
+#define BFM_DCP_PACKET6_ADDR(v)     BM_DCP_PACKET6_ADDR
+#define BF_DCP_PACKET6_ADDR_V(e)    BF_DCP_PACKET6_ADDR(BV_DCP_PACKET6_ADDR__##e)
+#define BFM_DCP_PACKET6_ADDR_V(v)   BM_DCP_PACKET6_ADDR
+
+#define HW_DCP_CHnCMDPTR(_n1)       HW(DCP_CHnCMDPTR(_n1))
+#define HWA_DCP_CHnCMDPTR(_n1)      (0x80028000 + 0x100 + (_n1) * 0x40)
+#define HWT_DCP_CHnCMDPTR(_n1)      HWIO_32_RW
+#define HWN_DCP_CHnCMDPTR(_n1)      DCP_CHnCMDPTR
+#define HWI_DCP_CHnCMDPTR(_n1)      (_n1)
+#define BP_DCP_CHnCMDPTR_ADDR       0
+#define BM_DCP_CHnCMDPTR_ADDR       0xffffffff
+#define BF_DCP_CHnCMDPTR_ADDR(v)    (((v) & 0xffffffff) << 0)
+#define BFM_DCP_CHnCMDPTR_ADDR(v)   BM_DCP_CHnCMDPTR_ADDR
+#define BF_DCP_CHnCMDPTR_ADDR_V(e)  BF_DCP_CHnCMDPTR_ADDR(BV_DCP_CHnCMDPTR_ADDR__##e)
+#define BFM_DCP_CHnCMDPTR_ADDR_V(v) BM_DCP_CHnCMDPTR_ADDR
+
+#define HW_DCP_CHnSEMA(_n1)             HW(DCP_CHnSEMA(_n1))
+#define HWA_DCP_CHnSEMA(_n1)            (0x80028000 + 0x110 + (_n1) * 0x40)
+#define HWT_DCP_CHnSEMA(_n1)            HWIO_32_RW
+#define HWN_DCP_CHnSEMA(_n1)            DCP_CHnSEMA
+#define HWI_DCP_CHnSEMA(_n1)            (_n1)
+#define BP_DCP_CHnSEMA_VALUE            16
+#define BM_DCP_CHnSEMA_VALUE            0xff0000
+#define BF_DCP_CHnSEMA_VALUE(v)         (((v) & 0xff) << 16)
+#define BFM_DCP_CHnSEMA_VALUE(v)        BM_DCP_CHnSEMA_VALUE
+#define BF_DCP_CHnSEMA_VALUE_V(e)       BF_DCP_CHnSEMA_VALUE(BV_DCP_CHnSEMA_VALUE__##e)
+#define BFM_DCP_CHnSEMA_VALUE_V(v)      BM_DCP_CHnSEMA_VALUE
+#define BP_DCP_CHnSEMA_INCREMENT        0
+#define BM_DCP_CHnSEMA_INCREMENT        0xff
+#define BF_DCP_CHnSEMA_INCREMENT(v)     (((v) & 0xff) << 0)
+#define BFM_DCP_CHnSEMA_INCREMENT(v)    BM_DCP_CHnSEMA_INCREMENT
+#define BF_DCP_CHnSEMA_INCREMENT_V(e)   BF_DCP_CHnSEMA_INCREMENT(BV_DCP_CHnSEMA_INCREMENT__##e)
+#define BFM_DCP_CHnSEMA_INCREMENT_V(v)  BM_DCP_CHnSEMA_INCREMENT
+
+#define HW_DCP_CHnSTAT(_n1)                         HW(DCP_CHnSTAT(_n1))
+#define HWA_DCP_CHnSTAT(_n1)                        (0x80028000 + 0x120 + (_n1) * 0x40)
+#define HWT_DCP_CHnSTAT(_n1)                        HWIO_32_RW
+#define HWN_DCP_CHnSTAT(_n1)                        DCP_CHnSTAT
+#define HWI_DCP_CHnSTAT(_n1)                        (_n1)
+#define HW_DCP_CHnSTAT_SET(_n1)                     HW(DCP_CHnSTAT_SET(_n1))
+#define HWA_DCP_CHnSTAT_SET(_n1)                    (HWA_DCP_CHnSTAT(_n1) + 0x4)
+#define HWT_DCP_CHnSTAT_SET(_n1)                    HWIO_32_WO
+#define HWN_DCP_CHnSTAT_SET(_n1)                    DCP_CHnSTAT
+#define HWI_DCP_CHnSTAT_SET(_n1)                    (_n1)
+#define HW_DCP_CHnSTAT_CLR(_n1)                     HW(DCP_CHnSTAT_CLR(_n1))
+#define HWA_DCP_CHnSTAT_CLR(_n1)                    (HWA_DCP_CHnSTAT(_n1) + 0x8)
+#define HWT_DCP_CHnSTAT_CLR(_n1)                    HWIO_32_WO
+#define HWN_DCP_CHnSTAT_CLR(_n1)                    DCP_CHnSTAT
+#define HWI_DCP_CHnSTAT_CLR(_n1)                    (_n1)
+#define HW_DCP_CHnSTAT_TOG(_n1)                     HW(DCP_CHnSTAT_TOG(_n1))
+#define HWA_DCP_CHnSTAT_TOG(_n1)                    (HWA_DCP_CHnSTAT(_n1) + 0xc)
+#define HWT_DCP_CHnSTAT_TOG(_n1)                    HWIO_32_WO
+#define HWN_DCP_CHnSTAT_TOG(_n1)                    DCP_CHnSTAT
+#define HWI_DCP_CHnSTAT_TOG(_n1)                    (_n1)
+#define BP_DCP_CHnSTAT_TAG                          24
+#define BM_DCP_CHnSTAT_TAG                          0xff000000
+#define BF_DCP_CHnSTAT_TAG(v)                       (((v) & 0xff) << 24)
+#define BFM_DCP_CHnSTAT_TAG(v)                      BM_DCP_CHnSTAT_TAG
+#define BF_DCP_CHnSTAT_TAG_V(e)                     BF_DCP_CHnSTAT_TAG(BV_DCP_CHnSTAT_TAG__##e)
+#define BFM_DCP_CHnSTAT_TAG_V(v)                    BM_DCP_CHnSTAT_TAG
+#define BP_DCP_CHnSTAT_ERROR_CODE                   16
+#define BM_DCP_CHnSTAT_ERROR_CODE                   0xff0000
+#define BV_DCP_CHnSTAT_ERROR_CODE__NEXT_CHAIN_IS_0  0x1
+#define BV_DCP_CHnSTAT_ERROR_CODE__NO_CHAIN         0x2
+#define BV_DCP_CHnSTAT_ERROR_CODE__CONTEXT_ERROR    0x3
+#define BV_DCP_CHnSTAT_ERROR_CODE__PAYLOAD_ERROR    0x4
+#define BV_DCP_CHnSTAT_ERROR_CODE__INVALID_MODE     0x5
+#define BF_DCP_CHnSTAT_ERROR_CODE(v)                (((v) & 0xff) << 16)
+#define BFM_DCP_CHnSTAT_ERROR_CODE(v)               BM_DCP_CHnSTAT_ERROR_CODE
+#define BF_DCP_CHnSTAT_ERROR_CODE_V(e)              BF_DCP_CHnSTAT_ERROR_CODE(BV_DCP_CHnSTAT_ERROR_CODE__##e)
+#define BFM_DCP_CHnSTAT_ERROR_CODE_V(v)             BM_DCP_CHnSTAT_ERROR_CODE
+#define BP_DCP_CHnSTAT_ERROR_DST                    5
+#define BM_DCP_CHnSTAT_ERROR_DST                    0x20
+#define BF_DCP_CHnSTAT_ERROR_DST(v)                 (((v) & 0x1) << 5)
+#define BFM_DCP_CHnSTAT_ERROR_DST(v)                BM_DCP_CHnSTAT_ERROR_DST
+#define BF_DCP_CHnSTAT_ERROR_DST_V(e)               BF_DCP_CHnSTAT_ERROR_DST(BV_DCP_CHnSTAT_ERROR_DST__##e)
+#define BFM_DCP_CHnSTAT_ERROR_DST_V(v)              BM_DCP_CHnSTAT_ERROR_DST
+#define BP_DCP_CHnSTAT_ERROR_SRC                    4
+#define BM_DCP_CHnSTAT_ERROR_SRC                    0x10
+#define BF_DCP_CHnSTAT_ERROR_SRC(v)                 (((v) & 0x1) << 4)
+#define BFM_DCP_CHnSTAT_ERROR_SRC(v)                BM_DCP_CHnSTAT_ERROR_SRC
+#define BF_DCP_CHnSTAT_ERROR_SRC_V(e)               BF_DCP_CHnSTAT_ERROR_SRC(BV_DCP_CHnSTAT_ERROR_SRC__##e)
+#define BFM_DCP_CHnSTAT_ERROR_SRC_V(v)              BM_DCP_CHnSTAT_ERROR_SRC
+#define BP_DCP_CHnSTAT_ERROR_PACKET                 3
+#define BM_DCP_CHnSTAT_ERROR_PACKET                 0x8
+#define BF_DCP_CHnSTAT_ERROR_PACKET(v)              (((v) & 0x1) << 3)
+#define BFM_DCP_CHnSTAT_ERROR_PACKET(v)             BM_DCP_CHnSTAT_ERROR_PACKET
+#define BF_DCP_CHnSTAT_ERROR_PACKET_V(e)            BF_DCP_CHnSTAT_ERROR_PACKET(BV_DCP_CHnSTAT_ERROR_PACKET__##e)
+#define BFM_DCP_CHnSTAT_ERROR_PACKET_V(v)           BM_DCP_CHnSTAT_ERROR_PACKET
+#define BP_DCP_CHnSTAT_ERROR_SETUP                  2
+#define BM_DCP_CHnSTAT_ERROR_SETUP                  0x4
+#define BF_DCP_CHnSTAT_ERROR_SETUP(v)               (((v) & 0x1) << 2)
+#define BFM_DCP_CHnSTAT_ERROR_SETUP(v)              BM_DCP_CHnSTAT_ERROR_SETUP
+#define BF_DCP_CHnSTAT_ERROR_SETUP_V(e)             BF_DCP_CHnSTAT_ERROR_SETUP(BV_DCP_CHnSTAT_ERROR_SETUP__##e)
+#define BFM_DCP_CHnSTAT_ERROR_SETUP_V(v)            BM_DCP_CHnSTAT_ERROR_SETUP
+#define BP_DCP_CHnSTAT_HASH_MISMATCH                1
+#define BM_DCP_CHnSTAT_HASH_MISMATCH                0x2
+#define BF_DCP_CHnSTAT_HASH_MISMATCH(v)             (((v) & 0x1) << 1)
+#define BFM_DCP_CHnSTAT_HASH_MISMATCH(v)            BM_DCP_CHnSTAT_HASH_MISMATCH
+#define BF_DCP_CHnSTAT_HASH_MISMATCH_V(e)           BF_DCP_CHnSTAT_HASH_MISMATCH(BV_DCP_CHnSTAT_HASH_MISMATCH__##e)
+#define BFM_DCP_CHnSTAT_HASH_MISMATCH_V(v)          BM_DCP_CHnSTAT_HASH_MISMATCH
+
+#define HW_DCP_CHnOPTS(_n1)                 HW(DCP_CHnOPTS(_n1))
+#define HWA_DCP_CHnOPTS(_n1)                (0x80028000 + 0x130 + (_n1) * 0x40)
+#define HWT_DCP_CHnOPTS(_n1)                HWIO_32_RW
+#define HWN_DCP_CHnOPTS(_n1)                DCP_CHnOPTS
+#define HWI_DCP_CHnOPTS(_n1)                (_n1)
+#define HW_DCP_CHnOPTS_SET(_n1)             HW(DCP_CHnOPTS_SET(_n1))
+#define HWA_DCP_CHnOPTS_SET(_n1)            (HWA_DCP_CHnOPTS(_n1) + 0x4)
+#define HWT_DCP_CHnOPTS_SET(_n1)            HWIO_32_WO
+#define HWN_DCP_CHnOPTS_SET(_n1)            DCP_CHnOPTS
+#define HWI_DCP_CHnOPTS_SET(_n1)            (_n1)
+#define HW_DCP_CHnOPTS_CLR(_n1)             HW(DCP_CHnOPTS_CLR(_n1))
+#define HWA_DCP_CHnOPTS_CLR(_n1)            (HWA_DCP_CHnOPTS(_n1) + 0x8)
+#define HWT_DCP_CHnOPTS_CLR(_n1)            HWIO_32_WO
+#define HWN_DCP_CHnOPTS_CLR(_n1)            DCP_CHnOPTS
+#define HWI_DCP_CHnOPTS_CLR(_n1)            (_n1)
+#define HW_DCP_CHnOPTS_TOG(_n1)             HW(DCP_CHnOPTS_TOG(_n1))
+#define HWA_DCP_CHnOPTS_TOG(_n1)            (HWA_DCP_CHnOPTS(_n1) + 0xc)
+#define HWT_DCP_CHnOPTS_TOG(_n1)            HWIO_32_WO
+#define HWN_DCP_CHnOPTS_TOG(_n1)            DCP_CHnOPTS
+#define HWI_DCP_CHnOPTS_TOG(_n1)            (_n1)
+#define BP_DCP_CHnOPTS_RECOVERY_TIMER       0
+#define BM_DCP_CHnOPTS_RECOVERY_TIMER       0xffff
+#define BF_DCP_CHnOPTS_RECOVERY_TIMER(v)    (((v) & 0xffff) << 0)
+#define BFM_DCP_CHnOPTS_RECOVERY_TIMER(v)   BM_DCP_CHnOPTS_RECOVERY_TIMER
+#define BF_DCP_CHnOPTS_RECOVERY_TIMER_V(e)  BF_DCP_CHnOPTS_RECOVERY_TIMER(BV_DCP_CHnOPTS_RECOVERY_TIMER__##e)
+#define BFM_DCP_CHnOPTS_RECOVERY_TIMER_V(v) BM_DCP_CHnOPTS_RECOVERY_TIMER
+
+#define HW_DCP_CSCCTRL0                         HW(DCP_CSCCTRL0)
+#define HWA_DCP_CSCCTRL0                        (0x80028000 + 0x300)
+#define HWT_DCP_CSCCTRL0                        HWIO_32_RW
+#define HWN_DCP_CSCCTRL0                        DCP_CSCCTRL0
+#define HWI_DCP_CSCCTRL0                        
+#define HW_DCP_CSCCTRL0_SET                     HW(DCP_CSCCTRL0_SET)
+#define HWA_DCP_CSCCTRL0_SET                    (HWA_DCP_CSCCTRL0 + 0x4)
+#define HWT_DCP_CSCCTRL0_SET                    HWIO_32_WO
+#define HWN_DCP_CSCCTRL0_SET                    DCP_CSCCTRL0
+#define HWI_DCP_CSCCTRL0_SET                    
+#define HW_DCP_CSCCTRL0_CLR                     HW(DCP_CSCCTRL0_CLR)
+#define HWA_DCP_CSCCTRL0_CLR                    (HWA_DCP_CSCCTRL0 + 0x8)
+#define HWT_DCP_CSCCTRL0_CLR                    HWIO_32_WO
+#define HWN_DCP_CSCCTRL0_CLR                    DCP_CSCCTRL0
+#define HWI_DCP_CSCCTRL0_CLR                    
+#define HW_DCP_CSCCTRL0_TOG                     HW(DCP_CSCCTRL0_TOG)
+#define HWA_DCP_CSCCTRL0_TOG                    (HWA_DCP_CSCCTRL0 + 0xc)
+#define HWT_DCP_CSCCTRL0_TOG                    HWIO_32_WO
+#define HWN_DCP_CSCCTRL0_TOG                    DCP_CSCCTRL0
+#define HWI_DCP_CSCCTRL0_TOG                    
+#define BP_DCP_CSCCTRL0_UPSAMPLE                14
+#define BM_DCP_CSCCTRL0_UPSAMPLE                0x4000
+#define BF_DCP_CSCCTRL0_UPSAMPLE(v)             (((v) & 0x1) << 14)
+#define BFM_DCP_CSCCTRL0_UPSAMPLE(v)            BM_DCP_CSCCTRL0_UPSAMPLE
+#define BF_DCP_CSCCTRL0_UPSAMPLE_V(e)           BF_DCP_CSCCTRL0_UPSAMPLE(BV_DCP_CSCCTRL0_UPSAMPLE__##e)
+#define BFM_DCP_CSCCTRL0_UPSAMPLE_V(v)          BM_DCP_CSCCTRL0_UPSAMPLE
+#define BP_DCP_CSCCTRL0_SCALE                   13
+#define BM_DCP_CSCCTRL0_SCALE                   0x2000
+#define BF_DCP_CSCCTRL0_SCALE(v)                (((v) & 0x1) << 13)
+#define BFM_DCP_CSCCTRL0_SCALE(v)               BM_DCP_CSCCTRL0_SCALE
+#define BF_DCP_CSCCTRL0_SCALE_V(e)              BF_DCP_CSCCTRL0_SCALE(BV_DCP_CSCCTRL0_SCALE__##e)
+#define BFM_DCP_CSCCTRL0_SCALE_V(v)             BM_DCP_CSCCTRL0_SCALE
+#define BP_DCP_CSCCTRL0_ROTATE                  12
+#define BM_DCP_CSCCTRL0_ROTATE                  0x1000
+#define BF_DCP_CSCCTRL0_ROTATE(v)               (((v) & 0x1) << 12)
+#define BFM_DCP_CSCCTRL0_ROTATE(v)              BM_DCP_CSCCTRL0_ROTATE
+#define BF_DCP_CSCCTRL0_ROTATE_V(e)             BF_DCP_CSCCTRL0_ROTATE(BV_DCP_CSCCTRL0_ROTATE__##e)
+#define BFM_DCP_CSCCTRL0_ROTATE_V(v)            BM_DCP_CSCCTRL0_ROTATE
+#define BP_DCP_CSCCTRL0_SUBSAMPLE               11
+#define BM_DCP_CSCCTRL0_SUBSAMPLE               0x800
+#define BF_DCP_CSCCTRL0_SUBSAMPLE(v)            (((v) & 0x1) << 11)
+#define BFM_DCP_CSCCTRL0_SUBSAMPLE(v)           BM_DCP_CSCCTRL0_SUBSAMPLE
+#define BF_DCP_CSCCTRL0_SUBSAMPLE_V(e)          BF_DCP_CSCCTRL0_SUBSAMPLE(BV_DCP_CSCCTRL0_SUBSAMPLE__##e)
+#define BFM_DCP_CSCCTRL0_SUBSAMPLE_V(v)         BM_DCP_CSCCTRL0_SUBSAMPLE
+#define BP_DCP_CSCCTRL0_DELTA                   10
+#define BM_DCP_CSCCTRL0_DELTA                   0x400
+#define BF_DCP_CSCCTRL0_DELTA(v)                (((v) & 0x1) << 10)
+#define BFM_DCP_CSCCTRL0_DELTA(v)               BM_DCP_CSCCTRL0_DELTA
+#define BF_DCP_CSCCTRL0_DELTA_V(e)              BF_DCP_CSCCTRL0_DELTA(BV_DCP_CSCCTRL0_DELTA__##e)
+#define BFM_DCP_CSCCTRL0_DELTA_V(v)             BM_DCP_CSCCTRL0_DELTA
+#define BP_DCP_CSCCTRL0_RGB_FORMAT              8
+#define BM_DCP_CSCCTRL0_RGB_FORMAT              0x300
+#define BV_DCP_CSCCTRL0_RGB_FORMAT__RGB16_565   0x0
+#define BV_DCP_CSCCTRL0_RGB_FORMAT__RGB24       0x2
+#define BV_DCP_CSCCTRL0_RGB_FORMAT__YUV422I     0x3
+#define BF_DCP_CSCCTRL0_RGB_FORMAT(v)           (((v) & 0x3) << 8)
+#define BFM_DCP_CSCCTRL0_RGB_FORMAT(v)          BM_DCP_CSCCTRL0_RGB_FORMAT
+#define BF_DCP_CSCCTRL0_RGB_FORMAT_V(e)         BF_DCP_CSCCTRL0_RGB_FORMAT(BV_DCP_CSCCTRL0_RGB_FORMAT__##e)
+#define BFM_DCP_CSCCTRL0_RGB_FORMAT_V(v)        BM_DCP_CSCCTRL0_RGB_FORMAT
+#define BP_DCP_CSCCTRL0_YUV_FORMAT              4
+#define BM_DCP_CSCCTRL0_YUV_FORMAT              0xf0
+#define BV_DCP_CSCCTRL0_YUV_FORMAT__YUV420      0x0
+#define BV_DCP_CSCCTRL0_YUV_FORMAT__YUV422      0x2
+#define BF_DCP_CSCCTRL0_YUV_FORMAT(v)           (((v) & 0xf) << 4)
+#define BFM_DCP_CSCCTRL0_YUV_FORMAT(v)          BM_DCP_CSCCTRL0_YUV_FORMAT
+#define BF_DCP_CSCCTRL0_YUV_FORMAT_V(e)         BF_DCP_CSCCTRL0_YUV_FORMAT(BV_DCP_CSCCTRL0_YUV_FORMAT__##e)
+#define BFM_DCP_CSCCTRL0_YUV_FORMAT_V(v)        BM_DCP_CSCCTRL0_YUV_FORMAT
+#define BP_DCP_CSCCTRL0_ENABLE                  0
+#define BM_DCP_CSCCTRL0_ENABLE                  0x1
+#define BF_DCP_CSCCTRL0_ENABLE(v)               (((v) & 0x1) << 0)
+#define BFM_DCP_CSCCTRL0_ENABLE(v)              BM_DCP_CSCCTRL0_ENABLE
+#define BF_DCP_CSCCTRL0_ENABLE_V(e)             BF_DCP_CSCCTRL0_ENABLE(BV_DCP_CSCCTRL0_ENABLE__##e)
+#define BFM_DCP_CSCCTRL0_ENABLE_V(v)            BM_DCP_CSCCTRL0_ENABLE
+
+#define HW_DCP_CSCSTAT                                  HW(DCP_CSCSTAT)
+#define HWA_DCP_CSCSTAT                                 (0x80028000 + 0x310)
+#define HWT_DCP_CSCSTAT                                 HWIO_32_RW
+#define HWN_DCP_CSCSTAT                                 DCP_CSCSTAT
+#define HWI_DCP_CSCSTAT                                 
+#define HW_DCP_CSCSTAT_SET                              HW(DCP_CSCSTAT_SET)
+#define HWA_DCP_CSCSTAT_SET                             (HWA_DCP_CSCSTAT + 0x4)
+#define HWT_DCP_CSCSTAT_SET                             HWIO_32_WO
+#define HWN_DCP_CSCSTAT_SET                             DCP_CSCSTAT
+#define HWI_DCP_CSCSTAT_SET                             
+#define HW_DCP_CSCSTAT_CLR                              HW(DCP_CSCSTAT_CLR)
+#define HWA_DCP_CSCSTAT_CLR                             (HWA_DCP_CSCSTAT + 0x8)
+#define HWT_DCP_CSCSTAT_CLR                             HWIO_32_WO
+#define HWN_DCP_CSCSTAT_CLR                             DCP_CSCSTAT
+#define HWI_DCP_CSCSTAT_CLR                             
+#define HW_DCP_CSCSTAT_TOG                              HW(DCP_CSCSTAT_TOG)
+#define HWA_DCP_CSCSTAT_TOG                             (HWA_DCP_CSCSTAT + 0xc)
+#define HWT_DCP_CSCSTAT_TOG                             HWIO_32_WO
+#define HWN_DCP_CSCSTAT_TOG                             DCP_CSCSTAT
+#define HWI_DCP_CSCSTAT_TOG                             
+#define BP_DCP_CSCSTAT_ERROR_CODE                       16
+#define BM_DCP_CSCSTAT_ERROR_CODE                       0xff0000
+#define BV_DCP_CSCSTAT_ERROR_CODE__LUMA0_FETCH_ERROR_Y0 0x1
+#define BV_DCP_CSCSTAT_ERROR_CODE__LUMA1_FETCH_ERROR_Y1 0x2
+#define BV_DCP_CSCSTAT_ERROR_CODE__CHROMA_FETCH_ERROR_U 0x3
+#define BV_DCP_CSCSTAT_ERROR_CODE__CHROMA_FETCH_ERROR_V 0x4
+#define BF_DCP_CSCSTAT_ERROR_CODE(v)                    (((v) & 0xff) << 16)
+#define BFM_DCP_CSCSTAT_ERROR_CODE(v)                   BM_DCP_CSCSTAT_ERROR_CODE
+#define BF_DCP_CSCSTAT_ERROR_CODE_V(e)                  BF_DCP_CSCSTAT_ERROR_CODE(BV_DCP_CSCSTAT_ERROR_CODE__##e)
+#define BFM_DCP_CSCSTAT_ERROR_CODE_V(v)                 BM_DCP_CSCSTAT_ERROR_CODE
+#define BP_DCP_CSCSTAT_ERROR_DST                        5
+#define BM_DCP_CSCSTAT_ERROR_DST                        0x20
+#define BF_DCP_CSCSTAT_ERROR_DST(v)                     (((v) & 0x1) << 5)
+#define BFM_DCP_CSCSTAT_ERROR_DST(v)                    BM_DCP_CSCSTAT_ERROR_DST
+#define BF_DCP_CSCSTAT_ERROR_DST_V(e)                   BF_DCP_CSCSTAT_ERROR_DST(BV_DCP_CSCSTAT_ERROR_DST__##e)
+#define BFM_DCP_CSCSTAT_ERROR_DST_V(v)                  BM_DCP_CSCSTAT_ERROR_DST
+#define BP_DCP_CSCSTAT_ERROR_SRC                        4
+#define BM_DCP_CSCSTAT_ERROR_SRC                        0x10
+#define BF_DCP_CSCSTAT_ERROR_SRC(v)                     (((v) & 0x1) << 4)
+#define BFM_DCP_CSCSTAT_ERROR_SRC(v)                    BM_DCP_CSCSTAT_ERROR_SRC
+#define BF_DCP_CSCSTAT_ERROR_SRC_V(e)                   BF_DCP_CSCSTAT_ERROR_SRC(BV_DCP_CSCSTAT_ERROR_SRC__##e)
+#define BFM_DCP_CSCSTAT_ERROR_SRC_V(v)                  BM_DCP_CSCSTAT_ERROR_SRC
+#define BP_DCP_CSCSTAT_ERROR_SETUP                      2
+#define BM_DCP_CSCSTAT_ERROR_SETUP                      0x4
+#define BF_DCP_CSCSTAT_ERROR_SETUP(v)                   (((v) & 0x1) << 2)
+#define BFM_DCP_CSCSTAT_ERROR_SETUP(v)                  BM_DCP_CSCSTAT_ERROR_SETUP
+#define BF_DCP_CSCSTAT_ERROR_SETUP_V(e)                 BF_DCP_CSCSTAT_ERROR_SETUP(BV_DCP_CSCSTAT_ERROR_SETUP__##e)
+#define BFM_DCP_CSCSTAT_ERROR_SETUP_V(v)                BM_DCP_CSCSTAT_ERROR_SETUP
+#define BP_DCP_CSCSTAT_COMPLETE                         0
+#define BM_DCP_CSCSTAT_COMPLETE                         0x1
+#define BF_DCP_CSCSTAT_COMPLETE(v)                      (((v) & 0x1) << 0)
+#define BFM_DCP_CSCSTAT_COMPLETE(v)                     BM_DCP_CSCSTAT_COMPLETE
+#define BF_DCP_CSCSTAT_COMPLETE_V(e)                    BF_DCP_CSCSTAT_COMPLETE(BV_DCP_CSCSTAT_COMPLETE__##e)
+#define BFM_DCP_CSCSTAT_COMPLETE_V(v)                   BM_DCP_CSCSTAT_COMPLETE
+
+#define HW_DCP_CSCOUTBUFPARAM                   HW(DCP_CSCOUTBUFPARAM)
+#define HWA_DCP_CSCOUTBUFPARAM                  (0x80028000 + 0x320)
+#define HWT_DCP_CSCOUTBUFPARAM                  HWIO_32_RW
+#define HWN_DCP_CSCOUTBUFPARAM                  DCP_CSCOUTBUFPARAM
+#define HWI_DCP_CSCOUTBUFPARAM                  
+#define BP_DCP_CSCOUTBUFPARAM_FIELD_SIZE        12
+#define BM_DCP_CSCOUTBUFPARAM_FIELD_SIZE        0xfff000
+#define BF_DCP_CSCOUTBUFPARAM_FIELD_SIZE(v)     (((v) & 0xfff) << 12)
+#define BFM_DCP_CSCOUTBUFPARAM_FIELD_SIZE(v)    BM_DCP_CSCOUTBUFPARAM_FIELD_SIZE
+#define BF_DCP_CSCOUTBUFPARAM_FIELD_SIZE_V(e)   BF_DCP_CSCOUTBUFPARAM_FIELD_SIZE(BV_DCP_CSCOUTBUFPARAM_FIELD_SIZE__##e)
+#define BFM_DCP_CSCOUTBUFPARAM_FIELD_SIZE_V(v)  BM_DCP_CSCOUTBUFPARAM_FIELD_SIZE
+#define BP_DCP_CSCOUTBUFPARAM_LINE_SIZE         0
+#define BM_DCP_CSCOUTBUFPARAM_LINE_SIZE         0xfff
+#define BF_DCP_CSCOUTBUFPARAM_LINE_SIZE(v)      (((v) & 0xfff) << 0)
+#define BFM_DCP_CSCOUTBUFPARAM_LINE_SIZE(v)     BM_DCP_CSCOUTBUFPARAM_LINE_SIZE
+#define BF_DCP_CSCOUTBUFPARAM_LINE_SIZE_V(e)    BF_DCP_CSCOUTBUFPARAM_LINE_SIZE(BV_DCP_CSCOUTBUFPARAM_LINE_SIZE__##e)
+#define BFM_DCP_CSCOUTBUFPARAM_LINE_SIZE_V(v)   BM_DCP_CSCOUTBUFPARAM_LINE_SIZE
+
+#define HW_DCP_CSCINBUFPARAM                    HW(DCP_CSCINBUFPARAM)
+#define HWA_DCP_CSCINBUFPARAM                   (0x80028000 + 0x330)
+#define HWT_DCP_CSCINBUFPARAM                   HWIO_32_RW
+#define HWN_DCP_CSCINBUFPARAM                   DCP_CSCINBUFPARAM
+#define HWI_DCP_CSCINBUFPARAM                   
+#define BP_DCP_CSCINBUFPARAM_LINE_SIZE          0
+#define BM_DCP_CSCINBUFPARAM_LINE_SIZE          0xfff
+#define BF_DCP_CSCINBUFPARAM_LINE_SIZE(v)       (((v) & 0xfff) << 0)
+#define BFM_DCP_CSCINBUFPARAM_LINE_SIZE(v)      BM_DCP_CSCINBUFPARAM_LINE_SIZE
+#define BF_DCP_CSCINBUFPARAM_LINE_SIZE_V(e)     BF_DCP_CSCINBUFPARAM_LINE_SIZE(BV_DCP_CSCINBUFPARAM_LINE_SIZE__##e)
+#define BFM_DCP_CSCINBUFPARAM_LINE_SIZE_V(v)    BM_DCP_CSCINBUFPARAM_LINE_SIZE
+
+#define HW_DCP_CSCRGB               HW(DCP_CSCRGB)
+#define HWA_DCP_CSCRGB              (0x80028000 + 0x340)
+#define HWT_DCP_CSCRGB              HWIO_32_RW
+#define HWN_DCP_CSCRGB              DCP_CSCRGB
+#define HWI_DCP_CSCRGB              
+#define BP_DCP_CSCRGB_ADDR          0
+#define BM_DCP_CSCRGB_ADDR          0xffffffff
+#define BF_DCP_CSCRGB_ADDR(v)       (((v) & 0xffffffff) << 0)
+#define BFM_DCP_CSCRGB_ADDR(v)      BM_DCP_CSCRGB_ADDR
+#define BF_DCP_CSCRGB_ADDR_V(e)     BF_DCP_CSCRGB_ADDR(BV_DCP_CSCRGB_ADDR__##e)
+#define BFM_DCP_CSCRGB_ADDR_V(v)    BM_DCP_CSCRGB_ADDR
+
+#define HW_DCP_CSCLUMA              HW(DCP_CSCLUMA)
+#define HWA_DCP_CSCLUMA             (0x80028000 + 0x350)
+#define HWT_DCP_CSCLUMA             HWIO_32_RW
+#define HWN_DCP_CSCLUMA             DCP_CSCLUMA
+#define HWI_DCP_CSCLUMA             
+#define BP_DCP_CSCLUMA_ADDR         0
+#define BM_DCP_CSCLUMA_ADDR         0xffffffff
+#define BF_DCP_CSCLUMA_ADDR(v)      (((v) & 0xffffffff) << 0)
+#define BFM_DCP_CSCLUMA_ADDR(v)     BM_DCP_CSCLUMA_ADDR
+#define BF_DCP_CSCLUMA_ADDR_V(e)    BF_DCP_CSCLUMA_ADDR(BV_DCP_CSCLUMA_ADDR__##e)
+#define BFM_DCP_CSCLUMA_ADDR_V(v)   BM_DCP_CSCLUMA_ADDR
+
+#define HW_DCP_CSCCHROMAU               HW(DCP_CSCCHROMAU)
+#define HWA_DCP_CSCCHROMAU              (0x80028000 + 0x360)
+#define HWT_DCP_CSCCHROMAU              HWIO_32_RW
+#define HWN_DCP_CSCCHROMAU              DCP_CSCCHROMAU
+#define HWI_DCP_CSCCHROMAU              
+#define BP_DCP_CSCCHROMAU_ADDR          0
+#define BM_DCP_CSCCHROMAU_ADDR          0xffffffff
+#define BF_DCP_CSCCHROMAU_ADDR(v)       (((v) & 0xffffffff) << 0)
+#define BFM_DCP_CSCCHROMAU_ADDR(v)      BM_DCP_CSCCHROMAU_ADDR
+#define BF_DCP_CSCCHROMAU_ADDR_V(e)     BF_DCP_CSCCHROMAU_ADDR(BV_DCP_CSCCHROMAU_ADDR__##e)
+#define BFM_DCP_CSCCHROMAU_ADDR_V(v)    BM_DCP_CSCCHROMAU_ADDR
+
+#define HW_DCP_CSCCHROMAV               HW(DCP_CSCCHROMAV)
+#define HWA_DCP_CSCCHROMAV              (0x80028000 + 0x370)
+#define HWT_DCP_CSCCHROMAV              HWIO_32_RW
+#define HWN_DCP_CSCCHROMAV              DCP_CSCCHROMAV
+#define HWI_DCP_CSCCHROMAV              
+#define BP_DCP_CSCCHROMAV_ADDR          0
+#define BM_DCP_CSCCHROMAV_ADDR          0xffffffff
+#define BF_DCP_CSCCHROMAV_ADDR(v)       (((v) & 0xffffffff) << 0)
+#define BFM_DCP_CSCCHROMAV_ADDR(v)      BM_DCP_CSCCHROMAV_ADDR
+#define BF_DCP_CSCCHROMAV_ADDR_V(e)     BF_DCP_CSCCHROMAV_ADDR(BV_DCP_CSCCHROMAV_ADDR__##e)
+#define BFM_DCP_CSCCHROMAV_ADDR_V(v)    BM_DCP_CSCCHROMAV_ADDR
+
+#define HW_DCP_CSCCOEFF0                    HW(DCP_CSCCOEFF0)
+#define HWA_DCP_CSCCOEFF0                   (0x80028000 + 0x380)
+#define HWT_DCP_CSCCOEFF0                   HWIO_32_RW
+#define HWN_DCP_CSCCOEFF0                   DCP_CSCCOEFF0
+#define HWI_DCP_CSCCOEFF0                   
+#define BP_DCP_CSCCOEFF0_C0                 16
+#define BM_DCP_CSCCOEFF0_C0                 0x3ff0000
+#define BF_DCP_CSCCOEFF0_C0(v)              (((v) & 0x3ff) << 16)
+#define BFM_DCP_CSCCOEFF0_C0(v)             BM_DCP_CSCCOEFF0_C0
+#define BF_DCP_CSCCOEFF0_C0_V(e)            BF_DCP_CSCCOEFF0_C0(BV_DCP_CSCCOEFF0_C0__##e)
+#define BFM_DCP_CSCCOEFF0_C0_V(v)           BM_DCP_CSCCOEFF0_C0
+#define BP_DCP_CSCCOEFF0_UV_OFFSET          8
+#define BM_DCP_CSCCOEFF0_UV_OFFSET          0xff00
+#define BF_DCP_CSCCOEFF0_UV_OFFSET(v)       (((v) & 0xff) << 8)
+#define BFM_DCP_CSCCOEFF0_UV_OFFSET(v)      BM_DCP_CSCCOEFF0_UV_OFFSET
+#define BF_DCP_CSCCOEFF0_UV_OFFSET_V(e)     BF_DCP_CSCCOEFF0_UV_OFFSET(BV_DCP_CSCCOEFF0_UV_OFFSET__##e)
+#define BFM_DCP_CSCCOEFF0_UV_OFFSET_V(v)    BM_DCP_CSCCOEFF0_UV_OFFSET
+#define BP_DCP_CSCCOEFF0_Y_OFFSET           0
+#define BM_DCP_CSCCOEFF0_Y_OFFSET           0xff
+#define BF_DCP_CSCCOEFF0_Y_OFFSET(v)        (((v) & 0xff) << 0)
+#define BFM_DCP_CSCCOEFF0_Y_OFFSET(v)       BM_DCP_CSCCOEFF0_Y_OFFSET
+#define BF_DCP_CSCCOEFF0_Y_OFFSET_V(e)      BF_DCP_CSCCOEFF0_Y_OFFSET(BV_DCP_CSCCOEFF0_Y_OFFSET__##e)
+#define BFM_DCP_CSCCOEFF0_Y_OFFSET_V(v)     BM_DCP_CSCCOEFF0_Y_OFFSET
+
+#define HW_DCP_CSCCOEFF1            HW(DCP_CSCCOEFF1)
+#define HWA_DCP_CSCCOEFF1           (0x80028000 + 0x390)
+#define HWT_DCP_CSCCOEFF1           HWIO_32_RW
+#define HWN_DCP_CSCCOEFF1           DCP_CSCCOEFF1
+#define HWI_DCP_CSCCOEFF1           
+#define BP_DCP_CSCCOEFF1_C1         16
+#define BM_DCP_CSCCOEFF1_C1         0x3ff0000
+#define BF_DCP_CSCCOEFF1_C1(v)      (((v) & 0x3ff) << 16)
+#define BFM_DCP_CSCCOEFF1_C1(v)     BM_DCP_CSCCOEFF1_C1
+#define BF_DCP_CSCCOEFF1_C1_V(e)    BF_DCP_CSCCOEFF1_C1(BV_DCP_CSCCOEFF1_C1__##e)
+#define BFM_DCP_CSCCOEFF1_C1_V(v)   BM_DCP_CSCCOEFF1_C1
+#define BP_DCP_CSCCOEFF1_C4         0
+#define BM_DCP_CSCCOEFF1_C4         0x3ff
+#define BF_DCP_CSCCOEFF1_C4(v)      (((v) & 0x3ff) << 0)
+#define BFM_DCP_CSCCOEFF1_C4(v)     BM_DCP_CSCCOEFF1_C4
+#define BF_DCP_CSCCOEFF1_C4_V(e)    BF_DCP_CSCCOEFF1_C4(BV_DCP_CSCCOEFF1_C4__##e)
+#define BFM_DCP_CSCCOEFF1_C4_V(v)   BM_DCP_CSCCOEFF1_C4
+
+#define HW_DCP_CSCCOEFF2            HW(DCP_CSCCOEFF2)
+#define HWA_DCP_CSCCOEFF2           (0x80028000 + 0x3a0)
+#define HWT_DCP_CSCCOEFF2           HWIO_32_RW
+#define HWN_DCP_CSCCOEFF2           DCP_CSCCOEFF2
+#define HWI_DCP_CSCCOEFF2           
+#define BP_DCP_CSCCOEFF2_C2         16
+#define BM_DCP_CSCCOEFF2_C2         0x3ff0000
+#define BF_DCP_CSCCOEFF2_C2(v)      (((v) & 0x3ff) << 16)
+#define BFM_DCP_CSCCOEFF2_C2(v)     BM_DCP_CSCCOEFF2_C2
+#define BF_DCP_CSCCOEFF2_C2_V(e)    BF_DCP_CSCCOEFF2_C2(BV_DCP_CSCCOEFF2_C2__##e)
+#define BFM_DCP_CSCCOEFF2_C2_V(v)   BM_DCP_CSCCOEFF2_C2
+#define BP_DCP_CSCCOEFF2_C3         0
+#define BM_DCP_CSCCOEFF2_C3         0x3ff
+#define BF_DCP_CSCCOEFF2_C3(v)      (((v) & 0x3ff) << 0)
+#define BFM_DCP_CSCCOEFF2_C3(v)     BM_DCP_CSCCOEFF2_C3
+#define BF_DCP_CSCCOEFF2_C3_V(e)    BF_DCP_CSCCOEFF2_C3(BV_DCP_CSCCOEFF2_C3__##e)
+#define BFM_DCP_CSCCOEFF2_C3_V(v)   BM_DCP_CSCCOEFF2_C3
+
+#define HW_DCP_CSCXSCALE                HW(DCP_CSCXSCALE)
+#define HWA_DCP_CSCXSCALE               (0x80028000 + 0x3e0)
+#define HWT_DCP_CSCXSCALE               HWIO_32_RW
+#define HWN_DCP_CSCXSCALE               DCP_CSCXSCALE
+#define HWI_DCP_CSCXSCALE               
+#define BP_DCP_CSCXSCALE_INT            24
+#define BM_DCP_CSCXSCALE_INT            0x3000000
+#define BF_DCP_CSCXSCALE_INT(v)         (((v) & 0x3) << 24)
+#define BFM_DCP_CSCXSCALE_INT(v)        BM_DCP_CSCXSCALE_INT
+#define BF_DCP_CSCXSCALE_INT_V(e)       BF_DCP_CSCXSCALE_INT(BV_DCP_CSCXSCALE_INT__##e)
+#define BFM_DCP_CSCXSCALE_INT_V(v)      BM_DCP_CSCXSCALE_INT
+#define BP_DCP_CSCXSCALE_FRAC           12
+#define BM_DCP_CSCXSCALE_FRAC           0xfff000
+#define BF_DCP_CSCXSCALE_FRAC(v)        (((v) & 0xfff) << 12)
+#define BFM_DCP_CSCXSCALE_FRAC(v)       BM_DCP_CSCXSCALE_FRAC
+#define BF_DCP_CSCXSCALE_FRAC_V(e)      BF_DCP_CSCXSCALE_FRAC(BV_DCP_CSCXSCALE_FRAC__##e)
+#define BFM_DCP_CSCXSCALE_FRAC_V(v)     BM_DCP_CSCXSCALE_FRAC
+#define BP_DCP_CSCXSCALE_WIDTH          0
+#define BM_DCP_CSCXSCALE_WIDTH          0xfff
+#define BF_DCP_CSCXSCALE_WIDTH(v)       (((v) & 0xfff) << 0)
+#define BFM_DCP_CSCXSCALE_WIDTH(v)      BM_DCP_CSCXSCALE_WIDTH
+#define BF_DCP_CSCXSCALE_WIDTH_V(e)     BF_DCP_CSCXSCALE_WIDTH(BV_DCP_CSCXSCALE_WIDTH__##e)
+#define BFM_DCP_CSCXSCALE_WIDTH_V(v)    BM_DCP_CSCXSCALE_WIDTH
+
+#define HW_DCP_CSCYSCALE                HW(DCP_CSCYSCALE)
+#define HWA_DCP_CSCYSCALE               (0x80028000 + 0x3f0)
+#define HWT_DCP_CSCYSCALE               HWIO_32_RW
+#define HWN_DCP_CSCYSCALE               DCP_CSCYSCALE
+#define HWI_DCP_CSCYSCALE               
+#define BP_DCP_CSCYSCALE_INT            24
+#define BM_DCP_CSCYSCALE_INT            0x3000000
+#define BF_DCP_CSCYSCALE_INT(v)         (((v) & 0x3) << 24)
+#define BFM_DCP_CSCYSCALE_INT(v)        BM_DCP_CSCYSCALE_INT
+#define BF_DCP_CSCYSCALE_INT_V(e)       BF_DCP_CSCYSCALE_INT(BV_DCP_CSCYSCALE_INT__##e)
+#define BFM_DCP_CSCYSCALE_INT_V(v)      BM_DCP_CSCYSCALE_INT
+#define BP_DCP_CSCYSCALE_FRAC           12
+#define BM_DCP_CSCYSCALE_FRAC           0xfff000
+#define BF_DCP_CSCYSCALE_FRAC(v)        (((v) & 0xfff) << 12)
+#define BFM_DCP_CSCYSCALE_FRAC(v)       BM_DCP_CSCYSCALE_FRAC
+#define BF_DCP_CSCYSCALE_FRAC_V(e)      BF_DCP_CSCYSCALE_FRAC(BV_DCP_CSCYSCALE_FRAC__##e)
+#define BFM_DCP_CSCYSCALE_FRAC_V(v)     BM_DCP_CSCYSCALE_FRAC
+#define BP_DCP_CSCYSCALE_HEIGHT         0
+#define BM_DCP_CSCYSCALE_HEIGHT         0xfff
+#define BF_DCP_CSCYSCALE_HEIGHT(v)      (((v) & 0xfff) << 0)
+#define BFM_DCP_CSCYSCALE_HEIGHT(v)     BM_DCP_CSCYSCALE_HEIGHT
+#define BF_DCP_CSCYSCALE_HEIGHT_V(e)    BF_DCP_CSCYSCALE_HEIGHT(BV_DCP_CSCYSCALE_HEIGHT__##e)
+#define BFM_DCP_CSCYSCALE_HEIGHT_V(v)   BM_DCP_CSCYSCALE_HEIGHT
+
+#define HW_DCP_DBGSELECT                HW(DCP_DBGSELECT)
+#define HWA_DCP_DBGSELECT               (0x80028000 + 0x400)
+#define HWT_DCP_DBGSELECT               HWIO_32_RW
+#define HWN_DCP_DBGSELECT               DCP_DBGSELECT
+#define HWI_DCP_DBGSELECT               
+#define BP_DCP_DBGSELECT_INDEX          0
+#define BM_DCP_DBGSELECT_INDEX          0xff
+#define BV_DCP_DBGSELECT_INDEX__CONTROL 0x1
+#define BV_DCP_DBGSELECT_INDEX__OTPKEY0 0x10
+#define BV_DCP_DBGSELECT_INDEX__OTPKEY1 0x11
+#define BV_DCP_DBGSELECT_INDEX__OTPKEY2 0x12
+#define BV_DCP_DBGSELECT_INDEX__OTPKEY3 0x13
+#define BF_DCP_DBGSELECT_INDEX(v)       (((v) & 0xff) << 0)
+#define BFM_DCP_DBGSELECT_INDEX(v)      BM_DCP_DBGSELECT_INDEX
+#define BF_DCP_DBGSELECT_INDEX_V(e)     BF_DCP_DBGSELECT_INDEX(BV_DCP_DBGSELECT_INDEX__##e)
+#define BFM_DCP_DBGSELECT_INDEX_V(v)    BM_DCP_DBGSELECT_INDEX
+
+#define HW_DCP_DBGDATA              HW(DCP_DBGDATA)
+#define HWA_DCP_DBGDATA             (0x80028000 + 0x410)
+#define HWT_DCP_DBGDATA             HWIO_32_RW
+#define HWN_DCP_DBGDATA             DCP_DBGDATA
+#define HWI_DCP_DBGDATA             
+#define BP_DCP_DBGDATA_DATA         0
+#define BM_DCP_DBGDATA_DATA         0xffffffff
+#define BF_DCP_DBGDATA_DATA(v)      (((v) & 0xffffffff) << 0)
+#define BFM_DCP_DBGDATA_DATA(v)     BM_DCP_DBGDATA_DATA
+#define BF_DCP_DBGDATA_DATA_V(e)    BF_DCP_DBGDATA_DATA(BV_DCP_DBGDATA_DATA__##e)
+#define BFM_DCP_DBGDATA_DATA_V(v)   BM_DCP_DBGDATA_DATA
+
+#define HW_DCP_VERSION              HW(DCP_VERSION)
+#define HWA_DCP_VERSION             (0x80028000 + 0x420)
+#define HWT_DCP_VERSION             HWIO_32_RW
+#define HWN_DCP_VERSION             DCP_VERSION
+#define HWI_DCP_VERSION             
+#define BP_DCP_VERSION_MAJOR        24
+#define BM_DCP_VERSION_MAJOR        0xff000000
+#define BF_DCP_VERSION_MAJOR(v)     (((v) & 0xff) << 24)
+#define BFM_DCP_VERSION_MAJOR(v)    BM_DCP_VERSION_MAJOR
+#define BF_DCP_VERSION_MAJOR_V(e)   BF_DCP_VERSION_MAJOR(BV_DCP_VERSION_MAJOR__##e)
+#define BFM_DCP_VERSION_MAJOR_V(v)  BM_DCP_VERSION_MAJOR
+#define BP_DCP_VERSION_MINOR        16
+#define BM_DCP_VERSION_MINOR        0xff0000
+#define BF_DCP_VERSION_MINOR(v)     (((v) & 0xff) << 16)
+#define BFM_DCP_VERSION_MINOR(v)    BM_DCP_VERSION_MINOR
+#define BF_DCP_VERSION_MINOR_V(e)   BF_DCP_VERSION_MINOR(BV_DCP_VERSION_MINOR__##e)
+#define BFM_DCP_VERSION_MINOR_V(v)  BM_DCP_VERSION_MINOR
+#define BP_DCP_VERSION_STEP         0
+#define BM_DCP_VERSION_STEP         0xffff
+#define BF_DCP_VERSION_STEP(v)      (((v) & 0xffff) << 0)
+#define BFM_DCP_VERSION_STEP(v)     BM_DCP_VERSION_STEP
+#define BF_DCP_VERSION_STEP_V(e)    BF_DCP_VERSION_STEP(BV_DCP_VERSION_STEP__##e)
+#define BFM_DCP_VERSION_STEP_V(v)   BM_DCP_VERSION_STEP
+
+#endif /* __HEADERGEN_STMP3700_DCP_H__*/
diff --git a/firmware/target/arm/imx233/regs/stmp3700/digctl.h b/firmware/target/arm/imx233/regs/stmp3700/digctl.h
new file mode 100644
index 0000000000..b85edec35a
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3700/digctl.h
@@ -0,0 +1,1103 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * stmp3700 version: 2.4.0
+ * stmp3700 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_STMP3700_DIGCTL_H__
+#define __HEADERGEN_STMP3700_DIGCTL_H__
+
+#define HW_DIGCTL_CTRL                                      HW(DIGCTL_CTRL)
+#define HWA_DIGCTL_CTRL                                     (0x8001c000 + 0x0)
+#define HWT_DIGCTL_CTRL                                     HWIO_32_RW
+#define HWN_DIGCTL_CTRL                                     DIGCTL_CTRL
+#define HWI_DIGCTL_CTRL                                     
+#define HW_DIGCTL_CTRL_SET                                  HW(DIGCTL_CTRL_SET)
+#define HWA_DIGCTL_CTRL_SET                                 (HWA_DIGCTL_CTRL + 0x4)
+#define HWT_DIGCTL_CTRL_SET                                 HWIO_32_WO
+#define HWN_DIGCTL_CTRL_SET                                 DIGCTL_CTRL
+#define HWI_DIGCTL_CTRL_SET                                 
+#define HW_DIGCTL_CTRL_CLR                                  HW(DIGCTL_CTRL_CLR)
+#define HWA_DIGCTL_CTRL_CLR                                 (HWA_DIGCTL_CTRL + 0x8)
+#define HWT_DIGCTL_CTRL_CLR                                 HWIO_32_WO
+#define HWN_DIGCTL_CTRL_CLR                                 DIGCTL_CTRL
+#define HWI_DIGCTL_CTRL_CLR                                 
+#define HW_DIGCTL_CTRL_TOG                                  HW(DIGCTL_CTRL_TOG)
+#define HWA_DIGCTL_CTRL_TOG                                 (HWA_DIGCTL_CTRL + 0xc)
+#define HWT_DIGCTL_CTRL_TOG                                 HWIO_32_WO
+#define HWN_DIGCTL_CTRL_TOG                                 DIGCTL_CTRL
+#define HWI_DIGCTL_CTRL_TOG                                 
+#define BP_DIGCTL_CTRL_TRAP_IRQ                             29
+#define BM_DIGCTL_CTRL_TRAP_IRQ                             0x20000000
+#define BF_DIGCTL_CTRL_TRAP_IRQ(v)                          (((v) & 0x1) << 29)
+#define BFM_DIGCTL_CTRL_TRAP_IRQ(v)                         BM_DIGCTL_CTRL_TRAP_IRQ
+#define BF_DIGCTL_CTRL_TRAP_IRQ_V(e)                        BF_DIGCTL_CTRL_TRAP_IRQ(BV_DIGCTL_CTRL_TRAP_IRQ__##e)
+#define BFM_DIGCTL_CTRL_TRAP_IRQ_V(v)                       BM_DIGCTL_CTRL_TRAP_IRQ
+#define BP_DIGCTL_CTRL_DCP_BIST_CLKEN                       23
+#define BM_DIGCTL_CTRL_DCP_BIST_CLKEN                       0x800000
+#define BF_DIGCTL_CTRL_DCP_BIST_CLKEN(v)                    (((v) & 0x1) << 23)
+#define BFM_DIGCTL_CTRL_DCP_BIST_CLKEN(v)                   BM_DIGCTL_CTRL_DCP_BIST_CLKEN
+#define BF_DIGCTL_CTRL_DCP_BIST_CLKEN_V(e)                  BF_DIGCTL_CTRL_DCP_BIST_CLKEN(BV_DIGCTL_CTRL_DCP_BIST_CLKEN__##e)
+#define BFM_DIGCTL_CTRL_DCP_BIST_CLKEN_V(v)                 BM_DIGCTL_CTRL_DCP_BIST_CLKEN
+#define BP_DIGCTL_CTRL_DCP_BIST_START                       22
+#define BM_DIGCTL_CTRL_DCP_BIST_START                       0x400000
+#define BF_DIGCTL_CTRL_DCP_BIST_START(v)                    (((v) & 0x1) << 22)
+#define BFM_DIGCTL_CTRL_DCP_BIST_START(v)                   BM_DIGCTL_CTRL_DCP_BIST_START
+#define BF_DIGCTL_CTRL_DCP_BIST_START_V(e)                  BF_DIGCTL_CTRL_DCP_BIST_START(BV_DIGCTL_CTRL_DCP_BIST_START__##e)
+#define BFM_DIGCTL_CTRL_DCP_BIST_START_V(v)                 BM_DIGCTL_CTRL_DCP_BIST_START
+#define BP_DIGCTL_CTRL_ARM_BIST_CLKEN                       21
+#define BM_DIGCTL_CTRL_ARM_BIST_CLKEN                       0x200000
+#define BF_DIGCTL_CTRL_ARM_BIST_CLKEN(v)                    (((v) & 0x1) << 21)
+#define BFM_DIGCTL_CTRL_ARM_BIST_CLKEN(v)                   BM_DIGCTL_CTRL_ARM_BIST_CLKEN
+#define BF_DIGCTL_CTRL_ARM_BIST_CLKEN_V(e)                  BF_DIGCTL_CTRL_ARM_BIST_CLKEN(BV_DIGCTL_CTRL_ARM_BIST_CLKEN__##e)
+#define BFM_DIGCTL_CTRL_ARM_BIST_CLKEN_V(v)                 BM_DIGCTL_CTRL_ARM_BIST_CLKEN
+#define BP_DIGCTL_CTRL_USB_TESTMODE                         20
+#define BM_DIGCTL_CTRL_USB_TESTMODE                         0x100000
+#define BF_DIGCTL_CTRL_USB_TESTMODE(v)                      (((v) & 0x1) << 20)
+#define BFM_DIGCTL_CTRL_USB_TESTMODE(v)                     BM_DIGCTL_CTRL_USB_TESTMODE
+#define BF_DIGCTL_CTRL_USB_TESTMODE_V(e)                    BF_DIGCTL_CTRL_USB_TESTMODE(BV_DIGCTL_CTRL_USB_TESTMODE__##e)
+#define BFM_DIGCTL_CTRL_USB_TESTMODE_V(v)                   BM_DIGCTL_CTRL_USB_TESTMODE
+#define BP_DIGCTL_CTRL_ANALOG_TESTMODE                      19
+#define BM_DIGCTL_CTRL_ANALOG_TESTMODE                      0x80000
+#define BF_DIGCTL_CTRL_ANALOG_TESTMODE(v)                   (((v) & 0x1) << 19)
+#define BFM_DIGCTL_CTRL_ANALOG_TESTMODE(v)                  BM_DIGCTL_CTRL_ANALOG_TESTMODE
+#define BF_DIGCTL_CTRL_ANALOG_TESTMODE_V(e)                 BF_DIGCTL_CTRL_ANALOG_TESTMODE(BV_DIGCTL_CTRL_ANALOG_TESTMODE__##e)
+#define BFM_DIGCTL_CTRL_ANALOG_TESTMODE_V(v)                BM_DIGCTL_CTRL_ANALOG_TESTMODE
+#define BP_DIGCTL_CTRL_DIGITAL_TESTMODE                     18
+#define BM_DIGCTL_CTRL_DIGITAL_TESTMODE                     0x40000
+#define BF_DIGCTL_CTRL_DIGITAL_TESTMODE(v)                  (((v) & 0x1) << 18)
+#define BFM_DIGCTL_CTRL_DIGITAL_TESTMODE(v)                 BM_DIGCTL_CTRL_DIGITAL_TESTMODE
+#define BF_DIGCTL_CTRL_DIGITAL_TESTMODE_V(e)                BF_DIGCTL_CTRL_DIGITAL_TESTMODE(BV_DIGCTL_CTRL_DIGITAL_TESTMODE__##e)
+#define BFM_DIGCTL_CTRL_DIGITAL_TESTMODE_V(v)               BM_DIGCTL_CTRL_DIGITAL_TESTMODE
+#define BP_DIGCTL_CTRL_ARM_BIST_START                       17
+#define BM_DIGCTL_CTRL_ARM_BIST_START                       0x20000
+#define BF_DIGCTL_CTRL_ARM_BIST_START(v)                    (((v) & 0x1) << 17)
+#define BFM_DIGCTL_CTRL_ARM_BIST_START(v)                   BM_DIGCTL_CTRL_ARM_BIST_START
+#define BF_DIGCTL_CTRL_ARM_BIST_START_V(e)                  BF_DIGCTL_CTRL_ARM_BIST_START(BV_DIGCTL_CTRL_ARM_BIST_START__##e)
+#define BFM_DIGCTL_CTRL_ARM_BIST_START_V(v)                 BM_DIGCTL_CTRL_ARM_BIST_START
+#define BP_DIGCTL_CTRL_UART_LOOPBACK                        16
+#define BM_DIGCTL_CTRL_UART_LOOPBACK                        0x10000
+#define BV_DIGCTL_CTRL_UART_LOOPBACK__NORMAL                0x0
+#define BV_DIGCTL_CTRL_UART_LOOPBACK__LOOPIT                0x1
+#define BF_DIGCTL_CTRL_UART_LOOPBACK(v)                     (((v) & 0x1) << 16)
+#define BFM_DIGCTL_CTRL_UART_LOOPBACK(v)                    BM_DIGCTL_CTRL_UART_LOOPBACK
+#define BF_DIGCTL_CTRL_UART_LOOPBACK_V(e)                   BF_DIGCTL_CTRL_UART_LOOPBACK(BV_DIGCTL_CTRL_UART_LOOPBACK__##e)
+#define BFM_DIGCTL_CTRL_UART_LOOPBACK_V(v)                  BM_DIGCTL_CTRL_UART_LOOPBACK
+#define BP_DIGCTL_CTRL_SAIF_LOOPBACK                        15
+#define BM_DIGCTL_CTRL_SAIF_LOOPBACK                        0x8000
+#define BV_DIGCTL_CTRL_SAIF_LOOPBACK__NORMAL                0x0
+#define BV_DIGCTL_CTRL_SAIF_LOOPBACK__LOOPIT                0x1
+#define BF_DIGCTL_CTRL_SAIF_LOOPBACK(v)                     (((v) & 0x1) << 15)
+#define BFM_DIGCTL_CTRL_SAIF_LOOPBACK(v)                    BM_DIGCTL_CTRL_SAIF_LOOPBACK
+#define BF_DIGCTL_CTRL_SAIF_LOOPBACK_V(e)                   BF_DIGCTL_CTRL_SAIF_LOOPBACK(BV_DIGCTL_CTRL_SAIF_LOOPBACK__##e)
+#define BFM_DIGCTL_CTRL_SAIF_LOOPBACK_V(v)                  BM_DIGCTL_CTRL_SAIF_LOOPBACK
+#define BP_DIGCTL_CTRL_SAIF_CLKMUX_SEL                      13
+#define BM_DIGCTL_CTRL_SAIF_CLKMUX_SEL                      0x6000
+#define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__MBL_CLK_OUT         0x0
+#define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__BL_CLK_OUT          0x1
+#define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__M_CLK_OUT_BL_CLK_IN 0x2
+#define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__BL_CLK_IN           0x3
+#define BF_DIGCTL_CTRL_SAIF_CLKMUX_SEL(v)                   (((v) & 0x3) << 13)
+#define BFM_DIGCTL_CTRL_SAIF_CLKMUX_SEL(v)                  BM_DIGCTL_CTRL_SAIF_CLKMUX_SEL
+#define BF_DIGCTL_CTRL_SAIF_CLKMUX_SEL_V(e)                 BF_DIGCTL_CTRL_SAIF_CLKMUX_SEL(BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__##e)
+#define BFM_DIGCTL_CTRL_SAIF_CLKMUX_SEL_V(v)                BM_DIGCTL_CTRL_SAIF_CLKMUX_SEL
+#define BP_DIGCTL_CTRL_SAIF_CLKMST_SEL                      12
+#define BM_DIGCTL_CTRL_SAIF_CLKMST_SEL                      0x1000
+#define BV_DIGCTL_CTRL_SAIF_CLKMST_SEL__SAIF1_MST           0x0
+#define BV_DIGCTL_CTRL_SAIF_CLKMST_SEL__SAIF2_MST           0x1
+#define BF_DIGCTL_CTRL_SAIF_CLKMST_SEL(v)                   (((v) & 0x1) << 12)
+#define BFM_DIGCTL_CTRL_SAIF_CLKMST_SEL(v)                  BM_DIGCTL_CTRL_SAIF_CLKMST_SEL
+#define BF_DIGCTL_CTRL_SAIF_CLKMST_SEL_V(e)                 BF_DIGCTL_CTRL_SAIF_CLKMST_SEL(BV_DIGCTL_CTRL_SAIF_CLKMST_SEL__##e)
+#define BFM_DIGCTL_CTRL_SAIF_CLKMST_SEL_V(v)                BM_DIGCTL_CTRL_SAIF_CLKMST_SEL
+#define BP_DIGCTL_CTRL_SAIF_ALT_BITCLK_SEL                  11
+#define BM_DIGCTL_CTRL_SAIF_ALT_BITCLK_SEL                  0x800
+#define BF_DIGCTL_CTRL_SAIF_ALT_BITCLK_SEL(v)               (((v) & 0x1) << 11)
+#define BFM_DIGCTL_CTRL_SAIF_ALT_BITCLK_SEL(v)              BM_DIGCTL_CTRL_SAIF_ALT_BITCLK_SEL
+#define BF_DIGCTL_CTRL_SAIF_ALT_BITCLK_SEL_V(e)             BF_DIGCTL_CTRL_SAIF_ALT_BITCLK_SEL(BV_DIGCTL_CTRL_SAIF_ALT_BITCLK_SEL__##e)
+#define BFM_DIGCTL_CTRL_SAIF_ALT_BITCLK_SEL_V(v)            BM_DIGCTL_CTRL_SAIF_ALT_BITCLK_SEL
+#define BP_DIGCTL_CTRL_USE_SERIAL_JTAG                      6
+#define BM_DIGCTL_CTRL_USE_SERIAL_JTAG                      0x40
+#define BV_DIGCTL_CTRL_USE_SERIAL_JTAG__OLD_JTAG            0x0
+#define BV_DIGCTL_CTRL_USE_SERIAL_JTAG__SERIAL_JTAG         0x1
+#define BF_DIGCTL_CTRL_USE_SERIAL_JTAG(v)                   (((v) & 0x1) << 6)
+#define BFM_DIGCTL_CTRL_USE_SERIAL_JTAG(v)                  BM_DIGCTL_CTRL_USE_SERIAL_JTAG
+#define BF_DIGCTL_CTRL_USE_SERIAL_JTAG_V(e)                 BF_DIGCTL_CTRL_USE_SERIAL_JTAG(BV_DIGCTL_CTRL_USE_SERIAL_JTAG__##e)
+#define BFM_DIGCTL_CTRL_USE_SERIAL_JTAG_V(v)                BM_DIGCTL_CTRL_USE_SERIAL_JTAG
+#define BP_DIGCTL_CTRL_TRAP_IN_RANGE                        5
+#define BM_DIGCTL_CTRL_TRAP_IN_RANGE                        0x20
+#define BF_DIGCTL_CTRL_TRAP_IN_RANGE(v)                     (((v) & 0x1) << 5)
+#define BFM_DIGCTL_CTRL_TRAP_IN_RANGE(v)                    BM_DIGCTL_CTRL_TRAP_IN_RANGE
+#define BF_DIGCTL_CTRL_TRAP_IN_RANGE_V(e)                   BF_DIGCTL_CTRL_TRAP_IN_RANGE(BV_DIGCTL_CTRL_TRAP_IN_RANGE__##e)
+#define BFM_DIGCTL_CTRL_TRAP_IN_RANGE_V(v)                  BM_DIGCTL_CTRL_TRAP_IN_RANGE
+#define BP_DIGCTL_CTRL_TRAP_ENABLE                          4
+#define BM_DIGCTL_CTRL_TRAP_ENABLE                          0x10
+#define BF_DIGCTL_CTRL_TRAP_ENABLE(v)                       (((v) & 0x1) << 4)
+#define BFM_DIGCTL_CTRL_TRAP_ENABLE(v)                      BM_DIGCTL_CTRL_TRAP_ENABLE
+#define BF_DIGCTL_CTRL_TRAP_ENABLE_V(e)                     BF_DIGCTL_CTRL_TRAP_ENABLE(BV_DIGCTL_CTRL_TRAP_ENABLE__##e)
+#define BFM_DIGCTL_CTRL_TRAP_ENABLE_V(v)                    BM_DIGCTL_CTRL_TRAP_ENABLE
+#define BP_DIGCTL_CTRL_DEBUG_DISABLE                        3
+#define BM_DIGCTL_CTRL_DEBUG_DISABLE                        0x8
+#define BF_DIGCTL_CTRL_DEBUG_DISABLE(v)                     (((v) & 0x1) << 3)
+#define BFM_DIGCTL_CTRL_DEBUG_DISABLE(v)                    BM_DIGCTL_CTRL_DEBUG_DISABLE
+#define BF_DIGCTL_CTRL_DEBUG_DISABLE_V(e)                   BF_DIGCTL_CTRL_DEBUG_DISABLE(BV_DIGCTL_CTRL_DEBUG_DISABLE__##e)
+#define BFM_DIGCTL_CTRL_DEBUG_DISABLE_V(v)                  BM_DIGCTL_CTRL_DEBUG_DISABLE
+#define BP_DIGCTL_CTRL_USB_CLKGATE                          2
+#define BM_DIGCTL_CTRL_USB_CLKGATE                          0x4
+#define BV_DIGCTL_CTRL_USB_CLKGATE__RUN                     0x0
+#define BV_DIGCTL_CTRL_USB_CLKGATE__NO_CLKS                 0x1
+#define BF_DIGCTL_CTRL_USB_CLKGATE(v)                       (((v) & 0x1) << 2)
+#define BFM_DIGCTL_CTRL_USB_CLKGATE(v)                      BM_DIGCTL_CTRL_USB_CLKGATE
+#define BF_DIGCTL_CTRL_USB_CLKGATE_V(e)                     BF_DIGCTL_CTRL_USB_CLKGATE(BV_DIGCTL_CTRL_USB_CLKGATE__##e)
+#define BFM_DIGCTL_CTRL_USB_CLKGATE_V(v)                    BM_DIGCTL_CTRL_USB_CLKGATE
+#define BP_DIGCTL_CTRL_JTAG_SHIELD                          1
+#define BM_DIGCTL_CTRL_JTAG_SHIELD                          0x2
+#define BV_DIGCTL_CTRL_JTAG_SHIELD__NORMAL                  0x0
+#define BV_DIGCTL_CTRL_JTAG_SHIELD__SHIELDS_UP              0x1
+#define BF_DIGCTL_CTRL_JTAG_SHIELD(v)                       (((v) & 0x1) << 1)
+#define BFM_DIGCTL_CTRL_JTAG_SHIELD(v)                      BM_DIGCTL_CTRL_JTAG_SHIELD
+#define BF_DIGCTL_CTRL_JTAG_SHIELD_V(e)                     BF_DIGCTL_CTRL_JTAG_SHIELD(BV_DIGCTL_CTRL_JTAG_SHIELD__##e)
+#define BFM_DIGCTL_CTRL_JTAG_SHIELD_V(v)                    BM_DIGCTL_CTRL_JTAG_SHIELD
+#define BP_DIGCTL_CTRL_LATCH_ENTROPY                        0
+#define BM_DIGCTL_CTRL_LATCH_ENTROPY                        0x1
+#define BF_DIGCTL_CTRL_LATCH_ENTROPY(v)                     (((v) & 0x1) << 0)
+#define BFM_DIGCTL_CTRL_LATCH_ENTROPY(v)                    BM_DIGCTL_CTRL_LATCH_ENTROPY
+#define BF_DIGCTL_CTRL_LATCH_ENTROPY_V(e)                   BF_DIGCTL_CTRL_LATCH_ENTROPY(BV_DIGCTL_CTRL_LATCH_ENTROPY__##e)
+#define BFM_DIGCTL_CTRL_LATCH_ENTROPY_V(v)                  BM_DIGCTL_CTRL_LATCH_ENTROPY
+
+#define HW_DIGCTL_STATUS                            HW(DIGCTL_STATUS)
+#define HWA_DIGCTL_STATUS                           (0x8001c000 + 0x10)
+#define HWT_DIGCTL_STATUS                           HWIO_32_RW
+#define HWN_DIGCTL_STATUS                           DIGCTL_STATUS
+#define HWI_DIGCTL_STATUS                           
+#define BP_DIGCTL_STATUS_USB_HS_PRESENT             31
+#define BM_DIGCTL_STATUS_USB_HS_PRESENT             0x80000000
+#define BF_DIGCTL_STATUS_USB_HS_PRESENT(v)          (((v) & 0x1) << 31)
+#define BFM_DIGCTL_STATUS_USB_HS_PRESENT(v)         BM_DIGCTL_STATUS_USB_HS_PRESENT
+#define BF_DIGCTL_STATUS_USB_HS_PRESENT_V(e)        BF_DIGCTL_STATUS_USB_HS_PRESENT(BV_DIGCTL_STATUS_USB_HS_PRESENT__##e)
+#define BFM_DIGCTL_STATUS_USB_HS_PRESENT_V(v)       BM_DIGCTL_STATUS_USB_HS_PRESENT
+#define BP_DIGCTL_STATUS_USB_OTG_PRESENT            30
+#define BM_DIGCTL_STATUS_USB_OTG_PRESENT            0x40000000
+#define BF_DIGCTL_STATUS_USB_OTG_PRESENT(v)         (((v) & 0x1) << 30)
+#define BFM_DIGCTL_STATUS_USB_OTG_PRESENT(v)        BM_DIGCTL_STATUS_USB_OTG_PRESENT
+#define BF_DIGCTL_STATUS_USB_OTG_PRESENT_V(e)       BF_DIGCTL_STATUS_USB_OTG_PRESENT(BV_DIGCTL_STATUS_USB_OTG_PRESENT__##e)
+#define BFM_DIGCTL_STATUS_USB_OTG_PRESENT_V(v)      BM_DIGCTL_STATUS_USB_OTG_PRESENT
+#define BP_DIGCTL_STATUS_USB_HOST_PRESENT           29
+#define BM_DIGCTL_STATUS_USB_HOST_PRESENT           0x20000000
+#define BF_DIGCTL_STATUS_USB_HOST_PRESENT(v)        (((v) & 0x1) << 29)
+#define BFM_DIGCTL_STATUS_USB_HOST_PRESENT(v)       BM_DIGCTL_STATUS_USB_HOST_PRESENT
+#define BF_DIGCTL_STATUS_USB_HOST_PRESENT_V(e)      BF_DIGCTL_STATUS_USB_HOST_PRESENT(BV_DIGCTL_STATUS_USB_HOST_PRESENT__##e)
+#define BFM_DIGCTL_STATUS_USB_HOST_PRESENT_V(v)     BM_DIGCTL_STATUS_USB_HOST_PRESENT
+#define BP_DIGCTL_STATUS_USB_DEVICE_PRESENT         28
+#define BM_DIGCTL_STATUS_USB_DEVICE_PRESENT         0x10000000
+#define BF_DIGCTL_STATUS_USB_DEVICE_PRESENT(v)      (((v) & 0x1) << 28)
+#define BFM_DIGCTL_STATUS_USB_DEVICE_PRESENT(v)     BM_DIGCTL_STATUS_USB_DEVICE_PRESENT
+#define BF_DIGCTL_STATUS_USB_DEVICE_PRESENT_V(e)    BF_DIGCTL_STATUS_USB_DEVICE_PRESENT(BV_DIGCTL_STATUS_USB_DEVICE_PRESENT__##e)
+#define BFM_DIGCTL_STATUS_USB_DEVICE_PRESENT_V(v)   BM_DIGCTL_STATUS_USB_DEVICE_PRESENT
+#define BP_DIGCTL_STATUS_DCP_BIST_FAIL              10
+#define BM_DIGCTL_STATUS_DCP_BIST_FAIL              0x400
+#define BF_DIGCTL_STATUS_DCP_BIST_FAIL(v)           (((v) & 0x1) << 10)
+#define BFM_DIGCTL_STATUS_DCP_BIST_FAIL(v)          BM_DIGCTL_STATUS_DCP_BIST_FAIL
+#define BF_DIGCTL_STATUS_DCP_BIST_FAIL_V(e)         BF_DIGCTL_STATUS_DCP_BIST_FAIL(BV_DIGCTL_STATUS_DCP_BIST_FAIL__##e)
+#define BFM_DIGCTL_STATUS_DCP_BIST_FAIL_V(v)        BM_DIGCTL_STATUS_DCP_BIST_FAIL
+#define BP_DIGCTL_STATUS_DCP_BIST_PASS              9
+#define BM_DIGCTL_STATUS_DCP_BIST_PASS              0x200
+#define BF_DIGCTL_STATUS_DCP_BIST_PASS(v)           (((v) & 0x1) << 9)
+#define BFM_DIGCTL_STATUS_DCP_BIST_PASS(v)          BM_DIGCTL_STATUS_DCP_BIST_PASS
+#define BF_DIGCTL_STATUS_DCP_BIST_PASS_V(e)         BF_DIGCTL_STATUS_DCP_BIST_PASS(BV_DIGCTL_STATUS_DCP_BIST_PASS__##e)
+#define BFM_DIGCTL_STATUS_DCP_BIST_PASS_V(v)        BM_DIGCTL_STATUS_DCP_BIST_PASS
+#define BP_DIGCTL_STATUS_DCP_BIST_DONE              8
+#define BM_DIGCTL_STATUS_DCP_BIST_DONE              0x100
+#define BF_DIGCTL_STATUS_DCP_BIST_DONE(v)           (((v) & 0x1) << 8)
+#define BFM_DIGCTL_STATUS_DCP_BIST_DONE(v)          BM_DIGCTL_STATUS_DCP_BIST_DONE
+#define BF_DIGCTL_STATUS_DCP_BIST_DONE_V(e)         BF_DIGCTL_STATUS_DCP_BIST_DONE(BV_DIGCTL_STATUS_DCP_BIST_DONE__##e)
+#define BFM_DIGCTL_STATUS_DCP_BIST_DONE_V(v)        BM_DIGCTL_STATUS_DCP_BIST_DONE
+#define BP_DIGCTL_STATUS_JTAG_IN_USE                4
+#define BM_DIGCTL_STATUS_JTAG_IN_USE                0x10
+#define BF_DIGCTL_STATUS_JTAG_IN_USE(v)             (((v) & 0x1) << 4)
+#define BFM_DIGCTL_STATUS_JTAG_IN_USE(v)            BM_DIGCTL_STATUS_JTAG_IN_USE
+#define BF_DIGCTL_STATUS_JTAG_IN_USE_V(e)           BF_DIGCTL_STATUS_JTAG_IN_USE(BV_DIGCTL_STATUS_JTAG_IN_USE__##e)
+#define BFM_DIGCTL_STATUS_JTAG_IN_USE_V(v)          BM_DIGCTL_STATUS_JTAG_IN_USE
+#define BP_DIGCTL_STATUS_PACKAGE_TYPE               1
+#define BM_DIGCTL_STATUS_PACKAGE_TYPE               0xe
+#define BF_DIGCTL_STATUS_PACKAGE_TYPE(v)            (((v) & 0x7) << 1)
+#define BFM_DIGCTL_STATUS_PACKAGE_TYPE(v)           BM_DIGCTL_STATUS_PACKAGE_TYPE
+#define BF_DIGCTL_STATUS_PACKAGE_TYPE_V(e)          BF_DIGCTL_STATUS_PACKAGE_TYPE(BV_DIGCTL_STATUS_PACKAGE_TYPE__##e)
+#define BFM_DIGCTL_STATUS_PACKAGE_TYPE_V(v)         BM_DIGCTL_STATUS_PACKAGE_TYPE
+#define BP_DIGCTL_STATUS_WRITTEN                    0
+#define BM_DIGCTL_STATUS_WRITTEN                    0x1
+#define BF_DIGCTL_STATUS_WRITTEN(v)                 (((v) & 0x1) << 0)
+#define BFM_DIGCTL_STATUS_WRITTEN(v)                BM_DIGCTL_STATUS_WRITTEN
+#define BF_DIGCTL_STATUS_WRITTEN_V(e)               BF_DIGCTL_STATUS_WRITTEN(BV_DIGCTL_STATUS_WRITTEN__##e)
+#define BFM_DIGCTL_STATUS_WRITTEN_V(v)              BM_DIGCTL_STATUS_WRITTEN
+
+#define HW_DIGCTL_HCLKCOUNT             HW(DIGCTL_HCLKCOUNT)
+#define HWA_DIGCTL_HCLKCOUNT            (0x8001c000 + 0x20)
+#define HWT_DIGCTL_HCLKCOUNT            HWIO_32_RW
+#define HWN_DIGCTL_HCLKCOUNT            DIGCTL_HCLKCOUNT
+#define HWI_DIGCTL_HCLKCOUNT            
+#define BP_DIGCTL_HCLKCOUNT_COUNT       0
+#define BM_DIGCTL_HCLKCOUNT_COUNT       0xffffffff
+#define BF_DIGCTL_HCLKCOUNT_COUNT(v)    (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_HCLKCOUNT_COUNT(v)   BM_DIGCTL_HCLKCOUNT_COUNT
+#define BF_DIGCTL_HCLKCOUNT_COUNT_V(e)  BF_DIGCTL_HCLKCOUNT_COUNT(BV_DIGCTL_HCLKCOUNT_COUNT__##e)
+#define BFM_DIGCTL_HCLKCOUNT_COUNT_V(v) BM_DIGCTL_HCLKCOUNT_COUNT
+
+#define HW_DIGCTL_RAMCTRL                       HW(DIGCTL_RAMCTRL)
+#define HWA_DIGCTL_RAMCTRL                      (0x8001c000 + 0x30)
+#define HWT_DIGCTL_RAMCTRL                      HWIO_32_RW
+#define HWN_DIGCTL_RAMCTRL                      DIGCTL_RAMCTRL
+#define HWI_DIGCTL_RAMCTRL                      
+#define HW_DIGCTL_RAMCTRL_SET                   HW(DIGCTL_RAMCTRL_SET)
+#define HWA_DIGCTL_RAMCTRL_SET                  (HWA_DIGCTL_RAMCTRL + 0x4)
+#define HWT_DIGCTL_RAMCTRL_SET                  HWIO_32_WO
+#define HWN_DIGCTL_RAMCTRL_SET                  DIGCTL_RAMCTRL
+#define HWI_DIGCTL_RAMCTRL_SET                  
+#define HW_DIGCTL_RAMCTRL_CLR                   HW(DIGCTL_RAMCTRL_CLR)
+#define HWA_DIGCTL_RAMCTRL_CLR                  (HWA_DIGCTL_RAMCTRL + 0x8)
+#define HWT_DIGCTL_RAMCTRL_CLR                  HWIO_32_WO
+#define HWN_DIGCTL_RAMCTRL_CLR                  DIGCTL_RAMCTRL
+#define HWI_DIGCTL_RAMCTRL_CLR                  
+#define HW_DIGCTL_RAMCTRL_TOG                   HW(DIGCTL_RAMCTRL_TOG)
+#define HWA_DIGCTL_RAMCTRL_TOG                  (HWA_DIGCTL_RAMCTRL + 0xc)
+#define HWT_DIGCTL_RAMCTRL_TOG                  HWIO_32_WO
+#define HWN_DIGCTL_RAMCTRL_TOG                  DIGCTL_RAMCTRL
+#define HWI_DIGCTL_RAMCTRL_TOG                  
+#define BP_DIGCTL_RAMCTRL_SPEED_SELECT          8
+#define BM_DIGCTL_RAMCTRL_SPEED_SELECT          0xf00
+#define BF_DIGCTL_RAMCTRL_SPEED_SELECT(v)       (((v) & 0xf) << 8)
+#define BFM_DIGCTL_RAMCTRL_SPEED_SELECT(v)      BM_DIGCTL_RAMCTRL_SPEED_SELECT
+#define BF_DIGCTL_RAMCTRL_SPEED_SELECT_V(e)     BF_DIGCTL_RAMCTRL_SPEED_SELECT(BV_DIGCTL_RAMCTRL_SPEED_SELECT__##e)
+#define BFM_DIGCTL_RAMCTRL_SPEED_SELECT_V(v)    BM_DIGCTL_RAMCTRL_SPEED_SELECT
+#define BP_DIGCTL_RAMCTRL_RAM_REPAIR_EN         0
+#define BM_DIGCTL_RAMCTRL_RAM_REPAIR_EN         0x1
+#define BF_DIGCTL_RAMCTRL_RAM_REPAIR_EN(v)      (((v) & 0x1) << 0)
+#define BFM_DIGCTL_RAMCTRL_RAM_REPAIR_EN(v)     BM_DIGCTL_RAMCTRL_RAM_REPAIR_EN
+#define BF_DIGCTL_RAMCTRL_RAM_REPAIR_EN_V(e)    BF_DIGCTL_RAMCTRL_RAM_REPAIR_EN(BV_DIGCTL_RAMCTRL_RAM_REPAIR_EN__##e)
+#define BFM_DIGCTL_RAMCTRL_RAM_REPAIR_EN_V(v)   BM_DIGCTL_RAMCTRL_RAM_REPAIR_EN
+
+#define HW_DIGCTL_RAMREPAIR             HW(DIGCTL_RAMREPAIR)
+#define HWA_DIGCTL_RAMREPAIR            (0x8001c000 + 0x40)
+#define HWT_DIGCTL_RAMREPAIR            HWIO_32_RW
+#define HWN_DIGCTL_RAMREPAIR            DIGCTL_RAMREPAIR
+#define HWI_DIGCTL_RAMREPAIR            
+#define HW_DIGCTL_RAMREPAIR_SET         HW(DIGCTL_RAMREPAIR_SET)
+#define HWA_DIGCTL_RAMREPAIR_SET        (HWA_DIGCTL_RAMREPAIR + 0x4)
+#define HWT_DIGCTL_RAMREPAIR_SET        HWIO_32_WO
+#define HWN_DIGCTL_RAMREPAIR_SET        DIGCTL_RAMREPAIR
+#define HWI_DIGCTL_RAMREPAIR_SET        
+#define HW_DIGCTL_RAMREPAIR_CLR         HW(DIGCTL_RAMREPAIR_CLR)
+#define HWA_DIGCTL_RAMREPAIR_CLR        (HWA_DIGCTL_RAMREPAIR + 0x8)
+#define HWT_DIGCTL_RAMREPAIR_CLR        HWIO_32_WO
+#define HWN_DIGCTL_RAMREPAIR_CLR        DIGCTL_RAMREPAIR
+#define HWI_DIGCTL_RAMREPAIR_CLR        
+#define HW_DIGCTL_RAMREPAIR_TOG         HW(DIGCTL_RAMREPAIR_TOG)
+#define HWA_DIGCTL_RAMREPAIR_TOG        (HWA_DIGCTL_RAMREPAIR + 0xc)
+#define HWT_DIGCTL_RAMREPAIR_TOG        HWIO_32_WO
+#define HWN_DIGCTL_RAMREPAIR_TOG        DIGCTL_RAMREPAIR
+#define HWI_DIGCTL_RAMREPAIR_TOG        
+#define BP_DIGCTL_RAMREPAIR_ADDR        0
+#define BM_DIGCTL_RAMREPAIR_ADDR        0xffff
+#define BF_DIGCTL_RAMREPAIR_ADDR(v)     (((v) & 0xffff) << 0)
+#define BFM_DIGCTL_RAMREPAIR_ADDR(v)    BM_DIGCTL_RAMREPAIR_ADDR
+#define BF_DIGCTL_RAMREPAIR_ADDR_V(e)   BF_DIGCTL_RAMREPAIR_ADDR(BV_DIGCTL_RAMREPAIR_ADDR__##e)
+#define BFM_DIGCTL_RAMREPAIR_ADDR_V(v)  BM_DIGCTL_RAMREPAIR_ADDR
+
+#define HW_DIGCTL_ROMCTRL                   HW(DIGCTL_ROMCTRL)
+#define HWA_DIGCTL_ROMCTRL                  (0x8001c000 + 0x50)
+#define HWT_DIGCTL_ROMCTRL                  HWIO_32_RW
+#define HWN_DIGCTL_ROMCTRL                  DIGCTL_ROMCTRL
+#define HWI_DIGCTL_ROMCTRL                  
+#define HW_DIGCTL_ROMCTRL_SET               HW(DIGCTL_ROMCTRL_SET)
+#define HWA_DIGCTL_ROMCTRL_SET              (HWA_DIGCTL_ROMCTRL + 0x4)
+#define HWT_DIGCTL_ROMCTRL_SET              HWIO_32_WO
+#define HWN_DIGCTL_ROMCTRL_SET              DIGCTL_ROMCTRL
+#define HWI_DIGCTL_ROMCTRL_SET              
+#define HW_DIGCTL_ROMCTRL_CLR               HW(DIGCTL_ROMCTRL_CLR)
+#define HWA_DIGCTL_ROMCTRL_CLR              (HWA_DIGCTL_ROMCTRL + 0x8)
+#define HWT_DIGCTL_ROMCTRL_CLR              HWIO_32_WO
+#define HWN_DIGCTL_ROMCTRL_CLR              DIGCTL_ROMCTRL
+#define HWI_DIGCTL_ROMCTRL_CLR              
+#define HW_DIGCTL_ROMCTRL_TOG               HW(DIGCTL_ROMCTRL_TOG)
+#define HWA_DIGCTL_ROMCTRL_TOG              (HWA_DIGCTL_ROMCTRL + 0xc)
+#define HWT_DIGCTL_ROMCTRL_TOG              HWIO_32_WO
+#define HWN_DIGCTL_ROMCTRL_TOG              DIGCTL_ROMCTRL
+#define HWI_DIGCTL_ROMCTRL_TOG              
+#define BP_DIGCTL_ROMCTRL_RD_MARGIN         0
+#define BM_DIGCTL_ROMCTRL_RD_MARGIN         0xf
+#define BF_DIGCTL_ROMCTRL_RD_MARGIN(v)      (((v) & 0xf) << 0)
+#define BFM_DIGCTL_ROMCTRL_RD_MARGIN(v)     BM_DIGCTL_ROMCTRL_RD_MARGIN
+#define BF_DIGCTL_ROMCTRL_RD_MARGIN_V(e)    BF_DIGCTL_ROMCTRL_RD_MARGIN(BV_DIGCTL_ROMCTRL_RD_MARGIN__##e)
+#define BFM_DIGCTL_ROMCTRL_RD_MARGIN_V(v)   BM_DIGCTL_ROMCTRL_RD_MARGIN
+
+#define HW_DIGCTL_WRITEONCE             HW(DIGCTL_WRITEONCE)
+#define HWA_DIGCTL_WRITEONCE            (0x8001c000 + 0x60)
+#define HWT_DIGCTL_WRITEONCE            HWIO_32_RW
+#define HWN_DIGCTL_WRITEONCE            DIGCTL_WRITEONCE
+#define HWI_DIGCTL_WRITEONCE            
+#define BP_DIGCTL_WRITEONCE_BITS        0
+#define BM_DIGCTL_WRITEONCE_BITS        0xffffffff
+#define BF_DIGCTL_WRITEONCE_BITS(v)     (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_WRITEONCE_BITS(v)    BM_DIGCTL_WRITEONCE_BITS
+#define BF_DIGCTL_WRITEONCE_BITS_V(e)   BF_DIGCTL_WRITEONCE_BITS(BV_DIGCTL_WRITEONCE_BITS__##e)
+#define BFM_DIGCTL_WRITEONCE_BITS_V(v)  BM_DIGCTL_WRITEONCE_BITS
+
+#define HW_DIGCTL_ENTROPY               HW(DIGCTL_ENTROPY)
+#define HWA_DIGCTL_ENTROPY              (0x8001c000 + 0x90)
+#define HWT_DIGCTL_ENTROPY              HWIO_32_RW
+#define HWN_DIGCTL_ENTROPY              DIGCTL_ENTROPY
+#define HWI_DIGCTL_ENTROPY              
+#define BP_DIGCTL_ENTROPY_VALUE         0
+#define BM_DIGCTL_ENTROPY_VALUE         0xffffffff
+#define BF_DIGCTL_ENTROPY_VALUE(v)      (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_ENTROPY_VALUE(v)     BM_DIGCTL_ENTROPY_VALUE
+#define BF_DIGCTL_ENTROPY_VALUE_V(e)    BF_DIGCTL_ENTROPY_VALUE(BV_DIGCTL_ENTROPY_VALUE__##e)
+#define BFM_DIGCTL_ENTROPY_VALUE_V(v)   BM_DIGCTL_ENTROPY_VALUE
+
+#define HW_DIGCTL_ENTROPY_LATCHED               HW(DIGCTL_ENTROPY_LATCHED)
+#define HWA_DIGCTL_ENTROPY_LATCHED              (0x8001c000 + 0xa0)
+#define HWT_DIGCTL_ENTROPY_LATCHED              HWIO_32_RW
+#define HWN_DIGCTL_ENTROPY_LATCHED              DIGCTL_ENTROPY_LATCHED
+#define HWI_DIGCTL_ENTROPY_LATCHED              
+#define BP_DIGCTL_ENTROPY_LATCHED_VALUE         0
+#define BM_DIGCTL_ENTROPY_LATCHED_VALUE         0xffffffff
+#define BF_DIGCTL_ENTROPY_LATCHED_VALUE(v)      (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_ENTROPY_LATCHED_VALUE(v)     BM_DIGCTL_ENTROPY_LATCHED_VALUE
+#define BF_DIGCTL_ENTROPY_LATCHED_VALUE_V(e)    BF_DIGCTL_ENTROPY_LATCHED_VALUE(BV_DIGCTL_ENTROPY_LATCHED_VALUE__##e)
+#define BFM_DIGCTL_ENTROPY_LATCHED_VALUE_V(v)   BM_DIGCTL_ENTROPY_LATCHED_VALUE
+
+#define HW_DIGCTL_SJTAGDBG                          HW(DIGCTL_SJTAGDBG)
+#define HWA_DIGCTL_SJTAGDBG                         (0x8001c000 + 0xb0)
+#define HWT_DIGCTL_SJTAGDBG                         HWIO_32_RW
+#define HWN_DIGCTL_SJTAGDBG                         DIGCTL_SJTAGDBG
+#define HWI_DIGCTL_SJTAGDBG                         
+#define HW_DIGCTL_SJTAGDBG_SET                      HW(DIGCTL_SJTAGDBG_SET)
+#define HWA_DIGCTL_SJTAGDBG_SET                     (HWA_DIGCTL_SJTAGDBG + 0x4)
+#define HWT_DIGCTL_SJTAGDBG_SET                     HWIO_32_WO
+#define HWN_DIGCTL_SJTAGDBG_SET                     DIGCTL_SJTAGDBG
+#define HWI_DIGCTL_SJTAGDBG_SET                     
+#define HW_DIGCTL_SJTAGDBG_CLR                      HW(DIGCTL_SJTAGDBG_CLR)
+#define HWA_DIGCTL_SJTAGDBG_CLR                     (HWA_DIGCTL_SJTAGDBG + 0x8)
+#define HWT_DIGCTL_SJTAGDBG_CLR                     HWIO_32_WO
+#define HWN_DIGCTL_SJTAGDBG_CLR                     DIGCTL_SJTAGDBG
+#define HWI_DIGCTL_SJTAGDBG_CLR                     
+#define HW_DIGCTL_SJTAGDBG_TOG                      HW(DIGCTL_SJTAGDBG_TOG)
+#define HWA_DIGCTL_SJTAGDBG_TOG                     (HWA_DIGCTL_SJTAGDBG + 0xc)
+#define HWT_DIGCTL_SJTAGDBG_TOG                     HWIO_32_WO
+#define HWN_DIGCTL_SJTAGDBG_TOG                     DIGCTL_SJTAGDBG
+#define HWI_DIGCTL_SJTAGDBG_TOG                     
+#define BP_DIGCTL_SJTAGDBG_SJTAG_STATE              16
+#define BM_DIGCTL_SJTAGDBG_SJTAG_STATE              0x7ff0000
+#define BF_DIGCTL_SJTAGDBG_SJTAG_STATE(v)           (((v) & 0x7ff) << 16)
+#define BFM_DIGCTL_SJTAGDBG_SJTAG_STATE(v)          BM_DIGCTL_SJTAGDBG_SJTAG_STATE
+#define BF_DIGCTL_SJTAGDBG_SJTAG_STATE_V(e)         BF_DIGCTL_SJTAGDBG_SJTAG_STATE(BV_DIGCTL_SJTAGDBG_SJTAG_STATE__##e)
+#define BFM_DIGCTL_SJTAGDBG_SJTAG_STATE_V(v)        BM_DIGCTL_SJTAGDBG_SJTAG_STATE
+#define BP_DIGCTL_SJTAGDBG_SJTAG_TDO                10
+#define BM_DIGCTL_SJTAGDBG_SJTAG_TDO                0x400
+#define BF_DIGCTL_SJTAGDBG_SJTAG_TDO(v)             (((v) & 0x1) << 10)
+#define BFM_DIGCTL_SJTAGDBG_SJTAG_TDO(v)            BM_DIGCTL_SJTAGDBG_SJTAG_TDO
+#define BF_DIGCTL_SJTAGDBG_SJTAG_TDO_V(e)           BF_DIGCTL_SJTAGDBG_SJTAG_TDO(BV_DIGCTL_SJTAGDBG_SJTAG_TDO__##e)
+#define BFM_DIGCTL_SJTAGDBG_SJTAG_TDO_V(v)          BM_DIGCTL_SJTAGDBG_SJTAG_TDO
+#define BP_DIGCTL_SJTAGDBG_SJTAG_TDI                9
+#define BM_DIGCTL_SJTAGDBG_SJTAG_TDI                0x200
+#define BF_DIGCTL_SJTAGDBG_SJTAG_TDI(v)             (((v) & 0x1) << 9)
+#define BFM_DIGCTL_SJTAGDBG_SJTAG_TDI(v)            BM_DIGCTL_SJTAGDBG_SJTAG_TDI
+#define BF_DIGCTL_SJTAGDBG_SJTAG_TDI_V(e)           BF_DIGCTL_SJTAGDBG_SJTAG_TDI(BV_DIGCTL_SJTAGDBG_SJTAG_TDI__##e)
+#define BFM_DIGCTL_SJTAGDBG_SJTAG_TDI_V(v)          BM_DIGCTL_SJTAGDBG_SJTAG_TDI
+#define BP_DIGCTL_SJTAGDBG_SJTAG_MODE               8
+#define BM_DIGCTL_SJTAGDBG_SJTAG_MODE               0x100
+#define BF_DIGCTL_SJTAGDBG_SJTAG_MODE(v)            (((v) & 0x1) << 8)
+#define BFM_DIGCTL_SJTAGDBG_SJTAG_MODE(v)           BM_DIGCTL_SJTAGDBG_SJTAG_MODE
+#define BF_DIGCTL_SJTAGDBG_SJTAG_MODE_V(e)          BF_DIGCTL_SJTAGDBG_SJTAG_MODE(BV_DIGCTL_SJTAGDBG_SJTAG_MODE__##e)
+#define BFM_DIGCTL_SJTAGDBG_SJTAG_MODE_V(v)         BM_DIGCTL_SJTAGDBG_SJTAG_MODE
+#define BP_DIGCTL_SJTAGDBG_DELAYED_ACTIVE           4
+#define BM_DIGCTL_SJTAGDBG_DELAYED_ACTIVE           0xf0
+#define BF_DIGCTL_SJTAGDBG_DELAYED_ACTIVE(v)        (((v) & 0xf) << 4)
+#define BFM_DIGCTL_SJTAGDBG_DELAYED_ACTIVE(v)       BM_DIGCTL_SJTAGDBG_DELAYED_ACTIVE
+#define BF_DIGCTL_SJTAGDBG_DELAYED_ACTIVE_V(e)      BF_DIGCTL_SJTAGDBG_DELAYED_ACTIVE(BV_DIGCTL_SJTAGDBG_DELAYED_ACTIVE__##e)
+#define BFM_DIGCTL_SJTAGDBG_DELAYED_ACTIVE_V(v)     BM_DIGCTL_SJTAGDBG_DELAYED_ACTIVE
+#define BP_DIGCTL_SJTAGDBG_ACTIVE                   3
+#define BM_DIGCTL_SJTAGDBG_ACTIVE                   0x8
+#define BF_DIGCTL_SJTAGDBG_ACTIVE(v)                (((v) & 0x1) << 3)
+#define BFM_DIGCTL_SJTAGDBG_ACTIVE(v)               BM_DIGCTL_SJTAGDBG_ACTIVE
+#define BF_DIGCTL_SJTAGDBG_ACTIVE_V(e)              BF_DIGCTL_SJTAGDBG_ACTIVE(BV_DIGCTL_SJTAGDBG_ACTIVE__##e)
+#define BFM_DIGCTL_SJTAGDBG_ACTIVE_V(v)             BM_DIGCTL_SJTAGDBG_ACTIVE
+#define BP_DIGCTL_SJTAGDBG_SJTAG_PIN_STATE          2
+#define BM_DIGCTL_SJTAGDBG_SJTAG_PIN_STATE          0x4
+#define BF_DIGCTL_SJTAGDBG_SJTAG_PIN_STATE(v)       (((v) & 0x1) << 2)
+#define BFM_DIGCTL_SJTAGDBG_SJTAG_PIN_STATE(v)      BM_DIGCTL_SJTAGDBG_SJTAG_PIN_STATE
+#define BF_DIGCTL_SJTAGDBG_SJTAG_PIN_STATE_V(e)     BF_DIGCTL_SJTAGDBG_SJTAG_PIN_STATE(BV_DIGCTL_SJTAGDBG_SJTAG_PIN_STATE__##e)
+#define BFM_DIGCTL_SJTAGDBG_SJTAG_PIN_STATE_V(v)    BM_DIGCTL_SJTAGDBG_SJTAG_PIN_STATE
+#define BP_DIGCTL_SJTAGDBG_SJTAG_DEBUG_DATA         1
+#define BM_DIGCTL_SJTAGDBG_SJTAG_DEBUG_DATA         0x2
+#define BF_DIGCTL_SJTAGDBG_SJTAG_DEBUG_DATA(v)      (((v) & 0x1) << 1)
+#define BFM_DIGCTL_SJTAGDBG_SJTAG_DEBUG_DATA(v)     BM_DIGCTL_SJTAGDBG_SJTAG_DEBUG_DATA
+#define BF_DIGCTL_SJTAGDBG_SJTAG_DEBUG_DATA_V(e)    BF_DIGCTL_SJTAGDBG_SJTAG_DEBUG_DATA(BV_DIGCTL_SJTAGDBG_SJTAG_DEBUG_DATA__##e)
+#define BFM_DIGCTL_SJTAGDBG_SJTAG_DEBUG_DATA_V(v)   BM_DIGCTL_SJTAGDBG_SJTAG_DEBUG_DATA
+#define BP_DIGCTL_SJTAGDBG_SJTAG_DEBUG_OE           0
+#define BM_DIGCTL_SJTAGDBG_SJTAG_DEBUG_OE           0x1
+#define BF_DIGCTL_SJTAGDBG_SJTAG_DEBUG_OE(v)        (((v) & 0x1) << 0)
+#define BFM_DIGCTL_SJTAGDBG_SJTAG_DEBUG_OE(v)       BM_DIGCTL_SJTAGDBG_SJTAG_DEBUG_OE
+#define BF_DIGCTL_SJTAGDBG_SJTAG_DEBUG_OE_V(e)      BF_DIGCTL_SJTAGDBG_SJTAG_DEBUG_OE(BV_DIGCTL_SJTAGDBG_SJTAG_DEBUG_OE__##e)
+#define BFM_DIGCTL_SJTAGDBG_SJTAG_DEBUG_OE_V(v)     BM_DIGCTL_SJTAGDBG_SJTAG_DEBUG_OE
+
+#define HW_DIGCTL_MICROSECONDS              HW(DIGCTL_MICROSECONDS)
+#define HWA_DIGCTL_MICROSECONDS             (0x8001c000 + 0xc0)
+#define HWT_DIGCTL_MICROSECONDS             HWIO_32_RW
+#define HWN_DIGCTL_MICROSECONDS             DIGCTL_MICROSECONDS
+#define HWI_DIGCTL_MICROSECONDS             
+#define HW_DIGCTL_MICROSECONDS_SET          HW(DIGCTL_MICROSECONDS_SET)
+#define HWA_DIGCTL_MICROSECONDS_SET         (HWA_DIGCTL_MICROSECONDS + 0x4)
+#define HWT_DIGCTL_MICROSECONDS_SET         HWIO_32_WO
+#define HWN_DIGCTL_MICROSECONDS_SET         DIGCTL_MICROSECONDS
+#define HWI_DIGCTL_MICROSECONDS_SET         
+#define HW_DIGCTL_MICROSECONDS_CLR          HW(DIGCTL_MICROSECONDS_CLR)
+#define HWA_DIGCTL_MICROSECONDS_CLR         (HWA_DIGCTL_MICROSECONDS + 0x8)
+#define HWT_DIGCTL_MICROSECONDS_CLR         HWIO_32_WO
+#define HWN_DIGCTL_MICROSECONDS_CLR         DIGCTL_MICROSECONDS
+#define HWI_DIGCTL_MICROSECONDS_CLR         
+#define HW_DIGCTL_MICROSECONDS_TOG          HW(DIGCTL_MICROSECONDS_TOG)
+#define HWA_DIGCTL_MICROSECONDS_TOG         (HWA_DIGCTL_MICROSECONDS + 0xc)
+#define HWT_DIGCTL_MICROSECONDS_TOG         HWIO_32_WO
+#define HWN_DIGCTL_MICROSECONDS_TOG         DIGCTL_MICROSECONDS
+#define HWI_DIGCTL_MICROSECONDS_TOG         
+#define BP_DIGCTL_MICROSECONDS_VALUE        0
+#define BM_DIGCTL_MICROSECONDS_VALUE        0xffffffff
+#define BF_DIGCTL_MICROSECONDS_VALUE(v)     (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_MICROSECONDS_VALUE(v)    BM_DIGCTL_MICROSECONDS_VALUE
+#define BF_DIGCTL_MICROSECONDS_VALUE_V(e)   BF_DIGCTL_MICROSECONDS_VALUE(BV_DIGCTL_MICROSECONDS_VALUE__##e)
+#define BFM_DIGCTL_MICROSECONDS_VALUE_V(v)  BM_DIGCTL_MICROSECONDS_VALUE
+
+#define HW_DIGCTL_DBGRD                     HW(DIGCTL_DBGRD)
+#define HWA_DIGCTL_DBGRD                    (0x8001c000 + 0xd0)
+#define HWT_DIGCTL_DBGRD                    HWIO_32_RW
+#define HWN_DIGCTL_DBGRD                    DIGCTL_DBGRD
+#define HWI_DIGCTL_DBGRD                    
+#define BP_DIGCTL_DBGRD_COMPLEMENT          0
+#define BM_DIGCTL_DBGRD_COMPLEMENT          0xffffffff
+#define BF_DIGCTL_DBGRD_COMPLEMENT(v)       (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_DBGRD_COMPLEMENT(v)      BM_DIGCTL_DBGRD_COMPLEMENT
+#define BF_DIGCTL_DBGRD_COMPLEMENT_V(e)     BF_DIGCTL_DBGRD_COMPLEMENT(BV_DIGCTL_DBGRD_COMPLEMENT__##e)
+#define BFM_DIGCTL_DBGRD_COMPLEMENT_V(v)    BM_DIGCTL_DBGRD_COMPLEMENT
+
+#define HW_DIGCTL_DBG               HW(DIGCTL_DBG)
+#define HWA_DIGCTL_DBG              (0x8001c000 + 0xe0)
+#define HWT_DIGCTL_DBG              HWIO_32_RW
+#define HWN_DIGCTL_DBG              DIGCTL_DBG
+#define HWI_DIGCTL_DBG              
+#define BP_DIGCTL_DBG_VALUE         0
+#define BM_DIGCTL_DBG_VALUE         0xffffffff
+#define BF_DIGCTL_DBG_VALUE(v)      (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_DBG_VALUE(v)     BM_DIGCTL_DBG_VALUE
+#define BF_DIGCTL_DBG_VALUE_V(e)    BF_DIGCTL_DBG_VALUE(BV_DIGCTL_DBG_VALUE__##e)
+#define BFM_DIGCTL_DBG_VALUE_V(v)   BM_DIGCTL_DBG_VALUE
+
+#define HW_DIGCTL_OCRAM_BIST_CSR                        HW(DIGCTL_OCRAM_BIST_CSR)
+#define HWA_DIGCTL_OCRAM_BIST_CSR                       (0x8001c000 + 0xf0)
+#define HWT_DIGCTL_OCRAM_BIST_CSR                       HWIO_32_RW
+#define HWN_DIGCTL_OCRAM_BIST_CSR                       DIGCTL_OCRAM_BIST_CSR
+#define HWI_DIGCTL_OCRAM_BIST_CSR                       
+#define HW_DIGCTL_OCRAM_BIST_CSR_SET                    HW(DIGCTL_OCRAM_BIST_CSR_SET)
+#define HWA_DIGCTL_OCRAM_BIST_CSR_SET                   (HWA_DIGCTL_OCRAM_BIST_CSR + 0x4)
+#define HWT_DIGCTL_OCRAM_BIST_CSR_SET                   HWIO_32_WO
+#define HWN_DIGCTL_OCRAM_BIST_CSR_SET                   DIGCTL_OCRAM_BIST_CSR
+#define HWI_DIGCTL_OCRAM_BIST_CSR_SET                   
+#define HW_DIGCTL_OCRAM_BIST_CSR_CLR                    HW(DIGCTL_OCRAM_BIST_CSR_CLR)
+#define HWA_DIGCTL_OCRAM_BIST_CSR_CLR                   (HWA_DIGCTL_OCRAM_BIST_CSR + 0x8)
+#define HWT_DIGCTL_OCRAM_BIST_CSR_CLR                   HWIO_32_WO
+#define HWN_DIGCTL_OCRAM_BIST_CSR_CLR                   DIGCTL_OCRAM_BIST_CSR
+#define HWI_DIGCTL_OCRAM_BIST_CSR_CLR                   
+#define HW_DIGCTL_OCRAM_BIST_CSR_TOG                    HW(DIGCTL_OCRAM_BIST_CSR_TOG)
+#define HWA_DIGCTL_OCRAM_BIST_CSR_TOG                   (HWA_DIGCTL_OCRAM_BIST_CSR + 0xc)
+#define HWT_DIGCTL_OCRAM_BIST_CSR_TOG                   HWIO_32_WO
+#define HWN_DIGCTL_OCRAM_BIST_CSR_TOG                   DIGCTL_OCRAM_BIST_CSR
+#define HWI_DIGCTL_OCRAM_BIST_CSR_TOG                   
+#define BP_DIGCTL_OCRAM_BIST_CSR_BIST_DATA_CHANGE       9
+#define BM_DIGCTL_OCRAM_BIST_CSR_BIST_DATA_CHANGE       0x200
+#define BF_DIGCTL_OCRAM_BIST_CSR_BIST_DATA_CHANGE(v)    (((v) & 0x1) << 9)
+#define BFM_DIGCTL_OCRAM_BIST_CSR_BIST_DATA_CHANGE(v)   BM_DIGCTL_OCRAM_BIST_CSR_BIST_DATA_CHANGE
+#define BF_DIGCTL_OCRAM_BIST_CSR_BIST_DATA_CHANGE_V(e)  BF_DIGCTL_OCRAM_BIST_CSR_BIST_DATA_CHANGE(BV_DIGCTL_OCRAM_BIST_CSR_BIST_DATA_CHANGE__##e)
+#define BFM_DIGCTL_OCRAM_BIST_CSR_BIST_DATA_CHANGE_V(v) BM_DIGCTL_OCRAM_BIST_CSR_BIST_DATA_CHANGE
+#define BP_DIGCTL_OCRAM_BIST_CSR_BIST_CLKEN             8
+#define BM_DIGCTL_OCRAM_BIST_CSR_BIST_CLKEN             0x100
+#define BF_DIGCTL_OCRAM_BIST_CSR_BIST_CLKEN(v)          (((v) & 0x1) << 8)
+#define BFM_DIGCTL_OCRAM_BIST_CSR_BIST_CLKEN(v)         BM_DIGCTL_OCRAM_BIST_CSR_BIST_CLKEN
+#define BF_DIGCTL_OCRAM_BIST_CSR_BIST_CLKEN_V(e)        BF_DIGCTL_OCRAM_BIST_CSR_BIST_CLKEN(BV_DIGCTL_OCRAM_BIST_CSR_BIST_CLKEN__##e)
+#define BFM_DIGCTL_OCRAM_BIST_CSR_BIST_CLKEN_V(v)       BM_DIGCTL_OCRAM_BIST_CSR_BIST_CLKEN
+#define BP_DIGCTL_OCRAM_BIST_CSR_FAIL                   3
+#define BM_DIGCTL_OCRAM_BIST_CSR_FAIL                   0x8
+#define BF_DIGCTL_OCRAM_BIST_CSR_FAIL(v)                (((v) & 0x1) << 3)
+#define BFM_DIGCTL_OCRAM_BIST_CSR_FAIL(v)               BM_DIGCTL_OCRAM_BIST_CSR_FAIL
+#define BF_DIGCTL_OCRAM_BIST_CSR_FAIL_V(e)              BF_DIGCTL_OCRAM_BIST_CSR_FAIL(BV_DIGCTL_OCRAM_BIST_CSR_FAIL__##e)
+#define BFM_DIGCTL_OCRAM_BIST_CSR_FAIL_V(v)             BM_DIGCTL_OCRAM_BIST_CSR_FAIL
+#define BP_DIGCTL_OCRAM_BIST_CSR_PASS                   2
+#define BM_DIGCTL_OCRAM_BIST_CSR_PASS                   0x4
+#define BF_DIGCTL_OCRAM_BIST_CSR_PASS(v)                (((v) & 0x1) << 2)
+#define BFM_DIGCTL_OCRAM_BIST_CSR_PASS(v)               BM_DIGCTL_OCRAM_BIST_CSR_PASS
+#define BF_DIGCTL_OCRAM_BIST_CSR_PASS_V(e)              BF_DIGCTL_OCRAM_BIST_CSR_PASS(BV_DIGCTL_OCRAM_BIST_CSR_PASS__##e)
+#define BFM_DIGCTL_OCRAM_BIST_CSR_PASS_V(v)             BM_DIGCTL_OCRAM_BIST_CSR_PASS
+#define BP_DIGCTL_OCRAM_BIST_CSR_DONE                   1
+#define BM_DIGCTL_OCRAM_BIST_CSR_DONE                   0x2
+#define BF_DIGCTL_OCRAM_BIST_CSR_DONE(v)                (((v) & 0x1) << 1)
+#define BFM_DIGCTL_OCRAM_BIST_CSR_DONE(v)               BM_DIGCTL_OCRAM_BIST_CSR_DONE
+#define BF_DIGCTL_OCRAM_BIST_CSR_DONE_V(e)              BF_DIGCTL_OCRAM_BIST_CSR_DONE(BV_DIGCTL_OCRAM_BIST_CSR_DONE__##e)
+#define BFM_DIGCTL_OCRAM_BIST_CSR_DONE_V(v)             BM_DIGCTL_OCRAM_BIST_CSR_DONE
+#define BP_DIGCTL_OCRAM_BIST_CSR_START                  0
+#define BM_DIGCTL_OCRAM_BIST_CSR_START                  0x1
+#define BF_DIGCTL_OCRAM_BIST_CSR_START(v)               (((v) & 0x1) << 0)
+#define BFM_DIGCTL_OCRAM_BIST_CSR_START(v)              BM_DIGCTL_OCRAM_BIST_CSR_START
+#define BF_DIGCTL_OCRAM_BIST_CSR_START_V(e)             BF_DIGCTL_OCRAM_BIST_CSR_START(BV_DIGCTL_OCRAM_BIST_CSR_START__##e)
+#define BFM_DIGCTL_OCRAM_BIST_CSR_START_V(v)            BM_DIGCTL_OCRAM_BIST_CSR_START
+
+#define HW_DIGCTL_OCRAM_STATUS0                     HW(DIGCTL_OCRAM_STATUS0)
+#define HWA_DIGCTL_OCRAM_STATUS0                    (0x8001c000 + 0x110)
+#define HWT_DIGCTL_OCRAM_STATUS0                    HWIO_32_RW
+#define HWN_DIGCTL_OCRAM_STATUS0                    DIGCTL_OCRAM_STATUS0
+#define HWI_DIGCTL_OCRAM_STATUS0                    
+#define BP_DIGCTL_OCRAM_STATUS0_FAILDATA00          0
+#define BM_DIGCTL_OCRAM_STATUS0_FAILDATA00          0xffffffff
+#define BF_DIGCTL_OCRAM_STATUS0_FAILDATA00(v)       (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_OCRAM_STATUS0_FAILDATA00(v)      BM_DIGCTL_OCRAM_STATUS0_FAILDATA00
+#define BF_DIGCTL_OCRAM_STATUS0_FAILDATA00_V(e)     BF_DIGCTL_OCRAM_STATUS0_FAILDATA00(BV_DIGCTL_OCRAM_STATUS0_FAILDATA00__##e)
+#define BFM_DIGCTL_OCRAM_STATUS0_FAILDATA00_V(v)    BM_DIGCTL_OCRAM_STATUS0_FAILDATA00
+
+#define HW_DIGCTL_OCRAM_STATUS1                     HW(DIGCTL_OCRAM_STATUS1)
+#define HWA_DIGCTL_OCRAM_STATUS1                    (0x8001c000 + 0x120)
+#define HWT_DIGCTL_OCRAM_STATUS1                    HWIO_32_RW
+#define HWN_DIGCTL_OCRAM_STATUS1                    DIGCTL_OCRAM_STATUS1
+#define HWI_DIGCTL_OCRAM_STATUS1                    
+#define BP_DIGCTL_OCRAM_STATUS1_FAILDATA01          0
+#define BM_DIGCTL_OCRAM_STATUS1_FAILDATA01          0xffffffff
+#define BF_DIGCTL_OCRAM_STATUS1_FAILDATA01(v)       (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_OCRAM_STATUS1_FAILDATA01(v)      BM_DIGCTL_OCRAM_STATUS1_FAILDATA01
+#define BF_DIGCTL_OCRAM_STATUS1_FAILDATA01_V(e)     BF_DIGCTL_OCRAM_STATUS1_FAILDATA01(BV_DIGCTL_OCRAM_STATUS1_FAILDATA01__##e)
+#define BFM_DIGCTL_OCRAM_STATUS1_FAILDATA01_V(v)    BM_DIGCTL_OCRAM_STATUS1_FAILDATA01
+
+#define HW_DIGCTL_OCRAM_STATUS2                     HW(DIGCTL_OCRAM_STATUS2)
+#define HWA_DIGCTL_OCRAM_STATUS2                    (0x8001c000 + 0x130)
+#define HWT_DIGCTL_OCRAM_STATUS2                    HWIO_32_RW
+#define HWN_DIGCTL_OCRAM_STATUS2                    DIGCTL_OCRAM_STATUS2
+#define HWI_DIGCTL_OCRAM_STATUS2                    
+#define BP_DIGCTL_OCRAM_STATUS2_FAILDATA10          0
+#define BM_DIGCTL_OCRAM_STATUS2_FAILDATA10          0xffffffff
+#define BF_DIGCTL_OCRAM_STATUS2_FAILDATA10(v)       (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_OCRAM_STATUS2_FAILDATA10(v)      BM_DIGCTL_OCRAM_STATUS2_FAILDATA10
+#define BF_DIGCTL_OCRAM_STATUS2_FAILDATA10_V(e)     BF_DIGCTL_OCRAM_STATUS2_FAILDATA10(BV_DIGCTL_OCRAM_STATUS2_FAILDATA10__##e)
+#define BFM_DIGCTL_OCRAM_STATUS2_FAILDATA10_V(v)    BM_DIGCTL_OCRAM_STATUS2_FAILDATA10
+
+#define HW_DIGCTL_OCRAM_STATUS3                     HW(DIGCTL_OCRAM_STATUS3)
+#define HWA_DIGCTL_OCRAM_STATUS3                    (0x8001c000 + 0x140)
+#define HWT_DIGCTL_OCRAM_STATUS3                    HWIO_32_RW
+#define HWN_DIGCTL_OCRAM_STATUS3                    DIGCTL_OCRAM_STATUS3
+#define HWI_DIGCTL_OCRAM_STATUS3                    
+#define BP_DIGCTL_OCRAM_STATUS3_FAILDATA11          0
+#define BM_DIGCTL_OCRAM_STATUS3_FAILDATA11          0xffffffff
+#define BF_DIGCTL_OCRAM_STATUS3_FAILDATA11(v)       (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_OCRAM_STATUS3_FAILDATA11(v)      BM_DIGCTL_OCRAM_STATUS3_FAILDATA11
+#define BF_DIGCTL_OCRAM_STATUS3_FAILDATA11_V(e)     BF_DIGCTL_OCRAM_STATUS3_FAILDATA11(BV_DIGCTL_OCRAM_STATUS3_FAILDATA11__##e)
+#define BFM_DIGCTL_OCRAM_STATUS3_FAILDATA11_V(v)    BM_DIGCTL_OCRAM_STATUS3_FAILDATA11
+
+#define HW_DIGCTL_OCRAM_STATUS4                     HW(DIGCTL_OCRAM_STATUS4)
+#define HWA_DIGCTL_OCRAM_STATUS4                    (0x8001c000 + 0x150)
+#define HWT_DIGCTL_OCRAM_STATUS4                    HWIO_32_RW
+#define HWN_DIGCTL_OCRAM_STATUS4                    DIGCTL_OCRAM_STATUS4
+#define HWI_DIGCTL_OCRAM_STATUS4                    
+#define BP_DIGCTL_OCRAM_STATUS4_FAILDATA20          0
+#define BM_DIGCTL_OCRAM_STATUS4_FAILDATA20          0xffffffff
+#define BF_DIGCTL_OCRAM_STATUS4_FAILDATA20(v)       (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_OCRAM_STATUS4_FAILDATA20(v)      BM_DIGCTL_OCRAM_STATUS4_FAILDATA20
+#define BF_DIGCTL_OCRAM_STATUS4_FAILDATA20_V(e)     BF_DIGCTL_OCRAM_STATUS4_FAILDATA20(BV_DIGCTL_OCRAM_STATUS4_FAILDATA20__##e)
+#define BFM_DIGCTL_OCRAM_STATUS4_FAILDATA20_V(v)    BM_DIGCTL_OCRAM_STATUS4_FAILDATA20
+
+#define HW_DIGCTL_OCRAM_STATUS5                     HW(DIGCTL_OCRAM_STATUS5)
+#define HWA_DIGCTL_OCRAM_STATUS5                    (0x8001c000 + 0x160)
+#define HWT_DIGCTL_OCRAM_STATUS5                    HWIO_32_RW
+#define HWN_DIGCTL_OCRAM_STATUS5                    DIGCTL_OCRAM_STATUS5
+#define HWI_DIGCTL_OCRAM_STATUS5                    
+#define BP_DIGCTL_OCRAM_STATUS5_FAILDATA21          0
+#define BM_DIGCTL_OCRAM_STATUS5_FAILDATA21          0xffffffff
+#define BF_DIGCTL_OCRAM_STATUS5_FAILDATA21(v)       (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_OCRAM_STATUS5_FAILDATA21(v)      BM_DIGCTL_OCRAM_STATUS5_FAILDATA21
+#define BF_DIGCTL_OCRAM_STATUS5_FAILDATA21_V(e)     BF_DIGCTL_OCRAM_STATUS5_FAILDATA21(BV_DIGCTL_OCRAM_STATUS5_FAILDATA21__##e)
+#define BFM_DIGCTL_OCRAM_STATUS5_FAILDATA21_V(v)    BM_DIGCTL_OCRAM_STATUS5_FAILDATA21
+
+#define HW_DIGCTL_OCRAM_STATUS6                     HW(DIGCTL_OCRAM_STATUS6)
+#define HWA_DIGCTL_OCRAM_STATUS6                    (0x8001c000 + 0x170)
+#define HWT_DIGCTL_OCRAM_STATUS6                    HWIO_32_RW
+#define HWN_DIGCTL_OCRAM_STATUS6                    DIGCTL_OCRAM_STATUS6
+#define HWI_DIGCTL_OCRAM_STATUS6                    
+#define BP_DIGCTL_OCRAM_STATUS6_FAILDATA30          0
+#define BM_DIGCTL_OCRAM_STATUS6_FAILDATA30          0xffffffff
+#define BF_DIGCTL_OCRAM_STATUS6_FAILDATA30(v)       (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_OCRAM_STATUS6_FAILDATA30(v)      BM_DIGCTL_OCRAM_STATUS6_FAILDATA30
+#define BF_DIGCTL_OCRAM_STATUS6_FAILDATA30_V(e)     BF_DIGCTL_OCRAM_STATUS6_FAILDATA30(BV_DIGCTL_OCRAM_STATUS6_FAILDATA30__##e)
+#define BFM_DIGCTL_OCRAM_STATUS6_FAILDATA30_V(v)    BM_DIGCTL_OCRAM_STATUS6_FAILDATA30
+
+#define HW_DIGCTL_OCRAM_STATUS7                     HW(DIGCTL_OCRAM_STATUS7)
+#define HWA_DIGCTL_OCRAM_STATUS7                    (0x8001c000 + 0x180)
+#define HWT_DIGCTL_OCRAM_STATUS7                    HWIO_32_RW
+#define HWN_DIGCTL_OCRAM_STATUS7                    DIGCTL_OCRAM_STATUS7
+#define HWI_DIGCTL_OCRAM_STATUS7                    
+#define BP_DIGCTL_OCRAM_STATUS7_FAILDATA31          0
+#define BM_DIGCTL_OCRAM_STATUS7_FAILDATA31          0xffffffff
+#define BF_DIGCTL_OCRAM_STATUS7_FAILDATA31(v)       (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_OCRAM_STATUS7_FAILDATA31(v)      BM_DIGCTL_OCRAM_STATUS7_FAILDATA31
+#define BF_DIGCTL_OCRAM_STATUS7_FAILDATA31_V(e)     BF_DIGCTL_OCRAM_STATUS7_FAILDATA31(BV_DIGCTL_OCRAM_STATUS7_FAILDATA31__##e)
+#define BFM_DIGCTL_OCRAM_STATUS7_FAILDATA31_V(v)    BM_DIGCTL_OCRAM_STATUS7_FAILDATA31
+
+#define HW_DIGCTL_OCRAM_STATUS8                     HW(DIGCTL_OCRAM_STATUS8)
+#define HWA_DIGCTL_OCRAM_STATUS8                    (0x8001c000 + 0x190)
+#define HWT_DIGCTL_OCRAM_STATUS8                    HWIO_32_RW
+#define HWN_DIGCTL_OCRAM_STATUS8                    DIGCTL_OCRAM_STATUS8
+#define HWI_DIGCTL_OCRAM_STATUS8                    
+#define BP_DIGCTL_OCRAM_STATUS8_FAILADDR01          16
+#define BM_DIGCTL_OCRAM_STATUS8_FAILADDR01          0xffff0000
+#define BF_DIGCTL_OCRAM_STATUS8_FAILADDR01(v)       (((v) & 0xffff) << 16)
+#define BFM_DIGCTL_OCRAM_STATUS8_FAILADDR01(v)      BM_DIGCTL_OCRAM_STATUS8_FAILADDR01
+#define BF_DIGCTL_OCRAM_STATUS8_FAILADDR01_V(e)     BF_DIGCTL_OCRAM_STATUS8_FAILADDR01(BV_DIGCTL_OCRAM_STATUS8_FAILADDR01__##e)
+#define BFM_DIGCTL_OCRAM_STATUS8_FAILADDR01_V(v)    BM_DIGCTL_OCRAM_STATUS8_FAILADDR01
+#define BP_DIGCTL_OCRAM_STATUS8_FAILADDR00          0
+#define BM_DIGCTL_OCRAM_STATUS8_FAILADDR00          0xffff
+#define BF_DIGCTL_OCRAM_STATUS8_FAILADDR00(v)       (((v) & 0xffff) << 0)
+#define BFM_DIGCTL_OCRAM_STATUS8_FAILADDR00(v)      BM_DIGCTL_OCRAM_STATUS8_FAILADDR00
+#define BF_DIGCTL_OCRAM_STATUS8_FAILADDR00_V(e)     BF_DIGCTL_OCRAM_STATUS8_FAILADDR00(BV_DIGCTL_OCRAM_STATUS8_FAILADDR00__##e)
+#define BFM_DIGCTL_OCRAM_STATUS8_FAILADDR00_V(v)    BM_DIGCTL_OCRAM_STATUS8_FAILADDR00
+
+#define HW_DIGCTL_OCRAM_STATUS9                     HW(DIGCTL_OCRAM_STATUS9)
+#define HWA_DIGCTL_OCRAM_STATUS9                    (0x8001c000 + 0x1a0)
+#define HWT_DIGCTL_OCRAM_STATUS9                    HWIO_32_RW
+#define HWN_DIGCTL_OCRAM_STATUS9                    DIGCTL_OCRAM_STATUS9
+#define HWI_DIGCTL_OCRAM_STATUS9                    
+#define BP_DIGCTL_OCRAM_STATUS9_FAILADDR11          16
+#define BM_DIGCTL_OCRAM_STATUS9_FAILADDR11          0xffff0000
+#define BF_DIGCTL_OCRAM_STATUS9_FAILADDR11(v)       (((v) & 0xffff) << 16)
+#define BFM_DIGCTL_OCRAM_STATUS9_FAILADDR11(v)      BM_DIGCTL_OCRAM_STATUS9_FAILADDR11
+#define BF_DIGCTL_OCRAM_STATUS9_FAILADDR11_V(e)     BF_DIGCTL_OCRAM_STATUS9_FAILADDR11(BV_DIGCTL_OCRAM_STATUS9_FAILADDR11__##e)
+#define BFM_DIGCTL_OCRAM_STATUS9_FAILADDR11_V(v)    BM_DIGCTL_OCRAM_STATUS9_FAILADDR11
+#define BP_DIGCTL_OCRAM_STATUS9_FAILADDR10          0
+#define BM_DIGCTL_OCRAM_STATUS9_FAILADDR10          0xffff
+#define BF_DIGCTL_OCRAM_STATUS9_FAILADDR10(v)       (((v) & 0xffff) << 0)
+#define BFM_DIGCTL_OCRAM_STATUS9_FAILADDR10(v)      BM_DIGCTL_OCRAM_STATUS9_FAILADDR10
+#define BF_DIGCTL_OCRAM_STATUS9_FAILADDR10_V(e)     BF_DIGCTL_OCRAM_STATUS9_FAILADDR10(BV_DIGCTL_OCRAM_STATUS9_FAILADDR10__##e)
+#define BFM_DIGCTL_OCRAM_STATUS9_FAILADDR10_V(v)    BM_DIGCTL_OCRAM_STATUS9_FAILADDR10
+
+#define HW_DIGCTL_OCRAM_STATUS10                    HW(DIGCTL_OCRAM_STATUS10)
+#define HWA_DIGCTL_OCRAM_STATUS10                   (0x8001c000 + 0x1b0)
+#define HWT_DIGCTL_OCRAM_STATUS10                   HWIO_32_RW
+#define HWN_DIGCTL_OCRAM_STATUS10                   DIGCTL_OCRAM_STATUS10
+#define HWI_DIGCTL_OCRAM_STATUS10                   
+#define BP_DIGCTL_OCRAM_STATUS10_FAILADDR21         16
+#define BM_DIGCTL_OCRAM_STATUS10_FAILADDR21         0xffff0000
+#define BF_DIGCTL_OCRAM_STATUS10_FAILADDR21(v)      (((v) & 0xffff) << 16)
+#define BFM_DIGCTL_OCRAM_STATUS10_FAILADDR21(v)     BM_DIGCTL_OCRAM_STATUS10_FAILADDR21
+#define BF_DIGCTL_OCRAM_STATUS10_FAILADDR21_V(e)    BF_DIGCTL_OCRAM_STATUS10_FAILADDR21(BV_DIGCTL_OCRAM_STATUS10_FAILADDR21__##e)
+#define BFM_DIGCTL_OCRAM_STATUS10_FAILADDR21_V(v)   BM_DIGCTL_OCRAM_STATUS10_FAILADDR21
+#define BP_DIGCTL_OCRAM_STATUS10_FAILADDR20         0
+#define BM_DIGCTL_OCRAM_STATUS10_FAILADDR20         0xffff
+#define BF_DIGCTL_OCRAM_STATUS10_FAILADDR20(v)      (((v) & 0xffff) << 0)
+#define BFM_DIGCTL_OCRAM_STATUS10_FAILADDR20(v)     BM_DIGCTL_OCRAM_STATUS10_FAILADDR20
+#define BF_DIGCTL_OCRAM_STATUS10_FAILADDR20_V(e)    BF_DIGCTL_OCRAM_STATUS10_FAILADDR20(BV_DIGCTL_OCRAM_STATUS10_FAILADDR20__##e)
+#define BFM_DIGCTL_OCRAM_STATUS10_FAILADDR20_V(v)   BM_DIGCTL_OCRAM_STATUS10_FAILADDR20
+
+#define HW_DIGCTL_OCRAM_STATUS11                    HW(DIGCTL_OCRAM_STATUS11)
+#define HWA_DIGCTL_OCRAM_STATUS11                   (0x8001c000 + 0x1c0)
+#define HWT_DIGCTL_OCRAM_STATUS11                   HWIO_32_RW
+#define HWN_DIGCTL_OCRAM_STATUS11                   DIGCTL_OCRAM_STATUS11
+#define HWI_DIGCTL_OCRAM_STATUS11                   
+#define BP_DIGCTL_OCRAM_STATUS11_FAILADDR31         16
+#define BM_DIGCTL_OCRAM_STATUS11_FAILADDR31         0xffff0000
+#define BF_DIGCTL_OCRAM_STATUS11_FAILADDR31(v)      (((v) & 0xffff) << 16)
+#define BFM_DIGCTL_OCRAM_STATUS11_FAILADDR31(v)     BM_DIGCTL_OCRAM_STATUS11_FAILADDR31
+#define BF_DIGCTL_OCRAM_STATUS11_FAILADDR31_V(e)    BF_DIGCTL_OCRAM_STATUS11_FAILADDR31(BV_DIGCTL_OCRAM_STATUS11_FAILADDR31__##e)
+#define BFM_DIGCTL_OCRAM_STATUS11_FAILADDR31_V(v)   BM_DIGCTL_OCRAM_STATUS11_FAILADDR31
+#define BP_DIGCTL_OCRAM_STATUS11_FAILADDR30         0
+#define BM_DIGCTL_OCRAM_STATUS11_FAILADDR30         0xffff
+#define BF_DIGCTL_OCRAM_STATUS11_FAILADDR30(v)      (((v) & 0xffff) << 0)
+#define BFM_DIGCTL_OCRAM_STATUS11_FAILADDR30(v)     BM_DIGCTL_OCRAM_STATUS11_FAILADDR30
+#define BF_DIGCTL_OCRAM_STATUS11_FAILADDR30_V(e)    BF_DIGCTL_OCRAM_STATUS11_FAILADDR30(BV_DIGCTL_OCRAM_STATUS11_FAILADDR30__##e)
+#define BFM_DIGCTL_OCRAM_STATUS11_FAILADDR30_V(v)   BM_DIGCTL_OCRAM_STATUS11_FAILADDR30
+
+#define HW_DIGCTL_OCRAM_STATUS12                    HW(DIGCTL_OCRAM_STATUS12)
+#define HWA_DIGCTL_OCRAM_STATUS12                   (0x8001c000 + 0x1d0)
+#define HWT_DIGCTL_OCRAM_STATUS12                   HWIO_32_RW
+#define HWN_DIGCTL_OCRAM_STATUS12                   DIGCTL_OCRAM_STATUS12
+#define HWI_DIGCTL_OCRAM_STATUS12                   
+#define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE11        24
+#define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE11        0x1f000000
+#define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE11(v)     (((v) & 0x1f) << 24)
+#define BFM_DIGCTL_OCRAM_STATUS12_FAILSTATE11(v)    BM_DIGCTL_OCRAM_STATUS12_FAILSTATE11
+#define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE11_V(e)   BF_DIGCTL_OCRAM_STATUS12_FAILSTATE11(BV_DIGCTL_OCRAM_STATUS12_FAILSTATE11__##e)
+#define BFM_DIGCTL_OCRAM_STATUS12_FAILSTATE11_V(v)  BM_DIGCTL_OCRAM_STATUS12_FAILSTATE11
+#define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE10        16
+#define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE10        0x1f0000
+#define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE10(v)     (((v) & 0x1f) << 16)
+#define BFM_DIGCTL_OCRAM_STATUS12_FAILSTATE10(v)    BM_DIGCTL_OCRAM_STATUS12_FAILSTATE10
+#define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE10_V(e)   BF_DIGCTL_OCRAM_STATUS12_FAILSTATE10(BV_DIGCTL_OCRAM_STATUS12_FAILSTATE10__##e)
+#define BFM_DIGCTL_OCRAM_STATUS12_FAILSTATE10_V(v)  BM_DIGCTL_OCRAM_STATUS12_FAILSTATE10
+#define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE01        8
+#define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE01        0x1f00
+#define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE01(v)     (((v) & 0x1f) << 8)
+#define BFM_DIGCTL_OCRAM_STATUS12_FAILSTATE01(v)    BM_DIGCTL_OCRAM_STATUS12_FAILSTATE01
+#define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE01_V(e)   BF_DIGCTL_OCRAM_STATUS12_FAILSTATE01(BV_DIGCTL_OCRAM_STATUS12_FAILSTATE01__##e)
+#define BFM_DIGCTL_OCRAM_STATUS12_FAILSTATE01_V(v)  BM_DIGCTL_OCRAM_STATUS12_FAILSTATE01
+#define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE00        0
+#define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE00        0x1f
+#define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE00(v)     (((v) & 0x1f) << 0)
+#define BFM_DIGCTL_OCRAM_STATUS12_FAILSTATE00(v)    BM_DIGCTL_OCRAM_STATUS12_FAILSTATE00
+#define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE00_V(e)   BF_DIGCTL_OCRAM_STATUS12_FAILSTATE00(BV_DIGCTL_OCRAM_STATUS12_FAILSTATE00__##e)
+#define BFM_DIGCTL_OCRAM_STATUS12_FAILSTATE00_V(v)  BM_DIGCTL_OCRAM_STATUS12_FAILSTATE00
+
+#define HW_DIGCTL_OCRAM_STATUS13                    HW(DIGCTL_OCRAM_STATUS13)
+#define HWA_DIGCTL_OCRAM_STATUS13                   (0x8001c000 + 0x1e0)
+#define HWT_DIGCTL_OCRAM_STATUS13                   HWIO_32_RW
+#define HWN_DIGCTL_OCRAM_STATUS13                   DIGCTL_OCRAM_STATUS13
+#define HWI_DIGCTL_OCRAM_STATUS13                   
+#define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE31        24
+#define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE31        0x1f000000
+#define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE31(v)     (((v) & 0x1f) << 24)
+#define BFM_DIGCTL_OCRAM_STATUS13_FAILSTATE31(v)    BM_DIGCTL_OCRAM_STATUS13_FAILSTATE31
+#define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE31_V(e)   BF_DIGCTL_OCRAM_STATUS13_FAILSTATE31(BV_DIGCTL_OCRAM_STATUS13_FAILSTATE31__##e)
+#define BFM_DIGCTL_OCRAM_STATUS13_FAILSTATE31_V(v)  BM_DIGCTL_OCRAM_STATUS13_FAILSTATE31
+#define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE30        16
+#define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE30        0x1f0000
+#define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE30(v)     (((v) & 0x1f) << 16)
+#define BFM_DIGCTL_OCRAM_STATUS13_FAILSTATE30(v)    BM_DIGCTL_OCRAM_STATUS13_FAILSTATE30
+#define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE30_V(e)   BF_DIGCTL_OCRAM_STATUS13_FAILSTATE30(BV_DIGCTL_OCRAM_STATUS13_FAILSTATE30__##e)
+#define BFM_DIGCTL_OCRAM_STATUS13_FAILSTATE30_V(v)  BM_DIGCTL_OCRAM_STATUS13_FAILSTATE30
+#define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE21        8
+#define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE21        0x1f00
+#define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE21(v)     (((v) & 0x1f) << 8)
+#define BFM_DIGCTL_OCRAM_STATUS13_FAILSTATE21(v)    BM_DIGCTL_OCRAM_STATUS13_FAILSTATE21
+#define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE21_V(e)   BF_DIGCTL_OCRAM_STATUS13_FAILSTATE21(BV_DIGCTL_OCRAM_STATUS13_FAILSTATE21__##e)
+#define BFM_DIGCTL_OCRAM_STATUS13_FAILSTATE21_V(v)  BM_DIGCTL_OCRAM_STATUS13_FAILSTATE21
+#define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE20        0
+#define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE20        0x1f
+#define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE20(v)     (((v) & 0x1f) << 0)
+#define BFM_DIGCTL_OCRAM_STATUS13_FAILSTATE20(v)    BM_DIGCTL_OCRAM_STATUS13_FAILSTATE20
+#define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE20_V(e)   BF_DIGCTL_OCRAM_STATUS13_FAILSTATE20(BV_DIGCTL_OCRAM_STATUS13_FAILSTATE20__##e)
+#define BFM_DIGCTL_OCRAM_STATUS13_FAILSTATE20_V(v)  BM_DIGCTL_OCRAM_STATUS13_FAILSTATE20
+
+#define HW_DIGCTL_SCRATCH0              HW(DIGCTL_SCRATCH0)
+#define HWA_DIGCTL_SCRATCH0             (0x8001c000 + 0x290)
+#define HWT_DIGCTL_SCRATCH0             HWIO_32_RW
+#define HWN_DIGCTL_SCRATCH0             DIGCTL_SCRATCH0
+#define HWI_DIGCTL_SCRATCH0             
+#define BP_DIGCTL_SCRATCH0_PTR          0
+#define BM_DIGCTL_SCRATCH0_PTR          0xffffffff
+#define BF_DIGCTL_SCRATCH0_PTR(v)       (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_SCRATCH0_PTR(v)      BM_DIGCTL_SCRATCH0_PTR
+#define BF_DIGCTL_SCRATCH0_PTR_V(e)     BF_DIGCTL_SCRATCH0_PTR(BV_DIGCTL_SCRATCH0_PTR__##e)
+#define BFM_DIGCTL_SCRATCH0_PTR_V(v)    BM_DIGCTL_SCRATCH0_PTR
+
+#define HW_DIGCTL_SCRATCH1              HW(DIGCTL_SCRATCH1)
+#define HWA_DIGCTL_SCRATCH1             (0x8001c000 + 0x2a0)
+#define HWT_DIGCTL_SCRATCH1             HWIO_32_RW
+#define HWN_DIGCTL_SCRATCH1             DIGCTL_SCRATCH1
+#define HWI_DIGCTL_SCRATCH1             
+#define BP_DIGCTL_SCRATCH1_PTR          0
+#define BM_DIGCTL_SCRATCH1_PTR          0xffffffff
+#define BF_DIGCTL_SCRATCH1_PTR(v)       (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_SCRATCH1_PTR(v)      BM_DIGCTL_SCRATCH1_PTR
+#define BF_DIGCTL_SCRATCH1_PTR_V(e)     BF_DIGCTL_SCRATCH1_PTR(BV_DIGCTL_SCRATCH1_PTR__##e)
+#define BFM_DIGCTL_SCRATCH1_PTR_V(v)    BM_DIGCTL_SCRATCH1_PTR
+
+#define HW_DIGCTL_ARMCACHE                  HW(DIGCTL_ARMCACHE)
+#define HWA_DIGCTL_ARMCACHE                 (0x8001c000 + 0x2b0)
+#define HWT_DIGCTL_ARMCACHE                 HWIO_32_RW
+#define HWN_DIGCTL_ARMCACHE                 DIGCTL_ARMCACHE
+#define HWI_DIGCTL_ARMCACHE                 
+#define BP_DIGCTL_ARMCACHE_CACHE_SS         8
+#define BM_DIGCTL_ARMCACHE_CACHE_SS         0x300
+#define BF_DIGCTL_ARMCACHE_CACHE_SS(v)      (((v) & 0x3) << 8)
+#define BFM_DIGCTL_ARMCACHE_CACHE_SS(v)     BM_DIGCTL_ARMCACHE_CACHE_SS
+#define BF_DIGCTL_ARMCACHE_CACHE_SS_V(e)    BF_DIGCTL_ARMCACHE_CACHE_SS(BV_DIGCTL_ARMCACHE_CACHE_SS__##e)
+#define BFM_DIGCTL_ARMCACHE_CACHE_SS_V(v)   BM_DIGCTL_ARMCACHE_CACHE_SS
+#define BP_DIGCTL_ARMCACHE_DTAG_SS          4
+#define BM_DIGCTL_ARMCACHE_DTAG_SS          0x30
+#define BF_DIGCTL_ARMCACHE_DTAG_SS(v)       (((v) & 0x3) << 4)
+#define BFM_DIGCTL_ARMCACHE_DTAG_SS(v)      BM_DIGCTL_ARMCACHE_DTAG_SS
+#define BF_DIGCTL_ARMCACHE_DTAG_SS_V(e)     BF_DIGCTL_ARMCACHE_DTAG_SS(BV_DIGCTL_ARMCACHE_DTAG_SS__##e)
+#define BFM_DIGCTL_ARMCACHE_DTAG_SS_V(v)    BM_DIGCTL_ARMCACHE_DTAG_SS
+#define BP_DIGCTL_ARMCACHE_ITAG_SS          0
+#define BM_DIGCTL_ARMCACHE_ITAG_SS          0x3
+#define BF_DIGCTL_ARMCACHE_ITAG_SS(v)       (((v) & 0x3) << 0)
+#define BFM_DIGCTL_ARMCACHE_ITAG_SS(v)      BM_DIGCTL_ARMCACHE_ITAG_SS
+#define BF_DIGCTL_ARMCACHE_ITAG_SS_V(e)     BF_DIGCTL_ARMCACHE_ITAG_SS(BV_DIGCTL_ARMCACHE_ITAG_SS__##e)
+#define BFM_DIGCTL_ARMCACHE_ITAG_SS_V(v)    BM_DIGCTL_ARMCACHE_ITAG_SS
+
+#define HW_DIGCTL_DEBUG_TRAP_ADDR_LOW               HW(DIGCTL_DEBUG_TRAP_ADDR_LOW)
+#define HWA_DIGCTL_DEBUG_TRAP_ADDR_LOW              (0x8001c000 + 0x2c0)
+#define HWT_DIGCTL_DEBUG_TRAP_ADDR_LOW              HWIO_32_RW
+#define HWN_DIGCTL_DEBUG_TRAP_ADDR_LOW              DIGCTL_DEBUG_TRAP_ADDR_LOW
+#define HWI_DIGCTL_DEBUG_TRAP_ADDR_LOW              
+#define BP_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR          0
+#define BM_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR          0xffffffff
+#define BF_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR(v)       (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR(v)      BM_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR
+#define BF_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR_V(e)     BF_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR(BV_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR__##e)
+#define BFM_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR_V(v)    BM_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR
+
+#define HW_DIGCTL_DEBUG_TRAP_ADDR_HIGH              HW(DIGCTL_DEBUG_TRAP_ADDR_HIGH)
+#define HWA_DIGCTL_DEBUG_TRAP_ADDR_HIGH             (0x8001c000 + 0x2d0)
+#define HWT_DIGCTL_DEBUG_TRAP_ADDR_HIGH             HWIO_32_RW
+#define HWN_DIGCTL_DEBUG_TRAP_ADDR_HIGH             DIGCTL_DEBUG_TRAP_ADDR_HIGH
+#define HWI_DIGCTL_DEBUG_TRAP_ADDR_HIGH             
+#define BP_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR         0
+#define BM_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR         0xffffffff
+#define BF_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR(v)      (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR(v)     BM_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR
+#define BF_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR_V(e)    BF_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR(BV_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR__##e)
+#define BFM_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR_V(v)   BM_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR
+
+#define HW_DIGCTL_SGTL                  HW(DIGCTL_SGTL)
+#define HWA_DIGCTL_SGTL                 (0x8001c000 + 0x300)
+#define HWT_DIGCTL_SGTL                 HWIO_32_RW
+#define HWN_DIGCTL_SGTL                 DIGCTL_SGTL
+#define HWI_DIGCTL_SGTL                 
+#define BP_DIGCTL_SGTL_COPYRIGHT        0
+#define BM_DIGCTL_SGTL_COPYRIGHT        0xffffffff
+#define BF_DIGCTL_SGTL_COPYRIGHT(v)     (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_SGTL_COPYRIGHT(v)    BM_DIGCTL_SGTL_COPYRIGHT
+#define BF_DIGCTL_SGTL_COPYRIGHT_V(e)   BF_DIGCTL_SGTL_COPYRIGHT(BV_DIGCTL_SGTL_COPYRIGHT__##e)
+#define BFM_DIGCTL_SGTL_COPYRIGHT_V(v)  BM_DIGCTL_SGTL_COPYRIGHT
+
+#define HW_DIGCTL_CHIPID                    HW(DIGCTL_CHIPID)
+#define HWA_DIGCTL_CHIPID                   (0x8001c000 + 0x310)
+#define HWT_DIGCTL_CHIPID                   HWIO_32_RW
+#define HWN_DIGCTL_CHIPID                   DIGCTL_CHIPID
+#define HWI_DIGCTL_CHIPID                   
+#define BP_DIGCTL_CHIPID_PRODUCT_CODE       16
+#define BM_DIGCTL_CHIPID_PRODUCT_CODE       0xffff0000
+#define BF_DIGCTL_CHIPID_PRODUCT_CODE(v)    (((v) & 0xffff) << 16)
+#define BFM_DIGCTL_CHIPID_PRODUCT_CODE(v)   BM_DIGCTL_CHIPID_PRODUCT_CODE
+#define BF_DIGCTL_CHIPID_PRODUCT_CODE_V(e)  BF_DIGCTL_CHIPID_PRODUCT_CODE(BV_DIGCTL_CHIPID_PRODUCT_CODE__##e)
+#define BFM_DIGCTL_CHIPID_PRODUCT_CODE_V(v) BM_DIGCTL_CHIPID_PRODUCT_CODE
+#define BP_DIGCTL_CHIPID_REVISION           0
+#define BM_DIGCTL_CHIPID_REVISION           0xff
+#define BF_DIGCTL_CHIPID_REVISION(v)        (((v) & 0xff) << 0)
+#define BFM_DIGCTL_CHIPID_REVISION(v)       BM_DIGCTL_CHIPID_REVISION
+#define BF_DIGCTL_CHIPID_REVISION_V(e)      BF_DIGCTL_CHIPID_REVISION(BV_DIGCTL_CHIPID_REVISION__##e)
+#define BFM_DIGCTL_CHIPID_REVISION_V(v)     BM_DIGCTL_CHIPID_REVISION
+
+#define HW_DIGCTL_AHB_STATS_SELECT                          HW(DIGCTL_AHB_STATS_SELECT)
+#define HWA_DIGCTL_AHB_STATS_SELECT                         (0x8001c000 + 0x330)
+#define HWT_DIGCTL_AHB_STATS_SELECT                         HWIO_32_RW
+#define HWN_DIGCTL_AHB_STATS_SELECT                         DIGCTL_AHB_STATS_SELECT
+#define HWI_DIGCTL_AHB_STATS_SELECT                         
+#define BP_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT         24
+#define BM_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT         0xf000000
+#define BV_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT__APBH   0x1
+#define BV_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT__APBX   0x2
+#define BV_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT__USB    0x4
+#define BF_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT(v)      (((v) & 0xf) << 24)
+#define BFM_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT(v)     BM_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT
+#define BF_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT_V(e)    BF_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT(BV_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT__##e)
+#define BFM_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT_V(v)   BM_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT
+#define BP_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT         16
+#define BM_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT         0xf0000
+#define BV_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT__ARM_D  0x1
+#define BF_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT(v)      (((v) & 0xf) << 16)
+#define BFM_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT(v)     BM_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT
+#define BF_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT_V(e)    BF_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT(BV_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT__##e)
+#define BFM_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT_V(v)   BM_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT
+#define BP_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT         8
+#define BM_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT         0xf00
+#define BV_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT__ARM_I  0x1
+#define BF_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT(v)      (((v) & 0xf) << 8)
+#define BFM_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT(v)     BM_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT
+#define BF_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT_V(e)    BF_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT(BV_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT__##e)
+#define BFM_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT_V(v)   BM_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT
+#define BP_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT         0
+#define BM_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT         0xf
+#define BV_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT__ECC8   0x1
+#define BV_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT__CRYPTO 0x2
+#define BF_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT(v)      (((v) & 0xf) << 0)
+#define BFM_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT(v)     BM_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT
+#define BF_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT_V(e)    BF_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT(BV_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT__##e)
+#define BFM_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT_V(v)   BM_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT
+
+#define HW_DIGCTL_L0_AHB_ACTIVE_CYCLES              HW(DIGCTL_L0_AHB_ACTIVE_CYCLES)
+#define HWA_DIGCTL_L0_AHB_ACTIVE_CYCLES             (0x8001c000 + 0x340)
+#define HWT_DIGCTL_L0_AHB_ACTIVE_CYCLES             HWIO_32_RW
+#define HWN_DIGCTL_L0_AHB_ACTIVE_CYCLES             DIGCTL_L0_AHB_ACTIVE_CYCLES
+#define HWI_DIGCTL_L0_AHB_ACTIVE_CYCLES             
+#define BP_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT        0
+#define BM_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT        0xffffffff
+#define BF_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT(v)     (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT(v)    BM_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT
+#define BF_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT_V(e)   BF_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT(BV_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT__##e)
+#define BFM_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT_V(v)  BM_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT
+
+#define HW_DIGCTL_L0_AHB_DATA_STALLED               HW(DIGCTL_L0_AHB_DATA_STALLED)
+#define HWA_DIGCTL_L0_AHB_DATA_STALLED              (0x8001c000 + 0x350)
+#define HWT_DIGCTL_L0_AHB_DATA_STALLED              HWIO_32_RW
+#define HWN_DIGCTL_L0_AHB_DATA_STALLED              DIGCTL_L0_AHB_DATA_STALLED
+#define HWI_DIGCTL_L0_AHB_DATA_STALLED              
+#define BP_DIGCTL_L0_AHB_DATA_STALLED_COUNT         0
+#define BM_DIGCTL_L0_AHB_DATA_STALLED_COUNT         0xffffffff
+#define BF_DIGCTL_L0_AHB_DATA_STALLED_COUNT(v)      (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_L0_AHB_DATA_STALLED_COUNT(v)     BM_DIGCTL_L0_AHB_DATA_STALLED_COUNT
+#define BF_DIGCTL_L0_AHB_DATA_STALLED_COUNT_V(e)    BF_DIGCTL_L0_AHB_DATA_STALLED_COUNT(BV_DIGCTL_L0_AHB_DATA_STALLED_COUNT__##e)
+#define BFM_DIGCTL_L0_AHB_DATA_STALLED_COUNT_V(v)   BM_DIGCTL_L0_AHB_DATA_STALLED_COUNT
+
+#define HW_DIGCTL_L0_AHB_DATA_CYCLES                HW(DIGCTL_L0_AHB_DATA_CYCLES)
+#define HWA_DIGCTL_L0_AHB_DATA_CYCLES               (0x8001c000 + 0x360)
+#define HWT_DIGCTL_L0_AHB_DATA_CYCLES               HWIO_32_RW
+#define HWN_DIGCTL_L0_AHB_DATA_CYCLES               DIGCTL_L0_AHB_DATA_CYCLES
+#define HWI_DIGCTL_L0_AHB_DATA_CYCLES               
+#define BP_DIGCTL_L0_AHB_DATA_CYCLES_COUNT          0
+#define BM_DIGCTL_L0_AHB_DATA_CYCLES_COUNT          0xffffffff
+#define BF_DIGCTL_L0_AHB_DATA_CYCLES_COUNT(v)       (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_L0_AHB_DATA_CYCLES_COUNT(v)      BM_DIGCTL_L0_AHB_DATA_CYCLES_COUNT
+#define BF_DIGCTL_L0_AHB_DATA_CYCLES_COUNT_V(e)     BF_DIGCTL_L0_AHB_DATA_CYCLES_COUNT(BV_DIGCTL_L0_AHB_DATA_CYCLES_COUNT__##e)
+#define BFM_DIGCTL_L0_AHB_DATA_CYCLES_COUNT_V(v)    BM_DIGCTL_L0_AHB_DATA_CYCLES_COUNT
+
+#define HW_DIGCTL_L1_AHB_ACTIVE_CYCLES              HW(DIGCTL_L1_AHB_ACTIVE_CYCLES)
+#define HWA_DIGCTL_L1_AHB_ACTIVE_CYCLES             (0x8001c000 + 0x370)
+#define HWT_DIGCTL_L1_AHB_ACTIVE_CYCLES             HWIO_32_RW
+#define HWN_DIGCTL_L1_AHB_ACTIVE_CYCLES             DIGCTL_L1_AHB_ACTIVE_CYCLES
+#define HWI_DIGCTL_L1_AHB_ACTIVE_CYCLES             
+#define BP_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT        0
+#define BM_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT        0xffffffff
+#define BF_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT(v)     (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT(v)    BM_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT
+#define BF_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT_V(e)   BF_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT(BV_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT__##e)
+#define BFM_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT_V(v)  BM_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT
+
+#define HW_DIGCTL_L1_AHB_DATA_STALLED               HW(DIGCTL_L1_AHB_DATA_STALLED)
+#define HWA_DIGCTL_L1_AHB_DATA_STALLED              (0x8001c000 + 0x380)
+#define HWT_DIGCTL_L1_AHB_DATA_STALLED              HWIO_32_RW
+#define HWN_DIGCTL_L1_AHB_DATA_STALLED              DIGCTL_L1_AHB_DATA_STALLED
+#define HWI_DIGCTL_L1_AHB_DATA_STALLED              
+#define BP_DIGCTL_L1_AHB_DATA_STALLED_COUNT         0
+#define BM_DIGCTL_L1_AHB_DATA_STALLED_COUNT         0xffffffff
+#define BF_DIGCTL_L1_AHB_DATA_STALLED_COUNT(v)      (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_L1_AHB_DATA_STALLED_COUNT(v)     BM_DIGCTL_L1_AHB_DATA_STALLED_COUNT
+#define BF_DIGCTL_L1_AHB_DATA_STALLED_COUNT_V(e)    BF_DIGCTL_L1_AHB_DATA_STALLED_COUNT(BV_DIGCTL_L1_AHB_DATA_STALLED_COUNT__##e)
+#define BFM_DIGCTL_L1_AHB_DATA_STALLED_COUNT_V(v)   BM_DIGCTL_L1_AHB_DATA_STALLED_COUNT
+
+#define HW_DIGCTL_L1_AHB_DATA_CYCLES                HW(DIGCTL_L1_AHB_DATA_CYCLES)
+#define HWA_DIGCTL_L1_AHB_DATA_CYCLES               (0x8001c000 + 0x390)
+#define HWT_DIGCTL_L1_AHB_DATA_CYCLES               HWIO_32_RW
+#define HWN_DIGCTL_L1_AHB_DATA_CYCLES               DIGCTL_L1_AHB_DATA_CYCLES
+#define HWI_DIGCTL_L1_AHB_DATA_CYCLES               
+#define BP_DIGCTL_L1_AHB_DATA_CYCLES_COUNT          0
+#define BM_DIGCTL_L1_AHB_DATA_CYCLES_COUNT          0xffffffff
+#define BF_DIGCTL_L1_AHB_DATA_CYCLES_COUNT(v)       (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_L1_AHB_DATA_CYCLES_COUNT(v)      BM_DIGCTL_L1_AHB_DATA_CYCLES_COUNT
+#define BF_DIGCTL_L1_AHB_DATA_CYCLES_COUNT_V(e)     BF_DIGCTL_L1_AHB_DATA_CYCLES_COUNT(BV_DIGCTL_L1_AHB_DATA_CYCLES_COUNT__##e)
+#define BFM_DIGCTL_L1_AHB_DATA_CYCLES_COUNT_V(v)    BM_DIGCTL_L1_AHB_DATA_CYCLES_COUNT
+
+#define HW_DIGCTL_L2_AHB_ACTIVE_CYCLES              HW(DIGCTL_L2_AHB_ACTIVE_CYCLES)
+#define HWA_DIGCTL_L2_AHB_ACTIVE_CYCLES             (0x8001c000 + 0x3a0)
+#define HWT_DIGCTL_L2_AHB_ACTIVE_CYCLES             HWIO_32_RW
+#define HWN_DIGCTL_L2_AHB_ACTIVE_CYCLES             DIGCTL_L2_AHB_ACTIVE_CYCLES
+#define HWI_DIGCTL_L2_AHB_ACTIVE_CYCLES             
+#define BP_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT        0
+#define BM_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT        0xffffffff
+#define BF_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT(v)     (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT(v)    BM_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT
+#define BF_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT_V(e)   BF_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT(BV_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT__##e)
+#define BFM_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT_V(v)  BM_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT
+
+#define HW_DIGCTL_L2_AHB_DATA_STALLED               HW(DIGCTL_L2_AHB_DATA_STALLED)
+#define HWA_DIGCTL_L2_AHB_DATA_STALLED              (0x8001c000 + 0x3b0)
+#define HWT_DIGCTL_L2_AHB_DATA_STALLED              HWIO_32_RW
+#define HWN_DIGCTL_L2_AHB_DATA_STALLED              DIGCTL_L2_AHB_DATA_STALLED
+#define HWI_DIGCTL_L2_AHB_DATA_STALLED              
+#define BP_DIGCTL_L2_AHB_DATA_STALLED_COUNT         0
+#define BM_DIGCTL_L2_AHB_DATA_STALLED_COUNT         0xffffffff
+#define BF_DIGCTL_L2_AHB_DATA_STALLED_COUNT(v)      (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_L2_AHB_DATA_STALLED_COUNT(v)     BM_DIGCTL_L2_AHB_DATA_STALLED_COUNT
+#define BF_DIGCTL_L2_AHB_DATA_STALLED_COUNT_V(e)    BF_DIGCTL_L2_AHB_DATA_STALLED_COUNT(BV_DIGCTL_L2_AHB_DATA_STALLED_COUNT__##e)
+#define BFM_DIGCTL_L2_AHB_DATA_STALLED_COUNT_V(v)   BM_DIGCTL_L2_AHB_DATA_STALLED_COUNT
+
+#define HW_DIGCTL_L2_AHB_DATA_CYCLES                HW(DIGCTL_L2_AHB_DATA_CYCLES)
+#define HWA_DIGCTL_L2_AHB_DATA_CYCLES               (0x8001c000 + 0x3c0)
+#define HWT_DIGCTL_L2_AHB_DATA_CYCLES               HWIO_32_RW
+#define HWN_DIGCTL_L2_AHB_DATA_CYCLES               DIGCTL_L2_AHB_DATA_CYCLES
+#define HWI_DIGCTL_L2_AHB_DATA_CYCLES               
+#define BP_DIGCTL_L2_AHB_DATA_CYCLES_COUNT          0
+#define BM_DIGCTL_L2_AHB_DATA_CYCLES_COUNT          0xffffffff
+#define BF_DIGCTL_L2_AHB_DATA_CYCLES_COUNT(v)       (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_L2_AHB_DATA_CYCLES_COUNT(v)      BM_DIGCTL_L2_AHB_DATA_CYCLES_COUNT
+#define BF_DIGCTL_L2_AHB_DATA_CYCLES_COUNT_V(e)     BF_DIGCTL_L2_AHB_DATA_CYCLES_COUNT(BV_DIGCTL_L2_AHB_DATA_CYCLES_COUNT__##e)
+#define BFM_DIGCTL_L2_AHB_DATA_CYCLES_COUNT_V(v)    BM_DIGCTL_L2_AHB_DATA_CYCLES_COUNT
+
+#define HW_DIGCTL_L3_AHB_ACTIVE_CYCLES              HW(DIGCTL_L3_AHB_ACTIVE_CYCLES)
+#define HWA_DIGCTL_L3_AHB_ACTIVE_CYCLES             (0x8001c000 + 0x3d0)
+#define HWT_DIGCTL_L3_AHB_ACTIVE_CYCLES             HWIO_32_RW
+#define HWN_DIGCTL_L3_AHB_ACTIVE_CYCLES             DIGCTL_L3_AHB_ACTIVE_CYCLES
+#define HWI_DIGCTL_L3_AHB_ACTIVE_CYCLES             
+#define BP_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT        0
+#define BM_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT        0xffffffff
+#define BF_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT(v)     (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT(v)    BM_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT
+#define BF_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT_V(e)   BF_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT(BV_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT__##e)
+#define BFM_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT_V(v)  BM_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT
+
+#define HW_DIGCTL_L3_AHB_DATA_STALLED               HW(DIGCTL_L3_AHB_DATA_STALLED)
+#define HWA_DIGCTL_L3_AHB_DATA_STALLED              (0x8001c000 + 0x3e0)
+#define HWT_DIGCTL_L3_AHB_DATA_STALLED              HWIO_32_RW
+#define HWN_DIGCTL_L3_AHB_DATA_STALLED              DIGCTL_L3_AHB_DATA_STALLED
+#define HWI_DIGCTL_L3_AHB_DATA_STALLED              
+#define BP_DIGCTL_L3_AHB_DATA_STALLED_COUNT         0
+#define BM_DIGCTL_L3_AHB_DATA_STALLED_COUNT         0xffffffff
+#define BF_DIGCTL_L3_AHB_DATA_STALLED_COUNT(v)      (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_L3_AHB_DATA_STALLED_COUNT(v)     BM_DIGCTL_L3_AHB_DATA_STALLED_COUNT
+#define BF_DIGCTL_L3_AHB_DATA_STALLED_COUNT_V(e)    BF_DIGCTL_L3_AHB_DATA_STALLED_COUNT(BV_DIGCTL_L3_AHB_DATA_STALLED_COUNT__##e)
+#define BFM_DIGCTL_L3_AHB_DATA_STALLED_COUNT_V(v)   BM_DIGCTL_L3_AHB_DATA_STALLED_COUNT
+
+#define HW_DIGCTL_L3_AHB_DATA_CYCLES                HW(DIGCTL_L3_AHB_DATA_CYCLES)
+#define HWA_DIGCTL_L3_AHB_DATA_CYCLES               (0x8001c000 + 0x3f0)
+#define HWT_DIGCTL_L3_AHB_DATA_CYCLES               HWIO_32_RW
+#define HWN_DIGCTL_L3_AHB_DATA_CYCLES               DIGCTL_L3_AHB_DATA_CYCLES
+#define HWI_DIGCTL_L3_AHB_DATA_CYCLES               
+#define BP_DIGCTL_L3_AHB_DATA_CYCLES_COUNT          0
+#define BM_DIGCTL_L3_AHB_DATA_CYCLES_COUNT          0xffffffff
+#define BF_DIGCTL_L3_AHB_DATA_CYCLES_COUNT(v)       (((v) & 0xffffffff) << 0)
+#define BFM_DIGCTL_L3_AHB_DATA_CYCLES_COUNT(v)      BM_DIGCTL_L3_AHB_DATA_CYCLES_COUNT
+#define BF_DIGCTL_L3_AHB_DATA_CYCLES_COUNT_V(e)     BF_DIGCTL_L3_AHB_DATA_CYCLES_COUNT(BV_DIGCTL_L3_AHB_DATA_CYCLES_COUNT__##e)
+#define BFM_DIGCTL_L3_AHB_DATA_CYCLES_COUNT_V(v)    BM_DIGCTL_L3_AHB_DATA_CYCLES_COUNT
+
+#define HW_DIGCTL_MPTEn_LOC(_n1)        HW(DIGCTL_MPTEn_LOC(_n1))
+#define HWA_DIGCTL_MPTEn_LOC(_n1)       (0x8001c000 + 0x400 + (_n1) * 0x10)
+#define HWT_DIGCTL_MPTEn_LOC(_n1)       HWIO_32_RW
+#define HWN_DIGCTL_MPTEn_LOC(_n1)       DIGCTL_MPTEn_LOC
+#define HWI_DIGCTL_MPTEn_LOC(_n1)       (_n1)
+#define BP_DIGCTL_MPTEn_LOC_LOC         0
+#define BM_DIGCTL_MPTEn_LOC_LOC         0xfff
+#define BF_DIGCTL_MPTEn_LOC_LOC(v)      (((v) & 0xfff) << 0)
+#define BFM_DIGCTL_MPTEn_LOC_LOC(v)     BM_DIGCTL_MPTEn_LOC_LOC
+#define BF_DIGCTL_MPTEn_LOC_LOC_V(e)    BF_DIGCTL_MPTEn_LOC_LOC(BV_DIGCTL_MPTEn_LOC_LOC__##e)
+#define BFM_DIGCTL_MPTEn_LOC_LOC_V(v)   BM_DIGCTL_MPTEn_LOC_LOC
+
+#define HW_DIGCTL_EMICLK_DELAY                  HW(DIGCTL_EMICLK_DELAY)
+#define HWA_DIGCTL_EMICLK_DELAY                 (0x8001c000 + 0x480)
+#define HWT_DIGCTL_EMICLK_DELAY                 HWIO_32_RW
+#define HWN_DIGCTL_EMICLK_DELAY                 DIGCTL_EMICLK_DELAY
+#define HWI_DIGCTL_EMICLK_DELAY                 
+#define BP_DIGCTL_EMICLK_DELAY_NUM_TAPS         0
+#define BM_DIGCTL_EMICLK_DELAY_NUM_TAPS         0x1f
+#define BF_DIGCTL_EMICLK_DELAY_NUM_TAPS(v)      (((v) & 0x1f) << 0)
+#define BFM_DIGCTL_EMICLK_DELAY_NUM_TAPS(v)     BM_DIGCTL_EMICLK_DELAY_NUM_TAPS
+#define BF_DIGCTL_EMICLK_DELAY_NUM_TAPS_V(e)    BF_DIGCTL_EMICLK_DELAY_NUM_TAPS(BV_DIGCTL_EMICLK_DELAY_NUM_TAPS__##e)
+#define BFM_DIGCTL_EMICLK_DELAY_NUM_TAPS_V(v)   BM_DIGCTL_EMICLK_DELAY_NUM_TAPS
+
+#endif /* __HEADERGEN_STMP3700_DIGCTL_H__*/
diff --git a/firmware/target/arm/imx233/regs/stmp3700/dram.h b/firmware/target/arm/imx233/regs/stmp3700/dram.h
new file mode 100644
index 0000000000..86ad47905e
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3700/dram.h
@@ -0,0 +1,981 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * stmp3700 version: 2.4.0
+ * stmp3700 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_STMP3700_DRAM_H__
+#define __HEADERGEN_STMP3700_DRAM_H__
+
+#define HW_DRAM_CTL00                           HW(DRAM_CTL00)
+#define HWA_DRAM_CTL00                          (0x800e0000 + 0x0)
+#define HWT_DRAM_CTL00                          HWIO_32_RW
+#define HWN_DRAM_CTL00                          DRAM_CTL00
+#define HWI_DRAM_CTL00                          
+#define BP_DRAM_CTL00_AHB0_W_PRIORITY           24
+#define BM_DRAM_CTL00_AHB0_W_PRIORITY           0x1000000
+#define BF_DRAM_CTL00_AHB0_W_PRIORITY(v)        (((v) & 0x1) << 24)
+#define BFM_DRAM_CTL00_AHB0_W_PRIORITY(v)       BM_DRAM_CTL00_AHB0_W_PRIORITY
+#define BF_DRAM_CTL00_AHB0_W_PRIORITY_V(e)      BF_DRAM_CTL00_AHB0_W_PRIORITY(BV_DRAM_CTL00_AHB0_W_PRIORITY__##e)
+#define BFM_DRAM_CTL00_AHB0_W_PRIORITY_V(v)     BM_DRAM_CTL00_AHB0_W_PRIORITY
+#define BP_DRAM_CTL00_AHB0_R_PRIORITY           16
+#define BM_DRAM_CTL00_AHB0_R_PRIORITY           0x10000
+#define BF_DRAM_CTL00_AHB0_R_PRIORITY(v)        (((v) & 0x1) << 16)
+#define BFM_DRAM_CTL00_AHB0_R_PRIORITY(v)       BM_DRAM_CTL00_AHB0_R_PRIORITY
+#define BF_DRAM_CTL00_AHB0_R_PRIORITY_V(e)      BF_DRAM_CTL00_AHB0_R_PRIORITY(BV_DRAM_CTL00_AHB0_R_PRIORITY__##e)
+#define BFM_DRAM_CTL00_AHB0_R_PRIORITY_V(v)     BM_DRAM_CTL00_AHB0_R_PRIORITY
+#define BP_DRAM_CTL00_AHB0_FIFO_TYPE_REG        8
+#define BM_DRAM_CTL00_AHB0_FIFO_TYPE_REG        0x100
+#define BF_DRAM_CTL00_AHB0_FIFO_TYPE_REG(v)     (((v) & 0x1) << 8)
+#define BFM_DRAM_CTL00_AHB0_FIFO_TYPE_REG(v)    BM_DRAM_CTL00_AHB0_FIFO_TYPE_REG
+#define BF_DRAM_CTL00_AHB0_FIFO_TYPE_REG_V(e)   BF_DRAM_CTL00_AHB0_FIFO_TYPE_REG(BV_DRAM_CTL00_AHB0_FIFO_TYPE_REG__##e)
+#define BFM_DRAM_CTL00_AHB0_FIFO_TYPE_REG_V(v)  BM_DRAM_CTL00_AHB0_FIFO_TYPE_REG
+#define BP_DRAM_CTL00_ADDR_CMP_EN               0
+#define BM_DRAM_CTL00_ADDR_CMP_EN               0x1
+#define BF_DRAM_CTL00_ADDR_CMP_EN(v)            (((v) & 0x1) << 0)
+#define BFM_DRAM_CTL00_ADDR_CMP_EN(v)           BM_DRAM_CTL00_ADDR_CMP_EN
+#define BF_DRAM_CTL00_ADDR_CMP_EN_V(e)          BF_DRAM_CTL00_ADDR_CMP_EN(BV_DRAM_CTL00_ADDR_CMP_EN__##e)
+#define BFM_DRAM_CTL00_ADDR_CMP_EN_V(v)         BM_DRAM_CTL00_ADDR_CMP_EN
+
+#define HW_DRAM_CTL01                           HW(DRAM_CTL01)
+#define HWA_DRAM_CTL01                          (0x800e0000 + 0x4)
+#define HWT_DRAM_CTL01                          HWIO_32_RW
+#define HWN_DRAM_CTL01                          DRAM_CTL01
+#define HWI_DRAM_CTL01                          
+#define BP_DRAM_CTL01_AHB2_FIFO_TYPE_REG        24
+#define BM_DRAM_CTL01_AHB2_FIFO_TYPE_REG        0x1000000
+#define BF_DRAM_CTL01_AHB2_FIFO_TYPE_REG(v)     (((v) & 0x1) << 24)
+#define BFM_DRAM_CTL01_AHB2_FIFO_TYPE_REG(v)    BM_DRAM_CTL01_AHB2_FIFO_TYPE_REG
+#define BF_DRAM_CTL01_AHB2_FIFO_TYPE_REG_V(e)   BF_DRAM_CTL01_AHB2_FIFO_TYPE_REG(BV_DRAM_CTL01_AHB2_FIFO_TYPE_REG__##e)
+#define BFM_DRAM_CTL01_AHB2_FIFO_TYPE_REG_V(v)  BM_DRAM_CTL01_AHB2_FIFO_TYPE_REG
+#define BP_DRAM_CTL01_AHB1_W_PRIORITY           16
+#define BM_DRAM_CTL01_AHB1_W_PRIORITY           0x10000
+#define BF_DRAM_CTL01_AHB1_W_PRIORITY(v)        (((v) & 0x1) << 16)
+#define BFM_DRAM_CTL01_AHB1_W_PRIORITY(v)       BM_DRAM_CTL01_AHB1_W_PRIORITY
+#define BF_DRAM_CTL01_AHB1_W_PRIORITY_V(e)      BF_DRAM_CTL01_AHB1_W_PRIORITY(BV_DRAM_CTL01_AHB1_W_PRIORITY__##e)
+#define BFM_DRAM_CTL01_AHB1_W_PRIORITY_V(v)     BM_DRAM_CTL01_AHB1_W_PRIORITY
+#define BP_DRAM_CTL01_AHB1_R_PRIORITY           8
+#define BM_DRAM_CTL01_AHB1_R_PRIORITY           0x100
+#define BF_DRAM_CTL01_AHB1_R_PRIORITY(v)        (((v) & 0x1) << 8)
+#define BFM_DRAM_CTL01_AHB1_R_PRIORITY(v)       BM_DRAM_CTL01_AHB1_R_PRIORITY
+#define BF_DRAM_CTL01_AHB1_R_PRIORITY_V(e)      BF_DRAM_CTL01_AHB1_R_PRIORITY(BV_DRAM_CTL01_AHB1_R_PRIORITY__##e)
+#define BFM_DRAM_CTL01_AHB1_R_PRIORITY_V(v)     BM_DRAM_CTL01_AHB1_R_PRIORITY
+#define BP_DRAM_CTL01_AHB1_FIFO_TYPE_REG        0
+#define BM_DRAM_CTL01_AHB1_FIFO_TYPE_REG        0x1
+#define BF_DRAM_CTL01_AHB1_FIFO_TYPE_REG(v)     (((v) & 0x1) << 0)
+#define BFM_DRAM_CTL01_AHB1_FIFO_TYPE_REG(v)    BM_DRAM_CTL01_AHB1_FIFO_TYPE_REG
+#define BF_DRAM_CTL01_AHB1_FIFO_TYPE_REG_V(e)   BF_DRAM_CTL01_AHB1_FIFO_TYPE_REG(BV_DRAM_CTL01_AHB1_FIFO_TYPE_REG__##e)
+#define BFM_DRAM_CTL01_AHB1_FIFO_TYPE_REG_V(v)  BM_DRAM_CTL01_AHB1_FIFO_TYPE_REG
+
+#define HW_DRAM_CTL02                           HW(DRAM_CTL02)
+#define HWA_DRAM_CTL02                          (0x800e0000 + 0x8)
+#define HWT_DRAM_CTL02                          HWIO_32_RW
+#define HWN_DRAM_CTL02                          DRAM_CTL02
+#define HWI_DRAM_CTL02                          
+#define BP_DRAM_CTL02_AHB3_R_PRIORITY           24
+#define BM_DRAM_CTL02_AHB3_R_PRIORITY           0x1000000
+#define BF_DRAM_CTL02_AHB3_R_PRIORITY(v)        (((v) & 0x1) << 24)
+#define BFM_DRAM_CTL02_AHB3_R_PRIORITY(v)       BM_DRAM_CTL02_AHB3_R_PRIORITY
+#define BF_DRAM_CTL02_AHB3_R_PRIORITY_V(e)      BF_DRAM_CTL02_AHB3_R_PRIORITY(BV_DRAM_CTL02_AHB3_R_PRIORITY__##e)
+#define BFM_DRAM_CTL02_AHB3_R_PRIORITY_V(v)     BM_DRAM_CTL02_AHB3_R_PRIORITY
+#define BP_DRAM_CTL02_AHB3_FIFO_TYPE_REG        16
+#define BM_DRAM_CTL02_AHB3_FIFO_TYPE_REG        0x10000
+#define BF_DRAM_CTL02_AHB3_FIFO_TYPE_REG(v)     (((v) & 0x1) << 16)
+#define BFM_DRAM_CTL02_AHB3_FIFO_TYPE_REG(v)    BM_DRAM_CTL02_AHB3_FIFO_TYPE_REG
+#define BF_DRAM_CTL02_AHB3_FIFO_TYPE_REG_V(e)   BF_DRAM_CTL02_AHB3_FIFO_TYPE_REG(BV_DRAM_CTL02_AHB3_FIFO_TYPE_REG__##e)
+#define BFM_DRAM_CTL02_AHB3_FIFO_TYPE_REG_V(v)  BM_DRAM_CTL02_AHB3_FIFO_TYPE_REG
+#define BP_DRAM_CTL02_AHB2_W_PRIORITY           8
+#define BM_DRAM_CTL02_AHB2_W_PRIORITY           0x100
+#define BF_DRAM_CTL02_AHB2_W_PRIORITY(v)        (((v) & 0x1) << 8)
+#define BFM_DRAM_CTL02_AHB2_W_PRIORITY(v)       BM_DRAM_CTL02_AHB2_W_PRIORITY
+#define BF_DRAM_CTL02_AHB2_W_PRIORITY_V(e)      BF_DRAM_CTL02_AHB2_W_PRIORITY(BV_DRAM_CTL02_AHB2_W_PRIORITY__##e)
+#define BFM_DRAM_CTL02_AHB2_W_PRIORITY_V(v)     BM_DRAM_CTL02_AHB2_W_PRIORITY
+#define BP_DRAM_CTL02_AHB2_R_PRIORITY           0
+#define BM_DRAM_CTL02_AHB2_R_PRIORITY           0x1
+#define BF_DRAM_CTL02_AHB2_R_PRIORITY(v)        (((v) & 0x1) << 0)
+#define BFM_DRAM_CTL02_AHB2_R_PRIORITY(v)       BM_DRAM_CTL02_AHB2_R_PRIORITY
+#define BF_DRAM_CTL02_AHB2_R_PRIORITY_V(e)      BF_DRAM_CTL02_AHB2_R_PRIORITY(BV_DRAM_CTL02_AHB2_R_PRIORITY__##e)
+#define BFM_DRAM_CTL02_AHB2_R_PRIORITY_V(v)     BM_DRAM_CTL02_AHB2_R_PRIORITY
+
+#define HW_DRAM_CTL03                           HW(DRAM_CTL03)
+#define HWA_DRAM_CTL03                          (0x800e0000 + 0xc)
+#define HWT_DRAM_CTL03                          HWIO_32_RW
+#define HWN_DRAM_CTL03                          DRAM_CTL03
+#define HWI_DRAM_CTL03                          
+#define BP_DRAM_CTL03_AUTO_REFRESH_MODE         24
+#define BM_DRAM_CTL03_AUTO_REFRESH_MODE         0x1000000
+#define BF_DRAM_CTL03_AUTO_REFRESH_MODE(v)      (((v) & 0x1) << 24)
+#define BFM_DRAM_CTL03_AUTO_REFRESH_MODE(v)     BM_DRAM_CTL03_AUTO_REFRESH_MODE
+#define BF_DRAM_CTL03_AUTO_REFRESH_MODE_V(e)    BF_DRAM_CTL03_AUTO_REFRESH_MODE(BV_DRAM_CTL03_AUTO_REFRESH_MODE__##e)
+#define BFM_DRAM_CTL03_AUTO_REFRESH_MODE_V(v)   BM_DRAM_CTL03_AUTO_REFRESH_MODE
+#define BP_DRAM_CTL03_AREFRESH                  16
+#define BM_DRAM_CTL03_AREFRESH                  0x10000
+#define BF_DRAM_CTL03_AREFRESH(v)               (((v) & 0x1) << 16)
+#define BFM_DRAM_CTL03_AREFRESH(v)              BM_DRAM_CTL03_AREFRESH
+#define BF_DRAM_CTL03_AREFRESH_V(e)             BF_DRAM_CTL03_AREFRESH(BV_DRAM_CTL03_AREFRESH__##e)
+#define BFM_DRAM_CTL03_AREFRESH_V(v)            BM_DRAM_CTL03_AREFRESH
+#define BP_DRAM_CTL03_AP                        8
+#define BM_DRAM_CTL03_AP                        0x100
+#define BF_DRAM_CTL03_AP(v)                     (((v) & 0x1) << 8)
+#define BFM_DRAM_CTL03_AP(v)                    BM_DRAM_CTL03_AP
+#define BF_DRAM_CTL03_AP_V(e)                   BF_DRAM_CTL03_AP(BV_DRAM_CTL03_AP__##e)
+#define BFM_DRAM_CTL03_AP_V(v)                  BM_DRAM_CTL03_AP
+#define BP_DRAM_CTL03_AHB3_W_PRIORITY           0
+#define BM_DRAM_CTL03_AHB3_W_PRIORITY           0x1
+#define BF_DRAM_CTL03_AHB3_W_PRIORITY(v)        (((v) & 0x1) << 0)
+#define BFM_DRAM_CTL03_AHB3_W_PRIORITY(v)       BM_DRAM_CTL03_AHB3_W_PRIORITY
+#define BF_DRAM_CTL03_AHB3_W_PRIORITY_V(e)      BF_DRAM_CTL03_AHB3_W_PRIORITY(BV_DRAM_CTL03_AHB3_W_PRIORITY__##e)
+#define BFM_DRAM_CTL03_AHB3_W_PRIORITY_V(v)     BM_DRAM_CTL03_AHB3_W_PRIORITY
+
+#define HW_DRAM_CTL04                       HW(DRAM_CTL04)
+#define HWA_DRAM_CTL04                      (0x800e0000 + 0x10)
+#define HWT_DRAM_CTL04                      HWIO_32_RW
+#define HWN_DRAM_CTL04                      DRAM_CTL04
+#define HWI_DRAM_CTL04                      
+#define BP_DRAM_CTL04_DLL_BYPASS_MODE       24
+#define BM_DRAM_CTL04_DLL_BYPASS_MODE       0x1000000
+#define BF_DRAM_CTL04_DLL_BYPASS_MODE(v)    (((v) & 0x1) << 24)
+#define BFM_DRAM_CTL04_DLL_BYPASS_MODE(v)   BM_DRAM_CTL04_DLL_BYPASS_MODE
+#define BF_DRAM_CTL04_DLL_BYPASS_MODE_V(e)  BF_DRAM_CTL04_DLL_BYPASS_MODE(BV_DRAM_CTL04_DLL_BYPASS_MODE__##e)
+#define BFM_DRAM_CTL04_DLL_BYPASS_MODE_V(v) BM_DRAM_CTL04_DLL_BYPASS_MODE
+#define BP_DRAM_CTL04_DLLLOCKREG            16
+#define BM_DRAM_CTL04_DLLLOCKREG            0x10000
+#define BF_DRAM_CTL04_DLLLOCKREG(v)         (((v) & 0x1) << 16)
+#define BFM_DRAM_CTL04_DLLLOCKREG(v)        BM_DRAM_CTL04_DLLLOCKREG
+#define BF_DRAM_CTL04_DLLLOCKREG_V(e)       BF_DRAM_CTL04_DLLLOCKREG(BV_DRAM_CTL04_DLLLOCKREG__##e)
+#define BFM_DRAM_CTL04_DLLLOCKREG_V(v)      BM_DRAM_CTL04_DLLLOCKREG
+#define BP_DRAM_CTL04_CONCURRENTAP          8
+#define BM_DRAM_CTL04_CONCURRENTAP          0x100
+#define BF_DRAM_CTL04_CONCURRENTAP(v)       (((v) & 0x1) << 8)
+#define BFM_DRAM_CTL04_CONCURRENTAP(v)      BM_DRAM_CTL04_CONCURRENTAP
+#define BF_DRAM_CTL04_CONCURRENTAP_V(e)     BF_DRAM_CTL04_CONCURRENTAP(BV_DRAM_CTL04_CONCURRENTAP__##e)
+#define BFM_DRAM_CTL04_CONCURRENTAP_V(v)    BM_DRAM_CTL04_CONCURRENTAP
+#define BP_DRAM_CTL04_BANK_SPLIT_EN         0
+#define BM_DRAM_CTL04_BANK_SPLIT_EN         0x1
+#define BF_DRAM_CTL04_BANK_SPLIT_EN(v)      (((v) & 0x1) << 0)
+#define BFM_DRAM_CTL04_BANK_SPLIT_EN(v)     BM_DRAM_CTL04_BANK_SPLIT_EN
+#define BF_DRAM_CTL04_BANK_SPLIT_EN_V(e)    BF_DRAM_CTL04_BANK_SPLIT_EN(BV_DRAM_CTL04_BANK_SPLIT_EN__##e)
+#define BFM_DRAM_CTL04_BANK_SPLIT_EN_V(v)   BM_DRAM_CTL04_BANK_SPLIT_EN
+
+#define HW_DRAM_CTL05                           HW(DRAM_CTL05)
+#define HWA_DRAM_CTL05                          (0x800e0000 + 0x14)
+#define HWT_DRAM_CTL05                          HWIO_32_RW
+#define HWN_DRAM_CTL05                          DRAM_CTL05
+#define HWI_DRAM_CTL05                          
+#define BP_DRAM_CTL05_INTRPTREADA               24
+#define BM_DRAM_CTL05_INTRPTREADA               0x1000000
+#define BF_DRAM_CTL05_INTRPTREADA(v)            (((v) & 0x1) << 24)
+#define BFM_DRAM_CTL05_INTRPTREADA(v)           BM_DRAM_CTL05_INTRPTREADA
+#define BF_DRAM_CTL05_INTRPTREADA_V(e)          BF_DRAM_CTL05_INTRPTREADA(BV_DRAM_CTL05_INTRPTREADA__##e)
+#define BFM_DRAM_CTL05_INTRPTREADA_V(v)         BM_DRAM_CTL05_INTRPTREADA
+#define BP_DRAM_CTL05_INTRPTAPBURST             16
+#define BM_DRAM_CTL05_INTRPTAPBURST             0x10000
+#define BF_DRAM_CTL05_INTRPTAPBURST(v)          (((v) & 0x1) << 16)
+#define BFM_DRAM_CTL05_INTRPTAPBURST(v)         BM_DRAM_CTL05_INTRPTAPBURST
+#define BF_DRAM_CTL05_INTRPTAPBURST_V(e)        BF_DRAM_CTL05_INTRPTAPBURST(BV_DRAM_CTL05_INTRPTAPBURST__##e)
+#define BFM_DRAM_CTL05_INTRPTAPBURST_V(v)       BM_DRAM_CTL05_INTRPTAPBURST
+#define BP_DRAM_CTL05_FAST_WRITE                8
+#define BM_DRAM_CTL05_FAST_WRITE                0x100
+#define BF_DRAM_CTL05_FAST_WRITE(v)             (((v) & 0x1) << 8)
+#define BFM_DRAM_CTL05_FAST_WRITE(v)            BM_DRAM_CTL05_FAST_WRITE
+#define BF_DRAM_CTL05_FAST_WRITE_V(e)           BF_DRAM_CTL05_FAST_WRITE(BV_DRAM_CTL05_FAST_WRITE__##e)
+#define BFM_DRAM_CTL05_FAST_WRITE_V(v)          BM_DRAM_CTL05_FAST_WRITE
+#define BP_DRAM_CTL05_EN_LOWPOWER_MODE          0
+#define BM_DRAM_CTL05_EN_LOWPOWER_MODE          0x1
+#define BF_DRAM_CTL05_EN_LOWPOWER_MODE(v)       (((v) & 0x1) << 0)
+#define BFM_DRAM_CTL05_EN_LOWPOWER_MODE(v)      BM_DRAM_CTL05_EN_LOWPOWER_MODE
+#define BF_DRAM_CTL05_EN_LOWPOWER_MODE_V(e)     BF_DRAM_CTL05_EN_LOWPOWER_MODE(BV_DRAM_CTL05_EN_LOWPOWER_MODE__##e)
+#define BFM_DRAM_CTL05_EN_LOWPOWER_MODE_V(v)    BM_DRAM_CTL05_EN_LOWPOWER_MODE
+
+#define HW_DRAM_CTL06                       HW(DRAM_CTL06)
+#define HWA_DRAM_CTL06                      (0x800e0000 + 0x18)
+#define HWT_DRAM_CTL06                      HWIO_32_RW
+#define HWN_DRAM_CTL06                      DRAM_CTL06
+#define HWI_DRAM_CTL06                      
+#define BP_DRAM_CTL06_POWER_DOWN            24
+#define BM_DRAM_CTL06_POWER_DOWN            0x1000000
+#define BF_DRAM_CTL06_POWER_DOWN(v)         (((v) & 0x1) << 24)
+#define BFM_DRAM_CTL06_POWER_DOWN(v)        BM_DRAM_CTL06_POWER_DOWN
+#define BF_DRAM_CTL06_POWER_DOWN_V(e)       BF_DRAM_CTL06_POWER_DOWN(BV_DRAM_CTL06_POWER_DOWN__##e)
+#define BFM_DRAM_CTL06_POWER_DOWN_V(v)      BM_DRAM_CTL06_POWER_DOWN
+#define BP_DRAM_CTL06_PLACEMENT_EN          16
+#define BM_DRAM_CTL06_PLACEMENT_EN          0x10000
+#define BF_DRAM_CTL06_PLACEMENT_EN(v)       (((v) & 0x1) << 16)
+#define BFM_DRAM_CTL06_PLACEMENT_EN(v)      BM_DRAM_CTL06_PLACEMENT_EN
+#define BF_DRAM_CTL06_PLACEMENT_EN_V(e)     BF_DRAM_CTL06_PLACEMENT_EN(BV_DRAM_CTL06_PLACEMENT_EN__##e)
+#define BFM_DRAM_CTL06_PLACEMENT_EN_V(v)    BM_DRAM_CTL06_PLACEMENT_EN
+#define BP_DRAM_CTL06_NO_CMD_INIT           8
+#define BM_DRAM_CTL06_NO_CMD_INIT           0x100
+#define BF_DRAM_CTL06_NO_CMD_INIT(v)        (((v) & 0x1) << 8)
+#define BFM_DRAM_CTL06_NO_CMD_INIT(v)       BM_DRAM_CTL06_NO_CMD_INIT
+#define BF_DRAM_CTL06_NO_CMD_INIT_V(e)      BF_DRAM_CTL06_NO_CMD_INIT(BV_DRAM_CTL06_NO_CMD_INIT__##e)
+#define BFM_DRAM_CTL06_NO_CMD_INIT_V(v)     BM_DRAM_CTL06_NO_CMD_INIT
+#define BP_DRAM_CTL06_INTRPTWRITEA          0
+#define BM_DRAM_CTL06_INTRPTWRITEA          0x1
+#define BF_DRAM_CTL06_INTRPTWRITEA(v)       (((v) & 0x1) << 0)
+#define BFM_DRAM_CTL06_INTRPTWRITEA(v)      BM_DRAM_CTL06_INTRPTWRITEA
+#define BF_DRAM_CTL06_INTRPTWRITEA_V(e)     BF_DRAM_CTL06_INTRPTWRITEA(BV_DRAM_CTL06_INTRPTWRITEA__##e)
+#define BFM_DRAM_CTL06_INTRPTWRITEA_V(v)    BM_DRAM_CTL06_INTRPTWRITEA
+
+#define HW_DRAM_CTL07                       HW(DRAM_CTL07)
+#define HWA_DRAM_CTL07                      (0x800e0000 + 0x1c)
+#define HWT_DRAM_CTL07                      HWIO_32_RW
+#define HWN_DRAM_CTL07                      DRAM_CTL07
+#define HWI_DRAM_CTL07                      
+#define BP_DRAM_CTL07_RW_SAME_EN            24
+#define BM_DRAM_CTL07_RW_SAME_EN            0x1000000
+#define BF_DRAM_CTL07_RW_SAME_EN(v)         (((v) & 0x1) << 24)
+#define BFM_DRAM_CTL07_RW_SAME_EN(v)        BM_DRAM_CTL07_RW_SAME_EN
+#define BF_DRAM_CTL07_RW_SAME_EN_V(e)       BF_DRAM_CTL07_RW_SAME_EN(BV_DRAM_CTL07_RW_SAME_EN__##e)
+#define BFM_DRAM_CTL07_RW_SAME_EN_V(v)      BM_DRAM_CTL07_RW_SAME_EN
+#define BP_DRAM_CTL07_REG_DIMM_ENABLE       16
+#define BM_DRAM_CTL07_REG_DIMM_ENABLE       0x10000
+#define BF_DRAM_CTL07_REG_DIMM_ENABLE(v)    (((v) & 0x1) << 16)
+#define BFM_DRAM_CTL07_REG_DIMM_ENABLE(v)   BM_DRAM_CTL07_REG_DIMM_ENABLE
+#define BF_DRAM_CTL07_REG_DIMM_ENABLE_V(e)  BF_DRAM_CTL07_REG_DIMM_ENABLE(BV_DRAM_CTL07_REG_DIMM_ENABLE__##e)
+#define BFM_DRAM_CTL07_REG_DIMM_ENABLE_V(v) BM_DRAM_CTL07_REG_DIMM_ENABLE
+#define BP_DRAM_CTL07_RD2RD_TURN            8
+#define BM_DRAM_CTL07_RD2RD_TURN            0x100
+#define BF_DRAM_CTL07_RD2RD_TURN(v)         (((v) & 0x1) << 8)
+#define BFM_DRAM_CTL07_RD2RD_TURN(v)        BM_DRAM_CTL07_RD2RD_TURN
+#define BF_DRAM_CTL07_RD2RD_TURN_V(e)       BF_DRAM_CTL07_RD2RD_TURN(BV_DRAM_CTL07_RD2RD_TURN__##e)
+#define BFM_DRAM_CTL07_RD2RD_TURN_V(v)      BM_DRAM_CTL07_RD2RD_TURN
+#define BP_DRAM_CTL07_PRIORITY_EN           0
+#define BM_DRAM_CTL07_PRIORITY_EN           0x1
+#define BF_DRAM_CTL07_PRIORITY_EN(v)        (((v) & 0x1) << 0)
+#define BFM_DRAM_CTL07_PRIORITY_EN(v)       BM_DRAM_CTL07_PRIORITY_EN
+#define BF_DRAM_CTL07_PRIORITY_EN_V(e)      BF_DRAM_CTL07_PRIORITY_EN(BV_DRAM_CTL07_PRIORITY_EN__##e)
+#define BFM_DRAM_CTL07_PRIORITY_EN_V(v)     BM_DRAM_CTL07_PRIORITY_EN
+
+#define HW_DRAM_CTL08                       HW(DRAM_CTL08)
+#define HWA_DRAM_CTL08                      (0x800e0000 + 0x20)
+#define HWT_DRAM_CTL08                      HWIO_32_RW
+#define HWN_DRAM_CTL08                      DRAM_CTL08
+#define HWI_DRAM_CTL08                      
+#define BP_DRAM_CTL08_TRAS_LOCKOUT          24
+#define BM_DRAM_CTL08_TRAS_LOCKOUT          0x1000000
+#define BF_DRAM_CTL08_TRAS_LOCKOUT(v)       (((v) & 0x1) << 24)
+#define BFM_DRAM_CTL08_TRAS_LOCKOUT(v)      BM_DRAM_CTL08_TRAS_LOCKOUT
+#define BF_DRAM_CTL08_TRAS_LOCKOUT_V(e)     BF_DRAM_CTL08_TRAS_LOCKOUT(BV_DRAM_CTL08_TRAS_LOCKOUT__##e)
+#define BFM_DRAM_CTL08_TRAS_LOCKOUT_V(v)    BM_DRAM_CTL08_TRAS_LOCKOUT
+#define BP_DRAM_CTL08_START                 16
+#define BM_DRAM_CTL08_START                 0x10000
+#define BF_DRAM_CTL08_START(v)              (((v) & 0x1) << 16)
+#define BFM_DRAM_CTL08_START(v)             BM_DRAM_CTL08_START
+#define BF_DRAM_CTL08_START_V(e)            BF_DRAM_CTL08_START(BV_DRAM_CTL08_START__##e)
+#define BFM_DRAM_CTL08_START_V(v)           BM_DRAM_CTL08_START
+#define BP_DRAM_CTL08_SREFRESH              8
+#define BM_DRAM_CTL08_SREFRESH              0x100
+#define BF_DRAM_CTL08_SREFRESH(v)           (((v) & 0x1) << 8)
+#define BFM_DRAM_CTL08_SREFRESH(v)          BM_DRAM_CTL08_SREFRESH
+#define BF_DRAM_CTL08_SREFRESH_V(e)         BF_DRAM_CTL08_SREFRESH(BV_DRAM_CTL08_SREFRESH__##e)
+#define BFM_DRAM_CTL08_SREFRESH_V(v)        BM_DRAM_CTL08_SREFRESH
+#define BP_DRAM_CTL08_SDR_MODE              0
+#define BM_DRAM_CTL08_SDR_MODE              0x1
+#define BF_DRAM_CTL08_SDR_MODE(v)           (((v) & 0x1) << 0)
+#define BFM_DRAM_CTL08_SDR_MODE(v)          BM_DRAM_CTL08_SDR_MODE
+#define BF_DRAM_CTL08_SDR_MODE_V(e)         BF_DRAM_CTL08_SDR_MODE(BV_DRAM_CTL08_SDR_MODE__##e)
+#define BFM_DRAM_CTL08_SDR_MODE_V(v)        BM_DRAM_CTL08_SDR_MODE
+
+#define HW_DRAM_CTL09                               HW(DRAM_CTL09)
+#define HWA_DRAM_CTL09                              (0x800e0000 + 0x24)
+#define HWT_DRAM_CTL09                              HWIO_32_RW
+#define HWN_DRAM_CTL09                              DRAM_CTL09
+#define HWI_DRAM_CTL09                              
+#define BP_DRAM_CTL09_OUT_OF_RANGE_TYPE             24
+#define BM_DRAM_CTL09_OUT_OF_RANGE_TYPE             0x3000000
+#define BF_DRAM_CTL09_OUT_OF_RANGE_TYPE(v)          (((v) & 0x3) << 24)
+#define BFM_DRAM_CTL09_OUT_OF_RANGE_TYPE(v)         BM_DRAM_CTL09_OUT_OF_RANGE_TYPE
+#define BF_DRAM_CTL09_OUT_OF_RANGE_TYPE_V(e)        BF_DRAM_CTL09_OUT_OF_RANGE_TYPE(BV_DRAM_CTL09_OUT_OF_RANGE_TYPE__##e)
+#define BFM_DRAM_CTL09_OUT_OF_RANGE_TYPE_V(v)       BM_DRAM_CTL09_OUT_OF_RANGE_TYPE
+#define BP_DRAM_CTL09_OUT_OF_RANGE_SOURCE_ID        16
+#define BM_DRAM_CTL09_OUT_OF_RANGE_SOURCE_ID        0x30000
+#define BF_DRAM_CTL09_OUT_OF_RANGE_SOURCE_ID(v)     (((v) & 0x3) << 16)
+#define BFM_DRAM_CTL09_OUT_OF_RANGE_SOURCE_ID(v)    BM_DRAM_CTL09_OUT_OF_RANGE_SOURCE_ID
+#define BF_DRAM_CTL09_OUT_OF_RANGE_SOURCE_ID_V(e)   BF_DRAM_CTL09_OUT_OF_RANGE_SOURCE_ID(BV_DRAM_CTL09_OUT_OF_RANGE_SOURCE_ID__##e)
+#define BFM_DRAM_CTL09_OUT_OF_RANGE_SOURCE_ID_V(v)  BM_DRAM_CTL09_OUT_OF_RANGE_SOURCE_ID
+#define BP_DRAM_CTL09_WRITE_MODEREG                 8
+#define BM_DRAM_CTL09_WRITE_MODEREG                 0x100
+#define BF_DRAM_CTL09_WRITE_MODEREG(v)              (((v) & 0x1) << 8)
+#define BFM_DRAM_CTL09_WRITE_MODEREG(v)             BM_DRAM_CTL09_WRITE_MODEREG
+#define BF_DRAM_CTL09_WRITE_MODEREG_V(e)            BF_DRAM_CTL09_WRITE_MODEREG(BV_DRAM_CTL09_WRITE_MODEREG__##e)
+#define BFM_DRAM_CTL09_WRITE_MODEREG_V(v)           BM_DRAM_CTL09_WRITE_MODEREG
+#define BP_DRAM_CTL09_WRITEINTERP                   0
+#define BM_DRAM_CTL09_WRITEINTERP                   0x1
+#define BF_DRAM_CTL09_WRITEINTERP(v)                (((v) & 0x1) << 0)
+#define BFM_DRAM_CTL09_WRITEINTERP(v)               BM_DRAM_CTL09_WRITEINTERP
+#define BF_DRAM_CTL09_WRITEINTERP_V(e)              BF_DRAM_CTL09_WRITEINTERP(BV_DRAM_CTL09_WRITEINTERP__##e)
+#define BFM_DRAM_CTL09_WRITEINTERP_V(v)             BM_DRAM_CTL09_WRITEINTERP
+
+#define HW_DRAM_CTL10                   HW(DRAM_CTL10)
+#define HWA_DRAM_CTL10                  (0x800e0000 + 0x28)
+#define HWT_DRAM_CTL10                  HWIO_32_RW
+#define HWN_DRAM_CTL10                  DRAM_CTL10
+#define HWI_DRAM_CTL10                  
+#define BP_DRAM_CTL10_AGE_COUNT         24
+#define BM_DRAM_CTL10_AGE_COUNT         0x7000000
+#define BF_DRAM_CTL10_AGE_COUNT(v)      (((v) & 0x7) << 24)
+#define BFM_DRAM_CTL10_AGE_COUNT(v)     BM_DRAM_CTL10_AGE_COUNT
+#define BF_DRAM_CTL10_AGE_COUNT_V(e)    BF_DRAM_CTL10_AGE_COUNT(BV_DRAM_CTL10_AGE_COUNT__##e)
+#define BFM_DRAM_CTL10_AGE_COUNT_V(v)   BM_DRAM_CTL10_AGE_COUNT
+#define BP_DRAM_CTL10_ADDR_PINS         16
+#define BM_DRAM_CTL10_ADDR_PINS         0x70000
+#define BF_DRAM_CTL10_ADDR_PINS(v)      (((v) & 0x7) << 16)
+#define BFM_DRAM_CTL10_ADDR_PINS(v)     BM_DRAM_CTL10_ADDR_PINS
+#define BF_DRAM_CTL10_ADDR_PINS_V(e)    BF_DRAM_CTL10_ADDR_PINS(BV_DRAM_CTL10_ADDR_PINS__##e)
+#define BFM_DRAM_CTL10_ADDR_PINS_V(v)   BM_DRAM_CTL10_ADDR_PINS
+#define BP_DRAM_CTL10_TEMRS             8
+#define BM_DRAM_CTL10_TEMRS             0x300
+#define BF_DRAM_CTL10_TEMRS(v)          (((v) & 0x3) << 8)
+#define BFM_DRAM_CTL10_TEMRS(v)         BM_DRAM_CTL10_TEMRS
+#define BF_DRAM_CTL10_TEMRS_V(e)        BF_DRAM_CTL10_TEMRS(BV_DRAM_CTL10_TEMRS__##e)
+#define BFM_DRAM_CTL10_TEMRS_V(v)       BM_DRAM_CTL10_TEMRS
+#define BP_DRAM_CTL10_Q_FULLNESS        0
+#define BM_DRAM_CTL10_Q_FULLNESS        0x3
+#define BF_DRAM_CTL10_Q_FULLNESS(v)     (((v) & 0x3) << 0)
+#define BFM_DRAM_CTL10_Q_FULLNESS(v)    BM_DRAM_CTL10_Q_FULLNESS
+#define BF_DRAM_CTL10_Q_FULLNESS_V(e)   BF_DRAM_CTL10_Q_FULLNESS(BV_DRAM_CTL10_Q_FULLNESS__##e)
+#define BFM_DRAM_CTL10_Q_FULLNESS_V(v)  BM_DRAM_CTL10_Q_FULLNESS
+
+#define HW_DRAM_CTL11                           HW(DRAM_CTL11)
+#define HWA_DRAM_CTL11                          (0x800e0000 + 0x2c)
+#define HWT_DRAM_CTL11                          HWIO_32_RW
+#define HWN_DRAM_CTL11                          DRAM_CTL11
+#define HWI_DRAM_CTL11                          
+#define BP_DRAM_CTL11_MAX_CS_REG                24
+#define BM_DRAM_CTL11_MAX_CS_REG                0x7000000
+#define BF_DRAM_CTL11_MAX_CS_REG(v)             (((v) & 0x7) << 24)
+#define BFM_DRAM_CTL11_MAX_CS_REG(v)            BM_DRAM_CTL11_MAX_CS_REG
+#define BF_DRAM_CTL11_MAX_CS_REG_V(e)           BF_DRAM_CTL11_MAX_CS_REG(BV_DRAM_CTL11_MAX_CS_REG__##e)
+#define BFM_DRAM_CTL11_MAX_CS_REG_V(v)          BM_DRAM_CTL11_MAX_CS_REG
+#define BP_DRAM_CTL11_COMMAND_AGE_COUNT         16
+#define BM_DRAM_CTL11_COMMAND_AGE_COUNT         0x70000
+#define BF_DRAM_CTL11_COMMAND_AGE_COUNT(v)      (((v) & 0x7) << 16)
+#define BFM_DRAM_CTL11_COMMAND_AGE_COUNT(v)     BM_DRAM_CTL11_COMMAND_AGE_COUNT
+#define BF_DRAM_CTL11_COMMAND_AGE_COUNT_V(e)    BF_DRAM_CTL11_COMMAND_AGE_COUNT(BV_DRAM_CTL11_COMMAND_AGE_COUNT__##e)
+#define BFM_DRAM_CTL11_COMMAND_AGE_COUNT_V(v)   BM_DRAM_CTL11_COMMAND_AGE_COUNT
+#define BP_DRAM_CTL11_COLUMN_SIZE               8
+#define BM_DRAM_CTL11_COLUMN_SIZE               0x700
+#define BF_DRAM_CTL11_COLUMN_SIZE(v)            (((v) & 0x7) << 8)
+#define BFM_DRAM_CTL11_COLUMN_SIZE(v)           BM_DRAM_CTL11_COLUMN_SIZE
+#define BF_DRAM_CTL11_COLUMN_SIZE_V(e)          BF_DRAM_CTL11_COLUMN_SIZE(BV_DRAM_CTL11_COLUMN_SIZE__##e)
+#define BFM_DRAM_CTL11_COLUMN_SIZE_V(v)         BM_DRAM_CTL11_COLUMN_SIZE
+#define BP_DRAM_CTL11_CASLAT                    0
+#define BM_DRAM_CTL11_CASLAT                    0x7
+#define BF_DRAM_CTL11_CASLAT(v)                 (((v) & 0x7) << 0)
+#define BFM_DRAM_CTL11_CASLAT(v)                BM_DRAM_CTL11_CASLAT
+#define BF_DRAM_CTL11_CASLAT_V(e)               BF_DRAM_CTL11_CASLAT(BV_DRAM_CTL11_CASLAT__##e)
+#define BFM_DRAM_CTL11_CASLAT_V(v)              BM_DRAM_CTL11_CASLAT
+
+#define HW_DRAM_CTL12               HW(DRAM_CTL12)
+#define HWA_DRAM_CTL12              (0x800e0000 + 0x30)
+#define HWT_DRAM_CTL12              HWIO_32_RW
+#define HWN_DRAM_CTL12              DRAM_CTL12
+#define HWI_DRAM_CTL12              
+#define BP_DRAM_CTL12_TWR_INT       24
+#define BM_DRAM_CTL12_TWR_INT       0x7000000
+#define BF_DRAM_CTL12_TWR_INT(v)    (((v) & 0x7) << 24)
+#define BFM_DRAM_CTL12_TWR_INT(v)   BM_DRAM_CTL12_TWR_INT
+#define BF_DRAM_CTL12_TWR_INT_V(e)  BF_DRAM_CTL12_TWR_INT(BV_DRAM_CTL12_TWR_INT__##e)
+#define BFM_DRAM_CTL12_TWR_INT_V(v) BM_DRAM_CTL12_TWR_INT
+#define BP_DRAM_CTL12_TRRD          16
+#define BM_DRAM_CTL12_TRRD          0x70000
+#define BF_DRAM_CTL12_TRRD(v)       (((v) & 0x7) << 16)
+#define BFM_DRAM_CTL12_TRRD(v)      BM_DRAM_CTL12_TRRD
+#define BF_DRAM_CTL12_TRRD_V(e)     BF_DRAM_CTL12_TRRD(BV_DRAM_CTL12_TRRD__##e)
+#define BFM_DRAM_CTL12_TRRD_V(v)    BM_DRAM_CTL12_TRRD
+#define BP_DRAM_CTL12_TCKE          0
+#define BM_DRAM_CTL12_TCKE          0x7
+#define BF_DRAM_CTL12_TCKE(v)       (((v) & 0x7) << 0)
+#define BFM_DRAM_CTL12_TCKE(v)      BM_DRAM_CTL12_TCKE
+#define BF_DRAM_CTL12_TCKE_V(e)     BF_DRAM_CTL12_TCKE(BV_DRAM_CTL12_TCKE__##e)
+#define BFM_DRAM_CTL12_TCKE_V(v)    BM_DRAM_CTL12_TCKE
+
+#define HW_DRAM_CTL13                       HW(DRAM_CTL13)
+#define HWA_DRAM_CTL13                      (0x800e0000 + 0x34)
+#define HWT_DRAM_CTL13                      HWIO_32_RW
+#define HWN_DRAM_CTL13                      DRAM_CTL13
+#define HWI_DRAM_CTL13                      
+#define BP_DRAM_CTL13_CASLAT_LIN_GATE       24
+#define BM_DRAM_CTL13_CASLAT_LIN_GATE       0xf000000
+#define BF_DRAM_CTL13_CASLAT_LIN_GATE(v)    (((v) & 0xf) << 24)
+#define BFM_DRAM_CTL13_CASLAT_LIN_GATE(v)   BM_DRAM_CTL13_CASLAT_LIN_GATE
+#define BF_DRAM_CTL13_CASLAT_LIN_GATE_V(e)  BF_DRAM_CTL13_CASLAT_LIN_GATE(BV_DRAM_CTL13_CASLAT_LIN_GATE__##e)
+#define BFM_DRAM_CTL13_CASLAT_LIN_GATE_V(v) BM_DRAM_CTL13_CASLAT_LIN_GATE
+#define BP_DRAM_CTL13_CASLAT_LIN            16
+#define BM_DRAM_CTL13_CASLAT_LIN            0xf0000
+#define BF_DRAM_CTL13_CASLAT_LIN(v)         (((v) & 0xf) << 16)
+#define BFM_DRAM_CTL13_CASLAT_LIN(v)        BM_DRAM_CTL13_CASLAT_LIN
+#define BF_DRAM_CTL13_CASLAT_LIN_V(e)       BF_DRAM_CTL13_CASLAT_LIN(BV_DRAM_CTL13_CASLAT_LIN__##e)
+#define BFM_DRAM_CTL13_CASLAT_LIN_V(v)      BM_DRAM_CTL13_CASLAT_LIN
+#define BP_DRAM_CTL13_APREBIT               8
+#define BM_DRAM_CTL13_APREBIT               0xf00
+#define BF_DRAM_CTL13_APREBIT(v)            (((v) & 0xf) << 8)
+#define BFM_DRAM_CTL13_APREBIT(v)           BM_DRAM_CTL13_APREBIT
+#define BF_DRAM_CTL13_APREBIT_V(e)          BF_DRAM_CTL13_APREBIT(BV_DRAM_CTL13_APREBIT__##e)
+#define BFM_DRAM_CTL13_APREBIT_V(v)         BM_DRAM_CTL13_APREBIT
+#define BP_DRAM_CTL13_TWTR                  0
+#define BM_DRAM_CTL13_TWTR                  0x7
+#define BF_DRAM_CTL13_TWTR(v)               (((v) & 0x7) << 0)
+#define BFM_DRAM_CTL13_TWTR(v)              BM_DRAM_CTL13_TWTR
+#define BF_DRAM_CTL13_TWTR_V(e)             BF_DRAM_CTL13_TWTR(BV_DRAM_CTL13_TWTR__##e)
+#define BFM_DRAM_CTL13_TWTR_V(v)            BM_DRAM_CTL13_TWTR
+
+#define HW_DRAM_CTL14                               HW(DRAM_CTL14)
+#define HWA_DRAM_CTL14                              (0x800e0000 + 0x38)
+#define HWT_DRAM_CTL14                              HWIO_32_RW
+#define HWN_DRAM_CTL14                              DRAM_CTL14
+#define HWI_DRAM_CTL14                              
+#define BP_DRAM_CTL14_MAX_COL_REG                   24
+#define BM_DRAM_CTL14_MAX_COL_REG                   0xf000000
+#define BF_DRAM_CTL14_MAX_COL_REG(v)                (((v) & 0xf) << 24)
+#define BFM_DRAM_CTL14_MAX_COL_REG(v)               BM_DRAM_CTL14_MAX_COL_REG
+#define BF_DRAM_CTL14_MAX_COL_REG_V(e)              BF_DRAM_CTL14_MAX_COL_REG(BV_DRAM_CTL14_MAX_COL_REG__##e)
+#define BFM_DRAM_CTL14_MAX_COL_REG_V(v)             BM_DRAM_CTL14_MAX_COL_REG
+#define BP_DRAM_CTL14_LOWPOWER_REFRESH_ENABLE       16
+#define BM_DRAM_CTL14_LOWPOWER_REFRESH_ENABLE       0xf0000
+#define BF_DRAM_CTL14_LOWPOWER_REFRESH_ENABLE(v)    (((v) & 0xf) << 16)
+#define BFM_DRAM_CTL14_LOWPOWER_REFRESH_ENABLE(v)   BM_DRAM_CTL14_LOWPOWER_REFRESH_ENABLE
+#define BF_DRAM_CTL14_LOWPOWER_REFRESH_ENABLE_V(e)  BF_DRAM_CTL14_LOWPOWER_REFRESH_ENABLE(BV_DRAM_CTL14_LOWPOWER_REFRESH_ENABLE__##e)
+#define BFM_DRAM_CTL14_LOWPOWER_REFRESH_ENABLE_V(v) BM_DRAM_CTL14_LOWPOWER_REFRESH_ENABLE
+#define BP_DRAM_CTL14_INITAREF                      8
+#define BM_DRAM_CTL14_INITAREF                      0xf00
+#define BF_DRAM_CTL14_INITAREF(v)                   (((v) & 0xf) << 8)
+#define BFM_DRAM_CTL14_INITAREF(v)                  BM_DRAM_CTL14_INITAREF
+#define BF_DRAM_CTL14_INITAREF_V(e)                 BF_DRAM_CTL14_INITAREF(BV_DRAM_CTL14_INITAREF__##e)
+#define BFM_DRAM_CTL14_INITAREF_V(v)                BM_DRAM_CTL14_INITAREF
+#define BP_DRAM_CTL14_CS_MAP                        0
+#define BM_DRAM_CTL14_CS_MAP                        0xf
+#define BF_DRAM_CTL14_CS_MAP(v)                     (((v) & 0xf) << 0)
+#define BFM_DRAM_CTL14_CS_MAP(v)                    BM_DRAM_CTL14_CS_MAP
+#define BF_DRAM_CTL14_CS_MAP_V(e)                   BF_DRAM_CTL14_CS_MAP(BV_DRAM_CTL14_CS_MAP__##e)
+#define BFM_DRAM_CTL14_CS_MAP_V(v)                  BM_DRAM_CTL14_CS_MAP
+
+#define HW_DRAM_CTL15                   HW(DRAM_CTL15)
+#define HWA_DRAM_CTL15                  (0x800e0000 + 0x3c)
+#define HWT_DRAM_CTL15                  HWIO_32_RW
+#define HWN_DRAM_CTL15                  DRAM_CTL15
+#define HWI_DRAM_CTL15                  
+#define BP_DRAM_CTL15_TRP               24
+#define BM_DRAM_CTL15_TRP               0xf000000
+#define BF_DRAM_CTL15_TRP(v)            (((v) & 0xf) << 24)
+#define BFM_DRAM_CTL15_TRP(v)           BM_DRAM_CTL15_TRP
+#define BF_DRAM_CTL15_TRP_V(e)          BF_DRAM_CTL15_TRP(BV_DRAM_CTL15_TRP__##e)
+#define BFM_DRAM_CTL15_TRP_V(v)         BM_DRAM_CTL15_TRP
+#define BP_DRAM_CTL15_TDAL              16
+#define BM_DRAM_CTL15_TDAL              0xf0000
+#define BF_DRAM_CTL15_TDAL(v)           (((v) & 0xf) << 16)
+#define BFM_DRAM_CTL15_TDAL(v)          BM_DRAM_CTL15_TDAL
+#define BF_DRAM_CTL15_TDAL_V(e)         BF_DRAM_CTL15_TDAL(BV_DRAM_CTL15_TDAL__##e)
+#define BFM_DRAM_CTL15_TDAL_V(v)        BM_DRAM_CTL15_TDAL
+#define BP_DRAM_CTL15_PORT_BUSY         8
+#define BM_DRAM_CTL15_PORT_BUSY         0xf00
+#define BF_DRAM_CTL15_PORT_BUSY(v)      (((v) & 0xf) << 8)
+#define BFM_DRAM_CTL15_PORT_BUSY(v)     BM_DRAM_CTL15_PORT_BUSY
+#define BF_DRAM_CTL15_PORT_BUSY_V(e)    BF_DRAM_CTL15_PORT_BUSY(BV_DRAM_CTL15_PORT_BUSY__##e)
+#define BFM_DRAM_CTL15_PORT_BUSY_V(v)   BM_DRAM_CTL15_PORT_BUSY
+#define BP_DRAM_CTL15_MAX_ROW_REG       0
+#define BM_DRAM_CTL15_MAX_ROW_REG       0xf
+#define BF_DRAM_CTL15_MAX_ROW_REG(v)    (((v) & 0xf) << 0)
+#define BFM_DRAM_CTL15_MAX_ROW_REG(v)   BM_DRAM_CTL15_MAX_ROW_REG
+#define BF_DRAM_CTL15_MAX_ROW_REG_V(e)  BF_DRAM_CTL15_MAX_ROW_REG(BV_DRAM_CTL15_MAX_ROW_REG__##e)
+#define BFM_DRAM_CTL15_MAX_ROW_REG_V(v) BM_DRAM_CTL15_MAX_ROW_REG
+
+#define HW_DRAM_CTL16                               HW(DRAM_CTL16)
+#define HWA_DRAM_CTL16                              (0x800e0000 + 0x40)
+#define HWT_DRAM_CTL16                              HWIO_32_RW
+#define HWN_DRAM_CTL16                              DRAM_CTL16
+#define HWI_DRAM_CTL16                              
+#define BP_DRAM_CTL16_TMRD                          24
+#define BM_DRAM_CTL16_TMRD                          0x1f000000
+#define BF_DRAM_CTL16_TMRD(v)                       (((v) & 0x1f) << 24)
+#define BFM_DRAM_CTL16_TMRD(v)                      BM_DRAM_CTL16_TMRD
+#define BF_DRAM_CTL16_TMRD_V(e)                     BF_DRAM_CTL16_TMRD(BV_DRAM_CTL16_TMRD__##e)
+#define BFM_DRAM_CTL16_TMRD_V(v)                    BM_DRAM_CTL16_TMRD
+#define BP_DRAM_CTL16_LOWPOWER_CONTROL              16
+#define BM_DRAM_CTL16_LOWPOWER_CONTROL              0x1f0000
+#define BF_DRAM_CTL16_LOWPOWER_CONTROL(v)           (((v) & 0x1f) << 16)
+#define BFM_DRAM_CTL16_LOWPOWER_CONTROL(v)          BM_DRAM_CTL16_LOWPOWER_CONTROL
+#define BF_DRAM_CTL16_LOWPOWER_CONTROL_V(e)         BF_DRAM_CTL16_LOWPOWER_CONTROL(BV_DRAM_CTL16_LOWPOWER_CONTROL__##e)
+#define BFM_DRAM_CTL16_LOWPOWER_CONTROL_V(v)        BM_DRAM_CTL16_LOWPOWER_CONTROL
+#define BP_DRAM_CTL16_LOWPOWER_AUTO_ENABLE          8
+#define BM_DRAM_CTL16_LOWPOWER_AUTO_ENABLE          0x1f00
+#define BF_DRAM_CTL16_LOWPOWER_AUTO_ENABLE(v)       (((v) & 0x1f) << 8)
+#define BFM_DRAM_CTL16_LOWPOWER_AUTO_ENABLE(v)      BM_DRAM_CTL16_LOWPOWER_AUTO_ENABLE
+#define BF_DRAM_CTL16_LOWPOWER_AUTO_ENABLE_V(e)     BF_DRAM_CTL16_LOWPOWER_AUTO_ENABLE(BV_DRAM_CTL16_LOWPOWER_AUTO_ENABLE__##e)
+#define BFM_DRAM_CTL16_LOWPOWER_AUTO_ENABLE_V(v)    BM_DRAM_CTL16_LOWPOWER_AUTO_ENABLE
+#define BP_DRAM_CTL16_INT_ACK                       0
+#define BM_DRAM_CTL16_INT_ACK                       0xf
+#define BF_DRAM_CTL16_INT_ACK(v)                    (((v) & 0xf) << 0)
+#define BFM_DRAM_CTL16_INT_ACK(v)                   BM_DRAM_CTL16_INT_ACK
+#define BF_DRAM_CTL16_INT_ACK_V(e)                  BF_DRAM_CTL16_INT_ACK(BV_DRAM_CTL16_INT_ACK__##e)
+#define BFM_DRAM_CTL16_INT_ACK_V(v)                 BM_DRAM_CTL16_INT_ACK
+
+#define HW_DRAM_CTL17                       HW(DRAM_CTL17)
+#define HWA_DRAM_CTL17                      (0x800e0000 + 0x44)
+#define HWT_DRAM_CTL17                      HWIO_32_RW
+#define HWN_DRAM_CTL17                      DRAM_CTL17
+#define HWI_DRAM_CTL17                      
+#define BP_DRAM_CTL17_DLL_START_POINT       24
+#define BM_DRAM_CTL17_DLL_START_POINT       0xff000000
+#define BF_DRAM_CTL17_DLL_START_POINT(v)    (((v) & 0xff) << 24)
+#define BFM_DRAM_CTL17_DLL_START_POINT(v)   BM_DRAM_CTL17_DLL_START_POINT
+#define BF_DRAM_CTL17_DLL_START_POINT_V(e)  BF_DRAM_CTL17_DLL_START_POINT(BV_DRAM_CTL17_DLL_START_POINT__##e)
+#define BFM_DRAM_CTL17_DLL_START_POINT_V(v) BM_DRAM_CTL17_DLL_START_POINT
+#define BP_DRAM_CTL17_DLL_LOCK              16
+#define BM_DRAM_CTL17_DLL_LOCK              0xff0000
+#define BF_DRAM_CTL17_DLL_LOCK(v)           (((v) & 0xff) << 16)
+#define BFM_DRAM_CTL17_DLL_LOCK(v)          BM_DRAM_CTL17_DLL_LOCK
+#define BF_DRAM_CTL17_DLL_LOCK_V(e)         BF_DRAM_CTL17_DLL_LOCK(BV_DRAM_CTL17_DLL_LOCK__##e)
+#define BFM_DRAM_CTL17_DLL_LOCK_V(v)        BM_DRAM_CTL17_DLL_LOCK
+#define BP_DRAM_CTL17_DLL_INCREMENT         8
+#define BM_DRAM_CTL17_DLL_INCREMENT         0xff00
+#define BF_DRAM_CTL17_DLL_INCREMENT(v)      (((v) & 0xff) << 8)
+#define BFM_DRAM_CTL17_DLL_INCREMENT(v)     BM_DRAM_CTL17_DLL_INCREMENT
+#define BF_DRAM_CTL17_DLL_INCREMENT_V(e)    BF_DRAM_CTL17_DLL_INCREMENT(BV_DRAM_CTL17_DLL_INCREMENT__##e)
+#define BFM_DRAM_CTL17_DLL_INCREMENT_V(v)   BM_DRAM_CTL17_DLL_INCREMENT
+#define BP_DRAM_CTL17_TRC                   0
+#define BM_DRAM_CTL17_TRC                   0x1f
+#define BF_DRAM_CTL17_TRC(v)                (((v) & 0x1f) << 0)
+#define BFM_DRAM_CTL17_TRC(v)               BM_DRAM_CTL17_TRC
+#define BF_DRAM_CTL17_TRC_V(e)              BF_DRAM_CTL17_TRC(BV_DRAM_CTL17_TRC__##e)
+#define BFM_DRAM_CTL17_TRC_V(v)             BM_DRAM_CTL17_TRC
+
+#define HW_DRAM_CTL18                       HW(DRAM_CTL18)
+#define HWA_DRAM_CTL18                      (0x800e0000 + 0x48)
+#define HWT_DRAM_CTL18                      HWIO_32_RW
+#define HWN_DRAM_CTL18                      DRAM_CTL18
+#define HWI_DRAM_CTL18                      
+#define BP_DRAM_CTL18_DLL_DQS_DELAY_1       24
+#define BM_DRAM_CTL18_DLL_DQS_DELAY_1       0x7f000000
+#define BF_DRAM_CTL18_DLL_DQS_DELAY_1(v)    (((v) & 0x7f) << 24)
+#define BFM_DRAM_CTL18_DLL_DQS_DELAY_1(v)   BM_DRAM_CTL18_DLL_DQS_DELAY_1
+#define BF_DRAM_CTL18_DLL_DQS_DELAY_1_V(e)  BF_DRAM_CTL18_DLL_DQS_DELAY_1(BV_DRAM_CTL18_DLL_DQS_DELAY_1__##e)
+#define BFM_DRAM_CTL18_DLL_DQS_DELAY_1_V(v) BM_DRAM_CTL18_DLL_DQS_DELAY_1
+#define BP_DRAM_CTL18_DLL_DQS_DELAY_0       16
+#define BM_DRAM_CTL18_DLL_DQS_DELAY_0       0x7f0000
+#define BF_DRAM_CTL18_DLL_DQS_DELAY_0(v)    (((v) & 0x7f) << 16)
+#define BFM_DRAM_CTL18_DLL_DQS_DELAY_0(v)   BM_DRAM_CTL18_DLL_DQS_DELAY_0
+#define BF_DRAM_CTL18_DLL_DQS_DELAY_0_V(e)  BF_DRAM_CTL18_DLL_DQS_DELAY_0(BV_DRAM_CTL18_DLL_DQS_DELAY_0__##e)
+#define BFM_DRAM_CTL18_DLL_DQS_DELAY_0_V(v) BM_DRAM_CTL18_DLL_DQS_DELAY_0
+#define BP_DRAM_CTL18_INT_STATUS            8
+#define BM_DRAM_CTL18_INT_STATUS            0x1f00
+#define BF_DRAM_CTL18_INT_STATUS(v)         (((v) & 0x1f) << 8)
+#define BFM_DRAM_CTL18_INT_STATUS(v)        BM_DRAM_CTL18_INT_STATUS
+#define BF_DRAM_CTL18_INT_STATUS_V(e)       BF_DRAM_CTL18_INT_STATUS(BV_DRAM_CTL18_INT_STATUS__##e)
+#define BFM_DRAM_CTL18_INT_STATUS_V(v)      BM_DRAM_CTL18_INT_STATUS
+#define BP_DRAM_CTL18_INT_MASK              0
+#define BM_DRAM_CTL18_INT_MASK              0x1f
+#define BF_DRAM_CTL18_INT_MASK(v)           (((v) & 0x1f) << 0)
+#define BFM_DRAM_CTL18_INT_MASK(v)          BM_DRAM_CTL18_INT_MASK
+#define BF_DRAM_CTL18_INT_MASK_V(e)         BF_DRAM_CTL18_INT_MASK(BV_DRAM_CTL18_INT_MASK__##e)
+#define BFM_DRAM_CTL18_INT_MASK_V(v)        BM_DRAM_CTL18_INT_MASK
+
+#define HW_DRAM_CTL19                               HW(DRAM_CTL19)
+#define HWA_DRAM_CTL19                              (0x800e0000 + 0x4c)
+#define HWT_DRAM_CTL19                              HWIO_32_RW
+#define HWN_DRAM_CTL19                              DRAM_CTL19
+#define HWI_DRAM_CTL19                              
+#define BP_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS          24
+#define BM_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS          0xff000000
+#define BF_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS(v)       (((v) & 0xff) << 24)
+#define BFM_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS(v)      BM_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS
+#define BF_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS_V(e)     BF_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS(BV_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS__##e)
+#define BFM_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS_V(v)    BM_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS
+#define BP_DRAM_CTL19_DQS_OUT_SHIFT                 16
+#define BM_DRAM_CTL19_DQS_OUT_SHIFT                 0x7f0000
+#define BF_DRAM_CTL19_DQS_OUT_SHIFT(v)              (((v) & 0x7f) << 16)
+#define BFM_DRAM_CTL19_DQS_OUT_SHIFT(v)             BM_DRAM_CTL19_DQS_OUT_SHIFT
+#define BF_DRAM_CTL19_DQS_OUT_SHIFT_V(e)            BF_DRAM_CTL19_DQS_OUT_SHIFT(BV_DRAM_CTL19_DQS_OUT_SHIFT__##e)
+#define BFM_DRAM_CTL19_DQS_OUT_SHIFT_V(v)           BM_DRAM_CTL19_DQS_OUT_SHIFT
+#define BP_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1        8
+#define BM_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1        0xff00
+#define BF_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1(v)     (((v) & 0xff) << 8)
+#define BFM_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1(v)    BM_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1
+#define BF_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1_V(e)   BF_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1(BV_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1__##e)
+#define BFM_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1_V(v)  BM_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1
+#define BP_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0        0
+#define BM_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0        0xff
+#define BF_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0(v)     (((v) & 0xff) << 0)
+#define BFM_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0(v)    BM_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0
+#define BF_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0_V(e)   BF_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0(BV_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0__##e)
+#define BFM_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0_V(v)  BM_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0
+
+#define HW_DRAM_CTL20                           HW(DRAM_CTL20)
+#define HWA_DRAM_CTL20                          (0x800e0000 + 0x50)
+#define HWT_DRAM_CTL20                          HWIO_32_RW
+#define HWN_DRAM_CTL20                          DRAM_CTL20
+#define HWI_DRAM_CTL20                          
+#define BP_DRAM_CTL20_TRCD_INT                  24
+#define BM_DRAM_CTL20_TRCD_INT                  0xff000000
+#define BF_DRAM_CTL20_TRCD_INT(v)               (((v) & 0xff) << 24)
+#define BFM_DRAM_CTL20_TRCD_INT(v)              BM_DRAM_CTL20_TRCD_INT
+#define BF_DRAM_CTL20_TRCD_INT_V(e)             BF_DRAM_CTL20_TRCD_INT(BV_DRAM_CTL20_TRCD_INT__##e)
+#define BFM_DRAM_CTL20_TRCD_INT_V(v)            BM_DRAM_CTL20_TRCD_INT
+#define BP_DRAM_CTL20_TRAS_MIN                  16
+#define BM_DRAM_CTL20_TRAS_MIN                  0xff0000
+#define BF_DRAM_CTL20_TRAS_MIN(v)               (((v) & 0xff) << 16)
+#define BFM_DRAM_CTL20_TRAS_MIN(v)              BM_DRAM_CTL20_TRAS_MIN
+#define BF_DRAM_CTL20_TRAS_MIN_V(e)             BF_DRAM_CTL20_TRAS_MIN(BV_DRAM_CTL20_TRAS_MIN__##e)
+#define BFM_DRAM_CTL20_TRAS_MIN_V(v)            BM_DRAM_CTL20_TRAS_MIN
+#define BP_DRAM_CTL20_WR_DQS_SHIFT_BYPASS       8
+#define BM_DRAM_CTL20_WR_DQS_SHIFT_BYPASS       0xff00
+#define BF_DRAM_CTL20_WR_DQS_SHIFT_BYPASS(v)    (((v) & 0xff) << 8)
+#define BFM_DRAM_CTL20_WR_DQS_SHIFT_BYPASS(v)   BM_DRAM_CTL20_WR_DQS_SHIFT_BYPASS
+#define BF_DRAM_CTL20_WR_DQS_SHIFT_BYPASS_V(e)  BF_DRAM_CTL20_WR_DQS_SHIFT_BYPASS(BV_DRAM_CTL20_WR_DQS_SHIFT_BYPASS__##e)
+#define BFM_DRAM_CTL20_WR_DQS_SHIFT_BYPASS_V(v) BM_DRAM_CTL20_WR_DQS_SHIFT_BYPASS
+#define BP_DRAM_CTL20_WR_DQS_SHIFT              0
+#define BM_DRAM_CTL20_WR_DQS_SHIFT              0x7f
+#define BF_DRAM_CTL20_WR_DQS_SHIFT(v)           (((v) & 0x7f) << 0)
+#define BFM_DRAM_CTL20_WR_DQS_SHIFT(v)          BM_DRAM_CTL20_WR_DQS_SHIFT
+#define BF_DRAM_CTL20_WR_DQS_SHIFT_V(e)         BF_DRAM_CTL20_WR_DQS_SHIFT(BV_DRAM_CTL20_WR_DQS_SHIFT__##e)
+#define BFM_DRAM_CTL20_WR_DQS_SHIFT_V(v)        BM_DRAM_CTL20_WR_DQS_SHIFT
+
+#define HW_DRAM_CTL21                           HW(DRAM_CTL21)
+#define HWA_DRAM_CTL21                          (0x800e0000 + 0x54)
+#define HWT_DRAM_CTL21                          HWIO_32_RW
+#define HWN_DRAM_CTL21                          DRAM_CTL21
+#define HWI_DRAM_CTL21                          
+#define BP_DRAM_CTL21_OUT_OF_RANGE_LENGTH       8
+#define BM_DRAM_CTL21_OUT_OF_RANGE_LENGTH       0x3ff00
+#define BF_DRAM_CTL21_OUT_OF_RANGE_LENGTH(v)    (((v) & 0x3ff) << 8)
+#define BFM_DRAM_CTL21_OUT_OF_RANGE_LENGTH(v)   BM_DRAM_CTL21_OUT_OF_RANGE_LENGTH
+#define BF_DRAM_CTL21_OUT_OF_RANGE_LENGTH_V(e)  BF_DRAM_CTL21_OUT_OF_RANGE_LENGTH(BV_DRAM_CTL21_OUT_OF_RANGE_LENGTH__##e)
+#define BFM_DRAM_CTL21_OUT_OF_RANGE_LENGTH_V(v) BM_DRAM_CTL21_OUT_OF_RANGE_LENGTH
+#define BP_DRAM_CTL21_TRFC                      0
+#define BM_DRAM_CTL21_TRFC                      0xff
+#define BF_DRAM_CTL21_TRFC(v)                   (((v) & 0xff) << 0)
+#define BFM_DRAM_CTL21_TRFC(v)                  BM_DRAM_CTL21_TRFC
+#define BF_DRAM_CTL21_TRFC_V(e)                 BF_DRAM_CTL21_TRFC(BV_DRAM_CTL21_TRFC__##e)
+#define BFM_DRAM_CTL21_TRFC_V(v)                BM_DRAM_CTL21_TRFC
+
+#define HW_DRAM_CTL22                   HW(DRAM_CTL22)
+#define HWA_DRAM_CTL22                  (0x800e0000 + 0x58)
+#define HWT_DRAM_CTL22                  HWIO_32_RW
+#define HWN_DRAM_CTL22                  DRAM_CTL22
+#define HWI_DRAM_CTL22                  
+#define BP_DRAM_CTL22_AHB0_WRCNT        16
+#define BM_DRAM_CTL22_AHB0_WRCNT        0x7ff0000
+#define BF_DRAM_CTL22_AHB0_WRCNT(v)     (((v) & 0x7ff) << 16)
+#define BFM_DRAM_CTL22_AHB0_WRCNT(v)    BM_DRAM_CTL22_AHB0_WRCNT
+#define BF_DRAM_CTL22_AHB0_WRCNT_V(e)   BF_DRAM_CTL22_AHB0_WRCNT(BV_DRAM_CTL22_AHB0_WRCNT__##e)
+#define BFM_DRAM_CTL22_AHB0_WRCNT_V(v)  BM_DRAM_CTL22_AHB0_WRCNT
+#define BP_DRAM_CTL22_AHB0_RDCNT        0
+#define BM_DRAM_CTL22_AHB0_RDCNT        0x7ff
+#define BF_DRAM_CTL22_AHB0_RDCNT(v)     (((v) & 0x7ff) << 0)
+#define BFM_DRAM_CTL22_AHB0_RDCNT(v)    BM_DRAM_CTL22_AHB0_RDCNT
+#define BF_DRAM_CTL22_AHB0_RDCNT_V(e)   BF_DRAM_CTL22_AHB0_RDCNT(BV_DRAM_CTL22_AHB0_RDCNT__##e)
+#define BFM_DRAM_CTL22_AHB0_RDCNT_V(v)  BM_DRAM_CTL22_AHB0_RDCNT
+
+#define HW_DRAM_CTL23                   HW(DRAM_CTL23)
+#define HWA_DRAM_CTL23                  (0x800e0000 + 0x5c)
+#define HWT_DRAM_CTL23                  HWIO_32_RW
+#define HWN_DRAM_CTL23                  DRAM_CTL23
+#define HWI_DRAM_CTL23                  
+#define BP_DRAM_CTL23_AHB1_WRCNT        16
+#define BM_DRAM_CTL23_AHB1_WRCNT        0x7ff0000
+#define BF_DRAM_CTL23_AHB1_WRCNT(v)     (((v) & 0x7ff) << 16)
+#define BFM_DRAM_CTL23_AHB1_WRCNT(v)    BM_DRAM_CTL23_AHB1_WRCNT
+#define BF_DRAM_CTL23_AHB1_WRCNT_V(e)   BF_DRAM_CTL23_AHB1_WRCNT(BV_DRAM_CTL23_AHB1_WRCNT__##e)
+#define BFM_DRAM_CTL23_AHB1_WRCNT_V(v)  BM_DRAM_CTL23_AHB1_WRCNT
+#define BP_DRAM_CTL23_AHB1_RDCNT        0
+#define BM_DRAM_CTL23_AHB1_RDCNT        0x7ff
+#define BF_DRAM_CTL23_AHB1_RDCNT(v)     (((v) & 0x7ff) << 0)
+#define BFM_DRAM_CTL23_AHB1_RDCNT(v)    BM_DRAM_CTL23_AHB1_RDCNT
+#define BF_DRAM_CTL23_AHB1_RDCNT_V(e)   BF_DRAM_CTL23_AHB1_RDCNT(BV_DRAM_CTL23_AHB1_RDCNT__##e)
+#define BFM_DRAM_CTL23_AHB1_RDCNT_V(v)  BM_DRAM_CTL23_AHB1_RDCNT
+
+#define HW_DRAM_CTL24                   HW(DRAM_CTL24)
+#define HWA_DRAM_CTL24                  (0x800e0000 + 0x60)
+#define HWT_DRAM_CTL24                  HWIO_32_RW
+#define HWN_DRAM_CTL24                  DRAM_CTL24
+#define HWI_DRAM_CTL24                  
+#define BP_DRAM_CTL24_AHB2_WRCNT        16
+#define BM_DRAM_CTL24_AHB2_WRCNT        0x7ff0000
+#define BF_DRAM_CTL24_AHB2_WRCNT(v)     (((v) & 0x7ff) << 16)
+#define BFM_DRAM_CTL24_AHB2_WRCNT(v)    BM_DRAM_CTL24_AHB2_WRCNT
+#define BF_DRAM_CTL24_AHB2_WRCNT_V(e)   BF_DRAM_CTL24_AHB2_WRCNT(BV_DRAM_CTL24_AHB2_WRCNT__##e)
+#define BFM_DRAM_CTL24_AHB2_WRCNT_V(v)  BM_DRAM_CTL24_AHB2_WRCNT
+#define BP_DRAM_CTL24_AHB2_RDCNT        0
+#define BM_DRAM_CTL24_AHB2_RDCNT        0x7ff
+#define BF_DRAM_CTL24_AHB2_RDCNT(v)     (((v) & 0x7ff) << 0)
+#define BFM_DRAM_CTL24_AHB2_RDCNT(v)    BM_DRAM_CTL24_AHB2_RDCNT
+#define BF_DRAM_CTL24_AHB2_RDCNT_V(e)   BF_DRAM_CTL24_AHB2_RDCNT(BV_DRAM_CTL24_AHB2_RDCNT__##e)
+#define BFM_DRAM_CTL24_AHB2_RDCNT_V(v)  BM_DRAM_CTL24_AHB2_RDCNT
+
+#define HW_DRAM_CTL25                   HW(DRAM_CTL25)
+#define HWA_DRAM_CTL25                  (0x800e0000 + 0x64)
+#define HWT_DRAM_CTL25                  HWIO_32_RW
+#define HWN_DRAM_CTL25                  DRAM_CTL25
+#define HWI_DRAM_CTL25                  
+#define BP_DRAM_CTL25_AHB3_WRCNT        16
+#define BM_DRAM_CTL25_AHB3_WRCNT        0x7ff0000
+#define BF_DRAM_CTL25_AHB3_WRCNT(v)     (((v) & 0x7ff) << 16)
+#define BFM_DRAM_CTL25_AHB3_WRCNT(v)    BM_DRAM_CTL25_AHB3_WRCNT
+#define BF_DRAM_CTL25_AHB3_WRCNT_V(e)   BF_DRAM_CTL25_AHB3_WRCNT(BV_DRAM_CTL25_AHB3_WRCNT__##e)
+#define BFM_DRAM_CTL25_AHB3_WRCNT_V(v)  BM_DRAM_CTL25_AHB3_WRCNT
+#define BP_DRAM_CTL25_AHB3_RDCNT        0
+#define BM_DRAM_CTL25_AHB3_RDCNT        0x7ff
+#define BF_DRAM_CTL25_AHB3_RDCNT(v)     (((v) & 0x7ff) << 0)
+#define BFM_DRAM_CTL25_AHB3_RDCNT(v)    BM_DRAM_CTL25_AHB3_RDCNT
+#define BF_DRAM_CTL25_AHB3_RDCNT_V(e)   BF_DRAM_CTL25_AHB3_RDCNT(BV_DRAM_CTL25_AHB3_RDCNT__##e)
+#define BFM_DRAM_CTL25_AHB3_RDCNT_V(v)  BM_DRAM_CTL25_AHB3_RDCNT
+
+#define HW_DRAM_CTL26               HW(DRAM_CTL26)
+#define HWA_DRAM_CTL26              (0x800e0000 + 0x68)
+#define HWT_DRAM_CTL26              HWIO_32_RW
+#define HWN_DRAM_CTL26              DRAM_CTL26
+#define HWI_DRAM_CTL26              
+#define BP_DRAM_CTL26_TREF          0
+#define BM_DRAM_CTL26_TREF          0xfff
+#define BF_DRAM_CTL26_TREF(v)       (((v) & 0xfff) << 0)
+#define BFM_DRAM_CTL26_TREF(v)      BM_DRAM_CTL26_TREF
+#define BF_DRAM_CTL26_TREF_V(e)     BF_DRAM_CTL26_TREF(BV_DRAM_CTL26_TREF__##e)
+#define BFM_DRAM_CTL26_TREF_V(v)    BM_DRAM_CTL26_TREF
+
+#define HW_DRAM_CTL27   HW(DRAM_CTL27)
+#define HWA_DRAM_CTL27  (0x800e0000 + 0x6c)
+#define HWT_DRAM_CTL27  HWIO_32_RW
+#define HWN_DRAM_CTL27  DRAM_CTL27
+#define HWI_DRAM_CTL27  
+
+#define HW_DRAM_CTL28   HW(DRAM_CTL28)
+#define HWA_DRAM_CTL28  (0x800e0000 + 0x70)
+#define HWT_DRAM_CTL28  HWIO_32_RW
+#define HWN_DRAM_CTL28  DRAM_CTL28
+#define HWI_DRAM_CTL28  
+
+#define HW_DRAM_CTL29                               HW(DRAM_CTL29)
+#define HWA_DRAM_CTL29                              (0x800e0000 + 0x74)
+#define HWT_DRAM_CTL29                              HWIO_32_RW
+#define HWN_DRAM_CTL29                              DRAM_CTL29
+#define HWI_DRAM_CTL29                              
+#define BP_DRAM_CTL29_LOWPOWER_INTERNAL_CNT         16
+#define BM_DRAM_CTL29_LOWPOWER_INTERNAL_CNT         0xffff0000
+#define BF_DRAM_CTL29_LOWPOWER_INTERNAL_CNT(v)      (((v) & 0xffff) << 16)
+#define BFM_DRAM_CTL29_LOWPOWER_INTERNAL_CNT(v)     BM_DRAM_CTL29_LOWPOWER_INTERNAL_CNT
+#define BF_DRAM_CTL29_LOWPOWER_INTERNAL_CNT_V(e)    BF_DRAM_CTL29_LOWPOWER_INTERNAL_CNT(BV_DRAM_CTL29_LOWPOWER_INTERNAL_CNT__##e)
+#define BFM_DRAM_CTL29_LOWPOWER_INTERNAL_CNT_V(v)   BM_DRAM_CTL29_LOWPOWER_INTERNAL_CNT
+#define BP_DRAM_CTL29_LOWPOWER_EXTERNAL_CNT         0
+#define BM_DRAM_CTL29_LOWPOWER_EXTERNAL_CNT         0xffff
+#define BF_DRAM_CTL29_LOWPOWER_EXTERNAL_CNT(v)      (((v) & 0xffff) << 0)
+#define BFM_DRAM_CTL29_LOWPOWER_EXTERNAL_CNT(v)     BM_DRAM_CTL29_LOWPOWER_EXTERNAL_CNT
+#define BF_DRAM_CTL29_LOWPOWER_EXTERNAL_CNT_V(e)    BF_DRAM_CTL29_LOWPOWER_EXTERNAL_CNT(BV_DRAM_CTL29_LOWPOWER_EXTERNAL_CNT__##e)
+#define BFM_DRAM_CTL29_LOWPOWER_EXTERNAL_CNT_V(v)   BM_DRAM_CTL29_LOWPOWER_EXTERNAL_CNT
+
+#define HW_DRAM_CTL30                               HW(DRAM_CTL30)
+#define HWA_DRAM_CTL30                              (0x800e0000 + 0x78)
+#define HWT_DRAM_CTL30                              HWIO_32_RW
+#define HWN_DRAM_CTL30                              DRAM_CTL30
+#define HWI_DRAM_CTL30                              
+#define BP_DRAM_CTL30_LOWPOWER_REFRESH_HOLD         16
+#define BM_DRAM_CTL30_LOWPOWER_REFRESH_HOLD         0xffff0000
+#define BF_DRAM_CTL30_LOWPOWER_REFRESH_HOLD(v)      (((v) & 0xffff) << 16)
+#define BFM_DRAM_CTL30_LOWPOWER_REFRESH_HOLD(v)     BM_DRAM_CTL30_LOWPOWER_REFRESH_HOLD
+#define BF_DRAM_CTL30_LOWPOWER_REFRESH_HOLD_V(e)    BF_DRAM_CTL30_LOWPOWER_REFRESH_HOLD(BV_DRAM_CTL30_LOWPOWER_REFRESH_HOLD__##e)
+#define BFM_DRAM_CTL30_LOWPOWER_REFRESH_HOLD_V(v)   BM_DRAM_CTL30_LOWPOWER_REFRESH_HOLD
+#define BP_DRAM_CTL30_LOWPOWER_POWER_DOWN_CNT       0
+#define BM_DRAM_CTL30_LOWPOWER_POWER_DOWN_CNT       0xffff
+#define BF_DRAM_CTL30_LOWPOWER_POWER_DOWN_CNT(v)    (((v) & 0xffff) << 0)
+#define BFM_DRAM_CTL30_LOWPOWER_POWER_DOWN_CNT(v)   BM_DRAM_CTL30_LOWPOWER_POWER_DOWN_CNT
+#define BF_DRAM_CTL30_LOWPOWER_POWER_DOWN_CNT_V(e)  BF_DRAM_CTL30_LOWPOWER_POWER_DOWN_CNT(BV_DRAM_CTL30_LOWPOWER_POWER_DOWN_CNT__##e)
+#define BFM_DRAM_CTL30_LOWPOWER_POWER_DOWN_CNT_V(v) BM_DRAM_CTL30_LOWPOWER_POWER_DOWN_CNT
+
+#define HW_DRAM_CTL31                                   HW(DRAM_CTL31)
+#define HWA_DRAM_CTL31                                  (0x800e0000 + 0x7c)
+#define HWT_DRAM_CTL31                                  HWIO_32_RW
+#define HWN_DRAM_CTL31                                  DRAM_CTL31
+#define HWI_DRAM_CTL31                                  
+#define BP_DRAM_CTL31_TDLL                              16
+#define BM_DRAM_CTL31_TDLL                              0xffff0000
+#define BF_DRAM_CTL31_TDLL(v)                           (((v) & 0xffff) << 16)
+#define BFM_DRAM_CTL31_TDLL(v)                          BM_DRAM_CTL31_TDLL
+#define BF_DRAM_CTL31_TDLL_V(e)                         BF_DRAM_CTL31_TDLL(BV_DRAM_CTL31_TDLL__##e)
+#define BFM_DRAM_CTL31_TDLL_V(v)                        BM_DRAM_CTL31_TDLL
+#define BP_DRAM_CTL31_LOWPOWER_SELF_REFRESH_CNT         0
+#define BM_DRAM_CTL31_LOWPOWER_SELF_REFRESH_CNT         0xffff
+#define BF_DRAM_CTL31_LOWPOWER_SELF_REFRESH_CNT(v)      (((v) & 0xffff) << 0)
+#define BFM_DRAM_CTL31_LOWPOWER_SELF_REFRESH_CNT(v)     BM_DRAM_CTL31_LOWPOWER_SELF_REFRESH_CNT
+#define BF_DRAM_CTL31_LOWPOWER_SELF_REFRESH_CNT_V(e)    BF_DRAM_CTL31_LOWPOWER_SELF_REFRESH_CNT(BV_DRAM_CTL31_LOWPOWER_SELF_REFRESH_CNT__##e)
+#define BFM_DRAM_CTL31_LOWPOWER_SELF_REFRESH_CNT_V(v)   BM_DRAM_CTL31_LOWPOWER_SELF_REFRESH_CNT
+
+#define HW_DRAM_CTL32                   HW(DRAM_CTL32)
+#define HWA_DRAM_CTL32                  (0x800e0000 + 0x80)
+#define HWT_DRAM_CTL32                  HWIO_32_RW
+#define HWN_DRAM_CTL32                  DRAM_CTL32
+#define HWI_DRAM_CTL32                  
+#define BP_DRAM_CTL32_TXSNR             16
+#define BM_DRAM_CTL32_TXSNR             0xffff0000
+#define BF_DRAM_CTL32_TXSNR(v)          (((v) & 0xffff) << 16)
+#define BFM_DRAM_CTL32_TXSNR(v)         BM_DRAM_CTL32_TXSNR
+#define BF_DRAM_CTL32_TXSNR_V(e)        BF_DRAM_CTL32_TXSNR(BV_DRAM_CTL32_TXSNR__##e)
+#define BFM_DRAM_CTL32_TXSNR_V(v)       BM_DRAM_CTL32_TXSNR
+#define BP_DRAM_CTL32_TRAS_MAX          0
+#define BM_DRAM_CTL32_TRAS_MAX          0xffff
+#define BF_DRAM_CTL32_TRAS_MAX(v)       (((v) & 0xffff) << 0)
+#define BFM_DRAM_CTL32_TRAS_MAX(v)      BM_DRAM_CTL32_TRAS_MAX
+#define BF_DRAM_CTL32_TRAS_MAX_V(e)     BF_DRAM_CTL32_TRAS_MAX(BV_DRAM_CTL32_TRAS_MAX__##e)
+#define BFM_DRAM_CTL32_TRAS_MAX_V(v)    BM_DRAM_CTL32_TRAS_MAX
+
+#define HW_DRAM_CTL33               HW(DRAM_CTL33)
+#define HWA_DRAM_CTL33              (0x800e0000 + 0x84)
+#define HWT_DRAM_CTL33              HWIO_32_RW
+#define HWN_DRAM_CTL33              DRAM_CTL33
+#define HWI_DRAM_CTL33              
+#define BP_DRAM_CTL33_VERSION       16
+#define BM_DRAM_CTL33_VERSION       0xffff0000
+#define BF_DRAM_CTL33_VERSION(v)    (((v) & 0xffff) << 16)
+#define BFM_DRAM_CTL33_VERSION(v)   BM_DRAM_CTL33_VERSION
+#define BF_DRAM_CTL33_VERSION_V(e)  BF_DRAM_CTL33_VERSION(BV_DRAM_CTL33_VERSION__##e)
+#define BFM_DRAM_CTL33_VERSION_V(v) BM_DRAM_CTL33_VERSION
+#define BP_DRAM_CTL33_TXSR          0
+#define BM_DRAM_CTL33_TXSR          0xffff
+#define BF_DRAM_CTL33_TXSR(v)       (((v) & 0xffff) << 0)
+#define BFM_DRAM_CTL33_TXSR(v)      BM_DRAM_CTL33_TXSR
+#define BF_DRAM_CTL33_TXSR_V(e)     BF_DRAM_CTL33_TXSR(BV_DRAM_CTL33_TXSR__##e)
+#define BFM_DRAM_CTL33_TXSR_V(v)    BM_DRAM_CTL33_TXSR
+
+#define HW_DRAM_CTL34               HW(DRAM_CTL34)
+#define HWA_DRAM_CTL34              (0x800e0000 + 0x88)
+#define HWT_DRAM_CTL34              HWIO_32_RW
+#define HWN_DRAM_CTL34              DRAM_CTL34
+#define HWI_DRAM_CTL34              
+#define BP_DRAM_CTL34_TINIT         0
+#define BM_DRAM_CTL34_TINIT         0xffffff
+#define BF_DRAM_CTL34_TINIT(v)      (((v) & 0xffffff) << 0)
+#define BFM_DRAM_CTL34_TINIT(v)     BM_DRAM_CTL34_TINIT
+#define BF_DRAM_CTL34_TINIT_V(e)    BF_DRAM_CTL34_TINIT(BV_DRAM_CTL34_TINIT__##e)
+#define BFM_DRAM_CTL34_TINIT_V(v)   BM_DRAM_CTL34_TINIT
+
+#define HW_DRAM_CTL35                           HW(DRAM_CTL35)
+#define HWA_DRAM_CTL35                          (0x800e0000 + 0x8c)
+#define HWT_DRAM_CTL35                          HWIO_32_RW
+#define HWN_DRAM_CTL35                          DRAM_CTL35
+#define HWI_DRAM_CTL35                          
+#define BP_DRAM_CTL35_OUT_OF_RANGE_ADDR         0
+#define BM_DRAM_CTL35_OUT_OF_RANGE_ADDR         0x7fffffff
+#define BF_DRAM_CTL35_OUT_OF_RANGE_ADDR(v)      (((v) & 0x7fffffff) << 0)
+#define BFM_DRAM_CTL35_OUT_OF_RANGE_ADDR(v)     BM_DRAM_CTL35_OUT_OF_RANGE_ADDR
+#define BF_DRAM_CTL35_OUT_OF_RANGE_ADDR_V(e)    BF_DRAM_CTL35_OUT_OF_RANGE_ADDR(BV_DRAM_CTL35_OUT_OF_RANGE_ADDR__##e)
+#define BFM_DRAM_CTL35_OUT_OF_RANGE_ADDR_V(v)   BM_DRAM_CTL35_OUT_OF_RANGE_ADDR
+
+#define HW_DRAM_CTL36                               HW(DRAM_CTL36)
+#define HWA_DRAM_CTL36                              (0x800e0000 + 0x90)
+#define HWT_DRAM_CTL36                              HWIO_32_RW
+#define HWN_DRAM_CTL36                              DRAM_CTL36
+#define HWI_DRAM_CTL36                              
+#define BP_DRAM_CTL36_PWRUP_SREFRESH_EXIT           24
+#define BM_DRAM_CTL36_PWRUP_SREFRESH_EXIT           0x1000000
+#define BF_DRAM_CTL36_PWRUP_SREFRESH_EXIT(v)        (((v) & 0x1) << 24)
+#define BFM_DRAM_CTL36_PWRUP_SREFRESH_EXIT(v)       BM_DRAM_CTL36_PWRUP_SREFRESH_EXIT
+#define BF_DRAM_CTL36_PWRUP_SREFRESH_EXIT_V(e)      BF_DRAM_CTL36_PWRUP_SREFRESH_EXIT(BV_DRAM_CTL36_PWRUP_SREFRESH_EXIT__##e)
+#define BFM_DRAM_CTL36_PWRUP_SREFRESH_EXIT_V(v)     BM_DRAM_CTL36_PWRUP_SREFRESH_EXIT
+#define BP_DRAM_CTL36_ENABLE_QUICK_SREFRESH         16
+#define BM_DRAM_CTL36_ENABLE_QUICK_SREFRESH         0x10000
+#define BF_DRAM_CTL36_ENABLE_QUICK_SREFRESH(v)      (((v) & 0x1) << 16)
+#define BFM_DRAM_CTL36_ENABLE_QUICK_SREFRESH(v)     BM_DRAM_CTL36_ENABLE_QUICK_SREFRESH
+#define BF_DRAM_CTL36_ENABLE_QUICK_SREFRESH_V(e)    BF_DRAM_CTL36_ENABLE_QUICK_SREFRESH(BV_DRAM_CTL36_ENABLE_QUICK_SREFRESH__##e)
+#define BFM_DRAM_CTL36_ENABLE_QUICK_SREFRESH_V(v)   BM_DRAM_CTL36_ENABLE_QUICK_SREFRESH
+#define BP_DRAM_CTL36_BUS_SHARE_ENABLE              8
+#define BM_DRAM_CTL36_BUS_SHARE_ENABLE              0x100
+#define BF_DRAM_CTL36_BUS_SHARE_ENABLE(v)           (((v) & 0x1) << 8)
+#define BFM_DRAM_CTL36_BUS_SHARE_ENABLE(v)          BM_DRAM_CTL36_BUS_SHARE_ENABLE
+#define BF_DRAM_CTL36_BUS_SHARE_ENABLE_V(e)         BF_DRAM_CTL36_BUS_SHARE_ENABLE(BV_DRAM_CTL36_BUS_SHARE_ENABLE__##e)
+#define BFM_DRAM_CTL36_BUS_SHARE_ENABLE_V(v)        BM_DRAM_CTL36_BUS_SHARE_ENABLE
+#define BP_DRAM_CTL36_ACTIVE_AGING                  0
+#define BM_DRAM_CTL36_ACTIVE_AGING                  0x1
+#define BF_DRAM_CTL36_ACTIVE_AGING(v)               (((v) & 0x1) << 0)
+#define BFM_DRAM_CTL36_ACTIVE_AGING(v)              BM_DRAM_CTL36_ACTIVE_AGING
+#define BF_DRAM_CTL36_ACTIVE_AGING_V(e)             BF_DRAM_CTL36_ACTIVE_AGING(BV_DRAM_CTL36_ACTIVE_AGING__##e)
+#define BFM_DRAM_CTL36_ACTIVE_AGING_V(v)            BM_DRAM_CTL36_ACTIVE_AGING
+
+#define HW_DRAM_CTL37                           HW(DRAM_CTL37)
+#define HWA_DRAM_CTL37                          (0x800e0000 + 0x94)
+#define HWT_DRAM_CTL37                          HWIO_32_RW
+#define HWN_DRAM_CTL37                          DRAM_CTL37
+#define HWI_DRAM_CTL37                          
+#define BP_DRAM_CTL37_BUS_SHARE_TIMEOUT         8
+#define BM_DRAM_CTL37_BUS_SHARE_TIMEOUT         0x3ff00
+#define BF_DRAM_CTL37_BUS_SHARE_TIMEOUT(v)      (((v) & 0x3ff) << 8)
+#define BFM_DRAM_CTL37_BUS_SHARE_TIMEOUT(v)     BM_DRAM_CTL37_BUS_SHARE_TIMEOUT
+#define BF_DRAM_CTL37_BUS_SHARE_TIMEOUT_V(e)    BF_DRAM_CTL37_BUS_SHARE_TIMEOUT(BV_DRAM_CTL37_BUS_SHARE_TIMEOUT__##e)
+#define BFM_DRAM_CTL37_BUS_SHARE_TIMEOUT_V(v)   BM_DRAM_CTL37_BUS_SHARE_TIMEOUT
+#define BP_DRAM_CTL37_TREF_ENABLE               0
+#define BM_DRAM_CTL37_TREF_ENABLE               0x1
+#define BF_DRAM_CTL37_TREF_ENABLE(v)            (((v) & 0x1) << 0)
+#define BFM_DRAM_CTL37_TREF_ENABLE(v)           BM_DRAM_CTL37_TREF_ENABLE
+#define BF_DRAM_CTL37_TREF_ENABLE_V(e)          BF_DRAM_CTL37_TREF_ENABLE(BV_DRAM_CTL37_TREF_ENABLE__##e)
+#define BFM_DRAM_CTL37_TREF_ENABLE_V(v)         BM_DRAM_CTL37_TREF_ENABLE
+
+#define HW_DRAM_CTL38                       HW(DRAM_CTL38)
+#define HWA_DRAM_CTL38                      (0x800e0000 + 0x98)
+#define HWT_DRAM_CTL38                      HWIO_32_RW
+#define HWN_DRAM_CTL38                      DRAM_CTL38
+#define HWI_DRAM_CTL38                      
+#define BP_DRAM_CTL38_EMRS2_DATA_0          16
+#define BM_DRAM_CTL38_EMRS2_DATA_0          0x1fff0000
+#define BF_DRAM_CTL38_EMRS2_DATA_0(v)       (((v) & 0x1fff) << 16)
+#define BFM_DRAM_CTL38_EMRS2_DATA_0(v)      BM_DRAM_CTL38_EMRS2_DATA_0
+#define BF_DRAM_CTL38_EMRS2_DATA_0_V(e)     BF_DRAM_CTL38_EMRS2_DATA_0(BV_DRAM_CTL38_EMRS2_DATA_0__##e)
+#define BFM_DRAM_CTL38_EMRS2_DATA_0_V(v)    BM_DRAM_CTL38_EMRS2_DATA_0
+#define BP_DRAM_CTL38_EMRS1_DATA            0
+#define BM_DRAM_CTL38_EMRS1_DATA            0x1fff
+#define BF_DRAM_CTL38_EMRS1_DATA(v)         (((v) & 0x1fff) << 0)
+#define BFM_DRAM_CTL38_EMRS1_DATA(v)        BM_DRAM_CTL38_EMRS1_DATA
+#define BF_DRAM_CTL38_EMRS1_DATA_V(e)       BF_DRAM_CTL38_EMRS1_DATA(BV_DRAM_CTL38_EMRS1_DATA__##e)
+#define BFM_DRAM_CTL38_EMRS1_DATA_V(v)      BM_DRAM_CTL38_EMRS1_DATA
+
+#define HW_DRAM_CTL39                       HW(DRAM_CTL39)
+#define HWA_DRAM_CTL39                      (0x800e0000 + 0x9c)
+#define HWT_DRAM_CTL39                      HWIO_32_RW
+#define HWN_DRAM_CTL39                      DRAM_CTL39
+#define HWI_DRAM_CTL39                      
+#define BP_DRAM_CTL39_EMRS2_DATA_2          16
+#define BM_DRAM_CTL39_EMRS2_DATA_2          0x1fff0000
+#define BF_DRAM_CTL39_EMRS2_DATA_2(v)       (((v) & 0x1fff) << 16)
+#define BFM_DRAM_CTL39_EMRS2_DATA_2(v)      BM_DRAM_CTL39_EMRS2_DATA_2
+#define BF_DRAM_CTL39_EMRS2_DATA_2_V(e)     BF_DRAM_CTL39_EMRS2_DATA_2(BV_DRAM_CTL39_EMRS2_DATA_2__##e)
+#define BFM_DRAM_CTL39_EMRS2_DATA_2_V(v)    BM_DRAM_CTL39_EMRS2_DATA_2
+#define BP_DRAM_CTL39_EMRS2_DATA_1          0
+#define BM_DRAM_CTL39_EMRS2_DATA_1          0x1fff
+#define BF_DRAM_CTL39_EMRS2_DATA_1(v)       (((v) & 0x1fff) << 0)
+#define BFM_DRAM_CTL39_EMRS2_DATA_1(v)      BM_DRAM_CTL39_EMRS2_DATA_1
+#define BF_DRAM_CTL39_EMRS2_DATA_1_V(e)     BF_DRAM_CTL39_EMRS2_DATA_1(BV_DRAM_CTL39_EMRS2_DATA_1__##e)
+#define BFM_DRAM_CTL39_EMRS2_DATA_1_V(v)    BM_DRAM_CTL39_EMRS2_DATA_1
+
+#define HW_DRAM_CTL40                       HW(DRAM_CTL40)
+#define HWA_DRAM_CTL40                      (0x800e0000 + 0xa0)
+#define HWT_DRAM_CTL40                      HWIO_32_RW
+#define HWN_DRAM_CTL40                      DRAM_CTL40
+#define HWI_DRAM_CTL40                      
+#define BP_DRAM_CTL40_TPDEX                 16
+#define BM_DRAM_CTL40_TPDEX                 0xffff0000
+#define BF_DRAM_CTL40_TPDEX(v)              (((v) & 0xffff) << 16)
+#define BFM_DRAM_CTL40_TPDEX(v)             BM_DRAM_CTL40_TPDEX
+#define BF_DRAM_CTL40_TPDEX_V(e)            BF_DRAM_CTL40_TPDEX(BV_DRAM_CTL40_TPDEX__##e)
+#define BFM_DRAM_CTL40_TPDEX_V(v)           BM_DRAM_CTL40_TPDEX
+#define BP_DRAM_CTL40_EMRS2_DATA_3          0
+#define BM_DRAM_CTL40_EMRS2_DATA_3          0x1fff
+#define BF_DRAM_CTL40_EMRS2_DATA_3(v)       (((v) & 0x1fff) << 0)
+#define BFM_DRAM_CTL40_EMRS2_DATA_3(v)      BM_DRAM_CTL40_EMRS2_DATA_3
+#define BF_DRAM_CTL40_EMRS2_DATA_3_V(e)     BF_DRAM_CTL40_EMRS2_DATA_3(BV_DRAM_CTL40_EMRS2_DATA_3__##e)
+#define BFM_DRAM_CTL40_EMRS2_DATA_3_V(v)    BM_DRAM_CTL40_EMRS2_DATA_3
+
+#endif /* __HEADERGEN_STMP3700_DRAM_H__*/
diff --git a/firmware/target/arm/imx233/regs/stmp3700/dri.h b/firmware/target/arm/imx233/regs/stmp3700/dri.h
new file mode 100644
index 0000000000..6846f03982
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3700/dri.h
@@ -0,0 +1,394 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * stmp3700 version: 2.4.0
+ * stmp3700 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_STMP3700_DRI_H__
+#define __HEADERGEN_STMP3700_DRI_H__
+
+#define HW_DRI_CTRL                                     HW(DRI_CTRL)
+#define HWA_DRI_CTRL                                    (0x80074000 + 0x0)
+#define HWT_DRI_CTRL                                    HWIO_32_RW
+#define HWN_DRI_CTRL                                    DRI_CTRL
+#define HWI_DRI_CTRL                                    
+#define HW_DRI_CTRL_SET                                 HW(DRI_CTRL_SET)
+#define HWA_DRI_CTRL_SET                                (HWA_DRI_CTRL + 0x4)
+#define HWT_DRI_CTRL_SET                                HWIO_32_WO
+#define HWN_DRI_CTRL_SET                                DRI_CTRL
+#define HWI_DRI_CTRL_SET                                
+#define HW_DRI_CTRL_CLR                                 HW(DRI_CTRL_CLR)
+#define HWA_DRI_CTRL_CLR                                (HWA_DRI_CTRL + 0x8)
+#define HWT_DRI_CTRL_CLR                                HWIO_32_WO
+#define HWN_DRI_CTRL_CLR                                DRI_CTRL
+#define HWI_DRI_CTRL_CLR                                
+#define HW_DRI_CTRL_TOG                                 HW(DRI_CTRL_TOG)
+#define HWA_DRI_CTRL_TOG                                (HWA_DRI_CTRL + 0xc)
+#define HWT_DRI_CTRL_TOG                                HWIO_32_WO
+#define HWN_DRI_CTRL_TOG                                DRI_CTRL
+#define HWI_DRI_CTRL_TOG                                
+#define BP_DRI_CTRL_SFTRST                              31
+#define BM_DRI_CTRL_SFTRST                              0x80000000
+#define BV_DRI_CTRL_SFTRST__RUN                         0x0
+#define BV_DRI_CTRL_SFTRST__RESET                       0x1
+#define BF_DRI_CTRL_SFTRST(v)                           (((v) & 0x1) << 31)
+#define BFM_DRI_CTRL_SFTRST(v)                          BM_DRI_CTRL_SFTRST
+#define BF_DRI_CTRL_SFTRST_V(e)                         BF_DRI_CTRL_SFTRST(BV_DRI_CTRL_SFTRST__##e)
+#define BFM_DRI_CTRL_SFTRST_V(v)                        BM_DRI_CTRL_SFTRST
+#define BP_DRI_CTRL_CLKGATE                             30
+#define BM_DRI_CTRL_CLKGATE                             0x40000000
+#define BV_DRI_CTRL_CLKGATE__RUN                        0x0
+#define BV_DRI_CTRL_CLKGATE__NO_CLKS                    0x1
+#define BF_DRI_CTRL_CLKGATE(v)                          (((v) & 0x1) << 30)
+#define BFM_DRI_CTRL_CLKGATE(v)                         BM_DRI_CTRL_CLKGATE
+#define BF_DRI_CTRL_CLKGATE_V(e)                        BF_DRI_CTRL_CLKGATE(BV_DRI_CTRL_CLKGATE__##e)
+#define BFM_DRI_CTRL_CLKGATE_V(v)                       BM_DRI_CTRL_CLKGATE
+#define BP_DRI_CTRL_ENABLE_INPUTS                       29
+#define BM_DRI_CTRL_ENABLE_INPUTS                       0x20000000
+#define BV_DRI_CTRL_ENABLE_INPUTS__ANALOG_LINE_IN       0x0
+#define BV_DRI_CTRL_ENABLE_INPUTS__DRI_DIGITAL_IN       0x1
+#define BF_DRI_CTRL_ENABLE_INPUTS(v)                    (((v) & 0x1) << 29)
+#define BFM_DRI_CTRL_ENABLE_INPUTS(v)                   BM_DRI_CTRL_ENABLE_INPUTS
+#define BF_DRI_CTRL_ENABLE_INPUTS_V(e)                  BF_DRI_CTRL_ENABLE_INPUTS(BV_DRI_CTRL_ENABLE_INPUTS__##e)
+#define BFM_DRI_CTRL_ENABLE_INPUTS_V(v)                 BM_DRI_CTRL_ENABLE_INPUTS
+#define BP_DRI_CTRL_STOP_ON_OFLOW_ERROR                 26
+#define BM_DRI_CTRL_STOP_ON_OFLOW_ERROR                 0x4000000
+#define BV_DRI_CTRL_STOP_ON_OFLOW_ERROR__IGNORE         0x0
+#define BV_DRI_CTRL_STOP_ON_OFLOW_ERROR__STOP           0x1
+#define BF_DRI_CTRL_STOP_ON_OFLOW_ERROR(v)              (((v) & 0x1) << 26)
+#define BFM_DRI_CTRL_STOP_ON_OFLOW_ERROR(v)             BM_DRI_CTRL_STOP_ON_OFLOW_ERROR
+#define BF_DRI_CTRL_STOP_ON_OFLOW_ERROR_V(e)            BF_DRI_CTRL_STOP_ON_OFLOW_ERROR(BV_DRI_CTRL_STOP_ON_OFLOW_ERROR__##e)
+#define BFM_DRI_CTRL_STOP_ON_OFLOW_ERROR_V(v)           BM_DRI_CTRL_STOP_ON_OFLOW_ERROR
+#define BP_DRI_CTRL_STOP_ON_PILOT_ERROR                 25
+#define BM_DRI_CTRL_STOP_ON_PILOT_ERROR                 0x2000000
+#define BV_DRI_CTRL_STOP_ON_PILOT_ERROR__IGNORE         0x0
+#define BV_DRI_CTRL_STOP_ON_PILOT_ERROR__STOP           0x1
+#define BF_DRI_CTRL_STOP_ON_PILOT_ERROR(v)              (((v) & 0x1) << 25)
+#define BFM_DRI_CTRL_STOP_ON_PILOT_ERROR(v)             BM_DRI_CTRL_STOP_ON_PILOT_ERROR
+#define BF_DRI_CTRL_STOP_ON_PILOT_ERROR_V(e)            BF_DRI_CTRL_STOP_ON_PILOT_ERROR(BV_DRI_CTRL_STOP_ON_PILOT_ERROR__##e)
+#define BFM_DRI_CTRL_STOP_ON_PILOT_ERROR_V(v)           BM_DRI_CTRL_STOP_ON_PILOT_ERROR
+#define BP_DRI_CTRL_DMA_DELAY_COUNT                     16
+#define BM_DRI_CTRL_DMA_DELAY_COUNT                     0x1f0000
+#define BF_DRI_CTRL_DMA_DELAY_COUNT(v)                  (((v) & 0x1f) << 16)
+#define BFM_DRI_CTRL_DMA_DELAY_COUNT(v)                 BM_DRI_CTRL_DMA_DELAY_COUNT
+#define BF_DRI_CTRL_DMA_DELAY_COUNT_V(e)                BF_DRI_CTRL_DMA_DELAY_COUNT(BV_DRI_CTRL_DMA_DELAY_COUNT__##e)
+#define BFM_DRI_CTRL_DMA_DELAY_COUNT_V(v)               BM_DRI_CTRL_DMA_DELAY_COUNT
+#define BP_DRI_CTRL_REACQUIRE_PHASE                     15
+#define BM_DRI_CTRL_REACQUIRE_PHASE                     0x8000
+#define BV_DRI_CTRL_REACQUIRE_PHASE__NORMAL             0x0
+#define BV_DRI_CTRL_REACQUIRE_PHASE__NEW_PHASE          0x1
+#define BF_DRI_CTRL_REACQUIRE_PHASE(v)                  (((v) & 0x1) << 15)
+#define BFM_DRI_CTRL_REACQUIRE_PHASE(v)                 BM_DRI_CTRL_REACQUIRE_PHASE
+#define BF_DRI_CTRL_REACQUIRE_PHASE_V(e)                BF_DRI_CTRL_REACQUIRE_PHASE(BV_DRI_CTRL_REACQUIRE_PHASE__##e)
+#define BFM_DRI_CTRL_REACQUIRE_PHASE_V(v)               BM_DRI_CTRL_REACQUIRE_PHASE
+#define BP_DRI_CTRL_OVERFLOW_IRQ_EN                     11
+#define BM_DRI_CTRL_OVERFLOW_IRQ_EN                     0x800
+#define BV_DRI_CTRL_OVERFLOW_IRQ_EN__DISABLED           0x0
+#define BV_DRI_CTRL_OVERFLOW_IRQ_EN__ENABLED            0x1
+#define BF_DRI_CTRL_OVERFLOW_IRQ_EN(v)                  (((v) & 0x1) << 11)
+#define BFM_DRI_CTRL_OVERFLOW_IRQ_EN(v)                 BM_DRI_CTRL_OVERFLOW_IRQ_EN
+#define BF_DRI_CTRL_OVERFLOW_IRQ_EN_V(e)                BF_DRI_CTRL_OVERFLOW_IRQ_EN(BV_DRI_CTRL_OVERFLOW_IRQ_EN__##e)
+#define BFM_DRI_CTRL_OVERFLOW_IRQ_EN_V(v)               BM_DRI_CTRL_OVERFLOW_IRQ_EN
+#define BP_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN              10
+#define BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN              0x400
+#define BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN__DISABLED    0x0
+#define BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN__ENABLED     0x1
+#define BF_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN(v)           (((v) & 0x1) << 10)
+#define BFM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN(v)          BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN
+#define BF_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN_V(e)         BF_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN(BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN__##e)
+#define BFM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN_V(v)        BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN
+#define BP_DRI_CTRL_ATTENTION_IRQ_EN                    9
+#define BM_DRI_CTRL_ATTENTION_IRQ_EN                    0x200
+#define BV_DRI_CTRL_ATTENTION_IRQ_EN__DISABLED          0x0
+#define BV_DRI_CTRL_ATTENTION_IRQ_EN__ENABLED           0x1
+#define BF_DRI_CTRL_ATTENTION_IRQ_EN(v)                 (((v) & 0x1) << 9)
+#define BFM_DRI_CTRL_ATTENTION_IRQ_EN(v)                BM_DRI_CTRL_ATTENTION_IRQ_EN
+#define BF_DRI_CTRL_ATTENTION_IRQ_EN_V(e)               BF_DRI_CTRL_ATTENTION_IRQ_EN(BV_DRI_CTRL_ATTENTION_IRQ_EN__##e)
+#define BFM_DRI_CTRL_ATTENTION_IRQ_EN_V(v)              BM_DRI_CTRL_ATTENTION_IRQ_EN
+#define BP_DRI_CTRL_OVERFLOW_IRQ                        3
+#define BM_DRI_CTRL_OVERFLOW_IRQ                        0x8
+#define BV_DRI_CTRL_OVERFLOW_IRQ__NO_REQUEST            0x0
+#define BV_DRI_CTRL_OVERFLOW_IRQ__REQUEST               0x1
+#define BF_DRI_CTRL_OVERFLOW_IRQ(v)                     (((v) & 0x1) << 3)
+#define BFM_DRI_CTRL_OVERFLOW_IRQ(v)                    BM_DRI_CTRL_OVERFLOW_IRQ
+#define BF_DRI_CTRL_OVERFLOW_IRQ_V(e)                   BF_DRI_CTRL_OVERFLOW_IRQ(BV_DRI_CTRL_OVERFLOW_IRQ__##e)
+#define BFM_DRI_CTRL_OVERFLOW_IRQ_V(v)                  BM_DRI_CTRL_OVERFLOW_IRQ
+#define BP_DRI_CTRL_PILOT_SYNC_LOSS_IRQ                 2
+#define BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ                 0x4
+#define BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ__NO_REQUEST     0x0
+#define BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ__REQUEST        0x1
+#define BF_DRI_CTRL_PILOT_SYNC_LOSS_IRQ(v)              (((v) & 0x1) << 2)
+#define BFM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ(v)             BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ
+#define BF_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_V(e)            BF_DRI_CTRL_PILOT_SYNC_LOSS_IRQ(BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ__##e)
+#define BFM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_V(v)           BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ
+#define BP_DRI_CTRL_ATTENTION_IRQ                       1
+#define BM_DRI_CTRL_ATTENTION_IRQ                       0x2
+#define BV_DRI_CTRL_ATTENTION_IRQ__NO_REQUEST           0x0
+#define BV_DRI_CTRL_ATTENTION_IRQ__REQUEST              0x1
+#define BF_DRI_CTRL_ATTENTION_IRQ(v)                    (((v) & 0x1) << 1)
+#define BFM_DRI_CTRL_ATTENTION_IRQ(v)                   BM_DRI_CTRL_ATTENTION_IRQ
+#define BF_DRI_CTRL_ATTENTION_IRQ_V(e)                  BF_DRI_CTRL_ATTENTION_IRQ(BV_DRI_CTRL_ATTENTION_IRQ__##e)
+#define BFM_DRI_CTRL_ATTENTION_IRQ_V(v)                 BM_DRI_CTRL_ATTENTION_IRQ
+#define BP_DRI_CTRL_RUN                                 0
+#define BM_DRI_CTRL_RUN                                 0x1
+#define BV_DRI_CTRL_RUN__HALT                           0x0
+#define BV_DRI_CTRL_RUN__RUN                            0x1
+#define BF_DRI_CTRL_RUN(v)                              (((v) & 0x1) << 0)
+#define BFM_DRI_CTRL_RUN(v)                             BM_DRI_CTRL_RUN
+#define BF_DRI_CTRL_RUN_V(e)                            BF_DRI_CTRL_RUN(BV_DRI_CTRL_RUN__##e)
+#define BFM_DRI_CTRL_RUN_V(v)                           BM_DRI_CTRL_RUN
+
+#define HW_DRI_TIMING                               HW(DRI_TIMING)
+#define HWA_DRI_TIMING                              (0x80074000 + 0x10)
+#define HWT_DRI_TIMING                              HWIO_32_RW
+#define HWN_DRI_TIMING                              DRI_TIMING
+#define HWI_DRI_TIMING                              
+#define BP_DRI_TIMING_PILOT_REP_RATE                16
+#define BM_DRI_TIMING_PILOT_REP_RATE                0xf0000
+#define BF_DRI_TIMING_PILOT_REP_RATE(v)             (((v) & 0xf) << 16)
+#define BFM_DRI_TIMING_PILOT_REP_RATE(v)            BM_DRI_TIMING_PILOT_REP_RATE
+#define BF_DRI_TIMING_PILOT_REP_RATE_V(e)           BF_DRI_TIMING_PILOT_REP_RATE(BV_DRI_TIMING_PILOT_REP_RATE__##e)
+#define BFM_DRI_TIMING_PILOT_REP_RATE_V(v)          BM_DRI_TIMING_PILOT_REP_RATE
+#define BP_DRI_TIMING_GAP_DETECTION_INTERVAL        0
+#define BM_DRI_TIMING_GAP_DETECTION_INTERVAL        0xff
+#define BF_DRI_TIMING_GAP_DETECTION_INTERVAL(v)     (((v) & 0xff) << 0)
+#define BFM_DRI_TIMING_GAP_DETECTION_INTERVAL(v)    BM_DRI_TIMING_GAP_DETECTION_INTERVAL
+#define BF_DRI_TIMING_GAP_DETECTION_INTERVAL_V(e)   BF_DRI_TIMING_GAP_DETECTION_INTERVAL(BV_DRI_TIMING_GAP_DETECTION_INTERVAL__##e)
+#define BFM_DRI_TIMING_GAP_DETECTION_INTERVAL_V(v)  BM_DRI_TIMING_GAP_DETECTION_INTERVAL
+
+#define HW_DRI_STAT                                         HW(DRI_STAT)
+#define HWA_DRI_STAT                                        (0x80074000 + 0x20)
+#define HWT_DRI_STAT                                        HWIO_32_RW
+#define HWN_DRI_STAT                                        DRI_STAT
+#define HWI_DRI_STAT                                        
+#define BP_DRI_STAT_DRI_PRESENT                             31
+#define BM_DRI_STAT_DRI_PRESENT                             0x80000000
+#define BV_DRI_STAT_DRI_PRESENT__UNAVAILABLE                0x0
+#define BV_DRI_STAT_DRI_PRESENT__AVAILABLE                  0x1
+#define BF_DRI_STAT_DRI_PRESENT(v)                          (((v) & 0x1) << 31)
+#define BFM_DRI_STAT_DRI_PRESENT(v)                         BM_DRI_STAT_DRI_PRESENT
+#define BF_DRI_STAT_DRI_PRESENT_V(e)                        BF_DRI_STAT_DRI_PRESENT(BV_DRI_STAT_DRI_PRESENT__##e)
+#define BFM_DRI_STAT_DRI_PRESENT_V(v)                       BM_DRI_STAT_DRI_PRESENT
+#define BP_DRI_STAT_PILOT_PHASE                             16
+#define BM_DRI_STAT_PILOT_PHASE                             0xf0000
+#define BF_DRI_STAT_PILOT_PHASE(v)                          (((v) & 0xf) << 16)
+#define BFM_DRI_STAT_PILOT_PHASE(v)                         BM_DRI_STAT_PILOT_PHASE
+#define BF_DRI_STAT_PILOT_PHASE_V(e)                        BF_DRI_STAT_PILOT_PHASE(BV_DRI_STAT_PILOT_PHASE__##e)
+#define BFM_DRI_STAT_PILOT_PHASE_V(v)                       BM_DRI_STAT_PILOT_PHASE
+#define BP_DRI_STAT_OVERFLOW_IRQ_SUMMARY                    3
+#define BM_DRI_STAT_OVERFLOW_IRQ_SUMMARY                    0x8
+#define BV_DRI_STAT_OVERFLOW_IRQ_SUMMARY__NO_REQUEST        0x0
+#define BV_DRI_STAT_OVERFLOW_IRQ_SUMMARY__REQUEST           0x1
+#define BF_DRI_STAT_OVERFLOW_IRQ_SUMMARY(v)                 (((v) & 0x1) << 3)
+#define BFM_DRI_STAT_OVERFLOW_IRQ_SUMMARY(v)                BM_DRI_STAT_OVERFLOW_IRQ_SUMMARY
+#define BF_DRI_STAT_OVERFLOW_IRQ_SUMMARY_V(e)               BF_DRI_STAT_OVERFLOW_IRQ_SUMMARY(BV_DRI_STAT_OVERFLOW_IRQ_SUMMARY__##e)
+#define BFM_DRI_STAT_OVERFLOW_IRQ_SUMMARY_V(v)              BM_DRI_STAT_OVERFLOW_IRQ_SUMMARY
+#define BP_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY             2
+#define BM_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY             0x4
+#define BV_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY__NO_REQUEST 0x0
+#define BV_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY__REQUEST    0x1
+#define BF_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY(v)          (((v) & 0x1) << 2)
+#define BFM_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY(v)         BM_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY
+#define BF_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY_V(e)        BF_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY(BV_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY__##e)
+#define BFM_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY_V(v)       BM_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY
+#define BP_DRI_STAT_ATTENTION_IRQ_SUMMARY                   1
+#define BM_DRI_STAT_ATTENTION_IRQ_SUMMARY                   0x2
+#define BV_DRI_STAT_ATTENTION_IRQ_SUMMARY__NO_REQUEST       0x0
+#define BV_DRI_STAT_ATTENTION_IRQ_SUMMARY__REQUEST          0x1
+#define BF_DRI_STAT_ATTENTION_IRQ_SUMMARY(v)                (((v) & 0x1) << 1)
+#define BFM_DRI_STAT_ATTENTION_IRQ_SUMMARY(v)               BM_DRI_STAT_ATTENTION_IRQ_SUMMARY
+#define BF_DRI_STAT_ATTENTION_IRQ_SUMMARY_V(e)              BF_DRI_STAT_ATTENTION_IRQ_SUMMARY(BV_DRI_STAT_ATTENTION_IRQ_SUMMARY__##e)
+#define BFM_DRI_STAT_ATTENTION_IRQ_SUMMARY_V(v)             BM_DRI_STAT_ATTENTION_IRQ_SUMMARY
+
+#define HW_DRI_DATA             HW(DRI_DATA)
+#define HWA_DRI_DATA            (0x80074000 + 0x30)
+#define HWT_DRI_DATA            HWIO_32_RW
+#define HWN_DRI_DATA            DRI_DATA
+#define HWI_DRI_DATA            
+#define BP_DRI_DATA_DATA        0
+#define BM_DRI_DATA_DATA        0xffffffff
+#define BF_DRI_DATA_DATA(v)     (((v) & 0xffffffff) << 0)
+#define BFM_DRI_DATA_DATA(v)    BM_DRI_DATA_DATA
+#define BF_DRI_DATA_DATA_V(e)   BF_DRI_DATA_DATA(BV_DRI_DATA_DATA__##e)
+#define BFM_DRI_DATA_DATA_V(v)  BM_DRI_DATA_DATA
+
+#define HW_DRI_DEBUG0                               HW(DRI_DEBUG0)
+#define HWA_DRI_DEBUG0                              (0x80074000 + 0x40)
+#define HWT_DRI_DEBUG0                              HWIO_32_RW
+#define HWN_DRI_DEBUG0                              DRI_DEBUG0
+#define HWI_DRI_DEBUG0                              
+#define HW_DRI_DEBUG0_SET                           HW(DRI_DEBUG0_SET)
+#define HWA_DRI_DEBUG0_SET                          (HWA_DRI_DEBUG0 + 0x4)
+#define HWT_DRI_DEBUG0_SET                          HWIO_32_WO
+#define HWN_DRI_DEBUG0_SET                          DRI_DEBUG0
+#define HWI_DRI_DEBUG0_SET                          
+#define HW_DRI_DEBUG0_CLR                           HW(DRI_DEBUG0_CLR)
+#define HWA_DRI_DEBUG0_CLR                          (HWA_DRI_DEBUG0 + 0x8)
+#define HWT_DRI_DEBUG0_CLR                          HWIO_32_WO
+#define HWN_DRI_DEBUG0_CLR                          DRI_DEBUG0
+#define HWI_DRI_DEBUG0_CLR                          
+#define HW_DRI_DEBUG0_TOG                           HW(DRI_DEBUG0_TOG)
+#define HWA_DRI_DEBUG0_TOG                          (HWA_DRI_DEBUG0 + 0xc)
+#define HWT_DRI_DEBUG0_TOG                          HWIO_32_WO
+#define HWN_DRI_DEBUG0_TOG                          DRI_DEBUG0
+#define HWI_DRI_DEBUG0_TOG                          
+#define BP_DRI_DEBUG0_DMAREQ                        31
+#define BM_DRI_DEBUG0_DMAREQ                        0x80000000
+#define BF_DRI_DEBUG0_DMAREQ(v)                     (((v) & 0x1) << 31)
+#define BFM_DRI_DEBUG0_DMAREQ(v)                    BM_DRI_DEBUG0_DMAREQ
+#define BF_DRI_DEBUG0_DMAREQ_V(e)                   BF_DRI_DEBUG0_DMAREQ(BV_DRI_DEBUG0_DMAREQ__##e)
+#define BFM_DRI_DEBUG0_DMAREQ_V(v)                  BM_DRI_DEBUG0_DMAREQ
+#define BP_DRI_DEBUG0_DMACMDKICK                    30
+#define BM_DRI_DEBUG0_DMACMDKICK                    0x40000000
+#define BF_DRI_DEBUG0_DMACMDKICK(v)                 (((v) & 0x1) << 30)
+#define BFM_DRI_DEBUG0_DMACMDKICK(v)                BM_DRI_DEBUG0_DMACMDKICK
+#define BF_DRI_DEBUG0_DMACMDKICK_V(e)               BF_DRI_DEBUG0_DMACMDKICK(BV_DRI_DEBUG0_DMACMDKICK__##e)
+#define BFM_DRI_DEBUG0_DMACMDKICK_V(v)              BM_DRI_DEBUG0_DMACMDKICK
+#define BP_DRI_DEBUG0_DRI_CLK_INPUT                 29
+#define BM_DRI_DEBUG0_DRI_CLK_INPUT                 0x20000000
+#define BF_DRI_DEBUG0_DRI_CLK_INPUT(v)              (((v) & 0x1) << 29)
+#define BFM_DRI_DEBUG0_DRI_CLK_INPUT(v)             BM_DRI_DEBUG0_DRI_CLK_INPUT
+#define BF_DRI_DEBUG0_DRI_CLK_INPUT_V(e)            BF_DRI_DEBUG0_DRI_CLK_INPUT(BV_DRI_DEBUG0_DRI_CLK_INPUT__##e)
+#define BFM_DRI_DEBUG0_DRI_CLK_INPUT_V(v)           BM_DRI_DEBUG0_DRI_CLK_INPUT
+#define BP_DRI_DEBUG0_DRI_DATA_INPUT                28
+#define BM_DRI_DEBUG0_DRI_DATA_INPUT                0x10000000
+#define BF_DRI_DEBUG0_DRI_DATA_INPUT(v)             (((v) & 0x1) << 28)
+#define BFM_DRI_DEBUG0_DRI_DATA_INPUT(v)            BM_DRI_DEBUG0_DRI_DATA_INPUT
+#define BF_DRI_DEBUG0_DRI_DATA_INPUT_V(e)           BF_DRI_DEBUG0_DRI_DATA_INPUT(BV_DRI_DEBUG0_DRI_DATA_INPUT__##e)
+#define BFM_DRI_DEBUG0_DRI_DATA_INPUT_V(v)          BM_DRI_DEBUG0_DRI_DATA_INPUT
+#define BP_DRI_DEBUG0_TEST_MODE                     27
+#define BM_DRI_DEBUG0_TEST_MODE                     0x8000000
+#define BF_DRI_DEBUG0_TEST_MODE(v)                  (((v) & 0x1) << 27)
+#define BFM_DRI_DEBUG0_TEST_MODE(v)                 BM_DRI_DEBUG0_TEST_MODE
+#define BF_DRI_DEBUG0_TEST_MODE_V(e)                BF_DRI_DEBUG0_TEST_MODE(BV_DRI_DEBUG0_TEST_MODE__##e)
+#define BFM_DRI_DEBUG0_TEST_MODE_V(v)               BM_DRI_DEBUG0_TEST_MODE
+#define BP_DRI_DEBUG0_PILOT_REP_RATE                26
+#define BM_DRI_DEBUG0_PILOT_REP_RATE                0x4000000
+#define BV_DRI_DEBUG0_PILOT_REP_RATE__8_AT_4MHZ     0x0
+#define BV_DRI_DEBUG0_PILOT_REP_RATE__12_AT_6MHZ    0x1
+#define BF_DRI_DEBUG0_PILOT_REP_RATE(v)             (((v) & 0x1) << 26)
+#define BFM_DRI_DEBUG0_PILOT_REP_RATE(v)            BM_DRI_DEBUG0_PILOT_REP_RATE
+#define BF_DRI_DEBUG0_PILOT_REP_RATE_V(e)           BF_DRI_DEBUG0_PILOT_REP_RATE(BV_DRI_DEBUG0_PILOT_REP_RATE__##e)
+#define BFM_DRI_DEBUG0_PILOT_REP_RATE_V(v)          BM_DRI_DEBUG0_PILOT_REP_RATE
+#define BP_DRI_DEBUG0_SPARE                         18
+#define BM_DRI_DEBUG0_SPARE                         0x3fc0000
+#define BF_DRI_DEBUG0_SPARE(v)                      (((v) & 0xff) << 18)
+#define BFM_DRI_DEBUG0_SPARE(v)                     BM_DRI_DEBUG0_SPARE
+#define BF_DRI_DEBUG0_SPARE_V(e)                    BF_DRI_DEBUG0_SPARE(BV_DRI_DEBUG0_SPARE__##e)
+#define BFM_DRI_DEBUG0_SPARE_V(v)                   BM_DRI_DEBUG0_SPARE
+#define BP_DRI_DEBUG0_FRAME                         0
+#define BM_DRI_DEBUG0_FRAME                         0x3ffff
+#define BF_DRI_DEBUG0_FRAME(v)                      (((v) & 0x3ffff) << 0)
+#define BFM_DRI_DEBUG0_FRAME(v)                     BM_DRI_DEBUG0_FRAME
+#define BF_DRI_DEBUG0_FRAME_V(e)                    BF_DRI_DEBUG0_FRAME(BV_DRI_DEBUG0_FRAME__##e)
+#define BFM_DRI_DEBUG0_FRAME_V(v)                   BM_DRI_DEBUG0_FRAME
+
+#define HW_DRI_DEBUG1                               HW(DRI_DEBUG1)
+#define HWA_DRI_DEBUG1                              (0x80074000 + 0x50)
+#define HWT_DRI_DEBUG1                              HWIO_32_RW
+#define HWN_DRI_DEBUG1                              DRI_DEBUG1
+#define HWI_DRI_DEBUG1                              
+#define HW_DRI_DEBUG1_SET                           HW(DRI_DEBUG1_SET)
+#define HWA_DRI_DEBUG1_SET                          (HWA_DRI_DEBUG1 + 0x4)
+#define HWT_DRI_DEBUG1_SET                          HWIO_32_WO
+#define HWN_DRI_DEBUG1_SET                          DRI_DEBUG1
+#define HWI_DRI_DEBUG1_SET                          
+#define HW_DRI_DEBUG1_CLR                           HW(DRI_DEBUG1_CLR)
+#define HWA_DRI_DEBUG1_CLR                          (HWA_DRI_DEBUG1 + 0x8)
+#define HWT_DRI_DEBUG1_CLR                          HWIO_32_WO
+#define HWN_DRI_DEBUG1_CLR                          DRI_DEBUG1
+#define HWI_DRI_DEBUG1_CLR                          
+#define HW_DRI_DEBUG1_TOG                           HW(DRI_DEBUG1_TOG)
+#define HWA_DRI_DEBUG1_TOG                          (HWA_DRI_DEBUG1 + 0xc)
+#define HWT_DRI_DEBUG1_TOG                          HWIO_32_WO
+#define HWN_DRI_DEBUG1_TOG                          DRI_DEBUG1
+#define HWI_DRI_DEBUG1_TOG                          
+#define BP_DRI_DEBUG1_INVERT_PILOT                  31
+#define BM_DRI_DEBUG1_INVERT_PILOT                  0x80000000
+#define BV_DRI_DEBUG1_INVERT_PILOT__NORMAL          0x0
+#define BV_DRI_DEBUG1_INVERT_PILOT__INVERTED        0x1
+#define BF_DRI_DEBUG1_INVERT_PILOT(v)               (((v) & 0x1) << 31)
+#define BFM_DRI_DEBUG1_INVERT_PILOT(v)              BM_DRI_DEBUG1_INVERT_PILOT
+#define BF_DRI_DEBUG1_INVERT_PILOT_V(e)             BF_DRI_DEBUG1_INVERT_PILOT(BV_DRI_DEBUG1_INVERT_PILOT__##e)
+#define BFM_DRI_DEBUG1_INVERT_PILOT_V(v)            BM_DRI_DEBUG1_INVERT_PILOT
+#define BP_DRI_DEBUG1_INVERT_ATTENTION              30
+#define BM_DRI_DEBUG1_INVERT_ATTENTION              0x40000000
+#define BV_DRI_DEBUG1_INVERT_ATTENTION__NORMAL      0x0
+#define BV_DRI_DEBUG1_INVERT_ATTENTION__INVERTED    0x1
+#define BF_DRI_DEBUG1_INVERT_ATTENTION(v)           (((v) & 0x1) << 30)
+#define BFM_DRI_DEBUG1_INVERT_ATTENTION(v)          BM_DRI_DEBUG1_INVERT_ATTENTION
+#define BF_DRI_DEBUG1_INVERT_ATTENTION_V(e)         BF_DRI_DEBUG1_INVERT_ATTENTION(BV_DRI_DEBUG1_INVERT_ATTENTION__##e)
+#define BFM_DRI_DEBUG1_INVERT_ATTENTION_V(v)        BM_DRI_DEBUG1_INVERT_ATTENTION
+#define BP_DRI_DEBUG1_INVERT_DRI_DATA               29
+#define BM_DRI_DEBUG1_INVERT_DRI_DATA               0x20000000
+#define BV_DRI_DEBUG1_INVERT_DRI_DATA__NORMAL       0x0
+#define BV_DRI_DEBUG1_INVERT_DRI_DATA__INVERTED     0x1
+#define BF_DRI_DEBUG1_INVERT_DRI_DATA(v)            (((v) & 0x1) << 29)
+#define BFM_DRI_DEBUG1_INVERT_DRI_DATA(v)           BM_DRI_DEBUG1_INVERT_DRI_DATA
+#define BF_DRI_DEBUG1_INVERT_DRI_DATA_V(e)          BF_DRI_DEBUG1_INVERT_DRI_DATA(BV_DRI_DEBUG1_INVERT_DRI_DATA__##e)
+#define BFM_DRI_DEBUG1_INVERT_DRI_DATA_V(v)         BM_DRI_DEBUG1_INVERT_DRI_DATA
+#define BP_DRI_DEBUG1_INVERT_DRI_CLOCK              28
+#define BM_DRI_DEBUG1_INVERT_DRI_CLOCK              0x10000000
+#define BV_DRI_DEBUG1_INVERT_DRI_CLOCK__NORMAL      0x0
+#define BV_DRI_DEBUG1_INVERT_DRI_CLOCK__INVERTED    0x1
+#define BF_DRI_DEBUG1_INVERT_DRI_CLOCK(v)           (((v) & 0x1) << 28)
+#define BFM_DRI_DEBUG1_INVERT_DRI_CLOCK(v)          BM_DRI_DEBUG1_INVERT_DRI_CLOCK
+#define BF_DRI_DEBUG1_INVERT_DRI_CLOCK_V(e)         BF_DRI_DEBUG1_INVERT_DRI_CLOCK(BV_DRI_DEBUG1_INVERT_DRI_CLOCK__##e)
+#define BFM_DRI_DEBUG1_INVERT_DRI_CLOCK_V(v)        BM_DRI_DEBUG1_INVERT_DRI_CLOCK
+#define BP_DRI_DEBUG1_REVERSE_FRAME                 27
+#define BM_DRI_DEBUG1_REVERSE_FRAME                 0x8000000
+#define BV_DRI_DEBUG1_REVERSE_FRAME__NORMAL         0x0
+#define BV_DRI_DEBUG1_REVERSE_FRAME__REVERSED       0x1
+#define BF_DRI_DEBUG1_REVERSE_FRAME(v)              (((v) & 0x1) << 27)
+#define BFM_DRI_DEBUG1_REVERSE_FRAME(v)             BM_DRI_DEBUG1_REVERSE_FRAME
+#define BF_DRI_DEBUG1_REVERSE_FRAME_V(e)            BF_DRI_DEBUG1_REVERSE_FRAME(BV_DRI_DEBUG1_REVERSE_FRAME__##e)
+#define BFM_DRI_DEBUG1_REVERSE_FRAME_V(v)           BM_DRI_DEBUG1_REVERSE_FRAME
+#define BP_DRI_DEBUG1_SWIZZLED_FRAME                0
+#define BM_DRI_DEBUG1_SWIZZLED_FRAME                0x3ffff
+#define BF_DRI_DEBUG1_SWIZZLED_FRAME(v)             (((v) & 0x3ffff) << 0)
+#define BFM_DRI_DEBUG1_SWIZZLED_FRAME(v)            BM_DRI_DEBUG1_SWIZZLED_FRAME
+#define BF_DRI_DEBUG1_SWIZZLED_FRAME_V(e)           BF_DRI_DEBUG1_SWIZZLED_FRAME(BV_DRI_DEBUG1_SWIZZLED_FRAME__##e)
+#define BFM_DRI_DEBUG1_SWIZZLED_FRAME_V(v)          BM_DRI_DEBUG1_SWIZZLED_FRAME
+
+#define HW_DRI_VERSION              HW(DRI_VERSION)
+#define HWA_DRI_VERSION             (0x80074000 + 0x60)
+#define HWT_DRI_VERSION             HWIO_32_RW
+#define HWN_DRI_VERSION             DRI_VERSION
+#define HWI_DRI_VERSION             
+#define BP_DRI_VERSION_MAJOR        24
+#define BM_DRI_VERSION_MAJOR        0xff000000
+#define BF_DRI_VERSION_MAJOR(v)     (((v) & 0xff) << 24)
+#define BFM_DRI_VERSION_MAJOR(v)    BM_DRI_VERSION_MAJOR
+#define BF_DRI_VERSION_MAJOR_V(e)   BF_DRI_VERSION_MAJOR(BV_DRI_VERSION_MAJOR__##e)
+#define BFM_DRI_VERSION_MAJOR_V(v)  BM_DRI_VERSION_MAJOR
+#define BP_DRI_VERSION_MINOR        16
+#define BM_DRI_VERSION_MINOR        0xff0000
+#define BF_DRI_VERSION_MINOR(v)     (((v) & 0xff) << 16)
+#define BFM_DRI_VERSION_MINOR(v)    BM_DRI_VERSION_MINOR
+#define BF_DRI_VERSION_MINOR_V(e)   BF_DRI_VERSION_MINOR(BV_DRI_VERSION_MINOR__##e)
+#define BFM_DRI_VERSION_MINOR_V(v)  BM_DRI_VERSION_MINOR
+#define BP_DRI_VERSION_STEP         0
+#define BM_DRI_VERSION_STEP         0xffff
+#define BF_DRI_VERSION_STEP(v)      (((v) & 0xffff) << 0)
+#define BFM_DRI_VERSION_STEP(v)     BM_DRI_VERSION_STEP
+#define BF_DRI_VERSION_STEP_V(e)    BF_DRI_VERSION_STEP(BV_DRI_VERSION_STEP__##e)
+#define BFM_DRI_VERSION_STEP_V(v)   BM_DRI_VERSION_STEP
+
+#endif /* __HEADERGEN_STMP3700_DRI_H__*/
diff --git a/firmware/target/arm/imx233/regs/stmp3700/ecc8.h b/firmware/target/arm/imx233/regs/stmp3700/ecc8.h
new file mode 100644
index 0000000000..128b886c0d
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3700/ecc8.h
@@ -0,0 +1,521 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * stmp3700 version: 2.4.0
+ * stmp3700 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_STMP3700_ECC8_H__
+#define __HEADERGEN_STMP3700_ECC8_H__
+
+#define HW_ECC8_CTRL                            HW(ECC8_CTRL)
+#define HWA_ECC8_CTRL                           (0x80008000 + 0x0)
+#define HWT_ECC8_CTRL                           HWIO_32_RW
+#define HWN_ECC8_CTRL                           ECC8_CTRL
+#define HWI_ECC8_CTRL                           
+#define HW_ECC8_CTRL_SET                        HW(ECC8_CTRL_SET)
+#define HWA_ECC8_CTRL_SET                       (HWA_ECC8_CTRL + 0x4)
+#define HWT_ECC8_CTRL_SET                       HWIO_32_WO
+#define HWN_ECC8_CTRL_SET                       ECC8_CTRL
+#define HWI_ECC8_CTRL_SET                       
+#define HW_ECC8_CTRL_CLR                        HW(ECC8_CTRL_CLR)
+#define HWA_ECC8_CTRL_CLR                       (HWA_ECC8_CTRL + 0x8)
+#define HWT_ECC8_CTRL_CLR                       HWIO_32_WO
+#define HWN_ECC8_CTRL_CLR                       ECC8_CTRL
+#define HWI_ECC8_CTRL_CLR                       
+#define HW_ECC8_CTRL_TOG                        HW(ECC8_CTRL_TOG)
+#define HWA_ECC8_CTRL_TOG                       (HWA_ECC8_CTRL + 0xc)
+#define HWT_ECC8_CTRL_TOG                       HWIO_32_WO
+#define HWN_ECC8_CTRL_TOG                       ECC8_CTRL
+#define HWI_ECC8_CTRL_TOG                       
+#define BP_ECC8_CTRL_SFTRST                     31
+#define BM_ECC8_CTRL_SFTRST                     0x80000000
+#define BV_ECC8_CTRL_SFTRST__RUN                0x0
+#define BV_ECC8_CTRL_SFTRST__RESET              0x1
+#define BF_ECC8_CTRL_SFTRST(v)                  (((v) & 0x1) << 31)
+#define BFM_ECC8_CTRL_SFTRST(v)                 BM_ECC8_CTRL_SFTRST
+#define BF_ECC8_CTRL_SFTRST_V(e)                BF_ECC8_CTRL_SFTRST(BV_ECC8_CTRL_SFTRST__##e)
+#define BFM_ECC8_CTRL_SFTRST_V(v)               BM_ECC8_CTRL_SFTRST
+#define BP_ECC8_CTRL_CLKGATE                    30
+#define BM_ECC8_CTRL_CLKGATE                    0x40000000
+#define BV_ECC8_CTRL_CLKGATE__RUN               0x0
+#define BV_ECC8_CTRL_CLKGATE__NO_CLKS           0x1
+#define BF_ECC8_CTRL_CLKGATE(v)                 (((v) & 0x1) << 30)
+#define BFM_ECC8_CTRL_CLKGATE(v)                BM_ECC8_CTRL_CLKGATE
+#define BF_ECC8_CTRL_CLKGATE_V(e)               BF_ECC8_CTRL_CLKGATE(BV_ECC8_CTRL_CLKGATE__##e)
+#define BFM_ECC8_CTRL_CLKGATE_V(v)              BM_ECC8_CTRL_CLKGATE
+#define BP_ECC8_CTRL_AHBM_SFTRST                29
+#define BM_ECC8_CTRL_AHBM_SFTRST                0x20000000
+#define BV_ECC8_CTRL_AHBM_SFTRST__RUN           0x0
+#define BV_ECC8_CTRL_AHBM_SFTRST__RESET         0x1
+#define BF_ECC8_CTRL_AHBM_SFTRST(v)             (((v) & 0x1) << 29)
+#define BFM_ECC8_CTRL_AHBM_SFTRST(v)            BM_ECC8_CTRL_AHBM_SFTRST
+#define BF_ECC8_CTRL_AHBM_SFTRST_V(e)           BF_ECC8_CTRL_AHBM_SFTRST(BV_ECC8_CTRL_AHBM_SFTRST__##e)
+#define BFM_ECC8_CTRL_AHBM_SFTRST_V(v)          BM_ECC8_CTRL_AHBM_SFTRST
+#define BP_ECC8_CTRL_THROTTLE                   24
+#define BM_ECC8_CTRL_THROTTLE                   0xf000000
+#define BF_ECC8_CTRL_THROTTLE(v)                (((v) & 0xf) << 24)
+#define BFM_ECC8_CTRL_THROTTLE(v)               BM_ECC8_CTRL_THROTTLE
+#define BF_ECC8_CTRL_THROTTLE_V(e)              BF_ECC8_CTRL_THROTTLE(BV_ECC8_CTRL_THROTTLE__##e)
+#define BFM_ECC8_CTRL_THROTTLE_V(v)             BM_ECC8_CTRL_THROTTLE
+#define BP_ECC8_CTRL_DEBUG_STALL_IRQ_EN         10
+#define BM_ECC8_CTRL_DEBUG_STALL_IRQ_EN         0x400
+#define BF_ECC8_CTRL_DEBUG_STALL_IRQ_EN(v)      (((v) & 0x1) << 10)
+#define BFM_ECC8_CTRL_DEBUG_STALL_IRQ_EN(v)     BM_ECC8_CTRL_DEBUG_STALL_IRQ_EN
+#define BF_ECC8_CTRL_DEBUG_STALL_IRQ_EN_V(e)    BF_ECC8_CTRL_DEBUG_STALL_IRQ_EN(BV_ECC8_CTRL_DEBUG_STALL_IRQ_EN__##e)
+#define BFM_ECC8_CTRL_DEBUG_STALL_IRQ_EN_V(v)   BM_ECC8_CTRL_DEBUG_STALL_IRQ_EN
+#define BP_ECC8_CTRL_DEBUG_WRITE_IRQ_EN         9
+#define BM_ECC8_CTRL_DEBUG_WRITE_IRQ_EN         0x200
+#define BF_ECC8_CTRL_DEBUG_WRITE_IRQ_EN(v)      (((v) & 0x1) << 9)
+#define BFM_ECC8_CTRL_DEBUG_WRITE_IRQ_EN(v)     BM_ECC8_CTRL_DEBUG_WRITE_IRQ_EN
+#define BF_ECC8_CTRL_DEBUG_WRITE_IRQ_EN_V(e)    BF_ECC8_CTRL_DEBUG_WRITE_IRQ_EN(BV_ECC8_CTRL_DEBUG_WRITE_IRQ_EN__##e)
+#define BFM_ECC8_CTRL_DEBUG_WRITE_IRQ_EN_V(v)   BM_ECC8_CTRL_DEBUG_WRITE_IRQ_EN
+#define BP_ECC8_CTRL_COMPLETE_IRQ_EN            8
+#define BM_ECC8_CTRL_COMPLETE_IRQ_EN            0x100
+#define BF_ECC8_CTRL_COMPLETE_IRQ_EN(v)         (((v) & 0x1) << 8)
+#define BFM_ECC8_CTRL_COMPLETE_IRQ_EN(v)        BM_ECC8_CTRL_COMPLETE_IRQ_EN
+#define BF_ECC8_CTRL_COMPLETE_IRQ_EN_V(e)       BF_ECC8_CTRL_COMPLETE_IRQ_EN(BV_ECC8_CTRL_COMPLETE_IRQ_EN__##e)
+#define BFM_ECC8_CTRL_COMPLETE_IRQ_EN_V(v)      BM_ECC8_CTRL_COMPLETE_IRQ_EN
+#define BP_ECC8_CTRL_BM_ERROR_IRQ               3
+#define BM_ECC8_CTRL_BM_ERROR_IRQ               0x8
+#define BF_ECC8_CTRL_BM_ERROR_IRQ(v)            (((v) & 0x1) << 3)
+#define BFM_ECC8_CTRL_BM_ERROR_IRQ(v)           BM_ECC8_CTRL_BM_ERROR_IRQ
+#define BF_ECC8_CTRL_BM_ERROR_IRQ_V(e)          BF_ECC8_CTRL_BM_ERROR_IRQ(BV_ECC8_CTRL_BM_ERROR_IRQ__##e)
+#define BFM_ECC8_CTRL_BM_ERROR_IRQ_V(v)         BM_ECC8_CTRL_BM_ERROR_IRQ
+#define BP_ECC8_CTRL_DEBUG_STALL_IRQ            2
+#define BM_ECC8_CTRL_DEBUG_STALL_IRQ            0x4
+#define BF_ECC8_CTRL_DEBUG_STALL_IRQ(v)         (((v) & 0x1) << 2)
+#define BFM_ECC8_CTRL_DEBUG_STALL_IRQ(v)        BM_ECC8_CTRL_DEBUG_STALL_IRQ
+#define BF_ECC8_CTRL_DEBUG_STALL_IRQ_V(e)       BF_ECC8_CTRL_DEBUG_STALL_IRQ(BV_ECC8_CTRL_DEBUG_STALL_IRQ__##e)
+#define BFM_ECC8_CTRL_DEBUG_STALL_IRQ_V(v)      BM_ECC8_CTRL_DEBUG_STALL_IRQ
+#define BP_ECC8_CTRL_DEBUG_WRITE_IRQ            1
+#define BM_ECC8_CTRL_DEBUG_WRITE_IRQ            0x2
+#define BF_ECC8_CTRL_DEBUG_WRITE_IRQ(v)         (((v) & 0x1) << 1)
+#define BFM_ECC8_CTRL_DEBUG_WRITE_IRQ(v)        BM_ECC8_CTRL_DEBUG_WRITE_IRQ
+#define BF_ECC8_CTRL_DEBUG_WRITE_IRQ_V(e)       BF_ECC8_CTRL_DEBUG_WRITE_IRQ(BV_ECC8_CTRL_DEBUG_WRITE_IRQ__##e)
+#define BFM_ECC8_CTRL_DEBUG_WRITE_IRQ_V(v)      BM_ECC8_CTRL_DEBUG_WRITE_IRQ
+#define BP_ECC8_CTRL_COMPLETE_IRQ               0
+#define BM_ECC8_CTRL_COMPLETE_IRQ               0x1
+#define BF_ECC8_CTRL_COMPLETE_IRQ(v)            (((v) & 0x1) << 0)
+#define BFM_ECC8_CTRL_COMPLETE_IRQ(v)           BM_ECC8_CTRL_COMPLETE_IRQ
+#define BF_ECC8_CTRL_COMPLETE_IRQ_V(e)          BF_ECC8_CTRL_COMPLETE_IRQ(BV_ECC8_CTRL_COMPLETE_IRQ__##e)
+#define BFM_ECC8_CTRL_COMPLETE_IRQ_V(v)         BM_ECC8_CTRL_COMPLETE_IRQ
+
+#define HW_ECC8_STATUS0                                 HW(ECC8_STATUS0)
+#define HWA_ECC8_STATUS0                                (0x80008000 + 0x10)
+#define HWT_ECC8_STATUS0                                HWIO_32_RW
+#define HWN_ECC8_STATUS0                                ECC8_STATUS0
+#define HWI_ECC8_STATUS0                                
+#define BP_ECC8_STATUS0_HANDLE                          16
+#define BM_ECC8_STATUS0_HANDLE                          0xffff0000
+#define BF_ECC8_STATUS0_HANDLE(v)                       (((v) & 0xffff) << 16)
+#define BFM_ECC8_STATUS0_HANDLE(v)                      BM_ECC8_STATUS0_HANDLE
+#define BF_ECC8_STATUS0_HANDLE_V(e)                     BF_ECC8_STATUS0_HANDLE(BV_ECC8_STATUS0_HANDLE__##e)
+#define BFM_ECC8_STATUS0_HANDLE_V(v)                    BM_ECC8_STATUS0_HANDLE
+#define BP_ECC8_STATUS0_RS8ECC_ENC_PRESENT              15
+#define BM_ECC8_STATUS0_RS8ECC_ENC_PRESENT              0x8000
+#define BF_ECC8_STATUS0_RS8ECC_ENC_PRESENT(v)           (((v) & 0x1) << 15)
+#define BFM_ECC8_STATUS0_RS8ECC_ENC_PRESENT(v)          BM_ECC8_STATUS0_RS8ECC_ENC_PRESENT
+#define BF_ECC8_STATUS0_RS8ECC_ENC_PRESENT_V(e)         BF_ECC8_STATUS0_RS8ECC_ENC_PRESENT(BV_ECC8_STATUS0_RS8ECC_ENC_PRESENT__##e)
+#define BFM_ECC8_STATUS0_RS8ECC_ENC_PRESENT_V(v)        BM_ECC8_STATUS0_RS8ECC_ENC_PRESENT
+#define BP_ECC8_STATUS0_RS8ECC_DEC_PRESENT              14
+#define BM_ECC8_STATUS0_RS8ECC_DEC_PRESENT              0x4000
+#define BF_ECC8_STATUS0_RS8ECC_DEC_PRESENT(v)           (((v) & 0x1) << 14)
+#define BFM_ECC8_STATUS0_RS8ECC_DEC_PRESENT(v)          BM_ECC8_STATUS0_RS8ECC_DEC_PRESENT
+#define BF_ECC8_STATUS0_RS8ECC_DEC_PRESENT_V(e)         BF_ECC8_STATUS0_RS8ECC_DEC_PRESENT(BV_ECC8_STATUS0_RS8ECC_DEC_PRESENT__##e)
+#define BFM_ECC8_STATUS0_RS8ECC_DEC_PRESENT_V(v)        BM_ECC8_STATUS0_RS8ECC_DEC_PRESENT
+#define BP_ECC8_STATUS0_RS4ECC_ENC_PRESENT              13
+#define BM_ECC8_STATUS0_RS4ECC_ENC_PRESENT              0x2000
+#define BF_ECC8_STATUS0_RS4ECC_ENC_PRESENT(v)           (((v) & 0x1) << 13)
+#define BFM_ECC8_STATUS0_RS4ECC_ENC_PRESENT(v)          BM_ECC8_STATUS0_RS4ECC_ENC_PRESENT
+#define BF_ECC8_STATUS0_RS4ECC_ENC_PRESENT_V(e)         BF_ECC8_STATUS0_RS4ECC_ENC_PRESENT(BV_ECC8_STATUS0_RS4ECC_ENC_PRESENT__##e)
+#define BFM_ECC8_STATUS0_RS4ECC_ENC_PRESENT_V(v)        BM_ECC8_STATUS0_RS4ECC_ENC_PRESENT
+#define BP_ECC8_STATUS0_RS4ECC_DEC_PRESENT              12
+#define BM_ECC8_STATUS0_RS4ECC_DEC_PRESENT              0x1000
+#define BF_ECC8_STATUS0_RS4ECC_DEC_PRESENT(v)           (((v) & 0x1) << 12)
+#define BFM_ECC8_STATUS0_RS4ECC_DEC_PRESENT(v)          BM_ECC8_STATUS0_RS4ECC_DEC_PRESENT
+#define BF_ECC8_STATUS0_RS4ECC_DEC_PRESENT_V(e)         BF_ECC8_STATUS0_RS4ECC_DEC_PRESENT(BV_ECC8_STATUS0_RS4ECC_DEC_PRESENT__##e)
+#define BFM_ECC8_STATUS0_RS4ECC_DEC_PRESENT_V(v)        BM_ECC8_STATUS0_RS4ECC_DEC_PRESENT
+#define BP_ECC8_STATUS0_STATUS_AUX                      8
+#define BM_ECC8_STATUS0_STATUS_AUX                      0xf00
+#define BV_ECC8_STATUS0_STATUS_AUX__NO_ERRORS           0x0
+#define BV_ECC8_STATUS0_STATUS_AUX__ONE_CORRECTABLE     0x1
+#define BV_ECC8_STATUS0_STATUS_AUX__TWO_CORRECTABLE     0x2
+#define BV_ECC8_STATUS0_STATUS_AUX__THREE_CORRECTABLE   0x3
+#define BV_ECC8_STATUS0_STATUS_AUX__FOUR_CORRECTABLE    0x4
+#define BV_ECC8_STATUS0_STATUS_AUX__NOT_CHECKED         0xc
+#define BV_ECC8_STATUS0_STATUS_AUX__UNCORRECTABLE       0xe
+#define BV_ECC8_STATUS0_STATUS_AUX__ALL_ONES            0xf
+#define BF_ECC8_STATUS0_STATUS_AUX(v)                   (((v) & 0xf) << 8)
+#define BFM_ECC8_STATUS0_STATUS_AUX(v)                  BM_ECC8_STATUS0_STATUS_AUX
+#define BF_ECC8_STATUS0_STATUS_AUX_V(e)                 BF_ECC8_STATUS0_STATUS_AUX(BV_ECC8_STATUS0_STATUS_AUX__##e)
+#define BFM_ECC8_STATUS0_STATUS_AUX_V(v)                BM_ECC8_STATUS0_STATUS_AUX
+#define BP_ECC8_STATUS0_ALLONES                         4
+#define BM_ECC8_STATUS0_ALLONES                         0x10
+#define BF_ECC8_STATUS0_ALLONES(v)                      (((v) & 0x1) << 4)
+#define BFM_ECC8_STATUS0_ALLONES(v)                     BM_ECC8_STATUS0_ALLONES
+#define BF_ECC8_STATUS0_ALLONES_V(e)                    BF_ECC8_STATUS0_ALLONES(BV_ECC8_STATUS0_ALLONES__##e)
+#define BFM_ECC8_STATUS0_ALLONES_V(v)                   BM_ECC8_STATUS0_ALLONES
+#define BP_ECC8_STATUS0_CORRECTED                       3
+#define BM_ECC8_STATUS0_CORRECTED                       0x8
+#define BF_ECC8_STATUS0_CORRECTED(v)                    (((v) & 0x1) << 3)
+#define BFM_ECC8_STATUS0_CORRECTED(v)                   BM_ECC8_STATUS0_CORRECTED
+#define BF_ECC8_STATUS0_CORRECTED_V(e)                  BF_ECC8_STATUS0_CORRECTED(BV_ECC8_STATUS0_CORRECTED__##e)
+#define BFM_ECC8_STATUS0_CORRECTED_V(v)                 BM_ECC8_STATUS0_CORRECTED
+#define BP_ECC8_STATUS0_UNCORRECTABLE                   2
+#define BM_ECC8_STATUS0_UNCORRECTABLE                   0x4
+#define BF_ECC8_STATUS0_UNCORRECTABLE(v)                (((v) & 0x1) << 2)
+#define BFM_ECC8_STATUS0_UNCORRECTABLE(v)               BM_ECC8_STATUS0_UNCORRECTABLE
+#define BF_ECC8_STATUS0_UNCORRECTABLE_V(e)              BF_ECC8_STATUS0_UNCORRECTABLE(BV_ECC8_STATUS0_UNCORRECTABLE__##e)
+#define BFM_ECC8_STATUS0_UNCORRECTABLE_V(v)             BM_ECC8_STATUS0_UNCORRECTABLE
+#define BP_ECC8_STATUS0_COMPLETED_CE                    0
+#define BM_ECC8_STATUS0_COMPLETED_CE                    0x3
+#define BF_ECC8_STATUS0_COMPLETED_CE(v)                 (((v) & 0x3) << 0)
+#define BFM_ECC8_STATUS0_COMPLETED_CE(v)                BM_ECC8_STATUS0_COMPLETED_CE
+#define BF_ECC8_STATUS0_COMPLETED_CE_V(e)               BF_ECC8_STATUS0_COMPLETED_CE(BV_ECC8_STATUS0_COMPLETED_CE__##e)
+#define BFM_ECC8_STATUS0_COMPLETED_CE_V(v)              BM_ECC8_STATUS0_COMPLETED_CE
+
+#define HW_ECC8_STATUS1                                     HW(ECC8_STATUS1)
+#define HWA_ECC8_STATUS1                                    (0x80008000 + 0x20)
+#define HWT_ECC8_STATUS1                                    HWIO_32_RW
+#define HWN_ECC8_STATUS1                                    ECC8_STATUS1
+#define HWI_ECC8_STATUS1                                    
+#define BP_ECC8_STATUS1_STATUS_PAYLOAD7                     28
+#define BM_ECC8_STATUS1_STATUS_PAYLOAD7                     0xf0000000
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__NO_ERRORS          0x0
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__ONE_CORRECTABLE    0x1
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__TWO_CORRECTABLE    0x2
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__THREE_CORRECTABLE  0x3
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__FOUR_CORRECTABLE   0x4
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__FIVE_CORRECTABLE   0x5
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__SIX_CORRECTABLE    0x6
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__SEVEN_CORRECTABLE  0x7
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__EIGHT_CORRECTABLE  0x8
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__NOT_CHECKED        0xc
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__UNCORRECTABLE      0xe
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__ALL_ONES           0xf
+#define BF_ECC8_STATUS1_STATUS_PAYLOAD7(v)                  (((v) & 0xf) << 28)
+#define BFM_ECC8_STATUS1_STATUS_PAYLOAD7(v)                 BM_ECC8_STATUS1_STATUS_PAYLOAD7
+#define BF_ECC8_STATUS1_STATUS_PAYLOAD7_V(e)                BF_ECC8_STATUS1_STATUS_PAYLOAD7(BV_ECC8_STATUS1_STATUS_PAYLOAD7__##e)
+#define BFM_ECC8_STATUS1_STATUS_PAYLOAD7_V(v)               BM_ECC8_STATUS1_STATUS_PAYLOAD7
+#define BP_ECC8_STATUS1_STATUS_PAYLOAD6                     24
+#define BM_ECC8_STATUS1_STATUS_PAYLOAD6                     0xf000000
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__NO_ERRORS          0x0
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__ONE_CORRECTABLE    0x1
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__TWO_CORRECTABLE    0x2
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__THREE_CORRECTABLE  0x3
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__FOUR_CORRECTABLE   0x4
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__FIVE_CORRECTABLE   0x5
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__SIX_CORRECTABLE    0x6
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__SEVEN_CORRECTABLE  0x7
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__EIGHT_CORRECTABLE  0x8
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__NOT_CHECKED        0xc
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__UNCORRECTABLE      0xe
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__ALL_ONES           0xf
+#define BF_ECC8_STATUS1_STATUS_PAYLOAD6(v)                  (((v) & 0xf) << 24)
+#define BFM_ECC8_STATUS1_STATUS_PAYLOAD6(v)                 BM_ECC8_STATUS1_STATUS_PAYLOAD6
+#define BF_ECC8_STATUS1_STATUS_PAYLOAD6_V(e)                BF_ECC8_STATUS1_STATUS_PAYLOAD6(BV_ECC8_STATUS1_STATUS_PAYLOAD6__##e)
+#define BFM_ECC8_STATUS1_STATUS_PAYLOAD6_V(v)               BM_ECC8_STATUS1_STATUS_PAYLOAD6
+#define BP_ECC8_STATUS1_STATUS_PAYLOAD5                     20
+#define BM_ECC8_STATUS1_STATUS_PAYLOAD5                     0xf00000
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__NO_ERRORS          0x0
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__ONE_CORRECTABLE    0x1
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__TWO_CORRECTABLE    0x2
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__THREE_CORRECTABLE  0x3
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__FOUR_CORRECTABLE   0x4
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__FIVE_CORRECTABLE   0x5
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__SIX_CORRECTABLE    0x6
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__SEVEN_CORRECTABLE  0x7
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__EIGHT_CORRECTABLE  0x8
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__NOT_CHECKED        0xc
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__UNCORRECTABLE      0xe
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__ALL_ONES           0xf
+#define BF_ECC8_STATUS1_STATUS_PAYLOAD5(v)                  (((v) & 0xf) << 20)
+#define BFM_ECC8_STATUS1_STATUS_PAYLOAD5(v)                 BM_ECC8_STATUS1_STATUS_PAYLOAD5
+#define BF_ECC8_STATUS1_STATUS_PAYLOAD5_V(e)                BF_ECC8_STATUS1_STATUS_PAYLOAD5(BV_ECC8_STATUS1_STATUS_PAYLOAD5__##e)
+#define BFM_ECC8_STATUS1_STATUS_PAYLOAD5_V(v)               BM_ECC8_STATUS1_STATUS_PAYLOAD5
+#define BP_ECC8_STATUS1_STATUS_PAYLOAD4                     16
+#define BM_ECC8_STATUS1_STATUS_PAYLOAD4                     0xf0000
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__NO_ERRORS          0x0
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__ONE_CORRECTABLE    0x1
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__TWO_CORRECTABLE    0x2
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__THREE_CORRECTABLE  0x3
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__FOUR_CORRECTABLE   0x4
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__FIVE_CORRECTABLE   0x5
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__SIX_CORRECTABLE    0x6
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__SEVEN_CORRECTABLE  0x7
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__EIGHT_CORRECTABLE  0x8
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__NOT_CHECKED        0xc
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__UNCORRECTABLE      0xe
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__ALL_ONES           0xf
+#define BF_ECC8_STATUS1_STATUS_PAYLOAD4(v)                  (((v) & 0xf) << 16)
+#define BFM_ECC8_STATUS1_STATUS_PAYLOAD4(v)                 BM_ECC8_STATUS1_STATUS_PAYLOAD4
+#define BF_ECC8_STATUS1_STATUS_PAYLOAD4_V(e)                BF_ECC8_STATUS1_STATUS_PAYLOAD4(BV_ECC8_STATUS1_STATUS_PAYLOAD4__##e)
+#define BFM_ECC8_STATUS1_STATUS_PAYLOAD4_V(v)               BM_ECC8_STATUS1_STATUS_PAYLOAD4
+#define BP_ECC8_STATUS1_STATUS_PAYLOAD3                     12
+#define BM_ECC8_STATUS1_STATUS_PAYLOAD3                     0xf000
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__NO_ERRORS          0x0
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__ONE_CORRECTABLE    0x1
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__TWO_CORRECTABLE    0x2
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__THREE_CORRECTABLE  0x3
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__FOUR_CORRECTABLE   0x4
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__FIVE_CORRECTABLE   0x5
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__SIX_CORRECTABLE    0x6
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__SEVEN_CORRECTABLE  0x7
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__EIGHT_CORRECTABLE  0x8
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__NOT_CHECKED        0xc
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__UNCORRECTABLE      0xe
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__ALL_ONES           0xf
+#define BF_ECC8_STATUS1_STATUS_PAYLOAD3(v)                  (((v) & 0xf) << 12)
+#define BFM_ECC8_STATUS1_STATUS_PAYLOAD3(v)                 BM_ECC8_STATUS1_STATUS_PAYLOAD3
+#define BF_ECC8_STATUS1_STATUS_PAYLOAD3_V(e)                BF_ECC8_STATUS1_STATUS_PAYLOAD3(BV_ECC8_STATUS1_STATUS_PAYLOAD3__##e)
+#define BFM_ECC8_STATUS1_STATUS_PAYLOAD3_V(v)               BM_ECC8_STATUS1_STATUS_PAYLOAD3
+#define BP_ECC8_STATUS1_STATUS_PAYLOAD2                     8
+#define BM_ECC8_STATUS1_STATUS_PAYLOAD2                     0xf00
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__NO_ERRORS          0x0
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__ONE_CORRECTABLE    0x1
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__TWO_CORRECTABLE    0x2
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__THREE_CORRECTABLE  0x3
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__FOUR_CORRECTABLE   0x4
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__FIVE_CORRECTABLE   0x5
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__SIX_CORRECTABLE    0x6
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__SEVEN_CORRECTABLE  0x7
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__EIGHT_CORRECTABLE  0x8
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__NOT_CHECKED        0xc
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__UNCORRECTABLE      0xe
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__ALL_ONES           0xf
+#define BF_ECC8_STATUS1_STATUS_PAYLOAD2(v)                  (((v) & 0xf) << 8)
+#define BFM_ECC8_STATUS1_STATUS_PAYLOAD2(v)                 BM_ECC8_STATUS1_STATUS_PAYLOAD2
+#define BF_ECC8_STATUS1_STATUS_PAYLOAD2_V(e)                BF_ECC8_STATUS1_STATUS_PAYLOAD2(BV_ECC8_STATUS1_STATUS_PAYLOAD2__##e)
+#define BFM_ECC8_STATUS1_STATUS_PAYLOAD2_V(v)               BM_ECC8_STATUS1_STATUS_PAYLOAD2
+#define BP_ECC8_STATUS1_STATUS_PAYLOAD1                     4
+#define BM_ECC8_STATUS1_STATUS_PAYLOAD1                     0xf0
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__NO_ERRORS          0x0
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__ONE_CORRECTABLE    0x1
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__TWO_CORRECTABLE    0x2
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__THREE_CORRECTABLE  0x3
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__FOUR_CORRECTABLE   0x4
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__FIVE_CORRECTABLE   0x5
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__SIX_CORRECTABLE    0x6
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__SEVEN_CORRECTABLE  0x7
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__EIGHT_CORRECTABLE  0x8
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__NOT_CHECKED        0xc
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__UNCORRECTABLE      0xe
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__ALL_ONES           0xf
+#define BF_ECC8_STATUS1_STATUS_PAYLOAD1(v)                  (((v) & 0xf) << 4)
+#define BFM_ECC8_STATUS1_STATUS_PAYLOAD1(v)                 BM_ECC8_STATUS1_STATUS_PAYLOAD1
+#define BF_ECC8_STATUS1_STATUS_PAYLOAD1_V(e)                BF_ECC8_STATUS1_STATUS_PAYLOAD1(BV_ECC8_STATUS1_STATUS_PAYLOAD1__##e)
+#define BFM_ECC8_STATUS1_STATUS_PAYLOAD1_V(v)               BM_ECC8_STATUS1_STATUS_PAYLOAD1
+#define BP_ECC8_STATUS1_STATUS_PAYLOAD0                     0
+#define BM_ECC8_STATUS1_STATUS_PAYLOAD0                     0xf
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__NO_ERRORS          0x0
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__ONE_CORRECTABLE    0x1
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__TWO_CORRECTABLE    0x2
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__THREE_CORRECTABLE  0x3
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__FOUR_CORRECTABLE   0x4
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__FIVE_CORRECTABLE   0x5
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__SIX_CORRECTABLE    0x6
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__SEVEN_CORRECTABLE  0x7
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__EIGHT_CORRECTABLE  0x8
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__NOT_CHECKED        0xc
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__UNCORRECTABLE      0xe
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__ALL_ONES           0xf
+#define BF_ECC8_STATUS1_STATUS_PAYLOAD0(v)                  (((v) & 0xf) << 0)
+#define BFM_ECC8_STATUS1_STATUS_PAYLOAD0(v)                 BM_ECC8_STATUS1_STATUS_PAYLOAD0
+#define BF_ECC8_STATUS1_STATUS_PAYLOAD0_V(e)                BF_ECC8_STATUS1_STATUS_PAYLOAD0(BV_ECC8_STATUS1_STATUS_PAYLOAD0__##e)
+#define BFM_ECC8_STATUS1_STATUS_PAYLOAD0_V(v)               BM_ECC8_STATUS1_STATUS_PAYLOAD0
+
+#define HW_ECC8_DEBUG0                                      HW(ECC8_DEBUG0)
+#define HWA_ECC8_DEBUG0                                     (0x80008000 + 0x30)
+#define HWT_ECC8_DEBUG0                                     HWIO_32_RW
+#define HWN_ECC8_DEBUG0                                     ECC8_DEBUG0
+#define HWI_ECC8_DEBUG0                                     
+#define HW_ECC8_DEBUG0_SET                                  HW(ECC8_DEBUG0_SET)
+#define HWA_ECC8_DEBUG0_SET                                 (HWA_ECC8_DEBUG0 + 0x4)
+#define HWT_ECC8_DEBUG0_SET                                 HWIO_32_WO
+#define HWN_ECC8_DEBUG0_SET                                 ECC8_DEBUG0
+#define HWI_ECC8_DEBUG0_SET                                 
+#define HW_ECC8_DEBUG0_CLR                                  HW(ECC8_DEBUG0_CLR)
+#define HWA_ECC8_DEBUG0_CLR                                 (HWA_ECC8_DEBUG0 + 0x8)
+#define HWT_ECC8_DEBUG0_CLR                                 HWIO_32_WO
+#define HWN_ECC8_DEBUG0_CLR                                 ECC8_DEBUG0
+#define HWI_ECC8_DEBUG0_CLR                                 
+#define HW_ECC8_DEBUG0_TOG                                  HW(ECC8_DEBUG0_TOG)
+#define HWA_ECC8_DEBUG0_TOG                                 (HWA_ECC8_DEBUG0 + 0xc)
+#define HWT_ECC8_DEBUG0_TOG                                 HWIO_32_WO
+#define HWN_ECC8_DEBUG0_TOG                                 ECC8_DEBUG0
+#define HWI_ECC8_DEBUG0_TOG                                 
+#define BP_ECC8_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL            16
+#define BM_ECC8_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL            0x1ff0000
+#define BV_ECC8_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__NORMAL    0x0
+#define BV_ECC8_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__TEST_MODE 0x1
+#define BF_ECC8_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL(v)         (((v) & 0x1ff) << 16)
+#define BFM_ECC8_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL(v)        BM_ECC8_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL
+#define BF_ECC8_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_V(e)       BF_ECC8_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL(BV_ECC8_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__##e)
+#define BFM_ECC8_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_V(v)      BM_ECC8_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL
+#define BP_ECC8_DEBUG0_KES_DEBUG_SHIFT_SYND                 15
+#define BM_ECC8_DEBUG0_KES_DEBUG_SHIFT_SYND                 0x8000
+#define BF_ECC8_DEBUG0_KES_DEBUG_SHIFT_SYND(v)              (((v) & 0x1) << 15)
+#define BFM_ECC8_DEBUG0_KES_DEBUG_SHIFT_SYND(v)             BM_ECC8_DEBUG0_KES_DEBUG_SHIFT_SYND
+#define BF_ECC8_DEBUG0_KES_DEBUG_SHIFT_SYND_V(e)            BF_ECC8_DEBUG0_KES_DEBUG_SHIFT_SYND(BV_ECC8_DEBUG0_KES_DEBUG_SHIFT_SYND__##e)
+#define BFM_ECC8_DEBUG0_KES_DEBUG_SHIFT_SYND_V(v)           BM_ECC8_DEBUG0_KES_DEBUG_SHIFT_SYND
+#define BP_ECC8_DEBUG0_KES_DEBUG_PAYLOAD_FLAG               14
+#define BM_ECC8_DEBUG0_KES_DEBUG_PAYLOAD_FLAG               0x4000
+#define BV_ECC8_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__DATA         0x1
+#define BV_ECC8_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__AUX          0x1
+#define BF_ECC8_DEBUG0_KES_DEBUG_PAYLOAD_FLAG(v)            (((v) & 0x1) << 14)
+#define BFM_ECC8_DEBUG0_KES_DEBUG_PAYLOAD_FLAG(v)           BM_ECC8_DEBUG0_KES_DEBUG_PAYLOAD_FLAG
+#define BF_ECC8_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_V(e)          BF_ECC8_DEBUG0_KES_DEBUG_PAYLOAD_FLAG(BV_ECC8_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__##e)
+#define BFM_ECC8_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_V(v)         BM_ECC8_DEBUG0_KES_DEBUG_PAYLOAD_FLAG
+#define BP_ECC8_DEBUG0_KES_DEBUG_MODE4K                     13
+#define BM_ECC8_DEBUG0_KES_DEBUG_MODE4K                     0x2000
+#define BV_ECC8_DEBUG0_KES_DEBUG_MODE4K__4k                 0x1
+#define BV_ECC8_DEBUG0_KES_DEBUG_MODE4K__2k                 0x1
+#define BF_ECC8_DEBUG0_KES_DEBUG_MODE4K(v)                  (((v) & 0x1) << 13)
+#define BFM_ECC8_DEBUG0_KES_DEBUG_MODE4K(v)                 BM_ECC8_DEBUG0_KES_DEBUG_MODE4K
+#define BF_ECC8_DEBUG0_KES_DEBUG_MODE4K_V(e)                BF_ECC8_DEBUG0_KES_DEBUG_MODE4K(BV_ECC8_DEBUG0_KES_DEBUG_MODE4K__##e)
+#define BFM_ECC8_DEBUG0_KES_DEBUG_MODE4K_V(v)               BM_ECC8_DEBUG0_KES_DEBUG_MODE4K
+#define BP_ECC8_DEBUG0_KES_DEBUG_KICK                       12
+#define BM_ECC8_DEBUG0_KES_DEBUG_KICK                       0x1000
+#define BF_ECC8_DEBUG0_KES_DEBUG_KICK(v)                    (((v) & 0x1) << 12)
+#define BFM_ECC8_DEBUG0_KES_DEBUG_KICK(v)                   BM_ECC8_DEBUG0_KES_DEBUG_KICK
+#define BF_ECC8_DEBUG0_KES_DEBUG_KICK_V(e)                  BF_ECC8_DEBUG0_KES_DEBUG_KICK(BV_ECC8_DEBUG0_KES_DEBUG_KICK__##e)
+#define BFM_ECC8_DEBUG0_KES_DEBUG_KICK_V(v)                 BM_ECC8_DEBUG0_KES_DEBUG_KICK
+#define BP_ECC8_DEBUG0_KES_STANDALONE                       11
+#define BM_ECC8_DEBUG0_KES_STANDALONE                       0x800
+#define BV_ECC8_DEBUG0_KES_STANDALONE__NORMAL               0x0
+#define BV_ECC8_DEBUG0_KES_STANDALONE__TEST_MODE            0x1
+#define BF_ECC8_DEBUG0_KES_STANDALONE(v)                    (((v) & 0x1) << 11)
+#define BFM_ECC8_DEBUG0_KES_STANDALONE(v)                   BM_ECC8_DEBUG0_KES_STANDALONE
+#define BF_ECC8_DEBUG0_KES_STANDALONE_V(e)                  BF_ECC8_DEBUG0_KES_STANDALONE(BV_ECC8_DEBUG0_KES_STANDALONE__##e)
+#define BFM_ECC8_DEBUG0_KES_STANDALONE_V(v)                 BM_ECC8_DEBUG0_KES_STANDALONE
+#define BP_ECC8_DEBUG0_KES_DEBUG_STEP                       10
+#define BM_ECC8_DEBUG0_KES_DEBUG_STEP                       0x400
+#define BF_ECC8_DEBUG0_KES_DEBUG_STEP(v)                    (((v) & 0x1) << 10)
+#define BFM_ECC8_DEBUG0_KES_DEBUG_STEP(v)                   BM_ECC8_DEBUG0_KES_DEBUG_STEP
+#define BF_ECC8_DEBUG0_KES_DEBUG_STEP_V(e)                  BF_ECC8_DEBUG0_KES_DEBUG_STEP(BV_ECC8_DEBUG0_KES_DEBUG_STEP__##e)
+#define BFM_ECC8_DEBUG0_KES_DEBUG_STEP_V(v)                 BM_ECC8_DEBUG0_KES_DEBUG_STEP
+#define BP_ECC8_DEBUG0_KES_DEBUG_STALL                      9
+#define BM_ECC8_DEBUG0_KES_DEBUG_STALL                      0x200
+#define BV_ECC8_DEBUG0_KES_DEBUG_STALL__NORMAL              0x0
+#define BV_ECC8_DEBUG0_KES_DEBUG_STALL__WAIT                0x1
+#define BF_ECC8_DEBUG0_KES_DEBUG_STALL(v)                   (((v) & 0x1) << 9)
+#define BFM_ECC8_DEBUG0_KES_DEBUG_STALL(v)                  BM_ECC8_DEBUG0_KES_DEBUG_STALL
+#define BF_ECC8_DEBUG0_KES_DEBUG_STALL_V(e)                 BF_ECC8_DEBUG0_KES_DEBUG_STALL(BV_ECC8_DEBUG0_KES_DEBUG_STALL__##e)
+#define BFM_ECC8_DEBUG0_KES_DEBUG_STALL_V(v)                BM_ECC8_DEBUG0_KES_DEBUG_STALL
+#define BP_ECC8_DEBUG0_BM_KES_TEST_BYPASS                   8
+#define BM_ECC8_DEBUG0_BM_KES_TEST_BYPASS                   0x100
+#define BV_ECC8_DEBUG0_BM_KES_TEST_BYPASS__NORMAL           0x0
+#define BV_ECC8_DEBUG0_BM_KES_TEST_BYPASS__TEST_MODE        0x1
+#define BF_ECC8_DEBUG0_BM_KES_TEST_BYPASS(v)                (((v) & 0x1) << 8)
+#define BFM_ECC8_DEBUG0_BM_KES_TEST_BYPASS(v)               BM_ECC8_DEBUG0_BM_KES_TEST_BYPASS
+#define BF_ECC8_DEBUG0_BM_KES_TEST_BYPASS_V(e)              BF_ECC8_DEBUG0_BM_KES_TEST_BYPASS(BV_ECC8_DEBUG0_BM_KES_TEST_BYPASS__##e)
+#define BFM_ECC8_DEBUG0_BM_KES_TEST_BYPASS_V(v)             BM_ECC8_DEBUG0_BM_KES_TEST_BYPASS
+#define BP_ECC8_DEBUG0_DEBUG_REG_SELECT                     0
+#define BM_ECC8_DEBUG0_DEBUG_REG_SELECT                     0x3f
+#define BF_ECC8_DEBUG0_DEBUG_REG_SELECT(v)                  (((v) & 0x3f) << 0)
+#define BFM_ECC8_DEBUG0_DEBUG_REG_SELECT(v)                 BM_ECC8_DEBUG0_DEBUG_REG_SELECT
+#define BF_ECC8_DEBUG0_DEBUG_REG_SELECT_V(e)                BF_ECC8_DEBUG0_DEBUG_REG_SELECT(BV_ECC8_DEBUG0_DEBUG_REG_SELECT__##e)
+#define BFM_ECC8_DEBUG0_DEBUG_REG_SELECT_V(v)               BM_ECC8_DEBUG0_DEBUG_REG_SELECT
+
+#define HW_ECC8_DBGKESREAD              HW(ECC8_DBGKESREAD)
+#define HWA_ECC8_DBGKESREAD             (0x80008000 + 0x40)
+#define HWT_ECC8_DBGKESREAD             HWIO_32_RW
+#define HWN_ECC8_DBGKESREAD             ECC8_DBGKESREAD
+#define HWI_ECC8_DBGKESREAD             
+#define BP_ECC8_DBGKESREAD_VALUES       0
+#define BM_ECC8_DBGKESREAD_VALUES       0xffffffff
+#define BF_ECC8_DBGKESREAD_VALUES(v)    (((v) & 0xffffffff) << 0)
+#define BFM_ECC8_DBGKESREAD_VALUES(v)   BM_ECC8_DBGKESREAD_VALUES
+#define BF_ECC8_DBGKESREAD_VALUES_V(e)  BF_ECC8_DBGKESREAD_VALUES(BV_ECC8_DBGKESREAD_VALUES__##e)
+#define BFM_ECC8_DBGKESREAD_VALUES_V(v) BM_ECC8_DBGKESREAD_VALUES
+
+#define HW_ECC8_DBGCSFEREAD                 HW(ECC8_DBGCSFEREAD)
+#define HWA_ECC8_DBGCSFEREAD                (0x80008000 + 0x50)
+#define HWT_ECC8_DBGCSFEREAD                HWIO_32_RW
+#define HWN_ECC8_DBGCSFEREAD                ECC8_DBGCSFEREAD
+#define HWI_ECC8_DBGCSFEREAD                
+#define BP_ECC8_DBGCSFEREAD_VALUES          0
+#define BM_ECC8_DBGCSFEREAD_VALUES          0xffffffff
+#define BF_ECC8_DBGCSFEREAD_VALUES(v)       (((v) & 0xffffffff) << 0)
+#define BFM_ECC8_DBGCSFEREAD_VALUES(v)      BM_ECC8_DBGCSFEREAD_VALUES
+#define BF_ECC8_DBGCSFEREAD_VALUES_V(e)     BF_ECC8_DBGCSFEREAD_VALUES(BV_ECC8_DBGCSFEREAD_VALUES__##e)
+#define BFM_ECC8_DBGCSFEREAD_VALUES_V(v)    BM_ECC8_DBGCSFEREAD_VALUES
+
+#define HW_ECC8_DBGSYNDGENREAD              HW(ECC8_DBGSYNDGENREAD)
+#define HWA_ECC8_DBGSYNDGENREAD             (0x80008000 + 0x60)
+#define HWT_ECC8_DBGSYNDGENREAD             HWIO_32_RW
+#define HWN_ECC8_DBGSYNDGENREAD             ECC8_DBGSYNDGENREAD
+#define HWI_ECC8_DBGSYNDGENREAD             
+#define BP_ECC8_DBGSYNDGENREAD_VALUES       0
+#define BM_ECC8_DBGSYNDGENREAD_VALUES       0xffffffff
+#define BF_ECC8_DBGSYNDGENREAD_VALUES(v)    (((v) & 0xffffffff) << 0)
+#define BFM_ECC8_DBGSYNDGENREAD_VALUES(v)   BM_ECC8_DBGSYNDGENREAD_VALUES
+#define BF_ECC8_DBGSYNDGENREAD_VALUES_V(e)  BF_ECC8_DBGSYNDGENREAD_VALUES(BV_ECC8_DBGSYNDGENREAD_VALUES__##e)
+#define BFM_ECC8_DBGSYNDGENREAD_VALUES_V(v) BM_ECC8_DBGSYNDGENREAD_VALUES
+
+#define HW_ECC8_DBGAHBMREAD                 HW(ECC8_DBGAHBMREAD)
+#define HWA_ECC8_DBGAHBMREAD                (0x80008000 + 0x70)
+#define HWT_ECC8_DBGAHBMREAD                HWIO_32_RW
+#define HWN_ECC8_DBGAHBMREAD                ECC8_DBGAHBMREAD
+#define HWI_ECC8_DBGAHBMREAD                
+#define BP_ECC8_DBGAHBMREAD_VALUES          0
+#define BM_ECC8_DBGAHBMREAD_VALUES          0xffffffff
+#define BF_ECC8_DBGAHBMREAD_VALUES(v)       (((v) & 0xffffffff) << 0)
+#define BFM_ECC8_DBGAHBMREAD_VALUES(v)      BM_ECC8_DBGAHBMREAD_VALUES
+#define BF_ECC8_DBGAHBMREAD_VALUES_V(e)     BF_ECC8_DBGAHBMREAD_VALUES(BV_ECC8_DBGAHBMREAD_VALUES__##e)
+#define BFM_ECC8_DBGAHBMREAD_VALUES_V(v)    BM_ECC8_DBGAHBMREAD_VALUES
+
+#define HW_ECC8_BLOCKNAME               HW(ECC8_BLOCKNAME)
+#define HWA_ECC8_BLOCKNAME              (0x80008000 + 0x80)
+#define HWT_ECC8_BLOCKNAME              HWIO_32_RW
+#define HWN_ECC8_BLOCKNAME              ECC8_BLOCKNAME
+#define HWI_ECC8_BLOCKNAME              
+#define BP_ECC8_BLOCKNAME_NAME          0
+#define BM_ECC8_BLOCKNAME_NAME          0xffffffff
+#define BF_ECC8_BLOCKNAME_NAME(v)       (((v) & 0xffffffff) << 0)
+#define BFM_ECC8_BLOCKNAME_NAME(v)      BM_ECC8_BLOCKNAME_NAME
+#define BF_ECC8_BLOCKNAME_NAME_V(e)     BF_ECC8_BLOCKNAME_NAME(BV_ECC8_BLOCKNAME_NAME__##e)
+#define BFM_ECC8_BLOCKNAME_NAME_V(v)    BM_ECC8_BLOCKNAME_NAME
+
+#define HW_ECC8_VERSION             HW(ECC8_VERSION)
+#define HWA_ECC8_VERSION            (0x80008000 + 0xa0)
+#define HWT_ECC8_VERSION            HWIO_32_RW
+#define HWN_ECC8_VERSION            ECC8_VERSION
+#define HWI_ECC8_VERSION            
+#define BP_ECC8_VERSION_MAJOR       24
+#define BM_ECC8_VERSION_MAJOR       0xff000000
+#define BF_ECC8_VERSION_MAJOR(v)    (((v) & 0xff) << 24)
+#define BFM_ECC8_VERSION_MAJOR(v)   BM_ECC8_VERSION_MAJOR
+#define BF_ECC8_VERSION_MAJOR_V(e)  BF_ECC8_VERSION_MAJOR(BV_ECC8_VERSION_MAJOR__##e)
+#define BFM_ECC8_VERSION_MAJOR_V(v) BM_ECC8_VERSION_MAJOR
+#define BP_ECC8_VERSION_MINOR       16
+#define BM_ECC8_VERSION_MINOR       0xff0000
+#define BF_ECC8_VERSION_MINOR(v)    (((v) & 0xff) << 16)
+#define BFM_ECC8_VERSION_MINOR(v)   BM_ECC8_VERSION_MINOR
+#define BF_ECC8_VERSION_MINOR_V(e)  BF_ECC8_VERSION_MINOR(BV_ECC8_VERSION_MINOR__##e)
+#define BFM_ECC8_VERSION_MINOR_V(v) BM_ECC8_VERSION_MINOR
+#define BP_ECC8_VERSION_STEP        0
+#define BM_ECC8_VERSION_STEP        0xffff
+#define BF_ECC8_VERSION_STEP(v)     (((v) & 0xffff) << 0)
+#define BFM_ECC8_VERSION_STEP(v)    BM_ECC8_VERSION_STEP
+#define BF_ECC8_VERSION_STEP_V(e)   BF_ECC8_VERSION_STEP(BV_ECC8_VERSION_STEP__##e)
+#define BFM_ECC8_VERSION_STEP_V(v)  BM_ECC8_VERSION_STEP
+
+#endif /* __HEADERGEN_STMP3700_ECC8_H__*/
diff --git a/firmware/target/arm/imx233/regs/stmp3700/emi.h b/firmware/target/arm/imx233/regs/stmp3700/emi.h
new file mode 100644
index 0000000000..a72d815c55
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3700/emi.h
@@ -0,0 +1,291 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * stmp3700 version: 2.4.0
+ * stmp3700 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_STMP3700_EMI_H__
+#define __HEADERGEN_STMP3700_EMI_H__
+
+#define HW_EMI_CTRL                     HW(EMI_CTRL)
+#define HWA_EMI_CTRL                    (0x80020000 + 0x0)
+#define HWT_EMI_CTRL                    HWIO_32_RW
+#define HWN_EMI_CTRL                    EMI_CTRL
+#define HWI_EMI_CTRL                    
+#define HW_EMI_CTRL_SET                 HW(EMI_CTRL_SET)
+#define HWA_EMI_CTRL_SET                (HWA_EMI_CTRL + 0x4)
+#define HWT_EMI_CTRL_SET                HWIO_32_WO
+#define HWN_EMI_CTRL_SET                EMI_CTRL
+#define HWI_EMI_CTRL_SET                
+#define HW_EMI_CTRL_CLR                 HW(EMI_CTRL_CLR)
+#define HWA_EMI_CTRL_CLR                (HWA_EMI_CTRL + 0x8)
+#define HWT_EMI_CTRL_CLR                HWIO_32_WO
+#define HWN_EMI_CTRL_CLR                EMI_CTRL
+#define HWI_EMI_CTRL_CLR                
+#define HW_EMI_CTRL_TOG                 HW(EMI_CTRL_TOG)
+#define HWA_EMI_CTRL_TOG                (HWA_EMI_CTRL + 0xc)
+#define HWT_EMI_CTRL_TOG                HWIO_32_WO
+#define HWN_EMI_CTRL_TOG                EMI_CTRL
+#define HWI_EMI_CTRL_TOG                
+#define BP_EMI_CTRL_SFTRST              31
+#define BM_EMI_CTRL_SFTRST              0x80000000
+#define BF_EMI_CTRL_SFTRST(v)           (((v) & 0x1) << 31)
+#define BFM_EMI_CTRL_SFTRST(v)          BM_EMI_CTRL_SFTRST
+#define BF_EMI_CTRL_SFTRST_V(e)         BF_EMI_CTRL_SFTRST(BV_EMI_CTRL_SFTRST__##e)
+#define BFM_EMI_CTRL_SFTRST_V(v)        BM_EMI_CTRL_SFTRST
+#define BP_EMI_CTRL_CLKGATE             30
+#define BM_EMI_CTRL_CLKGATE             0x40000000
+#define BF_EMI_CTRL_CLKGATE(v)          (((v) & 0x1) << 30)
+#define BFM_EMI_CTRL_CLKGATE(v)         BM_EMI_CTRL_CLKGATE
+#define BF_EMI_CTRL_CLKGATE_V(e)        BF_EMI_CTRL_CLKGATE(BV_EMI_CTRL_CLKGATE__##e)
+#define BFM_EMI_CTRL_CLKGATE_V(v)       BM_EMI_CTRL_CLKGATE
+#define BP_EMI_CTRL_MEM_WIDTH           6
+#define BM_EMI_CTRL_MEM_WIDTH           0x40
+#define BF_EMI_CTRL_MEM_WIDTH(v)        (((v) & 0x1) << 6)
+#define BFM_EMI_CTRL_MEM_WIDTH(v)       BM_EMI_CTRL_MEM_WIDTH
+#define BF_EMI_CTRL_MEM_WIDTH_V(e)      BF_EMI_CTRL_MEM_WIDTH(BV_EMI_CTRL_MEM_WIDTH__##e)
+#define BFM_EMI_CTRL_MEM_WIDTH_V(v)     BM_EMI_CTRL_MEM_WIDTH
+#define BP_EMI_CTRL_WRITE_PROTECT       5
+#define BM_EMI_CTRL_WRITE_PROTECT       0x20
+#define BF_EMI_CTRL_WRITE_PROTECT(v)    (((v) & 0x1) << 5)
+#define BFM_EMI_CTRL_WRITE_PROTECT(v)   BM_EMI_CTRL_WRITE_PROTECT
+#define BF_EMI_CTRL_WRITE_PROTECT_V(e)  BF_EMI_CTRL_WRITE_PROTECT(BV_EMI_CTRL_WRITE_PROTECT__##e)
+#define BFM_EMI_CTRL_WRITE_PROTECT_V(v) BM_EMI_CTRL_WRITE_PROTECT
+#define BP_EMI_CTRL_RESET_OUT           4
+#define BM_EMI_CTRL_RESET_OUT           0x10
+#define BF_EMI_CTRL_RESET_OUT(v)        (((v) & 0x1) << 4)
+#define BFM_EMI_CTRL_RESET_OUT(v)       BM_EMI_CTRL_RESET_OUT
+#define BF_EMI_CTRL_RESET_OUT_V(e)      BF_EMI_CTRL_RESET_OUT(BV_EMI_CTRL_RESET_OUT__##e)
+#define BFM_EMI_CTRL_RESET_OUT_V(v)     BM_EMI_CTRL_RESET_OUT
+#define BP_EMI_CTRL_CE_SELECT           0
+#define BM_EMI_CTRL_CE_SELECT           0xf
+#define BV_EMI_CTRL_CE_SELECT__NONE     0x0
+#define BV_EMI_CTRL_CE_SELECT__CE0      0x1
+#define BV_EMI_CTRL_CE_SELECT__CE1      0x2
+#define BV_EMI_CTRL_CE_SELECT__CE2      0x4
+#define BV_EMI_CTRL_CE_SELECT__CE3      0x8
+#define BF_EMI_CTRL_CE_SELECT(v)        (((v) & 0xf) << 0)
+#define BFM_EMI_CTRL_CE_SELECT(v)       BM_EMI_CTRL_CE_SELECT
+#define BF_EMI_CTRL_CE_SELECT_V(e)      BF_EMI_CTRL_CE_SELECT(BV_EMI_CTRL_CE_SELECT__##e)
+#define BFM_EMI_CTRL_CE_SELECT_V(v)     BM_EMI_CTRL_CE_SELECT
+
+#define HW_EMI_STAT                             HW(EMI_STAT)
+#define HWA_EMI_STAT                            (0x80020000 + 0x10)
+#define HWT_EMI_STAT                            HWIO_32_RW
+#define HWN_EMI_STAT                            EMI_STAT
+#define HWI_EMI_STAT                            
+#define BP_EMI_STAT_DRAM_PRESENT                31
+#define BM_EMI_STAT_DRAM_PRESENT                0x80000000
+#define BF_EMI_STAT_DRAM_PRESENT(v)             (((v) & 0x1) << 31)
+#define BFM_EMI_STAT_DRAM_PRESENT(v)            BM_EMI_STAT_DRAM_PRESENT
+#define BF_EMI_STAT_DRAM_PRESENT_V(e)           BF_EMI_STAT_DRAM_PRESENT(BV_EMI_STAT_DRAM_PRESENT__##e)
+#define BFM_EMI_STAT_DRAM_PRESENT_V(v)          BM_EMI_STAT_DRAM_PRESENT
+#define BP_EMI_STAT_NOR_PRESENT                 30
+#define BM_EMI_STAT_NOR_PRESENT                 0x40000000
+#define BF_EMI_STAT_NOR_PRESENT(v)              (((v) & 0x1) << 30)
+#define BFM_EMI_STAT_NOR_PRESENT(v)             BM_EMI_STAT_NOR_PRESENT
+#define BF_EMI_STAT_NOR_PRESENT_V(e)            BF_EMI_STAT_NOR_PRESENT(BV_EMI_STAT_NOR_PRESENT__##e)
+#define BFM_EMI_STAT_NOR_PRESENT_V(v)           BM_EMI_STAT_NOR_PRESENT
+#define BP_EMI_STAT_LARGE_DRAM_ENABLED          29
+#define BM_EMI_STAT_LARGE_DRAM_ENABLED          0x20000000
+#define BF_EMI_STAT_LARGE_DRAM_ENABLED(v)       (((v) & 0x1) << 29)
+#define BFM_EMI_STAT_LARGE_DRAM_ENABLED(v)      BM_EMI_STAT_LARGE_DRAM_ENABLED
+#define BF_EMI_STAT_LARGE_DRAM_ENABLED_V(e)     BF_EMI_STAT_LARGE_DRAM_ENABLED(BV_EMI_STAT_LARGE_DRAM_ENABLED__##e)
+#define BFM_EMI_STAT_LARGE_DRAM_ENABLED_V(v)    BM_EMI_STAT_LARGE_DRAM_ENABLED
+#define BP_EMI_STAT_DRAM_HALTED                 1
+#define BM_EMI_STAT_DRAM_HALTED                 0x2
+#define BV_EMI_STAT_DRAM_HALTED__NOT_HALTED     0x0
+#define BV_EMI_STAT_DRAM_HALTED__HALTED         0x1
+#define BF_EMI_STAT_DRAM_HALTED(v)              (((v) & 0x1) << 1)
+#define BFM_EMI_STAT_DRAM_HALTED(v)             BM_EMI_STAT_DRAM_HALTED
+#define BF_EMI_STAT_DRAM_HALTED_V(e)            BF_EMI_STAT_DRAM_HALTED(BV_EMI_STAT_DRAM_HALTED__##e)
+#define BFM_EMI_STAT_DRAM_HALTED_V(v)           BM_EMI_STAT_DRAM_HALTED
+#define BP_EMI_STAT_NOR_BUSY                    0
+#define BM_EMI_STAT_NOR_BUSY                    0x1
+#define BV_EMI_STAT_NOR_BUSY__NOT_BUSY          0x0
+#define BV_EMI_STAT_NOR_BUSY__BUSY              0x1
+#define BF_EMI_STAT_NOR_BUSY(v)                 (((v) & 0x1) << 0)
+#define BFM_EMI_STAT_NOR_BUSY(v)                BM_EMI_STAT_NOR_BUSY
+#define BF_EMI_STAT_NOR_BUSY_V(e)               BF_EMI_STAT_NOR_BUSY(BV_EMI_STAT_NOR_BUSY__##e)
+#define BFM_EMI_STAT_NOR_BUSY_V(v)              BM_EMI_STAT_NOR_BUSY
+
+#define HW_EMI_TIME             HW(EMI_TIME)
+#define HWA_EMI_TIME            (0x80020000 + 0x20)
+#define HWT_EMI_TIME            HWIO_32_RW
+#define HWN_EMI_TIME            EMI_TIME
+#define HWI_EMI_TIME            
+#define HW_EMI_TIME_SET         HW(EMI_TIME_SET)
+#define HWA_EMI_TIME_SET        (HWA_EMI_TIME + 0x4)
+#define HWT_EMI_TIME_SET        HWIO_32_WO
+#define HWN_EMI_TIME_SET        EMI_TIME
+#define HWI_EMI_TIME_SET        
+#define HW_EMI_TIME_CLR         HW(EMI_TIME_CLR)
+#define HWA_EMI_TIME_CLR        (HWA_EMI_TIME + 0x8)
+#define HWT_EMI_TIME_CLR        HWIO_32_WO
+#define HWN_EMI_TIME_CLR        EMI_TIME
+#define HWI_EMI_TIME_CLR        
+#define HW_EMI_TIME_TOG         HW(EMI_TIME_TOG)
+#define HWA_EMI_TIME_TOG        (HWA_EMI_TIME + 0xc)
+#define HWT_EMI_TIME_TOG        HWIO_32_WO
+#define HWN_EMI_TIME_TOG        EMI_TIME
+#define HWI_EMI_TIME_TOG        
+#define BP_EMI_TIME_THZ         24
+#define BM_EMI_TIME_THZ         0xf000000
+#define BF_EMI_TIME_THZ(v)      (((v) & 0xf) << 24)
+#define BFM_EMI_TIME_THZ(v)     BM_EMI_TIME_THZ
+#define BF_EMI_TIME_THZ_V(e)    BF_EMI_TIME_THZ(BV_EMI_TIME_THZ__##e)
+#define BFM_EMI_TIME_THZ_V(v)   BM_EMI_TIME_THZ
+#define BP_EMI_TIME_TDH         16
+#define BM_EMI_TIME_TDH         0xf0000
+#define BF_EMI_TIME_TDH(v)      (((v) & 0xf) << 16)
+#define BFM_EMI_TIME_TDH(v)     BM_EMI_TIME_TDH
+#define BF_EMI_TIME_TDH_V(e)    BF_EMI_TIME_TDH(BV_EMI_TIME_TDH__##e)
+#define BFM_EMI_TIME_TDH_V(v)   BM_EMI_TIME_TDH
+#define BP_EMI_TIME_TDS         8
+#define BM_EMI_TIME_TDS         0x1f00
+#define BF_EMI_TIME_TDS(v)      (((v) & 0x1f) << 8)
+#define BFM_EMI_TIME_TDS(v)     BM_EMI_TIME_TDS
+#define BF_EMI_TIME_TDS_V(e)    BF_EMI_TIME_TDS(BV_EMI_TIME_TDS__##e)
+#define BFM_EMI_TIME_TDS_V(v)   BM_EMI_TIME_TDS
+#define BP_EMI_TIME_TAS         0
+#define BM_EMI_TIME_TAS         0xf
+#define BF_EMI_TIME_TAS(v)      (((v) & 0xf) << 0)
+#define BFM_EMI_TIME_TAS(v)     BM_EMI_TIME_TAS
+#define BF_EMI_TIME_TAS_V(e)    BF_EMI_TIME_TAS(BV_EMI_TIME_TAS__##e)
+#define BFM_EMI_TIME_TAS_V(v)   BM_EMI_TIME_TAS
+
+#define HW_EMI_DDR_TEST_MODE_CSR                HW(EMI_DDR_TEST_MODE_CSR)
+#define HWA_EMI_DDR_TEST_MODE_CSR               (0x80020000 + 0x30)
+#define HWT_EMI_DDR_TEST_MODE_CSR               HWIO_32_RW
+#define HWN_EMI_DDR_TEST_MODE_CSR               EMI_DDR_TEST_MODE_CSR
+#define HWI_EMI_DDR_TEST_MODE_CSR               
+#define HW_EMI_DDR_TEST_MODE_CSR_SET            HW(EMI_DDR_TEST_MODE_CSR_SET)
+#define HWA_EMI_DDR_TEST_MODE_CSR_SET           (HWA_EMI_DDR_TEST_MODE_CSR + 0x4)
+#define HWT_EMI_DDR_TEST_MODE_CSR_SET           HWIO_32_WO
+#define HWN_EMI_DDR_TEST_MODE_CSR_SET           EMI_DDR_TEST_MODE_CSR
+#define HWI_EMI_DDR_TEST_MODE_CSR_SET           
+#define HW_EMI_DDR_TEST_MODE_CSR_CLR            HW(EMI_DDR_TEST_MODE_CSR_CLR)
+#define HWA_EMI_DDR_TEST_MODE_CSR_CLR           (HWA_EMI_DDR_TEST_MODE_CSR + 0x8)
+#define HWT_EMI_DDR_TEST_MODE_CSR_CLR           HWIO_32_WO
+#define HWN_EMI_DDR_TEST_MODE_CSR_CLR           EMI_DDR_TEST_MODE_CSR
+#define HWI_EMI_DDR_TEST_MODE_CSR_CLR           
+#define HW_EMI_DDR_TEST_MODE_CSR_TOG            HW(EMI_DDR_TEST_MODE_CSR_TOG)
+#define HWA_EMI_DDR_TEST_MODE_CSR_TOG           (HWA_EMI_DDR_TEST_MODE_CSR + 0xc)
+#define HWT_EMI_DDR_TEST_MODE_CSR_TOG           HWIO_32_WO
+#define HWN_EMI_DDR_TEST_MODE_CSR_TOG           EMI_DDR_TEST_MODE_CSR
+#define HWI_EMI_DDR_TEST_MODE_CSR_TOG           
+#define BP_EMI_DDR_TEST_MODE_CSR_DONE           1
+#define BM_EMI_DDR_TEST_MODE_CSR_DONE           0x2
+#define BF_EMI_DDR_TEST_MODE_CSR_DONE(v)        (((v) & 0x1) << 1)
+#define BFM_EMI_DDR_TEST_MODE_CSR_DONE(v)       BM_EMI_DDR_TEST_MODE_CSR_DONE
+#define BF_EMI_DDR_TEST_MODE_CSR_DONE_V(e)      BF_EMI_DDR_TEST_MODE_CSR_DONE(BV_EMI_DDR_TEST_MODE_CSR_DONE__##e)
+#define BFM_EMI_DDR_TEST_MODE_CSR_DONE_V(v)     BM_EMI_DDR_TEST_MODE_CSR_DONE
+#define BP_EMI_DDR_TEST_MODE_CSR_START          0
+#define BM_EMI_DDR_TEST_MODE_CSR_START          0x1
+#define BF_EMI_DDR_TEST_MODE_CSR_START(v)       (((v) & 0x1) << 0)
+#define BFM_EMI_DDR_TEST_MODE_CSR_START(v)      BM_EMI_DDR_TEST_MODE_CSR_START
+#define BF_EMI_DDR_TEST_MODE_CSR_START_V(e)     BF_EMI_DDR_TEST_MODE_CSR_START(BV_EMI_DDR_TEST_MODE_CSR_START__##e)
+#define BFM_EMI_DDR_TEST_MODE_CSR_START_V(v)    BM_EMI_DDR_TEST_MODE_CSR_START
+
+#define HW_EMI_DEBUG                    HW(EMI_DEBUG)
+#define HWA_EMI_DEBUG                   (0x80020000 + 0x80)
+#define HWT_EMI_DEBUG                   HWIO_32_RW
+#define HWN_EMI_DEBUG                   EMI_DEBUG
+#define HWI_EMI_DEBUG                   
+#define BP_EMI_DEBUG_NOR_STATE          0
+#define BM_EMI_DEBUG_NOR_STATE          0xf
+#define BF_EMI_DEBUG_NOR_STATE(v)       (((v) & 0xf) << 0)
+#define BFM_EMI_DEBUG_NOR_STATE(v)      BM_EMI_DEBUG_NOR_STATE
+#define BF_EMI_DEBUG_NOR_STATE_V(e)     BF_EMI_DEBUG_NOR_STATE(BV_EMI_DEBUG_NOR_STATE__##e)
+#define BFM_EMI_DEBUG_NOR_STATE_V(v)    BM_EMI_DEBUG_NOR_STATE
+
+#define HW_EMI_DDR_TEST_MODE_STATUS0                HW(EMI_DDR_TEST_MODE_STATUS0)
+#define HWA_EMI_DDR_TEST_MODE_STATUS0               (0x80020000 + 0x90)
+#define HWT_EMI_DDR_TEST_MODE_STATUS0               HWIO_32_RW
+#define HWN_EMI_DDR_TEST_MODE_STATUS0               EMI_DDR_TEST_MODE_STATUS0
+#define HWI_EMI_DDR_TEST_MODE_STATUS0               
+#define BP_EMI_DDR_TEST_MODE_STATUS0_ADDR0          0
+#define BM_EMI_DDR_TEST_MODE_STATUS0_ADDR0          0x1fff
+#define BF_EMI_DDR_TEST_MODE_STATUS0_ADDR0(v)       (((v) & 0x1fff) << 0)
+#define BFM_EMI_DDR_TEST_MODE_STATUS0_ADDR0(v)      BM_EMI_DDR_TEST_MODE_STATUS0_ADDR0
+#define BF_EMI_DDR_TEST_MODE_STATUS0_ADDR0_V(e)     BF_EMI_DDR_TEST_MODE_STATUS0_ADDR0(BV_EMI_DDR_TEST_MODE_STATUS0_ADDR0__##e)
+#define BFM_EMI_DDR_TEST_MODE_STATUS0_ADDR0_V(v)    BM_EMI_DDR_TEST_MODE_STATUS0_ADDR0
+
+#define HW_EMI_DDR_TEST_MODE_STATUS1                HW(EMI_DDR_TEST_MODE_STATUS1)
+#define HWA_EMI_DDR_TEST_MODE_STATUS1               (0x80020000 + 0xa0)
+#define HWT_EMI_DDR_TEST_MODE_STATUS1               HWIO_32_RW
+#define HWN_EMI_DDR_TEST_MODE_STATUS1               EMI_DDR_TEST_MODE_STATUS1
+#define HWI_EMI_DDR_TEST_MODE_STATUS1               
+#define BP_EMI_DDR_TEST_MODE_STATUS1_ADDR1          0
+#define BM_EMI_DDR_TEST_MODE_STATUS1_ADDR1          0x1fff
+#define BF_EMI_DDR_TEST_MODE_STATUS1_ADDR1(v)       (((v) & 0x1fff) << 0)
+#define BFM_EMI_DDR_TEST_MODE_STATUS1_ADDR1(v)      BM_EMI_DDR_TEST_MODE_STATUS1_ADDR1
+#define BF_EMI_DDR_TEST_MODE_STATUS1_ADDR1_V(e)     BF_EMI_DDR_TEST_MODE_STATUS1_ADDR1(BV_EMI_DDR_TEST_MODE_STATUS1_ADDR1__##e)
+#define BFM_EMI_DDR_TEST_MODE_STATUS1_ADDR1_V(v)    BM_EMI_DDR_TEST_MODE_STATUS1_ADDR1
+
+#define HW_EMI_DDR_TEST_MODE_STATUS2                HW(EMI_DDR_TEST_MODE_STATUS2)
+#define HWA_EMI_DDR_TEST_MODE_STATUS2               (0x80020000 + 0xb0)
+#define HWT_EMI_DDR_TEST_MODE_STATUS2               HWIO_32_RW
+#define HWN_EMI_DDR_TEST_MODE_STATUS2               EMI_DDR_TEST_MODE_STATUS2
+#define HWI_EMI_DDR_TEST_MODE_STATUS2               
+#define BP_EMI_DDR_TEST_MODE_STATUS2_DATA0          0
+#define BM_EMI_DDR_TEST_MODE_STATUS2_DATA0          0xffffffff
+#define BF_EMI_DDR_TEST_MODE_STATUS2_DATA0(v)       (((v) & 0xffffffff) << 0)
+#define BFM_EMI_DDR_TEST_MODE_STATUS2_DATA0(v)      BM_EMI_DDR_TEST_MODE_STATUS2_DATA0
+#define BF_EMI_DDR_TEST_MODE_STATUS2_DATA0_V(e)     BF_EMI_DDR_TEST_MODE_STATUS2_DATA0(BV_EMI_DDR_TEST_MODE_STATUS2_DATA0__##e)
+#define BFM_EMI_DDR_TEST_MODE_STATUS2_DATA0_V(v)    BM_EMI_DDR_TEST_MODE_STATUS2_DATA0
+
+#define HW_EMI_DDR_TEST_MODE_STATUS3                HW(EMI_DDR_TEST_MODE_STATUS3)
+#define HWA_EMI_DDR_TEST_MODE_STATUS3               (0x80020000 + 0xc0)
+#define HWT_EMI_DDR_TEST_MODE_STATUS3               HWIO_32_RW
+#define HWN_EMI_DDR_TEST_MODE_STATUS3               EMI_DDR_TEST_MODE_STATUS3
+#define HWI_EMI_DDR_TEST_MODE_STATUS3               
+#define BP_EMI_DDR_TEST_MODE_STATUS3_DATA1          0
+#define BM_EMI_DDR_TEST_MODE_STATUS3_DATA1          0xffffffff
+#define BF_EMI_DDR_TEST_MODE_STATUS3_DATA1(v)       (((v) & 0xffffffff) << 0)
+#define BFM_EMI_DDR_TEST_MODE_STATUS3_DATA1(v)      BM_EMI_DDR_TEST_MODE_STATUS3_DATA1
+#define BF_EMI_DDR_TEST_MODE_STATUS3_DATA1_V(e)     BF_EMI_DDR_TEST_MODE_STATUS3_DATA1(BV_EMI_DDR_TEST_MODE_STATUS3_DATA1__##e)
+#define BFM_EMI_DDR_TEST_MODE_STATUS3_DATA1_V(v)    BM_EMI_DDR_TEST_MODE_STATUS3_DATA1
+
+#define HW_EMI_VERSION              HW(EMI_VERSION)
+#define HWA_EMI_VERSION             (0x80020000 + 0xf0)
+#define HWT_EMI_VERSION             HWIO_32_RW
+#define HWN_EMI_VERSION             EMI_VERSION
+#define HWI_EMI_VERSION             
+#define BP_EMI_VERSION_MAJOR        24
+#define BM_EMI_VERSION_MAJOR        0xff000000
+#define BF_EMI_VERSION_MAJOR(v)     (((v) & 0xff) << 24)
+#define BFM_EMI_VERSION_MAJOR(v)    BM_EMI_VERSION_MAJOR
+#define BF_EMI_VERSION_MAJOR_V(e)   BF_EMI_VERSION_MAJOR(BV_EMI_VERSION_MAJOR__##e)
+#define BFM_EMI_VERSION_MAJOR_V(v)  BM_EMI_VERSION_MAJOR
+#define BP_EMI_VERSION_MINOR        16
+#define BM_EMI_VERSION_MINOR        0xff0000
+#define BF_EMI_VERSION_MINOR(v)     (((v) & 0xff) << 16)
+#define BFM_EMI_VERSION_MINOR(v)    BM_EMI_VERSION_MINOR
+#define BF_EMI_VERSION_MINOR_V(e)   BF_EMI_VERSION_MINOR(BV_EMI_VERSION_MINOR__##e)
+#define BFM_EMI_VERSION_MINOR_V(v)  BM_EMI_VERSION_MINOR
+#define BP_EMI_VERSION_STEP         0
+#define BM_EMI_VERSION_STEP         0xffff
+#define BF_EMI_VERSION_STEP(v)      (((v) & 0xffff) << 0)
+#define BFM_EMI_VERSION_STEP(v)     BM_EMI_VERSION_STEP
+#define BF_EMI_VERSION_STEP_V(e)    BF_EMI_VERSION_STEP(BV_EMI_VERSION_STEP__##e)
+#define BFM_EMI_VERSION_STEP_V(v)   BM_EMI_VERSION_STEP
+
+#endif /* __HEADERGEN_STMP3700_EMI_H__*/
diff --git a/firmware/target/arm/imx233/regs/stmp3700/gpiomon.h b/firmware/target/arm/imx233/regs/stmp3700/gpiomon.h
new file mode 100644
index 0000000000..ad5945dc53
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3700/gpiomon.h
@@ -0,0 +1,666 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * stmp3700 version: 2.4.0
+ * stmp3700 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_STMP3700_GPIOMON_H__
+#define __HEADERGEN_STMP3700_GPIOMON_H__
+
+#define HW_GPIOMON_BANK0_DATAIN             HW(GPIOMON_BANK0_DATAIN)
+#define HWA_GPIOMON_BANK0_DATAIN            (0x8003c300 + 0x0)
+#define HWT_GPIOMON_BANK0_DATAIN            HWIO_32_RW
+#define HWN_GPIOMON_BANK0_DATAIN            GPIOMON_BANK0_DATAIN
+#define HWI_GPIOMON_BANK0_DATAIN            
+#define BP_GPIOMON_BANK0_DATAIN_DATA        0
+#define BM_GPIOMON_BANK0_DATAIN_DATA        0xffffffff
+#define BF_GPIOMON_BANK0_DATAIN_DATA(v)     (((v) & 0xffffffff) << 0)
+#define BFM_GPIOMON_BANK0_DATAIN_DATA(v)    BM_GPIOMON_BANK0_DATAIN_DATA
+#define BF_GPIOMON_BANK0_DATAIN_DATA_V(e)   BF_GPIOMON_BANK0_DATAIN_DATA(BV_GPIOMON_BANK0_DATAIN_DATA__##e)
+#define BFM_GPIOMON_BANK0_DATAIN_DATA_V(v)  BM_GPIOMON_BANK0_DATAIN_DATA
+
+#define HW_GPIOMON_BANK1_DATAIN             HW(GPIOMON_BANK1_DATAIN)
+#define HWA_GPIOMON_BANK1_DATAIN            (0x8003c300 + 0x10)
+#define HWT_GPIOMON_BANK1_DATAIN            HWIO_32_RW
+#define HWN_GPIOMON_BANK1_DATAIN            GPIOMON_BANK1_DATAIN
+#define HWI_GPIOMON_BANK1_DATAIN            
+#define BP_GPIOMON_BANK1_DATAIN_DATA        0
+#define BM_GPIOMON_BANK1_DATAIN_DATA        0xffffffff
+#define BF_GPIOMON_BANK1_DATAIN_DATA(v)     (((v) & 0xffffffff) << 0)
+#define BFM_GPIOMON_BANK1_DATAIN_DATA(v)    BM_GPIOMON_BANK1_DATAIN_DATA
+#define BF_GPIOMON_BANK1_DATAIN_DATA_V(e)   BF_GPIOMON_BANK1_DATAIN_DATA(BV_GPIOMON_BANK1_DATAIN_DATA__##e)
+#define BFM_GPIOMON_BANK1_DATAIN_DATA_V(v)  BM_GPIOMON_BANK1_DATAIN_DATA
+
+#define HW_GPIOMON_BANK2_DATAIN             HW(GPIOMON_BANK2_DATAIN)
+#define HWA_GPIOMON_BANK2_DATAIN            (0x8003c300 + 0x20)
+#define HWT_GPIOMON_BANK2_DATAIN            HWIO_32_RW
+#define HWN_GPIOMON_BANK2_DATAIN            GPIOMON_BANK2_DATAIN
+#define HWI_GPIOMON_BANK2_DATAIN            
+#define BP_GPIOMON_BANK2_DATAIN_DATA        0
+#define BM_GPIOMON_BANK2_DATAIN_DATA        0xffffffff
+#define BF_GPIOMON_BANK2_DATAIN_DATA(v)     (((v) & 0xffffffff) << 0)
+#define BFM_GPIOMON_BANK2_DATAIN_DATA(v)    BM_GPIOMON_BANK2_DATAIN_DATA
+#define BF_GPIOMON_BANK2_DATAIN_DATA_V(e)   BF_GPIOMON_BANK2_DATAIN_DATA(BV_GPIOMON_BANK2_DATAIN_DATA__##e)
+#define BFM_GPIOMON_BANK2_DATAIN_DATA_V(v)  BM_GPIOMON_BANK2_DATAIN_DATA
+
+#define HW_GPIOMON_BANK3_DATAIN             HW(GPIOMON_BANK3_DATAIN)
+#define HWA_GPIOMON_BANK3_DATAIN            (0x8003c300 + 0x30)
+#define HWT_GPIOMON_BANK3_DATAIN            HWIO_32_RW
+#define HWN_GPIOMON_BANK3_DATAIN            GPIOMON_BANK3_DATAIN
+#define HWI_GPIOMON_BANK3_DATAIN            
+#define BP_GPIOMON_BANK3_DATAIN_DATA        0
+#define BM_GPIOMON_BANK3_DATAIN_DATA        0xffffffff
+#define BF_GPIOMON_BANK3_DATAIN_DATA(v)     (((v) & 0xffffffff) << 0)
+#define BFM_GPIOMON_BANK3_DATAIN_DATA(v)    BM_GPIOMON_BANK3_DATAIN_DATA
+#define BF_GPIOMON_BANK3_DATAIN_DATA_V(e)   BF_GPIOMON_BANK3_DATAIN_DATA(BV_GPIOMON_BANK3_DATAIN_DATA__##e)
+#define BFM_GPIOMON_BANK3_DATAIN_DATA_V(v)  BM_GPIOMON_BANK3_DATAIN_DATA
+
+#define HW_GPIOMON_BANK0_DATAOUT            HW(GPIOMON_BANK0_DATAOUT)
+#define HWA_GPIOMON_BANK0_DATAOUT           (0x8003c300 + 0x40)
+#define HWT_GPIOMON_BANK0_DATAOUT           HWIO_32_RW
+#define HWN_GPIOMON_BANK0_DATAOUT           GPIOMON_BANK0_DATAOUT
+#define HWI_GPIOMON_BANK0_DATAOUT           
+#define HW_GPIOMON_BANK0_DATAOUT_SET        HW(GPIOMON_BANK0_DATAOUT_SET)
+#define HWA_GPIOMON_BANK0_DATAOUT_SET       (HWA_GPIOMON_BANK0_DATAOUT + 0x4)
+#define HWT_GPIOMON_BANK0_DATAOUT_SET       HWIO_32_WO
+#define HWN_GPIOMON_BANK0_DATAOUT_SET       GPIOMON_BANK0_DATAOUT
+#define HWI_GPIOMON_BANK0_DATAOUT_SET       
+#define HW_GPIOMON_BANK0_DATAOUT_CLR        HW(GPIOMON_BANK0_DATAOUT_CLR)
+#define HWA_GPIOMON_BANK0_DATAOUT_CLR       (HWA_GPIOMON_BANK0_DATAOUT + 0x8)
+#define HWT_GPIOMON_BANK0_DATAOUT_CLR       HWIO_32_WO
+#define HWN_GPIOMON_BANK0_DATAOUT_CLR       GPIOMON_BANK0_DATAOUT
+#define HWI_GPIOMON_BANK0_DATAOUT_CLR       
+#define HW_GPIOMON_BANK0_DATAOUT_TOG        HW(GPIOMON_BANK0_DATAOUT_TOG)
+#define HWA_GPIOMON_BANK0_DATAOUT_TOG       (HWA_GPIOMON_BANK0_DATAOUT + 0xc)
+#define HWT_GPIOMON_BANK0_DATAOUT_TOG       HWIO_32_WO
+#define HWN_GPIOMON_BANK0_DATAOUT_TOG       GPIOMON_BANK0_DATAOUT
+#define HWI_GPIOMON_BANK0_DATAOUT_TOG       
+#define BP_GPIOMON_BANK0_DATAOUT_DATA       0
+#define BM_GPIOMON_BANK0_DATAOUT_DATA       0xffffffff
+#define BF_GPIOMON_BANK0_DATAOUT_DATA(v)    (((v) & 0xffffffff) << 0)
+#define BFM_GPIOMON_BANK0_DATAOUT_DATA(v)   BM_GPIOMON_BANK0_DATAOUT_DATA
+#define BF_GPIOMON_BANK0_DATAOUT_DATA_V(e)  BF_GPIOMON_BANK0_DATAOUT_DATA(BV_GPIOMON_BANK0_DATAOUT_DATA__##e)
+#define BFM_GPIOMON_BANK0_DATAOUT_DATA_V(v) BM_GPIOMON_BANK0_DATAOUT_DATA
+
+#define HW_GPIOMON_BANK1_DATAOUT            HW(GPIOMON_BANK1_DATAOUT)
+#define HWA_GPIOMON_BANK1_DATAOUT           (0x8003c300 + 0x50)
+#define HWT_GPIOMON_BANK1_DATAOUT           HWIO_32_RW
+#define HWN_GPIOMON_BANK1_DATAOUT           GPIOMON_BANK1_DATAOUT
+#define HWI_GPIOMON_BANK1_DATAOUT           
+#define HW_GPIOMON_BANK1_DATAOUT_SET        HW(GPIOMON_BANK1_DATAOUT_SET)
+#define HWA_GPIOMON_BANK1_DATAOUT_SET       (HWA_GPIOMON_BANK1_DATAOUT + 0x4)
+#define HWT_GPIOMON_BANK1_DATAOUT_SET       HWIO_32_WO
+#define HWN_GPIOMON_BANK1_DATAOUT_SET       GPIOMON_BANK1_DATAOUT
+#define HWI_GPIOMON_BANK1_DATAOUT_SET       
+#define HW_GPIOMON_BANK1_DATAOUT_CLR        HW(GPIOMON_BANK1_DATAOUT_CLR)
+#define HWA_GPIOMON_BANK1_DATAOUT_CLR       (HWA_GPIOMON_BANK1_DATAOUT + 0x8)
+#define HWT_GPIOMON_BANK1_DATAOUT_CLR       HWIO_32_WO
+#define HWN_GPIOMON_BANK1_DATAOUT_CLR       GPIOMON_BANK1_DATAOUT
+#define HWI_GPIOMON_BANK1_DATAOUT_CLR       
+#define HW_GPIOMON_BANK1_DATAOUT_TOG        HW(GPIOMON_BANK1_DATAOUT_TOG)
+#define HWA_GPIOMON_BANK1_DATAOUT_TOG       (HWA_GPIOMON_BANK1_DATAOUT + 0xc)
+#define HWT_GPIOMON_BANK1_DATAOUT_TOG       HWIO_32_WO
+#define HWN_GPIOMON_BANK1_DATAOUT_TOG       GPIOMON_BANK1_DATAOUT
+#define HWI_GPIOMON_BANK1_DATAOUT_TOG       
+#define BP_GPIOMON_BANK1_DATAOUT_DATA       0
+#define BM_GPIOMON_BANK1_DATAOUT_DATA       0xffffffff
+#define BF_GPIOMON_BANK1_DATAOUT_DATA(v)    (((v) & 0xffffffff) << 0)
+#define BFM_GPIOMON_BANK1_DATAOUT_DATA(v)   BM_GPIOMON_BANK1_DATAOUT_DATA
+#define BF_GPIOMON_BANK1_DATAOUT_DATA_V(e)  BF_GPIOMON_BANK1_DATAOUT_DATA(BV_GPIOMON_BANK1_DATAOUT_DATA__##e)
+#define BFM_GPIOMON_BANK1_DATAOUT_DATA_V(v) BM_GPIOMON_BANK1_DATAOUT_DATA
+
+#define HW_GPIOMON_BANK2_DATAOUT            HW(GPIOMON_BANK2_DATAOUT)
+#define HWA_GPIOMON_BANK2_DATAOUT           (0x8003c300 + 0x60)
+#define HWT_GPIOMON_BANK2_DATAOUT           HWIO_32_RW
+#define HWN_GPIOMON_BANK2_DATAOUT           GPIOMON_BANK2_DATAOUT
+#define HWI_GPIOMON_BANK2_DATAOUT           
+#define HW_GPIOMON_BANK2_DATAOUT_SET        HW(GPIOMON_BANK2_DATAOUT_SET)
+#define HWA_GPIOMON_BANK2_DATAOUT_SET       (HWA_GPIOMON_BANK2_DATAOUT + 0x4)
+#define HWT_GPIOMON_BANK2_DATAOUT_SET       HWIO_32_WO
+#define HWN_GPIOMON_BANK2_DATAOUT_SET       GPIOMON_BANK2_DATAOUT
+#define HWI_GPIOMON_BANK2_DATAOUT_SET       
+#define HW_GPIOMON_BANK2_DATAOUT_CLR        HW(GPIOMON_BANK2_DATAOUT_CLR)
+#define HWA_GPIOMON_BANK2_DATAOUT_CLR       (HWA_GPIOMON_BANK2_DATAOUT + 0x8)
+#define HWT_GPIOMON_BANK2_DATAOUT_CLR       HWIO_32_WO
+#define HWN_GPIOMON_BANK2_DATAOUT_CLR       GPIOMON_BANK2_DATAOUT
+#define HWI_GPIOMON_BANK2_DATAOUT_CLR       
+#define HW_GPIOMON_BANK2_DATAOUT_TOG        HW(GPIOMON_BANK2_DATAOUT_TOG)
+#define HWA_GPIOMON_BANK2_DATAOUT_TOG       (HWA_GPIOMON_BANK2_DATAOUT + 0xc)
+#define HWT_GPIOMON_BANK2_DATAOUT_TOG       HWIO_32_WO
+#define HWN_GPIOMON_BANK2_DATAOUT_TOG       GPIOMON_BANK2_DATAOUT
+#define HWI_GPIOMON_BANK2_DATAOUT_TOG       
+#define BP_GPIOMON_BANK2_DATAOUT_DATA       0
+#define BM_GPIOMON_BANK2_DATAOUT_DATA       0xffffffff
+#define BF_GPIOMON_BANK2_DATAOUT_DATA(v)    (((v) & 0xffffffff) << 0)
+#define BFM_GPIOMON_BANK2_DATAOUT_DATA(v)   BM_GPIOMON_BANK2_DATAOUT_DATA
+#define BF_GPIOMON_BANK2_DATAOUT_DATA_V(e)  BF_GPIOMON_BANK2_DATAOUT_DATA(BV_GPIOMON_BANK2_DATAOUT_DATA__##e)
+#define BFM_GPIOMON_BANK2_DATAOUT_DATA_V(v) BM_GPIOMON_BANK2_DATAOUT_DATA
+
+#define HW_GPIOMON_BANK3_DATAOUT            HW(GPIOMON_BANK3_DATAOUT)
+#define HWA_GPIOMON_BANK3_DATAOUT           (0x8003c300 + 0x70)
+#define HWT_GPIOMON_BANK3_DATAOUT           HWIO_32_RW
+#define HWN_GPIOMON_BANK3_DATAOUT           GPIOMON_BANK3_DATAOUT
+#define HWI_GPIOMON_BANK3_DATAOUT           
+#define HW_GPIOMON_BANK3_DATAOUT_SET        HW(GPIOMON_BANK3_DATAOUT_SET)
+#define HWA_GPIOMON_BANK3_DATAOUT_SET       (HWA_GPIOMON_BANK3_DATAOUT + 0x4)
+#define HWT_GPIOMON_BANK3_DATAOUT_SET       HWIO_32_WO
+#define HWN_GPIOMON_BANK3_DATAOUT_SET       GPIOMON_BANK3_DATAOUT
+#define HWI_GPIOMON_BANK3_DATAOUT_SET       
+#define HW_GPIOMON_BANK3_DATAOUT_CLR        HW(GPIOMON_BANK3_DATAOUT_CLR)
+#define HWA_GPIOMON_BANK3_DATAOUT_CLR       (HWA_GPIOMON_BANK3_DATAOUT + 0x8)
+#define HWT_GPIOMON_BANK3_DATAOUT_CLR       HWIO_32_WO
+#define HWN_GPIOMON_BANK3_DATAOUT_CLR       GPIOMON_BANK3_DATAOUT
+#define HWI_GPIOMON_BANK3_DATAOUT_CLR       
+#define HW_GPIOMON_BANK3_DATAOUT_TOG        HW(GPIOMON_BANK3_DATAOUT_TOG)
+#define HWA_GPIOMON_BANK3_DATAOUT_TOG       (HWA_GPIOMON_BANK3_DATAOUT + 0xc)
+#define HWT_GPIOMON_BANK3_DATAOUT_TOG       HWIO_32_WO
+#define HWN_GPIOMON_BANK3_DATAOUT_TOG       GPIOMON_BANK3_DATAOUT
+#define HWI_GPIOMON_BANK3_DATAOUT_TOG       
+#define BP_GPIOMON_BANK3_DATAOUT_DATA       0
+#define BM_GPIOMON_BANK3_DATAOUT_DATA       0xffffffff
+#define BF_GPIOMON_BANK3_DATAOUT_DATA(v)    (((v) & 0xffffffff) << 0)
+#define BFM_GPIOMON_BANK3_DATAOUT_DATA(v)   BM_GPIOMON_BANK3_DATAOUT_DATA
+#define BF_GPIOMON_BANK3_DATAOUT_DATA_V(e)  BF_GPIOMON_BANK3_DATAOUT_DATA(BV_GPIOMON_BANK3_DATAOUT_DATA__##e)
+#define BFM_GPIOMON_BANK3_DATAOUT_DATA_V(v) BM_GPIOMON_BANK3_DATAOUT_DATA
+
+#define HW_GPIOMON_BANK0_DATAOEN                        HW(GPIOMON_BANK0_DATAOEN)
+#define HWA_GPIOMON_BANK0_DATAOEN                       (0x8003c300 + 0x80)
+#define HWT_GPIOMON_BANK0_DATAOEN                       HWIO_32_RW
+#define HWN_GPIOMON_BANK0_DATAOEN                       GPIOMON_BANK0_DATAOEN
+#define HWI_GPIOMON_BANK0_DATAOEN                       
+#define HW_GPIOMON_BANK0_DATAOEN_SET                    HW(GPIOMON_BANK0_DATAOEN_SET)
+#define HWA_GPIOMON_BANK0_DATAOEN_SET                   (HWA_GPIOMON_BANK0_DATAOEN + 0x4)
+#define HWT_GPIOMON_BANK0_DATAOEN_SET                   HWIO_32_WO
+#define HWN_GPIOMON_BANK0_DATAOEN_SET                   GPIOMON_BANK0_DATAOEN
+#define HWI_GPIOMON_BANK0_DATAOEN_SET                   
+#define HW_GPIOMON_BANK0_DATAOEN_CLR                    HW(GPIOMON_BANK0_DATAOEN_CLR)
+#define HWA_GPIOMON_BANK0_DATAOEN_CLR                   (HWA_GPIOMON_BANK0_DATAOEN + 0x8)
+#define HWT_GPIOMON_BANK0_DATAOEN_CLR                   HWIO_32_WO
+#define HWN_GPIOMON_BANK0_DATAOEN_CLR                   GPIOMON_BANK0_DATAOEN
+#define HWI_GPIOMON_BANK0_DATAOEN_CLR                   
+#define HW_GPIOMON_BANK0_DATAOEN_TOG                    HW(GPIOMON_BANK0_DATAOEN_TOG)
+#define HWA_GPIOMON_BANK0_DATAOEN_TOG                   (HWA_GPIOMON_BANK0_DATAOEN + 0xc)
+#define HWT_GPIOMON_BANK0_DATAOEN_TOG                   HWIO_32_WO
+#define HWN_GPIOMON_BANK0_DATAOEN_TOG                   GPIOMON_BANK0_DATAOEN
+#define HWI_GPIOMON_BANK0_DATAOEN_TOG                   
+#define BP_GPIOMON_BANK0_DATAOEN_OUTPUT_ENABLES         0
+#define BM_GPIOMON_BANK0_DATAOEN_OUTPUT_ENABLES         0xffffffff
+#define BF_GPIOMON_BANK0_DATAOEN_OUTPUT_ENABLES(v)      (((v) & 0xffffffff) << 0)
+#define BFM_GPIOMON_BANK0_DATAOEN_OUTPUT_ENABLES(v)     BM_GPIOMON_BANK0_DATAOEN_OUTPUT_ENABLES
+#define BF_GPIOMON_BANK0_DATAOEN_OUTPUT_ENABLES_V(e)    BF_GPIOMON_BANK0_DATAOEN_OUTPUT_ENABLES(BV_GPIOMON_BANK0_DATAOEN_OUTPUT_ENABLES__##e)
+#define BFM_GPIOMON_BANK0_DATAOEN_OUTPUT_ENABLES_V(v)   BM_GPIOMON_BANK0_DATAOEN_OUTPUT_ENABLES
+
+#define HW_GPIOMON_BANK1_DATAOEN                        HW(GPIOMON_BANK1_DATAOEN)
+#define HWA_GPIOMON_BANK1_DATAOEN                       (0x8003c300 + 0x90)
+#define HWT_GPIOMON_BANK1_DATAOEN                       HWIO_32_RW
+#define HWN_GPIOMON_BANK1_DATAOEN                       GPIOMON_BANK1_DATAOEN
+#define HWI_GPIOMON_BANK1_DATAOEN                       
+#define HW_GPIOMON_BANK1_DATAOEN_SET                    HW(GPIOMON_BANK1_DATAOEN_SET)
+#define HWA_GPIOMON_BANK1_DATAOEN_SET                   (HWA_GPIOMON_BANK1_DATAOEN + 0x4)
+#define HWT_GPIOMON_BANK1_DATAOEN_SET                   HWIO_32_WO
+#define HWN_GPIOMON_BANK1_DATAOEN_SET                   GPIOMON_BANK1_DATAOEN
+#define HWI_GPIOMON_BANK1_DATAOEN_SET                   
+#define HW_GPIOMON_BANK1_DATAOEN_CLR                    HW(GPIOMON_BANK1_DATAOEN_CLR)
+#define HWA_GPIOMON_BANK1_DATAOEN_CLR                   (HWA_GPIOMON_BANK1_DATAOEN + 0x8)
+#define HWT_GPIOMON_BANK1_DATAOEN_CLR                   HWIO_32_WO
+#define HWN_GPIOMON_BANK1_DATAOEN_CLR                   GPIOMON_BANK1_DATAOEN
+#define HWI_GPIOMON_BANK1_DATAOEN_CLR                   
+#define HW_GPIOMON_BANK1_DATAOEN_TOG                    HW(GPIOMON_BANK1_DATAOEN_TOG)
+#define HWA_GPIOMON_BANK1_DATAOEN_TOG                   (HWA_GPIOMON_BANK1_DATAOEN + 0xc)
+#define HWT_GPIOMON_BANK1_DATAOEN_TOG                   HWIO_32_WO
+#define HWN_GPIOMON_BANK1_DATAOEN_TOG                   GPIOMON_BANK1_DATAOEN
+#define HWI_GPIOMON_BANK1_DATAOEN_TOG                   
+#define BP_GPIOMON_BANK1_DATAOEN_OUTPUT_ENABLES         0
+#define BM_GPIOMON_BANK1_DATAOEN_OUTPUT_ENABLES         0xffffffff
+#define BF_GPIOMON_BANK1_DATAOEN_OUTPUT_ENABLES(v)      (((v) & 0xffffffff) << 0)
+#define BFM_GPIOMON_BANK1_DATAOEN_OUTPUT_ENABLES(v)     BM_GPIOMON_BANK1_DATAOEN_OUTPUT_ENABLES
+#define BF_GPIOMON_BANK1_DATAOEN_OUTPUT_ENABLES_V(e)    BF_GPIOMON_BANK1_DATAOEN_OUTPUT_ENABLES(BV_GPIOMON_BANK1_DATAOEN_OUTPUT_ENABLES__##e)
+#define BFM_GPIOMON_BANK1_DATAOEN_OUTPUT_ENABLES_V(v)   BM_GPIOMON_BANK1_DATAOEN_OUTPUT_ENABLES
+
+#define HW_GPIOMON_BANK2_DATAOEN                        HW(GPIOMON_BANK2_DATAOEN)
+#define HWA_GPIOMON_BANK2_DATAOEN                       (0x8003c300 + 0xa0)
+#define HWT_GPIOMON_BANK2_DATAOEN                       HWIO_32_RW
+#define HWN_GPIOMON_BANK2_DATAOEN                       GPIOMON_BANK2_DATAOEN
+#define HWI_GPIOMON_BANK2_DATAOEN                       
+#define HW_GPIOMON_BANK2_DATAOEN_SET                    HW(GPIOMON_BANK2_DATAOEN_SET)
+#define HWA_GPIOMON_BANK2_DATAOEN_SET                   (HWA_GPIOMON_BANK2_DATAOEN + 0x4)
+#define HWT_GPIOMON_BANK2_DATAOEN_SET                   HWIO_32_WO
+#define HWN_GPIOMON_BANK2_DATAOEN_SET                   GPIOMON_BANK2_DATAOEN
+#define HWI_GPIOMON_BANK2_DATAOEN_SET                   
+#define HW_GPIOMON_BANK2_DATAOEN_CLR                    HW(GPIOMON_BANK2_DATAOEN_CLR)
+#define HWA_GPIOMON_BANK2_DATAOEN_CLR                   (HWA_GPIOMON_BANK2_DATAOEN + 0x8)
+#define HWT_GPIOMON_BANK2_DATAOEN_CLR                   HWIO_32_WO
+#define HWN_GPIOMON_BANK2_DATAOEN_CLR                   GPIOMON_BANK2_DATAOEN
+#define HWI_GPIOMON_BANK2_DATAOEN_CLR                   
+#define HW_GPIOMON_BANK2_DATAOEN_TOG                    HW(GPIOMON_BANK2_DATAOEN_TOG)
+#define HWA_GPIOMON_BANK2_DATAOEN_TOG                   (HWA_GPIOMON_BANK2_DATAOEN + 0xc)
+#define HWT_GPIOMON_BANK2_DATAOEN_TOG                   HWIO_32_WO
+#define HWN_GPIOMON_BANK2_DATAOEN_TOG                   GPIOMON_BANK2_DATAOEN
+#define HWI_GPIOMON_BANK2_DATAOEN_TOG                   
+#define BP_GPIOMON_BANK2_DATAOEN_OUTPUT_ENABLES         0
+#define BM_GPIOMON_BANK2_DATAOEN_OUTPUT_ENABLES         0xffffffff
+#define BF_GPIOMON_BANK2_DATAOEN_OUTPUT_ENABLES(v)      (((v) & 0xffffffff) << 0)
+#define BFM_GPIOMON_BANK2_DATAOEN_OUTPUT_ENABLES(v)     BM_GPIOMON_BANK2_DATAOEN_OUTPUT_ENABLES
+#define BF_GPIOMON_BANK2_DATAOEN_OUTPUT_ENABLES_V(e)    BF_GPIOMON_BANK2_DATAOEN_OUTPUT_ENABLES(BV_GPIOMON_BANK2_DATAOEN_OUTPUT_ENABLES__##e)
+#define BFM_GPIOMON_BANK2_DATAOEN_OUTPUT_ENABLES_V(v)   BM_GPIOMON_BANK2_DATAOEN_OUTPUT_ENABLES
+
+#define HW_GPIOMON_BANK3_DATAOEN                        HW(GPIOMON_BANK3_DATAOEN)
+#define HWA_GPIOMON_BANK3_DATAOEN                       (0x8003c300 + 0xb0)
+#define HWT_GPIOMON_BANK3_DATAOEN                       HWIO_32_RW
+#define HWN_GPIOMON_BANK3_DATAOEN                       GPIOMON_BANK3_DATAOEN
+#define HWI_GPIOMON_BANK3_DATAOEN                       
+#define HW_GPIOMON_BANK3_DATAOEN_SET                    HW(GPIOMON_BANK3_DATAOEN_SET)
+#define HWA_GPIOMON_BANK3_DATAOEN_SET                   (HWA_GPIOMON_BANK3_DATAOEN + 0x4)
+#define HWT_GPIOMON_BANK3_DATAOEN_SET                   HWIO_32_WO
+#define HWN_GPIOMON_BANK3_DATAOEN_SET                   GPIOMON_BANK3_DATAOEN
+#define HWI_GPIOMON_BANK3_DATAOEN_SET                   
+#define HW_GPIOMON_BANK3_DATAOEN_CLR                    HW(GPIOMON_BANK3_DATAOEN_CLR)
+#define HWA_GPIOMON_BANK3_DATAOEN_CLR                   (HWA_GPIOMON_BANK3_DATAOEN + 0x8)
+#define HWT_GPIOMON_BANK3_DATAOEN_CLR                   HWIO_32_WO
+#define HWN_GPIOMON_BANK3_DATAOEN_CLR                   GPIOMON_BANK3_DATAOEN
+#define HWI_GPIOMON_BANK3_DATAOEN_CLR                   
+#define HW_GPIOMON_BANK3_DATAOEN_TOG                    HW(GPIOMON_BANK3_DATAOEN_TOG)
+#define HWA_GPIOMON_BANK3_DATAOEN_TOG                   (HWA_GPIOMON_BANK3_DATAOEN + 0xc)
+#define HWT_GPIOMON_BANK3_DATAOEN_TOG                   HWIO_32_WO
+#define HWN_GPIOMON_BANK3_DATAOEN_TOG                   GPIOMON_BANK3_DATAOEN
+#define HWI_GPIOMON_BANK3_DATAOEN_TOG                   
+#define BP_GPIOMON_BANK3_DATAOEN_OUTPUT_ENABLES         0
+#define BM_GPIOMON_BANK3_DATAOEN_OUTPUT_ENABLES         0xffffffff
+#define BF_GPIOMON_BANK3_DATAOEN_OUTPUT_ENABLES(v)      (((v) & 0xffffffff) << 0)
+#define BFM_GPIOMON_BANK3_DATAOEN_OUTPUT_ENABLES(v)     BM_GPIOMON_BANK3_DATAOEN_OUTPUT_ENABLES
+#define BF_GPIOMON_BANK3_DATAOEN_OUTPUT_ENABLES_V(e)    BF_GPIOMON_BANK3_DATAOEN_OUTPUT_ENABLES(BV_GPIOMON_BANK3_DATAOEN_OUTPUT_ENABLES__##e)
+#define BFM_GPIOMON_BANK3_DATAOEN_OUTPUT_ENABLES_V(v)   BM_GPIOMON_BANK3_DATAOEN_OUTPUT_ENABLES
+
+#define HW_GPIOMON_CTRL                         HW(GPIOMON_CTRL)
+#define HWA_GPIOMON_CTRL                        (0x8003c300 + 0xc0)
+#define HWT_GPIOMON_CTRL                        HWIO_32_RW
+#define HWN_GPIOMON_CTRL                        GPIOMON_CTRL
+#define HWI_GPIOMON_CTRL                        
+#define HW_GPIOMON_CTRL_SET                     HW(GPIOMON_CTRL_SET)
+#define HWA_GPIOMON_CTRL_SET                    (HWA_GPIOMON_CTRL + 0x4)
+#define HWT_GPIOMON_CTRL_SET                    HWIO_32_WO
+#define HWN_GPIOMON_CTRL_SET                    GPIOMON_CTRL
+#define HWI_GPIOMON_CTRL_SET                    
+#define HW_GPIOMON_CTRL_CLR                     HW(GPIOMON_CTRL_CLR)
+#define HWA_GPIOMON_CTRL_CLR                    (HWA_GPIOMON_CTRL + 0x8)
+#define HWT_GPIOMON_CTRL_CLR                    HWIO_32_WO
+#define HWN_GPIOMON_CTRL_CLR                    GPIOMON_CTRL
+#define HWI_GPIOMON_CTRL_CLR                    
+#define HW_GPIOMON_CTRL_TOG                     HW(GPIOMON_CTRL_TOG)
+#define HWA_GPIOMON_CTRL_TOG                    (HWA_GPIOMON_CTRL + 0xc)
+#define HWT_GPIOMON_CTRL_TOG                    HWIO_32_WO
+#define HWN_GPIOMON_CTRL_TOG                    GPIOMON_CTRL
+#define HWI_GPIOMON_CTRL_TOG                    
+#define BP_GPIOMON_CTRL_RSRVD                   4
+#define BM_GPIOMON_CTRL_RSRVD                   0xfffffff0
+#define BF_GPIOMON_CTRL_RSRVD(v)                (((v) & 0xfffffff) << 4)
+#define BFM_GPIOMON_CTRL_RSRVD(v)               BM_GPIOMON_CTRL_RSRVD
+#define BF_GPIOMON_CTRL_RSRVD_V(e)              BF_GPIOMON_CTRL_RSRVD(BV_GPIOMON_CTRL_RSRVD__##e)
+#define BFM_GPIOMON_CTRL_RSRVD_V(v)             BM_GPIOMON_CTRL_RSRVD
+#define BP_GPIOMON_CTRL_PINMUX_ALT_RESET        3
+#define BM_GPIOMON_CTRL_PINMUX_ALT_RESET        0x8
+#define BF_GPIOMON_CTRL_PINMUX_ALT_RESET(v)     (((v) & 0x1) << 3)
+#define BFM_GPIOMON_CTRL_PINMUX_ALT_RESET(v)    BM_GPIOMON_CTRL_PINMUX_ALT_RESET
+#define BF_GPIOMON_CTRL_PINMUX_ALT_RESET_V(e)   BF_GPIOMON_CTRL_PINMUX_ALT_RESET(BV_GPIOMON_CTRL_PINMUX_ALT_RESET__##e)
+#define BFM_GPIOMON_CTRL_PINMUX_ALT_RESET_V(v)  BM_GPIOMON_CTRL_PINMUX_ALT_RESET
+#define BP_GPIOMON_CTRL_OEN_8MA                 2
+#define BM_GPIOMON_CTRL_OEN_8MA                 0x4
+#define BF_GPIOMON_CTRL_OEN_8MA(v)              (((v) & 0x1) << 2)
+#define BFM_GPIOMON_CTRL_OEN_8MA(v)             BM_GPIOMON_CTRL_OEN_8MA
+#define BF_GPIOMON_CTRL_OEN_8MA_V(e)            BF_GPIOMON_CTRL_OEN_8MA(BV_GPIOMON_CTRL_OEN_8MA__##e)
+#define BFM_GPIOMON_CTRL_OEN_8MA_V(v)           BM_GPIOMON_CTRL_OEN_8MA
+#define BP_GPIOMON_CTRL_OEN_4MA                 1
+#define BM_GPIOMON_CTRL_OEN_4MA                 0x2
+#define BF_GPIOMON_CTRL_OEN_4MA(v)              (((v) & 0x1) << 1)
+#define BFM_GPIOMON_CTRL_OEN_4MA(v)             BM_GPIOMON_CTRL_OEN_4MA
+#define BF_GPIOMON_CTRL_OEN_4MA_V(e)            BF_GPIOMON_CTRL_OEN_4MA(BV_GPIOMON_CTRL_OEN_4MA__##e)
+#define BFM_GPIOMON_CTRL_OEN_4MA_V(v)           BM_GPIOMON_CTRL_OEN_4MA
+#define BP_GPIOMON_CTRL_OEN_NAND                0
+#define BM_GPIOMON_CTRL_OEN_NAND                0x1
+#define BF_GPIOMON_CTRL_OEN_NAND(v)             (((v) & 0x1) << 0)
+#define BFM_GPIOMON_CTRL_OEN_NAND(v)            BM_GPIOMON_CTRL_OEN_NAND
+#define BF_GPIOMON_CTRL_OEN_NAND_V(e)           BF_GPIOMON_CTRL_OEN_NAND(BV_GPIOMON_CTRL_OEN_NAND__##e)
+#define BFM_GPIOMON_CTRL_OEN_NAND_V(v)          BM_GPIOMON_CTRL_OEN_NAND
+
+#define HW_GPIOMON_ALT1_PINMUX_BANK0                HW(GPIOMON_ALT1_PINMUX_BANK0)
+#define HWA_GPIOMON_ALT1_PINMUX_BANK0               (0x8003c300 + 0xd0)
+#define HWT_GPIOMON_ALT1_PINMUX_BANK0               HWIO_32_RW
+#define HWN_GPIOMON_ALT1_PINMUX_BANK0               GPIOMON_ALT1_PINMUX_BANK0
+#define HWI_GPIOMON_ALT1_PINMUX_BANK0               
+#define HW_GPIOMON_ALT1_PINMUX_BANK0_SET            HW(GPIOMON_ALT1_PINMUX_BANK0_SET)
+#define HWA_GPIOMON_ALT1_PINMUX_BANK0_SET           (HWA_GPIOMON_ALT1_PINMUX_BANK0 + 0x4)
+#define HWT_GPIOMON_ALT1_PINMUX_BANK0_SET           HWIO_32_WO
+#define HWN_GPIOMON_ALT1_PINMUX_BANK0_SET           GPIOMON_ALT1_PINMUX_BANK0
+#define HWI_GPIOMON_ALT1_PINMUX_BANK0_SET           
+#define HW_GPIOMON_ALT1_PINMUX_BANK0_CLR            HW(GPIOMON_ALT1_PINMUX_BANK0_CLR)
+#define HWA_GPIOMON_ALT1_PINMUX_BANK0_CLR           (HWA_GPIOMON_ALT1_PINMUX_BANK0 + 0x8)
+#define HWT_GPIOMON_ALT1_PINMUX_BANK0_CLR           HWIO_32_WO
+#define HWN_GPIOMON_ALT1_PINMUX_BANK0_CLR           GPIOMON_ALT1_PINMUX_BANK0
+#define HWI_GPIOMON_ALT1_PINMUX_BANK0_CLR           
+#define HW_GPIOMON_ALT1_PINMUX_BANK0_TOG            HW(GPIOMON_ALT1_PINMUX_BANK0_TOG)
+#define HWA_GPIOMON_ALT1_PINMUX_BANK0_TOG           (HWA_GPIOMON_ALT1_PINMUX_BANK0 + 0xc)
+#define HWT_GPIOMON_ALT1_PINMUX_BANK0_TOG           HWIO_32_WO
+#define HWN_GPIOMON_ALT1_PINMUX_BANK0_TOG           GPIOMON_ALT1_PINMUX_BANK0
+#define HWI_GPIOMON_ALT1_PINMUX_BANK0_TOG           
+#define BP_GPIOMON_ALT1_PINMUX_BANK0_INDEX          0
+#define BM_GPIOMON_ALT1_PINMUX_BANK0_INDEX          0xffffffff
+#define BF_GPIOMON_ALT1_PINMUX_BANK0_INDEX(v)       (((v) & 0xffffffff) << 0)
+#define BFM_GPIOMON_ALT1_PINMUX_BANK0_INDEX(v)      BM_GPIOMON_ALT1_PINMUX_BANK0_INDEX
+#define BF_GPIOMON_ALT1_PINMUX_BANK0_INDEX_V(e)     BF_GPIOMON_ALT1_PINMUX_BANK0_INDEX(BV_GPIOMON_ALT1_PINMUX_BANK0_INDEX__##e)
+#define BFM_GPIOMON_ALT1_PINMUX_BANK0_INDEX_V(v)    BM_GPIOMON_ALT1_PINMUX_BANK0_INDEX
+
+#define HW_GPIOMON_ALT1_PINMUX_BANK1                HW(GPIOMON_ALT1_PINMUX_BANK1)
+#define HWA_GPIOMON_ALT1_PINMUX_BANK1               (0x8003c300 + 0xe0)
+#define HWT_GPIOMON_ALT1_PINMUX_BANK1               HWIO_32_RW
+#define HWN_GPIOMON_ALT1_PINMUX_BANK1               GPIOMON_ALT1_PINMUX_BANK1
+#define HWI_GPIOMON_ALT1_PINMUX_BANK1               
+#define HW_GPIOMON_ALT1_PINMUX_BANK1_SET            HW(GPIOMON_ALT1_PINMUX_BANK1_SET)
+#define HWA_GPIOMON_ALT1_PINMUX_BANK1_SET           (HWA_GPIOMON_ALT1_PINMUX_BANK1 + 0x4)
+#define HWT_GPIOMON_ALT1_PINMUX_BANK1_SET           HWIO_32_WO
+#define HWN_GPIOMON_ALT1_PINMUX_BANK1_SET           GPIOMON_ALT1_PINMUX_BANK1
+#define HWI_GPIOMON_ALT1_PINMUX_BANK1_SET           
+#define HW_GPIOMON_ALT1_PINMUX_BANK1_CLR            HW(GPIOMON_ALT1_PINMUX_BANK1_CLR)
+#define HWA_GPIOMON_ALT1_PINMUX_BANK1_CLR           (HWA_GPIOMON_ALT1_PINMUX_BANK1 + 0x8)
+#define HWT_GPIOMON_ALT1_PINMUX_BANK1_CLR           HWIO_32_WO
+#define HWN_GPIOMON_ALT1_PINMUX_BANK1_CLR           GPIOMON_ALT1_PINMUX_BANK1
+#define HWI_GPIOMON_ALT1_PINMUX_BANK1_CLR           
+#define HW_GPIOMON_ALT1_PINMUX_BANK1_TOG            HW(GPIOMON_ALT1_PINMUX_BANK1_TOG)
+#define HWA_GPIOMON_ALT1_PINMUX_BANK1_TOG           (HWA_GPIOMON_ALT1_PINMUX_BANK1 + 0xc)
+#define HWT_GPIOMON_ALT1_PINMUX_BANK1_TOG           HWIO_32_WO
+#define HWN_GPIOMON_ALT1_PINMUX_BANK1_TOG           GPIOMON_ALT1_PINMUX_BANK1
+#define HWI_GPIOMON_ALT1_PINMUX_BANK1_TOG           
+#define BP_GPIOMON_ALT1_PINMUX_BANK1_INDEX          0
+#define BM_GPIOMON_ALT1_PINMUX_BANK1_INDEX          0xffffffff
+#define BF_GPIOMON_ALT1_PINMUX_BANK1_INDEX(v)       (((v) & 0xffffffff) << 0)
+#define BFM_GPIOMON_ALT1_PINMUX_BANK1_INDEX(v)      BM_GPIOMON_ALT1_PINMUX_BANK1_INDEX
+#define BF_GPIOMON_ALT1_PINMUX_BANK1_INDEX_V(e)     BF_GPIOMON_ALT1_PINMUX_BANK1_INDEX(BV_GPIOMON_ALT1_PINMUX_BANK1_INDEX__##e)
+#define BFM_GPIOMON_ALT1_PINMUX_BANK1_INDEX_V(v)    BM_GPIOMON_ALT1_PINMUX_BANK1_INDEX
+
+#define HW_GPIOMON_ALT1_PINMUX_BANK2                HW(GPIOMON_ALT1_PINMUX_BANK2)
+#define HWA_GPIOMON_ALT1_PINMUX_BANK2               (0x8003c300 + 0xf0)
+#define HWT_GPIOMON_ALT1_PINMUX_BANK2               HWIO_32_RW
+#define HWN_GPIOMON_ALT1_PINMUX_BANK2               GPIOMON_ALT1_PINMUX_BANK2
+#define HWI_GPIOMON_ALT1_PINMUX_BANK2               
+#define HW_GPIOMON_ALT1_PINMUX_BANK2_SET            HW(GPIOMON_ALT1_PINMUX_BANK2_SET)
+#define HWA_GPIOMON_ALT1_PINMUX_BANK2_SET           (HWA_GPIOMON_ALT1_PINMUX_BANK2 + 0x4)
+#define HWT_GPIOMON_ALT1_PINMUX_BANK2_SET           HWIO_32_WO
+#define HWN_GPIOMON_ALT1_PINMUX_BANK2_SET           GPIOMON_ALT1_PINMUX_BANK2
+#define HWI_GPIOMON_ALT1_PINMUX_BANK2_SET           
+#define HW_GPIOMON_ALT1_PINMUX_BANK2_CLR            HW(GPIOMON_ALT1_PINMUX_BANK2_CLR)
+#define HWA_GPIOMON_ALT1_PINMUX_BANK2_CLR           (HWA_GPIOMON_ALT1_PINMUX_BANK2 + 0x8)
+#define HWT_GPIOMON_ALT1_PINMUX_BANK2_CLR           HWIO_32_WO
+#define HWN_GPIOMON_ALT1_PINMUX_BANK2_CLR           GPIOMON_ALT1_PINMUX_BANK2
+#define HWI_GPIOMON_ALT1_PINMUX_BANK2_CLR           
+#define HW_GPIOMON_ALT1_PINMUX_BANK2_TOG            HW(GPIOMON_ALT1_PINMUX_BANK2_TOG)
+#define HWA_GPIOMON_ALT1_PINMUX_BANK2_TOG           (HWA_GPIOMON_ALT1_PINMUX_BANK2 + 0xc)
+#define HWT_GPIOMON_ALT1_PINMUX_BANK2_TOG           HWIO_32_WO
+#define HWN_GPIOMON_ALT1_PINMUX_BANK2_TOG           GPIOMON_ALT1_PINMUX_BANK2
+#define HWI_GPIOMON_ALT1_PINMUX_BANK2_TOG           
+#define BP_GPIOMON_ALT1_PINMUX_BANK2_INDEX          0
+#define BM_GPIOMON_ALT1_PINMUX_BANK2_INDEX          0xffffffff
+#define BF_GPIOMON_ALT1_PINMUX_BANK2_INDEX(v)       (((v) & 0xffffffff) << 0)
+#define BFM_GPIOMON_ALT1_PINMUX_BANK2_INDEX(v)      BM_GPIOMON_ALT1_PINMUX_BANK2_INDEX
+#define BF_GPIOMON_ALT1_PINMUX_BANK2_INDEX_V(e)     BF_GPIOMON_ALT1_PINMUX_BANK2_INDEX(BV_GPIOMON_ALT1_PINMUX_BANK2_INDEX__##e)
+#define BFM_GPIOMON_ALT1_PINMUX_BANK2_INDEX_V(v)    BM_GPIOMON_ALT1_PINMUX_BANK2_INDEX
+
+#define HW_GPIOMON_ALT1_PINMUX_BANK3                HW(GPIOMON_ALT1_PINMUX_BANK3)
+#define HWA_GPIOMON_ALT1_PINMUX_BANK3               (0x8003c300 + 0x100)
+#define HWT_GPIOMON_ALT1_PINMUX_BANK3               HWIO_32_RW
+#define HWN_GPIOMON_ALT1_PINMUX_BANK3               GPIOMON_ALT1_PINMUX_BANK3
+#define HWI_GPIOMON_ALT1_PINMUX_BANK3               
+#define HW_GPIOMON_ALT1_PINMUX_BANK3_SET            HW(GPIOMON_ALT1_PINMUX_BANK3_SET)
+#define HWA_GPIOMON_ALT1_PINMUX_BANK3_SET           (HWA_GPIOMON_ALT1_PINMUX_BANK3 + 0x4)
+#define HWT_GPIOMON_ALT1_PINMUX_BANK3_SET           HWIO_32_WO
+#define HWN_GPIOMON_ALT1_PINMUX_BANK3_SET           GPIOMON_ALT1_PINMUX_BANK3
+#define HWI_GPIOMON_ALT1_PINMUX_BANK3_SET           
+#define HW_GPIOMON_ALT1_PINMUX_BANK3_CLR            HW(GPIOMON_ALT1_PINMUX_BANK3_CLR)
+#define HWA_GPIOMON_ALT1_PINMUX_BANK3_CLR           (HWA_GPIOMON_ALT1_PINMUX_BANK3 + 0x8)
+#define HWT_GPIOMON_ALT1_PINMUX_BANK3_CLR           HWIO_32_WO
+#define HWN_GPIOMON_ALT1_PINMUX_BANK3_CLR           GPIOMON_ALT1_PINMUX_BANK3
+#define HWI_GPIOMON_ALT1_PINMUX_BANK3_CLR           
+#define HW_GPIOMON_ALT1_PINMUX_BANK3_TOG            HW(GPIOMON_ALT1_PINMUX_BANK3_TOG)
+#define HWA_GPIOMON_ALT1_PINMUX_BANK3_TOG           (HWA_GPIOMON_ALT1_PINMUX_BANK3 + 0xc)
+#define HWT_GPIOMON_ALT1_PINMUX_BANK3_TOG           HWIO_32_WO
+#define HWN_GPIOMON_ALT1_PINMUX_BANK3_TOG           GPIOMON_ALT1_PINMUX_BANK3
+#define HWI_GPIOMON_ALT1_PINMUX_BANK3_TOG           
+#define BP_GPIOMON_ALT1_PINMUX_BANK3_INDEX          0
+#define BM_GPIOMON_ALT1_PINMUX_BANK3_INDEX          0xffffffff
+#define BF_GPIOMON_ALT1_PINMUX_BANK3_INDEX(v)       (((v) & 0xffffffff) << 0)
+#define BFM_GPIOMON_ALT1_PINMUX_BANK3_INDEX(v)      BM_GPIOMON_ALT1_PINMUX_BANK3_INDEX
+#define BF_GPIOMON_ALT1_PINMUX_BANK3_INDEX_V(e)     BF_GPIOMON_ALT1_PINMUX_BANK3_INDEX(BV_GPIOMON_ALT1_PINMUX_BANK3_INDEX__##e)
+#define BFM_GPIOMON_ALT1_PINMUX_BANK3_INDEX_V(v)    BM_GPIOMON_ALT1_PINMUX_BANK3_INDEX
+
+#define HW_GPIOMON_ALT2_PINMUX_BANK0                HW(GPIOMON_ALT2_PINMUX_BANK0)
+#define HWA_GPIOMON_ALT2_PINMUX_BANK0               (0x8003c300 + 0x110)
+#define HWT_GPIOMON_ALT2_PINMUX_BANK0               HWIO_32_RW
+#define HWN_GPIOMON_ALT2_PINMUX_BANK0               GPIOMON_ALT2_PINMUX_BANK0
+#define HWI_GPIOMON_ALT2_PINMUX_BANK0               
+#define HW_GPIOMON_ALT2_PINMUX_BANK0_SET            HW(GPIOMON_ALT2_PINMUX_BANK0_SET)
+#define HWA_GPIOMON_ALT2_PINMUX_BANK0_SET           (HWA_GPIOMON_ALT2_PINMUX_BANK0 + 0x4)
+#define HWT_GPIOMON_ALT2_PINMUX_BANK0_SET           HWIO_32_WO
+#define HWN_GPIOMON_ALT2_PINMUX_BANK0_SET           GPIOMON_ALT2_PINMUX_BANK0
+#define HWI_GPIOMON_ALT2_PINMUX_BANK0_SET           
+#define HW_GPIOMON_ALT2_PINMUX_BANK0_CLR            HW(GPIOMON_ALT2_PINMUX_BANK0_CLR)
+#define HWA_GPIOMON_ALT2_PINMUX_BANK0_CLR           (HWA_GPIOMON_ALT2_PINMUX_BANK0 + 0x8)
+#define HWT_GPIOMON_ALT2_PINMUX_BANK0_CLR           HWIO_32_WO
+#define HWN_GPIOMON_ALT2_PINMUX_BANK0_CLR           GPIOMON_ALT2_PINMUX_BANK0
+#define HWI_GPIOMON_ALT2_PINMUX_BANK0_CLR           
+#define HW_GPIOMON_ALT2_PINMUX_BANK0_TOG            HW(GPIOMON_ALT2_PINMUX_BANK0_TOG)
+#define HWA_GPIOMON_ALT2_PINMUX_BANK0_TOG           (HWA_GPIOMON_ALT2_PINMUX_BANK0 + 0xc)
+#define HWT_GPIOMON_ALT2_PINMUX_BANK0_TOG           HWIO_32_WO
+#define HWN_GPIOMON_ALT2_PINMUX_BANK0_TOG           GPIOMON_ALT2_PINMUX_BANK0
+#define HWI_GPIOMON_ALT2_PINMUX_BANK0_TOG           
+#define BP_GPIOMON_ALT2_PINMUX_BANK0_INDEX          0
+#define BM_GPIOMON_ALT2_PINMUX_BANK0_INDEX          0xffffffff
+#define BF_GPIOMON_ALT2_PINMUX_BANK0_INDEX(v)       (((v) & 0xffffffff) << 0)
+#define BFM_GPIOMON_ALT2_PINMUX_BANK0_INDEX(v)      BM_GPIOMON_ALT2_PINMUX_BANK0_INDEX
+#define BF_GPIOMON_ALT2_PINMUX_BANK0_INDEX_V(e)     BF_GPIOMON_ALT2_PINMUX_BANK0_INDEX(BV_GPIOMON_ALT2_PINMUX_BANK0_INDEX__##e)
+#define BFM_GPIOMON_ALT2_PINMUX_BANK0_INDEX_V(v)    BM_GPIOMON_ALT2_PINMUX_BANK0_INDEX
+
+#define HW_GPIOMON_ALT2_PINMUX_BANK1                HW(GPIOMON_ALT2_PINMUX_BANK1)
+#define HWA_GPIOMON_ALT2_PINMUX_BANK1               (0x8003c300 + 0x120)
+#define HWT_GPIOMON_ALT2_PINMUX_BANK1               HWIO_32_RW
+#define HWN_GPIOMON_ALT2_PINMUX_BANK1               GPIOMON_ALT2_PINMUX_BANK1
+#define HWI_GPIOMON_ALT2_PINMUX_BANK1               
+#define HW_GPIOMON_ALT2_PINMUX_BANK1_SET            HW(GPIOMON_ALT2_PINMUX_BANK1_SET)
+#define HWA_GPIOMON_ALT2_PINMUX_BANK1_SET           (HWA_GPIOMON_ALT2_PINMUX_BANK1 + 0x4)
+#define HWT_GPIOMON_ALT2_PINMUX_BANK1_SET           HWIO_32_WO
+#define HWN_GPIOMON_ALT2_PINMUX_BANK1_SET           GPIOMON_ALT2_PINMUX_BANK1
+#define HWI_GPIOMON_ALT2_PINMUX_BANK1_SET           
+#define HW_GPIOMON_ALT2_PINMUX_BANK1_CLR            HW(GPIOMON_ALT2_PINMUX_BANK1_CLR)
+#define HWA_GPIOMON_ALT2_PINMUX_BANK1_CLR           (HWA_GPIOMON_ALT2_PINMUX_BANK1 + 0x8)
+#define HWT_GPIOMON_ALT2_PINMUX_BANK1_CLR           HWIO_32_WO
+#define HWN_GPIOMON_ALT2_PINMUX_BANK1_CLR           GPIOMON_ALT2_PINMUX_BANK1
+#define HWI_GPIOMON_ALT2_PINMUX_BANK1_CLR           
+#define HW_GPIOMON_ALT2_PINMUX_BANK1_TOG            HW(GPIOMON_ALT2_PINMUX_BANK1_TOG)
+#define HWA_GPIOMON_ALT2_PINMUX_BANK1_TOG           (HWA_GPIOMON_ALT2_PINMUX_BANK1 + 0xc)
+#define HWT_GPIOMON_ALT2_PINMUX_BANK1_TOG           HWIO_32_WO
+#define HWN_GPIOMON_ALT2_PINMUX_BANK1_TOG           GPIOMON_ALT2_PINMUX_BANK1
+#define HWI_GPIOMON_ALT2_PINMUX_BANK1_TOG           
+#define BP_GPIOMON_ALT2_PINMUX_BANK1_INDEX          0
+#define BM_GPIOMON_ALT2_PINMUX_BANK1_INDEX          0xffffffff
+#define BF_GPIOMON_ALT2_PINMUX_BANK1_INDEX(v)       (((v) & 0xffffffff) << 0)
+#define BFM_GPIOMON_ALT2_PINMUX_BANK1_INDEX(v)      BM_GPIOMON_ALT2_PINMUX_BANK1_INDEX
+#define BF_GPIOMON_ALT2_PINMUX_BANK1_INDEX_V(e)     BF_GPIOMON_ALT2_PINMUX_BANK1_INDEX(BV_GPIOMON_ALT2_PINMUX_BANK1_INDEX__##e)
+#define BFM_GPIOMON_ALT2_PINMUX_BANK1_INDEX_V(v)    BM_GPIOMON_ALT2_PINMUX_BANK1_INDEX
+
+#define HW_GPIOMON_ALT2_PINMUX_BANK2                HW(GPIOMON_ALT2_PINMUX_BANK2)
+#define HWA_GPIOMON_ALT2_PINMUX_BANK2               (0x8003c300 + 0x130)
+#define HWT_GPIOMON_ALT2_PINMUX_BANK2               HWIO_32_RW
+#define HWN_GPIOMON_ALT2_PINMUX_BANK2               GPIOMON_ALT2_PINMUX_BANK2
+#define HWI_GPIOMON_ALT2_PINMUX_BANK2               
+#define HW_GPIOMON_ALT2_PINMUX_BANK2_SET            HW(GPIOMON_ALT2_PINMUX_BANK2_SET)
+#define HWA_GPIOMON_ALT2_PINMUX_BANK2_SET           (HWA_GPIOMON_ALT2_PINMUX_BANK2 + 0x4)
+#define HWT_GPIOMON_ALT2_PINMUX_BANK2_SET           HWIO_32_WO
+#define HWN_GPIOMON_ALT2_PINMUX_BANK2_SET           GPIOMON_ALT2_PINMUX_BANK2
+#define HWI_GPIOMON_ALT2_PINMUX_BANK2_SET           
+#define HW_GPIOMON_ALT2_PINMUX_BANK2_CLR            HW(GPIOMON_ALT2_PINMUX_BANK2_CLR)
+#define HWA_GPIOMON_ALT2_PINMUX_BANK2_CLR           (HWA_GPIOMON_ALT2_PINMUX_BANK2 + 0x8)
+#define HWT_GPIOMON_ALT2_PINMUX_BANK2_CLR           HWIO_32_WO
+#define HWN_GPIOMON_ALT2_PINMUX_BANK2_CLR           GPIOMON_ALT2_PINMUX_BANK2
+#define HWI_GPIOMON_ALT2_PINMUX_BANK2_CLR           
+#define HW_GPIOMON_ALT2_PINMUX_BANK2_TOG            HW(GPIOMON_ALT2_PINMUX_BANK2_TOG)
+#define HWA_GPIOMON_ALT2_PINMUX_BANK2_TOG           (HWA_GPIOMON_ALT2_PINMUX_BANK2 + 0xc)
+#define HWT_GPIOMON_ALT2_PINMUX_BANK2_TOG           HWIO_32_WO
+#define HWN_GPIOMON_ALT2_PINMUX_BANK2_TOG           GPIOMON_ALT2_PINMUX_BANK2
+#define HWI_GPIOMON_ALT2_PINMUX_BANK2_TOG           
+#define BP_GPIOMON_ALT2_PINMUX_BANK2_INDEX          0
+#define BM_GPIOMON_ALT2_PINMUX_BANK2_INDEX          0xffffffff
+#define BF_GPIOMON_ALT2_PINMUX_BANK2_INDEX(v)       (((v) & 0xffffffff) << 0)
+#define BFM_GPIOMON_ALT2_PINMUX_BANK2_INDEX(v)      BM_GPIOMON_ALT2_PINMUX_BANK2_INDEX
+#define BF_GPIOMON_ALT2_PINMUX_BANK2_INDEX_V(e)     BF_GPIOMON_ALT2_PINMUX_BANK2_INDEX(BV_GPIOMON_ALT2_PINMUX_BANK2_INDEX__##e)
+#define BFM_GPIOMON_ALT2_PINMUX_BANK2_INDEX_V(v)    BM_GPIOMON_ALT2_PINMUX_BANK2_INDEX
+
+#define HW_GPIOMON_ALT2_PINMUX_BANK3                HW(GPIOMON_ALT2_PINMUX_BANK3)
+#define HWA_GPIOMON_ALT2_PINMUX_BANK3               (0x8003c300 + 0x140)
+#define HWT_GPIOMON_ALT2_PINMUX_BANK3               HWIO_32_RW
+#define HWN_GPIOMON_ALT2_PINMUX_BANK3               GPIOMON_ALT2_PINMUX_BANK3
+#define HWI_GPIOMON_ALT2_PINMUX_BANK3               
+#define HW_GPIOMON_ALT2_PINMUX_BANK3_SET            HW(GPIOMON_ALT2_PINMUX_BANK3_SET)
+#define HWA_GPIOMON_ALT2_PINMUX_BANK3_SET           (HWA_GPIOMON_ALT2_PINMUX_BANK3 + 0x4)
+#define HWT_GPIOMON_ALT2_PINMUX_BANK3_SET           HWIO_32_WO
+#define HWN_GPIOMON_ALT2_PINMUX_BANK3_SET           GPIOMON_ALT2_PINMUX_BANK3
+#define HWI_GPIOMON_ALT2_PINMUX_BANK3_SET           
+#define HW_GPIOMON_ALT2_PINMUX_BANK3_CLR            HW(GPIOMON_ALT2_PINMUX_BANK3_CLR)
+#define HWA_GPIOMON_ALT2_PINMUX_BANK3_CLR           (HWA_GPIOMON_ALT2_PINMUX_BANK3 + 0x8)
+#define HWT_GPIOMON_ALT2_PINMUX_BANK3_CLR           HWIO_32_WO
+#define HWN_GPIOMON_ALT2_PINMUX_BANK3_CLR           GPIOMON_ALT2_PINMUX_BANK3
+#define HWI_GPIOMON_ALT2_PINMUX_BANK3_CLR           
+#define HW_GPIOMON_ALT2_PINMUX_BANK3_TOG            HW(GPIOMON_ALT2_PINMUX_BANK3_TOG)
+#define HWA_GPIOMON_ALT2_PINMUX_BANK3_TOG           (HWA_GPIOMON_ALT2_PINMUX_BANK3 + 0xc)
+#define HWT_GPIOMON_ALT2_PINMUX_BANK3_TOG           HWIO_32_WO
+#define HWN_GPIOMON_ALT2_PINMUX_BANK3_TOG           GPIOMON_ALT2_PINMUX_BANK3
+#define HWI_GPIOMON_ALT2_PINMUX_BANK3_TOG           
+#define BP_GPIOMON_ALT2_PINMUX_BANK3_INDEX          0
+#define BM_GPIOMON_ALT2_PINMUX_BANK3_INDEX          0xffffffff
+#define BF_GPIOMON_ALT2_PINMUX_BANK3_INDEX(v)       (((v) & 0xffffffff) << 0)
+#define BFM_GPIOMON_ALT2_PINMUX_BANK3_INDEX(v)      BM_GPIOMON_ALT2_PINMUX_BANK3_INDEX
+#define BF_GPIOMON_ALT2_PINMUX_BANK3_INDEX_V(e)     BF_GPIOMON_ALT2_PINMUX_BANK3_INDEX(BV_GPIOMON_ALT2_PINMUX_BANK3_INDEX__##e)
+#define BFM_GPIOMON_ALT2_PINMUX_BANK3_INDEX_V(v)    BM_GPIOMON_ALT2_PINMUX_BANK3_INDEX
+
+#define HW_GPIOMON_ALT3_PINMUX_BANK0                HW(GPIOMON_ALT3_PINMUX_BANK0)
+#define HWA_GPIOMON_ALT3_PINMUX_BANK0               (0x8003c300 + 0x150)
+#define HWT_GPIOMON_ALT3_PINMUX_BANK0               HWIO_32_RW
+#define HWN_GPIOMON_ALT3_PINMUX_BANK0               GPIOMON_ALT3_PINMUX_BANK0
+#define HWI_GPIOMON_ALT3_PINMUX_BANK0               
+#define HW_GPIOMON_ALT3_PINMUX_BANK0_SET            HW(GPIOMON_ALT3_PINMUX_BANK0_SET)
+#define HWA_GPIOMON_ALT3_PINMUX_BANK0_SET           (HWA_GPIOMON_ALT3_PINMUX_BANK0 + 0x4)
+#define HWT_GPIOMON_ALT3_PINMUX_BANK0_SET           HWIO_32_WO
+#define HWN_GPIOMON_ALT3_PINMUX_BANK0_SET           GPIOMON_ALT3_PINMUX_BANK0
+#define HWI_GPIOMON_ALT3_PINMUX_BANK0_SET           
+#define HW_GPIOMON_ALT3_PINMUX_BANK0_CLR            HW(GPIOMON_ALT3_PINMUX_BANK0_CLR)
+#define HWA_GPIOMON_ALT3_PINMUX_BANK0_CLR           (HWA_GPIOMON_ALT3_PINMUX_BANK0 + 0x8)
+#define HWT_GPIOMON_ALT3_PINMUX_BANK0_CLR           HWIO_32_WO
+#define HWN_GPIOMON_ALT3_PINMUX_BANK0_CLR           GPIOMON_ALT3_PINMUX_BANK0
+#define HWI_GPIOMON_ALT3_PINMUX_BANK0_CLR           
+#define HW_GPIOMON_ALT3_PINMUX_BANK0_TOG            HW(GPIOMON_ALT3_PINMUX_BANK0_TOG)
+#define HWA_GPIOMON_ALT3_PINMUX_BANK0_TOG           (HWA_GPIOMON_ALT3_PINMUX_BANK0 + 0xc)
+#define HWT_GPIOMON_ALT3_PINMUX_BANK0_TOG           HWIO_32_WO
+#define HWN_GPIOMON_ALT3_PINMUX_BANK0_TOG           GPIOMON_ALT3_PINMUX_BANK0
+#define HWI_GPIOMON_ALT3_PINMUX_BANK0_TOG           
+#define BP_GPIOMON_ALT3_PINMUX_BANK0_INDEX          0
+#define BM_GPIOMON_ALT3_PINMUX_BANK0_INDEX          0xffffffff
+#define BF_GPIOMON_ALT3_PINMUX_BANK0_INDEX(v)       (((v) & 0xffffffff) << 0)
+#define BFM_GPIOMON_ALT3_PINMUX_BANK0_INDEX(v)      BM_GPIOMON_ALT3_PINMUX_BANK0_INDEX
+#define BF_GPIOMON_ALT3_PINMUX_BANK0_INDEX_V(e)     BF_GPIOMON_ALT3_PINMUX_BANK0_INDEX(BV_GPIOMON_ALT3_PINMUX_BANK0_INDEX__##e)
+#define BFM_GPIOMON_ALT3_PINMUX_BANK0_INDEX_V(v)    BM_GPIOMON_ALT3_PINMUX_BANK0_INDEX
+
+#define HW_GPIOMON_ALT3_PINMUX_BANK1                HW(GPIOMON_ALT3_PINMUX_BANK1)
+#define HWA_GPIOMON_ALT3_PINMUX_BANK1               (0x8003c300 + 0x160)
+#define HWT_GPIOMON_ALT3_PINMUX_BANK1               HWIO_32_RW
+#define HWN_GPIOMON_ALT3_PINMUX_BANK1               GPIOMON_ALT3_PINMUX_BANK1
+#define HWI_GPIOMON_ALT3_PINMUX_BANK1               
+#define HW_GPIOMON_ALT3_PINMUX_BANK1_SET            HW(GPIOMON_ALT3_PINMUX_BANK1_SET)
+#define HWA_GPIOMON_ALT3_PINMUX_BANK1_SET           (HWA_GPIOMON_ALT3_PINMUX_BANK1 + 0x4)
+#define HWT_GPIOMON_ALT3_PINMUX_BANK1_SET           HWIO_32_WO
+#define HWN_GPIOMON_ALT3_PINMUX_BANK1_SET           GPIOMON_ALT3_PINMUX_BANK1
+#define HWI_GPIOMON_ALT3_PINMUX_BANK1_SET           
+#define HW_GPIOMON_ALT3_PINMUX_BANK1_CLR            HW(GPIOMON_ALT3_PINMUX_BANK1_CLR)
+#define HWA_GPIOMON_ALT3_PINMUX_BANK1_CLR           (HWA_GPIOMON_ALT3_PINMUX_BANK1 + 0x8)
+#define HWT_GPIOMON_ALT3_PINMUX_BANK1_CLR           HWIO_32_WO
+#define HWN_GPIOMON_ALT3_PINMUX_BANK1_CLR           GPIOMON_ALT3_PINMUX_BANK1
+#define HWI_GPIOMON_ALT3_PINMUX_BANK1_CLR           
+#define HW_GPIOMON_ALT3_PINMUX_BANK1_TOG            HW(GPIOMON_ALT3_PINMUX_BANK1_TOG)
+#define HWA_GPIOMON_ALT3_PINMUX_BANK1_TOG           (HWA_GPIOMON_ALT3_PINMUX_BANK1 + 0xc)
+#define HWT_GPIOMON_ALT3_PINMUX_BANK1_TOG           HWIO_32_WO
+#define HWN_GPIOMON_ALT3_PINMUX_BANK1_TOG           GPIOMON_ALT3_PINMUX_BANK1
+#define HWI_GPIOMON_ALT3_PINMUX_BANK1_TOG           
+#define BP_GPIOMON_ALT3_PINMUX_BANK1_INDEX          0
+#define BM_GPIOMON_ALT3_PINMUX_BANK1_INDEX          0xffffffff
+#define BF_GPIOMON_ALT3_PINMUX_BANK1_INDEX(v)       (((v) & 0xffffffff) << 0)
+#define BFM_GPIOMON_ALT3_PINMUX_BANK1_INDEX(v)      BM_GPIOMON_ALT3_PINMUX_BANK1_INDEX
+#define BF_GPIOMON_ALT3_PINMUX_BANK1_INDEX_V(e)     BF_GPIOMON_ALT3_PINMUX_BANK1_INDEX(BV_GPIOMON_ALT3_PINMUX_BANK1_INDEX__##e)
+#define BFM_GPIOMON_ALT3_PINMUX_BANK1_INDEX_V(v)    BM_GPIOMON_ALT3_PINMUX_BANK1_INDEX
+
+#define HW_GPIOMON_ALT3_PINMUX_BANK2                HW(GPIOMON_ALT3_PINMUX_BANK2)
+#define HWA_GPIOMON_ALT3_PINMUX_BANK2               (0x8003c300 + 0x170)
+#define HWT_GPIOMON_ALT3_PINMUX_BANK2               HWIO_32_RW
+#define HWN_GPIOMON_ALT3_PINMUX_BANK2               GPIOMON_ALT3_PINMUX_BANK2
+#define HWI_GPIOMON_ALT3_PINMUX_BANK2               
+#define HW_GPIOMON_ALT3_PINMUX_BANK2_SET            HW(GPIOMON_ALT3_PINMUX_BANK2_SET)
+#define HWA_GPIOMON_ALT3_PINMUX_BANK2_SET           (HWA_GPIOMON_ALT3_PINMUX_BANK2 + 0x4)
+#define HWT_GPIOMON_ALT3_PINMUX_BANK2_SET           HWIO_32_WO
+#define HWN_GPIOMON_ALT3_PINMUX_BANK2_SET           GPIOMON_ALT3_PINMUX_BANK2
+#define HWI_GPIOMON_ALT3_PINMUX_BANK2_SET           
+#define HW_GPIOMON_ALT3_PINMUX_BANK2_CLR            HW(GPIOMON_ALT3_PINMUX_BANK2_CLR)
+#define HWA_GPIOMON_ALT3_PINMUX_BANK2_CLR           (HWA_GPIOMON_ALT3_PINMUX_BANK2 + 0x8)
+#define HWT_GPIOMON_ALT3_PINMUX_BANK2_CLR           HWIO_32_WO
+#define HWN_GPIOMON_ALT3_PINMUX_BANK2_CLR           GPIOMON_ALT3_PINMUX_BANK2
+#define HWI_GPIOMON_ALT3_PINMUX_BANK2_CLR           
+#define HW_GPIOMON_ALT3_PINMUX_BANK2_TOG            HW(GPIOMON_ALT3_PINMUX_BANK2_TOG)
+#define HWA_GPIOMON_ALT3_PINMUX_BANK2_TOG           (HWA_GPIOMON_ALT3_PINMUX_BANK2 + 0xc)
+#define HWT_GPIOMON_ALT3_PINMUX_BANK2_TOG           HWIO_32_WO
+#define HWN_GPIOMON_ALT3_PINMUX_BANK2_TOG           GPIOMON_ALT3_PINMUX_BANK2
+#define HWI_GPIOMON_ALT3_PINMUX_BANK2_TOG           
+#define BP_GPIOMON_ALT3_PINMUX_BANK2_INDEX          0
+#define BM_GPIOMON_ALT3_PINMUX_BANK2_INDEX          0xffffffff
+#define BF_GPIOMON_ALT3_PINMUX_BANK2_INDEX(v)       (((v) & 0xffffffff) << 0)
+#define BFM_GPIOMON_ALT3_PINMUX_BANK2_INDEX(v)      BM_GPIOMON_ALT3_PINMUX_BANK2_INDEX
+#define BF_GPIOMON_ALT3_PINMUX_BANK2_INDEX_V(e)     BF_GPIOMON_ALT3_PINMUX_BANK2_INDEX(BV_GPIOMON_ALT3_PINMUX_BANK2_INDEX__##e)
+#define BFM_GPIOMON_ALT3_PINMUX_BANK2_INDEX_V(v)    BM_GPIOMON_ALT3_PINMUX_BANK2_INDEX
+
+#define HW_GPIOMON_ALT3_PINMUX_BANK3                HW(GPIOMON_ALT3_PINMUX_BANK3)
+#define HWA_GPIOMON_ALT3_PINMUX_BANK3               (0x8003c300 + 0x180)
+#define HWT_GPIOMON_ALT3_PINMUX_BANK3               HWIO_32_RW
+#define HWN_GPIOMON_ALT3_PINMUX_BANK3               GPIOMON_ALT3_PINMUX_BANK3
+#define HWI_GPIOMON_ALT3_PINMUX_BANK3               
+#define HW_GPIOMON_ALT3_PINMUX_BANK3_SET            HW(GPIOMON_ALT3_PINMUX_BANK3_SET)
+#define HWA_GPIOMON_ALT3_PINMUX_BANK3_SET           (HWA_GPIOMON_ALT3_PINMUX_BANK3 + 0x4)
+#define HWT_GPIOMON_ALT3_PINMUX_BANK3_SET           HWIO_32_WO
+#define HWN_GPIOMON_ALT3_PINMUX_BANK3_SET           GPIOMON_ALT3_PINMUX_BANK3
+#define HWI_GPIOMON_ALT3_PINMUX_BANK3_SET           
+#define HW_GPIOMON_ALT3_PINMUX_BANK3_CLR            HW(GPIOMON_ALT3_PINMUX_BANK3_CLR)
+#define HWA_GPIOMON_ALT3_PINMUX_BANK3_CLR           (HWA_GPIOMON_ALT3_PINMUX_BANK3 + 0x8)
+#define HWT_GPIOMON_ALT3_PINMUX_BANK3_CLR           HWIO_32_WO
+#define HWN_GPIOMON_ALT3_PINMUX_BANK3_CLR           GPIOMON_ALT3_PINMUX_BANK3
+#define HWI_GPIOMON_ALT3_PINMUX_BANK3_CLR           
+#define HW_GPIOMON_ALT3_PINMUX_BANK3_TOG            HW(GPIOMON_ALT3_PINMUX_BANK3_TOG)
+#define HWA_GPIOMON_ALT3_PINMUX_BANK3_TOG           (HWA_GPIOMON_ALT3_PINMUX_BANK3 + 0xc)
+#define HWT_GPIOMON_ALT3_PINMUX_BANK3_TOG           HWIO_32_WO
+#define HWN_GPIOMON_ALT3_PINMUX_BANK3_TOG           GPIOMON_ALT3_PINMUX_BANK3
+#define HWI_GPIOMON_ALT3_PINMUX_BANK3_TOG           
+#define BP_GPIOMON_ALT3_PINMUX_BANK3_INDEX          0
+#define BM_GPIOMON_ALT3_PINMUX_BANK3_INDEX          0xffffffff
+#define BF_GPIOMON_ALT3_PINMUX_BANK3_INDEX(v)       (((v) & 0xffffffff) << 0)
+#define BFM_GPIOMON_ALT3_PINMUX_BANK3_INDEX(v)      BM_GPIOMON_ALT3_PINMUX_BANK3_INDEX
+#define BF_GPIOMON_ALT3_PINMUX_BANK3_INDEX_V(e)     BF_GPIOMON_ALT3_PINMUX_BANK3_INDEX(BV_GPIOMON_ALT3_PINMUX_BANK3_INDEX__##e)
+#define BFM_GPIOMON_ALT3_PINMUX_BANK3_INDEX_V(v)    BM_GPIOMON_ALT3_PINMUX_BANK3_INDEX
+
+#endif /* __HEADERGEN_STMP3700_GPIOMON_H__*/
diff --git a/firmware/target/arm/imx233/regs/stmp3700/gpmi.h b/firmware/target/arm/imx233/regs/stmp3700/gpmi.h
new file mode 100644
index 0000000000..97dd54722d
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3700/gpmi.h
@@ -0,0 +1,693 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * stmp3700 version: 2.4.0
+ * stmp3700 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_STMP3700_GPMI_H__
+#define __HEADERGEN_STMP3700_GPMI_H__
+
+#define HW_GPMI_CTRL0                                   HW(GPMI_CTRL0)
+#define HWA_GPMI_CTRL0                                  (0x8000c000 + 0x0)
+#define HWT_GPMI_CTRL0                                  HWIO_32_RW
+#define HWN_GPMI_CTRL0                                  GPMI_CTRL0
+#define HWI_GPMI_CTRL0                                  
+#define HW_GPMI_CTRL0_SET                               HW(GPMI_CTRL0_SET)
+#define HWA_GPMI_CTRL0_SET                              (HWA_GPMI_CTRL0 + 0x4)
+#define HWT_GPMI_CTRL0_SET                              HWIO_32_WO
+#define HWN_GPMI_CTRL0_SET                              GPMI_CTRL0
+#define HWI_GPMI_CTRL0_SET                              
+#define HW_GPMI_CTRL0_CLR                               HW(GPMI_CTRL0_CLR)
+#define HWA_GPMI_CTRL0_CLR                              (HWA_GPMI_CTRL0 + 0x8)
+#define HWT_GPMI_CTRL0_CLR                              HWIO_32_WO
+#define HWN_GPMI_CTRL0_CLR                              GPMI_CTRL0
+#define HWI_GPMI_CTRL0_CLR                              
+#define HW_GPMI_CTRL0_TOG                               HW(GPMI_CTRL0_TOG)
+#define HWA_GPMI_CTRL0_TOG                              (HWA_GPMI_CTRL0 + 0xc)
+#define HWT_GPMI_CTRL0_TOG                              HWIO_32_WO
+#define HWN_GPMI_CTRL0_TOG                              GPMI_CTRL0
+#define HWI_GPMI_CTRL0_TOG                              
+#define BP_GPMI_CTRL0_SFTRST                            31
+#define BM_GPMI_CTRL0_SFTRST                            0x80000000
+#define BV_GPMI_CTRL0_SFTRST__RUN                       0x0
+#define BV_GPMI_CTRL0_SFTRST__RESET                     0x1
+#define BF_GPMI_CTRL0_SFTRST(v)                         (((v) & 0x1) << 31)
+#define BFM_GPMI_CTRL0_SFTRST(v)                        BM_GPMI_CTRL0_SFTRST
+#define BF_GPMI_CTRL0_SFTRST_V(e)                       BF_GPMI_CTRL0_SFTRST(BV_GPMI_CTRL0_SFTRST__##e)
+#define BFM_GPMI_CTRL0_SFTRST_V(v)                      BM_GPMI_CTRL0_SFTRST
+#define BP_GPMI_CTRL0_CLKGATE                           30
+#define BM_GPMI_CTRL0_CLKGATE                           0x40000000
+#define BV_GPMI_CTRL0_CLKGATE__RUN                      0x0
+#define BV_GPMI_CTRL0_CLKGATE__NO_CLKS                  0x1
+#define BF_GPMI_CTRL0_CLKGATE(v)                        (((v) & 0x1) << 30)
+#define BFM_GPMI_CTRL0_CLKGATE(v)                       BM_GPMI_CTRL0_CLKGATE
+#define BF_GPMI_CTRL0_CLKGATE_V(e)                      BF_GPMI_CTRL0_CLKGATE(BV_GPMI_CTRL0_CLKGATE__##e)
+#define BFM_GPMI_CTRL0_CLKGATE_V(v)                     BM_GPMI_CTRL0_CLKGATE
+#define BP_GPMI_CTRL0_RUN                               29
+#define BM_GPMI_CTRL0_RUN                               0x20000000
+#define BV_GPMI_CTRL0_RUN__IDLE                         0x0
+#define BV_GPMI_CTRL0_RUN__BUSY                         0x1
+#define BF_GPMI_CTRL0_RUN(v)                            (((v) & 0x1) << 29)
+#define BFM_GPMI_CTRL0_RUN(v)                           BM_GPMI_CTRL0_RUN
+#define BF_GPMI_CTRL0_RUN_V(e)                          BF_GPMI_CTRL0_RUN(BV_GPMI_CTRL0_RUN__##e)
+#define BFM_GPMI_CTRL0_RUN_V(v)                         BM_GPMI_CTRL0_RUN
+#define BP_GPMI_CTRL0_DEV_IRQ_EN                        28
+#define BM_GPMI_CTRL0_DEV_IRQ_EN                        0x10000000
+#define BF_GPMI_CTRL0_DEV_IRQ_EN(v)                     (((v) & 0x1) << 28)
+#define BFM_GPMI_CTRL0_DEV_IRQ_EN(v)                    BM_GPMI_CTRL0_DEV_IRQ_EN
+#define BF_GPMI_CTRL0_DEV_IRQ_EN_V(e)                   BF_GPMI_CTRL0_DEV_IRQ_EN(BV_GPMI_CTRL0_DEV_IRQ_EN__##e)
+#define BFM_GPMI_CTRL0_DEV_IRQ_EN_V(v)                  BM_GPMI_CTRL0_DEV_IRQ_EN
+#define BP_GPMI_CTRL0_TIMEOUT_IRQ_EN                    27
+#define BM_GPMI_CTRL0_TIMEOUT_IRQ_EN                    0x8000000
+#define BF_GPMI_CTRL0_TIMEOUT_IRQ_EN(v)                 (((v) & 0x1) << 27)
+#define BFM_GPMI_CTRL0_TIMEOUT_IRQ_EN(v)                BM_GPMI_CTRL0_TIMEOUT_IRQ_EN
+#define BF_GPMI_CTRL0_TIMEOUT_IRQ_EN_V(e)               BF_GPMI_CTRL0_TIMEOUT_IRQ_EN(BV_GPMI_CTRL0_TIMEOUT_IRQ_EN__##e)
+#define BFM_GPMI_CTRL0_TIMEOUT_IRQ_EN_V(v)              BM_GPMI_CTRL0_TIMEOUT_IRQ_EN
+#define BP_GPMI_CTRL0_UDMA                              26
+#define BM_GPMI_CTRL0_UDMA                              0x4000000
+#define BV_GPMI_CTRL0_UDMA__DISABLED                    0x0
+#define BV_GPMI_CTRL0_UDMA__ENABLED                     0x1
+#define BF_GPMI_CTRL0_UDMA(v)                           (((v) & 0x1) << 26)
+#define BFM_GPMI_CTRL0_UDMA(v)                          BM_GPMI_CTRL0_UDMA
+#define BF_GPMI_CTRL0_UDMA_V(e)                         BF_GPMI_CTRL0_UDMA(BV_GPMI_CTRL0_UDMA__##e)
+#define BFM_GPMI_CTRL0_UDMA_V(v)                        BM_GPMI_CTRL0_UDMA
+#define BP_GPMI_CTRL0_COMMAND_MODE                      24
+#define BM_GPMI_CTRL0_COMMAND_MODE                      0x3000000
+#define BV_GPMI_CTRL0_COMMAND_MODE__WRITE               0x0
+#define BV_GPMI_CTRL0_COMMAND_MODE__READ                0x1
+#define BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE    0x2
+#define BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY      0x3
+#define BF_GPMI_CTRL0_COMMAND_MODE(v)                   (((v) & 0x3) << 24)
+#define BFM_GPMI_CTRL0_COMMAND_MODE(v)                  BM_GPMI_CTRL0_COMMAND_MODE
+#define BF_GPMI_CTRL0_COMMAND_MODE_V(e)                 BF_GPMI_CTRL0_COMMAND_MODE(BV_GPMI_CTRL0_COMMAND_MODE__##e)
+#define BFM_GPMI_CTRL0_COMMAND_MODE_V(v)                BM_GPMI_CTRL0_COMMAND_MODE
+#define BP_GPMI_CTRL0_WORD_LENGTH                       23
+#define BM_GPMI_CTRL0_WORD_LENGTH                       0x800000
+#define BV_GPMI_CTRL0_WORD_LENGTH__16_BIT               0x0
+#define BV_GPMI_CTRL0_WORD_LENGTH__8_BIT                0x1
+#define BF_GPMI_CTRL0_WORD_LENGTH(v)                    (((v) & 0x1) << 23)
+#define BFM_GPMI_CTRL0_WORD_LENGTH(v)                   BM_GPMI_CTRL0_WORD_LENGTH
+#define BF_GPMI_CTRL0_WORD_LENGTH_V(e)                  BF_GPMI_CTRL0_WORD_LENGTH(BV_GPMI_CTRL0_WORD_LENGTH__##e)
+#define BFM_GPMI_CTRL0_WORD_LENGTH_V(v)                 BM_GPMI_CTRL0_WORD_LENGTH
+#define BP_GPMI_CTRL0_LOCK_CS                           22
+#define BM_GPMI_CTRL0_LOCK_CS                           0x400000
+#define BV_GPMI_CTRL0_LOCK_CS__DISABLED                 0x0
+#define BV_GPMI_CTRL0_LOCK_CS__ENABLED                  0x1
+#define BF_GPMI_CTRL0_LOCK_CS(v)                        (((v) & 0x1) << 22)
+#define BFM_GPMI_CTRL0_LOCK_CS(v)                       BM_GPMI_CTRL0_LOCK_CS
+#define BF_GPMI_CTRL0_LOCK_CS_V(e)                      BF_GPMI_CTRL0_LOCK_CS(BV_GPMI_CTRL0_LOCK_CS__##e)
+#define BFM_GPMI_CTRL0_LOCK_CS_V(v)                     BM_GPMI_CTRL0_LOCK_CS
+#define BP_GPMI_CTRL0_CS                                20
+#define BM_GPMI_CTRL0_CS                                0x300000
+#define BF_GPMI_CTRL0_CS(v)                             (((v) & 0x3) << 20)
+#define BFM_GPMI_CTRL0_CS(v)                            BM_GPMI_CTRL0_CS
+#define BF_GPMI_CTRL0_CS_V(e)                           BF_GPMI_CTRL0_CS(BV_GPMI_CTRL0_CS__##e)
+#define BFM_GPMI_CTRL0_CS_V(v)                          BM_GPMI_CTRL0_CS
+#define BP_GPMI_CTRL0_ADDRESS                           17
+#define BM_GPMI_CTRL0_ADDRESS                           0xe0000
+#define BV_GPMI_CTRL0_ADDRESS__NAND_DATA                0x0
+#define BV_GPMI_CTRL0_ADDRESS__NAND_CLE                 0x1
+#define BV_GPMI_CTRL0_ADDRESS__NAND_ALE                 0x2
+#define BF_GPMI_CTRL0_ADDRESS(v)                        (((v) & 0x7) << 17)
+#define BFM_GPMI_CTRL0_ADDRESS(v)                       BM_GPMI_CTRL0_ADDRESS
+#define BF_GPMI_CTRL0_ADDRESS_V(e)                      BF_GPMI_CTRL0_ADDRESS(BV_GPMI_CTRL0_ADDRESS__##e)
+#define BFM_GPMI_CTRL0_ADDRESS_V(v)                     BM_GPMI_CTRL0_ADDRESS
+#define BP_GPMI_CTRL0_ADDRESS_INCREMENT                 16
+#define BM_GPMI_CTRL0_ADDRESS_INCREMENT                 0x10000
+#define BV_GPMI_CTRL0_ADDRESS_INCREMENT__DISABLED       0x0
+#define BV_GPMI_CTRL0_ADDRESS_INCREMENT__ENABLED        0x1
+#define BF_GPMI_CTRL0_ADDRESS_INCREMENT(v)              (((v) & 0x1) << 16)
+#define BFM_GPMI_CTRL0_ADDRESS_INCREMENT(v)             BM_GPMI_CTRL0_ADDRESS_INCREMENT
+#define BF_GPMI_CTRL0_ADDRESS_INCREMENT_V(e)            BF_GPMI_CTRL0_ADDRESS_INCREMENT(BV_GPMI_CTRL0_ADDRESS_INCREMENT__##e)
+#define BFM_GPMI_CTRL0_ADDRESS_INCREMENT_V(v)           BM_GPMI_CTRL0_ADDRESS_INCREMENT
+#define BP_GPMI_CTRL0_XFER_COUNT                        0
+#define BM_GPMI_CTRL0_XFER_COUNT                        0xffff
+#define BF_GPMI_CTRL0_XFER_COUNT(v)                     (((v) & 0xffff) << 0)
+#define BFM_GPMI_CTRL0_XFER_COUNT(v)                    BM_GPMI_CTRL0_XFER_COUNT
+#define BF_GPMI_CTRL0_XFER_COUNT_V(e)                   BF_GPMI_CTRL0_XFER_COUNT(BV_GPMI_CTRL0_XFER_COUNT__##e)
+#define BFM_GPMI_CTRL0_XFER_COUNT_V(v)                  BM_GPMI_CTRL0_XFER_COUNT
+
+#define HW_GPMI_COMPARE                 HW(GPMI_COMPARE)
+#define HWA_GPMI_COMPARE                (0x8000c000 + 0x10)
+#define HWT_GPMI_COMPARE                HWIO_32_RW
+#define HWN_GPMI_COMPARE                GPMI_COMPARE
+#define HWI_GPMI_COMPARE                
+#define BP_GPMI_COMPARE_MASK            16
+#define BM_GPMI_COMPARE_MASK            0xffff0000
+#define BF_GPMI_COMPARE_MASK(v)         (((v) & 0xffff) << 16)
+#define BFM_GPMI_COMPARE_MASK(v)        BM_GPMI_COMPARE_MASK
+#define BF_GPMI_COMPARE_MASK_V(e)       BF_GPMI_COMPARE_MASK(BV_GPMI_COMPARE_MASK__##e)
+#define BFM_GPMI_COMPARE_MASK_V(v)      BM_GPMI_COMPARE_MASK
+#define BP_GPMI_COMPARE_REFERENCE       0
+#define BM_GPMI_COMPARE_REFERENCE       0xffff
+#define BF_GPMI_COMPARE_REFERENCE(v)    (((v) & 0xffff) << 0)
+#define BFM_GPMI_COMPARE_REFERENCE(v)   BM_GPMI_COMPARE_REFERENCE
+#define BF_GPMI_COMPARE_REFERENCE_V(e)  BF_GPMI_COMPARE_REFERENCE(BV_GPMI_COMPARE_REFERENCE__##e)
+#define BFM_GPMI_COMPARE_REFERENCE_V(v) BM_GPMI_COMPARE_REFERENCE
+
+#define HW_GPMI_ECCCTRL                         HW(GPMI_ECCCTRL)
+#define HWA_GPMI_ECCCTRL                        (0x8000c000 + 0x20)
+#define HWT_GPMI_ECCCTRL                        HWIO_32_RW
+#define HWN_GPMI_ECCCTRL                        GPMI_ECCCTRL
+#define HWI_GPMI_ECCCTRL                        
+#define HW_GPMI_ECCCTRL_SET                     HW(GPMI_ECCCTRL_SET)
+#define HWA_GPMI_ECCCTRL_SET                    (HWA_GPMI_ECCCTRL + 0x4)
+#define HWT_GPMI_ECCCTRL_SET                    HWIO_32_WO
+#define HWN_GPMI_ECCCTRL_SET                    GPMI_ECCCTRL
+#define HWI_GPMI_ECCCTRL_SET                    
+#define HW_GPMI_ECCCTRL_CLR                     HW(GPMI_ECCCTRL_CLR)
+#define HWA_GPMI_ECCCTRL_CLR                    (HWA_GPMI_ECCCTRL + 0x8)
+#define HWT_GPMI_ECCCTRL_CLR                    HWIO_32_WO
+#define HWN_GPMI_ECCCTRL_CLR                    GPMI_ECCCTRL
+#define HWI_GPMI_ECCCTRL_CLR                    
+#define HW_GPMI_ECCCTRL_TOG                     HW(GPMI_ECCCTRL_TOG)
+#define HWA_GPMI_ECCCTRL_TOG                    (HWA_GPMI_ECCCTRL + 0xc)
+#define HWT_GPMI_ECCCTRL_TOG                    HWIO_32_WO
+#define HWN_GPMI_ECCCTRL_TOG                    GPMI_ECCCTRL
+#define HWI_GPMI_ECCCTRL_TOG                    
+#define BP_GPMI_ECCCTRL_HANDLE                  16
+#define BM_GPMI_ECCCTRL_HANDLE                  0xffff0000
+#define BF_GPMI_ECCCTRL_HANDLE(v)               (((v) & 0xffff) << 16)
+#define BFM_GPMI_ECCCTRL_HANDLE(v)              BM_GPMI_ECCCTRL_HANDLE
+#define BF_GPMI_ECCCTRL_HANDLE_V(e)             BF_GPMI_ECCCTRL_HANDLE(BV_GPMI_ECCCTRL_HANDLE__##e)
+#define BFM_GPMI_ECCCTRL_HANDLE_V(v)            BM_GPMI_ECCCTRL_HANDLE
+#define BP_GPMI_ECCCTRL_ECC_CMD                 13
+#define BM_GPMI_ECCCTRL_ECC_CMD                 0x6000
+#define BV_GPMI_ECCCTRL_ECC_CMD__DECODE_4_BIT   0x0
+#define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE_4_BIT   0x1
+#define BV_GPMI_ECCCTRL_ECC_CMD__DECODE_8_BIT   0x2
+#define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE_8_BIT   0x3
+#define BF_GPMI_ECCCTRL_ECC_CMD(v)              (((v) & 0x3) << 13)
+#define BFM_GPMI_ECCCTRL_ECC_CMD(v)             BM_GPMI_ECCCTRL_ECC_CMD
+#define BF_GPMI_ECCCTRL_ECC_CMD_V(e)            BF_GPMI_ECCCTRL_ECC_CMD(BV_GPMI_ECCCTRL_ECC_CMD__##e)
+#define BFM_GPMI_ECCCTRL_ECC_CMD_V(v)           BM_GPMI_ECCCTRL_ECC_CMD
+#define BP_GPMI_ECCCTRL_ENABLE_ECC              12
+#define BM_GPMI_ECCCTRL_ENABLE_ECC              0x1000
+#define BV_GPMI_ECCCTRL_ENABLE_ECC__ENABLE      0x1
+#define BV_GPMI_ECCCTRL_ENABLE_ECC__DISABLE     0x0
+#define BF_GPMI_ECCCTRL_ENABLE_ECC(v)           (((v) & 0x1) << 12)
+#define BFM_GPMI_ECCCTRL_ENABLE_ECC(v)          BM_GPMI_ECCCTRL_ENABLE_ECC
+#define BF_GPMI_ECCCTRL_ENABLE_ECC_V(e)         BF_GPMI_ECCCTRL_ENABLE_ECC(BV_GPMI_ECCCTRL_ENABLE_ECC__##e)
+#define BFM_GPMI_ECCCTRL_ENABLE_ECC_V(v)        BM_GPMI_ECCCTRL_ENABLE_ECC
+#define BP_GPMI_ECCCTRL_BUFFER_MASK             0
+#define BM_GPMI_ECCCTRL_BUFFER_MASK             0x1ff
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__AUXILIARY  0x100
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER7    0x80
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER6    0x40
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER5    0x20
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER4    0x10
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER3    0x8
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER2    0x4
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER1    0x2
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER0    0x1
+#define BF_GPMI_ECCCTRL_BUFFER_MASK(v)          (((v) & 0x1ff) << 0)
+#define BFM_GPMI_ECCCTRL_BUFFER_MASK(v)         BM_GPMI_ECCCTRL_BUFFER_MASK
+#define BF_GPMI_ECCCTRL_BUFFER_MASK_V(e)        BF_GPMI_ECCCTRL_BUFFER_MASK(BV_GPMI_ECCCTRL_BUFFER_MASK__##e)
+#define BFM_GPMI_ECCCTRL_BUFFER_MASK_V(v)       BM_GPMI_ECCCTRL_BUFFER_MASK
+
+#define HW_GPMI_ECCCOUNT                HW(GPMI_ECCCOUNT)
+#define HWA_GPMI_ECCCOUNT               (0x8000c000 + 0x30)
+#define HWT_GPMI_ECCCOUNT               HWIO_32_RW
+#define HWN_GPMI_ECCCOUNT               GPMI_ECCCOUNT
+#define HWI_GPMI_ECCCOUNT               
+#define BP_GPMI_ECCCOUNT_COUNT          0
+#define BM_GPMI_ECCCOUNT_COUNT          0xffff
+#define BF_GPMI_ECCCOUNT_COUNT(v)       (((v) & 0xffff) << 0)
+#define BFM_GPMI_ECCCOUNT_COUNT(v)      BM_GPMI_ECCCOUNT_COUNT
+#define BF_GPMI_ECCCOUNT_COUNT_V(e)     BF_GPMI_ECCCOUNT_COUNT(BV_GPMI_ECCCOUNT_COUNT__##e)
+#define BFM_GPMI_ECCCOUNT_COUNT_V(v)    BM_GPMI_ECCCOUNT_COUNT
+
+#define HW_GPMI_PAYLOAD                 HW(GPMI_PAYLOAD)
+#define HWA_GPMI_PAYLOAD                (0x8000c000 + 0x40)
+#define HWT_GPMI_PAYLOAD                HWIO_32_RW
+#define HWN_GPMI_PAYLOAD                GPMI_PAYLOAD
+#define HWI_GPMI_PAYLOAD                
+#define BP_GPMI_PAYLOAD_ADDRESS         2
+#define BM_GPMI_PAYLOAD_ADDRESS         0xfffffffc
+#define BF_GPMI_PAYLOAD_ADDRESS(v)      (((v) & 0x3fffffff) << 2)
+#define BFM_GPMI_PAYLOAD_ADDRESS(v)     BM_GPMI_PAYLOAD_ADDRESS
+#define BF_GPMI_PAYLOAD_ADDRESS_V(e)    BF_GPMI_PAYLOAD_ADDRESS(BV_GPMI_PAYLOAD_ADDRESS__##e)
+#define BFM_GPMI_PAYLOAD_ADDRESS_V(v)   BM_GPMI_PAYLOAD_ADDRESS
+
+#define HW_GPMI_AUXILIARY               HW(GPMI_AUXILIARY)
+#define HWA_GPMI_AUXILIARY              (0x8000c000 + 0x50)
+#define HWT_GPMI_AUXILIARY              HWIO_32_RW
+#define HWN_GPMI_AUXILIARY              GPMI_AUXILIARY
+#define HWI_GPMI_AUXILIARY              
+#define BP_GPMI_AUXILIARY_ADDRESS       2
+#define BM_GPMI_AUXILIARY_ADDRESS       0xfffffffc
+#define BF_GPMI_AUXILIARY_ADDRESS(v)    (((v) & 0x3fffffff) << 2)
+#define BFM_GPMI_AUXILIARY_ADDRESS(v)   BM_GPMI_AUXILIARY_ADDRESS
+#define BF_GPMI_AUXILIARY_ADDRESS_V(e)  BF_GPMI_AUXILIARY_ADDRESS(BV_GPMI_AUXILIARY_ADDRESS__##e)
+#define BFM_GPMI_AUXILIARY_ADDRESS_V(v) BM_GPMI_AUXILIARY_ADDRESS
+
+#define HW_GPMI_CTRL1                                   HW(GPMI_CTRL1)
+#define HWA_GPMI_CTRL1                                  (0x8000c000 + 0x60)
+#define HWT_GPMI_CTRL1                                  HWIO_32_RW
+#define HWN_GPMI_CTRL1                                  GPMI_CTRL1
+#define HWI_GPMI_CTRL1                                  
+#define HW_GPMI_CTRL1_SET                               HW(GPMI_CTRL1_SET)
+#define HWA_GPMI_CTRL1_SET                              (HWA_GPMI_CTRL1 + 0x4)
+#define HWT_GPMI_CTRL1_SET                              HWIO_32_WO
+#define HWN_GPMI_CTRL1_SET                              GPMI_CTRL1
+#define HWI_GPMI_CTRL1_SET                              
+#define HW_GPMI_CTRL1_CLR                               HW(GPMI_CTRL1_CLR)
+#define HWA_GPMI_CTRL1_CLR                              (HWA_GPMI_CTRL1 + 0x8)
+#define HWT_GPMI_CTRL1_CLR                              HWIO_32_WO
+#define HWN_GPMI_CTRL1_CLR                              GPMI_CTRL1
+#define HWI_GPMI_CTRL1_CLR                              
+#define HW_GPMI_CTRL1_TOG                               HW(GPMI_CTRL1_TOG)
+#define HWA_GPMI_CTRL1_TOG                              (HWA_GPMI_CTRL1 + 0xc)
+#define HWT_GPMI_CTRL1_TOG                              HWIO_32_WO
+#define HWN_GPMI_CTRL1_TOG                              GPMI_CTRL1
+#define HWI_GPMI_CTRL1_TOG                              
+#define BP_GPMI_CTRL1_DSAMPLE_TIME                      12
+#define BM_GPMI_CTRL1_DSAMPLE_TIME                      0x7000
+#define BF_GPMI_CTRL1_DSAMPLE_TIME(v)                   (((v) & 0x7) << 12)
+#define BFM_GPMI_CTRL1_DSAMPLE_TIME(v)                  BM_GPMI_CTRL1_DSAMPLE_TIME
+#define BF_GPMI_CTRL1_DSAMPLE_TIME_V(e)                 BF_GPMI_CTRL1_DSAMPLE_TIME(BV_GPMI_CTRL1_DSAMPLE_TIME__##e)
+#define BFM_GPMI_CTRL1_DSAMPLE_TIME_V(v)                BM_GPMI_CTRL1_DSAMPLE_TIME
+#define BP_GPMI_CTRL1_DMA2ECC_MODE                      11
+#define BM_GPMI_CTRL1_DMA2ECC_MODE                      0x800
+#define BF_GPMI_CTRL1_DMA2ECC_MODE(v)                   (((v) & 0x1) << 11)
+#define BFM_GPMI_CTRL1_DMA2ECC_MODE(v)                  BM_GPMI_CTRL1_DMA2ECC_MODE
+#define BF_GPMI_CTRL1_DMA2ECC_MODE_V(e)                 BF_GPMI_CTRL1_DMA2ECC_MODE(BV_GPMI_CTRL1_DMA2ECC_MODE__##e)
+#define BFM_GPMI_CTRL1_DMA2ECC_MODE_V(v)                BM_GPMI_CTRL1_DMA2ECC_MODE
+#define BP_GPMI_CTRL1_DEV_IRQ                           10
+#define BM_GPMI_CTRL1_DEV_IRQ                           0x400
+#define BF_GPMI_CTRL1_DEV_IRQ(v)                        (((v) & 0x1) << 10)
+#define BFM_GPMI_CTRL1_DEV_IRQ(v)                       BM_GPMI_CTRL1_DEV_IRQ
+#define BF_GPMI_CTRL1_DEV_IRQ_V(e)                      BF_GPMI_CTRL1_DEV_IRQ(BV_GPMI_CTRL1_DEV_IRQ__##e)
+#define BFM_GPMI_CTRL1_DEV_IRQ_V(v)                     BM_GPMI_CTRL1_DEV_IRQ
+#define BP_GPMI_CTRL1_TIMEOUT_IRQ                       9
+#define BM_GPMI_CTRL1_TIMEOUT_IRQ                       0x200
+#define BF_GPMI_CTRL1_TIMEOUT_IRQ(v)                    (((v) & 0x1) << 9)
+#define BFM_GPMI_CTRL1_TIMEOUT_IRQ(v)                   BM_GPMI_CTRL1_TIMEOUT_IRQ
+#define BF_GPMI_CTRL1_TIMEOUT_IRQ_V(e)                  BF_GPMI_CTRL1_TIMEOUT_IRQ(BV_GPMI_CTRL1_TIMEOUT_IRQ__##e)
+#define BFM_GPMI_CTRL1_TIMEOUT_IRQ_V(v)                 BM_GPMI_CTRL1_TIMEOUT_IRQ
+#define BP_GPMI_CTRL1_BURST_EN                          8
+#define BM_GPMI_CTRL1_BURST_EN                          0x100
+#define BF_GPMI_CTRL1_BURST_EN(v)                       (((v) & 0x1) << 8)
+#define BFM_GPMI_CTRL1_BURST_EN(v)                      BM_GPMI_CTRL1_BURST_EN
+#define BF_GPMI_CTRL1_BURST_EN_V(e)                     BF_GPMI_CTRL1_BURST_EN(BV_GPMI_CTRL1_BURST_EN__##e)
+#define BFM_GPMI_CTRL1_BURST_EN_V(v)                    BM_GPMI_CTRL1_BURST_EN
+#define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY3             7
+#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY3             0x80
+#define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY3(v)          (((v) & 0x1) << 7)
+#define BFM_GPMI_CTRL1_ABORT_WAIT_FOR_READY3(v)         BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY3
+#define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY3_V(e)        BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY3(BV_GPMI_CTRL1_ABORT_WAIT_FOR_READY3__##e)
+#define BFM_GPMI_CTRL1_ABORT_WAIT_FOR_READY3_V(v)       BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY3
+#define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY2             6
+#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY2             0x40
+#define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY2(v)          (((v) & 0x1) << 6)
+#define BFM_GPMI_CTRL1_ABORT_WAIT_FOR_READY2(v)         BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY2
+#define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY2_V(e)        BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY2(BV_GPMI_CTRL1_ABORT_WAIT_FOR_READY2__##e)
+#define BFM_GPMI_CTRL1_ABORT_WAIT_FOR_READY2_V(v)       BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY2
+#define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY1             5
+#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY1             0x20
+#define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY1(v)          (((v) & 0x1) << 5)
+#define BFM_GPMI_CTRL1_ABORT_WAIT_FOR_READY1(v)         BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY1
+#define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY1_V(e)        BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY1(BV_GPMI_CTRL1_ABORT_WAIT_FOR_READY1__##e)
+#define BFM_GPMI_CTRL1_ABORT_WAIT_FOR_READY1_V(v)       BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY1
+#define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY0             4
+#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY0             0x10
+#define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY0(v)          (((v) & 0x1) << 4)
+#define BFM_GPMI_CTRL1_ABORT_WAIT_FOR_READY0(v)         BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY0
+#define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY0_V(e)        BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY0(BV_GPMI_CTRL1_ABORT_WAIT_FOR_READY0__##e)
+#define BFM_GPMI_CTRL1_ABORT_WAIT_FOR_READY0_V(v)       BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY0
+#define BP_GPMI_CTRL1_DEV_RESET                         3
+#define BM_GPMI_CTRL1_DEV_RESET                         0x8
+#define BV_GPMI_CTRL1_DEV_RESET__ENABLED                0x0
+#define BV_GPMI_CTRL1_DEV_RESET__DISABLED               0x1
+#define BF_GPMI_CTRL1_DEV_RESET(v)                      (((v) & 0x1) << 3)
+#define BFM_GPMI_CTRL1_DEV_RESET(v)                     BM_GPMI_CTRL1_DEV_RESET
+#define BF_GPMI_CTRL1_DEV_RESET_V(e)                    BF_GPMI_CTRL1_DEV_RESET(BV_GPMI_CTRL1_DEV_RESET__##e)
+#define BFM_GPMI_CTRL1_DEV_RESET_V(v)                   BM_GPMI_CTRL1_DEV_RESET
+#define BP_GPMI_CTRL1_ATA_IRQRDY_POLARITY               2
+#define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY               0x4
+#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVELOW    0x0
+#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVEHIGH   0x1
+#define BF_GPMI_CTRL1_ATA_IRQRDY_POLARITY(v)            (((v) & 0x1) << 2)
+#define BFM_GPMI_CTRL1_ATA_IRQRDY_POLARITY(v)           BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY
+#define BF_GPMI_CTRL1_ATA_IRQRDY_POLARITY_V(e)          BF_GPMI_CTRL1_ATA_IRQRDY_POLARITY(BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__##e)
+#define BFM_GPMI_CTRL1_ATA_IRQRDY_POLARITY_V(v)         BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY
+#define BP_GPMI_CTRL1_CAMERA_MODE                       1
+#define BM_GPMI_CTRL1_CAMERA_MODE                       0x2
+#define BF_GPMI_CTRL1_CAMERA_MODE(v)                    (((v) & 0x1) << 1)
+#define BFM_GPMI_CTRL1_CAMERA_MODE(v)                   BM_GPMI_CTRL1_CAMERA_MODE
+#define BF_GPMI_CTRL1_CAMERA_MODE_V(e)                  BF_GPMI_CTRL1_CAMERA_MODE(BV_GPMI_CTRL1_CAMERA_MODE__##e)
+#define BFM_GPMI_CTRL1_CAMERA_MODE_V(v)                 BM_GPMI_CTRL1_CAMERA_MODE
+#define BP_GPMI_CTRL1_GPMI_MODE                         0
+#define BM_GPMI_CTRL1_GPMI_MODE                         0x1
+#define BV_GPMI_CTRL1_GPMI_MODE__NAND                   0x0
+#define BV_GPMI_CTRL1_GPMI_MODE__ATA                    0x1
+#define BF_GPMI_CTRL1_GPMI_MODE(v)                      (((v) & 0x1) << 0)
+#define BFM_GPMI_CTRL1_GPMI_MODE(v)                     BM_GPMI_CTRL1_GPMI_MODE
+#define BF_GPMI_CTRL1_GPMI_MODE_V(e)                    BF_GPMI_CTRL1_GPMI_MODE(BV_GPMI_CTRL1_GPMI_MODE__##e)
+#define BFM_GPMI_CTRL1_GPMI_MODE_V(v)                   BM_GPMI_CTRL1_GPMI_MODE
+
+#define HW_GPMI_TIMING0                     HW(GPMI_TIMING0)
+#define HWA_GPMI_TIMING0                    (0x8000c000 + 0x70)
+#define HWT_GPMI_TIMING0                    HWIO_32_RW
+#define HWN_GPMI_TIMING0                    GPMI_TIMING0
+#define HWI_GPMI_TIMING0                    
+#define BP_GPMI_TIMING0_ADDRESS_SETUP       16
+#define BM_GPMI_TIMING0_ADDRESS_SETUP       0xff0000
+#define BF_GPMI_TIMING0_ADDRESS_SETUP(v)    (((v) & 0xff) << 16)
+#define BFM_GPMI_TIMING0_ADDRESS_SETUP(v)   BM_GPMI_TIMING0_ADDRESS_SETUP
+#define BF_GPMI_TIMING0_ADDRESS_SETUP_V(e)  BF_GPMI_TIMING0_ADDRESS_SETUP(BV_GPMI_TIMING0_ADDRESS_SETUP__##e)
+#define BFM_GPMI_TIMING0_ADDRESS_SETUP_V(v) BM_GPMI_TIMING0_ADDRESS_SETUP
+#define BP_GPMI_TIMING0_DATA_HOLD           8
+#define BM_GPMI_TIMING0_DATA_HOLD           0xff00
+#define BF_GPMI_TIMING0_DATA_HOLD(v)        (((v) & 0xff) << 8)
+#define BFM_GPMI_TIMING0_DATA_HOLD(v)       BM_GPMI_TIMING0_DATA_HOLD
+#define BF_GPMI_TIMING0_DATA_HOLD_V(e)      BF_GPMI_TIMING0_DATA_HOLD(BV_GPMI_TIMING0_DATA_HOLD__##e)
+#define BFM_GPMI_TIMING0_DATA_HOLD_V(v)     BM_GPMI_TIMING0_DATA_HOLD
+#define BP_GPMI_TIMING0_DATA_SETUP          0
+#define BM_GPMI_TIMING0_DATA_SETUP          0xff
+#define BF_GPMI_TIMING0_DATA_SETUP(v)       (((v) & 0xff) << 0)
+#define BFM_GPMI_TIMING0_DATA_SETUP(v)      BM_GPMI_TIMING0_DATA_SETUP
+#define BF_GPMI_TIMING0_DATA_SETUP_V(e)     BF_GPMI_TIMING0_DATA_SETUP(BV_GPMI_TIMING0_DATA_SETUP__##e)
+#define BFM_GPMI_TIMING0_DATA_SETUP_V(v)    BM_GPMI_TIMING0_DATA_SETUP
+
+#define HW_GPMI_TIMING1                             HW(GPMI_TIMING1)
+#define HWA_GPMI_TIMING1                            (0x8000c000 + 0x80)
+#define HWT_GPMI_TIMING1                            HWIO_32_RW
+#define HWN_GPMI_TIMING1                            GPMI_TIMING1
+#define HWI_GPMI_TIMING1                            
+#define BP_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT         16
+#define BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT         0xffff0000
+#define BF_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(v)      (((v) & 0xffff) << 16)
+#define BFM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(v)     BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT
+#define BF_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_V(e)    BF_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(BV_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT__##e)
+#define BFM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_V(v)   BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT
+
+#define HW_GPMI_TIMING2                     HW(GPMI_TIMING2)
+#define HWA_GPMI_TIMING2                    (0x8000c000 + 0x90)
+#define HWT_GPMI_TIMING2                    HWIO_32_RW
+#define HWN_GPMI_TIMING2                    GPMI_TIMING2
+#define HWI_GPMI_TIMING2                    
+#define BP_GPMI_TIMING2_UDMA_TRP            24
+#define BM_GPMI_TIMING2_UDMA_TRP            0xff000000
+#define BF_GPMI_TIMING2_UDMA_TRP(v)         (((v) & 0xff) << 24)
+#define BFM_GPMI_TIMING2_UDMA_TRP(v)        BM_GPMI_TIMING2_UDMA_TRP
+#define BF_GPMI_TIMING2_UDMA_TRP_V(e)       BF_GPMI_TIMING2_UDMA_TRP(BV_GPMI_TIMING2_UDMA_TRP__##e)
+#define BFM_GPMI_TIMING2_UDMA_TRP_V(v)      BM_GPMI_TIMING2_UDMA_TRP
+#define BP_GPMI_TIMING2_UDMA_ENV            16
+#define BM_GPMI_TIMING2_UDMA_ENV            0xff0000
+#define BF_GPMI_TIMING2_UDMA_ENV(v)         (((v) & 0xff) << 16)
+#define BFM_GPMI_TIMING2_UDMA_ENV(v)        BM_GPMI_TIMING2_UDMA_ENV
+#define BF_GPMI_TIMING2_UDMA_ENV_V(e)       BF_GPMI_TIMING2_UDMA_ENV(BV_GPMI_TIMING2_UDMA_ENV__##e)
+#define BFM_GPMI_TIMING2_UDMA_ENV_V(v)      BM_GPMI_TIMING2_UDMA_ENV
+#define BP_GPMI_TIMING2_UDMA_HOLD           8
+#define BM_GPMI_TIMING2_UDMA_HOLD           0xff00
+#define BF_GPMI_TIMING2_UDMA_HOLD(v)        (((v) & 0xff) << 8)
+#define BFM_GPMI_TIMING2_UDMA_HOLD(v)       BM_GPMI_TIMING2_UDMA_HOLD
+#define BF_GPMI_TIMING2_UDMA_HOLD_V(e)      BF_GPMI_TIMING2_UDMA_HOLD(BV_GPMI_TIMING2_UDMA_HOLD__##e)
+#define BFM_GPMI_TIMING2_UDMA_HOLD_V(v)     BM_GPMI_TIMING2_UDMA_HOLD
+#define BP_GPMI_TIMING2_UDMA_SETUP          0
+#define BM_GPMI_TIMING2_UDMA_SETUP          0xff
+#define BF_GPMI_TIMING2_UDMA_SETUP(v)       (((v) & 0xff) << 0)
+#define BFM_GPMI_TIMING2_UDMA_SETUP(v)      BM_GPMI_TIMING2_UDMA_SETUP
+#define BF_GPMI_TIMING2_UDMA_SETUP_V(e)     BF_GPMI_TIMING2_UDMA_SETUP(BV_GPMI_TIMING2_UDMA_SETUP__##e)
+#define BFM_GPMI_TIMING2_UDMA_SETUP_V(v)    BM_GPMI_TIMING2_UDMA_SETUP
+
+#define HW_GPMI_DATA            HW(GPMI_DATA)
+#define HWA_GPMI_DATA           (0x8000c000 + 0xa0)
+#define HWT_GPMI_DATA           HWIO_32_RW
+#define HWN_GPMI_DATA           GPMI_DATA
+#define HWI_GPMI_DATA           
+#define BP_GPMI_DATA_DATA       0
+#define BM_GPMI_DATA_DATA       0xffffffff
+#define BF_GPMI_DATA_DATA(v)    (((v) & 0xffffffff) << 0)
+#define BFM_GPMI_DATA_DATA(v)   BM_GPMI_DATA_DATA
+#define BF_GPMI_DATA_DATA_V(e)  BF_GPMI_DATA_DATA(BV_GPMI_DATA_DATA__##e)
+#define BFM_GPMI_DATA_DATA_V(v) BM_GPMI_DATA_DATA
+
+#define HW_GPMI_STAT                            HW(GPMI_STAT)
+#define HWA_GPMI_STAT                           (0x8000c000 + 0xb0)
+#define HWT_GPMI_STAT                           HWIO_32_RW
+#define HWN_GPMI_STAT                           GPMI_STAT
+#define HWI_GPMI_STAT                           
+#define BP_GPMI_STAT_PRESENT                    31
+#define BM_GPMI_STAT_PRESENT                    0x80000000
+#define BV_GPMI_STAT_PRESENT__UNAVAILABLE       0x0
+#define BV_GPMI_STAT_PRESENT__AVAILABLE         0x1
+#define BF_GPMI_STAT_PRESENT(v)                 (((v) & 0x1) << 31)
+#define BFM_GPMI_STAT_PRESENT(v)                BM_GPMI_STAT_PRESENT
+#define BF_GPMI_STAT_PRESENT_V(e)               BF_GPMI_STAT_PRESENT(BV_GPMI_STAT_PRESENT__##e)
+#define BFM_GPMI_STAT_PRESENT_V(v)              BM_GPMI_STAT_PRESENT
+#define BP_GPMI_STAT_RDY_TIMEOUT                8
+#define BM_GPMI_STAT_RDY_TIMEOUT                0xf00
+#define BF_GPMI_STAT_RDY_TIMEOUT(v)             (((v) & 0xf) << 8)
+#define BFM_GPMI_STAT_RDY_TIMEOUT(v)            BM_GPMI_STAT_RDY_TIMEOUT
+#define BF_GPMI_STAT_RDY_TIMEOUT_V(e)           BF_GPMI_STAT_RDY_TIMEOUT(BV_GPMI_STAT_RDY_TIMEOUT__##e)
+#define BFM_GPMI_STAT_RDY_TIMEOUT_V(v)          BM_GPMI_STAT_RDY_TIMEOUT
+#define BP_GPMI_STAT_ATA_IRQ                    7
+#define BM_GPMI_STAT_ATA_IRQ                    0x80
+#define BF_GPMI_STAT_ATA_IRQ(v)                 (((v) & 0x1) << 7)
+#define BFM_GPMI_STAT_ATA_IRQ(v)                BM_GPMI_STAT_ATA_IRQ
+#define BF_GPMI_STAT_ATA_IRQ_V(e)               BF_GPMI_STAT_ATA_IRQ(BV_GPMI_STAT_ATA_IRQ__##e)
+#define BFM_GPMI_STAT_ATA_IRQ_V(v)              BM_GPMI_STAT_ATA_IRQ
+#define BP_GPMI_STAT_INVALID_BUFFER_MASK        6
+#define BM_GPMI_STAT_INVALID_BUFFER_MASK        0x40
+#define BF_GPMI_STAT_INVALID_BUFFER_MASK(v)     (((v) & 0x1) << 6)
+#define BFM_GPMI_STAT_INVALID_BUFFER_MASK(v)    BM_GPMI_STAT_INVALID_BUFFER_MASK
+#define BF_GPMI_STAT_INVALID_BUFFER_MASK_V(e)   BF_GPMI_STAT_INVALID_BUFFER_MASK(BV_GPMI_STAT_INVALID_BUFFER_MASK__##e)
+#define BFM_GPMI_STAT_INVALID_BUFFER_MASK_V(v)  BM_GPMI_STAT_INVALID_BUFFER_MASK
+#define BP_GPMI_STAT_FIFO_EMPTY                 5
+#define BM_GPMI_STAT_FIFO_EMPTY                 0x20
+#define BV_GPMI_STAT_FIFO_EMPTY__NOT_EMPTY      0x0
+#define BV_GPMI_STAT_FIFO_EMPTY__EMPTY          0x1
+#define BF_GPMI_STAT_FIFO_EMPTY(v)              (((v) & 0x1) << 5)
+#define BFM_GPMI_STAT_FIFO_EMPTY(v)             BM_GPMI_STAT_FIFO_EMPTY
+#define BF_GPMI_STAT_FIFO_EMPTY_V(e)            BF_GPMI_STAT_FIFO_EMPTY(BV_GPMI_STAT_FIFO_EMPTY__##e)
+#define BFM_GPMI_STAT_FIFO_EMPTY_V(v)           BM_GPMI_STAT_FIFO_EMPTY
+#define BP_GPMI_STAT_FIFO_FULL                  4
+#define BM_GPMI_STAT_FIFO_FULL                  0x10
+#define BV_GPMI_STAT_FIFO_FULL__NOT_FULL        0x0
+#define BV_GPMI_STAT_FIFO_FULL__FULL            0x1
+#define BF_GPMI_STAT_FIFO_FULL(v)               (((v) & 0x1) << 4)
+#define BFM_GPMI_STAT_FIFO_FULL(v)              BM_GPMI_STAT_FIFO_FULL
+#define BF_GPMI_STAT_FIFO_FULL_V(e)             BF_GPMI_STAT_FIFO_FULL(BV_GPMI_STAT_FIFO_FULL__##e)
+#define BFM_GPMI_STAT_FIFO_FULL_V(v)            BM_GPMI_STAT_FIFO_FULL
+#define BP_GPMI_STAT_DEV3_ERROR                 3
+#define BM_GPMI_STAT_DEV3_ERROR                 0x8
+#define BF_GPMI_STAT_DEV3_ERROR(v)              (((v) & 0x1) << 3)
+#define BFM_GPMI_STAT_DEV3_ERROR(v)             BM_GPMI_STAT_DEV3_ERROR
+#define BF_GPMI_STAT_DEV3_ERROR_V(e)            BF_GPMI_STAT_DEV3_ERROR(BV_GPMI_STAT_DEV3_ERROR__##e)
+#define BFM_GPMI_STAT_DEV3_ERROR_V(v)           BM_GPMI_STAT_DEV3_ERROR
+#define BP_GPMI_STAT_DEV2_ERROR                 2
+#define BM_GPMI_STAT_DEV2_ERROR                 0x4
+#define BF_GPMI_STAT_DEV2_ERROR(v)              (((v) & 0x1) << 2)
+#define BFM_GPMI_STAT_DEV2_ERROR(v)             BM_GPMI_STAT_DEV2_ERROR
+#define BF_GPMI_STAT_DEV2_ERROR_V(e)            BF_GPMI_STAT_DEV2_ERROR(BV_GPMI_STAT_DEV2_ERROR__##e)
+#define BFM_GPMI_STAT_DEV2_ERROR_V(v)           BM_GPMI_STAT_DEV2_ERROR
+#define BP_GPMI_STAT_DEV1_ERROR                 1
+#define BM_GPMI_STAT_DEV1_ERROR                 0x2
+#define BF_GPMI_STAT_DEV1_ERROR(v)              (((v) & 0x1) << 1)
+#define BFM_GPMI_STAT_DEV1_ERROR(v)             BM_GPMI_STAT_DEV1_ERROR
+#define BF_GPMI_STAT_DEV1_ERROR_V(e)            BF_GPMI_STAT_DEV1_ERROR(BV_GPMI_STAT_DEV1_ERROR__##e)
+#define BFM_GPMI_STAT_DEV1_ERROR_V(v)           BM_GPMI_STAT_DEV1_ERROR
+#define BP_GPMI_STAT_DEV0_ERROR                 0
+#define BM_GPMI_STAT_DEV0_ERROR                 0x1
+#define BF_GPMI_STAT_DEV0_ERROR(v)              (((v) & 0x1) << 0)
+#define BFM_GPMI_STAT_DEV0_ERROR(v)             BM_GPMI_STAT_DEV0_ERROR
+#define BF_GPMI_STAT_DEV0_ERROR_V(e)            BF_GPMI_STAT_DEV0_ERROR(BV_GPMI_STAT_DEV0_ERROR__##e)
+#define BFM_GPMI_STAT_DEV0_ERROR_V(v)           BM_GPMI_STAT_DEV0_ERROR
+
+#define HW_GPMI_DEBUG                           HW(GPMI_DEBUG)
+#define HWA_GPMI_DEBUG                          (0x8000c000 + 0xc0)
+#define HWT_GPMI_DEBUG                          HWIO_32_RW
+#define HWN_GPMI_DEBUG                          GPMI_DEBUG
+#define HWI_GPMI_DEBUG                          
+#define BP_GPMI_DEBUG_READY3                    31
+#define BM_GPMI_DEBUG_READY3                    0x80000000
+#define BF_GPMI_DEBUG_READY3(v)                 (((v) & 0x1) << 31)
+#define BFM_GPMI_DEBUG_READY3(v)                BM_GPMI_DEBUG_READY3
+#define BF_GPMI_DEBUG_READY3_V(e)               BF_GPMI_DEBUG_READY3(BV_GPMI_DEBUG_READY3__##e)
+#define BFM_GPMI_DEBUG_READY3_V(v)              BM_GPMI_DEBUG_READY3
+#define BP_GPMI_DEBUG_READY2                    30
+#define BM_GPMI_DEBUG_READY2                    0x40000000
+#define BF_GPMI_DEBUG_READY2(v)                 (((v) & 0x1) << 30)
+#define BFM_GPMI_DEBUG_READY2(v)                BM_GPMI_DEBUG_READY2
+#define BF_GPMI_DEBUG_READY2_V(e)               BF_GPMI_DEBUG_READY2(BV_GPMI_DEBUG_READY2__##e)
+#define BFM_GPMI_DEBUG_READY2_V(v)              BM_GPMI_DEBUG_READY2
+#define BP_GPMI_DEBUG_READY1                    29
+#define BM_GPMI_DEBUG_READY1                    0x20000000
+#define BF_GPMI_DEBUG_READY1(v)                 (((v) & 0x1) << 29)
+#define BFM_GPMI_DEBUG_READY1(v)                BM_GPMI_DEBUG_READY1
+#define BF_GPMI_DEBUG_READY1_V(e)               BF_GPMI_DEBUG_READY1(BV_GPMI_DEBUG_READY1__##e)
+#define BFM_GPMI_DEBUG_READY1_V(v)              BM_GPMI_DEBUG_READY1
+#define BP_GPMI_DEBUG_READY0                    28
+#define BM_GPMI_DEBUG_READY0                    0x10000000
+#define BF_GPMI_DEBUG_READY0(v)                 (((v) & 0x1) << 28)
+#define BFM_GPMI_DEBUG_READY0(v)                BM_GPMI_DEBUG_READY0
+#define BF_GPMI_DEBUG_READY0_V(e)               BF_GPMI_DEBUG_READY0(BV_GPMI_DEBUG_READY0__##e)
+#define BFM_GPMI_DEBUG_READY0_V(v)              BM_GPMI_DEBUG_READY0
+#define BP_GPMI_DEBUG_WAIT_FOR_READY_END3       27
+#define BM_GPMI_DEBUG_WAIT_FOR_READY_END3       0x8000000
+#define BF_GPMI_DEBUG_WAIT_FOR_READY_END3(v)    (((v) & 0x1) << 27)
+#define BFM_GPMI_DEBUG_WAIT_FOR_READY_END3(v)   BM_GPMI_DEBUG_WAIT_FOR_READY_END3
+#define BF_GPMI_DEBUG_WAIT_FOR_READY_END3_V(e)  BF_GPMI_DEBUG_WAIT_FOR_READY_END3(BV_GPMI_DEBUG_WAIT_FOR_READY_END3__##e)
+#define BFM_GPMI_DEBUG_WAIT_FOR_READY_END3_V(v) BM_GPMI_DEBUG_WAIT_FOR_READY_END3
+#define BP_GPMI_DEBUG_WAIT_FOR_READY_END2       26
+#define BM_GPMI_DEBUG_WAIT_FOR_READY_END2       0x4000000
+#define BF_GPMI_DEBUG_WAIT_FOR_READY_END2(v)    (((v) & 0x1) << 26)
+#define BFM_GPMI_DEBUG_WAIT_FOR_READY_END2(v)   BM_GPMI_DEBUG_WAIT_FOR_READY_END2
+#define BF_GPMI_DEBUG_WAIT_FOR_READY_END2_V(e)  BF_GPMI_DEBUG_WAIT_FOR_READY_END2(BV_GPMI_DEBUG_WAIT_FOR_READY_END2__##e)
+#define BFM_GPMI_DEBUG_WAIT_FOR_READY_END2_V(v) BM_GPMI_DEBUG_WAIT_FOR_READY_END2
+#define BP_GPMI_DEBUG_WAIT_FOR_READY_END1       25
+#define BM_GPMI_DEBUG_WAIT_FOR_READY_END1       0x2000000
+#define BF_GPMI_DEBUG_WAIT_FOR_READY_END1(v)    (((v) & 0x1) << 25)
+#define BFM_GPMI_DEBUG_WAIT_FOR_READY_END1(v)   BM_GPMI_DEBUG_WAIT_FOR_READY_END1
+#define BF_GPMI_DEBUG_WAIT_FOR_READY_END1_V(e)  BF_GPMI_DEBUG_WAIT_FOR_READY_END1(BV_GPMI_DEBUG_WAIT_FOR_READY_END1__##e)
+#define BFM_GPMI_DEBUG_WAIT_FOR_READY_END1_V(v) BM_GPMI_DEBUG_WAIT_FOR_READY_END1
+#define BP_GPMI_DEBUG_WAIT_FOR_READY_END0       24
+#define BM_GPMI_DEBUG_WAIT_FOR_READY_END0       0x1000000
+#define BF_GPMI_DEBUG_WAIT_FOR_READY_END0(v)    (((v) & 0x1) << 24)
+#define BFM_GPMI_DEBUG_WAIT_FOR_READY_END0(v)   BM_GPMI_DEBUG_WAIT_FOR_READY_END0
+#define BF_GPMI_DEBUG_WAIT_FOR_READY_END0_V(e)  BF_GPMI_DEBUG_WAIT_FOR_READY_END0(BV_GPMI_DEBUG_WAIT_FOR_READY_END0__##e)
+#define BFM_GPMI_DEBUG_WAIT_FOR_READY_END0_V(v) BM_GPMI_DEBUG_WAIT_FOR_READY_END0
+#define BP_GPMI_DEBUG_SENSE3                    23
+#define BM_GPMI_DEBUG_SENSE3                    0x800000
+#define BF_GPMI_DEBUG_SENSE3(v)                 (((v) & 0x1) << 23)
+#define BFM_GPMI_DEBUG_SENSE3(v)                BM_GPMI_DEBUG_SENSE3
+#define BF_GPMI_DEBUG_SENSE3_V(e)               BF_GPMI_DEBUG_SENSE3(BV_GPMI_DEBUG_SENSE3__##e)
+#define BFM_GPMI_DEBUG_SENSE3_V(v)              BM_GPMI_DEBUG_SENSE3
+#define BP_GPMI_DEBUG_SENSE2                    22
+#define BM_GPMI_DEBUG_SENSE2                    0x400000
+#define BF_GPMI_DEBUG_SENSE2(v)                 (((v) & 0x1) << 22)
+#define BFM_GPMI_DEBUG_SENSE2(v)                BM_GPMI_DEBUG_SENSE2
+#define BF_GPMI_DEBUG_SENSE2_V(e)               BF_GPMI_DEBUG_SENSE2(BV_GPMI_DEBUG_SENSE2__##e)
+#define BFM_GPMI_DEBUG_SENSE2_V(v)              BM_GPMI_DEBUG_SENSE2
+#define BP_GPMI_DEBUG_SENSE1                    21
+#define BM_GPMI_DEBUG_SENSE1                    0x200000
+#define BF_GPMI_DEBUG_SENSE1(v)                 (((v) & 0x1) << 21)
+#define BFM_GPMI_DEBUG_SENSE1(v)                BM_GPMI_DEBUG_SENSE1
+#define BF_GPMI_DEBUG_SENSE1_V(e)               BF_GPMI_DEBUG_SENSE1(BV_GPMI_DEBUG_SENSE1__##e)
+#define BFM_GPMI_DEBUG_SENSE1_V(v)              BM_GPMI_DEBUG_SENSE1
+#define BP_GPMI_DEBUG_SENSE0                    20
+#define BM_GPMI_DEBUG_SENSE0                    0x100000
+#define BF_GPMI_DEBUG_SENSE0(v)                 (((v) & 0x1) << 20)
+#define BFM_GPMI_DEBUG_SENSE0(v)                BM_GPMI_DEBUG_SENSE0
+#define BF_GPMI_DEBUG_SENSE0_V(e)               BF_GPMI_DEBUG_SENSE0(BV_GPMI_DEBUG_SENSE0__##e)
+#define BFM_GPMI_DEBUG_SENSE0_V(v)              BM_GPMI_DEBUG_SENSE0
+#define BP_GPMI_DEBUG_DMAREQ3                   19
+#define BM_GPMI_DEBUG_DMAREQ3                   0x80000
+#define BF_GPMI_DEBUG_DMAREQ3(v)                (((v) & 0x1) << 19)
+#define BFM_GPMI_DEBUG_DMAREQ3(v)               BM_GPMI_DEBUG_DMAREQ3
+#define BF_GPMI_DEBUG_DMAREQ3_V(e)              BF_GPMI_DEBUG_DMAREQ3(BV_GPMI_DEBUG_DMAREQ3__##e)
+#define BFM_GPMI_DEBUG_DMAREQ3_V(v)             BM_GPMI_DEBUG_DMAREQ3
+#define BP_GPMI_DEBUG_DMAREQ2                   18
+#define BM_GPMI_DEBUG_DMAREQ2                   0x40000
+#define BF_GPMI_DEBUG_DMAREQ2(v)                (((v) & 0x1) << 18)
+#define BFM_GPMI_DEBUG_DMAREQ2(v)               BM_GPMI_DEBUG_DMAREQ2
+#define BF_GPMI_DEBUG_DMAREQ2_V(e)              BF_GPMI_DEBUG_DMAREQ2(BV_GPMI_DEBUG_DMAREQ2__##e)
+#define BFM_GPMI_DEBUG_DMAREQ2_V(v)             BM_GPMI_DEBUG_DMAREQ2
+#define BP_GPMI_DEBUG_DMAREQ1                   17
+#define BM_GPMI_DEBUG_DMAREQ1                   0x20000
+#define BF_GPMI_DEBUG_DMAREQ1(v)                (((v) & 0x1) << 17)
+#define BFM_GPMI_DEBUG_DMAREQ1(v)               BM_GPMI_DEBUG_DMAREQ1
+#define BF_GPMI_DEBUG_DMAREQ1_V(e)              BF_GPMI_DEBUG_DMAREQ1(BV_GPMI_DEBUG_DMAREQ1__##e)
+#define BFM_GPMI_DEBUG_DMAREQ1_V(v)             BM_GPMI_DEBUG_DMAREQ1
+#define BP_GPMI_DEBUG_DMAREQ0                   16
+#define BM_GPMI_DEBUG_DMAREQ0                   0x10000
+#define BF_GPMI_DEBUG_DMAREQ0(v)                (((v) & 0x1) << 16)
+#define BFM_GPMI_DEBUG_DMAREQ0(v)               BM_GPMI_DEBUG_DMAREQ0
+#define BF_GPMI_DEBUG_DMAREQ0_V(e)              BF_GPMI_DEBUG_DMAREQ0(BV_GPMI_DEBUG_DMAREQ0__##e)
+#define BFM_GPMI_DEBUG_DMAREQ0_V(v)             BM_GPMI_DEBUG_DMAREQ0
+#define BP_GPMI_DEBUG_CMD_END                   12
+#define BM_GPMI_DEBUG_CMD_END                   0xf000
+#define BF_GPMI_DEBUG_CMD_END(v)                (((v) & 0xf) << 12)
+#define BFM_GPMI_DEBUG_CMD_END(v)               BM_GPMI_DEBUG_CMD_END
+#define BF_GPMI_DEBUG_CMD_END_V(e)              BF_GPMI_DEBUG_CMD_END(BV_GPMI_DEBUG_CMD_END__##e)
+#define BFM_GPMI_DEBUG_CMD_END_V(v)             BM_GPMI_DEBUG_CMD_END
+#define BP_GPMI_DEBUG_UDMA_STATE                8
+#define BM_GPMI_DEBUG_UDMA_STATE                0xf00
+#define BF_GPMI_DEBUG_UDMA_STATE(v)             (((v) & 0xf) << 8)
+#define BFM_GPMI_DEBUG_UDMA_STATE(v)            BM_GPMI_DEBUG_UDMA_STATE
+#define BF_GPMI_DEBUG_UDMA_STATE_V(e)           BF_GPMI_DEBUG_UDMA_STATE(BV_GPMI_DEBUG_UDMA_STATE__##e)
+#define BFM_GPMI_DEBUG_UDMA_STATE_V(v)          BM_GPMI_DEBUG_UDMA_STATE
+#define BP_GPMI_DEBUG_BUSY                      7
+#define BM_GPMI_DEBUG_BUSY                      0x80
+#define BV_GPMI_DEBUG_BUSY__DISABLED            0x0
+#define BV_GPMI_DEBUG_BUSY__ENABLED             0x1
+#define BF_GPMI_DEBUG_BUSY(v)                   (((v) & 0x1) << 7)
+#define BFM_GPMI_DEBUG_BUSY(v)                  BM_GPMI_DEBUG_BUSY
+#define BF_GPMI_DEBUG_BUSY_V(e)                 BF_GPMI_DEBUG_BUSY(BV_GPMI_DEBUG_BUSY__##e)
+#define BFM_GPMI_DEBUG_BUSY_V(v)                BM_GPMI_DEBUG_BUSY
+#define BP_GPMI_DEBUG_PIN_STATE                 4
+#define BM_GPMI_DEBUG_PIN_STATE                 0x70
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_IDLE       0x0
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_BYTCNT     0x1
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_ADDR       0x2
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_STALL      0x3
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_STROBE     0x4
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_ATARDY     0x5
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_DHOLD      0x6
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_DONE       0x7
+#define BF_GPMI_DEBUG_PIN_STATE(v)              (((v) & 0x7) << 4)
+#define BFM_GPMI_DEBUG_PIN_STATE(v)             BM_GPMI_DEBUG_PIN_STATE
+#define BF_GPMI_DEBUG_PIN_STATE_V(e)            BF_GPMI_DEBUG_PIN_STATE(BV_GPMI_DEBUG_PIN_STATE__##e)
+#define BFM_GPMI_DEBUG_PIN_STATE_V(v)           BM_GPMI_DEBUG_PIN_STATE
+#define BP_GPMI_DEBUG_MAIN_STATE                0
+#define BM_GPMI_DEBUG_MAIN_STATE                0xf
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_IDLE      0x0
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_BYTCNT    0x1
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFE    0x2
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFR    0x3
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_DMAREQ    0x4
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_DMAACK    0x5
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFF    0x6
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_LDFIFO    0x7
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_LDDMAR    0x8
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_RDCMP     0x9
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_DONE      0xa
+#define BF_GPMI_DEBUG_MAIN_STATE(v)             (((v) & 0xf) << 0)
+#define BFM_GPMI_DEBUG_MAIN_STATE(v)            BM_GPMI_DEBUG_MAIN_STATE
+#define BF_GPMI_DEBUG_MAIN_STATE_V(e)           BF_GPMI_DEBUG_MAIN_STATE(BV_GPMI_DEBUG_MAIN_STATE__##e)
+#define BFM_GPMI_DEBUG_MAIN_STATE_V(v)          BM_GPMI_DEBUG_MAIN_STATE
+
+#define HW_GPMI_VERSION             HW(GPMI_VERSION)
+#define HWA_GPMI_VERSION            (0x8000c000 + 0xd0)
+#define HWT_GPMI_VERSION            HWIO_32_RW
+#define HWN_GPMI_VERSION            GPMI_VERSION
+#define HWI_GPMI_VERSION            
+#define BP_GPMI_VERSION_MAJOR       24
+#define BM_GPMI_VERSION_MAJOR       0xff000000
+#define BF_GPMI_VERSION_MAJOR(v)    (((v) & 0xff) << 24)
+#define BFM_GPMI_VERSION_MAJOR(v)   BM_GPMI_VERSION_MAJOR
+#define BF_GPMI_VERSION_MAJOR_V(e)  BF_GPMI_VERSION_MAJOR(BV_GPMI_VERSION_MAJOR__##e)
+#define BFM_GPMI_VERSION_MAJOR_V(v) BM_GPMI_VERSION_MAJOR
+#define BP_GPMI_VERSION_MINOR       16
+#define BM_GPMI_VERSION_MINOR       0xff0000
+#define BF_GPMI_VERSION_MINOR(v)    (((v) & 0xff) << 16)
+#define BFM_GPMI_VERSION_MINOR(v)   BM_GPMI_VERSION_MINOR
+#define BF_GPMI_VERSION_MINOR_V(e)  BF_GPMI_VERSION_MINOR(BV_GPMI_VERSION_MINOR__##e)
+#define BFM_GPMI_VERSION_MINOR_V(v) BM_GPMI_VERSION_MINOR
+#define BP_GPMI_VERSION_STEP        0
+#define BM_GPMI_VERSION_STEP        0xffff
+#define BF_GPMI_VERSION_STEP(v)     (((v) & 0xffff) << 0)
+#define BFM_GPMI_VERSION_STEP(v)    BM_GPMI_VERSION_STEP
+#define BF_GPMI_VERSION_STEP_V(e)   BF_GPMI_VERSION_STEP(BV_GPMI_VERSION_STEP__##e)
+#define BFM_GPMI_VERSION_STEP_V(v)  BM_GPMI_VERSION_STEP
+
+#endif /* __HEADERGEN_STMP3700_GPMI_H__*/
diff --git a/firmware/target/arm/imx233/regs/stmp3700/i2c.h b/firmware/target/arm/imx233/regs/stmp3700/i2c.h
new file mode 100644
index 0000000000..5340f310b3
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3700/i2c.h
@@ -0,0 +1,822 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * stmp3700 version: 2.4.0
+ * stmp3700 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_STMP3700_I2C_H__
+#define __HEADERGEN_STMP3700_I2C_H__
+
+#define HW_I2C_CTRL0                                HW(I2C_CTRL0)
+#define HWA_I2C_CTRL0                               (0x80058000 + 0x0)
+#define HWT_I2C_CTRL0                               HWIO_32_RW
+#define HWN_I2C_CTRL0                               I2C_CTRL0
+#define HWI_I2C_CTRL0                               
+#define HW_I2C_CTRL0_SET                            HW(I2C_CTRL0_SET)
+#define HWA_I2C_CTRL0_SET                           (HWA_I2C_CTRL0 + 0x4)
+#define HWT_I2C_CTRL0_SET                           HWIO_32_WO
+#define HWN_I2C_CTRL0_SET                           I2C_CTRL0
+#define HWI_I2C_CTRL0_SET                           
+#define HW_I2C_CTRL0_CLR                            HW(I2C_CTRL0_CLR)
+#define HWA_I2C_CTRL0_CLR                           (HWA_I2C_CTRL0 + 0x8)
+#define HWT_I2C_CTRL0_CLR                           HWIO_32_WO
+#define HWN_I2C_CTRL0_CLR                           I2C_CTRL0
+#define HWI_I2C_CTRL0_CLR                           
+#define HW_I2C_CTRL0_TOG                            HW(I2C_CTRL0_TOG)
+#define HWA_I2C_CTRL0_TOG                           (HWA_I2C_CTRL0 + 0xc)
+#define HWT_I2C_CTRL0_TOG                           HWIO_32_WO
+#define HWN_I2C_CTRL0_TOG                           I2C_CTRL0
+#define HWI_I2C_CTRL0_TOG                           
+#define BP_I2C_CTRL0_SFTRST                         31
+#define BM_I2C_CTRL0_SFTRST                         0x80000000
+#define BV_I2C_CTRL0_SFTRST__RUN                    0x0
+#define BV_I2C_CTRL0_SFTRST__RESET                  0x1
+#define BF_I2C_CTRL0_SFTRST(v)                      (((v) & 0x1) << 31)
+#define BFM_I2C_CTRL0_SFTRST(v)                     BM_I2C_CTRL0_SFTRST
+#define BF_I2C_CTRL0_SFTRST_V(e)                    BF_I2C_CTRL0_SFTRST(BV_I2C_CTRL0_SFTRST__##e)
+#define BFM_I2C_CTRL0_SFTRST_V(v)                   BM_I2C_CTRL0_SFTRST
+#define BP_I2C_CTRL0_CLKGATE                        30
+#define BM_I2C_CTRL0_CLKGATE                        0x40000000
+#define BV_I2C_CTRL0_CLKGATE__RUN                   0x0
+#define BV_I2C_CTRL0_CLKGATE__NO_CLKS               0x1
+#define BF_I2C_CTRL0_CLKGATE(v)                     (((v) & 0x1) << 30)
+#define BFM_I2C_CTRL0_CLKGATE(v)                    BM_I2C_CTRL0_CLKGATE
+#define BF_I2C_CTRL0_CLKGATE_V(e)                   BF_I2C_CTRL0_CLKGATE(BV_I2C_CTRL0_CLKGATE__##e)
+#define BFM_I2C_CTRL0_CLKGATE_V(v)                  BM_I2C_CTRL0_CLKGATE
+#define BP_I2C_CTRL0_RUN                            29
+#define BM_I2C_CTRL0_RUN                            0x20000000
+#define BV_I2C_CTRL0_RUN__HALT                      0x0
+#define BV_I2C_CTRL0_RUN__RUN                       0x1
+#define BF_I2C_CTRL0_RUN(v)                         (((v) & 0x1) << 29)
+#define BFM_I2C_CTRL0_RUN(v)                        BM_I2C_CTRL0_RUN
+#define BF_I2C_CTRL0_RUN_V(e)                       BF_I2C_CTRL0_RUN(BV_I2C_CTRL0_RUN__##e)
+#define BFM_I2C_CTRL0_RUN_V(v)                      BM_I2C_CTRL0_RUN
+#define BP_I2C_CTRL0_PRE_ACK                        27
+#define BM_I2C_CTRL0_PRE_ACK                        0x8000000
+#define BF_I2C_CTRL0_PRE_ACK(v)                     (((v) & 0x1) << 27)
+#define BFM_I2C_CTRL0_PRE_ACK(v)                    BM_I2C_CTRL0_PRE_ACK
+#define BF_I2C_CTRL0_PRE_ACK_V(e)                   BF_I2C_CTRL0_PRE_ACK(BV_I2C_CTRL0_PRE_ACK__##e)
+#define BFM_I2C_CTRL0_PRE_ACK_V(v)                  BM_I2C_CTRL0_PRE_ACK
+#define BP_I2C_CTRL0_ACKNOWLEDGE                    26
+#define BM_I2C_CTRL0_ACKNOWLEDGE                    0x4000000
+#define BV_I2C_CTRL0_ACKNOWLEDGE__SNAK              0x0
+#define BV_I2C_CTRL0_ACKNOWLEDGE__ACK               0x1
+#define BF_I2C_CTRL0_ACKNOWLEDGE(v)                 (((v) & 0x1) << 26)
+#define BFM_I2C_CTRL0_ACKNOWLEDGE(v)                BM_I2C_CTRL0_ACKNOWLEDGE
+#define BF_I2C_CTRL0_ACKNOWLEDGE_V(e)               BF_I2C_CTRL0_ACKNOWLEDGE(BV_I2C_CTRL0_ACKNOWLEDGE__##e)
+#define BFM_I2C_CTRL0_ACKNOWLEDGE_V(v)              BM_I2C_CTRL0_ACKNOWLEDGE
+#define BP_I2C_CTRL0_SEND_NAK_ON_LAST               25
+#define BM_I2C_CTRL0_SEND_NAK_ON_LAST               0x2000000
+#define BV_I2C_CTRL0_SEND_NAK_ON_LAST__ACK_IT       0x0
+#define BV_I2C_CTRL0_SEND_NAK_ON_LAST__NAK_IT       0x1
+#define BF_I2C_CTRL0_SEND_NAK_ON_LAST(v)            (((v) & 0x1) << 25)
+#define BFM_I2C_CTRL0_SEND_NAK_ON_LAST(v)           BM_I2C_CTRL0_SEND_NAK_ON_LAST
+#define BF_I2C_CTRL0_SEND_NAK_ON_LAST_V(e)          BF_I2C_CTRL0_SEND_NAK_ON_LAST(BV_I2C_CTRL0_SEND_NAK_ON_LAST__##e)
+#define BFM_I2C_CTRL0_SEND_NAK_ON_LAST_V(v)         BM_I2C_CTRL0_SEND_NAK_ON_LAST
+#define BP_I2C_CTRL0_PIO_MODE                       24
+#define BM_I2C_CTRL0_PIO_MODE                       0x1000000
+#define BF_I2C_CTRL0_PIO_MODE(v)                    (((v) & 0x1) << 24)
+#define BFM_I2C_CTRL0_PIO_MODE(v)                   BM_I2C_CTRL0_PIO_MODE
+#define BF_I2C_CTRL0_PIO_MODE_V(e)                  BF_I2C_CTRL0_PIO_MODE(BV_I2C_CTRL0_PIO_MODE__##e)
+#define BFM_I2C_CTRL0_PIO_MODE_V(v)                 BM_I2C_CTRL0_PIO_MODE
+#define BP_I2C_CTRL0_MULTI_MASTER                   23
+#define BM_I2C_CTRL0_MULTI_MASTER                   0x800000
+#define BV_I2C_CTRL0_MULTI_MASTER__SINGLE           0x0
+#define BV_I2C_CTRL0_MULTI_MASTER__MULTIPLE         0x1
+#define BF_I2C_CTRL0_MULTI_MASTER(v)                (((v) & 0x1) << 23)
+#define BFM_I2C_CTRL0_MULTI_MASTER(v)               BM_I2C_CTRL0_MULTI_MASTER
+#define BF_I2C_CTRL0_MULTI_MASTER_V(e)              BF_I2C_CTRL0_MULTI_MASTER(BV_I2C_CTRL0_MULTI_MASTER__##e)
+#define BFM_I2C_CTRL0_MULTI_MASTER_V(v)             BM_I2C_CTRL0_MULTI_MASTER
+#define BP_I2C_CTRL0_CLOCK_HELD                     22
+#define BM_I2C_CTRL0_CLOCK_HELD                     0x400000
+#define BV_I2C_CTRL0_CLOCK_HELD__RELEASE            0x0
+#define BV_I2C_CTRL0_CLOCK_HELD__HELD_LOW           0x1
+#define BF_I2C_CTRL0_CLOCK_HELD(v)                  (((v) & 0x1) << 22)
+#define BFM_I2C_CTRL0_CLOCK_HELD(v)                 BM_I2C_CTRL0_CLOCK_HELD
+#define BF_I2C_CTRL0_CLOCK_HELD_V(e)                BF_I2C_CTRL0_CLOCK_HELD(BV_I2C_CTRL0_CLOCK_HELD__##e)
+#define BFM_I2C_CTRL0_CLOCK_HELD_V(v)               BM_I2C_CTRL0_CLOCK_HELD
+#define BP_I2C_CTRL0_RETAIN_CLOCK                   21
+#define BM_I2C_CTRL0_RETAIN_CLOCK                   0x200000
+#define BV_I2C_CTRL0_RETAIN_CLOCK__RELEASE          0x0
+#define BV_I2C_CTRL0_RETAIN_CLOCK__HOLD_LOW         0x1
+#define BF_I2C_CTRL0_RETAIN_CLOCK(v)                (((v) & 0x1) << 21)
+#define BFM_I2C_CTRL0_RETAIN_CLOCK(v)               BM_I2C_CTRL0_RETAIN_CLOCK
+#define BF_I2C_CTRL0_RETAIN_CLOCK_V(e)              BF_I2C_CTRL0_RETAIN_CLOCK(BV_I2C_CTRL0_RETAIN_CLOCK__##e)
+#define BFM_I2C_CTRL0_RETAIN_CLOCK_V(v)             BM_I2C_CTRL0_RETAIN_CLOCK
+#define BP_I2C_CTRL0_POST_SEND_STOP                 20
+#define BM_I2C_CTRL0_POST_SEND_STOP                 0x100000
+#define BV_I2C_CTRL0_POST_SEND_STOP__NO_STOP        0x0
+#define BV_I2C_CTRL0_POST_SEND_STOP__SEND_STOP      0x1
+#define BF_I2C_CTRL0_POST_SEND_STOP(v)              (((v) & 0x1) << 20)
+#define BFM_I2C_CTRL0_POST_SEND_STOP(v)             BM_I2C_CTRL0_POST_SEND_STOP
+#define BF_I2C_CTRL0_POST_SEND_STOP_V(e)            BF_I2C_CTRL0_POST_SEND_STOP(BV_I2C_CTRL0_POST_SEND_STOP__##e)
+#define BFM_I2C_CTRL0_POST_SEND_STOP_V(v)           BM_I2C_CTRL0_POST_SEND_STOP
+#define BP_I2C_CTRL0_PRE_SEND_START                 19
+#define BM_I2C_CTRL0_PRE_SEND_START                 0x80000
+#define BV_I2C_CTRL0_PRE_SEND_START__NO_START       0x0
+#define BV_I2C_CTRL0_PRE_SEND_START__SEND_START     0x1
+#define BF_I2C_CTRL0_PRE_SEND_START(v)              (((v) & 0x1) << 19)
+#define BFM_I2C_CTRL0_PRE_SEND_START(v)             BM_I2C_CTRL0_PRE_SEND_START
+#define BF_I2C_CTRL0_PRE_SEND_START_V(e)            BF_I2C_CTRL0_PRE_SEND_START(BV_I2C_CTRL0_PRE_SEND_START__##e)
+#define BFM_I2C_CTRL0_PRE_SEND_START_V(v)           BM_I2C_CTRL0_PRE_SEND_START
+#define BP_I2C_CTRL0_SLAVE_ADDRESS_ENABLE           18
+#define BM_I2C_CTRL0_SLAVE_ADDRESS_ENABLE           0x40000
+#define BV_I2C_CTRL0_SLAVE_ADDRESS_ENABLE__DISABLED 0x0
+#define BV_I2C_CTRL0_SLAVE_ADDRESS_ENABLE__ENABLED  0x1
+#define BF_I2C_CTRL0_SLAVE_ADDRESS_ENABLE(v)        (((v) & 0x1) << 18)
+#define BFM_I2C_CTRL0_SLAVE_ADDRESS_ENABLE(v)       BM_I2C_CTRL0_SLAVE_ADDRESS_ENABLE
+#define BF_I2C_CTRL0_SLAVE_ADDRESS_ENABLE_V(e)      BF_I2C_CTRL0_SLAVE_ADDRESS_ENABLE(BV_I2C_CTRL0_SLAVE_ADDRESS_ENABLE__##e)
+#define BFM_I2C_CTRL0_SLAVE_ADDRESS_ENABLE_V(v)     BM_I2C_CTRL0_SLAVE_ADDRESS_ENABLE
+#define BP_I2C_CTRL0_MASTER_MODE                    17
+#define BM_I2C_CTRL0_MASTER_MODE                    0x20000
+#define BV_I2C_CTRL0_MASTER_MODE__SLAVE             0x0
+#define BV_I2C_CTRL0_MASTER_MODE__MASTER            0x1
+#define BF_I2C_CTRL0_MASTER_MODE(v)                 (((v) & 0x1) << 17)
+#define BFM_I2C_CTRL0_MASTER_MODE(v)                BM_I2C_CTRL0_MASTER_MODE
+#define BF_I2C_CTRL0_MASTER_MODE_V(e)               BF_I2C_CTRL0_MASTER_MODE(BV_I2C_CTRL0_MASTER_MODE__##e)
+#define BFM_I2C_CTRL0_MASTER_MODE_V(v)              BM_I2C_CTRL0_MASTER_MODE
+#define BP_I2C_CTRL0_DIRECTION                      16
+#define BM_I2C_CTRL0_DIRECTION                      0x10000
+#define BV_I2C_CTRL0_DIRECTION__RECEIVE             0x0
+#define BV_I2C_CTRL0_DIRECTION__TRANSMIT            0x1
+#define BF_I2C_CTRL0_DIRECTION(v)                   (((v) & 0x1) << 16)
+#define BFM_I2C_CTRL0_DIRECTION(v)                  BM_I2C_CTRL0_DIRECTION
+#define BF_I2C_CTRL0_DIRECTION_V(e)                 BF_I2C_CTRL0_DIRECTION(BV_I2C_CTRL0_DIRECTION__##e)
+#define BFM_I2C_CTRL0_DIRECTION_V(v)                BM_I2C_CTRL0_DIRECTION
+#define BP_I2C_CTRL0_XFER_COUNT                     0
+#define BM_I2C_CTRL0_XFER_COUNT                     0xffff
+#define BF_I2C_CTRL0_XFER_COUNT(v)                  (((v) & 0xffff) << 0)
+#define BFM_I2C_CTRL0_XFER_COUNT(v)                 BM_I2C_CTRL0_XFER_COUNT
+#define BF_I2C_CTRL0_XFER_COUNT_V(e)                BF_I2C_CTRL0_XFER_COUNT(BV_I2C_CTRL0_XFER_COUNT__##e)
+#define BFM_I2C_CTRL0_XFER_COUNT_V(v)               BM_I2C_CTRL0_XFER_COUNT
+
+#define HW_I2C_TIMING0                  HW(I2C_TIMING0)
+#define HWA_I2C_TIMING0                 (0x80058000 + 0x10)
+#define HWT_I2C_TIMING0                 HWIO_32_RW
+#define HWN_I2C_TIMING0                 I2C_TIMING0
+#define HWI_I2C_TIMING0                 
+#define HW_I2C_TIMING0_SET              HW(I2C_TIMING0_SET)
+#define HWA_I2C_TIMING0_SET             (HWA_I2C_TIMING0 + 0x4)
+#define HWT_I2C_TIMING0_SET             HWIO_32_WO
+#define HWN_I2C_TIMING0_SET             I2C_TIMING0
+#define HWI_I2C_TIMING0_SET             
+#define HW_I2C_TIMING0_CLR              HW(I2C_TIMING0_CLR)
+#define HWA_I2C_TIMING0_CLR             (HWA_I2C_TIMING0 + 0x8)
+#define HWT_I2C_TIMING0_CLR             HWIO_32_WO
+#define HWN_I2C_TIMING0_CLR             I2C_TIMING0
+#define HWI_I2C_TIMING0_CLR             
+#define HW_I2C_TIMING0_TOG              HW(I2C_TIMING0_TOG)
+#define HWA_I2C_TIMING0_TOG             (HWA_I2C_TIMING0 + 0xc)
+#define HWT_I2C_TIMING0_TOG             HWIO_32_WO
+#define HWN_I2C_TIMING0_TOG             I2C_TIMING0
+#define HWI_I2C_TIMING0_TOG             
+#define BP_I2C_TIMING0_HIGH_COUNT       16
+#define BM_I2C_TIMING0_HIGH_COUNT       0x3ff0000
+#define BF_I2C_TIMING0_HIGH_COUNT(v)    (((v) & 0x3ff) << 16)
+#define BFM_I2C_TIMING0_HIGH_COUNT(v)   BM_I2C_TIMING0_HIGH_COUNT
+#define BF_I2C_TIMING0_HIGH_COUNT_V(e)  BF_I2C_TIMING0_HIGH_COUNT(BV_I2C_TIMING0_HIGH_COUNT__##e)
+#define BFM_I2C_TIMING0_HIGH_COUNT_V(v) BM_I2C_TIMING0_HIGH_COUNT
+#define BP_I2C_TIMING0_RCV_COUNT        0
+#define BM_I2C_TIMING0_RCV_COUNT        0x3ff
+#define BF_I2C_TIMING0_RCV_COUNT(v)     (((v) & 0x3ff) << 0)
+#define BFM_I2C_TIMING0_RCV_COUNT(v)    BM_I2C_TIMING0_RCV_COUNT
+#define BF_I2C_TIMING0_RCV_COUNT_V(e)   BF_I2C_TIMING0_RCV_COUNT(BV_I2C_TIMING0_RCV_COUNT__##e)
+#define BFM_I2C_TIMING0_RCV_COUNT_V(v)  BM_I2C_TIMING0_RCV_COUNT
+
+#define HW_I2C_TIMING1                  HW(I2C_TIMING1)
+#define HWA_I2C_TIMING1                 (0x80058000 + 0x20)
+#define HWT_I2C_TIMING1                 HWIO_32_RW
+#define HWN_I2C_TIMING1                 I2C_TIMING1
+#define HWI_I2C_TIMING1                 
+#define HW_I2C_TIMING1_SET              HW(I2C_TIMING1_SET)
+#define HWA_I2C_TIMING1_SET             (HWA_I2C_TIMING1 + 0x4)
+#define HWT_I2C_TIMING1_SET             HWIO_32_WO
+#define HWN_I2C_TIMING1_SET             I2C_TIMING1
+#define HWI_I2C_TIMING1_SET             
+#define HW_I2C_TIMING1_CLR              HW(I2C_TIMING1_CLR)
+#define HWA_I2C_TIMING1_CLR             (HWA_I2C_TIMING1 + 0x8)
+#define HWT_I2C_TIMING1_CLR             HWIO_32_WO
+#define HWN_I2C_TIMING1_CLR             I2C_TIMING1
+#define HWI_I2C_TIMING1_CLR             
+#define HW_I2C_TIMING1_TOG              HW(I2C_TIMING1_TOG)
+#define HWA_I2C_TIMING1_TOG             (HWA_I2C_TIMING1 + 0xc)
+#define HWT_I2C_TIMING1_TOG             HWIO_32_WO
+#define HWN_I2C_TIMING1_TOG             I2C_TIMING1
+#define HWI_I2C_TIMING1_TOG             
+#define BP_I2C_TIMING1_LOW_COUNT        16
+#define BM_I2C_TIMING1_LOW_COUNT        0x3ff0000
+#define BF_I2C_TIMING1_LOW_COUNT(v)     (((v) & 0x3ff) << 16)
+#define BFM_I2C_TIMING1_LOW_COUNT(v)    BM_I2C_TIMING1_LOW_COUNT
+#define BF_I2C_TIMING1_LOW_COUNT_V(e)   BF_I2C_TIMING1_LOW_COUNT(BV_I2C_TIMING1_LOW_COUNT__##e)
+#define BFM_I2C_TIMING1_LOW_COUNT_V(v)  BM_I2C_TIMING1_LOW_COUNT
+#define BP_I2C_TIMING1_XMIT_COUNT       0
+#define BM_I2C_TIMING1_XMIT_COUNT       0x3ff
+#define BF_I2C_TIMING1_XMIT_COUNT(v)    (((v) & 0x3ff) << 0)
+#define BFM_I2C_TIMING1_XMIT_COUNT(v)   BM_I2C_TIMING1_XMIT_COUNT
+#define BF_I2C_TIMING1_XMIT_COUNT_V(e)  BF_I2C_TIMING1_XMIT_COUNT(BV_I2C_TIMING1_XMIT_COUNT__##e)
+#define BFM_I2C_TIMING1_XMIT_COUNT_V(v) BM_I2C_TIMING1_XMIT_COUNT
+
+#define HW_I2C_TIMING2                      HW(I2C_TIMING2)
+#define HWA_I2C_TIMING2                     (0x80058000 + 0x30)
+#define HWT_I2C_TIMING2                     HWIO_32_RW
+#define HWN_I2C_TIMING2                     I2C_TIMING2
+#define HWI_I2C_TIMING2                     
+#define HW_I2C_TIMING2_SET                  HW(I2C_TIMING2_SET)
+#define HWA_I2C_TIMING2_SET                 (HWA_I2C_TIMING2 + 0x4)
+#define HWT_I2C_TIMING2_SET                 HWIO_32_WO
+#define HWN_I2C_TIMING2_SET                 I2C_TIMING2
+#define HWI_I2C_TIMING2_SET                 
+#define HW_I2C_TIMING2_CLR                  HW(I2C_TIMING2_CLR)
+#define HWA_I2C_TIMING2_CLR                 (HWA_I2C_TIMING2 + 0x8)
+#define HWT_I2C_TIMING2_CLR                 HWIO_32_WO
+#define HWN_I2C_TIMING2_CLR                 I2C_TIMING2
+#define HWI_I2C_TIMING2_CLR                 
+#define HW_I2C_TIMING2_TOG                  HW(I2C_TIMING2_TOG)
+#define HWA_I2C_TIMING2_TOG                 (HWA_I2C_TIMING2 + 0xc)
+#define HWT_I2C_TIMING2_TOG                 HWIO_32_WO
+#define HWN_I2C_TIMING2_TOG                 I2C_TIMING2
+#define HWI_I2C_TIMING2_TOG                 
+#define BP_I2C_TIMING2_BUS_FREE             16
+#define BM_I2C_TIMING2_BUS_FREE             0x3ff0000
+#define BF_I2C_TIMING2_BUS_FREE(v)          (((v) & 0x3ff) << 16)
+#define BFM_I2C_TIMING2_BUS_FREE(v)         BM_I2C_TIMING2_BUS_FREE
+#define BF_I2C_TIMING2_BUS_FREE_V(e)        BF_I2C_TIMING2_BUS_FREE(BV_I2C_TIMING2_BUS_FREE__##e)
+#define BFM_I2C_TIMING2_BUS_FREE_V(v)       BM_I2C_TIMING2_BUS_FREE
+#define BP_I2C_TIMING2_LEADIN_COUNT         0
+#define BM_I2C_TIMING2_LEADIN_COUNT         0x3ff
+#define BF_I2C_TIMING2_LEADIN_COUNT(v)      (((v) & 0x3ff) << 0)
+#define BFM_I2C_TIMING2_LEADIN_COUNT(v)     BM_I2C_TIMING2_LEADIN_COUNT
+#define BF_I2C_TIMING2_LEADIN_COUNT_V(e)    BF_I2C_TIMING2_LEADIN_COUNT(BV_I2C_TIMING2_LEADIN_COUNT__##e)
+#define BFM_I2C_TIMING2_LEADIN_COUNT_V(v)   BM_I2C_TIMING2_LEADIN_COUNT
+
+#define HW_I2C_CTRL1                                        HW(I2C_CTRL1)
+#define HWA_I2C_CTRL1                                       (0x80058000 + 0x40)
+#define HWT_I2C_CTRL1                                       HWIO_32_RW
+#define HWN_I2C_CTRL1                                       I2C_CTRL1
+#define HWI_I2C_CTRL1                                       
+#define HW_I2C_CTRL1_SET                                    HW(I2C_CTRL1_SET)
+#define HWA_I2C_CTRL1_SET                                   (HWA_I2C_CTRL1 + 0x4)
+#define HWT_I2C_CTRL1_SET                                   HWIO_32_WO
+#define HWN_I2C_CTRL1_SET                                   I2C_CTRL1
+#define HWI_I2C_CTRL1_SET                                   
+#define HW_I2C_CTRL1_CLR                                    HW(I2C_CTRL1_CLR)
+#define HWA_I2C_CTRL1_CLR                                   (HWA_I2C_CTRL1 + 0x8)
+#define HWT_I2C_CTRL1_CLR                                   HWIO_32_WO
+#define HWN_I2C_CTRL1_CLR                                   I2C_CTRL1
+#define HWI_I2C_CTRL1_CLR                                   
+#define HW_I2C_CTRL1_TOG                                    HW(I2C_CTRL1_TOG)
+#define HWA_I2C_CTRL1_TOG                                   (HWA_I2C_CTRL1 + 0xc)
+#define HWT_I2C_CTRL1_TOG                                   HWIO_32_WO
+#define HWN_I2C_CTRL1_TOG                                   I2C_CTRL1
+#define HWI_I2C_CTRL1_TOG                                   
+#define BP_I2C_CTRL1_BCAST_SLAVE_EN                         24
+#define BM_I2C_CTRL1_BCAST_SLAVE_EN                         0x1000000
+#define BV_I2C_CTRL1_BCAST_SLAVE_EN__NO_BCAST               0x0
+#define BV_I2C_CTRL1_BCAST_SLAVE_EN__WATCH_BCAST            0x1
+#define BF_I2C_CTRL1_BCAST_SLAVE_EN(v)                      (((v) & 0x1) << 24)
+#define BFM_I2C_CTRL1_BCAST_SLAVE_EN(v)                     BM_I2C_CTRL1_BCAST_SLAVE_EN
+#define BF_I2C_CTRL1_BCAST_SLAVE_EN_V(e)                    BF_I2C_CTRL1_BCAST_SLAVE_EN(BV_I2C_CTRL1_BCAST_SLAVE_EN__##e)
+#define BFM_I2C_CTRL1_BCAST_SLAVE_EN_V(v)                   BM_I2C_CTRL1_BCAST_SLAVE_EN
+#define BP_I2C_CTRL1_SLAVE_ADDRESS_BYTE                     16
+#define BM_I2C_CTRL1_SLAVE_ADDRESS_BYTE                     0xff0000
+#define BF_I2C_CTRL1_SLAVE_ADDRESS_BYTE(v)                  (((v) & 0xff) << 16)
+#define BFM_I2C_CTRL1_SLAVE_ADDRESS_BYTE(v)                 BM_I2C_CTRL1_SLAVE_ADDRESS_BYTE
+#define BF_I2C_CTRL1_SLAVE_ADDRESS_BYTE_V(e)                BF_I2C_CTRL1_SLAVE_ADDRESS_BYTE(BV_I2C_CTRL1_SLAVE_ADDRESS_BYTE__##e)
+#define BFM_I2C_CTRL1_SLAVE_ADDRESS_BYTE_V(v)               BM_I2C_CTRL1_SLAVE_ADDRESS_BYTE
+#define BP_I2C_CTRL1_BUS_FREE_IRQ_EN                        15
+#define BM_I2C_CTRL1_BUS_FREE_IRQ_EN                        0x8000
+#define BV_I2C_CTRL1_BUS_FREE_IRQ_EN__DISABLED              0x0
+#define BV_I2C_CTRL1_BUS_FREE_IRQ_EN__ENABLED               0x1
+#define BF_I2C_CTRL1_BUS_FREE_IRQ_EN(v)                     (((v) & 0x1) << 15)
+#define BFM_I2C_CTRL1_BUS_FREE_IRQ_EN(v)                    BM_I2C_CTRL1_BUS_FREE_IRQ_EN
+#define BF_I2C_CTRL1_BUS_FREE_IRQ_EN_V(e)                   BF_I2C_CTRL1_BUS_FREE_IRQ_EN(BV_I2C_CTRL1_BUS_FREE_IRQ_EN__##e)
+#define BFM_I2C_CTRL1_BUS_FREE_IRQ_EN_V(v)                  BM_I2C_CTRL1_BUS_FREE_IRQ_EN
+#define BP_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN               14
+#define BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN               0x4000
+#define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN__DISABLED     0x0
+#define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN__ENABLED      0x1
+#define BF_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN(v)            (((v) & 0x1) << 14)
+#define BFM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN(v)           BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN
+#define BF_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN_V(e)          BF_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN(BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN__##e)
+#define BFM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN_V(v)         BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN
+#define BP_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN                    13
+#define BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN                    0x2000
+#define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN__DISABLED          0x0
+#define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN__ENABLED           0x1
+#define BF_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN(v)                 (((v) & 0x1) << 13)
+#define BFM_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN(v)                BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN
+#define BF_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN_V(e)               BF_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN(BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN__##e)
+#define BFM_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN_V(v)              BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN
+#define BP_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN              12
+#define BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN              0x1000
+#define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN__DISABLED    0x0
+#define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN__ENABLED     0x1
+#define BF_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN(v)           (((v) & 0x1) << 12)
+#define BFM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN(v)          BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN
+#define BF_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN_V(e)         BF_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN(BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN__##e)
+#define BFM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN_V(v)        BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN
+#define BP_I2C_CTRL1_EARLY_TERM_IRQ_EN                      11
+#define BM_I2C_CTRL1_EARLY_TERM_IRQ_EN                      0x800
+#define BV_I2C_CTRL1_EARLY_TERM_IRQ_EN__DISABLED            0x0
+#define BV_I2C_CTRL1_EARLY_TERM_IRQ_EN__ENABLED             0x1
+#define BF_I2C_CTRL1_EARLY_TERM_IRQ_EN(v)                   (((v) & 0x1) << 11)
+#define BFM_I2C_CTRL1_EARLY_TERM_IRQ_EN(v)                  BM_I2C_CTRL1_EARLY_TERM_IRQ_EN
+#define BF_I2C_CTRL1_EARLY_TERM_IRQ_EN_V(e)                 BF_I2C_CTRL1_EARLY_TERM_IRQ_EN(BV_I2C_CTRL1_EARLY_TERM_IRQ_EN__##e)
+#define BFM_I2C_CTRL1_EARLY_TERM_IRQ_EN_V(v)                BM_I2C_CTRL1_EARLY_TERM_IRQ_EN
+#define BP_I2C_CTRL1_MASTER_LOSS_IRQ_EN                     10
+#define BM_I2C_CTRL1_MASTER_LOSS_IRQ_EN                     0x400
+#define BV_I2C_CTRL1_MASTER_LOSS_IRQ_EN__DISABLED           0x0
+#define BV_I2C_CTRL1_MASTER_LOSS_IRQ_EN__ENABLED            0x1
+#define BF_I2C_CTRL1_MASTER_LOSS_IRQ_EN(v)                  (((v) & 0x1) << 10)
+#define BFM_I2C_CTRL1_MASTER_LOSS_IRQ_EN(v)                 BM_I2C_CTRL1_MASTER_LOSS_IRQ_EN
+#define BF_I2C_CTRL1_MASTER_LOSS_IRQ_EN_V(e)                BF_I2C_CTRL1_MASTER_LOSS_IRQ_EN(BV_I2C_CTRL1_MASTER_LOSS_IRQ_EN__##e)
+#define BFM_I2C_CTRL1_MASTER_LOSS_IRQ_EN_V(v)               BM_I2C_CTRL1_MASTER_LOSS_IRQ_EN
+#define BP_I2C_CTRL1_SLAVE_STOP_IRQ_EN                      9
+#define BM_I2C_CTRL1_SLAVE_STOP_IRQ_EN                      0x200
+#define BV_I2C_CTRL1_SLAVE_STOP_IRQ_EN__DISABLED            0x0
+#define BV_I2C_CTRL1_SLAVE_STOP_IRQ_EN__ENABLED             0x1
+#define BF_I2C_CTRL1_SLAVE_STOP_IRQ_EN(v)                   (((v) & 0x1) << 9)
+#define BFM_I2C_CTRL1_SLAVE_STOP_IRQ_EN(v)                  BM_I2C_CTRL1_SLAVE_STOP_IRQ_EN
+#define BF_I2C_CTRL1_SLAVE_STOP_IRQ_EN_V(e)                 BF_I2C_CTRL1_SLAVE_STOP_IRQ_EN(BV_I2C_CTRL1_SLAVE_STOP_IRQ_EN__##e)
+#define BFM_I2C_CTRL1_SLAVE_STOP_IRQ_EN_V(v)                BM_I2C_CTRL1_SLAVE_STOP_IRQ_EN
+#define BP_I2C_CTRL1_SLAVE_IRQ_EN                           8
+#define BM_I2C_CTRL1_SLAVE_IRQ_EN                           0x100
+#define BV_I2C_CTRL1_SLAVE_IRQ_EN__DISABLED                 0x0
+#define BV_I2C_CTRL1_SLAVE_IRQ_EN__ENABLED                  0x1
+#define BF_I2C_CTRL1_SLAVE_IRQ_EN(v)                        (((v) & 0x1) << 8)
+#define BFM_I2C_CTRL1_SLAVE_IRQ_EN(v)                       BM_I2C_CTRL1_SLAVE_IRQ_EN
+#define BF_I2C_CTRL1_SLAVE_IRQ_EN_V(e)                      BF_I2C_CTRL1_SLAVE_IRQ_EN(BV_I2C_CTRL1_SLAVE_IRQ_EN__##e)
+#define BFM_I2C_CTRL1_SLAVE_IRQ_EN_V(v)                     BM_I2C_CTRL1_SLAVE_IRQ_EN
+#define BP_I2C_CTRL1_BUS_FREE_IRQ                           7
+#define BM_I2C_CTRL1_BUS_FREE_IRQ                           0x80
+#define BV_I2C_CTRL1_BUS_FREE_IRQ__NO_REQUEST               0x0
+#define BV_I2C_CTRL1_BUS_FREE_IRQ__REQUEST                  0x1
+#define BF_I2C_CTRL1_BUS_FREE_IRQ(v)                        (((v) & 0x1) << 7)
+#define BFM_I2C_CTRL1_BUS_FREE_IRQ(v)                       BM_I2C_CTRL1_BUS_FREE_IRQ
+#define BF_I2C_CTRL1_BUS_FREE_IRQ_V(e)                      BF_I2C_CTRL1_BUS_FREE_IRQ(BV_I2C_CTRL1_BUS_FREE_IRQ__##e)
+#define BFM_I2C_CTRL1_BUS_FREE_IRQ_V(v)                     BM_I2C_CTRL1_BUS_FREE_IRQ
+#define BP_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ                  6
+#define BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ                  0x40
+#define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ__NO_REQUEST      0x0
+#define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ__REQUEST         0x1
+#define BF_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ(v)               (((v) & 0x1) << 6)
+#define BFM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ(v)              BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ
+#define BF_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_V(e)             BF_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ(BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ__##e)
+#define BFM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_V(v)            BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ
+#define BP_I2C_CTRL1_NO_SLAVE_ACK_IRQ                       5
+#define BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ                       0x20
+#define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ__NO_REQUEST           0x0
+#define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ__REQUEST              0x1
+#define BF_I2C_CTRL1_NO_SLAVE_ACK_IRQ(v)                    (((v) & 0x1) << 5)
+#define BFM_I2C_CTRL1_NO_SLAVE_ACK_IRQ(v)                   BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ
+#define BF_I2C_CTRL1_NO_SLAVE_ACK_IRQ_V(e)                  BF_I2C_CTRL1_NO_SLAVE_ACK_IRQ(BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ__##e)
+#define BFM_I2C_CTRL1_NO_SLAVE_ACK_IRQ_V(v)                 BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ
+#define BP_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ                 4
+#define BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ                 0x10
+#define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ__NO_REQUEST     0x0
+#define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ__REQUEST        0x1
+#define BF_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ(v)              (((v) & 0x1) << 4)
+#define BFM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ(v)             BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ
+#define BF_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_V(e)            BF_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ(BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ__##e)
+#define BFM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_V(v)           BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ
+#define BP_I2C_CTRL1_EARLY_TERM_IRQ                         3
+#define BM_I2C_CTRL1_EARLY_TERM_IRQ                         0x8
+#define BV_I2C_CTRL1_EARLY_TERM_IRQ__NO_REQUEST             0x0
+#define BV_I2C_CTRL1_EARLY_TERM_IRQ__REQUEST                0x1
+#define BF_I2C_CTRL1_EARLY_TERM_IRQ(v)                      (((v) & 0x1) << 3)
+#define BFM_I2C_CTRL1_EARLY_TERM_IRQ(v)                     BM_I2C_CTRL1_EARLY_TERM_IRQ
+#define BF_I2C_CTRL1_EARLY_TERM_IRQ_V(e)                    BF_I2C_CTRL1_EARLY_TERM_IRQ(BV_I2C_CTRL1_EARLY_TERM_IRQ__##e)
+#define BFM_I2C_CTRL1_EARLY_TERM_IRQ_V(v)                   BM_I2C_CTRL1_EARLY_TERM_IRQ
+#define BP_I2C_CTRL1_MASTER_LOSS_IRQ                        2
+#define BM_I2C_CTRL1_MASTER_LOSS_IRQ                        0x4
+#define BV_I2C_CTRL1_MASTER_LOSS_IRQ__NO_REQUEST            0x0
+#define BV_I2C_CTRL1_MASTER_LOSS_IRQ__REQUEST               0x1
+#define BF_I2C_CTRL1_MASTER_LOSS_IRQ(v)                     (((v) & 0x1) << 2)
+#define BFM_I2C_CTRL1_MASTER_LOSS_IRQ(v)                    BM_I2C_CTRL1_MASTER_LOSS_IRQ
+#define BF_I2C_CTRL1_MASTER_LOSS_IRQ_V(e)                   BF_I2C_CTRL1_MASTER_LOSS_IRQ(BV_I2C_CTRL1_MASTER_LOSS_IRQ__##e)
+#define BFM_I2C_CTRL1_MASTER_LOSS_IRQ_V(v)                  BM_I2C_CTRL1_MASTER_LOSS_IRQ
+#define BP_I2C_CTRL1_SLAVE_STOP_IRQ                         1
+#define BM_I2C_CTRL1_SLAVE_STOP_IRQ                         0x2
+#define BV_I2C_CTRL1_SLAVE_STOP_IRQ__NO_REQUEST             0x0
+#define BV_I2C_CTRL1_SLAVE_STOP_IRQ__REQUEST                0x1
+#define BF_I2C_CTRL1_SLAVE_STOP_IRQ(v)                      (((v) & 0x1) << 1)
+#define BFM_I2C_CTRL1_SLAVE_STOP_IRQ(v)                     BM_I2C_CTRL1_SLAVE_STOP_IRQ
+#define BF_I2C_CTRL1_SLAVE_STOP_IRQ_V(e)                    BF_I2C_CTRL1_SLAVE_STOP_IRQ(BV_I2C_CTRL1_SLAVE_STOP_IRQ__##e)
+#define BFM_I2C_CTRL1_SLAVE_STOP_IRQ_V(v)                   BM_I2C_CTRL1_SLAVE_STOP_IRQ
+#define BP_I2C_CTRL1_SLAVE_IRQ                              0
+#define BM_I2C_CTRL1_SLAVE_IRQ                              0x1
+#define BV_I2C_CTRL1_SLAVE_IRQ__NO_REQUEST                  0x0
+#define BV_I2C_CTRL1_SLAVE_IRQ__REQUEST                     0x1
+#define BF_I2C_CTRL1_SLAVE_IRQ(v)                           (((v) & 0x1) << 0)
+#define BFM_I2C_CTRL1_SLAVE_IRQ(v)                          BM_I2C_CTRL1_SLAVE_IRQ
+#define BF_I2C_CTRL1_SLAVE_IRQ_V(e)                         BF_I2C_CTRL1_SLAVE_IRQ(BV_I2C_CTRL1_SLAVE_IRQ__##e)
+#define BFM_I2C_CTRL1_SLAVE_IRQ_V(v)                        BM_I2C_CTRL1_SLAVE_IRQ
+
+#define HW_I2C_STAT                                             HW(I2C_STAT)
+#define HWA_I2C_STAT                                            (0x80058000 + 0x50)
+#define HWT_I2C_STAT                                            HWIO_32_RW
+#define HWN_I2C_STAT                                            I2C_STAT
+#define HWI_I2C_STAT                                            
+#define BP_I2C_STAT_MASTER_PRESENT                              31
+#define BM_I2C_STAT_MASTER_PRESENT                              0x80000000
+#define BV_I2C_STAT_MASTER_PRESENT__UNAVAILABLE                 0x0
+#define BV_I2C_STAT_MASTER_PRESENT__AVAILABLE                   0x1
+#define BF_I2C_STAT_MASTER_PRESENT(v)                           (((v) & 0x1) << 31)
+#define BFM_I2C_STAT_MASTER_PRESENT(v)                          BM_I2C_STAT_MASTER_PRESENT
+#define BF_I2C_STAT_MASTER_PRESENT_V(e)                         BF_I2C_STAT_MASTER_PRESENT(BV_I2C_STAT_MASTER_PRESENT__##e)
+#define BFM_I2C_STAT_MASTER_PRESENT_V(v)                        BM_I2C_STAT_MASTER_PRESENT
+#define BP_I2C_STAT_SLAVE_PRESENT                               30
+#define BM_I2C_STAT_SLAVE_PRESENT                               0x40000000
+#define BV_I2C_STAT_SLAVE_PRESENT__UNAVAILABLE                  0x0
+#define BV_I2C_STAT_SLAVE_PRESENT__AVAILABLE                    0x1
+#define BF_I2C_STAT_SLAVE_PRESENT(v)                            (((v) & 0x1) << 30)
+#define BFM_I2C_STAT_SLAVE_PRESENT(v)                           BM_I2C_STAT_SLAVE_PRESENT
+#define BF_I2C_STAT_SLAVE_PRESENT_V(e)                          BF_I2C_STAT_SLAVE_PRESENT(BV_I2C_STAT_SLAVE_PRESENT__##e)
+#define BFM_I2C_STAT_SLAVE_PRESENT_V(v)                         BM_I2C_STAT_SLAVE_PRESENT
+#define BP_I2C_STAT_ANY_ENABLED_IRQ                             29
+#define BM_I2C_STAT_ANY_ENABLED_IRQ                             0x20000000
+#define BV_I2C_STAT_ANY_ENABLED_IRQ__NO_REQUESTS                0x0
+#define BV_I2C_STAT_ANY_ENABLED_IRQ__AT_LEAST_ONE_REQUEST       0x1
+#define BF_I2C_STAT_ANY_ENABLED_IRQ(v)                          (((v) & 0x1) << 29)
+#define BFM_I2C_STAT_ANY_ENABLED_IRQ(v)                         BM_I2C_STAT_ANY_ENABLED_IRQ
+#define BF_I2C_STAT_ANY_ENABLED_IRQ_V(e)                        BF_I2C_STAT_ANY_ENABLED_IRQ(BV_I2C_STAT_ANY_ENABLED_IRQ__##e)
+#define BFM_I2C_STAT_ANY_ENABLED_IRQ_V(v)                       BM_I2C_STAT_ANY_ENABLED_IRQ
+#define BP_I2C_STAT_RCVD_SLAVE_ADDR                             16
+#define BM_I2C_STAT_RCVD_SLAVE_ADDR                             0xff0000
+#define BF_I2C_STAT_RCVD_SLAVE_ADDR(v)                          (((v) & 0xff) << 16)
+#define BFM_I2C_STAT_RCVD_SLAVE_ADDR(v)                         BM_I2C_STAT_RCVD_SLAVE_ADDR
+#define BF_I2C_STAT_RCVD_SLAVE_ADDR_V(e)                        BF_I2C_STAT_RCVD_SLAVE_ADDR(BV_I2C_STAT_RCVD_SLAVE_ADDR__##e)
+#define BFM_I2C_STAT_RCVD_SLAVE_ADDR_V(v)                       BM_I2C_STAT_RCVD_SLAVE_ADDR
+#define BP_I2C_STAT_SLAVE_ADDR_EQ_ZERO                          15
+#define BM_I2C_STAT_SLAVE_ADDR_EQ_ZERO                          0x8000
+#define BV_I2C_STAT_SLAVE_ADDR_EQ_ZERO__ZERO_NOT_MATCHED        0x0
+#define BV_I2C_STAT_SLAVE_ADDR_EQ_ZERO__WAS_ZERO                0x1
+#define BF_I2C_STAT_SLAVE_ADDR_EQ_ZERO(v)                       (((v) & 0x1) << 15)
+#define BFM_I2C_STAT_SLAVE_ADDR_EQ_ZERO(v)                      BM_I2C_STAT_SLAVE_ADDR_EQ_ZERO
+#define BF_I2C_STAT_SLAVE_ADDR_EQ_ZERO_V(e)                     BF_I2C_STAT_SLAVE_ADDR_EQ_ZERO(BV_I2C_STAT_SLAVE_ADDR_EQ_ZERO__##e)
+#define BFM_I2C_STAT_SLAVE_ADDR_EQ_ZERO_V(v)                    BM_I2C_STAT_SLAVE_ADDR_EQ_ZERO
+#define BP_I2C_STAT_SLAVE_FOUND                                 14
+#define BM_I2C_STAT_SLAVE_FOUND                                 0x4000
+#define BV_I2C_STAT_SLAVE_FOUND__IDLE                           0x0
+#define BV_I2C_STAT_SLAVE_FOUND__WAITING                        0x1
+#define BF_I2C_STAT_SLAVE_FOUND(v)                              (((v) & 0x1) << 14)
+#define BFM_I2C_STAT_SLAVE_FOUND(v)                             BM_I2C_STAT_SLAVE_FOUND
+#define BF_I2C_STAT_SLAVE_FOUND_V(e)                            BF_I2C_STAT_SLAVE_FOUND(BV_I2C_STAT_SLAVE_FOUND__##e)
+#define BFM_I2C_STAT_SLAVE_FOUND_V(v)                           BM_I2C_STAT_SLAVE_FOUND
+#define BP_I2C_STAT_SLAVE_SEARCHING                             13
+#define BM_I2C_STAT_SLAVE_SEARCHING                             0x2000
+#define BV_I2C_STAT_SLAVE_SEARCHING__IDLE                       0x0
+#define BV_I2C_STAT_SLAVE_SEARCHING__ACTIVE                     0x1
+#define BF_I2C_STAT_SLAVE_SEARCHING(v)                          (((v) & 0x1) << 13)
+#define BFM_I2C_STAT_SLAVE_SEARCHING(v)                         BM_I2C_STAT_SLAVE_SEARCHING
+#define BF_I2C_STAT_SLAVE_SEARCHING_V(e)                        BF_I2C_STAT_SLAVE_SEARCHING(BV_I2C_STAT_SLAVE_SEARCHING__##e)
+#define BFM_I2C_STAT_SLAVE_SEARCHING_V(v)                       BM_I2C_STAT_SLAVE_SEARCHING
+#define BP_I2C_STAT_DATA_ENGINE_DMA_WAIT                        12
+#define BM_I2C_STAT_DATA_ENGINE_DMA_WAIT                        0x1000
+#define BV_I2C_STAT_DATA_ENGINE_DMA_WAIT__CONTINUE              0x0
+#define BV_I2C_STAT_DATA_ENGINE_DMA_WAIT__WAITING               0x1
+#define BF_I2C_STAT_DATA_ENGINE_DMA_WAIT(v)                     (((v) & 0x1) << 12)
+#define BFM_I2C_STAT_DATA_ENGINE_DMA_WAIT(v)                    BM_I2C_STAT_DATA_ENGINE_DMA_WAIT
+#define BF_I2C_STAT_DATA_ENGINE_DMA_WAIT_V(e)                   BF_I2C_STAT_DATA_ENGINE_DMA_WAIT(BV_I2C_STAT_DATA_ENGINE_DMA_WAIT__##e)
+#define BFM_I2C_STAT_DATA_ENGINE_DMA_WAIT_V(v)                  BM_I2C_STAT_DATA_ENGINE_DMA_WAIT
+#define BP_I2C_STAT_BUS_BUSY                                    11
+#define BM_I2C_STAT_BUS_BUSY                                    0x800
+#define BV_I2C_STAT_BUS_BUSY__IDLE                              0x0
+#define BV_I2C_STAT_BUS_BUSY__BUSY                              0x1
+#define BF_I2C_STAT_BUS_BUSY(v)                                 (((v) & 0x1) << 11)
+#define BFM_I2C_STAT_BUS_BUSY(v)                                BM_I2C_STAT_BUS_BUSY
+#define BF_I2C_STAT_BUS_BUSY_V(e)                               BF_I2C_STAT_BUS_BUSY(BV_I2C_STAT_BUS_BUSY__##e)
+#define BFM_I2C_STAT_BUS_BUSY_V(v)                              BM_I2C_STAT_BUS_BUSY
+#define BP_I2C_STAT_CLK_GEN_BUSY                                10
+#define BM_I2C_STAT_CLK_GEN_BUSY                                0x400
+#define BV_I2C_STAT_CLK_GEN_BUSY__IDLE                          0x0
+#define BV_I2C_STAT_CLK_GEN_BUSY__BUSY                          0x1
+#define BF_I2C_STAT_CLK_GEN_BUSY(v)                             (((v) & 0x1) << 10)
+#define BFM_I2C_STAT_CLK_GEN_BUSY(v)                            BM_I2C_STAT_CLK_GEN_BUSY
+#define BF_I2C_STAT_CLK_GEN_BUSY_V(e)                           BF_I2C_STAT_CLK_GEN_BUSY(BV_I2C_STAT_CLK_GEN_BUSY__##e)
+#define BFM_I2C_STAT_CLK_GEN_BUSY_V(v)                          BM_I2C_STAT_CLK_GEN_BUSY
+#define BP_I2C_STAT_DATA_ENGINE_BUSY                            9
+#define BM_I2C_STAT_DATA_ENGINE_BUSY                            0x200
+#define BV_I2C_STAT_DATA_ENGINE_BUSY__IDLE                      0x0
+#define BV_I2C_STAT_DATA_ENGINE_BUSY__BUSY                      0x1
+#define BF_I2C_STAT_DATA_ENGINE_BUSY(v)                         (((v) & 0x1) << 9)
+#define BFM_I2C_STAT_DATA_ENGINE_BUSY(v)                        BM_I2C_STAT_DATA_ENGINE_BUSY
+#define BF_I2C_STAT_DATA_ENGINE_BUSY_V(e)                       BF_I2C_STAT_DATA_ENGINE_BUSY(BV_I2C_STAT_DATA_ENGINE_BUSY__##e)
+#define BFM_I2C_STAT_DATA_ENGINE_BUSY_V(v)                      BM_I2C_STAT_DATA_ENGINE_BUSY
+#define BP_I2C_STAT_SLAVE_BUSY                                  8
+#define BM_I2C_STAT_SLAVE_BUSY                                  0x100
+#define BV_I2C_STAT_SLAVE_BUSY__IDLE                            0x0
+#define BV_I2C_STAT_SLAVE_BUSY__BUSY                            0x1
+#define BF_I2C_STAT_SLAVE_BUSY(v)                               (((v) & 0x1) << 8)
+#define BFM_I2C_STAT_SLAVE_BUSY(v)                              BM_I2C_STAT_SLAVE_BUSY
+#define BF_I2C_STAT_SLAVE_BUSY_V(e)                             BF_I2C_STAT_SLAVE_BUSY(BV_I2C_STAT_SLAVE_BUSY__##e)
+#define BFM_I2C_STAT_SLAVE_BUSY_V(v)                            BM_I2C_STAT_SLAVE_BUSY
+#define BP_I2C_STAT_BUS_FREE_IRQ_SUMMARY                        7
+#define BM_I2C_STAT_BUS_FREE_IRQ_SUMMARY                        0x80
+#define BV_I2C_STAT_BUS_FREE_IRQ_SUMMARY__NO_REQUEST            0x0
+#define BV_I2C_STAT_BUS_FREE_IRQ_SUMMARY__REQUEST               0x1
+#define BF_I2C_STAT_BUS_FREE_IRQ_SUMMARY(v)                     (((v) & 0x1) << 7)
+#define BFM_I2C_STAT_BUS_FREE_IRQ_SUMMARY(v)                    BM_I2C_STAT_BUS_FREE_IRQ_SUMMARY
+#define BF_I2C_STAT_BUS_FREE_IRQ_SUMMARY_V(e)                   BF_I2C_STAT_BUS_FREE_IRQ_SUMMARY(BV_I2C_STAT_BUS_FREE_IRQ_SUMMARY__##e)
+#define BFM_I2C_STAT_BUS_FREE_IRQ_SUMMARY_V(v)                  BM_I2C_STAT_BUS_FREE_IRQ_SUMMARY
+#define BP_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY               6
+#define BM_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY               0x40
+#define BV_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY__NO_REQUEST   0x0
+#define BV_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY__REQUEST      0x1
+#define BF_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY(v)            (((v) & 0x1) << 6)
+#define BFM_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY(v)           BM_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY
+#define BF_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY_V(e)          BF_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY(BV_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY__##e)
+#define BFM_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY_V(v)         BM_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY
+#define BP_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY                    5
+#define BM_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY                    0x20
+#define BV_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY__NO_REQUEST        0x0
+#define BV_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY__REQUEST           0x1
+#define BF_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY(v)                 (((v) & 0x1) << 5)
+#define BFM_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY(v)                BM_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY
+#define BF_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY_V(e)               BF_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY(BV_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY__##e)
+#define BFM_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY_V(v)              BM_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY
+#define BP_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY              4
+#define BM_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY              0x10
+#define BV_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY__NO_REQUEST  0x0
+#define BV_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY__REQUEST     0x1
+#define BF_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY(v)           (((v) & 0x1) << 4)
+#define BFM_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY(v)          BM_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY
+#define BF_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY_V(e)         BF_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY(BV_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY__##e)
+#define BFM_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY_V(v)        BM_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY
+#define BP_I2C_STAT_EARLY_TERM_IRQ_SUMMARY                      3
+#define BM_I2C_STAT_EARLY_TERM_IRQ_SUMMARY                      0x8
+#define BV_I2C_STAT_EARLY_TERM_IRQ_SUMMARY__NO_REQUEST          0x0
+#define BV_I2C_STAT_EARLY_TERM_IRQ_SUMMARY__REQUEST             0x1
+#define BF_I2C_STAT_EARLY_TERM_IRQ_SUMMARY(v)                   (((v) & 0x1) << 3)
+#define BFM_I2C_STAT_EARLY_TERM_IRQ_SUMMARY(v)                  BM_I2C_STAT_EARLY_TERM_IRQ_SUMMARY
+#define BF_I2C_STAT_EARLY_TERM_IRQ_SUMMARY_V(e)                 BF_I2C_STAT_EARLY_TERM_IRQ_SUMMARY(BV_I2C_STAT_EARLY_TERM_IRQ_SUMMARY__##e)
+#define BFM_I2C_STAT_EARLY_TERM_IRQ_SUMMARY_V(v)                BM_I2C_STAT_EARLY_TERM_IRQ_SUMMARY
+#define BP_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY                     2
+#define BM_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY                     0x4
+#define BV_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY__NO_REQUEST         0x0
+#define BV_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY__REQUEST            0x1
+#define BF_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY(v)                  (((v) & 0x1) << 2)
+#define BFM_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY(v)                 BM_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY
+#define BF_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY_V(e)                BF_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY(BV_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY__##e)
+#define BFM_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY_V(v)               BM_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY
+#define BP_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY                      1
+#define BM_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY                      0x2
+#define BV_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY__NO_REQUEST          0x0
+#define BV_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY__REQUEST             0x1
+#define BF_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY(v)                   (((v) & 0x1) << 1)
+#define BFM_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY(v)                  BM_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY
+#define BF_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY_V(e)                 BF_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY(BV_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY__##e)
+#define BFM_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY_V(v)                BM_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY
+#define BP_I2C_STAT_SLAVE_IRQ_SUMMARY                           0
+#define BM_I2C_STAT_SLAVE_IRQ_SUMMARY                           0x1
+#define BV_I2C_STAT_SLAVE_IRQ_SUMMARY__NO_REQUEST               0x0
+#define BV_I2C_STAT_SLAVE_IRQ_SUMMARY__REQUEST                  0x1
+#define BF_I2C_STAT_SLAVE_IRQ_SUMMARY(v)                        (((v) & 0x1) << 0)
+#define BFM_I2C_STAT_SLAVE_IRQ_SUMMARY(v)                       BM_I2C_STAT_SLAVE_IRQ_SUMMARY
+#define BF_I2C_STAT_SLAVE_IRQ_SUMMARY_V(e)                      BF_I2C_STAT_SLAVE_IRQ_SUMMARY(BV_I2C_STAT_SLAVE_IRQ_SUMMARY__##e)
+#define BFM_I2C_STAT_SLAVE_IRQ_SUMMARY_V(v)                     BM_I2C_STAT_SLAVE_IRQ_SUMMARY
+
+#define HW_I2C_DATA             HW(I2C_DATA)
+#define HWA_I2C_DATA            (0x80058000 + 0x60)
+#define HWT_I2C_DATA            HWIO_32_RW
+#define HWN_I2C_DATA            I2C_DATA
+#define HWI_I2C_DATA            
+#define BP_I2C_DATA_DATA        0
+#define BM_I2C_DATA_DATA        0xffffffff
+#define BF_I2C_DATA_DATA(v)     (((v) & 0xffffffff) << 0)
+#define BFM_I2C_DATA_DATA(v)    BM_I2C_DATA_DATA
+#define BF_I2C_DATA_DATA_V(e)   BF_I2C_DATA_DATA(BV_I2C_DATA_DATA__##e)
+#define BFM_I2C_DATA_DATA_V(v)  BM_I2C_DATA_DATA
+
+#define HW_I2C_DEBUG0                       HW(I2C_DEBUG0)
+#define HWA_I2C_DEBUG0                      (0x80058000 + 0x70)
+#define HWT_I2C_DEBUG0                      HWIO_32_RW
+#define HWN_I2C_DEBUG0                      I2C_DEBUG0
+#define HWI_I2C_DEBUG0                      
+#define HW_I2C_DEBUG0_SET                   HW(I2C_DEBUG0_SET)
+#define HWA_I2C_DEBUG0_SET                  (HWA_I2C_DEBUG0 + 0x4)
+#define HWT_I2C_DEBUG0_SET                  HWIO_32_WO
+#define HWN_I2C_DEBUG0_SET                  I2C_DEBUG0
+#define HWI_I2C_DEBUG0_SET                  
+#define HW_I2C_DEBUG0_CLR                   HW(I2C_DEBUG0_CLR)
+#define HWA_I2C_DEBUG0_CLR                  (HWA_I2C_DEBUG0 + 0x8)
+#define HWT_I2C_DEBUG0_CLR                  HWIO_32_WO
+#define HWN_I2C_DEBUG0_CLR                  I2C_DEBUG0
+#define HWI_I2C_DEBUG0_CLR                  
+#define HW_I2C_DEBUG0_TOG                   HW(I2C_DEBUG0_TOG)
+#define HWA_I2C_DEBUG0_TOG                  (HWA_I2C_DEBUG0 + 0xc)
+#define HWT_I2C_DEBUG0_TOG                  HWIO_32_WO
+#define HWN_I2C_DEBUG0_TOG                  I2C_DEBUG0
+#define HWI_I2C_DEBUG0_TOG                  
+#define BP_I2C_DEBUG0_DMAREQ                31
+#define BM_I2C_DEBUG0_DMAREQ                0x80000000
+#define BF_I2C_DEBUG0_DMAREQ(v)             (((v) & 0x1) << 31)
+#define BFM_I2C_DEBUG0_DMAREQ(v)            BM_I2C_DEBUG0_DMAREQ
+#define BF_I2C_DEBUG0_DMAREQ_V(e)           BF_I2C_DEBUG0_DMAREQ(BV_I2C_DEBUG0_DMAREQ__##e)
+#define BFM_I2C_DEBUG0_DMAREQ_V(v)          BM_I2C_DEBUG0_DMAREQ
+#define BP_I2C_DEBUG0_DMAENDCMD             30
+#define BM_I2C_DEBUG0_DMAENDCMD             0x40000000
+#define BF_I2C_DEBUG0_DMAENDCMD(v)          (((v) & 0x1) << 30)
+#define BFM_I2C_DEBUG0_DMAENDCMD(v)         BM_I2C_DEBUG0_DMAENDCMD
+#define BF_I2C_DEBUG0_DMAENDCMD_V(e)        BF_I2C_DEBUG0_DMAENDCMD(BV_I2C_DEBUG0_DMAENDCMD__##e)
+#define BFM_I2C_DEBUG0_DMAENDCMD_V(v)       BM_I2C_DEBUG0_DMAENDCMD
+#define BP_I2C_DEBUG0_DMAKICK               29
+#define BM_I2C_DEBUG0_DMAKICK               0x20000000
+#define BF_I2C_DEBUG0_DMAKICK(v)            (((v) & 0x1) << 29)
+#define BFM_I2C_DEBUG0_DMAKICK(v)           BM_I2C_DEBUG0_DMAKICK
+#define BF_I2C_DEBUG0_DMAKICK_V(e)          BF_I2C_DEBUG0_DMAKICK(BV_I2C_DEBUG0_DMAKICK__##e)
+#define BFM_I2C_DEBUG0_DMAKICK_V(v)         BM_I2C_DEBUG0_DMAKICK
+#define BP_I2C_DEBUG0_TBD                   26
+#define BM_I2C_DEBUG0_TBD                   0x1c000000
+#define BF_I2C_DEBUG0_TBD(v)                (((v) & 0x7) << 26)
+#define BFM_I2C_DEBUG0_TBD(v)               BM_I2C_DEBUG0_TBD
+#define BF_I2C_DEBUG0_TBD_V(e)              BF_I2C_DEBUG0_TBD(BV_I2C_DEBUG0_TBD__##e)
+#define BFM_I2C_DEBUG0_TBD_V(v)             BM_I2C_DEBUG0_TBD
+#define BP_I2C_DEBUG0_DMA_STATE             16
+#define BM_I2C_DEBUG0_DMA_STATE             0x3ff0000
+#define BF_I2C_DEBUG0_DMA_STATE(v)          (((v) & 0x3ff) << 16)
+#define BFM_I2C_DEBUG0_DMA_STATE(v)         BM_I2C_DEBUG0_DMA_STATE
+#define BF_I2C_DEBUG0_DMA_STATE_V(e)        BF_I2C_DEBUG0_DMA_STATE(BV_I2C_DEBUG0_DMA_STATE__##e)
+#define BFM_I2C_DEBUG0_DMA_STATE_V(v)       BM_I2C_DEBUG0_DMA_STATE
+#define BP_I2C_DEBUG0_START_TOGGLE          15
+#define BM_I2C_DEBUG0_START_TOGGLE          0x8000
+#define BF_I2C_DEBUG0_START_TOGGLE(v)       (((v) & 0x1) << 15)
+#define BFM_I2C_DEBUG0_START_TOGGLE(v)      BM_I2C_DEBUG0_START_TOGGLE
+#define BF_I2C_DEBUG0_START_TOGGLE_V(e)     BF_I2C_DEBUG0_START_TOGGLE(BV_I2C_DEBUG0_START_TOGGLE__##e)
+#define BFM_I2C_DEBUG0_START_TOGGLE_V(v)    BM_I2C_DEBUG0_START_TOGGLE
+#define BP_I2C_DEBUG0_STOP_TOGGLE           14
+#define BM_I2C_DEBUG0_STOP_TOGGLE           0x4000
+#define BF_I2C_DEBUG0_STOP_TOGGLE(v)        (((v) & 0x1) << 14)
+#define BFM_I2C_DEBUG0_STOP_TOGGLE(v)       BM_I2C_DEBUG0_STOP_TOGGLE
+#define BF_I2C_DEBUG0_STOP_TOGGLE_V(e)      BF_I2C_DEBUG0_STOP_TOGGLE(BV_I2C_DEBUG0_STOP_TOGGLE__##e)
+#define BFM_I2C_DEBUG0_STOP_TOGGLE_V(v)     BM_I2C_DEBUG0_STOP_TOGGLE
+#define BP_I2C_DEBUG0_GRAB_TOGGLE           13
+#define BM_I2C_DEBUG0_GRAB_TOGGLE           0x2000
+#define BF_I2C_DEBUG0_GRAB_TOGGLE(v)        (((v) & 0x1) << 13)
+#define BFM_I2C_DEBUG0_GRAB_TOGGLE(v)       BM_I2C_DEBUG0_GRAB_TOGGLE
+#define BF_I2C_DEBUG0_GRAB_TOGGLE_V(e)      BF_I2C_DEBUG0_GRAB_TOGGLE(BV_I2C_DEBUG0_GRAB_TOGGLE__##e)
+#define BFM_I2C_DEBUG0_GRAB_TOGGLE_V(v)     BM_I2C_DEBUG0_GRAB_TOGGLE
+#define BP_I2C_DEBUG0_CHANGE_TOGGLE         12
+#define BM_I2C_DEBUG0_CHANGE_TOGGLE         0x1000
+#define BF_I2C_DEBUG0_CHANGE_TOGGLE(v)      (((v) & 0x1) << 12)
+#define BFM_I2C_DEBUG0_CHANGE_TOGGLE(v)     BM_I2C_DEBUG0_CHANGE_TOGGLE
+#define BF_I2C_DEBUG0_CHANGE_TOGGLE_V(e)    BF_I2C_DEBUG0_CHANGE_TOGGLE(BV_I2C_DEBUG0_CHANGE_TOGGLE__##e)
+#define BFM_I2C_DEBUG0_CHANGE_TOGGLE_V(v)   BM_I2C_DEBUG0_CHANGE_TOGGLE
+#define BP_I2C_DEBUG0_TESTMODE              11
+#define BM_I2C_DEBUG0_TESTMODE              0x800
+#define BF_I2C_DEBUG0_TESTMODE(v)           (((v) & 0x1) << 11)
+#define BFM_I2C_DEBUG0_TESTMODE(v)          BM_I2C_DEBUG0_TESTMODE
+#define BF_I2C_DEBUG0_TESTMODE_V(e)         BF_I2C_DEBUG0_TESTMODE(BV_I2C_DEBUG0_TESTMODE__##e)
+#define BFM_I2C_DEBUG0_TESTMODE_V(v)        BM_I2C_DEBUG0_TESTMODE
+#define BP_I2C_DEBUG0_SLAVE_HOLD_CLK        10
+#define BM_I2C_DEBUG0_SLAVE_HOLD_CLK        0x400
+#define BF_I2C_DEBUG0_SLAVE_HOLD_CLK(v)     (((v) & 0x1) << 10)
+#define BFM_I2C_DEBUG0_SLAVE_HOLD_CLK(v)    BM_I2C_DEBUG0_SLAVE_HOLD_CLK
+#define BF_I2C_DEBUG0_SLAVE_HOLD_CLK_V(e)   BF_I2C_DEBUG0_SLAVE_HOLD_CLK(BV_I2C_DEBUG0_SLAVE_HOLD_CLK__##e)
+#define BFM_I2C_DEBUG0_SLAVE_HOLD_CLK_V(v)  BM_I2C_DEBUG0_SLAVE_HOLD_CLK
+#define BP_I2C_DEBUG0_SLAVE_STATE           0
+#define BM_I2C_DEBUG0_SLAVE_STATE           0x3ff
+#define BF_I2C_DEBUG0_SLAVE_STATE(v)        (((v) & 0x3ff) << 0)
+#define BFM_I2C_DEBUG0_SLAVE_STATE(v)       BM_I2C_DEBUG0_SLAVE_STATE
+#define BF_I2C_DEBUG0_SLAVE_STATE_V(e)      BF_I2C_DEBUG0_SLAVE_STATE(BV_I2C_DEBUG0_SLAVE_STATE__##e)
+#define BFM_I2C_DEBUG0_SLAVE_STATE_V(v)     BM_I2C_DEBUG0_SLAVE_STATE
+
+#define HW_I2C_DEBUG1                           HW(I2C_DEBUG1)
+#define HWA_I2C_DEBUG1                          (0x80058000 + 0x80)
+#define HWT_I2C_DEBUG1                          HWIO_32_RW
+#define HWN_I2C_DEBUG1                          I2C_DEBUG1
+#define HWI_I2C_DEBUG1                          
+#define HW_I2C_DEBUG1_SET                       HW(I2C_DEBUG1_SET)
+#define HWA_I2C_DEBUG1_SET                      (HWA_I2C_DEBUG1 + 0x4)
+#define HWT_I2C_DEBUG1_SET                      HWIO_32_WO
+#define HWN_I2C_DEBUG1_SET                      I2C_DEBUG1
+#define HWI_I2C_DEBUG1_SET                      
+#define HW_I2C_DEBUG1_CLR                       HW(I2C_DEBUG1_CLR)
+#define HWA_I2C_DEBUG1_CLR                      (HWA_I2C_DEBUG1 + 0x8)
+#define HWT_I2C_DEBUG1_CLR                      HWIO_32_WO
+#define HWN_I2C_DEBUG1_CLR                      I2C_DEBUG1
+#define HWI_I2C_DEBUG1_CLR                      
+#define HW_I2C_DEBUG1_TOG                       HW(I2C_DEBUG1_TOG)
+#define HWA_I2C_DEBUG1_TOG                      (HWA_I2C_DEBUG1 + 0xc)
+#define HWT_I2C_DEBUG1_TOG                      HWIO_32_WO
+#define HWN_I2C_DEBUG1_TOG                      I2C_DEBUG1
+#define HWI_I2C_DEBUG1_TOG                      
+#define BP_I2C_DEBUG1_I2C_CLK_IN                31
+#define BM_I2C_DEBUG1_I2C_CLK_IN                0x80000000
+#define BF_I2C_DEBUG1_I2C_CLK_IN(v)             (((v) & 0x1) << 31)
+#define BFM_I2C_DEBUG1_I2C_CLK_IN(v)            BM_I2C_DEBUG1_I2C_CLK_IN
+#define BF_I2C_DEBUG1_I2C_CLK_IN_V(e)           BF_I2C_DEBUG1_I2C_CLK_IN(BV_I2C_DEBUG1_I2C_CLK_IN__##e)
+#define BFM_I2C_DEBUG1_I2C_CLK_IN_V(v)          BM_I2C_DEBUG1_I2C_CLK_IN
+#define BP_I2C_DEBUG1_I2C_DATA_IN               30
+#define BM_I2C_DEBUG1_I2C_DATA_IN               0x40000000
+#define BF_I2C_DEBUG1_I2C_DATA_IN(v)            (((v) & 0x1) << 30)
+#define BFM_I2C_DEBUG1_I2C_DATA_IN(v)           BM_I2C_DEBUG1_I2C_DATA_IN
+#define BF_I2C_DEBUG1_I2C_DATA_IN_V(e)          BF_I2C_DEBUG1_I2C_DATA_IN(BV_I2C_DEBUG1_I2C_DATA_IN__##e)
+#define BFM_I2C_DEBUG1_I2C_DATA_IN_V(v)         BM_I2C_DEBUG1_I2C_DATA_IN
+#define BP_I2C_DEBUG1_DMA_BYTE_ENABLES          24
+#define BM_I2C_DEBUG1_DMA_BYTE_ENABLES          0xf000000
+#define BF_I2C_DEBUG1_DMA_BYTE_ENABLES(v)       (((v) & 0xf) << 24)
+#define BFM_I2C_DEBUG1_DMA_BYTE_ENABLES(v)      BM_I2C_DEBUG1_DMA_BYTE_ENABLES
+#define BF_I2C_DEBUG1_DMA_BYTE_ENABLES_V(e)     BF_I2C_DEBUG1_DMA_BYTE_ENABLES(BV_I2C_DEBUG1_DMA_BYTE_ENABLES__##e)
+#define BFM_I2C_DEBUG1_DMA_BYTE_ENABLES_V(v)    BM_I2C_DEBUG1_DMA_BYTE_ENABLES
+#define BP_I2C_DEBUG1_CLK_GEN_STATE             16
+#define BM_I2C_DEBUG1_CLK_GEN_STATE             0x7f0000
+#define BF_I2C_DEBUG1_CLK_GEN_STATE(v)          (((v) & 0x7f) << 16)
+#define BFM_I2C_DEBUG1_CLK_GEN_STATE(v)         BM_I2C_DEBUG1_CLK_GEN_STATE
+#define BF_I2C_DEBUG1_CLK_GEN_STATE_V(e)        BF_I2C_DEBUG1_CLK_GEN_STATE(BV_I2C_DEBUG1_CLK_GEN_STATE__##e)
+#define BFM_I2C_DEBUG1_CLK_GEN_STATE_V(v)       BM_I2C_DEBUG1_CLK_GEN_STATE
+#define BP_I2C_DEBUG1_LST_MODE                  9
+#define BM_I2C_DEBUG1_LST_MODE                  0x600
+#define BV_I2C_DEBUG1_LST_MODE__BCAST           0x0
+#define BV_I2C_DEBUG1_LST_MODE__MY_WRITE        0x1
+#define BV_I2C_DEBUG1_LST_MODE__MY_READ         0x2
+#define BV_I2C_DEBUG1_LST_MODE__NOT_ME          0x3
+#define BF_I2C_DEBUG1_LST_MODE(v)               (((v) & 0x3) << 9)
+#define BFM_I2C_DEBUG1_LST_MODE(v)              BM_I2C_DEBUG1_LST_MODE
+#define BF_I2C_DEBUG1_LST_MODE_V(e)             BF_I2C_DEBUG1_LST_MODE(BV_I2C_DEBUG1_LST_MODE__##e)
+#define BFM_I2C_DEBUG1_LST_MODE_V(v)            BM_I2C_DEBUG1_LST_MODE
+#define BP_I2C_DEBUG1_LOCAL_SLAVE_TEST          8
+#define BM_I2C_DEBUG1_LOCAL_SLAVE_TEST          0x100
+#define BF_I2C_DEBUG1_LOCAL_SLAVE_TEST(v)       (((v) & 0x1) << 8)
+#define BFM_I2C_DEBUG1_LOCAL_SLAVE_TEST(v)      BM_I2C_DEBUG1_LOCAL_SLAVE_TEST
+#define BF_I2C_DEBUG1_LOCAL_SLAVE_TEST_V(e)     BF_I2C_DEBUG1_LOCAL_SLAVE_TEST(BV_I2C_DEBUG1_LOCAL_SLAVE_TEST__##e)
+#define BFM_I2C_DEBUG1_LOCAL_SLAVE_TEST_V(v)    BM_I2C_DEBUG1_LOCAL_SLAVE_TEST
+#define BP_I2C_DEBUG1_FORCE_CLK_ON              5
+#define BM_I2C_DEBUG1_FORCE_CLK_ON              0x20
+#define BF_I2C_DEBUG1_FORCE_CLK_ON(v)           (((v) & 0x1) << 5)
+#define BFM_I2C_DEBUG1_FORCE_CLK_ON(v)          BM_I2C_DEBUG1_FORCE_CLK_ON
+#define BF_I2C_DEBUG1_FORCE_CLK_ON_V(e)         BF_I2C_DEBUG1_FORCE_CLK_ON(BV_I2C_DEBUG1_FORCE_CLK_ON__##e)
+#define BFM_I2C_DEBUG1_FORCE_CLK_ON_V(v)        BM_I2C_DEBUG1_FORCE_CLK_ON
+#define BP_I2C_DEBUG1_FORCE_CLK_IDLE            4
+#define BM_I2C_DEBUG1_FORCE_CLK_IDLE            0x10
+#define BF_I2C_DEBUG1_FORCE_CLK_IDLE(v)         (((v) & 0x1) << 4)
+#define BFM_I2C_DEBUG1_FORCE_CLK_IDLE(v)        BM_I2C_DEBUG1_FORCE_CLK_IDLE
+#define BF_I2C_DEBUG1_FORCE_CLK_IDLE_V(e)       BF_I2C_DEBUG1_FORCE_CLK_IDLE(BV_I2C_DEBUG1_FORCE_CLK_IDLE__##e)
+#define BFM_I2C_DEBUG1_FORCE_CLK_IDLE_V(v)      BM_I2C_DEBUG1_FORCE_CLK_IDLE
+#define BP_I2C_DEBUG1_FORCE_ARB_LOSS            3
+#define BM_I2C_DEBUG1_FORCE_ARB_LOSS            0x8
+#define BF_I2C_DEBUG1_FORCE_ARB_LOSS(v)         (((v) & 0x1) << 3)
+#define BFM_I2C_DEBUG1_FORCE_ARB_LOSS(v)        BM_I2C_DEBUG1_FORCE_ARB_LOSS
+#define BF_I2C_DEBUG1_FORCE_ARB_LOSS_V(e)       BF_I2C_DEBUG1_FORCE_ARB_LOSS(BV_I2C_DEBUG1_FORCE_ARB_LOSS__##e)
+#define BFM_I2C_DEBUG1_FORCE_ARB_LOSS_V(v)      BM_I2C_DEBUG1_FORCE_ARB_LOSS
+#define BP_I2C_DEBUG1_FORCE_RCV_ACK             2
+#define BM_I2C_DEBUG1_FORCE_RCV_ACK             0x4
+#define BF_I2C_DEBUG1_FORCE_RCV_ACK(v)          (((v) & 0x1) << 2)
+#define BFM_I2C_DEBUG1_FORCE_RCV_ACK(v)         BM_I2C_DEBUG1_FORCE_RCV_ACK
+#define BF_I2C_DEBUG1_FORCE_RCV_ACK_V(e)        BF_I2C_DEBUG1_FORCE_RCV_ACK(BV_I2C_DEBUG1_FORCE_RCV_ACK__##e)
+#define BFM_I2C_DEBUG1_FORCE_RCV_ACK_V(v)       BM_I2C_DEBUG1_FORCE_RCV_ACK
+#define BP_I2C_DEBUG1_FORCE_I2C_DATA_OE         1
+#define BM_I2C_DEBUG1_FORCE_I2C_DATA_OE         0x2
+#define BF_I2C_DEBUG1_FORCE_I2C_DATA_OE(v)      (((v) & 0x1) << 1)
+#define BFM_I2C_DEBUG1_FORCE_I2C_DATA_OE(v)     BM_I2C_DEBUG1_FORCE_I2C_DATA_OE
+#define BF_I2C_DEBUG1_FORCE_I2C_DATA_OE_V(e)    BF_I2C_DEBUG1_FORCE_I2C_DATA_OE(BV_I2C_DEBUG1_FORCE_I2C_DATA_OE__##e)
+#define BFM_I2C_DEBUG1_FORCE_I2C_DATA_OE_V(v)   BM_I2C_DEBUG1_FORCE_I2C_DATA_OE
+#define BP_I2C_DEBUG1_FORCE_I2C_CLK_OE          0
+#define BM_I2C_DEBUG1_FORCE_I2C_CLK_OE          0x1
+#define BF_I2C_DEBUG1_FORCE_I2C_CLK_OE(v)       (((v) & 0x1) << 0)
+#define BFM_I2C_DEBUG1_FORCE_I2C_CLK_OE(v)      BM_I2C_DEBUG1_FORCE_I2C_CLK_OE
+#define BF_I2C_DEBUG1_FORCE_I2C_CLK_OE_V(e)     BF_I2C_DEBUG1_FORCE_I2C_CLK_OE(BV_I2C_DEBUG1_FORCE_I2C_CLK_OE__##e)
+#define BFM_I2C_DEBUG1_FORCE_I2C_CLK_OE_V(v)    BM_I2C_DEBUG1_FORCE_I2C_CLK_OE
+
+#define HW_I2C_VERSION              HW(I2C_VERSION)
+#define HWA_I2C_VERSION             (0x80058000 + 0x90)
+#define HWT_I2C_VERSION             HWIO_32_RW
+#define HWN_I2C_VERSION             I2C_VERSION
+#define HWI_I2C_VERSION             
+#define BP_I2C_VERSION_MAJOR        24
+#define BM_I2C_VERSION_MAJOR        0xff000000
+#define BF_I2C_VERSION_MAJOR(v)     (((v) & 0xff) << 24)
+#define BFM_I2C_VERSION_MAJOR(v)    BM_I2C_VERSION_MAJOR
+#define BF_I2C_VERSION_MAJOR_V(e)   BF_I2C_VERSION_MAJOR(BV_I2C_VERSION_MAJOR__##e)
+#define BFM_I2C_VERSION_MAJOR_V(v)  BM_I2C_VERSION_MAJOR
+#define BP_I2C_VERSION_MINOR        16
+#define BM_I2C_VERSION_MINOR        0xff0000
+#define BF_I2C_VERSION_MINOR(v)     (((v) & 0xff) << 16)
+#define BFM_I2C_VERSION_MINOR(v)    BM_I2C_VERSION_MINOR
+#define BF_I2C_VERSION_MINOR_V(e)   BF_I2C_VERSION_MINOR(BV_I2C_VERSION_MINOR__##e)
+#define BFM_I2C_VERSION_MINOR_V(v)  BM_I2C_VERSION_MINOR
+#define BP_I2C_VERSION_STEP         0
+#define BM_I2C_VERSION_STEP         0xffff
+#define BF_I2C_VERSION_STEP(v)      (((v) & 0xffff) << 0)
+#define BFM_I2C_VERSION_STEP(v)     BM_I2C_VERSION_STEP
+#define BF_I2C_VERSION_STEP_V(e)    BF_I2C_VERSION_STEP(BV_I2C_VERSION_STEP__##e)
+#define BFM_I2C_VERSION_STEP_V(v)   BM_I2C_VERSION_STEP
+
+#endif /* __HEADERGEN_STMP3700_I2C_H__*/
diff --git a/firmware/target/arm/imx233/regs/stmp3700/icoll.h b/firmware/target/arm/imx233/regs/stmp3700/icoll.h
new file mode 100644
index 0000000000..b35fa805bc
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3700/icoll.h
@@ -0,0 +1,557 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * stmp3700 version: 2.4.0
+ * stmp3700 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_STMP3700_ICOLL_H__
+#define __HEADERGEN_STMP3700_ICOLL_H__
+
+#define HW_ICOLL_VECTOR                 HW(ICOLL_VECTOR)
+#define HWA_ICOLL_VECTOR                (0x80000000 + 0x0)
+#define HWT_ICOLL_VECTOR                HWIO_32_RW
+#define HWN_ICOLL_VECTOR                ICOLL_VECTOR
+#define HWI_ICOLL_VECTOR                
+#define HW_ICOLL_VECTOR_SET             HW(ICOLL_VECTOR_SET)
+#define HWA_ICOLL_VECTOR_SET            (HWA_ICOLL_VECTOR + 0x4)
+#define HWT_ICOLL_VECTOR_SET            HWIO_32_WO
+#define HWN_ICOLL_VECTOR_SET            ICOLL_VECTOR
+#define HWI_ICOLL_VECTOR_SET            
+#define HW_ICOLL_VECTOR_CLR             HW(ICOLL_VECTOR_CLR)
+#define HWA_ICOLL_VECTOR_CLR            (HWA_ICOLL_VECTOR + 0x8)
+#define HWT_ICOLL_VECTOR_CLR            HWIO_32_WO
+#define HWN_ICOLL_VECTOR_CLR            ICOLL_VECTOR
+#define HWI_ICOLL_VECTOR_CLR            
+#define HW_ICOLL_VECTOR_TOG             HW(ICOLL_VECTOR_TOG)
+#define HWA_ICOLL_VECTOR_TOG            (HWA_ICOLL_VECTOR + 0xc)
+#define HWT_ICOLL_VECTOR_TOG            HWIO_32_WO
+#define HWN_ICOLL_VECTOR_TOG            ICOLL_VECTOR
+#define HWI_ICOLL_VECTOR_TOG            
+#define BP_ICOLL_VECTOR_IRQVECTOR       2
+#define BM_ICOLL_VECTOR_IRQVECTOR       0xfffffffc
+#define BF_ICOLL_VECTOR_IRQVECTOR(v)    (((v) & 0x3fffffff) << 2)
+#define BFM_ICOLL_VECTOR_IRQVECTOR(v)   BM_ICOLL_VECTOR_IRQVECTOR
+#define BF_ICOLL_VECTOR_IRQVECTOR_V(e)  BF_ICOLL_VECTOR_IRQVECTOR(BV_ICOLL_VECTOR_IRQVECTOR__##e)
+#define BFM_ICOLL_VECTOR_IRQVECTOR_V(v) BM_ICOLL_VECTOR_IRQVECTOR
+
+#define HW_ICOLL_LEVELACK                       HW(ICOLL_LEVELACK)
+#define HWA_ICOLL_LEVELACK                      (0x80000000 + 0x10)
+#define HWT_ICOLL_LEVELACK                      HWIO_32_RW
+#define HWN_ICOLL_LEVELACK                      ICOLL_LEVELACK
+#define HWI_ICOLL_LEVELACK                      
+#define BP_ICOLL_LEVELACK_IRQLEVELACK           0
+#define BM_ICOLL_LEVELACK_IRQLEVELACK           0xf
+#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0   0x1
+#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL1   0x2
+#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL2   0x4
+#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL3   0x8
+#define BF_ICOLL_LEVELACK_IRQLEVELACK(v)        (((v) & 0xf) << 0)
+#define BFM_ICOLL_LEVELACK_IRQLEVELACK(v)       BM_ICOLL_LEVELACK_IRQLEVELACK
+#define BF_ICOLL_LEVELACK_IRQLEVELACK_V(e)      BF_ICOLL_LEVELACK_IRQLEVELACK(BV_ICOLL_LEVELACK_IRQLEVELACK__##e)
+#define BFM_ICOLL_LEVELACK_IRQLEVELACK_V(v)     BM_ICOLL_LEVELACK_IRQLEVELACK
+
+#define HW_ICOLL_CTRL                                   HW(ICOLL_CTRL)
+#define HWA_ICOLL_CTRL                                  (0x80000000 + 0x20)
+#define HWT_ICOLL_CTRL                                  HWIO_32_RW
+#define HWN_ICOLL_CTRL                                  ICOLL_CTRL
+#define HWI_ICOLL_CTRL                                  
+#define HW_ICOLL_CTRL_SET                               HW(ICOLL_CTRL_SET)
+#define HWA_ICOLL_CTRL_SET                              (HWA_ICOLL_CTRL + 0x4)
+#define HWT_ICOLL_CTRL_SET                              HWIO_32_WO
+#define HWN_ICOLL_CTRL_SET                              ICOLL_CTRL
+#define HWI_ICOLL_CTRL_SET                              
+#define HW_ICOLL_CTRL_CLR                               HW(ICOLL_CTRL_CLR)
+#define HWA_ICOLL_CTRL_CLR                              (HWA_ICOLL_CTRL + 0x8)
+#define HWT_ICOLL_CTRL_CLR                              HWIO_32_WO
+#define HWN_ICOLL_CTRL_CLR                              ICOLL_CTRL
+#define HWI_ICOLL_CTRL_CLR                              
+#define HW_ICOLL_CTRL_TOG                               HW(ICOLL_CTRL_TOG)
+#define HWA_ICOLL_CTRL_TOG                              (HWA_ICOLL_CTRL + 0xc)
+#define HWT_ICOLL_CTRL_TOG                              HWIO_32_WO
+#define HWN_ICOLL_CTRL_TOG                              ICOLL_CTRL
+#define HWI_ICOLL_CTRL_TOG                              
+#define BP_ICOLL_CTRL_SFTRST                            31
+#define BM_ICOLL_CTRL_SFTRST                            0x80000000
+#define BV_ICOLL_CTRL_SFTRST__RUN                       0x0
+#define BV_ICOLL_CTRL_SFTRST__IN_RESET                  0x1
+#define BF_ICOLL_CTRL_SFTRST(v)                         (((v) & 0x1) << 31)
+#define BFM_ICOLL_CTRL_SFTRST(v)                        BM_ICOLL_CTRL_SFTRST
+#define BF_ICOLL_CTRL_SFTRST_V(e)                       BF_ICOLL_CTRL_SFTRST(BV_ICOLL_CTRL_SFTRST__##e)
+#define BFM_ICOLL_CTRL_SFTRST_V(v)                      BM_ICOLL_CTRL_SFTRST
+#define BP_ICOLL_CTRL_CLKGATE                           30
+#define BM_ICOLL_CTRL_CLKGATE                           0x40000000
+#define BV_ICOLL_CTRL_CLKGATE__RUN                      0x0
+#define BV_ICOLL_CTRL_CLKGATE__NO_CLOCKS                0x1
+#define BF_ICOLL_CTRL_CLKGATE(v)                        (((v) & 0x1) << 30)
+#define BFM_ICOLL_CTRL_CLKGATE(v)                       BM_ICOLL_CTRL_CLKGATE
+#define BF_ICOLL_CTRL_CLKGATE_V(e)                      BF_ICOLL_CTRL_CLKGATE(BV_ICOLL_CTRL_CLKGATE__##e)
+#define BFM_ICOLL_CTRL_CLKGATE_V(v)                     BM_ICOLL_CTRL_CLKGATE
+#define BP_ICOLL_CTRL_VECTOR_PITCH                      21
+#define BM_ICOLL_CTRL_VECTOR_PITCH                      0xe00000
+#define BV_ICOLL_CTRL_VECTOR_PITCH__DEFAULT_BY4         0x0
+#define BV_ICOLL_CTRL_VECTOR_PITCH__BY4                 0x1
+#define BV_ICOLL_CTRL_VECTOR_PITCH__BY8                 0x2
+#define BV_ICOLL_CTRL_VECTOR_PITCH__BY12                0x3
+#define BV_ICOLL_CTRL_VECTOR_PITCH__BY16                0x4
+#define BV_ICOLL_CTRL_VECTOR_PITCH__BY20                0x5
+#define BV_ICOLL_CTRL_VECTOR_PITCH__BY24                0x6
+#define BV_ICOLL_CTRL_VECTOR_PITCH__BY28                0x7
+#define BF_ICOLL_CTRL_VECTOR_PITCH(v)                   (((v) & 0x7) << 21)
+#define BFM_ICOLL_CTRL_VECTOR_PITCH(v)                  BM_ICOLL_CTRL_VECTOR_PITCH
+#define BF_ICOLL_CTRL_VECTOR_PITCH_V(e)                 BF_ICOLL_CTRL_VECTOR_PITCH(BV_ICOLL_CTRL_VECTOR_PITCH__##e)
+#define BFM_ICOLL_CTRL_VECTOR_PITCH_V(v)                BM_ICOLL_CTRL_VECTOR_PITCH
+#define BP_ICOLL_CTRL_BYPASS_FSM                        20
+#define BM_ICOLL_CTRL_BYPASS_FSM                        0x100000
+#define BV_ICOLL_CTRL_BYPASS_FSM__NORMAL                0x0
+#define BV_ICOLL_CTRL_BYPASS_FSM__BYPASS                0x1
+#define BF_ICOLL_CTRL_BYPASS_FSM(v)                     (((v) & 0x1) << 20)
+#define BFM_ICOLL_CTRL_BYPASS_FSM(v)                    BM_ICOLL_CTRL_BYPASS_FSM
+#define BF_ICOLL_CTRL_BYPASS_FSM_V(e)                   BF_ICOLL_CTRL_BYPASS_FSM(BV_ICOLL_CTRL_BYPASS_FSM__##e)
+#define BFM_ICOLL_CTRL_BYPASS_FSM_V(v)                  BM_ICOLL_CTRL_BYPASS_FSM
+#define BP_ICOLL_CTRL_NO_NESTING                        19
+#define BM_ICOLL_CTRL_NO_NESTING                        0x80000
+#define BV_ICOLL_CTRL_NO_NESTING__NORMAL                0x0
+#define BV_ICOLL_CTRL_NO_NESTING__NO_NEST               0x1
+#define BF_ICOLL_CTRL_NO_NESTING(v)                     (((v) & 0x1) << 19)
+#define BFM_ICOLL_CTRL_NO_NESTING(v)                    BM_ICOLL_CTRL_NO_NESTING
+#define BF_ICOLL_CTRL_NO_NESTING_V(e)                   BF_ICOLL_CTRL_NO_NESTING(BV_ICOLL_CTRL_NO_NESTING__##e)
+#define BFM_ICOLL_CTRL_NO_NESTING_V(v)                  BM_ICOLL_CTRL_NO_NESTING
+#define BP_ICOLL_CTRL_ARM_RSE_MODE                      18
+#define BM_ICOLL_CTRL_ARM_RSE_MODE                      0x40000
+#define BV_ICOLL_CTRL_ARM_RSE_MODE__MUST_WRITE          0x0
+#define BV_ICOLL_CTRL_ARM_RSE_MODE__READ_SIDE_EFFECT    0x1
+#define BF_ICOLL_CTRL_ARM_RSE_MODE(v)                   (((v) & 0x1) << 18)
+#define BFM_ICOLL_CTRL_ARM_RSE_MODE(v)                  BM_ICOLL_CTRL_ARM_RSE_MODE
+#define BF_ICOLL_CTRL_ARM_RSE_MODE_V(e)                 BF_ICOLL_CTRL_ARM_RSE_MODE(BV_ICOLL_CTRL_ARM_RSE_MODE__##e)
+#define BFM_ICOLL_CTRL_ARM_RSE_MODE_V(v)                BM_ICOLL_CTRL_ARM_RSE_MODE
+#define BP_ICOLL_CTRL_FIQ_FINAL_ENABLE                  17
+#define BM_ICOLL_CTRL_FIQ_FINAL_ENABLE                  0x20000
+#define BV_ICOLL_CTRL_FIQ_FINAL_ENABLE__DISABLE         0x0
+#define BV_ICOLL_CTRL_FIQ_FINAL_ENABLE__ENABLE          0x1
+#define BF_ICOLL_CTRL_FIQ_FINAL_ENABLE(v)               (((v) & 0x1) << 17)
+#define BFM_ICOLL_CTRL_FIQ_FINAL_ENABLE(v)              BM_ICOLL_CTRL_FIQ_FINAL_ENABLE
+#define BF_ICOLL_CTRL_FIQ_FINAL_ENABLE_V(e)             BF_ICOLL_CTRL_FIQ_FINAL_ENABLE(BV_ICOLL_CTRL_FIQ_FINAL_ENABLE__##e)
+#define BFM_ICOLL_CTRL_FIQ_FINAL_ENABLE_V(v)            BM_ICOLL_CTRL_FIQ_FINAL_ENABLE
+#define BP_ICOLL_CTRL_IRQ_FINAL_ENABLE                  16
+#define BM_ICOLL_CTRL_IRQ_FINAL_ENABLE                  0x10000
+#define BV_ICOLL_CTRL_IRQ_FINAL_ENABLE__DISABLE         0x0
+#define BV_ICOLL_CTRL_IRQ_FINAL_ENABLE__ENABLE          0x1
+#define BF_ICOLL_CTRL_IRQ_FINAL_ENABLE(v)               (((v) & 0x1) << 16)
+#define BFM_ICOLL_CTRL_IRQ_FINAL_ENABLE(v)              BM_ICOLL_CTRL_IRQ_FINAL_ENABLE
+#define BF_ICOLL_CTRL_IRQ_FINAL_ENABLE_V(e)             BF_ICOLL_CTRL_IRQ_FINAL_ENABLE(BV_ICOLL_CTRL_IRQ_FINAL_ENABLE__##e)
+#define BFM_ICOLL_CTRL_IRQ_FINAL_ENABLE_V(v)            BM_ICOLL_CTRL_IRQ_FINAL_ENABLE
+#define BP_ICOLL_CTRL_ENABLE2FIQ35                      7
+#define BM_ICOLL_CTRL_ENABLE2FIQ35                      0x80
+#define BV_ICOLL_CTRL_ENABLE2FIQ35__DISABLE             0x0
+#define BV_ICOLL_CTRL_ENABLE2FIQ35__ENABLE              0x1
+#define BF_ICOLL_CTRL_ENABLE2FIQ35(v)                   (((v) & 0x1) << 7)
+#define BFM_ICOLL_CTRL_ENABLE2FIQ35(v)                  BM_ICOLL_CTRL_ENABLE2FIQ35
+#define BF_ICOLL_CTRL_ENABLE2FIQ35_V(e)                 BF_ICOLL_CTRL_ENABLE2FIQ35(BV_ICOLL_CTRL_ENABLE2FIQ35__##e)
+#define BFM_ICOLL_CTRL_ENABLE2FIQ35_V(v)                BM_ICOLL_CTRL_ENABLE2FIQ35
+#define BP_ICOLL_CTRL_ENABLE2FIQ34                      6
+#define BM_ICOLL_CTRL_ENABLE2FIQ34                      0x40
+#define BV_ICOLL_CTRL_ENABLE2FIQ34__DISABLE             0x0
+#define BV_ICOLL_CTRL_ENABLE2FIQ34__ENABLE              0x1
+#define BF_ICOLL_CTRL_ENABLE2FIQ34(v)                   (((v) & 0x1) << 6)
+#define BFM_ICOLL_CTRL_ENABLE2FIQ34(v)                  BM_ICOLL_CTRL_ENABLE2FIQ34
+#define BF_ICOLL_CTRL_ENABLE2FIQ34_V(e)                 BF_ICOLL_CTRL_ENABLE2FIQ34(BV_ICOLL_CTRL_ENABLE2FIQ34__##e)
+#define BFM_ICOLL_CTRL_ENABLE2FIQ34_V(v)                BM_ICOLL_CTRL_ENABLE2FIQ34
+#define BP_ICOLL_CTRL_ENABLE2FIQ33                      5
+#define BM_ICOLL_CTRL_ENABLE2FIQ33                      0x20
+#define BV_ICOLL_CTRL_ENABLE2FIQ33__DISABLE             0x0
+#define BV_ICOLL_CTRL_ENABLE2FIQ33__ENABLE              0x1
+#define BF_ICOLL_CTRL_ENABLE2FIQ33(v)                   (((v) & 0x1) << 5)
+#define BFM_ICOLL_CTRL_ENABLE2FIQ33(v)                  BM_ICOLL_CTRL_ENABLE2FIQ33
+#define BF_ICOLL_CTRL_ENABLE2FIQ33_V(e)                 BF_ICOLL_CTRL_ENABLE2FIQ33(BV_ICOLL_CTRL_ENABLE2FIQ33__##e)
+#define BFM_ICOLL_CTRL_ENABLE2FIQ33_V(v)                BM_ICOLL_CTRL_ENABLE2FIQ33
+#define BP_ICOLL_CTRL_ENABLE2FIQ32                      4
+#define BM_ICOLL_CTRL_ENABLE2FIQ32                      0x10
+#define BV_ICOLL_CTRL_ENABLE2FIQ32__DISABLE             0x0
+#define BV_ICOLL_CTRL_ENABLE2FIQ32__ENABLE              0x1
+#define BF_ICOLL_CTRL_ENABLE2FIQ32(v)                   (((v) & 0x1) << 4)
+#define BFM_ICOLL_CTRL_ENABLE2FIQ32(v)                  BM_ICOLL_CTRL_ENABLE2FIQ32
+#define BF_ICOLL_CTRL_ENABLE2FIQ32_V(e)                 BF_ICOLL_CTRL_ENABLE2FIQ32(BV_ICOLL_CTRL_ENABLE2FIQ32__##e)
+#define BFM_ICOLL_CTRL_ENABLE2FIQ32_V(v)                BM_ICOLL_CTRL_ENABLE2FIQ32
+#define BP_ICOLL_CTRL_ENABLE2FIQ_T3                     3
+#define BM_ICOLL_CTRL_ENABLE2FIQ_T3                     0x8
+#define BV_ICOLL_CTRL_ENABLE2FIQ_T3__DISABLE            0x0
+#define BV_ICOLL_CTRL_ENABLE2FIQ_T3__ENABLE             0x1
+#define BF_ICOLL_CTRL_ENABLE2FIQ_T3(v)                  (((v) & 0x1) << 3)
+#define BFM_ICOLL_CTRL_ENABLE2FIQ_T3(v)                 BM_ICOLL_CTRL_ENABLE2FIQ_T3
+#define BF_ICOLL_CTRL_ENABLE2FIQ_T3_V(e)                BF_ICOLL_CTRL_ENABLE2FIQ_T3(BV_ICOLL_CTRL_ENABLE2FIQ_T3__##e)
+#define BFM_ICOLL_CTRL_ENABLE2FIQ_T3_V(v)               BM_ICOLL_CTRL_ENABLE2FIQ_T3
+#define BP_ICOLL_CTRL_ENABLE2FIQ_T2                     2
+#define BM_ICOLL_CTRL_ENABLE2FIQ_T2                     0x4
+#define BV_ICOLL_CTRL_ENABLE2FIQ_T2__DISABLE            0x0
+#define BV_ICOLL_CTRL_ENABLE2FIQ_T2__ENABLE             0x1
+#define BF_ICOLL_CTRL_ENABLE2FIQ_T2(v)                  (((v) & 0x1) << 2)
+#define BFM_ICOLL_CTRL_ENABLE2FIQ_T2(v)                 BM_ICOLL_CTRL_ENABLE2FIQ_T2
+#define BF_ICOLL_CTRL_ENABLE2FIQ_T2_V(e)                BF_ICOLL_CTRL_ENABLE2FIQ_T2(BV_ICOLL_CTRL_ENABLE2FIQ_T2__##e)
+#define BFM_ICOLL_CTRL_ENABLE2FIQ_T2_V(v)               BM_ICOLL_CTRL_ENABLE2FIQ_T2
+#define BP_ICOLL_CTRL_ENABLE2FIQ_T1                     1
+#define BM_ICOLL_CTRL_ENABLE2FIQ_T1                     0x2
+#define BV_ICOLL_CTRL_ENABLE2FIQ_T1__DISABLE            0x0
+#define BV_ICOLL_CTRL_ENABLE2FIQ_T1__ENABLE             0x1
+#define BF_ICOLL_CTRL_ENABLE2FIQ_T1(v)                  (((v) & 0x1) << 1)
+#define BFM_ICOLL_CTRL_ENABLE2FIQ_T1(v)                 BM_ICOLL_CTRL_ENABLE2FIQ_T1
+#define BF_ICOLL_CTRL_ENABLE2FIQ_T1_V(e)                BF_ICOLL_CTRL_ENABLE2FIQ_T1(BV_ICOLL_CTRL_ENABLE2FIQ_T1__##e)
+#define BFM_ICOLL_CTRL_ENABLE2FIQ_T1_V(v)               BM_ICOLL_CTRL_ENABLE2FIQ_T1
+#define BP_ICOLL_CTRL_ENABLE2FIQ_T0                     0
+#define BM_ICOLL_CTRL_ENABLE2FIQ_T0                     0x1
+#define BV_ICOLL_CTRL_ENABLE2FIQ_T0__DISABLE            0x0
+#define BV_ICOLL_CTRL_ENABLE2FIQ_T0__ENABLE             0x1
+#define BF_ICOLL_CTRL_ENABLE2FIQ_T0(v)                  (((v) & 0x1) << 0)
+#define BFM_ICOLL_CTRL_ENABLE2FIQ_T0(v)                 BM_ICOLL_CTRL_ENABLE2FIQ_T0
+#define BF_ICOLL_CTRL_ENABLE2FIQ_T0_V(e)                BF_ICOLL_CTRL_ENABLE2FIQ_T0(BV_ICOLL_CTRL_ENABLE2FIQ_T0__##e)
+#define BFM_ICOLL_CTRL_ENABLE2FIQ_T0_V(v)               BM_ICOLL_CTRL_ENABLE2FIQ_T0
+
+#define HW_ICOLL_STAT                       HW(ICOLL_STAT)
+#define HWA_ICOLL_STAT                      (0x80000000 + 0x30)
+#define HWT_ICOLL_STAT                      HWIO_32_RW
+#define HWN_ICOLL_STAT                      ICOLL_STAT
+#define HWI_ICOLL_STAT                      
+#define BP_ICOLL_STAT_VECTOR_NUMBER         0
+#define BM_ICOLL_STAT_VECTOR_NUMBER         0x3f
+#define BF_ICOLL_STAT_VECTOR_NUMBER(v)      (((v) & 0x3f) << 0)
+#define BFM_ICOLL_STAT_VECTOR_NUMBER(v)     BM_ICOLL_STAT_VECTOR_NUMBER
+#define BF_ICOLL_STAT_VECTOR_NUMBER_V(e)    BF_ICOLL_STAT_VECTOR_NUMBER(BV_ICOLL_STAT_VECTOR_NUMBER__##e)
+#define BFM_ICOLL_STAT_VECTOR_NUMBER_V(v)   BM_ICOLL_STAT_VECTOR_NUMBER
+
+#define HW_ICOLL_RAWn(_n1)              HW(ICOLL_RAWn(_n1))
+#define HWA_ICOLL_RAWn(_n1)             (0x80000000 + 0x40 + (_n1) * 0x10)
+#define HWT_ICOLL_RAWn(_n1)             HWIO_32_RW
+#define HWN_ICOLL_RAWn(_n1)             ICOLL_RAWn
+#define HWI_ICOLL_RAWn(_n1)             (_n1)
+#define BP_ICOLL_RAWn_RAW_IRQS          0
+#define BM_ICOLL_RAWn_RAW_IRQS          0xffffffff
+#define BF_ICOLL_RAWn_RAW_IRQS(v)       (((v) & 0xffffffff) << 0)
+#define BFM_ICOLL_RAWn_RAW_IRQS(v)      BM_ICOLL_RAWn_RAW_IRQS
+#define BF_ICOLL_RAWn_RAW_IRQS_V(e)     BF_ICOLL_RAWn_RAW_IRQS(BV_ICOLL_RAWn_RAW_IRQS__##e)
+#define BFM_ICOLL_RAWn_RAW_IRQS_V(v)    BM_ICOLL_RAWn_RAW_IRQS
+
+#define HW_ICOLL_PRIORITYn(_n1)                         HW(ICOLL_PRIORITYn(_n1))
+#define HWA_ICOLL_PRIORITYn(_n1)                        (0x80000000 + 0x60 + (_n1) * 0x10)
+#define HWT_ICOLL_PRIORITYn(_n1)                        HWIO_32_RW
+#define HWN_ICOLL_PRIORITYn(_n1)                        ICOLL_PRIORITYn
+#define HWI_ICOLL_PRIORITYn(_n1)                        (_n1)
+#define HW_ICOLL_PRIORITYn_SET(_n1)                     HW(ICOLL_PRIORITYn_SET(_n1))
+#define HWA_ICOLL_PRIORITYn_SET(_n1)                    (HWA_ICOLL_PRIORITYn(_n1) + 0x4)
+#define HWT_ICOLL_PRIORITYn_SET(_n1)                    HWIO_32_WO
+#define HWN_ICOLL_PRIORITYn_SET(_n1)                    ICOLL_PRIORITYn
+#define HWI_ICOLL_PRIORITYn_SET(_n1)                    (_n1)
+#define HW_ICOLL_PRIORITYn_CLR(_n1)                     HW(ICOLL_PRIORITYn_CLR(_n1))
+#define HWA_ICOLL_PRIORITYn_CLR(_n1)                    (HWA_ICOLL_PRIORITYn(_n1) + 0x8)
+#define HWT_ICOLL_PRIORITYn_CLR(_n1)                    HWIO_32_WO
+#define HWN_ICOLL_PRIORITYn_CLR(_n1)                    ICOLL_PRIORITYn
+#define HWI_ICOLL_PRIORITYn_CLR(_n1)                    (_n1)
+#define HW_ICOLL_PRIORITYn_TOG(_n1)                     HW(ICOLL_PRIORITYn_TOG(_n1))
+#define HWA_ICOLL_PRIORITYn_TOG(_n1)                    (HWA_ICOLL_PRIORITYn(_n1) + 0xc)
+#define HWT_ICOLL_PRIORITYn_TOG(_n1)                    HWIO_32_WO
+#define HWN_ICOLL_PRIORITYn_TOG(_n1)                    ICOLL_PRIORITYn
+#define HWI_ICOLL_PRIORITYn_TOG(_n1)                    (_n1)
+#define BP_ICOLL_PRIORITYn_SOFTIRQ3                     27
+#define BM_ICOLL_PRIORITYn_SOFTIRQ3                     0x8000000
+#define BV_ICOLL_PRIORITYn_SOFTIRQ3__NO_INTERRUPT       0x0
+#define BV_ICOLL_PRIORITYn_SOFTIRQ3__FORCE_INTERRUPT    0x1
+#define BF_ICOLL_PRIORITYn_SOFTIRQ3(v)                  (((v) & 0x1) << 27)
+#define BFM_ICOLL_PRIORITYn_SOFTIRQ3(v)                 BM_ICOLL_PRIORITYn_SOFTIRQ3
+#define BF_ICOLL_PRIORITYn_SOFTIRQ3_V(e)                BF_ICOLL_PRIORITYn_SOFTIRQ3(BV_ICOLL_PRIORITYn_SOFTIRQ3__##e)
+#define BFM_ICOLL_PRIORITYn_SOFTIRQ3_V(v)               BM_ICOLL_PRIORITYn_SOFTIRQ3
+#define BP_ICOLL_PRIORITYn_ENABLE3                      26
+#define BM_ICOLL_PRIORITYn_ENABLE3                      0x4000000
+#define BV_ICOLL_PRIORITYn_ENABLE3__DISABLE             0x0
+#define BV_ICOLL_PRIORITYn_ENABLE3__ENABLE              0x1
+#define BF_ICOLL_PRIORITYn_ENABLE3(v)                   (((v) & 0x1) << 26)
+#define BFM_ICOLL_PRIORITYn_ENABLE3(v)                  BM_ICOLL_PRIORITYn_ENABLE3
+#define BF_ICOLL_PRIORITYn_ENABLE3_V(e)                 BF_ICOLL_PRIORITYn_ENABLE3(BV_ICOLL_PRIORITYn_ENABLE3__##e)
+#define BFM_ICOLL_PRIORITYn_ENABLE3_V(v)                BM_ICOLL_PRIORITYn_ENABLE3
+#define BP_ICOLL_PRIORITYn_PRIORITY3                    24
+#define BM_ICOLL_PRIORITYn_PRIORITY3                    0x3000000
+#define BV_ICOLL_PRIORITYn_PRIORITY3__LEVEL0            0x0
+#define BV_ICOLL_PRIORITYn_PRIORITY3__LEVEL1            0x1
+#define BV_ICOLL_PRIORITYn_PRIORITY3__LEVEL2            0x2
+#define BV_ICOLL_PRIORITYn_PRIORITY3__LEVEL3            0x3
+#define BF_ICOLL_PRIORITYn_PRIORITY3(v)                 (((v) & 0x3) << 24)
+#define BFM_ICOLL_PRIORITYn_PRIORITY3(v)                BM_ICOLL_PRIORITYn_PRIORITY3
+#define BF_ICOLL_PRIORITYn_PRIORITY3_V(e)               BF_ICOLL_PRIORITYn_PRIORITY3(BV_ICOLL_PRIORITYn_PRIORITY3__##e)
+#define BFM_ICOLL_PRIORITYn_PRIORITY3_V(v)              BM_ICOLL_PRIORITYn_PRIORITY3
+#define BP_ICOLL_PRIORITYn_SOFTIRQ2                     19
+#define BM_ICOLL_PRIORITYn_SOFTIRQ2                     0x80000
+#define BV_ICOLL_PRIORITYn_SOFTIRQ2__NO_INTERRUPT       0x0
+#define BV_ICOLL_PRIORITYn_SOFTIRQ2__FORCE_INTERRUPT    0x1
+#define BF_ICOLL_PRIORITYn_SOFTIRQ2(v)                  (((v) & 0x1) << 19)
+#define BFM_ICOLL_PRIORITYn_SOFTIRQ2(v)                 BM_ICOLL_PRIORITYn_SOFTIRQ2
+#define BF_ICOLL_PRIORITYn_SOFTIRQ2_V(e)                BF_ICOLL_PRIORITYn_SOFTIRQ2(BV_ICOLL_PRIORITYn_SOFTIRQ2__##e)
+#define BFM_ICOLL_PRIORITYn_SOFTIRQ2_V(v)               BM_ICOLL_PRIORITYn_SOFTIRQ2
+#define BP_ICOLL_PRIORITYn_ENABLE2                      18
+#define BM_ICOLL_PRIORITYn_ENABLE2                      0x40000
+#define BV_ICOLL_PRIORITYn_ENABLE2__DISABLE             0x0
+#define BV_ICOLL_PRIORITYn_ENABLE2__ENABLE              0x1
+#define BF_ICOLL_PRIORITYn_ENABLE2(v)                   (((v) & 0x1) << 18)
+#define BFM_ICOLL_PRIORITYn_ENABLE2(v)                  BM_ICOLL_PRIORITYn_ENABLE2
+#define BF_ICOLL_PRIORITYn_ENABLE2_V(e)                 BF_ICOLL_PRIORITYn_ENABLE2(BV_ICOLL_PRIORITYn_ENABLE2__##e)
+#define BFM_ICOLL_PRIORITYn_ENABLE2_V(v)                BM_ICOLL_PRIORITYn_ENABLE2
+#define BP_ICOLL_PRIORITYn_PRIORITY2                    16
+#define BM_ICOLL_PRIORITYn_PRIORITY2                    0x30000
+#define BV_ICOLL_PRIORITYn_PRIORITY2__LEVEL0            0x0
+#define BV_ICOLL_PRIORITYn_PRIORITY2__LEVEL1            0x1
+#define BV_ICOLL_PRIORITYn_PRIORITY2__LEVEL2            0x2
+#define BV_ICOLL_PRIORITYn_PRIORITY2__LEVEL3            0x3
+#define BF_ICOLL_PRIORITYn_PRIORITY2(v)                 (((v) & 0x3) << 16)
+#define BFM_ICOLL_PRIORITYn_PRIORITY2(v)                BM_ICOLL_PRIORITYn_PRIORITY2
+#define BF_ICOLL_PRIORITYn_PRIORITY2_V(e)               BF_ICOLL_PRIORITYn_PRIORITY2(BV_ICOLL_PRIORITYn_PRIORITY2__##e)
+#define BFM_ICOLL_PRIORITYn_PRIORITY2_V(v)              BM_ICOLL_PRIORITYn_PRIORITY2
+#define BP_ICOLL_PRIORITYn_SOFTIRQ1                     11
+#define BM_ICOLL_PRIORITYn_SOFTIRQ1                     0x800
+#define BV_ICOLL_PRIORITYn_SOFTIRQ1__NO_INTERRUPT       0x0
+#define BV_ICOLL_PRIORITYn_SOFTIRQ1__FORCE_INTERRUPT    0x1
+#define BF_ICOLL_PRIORITYn_SOFTIRQ1(v)                  (((v) & 0x1) << 11)
+#define BFM_ICOLL_PRIORITYn_SOFTIRQ1(v)                 BM_ICOLL_PRIORITYn_SOFTIRQ1
+#define BF_ICOLL_PRIORITYn_SOFTIRQ1_V(e)                BF_ICOLL_PRIORITYn_SOFTIRQ1(BV_ICOLL_PRIORITYn_SOFTIRQ1__##e)
+#define BFM_ICOLL_PRIORITYn_SOFTIRQ1_V(v)               BM_ICOLL_PRIORITYn_SOFTIRQ1
+#define BP_ICOLL_PRIORITYn_ENABLE1                      10
+#define BM_ICOLL_PRIORITYn_ENABLE1                      0x400
+#define BV_ICOLL_PRIORITYn_ENABLE1__DISABLE             0x0
+#define BV_ICOLL_PRIORITYn_ENABLE1__ENABLE              0x1
+#define BF_ICOLL_PRIORITYn_ENABLE1(v)                   (((v) & 0x1) << 10)
+#define BFM_ICOLL_PRIORITYn_ENABLE1(v)                  BM_ICOLL_PRIORITYn_ENABLE1
+#define BF_ICOLL_PRIORITYn_ENABLE1_V(e)                 BF_ICOLL_PRIORITYn_ENABLE1(BV_ICOLL_PRIORITYn_ENABLE1__##e)
+#define BFM_ICOLL_PRIORITYn_ENABLE1_V(v)                BM_ICOLL_PRIORITYn_ENABLE1
+#define BP_ICOLL_PRIORITYn_PRIORITY1                    8
+#define BM_ICOLL_PRIORITYn_PRIORITY1                    0x300
+#define BV_ICOLL_PRIORITYn_PRIORITY1__LEVEL0            0x0
+#define BV_ICOLL_PRIORITYn_PRIORITY1__LEVEL1            0x1
+#define BV_ICOLL_PRIORITYn_PRIORITY1__LEVEL2            0x2
+#define BV_ICOLL_PRIORITYn_PRIORITY1__LEVEL3            0x3
+#define BF_ICOLL_PRIORITYn_PRIORITY1(v)                 (((v) & 0x3) << 8)
+#define BFM_ICOLL_PRIORITYn_PRIORITY1(v)                BM_ICOLL_PRIORITYn_PRIORITY1
+#define BF_ICOLL_PRIORITYn_PRIORITY1_V(e)               BF_ICOLL_PRIORITYn_PRIORITY1(BV_ICOLL_PRIORITYn_PRIORITY1__##e)
+#define BFM_ICOLL_PRIORITYn_PRIORITY1_V(v)              BM_ICOLL_PRIORITYn_PRIORITY1
+#define BP_ICOLL_PRIORITYn_SOFTIRQ0                     3
+#define BM_ICOLL_PRIORITYn_SOFTIRQ0                     0x8
+#define BV_ICOLL_PRIORITYn_SOFTIRQ0__NO_INTERRUPT       0x0
+#define BV_ICOLL_PRIORITYn_SOFTIRQ0__FORCE_INTERRUPT    0x1
+#define BF_ICOLL_PRIORITYn_SOFTIRQ0(v)                  (((v) & 0x1) << 3)
+#define BFM_ICOLL_PRIORITYn_SOFTIRQ0(v)                 BM_ICOLL_PRIORITYn_SOFTIRQ0
+#define BF_ICOLL_PRIORITYn_SOFTIRQ0_V(e)                BF_ICOLL_PRIORITYn_SOFTIRQ0(BV_ICOLL_PRIORITYn_SOFTIRQ0__##e)
+#define BFM_ICOLL_PRIORITYn_SOFTIRQ0_V(v)               BM_ICOLL_PRIORITYn_SOFTIRQ0
+#define BP_ICOLL_PRIORITYn_ENABLE0                      2
+#define BM_ICOLL_PRIORITYn_ENABLE0                      0x4
+#define BV_ICOLL_PRIORITYn_ENABLE0__DISABLE             0x0
+#define BV_ICOLL_PRIORITYn_ENABLE0__ENABLE              0x1
+#define BF_ICOLL_PRIORITYn_ENABLE0(v)                   (((v) & 0x1) << 2)
+#define BFM_ICOLL_PRIORITYn_ENABLE0(v)                  BM_ICOLL_PRIORITYn_ENABLE0
+#define BF_ICOLL_PRIORITYn_ENABLE0_V(e)                 BF_ICOLL_PRIORITYn_ENABLE0(BV_ICOLL_PRIORITYn_ENABLE0__##e)
+#define BFM_ICOLL_PRIORITYn_ENABLE0_V(v)                BM_ICOLL_PRIORITYn_ENABLE0
+#define BP_ICOLL_PRIORITYn_PRIORITY0                    0
+#define BM_ICOLL_PRIORITYn_PRIORITY0                    0x3
+#define BV_ICOLL_PRIORITYn_PRIORITY0__LEVEL0            0x0
+#define BV_ICOLL_PRIORITYn_PRIORITY0__LEVEL1            0x1
+#define BV_ICOLL_PRIORITYn_PRIORITY0__LEVEL2            0x2
+#define BV_ICOLL_PRIORITYn_PRIORITY0__LEVEL3            0x3
+#define BF_ICOLL_PRIORITYn_PRIORITY0(v)                 (((v) & 0x3) << 0)
+#define BFM_ICOLL_PRIORITYn_PRIORITY0(v)                BM_ICOLL_PRIORITYn_PRIORITY0
+#define BF_ICOLL_PRIORITYn_PRIORITY0_V(e)               BF_ICOLL_PRIORITYn_PRIORITY0(BV_ICOLL_PRIORITYn_PRIORITY0__##e)
+#define BFM_ICOLL_PRIORITYn_PRIORITY0_V(v)              BM_ICOLL_PRIORITYn_PRIORITY0
+
+#define HW_ICOLL_VBASE                      HW(ICOLL_VBASE)
+#define HWA_ICOLL_VBASE                     (0x80000000 + 0x160)
+#define HWT_ICOLL_VBASE                     HWIO_32_RW
+#define HWN_ICOLL_VBASE                     ICOLL_VBASE
+#define HWI_ICOLL_VBASE                     
+#define HW_ICOLL_VBASE_SET                  HW(ICOLL_VBASE_SET)
+#define HWA_ICOLL_VBASE_SET                 (HWA_ICOLL_VBASE + 0x4)
+#define HWT_ICOLL_VBASE_SET                 HWIO_32_WO
+#define HWN_ICOLL_VBASE_SET                 ICOLL_VBASE
+#define HWI_ICOLL_VBASE_SET                 
+#define HW_ICOLL_VBASE_CLR                  HW(ICOLL_VBASE_CLR)
+#define HWA_ICOLL_VBASE_CLR                 (HWA_ICOLL_VBASE + 0x8)
+#define HWT_ICOLL_VBASE_CLR                 HWIO_32_WO
+#define HWN_ICOLL_VBASE_CLR                 ICOLL_VBASE
+#define HWI_ICOLL_VBASE_CLR                 
+#define HW_ICOLL_VBASE_TOG                  HW(ICOLL_VBASE_TOG)
+#define HWA_ICOLL_VBASE_TOG                 (HWA_ICOLL_VBASE + 0xc)
+#define HWT_ICOLL_VBASE_TOG                 HWIO_32_WO
+#define HWN_ICOLL_VBASE_TOG                 ICOLL_VBASE
+#define HWI_ICOLL_VBASE_TOG                 
+#define BP_ICOLL_VBASE_TABLE_ADDRESS        2
+#define BM_ICOLL_VBASE_TABLE_ADDRESS        0xfffffffc
+#define BF_ICOLL_VBASE_TABLE_ADDRESS(v)     (((v) & 0x3fffffff) << 2)
+#define BFM_ICOLL_VBASE_TABLE_ADDRESS(v)    BM_ICOLL_VBASE_TABLE_ADDRESS
+#define BF_ICOLL_VBASE_TABLE_ADDRESS_V(e)   BF_ICOLL_VBASE_TABLE_ADDRESS(BV_ICOLL_VBASE_TABLE_ADDRESS__##e)
+#define BFM_ICOLL_VBASE_TABLE_ADDRESS_V(v)  BM_ICOLL_VBASE_TABLE_ADDRESS
+
+#define HW_ICOLL_DEBUG                              HW(ICOLL_DEBUG)
+#define HWA_ICOLL_DEBUG                             (0x80000000 + 0x170)
+#define HWT_ICOLL_DEBUG                             HWIO_32_RW
+#define HWN_ICOLL_DEBUG                             ICOLL_DEBUG
+#define HWI_ICOLL_DEBUG                             
+#define BP_ICOLL_DEBUG_INSERVICE                    28
+#define BM_ICOLL_DEBUG_INSERVICE                    0xf0000000
+#define BV_ICOLL_DEBUG_INSERVICE__LEVEL0            0x1
+#define BV_ICOLL_DEBUG_INSERVICE__LEVEL1            0x2
+#define BV_ICOLL_DEBUG_INSERVICE__LEVEL2            0x4
+#define BV_ICOLL_DEBUG_INSERVICE__LEVEL3            0x8
+#define BF_ICOLL_DEBUG_INSERVICE(v)                 (((v) & 0xf) << 28)
+#define BFM_ICOLL_DEBUG_INSERVICE(v)                BM_ICOLL_DEBUG_INSERVICE
+#define BF_ICOLL_DEBUG_INSERVICE_V(e)               BF_ICOLL_DEBUG_INSERVICE(BV_ICOLL_DEBUG_INSERVICE__##e)
+#define BFM_ICOLL_DEBUG_INSERVICE_V(v)              BM_ICOLL_DEBUG_INSERVICE
+#define BP_ICOLL_DEBUG_LEVEL_REQUESTS               24
+#define BM_ICOLL_DEBUG_LEVEL_REQUESTS               0xf000000
+#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL0       0x1
+#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL1       0x2
+#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL2       0x4
+#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL3       0x8
+#define BF_ICOLL_DEBUG_LEVEL_REQUESTS(v)            (((v) & 0xf) << 24)
+#define BFM_ICOLL_DEBUG_LEVEL_REQUESTS(v)           BM_ICOLL_DEBUG_LEVEL_REQUESTS
+#define BF_ICOLL_DEBUG_LEVEL_REQUESTS_V(e)          BF_ICOLL_DEBUG_LEVEL_REQUESTS(BV_ICOLL_DEBUG_LEVEL_REQUESTS__##e)
+#define BFM_ICOLL_DEBUG_LEVEL_REQUESTS_V(v)         BM_ICOLL_DEBUG_LEVEL_REQUESTS
+#define BP_ICOLL_DEBUG_REQUESTS_BY_LEVEL            20
+#define BM_ICOLL_DEBUG_REQUESTS_BY_LEVEL            0xf00000
+#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL0    0x1
+#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL1    0x2
+#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL2    0x4
+#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL3    0x8
+#define BF_ICOLL_DEBUG_REQUESTS_BY_LEVEL(v)         (((v) & 0xf) << 20)
+#define BFM_ICOLL_DEBUG_REQUESTS_BY_LEVEL(v)        BM_ICOLL_DEBUG_REQUESTS_BY_LEVEL
+#define BF_ICOLL_DEBUG_REQUESTS_BY_LEVEL_V(e)       BF_ICOLL_DEBUG_REQUESTS_BY_LEVEL(BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__##e)
+#define BFM_ICOLL_DEBUG_REQUESTS_BY_LEVEL_V(v)      BM_ICOLL_DEBUG_REQUESTS_BY_LEVEL
+#define BP_ICOLL_DEBUG_FIQ                          17
+#define BM_ICOLL_DEBUG_FIQ                          0x20000
+#define BV_ICOLL_DEBUG_FIQ__NO_FIQ_REQUESTED        0x0
+#define BV_ICOLL_DEBUG_FIQ__FIQ_REQUESTED           0x1
+#define BF_ICOLL_DEBUG_FIQ(v)                       (((v) & 0x1) << 17)
+#define BFM_ICOLL_DEBUG_FIQ(v)                      BM_ICOLL_DEBUG_FIQ
+#define BF_ICOLL_DEBUG_FIQ_V(e)                     BF_ICOLL_DEBUG_FIQ(BV_ICOLL_DEBUG_FIQ__##e)
+#define BFM_ICOLL_DEBUG_FIQ_V(v)                    BM_ICOLL_DEBUG_FIQ
+#define BP_ICOLL_DEBUG_IRQ                          16
+#define BM_ICOLL_DEBUG_IRQ                          0x10000
+#define BV_ICOLL_DEBUG_IRQ__NO_IRQ_REQUESTED        0x0
+#define BV_ICOLL_DEBUG_IRQ__IRQ_REQUESTED           0x1
+#define BF_ICOLL_DEBUG_IRQ(v)                       (((v) & 0x1) << 16)
+#define BFM_ICOLL_DEBUG_IRQ(v)                      BM_ICOLL_DEBUG_IRQ
+#define BF_ICOLL_DEBUG_IRQ_V(e)                     BF_ICOLL_DEBUG_IRQ(BV_ICOLL_DEBUG_IRQ__##e)
+#define BFM_ICOLL_DEBUG_IRQ_V(v)                    BM_ICOLL_DEBUG_IRQ
+#define BP_ICOLL_DEBUG_VECTOR_FSM                   0
+#define BM_ICOLL_DEBUG_VECTOR_FSM                   0x3ff
+#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_IDLE         0x0
+#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE1  0x1
+#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE2  0x2
+#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_PENDING      0x4
+#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE3  0x8
+#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE4  0x10
+#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING1 0x20
+#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING2 0x40
+#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING3 0x80
+#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE5  0x100
+#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE6  0x200
+#define BF_ICOLL_DEBUG_VECTOR_FSM(v)                (((v) & 0x3ff) << 0)
+#define BFM_ICOLL_DEBUG_VECTOR_FSM(v)               BM_ICOLL_DEBUG_VECTOR_FSM
+#define BF_ICOLL_DEBUG_VECTOR_FSM_V(e)              BF_ICOLL_DEBUG_VECTOR_FSM(BV_ICOLL_DEBUG_VECTOR_FSM__##e)
+#define BFM_ICOLL_DEBUG_VECTOR_FSM_V(v)             BM_ICOLL_DEBUG_VECTOR_FSM
+
+#define HW_ICOLL_DBGREAD0               HW(ICOLL_DBGREAD0)
+#define HWA_ICOLL_DBGREAD0              (0x80000000 + 0x180)
+#define HWT_ICOLL_DBGREAD0              HWIO_32_RW
+#define HWN_ICOLL_DBGREAD0              ICOLL_DBGREAD0
+#define HWI_ICOLL_DBGREAD0              
+#define BP_ICOLL_DBGREAD0_VALUE         0
+#define BM_ICOLL_DBGREAD0_VALUE         0xffffffff
+#define BF_ICOLL_DBGREAD0_VALUE(v)      (((v) & 0xffffffff) << 0)
+#define BFM_ICOLL_DBGREAD0_VALUE(v)     BM_ICOLL_DBGREAD0_VALUE
+#define BF_ICOLL_DBGREAD0_VALUE_V(e)    BF_ICOLL_DBGREAD0_VALUE(BV_ICOLL_DBGREAD0_VALUE__##e)
+#define BFM_ICOLL_DBGREAD0_VALUE_V(v)   BM_ICOLL_DBGREAD0_VALUE
+
+#define HW_ICOLL_DBGREAD1               HW(ICOLL_DBGREAD1)
+#define HWA_ICOLL_DBGREAD1              (0x80000000 + 0x190)
+#define HWT_ICOLL_DBGREAD1              HWIO_32_RW
+#define HWN_ICOLL_DBGREAD1              ICOLL_DBGREAD1
+#define HWI_ICOLL_DBGREAD1              
+#define BP_ICOLL_DBGREAD1_VALUE         0
+#define BM_ICOLL_DBGREAD1_VALUE         0xffffffff
+#define BF_ICOLL_DBGREAD1_VALUE(v)      (((v) & 0xffffffff) << 0)
+#define BFM_ICOLL_DBGREAD1_VALUE(v)     BM_ICOLL_DBGREAD1_VALUE
+#define BF_ICOLL_DBGREAD1_VALUE_V(e)    BF_ICOLL_DBGREAD1_VALUE(BV_ICOLL_DBGREAD1_VALUE__##e)
+#define BFM_ICOLL_DBGREAD1_VALUE_V(v)   BM_ICOLL_DBGREAD1_VALUE
+
+#define HW_ICOLL_DBGFLAG            HW(ICOLL_DBGFLAG)
+#define HWA_ICOLL_DBGFLAG           (0x80000000 + 0x1a0)
+#define HWT_ICOLL_DBGFLAG           HWIO_32_RW
+#define HWN_ICOLL_DBGFLAG           ICOLL_DBGFLAG
+#define HWI_ICOLL_DBGFLAG           
+#define HW_ICOLL_DBGFLAG_SET        HW(ICOLL_DBGFLAG_SET)
+#define HWA_ICOLL_DBGFLAG_SET       (HWA_ICOLL_DBGFLAG + 0x4)
+#define HWT_ICOLL_DBGFLAG_SET       HWIO_32_WO
+#define HWN_ICOLL_DBGFLAG_SET       ICOLL_DBGFLAG
+#define HWI_ICOLL_DBGFLAG_SET       
+#define HW_ICOLL_DBGFLAG_CLR        HW(ICOLL_DBGFLAG_CLR)
+#define HWA_ICOLL_DBGFLAG_CLR       (HWA_ICOLL_DBGFLAG + 0x8)
+#define HWT_ICOLL_DBGFLAG_CLR       HWIO_32_WO
+#define HWN_ICOLL_DBGFLAG_CLR       ICOLL_DBGFLAG
+#define HWI_ICOLL_DBGFLAG_CLR       
+#define HW_ICOLL_DBGFLAG_TOG        HW(ICOLL_DBGFLAG_TOG)
+#define HWA_ICOLL_DBGFLAG_TOG       (HWA_ICOLL_DBGFLAG + 0xc)
+#define HWT_ICOLL_DBGFLAG_TOG       HWIO_32_WO
+#define HWN_ICOLL_DBGFLAG_TOG       ICOLL_DBGFLAG
+#define HWI_ICOLL_DBGFLAG_TOG       
+#define BP_ICOLL_DBGFLAG_FLAG       0
+#define BM_ICOLL_DBGFLAG_FLAG       0xffff
+#define BF_ICOLL_DBGFLAG_FLAG(v)    (((v) & 0xffff) << 0)
+#define BFM_ICOLL_DBGFLAG_FLAG(v)   BM_ICOLL_DBGFLAG_FLAG
+#define BF_ICOLL_DBGFLAG_FLAG_V(e)  BF_ICOLL_DBGFLAG_FLAG(BV_ICOLL_DBGFLAG_FLAG__##e)
+#define BFM_ICOLL_DBGFLAG_FLAG_V(v) BM_ICOLL_DBGFLAG_FLAG
+
+#define HW_ICOLL_DBGREQUESTn(_n1)       HW(ICOLL_DBGREQUESTn(_n1))
+#define HWA_ICOLL_DBGREQUESTn(_n1)      (0x80000000 + 0x1b0 + (_n1) * 0x10)
+#define HWT_ICOLL_DBGREQUESTn(_n1)      HWIO_32_RW
+#define HWN_ICOLL_DBGREQUESTn(_n1)      ICOLL_DBGREQUESTn
+#define HWI_ICOLL_DBGREQUESTn(_n1)      (_n1)
+#define BP_ICOLL_DBGREQUESTn_BITS       0
+#define BM_ICOLL_DBGREQUESTn_BITS       0xffffffff
+#define BF_ICOLL_DBGREQUESTn_BITS(v)    (((v) & 0xffffffff) << 0)
+#define BFM_ICOLL_DBGREQUESTn_BITS(v)   BM_ICOLL_DBGREQUESTn_BITS
+#define BF_ICOLL_DBGREQUESTn_BITS_V(e)  BF_ICOLL_DBGREQUESTn_BITS(BV_ICOLL_DBGREQUESTn_BITS__##e)
+#define BFM_ICOLL_DBGREQUESTn_BITS_V(v) BM_ICOLL_DBGREQUESTn_BITS
+
+#define HW_ICOLL_VERSION                HW(ICOLL_VERSION)
+#define HWA_ICOLL_VERSION               (0x80000000 + 0x1d0)
+#define HWT_ICOLL_VERSION               HWIO_32_RW
+#define HWN_ICOLL_VERSION               ICOLL_VERSION
+#define HWI_ICOLL_VERSION               
+#define BP_ICOLL_VERSION_MAJOR          24
+#define BM_ICOLL_VERSION_MAJOR          0xff000000
+#define BF_ICOLL_VERSION_MAJOR(v)       (((v) & 0xff) << 24)
+#define BFM_ICOLL_VERSION_MAJOR(v)      BM_ICOLL_VERSION_MAJOR
+#define BF_ICOLL_VERSION_MAJOR_V(e)     BF_ICOLL_VERSION_MAJOR(BV_ICOLL_VERSION_MAJOR__##e)
+#define BFM_ICOLL_VERSION_MAJOR_V(v)    BM_ICOLL_VERSION_MAJOR
+#define BP_ICOLL_VERSION_MINOR          16
+#define BM_ICOLL_VERSION_MINOR          0xff0000
+#define BF_ICOLL_VERSION_MINOR(v)       (((v) & 0xff) << 16)
+#define BFM_ICOLL_VERSION_MINOR(v)      BM_ICOLL_VERSION_MINOR
+#define BF_ICOLL_VERSION_MINOR_V(e)     BF_ICOLL_VERSION_MINOR(BV_ICOLL_VERSION_MINOR__##e)
+#define BFM_ICOLL_VERSION_MINOR_V(v)    BM_ICOLL_VERSION_MINOR
+#define BP_ICOLL_VERSION_STEP           0
+#define BM_ICOLL_VERSION_STEP           0xffff
+#define BF_ICOLL_VERSION_STEP(v)        (((v) & 0xffff) << 0)
+#define BFM_ICOLL_VERSION_STEP(v)       BM_ICOLL_VERSION_STEP
+#define BF_ICOLL_VERSION_STEP_V(e)      BF_ICOLL_VERSION_STEP(BV_ICOLL_VERSION_STEP__##e)
+#define BFM_ICOLL_VERSION_STEP_V(v)     BM_ICOLL_VERSION_STEP
+
+#endif /* __HEADERGEN_STMP3700_ICOLL_H__*/
diff --git a/firmware/target/arm/imx233/regs/stmp3700/ir.h b/firmware/target/arm/imx233/regs/stmp3700/ir.h
new file mode 100644
index 0000000000..4d7eb5131f
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3700/ir.h
@@ -0,0 +1,775 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * stmp3700 version: 2.4.0
+ * stmp3700 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_STMP3700_IR_H__
+#define __HEADERGEN_STMP3700_IR_H__
+
+#define HW_IR_CTRL                      HW(IR_CTRL)
+#define HWA_IR_CTRL                     (0x80078000 + 0x0)
+#define HWT_IR_CTRL                     HWIO_32_RW
+#define HWN_IR_CTRL                     IR_CTRL
+#define HWI_IR_CTRL                     
+#define HW_IR_CTRL_SET                  HW(IR_CTRL_SET)
+#define HWA_IR_CTRL_SET                 (HWA_IR_CTRL + 0x4)
+#define HWT_IR_CTRL_SET                 HWIO_32_WO
+#define HWN_IR_CTRL_SET                 IR_CTRL
+#define HWI_IR_CTRL_SET                 
+#define HW_IR_CTRL_CLR                  HW(IR_CTRL_CLR)
+#define HWA_IR_CTRL_CLR                 (HWA_IR_CTRL + 0x8)
+#define HWT_IR_CTRL_CLR                 HWIO_32_WO
+#define HWN_IR_CTRL_CLR                 IR_CTRL
+#define HWI_IR_CTRL_CLR                 
+#define HW_IR_CTRL_TOG                  HW(IR_CTRL_TOG)
+#define HWA_IR_CTRL_TOG                 (HWA_IR_CTRL + 0xc)
+#define HWT_IR_CTRL_TOG                 HWIO_32_WO
+#define HWN_IR_CTRL_TOG                 IR_CTRL
+#define HWI_IR_CTRL_TOG                 
+#define BP_IR_CTRL_SFTRST               31
+#define BM_IR_CTRL_SFTRST               0x80000000
+#define BV_IR_CTRL_SFTRST__RUN          0x0
+#define BV_IR_CTRL_SFTRST__RESET        0x1
+#define BF_IR_CTRL_SFTRST(v)            (((v) & 0x1) << 31)
+#define BFM_IR_CTRL_SFTRST(v)           BM_IR_CTRL_SFTRST
+#define BF_IR_CTRL_SFTRST_V(e)          BF_IR_CTRL_SFTRST(BV_IR_CTRL_SFTRST__##e)
+#define BFM_IR_CTRL_SFTRST_V(v)         BM_IR_CTRL_SFTRST
+#define BP_IR_CTRL_CLKGATE              30
+#define BM_IR_CTRL_CLKGATE              0x40000000
+#define BF_IR_CTRL_CLKGATE(v)           (((v) & 0x1) << 30)
+#define BFM_IR_CTRL_CLKGATE(v)          BM_IR_CTRL_CLKGATE
+#define BF_IR_CTRL_CLKGATE_V(e)         BF_IR_CTRL_CLKGATE(BV_IR_CTRL_CLKGATE__##e)
+#define BFM_IR_CTRL_CLKGATE_V(v)        BM_IR_CTRL_CLKGATE
+#define BP_IR_CTRL_MTA                  24
+#define BM_IR_CTRL_MTA                  0x7000000
+#define BV_IR_CTRL_MTA__MTA_10MS        0x0
+#define BV_IR_CTRL_MTA__MTA_5MS         0x1
+#define BV_IR_CTRL_MTA__MTA_1MS         0x2
+#define BV_IR_CTRL_MTA__MTA_500US       0x3
+#define BV_IR_CTRL_MTA__MTA_100US       0x4
+#define BV_IR_CTRL_MTA__MTA_50US        0x5
+#define BV_IR_CTRL_MTA__MTA_10US        0x6
+#define BV_IR_CTRL_MTA__MTA_0           0x7
+#define BF_IR_CTRL_MTA(v)               (((v) & 0x7) << 24)
+#define BFM_IR_CTRL_MTA(v)              BM_IR_CTRL_MTA
+#define BF_IR_CTRL_MTA_V(e)             BF_IR_CTRL_MTA(BV_IR_CTRL_MTA__##e)
+#define BFM_IR_CTRL_MTA_V(v)            BM_IR_CTRL_MTA
+#define BP_IR_CTRL_MODE                 22
+#define BM_IR_CTRL_MODE                 0xc00000
+#define BV_IR_CTRL_MODE__SIR            0x0
+#define BV_IR_CTRL_MODE__MIR            0x1
+#define BV_IR_CTRL_MODE__FIR            0x2
+#define BV_IR_CTRL_MODE__VFIR           0x3
+#define BF_IR_CTRL_MODE(v)              (((v) & 0x3) << 22)
+#define BFM_IR_CTRL_MODE(v)             BM_IR_CTRL_MODE
+#define BF_IR_CTRL_MODE_V(e)            BF_IR_CTRL_MODE(BV_IR_CTRL_MODE__##e)
+#define BFM_IR_CTRL_MODE_V(v)           BM_IR_CTRL_MODE
+#define BP_IR_CTRL_SPEED                19
+#define BM_IR_CTRL_SPEED                0x380000
+#define BV_IR_CTRL_SPEED__SPD000        0x0
+#define BV_IR_CTRL_SPEED__SPD001        0x1
+#define BV_IR_CTRL_SPEED__SPD010        0x2
+#define BV_IR_CTRL_SPEED__SPD011        0x3
+#define BV_IR_CTRL_SPEED__SPD100        0x4
+#define BV_IR_CTRL_SPEED__SPD101        0x5
+#define BF_IR_CTRL_SPEED(v)             (((v) & 0x7) << 19)
+#define BFM_IR_CTRL_SPEED(v)            BM_IR_CTRL_SPEED
+#define BF_IR_CTRL_SPEED_V(e)           BF_IR_CTRL_SPEED(BV_IR_CTRL_SPEED__##e)
+#define BFM_IR_CTRL_SPEED_V(v)          BM_IR_CTRL_SPEED
+#define BP_IR_CTRL_TC_TIME_DIV          8
+#define BM_IR_CTRL_TC_TIME_DIV          0x3f00
+#define BF_IR_CTRL_TC_TIME_DIV(v)       (((v) & 0x3f) << 8)
+#define BFM_IR_CTRL_TC_TIME_DIV(v)      BM_IR_CTRL_TC_TIME_DIV
+#define BF_IR_CTRL_TC_TIME_DIV_V(e)     BF_IR_CTRL_TC_TIME_DIV(BV_IR_CTRL_TC_TIME_DIV__##e)
+#define BFM_IR_CTRL_TC_TIME_DIV_V(v)    BM_IR_CTRL_TC_TIME_DIV
+#define BP_IR_CTRL_TC_TYPE              7
+#define BM_IR_CTRL_TC_TYPE              0x80
+#define BF_IR_CTRL_TC_TYPE(v)           (((v) & 0x1) << 7)
+#define BFM_IR_CTRL_TC_TYPE(v)          BM_IR_CTRL_TC_TYPE
+#define BF_IR_CTRL_TC_TYPE_V(e)         BF_IR_CTRL_TC_TYPE(BV_IR_CTRL_TC_TYPE__##e)
+#define BFM_IR_CTRL_TC_TYPE_V(v)        BM_IR_CTRL_TC_TYPE
+#define BP_IR_CTRL_SIR_GAP              4
+#define BM_IR_CTRL_SIR_GAP              0x70
+#define BV_IR_CTRL_SIR_GAP__GAP_10K     0x0
+#define BV_IR_CTRL_SIR_GAP__GAP_5K      0x1
+#define BV_IR_CTRL_SIR_GAP__GAP_1K      0x2
+#define BV_IR_CTRL_SIR_GAP__GAP_500     0x3
+#define BV_IR_CTRL_SIR_GAP__GAP_100     0x4
+#define BV_IR_CTRL_SIR_GAP__GAP_50      0x5
+#define BV_IR_CTRL_SIR_GAP__GAP_10      0x6
+#define BV_IR_CTRL_SIR_GAP__GAP_0       0x7
+#define BF_IR_CTRL_SIR_GAP(v)           (((v) & 0x7) << 4)
+#define BFM_IR_CTRL_SIR_GAP(v)          BM_IR_CTRL_SIR_GAP
+#define BF_IR_CTRL_SIR_GAP_V(e)         BF_IR_CTRL_SIR_GAP(BV_IR_CTRL_SIR_GAP__##e)
+#define BFM_IR_CTRL_SIR_GAP_V(v)        BM_IR_CTRL_SIR_GAP
+#define BP_IR_CTRL_SIPEN                3
+#define BM_IR_CTRL_SIPEN                0x8
+#define BF_IR_CTRL_SIPEN(v)             (((v) & 0x1) << 3)
+#define BFM_IR_CTRL_SIPEN(v)            BM_IR_CTRL_SIPEN
+#define BF_IR_CTRL_SIPEN_V(e)           BF_IR_CTRL_SIPEN(BV_IR_CTRL_SIPEN__##e)
+#define BFM_IR_CTRL_SIPEN_V(v)          BM_IR_CTRL_SIPEN
+#define BP_IR_CTRL_TCEN                 2
+#define BM_IR_CTRL_TCEN                 0x4
+#define BF_IR_CTRL_TCEN(v)              (((v) & 0x1) << 2)
+#define BFM_IR_CTRL_TCEN(v)             BM_IR_CTRL_TCEN
+#define BF_IR_CTRL_TCEN_V(e)            BF_IR_CTRL_TCEN(BV_IR_CTRL_TCEN__##e)
+#define BFM_IR_CTRL_TCEN_V(v)           BM_IR_CTRL_TCEN
+#define BP_IR_CTRL_TXEN                 1
+#define BM_IR_CTRL_TXEN                 0x2
+#define BF_IR_CTRL_TXEN(v)              (((v) & 0x1) << 1)
+#define BFM_IR_CTRL_TXEN(v)             BM_IR_CTRL_TXEN
+#define BF_IR_CTRL_TXEN_V(e)            BF_IR_CTRL_TXEN(BV_IR_CTRL_TXEN__##e)
+#define BFM_IR_CTRL_TXEN_V(v)           BM_IR_CTRL_TXEN
+#define BP_IR_CTRL_RXEN                 0
+#define BM_IR_CTRL_RXEN                 0x1
+#define BF_IR_CTRL_RXEN(v)              (((v) & 0x1) << 0)
+#define BFM_IR_CTRL_RXEN(v)             BM_IR_CTRL_RXEN
+#define BF_IR_CTRL_RXEN_V(e)            BF_IR_CTRL_RXEN(BV_IR_CTRL_RXEN__##e)
+#define BFM_IR_CTRL_RXEN_V(v)           BM_IR_CTRL_RXEN
+
+#define HW_IR_TXDMA                     HW(IR_TXDMA)
+#define HWA_IR_TXDMA                    (0x80078000 + 0x10)
+#define HWT_IR_TXDMA                    HWIO_32_RW
+#define HWN_IR_TXDMA                    IR_TXDMA
+#define HWI_IR_TXDMA                    
+#define HW_IR_TXDMA_SET                 HW(IR_TXDMA_SET)
+#define HWA_IR_TXDMA_SET                (HWA_IR_TXDMA + 0x4)
+#define HWT_IR_TXDMA_SET                HWIO_32_WO
+#define HWN_IR_TXDMA_SET                IR_TXDMA
+#define HWI_IR_TXDMA_SET                
+#define HW_IR_TXDMA_CLR                 HW(IR_TXDMA_CLR)
+#define HWA_IR_TXDMA_CLR                (HWA_IR_TXDMA + 0x8)
+#define HWT_IR_TXDMA_CLR                HWIO_32_WO
+#define HWN_IR_TXDMA_CLR                IR_TXDMA
+#define HWI_IR_TXDMA_CLR                
+#define HW_IR_TXDMA_TOG                 HW(IR_TXDMA_TOG)
+#define HWA_IR_TXDMA_TOG                (HWA_IR_TXDMA + 0xc)
+#define HWT_IR_TXDMA_TOG                HWIO_32_WO
+#define HWN_IR_TXDMA_TOG                IR_TXDMA
+#define HWI_IR_TXDMA_TOG                
+#define BP_IR_TXDMA_RUN                 31
+#define BM_IR_TXDMA_RUN                 0x80000000
+#define BF_IR_TXDMA_RUN(v)              (((v) & 0x1) << 31)
+#define BFM_IR_TXDMA_RUN(v)             BM_IR_TXDMA_RUN
+#define BF_IR_TXDMA_RUN_V(e)            BF_IR_TXDMA_RUN(BV_IR_TXDMA_RUN__##e)
+#define BFM_IR_TXDMA_RUN_V(v)           BM_IR_TXDMA_RUN
+#define BP_IR_TXDMA_EMPTY               29
+#define BM_IR_TXDMA_EMPTY               0x20000000
+#define BF_IR_TXDMA_EMPTY(v)            (((v) & 0x1) << 29)
+#define BFM_IR_TXDMA_EMPTY(v)           BM_IR_TXDMA_EMPTY
+#define BF_IR_TXDMA_EMPTY_V(e)          BF_IR_TXDMA_EMPTY(BV_IR_TXDMA_EMPTY__##e)
+#define BFM_IR_TXDMA_EMPTY_V(v)         BM_IR_TXDMA_EMPTY
+#define BP_IR_TXDMA_INT                 28
+#define BM_IR_TXDMA_INT                 0x10000000
+#define BF_IR_TXDMA_INT(v)              (((v) & 0x1) << 28)
+#define BFM_IR_TXDMA_INT(v)             BM_IR_TXDMA_INT
+#define BF_IR_TXDMA_INT_V(e)            BF_IR_TXDMA_INT(BV_IR_TXDMA_INT__##e)
+#define BFM_IR_TXDMA_INT_V(v)           BM_IR_TXDMA_INT
+#define BP_IR_TXDMA_CHANGE              27
+#define BM_IR_TXDMA_CHANGE              0x8000000
+#define BF_IR_TXDMA_CHANGE(v)           (((v) & 0x1) << 27)
+#define BFM_IR_TXDMA_CHANGE(v)          BM_IR_TXDMA_CHANGE
+#define BF_IR_TXDMA_CHANGE_V(e)         BF_IR_TXDMA_CHANGE(BV_IR_TXDMA_CHANGE__##e)
+#define BFM_IR_TXDMA_CHANGE_V(v)        BM_IR_TXDMA_CHANGE
+#define BP_IR_TXDMA_NEW_MTA             24
+#define BM_IR_TXDMA_NEW_MTA             0x7000000
+#define BF_IR_TXDMA_NEW_MTA(v)          (((v) & 0x7) << 24)
+#define BFM_IR_TXDMA_NEW_MTA(v)         BM_IR_TXDMA_NEW_MTA
+#define BF_IR_TXDMA_NEW_MTA_V(e)        BF_IR_TXDMA_NEW_MTA(BV_IR_TXDMA_NEW_MTA__##e)
+#define BFM_IR_TXDMA_NEW_MTA_V(v)       BM_IR_TXDMA_NEW_MTA
+#define BP_IR_TXDMA_NEW_MODE            22
+#define BM_IR_TXDMA_NEW_MODE            0xc00000
+#define BF_IR_TXDMA_NEW_MODE(v)         (((v) & 0x3) << 22)
+#define BFM_IR_TXDMA_NEW_MODE(v)        BM_IR_TXDMA_NEW_MODE
+#define BF_IR_TXDMA_NEW_MODE_V(e)       BF_IR_TXDMA_NEW_MODE(BV_IR_TXDMA_NEW_MODE__##e)
+#define BFM_IR_TXDMA_NEW_MODE_V(v)      BM_IR_TXDMA_NEW_MODE
+#define BP_IR_TXDMA_NEW_SPEED           19
+#define BM_IR_TXDMA_NEW_SPEED           0x380000
+#define BF_IR_TXDMA_NEW_SPEED(v)        (((v) & 0x7) << 19)
+#define BFM_IR_TXDMA_NEW_SPEED(v)       BM_IR_TXDMA_NEW_SPEED
+#define BF_IR_TXDMA_NEW_SPEED_V(e)      BF_IR_TXDMA_NEW_SPEED(BV_IR_TXDMA_NEW_SPEED__##e)
+#define BFM_IR_TXDMA_NEW_SPEED_V(v)     BM_IR_TXDMA_NEW_SPEED
+#define BP_IR_TXDMA_BOF_TYPE            18
+#define BM_IR_TXDMA_BOF_TYPE            0x40000
+#define BF_IR_TXDMA_BOF_TYPE(v)         (((v) & 0x1) << 18)
+#define BFM_IR_TXDMA_BOF_TYPE(v)        BM_IR_TXDMA_BOF_TYPE
+#define BF_IR_TXDMA_BOF_TYPE_V(e)       BF_IR_TXDMA_BOF_TYPE(BV_IR_TXDMA_BOF_TYPE__##e)
+#define BFM_IR_TXDMA_BOF_TYPE_V(v)      BM_IR_TXDMA_BOF_TYPE
+#define BP_IR_TXDMA_XBOFS               12
+#define BM_IR_TXDMA_XBOFS               0x3f000
+#define BF_IR_TXDMA_XBOFS(v)            (((v) & 0x3f) << 12)
+#define BFM_IR_TXDMA_XBOFS(v)           BM_IR_TXDMA_XBOFS
+#define BF_IR_TXDMA_XBOFS_V(e)          BF_IR_TXDMA_XBOFS(BV_IR_TXDMA_XBOFS__##e)
+#define BFM_IR_TXDMA_XBOFS_V(v)         BM_IR_TXDMA_XBOFS
+#define BP_IR_TXDMA_XFER_COUNT          0
+#define BM_IR_TXDMA_XFER_COUNT          0xfff
+#define BF_IR_TXDMA_XFER_COUNT(v)       (((v) & 0xfff) << 0)
+#define BFM_IR_TXDMA_XFER_COUNT(v)      BM_IR_TXDMA_XFER_COUNT
+#define BF_IR_TXDMA_XFER_COUNT_V(e)     BF_IR_TXDMA_XFER_COUNT(BV_IR_TXDMA_XFER_COUNT__##e)
+#define BFM_IR_TXDMA_XFER_COUNT_V(v)    BM_IR_TXDMA_XFER_COUNT
+
+#define HW_IR_RXDMA                     HW(IR_RXDMA)
+#define HWA_IR_RXDMA                    (0x80078000 + 0x20)
+#define HWT_IR_RXDMA                    HWIO_32_RW
+#define HWN_IR_RXDMA                    IR_RXDMA
+#define HWI_IR_RXDMA                    
+#define HW_IR_RXDMA_SET                 HW(IR_RXDMA_SET)
+#define HWA_IR_RXDMA_SET                (HWA_IR_RXDMA + 0x4)
+#define HWT_IR_RXDMA_SET                HWIO_32_WO
+#define HWN_IR_RXDMA_SET                IR_RXDMA
+#define HWI_IR_RXDMA_SET                
+#define HW_IR_RXDMA_CLR                 HW(IR_RXDMA_CLR)
+#define HWA_IR_RXDMA_CLR                (HWA_IR_RXDMA + 0x8)
+#define HWT_IR_RXDMA_CLR                HWIO_32_WO
+#define HWN_IR_RXDMA_CLR                IR_RXDMA
+#define HWI_IR_RXDMA_CLR                
+#define HW_IR_RXDMA_TOG                 HW(IR_RXDMA_TOG)
+#define HWA_IR_RXDMA_TOG                (HWA_IR_RXDMA + 0xc)
+#define HWT_IR_RXDMA_TOG                HWIO_32_WO
+#define HWN_IR_RXDMA_TOG                IR_RXDMA
+#define HWI_IR_RXDMA_TOG                
+#define BP_IR_RXDMA_RUN                 31
+#define BM_IR_RXDMA_RUN                 0x80000000
+#define BF_IR_RXDMA_RUN(v)              (((v) & 0x1) << 31)
+#define BFM_IR_RXDMA_RUN(v)             BM_IR_RXDMA_RUN
+#define BF_IR_RXDMA_RUN_V(e)            BF_IR_RXDMA_RUN(BV_IR_RXDMA_RUN__##e)
+#define BFM_IR_RXDMA_RUN_V(v)           BM_IR_RXDMA_RUN
+#define BP_IR_RXDMA_XFER_COUNT          0
+#define BM_IR_RXDMA_XFER_COUNT          0x3ff
+#define BF_IR_RXDMA_XFER_COUNT(v)       (((v) & 0x3ff) << 0)
+#define BFM_IR_RXDMA_XFER_COUNT(v)      BM_IR_RXDMA_XFER_COUNT
+#define BF_IR_RXDMA_XFER_COUNT_V(e)     BF_IR_RXDMA_XFER_COUNT(BV_IR_RXDMA_XFER_COUNT__##e)
+#define BFM_IR_RXDMA_XFER_COUNT_V(v)    BM_IR_RXDMA_XFER_COUNT
+
+#define HW_IR_DBGCTRL                   HW(IR_DBGCTRL)
+#define HWA_IR_DBGCTRL                  (0x80078000 + 0x30)
+#define HWT_IR_DBGCTRL                  HWIO_32_RW
+#define HWN_IR_DBGCTRL                  IR_DBGCTRL
+#define HWI_IR_DBGCTRL                  
+#define HW_IR_DBGCTRL_SET               HW(IR_DBGCTRL_SET)
+#define HWA_IR_DBGCTRL_SET              (HWA_IR_DBGCTRL + 0x4)
+#define HWT_IR_DBGCTRL_SET              HWIO_32_WO
+#define HWN_IR_DBGCTRL_SET              IR_DBGCTRL
+#define HWI_IR_DBGCTRL_SET              
+#define HW_IR_DBGCTRL_CLR               HW(IR_DBGCTRL_CLR)
+#define HWA_IR_DBGCTRL_CLR              (HWA_IR_DBGCTRL + 0x8)
+#define HWT_IR_DBGCTRL_CLR              HWIO_32_WO
+#define HWN_IR_DBGCTRL_CLR              IR_DBGCTRL
+#define HWI_IR_DBGCTRL_CLR              
+#define HW_IR_DBGCTRL_TOG               HW(IR_DBGCTRL_TOG)
+#define HWA_IR_DBGCTRL_TOG              (HWA_IR_DBGCTRL + 0xc)
+#define HWT_IR_DBGCTRL_TOG              HWIO_32_WO
+#define HWN_IR_DBGCTRL_TOG              IR_DBGCTRL
+#define HWI_IR_DBGCTRL_TOG              
+#define BP_IR_DBGCTRL_VFIRSWZ           12
+#define BM_IR_DBGCTRL_VFIRSWZ           0x1000
+#define BV_IR_DBGCTRL_VFIRSWZ__NORMAL   0x0
+#define BV_IR_DBGCTRL_VFIRSWZ__SWAP     0x1
+#define BF_IR_DBGCTRL_VFIRSWZ(v)        (((v) & 0x1) << 12)
+#define BFM_IR_DBGCTRL_VFIRSWZ(v)       BM_IR_DBGCTRL_VFIRSWZ
+#define BF_IR_DBGCTRL_VFIRSWZ_V(e)      BF_IR_DBGCTRL_VFIRSWZ(BV_IR_DBGCTRL_VFIRSWZ__##e)
+#define BFM_IR_DBGCTRL_VFIRSWZ_V(v)     BM_IR_DBGCTRL_VFIRSWZ
+#define BP_IR_DBGCTRL_RXFRMOFF          11
+#define BM_IR_DBGCTRL_RXFRMOFF          0x800
+#define BF_IR_DBGCTRL_RXFRMOFF(v)       (((v) & 0x1) << 11)
+#define BFM_IR_DBGCTRL_RXFRMOFF(v)      BM_IR_DBGCTRL_RXFRMOFF
+#define BF_IR_DBGCTRL_RXFRMOFF_V(e)     BF_IR_DBGCTRL_RXFRMOFF(BV_IR_DBGCTRL_RXFRMOFF__##e)
+#define BFM_IR_DBGCTRL_RXFRMOFF_V(v)    BM_IR_DBGCTRL_RXFRMOFF
+#define BP_IR_DBGCTRL_RXCRCOFF          10
+#define BM_IR_DBGCTRL_RXCRCOFF          0x400
+#define BF_IR_DBGCTRL_RXCRCOFF(v)       (((v) & 0x1) << 10)
+#define BFM_IR_DBGCTRL_RXCRCOFF(v)      BM_IR_DBGCTRL_RXCRCOFF
+#define BF_IR_DBGCTRL_RXCRCOFF_V(e)     BF_IR_DBGCTRL_RXCRCOFF(BV_IR_DBGCTRL_RXCRCOFF__##e)
+#define BFM_IR_DBGCTRL_RXCRCOFF_V(v)    BM_IR_DBGCTRL_RXCRCOFF
+#define BP_IR_DBGCTRL_RXINVERT          9
+#define BM_IR_DBGCTRL_RXINVERT          0x200
+#define BF_IR_DBGCTRL_RXINVERT(v)       (((v) & 0x1) << 9)
+#define BFM_IR_DBGCTRL_RXINVERT(v)      BM_IR_DBGCTRL_RXINVERT
+#define BF_IR_DBGCTRL_RXINVERT_V(e)     BF_IR_DBGCTRL_RXINVERT(BV_IR_DBGCTRL_RXINVERT__##e)
+#define BFM_IR_DBGCTRL_RXINVERT_V(v)    BM_IR_DBGCTRL_RXINVERT
+#define BP_IR_DBGCTRL_TXFRMOFF          8
+#define BM_IR_DBGCTRL_TXFRMOFF          0x100
+#define BF_IR_DBGCTRL_TXFRMOFF(v)       (((v) & 0x1) << 8)
+#define BFM_IR_DBGCTRL_TXFRMOFF(v)      BM_IR_DBGCTRL_TXFRMOFF
+#define BF_IR_DBGCTRL_TXFRMOFF_V(e)     BF_IR_DBGCTRL_TXFRMOFF(BV_IR_DBGCTRL_TXFRMOFF__##e)
+#define BFM_IR_DBGCTRL_TXFRMOFF_V(v)    BM_IR_DBGCTRL_TXFRMOFF
+#define BP_IR_DBGCTRL_TXCRCOFF          7
+#define BM_IR_DBGCTRL_TXCRCOFF          0x80
+#define BF_IR_DBGCTRL_TXCRCOFF(v)       (((v) & 0x1) << 7)
+#define BFM_IR_DBGCTRL_TXCRCOFF(v)      BM_IR_DBGCTRL_TXCRCOFF
+#define BF_IR_DBGCTRL_TXCRCOFF_V(e)     BF_IR_DBGCTRL_TXCRCOFF(BV_IR_DBGCTRL_TXCRCOFF__##e)
+#define BFM_IR_DBGCTRL_TXCRCOFF_V(v)    BM_IR_DBGCTRL_TXCRCOFF
+#define BP_IR_DBGCTRL_TXINVERT          6
+#define BM_IR_DBGCTRL_TXINVERT          0x40
+#define BF_IR_DBGCTRL_TXINVERT(v)       (((v) & 0x1) << 6)
+#define BFM_IR_DBGCTRL_TXINVERT(v)      BM_IR_DBGCTRL_TXINVERT
+#define BF_IR_DBGCTRL_TXINVERT_V(e)     BF_IR_DBGCTRL_TXINVERT(BV_IR_DBGCTRL_TXINVERT__##e)
+#define BFM_IR_DBGCTRL_TXINVERT_V(v)    BM_IR_DBGCTRL_TXINVERT
+#define BP_IR_DBGCTRL_INTLOOPBACK       5
+#define BM_IR_DBGCTRL_INTLOOPBACK       0x20
+#define BF_IR_DBGCTRL_INTLOOPBACK(v)    (((v) & 0x1) << 5)
+#define BFM_IR_DBGCTRL_INTLOOPBACK(v)   BM_IR_DBGCTRL_INTLOOPBACK
+#define BF_IR_DBGCTRL_INTLOOPBACK_V(e)  BF_IR_DBGCTRL_INTLOOPBACK(BV_IR_DBGCTRL_INTLOOPBACK__##e)
+#define BFM_IR_DBGCTRL_INTLOOPBACK_V(v) BM_IR_DBGCTRL_INTLOOPBACK
+#define BP_IR_DBGCTRL_DUPLEX            4
+#define BM_IR_DBGCTRL_DUPLEX            0x10
+#define BF_IR_DBGCTRL_DUPLEX(v)         (((v) & 0x1) << 4)
+#define BFM_IR_DBGCTRL_DUPLEX(v)        BM_IR_DBGCTRL_DUPLEX
+#define BF_IR_DBGCTRL_DUPLEX_V(e)       BF_IR_DBGCTRL_DUPLEX(BV_IR_DBGCTRL_DUPLEX__##e)
+#define BFM_IR_DBGCTRL_DUPLEX_V(v)      BM_IR_DBGCTRL_DUPLEX
+#define BP_IR_DBGCTRL_MIO_RX            3
+#define BM_IR_DBGCTRL_MIO_RX            0x8
+#define BF_IR_DBGCTRL_MIO_RX(v)         (((v) & 0x1) << 3)
+#define BFM_IR_DBGCTRL_MIO_RX(v)        BM_IR_DBGCTRL_MIO_RX
+#define BF_IR_DBGCTRL_MIO_RX_V(e)       BF_IR_DBGCTRL_MIO_RX(BV_IR_DBGCTRL_MIO_RX__##e)
+#define BFM_IR_DBGCTRL_MIO_RX_V(v)      BM_IR_DBGCTRL_MIO_RX
+#define BP_IR_DBGCTRL_MIO_TX            2
+#define BM_IR_DBGCTRL_MIO_TX            0x4
+#define BF_IR_DBGCTRL_MIO_TX(v)         (((v) & 0x1) << 2)
+#define BFM_IR_DBGCTRL_MIO_TX(v)        BM_IR_DBGCTRL_MIO_TX
+#define BF_IR_DBGCTRL_MIO_TX_V(e)       BF_IR_DBGCTRL_MIO_TX(BV_IR_DBGCTRL_MIO_TX__##e)
+#define BFM_IR_DBGCTRL_MIO_TX_V(v)      BM_IR_DBGCTRL_MIO_TX
+#define BP_IR_DBGCTRL_MIO_SCLK          1
+#define BM_IR_DBGCTRL_MIO_SCLK          0x2
+#define BF_IR_DBGCTRL_MIO_SCLK(v)       (((v) & 0x1) << 1)
+#define BFM_IR_DBGCTRL_MIO_SCLK(v)      BM_IR_DBGCTRL_MIO_SCLK
+#define BF_IR_DBGCTRL_MIO_SCLK_V(e)     BF_IR_DBGCTRL_MIO_SCLK(BV_IR_DBGCTRL_MIO_SCLK__##e)
+#define BFM_IR_DBGCTRL_MIO_SCLK_V(v)    BM_IR_DBGCTRL_MIO_SCLK
+#define BP_IR_DBGCTRL_MIO_EN            0
+#define BM_IR_DBGCTRL_MIO_EN            0x1
+#define BF_IR_DBGCTRL_MIO_EN(v)         (((v) & 0x1) << 0)
+#define BFM_IR_DBGCTRL_MIO_EN(v)        BM_IR_DBGCTRL_MIO_EN
+#define BF_IR_DBGCTRL_MIO_EN_V(e)       BF_IR_DBGCTRL_MIO_EN(BV_IR_DBGCTRL_MIO_EN__##e)
+#define BFM_IR_DBGCTRL_MIO_EN_V(v)      BM_IR_DBGCTRL_MIO_EN
+
+#define HW_IR_INTR                          HW(IR_INTR)
+#define HWA_IR_INTR                         (0x80078000 + 0x40)
+#define HWT_IR_INTR                         HWIO_32_RW
+#define HWN_IR_INTR                         IR_INTR
+#define HWI_IR_INTR                         
+#define HW_IR_INTR_SET                      HW(IR_INTR_SET)
+#define HWA_IR_INTR_SET                     (HWA_IR_INTR + 0x4)
+#define HWT_IR_INTR_SET                     HWIO_32_WO
+#define HWN_IR_INTR_SET                     IR_INTR
+#define HWI_IR_INTR_SET                     
+#define HW_IR_INTR_CLR                      HW(IR_INTR_CLR)
+#define HWA_IR_INTR_CLR                     (HWA_IR_INTR + 0x8)
+#define HWT_IR_INTR_CLR                     HWIO_32_WO
+#define HWN_IR_INTR_CLR                     IR_INTR
+#define HWI_IR_INTR_CLR                     
+#define HW_IR_INTR_TOG                      HW(IR_INTR_TOG)
+#define HWA_IR_INTR_TOG                     (HWA_IR_INTR + 0xc)
+#define HWT_IR_INTR_TOG                     HWIO_32_WO
+#define HWN_IR_INTR_TOG                     IR_INTR
+#define HWI_IR_INTR_TOG                     
+#define BP_IR_INTR_RXABORT_IRQ_EN           22
+#define BM_IR_INTR_RXABORT_IRQ_EN           0x400000
+#define BV_IR_INTR_RXABORT_IRQ_EN__DISABLED 0x0
+#define BV_IR_INTR_RXABORT_IRQ_EN__ENABLED  0x1
+#define BF_IR_INTR_RXABORT_IRQ_EN(v)        (((v) & 0x1) << 22)
+#define BFM_IR_INTR_RXABORT_IRQ_EN(v)       BM_IR_INTR_RXABORT_IRQ_EN
+#define BF_IR_INTR_RXABORT_IRQ_EN_V(e)      BF_IR_INTR_RXABORT_IRQ_EN(BV_IR_INTR_RXABORT_IRQ_EN__##e)
+#define BFM_IR_INTR_RXABORT_IRQ_EN_V(v)     BM_IR_INTR_RXABORT_IRQ_EN
+#define BP_IR_INTR_SPEED_IRQ_EN             21
+#define BM_IR_INTR_SPEED_IRQ_EN             0x200000
+#define BV_IR_INTR_SPEED_IRQ_EN__DISABLED   0x0
+#define BV_IR_INTR_SPEED_IRQ_EN__ENABLED    0x1
+#define BF_IR_INTR_SPEED_IRQ_EN(v)          (((v) & 0x1) << 21)
+#define BFM_IR_INTR_SPEED_IRQ_EN(v)         BM_IR_INTR_SPEED_IRQ_EN
+#define BF_IR_INTR_SPEED_IRQ_EN_V(e)        BF_IR_INTR_SPEED_IRQ_EN(BV_IR_INTR_SPEED_IRQ_EN__##e)
+#define BFM_IR_INTR_SPEED_IRQ_EN_V(v)       BM_IR_INTR_SPEED_IRQ_EN
+#define BP_IR_INTR_RXOF_IRQ_EN              20
+#define BM_IR_INTR_RXOF_IRQ_EN              0x100000
+#define BV_IR_INTR_RXOF_IRQ_EN__DISABLED    0x0
+#define BV_IR_INTR_RXOF_IRQ_EN__ENABLED     0x1
+#define BF_IR_INTR_RXOF_IRQ_EN(v)           (((v) & 0x1) << 20)
+#define BFM_IR_INTR_RXOF_IRQ_EN(v)          BM_IR_INTR_RXOF_IRQ_EN
+#define BF_IR_INTR_RXOF_IRQ_EN_V(e)         BF_IR_INTR_RXOF_IRQ_EN(BV_IR_INTR_RXOF_IRQ_EN__##e)
+#define BFM_IR_INTR_RXOF_IRQ_EN_V(v)        BM_IR_INTR_RXOF_IRQ_EN
+#define BP_IR_INTR_TXUF_IRQ_EN              19
+#define BM_IR_INTR_TXUF_IRQ_EN              0x80000
+#define BV_IR_INTR_TXUF_IRQ_EN__DISABLED    0x0
+#define BV_IR_INTR_TXUF_IRQ_EN__ENABLED     0x1
+#define BF_IR_INTR_TXUF_IRQ_EN(v)           (((v) & 0x1) << 19)
+#define BFM_IR_INTR_TXUF_IRQ_EN(v)          BM_IR_INTR_TXUF_IRQ_EN
+#define BF_IR_INTR_TXUF_IRQ_EN_V(e)         BF_IR_INTR_TXUF_IRQ_EN(BV_IR_INTR_TXUF_IRQ_EN__##e)
+#define BFM_IR_INTR_TXUF_IRQ_EN_V(v)        BM_IR_INTR_TXUF_IRQ_EN
+#define BP_IR_INTR_TC_IRQ_EN                18
+#define BM_IR_INTR_TC_IRQ_EN                0x40000
+#define BV_IR_INTR_TC_IRQ_EN__DISABLED      0x0
+#define BV_IR_INTR_TC_IRQ_EN__ENABLED       0x1
+#define BF_IR_INTR_TC_IRQ_EN(v)             (((v) & 0x1) << 18)
+#define BFM_IR_INTR_TC_IRQ_EN(v)            BM_IR_INTR_TC_IRQ_EN
+#define BF_IR_INTR_TC_IRQ_EN_V(e)           BF_IR_INTR_TC_IRQ_EN(BV_IR_INTR_TC_IRQ_EN__##e)
+#define BFM_IR_INTR_TC_IRQ_EN_V(v)          BM_IR_INTR_TC_IRQ_EN
+#define BP_IR_INTR_RX_IRQ_EN                17
+#define BM_IR_INTR_RX_IRQ_EN                0x20000
+#define BV_IR_INTR_RX_IRQ_EN__DISABLED      0x0
+#define BV_IR_INTR_RX_IRQ_EN__ENABLED       0x1
+#define BF_IR_INTR_RX_IRQ_EN(v)             (((v) & 0x1) << 17)
+#define BFM_IR_INTR_RX_IRQ_EN(v)            BM_IR_INTR_RX_IRQ_EN
+#define BF_IR_INTR_RX_IRQ_EN_V(e)           BF_IR_INTR_RX_IRQ_EN(BV_IR_INTR_RX_IRQ_EN__##e)
+#define BFM_IR_INTR_RX_IRQ_EN_V(v)          BM_IR_INTR_RX_IRQ_EN
+#define BP_IR_INTR_TX_IRQ_EN                16
+#define BM_IR_INTR_TX_IRQ_EN                0x10000
+#define BV_IR_INTR_TX_IRQ_EN__DISABLED      0x0
+#define BV_IR_INTR_TX_IRQ_EN__ENABLED       0x1
+#define BF_IR_INTR_TX_IRQ_EN(v)             (((v) & 0x1) << 16)
+#define BFM_IR_INTR_TX_IRQ_EN(v)            BM_IR_INTR_TX_IRQ_EN
+#define BF_IR_INTR_TX_IRQ_EN_V(e)           BF_IR_INTR_TX_IRQ_EN(BV_IR_INTR_TX_IRQ_EN__##e)
+#define BFM_IR_INTR_TX_IRQ_EN_V(v)          BM_IR_INTR_TX_IRQ_EN
+#define BP_IR_INTR_RXABORT_IRQ              6
+#define BM_IR_INTR_RXABORT_IRQ              0x40
+#define BV_IR_INTR_RXABORT_IRQ__NO_REQUEST  0x0
+#define BV_IR_INTR_RXABORT_IRQ__REQUEST     0x1
+#define BF_IR_INTR_RXABORT_IRQ(v)           (((v) & 0x1) << 6)
+#define BFM_IR_INTR_RXABORT_IRQ(v)          BM_IR_INTR_RXABORT_IRQ
+#define BF_IR_INTR_RXABORT_IRQ_V(e)         BF_IR_INTR_RXABORT_IRQ(BV_IR_INTR_RXABORT_IRQ__##e)
+#define BFM_IR_INTR_RXABORT_IRQ_V(v)        BM_IR_INTR_RXABORT_IRQ
+#define BP_IR_INTR_SPEED_IRQ                5
+#define BM_IR_INTR_SPEED_IRQ                0x20
+#define BV_IR_INTR_SPEED_IRQ__NO_REQUEST    0x0
+#define BV_IR_INTR_SPEED_IRQ__REQUEST       0x1
+#define BF_IR_INTR_SPEED_IRQ(v)             (((v) & 0x1) << 5)
+#define BFM_IR_INTR_SPEED_IRQ(v)            BM_IR_INTR_SPEED_IRQ
+#define BF_IR_INTR_SPEED_IRQ_V(e)           BF_IR_INTR_SPEED_IRQ(BV_IR_INTR_SPEED_IRQ__##e)
+#define BFM_IR_INTR_SPEED_IRQ_V(v)          BM_IR_INTR_SPEED_IRQ
+#define BP_IR_INTR_RXOF_IRQ                 4
+#define BM_IR_INTR_RXOF_IRQ                 0x10
+#define BV_IR_INTR_RXOF_IRQ__NO_REQUEST     0x0
+#define BV_IR_INTR_RXOF_IRQ__REQUEST        0x1
+#define BF_IR_INTR_RXOF_IRQ(v)              (((v) & 0x1) << 4)
+#define BFM_IR_INTR_RXOF_IRQ(v)             BM_IR_INTR_RXOF_IRQ
+#define BF_IR_INTR_RXOF_IRQ_V(e)            BF_IR_INTR_RXOF_IRQ(BV_IR_INTR_RXOF_IRQ__##e)
+#define BFM_IR_INTR_RXOF_IRQ_V(v)           BM_IR_INTR_RXOF_IRQ
+#define BP_IR_INTR_TXUF_IRQ                 3
+#define BM_IR_INTR_TXUF_IRQ                 0x8
+#define BV_IR_INTR_TXUF_IRQ__NO_REQUEST     0x0
+#define BV_IR_INTR_TXUF_IRQ__REQUEST        0x1
+#define BF_IR_INTR_TXUF_IRQ(v)              (((v) & 0x1) << 3)
+#define BFM_IR_INTR_TXUF_IRQ(v)             BM_IR_INTR_TXUF_IRQ
+#define BF_IR_INTR_TXUF_IRQ_V(e)            BF_IR_INTR_TXUF_IRQ(BV_IR_INTR_TXUF_IRQ__##e)
+#define BFM_IR_INTR_TXUF_IRQ_V(v)           BM_IR_INTR_TXUF_IRQ
+#define BP_IR_INTR_TC_IRQ                   2
+#define BM_IR_INTR_TC_IRQ                   0x4
+#define BV_IR_INTR_TC_IRQ__NO_REQUEST       0x0
+#define BV_IR_INTR_TC_IRQ__REQUEST          0x1
+#define BF_IR_INTR_TC_IRQ(v)                (((v) & 0x1) << 2)
+#define BFM_IR_INTR_TC_IRQ(v)               BM_IR_INTR_TC_IRQ
+#define BF_IR_INTR_TC_IRQ_V(e)              BF_IR_INTR_TC_IRQ(BV_IR_INTR_TC_IRQ__##e)
+#define BFM_IR_INTR_TC_IRQ_V(v)             BM_IR_INTR_TC_IRQ
+#define BP_IR_INTR_RX_IRQ                   1
+#define BM_IR_INTR_RX_IRQ                   0x2
+#define BV_IR_INTR_RX_IRQ__NO_REQUEST       0x0
+#define BV_IR_INTR_RX_IRQ__REQUEST          0x1
+#define BF_IR_INTR_RX_IRQ(v)                (((v) & 0x1) << 1)
+#define BFM_IR_INTR_RX_IRQ(v)               BM_IR_INTR_RX_IRQ
+#define BF_IR_INTR_RX_IRQ_V(e)              BF_IR_INTR_RX_IRQ(BV_IR_INTR_RX_IRQ__##e)
+#define BFM_IR_INTR_RX_IRQ_V(v)             BM_IR_INTR_RX_IRQ
+#define BP_IR_INTR_TX_IRQ                   0
+#define BM_IR_INTR_TX_IRQ                   0x1
+#define BV_IR_INTR_TX_IRQ__NO_REQUEST       0x0
+#define BV_IR_INTR_TX_IRQ__REQUEST          0x1
+#define BF_IR_INTR_TX_IRQ(v)                (((v) & 0x1) << 0)
+#define BFM_IR_INTR_TX_IRQ(v)               BM_IR_INTR_TX_IRQ
+#define BF_IR_INTR_TX_IRQ_V(e)              BF_IR_INTR_TX_IRQ(BV_IR_INTR_TX_IRQ__##e)
+#define BFM_IR_INTR_TX_IRQ_V(v)             BM_IR_INTR_TX_IRQ
+
+#define HW_IR_DATA              HW(IR_DATA)
+#define HWA_IR_DATA             (0x80078000 + 0x50)
+#define HWT_IR_DATA             HWIO_32_RW
+#define HWN_IR_DATA             IR_DATA
+#define HWI_IR_DATA             
+#define BP_IR_DATA_DATA         0
+#define BM_IR_DATA_DATA         0xffffffff
+#define BF_IR_DATA_DATA(v)      (((v) & 0xffffffff) << 0)
+#define BFM_IR_DATA_DATA(v)     BM_IR_DATA_DATA
+#define BF_IR_DATA_DATA_V(e)    BF_IR_DATA_DATA(BV_IR_DATA_DATA__##e)
+#define BFM_IR_DATA_DATA_V(v)   BM_IR_DATA_DATA
+
+#define HW_IR_STAT                              HW(IR_STAT)
+#define HWA_IR_STAT                             (0x80078000 + 0x60)
+#define HWT_IR_STAT                             HWIO_32_RW
+#define HWN_IR_STAT                             IR_STAT
+#define HWI_IR_STAT                             
+#define BP_IR_STAT_PRESENT                      31
+#define BM_IR_STAT_PRESENT                      0x80000000
+#define BV_IR_STAT_PRESENT__UNAVAILABLE         0x0
+#define BV_IR_STAT_PRESENT__AVAILABLE           0x1
+#define BF_IR_STAT_PRESENT(v)                   (((v) & 0x1) << 31)
+#define BFM_IR_STAT_PRESENT(v)                  BM_IR_STAT_PRESENT
+#define BF_IR_STAT_PRESENT_V(e)                 BF_IR_STAT_PRESENT(BV_IR_STAT_PRESENT__##e)
+#define BFM_IR_STAT_PRESENT_V(v)                BM_IR_STAT_PRESENT
+#define BP_IR_STAT_MODE_ALLOWED                 29
+#define BM_IR_STAT_MODE_ALLOWED                 0x60000000
+#define BV_IR_STAT_MODE_ALLOWED__VFIR           0x0
+#define BV_IR_STAT_MODE_ALLOWED__FIR            0x1
+#define BV_IR_STAT_MODE_ALLOWED__MIR            0x2
+#define BV_IR_STAT_MODE_ALLOWED__SIR            0x3
+#define BF_IR_STAT_MODE_ALLOWED(v)              (((v) & 0x3) << 29)
+#define BFM_IR_STAT_MODE_ALLOWED(v)             BM_IR_STAT_MODE_ALLOWED
+#define BF_IR_STAT_MODE_ALLOWED_V(e)            BF_IR_STAT_MODE_ALLOWED(BV_IR_STAT_MODE_ALLOWED__##e)
+#define BFM_IR_STAT_MODE_ALLOWED_V(v)           BM_IR_STAT_MODE_ALLOWED
+#define BP_IR_STAT_ANY_IRQ                      28
+#define BM_IR_STAT_ANY_IRQ                      0x10000000
+#define BV_IR_STAT_ANY_IRQ__NO_REQUEST          0x0
+#define BV_IR_STAT_ANY_IRQ__REQUEST             0x1
+#define BF_IR_STAT_ANY_IRQ(v)                   (((v) & 0x1) << 28)
+#define BFM_IR_STAT_ANY_IRQ(v)                  BM_IR_STAT_ANY_IRQ
+#define BF_IR_STAT_ANY_IRQ_V(e)                 BF_IR_STAT_ANY_IRQ(BV_IR_STAT_ANY_IRQ__##e)
+#define BFM_IR_STAT_ANY_IRQ_V(v)                BM_IR_STAT_ANY_IRQ
+#define BP_IR_STAT_RXABORT_SUMMARY              22
+#define BM_IR_STAT_RXABORT_SUMMARY              0x400000
+#define BV_IR_STAT_RXABORT_SUMMARY__NO_REQUEST  0x0
+#define BV_IR_STAT_RXABORT_SUMMARY__REQUEST     0x1
+#define BF_IR_STAT_RXABORT_SUMMARY(v)           (((v) & 0x1) << 22)
+#define BFM_IR_STAT_RXABORT_SUMMARY(v)          BM_IR_STAT_RXABORT_SUMMARY
+#define BF_IR_STAT_RXABORT_SUMMARY_V(e)         BF_IR_STAT_RXABORT_SUMMARY(BV_IR_STAT_RXABORT_SUMMARY__##e)
+#define BFM_IR_STAT_RXABORT_SUMMARY_V(v)        BM_IR_STAT_RXABORT_SUMMARY
+#define BP_IR_STAT_SPEED_SUMMARY                21
+#define BM_IR_STAT_SPEED_SUMMARY                0x200000
+#define BV_IR_STAT_SPEED_SUMMARY__NO_REQUEST    0x0
+#define BV_IR_STAT_SPEED_SUMMARY__REQUEST       0x1
+#define BF_IR_STAT_SPEED_SUMMARY(v)             (((v) & 0x1) << 21)
+#define BFM_IR_STAT_SPEED_SUMMARY(v)            BM_IR_STAT_SPEED_SUMMARY
+#define BF_IR_STAT_SPEED_SUMMARY_V(e)           BF_IR_STAT_SPEED_SUMMARY(BV_IR_STAT_SPEED_SUMMARY__##e)
+#define BFM_IR_STAT_SPEED_SUMMARY_V(v)          BM_IR_STAT_SPEED_SUMMARY
+#define BP_IR_STAT_RXOF_SUMMARY                 20
+#define BM_IR_STAT_RXOF_SUMMARY                 0x100000
+#define BV_IR_STAT_RXOF_SUMMARY__NO_REQUEST     0x0
+#define BV_IR_STAT_RXOF_SUMMARY__REQUEST        0x1
+#define BF_IR_STAT_RXOF_SUMMARY(v)              (((v) & 0x1) << 20)
+#define BFM_IR_STAT_RXOF_SUMMARY(v)             BM_IR_STAT_RXOF_SUMMARY
+#define BF_IR_STAT_RXOF_SUMMARY_V(e)            BF_IR_STAT_RXOF_SUMMARY(BV_IR_STAT_RXOF_SUMMARY__##e)
+#define BFM_IR_STAT_RXOF_SUMMARY_V(v)           BM_IR_STAT_RXOF_SUMMARY
+#define BP_IR_STAT_TXUF_SUMMARY                 19
+#define BM_IR_STAT_TXUF_SUMMARY                 0x80000
+#define BV_IR_STAT_TXUF_SUMMARY__NO_REQUEST     0x0
+#define BV_IR_STAT_TXUF_SUMMARY__REQUEST        0x1
+#define BF_IR_STAT_TXUF_SUMMARY(v)              (((v) & 0x1) << 19)
+#define BFM_IR_STAT_TXUF_SUMMARY(v)             BM_IR_STAT_TXUF_SUMMARY
+#define BF_IR_STAT_TXUF_SUMMARY_V(e)            BF_IR_STAT_TXUF_SUMMARY(BV_IR_STAT_TXUF_SUMMARY__##e)
+#define BFM_IR_STAT_TXUF_SUMMARY_V(v)           BM_IR_STAT_TXUF_SUMMARY
+#define BP_IR_STAT_TC_SUMMARY                   18
+#define BM_IR_STAT_TC_SUMMARY                   0x40000
+#define BV_IR_STAT_TC_SUMMARY__NO_REQUEST       0x0
+#define BV_IR_STAT_TC_SUMMARY__REQUEST          0x1
+#define BF_IR_STAT_TC_SUMMARY(v)                (((v) & 0x1) << 18)
+#define BFM_IR_STAT_TC_SUMMARY(v)               BM_IR_STAT_TC_SUMMARY
+#define BF_IR_STAT_TC_SUMMARY_V(e)              BF_IR_STAT_TC_SUMMARY(BV_IR_STAT_TC_SUMMARY__##e)
+#define BFM_IR_STAT_TC_SUMMARY_V(v)             BM_IR_STAT_TC_SUMMARY
+#define BP_IR_STAT_RX_SUMMARY                   17
+#define BM_IR_STAT_RX_SUMMARY                   0x20000
+#define BV_IR_STAT_RX_SUMMARY__NO_REQUEST       0x0
+#define BV_IR_STAT_RX_SUMMARY__REQUEST          0x1
+#define BF_IR_STAT_RX_SUMMARY(v)                (((v) & 0x1) << 17)
+#define BFM_IR_STAT_RX_SUMMARY(v)               BM_IR_STAT_RX_SUMMARY
+#define BF_IR_STAT_RX_SUMMARY_V(e)              BF_IR_STAT_RX_SUMMARY(BV_IR_STAT_RX_SUMMARY__##e)
+#define BFM_IR_STAT_RX_SUMMARY_V(v)             BM_IR_STAT_RX_SUMMARY
+#define BP_IR_STAT_TX_SUMMARY                   16
+#define BM_IR_STAT_TX_SUMMARY                   0x10000
+#define BV_IR_STAT_TX_SUMMARY__NO_REQUEST       0x0
+#define BV_IR_STAT_TX_SUMMARY__REQUEST          0x1
+#define BF_IR_STAT_TX_SUMMARY(v)                (((v) & 0x1) << 16)
+#define BFM_IR_STAT_TX_SUMMARY(v)               BM_IR_STAT_TX_SUMMARY
+#define BF_IR_STAT_TX_SUMMARY_V(e)              BF_IR_STAT_TX_SUMMARY(BV_IR_STAT_TX_SUMMARY__##e)
+#define BFM_IR_STAT_TX_SUMMARY_V(v)             BM_IR_STAT_TX_SUMMARY
+#define BP_IR_STAT_MEDIA_BUSY                   2
+#define BM_IR_STAT_MEDIA_BUSY                   0x4
+#define BF_IR_STAT_MEDIA_BUSY(v)                (((v) & 0x1) << 2)
+#define BFM_IR_STAT_MEDIA_BUSY(v)               BM_IR_STAT_MEDIA_BUSY
+#define BF_IR_STAT_MEDIA_BUSY_V(e)              BF_IR_STAT_MEDIA_BUSY(BV_IR_STAT_MEDIA_BUSY__##e)
+#define BFM_IR_STAT_MEDIA_BUSY_V(v)             BM_IR_STAT_MEDIA_BUSY
+#define BP_IR_STAT_RX_ACTIVE                    1
+#define BM_IR_STAT_RX_ACTIVE                    0x2
+#define BF_IR_STAT_RX_ACTIVE(v)                 (((v) & 0x1) << 1)
+#define BFM_IR_STAT_RX_ACTIVE(v)                BM_IR_STAT_RX_ACTIVE
+#define BF_IR_STAT_RX_ACTIVE_V(e)               BF_IR_STAT_RX_ACTIVE(BV_IR_STAT_RX_ACTIVE__##e)
+#define BFM_IR_STAT_RX_ACTIVE_V(v)              BM_IR_STAT_RX_ACTIVE
+#define BP_IR_STAT_TX_ACTIVE                    0
+#define BM_IR_STAT_TX_ACTIVE                    0x1
+#define BF_IR_STAT_TX_ACTIVE(v)                 (((v) & 0x1) << 0)
+#define BFM_IR_STAT_TX_ACTIVE(v)                BM_IR_STAT_TX_ACTIVE
+#define BF_IR_STAT_TX_ACTIVE_V(e)               BF_IR_STAT_TX_ACTIVE(BV_IR_STAT_TX_ACTIVE__##e)
+#define BFM_IR_STAT_TX_ACTIVE_V(v)              BM_IR_STAT_TX_ACTIVE
+
+#define HW_IR_TCCTRL                HW(IR_TCCTRL)
+#define HWA_IR_TCCTRL               (0x80078000 + 0x70)
+#define HWT_IR_TCCTRL               HWIO_32_RW
+#define HWN_IR_TCCTRL               IR_TCCTRL
+#define HWI_IR_TCCTRL               
+#define HW_IR_TCCTRL_SET            HW(IR_TCCTRL_SET)
+#define HWA_IR_TCCTRL_SET           (HWA_IR_TCCTRL + 0x4)
+#define HWT_IR_TCCTRL_SET           HWIO_32_WO
+#define HWN_IR_TCCTRL_SET           IR_TCCTRL
+#define HWI_IR_TCCTRL_SET           
+#define HW_IR_TCCTRL_CLR            HW(IR_TCCTRL_CLR)
+#define HWA_IR_TCCTRL_CLR           (HWA_IR_TCCTRL + 0x8)
+#define HWT_IR_TCCTRL_CLR           HWIO_32_WO
+#define HWN_IR_TCCTRL_CLR           IR_TCCTRL
+#define HWI_IR_TCCTRL_CLR           
+#define HW_IR_TCCTRL_TOG            HW(IR_TCCTRL_TOG)
+#define HWA_IR_TCCTRL_TOG           (HWA_IR_TCCTRL + 0xc)
+#define HWT_IR_TCCTRL_TOG           HWIO_32_WO
+#define HWN_IR_TCCTRL_TOG           IR_TCCTRL
+#define HWI_IR_TCCTRL_TOG           
+#define BP_IR_TCCTRL_INIT           31
+#define BM_IR_TCCTRL_INIT           0x80000000
+#define BF_IR_TCCTRL_INIT(v)        (((v) & 0x1) << 31)
+#define BFM_IR_TCCTRL_INIT(v)       BM_IR_TCCTRL_INIT
+#define BF_IR_TCCTRL_INIT_V(e)      BF_IR_TCCTRL_INIT(BV_IR_TCCTRL_INIT__##e)
+#define BFM_IR_TCCTRL_INIT_V(v)     BM_IR_TCCTRL_INIT
+#define BP_IR_TCCTRL_GO             30
+#define BM_IR_TCCTRL_GO             0x40000000
+#define BF_IR_TCCTRL_GO(v)          (((v) & 0x1) << 30)
+#define BFM_IR_TCCTRL_GO(v)         BM_IR_TCCTRL_GO
+#define BF_IR_TCCTRL_GO_V(e)        BF_IR_TCCTRL_GO(BV_IR_TCCTRL_GO__##e)
+#define BFM_IR_TCCTRL_GO_V(v)       BM_IR_TCCTRL_GO
+#define BP_IR_TCCTRL_BUSY           29
+#define BM_IR_TCCTRL_BUSY           0x20000000
+#define BF_IR_TCCTRL_BUSY(v)        (((v) & 0x1) << 29)
+#define BFM_IR_TCCTRL_BUSY(v)       BM_IR_TCCTRL_BUSY
+#define BF_IR_TCCTRL_BUSY_V(e)      BF_IR_TCCTRL_BUSY(BV_IR_TCCTRL_BUSY__##e)
+#define BFM_IR_TCCTRL_BUSY_V(v)     BM_IR_TCCTRL_BUSY
+#define BP_IR_TCCTRL_TEMIC          24
+#define BM_IR_TCCTRL_TEMIC          0x1000000
+#define BV_IR_TCCTRL_TEMIC__LOW     0x0
+#define BV_IR_TCCTRL_TEMIC__HIGH    0x1
+#define BF_IR_TCCTRL_TEMIC(v)       (((v) & 0x1) << 24)
+#define BFM_IR_TCCTRL_TEMIC(v)      BM_IR_TCCTRL_TEMIC
+#define BF_IR_TCCTRL_TEMIC_V(e)     BF_IR_TCCTRL_TEMIC(BV_IR_TCCTRL_TEMIC__##e)
+#define BFM_IR_TCCTRL_TEMIC_V(v)    BM_IR_TCCTRL_TEMIC
+#define BP_IR_TCCTRL_EXT_DATA       16
+#define BM_IR_TCCTRL_EXT_DATA       0xff0000
+#define BF_IR_TCCTRL_EXT_DATA(v)    (((v) & 0xff) << 16)
+#define BFM_IR_TCCTRL_EXT_DATA(v)   BM_IR_TCCTRL_EXT_DATA
+#define BF_IR_TCCTRL_EXT_DATA_V(e)  BF_IR_TCCTRL_EXT_DATA(BV_IR_TCCTRL_EXT_DATA__##e)
+#define BFM_IR_TCCTRL_EXT_DATA_V(v) BM_IR_TCCTRL_EXT_DATA
+#define BP_IR_TCCTRL_DATA           8
+#define BM_IR_TCCTRL_DATA           0xff00
+#define BF_IR_TCCTRL_DATA(v)        (((v) & 0xff) << 8)
+#define BFM_IR_TCCTRL_DATA(v)       BM_IR_TCCTRL_DATA
+#define BF_IR_TCCTRL_DATA_V(e)      BF_IR_TCCTRL_DATA(BV_IR_TCCTRL_DATA__##e)
+#define BFM_IR_TCCTRL_DATA_V(v)     BM_IR_TCCTRL_DATA
+#define BP_IR_TCCTRL_ADDR           5
+#define BM_IR_TCCTRL_ADDR           0xe0
+#define BF_IR_TCCTRL_ADDR(v)        (((v) & 0x7) << 5)
+#define BFM_IR_TCCTRL_ADDR(v)       BM_IR_TCCTRL_ADDR
+#define BF_IR_TCCTRL_ADDR_V(e)      BF_IR_TCCTRL_ADDR(BV_IR_TCCTRL_ADDR__##e)
+#define BFM_IR_TCCTRL_ADDR_V(v)     BM_IR_TCCTRL_ADDR
+#define BP_IR_TCCTRL_INDX           1
+#define BM_IR_TCCTRL_INDX           0x1e
+#define BF_IR_TCCTRL_INDX(v)        (((v) & 0xf) << 1)
+#define BFM_IR_TCCTRL_INDX(v)       BM_IR_TCCTRL_INDX
+#define BF_IR_TCCTRL_INDX_V(e)      BF_IR_TCCTRL_INDX(BV_IR_TCCTRL_INDX__##e)
+#define BFM_IR_TCCTRL_INDX_V(v)     BM_IR_TCCTRL_INDX
+#define BP_IR_TCCTRL_C              0
+#define BM_IR_TCCTRL_C              0x1
+#define BF_IR_TCCTRL_C(v)           (((v) & 0x1) << 0)
+#define BFM_IR_TCCTRL_C(v)          BM_IR_TCCTRL_C
+#define BF_IR_TCCTRL_C_V(e)         BF_IR_TCCTRL_C(BV_IR_TCCTRL_C__##e)
+#define BFM_IR_TCCTRL_C_V(v)        BM_IR_TCCTRL_C
+
+#define HW_IR_SI_READ               HW(IR_SI_READ)
+#define HWA_IR_SI_READ              (0x80078000 + 0x80)
+#define HWT_IR_SI_READ              HWIO_32_RW
+#define HWN_IR_SI_READ              IR_SI_READ
+#define HWI_IR_SI_READ              
+#define BP_IR_SI_READ_ABORT         8
+#define BM_IR_SI_READ_ABORT         0x100
+#define BF_IR_SI_READ_ABORT(v)      (((v) & 0x1) << 8)
+#define BFM_IR_SI_READ_ABORT(v)     BM_IR_SI_READ_ABORT
+#define BF_IR_SI_READ_ABORT_V(e)    BF_IR_SI_READ_ABORT(BV_IR_SI_READ_ABORT__##e)
+#define BFM_IR_SI_READ_ABORT_V(v)   BM_IR_SI_READ_ABORT
+#define BP_IR_SI_READ_DATA          0
+#define BM_IR_SI_READ_DATA          0xff
+#define BF_IR_SI_READ_DATA(v)       (((v) & 0xff) << 0)
+#define BFM_IR_SI_READ_DATA(v)      BM_IR_SI_READ_DATA
+#define BF_IR_SI_READ_DATA_V(e)     BF_IR_SI_READ_DATA(BV_IR_SI_READ_DATA__##e)
+#define BFM_IR_SI_READ_DATA_V(v)    BM_IR_SI_READ_DATA
+
+#define HW_IR_DEBUG                 HW(IR_DEBUG)
+#define HWA_IR_DEBUG                (0x80078000 + 0x90)
+#define HWT_IR_DEBUG                HWIO_32_RW
+#define HWN_IR_DEBUG                IR_DEBUG
+#define HWI_IR_DEBUG                
+#define BP_IR_DEBUG_TXDMAKICK       5
+#define BM_IR_DEBUG_TXDMAKICK       0x20
+#define BF_IR_DEBUG_TXDMAKICK(v)    (((v) & 0x1) << 5)
+#define BFM_IR_DEBUG_TXDMAKICK(v)   BM_IR_DEBUG_TXDMAKICK
+#define BF_IR_DEBUG_TXDMAKICK_V(e)  BF_IR_DEBUG_TXDMAKICK(BV_IR_DEBUG_TXDMAKICK__##e)
+#define BFM_IR_DEBUG_TXDMAKICK_V(v) BM_IR_DEBUG_TXDMAKICK
+#define BP_IR_DEBUG_RXDMAKICK       4
+#define BM_IR_DEBUG_RXDMAKICK       0x10
+#define BF_IR_DEBUG_RXDMAKICK(v)    (((v) & 0x1) << 4)
+#define BFM_IR_DEBUG_RXDMAKICK(v)   BM_IR_DEBUG_RXDMAKICK
+#define BF_IR_DEBUG_RXDMAKICK_V(e)  BF_IR_DEBUG_RXDMAKICK(BV_IR_DEBUG_RXDMAKICK__##e)
+#define BFM_IR_DEBUG_RXDMAKICK_V(v) BM_IR_DEBUG_RXDMAKICK
+#define BP_IR_DEBUG_TXDMAEND        3
+#define BM_IR_DEBUG_TXDMAEND        0x8
+#define BF_IR_DEBUG_TXDMAEND(v)     (((v) & 0x1) << 3)
+#define BFM_IR_DEBUG_TXDMAEND(v)    BM_IR_DEBUG_TXDMAEND
+#define BF_IR_DEBUG_TXDMAEND_V(e)   BF_IR_DEBUG_TXDMAEND(BV_IR_DEBUG_TXDMAEND__##e)
+#define BFM_IR_DEBUG_TXDMAEND_V(v)  BM_IR_DEBUG_TXDMAEND
+#define BP_IR_DEBUG_RXDMAEND        2
+#define BM_IR_DEBUG_RXDMAEND        0x4
+#define BF_IR_DEBUG_RXDMAEND(v)     (((v) & 0x1) << 2)
+#define BFM_IR_DEBUG_RXDMAEND(v)    BM_IR_DEBUG_RXDMAEND
+#define BF_IR_DEBUG_RXDMAEND_V(e)   BF_IR_DEBUG_RXDMAEND(BV_IR_DEBUG_RXDMAEND__##e)
+#define BFM_IR_DEBUG_RXDMAEND_V(v)  BM_IR_DEBUG_RXDMAEND
+#define BP_IR_DEBUG_TXDMAREQ        1
+#define BM_IR_DEBUG_TXDMAREQ        0x2
+#define BF_IR_DEBUG_TXDMAREQ(v)     (((v) & 0x1) << 1)
+#define BFM_IR_DEBUG_TXDMAREQ(v)    BM_IR_DEBUG_TXDMAREQ
+#define BF_IR_DEBUG_TXDMAREQ_V(e)   BF_IR_DEBUG_TXDMAREQ(BV_IR_DEBUG_TXDMAREQ__##e)
+#define BFM_IR_DEBUG_TXDMAREQ_V(v)  BM_IR_DEBUG_TXDMAREQ
+#define BP_IR_DEBUG_RXDMAREQ        0
+#define BM_IR_DEBUG_RXDMAREQ        0x1
+#define BF_IR_DEBUG_RXDMAREQ(v)     (((v) & 0x1) << 0)
+#define BFM_IR_DEBUG_RXDMAREQ(v)    BM_IR_DEBUG_RXDMAREQ
+#define BF_IR_DEBUG_RXDMAREQ_V(e)   BF_IR_DEBUG_RXDMAREQ(BV_IR_DEBUG_RXDMAREQ__##e)
+#define BFM_IR_DEBUG_RXDMAREQ_V(v)  BM_IR_DEBUG_RXDMAREQ
+
+#define HW_IR_VERSION               HW(IR_VERSION)
+#define HWA_IR_VERSION              (0x80078000 + 0xa0)
+#define HWT_IR_VERSION              HWIO_32_RW
+#define HWN_IR_VERSION              IR_VERSION
+#define HWI_IR_VERSION              
+#define BP_IR_VERSION_MAJOR         24
+#define BM_IR_VERSION_MAJOR         0xff000000
+#define BF_IR_VERSION_MAJOR(v)      (((v) & 0xff) << 24)
+#define BFM_IR_VERSION_MAJOR(v)     BM_IR_VERSION_MAJOR
+#define BF_IR_VERSION_MAJOR_V(e)    BF_IR_VERSION_MAJOR(BV_IR_VERSION_MAJOR__##e)
+#define BFM_IR_VERSION_MAJOR_V(v)   BM_IR_VERSION_MAJOR
+#define BP_IR_VERSION_MINOR         16
+#define BM_IR_VERSION_MINOR         0xff0000
+#define BF_IR_VERSION_MINOR(v)      (((v) & 0xff) << 16)
+#define BFM_IR_VERSION_MINOR(v)     BM_IR_VERSION_MINOR
+#define BF_IR_VERSION_MINOR_V(e)    BF_IR_VERSION_MINOR(BV_IR_VERSION_MINOR__##e)
+#define BFM_IR_VERSION_MINOR_V(v)   BM_IR_VERSION_MINOR
+#define BP_IR_VERSION_STEP          0
+#define BM_IR_VERSION_STEP          0xffff
+#define BF_IR_VERSION_STEP(v)       (((v) & 0xffff) << 0)
+#define BFM_IR_VERSION_STEP(v)      BM_IR_VERSION_STEP
+#define BF_IR_VERSION_STEP_V(e)     BF_IR_VERSION_STEP(BV_IR_VERSION_STEP__##e)
+#define BFM_IR_VERSION_STEP_V(v)    BM_IR_VERSION_STEP
+
+#endif /* __HEADERGEN_STMP3700_IR_H__*/
diff --git a/firmware/target/arm/imx233/regs/stmp3700/lcdif.h b/firmware/target/arm/imx233/regs/stmp3700/lcdif.h
new file mode 100644
index 0000000000..fef1b252bf
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3700/lcdif.h
@@ -0,0 +1,724 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * stmp3700 version: 2.4.0
+ * stmp3700 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_STMP3700_LCDIF_H__
+#define __HEADERGEN_STMP3700_LCDIF_H__
+
+#define HW_LCDIF_CTRL                                       HW(LCDIF_CTRL)
+#define HWA_LCDIF_CTRL                                      (0x80030000 + 0x0)
+#define HWT_LCDIF_CTRL                                      HWIO_32_RW
+#define HWN_LCDIF_CTRL                                      LCDIF_CTRL
+#define HWI_LCDIF_CTRL                                      
+#define HW_LCDIF_CTRL_SET                                   HW(LCDIF_CTRL_SET)
+#define HWA_LCDIF_CTRL_SET                                  (HWA_LCDIF_CTRL + 0x4)
+#define HWT_LCDIF_CTRL_SET                                  HWIO_32_WO
+#define HWN_LCDIF_CTRL_SET                                  LCDIF_CTRL
+#define HWI_LCDIF_CTRL_SET                                  
+#define HW_LCDIF_CTRL_CLR                                   HW(LCDIF_CTRL_CLR)
+#define HWA_LCDIF_CTRL_CLR                                  (HWA_LCDIF_CTRL + 0x8)
+#define HWT_LCDIF_CTRL_CLR                                  HWIO_32_WO
+#define HWN_LCDIF_CTRL_CLR                                  LCDIF_CTRL
+#define HWI_LCDIF_CTRL_CLR                                  
+#define HW_LCDIF_CTRL_TOG                                   HW(LCDIF_CTRL_TOG)
+#define HWA_LCDIF_CTRL_TOG                                  (HWA_LCDIF_CTRL + 0xc)
+#define HWT_LCDIF_CTRL_TOG                                  HWIO_32_WO
+#define HWN_LCDIF_CTRL_TOG                                  LCDIF_CTRL
+#define HWI_LCDIF_CTRL_TOG                                  
+#define BP_LCDIF_CTRL_SFTRST                                31
+#define BM_LCDIF_CTRL_SFTRST                                0x80000000
+#define BF_LCDIF_CTRL_SFTRST(v)                             (((v) & 0x1) << 31)
+#define BFM_LCDIF_CTRL_SFTRST(v)                            BM_LCDIF_CTRL_SFTRST
+#define BF_LCDIF_CTRL_SFTRST_V(e)                           BF_LCDIF_CTRL_SFTRST(BV_LCDIF_CTRL_SFTRST__##e)
+#define BFM_LCDIF_CTRL_SFTRST_V(v)                          BM_LCDIF_CTRL_SFTRST
+#define BP_LCDIF_CTRL_CLKGATE                               30
+#define BM_LCDIF_CTRL_CLKGATE                               0x40000000
+#define BF_LCDIF_CTRL_CLKGATE(v)                            (((v) & 0x1) << 30)
+#define BFM_LCDIF_CTRL_CLKGATE(v)                           BM_LCDIF_CTRL_CLKGATE
+#define BF_LCDIF_CTRL_CLKGATE_V(e)                          BF_LCDIF_CTRL_CLKGATE(BV_LCDIF_CTRL_CLKGATE__##e)
+#define BFM_LCDIF_CTRL_CLKGATE_V(v)                         BM_LCDIF_CTRL_CLKGATE
+#define BP_LCDIF_CTRL_READ_WRITEB                           29
+#define BM_LCDIF_CTRL_READ_WRITEB                           0x20000000
+#define BF_LCDIF_CTRL_READ_WRITEB(v)                        (((v) & 0x1) << 29)
+#define BFM_LCDIF_CTRL_READ_WRITEB(v)                       BM_LCDIF_CTRL_READ_WRITEB
+#define BF_LCDIF_CTRL_READ_WRITEB_V(e)                      BF_LCDIF_CTRL_READ_WRITEB(BV_LCDIF_CTRL_READ_WRITEB__##e)
+#define BFM_LCDIF_CTRL_READ_WRITEB_V(v)                     BM_LCDIF_CTRL_READ_WRITEB
+#define BP_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE                   28
+#define BM_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE                   0x10000000
+#define BF_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE(v)                (((v) & 0x1) << 28)
+#define BFM_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE(v)               BM_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE
+#define BF_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE_V(e)              BF_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE(BV_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE__##e)
+#define BFM_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE_V(v)             BM_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE
+#define BP_LCDIF_CTRL_DATA_SHIFT_DIR                        27
+#define BM_LCDIF_CTRL_DATA_SHIFT_DIR                        0x8000000
+#define BV_LCDIF_CTRL_DATA_SHIFT_DIR__TXDATA_SHIFT_LEFT     0x0
+#define BV_LCDIF_CTRL_DATA_SHIFT_DIR__TXDATA_SHIFT_RIGHT    0x1
+#define BF_LCDIF_CTRL_DATA_SHIFT_DIR(v)                     (((v) & 0x1) << 27)
+#define BFM_LCDIF_CTRL_DATA_SHIFT_DIR(v)                    BM_LCDIF_CTRL_DATA_SHIFT_DIR
+#define BF_LCDIF_CTRL_DATA_SHIFT_DIR_V(e)                   BF_LCDIF_CTRL_DATA_SHIFT_DIR(BV_LCDIF_CTRL_DATA_SHIFT_DIR__##e)
+#define BFM_LCDIF_CTRL_DATA_SHIFT_DIR_V(v)                  BM_LCDIF_CTRL_DATA_SHIFT_DIR
+#define BP_LCDIF_CTRL_SHIFT_NUM_BITS                        25
+#define BM_LCDIF_CTRL_SHIFT_NUM_BITS                        0x6000000
+#define BF_LCDIF_CTRL_SHIFT_NUM_BITS(v)                     (((v) & 0x3) << 25)
+#define BFM_LCDIF_CTRL_SHIFT_NUM_BITS(v)                    BM_LCDIF_CTRL_SHIFT_NUM_BITS
+#define BF_LCDIF_CTRL_SHIFT_NUM_BITS_V(e)                   BF_LCDIF_CTRL_SHIFT_NUM_BITS(BV_LCDIF_CTRL_SHIFT_NUM_BITS__##e)
+#define BFM_LCDIF_CTRL_SHIFT_NUM_BITS_V(v)                  BM_LCDIF_CTRL_SHIFT_NUM_BITS
+#define BP_LCDIF_CTRL_DVI_MODE                              24
+#define BM_LCDIF_CTRL_DVI_MODE                              0x1000000
+#define BF_LCDIF_CTRL_DVI_MODE(v)                           (((v) & 0x1) << 24)
+#define BFM_LCDIF_CTRL_DVI_MODE(v)                          BM_LCDIF_CTRL_DVI_MODE
+#define BF_LCDIF_CTRL_DVI_MODE_V(e)                         BF_LCDIF_CTRL_DVI_MODE(BV_LCDIF_CTRL_DVI_MODE__##e)
+#define BFM_LCDIF_CTRL_DVI_MODE_V(v)                        BM_LCDIF_CTRL_DVI_MODE
+#define BP_LCDIF_CTRL_BYPASS_COUNT                          23
+#define BM_LCDIF_CTRL_BYPASS_COUNT                          0x800000
+#define BF_LCDIF_CTRL_BYPASS_COUNT(v)                       (((v) & 0x1) << 23)
+#define BFM_LCDIF_CTRL_BYPASS_COUNT(v)                      BM_LCDIF_CTRL_BYPASS_COUNT
+#define BF_LCDIF_CTRL_BYPASS_COUNT_V(e)                     BF_LCDIF_CTRL_BYPASS_COUNT(BV_LCDIF_CTRL_BYPASS_COUNT__##e)
+#define BFM_LCDIF_CTRL_BYPASS_COUNT_V(v)                    BM_LCDIF_CTRL_BYPASS_COUNT
+#define BP_LCDIF_CTRL_DATA_SWIZZLE                          21
+#define BM_LCDIF_CTRL_DATA_SWIZZLE                          0x600000
+#define BV_LCDIF_CTRL_DATA_SWIZZLE__NO_SWAP                 0x0
+#define BV_LCDIF_CTRL_DATA_SWIZZLE__LITTLE_ENDIAN           0x0
+#define BV_LCDIF_CTRL_DATA_SWIZZLE__BIG_ENDIAN_SWAP         0x1
+#define BV_LCDIF_CTRL_DATA_SWIZZLE__SWAP_ALL_BYTES          0x1
+#define BV_LCDIF_CTRL_DATA_SWIZZLE__HWD_SWAP                0x2
+#define BV_LCDIF_CTRL_DATA_SWIZZLE__HWD_BYTE_SWAP           0x3
+#define BF_LCDIF_CTRL_DATA_SWIZZLE(v)                       (((v) & 0x3) << 21)
+#define BFM_LCDIF_CTRL_DATA_SWIZZLE(v)                      BM_LCDIF_CTRL_DATA_SWIZZLE
+#define BF_LCDIF_CTRL_DATA_SWIZZLE_V(e)                     BF_LCDIF_CTRL_DATA_SWIZZLE(BV_LCDIF_CTRL_DATA_SWIZZLE__##e)
+#define BFM_LCDIF_CTRL_DATA_SWIZZLE_V(v)                    BM_LCDIF_CTRL_DATA_SWIZZLE
+#define BP_LCDIF_CTRL_VSYNC_MODE                            20
+#define BM_LCDIF_CTRL_VSYNC_MODE                            0x100000
+#define BF_LCDIF_CTRL_VSYNC_MODE(v)                         (((v) & 0x1) << 20)
+#define BFM_LCDIF_CTRL_VSYNC_MODE(v)                        BM_LCDIF_CTRL_VSYNC_MODE
+#define BF_LCDIF_CTRL_VSYNC_MODE_V(e)                       BF_LCDIF_CTRL_VSYNC_MODE(BV_LCDIF_CTRL_VSYNC_MODE__##e)
+#define BFM_LCDIF_CTRL_VSYNC_MODE_V(v)                      BM_LCDIF_CTRL_VSYNC_MODE
+#define BP_LCDIF_CTRL_DOTCLK_MODE                           19
+#define BM_LCDIF_CTRL_DOTCLK_MODE                           0x80000
+#define BF_LCDIF_CTRL_DOTCLK_MODE(v)                        (((v) & 0x1) << 19)
+#define BFM_LCDIF_CTRL_DOTCLK_MODE(v)                       BM_LCDIF_CTRL_DOTCLK_MODE
+#define BF_LCDIF_CTRL_DOTCLK_MODE_V(e)                      BF_LCDIF_CTRL_DOTCLK_MODE(BV_LCDIF_CTRL_DOTCLK_MODE__##e)
+#define BFM_LCDIF_CTRL_DOTCLK_MODE_V(v)                     BM_LCDIF_CTRL_DOTCLK_MODE
+#define BP_LCDIF_CTRL_DATA_SELECT                           18
+#define BM_LCDIF_CTRL_DATA_SELECT                           0x40000
+#define BV_LCDIF_CTRL_DATA_SELECT__CMD_MODE                 0x0
+#define BV_LCDIF_CTRL_DATA_SELECT__DATA_MODE                0x1
+#define BF_LCDIF_CTRL_DATA_SELECT(v)                        (((v) & 0x1) << 18)
+#define BFM_LCDIF_CTRL_DATA_SELECT(v)                       BM_LCDIF_CTRL_DATA_SELECT
+#define BF_LCDIF_CTRL_DATA_SELECT_V(e)                      BF_LCDIF_CTRL_DATA_SELECT(BV_LCDIF_CTRL_DATA_SELECT__##e)
+#define BFM_LCDIF_CTRL_DATA_SELECT_V(v)                     BM_LCDIF_CTRL_DATA_SELECT
+#define BP_LCDIF_CTRL_WORD_LENGTH                           17
+#define BM_LCDIF_CTRL_WORD_LENGTH                           0x20000
+#define BV_LCDIF_CTRL_WORD_LENGTH__16_BIT                   0x0
+#define BV_LCDIF_CTRL_WORD_LENGTH__8_BIT                    0x1
+#define BF_LCDIF_CTRL_WORD_LENGTH(v)                        (((v) & 0x1) << 17)
+#define BFM_LCDIF_CTRL_WORD_LENGTH(v)                       BM_LCDIF_CTRL_WORD_LENGTH
+#define BF_LCDIF_CTRL_WORD_LENGTH_V(e)                      BF_LCDIF_CTRL_WORD_LENGTH(BV_LCDIF_CTRL_WORD_LENGTH__##e)
+#define BFM_LCDIF_CTRL_WORD_LENGTH_V(v)                     BM_LCDIF_CTRL_WORD_LENGTH
+#define BP_LCDIF_CTRL_RUN                                   16
+#define BM_LCDIF_CTRL_RUN                                   0x10000
+#define BF_LCDIF_CTRL_RUN(v)                                (((v) & 0x1) << 16)
+#define BFM_LCDIF_CTRL_RUN(v)                               BM_LCDIF_CTRL_RUN
+#define BF_LCDIF_CTRL_RUN_V(e)                              BF_LCDIF_CTRL_RUN(BV_LCDIF_CTRL_RUN__##e)
+#define BFM_LCDIF_CTRL_RUN_V(v)                             BM_LCDIF_CTRL_RUN
+#define BP_LCDIF_CTRL_COUNT                                 0
+#define BM_LCDIF_CTRL_COUNT                                 0xffff
+#define BF_LCDIF_CTRL_COUNT(v)                              (((v) & 0xffff) << 0)
+#define BFM_LCDIF_CTRL_COUNT(v)                             BM_LCDIF_CTRL_COUNT
+#define BF_LCDIF_CTRL_COUNT_V(e)                            BF_LCDIF_CTRL_COUNT(BV_LCDIF_CTRL_COUNT__##e)
+#define BFM_LCDIF_CTRL_COUNT_V(v)                           BM_LCDIF_CTRL_COUNT
+
+#define HW_LCDIF_CTRL1                                      HW(LCDIF_CTRL1)
+#define HWA_LCDIF_CTRL1                                     (0x80030000 + 0x10)
+#define HWT_LCDIF_CTRL1                                     HWIO_32_RW
+#define HWN_LCDIF_CTRL1                                     LCDIF_CTRL1
+#define HWI_LCDIF_CTRL1                                     
+#define HW_LCDIF_CTRL1_SET                                  HW(LCDIF_CTRL1_SET)
+#define HWA_LCDIF_CTRL1_SET                                 (HWA_LCDIF_CTRL1 + 0x4)
+#define HWT_LCDIF_CTRL1_SET                                 HWIO_32_WO
+#define HWN_LCDIF_CTRL1_SET                                 LCDIF_CTRL1
+#define HWI_LCDIF_CTRL1_SET                                 
+#define HW_LCDIF_CTRL1_CLR                                  HW(LCDIF_CTRL1_CLR)
+#define HWA_LCDIF_CTRL1_CLR                                 (HWA_LCDIF_CTRL1 + 0x8)
+#define HWT_LCDIF_CTRL1_CLR                                 HWIO_32_WO
+#define HWN_LCDIF_CTRL1_CLR                                 LCDIF_CTRL1
+#define HWI_LCDIF_CTRL1_CLR                                 
+#define HW_LCDIF_CTRL1_TOG                                  HW(LCDIF_CTRL1_TOG)
+#define HWA_LCDIF_CTRL1_TOG                                 (HWA_LCDIF_CTRL1 + 0xc)
+#define HWT_LCDIF_CTRL1_TOG                                 HWIO_32_WO
+#define HWN_LCDIF_CTRL1_TOG                                 LCDIF_CTRL1
+#define HWI_LCDIF_CTRL1_TOG                                 
+#define BP_LCDIF_CTRL1_BYTE_PACKING_FORMAT                  16
+#define BM_LCDIF_CTRL1_BYTE_PACKING_FORMAT                  0xf0000
+#define BF_LCDIF_CTRL1_BYTE_PACKING_FORMAT(v)               (((v) & 0xf) << 16)
+#define BFM_LCDIF_CTRL1_BYTE_PACKING_FORMAT(v)              BM_LCDIF_CTRL1_BYTE_PACKING_FORMAT
+#define BF_LCDIF_CTRL1_BYTE_PACKING_FORMAT_V(e)             BF_LCDIF_CTRL1_BYTE_PACKING_FORMAT(BV_LCDIF_CTRL1_BYTE_PACKING_FORMAT__##e)
+#define BFM_LCDIF_CTRL1_BYTE_PACKING_FORMAT_V(v)            BM_LCDIF_CTRL1_BYTE_PACKING_FORMAT
+#define BP_LCDIF_CTRL1_OVERFLOW_IRQ_EN                      15
+#define BM_LCDIF_CTRL1_OVERFLOW_IRQ_EN                      0x8000
+#define BF_LCDIF_CTRL1_OVERFLOW_IRQ_EN(v)                   (((v) & 0x1) << 15)
+#define BFM_LCDIF_CTRL1_OVERFLOW_IRQ_EN(v)                  BM_LCDIF_CTRL1_OVERFLOW_IRQ_EN
+#define BF_LCDIF_CTRL1_OVERFLOW_IRQ_EN_V(e)                 BF_LCDIF_CTRL1_OVERFLOW_IRQ_EN(BV_LCDIF_CTRL1_OVERFLOW_IRQ_EN__##e)
+#define BFM_LCDIF_CTRL1_OVERFLOW_IRQ_EN_V(v)                BM_LCDIF_CTRL1_OVERFLOW_IRQ_EN
+#define BP_LCDIF_CTRL1_UNDERFLOW_IRQ_EN                     14
+#define BM_LCDIF_CTRL1_UNDERFLOW_IRQ_EN                     0x4000
+#define BF_LCDIF_CTRL1_UNDERFLOW_IRQ_EN(v)                  (((v) & 0x1) << 14)
+#define BFM_LCDIF_CTRL1_UNDERFLOW_IRQ_EN(v)                 BM_LCDIF_CTRL1_UNDERFLOW_IRQ_EN
+#define BF_LCDIF_CTRL1_UNDERFLOW_IRQ_EN_V(e)                BF_LCDIF_CTRL1_UNDERFLOW_IRQ_EN(BV_LCDIF_CTRL1_UNDERFLOW_IRQ_EN__##e)
+#define BFM_LCDIF_CTRL1_UNDERFLOW_IRQ_EN_V(v)               BM_LCDIF_CTRL1_UNDERFLOW_IRQ_EN
+#define BP_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN                13
+#define BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN                0x2000
+#define BF_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN(v)             (((v) & 0x1) << 13)
+#define BFM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN(v)            BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN
+#define BF_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_V(e)           BF_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN(BV_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN__##e)
+#define BFM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_V(v)          BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN
+#define BP_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN                    12
+#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN                    0x1000
+#define BF_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN(v)                 (((v) & 0x1) << 12)
+#define BFM_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN(v)                BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN
+#define BF_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_V(e)               BF_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN(BV_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN__##e)
+#define BFM_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_V(v)              BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN
+#define BP_LCDIF_CTRL1_OVERFLOW_IRQ                         11
+#define BM_LCDIF_CTRL1_OVERFLOW_IRQ                         0x800
+#define BV_LCDIF_CTRL1_OVERFLOW_IRQ__NO_REQUEST             0x0
+#define BV_LCDIF_CTRL1_OVERFLOW_IRQ__REQUEST                0x1
+#define BF_LCDIF_CTRL1_OVERFLOW_IRQ(v)                      (((v) & 0x1) << 11)
+#define BFM_LCDIF_CTRL1_OVERFLOW_IRQ(v)                     BM_LCDIF_CTRL1_OVERFLOW_IRQ
+#define BF_LCDIF_CTRL1_OVERFLOW_IRQ_V(e)                    BF_LCDIF_CTRL1_OVERFLOW_IRQ(BV_LCDIF_CTRL1_OVERFLOW_IRQ__##e)
+#define BFM_LCDIF_CTRL1_OVERFLOW_IRQ_V(v)                   BM_LCDIF_CTRL1_OVERFLOW_IRQ
+#define BP_LCDIF_CTRL1_UNDERFLOW_IRQ                        10
+#define BM_LCDIF_CTRL1_UNDERFLOW_IRQ                        0x400
+#define BV_LCDIF_CTRL1_UNDERFLOW_IRQ__NO_REQUEST            0x0
+#define BV_LCDIF_CTRL1_UNDERFLOW_IRQ__REQUEST               0x1
+#define BF_LCDIF_CTRL1_UNDERFLOW_IRQ(v)                     (((v) & 0x1) << 10)
+#define BFM_LCDIF_CTRL1_UNDERFLOW_IRQ(v)                    BM_LCDIF_CTRL1_UNDERFLOW_IRQ
+#define BF_LCDIF_CTRL1_UNDERFLOW_IRQ_V(e)                   BF_LCDIF_CTRL1_UNDERFLOW_IRQ(BV_LCDIF_CTRL1_UNDERFLOW_IRQ__##e)
+#define BFM_LCDIF_CTRL1_UNDERFLOW_IRQ_V(v)                  BM_LCDIF_CTRL1_UNDERFLOW_IRQ
+#define BP_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ                   9
+#define BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ                   0x200
+#define BV_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ__NO_REQUEST       0x0
+#define BV_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ__REQUEST          0x1
+#define BF_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ(v)                (((v) & 0x1) << 9)
+#define BFM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ(v)               BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ
+#define BF_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_V(e)              BF_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ(BV_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ__##e)
+#define BFM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_V(v)             BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ
+#define BP_LCDIF_CTRL1_VSYNC_EDGE_IRQ                       8
+#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ                       0x100
+#define BV_LCDIF_CTRL1_VSYNC_EDGE_IRQ__NO_REQUEST           0x0
+#define BV_LCDIF_CTRL1_VSYNC_EDGE_IRQ__REQUEST              0x1
+#define BF_LCDIF_CTRL1_VSYNC_EDGE_IRQ(v)                    (((v) & 0x1) << 8)
+#define BFM_LCDIF_CTRL1_VSYNC_EDGE_IRQ(v)                   BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ
+#define BF_LCDIF_CTRL1_VSYNC_EDGE_IRQ_V(e)                  BF_LCDIF_CTRL1_VSYNC_EDGE_IRQ(BV_LCDIF_CTRL1_VSYNC_EDGE_IRQ__##e)
+#define BFM_LCDIF_CTRL1_VSYNC_EDGE_IRQ_V(v)                 BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ
+#define BP_LCDIF_CTRL1_READ_MODE_NUM_PACKED_SUBWORDS        5
+#define BM_LCDIF_CTRL1_READ_MODE_NUM_PACKED_SUBWORDS        0xe0
+#define BF_LCDIF_CTRL1_READ_MODE_NUM_PACKED_SUBWORDS(v)     (((v) & 0x7) << 5)
+#define BFM_LCDIF_CTRL1_READ_MODE_NUM_PACKED_SUBWORDS(v)    BM_LCDIF_CTRL1_READ_MODE_NUM_PACKED_SUBWORDS
+#define BF_LCDIF_CTRL1_READ_MODE_NUM_PACKED_SUBWORDS_V(e)   BF_LCDIF_CTRL1_READ_MODE_NUM_PACKED_SUBWORDS(BV_LCDIF_CTRL1_READ_MODE_NUM_PACKED_SUBWORDS__##e)
+#define BFM_LCDIF_CTRL1_READ_MODE_NUM_PACKED_SUBWORDS_V(v)  BM_LCDIF_CTRL1_READ_MODE_NUM_PACKED_SUBWORDS
+#define BP_LCDIF_CTRL1_FIRST_READ_DUMMY                     4
+#define BM_LCDIF_CTRL1_FIRST_READ_DUMMY                     0x10
+#define BF_LCDIF_CTRL1_FIRST_READ_DUMMY(v)                  (((v) & 0x1) << 4)
+#define BFM_LCDIF_CTRL1_FIRST_READ_DUMMY(v)                 BM_LCDIF_CTRL1_FIRST_READ_DUMMY
+#define BF_LCDIF_CTRL1_FIRST_READ_DUMMY_V(e)                BF_LCDIF_CTRL1_FIRST_READ_DUMMY(BV_LCDIF_CTRL1_FIRST_READ_DUMMY__##e)
+#define BFM_LCDIF_CTRL1_FIRST_READ_DUMMY_V(v)               BM_LCDIF_CTRL1_FIRST_READ_DUMMY
+#define BP_LCDIF_CTRL1_LCD_CS_CTRL                          3
+#define BM_LCDIF_CTRL1_LCD_CS_CTRL                          0x8
+#define BF_LCDIF_CTRL1_LCD_CS_CTRL(v)                       (((v) & 0x1) << 3)
+#define BFM_LCDIF_CTRL1_LCD_CS_CTRL(v)                      BM_LCDIF_CTRL1_LCD_CS_CTRL
+#define BF_LCDIF_CTRL1_LCD_CS_CTRL_V(e)                     BF_LCDIF_CTRL1_LCD_CS_CTRL(BV_LCDIF_CTRL1_LCD_CS_CTRL__##e)
+#define BFM_LCDIF_CTRL1_LCD_CS_CTRL_V(v)                    BM_LCDIF_CTRL1_LCD_CS_CTRL
+#define BP_LCDIF_CTRL1_BUSY_ENABLE                          2
+#define BM_LCDIF_CTRL1_BUSY_ENABLE                          0x4
+#define BV_LCDIF_CTRL1_BUSY_ENABLE__BUSY_DISABLED           0x0
+#define BV_LCDIF_CTRL1_BUSY_ENABLE__BUSY_ENABLED            0x1
+#define BF_LCDIF_CTRL1_BUSY_ENABLE(v)                       (((v) & 0x1) << 2)
+#define BFM_LCDIF_CTRL1_BUSY_ENABLE(v)                      BM_LCDIF_CTRL1_BUSY_ENABLE
+#define BF_LCDIF_CTRL1_BUSY_ENABLE_V(e)                     BF_LCDIF_CTRL1_BUSY_ENABLE(BV_LCDIF_CTRL1_BUSY_ENABLE__##e)
+#define BFM_LCDIF_CTRL1_BUSY_ENABLE_V(v)                    BM_LCDIF_CTRL1_BUSY_ENABLE
+#define BP_LCDIF_CTRL1_MODE86                               1
+#define BM_LCDIF_CTRL1_MODE86                               0x2
+#define BV_LCDIF_CTRL1_MODE86__8080_MODE                    0x0
+#define BV_LCDIF_CTRL1_MODE86__6800_MODE                    0x1
+#define BF_LCDIF_CTRL1_MODE86(v)                            (((v) & 0x1) << 1)
+#define BFM_LCDIF_CTRL1_MODE86(v)                           BM_LCDIF_CTRL1_MODE86
+#define BF_LCDIF_CTRL1_MODE86_V(e)                          BF_LCDIF_CTRL1_MODE86(BV_LCDIF_CTRL1_MODE86__##e)
+#define BFM_LCDIF_CTRL1_MODE86_V(v)                         BM_LCDIF_CTRL1_MODE86
+#define BP_LCDIF_CTRL1_RESET                                0
+#define BM_LCDIF_CTRL1_RESET                                0x1
+#define BV_LCDIF_CTRL1_RESET__LCDRESET_LOW                  0x0
+#define BV_LCDIF_CTRL1_RESET__LCDRESET_HIGH                 0x1
+#define BF_LCDIF_CTRL1_RESET(v)                             (((v) & 0x1) << 0)
+#define BFM_LCDIF_CTRL1_RESET(v)                            BM_LCDIF_CTRL1_RESET
+#define BF_LCDIF_CTRL1_RESET_V(e)                           BF_LCDIF_CTRL1_RESET(BV_LCDIF_CTRL1_RESET__##e)
+#define BFM_LCDIF_CTRL1_RESET_V(v)                          BM_LCDIF_CTRL1_RESET
+
+#define HW_LCDIF_TIMING                     HW(LCDIF_TIMING)
+#define HWA_LCDIF_TIMING                    (0x80030000 + 0x20)
+#define HWT_LCDIF_TIMING                    HWIO_32_RW
+#define HWN_LCDIF_TIMING                    LCDIF_TIMING
+#define HWI_LCDIF_TIMING                    
+#define BP_LCDIF_TIMING_CMD_HOLD            24
+#define BM_LCDIF_TIMING_CMD_HOLD            0xff000000
+#define BF_LCDIF_TIMING_CMD_HOLD(v)         (((v) & 0xff) << 24)
+#define BFM_LCDIF_TIMING_CMD_HOLD(v)        BM_LCDIF_TIMING_CMD_HOLD
+#define BF_LCDIF_TIMING_CMD_HOLD_V(e)       BF_LCDIF_TIMING_CMD_HOLD(BV_LCDIF_TIMING_CMD_HOLD__##e)
+#define BFM_LCDIF_TIMING_CMD_HOLD_V(v)      BM_LCDIF_TIMING_CMD_HOLD
+#define BP_LCDIF_TIMING_CMD_SETUP           16
+#define BM_LCDIF_TIMING_CMD_SETUP           0xff0000
+#define BF_LCDIF_TIMING_CMD_SETUP(v)        (((v) & 0xff) << 16)
+#define BFM_LCDIF_TIMING_CMD_SETUP(v)       BM_LCDIF_TIMING_CMD_SETUP
+#define BF_LCDIF_TIMING_CMD_SETUP_V(e)      BF_LCDIF_TIMING_CMD_SETUP(BV_LCDIF_TIMING_CMD_SETUP__##e)
+#define BFM_LCDIF_TIMING_CMD_SETUP_V(v)     BM_LCDIF_TIMING_CMD_SETUP
+#define BP_LCDIF_TIMING_DATA_HOLD           8
+#define BM_LCDIF_TIMING_DATA_HOLD           0xff00
+#define BF_LCDIF_TIMING_DATA_HOLD(v)        (((v) & 0xff) << 8)
+#define BFM_LCDIF_TIMING_DATA_HOLD(v)       BM_LCDIF_TIMING_DATA_HOLD
+#define BF_LCDIF_TIMING_DATA_HOLD_V(e)      BF_LCDIF_TIMING_DATA_HOLD(BV_LCDIF_TIMING_DATA_HOLD__##e)
+#define BFM_LCDIF_TIMING_DATA_HOLD_V(v)     BM_LCDIF_TIMING_DATA_HOLD
+#define BP_LCDIF_TIMING_DATA_SETUP          0
+#define BM_LCDIF_TIMING_DATA_SETUP          0xff
+#define BF_LCDIF_TIMING_DATA_SETUP(v)       (((v) & 0xff) << 0)
+#define BFM_LCDIF_TIMING_DATA_SETUP(v)      BM_LCDIF_TIMING_DATA_SETUP
+#define BF_LCDIF_TIMING_DATA_SETUP_V(e)     BF_LCDIF_TIMING_DATA_SETUP(BV_LCDIF_TIMING_DATA_SETUP__##e)
+#define BFM_LCDIF_TIMING_DATA_SETUP_V(v)    BM_LCDIF_TIMING_DATA_SETUP
+
+#define HW_LCDIF_VDCTRL0                                HW(LCDIF_VDCTRL0)
+#define HWA_LCDIF_VDCTRL0                               (0x80030000 + 0x30)
+#define HWT_LCDIF_VDCTRL0                               HWIO_32_RW
+#define HWN_LCDIF_VDCTRL0                               LCDIF_VDCTRL0
+#define HWI_LCDIF_VDCTRL0                               
+#define HW_LCDIF_VDCTRL0_SET                            HW(LCDIF_VDCTRL0_SET)
+#define HWA_LCDIF_VDCTRL0_SET                           (HWA_LCDIF_VDCTRL0 + 0x4)
+#define HWT_LCDIF_VDCTRL0_SET                           HWIO_32_WO
+#define HWN_LCDIF_VDCTRL0_SET                           LCDIF_VDCTRL0
+#define HWI_LCDIF_VDCTRL0_SET                           
+#define HW_LCDIF_VDCTRL0_CLR                            HW(LCDIF_VDCTRL0_CLR)
+#define HWA_LCDIF_VDCTRL0_CLR                           (HWA_LCDIF_VDCTRL0 + 0x8)
+#define HWT_LCDIF_VDCTRL0_CLR                           HWIO_32_WO
+#define HWN_LCDIF_VDCTRL0_CLR                           LCDIF_VDCTRL0
+#define HWI_LCDIF_VDCTRL0_CLR                           
+#define HW_LCDIF_VDCTRL0_TOG                            HW(LCDIF_VDCTRL0_TOG)
+#define HWA_LCDIF_VDCTRL0_TOG                           (HWA_LCDIF_VDCTRL0 + 0xc)
+#define HWT_LCDIF_VDCTRL0_TOG                           HWIO_32_WO
+#define HWN_LCDIF_VDCTRL0_TOG                           LCDIF_VDCTRL0
+#define HWI_LCDIF_VDCTRL0_TOG                           
+#define BP_LCDIF_VDCTRL0_VSYNC_OEB                      29
+#define BM_LCDIF_VDCTRL0_VSYNC_OEB                      0x20000000
+#define BV_LCDIF_VDCTRL0_VSYNC_OEB__VSYNC_OUTPUT        0x0
+#define BV_LCDIF_VDCTRL0_VSYNC_OEB__VSYNC_INPUT         0x1
+#define BF_LCDIF_VDCTRL0_VSYNC_OEB(v)                   (((v) & 0x1) << 29)
+#define BFM_LCDIF_VDCTRL0_VSYNC_OEB(v)                  BM_LCDIF_VDCTRL0_VSYNC_OEB
+#define BF_LCDIF_VDCTRL0_VSYNC_OEB_V(e)                 BF_LCDIF_VDCTRL0_VSYNC_OEB(BV_LCDIF_VDCTRL0_VSYNC_OEB__##e)
+#define BFM_LCDIF_VDCTRL0_VSYNC_OEB_V(v)                BM_LCDIF_VDCTRL0_VSYNC_OEB
+#define BP_LCDIF_VDCTRL0_ENABLE_PRESENT                 28
+#define BM_LCDIF_VDCTRL0_ENABLE_PRESENT                 0x10000000
+#define BF_LCDIF_VDCTRL0_ENABLE_PRESENT(v)              (((v) & 0x1) << 28)
+#define BFM_LCDIF_VDCTRL0_ENABLE_PRESENT(v)             BM_LCDIF_VDCTRL0_ENABLE_PRESENT
+#define BF_LCDIF_VDCTRL0_ENABLE_PRESENT_V(e)            BF_LCDIF_VDCTRL0_ENABLE_PRESENT(BV_LCDIF_VDCTRL0_ENABLE_PRESENT__##e)
+#define BFM_LCDIF_VDCTRL0_ENABLE_PRESENT_V(v)           BM_LCDIF_VDCTRL0_ENABLE_PRESENT
+#define BP_LCDIF_VDCTRL0_VSYNC_POL                      27
+#define BM_LCDIF_VDCTRL0_VSYNC_POL                      0x8000000
+#define BF_LCDIF_VDCTRL0_VSYNC_POL(v)                   (((v) & 0x1) << 27)
+#define BFM_LCDIF_VDCTRL0_VSYNC_POL(v)                  BM_LCDIF_VDCTRL0_VSYNC_POL
+#define BF_LCDIF_VDCTRL0_VSYNC_POL_V(e)                 BF_LCDIF_VDCTRL0_VSYNC_POL(BV_LCDIF_VDCTRL0_VSYNC_POL__##e)
+#define BFM_LCDIF_VDCTRL0_VSYNC_POL_V(v)                BM_LCDIF_VDCTRL0_VSYNC_POL
+#define BP_LCDIF_VDCTRL0_HSYNC_POL                      26
+#define BM_LCDIF_VDCTRL0_HSYNC_POL                      0x4000000
+#define BF_LCDIF_VDCTRL0_HSYNC_POL(v)                   (((v) & 0x1) << 26)
+#define BFM_LCDIF_VDCTRL0_HSYNC_POL(v)                  BM_LCDIF_VDCTRL0_HSYNC_POL
+#define BF_LCDIF_VDCTRL0_HSYNC_POL_V(e)                 BF_LCDIF_VDCTRL0_HSYNC_POL(BV_LCDIF_VDCTRL0_HSYNC_POL__##e)
+#define BFM_LCDIF_VDCTRL0_HSYNC_POL_V(v)                BM_LCDIF_VDCTRL0_HSYNC_POL
+#define BP_LCDIF_VDCTRL0_DOTCLK_POL                     25
+#define BM_LCDIF_VDCTRL0_DOTCLK_POL                     0x2000000
+#define BF_LCDIF_VDCTRL0_DOTCLK_POL(v)                  (((v) & 0x1) << 25)
+#define BFM_LCDIF_VDCTRL0_DOTCLK_POL(v)                 BM_LCDIF_VDCTRL0_DOTCLK_POL
+#define BF_LCDIF_VDCTRL0_DOTCLK_POL_V(e)                BF_LCDIF_VDCTRL0_DOTCLK_POL(BV_LCDIF_VDCTRL0_DOTCLK_POL__##e)
+#define BFM_LCDIF_VDCTRL0_DOTCLK_POL_V(v)               BM_LCDIF_VDCTRL0_DOTCLK_POL
+#define BP_LCDIF_VDCTRL0_ENABLE_POL                     24
+#define BM_LCDIF_VDCTRL0_ENABLE_POL                     0x1000000
+#define BF_LCDIF_VDCTRL0_ENABLE_POL(v)                  (((v) & 0x1) << 24)
+#define BFM_LCDIF_VDCTRL0_ENABLE_POL(v)                 BM_LCDIF_VDCTRL0_ENABLE_POL
+#define BF_LCDIF_VDCTRL0_ENABLE_POL_V(e)                BF_LCDIF_VDCTRL0_ENABLE_POL(BV_LCDIF_VDCTRL0_ENABLE_POL__##e)
+#define BFM_LCDIF_VDCTRL0_ENABLE_POL_V(v)               BM_LCDIF_VDCTRL0_ENABLE_POL
+#define BP_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT              21
+#define BM_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT              0x200000
+#define BF_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT(v)           (((v) & 0x1) << 21)
+#define BFM_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT(v)          BM_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT
+#define BF_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_V(e)         BF_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT(BV_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT__##e)
+#define BFM_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_V(v)        BM_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT
+#define BP_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT         20
+#define BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT         0x100000
+#define BF_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT(v)      (((v) & 0x1) << 20)
+#define BFM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT(v)     BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT
+#define BF_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_V(e)    BF_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT(BV_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT__##e)
+#define BFM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_V(v)   BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT
+#define BP_LCDIF_VDCTRL0_INTERLACE                      19
+#define BM_LCDIF_VDCTRL0_INTERLACE                      0x80000
+#define BF_LCDIF_VDCTRL0_INTERLACE(v)                   (((v) & 0x1) << 19)
+#define BFM_LCDIF_VDCTRL0_INTERLACE(v)                  BM_LCDIF_VDCTRL0_INTERLACE
+#define BF_LCDIF_VDCTRL0_INTERLACE_V(e)                 BF_LCDIF_VDCTRL0_INTERLACE(BV_LCDIF_VDCTRL0_INTERLACE__##e)
+#define BFM_LCDIF_VDCTRL0_INTERLACE_V(v)                BM_LCDIF_VDCTRL0_INTERLACE
+#define BP_LCDIF_VDCTRL0_DOTCLK_V_VALID_DATA_CNT        0
+#define BM_LCDIF_VDCTRL0_DOTCLK_V_VALID_DATA_CNT        0x3ff
+#define BF_LCDIF_VDCTRL0_DOTCLK_V_VALID_DATA_CNT(v)     (((v) & 0x3ff) << 0)
+#define BFM_LCDIF_VDCTRL0_DOTCLK_V_VALID_DATA_CNT(v)    BM_LCDIF_VDCTRL0_DOTCLK_V_VALID_DATA_CNT
+#define BF_LCDIF_VDCTRL0_DOTCLK_V_VALID_DATA_CNT_V(e)   BF_LCDIF_VDCTRL0_DOTCLK_V_VALID_DATA_CNT(BV_LCDIF_VDCTRL0_DOTCLK_V_VALID_DATA_CNT__##e)
+#define BFM_LCDIF_VDCTRL0_DOTCLK_V_VALID_DATA_CNT_V(v)  BM_LCDIF_VDCTRL0_DOTCLK_V_VALID_DATA_CNT
+
+#define HW_LCDIF_VDCTRL1                            HW(LCDIF_VDCTRL1)
+#define HWA_LCDIF_VDCTRL1                           (0x80030000 + 0x40)
+#define HWT_LCDIF_VDCTRL1                           HWIO_32_RW
+#define HWN_LCDIF_VDCTRL1                           LCDIF_VDCTRL1
+#define HWI_LCDIF_VDCTRL1                           
+#define BP_LCDIF_VDCTRL1_VSYNC_PULSE_WIDTH          20
+#define BM_LCDIF_VDCTRL1_VSYNC_PULSE_WIDTH          0xfff00000
+#define BF_LCDIF_VDCTRL1_VSYNC_PULSE_WIDTH(v)       (((v) & 0xfff) << 20)
+#define BFM_LCDIF_VDCTRL1_VSYNC_PULSE_WIDTH(v)      BM_LCDIF_VDCTRL1_VSYNC_PULSE_WIDTH
+#define BF_LCDIF_VDCTRL1_VSYNC_PULSE_WIDTH_V(e)     BF_LCDIF_VDCTRL1_VSYNC_PULSE_WIDTH(BV_LCDIF_VDCTRL1_VSYNC_PULSE_WIDTH__##e)
+#define BFM_LCDIF_VDCTRL1_VSYNC_PULSE_WIDTH_V(v)    BM_LCDIF_VDCTRL1_VSYNC_PULSE_WIDTH
+#define BP_LCDIF_VDCTRL1_VSYNC_PERIOD               0
+#define BM_LCDIF_VDCTRL1_VSYNC_PERIOD               0xfffff
+#define BF_LCDIF_VDCTRL1_VSYNC_PERIOD(v)            (((v) & 0xfffff) << 0)
+#define BFM_LCDIF_VDCTRL1_VSYNC_PERIOD(v)           BM_LCDIF_VDCTRL1_VSYNC_PERIOD
+#define BF_LCDIF_VDCTRL1_VSYNC_PERIOD_V(e)          BF_LCDIF_VDCTRL1_VSYNC_PERIOD(BV_LCDIF_VDCTRL1_VSYNC_PERIOD__##e)
+#define BFM_LCDIF_VDCTRL1_VSYNC_PERIOD_V(v)         BM_LCDIF_VDCTRL1_VSYNC_PERIOD
+
+#define HW_LCDIF_VDCTRL2                                HW(LCDIF_VDCTRL2)
+#define HWA_LCDIF_VDCTRL2                               (0x80030000 + 0x50)
+#define HWT_LCDIF_VDCTRL2                               HWIO_32_RW
+#define HWN_LCDIF_VDCTRL2                               LCDIF_VDCTRL2
+#define HWI_LCDIF_VDCTRL2                               
+#define BP_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH              23
+#define BM_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH              0xff800000
+#define BF_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(v)           (((v) & 0x1ff) << 23)
+#define BFM_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(v)          BM_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH
+#define BF_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_V(e)         BF_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(BV_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH__##e)
+#define BFM_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_V(v)        BM_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH
+#define BP_LCDIF_VDCTRL2_HSYNC_PERIOD                   11
+#define BM_LCDIF_VDCTRL2_HSYNC_PERIOD                   0x7ff800
+#define BF_LCDIF_VDCTRL2_HSYNC_PERIOD(v)                (((v) & 0xfff) << 11)
+#define BFM_LCDIF_VDCTRL2_HSYNC_PERIOD(v)               BM_LCDIF_VDCTRL2_HSYNC_PERIOD
+#define BF_LCDIF_VDCTRL2_HSYNC_PERIOD_V(e)              BF_LCDIF_VDCTRL2_HSYNC_PERIOD(BV_LCDIF_VDCTRL2_HSYNC_PERIOD__##e)
+#define BFM_LCDIF_VDCTRL2_HSYNC_PERIOD_V(v)             BM_LCDIF_VDCTRL2_HSYNC_PERIOD
+#define BP_LCDIF_VDCTRL2_DOTCLK_H_VALID_DATA_CNT        0
+#define BM_LCDIF_VDCTRL2_DOTCLK_H_VALID_DATA_CNT        0x7ff
+#define BF_LCDIF_VDCTRL2_DOTCLK_H_VALID_DATA_CNT(v)     (((v) & 0x7ff) << 0)
+#define BFM_LCDIF_VDCTRL2_DOTCLK_H_VALID_DATA_CNT(v)    BM_LCDIF_VDCTRL2_DOTCLK_H_VALID_DATA_CNT
+#define BF_LCDIF_VDCTRL2_DOTCLK_H_VALID_DATA_CNT_V(e)   BF_LCDIF_VDCTRL2_DOTCLK_H_VALID_DATA_CNT(BV_LCDIF_VDCTRL2_DOTCLK_H_VALID_DATA_CNT__##e)
+#define BFM_LCDIF_VDCTRL2_DOTCLK_H_VALID_DATA_CNT_V(v)  BM_LCDIF_VDCTRL2_DOTCLK_H_VALID_DATA_CNT
+
+#define HW_LCDIF_VDCTRL3                            HW(LCDIF_VDCTRL3)
+#define HWA_LCDIF_VDCTRL3                           (0x80030000 + 0x60)
+#define HWT_LCDIF_VDCTRL3                           HWIO_32_RW
+#define HWN_LCDIF_VDCTRL3                           LCDIF_VDCTRL3
+#define HWI_LCDIF_VDCTRL3                           
+#define BP_LCDIF_VDCTRL3_SYNC_SIGNALS_ON            24
+#define BM_LCDIF_VDCTRL3_SYNC_SIGNALS_ON            0x1000000
+#define BF_LCDIF_VDCTRL3_SYNC_SIGNALS_ON(v)         (((v) & 0x1) << 24)
+#define BFM_LCDIF_VDCTRL3_SYNC_SIGNALS_ON(v)        BM_LCDIF_VDCTRL3_SYNC_SIGNALS_ON
+#define BF_LCDIF_VDCTRL3_SYNC_SIGNALS_ON_V(e)       BF_LCDIF_VDCTRL3_SYNC_SIGNALS_ON(BV_LCDIF_VDCTRL3_SYNC_SIGNALS_ON__##e)
+#define BFM_LCDIF_VDCTRL3_SYNC_SIGNALS_ON_V(v)      BM_LCDIF_VDCTRL3_SYNC_SIGNALS_ON
+#define BP_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT        12
+#define BM_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT        0xfff000
+#define BF_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(v)     (((v) & 0xfff) << 12)
+#define BFM_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(v)    BM_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT
+#define BF_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_V(e)   BF_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(BV_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT__##e)
+#define BFM_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_V(v)  BM_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT
+#define BP_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT          0
+#define BM_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT          0x1ff
+#define BF_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT(v)       (((v) & 0x1ff) << 0)
+#define BFM_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT(v)      BM_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT
+#define BF_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_V(e)     BF_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT(BV_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT__##e)
+#define BFM_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_V(v)    BM_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT
+
+#define HW_LCDIF_DVICTRL0                       HW(LCDIF_DVICTRL0)
+#define HWA_LCDIF_DVICTRL0                      (0x80030000 + 0x70)
+#define HWT_LCDIF_DVICTRL0                      HWIO_32_RW
+#define HWN_LCDIF_DVICTRL0                      LCDIF_DVICTRL0
+#define HWI_LCDIF_DVICTRL0                      
+#define BP_LCDIF_DVICTRL0_H_ACTIVE_CNT          20
+#define BM_LCDIF_DVICTRL0_H_ACTIVE_CNT          0x7ff00000
+#define BF_LCDIF_DVICTRL0_H_ACTIVE_CNT(v)       (((v) & 0x7ff) << 20)
+#define BFM_LCDIF_DVICTRL0_H_ACTIVE_CNT(v)      BM_LCDIF_DVICTRL0_H_ACTIVE_CNT
+#define BF_LCDIF_DVICTRL0_H_ACTIVE_CNT_V(e)     BF_LCDIF_DVICTRL0_H_ACTIVE_CNT(BV_LCDIF_DVICTRL0_H_ACTIVE_CNT__##e)
+#define BFM_LCDIF_DVICTRL0_H_ACTIVE_CNT_V(v)    BM_LCDIF_DVICTRL0_H_ACTIVE_CNT
+#define BP_LCDIF_DVICTRL0_H_BLANKING_CNT        10
+#define BM_LCDIF_DVICTRL0_H_BLANKING_CNT        0xffc00
+#define BF_LCDIF_DVICTRL0_H_BLANKING_CNT(v)     (((v) & 0x3ff) << 10)
+#define BFM_LCDIF_DVICTRL0_H_BLANKING_CNT(v)    BM_LCDIF_DVICTRL0_H_BLANKING_CNT
+#define BF_LCDIF_DVICTRL0_H_BLANKING_CNT_V(e)   BF_LCDIF_DVICTRL0_H_BLANKING_CNT(BV_LCDIF_DVICTRL0_H_BLANKING_CNT__##e)
+#define BFM_LCDIF_DVICTRL0_H_BLANKING_CNT_V(v)  BM_LCDIF_DVICTRL0_H_BLANKING_CNT
+#define BP_LCDIF_DVICTRL0_V_LINES_CNT           0
+#define BM_LCDIF_DVICTRL0_V_LINES_CNT           0x3ff
+#define BF_LCDIF_DVICTRL0_V_LINES_CNT(v)        (((v) & 0x3ff) << 0)
+#define BFM_LCDIF_DVICTRL0_V_LINES_CNT(v)       BM_LCDIF_DVICTRL0_V_LINES_CNT
+#define BF_LCDIF_DVICTRL0_V_LINES_CNT_V(e)      BF_LCDIF_DVICTRL0_V_LINES_CNT(BV_LCDIF_DVICTRL0_V_LINES_CNT__##e)
+#define BFM_LCDIF_DVICTRL0_V_LINES_CNT_V(v)     BM_LCDIF_DVICTRL0_V_LINES_CNT
+
+#define HW_LCDIF_DVICTRL1                       HW(LCDIF_DVICTRL1)
+#define HWA_LCDIF_DVICTRL1                      (0x80030000 + 0x80)
+#define HWT_LCDIF_DVICTRL1                      HWIO_32_RW
+#define HWN_LCDIF_DVICTRL1                      LCDIF_DVICTRL1
+#define HWI_LCDIF_DVICTRL1                      
+#define BP_LCDIF_DVICTRL1_F1_START_LINE         20
+#define BM_LCDIF_DVICTRL1_F1_START_LINE         0x3ff00000
+#define BF_LCDIF_DVICTRL1_F1_START_LINE(v)      (((v) & 0x3ff) << 20)
+#define BFM_LCDIF_DVICTRL1_F1_START_LINE(v)     BM_LCDIF_DVICTRL1_F1_START_LINE
+#define BF_LCDIF_DVICTRL1_F1_START_LINE_V(e)    BF_LCDIF_DVICTRL1_F1_START_LINE(BV_LCDIF_DVICTRL1_F1_START_LINE__##e)
+#define BFM_LCDIF_DVICTRL1_F1_START_LINE_V(v)   BM_LCDIF_DVICTRL1_F1_START_LINE
+#define BP_LCDIF_DVICTRL1_F1_END_LINE           10
+#define BM_LCDIF_DVICTRL1_F1_END_LINE           0xffc00
+#define BF_LCDIF_DVICTRL1_F1_END_LINE(v)        (((v) & 0x3ff) << 10)
+#define BFM_LCDIF_DVICTRL1_F1_END_LINE(v)       BM_LCDIF_DVICTRL1_F1_END_LINE
+#define BF_LCDIF_DVICTRL1_F1_END_LINE_V(e)      BF_LCDIF_DVICTRL1_F1_END_LINE(BV_LCDIF_DVICTRL1_F1_END_LINE__##e)
+#define BFM_LCDIF_DVICTRL1_F1_END_LINE_V(v)     BM_LCDIF_DVICTRL1_F1_END_LINE
+#define BP_LCDIF_DVICTRL1_F2_START_LINE         0
+#define BM_LCDIF_DVICTRL1_F2_START_LINE         0x3ff
+#define BF_LCDIF_DVICTRL1_F2_START_LINE(v)      (((v) & 0x3ff) << 0)
+#define BFM_LCDIF_DVICTRL1_F2_START_LINE(v)     BM_LCDIF_DVICTRL1_F2_START_LINE
+#define BF_LCDIF_DVICTRL1_F2_START_LINE_V(e)    BF_LCDIF_DVICTRL1_F2_START_LINE(BV_LCDIF_DVICTRL1_F2_START_LINE__##e)
+#define BFM_LCDIF_DVICTRL1_F2_START_LINE_V(v)   BM_LCDIF_DVICTRL1_F2_START_LINE
+
+#define HW_LCDIF_DVICTRL2                           HW(LCDIF_DVICTRL2)
+#define HWA_LCDIF_DVICTRL2                          (0x80030000 + 0x90)
+#define HWT_LCDIF_DVICTRL2                          HWIO_32_RW
+#define HWN_LCDIF_DVICTRL2                          LCDIF_DVICTRL2
+#define HWI_LCDIF_DVICTRL2                          
+#define BP_LCDIF_DVICTRL2_F2_END_LINE               20
+#define BM_LCDIF_DVICTRL2_F2_END_LINE               0x3ff00000
+#define BF_LCDIF_DVICTRL2_F2_END_LINE(v)            (((v) & 0x3ff) << 20)
+#define BFM_LCDIF_DVICTRL2_F2_END_LINE(v)           BM_LCDIF_DVICTRL2_F2_END_LINE
+#define BF_LCDIF_DVICTRL2_F2_END_LINE_V(e)          BF_LCDIF_DVICTRL2_F2_END_LINE(BV_LCDIF_DVICTRL2_F2_END_LINE__##e)
+#define BFM_LCDIF_DVICTRL2_F2_END_LINE_V(v)         BM_LCDIF_DVICTRL2_F2_END_LINE
+#define BP_LCDIF_DVICTRL2_V1_BLANK_START_LINE       10
+#define BM_LCDIF_DVICTRL2_V1_BLANK_START_LINE       0xffc00
+#define BF_LCDIF_DVICTRL2_V1_BLANK_START_LINE(v)    (((v) & 0x3ff) << 10)
+#define BFM_LCDIF_DVICTRL2_V1_BLANK_START_LINE(v)   BM_LCDIF_DVICTRL2_V1_BLANK_START_LINE
+#define BF_LCDIF_DVICTRL2_V1_BLANK_START_LINE_V(e)  BF_LCDIF_DVICTRL2_V1_BLANK_START_LINE(BV_LCDIF_DVICTRL2_V1_BLANK_START_LINE__##e)
+#define BFM_LCDIF_DVICTRL2_V1_BLANK_START_LINE_V(v) BM_LCDIF_DVICTRL2_V1_BLANK_START_LINE
+#define BP_LCDIF_DVICTRL2_V1_BLANK_END_LINE         0
+#define BM_LCDIF_DVICTRL2_V1_BLANK_END_LINE         0x3ff
+#define BF_LCDIF_DVICTRL2_V1_BLANK_END_LINE(v)      (((v) & 0x3ff) << 0)
+#define BFM_LCDIF_DVICTRL2_V1_BLANK_END_LINE(v)     BM_LCDIF_DVICTRL2_V1_BLANK_END_LINE
+#define BF_LCDIF_DVICTRL2_V1_BLANK_END_LINE_V(e)    BF_LCDIF_DVICTRL2_V1_BLANK_END_LINE(BV_LCDIF_DVICTRL2_V1_BLANK_END_LINE__##e)
+#define BFM_LCDIF_DVICTRL2_V1_BLANK_END_LINE_V(v)   BM_LCDIF_DVICTRL2_V1_BLANK_END_LINE
+
+#define HW_LCDIF_DVICTRL3                           HW(LCDIF_DVICTRL3)
+#define HWA_LCDIF_DVICTRL3                          (0x80030000 + 0xa0)
+#define HWT_LCDIF_DVICTRL3                          HWIO_32_RW
+#define HWN_LCDIF_DVICTRL3                          LCDIF_DVICTRL3
+#define HWI_LCDIF_DVICTRL3                          
+#define BP_LCDIF_DVICTRL3_V2_BLANK_START_LINE       16
+#define BM_LCDIF_DVICTRL3_V2_BLANK_START_LINE       0x3ff0000
+#define BF_LCDIF_DVICTRL3_V2_BLANK_START_LINE(v)    (((v) & 0x3ff) << 16)
+#define BFM_LCDIF_DVICTRL3_V2_BLANK_START_LINE(v)   BM_LCDIF_DVICTRL3_V2_BLANK_START_LINE
+#define BF_LCDIF_DVICTRL3_V2_BLANK_START_LINE_V(e)  BF_LCDIF_DVICTRL3_V2_BLANK_START_LINE(BV_LCDIF_DVICTRL3_V2_BLANK_START_LINE__##e)
+#define BFM_LCDIF_DVICTRL3_V2_BLANK_START_LINE_V(v) BM_LCDIF_DVICTRL3_V2_BLANK_START_LINE
+#define BP_LCDIF_DVICTRL3_V2_BLANK_END_LINE         0
+#define BM_LCDIF_DVICTRL3_V2_BLANK_END_LINE         0x3ff
+#define BF_LCDIF_DVICTRL3_V2_BLANK_END_LINE(v)      (((v) & 0x3ff) << 0)
+#define BFM_LCDIF_DVICTRL3_V2_BLANK_END_LINE(v)     BM_LCDIF_DVICTRL3_V2_BLANK_END_LINE
+#define BF_LCDIF_DVICTRL3_V2_BLANK_END_LINE_V(e)    BF_LCDIF_DVICTRL3_V2_BLANK_END_LINE(BV_LCDIF_DVICTRL3_V2_BLANK_END_LINE__##e)
+#define BFM_LCDIF_DVICTRL3_V2_BLANK_END_LINE_V(v)   BM_LCDIF_DVICTRL3_V2_BLANK_END_LINE
+
+#define HW_LCDIF_DATA                   HW(LCDIF_DATA)
+#define HWA_LCDIF_DATA                  (0x80030000 + 0xb0)
+#define HWT_LCDIF_DATA                  HWIO_32_RW
+#define HWN_LCDIF_DATA                  LCDIF_DATA
+#define HWI_LCDIF_DATA                  
+#define BP_LCDIF_DATA_DATA_THREE        24
+#define BM_LCDIF_DATA_DATA_THREE        0xff000000
+#define BF_LCDIF_DATA_DATA_THREE(v)     (((v) & 0xff) << 24)
+#define BFM_LCDIF_DATA_DATA_THREE(v)    BM_LCDIF_DATA_DATA_THREE
+#define BF_LCDIF_DATA_DATA_THREE_V(e)   BF_LCDIF_DATA_DATA_THREE(BV_LCDIF_DATA_DATA_THREE__##e)
+#define BFM_LCDIF_DATA_DATA_THREE_V(v)  BM_LCDIF_DATA_DATA_THREE
+#define BP_LCDIF_DATA_DATA_TWO          16
+#define BM_LCDIF_DATA_DATA_TWO          0xff0000
+#define BF_LCDIF_DATA_DATA_TWO(v)       (((v) & 0xff) << 16)
+#define BFM_LCDIF_DATA_DATA_TWO(v)      BM_LCDIF_DATA_DATA_TWO
+#define BF_LCDIF_DATA_DATA_TWO_V(e)     BF_LCDIF_DATA_DATA_TWO(BV_LCDIF_DATA_DATA_TWO__##e)
+#define BFM_LCDIF_DATA_DATA_TWO_V(v)    BM_LCDIF_DATA_DATA_TWO
+#define BP_LCDIF_DATA_DATA_ONE          8
+#define BM_LCDIF_DATA_DATA_ONE          0xff00
+#define BF_LCDIF_DATA_DATA_ONE(v)       (((v) & 0xff) << 8)
+#define BFM_LCDIF_DATA_DATA_ONE(v)      BM_LCDIF_DATA_DATA_ONE
+#define BF_LCDIF_DATA_DATA_ONE_V(e)     BF_LCDIF_DATA_DATA_ONE(BV_LCDIF_DATA_DATA_ONE__##e)
+#define BFM_LCDIF_DATA_DATA_ONE_V(v)    BM_LCDIF_DATA_DATA_ONE
+#define BP_LCDIF_DATA_DATA_ZERO         0
+#define BM_LCDIF_DATA_DATA_ZERO         0xff
+#define BF_LCDIF_DATA_DATA_ZERO(v)      (((v) & 0xff) << 0)
+#define BFM_LCDIF_DATA_DATA_ZERO(v)     BM_LCDIF_DATA_DATA_ZERO
+#define BF_LCDIF_DATA_DATA_ZERO_V(e)    BF_LCDIF_DATA_DATA_ZERO(BV_LCDIF_DATA_DATA_ZERO__##e)
+#define BFM_LCDIF_DATA_DATA_ZERO_V(v)   BM_LCDIF_DATA_DATA_ZERO
+
+#define HW_LCDIF_STAT                           HW(LCDIF_STAT)
+#define HWA_LCDIF_STAT                          (0x80030000 + 0xc0)
+#define HWT_LCDIF_STAT                          HWIO_32_RW
+#define HWN_LCDIF_STAT                          LCDIF_STAT
+#define HWI_LCDIF_STAT                          
+#define BP_LCDIF_STAT_PRESENT                   31
+#define BM_LCDIF_STAT_PRESENT                   0x80000000
+#define BF_LCDIF_STAT_PRESENT(v)                (((v) & 0x1) << 31)
+#define BFM_LCDIF_STAT_PRESENT(v)               BM_LCDIF_STAT_PRESENT
+#define BF_LCDIF_STAT_PRESENT_V(e)              BF_LCDIF_STAT_PRESENT(BV_LCDIF_STAT_PRESENT__##e)
+#define BFM_LCDIF_STAT_PRESENT_V(v)             BM_LCDIF_STAT_PRESENT
+#define BP_LCDIF_STAT_DMA_REQ                   30
+#define BM_LCDIF_STAT_DMA_REQ                   0x40000000
+#define BF_LCDIF_STAT_DMA_REQ(v)                (((v) & 0x1) << 30)
+#define BFM_LCDIF_STAT_DMA_REQ(v)               BM_LCDIF_STAT_DMA_REQ
+#define BF_LCDIF_STAT_DMA_REQ_V(e)              BF_LCDIF_STAT_DMA_REQ(BV_LCDIF_STAT_DMA_REQ__##e)
+#define BFM_LCDIF_STAT_DMA_REQ_V(v)             BM_LCDIF_STAT_DMA_REQ
+#define BP_LCDIF_STAT_RXFIFO_FULL               29
+#define BM_LCDIF_STAT_RXFIFO_FULL               0x20000000
+#define BF_LCDIF_STAT_RXFIFO_FULL(v)            (((v) & 0x1) << 29)
+#define BFM_LCDIF_STAT_RXFIFO_FULL(v)           BM_LCDIF_STAT_RXFIFO_FULL
+#define BF_LCDIF_STAT_RXFIFO_FULL_V(e)          BF_LCDIF_STAT_RXFIFO_FULL(BV_LCDIF_STAT_RXFIFO_FULL__##e)
+#define BFM_LCDIF_STAT_RXFIFO_FULL_V(v)         BM_LCDIF_STAT_RXFIFO_FULL
+#define BP_LCDIF_STAT_RXFIFO_EMPTY              28
+#define BM_LCDIF_STAT_RXFIFO_EMPTY              0x10000000
+#define BF_LCDIF_STAT_RXFIFO_EMPTY(v)           (((v) & 0x1) << 28)
+#define BFM_LCDIF_STAT_RXFIFO_EMPTY(v)          BM_LCDIF_STAT_RXFIFO_EMPTY
+#define BF_LCDIF_STAT_RXFIFO_EMPTY_V(e)         BF_LCDIF_STAT_RXFIFO_EMPTY(BV_LCDIF_STAT_RXFIFO_EMPTY__##e)
+#define BFM_LCDIF_STAT_RXFIFO_EMPTY_V(v)        BM_LCDIF_STAT_RXFIFO_EMPTY
+#define BP_LCDIF_STAT_TXFIFO_FULL               27
+#define BM_LCDIF_STAT_TXFIFO_FULL               0x8000000
+#define BF_LCDIF_STAT_TXFIFO_FULL(v)            (((v) & 0x1) << 27)
+#define BFM_LCDIF_STAT_TXFIFO_FULL(v)           BM_LCDIF_STAT_TXFIFO_FULL
+#define BF_LCDIF_STAT_TXFIFO_FULL_V(e)          BF_LCDIF_STAT_TXFIFO_FULL(BV_LCDIF_STAT_TXFIFO_FULL__##e)
+#define BFM_LCDIF_STAT_TXFIFO_FULL_V(v)         BM_LCDIF_STAT_TXFIFO_FULL
+#define BP_LCDIF_STAT_TXFIFO_EMPTY              26
+#define BM_LCDIF_STAT_TXFIFO_EMPTY              0x4000000
+#define BF_LCDIF_STAT_TXFIFO_EMPTY(v)           (((v) & 0x1) << 26)
+#define BFM_LCDIF_STAT_TXFIFO_EMPTY(v)          BM_LCDIF_STAT_TXFIFO_EMPTY
+#define BF_LCDIF_STAT_TXFIFO_EMPTY_V(e)         BF_LCDIF_STAT_TXFIFO_EMPTY(BV_LCDIF_STAT_TXFIFO_EMPTY__##e)
+#define BFM_LCDIF_STAT_TXFIFO_EMPTY_V(v)        BM_LCDIF_STAT_TXFIFO_EMPTY
+#define BP_LCDIF_STAT_BUSY                      25
+#define BM_LCDIF_STAT_BUSY                      0x2000000
+#define BF_LCDIF_STAT_BUSY(v)                   (((v) & 0x1) << 25)
+#define BFM_LCDIF_STAT_BUSY(v)                  BM_LCDIF_STAT_BUSY
+#define BF_LCDIF_STAT_BUSY_V(e)                 BF_LCDIF_STAT_BUSY(BV_LCDIF_STAT_BUSY__##e)
+#define BFM_LCDIF_STAT_BUSY_V(v)                BM_LCDIF_STAT_BUSY
+#define BP_LCDIF_STAT_DVI_CURRENT_FIELD         24
+#define BM_LCDIF_STAT_DVI_CURRENT_FIELD         0x1000000
+#define BF_LCDIF_STAT_DVI_CURRENT_FIELD(v)      (((v) & 0x1) << 24)
+#define BFM_LCDIF_STAT_DVI_CURRENT_FIELD(v)     BM_LCDIF_STAT_DVI_CURRENT_FIELD
+#define BF_LCDIF_STAT_DVI_CURRENT_FIELD_V(e)    BF_LCDIF_STAT_DVI_CURRENT_FIELD(BV_LCDIF_STAT_DVI_CURRENT_FIELD__##e)
+#define BFM_LCDIF_STAT_DVI_CURRENT_FIELD_V(v)   BM_LCDIF_STAT_DVI_CURRENT_FIELD
+
+#define HW_LCDIF_VERSION                HW(LCDIF_VERSION)
+#define HWA_LCDIF_VERSION               (0x80030000 + 0xd0)
+#define HWT_LCDIF_VERSION               HWIO_32_RW
+#define HWN_LCDIF_VERSION               LCDIF_VERSION
+#define HWI_LCDIF_VERSION               
+#define BP_LCDIF_VERSION_MAJOR          24
+#define BM_LCDIF_VERSION_MAJOR          0xff000000
+#define BF_LCDIF_VERSION_MAJOR(v)       (((v) & 0xff) << 24)
+#define BFM_LCDIF_VERSION_MAJOR(v)      BM_LCDIF_VERSION_MAJOR
+#define BF_LCDIF_VERSION_MAJOR_V(e)     BF_LCDIF_VERSION_MAJOR(BV_LCDIF_VERSION_MAJOR__##e)
+#define BFM_LCDIF_VERSION_MAJOR_V(v)    BM_LCDIF_VERSION_MAJOR
+#define BP_LCDIF_VERSION_MINOR          16
+#define BM_LCDIF_VERSION_MINOR          0xff0000
+#define BF_LCDIF_VERSION_MINOR(v)       (((v) & 0xff) << 16)
+#define BFM_LCDIF_VERSION_MINOR(v)      BM_LCDIF_VERSION_MINOR
+#define BF_LCDIF_VERSION_MINOR_V(e)     BF_LCDIF_VERSION_MINOR(BV_LCDIF_VERSION_MINOR__##e)
+#define BFM_LCDIF_VERSION_MINOR_V(v)    BM_LCDIF_VERSION_MINOR
+#define BP_LCDIF_VERSION_STEP           0
+#define BM_LCDIF_VERSION_STEP           0xffff
+#define BF_LCDIF_VERSION_STEP(v)        (((v) & 0xffff) << 0)
+#define BFM_LCDIF_VERSION_STEP(v)       BM_LCDIF_VERSION_STEP
+#define BF_LCDIF_VERSION_STEP_V(e)      BF_LCDIF_VERSION_STEP(BV_LCDIF_VERSION_STEP__##e)
+#define BFM_LCDIF_VERSION_STEP_V(v)     BM_LCDIF_VERSION_STEP
+
+#define HW_LCDIF_DEBUG0                                 HW(LCDIF_DEBUG0)
+#define HWA_LCDIF_DEBUG0                                (0x80030000 + 0xe0)
+#define HWT_LCDIF_DEBUG0                                HWIO_32_RW
+#define HWN_LCDIF_DEBUG0                                LCDIF_DEBUG0
+#define HWI_LCDIF_DEBUG0                                
+#define BP_LCDIF_DEBUG0_STREAMING_END_DETECTED          31
+#define BM_LCDIF_DEBUG0_STREAMING_END_DETECTED          0x80000000
+#define BF_LCDIF_DEBUG0_STREAMING_END_DETECTED(v)       (((v) & 0x1) << 31)
+#define BFM_LCDIF_DEBUG0_STREAMING_END_DETECTED(v)      BM_LCDIF_DEBUG0_STREAMING_END_DETECTED
+#define BF_LCDIF_DEBUG0_STREAMING_END_DETECTED_V(e)     BF_LCDIF_DEBUG0_STREAMING_END_DETECTED(BV_LCDIF_DEBUG0_STREAMING_END_DETECTED__##e)
+#define BFM_LCDIF_DEBUG0_STREAMING_END_DETECTED_V(v)    BM_LCDIF_DEBUG0_STREAMING_END_DETECTED
+#define BP_LCDIF_DEBUG0_WAIT_FOR_VSYNC_EDGE_OUT         30
+#define BM_LCDIF_DEBUG0_WAIT_FOR_VSYNC_EDGE_OUT         0x40000000
+#define BF_LCDIF_DEBUG0_WAIT_FOR_VSYNC_EDGE_OUT(v)      (((v) & 0x1) << 30)
+#define BFM_LCDIF_DEBUG0_WAIT_FOR_VSYNC_EDGE_OUT(v)     BM_LCDIF_DEBUG0_WAIT_FOR_VSYNC_EDGE_OUT
+#define BF_LCDIF_DEBUG0_WAIT_FOR_VSYNC_EDGE_OUT_V(e)    BF_LCDIF_DEBUG0_WAIT_FOR_VSYNC_EDGE_OUT(BV_LCDIF_DEBUG0_WAIT_FOR_VSYNC_EDGE_OUT__##e)
+#define BFM_LCDIF_DEBUG0_WAIT_FOR_VSYNC_EDGE_OUT_V(v)   BM_LCDIF_DEBUG0_WAIT_FOR_VSYNC_EDGE_OUT
+#define BP_LCDIF_DEBUG0_SYNC_SIGNALS_ON_REG             29
+#define BM_LCDIF_DEBUG0_SYNC_SIGNALS_ON_REG             0x20000000
+#define BF_LCDIF_DEBUG0_SYNC_SIGNALS_ON_REG(v)          (((v) & 0x1) << 29)
+#define BFM_LCDIF_DEBUG0_SYNC_SIGNALS_ON_REG(v)         BM_LCDIF_DEBUG0_SYNC_SIGNALS_ON_REG
+#define BF_LCDIF_DEBUG0_SYNC_SIGNALS_ON_REG_V(e)        BF_LCDIF_DEBUG0_SYNC_SIGNALS_ON_REG(BV_LCDIF_DEBUG0_SYNC_SIGNALS_ON_REG__##e)
+#define BFM_LCDIF_DEBUG0_SYNC_SIGNALS_ON_REG_V(v)       BM_LCDIF_DEBUG0_SYNC_SIGNALS_ON_REG
+#define BP_LCDIF_DEBUG0_DMACMDKICK                      28
+#define BM_LCDIF_DEBUG0_DMACMDKICK                      0x10000000
+#define BF_LCDIF_DEBUG0_DMACMDKICK(v)                   (((v) & 0x1) << 28)
+#define BFM_LCDIF_DEBUG0_DMACMDKICK(v)                  BM_LCDIF_DEBUG0_DMACMDKICK
+#define BF_LCDIF_DEBUG0_DMACMDKICK_V(e)                 BF_LCDIF_DEBUG0_DMACMDKICK(BV_LCDIF_DEBUG0_DMACMDKICK__##e)
+#define BFM_LCDIF_DEBUG0_DMACMDKICK_V(v)                BM_LCDIF_DEBUG0_DMACMDKICK
+#define BP_LCDIF_DEBUG0_ENABLE                          27
+#define BM_LCDIF_DEBUG0_ENABLE                          0x8000000
+#define BF_LCDIF_DEBUG0_ENABLE(v)                       (((v) & 0x1) << 27)
+#define BFM_LCDIF_DEBUG0_ENABLE(v)                      BM_LCDIF_DEBUG0_ENABLE
+#define BF_LCDIF_DEBUG0_ENABLE_V(e)                     BF_LCDIF_DEBUG0_ENABLE(BV_LCDIF_DEBUG0_ENABLE__##e)
+#define BFM_LCDIF_DEBUG0_ENABLE_V(v)                    BM_LCDIF_DEBUG0_ENABLE
+#define BP_LCDIF_DEBUG0_HSYNC                           26
+#define BM_LCDIF_DEBUG0_HSYNC                           0x4000000
+#define BF_LCDIF_DEBUG0_HSYNC(v)                        (((v) & 0x1) << 26)
+#define BFM_LCDIF_DEBUG0_HSYNC(v)                       BM_LCDIF_DEBUG0_HSYNC
+#define BF_LCDIF_DEBUG0_HSYNC_V(e)                      BF_LCDIF_DEBUG0_HSYNC(BV_LCDIF_DEBUG0_HSYNC__##e)
+#define BFM_LCDIF_DEBUG0_HSYNC_V(v)                     BM_LCDIF_DEBUG0_HSYNC
+#define BP_LCDIF_DEBUG0_VSYNC                           25
+#define BM_LCDIF_DEBUG0_VSYNC                           0x2000000
+#define BF_LCDIF_DEBUG0_VSYNC(v)                        (((v) & 0x1) << 25)
+#define BFM_LCDIF_DEBUG0_VSYNC(v)                       BM_LCDIF_DEBUG0_VSYNC
+#define BF_LCDIF_DEBUG0_VSYNC_V(e)                      BF_LCDIF_DEBUG0_VSYNC(BV_LCDIF_DEBUG0_VSYNC__##e)
+#define BFM_LCDIF_DEBUG0_VSYNC_V(v)                     BM_LCDIF_DEBUG0_VSYNC
+#define BP_LCDIF_DEBUG0_CUR_FRAME_TX                    24
+#define BM_LCDIF_DEBUG0_CUR_FRAME_TX                    0x1000000
+#define BF_LCDIF_DEBUG0_CUR_FRAME_TX(v)                 (((v) & 0x1) << 24)
+#define BFM_LCDIF_DEBUG0_CUR_FRAME_TX(v)                BM_LCDIF_DEBUG0_CUR_FRAME_TX
+#define BF_LCDIF_DEBUG0_CUR_FRAME_TX_V(e)               BF_LCDIF_DEBUG0_CUR_FRAME_TX(BV_LCDIF_DEBUG0_CUR_FRAME_TX__##e)
+#define BFM_LCDIF_DEBUG0_CUR_FRAME_TX_V(v)              BM_LCDIF_DEBUG0_CUR_FRAME_TX
+#define BP_LCDIF_DEBUG0_EMPTY_WORD                      23
+#define BM_LCDIF_DEBUG0_EMPTY_WORD                      0x800000
+#define BF_LCDIF_DEBUG0_EMPTY_WORD(v)                   (((v) & 0x1) << 23)
+#define BFM_LCDIF_DEBUG0_EMPTY_WORD(v)                  BM_LCDIF_DEBUG0_EMPTY_WORD
+#define BF_LCDIF_DEBUG0_EMPTY_WORD_V(e)                 BF_LCDIF_DEBUG0_EMPTY_WORD(BV_LCDIF_DEBUG0_EMPTY_WORD__##e)
+#define BFM_LCDIF_DEBUG0_EMPTY_WORD_V(v)                BM_LCDIF_DEBUG0_EMPTY_WORD
+#define BP_LCDIF_DEBUG0_CUR_STATE                       16
+#define BM_LCDIF_DEBUG0_CUR_STATE                       0x7f0000
+#define BF_LCDIF_DEBUG0_CUR_STATE(v)                    (((v) & 0x7f) << 16)
+#define BFM_LCDIF_DEBUG0_CUR_STATE(v)                   BM_LCDIF_DEBUG0_CUR_STATE
+#define BF_LCDIF_DEBUG0_CUR_STATE_V(e)                  BF_LCDIF_DEBUG0_CUR_STATE(BV_LCDIF_DEBUG0_CUR_STATE__##e)
+#define BFM_LCDIF_DEBUG0_CUR_STATE_V(v)                 BM_LCDIF_DEBUG0_CUR_STATE
+#define BP_LCDIF_DEBUG0_DATA_COUNT                      0
+#define BM_LCDIF_DEBUG0_DATA_COUNT                      0xffff
+#define BF_LCDIF_DEBUG0_DATA_COUNT(v)                   (((v) & 0xffff) << 0)
+#define BFM_LCDIF_DEBUG0_DATA_COUNT(v)                  BM_LCDIF_DEBUG0_DATA_COUNT
+#define BF_LCDIF_DEBUG0_DATA_COUNT_V(e)                 BF_LCDIF_DEBUG0_DATA_COUNT(BV_LCDIF_DEBUG0_DATA_COUNT__##e)
+#define BFM_LCDIF_DEBUG0_DATA_COUNT_V(v)                BM_LCDIF_DEBUG0_DATA_COUNT
+
+#endif /* __HEADERGEN_STMP3700_LCDIF_H__*/
diff --git a/firmware/target/arm/imx233/regs/stmp3700/lradc.h b/firmware/target/arm/imx233/regs/stmp3700/lradc.h
new file mode 100644
index 0000000000..a448346ed6
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3700/lradc.h
@@ -0,0 +1,1013 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * stmp3700 version: 2.4.0
+ * stmp3700 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_STMP3700_LRADC_H__
+#define __HEADERGEN_STMP3700_LRADC_H__
+
+#define HW_LRADC_CTRL0                              HW(LRADC_CTRL0)
+#define HWA_LRADC_CTRL0                             (0x80050000 + 0x0)
+#define HWT_LRADC_CTRL0                             HWIO_32_RW
+#define HWN_LRADC_CTRL0                             LRADC_CTRL0
+#define HWI_LRADC_CTRL0                             
+#define HW_LRADC_CTRL0_SET                          HW(LRADC_CTRL0_SET)
+#define HWA_LRADC_CTRL0_SET                         (HWA_LRADC_CTRL0 + 0x4)
+#define HWT_LRADC_CTRL0_SET                         HWIO_32_WO
+#define HWN_LRADC_CTRL0_SET                         LRADC_CTRL0
+#define HWI_LRADC_CTRL0_SET                         
+#define HW_LRADC_CTRL0_CLR                          HW(LRADC_CTRL0_CLR)
+#define HWA_LRADC_CTRL0_CLR                         (HWA_LRADC_CTRL0 + 0x8)
+#define HWT_LRADC_CTRL0_CLR                         HWIO_32_WO
+#define HWN_LRADC_CTRL0_CLR                         LRADC_CTRL0
+#define HWI_LRADC_CTRL0_CLR                         
+#define HW_LRADC_CTRL0_TOG                          HW(LRADC_CTRL0_TOG)
+#define HWA_LRADC_CTRL0_TOG                         (HWA_LRADC_CTRL0 + 0xc)
+#define HWT_LRADC_CTRL0_TOG                         HWIO_32_WO
+#define HWN_LRADC_CTRL0_TOG                         LRADC_CTRL0
+#define HWI_LRADC_CTRL0_TOG                         
+#define BP_LRADC_CTRL0_SFTRST                       31
+#define BM_LRADC_CTRL0_SFTRST                       0x80000000
+#define BF_LRADC_CTRL0_SFTRST(v)                    (((v) & 0x1) << 31)
+#define BFM_LRADC_CTRL0_SFTRST(v)                   BM_LRADC_CTRL0_SFTRST
+#define BF_LRADC_CTRL0_SFTRST_V(e)                  BF_LRADC_CTRL0_SFTRST(BV_LRADC_CTRL0_SFTRST__##e)
+#define BFM_LRADC_CTRL0_SFTRST_V(v)                 BM_LRADC_CTRL0_SFTRST
+#define BP_LRADC_CTRL0_CLKGATE                      30
+#define BM_LRADC_CTRL0_CLKGATE                      0x40000000
+#define BF_LRADC_CTRL0_CLKGATE(v)                   (((v) & 0x1) << 30)
+#define BFM_LRADC_CTRL0_CLKGATE(v)                  BM_LRADC_CTRL0_CLKGATE
+#define BF_LRADC_CTRL0_CLKGATE_V(e)                 BF_LRADC_CTRL0_CLKGATE(BV_LRADC_CTRL0_CLKGATE__##e)
+#define BFM_LRADC_CTRL0_CLKGATE_V(v)                BM_LRADC_CTRL0_CLKGATE
+#define BP_LRADC_CTRL0_ONCHIP_GROUNDREF             21
+#define BM_LRADC_CTRL0_ONCHIP_GROUNDREF             0x200000
+#define BV_LRADC_CTRL0_ONCHIP_GROUNDREF__OFF        0x0
+#define BV_LRADC_CTRL0_ONCHIP_GROUNDREF__ON         0x1
+#define BF_LRADC_CTRL0_ONCHIP_GROUNDREF(v)          (((v) & 0x1) << 21)
+#define BFM_LRADC_CTRL0_ONCHIP_GROUNDREF(v)         BM_LRADC_CTRL0_ONCHIP_GROUNDREF
+#define BF_LRADC_CTRL0_ONCHIP_GROUNDREF_V(e)        BF_LRADC_CTRL0_ONCHIP_GROUNDREF(BV_LRADC_CTRL0_ONCHIP_GROUNDREF__##e)
+#define BFM_LRADC_CTRL0_ONCHIP_GROUNDREF_V(v)       BM_LRADC_CTRL0_ONCHIP_GROUNDREF
+#define BP_LRADC_CTRL0_TOUCH_DETECT_ENABLE          20
+#define BM_LRADC_CTRL0_TOUCH_DETECT_ENABLE          0x100000
+#define BV_LRADC_CTRL0_TOUCH_DETECT_ENABLE__OFF     0x0
+#define BV_LRADC_CTRL0_TOUCH_DETECT_ENABLE__ON      0x1
+#define BF_LRADC_CTRL0_TOUCH_DETECT_ENABLE(v)       (((v) & 0x1) << 20)
+#define BFM_LRADC_CTRL0_TOUCH_DETECT_ENABLE(v)      BM_LRADC_CTRL0_TOUCH_DETECT_ENABLE
+#define BF_LRADC_CTRL0_TOUCH_DETECT_ENABLE_V(e)     BF_LRADC_CTRL0_TOUCH_DETECT_ENABLE(BV_LRADC_CTRL0_TOUCH_DETECT_ENABLE__##e)
+#define BFM_LRADC_CTRL0_TOUCH_DETECT_ENABLE_V(v)    BM_LRADC_CTRL0_TOUCH_DETECT_ENABLE
+#define BP_LRADC_CTRL0_YMINUS_ENABLE                19
+#define BM_LRADC_CTRL0_YMINUS_ENABLE                0x80000
+#define BV_LRADC_CTRL0_YMINUS_ENABLE__OFF           0x0
+#define BV_LRADC_CTRL0_YMINUS_ENABLE__ON            0x1
+#define BF_LRADC_CTRL0_YMINUS_ENABLE(v)             (((v) & 0x1) << 19)
+#define BFM_LRADC_CTRL0_YMINUS_ENABLE(v)            BM_LRADC_CTRL0_YMINUS_ENABLE
+#define BF_LRADC_CTRL0_YMINUS_ENABLE_V(e)           BF_LRADC_CTRL0_YMINUS_ENABLE(BV_LRADC_CTRL0_YMINUS_ENABLE__##e)
+#define BFM_LRADC_CTRL0_YMINUS_ENABLE_V(v)          BM_LRADC_CTRL0_YMINUS_ENABLE
+#define BP_LRADC_CTRL0_XMINUS_ENABLE                18
+#define BM_LRADC_CTRL0_XMINUS_ENABLE                0x40000
+#define BV_LRADC_CTRL0_XMINUS_ENABLE__OFF           0x0
+#define BV_LRADC_CTRL0_XMINUS_ENABLE__ON            0x1
+#define BF_LRADC_CTRL0_XMINUS_ENABLE(v)             (((v) & 0x1) << 18)
+#define BFM_LRADC_CTRL0_XMINUS_ENABLE(v)            BM_LRADC_CTRL0_XMINUS_ENABLE
+#define BF_LRADC_CTRL0_XMINUS_ENABLE_V(e)           BF_LRADC_CTRL0_XMINUS_ENABLE(BV_LRADC_CTRL0_XMINUS_ENABLE__##e)
+#define BFM_LRADC_CTRL0_XMINUS_ENABLE_V(v)          BM_LRADC_CTRL0_XMINUS_ENABLE
+#define BP_LRADC_CTRL0_YPLUS_ENABLE                 17
+#define BM_LRADC_CTRL0_YPLUS_ENABLE                 0x20000
+#define BV_LRADC_CTRL0_YPLUS_ENABLE__OFF            0x0
+#define BV_LRADC_CTRL0_YPLUS_ENABLE__ON             0x1
+#define BF_LRADC_CTRL0_YPLUS_ENABLE(v)              (((v) & 0x1) << 17)
+#define BFM_LRADC_CTRL0_YPLUS_ENABLE(v)             BM_LRADC_CTRL0_YPLUS_ENABLE
+#define BF_LRADC_CTRL0_YPLUS_ENABLE_V(e)            BF_LRADC_CTRL0_YPLUS_ENABLE(BV_LRADC_CTRL0_YPLUS_ENABLE__##e)
+#define BFM_LRADC_CTRL0_YPLUS_ENABLE_V(v)           BM_LRADC_CTRL0_YPLUS_ENABLE
+#define BP_LRADC_CTRL0_XPLUS_ENABLE                 16
+#define BM_LRADC_CTRL0_XPLUS_ENABLE                 0x10000
+#define BV_LRADC_CTRL0_XPLUS_ENABLE__OFF            0x0
+#define BV_LRADC_CTRL0_XPLUS_ENABLE__ON             0x1
+#define BF_LRADC_CTRL0_XPLUS_ENABLE(v)              (((v) & 0x1) << 16)
+#define BFM_LRADC_CTRL0_XPLUS_ENABLE(v)             BM_LRADC_CTRL0_XPLUS_ENABLE
+#define BF_LRADC_CTRL0_XPLUS_ENABLE_V(e)            BF_LRADC_CTRL0_XPLUS_ENABLE(BV_LRADC_CTRL0_XPLUS_ENABLE__##e)
+#define BFM_LRADC_CTRL0_XPLUS_ENABLE_V(v)           BM_LRADC_CTRL0_XPLUS_ENABLE
+#define BP_LRADC_CTRL0_SCHEDULE                     0
+#define BM_LRADC_CTRL0_SCHEDULE                     0xff
+#define BF_LRADC_CTRL0_SCHEDULE(v)                  (((v) & 0xff) << 0)
+#define BFM_LRADC_CTRL0_SCHEDULE(v)                 BM_LRADC_CTRL0_SCHEDULE
+#define BF_LRADC_CTRL0_SCHEDULE_V(e)                BF_LRADC_CTRL0_SCHEDULE(BV_LRADC_CTRL0_SCHEDULE__##e)
+#define BFM_LRADC_CTRL0_SCHEDULE_V(v)               BM_LRADC_CTRL0_SCHEDULE
+
+#define HW_LRADC_CTRL1                              HW(LRADC_CTRL1)
+#define HWA_LRADC_CTRL1                             (0x80050000 + 0x10)
+#define HWT_LRADC_CTRL1                             HWIO_32_RW
+#define HWN_LRADC_CTRL1                             LRADC_CTRL1
+#define HWI_LRADC_CTRL1                             
+#define HW_LRADC_CTRL1_SET                          HW(LRADC_CTRL1_SET)
+#define HWA_LRADC_CTRL1_SET                         (HWA_LRADC_CTRL1 + 0x4)
+#define HWT_LRADC_CTRL1_SET                         HWIO_32_WO
+#define HWN_LRADC_CTRL1_SET                         LRADC_CTRL1
+#define HWI_LRADC_CTRL1_SET                         
+#define HW_LRADC_CTRL1_CLR                          HW(LRADC_CTRL1_CLR)
+#define HWA_LRADC_CTRL1_CLR                         (HWA_LRADC_CTRL1 + 0x8)
+#define HWT_LRADC_CTRL1_CLR                         HWIO_32_WO
+#define HWN_LRADC_CTRL1_CLR                         LRADC_CTRL1
+#define HWI_LRADC_CTRL1_CLR                         
+#define HW_LRADC_CTRL1_TOG                          HW(LRADC_CTRL1_TOG)
+#define HWA_LRADC_CTRL1_TOG                         (HWA_LRADC_CTRL1 + 0xc)
+#define HWT_LRADC_CTRL1_TOG                         HWIO_32_WO
+#define HWN_LRADC_CTRL1_TOG                         LRADC_CTRL1
+#define HWI_LRADC_CTRL1_TOG                         
+#define BP_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN          24
+#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN          0x1000000
+#define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN__DISABLE 0x0
+#define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN__ENABLE  0x1
+#define BF_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN(v)       (((v) & 0x1) << 24)
+#define BFM_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN(v)      BM_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN
+#define BF_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN_V(e)     BF_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN(BV_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN__##e)
+#define BFM_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN_V(v)    BM_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN
+#define BP_LRADC_CTRL1_LRADC7_IRQ_EN                23
+#define BM_LRADC_CTRL1_LRADC7_IRQ_EN                0x800000
+#define BV_LRADC_CTRL1_LRADC7_IRQ_EN__DISABLE       0x0
+#define BV_LRADC_CTRL1_LRADC7_IRQ_EN__ENABLE        0x1
+#define BF_LRADC_CTRL1_LRADC7_IRQ_EN(v)             (((v) & 0x1) << 23)
+#define BFM_LRADC_CTRL1_LRADC7_IRQ_EN(v)            BM_LRADC_CTRL1_LRADC7_IRQ_EN
+#define BF_LRADC_CTRL1_LRADC7_IRQ_EN_V(e)           BF_LRADC_CTRL1_LRADC7_IRQ_EN(BV_LRADC_CTRL1_LRADC7_IRQ_EN__##e)
+#define BFM_LRADC_CTRL1_LRADC7_IRQ_EN_V(v)          BM_LRADC_CTRL1_LRADC7_IRQ_EN
+#define BP_LRADC_CTRL1_LRADC6_IRQ_EN                22
+#define BM_LRADC_CTRL1_LRADC6_IRQ_EN                0x400000
+#define BV_LRADC_CTRL1_LRADC6_IRQ_EN__DISABLE       0x0
+#define BV_LRADC_CTRL1_LRADC6_IRQ_EN__ENABLE        0x1
+#define BF_LRADC_CTRL1_LRADC6_IRQ_EN(v)             (((v) & 0x1) << 22)
+#define BFM_LRADC_CTRL1_LRADC6_IRQ_EN(v)            BM_LRADC_CTRL1_LRADC6_IRQ_EN
+#define BF_LRADC_CTRL1_LRADC6_IRQ_EN_V(e)           BF_LRADC_CTRL1_LRADC6_IRQ_EN(BV_LRADC_CTRL1_LRADC6_IRQ_EN__##e)
+#define BFM_LRADC_CTRL1_LRADC6_IRQ_EN_V(v)          BM_LRADC_CTRL1_LRADC6_IRQ_EN
+#define BP_LRADC_CTRL1_LRADC5_IRQ_EN                21
+#define BM_LRADC_CTRL1_LRADC5_IRQ_EN                0x200000
+#define BV_LRADC_CTRL1_LRADC5_IRQ_EN__DISABLE       0x0
+#define BV_LRADC_CTRL1_LRADC5_IRQ_EN__ENABLE        0x1
+#define BF_LRADC_CTRL1_LRADC5_IRQ_EN(v)             (((v) & 0x1) << 21)
+#define BFM_LRADC_CTRL1_LRADC5_IRQ_EN(v)            BM_LRADC_CTRL1_LRADC5_IRQ_EN
+#define BF_LRADC_CTRL1_LRADC5_IRQ_EN_V(e)           BF_LRADC_CTRL1_LRADC5_IRQ_EN(BV_LRADC_CTRL1_LRADC5_IRQ_EN__##e)
+#define BFM_LRADC_CTRL1_LRADC5_IRQ_EN_V(v)          BM_LRADC_CTRL1_LRADC5_IRQ_EN
+#define BP_LRADC_CTRL1_LRADC4_IRQ_EN                20
+#define BM_LRADC_CTRL1_LRADC4_IRQ_EN                0x100000
+#define BV_LRADC_CTRL1_LRADC4_IRQ_EN__DISABLE       0x0
+#define BV_LRADC_CTRL1_LRADC4_IRQ_EN__ENABLE        0x1
+#define BF_LRADC_CTRL1_LRADC4_IRQ_EN(v)             (((v) & 0x1) << 20)
+#define BFM_LRADC_CTRL1_LRADC4_IRQ_EN(v)            BM_LRADC_CTRL1_LRADC4_IRQ_EN
+#define BF_LRADC_CTRL1_LRADC4_IRQ_EN_V(e)           BF_LRADC_CTRL1_LRADC4_IRQ_EN(BV_LRADC_CTRL1_LRADC4_IRQ_EN__##e)
+#define BFM_LRADC_CTRL1_LRADC4_IRQ_EN_V(v)          BM_LRADC_CTRL1_LRADC4_IRQ_EN
+#define BP_LRADC_CTRL1_LRADC3_IRQ_EN                19
+#define BM_LRADC_CTRL1_LRADC3_IRQ_EN                0x80000
+#define BV_LRADC_CTRL1_LRADC3_IRQ_EN__DISABLE       0x0
+#define BV_LRADC_CTRL1_LRADC3_IRQ_EN__ENABLE        0x1
+#define BF_LRADC_CTRL1_LRADC3_IRQ_EN(v)             (((v) & 0x1) << 19)
+#define BFM_LRADC_CTRL1_LRADC3_IRQ_EN(v)            BM_LRADC_CTRL1_LRADC3_IRQ_EN
+#define BF_LRADC_CTRL1_LRADC3_IRQ_EN_V(e)           BF_LRADC_CTRL1_LRADC3_IRQ_EN(BV_LRADC_CTRL1_LRADC3_IRQ_EN__##e)
+#define BFM_LRADC_CTRL1_LRADC3_IRQ_EN_V(v)          BM_LRADC_CTRL1_LRADC3_IRQ_EN
+#define BP_LRADC_CTRL1_LRADC2_IRQ_EN                18
+#define BM_LRADC_CTRL1_LRADC2_IRQ_EN                0x40000
+#define BV_LRADC_CTRL1_LRADC2_IRQ_EN__DISABLE       0x0
+#define BV_LRADC_CTRL1_LRADC2_IRQ_EN__ENABLE        0x1
+#define BF_LRADC_CTRL1_LRADC2_IRQ_EN(v)             (((v) & 0x1) << 18)
+#define BFM_LRADC_CTRL1_LRADC2_IRQ_EN(v)            BM_LRADC_CTRL1_LRADC2_IRQ_EN
+#define BF_LRADC_CTRL1_LRADC2_IRQ_EN_V(e)           BF_LRADC_CTRL1_LRADC2_IRQ_EN(BV_LRADC_CTRL1_LRADC2_IRQ_EN__##e)
+#define BFM_LRADC_CTRL1_LRADC2_IRQ_EN_V(v)          BM_LRADC_CTRL1_LRADC2_IRQ_EN
+#define BP_LRADC_CTRL1_LRADC1_IRQ_EN                17
+#define BM_LRADC_CTRL1_LRADC1_IRQ_EN                0x20000
+#define BV_LRADC_CTRL1_LRADC1_IRQ_EN__DISABLE       0x0
+#define BV_LRADC_CTRL1_LRADC1_IRQ_EN__ENABLE        0x1
+#define BF_LRADC_CTRL1_LRADC1_IRQ_EN(v)             (((v) & 0x1) << 17)
+#define BFM_LRADC_CTRL1_LRADC1_IRQ_EN(v)            BM_LRADC_CTRL1_LRADC1_IRQ_EN
+#define BF_LRADC_CTRL1_LRADC1_IRQ_EN_V(e)           BF_LRADC_CTRL1_LRADC1_IRQ_EN(BV_LRADC_CTRL1_LRADC1_IRQ_EN__##e)
+#define BFM_LRADC_CTRL1_LRADC1_IRQ_EN_V(v)          BM_LRADC_CTRL1_LRADC1_IRQ_EN
+#define BP_LRADC_CTRL1_LRADC0_IRQ_EN                16
+#define BM_LRADC_CTRL1_LRADC0_IRQ_EN                0x10000
+#define BV_LRADC_CTRL1_LRADC0_IRQ_EN__DISABLE       0x0
+#define BV_LRADC_CTRL1_LRADC0_IRQ_EN__ENABLE        0x1
+#define BF_LRADC_CTRL1_LRADC0_IRQ_EN(v)             (((v) & 0x1) << 16)
+#define BFM_LRADC_CTRL1_LRADC0_IRQ_EN(v)            BM_LRADC_CTRL1_LRADC0_IRQ_EN
+#define BF_LRADC_CTRL1_LRADC0_IRQ_EN_V(e)           BF_LRADC_CTRL1_LRADC0_IRQ_EN(BV_LRADC_CTRL1_LRADC0_IRQ_EN__##e)
+#define BFM_LRADC_CTRL1_LRADC0_IRQ_EN_V(v)          BM_LRADC_CTRL1_LRADC0_IRQ_EN
+#define BP_LRADC_CTRL1_TOUCH_DETECT_IRQ             8
+#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ             0x100
+#define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ__CLEAR      0x0
+#define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ__PENDING    0x1
+#define BF_LRADC_CTRL1_TOUCH_DETECT_IRQ(v)          (((v) & 0x1) << 8)
+#define BFM_LRADC_CTRL1_TOUCH_DETECT_IRQ(v)         BM_LRADC_CTRL1_TOUCH_DETECT_IRQ
+#define BF_LRADC_CTRL1_TOUCH_DETECT_IRQ_V(e)        BF_LRADC_CTRL1_TOUCH_DETECT_IRQ(BV_LRADC_CTRL1_TOUCH_DETECT_IRQ__##e)
+#define BFM_LRADC_CTRL1_TOUCH_DETECT_IRQ_V(v)       BM_LRADC_CTRL1_TOUCH_DETECT_IRQ
+#define BP_LRADC_CTRL1_LRADC7_IRQ                   7
+#define BM_LRADC_CTRL1_LRADC7_IRQ                   0x80
+#define BV_LRADC_CTRL1_LRADC7_IRQ__CLEAR            0x0
+#define BV_LRADC_CTRL1_LRADC7_IRQ__PENDING          0x1
+#define BF_LRADC_CTRL1_LRADC7_IRQ(v)                (((v) & 0x1) << 7)
+#define BFM_LRADC_CTRL1_LRADC7_IRQ(v)               BM_LRADC_CTRL1_LRADC7_IRQ
+#define BF_LRADC_CTRL1_LRADC7_IRQ_V(e)              BF_LRADC_CTRL1_LRADC7_IRQ(BV_LRADC_CTRL1_LRADC7_IRQ__##e)
+#define BFM_LRADC_CTRL1_LRADC7_IRQ_V(v)             BM_LRADC_CTRL1_LRADC7_IRQ
+#define BP_LRADC_CTRL1_LRADC6_IRQ                   6
+#define BM_LRADC_CTRL1_LRADC6_IRQ                   0x40
+#define BV_LRADC_CTRL1_LRADC6_IRQ__CLEAR            0x0
+#define BV_LRADC_CTRL1_LRADC6_IRQ__PENDING          0x1
+#define BF_LRADC_CTRL1_LRADC6_IRQ(v)                (((v) & 0x1) << 6)
+#define BFM_LRADC_CTRL1_LRADC6_IRQ(v)               BM_LRADC_CTRL1_LRADC6_IRQ
+#define BF_LRADC_CTRL1_LRADC6_IRQ_V(e)              BF_LRADC_CTRL1_LRADC6_IRQ(BV_LRADC_CTRL1_LRADC6_IRQ__##e)
+#define BFM_LRADC_CTRL1_LRADC6_IRQ_V(v)             BM_LRADC_CTRL1_LRADC6_IRQ
+#define BP_LRADC_CTRL1_LRADC5_IRQ                   5
+#define BM_LRADC_CTRL1_LRADC5_IRQ                   0x20
+#define BV_LRADC_CTRL1_LRADC5_IRQ__CLEAR            0x0
+#define BV_LRADC_CTRL1_LRADC5_IRQ__PENDING          0x1
+#define BF_LRADC_CTRL1_LRADC5_IRQ(v)                (((v) & 0x1) << 5)
+#define BFM_LRADC_CTRL1_LRADC5_IRQ(v)               BM_LRADC_CTRL1_LRADC5_IRQ
+#define BF_LRADC_CTRL1_LRADC5_IRQ_V(e)              BF_LRADC_CTRL1_LRADC5_IRQ(BV_LRADC_CTRL1_LRADC5_IRQ__##e)
+#define BFM_LRADC_CTRL1_LRADC5_IRQ_V(v)             BM_LRADC_CTRL1_LRADC5_IRQ
+#define BP_LRADC_CTRL1_LRADC4_IRQ                   4
+#define BM_LRADC_CTRL1_LRADC4_IRQ                   0x10
+#define BV_LRADC_CTRL1_LRADC4_IRQ__CLEAR            0x0
+#define BV_LRADC_CTRL1_LRADC4_IRQ__PENDING          0x1
+#define BF_LRADC_CTRL1_LRADC4_IRQ(v)                (((v) & 0x1) << 4)
+#define BFM_LRADC_CTRL1_LRADC4_IRQ(v)               BM_LRADC_CTRL1_LRADC4_IRQ
+#define BF_LRADC_CTRL1_LRADC4_IRQ_V(e)              BF_LRADC_CTRL1_LRADC4_IRQ(BV_LRADC_CTRL1_LRADC4_IRQ__##e)
+#define BFM_LRADC_CTRL1_LRADC4_IRQ_V(v)             BM_LRADC_CTRL1_LRADC4_IRQ
+#define BP_LRADC_CTRL1_LRADC3_IRQ                   3
+#define BM_LRADC_CTRL1_LRADC3_IRQ                   0x8
+#define BV_LRADC_CTRL1_LRADC3_IRQ__CLEAR            0x0
+#define BV_LRADC_CTRL1_LRADC3_IRQ__PENDING          0x1
+#define BF_LRADC_CTRL1_LRADC3_IRQ(v)                (((v) & 0x1) << 3)
+#define BFM_LRADC_CTRL1_LRADC3_IRQ(v)               BM_LRADC_CTRL1_LRADC3_IRQ
+#define BF_LRADC_CTRL1_LRADC3_IRQ_V(e)              BF_LRADC_CTRL1_LRADC3_IRQ(BV_LRADC_CTRL1_LRADC3_IRQ__##e)
+#define BFM_LRADC_CTRL1_LRADC3_IRQ_V(v)             BM_LRADC_CTRL1_LRADC3_IRQ
+#define BP_LRADC_CTRL1_LRADC2_IRQ                   2
+#define BM_LRADC_CTRL1_LRADC2_IRQ                   0x4
+#define BV_LRADC_CTRL1_LRADC2_IRQ__CLEAR            0x0
+#define BV_LRADC_CTRL1_LRADC2_IRQ__PENDING          0x1
+#define BF_LRADC_CTRL1_LRADC2_IRQ(v)                (((v) & 0x1) << 2)
+#define BFM_LRADC_CTRL1_LRADC2_IRQ(v)               BM_LRADC_CTRL1_LRADC2_IRQ
+#define BF_LRADC_CTRL1_LRADC2_IRQ_V(e)              BF_LRADC_CTRL1_LRADC2_IRQ(BV_LRADC_CTRL1_LRADC2_IRQ__##e)
+#define BFM_LRADC_CTRL1_LRADC2_IRQ_V(v)             BM_LRADC_CTRL1_LRADC2_IRQ
+#define BP_LRADC_CTRL1_LRADC1_IRQ                   1
+#define BM_LRADC_CTRL1_LRADC1_IRQ                   0x2
+#define BV_LRADC_CTRL1_LRADC1_IRQ__CLEAR            0x0
+#define BV_LRADC_CTRL1_LRADC1_IRQ__PENDING          0x1
+#define BF_LRADC_CTRL1_LRADC1_IRQ(v)                (((v) & 0x1) << 1)
+#define BFM_LRADC_CTRL1_LRADC1_IRQ(v)               BM_LRADC_CTRL1_LRADC1_IRQ
+#define BF_LRADC_CTRL1_LRADC1_IRQ_V(e)              BF_LRADC_CTRL1_LRADC1_IRQ(BV_LRADC_CTRL1_LRADC1_IRQ__##e)
+#define BFM_LRADC_CTRL1_LRADC1_IRQ_V(v)             BM_LRADC_CTRL1_LRADC1_IRQ
+#define BP_LRADC_CTRL1_LRADC0_IRQ                   0
+#define BM_LRADC_CTRL1_LRADC0_IRQ                   0x1
+#define BV_LRADC_CTRL1_LRADC0_IRQ__CLEAR            0x0
+#define BV_LRADC_CTRL1_LRADC0_IRQ__PENDING          0x1
+#define BF_LRADC_CTRL1_LRADC0_IRQ(v)                (((v) & 0x1) << 0)
+#define BFM_LRADC_CTRL1_LRADC0_IRQ(v)               BM_LRADC_CTRL1_LRADC0_IRQ
+#define BF_LRADC_CTRL1_LRADC0_IRQ_V(e)              BF_LRADC_CTRL1_LRADC0_IRQ(BV_LRADC_CTRL1_LRADC0_IRQ__##e)
+#define BFM_LRADC_CTRL1_LRADC0_IRQ_V(v)             BM_LRADC_CTRL1_LRADC0_IRQ
+
+#define HW_LRADC_CTRL2                                  HW(LRADC_CTRL2)
+#define HWA_LRADC_CTRL2                                 (0x80050000 + 0x20)
+#define HWT_LRADC_CTRL2                                 HWIO_32_RW
+#define HWN_LRADC_CTRL2                                 LRADC_CTRL2
+#define HWI_LRADC_CTRL2                                 
+#define HW_LRADC_CTRL2_SET                              HW(LRADC_CTRL2_SET)
+#define HWA_LRADC_CTRL2_SET                             (HWA_LRADC_CTRL2 + 0x4)
+#define HWT_LRADC_CTRL2_SET                             HWIO_32_WO
+#define HWN_LRADC_CTRL2_SET                             LRADC_CTRL2
+#define HWI_LRADC_CTRL2_SET                             
+#define HW_LRADC_CTRL2_CLR                              HW(LRADC_CTRL2_CLR)
+#define HWA_LRADC_CTRL2_CLR                             (HWA_LRADC_CTRL2 + 0x8)
+#define HWT_LRADC_CTRL2_CLR                             HWIO_32_WO
+#define HWN_LRADC_CTRL2_CLR                             LRADC_CTRL2
+#define HWI_LRADC_CTRL2_CLR                             
+#define HW_LRADC_CTRL2_TOG                              HW(LRADC_CTRL2_TOG)
+#define HWA_LRADC_CTRL2_TOG                             (HWA_LRADC_CTRL2 + 0xc)
+#define HWT_LRADC_CTRL2_TOG                             HWIO_32_WO
+#define HWN_LRADC_CTRL2_TOG                             LRADC_CTRL2
+#define HWI_LRADC_CTRL2_TOG                             
+#define BP_LRADC_CTRL2_DIVIDE_BY_TWO                    24
+#define BM_LRADC_CTRL2_DIVIDE_BY_TWO                    0xff000000
+#define BF_LRADC_CTRL2_DIVIDE_BY_TWO(v)                 (((v) & 0xff) << 24)
+#define BFM_LRADC_CTRL2_DIVIDE_BY_TWO(v)                BM_LRADC_CTRL2_DIVIDE_BY_TWO
+#define BF_LRADC_CTRL2_DIVIDE_BY_TWO_V(e)               BF_LRADC_CTRL2_DIVIDE_BY_TWO(BV_LRADC_CTRL2_DIVIDE_BY_TWO__##e)
+#define BFM_LRADC_CTRL2_DIVIDE_BY_TWO_V(v)              BM_LRADC_CTRL2_DIVIDE_BY_TWO
+#define BP_LRADC_CTRL2_BL_AMP_BYPASS                    23
+#define BM_LRADC_CTRL2_BL_AMP_BYPASS                    0x800000
+#define BV_LRADC_CTRL2_BL_AMP_BYPASS__DISABLE           0x0
+#define BV_LRADC_CTRL2_BL_AMP_BYPASS__ENABLE            0x1
+#define BF_LRADC_CTRL2_BL_AMP_BYPASS(v)                 (((v) & 0x1) << 23)
+#define BFM_LRADC_CTRL2_BL_AMP_BYPASS(v)                BM_LRADC_CTRL2_BL_AMP_BYPASS
+#define BF_LRADC_CTRL2_BL_AMP_BYPASS_V(e)               BF_LRADC_CTRL2_BL_AMP_BYPASS(BV_LRADC_CTRL2_BL_AMP_BYPASS__##e)
+#define BFM_LRADC_CTRL2_BL_AMP_BYPASS_V(v)              BM_LRADC_CTRL2_BL_AMP_BYPASS
+#define BP_LRADC_CTRL2_BL_ENABLE                        22
+#define BM_LRADC_CTRL2_BL_ENABLE                        0x400000
+#define BF_LRADC_CTRL2_BL_ENABLE(v)                     (((v) & 0x1) << 22)
+#define BFM_LRADC_CTRL2_BL_ENABLE(v)                    BM_LRADC_CTRL2_BL_ENABLE
+#define BF_LRADC_CTRL2_BL_ENABLE_V(e)                   BF_LRADC_CTRL2_BL_ENABLE(BV_LRADC_CTRL2_BL_ENABLE__##e)
+#define BFM_LRADC_CTRL2_BL_ENABLE_V(v)                  BM_LRADC_CTRL2_BL_ENABLE
+#define BP_LRADC_CTRL2_BL_MUX_SELECT                    21
+#define BM_LRADC_CTRL2_BL_MUX_SELECT                    0x200000
+#define BF_LRADC_CTRL2_BL_MUX_SELECT(v)                 (((v) & 0x1) << 21)
+#define BFM_LRADC_CTRL2_BL_MUX_SELECT(v)                BM_LRADC_CTRL2_BL_MUX_SELECT
+#define BF_LRADC_CTRL2_BL_MUX_SELECT_V(e)               BF_LRADC_CTRL2_BL_MUX_SELECT(BV_LRADC_CTRL2_BL_MUX_SELECT__##e)
+#define BFM_LRADC_CTRL2_BL_MUX_SELECT_V(v)              BM_LRADC_CTRL2_BL_MUX_SELECT
+#define BP_LRADC_CTRL2_BL_BRIGHTNESS                    16
+#define BM_LRADC_CTRL2_BL_BRIGHTNESS                    0x1f0000
+#define BF_LRADC_CTRL2_BL_BRIGHTNESS(v)                 (((v) & 0x1f) << 16)
+#define BFM_LRADC_CTRL2_BL_BRIGHTNESS(v)                BM_LRADC_CTRL2_BL_BRIGHTNESS
+#define BF_LRADC_CTRL2_BL_BRIGHTNESS_V(e)               BF_LRADC_CTRL2_BL_BRIGHTNESS(BV_LRADC_CTRL2_BL_BRIGHTNESS__##e)
+#define BFM_LRADC_CTRL2_BL_BRIGHTNESS_V(v)              BM_LRADC_CTRL2_BL_BRIGHTNESS
+#define BP_LRADC_CTRL2_TEMPSENSE_PWD                    15
+#define BM_LRADC_CTRL2_TEMPSENSE_PWD                    0x8000
+#define BV_LRADC_CTRL2_TEMPSENSE_PWD__DISABLE           0x0
+#define BV_LRADC_CTRL2_TEMPSENSE_PWD__ENABLE            0x1
+#define BF_LRADC_CTRL2_TEMPSENSE_PWD(v)                 (((v) & 0x1) << 15)
+#define BFM_LRADC_CTRL2_TEMPSENSE_PWD(v)                BM_LRADC_CTRL2_TEMPSENSE_PWD
+#define BF_LRADC_CTRL2_TEMPSENSE_PWD_V(e)               BF_LRADC_CTRL2_TEMPSENSE_PWD(BV_LRADC_CTRL2_TEMPSENSE_PWD__##e)
+#define BFM_LRADC_CTRL2_TEMPSENSE_PWD_V(v)              BM_LRADC_CTRL2_TEMPSENSE_PWD
+#define BP_LRADC_CTRL2_EXT_EN1                          13
+#define BM_LRADC_CTRL2_EXT_EN1                          0x2000
+#define BV_LRADC_CTRL2_EXT_EN1__DISABLE                 0x0
+#define BV_LRADC_CTRL2_EXT_EN1__ENABLE                  0x1
+#define BF_LRADC_CTRL2_EXT_EN1(v)                       (((v) & 0x1) << 13)
+#define BFM_LRADC_CTRL2_EXT_EN1(v)                      BM_LRADC_CTRL2_EXT_EN1
+#define BF_LRADC_CTRL2_EXT_EN1_V(e)                     BF_LRADC_CTRL2_EXT_EN1(BV_LRADC_CTRL2_EXT_EN1__##e)
+#define BFM_LRADC_CTRL2_EXT_EN1_V(v)                    BM_LRADC_CTRL2_EXT_EN1
+#define BP_LRADC_CTRL2_EXT_EN0                          12
+#define BM_LRADC_CTRL2_EXT_EN0                          0x1000
+#define BF_LRADC_CTRL2_EXT_EN0(v)                       (((v) & 0x1) << 12)
+#define BFM_LRADC_CTRL2_EXT_EN0(v)                      BM_LRADC_CTRL2_EXT_EN0
+#define BF_LRADC_CTRL2_EXT_EN0_V(e)                     BF_LRADC_CTRL2_EXT_EN0(BV_LRADC_CTRL2_EXT_EN0__##e)
+#define BFM_LRADC_CTRL2_EXT_EN0_V(v)                    BM_LRADC_CTRL2_EXT_EN0
+#define BP_LRADC_CTRL2_TEMP_SENSOR_IENABLE1             9
+#define BM_LRADC_CTRL2_TEMP_SENSOR_IENABLE1             0x200
+#define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE1__DISABLE    0x0
+#define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE1__ENABLE     0x1
+#define BF_LRADC_CTRL2_TEMP_SENSOR_IENABLE1(v)          (((v) & 0x1) << 9)
+#define BFM_LRADC_CTRL2_TEMP_SENSOR_IENABLE1(v)         BM_LRADC_CTRL2_TEMP_SENSOR_IENABLE1
+#define BF_LRADC_CTRL2_TEMP_SENSOR_IENABLE1_V(e)        BF_LRADC_CTRL2_TEMP_SENSOR_IENABLE1(BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE1__##e)
+#define BFM_LRADC_CTRL2_TEMP_SENSOR_IENABLE1_V(v)       BM_LRADC_CTRL2_TEMP_SENSOR_IENABLE1
+#define BP_LRADC_CTRL2_TEMP_SENSOR_IENABLE0             8
+#define BM_LRADC_CTRL2_TEMP_SENSOR_IENABLE0             0x100
+#define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE0__DISABLE    0x0
+#define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE0__ENABLE     0x1
+#define BF_LRADC_CTRL2_TEMP_SENSOR_IENABLE0(v)          (((v) & 0x1) << 8)
+#define BFM_LRADC_CTRL2_TEMP_SENSOR_IENABLE0(v)         BM_LRADC_CTRL2_TEMP_SENSOR_IENABLE0
+#define BF_LRADC_CTRL2_TEMP_SENSOR_IENABLE0_V(e)        BF_LRADC_CTRL2_TEMP_SENSOR_IENABLE0(BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE0__##e)
+#define BFM_LRADC_CTRL2_TEMP_SENSOR_IENABLE0_V(v)       BM_LRADC_CTRL2_TEMP_SENSOR_IENABLE0
+#define BP_LRADC_CTRL2_TEMP_ISRC1                       4
+#define BM_LRADC_CTRL2_TEMP_ISRC1                       0xf0
+#define BV_LRADC_CTRL2_TEMP_ISRC1__300                  0xf
+#define BV_LRADC_CTRL2_TEMP_ISRC1__280                  0xe
+#define BV_LRADC_CTRL2_TEMP_ISRC1__260                  0xd
+#define BV_LRADC_CTRL2_TEMP_ISRC1__240                  0xc
+#define BV_LRADC_CTRL2_TEMP_ISRC1__220                  0xb
+#define BV_LRADC_CTRL2_TEMP_ISRC1__200                  0xa
+#define BV_LRADC_CTRL2_TEMP_ISRC1__180                  0x9
+#define BV_LRADC_CTRL2_TEMP_ISRC1__160                  0x8
+#define BV_LRADC_CTRL2_TEMP_ISRC1__140                  0x7
+#define BV_LRADC_CTRL2_TEMP_ISRC1__120                  0x6
+#define BV_LRADC_CTRL2_TEMP_ISRC1__100                  0x5
+#define BV_LRADC_CTRL2_TEMP_ISRC1__80                   0x4
+#define BV_LRADC_CTRL2_TEMP_ISRC1__60                   0x3
+#define BV_LRADC_CTRL2_TEMP_ISRC1__40                   0x2
+#define BV_LRADC_CTRL2_TEMP_ISRC1__20                   0x1
+#define BV_LRADC_CTRL2_TEMP_ISRC1__ZERO                 0x0
+#define BF_LRADC_CTRL2_TEMP_ISRC1(v)                    (((v) & 0xf) << 4)
+#define BFM_LRADC_CTRL2_TEMP_ISRC1(v)                   BM_LRADC_CTRL2_TEMP_ISRC1
+#define BF_LRADC_CTRL2_TEMP_ISRC1_V(e)                  BF_LRADC_CTRL2_TEMP_ISRC1(BV_LRADC_CTRL2_TEMP_ISRC1__##e)
+#define BFM_LRADC_CTRL2_TEMP_ISRC1_V(v)                 BM_LRADC_CTRL2_TEMP_ISRC1
+#define BP_LRADC_CTRL2_TEMP_ISRC0                       0
+#define BM_LRADC_CTRL2_TEMP_ISRC0                       0xf
+#define BV_LRADC_CTRL2_TEMP_ISRC0__300                  0xf
+#define BV_LRADC_CTRL2_TEMP_ISRC0__280                  0xe
+#define BV_LRADC_CTRL2_TEMP_ISRC0__260                  0xd
+#define BV_LRADC_CTRL2_TEMP_ISRC0__240                  0xc
+#define BV_LRADC_CTRL2_TEMP_ISRC0__220                  0xb
+#define BV_LRADC_CTRL2_TEMP_ISRC0__200                  0xa
+#define BV_LRADC_CTRL2_TEMP_ISRC0__180                  0x9
+#define BV_LRADC_CTRL2_TEMP_ISRC0__160                  0x8
+#define BV_LRADC_CTRL2_TEMP_ISRC0__140                  0x7
+#define BV_LRADC_CTRL2_TEMP_ISRC0__120                  0x6
+#define BV_LRADC_CTRL2_TEMP_ISRC0__100                  0x5
+#define BV_LRADC_CTRL2_TEMP_ISRC0__80                   0x4
+#define BV_LRADC_CTRL2_TEMP_ISRC0__60                   0x3
+#define BV_LRADC_CTRL2_TEMP_ISRC0__40                   0x2
+#define BV_LRADC_CTRL2_TEMP_ISRC0__20                   0x1
+#define BV_LRADC_CTRL2_TEMP_ISRC0__ZERO                 0x0
+#define BF_LRADC_CTRL2_TEMP_ISRC0(v)                    (((v) & 0xf) << 0)
+#define BFM_LRADC_CTRL2_TEMP_ISRC0(v)                   BM_LRADC_CTRL2_TEMP_ISRC0
+#define BF_LRADC_CTRL2_TEMP_ISRC0_V(e)                  BF_LRADC_CTRL2_TEMP_ISRC0(BV_LRADC_CTRL2_TEMP_ISRC0__##e)
+#define BFM_LRADC_CTRL2_TEMP_ISRC0_V(v)                 BM_LRADC_CTRL2_TEMP_ISRC0
+
+#define HW_LRADC_CTRL3                          HW(LRADC_CTRL3)
+#define HWA_LRADC_CTRL3                         (0x80050000 + 0x30)
+#define HWT_LRADC_CTRL3                         HWIO_32_RW
+#define HWN_LRADC_CTRL3                         LRADC_CTRL3
+#define HWI_LRADC_CTRL3                         
+#define HW_LRADC_CTRL3_SET                      HW(LRADC_CTRL3_SET)
+#define HWA_LRADC_CTRL3_SET                     (HWA_LRADC_CTRL3 + 0x4)
+#define HWT_LRADC_CTRL3_SET                     HWIO_32_WO
+#define HWN_LRADC_CTRL3_SET                     LRADC_CTRL3
+#define HWI_LRADC_CTRL3_SET                     
+#define HW_LRADC_CTRL3_CLR                      HW(LRADC_CTRL3_CLR)
+#define HWA_LRADC_CTRL3_CLR                     (HWA_LRADC_CTRL3 + 0x8)
+#define HWT_LRADC_CTRL3_CLR                     HWIO_32_WO
+#define HWN_LRADC_CTRL3_CLR                     LRADC_CTRL3
+#define HWI_LRADC_CTRL3_CLR                     
+#define HW_LRADC_CTRL3_TOG                      HW(LRADC_CTRL3_TOG)
+#define HWA_LRADC_CTRL3_TOG                     (HWA_LRADC_CTRL3 + 0xc)
+#define HWT_LRADC_CTRL3_TOG                     HWIO_32_WO
+#define HWN_LRADC_CTRL3_TOG                     LRADC_CTRL3
+#define HWI_LRADC_CTRL3_TOG                     
+#define BP_LRADC_CTRL3_DISCARD                  24
+#define BM_LRADC_CTRL3_DISCARD                  0x3000000
+#define BV_LRADC_CTRL3_DISCARD__1_SAMPLE        0x1
+#define BV_LRADC_CTRL3_DISCARD__2_SAMPLES       0x2
+#define BV_LRADC_CTRL3_DISCARD__3_SAMPLES       0x3
+#define BF_LRADC_CTRL3_DISCARD(v)               (((v) & 0x3) << 24)
+#define BFM_LRADC_CTRL3_DISCARD(v)              BM_LRADC_CTRL3_DISCARD
+#define BF_LRADC_CTRL3_DISCARD_V(e)             BF_LRADC_CTRL3_DISCARD(BV_LRADC_CTRL3_DISCARD__##e)
+#define BFM_LRADC_CTRL3_DISCARD_V(v)            BM_LRADC_CTRL3_DISCARD
+#define BP_LRADC_CTRL3_FORCE_ANALOG_PWUP        23
+#define BM_LRADC_CTRL3_FORCE_ANALOG_PWUP        0x800000
+#define BV_LRADC_CTRL3_FORCE_ANALOG_PWUP__OFF   0x0
+#define BV_LRADC_CTRL3_FORCE_ANALOG_PWUP__ON    0x1
+#define BF_LRADC_CTRL3_FORCE_ANALOG_PWUP(v)     (((v) & 0x1) << 23)
+#define BFM_LRADC_CTRL3_FORCE_ANALOG_PWUP(v)    BM_LRADC_CTRL3_FORCE_ANALOG_PWUP
+#define BF_LRADC_CTRL3_FORCE_ANALOG_PWUP_V(e)   BF_LRADC_CTRL3_FORCE_ANALOG_PWUP(BV_LRADC_CTRL3_FORCE_ANALOG_PWUP__##e)
+#define BFM_LRADC_CTRL3_FORCE_ANALOG_PWUP_V(v)  BM_LRADC_CTRL3_FORCE_ANALOG_PWUP
+#define BP_LRADC_CTRL3_FORCE_ANALOG_PWDN        22
+#define BM_LRADC_CTRL3_FORCE_ANALOG_PWDN        0x400000
+#define BV_LRADC_CTRL3_FORCE_ANALOG_PWDN__ON    0x0
+#define BV_LRADC_CTRL3_FORCE_ANALOG_PWDN__OFF   0x1
+#define BF_LRADC_CTRL3_FORCE_ANALOG_PWDN(v)     (((v) & 0x1) << 22)
+#define BFM_LRADC_CTRL3_FORCE_ANALOG_PWDN(v)    BM_LRADC_CTRL3_FORCE_ANALOG_PWDN
+#define BF_LRADC_CTRL3_FORCE_ANALOG_PWDN_V(e)   BF_LRADC_CTRL3_FORCE_ANALOG_PWDN(BV_LRADC_CTRL3_FORCE_ANALOG_PWDN__##e)
+#define BFM_LRADC_CTRL3_FORCE_ANALOG_PWDN_V(v)  BM_LRADC_CTRL3_FORCE_ANALOG_PWDN
+#define BP_LRADC_CTRL3_CYCLE_TIME               8
+#define BM_LRADC_CTRL3_CYCLE_TIME               0x300
+#define BV_LRADC_CTRL3_CYCLE_TIME__6MHZ         0x0
+#define BV_LRADC_CTRL3_CYCLE_TIME__4MHZ         0x1
+#define BV_LRADC_CTRL3_CYCLE_TIME__3MHZ         0x2
+#define BV_LRADC_CTRL3_CYCLE_TIME__2MHZ         0x3
+#define BF_LRADC_CTRL3_CYCLE_TIME(v)            (((v) & 0x3) << 8)
+#define BFM_LRADC_CTRL3_CYCLE_TIME(v)           BM_LRADC_CTRL3_CYCLE_TIME
+#define BF_LRADC_CTRL3_CYCLE_TIME_V(e)          BF_LRADC_CTRL3_CYCLE_TIME(BV_LRADC_CTRL3_CYCLE_TIME__##e)
+#define BFM_LRADC_CTRL3_CYCLE_TIME_V(v)         BM_LRADC_CTRL3_CYCLE_TIME
+#define BP_LRADC_CTRL3_HIGH_TIME                4
+#define BM_LRADC_CTRL3_HIGH_TIME                0x30
+#define BV_LRADC_CTRL3_HIGH_TIME__42NS          0x0
+#define BV_LRADC_CTRL3_HIGH_TIME__83NS          0x1
+#define BV_LRADC_CTRL3_HIGH_TIME__125NS         0x2
+#define BV_LRADC_CTRL3_HIGH_TIME__250NS         0x3
+#define BF_LRADC_CTRL3_HIGH_TIME(v)             (((v) & 0x3) << 4)
+#define BFM_LRADC_CTRL3_HIGH_TIME(v)            BM_LRADC_CTRL3_HIGH_TIME
+#define BF_LRADC_CTRL3_HIGH_TIME_V(e)           BF_LRADC_CTRL3_HIGH_TIME(BV_LRADC_CTRL3_HIGH_TIME__##e)
+#define BFM_LRADC_CTRL3_HIGH_TIME_V(v)          BM_LRADC_CTRL3_HIGH_TIME
+#define BP_LRADC_CTRL3_DELAY_CLOCK              1
+#define BM_LRADC_CTRL3_DELAY_CLOCK              0x2
+#define BV_LRADC_CTRL3_DELAY_CLOCK__NORMAL      0x0
+#define BV_LRADC_CTRL3_DELAY_CLOCK__DELAYED     0x1
+#define BF_LRADC_CTRL3_DELAY_CLOCK(v)           (((v) & 0x1) << 1)
+#define BFM_LRADC_CTRL3_DELAY_CLOCK(v)          BM_LRADC_CTRL3_DELAY_CLOCK
+#define BF_LRADC_CTRL3_DELAY_CLOCK_V(e)         BF_LRADC_CTRL3_DELAY_CLOCK(BV_LRADC_CTRL3_DELAY_CLOCK__##e)
+#define BFM_LRADC_CTRL3_DELAY_CLOCK_V(v)        BM_LRADC_CTRL3_DELAY_CLOCK
+#define BP_LRADC_CTRL3_INVERT_CLOCK             0
+#define BM_LRADC_CTRL3_INVERT_CLOCK             0x1
+#define BV_LRADC_CTRL3_INVERT_CLOCK__NORMAL     0x0
+#define BV_LRADC_CTRL3_INVERT_CLOCK__INVERT     0x1
+#define BF_LRADC_CTRL3_INVERT_CLOCK(v)          (((v) & 0x1) << 0)
+#define BFM_LRADC_CTRL3_INVERT_CLOCK(v)         BM_LRADC_CTRL3_INVERT_CLOCK
+#define BF_LRADC_CTRL3_INVERT_CLOCK_V(e)        BF_LRADC_CTRL3_INVERT_CLOCK(BV_LRADC_CTRL3_INVERT_CLOCK__##e)
+#define BFM_LRADC_CTRL3_INVERT_CLOCK_V(v)       BM_LRADC_CTRL3_INVERT_CLOCK
+
+#define HW_LRADC_STATUS                             HW(LRADC_STATUS)
+#define HWA_LRADC_STATUS                            (0x80050000 + 0x40)
+#define HWT_LRADC_STATUS                            HWIO_32_RW
+#define HWN_LRADC_STATUS                            LRADC_STATUS
+#define HWI_LRADC_STATUS                            
+#define BP_LRADC_STATUS_TEMP1_PRESENT               26
+#define BM_LRADC_STATUS_TEMP1_PRESENT               0x4000000
+#define BF_LRADC_STATUS_TEMP1_PRESENT(v)            (((v) & 0x1) << 26)
+#define BFM_LRADC_STATUS_TEMP1_PRESENT(v)           BM_LRADC_STATUS_TEMP1_PRESENT
+#define BF_LRADC_STATUS_TEMP1_PRESENT_V(e)          BF_LRADC_STATUS_TEMP1_PRESENT(BV_LRADC_STATUS_TEMP1_PRESENT__##e)
+#define BFM_LRADC_STATUS_TEMP1_PRESENT_V(v)         BM_LRADC_STATUS_TEMP1_PRESENT
+#define BP_LRADC_STATUS_TEMP0_PRESENT               25
+#define BM_LRADC_STATUS_TEMP0_PRESENT               0x2000000
+#define BF_LRADC_STATUS_TEMP0_PRESENT(v)            (((v) & 0x1) << 25)
+#define BFM_LRADC_STATUS_TEMP0_PRESENT(v)           BM_LRADC_STATUS_TEMP0_PRESENT
+#define BF_LRADC_STATUS_TEMP0_PRESENT_V(e)          BF_LRADC_STATUS_TEMP0_PRESENT(BV_LRADC_STATUS_TEMP0_PRESENT__##e)
+#define BFM_LRADC_STATUS_TEMP0_PRESENT_V(v)         BM_LRADC_STATUS_TEMP0_PRESENT
+#define BP_LRADC_STATUS_TOUCH_PANEL_PRESENT         24
+#define BM_LRADC_STATUS_TOUCH_PANEL_PRESENT         0x1000000
+#define BF_LRADC_STATUS_TOUCH_PANEL_PRESENT(v)      (((v) & 0x1) << 24)
+#define BFM_LRADC_STATUS_TOUCH_PANEL_PRESENT(v)     BM_LRADC_STATUS_TOUCH_PANEL_PRESENT
+#define BF_LRADC_STATUS_TOUCH_PANEL_PRESENT_V(e)    BF_LRADC_STATUS_TOUCH_PANEL_PRESENT(BV_LRADC_STATUS_TOUCH_PANEL_PRESENT__##e)
+#define BFM_LRADC_STATUS_TOUCH_PANEL_PRESENT_V(v)   BM_LRADC_STATUS_TOUCH_PANEL_PRESENT
+#define BP_LRADC_STATUS_CHANNEL7_PRESENT            23
+#define BM_LRADC_STATUS_CHANNEL7_PRESENT            0x800000
+#define BF_LRADC_STATUS_CHANNEL7_PRESENT(v)         (((v) & 0x1) << 23)
+#define BFM_LRADC_STATUS_CHANNEL7_PRESENT(v)        BM_LRADC_STATUS_CHANNEL7_PRESENT
+#define BF_LRADC_STATUS_CHANNEL7_PRESENT_V(e)       BF_LRADC_STATUS_CHANNEL7_PRESENT(BV_LRADC_STATUS_CHANNEL7_PRESENT__##e)
+#define BFM_LRADC_STATUS_CHANNEL7_PRESENT_V(v)      BM_LRADC_STATUS_CHANNEL7_PRESENT
+#define BP_LRADC_STATUS_CHANNEL6_PRESENT            22
+#define BM_LRADC_STATUS_CHANNEL6_PRESENT            0x400000
+#define BF_LRADC_STATUS_CHANNEL6_PRESENT(v)         (((v) & 0x1) << 22)
+#define BFM_LRADC_STATUS_CHANNEL6_PRESENT(v)        BM_LRADC_STATUS_CHANNEL6_PRESENT
+#define BF_LRADC_STATUS_CHANNEL6_PRESENT_V(e)       BF_LRADC_STATUS_CHANNEL6_PRESENT(BV_LRADC_STATUS_CHANNEL6_PRESENT__##e)
+#define BFM_LRADC_STATUS_CHANNEL6_PRESENT_V(v)      BM_LRADC_STATUS_CHANNEL6_PRESENT
+#define BP_LRADC_STATUS_CHANNEL5_PRESENT            21
+#define BM_LRADC_STATUS_CHANNEL5_PRESENT            0x200000
+#define BF_LRADC_STATUS_CHANNEL5_PRESENT(v)         (((v) & 0x1) << 21)
+#define BFM_LRADC_STATUS_CHANNEL5_PRESENT(v)        BM_LRADC_STATUS_CHANNEL5_PRESENT
+#define BF_LRADC_STATUS_CHANNEL5_PRESENT_V(e)       BF_LRADC_STATUS_CHANNEL5_PRESENT(BV_LRADC_STATUS_CHANNEL5_PRESENT__##e)
+#define BFM_LRADC_STATUS_CHANNEL5_PRESENT_V(v)      BM_LRADC_STATUS_CHANNEL5_PRESENT
+#define BP_LRADC_STATUS_CHANNEL4_PRESENT            20
+#define BM_LRADC_STATUS_CHANNEL4_PRESENT            0x100000
+#define BF_LRADC_STATUS_CHANNEL4_PRESENT(v)         (((v) & 0x1) << 20)
+#define BFM_LRADC_STATUS_CHANNEL4_PRESENT(v)        BM_LRADC_STATUS_CHANNEL4_PRESENT
+#define BF_LRADC_STATUS_CHANNEL4_PRESENT_V(e)       BF_LRADC_STATUS_CHANNEL4_PRESENT(BV_LRADC_STATUS_CHANNEL4_PRESENT__##e)
+#define BFM_LRADC_STATUS_CHANNEL4_PRESENT_V(v)      BM_LRADC_STATUS_CHANNEL4_PRESENT
+#define BP_LRADC_STATUS_CHANNEL3_PRESENT            19
+#define BM_LRADC_STATUS_CHANNEL3_PRESENT            0x80000
+#define BF_LRADC_STATUS_CHANNEL3_PRESENT(v)         (((v) & 0x1) << 19)
+#define BFM_LRADC_STATUS_CHANNEL3_PRESENT(v)        BM_LRADC_STATUS_CHANNEL3_PRESENT
+#define BF_LRADC_STATUS_CHANNEL3_PRESENT_V(e)       BF_LRADC_STATUS_CHANNEL3_PRESENT(BV_LRADC_STATUS_CHANNEL3_PRESENT__##e)
+#define BFM_LRADC_STATUS_CHANNEL3_PRESENT_V(v)      BM_LRADC_STATUS_CHANNEL3_PRESENT
+#define BP_LRADC_STATUS_CHANNEL2_PRESENT            18
+#define BM_LRADC_STATUS_CHANNEL2_PRESENT            0x40000
+#define BF_LRADC_STATUS_CHANNEL2_PRESENT(v)         (((v) & 0x1) << 18)
+#define BFM_LRADC_STATUS_CHANNEL2_PRESENT(v)        BM_LRADC_STATUS_CHANNEL2_PRESENT
+#define BF_LRADC_STATUS_CHANNEL2_PRESENT_V(e)       BF_LRADC_STATUS_CHANNEL2_PRESENT(BV_LRADC_STATUS_CHANNEL2_PRESENT__##e)
+#define BFM_LRADC_STATUS_CHANNEL2_PRESENT_V(v)      BM_LRADC_STATUS_CHANNEL2_PRESENT
+#define BP_LRADC_STATUS_CHANNEL1_PRESENT            17
+#define BM_LRADC_STATUS_CHANNEL1_PRESENT            0x20000
+#define BF_LRADC_STATUS_CHANNEL1_PRESENT(v)         (((v) & 0x1) << 17)
+#define BFM_LRADC_STATUS_CHANNEL1_PRESENT(v)        BM_LRADC_STATUS_CHANNEL1_PRESENT
+#define BF_LRADC_STATUS_CHANNEL1_PRESENT_V(e)       BF_LRADC_STATUS_CHANNEL1_PRESENT(BV_LRADC_STATUS_CHANNEL1_PRESENT__##e)
+#define BFM_LRADC_STATUS_CHANNEL1_PRESENT_V(v)      BM_LRADC_STATUS_CHANNEL1_PRESENT
+#define BP_LRADC_STATUS_CHANNEL0_PRESENT            16
+#define BM_LRADC_STATUS_CHANNEL0_PRESENT            0x10000
+#define BF_LRADC_STATUS_CHANNEL0_PRESENT(v)         (((v) & 0x1) << 16)
+#define BFM_LRADC_STATUS_CHANNEL0_PRESENT(v)        BM_LRADC_STATUS_CHANNEL0_PRESENT
+#define BF_LRADC_STATUS_CHANNEL0_PRESENT_V(e)       BF_LRADC_STATUS_CHANNEL0_PRESENT(BV_LRADC_STATUS_CHANNEL0_PRESENT__##e)
+#define BFM_LRADC_STATUS_CHANNEL0_PRESENT_V(v)      BM_LRADC_STATUS_CHANNEL0_PRESENT
+#define BP_LRADC_STATUS_TOUCH_DETECT_RAW            0
+#define BM_LRADC_STATUS_TOUCH_DETECT_RAW            0x1
+#define BV_LRADC_STATUS_TOUCH_DETECT_RAW__OPEN      0x0
+#define BV_LRADC_STATUS_TOUCH_DETECT_RAW__HIT       0x1
+#define BF_LRADC_STATUS_TOUCH_DETECT_RAW(v)         (((v) & 0x1) << 0)
+#define BFM_LRADC_STATUS_TOUCH_DETECT_RAW(v)        BM_LRADC_STATUS_TOUCH_DETECT_RAW
+#define BF_LRADC_STATUS_TOUCH_DETECT_RAW_V(e)       BF_LRADC_STATUS_TOUCH_DETECT_RAW(BV_LRADC_STATUS_TOUCH_DETECT_RAW__##e)
+#define BFM_LRADC_STATUS_TOUCH_DETECT_RAW_V(v)      BM_LRADC_STATUS_TOUCH_DETECT_RAW
+
+#define HW_LRADC_CHn(_n1)               HW(LRADC_CHn(_n1))
+#define HWA_LRADC_CHn(_n1)              (0x80050000 + 0x50 + (_n1) * 0x10)
+#define HWT_LRADC_CHn(_n1)              HWIO_32_RW
+#define HWN_LRADC_CHn(_n1)              LRADC_CHn
+#define HWI_LRADC_CHn(_n1)              (_n1)
+#define HW_LRADC_CHn_SET(_n1)           HW(LRADC_CHn_SET(_n1))
+#define HWA_LRADC_CHn_SET(_n1)          (HWA_LRADC_CHn(_n1) + 0x4)
+#define HWT_LRADC_CHn_SET(_n1)          HWIO_32_WO
+#define HWN_LRADC_CHn_SET(_n1)          LRADC_CHn
+#define HWI_LRADC_CHn_SET(_n1)          (_n1)
+#define HW_LRADC_CHn_CLR(_n1)           HW(LRADC_CHn_CLR(_n1))
+#define HWA_LRADC_CHn_CLR(_n1)          (HWA_LRADC_CHn(_n1) + 0x8)
+#define HWT_LRADC_CHn_CLR(_n1)          HWIO_32_WO
+#define HWN_LRADC_CHn_CLR(_n1)          LRADC_CHn
+#define HWI_LRADC_CHn_CLR(_n1)          (_n1)
+#define HW_LRADC_CHn_TOG(_n1)           HW(LRADC_CHn_TOG(_n1))
+#define HWA_LRADC_CHn_TOG(_n1)          (HWA_LRADC_CHn(_n1) + 0xc)
+#define HWT_LRADC_CHn_TOG(_n1)          HWIO_32_WO
+#define HWN_LRADC_CHn_TOG(_n1)          LRADC_CHn
+#define HWI_LRADC_CHn_TOG(_n1)          (_n1)
+#define BP_LRADC_CHn_TOGGLE             31
+#define BM_LRADC_CHn_TOGGLE             0x80000000
+#define BF_LRADC_CHn_TOGGLE(v)          (((v) & 0x1) << 31)
+#define BFM_LRADC_CHn_TOGGLE(v)         BM_LRADC_CHn_TOGGLE
+#define BF_LRADC_CHn_TOGGLE_V(e)        BF_LRADC_CHn_TOGGLE(BV_LRADC_CHn_TOGGLE__##e)
+#define BFM_LRADC_CHn_TOGGLE_V(v)       BM_LRADC_CHn_TOGGLE
+#define BP_LRADC_CHn_ACCUMULATE         29
+#define BM_LRADC_CHn_ACCUMULATE         0x20000000
+#define BF_LRADC_CHn_ACCUMULATE(v)      (((v) & 0x1) << 29)
+#define BFM_LRADC_CHn_ACCUMULATE(v)     BM_LRADC_CHn_ACCUMULATE
+#define BF_LRADC_CHn_ACCUMULATE_V(e)    BF_LRADC_CHn_ACCUMULATE(BV_LRADC_CHn_ACCUMULATE__##e)
+#define BFM_LRADC_CHn_ACCUMULATE_V(v)   BM_LRADC_CHn_ACCUMULATE
+#define BP_LRADC_CHn_NUM_SAMPLES        24
+#define BM_LRADC_CHn_NUM_SAMPLES        0x1f000000
+#define BF_LRADC_CHn_NUM_SAMPLES(v)     (((v) & 0x1f) << 24)
+#define BFM_LRADC_CHn_NUM_SAMPLES(v)    BM_LRADC_CHn_NUM_SAMPLES
+#define BF_LRADC_CHn_NUM_SAMPLES_V(e)   BF_LRADC_CHn_NUM_SAMPLES(BV_LRADC_CHn_NUM_SAMPLES__##e)
+#define BFM_LRADC_CHn_NUM_SAMPLES_V(v)  BM_LRADC_CHn_NUM_SAMPLES
+#define BP_LRADC_CHn_VALUE              0
+#define BM_LRADC_CHn_VALUE              0x3ffff
+#define BF_LRADC_CHn_VALUE(v)           (((v) & 0x3ffff) << 0)
+#define BFM_LRADC_CHn_VALUE(v)          BM_LRADC_CHn_VALUE
+#define BF_LRADC_CHn_VALUE_V(e)         BF_LRADC_CHn_VALUE(BV_LRADC_CHn_VALUE__##e)
+#define BFM_LRADC_CHn_VALUE_V(v)        BM_LRADC_CHn_VALUE
+
+#define HW_LRADC_DELAYn(_n1)                    HW(LRADC_DELAYn(_n1))
+#define HWA_LRADC_DELAYn(_n1)                   (0x80050000 + 0xd0 + (_n1) * 0x10)
+#define HWT_LRADC_DELAYn(_n1)                   HWIO_32_RW
+#define HWN_LRADC_DELAYn(_n1)                   LRADC_DELAYn
+#define HWI_LRADC_DELAYn(_n1)                   (_n1)
+#define HW_LRADC_DELAYn_SET(_n1)                HW(LRADC_DELAYn_SET(_n1))
+#define HWA_LRADC_DELAYn_SET(_n1)               (HWA_LRADC_DELAYn(_n1) + 0x4)
+#define HWT_LRADC_DELAYn_SET(_n1)               HWIO_32_WO
+#define HWN_LRADC_DELAYn_SET(_n1)               LRADC_DELAYn
+#define HWI_LRADC_DELAYn_SET(_n1)               (_n1)
+#define HW_LRADC_DELAYn_CLR(_n1)                HW(LRADC_DELAYn_CLR(_n1))
+#define HWA_LRADC_DELAYn_CLR(_n1)               (HWA_LRADC_DELAYn(_n1) + 0x8)
+#define HWT_LRADC_DELAYn_CLR(_n1)               HWIO_32_WO
+#define HWN_LRADC_DELAYn_CLR(_n1)               LRADC_DELAYn
+#define HWI_LRADC_DELAYn_CLR(_n1)               (_n1)
+#define HW_LRADC_DELAYn_TOG(_n1)                HW(LRADC_DELAYn_TOG(_n1))
+#define HWA_LRADC_DELAYn_TOG(_n1)               (HWA_LRADC_DELAYn(_n1) + 0xc)
+#define HWT_LRADC_DELAYn_TOG(_n1)               HWIO_32_WO
+#define HWN_LRADC_DELAYn_TOG(_n1)               LRADC_DELAYn
+#define HWI_LRADC_DELAYn_TOG(_n1)               (_n1)
+#define BP_LRADC_DELAYn_TRIGGER_LRADCS          24
+#define BM_LRADC_DELAYn_TRIGGER_LRADCS          0xff000000
+#define BF_LRADC_DELAYn_TRIGGER_LRADCS(v)       (((v) & 0xff) << 24)
+#define BFM_LRADC_DELAYn_TRIGGER_LRADCS(v)      BM_LRADC_DELAYn_TRIGGER_LRADCS
+#define BF_LRADC_DELAYn_TRIGGER_LRADCS_V(e)     BF_LRADC_DELAYn_TRIGGER_LRADCS(BV_LRADC_DELAYn_TRIGGER_LRADCS__##e)
+#define BFM_LRADC_DELAYn_TRIGGER_LRADCS_V(v)    BM_LRADC_DELAYn_TRIGGER_LRADCS
+#define BP_LRADC_DELAYn_KICK                    20
+#define BM_LRADC_DELAYn_KICK                    0x100000
+#define BF_LRADC_DELAYn_KICK(v)                 (((v) & 0x1) << 20)
+#define BFM_LRADC_DELAYn_KICK(v)                BM_LRADC_DELAYn_KICK
+#define BF_LRADC_DELAYn_KICK_V(e)               BF_LRADC_DELAYn_KICK(BV_LRADC_DELAYn_KICK__##e)
+#define BFM_LRADC_DELAYn_KICK_V(v)              BM_LRADC_DELAYn_KICK
+#define BP_LRADC_DELAYn_TRIGGER_DELAYS          16
+#define BM_LRADC_DELAYn_TRIGGER_DELAYS          0xf0000
+#define BF_LRADC_DELAYn_TRIGGER_DELAYS(v)       (((v) & 0xf) << 16)
+#define BFM_LRADC_DELAYn_TRIGGER_DELAYS(v)      BM_LRADC_DELAYn_TRIGGER_DELAYS
+#define BF_LRADC_DELAYn_TRIGGER_DELAYS_V(e)     BF_LRADC_DELAYn_TRIGGER_DELAYS(BV_LRADC_DELAYn_TRIGGER_DELAYS__##e)
+#define BFM_LRADC_DELAYn_TRIGGER_DELAYS_V(v)    BM_LRADC_DELAYn_TRIGGER_DELAYS
+#define BP_LRADC_DELAYn_LOOP_COUNT              11
+#define BM_LRADC_DELAYn_LOOP_COUNT              0xf800
+#define BF_LRADC_DELAYn_LOOP_COUNT(v)           (((v) & 0x1f) << 11)
+#define BFM_LRADC_DELAYn_LOOP_COUNT(v)          BM_LRADC_DELAYn_LOOP_COUNT
+#define BF_LRADC_DELAYn_LOOP_COUNT_V(e)         BF_LRADC_DELAYn_LOOP_COUNT(BV_LRADC_DELAYn_LOOP_COUNT__##e)
+#define BFM_LRADC_DELAYn_LOOP_COUNT_V(v)        BM_LRADC_DELAYn_LOOP_COUNT
+#define BP_LRADC_DELAYn_DELAY                   0
+#define BM_LRADC_DELAYn_DELAY                   0x7ff
+#define BF_LRADC_DELAYn_DELAY(v)                (((v) & 0x7ff) << 0)
+#define BFM_LRADC_DELAYn_DELAY(v)               BM_LRADC_DELAYn_DELAY
+#define BF_LRADC_DELAYn_DELAY_V(e)              BF_LRADC_DELAYn_DELAY(BV_LRADC_DELAYn_DELAY__##e)
+#define BFM_LRADC_DELAYn_DELAY_V(v)             BM_LRADC_DELAYn_DELAY
+
+#define HW_LRADC_DEBUG0                 HW(LRADC_DEBUG0)
+#define HWA_LRADC_DEBUG0                (0x80050000 + 0x110)
+#define HWT_LRADC_DEBUG0                HWIO_32_RW
+#define HWN_LRADC_DEBUG0                LRADC_DEBUG0
+#define HWI_LRADC_DEBUG0                
+#define BP_LRADC_DEBUG0_READONLY        16
+#define BM_LRADC_DEBUG0_READONLY        0xffff0000
+#define BF_LRADC_DEBUG0_READONLY(v)     (((v) & 0xffff) << 16)
+#define BFM_LRADC_DEBUG0_READONLY(v)    BM_LRADC_DEBUG0_READONLY
+#define BF_LRADC_DEBUG0_READONLY_V(e)   BF_LRADC_DEBUG0_READONLY(BV_LRADC_DEBUG0_READONLY__##e)
+#define BFM_LRADC_DEBUG0_READONLY_V(v)  BM_LRADC_DEBUG0_READONLY
+#define BP_LRADC_DEBUG0_STATE           0
+#define BM_LRADC_DEBUG0_STATE           0xfff
+#define BF_LRADC_DEBUG0_STATE(v)        (((v) & 0xfff) << 0)
+#define BFM_LRADC_DEBUG0_STATE(v)       BM_LRADC_DEBUG0_STATE
+#define BF_LRADC_DEBUG0_STATE_V(e)      BF_LRADC_DEBUG0_STATE(BV_LRADC_DEBUG0_STATE__##e)
+#define BFM_LRADC_DEBUG0_STATE_V(v)     BM_LRADC_DEBUG0_STATE
+
+#define HW_LRADC_DEBUG1                         HW(LRADC_DEBUG1)
+#define HWA_LRADC_DEBUG1                        (0x80050000 + 0x120)
+#define HWT_LRADC_DEBUG1                        HWIO_32_RW
+#define HWN_LRADC_DEBUG1                        LRADC_DEBUG1
+#define HWI_LRADC_DEBUG1                        
+#define HW_LRADC_DEBUG1_SET                     HW(LRADC_DEBUG1_SET)
+#define HWA_LRADC_DEBUG1_SET                    (HWA_LRADC_DEBUG1 + 0x4)
+#define HWT_LRADC_DEBUG1_SET                    HWIO_32_WO
+#define HWN_LRADC_DEBUG1_SET                    LRADC_DEBUG1
+#define HWI_LRADC_DEBUG1_SET                    
+#define HW_LRADC_DEBUG1_CLR                     HW(LRADC_DEBUG1_CLR)
+#define HWA_LRADC_DEBUG1_CLR                    (HWA_LRADC_DEBUG1 + 0x8)
+#define HWT_LRADC_DEBUG1_CLR                    HWIO_32_WO
+#define HWN_LRADC_DEBUG1_CLR                    LRADC_DEBUG1
+#define HWI_LRADC_DEBUG1_CLR                    
+#define HW_LRADC_DEBUG1_TOG                     HW(LRADC_DEBUG1_TOG)
+#define HWA_LRADC_DEBUG1_TOG                    (HWA_LRADC_DEBUG1 + 0xc)
+#define HWT_LRADC_DEBUG1_TOG                    HWIO_32_WO
+#define HWN_LRADC_DEBUG1_TOG                    LRADC_DEBUG1
+#define HWI_LRADC_DEBUG1_TOG                    
+#define BP_LRADC_DEBUG1_REQUEST                 16
+#define BM_LRADC_DEBUG1_REQUEST                 0xff0000
+#define BF_LRADC_DEBUG1_REQUEST(v)              (((v) & 0xff) << 16)
+#define BFM_LRADC_DEBUG1_REQUEST(v)             BM_LRADC_DEBUG1_REQUEST
+#define BF_LRADC_DEBUG1_REQUEST_V(e)            BF_LRADC_DEBUG1_REQUEST(BV_LRADC_DEBUG1_REQUEST__##e)
+#define BFM_LRADC_DEBUG1_REQUEST_V(v)           BM_LRADC_DEBUG1_REQUEST
+#define BP_LRADC_DEBUG1_TESTMODE_COUNT          8
+#define BM_LRADC_DEBUG1_TESTMODE_COUNT          0x1f00
+#define BF_LRADC_DEBUG1_TESTMODE_COUNT(v)       (((v) & 0x1f) << 8)
+#define BFM_LRADC_DEBUG1_TESTMODE_COUNT(v)      BM_LRADC_DEBUG1_TESTMODE_COUNT
+#define BF_LRADC_DEBUG1_TESTMODE_COUNT_V(e)     BF_LRADC_DEBUG1_TESTMODE_COUNT(BV_LRADC_DEBUG1_TESTMODE_COUNT__##e)
+#define BFM_LRADC_DEBUG1_TESTMODE_COUNT_V(v)    BM_LRADC_DEBUG1_TESTMODE_COUNT
+#define BP_LRADC_DEBUG1_TESTMODE6               2
+#define BM_LRADC_DEBUG1_TESTMODE6               0x4
+#define BV_LRADC_DEBUG1_TESTMODE6__NORMAL       0x0
+#define BV_LRADC_DEBUG1_TESTMODE6__TEST         0x1
+#define BF_LRADC_DEBUG1_TESTMODE6(v)            (((v) & 0x1) << 2)
+#define BFM_LRADC_DEBUG1_TESTMODE6(v)           BM_LRADC_DEBUG1_TESTMODE6
+#define BF_LRADC_DEBUG1_TESTMODE6_V(e)          BF_LRADC_DEBUG1_TESTMODE6(BV_LRADC_DEBUG1_TESTMODE6__##e)
+#define BFM_LRADC_DEBUG1_TESTMODE6_V(v)         BM_LRADC_DEBUG1_TESTMODE6
+#define BP_LRADC_DEBUG1_TESTMODE5               1
+#define BM_LRADC_DEBUG1_TESTMODE5               0x2
+#define BV_LRADC_DEBUG1_TESTMODE5__NORMAL       0x0
+#define BV_LRADC_DEBUG1_TESTMODE5__TEST         0x1
+#define BF_LRADC_DEBUG1_TESTMODE5(v)            (((v) & 0x1) << 1)
+#define BFM_LRADC_DEBUG1_TESTMODE5(v)           BM_LRADC_DEBUG1_TESTMODE5
+#define BF_LRADC_DEBUG1_TESTMODE5_V(e)          BF_LRADC_DEBUG1_TESTMODE5(BV_LRADC_DEBUG1_TESTMODE5__##e)
+#define BFM_LRADC_DEBUG1_TESTMODE5_V(v)         BM_LRADC_DEBUG1_TESTMODE5
+#define BP_LRADC_DEBUG1_TESTMODE                0
+#define BM_LRADC_DEBUG1_TESTMODE                0x1
+#define BV_LRADC_DEBUG1_TESTMODE__NORMAL        0x0
+#define BV_LRADC_DEBUG1_TESTMODE__TEST          0x1
+#define BF_LRADC_DEBUG1_TESTMODE(v)             (((v) & 0x1) << 0)
+#define BFM_LRADC_DEBUG1_TESTMODE(v)            BM_LRADC_DEBUG1_TESTMODE
+#define BF_LRADC_DEBUG1_TESTMODE_V(e)           BF_LRADC_DEBUG1_TESTMODE(BV_LRADC_DEBUG1_TESTMODE__##e)
+#define BFM_LRADC_DEBUG1_TESTMODE_V(v)          BM_LRADC_DEBUG1_TESTMODE
+
+#define HW_LRADC_CONVERSION                             HW(LRADC_CONVERSION)
+#define HWA_LRADC_CONVERSION                            (0x80050000 + 0x130)
+#define HWT_LRADC_CONVERSION                            HWIO_32_RW
+#define HWN_LRADC_CONVERSION                            LRADC_CONVERSION
+#define HWI_LRADC_CONVERSION                            
+#define HW_LRADC_CONVERSION_SET                         HW(LRADC_CONVERSION_SET)
+#define HWA_LRADC_CONVERSION_SET                        (HWA_LRADC_CONVERSION + 0x4)
+#define HWT_LRADC_CONVERSION_SET                        HWIO_32_WO
+#define HWN_LRADC_CONVERSION_SET                        LRADC_CONVERSION
+#define HWI_LRADC_CONVERSION_SET                        
+#define HW_LRADC_CONVERSION_CLR                         HW(LRADC_CONVERSION_CLR)
+#define HWA_LRADC_CONVERSION_CLR                        (HWA_LRADC_CONVERSION + 0x8)
+#define HWT_LRADC_CONVERSION_CLR                        HWIO_32_WO
+#define HWN_LRADC_CONVERSION_CLR                        LRADC_CONVERSION
+#define HWI_LRADC_CONVERSION_CLR                        
+#define HW_LRADC_CONVERSION_TOG                         HW(LRADC_CONVERSION_TOG)
+#define HWA_LRADC_CONVERSION_TOG                        (HWA_LRADC_CONVERSION + 0xc)
+#define HWT_LRADC_CONVERSION_TOG                        HWIO_32_WO
+#define HWN_LRADC_CONVERSION_TOG                        LRADC_CONVERSION
+#define HWI_LRADC_CONVERSION_TOG                        
+#define BP_LRADC_CONVERSION_AUTOMATIC                   20
+#define BM_LRADC_CONVERSION_AUTOMATIC                   0x100000
+#define BV_LRADC_CONVERSION_AUTOMATIC__DISABLE          0x0
+#define BV_LRADC_CONVERSION_AUTOMATIC__ENABLE           0x1
+#define BF_LRADC_CONVERSION_AUTOMATIC(v)                (((v) & 0x1) << 20)
+#define BFM_LRADC_CONVERSION_AUTOMATIC(v)               BM_LRADC_CONVERSION_AUTOMATIC
+#define BF_LRADC_CONVERSION_AUTOMATIC_V(e)              BF_LRADC_CONVERSION_AUTOMATIC(BV_LRADC_CONVERSION_AUTOMATIC__##e)
+#define BFM_LRADC_CONVERSION_AUTOMATIC_V(v)             BM_LRADC_CONVERSION_AUTOMATIC
+#define BP_LRADC_CONVERSION_SCALE_FACTOR                16
+#define BM_LRADC_CONVERSION_SCALE_FACTOR                0x30000
+#define BV_LRADC_CONVERSION_SCALE_FACTOR__NIMH          0x0
+#define BV_LRADC_CONVERSION_SCALE_FACTOR__DUAL_NIMH     0x1
+#define BV_LRADC_CONVERSION_SCALE_FACTOR__LI_ION        0x2
+#define BV_LRADC_CONVERSION_SCALE_FACTOR__ALT_LI_ION    0x3
+#define BF_LRADC_CONVERSION_SCALE_FACTOR(v)             (((v) & 0x3) << 16)
+#define BFM_LRADC_CONVERSION_SCALE_FACTOR(v)            BM_LRADC_CONVERSION_SCALE_FACTOR
+#define BF_LRADC_CONVERSION_SCALE_FACTOR_V(e)           BF_LRADC_CONVERSION_SCALE_FACTOR(BV_LRADC_CONVERSION_SCALE_FACTOR__##e)
+#define BFM_LRADC_CONVERSION_SCALE_FACTOR_V(v)          BM_LRADC_CONVERSION_SCALE_FACTOR
+#define BP_LRADC_CONVERSION_SCALED_BATT_VOLTAGE         0
+#define BM_LRADC_CONVERSION_SCALED_BATT_VOLTAGE         0x3ff
+#define BF_LRADC_CONVERSION_SCALED_BATT_VOLTAGE(v)      (((v) & 0x3ff) << 0)
+#define BFM_LRADC_CONVERSION_SCALED_BATT_VOLTAGE(v)     BM_LRADC_CONVERSION_SCALED_BATT_VOLTAGE
+#define BF_LRADC_CONVERSION_SCALED_BATT_VOLTAGE_V(e)    BF_LRADC_CONVERSION_SCALED_BATT_VOLTAGE(BV_LRADC_CONVERSION_SCALED_BATT_VOLTAGE__##e)
+#define BFM_LRADC_CONVERSION_SCALED_BATT_VOLTAGE_V(v)   BM_LRADC_CONVERSION_SCALED_BATT_VOLTAGE
+
+#define HW_LRADC_CTRL4                          HW(LRADC_CTRL4)
+#define HWA_LRADC_CTRL4                         (0x80050000 + 0x140)
+#define HWT_LRADC_CTRL4                         HWIO_32_RW
+#define HWN_LRADC_CTRL4                         LRADC_CTRL4
+#define HWI_LRADC_CTRL4                         
+#define HW_LRADC_CTRL4_SET                      HW(LRADC_CTRL4_SET)
+#define HWA_LRADC_CTRL4_SET                     (HWA_LRADC_CTRL4 + 0x4)
+#define HWT_LRADC_CTRL4_SET                     HWIO_32_WO
+#define HWN_LRADC_CTRL4_SET                     LRADC_CTRL4
+#define HWI_LRADC_CTRL4_SET                     
+#define HW_LRADC_CTRL4_CLR                      HW(LRADC_CTRL4_CLR)
+#define HWA_LRADC_CTRL4_CLR                     (HWA_LRADC_CTRL4 + 0x8)
+#define HWT_LRADC_CTRL4_CLR                     HWIO_32_WO
+#define HWN_LRADC_CTRL4_CLR                     LRADC_CTRL4
+#define HWI_LRADC_CTRL4_CLR                     
+#define HW_LRADC_CTRL4_TOG                      HW(LRADC_CTRL4_TOG)
+#define HWA_LRADC_CTRL4_TOG                     (HWA_LRADC_CTRL4 + 0xc)
+#define HWT_LRADC_CTRL4_TOG                     HWIO_32_WO
+#define HWN_LRADC_CTRL4_TOG                     LRADC_CTRL4
+#define HWI_LRADC_CTRL4_TOG                     
+#define BP_LRADC_CTRL4_LRADC7SELECT             28
+#define BM_LRADC_CTRL4_LRADC7SELECT             0xf0000000
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL0   0x0
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL1   0x1
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL2   0x2
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL3   0x3
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL4   0x4
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL5   0x5
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL6   0x6
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL7   0x7
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL8   0x8
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL9   0x9
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL10  0xa
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL11  0xb
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL12  0xc
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL13  0xd
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL14  0xe
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL15  0xf
+#define BF_LRADC_CTRL4_LRADC7SELECT(v)          (((v) & 0xf) << 28)
+#define BFM_LRADC_CTRL4_LRADC7SELECT(v)         BM_LRADC_CTRL4_LRADC7SELECT
+#define BF_LRADC_CTRL4_LRADC7SELECT_V(e)        BF_LRADC_CTRL4_LRADC7SELECT(BV_LRADC_CTRL4_LRADC7SELECT__##e)
+#define BFM_LRADC_CTRL4_LRADC7SELECT_V(v)       BM_LRADC_CTRL4_LRADC7SELECT
+#define BP_LRADC_CTRL4_LRADC6SELECT             24
+#define BM_LRADC_CTRL4_LRADC6SELECT             0xf000000
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL0   0x0
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL1   0x1
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL2   0x2
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL3   0x3
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL4   0x4
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL5   0x5
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL6   0x6
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL7   0x7
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL8   0x8
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL9   0x9
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL10  0xa
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL11  0xb
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL12  0xc
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL13  0xd
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL14  0xe
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL15  0xf
+#define BF_LRADC_CTRL4_LRADC6SELECT(v)          (((v) & 0xf) << 24)
+#define BFM_LRADC_CTRL4_LRADC6SELECT(v)         BM_LRADC_CTRL4_LRADC6SELECT
+#define BF_LRADC_CTRL4_LRADC6SELECT_V(e)        BF_LRADC_CTRL4_LRADC6SELECT(BV_LRADC_CTRL4_LRADC6SELECT__##e)
+#define BFM_LRADC_CTRL4_LRADC6SELECT_V(v)       BM_LRADC_CTRL4_LRADC6SELECT
+#define BP_LRADC_CTRL4_LRADC5SELECT             20
+#define BM_LRADC_CTRL4_LRADC5SELECT             0xf00000
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL0   0x0
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL1   0x1
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL2   0x2
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL3   0x3
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL4   0x4
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL5   0x5
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL6   0x6
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL7   0x7
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL8   0x8
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL9   0x9
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL10  0xa
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL11  0xb
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL12  0xc
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL13  0xd
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL14  0xe
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL15  0xf
+#define BF_LRADC_CTRL4_LRADC5SELECT(v)          (((v) & 0xf) << 20)
+#define BFM_LRADC_CTRL4_LRADC5SELECT(v)         BM_LRADC_CTRL4_LRADC5SELECT
+#define BF_LRADC_CTRL4_LRADC5SELECT_V(e)        BF_LRADC_CTRL4_LRADC5SELECT(BV_LRADC_CTRL4_LRADC5SELECT__##e)
+#define BFM_LRADC_CTRL4_LRADC5SELECT_V(v)       BM_LRADC_CTRL4_LRADC5SELECT
+#define BP_LRADC_CTRL4_LRADC4SELECT             16
+#define BM_LRADC_CTRL4_LRADC4SELECT             0xf0000
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL0   0x0
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL1   0x1
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL2   0x2
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL3   0x3
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL4   0x4
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL5   0x5
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL6   0x6
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL7   0x7
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL8   0x8
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL9   0x9
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL10  0xa
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL11  0xb
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL12  0xc
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL13  0xd
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL14  0xe
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL15  0xf
+#define BF_LRADC_CTRL4_LRADC4SELECT(v)          (((v) & 0xf) << 16)
+#define BFM_LRADC_CTRL4_LRADC4SELECT(v)         BM_LRADC_CTRL4_LRADC4SELECT
+#define BF_LRADC_CTRL4_LRADC4SELECT_V(e)        BF_LRADC_CTRL4_LRADC4SELECT(BV_LRADC_CTRL4_LRADC4SELECT__##e)
+#define BFM_LRADC_CTRL4_LRADC4SELECT_V(v)       BM_LRADC_CTRL4_LRADC4SELECT
+#define BP_LRADC_CTRL4_LRADC3SELECT             12
+#define BM_LRADC_CTRL4_LRADC3SELECT             0xf000
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL0   0x0
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL1   0x1
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL2   0x2
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL3   0x3
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL4   0x4
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL5   0x5
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL6   0x6
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL7   0x7
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL8   0x8
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL9   0x9
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL10  0xa
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL11  0xb
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL12  0xc
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL13  0xd
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL14  0xe
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL15  0xf
+#define BF_LRADC_CTRL4_LRADC3SELECT(v)          (((v) & 0xf) << 12)
+#define BFM_LRADC_CTRL4_LRADC3SELECT(v)         BM_LRADC_CTRL4_LRADC3SELECT
+#define BF_LRADC_CTRL4_LRADC3SELECT_V(e)        BF_LRADC_CTRL4_LRADC3SELECT(BV_LRADC_CTRL4_LRADC3SELECT__##e)
+#define BFM_LRADC_CTRL4_LRADC3SELECT_V(v)       BM_LRADC_CTRL4_LRADC3SELECT
+#define BP_LRADC_CTRL4_LRADC2SELECT             8
+#define BM_LRADC_CTRL4_LRADC2SELECT             0xf00
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL0   0x0
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL1   0x1
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL2   0x2
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL3   0x3
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL4   0x4
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL5   0x5
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL6   0x6
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL7   0x7
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL8   0x8
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL9   0x9
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL10  0xa
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL11  0xb
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL12  0xc
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL13  0xd
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL14  0xe
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL15  0xf
+#define BF_LRADC_CTRL4_LRADC2SELECT(v)          (((v) & 0xf) << 8)
+#define BFM_LRADC_CTRL4_LRADC2SELECT(v)         BM_LRADC_CTRL4_LRADC2SELECT
+#define BF_LRADC_CTRL4_LRADC2SELECT_V(e)        BF_LRADC_CTRL4_LRADC2SELECT(BV_LRADC_CTRL4_LRADC2SELECT__##e)
+#define BFM_LRADC_CTRL4_LRADC2SELECT_V(v)       BM_LRADC_CTRL4_LRADC2SELECT
+#define BP_LRADC_CTRL4_LRADC1SELECT             4
+#define BM_LRADC_CTRL4_LRADC1SELECT             0xf0
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL0   0x0
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL1   0x1
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL2   0x2
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL3   0x3
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL4   0x4
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL5   0x5
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL6   0x6
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL7   0x7
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL8   0x8
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL9   0x9
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL10  0xa
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL11  0xb
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL12  0xc
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL13  0xd
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL14  0xe
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL15  0xf
+#define BF_LRADC_CTRL4_LRADC1SELECT(v)          (((v) & 0xf) << 4)
+#define BFM_LRADC_CTRL4_LRADC1SELECT(v)         BM_LRADC_CTRL4_LRADC1SELECT
+#define BF_LRADC_CTRL4_LRADC1SELECT_V(e)        BF_LRADC_CTRL4_LRADC1SELECT(BV_LRADC_CTRL4_LRADC1SELECT__##e)
+#define BFM_LRADC_CTRL4_LRADC1SELECT_V(v)       BM_LRADC_CTRL4_LRADC1SELECT
+#define BP_LRADC_CTRL4_LRADC0SELECT             0
+#define BM_LRADC_CTRL4_LRADC0SELECT             0xf
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL0   0x0
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL1   0x1
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL2   0x2
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL3   0x3
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL4   0x4
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL5   0x5
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL6   0x6
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL7   0x7
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL8   0x8
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL9   0x9
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL10  0xa
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL11  0xb
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL12  0xc
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL13  0xd
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL14  0xe
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL15  0xf
+#define BF_LRADC_CTRL4_LRADC0SELECT(v)          (((v) & 0xf) << 0)
+#define BFM_LRADC_CTRL4_LRADC0SELECT(v)         BM_LRADC_CTRL4_LRADC0SELECT
+#define BF_LRADC_CTRL4_LRADC0SELECT_V(e)        BF_LRADC_CTRL4_LRADC0SELECT(BV_LRADC_CTRL4_LRADC0SELECT__##e)
+#define BFM_LRADC_CTRL4_LRADC0SELECT_V(v)       BM_LRADC_CTRL4_LRADC0SELECT
+
+#define HW_LRADC_VERSION                HW(LRADC_VERSION)
+#define HWA_LRADC_VERSION               (0x80050000 + 0x150)
+#define HWT_LRADC_VERSION               HWIO_32_RW
+#define HWN_LRADC_VERSION               LRADC_VERSION
+#define HWI_LRADC_VERSION               
+#define BP_LRADC_VERSION_MAJOR          24
+#define BM_LRADC_VERSION_MAJOR          0xff000000
+#define BF_LRADC_VERSION_MAJOR(v)       (((v) & 0xff) << 24)
+#define BFM_LRADC_VERSION_MAJOR(v)      BM_LRADC_VERSION_MAJOR
+#define BF_LRADC_VERSION_MAJOR_V(e)     BF_LRADC_VERSION_MAJOR(BV_LRADC_VERSION_MAJOR__##e)
+#define BFM_LRADC_VERSION_MAJOR_V(v)    BM_LRADC_VERSION_MAJOR
+#define BP_LRADC_VERSION_MINOR          16
+#define BM_LRADC_VERSION_MINOR          0xff0000
+#define BF_LRADC_VERSION_MINOR(v)       (((v) & 0xff) << 16)
+#define BFM_LRADC_VERSION_MINOR(v)      BM_LRADC_VERSION_MINOR
+#define BF_LRADC_VERSION_MINOR_V(e)     BF_LRADC_VERSION_MINOR(BV_LRADC_VERSION_MINOR__##e)
+#define BFM_LRADC_VERSION_MINOR_V(v)    BM_LRADC_VERSION_MINOR
+#define BP_LRADC_VERSION_STEP           0
+#define BM_LRADC_VERSION_STEP           0xffff
+#define BF_LRADC_VERSION_STEP(v)        (((v) & 0xffff) << 0)
+#define BFM_LRADC_VERSION_STEP(v)       BM_LRADC_VERSION_STEP
+#define BF_LRADC_VERSION_STEP_V(e)      BF_LRADC_VERSION_STEP(BV_LRADC_VERSION_STEP__##e)
+#define BFM_LRADC_VERSION_STEP_V(v)     BM_LRADC_VERSION_STEP
+
+#endif /* __HEADERGEN_STMP3700_LRADC_H__*/
diff --git a/firmware/target/arm/imx233/regs/stmp3700/ocotp.h b/firmware/target/arm/imx233/regs/stmp3700/ocotp.h
new file mode 100644
index 0000000000..ce2decd4b9
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3700/ocotp.h
@@ -0,0 +1,385 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * stmp3700 version: 2.4.0
+ * stmp3700 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_STMP3700_OCOTP_H__
+#define __HEADERGEN_STMP3700_OCOTP_H__
+
+#define HW_OCOTP_CTRL                       HW(OCOTP_CTRL)
+#define HWA_OCOTP_CTRL                      (0x8002c000 + 0x0)
+#define HWT_OCOTP_CTRL                      HWIO_32_RW
+#define HWN_OCOTP_CTRL                      OCOTP_CTRL
+#define HWI_OCOTP_CTRL                      
+#define HW_OCOTP_CTRL_SET                   HW(OCOTP_CTRL_SET)
+#define HWA_OCOTP_CTRL_SET                  (HWA_OCOTP_CTRL + 0x4)
+#define HWT_OCOTP_CTRL_SET                  HWIO_32_WO
+#define HWN_OCOTP_CTRL_SET                  OCOTP_CTRL
+#define HWI_OCOTP_CTRL_SET                  
+#define HW_OCOTP_CTRL_CLR                   HW(OCOTP_CTRL_CLR)
+#define HWA_OCOTP_CTRL_CLR                  (HWA_OCOTP_CTRL + 0x8)
+#define HWT_OCOTP_CTRL_CLR                  HWIO_32_WO
+#define HWN_OCOTP_CTRL_CLR                  OCOTP_CTRL
+#define HWI_OCOTP_CTRL_CLR                  
+#define HW_OCOTP_CTRL_TOG                   HW(OCOTP_CTRL_TOG)
+#define HWA_OCOTP_CTRL_TOG                  (HWA_OCOTP_CTRL + 0xc)
+#define HWT_OCOTP_CTRL_TOG                  HWIO_32_WO
+#define HWN_OCOTP_CTRL_TOG                  OCOTP_CTRL
+#define HWI_OCOTP_CTRL_TOG                  
+#define BP_OCOTP_CTRL_WR_UNLOCK             16
+#define BM_OCOTP_CTRL_WR_UNLOCK             0xffff0000
+#define BV_OCOTP_CTRL_WR_UNLOCK__KEY        0x3e77
+#define BF_OCOTP_CTRL_WR_UNLOCK(v)          (((v) & 0xffff) << 16)
+#define BFM_OCOTP_CTRL_WR_UNLOCK(v)         BM_OCOTP_CTRL_WR_UNLOCK
+#define BF_OCOTP_CTRL_WR_UNLOCK_V(e)        BF_OCOTP_CTRL_WR_UNLOCK(BV_OCOTP_CTRL_WR_UNLOCK__##e)
+#define BFM_OCOTP_CTRL_WR_UNLOCK_V(v)       BM_OCOTP_CTRL_WR_UNLOCK
+#define BP_OCOTP_CTRL_RELOAD_SHADOWS        13
+#define BM_OCOTP_CTRL_RELOAD_SHADOWS        0x2000
+#define BF_OCOTP_CTRL_RELOAD_SHADOWS(v)     (((v) & 0x1) << 13)
+#define BFM_OCOTP_CTRL_RELOAD_SHADOWS(v)    BM_OCOTP_CTRL_RELOAD_SHADOWS
+#define BF_OCOTP_CTRL_RELOAD_SHADOWS_V(e)   BF_OCOTP_CTRL_RELOAD_SHADOWS(BV_OCOTP_CTRL_RELOAD_SHADOWS__##e)
+#define BFM_OCOTP_CTRL_RELOAD_SHADOWS_V(v)  BM_OCOTP_CTRL_RELOAD_SHADOWS
+#define BP_OCOTP_CTRL_RD_BANK_OPEN          12
+#define BM_OCOTP_CTRL_RD_BANK_OPEN          0x1000
+#define BF_OCOTP_CTRL_RD_BANK_OPEN(v)       (((v) & 0x1) << 12)
+#define BFM_OCOTP_CTRL_RD_BANK_OPEN(v)      BM_OCOTP_CTRL_RD_BANK_OPEN
+#define BF_OCOTP_CTRL_RD_BANK_OPEN_V(e)     BF_OCOTP_CTRL_RD_BANK_OPEN(BV_OCOTP_CTRL_RD_BANK_OPEN__##e)
+#define BFM_OCOTP_CTRL_RD_BANK_OPEN_V(v)    BM_OCOTP_CTRL_RD_BANK_OPEN
+#define BP_OCOTP_CTRL_ERROR                 9
+#define BM_OCOTP_CTRL_ERROR                 0x200
+#define BF_OCOTP_CTRL_ERROR(v)              (((v) & 0x1) << 9)
+#define BFM_OCOTP_CTRL_ERROR(v)             BM_OCOTP_CTRL_ERROR
+#define BF_OCOTP_CTRL_ERROR_V(e)            BF_OCOTP_CTRL_ERROR(BV_OCOTP_CTRL_ERROR__##e)
+#define BFM_OCOTP_CTRL_ERROR_V(v)           BM_OCOTP_CTRL_ERROR
+#define BP_OCOTP_CTRL_BUSY                  8
+#define BM_OCOTP_CTRL_BUSY                  0x100
+#define BF_OCOTP_CTRL_BUSY(v)               (((v) & 0x1) << 8)
+#define BFM_OCOTP_CTRL_BUSY(v)              BM_OCOTP_CTRL_BUSY
+#define BF_OCOTP_CTRL_BUSY_V(e)             BF_OCOTP_CTRL_BUSY(BV_OCOTP_CTRL_BUSY__##e)
+#define BFM_OCOTP_CTRL_BUSY_V(v)            BM_OCOTP_CTRL_BUSY
+#define BP_OCOTP_CTRL_ADDR                  0
+#define BM_OCOTP_CTRL_ADDR                  0x1f
+#define BF_OCOTP_CTRL_ADDR(v)               (((v) & 0x1f) << 0)
+#define BFM_OCOTP_CTRL_ADDR(v)              BM_OCOTP_CTRL_ADDR
+#define BF_OCOTP_CTRL_ADDR_V(e)             BF_OCOTP_CTRL_ADDR(BV_OCOTP_CTRL_ADDR__##e)
+#define BFM_OCOTP_CTRL_ADDR_V(v)            BM_OCOTP_CTRL_ADDR
+
+#define HW_OCOTP_DATA               HW(OCOTP_DATA)
+#define HWA_OCOTP_DATA              (0x8002c000 + 0x10)
+#define HWT_OCOTP_DATA              HWIO_32_RW
+#define HWN_OCOTP_DATA              OCOTP_DATA
+#define HWI_OCOTP_DATA              
+#define BP_OCOTP_DATA_DATA          0
+#define BM_OCOTP_DATA_DATA          0xffffffff
+#define BF_OCOTP_DATA_DATA(v)       (((v) & 0xffffffff) << 0)
+#define BFM_OCOTP_DATA_DATA(v)      BM_OCOTP_DATA_DATA
+#define BF_OCOTP_DATA_DATA_V(e)     BF_OCOTP_DATA_DATA(BV_OCOTP_DATA_DATA__##e)
+#define BFM_OCOTP_DATA_DATA_V(v)    BM_OCOTP_DATA_DATA
+
+#define HW_OCOTP_CUSTn(_n1)         HW(OCOTP_CUSTn(_n1))
+#define HWA_OCOTP_CUSTn(_n1)        (0x8002c000 + 0x20 + (_n1) * 0x10)
+#define HWT_OCOTP_CUSTn(_n1)        HWIO_32_RW
+#define HWN_OCOTP_CUSTn(_n1)        OCOTP_CUSTn
+#define HWI_OCOTP_CUSTn(_n1)        (_n1)
+#define BP_OCOTP_CUSTn_BITS         0
+#define BM_OCOTP_CUSTn_BITS         0xffffffff
+#define BF_OCOTP_CUSTn_BITS(v)      (((v) & 0xffffffff) << 0)
+#define BFM_OCOTP_CUSTn_BITS(v)     BM_OCOTP_CUSTn_BITS
+#define BF_OCOTP_CUSTn_BITS_V(e)    BF_OCOTP_CUSTn_BITS(BV_OCOTP_CUSTn_BITS__##e)
+#define BFM_OCOTP_CUSTn_BITS_V(v)   BM_OCOTP_CUSTn_BITS
+
+#define HW_OCOTP_CRYPTOn(_n1)       HW(OCOTP_CRYPTOn(_n1))
+#define HWA_OCOTP_CRYPTOn(_n1)      (0x8002c000 + 0x60 + (_n1) * 0x10)
+#define HWT_OCOTP_CRYPTOn(_n1)      HWIO_32_RW
+#define HWN_OCOTP_CRYPTOn(_n1)      OCOTP_CRYPTOn
+#define HWI_OCOTP_CRYPTOn(_n1)      (_n1)
+#define BP_OCOTP_CRYPTOn_BITS       0
+#define BM_OCOTP_CRYPTOn_BITS       0xffffffff
+#define BF_OCOTP_CRYPTOn_BITS(v)    (((v) & 0xffffffff) << 0)
+#define BFM_OCOTP_CRYPTOn_BITS(v)   BM_OCOTP_CRYPTOn_BITS
+#define BF_OCOTP_CRYPTOn_BITS_V(e)  BF_OCOTP_CRYPTOn_BITS(BV_OCOTP_CRYPTOn_BITS__##e)
+#define BFM_OCOTP_CRYPTOn_BITS_V(v) BM_OCOTP_CRYPTOn_BITS
+
+#define HW_OCOTP_HWCAPn(_n1)        HW(OCOTP_HWCAPn(_n1))
+#define HWA_OCOTP_HWCAPn(_n1)       (0x8002c000 + 0xa0 + (_n1) * 0x10)
+#define HWT_OCOTP_HWCAPn(_n1)       HWIO_32_RW
+#define HWN_OCOTP_HWCAPn(_n1)       OCOTP_HWCAPn
+#define HWI_OCOTP_HWCAPn(_n1)       (_n1)
+#define BP_OCOTP_HWCAPn_BITS        0
+#define BM_OCOTP_HWCAPn_BITS        0xffffffff
+#define BF_OCOTP_HWCAPn_BITS(v)     (((v) & 0xffffffff) << 0)
+#define BFM_OCOTP_HWCAPn_BITS(v)    BM_OCOTP_HWCAPn_BITS
+#define BF_OCOTP_HWCAPn_BITS_V(e)   BF_OCOTP_HWCAPn_BITS(BV_OCOTP_HWCAPn_BITS__##e)
+#define BFM_OCOTP_HWCAPn_BITS_V(v)  BM_OCOTP_HWCAPn_BITS
+
+#define HW_OCOTP_SWCAP              HW(OCOTP_SWCAP)
+#define HWA_OCOTP_SWCAP             (0x8002c000 + 0x100)
+#define HWT_OCOTP_SWCAP             HWIO_32_RW
+#define HWN_OCOTP_SWCAP             OCOTP_SWCAP
+#define HWI_OCOTP_SWCAP             
+#define BP_OCOTP_SWCAP_BITS         0
+#define BM_OCOTP_SWCAP_BITS         0xffffffff
+#define BF_OCOTP_SWCAP_BITS(v)      (((v) & 0xffffffff) << 0)
+#define BFM_OCOTP_SWCAP_BITS(v)     BM_OCOTP_SWCAP_BITS
+#define BF_OCOTP_SWCAP_BITS_V(e)    BF_OCOTP_SWCAP_BITS(BV_OCOTP_SWCAP_BITS__##e)
+#define BFM_OCOTP_SWCAP_BITS_V(v)   BM_OCOTP_SWCAP_BITS
+
+#define HW_OCOTP_CUSTCAP            HW(OCOTP_CUSTCAP)
+#define HWA_OCOTP_CUSTCAP           (0x8002c000 + 0x110)
+#define HWT_OCOTP_CUSTCAP           HWIO_32_RW
+#define HWN_OCOTP_CUSTCAP           OCOTP_CUSTCAP
+#define HWI_OCOTP_CUSTCAP           
+#define BP_OCOTP_CUSTCAP_BITS       0
+#define BM_OCOTP_CUSTCAP_BITS       0xffffffff
+#define BF_OCOTP_CUSTCAP_BITS(v)    (((v) & 0xffffffff) << 0)
+#define BFM_OCOTP_CUSTCAP_BITS(v)   BM_OCOTP_CUSTCAP_BITS
+#define BF_OCOTP_CUSTCAP_BITS_V(e)  BF_OCOTP_CUSTCAP_BITS(BV_OCOTP_CUSTCAP_BITS__##e)
+#define BFM_OCOTP_CUSTCAP_BITS_V(v) BM_OCOTP_CUSTCAP_BITS
+
+#define HW_OCOTP_LOCK                       HW(OCOTP_LOCK)
+#define HWA_OCOTP_LOCK                      (0x8002c000 + 0x120)
+#define HWT_OCOTP_LOCK                      HWIO_32_RW
+#define HWN_OCOTP_LOCK                      OCOTP_LOCK
+#define HWI_OCOTP_LOCK                      
+#define BP_OCOTP_LOCK_ROM7                  31
+#define BM_OCOTP_LOCK_ROM7                  0x80000000
+#define BF_OCOTP_LOCK_ROM7(v)               (((v) & 0x1) << 31)
+#define BFM_OCOTP_LOCK_ROM7(v)              BM_OCOTP_LOCK_ROM7
+#define BF_OCOTP_LOCK_ROM7_V(e)             BF_OCOTP_LOCK_ROM7(BV_OCOTP_LOCK_ROM7__##e)
+#define BFM_OCOTP_LOCK_ROM7_V(v)            BM_OCOTP_LOCK_ROM7
+#define BP_OCOTP_LOCK_ROM6                  30
+#define BM_OCOTP_LOCK_ROM6                  0x40000000
+#define BF_OCOTP_LOCK_ROM6(v)               (((v) & 0x1) << 30)
+#define BFM_OCOTP_LOCK_ROM6(v)              BM_OCOTP_LOCK_ROM6
+#define BF_OCOTP_LOCK_ROM6_V(e)             BF_OCOTP_LOCK_ROM6(BV_OCOTP_LOCK_ROM6__##e)
+#define BFM_OCOTP_LOCK_ROM6_V(v)            BM_OCOTP_LOCK_ROM6
+#define BP_OCOTP_LOCK_ROM5                  29
+#define BM_OCOTP_LOCK_ROM5                  0x20000000
+#define BF_OCOTP_LOCK_ROM5(v)               (((v) & 0x1) << 29)
+#define BFM_OCOTP_LOCK_ROM5(v)              BM_OCOTP_LOCK_ROM5
+#define BF_OCOTP_LOCK_ROM5_V(e)             BF_OCOTP_LOCK_ROM5(BV_OCOTP_LOCK_ROM5__##e)
+#define BFM_OCOTP_LOCK_ROM5_V(v)            BM_OCOTP_LOCK_ROM5
+#define BP_OCOTP_LOCK_ROM4                  28
+#define BM_OCOTP_LOCK_ROM4                  0x10000000
+#define BF_OCOTP_LOCK_ROM4(v)               (((v) & 0x1) << 28)
+#define BFM_OCOTP_LOCK_ROM4(v)              BM_OCOTP_LOCK_ROM4
+#define BF_OCOTP_LOCK_ROM4_V(e)             BF_OCOTP_LOCK_ROM4(BV_OCOTP_LOCK_ROM4__##e)
+#define BFM_OCOTP_LOCK_ROM4_V(v)            BM_OCOTP_LOCK_ROM4
+#define BP_OCOTP_LOCK_ROM3                  27
+#define BM_OCOTP_LOCK_ROM3                  0x8000000
+#define BF_OCOTP_LOCK_ROM3(v)               (((v) & 0x1) << 27)
+#define BFM_OCOTP_LOCK_ROM3(v)              BM_OCOTP_LOCK_ROM3
+#define BF_OCOTP_LOCK_ROM3_V(e)             BF_OCOTP_LOCK_ROM3(BV_OCOTP_LOCK_ROM3__##e)
+#define BFM_OCOTP_LOCK_ROM3_V(v)            BM_OCOTP_LOCK_ROM3
+#define BP_OCOTP_LOCK_ROM2                  26
+#define BM_OCOTP_LOCK_ROM2                  0x4000000
+#define BF_OCOTP_LOCK_ROM2(v)               (((v) & 0x1) << 26)
+#define BFM_OCOTP_LOCK_ROM2(v)              BM_OCOTP_LOCK_ROM2
+#define BF_OCOTP_LOCK_ROM2_V(e)             BF_OCOTP_LOCK_ROM2(BV_OCOTP_LOCK_ROM2__##e)
+#define BFM_OCOTP_LOCK_ROM2_V(v)            BM_OCOTP_LOCK_ROM2
+#define BP_OCOTP_LOCK_ROM1                  25
+#define BM_OCOTP_LOCK_ROM1                  0x2000000
+#define BF_OCOTP_LOCK_ROM1(v)               (((v) & 0x1) << 25)
+#define BFM_OCOTP_LOCK_ROM1(v)              BM_OCOTP_LOCK_ROM1
+#define BF_OCOTP_LOCK_ROM1_V(e)             BF_OCOTP_LOCK_ROM1(BV_OCOTP_LOCK_ROM1__##e)
+#define BFM_OCOTP_LOCK_ROM1_V(v)            BM_OCOTP_LOCK_ROM1
+#define BP_OCOTP_LOCK_ROM0                  24
+#define BM_OCOTP_LOCK_ROM0                  0x1000000
+#define BF_OCOTP_LOCK_ROM0(v)               (((v) & 0x1) << 24)
+#define BFM_OCOTP_LOCK_ROM0(v)              BM_OCOTP_LOCK_ROM0
+#define BF_OCOTP_LOCK_ROM0_V(e)             BF_OCOTP_LOCK_ROM0(BV_OCOTP_LOCK_ROM0__##e)
+#define BFM_OCOTP_LOCK_ROM0_V(v)            BM_OCOTP_LOCK_ROM0
+#define BP_OCOTP_LOCK_HWSW_SHADOW_ALT       23
+#define BM_OCOTP_LOCK_HWSW_SHADOW_ALT       0x800000
+#define BF_OCOTP_LOCK_HWSW_SHADOW_ALT(v)    (((v) & 0x1) << 23)
+#define BFM_OCOTP_LOCK_HWSW_SHADOW_ALT(v)   BM_OCOTP_LOCK_HWSW_SHADOW_ALT
+#define BF_OCOTP_LOCK_HWSW_SHADOW_ALT_V(e)  BF_OCOTP_LOCK_HWSW_SHADOW_ALT(BV_OCOTP_LOCK_HWSW_SHADOW_ALT__##e)
+#define BFM_OCOTP_LOCK_HWSW_SHADOW_ALT_V(v) BM_OCOTP_LOCK_HWSW_SHADOW_ALT
+#define BP_OCOTP_LOCK_CRYPTODCP_ALT         22
+#define BM_OCOTP_LOCK_CRYPTODCP_ALT         0x400000
+#define BF_OCOTP_LOCK_CRYPTODCP_ALT(v)      (((v) & 0x1) << 22)
+#define BFM_OCOTP_LOCK_CRYPTODCP_ALT(v)     BM_OCOTP_LOCK_CRYPTODCP_ALT
+#define BF_OCOTP_LOCK_CRYPTODCP_ALT_V(e)    BF_OCOTP_LOCK_CRYPTODCP_ALT(BV_OCOTP_LOCK_CRYPTODCP_ALT__##e)
+#define BFM_OCOTP_LOCK_CRYPTODCP_ALT_V(v)   BM_OCOTP_LOCK_CRYPTODCP_ALT
+#define BP_OCOTP_LOCK_CRYPTOKEY_ALT         21
+#define BM_OCOTP_LOCK_CRYPTOKEY_ALT         0x200000
+#define BF_OCOTP_LOCK_CRYPTOKEY_ALT(v)      (((v) & 0x1) << 21)
+#define BFM_OCOTP_LOCK_CRYPTOKEY_ALT(v)     BM_OCOTP_LOCK_CRYPTOKEY_ALT
+#define BF_OCOTP_LOCK_CRYPTOKEY_ALT_V(e)    BF_OCOTP_LOCK_CRYPTOKEY_ALT(BV_OCOTP_LOCK_CRYPTOKEY_ALT__##e)
+#define BFM_OCOTP_LOCK_CRYPTOKEY_ALT_V(v)   BM_OCOTP_LOCK_CRYPTOKEY_ALT
+#define BP_OCOTP_LOCK_PIN                   20
+#define BM_OCOTP_LOCK_PIN                   0x100000
+#define BF_OCOTP_LOCK_PIN(v)                (((v) & 0x1) << 20)
+#define BFM_OCOTP_LOCK_PIN(v)               BM_OCOTP_LOCK_PIN
+#define BF_OCOTP_LOCK_PIN_V(e)              BF_OCOTP_LOCK_PIN(BV_OCOTP_LOCK_PIN__##e)
+#define BFM_OCOTP_LOCK_PIN_V(v)             BM_OCOTP_LOCK_PIN
+#define BP_OCOTP_LOCK_OPS                   19
+#define BM_OCOTP_LOCK_OPS                   0x80000
+#define BF_OCOTP_LOCK_OPS(v)                (((v) & 0x1) << 19)
+#define BFM_OCOTP_LOCK_OPS(v)               BM_OCOTP_LOCK_OPS
+#define BF_OCOTP_LOCK_OPS_V(e)              BF_OCOTP_LOCK_OPS(BV_OCOTP_LOCK_OPS__##e)
+#define BFM_OCOTP_LOCK_OPS_V(v)             BM_OCOTP_LOCK_OPS
+#define BP_OCOTP_LOCK_UN2                   18
+#define BM_OCOTP_LOCK_UN2                   0x40000
+#define BF_OCOTP_LOCK_UN2(v)                (((v) & 0x1) << 18)
+#define BFM_OCOTP_LOCK_UN2(v)               BM_OCOTP_LOCK_UN2
+#define BF_OCOTP_LOCK_UN2_V(e)              BF_OCOTP_LOCK_UN2(BV_OCOTP_LOCK_UN2__##e)
+#define BFM_OCOTP_LOCK_UN2_V(v)             BM_OCOTP_LOCK_UN2
+#define BP_OCOTP_LOCK_UN1                   17
+#define BM_OCOTP_LOCK_UN1                   0x20000
+#define BF_OCOTP_LOCK_UN1(v)                (((v) & 0x1) << 17)
+#define BFM_OCOTP_LOCK_UN1(v)               BM_OCOTP_LOCK_UN1
+#define BF_OCOTP_LOCK_UN1_V(e)              BF_OCOTP_LOCK_UN1(BV_OCOTP_LOCK_UN1__##e)
+#define BFM_OCOTP_LOCK_UN1_V(v)             BM_OCOTP_LOCK_UN1
+#define BP_OCOTP_LOCK_UN0                   16
+#define BM_OCOTP_LOCK_UN0                   0x10000
+#define BF_OCOTP_LOCK_UN0(v)                (((v) & 0x1) << 16)
+#define BFM_OCOTP_LOCK_UN0(v)               BM_OCOTP_LOCK_UN0
+#define BF_OCOTP_LOCK_UN0_V(e)              BF_OCOTP_LOCK_UN0(BV_OCOTP_LOCK_UN0__##e)
+#define BFM_OCOTP_LOCK_UN0_V(v)             BM_OCOTP_LOCK_UN0
+#define BP_OCOTP_LOCK_UNALLOCATED           10
+#define BM_OCOTP_LOCK_UNALLOCATED           0xfc00
+#define BF_OCOTP_LOCK_UNALLOCATED(v)        (((v) & 0x3f) << 10)
+#define BFM_OCOTP_LOCK_UNALLOCATED(v)       BM_OCOTP_LOCK_UNALLOCATED
+#define BF_OCOTP_LOCK_UNALLOCATED_V(e)      BF_OCOTP_LOCK_UNALLOCATED(BV_OCOTP_LOCK_UNALLOCATED__##e)
+#define BFM_OCOTP_LOCK_UNALLOCATED_V(v)     BM_OCOTP_LOCK_UNALLOCATED
+#define BP_OCOTP_LOCK_CUSTCAP               9
+#define BM_OCOTP_LOCK_CUSTCAP               0x200
+#define BF_OCOTP_LOCK_CUSTCAP(v)            (((v) & 0x1) << 9)
+#define BFM_OCOTP_LOCK_CUSTCAP(v)           BM_OCOTP_LOCK_CUSTCAP
+#define BF_OCOTP_LOCK_CUSTCAP_V(e)          BF_OCOTP_LOCK_CUSTCAP(BV_OCOTP_LOCK_CUSTCAP__##e)
+#define BFM_OCOTP_LOCK_CUSTCAP_V(v)         BM_OCOTP_LOCK_CUSTCAP
+#define BP_OCOTP_LOCK_HWSW                  8
+#define BM_OCOTP_LOCK_HWSW                  0x100
+#define BF_OCOTP_LOCK_HWSW(v)               (((v) & 0x1) << 8)
+#define BFM_OCOTP_LOCK_HWSW(v)              BM_OCOTP_LOCK_HWSW
+#define BF_OCOTP_LOCK_HWSW_V(e)             BF_OCOTP_LOCK_HWSW(BV_OCOTP_LOCK_HWSW__##e)
+#define BFM_OCOTP_LOCK_HWSW_V(v)            BM_OCOTP_LOCK_HWSW
+#define BP_OCOTP_LOCK_CUSTCAP_SHADOW        7
+#define BM_OCOTP_LOCK_CUSTCAP_SHADOW        0x80
+#define BF_OCOTP_LOCK_CUSTCAP_SHADOW(v)     (((v) & 0x1) << 7)
+#define BFM_OCOTP_LOCK_CUSTCAP_SHADOW(v)    BM_OCOTP_LOCK_CUSTCAP_SHADOW
+#define BF_OCOTP_LOCK_CUSTCAP_SHADOW_V(e)   BF_OCOTP_LOCK_CUSTCAP_SHADOW(BV_OCOTP_LOCK_CUSTCAP_SHADOW__##e)
+#define BFM_OCOTP_LOCK_CUSTCAP_SHADOW_V(v)  BM_OCOTP_LOCK_CUSTCAP_SHADOW
+#define BP_OCOTP_LOCK_HWSW_SHADOW           6
+#define BM_OCOTP_LOCK_HWSW_SHADOW           0x40
+#define BF_OCOTP_LOCK_HWSW_SHADOW(v)        (((v) & 0x1) << 6)
+#define BFM_OCOTP_LOCK_HWSW_SHADOW(v)       BM_OCOTP_LOCK_HWSW_SHADOW
+#define BF_OCOTP_LOCK_HWSW_SHADOW_V(e)      BF_OCOTP_LOCK_HWSW_SHADOW(BV_OCOTP_LOCK_HWSW_SHADOW__##e)
+#define BFM_OCOTP_LOCK_HWSW_SHADOW_V(v)     BM_OCOTP_LOCK_HWSW_SHADOW
+#define BP_OCOTP_LOCK_CRYPTODCP             5
+#define BM_OCOTP_LOCK_CRYPTODCP             0x20
+#define BF_OCOTP_LOCK_CRYPTODCP(v)          (((v) & 0x1) << 5)
+#define BFM_OCOTP_LOCK_CRYPTODCP(v)         BM_OCOTP_LOCK_CRYPTODCP
+#define BF_OCOTP_LOCK_CRYPTODCP_V(e)        BF_OCOTP_LOCK_CRYPTODCP(BV_OCOTP_LOCK_CRYPTODCP__##e)
+#define BFM_OCOTP_LOCK_CRYPTODCP_V(v)       BM_OCOTP_LOCK_CRYPTODCP
+#define BP_OCOTP_LOCK_CRYPTOKEY             4
+#define BM_OCOTP_LOCK_CRYPTOKEY             0x10
+#define BF_OCOTP_LOCK_CRYPTOKEY(v)          (((v) & 0x1) << 4)
+#define BFM_OCOTP_LOCK_CRYPTOKEY(v)         BM_OCOTP_LOCK_CRYPTOKEY
+#define BF_OCOTP_LOCK_CRYPTOKEY_V(e)        BF_OCOTP_LOCK_CRYPTOKEY(BV_OCOTP_LOCK_CRYPTOKEY__##e)
+#define BFM_OCOTP_LOCK_CRYPTOKEY_V(v)       BM_OCOTP_LOCK_CRYPTOKEY
+#define BP_OCOTP_LOCK_CUST3                 3
+#define BM_OCOTP_LOCK_CUST3                 0x8
+#define BF_OCOTP_LOCK_CUST3(v)              (((v) & 0x1) << 3)
+#define BFM_OCOTP_LOCK_CUST3(v)             BM_OCOTP_LOCK_CUST3
+#define BF_OCOTP_LOCK_CUST3_V(e)            BF_OCOTP_LOCK_CUST3(BV_OCOTP_LOCK_CUST3__##e)
+#define BFM_OCOTP_LOCK_CUST3_V(v)           BM_OCOTP_LOCK_CUST3
+#define BP_OCOTP_LOCK_CUST2                 2
+#define BM_OCOTP_LOCK_CUST2                 0x4
+#define BF_OCOTP_LOCK_CUST2(v)              (((v) & 0x1) << 2)
+#define BFM_OCOTP_LOCK_CUST2(v)             BM_OCOTP_LOCK_CUST2
+#define BF_OCOTP_LOCK_CUST2_V(e)            BF_OCOTP_LOCK_CUST2(BV_OCOTP_LOCK_CUST2__##e)
+#define BFM_OCOTP_LOCK_CUST2_V(v)           BM_OCOTP_LOCK_CUST2
+#define BP_OCOTP_LOCK_CUST1                 1
+#define BM_OCOTP_LOCK_CUST1                 0x2
+#define BF_OCOTP_LOCK_CUST1(v)              (((v) & 0x1) << 1)
+#define BFM_OCOTP_LOCK_CUST1(v)             BM_OCOTP_LOCK_CUST1
+#define BF_OCOTP_LOCK_CUST1_V(e)            BF_OCOTP_LOCK_CUST1(BV_OCOTP_LOCK_CUST1__##e)
+#define BFM_OCOTP_LOCK_CUST1_V(v)           BM_OCOTP_LOCK_CUST1
+#define BP_OCOTP_LOCK_CUST0                 0
+#define BM_OCOTP_LOCK_CUST0                 0x1
+#define BF_OCOTP_LOCK_CUST0(v)              (((v) & 0x1) << 0)
+#define BFM_OCOTP_LOCK_CUST0(v)             BM_OCOTP_LOCK_CUST0
+#define BF_OCOTP_LOCK_CUST0_V(e)            BF_OCOTP_LOCK_CUST0(BV_OCOTP_LOCK_CUST0__##e)
+#define BFM_OCOTP_LOCK_CUST0_V(v)           BM_OCOTP_LOCK_CUST0
+
+#define HW_OCOTP_OPSn(_n1)          HW(OCOTP_OPSn(_n1))
+#define HWA_OCOTP_OPSn(_n1)         (0x8002c000 + 0x130 + (_n1) * 0x10)
+#define HWT_OCOTP_OPSn(_n1)         HWIO_32_RW
+#define HWN_OCOTP_OPSn(_n1)         OCOTP_OPSn
+#define HWI_OCOTP_OPSn(_n1)         (_n1)
+#define BP_OCOTP_OPSn_BITS          0
+#define BM_OCOTP_OPSn_BITS          0xffffffff
+#define BF_OCOTP_OPSn_BITS(v)       (((v) & 0xffffffff) << 0)
+#define BFM_OCOTP_OPSn_BITS(v)      BM_OCOTP_OPSn_BITS
+#define BF_OCOTP_OPSn_BITS_V(e)     BF_OCOTP_OPSn_BITS(BV_OCOTP_OPSn_BITS__##e)
+#define BFM_OCOTP_OPSn_BITS_V(v)    BM_OCOTP_OPSn_BITS
+
+#define HW_OCOTP_UNn(_n1)       HW(OCOTP_UNn(_n1))
+#define HWA_OCOTP_UNn(_n1)      (0x8002c000 + 0x170 + (_n1) * 0x10)
+#define HWT_OCOTP_UNn(_n1)      HWIO_32_RW
+#define HWN_OCOTP_UNn(_n1)      OCOTP_UNn
+#define HWI_OCOTP_UNn(_n1)      (_n1)
+#define BP_OCOTP_UNn_BITS       0
+#define BM_OCOTP_UNn_BITS       0xffffffff
+#define BF_OCOTP_UNn_BITS(v)    (((v) & 0xffffffff) << 0)
+#define BFM_OCOTP_UNn_BITS(v)   BM_OCOTP_UNn_BITS
+#define BF_OCOTP_UNn_BITS_V(e)  BF_OCOTP_UNn_BITS(BV_OCOTP_UNn_BITS__##e)
+#define BFM_OCOTP_UNn_BITS_V(v) BM_OCOTP_UNn_BITS
+
+#define HW_OCOTP_ROMn(_n1)          HW(OCOTP_ROMn(_n1))
+#define HWA_OCOTP_ROMn(_n1)         (0x8002c000 + 0x1a0 + (_n1) * 0x10)
+#define HWT_OCOTP_ROMn(_n1)         HWIO_32_RW
+#define HWN_OCOTP_ROMn(_n1)         OCOTP_ROMn
+#define HWI_OCOTP_ROMn(_n1)         (_n1)
+#define BP_OCOTP_ROMn_BITS          0
+#define BM_OCOTP_ROMn_BITS          0xffffffff
+#define BF_OCOTP_ROMn_BITS(v)       (((v) & 0xffffffff) << 0)
+#define BFM_OCOTP_ROMn_BITS(v)      BM_OCOTP_ROMn_BITS
+#define BF_OCOTP_ROMn_BITS_V(e)     BF_OCOTP_ROMn_BITS(BV_OCOTP_ROMn_BITS__##e)
+#define BFM_OCOTP_ROMn_BITS_V(v)    BM_OCOTP_ROMn_BITS
+
+#define HW_OCOTP_VERSION                HW(OCOTP_VERSION)
+#define HWA_OCOTP_VERSION               (0x8002c000 + 0x220)
+#define HWT_OCOTP_VERSION               HWIO_32_RW
+#define HWN_OCOTP_VERSION               OCOTP_VERSION
+#define HWI_OCOTP_VERSION               
+#define BP_OCOTP_VERSION_MAJOR          24
+#define BM_OCOTP_VERSION_MAJOR          0xff000000
+#define BF_OCOTP_VERSION_MAJOR(v)       (((v) & 0xff) << 24)
+#define BFM_OCOTP_VERSION_MAJOR(v)      BM_OCOTP_VERSION_MAJOR
+#define BF_OCOTP_VERSION_MAJOR_V(e)     BF_OCOTP_VERSION_MAJOR(BV_OCOTP_VERSION_MAJOR__##e)
+#define BFM_OCOTP_VERSION_MAJOR_V(v)    BM_OCOTP_VERSION_MAJOR
+#define BP_OCOTP_VERSION_MINOR          16
+#define BM_OCOTP_VERSION_MINOR          0xff0000
+#define BF_OCOTP_VERSION_MINOR(v)       (((v) & 0xff) << 16)
+#define BFM_OCOTP_VERSION_MINOR(v)      BM_OCOTP_VERSION_MINOR
+#define BF_OCOTP_VERSION_MINOR_V(e)     BF_OCOTP_VERSION_MINOR(BV_OCOTP_VERSION_MINOR__##e)
+#define BFM_OCOTP_VERSION_MINOR_V(v)    BM_OCOTP_VERSION_MINOR
+#define BP_OCOTP_VERSION_STEP           0
+#define BM_OCOTP_VERSION_STEP           0xffff
+#define BF_OCOTP_VERSION_STEP(v)        (((v) & 0xffff) << 0)
+#define BFM_OCOTP_VERSION_STEP(v)       BM_OCOTP_VERSION_STEP
+#define BF_OCOTP_VERSION_STEP_V(e)      BF_OCOTP_VERSION_STEP(BV_OCOTP_VERSION_STEP__##e)
+#define BFM_OCOTP_VERSION_STEP_V(v)     BM_OCOTP_VERSION_STEP
+
+#endif /* __HEADERGEN_STMP3700_OCOTP_H__*/
diff --git a/firmware/target/arm/imx233/regs/stmp3700/pinctrl.h b/firmware/target/arm/imx233/regs/stmp3700/pinctrl.h
new file mode 100644
index 0000000000..6d3a1ea83f
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3700/pinctrl.h
@@ -0,0 +1,405 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * stmp3700 version: 2.4.0
+ * stmp3700 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_STMP3700_PINCTRL_H__
+#define __HEADERGEN_STMP3700_PINCTRL_H__
+
+#define HW_PINCTRL_CTRL                 HW(PINCTRL_CTRL)
+#define HWA_PINCTRL_CTRL                (0x80018000 + 0x0)
+#define HWT_PINCTRL_CTRL                HWIO_32_RW
+#define HWN_PINCTRL_CTRL                PINCTRL_CTRL
+#define HWI_PINCTRL_CTRL                
+#define HW_PINCTRL_CTRL_SET             HW(PINCTRL_CTRL_SET)
+#define HWA_PINCTRL_CTRL_SET            (HWA_PINCTRL_CTRL + 0x4)
+#define HWT_PINCTRL_CTRL_SET            HWIO_32_WO
+#define HWN_PINCTRL_CTRL_SET            PINCTRL_CTRL
+#define HWI_PINCTRL_CTRL_SET            
+#define HW_PINCTRL_CTRL_CLR             HW(PINCTRL_CTRL_CLR)
+#define HWA_PINCTRL_CTRL_CLR            (HWA_PINCTRL_CTRL + 0x8)
+#define HWT_PINCTRL_CTRL_CLR            HWIO_32_WO
+#define HWN_PINCTRL_CTRL_CLR            PINCTRL_CTRL
+#define HWI_PINCTRL_CTRL_CLR            
+#define HW_PINCTRL_CTRL_TOG             HW(PINCTRL_CTRL_TOG)
+#define HWA_PINCTRL_CTRL_TOG            (HWA_PINCTRL_CTRL + 0xc)
+#define HWT_PINCTRL_CTRL_TOG            HWIO_32_WO
+#define HWN_PINCTRL_CTRL_TOG            PINCTRL_CTRL
+#define HWI_PINCTRL_CTRL_TOG            
+#define BP_PINCTRL_CTRL_SFTRST          31
+#define BM_PINCTRL_CTRL_SFTRST          0x80000000
+#define BF_PINCTRL_CTRL_SFTRST(v)       (((v) & 0x1) << 31)
+#define BFM_PINCTRL_CTRL_SFTRST(v)      BM_PINCTRL_CTRL_SFTRST
+#define BF_PINCTRL_CTRL_SFTRST_V(e)     BF_PINCTRL_CTRL_SFTRST(BV_PINCTRL_CTRL_SFTRST__##e)
+#define BFM_PINCTRL_CTRL_SFTRST_V(v)    BM_PINCTRL_CTRL_SFTRST
+#define BP_PINCTRL_CTRL_CLKGATE         30
+#define BM_PINCTRL_CTRL_CLKGATE         0x40000000
+#define BF_PINCTRL_CTRL_CLKGATE(v)      (((v) & 0x1) << 30)
+#define BFM_PINCTRL_CTRL_CLKGATE(v)     BM_PINCTRL_CTRL_CLKGATE
+#define BF_PINCTRL_CTRL_CLKGATE_V(e)    BF_PINCTRL_CTRL_CLKGATE(BV_PINCTRL_CTRL_CLKGATE__##e)
+#define BFM_PINCTRL_CTRL_CLKGATE_V(v)   BM_PINCTRL_CTRL_CLKGATE
+#define BP_PINCTRL_CTRL_PRESENT3        29
+#define BM_PINCTRL_CTRL_PRESENT3        0x20000000
+#define BF_PINCTRL_CTRL_PRESENT3(v)     (((v) & 0x1) << 29)
+#define BFM_PINCTRL_CTRL_PRESENT3(v)    BM_PINCTRL_CTRL_PRESENT3
+#define BF_PINCTRL_CTRL_PRESENT3_V(e)   BF_PINCTRL_CTRL_PRESENT3(BV_PINCTRL_CTRL_PRESENT3__##e)
+#define BFM_PINCTRL_CTRL_PRESENT3_V(v)  BM_PINCTRL_CTRL_PRESENT3
+#define BP_PINCTRL_CTRL_PRESENT2        28
+#define BM_PINCTRL_CTRL_PRESENT2        0x10000000
+#define BF_PINCTRL_CTRL_PRESENT2(v)     (((v) & 0x1) << 28)
+#define BFM_PINCTRL_CTRL_PRESENT2(v)    BM_PINCTRL_CTRL_PRESENT2
+#define BF_PINCTRL_CTRL_PRESENT2_V(e)   BF_PINCTRL_CTRL_PRESENT2(BV_PINCTRL_CTRL_PRESENT2__##e)
+#define BFM_PINCTRL_CTRL_PRESENT2_V(v)  BM_PINCTRL_CTRL_PRESENT2
+#define BP_PINCTRL_CTRL_PRESENT1        27
+#define BM_PINCTRL_CTRL_PRESENT1        0x8000000
+#define BF_PINCTRL_CTRL_PRESENT1(v)     (((v) & 0x1) << 27)
+#define BFM_PINCTRL_CTRL_PRESENT1(v)    BM_PINCTRL_CTRL_PRESENT1
+#define BF_PINCTRL_CTRL_PRESENT1_V(e)   BF_PINCTRL_CTRL_PRESENT1(BV_PINCTRL_CTRL_PRESENT1__##e)
+#define BFM_PINCTRL_CTRL_PRESENT1_V(v)  BM_PINCTRL_CTRL_PRESENT1
+#define BP_PINCTRL_CTRL_PRESENT0        26
+#define BM_PINCTRL_CTRL_PRESENT0        0x4000000
+#define BF_PINCTRL_CTRL_PRESENT0(v)     (((v) & 0x1) << 26)
+#define BFM_PINCTRL_CTRL_PRESENT0(v)    BM_PINCTRL_CTRL_PRESENT0
+#define BF_PINCTRL_CTRL_PRESENT0_V(e)   BF_PINCTRL_CTRL_PRESENT0(BV_PINCTRL_CTRL_PRESENT0__##e)
+#define BFM_PINCTRL_CTRL_PRESENT0_V(v)  BM_PINCTRL_CTRL_PRESENT0
+#define BP_PINCTRL_CTRL_IRQOUT3         3
+#define BM_PINCTRL_CTRL_IRQOUT3         0x8
+#define BF_PINCTRL_CTRL_IRQOUT3(v)      (((v) & 0x1) << 3)
+#define BFM_PINCTRL_CTRL_IRQOUT3(v)     BM_PINCTRL_CTRL_IRQOUT3
+#define BF_PINCTRL_CTRL_IRQOUT3_V(e)    BF_PINCTRL_CTRL_IRQOUT3(BV_PINCTRL_CTRL_IRQOUT3__##e)
+#define BFM_PINCTRL_CTRL_IRQOUT3_V(v)   BM_PINCTRL_CTRL_IRQOUT3
+#define BP_PINCTRL_CTRL_IRQOUT2         2
+#define BM_PINCTRL_CTRL_IRQOUT2         0x4
+#define BF_PINCTRL_CTRL_IRQOUT2(v)      (((v) & 0x1) << 2)
+#define BFM_PINCTRL_CTRL_IRQOUT2(v)     BM_PINCTRL_CTRL_IRQOUT2
+#define BF_PINCTRL_CTRL_IRQOUT2_V(e)    BF_PINCTRL_CTRL_IRQOUT2(BV_PINCTRL_CTRL_IRQOUT2__##e)
+#define BFM_PINCTRL_CTRL_IRQOUT2_V(v)   BM_PINCTRL_CTRL_IRQOUT2
+#define BP_PINCTRL_CTRL_IRQOUT1         1
+#define BM_PINCTRL_CTRL_IRQOUT1         0x2
+#define BF_PINCTRL_CTRL_IRQOUT1(v)      (((v) & 0x1) << 1)
+#define BFM_PINCTRL_CTRL_IRQOUT1(v)     BM_PINCTRL_CTRL_IRQOUT1
+#define BF_PINCTRL_CTRL_IRQOUT1_V(e)    BF_PINCTRL_CTRL_IRQOUT1(BV_PINCTRL_CTRL_IRQOUT1__##e)
+#define BFM_PINCTRL_CTRL_IRQOUT1_V(v)   BM_PINCTRL_CTRL_IRQOUT1
+#define BP_PINCTRL_CTRL_IRQOUT0         0
+#define BM_PINCTRL_CTRL_IRQOUT0         0x1
+#define BF_PINCTRL_CTRL_IRQOUT0(v)      (((v) & 0x1) << 0)
+#define BFM_PINCTRL_CTRL_IRQOUT0(v)     BM_PINCTRL_CTRL_IRQOUT0
+#define BF_PINCTRL_CTRL_IRQOUT0_V(e)    BF_PINCTRL_CTRL_IRQOUT0(BV_PINCTRL_CTRL_IRQOUT0__##e)
+#define BFM_PINCTRL_CTRL_IRQOUT0_V(v)   BM_PINCTRL_CTRL_IRQOUT0
+
+#define HW_PINCTRL_MUXSELn(_n1)         HW(PINCTRL_MUXSELn(_n1))
+#define HWA_PINCTRL_MUXSELn(_n1)        (0x80018000 + 0x100 + (_n1) * 0x10)
+#define HWT_PINCTRL_MUXSELn(_n1)        HWIO_32_RW
+#define HWN_PINCTRL_MUXSELn(_n1)        PINCTRL_MUXSELn
+#define HWI_PINCTRL_MUXSELn(_n1)        (_n1)
+#define HW_PINCTRL_MUXSELn_SET(_n1)     HW(PINCTRL_MUXSELn_SET(_n1))
+#define HWA_PINCTRL_MUXSELn_SET(_n1)    (HWA_PINCTRL_MUXSELn(_n1) + 0x4)
+#define HWT_PINCTRL_MUXSELn_SET(_n1)    HWIO_32_WO
+#define HWN_PINCTRL_MUXSELn_SET(_n1)    PINCTRL_MUXSELn
+#define HWI_PINCTRL_MUXSELn_SET(_n1)    (_n1)
+#define HW_PINCTRL_MUXSELn_CLR(_n1)     HW(PINCTRL_MUXSELn_CLR(_n1))
+#define HWA_PINCTRL_MUXSELn_CLR(_n1)    (HWA_PINCTRL_MUXSELn(_n1) + 0x8)
+#define HWT_PINCTRL_MUXSELn_CLR(_n1)    HWIO_32_WO
+#define HWN_PINCTRL_MUXSELn_CLR(_n1)    PINCTRL_MUXSELn
+#define HWI_PINCTRL_MUXSELn_CLR(_n1)    (_n1)
+#define HW_PINCTRL_MUXSELn_TOG(_n1)     HW(PINCTRL_MUXSELn_TOG(_n1))
+#define HWA_PINCTRL_MUXSELn_TOG(_n1)    (HWA_PINCTRL_MUXSELn(_n1) + 0xc)
+#define HWT_PINCTRL_MUXSELn_TOG(_n1)    HWIO_32_WO
+#define HWN_PINCTRL_MUXSELn_TOG(_n1)    PINCTRL_MUXSELn
+#define HWI_PINCTRL_MUXSELn_TOG(_n1)    (_n1)
+#define BP_PINCTRL_MUXSELn_BITS         0
+#define BM_PINCTRL_MUXSELn_BITS         0xffffffff
+#define BF_PINCTRL_MUXSELn_BITS(v)      (((v) & 0xffffffff) << 0)
+#define BFM_PINCTRL_MUXSELn_BITS(v)     BM_PINCTRL_MUXSELn_BITS
+#define BF_PINCTRL_MUXSELn_BITS_V(e)    BF_PINCTRL_MUXSELn_BITS(BV_PINCTRL_MUXSELn_BITS__##e)
+#define BFM_PINCTRL_MUXSELn_BITS_V(v)   BM_PINCTRL_MUXSELn_BITS
+
+#define HW_PINCTRL_DRIVEn(_n1)          HW(PINCTRL_DRIVEn(_n1))
+#define HWA_PINCTRL_DRIVEn(_n1)         (0x80018000 + 0x200 + (_n1) * 0x10)
+#define HWT_PINCTRL_DRIVEn(_n1)         HWIO_32_RW
+#define HWN_PINCTRL_DRIVEn(_n1)         PINCTRL_DRIVEn
+#define HWI_PINCTRL_DRIVEn(_n1)         (_n1)
+#define HW_PINCTRL_DRIVEn_SET(_n1)      HW(PINCTRL_DRIVEn_SET(_n1))
+#define HWA_PINCTRL_DRIVEn_SET(_n1)     (HWA_PINCTRL_DRIVEn(_n1) + 0x4)
+#define HWT_PINCTRL_DRIVEn_SET(_n1)     HWIO_32_WO
+#define HWN_PINCTRL_DRIVEn_SET(_n1)     PINCTRL_DRIVEn
+#define HWI_PINCTRL_DRIVEn_SET(_n1)     (_n1)
+#define HW_PINCTRL_DRIVEn_CLR(_n1)      HW(PINCTRL_DRIVEn_CLR(_n1))
+#define HWA_PINCTRL_DRIVEn_CLR(_n1)     (HWA_PINCTRL_DRIVEn(_n1) + 0x8)
+#define HWT_PINCTRL_DRIVEn_CLR(_n1)     HWIO_32_WO
+#define HWN_PINCTRL_DRIVEn_CLR(_n1)     PINCTRL_DRIVEn
+#define HWI_PINCTRL_DRIVEn_CLR(_n1)     (_n1)
+#define HW_PINCTRL_DRIVEn_TOG(_n1)      HW(PINCTRL_DRIVEn_TOG(_n1))
+#define HWA_PINCTRL_DRIVEn_TOG(_n1)     (HWA_PINCTRL_DRIVEn(_n1) + 0xc)
+#define HWT_PINCTRL_DRIVEn_TOG(_n1)     HWIO_32_WO
+#define HWN_PINCTRL_DRIVEn_TOG(_n1)     PINCTRL_DRIVEn
+#define HWI_PINCTRL_DRIVEn_TOG(_n1)     (_n1)
+#define BP_PINCTRL_DRIVEn_BITS          0
+#define BM_PINCTRL_DRIVEn_BITS          0xffffffff
+#define BF_PINCTRL_DRIVEn_BITS(v)       (((v) & 0xffffffff) << 0)
+#define BFM_PINCTRL_DRIVEn_BITS(v)      BM_PINCTRL_DRIVEn_BITS
+#define BF_PINCTRL_DRIVEn_BITS_V(e)     BF_PINCTRL_DRIVEn_BITS(BV_PINCTRL_DRIVEn_BITS__##e)
+#define BFM_PINCTRL_DRIVEn_BITS_V(v)    BM_PINCTRL_DRIVEn_BITS
+
+#define HW_PINCTRL_PULLn(_n1)       HW(PINCTRL_PULLn(_n1))
+#define HWA_PINCTRL_PULLn(_n1)      (0x80018000 + 0x300 + (_n1) * 0x10)
+#define HWT_PINCTRL_PULLn(_n1)      HWIO_32_RW
+#define HWN_PINCTRL_PULLn(_n1)      PINCTRL_PULLn
+#define HWI_PINCTRL_PULLn(_n1)      (_n1)
+#define HW_PINCTRL_PULLn_SET(_n1)   HW(PINCTRL_PULLn_SET(_n1))
+#define HWA_PINCTRL_PULLn_SET(_n1)  (HWA_PINCTRL_PULLn(_n1) + 0x4)
+#define HWT_PINCTRL_PULLn_SET(_n1)  HWIO_32_WO
+#define HWN_PINCTRL_PULLn_SET(_n1)  PINCTRL_PULLn
+#define HWI_PINCTRL_PULLn_SET(_n1)  (_n1)
+#define HW_PINCTRL_PULLn_CLR(_n1)   HW(PINCTRL_PULLn_CLR(_n1))
+#define HWA_PINCTRL_PULLn_CLR(_n1)  (HWA_PINCTRL_PULLn(_n1) + 0x8)
+#define HWT_PINCTRL_PULLn_CLR(_n1)  HWIO_32_WO
+#define HWN_PINCTRL_PULLn_CLR(_n1)  PINCTRL_PULLn
+#define HWI_PINCTRL_PULLn_CLR(_n1)  (_n1)
+#define HW_PINCTRL_PULLn_TOG(_n1)   HW(PINCTRL_PULLn_TOG(_n1))
+#define HWA_PINCTRL_PULLn_TOG(_n1)  (HWA_PINCTRL_PULLn(_n1) + 0xc)
+#define HWT_PINCTRL_PULLn_TOG(_n1)  HWIO_32_WO
+#define HWN_PINCTRL_PULLn_TOG(_n1)  PINCTRL_PULLn
+#define HWI_PINCTRL_PULLn_TOG(_n1)  (_n1)
+#define BP_PINCTRL_PULLn_BITS       0
+#define BM_PINCTRL_PULLn_BITS       0xffffffff
+#define BF_PINCTRL_PULLn_BITS(v)    (((v) & 0xffffffff) << 0)
+#define BFM_PINCTRL_PULLn_BITS(v)   BM_PINCTRL_PULLn_BITS
+#define BF_PINCTRL_PULLn_BITS_V(e)  BF_PINCTRL_PULLn_BITS(BV_PINCTRL_PULLn_BITS__##e)
+#define BFM_PINCTRL_PULLn_BITS_V(v) BM_PINCTRL_PULLn_BITS
+
+#define HW_PINCTRL_DOUTn(_n1)       HW(PINCTRL_DOUTn(_n1))
+#define HWA_PINCTRL_DOUTn(_n1)      (0x80018000 + 0x400 + (_n1) * 0x10)
+#define HWT_PINCTRL_DOUTn(_n1)      HWIO_32_RW
+#define HWN_PINCTRL_DOUTn(_n1)      PINCTRL_DOUTn
+#define HWI_PINCTRL_DOUTn(_n1)      (_n1)
+#define HW_PINCTRL_DOUTn_SET(_n1)   HW(PINCTRL_DOUTn_SET(_n1))
+#define HWA_PINCTRL_DOUTn_SET(_n1)  (HWA_PINCTRL_DOUTn(_n1) + 0x4)
+#define HWT_PINCTRL_DOUTn_SET(_n1)  HWIO_32_WO
+#define HWN_PINCTRL_DOUTn_SET(_n1)  PINCTRL_DOUTn
+#define HWI_PINCTRL_DOUTn_SET(_n1)  (_n1)
+#define HW_PINCTRL_DOUTn_CLR(_n1)   HW(PINCTRL_DOUTn_CLR(_n1))
+#define HWA_PINCTRL_DOUTn_CLR(_n1)  (HWA_PINCTRL_DOUTn(_n1) + 0x8)
+#define HWT_PINCTRL_DOUTn_CLR(_n1)  HWIO_32_WO
+#define HWN_PINCTRL_DOUTn_CLR(_n1)  PINCTRL_DOUTn
+#define HWI_PINCTRL_DOUTn_CLR(_n1)  (_n1)
+#define HW_PINCTRL_DOUTn_TOG(_n1)   HW(PINCTRL_DOUTn_TOG(_n1))
+#define HWA_PINCTRL_DOUTn_TOG(_n1)  (HWA_PINCTRL_DOUTn(_n1) + 0xc)
+#define HWT_PINCTRL_DOUTn_TOG(_n1)  HWIO_32_WO
+#define HWN_PINCTRL_DOUTn_TOG(_n1)  PINCTRL_DOUTn
+#define HWI_PINCTRL_DOUTn_TOG(_n1)  (_n1)
+#define BP_PINCTRL_DOUTn_BITS       0
+#define BM_PINCTRL_DOUTn_BITS       0xffffffff
+#define BF_PINCTRL_DOUTn_BITS(v)    (((v) & 0xffffffff) << 0)
+#define BFM_PINCTRL_DOUTn_BITS(v)   BM_PINCTRL_DOUTn_BITS
+#define BF_PINCTRL_DOUTn_BITS_V(e)  BF_PINCTRL_DOUTn_BITS(BV_PINCTRL_DOUTn_BITS__##e)
+#define BFM_PINCTRL_DOUTn_BITS_V(v) BM_PINCTRL_DOUTn_BITS
+
+#define HW_PINCTRL_DINn(_n1)        HW(PINCTRL_DINn(_n1))
+#define HWA_PINCTRL_DINn(_n1)       (0x80018000 + 0x500 + (_n1) * 0x10)
+#define HWT_PINCTRL_DINn(_n1)       HWIO_32_RW
+#define HWN_PINCTRL_DINn(_n1)       PINCTRL_DINn
+#define HWI_PINCTRL_DINn(_n1)       (_n1)
+#define HW_PINCTRL_DINn_SET(_n1)    HW(PINCTRL_DINn_SET(_n1))
+#define HWA_PINCTRL_DINn_SET(_n1)   (HWA_PINCTRL_DINn(_n1) + 0x4)
+#define HWT_PINCTRL_DINn_SET(_n1)   HWIO_32_WO
+#define HWN_PINCTRL_DINn_SET(_n1)   PINCTRL_DINn
+#define HWI_PINCTRL_DINn_SET(_n1)   (_n1)
+#define HW_PINCTRL_DINn_CLR(_n1)    HW(PINCTRL_DINn_CLR(_n1))
+#define HWA_PINCTRL_DINn_CLR(_n1)   (HWA_PINCTRL_DINn(_n1) + 0x8)
+#define HWT_PINCTRL_DINn_CLR(_n1)   HWIO_32_WO
+#define HWN_PINCTRL_DINn_CLR(_n1)   PINCTRL_DINn
+#define HWI_PINCTRL_DINn_CLR(_n1)   (_n1)
+#define HW_PINCTRL_DINn_TOG(_n1)    HW(PINCTRL_DINn_TOG(_n1))
+#define HWA_PINCTRL_DINn_TOG(_n1)   (HWA_PINCTRL_DINn(_n1) + 0xc)
+#define HWT_PINCTRL_DINn_TOG(_n1)   HWIO_32_WO
+#define HWN_PINCTRL_DINn_TOG(_n1)   PINCTRL_DINn
+#define HWI_PINCTRL_DINn_TOG(_n1)   (_n1)
+#define BP_PINCTRL_DINn_BITS        0
+#define BM_PINCTRL_DINn_BITS        0xffffffff
+#define BF_PINCTRL_DINn_BITS(v)     (((v) & 0xffffffff) << 0)
+#define BFM_PINCTRL_DINn_BITS(v)    BM_PINCTRL_DINn_BITS
+#define BF_PINCTRL_DINn_BITS_V(e)   BF_PINCTRL_DINn_BITS(BV_PINCTRL_DINn_BITS__##e)
+#define BFM_PINCTRL_DINn_BITS_V(v)  BM_PINCTRL_DINn_BITS
+
+#define HW_PINCTRL_DOEn(_n1)        HW(PINCTRL_DOEn(_n1))
+#define HWA_PINCTRL_DOEn(_n1)       (0x80018000 + 0x600 + (_n1) * 0x10)
+#define HWT_PINCTRL_DOEn(_n1)       HWIO_32_RW
+#define HWN_PINCTRL_DOEn(_n1)       PINCTRL_DOEn
+#define HWI_PINCTRL_DOEn(_n1)       (_n1)
+#define HW_PINCTRL_DOEn_SET(_n1)    HW(PINCTRL_DOEn_SET(_n1))
+#define HWA_PINCTRL_DOEn_SET(_n1)   (HWA_PINCTRL_DOEn(_n1) + 0x4)
+#define HWT_PINCTRL_DOEn_SET(_n1)   HWIO_32_WO
+#define HWN_PINCTRL_DOEn_SET(_n1)   PINCTRL_DOEn
+#define HWI_PINCTRL_DOEn_SET(_n1)   (_n1)
+#define HW_PINCTRL_DOEn_CLR(_n1)    HW(PINCTRL_DOEn_CLR(_n1))
+#define HWA_PINCTRL_DOEn_CLR(_n1)   (HWA_PINCTRL_DOEn(_n1) + 0x8)
+#define HWT_PINCTRL_DOEn_CLR(_n1)   HWIO_32_WO
+#define HWN_PINCTRL_DOEn_CLR(_n1)   PINCTRL_DOEn
+#define HWI_PINCTRL_DOEn_CLR(_n1)   (_n1)
+#define HW_PINCTRL_DOEn_TOG(_n1)    HW(PINCTRL_DOEn_TOG(_n1))
+#define HWA_PINCTRL_DOEn_TOG(_n1)   (HWA_PINCTRL_DOEn(_n1) + 0xc)
+#define HWT_PINCTRL_DOEn_TOG(_n1)   HWIO_32_WO
+#define HWN_PINCTRL_DOEn_TOG(_n1)   PINCTRL_DOEn
+#define HWI_PINCTRL_DOEn_TOG(_n1)   (_n1)
+#define BP_PINCTRL_DOEn_BITS        0
+#define BM_PINCTRL_DOEn_BITS        0xffffffff
+#define BF_PINCTRL_DOEn_BITS(v)     (((v) & 0xffffffff) << 0)
+#define BFM_PINCTRL_DOEn_BITS(v)    BM_PINCTRL_DOEn_BITS
+#define BF_PINCTRL_DOEn_BITS_V(e)   BF_PINCTRL_DOEn_BITS(BV_PINCTRL_DOEn_BITS__##e)
+#define BFM_PINCTRL_DOEn_BITS_V(v)  BM_PINCTRL_DOEn_BITS
+
+#define HW_PINCTRL_PIN2IRQn(_n1)        HW(PINCTRL_PIN2IRQn(_n1))
+#define HWA_PINCTRL_PIN2IRQn(_n1)       (0x80018000 + 0x700 + (_n1) * 0x10)
+#define HWT_PINCTRL_PIN2IRQn(_n1)       HWIO_32_RW
+#define HWN_PINCTRL_PIN2IRQn(_n1)       PINCTRL_PIN2IRQn
+#define HWI_PINCTRL_PIN2IRQn(_n1)       (_n1)
+#define HW_PINCTRL_PIN2IRQn_SET(_n1)    HW(PINCTRL_PIN2IRQn_SET(_n1))
+#define HWA_PINCTRL_PIN2IRQn_SET(_n1)   (HWA_PINCTRL_PIN2IRQn(_n1) + 0x4)
+#define HWT_PINCTRL_PIN2IRQn_SET(_n1)   HWIO_32_WO
+#define HWN_PINCTRL_PIN2IRQn_SET(_n1)   PINCTRL_PIN2IRQn
+#define HWI_PINCTRL_PIN2IRQn_SET(_n1)   (_n1)
+#define HW_PINCTRL_PIN2IRQn_CLR(_n1)    HW(PINCTRL_PIN2IRQn_CLR(_n1))
+#define HWA_PINCTRL_PIN2IRQn_CLR(_n1)   (HWA_PINCTRL_PIN2IRQn(_n1) + 0x8)
+#define HWT_PINCTRL_PIN2IRQn_CLR(_n1)   HWIO_32_WO
+#define HWN_PINCTRL_PIN2IRQn_CLR(_n1)   PINCTRL_PIN2IRQn
+#define HWI_PINCTRL_PIN2IRQn_CLR(_n1)   (_n1)
+#define HW_PINCTRL_PIN2IRQn_TOG(_n1)    HW(PINCTRL_PIN2IRQn_TOG(_n1))
+#define HWA_PINCTRL_PIN2IRQn_TOG(_n1)   (HWA_PINCTRL_PIN2IRQn(_n1) + 0xc)
+#define HWT_PINCTRL_PIN2IRQn_TOG(_n1)   HWIO_32_WO
+#define HWN_PINCTRL_PIN2IRQn_TOG(_n1)   PINCTRL_PIN2IRQn
+#define HWI_PINCTRL_PIN2IRQn_TOG(_n1)   (_n1)
+#define BP_PINCTRL_PIN2IRQn_BITS        0
+#define BM_PINCTRL_PIN2IRQn_BITS        0xffffffff
+#define BF_PINCTRL_PIN2IRQn_BITS(v)     (((v) & 0xffffffff) << 0)
+#define BFM_PINCTRL_PIN2IRQn_BITS(v)    BM_PINCTRL_PIN2IRQn_BITS
+#define BF_PINCTRL_PIN2IRQn_BITS_V(e)   BF_PINCTRL_PIN2IRQn_BITS(BV_PINCTRL_PIN2IRQn_BITS__##e)
+#define BFM_PINCTRL_PIN2IRQn_BITS_V(v)  BM_PINCTRL_PIN2IRQn_BITS
+
+#define HW_PINCTRL_IRQENn(_n1)          HW(PINCTRL_IRQENn(_n1))
+#define HWA_PINCTRL_IRQENn(_n1)         (0x80018000 + 0x800 + (_n1) * 0x10)
+#define HWT_PINCTRL_IRQENn(_n1)         HWIO_32_RW
+#define HWN_PINCTRL_IRQENn(_n1)         PINCTRL_IRQENn
+#define HWI_PINCTRL_IRQENn(_n1)         (_n1)
+#define HW_PINCTRL_IRQENn_SET(_n1)      HW(PINCTRL_IRQENn_SET(_n1))
+#define HWA_PINCTRL_IRQENn_SET(_n1)     (HWA_PINCTRL_IRQENn(_n1) + 0x4)
+#define HWT_PINCTRL_IRQENn_SET(_n1)     HWIO_32_WO
+#define HWN_PINCTRL_IRQENn_SET(_n1)     PINCTRL_IRQENn
+#define HWI_PINCTRL_IRQENn_SET(_n1)     (_n1)
+#define HW_PINCTRL_IRQENn_CLR(_n1)      HW(PINCTRL_IRQENn_CLR(_n1))
+#define HWA_PINCTRL_IRQENn_CLR(_n1)     (HWA_PINCTRL_IRQENn(_n1) + 0x8)
+#define HWT_PINCTRL_IRQENn_CLR(_n1)     HWIO_32_WO
+#define HWN_PINCTRL_IRQENn_CLR(_n1)     PINCTRL_IRQENn
+#define HWI_PINCTRL_IRQENn_CLR(_n1)     (_n1)
+#define HW_PINCTRL_IRQENn_TOG(_n1)      HW(PINCTRL_IRQENn_TOG(_n1))
+#define HWA_PINCTRL_IRQENn_TOG(_n1)     (HWA_PINCTRL_IRQENn(_n1) + 0xc)
+#define HWT_PINCTRL_IRQENn_TOG(_n1)     HWIO_32_WO
+#define HWN_PINCTRL_IRQENn_TOG(_n1)     PINCTRL_IRQENn
+#define HWI_PINCTRL_IRQENn_TOG(_n1)     (_n1)
+#define BP_PINCTRL_IRQENn_BITS          0
+#define BM_PINCTRL_IRQENn_BITS          0xffffffff
+#define BF_PINCTRL_IRQENn_BITS(v)       (((v) & 0xffffffff) << 0)
+#define BFM_PINCTRL_IRQENn_BITS(v)      BM_PINCTRL_IRQENn_BITS
+#define BF_PINCTRL_IRQENn_BITS_V(e)     BF_PINCTRL_IRQENn_BITS(BV_PINCTRL_IRQENn_BITS__##e)
+#define BFM_PINCTRL_IRQENn_BITS_V(v)    BM_PINCTRL_IRQENn_BITS
+
+#define HW_PINCTRL_IRQLEVELn(_n1)       HW(PINCTRL_IRQLEVELn(_n1))
+#define HWA_PINCTRL_IRQLEVELn(_n1)      (0x80018000 + 0x900 + (_n1) * 0x10)
+#define HWT_PINCTRL_IRQLEVELn(_n1)      HWIO_32_RW
+#define HWN_PINCTRL_IRQLEVELn(_n1)      PINCTRL_IRQLEVELn
+#define HWI_PINCTRL_IRQLEVELn(_n1)      (_n1)
+#define HW_PINCTRL_IRQLEVELn_SET(_n1)   HW(PINCTRL_IRQLEVELn_SET(_n1))
+#define HWA_PINCTRL_IRQLEVELn_SET(_n1)  (HWA_PINCTRL_IRQLEVELn(_n1) + 0x4)
+#define HWT_PINCTRL_IRQLEVELn_SET(_n1)  HWIO_32_WO
+#define HWN_PINCTRL_IRQLEVELn_SET(_n1)  PINCTRL_IRQLEVELn
+#define HWI_PINCTRL_IRQLEVELn_SET(_n1)  (_n1)
+#define HW_PINCTRL_IRQLEVELn_CLR(_n1)   HW(PINCTRL_IRQLEVELn_CLR(_n1))
+#define HWA_PINCTRL_IRQLEVELn_CLR(_n1)  (HWA_PINCTRL_IRQLEVELn(_n1) + 0x8)
+#define HWT_PINCTRL_IRQLEVELn_CLR(_n1)  HWIO_32_WO
+#define HWN_PINCTRL_IRQLEVELn_CLR(_n1)  PINCTRL_IRQLEVELn
+#define HWI_PINCTRL_IRQLEVELn_CLR(_n1)  (_n1)
+#define HW_PINCTRL_IRQLEVELn_TOG(_n1)   HW(PINCTRL_IRQLEVELn_TOG(_n1))
+#define HWA_PINCTRL_IRQLEVELn_TOG(_n1)  (HWA_PINCTRL_IRQLEVELn(_n1) + 0xc)
+#define HWT_PINCTRL_IRQLEVELn_TOG(_n1)  HWIO_32_WO
+#define HWN_PINCTRL_IRQLEVELn_TOG(_n1)  PINCTRL_IRQLEVELn
+#define HWI_PINCTRL_IRQLEVELn_TOG(_n1)  (_n1)
+#define BP_PINCTRL_IRQLEVELn_BITS       0
+#define BM_PINCTRL_IRQLEVELn_BITS       0xffffffff
+#define BF_PINCTRL_IRQLEVELn_BITS(v)    (((v) & 0xffffffff) << 0)
+#define BFM_PINCTRL_IRQLEVELn_BITS(v)   BM_PINCTRL_IRQLEVELn_BITS
+#define BF_PINCTRL_IRQLEVELn_BITS_V(e)  BF_PINCTRL_IRQLEVELn_BITS(BV_PINCTRL_IRQLEVELn_BITS__##e)
+#define BFM_PINCTRL_IRQLEVELn_BITS_V(v) BM_PINCTRL_IRQLEVELn_BITS
+
+#define HW_PINCTRL_IRQPOLn(_n1)         HW(PINCTRL_IRQPOLn(_n1))
+#define HWA_PINCTRL_IRQPOLn(_n1)        (0x80018000 + 0xa00 + (_n1) * 0x10)
+#define HWT_PINCTRL_IRQPOLn(_n1)        HWIO_32_RW
+#define HWN_PINCTRL_IRQPOLn(_n1)        PINCTRL_IRQPOLn
+#define HWI_PINCTRL_IRQPOLn(_n1)        (_n1)
+#define HW_PINCTRL_IRQPOLn_SET(_n1)     HW(PINCTRL_IRQPOLn_SET(_n1))
+#define HWA_PINCTRL_IRQPOLn_SET(_n1)    (HWA_PINCTRL_IRQPOLn(_n1) + 0x4)
+#define HWT_PINCTRL_IRQPOLn_SET(_n1)    HWIO_32_WO
+#define HWN_PINCTRL_IRQPOLn_SET(_n1)    PINCTRL_IRQPOLn
+#define HWI_PINCTRL_IRQPOLn_SET(_n1)    (_n1)
+#define HW_PINCTRL_IRQPOLn_CLR(_n1)     HW(PINCTRL_IRQPOLn_CLR(_n1))
+#define HWA_PINCTRL_IRQPOLn_CLR(_n1)    (HWA_PINCTRL_IRQPOLn(_n1) + 0x8)
+#define HWT_PINCTRL_IRQPOLn_CLR(_n1)    HWIO_32_WO
+#define HWN_PINCTRL_IRQPOLn_CLR(_n1)    PINCTRL_IRQPOLn
+#define HWI_PINCTRL_IRQPOLn_CLR(_n1)    (_n1)
+#define HW_PINCTRL_IRQPOLn_TOG(_n1)     HW(PINCTRL_IRQPOLn_TOG(_n1))
+#define HWA_PINCTRL_IRQPOLn_TOG(_n1)    (HWA_PINCTRL_IRQPOLn(_n1) + 0xc)
+#define HWT_PINCTRL_IRQPOLn_TOG(_n1)    HWIO_32_WO
+#define HWN_PINCTRL_IRQPOLn_TOG(_n1)    PINCTRL_IRQPOLn
+#define HWI_PINCTRL_IRQPOLn_TOG(_n1)    (_n1)
+#define BP_PINCTRL_IRQPOLn_BITS         0
+#define BM_PINCTRL_IRQPOLn_BITS         0xffffffff
+#define BF_PINCTRL_IRQPOLn_BITS(v)      (((v) & 0xffffffff) << 0)
+#define BFM_PINCTRL_IRQPOLn_BITS(v)     BM_PINCTRL_IRQPOLn_BITS
+#define BF_PINCTRL_IRQPOLn_BITS_V(e)    BF_PINCTRL_IRQPOLn_BITS(BV_PINCTRL_IRQPOLn_BITS__##e)
+#define BFM_PINCTRL_IRQPOLn_BITS_V(v)   BM_PINCTRL_IRQPOLn_BITS
+
+#define HW_PINCTRL_IRQSTATn(_n1)        HW(PINCTRL_IRQSTATn(_n1))
+#define HWA_PINCTRL_IRQSTATn(_n1)       (0x80018000 + 0xb00 + (_n1) * 0x10)
+#define HWT_PINCTRL_IRQSTATn(_n1)       HWIO_32_RW
+#define HWN_PINCTRL_IRQSTATn(_n1)       PINCTRL_IRQSTATn
+#define HWI_PINCTRL_IRQSTATn(_n1)       (_n1)
+#define HW_PINCTRL_IRQSTATn_SET(_n1)    HW(PINCTRL_IRQSTATn_SET(_n1))
+#define HWA_PINCTRL_IRQSTATn_SET(_n1)   (HWA_PINCTRL_IRQSTATn(_n1) + 0x4)
+#define HWT_PINCTRL_IRQSTATn_SET(_n1)   HWIO_32_WO
+#define HWN_PINCTRL_IRQSTATn_SET(_n1)   PINCTRL_IRQSTATn
+#define HWI_PINCTRL_IRQSTATn_SET(_n1)   (_n1)
+#define HW_PINCTRL_IRQSTATn_CLR(_n1)    HW(PINCTRL_IRQSTATn_CLR(_n1))
+#define HWA_PINCTRL_IRQSTATn_CLR(_n1)   (HWA_PINCTRL_IRQSTATn(_n1) + 0x8)
+#define HWT_PINCTRL_IRQSTATn_CLR(_n1)   HWIO_32_WO
+#define HWN_PINCTRL_IRQSTATn_CLR(_n1)   PINCTRL_IRQSTATn
+#define HWI_PINCTRL_IRQSTATn_CLR(_n1)   (_n1)
+#define HW_PINCTRL_IRQSTATn_TOG(_n1)    HW(PINCTRL_IRQSTATn_TOG(_n1))
+#define HWA_PINCTRL_IRQSTATn_TOG(_n1)   (HWA_PINCTRL_IRQSTATn(_n1) + 0xc)
+#define HWT_PINCTRL_IRQSTATn_TOG(_n1)   HWIO_32_WO
+#define HWN_PINCTRL_IRQSTATn_TOG(_n1)   PINCTRL_IRQSTATn
+#define HWI_PINCTRL_IRQSTATn_TOG(_n1)   (_n1)
+#define BP_PINCTRL_IRQSTATn_BITS        0
+#define BM_PINCTRL_IRQSTATn_BITS        0xffffffff
+#define BF_PINCTRL_IRQSTATn_BITS(v)     (((v) & 0xffffffff) << 0)
+#define BFM_PINCTRL_IRQSTATn_BITS(v)    BM_PINCTRL_IRQSTATn_BITS
+#define BF_PINCTRL_IRQSTATn_BITS_V(e)   BF_PINCTRL_IRQSTATn_BITS(BV_PINCTRL_IRQSTATn_BITS__##e)
+#define BFM_PINCTRL_IRQSTATn_BITS_V(v)  BM_PINCTRL_IRQSTATn_BITS
+
+#endif /* __HEADERGEN_STMP3700_PINCTRL_H__*/
diff --git a/firmware/target/arm/imx233/regs/stmp3700/power.h b/firmware/target/arm/imx233/regs/stmp3700/power.h
new file mode 100644
index 0000000000..1dcffbfd88
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3700/power.h
@@ -0,0 +1,1063 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * stmp3700 version: 2.4.0
+ * stmp3700 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_STMP3700_POWER_H__
+#define __HEADERGEN_STMP3700_POWER_H__
+
+#define HW_POWER_CTRL                               HW(POWER_CTRL)
+#define HWA_POWER_CTRL                              (0x80044000 + 0x0)
+#define HWT_POWER_CTRL                              HWIO_32_RW
+#define HWN_POWER_CTRL                              POWER_CTRL
+#define HWI_POWER_CTRL                              
+#define HW_POWER_CTRL_SET                           HW(POWER_CTRL_SET)
+#define HWA_POWER_CTRL_SET                          (HWA_POWER_CTRL + 0x4)
+#define HWT_POWER_CTRL_SET                          HWIO_32_WO
+#define HWN_POWER_CTRL_SET                          POWER_CTRL
+#define HWI_POWER_CTRL_SET                          
+#define HW_POWER_CTRL_CLR                           HW(POWER_CTRL_CLR)
+#define HWA_POWER_CTRL_CLR                          (HWA_POWER_CTRL + 0x8)
+#define HWT_POWER_CTRL_CLR                          HWIO_32_WO
+#define HWN_POWER_CTRL_CLR                          POWER_CTRL
+#define HWI_POWER_CTRL_CLR                          
+#define HW_POWER_CTRL_TOG                           HW(POWER_CTRL_TOG)
+#define HWA_POWER_CTRL_TOG                          (HWA_POWER_CTRL + 0xc)
+#define HWT_POWER_CTRL_TOG                          HWIO_32_WO
+#define HWN_POWER_CTRL_TOG                          POWER_CTRL
+#define HWI_POWER_CTRL_TOG                          
+#define BP_POWER_CTRL_CLKGATE                       30
+#define BM_POWER_CTRL_CLKGATE                       0x40000000
+#define BF_POWER_CTRL_CLKGATE(v)                    (((v) & 0x1) << 30)
+#define BFM_POWER_CTRL_CLKGATE(v)                   BM_POWER_CTRL_CLKGATE
+#define BF_POWER_CTRL_CLKGATE_V(e)                  BF_POWER_CTRL_CLKGATE(BV_POWER_CTRL_CLKGATE__##e)
+#define BFM_POWER_CTRL_CLKGATE_V(v)                 BM_POWER_CTRL_CLKGATE
+#define BP_POWER_CTRL_PSWITCH_IRQ                   22
+#define BM_POWER_CTRL_PSWITCH_IRQ                   0x400000
+#define BF_POWER_CTRL_PSWITCH_IRQ(v)                (((v) & 0x1) << 22)
+#define BFM_POWER_CTRL_PSWITCH_IRQ(v)               BM_POWER_CTRL_PSWITCH_IRQ
+#define BF_POWER_CTRL_PSWITCH_IRQ_V(e)              BF_POWER_CTRL_PSWITCH_IRQ(BV_POWER_CTRL_PSWITCH_IRQ__##e)
+#define BFM_POWER_CTRL_PSWITCH_IRQ_V(v)             BM_POWER_CTRL_PSWITCH_IRQ
+#define BP_POWER_CTRL_PSWITCH_IRQ_SRC               21
+#define BM_POWER_CTRL_PSWITCH_IRQ_SRC               0x200000
+#define BF_POWER_CTRL_PSWITCH_IRQ_SRC(v)            (((v) & 0x1) << 21)
+#define BFM_POWER_CTRL_PSWITCH_IRQ_SRC(v)           BM_POWER_CTRL_PSWITCH_IRQ_SRC
+#define BF_POWER_CTRL_PSWITCH_IRQ_SRC_V(e)          BF_POWER_CTRL_PSWITCH_IRQ_SRC(BV_POWER_CTRL_PSWITCH_IRQ_SRC__##e)
+#define BFM_POWER_CTRL_PSWITCH_IRQ_SRC_V(v)         BM_POWER_CTRL_PSWITCH_IRQ_SRC
+#define BP_POWER_CTRL_POLARITY_PSWITCH              20
+#define BM_POWER_CTRL_POLARITY_PSWITCH              0x100000
+#define BF_POWER_CTRL_POLARITY_PSWITCH(v)           (((v) & 0x1) << 20)
+#define BFM_POWER_CTRL_POLARITY_PSWITCH(v)          BM_POWER_CTRL_POLARITY_PSWITCH
+#define BF_POWER_CTRL_POLARITY_PSWITCH_V(e)         BF_POWER_CTRL_POLARITY_PSWITCH(BV_POWER_CTRL_POLARITY_PSWITCH__##e)
+#define BFM_POWER_CTRL_POLARITY_PSWITCH_V(v)        BM_POWER_CTRL_POLARITY_PSWITCH
+#define BP_POWER_CTRL_ENIRQ_PSWITCH                 19
+#define BM_POWER_CTRL_ENIRQ_PSWITCH                 0x80000
+#define BF_POWER_CTRL_ENIRQ_PSWITCH(v)              (((v) & 0x1) << 19)
+#define BFM_POWER_CTRL_ENIRQ_PSWITCH(v)             BM_POWER_CTRL_ENIRQ_PSWITCH
+#define BF_POWER_CTRL_ENIRQ_PSWITCH_V(e)            BF_POWER_CTRL_ENIRQ_PSWITCH(BV_POWER_CTRL_ENIRQ_PSWITCH__##e)
+#define BFM_POWER_CTRL_ENIRQ_PSWITCH_V(v)           BM_POWER_CTRL_ENIRQ_PSWITCH
+#define BP_POWER_CTRL_POLARITY_LINREG_OK            18
+#define BM_POWER_CTRL_POLARITY_LINREG_OK            0x40000
+#define BF_POWER_CTRL_POLARITY_LINREG_OK(v)         (((v) & 0x1) << 18)
+#define BFM_POWER_CTRL_POLARITY_LINREG_OK(v)        BM_POWER_CTRL_POLARITY_LINREG_OK
+#define BF_POWER_CTRL_POLARITY_LINREG_OK_V(e)       BF_POWER_CTRL_POLARITY_LINREG_OK(BV_POWER_CTRL_POLARITY_LINREG_OK__##e)
+#define BFM_POWER_CTRL_POLARITY_LINREG_OK_V(v)      BM_POWER_CTRL_POLARITY_LINREG_OK
+#define BP_POWER_CTRL_LINREG_OK_IRQ                 17
+#define BM_POWER_CTRL_LINREG_OK_IRQ                 0x20000
+#define BF_POWER_CTRL_LINREG_OK_IRQ(v)              (((v) & 0x1) << 17)
+#define BFM_POWER_CTRL_LINREG_OK_IRQ(v)             BM_POWER_CTRL_LINREG_OK_IRQ
+#define BF_POWER_CTRL_LINREG_OK_IRQ_V(e)            BF_POWER_CTRL_LINREG_OK_IRQ(BV_POWER_CTRL_LINREG_OK_IRQ__##e)
+#define BFM_POWER_CTRL_LINREG_OK_IRQ_V(v)           BM_POWER_CTRL_LINREG_OK_IRQ
+#define BP_POWER_CTRL_ENIRQ_LINREG_OK               16
+#define BM_POWER_CTRL_ENIRQ_LINREG_OK               0x10000
+#define BF_POWER_CTRL_ENIRQ_LINREG_OK(v)            (((v) & 0x1) << 16)
+#define BFM_POWER_CTRL_ENIRQ_LINREG_OK(v)           BM_POWER_CTRL_ENIRQ_LINREG_OK
+#define BF_POWER_CTRL_ENIRQ_LINREG_OK_V(e)          BF_POWER_CTRL_ENIRQ_LINREG_OK(BV_POWER_CTRL_ENIRQ_LINREG_OK__##e)
+#define BFM_POWER_CTRL_ENIRQ_LINREG_OK_V(v)         BM_POWER_CTRL_ENIRQ_LINREG_OK
+#define BP_POWER_CTRL_DC_OK_IRQ                     15
+#define BM_POWER_CTRL_DC_OK_IRQ                     0x8000
+#define BF_POWER_CTRL_DC_OK_IRQ(v)                  (((v) & 0x1) << 15)
+#define BFM_POWER_CTRL_DC_OK_IRQ(v)                 BM_POWER_CTRL_DC_OK_IRQ
+#define BF_POWER_CTRL_DC_OK_IRQ_V(e)                BF_POWER_CTRL_DC_OK_IRQ(BV_POWER_CTRL_DC_OK_IRQ__##e)
+#define BFM_POWER_CTRL_DC_OK_IRQ_V(v)               BM_POWER_CTRL_DC_OK_IRQ
+#define BP_POWER_CTRL_ENIRQ_DC_OK                   14
+#define BM_POWER_CTRL_ENIRQ_DC_OK                   0x4000
+#define BF_POWER_CTRL_ENIRQ_DC_OK(v)                (((v) & 0x1) << 14)
+#define BFM_POWER_CTRL_ENIRQ_DC_OK(v)               BM_POWER_CTRL_ENIRQ_DC_OK
+#define BF_POWER_CTRL_ENIRQ_DC_OK_V(e)              BF_POWER_CTRL_ENIRQ_DC_OK(BV_POWER_CTRL_ENIRQ_DC_OK__##e)
+#define BFM_POWER_CTRL_ENIRQ_DC_OK_V(v)             BM_POWER_CTRL_ENIRQ_DC_OK
+#define BP_POWER_CTRL_BATT_BO_IRQ                   13
+#define BM_POWER_CTRL_BATT_BO_IRQ                   0x2000
+#define BF_POWER_CTRL_BATT_BO_IRQ(v)                (((v) & 0x1) << 13)
+#define BFM_POWER_CTRL_BATT_BO_IRQ(v)               BM_POWER_CTRL_BATT_BO_IRQ
+#define BF_POWER_CTRL_BATT_BO_IRQ_V(e)              BF_POWER_CTRL_BATT_BO_IRQ(BV_POWER_CTRL_BATT_BO_IRQ__##e)
+#define BFM_POWER_CTRL_BATT_BO_IRQ_V(v)             BM_POWER_CTRL_BATT_BO_IRQ
+#define BP_POWER_CTRL_ENIRQBATT_BO                  12
+#define BM_POWER_CTRL_ENIRQBATT_BO                  0x1000
+#define BF_POWER_CTRL_ENIRQBATT_BO(v)               (((v) & 0x1) << 12)
+#define BFM_POWER_CTRL_ENIRQBATT_BO(v)              BM_POWER_CTRL_ENIRQBATT_BO
+#define BF_POWER_CTRL_ENIRQBATT_BO_V(e)             BF_POWER_CTRL_ENIRQBATT_BO(BV_POWER_CTRL_ENIRQBATT_BO__##e)
+#define BFM_POWER_CTRL_ENIRQBATT_BO_V(v)            BM_POWER_CTRL_ENIRQBATT_BO
+#define BP_POWER_CTRL_VDDIO_BO_IRQ                  11
+#define BM_POWER_CTRL_VDDIO_BO_IRQ                  0x800
+#define BF_POWER_CTRL_VDDIO_BO_IRQ(v)               (((v) & 0x1) << 11)
+#define BFM_POWER_CTRL_VDDIO_BO_IRQ(v)              BM_POWER_CTRL_VDDIO_BO_IRQ
+#define BF_POWER_CTRL_VDDIO_BO_IRQ_V(e)             BF_POWER_CTRL_VDDIO_BO_IRQ(BV_POWER_CTRL_VDDIO_BO_IRQ__##e)
+#define BFM_POWER_CTRL_VDDIO_BO_IRQ_V(v)            BM_POWER_CTRL_VDDIO_BO_IRQ
+#define BP_POWER_CTRL_ENIRQ_VDDIO_BO                10
+#define BM_POWER_CTRL_ENIRQ_VDDIO_BO                0x400
+#define BF_POWER_CTRL_ENIRQ_VDDIO_BO(v)             (((v) & 0x1) << 10)
+#define BFM_POWER_CTRL_ENIRQ_VDDIO_BO(v)            BM_POWER_CTRL_ENIRQ_VDDIO_BO
+#define BF_POWER_CTRL_ENIRQ_VDDIO_BO_V(e)           BF_POWER_CTRL_ENIRQ_VDDIO_BO(BV_POWER_CTRL_ENIRQ_VDDIO_BO__##e)
+#define BFM_POWER_CTRL_ENIRQ_VDDIO_BO_V(v)          BM_POWER_CTRL_ENIRQ_VDDIO_BO
+#define BP_POWER_CTRL_VDDA_BO_IRQ                   9
+#define BM_POWER_CTRL_VDDA_BO_IRQ                   0x200
+#define BF_POWER_CTRL_VDDA_BO_IRQ(v)                (((v) & 0x1) << 9)
+#define BFM_POWER_CTRL_VDDA_BO_IRQ(v)               BM_POWER_CTRL_VDDA_BO_IRQ
+#define BF_POWER_CTRL_VDDA_BO_IRQ_V(e)              BF_POWER_CTRL_VDDA_BO_IRQ(BV_POWER_CTRL_VDDA_BO_IRQ__##e)
+#define BFM_POWER_CTRL_VDDA_BO_IRQ_V(v)             BM_POWER_CTRL_VDDA_BO_IRQ
+#define BP_POWER_CTRL_ENIRQ_VDDA_BO                 8
+#define BM_POWER_CTRL_ENIRQ_VDDA_BO                 0x100
+#define BF_POWER_CTRL_ENIRQ_VDDA_BO(v)              (((v) & 0x1) << 8)
+#define BFM_POWER_CTRL_ENIRQ_VDDA_BO(v)             BM_POWER_CTRL_ENIRQ_VDDA_BO
+#define BF_POWER_CTRL_ENIRQ_VDDA_BO_V(e)            BF_POWER_CTRL_ENIRQ_VDDA_BO(BV_POWER_CTRL_ENIRQ_VDDA_BO__##e)
+#define BFM_POWER_CTRL_ENIRQ_VDDA_BO_V(v)           BM_POWER_CTRL_ENIRQ_VDDA_BO
+#define BP_POWER_CTRL_VDDD_BO_IRQ                   7
+#define BM_POWER_CTRL_VDDD_BO_IRQ                   0x80
+#define BF_POWER_CTRL_VDDD_BO_IRQ(v)                (((v) & 0x1) << 7)
+#define BFM_POWER_CTRL_VDDD_BO_IRQ(v)               BM_POWER_CTRL_VDDD_BO_IRQ
+#define BF_POWER_CTRL_VDDD_BO_IRQ_V(e)              BF_POWER_CTRL_VDDD_BO_IRQ(BV_POWER_CTRL_VDDD_BO_IRQ__##e)
+#define BFM_POWER_CTRL_VDDD_BO_IRQ_V(v)             BM_POWER_CTRL_VDDD_BO_IRQ
+#define BP_POWER_CTRL_ENIRQ_VDDD_BO                 6
+#define BM_POWER_CTRL_ENIRQ_VDDD_BO                 0x40
+#define BF_POWER_CTRL_ENIRQ_VDDD_BO(v)              (((v) & 0x1) << 6)
+#define BFM_POWER_CTRL_ENIRQ_VDDD_BO(v)             BM_POWER_CTRL_ENIRQ_VDDD_BO
+#define BF_POWER_CTRL_ENIRQ_VDDD_BO_V(e)            BF_POWER_CTRL_ENIRQ_VDDD_BO(BV_POWER_CTRL_ENIRQ_VDDD_BO__##e)
+#define BFM_POWER_CTRL_ENIRQ_VDDD_BO_V(v)           BM_POWER_CTRL_ENIRQ_VDDD_BO
+#define BP_POWER_CTRL_POLARITY_VBUSVALID            5
+#define BM_POWER_CTRL_POLARITY_VBUSVALID            0x20
+#define BF_POWER_CTRL_POLARITY_VBUSVALID(v)         (((v) & 0x1) << 5)
+#define BFM_POWER_CTRL_POLARITY_VBUSVALID(v)        BM_POWER_CTRL_POLARITY_VBUSVALID
+#define BF_POWER_CTRL_POLARITY_VBUSVALID_V(e)       BF_POWER_CTRL_POLARITY_VBUSVALID(BV_POWER_CTRL_POLARITY_VBUSVALID__##e)
+#define BFM_POWER_CTRL_POLARITY_VBUSVALID_V(v)      BM_POWER_CTRL_POLARITY_VBUSVALID
+#define BP_POWER_CTRL_VBUSVALID_IRQ                 4
+#define BM_POWER_CTRL_VBUSVALID_IRQ                 0x10
+#define BF_POWER_CTRL_VBUSVALID_IRQ(v)              (((v) & 0x1) << 4)
+#define BFM_POWER_CTRL_VBUSVALID_IRQ(v)             BM_POWER_CTRL_VBUSVALID_IRQ
+#define BF_POWER_CTRL_VBUSVALID_IRQ_V(e)            BF_POWER_CTRL_VBUSVALID_IRQ(BV_POWER_CTRL_VBUSVALID_IRQ__##e)
+#define BFM_POWER_CTRL_VBUSVALID_IRQ_V(v)           BM_POWER_CTRL_VBUSVALID_IRQ
+#define BP_POWER_CTRL_ENIRQ_VBUS_VALID              3
+#define BM_POWER_CTRL_ENIRQ_VBUS_VALID              0x8
+#define BF_POWER_CTRL_ENIRQ_VBUS_VALID(v)           (((v) & 0x1) << 3)
+#define BFM_POWER_CTRL_ENIRQ_VBUS_VALID(v)          BM_POWER_CTRL_ENIRQ_VBUS_VALID
+#define BF_POWER_CTRL_ENIRQ_VBUS_VALID_V(e)         BF_POWER_CTRL_ENIRQ_VBUS_VALID(BV_POWER_CTRL_ENIRQ_VBUS_VALID__##e)
+#define BFM_POWER_CTRL_ENIRQ_VBUS_VALID_V(v)        BM_POWER_CTRL_ENIRQ_VBUS_VALID
+#define BP_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO       2
+#define BM_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO       0x4
+#define BF_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO(v)    (((v) & 0x1) << 2)
+#define BFM_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO(v)   BM_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO
+#define BF_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO_V(e)  BF_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO(BV_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO__##e)
+#define BFM_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO_V(v) BM_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO
+#define BP_POWER_CTRL_VDD5V_GT_VDDIO_IRQ            1
+#define BM_POWER_CTRL_VDD5V_GT_VDDIO_IRQ            0x2
+#define BF_POWER_CTRL_VDD5V_GT_VDDIO_IRQ(v)         (((v) & 0x1) << 1)
+#define BFM_POWER_CTRL_VDD5V_GT_VDDIO_IRQ(v)        BM_POWER_CTRL_VDD5V_GT_VDDIO_IRQ
+#define BF_POWER_CTRL_VDD5V_GT_VDDIO_IRQ_V(e)       BF_POWER_CTRL_VDD5V_GT_VDDIO_IRQ(BV_POWER_CTRL_VDD5V_GT_VDDIO_IRQ__##e)
+#define BFM_POWER_CTRL_VDD5V_GT_VDDIO_IRQ_V(v)      BM_POWER_CTRL_VDD5V_GT_VDDIO_IRQ
+#define BP_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO          0
+#define BM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO          0x1
+#define BF_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO(v)       (((v) & 0x1) << 0)
+#define BFM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO(v)      BM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO
+#define BF_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO_V(e)     BF_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO(BV_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO__##e)
+#define BFM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO_V(v)    BM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO
+
+#define HW_POWER_5VCTRL                             HW(POWER_5VCTRL)
+#define HWA_POWER_5VCTRL                            (0x80044000 + 0x10)
+#define HWT_POWER_5VCTRL                            HWIO_32_RW
+#define HWN_POWER_5VCTRL                            POWER_5VCTRL
+#define HWI_POWER_5VCTRL                            
+#define HW_POWER_5VCTRL_SET                         HW(POWER_5VCTRL_SET)
+#define HWA_POWER_5VCTRL_SET                        (HWA_POWER_5VCTRL + 0x4)
+#define HWT_POWER_5VCTRL_SET                        HWIO_32_WO
+#define HWN_POWER_5VCTRL_SET                        POWER_5VCTRL
+#define HWI_POWER_5VCTRL_SET                        
+#define HW_POWER_5VCTRL_CLR                         HW(POWER_5VCTRL_CLR)
+#define HWA_POWER_5VCTRL_CLR                        (HWA_POWER_5VCTRL + 0x8)
+#define HWT_POWER_5VCTRL_CLR                        HWIO_32_WO
+#define HWN_POWER_5VCTRL_CLR                        POWER_5VCTRL
+#define HWI_POWER_5VCTRL_CLR                        
+#define HW_POWER_5VCTRL_TOG                         HW(POWER_5VCTRL_TOG)
+#define HWA_POWER_5VCTRL_TOG                        (HWA_POWER_5VCTRL + 0xc)
+#define HWT_POWER_5VCTRL_TOG                        HWIO_32_WO
+#define HWN_POWER_5VCTRL_TOG                        POWER_5VCTRL
+#define HWI_POWER_5VCTRL_TOG                        
+#define BP_POWER_5VCTRL_VBUSVALID_TRSH              10
+#define BM_POWER_5VCTRL_VBUSVALID_TRSH              0xc00
+#define BF_POWER_5VCTRL_VBUSVALID_TRSH(v)           (((v) & 0x3) << 10)
+#define BFM_POWER_5VCTRL_VBUSVALID_TRSH(v)          BM_POWER_5VCTRL_VBUSVALID_TRSH
+#define BF_POWER_5VCTRL_VBUSVALID_TRSH_V(e)         BF_POWER_5VCTRL_VBUSVALID_TRSH(BV_POWER_5VCTRL_VBUSVALID_TRSH__##e)
+#define BFM_POWER_5VCTRL_VBUSVALID_TRSH_V(v)        BM_POWER_5VCTRL_VBUSVALID_TRSH
+#define BP_POWER_5VCTRL_PWDN_5VBRNOUT               8
+#define BM_POWER_5VCTRL_PWDN_5VBRNOUT               0x100
+#define BF_POWER_5VCTRL_PWDN_5VBRNOUT(v)            (((v) & 0x1) << 8)
+#define BFM_POWER_5VCTRL_PWDN_5VBRNOUT(v)           BM_POWER_5VCTRL_PWDN_5VBRNOUT
+#define BF_POWER_5VCTRL_PWDN_5VBRNOUT_V(e)          BF_POWER_5VCTRL_PWDN_5VBRNOUT(BV_POWER_5VCTRL_PWDN_5VBRNOUT__##e)
+#define BFM_POWER_5VCTRL_PWDN_5VBRNOUT_V(v)         BM_POWER_5VCTRL_PWDN_5VBRNOUT
+#define BP_POWER_5VCTRL_ENABLE_ILIMIT               7
+#define BM_POWER_5VCTRL_ENABLE_ILIMIT               0x80
+#define BF_POWER_5VCTRL_ENABLE_ILIMIT(v)            (((v) & 0x1) << 7)
+#define BFM_POWER_5VCTRL_ENABLE_ILIMIT(v)           BM_POWER_5VCTRL_ENABLE_ILIMIT
+#define BF_POWER_5VCTRL_ENABLE_ILIMIT_V(e)          BF_POWER_5VCTRL_ENABLE_ILIMIT(BV_POWER_5VCTRL_ENABLE_ILIMIT__##e)
+#define BFM_POWER_5VCTRL_ENABLE_ILIMIT_V(v)         BM_POWER_5VCTRL_ENABLE_ILIMIT
+#define BP_POWER_5VCTRL_DCDC_XFER                   6
+#define BM_POWER_5VCTRL_DCDC_XFER                   0x40
+#define BF_POWER_5VCTRL_DCDC_XFER(v)                (((v) & 0x1) << 6)
+#define BFM_POWER_5VCTRL_DCDC_XFER(v)               BM_POWER_5VCTRL_DCDC_XFER
+#define BF_POWER_5VCTRL_DCDC_XFER_V(e)              BF_POWER_5VCTRL_DCDC_XFER(BV_POWER_5VCTRL_DCDC_XFER__##e)
+#define BFM_POWER_5VCTRL_DCDC_XFER_V(v)             BM_POWER_5VCTRL_DCDC_XFER
+#define BP_POWER_5VCTRL_EN_BATT_PULLDN              5
+#define BM_POWER_5VCTRL_EN_BATT_PULLDN              0x20
+#define BF_POWER_5VCTRL_EN_BATT_PULLDN(v)           (((v) & 0x1) << 5)
+#define BFM_POWER_5VCTRL_EN_BATT_PULLDN(v)          BM_POWER_5VCTRL_EN_BATT_PULLDN
+#define BF_POWER_5VCTRL_EN_BATT_PULLDN_V(e)         BF_POWER_5VCTRL_EN_BATT_PULLDN(BV_POWER_5VCTRL_EN_BATT_PULLDN__##e)
+#define BFM_POWER_5VCTRL_EN_BATT_PULLDN_V(v)        BM_POWER_5VCTRL_EN_BATT_PULLDN
+#define BP_POWER_5VCTRL_VBUSVALID_5VDETECT          4
+#define BM_POWER_5VCTRL_VBUSVALID_5VDETECT          0x10
+#define BF_POWER_5VCTRL_VBUSVALID_5VDETECT(v)       (((v) & 0x1) << 4)
+#define BFM_POWER_5VCTRL_VBUSVALID_5VDETECT(v)      BM_POWER_5VCTRL_VBUSVALID_5VDETECT
+#define BF_POWER_5VCTRL_VBUSVALID_5VDETECT_V(e)     BF_POWER_5VCTRL_VBUSVALID_5VDETECT(BV_POWER_5VCTRL_VBUSVALID_5VDETECT__##e)
+#define BFM_POWER_5VCTRL_VBUSVALID_5VDETECT_V(v)    BM_POWER_5VCTRL_VBUSVALID_5VDETECT
+#define BP_POWER_5VCTRL_VBUSVALID_TO_B              3
+#define BM_POWER_5VCTRL_VBUSVALID_TO_B              0x8
+#define BF_POWER_5VCTRL_VBUSVALID_TO_B(v)           (((v) & 0x1) << 3)
+#define BFM_POWER_5VCTRL_VBUSVALID_TO_B(v)          BM_POWER_5VCTRL_VBUSVALID_TO_B
+#define BF_POWER_5VCTRL_VBUSVALID_TO_B_V(e)         BF_POWER_5VCTRL_VBUSVALID_TO_B(BV_POWER_5VCTRL_VBUSVALID_TO_B__##e)
+#define BFM_POWER_5VCTRL_VBUSVALID_TO_B_V(v)        BM_POWER_5VCTRL_VBUSVALID_TO_B
+#define BP_POWER_5VCTRL_ILIMIT_EQ_ZERO              2
+#define BM_POWER_5VCTRL_ILIMIT_EQ_ZERO              0x4
+#define BF_POWER_5VCTRL_ILIMIT_EQ_ZERO(v)           (((v) & 0x1) << 2)
+#define BFM_POWER_5VCTRL_ILIMIT_EQ_ZERO(v)          BM_POWER_5VCTRL_ILIMIT_EQ_ZERO
+#define BF_POWER_5VCTRL_ILIMIT_EQ_ZERO_V(e)         BF_POWER_5VCTRL_ILIMIT_EQ_ZERO(BV_POWER_5VCTRL_ILIMIT_EQ_ZERO__##e)
+#define BFM_POWER_5VCTRL_ILIMIT_EQ_ZERO_V(v)        BM_POWER_5VCTRL_ILIMIT_EQ_ZERO
+#define BP_POWER_5VCTRL_OTG_PWRUP_CMPS              1
+#define BM_POWER_5VCTRL_OTG_PWRUP_CMPS              0x2
+#define BF_POWER_5VCTRL_OTG_PWRUP_CMPS(v)           (((v) & 0x1) << 1)
+#define BFM_POWER_5VCTRL_OTG_PWRUP_CMPS(v)          BM_POWER_5VCTRL_OTG_PWRUP_CMPS
+#define BF_POWER_5VCTRL_OTG_PWRUP_CMPS_V(e)         BF_POWER_5VCTRL_OTG_PWRUP_CMPS(BV_POWER_5VCTRL_OTG_PWRUP_CMPS__##e)
+#define BFM_POWER_5VCTRL_OTG_PWRUP_CMPS_V(v)        BM_POWER_5VCTRL_OTG_PWRUP_CMPS
+#define BP_POWER_5VCTRL_ENABLE_DCDC                 0
+#define BM_POWER_5VCTRL_ENABLE_DCDC                 0x1
+#define BF_POWER_5VCTRL_ENABLE_DCDC(v)              (((v) & 0x1) << 0)
+#define BFM_POWER_5VCTRL_ENABLE_DCDC(v)             BM_POWER_5VCTRL_ENABLE_DCDC
+#define BF_POWER_5VCTRL_ENABLE_DCDC_V(e)            BF_POWER_5VCTRL_ENABLE_DCDC(BV_POWER_5VCTRL_ENABLE_DCDC__##e)
+#define BFM_POWER_5VCTRL_ENABLE_DCDC_V(v)           BM_POWER_5VCTRL_ENABLE_DCDC
+
+#define HW_POWER_MINPWR                     HW(POWER_MINPWR)
+#define HWA_POWER_MINPWR                    (0x80044000 + 0x20)
+#define HWT_POWER_MINPWR                    HWIO_32_RW
+#define HWN_POWER_MINPWR                    POWER_MINPWR
+#define HWI_POWER_MINPWR                    
+#define HW_POWER_MINPWR_SET                 HW(POWER_MINPWR_SET)
+#define HWA_POWER_MINPWR_SET                (HWA_POWER_MINPWR + 0x4)
+#define HWT_POWER_MINPWR_SET                HWIO_32_WO
+#define HWN_POWER_MINPWR_SET                POWER_MINPWR
+#define HWI_POWER_MINPWR_SET                
+#define HW_POWER_MINPWR_CLR                 HW(POWER_MINPWR_CLR)
+#define HWA_POWER_MINPWR_CLR                (HWA_POWER_MINPWR + 0x8)
+#define HWT_POWER_MINPWR_CLR                HWIO_32_WO
+#define HWN_POWER_MINPWR_CLR                POWER_MINPWR
+#define HWI_POWER_MINPWR_CLR                
+#define HW_POWER_MINPWR_TOG                 HW(POWER_MINPWR_TOG)
+#define HWA_POWER_MINPWR_TOG                (HWA_POWER_MINPWR + 0xc)
+#define HWT_POWER_MINPWR_TOG                HWIO_32_WO
+#define HWN_POWER_MINPWR_TOG                POWER_MINPWR
+#define HWI_POWER_MINPWR_TOG                
+#define BP_POWER_MINPWR_PWD_BO              11
+#define BM_POWER_MINPWR_PWD_BO              0x800
+#define BF_POWER_MINPWR_PWD_BO(v)           (((v) & 0x1) << 11)
+#define BFM_POWER_MINPWR_PWD_BO(v)          BM_POWER_MINPWR_PWD_BO
+#define BF_POWER_MINPWR_PWD_BO_V(e)         BF_POWER_MINPWR_PWD_BO(BV_POWER_MINPWR_PWD_BO__##e)
+#define BFM_POWER_MINPWR_PWD_BO_V(v)        BM_POWER_MINPWR_PWD_BO
+#define BP_POWER_MINPWR_USB_I_SUSPEND       10
+#define BM_POWER_MINPWR_USB_I_SUSPEND       0x400
+#define BF_POWER_MINPWR_USB_I_SUSPEND(v)    (((v) & 0x1) << 10)
+#define BFM_POWER_MINPWR_USB_I_SUSPEND(v)   BM_POWER_MINPWR_USB_I_SUSPEND
+#define BF_POWER_MINPWR_USB_I_SUSPEND_V(e)  BF_POWER_MINPWR_USB_I_SUSPEND(BV_POWER_MINPWR_USB_I_SUSPEND__##e)
+#define BFM_POWER_MINPWR_USB_I_SUSPEND_V(v) BM_POWER_MINPWR_USB_I_SUSPEND
+#define BP_POWER_MINPWR_ENABLE_OSC          9
+#define BM_POWER_MINPWR_ENABLE_OSC          0x200
+#define BF_POWER_MINPWR_ENABLE_OSC(v)       (((v) & 0x1) << 9)
+#define BFM_POWER_MINPWR_ENABLE_OSC(v)      BM_POWER_MINPWR_ENABLE_OSC
+#define BF_POWER_MINPWR_ENABLE_OSC_V(e)     BF_POWER_MINPWR_ENABLE_OSC(BV_POWER_MINPWR_ENABLE_OSC__##e)
+#define BFM_POWER_MINPWR_ENABLE_OSC_V(v)    BM_POWER_MINPWR_ENABLE_OSC
+#define BP_POWER_MINPWR_SELECT_OSC          8
+#define BM_POWER_MINPWR_SELECT_OSC          0x100
+#define BF_POWER_MINPWR_SELECT_OSC(v)       (((v) & 0x1) << 8)
+#define BFM_POWER_MINPWR_SELECT_OSC(v)      BM_POWER_MINPWR_SELECT_OSC
+#define BF_POWER_MINPWR_SELECT_OSC_V(e)     BF_POWER_MINPWR_SELECT_OSC(BV_POWER_MINPWR_SELECT_OSC__##e)
+#define BFM_POWER_MINPWR_SELECT_OSC_V(v)    BM_POWER_MINPWR_SELECT_OSC
+#define BP_POWER_MINPWR_VBG_OFF             7
+#define BM_POWER_MINPWR_VBG_OFF             0x80
+#define BF_POWER_MINPWR_VBG_OFF(v)          (((v) & 0x1) << 7)
+#define BFM_POWER_MINPWR_VBG_OFF(v)         BM_POWER_MINPWR_VBG_OFF
+#define BF_POWER_MINPWR_VBG_OFF_V(e)        BF_POWER_MINPWR_VBG_OFF(BV_POWER_MINPWR_VBG_OFF__##e)
+#define BFM_POWER_MINPWR_VBG_OFF_V(v)       BM_POWER_MINPWR_VBG_OFF
+#define BP_POWER_MINPWR_DOUBLE_FETS         6
+#define BM_POWER_MINPWR_DOUBLE_FETS         0x40
+#define BF_POWER_MINPWR_DOUBLE_FETS(v)      (((v) & 0x1) << 6)
+#define BFM_POWER_MINPWR_DOUBLE_FETS(v)     BM_POWER_MINPWR_DOUBLE_FETS
+#define BF_POWER_MINPWR_DOUBLE_FETS_V(e)    BF_POWER_MINPWR_DOUBLE_FETS(BV_POWER_MINPWR_DOUBLE_FETS__##e)
+#define BFM_POWER_MINPWR_DOUBLE_FETS_V(v)   BM_POWER_MINPWR_DOUBLE_FETS
+#define BP_POWER_MINPWR_HALF_FETS           5
+#define BM_POWER_MINPWR_HALF_FETS           0x20
+#define BF_POWER_MINPWR_HALF_FETS(v)        (((v) & 0x1) << 5)
+#define BFM_POWER_MINPWR_HALF_FETS(v)       BM_POWER_MINPWR_HALF_FETS
+#define BF_POWER_MINPWR_HALF_FETS_V(e)      BF_POWER_MINPWR_HALF_FETS(BV_POWER_MINPWR_HALF_FETS__##e)
+#define BFM_POWER_MINPWR_HALF_FETS_V(v)     BM_POWER_MINPWR_HALF_FETS
+#define BP_POWER_MINPWR_LESSANA_I           4
+#define BM_POWER_MINPWR_LESSANA_I           0x10
+#define BF_POWER_MINPWR_LESSANA_I(v)        (((v) & 0x1) << 4)
+#define BFM_POWER_MINPWR_LESSANA_I(v)       BM_POWER_MINPWR_LESSANA_I
+#define BF_POWER_MINPWR_LESSANA_I_V(e)      BF_POWER_MINPWR_LESSANA_I(BV_POWER_MINPWR_LESSANA_I__##e)
+#define BFM_POWER_MINPWR_LESSANA_I_V(v)     BM_POWER_MINPWR_LESSANA_I
+#define BP_POWER_MINPWR_PWD_XTAL24          3
+#define BM_POWER_MINPWR_PWD_XTAL24          0x8
+#define BF_POWER_MINPWR_PWD_XTAL24(v)       (((v) & 0x1) << 3)
+#define BFM_POWER_MINPWR_PWD_XTAL24(v)      BM_POWER_MINPWR_PWD_XTAL24
+#define BF_POWER_MINPWR_PWD_XTAL24_V(e)     BF_POWER_MINPWR_PWD_XTAL24(BV_POWER_MINPWR_PWD_XTAL24__##e)
+#define BFM_POWER_MINPWR_PWD_XTAL24_V(v)    BM_POWER_MINPWR_PWD_XTAL24
+#define BP_POWER_MINPWR_DC_STOPCLK          2
+#define BM_POWER_MINPWR_DC_STOPCLK          0x4
+#define BF_POWER_MINPWR_DC_STOPCLK(v)       (((v) & 0x1) << 2)
+#define BFM_POWER_MINPWR_DC_STOPCLK(v)      BM_POWER_MINPWR_DC_STOPCLK
+#define BF_POWER_MINPWR_DC_STOPCLK_V(e)     BF_POWER_MINPWR_DC_STOPCLK(BV_POWER_MINPWR_DC_STOPCLK__##e)
+#define BFM_POWER_MINPWR_DC_STOPCLK_V(v)    BM_POWER_MINPWR_DC_STOPCLK
+#define BP_POWER_MINPWR_EN_DC_PFM           1
+#define BM_POWER_MINPWR_EN_DC_PFM           0x2
+#define BF_POWER_MINPWR_EN_DC_PFM(v)        (((v) & 0x1) << 1)
+#define BFM_POWER_MINPWR_EN_DC_PFM(v)       BM_POWER_MINPWR_EN_DC_PFM
+#define BF_POWER_MINPWR_EN_DC_PFM_V(e)      BF_POWER_MINPWR_EN_DC_PFM(BV_POWER_MINPWR_EN_DC_PFM__##e)
+#define BFM_POWER_MINPWR_EN_DC_PFM_V(v)     BM_POWER_MINPWR_EN_DC_PFM
+#define BP_POWER_MINPWR_DC_HALFCLK          0
+#define BM_POWER_MINPWR_DC_HALFCLK          0x1
+#define BF_POWER_MINPWR_DC_HALFCLK(v)       (((v) & 0x1) << 0)
+#define BFM_POWER_MINPWR_DC_HALFCLK(v)      BM_POWER_MINPWR_DC_HALFCLK
+#define BF_POWER_MINPWR_DC_HALFCLK_V(e)     BF_POWER_MINPWR_DC_HALFCLK(BV_POWER_MINPWR_DC_HALFCLK__##e)
+#define BFM_POWER_MINPWR_DC_HALFCLK_V(v)    BM_POWER_MINPWR_DC_HALFCLK
+
+#define HW_POWER_CHARGE                             HW(POWER_CHARGE)
+#define HWA_POWER_CHARGE                            (0x80044000 + 0x30)
+#define HWT_POWER_CHARGE                            HWIO_32_RW
+#define HWN_POWER_CHARGE                            POWER_CHARGE
+#define HWI_POWER_CHARGE                            
+#define HW_POWER_CHARGE_SET                         HW(POWER_CHARGE_SET)
+#define HWA_POWER_CHARGE_SET                        (HWA_POWER_CHARGE + 0x4)
+#define HWT_POWER_CHARGE_SET                        HWIO_32_WO
+#define HWN_POWER_CHARGE_SET                        POWER_CHARGE
+#define HWI_POWER_CHARGE_SET                        
+#define HW_POWER_CHARGE_CLR                         HW(POWER_CHARGE_CLR)
+#define HWA_POWER_CHARGE_CLR                        (HWA_POWER_CHARGE + 0x8)
+#define HWT_POWER_CHARGE_CLR                        HWIO_32_WO
+#define HWN_POWER_CHARGE_CLR                        POWER_CHARGE
+#define HWI_POWER_CHARGE_CLR                        
+#define HW_POWER_CHARGE_TOG                         HW(POWER_CHARGE_TOG)
+#define HWA_POWER_CHARGE_TOG                        (HWA_POWER_CHARGE + 0xc)
+#define HWT_POWER_CHARGE_TOG                        HWIO_32_WO
+#define HWN_POWER_CHARGE_TOG                        POWER_CHARGE
+#define HWI_POWER_CHARGE_TOG                        
+#define BP_POWER_CHARGE_ENABLE_FAULT_DETECT         20
+#define BM_POWER_CHARGE_ENABLE_FAULT_DETECT         0x100000
+#define BF_POWER_CHARGE_ENABLE_FAULT_DETECT(v)      (((v) & 0x1) << 20)
+#define BFM_POWER_CHARGE_ENABLE_FAULT_DETECT(v)     BM_POWER_CHARGE_ENABLE_FAULT_DETECT
+#define BF_POWER_CHARGE_ENABLE_FAULT_DETECT_V(e)    BF_POWER_CHARGE_ENABLE_FAULT_DETECT(BV_POWER_CHARGE_ENABLE_FAULT_DETECT__##e)
+#define BFM_POWER_CHARGE_ENABLE_FAULT_DETECT_V(v)   BM_POWER_CHARGE_ENABLE_FAULT_DETECT
+#define BP_POWER_CHARGE_CHRG_STS_OFF                19
+#define BM_POWER_CHARGE_CHRG_STS_OFF                0x80000
+#define BF_POWER_CHARGE_CHRG_STS_OFF(v)             (((v) & 0x1) << 19)
+#define BFM_POWER_CHARGE_CHRG_STS_OFF(v)            BM_POWER_CHARGE_CHRG_STS_OFF
+#define BF_POWER_CHARGE_CHRG_STS_OFF_V(e)           BF_POWER_CHARGE_CHRG_STS_OFF(BV_POWER_CHARGE_CHRG_STS_OFF__##e)
+#define BFM_POWER_CHARGE_CHRG_STS_OFF_V(v)          BM_POWER_CHARGE_CHRG_STS_OFF
+#define BP_POWER_CHARGE_USE_EXTERN_R                17
+#define BM_POWER_CHARGE_USE_EXTERN_R                0x20000
+#define BF_POWER_CHARGE_USE_EXTERN_R(v)             (((v) & 0x1) << 17)
+#define BFM_POWER_CHARGE_USE_EXTERN_R(v)            BM_POWER_CHARGE_USE_EXTERN_R
+#define BF_POWER_CHARGE_USE_EXTERN_R_V(e)           BF_POWER_CHARGE_USE_EXTERN_R(BV_POWER_CHARGE_USE_EXTERN_R__##e)
+#define BFM_POWER_CHARGE_USE_EXTERN_R_V(v)          BM_POWER_CHARGE_USE_EXTERN_R
+#define BP_POWER_CHARGE_PWD_BATTCHRG                16
+#define BM_POWER_CHARGE_PWD_BATTCHRG                0x10000
+#define BF_POWER_CHARGE_PWD_BATTCHRG(v)             (((v) & 0x1) << 16)
+#define BFM_POWER_CHARGE_PWD_BATTCHRG(v)            BM_POWER_CHARGE_PWD_BATTCHRG
+#define BF_POWER_CHARGE_PWD_BATTCHRG_V(e)           BF_POWER_CHARGE_PWD_BATTCHRG(BV_POWER_CHARGE_PWD_BATTCHRG__##e)
+#define BFM_POWER_CHARGE_PWD_BATTCHRG_V(v)          BM_POWER_CHARGE_PWD_BATTCHRG
+#define BP_POWER_CHARGE_STOP_ILIMIT                 8
+#define BM_POWER_CHARGE_STOP_ILIMIT                 0xf00
+#define BF_POWER_CHARGE_STOP_ILIMIT(v)              (((v) & 0xf) << 8)
+#define BFM_POWER_CHARGE_STOP_ILIMIT(v)             BM_POWER_CHARGE_STOP_ILIMIT
+#define BF_POWER_CHARGE_STOP_ILIMIT_V(e)            BF_POWER_CHARGE_STOP_ILIMIT(BV_POWER_CHARGE_STOP_ILIMIT__##e)
+#define BFM_POWER_CHARGE_STOP_ILIMIT_V(v)           BM_POWER_CHARGE_STOP_ILIMIT
+#define BP_POWER_CHARGE_BATTCHRG_I                  0
+#define BM_POWER_CHARGE_BATTCHRG_I                  0x3f
+#define BF_POWER_CHARGE_BATTCHRG_I(v)               (((v) & 0x3f) << 0)
+#define BFM_POWER_CHARGE_BATTCHRG_I(v)              BM_POWER_CHARGE_BATTCHRG_I
+#define BF_POWER_CHARGE_BATTCHRG_I_V(e)             BF_POWER_CHARGE_BATTCHRG_I(BV_POWER_CHARGE_BATTCHRG_I__##e)
+#define BFM_POWER_CHARGE_BATTCHRG_I_V(v)            BM_POWER_CHARGE_BATTCHRG_I
+
+#define HW_POWER_VDDDCTRL                           HW(POWER_VDDDCTRL)
+#define HWA_POWER_VDDDCTRL                          (0x80044000 + 0x40)
+#define HWT_POWER_VDDDCTRL                          HWIO_32_RW
+#define HWN_POWER_VDDDCTRL                          POWER_VDDDCTRL
+#define HWI_POWER_VDDDCTRL                          
+#define BP_POWER_VDDDCTRL_ADJTN                     28
+#define BM_POWER_VDDDCTRL_ADJTN                     0xf0000000
+#define BF_POWER_VDDDCTRL_ADJTN(v)                  (((v) & 0xf) << 28)
+#define BFM_POWER_VDDDCTRL_ADJTN(v)                 BM_POWER_VDDDCTRL_ADJTN
+#define BF_POWER_VDDDCTRL_ADJTN_V(e)                BF_POWER_VDDDCTRL_ADJTN(BV_POWER_VDDDCTRL_ADJTN__##e)
+#define BFM_POWER_VDDDCTRL_ADJTN_V(v)               BM_POWER_VDDDCTRL_ADJTN
+#define BP_POWER_VDDDCTRL_ALKALINE_CHARGE           24
+#define BM_POWER_VDDDCTRL_ALKALINE_CHARGE           0x1000000
+#define BF_POWER_VDDDCTRL_ALKALINE_CHARGE(v)        (((v) & 0x1) << 24)
+#define BFM_POWER_VDDDCTRL_ALKALINE_CHARGE(v)       BM_POWER_VDDDCTRL_ALKALINE_CHARGE
+#define BF_POWER_VDDDCTRL_ALKALINE_CHARGE_V(e)      BF_POWER_VDDDCTRL_ALKALINE_CHARGE(BV_POWER_VDDDCTRL_ALKALINE_CHARGE__##e)
+#define BFM_POWER_VDDDCTRL_ALKALINE_CHARGE_V(v)     BM_POWER_VDDDCTRL_ALKALINE_CHARGE
+#define BP_POWER_VDDDCTRL_DISABLE_STEPPING          23
+#define BM_POWER_VDDDCTRL_DISABLE_STEPPING          0x800000
+#define BF_POWER_VDDDCTRL_DISABLE_STEPPING(v)       (((v) & 0x1) << 23)
+#define BFM_POWER_VDDDCTRL_DISABLE_STEPPING(v)      BM_POWER_VDDDCTRL_DISABLE_STEPPING
+#define BF_POWER_VDDDCTRL_DISABLE_STEPPING_V(e)     BF_POWER_VDDDCTRL_DISABLE_STEPPING(BV_POWER_VDDDCTRL_DISABLE_STEPPING__##e)
+#define BFM_POWER_VDDDCTRL_DISABLE_STEPPING_V(v)    BM_POWER_VDDDCTRL_DISABLE_STEPPING
+#define BP_POWER_VDDDCTRL_LINREG_FROM_BATT          22
+#define BM_POWER_VDDDCTRL_LINREG_FROM_BATT          0x400000
+#define BF_POWER_VDDDCTRL_LINREG_FROM_BATT(v)       (((v) & 0x1) << 22)
+#define BFM_POWER_VDDDCTRL_LINREG_FROM_BATT(v)      BM_POWER_VDDDCTRL_LINREG_FROM_BATT
+#define BF_POWER_VDDDCTRL_LINREG_FROM_BATT_V(e)     BF_POWER_VDDDCTRL_LINREG_FROM_BATT(BV_POWER_VDDDCTRL_LINREG_FROM_BATT__##e)
+#define BFM_POWER_VDDDCTRL_LINREG_FROM_BATT_V(v)    BM_POWER_VDDDCTRL_LINREG_FROM_BATT
+#define BP_POWER_VDDDCTRL_ENABLE_LINREG             21
+#define BM_POWER_VDDDCTRL_ENABLE_LINREG             0x200000
+#define BF_POWER_VDDDCTRL_ENABLE_LINREG(v)          (((v) & 0x1) << 21)
+#define BFM_POWER_VDDDCTRL_ENABLE_LINREG(v)         BM_POWER_VDDDCTRL_ENABLE_LINREG
+#define BF_POWER_VDDDCTRL_ENABLE_LINREG_V(e)        BF_POWER_VDDDCTRL_ENABLE_LINREG(BV_POWER_VDDDCTRL_ENABLE_LINREG__##e)
+#define BFM_POWER_VDDDCTRL_ENABLE_LINREG_V(v)       BM_POWER_VDDDCTRL_ENABLE_LINREG
+#define BP_POWER_VDDDCTRL_DISABLE_FET               20
+#define BM_POWER_VDDDCTRL_DISABLE_FET               0x100000
+#define BF_POWER_VDDDCTRL_DISABLE_FET(v)            (((v) & 0x1) << 20)
+#define BFM_POWER_VDDDCTRL_DISABLE_FET(v)           BM_POWER_VDDDCTRL_DISABLE_FET
+#define BF_POWER_VDDDCTRL_DISABLE_FET_V(e)          BF_POWER_VDDDCTRL_DISABLE_FET(BV_POWER_VDDDCTRL_DISABLE_FET__##e)
+#define BFM_POWER_VDDDCTRL_DISABLE_FET_V(v)         BM_POWER_VDDDCTRL_DISABLE_FET
+#define BP_POWER_VDDDCTRL_LINREG_OFFSET             16
+#define BM_POWER_VDDDCTRL_LINREG_OFFSET             0x30000
+#define BF_POWER_VDDDCTRL_LINREG_OFFSET(v)          (((v) & 0x3) << 16)
+#define BFM_POWER_VDDDCTRL_LINREG_OFFSET(v)         BM_POWER_VDDDCTRL_LINREG_OFFSET
+#define BF_POWER_VDDDCTRL_LINREG_OFFSET_V(e)        BF_POWER_VDDDCTRL_LINREG_OFFSET(BV_POWER_VDDDCTRL_LINREG_OFFSET__##e)
+#define BFM_POWER_VDDDCTRL_LINREG_OFFSET_V(v)       BM_POWER_VDDDCTRL_LINREG_OFFSET
+#define BP_POWER_VDDDCTRL_BO_OFFSET                 8
+#define BM_POWER_VDDDCTRL_BO_OFFSET                 0x700
+#define BF_POWER_VDDDCTRL_BO_OFFSET(v)              (((v) & 0x7) << 8)
+#define BFM_POWER_VDDDCTRL_BO_OFFSET(v)             BM_POWER_VDDDCTRL_BO_OFFSET
+#define BF_POWER_VDDDCTRL_BO_OFFSET_V(e)            BF_POWER_VDDDCTRL_BO_OFFSET(BV_POWER_VDDDCTRL_BO_OFFSET__##e)
+#define BFM_POWER_VDDDCTRL_BO_OFFSET_V(v)           BM_POWER_VDDDCTRL_BO_OFFSET
+#define BP_POWER_VDDDCTRL_TRG                       0
+#define BM_POWER_VDDDCTRL_TRG                       0x1f
+#define BF_POWER_VDDDCTRL_TRG(v)                    (((v) & 0x1f) << 0)
+#define BFM_POWER_VDDDCTRL_TRG(v)                   BM_POWER_VDDDCTRL_TRG
+#define BF_POWER_VDDDCTRL_TRG_V(e)                  BF_POWER_VDDDCTRL_TRG(BV_POWER_VDDDCTRL_TRG__##e)
+#define BFM_POWER_VDDDCTRL_TRG_V(v)                 BM_POWER_VDDDCTRL_TRG
+
+#define HW_POWER_VDDACTRL                           HW(POWER_VDDACTRL)
+#define HWA_POWER_VDDACTRL                          (0x80044000 + 0x50)
+#define HWT_POWER_VDDACTRL                          HWIO_32_RW
+#define HWN_POWER_VDDACTRL                          POWER_VDDACTRL
+#define HWI_POWER_VDDACTRL                          
+#define BP_POWER_VDDACTRL_DISABLE_STEPPING          18
+#define BM_POWER_VDDACTRL_DISABLE_STEPPING          0x40000
+#define BF_POWER_VDDACTRL_DISABLE_STEPPING(v)       (((v) & 0x1) << 18)
+#define BFM_POWER_VDDACTRL_DISABLE_STEPPING(v)      BM_POWER_VDDACTRL_DISABLE_STEPPING
+#define BF_POWER_VDDACTRL_DISABLE_STEPPING_V(e)     BF_POWER_VDDACTRL_DISABLE_STEPPING(BV_POWER_VDDACTRL_DISABLE_STEPPING__##e)
+#define BFM_POWER_VDDACTRL_DISABLE_STEPPING_V(v)    BM_POWER_VDDACTRL_DISABLE_STEPPING
+#define BP_POWER_VDDACTRL_ENABLE_LINREG             17
+#define BM_POWER_VDDACTRL_ENABLE_LINREG             0x20000
+#define BF_POWER_VDDACTRL_ENABLE_LINREG(v)          (((v) & 0x1) << 17)
+#define BFM_POWER_VDDACTRL_ENABLE_LINREG(v)         BM_POWER_VDDACTRL_ENABLE_LINREG
+#define BF_POWER_VDDACTRL_ENABLE_LINREG_V(e)        BF_POWER_VDDACTRL_ENABLE_LINREG(BV_POWER_VDDACTRL_ENABLE_LINREG__##e)
+#define BFM_POWER_VDDACTRL_ENABLE_LINREG_V(v)       BM_POWER_VDDACTRL_ENABLE_LINREG
+#define BP_POWER_VDDACTRL_DISABLE_FET               16
+#define BM_POWER_VDDACTRL_DISABLE_FET               0x10000
+#define BF_POWER_VDDACTRL_DISABLE_FET(v)            (((v) & 0x1) << 16)
+#define BFM_POWER_VDDACTRL_DISABLE_FET(v)           BM_POWER_VDDACTRL_DISABLE_FET
+#define BF_POWER_VDDACTRL_DISABLE_FET_V(e)          BF_POWER_VDDACTRL_DISABLE_FET(BV_POWER_VDDACTRL_DISABLE_FET__##e)
+#define BFM_POWER_VDDACTRL_DISABLE_FET_V(v)         BM_POWER_VDDACTRL_DISABLE_FET
+#define BP_POWER_VDDACTRL_LINREG_OFFSET             12
+#define BM_POWER_VDDACTRL_LINREG_OFFSET             0x3000
+#define BF_POWER_VDDACTRL_LINREG_OFFSET(v)          (((v) & 0x3) << 12)
+#define BFM_POWER_VDDACTRL_LINREG_OFFSET(v)         BM_POWER_VDDACTRL_LINREG_OFFSET
+#define BF_POWER_VDDACTRL_LINREG_OFFSET_V(e)        BF_POWER_VDDACTRL_LINREG_OFFSET(BV_POWER_VDDACTRL_LINREG_OFFSET__##e)
+#define BFM_POWER_VDDACTRL_LINREG_OFFSET_V(v)       BM_POWER_VDDACTRL_LINREG_OFFSET
+#define BP_POWER_VDDACTRL_BO_OFFSET                 8
+#define BM_POWER_VDDACTRL_BO_OFFSET                 0x700
+#define BF_POWER_VDDACTRL_BO_OFFSET(v)              (((v) & 0x7) << 8)
+#define BFM_POWER_VDDACTRL_BO_OFFSET(v)             BM_POWER_VDDACTRL_BO_OFFSET
+#define BF_POWER_VDDACTRL_BO_OFFSET_V(e)            BF_POWER_VDDACTRL_BO_OFFSET(BV_POWER_VDDACTRL_BO_OFFSET__##e)
+#define BFM_POWER_VDDACTRL_BO_OFFSET_V(v)           BM_POWER_VDDACTRL_BO_OFFSET
+#define BP_POWER_VDDACTRL_TRG                       0
+#define BM_POWER_VDDACTRL_TRG                       0x1f
+#define BF_POWER_VDDACTRL_TRG(v)                    (((v) & 0x1f) << 0)
+#define BFM_POWER_VDDACTRL_TRG(v)                   BM_POWER_VDDACTRL_TRG
+#define BF_POWER_VDDACTRL_TRG_V(e)                  BF_POWER_VDDACTRL_TRG(BV_POWER_VDDACTRL_TRG__##e)
+#define BFM_POWER_VDDACTRL_TRG_V(v)                 BM_POWER_VDDACTRL_TRG
+
+#define HW_POWER_VDDIOCTRL                          HW(POWER_VDDIOCTRL)
+#define HWA_POWER_VDDIOCTRL                         (0x80044000 + 0x60)
+#define HWT_POWER_VDDIOCTRL                         HWIO_32_RW
+#define HWN_POWER_VDDIOCTRL                         POWER_VDDIOCTRL
+#define HWI_POWER_VDDIOCTRL                         
+#define BP_POWER_VDDIOCTRL_ADJTN                    16
+#define BM_POWER_VDDIOCTRL_ADJTN                    0xf0000
+#define BF_POWER_VDDIOCTRL_ADJTN(v)                 (((v) & 0xf) << 16)
+#define BFM_POWER_VDDIOCTRL_ADJTN(v)                BM_POWER_VDDIOCTRL_ADJTN
+#define BF_POWER_VDDIOCTRL_ADJTN_V(e)               BF_POWER_VDDIOCTRL_ADJTN(BV_POWER_VDDIOCTRL_ADJTN__##e)
+#define BFM_POWER_VDDIOCTRL_ADJTN_V(v)              BM_POWER_VDDIOCTRL_ADJTN
+#define BP_POWER_VDDIOCTRL_DISABLE_STEPPING         15
+#define BM_POWER_VDDIOCTRL_DISABLE_STEPPING         0x8000
+#define BF_POWER_VDDIOCTRL_DISABLE_STEPPING(v)      (((v) & 0x1) << 15)
+#define BFM_POWER_VDDIOCTRL_DISABLE_STEPPING(v)     BM_POWER_VDDIOCTRL_DISABLE_STEPPING
+#define BF_POWER_VDDIOCTRL_DISABLE_STEPPING_V(e)    BF_POWER_VDDIOCTRL_DISABLE_STEPPING(BV_POWER_VDDIOCTRL_DISABLE_STEPPING__##e)
+#define BFM_POWER_VDDIOCTRL_DISABLE_STEPPING_V(v)   BM_POWER_VDDIOCTRL_DISABLE_STEPPING
+#define BP_POWER_VDDIOCTRL_DISABLE_FET              14
+#define BM_POWER_VDDIOCTRL_DISABLE_FET              0x4000
+#define BF_POWER_VDDIOCTRL_DISABLE_FET(v)           (((v) & 0x1) << 14)
+#define BFM_POWER_VDDIOCTRL_DISABLE_FET(v)          BM_POWER_VDDIOCTRL_DISABLE_FET
+#define BF_POWER_VDDIOCTRL_DISABLE_FET_V(e)         BF_POWER_VDDIOCTRL_DISABLE_FET(BV_POWER_VDDIOCTRL_DISABLE_FET__##e)
+#define BFM_POWER_VDDIOCTRL_DISABLE_FET_V(v)        BM_POWER_VDDIOCTRL_DISABLE_FET
+#define BP_POWER_VDDIOCTRL_LINREG_OFFSET            12
+#define BM_POWER_VDDIOCTRL_LINREG_OFFSET            0x3000
+#define BF_POWER_VDDIOCTRL_LINREG_OFFSET(v)         (((v) & 0x3) << 12)
+#define BFM_POWER_VDDIOCTRL_LINREG_OFFSET(v)        BM_POWER_VDDIOCTRL_LINREG_OFFSET
+#define BF_POWER_VDDIOCTRL_LINREG_OFFSET_V(e)       BF_POWER_VDDIOCTRL_LINREG_OFFSET(BV_POWER_VDDIOCTRL_LINREG_OFFSET__##e)
+#define BFM_POWER_VDDIOCTRL_LINREG_OFFSET_V(v)      BM_POWER_VDDIOCTRL_LINREG_OFFSET
+#define BP_POWER_VDDIOCTRL_BO_OFFSET                8
+#define BM_POWER_VDDIOCTRL_BO_OFFSET                0x700
+#define BF_POWER_VDDIOCTRL_BO_OFFSET(v)             (((v) & 0x7) << 8)
+#define BFM_POWER_VDDIOCTRL_BO_OFFSET(v)            BM_POWER_VDDIOCTRL_BO_OFFSET
+#define BF_POWER_VDDIOCTRL_BO_OFFSET_V(e)           BF_POWER_VDDIOCTRL_BO_OFFSET(BV_POWER_VDDIOCTRL_BO_OFFSET__##e)
+#define BFM_POWER_VDDIOCTRL_BO_OFFSET_V(v)          BM_POWER_VDDIOCTRL_BO_OFFSET
+#define BP_POWER_VDDIOCTRL_TRG                      0
+#define BM_POWER_VDDIOCTRL_TRG                      0x1f
+#define BF_POWER_VDDIOCTRL_TRG(v)                   (((v) & 0x1f) << 0)
+#define BFM_POWER_VDDIOCTRL_TRG(v)                  BM_POWER_VDDIOCTRL_TRG
+#define BF_POWER_VDDIOCTRL_TRG_V(e)                 BF_POWER_VDDIOCTRL_TRG(BV_POWER_VDDIOCTRL_TRG__##e)
+#define BFM_POWER_VDDIOCTRL_TRG_V(v)                BM_POWER_VDDIOCTRL_TRG
+
+#define HW_POWER_DCFUNCV                HW(POWER_DCFUNCV)
+#define HWA_POWER_DCFUNCV               (0x80044000 + 0x70)
+#define HWT_POWER_DCFUNCV               HWIO_32_RW
+#define HWN_POWER_DCFUNCV               POWER_DCFUNCV
+#define HWI_POWER_DCFUNCV               
+#define BP_POWER_DCFUNCV_VDDD           16
+#define BM_POWER_DCFUNCV_VDDD           0x3ff0000
+#define BF_POWER_DCFUNCV_VDDD(v)        (((v) & 0x3ff) << 16)
+#define BFM_POWER_DCFUNCV_VDDD(v)       BM_POWER_DCFUNCV_VDDD
+#define BF_POWER_DCFUNCV_VDDD_V(e)      BF_POWER_DCFUNCV_VDDD(BV_POWER_DCFUNCV_VDDD__##e)
+#define BFM_POWER_DCFUNCV_VDDD_V(v)     BM_POWER_DCFUNCV_VDDD
+#define BP_POWER_DCFUNCV_VDDIO          0
+#define BM_POWER_DCFUNCV_VDDIO          0x3ff
+#define BF_POWER_DCFUNCV_VDDIO(v)       (((v) & 0x3ff) << 0)
+#define BFM_POWER_DCFUNCV_VDDIO(v)      BM_POWER_DCFUNCV_VDDIO
+#define BF_POWER_DCFUNCV_VDDIO_V(e)     BF_POWER_DCFUNCV_VDDIO(BV_POWER_DCFUNCV_VDDIO__##e)
+#define BFM_POWER_DCFUNCV_VDDIO_V(v)    BM_POWER_DCFUNCV_VDDIO
+
+#define HW_POWER_MISC                       HW(POWER_MISC)
+#define HWA_POWER_MISC                      (0x80044000 + 0x80)
+#define HWT_POWER_MISC                      HWIO_32_RW
+#define HWN_POWER_MISC                      POWER_MISC
+#define HWI_POWER_MISC                      
+#define BP_POWER_MISC_FREQSEL               4
+#define BM_POWER_MISC_FREQSEL               0x30
+#define BF_POWER_MISC_FREQSEL(v)            (((v) & 0x3) << 4)
+#define BFM_POWER_MISC_FREQSEL(v)           BM_POWER_MISC_FREQSEL
+#define BF_POWER_MISC_FREQSEL_V(e)          BF_POWER_MISC_FREQSEL(BV_POWER_MISC_FREQSEL__##e)
+#define BFM_POWER_MISC_FREQSEL_V(v)         BM_POWER_MISC_FREQSEL
+#define BP_POWER_MISC_DELAY_TIMING          3
+#define BM_POWER_MISC_DELAY_TIMING          0x8
+#define BF_POWER_MISC_DELAY_TIMING(v)       (((v) & 0x1) << 3)
+#define BFM_POWER_MISC_DELAY_TIMING(v)      BM_POWER_MISC_DELAY_TIMING
+#define BF_POWER_MISC_DELAY_TIMING_V(e)     BF_POWER_MISC_DELAY_TIMING(BV_POWER_MISC_DELAY_TIMING__##e)
+#define BFM_POWER_MISC_DELAY_TIMING_V(v)    BM_POWER_MISC_DELAY_TIMING
+#define BP_POWER_MISC_TEST                  2
+#define BM_POWER_MISC_TEST                  0x4
+#define BF_POWER_MISC_TEST(v)               (((v) & 0x1) << 2)
+#define BFM_POWER_MISC_TEST(v)              BM_POWER_MISC_TEST
+#define BF_POWER_MISC_TEST_V(e)             BF_POWER_MISC_TEST(BV_POWER_MISC_TEST__##e)
+#define BFM_POWER_MISC_TEST_V(v)            BM_POWER_MISC_TEST
+#define BP_POWER_MISC_SEL_PLLCLK            1
+#define BM_POWER_MISC_SEL_PLLCLK            0x2
+#define BF_POWER_MISC_SEL_PLLCLK(v)         (((v) & 0x1) << 1)
+#define BFM_POWER_MISC_SEL_PLLCLK(v)        BM_POWER_MISC_SEL_PLLCLK
+#define BF_POWER_MISC_SEL_PLLCLK_V(e)       BF_POWER_MISC_SEL_PLLCLK(BV_POWER_MISC_SEL_PLLCLK__##e)
+#define BFM_POWER_MISC_SEL_PLLCLK_V(v)      BM_POWER_MISC_SEL_PLLCLK
+#define BP_POWER_MISC_PERIPHERALSWOFF       0
+#define BM_POWER_MISC_PERIPHERALSWOFF       0x1
+#define BF_POWER_MISC_PERIPHERALSWOFF(v)    (((v) & 0x1) << 0)
+#define BFM_POWER_MISC_PERIPHERALSWOFF(v)   BM_POWER_MISC_PERIPHERALSWOFF
+#define BF_POWER_MISC_PERIPHERALSWOFF_V(e)  BF_POWER_MISC_PERIPHERALSWOFF(BV_POWER_MISC_PERIPHERALSWOFF__##e)
+#define BFM_POWER_MISC_PERIPHERALSWOFF_V(v) BM_POWER_MISC_PERIPHERALSWOFF
+
+#define HW_POWER_DCLIMITS                       HW(POWER_DCLIMITS)
+#define HWA_POWER_DCLIMITS                      (0x80044000 + 0x90)
+#define HWT_POWER_DCLIMITS                      HWIO_32_RW
+#define HWN_POWER_DCLIMITS                      POWER_DCLIMITS
+#define HWI_POWER_DCLIMITS                      
+#define BP_POWER_DCLIMITS_POSLIMIT_BOOST        16
+#define BM_POWER_DCLIMITS_POSLIMIT_BOOST        0x7f0000
+#define BF_POWER_DCLIMITS_POSLIMIT_BOOST(v)     (((v) & 0x7f) << 16)
+#define BFM_POWER_DCLIMITS_POSLIMIT_BOOST(v)    BM_POWER_DCLIMITS_POSLIMIT_BOOST
+#define BF_POWER_DCLIMITS_POSLIMIT_BOOST_V(e)   BF_POWER_DCLIMITS_POSLIMIT_BOOST(BV_POWER_DCLIMITS_POSLIMIT_BOOST__##e)
+#define BFM_POWER_DCLIMITS_POSLIMIT_BOOST_V(v)  BM_POWER_DCLIMITS_POSLIMIT_BOOST
+#define BP_POWER_DCLIMITS_POSLIMIT_BUCK         8
+#define BM_POWER_DCLIMITS_POSLIMIT_BUCK         0x7f00
+#define BF_POWER_DCLIMITS_POSLIMIT_BUCK(v)      (((v) & 0x7f) << 8)
+#define BFM_POWER_DCLIMITS_POSLIMIT_BUCK(v)     BM_POWER_DCLIMITS_POSLIMIT_BUCK
+#define BF_POWER_DCLIMITS_POSLIMIT_BUCK_V(e)    BF_POWER_DCLIMITS_POSLIMIT_BUCK(BV_POWER_DCLIMITS_POSLIMIT_BUCK__##e)
+#define BFM_POWER_DCLIMITS_POSLIMIT_BUCK_V(v)   BM_POWER_DCLIMITS_POSLIMIT_BUCK
+#define BP_POWER_DCLIMITS_NEGLIMIT              0
+#define BM_POWER_DCLIMITS_NEGLIMIT              0x7f
+#define BF_POWER_DCLIMITS_NEGLIMIT(v)           (((v) & 0x7f) << 0)
+#define BFM_POWER_DCLIMITS_NEGLIMIT(v)          BM_POWER_DCLIMITS_NEGLIMIT
+#define BF_POWER_DCLIMITS_NEGLIMIT_V(e)         BF_POWER_DCLIMITS_NEGLIMIT(BV_POWER_DCLIMITS_NEGLIMIT__##e)
+#define BFM_POWER_DCLIMITS_NEGLIMIT_V(v)        BM_POWER_DCLIMITS_NEGLIMIT
+
+#define HW_POWER_LOOPCTRL                       HW(POWER_LOOPCTRL)
+#define HWA_POWER_LOOPCTRL                      (0x80044000 + 0xa0)
+#define HWT_POWER_LOOPCTRL                      HWIO_32_RW
+#define HWN_POWER_LOOPCTRL                      POWER_LOOPCTRL
+#define HWI_POWER_LOOPCTRL                      
+#define HW_POWER_LOOPCTRL_SET                   HW(POWER_LOOPCTRL_SET)
+#define HWA_POWER_LOOPCTRL_SET                  (HWA_POWER_LOOPCTRL + 0x4)
+#define HWT_POWER_LOOPCTRL_SET                  HWIO_32_WO
+#define HWN_POWER_LOOPCTRL_SET                  POWER_LOOPCTRL
+#define HWI_POWER_LOOPCTRL_SET                  
+#define HW_POWER_LOOPCTRL_CLR                   HW(POWER_LOOPCTRL_CLR)
+#define HWA_POWER_LOOPCTRL_CLR                  (HWA_POWER_LOOPCTRL + 0x8)
+#define HWT_POWER_LOOPCTRL_CLR                  HWIO_32_WO
+#define HWN_POWER_LOOPCTRL_CLR                  POWER_LOOPCTRL
+#define HWI_POWER_LOOPCTRL_CLR                  
+#define HW_POWER_LOOPCTRL_TOG                   HW(POWER_LOOPCTRL_TOG)
+#define HWA_POWER_LOOPCTRL_TOG                  (HWA_POWER_LOOPCTRL + 0xc)
+#define HWT_POWER_LOOPCTRL_TOG                  HWIO_32_WO
+#define HWN_POWER_LOOPCTRL_TOG                  POWER_LOOPCTRL
+#define HWI_POWER_LOOPCTRL_TOG                  
+#define BP_POWER_LOOPCTRL_TOGGLE_DIF            20
+#define BM_POWER_LOOPCTRL_TOGGLE_DIF            0x100000
+#define BF_POWER_LOOPCTRL_TOGGLE_DIF(v)         (((v) & 0x1) << 20)
+#define BFM_POWER_LOOPCTRL_TOGGLE_DIF(v)        BM_POWER_LOOPCTRL_TOGGLE_DIF
+#define BF_POWER_LOOPCTRL_TOGGLE_DIF_V(e)       BF_POWER_LOOPCTRL_TOGGLE_DIF(BV_POWER_LOOPCTRL_TOGGLE_DIF__##e)
+#define BFM_POWER_LOOPCTRL_TOGGLE_DIF_V(v)      BM_POWER_LOOPCTRL_TOGGLE_DIF
+#define BP_POWER_LOOPCTRL_HYST_SIGN             19
+#define BM_POWER_LOOPCTRL_HYST_SIGN             0x80000
+#define BF_POWER_LOOPCTRL_HYST_SIGN(v)          (((v) & 0x1) << 19)
+#define BFM_POWER_LOOPCTRL_HYST_SIGN(v)         BM_POWER_LOOPCTRL_HYST_SIGN
+#define BF_POWER_LOOPCTRL_HYST_SIGN_V(e)        BF_POWER_LOOPCTRL_HYST_SIGN(BV_POWER_LOOPCTRL_HYST_SIGN__##e)
+#define BFM_POWER_LOOPCTRL_HYST_SIGN_V(v)       BM_POWER_LOOPCTRL_HYST_SIGN
+#define BP_POWER_LOOPCTRL_EN_CM_HYST            18
+#define BM_POWER_LOOPCTRL_EN_CM_HYST            0x40000
+#define BF_POWER_LOOPCTRL_EN_CM_HYST(v)         (((v) & 0x1) << 18)
+#define BFM_POWER_LOOPCTRL_EN_CM_HYST(v)        BM_POWER_LOOPCTRL_EN_CM_HYST
+#define BF_POWER_LOOPCTRL_EN_CM_HYST_V(e)       BF_POWER_LOOPCTRL_EN_CM_HYST(BV_POWER_LOOPCTRL_EN_CM_HYST__##e)
+#define BFM_POWER_LOOPCTRL_EN_CM_HYST_V(v)      BM_POWER_LOOPCTRL_EN_CM_HYST
+#define BP_POWER_LOOPCTRL_EN_DF_HYST            17
+#define BM_POWER_LOOPCTRL_EN_DF_HYST            0x20000
+#define BF_POWER_LOOPCTRL_EN_DF_HYST(v)         (((v) & 0x1) << 17)
+#define BFM_POWER_LOOPCTRL_EN_DF_HYST(v)        BM_POWER_LOOPCTRL_EN_DF_HYST
+#define BF_POWER_LOOPCTRL_EN_DF_HYST_V(e)       BF_POWER_LOOPCTRL_EN_DF_HYST(BV_POWER_LOOPCTRL_EN_DF_HYST__##e)
+#define BFM_POWER_LOOPCTRL_EN_DF_HYST_V(v)      BM_POWER_LOOPCTRL_EN_DF_HYST
+#define BP_POWER_LOOPCTRL_CM_HYST_THRESH        16
+#define BM_POWER_LOOPCTRL_CM_HYST_THRESH        0x10000
+#define BF_POWER_LOOPCTRL_CM_HYST_THRESH(v)     (((v) & 0x1) << 16)
+#define BFM_POWER_LOOPCTRL_CM_HYST_THRESH(v)    BM_POWER_LOOPCTRL_CM_HYST_THRESH
+#define BF_POWER_LOOPCTRL_CM_HYST_THRESH_V(e)   BF_POWER_LOOPCTRL_CM_HYST_THRESH(BV_POWER_LOOPCTRL_CM_HYST_THRESH__##e)
+#define BFM_POWER_LOOPCTRL_CM_HYST_THRESH_V(v)  BM_POWER_LOOPCTRL_CM_HYST_THRESH
+#define BP_POWER_LOOPCTRL_DF_HYST_THRESH        15
+#define BM_POWER_LOOPCTRL_DF_HYST_THRESH        0x8000
+#define BF_POWER_LOOPCTRL_DF_HYST_THRESH(v)     (((v) & 0x1) << 15)
+#define BFM_POWER_LOOPCTRL_DF_HYST_THRESH(v)    BM_POWER_LOOPCTRL_DF_HYST_THRESH
+#define BF_POWER_LOOPCTRL_DF_HYST_THRESH_V(e)   BF_POWER_LOOPCTRL_DF_HYST_THRESH(BV_POWER_LOOPCTRL_DF_HYST_THRESH__##e)
+#define BFM_POWER_LOOPCTRL_DF_HYST_THRESH_V(v)  BM_POWER_LOOPCTRL_DF_HYST_THRESH
+#define BP_POWER_LOOPCTRL_RCSCALE_THRESH        14
+#define BM_POWER_LOOPCTRL_RCSCALE_THRESH        0x4000
+#define BF_POWER_LOOPCTRL_RCSCALE_THRESH(v)     (((v) & 0x1) << 14)
+#define BFM_POWER_LOOPCTRL_RCSCALE_THRESH(v)    BM_POWER_LOOPCTRL_RCSCALE_THRESH
+#define BF_POWER_LOOPCTRL_RCSCALE_THRESH_V(e)   BF_POWER_LOOPCTRL_RCSCALE_THRESH(BV_POWER_LOOPCTRL_RCSCALE_THRESH__##e)
+#define BFM_POWER_LOOPCTRL_RCSCALE_THRESH_V(v)  BM_POWER_LOOPCTRL_RCSCALE_THRESH
+#define BP_POWER_LOOPCTRL_EN_RCSCALE            12
+#define BM_POWER_LOOPCTRL_EN_RCSCALE            0x3000
+#define BF_POWER_LOOPCTRL_EN_RCSCALE(v)         (((v) & 0x3) << 12)
+#define BFM_POWER_LOOPCTRL_EN_RCSCALE(v)        BM_POWER_LOOPCTRL_EN_RCSCALE
+#define BF_POWER_LOOPCTRL_EN_RCSCALE_V(e)       BF_POWER_LOOPCTRL_EN_RCSCALE(BV_POWER_LOOPCTRL_EN_RCSCALE__##e)
+#define BFM_POWER_LOOPCTRL_EN_RCSCALE_V(v)      BM_POWER_LOOPCTRL_EN_RCSCALE
+#define BP_POWER_LOOPCTRL_DC_FF                 8
+#define BM_POWER_LOOPCTRL_DC_FF                 0x700
+#define BF_POWER_LOOPCTRL_DC_FF(v)              (((v) & 0x7) << 8)
+#define BFM_POWER_LOOPCTRL_DC_FF(v)             BM_POWER_LOOPCTRL_DC_FF
+#define BF_POWER_LOOPCTRL_DC_FF_V(e)            BF_POWER_LOOPCTRL_DC_FF(BV_POWER_LOOPCTRL_DC_FF__##e)
+#define BFM_POWER_LOOPCTRL_DC_FF_V(v)           BM_POWER_LOOPCTRL_DC_FF
+#define BP_POWER_LOOPCTRL_DC_R                  4
+#define BM_POWER_LOOPCTRL_DC_R                  0xf0
+#define BF_POWER_LOOPCTRL_DC_R(v)               (((v) & 0xf) << 4)
+#define BFM_POWER_LOOPCTRL_DC_R(v)              BM_POWER_LOOPCTRL_DC_R
+#define BF_POWER_LOOPCTRL_DC_R_V(e)             BF_POWER_LOOPCTRL_DC_R(BV_POWER_LOOPCTRL_DC_R__##e)
+#define BFM_POWER_LOOPCTRL_DC_R_V(v)            BM_POWER_LOOPCTRL_DC_R
+#define BP_POWER_LOOPCTRL_DC_C                  0
+#define BM_POWER_LOOPCTRL_DC_C                  0x3
+#define BF_POWER_LOOPCTRL_DC_C(v)               (((v) & 0x3) << 0)
+#define BFM_POWER_LOOPCTRL_DC_C(v)              BM_POWER_LOOPCTRL_DC_C
+#define BF_POWER_LOOPCTRL_DC_C_V(e)             BF_POWER_LOOPCTRL_DC_C(BV_POWER_LOOPCTRL_DC_C__##e)
+#define BFM_POWER_LOOPCTRL_DC_C_V(v)            BM_POWER_LOOPCTRL_DC_C
+
+#define HW_POWER_STS                            HW(POWER_STS)
+#define HWA_POWER_STS                           (0x80044000 + 0xb0)
+#define HWT_POWER_STS                           HWIO_32_RW
+#define HWN_POWER_STS                           POWER_STS
+#define HWI_POWER_STS                           
+#define BP_POWER_STS_BATT_CHRG_PRESENT          31
+#define BM_POWER_STS_BATT_CHRG_PRESENT          0x80000000
+#define BF_POWER_STS_BATT_CHRG_PRESENT(v)       (((v) & 0x1) << 31)
+#define BFM_POWER_STS_BATT_CHRG_PRESENT(v)      BM_POWER_STS_BATT_CHRG_PRESENT
+#define BF_POWER_STS_BATT_CHRG_PRESENT_V(e)     BF_POWER_STS_BATT_CHRG_PRESENT(BV_POWER_STS_BATT_CHRG_PRESENT__##e)
+#define BFM_POWER_STS_BATT_CHRG_PRESENT_V(v)    BM_POWER_STS_BATT_CHRG_PRESENT
+#define BP_POWER_STS_PSWITCH                    18
+#define BM_POWER_STS_PSWITCH                    0xc0000
+#define BF_POWER_STS_PSWITCH(v)                 (((v) & 0x3) << 18)
+#define BFM_POWER_STS_PSWITCH(v)                BM_POWER_STS_PSWITCH
+#define BF_POWER_STS_PSWITCH_V(e)               BF_POWER_STS_PSWITCH(BV_POWER_STS_PSWITCH__##e)
+#define BFM_POWER_STS_PSWITCH_V(v)              BM_POWER_STS_PSWITCH
+#define BP_POWER_STS_AVALID_STATUS              17
+#define BM_POWER_STS_AVALID_STATUS              0x20000
+#define BF_POWER_STS_AVALID_STATUS(v)           (((v) & 0x1) << 17)
+#define BFM_POWER_STS_AVALID_STATUS(v)          BM_POWER_STS_AVALID_STATUS
+#define BF_POWER_STS_AVALID_STATUS_V(e)         BF_POWER_STS_AVALID_STATUS(BV_POWER_STS_AVALID_STATUS__##e)
+#define BFM_POWER_STS_AVALID_STATUS_V(v)        BM_POWER_STS_AVALID_STATUS
+#define BP_POWER_STS_BVALID_STATUS              16
+#define BM_POWER_STS_BVALID_STATUS              0x10000
+#define BF_POWER_STS_BVALID_STATUS(v)           (((v) & 0x1) << 16)
+#define BFM_POWER_STS_BVALID_STATUS(v)          BM_POWER_STS_BVALID_STATUS
+#define BF_POWER_STS_BVALID_STATUS_V(e)         BF_POWER_STS_BVALID_STATUS(BV_POWER_STS_BVALID_STATUS__##e)
+#define BFM_POWER_STS_BVALID_STATUS_V(v)        BM_POWER_STS_BVALID_STATUS
+#define BP_POWER_STS_VBUSVALID_STATUS           15
+#define BM_POWER_STS_VBUSVALID_STATUS           0x8000
+#define BF_POWER_STS_VBUSVALID_STATUS(v)        (((v) & 0x1) << 15)
+#define BFM_POWER_STS_VBUSVALID_STATUS(v)       BM_POWER_STS_VBUSVALID_STATUS
+#define BF_POWER_STS_VBUSVALID_STATUS_V(e)      BF_POWER_STS_VBUSVALID_STATUS(BV_POWER_STS_VBUSVALID_STATUS__##e)
+#define BFM_POWER_STS_VBUSVALID_STATUS_V(v)     BM_POWER_STS_VBUSVALID_STATUS
+#define BP_POWER_STS_SESSEND_STATUS             14
+#define BM_POWER_STS_SESSEND_STATUS             0x4000
+#define BF_POWER_STS_SESSEND_STATUS(v)          (((v) & 0x1) << 14)
+#define BFM_POWER_STS_SESSEND_STATUS(v)         BM_POWER_STS_SESSEND_STATUS
+#define BF_POWER_STS_SESSEND_STATUS_V(e)        BF_POWER_STS_SESSEND_STATUS(BV_POWER_STS_SESSEND_STATUS__##e)
+#define BFM_POWER_STS_SESSEND_STATUS_V(v)       BM_POWER_STS_SESSEND_STATUS
+#define BP_POWER_STS_MODE                       13
+#define BM_POWER_STS_MODE                       0x2000
+#define BF_POWER_STS_MODE(v)                    (((v) & 0x1) << 13)
+#define BFM_POWER_STS_MODE(v)                   BM_POWER_STS_MODE
+#define BF_POWER_STS_MODE_V(e)                  BF_POWER_STS_MODE(BV_POWER_STS_MODE__##e)
+#define BFM_POWER_STS_MODE_V(v)                 BM_POWER_STS_MODE
+#define BP_POWER_STS_BATT_BO                    12
+#define BM_POWER_STS_BATT_BO                    0x1000
+#define BF_POWER_STS_BATT_BO(v)                 (((v) & 0x1) << 12)
+#define BFM_POWER_STS_BATT_BO(v)                BM_POWER_STS_BATT_BO
+#define BF_POWER_STS_BATT_BO_V(e)               BF_POWER_STS_BATT_BO(BV_POWER_STS_BATT_BO__##e)
+#define BFM_POWER_STS_BATT_BO_V(v)              BM_POWER_STS_BATT_BO
+#define BP_POWER_STS_VDD5V_FAULT                11
+#define BM_POWER_STS_VDD5V_FAULT                0x800
+#define BF_POWER_STS_VDD5V_FAULT(v)             (((v) & 0x1) << 11)
+#define BFM_POWER_STS_VDD5V_FAULT(v)            BM_POWER_STS_VDD5V_FAULT
+#define BF_POWER_STS_VDD5V_FAULT_V(e)           BF_POWER_STS_VDD5V_FAULT(BV_POWER_STS_VDD5V_FAULT__##e)
+#define BFM_POWER_STS_VDD5V_FAULT_V(v)          BM_POWER_STS_VDD5V_FAULT
+#define BP_POWER_STS_CHRGSTS                    10
+#define BM_POWER_STS_CHRGSTS                    0x400
+#define BF_POWER_STS_CHRGSTS(v)                 (((v) & 0x1) << 10)
+#define BFM_POWER_STS_CHRGSTS(v)                BM_POWER_STS_CHRGSTS
+#define BF_POWER_STS_CHRGSTS_V(e)               BF_POWER_STS_CHRGSTS(BV_POWER_STS_CHRGSTS__##e)
+#define BFM_POWER_STS_CHRGSTS_V(v)              BM_POWER_STS_CHRGSTS
+#define BP_POWER_STS_LINREG_OK                  9
+#define BM_POWER_STS_LINREG_OK                  0x200
+#define BF_POWER_STS_LINREG_OK(v)               (((v) & 0x1) << 9)
+#define BFM_POWER_STS_LINREG_OK(v)              BM_POWER_STS_LINREG_OK
+#define BF_POWER_STS_LINREG_OK_V(e)             BF_POWER_STS_LINREG_OK(BV_POWER_STS_LINREG_OK__##e)
+#define BFM_POWER_STS_LINREG_OK_V(v)            BM_POWER_STS_LINREG_OK
+#define BP_POWER_STS_DC_OK                      8
+#define BM_POWER_STS_DC_OK                      0x100
+#define BF_POWER_STS_DC_OK(v)                   (((v) & 0x1) << 8)
+#define BFM_POWER_STS_DC_OK(v)                  BM_POWER_STS_DC_OK
+#define BF_POWER_STS_DC_OK_V(e)                 BF_POWER_STS_DC_OK(BV_POWER_STS_DC_OK__##e)
+#define BFM_POWER_STS_DC_OK_V(v)                BM_POWER_STS_DC_OK
+#define BP_POWER_STS_VDDIO_BO                   7
+#define BM_POWER_STS_VDDIO_BO                   0x80
+#define BF_POWER_STS_VDDIO_BO(v)                (((v) & 0x1) << 7)
+#define BFM_POWER_STS_VDDIO_BO(v)               BM_POWER_STS_VDDIO_BO
+#define BF_POWER_STS_VDDIO_BO_V(e)              BF_POWER_STS_VDDIO_BO(BV_POWER_STS_VDDIO_BO__##e)
+#define BFM_POWER_STS_VDDIO_BO_V(v)             BM_POWER_STS_VDDIO_BO
+#define BP_POWER_STS_VDDA_BO                    6
+#define BM_POWER_STS_VDDA_BO                    0x40
+#define BF_POWER_STS_VDDA_BO(v)                 (((v) & 0x1) << 6)
+#define BFM_POWER_STS_VDDA_BO(v)                BM_POWER_STS_VDDA_BO
+#define BF_POWER_STS_VDDA_BO_V(e)               BF_POWER_STS_VDDA_BO(BV_POWER_STS_VDDA_BO__##e)
+#define BFM_POWER_STS_VDDA_BO_V(v)              BM_POWER_STS_VDDA_BO
+#define BP_POWER_STS_VDDD_BO                    5
+#define BM_POWER_STS_VDDD_BO                    0x20
+#define BF_POWER_STS_VDDD_BO(v)                 (((v) & 0x1) << 5)
+#define BFM_POWER_STS_VDDD_BO(v)                BM_POWER_STS_VDDD_BO
+#define BF_POWER_STS_VDDD_BO_V(e)               BF_POWER_STS_VDDD_BO(BV_POWER_STS_VDDD_BO__##e)
+#define BFM_POWER_STS_VDDD_BO_V(v)              BM_POWER_STS_VDDD_BO
+#define BP_POWER_STS_VDD5V_GT_VDDIO             4
+#define BM_POWER_STS_VDD5V_GT_VDDIO             0x10
+#define BF_POWER_STS_VDD5V_GT_VDDIO(v)          (((v) & 0x1) << 4)
+#define BFM_POWER_STS_VDD5V_GT_VDDIO(v)         BM_POWER_STS_VDD5V_GT_VDDIO
+#define BF_POWER_STS_VDD5V_GT_VDDIO_V(e)        BF_POWER_STS_VDD5V_GT_VDDIO(BV_POWER_STS_VDD5V_GT_VDDIO__##e)
+#define BFM_POWER_STS_VDD5V_GT_VDDIO_V(v)       BM_POWER_STS_VDD5V_GT_VDDIO
+#define BP_POWER_STS_AVALID                     3
+#define BM_POWER_STS_AVALID                     0x8
+#define BF_POWER_STS_AVALID(v)                  (((v) & 0x1) << 3)
+#define BFM_POWER_STS_AVALID(v)                 BM_POWER_STS_AVALID
+#define BF_POWER_STS_AVALID_V(e)                BF_POWER_STS_AVALID(BV_POWER_STS_AVALID__##e)
+#define BFM_POWER_STS_AVALID_V(v)               BM_POWER_STS_AVALID
+#define BP_POWER_STS_BVALID                     2
+#define BM_POWER_STS_BVALID                     0x4
+#define BF_POWER_STS_BVALID(v)                  (((v) & 0x1) << 2)
+#define BFM_POWER_STS_BVALID(v)                 BM_POWER_STS_BVALID
+#define BF_POWER_STS_BVALID_V(e)                BF_POWER_STS_BVALID(BV_POWER_STS_BVALID__##e)
+#define BFM_POWER_STS_BVALID_V(v)               BM_POWER_STS_BVALID
+#define BP_POWER_STS_VBUSVALID                  1
+#define BM_POWER_STS_VBUSVALID                  0x2
+#define BF_POWER_STS_VBUSVALID(v)               (((v) & 0x1) << 1)
+#define BFM_POWER_STS_VBUSVALID(v)              BM_POWER_STS_VBUSVALID
+#define BF_POWER_STS_VBUSVALID_V(e)             BF_POWER_STS_VBUSVALID(BV_POWER_STS_VBUSVALID__##e)
+#define BFM_POWER_STS_VBUSVALID_V(v)            BM_POWER_STS_VBUSVALID
+#define BP_POWER_STS_SESSEND                    0
+#define BM_POWER_STS_SESSEND                    0x1
+#define BF_POWER_STS_SESSEND(v)                 (((v) & 0x1) << 0)
+#define BFM_POWER_STS_SESSEND(v)                BM_POWER_STS_SESSEND
+#define BF_POWER_STS_SESSEND_V(e)               BF_POWER_STS_SESSEND(BV_POWER_STS_SESSEND__##e)
+#define BFM_POWER_STS_SESSEND_V(v)              BM_POWER_STS_SESSEND
+
+#define HW_POWER_SPEED              HW(POWER_SPEED)
+#define HWA_POWER_SPEED             (0x80044000 + 0xc0)
+#define HWT_POWER_SPEED             HWIO_32_RW
+#define HWN_POWER_SPEED             POWER_SPEED
+#define HWI_POWER_SPEED             
+#define HW_POWER_SPEED_SET          HW(POWER_SPEED_SET)
+#define HWA_POWER_SPEED_SET         (HWA_POWER_SPEED + 0x4)
+#define HWT_POWER_SPEED_SET         HWIO_32_WO
+#define HWN_POWER_SPEED_SET         POWER_SPEED
+#define HWI_POWER_SPEED_SET         
+#define HW_POWER_SPEED_CLR          HW(POWER_SPEED_CLR)
+#define HWA_POWER_SPEED_CLR         (HWA_POWER_SPEED + 0x8)
+#define HWT_POWER_SPEED_CLR         HWIO_32_WO
+#define HWN_POWER_SPEED_CLR         POWER_SPEED
+#define HWI_POWER_SPEED_CLR         
+#define HW_POWER_SPEED_TOG          HW(POWER_SPEED_TOG)
+#define HWA_POWER_SPEED_TOG         (HWA_POWER_SPEED + 0xc)
+#define HWT_POWER_SPEED_TOG         HWIO_32_WO
+#define HWN_POWER_SPEED_TOG         POWER_SPEED
+#define HWI_POWER_SPEED_TOG         
+#define BP_POWER_SPEED_STATUS       16
+#define BM_POWER_SPEED_STATUS       0xff0000
+#define BF_POWER_SPEED_STATUS(v)    (((v) & 0xff) << 16)
+#define BFM_POWER_SPEED_STATUS(v)   BM_POWER_SPEED_STATUS
+#define BF_POWER_SPEED_STATUS_V(e)  BF_POWER_SPEED_STATUS(BV_POWER_SPEED_STATUS__##e)
+#define BFM_POWER_SPEED_STATUS_V(v) BM_POWER_SPEED_STATUS
+#define BP_POWER_SPEED_CTRL         0
+#define BM_POWER_SPEED_CTRL         0x3
+#define BF_POWER_SPEED_CTRL(v)      (((v) & 0x3) << 0)
+#define BFM_POWER_SPEED_CTRL(v)     BM_POWER_SPEED_CTRL
+#define BF_POWER_SPEED_CTRL_V(e)    BF_POWER_SPEED_CTRL(BV_POWER_SPEED_CTRL__##e)
+#define BFM_POWER_SPEED_CTRL_V(v)   BM_POWER_SPEED_CTRL
+
+#define HW_POWER_BATTMONITOR                        HW(POWER_BATTMONITOR)
+#define HWA_POWER_BATTMONITOR                       (0x80044000 + 0xd0)
+#define HWT_POWER_BATTMONITOR                       HWIO_32_RW
+#define HWN_POWER_BATTMONITOR                       POWER_BATTMONITOR
+#define HWI_POWER_BATTMONITOR                       
+#define BP_POWER_BATTMONITOR_BATT_VAL               16
+#define BM_POWER_BATTMONITOR_BATT_VAL               0x3ff0000
+#define BF_POWER_BATTMONITOR_BATT_VAL(v)            (((v) & 0x3ff) << 16)
+#define BFM_POWER_BATTMONITOR_BATT_VAL(v)           BM_POWER_BATTMONITOR_BATT_VAL
+#define BF_POWER_BATTMONITOR_BATT_VAL_V(e)          BF_POWER_BATTMONITOR_BATT_VAL(BV_POWER_BATTMONITOR_BATT_VAL__##e)
+#define BFM_POWER_BATTMONITOR_BATT_VAL_V(v)         BM_POWER_BATTMONITOR_BATT_VAL
+#define BP_POWER_BATTMONITOR_EN_BATADJ              6
+#define BM_POWER_BATTMONITOR_EN_BATADJ              0x40
+#define BF_POWER_BATTMONITOR_EN_BATADJ(v)           (((v) & 0x1) << 6)
+#define BFM_POWER_BATTMONITOR_EN_BATADJ(v)          BM_POWER_BATTMONITOR_EN_BATADJ
+#define BF_POWER_BATTMONITOR_EN_BATADJ_V(e)         BF_POWER_BATTMONITOR_EN_BATADJ(BV_POWER_BATTMONITOR_EN_BATADJ__##e)
+#define BFM_POWER_BATTMONITOR_EN_BATADJ_V(v)        BM_POWER_BATTMONITOR_EN_BATADJ
+#define BP_POWER_BATTMONITOR_PWDN_BATTBRNOUT        5
+#define BM_POWER_BATTMONITOR_PWDN_BATTBRNOUT        0x20
+#define BF_POWER_BATTMONITOR_PWDN_BATTBRNOUT(v)     (((v) & 0x1) << 5)
+#define BFM_POWER_BATTMONITOR_PWDN_BATTBRNOUT(v)    BM_POWER_BATTMONITOR_PWDN_BATTBRNOUT
+#define BF_POWER_BATTMONITOR_PWDN_BATTBRNOUT_V(e)   BF_POWER_BATTMONITOR_PWDN_BATTBRNOUT(BV_POWER_BATTMONITOR_PWDN_BATTBRNOUT__##e)
+#define BFM_POWER_BATTMONITOR_PWDN_BATTBRNOUT_V(v)  BM_POWER_BATTMONITOR_PWDN_BATTBRNOUT
+#define BP_POWER_BATTMONITOR_BRWNOUT_PWD            4
+#define BM_POWER_BATTMONITOR_BRWNOUT_PWD            0x10
+#define BF_POWER_BATTMONITOR_BRWNOUT_PWD(v)         (((v) & 0x1) << 4)
+#define BFM_POWER_BATTMONITOR_BRWNOUT_PWD(v)        BM_POWER_BATTMONITOR_BRWNOUT_PWD
+#define BF_POWER_BATTMONITOR_BRWNOUT_PWD_V(e)       BF_POWER_BATTMONITOR_BRWNOUT_PWD(BV_POWER_BATTMONITOR_BRWNOUT_PWD__##e)
+#define BFM_POWER_BATTMONITOR_BRWNOUT_PWD_V(v)      BM_POWER_BATTMONITOR_BRWNOUT_PWD
+#define BP_POWER_BATTMONITOR_BRWNOUT_LVL            0
+#define BM_POWER_BATTMONITOR_BRWNOUT_LVL            0xf
+#define BF_POWER_BATTMONITOR_BRWNOUT_LVL(v)         (((v) & 0xf) << 0)
+#define BFM_POWER_BATTMONITOR_BRWNOUT_LVL(v)        BM_POWER_BATTMONITOR_BRWNOUT_LVL
+#define BF_POWER_BATTMONITOR_BRWNOUT_LVL_V(e)       BF_POWER_BATTMONITOR_BRWNOUT_LVL(BV_POWER_BATTMONITOR_BRWNOUT_LVL__##e)
+#define BFM_POWER_BATTMONITOR_BRWNOUT_LVL_V(v)      BM_POWER_BATTMONITOR_BRWNOUT_LVL
+
+#define HW_POWER_RESET                  HW(POWER_RESET)
+#define HWA_POWER_RESET                 (0x80044000 + 0xe0)
+#define HWT_POWER_RESET                 HWIO_32_RW
+#define HWN_POWER_RESET                 POWER_RESET
+#define HWI_POWER_RESET                 
+#define HW_POWER_RESET_SET              HW(POWER_RESET_SET)
+#define HWA_POWER_RESET_SET             (HWA_POWER_RESET + 0x4)
+#define HWT_POWER_RESET_SET             HWIO_32_WO
+#define HWN_POWER_RESET_SET             POWER_RESET
+#define HWI_POWER_RESET_SET             
+#define HW_POWER_RESET_CLR              HW(POWER_RESET_CLR)
+#define HWA_POWER_RESET_CLR             (HWA_POWER_RESET + 0x8)
+#define HWT_POWER_RESET_CLR             HWIO_32_WO
+#define HWN_POWER_RESET_CLR             POWER_RESET
+#define HWI_POWER_RESET_CLR             
+#define HW_POWER_RESET_TOG              HW(POWER_RESET_TOG)
+#define HWA_POWER_RESET_TOG             (HWA_POWER_RESET + 0xc)
+#define HWT_POWER_RESET_TOG             HWIO_32_WO
+#define HWN_POWER_RESET_TOG             POWER_RESET
+#define HWI_POWER_RESET_TOG             
+#define BP_POWER_RESET_UNLOCK           16
+#define BM_POWER_RESET_UNLOCK           0xffff0000
+#define BV_POWER_RESET_UNLOCK__KEY      0x3e77
+#define BF_POWER_RESET_UNLOCK(v)        (((v) & 0xffff) << 16)
+#define BFM_POWER_RESET_UNLOCK(v)       BM_POWER_RESET_UNLOCK
+#define BF_POWER_RESET_UNLOCK_V(e)      BF_POWER_RESET_UNLOCK(BV_POWER_RESET_UNLOCK__##e)
+#define BFM_POWER_RESET_UNLOCK_V(v)     BM_POWER_RESET_UNLOCK
+#define BP_POWER_RESET_PWD_OFF          1
+#define BM_POWER_RESET_PWD_OFF          0x2
+#define BF_POWER_RESET_PWD_OFF(v)       (((v) & 0x1) << 1)
+#define BFM_POWER_RESET_PWD_OFF(v)      BM_POWER_RESET_PWD_OFF
+#define BF_POWER_RESET_PWD_OFF_V(e)     BF_POWER_RESET_PWD_OFF(BV_POWER_RESET_PWD_OFF__##e)
+#define BFM_POWER_RESET_PWD_OFF_V(v)    BM_POWER_RESET_PWD_OFF
+#define BP_POWER_RESET_PWD              0
+#define BM_POWER_RESET_PWD              0x1
+#define BF_POWER_RESET_PWD(v)           (((v) & 0x1) << 0)
+#define BFM_POWER_RESET_PWD(v)          BM_POWER_RESET_PWD
+#define BF_POWER_RESET_PWD_V(e)         BF_POWER_RESET_PWD(BV_POWER_RESET_PWD__##e)
+#define BFM_POWER_RESET_PWD_V(v)        BM_POWER_RESET_PWD
+
+#define HW_POWER_DEBUG                          HW(POWER_DEBUG)
+#define HWA_POWER_DEBUG                         (0x80044000 + 0xf0)
+#define HWT_POWER_DEBUG                         HWIO_32_RW
+#define HWN_POWER_DEBUG                         POWER_DEBUG
+#define HWI_POWER_DEBUG                         
+#define HW_POWER_DEBUG_SET                      HW(POWER_DEBUG_SET)
+#define HWA_POWER_DEBUG_SET                     (HWA_POWER_DEBUG + 0x4)
+#define HWT_POWER_DEBUG_SET                     HWIO_32_WO
+#define HWN_POWER_DEBUG_SET                     POWER_DEBUG
+#define HWI_POWER_DEBUG_SET                     
+#define HW_POWER_DEBUG_CLR                      HW(POWER_DEBUG_CLR)
+#define HWA_POWER_DEBUG_CLR                     (HWA_POWER_DEBUG + 0x8)
+#define HWT_POWER_DEBUG_CLR                     HWIO_32_WO
+#define HWN_POWER_DEBUG_CLR                     POWER_DEBUG
+#define HWI_POWER_DEBUG_CLR                     
+#define HW_POWER_DEBUG_TOG                      HW(POWER_DEBUG_TOG)
+#define HWA_POWER_DEBUG_TOG                     (HWA_POWER_DEBUG + 0xc)
+#define HWT_POWER_DEBUG_TOG                     HWIO_32_WO
+#define HWN_POWER_DEBUG_TOG                     POWER_DEBUG
+#define HWI_POWER_DEBUG_TOG                     
+#define BP_POWER_DEBUG_VBUSVALIDPIOLOCK         3
+#define BM_POWER_DEBUG_VBUSVALIDPIOLOCK         0x8
+#define BF_POWER_DEBUG_VBUSVALIDPIOLOCK(v)      (((v) & 0x1) << 3)
+#define BFM_POWER_DEBUG_VBUSVALIDPIOLOCK(v)     BM_POWER_DEBUG_VBUSVALIDPIOLOCK
+#define BF_POWER_DEBUG_VBUSVALIDPIOLOCK_V(e)    BF_POWER_DEBUG_VBUSVALIDPIOLOCK(BV_POWER_DEBUG_VBUSVALIDPIOLOCK__##e)
+#define BFM_POWER_DEBUG_VBUSVALIDPIOLOCK_V(v)   BM_POWER_DEBUG_VBUSVALIDPIOLOCK
+#define BP_POWER_DEBUG_AVALIDPIOLOCK            2
+#define BM_POWER_DEBUG_AVALIDPIOLOCK            0x4
+#define BF_POWER_DEBUG_AVALIDPIOLOCK(v)         (((v) & 0x1) << 2)
+#define BFM_POWER_DEBUG_AVALIDPIOLOCK(v)        BM_POWER_DEBUG_AVALIDPIOLOCK
+#define BF_POWER_DEBUG_AVALIDPIOLOCK_V(e)       BF_POWER_DEBUG_AVALIDPIOLOCK(BV_POWER_DEBUG_AVALIDPIOLOCK__##e)
+#define BFM_POWER_DEBUG_AVALIDPIOLOCK_V(v)      BM_POWER_DEBUG_AVALIDPIOLOCK
+#define BP_POWER_DEBUG_BVALIDPIOLOCK            1
+#define BM_POWER_DEBUG_BVALIDPIOLOCK            0x2
+#define BF_POWER_DEBUG_BVALIDPIOLOCK(v)         (((v) & 0x1) << 1)
+#define BFM_POWER_DEBUG_BVALIDPIOLOCK(v)        BM_POWER_DEBUG_BVALIDPIOLOCK
+#define BF_POWER_DEBUG_BVALIDPIOLOCK_V(e)       BF_POWER_DEBUG_BVALIDPIOLOCK(BV_POWER_DEBUG_BVALIDPIOLOCK__##e)
+#define BFM_POWER_DEBUG_BVALIDPIOLOCK_V(v)      BM_POWER_DEBUG_BVALIDPIOLOCK
+#define BP_POWER_DEBUG_SESSENDPIOLOCK           0
+#define BM_POWER_DEBUG_SESSENDPIOLOCK           0x1
+#define BF_POWER_DEBUG_SESSENDPIOLOCK(v)        (((v) & 0x1) << 0)
+#define BFM_POWER_DEBUG_SESSENDPIOLOCK(v)       BM_POWER_DEBUG_SESSENDPIOLOCK
+#define BF_POWER_DEBUG_SESSENDPIOLOCK_V(e)      BF_POWER_DEBUG_SESSENDPIOLOCK(BV_POWER_DEBUG_SESSENDPIOLOCK__##e)
+#define BFM_POWER_DEBUG_SESSENDPIOLOCK_V(v)     BM_POWER_DEBUG_SESSENDPIOLOCK
+
+#define HW_POWER_SPECIAL            HW(POWER_SPECIAL)
+#define HWA_POWER_SPECIAL           (0x80044000 + 0x100)
+#define HWT_POWER_SPECIAL           HWIO_32_RW
+#define HWN_POWER_SPECIAL           POWER_SPECIAL
+#define HWI_POWER_SPECIAL           
+#define HW_POWER_SPECIAL_SET        HW(POWER_SPECIAL_SET)
+#define HWA_POWER_SPECIAL_SET       (HWA_POWER_SPECIAL + 0x4)
+#define HWT_POWER_SPECIAL_SET       HWIO_32_WO
+#define HWN_POWER_SPECIAL_SET       POWER_SPECIAL
+#define HWI_POWER_SPECIAL_SET       
+#define HW_POWER_SPECIAL_CLR        HW(POWER_SPECIAL_CLR)
+#define HWA_POWER_SPECIAL_CLR       (HWA_POWER_SPECIAL + 0x8)
+#define HWT_POWER_SPECIAL_CLR       HWIO_32_WO
+#define HWN_POWER_SPECIAL_CLR       POWER_SPECIAL
+#define HWI_POWER_SPECIAL_CLR       
+#define HW_POWER_SPECIAL_TOG        HW(POWER_SPECIAL_TOG)
+#define HWA_POWER_SPECIAL_TOG       (HWA_POWER_SPECIAL + 0xc)
+#define HWT_POWER_SPECIAL_TOG       HWIO_32_WO
+#define HWN_POWER_SPECIAL_TOG       POWER_SPECIAL
+#define HWI_POWER_SPECIAL_TOG       
+#define BP_POWER_SPECIAL_TEST       0
+#define BM_POWER_SPECIAL_TEST       0xffffffff
+#define BF_POWER_SPECIAL_TEST(v)    (((v) & 0xffffffff) << 0)
+#define BFM_POWER_SPECIAL_TEST(v)   BM_POWER_SPECIAL_TEST
+#define BF_POWER_SPECIAL_TEST_V(e)  BF_POWER_SPECIAL_TEST(BV_POWER_SPECIAL_TEST__##e)
+#define BFM_POWER_SPECIAL_TEST_V(v) BM_POWER_SPECIAL_TEST
+
+#define HW_POWER_VERSION                HW(POWER_VERSION)
+#define HWA_POWER_VERSION               (0x80044000 + 0x110)
+#define HWT_POWER_VERSION               HWIO_32_RW
+#define HWN_POWER_VERSION               POWER_VERSION
+#define HWI_POWER_VERSION               
+#define BP_POWER_VERSION_MAJOR          24
+#define BM_POWER_VERSION_MAJOR          0xff000000
+#define BF_POWER_VERSION_MAJOR(v)       (((v) & 0xff) << 24)
+#define BFM_POWER_VERSION_MAJOR(v)      BM_POWER_VERSION_MAJOR
+#define BF_POWER_VERSION_MAJOR_V(e)     BF_POWER_VERSION_MAJOR(BV_POWER_VERSION_MAJOR__##e)
+#define BFM_POWER_VERSION_MAJOR_V(v)    BM_POWER_VERSION_MAJOR
+#define BP_POWER_VERSION_MINOR          16
+#define BM_POWER_VERSION_MINOR          0xff0000
+#define BF_POWER_VERSION_MINOR(v)       (((v) & 0xff) << 16)
+#define BFM_POWER_VERSION_MINOR(v)      BM_POWER_VERSION_MINOR
+#define BF_POWER_VERSION_MINOR_V(e)     BF_POWER_VERSION_MINOR(BV_POWER_VERSION_MINOR__##e)
+#define BFM_POWER_VERSION_MINOR_V(v)    BM_POWER_VERSION_MINOR
+#define BP_POWER_VERSION_STEP           0
+#define BM_POWER_VERSION_STEP           0xffff
+#define BF_POWER_VERSION_STEP(v)        (((v) & 0xffff) << 0)
+#define BFM_POWER_VERSION_STEP(v)       BM_POWER_VERSION_STEP
+#define BF_POWER_VERSION_STEP_V(e)      BF_POWER_VERSION_STEP(BV_POWER_VERSION_STEP__##e)
+#define BFM_POWER_VERSION_STEP_V(v)     BM_POWER_VERSION_STEP
+
+#endif /* __HEADERGEN_STMP3700_POWER_H__*/
diff --git a/firmware/target/arm/imx233/regs/stmp3700/pwm.h b/firmware/target/arm/imx233/regs/stmp3700/pwm.h
new file mode 100644
index 0000000000..45326aaa89
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3700/pwm.h
@@ -0,0 +1,248 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * stmp3700 version: 2.4.0
+ * stmp3700 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_STMP3700_PWM_H__
+#define __HEADERGEN_STMP3700_PWM_H__
+
+#define HW_PWM_CTRL                             HW(PWM_CTRL)
+#define HWA_PWM_CTRL                            (0x80064000 + 0x0)
+#define HWT_PWM_CTRL                            HWIO_32_RW
+#define HWN_PWM_CTRL                            PWM_CTRL
+#define HWI_PWM_CTRL                            
+#define HW_PWM_CTRL_SET                         HW(PWM_CTRL_SET)
+#define HWA_PWM_CTRL_SET                        (HWA_PWM_CTRL + 0x4)
+#define HWT_PWM_CTRL_SET                        HWIO_32_WO
+#define HWN_PWM_CTRL_SET                        PWM_CTRL
+#define HWI_PWM_CTRL_SET                        
+#define HW_PWM_CTRL_CLR                         HW(PWM_CTRL_CLR)
+#define HWA_PWM_CTRL_CLR                        (HWA_PWM_CTRL + 0x8)
+#define HWT_PWM_CTRL_CLR                        HWIO_32_WO
+#define HWN_PWM_CTRL_CLR                        PWM_CTRL
+#define HWI_PWM_CTRL_CLR                        
+#define HW_PWM_CTRL_TOG                         HW(PWM_CTRL_TOG)
+#define HWA_PWM_CTRL_TOG                        (HWA_PWM_CTRL + 0xc)
+#define HWT_PWM_CTRL_TOG                        HWIO_32_WO
+#define HWN_PWM_CTRL_TOG                        PWM_CTRL
+#define HWI_PWM_CTRL_TOG                        
+#define BP_PWM_CTRL_SFTRST                      31
+#define BM_PWM_CTRL_SFTRST                      0x80000000
+#define BF_PWM_CTRL_SFTRST(v)                   (((v) & 0x1) << 31)
+#define BFM_PWM_CTRL_SFTRST(v)                  BM_PWM_CTRL_SFTRST
+#define BF_PWM_CTRL_SFTRST_V(e)                 BF_PWM_CTRL_SFTRST(BV_PWM_CTRL_SFTRST__##e)
+#define BFM_PWM_CTRL_SFTRST_V(v)                BM_PWM_CTRL_SFTRST
+#define BP_PWM_CTRL_CLKGATE                     30
+#define BM_PWM_CTRL_CLKGATE                     0x40000000
+#define BF_PWM_CTRL_CLKGATE(v)                  (((v) & 0x1) << 30)
+#define BFM_PWM_CTRL_CLKGATE(v)                 BM_PWM_CTRL_CLKGATE
+#define BF_PWM_CTRL_CLKGATE_V(e)                BF_PWM_CTRL_CLKGATE(BV_PWM_CTRL_CLKGATE__##e)
+#define BFM_PWM_CTRL_CLKGATE_V(v)               BM_PWM_CTRL_CLKGATE
+#define BP_PWM_CTRL_PWM4_PRESENT                29
+#define BM_PWM_CTRL_PWM4_PRESENT                0x20000000
+#define BF_PWM_CTRL_PWM4_PRESENT(v)             (((v) & 0x1) << 29)
+#define BFM_PWM_CTRL_PWM4_PRESENT(v)            BM_PWM_CTRL_PWM4_PRESENT
+#define BF_PWM_CTRL_PWM4_PRESENT_V(e)           BF_PWM_CTRL_PWM4_PRESENT(BV_PWM_CTRL_PWM4_PRESENT__##e)
+#define BFM_PWM_CTRL_PWM4_PRESENT_V(v)          BM_PWM_CTRL_PWM4_PRESENT
+#define BP_PWM_CTRL_PWM3_PRESENT                28
+#define BM_PWM_CTRL_PWM3_PRESENT                0x10000000
+#define BF_PWM_CTRL_PWM3_PRESENT(v)             (((v) & 0x1) << 28)
+#define BFM_PWM_CTRL_PWM3_PRESENT(v)            BM_PWM_CTRL_PWM3_PRESENT
+#define BF_PWM_CTRL_PWM3_PRESENT_V(e)           BF_PWM_CTRL_PWM3_PRESENT(BV_PWM_CTRL_PWM3_PRESENT__##e)
+#define BFM_PWM_CTRL_PWM3_PRESENT_V(v)          BM_PWM_CTRL_PWM3_PRESENT
+#define BP_PWM_CTRL_PWM2_PRESENT                27
+#define BM_PWM_CTRL_PWM2_PRESENT                0x8000000
+#define BF_PWM_CTRL_PWM2_PRESENT(v)             (((v) & 0x1) << 27)
+#define BFM_PWM_CTRL_PWM2_PRESENT(v)            BM_PWM_CTRL_PWM2_PRESENT
+#define BF_PWM_CTRL_PWM2_PRESENT_V(e)           BF_PWM_CTRL_PWM2_PRESENT(BV_PWM_CTRL_PWM2_PRESENT__##e)
+#define BFM_PWM_CTRL_PWM2_PRESENT_V(v)          BM_PWM_CTRL_PWM2_PRESENT
+#define BP_PWM_CTRL_PWM1_PRESENT                26
+#define BM_PWM_CTRL_PWM1_PRESENT                0x4000000
+#define BF_PWM_CTRL_PWM1_PRESENT(v)             (((v) & 0x1) << 26)
+#define BFM_PWM_CTRL_PWM1_PRESENT(v)            BM_PWM_CTRL_PWM1_PRESENT
+#define BF_PWM_CTRL_PWM1_PRESENT_V(e)           BF_PWM_CTRL_PWM1_PRESENT(BV_PWM_CTRL_PWM1_PRESENT__##e)
+#define BFM_PWM_CTRL_PWM1_PRESENT_V(v)          BM_PWM_CTRL_PWM1_PRESENT
+#define BP_PWM_CTRL_PWM0_PRESENT                25
+#define BM_PWM_CTRL_PWM0_PRESENT                0x2000000
+#define BF_PWM_CTRL_PWM0_PRESENT(v)             (((v) & 0x1) << 25)
+#define BFM_PWM_CTRL_PWM0_PRESENT(v)            BM_PWM_CTRL_PWM0_PRESENT
+#define BF_PWM_CTRL_PWM0_PRESENT_V(e)           BF_PWM_CTRL_PWM0_PRESENT(BV_PWM_CTRL_PWM0_PRESENT__##e)
+#define BFM_PWM_CTRL_PWM0_PRESENT_V(v)          BM_PWM_CTRL_PWM0_PRESENT
+#define BP_PWM_CTRL_PWM2_ANA_CTRL_ENABLE        5
+#define BM_PWM_CTRL_PWM2_ANA_CTRL_ENABLE        0x20
+#define BF_PWM_CTRL_PWM2_ANA_CTRL_ENABLE(v)     (((v) & 0x1) << 5)
+#define BFM_PWM_CTRL_PWM2_ANA_CTRL_ENABLE(v)    BM_PWM_CTRL_PWM2_ANA_CTRL_ENABLE
+#define BF_PWM_CTRL_PWM2_ANA_CTRL_ENABLE_V(e)   BF_PWM_CTRL_PWM2_ANA_CTRL_ENABLE(BV_PWM_CTRL_PWM2_ANA_CTRL_ENABLE__##e)
+#define BFM_PWM_CTRL_PWM2_ANA_CTRL_ENABLE_V(v)  BM_PWM_CTRL_PWM2_ANA_CTRL_ENABLE
+#define BP_PWM_CTRL_PWM4_ENABLE                 4
+#define BM_PWM_CTRL_PWM4_ENABLE                 0x10
+#define BF_PWM_CTRL_PWM4_ENABLE(v)              (((v) & 0x1) << 4)
+#define BFM_PWM_CTRL_PWM4_ENABLE(v)             BM_PWM_CTRL_PWM4_ENABLE
+#define BF_PWM_CTRL_PWM4_ENABLE_V(e)            BF_PWM_CTRL_PWM4_ENABLE(BV_PWM_CTRL_PWM4_ENABLE__##e)
+#define BFM_PWM_CTRL_PWM4_ENABLE_V(v)           BM_PWM_CTRL_PWM4_ENABLE
+#define BP_PWM_CTRL_PWM3_ENABLE                 3
+#define BM_PWM_CTRL_PWM3_ENABLE                 0x8
+#define BF_PWM_CTRL_PWM3_ENABLE(v)              (((v) & 0x1) << 3)
+#define BFM_PWM_CTRL_PWM3_ENABLE(v)             BM_PWM_CTRL_PWM3_ENABLE
+#define BF_PWM_CTRL_PWM3_ENABLE_V(e)            BF_PWM_CTRL_PWM3_ENABLE(BV_PWM_CTRL_PWM3_ENABLE__##e)
+#define BFM_PWM_CTRL_PWM3_ENABLE_V(v)           BM_PWM_CTRL_PWM3_ENABLE
+#define BP_PWM_CTRL_PWM2_ENABLE                 2
+#define BM_PWM_CTRL_PWM2_ENABLE                 0x4
+#define BF_PWM_CTRL_PWM2_ENABLE(v)              (((v) & 0x1) << 2)
+#define BFM_PWM_CTRL_PWM2_ENABLE(v)             BM_PWM_CTRL_PWM2_ENABLE
+#define BF_PWM_CTRL_PWM2_ENABLE_V(e)            BF_PWM_CTRL_PWM2_ENABLE(BV_PWM_CTRL_PWM2_ENABLE__##e)
+#define BFM_PWM_CTRL_PWM2_ENABLE_V(v)           BM_PWM_CTRL_PWM2_ENABLE
+#define BP_PWM_CTRL_PWM1_ENABLE                 1
+#define BM_PWM_CTRL_PWM1_ENABLE                 0x2
+#define BF_PWM_CTRL_PWM1_ENABLE(v)              (((v) & 0x1) << 1)
+#define BFM_PWM_CTRL_PWM1_ENABLE(v)             BM_PWM_CTRL_PWM1_ENABLE
+#define BF_PWM_CTRL_PWM1_ENABLE_V(e)            BF_PWM_CTRL_PWM1_ENABLE(BV_PWM_CTRL_PWM1_ENABLE__##e)
+#define BFM_PWM_CTRL_PWM1_ENABLE_V(v)           BM_PWM_CTRL_PWM1_ENABLE
+#define BP_PWM_CTRL_PWM0_ENABLE                 0
+#define BM_PWM_CTRL_PWM0_ENABLE                 0x1
+#define BF_PWM_CTRL_PWM0_ENABLE(v)              (((v) & 0x1) << 0)
+#define BFM_PWM_CTRL_PWM0_ENABLE(v)             BM_PWM_CTRL_PWM0_ENABLE
+#define BF_PWM_CTRL_PWM0_ENABLE_V(e)            BF_PWM_CTRL_PWM0_ENABLE(BV_PWM_CTRL_PWM0_ENABLE__##e)
+#define BFM_PWM_CTRL_PWM0_ENABLE_V(v)           BM_PWM_CTRL_PWM0_ENABLE
+
+#define HW_PWM_ACTIVEn(_n1)             HW(PWM_ACTIVEn(_n1))
+#define HWA_PWM_ACTIVEn(_n1)            (0x80064000 + 0x10 + (_n1) * 0x20)
+#define HWT_PWM_ACTIVEn(_n1)            HWIO_32_RW
+#define HWN_PWM_ACTIVEn(_n1)            PWM_ACTIVEn
+#define HWI_PWM_ACTIVEn(_n1)            (_n1)
+#define HW_PWM_ACTIVEn_SET(_n1)         HW(PWM_ACTIVEn_SET(_n1))
+#define HWA_PWM_ACTIVEn_SET(_n1)        (HWA_PWM_ACTIVEn(_n1) + 0x4)
+#define HWT_PWM_ACTIVEn_SET(_n1)        HWIO_32_WO
+#define HWN_PWM_ACTIVEn_SET(_n1)        PWM_ACTIVEn
+#define HWI_PWM_ACTIVEn_SET(_n1)        (_n1)
+#define HW_PWM_ACTIVEn_CLR(_n1)         HW(PWM_ACTIVEn_CLR(_n1))
+#define HWA_PWM_ACTIVEn_CLR(_n1)        (HWA_PWM_ACTIVEn(_n1) + 0x8)
+#define HWT_PWM_ACTIVEn_CLR(_n1)        HWIO_32_WO
+#define HWN_PWM_ACTIVEn_CLR(_n1)        PWM_ACTIVEn
+#define HWI_PWM_ACTIVEn_CLR(_n1)        (_n1)
+#define HW_PWM_ACTIVEn_TOG(_n1)         HW(PWM_ACTIVEn_TOG(_n1))
+#define HWA_PWM_ACTIVEn_TOG(_n1)        (HWA_PWM_ACTIVEn(_n1) + 0xc)
+#define HWT_PWM_ACTIVEn_TOG(_n1)        HWIO_32_WO
+#define HWN_PWM_ACTIVEn_TOG(_n1)        PWM_ACTIVEn
+#define HWI_PWM_ACTIVEn_TOG(_n1)        (_n1)
+#define BP_PWM_ACTIVEn_INACTIVE         16
+#define BM_PWM_ACTIVEn_INACTIVE         0xffff0000
+#define BF_PWM_ACTIVEn_INACTIVE(v)      (((v) & 0xffff) << 16)
+#define BFM_PWM_ACTIVEn_INACTIVE(v)     BM_PWM_ACTIVEn_INACTIVE
+#define BF_PWM_ACTIVEn_INACTIVE_V(e)    BF_PWM_ACTIVEn_INACTIVE(BV_PWM_ACTIVEn_INACTIVE__##e)
+#define BFM_PWM_ACTIVEn_INACTIVE_V(v)   BM_PWM_ACTIVEn_INACTIVE
+#define BP_PWM_ACTIVEn_ACTIVE           0
+#define BM_PWM_ACTIVEn_ACTIVE           0xffff
+#define BF_PWM_ACTIVEn_ACTIVE(v)        (((v) & 0xffff) << 0)
+#define BFM_PWM_ACTIVEn_ACTIVE(v)       BM_PWM_ACTIVEn_ACTIVE
+#define BF_PWM_ACTIVEn_ACTIVE_V(e)      BF_PWM_ACTIVEn_ACTIVE(BV_PWM_ACTIVEn_ACTIVE__##e)
+#define BFM_PWM_ACTIVEn_ACTIVE_V(v)     BM_PWM_ACTIVEn_ACTIVE
+
+#define HW_PWM_PERIODn(_n1)                 HW(PWM_PERIODn(_n1))
+#define HWA_PWM_PERIODn(_n1)                (0x80064000 + 0x20 + (_n1) * 0x20)
+#define HWT_PWM_PERIODn(_n1)                HWIO_32_RW
+#define HWN_PWM_PERIODn(_n1)                PWM_PERIODn
+#define HWI_PWM_PERIODn(_n1)                (_n1)
+#define HW_PWM_PERIODn_SET(_n1)             HW(PWM_PERIODn_SET(_n1))
+#define HWA_PWM_PERIODn_SET(_n1)            (HWA_PWM_PERIODn(_n1) + 0x4)
+#define HWT_PWM_PERIODn_SET(_n1)            HWIO_32_WO
+#define HWN_PWM_PERIODn_SET(_n1)            PWM_PERIODn
+#define HWI_PWM_PERIODn_SET(_n1)            (_n1)
+#define HW_PWM_PERIODn_CLR(_n1)             HW(PWM_PERIODn_CLR(_n1))
+#define HWA_PWM_PERIODn_CLR(_n1)            (HWA_PWM_PERIODn(_n1) + 0x8)
+#define HWT_PWM_PERIODn_CLR(_n1)            HWIO_32_WO
+#define HWN_PWM_PERIODn_CLR(_n1)            PWM_PERIODn
+#define HWI_PWM_PERIODn_CLR(_n1)            (_n1)
+#define HW_PWM_PERIODn_TOG(_n1)             HW(PWM_PERIODn_TOG(_n1))
+#define HWA_PWM_PERIODn_TOG(_n1)            (HWA_PWM_PERIODn(_n1) + 0xc)
+#define HWT_PWM_PERIODn_TOG(_n1)            HWIO_32_WO
+#define HWN_PWM_PERIODn_TOG(_n1)            PWM_PERIODn
+#define HWI_PWM_PERIODn_TOG(_n1)            (_n1)
+#define BP_PWM_PERIODn_MATT                 23
+#define BM_PWM_PERIODn_MATT                 0x800000
+#define BF_PWM_PERIODn_MATT(v)              (((v) & 0x1) << 23)
+#define BFM_PWM_PERIODn_MATT(v)             BM_PWM_PERIODn_MATT
+#define BF_PWM_PERIODn_MATT_V(e)            BF_PWM_PERIODn_MATT(BV_PWM_PERIODn_MATT__##e)
+#define BFM_PWM_PERIODn_MATT_V(v)           BM_PWM_PERIODn_MATT
+#define BP_PWM_PERIODn_CDIV                 20
+#define BM_PWM_PERIODn_CDIV                 0x700000
+#define BV_PWM_PERIODn_CDIV__DIV_1          0x0
+#define BV_PWM_PERIODn_CDIV__DIV_2          0x1
+#define BV_PWM_PERIODn_CDIV__DIV_4          0x2
+#define BV_PWM_PERIODn_CDIV__DIV_8          0x3
+#define BV_PWM_PERIODn_CDIV__DIV_16         0x4
+#define BV_PWM_PERIODn_CDIV__DIV_64         0x5
+#define BV_PWM_PERIODn_CDIV__DIV_256        0x6
+#define BV_PWM_PERIODn_CDIV__DIV_1024       0x7
+#define BF_PWM_PERIODn_CDIV(v)              (((v) & 0x7) << 20)
+#define BFM_PWM_PERIODn_CDIV(v)             BM_PWM_PERIODn_CDIV
+#define BF_PWM_PERIODn_CDIV_V(e)            BF_PWM_PERIODn_CDIV(BV_PWM_PERIODn_CDIV__##e)
+#define BFM_PWM_PERIODn_CDIV_V(v)           BM_PWM_PERIODn_CDIV
+#define BP_PWM_PERIODn_INACTIVE_STATE       18
+#define BM_PWM_PERIODn_INACTIVE_STATE       0xc0000
+#define BV_PWM_PERIODn_INACTIVE_STATE__HI_Z 0x0
+#define BV_PWM_PERIODn_INACTIVE_STATE__0    0x2
+#define BV_PWM_PERIODn_INACTIVE_STATE__1    0x3
+#define BF_PWM_PERIODn_INACTIVE_STATE(v)    (((v) & 0x3) << 18)
+#define BFM_PWM_PERIODn_INACTIVE_STATE(v)   BM_PWM_PERIODn_INACTIVE_STATE
+#define BF_PWM_PERIODn_INACTIVE_STATE_V(e)  BF_PWM_PERIODn_INACTIVE_STATE(BV_PWM_PERIODn_INACTIVE_STATE__##e)
+#define BFM_PWM_PERIODn_INACTIVE_STATE_V(v) BM_PWM_PERIODn_INACTIVE_STATE
+#define BP_PWM_PERIODn_ACTIVE_STATE         16
+#define BM_PWM_PERIODn_ACTIVE_STATE         0x30000
+#define BV_PWM_PERIODn_ACTIVE_STATE__HI_Z   0x0
+#define BV_PWM_PERIODn_ACTIVE_STATE__0      0x2
+#define BV_PWM_PERIODn_ACTIVE_STATE__1      0x3
+#define BF_PWM_PERIODn_ACTIVE_STATE(v)      (((v) & 0x3) << 16)
+#define BFM_PWM_PERIODn_ACTIVE_STATE(v)     BM_PWM_PERIODn_ACTIVE_STATE
+#define BF_PWM_PERIODn_ACTIVE_STATE_V(e)    BF_PWM_PERIODn_ACTIVE_STATE(BV_PWM_PERIODn_ACTIVE_STATE__##e)
+#define BFM_PWM_PERIODn_ACTIVE_STATE_V(v)   BM_PWM_PERIODn_ACTIVE_STATE
+#define BP_PWM_PERIODn_PERIOD               0
+#define BM_PWM_PERIODn_PERIOD               0xffff
+#define BF_PWM_PERIODn_PERIOD(v)            (((v) & 0xffff) << 0)
+#define BFM_PWM_PERIODn_PERIOD(v)           BM_PWM_PERIODn_PERIOD
+#define BF_PWM_PERIODn_PERIOD_V(e)          BF_PWM_PERIODn_PERIOD(BV_PWM_PERIODn_PERIOD__##e)
+#define BFM_PWM_PERIODn_PERIOD_V(v)         BM_PWM_PERIODn_PERIOD
+
+#define HW_PWM_VERSION              HW(PWM_VERSION)
+#define HWA_PWM_VERSION             (0x80064000 + 0xb0)
+#define HWT_PWM_VERSION             HWIO_32_RW
+#define HWN_PWM_VERSION             PWM_VERSION
+#define HWI_PWM_VERSION             
+#define BP_PWM_VERSION_MAJOR        24
+#define BM_PWM_VERSION_MAJOR        0xff000000
+#define BF_PWM_VERSION_MAJOR(v)     (((v) & 0xff) << 24)
+#define BFM_PWM_VERSION_MAJOR(v)    BM_PWM_VERSION_MAJOR
+#define BF_PWM_VERSION_MAJOR_V(e)   BF_PWM_VERSION_MAJOR(BV_PWM_VERSION_MAJOR__##e)
+#define BFM_PWM_VERSION_MAJOR_V(v)  BM_PWM_VERSION_MAJOR
+#define BP_PWM_VERSION_MINOR        16
+#define BM_PWM_VERSION_MINOR        0xff0000
+#define BF_PWM_VERSION_MINOR(v)     (((v) & 0xff) << 16)
+#define BFM_PWM_VERSION_MINOR(v)    BM_PWM_VERSION_MINOR
+#define BF_PWM_VERSION_MINOR_V(e)   BF_PWM_VERSION_MINOR(BV_PWM_VERSION_MINOR__##e)
+#define BFM_PWM_VERSION_MINOR_V(v)  BM_PWM_VERSION_MINOR
+#define BP_PWM_VERSION_STEP         0
+#define BM_PWM_VERSION_STEP         0xffff
+#define BF_PWM_VERSION_STEP(v)      (((v) & 0xffff) << 0)
+#define BFM_PWM_VERSION_STEP(v)     BM_PWM_VERSION_STEP
+#define BF_PWM_VERSION_STEP_V(e)    BF_PWM_VERSION_STEP(BV_PWM_VERSION_STEP__##e)
+#define BFM_PWM_VERSION_STEP_V(v)   BM_PWM_VERSION_STEP
+
+#endif /* __HEADERGEN_STMP3700_PWM_H__*/
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-apbh.h b/firmware/target/arm/imx233/regs/stmp3700/regs-apbh.h
deleted file mode 100644
index 5dfc5c0f3b..0000000000
--- a/firmware/target/arm/imx233/regs/stmp3700/regs-apbh.h
+++ /dev/null
@@ -1,301 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3700:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__STMP3700__APBH__H__
-#define __HEADERGEN__STMP3700__APBH__H__
-
-#define REGS_APBH_BASE (0x80004000)
-
-#define REGS_APBH_VERSION "3.2.0"
-
-/**
- * Register: HW_APBH_CTRL0
- * Address: 0
- * SCT: yes
-*/
-#define HW_APBH_CTRL0                           (*(volatile unsigned long *)(REGS_APBH_BASE + 0x0 + 0x0))
-#define HW_APBH_CTRL0_SET                       (*(volatile unsigned long *)(REGS_APBH_BASE + 0x0 + 0x4))
-#define HW_APBH_CTRL0_CLR                       (*(volatile unsigned long *)(REGS_APBH_BASE + 0x0 + 0x8))
-#define HW_APBH_CTRL0_TOG                       (*(volatile unsigned long *)(REGS_APBH_BASE + 0x0 + 0xc))
-#define BP_APBH_CTRL0_SFTRST                    31
-#define BM_APBH_CTRL0_SFTRST                    0x80000000
-#define BF_APBH_CTRL0_SFTRST(v)                 (((v) << 31) & 0x80000000)
-#define BP_APBH_CTRL0_CLKGATE                   30
-#define BM_APBH_CTRL0_CLKGATE                   0x40000000
-#define BF_APBH_CTRL0_CLKGATE(v)                (((v) << 30) & 0x40000000)
-#define BP_APBH_CTRL0_RESET_CHANNEL             16
-#define BM_APBH_CTRL0_RESET_CHANNEL             0xff0000
-#define BV_APBH_CTRL0_RESET_CHANNEL__SSP1       0x1
-#define BV_APBH_CTRL0_RESET_CHANNEL__SSP2       0x2
-#define BV_APBH_CTRL0_RESET_CHANNEL__LCDIF      0x4
-#define BV_APBH_CTRL0_RESET_CHANNEL__ATA        0x10
-#define BV_APBH_CTRL0_RESET_CHANNEL__NAND0      0x10
-#define BV_APBH_CTRL0_RESET_CHANNEL__NAND1      0x20
-#define BV_APBH_CTRL0_RESET_CHANNEL__NAND2      0x40
-#define BV_APBH_CTRL0_RESET_CHANNEL__NAND3      0x80
-#define BF_APBH_CTRL0_RESET_CHANNEL(v)          (((v) << 16) & 0xff0000)
-#define BF_APBH_CTRL0_RESET_CHANNEL_V(v)        ((BV_APBH_CTRL0_RESET_CHANNEL__##v << 16) & 0xff0000)
-#define BP_APBH_CTRL0_CLKGATE_CHANNEL           8
-#define BM_APBH_CTRL0_CLKGATE_CHANNEL           0xff00
-#define BV_APBH_CTRL0_CLKGATE_CHANNEL__SSP1     0x1
-#define BV_APBH_CTRL0_CLKGATE_CHANNEL__SSP2     0x2
-#define BV_APBH_CTRL0_CLKGATE_CHANNEL__LCDIF    0x4
-#define BV_APBH_CTRL0_CLKGATE_CHANNEL__ATA      0x10
-#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND0    0x10
-#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND1    0x20
-#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND2    0x40
-#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND3    0x80
-#define BF_APBH_CTRL0_CLKGATE_CHANNEL(v)        (((v) << 8) & 0xff00)
-#define BF_APBH_CTRL0_CLKGATE_CHANNEL_V(v)      ((BV_APBH_CTRL0_CLKGATE_CHANNEL__##v << 8) & 0xff00)
-#define BP_APBH_CTRL0_FREEZE_CHANNEL            0
-#define BM_APBH_CTRL0_FREEZE_CHANNEL            0xff
-#define BV_APBH_CTRL0_FREEZE_CHANNEL__SSP1      0x1
-#define BV_APBH_CTRL0_FREEZE_CHANNEL__SSP2      0x2
-#define BV_APBH_CTRL0_FREEZE_CHANNEL__LCDIF     0x4
-#define BV_APBH_CTRL0_FREEZE_CHANNEL__ATA       0x10
-#define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND0     0x10
-#define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND1     0x20
-#define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND2     0x30
-#define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND3     0x40
-#define BF_APBH_CTRL0_FREEZE_CHANNEL(v)         (((v) << 0) & 0xff)
-#define BF_APBH_CTRL0_FREEZE_CHANNEL_V(v)       ((BV_APBH_CTRL0_FREEZE_CHANNEL__##v << 0) & 0xff)
-
-/**
- * Register: HW_APBH_CTRL1
- * Address: 0x10
- * SCT: yes
-*/
-#define HW_APBH_CTRL1                       (*(volatile unsigned long *)(REGS_APBH_BASE + 0x10 + 0x0))
-#define HW_APBH_CTRL1_SET                   (*(volatile unsigned long *)(REGS_APBH_BASE + 0x10 + 0x4))
-#define HW_APBH_CTRL1_CLR                   (*(volatile unsigned long *)(REGS_APBH_BASE + 0x10 + 0x8))
-#define HW_APBH_CTRL1_TOG                   (*(volatile unsigned long *)(REGS_APBH_BASE + 0x10 + 0xc))
-#define BP_APBH_CTRL1_CH_AHB_ERROR_IRQ      16
-#define BM_APBH_CTRL1_CH_AHB_ERROR_IRQ      0xff0000
-#define BF_APBH_CTRL1_CH_AHB_ERROR_IRQ(v)   (((v) << 16) & 0xff0000)
-#define BP_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN    8
-#define BM_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN    0xff00
-#define BF_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN(v) (((v) << 8) & 0xff00)
-#define BP_APBH_CTRL1_CH_CMDCMPLT_IRQ       0
-#define BM_APBH_CTRL1_CH_CMDCMPLT_IRQ       0xff
-#define BF_APBH_CTRL1_CH_CMDCMPLT_IRQ(v)    (((v) << 0) & 0xff)
-
-/**
- * Register: HW_APBH_DEVSEL
- * Address: 0x20
- * SCT: no
-*/
-#define HW_APBH_DEVSEL          (*(volatile unsigned long *)(REGS_APBH_BASE + 0x20))
-#define BP_APBH_DEVSEL_CH7      28
-#define BM_APBH_DEVSEL_CH7      0xf0000000
-#define BF_APBH_DEVSEL_CH7(v)   (((v) << 28) & 0xf0000000)
-#define BP_APBH_DEVSEL_CH6      24
-#define BM_APBH_DEVSEL_CH6      0xf000000
-#define BF_APBH_DEVSEL_CH6(v)   (((v) << 24) & 0xf000000)
-#define BP_APBH_DEVSEL_CH5      20
-#define BM_APBH_DEVSEL_CH5      0xf00000
-#define BF_APBH_DEVSEL_CH5(v)   (((v) << 20) & 0xf00000)
-#define BP_APBH_DEVSEL_CH4      16
-#define BM_APBH_DEVSEL_CH4      0xf0000
-#define BF_APBH_DEVSEL_CH4(v)   (((v) << 16) & 0xf0000)
-#define BP_APBH_DEVSEL_CH3      12
-#define BM_APBH_DEVSEL_CH3      0xf000
-#define BF_APBH_DEVSEL_CH3(v)   (((v) << 12) & 0xf000)
-#define BP_APBH_DEVSEL_CH2      8
-#define BM_APBH_DEVSEL_CH2      0xf00
-#define BF_APBH_DEVSEL_CH2(v)   (((v) << 8) & 0xf00)
-#define BP_APBH_DEVSEL_CH1      4
-#define BM_APBH_DEVSEL_CH1      0xf0
-#define BF_APBH_DEVSEL_CH1(v)   (((v) << 4) & 0xf0)
-#define BP_APBH_DEVSEL_CH0      0
-#define BM_APBH_DEVSEL_CH0      0xf
-#define BF_APBH_DEVSEL_CH0(v)   (((v) << 0) & 0xf)
-
-/**
- * Register: HW_APBH_CHn_CURCMDAR
- * Address: 0x40+n*0x70
- * SCT: no
-*/
-#define HW_APBH_CHn_CURCMDAR(n)             (*(volatile unsigned long *)(REGS_APBH_BASE + 0x40+(n)*0x70))
-#define BP_APBH_CHn_CURCMDAR_CMD_ADDR       0
-#define BM_APBH_CHn_CURCMDAR_CMD_ADDR       0xffffffff
-#define BF_APBH_CHn_CURCMDAR_CMD_ADDR(v)    (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_APBH_CHn_NXTCMDAR
- * Address: 0x50+n*0x70
- * SCT: no
-*/
-#define HW_APBH_CHn_NXTCMDAR(n)             (*(volatile unsigned long *)(REGS_APBH_BASE + 0x50+(n)*0x70))
-#define BP_APBH_CHn_NXTCMDAR_CMD_ADDR       0
-#define BM_APBH_CHn_NXTCMDAR_CMD_ADDR       0xffffffff
-#define BF_APBH_CHn_NXTCMDAR_CMD_ADDR(v)    (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_APBH_CHn_CMD
- * Address: 0x60+n*0x70
- * SCT: no
-*/
-#define HW_APBH_CHn_CMD(n)                      (*(volatile unsigned long *)(REGS_APBH_BASE + 0x60+(n)*0x70))
-#define BP_APBH_CHn_CMD_XFER_COUNT              16
-#define BM_APBH_CHn_CMD_XFER_COUNT              0xffff0000
-#define BF_APBH_CHn_CMD_XFER_COUNT(v)           (((v) << 16) & 0xffff0000)
-#define BP_APBH_CHn_CMD_CMDWORDS                12
-#define BM_APBH_CHn_CMD_CMDWORDS                0xf000
-#define BF_APBH_CHn_CMD_CMDWORDS(v)             (((v) << 12) & 0xf000)
-#define BP_APBH_CHn_CMD_HALTONTERMINATE         8
-#define BM_APBH_CHn_CMD_HALTONTERMINATE         0x100
-#define BF_APBH_CHn_CMD_HALTONTERMINATE(v)      (((v) << 8) & 0x100)
-#define BP_APBH_CHn_CMD_WAIT4ENDCMD             7
-#define BM_APBH_CHn_CMD_WAIT4ENDCMD             0x80
-#define BF_APBH_CHn_CMD_WAIT4ENDCMD(v)          (((v) << 7) & 0x80)
-#define BP_APBH_CHn_CMD_SEMAPHORE               6
-#define BM_APBH_CHn_CMD_SEMAPHORE               0x40
-#define BF_APBH_CHn_CMD_SEMAPHORE(v)            (((v) << 6) & 0x40)
-#define BP_APBH_CHn_CMD_NANDWAIT4READY          5
-#define BM_APBH_CHn_CMD_NANDWAIT4READY          0x20
-#define BF_APBH_CHn_CMD_NANDWAIT4READY(v)       (((v) << 5) & 0x20)
-#define BP_APBH_CHn_CMD_NANDLOCK                4
-#define BM_APBH_CHn_CMD_NANDLOCK                0x10
-#define BF_APBH_CHn_CMD_NANDLOCK(v)             (((v) << 4) & 0x10)
-#define BP_APBH_CHn_CMD_IRQONCMPLT              3
-#define BM_APBH_CHn_CMD_IRQONCMPLT              0x8
-#define BF_APBH_CHn_CMD_IRQONCMPLT(v)           (((v) << 3) & 0x8)
-#define BP_APBH_CHn_CMD_CHAIN                   2
-#define BM_APBH_CHn_CMD_CHAIN                   0x4
-#define BF_APBH_CHn_CMD_CHAIN(v)                (((v) << 2) & 0x4)
-#define BP_APBH_CHn_CMD_COMMAND                 0
-#define BM_APBH_CHn_CMD_COMMAND                 0x3
-#define BV_APBH_CHn_CMD_COMMAND__NO_DMA_XFER    0x0
-#define BV_APBH_CHn_CMD_COMMAND__DMA_WRITE      0x1
-#define BV_APBH_CHn_CMD_COMMAND__DMA_READ       0x2
-#define BV_APBH_CHn_CMD_COMMAND__DMA_SENSE      0x3
-#define BF_APBH_CHn_CMD_COMMAND(v)              (((v) << 0) & 0x3)
-#define BF_APBH_CHn_CMD_COMMAND_V(v)            ((BV_APBH_CHn_CMD_COMMAND__##v << 0) & 0x3)
-
-/**
- * Register: HW_APBH_CHn_BAR
- * Address: 0x70+n*0x70
- * SCT: no
-*/
-#define HW_APBH_CHn_BAR(n)          (*(volatile unsigned long *)(REGS_APBH_BASE + 0x70+(n)*0x70))
-#define BP_APBH_CHn_BAR_ADDRESS     0
-#define BM_APBH_CHn_BAR_ADDRESS     0xffffffff
-#define BF_APBH_CHn_BAR_ADDRESS(v)  (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_APBH_CHn_SEMA
- * Address: 0x80+n*0x70
- * SCT: no
-*/
-#define HW_APBH_CHn_SEMA(n)                 (*(volatile unsigned long *)(REGS_APBH_BASE + 0x80+(n)*0x70))
-#define BP_APBH_CHn_SEMA_PHORE              16
-#define BM_APBH_CHn_SEMA_PHORE              0xff0000
-#define BF_APBH_CHn_SEMA_PHORE(v)           (((v) << 16) & 0xff0000)
-#define BP_APBH_CHn_SEMA_INCREMENT_SEMA     0
-#define BM_APBH_CHn_SEMA_INCREMENT_SEMA     0xff
-#define BF_APBH_CHn_SEMA_INCREMENT_SEMA(v)  (((v) << 0) & 0xff)
-
-/**
- * Register: HW_APBH_CHn_DEBUG1
- * Address: 0x90+n*0x70
- * SCT: no
-*/
-#define HW_APBH_CHn_DEBUG1(n)                           (*(volatile unsigned long *)(REGS_APBH_BASE + 0x90+(n)*0x70))
-#define BP_APBH_CHn_DEBUG1_REQ                          31
-#define BM_APBH_CHn_DEBUG1_REQ                          0x80000000
-#define BF_APBH_CHn_DEBUG1_REQ(v)                       (((v) << 31) & 0x80000000)
-#define BP_APBH_CHn_DEBUG1_BURST                        30
-#define BM_APBH_CHn_DEBUG1_BURST                        0x40000000
-#define BF_APBH_CHn_DEBUG1_BURST(v)                     (((v) << 30) & 0x40000000)
-#define BP_APBH_CHn_DEBUG1_KICK                         29
-#define BM_APBH_CHn_DEBUG1_KICK                         0x20000000
-#define BF_APBH_CHn_DEBUG1_KICK(v)                      (((v) << 29) & 0x20000000)
-#define BP_APBH_CHn_DEBUG1_END                          28
-#define BM_APBH_CHn_DEBUG1_END                          0x10000000
-#define BF_APBH_CHn_DEBUG1_END(v)                       (((v) << 28) & 0x10000000)
-#define BP_APBH_CHn_DEBUG1_NEXTCMDADDRVALID             24
-#define BM_APBH_CHn_DEBUG1_NEXTCMDADDRVALID             0x1000000
-#define BF_APBH_CHn_DEBUG1_NEXTCMDADDRVALID(v)          (((v) << 24) & 0x1000000)
-#define BP_APBH_CHn_DEBUG1_RD_FIFO_EMPTY                23
-#define BM_APBH_CHn_DEBUG1_RD_FIFO_EMPTY                0x800000
-#define BF_APBH_CHn_DEBUG1_RD_FIFO_EMPTY(v)             (((v) << 23) & 0x800000)
-#define BP_APBH_CHn_DEBUG1_RD_FIFO_FULL                 22
-#define BM_APBH_CHn_DEBUG1_RD_FIFO_FULL                 0x400000
-#define BF_APBH_CHn_DEBUG1_RD_FIFO_FULL(v)              (((v) << 22) & 0x400000)
-#define BP_APBH_CHn_DEBUG1_WR_FIFO_EMPTY                21
-#define BM_APBH_CHn_DEBUG1_WR_FIFO_EMPTY                0x200000
-#define BF_APBH_CHn_DEBUG1_WR_FIFO_EMPTY(v)             (((v) << 21) & 0x200000)
-#define BP_APBH_CHn_DEBUG1_WR_FIFO_FULL                 20
-#define BM_APBH_CHn_DEBUG1_WR_FIFO_FULL                 0x100000
-#define BF_APBH_CHn_DEBUG1_WR_FIFO_FULL(v)              (((v) << 20) & 0x100000)
-#define BP_APBH_CHn_DEBUG1_STATEMACHINE                 0
-#define BM_APBH_CHn_DEBUG1_STATEMACHINE                 0x1f
-#define BV_APBH_CHn_DEBUG1_STATEMACHINE__IDLE           0x0
-#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD1       0x1
-#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD3       0x2
-#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD2       0x3
-#define BV_APBH_CHn_DEBUG1_STATEMACHINE__XFER_DECODE    0x4
-#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_WAIT       0x5
-#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD4       0x6
-#define BV_APBH_CHn_DEBUG1_STATEMACHINE__PIO_REQ        0x7
-#define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_FLUSH     0x8
-#define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_WAIT      0x9
-#define BV_APBH_CHn_DEBUG1_STATEMACHINE__WRITE          0xc
-#define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_REQ       0xd
-#define BV_APBH_CHn_DEBUG1_STATEMACHINE__CHECK_CHAIN    0xe
-#define BV_APBH_CHn_DEBUG1_STATEMACHINE__XFER_COMPLETE  0xf
-#define BV_APBH_CHn_DEBUG1_STATEMACHINE__WAIT_END       0x15
-#define BV_APBH_CHn_DEBUG1_STATEMACHINE__WRITE_WAIT     0x1c
-#define BV_APBH_CHn_DEBUG1_STATEMACHINE__CHECK_WAIT     0x1e
-#define BF_APBH_CHn_DEBUG1_STATEMACHINE(v)              (((v) << 0) & 0x1f)
-#define BF_APBH_CHn_DEBUG1_STATEMACHINE_V(v)            ((BV_APBH_CHn_DEBUG1_STATEMACHINE__##v << 0) & 0x1f)
-
-/**
- * Register: HW_APBH_CHn_DEBUG2
- * Address: 0xa0+n*0x70
- * SCT: no
-*/
-#define HW_APBH_CHn_DEBUG2(n)           (*(volatile unsigned long *)(REGS_APBH_BASE + 0xa0+(n)*0x70))
-#define BP_APBH_CHn_DEBUG2_APB_BYTES    16
-#define BM_APBH_CHn_DEBUG2_APB_BYTES    0xffff0000
-#define BF_APBH_CHn_DEBUG2_APB_BYTES(v) (((v) << 16) & 0xffff0000)
-#define BP_APBH_CHn_DEBUG2_AHB_BYTES    0
-#define BM_APBH_CHn_DEBUG2_AHB_BYTES    0xffff
-#define BF_APBH_CHn_DEBUG2_AHB_BYTES(v) (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_APBH_VERSION
- * Address: 0x3f0
- * SCT: no
-*/
-#define HW_APBH_VERSION             (*(volatile unsigned long *)(REGS_APBH_BASE + 0x3f0))
-#define BP_APBH_VERSION_MAJOR       24
-#define BM_APBH_VERSION_MAJOR       0xff000000
-#define BF_APBH_VERSION_MAJOR(v)    (((v) << 24) & 0xff000000)
-#define BP_APBH_VERSION_MINOR       16
-#define BM_APBH_VERSION_MINOR       0xff0000
-#define BF_APBH_VERSION_MINOR(v)    (((v) << 16) & 0xff0000)
-#define BP_APBH_VERSION_STEP        0
-#define BM_APBH_VERSION_STEP        0xffff
-#define BF_APBH_VERSION_STEP(v)     (((v) << 0) & 0xffff)
-
-#endif /* __HEADERGEN__STMP3700__APBH__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-apbx.h b/firmware/target/arm/imx233/regs/stmp3700/regs-apbx.h
deleted file mode 100644
index 32dc6d035b..0000000000
--- a/firmware/target/arm/imx233/regs/stmp3700/regs-apbx.h
+++ /dev/null
@@ -1,294 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3700:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__STMP3700__APBX__H__
-#define __HEADERGEN__STMP3700__APBX__H__
-
-#define REGS_APBX_BASE (0x80024000)
-
-#define REGS_APBX_VERSION "3.2.0"
-
-/**
- * Register: HW_APBX_CTRL0
- * Address: 0
- * SCT: yes
-*/
-#define HW_APBX_CTRL0                           (*(volatile unsigned long *)(REGS_APBX_BASE + 0x0 + 0x0))
-#define HW_APBX_CTRL0_SET                       (*(volatile unsigned long *)(REGS_APBX_BASE + 0x0 + 0x4))
-#define HW_APBX_CTRL0_CLR                       (*(volatile unsigned long *)(REGS_APBX_BASE + 0x0 + 0x8))
-#define HW_APBX_CTRL0_TOG                       (*(volatile unsigned long *)(REGS_APBX_BASE + 0x0 + 0xc))
-#define BP_APBX_CTRL0_SFTRST                    31
-#define BM_APBX_CTRL0_SFTRST                    0x80000000
-#define BF_APBX_CTRL0_SFTRST(v)                 (((v) << 31) & 0x80000000)
-#define BP_APBX_CTRL0_CLKGATE                   30
-#define BM_APBX_CTRL0_CLKGATE                   0x40000000
-#define BF_APBX_CTRL0_CLKGATE(v)                (((v) << 30) & 0x40000000)
-#define BP_APBX_CTRL0_RESET_CHANNEL             16
-#define BM_APBX_CTRL0_RESET_CHANNEL             0xff0000
-#define BV_APBX_CTRL0_RESET_CHANNEL__AUDIOIN    0x1
-#define BV_APBX_CTRL0_RESET_CHANNEL__AUDIOOUT   0x2
-#define BV_APBX_CTRL0_RESET_CHANNEL__SPDIF_TX   0x4
-#define BV_APBX_CTRL0_RESET_CHANNEL__SAIF2      0x4
-#define BV_APBX_CTRL0_RESET_CHANNEL__I2C        0x8
-#define BV_APBX_CTRL0_RESET_CHANNEL__SAIF1      0x10
-#define BV_APBX_CTRL0_RESET_CHANNEL__DRI        0x20
-#define BV_APBX_CTRL0_RESET_CHANNEL__UART_RX    0x40
-#define BV_APBX_CTRL0_RESET_CHANNEL__IRDA_RX    0x40
-#define BV_APBX_CTRL0_RESET_CHANNEL__UART_TX    0x80
-#define BV_APBX_CTRL0_RESET_CHANNEL__IRDA_TX    0x80
-#define BF_APBX_CTRL0_RESET_CHANNEL(v)          (((v) << 16) & 0xff0000)
-#define BF_APBX_CTRL0_RESET_CHANNEL_V(v)        ((BV_APBX_CTRL0_RESET_CHANNEL__##v << 16) & 0xff0000)
-#define BP_APBX_CTRL0_FREEZE_CHANNEL            0
-#define BM_APBX_CTRL0_FREEZE_CHANNEL            0xff
-#define BV_APBX_CTRL0_FREEZE_CHANNEL__AUDIOIN   0x1
-#define BV_APBX_CTRL0_FREEZE_CHANNEL__AUDIOOUT  0x2
-#define BV_APBX_CTRL0_FREEZE_CHANNEL__SPDIF_TX  0x4
-#define BV_APBX_CTRL0_FREEZE_CHANNEL__SAIF2     0x4
-#define BV_APBX_CTRL0_FREEZE_CHANNEL__I2C       0x8
-#define BV_APBX_CTRL0_FREEZE_CHANNEL__SAIF1     0x10
-#define BV_APBX_CTRL0_FREEZE_CHANNEL__DRI       0x20
-#define BV_APBX_CTRL0_FREEZE_CHANNEL__UART_RX   0x40
-#define BV_APBX_CTRL0_FREEZE_CHANNEL__IRDA_RX   0x40
-#define BV_APBX_CTRL0_FREEZE_CHANNEL__UART_TX   0x80
-#define BV_APBX_CTRL0_FREEZE_CHANNEL__IRDA_TX   0x80
-#define BF_APBX_CTRL0_FREEZE_CHANNEL(v)         (((v) << 0) & 0xff)
-#define BF_APBX_CTRL0_FREEZE_CHANNEL_V(v)       ((BV_APBX_CTRL0_FREEZE_CHANNEL__##v << 0) & 0xff)
-
-/**
- * Register: HW_APBX_CTRL1
- * Address: 0x10
- * SCT: yes
-*/
-#define HW_APBX_CTRL1                       (*(volatile unsigned long *)(REGS_APBX_BASE + 0x10 + 0x0))
-#define HW_APBX_CTRL1_SET                   (*(volatile unsigned long *)(REGS_APBX_BASE + 0x10 + 0x4))
-#define HW_APBX_CTRL1_CLR                   (*(volatile unsigned long *)(REGS_APBX_BASE + 0x10 + 0x8))
-#define HW_APBX_CTRL1_TOG                   (*(volatile unsigned long *)(REGS_APBX_BASE + 0x10 + 0xc))
-#define BP_APBX_CTRL1_CH_AHB_ERROR_IRQ      16
-#define BM_APBX_CTRL1_CH_AHB_ERROR_IRQ      0xff0000
-#define BF_APBX_CTRL1_CH_AHB_ERROR_IRQ(v)   (((v) << 16) & 0xff0000)
-#define BP_APBX_CTRL1_CH_CMDCMPLT_IRQ_EN    8
-#define BM_APBX_CTRL1_CH_CMDCMPLT_IRQ_EN    0xff00
-#define BF_APBX_CTRL1_CH_CMDCMPLT_IRQ_EN(v) (((v) << 8) & 0xff00)
-#define BP_APBX_CTRL1_CH_CMDCMPLT_IRQ       0
-#define BM_APBX_CTRL1_CH_CMDCMPLT_IRQ       0xff
-#define BF_APBX_CTRL1_CH_CMDCMPLT_IRQ(v)    (((v) << 0) & 0xff)
-
-/**
- * Register: HW_APBX_DEVSEL
- * Address: 0x20
- * SCT: no
-*/
-#define HW_APBX_DEVSEL                  (*(volatile unsigned long *)(REGS_APBX_BASE + 0x20))
-#define BP_APBX_DEVSEL_CH7              28
-#define BM_APBX_DEVSEL_CH7              0xf0000000
-#define BV_APBX_DEVSEL_CH7__USE_UART    0x0
-#define BV_APBX_DEVSEL_CH7__USE_IRDA    0x1
-#define BF_APBX_DEVSEL_CH7(v)           (((v) << 28) & 0xf0000000)
-#define BF_APBX_DEVSEL_CH7_V(v)         ((BV_APBX_DEVSEL_CH7__##v << 28) & 0xf0000000)
-#define BP_APBX_DEVSEL_CH6              24
-#define BM_APBX_DEVSEL_CH6              0xf000000
-#define BV_APBX_DEVSEL_CH6__USE_UART    0x0
-#define BV_APBX_DEVSEL_CH6__USE_IRDA    0x1
-#define BF_APBX_DEVSEL_CH6(v)           (((v) << 24) & 0xf000000)
-#define BF_APBX_DEVSEL_CH6_V(v)         ((BV_APBX_DEVSEL_CH6__##v << 24) & 0xf000000)
-#define BP_APBX_DEVSEL_CH5              20
-#define BM_APBX_DEVSEL_CH5              0xf00000
-#define BF_APBX_DEVSEL_CH5(v)           (((v) << 20) & 0xf00000)
-#define BP_APBX_DEVSEL_CH4              16
-#define BM_APBX_DEVSEL_CH4              0xf0000
-#define BF_APBX_DEVSEL_CH4(v)           (((v) << 16) & 0xf0000)
-#define BP_APBX_DEVSEL_CH3              12
-#define BM_APBX_DEVSEL_CH3              0xf000
-#define BF_APBX_DEVSEL_CH3(v)           (((v) << 12) & 0xf000)
-#define BP_APBX_DEVSEL_CH2              8
-#define BM_APBX_DEVSEL_CH2              0xf00
-#define BV_APBX_DEVSEL_CH2__USE_SPDIF   0x0
-#define BV_APBX_DEVSEL_CH2__USE_SAIF2   0x1
-#define BF_APBX_DEVSEL_CH2(v)           (((v) << 8) & 0xf00)
-#define BF_APBX_DEVSEL_CH2_V(v)         ((BV_APBX_DEVSEL_CH2__##v << 8) & 0xf00)
-#define BP_APBX_DEVSEL_CH1              4
-#define BM_APBX_DEVSEL_CH1              0xf0
-#define BF_APBX_DEVSEL_CH1(v)           (((v) << 4) & 0xf0)
-#define BP_APBX_DEVSEL_CH0              0
-#define BM_APBX_DEVSEL_CH0              0xf
-#define BF_APBX_DEVSEL_CH0(v)           (((v) << 0) & 0xf)
-
-/**
- * Register: HW_APBX_CHn_CURCMDAR
- * Address: 0x40+n*0x70
- * SCT: no
-*/
-#define HW_APBX_CHn_CURCMDAR(n)             (*(volatile unsigned long *)(REGS_APBX_BASE + 0x40+(n)*0x70))
-#define BP_APBX_CHn_CURCMDAR_CMD_ADDR       0
-#define BM_APBX_CHn_CURCMDAR_CMD_ADDR       0xffffffff
-#define BF_APBX_CHn_CURCMDAR_CMD_ADDR(v)    (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_APBX_CHn_NXTCMDAR
- * Address: 0x50+n*0x70
- * SCT: no
-*/
-#define HW_APBX_CHn_NXTCMDAR(n)             (*(volatile unsigned long *)(REGS_APBX_BASE + 0x50+(n)*0x70))
-#define BP_APBX_CHn_NXTCMDAR_CMD_ADDR       0
-#define BM_APBX_CHn_NXTCMDAR_CMD_ADDR       0xffffffff
-#define BF_APBX_CHn_NXTCMDAR_CMD_ADDR(v)    (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_APBX_CHn_CMD
- * Address: 0x60+n*0x70
- * SCT: no
-*/
-#define HW_APBX_CHn_CMD(n)                      (*(volatile unsigned long *)(REGS_APBX_BASE + 0x60+(n)*0x70))
-#define BP_APBX_CHn_CMD_XFER_COUNT              16
-#define BM_APBX_CHn_CMD_XFER_COUNT              0xffff0000
-#define BF_APBX_CHn_CMD_XFER_COUNT(v)           (((v) << 16) & 0xffff0000)
-#define BP_APBX_CHn_CMD_CMDWORDS                12
-#define BM_APBX_CHn_CMD_CMDWORDS                0xf000
-#define BF_APBX_CHn_CMD_CMDWORDS(v)             (((v) << 12) & 0xf000)
-#define BP_APBX_CHn_CMD_WAIT4ENDCMD             7
-#define BM_APBX_CHn_CMD_WAIT4ENDCMD             0x80
-#define BF_APBX_CHn_CMD_WAIT4ENDCMD(v)          (((v) << 7) & 0x80)
-#define BP_APBX_CHn_CMD_SEMAPHORE               6
-#define BM_APBX_CHn_CMD_SEMAPHORE               0x40
-#define BF_APBX_CHn_CMD_SEMAPHORE(v)            (((v) << 6) & 0x40)
-#define BP_APBX_CHn_CMD_IRQONCMPLT              3
-#define BM_APBX_CHn_CMD_IRQONCMPLT              0x8
-#define BF_APBX_CHn_CMD_IRQONCMPLT(v)           (((v) << 3) & 0x8)
-#define BP_APBX_CHn_CMD_CHAIN                   2
-#define BM_APBX_CHn_CMD_CHAIN                   0x4
-#define BF_APBX_CHn_CMD_CHAIN(v)                (((v) << 2) & 0x4)
-#define BP_APBX_CHn_CMD_COMMAND                 0
-#define BM_APBX_CHn_CMD_COMMAND                 0x3
-#define BV_APBX_CHn_CMD_COMMAND__NO_DMA_XFER    0x0
-#define BV_APBX_CHn_CMD_COMMAND__DMA_WRITE      0x1
-#define BV_APBX_CHn_CMD_COMMAND__DMA_READ       0x2
-#define BF_APBX_CHn_CMD_COMMAND(v)              (((v) << 0) & 0x3)
-#define BF_APBX_CHn_CMD_COMMAND_V(v)            ((BV_APBX_CHn_CMD_COMMAND__##v << 0) & 0x3)
-
-/**
- * Register: HW_APBX_CHn_BAR
- * Address: 0x70+n*0x70
- * SCT: no
-*/
-#define HW_APBX_CHn_BAR(n)          (*(volatile unsigned long *)(REGS_APBX_BASE + 0x70+(n)*0x70))
-#define BP_APBX_CHn_BAR_ADDRESS     0
-#define BM_APBX_CHn_BAR_ADDRESS     0xffffffff
-#define BF_APBX_CHn_BAR_ADDRESS(v)  (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_APBX_CHn_SEMA
- * Address: 0x80+n*0x70
- * SCT: no
-*/
-#define HW_APBX_CHn_SEMA(n)                 (*(volatile unsigned long *)(REGS_APBX_BASE + 0x80+(n)*0x70))
-#define BP_APBX_CHn_SEMA_PHORE              16
-#define BM_APBX_CHn_SEMA_PHORE              0xff0000
-#define BF_APBX_CHn_SEMA_PHORE(v)           (((v) << 16) & 0xff0000)
-#define BP_APBX_CHn_SEMA_INCREMENT_SEMA     0
-#define BM_APBX_CHn_SEMA_INCREMENT_SEMA     0xff
-#define BF_APBX_CHn_SEMA_INCREMENT_SEMA(v)  (((v) << 0) & 0xff)
-
-/**
- * Register: HW_APBX_CHn_DEBUG1
- * Address: 0x90+n*0x70
- * SCT: no
-*/
-#define HW_APBX_CHn_DEBUG1(n)                           (*(volatile unsigned long *)(REGS_APBX_BASE + 0x90+(n)*0x70))
-#define BP_APBX_CHn_DEBUG1_REQ                          31
-#define BM_APBX_CHn_DEBUG1_REQ                          0x80000000
-#define BF_APBX_CHn_DEBUG1_REQ(v)                       (((v) << 31) & 0x80000000)
-#define BP_APBX_CHn_DEBUG1_BURST                        30
-#define BM_APBX_CHn_DEBUG1_BURST                        0x40000000
-#define BF_APBX_CHn_DEBUG1_BURST(v)                     (((v) << 30) & 0x40000000)
-#define BP_APBX_CHn_DEBUG1_KICK                         29
-#define BM_APBX_CHn_DEBUG1_KICK                         0x20000000
-#define BF_APBX_CHn_DEBUG1_KICK(v)                      (((v) << 29) & 0x20000000)
-#define BP_APBX_CHn_DEBUG1_END                          28
-#define BM_APBX_CHn_DEBUG1_END                          0x10000000
-#define BF_APBX_CHn_DEBUG1_END(v)                       (((v) << 28) & 0x10000000)
-#define BP_APBX_CHn_DEBUG1_NEXTCMDADDRVALID             24
-#define BM_APBX_CHn_DEBUG1_NEXTCMDADDRVALID             0x1000000
-#define BF_APBX_CHn_DEBUG1_NEXTCMDADDRVALID(v)          (((v) << 24) & 0x1000000)
-#define BP_APBX_CHn_DEBUG1_RD_FIFO_EMPTY                23
-#define BM_APBX_CHn_DEBUG1_RD_FIFO_EMPTY                0x800000
-#define BF_APBX_CHn_DEBUG1_RD_FIFO_EMPTY(v)             (((v) << 23) & 0x800000)
-#define BP_APBX_CHn_DEBUG1_RD_FIFO_FULL                 22
-#define BM_APBX_CHn_DEBUG1_RD_FIFO_FULL                 0x400000
-#define BF_APBX_CHn_DEBUG1_RD_FIFO_FULL(v)              (((v) << 22) & 0x400000)
-#define BP_APBX_CHn_DEBUG1_WR_FIFO_EMPTY                21
-#define BM_APBX_CHn_DEBUG1_WR_FIFO_EMPTY                0x200000
-#define BF_APBX_CHn_DEBUG1_WR_FIFO_EMPTY(v)             (((v) << 21) & 0x200000)
-#define BP_APBX_CHn_DEBUG1_WR_FIFO_FULL                 20
-#define BM_APBX_CHn_DEBUG1_WR_FIFO_FULL                 0x100000
-#define BF_APBX_CHn_DEBUG1_WR_FIFO_FULL(v)              (((v) << 20) & 0x100000)
-#define BP_APBX_CHn_DEBUG1_STATEMACHINE                 0
-#define BM_APBX_CHn_DEBUG1_STATEMACHINE                 0x1f
-#define BV_APBX_CHn_DEBUG1_STATEMACHINE__IDLE           0x0
-#define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD1       0x1
-#define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD3       0x2
-#define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD2       0x3
-#define BV_APBX_CHn_DEBUG1_STATEMACHINE__XFER_DECODE    0x4
-#define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_WAIT       0x5
-#define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD4       0x6
-#define BV_APBX_CHn_DEBUG1_STATEMACHINE__PIO_REQ        0x7
-#define BV_APBX_CHn_DEBUG1_STATEMACHINE__READ_FLUSH     0x8
-#define BV_APBX_CHn_DEBUG1_STATEMACHINE__READ_WAIT      0x9
-#define BV_APBX_CHn_DEBUG1_STATEMACHINE__WRITE          0xc
-#define BV_APBX_CHn_DEBUG1_STATEMACHINE__READ_REQ       0xd
-#define BV_APBX_CHn_DEBUG1_STATEMACHINE__CHECK_CHAIN    0xe
-#define BV_APBX_CHn_DEBUG1_STATEMACHINE__XFER_COMPLETE  0xf
-#define BV_APBX_CHn_DEBUG1_STATEMACHINE__WAIT_END       0x15
-#define BV_APBX_CHn_DEBUG1_STATEMACHINE__WRITE_WAIT     0x1c
-#define BV_APBX_CHn_DEBUG1_STATEMACHINE__CHECK_WAIT     0x1e
-#define BF_APBX_CHn_DEBUG1_STATEMACHINE(v)              (((v) << 0) & 0x1f)
-#define BF_APBX_CHn_DEBUG1_STATEMACHINE_V(v)            ((BV_APBX_CHn_DEBUG1_STATEMACHINE__##v << 0) & 0x1f)
-
-/**
- * Register: HW_APBX_CHn_DEBUG2
- * Address: 0xa0+n*0x70
- * SCT: no
-*/
-#define HW_APBX_CHn_DEBUG2(n)           (*(volatile unsigned long *)(REGS_APBX_BASE + 0xa0+(n)*0x70))
-#define BP_APBX_CHn_DEBUG2_APB_BYTES    16
-#define BM_APBX_CHn_DEBUG2_APB_BYTES    0xffff0000
-#define BF_APBX_CHn_DEBUG2_APB_BYTES(v) (((v) << 16) & 0xffff0000)
-#define BP_APBX_CHn_DEBUG2_AHB_BYTES    0
-#define BM_APBX_CHn_DEBUG2_AHB_BYTES    0xffff
-#define BF_APBX_CHn_DEBUG2_AHB_BYTES(v) (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_APBX_VERSION
- * Address: 0x3f0
- * SCT: no
-*/
-#define HW_APBX_VERSION             (*(volatile unsigned long *)(REGS_APBX_BASE + 0x3f0))
-#define BP_APBX_VERSION_MAJOR       24
-#define BM_APBX_VERSION_MAJOR       0xff000000
-#define BF_APBX_VERSION_MAJOR(v)    (((v) << 24) & 0xff000000)
-#define BP_APBX_VERSION_MINOR       16
-#define BM_APBX_VERSION_MINOR       0xff0000
-#define BF_APBX_VERSION_MINOR(v)    (((v) << 16) & 0xff0000)
-#define BP_APBX_VERSION_STEP        0
-#define BM_APBX_VERSION_STEP        0xffff
-#define BF_APBX_VERSION_STEP(v)     (((v) << 0) & 0xffff)
-
-#endif /* __HEADERGEN__STMP3700__APBX__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-audioin.h b/firmware/target/arm/imx233/regs/stmp3700/regs-audioin.h
deleted file mode 100644
index 6676e393e9..0000000000
--- a/firmware/target/arm/imx233/regs/stmp3700/regs-audioin.h
+++ /dev/null
@@ -1,284 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3700:3.4.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__STMP3700__AUDIOIN__H__
-#define __HEADERGEN__STMP3700__AUDIOIN__H__
-
-#define REGS_AUDIOIN_BASE (0x8004c000)
-
-#define REGS_AUDIOIN_VERSION "3.4.0"
-
-/**
- * Register: HW_AUDIOIN_CTRL
- * Address: 0
- * SCT: yes
-*/
-#define HW_AUDIOIN_CTRL                         (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x0 + 0x0))
-#define HW_AUDIOIN_CTRL_SET                     (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x0 + 0x4))
-#define HW_AUDIOIN_CTRL_CLR                     (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x0 + 0x8))
-#define HW_AUDIOIN_CTRL_TOG                     (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x0 + 0xc))
-#define BP_AUDIOIN_CTRL_SFTRST                  31
-#define BM_AUDIOIN_CTRL_SFTRST                  0x80000000
-#define BF_AUDIOIN_CTRL_SFTRST(v)               (((v) << 31) & 0x80000000)
-#define BP_AUDIOIN_CTRL_CLKGATE                 30
-#define BM_AUDIOIN_CTRL_CLKGATE                 0x40000000
-#define BF_AUDIOIN_CTRL_CLKGATE(v)              (((v) << 30) & 0x40000000)
-#define BP_AUDIOIN_CTRL_DMAWAIT_COUNT           16
-#define BM_AUDIOIN_CTRL_DMAWAIT_COUNT           0x1f0000
-#define BF_AUDIOIN_CTRL_DMAWAIT_COUNT(v)        (((v) << 16) & 0x1f0000)
-#define BP_AUDIOIN_CTRL_LR_SWAP                 10
-#define BM_AUDIOIN_CTRL_LR_SWAP                 0x400
-#define BF_AUDIOIN_CTRL_LR_SWAP(v)              (((v) << 10) & 0x400)
-#define BP_AUDIOIN_CTRL_EDGE_SYNC               9
-#define BM_AUDIOIN_CTRL_EDGE_SYNC               0x200
-#define BF_AUDIOIN_CTRL_EDGE_SYNC(v)            (((v) << 9) & 0x200)
-#define BP_AUDIOIN_CTRL_INVERT_1BIT             8
-#define BM_AUDIOIN_CTRL_INVERT_1BIT             0x100
-#define BF_AUDIOIN_CTRL_INVERT_1BIT(v)          (((v) << 8) & 0x100)
-#define BP_AUDIOIN_CTRL_OFFSET_ENABLE           7
-#define BM_AUDIOIN_CTRL_OFFSET_ENABLE           0x80
-#define BF_AUDIOIN_CTRL_OFFSET_ENABLE(v)        (((v) << 7) & 0x80)
-#define BP_AUDIOIN_CTRL_HPF_ENABLE              6
-#define BM_AUDIOIN_CTRL_HPF_ENABLE              0x40
-#define BF_AUDIOIN_CTRL_HPF_ENABLE(v)           (((v) << 6) & 0x40)
-#define BP_AUDIOIN_CTRL_WORD_LENGTH             5
-#define BM_AUDIOIN_CTRL_WORD_LENGTH             0x20
-#define BF_AUDIOIN_CTRL_WORD_LENGTH(v)          (((v) << 5) & 0x20)
-#define BP_AUDIOIN_CTRL_LOOPBACK                4
-#define BM_AUDIOIN_CTRL_LOOPBACK                0x10
-#define BF_AUDIOIN_CTRL_LOOPBACK(v)             (((v) << 4) & 0x10)
-#define BP_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ      3
-#define BM_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ      0x8
-#define BF_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ(v)   (((v) << 3) & 0x8)
-#define BP_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ       2
-#define BM_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ       0x4
-#define BF_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ(v)    (((v) << 2) & 0x4)
-#define BP_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN       1
-#define BM_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN       0x2
-#define BF_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN(v)    (((v) << 1) & 0x2)
-#define BP_AUDIOIN_CTRL_RUN                     0
-#define BM_AUDIOIN_CTRL_RUN                     0x1
-#define BF_AUDIOIN_CTRL_RUN(v)                  (((v) << 0) & 0x1)
-
-/**
- * Register: HW_AUDIOIN_STAT
- * Address: 0x10
- * SCT: no
-*/
-#define HW_AUDIOIN_STAT                 (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x10))
-#define BP_AUDIOIN_STAT_ADC_PRESENT     31
-#define BM_AUDIOIN_STAT_ADC_PRESENT     0x80000000
-#define BF_AUDIOIN_STAT_ADC_PRESENT(v)  (((v) << 31) & 0x80000000)
-
-/**
- * Register: HW_AUDIOIN_ADCSRR
- * Address: 0x20
- * SCT: yes
-*/
-#define HW_AUDIOIN_ADCSRR                       (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x20 + 0x0))
-#define HW_AUDIOIN_ADCSRR_SET                   (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x20 + 0x4))
-#define HW_AUDIOIN_ADCSRR_CLR                   (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x20 + 0x8))
-#define HW_AUDIOIN_ADCSRR_TOG                   (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x20 + 0xc))
-#define BP_AUDIOIN_ADCSRR_OSR                   31
-#define BM_AUDIOIN_ADCSRR_OSR                   0x80000000
-#define BV_AUDIOIN_ADCSRR_OSR__OSR6             0x0
-#define BV_AUDIOIN_ADCSRR_OSR__OSR12            0x1
-#define BF_AUDIOIN_ADCSRR_OSR(v)                (((v) << 31) & 0x80000000)
-#define BF_AUDIOIN_ADCSRR_OSR_V(v)              ((BV_AUDIOIN_ADCSRR_OSR__##v << 31) & 0x80000000)
-#define BP_AUDIOIN_ADCSRR_BASEMULT              28
-#define BM_AUDIOIN_ADCSRR_BASEMULT              0x70000000
-#define BV_AUDIOIN_ADCSRR_BASEMULT__SINGLE_RATE 0x1
-#define BV_AUDIOIN_ADCSRR_BASEMULT__DOUBLE_RATE 0x2
-#define BV_AUDIOIN_ADCSRR_BASEMULT__QUAD_RATE   0x4
-#define BF_AUDIOIN_ADCSRR_BASEMULT(v)           (((v) << 28) & 0x70000000)
-#define BF_AUDIOIN_ADCSRR_BASEMULT_V(v)         ((BV_AUDIOIN_ADCSRR_BASEMULT__##v << 28) & 0x70000000)
-#define BP_AUDIOIN_ADCSRR_SRC_HOLD              24
-#define BM_AUDIOIN_ADCSRR_SRC_HOLD              0x7000000
-#define BF_AUDIOIN_ADCSRR_SRC_HOLD(v)           (((v) << 24) & 0x7000000)
-#define BP_AUDIOIN_ADCSRR_SRC_INT               16
-#define BM_AUDIOIN_ADCSRR_SRC_INT               0x1f0000
-#define BF_AUDIOIN_ADCSRR_SRC_INT(v)            (((v) << 16) & 0x1f0000)
-#define BP_AUDIOIN_ADCSRR_SRC_FRAC              0
-#define BM_AUDIOIN_ADCSRR_SRC_FRAC              0x1fff
-#define BF_AUDIOIN_ADCSRR_SRC_FRAC(v)           (((v) << 0) & 0x1fff)
-
-/**
- * Register: HW_AUDIOIN_ADCVOLUME
- * Address: 0x30
- * SCT: yes
-*/
-#define HW_AUDIOIN_ADCVOLUME                        (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x30 + 0x0))
-#define HW_AUDIOIN_ADCVOLUME_SET                    (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x30 + 0x4))
-#define HW_AUDIOIN_ADCVOLUME_CLR                    (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x30 + 0x8))
-#define HW_AUDIOIN_ADCVOLUME_TOG                    (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x30 + 0xc))
-#define BP_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_LEFT     28
-#define BM_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_LEFT     0x10000000
-#define BF_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_LEFT(v)  (((v) << 28) & 0x10000000)
-#define BP_AUDIOIN_ADCVOLUME_EN_ZCD                 25
-#define BM_AUDIOIN_ADCVOLUME_EN_ZCD                 0x2000000
-#define BF_AUDIOIN_ADCVOLUME_EN_ZCD(v)              (((v) << 25) & 0x2000000)
-#define BP_AUDIOIN_ADCVOLUME_VOLUME_LEFT            16
-#define BM_AUDIOIN_ADCVOLUME_VOLUME_LEFT            0xff0000
-#define BF_AUDIOIN_ADCVOLUME_VOLUME_LEFT(v)         (((v) << 16) & 0xff0000)
-#define BP_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_RIGHT    12
-#define BM_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_RIGHT    0x1000
-#define BF_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_RIGHT(v) (((v) << 12) & 0x1000)
-#define BP_AUDIOIN_ADCVOLUME_VOLUME_RIGHT           0
-#define BM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT           0xff
-#define BF_AUDIOIN_ADCVOLUME_VOLUME_RIGHT(v)        (((v) << 0) & 0xff)
-
-/**
- * Register: HW_AUDIOIN_ADCDEBUG
- * Address: 0x40
- * SCT: yes
-*/
-#define HW_AUDIOIN_ADCDEBUG                                     (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x40 + 0x0))
-#define HW_AUDIOIN_ADCDEBUG_SET                                 (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x40 + 0x4))
-#define HW_AUDIOIN_ADCDEBUG_CLR                                 (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x40 + 0x8))
-#define HW_AUDIOIN_ADCDEBUG_TOG                                 (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x40 + 0xc))
-#define BP_AUDIOIN_ADCDEBUG_ENABLE_ADCDMA                       31
-#define BM_AUDIOIN_ADCDEBUG_ENABLE_ADCDMA                       0x80000000
-#define BF_AUDIOIN_ADCDEBUG_ENABLE_ADCDMA(v)                    (((v) << 31) & 0x80000000)
-#define BP_AUDIOIN_ADCDEBUG_ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS    3
-#define BM_AUDIOIN_ADCDEBUG_ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS    0x8
-#define BF_AUDIOIN_ADCDEBUG_ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS(v) (((v) << 3) & 0x8)
-#define BP_AUDIOIN_ADCDEBUG_SET_INTERRUPT3_HAND_SHAKE           2
-#define BM_AUDIOIN_ADCDEBUG_SET_INTERRUPT3_HAND_SHAKE           0x4
-#define BF_AUDIOIN_ADCDEBUG_SET_INTERRUPT3_HAND_SHAKE(v)        (((v) << 2) & 0x4)
-#define BP_AUDIOIN_ADCDEBUG_DMA_PREQ                            1
-#define BM_AUDIOIN_ADCDEBUG_DMA_PREQ                            0x2
-#define BF_AUDIOIN_ADCDEBUG_DMA_PREQ(v)                         (((v) << 1) & 0x2)
-#define BP_AUDIOIN_ADCDEBUG_FIFO_STATUS                         0
-#define BM_AUDIOIN_ADCDEBUG_FIFO_STATUS                         0x1
-#define BF_AUDIOIN_ADCDEBUG_FIFO_STATUS(v)                      (((v) << 0) & 0x1)
-
-/**
- * Register: HW_AUDIOIN_ADCVOL
- * Address: 0x50
- * SCT: yes
-*/
-#define HW_AUDIOIN_ADCVOL                           (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x50 + 0x0))
-#define HW_AUDIOIN_ADCVOL_SET                       (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x50 + 0x4))
-#define HW_AUDIOIN_ADCVOL_CLR                       (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x50 + 0x8))
-#define HW_AUDIOIN_ADCVOL_TOG                       (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x50 + 0xc))
-#define BP_AUDIOIN_ADCVOL_VOLUME_UPDATE_PENDING     28
-#define BM_AUDIOIN_ADCVOL_VOLUME_UPDATE_PENDING     0x10000000
-#define BF_AUDIOIN_ADCVOL_VOLUME_UPDATE_PENDING(v)  (((v) << 28) & 0x10000000)
-#define BP_AUDIOIN_ADCVOL_EN_ADC_ZCD                25
-#define BM_AUDIOIN_ADCVOL_EN_ADC_ZCD                0x2000000
-#define BF_AUDIOIN_ADCVOL_EN_ADC_ZCD(v)             (((v) << 25) & 0x2000000)
-#define BP_AUDIOIN_ADCVOL_MUTE                      24
-#define BM_AUDIOIN_ADCVOL_MUTE                      0x1000000
-#define BF_AUDIOIN_ADCVOL_MUTE(v)                   (((v) << 24) & 0x1000000)
-#define BP_AUDIOIN_ADCVOL_SELECT_LEFT               12
-#define BM_AUDIOIN_ADCVOL_SELECT_LEFT               0x3000
-#define BF_AUDIOIN_ADCVOL_SELECT_LEFT(v)            (((v) << 12) & 0x3000)
-#define BP_AUDIOIN_ADCVOL_GAIN_LEFT                 8
-#define BM_AUDIOIN_ADCVOL_GAIN_LEFT                 0xf00
-#define BF_AUDIOIN_ADCVOL_GAIN_LEFT(v)              (((v) << 8) & 0xf00)
-#define BP_AUDIOIN_ADCVOL_SELECT_RIGHT              4
-#define BM_AUDIOIN_ADCVOL_SELECT_RIGHT              0x30
-#define BF_AUDIOIN_ADCVOL_SELECT_RIGHT(v)           (((v) << 4) & 0x30)
-#define BP_AUDIOIN_ADCVOL_GAIN_RIGHT                0
-#define BM_AUDIOIN_ADCVOL_GAIN_RIGHT                0xf
-#define BF_AUDIOIN_ADCVOL_GAIN_RIGHT(v)             (((v) << 0) & 0xf)
-
-/**
- * Register: HW_AUDIOIN_MICLINE
- * Address: 0x60
- * SCT: yes
-*/
-#define HW_AUDIOIN_MICLINE                      (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x60 + 0x0))
-#define HW_AUDIOIN_MICLINE_SET                  (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x60 + 0x4))
-#define HW_AUDIOIN_MICLINE_CLR                  (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x60 + 0x8))
-#define HW_AUDIOIN_MICLINE_TOG                  (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x60 + 0xc))
-#define BP_AUDIOIN_MICLINE_DIVIDE_LINE1         29
-#define BM_AUDIOIN_MICLINE_DIVIDE_LINE1         0x20000000
-#define BF_AUDIOIN_MICLINE_DIVIDE_LINE1(v)      (((v) << 29) & 0x20000000)
-#define BP_AUDIOIN_MICLINE_DIVIDE_LINE2         28
-#define BM_AUDIOIN_MICLINE_DIVIDE_LINE2         0x10000000
-#define BF_AUDIOIN_MICLINE_DIVIDE_LINE2(v)      (((v) << 28) & 0x10000000)
-#define BP_AUDIOIN_MICLINE_MIC_SELECT           24
-#define BM_AUDIOIN_MICLINE_MIC_SELECT           0x1000000
-#define BF_AUDIOIN_MICLINE_MIC_SELECT(v)        (((v) << 24) & 0x1000000)
-#define BP_AUDIOIN_MICLINE_MIC_RESISTOR         20
-#define BM_AUDIOIN_MICLINE_MIC_RESISTOR         0x300000
-#define BV_AUDIOIN_MICLINE_MIC_RESISTOR__Off    0x0
-#define BV_AUDIOIN_MICLINE_MIC_RESISTOR__2KOhm  0x1
-#define BV_AUDIOIN_MICLINE_MIC_RESISTOR__4KOhm  0x2
-#define BV_AUDIOIN_MICLINE_MIC_RESISTOR__8KOhm  0x3
-#define BF_AUDIOIN_MICLINE_MIC_RESISTOR(v)      (((v) << 20) & 0x300000)
-#define BF_AUDIOIN_MICLINE_MIC_RESISTOR_V(v)    ((BV_AUDIOIN_MICLINE_MIC_RESISTOR__##v << 20) & 0x300000)
-#define BP_AUDIOIN_MICLINE_MIC_BIAS             16
-#define BM_AUDIOIN_MICLINE_MIC_BIAS             0x70000
-#define BF_AUDIOIN_MICLINE_MIC_BIAS(v)          (((v) << 16) & 0x70000)
-#define BP_AUDIOIN_MICLINE_MIC_CHOPCLK          4
-#define BM_AUDIOIN_MICLINE_MIC_CHOPCLK          0x30
-#define BF_AUDIOIN_MICLINE_MIC_CHOPCLK(v)       (((v) << 4) & 0x30)
-#define BP_AUDIOIN_MICLINE_MIC_GAIN             0
-#define BM_AUDIOIN_MICLINE_MIC_GAIN             0x3
-#define BV_AUDIOIN_MICLINE_MIC_GAIN__0dB        0x0
-#define BV_AUDIOIN_MICLINE_MIC_GAIN__20dB       0x1
-#define BV_AUDIOIN_MICLINE_MIC_GAIN__30dB       0x2
-#define BV_AUDIOIN_MICLINE_MIC_GAIN__40dB       0x3
-#define BF_AUDIOIN_MICLINE_MIC_GAIN(v)          (((v) << 0) & 0x3)
-#define BF_AUDIOIN_MICLINE_MIC_GAIN_V(v)        ((BV_AUDIOIN_MICLINE_MIC_GAIN__##v << 0) & 0x3)
-
-/**
- * Register: HW_AUDIOIN_ANACLKCTRL
- * Address: 0x70
- * SCT: yes
-*/
-#define HW_AUDIOIN_ANACLKCTRL                   (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x70 + 0x0))
-#define HW_AUDIOIN_ANACLKCTRL_SET               (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x70 + 0x4))
-#define HW_AUDIOIN_ANACLKCTRL_CLR               (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x70 + 0x8))
-#define HW_AUDIOIN_ANACLKCTRL_TOG               (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x70 + 0xc))
-#define BP_AUDIOIN_ANACLKCTRL_CLKGATE           31
-#define BM_AUDIOIN_ANACLKCTRL_CLKGATE           0x80000000
-#define BF_AUDIOIN_ANACLKCTRL_CLKGATE(v)        (((v) << 31) & 0x80000000)
-#define BP_AUDIOIN_ANACLKCTRL_DITHER_OFF        6
-#define BM_AUDIOIN_ANACLKCTRL_DITHER_OFF        0x40
-#define BF_AUDIOIN_ANACLKCTRL_DITHER_OFF(v)     (((v) << 6) & 0x40)
-#define BP_AUDIOIN_ANACLKCTRL_SLOW_DITHER       5
-#define BM_AUDIOIN_ANACLKCTRL_SLOW_DITHER       0x20
-#define BF_AUDIOIN_ANACLKCTRL_SLOW_DITHER(v)    (((v) << 5) & 0x20)
-#define BP_AUDIOIN_ANACLKCTRL_INVERT_ADCCLK     4
-#define BM_AUDIOIN_ANACLKCTRL_INVERT_ADCCLK     0x10
-#define BF_AUDIOIN_ANACLKCTRL_INVERT_ADCCLK(v)  (((v) << 4) & 0x10)
-#define BP_AUDIOIN_ANACLKCTRL_ADCDIV            0
-#define BM_AUDIOIN_ANACLKCTRL_ADCDIV            0x7
-#define BF_AUDIOIN_ANACLKCTRL_ADCDIV(v)         (((v) << 0) & 0x7)
-
-/**
- * Register: HW_AUDIOIN_DATA
- * Address: 0x80
- * SCT: no
-*/
-#define HW_AUDIOIN_DATA         (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x80))
-#define BP_AUDIOIN_DATA_HIGH    16
-#define BM_AUDIOIN_DATA_HIGH    0xffff0000
-#define BF_AUDIOIN_DATA_HIGH(v) (((v) << 16) & 0xffff0000)
-#define BP_AUDIOIN_DATA_LOW     0
-#define BM_AUDIOIN_DATA_LOW     0xffff
-#define BF_AUDIOIN_DATA_LOW(v)  (((v) << 0) & 0xffff)
-
-#endif /* __HEADERGEN__STMP3700__AUDIOIN__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-audioout.h b/firmware/target/arm/imx233/regs/stmp3700/regs-audioout.h
deleted file mode 100644
index 854c207c72..0000000000
--- a/firmware/target/arm/imx233/regs/stmp3700/regs-audioout.h
+++ /dev/null
@@ -1,511 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3700:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__STMP3700__AUDIOOUT__H__
-#define __HEADERGEN__STMP3700__AUDIOOUT__H__
-
-#define REGS_AUDIOOUT_BASE (0x80048000)
-
-#define REGS_AUDIOOUT_VERSION "3.2.0"
-
-/**
- * Register: HW_AUDIOOUT_CTRL
- * Address: 0
- * SCT: yes
-*/
-#define HW_AUDIOOUT_CTRL                        (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x0 + 0x0))
-#define HW_AUDIOOUT_CTRL_SET                    (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x0 + 0x4))
-#define HW_AUDIOOUT_CTRL_CLR                    (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x0 + 0x8))
-#define HW_AUDIOOUT_CTRL_TOG                    (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x0 + 0xc))
-#define BP_AUDIOOUT_CTRL_SFTRST                 31
-#define BM_AUDIOOUT_CTRL_SFTRST                 0x80000000
-#define BF_AUDIOOUT_CTRL_SFTRST(v)              (((v) << 31) & 0x80000000)
-#define BP_AUDIOOUT_CTRL_CLKGATE                30
-#define BM_AUDIOOUT_CTRL_CLKGATE                0x40000000
-#define BF_AUDIOOUT_CTRL_CLKGATE(v)             (((v) << 30) & 0x40000000)
-#define BP_AUDIOOUT_CTRL_DMAWAIT_COUNT          16
-#define BM_AUDIOOUT_CTRL_DMAWAIT_COUNT          0x1f0000
-#define BF_AUDIOOUT_CTRL_DMAWAIT_COUNT(v)       (((v) << 16) & 0x1f0000)
-#define BP_AUDIOOUT_CTRL_LR_SWAP                14
-#define BM_AUDIOOUT_CTRL_LR_SWAP                0x4000
-#define BF_AUDIOOUT_CTRL_LR_SWAP(v)             (((v) << 14) & 0x4000)
-#define BP_AUDIOOUT_CTRL_EDGE_SYNC              13
-#define BM_AUDIOOUT_CTRL_EDGE_SYNC              0x2000
-#define BF_AUDIOOUT_CTRL_EDGE_SYNC(v)           (((v) << 13) & 0x2000)
-#define BP_AUDIOOUT_CTRL_INVERT_1BIT            12
-#define BM_AUDIOOUT_CTRL_INVERT_1BIT            0x1000
-#define BF_AUDIOOUT_CTRL_INVERT_1BIT(v)         (((v) << 12) & 0x1000)
-#define BP_AUDIOOUT_CTRL_SS3D_EFFECT            8
-#define BM_AUDIOOUT_CTRL_SS3D_EFFECT            0x300
-#define BF_AUDIOOUT_CTRL_SS3D_EFFECT(v)         (((v) << 8) & 0x300)
-#define BP_AUDIOOUT_CTRL_WORD_LENGTH            6
-#define BM_AUDIOOUT_CTRL_WORD_LENGTH            0x40
-#define BF_AUDIOOUT_CTRL_WORD_LENGTH(v)         (((v) << 6) & 0x40)
-#define BP_AUDIOOUT_CTRL_DAC_ZERO_ENABLE        5
-#define BM_AUDIOOUT_CTRL_DAC_ZERO_ENABLE        0x20
-#define BF_AUDIOOUT_CTRL_DAC_ZERO_ENABLE(v)     (((v) << 5) & 0x20)
-#define BP_AUDIOOUT_CTRL_LOOPBACK               4
-#define BM_AUDIOOUT_CTRL_LOOPBACK               0x10
-#define BF_AUDIOOUT_CTRL_LOOPBACK(v)            (((v) << 4) & 0x10)
-#define BP_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ     3
-#define BM_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ     0x8
-#define BF_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ(v)  (((v) << 3) & 0x8)
-#define BP_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ      2
-#define BM_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ      0x4
-#define BF_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ(v)   (((v) << 2) & 0x4)
-#define BP_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN      1
-#define BM_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN      0x2
-#define BF_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN(v)   (((v) << 1) & 0x2)
-#define BP_AUDIOOUT_CTRL_RUN                    0
-#define BM_AUDIOOUT_CTRL_RUN                    0x1
-#define BF_AUDIOOUT_CTRL_RUN(v)                 (((v) << 0) & 0x1)
-
-/**
- * Register: HW_AUDIOOUT_STAT
- * Address: 0x10
- * SCT: no
-*/
-#define HW_AUDIOOUT_STAT                (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x10))
-#define BP_AUDIOOUT_STAT_DAC_PRESENT    31
-#define BM_AUDIOOUT_STAT_DAC_PRESENT    0x80000000
-#define BF_AUDIOOUT_STAT_DAC_PRESENT(v) (((v) << 31) & 0x80000000)
-
-/**
- * Register: HW_AUDIOOUT_DACSRR
- * Address: 0x20
- * SCT: yes
-*/
-#define HW_AUDIOOUT_DACSRR                          (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x20 + 0x0))
-#define HW_AUDIOOUT_DACSRR_SET                      (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x20 + 0x4))
-#define HW_AUDIOOUT_DACSRR_CLR                      (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x20 + 0x8))
-#define HW_AUDIOOUT_DACSRR_TOG                      (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x20 + 0xc))
-#define BP_AUDIOOUT_DACSRR_OSR                      31
-#define BM_AUDIOOUT_DACSRR_OSR                      0x80000000
-#define BV_AUDIOOUT_DACSRR_OSR__OSR6                0x0
-#define BV_AUDIOOUT_DACSRR_OSR__OSR12               0x1
-#define BF_AUDIOOUT_DACSRR_OSR(v)                   (((v) << 31) & 0x80000000)
-#define BF_AUDIOOUT_DACSRR_OSR_V(v)                 ((BV_AUDIOOUT_DACSRR_OSR__##v << 31) & 0x80000000)
-#define BP_AUDIOOUT_DACSRR_BASEMULT                 28
-#define BM_AUDIOOUT_DACSRR_BASEMULT                 0x70000000
-#define BV_AUDIOOUT_DACSRR_BASEMULT__SINGLE_RATE    0x1
-#define BV_AUDIOOUT_DACSRR_BASEMULT__DOUBLE_RATE    0x2
-#define BV_AUDIOOUT_DACSRR_BASEMULT__QUAD_RATE      0x4
-#define BF_AUDIOOUT_DACSRR_BASEMULT(v)              (((v) << 28) & 0x70000000)
-#define BF_AUDIOOUT_DACSRR_BASEMULT_V(v)            ((BV_AUDIOOUT_DACSRR_BASEMULT__##v << 28) & 0x70000000)
-#define BP_AUDIOOUT_DACSRR_SRC_HOLD                 24
-#define BM_AUDIOOUT_DACSRR_SRC_HOLD                 0x7000000
-#define BF_AUDIOOUT_DACSRR_SRC_HOLD(v)              (((v) << 24) & 0x7000000)
-#define BP_AUDIOOUT_DACSRR_SRC_INT                  16
-#define BM_AUDIOOUT_DACSRR_SRC_INT                  0x1f0000
-#define BF_AUDIOOUT_DACSRR_SRC_INT(v)               (((v) << 16) & 0x1f0000)
-#define BP_AUDIOOUT_DACSRR_SRC_FRAC                 0
-#define BM_AUDIOOUT_DACSRR_SRC_FRAC                 0x1fff
-#define BF_AUDIOOUT_DACSRR_SRC_FRAC(v)              (((v) << 0) & 0x1fff)
-
-/**
- * Register: HW_AUDIOOUT_DACVOLUME
- * Address: 0x30
- * SCT: yes
-*/
-#define HW_AUDIOOUT_DACVOLUME                           (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x30 + 0x0))
-#define HW_AUDIOOUT_DACVOLUME_SET                       (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x30 + 0x4))
-#define HW_AUDIOOUT_DACVOLUME_CLR                       (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x30 + 0x8))
-#define HW_AUDIOOUT_DACVOLUME_TOG                       (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x30 + 0xc))
-#define BP_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT        28
-#define BM_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT        0x10000000
-#define BF_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT(v)     (((v) << 28) & 0x10000000)
-#define BP_AUDIOOUT_DACVOLUME_EN_ZCD                    25
-#define BM_AUDIOOUT_DACVOLUME_EN_ZCD                    0x2000000
-#define BF_AUDIOOUT_DACVOLUME_EN_ZCD(v)                 (((v) << 25) & 0x2000000)
-#define BP_AUDIOOUT_DACVOLUME_MUTE_LEFT                 24
-#define BM_AUDIOOUT_DACVOLUME_MUTE_LEFT                 0x1000000
-#define BF_AUDIOOUT_DACVOLUME_MUTE_LEFT(v)              (((v) << 24) & 0x1000000)
-#define BP_AUDIOOUT_DACVOLUME_VOLUME_LEFT               16
-#define BM_AUDIOOUT_DACVOLUME_VOLUME_LEFT               0xff0000
-#define BF_AUDIOOUT_DACVOLUME_VOLUME_LEFT(v)            (((v) << 16) & 0xff0000)
-#define BP_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT       12
-#define BM_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT       0x1000
-#define BF_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT(v)    (((v) << 12) & 0x1000)
-#define BP_AUDIOOUT_DACVOLUME_MUTE_RIGHT                8
-#define BM_AUDIOOUT_DACVOLUME_MUTE_RIGHT                0x100
-#define BF_AUDIOOUT_DACVOLUME_MUTE_RIGHT(v)             (((v) << 8) & 0x100)
-#define BP_AUDIOOUT_DACVOLUME_VOLUME_RIGHT              0
-#define BM_AUDIOOUT_DACVOLUME_VOLUME_RIGHT              0xff
-#define BF_AUDIOOUT_DACVOLUME_VOLUME_RIGHT(v)           (((v) << 0) & 0xff)
-
-/**
- * Register: HW_AUDIOOUT_DACDEBUG
- * Address: 0x40
- * SCT: yes
-*/
-#define HW_AUDIOOUT_DACDEBUG                                (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x40 + 0x0))
-#define HW_AUDIOOUT_DACDEBUG_SET                            (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x40 + 0x4))
-#define HW_AUDIOOUT_DACDEBUG_CLR                            (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x40 + 0x8))
-#define HW_AUDIOOUT_DACDEBUG_TOG                            (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x40 + 0xc))
-#define BP_AUDIOOUT_DACDEBUG_ENABLE_DACDMA                  31
-#define BM_AUDIOOUT_DACDEBUG_ENABLE_DACDMA                  0x80000000
-#define BF_AUDIOOUT_DACDEBUG_ENABLE_DACDMA(v)               (((v) << 31) & 0x80000000)
-#define BP_AUDIOOUT_DACDEBUG_RAM_SS                         8
-#define BM_AUDIOOUT_DACDEBUG_RAM_SS                         0xf00
-#define BF_AUDIOOUT_DACDEBUG_RAM_SS(v)                      (((v) << 8) & 0xf00)
-#define BP_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS       5
-#define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS       0x20
-#define BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS(v)    (((v) << 5) & 0x20)
-#define BP_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS       4
-#define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS       0x10
-#define BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS(v)    (((v) << 4) & 0x10)
-#define BP_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE      3
-#define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE      0x8
-#define BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE(v)   (((v) << 3) & 0x8)
-#define BP_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE      2
-#define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE      0x4
-#define BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE(v)   (((v) << 2) & 0x4)
-#define BP_AUDIOOUT_DACDEBUG_DMA_PREQ                       1
-#define BM_AUDIOOUT_DACDEBUG_DMA_PREQ                       0x2
-#define BF_AUDIOOUT_DACDEBUG_DMA_PREQ(v)                    (((v) << 1) & 0x2)
-#define BP_AUDIOOUT_DACDEBUG_FIFO_STATUS                    0
-#define BM_AUDIOOUT_DACDEBUG_FIFO_STATUS                    0x1
-#define BF_AUDIOOUT_DACDEBUG_FIFO_STATUS(v)                 (((v) << 0) & 0x1)
-
-/**
- * Register: HW_AUDIOOUT_HPVOL
- * Address: 0x50
- * SCT: yes
-*/
-#define HW_AUDIOOUT_HPVOL                           (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x50 + 0x0))
-#define HW_AUDIOOUT_HPVOL_SET                       (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x50 + 0x4))
-#define HW_AUDIOOUT_HPVOL_CLR                       (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x50 + 0x8))
-#define HW_AUDIOOUT_HPVOL_TOG                       (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x50 + 0xc))
-#define BP_AUDIOOUT_HPVOL_VOLUME_UPDATE_PENDING     28
-#define BM_AUDIOOUT_HPVOL_VOLUME_UPDATE_PENDING     0x10000000
-#define BF_AUDIOOUT_HPVOL_VOLUME_UPDATE_PENDING(v)  (((v) << 28) & 0x10000000)
-#define BP_AUDIOOUT_HPVOL_EN_MSTR_ZCD               25
-#define BM_AUDIOOUT_HPVOL_EN_MSTR_ZCD               0x2000000
-#define BF_AUDIOOUT_HPVOL_EN_MSTR_ZCD(v)            (((v) << 25) & 0x2000000)
-#define BP_AUDIOOUT_HPVOL_MUTE                      24
-#define BM_AUDIOOUT_HPVOL_MUTE                      0x1000000
-#define BF_AUDIOOUT_HPVOL_MUTE(v)                   (((v) << 24) & 0x1000000)
-#define BP_AUDIOOUT_HPVOL_SELECT                    16
-#define BM_AUDIOOUT_HPVOL_SELECT                    0x10000
-#define BF_AUDIOOUT_HPVOL_SELECT(v)                 (((v) << 16) & 0x10000)
-#define BP_AUDIOOUT_HPVOL_VOL_LEFT                  8
-#define BM_AUDIOOUT_HPVOL_VOL_LEFT                  0x7f00
-#define BF_AUDIOOUT_HPVOL_VOL_LEFT(v)               (((v) << 8) & 0x7f00)
-#define BP_AUDIOOUT_HPVOL_VOL_RIGHT                 0
-#define BM_AUDIOOUT_HPVOL_VOL_RIGHT                 0x7f
-#define BF_AUDIOOUT_HPVOL_VOL_RIGHT(v)              (((v) << 0) & 0x7f)
-
-/**
- * Register: HW_AUDIOOUT_RESERVED
- * Address: 0x60
- * SCT: no
-*/
-#define HW_AUDIOOUT_RESERVED    (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x60))
-
-/**
- * Register: HW_AUDIOOUT_PWRDN
- * Address: 0x70
- * SCT: yes
-*/
-#define HW_AUDIOOUT_PWRDN               (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x70 + 0x0))
-#define HW_AUDIOOUT_PWRDN_SET           (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x70 + 0x4))
-#define HW_AUDIOOUT_PWRDN_CLR           (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x70 + 0x8))
-#define HW_AUDIOOUT_PWRDN_TOG           (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x70 + 0xc))
-#define BP_AUDIOOUT_PWRDN_LINEOUT       24
-#define BM_AUDIOOUT_PWRDN_LINEOUT       0x1000000
-#define BF_AUDIOOUT_PWRDN_LINEOUT(v)    (((v) << 24) & 0x1000000)
-#define BP_AUDIOOUT_PWRDN_SELFBIAS      20
-#define BM_AUDIOOUT_PWRDN_SELFBIAS      0x100000
-#define BF_AUDIOOUT_PWRDN_SELFBIAS(v)   (((v) << 20) & 0x100000)
-#define BP_AUDIOOUT_PWRDN_RIGHT_ADC     16
-#define BM_AUDIOOUT_PWRDN_RIGHT_ADC     0x10000
-#define BF_AUDIOOUT_PWRDN_RIGHT_ADC(v)  (((v) << 16) & 0x10000)
-#define BP_AUDIOOUT_PWRDN_DAC           12
-#define BM_AUDIOOUT_PWRDN_DAC           0x1000
-#define BF_AUDIOOUT_PWRDN_DAC(v)        (((v) << 12) & 0x1000)
-#define BP_AUDIOOUT_PWRDN_ADC           8
-#define BM_AUDIOOUT_PWRDN_ADC           0x100
-#define BF_AUDIOOUT_PWRDN_ADC(v)        (((v) << 8) & 0x100)
-#define BP_AUDIOOUT_PWRDN_CAPLESS       4
-#define BM_AUDIOOUT_PWRDN_CAPLESS       0x10
-#define BF_AUDIOOUT_PWRDN_CAPLESS(v)    (((v) << 4) & 0x10)
-#define BP_AUDIOOUT_PWRDN_HEADPHONE     0
-#define BM_AUDIOOUT_PWRDN_HEADPHONE     0x1
-#define BF_AUDIOOUT_PWRDN_HEADPHONE(v)  (((v) << 0) & 0x1)
-
-/**
- * Register: HW_AUDIOOUT_REFCTRL
- * Address: 0x80
- * SCT: yes
-*/
-#define HW_AUDIOOUT_REFCTRL                     (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x80 + 0x0))
-#define HW_AUDIOOUT_REFCTRL_SET                 (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x80 + 0x4))
-#define HW_AUDIOOUT_REFCTRL_CLR                 (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x80 + 0x8))
-#define HW_AUDIOOUT_REFCTRL_TOG                 (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x80 + 0xc))
-#define BP_AUDIOOUT_REFCTRL_FASTSETTLING        26
-#define BM_AUDIOOUT_REFCTRL_FASTSETTLING        0x4000000
-#define BF_AUDIOOUT_REFCTRL_FASTSETTLING(v)     (((v) << 26) & 0x4000000)
-#define BP_AUDIOOUT_REFCTRL_RAISE_REF           25
-#define BM_AUDIOOUT_REFCTRL_RAISE_REF           0x2000000
-#define BF_AUDIOOUT_REFCTRL_RAISE_REF(v)        (((v) << 25) & 0x2000000)
-#define BP_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS       24
-#define BM_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS       0x1000000
-#define BF_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS(v)    (((v) << 24) & 0x1000000)
-#define BP_AUDIOOUT_REFCTRL_VBG_ADJ             20
-#define BM_AUDIOOUT_REFCTRL_VBG_ADJ             0x700000
-#define BF_AUDIOOUT_REFCTRL_VBG_ADJ(v)          (((v) << 20) & 0x700000)
-#define BP_AUDIOOUT_REFCTRL_LOW_PWR             19
-#define BM_AUDIOOUT_REFCTRL_LOW_PWR             0x80000
-#define BF_AUDIOOUT_REFCTRL_LOW_PWR(v)          (((v) << 19) & 0x80000)
-#define BP_AUDIOOUT_REFCTRL_LW_REF              18
-#define BM_AUDIOOUT_REFCTRL_LW_REF              0x40000
-#define BF_AUDIOOUT_REFCTRL_LW_REF(v)           (((v) << 18) & 0x40000)
-#define BP_AUDIOOUT_REFCTRL_BIAS_CTRL           16
-#define BM_AUDIOOUT_REFCTRL_BIAS_CTRL           0x30000
-#define BF_AUDIOOUT_REFCTRL_BIAS_CTRL(v)        (((v) << 16) & 0x30000)
-#define BP_AUDIOOUT_REFCTRL_VDDXTAL_TO_VDDD     14
-#define BM_AUDIOOUT_REFCTRL_VDDXTAL_TO_VDDD     0x4000
-#define BF_AUDIOOUT_REFCTRL_VDDXTAL_TO_VDDD(v)  (((v) << 14) & 0x4000)
-#define BP_AUDIOOUT_REFCTRL_ADJ_ADC             13
-#define BM_AUDIOOUT_REFCTRL_ADJ_ADC             0x2000
-#define BF_AUDIOOUT_REFCTRL_ADJ_ADC(v)          (((v) << 13) & 0x2000)
-#define BP_AUDIOOUT_REFCTRL_ADJ_VAG             12
-#define BM_AUDIOOUT_REFCTRL_ADJ_VAG             0x1000
-#define BF_AUDIOOUT_REFCTRL_ADJ_VAG(v)          (((v) << 12) & 0x1000)
-#define BP_AUDIOOUT_REFCTRL_ADC_REFVAL          8
-#define BM_AUDIOOUT_REFCTRL_ADC_REFVAL          0xf00
-#define BF_AUDIOOUT_REFCTRL_ADC_REFVAL(v)       (((v) << 8) & 0xf00)
-#define BP_AUDIOOUT_REFCTRL_VAG_VAL             4
-#define BM_AUDIOOUT_REFCTRL_VAG_VAL             0xf0
-#define BF_AUDIOOUT_REFCTRL_VAG_VAL(v)          (((v) << 4) & 0xf0)
-#define BP_AUDIOOUT_REFCTRL_DAC_ADJ             0
-#define BM_AUDIOOUT_REFCTRL_DAC_ADJ             0x7
-#define BF_AUDIOOUT_REFCTRL_DAC_ADJ(v)          (((v) << 0) & 0x7)
-
-/**
- * Register: HW_AUDIOOUT_ANACTRL
- * Address: 0x90
- * SCT: yes
-*/
-#define HW_AUDIOOUT_ANACTRL                     (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x90 + 0x0))
-#define HW_AUDIOOUT_ANACTRL_SET                 (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x90 + 0x4))
-#define HW_AUDIOOUT_ANACTRL_CLR                 (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x90 + 0x8))
-#define HW_AUDIOOUT_ANACTRL_TOG                 (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x90 + 0xc))
-#define BP_AUDIOOUT_ANACTRL_SHORT_CM_STS        28
-#define BM_AUDIOOUT_ANACTRL_SHORT_CM_STS        0x10000000
-#define BF_AUDIOOUT_ANACTRL_SHORT_CM_STS(v)     (((v) << 28) & 0x10000000)
-#define BP_AUDIOOUT_ANACTRL_SHORT_LR_STS        24
-#define BM_AUDIOOUT_ANACTRL_SHORT_LR_STS        0x1000000
-#define BF_AUDIOOUT_ANACTRL_SHORT_LR_STS(v)     (((v) << 24) & 0x1000000)
-#define BP_AUDIOOUT_ANACTRL_SHORTMODE_CM        20
-#define BM_AUDIOOUT_ANACTRL_SHORTMODE_CM        0x300000
-#define BF_AUDIOOUT_ANACTRL_SHORTMODE_CM(v)     (((v) << 20) & 0x300000)
-#define BP_AUDIOOUT_ANACTRL_SHORTMODE_LR        17
-#define BM_AUDIOOUT_ANACTRL_SHORTMODE_LR        0x60000
-#define BF_AUDIOOUT_ANACTRL_SHORTMODE_LR(v)     (((v) << 17) & 0x60000)
-#define BP_AUDIOOUT_ANACTRL_SHORT_LVLADJL       12
-#define BM_AUDIOOUT_ANACTRL_SHORT_LVLADJL       0x7000
-#define BF_AUDIOOUT_ANACTRL_SHORT_LVLADJL(v)    (((v) << 12) & 0x7000)
-#define BP_AUDIOOUT_ANACTRL_SHORT_LVLADJR       8
-#define BM_AUDIOOUT_ANACTRL_SHORT_LVLADJR       0x700
-#define BF_AUDIOOUT_ANACTRL_SHORT_LVLADJR(v)    (((v) << 8) & 0x700)
-#define BP_AUDIOOUT_ANACTRL_HP_HOLD_GND         5
-#define BM_AUDIOOUT_ANACTRL_HP_HOLD_GND         0x20
-#define BF_AUDIOOUT_ANACTRL_HP_HOLD_GND(v)      (((v) << 5) & 0x20)
-#define BP_AUDIOOUT_ANACTRL_HP_CLASSAB          4
-#define BM_AUDIOOUT_ANACTRL_HP_CLASSAB          0x10
-#define BF_AUDIOOUT_ANACTRL_HP_CLASSAB(v)       (((v) << 4) & 0x10)
-
-/**
- * Register: HW_AUDIOOUT_TEST
- * Address: 0xa0
- * SCT: yes
-*/
-#define HW_AUDIOOUT_TEST                    (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xa0 + 0x0))
-#define HW_AUDIOOUT_TEST_SET                (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xa0 + 0x4))
-#define HW_AUDIOOUT_TEST_CLR                (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xa0 + 0x8))
-#define HW_AUDIOOUT_TEST_TOG                (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xa0 + 0xc))
-#define BP_AUDIOOUT_TEST_HP_ANTIPOP         28
-#define BM_AUDIOOUT_TEST_HP_ANTIPOP         0x70000000
-#define BF_AUDIOOUT_TEST_HP_ANTIPOP(v)      (((v) << 28) & 0x70000000)
-#define BP_AUDIOOUT_TEST_TM_ADCIN_TOHP      26
-#define BM_AUDIOOUT_TEST_TM_ADCIN_TOHP      0x4000000
-#define BF_AUDIOOUT_TEST_TM_ADCIN_TOHP(v)   (((v) << 26) & 0x4000000)
-#define BP_AUDIOOUT_TEST_TM_LINEOUT         25
-#define BM_AUDIOOUT_TEST_TM_LINEOUT         0x2000000
-#define BF_AUDIOOUT_TEST_TM_LINEOUT(v)      (((v) << 25) & 0x2000000)
-#define BP_AUDIOOUT_TEST_TM_HPCOMMON        24
-#define BM_AUDIOOUT_TEST_TM_HPCOMMON        0x1000000
-#define BF_AUDIOOUT_TEST_TM_HPCOMMON(v)     (((v) << 24) & 0x1000000)
-#define BP_AUDIOOUT_TEST_HP_I1_ADJ          22
-#define BM_AUDIOOUT_TEST_HP_I1_ADJ          0xc00000
-#define BF_AUDIOOUT_TEST_HP_I1_ADJ(v)       (((v) << 22) & 0xc00000)
-#define BP_AUDIOOUT_TEST_HP_IALL_ADJ        20
-#define BM_AUDIOOUT_TEST_HP_IALL_ADJ        0x300000
-#define BF_AUDIOOUT_TEST_HP_IALL_ADJ(v)     (((v) << 20) & 0x300000)
-#define BP_AUDIOOUT_TEST_VAG_CLASSA         13
-#define BM_AUDIOOUT_TEST_VAG_CLASSA         0x2000
-#define BF_AUDIOOUT_TEST_VAG_CLASSA(v)      (((v) << 13) & 0x2000)
-#define BP_AUDIOOUT_TEST_VAG_DOUBLE_I       12
-#define BM_AUDIOOUT_TEST_VAG_DOUBLE_I       0x1000
-#define BF_AUDIOOUT_TEST_VAG_DOUBLE_I(v)    (((v) << 12) & 0x1000)
-#define BP_AUDIOOUT_TEST_DAC_CLASSA         2
-#define BM_AUDIOOUT_TEST_DAC_CLASSA         0x4
-#define BF_AUDIOOUT_TEST_DAC_CLASSA(v)      (((v) << 2) & 0x4)
-#define BP_AUDIOOUT_TEST_DAC_DOUBLE_I       1
-#define BM_AUDIOOUT_TEST_DAC_DOUBLE_I       0x2
-#define BF_AUDIOOUT_TEST_DAC_DOUBLE_I(v)    (((v) << 1) & 0x2)
-#define BP_AUDIOOUT_TEST_DAC_DIS_RTZ        0
-#define BM_AUDIOOUT_TEST_DAC_DIS_RTZ        0x1
-#define BF_AUDIOOUT_TEST_DAC_DIS_RTZ(v)     (((v) << 0) & 0x1)
-
-/**
- * Register: HW_AUDIOOUT_BISTCTRL
- * Address: 0xb0
- * SCT: yes
-*/
-#define HW_AUDIOOUT_BISTCTRL            (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xb0 + 0x0))
-#define HW_AUDIOOUT_BISTCTRL_SET        (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xb0 + 0x4))
-#define HW_AUDIOOUT_BISTCTRL_CLR        (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xb0 + 0x8))
-#define HW_AUDIOOUT_BISTCTRL_TOG        (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xb0 + 0xc))
-#define BP_AUDIOOUT_BISTCTRL_FAIL       3
-#define BM_AUDIOOUT_BISTCTRL_FAIL       0x8
-#define BF_AUDIOOUT_BISTCTRL_FAIL(v)    (((v) << 3) & 0x8)
-#define BP_AUDIOOUT_BISTCTRL_PASS       2
-#define BM_AUDIOOUT_BISTCTRL_PASS       0x4
-#define BF_AUDIOOUT_BISTCTRL_PASS(v)    (((v) << 2) & 0x4)
-#define BP_AUDIOOUT_BISTCTRL_DONE       1
-#define BM_AUDIOOUT_BISTCTRL_DONE       0x2
-#define BF_AUDIOOUT_BISTCTRL_DONE(v)    (((v) << 1) & 0x2)
-#define BP_AUDIOOUT_BISTCTRL_START      0
-#define BM_AUDIOOUT_BISTCTRL_START      0x1
-#define BF_AUDIOOUT_BISTCTRL_START(v)   (((v) << 0) & 0x1)
-
-/**
- * Register: HW_AUDIOOUT_BISTSTAT0
- * Address: 0xc0
- * SCT: no
-*/
-#define HW_AUDIOOUT_BISTSTAT0           (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xc0))
-#define BP_AUDIOOUT_BISTSTAT0_DATA      0
-#define BM_AUDIOOUT_BISTSTAT0_DATA      0xffffff
-#define BF_AUDIOOUT_BISTSTAT0_DATA(v)   (((v) << 0) & 0xffffff)
-
-/**
- * Register: HW_AUDIOOUT_BISTSTAT1
- * Address: 0xd0
- * SCT: no
-*/
-#define HW_AUDIOOUT_BISTSTAT1           (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xd0))
-#define BP_AUDIOOUT_BISTSTAT1_STATE     24
-#define BM_AUDIOOUT_BISTSTAT1_STATE     0x1f000000
-#define BF_AUDIOOUT_BISTSTAT1_STATE(v)  (((v) << 24) & 0x1f000000)
-#define BP_AUDIOOUT_BISTSTAT1_ADDR      0
-#define BM_AUDIOOUT_BISTSTAT1_ADDR      0xff
-#define BF_AUDIOOUT_BISTSTAT1_ADDR(v)   (((v) << 0) & 0xff)
-
-/**
- * Register: HW_AUDIOOUT_ANACLKCTRL
- * Address: 0xe0
- * SCT: yes
-*/
-#define HW_AUDIOOUT_ANACLKCTRL                  (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xe0 + 0x0))
-#define HW_AUDIOOUT_ANACLKCTRL_SET              (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xe0 + 0x4))
-#define HW_AUDIOOUT_ANACLKCTRL_CLR              (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xe0 + 0x8))
-#define HW_AUDIOOUT_ANACLKCTRL_TOG              (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xe0 + 0xc))
-#define BP_AUDIOOUT_ANACLKCTRL_CLKGATE          31
-#define BM_AUDIOOUT_ANACLKCTRL_CLKGATE          0x80000000
-#define BF_AUDIOOUT_ANACLKCTRL_CLKGATE(v)       (((v) << 31) & 0x80000000)
-#define BP_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK    4
-#define BM_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK    0x10
-#define BF_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK(v) (((v) << 4) & 0x10)
-#define BP_AUDIOOUT_ANACLKCTRL_DACDIV           0
-#define BM_AUDIOOUT_ANACLKCTRL_DACDIV           0x7
-#define BF_AUDIOOUT_ANACLKCTRL_DACDIV(v)        (((v) << 0) & 0x7)
-
-/**
- * Register: HW_AUDIOOUT_DATA
- * Address: 0xf0
- * SCT: yes
-*/
-#define HW_AUDIOOUT_DATA            (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xf0 + 0x0))
-#define HW_AUDIOOUT_DATA_SET        (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xf0 + 0x4))
-#define HW_AUDIOOUT_DATA_CLR        (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xf0 + 0x8))
-#define HW_AUDIOOUT_DATA_TOG        (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xf0 + 0xc))
-#define BP_AUDIOOUT_DATA_HIGH       16
-#define BM_AUDIOOUT_DATA_HIGH       0xffff0000
-#define BF_AUDIOOUT_DATA_HIGH(v)    (((v) << 16) & 0xffff0000)
-#define BP_AUDIOOUT_DATA_LOW        0
-#define BM_AUDIOOUT_DATA_LOW        0xffff
-#define BF_AUDIOOUT_DATA_LOW(v)     (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_AUDIOOUT_LINEOUTCTRL
- * Address: 0x100
- * SCT: yes
-*/
-#define HW_AUDIOOUT_LINEOUTCTRL                             (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x100 + 0x0))
-#define HW_AUDIOOUT_LINEOUTCTRL_SET                         (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x100 + 0x4))
-#define HW_AUDIOOUT_LINEOUTCTRL_CLR                         (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x100 + 0x8))
-#define HW_AUDIOOUT_LINEOUTCTRL_TOG                         (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x100 + 0xc))
-#define BP_AUDIOOUT_LINEOUTCTRL_VOLUME_UPDATE_PENDING       28
-#define BM_AUDIOOUT_LINEOUTCTRL_VOLUME_UPDATE_PENDING       0x10000000
-#define BF_AUDIOOUT_LINEOUTCTRL_VOLUME_UPDATE_PENDING(v)    (((v) << 28) & 0x10000000)
-#define BP_AUDIOOUT_LINEOUTCTRL_EN_LINEOUT_ZCD              25
-#define BM_AUDIOOUT_LINEOUTCTRL_EN_LINEOUT_ZCD              0x2000000
-#define BF_AUDIOOUT_LINEOUTCTRL_EN_LINEOUT_ZCD(v)           (((v) << 25) & 0x2000000)
-#define BP_AUDIOOUT_LINEOUTCTRL_MUTE                        24
-#define BM_AUDIOOUT_LINEOUTCTRL_MUTE                        0x1000000
-#define BF_AUDIOOUT_LINEOUTCTRL_MUTE(v)                     (((v) << 24) & 0x1000000)
-#define BP_AUDIOOUT_LINEOUTCTRL_VAG_CTRL                    20
-#define BM_AUDIOOUT_LINEOUTCTRL_VAG_CTRL                    0xf00000
-#define BF_AUDIOOUT_LINEOUTCTRL_VAG_CTRL(v)                 (((v) << 20) & 0xf00000)
-#define BP_AUDIOOUT_LINEOUTCTRL_OUT_CURRENT                 16
-#define BM_AUDIOOUT_LINEOUTCTRL_OUT_CURRENT                 0xf0000
-#define BF_AUDIOOUT_LINEOUTCTRL_OUT_CURRENT(v)              (((v) << 16) & 0xf0000)
-#define BP_AUDIOOUT_LINEOUTCTRL_CHARGE_CAP                  13
-#define BM_AUDIOOUT_LINEOUTCTRL_CHARGE_CAP                  0xe000
-#define BF_AUDIOOUT_LINEOUTCTRL_CHARGE_CAP(v)               (((v) << 13) & 0xe000)
-#define BP_AUDIOOUT_LINEOUTCTRL_VOLUME_LEFT                 8
-#define BM_AUDIOOUT_LINEOUTCTRL_VOLUME_LEFT                 0x1f00
-#define BF_AUDIOOUT_LINEOUTCTRL_VOLUME_LEFT(v)              (((v) << 8) & 0x1f00)
-#define BP_AUDIOOUT_LINEOUTCTRL_VOLUME_RIGHT                0
-#define BM_AUDIOOUT_LINEOUTCTRL_VOLUME_RIGHT                0x1f
-#define BF_AUDIOOUT_LINEOUTCTRL_VOLUME_RIGHT(v)             (((v) << 0) & 0x1f)
-
-/**
- * Register: HW_AUDIOOUT_VERSION
- * Address: 0x200
- * SCT: no
-*/
-#define HW_AUDIOOUT_VERSION             (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x200))
-#define BP_AUDIOOUT_VERSION_MAJOR       24
-#define BM_AUDIOOUT_VERSION_MAJOR       0xff000000
-#define BF_AUDIOOUT_VERSION_MAJOR(v)    (((v) << 24) & 0xff000000)
-#define BP_AUDIOOUT_VERSION_MINOR       16
-#define BM_AUDIOOUT_VERSION_MINOR       0xff0000
-#define BF_AUDIOOUT_VERSION_MINOR(v)    (((v) << 16) & 0xff0000)
-#define BP_AUDIOOUT_VERSION_STEP        0
-#define BM_AUDIOOUT_VERSION_STEP        0xffff
-#define BF_AUDIOOUT_VERSION_STEP(v)     (((v) << 0) & 0xffff)
-
-#endif /* __HEADERGEN__STMP3700__AUDIOOUT__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-clkctrl.h b/firmware/target/arm/imx233/regs/stmp3700/regs-clkctrl.h
deleted file mode 100644
index de75689842..0000000000
--- a/firmware/target/arm/imx233/regs/stmp3700/regs-clkctrl.h
+++ /dev/null
@@ -1,459 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3700:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__STMP3700__CLKCTRL__H__
-#define __HEADERGEN__STMP3700__CLKCTRL__H__
-
-#define REGS_CLKCTRL_BASE (0x80040000)
-
-#define REGS_CLKCTRL_VERSION "3.2.0"
-
-/**
- * Register: HW_CLKCTRL_PLLCTRL0
- * Address: 0
- * SCT: yes
-*/
-#define HW_CLKCTRL_PLLCTRL0                     (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x0 + 0x0))
-#define HW_CLKCTRL_PLLCTRL0_SET                 (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x0 + 0x4))
-#define HW_CLKCTRL_PLLCTRL0_CLR                 (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x0 + 0x8))
-#define HW_CLKCTRL_PLLCTRL0_TOG                 (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x0 + 0xc))
-#define BP_CLKCTRL_PLLCTRL0_LFR_SEL             28
-#define BM_CLKCTRL_PLLCTRL0_LFR_SEL             0x30000000
-#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__DEFAULT    0x0
-#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_2    0x1
-#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_05   0x2
-#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__UNDEFINED  0x3
-#define BF_CLKCTRL_PLLCTRL0_LFR_SEL(v)          (((v) << 28) & 0x30000000)
-#define BF_CLKCTRL_PLLCTRL0_LFR_SEL_V(v)        ((BV_CLKCTRL_PLLCTRL0_LFR_SEL__##v << 28) & 0x30000000)
-#define BP_CLKCTRL_PLLCTRL0_CP_SEL              24
-#define BM_CLKCTRL_PLLCTRL0_CP_SEL              0x3000000
-#define BV_CLKCTRL_PLLCTRL0_CP_SEL__DEFAULT     0x0
-#define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_2     0x1
-#define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_05    0x2
-#define BV_CLKCTRL_PLLCTRL0_CP_SEL__UNDEFINED   0x3
-#define BF_CLKCTRL_PLLCTRL0_CP_SEL(v)           (((v) << 24) & 0x3000000)
-#define BF_CLKCTRL_PLLCTRL0_CP_SEL_V(v)         ((BV_CLKCTRL_PLLCTRL0_CP_SEL__##v << 24) & 0x3000000)
-#define BP_CLKCTRL_PLLCTRL0_DIV_SEL             20
-#define BM_CLKCTRL_PLLCTRL0_DIV_SEL             0x300000
-#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__DEFAULT    0x0
-#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWER      0x1
-#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWEST     0x2
-#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__UNDEFINED  0x3
-#define BF_CLKCTRL_PLLCTRL0_DIV_SEL(v)          (((v) << 20) & 0x300000)
-#define BF_CLKCTRL_PLLCTRL0_DIV_SEL_V(v)        ((BV_CLKCTRL_PLLCTRL0_DIV_SEL__##v << 20) & 0x300000)
-#define BP_CLKCTRL_PLLCTRL0_EN_USB_CLKS         18
-#define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS         0x40000
-#define BF_CLKCTRL_PLLCTRL0_EN_USB_CLKS(v)      (((v) << 18) & 0x40000)
-#define BP_CLKCTRL_PLLCTRL0_POWER               16
-#define BM_CLKCTRL_PLLCTRL0_POWER               0x10000
-#define BF_CLKCTRL_PLLCTRL0_POWER(v)            (((v) << 16) & 0x10000)
-
-/**
- * Register: HW_CLKCTRL_PLLCTRL1
- * Address: 0x10
- * SCT: no
-*/
-#define HW_CLKCTRL_PLLCTRL1                 (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x10))
-#define BP_CLKCTRL_PLLCTRL1_LOCK            31
-#define BM_CLKCTRL_PLLCTRL1_LOCK            0x80000000
-#define BF_CLKCTRL_PLLCTRL1_LOCK(v)         (((v) << 31) & 0x80000000)
-#define BP_CLKCTRL_PLLCTRL1_FORCE_LOCK      30
-#define BM_CLKCTRL_PLLCTRL1_FORCE_LOCK      0x40000000
-#define BF_CLKCTRL_PLLCTRL1_FORCE_LOCK(v)   (((v) << 30) & 0x40000000)
-#define BP_CLKCTRL_PLLCTRL1_LOCK_COUNT      0
-#define BM_CLKCTRL_PLLCTRL1_LOCK_COUNT      0xffff
-#define BF_CLKCTRL_PLLCTRL1_LOCK_COUNT(v)   (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_CLKCTRL_CPU
- * Address: 0x20
- * SCT: yes
-*/
-#define HW_CLKCTRL_CPU                      (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x20 + 0x0))
-#define HW_CLKCTRL_CPU_SET                  (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x20 + 0x4))
-#define HW_CLKCTRL_CPU_CLR                  (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x20 + 0x8))
-#define HW_CLKCTRL_CPU_TOG                  (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x20 + 0xc))
-#define BP_CLKCTRL_CPU_BUSY_REF_XTAL        29
-#define BM_CLKCTRL_CPU_BUSY_REF_XTAL        0x20000000
-#define BF_CLKCTRL_CPU_BUSY_REF_XTAL(v)     (((v) << 29) & 0x20000000)
-#define BP_CLKCTRL_CPU_BUSY_REF_CPU         28
-#define BM_CLKCTRL_CPU_BUSY_REF_CPU         0x10000000
-#define BF_CLKCTRL_CPU_BUSY_REF_CPU(v)      (((v) << 28) & 0x10000000)
-#define BP_CLKCTRL_CPU_DIV_XTAL_FRAC_EN     26
-#define BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN     0x4000000
-#define BF_CLKCTRL_CPU_DIV_XTAL_FRAC_EN(v)  (((v) << 26) & 0x4000000)
-#define BP_CLKCTRL_CPU_DIV_XTAL             16
-#define BM_CLKCTRL_CPU_DIV_XTAL             0x3ff0000
-#define BF_CLKCTRL_CPU_DIV_XTAL(v)          (((v) << 16) & 0x3ff0000)
-#define BP_CLKCTRL_CPU_INTERRUPT_WAIT       12
-#define BM_CLKCTRL_CPU_INTERRUPT_WAIT       0x1000
-#define BF_CLKCTRL_CPU_INTERRUPT_WAIT(v)    (((v) << 12) & 0x1000)
-#define BP_CLKCTRL_CPU_DIV_CPU_FRAC_EN      10
-#define BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN      0x400
-#define BF_CLKCTRL_CPU_DIV_CPU_FRAC_EN(v)   (((v) << 10) & 0x400)
-#define BP_CLKCTRL_CPU_DIV_CPU              0
-#define BM_CLKCTRL_CPU_DIV_CPU              0x3ff
-#define BF_CLKCTRL_CPU_DIV_CPU(v)           (((v) << 0) & 0x3ff)
-
-/**
- * Register: HW_CLKCTRL_HBUS
- * Address: 0x30
- * SCT: yes
-*/
-#define HW_CLKCTRL_HBUS                             (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x30 + 0x0))
-#define HW_CLKCTRL_HBUS_SET                         (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x30 + 0x4))
-#define HW_CLKCTRL_HBUS_CLR                         (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x30 + 0x8))
-#define HW_CLKCTRL_HBUS_TOG                         (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x30 + 0xc))
-#define BP_CLKCTRL_HBUS_BUSY                        29
-#define BM_CLKCTRL_HBUS_BUSY                        0x20000000
-#define BF_CLKCTRL_HBUS_BUSY(v)                     (((v) << 29) & 0x20000000)
-#define BP_CLKCTRL_HBUS_APBHDMA_AS_ENABLE           26
-#define BM_CLKCTRL_HBUS_APBHDMA_AS_ENABLE           0x4000000
-#define BF_CLKCTRL_HBUS_APBHDMA_AS_ENABLE(v)        (((v) << 26) & 0x4000000)
-#define BP_CLKCTRL_HBUS_APBXDMA_AS_ENABLE           25
-#define BM_CLKCTRL_HBUS_APBXDMA_AS_ENABLE           0x2000000
-#define BF_CLKCTRL_HBUS_APBXDMA_AS_ENABLE(v)        (((v) << 25) & 0x2000000)
-#define BP_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE       24
-#define BM_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE       0x1000000
-#define BF_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE(v)    (((v) << 24) & 0x1000000)
-#define BP_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE           23
-#define BM_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE           0x800000
-#define BF_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE(v)        (((v) << 23) & 0x800000)
-#define BP_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE          22
-#define BM_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE          0x400000
-#define BF_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE(v)       (((v) << 22) & 0x400000)
-#define BP_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE         21
-#define BM_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE         0x200000
-#define BF_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE(v)      (((v) << 21) & 0x200000)
-#define BP_CLKCTRL_HBUS_AUTO_SLOW_MODE              20
-#define BM_CLKCTRL_HBUS_AUTO_SLOW_MODE              0x100000
-#define BF_CLKCTRL_HBUS_AUTO_SLOW_MODE(v)           (((v) << 20) & 0x100000)
-#define BP_CLKCTRL_HBUS_SLOW_DIV                    16
-#define BM_CLKCTRL_HBUS_SLOW_DIV                    0x70000
-#define BV_CLKCTRL_HBUS_SLOW_DIV__BY1               0x0
-#define BV_CLKCTRL_HBUS_SLOW_DIV__BY2               0x1
-#define BV_CLKCTRL_HBUS_SLOW_DIV__BY4               0x2
-#define BV_CLKCTRL_HBUS_SLOW_DIV__BY8               0x3
-#define BV_CLKCTRL_HBUS_SLOW_DIV__BY16              0x4
-#define BV_CLKCTRL_HBUS_SLOW_DIV__BY32              0x5
-#define BF_CLKCTRL_HBUS_SLOW_DIV(v)                 (((v) << 16) & 0x70000)
-#define BF_CLKCTRL_HBUS_SLOW_DIV_V(v)               ((BV_CLKCTRL_HBUS_SLOW_DIV__##v << 16) & 0x70000)
-#define BP_CLKCTRL_HBUS_DIV_FRAC_EN                 5
-#define BM_CLKCTRL_HBUS_DIV_FRAC_EN                 0x20
-#define BF_CLKCTRL_HBUS_DIV_FRAC_EN(v)              (((v) << 5) & 0x20)
-#define BP_CLKCTRL_HBUS_DIV                         0
-#define BM_CLKCTRL_HBUS_DIV                         0x1f
-#define BF_CLKCTRL_HBUS_DIV(v)                      (((v) << 0) & 0x1f)
-
-/**
- * Register: HW_CLKCTRL_XBUS
- * Address: 0x40
- * SCT: no
-*/
-#define HW_CLKCTRL_XBUS                 (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x40))
-#define BP_CLKCTRL_XBUS_BUSY            31
-#define BM_CLKCTRL_XBUS_BUSY            0x80000000
-#define BF_CLKCTRL_XBUS_BUSY(v)         (((v) << 31) & 0x80000000)
-#define BP_CLKCTRL_XBUS_DIV_FRAC_EN     10
-#define BM_CLKCTRL_XBUS_DIV_FRAC_EN     0x400
-#define BF_CLKCTRL_XBUS_DIV_FRAC_EN(v)  (((v) << 10) & 0x400)
-#define BP_CLKCTRL_XBUS_DIV             0
-#define BM_CLKCTRL_XBUS_DIV             0x3ff
-#define BF_CLKCTRL_XBUS_DIV(v)          (((v) << 0) & 0x3ff)
-
-/**
- * Register: HW_CLKCTRL_XTAL
- * Address: 0x50
- * SCT: yes
-*/
-#define HW_CLKCTRL_XTAL                         (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x50 + 0x0))
-#define HW_CLKCTRL_XTAL_SET                     (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x50 + 0x4))
-#define HW_CLKCTRL_XTAL_CLR                     (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x50 + 0x8))
-#define HW_CLKCTRL_XTAL_TOG                     (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x50 + 0xc))
-#define BP_CLKCTRL_XTAL_UART_CLK_GATE           31
-#define BM_CLKCTRL_XTAL_UART_CLK_GATE           0x80000000
-#define BF_CLKCTRL_XTAL_UART_CLK_GATE(v)        (((v) << 31) & 0x80000000)
-#define BP_CLKCTRL_XTAL_FILT_CLK24M_GATE        30
-#define BM_CLKCTRL_XTAL_FILT_CLK24M_GATE        0x40000000
-#define BF_CLKCTRL_XTAL_FILT_CLK24M_GATE(v)     (((v) << 30) & 0x40000000)
-#define BP_CLKCTRL_XTAL_PWM_CLK24M_GATE         29
-#define BM_CLKCTRL_XTAL_PWM_CLK24M_GATE         0x20000000
-#define BF_CLKCTRL_XTAL_PWM_CLK24M_GATE(v)      (((v) << 29) & 0x20000000)
-#define BP_CLKCTRL_XTAL_DRI_CLK24M_GATE         28
-#define BM_CLKCTRL_XTAL_DRI_CLK24M_GATE         0x10000000
-#define BF_CLKCTRL_XTAL_DRI_CLK24M_GATE(v)      (((v) << 28) & 0x10000000)
-#define BP_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE      27
-#define BM_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE      0x8000000
-#define BF_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE(v)   (((v) << 27) & 0x8000000)
-#define BP_CLKCTRL_XTAL_TIMROT_CLK32K_GATE      26
-#define BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE      0x4000000
-#define BF_CLKCTRL_XTAL_TIMROT_CLK32K_GATE(v)   (((v) << 26) & 0x4000000)
-#define BP_CLKCTRL_XTAL_DIV_UART                0
-#define BM_CLKCTRL_XTAL_DIV_UART                0x3
-#define BF_CLKCTRL_XTAL_DIV_UART(v)             (((v) << 0) & 0x3)
-
-/**
- * Register: HW_CLKCTRL_PIX
- * Address: 0x60
- * SCT: no
-*/
-#define HW_CLKCTRL_PIX                  (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x60))
-#define BP_CLKCTRL_PIX_CLKGATE          31
-#define BM_CLKCTRL_PIX_CLKGATE          0x80000000
-#define BF_CLKCTRL_PIX_CLKGATE(v)       (((v) << 31) & 0x80000000)
-#define BP_CLKCTRL_PIX_BUSY             29
-#define BM_CLKCTRL_PIX_BUSY             0x20000000
-#define BF_CLKCTRL_PIX_BUSY(v)          (((v) << 29) & 0x20000000)
-#define BP_CLKCTRL_PIX_DIV_FRAC_EN      15
-#define BM_CLKCTRL_PIX_DIV_FRAC_EN      0x8000
-#define BF_CLKCTRL_PIX_DIV_FRAC_EN(v)   (((v) << 15) & 0x8000)
-#define BP_CLKCTRL_PIX_DIV              0
-#define BM_CLKCTRL_PIX_DIV              0x7fff
-#define BF_CLKCTRL_PIX_DIV(v)           (((v) << 0) & 0x7fff)
-
-/**
- * Register: HW_CLKCTRL_SSP
- * Address: 0x70
- * SCT: no
-*/
-#define HW_CLKCTRL_SSP                  (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x70))
-#define BP_CLKCTRL_SSP_CLKGATE          31
-#define BM_CLKCTRL_SSP_CLKGATE          0x80000000
-#define BF_CLKCTRL_SSP_CLKGATE(v)       (((v) << 31) & 0x80000000)
-#define BP_CLKCTRL_SSP_BUSY             29
-#define BM_CLKCTRL_SSP_BUSY             0x20000000
-#define BF_CLKCTRL_SSP_BUSY(v)          (((v) << 29) & 0x20000000)
-#define BP_CLKCTRL_SSP_DIV_FRAC_EN      9
-#define BM_CLKCTRL_SSP_DIV_FRAC_EN      0x200
-#define BF_CLKCTRL_SSP_DIV_FRAC_EN(v)   (((v) << 9) & 0x200)
-#define BP_CLKCTRL_SSP_DIV              0
-#define BM_CLKCTRL_SSP_DIV              0x1ff
-#define BF_CLKCTRL_SSP_DIV(v)           (((v) << 0) & 0x1ff)
-
-/**
- * Register: HW_CLKCTRL_GPMI
- * Address: 0x80
- * SCT: no
-*/
-#define HW_CLKCTRL_GPMI                 (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x80))
-#define BP_CLKCTRL_GPMI_CLKGATE         31
-#define BM_CLKCTRL_GPMI_CLKGATE         0x80000000
-#define BF_CLKCTRL_GPMI_CLKGATE(v)      (((v) << 31) & 0x80000000)
-#define BP_CLKCTRL_GPMI_BUSY            29
-#define BM_CLKCTRL_GPMI_BUSY            0x20000000
-#define BF_CLKCTRL_GPMI_BUSY(v)         (((v) << 29) & 0x20000000)
-#define BP_CLKCTRL_GPMI_DIV_FRAC_EN     10
-#define BM_CLKCTRL_GPMI_DIV_FRAC_EN     0x400
-#define BF_CLKCTRL_GPMI_DIV_FRAC_EN(v)  (((v) << 10) & 0x400)
-#define BP_CLKCTRL_GPMI_DIV             0
-#define BM_CLKCTRL_GPMI_DIV             0x3ff
-#define BF_CLKCTRL_GPMI_DIV(v)          (((v) << 0) & 0x3ff)
-
-/**
- * Register: HW_CLKCTRL_SPDIF
- * Address: 0x90
- * SCT: no
-*/
-#define HW_CLKCTRL_SPDIF            (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x90))
-#define BP_CLKCTRL_SPDIF_CLKGATE    31
-#define BM_CLKCTRL_SPDIF_CLKGATE    0x80000000
-#define BF_CLKCTRL_SPDIF_CLKGATE(v) (((v) << 31) & 0x80000000)
-
-/**
- * Register: HW_CLKCTRL_EMI
- * Address: 0xa0
- * SCT: no
-*/
-#define HW_CLKCTRL_EMI                      (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xa0))
-#define BP_CLKCTRL_EMI_CLKGATE              31
-#define BM_CLKCTRL_EMI_CLKGATE              0x80000000
-#define BF_CLKCTRL_EMI_CLKGATE(v)           (((v) << 31) & 0x80000000)
-#define BP_CLKCTRL_EMI_BUSY_REF_XTAL        29
-#define BM_CLKCTRL_EMI_BUSY_REF_XTAL        0x20000000
-#define BF_CLKCTRL_EMI_BUSY_REF_XTAL(v)     (((v) << 29) & 0x20000000)
-#define BP_CLKCTRL_EMI_BUSY_REF_EMI         28
-#define BM_CLKCTRL_EMI_BUSY_REF_EMI         0x10000000
-#define BF_CLKCTRL_EMI_BUSY_REF_EMI(v)      (((v) << 28) & 0x10000000)
-#define BP_CLKCTRL_EMI_BUSY_DCC_RESYNC      17
-#define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC      0x20000
-#define BF_CLKCTRL_EMI_BUSY_DCC_RESYNC(v)   (((v) << 17) & 0x20000)
-#define BP_CLKCTRL_EMI_DCC_RESYNC_ENABLE    16
-#define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE    0x10000
-#define BF_CLKCTRL_EMI_DCC_RESYNC_ENABLE(v) (((v) << 16) & 0x10000)
-#define BP_CLKCTRL_EMI_DIV_XTAL             8
-#define BM_CLKCTRL_EMI_DIV_XTAL             0xf00
-#define BF_CLKCTRL_EMI_DIV_XTAL(v)          (((v) << 8) & 0xf00)
-#define BP_CLKCTRL_EMI_DIV_EMI              0
-#define BM_CLKCTRL_EMI_DIV_EMI              0x3f
-#define BF_CLKCTRL_EMI_DIV_EMI(v)           (((v) << 0) & 0x3f)
-
-/**
- * Register: HW_CLKCTRL_IR
- * Address: 0xb0
- * SCT: no
-*/
-#define HW_CLKCTRL_IR               (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xb0))
-#define BP_CLKCTRL_IR_CLKGATE       31
-#define BM_CLKCTRL_IR_CLKGATE       0x80000000
-#define BF_CLKCTRL_IR_CLKGATE(v)    (((v) << 31) & 0x80000000)
-#define BP_CLKCTRL_IR_AUTO_DIV      29
-#define BM_CLKCTRL_IR_AUTO_DIV      0x20000000
-#define BF_CLKCTRL_IR_AUTO_DIV(v)   (((v) << 29) & 0x20000000)
-#define BP_CLKCTRL_IR_IR_BUSY       28
-#define BM_CLKCTRL_IR_IR_BUSY       0x10000000
-#define BF_CLKCTRL_IR_IR_BUSY(v)    (((v) << 28) & 0x10000000)
-#define BP_CLKCTRL_IR_IROV_BUSY     27
-#define BM_CLKCTRL_IR_IROV_BUSY     0x8000000
-#define BF_CLKCTRL_IR_IROV_BUSY(v)  (((v) << 27) & 0x8000000)
-#define BP_CLKCTRL_IR_IROV_DIV      16
-#define BM_CLKCTRL_IR_IROV_DIV      0x1ff0000
-#define BF_CLKCTRL_IR_IROV_DIV(v)   (((v) << 16) & 0x1ff0000)
-#define BP_CLKCTRL_IR_IR_DIV        0
-#define BM_CLKCTRL_IR_IR_DIV        0x3ff
-#define BF_CLKCTRL_IR_IR_DIV(v)     (((v) << 0) & 0x3ff)
-
-/**
- * Register: HW_CLKCTRL_SAIF
- * Address: 0xc0
- * SCT: no
-*/
-#define HW_CLKCTRL_SAIF                 (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xc0))
-#define BP_CLKCTRL_SAIF_CLKGATE         31
-#define BM_CLKCTRL_SAIF_CLKGATE         0x80000000
-#define BF_CLKCTRL_SAIF_CLKGATE(v)      (((v) << 31) & 0x80000000)
-#define BP_CLKCTRL_SAIF_BUSY            29
-#define BM_CLKCTRL_SAIF_BUSY            0x20000000
-#define BF_CLKCTRL_SAIF_BUSY(v)         (((v) << 29) & 0x20000000)
-#define BP_CLKCTRL_SAIF_DIV_FRAC_EN     16
-#define BM_CLKCTRL_SAIF_DIV_FRAC_EN     0x10000
-#define BF_CLKCTRL_SAIF_DIV_FRAC_EN(v)  (((v) << 16) & 0x10000)
-#define BP_CLKCTRL_SAIF_DIV             0
-#define BM_CLKCTRL_SAIF_DIV             0xffff
-#define BF_CLKCTRL_SAIF_DIV(v)          (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_CLKCTRL_FRAC
- * Address: 0xd0
- * SCT: yes
-*/
-#define HW_CLKCTRL_FRAC                 (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xd0 + 0x0))
-#define HW_CLKCTRL_FRAC_SET             (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xd0 + 0x4))
-#define HW_CLKCTRL_FRAC_CLR             (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xd0 + 0x8))
-#define HW_CLKCTRL_FRAC_TOG             (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xd0 + 0xc))
-#define BP_CLKCTRL_FRAC_CLKGATEIO       31
-#define BM_CLKCTRL_FRAC_CLKGATEIO       0x80000000
-#define BF_CLKCTRL_FRAC_CLKGATEIO(v)    (((v) << 31) & 0x80000000)
-#define BP_CLKCTRL_FRAC_IO_STABLE       30
-#define BM_CLKCTRL_FRAC_IO_STABLE       0x40000000
-#define BF_CLKCTRL_FRAC_IO_STABLE(v)    (((v) << 30) & 0x40000000)
-#define BP_CLKCTRL_FRAC_IOFRAC          24
-#define BM_CLKCTRL_FRAC_IOFRAC          0x3f000000
-#define BF_CLKCTRL_FRAC_IOFRAC(v)       (((v) << 24) & 0x3f000000)
-#define BP_CLKCTRL_FRAC_CLKGATEPIX      23
-#define BM_CLKCTRL_FRAC_CLKGATEPIX      0x800000
-#define BF_CLKCTRL_FRAC_CLKGATEPIX(v)   (((v) << 23) & 0x800000)
-#define BP_CLKCTRL_FRAC_PIX_STABLE      22
-#define BM_CLKCTRL_FRAC_PIX_STABLE      0x400000
-#define BF_CLKCTRL_FRAC_PIX_STABLE(v)   (((v) << 22) & 0x400000)
-#define BP_CLKCTRL_FRAC_PIXFRAC         16
-#define BM_CLKCTRL_FRAC_PIXFRAC         0x3f0000
-#define BF_CLKCTRL_FRAC_PIXFRAC(v)      (((v) << 16) & 0x3f0000)
-#define BP_CLKCTRL_FRAC_CLKGATEEMI      15
-#define BM_CLKCTRL_FRAC_CLKGATEEMI      0x8000
-#define BF_CLKCTRL_FRAC_CLKGATEEMI(v)   (((v) << 15) & 0x8000)
-#define BP_CLKCTRL_FRAC_EMI_STABLE      14
-#define BM_CLKCTRL_FRAC_EMI_STABLE      0x4000
-#define BF_CLKCTRL_FRAC_EMI_STABLE(v)   (((v) << 14) & 0x4000)
-#define BP_CLKCTRL_FRAC_EMIFRAC         8
-#define BM_CLKCTRL_FRAC_EMIFRAC         0x3f00
-#define BF_CLKCTRL_FRAC_EMIFRAC(v)      (((v) << 8) & 0x3f00)
-#define BP_CLKCTRL_FRAC_CLKGATECPU      7
-#define BM_CLKCTRL_FRAC_CLKGATECPU      0x80
-#define BF_CLKCTRL_FRAC_CLKGATECPU(v)   (((v) << 7) & 0x80)
-#define BP_CLKCTRL_FRAC_CPU_STABLE      6
-#define BM_CLKCTRL_FRAC_CPU_STABLE      0x40
-#define BF_CLKCTRL_FRAC_CPU_STABLE(v)   (((v) << 6) & 0x40)
-#define BP_CLKCTRL_FRAC_CPUFRAC         0
-#define BM_CLKCTRL_FRAC_CPUFRAC         0x3f
-#define BF_CLKCTRL_FRAC_CPUFRAC(v)      (((v) << 0) & 0x3f)
-
-/**
- * Register: HW_CLKCTRL_CLKSEQ
- * Address: 0xe0
- * SCT: yes
-*/
-#define HW_CLKCTRL_CLKSEQ                   (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xe0 + 0x0))
-#define HW_CLKCTRL_CLKSEQ_SET               (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xe0 + 0x4))
-#define HW_CLKCTRL_CLKSEQ_CLR               (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xe0 + 0x8))
-#define HW_CLKCTRL_CLKSEQ_TOG               (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xe0 + 0xc))
-#define BP_CLKCTRL_CLKSEQ_BYPASS_CPU        7
-#define BM_CLKCTRL_CLKSEQ_BYPASS_CPU        0x80
-#define BF_CLKCTRL_CLKSEQ_BYPASS_CPU(v)     (((v) << 7) & 0x80)
-#define BP_CLKCTRL_CLKSEQ_BYPASS_EMI        6
-#define BM_CLKCTRL_CLKSEQ_BYPASS_EMI        0x40
-#define BF_CLKCTRL_CLKSEQ_BYPASS_EMI(v)     (((v) << 6) & 0x40)
-#define BP_CLKCTRL_CLKSEQ_BYPASS_SSP        5
-#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP        0x20
-#define BF_CLKCTRL_CLKSEQ_BYPASS_SSP(v)     (((v) << 5) & 0x20)
-#define BP_CLKCTRL_CLKSEQ_BYPASS_GPMI       4
-#define BM_CLKCTRL_CLKSEQ_BYPASS_GPMI       0x10
-#define BF_CLKCTRL_CLKSEQ_BYPASS_GPMI(v)    (((v) << 4) & 0x10)
-#define BP_CLKCTRL_CLKSEQ_BYPASS_IR         3
-#define BM_CLKCTRL_CLKSEQ_BYPASS_IR         0x8
-#define BF_CLKCTRL_CLKSEQ_BYPASS_IR(v)      (((v) << 3) & 0x8)
-#define BP_CLKCTRL_CLKSEQ_BYPASS_PIX        1
-#define BM_CLKCTRL_CLKSEQ_BYPASS_PIX        0x2
-#define BF_CLKCTRL_CLKSEQ_BYPASS_PIX(v)     (((v) << 1) & 0x2)
-#define BP_CLKCTRL_CLKSEQ_BYPASS_SAIF       0
-#define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF       0x1
-#define BF_CLKCTRL_CLKSEQ_BYPASS_SAIF(v)    (((v) << 0) & 0x1)
-
-/**
- * Register: HW_CLKCTRL_RESET
- * Address: 0xf0
- * SCT: no
-*/
-#define HW_CLKCTRL_RESET            (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xf0))
-#define BP_CLKCTRL_RESET_CHIP       1
-#define BM_CLKCTRL_RESET_CHIP       0x2
-#define BF_CLKCTRL_RESET_CHIP(v)    (((v) << 1) & 0x2)
-#define BP_CLKCTRL_RESET_DIG        0
-#define BM_CLKCTRL_RESET_DIG        0x1
-#define BF_CLKCTRL_RESET_DIG(v)     (((v) << 0) & 0x1)
-
-/**
- * Register: HW_CLKCTRL_VERSION
- * Address: 0x100
- * SCT: no
-*/
-#define HW_CLKCTRL_VERSION          (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x100))
-#define BP_CLKCTRL_VERSION_MAJOR    24
-#define BM_CLKCTRL_VERSION_MAJOR    0xff000000
-#define BF_CLKCTRL_VERSION_MAJOR(v) (((v) << 24) & 0xff000000)
-#define BP_CLKCTRL_VERSION_MINOR    16
-#define BM_CLKCTRL_VERSION_MINOR    0xff0000
-#define BF_CLKCTRL_VERSION_MINOR(v) (((v) << 16) & 0xff0000)
-#define BP_CLKCTRL_VERSION_STEP     0
-#define BM_CLKCTRL_VERSION_STEP     0xffff
-#define BF_CLKCTRL_VERSION_STEP(v)  (((v) << 0) & 0xffff)
-
-#endif /* __HEADERGEN__STMP3700__CLKCTRL__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-dcp.h b/firmware/target/arm/imx233/regs/stmp3700/regs-dcp.h
deleted file mode 100644
index fedb492614..0000000000
--- a/firmware/target/arm/imx233/regs/stmp3700/regs-dcp.h
+++ /dev/null
@@ -1,707 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3700:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__STMP3700__DCP__H__
-#define __HEADERGEN__STMP3700__DCP__H__
-
-#define REGS_DCP_BASE (0x80028000)
-
-#define REGS_DCP_VERSION "3.2.0"
-
-/**
- * Register: HW_DCP_CTRL
- * Address: 0
- * SCT: yes
-*/
-#define HW_DCP_CTRL                                 (*(volatile unsigned long *)(REGS_DCP_BASE + 0x0 + 0x0))
-#define HW_DCP_CTRL_SET                             (*(volatile unsigned long *)(REGS_DCP_BASE + 0x0 + 0x4))
-#define HW_DCP_CTRL_CLR                             (*(volatile unsigned long *)(REGS_DCP_BASE + 0x0 + 0x8))
-#define HW_DCP_CTRL_TOG                             (*(volatile unsigned long *)(REGS_DCP_BASE + 0x0 + 0xc))
-#define BP_DCP_CTRL_SFTRST                          31
-#define BM_DCP_CTRL_SFTRST                          0x80000000
-#define BF_DCP_CTRL_SFTRST(v)                       (((v) << 31) & 0x80000000)
-#define BP_DCP_CTRL_CLKGATE                         30
-#define BM_DCP_CTRL_CLKGATE                         0x40000000
-#define BF_DCP_CTRL_CLKGATE(v)                      (((v) << 30) & 0x40000000)
-#define BP_DCP_CTRL_PRESENT_CRYPTO                  29
-#define BM_DCP_CTRL_PRESENT_CRYPTO                  0x20000000
-#define BV_DCP_CTRL_PRESENT_CRYPTO__Present         0x1
-#define BV_DCP_CTRL_PRESENT_CRYPTO__Absent          0x0
-#define BF_DCP_CTRL_PRESENT_CRYPTO(v)               (((v) << 29) & 0x20000000)
-#define BF_DCP_CTRL_PRESENT_CRYPTO_V(v)             ((BV_DCP_CTRL_PRESENT_CRYPTO__##v << 29) & 0x20000000)
-#define BP_DCP_CTRL_PRESENT_CSC                     28
-#define BM_DCP_CTRL_PRESENT_CSC                     0x10000000
-#define BV_DCP_CTRL_PRESENT_CSC__Present            0x1
-#define BV_DCP_CTRL_PRESENT_CSC__Absent             0x0
-#define BF_DCP_CTRL_PRESENT_CSC(v)                  (((v) << 28) & 0x10000000)
-#define BF_DCP_CTRL_PRESENT_CSC_V(v)                ((BV_DCP_CTRL_PRESENT_CSC__##v << 28) & 0x10000000)
-#define BP_DCP_CTRL_GATHER_RESIDUAL_WRITES          23
-#define BM_DCP_CTRL_GATHER_RESIDUAL_WRITES          0x800000
-#define BF_DCP_CTRL_GATHER_RESIDUAL_WRITES(v)       (((v) << 23) & 0x800000)
-#define BP_DCP_CTRL_ENABLE_CONTEXT_CACHING          22
-#define BM_DCP_CTRL_ENABLE_CONTEXT_CACHING          0x400000
-#define BF_DCP_CTRL_ENABLE_CONTEXT_CACHING(v)       (((v) << 22) & 0x400000)
-#define BP_DCP_CTRL_ENABLE_CONTEXT_SWITCHING        21
-#define BM_DCP_CTRL_ENABLE_CONTEXT_SWITCHING        0x200000
-#define BF_DCP_CTRL_ENABLE_CONTEXT_SWITCHING(v)     (((v) << 21) & 0x200000)
-#define BP_DCP_CTRL_CSC_INTERRUPT_ENABLE            8
-#define BM_DCP_CTRL_CSC_INTERRUPT_ENABLE            0x100
-#define BF_DCP_CTRL_CSC_INTERRUPT_ENABLE(v)         (((v) << 8) & 0x100)
-#define BP_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE        0
-#define BM_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE        0xff
-#define BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__CH0   0x1
-#define BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__CH1   0x2
-#define BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__CH2   0x4
-#define BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__CH3   0x8
-#define BF_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE(v)     (((v) << 0) & 0xff)
-#define BF_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_V(v)   ((BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__##v << 0) & 0xff)
-
-/**
- * Register: HW_DCP_STAT
- * Address: 0x10
- * SCT: yes
-*/
-#define HW_DCP_STAT                     (*(volatile unsigned long *)(REGS_DCP_BASE + 0x10 + 0x0))
-#define HW_DCP_STAT_SET                 (*(volatile unsigned long *)(REGS_DCP_BASE + 0x10 + 0x4))
-#define HW_DCP_STAT_CLR                 (*(volatile unsigned long *)(REGS_DCP_BASE + 0x10 + 0x8))
-#define HW_DCP_STAT_TOG                 (*(volatile unsigned long *)(REGS_DCP_BASE + 0x10 + 0xc))
-#define BP_DCP_STAT_OTP_KEY_READY       28
-#define BM_DCP_STAT_OTP_KEY_READY       0x10000000
-#define BF_DCP_STAT_OTP_KEY_READY(v)    (((v) << 28) & 0x10000000)
-#define BP_DCP_STAT_CUR_CHANNEL         24
-#define BM_DCP_STAT_CUR_CHANNEL         0xf000000
-#define BV_DCP_STAT_CUR_CHANNEL__None   0x0
-#define BV_DCP_STAT_CUR_CHANNEL__CH0    0x1
-#define BV_DCP_STAT_CUR_CHANNEL__CH1    0x2
-#define BV_DCP_STAT_CUR_CHANNEL__CH2    0x3
-#define BV_DCP_STAT_CUR_CHANNEL__CH3    0x4
-#define BV_DCP_STAT_CUR_CHANNEL__CSC    0x8
-#define BF_DCP_STAT_CUR_CHANNEL(v)      (((v) << 24) & 0xf000000)
-#define BF_DCP_STAT_CUR_CHANNEL_V(v)    ((BV_DCP_STAT_CUR_CHANNEL__##v << 24) & 0xf000000)
-#define BP_DCP_STAT_READY_CHANNELS      16
-#define BM_DCP_STAT_READY_CHANNELS      0xff0000
-#define BV_DCP_STAT_READY_CHANNELS__CH0 0x1
-#define BV_DCP_STAT_READY_CHANNELS__CH1 0x2
-#define BV_DCP_STAT_READY_CHANNELS__CH2 0x4
-#define BV_DCP_STAT_READY_CHANNELS__CH3 0x8
-#define BF_DCP_STAT_READY_CHANNELS(v)   (((v) << 16) & 0xff0000)
-#define BF_DCP_STAT_READY_CHANNELS_V(v) ((BV_DCP_STAT_READY_CHANNELS__##v << 16) & 0xff0000)
-#define BP_DCP_STAT_CSCIRQ              8
-#define BM_DCP_STAT_CSCIRQ              0x100
-#define BF_DCP_STAT_CSCIRQ(v)           (((v) << 8) & 0x100)
-#define BP_DCP_STAT_IRQ                 0
-#define BM_DCP_STAT_IRQ                 0xf
-#define BF_DCP_STAT_IRQ(v)              (((v) << 0) & 0xf)
-
-/**
- * Register: HW_DCP_CHANNELCTRL
- * Address: 0x20
- * SCT: yes
-*/
-#define HW_DCP_CHANNELCTRL                              (*(volatile unsigned long *)(REGS_DCP_BASE + 0x20 + 0x0))
-#define HW_DCP_CHANNELCTRL_SET                          (*(volatile unsigned long *)(REGS_DCP_BASE + 0x20 + 0x4))
-#define HW_DCP_CHANNELCTRL_CLR                          (*(volatile unsigned long *)(REGS_DCP_BASE + 0x20 + 0x8))
-#define HW_DCP_CHANNELCTRL_TOG                          (*(volatile unsigned long *)(REGS_DCP_BASE + 0x20 + 0xc))
-#define BP_DCP_CHANNELCTRL_CSC_PRIORITY                 17
-#define BM_DCP_CHANNELCTRL_CSC_PRIORITY                 0x60000
-#define BV_DCP_CHANNELCTRL_CSC_PRIORITY__HIGH           0x3
-#define BV_DCP_CHANNELCTRL_CSC_PRIORITY__MED            0x2
-#define BV_DCP_CHANNELCTRL_CSC_PRIORITY__LOW            0x1
-#define BV_DCP_CHANNELCTRL_CSC_PRIORITY__BACKGROUND     0x0
-#define BF_DCP_CHANNELCTRL_CSC_PRIORITY(v)              (((v) << 17) & 0x60000)
-#define BF_DCP_CHANNELCTRL_CSC_PRIORITY_V(v)            ((BV_DCP_CHANNELCTRL_CSC_PRIORITY__##v << 17) & 0x60000)
-#define BP_DCP_CHANNELCTRL_CH0_IRQ_MERGED               16
-#define BM_DCP_CHANNELCTRL_CH0_IRQ_MERGED               0x10000
-#define BF_DCP_CHANNELCTRL_CH0_IRQ_MERGED(v)            (((v) << 16) & 0x10000)
-#define BP_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL        8
-#define BM_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL        0xff00
-#define BV_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL__CH0   0x1
-#define BV_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL__CH1   0x2
-#define BV_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL__CH2   0x4
-#define BV_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL__CH3   0x8
-#define BF_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL(v)     (((v) << 8) & 0xff00)
-#define BF_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_V(v)   ((BV_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL__##v << 8) & 0xff00)
-#define BP_DCP_CHANNELCTRL_ENABLE_CHANNEL               0
-#define BM_DCP_CHANNELCTRL_ENABLE_CHANNEL               0xff
-#define BV_DCP_CHANNELCTRL_ENABLE_CHANNEL__CH0          0x1
-#define BV_DCP_CHANNELCTRL_ENABLE_CHANNEL__CH1          0x2
-#define BV_DCP_CHANNELCTRL_ENABLE_CHANNEL__CH2          0x4
-#define BV_DCP_CHANNELCTRL_ENABLE_CHANNEL__CH3          0x8
-#define BF_DCP_CHANNELCTRL_ENABLE_CHANNEL(v)            (((v) << 0) & 0xff)
-#define BF_DCP_CHANNELCTRL_ENABLE_CHANNEL_V(v)          ((BV_DCP_CHANNELCTRL_ENABLE_CHANNEL__##v << 0) & 0xff)
-
-/**
- * Register: HW_DCP_CAPABILITY0
- * Address: 0x30
- * SCT: no
-*/
-#define HW_DCP_CAPABILITY0                  (*(volatile unsigned long *)(REGS_DCP_BASE + 0x30))
-#define BP_DCP_CAPABILITY0_NUM_CHANNELS     8
-#define BM_DCP_CAPABILITY0_NUM_CHANNELS     0xf00
-#define BF_DCP_CAPABILITY0_NUM_CHANNELS(v)  (((v) << 8) & 0xf00)
-#define BP_DCP_CAPABILITY0_NUM_KEYS         0
-#define BM_DCP_CAPABILITY0_NUM_KEYS         0xff
-#define BF_DCP_CAPABILITY0_NUM_KEYS(v)      (((v) << 0) & 0xff)
-
-/**
- * Register: HW_DCP_CAPABILITY1
- * Address: 0x40
- * SCT: no
-*/
-#define HW_DCP_CAPABILITY1                              (*(volatile unsigned long *)(REGS_DCP_BASE + 0x40))
-#define BP_DCP_CAPABILITY1_HASH_ALGORITHMS              16
-#define BM_DCP_CAPABILITY1_HASH_ALGORITHMS              0xffff0000
-#define BV_DCP_CAPABILITY1_HASH_ALGORITHMS__SHA1        0x1
-#define BV_DCP_CAPABILITY1_HASH_ALGORITHMS__CRC32       0x2
-#define BF_DCP_CAPABILITY1_HASH_ALGORITHMS(v)           (((v) << 16) & 0xffff0000)
-#define BF_DCP_CAPABILITY1_HASH_ALGORITHMS_V(v)         ((BV_DCP_CAPABILITY1_HASH_ALGORITHMS__##v << 16) & 0xffff0000)
-#define BP_DCP_CAPABILITY1_CIPHER_ALGORITHMS            0
-#define BM_DCP_CAPABILITY1_CIPHER_ALGORITHMS            0xffff
-#define BV_DCP_CAPABILITY1_CIPHER_ALGORITHMS__AES128    0x1
-#define BF_DCP_CAPABILITY1_CIPHER_ALGORITHMS(v)         (((v) << 0) & 0xffff)
-#define BF_DCP_CAPABILITY1_CIPHER_ALGORITHMS_V(v)       ((BV_DCP_CAPABILITY1_CIPHER_ALGORITHMS__##v << 0) & 0xffff)
-
-/**
- * Register: HW_DCP_CONTEXT
- * Address: 0x50
- * SCT: no
-*/
-#define HW_DCP_CONTEXT          (*(volatile unsigned long *)(REGS_DCP_BASE + 0x50))
-#define BP_DCP_CONTEXT_ADDR     0
-#define BM_DCP_CONTEXT_ADDR     0xffffffff
-#define BF_DCP_CONTEXT_ADDR(v)  (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DCP_KEY
- * Address: 0x60
- * SCT: no
-*/
-#define HW_DCP_KEY              (*(volatile unsigned long *)(REGS_DCP_BASE + 0x60))
-#define BP_DCP_KEY_INDEX        4
-#define BM_DCP_KEY_INDEX        0x30
-#define BF_DCP_KEY_INDEX(v)     (((v) << 4) & 0x30)
-#define BP_DCP_KEY_SUBWORD      0
-#define BM_DCP_KEY_SUBWORD      0x3
-#define BF_DCP_KEY_SUBWORD(v)   (((v) << 0) & 0x3)
-
-/**
- * Register: HW_DCP_KEYDATA
- * Address: 0x70
- * SCT: no
-*/
-#define HW_DCP_KEYDATA          (*(volatile unsigned long *)(REGS_DCP_BASE + 0x70))
-#define BP_DCP_KEYDATA_DATA     0
-#define BM_DCP_KEYDATA_DATA     0xffffffff
-#define BF_DCP_KEYDATA_DATA(v)  (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DCP_PACKET0
- * Address: 0x80
- * SCT: no
-*/
-#define HW_DCP_PACKET0          (*(volatile unsigned long *)(REGS_DCP_BASE + 0x80))
-#define BP_DCP_PACKET0_ADDR     0
-#define BM_DCP_PACKET0_ADDR     0xffffffff
-#define BF_DCP_PACKET0_ADDR(v)  (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DCP_PACKET1
- * Address: 0x90
- * SCT: no
-*/
-#define HW_DCP_PACKET1                          (*(volatile unsigned long *)(REGS_DCP_BASE + 0x90))
-#define BP_DCP_PACKET1_TAG                      24
-#define BM_DCP_PACKET1_TAG                      0xff000000
-#define BF_DCP_PACKET1_TAG(v)                   (((v) << 24) & 0xff000000)
-#define BP_DCP_PACKET1_OUTPUT_WORDSWAP          23
-#define BM_DCP_PACKET1_OUTPUT_WORDSWAP          0x800000
-#define BF_DCP_PACKET1_OUTPUT_WORDSWAP(v)       (((v) << 23) & 0x800000)
-#define BP_DCP_PACKET1_OUTPUT_BYTESWAP          22
-#define BM_DCP_PACKET1_OUTPUT_BYTESWAP          0x400000
-#define BF_DCP_PACKET1_OUTPUT_BYTESWAP(v)       (((v) << 22) & 0x400000)
-#define BP_DCP_PACKET1_INPUT_WORDSWAP           21
-#define BM_DCP_PACKET1_INPUT_WORDSWAP           0x200000
-#define BF_DCP_PACKET1_INPUT_WORDSWAP(v)        (((v) << 21) & 0x200000)
-#define BP_DCP_PACKET1_INPUT_BYTESWAP           20
-#define BM_DCP_PACKET1_INPUT_BYTESWAP           0x100000
-#define BF_DCP_PACKET1_INPUT_BYTESWAP(v)        (((v) << 20) & 0x100000)
-#define BP_DCP_PACKET1_KEY_WORDSWAP             19
-#define BM_DCP_PACKET1_KEY_WORDSWAP             0x80000
-#define BF_DCP_PACKET1_KEY_WORDSWAP(v)          (((v) << 19) & 0x80000)
-#define BP_DCP_PACKET1_KEY_BYTESWAP             18
-#define BM_DCP_PACKET1_KEY_BYTESWAP             0x40000
-#define BF_DCP_PACKET1_KEY_BYTESWAP(v)          (((v) << 18) & 0x40000)
-#define BP_DCP_PACKET1_TEST_SEMA_IRQ            17
-#define BM_DCP_PACKET1_TEST_SEMA_IRQ            0x20000
-#define BF_DCP_PACKET1_TEST_SEMA_IRQ(v)         (((v) << 17) & 0x20000)
-#define BP_DCP_PACKET1_CONSTANT_FILL            16
-#define BM_DCP_PACKET1_CONSTANT_FILL            0x10000
-#define BF_DCP_PACKET1_CONSTANT_FILL(v)         (((v) << 16) & 0x10000)
-#define BP_DCP_PACKET1_HASH_OUTPUT              15
-#define BM_DCP_PACKET1_HASH_OUTPUT              0x8000
-#define BV_DCP_PACKET1_HASH_OUTPUT__INPUT       0x0
-#define BV_DCP_PACKET1_HASH_OUTPUT__OUTPUT      0x1
-#define BF_DCP_PACKET1_HASH_OUTPUT(v)           (((v) << 15) & 0x8000)
-#define BF_DCP_PACKET1_HASH_OUTPUT_V(v)         ((BV_DCP_PACKET1_HASH_OUTPUT__##v << 15) & 0x8000)
-#define BP_DCP_PACKET1_CHECK_HASH               14
-#define BM_DCP_PACKET1_CHECK_HASH               0x4000
-#define BF_DCP_PACKET1_CHECK_HASH(v)            (((v) << 14) & 0x4000)
-#define BP_DCP_PACKET1_HASH_TERM                13
-#define BM_DCP_PACKET1_HASH_TERM                0x2000
-#define BF_DCP_PACKET1_HASH_TERM(v)             (((v) << 13) & 0x2000)
-#define BP_DCP_PACKET1_HASH_INIT                12
-#define BM_DCP_PACKET1_HASH_INIT                0x1000
-#define BF_DCP_PACKET1_HASH_INIT(v)             (((v) << 12) & 0x1000)
-#define BP_DCP_PACKET1_PAYLOAD_KEY              11
-#define BM_DCP_PACKET1_PAYLOAD_KEY              0x800
-#define BF_DCP_PACKET1_PAYLOAD_KEY(v)           (((v) << 11) & 0x800)
-#define BP_DCP_PACKET1_OTP_KEY                  10
-#define BM_DCP_PACKET1_OTP_KEY                  0x400
-#define BF_DCP_PACKET1_OTP_KEY(v)               (((v) << 10) & 0x400)
-#define BP_DCP_PACKET1_CIPHER_INIT              9
-#define BM_DCP_PACKET1_CIPHER_INIT              0x200
-#define BF_DCP_PACKET1_CIPHER_INIT(v)           (((v) << 9) & 0x200)
-#define BP_DCP_PACKET1_CIPHER_ENCRYPT           8
-#define BM_DCP_PACKET1_CIPHER_ENCRYPT           0x100
-#define BV_DCP_PACKET1_CIPHER_ENCRYPT__ENCRYPT  0x1
-#define BV_DCP_PACKET1_CIPHER_ENCRYPT__DECRYPT  0x0
-#define BF_DCP_PACKET1_CIPHER_ENCRYPT(v)        (((v) << 8) & 0x100)
-#define BF_DCP_PACKET1_CIPHER_ENCRYPT_V(v)      ((BV_DCP_PACKET1_CIPHER_ENCRYPT__##v << 8) & 0x100)
-#define BP_DCP_PACKET1_ENABLE_BLIT              7
-#define BM_DCP_PACKET1_ENABLE_BLIT              0x80
-#define BF_DCP_PACKET1_ENABLE_BLIT(v)           (((v) << 7) & 0x80)
-#define BP_DCP_PACKET1_ENABLE_HASH              6
-#define BM_DCP_PACKET1_ENABLE_HASH              0x40
-#define BF_DCP_PACKET1_ENABLE_HASH(v)           (((v) << 6) & 0x40)
-#define BP_DCP_PACKET1_ENABLE_CIPHER            5
-#define BM_DCP_PACKET1_ENABLE_CIPHER            0x20
-#define BF_DCP_PACKET1_ENABLE_CIPHER(v)         (((v) << 5) & 0x20)
-#define BP_DCP_PACKET1_ENABLE_MEMCOPY           4
-#define BM_DCP_PACKET1_ENABLE_MEMCOPY           0x10
-#define BF_DCP_PACKET1_ENABLE_MEMCOPY(v)        (((v) << 4) & 0x10)
-#define BP_DCP_PACKET1_CHAIN_CONTIGUOUS         3
-#define BM_DCP_PACKET1_CHAIN_CONTIGUOUS         0x8
-#define BF_DCP_PACKET1_CHAIN_CONTIGUOUS(v)      (((v) << 3) & 0x8)
-#define BP_DCP_PACKET1_CHAIN                    2
-#define BM_DCP_PACKET1_CHAIN                    0x4
-#define BF_DCP_PACKET1_CHAIN(v)                 (((v) << 2) & 0x4)
-#define BP_DCP_PACKET1_DECR_SEMAPHORE           1
-#define BM_DCP_PACKET1_DECR_SEMAPHORE           0x2
-#define BF_DCP_PACKET1_DECR_SEMAPHORE(v)        (((v) << 1) & 0x2)
-#define BP_DCP_PACKET1_INTERRUPT                0
-#define BM_DCP_PACKET1_INTERRUPT                0x1
-#define BF_DCP_PACKET1_INTERRUPT(v)             (((v) << 0) & 0x1)
-
-/**
- * Register: HW_DCP_PACKET2
- * Address: 0xa0
- * SCT: no
-*/
-#define HW_DCP_PACKET2                          (*(volatile unsigned long *)(REGS_DCP_BASE + 0xa0))
-#define BP_DCP_PACKET2_CIPHER_CFG               24
-#define BM_DCP_PACKET2_CIPHER_CFG               0xff000000
-#define BF_DCP_PACKET2_CIPHER_CFG(v)            (((v) << 24) & 0xff000000)
-#define BP_DCP_PACKET2_HASH_SELECT              16
-#define BM_DCP_PACKET2_HASH_SELECT              0xf0000
-#define BV_DCP_PACKET2_HASH_SELECT__SHA1        0x0
-#define BV_DCP_PACKET2_HASH_SELECT__CRC32       0x1
-#define BF_DCP_PACKET2_HASH_SELECT(v)           (((v) << 16) & 0xf0000)
-#define BF_DCP_PACKET2_HASH_SELECT_V(v)         ((BV_DCP_PACKET2_HASH_SELECT__##v << 16) & 0xf0000)
-#define BP_DCP_PACKET2_KEY_SELECT               8
-#define BM_DCP_PACKET2_KEY_SELECT               0xff00
-#define BF_DCP_PACKET2_KEY_SELECT(v)            (((v) << 8) & 0xff00)
-#define BP_DCP_PACKET2_CIPHER_MODE              4
-#define BM_DCP_PACKET2_CIPHER_MODE              0xf0
-#define BV_DCP_PACKET2_CIPHER_MODE__ECB         0x0
-#define BV_DCP_PACKET2_CIPHER_MODE__CCB         0x1
-#define BF_DCP_PACKET2_CIPHER_MODE(v)           (((v) << 4) & 0xf0)
-#define BF_DCP_PACKET2_CIPHER_MODE_V(v)         ((BV_DCP_PACKET2_CIPHER_MODE__##v << 4) & 0xf0)
-#define BP_DCP_PACKET2_CIPHER_SELECT            0
-#define BM_DCP_PACKET2_CIPHER_SELECT            0xf
-#define BV_DCP_PACKET2_CIPHER_SELECT__AES128    0x0
-#define BF_DCP_PACKET2_CIPHER_SELECT(v)         (((v) << 0) & 0xf)
-#define BF_DCP_PACKET2_CIPHER_SELECT_V(v)       ((BV_DCP_PACKET2_CIPHER_SELECT__##v << 0) & 0xf)
-
-/**
- * Register: HW_DCP_PACKET3
- * Address: 0xb0
- * SCT: no
-*/
-#define HW_DCP_PACKET3          (*(volatile unsigned long *)(REGS_DCP_BASE + 0xb0))
-#define BP_DCP_PACKET3_ADDR     0
-#define BM_DCP_PACKET3_ADDR     0xffffffff
-#define BF_DCP_PACKET3_ADDR(v)  (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DCP_PACKET4
- * Address: 0xc0
- * SCT: no
-*/
-#define HW_DCP_PACKET4          (*(volatile unsigned long *)(REGS_DCP_BASE + 0xc0))
-#define BP_DCP_PACKET4_ADDR     0
-#define BM_DCP_PACKET4_ADDR     0xffffffff
-#define BF_DCP_PACKET4_ADDR(v)  (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DCP_PACKET5
- * Address: 0xd0
- * SCT: no
-*/
-#define HW_DCP_PACKET5          (*(volatile unsigned long *)(REGS_DCP_BASE + 0xd0))
-#define BP_DCP_PACKET5_COUNT    0
-#define BM_DCP_PACKET5_COUNT    0xffffffff
-#define BF_DCP_PACKET5_COUNT(v) (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DCP_PACKET6
- * Address: 0xe0
- * SCT: no
-*/
-#define HW_DCP_PACKET6          (*(volatile unsigned long *)(REGS_DCP_BASE + 0xe0))
-#define BP_DCP_PACKET6_ADDR     0
-#define BM_DCP_PACKET6_ADDR     0xffffffff
-#define BF_DCP_PACKET6_ADDR(v)  (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DCP_CHnCMDPTR
- * Address: 0x100+n*0x40
- * SCT: no
-*/
-#define HW_DCP_CHnCMDPTR(n)         (*(volatile unsigned long *)(REGS_DCP_BASE + 0x100+(n)*0x40))
-#define BP_DCP_CHnCMDPTR_ADDR       0
-#define BM_DCP_CHnCMDPTR_ADDR       0xffffffff
-#define BF_DCP_CHnCMDPTR_ADDR(v)    (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DCP_CHnSEMA
- * Address: 0x110+n*0x40
- * SCT: no
-*/
-#define HW_DCP_CHnSEMA(n)           (*(volatile unsigned long *)(REGS_DCP_BASE + 0x110+(n)*0x40))
-#define BP_DCP_CHnSEMA_VALUE        16
-#define BM_DCP_CHnSEMA_VALUE        0xff0000
-#define BF_DCP_CHnSEMA_VALUE(v)     (((v) << 16) & 0xff0000)
-#define BP_DCP_CHnSEMA_INCREMENT    0
-#define BM_DCP_CHnSEMA_INCREMENT    0xff
-#define BF_DCP_CHnSEMA_INCREMENT(v) (((v) << 0) & 0xff)
-
-/**
- * Register: HW_DCP_CHnSTAT
- * Address: 0x120+n*0x40
- * SCT: yes
-*/
-#define HW_DCP_CHnSTAT(n)                           (*(volatile unsigned long *)(REGS_DCP_BASE + 0x120+(n)*0x40 + 0x0))
-#define HW_DCP_CHnSTAT_SET(n)                       (*(volatile unsigned long *)(REGS_DCP_BASE + 0x120+(n)*0x40 + 0x4))
-#define HW_DCP_CHnSTAT_CLR(n)                       (*(volatile unsigned long *)(REGS_DCP_BASE + 0x120+(n)*0x40 + 0x8))
-#define HW_DCP_CHnSTAT_TOG(n)                       (*(volatile unsigned long *)(REGS_DCP_BASE + 0x120+(n)*0x40 + 0xc))
-#define BP_DCP_CHnSTAT_TAG                          24
-#define BM_DCP_CHnSTAT_TAG                          0xff000000
-#define BF_DCP_CHnSTAT_TAG(v)                       (((v) << 24) & 0xff000000)
-#define BP_DCP_CHnSTAT_ERROR_CODE                   16
-#define BM_DCP_CHnSTAT_ERROR_CODE                   0xff0000
-#define BV_DCP_CHnSTAT_ERROR_CODE__NEXT_CHAIN_IS_0  0x1
-#define BV_DCP_CHnSTAT_ERROR_CODE__NO_CHAIN         0x2
-#define BV_DCP_CHnSTAT_ERROR_CODE__CONTEXT_ERROR    0x3
-#define BV_DCP_CHnSTAT_ERROR_CODE__PAYLOAD_ERROR    0x4
-#define BV_DCP_CHnSTAT_ERROR_CODE__INVALID_MODE     0x5
-#define BF_DCP_CHnSTAT_ERROR_CODE(v)                (((v) << 16) & 0xff0000)
-#define BF_DCP_CHnSTAT_ERROR_CODE_V(v)              ((BV_DCP_CHnSTAT_ERROR_CODE__##v << 16) & 0xff0000)
-#define BP_DCP_CHnSTAT_ERROR_DST                    5
-#define BM_DCP_CHnSTAT_ERROR_DST                    0x20
-#define BF_DCP_CHnSTAT_ERROR_DST(v)                 (((v) << 5) & 0x20)
-#define BP_DCP_CHnSTAT_ERROR_SRC                    4
-#define BM_DCP_CHnSTAT_ERROR_SRC                    0x10
-#define BF_DCP_CHnSTAT_ERROR_SRC(v)                 (((v) << 4) & 0x10)
-#define BP_DCP_CHnSTAT_ERROR_PACKET                 3
-#define BM_DCP_CHnSTAT_ERROR_PACKET                 0x8
-#define BF_DCP_CHnSTAT_ERROR_PACKET(v)              (((v) << 3) & 0x8)
-#define BP_DCP_CHnSTAT_ERROR_SETUP                  2
-#define BM_DCP_CHnSTAT_ERROR_SETUP                  0x4
-#define BF_DCP_CHnSTAT_ERROR_SETUP(v)               (((v) << 2) & 0x4)
-#define BP_DCP_CHnSTAT_HASH_MISMATCH                1
-#define BM_DCP_CHnSTAT_HASH_MISMATCH                0x2
-#define BF_DCP_CHnSTAT_HASH_MISMATCH(v)             (((v) << 1) & 0x2)
-
-/**
- * Register: HW_DCP_CHnOPTS
- * Address: 0x130+n*0x40
- * SCT: yes
-*/
-#define HW_DCP_CHnOPTS(n)                   (*(volatile unsigned long *)(REGS_DCP_BASE + 0x130+(n)*0x40 + 0x0))
-#define HW_DCP_CHnOPTS_SET(n)               (*(volatile unsigned long *)(REGS_DCP_BASE + 0x130+(n)*0x40 + 0x4))
-#define HW_DCP_CHnOPTS_CLR(n)               (*(volatile unsigned long *)(REGS_DCP_BASE + 0x130+(n)*0x40 + 0x8))
-#define HW_DCP_CHnOPTS_TOG(n)               (*(volatile unsigned long *)(REGS_DCP_BASE + 0x130+(n)*0x40 + 0xc))
-#define BP_DCP_CHnOPTS_RECOVERY_TIMER       0
-#define BM_DCP_CHnOPTS_RECOVERY_TIMER       0xffff
-#define BF_DCP_CHnOPTS_RECOVERY_TIMER(v)    (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_DCP_CSCCTRL0
- * Address: 0x300
- * SCT: yes
-*/
-#define HW_DCP_CSCCTRL0                         (*(volatile unsigned long *)(REGS_DCP_BASE + 0x300 + 0x0))
-#define HW_DCP_CSCCTRL0_SET                     (*(volatile unsigned long *)(REGS_DCP_BASE + 0x300 + 0x4))
-#define HW_DCP_CSCCTRL0_CLR                     (*(volatile unsigned long *)(REGS_DCP_BASE + 0x300 + 0x8))
-#define HW_DCP_CSCCTRL0_TOG                     (*(volatile unsigned long *)(REGS_DCP_BASE + 0x300 + 0xc))
-#define BP_DCP_CSCCTRL0_UPSAMPLE                14
-#define BM_DCP_CSCCTRL0_UPSAMPLE                0x4000
-#define BF_DCP_CSCCTRL0_UPSAMPLE(v)             (((v) << 14) & 0x4000)
-#define BP_DCP_CSCCTRL0_SCALE                   13
-#define BM_DCP_CSCCTRL0_SCALE                   0x2000
-#define BF_DCP_CSCCTRL0_SCALE(v)                (((v) << 13) & 0x2000)
-#define BP_DCP_CSCCTRL0_ROTATE                  12
-#define BM_DCP_CSCCTRL0_ROTATE                  0x1000
-#define BF_DCP_CSCCTRL0_ROTATE(v)               (((v) << 12) & 0x1000)
-#define BP_DCP_CSCCTRL0_SUBSAMPLE               11
-#define BM_DCP_CSCCTRL0_SUBSAMPLE               0x800
-#define BF_DCP_CSCCTRL0_SUBSAMPLE(v)            (((v) << 11) & 0x800)
-#define BP_DCP_CSCCTRL0_DELTA                   10
-#define BM_DCP_CSCCTRL0_DELTA                   0x400
-#define BF_DCP_CSCCTRL0_DELTA(v)                (((v) << 10) & 0x400)
-#define BP_DCP_CSCCTRL0_RGB_FORMAT              8
-#define BM_DCP_CSCCTRL0_RGB_FORMAT              0x300
-#define BV_DCP_CSCCTRL0_RGB_FORMAT__RGB16_565   0x0
-#define BV_DCP_CSCCTRL0_RGB_FORMAT__RGB24       0x2
-#define BV_DCP_CSCCTRL0_RGB_FORMAT__YUV422I     0x3
-#define BF_DCP_CSCCTRL0_RGB_FORMAT(v)           (((v) << 8) & 0x300)
-#define BF_DCP_CSCCTRL0_RGB_FORMAT_V(v)         ((BV_DCP_CSCCTRL0_RGB_FORMAT__##v << 8) & 0x300)
-#define BP_DCP_CSCCTRL0_YUV_FORMAT              4
-#define BM_DCP_CSCCTRL0_YUV_FORMAT              0xf0
-#define BV_DCP_CSCCTRL0_YUV_FORMAT__YUV420      0x0
-#define BV_DCP_CSCCTRL0_YUV_FORMAT__YUV422      0x2
-#define BF_DCP_CSCCTRL0_YUV_FORMAT(v)           (((v) << 4) & 0xf0)
-#define BF_DCP_CSCCTRL0_YUV_FORMAT_V(v)         ((BV_DCP_CSCCTRL0_YUV_FORMAT__##v << 4) & 0xf0)
-#define BP_DCP_CSCCTRL0_ENABLE                  0
-#define BM_DCP_CSCCTRL0_ENABLE                  0x1
-#define BF_DCP_CSCCTRL0_ENABLE(v)               (((v) << 0) & 0x1)
-
-/**
- * Register: HW_DCP_CSCSTAT
- * Address: 0x310
- * SCT: yes
-*/
-#define HW_DCP_CSCSTAT                                  (*(volatile unsigned long *)(REGS_DCP_BASE + 0x310 + 0x0))
-#define HW_DCP_CSCSTAT_SET                              (*(volatile unsigned long *)(REGS_DCP_BASE + 0x310 + 0x4))
-#define HW_DCP_CSCSTAT_CLR                              (*(volatile unsigned long *)(REGS_DCP_BASE + 0x310 + 0x8))
-#define HW_DCP_CSCSTAT_TOG                              (*(volatile unsigned long *)(REGS_DCP_BASE + 0x310 + 0xc))
-#define BP_DCP_CSCSTAT_ERROR_CODE                       16
-#define BM_DCP_CSCSTAT_ERROR_CODE                       0xff0000
-#define BV_DCP_CSCSTAT_ERROR_CODE__LUMA0_FETCH_ERROR_Y0 0x1
-#define BV_DCP_CSCSTAT_ERROR_CODE__LUMA1_FETCH_ERROR_Y1 0x2
-#define BV_DCP_CSCSTAT_ERROR_CODE__CHROMA_FETCH_ERROR_U 0x3
-#define BV_DCP_CSCSTAT_ERROR_CODE__CHROMA_FETCH_ERROR_V 0x4
-#define BF_DCP_CSCSTAT_ERROR_CODE(v)                    (((v) << 16) & 0xff0000)
-#define BF_DCP_CSCSTAT_ERROR_CODE_V(v)                  ((BV_DCP_CSCSTAT_ERROR_CODE__##v << 16) & 0xff0000)
-#define BP_DCP_CSCSTAT_ERROR_DST                        5
-#define BM_DCP_CSCSTAT_ERROR_DST                        0x20
-#define BF_DCP_CSCSTAT_ERROR_DST(v)                     (((v) << 5) & 0x20)
-#define BP_DCP_CSCSTAT_ERROR_SRC                        4
-#define BM_DCP_CSCSTAT_ERROR_SRC                        0x10
-#define BF_DCP_CSCSTAT_ERROR_SRC(v)                     (((v) << 4) & 0x10)
-#define BP_DCP_CSCSTAT_ERROR_SETUP                      2
-#define BM_DCP_CSCSTAT_ERROR_SETUP                      0x4
-#define BF_DCP_CSCSTAT_ERROR_SETUP(v)                   (((v) << 2) & 0x4)
-#define BP_DCP_CSCSTAT_COMPLETE                         0
-#define BM_DCP_CSCSTAT_COMPLETE                         0x1
-#define BF_DCP_CSCSTAT_COMPLETE(v)                      (((v) << 0) & 0x1)
-
-/**
- * Register: HW_DCP_CSCOUTBUFPARAM
- * Address: 0x320
- * SCT: no
-*/
-#define HW_DCP_CSCOUTBUFPARAM               (*(volatile unsigned long *)(REGS_DCP_BASE + 0x320))
-#define BP_DCP_CSCOUTBUFPARAM_FIELD_SIZE    12
-#define BM_DCP_CSCOUTBUFPARAM_FIELD_SIZE    0xfff000
-#define BF_DCP_CSCOUTBUFPARAM_FIELD_SIZE(v) (((v) << 12) & 0xfff000)
-#define BP_DCP_CSCOUTBUFPARAM_LINE_SIZE     0
-#define BM_DCP_CSCOUTBUFPARAM_LINE_SIZE     0xfff
-#define BF_DCP_CSCOUTBUFPARAM_LINE_SIZE(v)  (((v) << 0) & 0xfff)
-
-/**
- * Register: HW_DCP_CSCINBUFPARAM
- * Address: 0x330
- * SCT: no
-*/
-#define HW_DCP_CSCINBUFPARAM                (*(volatile unsigned long *)(REGS_DCP_BASE + 0x330))
-#define BP_DCP_CSCINBUFPARAM_LINE_SIZE      0
-#define BM_DCP_CSCINBUFPARAM_LINE_SIZE      0xfff
-#define BF_DCP_CSCINBUFPARAM_LINE_SIZE(v)   (((v) << 0) & 0xfff)
-
-/**
- * Register: HW_DCP_CSCRGB
- * Address: 0x340
- * SCT: no
-*/
-#define HW_DCP_CSCRGB           (*(volatile unsigned long *)(REGS_DCP_BASE + 0x340))
-#define BP_DCP_CSCRGB_ADDR      0
-#define BM_DCP_CSCRGB_ADDR      0xffffffff
-#define BF_DCP_CSCRGB_ADDR(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DCP_CSCLUMA
- * Address: 0x350
- * SCT: no
-*/
-#define HW_DCP_CSCLUMA          (*(volatile unsigned long *)(REGS_DCP_BASE + 0x350))
-#define BP_DCP_CSCLUMA_ADDR     0
-#define BM_DCP_CSCLUMA_ADDR     0xffffffff
-#define BF_DCP_CSCLUMA_ADDR(v)  (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DCP_CSCCHROMAU
- * Address: 0x360
- * SCT: no
-*/
-#define HW_DCP_CSCCHROMAU           (*(volatile unsigned long *)(REGS_DCP_BASE + 0x360))
-#define BP_DCP_CSCCHROMAU_ADDR      0
-#define BM_DCP_CSCCHROMAU_ADDR      0xffffffff
-#define BF_DCP_CSCCHROMAU_ADDR(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DCP_CSCCHROMAV
- * Address: 0x370
- * SCT: no
-*/
-#define HW_DCP_CSCCHROMAV           (*(volatile unsigned long *)(REGS_DCP_BASE + 0x370))
-#define BP_DCP_CSCCHROMAV_ADDR      0
-#define BM_DCP_CSCCHROMAV_ADDR      0xffffffff
-#define BF_DCP_CSCCHROMAV_ADDR(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DCP_CSCCOEFF0
- * Address: 0x380
- * SCT: no
-*/
-#define HW_DCP_CSCCOEFF0                (*(volatile unsigned long *)(REGS_DCP_BASE + 0x380))
-#define BP_DCP_CSCCOEFF0_C0             16
-#define BM_DCP_CSCCOEFF0_C0             0x3ff0000
-#define BF_DCP_CSCCOEFF0_C0(v)          (((v) << 16) & 0x3ff0000)
-#define BP_DCP_CSCCOEFF0_UV_OFFSET      8
-#define BM_DCP_CSCCOEFF0_UV_OFFSET      0xff00
-#define BF_DCP_CSCCOEFF0_UV_OFFSET(v)   (((v) << 8) & 0xff00)
-#define BP_DCP_CSCCOEFF0_Y_OFFSET       0
-#define BM_DCP_CSCCOEFF0_Y_OFFSET       0xff
-#define BF_DCP_CSCCOEFF0_Y_OFFSET(v)    (((v) << 0) & 0xff)
-
-/**
- * Register: HW_DCP_CSCCOEFF1
- * Address: 0x390
- * SCT: no
-*/
-#define HW_DCP_CSCCOEFF1        (*(volatile unsigned long *)(REGS_DCP_BASE + 0x390))
-#define BP_DCP_CSCCOEFF1_C1     16
-#define BM_DCP_CSCCOEFF1_C1     0x3ff0000
-#define BF_DCP_CSCCOEFF1_C1(v)  (((v) << 16) & 0x3ff0000)
-#define BP_DCP_CSCCOEFF1_C4     0
-#define BM_DCP_CSCCOEFF1_C4     0x3ff
-#define BF_DCP_CSCCOEFF1_C4(v)  (((v) << 0) & 0x3ff)
-
-/**
- * Register: HW_DCP_CSCCOEFF2
- * Address: 0x3a0
- * SCT: no
-*/
-#define HW_DCP_CSCCOEFF2        (*(volatile unsigned long *)(REGS_DCP_BASE + 0x3a0))
-#define BP_DCP_CSCCOEFF2_C2     16
-#define BM_DCP_CSCCOEFF2_C2     0x3ff0000
-#define BF_DCP_CSCCOEFF2_C2(v)  (((v) << 16) & 0x3ff0000)
-#define BP_DCP_CSCCOEFF2_C3     0
-#define BM_DCP_CSCCOEFF2_C3     0x3ff
-#define BF_DCP_CSCCOEFF2_C3(v)  (((v) << 0) & 0x3ff)
-
-/**
- * Register: HW_DCP_CSCXSCALE
- * Address: 0x3e0
- * SCT: no
-*/
-#define HW_DCP_CSCXSCALE            (*(volatile unsigned long *)(REGS_DCP_BASE + 0x3e0))
-#define BP_DCP_CSCXSCALE_INT        24
-#define BM_DCP_CSCXSCALE_INT        0x3000000
-#define BF_DCP_CSCXSCALE_INT(v)     (((v) << 24) & 0x3000000)
-#define BP_DCP_CSCXSCALE_FRAC       12
-#define BM_DCP_CSCXSCALE_FRAC       0xfff000
-#define BF_DCP_CSCXSCALE_FRAC(v)    (((v) << 12) & 0xfff000)
-#define BP_DCP_CSCXSCALE_WIDTH      0
-#define BM_DCP_CSCXSCALE_WIDTH      0xfff
-#define BF_DCP_CSCXSCALE_WIDTH(v)   (((v) << 0) & 0xfff)
-
-/**
- * Register: HW_DCP_CSCYSCALE
- * Address: 0x3f0
- * SCT: no
-*/
-#define HW_DCP_CSCYSCALE            (*(volatile unsigned long *)(REGS_DCP_BASE + 0x3f0))
-#define BP_DCP_CSCYSCALE_INT        24
-#define BM_DCP_CSCYSCALE_INT        0x3000000
-#define BF_DCP_CSCYSCALE_INT(v)     (((v) << 24) & 0x3000000)
-#define BP_DCP_CSCYSCALE_FRAC       12
-#define BM_DCP_CSCYSCALE_FRAC       0xfff000
-#define BF_DCP_CSCYSCALE_FRAC(v)    (((v) << 12) & 0xfff000)
-#define BP_DCP_CSCYSCALE_HEIGHT     0
-#define BM_DCP_CSCYSCALE_HEIGHT     0xfff
-#define BF_DCP_CSCYSCALE_HEIGHT(v)  (((v) << 0) & 0xfff)
-
-/**
- * Register: HW_DCP_DBGSELECT
- * Address: 0x400
- * SCT: no
-*/
-#define HW_DCP_DBGSELECT                (*(volatile unsigned long *)(REGS_DCP_BASE + 0x400))
-#define BP_DCP_DBGSELECT_INDEX          0
-#define BM_DCP_DBGSELECT_INDEX          0xff
-#define BV_DCP_DBGSELECT_INDEX__CONTROL 0x1
-#define BV_DCP_DBGSELECT_INDEX__OTPKEY0 0x10
-#define BV_DCP_DBGSELECT_INDEX__OTPKEY1 0x11
-#define BV_DCP_DBGSELECT_INDEX__OTPKEY2 0x12
-#define BV_DCP_DBGSELECT_INDEX__OTPKEY3 0x13
-#define BF_DCP_DBGSELECT_INDEX(v)       (((v) << 0) & 0xff)
-#define BF_DCP_DBGSELECT_INDEX_V(v)     ((BV_DCP_DBGSELECT_INDEX__##v << 0) & 0xff)
-
-/**
- * Register: HW_DCP_DBGDATA
- * Address: 0x410
- * SCT: no
-*/
-#define HW_DCP_DBGDATA          (*(volatile unsigned long *)(REGS_DCP_BASE + 0x410))
-#define BP_DCP_DBGDATA_DATA     0
-#define BM_DCP_DBGDATA_DATA     0xffffffff
-#define BF_DCP_DBGDATA_DATA(v)  (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DCP_VERSION
- * Address: 0x420
- * SCT: no
-*/
-#define HW_DCP_VERSION          (*(volatile unsigned long *)(REGS_DCP_BASE + 0x420))
-#define BP_DCP_VERSION_MAJOR    24
-#define BM_DCP_VERSION_MAJOR    0xff000000
-#define BF_DCP_VERSION_MAJOR(v) (((v) << 24) & 0xff000000)
-#define BP_DCP_VERSION_MINOR    16
-#define BM_DCP_VERSION_MINOR    0xff0000
-#define BF_DCP_VERSION_MINOR(v) (((v) << 16) & 0xff0000)
-#define BP_DCP_VERSION_STEP     0
-#define BM_DCP_VERSION_STEP     0xffff
-#define BF_DCP_VERSION_STEP(v)  (((v) << 0) & 0xffff)
-
-#endif /* __HEADERGEN__STMP3700__DCP__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-digctl.h b/firmware/target/arm/imx233/regs/stmp3700/regs-digctl.h
deleted file mode 100644
index b298663947..0000000000
--- a/firmware/target/arm/imx233/regs/stmp3700/regs-digctl.h
+++ /dev/null
@@ -1,759 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3700:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__STMP3700__DIGCTL__H__
-#define __HEADERGEN__STMP3700__DIGCTL__H__
-
-#define REGS_DIGCTL_BASE (0x8001c000)
-
-#define REGS_DIGCTL_VERSION "3.2.0"
-
-/**
- * Register: HW_DIGCTL_CTRL
- * Address: 0
- * SCT: yes
-*/
-#define HW_DIGCTL_CTRL                                      (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x0 + 0x0))
-#define HW_DIGCTL_CTRL_SET                                  (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x0 + 0x4))
-#define HW_DIGCTL_CTRL_CLR                                  (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x0 + 0x8))
-#define HW_DIGCTL_CTRL_TOG                                  (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x0 + 0xc))
-#define BP_DIGCTL_CTRL_TRAP_IRQ                             29
-#define BM_DIGCTL_CTRL_TRAP_IRQ                             0x20000000
-#define BF_DIGCTL_CTRL_TRAP_IRQ(v)                          (((v) << 29) & 0x20000000)
-#define BP_DIGCTL_CTRL_DCP_BIST_CLKEN                       23
-#define BM_DIGCTL_CTRL_DCP_BIST_CLKEN                       0x800000
-#define BF_DIGCTL_CTRL_DCP_BIST_CLKEN(v)                    (((v) << 23) & 0x800000)
-#define BP_DIGCTL_CTRL_DCP_BIST_START                       22
-#define BM_DIGCTL_CTRL_DCP_BIST_START                       0x400000
-#define BF_DIGCTL_CTRL_DCP_BIST_START(v)                    (((v) << 22) & 0x400000)
-#define BP_DIGCTL_CTRL_ARM_BIST_CLKEN                       21
-#define BM_DIGCTL_CTRL_ARM_BIST_CLKEN                       0x200000
-#define BF_DIGCTL_CTRL_ARM_BIST_CLKEN(v)                    (((v) << 21) & 0x200000)
-#define BP_DIGCTL_CTRL_USB_TESTMODE                         20
-#define BM_DIGCTL_CTRL_USB_TESTMODE                         0x100000
-#define BF_DIGCTL_CTRL_USB_TESTMODE(v)                      (((v) << 20) & 0x100000)
-#define BP_DIGCTL_CTRL_ANALOG_TESTMODE                      19
-#define BM_DIGCTL_CTRL_ANALOG_TESTMODE                      0x80000
-#define BF_DIGCTL_CTRL_ANALOG_TESTMODE(v)                   (((v) << 19) & 0x80000)
-#define BP_DIGCTL_CTRL_DIGITAL_TESTMODE                     18
-#define BM_DIGCTL_CTRL_DIGITAL_TESTMODE                     0x40000
-#define BF_DIGCTL_CTRL_DIGITAL_TESTMODE(v)                  (((v) << 18) & 0x40000)
-#define BP_DIGCTL_CTRL_ARM_BIST_START                       17
-#define BM_DIGCTL_CTRL_ARM_BIST_START                       0x20000
-#define BF_DIGCTL_CTRL_ARM_BIST_START(v)                    (((v) << 17) & 0x20000)
-#define BP_DIGCTL_CTRL_UART_LOOPBACK                        16
-#define BM_DIGCTL_CTRL_UART_LOOPBACK                        0x10000
-#define BV_DIGCTL_CTRL_UART_LOOPBACK__NORMAL                0x0
-#define BV_DIGCTL_CTRL_UART_LOOPBACK__LOOPIT                0x1
-#define BF_DIGCTL_CTRL_UART_LOOPBACK(v)                     (((v) << 16) & 0x10000)
-#define BF_DIGCTL_CTRL_UART_LOOPBACK_V(v)                   ((BV_DIGCTL_CTRL_UART_LOOPBACK__##v << 16) & 0x10000)
-#define BP_DIGCTL_CTRL_SAIF_LOOPBACK                        15
-#define BM_DIGCTL_CTRL_SAIF_LOOPBACK                        0x8000
-#define BV_DIGCTL_CTRL_SAIF_LOOPBACK__NORMAL                0x0
-#define BV_DIGCTL_CTRL_SAIF_LOOPBACK__LOOPIT                0x1
-#define BF_DIGCTL_CTRL_SAIF_LOOPBACK(v)                     (((v) << 15) & 0x8000)
-#define BF_DIGCTL_CTRL_SAIF_LOOPBACK_V(v)                   ((BV_DIGCTL_CTRL_SAIF_LOOPBACK__##v << 15) & 0x8000)
-#define BP_DIGCTL_CTRL_SAIF_CLKMUX_SEL                      13
-#define BM_DIGCTL_CTRL_SAIF_CLKMUX_SEL                      0x6000
-#define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__MBL_CLK_OUT         0x0
-#define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__BL_CLK_OUT          0x1
-#define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__M_CLK_OUT_BL_CLK_IN 0x2
-#define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__BL_CLK_IN           0x3
-#define BF_DIGCTL_CTRL_SAIF_CLKMUX_SEL(v)                   (((v) << 13) & 0x6000)
-#define BF_DIGCTL_CTRL_SAIF_CLKMUX_SEL_V(v)                 ((BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__##v << 13) & 0x6000)
-#define BP_DIGCTL_CTRL_SAIF_CLKMST_SEL                      12
-#define BM_DIGCTL_CTRL_SAIF_CLKMST_SEL                      0x1000
-#define BV_DIGCTL_CTRL_SAIF_CLKMST_SEL__SAIF1_MST           0x0
-#define BV_DIGCTL_CTRL_SAIF_CLKMST_SEL__SAIF2_MST           0x1
-#define BF_DIGCTL_CTRL_SAIF_CLKMST_SEL(v)                   (((v) << 12) & 0x1000)
-#define BF_DIGCTL_CTRL_SAIF_CLKMST_SEL_V(v)                 ((BV_DIGCTL_CTRL_SAIF_CLKMST_SEL__##v << 12) & 0x1000)
-#define BP_DIGCTL_CTRL_SAIF_ALT_BITCLK_SEL                  11
-#define BM_DIGCTL_CTRL_SAIF_ALT_BITCLK_SEL                  0x800
-#define BF_DIGCTL_CTRL_SAIF_ALT_BITCLK_SEL(v)               (((v) << 11) & 0x800)
-#define BP_DIGCTL_CTRL_USE_SERIAL_JTAG                      6
-#define BM_DIGCTL_CTRL_USE_SERIAL_JTAG                      0x40
-#define BV_DIGCTL_CTRL_USE_SERIAL_JTAG__OLD_JTAG            0x0
-#define BV_DIGCTL_CTRL_USE_SERIAL_JTAG__SERIAL_JTAG         0x1
-#define BF_DIGCTL_CTRL_USE_SERIAL_JTAG(v)                   (((v) << 6) & 0x40)
-#define BF_DIGCTL_CTRL_USE_SERIAL_JTAG_V(v)                 ((BV_DIGCTL_CTRL_USE_SERIAL_JTAG__##v << 6) & 0x40)
-#define BP_DIGCTL_CTRL_TRAP_IN_RANGE                        5
-#define BM_DIGCTL_CTRL_TRAP_IN_RANGE                        0x20
-#define BF_DIGCTL_CTRL_TRAP_IN_RANGE(v)                     (((v) << 5) & 0x20)
-#define BP_DIGCTL_CTRL_TRAP_ENABLE                          4
-#define BM_DIGCTL_CTRL_TRAP_ENABLE                          0x10
-#define BF_DIGCTL_CTRL_TRAP_ENABLE(v)                       (((v) << 4) & 0x10)
-#define BP_DIGCTL_CTRL_DEBUG_DISABLE                        3
-#define BM_DIGCTL_CTRL_DEBUG_DISABLE                        0x8
-#define BF_DIGCTL_CTRL_DEBUG_DISABLE(v)                     (((v) << 3) & 0x8)
-#define BP_DIGCTL_CTRL_USB_CLKGATE                          2
-#define BM_DIGCTL_CTRL_USB_CLKGATE                          0x4
-#define BV_DIGCTL_CTRL_USB_CLKGATE__RUN                     0x0
-#define BV_DIGCTL_CTRL_USB_CLKGATE__NO_CLKS                 0x1
-#define BF_DIGCTL_CTRL_USB_CLKGATE(v)                       (((v) << 2) & 0x4)
-#define BF_DIGCTL_CTRL_USB_CLKGATE_V(v)                     ((BV_DIGCTL_CTRL_USB_CLKGATE__##v << 2) & 0x4)
-#define BP_DIGCTL_CTRL_JTAG_SHIELD                          1
-#define BM_DIGCTL_CTRL_JTAG_SHIELD                          0x2
-#define BV_DIGCTL_CTRL_JTAG_SHIELD__NORMAL                  0x0
-#define BV_DIGCTL_CTRL_JTAG_SHIELD__SHIELDS_UP              0x1
-#define BF_DIGCTL_CTRL_JTAG_SHIELD(v)                       (((v) << 1) & 0x2)
-#define BF_DIGCTL_CTRL_JTAG_SHIELD_V(v)                     ((BV_DIGCTL_CTRL_JTAG_SHIELD__##v << 1) & 0x2)
-#define BP_DIGCTL_CTRL_LATCH_ENTROPY                        0
-#define BM_DIGCTL_CTRL_LATCH_ENTROPY                        0x1
-#define BF_DIGCTL_CTRL_LATCH_ENTROPY(v)                     (((v) << 0) & 0x1)
-
-/**
- * Register: HW_DIGCTL_STATUS
- * Address: 0x10
- * SCT: no
-*/
-#define HW_DIGCTL_STATUS                        (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x10))
-#define BP_DIGCTL_STATUS_USB_HS_PRESENT         31
-#define BM_DIGCTL_STATUS_USB_HS_PRESENT         0x80000000
-#define BF_DIGCTL_STATUS_USB_HS_PRESENT(v)      (((v) << 31) & 0x80000000)
-#define BP_DIGCTL_STATUS_USB_OTG_PRESENT        30
-#define BM_DIGCTL_STATUS_USB_OTG_PRESENT        0x40000000
-#define BF_DIGCTL_STATUS_USB_OTG_PRESENT(v)     (((v) << 30) & 0x40000000)
-#define BP_DIGCTL_STATUS_USB_HOST_PRESENT       29
-#define BM_DIGCTL_STATUS_USB_HOST_PRESENT       0x20000000
-#define BF_DIGCTL_STATUS_USB_HOST_PRESENT(v)    (((v) << 29) & 0x20000000)
-#define BP_DIGCTL_STATUS_USB_DEVICE_PRESENT     28
-#define BM_DIGCTL_STATUS_USB_DEVICE_PRESENT     0x10000000
-#define BF_DIGCTL_STATUS_USB_DEVICE_PRESENT(v)  (((v) << 28) & 0x10000000)
-#define BP_DIGCTL_STATUS_DCP_BIST_FAIL          10
-#define BM_DIGCTL_STATUS_DCP_BIST_FAIL          0x400
-#define BF_DIGCTL_STATUS_DCP_BIST_FAIL(v)       (((v) << 10) & 0x400)
-#define BP_DIGCTL_STATUS_DCP_BIST_PASS          9
-#define BM_DIGCTL_STATUS_DCP_BIST_PASS          0x200
-#define BF_DIGCTL_STATUS_DCP_BIST_PASS(v)       (((v) << 9) & 0x200)
-#define BP_DIGCTL_STATUS_DCP_BIST_DONE          8
-#define BM_DIGCTL_STATUS_DCP_BIST_DONE          0x100
-#define BF_DIGCTL_STATUS_DCP_BIST_DONE(v)       (((v) << 8) & 0x100)
-#define BP_DIGCTL_STATUS_JTAG_IN_USE            4
-#define BM_DIGCTL_STATUS_JTAG_IN_USE            0x10
-#define BF_DIGCTL_STATUS_JTAG_IN_USE(v)         (((v) << 4) & 0x10)
-#define BP_DIGCTL_STATUS_PACKAGE_TYPE           1
-#define BM_DIGCTL_STATUS_PACKAGE_TYPE           0xe
-#define BF_DIGCTL_STATUS_PACKAGE_TYPE(v)        (((v) << 1) & 0xe)
-#define BP_DIGCTL_STATUS_WRITTEN                0
-#define BM_DIGCTL_STATUS_WRITTEN                0x1
-#define BF_DIGCTL_STATUS_WRITTEN(v)             (((v) << 0) & 0x1)
-
-/**
- * Register: HW_DIGCTL_HCLKCOUNT
- * Address: 0x20
- * SCT: no
-*/
-#define HW_DIGCTL_HCLKCOUNT             (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x20))
-#define BP_DIGCTL_HCLKCOUNT_COUNT       0
-#define BM_DIGCTL_HCLKCOUNT_COUNT       0xffffffff
-#define BF_DIGCTL_HCLKCOUNT_COUNT(v)    (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_RAMCTRL
- * Address: 0x30
- * SCT: yes
-*/
-#define HW_DIGCTL_RAMCTRL                   (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x30 + 0x0))
-#define HW_DIGCTL_RAMCTRL_SET               (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x30 + 0x4))
-#define HW_DIGCTL_RAMCTRL_CLR               (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x30 + 0x8))
-#define HW_DIGCTL_RAMCTRL_TOG               (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x30 + 0xc))
-#define BP_DIGCTL_RAMCTRL_SPEED_SELECT      8
-#define BM_DIGCTL_RAMCTRL_SPEED_SELECT      0xf00
-#define BF_DIGCTL_RAMCTRL_SPEED_SELECT(v)   (((v) << 8) & 0xf00)
-#define BP_DIGCTL_RAMCTRL_RAM_REPAIR_EN     0
-#define BM_DIGCTL_RAMCTRL_RAM_REPAIR_EN     0x1
-#define BF_DIGCTL_RAMCTRL_RAM_REPAIR_EN(v)  (((v) << 0) & 0x1)
-
-/**
- * Register: HW_DIGCTL_RAMREPAIR
- * Address: 0x40
- * SCT: yes
-*/
-#define HW_DIGCTL_RAMREPAIR         (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x40 + 0x0))
-#define HW_DIGCTL_RAMREPAIR_SET     (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x40 + 0x4))
-#define HW_DIGCTL_RAMREPAIR_CLR     (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x40 + 0x8))
-#define HW_DIGCTL_RAMREPAIR_TOG     (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x40 + 0xc))
-#define BP_DIGCTL_RAMREPAIR_ADDR    0
-#define BM_DIGCTL_RAMREPAIR_ADDR    0xffff
-#define BF_DIGCTL_RAMREPAIR_ADDR(v) (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_DIGCTL_ROMCTRL
- * Address: 0x50
- * SCT: yes
-*/
-#define HW_DIGCTL_ROMCTRL               (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x50 + 0x0))
-#define HW_DIGCTL_ROMCTRL_SET           (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x50 + 0x4))
-#define HW_DIGCTL_ROMCTRL_CLR           (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x50 + 0x8))
-#define HW_DIGCTL_ROMCTRL_TOG           (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x50 + 0xc))
-#define BP_DIGCTL_ROMCTRL_RD_MARGIN     0
-#define BM_DIGCTL_ROMCTRL_RD_MARGIN     0xf
-#define BF_DIGCTL_ROMCTRL_RD_MARGIN(v)  (((v) << 0) & 0xf)
-
-/**
- * Register: HW_DIGCTL_WRITEONCE
- * Address: 0x60
- * SCT: no
-*/
-#define HW_DIGCTL_WRITEONCE         (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x60))
-#define BP_DIGCTL_WRITEONCE_BITS    0
-#define BM_DIGCTL_WRITEONCE_BITS    0xffffffff
-#define BF_DIGCTL_WRITEONCE_BITS(v) (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_ENTROPY
- * Address: 0x90
- * SCT: no
-*/
-#define HW_DIGCTL_ENTROPY           (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x90))
-#define BP_DIGCTL_ENTROPY_VALUE     0
-#define BM_DIGCTL_ENTROPY_VALUE     0xffffffff
-#define BF_DIGCTL_ENTROPY_VALUE(v)  (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_ENTROPY_LATCHED
- * Address: 0xa0
- * SCT: no
-*/
-#define HW_DIGCTL_ENTROPY_LATCHED           (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xa0))
-#define BP_DIGCTL_ENTROPY_LATCHED_VALUE     0
-#define BM_DIGCTL_ENTROPY_LATCHED_VALUE     0xffffffff
-#define BF_DIGCTL_ENTROPY_LATCHED_VALUE(v)  (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_SJTAGDBG
- * Address: 0xb0
- * SCT: yes
-*/
-#define HW_DIGCTL_SJTAGDBG                      (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xb0 + 0x0))
-#define HW_DIGCTL_SJTAGDBG_SET                  (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xb0 + 0x4))
-#define HW_DIGCTL_SJTAGDBG_CLR                  (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xb0 + 0x8))
-#define HW_DIGCTL_SJTAGDBG_TOG                  (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xb0 + 0xc))
-#define BP_DIGCTL_SJTAGDBG_SJTAG_STATE          16
-#define BM_DIGCTL_SJTAGDBG_SJTAG_STATE          0x7ff0000
-#define BF_DIGCTL_SJTAGDBG_SJTAG_STATE(v)       (((v) << 16) & 0x7ff0000)
-#define BP_DIGCTL_SJTAGDBG_SJTAG_TDO            10
-#define BM_DIGCTL_SJTAGDBG_SJTAG_TDO            0x400
-#define BF_DIGCTL_SJTAGDBG_SJTAG_TDO(v)         (((v) << 10) & 0x400)
-#define BP_DIGCTL_SJTAGDBG_SJTAG_TDI            9
-#define BM_DIGCTL_SJTAGDBG_SJTAG_TDI            0x200
-#define BF_DIGCTL_SJTAGDBG_SJTAG_TDI(v)         (((v) << 9) & 0x200)
-#define BP_DIGCTL_SJTAGDBG_SJTAG_MODE           8
-#define BM_DIGCTL_SJTAGDBG_SJTAG_MODE           0x100
-#define BF_DIGCTL_SJTAGDBG_SJTAG_MODE(v)        (((v) << 8) & 0x100)
-#define BP_DIGCTL_SJTAGDBG_DELAYED_ACTIVE       4
-#define BM_DIGCTL_SJTAGDBG_DELAYED_ACTIVE       0xf0
-#define BF_DIGCTL_SJTAGDBG_DELAYED_ACTIVE(v)    (((v) << 4) & 0xf0)
-#define BP_DIGCTL_SJTAGDBG_ACTIVE               3
-#define BM_DIGCTL_SJTAGDBG_ACTIVE               0x8
-#define BF_DIGCTL_SJTAGDBG_ACTIVE(v)            (((v) << 3) & 0x8)
-#define BP_DIGCTL_SJTAGDBG_SJTAG_PIN_STATE      2
-#define BM_DIGCTL_SJTAGDBG_SJTAG_PIN_STATE      0x4
-#define BF_DIGCTL_SJTAGDBG_SJTAG_PIN_STATE(v)   (((v) << 2) & 0x4)
-#define BP_DIGCTL_SJTAGDBG_SJTAG_DEBUG_DATA     1
-#define BM_DIGCTL_SJTAGDBG_SJTAG_DEBUG_DATA     0x2
-#define BF_DIGCTL_SJTAGDBG_SJTAG_DEBUG_DATA(v)  (((v) << 1) & 0x2)
-#define BP_DIGCTL_SJTAGDBG_SJTAG_DEBUG_OE       0
-#define BM_DIGCTL_SJTAGDBG_SJTAG_DEBUG_OE       0x1
-#define BF_DIGCTL_SJTAGDBG_SJTAG_DEBUG_OE(v)    (((v) << 0) & 0x1)
-
-/**
- * Register: HW_DIGCTL_MICROSECONDS
- * Address: 0xc0
- * SCT: yes
-*/
-#define HW_DIGCTL_MICROSECONDS          (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xc0 + 0x0))
-#define HW_DIGCTL_MICROSECONDS_SET      (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xc0 + 0x4))
-#define HW_DIGCTL_MICROSECONDS_CLR      (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xc0 + 0x8))
-#define HW_DIGCTL_MICROSECONDS_TOG      (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xc0 + 0xc))
-#define BP_DIGCTL_MICROSECONDS_VALUE    0
-#define BM_DIGCTL_MICROSECONDS_VALUE    0xffffffff
-#define BF_DIGCTL_MICROSECONDS_VALUE(v) (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_DBGRD
- * Address: 0xd0
- * SCT: no
-*/
-#define HW_DIGCTL_DBGRD                 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xd0))
-#define BP_DIGCTL_DBGRD_COMPLEMENT      0
-#define BM_DIGCTL_DBGRD_COMPLEMENT      0xffffffff
-#define BF_DIGCTL_DBGRD_COMPLEMENT(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_DBG
- * Address: 0xe0
- * SCT: no
-*/
-#define HW_DIGCTL_DBG           (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xe0))
-#define BP_DIGCTL_DBG_VALUE     0
-#define BM_DIGCTL_DBG_VALUE     0xffffffff
-#define BF_DIGCTL_DBG_VALUE(v)  (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_OCRAM_BIST_CSR
- * Address: 0xf0
- * SCT: yes
-*/
-#define HW_DIGCTL_OCRAM_BIST_CSR                        (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xf0 + 0x0))
-#define HW_DIGCTL_OCRAM_BIST_CSR_SET                    (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xf0 + 0x4))
-#define HW_DIGCTL_OCRAM_BIST_CSR_CLR                    (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xf0 + 0x8))
-#define HW_DIGCTL_OCRAM_BIST_CSR_TOG                    (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xf0 + 0xc))
-#define BP_DIGCTL_OCRAM_BIST_CSR_BIST_DATA_CHANGE       9
-#define BM_DIGCTL_OCRAM_BIST_CSR_BIST_DATA_CHANGE       0x200
-#define BF_DIGCTL_OCRAM_BIST_CSR_BIST_DATA_CHANGE(v)    (((v) << 9) & 0x200)
-#define BP_DIGCTL_OCRAM_BIST_CSR_BIST_CLKEN             8
-#define BM_DIGCTL_OCRAM_BIST_CSR_BIST_CLKEN             0x100
-#define BF_DIGCTL_OCRAM_BIST_CSR_BIST_CLKEN(v)          (((v) << 8) & 0x100)
-#define BP_DIGCTL_OCRAM_BIST_CSR_FAIL                   3
-#define BM_DIGCTL_OCRAM_BIST_CSR_FAIL                   0x8
-#define BF_DIGCTL_OCRAM_BIST_CSR_FAIL(v)                (((v) << 3) & 0x8)
-#define BP_DIGCTL_OCRAM_BIST_CSR_PASS                   2
-#define BM_DIGCTL_OCRAM_BIST_CSR_PASS                   0x4
-#define BF_DIGCTL_OCRAM_BIST_CSR_PASS(v)                (((v) << 2) & 0x4)
-#define BP_DIGCTL_OCRAM_BIST_CSR_DONE                   1
-#define BM_DIGCTL_OCRAM_BIST_CSR_DONE                   0x2
-#define BF_DIGCTL_OCRAM_BIST_CSR_DONE(v)                (((v) << 1) & 0x2)
-#define BP_DIGCTL_OCRAM_BIST_CSR_START                  0
-#define BM_DIGCTL_OCRAM_BIST_CSR_START                  0x1
-#define BF_DIGCTL_OCRAM_BIST_CSR_START(v)               (((v) << 0) & 0x1)
-
-/**
- * Register: HW_DIGCTL_OCRAM_STATUS0
- * Address: 0x110
- * SCT: no
-*/
-#define HW_DIGCTL_OCRAM_STATUS0                 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x110))
-#define BP_DIGCTL_OCRAM_STATUS0_FAILDATA00      0
-#define BM_DIGCTL_OCRAM_STATUS0_FAILDATA00      0xffffffff
-#define BF_DIGCTL_OCRAM_STATUS0_FAILDATA00(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_OCRAM_STATUS1
- * Address: 0x120
- * SCT: no
-*/
-#define HW_DIGCTL_OCRAM_STATUS1                 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x120))
-#define BP_DIGCTL_OCRAM_STATUS1_FAILDATA01      0
-#define BM_DIGCTL_OCRAM_STATUS1_FAILDATA01      0xffffffff
-#define BF_DIGCTL_OCRAM_STATUS1_FAILDATA01(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_OCRAM_STATUS2
- * Address: 0x130
- * SCT: no
-*/
-#define HW_DIGCTL_OCRAM_STATUS2                 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x130))
-#define BP_DIGCTL_OCRAM_STATUS2_FAILDATA10      0
-#define BM_DIGCTL_OCRAM_STATUS2_FAILDATA10      0xffffffff
-#define BF_DIGCTL_OCRAM_STATUS2_FAILDATA10(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_OCRAM_STATUS3
- * Address: 0x140
- * SCT: no
-*/
-#define HW_DIGCTL_OCRAM_STATUS3                 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x140))
-#define BP_DIGCTL_OCRAM_STATUS3_FAILDATA11      0
-#define BM_DIGCTL_OCRAM_STATUS3_FAILDATA11      0xffffffff
-#define BF_DIGCTL_OCRAM_STATUS3_FAILDATA11(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_OCRAM_STATUS4
- * Address: 0x150
- * SCT: no
-*/
-#define HW_DIGCTL_OCRAM_STATUS4                 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x150))
-#define BP_DIGCTL_OCRAM_STATUS4_FAILDATA20      0
-#define BM_DIGCTL_OCRAM_STATUS4_FAILDATA20      0xffffffff
-#define BF_DIGCTL_OCRAM_STATUS4_FAILDATA20(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_OCRAM_STATUS5
- * Address: 0x160
- * SCT: no
-*/
-#define HW_DIGCTL_OCRAM_STATUS5                 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x160))
-#define BP_DIGCTL_OCRAM_STATUS5_FAILDATA21      0
-#define BM_DIGCTL_OCRAM_STATUS5_FAILDATA21      0xffffffff
-#define BF_DIGCTL_OCRAM_STATUS5_FAILDATA21(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_OCRAM_STATUS6
- * Address: 0x170
- * SCT: no
-*/
-#define HW_DIGCTL_OCRAM_STATUS6                 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x170))
-#define BP_DIGCTL_OCRAM_STATUS6_FAILDATA30      0
-#define BM_DIGCTL_OCRAM_STATUS6_FAILDATA30      0xffffffff
-#define BF_DIGCTL_OCRAM_STATUS6_FAILDATA30(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_OCRAM_STATUS7
- * Address: 0x180
- * SCT: no
-*/
-#define HW_DIGCTL_OCRAM_STATUS7                 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x180))
-#define BP_DIGCTL_OCRAM_STATUS7_FAILDATA31      0
-#define BM_DIGCTL_OCRAM_STATUS7_FAILDATA31      0xffffffff
-#define BF_DIGCTL_OCRAM_STATUS7_FAILDATA31(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_OCRAM_STATUS8
- * Address: 0x190
- * SCT: no
-*/
-#define HW_DIGCTL_OCRAM_STATUS8                 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x190))
-#define BP_DIGCTL_OCRAM_STATUS8_FAILADDR01      16
-#define BM_DIGCTL_OCRAM_STATUS8_FAILADDR01      0xffff0000
-#define BF_DIGCTL_OCRAM_STATUS8_FAILADDR01(v)   (((v) << 16) & 0xffff0000)
-#define BP_DIGCTL_OCRAM_STATUS8_FAILADDR00      0
-#define BM_DIGCTL_OCRAM_STATUS8_FAILADDR00      0xffff
-#define BF_DIGCTL_OCRAM_STATUS8_FAILADDR00(v)   (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_DIGCTL_OCRAM_STATUS9
- * Address: 0x1a0
- * SCT: no
-*/
-#define HW_DIGCTL_OCRAM_STATUS9                 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1a0))
-#define BP_DIGCTL_OCRAM_STATUS9_FAILADDR11      16
-#define BM_DIGCTL_OCRAM_STATUS9_FAILADDR11      0xffff0000
-#define BF_DIGCTL_OCRAM_STATUS9_FAILADDR11(v)   (((v) << 16) & 0xffff0000)
-#define BP_DIGCTL_OCRAM_STATUS9_FAILADDR10      0
-#define BM_DIGCTL_OCRAM_STATUS9_FAILADDR10      0xffff
-#define BF_DIGCTL_OCRAM_STATUS9_FAILADDR10(v)   (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_DIGCTL_OCRAM_STATUS10
- * Address: 0x1b0
- * SCT: no
-*/
-#define HW_DIGCTL_OCRAM_STATUS10                (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1b0))
-#define BP_DIGCTL_OCRAM_STATUS10_FAILADDR21     16
-#define BM_DIGCTL_OCRAM_STATUS10_FAILADDR21     0xffff0000
-#define BF_DIGCTL_OCRAM_STATUS10_FAILADDR21(v)  (((v) << 16) & 0xffff0000)
-#define BP_DIGCTL_OCRAM_STATUS10_FAILADDR20     0
-#define BM_DIGCTL_OCRAM_STATUS10_FAILADDR20     0xffff
-#define BF_DIGCTL_OCRAM_STATUS10_FAILADDR20(v)  (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_DIGCTL_OCRAM_STATUS11
- * Address: 0x1c0
- * SCT: no
-*/
-#define HW_DIGCTL_OCRAM_STATUS11                (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1c0))
-#define BP_DIGCTL_OCRAM_STATUS11_FAILADDR31     16
-#define BM_DIGCTL_OCRAM_STATUS11_FAILADDR31     0xffff0000
-#define BF_DIGCTL_OCRAM_STATUS11_FAILADDR31(v)  (((v) << 16) & 0xffff0000)
-#define BP_DIGCTL_OCRAM_STATUS11_FAILADDR30     0
-#define BM_DIGCTL_OCRAM_STATUS11_FAILADDR30     0xffff
-#define BF_DIGCTL_OCRAM_STATUS11_FAILADDR30(v)  (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_DIGCTL_OCRAM_STATUS12
- * Address: 0x1d0
- * SCT: no
-*/
-#define HW_DIGCTL_OCRAM_STATUS12                (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1d0))
-#define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE11    24
-#define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE11    0x1f000000
-#define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE11(v) (((v) << 24) & 0x1f000000)
-#define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE10    16
-#define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE10    0x1f0000
-#define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE10(v) (((v) << 16) & 0x1f0000)
-#define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE01    8
-#define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE01    0x1f00
-#define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE01(v) (((v) << 8) & 0x1f00)
-#define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE00    0
-#define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE00    0x1f
-#define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE00(v) (((v) << 0) & 0x1f)
-
-/**
- * Register: HW_DIGCTL_OCRAM_STATUS13
- * Address: 0x1e0
- * SCT: no
-*/
-#define HW_DIGCTL_OCRAM_STATUS13                (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1e0))
-#define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE31    24
-#define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE31    0x1f000000
-#define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE31(v) (((v) << 24) & 0x1f000000)
-#define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE30    16
-#define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE30    0x1f0000
-#define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE30(v) (((v) << 16) & 0x1f0000)
-#define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE21    8
-#define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE21    0x1f00
-#define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE21(v) (((v) << 8) & 0x1f00)
-#define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE20    0
-#define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE20    0x1f
-#define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE20(v) (((v) << 0) & 0x1f)
-
-/**
- * Register: HW_DIGCTL_SCRATCH0
- * Address: 0x290
- * SCT: no
-*/
-#define HW_DIGCTL_SCRATCH0          (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x290))
-#define BP_DIGCTL_SCRATCH0_PTR      0
-#define BM_DIGCTL_SCRATCH0_PTR      0xffffffff
-#define BF_DIGCTL_SCRATCH0_PTR(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_SCRATCH1
- * Address: 0x2a0
- * SCT: no
-*/
-#define HW_DIGCTL_SCRATCH1          (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x2a0))
-#define BP_DIGCTL_SCRATCH1_PTR      0
-#define BM_DIGCTL_SCRATCH1_PTR      0xffffffff
-#define BF_DIGCTL_SCRATCH1_PTR(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_ARMCACHE
- * Address: 0x2b0
- * SCT: no
-*/
-#define HW_DIGCTL_ARMCACHE              (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x2b0))
-#define BP_DIGCTL_ARMCACHE_CACHE_SS     8
-#define BM_DIGCTL_ARMCACHE_CACHE_SS     0x300
-#define BF_DIGCTL_ARMCACHE_CACHE_SS(v)  (((v) << 8) & 0x300)
-#define BP_DIGCTL_ARMCACHE_DTAG_SS      4
-#define BM_DIGCTL_ARMCACHE_DTAG_SS      0x30
-#define BF_DIGCTL_ARMCACHE_DTAG_SS(v)   (((v) << 4) & 0x30)
-#define BP_DIGCTL_ARMCACHE_ITAG_SS      0
-#define BM_DIGCTL_ARMCACHE_ITAG_SS      0x3
-#define BF_DIGCTL_ARMCACHE_ITAG_SS(v)   (((v) << 0) & 0x3)
-
-/**
- * Register: HW_DIGCTL_DEBUG_TRAP_ADDR_LOW
- * Address: 0x2c0
- * SCT: no
-*/
-#define HW_DIGCTL_DEBUG_TRAP_ADDR_LOW           (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x2c0))
-#define BP_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR      0
-#define BM_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR      0xffffffff
-#define BF_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_DEBUG_TRAP_ADDR_HIGH
- * Address: 0x2d0
- * SCT: no
-*/
-#define HW_DIGCTL_DEBUG_TRAP_ADDR_HIGH          (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x2d0))
-#define BP_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR     0
-#define BM_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR     0xffffffff
-#define BF_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR(v)  (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_SGTL
- * Address: 0x300
- * SCT: no
-*/
-#define HW_DIGCTL_SGTL              (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x300))
-#define BP_DIGCTL_SGTL_COPYRIGHT    0
-#define BM_DIGCTL_SGTL_COPYRIGHT    0xffffffff
-#define BF_DIGCTL_SGTL_COPYRIGHT(v) (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_CHIPID
- * Address: 0x310
- * SCT: no
-*/
-#define HW_DIGCTL_CHIPID                    (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x310))
-#define BP_DIGCTL_CHIPID_PRODUCT_CODE       16
-#define BM_DIGCTL_CHIPID_PRODUCT_CODE       0xffff0000
-#define BF_DIGCTL_CHIPID_PRODUCT_CODE(v)    (((v) << 16) & 0xffff0000)
-#define BP_DIGCTL_CHIPID_REVISION           0
-#define BM_DIGCTL_CHIPID_REVISION           0xff
-#define BF_DIGCTL_CHIPID_REVISION(v)        (((v) << 0) & 0xff)
-
-/**
- * Register: HW_DIGCTL_AHB_STATS_SELECT
- * Address: 0x330
- * SCT: no
-*/
-#define HW_DIGCTL_AHB_STATS_SELECT                          (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x330))
-#define BP_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT         24
-#define BM_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT         0xf000000
-#define BV_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT__APBH   0x1
-#define BV_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT__APBX   0x2
-#define BV_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT__USB    0x4
-#define BF_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT(v)      (((v) << 24) & 0xf000000)
-#define BF_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT_V(v)    ((BV_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT__##v << 24) & 0xf000000)
-#define BP_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT         16
-#define BM_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT         0xf0000
-#define BV_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT__ARM_D  0x1
-#define BF_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT(v)      (((v) << 16) & 0xf0000)
-#define BF_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT_V(v)    ((BV_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT__##v << 16) & 0xf0000)
-#define BP_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT         8
-#define BM_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT         0xf00
-#define BV_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT__ARM_I  0x1
-#define BF_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT(v)      (((v) << 8) & 0xf00)
-#define BF_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT_V(v)    ((BV_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT__##v << 8) & 0xf00)
-#define BP_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT         0
-#define BM_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT         0xf
-#define BV_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT__ECC8   0x1
-#define BV_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT__CRYPTO 0x2
-#define BF_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT(v)      (((v) << 0) & 0xf)
-#define BF_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT_V(v)    ((BV_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT__##v << 0) & 0xf)
-
-/**
- * Register: HW_DIGCTL_L0_AHB_ACTIVE_CYCLES
- * Address: 0x340
- * SCT: no
-*/
-#define HW_DIGCTL_L0_AHB_ACTIVE_CYCLES          (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x340))
-#define BP_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT    0
-#define BM_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT    0xffffffff
-#define BF_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT(v) (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_L0_AHB_DATA_STALLED
- * Address: 0x350
- * SCT: no
-*/
-#define HW_DIGCTL_L0_AHB_DATA_STALLED           (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x350))
-#define BP_DIGCTL_L0_AHB_DATA_STALLED_COUNT     0
-#define BM_DIGCTL_L0_AHB_DATA_STALLED_COUNT     0xffffffff
-#define BF_DIGCTL_L0_AHB_DATA_STALLED_COUNT(v)  (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_L0_AHB_DATA_CYCLES
- * Address: 0x360
- * SCT: no
-*/
-#define HW_DIGCTL_L0_AHB_DATA_CYCLES            (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x360))
-#define BP_DIGCTL_L0_AHB_DATA_CYCLES_COUNT      0
-#define BM_DIGCTL_L0_AHB_DATA_CYCLES_COUNT      0xffffffff
-#define BF_DIGCTL_L0_AHB_DATA_CYCLES_COUNT(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_L1_AHB_ACTIVE_CYCLES
- * Address: 0x370
- * SCT: no
-*/
-#define HW_DIGCTL_L1_AHB_ACTIVE_CYCLES          (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x370))
-#define BP_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT    0
-#define BM_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT    0xffffffff
-#define BF_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT(v) (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_L1_AHB_DATA_STALLED
- * Address: 0x380
- * SCT: no
-*/
-#define HW_DIGCTL_L1_AHB_DATA_STALLED           (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x380))
-#define BP_DIGCTL_L1_AHB_DATA_STALLED_COUNT     0
-#define BM_DIGCTL_L1_AHB_DATA_STALLED_COUNT     0xffffffff
-#define BF_DIGCTL_L1_AHB_DATA_STALLED_COUNT(v)  (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_L1_AHB_DATA_CYCLES
- * Address: 0x390
- * SCT: no
-*/
-#define HW_DIGCTL_L1_AHB_DATA_CYCLES            (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x390))
-#define BP_DIGCTL_L1_AHB_DATA_CYCLES_COUNT      0
-#define BM_DIGCTL_L1_AHB_DATA_CYCLES_COUNT      0xffffffff
-#define BF_DIGCTL_L1_AHB_DATA_CYCLES_COUNT(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_L2_AHB_ACTIVE_CYCLES
- * Address: 0x3a0
- * SCT: no
-*/
-#define HW_DIGCTL_L2_AHB_ACTIVE_CYCLES          (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x3a0))
-#define BP_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT    0
-#define BM_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT    0xffffffff
-#define BF_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT(v) (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_L2_AHB_DATA_STALLED
- * Address: 0x3b0
- * SCT: no
-*/
-#define HW_DIGCTL_L2_AHB_DATA_STALLED           (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x3b0))
-#define BP_DIGCTL_L2_AHB_DATA_STALLED_COUNT     0
-#define BM_DIGCTL_L2_AHB_DATA_STALLED_COUNT     0xffffffff
-#define BF_DIGCTL_L2_AHB_DATA_STALLED_COUNT(v)  (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_L2_AHB_DATA_CYCLES
- * Address: 0x3c0
- * SCT: no
-*/
-#define HW_DIGCTL_L2_AHB_DATA_CYCLES            (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x3c0))
-#define BP_DIGCTL_L2_AHB_DATA_CYCLES_COUNT      0
-#define BM_DIGCTL_L2_AHB_DATA_CYCLES_COUNT      0xffffffff
-#define BF_DIGCTL_L2_AHB_DATA_CYCLES_COUNT(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_L3_AHB_ACTIVE_CYCLES
- * Address: 0x3d0
- * SCT: no
-*/
-#define HW_DIGCTL_L3_AHB_ACTIVE_CYCLES          (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x3d0))
-#define BP_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT    0
-#define BM_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT    0xffffffff
-#define BF_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT(v) (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_L3_AHB_DATA_STALLED
- * Address: 0x3e0
- * SCT: no
-*/
-#define HW_DIGCTL_L3_AHB_DATA_STALLED           (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x3e0))
-#define BP_DIGCTL_L3_AHB_DATA_STALLED_COUNT     0
-#define BM_DIGCTL_L3_AHB_DATA_STALLED_COUNT     0xffffffff
-#define BF_DIGCTL_L3_AHB_DATA_STALLED_COUNT(v)  (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_L3_AHB_DATA_CYCLES
- * Address: 0x3f0
- * SCT: no
-*/
-#define HW_DIGCTL_L3_AHB_DATA_CYCLES            (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x3f0))
-#define BP_DIGCTL_L3_AHB_DATA_CYCLES_COUNT      0
-#define BM_DIGCTL_L3_AHB_DATA_CYCLES_COUNT      0xffffffff
-#define BF_DIGCTL_L3_AHB_DATA_CYCLES_COUNT(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DIGCTL_MPTEn_LOC
- * Address: 0x400+n*0x10
- * SCT: no
-*/
-#define HW_DIGCTL_MPTEn_LOC(n)      (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x400+(n)*0x10))
-#define BP_DIGCTL_MPTEn_LOC_LOC     0
-#define BM_DIGCTL_MPTEn_LOC_LOC     0xfff
-#define BF_DIGCTL_MPTEn_LOC_LOC(v)  (((v) << 0) & 0xfff)
-
-/**
- * Register: HW_DIGCTL_EMICLK_DELAY
- * Address: 0x480
- * SCT: no
-*/
-#define HW_DIGCTL_EMICLK_DELAY              (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x480))
-#define BP_DIGCTL_EMICLK_DELAY_NUM_TAPS     0
-#define BM_DIGCTL_EMICLK_DELAY_NUM_TAPS     0x1f
-#define BF_DIGCTL_EMICLK_DELAY_NUM_TAPS(v)  (((v) << 0) & 0x1f)
-
-#endif /* __HEADERGEN__STMP3700__DIGCTL__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-dram.h b/firmware/target/arm/imx233/regs/stmp3700/regs-dram.h
deleted file mode 100644
index b32370ddb1..0000000000
--- a/firmware/target/arm/imx233/regs/stmp3700/regs-dram.h
+++ /dev/null
@@ -1,671 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3700:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__STMP3700__DRAM__H__
-#define __HEADERGEN__STMP3700__DRAM__H__
-
-#define REGS_DRAM_BASE (0x800e0000)
-
-#define REGS_DRAM_VERSION "3.2.0"
-
-/**
- * Register: HW_DRAM_CTL00
- * Address: 0
- * SCT: no
-*/
-#define HW_DRAM_CTL00                       (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x0))
-#define BP_DRAM_CTL00_AHB0_W_PRIORITY       24
-#define BM_DRAM_CTL00_AHB0_W_PRIORITY       0x1000000
-#define BF_DRAM_CTL00_AHB0_W_PRIORITY(v)    (((v) << 24) & 0x1000000)
-#define BP_DRAM_CTL00_AHB0_R_PRIORITY       16
-#define BM_DRAM_CTL00_AHB0_R_PRIORITY       0x10000
-#define BF_DRAM_CTL00_AHB0_R_PRIORITY(v)    (((v) << 16) & 0x10000)
-#define BP_DRAM_CTL00_AHB0_FIFO_TYPE_REG    8
-#define BM_DRAM_CTL00_AHB0_FIFO_TYPE_REG    0x100
-#define BF_DRAM_CTL00_AHB0_FIFO_TYPE_REG(v) (((v) << 8) & 0x100)
-#define BP_DRAM_CTL00_ADDR_CMP_EN           0
-#define BM_DRAM_CTL00_ADDR_CMP_EN           0x1
-#define BF_DRAM_CTL00_ADDR_CMP_EN(v)        (((v) << 0) & 0x1)
-
-/**
- * Register: HW_DRAM_CTL01
- * Address: 0x4
- * SCT: no
-*/
-#define HW_DRAM_CTL01                       (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x4))
-#define BP_DRAM_CTL01_AHB2_FIFO_TYPE_REG    24
-#define BM_DRAM_CTL01_AHB2_FIFO_TYPE_REG    0x1000000
-#define BF_DRAM_CTL01_AHB2_FIFO_TYPE_REG(v) (((v) << 24) & 0x1000000)
-#define BP_DRAM_CTL01_AHB1_W_PRIORITY       16
-#define BM_DRAM_CTL01_AHB1_W_PRIORITY       0x10000
-#define BF_DRAM_CTL01_AHB1_W_PRIORITY(v)    (((v) << 16) & 0x10000)
-#define BP_DRAM_CTL01_AHB1_R_PRIORITY       8
-#define BM_DRAM_CTL01_AHB1_R_PRIORITY       0x100
-#define BF_DRAM_CTL01_AHB1_R_PRIORITY(v)    (((v) << 8) & 0x100)
-#define BP_DRAM_CTL01_AHB1_FIFO_TYPE_REG    0
-#define BM_DRAM_CTL01_AHB1_FIFO_TYPE_REG    0x1
-#define BF_DRAM_CTL01_AHB1_FIFO_TYPE_REG(v) (((v) << 0) & 0x1)
-
-/**
- * Register: HW_DRAM_CTL02
- * Address: 0x8
- * SCT: no
-*/
-#define HW_DRAM_CTL02                       (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x8))
-#define BP_DRAM_CTL02_AHB3_R_PRIORITY       24
-#define BM_DRAM_CTL02_AHB3_R_PRIORITY       0x1000000
-#define BF_DRAM_CTL02_AHB3_R_PRIORITY(v)    (((v) << 24) & 0x1000000)
-#define BP_DRAM_CTL02_AHB3_FIFO_TYPE_REG    16
-#define BM_DRAM_CTL02_AHB3_FIFO_TYPE_REG    0x10000
-#define BF_DRAM_CTL02_AHB3_FIFO_TYPE_REG(v) (((v) << 16) & 0x10000)
-#define BP_DRAM_CTL02_AHB2_W_PRIORITY       8
-#define BM_DRAM_CTL02_AHB2_W_PRIORITY       0x100
-#define BF_DRAM_CTL02_AHB2_W_PRIORITY(v)    (((v) << 8) & 0x100)
-#define BP_DRAM_CTL02_AHB2_R_PRIORITY       0
-#define BM_DRAM_CTL02_AHB2_R_PRIORITY       0x1
-#define BF_DRAM_CTL02_AHB2_R_PRIORITY(v)    (((v) << 0) & 0x1)
-
-/**
- * Register: HW_DRAM_CTL03
- * Address: 0xc
- * SCT: no
-*/
-#define HW_DRAM_CTL03                       (*(volatile unsigned long *)(REGS_DRAM_BASE + 0xc))
-#define BP_DRAM_CTL03_AUTO_REFRESH_MODE     24
-#define BM_DRAM_CTL03_AUTO_REFRESH_MODE     0x1000000
-#define BF_DRAM_CTL03_AUTO_REFRESH_MODE(v)  (((v) << 24) & 0x1000000)
-#define BP_DRAM_CTL03_AREFRESH              16
-#define BM_DRAM_CTL03_AREFRESH              0x10000
-#define BF_DRAM_CTL03_AREFRESH(v)           (((v) << 16) & 0x10000)
-#define BP_DRAM_CTL03_AP                    8
-#define BM_DRAM_CTL03_AP                    0x100
-#define BF_DRAM_CTL03_AP(v)                 (((v) << 8) & 0x100)
-#define BP_DRAM_CTL03_AHB3_W_PRIORITY       0
-#define BM_DRAM_CTL03_AHB3_W_PRIORITY       0x1
-#define BF_DRAM_CTL03_AHB3_W_PRIORITY(v)    (((v) << 0) & 0x1)
-
-/**
- * Register: HW_DRAM_CTL04
- * Address: 0x10
- * SCT: no
-*/
-#define HW_DRAM_CTL04                       (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x10))
-#define BP_DRAM_CTL04_DLL_BYPASS_MODE       24
-#define BM_DRAM_CTL04_DLL_BYPASS_MODE       0x1000000
-#define BF_DRAM_CTL04_DLL_BYPASS_MODE(v)    (((v) << 24) & 0x1000000)
-#define BP_DRAM_CTL04_DLLLOCKREG            16
-#define BM_DRAM_CTL04_DLLLOCKREG            0x10000
-#define BF_DRAM_CTL04_DLLLOCKREG(v)         (((v) << 16) & 0x10000)
-#define BP_DRAM_CTL04_CONCURRENTAP          8
-#define BM_DRAM_CTL04_CONCURRENTAP          0x100
-#define BF_DRAM_CTL04_CONCURRENTAP(v)       (((v) << 8) & 0x100)
-#define BP_DRAM_CTL04_BANK_SPLIT_EN         0
-#define BM_DRAM_CTL04_BANK_SPLIT_EN         0x1
-#define BF_DRAM_CTL04_BANK_SPLIT_EN(v)      (((v) << 0) & 0x1)
-
-/**
- * Register: HW_DRAM_CTL05
- * Address: 0x14
- * SCT: no
-*/
-#define HW_DRAM_CTL05                       (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x14))
-#define BP_DRAM_CTL05_INTRPTREADA           24
-#define BM_DRAM_CTL05_INTRPTREADA           0x1000000
-#define BF_DRAM_CTL05_INTRPTREADA(v)        (((v) << 24) & 0x1000000)
-#define BP_DRAM_CTL05_INTRPTAPBURST         16
-#define BM_DRAM_CTL05_INTRPTAPBURST         0x10000
-#define BF_DRAM_CTL05_INTRPTAPBURST(v)      (((v) << 16) & 0x10000)
-#define BP_DRAM_CTL05_FAST_WRITE            8
-#define BM_DRAM_CTL05_FAST_WRITE            0x100
-#define BF_DRAM_CTL05_FAST_WRITE(v)         (((v) << 8) & 0x100)
-#define BP_DRAM_CTL05_EN_LOWPOWER_MODE      0
-#define BM_DRAM_CTL05_EN_LOWPOWER_MODE      0x1
-#define BF_DRAM_CTL05_EN_LOWPOWER_MODE(v)   (((v) << 0) & 0x1)
-
-/**
- * Register: HW_DRAM_CTL06
- * Address: 0x18
- * SCT: no
-*/
-#define HW_DRAM_CTL06                   (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x18))
-#define BP_DRAM_CTL06_POWER_DOWN        24
-#define BM_DRAM_CTL06_POWER_DOWN        0x1000000
-#define BF_DRAM_CTL06_POWER_DOWN(v)     (((v) << 24) & 0x1000000)
-#define BP_DRAM_CTL06_PLACEMENT_EN      16
-#define BM_DRAM_CTL06_PLACEMENT_EN      0x10000
-#define BF_DRAM_CTL06_PLACEMENT_EN(v)   (((v) << 16) & 0x10000)
-#define BP_DRAM_CTL06_NO_CMD_INIT       8
-#define BM_DRAM_CTL06_NO_CMD_INIT       0x100
-#define BF_DRAM_CTL06_NO_CMD_INIT(v)    (((v) << 8) & 0x100)
-#define BP_DRAM_CTL06_INTRPTWRITEA      0
-#define BM_DRAM_CTL06_INTRPTWRITEA      0x1
-#define BF_DRAM_CTL06_INTRPTWRITEA(v)   (((v) << 0) & 0x1)
-
-/**
- * Register: HW_DRAM_CTL07
- * Address: 0x1c
- * SCT: no
-*/
-#define HW_DRAM_CTL07                       (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x1c))
-#define BP_DRAM_CTL07_RW_SAME_EN            24
-#define BM_DRAM_CTL07_RW_SAME_EN            0x1000000
-#define BF_DRAM_CTL07_RW_SAME_EN(v)         (((v) << 24) & 0x1000000)
-#define BP_DRAM_CTL07_REG_DIMM_ENABLE       16
-#define BM_DRAM_CTL07_REG_DIMM_ENABLE       0x10000
-#define BF_DRAM_CTL07_REG_DIMM_ENABLE(v)    (((v) << 16) & 0x10000)
-#define BP_DRAM_CTL07_RD2RD_TURN            8
-#define BM_DRAM_CTL07_RD2RD_TURN            0x100
-#define BF_DRAM_CTL07_RD2RD_TURN(v)         (((v) << 8) & 0x100)
-#define BP_DRAM_CTL07_PRIORITY_EN           0
-#define BM_DRAM_CTL07_PRIORITY_EN           0x1
-#define BF_DRAM_CTL07_PRIORITY_EN(v)        (((v) << 0) & 0x1)
-
-/**
- * Register: HW_DRAM_CTL08
- * Address: 0x20
- * SCT: no
-*/
-#define HW_DRAM_CTL08                   (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x20))
-#define BP_DRAM_CTL08_TRAS_LOCKOUT      24
-#define BM_DRAM_CTL08_TRAS_LOCKOUT      0x1000000
-#define BF_DRAM_CTL08_TRAS_LOCKOUT(v)   (((v) << 24) & 0x1000000)
-#define BP_DRAM_CTL08_START             16
-#define BM_DRAM_CTL08_START             0x10000
-#define BF_DRAM_CTL08_START(v)          (((v) << 16) & 0x10000)
-#define BP_DRAM_CTL08_SREFRESH          8
-#define BM_DRAM_CTL08_SREFRESH          0x100
-#define BF_DRAM_CTL08_SREFRESH(v)       (((v) << 8) & 0x100)
-#define BP_DRAM_CTL08_SDR_MODE          0
-#define BM_DRAM_CTL08_SDR_MODE          0x1
-#define BF_DRAM_CTL08_SDR_MODE(v)       (((v) << 0) & 0x1)
-
-/**
- * Register: HW_DRAM_CTL09
- * Address: 0x24
- * SCT: no
-*/
-#define HW_DRAM_CTL09                           (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x24))
-#define BP_DRAM_CTL09_OUT_OF_RANGE_TYPE         24
-#define BM_DRAM_CTL09_OUT_OF_RANGE_TYPE         0x3000000
-#define BF_DRAM_CTL09_OUT_OF_RANGE_TYPE(v)      (((v) << 24) & 0x3000000)
-#define BP_DRAM_CTL09_OUT_OF_RANGE_SOURCE_ID    16
-#define BM_DRAM_CTL09_OUT_OF_RANGE_SOURCE_ID    0x30000
-#define BF_DRAM_CTL09_OUT_OF_RANGE_SOURCE_ID(v) (((v) << 16) & 0x30000)
-#define BP_DRAM_CTL09_WRITE_MODEREG             8
-#define BM_DRAM_CTL09_WRITE_MODEREG             0x100
-#define BF_DRAM_CTL09_WRITE_MODEREG(v)          (((v) << 8) & 0x100)
-#define BP_DRAM_CTL09_WRITEINTERP               0
-#define BM_DRAM_CTL09_WRITEINTERP               0x1
-#define BF_DRAM_CTL09_WRITEINTERP(v)            (((v) << 0) & 0x1)
-
-/**
- * Register: HW_DRAM_CTL10
- * Address: 0x28
- * SCT: no
-*/
-#define HW_DRAM_CTL10               (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x28))
-#define BP_DRAM_CTL10_AGE_COUNT     24
-#define BM_DRAM_CTL10_AGE_COUNT     0x7000000
-#define BF_DRAM_CTL10_AGE_COUNT(v)  (((v) << 24) & 0x7000000)
-#define BP_DRAM_CTL10_ADDR_PINS     16
-#define BM_DRAM_CTL10_ADDR_PINS     0x70000
-#define BF_DRAM_CTL10_ADDR_PINS(v)  (((v) << 16) & 0x70000)
-#define BP_DRAM_CTL10_TEMRS         8
-#define BM_DRAM_CTL10_TEMRS         0x300
-#define BF_DRAM_CTL10_TEMRS(v)      (((v) << 8) & 0x300)
-#define BP_DRAM_CTL10_Q_FULLNESS    0
-#define BM_DRAM_CTL10_Q_FULLNESS    0x3
-#define BF_DRAM_CTL10_Q_FULLNESS(v) (((v) << 0) & 0x3)
-
-/**
- * Register: HW_DRAM_CTL11
- * Address: 0x2c
- * SCT: no
-*/
-#define HW_DRAM_CTL11                       (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x2c))
-#define BP_DRAM_CTL11_MAX_CS_REG            24
-#define BM_DRAM_CTL11_MAX_CS_REG            0x7000000
-#define BF_DRAM_CTL11_MAX_CS_REG(v)         (((v) << 24) & 0x7000000)
-#define BP_DRAM_CTL11_COMMAND_AGE_COUNT     16
-#define BM_DRAM_CTL11_COMMAND_AGE_COUNT     0x70000
-#define BF_DRAM_CTL11_COMMAND_AGE_COUNT(v)  (((v) << 16) & 0x70000)
-#define BP_DRAM_CTL11_COLUMN_SIZE           8
-#define BM_DRAM_CTL11_COLUMN_SIZE           0x700
-#define BF_DRAM_CTL11_COLUMN_SIZE(v)        (((v) << 8) & 0x700)
-#define BP_DRAM_CTL11_CASLAT                0
-#define BM_DRAM_CTL11_CASLAT                0x7
-#define BF_DRAM_CTL11_CASLAT(v)             (((v) << 0) & 0x7)
-
-/**
- * Register: HW_DRAM_CTL12
- * Address: 0x30
- * SCT: no
-*/
-#define HW_DRAM_CTL12               (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x30))
-#define BP_DRAM_CTL12_TWR_INT       24
-#define BM_DRAM_CTL12_TWR_INT       0x7000000
-#define BF_DRAM_CTL12_TWR_INT(v)    (((v) << 24) & 0x7000000)
-#define BP_DRAM_CTL12_TRRD          16
-#define BM_DRAM_CTL12_TRRD          0x70000
-#define BF_DRAM_CTL12_TRRD(v)       (((v) << 16) & 0x70000)
-#define BP_DRAM_CTL12_TCKE          0
-#define BM_DRAM_CTL12_TCKE          0x7
-#define BF_DRAM_CTL12_TCKE(v)       (((v) << 0) & 0x7)
-
-/**
- * Register: HW_DRAM_CTL13
- * Address: 0x34
- * SCT: no
-*/
-#define HW_DRAM_CTL13                       (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x34))
-#define BP_DRAM_CTL13_CASLAT_LIN_GATE       24
-#define BM_DRAM_CTL13_CASLAT_LIN_GATE       0xf000000
-#define BF_DRAM_CTL13_CASLAT_LIN_GATE(v)    (((v) << 24) & 0xf000000)
-#define BP_DRAM_CTL13_CASLAT_LIN            16
-#define BM_DRAM_CTL13_CASLAT_LIN            0xf0000
-#define BF_DRAM_CTL13_CASLAT_LIN(v)         (((v) << 16) & 0xf0000)
-#define BP_DRAM_CTL13_APREBIT               8
-#define BM_DRAM_CTL13_APREBIT               0xf00
-#define BF_DRAM_CTL13_APREBIT(v)            (((v) << 8) & 0xf00)
-#define BP_DRAM_CTL13_TWTR                  0
-#define BM_DRAM_CTL13_TWTR                  0x7
-#define BF_DRAM_CTL13_TWTR(v)               (((v) << 0) & 0x7)
-
-/**
- * Register: HW_DRAM_CTL14
- * Address: 0x38
- * SCT: no
-*/
-#define HW_DRAM_CTL14                               (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x38))
-#define BP_DRAM_CTL14_MAX_COL_REG                   24
-#define BM_DRAM_CTL14_MAX_COL_REG                   0xf000000
-#define BF_DRAM_CTL14_MAX_COL_REG(v)                (((v) << 24) & 0xf000000)
-#define BP_DRAM_CTL14_LOWPOWER_REFRESH_ENABLE       16
-#define BM_DRAM_CTL14_LOWPOWER_REFRESH_ENABLE       0xf0000
-#define BF_DRAM_CTL14_LOWPOWER_REFRESH_ENABLE(v)    (((v) << 16) & 0xf0000)
-#define BP_DRAM_CTL14_INITAREF                      8
-#define BM_DRAM_CTL14_INITAREF                      0xf00
-#define BF_DRAM_CTL14_INITAREF(v)                   (((v) << 8) & 0xf00)
-#define BP_DRAM_CTL14_CS_MAP                        0
-#define BM_DRAM_CTL14_CS_MAP                        0xf
-#define BF_DRAM_CTL14_CS_MAP(v)                     (((v) << 0) & 0xf)
-
-/**
- * Register: HW_DRAM_CTL15
- * Address: 0x3c
- * SCT: no
-*/
-#define HW_DRAM_CTL15                   (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x3c))
-#define BP_DRAM_CTL15_TRP               24
-#define BM_DRAM_CTL15_TRP               0xf000000
-#define BF_DRAM_CTL15_TRP(v)            (((v) << 24) & 0xf000000)
-#define BP_DRAM_CTL15_TDAL              16
-#define BM_DRAM_CTL15_TDAL              0xf0000
-#define BF_DRAM_CTL15_TDAL(v)           (((v) << 16) & 0xf0000)
-#define BP_DRAM_CTL15_PORT_BUSY         8
-#define BM_DRAM_CTL15_PORT_BUSY         0xf00
-#define BF_DRAM_CTL15_PORT_BUSY(v)      (((v) << 8) & 0xf00)
-#define BP_DRAM_CTL15_MAX_ROW_REG       0
-#define BM_DRAM_CTL15_MAX_ROW_REG       0xf
-#define BF_DRAM_CTL15_MAX_ROW_REG(v)    (((v) << 0) & 0xf)
-
-/**
- * Register: HW_DRAM_CTL16
- * Address: 0x40
- * SCT: no
-*/
-#define HW_DRAM_CTL16                           (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x40))
-#define BP_DRAM_CTL16_TMRD                      24
-#define BM_DRAM_CTL16_TMRD                      0x1f000000
-#define BF_DRAM_CTL16_TMRD(v)                   (((v) << 24) & 0x1f000000)
-#define BP_DRAM_CTL16_LOWPOWER_CONTROL          16
-#define BM_DRAM_CTL16_LOWPOWER_CONTROL          0x1f0000
-#define BF_DRAM_CTL16_LOWPOWER_CONTROL(v)       (((v) << 16) & 0x1f0000)
-#define BP_DRAM_CTL16_LOWPOWER_AUTO_ENABLE      8
-#define BM_DRAM_CTL16_LOWPOWER_AUTO_ENABLE      0x1f00
-#define BF_DRAM_CTL16_LOWPOWER_AUTO_ENABLE(v)   (((v) << 8) & 0x1f00)
-#define BP_DRAM_CTL16_INT_ACK                   0
-#define BM_DRAM_CTL16_INT_ACK                   0xf
-#define BF_DRAM_CTL16_INT_ACK(v)                (((v) << 0) & 0xf)
-
-/**
- * Register: HW_DRAM_CTL17
- * Address: 0x44
- * SCT: no
-*/
-#define HW_DRAM_CTL17                       (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x44))
-#define BP_DRAM_CTL17_DLL_START_POINT       24
-#define BM_DRAM_CTL17_DLL_START_POINT       0xff000000
-#define BF_DRAM_CTL17_DLL_START_POINT(v)    (((v) << 24) & 0xff000000)
-#define BP_DRAM_CTL17_DLL_LOCK              16
-#define BM_DRAM_CTL17_DLL_LOCK              0xff0000
-#define BF_DRAM_CTL17_DLL_LOCK(v)           (((v) << 16) & 0xff0000)
-#define BP_DRAM_CTL17_DLL_INCREMENT         8
-#define BM_DRAM_CTL17_DLL_INCREMENT         0xff00
-#define BF_DRAM_CTL17_DLL_INCREMENT(v)      (((v) << 8) & 0xff00)
-#define BP_DRAM_CTL17_TRC                   0
-#define BM_DRAM_CTL17_TRC                   0x1f
-#define BF_DRAM_CTL17_TRC(v)                (((v) << 0) & 0x1f)
-
-/**
- * Register: HW_DRAM_CTL18
- * Address: 0x48
- * SCT: no
-*/
-#define HW_DRAM_CTL18                       (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x48))
-#define BP_DRAM_CTL18_DLL_DQS_DELAY_1       24
-#define BM_DRAM_CTL18_DLL_DQS_DELAY_1       0x7f000000
-#define BF_DRAM_CTL18_DLL_DQS_DELAY_1(v)    (((v) << 24) & 0x7f000000)
-#define BP_DRAM_CTL18_DLL_DQS_DELAY_0       16
-#define BM_DRAM_CTL18_DLL_DQS_DELAY_0       0x7f0000
-#define BF_DRAM_CTL18_DLL_DQS_DELAY_0(v)    (((v) << 16) & 0x7f0000)
-#define BP_DRAM_CTL18_INT_STATUS            8
-#define BM_DRAM_CTL18_INT_STATUS            0x1f00
-#define BF_DRAM_CTL18_INT_STATUS(v)         (((v) << 8) & 0x1f00)
-#define BP_DRAM_CTL18_INT_MASK              0
-#define BM_DRAM_CTL18_INT_MASK              0x1f
-#define BF_DRAM_CTL18_INT_MASK(v)           (((v) << 0) & 0x1f)
-
-/**
- * Register: HW_DRAM_CTL19
- * Address: 0x4c
- * SCT: no
-*/
-#define HW_DRAM_CTL19                           (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x4c))
-#define BP_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS      24
-#define BM_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS      0xff000000
-#define BF_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS(v)   (((v) << 24) & 0xff000000)
-#define BP_DRAM_CTL19_DQS_OUT_SHIFT             16
-#define BM_DRAM_CTL19_DQS_OUT_SHIFT             0x7f0000
-#define BF_DRAM_CTL19_DQS_OUT_SHIFT(v)          (((v) << 16) & 0x7f0000)
-#define BP_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1    8
-#define BM_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1    0xff00
-#define BF_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1(v) (((v) << 8) & 0xff00)
-#define BP_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0    0
-#define BM_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0    0xff
-#define BF_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0(v) (((v) << 0) & 0xff)
-
-/**
- * Register: HW_DRAM_CTL20
- * Address: 0x50
- * SCT: no
-*/
-#define HW_DRAM_CTL20                           (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x50))
-#define BP_DRAM_CTL20_TRCD_INT                  24
-#define BM_DRAM_CTL20_TRCD_INT                  0xff000000
-#define BF_DRAM_CTL20_TRCD_INT(v)               (((v) << 24) & 0xff000000)
-#define BP_DRAM_CTL20_TRAS_MIN                  16
-#define BM_DRAM_CTL20_TRAS_MIN                  0xff0000
-#define BF_DRAM_CTL20_TRAS_MIN(v)               (((v) << 16) & 0xff0000)
-#define BP_DRAM_CTL20_WR_DQS_SHIFT_BYPASS       8
-#define BM_DRAM_CTL20_WR_DQS_SHIFT_BYPASS       0xff00
-#define BF_DRAM_CTL20_WR_DQS_SHIFT_BYPASS(v)    (((v) << 8) & 0xff00)
-#define BP_DRAM_CTL20_WR_DQS_SHIFT              0
-#define BM_DRAM_CTL20_WR_DQS_SHIFT              0x7f
-#define BF_DRAM_CTL20_WR_DQS_SHIFT(v)           (((v) << 0) & 0x7f)
-
-/**
- * Register: HW_DRAM_CTL21
- * Address: 0x54
- * SCT: no
-*/
-#define HW_DRAM_CTL21                           (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x54))
-#define BP_DRAM_CTL21_OUT_OF_RANGE_LENGTH       8
-#define BM_DRAM_CTL21_OUT_OF_RANGE_LENGTH       0x3ff00
-#define BF_DRAM_CTL21_OUT_OF_RANGE_LENGTH(v)    (((v) << 8) & 0x3ff00)
-#define BP_DRAM_CTL21_TRFC                      0
-#define BM_DRAM_CTL21_TRFC                      0xff
-#define BF_DRAM_CTL21_TRFC(v)                   (((v) << 0) & 0xff)
-
-/**
- * Register: HW_DRAM_CTL22
- * Address: 0x58
- * SCT: no
-*/
-#define HW_DRAM_CTL22               (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x58))
-#define BP_DRAM_CTL22_AHB0_WRCNT    16
-#define BM_DRAM_CTL22_AHB0_WRCNT    0x7ff0000
-#define BF_DRAM_CTL22_AHB0_WRCNT(v) (((v) << 16) & 0x7ff0000)
-#define BP_DRAM_CTL22_AHB0_RDCNT    0
-#define BM_DRAM_CTL22_AHB0_RDCNT    0x7ff
-#define BF_DRAM_CTL22_AHB0_RDCNT(v) (((v) << 0) & 0x7ff)
-
-/**
- * Register: HW_DRAM_CTL23
- * Address: 0x5c
- * SCT: no
-*/
-#define HW_DRAM_CTL23               (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x5c))
-#define BP_DRAM_CTL23_AHB1_WRCNT    16
-#define BM_DRAM_CTL23_AHB1_WRCNT    0x7ff0000
-#define BF_DRAM_CTL23_AHB1_WRCNT(v) (((v) << 16) & 0x7ff0000)
-#define BP_DRAM_CTL23_AHB1_RDCNT    0
-#define BM_DRAM_CTL23_AHB1_RDCNT    0x7ff
-#define BF_DRAM_CTL23_AHB1_RDCNT(v) (((v) << 0) & 0x7ff)
-
-/**
- * Register: HW_DRAM_CTL24
- * Address: 0x60
- * SCT: no
-*/
-#define HW_DRAM_CTL24               (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x60))
-#define BP_DRAM_CTL24_AHB2_WRCNT    16
-#define BM_DRAM_CTL24_AHB2_WRCNT    0x7ff0000
-#define BF_DRAM_CTL24_AHB2_WRCNT(v) (((v) << 16) & 0x7ff0000)
-#define BP_DRAM_CTL24_AHB2_RDCNT    0
-#define BM_DRAM_CTL24_AHB2_RDCNT    0x7ff
-#define BF_DRAM_CTL24_AHB2_RDCNT(v) (((v) << 0) & 0x7ff)
-
-/**
- * Register: HW_DRAM_CTL25
- * Address: 0x64
- * SCT: no
-*/
-#define HW_DRAM_CTL25               (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x64))
-#define BP_DRAM_CTL25_AHB3_WRCNT    16
-#define BM_DRAM_CTL25_AHB3_WRCNT    0x7ff0000
-#define BF_DRAM_CTL25_AHB3_WRCNT(v) (((v) << 16) & 0x7ff0000)
-#define BP_DRAM_CTL25_AHB3_RDCNT    0
-#define BM_DRAM_CTL25_AHB3_RDCNT    0x7ff
-#define BF_DRAM_CTL25_AHB3_RDCNT(v) (((v) << 0) & 0x7ff)
-
-/**
- * Register: HW_DRAM_CTL26
- * Address: 0x68
- * SCT: no
-*/
-#define HW_DRAM_CTL26           (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x68))
-#define BP_DRAM_CTL26_TREF      0
-#define BM_DRAM_CTL26_TREF      0xfff
-#define BF_DRAM_CTL26_TREF(v)   (((v) << 0) & 0xfff)
-
-/**
- * Register: HW_DRAM_CTL27
- * Address: 0x6c
- * SCT: no
-*/
-#define HW_DRAM_CTL27   (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x6c))
-
-/**
- * Register: HW_DRAM_CTL28
- * Address: 0x70
- * SCT: no
-*/
-#define HW_DRAM_CTL28   (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x70))
-
-/**
- * Register: HW_DRAM_CTL29
- * Address: 0x74
- * SCT: no
-*/
-#define HW_DRAM_CTL29                           (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x74))
-#define BP_DRAM_CTL29_LOWPOWER_INTERNAL_CNT     16
-#define BM_DRAM_CTL29_LOWPOWER_INTERNAL_CNT     0xffff0000
-#define BF_DRAM_CTL29_LOWPOWER_INTERNAL_CNT(v)  (((v) << 16) & 0xffff0000)
-#define BP_DRAM_CTL29_LOWPOWER_EXTERNAL_CNT     0
-#define BM_DRAM_CTL29_LOWPOWER_EXTERNAL_CNT     0xffff
-#define BF_DRAM_CTL29_LOWPOWER_EXTERNAL_CNT(v)  (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_DRAM_CTL30
- * Address: 0x78
- * SCT: no
-*/
-#define HW_DRAM_CTL30                               (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x78))
-#define BP_DRAM_CTL30_LOWPOWER_REFRESH_HOLD         16
-#define BM_DRAM_CTL30_LOWPOWER_REFRESH_HOLD         0xffff0000
-#define BF_DRAM_CTL30_LOWPOWER_REFRESH_HOLD(v)      (((v) << 16) & 0xffff0000)
-#define BP_DRAM_CTL30_LOWPOWER_POWER_DOWN_CNT       0
-#define BM_DRAM_CTL30_LOWPOWER_POWER_DOWN_CNT       0xffff
-#define BF_DRAM_CTL30_LOWPOWER_POWER_DOWN_CNT(v)    (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_DRAM_CTL31
- * Address: 0x7c
- * SCT: no
-*/
-#define HW_DRAM_CTL31                               (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x7c))
-#define BP_DRAM_CTL31_TDLL                          16
-#define BM_DRAM_CTL31_TDLL                          0xffff0000
-#define BF_DRAM_CTL31_TDLL(v)                       (((v) << 16) & 0xffff0000)
-#define BP_DRAM_CTL31_LOWPOWER_SELF_REFRESH_CNT     0
-#define BM_DRAM_CTL31_LOWPOWER_SELF_REFRESH_CNT     0xffff
-#define BF_DRAM_CTL31_LOWPOWER_SELF_REFRESH_CNT(v)  (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_DRAM_CTL32
- * Address: 0x80
- * SCT: no
-*/
-#define HW_DRAM_CTL32               (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x80))
-#define BP_DRAM_CTL32_TXSNR         16
-#define BM_DRAM_CTL32_TXSNR         0xffff0000
-#define BF_DRAM_CTL32_TXSNR(v)      (((v) << 16) & 0xffff0000)
-#define BP_DRAM_CTL32_TRAS_MAX      0
-#define BM_DRAM_CTL32_TRAS_MAX      0xffff
-#define BF_DRAM_CTL32_TRAS_MAX(v)   (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_DRAM_CTL33
- * Address: 0x84
- * SCT: no
-*/
-#define HW_DRAM_CTL33               (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x84))
-#define BP_DRAM_CTL33_VERSION       16
-#define BM_DRAM_CTL33_VERSION       0xffff0000
-#define BF_DRAM_CTL33_VERSION(v)    (((v) << 16) & 0xffff0000)
-#define BP_DRAM_CTL33_TXSR          0
-#define BM_DRAM_CTL33_TXSR          0xffff
-#define BF_DRAM_CTL33_TXSR(v)       (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_DRAM_CTL34
- * Address: 0x88
- * SCT: no
-*/
-#define HW_DRAM_CTL34           (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x88))
-#define BP_DRAM_CTL34_TINIT     0
-#define BM_DRAM_CTL34_TINIT     0xffffff
-#define BF_DRAM_CTL34_TINIT(v)  (((v) << 0) & 0xffffff)
-
-/**
- * Register: HW_DRAM_CTL35
- * Address: 0x8c
- * SCT: no
-*/
-#define HW_DRAM_CTL35                       (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x8c))
-#define BP_DRAM_CTL35_OUT_OF_RANGE_ADDR     0
-#define BM_DRAM_CTL35_OUT_OF_RANGE_ADDR     0x7fffffff
-#define BF_DRAM_CTL35_OUT_OF_RANGE_ADDR(v)  (((v) << 0) & 0x7fffffff)
-
-/**
- * Register: HW_DRAM_CTL36
- * Address: 0x90
- * SCT: no
-*/
-#define HW_DRAM_CTL36                           (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x90))
-#define BP_DRAM_CTL36_PWRUP_SREFRESH_EXIT       24
-#define BM_DRAM_CTL36_PWRUP_SREFRESH_EXIT       0x1000000
-#define BF_DRAM_CTL36_PWRUP_SREFRESH_EXIT(v)    (((v) << 24) & 0x1000000)
-#define BP_DRAM_CTL36_ENABLE_QUICK_SREFRESH     16
-#define BM_DRAM_CTL36_ENABLE_QUICK_SREFRESH     0x10000
-#define BF_DRAM_CTL36_ENABLE_QUICK_SREFRESH(v)  (((v) << 16) & 0x10000)
-#define BP_DRAM_CTL36_BUS_SHARE_ENABLE          8
-#define BM_DRAM_CTL36_BUS_SHARE_ENABLE          0x100
-#define BF_DRAM_CTL36_BUS_SHARE_ENABLE(v)       (((v) << 8) & 0x100)
-#define BP_DRAM_CTL36_ACTIVE_AGING              0
-#define BM_DRAM_CTL36_ACTIVE_AGING              0x1
-#define BF_DRAM_CTL36_ACTIVE_AGING(v)           (((v) << 0) & 0x1)
-
-/**
- * Register: HW_DRAM_CTL37
- * Address: 0x94
- * SCT: no
-*/
-#define HW_DRAM_CTL37                       (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x94))
-#define BP_DRAM_CTL37_BUS_SHARE_TIMEOUT     8
-#define BM_DRAM_CTL37_BUS_SHARE_TIMEOUT     0x3ff00
-#define BF_DRAM_CTL37_BUS_SHARE_TIMEOUT(v)  (((v) << 8) & 0x3ff00)
-#define BP_DRAM_CTL37_TREF_ENABLE           0
-#define BM_DRAM_CTL37_TREF_ENABLE           0x1
-#define BF_DRAM_CTL37_TREF_ENABLE(v)        (((v) << 0) & 0x1)
-
-/**
- * Register: HW_DRAM_CTL38
- * Address: 0x98
- * SCT: no
-*/
-#define HW_DRAM_CTL38                   (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x98))
-#define BP_DRAM_CTL38_EMRS2_DATA_0      16
-#define BM_DRAM_CTL38_EMRS2_DATA_0      0x1fff0000
-#define BF_DRAM_CTL38_EMRS2_DATA_0(v)   (((v) << 16) & 0x1fff0000)
-#define BP_DRAM_CTL38_EMRS1_DATA        0
-#define BM_DRAM_CTL38_EMRS1_DATA        0x1fff
-#define BF_DRAM_CTL38_EMRS1_DATA(v)     (((v) << 0) & 0x1fff)
-
-/**
- * Register: HW_DRAM_CTL39
- * Address: 0x9c
- * SCT: no
-*/
-#define HW_DRAM_CTL39                   (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x9c))
-#define BP_DRAM_CTL39_EMRS2_DATA_2      16
-#define BM_DRAM_CTL39_EMRS2_DATA_2      0x1fff0000
-#define BF_DRAM_CTL39_EMRS2_DATA_2(v)   (((v) << 16) & 0x1fff0000)
-#define BP_DRAM_CTL39_EMRS2_DATA_1      0
-#define BM_DRAM_CTL39_EMRS2_DATA_1      0x1fff
-#define BF_DRAM_CTL39_EMRS2_DATA_1(v)   (((v) << 0) & 0x1fff)
-
-/**
- * Register: HW_DRAM_CTL40
- * Address: 0xa0
- * SCT: no
-*/
-#define HW_DRAM_CTL40                   (*(volatile unsigned long *)(REGS_DRAM_BASE + 0xa0))
-#define BP_DRAM_CTL40_TPDEX             16
-#define BM_DRAM_CTL40_TPDEX             0xffff0000
-#define BF_DRAM_CTL40_TPDEX(v)          (((v) << 16) & 0xffff0000)
-#define BP_DRAM_CTL40_EMRS2_DATA_3      0
-#define BM_DRAM_CTL40_EMRS2_DATA_3      0x1fff
-#define BF_DRAM_CTL40_EMRS2_DATA_3(v)   (((v) << 0) & 0x1fff)
-
-#endif /* __HEADERGEN__STMP3700__DRAM__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-dri.h b/firmware/target/arm/imx233/regs/stmp3700/regs-dri.h
deleted file mode 100644
index 716eccfba7..0000000000
--- a/firmware/target/arm/imx233/regs/stmp3700/regs-dri.h
+++ /dev/null
@@ -1,274 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3700:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__STMP3700__DRI__H__
-#define __HEADERGEN__STMP3700__DRI__H__
-
-#define REGS_DRI_BASE (0x80074000)
-
-#define REGS_DRI_VERSION "3.2.0"
-
-/**
- * Register: HW_DRI_CTRL
- * Address: 0
- * SCT: yes
-*/
-#define HW_DRI_CTRL                                     (*(volatile unsigned long *)(REGS_DRI_BASE + 0x0 + 0x0))
-#define HW_DRI_CTRL_SET                                 (*(volatile unsigned long *)(REGS_DRI_BASE + 0x0 + 0x4))
-#define HW_DRI_CTRL_CLR                                 (*(volatile unsigned long *)(REGS_DRI_BASE + 0x0 + 0x8))
-#define HW_DRI_CTRL_TOG                                 (*(volatile unsigned long *)(REGS_DRI_BASE + 0x0 + 0xc))
-#define BP_DRI_CTRL_SFTRST                              31
-#define BM_DRI_CTRL_SFTRST                              0x80000000
-#define BV_DRI_CTRL_SFTRST__RUN                         0x0
-#define BV_DRI_CTRL_SFTRST__RESET                       0x1
-#define BF_DRI_CTRL_SFTRST(v)                           (((v) << 31) & 0x80000000)
-#define BF_DRI_CTRL_SFTRST_V(v)                         ((BV_DRI_CTRL_SFTRST__##v << 31) & 0x80000000)
-#define BP_DRI_CTRL_CLKGATE                             30
-#define BM_DRI_CTRL_CLKGATE                             0x40000000
-#define BV_DRI_CTRL_CLKGATE__RUN                        0x0
-#define BV_DRI_CTRL_CLKGATE__NO_CLKS                    0x1
-#define BF_DRI_CTRL_CLKGATE(v)                          (((v) << 30) & 0x40000000)
-#define BF_DRI_CTRL_CLKGATE_V(v)                        ((BV_DRI_CTRL_CLKGATE__##v << 30) & 0x40000000)
-#define BP_DRI_CTRL_ENABLE_INPUTS                       29
-#define BM_DRI_CTRL_ENABLE_INPUTS                       0x20000000
-#define BV_DRI_CTRL_ENABLE_INPUTS__ANALOG_LINE_IN       0x0
-#define BV_DRI_CTRL_ENABLE_INPUTS__DRI_DIGITAL_IN       0x1
-#define BF_DRI_CTRL_ENABLE_INPUTS(v)                    (((v) << 29) & 0x20000000)
-#define BF_DRI_CTRL_ENABLE_INPUTS_V(v)                  ((BV_DRI_CTRL_ENABLE_INPUTS__##v << 29) & 0x20000000)
-#define BP_DRI_CTRL_STOP_ON_OFLOW_ERROR                 26
-#define BM_DRI_CTRL_STOP_ON_OFLOW_ERROR                 0x4000000
-#define BV_DRI_CTRL_STOP_ON_OFLOW_ERROR__IGNORE         0x0
-#define BV_DRI_CTRL_STOP_ON_OFLOW_ERROR__STOP           0x1
-#define BF_DRI_CTRL_STOP_ON_OFLOW_ERROR(v)              (((v) << 26) & 0x4000000)
-#define BF_DRI_CTRL_STOP_ON_OFLOW_ERROR_V(v)            ((BV_DRI_CTRL_STOP_ON_OFLOW_ERROR__##v << 26) & 0x4000000)
-#define BP_DRI_CTRL_STOP_ON_PILOT_ERROR                 25
-#define BM_DRI_CTRL_STOP_ON_PILOT_ERROR                 0x2000000
-#define BV_DRI_CTRL_STOP_ON_PILOT_ERROR__IGNORE         0x0
-#define BV_DRI_CTRL_STOP_ON_PILOT_ERROR__STOP           0x1
-#define BF_DRI_CTRL_STOP_ON_PILOT_ERROR(v)              (((v) << 25) & 0x2000000)
-#define BF_DRI_CTRL_STOP_ON_PILOT_ERROR_V(v)            ((BV_DRI_CTRL_STOP_ON_PILOT_ERROR__##v << 25) & 0x2000000)
-#define BP_DRI_CTRL_DMA_DELAY_COUNT                     16
-#define BM_DRI_CTRL_DMA_DELAY_COUNT                     0x1f0000
-#define BF_DRI_CTRL_DMA_DELAY_COUNT(v)                  (((v) << 16) & 0x1f0000)
-#define BP_DRI_CTRL_REACQUIRE_PHASE                     15
-#define BM_DRI_CTRL_REACQUIRE_PHASE                     0x8000
-#define BV_DRI_CTRL_REACQUIRE_PHASE__NORMAL             0x0
-#define BV_DRI_CTRL_REACQUIRE_PHASE__NEW_PHASE          0x1
-#define BF_DRI_CTRL_REACQUIRE_PHASE(v)                  (((v) << 15) & 0x8000)
-#define BF_DRI_CTRL_REACQUIRE_PHASE_V(v)                ((BV_DRI_CTRL_REACQUIRE_PHASE__##v << 15) & 0x8000)
-#define BP_DRI_CTRL_OVERFLOW_IRQ_EN                     11
-#define BM_DRI_CTRL_OVERFLOW_IRQ_EN                     0x800
-#define BV_DRI_CTRL_OVERFLOW_IRQ_EN__DISABLED           0x0
-#define BV_DRI_CTRL_OVERFLOW_IRQ_EN__ENABLED            0x1
-#define BF_DRI_CTRL_OVERFLOW_IRQ_EN(v)                  (((v) << 11) & 0x800)
-#define BF_DRI_CTRL_OVERFLOW_IRQ_EN_V(v)                ((BV_DRI_CTRL_OVERFLOW_IRQ_EN__##v << 11) & 0x800)
-#define BP_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN              10
-#define BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN              0x400
-#define BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN__DISABLED    0x0
-#define BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN__ENABLED     0x1
-#define BF_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN(v)           (((v) << 10) & 0x400)
-#define BF_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN_V(v)         ((BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN__##v << 10) & 0x400)
-#define BP_DRI_CTRL_ATTENTION_IRQ_EN                    9
-#define BM_DRI_CTRL_ATTENTION_IRQ_EN                    0x200
-#define BV_DRI_CTRL_ATTENTION_IRQ_EN__DISABLED          0x0
-#define BV_DRI_CTRL_ATTENTION_IRQ_EN__ENABLED           0x1
-#define BF_DRI_CTRL_ATTENTION_IRQ_EN(v)                 (((v) << 9) & 0x200)
-#define BF_DRI_CTRL_ATTENTION_IRQ_EN_V(v)               ((BV_DRI_CTRL_ATTENTION_IRQ_EN__##v << 9) & 0x200)
-#define BP_DRI_CTRL_OVERFLOW_IRQ                        3
-#define BM_DRI_CTRL_OVERFLOW_IRQ                        0x8
-#define BV_DRI_CTRL_OVERFLOW_IRQ__NO_REQUEST            0x0
-#define BV_DRI_CTRL_OVERFLOW_IRQ__REQUEST               0x1
-#define BF_DRI_CTRL_OVERFLOW_IRQ(v)                     (((v) << 3) & 0x8)
-#define BF_DRI_CTRL_OVERFLOW_IRQ_V(v)                   ((BV_DRI_CTRL_OVERFLOW_IRQ__##v << 3) & 0x8)
-#define BP_DRI_CTRL_PILOT_SYNC_LOSS_IRQ                 2
-#define BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ                 0x4
-#define BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ__NO_REQUEST     0x0
-#define BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ__REQUEST        0x1
-#define BF_DRI_CTRL_PILOT_SYNC_LOSS_IRQ(v)              (((v) << 2) & 0x4)
-#define BF_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_V(v)            ((BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ__##v << 2) & 0x4)
-#define BP_DRI_CTRL_ATTENTION_IRQ                       1
-#define BM_DRI_CTRL_ATTENTION_IRQ                       0x2
-#define BV_DRI_CTRL_ATTENTION_IRQ__NO_REQUEST           0x0
-#define BV_DRI_CTRL_ATTENTION_IRQ__REQUEST              0x1
-#define BF_DRI_CTRL_ATTENTION_IRQ(v)                    (((v) << 1) & 0x2)
-#define BF_DRI_CTRL_ATTENTION_IRQ_V(v)                  ((BV_DRI_CTRL_ATTENTION_IRQ__##v << 1) & 0x2)
-#define BP_DRI_CTRL_RUN                                 0
-#define BM_DRI_CTRL_RUN                                 0x1
-#define BV_DRI_CTRL_RUN__HALT                           0x0
-#define BV_DRI_CTRL_RUN__RUN                            0x1
-#define BF_DRI_CTRL_RUN(v)                              (((v) << 0) & 0x1)
-#define BF_DRI_CTRL_RUN_V(v)                            ((BV_DRI_CTRL_RUN__##v << 0) & 0x1)
-
-/**
- * Register: HW_DRI_TIMING
- * Address: 0x10
- * SCT: no
-*/
-#define HW_DRI_TIMING                           (*(volatile unsigned long *)(REGS_DRI_BASE + 0x10))
-#define BP_DRI_TIMING_PILOT_REP_RATE            16
-#define BM_DRI_TIMING_PILOT_REP_RATE            0xf0000
-#define BF_DRI_TIMING_PILOT_REP_RATE(v)         (((v) << 16) & 0xf0000)
-#define BP_DRI_TIMING_GAP_DETECTION_INTERVAL    0
-#define BM_DRI_TIMING_GAP_DETECTION_INTERVAL    0xff
-#define BF_DRI_TIMING_GAP_DETECTION_INTERVAL(v) (((v) << 0) & 0xff)
-
-/**
- * Register: HW_DRI_STAT
- * Address: 0x20
- * SCT: no
-*/
-#define HW_DRI_STAT                                         (*(volatile unsigned long *)(REGS_DRI_BASE + 0x20))
-#define BP_DRI_STAT_DRI_PRESENT                             31
-#define BM_DRI_STAT_DRI_PRESENT                             0x80000000
-#define BV_DRI_STAT_DRI_PRESENT__UNAVAILABLE                0x0
-#define BV_DRI_STAT_DRI_PRESENT__AVAILABLE                  0x1
-#define BF_DRI_STAT_DRI_PRESENT(v)                          (((v) << 31) & 0x80000000)
-#define BF_DRI_STAT_DRI_PRESENT_V(v)                        ((BV_DRI_STAT_DRI_PRESENT__##v << 31) & 0x80000000)
-#define BP_DRI_STAT_PILOT_PHASE                             16
-#define BM_DRI_STAT_PILOT_PHASE                             0xf0000
-#define BF_DRI_STAT_PILOT_PHASE(v)                          (((v) << 16) & 0xf0000)
-#define BP_DRI_STAT_OVERFLOW_IRQ_SUMMARY                    3
-#define BM_DRI_STAT_OVERFLOW_IRQ_SUMMARY                    0x8
-#define BV_DRI_STAT_OVERFLOW_IRQ_SUMMARY__NO_REQUEST        0x0
-#define BV_DRI_STAT_OVERFLOW_IRQ_SUMMARY__REQUEST           0x1
-#define BF_DRI_STAT_OVERFLOW_IRQ_SUMMARY(v)                 (((v) << 3) & 0x8)
-#define BF_DRI_STAT_OVERFLOW_IRQ_SUMMARY_V(v)               ((BV_DRI_STAT_OVERFLOW_IRQ_SUMMARY__##v << 3) & 0x8)
-#define BP_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY             2
-#define BM_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY             0x4
-#define BV_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY__NO_REQUEST 0x0
-#define BV_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY__REQUEST    0x1
-#define BF_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY(v)          (((v) << 2) & 0x4)
-#define BF_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY_V(v)        ((BV_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY__##v << 2) & 0x4)
-#define BP_DRI_STAT_ATTENTION_IRQ_SUMMARY                   1
-#define BM_DRI_STAT_ATTENTION_IRQ_SUMMARY                   0x2
-#define BV_DRI_STAT_ATTENTION_IRQ_SUMMARY__NO_REQUEST       0x0
-#define BV_DRI_STAT_ATTENTION_IRQ_SUMMARY__REQUEST          0x1
-#define BF_DRI_STAT_ATTENTION_IRQ_SUMMARY(v)                (((v) << 1) & 0x2)
-#define BF_DRI_STAT_ATTENTION_IRQ_SUMMARY_V(v)              ((BV_DRI_STAT_ATTENTION_IRQ_SUMMARY__##v << 1) & 0x2)
-
-/**
- * Register: HW_DRI_DATA
- * Address: 0x30
- * SCT: no
-*/
-#define HW_DRI_DATA         (*(volatile unsigned long *)(REGS_DRI_BASE + 0x30))
-#define BP_DRI_DATA_DATA    0
-#define BM_DRI_DATA_DATA    0xffffffff
-#define BF_DRI_DATA_DATA(v) (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_DRI_DEBUG0
- * Address: 0x40
- * SCT: yes
-*/
-#define HW_DRI_DEBUG0                               (*(volatile unsigned long *)(REGS_DRI_BASE + 0x40 + 0x0))
-#define HW_DRI_DEBUG0_SET                           (*(volatile unsigned long *)(REGS_DRI_BASE + 0x40 + 0x4))
-#define HW_DRI_DEBUG0_CLR                           (*(volatile unsigned long *)(REGS_DRI_BASE + 0x40 + 0x8))
-#define HW_DRI_DEBUG0_TOG                           (*(volatile unsigned long *)(REGS_DRI_BASE + 0x40 + 0xc))
-#define BP_DRI_DEBUG0_DMAREQ                        31
-#define BM_DRI_DEBUG0_DMAREQ                        0x80000000
-#define BF_DRI_DEBUG0_DMAREQ(v)                     (((v) << 31) & 0x80000000)
-#define BP_DRI_DEBUG0_DMACMDKICK                    30
-#define BM_DRI_DEBUG0_DMACMDKICK                    0x40000000
-#define BF_DRI_DEBUG0_DMACMDKICK(v)                 (((v) << 30) & 0x40000000)
-#define BP_DRI_DEBUG0_DRI_CLK_INPUT                 29
-#define BM_DRI_DEBUG0_DRI_CLK_INPUT                 0x20000000
-#define BF_DRI_DEBUG0_DRI_CLK_INPUT(v)              (((v) << 29) & 0x20000000)
-#define BP_DRI_DEBUG0_DRI_DATA_INPUT                28
-#define BM_DRI_DEBUG0_DRI_DATA_INPUT                0x10000000
-#define BF_DRI_DEBUG0_DRI_DATA_INPUT(v)             (((v) << 28) & 0x10000000)
-#define BP_DRI_DEBUG0_TEST_MODE                     27
-#define BM_DRI_DEBUG0_TEST_MODE                     0x8000000
-#define BF_DRI_DEBUG0_TEST_MODE(v)                  (((v) << 27) & 0x8000000)
-#define BP_DRI_DEBUG0_PILOT_REP_RATE                26
-#define BM_DRI_DEBUG0_PILOT_REP_RATE                0x4000000
-#define BV_DRI_DEBUG0_PILOT_REP_RATE__8_AT_4MHZ     0x0
-#define BV_DRI_DEBUG0_PILOT_REP_RATE__12_AT_6MHZ    0x1
-#define BF_DRI_DEBUG0_PILOT_REP_RATE(v)             (((v) << 26) & 0x4000000)
-#define BF_DRI_DEBUG0_PILOT_REP_RATE_V(v)           ((BV_DRI_DEBUG0_PILOT_REP_RATE__##v << 26) & 0x4000000)
-#define BP_DRI_DEBUG0_SPARE                         18
-#define BM_DRI_DEBUG0_SPARE                         0x3fc0000
-#define BF_DRI_DEBUG0_SPARE(v)                      (((v) << 18) & 0x3fc0000)
-#define BP_DRI_DEBUG0_FRAME                         0
-#define BM_DRI_DEBUG0_FRAME                         0x3ffff
-#define BF_DRI_DEBUG0_FRAME(v)                      (((v) << 0) & 0x3ffff)
-
-/**
- * Register: HW_DRI_DEBUG1
- * Address: 0x50
- * SCT: yes
-*/
-#define HW_DRI_DEBUG1                               (*(volatile unsigned long *)(REGS_DRI_BASE + 0x50 + 0x0))
-#define HW_DRI_DEBUG1_SET                           (*(volatile unsigned long *)(REGS_DRI_BASE + 0x50 + 0x4))
-#define HW_DRI_DEBUG1_CLR                           (*(volatile unsigned long *)(REGS_DRI_BASE + 0x50 + 0x8))
-#define HW_DRI_DEBUG1_TOG                           (*(volatile unsigned long *)(REGS_DRI_BASE + 0x50 + 0xc))
-#define BP_DRI_DEBUG1_INVERT_PILOT                  31
-#define BM_DRI_DEBUG1_INVERT_PILOT                  0x80000000
-#define BV_DRI_DEBUG1_INVERT_PILOT__NORMAL          0x0
-#define BV_DRI_DEBUG1_INVERT_PILOT__INVERTED        0x1
-#define BF_DRI_DEBUG1_INVERT_PILOT(v)               (((v) << 31) & 0x80000000)
-#define BF_DRI_DEBUG1_INVERT_PILOT_V(v)             ((BV_DRI_DEBUG1_INVERT_PILOT__##v << 31) & 0x80000000)
-#define BP_DRI_DEBUG1_INVERT_ATTENTION              30
-#define BM_DRI_DEBUG1_INVERT_ATTENTION              0x40000000
-#define BV_DRI_DEBUG1_INVERT_ATTENTION__NORMAL      0x0
-#define BV_DRI_DEBUG1_INVERT_ATTENTION__INVERTED    0x1
-#define BF_DRI_DEBUG1_INVERT_ATTENTION(v)           (((v) << 30) & 0x40000000)
-#define BF_DRI_DEBUG1_INVERT_ATTENTION_V(v)         ((BV_DRI_DEBUG1_INVERT_ATTENTION__##v << 30) & 0x40000000)
-#define BP_DRI_DEBUG1_INVERT_DRI_DATA               29
-#define BM_DRI_DEBUG1_INVERT_DRI_DATA               0x20000000
-#define BV_DRI_DEBUG1_INVERT_DRI_DATA__NORMAL       0x0
-#define BV_DRI_DEBUG1_INVERT_DRI_DATA__INVERTED     0x1
-#define BF_DRI_DEBUG1_INVERT_DRI_DATA(v)            (((v) << 29) & 0x20000000)
-#define BF_DRI_DEBUG1_INVERT_DRI_DATA_V(v)          ((BV_DRI_DEBUG1_INVERT_DRI_DATA__##v << 29) & 0x20000000)
-#define BP_DRI_DEBUG1_INVERT_DRI_CLOCK              28
-#define BM_DRI_DEBUG1_INVERT_DRI_CLOCK              0x10000000
-#define BV_DRI_DEBUG1_INVERT_DRI_CLOCK__NORMAL      0x0
-#define BV_DRI_DEBUG1_INVERT_DRI_CLOCK__INVERTED    0x1
-#define BF_DRI_DEBUG1_INVERT_DRI_CLOCK(v)           (((v) << 28) & 0x10000000)
-#define BF_DRI_DEBUG1_INVERT_DRI_CLOCK_V(v)         ((BV_DRI_DEBUG1_INVERT_DRI_CLOCK__##v << 28) & 0x10000000)
-#define BP_DRI_DEBUG1_REVERSE_FRAME                 27
-#define BM_DRI_DEBUG1_REVERSE_FRAME                 0x8000000
-#define BV_DRI_DEBUG1_REVERSE_FRAME__NORMAL         0x0
-#define BV_DRI_DEBUG1_REVERSE_FRAME__REVERSED       0x1
-#define BF_DRI_DEBUG1_REVERSE_FRAME(v)              (((v) << 27) & 0x8000000)
-#define BF_DRI_DEBUG1_REVERSE_FRAME_V(v)            ((BV_DRI_DEBUG1_REVERSE_FRAME__##v << 27) & 0x8000000)
-#define BP_DRI_DEBUG1_SWIZZLED_FRAME                0
-#define BM_DRI_DEBUG1_SWIZZLED_FRAME                0x3ffff
-#define BF_DRI_DEBUG1_SWIZZLED_FRAME(v)             (((v) << 0) & 0x3ffff)
-
-/**
- * Register: HW_DRI_VERSION
- * Address: 0x60
- * SCT: no
-*/
-#define HW_DRI_VERSION          (*(volatile unsigned long *)(REGS_DRI_BASE + 0x60))
-#define BP_DRI_VERSION_MAJOR    24
-#define BM_DRI_VERSION_MAJOR    0xff000000
-#define BF_DRI_VERSION_MAJOR(v) (((v) << 24) & 0xff000000)
-#define BP_DRI_VERSION_MINOR    16
-#define BM_DRI_VERSION_MINOR    0xff0000
-#define BF_DRI_VERSION_MINOR(v) (((v) << 16) & 0xff0000)
-#define BP_DRI_VERSION_STEP     0
-#define BM_DRI_VERSION_STEP     0xffff
-#define BF_DRI_VERSION_STEP(v)  (((v) << 0) & 0xffff)
-
-#endif /* __HEADERGEN__STMP3700__DRI__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-ecc8.h b/firmware/target/arm/imx233/regs/stmp3700/regs-ecc8.h
deleted file mode 100644
index be5ba01d89..0000000000
--- a/firmware/target/arm/imx233/regs/stmp3700/regs-ecc8.h
+++ /dev/null
@@ -1,387 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3700:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__STMP3700__ECC8__H__
-#define __HEADERGEN__STMP3700__ECC8__H__
-
-#define REGS_ECC8_BASE (0x80008000)
-
-#define REGS_ECC8_VERSION "3.2.0"
-
-/**
- * Register: HW_ECC8_CTRL
- * Address: 0
- * SCT: yes
-*/
-#define HW_ECC8_CTRL                        (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x0 + 0x0))
-#define HW_ECC8_CTRL_SET                    (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x0 + 0x4))
-#define HW_ECC8_CTRL_CLR                    (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x0 + 0x8))
-#define HW_ECC8_CTRL_TOG                    (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x0 + 0xc))
-#define BP_ECC8_CTRL_SFTRST                 31
-#define BM_ECC8_CTRL_SFTRST                 0x80000000
-#define BV_ECC8_CTRL_SFTRST__RUN            0x0
-#define BV_ECC8_CTRL_SFTRST__RESET          0x1
-#define BF_ECC8_CTRL_SFTRST(v)              (((v) << 31) & 0x80000000)
-#define BF_ECC8_CTRL_SFTRST_V(v)            ((BV_ECC8_CTRL_SFTRST__##v << 31) & 0x80000000)
-#define BP_ECC8_CTRL_CLKGATE                30
-#define BM_ECC8_CTRL_CLKGATE                0x40000000
-#define BV_ECC8_CTRL_CLKGATE__RUN           0x0
-#define BV_ECC8_CTRL_CLKGATE__NO_CLKS       0x1
-#define BF_ECC8_CTRL_CLKGATE(v)             (((v) << 30) & 0x40000000)
-#define BF_ECC8_CTRL_CLKGATE_V(v)           ((BV_ECC8_CTRL_CLKGATE__##v << 30) & 0x40000000)
-#define BP_ECC8_CTRL_AHBM_SFTRST            29
-#define BM_ECC8_CTRL_AHBM_SFTRST            0x20000000
-#define BV_ECC8_CTRL_AHBM_SFTRST__RUN       0x0
-#define BV_ECC8_CTRL_AHBM_SFTRST__RESET     0x1
-#define BF_ECC8_CTRL_AHBM_SFTRST(v)         (((v) << 29) & 0x20000000)
-#define BF_ECC8_CTRL_AHBM_SFTRST_V(v)       ((BV_ECC8_CTRL_AHBM_SFTRST__##v << 29) & 0x20000000)
-#define BP_ECC8_CTRL_THROTTLE               24
-#define BM_ECC8_CTRL_THROTTLE               0xf000000
-#define BF_ECC8_CTRL_THROTTLE(v)            (((v) << 24) & 0xf000000)
-#define BP_ECC8_CTRL_DEBUG_STALL_IRQ_EN     10
-#define BM_ECC8_CTRL_DEBUG_STALL_IRQ_EN     0x400
-#define BF_ECC8_CTRL_DEBUG_STALL_IRQ_EN(v)  (((v) << 10) & 0x400)
-#define BP_ECC8_CTRL_DEBUG_WRITE_IRQ_EN     9
-#define BM_ECC8_CTRL_DEBUG_WRITE_IRQ_EN     0x200
-#define BF_ECC8_CTRL_DEBUG_WRITE_IRQ_EN(v)  (((v) << 9) & 0x200)
-#define BP_ECC8_CTRL_COMPLETE_IRQ_EN        8
-#define BM_ECC8_CTRL_COMPLETE_IRQ_EN        0x100
-#define BF_ECC8_CTRL_COMPLETE_IRQ_EN(v)     (((v) << 8) & 0x100)
-#define BP_ECC8_CTRL_BM_ERROR_IRQ           3
-#define BM_ECC8_CTRL_BM_ERROR_IRQ           0x8
-#define BF_ECC8_CTRL_BM_ERROR_IRQ(v)        (((v) << 3) & 0x8)
-#define BP_ECC8_CTRL_DEBUG_STALL_IRQ        2
-#define BM_ECC8_CTRL_DEBUG_STALL_IRQ        0x4
-#define BF_ECC8_CTRL_DEBUG_STALL_IRQ(v)     (((v) << 2) & 0x4)
-#define BP_ECC8_CTRL_DEBUG_WRITE_IRQ        1
-#define BM_ECC8_CTRL_DEBUG_WRITE_IRQ        0x2
-#define BF_ECC8_CTRL_DEBUG_WRITE_IRQ(v)     (((v) << 1) & 0x2)
-#define BP_ECC8_CTRL_COMPLETE_IRQ           0
-#define BM_ECC8_CTRL_COMPLETE_IRQ           0x1
-#define BF_ECC8_CTRL_COMPLETE_IRQ(v)        (((v) << 0) & 0x1)
-
-/**
- * Register: HW_ECC8_STATUS0
- * Address: 0x10
- * SCT: no
-*/
-#define HW_ECC8_STATUS0                                 (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x10))
-#define BP_ECC8_STATUS0_HANDLE                          16
-#define BM_ECC8_STATUS0_HANDLE                          0xffff0000
-#define BF_ECC8_STATUS0_HANDLE(v)                       (((v) << 16) & 0xffff0000)
-#define BP_ECC8_STATUS0_RS8ECC_ENC_PRESENT              15
-#define BM_ECC8_STATUS0_RS8ECC_ENC_PRESENT              0x8000
-#define BF_ECC8_STATUS0_RS8ECC_ENC_PRESENT(v)           (((v) << 15) & 0x8000)
-#define BP_ECC8_STATUS0_RS8ECC_DEC_PRESENT              14
-#define BM_ECC8_STATUS0_RS8ECC_DEC_PRESENT              0x4000
-#define BF_ECC8_STATUS0_RS8ECC_DEC_PRESENT(v)           (((v) << 14) & 0x4000)
-#define BP_ECC8_STATUS0_RS4ECC_ENC_PRESENT              13
-#define BM_ECC8_STATUS0_RS4ECC_ENC_PRESENT              0x2000
-#define BF_ECC8_STATUS0_RS4ECC_ENC_PRESENT(v)           (((v) << 13) & 0x2000)
-#define BP_ECC8_STATUS0_RS4ECC_DEC_PRESENT              12
-#define BM_ECC8_STATUS0_RS4ECC_DEC_PRESENT              0x1000
-#define BF_ECC8_STATUS0_RS4ECC_DEC_PRESENT(v)           (((v) << 12) & 0x1000)
-#define BP_ECC8_STATUS0_STATUS_AUX                      8
-#define BM_ECC8_STATUS0_STATUS_AUX                      0xf00
-#define BV_ECC8_STATUS0_STATUS_AUX__NO_ERRORS           0x0
-#define BV_ECC8_STATUS0_STATUS_AUX__ONE_CORRECTABLE     0x1
-#define BV_ECC8_STATUS0_STATUS_AUX__TWO_CORRECTABLE     0x2
-#define BV_ECC8_STATUS0_STATUS_AUX__THREE_CORRECTABLE   0x3
-#define BV_ECC8_STATUS0_STATUS_AUX__FOUR_CORRECTABLE    0x4
-#define BV_ECC8_STATUS0_STATUS_AUX__NOT_CHECKED         0xc
-#define BV_ECC8_STATUS0_STATUS_AUX__UNCORRECTABLE       0xe
-#define BV_ECC8_STATUS0_STATUS_AUX__ALL_ONES            0xf
-#define BF_ECC8_STATUS0_STATUS_AUX(v)                   (((v) << 8) & 0xf00)
-#define BF_ECC8_STATUS0_STATUS_AUX_V(v)                 ((BV_ECC8_STATUS0_STATUS_AUX__##v << 8) & 0xf00)
-#define BP_ECC8_STATUS0_ALLONES                         4
-#define BM_ECC8_STATUS0_ALLONES                         0x10
-#define BF_ECC8_STATUS0_ALLONES(v)                      (((v) << 4) & 0x10)
-#define BP_ECC8_STATUS0_CORRECTED                       3
-#define BM_ECC8_STATUS0_CORRECTED                       0x8
-#define BF_ECC8_STATUS0_CORRECTED(v)                    (((v) << 3) & 0x8)
-#define BP_ECC8_STATUS0_UNCORRECTABLE                   2
-#define BM_ECC8_STATUS0_UNCORRECTABLE                   0x4
-#define BF_ECC8_STATUS0_UNCORRECTABLE(v)                (((v) << 2) & 0x4)
-#define BP_ECC8_STATUS0_COMPLETED_CE                    0
-#define BM_ECC8_STATUS0_COMPLETED_CE                    0x3
-#define BF_ECC8_STATUS0_COMPLETED_CE(v)                 (((v) << 0) & 0x3)
-
-/**
- * Register: HW_ECC8_STATUS1
- * Address: 0x20
- * SCT: no
-*/
-#define HW_ECC8_STATUS1                                     (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x20))
-#define BP_ECC8_STATUS1_STATUS_PAYLOAD7                     28
-#define BM_ECC8_STATUS1_STATUS_PAYLOAD7                     0xf0000000
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__NO_ERRORS          0x0
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__ONE_CORRECTABLE    0x1
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__TWO_CORRECTABLE    0x2
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__THREE_CORRECTABLE  0x3
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__FOUR_CORRECTABLE   0x4
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__FIVE_CORRECTABLE   0x5
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__SIX_CORRECTABLE    0x6
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__SEVEN_CORRECTABLE  0x7
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__EIGHT_CORRECTABLE  0x8
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__NOT_CHECKED        0xc
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__UNCORRECTABLE      0xe
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__ALL_ONES           0xf
-#define BF_ECC8_STATUS1_STATUS_PAYLOAD7(v)                  (((v) << 28) & 0xf0000000)
-#define BF_ECC8_STATUS1_STATUS_PAYLOAD7_V(v)                ((BV_ECC8_STATUS1_STATUS_PAYLOAD7__##v << 28) & 0xf0000000)
-#define BP_ECC8_STATUS1_STATUS_PAYLOAD6                     24
-#define BM_ECC8_STATUS1_STATUS_PAYLOAD6                     0xf000000
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__NO_ERRORS          0x0
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__ONE_CORRECTABLE    0x1
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__TWO_CORRECTABLE    0x2
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__THREE_CORRECTABLE  0x3
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__FOUR_CORRECTABLE   0x4
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__FIVE_CORRECTABLE   0x5
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__SIX_CORRECTABLE    0x6
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__SEVEN_CORRECTABLE  0x7
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__EIGHT_CORRECTABLE  0x8
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__NOT_CHECKED        0xc
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__UNCORRECTABLE      0xe
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__ALL_ONES           0xf
-#define BF_ECC8_STATUS1_STATUS_PAYLOAD6(v)                  (((v) << 24) & 0xf000000)
-#define BF_ECC8_STATUS1_STATUS_PAYLOAD6_V(v)                ((BV_ECC8_STATUS1_STATUS_PAYLOAD6__##v << 24) & 0xf000000)
-#define BP_ECC8_STATUS1_STATUS_PAYLOAD5                     20
-#define BM_ECC8_STATUS1_STATUS_PAYLOAD5                     0xf00000
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__NO_ERRORS          0x0
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__ONE_CORRECTABLE    0x1
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__TWO_CORRECTABLE    0x2
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__THREE_CORRECTABLE  0x3
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__FOUR_CORRECTABLE   0x4
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__FIVE_CORRECTABLE   0x5
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__SIX_CORRECTABLE    0x6
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__SEVEN_CORRECTABLE  0x7
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__EIGHT_CORRECTABLE  0x8
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__NOT_CHECKED        0xc
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__UNCORRECTABLE      0xe
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__ALL_ONES           0xf
-#define BF_ECC8_STATUS1_STATUS_PAYLOAD5(v)                  (((v) << 20) & 0xf00000)
-#define BF_ECC8_STATUS1_STATUS_PAYLOAD5_V(v)                ((BV_ECC8_STATUS1_STATUS_PAYLOAD5__##v << 20) & 0xf00000)
-#define BP_ECC8_STATUS1_STATUS_PAYLOAD4                     16
-#define BM_ECC8_STATUS1_STATUS_PAYLOAD4                     0xf0000
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__NO_ERRORS          0x0
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__ONE_CORRECTABLE    0x1
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__TWO_CORRECTABLE    0x2
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__THREE_CORRECTABLE  0x3
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__FOUR_CORRECTABLE   0x4
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__FIVE_CORRECTABLE   0x5
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__SIX_CORRECTABLE    0x6
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__SEVEN_CORRECTABLE  0x7
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__EIGHT_CORRECTABLE  0x8
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__NOT_CHECKED        0xc
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__UNCORRECTABLE      0xe
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__ALL_ONES           0xf
-#define BF_ECC8_STATUS1_STATUS_PAYLOAD4(v)                  (((v) << 16) & 0xf0000)
-#define BF_ECC8_STATUS1_STATUS_PAYLOAD4_V(v)                ((BV_ECC8_STATUS1_STATUS_PAYLOAD4__##v << 16) & 0xf0000)
-#define BP_ECC8_STATUS1_STATUS_PAYLOAD3                     12
-#define BM_ECC8_STATUS1_STATUS_PAYLOAD3                     0xf000
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__NO_ERRORS          0x0
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__ONE_CORRECTABLE    0x1
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__TWO_CORRECTABLE    0x2
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__THREE_CORRECTABLE  0x3
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__FOUR_CORRECTABLE   0x4
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__FIVE_CORRECTABLE   0x5
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__SIX_CORRECTABLE    0x6
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__SEVEN_CORRECTABLE  0x7
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__EIGHT_CORRECTABLE  0x8
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__NOT_CHECKED        0xc
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__UNCORRECTABLE      0xe
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__ALL_ONES           0xf
-#define BF_ECC8_STATUS1_STATUS_PAYLOAD3(v)                  (((v) << 12) & 0xf000)
-#define BF_ECC8_STATUS1_STATUS_PAYLOAD3_V(v)                ((BV_ECC8_STATUS1_STATUS_PAYLOAD3__##v << 12) & 0xf000)
-#define BP_ECC8_STATUS1_STATUS_PAYLOAD2                     8
-#define BM_ECC8_STATUS1_STATUS_PAYLOAD2                     0xf00
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__NO_ERRORS          0x0
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__ONE_CORRECTABLE    0x1
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__TWO_CORRECTABLE    0x2
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__THREE_CORRECTABLE  0x3
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__FOUR_CORRECTABLE   0x4
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__FIVE_CORRECTABLE   0x5
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__SIX_CORRECTABLE    0x6
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__SEVEN_CORRECTABLE  0x7
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__EIGHT_CORRECTABLE  0x8
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__NOT_CHECKED        0xc
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__UNCORRECTABLE      0xe
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__ALL_ONES           0xf
-#define BF_ECC8_STATUS1_STATUS_PAYLOAD2(v)                  (((v) << 8) & 0xf00)
-#define BF_ECC8_STATUS1_STATUS_PAYLOAD2_V(v)                ((BV_ECC8_STATUS1_STATUS_PAYLOAD2__##v << 8) & 0xf00)
-#define BP_ECC8_STATUS1_STATUS_PAYLOAD1                     4
-#define BM_ECC8_STATUS1_STATUS_PAYLOAD1                     0xf0
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__NO_ERRORS          0x0
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__ONE_CORRECTABLE    0x1
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__TWO_CORRECTABLE    0x2
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__THREE_CORRECTABLE  0x3
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__FOUR_CORRECTABLE   0x4
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__FIVE_CORRECTABLE   0x5
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__SIX_CORRECTABLE    0x6
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__SEVEN_CORRECTABLE  0x7
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__EIGHT_CORRECTABLE  0x8
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__NOT_CHECKED        0xc
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__UNCORRECTABLE      0xe
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__ALL_ONES           0xf
-#define BF_ECC8_STATUS1_STATUS_PAYLOAD1(v)                  (((v) << 4) & 0xf0)
-#define BF_ECC8_STATUS1_STATUS_PAYLOAD1_V(v)                ((BV_ECC8_STATUS1_STATUS_PAYLOAD1__##v << 4) & 0xf0)
-#define BP_ECC8_STATUS1_STATUS_PAYLOAD0                     0
-#define BM_ECC8_STATUS1_STATUS_PAYLOAD0                     0xf
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__NO_ERRORS          0x0
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__ONE_CORRECTABLE    0x1
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__TWO_CORRECTABLE    0x2
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__THREE_CORRECTABLE  0x3
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__FOUR_CORRECTABLE   0x4
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__FIVE_CORRECTABLE   0x5
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__SIX_CORRECTABLE    0x6
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__SEVEN_CORRECTABLE  0x7
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__EIGHT_CORRECTABLE  0x8
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__NOT_CHECKED        0xc
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__UNCORRECTABLE      0xe
-#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__ALL_ONES           0xf
-#define BF_ECC8_STATUS1_STATUS_PAYLOAD0(v)                  (((v) << 0) & 0xf)
-#define BF_ECC8_STATUS1_STATUS_PAYLOAD0_V(v)                ((BV_ECC8_STATUS1_STATUS_PAYLOAD0__##v << 0) & 0xf)
-
-/**
- * Register: HW_ECC8_DEBUG0
- * Address: 0x30
- * SCT: yes
-*/
-#define HW_ECC8_DEBUG0                                      (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x30 + 0x0))
-#define HW_ECC8_DEBUG0_SET                                  (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x30 + 0x4))
-#define HW_ECC8_DEBUG0_CLR                                  (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x30 + 0x8))
-#define HW_ECC8_DEBUG0_TOG                                  (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x30 + 0xc))
-#define BP_ECC8_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL            16
-#define BM_ECC8_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL            0x1ff0000
-#define BV_ECC8_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__NORMAL    0x0
-#define BV_ECC8_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__TEST_MODE 0x1
-#define BF_ECC8_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL(v)         (((v) << 16) & 0x1ff0000)
-#define BF_ECC8_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_V(v)       ((BV_ECC8_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__##v << 16) & 0x1ff0000)
-#define BP_ECC8_DEBUG0_KES_DEBUG_SHIFT_SYND                 15
-#define BM_ECC8_DEBUG0_KES_DEBUG_SHIFT_SYND                 0x8000
-#define BF_ECC8_DEBUG0_KES_DEBUG_SHIFT_SYND(v)              (((v) << 15) & 0x8000)
-#define BP_ECC8_DEBUG0_KES_DEBUG_PAYLOAD_FLAG               14
-#define BM_ECC8_DEBUG0_KES_DEBUG_PAYLOAD_FLAG               0x4000
-#define BV_ECC8_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__DATA         0x1
-#define BV_ECC8_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__AUX          0x1
-#define BF_ECC8_DEBUG0_KES_DEBUG_PAYLOAD_FLAG(v)            (((v) << 14) & 0x4000)
-#define BF_ECC8_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_V(v)          ((BV_ECC8_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__##v << 14) & 0x4000)
-#define BP_ECC8_DEBUG0_KES_DEBUG_MODE4K                     13
-#define BM_ECC8_DEBUG0_KES_DEBUG_MODE4K                     0x2000
-#define BV_ECC8_DEBUG0_KES_DEBUG_MODE4K__4k                 0x1
-#define BV_ECC8_DEBUG0_KES_DEBUG_MODE4K__2k                 0x1
-#define BF_ECC8_DEBUG0_KES_DEBUG_MODE4K(v)                  (((v) << 13) & 0x2000)
-#define BF_ECC8_DEBUG0_KES_DEBUG_MODE4K_V(v)                ((BV_ECC8_DEBUG0_KES_DEBUG_MODE4K__##v << 13) & 0x2000)
-#define BP_ECC8_DEBUG0_KES_DEBUG_KICK                       12
-#define BM_ECC8_DEBUG0_KES_DEBUG_KICK                       0x1000
-#define BF_ECC8_DEBUG0_KES_DEBUG_KICK(v)                    (((v) << 12) & 0x1000)
-#define BP_ECC8_DEBUG0_KES_STANDALONE                       11
-#define BM_ECC8_DEBUG0_KES_STANDALONE                       0x800
-#define BV_ECC8_DEBUG0_KES_STANDALONE__NORMAL               0x0
-#define BV_ECC8_DEBUG0_KES_STANDALONE__TEST_MODE            0x1
-#define BF_ECC8_DEBUG0_KES_STANDALONE(v)                    (((v) << 11) & 0x800)
-#define BF_ECC8_DEBUG0_KES_STANDALONE_V(v)                  ((BV_ECC8_DEBUG0_KES_STANDALONE__##v << 11) & 0x800)
-#define BP_ECC8_DEBUG0_KES_DEBUG_STEP                       10
-#define BM_ECC8_DEBUG0_KES_DEBUG_STEP                       0x400
-#define BF_ECC8_DEBUG0_KES_DEBUG_STEP(v)                    (((v) << 10) & 0x400)
-#define BP_ECC8_DEBUG0_KES_DEBUG_STALL                      9
-#define BM_ECC8_DEBUG0_KES_DEBUG_STALL                      0x200
-#define BV_ECC8_DEBUG0_KES_DEBUG_STALL__NORMAL              0x0
-#define BV_ECC8_DEBUG0_KES_DEBUG_STALL__WAIT                0x1
-#define BF_ECC8_DEBUG0_KES_DEBUG_STALL(v)                   (((v) << 9) & 0x200)
-#define BF_ECC8_DEBUG0_KES_DEBUG_STALL_V(v)                 ((BV_ECC8_DEBUG0_KES_DEBUG_STALL__##v << 9) & 0x200)
-#define BP_ECC8_DEBUG0_BM_KES_TEST_BYPASS                   8
-#define BM_ECC8_DEBUG0_BM_KES_TEST_BYPASS                   0x100
-#define BV_ECC8_DEBUG0_BM_KES_TEST_BYPASS__NORMAL           0x0
-#define BV_ECC8_DEBUG0_BM_KES_TEST_BYPASS__TEST_MODE        0x1
-#define BF_ECC8_DEBUG0_BM_KES_TEST_BYPASS(v)                (((v) << 8) & 0x100)
-#define BF_ECC8_DEBUG0_BM_KES_TEST_BYPASS_V(v)              ((BV_ECC8_DEBUG0_BM_KES_TEST_BYPASS__##v << 8) & 0x100)
-#define BP_ECC8_DEBUG0_DEBUG_REG_SELECT                     0
-#define BM_ECC8_DEBUG0_DEBUG_REG_SELECT                     0x3f
-#define BF_ECC8_DEBUG0_DEBUG_REG_SELECT(v)                  (((v) << 0) & 0x3f)
-
-/**
- * Register: HW_ECC8_DBGKESREAD
- * Address: 0x40
- * SCT: no
-*/
-#define HW_ECC8_DBGKESREAD              (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x40))
-#define BP_ECC8_DBGKESREAD_VALUES       0
-#define BM_ECC8_DBGKESREAD_VALUES       0xffffffff
-#define BF_ECC8_DBGKESREAD_VALUES(v)    (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_ECC8_DBGCSFEREAD
- * Address: 0x50
- * SCT: no
-*/
-#define HW_ECC8_DBGCSFEREAD             (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x50))
-#define BP_ECC8_DBGCSFEREAD_VALUES      0
-#define BM_ECC8_DBGCSFEREAD_VALUES      0xffffffff
-#define BF_ECC8_DBGCSFEREAD_VALUES(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_ECC8_DBGSYNDGENREAD
- * Address: 0x60
- * SCT: no
-*/
-#define HW_ECC8_DBGSYNDGENREAD              (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x60))
-#define BP_ECC8_DBGSYNDGENREAD_VALUES       0
-#define BM_ECC8_DBGSYNDGENREAD_VALUES       0xffffffff
-#define BF_ECC8_DBGSYNDGENREAD_VALUES(v)    (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_ECC8_DBGAHBMREAD
- * Address: 0x70
- * SCT: no
-*/
-#define HW_ECC8_DBGAHBMREAD             (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x70))
-#define BP_ECC8_DBGAHBMREAD_VALUES      0
-#define BM_ECC8_DBGAHBMREAD_VALUES      0xffffffff
-#define BF_ECC8_DBGAHBMREAD_VALUES(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_ECC8_BLOCKNAME
- * Address: 0x80
- * SCT: no
-*/
-#define HW_ECC8_BLOCKNAME           (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x80))
-#define BP_ECC8_BLOCKNAME_NAME      0
-#define BM_ECC8_BLOCKNAME_NAME      0xffffffff
-#define BF_ECC8_BLOCKNAME_NAME(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_ECC8_VERSION
- * Address: 0xa0
- * SCT: no
-*/
-#define HW_ECC8_VERSION             (*(volatile unsigned long *)(REGS_ECC8_BASE + 0xa0))
-#define BP_ECC8_VERSION_MAJOR       24
-#define BM_ECC8_VERSION_MAJOR       0xff000000
-#define BF_ECC8_VERSION_MAJOR(v)    (((v) << 24) & 0xff000000)
-#define BP_ECC8_VERSION_MINOR       16
-#define BM_ECC8_VERSION_MINOR       0xff0000
-#define BF_ECC8_VERSION_MINOR(v)    (((v) << 16) & 0xff0000)
-#define BP_ECC8_VERSION_STEP        0
-#define BM_ECC8_VERSION_STEP        0xffff
-#define BF_ECC8_VERSION_STEP(v)     (((v) << 0) & 0xffff)
-
-#endif /* __HEADERGEN__STMP3700__ECC8__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-emi.h b/firmware/target/arm/imx233/regs/stmp3700/regs-emi.h
deleted file mode 100644
index 5244640f29..0000000000
--- a/firmware/target/arm/imx233/regs/stmp3700/regs-emi.h
+++ /dev/null
@@ -1,196 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3700:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__STMP3700__EMI__H__
-#define __HEADERGEN__STMP3700__EMI__H__
-
-#define REGS_EMI_BASE (0x80020000)
-
-#define REGS_EMI_VERSION "3.2.0"
-
-/**
- * Register: HW_EMI_CTRL
- * Address: 0
- * SCT: yes
-*/
-#define HW_EMI_CTRL                     (*(volatile unsigned long *)(REGS_EMI_BASE + 0x0 + 0x0))
-#define HW_EMI_CTRL_SET                 (*(volatile unsigned long *)(REGS_EMI_BASE + 0x0 + 0x4))
-#define HW_EMI_CTRL_CLR                 (*(volatile unsigned long *)(REGS_EMI_BASE + 0x0 + 0x8))
-#define HW_EMI_CTRL_TOG                 (*(volatile unsigned long *)(REGS_EMI_BASE + 0x0 + 0xc))
-#define BP_EMI_CTRL_SFTRST              31
-#define BM_EMI_CTRL_SFTRST              0x80000000
-#define BF_EMI_CTRL_SFTRST(v)           (((v) << 31) & 0x80000000)
-#define BP_EMI_CTRL_CLKGATE             30
-#define BM_EMI_CTRL_CLKGATE             0x40000000
-#define BF_EMI_CTRL_CLKGATE(v)          (((v) << 30) & 0x40000000)
-#define BP_EMI_CTRL_MEM_WIDTH           6
-#define BM_EMI_CTRL_MEM_WIDTH           0x40
-#define BF_EMI_CTRL_MEM_WIDTH(v)        (((v) << 6) & 0x40)
-#define BP_EMI_CTRL_WRITE_PROTECT       5
-#define BM_EMI_CTRL_WRITE_PROTECT       0x20
-#define BF_EMI_CTRL_WRITE_PROTECT(v)    (((v) << 5) & 0x20)
-#define BP_EMI_CTRL_RESET_OUT           4
-#define BM_EMI_CTRL_RESET_OUT           0x10
-#define BF_EMI_CTRL_RESET_OUT(v)        (((v) << 4) & 0x10)
-#define BP_EMI_CTRL_CE_SELECT           0
-#define BM_EMI_CTRL_CE_SELECT           0xf
-#define BV_EMI_CTRL_CE_SELECT__NONE     0x0
-#define BV_EMI_CTRL_CE_SELECT__CE0      0x1
-#define BV_EMI_CTRL_CE_SELECT__CE1      0x2
-#define BV_EMI_CTRL_CE_SELECT__CE2      0x4
-#define BV_EMI_CTRL_CE_SELECT__CE3      0x8
-#define BF_EMI_CTRL_CE_SELECT(v)        (((v) << 0) & 0xf)
-#define BF_EMI_CTRL_CE_SELECT_V(v)      ((BV_EMI_CTRL_CE_SELECT__##v << 0) & 0xf)
-
-/**
- * Register: HW_EMI_STAT
- * Address: 0x10
- * SCT: no
-*/
-#define HW_EMI_STAT                         (*(volatile unsigned long *)(REGS_EMI_BASE + 0x10))
-#define BP_EMI_STAT_DRAM_PRESENT            31
-#define BM_EMI_STAT_DRAM_PRESENT            0x80000000
-#define BF_EMI_STAT_DRAM_PRESENT(v)         (((v) << 31) & 0x80000000)
-#define BP_EMI_STAT_NOR_PRESENT             30
-#define BM_EMI_STAT_NOR_PRESENT             0x40000000
-#define BF_EMI_STAT_NOR_PRESENT(v)          (((v) << 30) & 0x40000000)
-#define BP_EMI_STAT_LARGE_DRAM_ENABLED      29
-#define BM_EMI_STAT_LARGE_DRAM_ENABLED      0x20000000
-#define BF_EMI_STAT_LARGE_DRAM_ENABLED(v)   (((v) << 29) & 0x20000000)
-#define BP_EMI_STAT_DRAM_HALTED             1
-#define BM_EMI_STAT_DRAM_HALTED             0x2
-#define BV_EMI_STAT_DRAM_HALTED__NOT_HALTED 0x0
-#define BV_EMI_STAT_DRAM_HALTED__HALTED     0x1
-#define BF_EMI_STAT_DRAM_HALTED(v)          (((v) << 1) & 0x2)
-#define BF_EMI_STAT_DRAM_HALTED_V(v)        ((BV_EMI_STAT_DRAM_HALTED__##v << 1) & 0x2)
-#define BP_EMI_STAT_NOR_BUSY                0
-#define BM_EMI_STAT_NOR_BUSY                0x1
-#define BV_EMI_STAT_NOR_BUSY__NOT_BUSY      0x0
-#define BV_EMI_STAT_NOR_BUSY__BUSY          0x1
-#define BF_EMI_STAT_NOR_BUSY(v)             (((v) << 0) & 0x1)
-#define BF_EMI_STAT_NOR_BUSY_V(v)           ((BV_EMI_STAT_NOR_BUSY__##v << 0) & 0x1)
-
-/**
- * Register: HW_EMI_TIME
- * Address: 0x20
- * SCT: yes
-*/
-#define HW_EMI_TIME         (*(volatile unsigned long *)(REGS_EMI_BASE + 0x20 + 0x0))
-#define HW_EMI_TIME_SET     (*(volatile unsigned long *)(REGS_EMI_BASE + 0x20 + 0x4))
-#define HW_EMI_TIME_CLR     (*(volatile unsigned long *)(REGS_EMI_BASE + 0x20 + 0x8))
-#define HW_EMI_TIME_TOG     (*(volatile unsigned long *)(REGS_EMI_BASE + 0x20 + 0xc))
-#define BP_EMI_TIME_THZ     24
-#define BM_EMI_TIME_THZ     0xf000000
-#define BF_EMI_TIME_THZ(v)  (((v) << 24) & 0xf000000)
-#define BP_EMI_TIME_TDH     16
-#define BM_EMI_TIME_TDH     0xf0000
-#define BF_EMI_TIME_TDH(v)  (((v) << 16) & 0xf0000)
-#define BP_EMI_TIME_TDS     8
-#define BM_EMI_TIME_TDS     0x1f00
-#define BF_EMI_TIME_TDS(v)  (((v) << 8) & 0x1f00)
-#define BP_EMI_TIME_TAS     0
-#define BM_EMI_TIME_TAS     0xf
-#define BF_EMI_TIME_TAS(v)  (((v) << 0) & 0xf)
-
-/**
- * Register: HW_EMI_DDR_TEST_MODE_CSR
- * Address: 0x30
- * SCT: yes
-*/
-#define HW_EMI_DDR_TEST_MODE_CSR            (*(volatile unsigned long *)(REGS_EMI_BASE + 0x30 + 0x0))
-#define HW_EMI_DDR_TEST_MODE_CSR_SET        (*(volatile unsigned long *)(REGS_EMI_BASE + 0x30 + 0x4))
-#define HW_EMI_DDR_TEST_MODE_CSR_CLR        (*(volatile unsigned long *)(REGS_EMI_BASE + 0x30 + 0x8))
-#define HW_EMI_DDR_TEST_MODE_CSR_TOG        (*(volatile unsigned long *)(REGS_EMI_BASE + 0x30 + 0xc))
-#define BP_EMI_DDR_TEST_MODE_CSR_DONE       1
-#define BM_EMI_DDR_TEST_MODE_CSR_DONE       0x2
-#define BF_EMI_DDR_TEST_MODE_CSR_DONE(v)    (((v) << 1) & 0x2)
-#define BP_EMI_DDR_TEST_MODE_CSR_START      0
-#define BM_EMI_DDR_TEST_MODE_CSR_START      0x1
-#define BF_EMI_DDR_TEST_MODE_CSR_START(v)   (((v) << 0) & 0x1)
-
-/**
- * Register: HW_EMI_DEBUG
- * Address: 0x80
- * SCT: no
-*/
-#define HW_EMI_DEBUG                (*(volatile unsigned long *)(REGS_EMI_BASE + 0x80))
-#define BP_EMI_DEBUG_NOR_STATE      0
-#define BM_EMI_DEBUG_NOR_STATE      0xf
-#define BF_EMI_DEBUG_NOR_STATE(v)   (((v) << 0) & 0xf)
-
-/**
- * Register: HW_EMI_DDR_TEST_MODE_STATUS0
- * Address: 0x90
- * SCT: no
-*/
-#define HW_EMI_DDR_TEST_MODE_STATUS0            (*(volatile unsigned long *)(REGS_EMI_BASE + 0x90))
-#define BP_EMI_DDR_TEST_MODE_STATUS0_ADDR0      0
-#define BM_EMI_DDR_TEST_MODE_STATUS0_ADDR0      0x1fff
-#define BF_EMI_DDR_TEST_MODE_STATUS0_ADDR0(v)   (((v) << 0) & 0x1fff)
-
-/**
- * Register: HW_EMI_DDR_TEST_MODE_STATUS1
- * Address: 0xa0
- * SCT: no
-*/
-#define HW_EMI_DDR_TEST_MODE_STATUS1            (*(volatile unsigned long *)(REGS_EMI_BASE + 0xa0))
-#define BP_EMI_DDR_TEST_MODE_STATUS1_ADDR1      0
-#define BM_EMI_DDR_TEST_MODE_STATUS1_ADDR1      0x1fff
-#define BF_EMI_DDR_TEST_MODE_STATUS1_ADDR1(v)   (((v) << 0) & 0x1fff)
-
-/**
- * Register: HW_EMI_DDR_TEST_MODE_STATUS2
- * Address: 0xb0
- * SCT: no
-*/
-#define HW_EMI_DDR_TEST_MODE_STATUS2            (*(volatile unsigned long *)(REGS_EMI_BASE + 0xb0))
-#define BP_EMI_DDR_TEST_MODE_STATUS2_DATA0      0
-#define BM_EMI_DDR_TEST_MODE_STATUS2_DATA0      0xffffffff
-#define BF_EMI_DDR_TEST_MODE_STATUS2_DATA0(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_EMI_DDR_TEST_MODE_STATUS3
- * Address: 0xc0
- * SCT: no
-*/
-#define HW_EMI_DDR_TEST_MODE_STATUS3            (*(volatile unsigned long *)(REGS_EMI_BASE + 0xc0))
-#define BP_EMI_DDR_TEST_MODE_STATUS3_DATA1      0
-#define BM_EMI_DDR_TEST_MODE_STATUS3_DATA1      0xffffffff
-#define BF_EMI_DDR_TEST_MODE_STATUS3_DATA1(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_EMI_VERSION
- * Address: 0xf0
- * SCT: no
-*/
-#define HW_EMI_VERSION          (*(volatile unsigned long *)(REGS_EMI_BASE + 0xf0))
-#define BP_EMI_VERSION_MAJOR    24
-#define BM_EMI_VERSION_MAJOR    0xff000000
-#define BF_EMI_VERSION_MAJOR(v) (((v) << 24) & 0xff000000)
-#define BP_EMI_VERSION_MINOR    16
-#define BM_EMI_VERSION_MINOR    0xff0000
-#define BF_EMI_VERSION_MINOR(v) (((v) << 16) & 0xff0000)
-#define BP_EMI_VERSION_STEP     0
-#define BM_EMI_VERSION_STEP     0xffff
-#define BF_EMI_VERSION_STEP(v)  (((v) << 0) & 0xffff)
-
-#endif /* __HEADERGEN__STMP3700__EMI__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-gpiomon.h b/firmware/target/arm/imx233/regs/stmp3700/regs-gpiomon.h
deleted file mode 100644
index 573d005fc0..0000000000
--- a/firmware/target/arm/imx233/regs/stmp3700/regs-gpiomon.h
+++ /dev/null
@@ -1,355 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3700:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__STMP3700__GPIOMON__H__
-#define __HEADERGEN__STMP3700__GPIOMON__H__
-
-#define REGS_GPIOMON_BASE (0x8003c300)
-
-#define REGS_GPIOMON_VERSION "3.2.0"
-
-/**
- * Register: HW_GPIOMON_BANK0_DATAIN
- * Address: 0
- * SCT: no
-*/
-#define HW_GPIOMON_BANK0_DATAIN         (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x0))
-#define BP_GPIOMON_BANK0_DATAIN_DATA    0
-#define BM_GPIOMON_BANK0_DATAIN_DATA    0xffffffff
-#define BF_GPIOMON_BANK0_DATAIN_DATA(v) (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_GPIOMON_BANK1_DATAIN
- * Address: 0x10
- * SCT: no
-*/
-#define HW_GPIOMON_BANK1_DATAIN         (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x10))
-#define BP_GPIOMON_BANK1_DATAIN_DATA    0
-#define BM_GPIOMON_BANK1_DATAIN_DATA    0xffffffff
-#define BF_GPIOMON_BANK1_DATAIN_DATA(v) (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_GPIOMON_BANK2_DATAIN
- * Address: 0x20
- * SCT: no
-*/
-#define HW_GPIOMON_BANK2_DATAIN         (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x20))
-#define BP_GPIOMON_BANK2_DATAIN_DATA    0
-#define BM_GPIOMON_BANK2_DATAIN_DATA    0xffffffff
-#define BF_GPIOMON_BANK2_DATAIN_DATA(v) (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_GPIOMON_BANK3_DATAIN
- * Address: 0x30
- * SCT: no
-*/
-#define HW_GPIOMON_BANK3_DATAIN         (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x30))
-#define BP_GPIOMON_BANK3_DATAIN_DATA    0
-#define BM_GPIOMON_BANK3_DATAIN_DATA    0xffffffff
-#define BF_GPIOMON_BANK3_DATAIN_DATA(v) (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_GPIOMON_BANK0_DATAOUT
- * Address: 0x40
- * SCT: yes
-*/
-#define HW_GPIOMON_BANK0_DATAOUT            (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x40 + 0x0))
-#define HW_GPIOMON_BANK0_DATAOUT_SET        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x40 + 0x4))
-#define HW_GPIOMON_BANK0_DATAOUT_CLR        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x40 + 0x8))
-#define HW_GPIOMON_BANK0_DATAOUT_TOG        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x40 + 0xc))
-#define BP_GPIOMON_BANK0_DATAOUT_DATA       0
-#define BM_GPIOMON_BANK0_DATAOUT_DATA       0xffffffff
-#define BF_GPIOMON_BANK0_DATAOUT_DATA(v)    (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_GPIOMON_BANK1_DATAOUT
- * Address: 0x50
- * SCT: yes
-*/
-#define HW_GPIOMON_BANK1_DATAOUT            (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x50 + 0x0))
-#define HW_GPIOMON_BANK1_DATAOUT_SET        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x50 + 0x4))
-#define HW_GPIOMON_BANK1_DATAOUT_CLR        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x50 + 0x8))
-#define HW_GPIOMON_BANK1_DATAOUT_TOG        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x50 + 0xc))
-#define BP_GPIOMON_BANK1_DATAOUT_DATA       0
-#define BM_GPIOMON_BANK1_DATAOUT_DATA       0xffffffff
-#define BF_GPIOMON_BANK1_DATAOUT_DATA(v)    (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_GPIOMON_BANK2_DATAOUT
- * Address: 0x60
- * SCT: yes
-*/
-#define HW_GPIOMON_BANK2_DATAOUT            (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x60 + 0x0))
-#define HW_GPIOMON_BANK2_DATAOUT_SET        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x60 + 0x4))
-#define HW_GPIOMON_BANK2_DATAOUT_CLR        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x60 + 0x8))
-#define HW_GPIOMON_BANK2_DATAOUT_TOG        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x60 + 0xc))
-#define BP_GPIOMON_BANK2_DATAOUT_DATA       0
-#define BM_GPIOMON_BANK2_DATAOUT_DATA       0xffffffff
-#define BF_GPIOMON_BANK2_DATAOUT_DATA(v)    (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_GPIOMON_BANK3_DATAOUT
- * Address: 0x70
- * SCT: yes
-*/
-#define HW_GPIOMON_BANK3_DATAOUT            (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x70 + 0x0))
-#define HW_GPIOMON_BANK3_DATAOUT_SET        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x70 + 0x4))
-#define HW_GPIOMON_BANK3_DATAOUT_CLR        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x70 + 0x8))
-#define HW_GPIOMON_BANK3_DATAOUT_TOG        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x70 + 0xc))
-#define BP_GPIOMON_BANK3_DATAOUT_DATA       0
-#define BM_GPIOMON_BANK3_DATAOUT_DATA       0xffffffff
-#define BF_GPIOMON_BANK3_DATAOUT_DATA(v)    (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_GPIOMON_BANK0_DATAOEN
- * Address: 0x80
- * SCT: yes
-*/
-#define HW_GPIOMON_BANK0_DATAOEN                    (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x80 + 0x0))
-#define HW_GPIOMON_BANK0_DATAOEN_SET                (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x80 + 0x4))
-#define HW_GPIOMON_BANK0_DATAOEN_CLR                (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x80 + 0x8))
-#define HW_GPIOMON_BANK0_DATAOEN_TOG                (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x80 + 0xc))
-#define BP_GPIOMON_BANK0_DATAOEN_OUTPUT_ENABLES     0
-#define BM_GPIOMON_BANK0_DATAOEN_OUTPUT_ENABLES     0xffffffff
-#define BF_GPIOMON_BANK0_DATAOEN_OUTPUT_ENABLES(v)  (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_GPIOMON_BANK1_DATAOEN
- * Address: 0x90
- * SCT: yes
-*/
-#define HW_GPIOMON_BANK1_DATAOEN                    (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x90 + 0x0))
-#define HW_GPIOMON_BANK1_DATAOEN_SET                (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x90 + 0x4))
-#define HW_GPIOMON_BANK1_DATAOEN_CLR                (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x90 + 0x8))
-#define HW_GPIOMON_BANK1_DATAOEN_TOG                (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x90 + 0xc))
-#define BP_GPIOMON_BANK1_DATAOEN_OUTPUT_ENABLES     0
-#define BM_GPIOMON_BANK1_DATAOEN_OUTPUT_ENABLES     0xffffffff
-#define BF_GPIOMON_BANK1_DATAOEN_OUTPUT_ENABLES(v)  (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_GPIOMON_BANK2_DATAOEN
- * Address: 0xa0
- * SCT: yes
-*/
-#define HW_GPIOMON_BANK2_DATAOEN                    (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xa0 + 0x0))
-#define HW_GPIOMON_BANK2_DATAOEN_SET                (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xa0 + 0x4))
-#define HW_GPIOMON_BANK2_DATAOEN_CLR                (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xa0 + 0x8))
-#define HW_GPIOMON_BANK2_DATAOEN_TOG                (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xa0 + 0xc))
-#define BP_GPIOMON_BANK2_DATAOEN_OUTPUT_ENABLES     0
-#define BM_GPIOMON_BANK2_DATAOEN_OUTPUT_ENABLES     0xffffffff
-#define BF_GPIOMON_BANK2_DATAOEN_OUTPUT_ENABLES(v)  (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_GPIOMON_BANK3_DATAOEN
- * Address: 0xb0
- * SCT: yes
-*/
-#define HW_GPIOMON_BANK3_DATAOEN                    (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xb0 + 0x0))
-#define HW_GPIOMON_BANK3_DATAOEN_SET                (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xb0 + 0x4))
-#define HW_GPIOMON_BANK3_DATAOEN_CLR                (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xb0 + 0x8))
-#define HW_GPIOMON_BANK3_DATAOEN_TOG                (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xb0 + 0xc))
-#define BP_GPIOMON_BANK3_DATAOEN_OUTPUT_ENABLES     0
-#define BM_GPIOMON_BANK3_DATAOEN_OUTPUT_ENABLES     0xffffffff
-#define BF_GPIOMON_BANK3_DATAOEN_OUTPUT_ENABLES(v)  (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_GPIOMON_CTRL
- * Address: 0xc0
- * SCT: yes
-*/
-#define HW_GPIOMON_CTRL                     (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xc0 + 0x0))
-#define HW_GPIOMON_CTRL_SET                 (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xc0 + 0x4))
-#define HW_GPIOMON_CTRL_CLR                 (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xc0 + 0x8))
-#define HW_GPIOMON_CTRL_TOG                 (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xc0 + 0xc))
-#define BP_GPIOMON_CTRL_RSRVD               4
-#define BM_GPIOMON_CTRL_RSRVD               0xfffffff0
-#define BF_GPIOMON_CTRL_RSRVD(v)            (((v) << 4) & 0xfffffff0)
-#define BP_GPIOMON_CTRL_PINMUX_ALT_RESET    3
-#define BM_GPIOMON_CTRL_PINMUX_ALT_RESET    0x8
-#define BF_GPIOMON_CTRL_PINMUX_ALT_RESET(v) (((v) << 3) & 0x8)
-#define BP_GPIOMON_CTRL_OEN_8MA             2
-#define BM_GPIOMON_CTRL_OEN_8MA             0x4
-#define BF_GPIOMON_CTRL_OEN_8MA(v)          (((v) << 2) & 0x4)
-#define BP_GPIOMON_CTRL_OEN_4MA             1
-#define BM_GPIOMON_CTRL_OEN_4MA             0x2
-#define BF_GPIOMON_CTRL_OEN_4MA(v)          (((v) << 1) & 0x2)
-#define BP_GPIOMON_CTRL_OEN_NAND            0
-#define BM_GPIOMON_CTRL_OEN_NAND            0x1
-#define BF_GPIOMON_CTRL_OEN_NAND(v)         (((v) << 0) & 0x1)
-
-/**
- * Register: HW_GPIOMON_ALT1_PINMUX_BANK0
- * Address: 0xd0
- * SCT: yes
-*/
-#define HW_GPIOMON_ALT1_PINMUX_BANK0            (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xd0 + 0x0))
-#define HW_GPIOMON_ALT1_PINMUX_BANK0_SET        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xd0 + 0x4))
-#define HW_GPIOMON_ALT1_PINMUX_BANK0_CLR        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xd0 + 0x8))
-#define HW_GPIOMON_ALT1_PINMUX_BANK0_TOG        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xd0 + 0xc))
-#define BP_GPIOMON_ALT1_PINMUX_BANK0_INDEX      0
-#define BM_GPIOMON_ALT1_PINMUX_BANK0_INDEX      0xffffffff
-#define BF_GPIOMON_ALT1_PINMUX_BANK0_INDEX(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_GPIOMON_ALT1_PINMUX_BANK1
- * Address: 0xe0
- * SCT: yes
-*/
-#define HW_GPIOMON_ALT1_PINMUX_BANK1            (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xe0 + 0x0))
-#define HW_GPIOMON_ALT1_PINMUX_BANK1_SET        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xe0 + 0x4))
-#define HW_GPIOMON_ALT1_PINMUX_BANK1_CLR        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xe0 + 0x8))
-#define HW_GPIOMON_ALT1_PINMUX_BANK1_TOG        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xe0 + 0xc))
-#define BP_GPIOMON_ALT1_PINMUX_BANK1_INDEX      0
-#define BM_GPIOMON_ALT1_PINMUX_BANK1_INDEX      0xffffffff
-#define BF_GPIOMON_ALT1_PINMUX_BANK1_INDEX(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_GPIOMON_ALT1_PINMUX_BANK2
- * Address: 0xf0
- * SCT: yes
-*/
-#define HW_GPIOMON_ALT1_PINMUX_BANK2            (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xf0 + 0x0))
-#define HW_GPIOMON_ALT1_PINMUX_BANK2_SET        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xf0 + 0x4))
-#define HW_GPIOMON_ALT1_PINMUX_BANK2_CLR        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xf0 + 0x8))
-#define HW_GPIOMON_ALT1_PINMUX_BANK2_TOG        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xf0 + 0xc))
-#define BP_GPIOMON_ALT1_PINMUX_BANK2_INDEX      0
-#define BM_GPIOMON_ALT1_PINMUX_BANK2_INDEX      0xffffffff
-#define BF_GPIOMON_ALT1_PINMUX_BANK2_INDEX(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_GPIOMON_ALT1_PINMUX_BANK3
- * Address: 0x100
- * SCT: yes
-*/
-#define HW_GPIOMON_ALT1_PINMUX_BANK3            (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x100 + 0x0))
-#define HW_GPIOMON_ALT1_PINMUX_BANK3_SET        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x100 + 0x4))
-#define HW_GPIOMON_ALT1_PINMUX_BANK3_CLR        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x100 + 0x8))
-#define HW_GPIOMON_ALT1_PINMUX_BANK3_TOG        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x100 + 0xc))
-#define BP_GPIOMON_ALT1_PINMUX_BANK3_INDEX      0
-#define BM_GPIOMON_ALT1_PINMUX_BANK3_INDEX      0xffffffff
-#define BF_GPIOMON_ALT1_PINMUX_BANK3_INDEX(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_GPIOMON_ALT2_PINMUX_BANK0
- * Address: 0x110
- * SCT: yes
-*/
-#define HW_GPIOMON_ALT2_PINMUX_BANK0            (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x110 + 0x0))
-#define HW_GPIOMON_ALT2_PINMUX_BANK0_SET        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x110 + 0x4))
-#define HW_GPIOMON_ALT2_PINMUX_BANK0_CLR        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x110 + 0x8))
-#define HW_GPIOMON_ALT2_PINMUX_BANK0_TOG        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x110 + 0xc))
-#define BP_GPIOMON_ALT2_PINMUX_BANK0_INDEX      0
-#define BM_GPIOMON_ALT2_PINMUX_BANK0_INDEX      0xffffffff
-#define BF_GPIOMON_ALT2_PINMUX_BANK0_INDEX(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_GPIOMON_ALT2_PINMUX_BANK1
- * Address: 0x120
- * SCT: yes
-*/
-#define HW_GPIOMON_ALT2_PINMUX_BANK1            (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x120 + 0x0))
-#define HW_GPIOMON_ALT2_PINMUX_BANK1_SET        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x120 + 0x4))
-#define HW_GPIOMON_ALT2_PINMUX_BANK1_CLR        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x120 + 0x8))
-#define HW_GPIOMON_ALT2_PINMUX_BANK1_TOG        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x120 + 0xc))
-#define BP_GPIOMON_ALT2_PINMUX_BANK1_INDEX      0
-#define BM_GPIOMON_ALT2_PINMUX_BANK1_INDEX      0xffffffff
-#define BF_GPIOMON_ALT2_PINMUX_BANK1_INDEX(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_GPIOMON_ALT2_PINMUX_BANK2
- * Address: 0x130
- * SCT: yes
-*/
-#define HW_GPIOMON_ALT2_PINMUX_BANK2            (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x130 + 0x0))
-#define HW_GPIOMON_ALT2_PINMUX_BANK2_SET        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x130 + 0x4))
-#define HW_GPIOMON_ALT2_PINMUX_BANK2_CLR        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x130 + 0x8))
-#define HW_GPIOMON_ALT2_PINMUX_BANK2_TOG        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x130 + 0xc))
-#define BP_GPIOMON_ALT2_PINMUX_BANK2_INDEX      0
-#define BM_GPIOMON_ALT2_PINMUX_BANK2_INDEX      0xffffffff
-#define BF_GPIOMON_ALT2_PINMUX_BANK2_INDEX(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_GPIOMON_ALT2_PINMUX_BANK3
- * Address: 0x140
- * SCT: yes
-*/
-#define HW_GPIOMON_ALT2_PINMUX_BANK3            (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x140 + 0x0))
-#define HW_GPIOMON_ALT2_PINMUX_BANK3_SET        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x140 + 0x4))
-#define HW_GPIOMON_ALT2_PINMUX_BANK3_CLR        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x140 + 0x8))
-#define HW_GPIOMON_ALT2_PINMUX_BANK3_TOG        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x140 + 0xc))
-#define BP_GPIOMON_ALT2_PINMUX_BANK3_INDEX      0
-#define BM_GPIOMON_ALT2_PINMUX_BANK3_INDEX      0xffffffff
-#define BF_GPIOMON_ALT2_PINMUX_BANK3_INDEX(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_GPIOMON_ALT3_PINMUX_BANK0
- * Address: 0x150
- * SCT: yes
-*/
-#define HW_GPIOMON_ALT3_PINMUX_BANK0            (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x150 + 0x0))
-#define HW_GPIOMON_ALT3_PINMUX_BANK0_SET        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x150 + 0x4))
-#define HW_GPIOMON_ALT3_PINMUX_BANK0_CLR        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x150 + 0x8))
-#define HW_GPIOMON_ALT3_PINMUX_BANK0_TOG        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x150 + 0xc))
-#define BP_GPIOMON_ALT3_PINMUX_BANK0_INDEX      0
-#define BM_GPIOMON_ALT3_PINMUX_BANK0_INDEX      0xffffffff
-#define BF_GPIOMON_ALT3_PINMUX_BANK0_INDEX(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_GPIOMON_ALT3_PINMUX_BANK1
- * Address: 0x160
- * SCT: yes
-*/
-#define HW_GPIOMON_ALT3_PINMUX_BANK1            (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x160 + 0x0))
-#define HW_GPIOMON_ALT3_PINMUX_BANK1_SET        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x160 + 0x4))
-#define HW_GPIOMON_ALT3_PINMUX_BANK1_CLR        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x160 + 0x8))
-#define HW_GPIOMON_ALT3_PINMUX_BANK1_TOG        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x160 + 0xc))
-#define BP_GPIOMON_ALT3_PINMUX_BANK1_INDEX      0
-#define BM_GPIOMON_ALT3_PINMUX_BANK1_INDEX      0xffffffff
-#define BF_GPIOMON_ALT3_PINMUX_BANK1_INDEX(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_GPIOMON_ALT3_PINMUX_BANK2
- * Address: 0x170
- * SCT: yes
-*/
-#define HW_GPIOMON_ALT3_PINMUX_BANK2            (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x170 + 0x0))
-#define HW_GPIOMON_ALT3_PINMUX_BANK2_SET        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x170 + 0x4))
-#define HW_GPIOMON_ALT3_PINMUX_BANK2_CLR        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x170 + 0x8))
-#define HW_GPIOMON_ALT3_PINMUX_BANK2_TOG        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x170 + 0xc))
-#define BP_GPIOMON_ALT3_PINMUX_BANK2_INDEX      0
-#define BM_GPIOMON_ALT3_PINMUX_BANK2_INDEX      0xffffffff
-#define BF_GPIOMON_ALT3_PINMUX_BANK2_INDEX(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_GPIOMON_ALT3_PINMUX_BANK3
- * Address: 0x180
- * SCT: yes
-*/
-#define HW_GPIOMON_ALT3_PINMUX_BANK3            (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x180 + 0x0))
-#define HW_GPIOMON_ALT3_PINMUX_BANK3_SET        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x180 + 0x4))
-#define HW_GPIOMON_ALT3_PINMUX_BANK3_CLR        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x180 + 0x8))
-#define HW_GPIOMON_ALT3_PINMUX_BANK3_TOG        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x180 + 0xc))
-#define BP_GPIOMON_ALT3_PINMUX_BANK3_INDEX      0
-#define BM_GPIOMON_ALT3_PINMUX_BANK3_INDEX      0xffffffff
-#define BF_GPIOMON_ALT3_PINMUX_BANK3_INDEX(v)   (((v) << 0) & 0xffffffff)
-
-#endif /* __HEADERGEN__STMP3700__GPIOMON__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-gpmi.h b/firmware/target/arm/imx233/regs/stmp3700/regs-gpmi.h
deleted file mode 100644
index 249b001d38..0000000000
--- a/firmware/target/arm/imx233/regs/stmp3700/regs-gpmi.h
+++ /dev/null
@@ -1,461 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3700:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__STMP3700__GPMI__H__
-#define __HEADERGEN__STMP3700__GPMI__H__
-
-#define REGS_GPMI_BASE (0x8000c000)
-
-#define REGS_GPMI_VERSION "3.2.0"
-
-/**
- * Register: HW_GPMI_CTRL0
- * Address: 0
- * SCT: yes
-*/
-#define HW_GPMI_CTRL0                                   (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x0 + 0x0))
-#define HW_GPMI_CTRL0_SET                               (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x0 + 0x4))
-#define HW_GPMI_CTRL0_CLR                               (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x0 + 0x8))
-#define HW_GPMI_CTRL0_TOG                               (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x0 + 0xc))
-#define BP_GPMI_CTRL0_SFTRST                            31
-#define BM_GPMI_CTRL0_SFTRST                            0x80000000
-#define BV_GPMI_CTRL0_SFTRST__RUN                       0x0
-#define BV_GPMI_CTRL0_SFTRST__RESET                     0x1
-#define BF_GPMI_CTRL0_SFTRST(v)                         (((v) << 31) & 0x80000000)
-#define BF_GPMI_CTRL0_SFTRST_V(v)                       ((BV_GPMI_CTRL0_SFTRST__##v << 31) & 0x80000000)
-#define BP_GPMI_CTRL0_CLKGATE                           30
-#define BM_GPMI_CTRL0_CLKGATE                           0x40000000
-#define BV_GPMI_CTRL0_CLKGATE__RUN                      0x0
-#define BV_GPMI_CTRL0_CLKGATE__NO_CLKS                  0x1
-#define BF_GPMI_CTRL0_CLKGATE(v)                        (((v) << 30) & 0x40000000)
-#define BF_GPMI_CTRL0_CLKGATE_V(v)                      ((BV_GPMI_CTRL0_CLKGATE__##v << 30) & 0x40000000)
-#define BP_GPMI_CTRL0_RUN                               29
-#define BM_GPMI_CTRL0_RUN                               0x20000000
-#define BV_GPMI_CTRL0_RUN__IDLE                         0x0
-#define BV_GPMI_CTRL0_RUN__BUSY                         0x1
-#define BF_GPMI_CTRL0_RUN(v)                            (((v) << 29) & 0x20000000)
-#define BF_GPMI_CTRL0_RUN_V(v)                          ((BV_GPMI_CTRL0_RUN__##v << 29) & 0x20000000)
-#define BP_GPMI_CTRL0_DEV_IRQ_EN                        28
-#define BM_GPMI_CTRL0_DEV_IRQ_EN                        0x10000000
-#define BF_GPMI_CTRL0_DEV_IRQ_EN(v)                     (((v) << 28) & 0x10000000)
-#define BP_GPMI_CTRL0_TIMEOUT_IRQ_EN                    27
-#define BM_GPMI_CTRL0_TIMEOUT_IRQ_EN                    0x8000000
-#define BF_GPMI_CTRL0_TIMEOUT_IRQ_EN(v)                 (((v) << 27) & 0x8000000)
-#define BP_GPMI_CTRL0_UDMA                              26
-#define BM_GPMI_CTRL0_UDMA                              0x4000000
-#define BV_GPMI_CTRL0_UDMA__DISABLED                    0x0
-#define BV_GPMI_CTRL0_UDMA__ENABLED                     0x1
-#define BF_GPMI_CTRL0_UDMA(v)                           (((v) << 26) & 0x4000000)
-#define BF_GPMI_CTRL0_UDMA_V(v)                         ((BV_GPMI_CTRL0_UDMA__##v << 26) & 0x4000000)
-#define BP_GPMI_CTRL0_COMMAND_MODE                      24
-#define BM_GPMI_CTRL0_COMMAND_MODE                      0x3000000
-#define BV_GPMI_CTRL0_COMMAND_MODE__WRITE               0x0
-#define BV_GPMI_CTRL0_COMMAND_MODE__READ                0x1
-#define BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE    0x2
-#define BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY      0x3
-#define BF_GPMI_CTRL0_COMMAND_MODE(v)                   (((v) << 24) & 0x3000000)
-#define BF_GPMI_CTRL0_COMMAND_MODE_V(v)                 ((BV_GPMI_CTRL0_COMMAND_MODE__##v << 24) & 0x3000000)
-#define BP_GPMI_CTRL0_WORD_LENGTH                       23
-#define BM_GPMI_CTRL0_WORD_LENGTH                       0x800000
-#define BV_GPMI_CTRL0_WORD_LENGTH__16_BIT               0x0
-#define BV_GPMI_CTRL0_WORD_LENGTH__8_BIT                0x1
-#define BF_GPMI_CTRL0_WORD_LENGTH(v)                    (((v) << 23) & 0x800000)
-#define BF_GPMI_CTRL0_WORD_LENGTH_V(v)                  ((BV_GPMI_CTRL0_WORD_LENGTH__##v << 23) & 0x800000)
-#define BP_GPMI_CTRL0_LOCK_CS                           22
-#define BM_GPMI_CTRL0_LOCK_CS                           0x400000
-#define BV_GPMI_CTRL0_LOCK_CS__DISABLED                 0x0
-#define BV_GPMI_CTRL0_LOCK_CS__ENABLED                  0x1
-#define BF_GPMI_CTRL0_LOCK_CS(v)                        (((v) << 22) & 0x400000)
-#define BF_GPMI_CTRL0_LOCK_CS_V(v)                      ((BV_GPMI_CTRL0_LOCK_CS__##v << 22) & 0x400000)
-#define BP_GPMI_CTRL0_CS                                20
-#define BM_GPMI_CTRL0_CS                                0x300000
-#define BF_GPMI_CTRL0_CS(v)                             (((v) << 20) & 0x300000)
-#define BP_GPMI_CTRL0_ADDRESS                           17
-#define BM_GPMI_CTRL0_ADDRESS                           0xe0000
-#define BV_GPMI_CTRL0_ADDRESS__NAND_DATA                0x0
-#define BV_GPMI_CTRL0_ADDRESS__NAND_CLE                 0x1
-#define BV_GPMI_CTRL0_ADDRESS__NAND_ALE                 0x2
-#define BF_GPMI_CTRL0_ADDRESS(v)                        (((v) << 17) & 0xe0000)
-#define BF_GPMI_CTRL0_ADDRESS_V(v)                      ((BV_GPMI_CTRL0_ADDRESS__##v << 17) & 0xe0000)
-#define BP_GPMI_CTRL0_ADDRESS_INCREMENT                 16
-#define BM_GPMI_CTRL0_ADDRESS_INCREMENT                 0x10000
-#define BV_GPMI_CTRL0_ADDRESS_INCREMENT__DISABLED       0x0
-#define BV_GPMI_CTRL0_ADDRESS_INCREMENT__ENABLED        0x1
-#define BF_GPMI_CTRL0_ADDRESS_INCREMENT(v)              (((v) << 16) & 0x10000)
-#define BF_GPMI_CTRL0_ADDRESS_INCREMENT_V(v)            ((BV_GPMI_CTRL0_ADDRESS_INCREMENT__##v << 16) & 0x10000)
-#define BP_GPMI_CTRL0_XFER_COUNT                        0
-#define BM_GPMI_CTRL0_XFER_COUNT                        0xffff
-#define BF_GPMI_CTRL0_XFER_COUNT(v)                     (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_GPMI_COMPARE
- * Address: 0x10
- * SCT: no
-*/
-#define HW_GPMI_COMPARE                 (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x10))
-#define BP_GPMI_COMPARE_MASK            16
-#define BM_GPMI_COMPARE_MASK            0xffff0000
-#define BF_GPMI_COMPARE_MASK(v)         (((v) << 16) & 0xffff0000)
-#define BP_GPMI_COMPARE_REFERENCE       0
-#define BM_GPMI_COMPARE_REFERENCE       0xffff
-#define BF_GPMI_COMPARE_REFERENCE(v)    (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_GPMI_ECCCTRL
- * Address: 0x20
- * SCT: yes
-*/
-#define HW_GPMI_ECCCTRL                         (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x20 + 0x0))
-#define HW_GPMI_ECCCTRL_SET                     (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x20 + 0x4))
-#define HW_GPMI_ECCCTRL_CLR                     (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x20 + 0x8))
-#define HW_GPMI_ECCCTRL_TOG                     (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x20 + 0xc))
-#define BP_GPMI_ECCCTRL_HANDLE                  16
-#define BM_GPMI_ECCCTRL_HANDLE                  0xffff0000
-#define BF_GPMI_ECCCTRL_HANDLE(v)               (((v) << 16) & 0xffff0000)
-#define BP_GPMI_ECCCTRL_ECC_CMD                 13
-#define BM_GPMI_ECCCTRL_ECC_CMD                 0x6000
-#define BV_GPMI_ECCCTRL_ECC_CMD__DECODE_4_BIT   0x0
-#define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE_4_BIT   0x1
-#define BV_GPMI_ECCCTRL_ECC_CMD__DECODE_8_BIT   0x2
-#define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE_8_BIT   0x3
-#define BF_GPMI_ECCCTRL_ECC_CMD(v)              (((v) << 13) & 0x6000)
-#define BF_GPMI_ECCCTRL_ECC_CMD_V(v)            ((BV_GPMI_ECCCTRL_ECC_CMD__##v << 13) & 0x6000)
-#define BP_GPMI_ECCCTRL_ENABLE_ECC              12
-#define BM_GPMI_ECCCTRL_ENABLE_ECC              0x1000
-#define BV_GPMI_ECCCTRL_ENABLE_ECC__ENABLE      0x1
-#define BV_GPMI_ECCCTRL_ENABLE_ECC__DISABLE     0x0
-#define BF_GPMI_ECCCTRL_ENABLE_ECC(v)           (((v) << 12) & 0x1000)
-#define BF_GPMI_ECCCTRL_ENABLE_ECC_V(v)         ((BV_GPMI_ECCCTRL_ENABLE_ECC__##v << 12) & 0x1000)
-#define BP_GPMI_ECCCTRL_BUFFER_MASK             0
-#define BM_GPMI_ECCCTRL_BUFFER_MASK             0x1ff
-#define BV_GPMI_ECCCTRL_BUFFER_MASK__AUXILIARY  0x100
-#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER7    0x80
-#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER6    0x40
-#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER5    0x20
-#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER4    0x10
-#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER3    0x8
-#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER2    0x4
-#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER1    0x2
-#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER0    0x1
-#define BF_GPMI_ECCCTRL_BUFFER_MASK(v)          (((v) << 0) & 0x1ff)
-#define BF_GPMI_ECCCTRL_BUFFER_MASK_V(v)        ((BV_GPMI_ECCCTRL_BUFFER_MASK__##v << 0) & 0x1ff)
-
-/**
- * Register: HW_GPMI_ECCCOUNT
- * Address: 0x30
- * SCT: no
-*/
-#define HW_GPMI_ECCCOUNT            (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x30))
-#define BP_GPMI_ECCCOUNT_COUNT      0
-#define BM_GPMI_ECCCOUNT_COUNT      0xffff
-#define BF_GPMI_ECCCOUNT_COUNT(v)   (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_GPMI_PAYLOAD
- * Address: 0x40
- * SCT: no
-*/
-#define HW_GPMI_PAYLOAD             (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x40))
-#define BP_GPMI_PAYLOAD_ADDRESS     2
-#define BM_GPMI_PAYLOAD_ADDRESS     0xfffffffc
-#define BF_GPMI_PAYLOAD_ADDRESS(v)  (((v) << 2) & 0xfffffffc)
-
-/**
- * Register: HW_GPMI_AUXILIARY
- * Address: 0x50
- * SCT: no
-*/
-#define HW_GPMI_AUXILIARY               (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x50))
-#define BP_GPMI_AUXILIARY_ADDRESS       2
-#define BM_GPMI_AUXILIARY_ADDRESS       0xfffffffc
-#define BF_GPMI_AUXILIARY_ADDRESS(v)    (((v) << 2) & 0xfffffffc)
-
-/**
- * Register: HW_GPMI_CTRL1
- * Address: 0x60
- * SCT: yes
-*/
-#define HW_GPMI_CTRL1                                   (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x60 + 0x0))
-#define HW_GPMI_CTRL1_SET                               (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x60 + 0x4))
-#define HW_GPMI_CTRL1_CLR                               (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x60 + 0x8))
-#define HW_GPMI_CTRL1_TOG                               (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x60 + 0xc))
-#define BP_GPMI_CTRL1_DSAMPLE_TIME                      12
-#define BM_GPMI_CTRL1_DSAMPLE_TIME                      0x7000
-#define BF_GPMI_CTRL1_DSAMPLE_TIME(v)                   (((v) << 12) & 0x7000)
-#define BP_GPMI_CTRL1_DMA2ECC_MODE                      11
-#define BM_GPMI_CTRL1_DMA2ECC_MODE                      0x800
-#define BF_GPMI_CTRL1_DMA2ECC_MODE(v)                   (((v) << 11) & 0x800)
-#define BP_GPMI_CTRL1_DEV_IRQ                           10
-#define BM_GPMI_CTRL1_DEV_IRQ                           0x400
-#define BF_GPMI_CTRL1_DEV_IRQ(v)                        (((v) << 10) & 0x400)
-#define BP_GPMI_CTRL1_TIMEOUT_IRQ                       9
-#define BM_GPMI_CTRL1_TIMEOUT_IRQ                       0x200
-#define BF_GPMI_CTRL1_TIMEOUT_IRQ(v)                    (((v) << 9) & 0x200)
-#define BP_GPMI_CTRL1_BURST_EN                          8
-#define BM_GPMI_CTRL1_BURST_EN                          0x100
-#define BF_GPMI_CTRL1_BURST_EN(v)                       (((v) << 8) & 0x100)
-#define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY3             7
-#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY3             0x80
-#define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY3(v)          (((v) << 7) & 0x80)
-#define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY2             6
-#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY2             0x40
-#define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY2(v)          (((v) << 6) & 0x40)
-#define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY1             5
-#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY1             0x20
-#define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY1(v)          (((v) << 5) & 0x20)
-#define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY0             4
-#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY0             0x10
-#define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY0(v)          (((v) << 4) & 0x10)
-#define BP_GPMI_CTRL1_DEV_RESET                         3
-#define BM_GPMI_CTRL1_DEV_RESET                         0x8
-#define BV_GPMI_CTRL1_DEV_RESET__ENABLED                0x0
-#define BV_GPMI_CTRL1_DEV_RESET__DISABLED               0x1
-#define BF_GPMI_CTRL1_DEV_RESET(v)                      (((v) << 3) & 0x8)
-#define BF_GPMI_CTRL1_DEV_RESET_V(v)                    ((BV_GPMI_CTRL1_DEV_RESET__##v << 3) & 0x8)
-#define BP_GPMI_CTRL1_ATA_IRQRDY_POLARITY               2
-#define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY               0x4
-#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVELOW    0x0
-#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVEHIGH   0x1
-#define BF_GPMI_CTRL1_ATA_IRQRDY_POLARITY(v)            (((v) << 2) & 0x4)
-#define BF_GPMI_CTRL1_ATA_IRQRDY_POLARITY_V(v)          ((BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__##v << 2) & 0x4)
-#define BP_GPMI_CTRL1_CAMERA_MODE                       1
-#define BM_GPMI_CTRL1_CAMERA_MODE                       0x2
-#define BF_GPMI_CTRL1_CAMERA_MODE(v)                    (((v) << 1) & 0x2)
-#define BP_GPMI_CTRL1_GPMI_MODE                         0
-#define BM_GPMI_CTRL1_GPMI_MODE                         0x1
-#define BV_GPMI_CTRL1_GPMI_MODE__NAND                   0x0
-#define BV_GPMI_CTRL1_GPMI_MODE__ATA                    0x1
-#define BF_GPMI_CTRL1_GPMI_MODE(v)                      (((v) << 0) & 0x1)
-#define BF_GPMI_CTRL1_GPMI_MODE_V(v)                    ((BV_GPMI_CTRL1_GPMI_MODE__##v << 0) & 0x1)
-
-/**
- * Register: HW_GPMI_TIMING0
- * Address: 0x70
- * SCT: no
-*/
-#define HW_GPMI_TIMING0                     (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x70))
-#define BP_GPMI_TIMING0_ADDRESS_SETUP       16
-#define BM_GPMI_TIMING0_ADDRESS_SETUP       0xff0000
-#define BF_GPMI_TIMING0_ADDRESS_SETUP(v)    (((v) << 16) & 0xff0000)
-#define BP_GPMI_TIMING0_DATA_HOLD           8
-#define BM_GPMI_TIMING0_DATA_HOLD           0xff00
-#define BF_GPMI_TIMING0_DATA_HOLD(v)        (((v) << 8) & 0xff00)
-#define BP_GPMI_TIMING0_DATA_SETUP          0
-#define BM_GPMI_TIMING0_DATA_SETUP          0xff
-#define BF_GPMI_TIMING0_DATA_SETUP(v)       (((v) << 0) & 0xff)
-
-/**
- * Register: HW_GPMI_TIMING1
- * Address: 0x80
- * SCT: no
-*/
-#define HW_GPMI_TIMING1                         (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x80))
-#define BP_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT     16
-#define BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT     0xffff0000
-#define BF_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(v)  (((v) << 16) & 0xffff0000)
-
-/**
- * Register: HW_GPMI_TIMING2
- * Address: 0x90
- * SCT: no
-*/
-#define HW_GPMI_TIMING2                 (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x90))
-#define BP_GPMI_TIMING2_UDMA_TRP        24
-#define BM_GPMI_TIMING2_UDMA_TRP        0xff000000
-#define BF_GPMI_TIMING2_UDMA_TRP(v)     (((v) << 24) & 0xff000000)
-#define BP_GPMI_TIMING2_UDMA_ENV        16
-#define BM_GPMI_TIMING2_UDMA_ENV        0xff0000
-#define BF_GPMI_TIMING2_UDMA_ENV(v)     (((v) << 16) & 0xff0000)
-#define BP_GPMI_TIMING2_UDMA_HOLD       8
-#define BM_GPMI_TIMING2_UDMA_HOLD       0xff00
-#define BF_GPMI_TIMING2_UDMA_HOLD(v)    (((v) << 8) & 0xff00)
-#define BP_GPMI_TIMING2_UDMA_SETUP      0
-#define BM_GPMI_TIMING2_UDMA_SETUP      0xff
-#define BF_GPMI_TIMING2_UDMA_SETUP(v)   (((v) << 0) & 0xff)
-
-/**
- * Register: HW_GPMI_DATA
- * Address: 0xa0
- * SCT: no
-*/
-#define HW_GPMI_DATA            (*(volatile unsigned long *)(REGS_GPMI_BASE + 0xa0))
-#define BP_GPMI_DATA_DATA       0
-#define BM_GPMI_DATA_DATA       0xffffffff
-#define BF_GPMI_DATA_DATA(v)    (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_GPMI_STAT
- * Address: 0xb0
- * SCT: no
-*/
-#define HW_GPMI_STAT                        (*(volatile unsigned long *)(REGS_GPMI_BASE + 0xb0))
-#define BP_GPMI_STAT_PRESENT                31
-#define BM_GPMI_STAT_PRESENT                0x80000000
-#define BV_GPMI_STAT_PRESENT__UNAVAILABLE   0x0
-#define BV_GPMI_STAT_PRESENT__AVAILABLE     0x1
-#define BF_GPMI_STAT_PRESENT(v)             (((v) << 31) & 0x80000000)
-#define BF_GPMI_STAT_PRESENT_V(v)           ((BV_GPMI_STAT_PRESENT__##v << 31) & 0x80000000)
-#define BP_GPMI_STAT_RDY_TIMEOUT            8
-#define BM_GPMI_STAT_RDY_TIMEOUT            0xf00
-#define BF_GPMI_STAT_RDY_TIMEOUT(v)         (((v) << 8) & 0xf00)
-#define BP_GPMI_STAT_ATA_IRQ                7
-#define BM_GPMI_STAT_ATA_IRQ                0x80
-#define BF_GPMI_STAT_ATA_IRQ(v)             (((v) << 7) & 0x80)
-#define BP_GPMI_STAT_INVALID_BUFFER_MASK    6
-#define BM_GPMI_STAT_INVALID_BUFFER_MASK    0x40
-#define BF_GPMI_STAT_INVALID_BUFFER_MASK(v) (((v) << 6) & 0x40)
-#define BP_GPMI_STAT_FIFO_EMPTY             5
-#define BM_GPMI_STAT_FIFO_EMPTY             0x20
-#define BV_GPMI_STAT_FIFO_EMPTY__NOT_EMPTY  0x0
-#define BV_GPMI_STAT_FIFO_EMPTY__EMPTY      0x1
-#define BF_GPMI_STAT_FIFO_EMPTY(v)          (((v) << 5) & 0x20)
-#define BF_GPMI_STAT_FIFO_EMPTY_V(v)        ((BV_GPMI_STAT_FIFO_EMPTY__##v << 5) & 0x20)
-#define BP_GPMI_STAT_FIFO_FULL              4
-#define BM_GPMI_STAT_FIFO_FULL              0x10
-#define BV_GPMI_STAT_FIFO_FULL__NOT_FULL    0x0
-#define BV_GPMI_STAT_FIFO_FULL__FULL        0x1
-#define BF_GPMI_STAT_FIFO_FULL(v)           (((v) << 4) & 0x10)
-#define BF_GPMI_STAT_FIFO_FULL_V(v)         ((BV_GPMI_STAT_FIFO_FULL__##v << 4) & 0x10)
-#define BP_GPMI_STAT_DEV3_ERROR             3
-#define BM_GPMI_STAT_DEV3_ERROR             0x8
-#define BF_GPMI_STAT_DEV3_ERROR(v)          (((v) << 3) & 0x8)
-#define BP_GPMI_STAT_DEV2_ERROR             2
-#define BM_GPMI_STAT_DEV2_ERROR             0x4
-#define BF_GPMI_STAT_DEV2_ERROR(v)          (((v) << 2) & 0x4)
-#define BP_GPMI_STAT_DEV1_ERROR             1
-#define BM_GPMI_STAT_DEV1_ERROR             0x2
-#define BF_GPMI_STAT_DEV1_ERROR(v)          (((v) << 1) & 0x2)
-#define BP_GPMI_STAT_DEV0_ERROR             0
-#define BM_GPMI_STAT_DEV0_ERROR             0x1
-#define BF_GPMI_STAT_DEV0_ERROR(v)          (((v) << 0) & 0x1)
-
-/**
- * Register: HW_GPMI_DEBUG
- * Address: 0xc0
- * SCT: no
-*/
-#define HW_GPMI_DEBUG                           (*(volatile unsigned long *)(REGS_GPMI_BASE + 0xc0))
-#define BP_GPMI_DEBUG_READY3                    31
-#define BM_GPMI_DEBUG_READY3                    0x80000000
-#define BF_GPMI_DEBUG_READY3(v)                 (((v) << 31) & 0x80000000)
-#define BP_GPMI_DEBUG_READY2                    30
-#define BM_GPMI_DEBUG_READY2                    0x40000000
-#define BF_GPMI_DEBUG_READY2(v)                 (((v) << 30) & 0x40000000)
-#define BP_GPMI_DEBUG_READY1                    29
-#define BM_GPMI_DEBUG_READY1                    0x20000000
-#define BF_GPMI_DEBUG_READY1(v)                 (((v) << 29) & 0x20000000)
-#define BP_GPMI_DEBUG_READY0                    28
-#define BM_GPMI_DEBUG_READY0                    0x10000000
-#define BF_GPMI_DEBUG_READY0(v)                 (((v) << 28) & 0x10000000)
-#define BP_GPMI_DEBUG_WAIT_FOR_READY_END3       27
-#define BM_GPMI_DEBUG_WAIT_FOR_READY_END3       0x8000000
-#define BF_GPMI_DEBUG_WAIT_FOR_READY_END3(v)    (((v) << 27) & 0x8000000)
-#define BP_GPMI_DEBUG_WAIT_FOR_READY_END2       26
-#define BM_GPMI_DEBUG_WAIT_FOR_READY_END2       0x4000000
-#define BF_GPMI_DEBUG_WAIT_FOR_READY_END2(v)    (((v) << 26) & 0x4000000)
-#define BP_GPMI_DEBUG_WAIT_FOR_READY_END1       25
-#define BM_GPMI_DEBUG_WAIT_FOR_READY_END1       0x2000000
-#define BF_GPMI_DEBUG_WAIT_FOR_READY_END1(v)    (((v) << 25) & 0x2000000)
-#define BP_GPMI_DEBUG_WAIT_FOR_READY_END0       24
-#define BM_GPMI_DEBUG_WAIT_FOR_READY_END0       0x1000000
-#define BF_GPMI_DEBUG_WAIT_FOR_READY_END0(v)    (((v) << 24) & 0x1000000)
-#define BP_GPMI_DEBUG_SENSE3                    23
-#define BM_GPMI_DEBUG_SENSE3                    0x800000
-#define BF_GPMI_DEBUG_SENSE3(v)                 (((v) << 23) & 0x800000)
-#define BP_GPMI_DEBUG_SENSE2                    22
-#define BM_GPMI_DEBUG_SENSE2                    0x400000
-#define BF_GPMI_DEBUG_SENSE2(v)                 (((v) << 22) & 0x400000)
-#define BP_GPMI_DEBUG_SENSE1                    21
-#define BM_GPMI_DEBUG_SENSE1                    0x200000
-#define BF_GPMI_DEBUG_SENSE1(v)                 (((v) << 21) & 0x200000)
-#define BP_GPMI_DEBUG_SENSE0                    20
-#define BM_GPMI_DEBUG_SENSE0                    0x100000
-#define BF_GPMI_DEBUG_SENSE0(v)                 (((v) << 20) & 0x100000)
-#define BP_GPMI_DEBUG_DMAREQ3                   19
-#define BM_GPMI_DEBUG_DMAREQ3                   0x80000
-#define BF_GPMI_DEBUG_DMAREQ3(v)                (((v) << 19) & 0x80000)
-#define BP_GPMI_DEBUG_DMAREQ2                   18
-#define BM_GPMI_DEBUG_DMAREQ2                   0x40000
-#define BF_GPMI_DEBUG_DMAREQ2(v)                (((v) << 18) & 0x40000)
-#define BP_GPMI_DEBUG_DMAREQ1                   17
-#define BM_GPMI_DEBUG_DMAREQ1                   0x20000
-#define BF_GPMI_DEBUG_DMAREQ1(v)                (((v) << 17) & 0x20000)
-#define BP_GPMI_DEBUG_DMAREQ0                   16
-#define BM_GPMI_DEBUG_DMAREQ0                   0x10000
-#define BF_GPMI_DEBUG_DMAREQ0(v)                (((v) << 16) & 0x10000)
-#define BP_GPMI_DEBUG_CMD_END                   12
-#define BM_GPMI_DEBUG_CMD_END                   0xf000
-#define BF_GPMI_DEBUG_CMD_END(v)                (((v) << 12) & 0xf000)
-#define BP_GPMI_DEBUG_UDMA_STATE                8
-#define BM_GPMI_DEBUG_UDMA_STATE                0xf00
-#define BF_GPMI_DEBUG_UDMA_STATE(v)             (((v) << 8) & 0xf00)
-#define BP_GPMI_DEBUG_BUSY                      7
-#define BM_GPMI_DEBUG_BUSY                      0x80
-#define BV_GPMI_DEBUG_BUSY__DISABLED            0x0
-#define BV_GPMI_DEBUG_BUSY__ENABLED             0x1
-#define BF_GPMI_DEBUG_BUSY(v)                   (((v) << 7) & 0x80)
-#define BF_GPMI_DEBUG_BUSY_V(v)                 ((BV_GPMI_DEBUG_BUSY__##v << 7) & 0x80)
-#define BP_GPMI_DEBUG_PIN_STATE                 4
-#define BM_GPMI_DEBUG_PIN_STATE                 0x70
-#define BV_GPMI_DEBUG_PIN_STATE__PSM_IDLE       0x0
-#define BV_GPMI_DEBUG_PIN_STATE__PSM_BYTCNT     0x1
-#define BV_GPMI_DEBUG_PIN_STATE__PSM_ADDR       0x2
-#define BV_GPMI_DEBUG_PIN_STATE__PSM_STALL      0x3
-#define BV_GPMI_DEBUG_PIN_STATE__PSM_STROBE     0x4
-#define BV_GPMI_DEBUG_PIN_STATE__PSM_ATARDY     0x5
-#define BV_GPMI_DEBUG_PIN_STATE__PSM_DHOLD      0x6
-#define BV_GPMI_DEBUG_PIN_STATE__PSM_DONE       0x7
-#define BF_GPMI_DEBUG_PIN_STATE(v)              (((v) << 4) & 0x70)
-#define BF_GPMI_DEBUG_PIN_STATE_V(v)            ((BV_GPMI_DEBUG_PIN_STATE__##v << 4) & 0x70)
-#define BP_GPMI_DEBUG_MAIN_STATE                0
-#define BM_GPMI_DEBUG_MAIN_STATE                0xf
-#define BV_GPMI_DEBUG_MAIN_STATE__MSM_IDLE      0x0
-#define BV_GPMI_DEBUG_MAIN_STATE__MSM_BYTCNT    0x1
-#define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFE    0x2
-#define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFR    0x3
-#define BV_GPMI_DEBUG_MAIN_STATE__MSM_DMAREQ    0x4
-#define BV_GPMI_DEBUG_MAIN_STATE__MSM_DMAACK    0x5
-#define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFF    0x6
-#define BV_GPMI_DEBUG_MAIN_STATE__MSM_LDFIFO    0x7
-#define BV_GPMI_DEBUG_MAIN_STATE__MSM_LDDMAR    0x8
-#define BV_GPMI_DEBUG_MAIN_STATE__MSM_RDCMP     0x9
-#define BV_GPMI_DEBUG_MAIN_STATE__MSM_DONE      0xa
-#define BF_GPMI_DEBUG_MAIN_STATE(v)             (((v) << 0) & 0xf)
-#define BF_GPMI_DEBUG_MAIN_STATE_V(v)           ((BV_GPMI_DEBUG_MAIN_STATE__##v << 0) & 0xf)
-
-/**
- * Register: HW_GPMI_VERSION
- * Address: 0xd0
- * SCT: no
-*/
-#define HW_GPMI_VERSION             (*(volatile unsigned long *)(REGS_GPMI_BASE + 0xd0))
-#define BP_GPMI_VERSION_MAJOR       24
-#define BM_GPMI_VERSION_MAJOR       0xff000000
-#define BF_GPMI_VERSION_MAJOR(v)    (((v) << 24) & 0xff000000)
-#define BP_GPMI_VERSION_MINOR       16
-#define BM_GPMI_VERSION_MINOR       0xff0000
-#define BF_GPMI_VERSION_MINOR(v)    (((v) << 16) & 0xff0000)
-#define BP_GPMI_VERSION_STEP        0
-#define BM_GPMI_VERSION_STEP        0xffff
-#define BF_GPMI_VERSION_STEP(v)     (((v) << 0) & 0xffff)
-
-#endif /* __HEADERGEN__STMP3700__GPMI__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-i2c.h b/firmware/target/arm/imx233/regs/stmp3700/regs-i2c.h
deleted file mode 100644
index 2172a615de..0000000000
--- a/firmware/target/arm/imx233/regs/stmp3700/regs-i2c.h
+++ /dev/null
@@ -1,537 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3700:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__STMP3700__I2C__H__
-#define __HEADERGEN__STMP3700__I2C__H__
-
-#define REGS_I2C_BASE (0x80058000)
-
-#define REGS_I2C_VERSION "3.2.0"
-
-/**
- * Register: HW_I2C_CTRL0
- * Address: 0
- * SCT: yes
-*/
-#define HW_I2C_CTRL0                                (*(volatile unsigned long *)(REGS_I2C_BASE + 0x0 + 0x0))
-#define HW_I2C_CTRL0_SET                            (*(volatile unsigned long *)(REGS_I2C_BASE + 0x0 + 0x4))
-#define HW_I2C_CTRL0_CLR                            (*(volatile unsigned long *)(REGS_I2C_BASE + 0x0 + 0x8))
-#define HW_I2C_CTRL0_TOG                            (*(volatile unsigned long *)(REGS_I2C_BASE + 0x0 + 0xc))
-#define BP_I2C_CTRL0_SFTRST                         31
-#define BM_I2C_CTRL0_SFTRST                         0x80000000
-#define BV_I2C_CTRL0_SFTRST__RUN                    0x0
-#define BV_I2C_CTRL0_SFTRST__RESET                  0x1
-#define BF_I2C_CTRL0_SFTRST(v)                      (((v) << 31) & 0x80000000)
-#define BF_I2C_CTRL0_SFTRST_V(v)                    ((BV_I2C_CTRL0_SFTRST__##v << 31) & 0x80000000)
-#define BP_I2C_CTRL0_CLKGATE                        30
-#define BM_I2C_CTRL0_CLKGATE                        0x40000000
-#define BV_I2C_CTRL0_CLKGATE__RUN                   0x0
-#define BV_I2C_CTRL0_CLKGATE__NO_CLKS               0x1
-#define BF_I2C_CTRL0_CLKGATE(v)                     (((v) << 30) & 0x40000000)
-#define BF_I2C_CTRL0_CLKGATE_V(v)                   ((BV_I2C_CTRL0_CLKGATE__##v << 30) & 0x40000000)
-#define BP_I2C_CTRL0_RUN                            29
-#define BM_I2C_CTRL0_RUN                            0x20000000
-#define BV_I2C_CTRL0_RUN__HALT                      0x0
-#define BV_I2C_CTRL0_RUN__RUN                       0x1
-#define BF_I2C_CTRL0_RUN(v)                         (((v) << 29) & 0x20000000)
-#define BF_I2C_CTRL0_RUN_V(v)                       ((BV_I2C_CTRL0_RUN__##v << 29) & 0x20000000)
-#define BP_I2C_CTRL0_PRE_ACK                        27
-#define BM_I2C_CTRL0_PRE_ACK                        0x8000000
-#define BF_I2C_CTRL0_PRE_ACK(v)                     (((v) << 27) & 0x8000000)
-#define BP_I2C_CTRL0_ACKNOWLEDGE                    26
-#define BM_I2C_CTRL0_ACKNOWLEDGE                    0x4000000
-#define BV_I2C_CTRL0_ACKNOWLEDGE__SNAK              0x0
-#define BV_I2C_CTRL0_ACKNOWLEDGE__ACK               0x1
-#define BF_I2C_CTRL0_ACKNOWLEDGE(v)                 (((v) << 26) & 0x4000000)
-#define BF_I2C_CTRL0_ACKNOWLEDGE_V(v)               ((BV_I2C_CTRL0_ACKNOWLEDGE__##v << 26) & 0x4000000)
-#define BP_I2C_CTRL0_SEND_NAK_ON_LAST               25
-#define BM_I2C_CTRL0_SEND_NAK_ON_LAST               0x2000000
-#define BV_I2C_CTRL0_SEND_NAK_ON_LAST__ACK_IT       0x0
-#define BV_I2C_CTRL0_SEND_NAK_ON_LAST__NAK_IT       0x1
-#define BF_I2C_CTRL0_SEND_NAK_ON_LAST(v)            (((v) << 25) & 0x2000000)
-#define BF_I2C_CTRL0_SEND_NAK_ON_LAST_V(v)          ((BV_I2C_CTRL0_SEND_NAK_ON_LAST__##v << 25) & 0x2000000)
-#define BP_I2C_CTRL0_PIO_MODE                       24
-#define BM_I2C_CTRL0_PIO_MODE                       0x1000000
-#define BF_I2C_CTRL0_PIO_MODE(v)                    (((v) << 24) & 0x1000000)
-#define BP_I2C_CTRL0_MULTI_MASTER                   23
-#define BM_I2C_CTRL0_MULTI_MASTER                   0x800000
-#define BV_I2C_CTRL0_MULTI_MASTER__SINGLE           0x0
-#define BV_I2C_CTRL0_MULTI_MASTER__MULTIPLE         0x1
-#define BF_I2C_CTRL0_MULTI_MASTER(v)                (((v) << 23) & 0x800000)
-#define BF_I2C_CTRL0_MULTI_MASTER_V(v)              ((BV_I2C_CTRL0_MULTI_MASTER__##v << 23) & 0x800000)
-#define BP_I2C_CTRL0_CLOCK_HELD                     22
-#define BM_I2C_CTRL0_CLOCK_HELD                     0x400000
-#define BV_I2C_CTRL0_CLOCK_HELD__RELEASE            0x0
-#define BV_I2C_CTRL0_CLOCK_HELD__HELD_LOW           0x1
-#define BF_I2C_CTRL0_CLOCK_HELD(v)                  (((v) << 22) & 0x400000)
-#define BF_I2C_CTRL0_CLOCK_HELD_V(v)                ((BV_I2C_CTRL0_CLOCK_HELD__##v << 22) & 0x400000)
-#define BP_I2C_CTRL0_RETAIN_CLOCK                   21
-#define BM_I2C_CTRL0_RETAIN_CLOCK                   0x200000
-#define BV_I2C_CTRL0_RETAIN_CLOCK__RELEASE          0x0
-#define BV_I2C_CTRL0_RETAIN_CLOCK__HOLD_LOW         0x1
-#define BF_I2C_CTRL0_RETAIN_CLOCK(v)                (((v) << 21) & 0x200000)
-#define BF_I2C_CTRL0_RETAIN_CLOCK_V(v)              ((BV_I2C_CTRL0_RETAIN_CLOCK__##v << 21) & 0x200000)
-#define BP_I2C_CTRL0_POST_SEND_STOP                 20
-#define BM_I2C_CTRL0_POST_SEND_STOP                 0x100000
-#define BV_I2C_CTRL0_POST_SEND_STOP__NO_STOP        0x0
-#define BV_I2C_CTRL0_POST_SEND_STOP__SEND_STOP      0x1
-#define BF_I2C_CTRL0_POST_SEND_STOP(v)              (((v) << 20) & 0x100000)
-#define BF_I2C_CTRL0_POST_SEND_STOP_V(v)            ((BV_I2C_CTRL0_POST_SEND_STOP__##v << 20) & 0x100000)
-#define BP_I2C_CTRL0_PRE_SEND_START                 19
-#define BM_I2C_CTRL0_PRE_SEND_START                 0x80000
-#define BV_I2C_CTRL0_PRE_SEND_START__NO_START       0x0
-#define BV_I2C_CTRL0_PRE_SEND_START__SEND_START     0x1
-#define BF_I2C_CTRL0_PRE_SEND_START(v)              (((v) << 19) & 0x80000)
-#define BF_I2C_CTRL0_PRE_SEND_START_V(v)            ((BV_I2C_CTRL0_PRE_SEND_START__##v << 19) & 0x80000)
-#define BP_I2C_CTRL0_SLAVE_ADDRESS_ENABLE           18
-#define BM_I2C_CTRL0_SLAVE_ADDRESS_ENABLE           0x40000
-#define BV_I2C_CTRL0_SLAVE_ADDRESS_ENABLE__DISABLED 0x0
-#define BV_I2C_CTRL0_SLAVE_ADDRESS_ENABLE__ENABLED  0x1
-#define BF_I2C_CTRL0_SLAVE_ADDRESS_ENABLE(v)        (((v) << 18) & 0x40000)
-#define BF_I2C_CTRL0_SLAVE_ADDRESS_ENABLE_V(v)      ((BV_I2C_CTRL0_SLAVE_ADDRESS_ENABLE__##v << 18) & 0x40000)
-#define BP_I2C_CTRL0_MASTER_MODE                    17
-#define BM_I2C_CTRL0_MASTER_MODE                    0x20000
-#define BV_I2C_CTRL0_MASTER_MODE__SLAVE             0x0
-#define BV_I2C_CTRL0_MASTER_MODE__MASTER            0x1
-#define BF_I2C_CTRL0_MASTER_MODE(v)                 (((v) << 17) & 0x20000)
-#define BF_I2C_CTRL0_MASTER_MODE_V(v)               ((BV_I2C_CTRL0_MASTER_MODE__##v << 17) & 0x20000)
-#define BP_I2C_CTRL0_DIRECTION                      16
-#define BM_I2C_CTRL0_DIRECTION                      0x10000
-#define BV_I2C_CTRL0_DIRECTION__RECEIVE             0x0
-#define BV_I2C_CTRL0_DIRECTION__TRANSMIT            0x1
-#define BF_I2C_CTRL0_DIRECTION(v)                   (((v) << 16) & 0x10000)
-#define BF_I2C_CTRL0_DIRECTION_V(v)                 ((BV_I2C_CTRL0_DIRECTION__##v << 16) & 0x10000)
-#define BP_I2C_CTRL0_XFER_COUNT                     0
-#define BM_I2C_CTRL0_XFER_COUNT                     0xffff
-#define BF_I2C_CTRL0_XFER_COUNT(v)                  (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_I2C_TIMING0
- * Address: 0x10
- * SCT: yes
-*/
-#define HW_I2C_TIMING0                  (*(volatile unsigned long *)(REGS_I2C_BASE + 0x10 + 0x0))
-#define HW_I2C_TIMING0_SET              (*(volatile unsigned long *)(REGS_I2C_BASE + 0x10 + 0x4))
-#define HW_I2C_TIMING0_CLR              (*(volatile unsigned long *)(REGS_I2C_BASE + 0x10 + 0x8))
-#define HW_I2C_TIMING0_TOG              (*(volatile unsigned long *)(REGS_I2C_BASE + 0x10 + 0xc))
-#define BP_I2C_TIMING0_HIGH_COUNT       16
-#define BM_I2C_TIMING0_HIGH_COUNT       0x3ff0000
-#define BF_I2C_TIMING0_HIGH_COUNT(v)    (((v) << 16) & 0x3ff0000)
-#define BP_I2C_TIMING0_RCV_COUNT        0
-#define BM_I2C_TIMING0_RCV_COUNT        0x3ff
-#define BF_I2C_TIMING0_RCV_COUNT(v)     (((v) << 0) & 0x3ff)
-
-/**
- * Register: HW_I2C_TIMING1
- * Address: 0x20
- * SCT: yes
-*/
-#define HW_I2C_TIMING1                  (*(volatile unsigned long *)(REGS_I2C_BASE + 0x20 + 0x0))
-#define HW_I2C_TIMING1_SET              (*(volatile unsigned long *)(REGS_I2C_BASE + 0x20 + 0x4))
-#define HW_I2C_TIMING1_CLR              (*(volatile unsigned long *)(REGS_I2C_BASE + 0x20 + 0x8))
-#define HW_I2C_TIMING1_TOG              (*(volatile unsigned long *)(REGS_I2C_BASE + 0x20 + 0xc))
-#define BP_I2C_TIMING1_LOW_COUNT        16
-#define BM_I2C_TIMING1_LOW_COUNT        0x3ff0000
-#define BF_I2C_TIMING1_LOW_COUNT(v)     (((v) << 16) & 0x3ff0000)
-#define BP_I2C_TIMING1_XMIT_COUNT       0
-#define BM_I2C_TIMING1_XMIT_COUNT       0x3ff
-#define BF_I2C_TIMING1_XMIT_COUNT(v)    (((v) << 0) & 0x3ff)
-
-/**
- * Register: HW_I2C_TIMING2
- * Address: 0x30
- * SCT: yes
-*/
-#define HW_I2C_TIMING2                  (*(volatile unsigned long *)(REGS_I2C_BASE + 0x30 + 0x0))
-#define HW_I2C_TIMING2_SET              (*(volatile unsigned long *)(REGS_I2C_BASE + 0x30 + 0x4))
-#define HW_I2C_TIMING2_CLR              (*(volatile unsigned long *)(REGS_I2C_BASE + 0x30 + 0x8))
-#define HW_I2C_TIMING2_TOG              (*(volatile unsigned long *)(REGS_I2C_BASE + 0x30 + 0xc))
-#define BP_I2C_TIMING2_BUS_FREE         16
-#define BM_I2C_TIMING2_BUS_FREE         0x3ff0000
-#define BF_I2C_TIMING2_BUS_FREE(v)      (((v) << 16) & 0x3ff0000)
-#define BP_I2C_TIMING2_LEADIN_COUNT     0
-#define BM_I2C_TIMING2_LEADIN_COUNT     0x3ff
-#define BF_I2C_TIMING2_LEADIN_COUNT(v)  (((v) << 0) & 0x3ff)
-
-/**
- * Register: HW_I2C_CTRL1
- * Address: 0x40
- * SCT: yes
-*/
-#define HW_I2C_CTRL1                                        (*(volatile unsigned long *)(REGS_I2C_BASE + 0x40 + 0x0))
-#define HW_I2C_CTRL1_SET                                    (*(volatile unsigned long *)(REGS_I2C_BASE + 0x40 + 0x4))
-#define HW_I2C_CTRL1_CLR                                    (*(volatile unsigned long *)(REGS_I2C_BASE + 0x40 + 0x8))
-#define HW_I2C_CTRL1_TOG                                    (*(volatile unsigned long *)(REGS_I2C_BASE + 0x40 + 0xc))
-#define BP_I2C_CTRL1_BCAST_SLAVE_EN                         24
-#define BM_I2C_CTRL1_BCAST_SLAVE_EN                         0x1000000
-#define BV_I2C_CTRL1_BCAST_SLAVE_EN__NO_BCAST               0x0
-#define BV_I2C_CTRL1_BCAST_SLAVE_EN__WATCH_BCAST            0x1
-#define BF_I2C_CTRL1_BCAST_SLAVE_EN(v)                      (((v) << 24) & 0x1000000)
-#define BF_I2C_CTRL1_BCAST_SLAVE_EN_V(v)                    ((BV_I2C_CTRL1_BCAST_SLAVE_EN__##v << 24) & 0x1000000)
-#define BP_I2C_CTRL1_SLAVE_ADDRESS_BYTE                     16
-#define BM_I2C_CTRL1_SLAVE_ADDRESS_BYTE                     0xff0000
-#define BF_I2C_CTRL1_SLAVE_ADDRESS_BYTE(v)                  (((v) << 16) & 0xff0000)
-#define BP_I2C_CTRL1_BUS_FREE_IRQ_EN                        15
-#define BM_I2C_CTRL1_BUS_FREE_IRQ_EN                        0x8000
-#define BV_I2C_CTRL1_BUS_FREE_IRQ_EN__DISABLED              0x0
-#define BV_I2C_CTRL1_BUS_FREE_IRQ_EN__ENABLED               0x1
-#define BF_I2C_CTRL1_BUS_FREE_IRQ_EN(v)                     (((v) << 15) & 0x8000)
-#define BF_I2C_CTRL1_BUS_FREE_IRQ_EN_V(v)                   ((BV_I2C_CTRL1_BUS_FREE_IRQ_EN__##v << 15) & 0x8000)
-#define BP_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN               14
-#define BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN               0x4000
-#define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN__DISABLED     0x0
-#define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN__ENABLED      0x1
-#define BF_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN(v)            (((v) << 14) & 0x4000)
-#define BF_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN_V(v)          ((BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN__##v << 14) & 0x4000)
-#define BP_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN                    13
-#define BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN                    0x2000
-#define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN__DISABLED          0x0
-#define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN__ENABLED           0x1
-#define BF_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN(v)                 (((v) << 13) & 0x2000)
-#define BF_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN_V(v)               ((BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN__##v << 13) & 0x2000)
-#define BP_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN              12
-#define BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN              0x1000
-#define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN__DISABLED    0x0
-#define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN__ENABLED     0x1
-#define BF_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN(v)           (((v) << 12) & 0x1000)
-#define BF_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN_V(v)         ((BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN__##v << 12) & 0x1000)
-#define BP_I2C_CTRL1_EARLY_TERM_IRQ_EN                      11
-#define BM_I2C_CTRL1_EARLY_TERM_IRQ_EN                      0x800
-#define BV_I2C_CTRL1_EARLY_TERM_IRQ_EN__DISABLED            0x0
-#define BV_I2C_CTRL1_EARLY_TERM_IRQ_EN__ENABLED             0x1
-#define BF_I2C_CTRL1_EARLY_TERM_IRQ_EN(v)                   (((v) << 11) & 0x800)
-#define BF_I2C_CTRL1_EARLY_TERM_IRQ_EN_V(v)                 ((BV_I2C_CTRL1_EARLY_TERM_IRQ_EN__##v << 11) & 0x800)
-#define BP_I2C_CTRL1_MASTER_LOSS_IRQ_EN                     10
-#define BM_I2C_CTRL1_MASTER_LOSS_IRQ_EN                     0x400
-#define BV_I2C_CTRL1_MASTER_LOSS_IRQ_EN__DISABLED           0x0
-#define BV_I2C_CTRL1_MASTER_LOSS_IRQ_EN__ENABLED            0x1
-#define BF_I2C_CTRL1_MASTER_LOSS_IRQ_EN(v)                  (((v) << 10) & 0x400)
-#define BF_I2C_CTRL1_MASTER_LOSS_IRQ_EN_V(v)                ((BV_I2C_CTRL1_MASTER_LOSS_IRQ_EN__##v << 10) & 0x400)
-#define BP_I2C_CTRL1_SLAVE_STOP_IRQ_EN                      9
-#define BM_I2C_CTRL1_SLAVE_STOP_IRQ_EN                      0x200
-#define BV_I2C_CTRL1_SLAVE_STOP_IRQ_EN__DISABLED            0x0
-#define BV_I2C_CTRL1_SLAVE_STOP_IRQ_EN__ENABLED             0x1
-#define BF_I2C_CTRL1_SLAVE_STOP_IRQ_EN(v)                   (((v) << 9) & 0x200)
-#define BF_I2C_CTRL1_SLAVE_STOP_IRQ_EN_V(v)                 ((BV_I2C_CTRL1_SLAVE_STOP_IRQ_EN__##v << 9) & 0x200)
-#define BP_I2C_CTRL1_SLAVE_IRQ_EN                           8
-#define BM_I2C_CTRL1_SLAVE_IRQ_EN                           0x100
-#define BV_I2C_CTRL1_SLAVE_IRQ_EN__DISABLED                 0x0
-#define BV_I2C_CTRL1_SLAVE_IRQ_EN__ENABLED                  0x1
-#define BF_I2C_CTRL1_SLAVE_IRQ_EN(v)                        (((v) << 8) & 0x100)
-#define BF_I2C_CTRL1_SLAVE_IRQ_EN_V(v)                      ((BV_I2C_CTRL1_SLAVE_IRQ_EN__##v << 8) & 0x100)
-#define BP_I2C_CTRL1_BUS_FREE_IRQ                           7
-#define BM_I2C_CTRL1_BUS_FREE_IRQ                           0x80
-#define BV_I2C_CTRL1_BUS_FREE_IRQ__NO_REQUEST               0x0
-#define BV_I2C_CTRL1_BUS_FREE_IRQ__REQUEST                  0x1
-#define BF_I2C_CTRL1_BUS_FREE_IRQ(v)                        (((v) << 7) & 0x80)
-#define BF_I2C_CTRL1_BUS_FREE_IRQ_V(v)                      ((BV_I2C_CTRL1_BUS_FREE_IRQ__##v << 7) & 0x80)
-#define BP_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ                  6
-#define BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ                  0x40
-#define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ__NO_REQUEST      0x0
-#define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ__REQUEST         0x1
-#define BF_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ(v)               (((v) << 6) & 0x40)
-#define BF_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_V(v)             ((BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ__##v << 6) & 0x40)
-#define BP_I2C_CTRL1_NO_SLAVE_ACK_IRQ                       5
-#define BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ                       0x20
-#define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ__NO_REQUEST           0x0
-#define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ__REQUEST              0x1
-#define BF_I2C_CTRL1_NO_SLAVE_ACK_IRQ(v)                    (((v) << 5) & 0x20)
-#define BF_I2C_CTRL1_NO_SLAVE_ACK_IRQ_V(v)                  ((BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ__##v << 5) & 0x20)
-#define BP_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ                 4
-#define BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ                 0x10
-#define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ__NO_REQUEST     0x0
-#define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ__REQUEST        0x1
-#define BF_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ(v)              (((v) << 4) & 0x10)
-#define BF_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_V(v)            ((BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ__##v << 4) & 0x10)
-#define BP_I2C_CTRL1_EARLY_TERM_IRQ                         3
-#define BM_I2C_CTRL1_EARLY_TERM_IRQ                         0x8
-#define BV_I2C_CTRL1_EARLY_TERM_IRQ__NO_REQUEST             0x0
-#define BV_I2C_CTRL1_EARLY_TERM_IRQ__REQUEST                0x1
-#define BF_I2C_CTRL1_EARLY_TERM_IRQ(v)                      (((v) << 3) & 0x8)
-#define BF_I2C_CTRL1_EARLY_TERM_IRQ_V(v)                    ((BV_I2C_CTRL1_EARLY_TERM_IRQ__##v << 3) & 0x8)
-#define BP_I2C_CTRL1_MASTER_LOSS_IRQ                        2
-#define BM_I2C_CTRL1_MASTER_LOSS_IRQ                        0x4
-#define BV_I2C_CTRL1_MASTER_LOSS_IRQ__NO_REQUEST            0x0
-#define BV_I2C_CTRL1_MASTER_LOSS_IRQ__REQUEST               0x1
-#define BF_I2C_CTRL1_MASTER_LOSS_IRQ(v)                     (((v) << 2) & 0x4)
-#define BF_I2C_CTRL1_MASTER_LOSS_IRQ_V(v)                   ((BV_I2C_CTRL1_MASTER_LOSS_IRQ__##v << 2) & 0x4)
-#define BP_I2C_CTRL1_SLAVE_STOP_IRQ                         1
-#define BM_I2C_CTRL1_SLAVE_STOP_IRQ                         0x2
-#define BV_I2C_CTRL1_SLAVE_STOP_IRQ__NO_REQUEST             0x0
-#define BV_I2C_CTRL1_SLAVE_STOP_IRQ__REQUEST                0x1
-#define BF_I2C_CTRL1_SLAVE_STOP_IRQ(v)                      (((v) << 1) & 0x2)
-#define BF_I2C_CTRL1_SLAVE_STOP_IRQ_V(v)                    ((BV_I2C_CTRL1_SLAVE_STOP_IRQ__##v << 1) & 0x2)
-#define BP_I2C_CTRL1_SLAVE_IRQ                              0
-#define BM_I2C_CTRL1_SLAVE_IRQ                              0x1
-#define BV_I2C_CTRL1_SLAVE_IRQ__NO_REQUEST                  0x0
-#define BV_I2C_CTRL1_SLAVE_IRQ__REQUEST                     0x1
-#define BF_I2C_CTRL1_SLAVE_IRQ(v)                           (((v) << 0) & 0x1)
-#define BF_I2C_CTRL1_SLAVE_IRQ_V(v)                         ((BV_I2C_CTRL1_SLAVE_IRQ__##v << 0) & 0x1)
-
-/**
- * Register: HW_I2C_STAT
- * Address: 0x50
- * SCT: no
-*/
-#define HW_I2C_STAT                                             (*(volatile unsigned long *)(REGS_I2C_BASE + 0x50))
-#define BP_I2C_STAT_MASTER_PRESENT                              31
-#define BM_I2C_STAT_MASTER_PRESENT                              0x80000000
-#define BV_I2C_STAT_MASTER_PRESENT__UNAVAILABLE                 0x0
-#define BV_I2C_STAT_MASTER_PRESENT__AVAILABLE                   0x1
-#define BF_I2C_STAT_MASTER_PRESENT(v)                           (((v) << 31) & 0x80000000)
-#define BF_I2C_STAT_MASTER_PRESENT_V(v)                         ((BV_I2C_STAT_MASTER_PRESENT__##v << 31) & 0x80000000)
-#define BP_I2C_STAT_SLAVE_PRESENT                               30
-#define BM_I2C_STAT_SLAVE_PRESENT                               0x40000000
-#define BV_I2C_STAT_SLAVE_PRESENT__UNAVAILABLE                  0x0
-#define BV_I2C_STAT_SLAVE_PRESENT__AVAILABLE                    0x1
-#define BF_I2C_STAT_SLAVE_PRESENT(v)                            (((v) << 30) & 0x40000000)
-#define BF_I2C_STAT_SLAVE_PRESENT_V(v)                          ((BV_I2C_STAT_SLAVE_PRESENT__##v << 30) & 0x40000000)
-#define BP_I2C_STAT_ANY_ENABLED_IRQ                             29
-#define BM_I2C_STAT_ANY_ENABLED_IRQ                             0x20000000
-#define BV_I2C_STAT_ANY_ENABLED_IRQ__NO_REQUESTS                0x0
-#define BV_I2C_STAT_ANY_ENABLED_IRQ__AT_LEAST_ONE_REQUEST       0x1
-#define BF_I2C_STAT_ANY_ENABLED_IRQ(v)                          (((v) << 29) & 0x20000000)
-#define BF_I2C_STAT_ANY_ENABLED_IRQ_V(v)                        ((BV_I2C_STAT_ANY_ENABLED_IRQ__##v << 29) & 0x20000000)
-#define BP_I2C_STAT_RCVD_SLAVE_ADDR                             16
-#define BM_I2C_STAT_RCVD_SLAVE_ADDR                             0xff0000
-#define BF_I2C_STAT_RCVD_SLAVE_ADDR(v)                          (((v) << 16) & 0xff0000)
-#define BP_I2C_STAT_SLAVE_ADDR_EQ_ZERO                          15
-#define BM_I2C_STAT_SLAVE_ADDR_EQ_ZERO                          0x8000
-#define BV_I2C_STAT_SLAVE_ADDR_EQ_ZERO__ZERO_NOT_MATCHED        0x0
-#define BV_I2C_STAT_SLAVE_ADDR_EQ_ZERO__WAS_ZERO                0x1
-#define BF_I2C_STAT_SLAVE_ADDR_EQ_ZERO(v)                       (((v) << 15) & 0x8000)
-#define BF_I2C_STAT_SLAVE_ADDR_EQ_ZERO_V(v)                     ((BV_I2C_STAT_SLAVE_ADDR_EQ_ZERO__##v << 15) & 0x8000)
-#define BP_I2C_STAT_SLAVE_FOUND                                 14
-#define BM_I2C_STAT_SLAVE_FOUND                                 0x4000
-#define BV_I2C_STAT_SLAVE_FOUND__IDLE                           0x0
-#define BV_I2C_STAT_SLAVE_FOUND__WAITING                        0x1
-#define BF_I2C_STAT_SLAVE_FOUND(v)                              (((v) << 14) & 0x4000)
-#define BF_I2C_STAT_SLAVE_FOUND_V(v)                            ((BV_I2C_STAT_SLAVE_FOUND__##v << 14) & 0x4000)
-#define BP_I2C_STAT_SLAVE_SEARCHING                             13
-#define BM_I2C_STAT_SLAVE_SEARCHING                             0x2000
-#define BV_I2C_STAT_SLAVE_SEARCHING__IDLE                       0x0
-#define BV_I2C_STAT_SLAVE_SEARCHING__ACTIVE                     0x1
-#define BF_I2C_STAT_SLAVE_SEARCHING(v)                          (((v) << 13) & 0x2000)
-#define BF_I2C_STAT_SLAVE_SEARCHING_V(v)                        ((BV_I2C_STAT_SLAVE_SEARCHING__##v << 13) & 0x2000)
-#define BP_I2C_STAT_DATA_ENGINE_DMA_WAIT                        12
-#define BM_I2C_STAT_DATA_ENGINE_DMA_WAIT                        0x1000
-#define BV_I2C_STAT_DATA_ENGINE_DMA_WAIT__CONTINUE              0x0
-#define BV_I2C_STAT_DATA_ENGINE_DMA_WAIT__WAITING               0x1
-#define BF_I2C_STAT_DATA_ENGINE_DMA_WAIT(v)                     (((v) << 12) & 0x1000)
-#define BF_I2C_STAT_DATA_ENGINE_DMA_WAIT_V(v)                   ((BV_I2C_STAT_DATA_ENGINE_DMA_WAIT__##v << 12) & 0x1000)
-#define BP_I2C_STAT_BUS_BUSY                                    11
-#define BM_I2C_STAT_BUS_BUSY                                    0x800
-#define BV_I2C_STAT_BUS_BUSY__IDLE                              0x0
-#define BV_I2C_STAT_BUS_BUSY__BUSY                              0x1
-#define BF_I2C_STAT_BUS_BUSY(v)                                 (((v) << 11) & 0x800)
-#define BF_I2C_STAT_BUS_BUSY_V(v)                               ((BV_I2C_STAT_BUS_BUSY__##v << 11) & 0x800)
-#define BP_I2C_STAT_CLK_GEN_BUSY                                10
-#define BM_I2C_STAT_CLK_GEN_BUSY                                0x400
-#define BV_I2C_STAT_CLK_GEN_BUSY__IDLE                          0x0
-#define BV_I2C_STAT_CLK_GEN_BUSY__BUSY                          0x1
-#define BF_I2C_STAT_CLK_GEN_BUSY(v)                             (((v) << 10) & 0x400)
-#define BF_I2C_STAT_CLK_GEN_BUSY_V(v)                           ((BV_I2C_STAT_CLK_GEN_BUSY__##v << 10) & 0x400)
-#define BP_I2C_STAT_DATA_ENGINE_BUSY                            9
-#define BM_I2C_STAT_DATA_ENGINE_BUSY                            0x200
-#define BV_I2C_STAT_DATA_ENGINE_BUSY__IDLE                      0x0
-#define BV_I2C_STAT_DATA_ENGINE_BUSY__BUSY                      0x1
-#define BF_I2C_STAT_DATA_ENGINE_BUSY(v)                         (((v) << 9) & 0x200)
-#define BF_I2C_STAT_DATA_ENGINE_BUSY_V(v)                       ((BV_I2C_STAT_DATA_ENGINE_BUSY__##v << 9) & 0x200)
-#define BP_I2C_STAT_SLAVE_BUSY                                  8
-#define BM_I2C_STAT_SLAVE_BUSY                                  0x100
-#define BV_I2C_STAT_SLAVE_BUSY__IDLE                            0x0
-#define BV_I2C_STAT_SLAVE_BUSY__BUSY                            0x1
-#define BF_I2C_STAT_SLAVE_BUSY(v)                               (((v) << 8) & 0x100)
-#define BF_I2C_STAT_SLAVE_BUSY_V(v)                             ((BV_I2C_STAT_SLAVE_BUSY__##v << 8) & 0x100)
-#define BP_I2C_STAT_BUS_FREE_IRQ_SUMMARY                        7
-#define BM_I2C_STAT_BUS_FREE_IRQ_SUMMARY                        0x80
-#define BV_I2C_STAT_BUS_FREE_IRQ_SUMMARY__NO_REQUEST            0x0
-#define BV_I2C_STAT_BUS_FREE_IRQ_SUMMARY__REQUEST               0x1
-#define BF_I2C_STAT_BUS_FREE_IRQ_SUMMARY(v)                     (((v) << 7) & 0x80)
-#define BF_I2C_STAT_BUS_FREE_IRQ_SUMMARY_V(v)                   ((BV_I2C_STAT_BUS_FREE_IRQ_SUMMARY__##v << 7) & 0x80)
-#define BP_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY               6
-#define BM_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY               0x40
-#define BV_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY__NO_REQUEST   0x0
-#define BV_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY__REQUEST      0x1
-#define BF_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY(v)            (((v) << 6) & 0x40)
-#define BF_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY_V(v)          ((BV_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY__##v << 6) & 0x40)
-#define BP_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY                    5
-#define BM_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY                    0x20
-#define BV_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY__NO_REQUEST        0x0
-#define BV_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY__REQUEST           0x1
-#define BF_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY(v)                 (((v) << 5) & 0x20)
-#define BF_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY_V(v)               ((BV_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY__##v << 5) & 0x20)
-#define BP_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY              4
-#define BM_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY              0x10
-#define BV_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY__NO_REQUEST  0x0
-#define BV_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY__REQUEST     0x1
-#define BF_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY(v)           (((v) << 4) & 0x10)
-#define BF_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY_V(v)         ((BV_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY__##v << 4) & 0x10)
-#define BP_I2C_STAT_EARLY_TERM_IRQ_SUMMARY                      3
-#define BM_I2C_STAT_EARLY_TERM_IRQ_SUMMARY                      0x8
-#define BV_I2C_STAT_EARLY_TERM_IRQ_SUMMARY__NO_REQUEST          0x0
-#define BV_I2C_STAT_EARLY_TERM_IRQ_SUMMARY__REQUEST             0x1
-#define BF_I2C_STAT_EARLY_TERM_IRQ_SUMMARY(v)                   (((v) << 3) & 0x8)
-#define BF_I2C_STAT_EARLY_TERM_IRQ_SUMMARY_V(v)                 ((BV_I2C_STAT_EARLY_TERM_IRQ_SUMMARY__##v << 3) & 0x8)
-#define BP_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY                     2
-#define BM_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY                     0x4
-#define BV_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY__NO_REQUEST         0x0
-#define BV_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY__REQUEST            0x1
-#define BF_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY(v)                  (((v) << 2) & 0x4)
-#define BF_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY_V(v)                ((BV_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY__##v << 2) & 0x4)
-#define BP_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY                      1
-#define BM_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY                      0x2
-#define BV_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY__NO_REQUEST          0x0
-#define BV_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY__REQUEST             0x1
-#define BF_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY(v)                   (((v) << 1) & 0x2)
-#define BF_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY_V(v)                 ((BV_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY__##v << 1) & 0x2)
-#define BP_I2C_STAT_SLAVE_IRQ_SUMMARY                           0
-#define BM_I2C_STAT_SLAVE_IRQ_SUMMARY                           0x1
-#define BV_I2C_STAT_SLAVE_IRQ_SUMMARY__NO_REQUEST               0x0
-#define BV_I2C_STAT_SLAVE_IRQ_SUMMARY__REQUEST                  0x1
-#define BF_I2C_STAT_SLAVE_IRQ_SUMMARY(v)                        (((v) << 0) & 0x1)
-#define BF_I2C_STAT_SLAVE_IRQ_SUMMARY_V(v)                      ((BV_I2C_STAT_SLAVE_IRQ_SUMMARY__##v << 0) & 0x1)
-
-/**
- * Register: HW_I2C_DATA
- * Address: 0x60
- * SCT: no
-*/
-#define HW_I2C_DATA         (*(volatile unsigned long *)(REGS_I2C_BASE + 0x60))
-#define BP_I2C_DATA_DATA    0
-#define BM_I2C_DATA_DATA    0xffffffff
-#define BF_I2C_DATA_DATA(v) (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_I2C_DEBUG0
- * Address: 0x70
- * SCT: yes
-*/
-#define HW_I2C_DEBUG0                   (*(volatile unsigned long *)(REGS_I2C_BASE + 0x70 + 0x0))
-#define HW_I2C_DEBUG0_SET               (*(volatile unsigned long *)(REGS_I2C_BASE + 0x70 + 0x4))
-#define HW_I2C_DEBUG0_CLR               (*(volatile unsigned long *)(REGS_I2C_BASE + 0x70 + 0x8))
-#define HW_I2C_DEBUG0_TOG               (*(volatile unsigned long *)(REGS_I2C_BASE + 0x70 + 0xc))
-#define BP_I2C_DEBUG0_DMAREQ            31
-#define BM_I2C_DEBUG0_DMAREQ            0x80000000
-#define BF_I2C_DEBUG0_DMAREQ(v)         (((v) << 31) & 0x80000000)
-#define BP_I2C_DEBUG0_DMAENDCMD         30
-#define BM_I2C_DEBUG0_DMAENDCMD         0x40000000
-#define BF_I2C_DEBUG0_DMAENDCMD(v)      (((v) << 30) & 0x40000000)
-#define BP_I2C_DEBUG0_DMAKICK           29
-#define BM_I2C_DEBUG0_DMAKICK           0x20000000
-#define BF_I2C_DEBUG0_DMAKICK(v)        (((v) << 29) & 0x20000000)
-#define BP_I2C_DEBUG0_TBD               26
-#define BM_I2C_DEBUG0_TBD               0x1c000000
-#define BF_I2C_DEBUG0_TBD(v)            (((v) << 26) & 0x1c000000)
-#define BP_I2C_DEBUG0_DMA_STATE         16
-#define BM_I2C_DEBUG0_DMA_STATE         0x3ff0000
-#define BF_I2C_DEBUG0_DMA_STATE(v)      (((v) << 16) & 0x3ff0000)
-#define BP_I2C_DEBUG0_START_TOGGLE      15
-#define BM_I2C_DEBUG0_START_TOGGLE      0x8000
-#define BF_I2C_DEBUG0_START_TOGGLE(v)   (((v) << 15) & 0x8000)
-#define BP_I2C_DEBUG0_STOP_TOGGLE       14
-#define BM_I2C_DEBUG0_STOP_TOGGLE       0x4000
-#define BF_I2C_DEBUG0_STOP_TOGGLE(v)    (((v) << 14) & 0x4000)
-#define BP_I2C_DEBUG0_GRAB_TOGGLE       13
-#define BM_I2C_DEBUG0_GRAB_TOGGLE       0x2000
-#define BF_I2C_DEBUG0_GRAB_TOGGLE(v)    (((v) << 13) & 0x2000)
-#define BP_I2C_DEBUG0_CHANGE_TOGGLE     12
-#define BM_I2C_DEBUG0_CHANGE_TOGGLE     0x1000
-#define BF_I2C_DEBUG0_CHANGE_TOGGLE(v)  (((v) << 12) & 0x1000)
-#define BP_I2C_DEBUG0_TESTMODE          11
-#define BM_I2C_DEBUG0_TESTMODE          0x800
-#define BF_I2C_DEBUG0_TESTMODE(v)       (((v) << 11) & 0x800)
-#define BP_I2C_DEBUG0_SLAVE_HOLD_CLK    10
-#define BM_I2C_DEBUG0_SLAVE_HOLD_CLK    0x400
-#define BF_I2C_DEBUG0_SLAVE_HOLD_CLK(v) (((v) << 10) & 0x400)
-#define BP_I2C_DEBUG0_SLAVE_STATE       0
-#define BM_I2C_DEBUG0_SLAVE_STATE       0x3ff
-#define BF_I2C_DEBUG0_SLAVE_STATE(v)    (((v) << 0) & 0x3ff)
-
-/**
- * Register: HW_I2C_DEBUG1
- * Address: 0x80
- * SCT: yes
-*/
-#define HW_I2C_DEBUG1                       (*(volatile unsigned long *)(REGS_I2C_BASE + 0x80 + 0x0))
-#define HW_I2C_DEBUG1_SET                   (*(volatile unsigned long *)(REGS_I2C_BASE + 0x80 + 0x4))
-#define HW_I2C_DEBUG1_CLR                   (*(volatile unsigned long *)(REGS_I2C_BASE + 0x80 + 0x8))
-#define HW_I2C_DEBUG1_TOG                   (*(volatile unsigned long *)(REGS_I2C_BASE + 0x80 + 0xc))
-#define BP_I2C_DEBUG1_I2C_CLK_IN            31
-#define BM_I2C_DEBUG1_I2C_CLK_IN            0x80000000
-#define BF_I2C_DEBUG1_I2C_CLK_IN(v)         (((v) << 31) & 0x80000000)
-#define BP_I2C_DEBUG1_I2C_DATA_IN           30
-#define BM_I2C_DEBUG1_I2C_DATA_IN           0x40000000
-#define BF_I2C_DEBUG1_I2C_DATA_IN(v)        (((v) << 30) & 0x40000000)
-#define BP_I2C_DEBUG1_DMA_BYTE_ENABLES      24
-#define BM_I2C_DEBUG1_DMA_BYTE_ENABLES      0xf000000
-#define BF_I2C_DEBUG1_DMA_BYTE_ENABLES(v)   (((v) << 24) & 0xf000000)
-#define BP_I2C_DEBUG1_CLK_GEN_STATE         16
-#define BM_I2C_DEBUG1_CLK_GEN_STATE         0x7f0000
-#define BF_I2C_DEBUG1_CLK_GEN_STATE(v)      (((v) << 16) & 0x7f0000)
-#define BP_I2C_DEBUG1_LST_MODE              9
-#define BM_I2C_DEBUG1_LST_MODE              0x600
-#define BV_I2C_DEBUG1_LST_MODE__BCAST       0x0
-#define BV_I2C_DEBUG1_LST_MODE__MY_WRITE    0x1
-#define BV_I2C_DEBUG1_LST_MODE__MY_READ     0x2
-#define BV_I2C_DEBUG1_LST_MODE__NOT_ME      0x3
-#define BF_I2C_DEBUG1_LST_MODE(v)           (((v) << 9) & 0x600)
-#define BF_I2C_DEBUG1_LST_MODE_V(v)         ((BV_I2C_DEBUG1_LST_MODE__##v << 9) & 0x600)
-#define BP_I2C_DEBUG1_LOCAL_SLAVE_TEST      8
-#define BM_I2C_DEBUG1_LOCAL_SLAVE_TEST      0x100
-#define BF_I2C_DEBUG1_LOCAL_SLAVE_TEST(v)   (((v) << 8) & 0x100)
-#define BP_I2C_DEBUG1_FORCE_CLK_ON          5
-#define BM_I2C_DEBUG1_FORCE_CLK_ON          0x20
-#define BF_I2C_DEBUG1_FORCE_CLK_ON(v)       (((v) << 5) & 0x20)
-#define BP_I2C_DEBUG1_FORCE_CLK_IDLE        4
-#define BM_I2C_DEBUG1_FORCE_CLK_IDLE        0x10
-#define BF_I2C_DEBUG1_FORCE_CLK_IDLE(v)     (((v) << 4) & 0x10)
-#define BP_I2C_DEBUG1_FORCE_ARB_LOSS        3
-#define BM_I2C_DEBUG1_FORCE_ARB_LOSS        0x8
-#define BF_I2C_DEBUG1_FORCE_ARB_LOSS(v)     (((v) << 3) & 0x8)
-#define BP_I2C_DEBUG1_FORCE_RCV_ACK         2
-#define BM_I2C_DEBUG1_FORCE_RCV_ACK         0x4
-#define BF_I2C_DEBUG1_FORCE_RCV_ACK(v)      (((v) << 2) & 0x4)
-#define BP_I2C_DEBUG1_FORCE_I2C_DATA_OE     1
-#define BM_I2C_DEBUG1_FORCE_I2C_DATA_OE     0x2
-#define BF_I2C_DEBUG1_FORCE_I2C_DATA_OE(v)  (((v) << 1) & 0x2)
-#define BP_I2C_DEBUG1_FORCE_I2C_CLK_OE      0
-#define BM_I2C_DEBUG1_FORCE_I2C_CLK_OE      0x1
-#define BF_I2C_DEBUG1_FORCE_I2C_CLK_OE(v)   (((v) << 0) & 0x1)
-
-/**
- * Register: HW_I2C_VERSION
- * Address: 0x90
- * SCT: no
-*/
-#define HW_I2C_VERSION          (*(volatile unsigned long *)(REGS_I2C_BASE + 0x90))
-#define BP_I2C_VERSION_MAJOR    24
-#define BM_I2C_VERSION_MAJOR    0xff000000
-#define BF_I2C_VERSION_MAJOR(v) (((v) << 24) & 0xff000000)
-#define BP_I2C_VERSION_MINOR    16
-#define BM_I2C_VERSION_MINOR    0xff0000
-#define BF_I2C_VERSION_MINOR(v) (((v) << 16) & 0xff0000)
-#define BP_I2C_VERSION_STEP     0
-#define BM_I2C_VERSION_STEP     0xffff
-#define BF_I2C_VERSION_STEP(v)  (((v) << 0) & 0xffff)
-
-#endif /* __HEADERGEN__STMP3700__I2C__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-icoll.h b/firmware/target/arm/imx233/regs/stmp3700/regs-icoll.h
deleted file mode 100644
index 04ece89a8f..0000000000
--- a/firmware/target/arm/imx233/regs/stmp3700/regs-icoll.h
+++ /dev/null
@@ -1,410 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3700:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__STMP3700__ICOLL__H__
-#define __HEADERGEN__STMP3700__ICOLL__H__
-
-#define REGS_ICOLL_BASE (0x80000000)
-
-#define REGS_ICOLL_VERSION "3.2.0"
-
-/**
- * Register: HW_ICOLL_VECTOR
- * Address: 0
- * SCT: yes
-*/
-#define HW_ICOLL_VECTOR                 (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x0 + 0x0))
-#define HW_ICOLL_VECTOR_SET             (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x0 + 0x4))
-#define HW_ICOLL_VECTOR_CLR             (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x0 + 0x8))
-#define HW_ICOLL_VECTOR_TOG             (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x0 + 0xc))
-#define BP_ICOLL_VECTOR_IRQVECTOR       2
-#define BM_ICOLL_VECTOR_IRQVECTOR       0xfffffffc
-#define BF_ICOLL_VECTOR_IRQVECTOR(v)    (((v) << 2) & 0xfffffffc)
-
-/**
- * Register: HW_ICOLL_LEVELACK
- * Address: 0x10
- * SCT: no
-*/
-#define HW_ICOLL_LEVELACK                       (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x10))
-#define BP_ICOLL_LEVELACK_IRQLEVELACK           0
-#define BM_ICOLL_LEVELACK_IRQLEVELACK           0xf
-#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0   0x1
-#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL1   0x2
-#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL2   0x4
-#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL3   0x8
-#define BF_ICOLL_LEVELACK_IRQLEVELACK(v)        (((v) << 0) & 0xf)
-#define BF_ICOLL_LEVELACK_IRQLEVELACK_V(v)      ((BV_ICOLL_LEVELACK_IRQLEVELACK__##v << 0) & 0xf)
-
-/**
- * Register: HW_ICOLL_CTRL
- * Address: 0x20
- * SCT: yes
-*/
-#define HW_ICOLL_CTRL                                   (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x20 + 0x0))
-#define HW_ICOLL_CTRL_SET                               (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x20 + 0x4))
-#define HW_ICOLL_CTRL_CLR                               (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x20 + 0x8))
-#define HW_ICOLL_CTRL_TOG                               (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x20 + 0xc))
-#define BP_ICOLL_CTRL_SFTRST                            31
-#define BM_ICOLL_CTRL_SFTRST                            0x80000000
-#define BV_ICOLL_CTRL_SFTRST__RUN                       0x0
-#define BV_ICOLL_CTRL_SFTRST__IN_RESET                  0x1
-#define BF_ICOLL_CTRL_SFTRST(v)                         (((v) << 31) & 0x80000000)
-#define BF_ICOLL_CTRL_SFTRST_V(v)                       ((BV_ICOLL_CTRL_SFTRST__##v << 31) & 0x80000000)
-#define BP_ICOLL_CTRL_CLKGATE                           30
-#define BM_ICOLL_CTRL_CLKGATE                           0x40000000
-#define BV_ICOLL_CTRL_CLKGATE__RUN                      0x0
-#define BV_ICOLL_CTRL_CLKGATE__NO_CLOCKS                0x1
-#define BF_ICOLL_CTRL_CLKGATE(v)                        (((v) << 30) & 0x40000000)
-#define BF_ICOLL_CTRL_CLKGATE_V(v)                      ((BV_ICOLL_CTRL_CLKGATE__##v << 30) & 0x40000000)
-#define BP_ICOLL_CTRL_VECTOR_PITCH                      21
-#define BM_ICOLL_CTRL_VECTOR_PITCH                      0xe00000
-#define BV_ICOLL_CTRL_VECTOR_PITCH__DEFAULT_BY4         0x0
-#define BV_ICOLL_CTRL_VECTOR_PITCH__BY4                 0x1
-#define BV_ICOLL_CTRL_VECTOR_PITCH__BY8                 0x2
-#define BV_ICOLL_CTRL_VECTOR_PITCH__BY12                0x3
-#define BV_ICOLL_CTRL_VECTOR_PITCH__BY16                0x4
-#define BV_ICOLL_CTRL_VECTOR_PITCH__BY20                0x5
-#define BV_ICOLL_CTRL_VECTOR_PITCH__BY24                0x6
-#define BV_ICOLL_CTRL_VECTOR_PITCH__BY28                0x7
-#define BF_ICOLL_CTRL_VECTOR_PITCH(v)                   (((v) << 21) & 0xe00000)
-#define BF_ICOLL_CTRL_VECTOR_PITCH_V(v)                 ((BV_ICOLL_CTRL_VECTOR_PITCH__##v << 21) & 0xe00000)
-#define BP_ICOLL_CTRL_BYPASS_FSM                        20
-#define BM_ICOLL_CTRL_BYPASS_FSM                        0x100000
-#define BV_ICOLL_CTRL_BYPASS_FSM__NORMAL                0x0
-#define BV_ICOLL_CTRL_BYPASS_FSM__BYPASS                0x1
-#define BF_ICOLL_CTRL_BYPASS_FSM(v)                     (((v) << 20) & 0x100000)
-#define BF_ICOLL_CTRL_BYPASS_FSM_V(v)                   ((BV_ICOLL_CTRL_BYPASS_FSM__##v << 20) & 0x100000)
-#define BP_ICOLL_CTRL_NO_NESTING                        19
-#define BM_ICOLL_CTRL_NO_NESTING                        0x80000
-#define BV_ICOLL_CTRL_NO_NESTING__NORMAL                0x0
-#define BV_ICOLL_CTRL_NO_NESTING__NO_NEST               0x1
-#define BF_ICOLL_CTRL_NO_NESTING(v)                     (((v) << 19) & 0x80000)
-#define BF_ICOLL_CTRL_NO_NESTING_V(v)                   ((BV_ICOLL_CTRL_NO_NESTING__##v << 19) & 0x80000)
-#define BP_ICOLL_CTRL_ARM_RSE_MODE                      18
-#define BM_ICOLL_CTRL_ARM_RSE_MODE                      0x40000
-#define BV_ICOLL_CTRL_ARM_RSE_MODE__MUST_WRITE          0x0
-#define BV_ICOLL_CTRL_ARM_RSE_MODE__READ_SIDE_EFFECT    0x1
-#define BF_ICOLL_CTRL_ARM_RSE_MODE(v)                   (((v) << 18) & 0x40000)
-#define BF_ICOLL_CTRL_ARM_RSE_MODE_V(v)                 ((BV_ICOLL_CTRL_ARM_RSE_MODE__##v << 18) & 0x40000)
-#define BP_ICOLL_CTRL_FIQ_FINAL_ENABLE                  17
-#define BM_ICOLL_CTRL_FIQ_FINAL_ENABLE                  0x20000
-#define BV_ICOLL_CTRL_FIQ_FINAL_ENABLE__DISABLE         0x0
-#define BV_ICOLL_CTRL_FIQ_FINAL_ENABLE__ENABLE          0x1
-#define BF_ICOLL_CTRL_FIQ_FINAL_ENABLE(v)               (((v) << 17) & 0x20000)
-#define BF_ICOLL_CTRL_FIQ_FINAL_ENABLE_V(v)             ((BV_ICOLL_CTRL_FIQ_FINAL_ENABLE__##v << 17) & 0x20000)
-#define BP_ICOLL_CTRL_IRQ_FINAL_ENABLE                  16
-#define BM_ICOLL_CTRL_IRQ_FINAL_ENABLE                  0x10000
-#define BV_ICOLL_CTRL_IRQ_FINAL_ENABLE__DISABLE         0x0
-#define BV_ICOLL_CTRL_IRQ_FINAL_ENABLE__ENABLE          0x1
-#define BF_ICOLL_CTRL_IRQ_FINAL_ENABLE(v)               (((v) << 16) & 0x10000)
-#define BF_ICOLL_CTRL_IRQ_FINAL_ENABLE_V(v)             ((BV_ICOLL_CTRL_IRQ_FINAL_ENABLE__##v << 16) & 0x10000)
-#define BP_ICOLL_CTRL_ENABLE2FIQ35                      7
-#define BM_ICOLL_CTRL_ENABLE2FIQ35                      0x80
-#define BV_ICOLL_CTRL_ENABLE2FIQ35__DISABLE             0x0
-#define BV_ICOLL_CTRL_ENABLE2FIQ35__ENABLE              0x1
-#define BF_ICOLL_CTRL_ENABLE2FIQ35(v)                   (((v) << 7) & 0x80)
-#define BF_ICOLL_CTRL_ENABLE2FIQ35_V(v)                 ((BV_ICOLL_CTRL_ENABLE2FIQ35__##v << 7) & 0x80)
-#define BP_ICOLL_CTRL_ENABLE2FIQ34                      6
-#define BM_ICOLL_CTRL_ENABLE2FIQ34                      0x40
-#define BV_ICOLL_CTRL_ENABLE2FIQ34__DISABLE             0x0
-#define BV_ICOLL_CTRL_ENABLE2FIQ34__ENABLE              0x1
-#define BF_ICOLL_CTRL_ENABLE2FIQ34(v)                   (((v) << 6) & 0x40)
-#define BF_ICOLL_CTRL_ENABLE2FIQ34_V(v)                 ((BV_ICOLL_CTRL_ENABLE2FIQ34__##v << 6) & 0x40)
-#define BP_ICOLL_CTRL_ENABLE2FIQ33                      5
-#define BM_ICOLL_CTRL_ENABLE2FIQ33                      0x20
-#define BV_ICOLL_CTRL_ENABLE2FIQ33__DISABLE             0x0
-#define BV_ICOLL_CTRL_ENABLE2FIQ33__ENABLE              0x1
-#define BF_ICOLL_CTRL_ENABLE2FIQ33(v)                   (((v) << 5) & 0x20)
-#define BF_ICOLL_CTRL_ENABLE2FIQ33_V(v)                 ((BV_ICOLL_CTRL_ENABLE2FIQ33__##v << 5) & 0x20)
-#define BP_ICOLL_CTRL_ENABLE2FIQ32                      4
-#define BM_ICOLL_CTRL_ENABLE2FIQ32                      0x10
-#define BV_ICOLL_CTRL_ENABLE2FIQ32__DISABLE             0x0
-#define BV_ICOLL_CTRL_ENABLE2FIQ32__ENABLE              0x1
-#define BF_ICOLL_CTRL_ENABLE2FIQ32(v)                   (((v) << 4) & 0x10)
-#define BF_ICOLL_CTRL_ENABLE2FIQ32_V(v)                 ((BV_ICOLL_CTRL_ENABLE2FIQ32__##v << 4) & 0x10)
-#define BP_ICOLL_CTRL_ENABLE2FIQ_T3                     3
-#define BM_ICOLL_CTRL_ENABLE2FIQ_T3                     0x8
-#define BV_ICOLL_CTRL_ENABLE2FIQ_T3__DISABLE            0x0
-#define BV_ICOLL_CTRL_ENABLE2FIQ_T3__ENABLE             0x1
-#define BF_ICOLL_CTRL_ENABLE2FIQ_T3(v)                  (((v) << 3) & 0x8)
-#define BF_ICOLL_CTRL_ENABLE2FIQ_T3_V(v)                ((BV_ICOLL_CTRL_ENABLE2FIQ_T3__##v << 3) & 0x8)
-#define BP_ICOLL_CTRL_ENABLE2FIQ_T2                     2
-#define BM_ICOLL_CTRL_ENABLE2FIQ_T2                     0x4
-#define BV_ICOLL_CTRL_ENABLE2FIQ_T2__DISABLE            0x0
-#define BV_ICOLL_CTRL_ENABLE2FIQ_T2__ENABLE             0x1
-#define BF_ICOLL_CTRL_ENABLE2FIQ_T2(v)                  (((v) << 2) & 0x4)
-#define BF_ICOLL_CTRL_ENABLE2FIQ_T2_V(v)                ((BV_ICOLL_CTRL_ENABLE2FIQ_T2__##v << 2) & 0x4)
-#define BP_ICOLL_CTRL_ENABLE2FIQ_T1                     1
-#define BM_ICOLL_CTRL_ENABLE2FIQ_T1                     0x2
-#define BV_ICOLL_CTRL_ENABLE2FIQ_T1__DISABLE            0x0
-#define BV_ICOLL_CTRL_ENABLE2FIQ_T1__ENABLE             0x1
-#define BF_ICOLL_CTRL_ENABLE2FIQ_T1(v)                  (((v) << 1) & 0x2)
-#define BF_ICOLL_CTRL_ENABLE2FIQ_T1_V(v)                ((BV_ICOLL_CTRL_ENABLE2FIQ_T1__##v << 1) & 0x2)
-#define BP_ICOLL_CTRL_ENABLE2FIQ_T0                     0
-#define BM_ICOLL_CTRL_ENABLE2FIQ_T0                     0x1
-#define BV_ICOLL_CTRL_ENABLE2FIQ_T0__DISABLE            0x0
-#define BV_ICOLL_CTRL_ENABLE2FIQ_T0__ENABLE             0x1
-#define BF_ICOLL_CTRL_ENABLE2FIQ_T0(v)                  (((v) << 0) & 0x1)
-#define BF_ICOLL_CTRL_ENABLE2FIQ_T0_V(v)                ((BV_ICOLL_CTRL_ENABLE2FIQ_T0__##v << 0) & 0x1)
-
-/**
- * Register: HW_ICOLL_STAT
- * Address: 0x30
- * SCT: no
-*/
-#define HW_ICOLL_STAT                   (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x30))
-#define BP_ICOLL_STAT_VECTOR_NUMBER     0
-#define BM_ICOLL_STAT_VECTOR_NUMBER     0x3f
-#define BF_ICOLL_STAT_VECTOR_NUMBER(v)  (((v) << 0) & 0x3f)
-
-/**
- * Register: HW_ICOLL_RAWn
- * Address: 0x40+n*0x10
- * SCT: no
-*/
-#define HW_ICOLL_RAWn(n)            (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x40+(n)*0x10))
-#define BP_ICOLL_RAWn_RAW_IRQS      0
-#define BM_ICOLL_RAWn_RAW_IRQS      0xffffffff
-#define BF_ICOLL_RAWn_RAW_IRQS(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_ICOLL_PRIORITYn
- * Address: 0x60+n*0x10
- * SCT: yes
-*/
-#define HW_ICOLL_PRIORITYn(n)                           (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x60+(n)*0x10 + 0x0))
-#define HW_ICOLL_PRIORITYn_SET(n)                       (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x60+(n)*0x10 + 0x4))
-#define HW_ICOLL_PRIORITYn_CLR(n)                       (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x60+(n)*0x10 + 0x8))
-#define HW_ICOLL_PRIORITYn_TOG(n)                       (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x60+(n)*0x10 + 0xc))
-#define BP_ICOLL_PRIORITYn_SOFTIRQ3                     27
-#define BM_ICOLL_PRIORITYn_SOFTIRQ3                     0x8000000
-#define BV_ICOLL_PRIORITYn_SOFTIRQ3__NO_INTERRUPT       0x0
-#define BV_ICOLL_PRIORITYn_SOFTIRQ3__FORCE_INTERRUPT    0x1
-#define BF_ICOLL_PRIORITYn_SOFTIRQ3(v)                  (((v) << 27) & 0x8000000)
-#define BF_ICOLL_PRIORITYn_SOFTIRQ3_V(v)                ((BV_ICOLL_PRIORITYn_SOFTIRQ3__##v << 27) & 0x8000000)
-#define BP_ICOLL_PRIORITYn_ENABLE3                      26
-#define BM_ICOLL_PRIORITYn_ENABLE3                      0x4000000
-#define BV_ICOLL_PRIORITYn_ENABLE3__DISABLE             0x0
-#define BV_ICOLL_PRIORITYn_ENABLE3__ENABLE              0x1
-#define BF_ICOLL_PRIORITYn_ENABLE3(v)                   (((v) << 26) & 0x4000000)
-#define BF_ICOLL_PRIORITYn_ENABLE3_V(v)                 ((BV_ICOLL_PRIORITYn_ENABLE3__##v << 26) & 0x4000000)
-#define BP_ICOLL_PRIORITYn_PRIORITY3                    24
-#define BM_ICOLL_PRIORITYn_PRIORITY3                    0x3000000
-#define BV_ICOLL_PRIORITYn_PRIORITY3__LEVEL0            0x0
-#define BV_ICOLL_PRIORITYn_PRIORITY3__LEVEL1            0x1
-#define BV_ICOLL_PRIORITYn_PRIORITY3__LEVEL2            0x2
-#define BV_ICOLL_PRIORITYn_PRIORITY3__LEVEL3            0x3
-#define BF_ICOLL_PRIORITYn_PRIORITY3(v)                 (((v) << 24) & 0x3000000)
-#define BF_ICOLL_PRIORITYn_PRIORITY3_V(v)               ((BV_ICOLL_PRIORITYn_PRIORITY3__##v << 24) & 0x3000000)
-#define BP_ICOLL_PRIORITYn_SOFTIRQ2                     19
-#define BM_ICOLL_PRIORITYn_SOFTIRQ2                     0x80000
-#define BV_ICOLL_PRIORITYn_SOFTIRQ2__NO_INTERRUPT       0x0
-#define BV_ICOLL_PRIORITYn_SOFTIRQ2__FORCE_INTERRUPT    0x1
-#define BF_ICOLL_PRIORITYn_SOFTIRQ2(v)                  (((v) << 19) & 0x80000)
-#define BF_ICOLL_PRIORITYn_SOFTIRQ2_V(v)                ((BV_ICOLL_PRIORITYn_SOFTIRQ2__##v << 19) & 0x80000)
-#define BP_ICOLL_PRIORITYn_ENABLE2                      18
-#define BM_ICOLL_PRIORITYn_ENABLE2                      0x40000
-#define BV_ICOLL_PRIORITYn_ENABLE2__DISABLE             0x0
-#define BV_ICOLL_PRIORITYn_ENABLE2__ENABLE              0x1
-#define BF_ICOLL_PRIORITYn_ENABLE2(v)                   (((v) << 18) & 0x40000)
-#define BF_ICOLL_PRIORITYn_ENABLE2_V(v)                 ((BV_ICOLL_PRIORITYn_ENABLE2__##v << 18) & 0x40000)
-#define BP_ICOLL_PRIORITYn_PRIORITY2                    16
-#define BM_ICOLL_PRIORITYn_PRIORITY2                    0x30000
-#define BV_ICOLL_PRIORITYn_PRIORITY2__LEVEL0            0x0
-#define BV_ICOLL_PRIORITYn_PRIORITY2__LEVEL1            0x1
-#define BV_ICOLL_PRIORITYn_PRIORITY2__LEVEL2            0x2
-#define BV_ICOLL_PRIORITYn_PRIORITY2__LEVEL3            0x3
-#define BF_ICOLL_PRIORITYn_PRIORITY2(v)                 (((v) << 16) & 0x30000)
-#define BF_ICOLL_PRIORITYn_PRIORITY2_V(v)               ((BV_ICOLL_PRIORITYn_PRIORITY2__##v << 16) & 0x30000)
-#define BP_ICOLL_PRIORITYn_SOFTIRQ1                     11
-#define BM_ICOLL_PRIORITYn_SOFTIRQ1                     0x800
-#define BV_ICOLL_PRIORITYn_SOFTIRQ1__NO_INTERRUPT       0x0
-#define BV_ICOLL_PRIORITYn_SOFTIRQ1__FORCE_INTERRUPT    0x1
-#define BF_ICOLL_PRIORITYn_SOFTIRQ1(v)                  (((v) << 11) & 0x800)
-#define BF_ICOLL_PRIORITYn_SOFTIRQ1_V(v)                ((BV_ICOLL_PRIORITYn_SOFTIRQ1__##v << 11) & 0x800)
-#define BP_ICOLL_PRIORITYn_ENABLE1                      10
-#define BM_ICOLL_PRIORITYn_ENABLE1                      0x400
-#define BV_ICOLL_PRIORITYn_ENABLE1__DISABLE             0x0
-#define BV_ICOLL_PRIORITYn_ENABLE1__ENABLE              0x1
-#define BF_ICOLL_PRIORITYn_ENABLE1(v)                   (((v) << 10) & 0x400)
-#define BF_ICOLL_PRIORITYn_ENABLE1_V(v)                 ((BV_ICOLL_PRIORITYn_ENABLE1__##v << 10) & 0x400)
-#define BP_ICOLL_PRIORITYn_PRIORITY1                    8
-#define BM_ICOLL_PRIORITYn_PRIORITY1                    0x300
-#define BV_ICOLL_PRIORITYn_PRIORITY1__LEVEL0            0x0
-#define BV_ICOLL_PRIORITYn_PRIORITY1__LEVEL1            0x1
-#define BV_ICOLL_PRIORITYn_PRIORITY1__LEVEL2            0x2
-#define BV_ICOLL_PRIORITYn_PRIORITY1__LEVEL3            0x3
-#define BF_ICOLL_PRIORITYn_PRIORITY1(v)                 (((v) << 8) & 0x300)
-#define BF_ICOLL_PRIORITYn_PRIORITY1_V(v)               ((BV_ICOLL_PRIORITYn_PRIORITY1__##v << 8) & 0x300)
-#define BP_ICOLL_PRIORITYn_SOFTIRQ0                     3
-#define BM_ICOLL_PRIORITYn_SOFTIRQ0                     0x8
-#define BV_ICOLL_PRIORITYn_SOFTIRQ0__NO_INTERRUPT       0x0
-#define BV_ICOLL_PRIORITYn_SOFTIRQ0__FORCE_INTERRUPT    0x1
-#define BF_ICOLL_PRIORITYn_SOFTIRQ0(v)                  (((v) << 3) & 0x8)
-#define BF_ICOLL_PRIORITYn_SOFTIRQ0_V(v)                ((BV_ICOLL_PRIORITYn_SOFTIRQ0__##v << 3) & 0x8)
-#define BP_ICOLL_PRIORITYn_ENABLE0                      2
-#define BM_ICOLL_PRIORITYn_ENABLE0                      0x4
-#define BV_ICOLL_PRIORITYn_ENABLE0__DISABLE             0x0
-#define BV_ICOLL_PRIORITYn_ENABLE0__ENABLE              0x1
-#define BF_ICOLL_PRIORITYn_ENABLE0(v)                   (((v) << 2) & 0x4)
-#define BF_ICOLL_PRIORITYn_ENABLE0_V(v)                 ((BV_ICOLL_PRIORITYn_ENABLE0__##v << 2) & 0x4)
-#define BP_ICOLL_PRIORITYn_PRIORITY0                    0
-#define BM_ICOLL_PRIORITYn_PRIORITY0                    0x3
-#define BV_ICOLL_PRIORITYn_PRIORITY0__LEVEL0            0x0
-#define BV_ICOLL_PRIORITYn_PRIORITY0__LEVEL1            0x1
-#define BV_ICOLL_PRIORITYn_PRIORITY0__LEVEL2            0x2
-#define BV_ICOLL_PRIORITYn_PRIORITY0__LEVEL3            0x3
-#define BF_ICOLL_PRIORITYn_PRIORITY0(v)                 (((v) << 0) & 0x3)
-#define BF_ICOLL_PRIORITYn_PRIORITY0_V(v)               ((BV_ICOLL_PRIORITYn_PRIORITY0__##v << 0) & 0x3)
-
-/**
- * Register: HW_ICOLL_VBASE
- * Address: 0x160
- * SCT: yes
-*/
-#define HW_ICOLL_VBASE                  (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x160 + 0x0))
-#define HW_ICOLL_VBASE_SET              (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x160 + 0x4))
-#define HW_ICOLL_VBASE_CLR              (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x160 + 0x8))
-#define HW_ICOLL_VBASE_TOG              (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x160 + 0xc))
-#define BP_ICOLL_VBASE_TABLE_ADDRESS    2
-#define BM_ICOLL_VBASE_TABLE_ADDRESS    0xfffffffc
-#define BF_ICOLL_VBASE_TABLE_ADDRESS(v) (((v) << 2) & 0xfffffffc)
-
-/**
- * Register: HW_ICOLL_DEBUG
- * Address: 0x170
- * SCT: no
-*/
-#define HW_ICOLL_DEBUG                              (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x170))
-#define BP_ICOLL_DEBUG_INSERVICE                    28
-#define BM_ICOLL_DEBUG_INSERVICE                    0xf0000000
-#define BV_ICOLL_DEBUG_INSERVICE__LEVEL0            0x1
-#define BV_ICOLL_DEBUG_INSERVICE__LEVEL1            0x2
-#define BV_ICOLL_DEBUG_INSERVICE__LEVEL2            0x4
-#define BV_ICOLL_DEBUG_INSERVICE__LEVEL3            0x8
-#define BF_ICOLL_DEBUG_INSERVICE(v)                 (((v) << 28) & 0xf0000000)
-#define BF_ICOLL_DEBUG_INSERVICE_V(v)               ((BV_ICOLL_DEBUG_INSERVICE__##v << 28) & 0xf0000000)
-#define BP_ICOLL_DEBUG_LEVEL_REQUESTS               24
-#define BM_ICOLL_DEBUG_LEVEL_REQUESTS               0xf000000
-#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL0       0x1
-#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL1       0x2
-#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL2       0x4
-#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL3       0x8
-#define BF_ICOLL_DEBUG_LEVEL_REQUESTS(v)            (((v) << 24) & 0xf000000)
-#define BF_ICOLL_DEBUG_LEVEL_REQUESTS_V(v)          ((BV_ICOLL_DEBUG_LEVEL_REQUESTS__##v << 24) & 0xf000000)
-#define BP_ICOLL_DEBUG_REQUESTS_BY_LEVEL            20
-#define BM_ICOLL_DEBUG_REQUESTS_BY_LEVEL            0xf00000
-#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL0    0x1
-#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL1    0x2
-#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL2    0x4
-#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL3    0x8
-#define BF_ICOLL_DEBUG_REQUESTS_BY_LEVEL(v)         (((v) << 20) & 0xf00000)
-#define BF_ICOLL_DEBUG_REQUESTS_BY_LEVEL_V(v)       ((BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__##v << 20) & 0xf00000)
-#define BP_ICOLL_DEBUG_FIQ                          17
-#define BM_ICOLL_DEBUG_FIQ                          0x20000
-#define BV_ICOLL_DEBUG_FIQ__NO_FIQ_REQUESTED        0x0
-#define BV_ICOLL_DEBUG_FIQ__FIQ_REQUESTED           0x1
-#define BF_ICOLL_DEBUG_FIQ(v)                       (((v) << 17) & 0x20000)
-#define BF_ICOLL_DEBUG_FIQ_V(v)                     ((BV_ICOLL_DEBUG_FIQ__##v << 17) & 0x20000)
-#define BP_ICOLL_DEBUG_IRQ                          16
-#define BM_ICOLL_DEBUG_IRQ                          0x10000
-#define BV_ICOLL_DEBUG_IRQ__NO_IRQ_REQUESTED        0x0
-#define BV_ICOLL_DEBUG_IRQ__IRQ_REQUESTED           0x1
-#define BF_ICOLL_DEBUG_IRQ(v)                       (((v) << 16) & 0x10000)
-#define BF_ICOLL_DEBUG_IRQ_V(v)                     ((BV_ICOLL_DEBUG_IRQ__##v << 16) & 0x10000)
-#define BP_ICOLL_DEBUG_VECTOR_FSM                   0
-#define BM_ICOLL_DEBUG_VECTOR_FSM                   0x3ff
-#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_IDLE         0x0
-#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE1  0x1
-#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE2  0x2
-#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_PENDING      0x4
-#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE3  0x8
-#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE4  0x10
-#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING1 0x20
-#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING2 0x40
-#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING3 0x80
-#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE5  0x100
-#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE6  0x200
-#define BF_ICOLL_DEBUG_VECTOR_FSM(v)                (((v) << 0) & 0x3ff)
-#define BF_ICOLL_DEBUG_VECTOR_FSM_V(v)              ((BV_ICOLL_DEBUG_VECTOR_FSM__##v << 0) & 0x3ff)
-
-/**
- * Register: HW_ICOLL_DBGREAD0
- * Address: 0x180
- * SCT: no
-*/
-#define HW_ICOLL_DBGREAD0           (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x180))
-#define BP_ICOLL_DBGREAD0_VALUE     0
-#define BM_ICOLL_DBGREAD0_VALUE     0xffffffff
-#define BF_ICOLL_DBGREAD0_VALUE(v)  (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_ICOLL_DBGREAD1
- * Address: 0x190
- * SCT: no
-*/
-#define HW_ICOLL_DBGREAD1           (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x190))
-#define BP_ICOLL_DBGREAD1_VALUE     0
-#define BM_ICOLL_DBGREAD1_VALUE     0xffffffff
-#define BF_ICOLL_DBGREAD1_VALUE(v)  (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_ICOLL_DBGFLAG
- * Address: 0x1a0
- * SCT: yes
-*/
-#define HW_ICOLL_DBGFLAG            (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1a0 + 0x0))
-#define HW_ICOLL_DBGFLAG_SET        (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1a0 + 0x4))
-#define HW_ICOLL_DBGFLAG_CLR        (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1a0 + 0x8))
-#define HW_ICOLL_DBGFLAG_TOG        (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1a0 + 0xc))
-#define BP_ICOLL_DBGFLAG_FLAG       0
-#define BM_ICOLL_DBGFLAG_FLAG       0xffff
-#define BF_ICOLL_DBGFLAG_FLAG(v)    (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_ICOLL_DBGREQUESTn
- * Address: 0x1b0+n*0x10
- * SCT: no
-*/
-#define HW_ICOLL_DBGREQUESTn(n)         (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1b0+(n)*0x10))
-#define BP_ICOLL_DBGREQUESTn_BITS       0
-#define BM_ICOLL_DBGREQUESTn_BITS       0xffffffff
-#define BF_ICOLL_DBGREQUESTn_BITS(v)    (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_ICOLL_VERSION
- * Address: 0x1d0
- * SCT: no
-*/
-#define HW_ICOLL_VERSION            (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1d0))
-#define BP_ICOLL_VERSION_MAJOR      24
-#define BM_ICOLL_VERSION_MAJOR      0xff000000
-#define BF_ICOLL_VERSION_MAJOR(v)   (((v) << 24) & 0xff000000)
-#define BP_ICOLL_VERSION_MINOR      16
-#define BM_ICOLL_VERSION_MINOR      0xff0000
-#define BF_ICOLL_VERSION_MINOR(v)   (((v) << 16) & 0xff0000)
-#define BP_ICOLL_VERSION_STEP       0
-#define BM_ICOLL_VERSION_STEP       0xffff
-#define BF_ICOLL_VERSION_STEP(v)    (((v) << 0) & 0xffff)
-
-#endif /* __HEADERGEN__STMP3700__ICOLL__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-ir.h b/firmware/target/arm/imx233/regs/stmp3700/regs-ir.h
deleted file mode 100644
index b326b2449f..0000000000
--- a/firmware/target/arm/imx233/regs/stmp3700/regs-ir.h
+++ /dev/null
@@ -1,493 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3700:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__STMP3700__IR__H__
-#define __HEADERGEN__STMP3700__IR__H__
-
-#define REGS_IR_BASE (0x80078000)
-
-#define REGS_IR_VERSION "3.2.0"
-
-/**
- * Register: HW_IR_CTRL
- * Address: 0
- * SCT: yes
-*/
-#define HW_IR_CTRL                  (*(volatile unsigned long *)(REGS_IR_BASE + 0x0 + 0x0))
-#define HW_IR_CTRL_SET              (*(volatile unsigned long *)(REGS_IR_BASE + 0x0 + 0x4))
-#define HW_IR_CTRL_CLR              (*(volatile unsigned long *)(REGS_IR_BASE + 0x0 + 0x8))
-#define HW_IR_CTRL_TOG              (*(volatile unsigned long *)(REGS_IR_BASE + 0x0 + 0xc))
-#define BP_IR_CTRL_SFTRST           31
-#define BM_IR_CTRL_SFTRST           0x80000000
-#define BV_IR_CTRL_SFTRST__RUN      0x0
-#define BV_IR_CTRL_SFTRST__RESET    0x1
-#define BF_IR_CTRL_SFTRST(v)        (((v) << 31) & 0x80000000)
-#define BF_IR_CTRL_SFTRST_V(v)      ((BV_IR_CTRL_SFTRST__##v << 31) & 0x80000000)
-#define BP_IR_CTRL_CLKGATE          30
-#define BM_IR_CTRL_CLKGATE          0x40000000
-#define BF_IR_CTRL_CLKGATE(v)       (((v) << 30) & 0x40000000)
-#define BP_IR_CTRL_MTA              24
-#define BM_IR_CTRL_MTA              0x7000000
-#define BV_IR_CTRL_MTA__MTA_10MS    0x0
-#define BV_IR_CTRL_MTA__MTA_5MS     0x1
-#define BV_IR_CTRL_MTA__MTA_1MS     0x2
-#define BV_IR_CTRL_MTA__MTA_500US   0x3
-#define BV_IR_CTRL_MTA__MTA_100US   0x4
-#define BV_IR_CTRL_MTA__MTA_50US    0x5
-#define BV_IR_CTRL_MTA__MTA_10US    0x6
-#define BV_IR_CTRL_MTA__MTA_0       0x7
-#define BF_IR_CTRL_MTA(v)           (((v) << 24) & 0x7000000)
-#define BF_IR_CTRL_MTA_V(v)         ((BV_IR_CTRL_MTA__##v << 24) & 0x7000000)
-#define BP_IR_CTRL_MODE             22
-#define BM_IR_CTRL_MODE             0xc00000
-#define BV_IR_CTRL_MODE__SIR        0x0
-#define BV_IR_CTRL_MODE__MIR        0x1
-#define BV_IR_CTRL_MODE__FIR        0x2
-#define BV_IR_CTRL_MODE__VFIR       0x3
-#define BF_IR_CTRL_MODE(v)          (((v) << 22) & 0xc00000)
-#define BF_IR_CTRL_MODE_V(v)        ((BV_IR_CTRL_MODE__##v << 22) & 0xc00000)
-#define BP_IR_CTRL_SPEED            19
-#define BM_IR_CTRL_SPEED            0x380000
-#define BV_IR_CTRL_SPEED__SPD000    0x0
-#define BV_IR_CTRL_SPEED__SPD001    0x1
-#define BV_IR_CTRL_SPEED__SPD010    0x2
-#define BV_IR_CTRL_SPEED__SPD011    0x3
-#define BV_IR_CTRL_SPEED__SPD100    0x4
-#define BV_IR_CTRL_SPEED__SPD101    0x5
-#define BF_IR_CTRL_SPEED(v)         (((v) << 19) & 0x380000)
-#define BF_IR_CTRL_SPEED_V(v)       ((BV_IR_CTRL_SPEED__##v << 19) & 0x380000)
-#define BP_IR_CTRL_TC_TIME_DIV      8
-#define BM_IR_CTRL_TC_TIME_DIV      0x3f00
-#define BF_IR_CTRL_TC_TIME_DIV(v)   (((v) << 8) & 0x3f00)
-#define BP_IR_CTRL_TC_TYPE          7
-#define BM_IR_CTRL_TC_TYPE          0x80
-#define BF_IR_CTRL_TC_TYPE(v)       (((v) << 7) & 0x80)
-#define BP_IR_CTRL_SIR_GAP          4
-#define BM_IR_CTRL_SIR_GAP          0x70
-#define BV_IR_CTRL_SIR_GAP__GAP_10K 0x0
-#define BV_IR_CTRL_SIR_GAP__GAP_5K  0x1
-#define BV_IR_CTRL_SIR_GAP__GAP_1K  0x2
-#define BV_IR_CTRL_SIR_GAP__GAP_500 0x3
-#define BV_IR_CTRL_SIR_GAP__GAP_100 0x4
-#define BV_IR_CTRL_SIR_GAP__GAP_50  0x5
-#define BV_IR_CTRL_SIR_GAP__GAP_10  0x6
-#define BV_IR_CTRL_SIR_GAP__GAP_0   0x7
-#define BF_IR_CTRL_SIR_GAP(v)       (((v) << 4) & 0x70)
-#define BF_IR_CTRL_SIR_GAP_V(v)     ((BV_IR_CTRL_SIR_GAP__##v << 4) & 0x70)
-#define BP_IR_CTRL_SIPEN            3
-#define BM_IR_CTRL_SIPEN            0x8
-#define BF_IR_CTRL_SIPEN(v)         (((v) << 3) & 0x8)
-#define BP_IR_CTRL_TCEN             2
-#define BM_IR_CTRL_TCEN             0x4
-#define BF_IR_CTRL_TCEN(v)          (((v) << 2) & 0x4)
-#define BP_IR_CTRL_TXEN             1
-#define BM_IR_CTRL_TXEN             0x2
-#define BF_IR_CTRL_TXEN(v)          (((v) << 1) & 0x2)
-#define BP_IR_CTRL_RXEN             0
-#define BM_IR_CTRL_RXEN             0x1
-#define BF_IR_CTRL_RXEN(v)          (((v) << 0) & 0x1)
-
-/**
- * Register: HW_IR_TXDMA
- * Address: 0x10
- * SCT: yes
-*/
-#define HW_IR_TXDMA                 (*(volatile unsigned long *)(REGS_IR_BASE + 0x10 + 0x0))
-#define HW_IR_TXDMA_SET             (*(volatile unsigned long *)(REGS_IR_BASE + 0x10 + 0x4))
-#define HW_IR_TXDMA_CLR             (*(volatile unsigned long *)(REGS_IR_BASE + 0x10 + 0x8))
-#define HW_IR_TXDMA_TOG             (*(volatile unsigned long *)(REGS_IR_BASE + 0x10 + 0xc))
-#define BP_IR_TXDMA_RUN             31
-#define BM_IR_TXDMA_RUN             0x80000000
-#define BF_IR_TXDMA_RUN(v)          (((v) << 31) & 0x80000000)
-#define BP_IR_TXDMA_EMPTY           29
-#define BM_IR_TXDMA_EMPTY           0x20000000
-#define BF_IR_TXDMA_EMPTY(v)        (((v) << 29) & 0x20000000)
-#define BP_IR_TXDMA_INT             28
-#define BM_IR_TXDMA_INT             0x10000000
-#define BF_IR_TXDMA_INT(v)          (((v) << 28) & 0x10000000)
-#define BP_IR_TXDMA_CHANGE          27
-#define BM_IR_TXDMA_CHANGE          0x8000000
-#define BF_IR_TXDMA_CHANGE(v)       (((v) << 27) & 0x8000000)
-#define BP_IR_TXDMA_NEW_MTA         24
-#define BM_IR_TXDMA_NEW_MTA         0x7000000
-#define BF_IR_TXDMA_NEW_MTA(v)      (((v) << 24) & 0x7000000)
-#define BP_IR_TXDMA_NEW_MODE        22
-#define BM_IR_TXDMA_NEW_MODE        0xc00000
-#define BF_IR_TXDMA_NEW_MODE(v)     (((v) << 22) & 0xc00000)
-#define BP_IR_TXDMA_NEW_SPEED       19
-#define BM_IR_TXDMA_NEW_SPEED       0x380000
-#define BF_IR_TXDMA_NEW_SPEED(v)    (((v) << 19) & 0x380000)
-#define BP_IR_TXDMA_BOF_TYPE        18
-#define BM_IR_TXDMA_BOF_TYPE        0x40000
-#define BF_IR_TXDMA_BOF_TYPE(v)     (((v) << 18) & 0x40000)
-#define BP_IR_TXDMA_XBOFS           12
-#define BM_IR_TXDMA_XBOFS           0x3f000
-#define BF_IR_TXDMA_XBOFS(v)        (((v) << 12) & 0x3f000)
-#define BP_IR_TXDMA_XFER_COUNT      0
-#define BM_IR_TXDMA_XFER_COUNT      0xfff
-#define BF_IR_TXDMA_XFER_COUNT(v)   (((v) << 0) & 0xfff)
-
-/**
- * Register: HW_IR_RXDMA
- * Address: 0x20
- * SCT: yes
-*/
-#define HW_IR_RXDMA                 (*(volatile unsigned long *)(REGS_IR_BASE + 0x20 + 0x0))
-#define HW_IR_RXDMA_SET             (*(volatile unsigned long *)(REGS_IR_BASE + 0x20 + 0x4))
-#define HW_IR_RXDMA_CLR             (*(volatile unsigned long *)(REGS_IR_BASE + 0x20 + 0x8))
-#define HW_IR_RXDMA_TOG             (*(volatile unsigned long *)(REGS_IR_BASE + 0x20 + 0xc))
-#define BP_IR_RXDMA_RUN             31
-#define BM_IR_RXDMA_RUN             0x80000000
-#define BF_IR_RXDMA_RUN(v)          (((v) << 31) & 0x80000000)
-#define BP_IR_RXDMA_XFER_COUNT      0
-#define BM_IR_RXDMA_XFER_COUNT      0x3ff
-#define BF_IR_RXDMA_XFER_COUNT(v)   (((v) << 0) & 0x3ff)
-
-/**
- * Register: HW_IR_DBGCTRL
- * Address: 0x30
- * SCT: yes
-*/
-#define HW_IR_DBGCTRL                   (*(volatile unsigned long *)(REGS_IR_BASE + 0x30 + 0x0))
-#define HW_IR_DBGCTRL_SET               (*(volatile unsigned long *)(REGS_IR_BASE + 0x30 + 0x4))
-#define HW_IR_DBGCTRL_CLR               (*(volatile unsigned long *)(REGS_IR_BASE + 0x30 + 0x8))
-#define HW_IR_DBGCTRL_TOG               (*(volatile unsigned long *)(REGS_IR_BASE + 0x30 + 0xc))
-#define BP_IR_DBGCTRL_VFIRSWZ           12
-#define BM_IR_DBGCTRL_VFIRSWZ           0x1000
-#define BV_IR_DBGCTRL_VFIRSWZ__NORMAL   0x0
-#define BV_IR_DBGCTRL_VFIRSWZ__SWAP     0x1
-#define BF_IR_DBGCTRL_VFIRSWZ(v)        (((v) << 12) & 0x1000)
-#define BF_IR_DBGCTRL_VFIRSWZ_V(v)      ((BV_IR_DBGCTRL_VFIRSWZ__##v << 12) & 0x1000)
-#define BP_IR_DBGCTRL_RXFRMOFF          11
-#define BM_IR_DBGCTRL_RXFRMOFF          0x800
-#define BF_IR_DBGCTRL_RXFRMOFF(v)       (((v) << 11) & 0x800)
-#define BP_IR_DBGCTRL_RXCRCOFF          10
-#define BM_IR_DBGCTRL_RXCRCOFF          0x400
-#define BF_IR_DBGCTRL_RXCRCOFF(v)       (((v) << 10) & 0x400)
-#define BP_IR_DBGCTRL_RXINVERT          9
-#define BM_IR_DBGCTRL_RXINVERT          0x200
-#define BF_IR_DBGCTRL_RXINVERT(v)       (((v) << 9) & 0x200)
-#define BP_IR_DBGCTRL_TXFRMOFF          8
-#define BM_IR_DBGCTRL_TXFRMOFF          0x100
-#define BF_IR_DBGCTRL_TXFRMOFF(v)       (((v) << 8) & 0x100)
-#define BP_IR_DBGCTRL_TXCRCOFF          7
-#define BM_IR_DBGCTRL_TXCRCOFF          0x80
-#define BF_IR_DBGCTRL_TXCRCOFF(v)       (((v) << 7) & 0x80)
-#define BP_IR_DBGCTRL_TXINVERT          6
-#define BM_IR_DBGCTRL_TXINVERT          0x40
-#define BF_IR_DBGCTRL_TXINVERT(v)       (((v) << 6) & 0x40)
-#define BP_IR_DBGCTRL_INTLOOPBACK       5
-#define BM_IR_DBGCTRL_INTLOOPBACK       0x20
-#define BF_IR_DBGCTRL_INTLOOPBACK(v)    (((v) << 5) & 0x20)
-#define BP_IR_DBGCTRL_DUPLEX            4
-#define BM_IR_DBGCTRL_DUPLEX            0x10
-#define BF_IR_DBGCTRL_DUPLEX(v)         (((v) << 4) & 0x10)
-#define BP_IR_DBGCTRL_MIO_RX            3
-#define BM_IR_DBGCTRL_MIO_RX            0x8
-#define BF_IR_DBGCTRL_MIO_RX(v)         (((v) << 3) & 0x8)
-#define BP_IR_DBGCTRL_MIO_TX            2
-#define BM_IR_DBGCTRL_MIO_TX            0x4
-#define BF_IR_DBGCTRL_MIO_TX(v)         (((v) << 2) & 0x4)
-#define BP_IR_DBGCTRL_MIO_SCLK          1
-#define BM_IR_DBGCTRL_MIO_SCLK          0x2
-#define BF_IR_DBGCTRL_MIO_SCLK(v)       (((v) << 1) & 0x2)
-#define BP_IR_DBGCTRL_MIO_EN            0
-#define BM_IR_DBGCTRL_MIO_EN            0x1
-#define BF_IR_DBGCTRL_MIO_EN(v)         (((v) << 0) & 0x1)
-
-/**
- * Register: HW_IR_INTR
- * Address: 0x40
- * SCT: yes
-*/
-#define HW_IR_INTR                          (*(volatile unsigned long *)(REGS_IR_BASE + 0x40 + 0x0))
-#define HW_IR_INTR_SET                      (*(volatile unsigned long *)(REGS_IR_BASE + 0x40 + 0x4))
-#define HW_IR_INTR_CLR                      (*(volatile unsigned long *)(REGS_IR_BASE + 0x40 + 0x8))
-#define HW_IR_INTR_TOG                      (*(volatile unsigned long *)(REGS_IR_BASE + 0x40 + 0xc))
-#define BP_IR_INTR_RXABORT_IRQ_EN           22
-#define BM_IR_INTR_RXABORT_IRQ_EN           0x400000
-#define BV_IR_INTR_RXABORT_IRQ_EN__DISABLED 0x0
-#define BV_IR_INTR_RXABORT_IRQ_EN__ENABLED  0x1
-#define BF_IR_INTR_RXABORT_IRQ_EN(v)        (((v) << 22) & 0x400000)
-#define BF_IR_INTR_RXABORT_IRQ_EN_V(v)      ((BV_IR_INTR_RXABORT_IRQ_EN__##v << 22) & 0x400000)
-#define BP_IR_INTR_SPEED_IRQ_EN             21
-#define BM_IR_INTR_SPEED_IRQ_EN             0x200000
-#define BV_IR_INTR_SPEED_IRQ_EN__DISABLED   0x0
-#define BV_IR_INTR_SPEED_IRQ_EN__ENABLED    0x1
-#define BF_IR_INTR_SPEED_IRQ_EN(v)          (((v) << 21) & 0x200000)
-#define BF_IR_INTR_SPEED_IRQ_EN_V(v)        ((BV_IR_INTR_SPEED_IRQ_EN__##v << 21) & 0x200000)
-#define BP_IR_INTR_RXOF_IRQ_EN              20
-#define BM_IR_INTR_RXOF_IRQ_EN              0x100000
-#define BV_IR_INTR_RXOF_IRQ_EN__DISABLED    0x0
-#define BV_IR_INTR_RXOF_IRQ_EN__ENABLED     0x1
-#define BF_IR_INTR_RXOF_IRQ_EN(v)           (((v) << 20) & 0x100000)
-#define BF_IR_INTR_RXOF_IRQ_EN_V(v)         ((BV_IR_INTR_RXOF_IRQ_EN__##v << 20) & 0x100000)
-#define BP_IR_INTR_TXUF_IRQ_EN              19
-#define BM_IR_INTR_TXUF_IRQ_EN              0x80000
-#define BV_IR_INTR_TXUF_IRQ_EN__DISABLED    0x0
-#define BV_IR_INTR_TXUF_IRQ_EN__ENABLED     0x1
-#define BF_IR_INTR_TXUF_IRQ_EN(v)           (((v) << 19) & 0x80000)
-#define BF_IR_INTR_TXUF_IRQ_EN_V(v)         ((BV_IR_INTR_TXUF_IRQ_EN__##v << 19) & 0x80000)
-#define BP_IR_INTR_TC_IRQ_EN                18
-#define BM_IR_INTR_TC_IRQ_EN                0x40000
-#define BV_IR_INTR_TC_IRQ_EN__DISABLED      0x0
-#define BV_IR_INTR_TC_IRQ_EN__ENABLED       0x1
-#define BF_IR_INTR_TC_IRQ_EN(v)             (((v) << 18) & 0x40000)
-#define BF_IR_INTR_TC_IRQ_EN_V(v)           ((BV_IR_INTR_TC_IRQ_EN__##v << 18) & 0x40000)
-#define BP_IR_INTR_RX_IRQ_EN                17
-#define BM_IR_INTR_RX_IRQ_EN                0x20000
-#define BV_IR_INTR_RX_IRQ_EN__DISABLED      0x0
-#define BV_IR_INTR_RX_IRQ_EN__ENABLED       0x1
-#define BF_IR_INTR_RX_IRQ_EN(v)             (((v) << 17) & 0x20000)
-#define BF_IR_INTR_RX_IRQ_EN_V(v)           ((BV_IR_INTR_RX_IRQ_EN__##v << 17) & 0x20000)
-#define BP_IR_INTR_TX_IRQ_EN                16
-#define BM_IR_INTR_TX_IRQ_EN                0x10000
-#define BV_IR_INTR_TX_IRQ_EN__DISABLED      0x0
-#define BV_IR_INTR_TX_IRQ_EN__ENABLED       0x1
-#define BF_IR_INTR_TX_IRQ_EN(v)             (((v) << 16) & 0x10000)
-#define BF_IR_INTR_TX_IRQ_EN_V(v)           ((BV_IR_INTR_TX_IRQ_EN__##v << 16) & 0x10000)
-#define BP_IR_INTR_RXABORT_IRQ              6
-#define BM_IR_INTR_RXABORT_IRQ              0x40
-#define BV_IR_INTR_RXABORT_IRQ__NO_REQUEST  0x0
-#define BV_IR_INTR_RXABORT_IRQ__REQUEST     0x1
-#define BF_IR_INTR_RXABORT_IRQ(v)           (((v) << 6) & 0x40)
-#define BF_IR_INTR_RXABORT_IRQ_V(v)         ((BV_IR_INTR_RXABORT_IRQ__##v << 6) & 0x40)
-#define BP_IR_INTR_SPEED_IRQ                5
-#define BM_IR_INTR_SPEED_IRQ                0x20
-#define BV_IR_INTR_SPEED_IRQ__NO_REQUEST    0x0
-#define BV_IR_INTR_SPEED_IRQ__REQUEST       0x1
-#define BF_IR_INTR_SPEED_IRQ(v)             (((v) << 5) & 0x20)
-#define BF_IR_INTR_SPEED_IRQ_V(v)           ((BV_IR_INTR_SPEED_IRQ__##v << 5) & 0x20)
-#define BP_IR_INTR_RXOF_IRQ                 4
-#define BM_IR_INTR_RXOF_IRQ                 0x10
-#define BV_IR_INTR_RXOF_IRQ__NO_REQUEST     0x0
-#define BV_IR_INTR_RXOF_IRQ__REQUEST        0x1
-#define BF_IR_INTR_RXOF_IRQ(v)              (((v) << 4) & 0x10)
-#define BF_IR_INTR_RXOF_IRQ_V(v)            ((BV_IR_INTR_RXOF_IRQ__##v << 4) & 0x10)
-#define BP_IR_INTR_TXUF_IRQ                 3
-#define BM_IR_INTR_TXUF_IRQ                 0x8
-#define BV_IR_INTR_TXUF_IRQ__NO_REQUEST     0x0
-#define BV_IR_INTR_TXUF_IRQ__REQUEST        0x1
-#define BF_IR_INTR_TXUF_IRQ(v)              (((v) << 3) & 0x8)
-#define BF_IR_INTR_TXUF_IRQ_V(v)            ((BV_IR_INTR_TXUF_IRQ__##v << 3) & 0x8)
-#define BP_IR_INTR_TC_IRQ                   2
-#define BM_IR_INTR_TC_IRQ                   0x4
-#define BV_IR_INTR_TC_IRQ__NO_REQUEST       0x0
-#define BV_IR_INTR_TC_IRQ__REQUEST          0x1
-#define BF_IR_INTR_TC_IRQ(v)                (((v) << 2) & 0x4)
-#define BF_IR_INTR_TC_IRQ_V(v)              ((BV_IR_INTR_TC_IRQ__##v << 2) & 0x4)
-#define BP_IR_INTR_RX_IRQ                   1
-#define BM_IR_INTR_RX_IRQ                   0x2
-#define BV_IR_INTR_RX_IRQ__NO_REQUEST       0x0
-#define BV_IR_INTR_RX_IRQ__REQUEST          0x1
-#define BF_IR_INTR_RX_IRQ(v)                (((v) << 1) & 0x2)
-#define BF_IR_INTR_RX_IRQ_V(v)              ((BV_IR_INTR_RX_IRQ__##v << 1) & 0x2)
-#define BP_IR_INTR_TX_IRQ                   0
-#define BM_IR_INTR_TX_IRQ                   0x1
-#define BV_IR_INTR_TX_IRQ__NO_REQUEST       0x0
-#define BV_IR_INTR_TX_IRQ__REQUEST          0x1
-#define BF_IR_INTR_TX_IRQ(v)                (((v) << 0) & 0x1)
-#define BF_IR_INTR_TX_IRQ_V(v)              ((BV_IR_INTR_TX_IRQ__##v << 0) & 0x1)
-
-/**
- * Register: HW_IR_DATA
- * Address: 0x50
- * SCT: no
-*/
-#define HW_IR_DATA          (*(volatile unsigned long *)(REGS_IR_BASE + 0x50))
-#define BP_IR_DATA_DATA     0
-#define BM_IR_DATA_DATA     0xffffffff
-#define BF_IR_DATA_DATA(v)  (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_IR_STAT
- * Address: 0x60
- * SCT: no
-*/
-#define HW_IR_STAT                              (*(volatile unsigned long *)(REGS_IR_BASE + 0x60))
-#define BP_IR_STAT_PRESENT                      31
-#define BM_IR_STAT_PRESENT                      0x80000000
-#define BV_IR_STAT_PRESENT__UNAVAILABLE         0x0
-#define BV_IR_STAT_PRESENT__AVAILABLE           0x1
-#define BF_IR_STAT_PRESENT(v)                   (((v) << 31) & 0x80000000)
-#define BF_IR_STAT_PRESENT_V(v)                 ((BV_IR_STAT_PRESENT__##v << 31) & 0x80000000)
-#define BP_IR_STAT_MODE_ALLOWED                 29
-#define BM_IR_STAT_MODE_ALLOWED                 0x60000000
-#define BV_IR_STAT_MODE_ALLOWED__VFIR           0x0
-#define BV_IR_STAT_MODE_ALLOWED__FIR            0x1
-#define BV_IR_STAT_MODE_ALLOWED__MIR            0x2
-#define BV_IR_STAT_MODE_ALLOWED__SIR            0x3
-#define BF_IR_STAT_MODE_ALLOWED(v)              (((v) << 29) & 0x60000000)
-#define BF_IR_STAT_MODE_ALLOWED_V(v)            ((BV_IR_STAT_MODE_ALLOWED__##v << 29) & 0x60000000)
-#define BP_IR_STAT_ANY_IRQ                      28
-#define BM_IR_STAT_ANY_IRQ                      0x10000000
-#define BV_IR_STAT_ANY_IRQ__NO_REQUEST          0x0
-#define BV_IR_STAT_ANY_IRQ__REQUEST             0x1
-#define BF_IR_STAT_ANY_IRQ(v)                   (((v) << 28) & 0x10000000)
-#define BF_IR_STAT_ANY_IRQ_V(v)                 ((BV_IR_STAT_ANY_IRQ__##v << 28) & 0x10000000)
-#define BP_IR_STAT_RXABORT_SUMMARY              22
-#define BM_IR_STAT_RXABORT_SUMMARY              0x400000
-#define BV_IR_STAT_RXABORT_SUMMARY__NO_REQUEST  0x0
-#define BV_IR_STAT_RXABORT_SUMMARY__REQUEST     0x1
-#define BF_IR_STAT_RXABORT_SUMMARY(v)           (((v) << 22) & 0x400000)
-#define BF_IR_STAT_RXABORT_SUMMARY_V(v)         ((BV_IR_STAT_RXABORT_SUMMARY__##v << 22) & 0x400000)
-#define BP_IR_STAT_SPEED_SUMMARY                21
-#define BM_IR_STAT_SPEED_SUMMARY                0x200000
-#define BV_IR_STAT_SPEED_SUMMARY__NO_REQUEST    0x0
-#define BV_IR_STAT_SPEED_SUMMARY__REQUEST       0x1
-#define BF_IR_STAT_SPEED_SUMMARY(v)             (((v) << 21) & 0x200000)
-#define BF_IR_STAT_SPEED_SUMMARY_V(v)           ((BV_IR_STAT_SPEED_SUMMARY__##v << 21) & 0x200000)
-#define BP_IR_STAT_RXOF_SUMMARY                 20
-#define BM_IR_STAT_RXOF_SUMMARY                 0x100000
-#define BV_IR_STAT_RXOF_SUMMARY__NO_REQUEST     0x0
-#define BV_IR_STAT_RXOF_SUMMARY__REQUEST        0x1
-#define BF_IR_STAT_RXOF_SUMMARY(v)              (((v) << 20) & 0x100000)
-#define BF_IR_STAT_RXOF_SUMMARY_V(v)            ((BV_IR_STAT_RXOF_SUMMARY__##v << 20) & 0x100000)
-#define BP_IR_STAT_TXUF_SUMMARY                 19
-#define BM_IR_STAT_TXUF_SUMMARY                 0x80000
-#define BV_IR_STAT_TXUF_SUMMARY__NO_REQUEST     0x0
-#define BV_IR_STAT_TXUF_SUMMARY__REQUEST        0x1
-#define BF_IR_STAT_TXUF_SUMMARY(v)              (((v) << 19) & 0x80000)
-#define BF_IR_STAT_TXUF_SUMMARY_V(v)            ((BV_IR_STAT_TXUF_SUMMARY__##v << 19) & 0x80000)
-#define BP_IR_STAT_TC_SUMMARY                   18
-#define BM_IR_STAT_TC_SUMMARY                   0x40000
-#define BV_IR_STAT_TC_SUMMARY__NO_REQUEST       0x0
-#define BV_IR_STAT_TC_SUMMARY__REQUEST          0x1
-#define BF_IR_STAT_TC_SUMMARY(v)                (((v) << 18) & 0x40000)
-#define BF_IR_STAT_TC_SUMMARY_V(v)              ((BV_IR_STAT_TC_SUMMARY__##v << 18) & 0x40000)
-#define BP_IR_STAT_RX_SUMMARY                   17
-#define BM_IR_STAT_RX_SUMMARY                   0x20000
-#define BV_IR_STAT_RX_SUMMARY__NO_REQUEST       0x0
-#define BV_IR_STAT_RX_SUMMARY__REQUEST          0x1
-#define BF_IR_STAT_RX_SUMMARY(v)                (((v) << 17) & 0x20000)
-#define BF_IR_STAT_RX_SUMMARY_V(v)              ((BV_IR_STAT_RX_SUMMARY__##v << 17) & 0x20000)
-#define BP_IR_STAT_TX_SUMMARY                   16
-#define BM_IR_STAT_TX_SUMMARY                   0x10000
-#define BV_IR_STAT_TX_SUMMARY__NO_REQUEST       0x0
-#define BV_IR_STAT_TX_SUMMARY__REQUEST          0x1
-#define BF_IR_STAT_TX_SUMMARY(v)                (((v) << 16) & 0x10000)
-#define BF_IR_STAT_TX_SUMMARY_V(v)              ((BV_IR_STAT_TX_SUMMARY__##v << 16) & 0x10000)
-#define BP_IR_STAT_MEDIA_BUSY                   2
-#define BM_IR_STAT_MEDIA_BUSY                   0x4
-#define BF_IR_STAT_MEDIA_BUSY(v)                (((v) << 2) & 0x4)
-#define BP_IR_STAT_RX_ACTIVE                    1
-#define BM_IR_STAT_RX_ACTIVE                    0x2
-#define BF_IR_STAT_RX_ACTIVE(v)                 (((v) << 1) & 0x2)
-#define BP_IR_STAT_TX_ACTIVE                    0
-#define BM_IR_STAT_TX_ACTIVE                    0x1
-#define BF_IR_STAT_TX_ACTIVE(v)                 (((v) << 0) & 0x1)
-
-/**
- * Register: HW_IR_TCCTRL
- * Address: 0x70
- * SCT: yes
-*/
-#define HW_IR_TCCTRL                (*(volatile unsigned long *)(REGS_IR_BASE + 0x70 + 0x0))
-#define HW_IR_TCCTRL_SET            (*(volatile unsigned long *)(REGS_IR_BASE + 0x70 + 0x4))
-#define HW_IR_TCCTRL_CLR            (*(volatile unsigned long *)(REGS_IR_BASE + 0x70 + 0x8))
-#define HW_IR_TCCTRL_TOG            (*(volatile unsigned long *)(REGS_IR_BASE + 0x70 + 0xc))
-#define BP_IR_TCCTRL_INIT           31
-#define BM_IR_TCCTRL_INIT           0x80000000
-#define BF_IR_TCCTRL_INIT(v)        (((v) << 31) & 0x80000000)
-#define BP_IR_TCCTRL_GO             30
-#define BM_IR_TCCTRL_GO             0x40000000
-#define BF_IR_TCCTRL_GO(v)          (((v) << 30) & 0x40000000)
-#define BP_IR_TCCTRL_BUSY           29
-#define BM_IR_TCCTRL_BUSY           0x20000000
-#define BF_IR_TCCTRL_BUSY(v)        (((v) << 29) & 0x20000000)
-#define BP_IR_TCCTRL_TEMIC          24
-#define BM_IR_TCCTRL_TEMIC          0x1000000
-#define BV_IR_TCCTRL_TEMIC__LOW     0x0
-#define BV_IR_TCCTRL_TEMIC__HIGH    0x1
-#define BF_IR_TCCTRL_TEMIC(v)       (((v) << 24) & 0x1000000)
-#define BF_IR_TCCTRL_TEMIC_V(v)     ((BV_IR_TCCTRL_TEMIC__##v << 24) & 0x1000000)
-#define BP_IR_TCCTRL_EXT_DATA       16
-#define BM_IR_TCCTRL_EXT_DATA       0xff0000
-#define BF_IR_TCCTRL_EXT_DATA(v)    (((v) << 16) & 0xff0000)
-#define BP_IR_TCCTRL_DATA           8
-#define BM_IR_TCCTRL_DATA           0xff00
-#define BF_IR_TCCTRL_DATA(v)        (((v) << 8) & 0xff00)
-#define BP_IR_TCCTRL_ADDR           5
-#define BM_IR_TCCTRL_ADDR           0xe0
-#define BF_IR_TCCTRL_ADDR(v)        (((v) << 5) & 0xe0)
-#define BP_IR_TCCTRL_INDX           1
-#define BM_IR_TCCTRL_INDX           0x1e
-#define BF_IR_TCCTRL_INDX(v)        (((v) << 1) & 0x1e)
-#define BP_IR_TCCTRL_C              0
-#define BM_IR_TCCTRL_C              0x1
-#define BF_IR_TCCTRL_C(v)           (((v) << 0) & 0x1)
-
-/**
- * Register: HW_IR_SI_READ
- * Address: 0x80
- * SCT: no
-*/
-#define HW_IR_SI_READ           (*(volatile unsigned long *)(REGS_IR_BASE + 0x80))
-#define BP_IR_SI_READ_ABORT     8
-#define BM_IR_SI_READ_ABORT     0x100
-#define BF_IR_SI_READ_ABORT(v)  (((v) << 8) & 0x100)
-#define BP_IR_SI_READ_DATA      0
-#define BM_IR_SI_READ_DATA      0xff
-#define BF_IR_SI_READ_DATA(v)   (((v) << 0) & 0xff)
-
-/**
- * Register: HW_IR_DEBUG
- * Address: 0x90
- * SCT: no
-*/
-#define HW_IR_DEBUG                 (*(volatile unsigned long *)(REGS_IR_BASE + 0x90))
-#define BP_IR_DEBUG_TXDMAKICK       5
-#define BM_IR_DEBUG_TXDMAKICK       0x20
-#define BF_IR_DEBUG_TXDMAKICK(v)    (((v) << 5) & 0x20)
-#define BP_IR_DEBUG_RXDMAKICK       4
-#define BM_IR_DEBUG_RXDMAKICK       0x10
-#define BF_IR_DEBUG_RXDMAKICK(v)    (((v) << 4) & 0x10)
-#define BP_IR_DEBUG_TXDMAEND        3
-#define BM_IR_DEBUG_TXDMAEND        0x8
-#define BF_IR_DEBUG_TXDMAEND(v)     (((v) << 3) & 0x8)
-#define BP_IR_DEBUG_RXDMAEND        2
-#define BM_IR_DEBUG_RXDMAEND        0x4
-#define BF_IR_DEBUG_RXDMAEND(v)     (((v) << 2) & 0x4)
-#define BP_IR_DEBUG_TXDMAREQ        1
-#define BM_IR_DEBUG_TXDMAREQ        0x2
-#define BF_IR_DEBUG_TXDMAREQ(v)     (((v) << 1) & 0x2)
-#define BP_IR_DEBUG_RXDMAREQ        0
-#define BM_IR_DEBUG_RXDMAREQ        0x1
-#define BF_IR_DEBUG_RXDMAREQ(v)     (((v) << 0) & 0x1)
-
-/**
- * Register: HW_IR_VERSION
- * Address: 0xa0
- * SCT: no
-*/
-#define HW_IR_VERSION           (*(volatile unsigned long *)(REGS_IR_BASE + 0xa0))
-#define BP_IR_VERSION_MAJOR     24
-#define BM_IR_VERSION_MAJOR     0xff000000
-#define BF_IR_VERSION_MAJOR(v)  (((v) << 24) & 0xff000000)
-#define BP_IR_VERSION_MINOR     16
-#define BM_IR_VERSION_MINOR     0xff0000
-#define BF_IR_VERSION_MINOR(v)  (((v) << 16) & 0xff0000)
-#define BP_IR_VERSION_STEP      0
-#define BM_IR_VERSION_STEP      0xffff
-#define BF_IR_VERSION_STEP(v)   (((v) << 0) & 0xffff)
-
-#endif /* __HEADERGEN__STMP3700__IR__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-lcdif.h b/firmware/target/arm/imx233/regs/stmp3700/regs-lcdif.h
deleted file mode 100644
index 5069610799..0000000000
--- a/firmware/target/arm/imx233/regs/stmp3700/regs-lcdif.h
+++ /dev/null
@@ -1,451 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3700:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__STMP3700__LCDIF__H__
-#define __HEADERGEN__STMP3700__LCDIF__H__
-
-#define REGS_LCDIF_BASE (0x80030000)
-
-#define REGS_LCDIF_VERSION "3.2.0"
-
-/**
- * Register: HW_LCDIF_CTRL
- * Address: 0
- * SCT: yes
-*/
-#define HW_LCDIF_CTRL                                       (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x0 + 0x0))
-#define HW_LCDIF_CTRL_SET                                   (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x0 + 0x4))
-#define HW_LCDIF_CTRL_CLR                                   (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x0 + 0x8))
-#define HW_LCDIF_CTRL_TOG                                   (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x0 + 0xc))
-#define BP_LCDIF_CTRL_SFTRST                                31
-#define BM_LCDIF_CTRL_SFTRST                                0x80000000
-#define BF_LCDIF_CTRL_SFTRST(v)                             (((v) << 31) & 0x80000000)
-#define BP_LCDIF_CTRL_CLKGATE                               30
-#define BM_LCDIF_CTRL_CLKGATE                               0x40000000
-#define BF_LCDIF_CTRL_CLKGATE(v)                            (((v) << 30) & 0x40000000)
-#define BP_LCDIF_CTRL_READ_WRITEB                           29
-#define BM_LCDIF_CTRL_READ_WRITEB                           0x20000000
-#define BF_LCDIF_CTRL_READ_WRITEB(v)                        (((v) << 29) & 0x20000000)
-#define BP_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE                   28
-#define BM_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE                   0x10000000
-#define BF_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE(v)                (((v) << 28) & 0x10000000)
-#define BP_LCDIF_CTRL_DATA_SHIFT_DIR                        27
-#define BM_LCDIF_CTRL_DATA_SHIFT_DIR                        0x8000000
-#define BV_LCDIF_CTRL_DATA_SHIFT_DIR__TXDATA_SHIFT_LEFT     0x0
-#define BV_LCDIF_CTRL_DATA_SHIFT_DIR__TXDATA_SHIFT_RIGHT    0x1
-#define BF_LCDIF_CTRL_DATA_SHIFT_DIR(v)                     (((v) << 27) & 0x8000000)
-#define BF_LCDIF_CTRL_DATA_SHIFT_DIR_V(v)                   ((BV_LCDIF_CTRL_DATA_SHIFT_DIR__##v << 27) & 0x8000000)
-#define BP_LCDIF_CTRL_SHIFT_NUM_BITS                        25
-#define BM_LCDIF_CTRL_SHIFT_NUM_BITS                        0x6000000
-#define BF_LCDIF_CTRL_SHIFT_NUM_BITS(v)                     (((v) << 25) & 0x6000000)
-#define BP_LCDIF_CTRL_DVI_MODE                              24
-#define BM_LCDIF_CTRL_DVI_MODE                              0x1000000
-#define BF_LCDIF_CTRL_DVI_MODE(v)                           (((v) << 24) & 0x1000000)
-#define BP_LCDIF_CTRL_BYPASS_COUNT                          23
-#define BM_LCDIF_CTRL_BYPASS_COUNT                          0x800000
-#define BF_LCDIF_CTRL_BYPASS_COUNT(v)                       (((v) << 23) & 0x800000)
-#define BP_LCDIF_CTRL_DATA_SWIZZLE                          21
-#define BM_LCDIF_CTRL_DATA_SWIZZLE                          0x600000
-#define BV_LCDIF_CTRL_DATA_SWIZZLE__NO_SWAP                 0x0
-#define BV_LCDIF_CTRL_DATA_SWIZZLE__LITTLE_ENDIAN           0x0
-#define BV_LCDIF_CTRL_DATA_SWIZZLE__BIG_ENDIAN_SWAP         0x1
-#define BV_LCDIF_CTRL_DATA_SWIZZLE__SWAP_ALL_BYTES          0x1
-#define BV_LCDIF_CTRL_DATA_SWIZZLE__HWD_SWAP                0x2
-#define BV_LCDIF_CTRL_DATA_SWIZZLE__HWD_BYTE_SWAP           0x3
-#define BF_LCDIF_CTRL_DATA_SWIZZLE(v)                       (((v) << 21) & 0x600000)
-#define BF_LCDIF_CTRL_DATA_SWIZZLE_V(v)                     ((BV_LCDIF_CTRL_DATA_SWIZZLE__##v << 21) & 0x600000)
-#define BP_LCDIF_CTRL_VSYNC_MODE                            20
-#define BM_LCDIF_CTRL_VSYNC_MODE                            0x100000
-#define BF_LCDIF_CTRL_VSYNC_MODE(v)                         (((v) << 20) & 0x100000)
-#define BP_LCDIF_CTRL_DOTCLK_MODE                           19
-#define BM_LCDIF_CTRL_DOTCLK_MODE                           0x80000
-#define BF_LCDIF_CTRL_DOTCLK_MODE(v)                        (((v) << 19) & 0x80000)
-#define BP_LCDIF_CTRL_DATA_SELECT                           18
-#define BM_LCDIF_CTRL_DATA_SELECT                           0x40000
-#define BV_LCDIF_CTRL_DATA_SELECT__CMD_MODE                 0x0
-#define BV_LCDIF_CTRL_DATA_SELECT__DATA_MODE                0x1
-#define BF_LCDIF_CTRL_DATA_SELECT(v)                        (((v) << 18) & 0x40000)
-#define BF_LCDIF_CTRL_DATA_SELECT_V(v)                      ((BV_LCDIF_CTRL_DATA_SELECT__##v << 18) & 0x40000)
-#define BP_LCDIF_CTRL_WORD_LENGTH                           17
-#define BM_LCDIF_CTRL_WORD_LENGTH                           0x20000
-#define BV_LCDIF_CTRL_WORD_LENGTH__16_BIT                   0x0
-#define BV_LCDIF_CTRL_WORD_LENGTH__8_BIT                    0x1
-#define BF_LCDIF_CTRL_WORD_LENGTH(v)                        (((v) << 17) & 0x20000)
-#define BF_LCDIF_CTRL_WORD_LENGTH_V(v)                      ((BV_LCDIF_CTRL_WORD_LENGTH__##v << 17) & 0x20000)
-#define BP_LCDIF_CTRL_RUN                                   16
-#define BM_LCDIF_CTRL_RUN                                   0x10000
-#define BF_LCDIF_CTRL_RUN(v)                                (((v) << 16) & 0x10000)
-#define BP_LCDIF_CTRL_COUNT                                 0
-#define BM_LCDIF_CTRL_COUNT                                 0xffff
-#define BF_LCDIF_CTRL_COUNT(v)                              (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_LCDIF_CTRL1
- * Address: 0x10
- * SCT: yes
-*/
-#define HW_LCDIF_CTRL1                                  (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x10 + 0x0))
-#define HW_LCDIF_CTRL1_SET                              (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x10 + 0x4))
-#define HW_LCDIF_CTRL1_CLR                              (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x10 + 0x8))
-#define HW_LCDIF_CTRL1_TOG                              (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x10 + 0xc))
-#define BP_LCDIF_CTRL1_BYTE_PACKING_FORMAT              16
-#define BM_LCDIF_CTRL1_BYTE_PACKING_FORMAT              0xf0000
-#define BF_LCDIF_CTRL1_BYTE_PACKING_FORMAT(v)           (((v) << 16) & 0xf0000)
-#define BP_LCDIF_CTRL1_OVERFLOW_IRQ_EN                  15
-#define BM_LCDIF_CTRL1_OVERFLOW_IRQ_EN                  0x8000
-#define BF_LCDIF_CTRL1_OVERFLOW_IRQ_EN(v)               (((v) << 15) & 0x8000)
-#define BP_LCDIF_CTRL1_UNDERFLOW_IRQ_EN                 14
-#define BM_LCDIF_CTRL1_UNDERFLOW_IRQ_EN                 0x4000
-#define BF_LCDIF_CTRL1_UNDERFLOW_IRQ_EN(v)              (((v) << 14) & 0x4000)
-#define BP_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN            13
-#define BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN            0x2000
-#define BF_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN(v)         (((v) << 13) & 0x2000)
-#define BP_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN                12
-#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN                0x1000
-#define BF_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN(v)             (((v) << 12) & 0x1000)
-#define BP_LCDIF_CTRL1_OVERFLOW_IRQ                     11
-#define BM_LCDIF_CTRL1_OVERFLOW_IRQ                     0x800
-#define BV_LCDIF_CTRL1_OVERFLOW_IRQ__NO_REQUEST         0x0
-#define BV_LCDIF_CTRL1_OVERFLOW_IRQ__REQUEST            0x1
-#define BF_LCDIF_CTRL1_OVERFLOW_IRQ(v)                  (((v) << 11) & 0x800)
-#define BF_LCDIF_CTRL1_OVERFLOW_IRQ_V(v)                ((BV_LCDIF_CTRL1_OVERFLOW_IRQ__##v << 11) & 0x800)
-#define BP_LCDIF_CTRL1_UNDERFLOW_IRQ                    10
-#define BM_LCDIF_CTRL1_UNDERFLOW_IRQ                    0x400
-#define BV_LCDIF_CTRL1_UNDERFLOW_IRQ__NO_REQUEST        0x0
-#define BV_LCDIF_CTRL1_UNDERFLOW_IRQ__REQUEST           0x1
-#define BF_LCDIF_CTRL1_UNDERFLOW_IRQ(v)                 (((v) << 10) & 0x400)
-#define BF_LCDIF_CTRL1_UNDERFLOW_IRQ_V(v)               ((BV_LCDIF_CTRL1_UNDERFLOW_IRQ__##v << 10) & 0x400)
-#define BP_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ               9
-#define BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ               0x200
-#define BV_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ__NO_REQUEST   0x0
-#define BV_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ__REQUEST      0x1
-#define BF_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ(v)            (((v) << 9) & 0x200)
-#define BF_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_V(v)          ((BV_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ__##v << 9) & 0x200)
-#define BP_LCDIF_CTRL1_VSYNC_EDGE_IRQ                   8
-#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ                   0x100
-#define BV_LCDIF_CTRL1_VSYNC_EDGE_IRQ__NO_REQUEST       0x0
-#define BV_LCDIF_CTRL1_VSYNC_EDGE_IRQ__REQUEST          0x1
-#define BF_LCDIF_CTRL1_VSYNC_EDGE_IRQ(v)                (((v) << 8) & 0x100)
-#define BF_LCDIF_CTRL1_VSYNC_EDGE_IRQ_V(v)              ((BV_LCDIF_CTRL1_VSYNC_EDGE_IRQ__##v << 8) & 0x100)
-#define BP_LCDIF_CTRL1_READ_MODE_NUM_PACKED_SUBWORDS    5
-#define BM_LCDIF_CTRL1_READ_MODE_NUM_PACKED_SUBWORDS    0xe0
-#define BF_LCDIF_CTRL1_READ_MODE_NUM_PACKED_SUBWORDS(v) (((v) << 5) & 0xe0)
-#define BP_LCDIF_CTRL1_FIRST_READ_DUMMY                 4
-#define BM_LCDIF_CTRL1_FIRST_READ_DUMMY                 0x10
-#define BF_LCDIF_CTRL1_FIRST_READ_DUMMY(v)              (((v) << 4) & 0x10)
-#define BP_LCDIF_CTRL1_LCD_CS_CTRL                      3
-#define BM_LCDIF_CTRL1_LCD_CS_CTRL                      0x8
-#define BF_LCDIF_CTRL1_LCD_CS_CTRL(v)                   (((v) << 3) & 0x8)
-#define BP_LCDIF_CTRL1_BUSY_ENABLE                      2
-#define BM_LCDIF_CTRL1_BUSY_ENABLE                      0x4
-#define BV_LCDIF_CTRL1_BUSY_ENABLE__BUSY_DISABLED       0x0
-#define BV_LCDIF_CTRL1_BUSY_ENABLE__BUSY_ENABLED        0x1
-#define BF_LCDIF_CTRL1_BUSY_ENABLE(v)                   (((v) << 2) & 0x4)
-#define BF_LCDIF_CTRL1_BUSY_ENABLE_V(v)                 ((BV_LCDIF_CTRL1_BUSY_ENABLE__##v << 2) & 0x4)
-#define BP_LCDIF_CTRL1_MODE86                           1
-#define BM_LCDIF_CTRL1_MODE86                           0x2
-#define BV_LCDIF_CTRL1_MODE86__8080_MODE                0x0
-#define BV_LCDIF_CTRL1_MODE86__6800_MODE                0x1
-#define BF_LCDIF_CTRL1_MODE86(v)                        (((v) << 1) & 0x2)
-#define BF_LCDIF_CTRL1_MODE86_V(v)                      ((BV_LCDIF_CTRL1_MODE86__##v << 1) & 0x2)
-#define BP_LCDIF_CTRL1_RESET                            0
-#define BM_LCDIF_CTRL1_RESET                            0x1
-#define BV_LCDIF_CTRL1_RESET__LCDRESET_LOW              0x0
-#define BV_LCDIF_CTRL1_RESET__LCDRESET_HIGH             0x1
-#define BF_LCDIF_CTRL1_RESET(v)                         (((v) << 0) & 0x1)
-#define BF_LCDIF_CTRL1_RESET_V(v)                       ((BV_LCDIF_CTRL1_RESET__##v << 0) & 0x1)
-
-/**
- * Register: HW_LCDIF_TIMING
- * Address: 0x20
- * SCT: no
-*/
-#define HW_LCDIF_TIMING                 (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x20))
-#define BP_LCDIF_TIMING_CMD_HOLD        24
-#define BM_LCDIF_TIMING_CMD_HOLD        0xff000000
-#define BF_LCDIF_TIMING_CMD_HOLD(v)     (((v) << 24) & 0xff000000)
-#define BP_LCDIF_TIMING_CMD_SETUP       16
-#define BM_LCDIF_TIMING_CMD_SETUP       0xff0000
-#define BF_LCDIF_TIMING_CMD_SETUP(v)    (((v) << 16) & 0xff0000)
-#define BP_LCDIF_TIMING_DATA_HOLD       8
-#define BM_LCDIF_TIMING_DATA_HOLD       0xff00
-#define BF_LCDIF_TIMING_DATA_HOLD(v)    (((v) << 8) & 0xff00)
-#define BP_LCDIF_TIMING_DATA_SETUP      0
-#define BM_LCDIF_TIMING_DATA_SETUP      0xff
-#define BF_LCDIF_TIMING_DATA_SETUP(v)   (((v) << 0) & 0xff)
-
-/**
- * Register: HW_LCDIF_VDCTRL0
- * Address: 0x30
- * SCT: yes
-*/
-#define HW_LCDIF_VDCTRL0                            (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x30 + 0x0))
-#define HW_LCDIF_VDCTRL0_SET                        (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x30 + 0x4))
-#define HW_LCDIF_VDCTRL0_CLR                        (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x30 + 0x8))
-#define HW_LCDIF_VDCTRL0_TOG                        (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x30 + 0xc))
-#define BP_LCDIF_VDCTRL0_VSYNC_OEB                  29
-#define BM_LCDIF_VDCTRL0_VSYNC_OEB                  0x20000000
-#define BV_LCDIF_VDCTRL0_VSYNC_OEB__VSYNC_OUTPUT    0x0
-#define BV_LCDIF_VDCTRL0_VSYNC_OEB__VSYNC_INPUT     0x1
-#define BF_LCDIF_VDCTRL0_VSYNC_OEB(v)               (((v) << 29) & 0x20000000)
-#define BF_LCDIF_VDCTRL0_VSYNC_OEB_V(v)             ((BV_LCDIF_VDCTRL0_VSYNC_OEB__##v << 29) & 0x20000000)
-#define BP_LCDIF_VDCTRL0_ENABLE_PRESENT             28
-#define BM_LCDIF_VDCTRL0_ENABLE_PRESENT             0x10000000
-#define BF_LCDIF_VDCTRL0_ENABLE_PRESENT(v)          (((v) << 28) & 0x10000000)
-#define BP_LCDIF_VDCTRL0_VSYNC_POL                  27
-#define BM_LCDIF_VDCTRL0_VSYNC_POL                  0x8000000
-#define BF_LCDIF_VDCTRL0_VSYNC_POL(v)               (((v) << 27) & 0x8000000)
-#define BP_LCDIF_VDCTRL0_HSYNC_POL                  26
-#define BM_LCDIF_VDCTRL0_HSYNC_POL                  0x4000000
-#define BF_LCDIF_VDCTRL0_HSYNC_POL(v)               (((v) << 26) & 0x4000000)
-#define BP_LCDIF_VDCTRL0_DOTCLK_POL                 25
-#define BM_LCDIF_VDCTRL0_DOTCLK_POL                 0x2000000
-#define BF_LCDIF_VDCTRL0_DOTCLK_POL(v)              (((v) << 25) & 0x2000000)
-#define BP_LCDIF_VDCTRL0_ENABLE_POL                 24
-#define BM_LCDIF_VDCTRL0_ENABLE_POL                 0x1000000
-#define BF_LCDIF_VDCTRL0_ENABLE_POL(v)              (((v) << 24) & 0x1000000)
-#define BP_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT          21
-#define BM_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT          0x200000
-#define BF_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT(v)       (((v) << 21) & 0x200000)
-#define BP_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT     20
-#define BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT     0x100000
-#define BF_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT(v)  (((v) << 20) & 0x100000)
-#define BP_LCDIF_VDCTRL0_INTERLACE                  19
-#define BM_LCDIF_VDCTRL0_INTERLACE                  0x80000
-#define BF_LCDIF_VDCTRL0_INTERLACE(v)               (((v) << 19) & 0x80000)
-#define BP_LCDIF_VDCTRL0_DOTCLK_V_VALID_DATA_CNT    0
-#define BM_LCDIF_VDCTRL0_DOTCLK_V_VALID_DATA_CNT    0x3ff
-#define BF_LCDIF_VDCTRL0_DOTCLK_V_VALID_DATA_CNT(v) (((v) << 0) & 0x3ff)
-
-/**
- * Register: HW_LCDIF_VDCTRL1
- * Address: 0x40
- * SCT: no
-*/
-#define HW_LCDIF_VDCTRL1                        (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x40))
-#define BP_LCDIF_VDCTRL1_VSYNC_PULSE_WIDTH      20
-#define BM_LCDIF_VDCTRL1_VSYNC_PULSE_WIDTH      0xfff00000
-#define BF_LCDIF_VDCTRL1_VSYNC_PULSE_WIDTH(v)   (((v) << 20) & 0xfff00000)
-#define BP_LCDIF_VDCTRL1_VSYNC_PERIOD           0
-#define BM_LCDIF_VDCTRL1_VSYNC_PERIOD           0xfffff
-#define BF_LCDIF_VDCTRL1_VSYNC_PERIOD(v)        (((v) << 0) & 0xfffff)
-
-/**
- * Register: HW_LCDIF_VDCTRL2
- * Address: 0x50
- * SCT: no
-*/
-#define HW_LCDIF_VDCTRL2                            (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x50))
-#define BP_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH          23
-#define BM_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH          0xff800000
-#define BF_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(v)       (((v) << 23) & 0xff800000)
-#define BP_LCDIF_VDCTRL2_HSYNC_PERIOD               11
-#define BM_LCDIF_VDCTRL2_HSYNC_PERIOD               0x7ff800
-#define BF_LCDIF_VDCTRL2_HSYNC_PERIOD(v)            (((v) << 11) & 0x7ff800)
-#define BP_LCDIF_VDCTRL2_DOTCLK_H_VALID_DATA_CNT    0
-#define BM_LCDIF_VDCTRL2_DOTCLK_H_VALID_DATA_CNT    0x7ff
-#define BF_LCDIF_VDCTRL2_DOTCLK_H_VALID_DATA_CNT(v) (((v) << 0) & 0x7ff)
-
-/**
- * Register: HW_LCDIF_VDCTRL3
- * Address: 0x60
- * SCT: no
-*/
-#define HW_LCDIF_VDCTRL3                        (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x60))
-#define BP_LCDIF_VDCTRL3_SYNC_SIGNALS_ON        24
-#define BM_LCDIF_VDCTRL3_SYNC_SIGNALS_ON        0x1000000
-#define BF_LCDIF_VDCTRL3_SYNC_SIGNALS_ON(v)     (((v) << 24) & 0x1000000)
-#define BP_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT    12
-#define BM_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT    0xfff000
-#define BF_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(v) (((v) << 12) & 0xfff000)
-#define BP_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT      0
-#define BM_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT      0x1ff
-#define BF_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT(v)   (((v) << 0) & 0x1ff)
-
-/**
- * Register: HW_LCDIF_DVICTRL0
- * Address: 0x70
- * SCT: no
-*/
-#define HW_LCDIF_DVICTRL0                   (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x70))
-#define BP_LCDIF_DVICTRL0_H_ACTIVE_CNT      20
-#define BM_LCDIF_DVICTRL0_H_ACTIVE_CNT      0x7ff00000
-#define BF_LCDIF_DVICTRL0_H_ACTIVE_CNT(v)   (((v) << 20) & 0x7ff00000)
-#define BP_LCDIF_DVICTRL0_H_BLANKING_CNT    10
-#define BM_LCDIF_DVICTRL0_H_BLANKING_CNT    0xffc00
-#define BF_LCDIF_DVICTRL0_H_BLANKING_CNT(v) (((v) << 10) & 0xffc00)
-#define BP_LCDIF_DVICTRL0_V_LINES_CNT       0
-#define BM_LCDIF_DVICTRL0_V_LINES_CNT       0x3ff
-#define BF_LCDIF_DVICTRL0_V_LINES_CNT(v)    (((v) << 0) & 0x3ff)
-
-/**
- * Register: HW_LCDIF_DVICTRL1
- * Address: 0x80
- * SCT: no
-*/
-#define HW_LCDIF_DVICTRL1                   (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x80))
-#define BP_LCDIF_DVICTRL1_F1_START_LINE     20
-#define BM_LCDIF_DVICTRL1_F1_START_LINE     0x3ff00000
-#define BF_LCDIF_DVICTRL1_F1_START_LINE(v)  (((v) << 20) & 0x3ff00000)
-#define BP_LCDIF_DVICTRL1_F1_END_LINE       10
-#define BM_LCDIF_DVICTRL1_F1_END_LINE       0xffc00
-#define BF_LCDIF_DVICTRL1_F1_END_LINE(v)    (((v) << 10) & 0xffc00)
-#define BP_LCDIF_DVICTRL1_F2_START_LINE     0
-#define BM_LCDIF_DVICTRL1_F2_START_LINE     0x3ff
-#define BF_LCDIF_DVICTRL1_F2_START_LINE(v)  (((v) << 0) & 0x3ff)
-
-/**
- * Register: HW_LCDIF_DVICTRL2
- * Address: 0x90
- * SCT: no
-*/
-#define HW_LCDIF_DVICTRL2                           (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x90))
-#define BP_LCDIF_DVICTRL2_F2_END_LINE               20
-#define BM_LCDIF_DVICTRL2_F2_END_LINE               0x3ff00000
-#define BF_LCDIF_DVICTRL2_F2_END_LINE(v)            (((v) << 20) & 0x3ff00000)
-#define BP_LCDIF_DVICTRL2_V1_BLANK_START_LINE       10
-#define BM_LCDIF_DVICTRL2_V1_BLANK_START_LINE       0xffc00
-#define BF_LCDIF_DVICTRL2_V1_BLANK_START_LINE(v)    (((v) << 10) & 0xffc00)
-#define BP_LCDIF_DVICTRL2_V1_BLANK_END_LINE         0
-#define BM_LCDIF_DVICTRL2_V1_BLANK_END_LINE         0x3ff
-#define BF_LCDIF_DVICTRL2_V1_BLANK_END_LINE(v)      (((v) << 0) & 0x3ff)
-
-/**
- * Register: HW_LCDIF_DVICTRL3
- * Address: 0xa0
- * SCT: no
-*/
-#define HW_LCDIF_DVICTRL3                           (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0xa0))
-#define BP_LCDIF_DVICTRL3_V2_BLANK_START_LINE       16
-#define BM_LCDIF_DVICTRL3_V2_BLANK_START_LINE       0x3ff0000
-#define BF_LCDIF_DVICTRL3_V2_BLANK_START_LINE(v)    (((v) << 16) & 0x3ff0000)
-#define BP_LCDIF_DVICTRL3_V2_BLANK_END_LINE         0
-#define BM_LCDIF_DVICTRL3_V2_BLANK_END_LINE         0x3ff
-#define BF_LCDIF_DVICTRL3_V2_BLANK_END_LINE(v)      (((v) << 0) & 0x3ff)
-
-/**
- * Register: HW_LCDIF_DATA
- * Address: 0xb0
- * SCT: no
-*/
-#define HW_LCDIF_DATA               (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0xb0))
-#define BP_LCDIF_DATA_DATA_THREE    24
-#define BM_LCDIF_DATA_DATA_THREE    0xff000000
-#define BF_LCDIF_DATA_DATA_THREE(v) (((v) << 24) & 0xff000000)
-#define BP_LCDIF_DATA_DATA_TWO      16
-#define BM_LCDIF_DATA_DATA_TWO      0xff0000
-#define BF_LCDIF_DATA_DATA_TWO(v)   (((v) << 16) & 0xff0000)
-#define BP_LCDIF_DATA_DATA_ONE      8
-#define BM_LCDIF_DATA_DATA_ONE      0xff00
-#define BF_LCDIF_DATA_DATA_ONE(v)   (((v) << 8) & 0xff00)
-#define BP_LCDIF_DATA_DATA_ZERO     0
-#define BM_LCDIF_DATA_DATA_ZERO     0xff
-#define BF_LCDIF_DATA_DATA_ZERO(v)  (((v) << 0) & 0xff)
-
-/**
- * Register: HW_LCDIF_STAT
- * Address: 0xc0
- * SCT: no
-*/
-#define HW_LCDIF_STAT                       (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0xc0))
-#define BP_LCDIF_STAT_PRESENT               31
-#define BM_LCDIF_STAT_PRESENT               0x80000000
-#define BF_LCDIF_STAT_PRESENT(v)            (((v) << 31) & 0x80000000)
-#define BP_LCDIF_STAT_DMA_REQ               30
-#define BM_LCDIF_STAT_DMA_REQ               0x40000000
-#define BF_LCDIF_STAT_DMA_REQ(v)            (((v) << 30) & 0x40000000)
-#define BP_LCDIF_STAT_RXFIFO_FULL           29
-#define BM_LCDIF_STAT_RXFIFO_FULL           0x20000000
-#define BF_LCDIF_STAT_RXFIFO_FULL(v)        (((v) << 29) & 0x20000000)
-#define BP_LCDIF_STAT_RXFIFO_EMPTY          28
-#define BM_LCDIF_STAT_RXFIFO_EMPTY          0x10000000
-#define BF_LCDIF_STAT_RXFIFO_EMPTY(v)       (((v) << 28) & 0x10000000)
-#define BP_LCDIF_STAT_TXFIFO_FULL           27
-#define BM_LCDIF_STAT_TXFIFO_FULL           0x8000000
-#define BF_LCDIF_STAT_TXFIFO_FULL(v)        (((v) << 27) & 0x8000000)
-#define BP_LCDIF_STAT_TXFIFO_EMPTY          26
-#define BM_LCDIF_STAT_TXFIFO_EMPTY          0x4000000
-#define BF_LCDIF_STAT_TXFIFO_EMPTY(v)       (((v) << 26) & 0x4000000)
-#define BP_LCDIF_STAT_BUSY                  25
-#define BM_LCDIF_STAT_BUSY                  0x2000000
-#define BF_LCDIF_STAT_BUSY(v)               (((v) << 25) & 0x2000000)
-#define BP_LCDIF_STAT_DVI_CURRENT_FIELD     24
-#define BM_LCDIF_STAT_DVI_CURRENT_FIELD     0x1000000
-#define BF_LCDIF_STAT_DVI_CURRENT_FIELD(v)  (((v) << 24) & 0x1000000)
-
-/**
- * Register: HW_LCDIF_VERSION
- * Address: 0xd0
- * SCT: no
-*/
-#define HW_LCDIF_VERSION            (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0xd0))
-#define BP_LCDIF_VERSION_MAJOR      24
-#define BM_LCDIF_VERSION_MAJOR      0xff000000
-#define BF_LCDIF_VERSION_MAJOR(v)   (((v) << 24) & 0xff000000)
-#define BP_LCDIF_VERSION_MINOR      16
-#define BM_LCDIF_VERSION_MINOR      0xff0000
-#define BF_LCDIF_VERSION_MINOR(v)   (((v) << 16) & 0xff0000)
-#define BP_LCDIF_VERSION_STEP       0
-#define BM_LCDIF_VERSION_STEP       0xffff
-#define BF_LCDIF_VERSION_STEP(v)    (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_LCDIF_DEBUG0
- * Address: 0xe0
- * SCT: no
-*/
-#define HW_LCDIF_DEBUG0                             (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0xe0))
-#define BP_LCDIF_DEBUG0_STREAMING_END_DETECTED      31
-#define BM_LCDIF_DEBUG0_STREAMING_END_DETECTED      0x80000000
-#define BF_LCDIF_DEBUG0_STREAMING_END_DETECTED(v)   (((v) << 31) & 0x80000000)
-#define BP_LCDIF_DEBUG0_WAIT_FOR_VSYNC_EDGE_OUT     30
-#define BM_LCDIF_DEBUG0_WAIT_FOR_VSYNC_EDGE_OUT     0x40000000
-#define BF_LCDIF_DEBUG0_WAIT_FOR_VSYNC_EDGE_OUT(v)  (((v) << 30) & 0x40000000)
-#define BP_LCDIF_DEBUG0_SYNC_SIGNALS_ON_REG         29
-#define BM_LCDIF_DEBUG0_SYNC_SIGNALS_ON_REG         0x20000000
-#define BF_LCDIF_DEBUG0_SYNC_SIGNALS_ON_REG(v)      (((v) << 29) & 0x20000000)
-#define BP_LCDIF_DEBUG0_DMACMDKICK                  28
-#define BM_LCDIF_DEBUG0_DMACMDKICK                  0x10000000
-#define BF_LCDIF_DEBUG0_DMACMDKICK(v)               (((v) << 28) & 0x10000000)
-#define BP_LCDIF_DEBUG0_ENABLE                      27
-#define BM_LCDIF_DEBUG0_ENABLE                      0x8000000
-#define BF_LCDIF_DEBUG0_ENABLE(v)                   (((v) << 27) & 0x8000000)
-#define BP_LCDIF_DEBUG0_HSYNC                       26
-#define BM_LCDIF_DEBUG0_HSYNC                       0x4000000
-#define BF_LCDIF_DEBUG0_HSYNC(v)                    (((v) << 26) & 0x4000000)
-#define BP_LCDIF_DEBUG0_VSYNC                       25
-#define BM_LCDIF_DEBUG0_VSYNC                       0x2000000
-#define BF_LCDIF_DEBUG0_VSYNC(v)                    (((v) << 25) & 0x2000000)
-#define BP_LCDIF_DEBUG0_CUR_FRAME_TX                24
-#define BM_LCDIF_DEBUG0_CUR_FRAME_TX                0x1000000
-#define BF_LCDIF_DEBUG0_CUR_FRAME_TX(v)             (((v) << 24) & 0x1000000)
-#define BP_LCDIF_DEBUG0_EMPTY_WORD                  23
-#define BM_LCDIF_DEBUG0_EMPTY_WORD                  0x800000
-#define BF_LCDIF_DEBUG0_EMPTY_WORD(v)               (((v) << 23) & 0x800000)
-#define BP_LCDIF_DEBUG0_CUR_STATE                   16
-#define BM_LCDIF_DEBUG0_CUR_STATE                   0x7f0000
-#define BF_LCDIF_DEBUG0_CUR_STATE(v)                (((v) << 16) & 0x7f0000)
-#define BP_LCDIF_DEBUG0_DATA_COUNT                  0
-#define BM_LCDIF_DEBUG0_DATA_COUNT                  0xffff
-#define BF_LCDIF_DEBUG0_DATA_COUNT(v)               (((v) << 0) & 0xffff)
-
-#endif /* __HEADERGEN__STMP3700__LCDIF__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-lradc.h b/firmware/target/arm/imx233/regs/stmp3700/regs-lradc.h
deleted file mode 100644
index 97132527a8..0000000000
--- a/firmware/target/arm/imx233/regs/stmp3700/regs-lradc.h
+++ /dev/null
@@ -1,708 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3700:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__STMP3700__LRADC__H__
-#define __HEADERGEN__STMP3700__LRADC__H__
-
-#define REGS_LRADC_BASE (0x80050000)
-
-#define REGS_LRADC_VERSION "3.2.0"
-
-/**
- * Register: HW_LRADC_CTRL0
- * Address: 0
- * SCT: yes
-*/
-#define HW_LRADC_CTRL0                          (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x0 + 0x0))
-#define HW_LRADC_CTRL0_SET                      (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x0 + 0x4))
-#define HW_LRADC_CTRL0_CLR                      (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x0 + 0x8))
-#define HW_LRADC_CTRL0_TOG                      (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x0 + 0xc))
-#define BP_LRADC_CTRL0_SFTRST                   31
-#define BM_LRADC_CTRL0_SFTRST                   0x80000000
-#define BF_LRADC_CTRL0_SFTRST(v)                (((v) << 31) & 0x80000000)
-#define BP_LRADC_CTRL0_CLKGATE                  30
-#define BM_LRADC_CTRL0_CLKGATE                  0x40000000
-#define BF_LRADC_CTRL0_CLKGATE(v)               (((v) << 30) & 0x40000000)
-#define BP_LRADC_CTRL0_ONCHIP_GROUNDREF         21
-#define BM_LRADC_CTRL0_ONCHIP_GROUNDREF         0x200000
-#define BV_LRADC_CTRL0_ONCHIP_GROUNDREF__OFF    0x0
-#define BV_LRADC_CTRL0_ONCHIP_GROUNDREF__ON     0x1
-#define BF_LRADC_CTRL0_ONCHIP_GROUNDREF(v)      (((v) << 21) & 0x200000)
-#define BF_LRADC_CTRL0_ONCHIP_GROUNDREF_V(v)    ((BV_LRADC_CTRL0_ONCHIP_GROUNDREF__##v << 21) & 0x200000)
-#define BP_LRADC_CTRL0_TOUCH_DETECT_ENABLE      20
-#define BM_LRADC_CTRL0_TOUCH_DETECT_ENABLE      0x100000
-#define BV_LRADC_CTRL0_TOUCH_DETECT_ENABLE__OFF 0x0
-#define BV_LRADC_CTRL0_TOUCH_DETECT_ENABLE__ON  0x1
-#define BF_LRADC_CTRL0_TOUCH_DETECT_ENABLE(v)   (((v) << 20) & 0x100000)
-#define BF_LRADC_CTRL0_TOUCH_DETECT_ENABLE_V(v) ((BV_LRADC_CTRL0_TOUCH_DETECT_ENABLE__##v << 20) & 0x100000)
-#define BP_LRADC_CTRL0_YMINUS_ENABLE            19
-#define BM_LRADC_CTRL0_YMINUS_ENABLE            0x80000
-#define BV_LRADC_CTRL0_YMINUS_ENABLE__OFF       0x0
-#define BV_LRADC_CTRL0_YMINUS_ENABLE__ON        0x1
-#define BF_LRADC_CTRL0_YMINUS_ENABLE(v)         (((v) << 19) & 0x80000)
-#define BF_LRADC_CTRL0_YMINUS_ENABLE_V(v)       ((BV_LRADC_CTRL0_YMINUS_ENABLE__##v << 19) & 0x80000)
-#define BP_LRADC_CTRL0_XMINUS_ENABLE            18
-#define BM_LRADC_CTRL0_XMINUS_ENABLE            0x40000
-#define BV_LRADC_CTRL0_XMINUS_ENABLE__OFF       0x0
-#define BV_LRADC_CTRL0_XMINUS_ENABLE__ON        0x1
-#define BF_LRADC_CTRL0_XMINUS_ENABLE(v)         (((v) << 18) & 0x40000)
-#define BF_LRADC_CTRL0_XMINUS_ENABLE_V(v)       ((BV_LRADC_CTRL0_XMINUS_ENABLE__##v << 18) & 0x40000)
-#define BP_LRADC_CTRL0_YPLUS_ENABLE             17
-#define BM_LRADC_CTRL0_YPLUS_ENABLE             0x20000
-#define BV_LRADC_CTRL0_YPLUS_ENABLE__OFF        0x0
-#define BV_LRADC_CTRL0_YPLUS_ENABLE__ON         0x1
-#define BF_LRADC_CTRL0_YPLUS_ENABLE(v)          (((v) << 17) & 0x20000)
-#define BF_LRADC_CTRL0_YPLUS_ENABLE_V(v)        ((BV_LRADC_CTRL0_YPLUS_ENABLE__##v << 17) & 0x20000)
-#define BP_LRADC_CTRL0_XPLUS_ENABLE             16
-#define BM_LRADC_CTRL0_XPLUS_ENABLE             0x10000
-#define BV_LRADC_CTRL0_XPLUS_ENABLE__OFF        0x0
-#define BV_LRADC_CTRL0_XPLUS_ENABLE__ON         0x1
-#define BF_LRADC_CTRL0_XPLUS_ENABLE(v)          (((v) << 16) & 0x10000)
-#define BF_LRADC_CTRL0_XPLUS_ENABLE_V(v)        ((BV_LRADC_CTRL0_XPLUS_ENABLE__##v << 16) & 0x10000)
-#define BP_LRADC_CTRL0_SCHEDULE                 0
-#define BM_LRADC_CTRL0_SCHEDULE                 0xff
-#define BF_LRADC_CTRL0_SCHEDULE(v)              (((v) << 0) & 0xff)
-
-/**
- * Register: HW_LRADC_CTRL1
- * Address: 0x10
- * SCT: yes
-*/
-#define HW_LRADC_CTRL1                              (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x10 + 0x0))
-#define HW_LRADC_CTRL1_SET                          (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x10 + 0x4))
-#define HW_LRADC_CTRL1_CLR                          (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x10 + 0x8))
-#define HW_LRADC_CTRL1_TOG                          (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x10 + 0xc))
-#define BP_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN          24
-#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN          0x1000000
-#define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN__DISABLE 0x0
-#define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN__ENABLE  0x1
-#define BF_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN(v)       (((v) << 24) & 0x1000000)
-#define BF_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN_V(v)     ((BV_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN__##v << 24) & 0x1000000)
-#define BP_LRADC_CTRL1_LRADC7_IRQ_EN                23
-#define BM_LRADC_CTRL1_LRADC7_IRQ_EN                0x800000
-#define BV_LRADC_CTRL1_LRADC7_IRQ_EN__DISABLE       0x0
-#define BV_LRADC_CTRL1_LRADC7_IRQ_EN__ENABLE        0x1
-#define BF_LRADC_CTRL1_LRADC7_IRQ_EN(v)             (((v) << 23) & 0x800000)
-#define BF_LRADC_CTRL1_LRADC7_IRQ_EN_V(v)           ((BV_LRADC_CTRL1_LRADC7_IRQ_EN__##v << 23) & 0x800000)
-#define BP_LRADC_CTRL1_LRADC6_IRQ_EN                22
-#define BM_LRADC_CTRL1_LRADC6_IRQ_EN                0x400000
-#define BV_LRADC_CTRL1_LRADC6_IRQ_EN__DISABLE       0x0
-#define BV_LRADC_CTRL1_LRADC6_IRQ_EN__ENABLE        0x1
-#define BF_LRADC_CTRL1_LRADC6_IRQ_EN(v)             (((v) << 22) & 0x400000)
-#define BF_LRADC_CTRL1_LRADC6_IRQ_EN_V(v)           ((BV_LRADC_CTRL1_LRADC6_IRQ_EN__##v << 22) & 0x400000)
-#define BP_LRADC_CTRL1_LRADC5_IRQ_EN                21
-#define BM_LRADC_CTRL1_LRADC5_IRQ_EN                0x200000
-#define BV_LRADC_CTRL1_LRADC5_IRQ_EN__DISABLE       0x0
-#define BV_LRADC_CTRL1_LRADC5_IRQ_EN__ENABLE        0x1
-#define BF_LRADC_CTRL1_LRADC5_IRQ_EN(v)             (((v) << 21) & 0x200000)
-#define BF_LRADC_CTRL1_LRADC5_IRQ_EN_V(v)           ((BV_LRADC_CTRL1_LRADC5_IRQ_EN__##v << 21) & 0x200000)
-#define BP_LRADC_CTRL1_LRADC4_IRQ_EN                20
-#define BM_LRADC_CTRL1_LRADC4_IRQ_EN                0x100000
-#define BV_LRADC_CTRL1_LRADC4_IRQ_EN__DISABLE       0x0
-#define BV_LRADC_CTRL1_LRADC4_IRQ_EN__ENABLE        0x1
-#define BF_LRADC_CTRL1_LRADC4_IRQ_EN(v)             (((v) << 20) & 0x100000)
-#define BF_LRADC_CTRL1_LRADC4_IRQ_EN_V(v)           ((BV_LRADC_CTRL1_LRADC4_IRQ_EN__##v << 20) & 0x100000)
-#define BP_LRADC_CTRL1_LRADC3_IRQ_EN                19
-#define BM_LRADC_CTRL1_LRADC3_IRQ_EN                0x80000
-#define BV_LRADC_CTRL1_LRADC3_IRQ_EN__DISABLE       0x0
-#define BV_LRADC_CTRL1_LRADC3_IRQ_EN__ENABLE        0x1
-#define BF_LRADC_CTRL1_LRADC3_IRQ_EN(v)             (((v) << 19) & 0x80000)
-#define BF_LRADC_CTRL1_LRADC3_IRQ_EN_V(v)           ((BV_LRADC_CTRL1_LRADC3_IRQ_EN__##v << 19) & 0x80000)
-#define BP_LRADC_CTRL1_LRADC2_IRQ_EN                18
-#define BM_LRADC_CTRL1_LRADC2_IRQ_EN                0x40000
-#define BV_LRADC_CTRL1_LRADC2_IRQ_EN__DISABLE       0x0
-#define BV_LRADC_CTRL1_LRADC2_IRQ_EN__ENABLE        0x1
-#define BF_LRADC_CTRL1_LRADC2_IRQ_EN(v)             (((v) << 18) & 0x40000)
-#define BF_LRADC_CTRL1_LRADC2_IRQ_EN_V(v)           ((BV_LRADC_CTRL1_LRADC2_IRQ_EN__##v << 18) & 0x40000)
-#define BP_LRADC_CTRL1_LRADC1_IRQ_EN                17
-#define BM_LRADC_CTRL1_LRADC1_IRQ_EN                0x20000
-#define BV_LRADC_CTRL1_LRADC1_IRQ_EN__DISABLE       0x0
-#define BV_LRADC_CTRL1_LRADC1_IRQ_EN__ENABLE        0x1
-#define BF_LRADC_CTRL1_LRADC1_IRQ_EN(v)             (((v) << 17) & 0x20000)
-#define BF_LRADC_CTRL1_LRADC1_IRQ_EN_V(v)           ((BV_LRADC_CTRL1_LRADC1_IRQ_EN__##v << 17) & 0x20000)
-#define BP_LRADC_CTRL1_LRADC0_IRQ_EN                16
-#define BM_LRADC_CTRL1_LRADC0_IRQ_EN                0x10000
-#define BV_LRADC_CTRL1_LRADC0_IRQ_EN__DISABLE       0x0
-#define BV_LRADC_CTRL1_LRADC0_IRQ_EN__ENABLE        0x1
-#define BF_LRADC_CTRL1_LRADC0_IRQ_EN(v)             (((v) << 16) & 0x10000)
-#define BF_LRADC_CTRL1_LRADC0_IRQ_EN_V(v)           ((BV_LRADC_CTRL1_LRADC0_IRQ_EN__##v << 16) & 0x10000)
-#define BP_LRADC_CTRL1_TOUCH_DETECT_IRQ             8
-#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ             0x100
-#define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ__CLEAR      0x0
-#define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ__PENDING    0x1
-#define BF_LRADC_CTRL1_TOUCH_DETECT_IRQ(v)          (((v) << 8) & 0x100)
-#define BF_LRADC_CTRL1_TOUCH_DETECT_IRQ_V(v)        ((BV_LRADC_CTRL1_TOUCH_DETECT_IRQ__##v << 8) & 0x100)
-#define BP_LRADC_CTRL1_LRADC7_IRQ                   7
-#define BM_LRADC_CTRL1_LRADC7_IRQ                   0x80
-#define BV_LRADC_CTRL1_LRADC7_IRQ__CLEAR            0x0
-#define BV_LRADC_CTRL1_LRADC7_IRQ__PENDING          0x1
-#define BF_LRADC_CTRL1_LRADC7_IRQ(v)                (((v) << 7) & 0x80)
-#define BF_LRADC_CTRL1_LRADC7_IRQ_V(v)              ((BV_LRADC_CTRL1_LRADC7_IRQ__##v << 7) & 0x80)
-#define BP_LRADC_CTRL1_LRADC6_IRQ                   6
-#define BM_LRADC_CTRL1_LRADC6_IRQ                   0x40
-#define BV_LRADC_CTRL1_LRADC6_IRQ__CLEAR            0x0
-#define BV_LRADC_CTRL1_LRADC6_IRQ__PENDING          0x1
-#define BF_LRADC_CTRL1_LRADC6_IRQ(v)                (((v) << 6) & 0x40)
-#define BF_LRADC_CTRL1_LRADC6_IRQ_V(v)              ((BV_LRADC_CTRL1_LRADC6_IRQ__##v << 6) & 0x40)
-#define BP_LRADC_CTRL1_LRADC5_IRQ                   5
-#define BM_LRADC_CTRL1_LRADC5_IRQ                   0x20
-#define BV_LRADC_CTRL1_LRADC5_IRQ__CLEAR            0x0
-#define BV_LRADC_CTRL1_LRADC5_IRQ__PENDING          0x1
-#define BF_LRADC_CTRL1_LRADC5_IRQ(v)                (((v) << 5) & 0x20)
-#define BF_LRADC_CTRL1_LRADC5_IRQ_V(v)              ((BV_LRADC_CTRL1_LRADC5_IRQ__##v << 5) & 0x20)
-#define BP_LRADC_CTRL1_LRADC4_IRQ                   4
-#define BM_LRADC_CTRL1_LRADC4_IRQ                   0x10
-#define BV_LRADC_CTRL1_LRADC4_IRQ__CLEAR            0x0
-#define BV_LRADC_CTRL1_LRADC4_IRQ__PENDING          0x1
-#define BF_LRADC_CTRL1_LRADC4_IRQ(v)                (((v) << 4) & 0x10)
-#define BF_LRADC_CTRL1_LRADC4_IRQ_V(v)              ((BV_LRADC_CTRL1_LRADC4_IRQ__##v << 4) & 0x10)
-#define BP_LRADC_CTRL1_LRADC3_IRQ                   3
-#define BM_LRADC_CTRL1_LRADC3_IRQ                   0x8
-#define BV_LRADC_CTRL1_LRADC3_IRQ__CLEAR            0x0
-#define BV_LRADC_CTRL1_LRADC3_IRQ__PENDING          0x1
-#define BF_LRADC_CTRL1_LRADC3_IRQ(v)                (((v) << 3) & 0x8)
-#define BF_LRADC_CTRL1_LRADC3_IRQ_V(v)              ((BV_LRADC_CTRL1_LRADC3_IRQ__##v << 3) & 0x8)
-#define BP_LRADC_CTRL1_LRADC2_IRQ                   2
-#define BM_LRADC_CTRL1_LRADC2_IRQ                   0x4
-#define BV_LRADC_CTRL1_LRADC2_IRQ__CLEAR            0x0
-#define BV_LRADC_CTRL1_LRADC2_IRQ__PENDING          0x1
-#define BF_LRADC_CTRL1_LRADC2_IRQ(v)                (((v) << 2) & 0x4)
-#define BF_LRADC_CTRL1_LRADC2_IRQ_V(v)              ((BV_LRADC_CTRL1_LRADC2_IRQ__##v << 2) & 0x4)
-#define BP_LRADC_CTRL1_LRADC1_IRQ                   1
-#define BM_LRADC_CTRL1_LRADC1_IRQ                   0x2
-#define BV_LRADC_CTRL1_LRADC1_IRQ__CLEAR            0x0
-#define BV_LRADC_CTRL1_LRADC1_IRQ__PENDING          0x1
-#define BF_LRADC_CTRL1_LRADC1_IRQ(v)                (((v) << 1) & 0x2)
-#define BF_LRADC_CTRL1_LRADC1_IRQ_V(v)              ((BV_LRADC_CTRL1_LRADC1_IRQ__##v << 1) & 0x2)
-#define BP_LRADC_CTRL1_LRADC0_IRQ                   0
-#define BM_LRADC_CTRL1_LRADC0_IRQ                   0x1
-#define BV_LRADC_CTRL1_LRADC0_IRQ__CLEAR            0x0
-#define BV_LRADC_CTRL1_LRADC0_IRQ__PENDING          0x1
-#define BF_LRADC_CTRL1_LRADC0_IRQ(v)                (((v) << 0) & 0x1)
-#define BF_LRADC_CTRL1_LRADC0_IRQ_V(v)              ((BV_LRADC_CTRL1_LRADC0_IRQ__##v << 0) & 0x1)
-
-/**
- * Register: HW_LRADC_CTRL2
- * Address: 0x20
- * SCT: yes
-*/
-#define HW_LRADC_CTRL2                                  (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x20 + 0x0))
-#define HW_LRADC_CTRL2_SET                              (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x20 + 0x4))
-#define HW_LRADC_CTRL2_CLR                              (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x20 + 0x8))
-#define HW_LRADC_CTRL2_TOG                              (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x20 + 0xc))
-#define BP_LRADC_CTRL2_DIVIDE_BY_TWO                    24
-#define BM_LRADC_CTRL2_DIVIDE_BY_TWO                    0xff000000
-#define BF_LRADC_CTRL2_DIVIDE_BY_TWO(v)                 (((v) << 24) & 0xff000000)
-#define BP_LRADC_CTRL2_BL_AMP_BYPASS                    23
-#define BM_LRADC_CTRL2_BL_AMP_BYPASS                    0x800000
-#define BV_LRADC_CTRL2_BL_AMP_BYPASS__DISABLE           0x0
-#define BV_LRADC_CTRL2_BL_AMP_BYPASS__ENABLE            0x1
-#define BF_LRADC_CTRL2_BL_AMP_BYPASS(v)                 (((v) << 23) & 0x800000)
-#define BF_LRADC_CTRL2_BL_AMP_BYPASS_V(v)               ((BV_LRADC_CTRL2_BL_AMP_BYPASS__##v << 23) & 0x800000)
-#define BP_LRADC_CTRL2_BL_ENABLE                        22
-#define BM_LRADC_CTRL2_BL_ENABLE                        0x400000
-#define BF_LRADC_CTRL2_BL_ENABLE(v)                     (((v) << 22) & 0x400000)
-#define BP_LRADC_CTRL2_BL_MUX_SELECT                    21
-#define BM_LRADC_CTRL2_BL_MUX_SELECT                    0x200000
-#define BF_LRADC_CTRL2_BL_MUX_SELECT(v)                 (((v) << 21) & 0x200000)
-#define BP_LRADC_CTRL2_BL_BRIGHTNESS                    16
-#define BM_LRADC_CTRL2_BL_BRIGHTNESS                    0x1f0000
-#define BF_LRADC_CTRL2_BL_BRIGHTNESS(v)                 (((v) << 16) & 0x1f0000)
-#define BP_LRADC_CTRL2_TEMPSENSE_PWD                    15
-#define BM_LRADC_CTRL2_TEMPSENSE_PWD                    0x8000
-#define BV_LRADC_CTRL2_TEMPSENSE_PWD__DISABLE           0x0
-#define BV_LRADC_CTRL2_TEMPSENSE_PWD__ENABLE            0x1
-#define BF_LRADC_CTRL2_TEMPSENSE_PWD(v)                 (((v) << 15) & 0x8000)
-#define BF_LRADC_CTRL2_TEMPSENSE_PWD_V(v)               ((BV_LRADC_CTRL2_TEMPSENSE_PWD__##v << 15) & 0x8000)
-#define BP_LRADC_CTRL2_EXT_EN1                          13
-#define BM_LRADC_CTRL2_EXT_EN1                          0x2000
-#define BV_LRADC_CTRL2_EXT_EN1__DISABLE                 0x0
-#define BV_LRADC_CTRL2_EXT_EN1__ENABLE                  0x1
-#define BF_LRADC_CTRL2_EXT_EN1(v)                       (((v) << 13) & 0x2000)
-#define BF_LRADC_CTRL2_EXT_EN1_V(v)                     ((BV_LRADC_CTRL2_EXT_EN1__##v << 13) & 0x2000)
-#define BP_LRADC_CTRL2_EXT_EN0                          12
-#define BM_LRADC_CTRL2_EXT_EN0                          0x1000
-#define BF_LRADC_CTRL2_EXT_EN0(v)                       (((v) << 12) & 0x1000)
-#define BP_LRADC_CTRL2_TEMP_SENSOR_IENABLE1             9
-#define BM_LRADC_CTRL2_TEMP_SENSOR_IENABLE1             0x200
-#define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE1__DISABLE    0x0
-#define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE1__ENABLE     0x1
-#define BF_LRADC_CTRL2_TEMP_SENSOR_IENABLE1(v)          (((v) << 9) & 0x200)
-#define BF_LRADC_CTRL2_TEMP_SENSOR_IENABLE1_V(v)        ((BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE1__##v << 9) & 0x200)
-#define BP_LRADC_CTRL2_TEMP_SENSOR_IENABLE0             8
-#define BM_LRADC_CTRL2_TEMP_SENSOR_IENABLE0             0x100
-#define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE0__DISABLE    0x0
-#define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE0__ENABLE     0x1
-#define BF_LRADC_CTRL2_TEMP_SENSOR_IENABLE0(v)          (((v) << 8) & 0x100)
-#define BF_LRADC_CTRL2_TEMP_SENSOR_IENABLE0_V(v)        ((BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE0__##v << 8) & 0x100)
-#define BP_LRADC_CTRL2_TEMP_ISRC1                       4
-#define BM_LRADC_CTRL2_TEMP_ISRC1                       0xf0
-#define BV_LRADC_CTRL2_TEMP_ISRC1__300                  0xf
-#define BV_LRADC_CTRL2_TEMP_ISRC1__280                  0xe
-#define BV_LRADC_CTRL2_TEMP_ISRC1__260                  0xd
-#define BV_LRADC_CTRL2_TEMP_ISRC1__240                  0xc
-#define BV_LRADC_CTRL2_TEMP_ISRC1__220                  0xb
-#define BV_LRADC_CTRL2_TEMP_ISRC1__200                  0xa
-#define BV_LRADC_CTRL2_TEMP_ISRC1__180                  0x9
-#define BV_LRADC_CTRL2_TEMP_ISRC1__160                  0x8
-#define BV_LRADC_CTRL2_TEMP_ISRC1__140                  0x7
-#define BV_LRADC_CTRL2_TEMP_ISRC1__120                  0x6
-#define BV_LRADC_CTRL2_TEMP_ISRC1__100                  0x5
-#define BV_LRADC_CTRL2_TEMP_ISRC1__80                   0x4
-#define BV_LRADC_CTRL2_TEMP_ISRC1__60                   0x3
-#define BV_LRADC_CTRL2_TEMP_ISRC1__40                   0x2
-#define BV_LRADC_CTRL2_TEMP_ISRC1__20                   0x1
-#define BV_LRADC_CTRL2_TEMP_ISRC1__ZERO                 0x0
-#define BF_LRADC_CTRL2_TEMP_ISRC1(v)                    (((v) << 4) & 0xf0)
-#define BF_LRADC_CTRL2_TEMP_ISRC1_V(v)                  ((BV_LRADC_CTRL2_TEMP_ISRC1__##v << 4) & 0xf0)
-#define BP_LRADC_CTRL2_TEMP_ISRC0                       0
-#define BM_LRADC_CTRL2_TEMP_ISRC0                       0xf
-#define BV_LRADC_CTRL2_TEMP_ISRC0__300                  0xf
-#define BV_LRADC_CTRL2_TEMP_ISRC0__280                  0xe
-#define BV_LRADC_CTRL2_TEMP_ISRC0__260                  0xd
-#define BV_LRADC_CTRL2_TEMP_ISRC0__240                  0xc
-#define BV_LRADC_CTRL2_TEMP_ISRC0__220                  0xb
-#define BV_LRADC_CTRL2_TEMP_ISRC0__200                  0xa
-#define BV_LRADC_CTRL2_TEMP_ISRC0__180                  0x9
-#define BV_LRADC_CTRL2_TEMP_ISRC0__160                  0x8
-#define BV_LRADC_CTRL2_TEMP_ISRC0__140                  0x7
-#define BV_LRADC_CTRL2_TEMP_ISRC0__120                  0x6
-#define BV_LRADC_CTRL2_TEMP_ISRC0__100                  0x5
-#define BV_LRADC_CTRL2_TEMP_ISRC0__80                   0x4
-#define BV_LRADC_CTRL2_TEMP_ISRC0__60                   0x3
-#define BV_LRADC_CTRL2_TEMP_ISRC0__40                   0x2
-#define BV_LRADC_CTRL2_TEMP_ISRC0__20                   0x1
-#define BV_LRADC_CTRL2_TEMP_ISRC0__ZERO                 0x0
-#define BF_LRADC_CTRL2_TEMP_ISRC0(v)                    (((v) << 0) & 0xf)
-#define BF_LRADC_CTRL2_TEMP_ISRC0_V(v)                  ((BV_LRADC_CTRL2_TEMP_ISRC0__##v << 0) & 0xf)
-
-/**
- * Register: HW_LRADC_CTRL3
- * Address: 0x30
- * SCT: yes
-*/
-#define HW_LRADC_CTRL3                          (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x30 + 0x0))
-#define HW_LRADC_CTRL3_SET                      (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x30 + 0x4))
-#define HW_LRADC_CTRL3_CLR                      (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x30 + 0x8))
-#define HW_LRADC_CTRL3_TOG                      (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x30 + 0xc))
-#define BP_LRADC_CTRL3_DISCARD                  24
-#define BM_LRADC_CTRL3_DISCARD                  0x3000000
-#define BV_LRADC_CTRL3_DISCARD__1_SAMPLE        0x1
-#define BV_LRADC_CTRL3_DISCARD__2_SAMPLES       0x2
-#define BV_LRADC_CTRL3_DISCARD__3_SAMPLES       0x3
-#define BF_LRADC_CTRL3_DISCARD(v)               (((v) << 24) & 0x3000000)
-#define BF_LRADC_CTRL3_DISCARD_V(v)             ((BV_LRADC_CTRL3_DISCARD__##v << 24) & 0x3000000)
-#define BP_LRADC_CTRL3_FORCE_ANALOG_PWUP        23
-#define BM_LRADC_CTRL3_FORCE_ANALOG_PWUP        0x800000
-#define BV_LRADC_CTRL3_FORCE_ANALOG_PWUP__OFF   0x0
-#define BV_LRADC_CTRL3_FORCE_ANALOG_PWUP__ON    0x1
-#define BF_LRADC_CTRL3_FORCE_ANALOG_PWUP(v)     (((v) << 23) & 0x800000)
-#define BF_LRADC_CTRL3_FORCE_ANALOG_PWUP_V(v)   ((BV_LRADC_CTRL3_FORCE_ANALOG_PWUP__##v << 23) & 0x800000)
-#define BP_LRADC_CTRL3_FORCE_ANALOG_PWDN        22
-#define BM_LRADC_CTRL3_FORCE_ANALOG_PWDN        0x400000
-#define BV_LRADC_CTRL3_FORCE_ANALOG_PWDN__ON    0x0
-#define BV_LRADC_CTRL3_FORCE_ANALOG_PWDN__OFF   0x1
-#define BF_LRADC_CTRL3_FORCE_ANALOG_PWDN(v)     (((v) << 22) & 0x400000)
-#define BF_LRADC_CTRL3_FORCE_ANALOG_PWDN_V(v)   ((BV_LRADC_CTRL3_FORCE_ANALOG_PWDN__##v << 22) & 0x400000)
-#define BP_LRADC_CTRL3_CYCLE_TIME               8
-#define BM_LRADC_CTRL3_CYCLE_TIME               0x300
-#define BV_LRADC_CTRL3_CYCLE_TIME__6MHZ         0x0
-#define BV_LRADC_CTRL3_CYCLE_TIME__4MHZ         0x1
-#define BV_LRADC_CTRL3_CYCLE_TIME__3MHZ         0x2
-#define BV_LRADC_CTRL3_CYCLE_TIME__2MHZ         0x3
-#define BF_LRADC_CTRL3_CYCLE_TIME(v)            (((v) << 8) & 0x300)
-#define BF_LRADC_CTRL3_CYCLE_TIME_V(v)          ((BV_LRADC_CTRL3_CYCLE_TIME__##v << 8) & 0x300)
-#define BP_LRADC_CTRL3_HIGH_TIME                4
-#define BM_LRADC_CTRL3_HIGH_TIME                0x30
-#define BV_LRADC_CTRL3_HIGH_TIME__42NS          0x0
-#define BV_LRADC_CTRL3_HIGH_TIME__83NS          0x1
-#define BV_LRADC_CTRL3_HIGH_TIME__125NS         0x2
-#define BV_LRADC_CTRL3_HIGH_TIME__250NS         0x3
-#define BF_LRADC_CTRL3_HIGH_TIME(v)             (((v) << 4) & 0x30)
-#define BF_LRADC_CTRL3_HIGH_TIME_V(v)           ((BV_LRADC_CTRL3_HIGH_TIME__##v << 4) & 0x30)
-#define BP_LRADC_CTRL3_DELAY_CLOCK              1
-#define BM_LRADC_CTRL3_DELAY_CLOCK              0x2
-#define BV_LRADC_CTRL3_DELAY_CLOCK__NORMAL      0x0
-#define BV_LRADC_CTRL3_DELAY_CLOCK__DELAYED     0x1
-#define BF_LRADC_CTRL3_DELAY_CLOCK(v)           (((v) << 1) & 0x2)
-#define BF_LRADC_CTRL3_DELAY_CLOCK_V(v)         ((BV_LRADC_CTRL3_DELAY_CLOCK__##v << 1) & 0x2)
-#define BP_LRADC_CTRL3_INVERT_CLOCK             0
-#define BM_LRADC_CTRL3_INVERT_CLOCK             0x1
-#define BV_LRADC_CTRL3_INVERT_CLOCK__NORMAL     0x0
-#define BV_LRADC_CTRL3_INVERT_CLOCK__INVERT     0x1
-#define BF_LRADC_CTRL3_INVERT_CLOCK(v)          (((v) << 0) & 0x1)
-#define BF_LRADC_CTRL3_INVERT_CLOCK_V(v)        ((BV_LRADC_CTRL3_INVERT_CLOCK__##v << 0) & 0x1)
-
-/**
- * Register: HW_LRADC_STATUS
- * Address: 0x40
- * SCT: no
-*/
-#define HW_LRADC_STATUS                         (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x40))
-#define BP_LRADC_STATUS_TEMP1_PRESENT           26
-#define BM_LRADC_STATUS_TEMP1_PRESENT           0x4000000
-#define BF_LRADC_STATUS_TEMP1_PRESENT(v)        (((v) << 26) & 0x4000000)
-#define BP_LRADC_STATUS_TEMP0_PRESENT           25
-#define BM_LRADC_STATUS_TEMP0_PRESENT           0x2000000
-#define BF_LRADC_STATUS_TEMP0_PRESENT(v)        (((v) << 25) & 0x2000000)
-#define BP_LRADC_STATUS_TOUCH_PANEL_PRESENT     24
-#define BM_LRADC_STATUS_TOUCH_PANEL_PRESENT     0x1000000
-#define BF_LRADC_STATUS_TOUCH_PANEL_PRESENT(v)  (((v) << 24) & 0x1000000)
-#define BP_LRADC_STATUS_CHANNEL7_PRESENT        23
-#define BM_LRADC_STATUS_CHANNEL7_PRESENT        0x800000
-#define BF_LRADC_STATUS_CHANNEL7_PRESENT(v)     (((v) << 23) & 0x800000)
-#define BP_LRADC_STATUS_CHANNEL6_PRESENT        22
-#define BM_LRADC_STATUS_CHANNEL6_PRESENT        0x400000
-#define BF_LRADC_STATUS_CHANNEL6_PRESENT(v)     (((v) << 22) & 0x400000)
-#define BP_LRADC_STATUS_CHANNEL5_PRESENT        21
-#define BM_LRADC_STATUS_CHANNEL5_PRESENT        0x200000
-#define BF_LRADC_STATUS_CHANNEL5_PRESENT(v)     (((v) << 21) & 0x200000)
-#define BP_LRADC_STATUS_CHANNEL4_PRESENT        20
-#define BM_LRADC_STATUS_CHANNEL4_PRESENT        0x100000
-#define BF_LRADC_STATUS_CHANNEL4_PRESENT(v)     (((v) << 20) & 0x100000)
-#define BP_LRADC_STATUS_CHANNEL3_PRESENT        19
-#define BM_LRADC_STATUS_CHANNEL3_PRESENT        0x80000
-#define BF_LRADC_STATUS_CHANNEL3_PRESENT(v)     (((v) << 19) & 0x80000)
-#define BP_LRADC_STATUS_CHANNEL2_PRESENT        18
-#define BM_LRADC_STATUS_CHANNEL2_PRESENT        0x40000
-#define BF_LRADC_STATUS_CHANNEL2_PRESENT(v)     (((v) << 18) & 0x40000)
-#define BP_LRADC_STATUS_CHANNEL1_PRESENT        17
-#define BM_LRADC_STATUS_CHANNEL1_PRESENT        0x20000
-#define BF_LRADC_STATUS_CHANNEL1_PRESENT(v)     (((v) << 17) & 0x20000)
-#define BP_LRADC_STATUS_CHANNEL0_PRESENT        16
-#define BM_LRADC_STATUS_CHANNEL0_PRESENT        0x10000
-#define BF_LRADC_STATUS_CHANNEL0_PRESENT(v)     (((v) << 16) & 0x10000)
-#define BP_LRADC_STATUS_TOUCH_DETECT_RAW        0
-#define BM_LRADC_STATUS_TOUCH_DETECT_RAW        0x1
-#define BV_LRADC_STATUS_TOUCH_DETECT_RAW__OPEN  0x0
-#define BV_LRADC_STATUS_TOUCH_DETECT_RAW__HIT   0x1
-#define BF_LRADC_STATUS_TOUCH_DETECT_RAW(v)     (((v) << 0) & 0x1)
-#define BF_LRADC_STATUS_TOUCH_DETECT_RAW_V(v)   ((BV_LRADC_STATUS_TOUCH_DETECT_RAW__##v << 0) & 0x1)
-
-/**
- * Register: HW_LRADC_CHn
- * Address: 0x50+n*0x10
- * SCT: yes
-*/
-#define HW_LRADC_CHn(n)             (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x50+(n)*0x10 + 0x0))
-#define HW_LRADC_CHn_SET(n)         (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x50+(n)*0x10 + 0x4))
-#define HW_LRADC_CHn_CLR(n)         (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x50+(n)*0x10 + 0x8))
-#define HW_LRADC_CHn_TOG(n)         (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x50+(n)*0x10 + 0xc))
-#define BP_LRADC_CHn_TOGGLE         31
-#define BM_LRADC_CHn_TOGGLE         0x80000000
-#define BF_LRADC_CHn_TOGGLE(v)      (((v) << 31) & 0x80000000)
-#define BP_LRADC_CHn_ACCUMULATE     29
-#define BM_LRADC_CHn_ACCUMULATE     0x20000000
-#define BF_LRADC_CHn_ACCUMULATE(v)  (((v) << 29) & 0x20000000)
-#define BP_LRADC_CHn_NUM_SAMPLES    24
-#define BM_LRADC_CHn_NUM_SAMPLES    0x1f000000
-#define BF_LRADC_CHn_NUM_SAMPLES(v) (((v) << 24) & 0x1f000000)
-#define BP_LRADC_CHn_VALUE          0
-#define BM_LRADC_CHn_VALUE          0x3ffff
-#define BF_LRADC_CHn_VALUE(v)       (((v) << 0) & 0x3ffff)
-
-/**
- * Register: HW_LRADC_DELAYn
- * Address: 0xd0+n*0x10
- * SCT: yes
-*/
-#define HW_LRADC_DELAYn(n)                  (*(volatile unsigned long *)(REGS_LRADC_BASE + 0xd0+(n)*0x10 + 0x0))
-#define HW_LRADC_DELAYn_SET(n)              (*(volatile unsigned long *)(REGS_LRADC_BASE + 0xd0+(n)*0x10 + 0x4))
-#define HW_LRADC_DELAYn_CLR(n)              (*(volatile unsigned long *)(REGS_LRADC_BASE + 0xd0+(n)*0x10 + 0x8))
-#define HW_LRADC_DELAYn_TOG(n)              (*(volatile unsigned long *)(REGS_LRADC_BASE + 0xd0+(n)*0x10 + 0xc))
-#define BP_LRADC_DELAYn_TRIGGER_LRADCS      24
-#define BM_LRADC_DELAYn_TRIGGER_LRADCS      0xff000000
-#define BF_LRADC_DELAYn_TRIGGER_LRADCS(v)   (((v) << 24) & 0xff000000)
-#define BP_LRADC_DELAYn_KICK                20
-#define BM_LRADC_DELAYn_KICK                0x100000
-#define BF_LRADC_DELAYn_KICK(v)             (((v) << 20) & 0x100000)
-#define BP_LRADC_DELAYn_TRIGGER_DELAYS      16
-#define BM_LRADC_DELAYn_TRIGGER_DELAYS      0xf0000
-#define BF_LRADC_DELAYn_TRIGGER_DELAYS(v)   (((v) << 16) & 0xf0000)
-#define BP_LRADC_DELAYn_LOOP_COUNT          11
-#define BM_LRADC_DELAYn_LOOP_COUNT          0xf800
-#define BF_LRADC_DELAYn_LOOP_COUNT(v)       (((v) << 11) & 0xf800)
-#define BP_LRADC_DELAYn_DELAY               0
-#define BM_LRADC_DELAYn_DELAY               0x7ff
-#define BF_LRADC_DELAYn_DELAY(v)            (((v) << 0) & 0x7ff)
-
-/**
- * Register: HW_LRADC_DEBUG0
- * Address: 0x110
- * SCT: no
-*/
-#define HW_LRADC_DEBUG0             (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x110))
-#define BP_LRADC_DEBUG0_READONLY    16
-#define BM_LRADC_DEBUG0_READONLY    0xffff0000
-#define BF_LRADC_DEBUG0_READONLY(v) (((v) << 16) & 0xffff0000)
-#define BP_LRADC_DEBUG0_STATE       0
-#define BM_LRADC_DEBUG0_STATE       0xfff
-#define BF_LRADC_DEBUG0_STATE(v)    (((v) << 0) & 0xfff)
-
-/**
- * Register: HW_LRADC_DEBUG1
- * Address: 0x120
- * SCT: yes
-*/
-#define HW_LRADC_DEBUG1                     (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x120 + 0x0))
-#define HW_LRADC_DEBUG1_SET                 (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x120 + 0x4))
-#define HW_LRADC_DEBUG1_CLR                 (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x120 + 0x8))
-#define HW_LRADC_DEBUG1_TOG                 (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x120 + 0xc))
-#define BP_LRADC_DEBUG1_REQUEST             16
-#define BM_LRADC_DEBUG1_REQUEST             0xff0000
-#define BF_LRADC_DEBUG1_REQUEST(v)          (((v) << 16) & 0xff0000)
-#define BP_LRADC_DEBUG1_TESTMODE_COUNT      8
-#define BM_LRADC_DEBUG1_TESTMODE_COUNT      0x1f00
-#define BF_LRADC_DEBUG1_TESTMODE_COUNT(v)   (((v) << 8) & 0x1f00)
-#define BP_LRADC_DEBUG1_TESTMODE6           2
-#define BM_LRADC_DEBUG1_TESTMODE6           0x4
-#define BV_LRADC_DEBUG1_TESTMODE6__NORMAL   0x0
-#define BV_LRADC_DEBUG1_TESTMODE6__TEST     0x1
-#define BF_LRADC_DEBUG1_TESTMODE6(v)        (((v) << 2) & 0x4)
-#define BF_LRADC_DEBUG1_TESTMODE6_V(v)      ((BV_LRADC_DEBUG1_TESTMODE6__##v << 2) & 0x4)
-#define BP_LRADC_DEBUG1_TESTMODE5           1
-#define BM_LRADC_DEBUG1_TESTMODE5           0x2
-#define BV_LRADC_DEBUG1_TESTMODE5__NORMAL   0x0
-#define BV_LRADC_DEBUG1_TESTMODE5__TEST     0x1
-#define BF_LRADC_DEBUG1_TESTMODE5(v)        (((v) << 1) & 0x2)
-#define BF_LRADC_DEBUG1_TESTMODE5_V(v)      ((BV_LRADC_DEBUG1_TESTMODE5__##v << 1) & 0x2)
-#define BP_LRADC_DEBUG1_TESTMODE            0
-#define BM_LRADC_DEBUG1_TESTMODE            0x1
-#define BV_LRADC_DEBUG1_TESTMODE__NORMAL    0x0
-#define BV_LRADC_DEBUG1_TESTMODE__TEST      0x1
-#define BF_LRADC_DEBUG1_TESTMODE(v)         (((v) << 0) & 0x1)
-#define BF_LRADC_DEBUG1_TESTMODE_V(v)       ((BV_LRADC_DEBUG1_TESTMODE__##v << 0) & 0x1)
-
-/**
- * Register: HW_LRADC_CONVERSION
- * Address: 0x130
- * SCT: yes
-*/
-#define HW_LRADC_CONVERSION                             (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x130 + 0x0))
-#define HW_LRADC_CONVERSION_SET                         (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x130 + 0x4))
-#define HW_LRADC_CONVERSION_CLR                         (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x130 + 0x8))
-#define HW_LRADC_CONVERSION_TOG                         (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x130 + 0xc))
-#define BP_LRADC_CONVERSION_AUTOMATIC                   20
-#define BM_LRADC_CONVERSION_AUTOMATIC                   0x100000
-#define BV_LRADC_CONVERSION_AUTOMATIC__DISABLE          0x0
-#define BV_LRADC_CONVERSION_AUTOMATIC__ENABLE           0x1
-#define BF_LRADC_CONVERSION_AUTOMATIC(v)                (((v) << 20) & 0x100000)
-#define BF_LRADC_CONVERSION_AUTOMATIC_V(v)              ((BV_LRADC_CONVERSION_AUTOMATIC__##v << 20) & 0x100000)
-#define BP_LRADC_CONVERSION_SCALE_FACTOR                16
-#define BM_LRADC_CONVERSION_SCALE_FACTOR                0x30000
-#define BV_LRADC_CONVERSION_SCALE_FACTOR__NIMH          0x0
-#define BV_LRADC_CONVERSION_SCALE_FACTOR__DUAL_NIMH     0x1
-#define BV_LRADC_CONVERSION_SCALE_FACTOR__LI_ION        0x2
-#define BV_LRADC_CONVERSION_SCALE_FACTOR__ALT_LI_ION    0x3
-#define BF_LRADC_CONVERSION_SCALE_FACTOR(v)             (((v) << 16) & 0x30000)
-#define BF_LRADC_CONVERSION_SCALE_FACTOR_V(v)           ((BV_LRADC_CONVERSION_SCALE_FACTOR__##v << 16) & 0x30000)
-#define BP_LRADC_CONVERSION_SCALED_BATT_VOLTAGE         0
-#define BM_LRADC_CONVERSION_SCALED_BATT_VOLTAGE         0x3ff
-#define BF_LRADC_CONVERSION_SCALED_BATT_VOLTAGE(v)      (((v) << 0) & 0x3ff)
-
-/**
- * Register: HW_LRADC_CTRL4
- * Address: 0x140
- * SCT: yes
-*/
-#define HW_LRADC_CTRL4                          (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x140 + 0x0))
-#define HW_LRADC_CTRL4_SET                      (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x140 + 0x4))
-#define HW_LRADC_CTRL4_CLR                      (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x140 + 0x8))
-#define HW_LRADC_CTRL4_TOG                      (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x140 + 0xc))
-#define BP_LRADC_CTRL4_LRADC7SELECT             28
-#define BM_LRADC_CTRL4_LRADC7SELECT             0xf0000000
-#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL0   0x0
-#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL1   0x1
-#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL2   0x2
-#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL3   0x3
-#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL4   0x4
-#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL5   0x5
-#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL6   0x6
-#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL7   0x7
-#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL8   0x8
-#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL9   0x9
-#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL10  0xa
-#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL11  0xb
-#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL12  0xc
-#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL13  0xd
-#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL14  0xe
-#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL15  0xf
-#define BF_LRADC_CTRL4_LRADC7SELECT(v)          (((v) << 28) & 0xf0000000)
-#define BF_LRADC_CTRL4_LRADC7SELECT_V(v)        ((BV_LRADC_CTRL4_LRADC7SELECT__##v << 28) & 0xf0000000)
-#define BP_LRADC_CTRL4_LRADC6SELECT             24
-#define BM_LRADC_CTRL4_LRADC6SELECT             0xf000000
-#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL0   0x0
-#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL1   0x1
-#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL2   0x2
-#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL3   0x3
-#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL4   0x4
-#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL5   0x5
-#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL6   0x6
-#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL7   0x7
-#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL8   0x8
-#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL9   0x9
-#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL10  0xa
-#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL11  0xb
-#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL12  0xc
-#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL13  0xd
-#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL14  0xe
-#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL15  0xf
-#define BF_LRADC_CTRL4_LRADC6SELECT(v)          (((v) << 24) & 0xf000000)
-#define BF_LRADC_CTRL4_LRADC6SELECT_V(v)        ((BV_LRADC_CTRL4_LRADC6SELECT__##v << 24) & 0xf000000)
-#define BP_LRADC_CTRL4_LRADC5SELECT             20
-#define BM_LRADC_CTRL4_LRADC5SELECT             0xf00000
-#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL0   0x0
-#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL1   0x1
-#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL2   0x2
-#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL3   0x3
-#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL4   0x4
-#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL5   0x5
-#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL6   0x6
-#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL7   0x7
-#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL8   0x8
-#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL9   0x9
-#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL10  0xa
-#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL11  0xb
-#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL12  0xc
-#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL13  0xd
-#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL14  0xe
-#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL15  0xf
-#define BF_LRADC_CTRL4_LRADC5SELECT(v)          (((v) << 20) & 0xf00000)
-#define BF_LRADC_CTRL4_LRADC5SELECT_V(v)        ((BV_LRADC_CTRL4_LRADC5SELECT__##v << 20) & 0xf00000)
-#define BP_LRADC_CTRL4_LRADC4SELECT             16
-#define BM_LRADC_CTRL4_LRADC4SELECT             0xf0000
-#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL0   0x0
-#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL1   0x1
-#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL2   0x2
-#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL3   0x3
-#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL4   0x4
-#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL5   0x5
-#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL6   0x6
-#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL7   0x7
-#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL8   0x8
-#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL9   0x9
-#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL10  0xa
-#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL11  0xb
-#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL12  0xc
-#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL13  0xd
-#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL14  0xe
-#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL15  0xf
-#define BF_LRADC_CTRL4_LRADC4SELECT(v)          (((v) << 16) & 0xf0000)
-#define BF_LRADC_CTRL4_LRADC4SELECT_V(v)        ((BV_LRADC_CTRL4_LRADC4SELECT__##v << 16) & 0xf0000)
-#define BP_LRADC_CTRL4_LRADC3SELECT             12
-#define BM_LRADC_CTRL4_LRADC3SELECT             0xf000
-#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL0   0x0
-#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL1   0x1
-#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL2   0x2
-#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL3   0x3
-#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL4   0x4
-#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL5   0x5
-#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL6   0x6
-#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL7   0x7
-#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL8   0x8
-#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL9   0x9
-#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL10  0xa
-#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL11  0xb
-#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL12  0xc
-#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL13  0xd
-#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL14  0xe
-#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL15  0xf
-#define BF_LRADC_CTRL4_LRADC3SELECT(v)          (((v) << 12) & 0xf000)
-#define BF_LRADC_CTRL4_LRADC3SELECT_V(v)        ((BV_LRADC_CTRL4_LRADC3SELECT__##v << 12) & 0xf000)
-#define BP_LRADC_CTRL4_LRADC2SELECT             8
-#define BM_LRADC_CTRL4_LRADC2SELECT             0xf00
-#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL0   0x0
-#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL1   0x1
-#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL2   0x2
-#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL3   0x3
-#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL4   0x4
-#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL5   0x5
-#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL6   0x6
-#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL7   0x7
-#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL8   0x8
-#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL9   0x9
-#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL10  0xa
-#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL11  0xb
-#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL12  0xc
-#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL13  0xd
-#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL14  0xe
-#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL15  0xf
-#define BF_LRADC_CTRL4_LRADC2SELECT(v)          (((v) << 8) & 0xf00)
-#define BF_LRADC_CTRL4_LRADC2SELECT_V(v)        ((BV_LRADC_CTRL4_LRADC2SELECT__##v << 8) & 0xf00)
-#define BP_LRADC_CTRL4_LRADC1SELECT             4
-#define BM_LRADC_CTRL4_LRADC1SELECT             0xf0
-#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL0   0x0
-#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL1   0x1
-#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL2   0x2
-#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL3   0x3
-#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL4   0x4
-#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL5   0x5
-#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL6   0x6
-#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL7   0x7
-#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL8   0x8
-#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL9   0x9
-#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL10  0xa
-#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL11  0xb
-#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL12  0xc
-#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL13  0xd
-#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL14  0xe
-#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL15  0xf
-#define BF_LRADC_CTRL4_LRADC1SELECT(v)          (((v) << 4) & 0xf0)
-#define BF_LRADC_CTRL4_LRADC1SELECT_V(v)        ((BV_LRADC_CTRL4_LRADC1SELECT__##v << 4) & 0xf0)
-#define BP_LRADC_CTRL4_LRADC0SELECT             0
-#define BM_LRADC_CTRL4_LRADC0SELECT             0xf
-#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL0   0x0
-#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL1   0x1
-#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL2   0x2
-#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL3   0x3
-#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL4   0x4
-#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL5   0x5
-#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL6   0x6
-#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL7   0x7
-#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL8   0x8
-#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL9   0x9
-#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL10  0xa
-#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL11  0xb
-#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL12  0xc
-#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL13  0xd
-#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL14  0xe
-#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL15  0xf
-#define BF_LRADC_CTRL4_LRADC0SELECT(v)          (((v) << 0) & 0xf)
-#define BF_LRADC_CTRL4_LRADC0SELECT_V(v)        ((BV_LRADC_CTRL4_LRADC0SELECT__##v << 0) & 0xf)
-
-/**
- * Register: HW_LRADC_VERSION
- * Address: 0x150
- * SCT: no
-*/
-#define HW_LRADC_VERSION            (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x150))
-#define BP_LRADC_VERSION_MAJOR      24
-#define BM_LRADC_VERSION_MAJOR      0xff000000
-#define BF_LRADC_VERSION_MAJOR(v)   (((v) << 24) & 0xff000000)
-#define BP_LRADC_VERSION_MINOR      16
-#define BM_LRADC_VERSION_MINOR      0xff0000
-#define BF_LRADC_VERSION_MINOR(v)   (((v) << 16) & 0xff0000)
-#define BP_LRADC_VERSION_STEP       0
-#define BM_LRADC_VERSION_STEP       0xffff
-#define BF_LRADC_VERSION_STEP(v)    (((v) << 0) & 0xffff)
-
-#endif /* __HEADERGEN__STMP3700__LRADC__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-ocotp.h b/firmware/target/arm/imx233/regs/stmp3700/regs-ocotp.h
deleted file mode 100644
index 574ab22c43..0000000000
--- a/firmware/target/arm/imx233/regs/stmp3700/regs-ocotp.h
+++ /dev/null
@@ -1,254 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3700:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__STMP3700__OCOTP__H__
-#define __HEADERGEN__STMP3700__OCOTP__H__
-
-#define REGS_OCOTP_BASE (0x8002c000)
-
-#define REGS_OCOTP_VERSION "3.2.0"
-
-/**
- * Register: HW_OCOTP_CTRL
- * Address: 0
- * SCT: yes
-*/
-#define HW_OCOTP_CTRL                   (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x0 + 0x0))
-#define HW_OCOTP_CTRL_SET               (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x0 + 0x4))
-#define HW_OCOTP_CTRL_CLR               (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x0 + 0x8))
-#define HW_OCOTP_CTRL_TOG               (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x0 + 0xc))
-#define BP_OCOTP_CTRL_WR_UNLOCK         16
-#define BM_OCOTP_CTRL_WR_UNLOCK         0xffff0000
-#define BV_OCOTP_CTRL_WR_UNLOCK__KEY    0x3e77
-#define BF_OCOTP_CTRL_WR_UNLOCK(v)      (((v) << 16) & 0xffff0000)
-#define BF_OCOTP_CTRL_WR_UNLOCK_V(v)    ((BV_OCOTP_CTRL_WR_UNLOCK__##v << 16) & 0xffff0000)
-#define BP_OCOTP_CTRL_RELOAD_SHADOWS    13
-#define BM_OCOTP_CTRL_RELOAD_SHADOWS    0x2000
-#define BF_OCOTP_CTRL_RELOAD_SHADOWS(v) (((v) << 13) & 0x2000)
-#define BP_OCOTP_CTRL_RD_BANK_OPEN      12
-#define BM_OCOTP_CTRL_RD_BANK_OPEN      0x1000
-#define BF_OCOTP_CTRL_RD_BANK_OPEN(v)   (((v) << 12) & 0x1000)
-#define BP_OCOTP_CTRL_ERROR             9
-#define BM_OCOTP_CTRL_ERROR             0x200
-#define BF_OCOTP_CTRL_ERROR(v)          (((v) << 9) & 0x200)
-#define BP_OCOTP_CTRL_BUSY              8
-#define BM_OCOTP_CTRL_BUSY              0x100
-#define BF_OCOTP_CTRL_BUSY(v)           (((v) << 8) & 0x100)
-#define BP_OCOTP_CTRL_ADDR              0
-#define BM_OCOTP_CTRL_ADDR              0x1f
-#define BF_OCOTP_CTRL_ADDR(v)           (((v) << 0) & 0x1f)
-
-/**
- * Register: HW_OCOTP_DATA
- * Address: 0x10
- * SCT: no
-*/
-#define HW_OCOTP_DATA           (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x10))
-#define BP_OCOTP_DATA_DATA      0
-#define BM_OCOTP_DATA_DATA      0xffffffff
-#define BF_OCOTP_DATA_DATA(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_OCOTP_CUSTn
- * Address: 0x20+n*0x10
- * SCT: no
-*/
-#define HW_OCOTP_CUSTn(n)       (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x20+(n)*0x10))
-#define BP_OCOTP_CUSTn_BITS     0
-#define BM_OCOTP_CUSTn_BITS     0xffffffff
-#define BF_OCOTP_CUSTn_BITS(v)  (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_OCOTP_CRYPTOn
- * Address: 0x60+n*0x10
- * SCT: no
-*/
-#define HW_OCOTP_CRYPTOn(n)         (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x60+(n)*0x10))
-#define BP_OCOTP_CRYPTOn_BITS       0
-#define BM_OCOTP_CRYPTOn_BITS       0xffffffff
-#define BF_OCOTP_CRYPTOn_BITS(v)    (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_OCOTP_HWCAPn
- * Address: 0xa0+n*0x10
- * SCT: no
-*/
-#define HW_OCOTP_HWCAPn(n)      (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0xa0+(n)*0x10))
-#define BP_OCOTP_HWCAPn_BITS    0
-#define BM_OCOTP_HWCAPn_BITS    0xffffffff
-#define BF_OCOTP_HWCAPn_BITS(v) (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_OCOTP_SWCAP
- * Address: 0x100
- * SCT: no
-*/
-#define HW_OCOTP_SWCAP          (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x100))
-#define BP_OCOTP_SWCAP_BITS     0
-#define BM_OCOTP_SWCAP_BITS     0xffffffff
-#define BF_OCOTP_SWCAP_BITS(v)  (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_OCOTP_CUSTCAP
- * Address: 0x110
- * SCT: no
-*/
-#define HW_OCOTP_CUSTCAP            (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x110))
-#define BP_OCOTP_CUSTCAP_BITS       0
-#define BM_OCOTP_CUSTCAP_BITS       0xffffffff
-#define BF_OCOTP_CUSTCAP_BITS(v)    (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_OCOTP_LOCK
- * Address: 0x120
- * SCT: no
-*/
-#define HW_OCOTP_LOCK                       (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x120))
-#define BP_OCOTP_LOCK_ROM7                  31
-#define BM_OCOTP_LOCK_ROM7                  0x80000000
-#define BF_OCOTP_LOCK_ROM7(v)               (((v) << 31) & 0x80000000)
-#define BP_OCOTP_LOCK_ROM6                  30
-#define BM_OCOTP_LOCK_ROM6                  0x40000000
-#define BF_OCOTP_LOCK_ROM6(v)               (((v) << 30) & 0x40000000)
-#define BP_OCOTP_LOCK_ROM5                  29
-#define BM_OCOTP_LOCK_ROM5                  0x20000000
-#define BF_OCOTP_LOCK_ROM5(v)               (((v) << 29) & 0x20000000)
-#define BP_OCOTP_LOCK_ROM4                  28
-#define BM_OCOTP_LOCK_ROM4                  0x10000000
-#define BF_OCOTP_LOCK_ROM4(v)               (((v) << 28) & 0x10000000)
-#define BP_OCOTP_LOCK_ROM3                  27
-#define BM_OCOTP_LOCK_ROM3                  0x8000000
-#define BF_OCOTP_LOCK_ROM3(v)               (((v) << 27) & 0x8000000)
-#define BP_OCOTP_LOCK_ROM2                  26
-#define BM_OCOTP_LOCK_ROM2                  0x4000000
-#define BF_OCOTP_LOCK_ROM2(v)               (((v) << 26) & 0x4000000)
-#define BP_OCOTP_LOCK_ROM1                  25
-#define BM_OCOTP_LOCK_ROM1                  0x2000000
-#define BF_OCOTP_LOCK_ROM1(v)               (((v) << 25) & 0x2000000)
-#define BP_OCOTP_LOCK_ROM0                  24
-#define BM_OCOTP_LOCK_ROM0                  0x1000000
-#define BF_OCOTP_LOCK_ROM0(v)               (((v) << 24) & 0x1000000)
-#define BP_OCOTP_LOCK_HWSW_SHADOW_ALT       23
-#define BM_OCOTP_LOCK_HWSW_SHADOW_ALT       0x800000
-#define BF_OCOTP_LOCK_HWSW_SHADOW_ALT(v)    (((v) << 23) & 0x800000)
-#define BP_OCOTP_LOCK_CRYPTODCP_ALT         22
-#define BM_OCOTP_LOCK_CRYPTODCP_ALT         0x400000
-#define BF_OCOTP_LOCK_CRYPTODCP_ALT(v)      (((v) << 22) & 0x400000)
-#define BP_OCOTP_LOCK_CRYPTOKEY_ALT         21
-#define BM_OCOTP_LOCK_CRYPTOKEY_ALT         0x200000
-#define BF_OCOTP_LOCK_CRYPTOKEY_ALT(v)      (((v) << 21) & 0x200000)
-#define BP_OCOTP_LOCK_PIN                   20
-#define BM_OCOTP_LOCK_PIN                   0x100000
-#define BF_OCOTP_LOCK_PIN(v)                (((v) << 20) & 0x100000)
-#define BP_OCOTP_LOCK_OPS                   19
-#define BM_OCOTP_LOCK_OPS                   0x80000
-#define BF_OCOTP_LOCK_OPS(v)                (((v) << 19) & 0x80000)
-#define BP_OCOTP_LOCK_UN2                   18
-#define BM_OCOTP_LOCK_UN2                   0x40000
-#define BF_OCOTP_LOCK_UN2(v)                (((v) << 18) & 0x40000)
-#define BP_OCOTP_LOCK_UN1                   17
-#define BM_OCOTP_LOCK_UN1                   0x20000
-#define BF_OCOTP_LOCK_UN1(v)                (((v) << 17) & 0x20000)
-#define BP_OCOTP_LOCK_UN0                   16
-#define BM_OCOTP_LOCK_UN0                   0x10000
-#define BF_OCOTP_LOCK_UN0(v)                (((v) << 16) & 0x10000)
-#define BP_OCOTP_LOCK_UNALLOCATED           10
-#define BM_OCOTP_LOCK_UNALLOCATED           0xfc00
-#define BF_OCOTP_LOCK_UNALLOCATED(v)        (((v) << 10) & 0xfc00)
-#define BP_OCOTP_LOCK_CUSTCAP               9
-#define BM_OCOTP_LOCK_CUSTCAP               0x200
-#define BF_OCOTP_LOCK_CUSTCAP(v)            (((v) << 9) & 0x200)
-#define BP_OCOTP_LOCK_HWSW                  8
-#define BM_OCOTP_LOCK_HWSW                  0x100
-#define BF_OCOTP_LOCK_HWSW(v)               (((v) << 8) & 0x100)
-#define BP_OCOTP_LOCK_CUSTCAP_SHADOW        7
-#define BM_OCOTP_LOCK_CUSTCAP_SHADOW        0x80
-#define BF_OCOTP_LOCK_CUSTCAP_SHADOW(v)     (((v) << 7) & 0x80)
-#define BP_OCOTP_LOCK_HWSW_SHADOW           6
-#define BM_OCOTP_LOCK_HWSW_SHADOW           0x40
-#define BF_OCOTP_LOCK_HWSW_SHADOW(v)        (((v) << 6) & 0x40)
-#define BP_OCOTP_LOCK_CRYPTODCP             5
-#define BM_OCOTP_LOCK_CRYPTODCP             0x20
-#define BF_OCOTP_LOCK_CRYPTODCP(v)          (((v) << 5) & 0x20)
-#define BP_OCOTP_LOCK_CRYPTOKEY             4
-#define BM_OCOTP_LOCK_CRYPTOKEY             0x10
-#define BF_OCOTP_LOCK_CRYPTOKEY(v)          (((v) << 4) & 0x10)
-#define BP_OCOTP_LOCK_CUST3                 3
-#define BM_OCOTP_LOCK_CUST3                 0x8
-#define BF_OCOTP_LOCK_CUST3(v)              (((v) << 3) & 0x8)
-#define BP_OCOTP_LOCK_CUST2                 2
-#define BM_OCOTP_LOCK_CUST2                 0x4
-#define BF_OCOTP_LOCK_CUST2(v)              (((v) << 2) & 0x4)
-#define BP_OCOTP_LOCK_CUST1                 1
-#define BM_OCOTP_LOCK_CUST1                 0x2
-#define BF_OCOTP_LOCK_CUST1(v)              (((v) << 1) & 0x2)
-#define BP_OCOTP_LOCK_CUST0                 0
-#define BM_OCOTP_LOCK_CUST0                 0x1
-#define BF_OCOTP_LOCK_CUST0(v)              (((v) << 0) & 0x1)
-
-/**
- * Register: HW_OCOTP_OPSn
- * Address: 0x130+n*0x10
- * SCT: no
-*/
-#define HW_OCOTP_OPSn(n)        (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x130+(n)*0x10))
-#define BP_OCOTP_OPSn_BITS      0
-#define BM_OCOTP_OPSn_BITS      0xffffffff
-#define BF_OCOTP_OPSn_BITS(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_OCOTP_UNn
- * Address: 0x170+n*0x10
- * SCT: no
-*/
-#define HW_OCOTP_UNn(n)         (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x170+(n)*0x10))
-#define BP_OCOTP_UNn_BITS       0
-#define BM_OCOTP_UNn_BITS       0xffffffff
-#define BF_OCOTP_UNn_BITS(v)    (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_OCOTP_ROMn
- * Address: 0x1a0+n*0x10
- * SCT: no
-*/
-#define HW_OCOTP_ROMn(n)        (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x1a0+(n)*0x10))
-#define BP_OCOTP_ROMn_BITS      0
-#define BM_OCOTP_ROMn_BITS      0xffffffff
-#define BF_OCOTP_ROMn_BITS(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_OCOTP_VERSION
- * Address: 0x220
- * SCT: no
-*/
-#define HW_OCOTP_VERSION            (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x220))
-#define BP_OCOTP_VERSION_MAJOR      24
-#define BM_OCOTP_VERSION_MAJOR      0xff000000
-#define BF_OCOTP_VERSION_MAJOR(v)   (((v) << 24) & 0xff000000)
-#define BP_OCOTP_VERSION_MINOR      16
-#define BM_OCOTP_VERSION_MINOR      0xff0000
-#define BF_OCOTP_VERSION_MINOR(v)   (((v) << 16) & 0xff0000)
-#define BP_OCOTP_VERSION_STEP       0
-#define BM_OCOTP_VERSION_STEP       0xffff
-#define BF_OCOTP_VERSION_STEP(v)    (((v) << 0) & 0xffff)
-
-#endif /* __HEADERGEN__STMP3700__OCOTP__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-pinctrl.h b/firmware/target/arm/imx233/regs/stmp3700/regs-pinctrl.h
deleted file mode 100644
index 102bf876ab..0000000000
--- a/firmware/target/arm/imx233/regs/stmp3700/regs-pinctrl.h
+++ /dev/null
@@ -1,213 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3700:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__STMP3700__PINCTRL__H__
-#define __HEADERGEN__STMP3700__PINCTRL__H__
-
-#define REGS_PINCTRL_BASE (0x80018000)
-
-#define REGS_PINCTRL_VERSION "3.2.0"
-
-/**
- * Register: HW_PINCTRL_CTRL
- * Address: 0
- * SCT: yes
-*/
-#define HW_PINCTRL_CTRL             (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x0 + 0x0))
-#define HW_PINCTRL_CTRL_SET         (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x0 + 0x4))
-#define HW_PINCTRL_CTRL_CLR         (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x0 + 0x8))
-#define HW_PINCTRL_CTRL_TOG         (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x0 + 0xc))
-#define BP_PINCTRL_CTRL_SFTRST      31
-#define BM_PINCTRL_CTRL_SFTRST      0x80000000
-#define BF_PINCTRL_CTRL_SFTRST(v)   (((v) << 31) & 0x80000000)
-#define BP_PINCTRL_CTRL_CLKGATE     30
-#define BM_PINCTRL_CTRL_CLKGATE     0x40000000
-#define BF_PINCTRL_CTRL_CLKGATE(v)  (((v) << 30) & 0x40000000)
-#define BP_PINCTRL_CTRL_PRESENT3    29
-#define BM_PINCTRL_CTRL_PRESENT3    0x20000000
-#define BF_PINCTRL_CTRL_PRESENT3(v) (((v) << 29) & 0x20000000)
-#define BP_PINCTRL_CTRL_PRESENT2    28
-#define BM_PINCTRL_CTRL_PRESENT2    0x10000000
-#define BF_PINCTRL_CTRL_PRESENT2(v) (((v) << 28) & 0x10000000)
-#define BP_PINCTRL_CTRL_PRESENT1    27
-#define BM_PINCTRL_CTRL_PRESENT1    0x8000000
-#define BF_PINCTRL_CTRL_PRESENT1(v) (((v) << 27) & 0x8000000)
-#define BP_PINCTRL_CTRL_PRESENT0    26
-#define BM_PINCTRL_CTRL_PRESENT0    0x4000000
-#define BF_PINCTRL_CTRL_PRESENT0(v) (((v) << 26) & 0x4000000)
-#define BP_PINCTRL_CTRL_IRQOUT3     3
-#define BM_PINCTRL_CTRL_IRQOUT3     0x8
-#define BF_PINCTRL_CTRL_IRQOUT3(v)  (((v) << 3) & 0x8)
-#define BP_PINCTRL_CTRL_IRQOUT2     2
-#define BM_PINCTRL_CTRL_IRQOUT2     0x4
-#define BF_PINCTRL_CTRL_IRQOUT2(v)  (((v) << 2) & 0x4)
-#define BP_PINCTRL_CTRL_IRQOUT1     1
-#define BM_PINCTRL_CTRL_IRQOUT1     0x2
-#define BF_PINCTRL_CTRL_IRQOUT1(v)  (((v) << 1) & 0x2)
-#define BP_PINCTRL_CTRL_IRQOUT0     0
-#define BM_PINCTRL_CTRL_IRQOUT0     0x1
-#define BF_PINCTRL_CTRL_IRQOUT0(v)  (((v) << 0) & 0x1)
-
-/**
- * Register: HW_PINCTRL_MUXSELn
- * Address: 0x100+n*0x10
- * SCT: yes
-*/
-#define HW_PINCTRL_MUXSELn(n)       (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x100+(n)*0x10 + 0x0))
-#define HW_PINCTRL_MUXSELn_SET(n)   (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x100+(n)*0x10 + 0x4))
-#define HW_PINCTRL_MUXSELn_CLR(n)   (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x100+(n)*0x10 + 0x8))
-#define HW_PINCTRL_MUXSELn_TOG(n)   (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x100+(n)*0x10 + 0xc))
-#define BP_PINCTRL_MUXSELn_BITS     0
-#define BM_PINCTRL_MUXSELn_BITS     0xffffffff
-#define BF_PINCTRL_MUXSELn_BITS(v)  (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_PINCTRL_DRIVEn
- * Address: 0x200+n*0x10
- * SCT: yes
-*/
-#define HW_PINCTRL_DRIVEn(n)        (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x200+(n)*0x10 + 0x0))
-#define HW_PINCTRL_DRIVEn_SET(n)    (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x200+(n)*0x10 + 0x4))
-#define HW_PINCTRL_DRIVEn_CLR(n)    (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x200+(n)*0x10 + 0x8))
-#define HW_PINCTRL_DRIVEn_TOG(n)    (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x200+(n)*0x10 + 0xc))
-#define BP_PINCTRL_DRIVEn_BITS      0
-#define BM_PINCTRL_DRIVEn_BITS      0xffffffff
-#define BF_PINCTRL_DRIVEn_BITS(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_PINCTRL_PULLn
- * Address: 0x300+n*0x10
- * SCT: yes
-*/
-#define HW_PINCTRL_PULLn(n)         (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x300+(n)*0x10 + 0x0))
-#define HW_PINCTRL_PULLn_SET(n)     (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x300+(n)*0x10 + 0x4))
-#define HW_PINCTRL_PULLn_CLR(n)     (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x300+(n)*0x10 + 0x8))
-#define HW_PINCTRL_PULLn_TOG(n)     (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x300+(n)*0x10 + 0xc))
-#define BP_PINCTRL_PULLn_BITS       0
-#define BM_PINCTRL_PULLn_BITS       0xffffffff
-#define BF_PINCTRL_PULLn_BITS(v)    (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_PINCTRL_DOUTn
- * Address: 0x400+n*0x10
- * SCT: yes
-*/
-#define HW_PINCTRL_DOUTn(n)         (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x400+(n)*0x10 + 0x0))
-#define HW_PINCTRL_DOUTn_SET(n)     (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x400+(n)*0x10 + 0x4))
-#define HW_PINCTRL_DOUTn_CLR(n)     (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x400+(n)*0x10 + 0x8))
-#define HW_PINCTRL_DOUTn_TOG(n)     (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x400+(n)*0x10 + 0xc))
-#define BP_PINCTRL_DOUTn_BITS       0
-#define BM_PINCTRL_DOUTn_BITS       0xffffffff
-#define BF_PINCTRL_DOUTn_BITS(v)    (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_PINCTRL_DINn
- * Address: 0x500+n*0x10
- * SCT: yes
-*/
-#define HW_PINCTRL_DINn(n)      (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x500+(n)*0x10 + 0x0))
-#define HW_PINCTRL_DINn_SET(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x500+(n)*0x10 + 0x4))
-#define HW_PINCTRL_DINn_CLR(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x500+(n)*0x10 + 0x8))
-#define HW_PINCTRL_DINn_TOG(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x500+(n)*0x10 + 0xc))
-#define BP_PINCTRL_DINn_BITS    0
-#define BM_PINCTRL_DINn_BITS    0xffffffff
-#define BF_PINCTRL_DINn_BITS(v) (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_PINCTRL_DOEn
- * Address: 0x600+n*0x10
- * SCT: yes
-*/
-#define HW_PINCTRL_DOEn(n)      (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x600+(n)*0x10 + 0x0))
-#define HW_PINCTRL_DOEn_SET(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x600+(n)*0x10 + 0x4))
-#define HW_PINCTRL_DOEn_CLR(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x600+(n)*0x10 + 0x8))
-#define HW_PINCTRL_DOEn_TOG(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x600+(n)*0x10 + 0xc))
-#define BP_PINCTRL_DOEn_BITS    0
-#define BM_PINCTRL_DOEn_BITS    0xffffffff
-#define BF_PINCTRL_DOEn_BITS(v) (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_PINCTRL_PIN2IRQn
- * Address: 0x700+n*0x10
- * SCT: yes
-*/
-#define HW_PINCTRL_PIN2IRQn(n)      (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x700+(n)*0x10 + 0x0))
-#define HW_PINCTRL_PIN2IRQn_SET(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x700+(n)*0x10 + 0x4))
-#define HW_PINCTRL_PIN2IRQn_CLR(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x700+(n)*0x10 + 0x8))
-#define HW_PINCTRL_PIN2IRQn_TOG(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x700+(n)*0x10 + 0xc))
-#define BP_PINCTRL_PIN2IRQn_BITS    0
-#define BM_PINCTRL_PIN2IRQn_BITS    0xffffffff
-#define BF_PINCTRL_PIN2IRQn_BITS(v) (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_PINCTRL_IRQENn
- * Address: 0x800+n*0x10
- * SCT: yes
-*/
-#define HW_PINCTRL_IRQENn(n)        (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x800+(n)*0x10 + 0x0))
-#define HW_PINCTRL_IRQENn_SET(n)    (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x800+(n)*0x10 + 0x4))
-#define HW_PINCTRL_IRQENn_CLR(n)    (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x800+(n)*0x10 + 0x8))
-#define HW_PINCTRL_IRQENn_TOG(n)    (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x800+(n)*0x10 + 0xc))
-#define BP_PINCTRL_IRQENn_BITS      0
-#define BM_PINCTRL_IRQENn_BITS      0xffffffff
-#define BF_PINCTRL_IRQENn_BITS(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_PINCTRL_IRQLEVELn
- * Address: 0x900+n*0x10
- * SCT: yes
-*/
-#define HW_PINCTRL_IRQLEVELn(n)         (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x900+(n)*0x10 + 0x0))
-#define HW_PINCTRL_IRQLEVELn_SET(n)     (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x900+(n)*0x10 + 0x4))
-#define HW_PINCTRL_IRQLEVELn_CLR(n)     (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x900+(n)*0x10 + 0x8))
-#define HW_PINCTRL_IRQLEVELn_TOG(n)     (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x900+(n)*0x10 + 0xc))
-#define BP_PINCTRL_IRQLEVELn_BITS       0
-#define BM_PINCTRL_IRQLEVELn_BITS       0xffffffff
-#define BF_PINCTRL_IRQLEVELn_BITS(v)    (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_PINCTRL_IRQPOLn
- * Address: 0xa00+n*0x10
- * SCT: yes
-*/
-#define HW_PINCTRL_IRQPOLn(n)       (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xa00+(n)*0x10 + 0x0))
-#define HW_PINCTRL_IRQPOLn_SET(n)   (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xa00+(n)*0x10 + 0x4))
-#define HW_PINCTRL_IRQPOLn_CLR(n)   (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xa00+(n)*0x10 + 0x8))
-#define HW_PINCTRL_IRQPOLn_TOG(n)   (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xa00+(n)*0x10 + 0xc))
-#define BP_PINCTRL_IRQPOLn_BITS     0
-#define BM_PINCTRL_IRQPOLn_BITS     0xffffffff
-#define BF_PINCTRL_IRQPOLn_BITS(v)  (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_PINCTRL_IRQSTATn
- * Address: 0xb00+n*0x10
- * SCT: yes
-*/
-#define HW_PINCTRL_IRQSTATn(n)      (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xb00+(n)*0x10 + 0x0))
-#define HW_PINCTRL_IRQSTATn_SET(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xb00+(n)*0x10 + 0x4))
-#define HW_PINCTRL_IRQSTATn_CLR(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xb00+(n)*0x10 + 0x8))
-#define HW_PINCTRL_IRQSTATn_TOG(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xb00+(n)*0x10 + 0xc))
-#define BP_PINCTRL_IRQSTATn_BITS    0
-#define BM_PINCTRL_IRQSTATn_BITS    0xffffffff
-#define BF_PINCTRL_IRQSTATn_BITS(v) (((v) << 0) & 0xffffffff)
-
-#endif /* __HEADERGEN__STMP3700__PINCTRL__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-power.h b/firmware/target/arm/imx233/regs/stmp3700/regs-power.h
deleted file mode 100644
index e61a54103e..0000000000
--- a/firmware/target/arm/imx233/regs/stmp3700/regs-power.h
+++ /dev/null
@@ -1,581 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3700:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__STMP3700__POWER__H__
-#define __HEADERGEN__STMP3700__POWER__H__
-
-#define REGS_POWER_BASE (0x80044000)
-
-#define REGS_POWER_VERSION "3.2.0"
-
-/**
- * Register: HW_POWER_CTRL
- * Address: 0
- * SCT: yes
-*/
-#define HW_POWER_CTRL                               (*(volatile unsigned long *)(REGS_POWER_BASE + 0x0 + 0x0))
-#define HW_POWER_CTRL_SET                           (*(volatile unsigned long *)(REGS_POWER_BASE + 0x0 + 0x4))
-#define HW_POWER_CTRL_CLR                           (*(volatile unsigned long *)(REGS_POWER_BASE + 0x0 + 0x8))
-#define HW_POWER_CTRL_TOG                           (*(volatile unsigned long *)(REGS_POWER_BASE + 0x0 + 0xc))
-#define BP_POWER_CTRL_CLKGATE                       30
-#define BM_POWER_CTRL_CLKGATE                       0x40000000
-#define BF_POWER_CTRL_CLKGATE(v)                    (((v) << 30) & 0x40000000)
-#define BP_POWER_CTRL_PSWITCH_IRQ                   22
-#define BM_POWER_CTRL_PSWITCH_IRQ                   0x400000
-#define BF_POWER_CTRL_PSWITCH_IRQ(v)                (((v) << 22) & 0x400000)
-#define BP_POWER_CTRL_PSWITCH_IRQ_SRC               21
-#define BM_POWER_CTRL_PSWITCH_IRQ_SRC               0x200000
-#define BF_POWER_CTRL_PSWITCH_IRQ_SRC(v)            (((v) << 21) & 0x200000)
-#define BP_POWER_CTRL_POLARITY_PSWITCH              20
-#define BM_POWER_CTRL_POLARITY_PSWITCH              0x100000
-#define BF_POWER_CTRL_POLARITY_PSWITCH(v)           (((v) << 20) & 0x100000)
-#define BP_POWER_CTRL_ENIRQ_PSWITCH                 19
-#define BM_POWER_CTRL_ENIRQ_PSWITCH                 0x80000
-#define BF_POWER_CTRL_ENIRQ_PSWITCH(v)              (((v) << 19) & 0x80000)
-#define BP_POWER_CTRL_POLARITY_LINREG_OK            18
-#define BM_POWER_CTRL_POLARITY_LINREG_OK            0x40000
-#define BF_POWER_CTRL_POLARITY_LINREG_OK(v)         (((v) << 18) & 0x40000)
-#define BP_POWER_CTRL_LINREG_OK_IRQ                 17
-#define BM_POWER_CTRL_LINREG_OK_IRQ                 0x20000
-#define BF_POWER_CTRL_LINREG_OK_IRQ(v)              (((v) << 17) & 0x20000)
-#define BP_POWER_CTRL_ENIRQ_LINREG_OK               16
-#define BM_POWER_CTRL_ENIRQ_LINREG_OK               0x10000
-#define BF_POWER_CTRL_ENIRQ_LINREG_OK(v)            (((v) << 16) & 0x10000)
-#define BP_POWER_CTRL_DC_OK_IRQ                     15
-#define BM_POWER_CTRL_DC_OK_IRQ                     0x8000
-#define BF_POWER_CTRL_DC_OK_IRQ(v)                  (((v) << 15) & 0x8000)
-#define BP_POWER_CTRL_ENIRQ_DC_OK                   14
-#define BM_POWER_CTRL_ENIRQ_DC_OK                   0x4000
-#define BF_POWER_CTRL_ENIRQ_DC_OK(v)                (((v) << 14) & 0x4000)
-#define BP_POWER_CTRL_BATT_BO_IRQ                   13
-#define BM_POWER_CTRL_BATT_BO_IRQ                   0x2000
-#define BF_POWER_CTRL_BATT_BO_IRQ(v)                (((v) << 13) & 0x2000)
-#define BP_POWER_CTRL_ENIRQBATT_BO                  12
-#define BM_POWER_CTRL_ENIRQBATT_BO                  0x1000
-#define BF_POWER_CTRL_ENIRQBATT_BO(v)               (((v) << 12) & 0x1000)
-#define BP_POWER_CTRL_VDDIO_BO_IRQ                  11
-#define BM_POWER_CTRL_VDDIO_BO_IRQ                  0x800
-#define BF_POWER_CTRL_VDDIO_BO_IRQ(v)               (((v) << 11) & 0x800)
-#define BP_POWER_CTRL_ENIRQ_VDDIO_BO                10
-#define BM_POWER_CTRL_ENIRQ_VDDIO_BO                0x400
-#define BF_POWER_CTRL_ENIRQ_VDDIO_BO(v)             (((v) << 10) & 0x400)
-#define BP_POWER_CTRL_VDDA_BO_IRQ                   9
-#define BM_POWER_CTRL_VDDA_BO_IRQ                   0x200
-#define BF_POWER_CTRL_VDDA_BO_IRQ(v)                (((v) << 9) & 0x200)
-#define BP_POWER_CTRL_ENIRQ_VDDA_BO                 8
-#define BM_POWER_CTRL_ENIRQ_VDDA_BO                 0x100
-#define BF_POWER_CTRL_ENIRQ_VDDA_BO(v)              (((v) << 8) & 0x100)
-#define BP_POWER_CTRL_VDDD_BO_IRQ                   7
-#define BM_POWER_CTRL_VDDD_BO_IRQ                   0x80
-#define BF_POWER_CTRL_VDDD_BO_IRQ(v)                (((v) << 7) & 0x80)
-#define BP_POWER_CTRL_ENIRQ_VDDD_BO                 6
-#define BM_POWER_CTRL_ENIRQ_VDDD_BO                 0x40
-#define BF_POWER_CTRL_ENIRQ_VDDD_BO(v)              (((v) << 6) & 0x40)
-#define BP_POWER_CTRL_POLARITY_VBUSVALID            5
-#define BM_POWER_CTRL_POLARITY_VBUSVALID            0x20
-#define BF_POWER_CTRL_POLARITY_VBUSVALID(v)         (((v) << 5) & 0x20)
-#define BP_POWER_CTRL_VBUSVALID_IRQ                 4
-#define BM_POWER_CTRL_VBUSVALID_IRQ                 0x10
-#define BF_POWER_CTRL_VBUSVALID_IRQ(v)              (((v) << 4) & 0x10)
-#define BP_POWER_CTRL_ENIRQ_VBUS_VALID              3
-#define BM_POWER_CTRL_ENIRQ_VBUS_VALID              0x8
-#define BF_POWER_CTRL_ENIRQ_VBUS_VALID(v)           (((v) << 3) & 0x8)
-#define BP_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO       2
-#define BM_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO       0x4
-#define BF_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO(v)    (((v) << 2) & 0x4)
-#define BP_POWER_CTRL_VDD5V_GT_VDDIO_IRQ            1
-#define BM_POWER_CTRL_VDD5V_GT_VDDIO_IRQ            0x2
-#define BF_POWER_CTRL_VDD5V_GT_VDDIO_IRQ(v)         (((v) << 1) & 0x2)
-#define BP_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO          0
-#define BM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO          0x1
-#define BF_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO(v)       (((v) << 0) & 0x1)
-
-/**
- * Register: HW_POWER_5VCTRL
- * Address: 0x10
- * SCT: yes
-*/
-#define HW_POWER_5VCTRL                         (*(volatile unsigned long *)(REGS_POWER_BASE + 0x10 + 0x0))
-#define HW_POWER_5VCTRL_SET                     (*(volatile unsigned long *)(REGS_POWER_BASE + 0x10 + 0x4))
-#define HW_POWER_5VCTRL_CLR                     (*(volatile unsigned long *)(REGS_POWER_BASE + 0x10 + 0x8))
-#define HW_POWER_5VCTRL_TOG                     (*(volatile unsigned long *)(REGS_POWER_BASE + 0x10 + 0xc))
-#define BP_POWER_5VCTRL_VBUSVALID_TRSH          10
-#define BM_POWER_5VCTRL_VBUSVALID_TRSH          0xc00
-#define BF_POWER_5VCTRL_VBUSVALID_TRSH(v)       (((v) << 10) & 0xc00)
-#define BP_POWER_5VCTRL_PWDN_5VBRNOUT           8
-#define BM_POWER_5VCTRL_PWDN_5VBRNOUT           0x100
-#define BF_POWER_5VCTRL_PWDN_5VBRNOUT(v)        (((v) << 8) & 0x100)
-#define BP_POWER_5VCTRL_ENABLE_ILIMIT           7
-#define BM_POWER_5VCTRL_ENABLE_ILIMIT           0x80
-#define BF_POWER_5VCTRL_ENABLE_ILIMIT(v)        (((v) << 7) & 0x80)
-#define BP_POWER_5VCTRL_DCDC_XFER               6
-#define BM_POWER_5VCTRL_DCDC_XFER               0x40
-#define BF_POWER_5VCTRL_DCDC_XFER(v)            (((v) << 6) & 0x40)
-#define BP_POWER_5VCTRL_EN_BATT_PULLDN          5
-#define BM_POWER_5VCTRL_EN_BATT_PULLDN          0x20
-#define BF_POWER_5VCTRL_EN_BATT_PULLDN(v)       (((v) << 5) & 0x20)
-#define BP_POWER_5VCTRL_VBUSVALID_5VDETECT      4
-#define BM_POWER_5VCTRL_VBUSVALID_5VDETECT      0x10
-#define BF_POWER_5VCTRL_VBUSVALID_5VDETECT(v)   (((v) << 4) & 0x10)
-#define BP_POWER_5VCTRL_VBUSVALID_TO_B          3
-#define BM_POWER_5VCTRL_VBUSVALID_TO_B          0x8
-#define BF_POWER_5VCTRL_VBUSVALID_TO_B(v)       (((v) << 3) & 0x8)
-#define BP_POWER_5VCTRL_ILIMIT_EQ_ZERO          2
-#define BM_POWER_5VCTRL_ILIMIT_EQ_ZERO          0x4
-#define BF_POWER_5VCTRL_ILIMIT_EQ_ZERO(v)       (((v) << 2) & 0x4)
-#define BP_POWER_5VCTRL_OTG_PWRUP_CMPS          1
-#define BM_POWER_5VCTRL_OTG_PWRUP_CMPS          0x2
-#define BF_POWER_5VCTRL_OTG_PWRUP_CMPS(v)       (((v) << 1) & 0x2)
-#define BP_POWER_5VCTRL_ENABLE_DCDC             0
-#define BM_POWER_5VCTRL_ENABLE_DCDC             0x1
-#define BF_POWER_5VCTRL_ENABLE_DCDC(v)          (((v) << 0) & 0x1)
-
-/**
- * Register: HW_POWER_MINPWR
- * Address: 0x20
- * SCT: yes
-*/
-#define HW_POWER_MINPWR                     (*(volatile unsigned long *)(REGS_POWER_BASE + 0x20 + 0x0))
-#define HW_POWER_MINPWR_SET                 (*(volatile unsigned long *)(REGS_POWER_BASE + 0x20 + 0x4))
-#define HW_POWER_MINPWR_CLR                 (*(volatile unsigned long *)(REGS_POWER_BASE + 0x20 + 0x8))
-#define HW_POWER_MINPWR_TOG                 (*(volatile unsigned long *)(REGS_POWER_BASE + 0x20 + 0xc))
-#define BP_POWER_MINPWR_PWD_BO              11
-#define BM_POWER_MINPWR_PWD_BO              0x800
-#define BF_POWER_MINPWR_PWD_BO(v)           (((v) << 11) & 0x800)
-#define BP_POWER_MINPWR_USB_I_SUSPEND       10
-#define BM_POWER_MINPWR_USB_I_SUSPEND       0x400
-#define BF_POWER_MINPWR_USB_I_SUSPEND(v)    (((v) << 10) & 0x400)
-#define BP_POWER_MINPWR_ENABLE_OSC          9
-#define BM_POWER_MINPWR_ENABLE_OSC          0x200
-#define BF_POWER_MINPWR_ENABLE_OSC(v)       (((v) << 9) & 0x200)
-#define BP_POWER_MINPWR_SELECT_OSC          8
-#define BM_POWER_MINPWR_SELECT_OSC          0x100
-#define BF_POWER_MINPWR_SELECT_OSC(v)       (((v) << 8) & 0x100)
-#define BP_POWER_MINPWR_VBG_OFF             7
-#define BM_POWER_MINPWR_VBG_OFF             0x80
-#define BF_POWER_MINPWR_VBG_OFF(v)          (((v) << 7) & 0x80)
-#define BP_POWER_MINPWR_DOUBLE_FETS         6
-#define BM_POWER_MINPWR_DOUBLE_FETS         0x40
-#define BF_POWER_MINPWR_DOUBLE_FETS(v)      (((v) << 6) & 0x40)
-#define BP_POWER_MINPWR_HALF_FETS           5
-#define BM_POWER_MINPWR_HALF_FETS           0x20
-#define BF_POWER_MINPWR_HALF_FETS(v)        (((v) << 5) & 0x20)
-#define BP_POWER_MINPWR_LESSANA_I           4
-#define BM_POWER_MINPWR_LESSANA_I           0x10
-#define BF_POWER_MINPWR_LESSANA_I(v)        (((v) << 4) & 0x10)
-#define BP_POWER_MINPWR_PWD_XTAL24          3
-#define BM_POWER_MINPWR_PWD_XTAL24          0x8
-#define BF_POWER_MINPWR_PWD_XTAL24(v)       (((v) << 3) & 0x8)
-#define BP_POWER_MINPWR_DC_STOPCLK          2
-#define BM_POWER_MINPWR_DC_STOPCLK          0x4
-#define BF_POWER_MINPWR_DC_STOPCLK(v)       (((v) << 2) & 0x4)
-#define BP_POWER_MINPWR_EN_DC_PFM           1
-#define BM_POWER_MINPWR_EN_DC_PFM           0x2
-#define BF_POWER_MINPWR_EN_DC_PFM(v)        (((v) << 1) & 0x2)
-#define BP_POWER_MINPWR_DC_HALFCLK          0
-#define BM_POWER_MINPWR_DC_HALFCLK          0x1
-#define BF_POWER_MINPWR_DC_HALFCLK(v)       (((v) << 0) & 0x1)
-
-/**
- * Register: HW_POWER_CHARGE
- * Address: 0x30
- * SCT: yes
-*/
-#define HW_POWER_CHARGE                         (*(volatile unsigned long *)(REGS_POWER_BASE + 0x30 + 0x0))
-#define HW_POWER_CHARGE_SET                     (*(volatile unsigned long *)(REGS_POWER_BASE + 0x30 + 0x4))
-#define HW_POWER_CHARGE_CLR                     (*(volatile unsigned long *)(REGS_POWER_BASE + 0x30 + 0x8))
-#define HW_POWER_CHARGE_TOG                     (*(volatile unsigned long *)(REGS_POWER_BASE + 0x30 + 0xc))
-#define BP_POWER_CHARGE_ENABLE_FAULT_DETECT     20
-#define BM_POWER_CHARGE_ENABLE_FAULT_DETECT     0x100000
-#define BF_POWER_CHARGE_ENABLE_FAULT_DETECT(v)  (((v) << 20) & 0x100000)
-#define BP_POWER_CHARGE_CHRG_STS_OFF            19
-#define BM_POWER_CHARGE_CHRG_STS_OFF            0x80000
-#define BF_POWER_CHARGE_CHRG_STS_OFF(v)         (((v) << 19) & 0x80000)
-#define BP_POWER_CHARGE_USE_EXTERN_R            17
-#define BM_POWER_CHARGE_USE_EXTERN_R            0x20000
-#define BF_POWER_CHARGE_USE_EXTERN_R(v)         (((v) << 17) & 0x20000)
-#define BP_POWER_CHARGE_PWD_BATTCHRG            16
-#define BM_POWER_CHARGE_PWD_BATTCHRG            0x10000
-#define BF_POWER_CHARGE_PWD_BATTCHRG(v)         (((v) << 16) & 0x10000)
-#define BP_POWER_CHARGE_STOP_ILIMIT             8
-#define BM_POWER_CHARGE_STOP_ILIMIT             0xf00
-#define BF_POWER_CHARGE_STOP_ILIMIT(v)          (((v) << 8) & 0xf00)
-#define BP_POWER_CHARGE_BATTCHRG_I              0
-#define BM_POWER_CHARGE_BATTCHRG_I              0x3f
-#define BF_POWER_CHARGE_BATTCHRG_I(v)           (((v) << 0) & 0x3f)
-
-/**
- * Register: HW_POWER_VDDDCTRL
- * Address: 0x40
- * SCT: no
-*/
-#define HW_POWER_VDDDCTRL                       (*(volatile unsigned long *)(REGS_POWER_BASE + 0x40))
-#define BP_POWER_VDDDCTRL_ADJTN                 28
-#define BM_POWER_VDDDCTRL_ADJTN                 0xf0000000
-#define BF_POWER_VDDDCTRL_ADJTN(v)              (((v) << 28) & 0xf0000000)
-#define BP_POWER_VDDDCTRL_ALKALINE_CHARGE       24
-#define BM_POWER_VDDDCTRL_ALKALINE_CHARGE       0x1000000
-#define BF_POWER_VDDDCTRL_ALKALINE_CHARGE(v)    (((v) << 24) & 0x1000000)
-#define BP_POWER_VDDDCTRL_DISABLE_STEPPING      23
-#define BM_POWER_VDDDCTRL_DISABLE_STEPPING      0x800000
-#define BF_POWER_VDDDCTRL_DISABLE_STEPPING(v)   (((v) << 23) & 0x800000)
-#define BP_POWER_VDDDCTRL_LINREG_FROM_BATT      22
-#define BM_POWER_VDDDCTRL_LINREG_FROM_BATT      0x400000
-#define BF_POWER_VDDDCTRL_LINREG_FROM_BATT(v)   (((v) << 22) & 0x400000)
-#define BP_POWER_VDDDCTRL_ENABLE_LINREG         21
-#define BM_POWER_VDDDCTRL_ENABLE_LINREG         0x200000
-#define BF_POWER_VDDDCTRL_ENABLE_LINREG(v)      (((v) << 21) & 0x200000)
-#define BP_POWER_VDDDCTRL_DISABLE_FET           20
-#define BM_POWER_VDDDCTRL_DISABLE_FET           0x100000
-#define BF_POWER_VDDDCTRL_DISABLE_FET(v)        (((v) << 20) & 0x100000)
-#define BP_POWER_VDDDCTRL_LINREG_OFFSET         16
-#define BM_POWER_VDDDCTRL_LINREG_OFFSET         0x30000
-#define BF_POWER_VDDDCTRL_LINREG_OFFSET(v)      (((v) << 16) & 0x30000)
-#define BP_POWER_VDDDCTRL_BO_OFFSET             8
-#define BM_POWER_VDDDCTRL_BO_OFFSET             0x700
-#define BF_POWER_VDDDCTRL_BO_OFFSET(v)          (((v) << 8) & 0x700)
-#define BP_POWER_VDDDCTRL_TRG                   0
-#define BM_POWER_VDDDCTRL_TRG                   0x1f
-#define BF_POWER_VDDDCTRL_TRG(v)                (((v) << 0) & 0x1f)
-
-/**
- * Register: HW_POWER_VDDACTRL
- * Address: 0x50
- * SCT: no
-*/
-#define HW_POWER_VDDACTRL                       (*(volatile unsigned long *)(REGS_POWER_BASE + 0x50))
-#define BP_POWER_VDDACTRL_DISABLE_STEPPING      18
-#define BM_POWER_VDDACTRL_DISABLE_STEPPING      0x40000
-#define BF_POWER_VDDACTRL_DISABLE_STEPPING(v)   (((v) << 18) & 0x40000)
-#define BP_POWER_VDDACTRL_ENABLE_LINREG         17
-#define BM_POWER_VDDACTRL_ENABLE_LINREG         0x20000
-#define BF_POWER_VDDACTRL_ENABLE_LINREG(v)      (((v) << 17) & 0x20000)
-#define BP_POWER_VDDACTRL_DISABLE_FET           16
-#define BM_POWER_VDDACTRL_DISABLE_FET           0x10000
-#define BF_POWER_VDDACTRL_DISABLE_FET(v)        (((v) << 16) & 0x10000)
-#define BP_POWER_VDDACTRL_LINREG_OFFSET         12
-#define BM_POWER_VDDACTRL_LINREG_OFFSET         0x3000
-#define BF_POWER_VDDACTRL_LINREG_OFFSET(v)      (((v) << 12) & 0x3000)
-#define BP_POWER_VDDACTRL_BO_OFFSET             8
-#define BM_POWER_VDDACTRL_BO_OFFSET             0x700
-#define BF_POWER_VDDACTRL_BO_OFFSET(v)          (((v) << 8) & 0x700)
-#define BP_POWER_VDDACTRL_TRG                   0
-#define BM_POWER_VDDACTRL_TRG                   0x1f
-#define BF_POWER_VDDACTRL_TRG(v)                (((v) << 0) & 0x1f)
-
-/**
- * Register: HW_POWER_VDDIOCTRL
- * Address: 0x60
- * SCT: no
-*/
-#define HW_POWER_VDDIOCTRL                      (*(volatile unsigned long *)(REGS_POWER_BASE + 0x60))
-#define BP_POWER_VDDIOCTRL_ADJTN                16
-#define BM_POWER_VDDIOCTRL_ADJTN                0xf0000
-#define BF_POWER_VDDIOCTRL_ADJTN(v)             (((v) << 16) & 0xf0000)
-#define BP_POWER_VDDIOCTRL_DISABLE_STEPPING     15
-#define BM_POWER_VDDIOCTRL_DISABLE_STEPPING     0x8000
-#define BF_POWER_VDDIOCTRL_DISABLE_STEPPING(v)  (((v) << 15) & 0x8000)
-#define BP_POWER_VDDIOCTRL_DISABLE_FET          14
-#define BM_POWER_VDDIOCTRL_DISABLE_FET          0x4000
-#define BF_POWER_VDDIOCTRL_DISABLE_FET(v)       (((v) << 14) & 0x4000)
-#define BP_POWER_VDDIOCTRL_LINREG_OFFSET        12
-#define BM_POWER_VDDIOCTRL_LINREG_OFFSET        0x3000
-#define BF_POWER_VDDIOCTRL_LINREG_OFFSET(v)     (((v) << 12) & 0x3000)
-#define BP_POWER_VDDIOCTRL_BO_OFFSET            8
-#define BM_POWER_VDDIOCTRL_BO_OFFSET            0x700
-#define BF_POWER_VDDIOCTRL_BO_OFFSET(v)         (((v) << 8) & 0x700)
-#define BP_POWER_VDDIOCTRL_TRG                  0
-#define BM_POWER_VDDIOCTRL_TRG                  0x1f
-#define BF_POWER_VDDIOCTRL_TRG(v)               (((v) << 0) & 0x1f)
-
-/**
- * Register: HW_POWER_DCFUNCV
- * Address: 0x70
- * SCT: no
-*/
-#define HW_POWER_DCFUNCV            (*(volatile unsigned long *)(REGS_POWER_BASE + 0x70))
-#define BP_POWER_DCFUNCV_VDDD       16
-#define BM_POWER_DCFUNCV_VDDD       0x3ff0000
-#define BF_POWER_DCFUNCV_VDDD(v)    (((v) << 16) & 0x3ff0000)
-#define BP_POWER_DCFUNCV_VDDIO      0
-#define BM_POWER_DCFUNCV_VDDIO      0x3ff
-#define BF_POWER_DCFUNCV_VDDIO(v)   (((v) << 0) & 0x3ff)
-
-/**
- * Register: HW_POWER_MISC
- * Address: 0x80
- * SCT: no
-*/
-#define HW_POWER_MISC                       (*(volatile unsigned long *)(REGS_POWER_BASE + 0x80))
-#define BP_POWER_MISC_FREQSEL               4
-#define BM_POWER_MISC_FREQSEL               0x30
-#define BF_POWER_MISC_FREQSEL(v)            (((v) << 4) & 0x30)
-#define BP_POWER_MISC_DELAY_TIMING          3
-#define BM_POWER_MISC_DELAY_TIMING          0x8
-#define BF_POWER_MISC_DELAY_TIMING(v)       (((v) << 3) & 0x8)
-#define BP_POWER_MISC_TEST                  2
-#define BM_POWER_MISC_TEST                  0x4
-#define BF_POWER_MISC_TEST(v)               (((v) << 2) & 0x4)
-#define BP_POWER_MISC_SEL_PLLCLK            1
-#define BM_POWER_MISC_SEL_PLLCLK            0x2
-#define BF_POWER_MISC_SEL_PLLCLK(v)         (((v) << 1) & 0x2)
-#define BP_POWER_MISC_PERIPHERALSWOFF       0
-#define BM_POWER_MISC_PERIPHERALSWOFF       0x1
-#define BF_POWER_MISC_PERIPHERALSWOFF(v)    (((v) << 0) & 0x1)
-
-/**
- * Register: HW_POWER_DCLIMITS
- * Address: 0x90
- * SCT: no
-*/
-#define HW_POWER_DCLIMITS                   (*(volatile unsigned long *)(REGS_POWER_BASE + 0x90))
-#define BP_POWER_DCLIMITS_POSLIMIT_BOOST    16
-#define BM_POWER_DCLIMITS_POSLIMIT_BOOST    0x7f0000
-#define BF_POWER_DCLIMITS_POSLIMIT_BOOST(v) (((v) << 16) & 0x7f0000)
-#define BP_POWER_DCLIMITS_POSLIMIT_BUCK     8
-#define BM_POWER_DCLIMITS_POSLIMIT_BUCK     0x7f00
-#define BF_POWER_DCLIMITS_POSLIMIT_BUCK(v)  (((v) << 8) & 0x7f00)
-#define BP_POWER_DCLIMITS_NEGLIMIT          0
-#define BM_POWER_DCLIMITS_NEGLIMIT          0x7f
-#define BF_POWER_DCLIMITS_NEGLIMIT(v)       (((v) << 0) & 0x7f)
-
-/**
- * Register: HW_POWER_LOOPCTRL
- * Address: 0xa0
- * SCT: yes
-*/
-#define HW_POWER_LOOPCTRL                   (*(volatile unsigned long *)(REGS_POWER_BASE + 0xa0 + 0x0))
-#define HW_POWER_LOOPCTRL_SET               (*(volatile unsigned long *)(REGS_POWER_BASE + 0xa0 + 0x4))
-#define HW_POWER_LOOPCTRL_CLR               (*(volatile unsigned long *)(REGS_POWER_BASE + 0xa0 + 0x8))
-#define HW_POWER_LOOPCTRL_TOG               (*(volatile unsigned long *)(REGS_POWER_BASE + 0xa0 + 0xc))
-#define BP_POWER_LOOPCTRL_TOGGLE_DIF        20
-#define BM_POWER_LOOPCTRL_TOGGLE_DIF        0x100000
-#define BF_POWER_LOOPCTRL_TOGGLE_DIF(v)     (((v) << 20) & 0x100000)
-#define BP_POWER_LOOPCTRL_HYST_SIGN         19
-#define BM_POWER_LOOPCTRL_HYST_SIGN         0x80000
-#define BF_POWER_LOOPCTRL_HYST_SIGN(v)      (((v) << 19) & 0x80000)
-#define BP_POWER_LOOPCTRL_EN_CM_HYST        18
-#define BM_POWER_LOOPCTRL_EN_CM_HYST        0x40000
-#define BF_POWER_LOOPCTRL_EN_CM_HYST(v)     (((v) << 18) & 0x40000)
-#define BP_POWER_LOOPCTRL_EN_DF_HYST        17
-#define BM_POWER_LOOPCTRL_EN_DF_HYST        0x20000
-#define BF_POWER_LOOPCTRL_EN_DF_HYST(v)     (((v) << 17) & 0x20000)
-#define BP_POWER_LOOPCTRL_CM_HYST_THRESH    16
-#define BM_POWER_LOOPCTRL_CM_HYST_THRESH    0x10000
-#define BF_POWER_LOOPCTRL_CM_HYST_THRESH(v) (((v) << 16) & 0x10000)
-#define BP_POWER_LOOPCTRL_DF_HYST_THRESH    15
-#define BM_POWER_LOOPCTRL_DF_HYST_THRESH    0x8000
-#define BF_POWER_LOOPCTRL_DF_HYST_THRESH(v) (((v) << 15) & 0x8000)
-#define BP_POWER_LOOPCTRL_RCSCALE_THRESH    14
-#define BM_POWER_LOOPCTRL_RCSCALE_THRESH    0x4000
-#define BF_POWER_LOOPCTRL_RCSCALE_THRESH(v) (((v) << 14) & 0x4000)
-#define BP_POWER_LOOPCTRL_EN_RCSCALE        12
-#define BM_POWER_LOOPCTRL_EN_RCSCALE        0x3000
-#define BF_POWER_LOOPCTRL_EN_RCSCALE(v)     (((v) << 12) & 0x3000)
-#define BP_POWER_LOOPCTRL_DC_FF             8
-#define BM_POWER_LOOPCTRL_DC_FF             0x700
-#define BF_POWER_LOOPCTRL_DC_FF(v)          (((v) << 8) & 0x700)
-#define BP_POWER_LOOPCTRL_DC_R              4
-#define BM_POWER_LOOPCTRL_DC_R              0xf0
-#define BF_POWER_LOOPCTRL_DC_R(v)           (((v) << 4) & 0xf0)
-#define BP_POWER_LOOPCTRL_DC_C              0
-#define BM_POWER_LOOPCTRL_DC_C              0x3
-#define BF_POWER_LOOPCTRL_DC_C(v)           (((v) << 0) & 0x3)
-
-/**
- * Register: HW_POWER_STS
- * Address: 0xb0
- * SCT: no
-*/
-#define HW_POWER_STS                        (*(volatile unsigned long *)(REGS_POWER_BASE + 0xb0))
-#define BP_POWER_STS_BATT_CHRG_PRESENT      31
-#define BM_POWER_STS_BATT_CHRG_PRESENT      0x80000000
-#define BF_POWER_STS_BATT_CHRG_PRESENT(v)   (((v) << 31) & 0x80000000)
-#define BP_POWER_STS_PSWITCH                18
-#define BM_POWER_STS_PSWITCH                0xc0000
-#define BF_POWER_STS_PSWITCH(v)             (((v) << 18) & 0xc0000)
-#define BP_POWER_STS_AVALID_STATUS          17
-#define BM_POWER_STS_AVALID_STATUS          0x20000
-#define BF_POWER_STS_AVALID_STATUS(v)       (((v) << 17) & 0x20000)
-#define BP_POWER_STS_BVALID_STATUS          16
-#define BM_POWER_STS_BVALID_STATUS          0x10000
-#define BF_POWER_STS_BVALID_STATUS(v)       (((v) << 16) & 0x10000)
-#define BP_POWER_STS_VBUSVALID_STATUS       15
-#define BM_POWER_STS_VBUSVALID_STATUS       0x8000
-#define BF_POWER_STS_VBUSVALID_STATUS(v)    (((v) << 15) & 0x8000)
-#define BP_POWER_STS_SESSEND_STATUS         14
-#define BM_POWER_STS_SESSEND_STATUS         0x4000
-#define BF_POWER_STS_SESSEND_STATUS(v)      (((v) << 14) & 0x4000)
-#define BP_POWER_STS_MODE                   13
-#define BM_POWER_STS_MODE                   0x2000
-#define BF_POWER_STS_MODE(v)                (((v) << 13) & 0x2000)
-#define BP_POWER_STS_BATT_BO                12
-#define BM_POWER_STS_BATT_BO                0x1000
-#define BF_POWER_STS_BATT_BO(v)             (((v) << 12) & 0x1000)
-#define BP_POWER_STS_VDD5V_FAULT            11
-#define BM_POWER_STS_VDD5V_FAULT            0x800
-#define BF_POWER_STS_VDD5V_FAULT(v)         (((v) << 11) & 0x800)
-#define BP_POWER_STS_CHRGSTS                10
-#define BM_POWER_STS_CHRGSTS                0x400
-#define BF_POWER_STS_CHRGSTS(v)             (((v) << 10) & 0x400)
-#define BP_POWER_STS_LINREG_OK              9
-#define BM_POWER_STS_LINREG_OK              0x200
-#define BF_POWER_STS_LINREG_OK(v)           (((v) << 9) & 0x200)
-#define BP_POWER_STS_DC_OK                  8
-#define BM_POWER_STS_DC_OK                  0x100
-#define BF_POWER_STS_DC_OK(v)               (((v) << 8) & 0x100)
-#define BP_POWER_STS_VDDIO_BO               7
-#define BM_POWER_STS_VDDIO_BO               0x80
-#define BF_POWER_STS_VDDIO_BO(v)            (((v) << 7) & 0x80)
-#define BP_POWER_STS_VDDA_BO                6
-#define BM_POWER_STS_VDDA_BO                0x40
-#define BF_POWER_STS_VDDA_BO(v)             (((v) << 6) & 0x40)
-#define BP_POWER_STS_VDDD_BO                5
-#define BM_POWER_STS_VDDD_BO                0x20
-#define BF_POWER_STS_VDDD_BO(v)             (((v) << 5) & 0x20)
-#define BP_POWER_STS_VDD5V_GT_VDDIO         4
-#define BM_POWER_STS_VDD5V_GT_VDDIO         0x10
-#define BF_POWER_STS_VDD5V_GT_VDDIO(v)      (((v) << 4) & 0x10)
-#define BP_POWER_STS_AVALID                 3
-#define BM_POWER_STS_AVALID                 0x8
-#define BF_POWER_STS_AVALID(v)              (((v) << 3) & 0x8)
-#define BP_POWER_STS_BVALID                 2
-#define BM_POWER_STS_BVALID                 0x4
-#define BF_POWER_STS_BVALID(v)              (((v) << 2) & 0x4)
-#define BP_POWER_STS_VBUSVALID              1
-#define BM_POWER_STS_VBUSVALID              0x2
-#define BF_POWER_STS_VBUSVALID(v)           (((v) << 1) & 0x2)
-#define BP_POWER_STS_SESSEND                0
-#define BM_POWER_STS_SESSEND                0x1
-#define BF_POWER_STS_SESSEND(v)             (((v) << 0) & 0x1)
-
-/**
- * Register: HW_POWER_SPEED
- * Address: 0xc0
- * SCT: yes
-*/
-#define HW_POWER_SPEED              (*(volatile unsigned long *)(REGS_POWER_BASE + 0xc0 + 0x0))
-#define HW_POWER_SPEED_SET          (*(volatile unsigned long *)(REGS_POWER_BASE + 0xc0 + 0x4))
-#define HW_POWER_SPEED_CLR          (*(volatile unsigned long *)(REGS_POWER_BASE + 0xc0 + 0x8))
-#define HW_POWER_SPEED_TOG          (*(volatile unsigned long *)(REGS_POWER_BASE + 0xc0 + 0xc))
-#define BP_POWER_SPEED_STATUS       16
-#define BM_POWER_SPEED_STATUS       0xff0000
-#define BF_POWER_SPEED_STATUS(v)    (((v) << 16) & 0xff0000)
-#define BP_POWER_SPEED_CTRL         0
-#define BM_POWER_SPEED_CTRL         0x3
-#define BF_POWER_SPEED_CTRL(v)      (((v) << 0) & 0x3)
-
-/**
- * Register: HW_POWER_BATTMONITOR
- * Address: 0xd0
- * SCT: no
-*/
-#define HW_POWER_BATTMONITOR                    (*(volatile unsigned long *)(REGS_POWER_BASE + 0xd0))
-#define BP_POWER_BATTMONITOR_BATT_VAL           16
-#define BM_POWER_BATTMONITOR_BATT_VAL           0x3ff0000
-#define BF_POWER_BATTMONITOR_BATT_VAL(v)        (((v) << 16) & 0x3ff0000)
-#define BP_POWER_BATTMONITOR_EN_BATADJ          6
-#define BM_POWER_BATTMONITOR_EN_BATADJ          0x40
-#define BF_POWER_BATTMONITOR_EN_BATADJ(v)       (((v) << 6) & 0x40)
-#define BP_POWER_BATTMONITOR_PWDN_BATTBRNOUT    5
-#define BM_POWER_BATTMONITOR_PWDN_BATTBRNOUT    0x20
-#define BF_POWER_BATTMONITOR_PWDN_BATTBRNOUT(v) (((v) << 5) & 0x20)
-#define BP_POWER_BATTMONITOR_BRWNOUT_PWD        4
-#define BM_POWER_BATTMONITOR_BRWNOUT_PWD        0x10
-#define BF_POWER_BATTMONITOR_BRWNOUT_PWD(v)     (((v) << 4) & 0x10)
-#define BP_POWER_BATTMONITOR_BRWNOUT_LVL        0
-#define BM_POWER_BATTMONITOR_BRWNOUT_LVL        0xf
-#define BF_POWER_BATTMONITOR_BRWNOUT_LVL(v)     (((v) << 0) & 0xf)
-
-/**
- * Register: HW_POWER_RESET
- * Address: 0xe0
- * SCT: yes
-*/
-#define HW_POWER_RESET              (*(volatile unsigned long *)(REGS_POWER_BASE + 0xe0 + 0x0))
-#define HW_POWER_RESET_SET          (*(volatile unsigned long *)(REGS_POWER_BASE + 0xe0 + 0x4))
-#define HW_POWER_RESET_CLR          (*(volatile unsigned long *)(REGS_POWER_BASE + 0xe0 + 0x8))
-#define HW_POWER_RESET_TOG          (*(volatile unsigned long *)(REGS_POWER_BASE + 0xe0 + 0xc))
-#define BP_POWER_RESET_UNLOCK       16
-#define BM_POWER_RESET_UNLOCK       0xffff0000
-#define BV_POWER_RESET_UNLOCK__KEY  0x3e77
-#define BF_POWER_RESET_UNLOCK(v)    (((v) << 16) & 0xffff0000)
-#define BF_POWER_RESET_UNLOCK_V(v)  ((BV_POWER_RESET_UNLOCK__##v << 16) & 0xffff0000)
-#define BP_POWER_RESET_PWD_OFF      1
-#define BM_POWER_RESET_PWD_OFF      0x2
-#define BF_POWER_RESET_PWD_OFF(v)   (((v) << 1) & 0x2)
-#define BP_POWER_RESET_PWD          0
-#define BM_POWER_RESET_PWD          0x1
-#define BF_POWER_RESET_PWD(v)       (((v) << 0) & 0x1)
-
-/**
- * Register: HW_POWER_DEBUG
- * Address: 0xf0
- * SCT: yes
-*/
-#define HW_POWER_DEBUG                      (*(volatile unsigned long *)(REGS_POWER_BASE + 0xf0 + 0x0))
-#define HW_POWER_DEBUG_SET                  (*(volatile unsigned long *)(REGS_POWER_BASE + 0xf0 + 0x4))
-#define HW_POWER_DEBUG_CLR                  (*(volatile unsigned long *)(REGS_POWER_BASE + 0xf0 + 0x8))
-#define HW_POWER_DEBUG_TOG                  (*(volatile unsigned long *)(REGS_POWER_BASE + 0xf0 + 0xc))
-#define BP_POWER_DEBUG_VBUSVALIDPIOLOCK     3
-#define BM_POWER_DEBUG_VBUSVALIDPIOLOCK     0x8
-#define BF_POWER_DEBUG_VBUSVALIDPIOLOCK(v)  (((v) << 3) & 0x8)
-#define BP_POWER_DEBUG_AVALIDPIOLOCK        2
-#define BM_POWER_DEBUG_AVALIDPIOLOCK        0x4
-#define BF_POWER_DEBUG_AVALIDPIOLOCK(v)     (((v) << 2) & 0x4)
-#define BP_POWER_DEBUG_BVALIDPIOLOCK        1
-#define BM_POWER_DEBUG_BVALIDPIOLOCK        0x2
-#define BF_POWER_DEBUG_BVALIDPIOLOCK(v)     (((v) << 1) & 0x2)
-#define BP_POWER_DEBUG_SESSENDPIOLOCK       0
-#define BM_POWER_DEBUG_SESSENDPIOLOCK       0x1
-#define BF_POWER_DEBUG_SESSENDPIOLOCK(v)    (((v) << 0) & 0x1)
-
-/**
- * Register: HW_POWER_SPECIAL
- * Address: 0x100
- * SCT: yes
-*/
-#define HW_POWER_SPECIAL            (*(volatile unsigned long *)(REGS_POWER_BASE + 0x100 + 0x0))
-#define HW_POWER_SPECIAL_SET        (*(volatile unsigned long *)(REGS_POWER_BASE + 0x100 + 0x4))
-#define HW_POWER_SPECIAL_CLR        (*(volatile unsigned long *)(REGS_POWER_BASE + 0x100 + 0x8))
-#define HW_POWER_SPECIAL_TOG        (*(volatile unsigned long *)(REGS_POWER_BASE + 0x100 + 0xc))
-#define BP_POWER_SPECIAL_TEST       0
-#define BM_POWER_SPECIAL_TEST       0xffffffff
-#define BF_POWER_SPECIAL_TEST(v)    (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_POWER_VERSION
- * Address: 0x110
- * SCT: no
-*/
-#define HW_POWER_VERSION            (*(volatile unsigned long *)(REGS_POWER_BASE + 0x110))
-#define BP_POWER_VERSION_MAJOR      24
-#define BM_POWER_VERSION_MAJOR      0xff000000
-#define BF_POWER_VERSION_MAJOR(v)   (((v) << 24) & 0xff000000)
-#define BP_POWER_VERSION_MINOR      16
-#define BM_POWER_VERSION_MINOR      0xff0000
-#define BF_POWER_VERSION_MINOR(v)   (((v) << 16) & 0xff0000)
-#define BP_POWER_VERSION_STEP       0
-#define BM_POWER_VERSION_STEP       0xffff
-#define BF_POWER_VERSION_STEP(v)    (((v) << 0) & 0xffff)
-
-#endif /* __HEADERGEN__STMP3700__POWER__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-pwm.h b/firmware/target/arm/imx233/regs/stmp3700/regs-pwm.h
deleted file mode 100644
index 417d133bbc..0000000000
--- a/firmware/target/arm/imx233/regs/stmp3700/regs-pwm.h
+++ /dev/null
@@ -1,153 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3700:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__STMP3700__PWM__H__
-#define __HEADERGEN__STMP3700__PWM__H__
-
-#define REGS_PWM_BASE (0x80064000)
-
-#define REGS_PWM_VERSION "3.2.0"
-
-/**
- * Register: HW_PWM_CTRL
- * Address: 0
- * SCT: yes
-*/
-#define HW_PWM_CTRL                         (*(volatile unsigned long *)(REGS_PWM_BASE + 0x0 + 0x0))
-#define HW_PWM_CTRL_SET                     (*(volatile unsigned long *)(REGS_PWM_BASE + 0x0 + 0x4))
-#define HW_PWM_CTRL_CLR                     (*(volatile unsigned long *)(REGS_PWM_BASE + 0x0 + 0x8))
-#define HW_PWM_CTRL_TOG                     (*(volatile unsigned long *)(REGS_PWM_BASE + 0x0 + 0xc))
-#define BP_PWM_CTRL_SFTRST                  31
-#define BM_PWM_CTRL_SFTRST                  0x80000000
-#define BF_PWM_CTRL_SFTRST(v)               (((v) << 31) & 0x80000000)
-#define BP_PWM_CTRL_CLKGATE                 30
-#define BM_PWM_CTRL_CLKGATE                 0x40000000
-#define BF_PWM_CTRL_CLKGATE(v)              (((v) << 30) & 0x40000000)
-#define BP_PWM_CTRL_PWM4_PRESENT            29
-#define BM_PWM_CTRL_PWM4_PRESENT            0x20000000
-#define BF_PWM_CTRL_PWM4_PRESENT(v)         (((v) << 29) & 0x20000000)
-#define BP_PWM_CTRL_PWM3_PRESENT            28
-#define BM_PWM_CTRL_PWM3_PRESENT            0x10000000
-#define BF_PWM_CTRL_PWM3_PRESENT(v)         (((v) << 28) & 0x10000000)
-#define BP_PWM_CTRL_PWM2_PRESENT            27
-#define BM_PWM_CTRL_PWM2_PRESENT            0x8000000
-#define BF_PWM_CTRL_PWM2_PRESENT(v)         (((v) << 27) & 0x8000000)
-#define BP_PWM_CTRL_PWM1_PRESENT            26
-#define BM_PWM_CTRL_PWM1_PRESENT            0x4000000
-#define BF_PWM_CTRL_PWM1_PRESENT(v)         (((v) << 26) & 0x4000000)
-#define BP_PWM_CTRL_PWM0_PRESENT            25
-#define BM_PWM_CTRL_PWM0_PRESENT            0x2000000
-#define BF_PWM_CTRL_PWM0_PRESENT(v)         (((v) << 25) & 0x2000000)
-#define BP_PWM_CTRL_PWM2_ANA_CTRL_ENABLE    5
-#define BM_PWM_CTRL_PWM2_ANA_CTRL_ENABLE    0x20
-#define BF_PWM_CTRL_PWM2_ANA_CTRL_ENABLE(v) (((v) << 5) & 0x20)
-#define BP_PWM_CTRL_PWM4_ENABLE             4
-#define BM_PWM_CTRL_PWM4_ENABLE             0x10
-#define BF_PWM_CTRL_PWM4_ENABLE(v)          (((v) << 4) & 0x10)
-#define BP_PWM_CTRL_PWM3_ENABLE             3
-#define BM_PWM_CTRL_PWM3_ENABLE             0x8
-#define BF_PWM_CTRL_PWM3_ENABLE(v)          (((v) << 3) & 0x8)
-#define BP_PWM_CTRL_PWM2_ENABLE             2
-#define BM_PWM_CTRL_PWM2_ENABLE             0x4
-#define BF_PWM_CTRL_PWM2_ENABLE(v)          (((v) << 2) & 0x4)
-#define BP_PWM_CTRL_PWM1_ENABLE             1
-#define BM_PWM_CTRL_PWM1_ENABLE             0x2
-#define BF_PWM_CTRL_PWM1_ENABLE(v)          (((v) << 1) & 0x2)
-#define BP_PWM_CTRL_PWM0_ENABLE             0
-#define BM_PWM_CTRL_PWM0_ENABLE             0x1
-#define BF_PWM_CTRL_PWM0_ENABLE(v)          (((v) << 0) & 0x1)
-
-/**
- * Register: HW_PWM_ACTIVEn
- * Address: 0x10+n*0x20
- * SCT: yes
-*/
-#define HW_PWM_ACTIVEn(n)           (*(volatile unsigned long *)(REGS_PWM_BASE + 0x10+(n)*0x20 + 0x0))
-#define HW_PWM_ACTIVEn_SET(n)       (*(volatile unsigned long *)(REGS_PWM_BASE + 0x10+(n)*0x20 + 0x4))
-#define HW_PWM_ACTIVEn_CLR(n)       (*(volatile unsigned long *)(REGS_PWM_BASE + 0x10+(n)*0x20 + 0x8))
-#define HW_PWM_ACTIVEn_TOG(n)       (*(volatile unsigned long *)(REGS_PWM_BASE + 0x10+(n)*0x20 + 0xc))
-#define BP_PWM_ACTIVEn_INACTIVE     16
-#define BM_PWM_ACTIVEn_INACTIVE     0xffff0000
-#define BF_PWM_ACTIVEn_INACTIVE(v)  (((v) << 16) & 0xffff0000)
-#define BP_PWM_ACTIVEn_ACTIVE       0
-#define BM_PWM_ACTIVEn_ACTIVE       0xffff
-#define BF_PWM_ACTIVEn_ACTIVE(v)    (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_PWM_PERIODn
- * Address: 0x20+n*0x20
- * SCT: yes
-*/
-#define HW_PWM_PERIODn(n)                   (*(volatile unsigned long *)(REGS_PWM_BASE + 0x20+(n)*0x20 + 0x0))
-#define HW_PWM_PERIODn_SET(n)               (*(volatile unsigned long *)(REGS_PWM_BASE + 0x20+(n)*0x20 + 0x4))
-#define HW_PWM_PERIODn_CLR(n)               (*(volatile unsigned long *)(REGS_PWM_BASE + 0x20+(n)*0x20 + 0x8))
-#define HW_PWM_PERIODn_TOG(n)               (*(volatile unsigned long *)(REGS_PWM_BASE + 0x20+(n)*0x20 + 0xc))
-#define BP_PWM_PERIODn_MATT                 23
-#define BM_PWM_PERIODn_MATT                 0x800000
-#define BF_PWM_PERIODn_MATT(v)              (((v) << 23) & 0x800000)
-#define BP_PWM_PERIODn_CDIV                 20
-#define BM_PWM_PERIODn_CDIV                 0x700000
-#define BV_PWM_PERIODn_CDIV__DIV_1          0x0
-#define BV_PWM_PERIODn_CDIV__DIV_2          0x1
-#define BV_PWM_PERIODn_CDIV__DIV_4          0x2
-#define BV_PWM_PERIODn_CDIV__DIV_8          0x3
-#define BV_PWM_PERIODn_CDIV__DIV_16         0x4
-#define BV_PWM_PERIODn_CDIV__DIV_64         0x5
-#define BV_PWM_PERIODn_CDIV__DIV_256        0x6
-#define BV_PWM_PERIODn_CDIV__DIV_1024       0x7
-#define BF_PWM_PERIODn_CDIV(v)              (((v) << 20) & 0x700000)
-#define BF_PWM_PERIODn_CDIV_V(v)            ((BV_PWM_PERIODn_CDIV__##v << 20) & 0x700000)
-#define BP_PWM_PERIODn_INACTIVE_STATE       18
-#define BM_PWM_PERIODn_INACTIVE_STATE       0xc0000
-#define BV_PWM_PERIODn_INACTIVE_STATE__HI_Z 0x0
-#define BV_PWM_PERIODn_INACTIVE_STATE__0    0x2
-#define BV_PWM_PERIODn_INACTIVE_STATE__1    0x3
-#define BF_PWM_PERIODn_INACTIVE_STATE(v)    (((v) << 18) & 0xc0000)
-#define BF_PWM_PERIODn_INACTIVE_STATE_V(v)  ((BV_PWM_PERIODn_INACTIVE_STATE__##v << 18) & 0xc0000)
-#define BP_PWM_PERIODn_ACTIVE_STATE         16
-#define BM_PWM_PERIODn_ACTIVE_STATE         0x30000
-#define BV_PWM_PERIODn_ACTIVE_STATE__HI_Z   0x0
-#define BV_PWM_PERIODn_ACTIVE_STATE__0      0x2
-#define BV_PWM_PERIODn_ACTIVE_STATE__1      0x3
-#define BF_PWM_PERIODn_ACTIVE_STATE(v)      (((v) << 16) & 0x30000)
-#define BF_PWM_PERIODn_ACTIVE_STATE_V(v)    ((BV_PWM_PERIODn_ACTIVE_STATE__##v << 16) & 0x30000)
-#define BP_PWM_PERIODn_PERIOD               0
-#define BM_PWM_PERIODn_PERIOD               0xffff
-#define BF_PWM_PERIODn_PERIOD(v)            (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_PWM_VERSION
- * Address: 0xb0
- * SCT: no
-*/
-#define HW_PWM_VERSION          (*(volatile unsigned long *)(REGS_PWM_BASE + 0xb0))
-#define BP_PWM_VERSION_MAJOR    24
-#define BM_PWM_VERSION_MAJOR    0xff000000
-#define BF_PWM_VERSION_MAJOR(v) (((v) << 24) & 0xff000000)
-#define BP_PWM_VERSION_MINOR    16
-#define BM_PWM_VERSION_MINOR    0xff0000
-#define BF_PWM_VERSION_MINOR(v) (((v) << 16) & 0xff0000)
-#define BP_PWM_VERSION_STEP     0
-#define BM_PWM_VERSION_STEP     0xffff
-#define BF_PWM_VERSION_STEP(v)  (((v) << 0) & 0xffff)
-
-#endif /* __HEADERGEN__STMP3700__PWM__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-rtc.h b/firmware/target/arm/imx233/regs/stmp3700/regs-rtc.h
deleted file mode 100644
index b8757e5823..0000000000
--- a/firmware/target/arm/imx233/regs/stmp3700/regs-rtc.h
+++ /dev/null
@@ -1,312 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3700:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__STMP3700__RTC__H__
-#define __HEADERGEN__STMP3700__RTC__H__
-
-#define REGS_RTC_BASE (0x8005c000)
-
-#define REGS_RTC_VERSION "3.2.0"
-
-/**
- * Register: HW_RTC_CTRL
- * Address: 0
- * SCT: yes
-*/
-#define HW_RTC_CTRL                         (*(volatile unsigned long *)(REGS_RTC_BASE + 0x0 + 0x0))
-#define HW_RTC_CTRL_SET                     (*(volatile unsigned long *)(REGS_RTC_BASE + 0x0 + 0x4))
-#define HW_RTC_CTRL_CLR                     (*(volatile unsigned long *)(REGS_RTC_BASE + 0x0 + 0x8))
-#define HW_RTC_CTRL_TOG                     (*(volatile unsigned long *)(REGS_RTC_BASE + 0x0 + 0xc))
-#define BP_RTC_CTRL_SFTRST                  31
-#define BM_RTC_CTRL_SFTRST                  0x80000000
-#define BF_RTC_CTRL_SFTRST(v)               (((v) << 31) & 0x80000000)
-#define BP_RTC_CTRL_CLKGATE                 30
-#define BM_RTC_CTRL_CLKGATE                 0x40000000
-#define BF_RTC_CTRL_CLKGATE(v)              (((v) << 30) & 0x40000000)
-#define BP_RTC_CTRL_SUPPRESS_COPY2ANALOG    6
-#define BM_RTC_CTRL_SUPPRESS_COPY2ANALOG    0x40
-#define BF_RTC_CTRL_SUPPRESS_COPY2ANALOG(v) (((v) << 6) & 0x40)
-#define BP_RTC_CTRL_FORCE_UPDATE            5
-#define BM_RTC_CTRL_FORCE_UPDATE            0x20
-#define BF_RTC_CTRL_FORCE_UPDATE(v)         (((v) << 5) & 0x20)
-#define BP_RTC_CTRL_WATCHDOGEN              4
-#define BM_RTC_CTRL_WATCHDOGEN              0x10
-#define BF_RTC_CTRL_WATCHDOGEN(v)           (((v) << 4) & 0x10)
-#define BP_RTC_CTRL_ONEMSEC_IRQ             3
-#define BM_RTC_CTRL_ONEMSEC_IRQ             0x8
-#define BF_RTC_CTRL_ONEMSEC_IRQ(v)          (((v) << 3) & 0x8)
-#define BP_RTC_CTRL_ALARM_IRQ               2
-#define BM_RTC_CTRL_ALARM_IRQ               0x4
-#define BF_RTC_CTRL_ALARM_IRQ(v)            (((v) << 2) & 0x4)
-#define BP_RTC_CTRL_ONEMSEC_IRQ_EN          1
-#define BM_RTC_CTRL_ONEMSEC_IRQ_EN          0x2
-#define BF_RTC_CTRL_ONEMSEC_IRQ_EN(v)       (((v) << 1) & 0x2)
-#define BP_RTC_CTRL_ALARM_IRQ_EN            0
-#define BM_RTC_CTRL_ALARM_IRQ_EN            0x1
-#define BF_RTC_CTRL_ALARM_IRQ_EN(v)         (((v) << 0) & 0x1)
-
-/**
- * Register: HW_RTC_STAT
- * Address: 0x10
- * SCT: no
-*/
-#define HW_RTC_STAT                         (*(volatile unsigned long *)(REGS_RTC_BASE + 0x10))
-#define BP_RTC_STAT_RTC_PRESENT             31
-#define BM_RTC_STAT_RTC_PRESENT             0x80000000
-#define BF_RTC_STAT_RTC_PRESENT(v)          (((v) << 31) & 0x80000000)
-#define BP_RTC_STAT_ALARM_PRESENT           30
-#define BM_RTC_STAT_ALARM_PRESENT           0x40000000
-#define BF_RTC_STAT_ALARM_PRESENT(v)        (((v) << 30) & 0x40000000)
-#define BP_RTC_STAT_WATCHDOG_PRESENT        29
-#define BM_RTC_STAT_WATCHDOG_PRESENT        0x20000000
-#define BF_RTC_STAT_WATCHDOG_PRESENT(v)     (((v) << 29) & 0x20000000)
-#define BP_RTC_STAT_XTAL32000_PRESENT       28
-#define BM_RTC_STAT_XTAL32000_PRESENT       0x10000000
-#define BF_RTC_STAT_XTAL32000_PRESENT(v)    (((v) << 28) & 0x10000000)
-#define BP_RTC_STAT_XTAL32768_PRESENT       27
-#define BM_RTC_STAT_XTAL32768_PRESENT       0x8000000
-#define BF_RTC_STAT_XTAL32768_PRESENT(v)    (((v) << 27) & 0x8000000)
-#define BP_RTC_STAT_STALE_REGS              16
-#define BM_RTC_STAT_STALE_REGS              0xff0000
-#define BF_RTC_STAT_STALE_REGS(v)           (((v) << 16) & 0xff0000)
-#define BP_RTC_STAT_NEW_REGS                8
-#define BM_RTC_STAT_NEW_REGS                0xff00
-#define BF_RTC_STAT_NEW_REGS(v)             (((v) << 8) & 0xff00)
-
-/**
- * Register: HW_RTC_MILLISECONDS
- * Address: 0x20
- * SCT: yes
-*/
-#define HW_RTC_MILLISECONDS             (*(volatile unsigned long *)(REGS_RTC_BASE + 0x20 + 0x0))
-#define HW_RTC_MILLISECONDS_SET         (*(volatile unsigned long *)(REGS_RTC_BASE + 0x20 + 0x4))
-#define HW_RTC_MILLISECONDS_CLR         (*(volatile unsigned long *)(REGS_RTC_BASE + 0x20 + 0x8))
-#define HW_RTC_MILLISECONDS_TOG         (*(volatile unsigned long *)(REGS_RTC_BASE + 0x20 + 0xc))
-#define BP_RTC_MILLISECONDS_COUNT       0
-#define BM_RTC_MILLISECONDS_COUNT       0xffffffff
-#define BF_RTC_MILLISECONDS_COUNT(v)    (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_RTC_SECONDS
- * Address: 0x30
- * SCT: yes
-*/
-#define HW_RTC_SECONDS          (*(volatile unsigned long *)(REGS_RTC_BASE + 0x30 + 0x0))
-#define HW_RTC_SECONDS_SET      (*(volatile unsigned long *)(REGS_RTC_BASE + 0x30 + 0x4))
-#define HW_RTC_SECONDS_CLR      (*(volatile unsigned long *)(REGS_RTC_BASE + 0x30 + 0x8))
-#define HW_RTC_SECONDS_TOG      (*(volatile unsigned long *)(REGS_RTC_BASE + 0x30 + 0xc))
-#define BP_RTC_SECONDS_COUNT    0
-#define BM_RTC_SECONDS_COUNT    0xffffffff
-#define BF_RTC_SECONDS_COUNT(v) (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_RTC_ALARM
- * Address: 0x40
- * SCT: yes
-*/
-#define HW_RTC_ALARM            (*(volatile unsigned long *)(REGS_RTC_BASE + 0x40 + 0x0))
-#define HW_RTC_ALARM_SET        (*(volatile unsigned long *)(REGS_RTC_BASE + 0x40 + 0x4))
-#define HW_RTC_ALARM_CLR        (*(volatile unsigned long *)(REGS_RTC_BASE + 0x40 + 0x8))
-#define HW_RTC_ALARM_TOG        (*(volatile unsigned long *)(REGS_RTC_BASE + 0x40 + 0xc))
-#define BP_RTC_ALARM_VALUE      0
-#define BM_RTC_ALARM_VALUE      0xffffffff
-#define BF_RTC_ALARM_VALUE(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_RTC_WATCHDOG
- * Address: 0x50
- * SCT: yes
-*/
-#define HW_RTC_WATCHDOG             (*(volatile unsigned long *)(REGS_RTC_BASE + 0x50 + 0x0))
-#define HW_RTC_WATCHDOG_SET         (*(volatile unsigned long *)(REGS_RTC_BASE + 0x50 + 0x4))
-#define HW_RTC_WATCHDOG_CLR         (*(volatile unsigned long *)(REGS_RTC_BASE + 0x50 + 0x8))
-#define HW_RTC_WATCHDOG_TOG         (*(volatile unsigned long *)(REGS_RTC_BASE + 0x50 + 0xc))
-#define BP_RTC_WATCHDOG_COUNT       0
-#define BM_RTC_WATCHDOG_COUNT       0xffffffff
-#define BF_RTC_WATCHDOG_COUNT(v)    (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_RTC_PERSISTENT0
- * Address: 0x60
- * SCT: yes
-*/
-#define HW_RTC_PERSISTENT0                      (*(volatile unsigned long *)(REGS_RTC_BASE + 0x60 + 0x0))
-#define HW_RTC_PERSISTENT0_SET                  (*(volatile unsigned long *)(REGS_RTC_BASE + 0x60 + 0x4))
-#define HW_RTC_PERSISTENT0_CLR                  (*(volatile unsigned long *)(REGS_RTC_BASE + 0x60 + 0x8))
-#define HW_RTC_PERSISTENT0_TOG                  (*(volatile unsigned long *)(REGS_RTC_BASE + 0x60 + 0xc))
-#define BP_RTC_PERSISTENT0_SPARE_ANALOG         18
-#define BM_RTC_PERSISTENT0_SPARE_ANALOG         0xfffc0000
-#define BF_RTC_PERSISTENT0_SPARE_ANALOG(v)      (((v) << 18) & 0xfffc0000)
-#define BP_RTC_PERSISTENT0_AUTO_RESTART         17
-#define BM_RTC_PERSISTENT0_AUTO_RESTART         0x20000
-#define BF_RTC_PERSISTENT0_AUTO_RESTART(v)      (((v) << 17) & 0x20000)
-#define BP_RTC_PERSISTENT0_DISABLE_PSWITCH      16
-#define BM_RTC_PERSISTENT0_DISABLE_PSWITCH      0x10000
-#define BF_RTC_PERSISTENT0_DISABLE_PSWITCH(v)   (((v) << 16) & 0x10000)
-#define BP_RTC_PERSISTENT0_LOWERBIAS            14
-#define BM_RTC_PERSISTENT0_LOWERBIAS            0xc000
-#define BF_RTC_PERSISTENT0_LOWERBIAS(v)         (((v) << 14) & 0xc000)
-#define BP_RTC_PERSISTENT0_DISABLE_XTALOK       13
-#define BM_RTC_PERSISTENT0_DISABLE_XTALOK       0x2000
-#define BF_RTC_PERSISTENT0_DISABLE_XTALOK(v)    (((v) << 13) & 0x2000)
-#define BP_RTC_PERSISTENT0_MSEC_RES             8
-#define BM_RTC_PERSISTENT0_MSEC_RES             0x1f00
-#define BF_RTC_PERSISTENT0_MSEC_RES(v)          (((v) << 8) & 0x1f00)
-#define BP_RTC_PERSISTENT0_ALARM_WAKE           7
-#define BM_RTC_PERSISTENT0_ALARM_WAKE           0x80
-#define BF_RTC_PERSISTENT0_ALARM_WAKE(v)        (((v) << 7) & 0x80)
-#define BP_RTC_PERSISTENT0_XTAL32_FREQ          6
-#define BM_RTC_PERSISTENT0_XTAL32_FREQ          0x40
-#define BF_RTC_PERSISTENT0_XTAL32_FREQ(v)       (((v) << 6) & 0x40)
-#define BP_RTC_PERSISTENT0_XTAL32KHZ_PWRUP      5
-#define BM_RTC_PERSISTENT0_XTAL32KHZ_PWRUP      0x20
-#define BF_RTC_PERSISTENT0_XTAL32KHZ_PWRUP(v)   (((v) << 5) & 0x20)
-#define BP_RTC_PERSISTENT0_XTAL24MHZ_PWRUP      4
-#define BM_RTC_PERSISTENT0_XTAL24MHZ_PWRUP      0x10
-#define BF_RTC_PERSISTENT0_XTAL24MHZ_PWRUP(v)   (((v) << 4) & 0x10)
-#define BP_RTC_PERSISTENT0_LCK_SECS             3
-#define BM_RTC_PERSISTENT0_LCK_SECS             0x8
-#define BF_RTC_PERSISTENT0_LCK_SECS(v)          (((v) << 3) & 0x8)
-#define BP_RTC_PERSISTENT0_ALARM_EN             2
-#define BM_RTC_PERSISTENT0_ALARM_EN             0x4
-#define BF_RTC_PERSISTENT0_ALARM_EN(v)          (((v) << 2) & 0x4)
-#define BP_RTC_PERSISTENT0_ALARM_WAKE_EN        1
-#define BM_RTC_PERSISTENT0_ALARM_WAKE_EN        0x2
-#define BF_RTC_PERSISTENT0_ALARM_WAKE_EN(v)     (((v) << 1) & 0x2)
-#define BP_RTC_PERSISTENT0_CLOCKSOURCE          0
-#define BM_RTC_PERSISTENT0_CLOCKSOURCE          0x1
-#define BF_RTC_PERSISTENT0_CLOCKSOURCE(v)       (((v) << 0) & 0x1)
-
-/**
- * Register: HW_RTC_PERSISTENT1
- * Address: 0x70
- * SCT: yes
-*/
-#define HW_RTC_PERSISTENT1                                  (*(volatile unsigned long *)(REGS_RTC_BASE + 0x70 + 0x0))
-#define HW_RTC_PERSISTENT1_SET                              (*(volatile unsigned long *)(REGS_RTC_BASE + 0x70 + 0x4))
-#define HW_RTC_PERSISTENT1_CLR                              (*(volatile unsigned long *)(REGS_RTC_BASE + 0x70 + 0x8))
-#define HW_RTC_PERSISTENT1_TOG                              (*(volatile unsigned long *)(REGS_RTC_BASE + 0x70 + 0xc))
-#define BP_RTC_PERSISTENT1_GENERAL                          0
-#define BM_RTC_PERSISTENT1_GENERAL                          0xffffffff
-#define BV_RTC_PERSISTENT1_GENERAL__SPARE3                  0x4000
-#define BV_RTC_PERSISTENT1_GENERAL__SDRAM_BOOT              0x2000
-#define BV_RTC_PERSISTENT1_GENERAL__ENUMERATE_500MA_TWICE   0x1000
-#define BV_RTC_PERSISTENT1_GENERAL__USB_BOOT_PLAYER_MODE    0x800
-#define BV_RTC_PERSISTENT1_GENERAL__SKIP_CHECKDISK          0x400
-#define BV_RTC_PERSISTENT1_GENERAL__USB_LOW_POWER_MODE      0x200
-#define BV_RTC_PERSISTENT1_GENERAL__OTG_HNP_BIT             0x100
-#define BV_RTC_PERSISTENT1_GENERAL__OTG_ATL_ROLE_BIT        0x80
-#define BV_RTC_PERSISTENT1_GENERAL__SDRAM_CS_HI             0x40
-#define BV_RTC_PERSISTENT1_GENERAL__SDRAM_CS_LO             0x20
-#define BV_RTC_PERSISTENT1_GENERAL__SDRAM_NDX_3             0x10
-#define BV_RTC_PERSISTENT1_GENERAL__SDRAM_NDX_2             0x8
-#define BV_RTC_PERSISTENT1_GENERAL__SDRAM_NDX_1             0x4
-#define BV_RTC_PERSISTENT1_GENERAL__SDRAM_NDX_0             0x2
-#define BV_RTC_PERSISTENT1_GENERAL__ETM_ENABLE              0x1
-#define BF_RTC_PERSISTENT1_GENERAL(v)                       (((v) << 0) & 0xffffffff)
-#define BF_RTC_PERSISTENT1_GENERAL_V(v)                     ((BV_RTC_PERSISTENT1_GENERAL__##v << 0) & 0xffffffff)
-
-/**
- * Register: HW_RTC_PERSISTENT2
- * Address: 0x80
- * SCT: yes
-*/
-#define HW_RTC_PERSISTENT2              (*(volatile unsigned long *)(REGS_RTC_BASE + 0x80 + 0x0))
-#define HW_RTC_PERSISTENT2_SET          (*(volatile unsigned long *)(REGS_RTC_BASE + 0x80 + 0x4))
-#define HW_RTC_PERSISTENT2_CLR          (*(volatile unsigned long *)(REGS_RTC_BASE + 0x80 + 0x8))
-#define HW_RTC_PERSISTENT2_TOG          (*(volatile unsigned long *)(REGS_RTC_BASE + 0x80 + 0xc))
-#define BP_RTC_PERSISTENT2_GENERAL      0
-#define BM_RTC_PERSISTENT2_GENERAL      0xffffffff
-#define BF_RTC_PERSISTENT2_GENERAL(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_RTC_PERSISTENT3
- * Address: 0x90
- * SCT: yes
-*/
-#define HW_RTC_PERSISTENT3              (*(volatile unsigned long *)(REGS_RTC_BASE + 0x90 + 0x0))
-#define HW_RTC_PERSISTENT3_SET          (*(volatile unsigned long *)(REGS_RTC_BASE + 0x90 + 0x4))
-#define HW_RTC_PERSISTENT3_CLR          (*(volatile unsigned long *)(REGS_RTC_BASE + 0x90 + 0x8))
-#define HW_RTC_PERSISTENT3_TOG          (*(volatile unsigned long *)(REGS_RTC_BASE + 0x90 + 0xc))
-#define BP_RTC_PERSISTENT3_GENERAL      0
-#define BM_RTC_PERSISTENT3_GENERAL      0xffffffff
-#define BF_RTC_PERSISTENT3_GENERAL(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_RTC_PERSISTENT4
- * Address: 0xa0
- * SCT: yes
-*/
-#define HW_RTC_PERSISTENT4              (*(volatile unsigned long *)(REGS_RTC_BASE + 0xa0 + 0x0))
-#define HW_RTC_PERSISTENT4_SET          (*(volatile unsigned long *)(REGS_RTC_BASE + 0xa0 + 0x4))
-#define HW_RTC_PERSISTENT4_CLR          (*(volatile unsigned long *)(REGS_RTC_BASE + 0xa0 + 0x8))
-#define HW_RTC_PERSISTENT4_TOG          (*(volatile unsigned long *)(REGS_RTC_BASE + 0xa0 + 0xc))
-#define BP_RTC_PERSISTENT4_GENERAL      0
-#define BM_RTC_PERSISTENT4_GENERAL      0xffffffff
-#define BF_RTC_PERSISTENT4_GENERAL(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_RTC_PERSISTENT5
- * Address: 0xb0
- * SCT: yes
-*/
-#define HW_RTC_PERSISTENT5              (*(volatile unsigned long *)(REGS_RTC_BASE + 0xb0 + 0x0))
-#define HW_RTC_PERSISTENT5_SET          (*(volatile unsigned long *)(REGS_RTC_BASE + 0xb0 + 0x4))
-#define HW_RTC_PERSISTENT5_CLR          (*(volatile unsigned long *)(REGS_RTC_BASE + 0xb0 + 0x8))
-#define HW_RTC_PERSISTENT5_TOG          (*(volatile unsigned long *)(REGS_RTC_BASE + 0xb0 + 0xc))
-#define BP_RTC_PERSISTENT5_GENERAL      0
-#define BM_RTC_PERSISTENT5_GENERAL      0xffffffff
-#define BF_RTC_PERSISTENT5_GENERAL(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_RTC_DEBUG
- * Address: 0xc0
- * SCT: yes
-*/
-#define HW_RTC_DEBUG                        (*(volatile unsigned long *)(REGS_RTC_BASE + 0xc0 + 0x0))
-#define HW_RTC_DEBUG_SET                    (*(volatile unsigned long *)(REGS_RTC_BASE + 0xc0 + 0x4))
-#define HW_RTC_DEBUG_CLR                    (*(volatile unsigned long *)(REGS_RTC_BASE + 0xc0 + 0x8))
-#define HW_RTC_DEBUG_TOG                    (*(volatile unsigned long *)(REGS_RTC_BASE + 0xc0 + 0xc))
-#define BP_RTC_DEBUG_WATCHDOG_RESET_MASK    1
-#define BM_RTC_DEBUG_WATCHDOG_RESET_MASK    0x2
-#define BF_RTC_DEBUG_WATCHDOG_RESET_MASK(v) (((v) << 1) & 0x2)
-#define BP_RTC_DEBUG_WATCHDOG_RESET         0
-#define BM_RTC_DEBUG_WATCHDOG_RESET         0x1
-#define BF_RTC_DEBUG_WATCHDOG_RESET(v)      (((v) << 0) & 0x1)
-
-/**
- * Register: HW_RTC_VERSION
- * Address: 0xd0
- * SCT: no
-*/
-#define HW_RTC_VERSION          (*(volatile unsigned long *)(REGS_RTC_BASE + 0xd0))
-#define BP_RTC_VERSION_MAJOR    24
-#define BM_RTC_VERSION_MAJOR    0xff000000
-#define BF_RTC_VERSION_MAJOR(v) (((v) << 24) & 0xff000000)
-#define BP_RTC_VERSION_MINOR    16
-#define BM_RTC_VERSION_MINOR    0xff0000
-#define BF_RTC_VERSION_MINOR(v) (((v) << 16) & 0xff0000)
-#define BP_RTC_VERSION_STEP     0
-#define BM_RTC_VERSION_STEP     0xffff
-#define BF_RTC_VERSION_STEP(v)  (((v) << 0) & 0xffff)
-
-#endif /* __HEADERGEN__STMP3700__RTC__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-saif.h b/firmware/target/arm/imx233/regs/stmp3700/regs-saif.h
deleted file mode 100644
index 2599104610..0000000000
--- a/firmware/target/arm/imx233/regs/stmp3700/regs-saif.h
+++ /dev/null
@@ -1,154 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3700:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__STMP3700__SAIF__H__
-#define __HEADERGEN__STMP3700__SAIF__H__
-
-#define REGS_SAIF_BASE(i) ((i) == 1 ? 0x80042000 : 0x80046000)
-
-#define REGS_SAIF_VERSION "3.2.0"
-
-/**
- * Register: HW_SAIF_CTRL
- * Address: 0
- * SCT: yes
-*/
-#define HW_SAIF_CTRL(d)                     (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x0 + 0x0))
-#define HW_SAIF_CTRL_SET(d)                 (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x0 + 0x4))
-#define HW_SAIF_CTRL_CLR(d)                 (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x0 + 0x8))
-#define HW_SAIF_CTRL_TOG(d)                 (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x0 + 0xc))
-#define BP_SAIF_CTRL_SFTRST                 31
-#define BM_SAIF_CTRL_SFTRST                 0x80000000
-#define BF_SAIF_CTRL_SFTRST(v)              (((v) << 31) & 0x80000000)
-#define BP_SAIF_CTRL_CLKGATE                30
-#define BM_SAIF_CTRL_CLKGATE                0x40000000
-#define BF_SAIF_CTRL_CLKGATE(v)             (((v) << 30) & 0x40000000)
-#define BP_SAIF_CTRL_BITCLK_MULT_RATE       27
-#define BM_SAIF_CTRL_BITCLK_MULT_RATE       0x38000000
-#define BF_SAIF_CTRL_BITCLK_MULT_RATE(v)    (((v) << 27) & 0x38000000)
-#define BP_SAIF_CTRL_BITCLK_BASE_RATE       26
-#define BM_SAIF_CTRL_BITCLK_BASE_RATE       0x4000000
-#define BF_SAIF_CTRL_BITCLK_BASE_RATE(v)    (((v) << 26) & 0x4000000)
-#define BP_SAIF_CTRL_FIFO_ERROR_IRQ_EN      25
-#define BM_SAIF_CTRL_FIFO_ERROR_IRQ_EN      0x2000000
-#define BF_SAIF_CTRL_FIFO_ERROR_IRQ_EN(v)   (((v) << 25) & 0x2000000)
-#define BP_SAIF_CTRL_FIFO_SERVICE_IRQ_EN    24
-#define BM_SAIF_CTRL_FIFO_SERVICE_IRQ_EN    0x1000000
-#define BF_SAIF_CTRL_FIFO_SERVICE_IRQ_EN(v) (((v) << 24) & 0x1000000)
-#define BP_SAIF_CTRL_DMAWAIT_COUNT          16
-#define BM_SAIF_CTRL_DMAWAIT_COUNT          0x1f0000
-#define BF_SAIF_CTRL_DMAWAIT_COUNT(v)       (((v) << 16) & 0x1f0000)
-#define BP_SAIF_CTRL_CHANNEL_NUM_SELECT     14
-#define BM_SAIF_CTRL_CHANNEL_NUM_SELECT     0xc000
-#define BF_SAIF_CTRL_CHANNEL_NUM_SELECT(v)  (((v) << 14) & 0xc000)
-#define BP_SAIF_CTRL_BIT_ORDER              12
-#define BM_SAIF_CTRL_BIT_ORDER              0x1000
-#define BF_SAIF_CTRL_BIT_ORDER(v)           (((v) << 12) & 0x1000)
-#define BP_SAIF_CTRL_DELAY                  11
-#define BM_SAIF_CTRL_DELAY                  0x800
-#define BF_SAIF_CTRL_DELAY(v)               (((v) << 11) & 0x800)
-#define BP_SAIF_CTRL_JUSTIFY                10
-#define BM_SAIF_CTRL_JUSTIFY                0x400
-#define BF_SAIF_CTRL_JUSTIFY(v)             (((v) << 10) & 0x400)
-#define BP_SAIF_CTRL_LRCLK_POLARITY         9
-#define BM_SAIF_CTRL_LRCLK_POLARITY         0x200
-#define BF_SAIF_CTRL_LRCLK_POLARITY(v)      (((v) << 9) & 0x200)
-#define BP_SAIF_CTRL_BITCLK_EDGE            8
-#define BM_SAIF_CTRL_BITCLK_EDGE            0x100
-#define BF_SAIF_CTRL_BITCLK_EDGE(v)         (((v) << 8) & 0x100)
-#define BP_SAIF_CTRL_WORD_LENGTH            4
-#define BM_SAIF_CTRL_WORD_LENGTH            0xf0
-#define BF_SAIF_CTRL_WORD_LENGTH(v)         (((v) << 4) & 0xf0)
-#define BP_SAIF_CTRL_BITCLK_48XFS_ENABLE    3
-#define BM_SAIF_CTRL_BITCLK_48XFS_ENABLE    0x8
-#define BF_SAIF_CTRL_BITCLK_48XFS_ENABLE(v) (((v) << 3) & 0x8)
-#define BP_SAIF_CTRL_SLAVE_MODE             2
-#define BM_SAIF_CTRL_SLAVE_MODE             0x4
-#define BF_SAIF_CTRL_SLAVE_MODE(v)          (((v) << 2) & 0x4)
-#define BP_SAIF_CTRL_READ_MODE              1
-#define BM_SAIF_CTRL_READ_MODE              0x2
-#define BF_SAIF_CTRL_READ_MODE(v)           (((v) << 1) & 0x2)
-#define BP_SAIF_CTRL_RUN                    0
-#define BM_SAIF_CTRL_RUN                    0x1
-#define BF_SAIF_CTRL_RUN(v)                 (((v) << 0) & 0x1)
-
-/**
- * Register: HW_SAIF_STAT
- * Address: 0x10
- * SCT: yes
-*/
-#define HW_SAIF_STAT(d)                     (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x10 + 0x0))
-#define HW_SAIF_STAT_SET(d)                 (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x10 + 0x4))
-#define HW_SAIF_STAT_CLR(d)                 (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x10 + 0x8))
-#define HW_SAIF_STAT_TOG(d)                 (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x10 + 0xc))
-#define BP_SAIF_STAT_PRESENT                31
-#define BM_SAIF_STAT_PRESENT                0x80000000
-#define BF_SAIF_STAT_PRESENT(v)             (((v) << 31) & 0x80000000)
-#define BP_SAIF_STAT_DMA_PREQ               16
-#define BM_SAIF_STAT_DMA_PREQ               0x10000
-#define BF_SAIF_STAT_DMA_PREQ(v)            (((v) << 16) & 0x10000)
-#define BP_SAIF_STAT_FIFO_UNDERFLOW_IRQ     6
-#define BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ     0x40
-#define BF_SAIF_STAT_FIFO_UNDERFLOW_IRQ(v)  (((v) << 6) & 0x40)
-#define BP_SAIF_STAT_FIFO_OVERFLOW_IRQ      5
-#define BM_SAIF_STAT_FIFO_OVERFLOW_IRQ      0x20
-#define BF_SAIF_STAT_FIFO_OVERFLOW_IRQ(v)   (((v) << 5) & 0x20)
-#define BP_SAIF_STAT_FIFO_SERVICE_IRQ       4
-#define BM_SAIF_STAT_FIFO_SERVICE_IRQ       0x10
-#define BF_SAIF_STAT_FIFO_SERVICE_IRQ(v)    (((v) << 4) & 0x10)
-#define BP_SAIF_STAT_BUSY                   0
-#define BM_SAIF_STAT_BUSY                   0x1
-#define BF_SAIF_STAT_BUSY(v)                (((v) << 0) & 0x1)
-
-/**
- * Register: HW_SAIF_DATA
- * Address: 0x20
- * SCT: yes
-*/
-#define HW_SAIF_DATA(d)             (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x20 + 0x0))
-#define HW_SAIF_DATA_SET(d)         (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x20 + 0x4))
-#define HW_SAIF_DATA_CLR(d)         (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x20 + 0x8))
-#define HW_SAIF_DATA_TOG(d)         (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x20 + 0xc))
-#define BP_SAIF_DATA_PCM_RIGHT      16
-#define BM_SAIF_DATA_PCM_RIGHT      0xffff0000
-#define BF_SAIF_DATA_PCM_RIGHT(v)   (((v) << 16) & 0xffff0000)
-#define BP_SAIF_DATA_PCM_LEFT       0
-#define BM_SAIF_DATA_PCM_LEFT       0xffff
-#define BF_SAIF_DATA_PCM_LEFT(v)    (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_SAIF_VERSION
- * Address: 0x30
- * SCT: no
-*/
-#define HW_SAIF_VERSION(d)          (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x30))
-#define BP_SAIF_VERSION_MAJOR       24
-#define BM_SAIF_VERSION_MAJOR       0xff000000
-#define BF_SAIF_VERSION_MAJOR(v)    (((v) << 24) & 0xff000000)
-#define BP_SAIF_VERSION_MINOR       16
-#define BM_SAIF_VERSION_MINOR       0xff0000
-#define BF_SAIF_VERSION_MINOR(v)    (((v) << 16) & 0xff0000)
-#define BP_SAIF_VERSION_STEP        0
-#define BM_SAIF_VERSION_STEP        0xffff
-#define BF_SAIF_VERSION_STEP(v)     (((v) << 0) & 0xffff)
-
-#endif /* __HEADERGEN__STMP3700__SAIF__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-spdif.h b/firmware/target/arm/imx233/regs/stmp3700/regs-spdif.h
deleted file mode 100644
index 07bbffe2e7..0000000000
--- a/firmware/target/arm/imx233/regs/stmp3700/regs-spdif.h
+++ /dev/null
@@ -1,181 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3700:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__STMP3700__SPDIF__H__
-#define __HEADERGEN__STMP3700__SPDIF__H__
-
-#define REGS_SPDIF_BASE (0x80054000)
-
-#define REGS_SPDIF_VERSION "3.2.0"
-
-/**
- * Register: HW_SPDIF_CTRL
- * Address: 0
- * SCT: yes
-*/
-#define HW_SPDIF_CTRL                       (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x0 + 0x0))
-#define HW_SPDIF_CTRL_SET                   (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x0 + 0x4))
-#define HW_SPDIF_CTRL_CLR                   (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x0 + 0x8))
-#define HW_SPDIF_CTRL_TOG                   (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x0 + 0xc))
-#define BP_SPDIF_CTRL_SFTRST                31
-#define BM_SPDIF_CTRL_SFTRST                0x80000000
-#define BF_SPDIF_CTRL_SFTRST(v)             (((v) << 31) & 0x80000000)
-#define BP_SPDIF_CTRL_CLKGATE               30
-#define BM_SPDIF_CTRL_CLKGATE               0x40000000
-#define BF_SPDIF_CTRL_CLKGATE(v)            (((v) << 30) & 0x40000000)
-#define BP_SPDIF_CTRL_DMAWAIT_COUNT         16
-#define BM_SPDIF_CTRL_DMAWAIT_COUNT         0x1f0000
-#define BF_SPDIF_CTRL_DMAWAIT_COUNT(v)      (((v) << 16) & 0x1f0000)
-#define BP_SPDIF_CTRL_WAIT_END_XFER         5
-#define BM_SPDIF_CTRL_WAIT_END_XFER         0x20
-#define BF_SPDIF_CTRL_WAIT_END_XFER(v)      (((v) << 5) & 0x20)
-#define BP_SPDIF_CTRL_WORD_LENGTH           4
-#define BM_SPDIF_CTRL_WORD_LENGTH           0x10
-#define BF_SPDIF_CTRL_WORD_LENGTH(v)        (((v) << 4) & 0x10)
-#define BP_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ    3
-#define BM_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ    0x8
-#define BF_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ(v) (((v) << 3) & 0x8)
-#define BP_SPDIF_CTRL_FIFO_OVERFLOW_IRQ     2
-#define BM_SPDIF_CTRL_FIFO_OVERFLOW_IRQ     0x4
-#define BF_SPDIF_CTRL_FIFO_OVERFLOW_IRQ(v)  (((v) << 2) & 0x4)
-#define BP_SPDIF_CTRL_FIFO_ERROR_IRQ_EN     1
-#define BM_SPDIF_CTRL_FIFO_ERROR_IRQ_EN     0x2
-#define BF_SPDIF_CTRL_FIFO_ERROR_IRQ_EN(v)  (((v) << 1) & 0x2)
-#define BP_SPDIF_CTRL_RUN                   0
-#define BM_SPDIF_CTRL_RUN                   0x1
-#define BF_SPDIF_CTRL_RUN(v)                (((v) << 0) & 0x1)
-
-/**
- * Register: HW_SPDIF_STAT
- * Address: 0x10
- * SCT: no
-*/
-#define HW_SPDIF_STAT               (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x10))
-#define BP_SPDIF_STAT_PRESENT       31
-#define BM_SPDIF_STAT_PRESENT       0x80000000
-#define BF_SPDIF_STAT_PRESENT(v)    (((v) << 31) & 0x80000000)
-#define BP_SPDIF_STAT_END_XFER      0
-#define BM_SPDIF_STAT_END_XFER      0x1
-#define BF_SPDIF_STAT_END_XFER(v)   (((v) << 0) & 0x1)
-
-/**
- * Register: HW_SPDIF_FRAMECTRL
- * Address: 0x20
- * SCT: yes
-*/
-#define HW_SPDIF_FRAMECTRL              (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x20 + 0x0))
-#define HW_SPDIF_FRAMECTRL_SET          (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x20 + 0x4))
-#define HW_SPDIF_FRAMECTRL_CLR          (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x20 + 0x8))
-#define HW_SPDIF_FRAMECTRL_TOG          (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x20 + 0xc))
-#define BP_SPDIF_FRAMECTRL_V_CONFIG     17
-#define BM_SPDIF_FRAMECTRL_V_CONFIG     0x20000
-#define BF_SPDIF_FRAMECTRL_V_CONFIG(v)  (((v) << 17) & 0x20000)
-#define BP_SPDIF_FRAMECTRL_AUTO_MUTE    16
-#define BM_SPDIF_FRAMECTRL_AUTO_MUTE    0x10000
-#define BF_SPDIF_FRAMECTRL_AUTO_MUTE(v) (((v) << 16) & 0x10000)
-#define BP_SPDIF_FRAMECTRL_USER_DATA    14
-#define BM_SPDIF_FRAMECTRL_USER_DATA    0x4000
-#define BF_SPDIF_FRAMECTRL_USER_DATA(v) (((v) << 14) & 0x4000)
-#define BP_SPDIF_FRAMECTRL_V            13
-#define BM_SPDIF_FRAMECTRL_V            0x2000
-#define BF_SPDIF_FRAMECTRL_V(v)         (((v) << 13) & 0x2000)
-#define BP_SPDIF_FRAMECTRL_L            12
-#define BM_SPDIF_FRAMECTRL_L            0x1000
-#define BF_SPDIF_FRAMECTRL_L(v)         (((v) << 12) & 0x1000)
-#define BP_SPDIF_FRAMECTRL_CC           4
-#define BM_SPDIF_FRAMECTRL_CC           0x7f0
-#define BF_SPDIF_FRAMECTRL_CC(v)        (((v) << 4) & 0x7f0)
-#define BP_SPDIF_FRAMECTRL_PRE          3
-#define BM_SPDIF_FRAMECTRL_PRE          0x8
-#define BF_SPDIF_FRAMECTRL_PRE(v)       (((v) << 3) & 0x8)
-#define BP_SPDIF_FRAMECTRL_COPY         2
-#define BM_SPDIF_FRAMECTRL_COPY         0x4
-#define BF_SPDIF_FRAMECTRL_COPY(v)      (((v) << 2) & 0x4)
-#define BP_SPDIF_FRAMECTRL_AUDIO        1
-#define BM_SPDIF_FRAMECTRL_AUDIO        0x2
-#define BF_SPDIF_FRAMECTRL_AUDIO(v)     (((v) << 1) & 0x2)
-#define BP_SPDIF_FRAMECTRL_PRO          0
-#define BM_SPDIF_FRAMECTRL_PRO          0x1
-#define BF_SPDIF_FRAMECTRL_PRO(v)       (((v) << 0) & 0x1)
-
-/**
- * Register: HW_SPDIF_SRR
- * Address: 0x30
- * SCT: yes
-*/
-#define HW_SPDIF_SRR                (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x30 + 0x0))
-#define HW_SPDIF_SRR_SET            (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x30 + 0x4))
-#define HW_SPDIF_SRR_CLR            (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x30 + 0x8))
-#define HW_SPDIF_SRR_TOG            (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x30 + 0xc))
-#define BP_SPDIF_SRR_BASEMULT       28
-#define BM_SPDIF_SRR_BASEMULT       0x70000000
-#define BF_SPDIF_SRR_BASEMULT(v)    (((v) << 28) & 0x70000000)
-#define BP_SPDIF_SRR_RATE           0
-#define BM_SPDIF_SRR_RATE           0xfffff
-#define BF_SPDIF_SRR_RATE(v)        (((v) << 0) & 0xfffff)
-
-/**
- * Register: HW_SPDIF_DEBUG
- * Address: 0x40
- * SCT: no
-*/
-#define HW_SPDIF_DEBUG                  (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x40))
-#define BP_SPDIF_DEBUG_DMA_PREQ         1
-#define BM_SPDIF_DEBUG_DMA_PREQ         0x2
-#define BF_SPDIF_DEBUG_DMA_PREQ(v)      (((v) << 1) & 0x2)
-#define BP_SPDIF_DEBUG_FIFO_STATUS      0
-#define BM_SPDIF_DEBUG_FIFO_STATUS      0x1
-#define BF_SPDIF_DEBUG_FIFO_STATUS(v)   (((v) << 0) & 0x1)
-
-/**
- * Register: HW_SPDIF_DATA
- * Address: 0x50
- * SCT: yes
-*/
-#define HW_SPDIF_DATA           (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x50 + 0x0))
-#define HW_SPDIF_DATA_SET       (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x50 + 0x4))
-#define HW_SPDIF_DATA_CLR       (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x50 + 0x8))
-#define HW_SPDIF_DATA_TOG       (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x50 + 0xc))
-#define BP_SPDIF_DATA_HIGH      16
-#define BM_SPDIF_DATA_HIGH      0xffff0000
-#define BF_SPDIF_DATA_HIGH(v)   (((v) << 16) & 0xffff0000)
-#define BP_SPDIF_DATA_LOW       0
-#define BM_SPDIF_DATA_LOW       0xffff
-#define BF_SPDIF_DATA_LOW(v)    (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_SPDIF_VERSION
- * Address: 0x60
- * SCT: no
-*/
-#define HW_SPDIF_VERSION            (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x60))
-#define BP_SPDIF_VERSION_MAJOR      24
-#define BM_SPDIF_VERSION_MAJOR      0xff000000
-#define BF_SPDIF_VERSION_MAJOR(v)   (((v) << 24) & 0xff000000)
-#define BP_SPDIF_VERSION_MINOR      16
-#define BM_SPDIF_VERSION_MINOR      0xff0000
-#define BF_SPDIF_VERSION_MINOR(v)   (((v) << 16) & 0xff0000)
-#define BP_SPDIF_VERSION_STEP       0
-#define BM_SPDIF_VERSION_STEP       0xffff
-#define BF_SPDIF_VERSION_STEP(v)    (((v) << 0) & 0xffff)
-
-#endif /* __HEADERGEN__STMP3700__SPDIF__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-ssp.h b/firmware/target/arm/imx233/regs/stmp3700/regs-ssp.h
deleted file mode 100644
index 1ab27d8da4..0000000000
--- a/firmware/target/arm/imx233/regs/stmp3700/regs-ssp.h
+++ /dev/null
@@ -1,558 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3700:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__STMP3700__SSP__H__
-#define __HEADERGEN__STMP3700__SSP__H__
-
-#define REGS_SSP_BASE(i) ((i) == 1 ? 0x80010000 : 0x80034000)
-
-#define REGS_SSP_VERSION "3.2.0"
-
-/**
- * Register: HW_SSP_CTRL0
- * Address: 0
- * SCT: yes
-*/
-#define HW_SSP_CTRL0(d)                     (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x0 + 0x0))
-#define HW_SSP_CTRL0_SET(d)                 (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x0 + 0x4))
-#define HW_SSP_CTRL0_CLR(d)                 (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x0 + 0x8))
-#define HW_SSP_CTRL0_TOG(d)                 (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x0 + 0xc))
-#define BP_SSP_CTRL0_SFTRST                 31
-#define BM_SSP_CTRL0_SFTRST                 0x80000000
-#define BF_SSP_CTRL0_SFTRST(v)              (((v) << 31) & 0x80000000)
-#define BP_SSP_CTRL0_CLKGATE                30
-#define BM_SSP_CTRL0_CLKGATE                0x40000000
-#define BF_SSP_CTRL0_CLKGATE(v)             (((v) << 30) & 0x40000000)
-#define BP_SSP_CTRL0_RUN                    29
-#define BM_SSP_CTRL0_RUN                    0x20000000
-#define BF_SSP_CTRL0_RUN(v)                 (((v) << 29) & 0x20000000)
-#define BP_SSP_CTRL0_SDIO_IRQ_CHECK         28
-#define BM_SSP_CTRL0_SDIO_IRQ_CHECK         0x10000000
-#define BF_SSP_CTRL0_SDIO_IRQ_CHECK(v)      (((v) << 28) & 0x10000000)
-#define BP_SSP_CTRL0_LOCK_CS                27
-#define BM_SSP_CTRL0_LOCK_CS                0x8000000
-#define BF_SSP_CTRL0_LOCK_CS(v)             (((v) << 27) & 0x8000000)
-#define BP_SSP_CTRL0_IGNORE_CRC             26
-#define BM_SSP_CTRL0_IGNORE_CRC             0x4000000
-#define BF_SSP_CTRL0_IGNORE_CRC(v)          (((v) << 26) & 0x4000000)
-#define BP_SSP_CTRL0_READ                   25
-#define BM_SSP_CTRL0_READ                   0x2000000
-#define BF_SSP_CTRL0_READ(v)                (((v) << 25) & 0x2000000)
-#define BP_SSP_CTRL0_DATA_XFER              24
-#define BM_SSP_CTRL0_DATA_XFER              0x1000000
-#define BF_SSP_CTRL0_DATA_XFER(v)           (((v) << 24) & 0x1000000)
-#define BP_SSP_CTRL0_BUS_WIDTH              22
-#define BM_SSP_CTRL0_BUS_WIDTH              0xc00000
-#define BV_SSP_CTRL0_BUS_WIDTH__ONE_BIT     0x0
-#define BV_SSP_CTRL0_BUS_WIDTH__FOUR_BIT    0x1
-#define BV_SSP_CTRL0_BUS_WIDTH__EIGHT_BIT   0x2
-#define BF_SSP_CTRL0_BUS_WIDTH(v)           (((v) << 22) & 0xc00000)
-#define BF_SSP_CTRL0_BUS_WIDTH_V(v)         ((BV_SSP_CTRL0_BUS_WIDTH__##v << 22) & 0xc00000)
-#define BP_SSP_CTRL0_WAIT_FOR_IRQ           21
-#define BM_SSP_CTRL0_WAIT_FOR_IRQ           0x200000
-#define BF_SSP_CTRL0_WAIT_FOR_IRQ(v)        (((v) << 21) & 0x200000)
-#define BP_SSP_CTRL0_WAIT_FOR_CMD           20
-#define BM_SSP_CTRL0_WAIT_FOR_CMD           0x100000
-#define BF_SSP_CTRL0_WAIT_FOR_CMD(v)        (((v) << 20) & 0x100000)
-#define BP_SSP_CTRL0_LONG_RESP              19
-#define BM_SSP_CTRL0_LONG_RESP              0x80000
-#define BF_SSP_CTRL0_LONG_RESP(v)           (((v) << 19) & 0x80000)
-#define BP_SSP_CTRL0_CHECK_RESP             18
-#define BM_SSP_CTRL0_CHECK_RESP             0x40000
-#define BF_SSP_CTRL0_CHECK_RESP(v)          (((v) << 18) & 0x40000)
-#define BP_SSP_CTRL0_GET_RESP               17
-#define BM_SSP_CTRL0_GET_RESP               0x20000
-#define BF_SSP_CTRL0_GET_RESP(v)            (((v) << 17) & 0x20000)
-#define BP_SSP_CTRL0_ENABLE                 16
-#define BM_SSP_CTRL0_ENABLE                 0x10000
-#define BF_SSP_CTRL0_ENABLE(v)              (((v) << 16) & 0x10000)
-#define BP_SSP_CTRL0_XFER_COUNT             0
-#define BM_SSP_CTRL0_XFER_COUNT             0xffff
-#define BF_SSP_CTRL0_XFER_COUNT(v)          (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_SSP_CMD0
- * Address: 0x10
- * SCT: yes
-*/
-#define HW_SSP_CMD0(d)                              (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x10 + 0x0))
-#define HW_SSP_CMD0_SET(d)                          (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x10 + 0x4))
-#define HW_SSP_CMD0_CLR(d)                          (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x10 + 0x8))
-#define HW_SSP_CMD0_TOG(d)                          (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x10 + 0xc))
-#define BP_SSP_CMD0_APPEND_8CYC                     20
-#define BM_SSP_CMD0_APPEND_8CYC                     0x100000
-#define BF_SSP_CMD0_APPEND_8CYC(v)                  (((v) << 20) & 0x100000)
-#define BP_SSP_CMD0_BLOCK_SIZE                      16
-#define BM_SSP_CMD0_BLOCK_SIZE                      0xf0000
-#define BF_SSP_CMD0_BLOCK_SIZE(v)                   (((v) << 16) & 0xf0000)
-#define BP_SSP_CMD0_BLOCK_COUNT                     8
-#define BM_SSP_CMD0_BLOCK_COUNT                     0xff00
-#define BF_SSP_CMD0_BLOCK_COUNT(v)                  (((v) << 8) & 0xff00)
-#define BP_SSP_CMD0_CMD                             0
-#define BM_SSP_CMD0_CMD                             0xff
-#define BV_SSP_CMD0_CMD__MMC_GO_IDLE_STATE          0x0
-#define BV_SSP_CMD0_CMD__MMC_SEND_OP_COND           0x1
-#define BV_SSP_CMD0_CMD__MMC_ALL_SEND_CID           0x2
-#define BV_SSP_CMD0_CMD__MMC_SET_RELATIVE_ADDR      0x3
-#define BV_SSP_CMD0_CMD__MMC_SET_DSR                0x4
-#define BV_SSP_CMD0_CMD__MMC_RESERVED_5             0x5
-#define BV_SSP_CMD0_CMD__MMC_SWITCH                 0x6
-#define BV_SSP_CMD0_CMD__MMC_SELECT_DESELECT_CARD   0x7
-#define BV_SSP_CMD0_CMD__MMC_SEND_EXT_CSD           0x8
-#define BV_SSP_CMD0_CMD__MMC_SEND_CSD               0x9
-#define BV_SSP_CMD0_CMD__MMC_SEND_CID               0xa
-#define BV_SSP_CMD0_CMD__MMC_READ_DAT_UNTIL_STOP    0xb
-#define BV_SSP_CMD0_CMD__MMC_STOP_TRANSMISSION      0xc
-#define BV_SSP_CMD0_CMD__MMC_SEND_STATUS            0xd
-#define BV_SSP_CMD0_CMD__MMC_BUSTEST_R              0xe
-#define BV_SSP_CMD0_CMD__MMC_GO_INACTIVE_STATE      0xf
-#define BV_SSP_CMD0_CMD__MMC_SET_BLOCKLEN           0x10
-#define BV_SSP_CMD0_CMD__MMC_READ_SINGLE_BLOCK      0x11
-#define BV_SSP_CMD0_CMD__MMC_READ_MULTIPLE_BLOCK    0x12
-#define BV_SSP_CMD0_CMD__MMC_BUSTEST_W              0x13
-#define BV_SSP_CMD0_CMD__MMC_WRITE_DAT_UNTIL_STOP   0x14
-#define BV_SSP_CMD0_CMD__MMC_SET_BLOCK_COUNT        0x17
-#define BV_SSP_CMD0_CMD__MMC_WRITE_BLOCK            0x18
-#define BV_SSP_CMD0_CMD__MMC_WRITE_MULTIPLE_BLOCK   0x19
-#define BV_SSP_CMD0_CMD__MMC_PROGRAM_CID            0x1a
-#define BV_SSP_CMD0_CMD__MMC_PROGRAM_CSD            0x1b
-#define BV_SSP_CMD0_CMD__MMC_SET_WRITE_PROT         0x1c
-#define BV_SSP_CMD0_CMD__MMC_CLR_WRITE_PROT         0x1d
-#define BV_SSP_CMD0_CMD__MMC_SEND_WRITE_PROT        0x1e
-#define BV_SSP_CMD0_CMD__MMC_ERASE_GROUP_START      0x23
-#define BV_SSP_CMD0_CMD__MMC_ERASE_GROUP_END        0x24
-#define BV_SSP_CMD0_CMD__MMC_ERASE                  0x26
-#define BV_SSP_CMD0_CMD__MMC_FAST_IO                0x27
-#define BV_SSP_CMD0_CMD__MMC_GO_IRQ_STATE           0x28
-#define BV_SSP_CMD0_CMD__MMC_LOCK_UNLOCK            0x2a
-#define BV_SSP_CMD0_CMD__MMC_APP_CMD                0x37
-#define BV_SSP_CMD0_CMD__MMC_GEN_CMD                0x38
-#define BV_SSP_CMD0_CMD__SD_GO_IDLE_STATE           0x0
-#define BV_SSP_CMD0_CMD__SD_ALL_SEND_CID            0x2
-#define BV_SSP_CMD0_CMD__SD_SEND_RELATIVE_ADDR      0x3
-#define BV_SSP_CMD0_CMD__SD_SET_DSR                 0x4
-#define BV_SSP_CMD0_CMD__SD_IO_SEND_OP_COND         0x5
-#define BV_SSP_CMD0_CMD__SD_SELECT_DESELECT_CARD    0x7
-#define BV_SSP_CMD0_CMD__SD_SEND_CSD                0x9
-#define BV_SSP_CMD0_CMD__SD_SEND_CID                0xa
-#define BV_SSP_CMD0_CMD__SD_STOP_TRANSMISSION       0xc
-#define BV_SSP_CMD0_CMD__SD_SEND_STATUS             0xd
-#define BV_SSP_CMD0_CMD__SD_GO_INACTIVE_STATE       0xf
-#define BV_SSP_CMD0_CMD__SD_SET_BLOCKLEN            0x10
-#define BV_SSP_CMD0_CMD__SD_READ_SINGLE_BLOCK       0x11
-#define BV_SSP_CMD0_CMD__SD_READ_MULTIPLE_BLOCK     0x12
-#define BV_SSP_CMD0_CMD__SD_WRITE_BLOCK             0x18
-#define BV_SSP_CMD0_CMD__SD_WRITE_MULTIPLE_BLOCK    0x19
-#define BV_SSP_CMD0_CMD__SD_PROGRAM_CSD             0x1b
-#define BV_SSP_CMD0_CMD__SD_SET_WRITE_PROT          0x1c
-#define BV_SSP_CMD0_CMD__SD_CLR_WRITE_PROT          0x1d
-#define BV_SSP_CMD0_CMD__SD_SEND_WRITE_PROT         0x1e
-#define BV_SSP_CMD0_CMD__SD_ERASE_WR_BLK_START      0x20
-#define BV_SSP_CMD0_CMD__SD_ERASE_WR_BLK_END        0x21
-#define BV_SSP_CMD0_CMD__SD_ERASE_GROUP_START       0x23
-#define BV_SSP_CMD0_CMD__SD_ERASE_GROUP_END         0x24
-#define BV_SSP_CMD0_CMD__SD_ERASE                   0x26
-#define BV_SSP_CMD0_CMD__SD_LOCK_UNLOCK             0x2a
-#define BV_SSP_CMD0_CMD__SD_IO_RW_DIRECT            0x34
-#define BV_SSP_CMD0_CMD__SD_IO_RW_EXTENDED          0x35
-#define BV_SSP_CMD0_CMD__SD_APP_CMD                 0x37
-#define BV_SSP_CMD0_CMD__SD_GEN_CMD                 0x38
-#define BF_SSP_CMD0_CMD(v)                          (((v) << 0) & 0xff)
-#define BF_SSP_CMD0_CMD_V(v)                        ((BV_SSP_CMD0_CMD__##v << 0) & 0xff)
-
-/**
- * Register: HW_SSP_CMD1
- * Address: 0x20
- * SCT: no
-*/
-#define HW_SSP_CMD1(d)          (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x20))
-#define BP_SSP_CMD1_CMD_ARG     0
-#define BM_SSP_CMD1_CMD_ARG     0xffffffff
-#define BF_SSP_CMD1_CMD_ARG(v)  (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_SSP_COMPREF
- * Address: 0x30
- * SCT: no
-*/
-#define HW_SSP_COMPREF(d)           (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x30))
-#define BP_SSP_COMPREF_REFERENCE    0
-#define BM_SSP_COMPREF_REFERENCE    0xffffffff
-#define BF_SSP_COMPREF_REFERENCE(v) (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_SSP_COMPMASK
- * Address: 0x40
- * SCT: no
-*/
-#define HW_SSP_COMPMASK(d)      (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x40))
-#define BP_SSP_COMPMASK_MASK    0
-#define BM_SSP_COMPMASK_MASK    0xffffffff
-#define BF_SSP_COMPMASK_MASK(v) (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_SSP_TIMING
- * Address: 0x50
- * SCT: no
-*/
-#define HW_SSP_TIMING(d)                (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x50))
-#define BP_SSP_TIMING_TIMEOUT           16
-#define BM_SSP_TIMING_TIMEOUT           0xffff0000
-#define BF_SSP_TIMING_TIMEOUT(v)        (((v) << 16) & 0xffff0000)
-#define BP_SSP_TIMING_CLOCK_DIVIDE      8
-#define BM_SSP_TIMING_CLOCK_DIVIDE      0xff00
-#define BF_SSP_TIMING_CLOCK_DIVIDE(v)   (((v) << 8) & 0xff00)
-#define BP_SSP_TIMING_CLOCK_RATE        0
-#define BM_SSP_TIMING_CLOCK_RATE        0xff
-#define BF_SSP_TIMING_CLOCK_RATE(v)     (((v) << 0) & 0xff)
-
-/**
- * Register: HW_SSP_CTRL1
- * Address: 0x60
- * SCT: yes
-*/
-#define HW_SSP_CTRL1(d)                         (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x60 + 0x0))
-#define HW_SSP_CTRL1_SET(d)                     (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x60 + 0x4))
-#define HW_SSP_CTRL1_CLR(d)                     (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x60 + 0x8))
-#define HW_SSP_CTRL1_TOG(d)                     (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x60 + 0xc))
-#define BP_SSP_CTRL1_SDIO_IRQ                   31
-#define BM_SSP_CTRL1_SDIO_IRQ                   0x80000000
-#define BF_SSP_CTRL1_SDIO_IRQ(v)                (((v) << 31) & 0x80000000)
-#define BP_SSP_CTRL1_SDIO_IRQ_EN                30
-#define BM_SSP_CTRL1_SDIO_IRQ_EN                0x40000000
-#define BF_SSP_CTRL1_SDIO_IRQ_EN(v)             (((v) << 30) & 0x40000000)
-#define BP_SSP_CTRL1_RESP_ERR_IRQ               29
-#define BM_SSP_CTRL1_RESP_ERR_IRQ               0x20000000
-#define BF_SSP_CTRL1_RESP_ERR_IRQ(v)            (((v) << 29) & 0x20000000)
-#define BP_SSP_CTRL1_RESP_ERR_IRQ_EN            28
-#define BM_SSP_CTRL1_RESP_ERR_IRQ_EN            0x10000000
-#define BF_SSP_CTRL1_RESP_ERR_IRQ_EN(v)         (((v) << 28) & 0x10000000)
-#define BP_SSP_CTRL1_RESP_TIMEOUT_IRQ           27
-#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ           0x8000000
-#define BF_SSP_CTRL1_RESP_TIMEOUT_IRQ(v)        (((v) << 27) & 0x8000000)
-#define BP_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN        26
-#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN        0x4000000
-#define BF_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN(v)     (((v) << 26) & 0x4000000)
-#define BP_SSP_CTRL1_DATA_TIMEOUT_IRQ           25
-#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ           0x2000000
-#define BF_SSP_CTRL1_DATA_TIMEOUT_IRQ(v)        (((v) << 25) & 0x2000000)
-#define BP_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN        24
-#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN        0x1000000
-#define BF_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN(v)     (((v) << 24) & 0x1000000)
-#define BP_SSP_CTRL1_DATA_CRC_IRQ               23
-#define BM_SSP_CTRL1_DATA_CRC_IRQ               0x800000
-#define BF_SSP_CTRL1_DATA_CRC_IRQ(v)            (((v) << 23) & 0x800000)
-#define BP_SSP_CTRL1_DATA_CRC_IRQ_EN            22
-#define BM_SSP_CTRL1_DATA_CRC_IRQ_EN            0x400000
-#define BF_SSP_CTRL1_DATA_CRC_IRQ_EN(v)         (((v) << 22) & 0x400000)
-#define BP_SSP_CTRL1_FIFO_UNDERRUN_IRQ          21
-#define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ          0x200000
-#define BF_SSP_CTRL1_FIFO_UNDERRUN_IRQ(v)       (((v) << 21) & 0x200000)
-#define BP_SSP_CTRL1_FIFO_UNDERRUN_EN           20
-#define BM_SSP_CTRL1_FIFO_UNDERRUN_EN           0x100000
-#define BF_SSP_CTRL1_FIFO_UNDERRUN_EN(v)        (((v) << 20) & 0x100000)
-#define BP_SSP_CTRL1_CEATA_CCS_ERR_IRQ          19
-#define BM_SSP_CTRL1_CEATA_CCS_ERR_IRQ          0x80000
-#define BF_SSP_CTRL1_CEATA_CCS_ERR_IRQ(v)       (((v) << 19) & 0x80000)
-#define BP_SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN       18
-#define BM_SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN       0x40000
-#define BF_SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN(v)    (((v) << 18) & 0x40000)
-#define BP_SSP_CTRL1_RECV_TIMEOUT_IRQ           17
-#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ           0x20000
-#define BF_SSP_CTRL1_RECV_TIMEOUT_IRQ(v)        (((v) << 17) & 0x20000)
-#define BP_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN        16
-#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN        0x10000
-#define BF_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN(v)     (((v) << 16) & 0x10000)
-#define BP_SSP_CTRL1_FIFO_OVERRUN_IRQ           15
-#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ           0x8000
-#define BF_SSP_CTRL1_FIFO_OVERRUN_IRQ(v)        (((v) << 15) & 0x8000)
-#define BP_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN        14
-#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN        0x4000
-#define BF_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN(v)     (((v) << 14) & 0x4000)
-#define BP_SSP_CTRL1_DMA_ENABLE                 13
-#define BM_SSP_CTRL1_DMA_ENABLE                 0x2000
-#define BF_SSP_CTRL1_DMA_ENABLE(v)              (((v) << 13) & 0x2000)
-#define BP_SSP_CTRL1_CEATA_CCS_ERR_EN           12
-#define BM_SSP_CTRL1_CEATA_CCS_ERR_EN           0x1000
-#define BF_SSP_CTRL1_CEATA_CCS_ERR_EN(v)        (((v) << 12) & 0x1000)
-#define BP_SSP_CTRL1_SLAVE_OUT_DISABLE          11
-#define BM_SSP_CTRL1_SLAVE_OUT_DISABLE          0x800
-#define BF_SSP_CTRL1_SLAVE_OUT_DISABLE(v)       (((v) << 11) & 0x800)
-#define BP_SSP_CTRL1_PHASE                      10
-#define BM_SSP_CTRL1_PHASE                      0x400
-#define BF_SSP_CTRL1_PHASE(v)                   (((v) << 10) & 0x400)
-#define BP_SSP_CTRL1_POLARITY                   9
-#define BM_SSP_CTRL1_POLARITY                   0x200
-#define BF_SSP_CTRL1_POLARITY(v)                (((v) << 9) & 0x200)
-#define BP_SSP_CTRL1_SLAVE_MODE                 8
-#define BM_SSP_CTRL1_SLAVE_MODE                 0x100
-#define BF_SSP_CTRL1_SLAVE_MODE(v)              (((v) << 8) & 0x100)
-#define BP_SSP_CTRL1_WORD_LENGTH                4
-#define BM_SSP_CTRL1_WORD_LENGTH                0xf0
-#define BV_SSP_CTRL1_WORD_LENGTH__RESERVED0     0x0
-#define BV_SSP_CTRL1_WORD_LENGTH__RESERVED1     0x1
-#define BV_SSP_CTRL1_WORD_LENGTH__RESERVED2     0x2
-#define BV_SSP_CTRL1_WORD_LENGTH__FOUR_BITS     0x3
-#define BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS    0x7
-#define BV_SSP_CTRL1_WORD_LENGTH__SIXTEEN_BITS  0xf
-#define BF_SSP_CTRL1_WORD_LENGTH(v)             (((v) << 4) & 0xf0)
-#define BF_SSP_CTRL1_WORD_LENGTH_V(v)           ((BV_SSP_CTRL1_WORD_LENGTH__##v << 4) & 0xf0)
-#define BP_SSP_CTRL1_SSP_MODE                   0
-#define BM_SSP_CTRL1_SSP_MODE                   0xf
-#define BV_SSP_CTRL1_SSP_MODE__SPI              0x0
-#define BV_SSP_CTRL1_SSP_MODE__SSI              0x1
-#define BV_SSP_CTRL1_SSP_MODE__SD_MMC           0x3
-#define BV_SSP_CTRL1_SSP_MODE__MS               0x4
-#define BV_SSP_CTRL1_SSP_MODE__CE_ATA           0x7
-#define BF_SSP_CTRL1_SSP_MODE(v)                (((v) << 0) & 0xf)
-#define BF_SSP_CTRL1_SSP_MODE_V(v)              ((BV_SSP_CTRL1_SSP_MODE__##v << 0) & 0xf)
-
-/**
- * Register: HW_SSP_DATA
- * Address: 0x70
- * SCT: no
-*/
-#define HW_SSP_DATA(d)      (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x70))
-#define BP_SSP_DATA_DATA    0
-#define BM_SSP_DATA_DATA    0xffffffff
-#define BF_SSP_DATA_DATA(v) (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_SSP_SDRESP0
- * Address: 0x80
- * SCT: no
-*/
-#define HW_SSP_SDRESP0(d)       (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x80))
-#define BP_SSP_SDRESP0_RESP0    0
-#define BM_SSP_SDRESP0_RESP0    0xffffffff
-#define BF_SSP_SDRESP0_RESP0(v) (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_SSP_SDRESP1
- * Address: 0x90
- * SCT: no
-*/
-#define HW_SSP_SDRESP1(d)       (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x90))
-#define BP_SSP_SDRESP1_RESP1    0
-#define BM_SSP_SDRESP1_RESP1    0xffffffff
-#define BF_SSP_SDRESP1_RESP1(v) (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_SSP_SDRESP2
- * Address: 0xa0
- * SCT: no
-*/
-#define HW_SSP_SDRESP2(d)       (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0xa0))
-#define BP_SSP_SDRESP2_RESP2    0
-#define BM_SSP_SDRESP2_RESP2    0xffffffff
-#define BF_SSP_SDRESP2_RESP2(v) (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_SSP_SDRESP3
- * Address: 0xb0
- * SCT: no
-*/
-#define HW_SSP_SDRESP3(d)       (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0xb0))
-#define BP_SSP_SDRESP3_RESP3    0
-#define BM_SSP_SDRESP3_RESP3    0xffffffff
-#define BF_SSP_SDRESP3_RESP3(v) (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_SSP_STATUS
- * Address: 0xc0
- * SCT: no
-*/
-#define HW_SSP_STATUS(d)                    (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0xc0))
-#define BP_SSP_STATUS_PRESENT               31
-#define BM_SSP_STATUS_PRESENT               0x80000000
-#define BF_SSP_STATUS_PRESENT(v)            (((v) << 31) & 0x80000000)
-#define BP_SSP_STATUS_MS_PRESENT            30
-#define BM_SSP_STATUS_MS_PRESENT            0x40000000
-#define BF_SSP_STATUS_MS_PRESENT(v)         (((v) << 30) & 0x40000000)
-#define BP_SSP_STATUS_SD_PRESENT            29
-#define BM_SSP_STATUS_SD_PRESENT            0x20000000
-#define BF_SSP_STATUS_SD_PRESENT(v)         (((v) << 29) & 0x20000000)
-#define BP_SSP_STATUS_CARD_DETECT           28
-#define BM_SSP_STATUS_CARD_DETECT           0x10000000
-#define BF_SSP_STATUS_CARD_DETECT(v)        (((v) << 28) & 0x10000000)
-#define BP_SSP_STATUS_DMASENSE              21
-#define BM_SSP_STATUS_DMASENSE              0x200000
-#define BF_SSP_STATUS_DMASENSE(v)           (((v) << 21) & 0x200000)
-#define BP_SSP_STATUS_DMATERM               20
-#define BM_SSP_STATUS_DMATERM               0x100000
-#define BF_SSP_STATUS_DMATERM(v)            (((v) << 20) & 0x100000)
-#define BP_SSP_STATUS_DMAREQ                19
-#define BM_SSP_STATUS_DMAREQ                0x80000
-#define BF_SSP_STATUS_DMAREQ(v)             (((v) << 19) & 0x80000)
-#define BP_SSP_STATUS_DMAEND                18
-#define BM_SSP_STATUS_DMAEND                0x40000
-#define BF_SSP_STATUS_DMAEND(v)             (((v) << 18) & 0x40000)
-#define BP_SSP_STATUS_SDIO_IRQ              17
-#define BM_SSP_STATUS_SDIO_IRQ              0x20000
-#define BF_SSP_STATUS_SDIO_IRQ(v)           (((v) << 17) & 0x20000)
-#define BP_SSP_STATUS_RESP_CRC_ERR          16
-#define BM_SSP_STATUS_RESP_CRC_ERR          0x10000
-#define BF_SSP_STATUS_RESP_CRC_ERR(v)       (((v) << 16) & 0x10000)
-#define BP_SSP_STATUS_RESP_ERR              15
-#define BM_SSP_STATUS_RESP_ERR              0x8000
-#define BF_SSP_STATUS_RESP_ERR(v)           (((v) << 15) & 0x8000)
-#define BP_SSP_STATUS_RESP_TIMEOUT          14
-#define BM_SSP_STATUS_RESP_TIMEOUT          0x4000
-#define BF_SSP_STATUS_RESP_TIMEOUT(v)       (((v) << 14) & 0x4000)
-#define BP_SSP_STATUS_DATA_CRC_ERR          13
-#define BM_SSP_STATUS_DATA_CRC_ERR          0x2000
-#define BF_SSP_STATUS_DATA_CRC_ERR(v)       (((v) << 13) & 0x2000)
-#define BP_SSP_STATUS_TIMEOUT               12
-#define BM_SSP_STATUS_TIMEOUT               0x1000
-#define BF_SSP_STATUS_TIMEOUT(v)            (((v) << 12) & 0x1000)
-#define BP_SSP_STATUS_RECV_TIMEOUT_STAT     11
-#define BM_SSP_STATUS_RECV_TIMEOUT_STAT     0x800
-#define BF_SSP_STATUS_RECV_TIMEOUT_STAT(v)  (((v) << 11) & 0x800)
-#define BP_SSP_STATUS_CEATA_CCS_ERR         10
-#define BM_SSP_STATUS_CEATA_CCS_ERR         0x400
-#define BF_SSP_STATUS_CEATA_CCS_ERR(v)      (((v) << 10) & 0x400)
-#define BP_SSP_STATUS_FIFO_OVRFLW           9
-#define BM_SSP_STATUS_FIFO_OVRFLW           0x200
-#define BF_SSP_STATUS_FIFO_OVRFLW(v)        (((v) << 9) & 0x200)
-#define BP_SSP_STATUS_FIFO_FULL             8
-#define BM_SSP_STATUS_FIFO_FULL             0x100
-#define BF_SSP_STATUS_FIFO_FULL(v)          (((v) << 8) & 0x100)
-#define BP_SSP_STATUS_FIFO_EMPTY            5
-#define BM_SSP_STATUS_FIFO_EMPTY            0x20
-#define BF_SSP_STATUS_FIFO_EMPTY(v)         (((v) << 5) & 0x20)
-#define BP_SSP_STATUS_FIFO_UNDRFLW          4
-#define BM_SSP_STATUS_FIFO_UNDRFLW          0x10
-#define BF_SSP_STATUS_FIFO_UNDRFLW(v)       (((v) << 4) & 0x10)
-#define BP_SSP_STATUS_CMD_BUSY              3
-#define BM_SSP_STATUS_CMD_BUSY              0x8
-#define BF_SSP_STATUS_CMD_BUSY(v)           (((v) << 3) & 0x8)
-#define BP_SSP_STATUS_DATA_BUSY             2
-#define BM_SSP_STATUS_DATA_BUSY             0x4
-#define BF_SSP_STATUS_DATA_BUSY(v)          (((v) << 2) & 0x4)
-#define BP_SSP_STATUS_BUSY                  0
-#define BM_SSP_STATUS_BUSY                  0x1
-#define BF_SSP_STATUS_BUSY(v)               (((v) << 0) & 0x1)
-
-/**
- * Register: HW_SSP_DEBUG
- * Address: 0x100
- * SCT: no
-*/
-#define HW_SSP_DEBUG(d)                     (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x100))
-#define BP_SSP_DEBUG_DATACRC_ERR            28
-#define BM_SSP_DEBUG_DATACRC_ERR            0xf0000000
-#define BF_SSP_DEBUG_DATACRC_ERR(v)         (((v) << 28) & 0xf0000000)
-#define BP_SSP_DEBUG_DATA_STALL             27
-#define BM_SSP_DEBUG_DATA_STALL             0x8000000
-#define BF_SSP_DEBUG_DATA_STALL(v)          (((v) << 27) & 0x8000000)
-#define BP_SSP_DEBUG_DAT_SM                 24
-#define BM_SSP_DEBUG_DAT_SM                 0x7000000
-#define BV_SSP_DEBUG_DAT_SM__DSM_IDLE       0x0
-#define BV_SSP_DEBUG_DAT_SM__DSM_WORD       0x2
-#define BV_SSP_DEBUG_DAT_SM__DSM_CRC1       0x3
-#define BV_SSP_DEBUG_DAT_SM__DSM_CRC2       0x4
-#define BV_SSP_DEBUG_DAT_SM__DSM_END        0x5
-#define BF_SSP_DEBUG_DAT_SM(v)              (((v) << 24) & 0x7000000)
-#define BF_SSP_DEBUG_DAT_SM_V(v)            ((BV_SSP_DEBUG_DAT_SM__##v << 24) & 0x7000000)
-#define BP_SSP_DEBUG_MSTK_SM                20
-#define BM_SSP_DEBUG_MSTK_SM                0xf00000
-#define BV_SSP_DEBUG_MSTK_SM__MSTK_IDLE     0x0
-#define BV_SSP_DEBUG_MSTK_SM__MSTK_CKON     0x1
-#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS1      0x2
-#define BV_SSP_DEBUG_MSTK_SM__MSTK_TPC      0x3
-#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS2      0x4
-#define BV_SSP_DEBUG_MSTK_SM__MSTK_HDSHK    0x5
-#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS3      0x6
-#define BV_SSP_DEBUG_MSTK_SM__MSTK_RW       0x7
-#define BV_SSP_DEBUG_MSTK_SM__MSTK_CRC1     0x8
-#define BV_SSP_DEBUG_MSTK_SM__MSTK_CRC2     0x9
-#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS0      0xa
-#define BV_SSP_DEBUG_MSTK_SM__MSTK_END1     0xb
-#define BV_SSP_DEBUG_MSTK_SM__MSTK_END2W    0xc
-#define BV_SSP_DEBUG_MSTK_SM__MSTK_END2R    0xd
-#define BV_SSP_DEBUG_MSTK_SM__MSTK_DONE     0xe
-#define BF_SSP_DEBUG_MSTK_SM(v)             (((v) << 20) & 0xf00000)
-#define BF_SSP_DEBUG_MSTK_SM_V(v)           ((BV_SSP_DEBUG_MSTK_SM__##v << 20) & 0xf00000)
-#define BP_SSP_DEBUG_CMD_OE                 19
-#define BM_SSP_DEBUG_CMD_OE                 0x80000
-#define BF_SSP_DEBUG_CMD_OE(v)              (((v) << 19) & 0x80000)
-#define BP_SSP_DEBUG_DMA_SM                 16
-#define BM_SSP_DEBUG_DMA_SM                 0x70000
-#define BV_SSP_DEBUG_DMA_SM__DMA_IDLE       0x0
-#define BV_SSP_DEBUG_DMA_SM__DMA_DMAREQ     0x1
-#define BV_SSP_DEBUG_DMA_SM__DMA_DMAACK     0x2
-#define BV_SSP_DEBUG_DMA_SM__DMA_STALL      0x3
-#define BV_SSP_DEBUG_DMA_SM__DMA_BUSY       0x4
-#define BV_SSP_DEBUG_DMA_SM__DMA_DONE       0x5
-#define BV_SSP_DEBUG_DMA_SM__DMA_COUNT      0x6
-#define BF_SSP_DEBUG_DMA_SM(v)              (((v) << 16) & 0x70000)
-#define BF_SSP_DEBUG_DMA_SM_V(v)            ((BV_SSP_DEBUG_DMA_SM__##v << 16) & 0x70000)
-#define BP_SSP_DEBUG_MMC_SM                 12
-#define BM_SSP_DEBUG_MMC_SM                 0xf000
-#define BV_SSP_DEBUG_MMC_SM__MMC_IDLE       0x0
-#define BV_SSP_DEBUG_MMC_SM__MMC_CMD        0x1
-#define BV_SSP_DEBUG_MMC_SM__MMC_TRC        0x2
-#define BV_SSP_DEBUG_MMC_SM__MMC_RESP       0x3
-#define BV_SSP_DEBUG_MMC_SM__MMC_RPRX       0x4
-#define BV_SSP_DEBUG_MMC_SM__MMC_TX         0x5
-#define BV_SSP_DEBUG_MMC_SM__MMC_CTOK       0x6
-#define BV_SSP_DEBUG_MMC_SM__MMC_RX         0x7
-#define BV_SSP_DEBUG_MMC_SM__MMC_CCS        0x8
-#define BV_SSP_DEBUG_MMC_SM__MMC_PUP        0x9
-#define BV_SSP_DEBUG_MMC_SM__MMC_WAIT       0xa
-#define BF_SSP_DEBUG_MMC_SM(v)              (((v) << 12) & 0xf000)
-#define BF_SSP_DEBUG_MMC_SM_V(v)            ((BV_SSP_DEBUG_MMC_SM__##v << 12) & 0xf000)
-#define BP_SSP_DEBUG_CMD_SM                 10
-#define BM_SSP_DEBUG_CMD_SM                 0xc00
-#define BV_SSP_DEBUG_CMD_SM__CSM_IDLE       0x0
-#define BV_SSP_DEBUG_CMD_SM__CSM_INDEX      0x1
-#define BV_SSP_DEBUG_CMD_SM__CSM_ARG        0x2
-#define BV_SSP_DEBUG_CMD_SM__CSM_CRC        0x3
-#define BF_SSP_DEBUG_CMD_SM(v)              (((v) << 10) & 0xc00)
-#define BF_SSP_DEBUG_CMD_SM_V(v)            ((BV_SSP_DEBUG_CMD_SM__##v << 10) & 0xc00)
-#define BP_SSP_DEBUG_SSP_CMD                9
-#define BM_SSP_DEBUG_SSP_CMD                0x200
-#define BF_SSP_DEBUG_SSP_CMD(v)             (((v) << 9) & 0x200)
-#define BP_SSP_DEBUG_SSP_RESP               8
-#define BM_SSP_DEBUG_SSP_RESP               0x100
-#define BF_SSP_DEBUG_SSP_RESP(v)            (((v) << 8) & 0x100)
-#define BP_SSP_DEBUG_SSP_RXD                0
-#define BM_SSP_DEBUG_SSP_RXD                0xff
-#define BF_SSP_DEBUG_SSP_RXD(v)             (((v) << 0) & 0xff)
-
-/**
- * Register: HW_SSP_VERSION
- * Address: 0x110
- * SCT: no
-*/
-#define HW_SSP_VERSION(d)       (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x110))
-#define BP_SSP_VERSION_MAJOR    24
-#define BM_SSP_VERSION_MAJOR    0xff000000
-#define BF_SSP_VERSION_MAJOR(v) (((v) << 24) & 0xff000000)
-#define BP_SSP_VERSION_MINOR    16
-#define BM_SSP_VERSION_MINOR    0xff0000
-#define BF_SSP_VERSION_MINOR(v) (((v) << 16) & 0xff0000)
-#define BP_SSP_VERSION_STEP     0
-#define BM_SSP_VERSION_STEP     0xffff
-#define BF_SSP_VERSION_STEP(v)  (((v) << 0) & 0xffff)
-
-#endif /* __HEADERGEN__STMP3700__SSP__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-timrot.h b/firmware/target/arm/imx233/regs/stmp3700/regs-timrot.h
deleted file mode 100644
index 6861b12968..0000000000
--- a/firmware/target/arm/imx233/regs/stmp3700/regs-timrot.h
+++ /dev/null
@@ -1,283 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3700:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__STMP3700__TIMROT__H__
-#define __HEADERGEN__STMP3700__TIMROT__H__
-
-#define REGS_TIMROT_BASE (0x80068000)
-
-#define REGS_TIMROT_VERSION "3.2.0"
-
-/**
- * Register: HW_TIMROT_ROTCTRL
- * Address: 0
- * SCT: yes
-*/
-#define HW_TIMROT_ROTCTRL                       (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x0 + 0x0))
-#define HW_TIMROT_ROTCTRL_SET                   (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x0 + 0x4))
-#define HW_TIMROT_ROTCTRL_CLR                   (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x0 + 0x8))
-#define HW_TIMROT_ROTCTRL_TOG                   (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x0 + 0xc))
-#define BP_TIMROT_ROTCTRL_SFTRST                31
-#define BM_TIMROT_ROTCTRL_SFTRST                0x80000000
-#define BF_TIMROT_ROTCTRL_SFTRST(v)             (((v) << 31) & 0x80000000)
-#define BP_TIMROT_ROTCTRL_CLKGATE               30
-#define BM_TIMROT_ROTCTRL_CLKGATE               0x40000000
-#define BF_TIMROT_ROTCTRL_CLKGATE(v)            (((v) << 30) & 0x40000000)
-#define BP_TIMROT_ROTCTRL_ROTARY_PRESENT        29
-#define BM_TIMROT_ROTCTRL_ROTARY_PRESENT        0x20000000
-#define BF_TIMROT_ROTCTRL_ROTARY_PRESENT(v)     (((v) << 29) & 0x20000000)
-#define BP_TIMROT_ROTCTRL_TIM3_PRESENT          28
-#define BM_TIMROT_ROTCTRL_TIM3_PRESENT          0x10000000
-#define BF_TIMROT_ROTCTRL_TIM3_PRESENT(v)       (((v) << 28) & 0x10000000)
-#define BP_TIMROT_ROTCTRL_TIM2_PRESENT          27
-#define BM_TIMROT_ROTCTRL_TIM2_PRESENT          0x8000000
-#define BF_TIMROT_ROTCTRL_TIM2_PRESENT(v)       (((v) << 27) & 0x8000000)
-#define BP_TIMROT_ROTCTRL_TIM1_PRESENT          26
-#define BM_TIMROT_ROTCTRL_TIM1_PRESENT          0x4000000
-#define BF_TIMROT_ROTCTRL_TIM1_PRESENT(v)       (((v) << 26) & 0x4000000)
-#define BP_TIMROT_ROTCTRL_TIM0_PRESENT          25
-#define BM_TIMROT_ROTCTRL_TIM0_PRESENT          0x2000000
-#define BF_TIMROT_ROTCTRL_TIM0_PRESENT(v)       (((v) << 25) & 0x2000000)
-#define BP_TIMROT_ROTCTRL_STATE                 22
-#define BM_TIMROT_ROTCTRL_STATE                 0x1c00000
-#define BF_TIMROT_ROTCTRL_STATE(v)              (((v) << 22) & 0x1c00000)
-#define BP_TIMROT_ROTCTRL_DIVIDER               16
-#define BM_TIMROT_ROTCTRL_DIVIDER               0x3f0000
-#define BF_TIMROT_ROTCTRL_DIVIDER(v)            (((v) << 16) & 0x3f0000)
-#define BP_TIMROT_ROTCTRL_RELATIVE              12
-#define BM_TIMROT_ROTCTRL_RELATIVE              0x1000
-#define BF_TIMROT_ROTCTRL_RELATIVE(v)           (((v) << 12) & 0x1000)
-#define BP_TIMROT_ROTCTRL_OVERSAMPLE            10
-#define BM_TIMROT_ROTCTRL_OVERSAMPLE            0xc00
-#define BV_TIMROT_ROTCTRL_OVERSAMPLE__8X        0x0
-#define BV_TIMROT_ROTCTRL_OVERSAMPLE__4X        0x1
-#define BV_TIMROT_ROTCTRL_OVERSAMPLE__2X        0x2
-#define BV_TIMROT_ROTCTRL_OVERSAMPLE__1X        0x3
-#define BF_TIMROT_ROTCTRL_OVERSAMPLE(v)         (((v) << 10) & 0xc00)
-#define BF_TIMROT_ROTCTRL_OVERSAMPLE_V(v)       ((BV_TIMROT_ROTCTRL_OVERSAMPLE__##v << 10) & 0xc00)
-#define BP_TIMROT_ROTCTRL_POLARITY_B            9
-#define BM_TIMROT_ROTCTRL_POLARITY_B            0x200
-#define BF_TIMROT_ROTCTRL_POLARITY_B(v)         (((v) << 9) & 0x200)
-#define BP_TIMROT_ROTCTRL_POLARITY_A            8
-#define BM_TIMROT_ROTCTRL_POLARITY_A            0x100
-#define BF_TIMROT_ROTCTRL_POLARITY_A(v)         (((v) << 8) & 0x100)
-#define BP_TIMROT_ROTCTRL_SELECT_B              4
-#define BM_TIMROT_ROTCTRL_SELECT_B              0x70
-#define BV_TIMROT_ROTCTRL_SELECT_B__NEVER_TICK  0x0
-#define BV_TIMROT_ROTCTRL_SELECT_B__PWM0        0x1
-#define BV_TIMROT_ROTCTRL_SELECT_B__PWM1        0x2
-#define BV_TIMROT_ROTCTRL_SELECT_B__PWM2        0x3
-#define BV_TIMROT_ROTCTRL_SELECT_B__PWM3        0x4
-#define BV_TIMROT_ROTCTRL_SELECT_B__PWM4        0x5
-#define BV_TIMROT_ROTCTRL_SELECT_B__ROTARYA     0x6
-#define BV_TIMROT_ROTCTRL_SELECT_B__ROTARYB     0x7
-#define BF_TIMROT_ROTCTRL_SELECT_B(v)           (((v) << 4) & 0x70)
-#define BF_TIMROT_ROTCTRL_SELECT_B_V(v)         ((BV_TIMROT_ROTCTRL_SELECT_B__##v << 4) & 0x70)
-#define BP_TIMROT_ROTCTRL_SELECT_A              0
-#define BM_TIMROT_ROTCTRL_SELECT_A              0x7
-#define BV_TIMROT_ROTCTRL_SELECT_A__NEVER_TICK  0x0
-#define BV_TIMROT_ROTCTRL_SELECT_A__PWM0        0x1
-#define BV_TIMROT_ROTCTRL_SELECT_A__PWM1        0x2
-#define BV_TIMROT_ROTCTRL_SELECT_A__PWM2        0x3
-#define BV_TIMROT_ROTCTRL_SELECT_A__PWM3        0x4
-#define BV_TIMROT_ROTCTRL_SELECT_A__PWM4        0x5
-#define BV_TIMROT_ROTCTRL_SELECT_A__ROTARYA     0x6
-#define BV_TIMROT_ROTCTRL_SELECT_A__ROTARYB     0x7
-#define BF_TIMROT_ROTCTRL_SELECT_A(v)           (((v) << 0) & 0x7)
-#define BF_TIMROT_ROTCTRL_SELECT_A_V(v)         ((BV_TIMROT_ROTCTRL_SELECT_A__##v << 0) & 0x7)
-
-/**
- * Register: HW_TIMROT_ROTCOUNT
- * Address: 0x10
- * SCT: no
-*/
-#define HW_TIMROT_ROTCOUNT              (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x10))
-#define BP_TIMROT_ROTCOUNT_UPDOWN       0
-#define BM_TIMROT_ROTCOUNT_UPDOWN       0xffff
-#define BF_TIMROT_ROTCOUNT_UPDOWN(v)    (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_TIMROT_TIMCTRLn
- * Address: 0x20+n*0x20
- * SCT: yes
-*/
-#define HW_TIMROT_TIMCTRLn(n)                   (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x20+(n)*0x20 + 0x0))
-#define HW_TIMROT_TIMCTRLn_SET(n)               (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x20+(n)*0x20 + 0x4))
-#define HW_TIMROT_TIMCTRLn_CLR(n)               (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x20+(n)*0x20 + 0x8))
-#define HW_TIMROT_TIMCTRLn_TOG(n)               (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x20+(n)*0x20 + 0xc))
-#define BP_TIMROT_TIMCTRLn_IRQ                  15
-#define BM_TIMROT_TIMCTRLn_IRQ                  0x8000
-#define BF_TIMROT_TIMCTRLn_IRQ(v)               (((v) << 15) & 0x8000)
-#define BP_TIMROT_TIMCTRLn_IRQ_EN               14
-#define BM_TIMROT_TIMCTRLn_IRQ_EN               0x4000
-#define BF_TIMROT_TIMCTRLn_IRQ_EN(v)            (((v) << 14) & 0x4000)
-#define BP_TIMROT_TIMCTRLn_POLARITY             8
-#define BM_TIMROT_TIMCTRLn_POLARITY             0x100
-#define BF_TIMROT_TIMCTRLn_POLARITY(v)          (((v) << 8) & 0x100)
-#define BP_TIMROT_TIMCTRLn_UPDATE               7
-#define BM_TIMROT_TIMCTRLn_UPDATE               0x80
-#define BF_TIMROT_TIMCTRLn_UPDATE(v)            (((v) << 7) & 0x80)
-#define BP_TIMROT_TIMCTRLn_RELOAD               6
-#define BM_TIMROT_TIMCTRLn_RELOAD               0x40
-#define BF_TIMROT_TIMCTRLn_RELOAD(v)            (((v) << 6) & 0x40)
-#define BP_TIMROT_TIMCTRLn_PRESCALE             4
-#define BM_TIMROT_TIMCTRLn_PRESCALE             0x30
-#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_1   0x0
-#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_2   0x1
-#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_4   0x2
-#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_8   0x3
-#define BF_TIMROT_TIMCTRLn_PRESCALE(v)          (((v) << 4) & 0x30)
-#define BF_TIMROT_TIMCTRLn_PRESCALE_V(v)        ((BV_TIMROT_TIMCTRLn_PRESCALE__##v << 4) & 0x30)
-#define BP_TIMROT_TIMCTRLn_SELECT               0
-#define BM_TIMROT_TIMCTRLn_SELECT               0xf
-#define BV_TIMROT_TIMCTRLn_SELECT__NEVER_TICK   0x0
-#define BV_TIMROT_TIMCTRLn_SELECT__PWM0         0x1
-#define BV_TIMROT_TIMCTRLn_SELECT__PWM1         0x2
-#define BV_TIMROT_TIMCTRLn_SELECT__PWM2         0x3
-#define BV_TIMROT_TIMCTRLn_SELECT__PWM3         0x4
-#define BV_TIMROT_TIMCTRLn_SELECT__PWM4         0x5
-#define BV_TIMROT_TIMCTRLn_SELECT__ROTARYA      0x6
-#define BV_TIMROT_TIMCTRLn_SELECT__ROTARYB      0x7
-#define BV_TIMROT_TIMCTRLn_SELECT__32KHZ_XTAL   0x8
-#define BV_TIMROT_TIMCTRLn_SELECT__8KHZ_XTAL    0x9
-#define BV_TIMROT_TIMCTRLn_SELECT__4KHZ_XTAL    0xa
-#define BV_TIMROT_TIMCTRLn_SELECT__1KHZ_XTAL    0xb
-#define BV_TIMROT_TIMCTRLn_SELECT__TICK_ALWAYS  0xc
-#define BF_TIMROT_TIMCTRLn_SELECT(v)            (((v) << 0) & 0xf)
-#define BF_TIMROT_TIMCTRLn_SELECT_V(v)          ((BV_TIMROT_TIMCTRLn_SELECT__##v << 0) & 0xf)
-
-/**
- * Register: HW_TIMROT_TIMCOUNTn
- * Address: 0x30+n*0x20
- * SCT: no
-*/
-#define HW_TIMROT_TIMCOUNTn(n)                  (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x30+(n)*0x20))
-#define BP_TIMROT_TIMCOUNTn_RUNNING_COUNT       16
-#define BM_TIMROT_TIMCOUNTn_RUNNING_COUNT       0xffff0000
-#define BF_TIMROT_TIMCOUNTn_RUNNING_COUNT(v)    (((v) << 16) & 0xffff0000)
-#define BP_TIMROT_TIMCOUNTn_FIXED_COUNT         0
-#define BM_TIMROT_TIMCOUNTn_FIXED_COUNT         0xffff
-#define BF_TIMROT_TIMCOUNTn_FIXED_COUNT(v)      (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_TIMROT_TIMCTRL3
- * Address: 0x80
- * SCT: yes
-*/
-#define HW_TIMROT_TIMCTRL3                          (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x80 + 0x0))
-#define HW_TIMROT_TIMCTRL3_SET                      (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x80 + 0x4))
-#define HW_TIMROT_TIMCTRL3_CLR                      (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x80 + 0x8))
-#define HW_TIMROT_TIMCTRL3_TOG                      (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x80 + 0xc))
-#define BP_TIMROT_TIMCTRL3_TEST_SIGNAL              16
-#define BM_TIMROT_TIMCTRL3_TEST_SIGNAL              0xf0000
-#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__NEVER_TICK  0x0
-#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM0        0x1
-#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM1        0x2
-#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM2        0x3
-#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM3        0x4
-#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM4        0x5
-#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__ROTARYA     0x6
-#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__ROTARYB     0x7
-#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__32KHZ_XTAL  0x8
-#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__8KHZ_XTAL   0x9
-#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__4KHZ_XTAL   0xa
-#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__1KHZ_XTAL   0xb
-#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__TICK_ALWAYS 0xc
-#define BF_TIMROT_TIMCTRL3_TEST_SIGNAL(v)           (((v) << 16) & 0xf0000)
-#define BF_TIMROT_TIMCTRL3_TEST_SIGNAL_V(v)         ((BV_TIMROT_TIMCTRL3_TEST_SIGNAL__##v << 16) & 0xf0000)
-#define BP_TIMROT_TIMCTRL3_IRQ                      15
-#define BM_TIMROT_TIMCTRL3_IRQ                      0x8000
-#define BF_TIMROT_TIMCTRL3_IRQ(v)                   (((v) << 15) & 0x8000)
-#define BP_TIMROT_TIMCTRL3_IRQ_EN                   14
-#define BM_TIMROT_TIMCTRL3_IRQ_EN                   0x4000
-#define BF_TIMROT_TIMCTRL3_IRQ_EN(v)                (((v) << 14) & 0x4000)
-#define BP_TIMROT_TIMCTRL3_DUTY_VALID               10
-#define BM_TIMROT_TIMCTRL3_DUTY_VALID               0x400
-#define BF_TIMROT_TIMCTRL3_DUTY_VALID(v)            (((v) << 10) & 0x400)
-#define BP_TIMROT_TIMCTRL3_DUTY_CYCLE               9
-#define BM_TIMROT_TIMCTRL3_DUTY_CYCLE               0x200
-#define BF_TIMROT_TIMCTRL3_DUTY_CYCLE(v)            (((v) << 9) & 0x200)
-#define BP_TIMROT_TIMCTRL3_POLARITY                 8
-#define BM_TIMROT_TIMCTRL3_POLARITY                 0x100
-#define BF_TIMROT_TIMCTRL3_POLARITY(v)              (((v) << 8) & 0x100)
-#define BP_TIMROT_TIMCTRL3_UPDATE                   7
-#define BM_TIMROT_TIMCTRL3_UPDATE                   0x80
-#define BF_TIMROT_TIMCTRL3_UPDATE(v)                (((v) << 7) & 0x80)
-#define BP_TIMROT_TIMCTRL3_RELOAD                   6
-#define BM_TIMROT_TIMCTRL3_RELOAD                   0x40
-#define BF_TIMROT_TIMCTRL3_RELOAD(v)                (((v) << 6) & 0x40)
-#define BP_TIMROT_TIMCTRL3_PRESCALE                 4
-#define BM_TIMROT_TIMCTRL3_PRESCALE                 0x30
-#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_1       0x0
-#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_2       0x1
-#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_4       0x2
-#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_8       0x3
-#define BF_TIMROT_TIMCTRL3_PRESCALE(v)              (((v) << 4) & 0x30)
-#define BF_TIMROT_TIMCTRL3_PRESCALE_V(v)            ((BV_TIMROT_TIMCTRL3_PRESCALE__##v << 4) & 0x30)
-#define BP_TIMROT_TIMCTRL3_SELECT                   0
-#define BM_TIMROT_TIMCTRL3_SELECT                   0xf
-#define BV_TIMROT_TIMCTRL3_SELECT__NEVER_TICK       0x0
-#define BV_TIMROT_TIMCTRL3_SELECT__PWM0             0x1
-#define BV_TIMROT_TIMCTRL3_SELECT__PWM1             0x2
-#define BV_TIMROT_TIMCTRL3_SELECT__PWM2             0x3
-#define BV_TIMROT_TIMCTRL3_SELECT__PWM3             0x4
-#define BV_TIMROT_TIMCTRL3_SELECT__PWM4             0x5
-#define BV_TIMROT_TIMCTRL3_SELECT__ROTARYA          0x6
-#define BV_TIMROT_TIMCTRL3_SELECT__ROTARYB          0x7
-#define BV_TIMROT_TIMCTRL3_SELECT__32KHZ_XTAL       0x8
-#define BV_TIMROT_TIMCTRL3_SELECT__8KHZ_XTAL        0x9
-#define BV_TIMROT_TIMCTRL3_SELECT__4KHZ_XTAL        0xa
-#define BV_TIMROT_TIMCTRL3_SELECT__1KHZ_XTAL        0xb
-#define BV_TIMROT_TIMCTRL3_SELECT__TICK_ALWAYS      0xc
-#define BF_TIMROT_TIMCTRL3_SELECT(v)                (((v) << 0) & 0xf)
-#define BF_TIMROT_TIMCTRL3_SELECT_V(v)              ((BV_TIMROT_TIMCTRL3_SELECT__##v << 0) & 0xf)
-
-/**
- * Register: HW_TIMROT_TIMCOUNT3
- * Address: 0x90
- * SCT: no
-*/
-#define HW_TIMROT_TIMCOUNT3                         (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x90))
-#define BP_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT       16
-#define BM_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT       0xffff0000
-#define BF_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT(v)    (((v) << 16) & 0xffff0000)
-#define BP_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT        0
-#define BM_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT        0xffff
-#define BF_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT(v)     (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_TIMROT_VERSION
- * Address: 0xa0
- * SCT: no
-*/
-#define HW_TIMROT_VERSION           (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0xa0))
-#define BP_TIMROT_VERSION_MAJOR     24
-#define BM_TIMROT_VERSION_MAJOR     0xff000000
-#define BF_TIMROT_VERSION_MAJOR(v)  (((v) << 24) & 0xff000000)
-#define BP_TIMROT_VERSION_MINOR     16
-#define BM_TIMROT_VERSION_MINOR     0xff0000
-#define BF_TIMROT_VERSION_MINOR(v)  (((v) << 16) & 0xff0000)
-#define BP_TIMROT_VERSION_STEP      0
-#define BM_TIMROT_VERSION_STEP      0xffff
-#define BF_TIMROT_VERSION_STEP(v)   (((v) << 0) & 0xffff)
-
-#endif /* __HEADERGEN__STMP3700__TIMROT__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-uartapp.h b/firmware/target/arm/imx233/regs/stmp3700/regs-uartapp.h
deleted file mode 100644
index 0bae54dcfd..0000000000
--- a/firmware/target/arm/imx233/regs/stmp3700/regs-uartapp.h
+++ /dev/null
@@ -1,427 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3700:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__STMP3700__UARTAPP__H__
-#define __HEADERGEN__STMP3700__UARTAPP__H__
-
-#define REGS_UARTAPP_BASE(i) ((i) == 1 ? 0x8006c000 : 0x8006e000)
-
-#define REGS_UARTAPP_VERSION "3.2.0"
-
-/**
- * Register: HW_UARTAPP_CTRL0
- * Address: 0
- * SCT: yes
-*/
-#define HW_UARTAPP_CTRL0(d)             (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x0 + 0x0))
-#define HW_UARTAPP_CTRL0_SET(d)         (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x0 + 0x4))
-#define HW_UARTAPP_CTRL0_CLR(d)         (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x0 + 0x8))
-#define HW_UARTAPP_CTRL0_TOG(d)         (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x0 + 0xc))
-#define BP_UARTAPP_CTRL0_SFTRST         31
-#define BM_UARTAPP_CTRL0_SFTRST         0x80000000
-#define BF_UARTAPP_CTRL0_SFTRST(v)      (((v) << 31) & 0x80000000)
-#define BP_UARTAPP_CTRL0_CLKGATE        30
-#define BM_UARTAPP_CTRL0_CLKGATE        0x40000000
-#define BF_UARTAPP_CTRL0_CLKGATE(v)     (((v) << 30) & 0x40000000)
-#define BP_UARTAPP_CTRL0_RUN            29
-#define BM_UARTAPP_CTRL0_RUN            0x20000000
-#define BF_UARTAPP_CTRL0_RUN(v)         (((v) << 29) & 0x20000000)
-#define BP_UARTAPP_CTRL0_RX_SOURCE      28
-#define BM_UARTAPP_CTRL0_RX_SOURCE      0x10000000
-#define BF_UARTAPP_CTRL0_RX_SOURCE(v)   (((v) << 28) & 0x10000000)
-#define BP_UARTAPP_CTRL0_RXTO_ENABLE    27
-#define BM_UARTAPP_CTRL0_RXTO_ENABLE    0x8000000
-#define BF_UARTAPP_CTRL0_RXTO_ENABLE(v) (((v) << 27) & 0x8000000)
-#define BP_UARTAPP_CTRL0_RXTIMEOUT      16
-#define BM_UARTAPP_CTRL0_RXTIMEOUT      0x7ff0000
-#define BF_UARTAPP_CTRL0_RXTIMEOUT(v)   (((v) << 16) & 0x7ff0000)
-#define BP_UARTAPP_CTRL0_XFER_COUNT     0
-#define BM_UARTAPP_CTRL0_XFER_COUNT     0xffff
-#define BF_UARTAPP_CTRL0_XFER_COUNT(v)  (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_UARTAPP_CTRL1
- * Address: 0x10
- * SCT: yes
-*/
-#define HW_UARTAPP_CTRL1(d)             (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x10 + 0x0))
-#define HW_UARTAPP_CTRL1_SET(d)         (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x10 + 0x4))
-#define HW_UARTAPP_CTRL1_CLR(d)         (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x10 + 0x8))
-#define HW_UARTAPP_CTRL1_TOG(d)         (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x10 + 0xc))
-#define BP_UARTAPP_CTRL1_RUN            28
-#define BM_UARTAPP_CTRL1_RUN            0x10000000
-#define BF_UARTAPP_CTRL1_RUN(v)         (((v) << 28) & 0x10000000)
-#define BP_UARTAPP_CTRL1_XFER_COUNT     0
-#define BM_UARTAPP_CTRL1_XFER_COUNT     0xffff
-#define BF_UARTAPP_CTRL1_XFER_COUNT(v)  (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_UARTAPP_CTRL2
- * Address: 0x20
- * SCT: yes
-*/
-#define HW_UARTAPP_CTRL2(d)                         (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x20 + 0x0))
-#define HW_UARTAPP_CTRL2_SET(d)                     (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x20 + 0x4))
-#define HW_UARTAPP_CTRL2_CLR(d)                     (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x20 + 0x8))
-#define HW_UARTAPP_CTRL2_TOG(d)                     (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x20 + 0xc))
-#define BP_UARTAPP_CTRL2_INVERT_RTS                 31
-#define BM_UARTAPP_CTRL2_INVERT_RTS                 0x80000000
-#define BF_UARTAPP_CTRL2_INVERT_RTS(v)              (((v) << 31) & 0x80000000)
-#define BP_UARTAPP_CTRL2_INVERT_CTS                 30
-#define BM_UARTAPP_CTRL2_INVERT_CTS                 0x40000000
-#define BF_UARTAPP_CTRL2_INVERT_CTS(v)              (((v) << 30) & 0x40000000)
-#define BP_UARTAPP_CTRL2_INVERT_TX                  29
-#define BM_UARTAPP_CTRL2_INVERT_TX                  0x20000000
-#define BF_UARTAPP_CTRL2_INVERT_TX(v)               (((v) << 29) & 0x20000000)
-#define BP_UARTAPP_CTRL2_INVERT_RX                  28
-#define BM_UARTAPP_CTRL2_INVERT_RX                  0x10000000
-#define BF_UARTAPP_CTRL2_INVERT_RX(v)               (((v) << 28) & 0x10000000)
-#define BP_UARTAPP_CTRL2_RTS_SEMAPHORE              27
-#define BM_UARTAPP_CTRL2_RTS_SEMAPHORE              0x8000000
-#define BF_UARTAPP_CTRL2_RTS_SEMAPHORE(v)           (((v) << 27) & 0x8000000)
-#define BP_UARTAPP_CTRL2_DMAONERR                   26
-#define BM_UARTAPP_CTRL2_DMAONERR                   0x4000000
-#define BF_UARTAPP_CTRL2_DMAONERR(v)                (((v) << 26) & 0x4000000)
-#define BP_UARTAPP_CTRL2_TXDMAE                     25
-#define BM_UARTAPP_CTRL2_TXDMAE                     0x2000000
-#define BF_UARTAPP_CTRL2_TXDMAE(v)                  (((v) << 25) & 0x2000000)
-#define BP_UARTAPP_CTRL2_RXDMAE                     24
-#define BM_UARTAPP_CTRL2_RXDMAE                     0x1000000
-#define BF_UARTAPP_CTRL2_RXDMAE(v)                  (((v) << 24) & 0x1000000)
-#define BP_UARTAPP_CTRL2_RXIFLSEL                   20
-#define BM_UARTAPP_CTRL2_RXIFLSEL                   0x700000
-#define BV_UARTAPP_CTRL2_RXIFLSEL__NOT_EMPTY        0x0
-#define BV_UARTAPP_CTRL2_RXIFLSEL__ONE_QUARTER      0x1
-#define BV_UARTAPP_CTRL2_RXIFLSEL__ONE_HALF         0x2
-#define BV_UARTAPP_CTRL2_RXIFLSEL__THREE_QUARTERS   0x3
-#define BV_UARTAPP_CTRL2_RXIFLSEL__SEVEN_EIGHTHS    0x4
-#define BV_UARTAPP_CTRL2_RXIFLSEL__INVALID5         0x5
-#define BV_UARTAPP_CTRL2_RXIFLSEL__INVALID6         0x6
-#define BV_UARTAPP_CTRL2_RXIFLSEL__INVALID7         0x7
-#define BF_UARTAPP_CTRL2_RXIFLSEL(v)                (((v) << 20) & 0x700000)
-#define BF_UARTAPP_CTRL2_RXIFLSEL_V(v)              ((BV_UARTAPP_CTRL2_RXIFLSEL__##v << 20) & 0x700000)
-#define BP_UARTAPP_CTRL2_TXIFLSEL                   16
-#define BM_UARTAPP_CTRL2_TXIFLSEL                   0x70000
-#define BV_UARTAPP_CTRL2_TXIFLSEL__EMPTY            0x0
-#define BV_UARTAPP_CTRL2_TXIFLSEL__ONE_QUARTER      0x1
-#define BV_UARTAPP_CTRL2_TXIFLSEL__ONE_HALF         0x2
-#define BV_UARTAPP_CTRL2_TXIFLSEL__THREE_QUARTERS   0x3
-#define BV_UARTAPP_CTRL2_TXIFLSEL__SEVEN_EIGHTHS    0x4
-#define BV_UARTAPP_CTRL2_TXIFLSEL__INVALID5         0x5
-#define BV_UARTAPP_CTRL2_TXIFLSEL__INVALID6         0x6
-#define BV_UARTAPP_CTRL2_TXIFLSEL__INVALID7         0x7
-#define BF_UARTAPP_CTRL2_TXIFLSEL(v)                (((v) << 16) & 0x70000)
-#define BF_UARTAPP_CTRL2_TXIFLSEL_V(v)              ((BV_UARTAPP_CTRL2_TXIFLSEL__##v << 16) & 0x70000)
-#define BP_UARTAPP_CTRL2_CTSEN                      15
-#define BM_UARTAPP_CTRL2_CTSEN                      0x8000
-#define BF_UARTAPP_CTRL2_CTSEN(v)                   (((v) << 15) & 0x8000)
-#define BP_UARTAPP_CTRL2_RTSEN                      14
-#define BM_UARTAPP_CTRL2_RTSEN                      0x4000
-#define BF_UARTAPP_CTRL2_RTSEN(v)                   (((v) << 14) & 0x4000)
-#define BP_UARTAPP_CTRL2_OUT2                       13
-#define BM_UARTAPP_CTRL2_OUT2                       0x2000
-#define BF_UARTAPP_CTRL2_OUT2(v)                    (((v) << 13) & 0x2000)
-#define BP_UARTAPP_CTRL2_OUT1                       12
-#define BM_UARTAPP_CTRL2_OUT1                       0x1000
-#define BF_UARTAPP_CTRL2_OUT1(v)                    (((v) << 12) & 0x1000)
-#define BP_UARTAPP_CTRL2_RTS                        11
-#define BM_UARTAPP_CTRL2_RTS                        0x800
-#define BF_UARTAPP_CTRL2_RTS(v)                     (((v) << 11) & 0x800)
-#define BP_UARTAPP_CTRL2_DTR                        10
-#define BM_UARTAPP_CTRL2_DTR                        0x400
-#define BF_UARTAPP_CTRL2_DTR(v)                     (((v) << 10) & 0x400)
-#define BP_UARTAPP_CTRL2_RXE                        9
-#define BM_UARTAPP_CTRL2_RXE                        0x200
-#define BF_UARTAPP_CTRL2_RXE(v)                     (((v) << 9) & 0x200)
-#define BP_UARTAPP_CTRL2_TXE                        8
-#define BM_UARTAPP_CTRL2_TXE                        0x100
-#define BF_UARTAPP_CTRL2_TXE(v)                     (((v) << 8) & 0x100)
-#define BP_UARTAPP_CTRL2_LBE                        7
-#define BM_UARTAPP_CTRL2_LBE                        0x80
-#define BF_UARTAPP_CTRL2_LBE(v)                     (((v) << 7) & 0x80)
-#define BP_UARTAPP_CTRL2_USE_LCR2                   6
-#define BM_UARTAPP_CTRL2_USE_LCR2                   0x40
-#define BF_UARTAPP_CTRL2_USE_LCR2(v)                (((v) << 6) & 0x40)
-#define BP_UARTAPP_CTRL2_SIRLP                      2
-#define BM_UARTAPP_CTRL2_SIRLP                      0x4
-#define BF_UARTAPP_CTRL2_SIRLP(v)                   (((v) << 2) & 0x4)
-#define BP_UARTAPP_CTRL2_SIREN                      1
-#define BM_UARTAPP_CTRL2_SIREN                      0x2
-#define BF_UARTAPP_CTRL2_SIREN(v)                   (((v) << 1) & 0x2)
-#define BP_UARTAPP_CTRL2_UARTEN                     0
-#define BM_UARTAPP_CTRL2_UARTEN                     0x1
-#define BF_UARTAPP_CTRL2_UARTEN(v)                  (((v) << 0) & 0x1)
-
-/**
- * Register: HW_UARTAPP_LINECTRL
- * Address: 0x30
- * SCT: yes
-*/
-#define HW_UARTAPP_LINECTRL(d)              (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x30 + 0x0))
-#define HW_UARTAPP_LINECTRL_SET(d)          (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x30 + 0x4))
-#define HW_UARTAPP_LINECTRL_CLR(d)          (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x30 + 0x8))
-#define HW_UARTAPP_LINECTRL_TOG(d)          (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x30 + 0xc))
-#define BP_UARTAPP_LINECTRL_BAUD_DIVINT     16
-#define BM_UARTAPP_LINECTRL_BAUD_DIVINT     0xffff0000
-#define BF_UARTAPP_LINECTRL_BAUD_DIVINT(v)  (((v) << 16) & 0xffff0000)
-#define BP_UARTAPP_LINECTRL_BAUD_DIVFRAC    8
-#define BM_UARTAPP_LINECTRL_BAUD_DIVFRAC    0x3f00
-#define BF_UARTAPP_LINECTRL_BAUD_DIVFRAC(v) (((v) << 8) & 0x3f00)
-#define BP_UARTAPP_LINECTRL_SPS             7
-#define BM_UARTAPP_LINECTRL_SPS             0x80
-#define BF_UARTAPP_LINECTRL_SPS(v)          (((v) << 7) & 0x80)
-#define BP_UARTAPP_LINECTRL_WLEN            5
-#define BM_UARTAPP_LINECTRL_WLEN            0x60
-#define BF_UARTAPP_LINECTRL_WLEN(v)         (((v) << 5) & 0x60)
-#define BP_UARTAPP_LINECTRL_FEN             4
-#define BM_UARTAPP_LINECTRL_FEN             0x10
-#define BF_UARTAPP_LINECTRL_FEN(v)          (((v) << 4) & 0x10)
-#define BP_UARTAPP_LINECTRL_STP2            3
-#define BM_UARTAPP_LINECTRL_STP2            0x8
-#define BF_UARTAPP_LINECTRL_STP2(v)         (((v) << 3) & 0x8)
-#define BP_UARTAPP_LINECTRL_EPS             2
-#define BM_UARTAPP_LINECTRL_EPS             0x4
-#define BF_UARTAPP_LINECTRL_EPS(v)          (((v) << 2) & 0x4)
-#define BP_UARTAPP_LINECTRL_PEN             1
-#define BM_UARTAPP_LINECTRL_PEN             0x2
-#define BF_UARTAPP_LINECTRL_PEN(v)          (((v) << 1) & 0x2)
-#define BP_UARTAPP_LINECTRL_BRK             0
-#define BM_UARTAPP_LINECTRL_BRK             0x1
-#define BF_UARTAPP_LINECTRL_BRK(v)          (((v) << 0) & 0x1)
-
-/**
- * Register: HW_UARTAPP_LINECTRL2
- * Address: 0x40
- * SCT: yes
-*/
-#define HW_UARTAPP_LINECTRL2(d)                 (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x40 + 0x0))
-#define HW_UARTAPP_LINECTRL2_SET(d)             (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x40 + 0x4))
-#define HW_UARTAPP_LINECTRL2_CLR(d)             (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x40 + 0x8))
-#define HW_UARTAPP_LINECTRL2_TOG(d)             (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x40 + 0xc))
-#define BP_UARTAPP_LINECTRL2_BAUD_DIVINT        16
-#define BM_UARTAPP_LINECTRL2_BAUD_DIVINT        0xffff0000
-#define BF_UARTAPP_LINECTRL2_BAUD_DIVINT(v)     (((v) << 16) & 0xffff0000)
-#define BP_UARTAPP_LINECTRL2_BAUD_DIVFRAC       8
-#define BM_UARTAPP_LINECTRL2_BAUD_DIVFRAC       0x3f00
-#define BF_UARTAPP_LINECTRL2_BAUD_DIVFRAC(v)    (((v) << 8) & 0x3f00)
-#define BP_UARTAPP_LINECTRL2_SPS                7
-#define BM_UARTAPP_LINECTRL2_SPS                0x80
-#define BF_UARTAPP_LINECTRL2_SPS(v)             (((v) << 7) & 0x80)
-#define BP_UARTAPP_LINECTRL2_WLEN               5
-#define BM_UARTAPP_LINECTRL2_WLEN               0x60
-#define BF_UARTAPP_LINECTRL2_WLEN(v)            (((v) << 5) & 0x60)
-#define BP_UARTAPP_LINECTRL2_FEN                4
-#define BM_UARTAPP_LINECTRL2_FEN                0x10
-#define BF_UARTAPP_LINECTRL2_FEN(v)             (((v) << 4) & 0x10)
-#define BP_UARTAPP_LINECTRL2_STP2               3
-#define BM_UARTAPP_LINECTRL2_STP2               0x8
-#define BF_UARTAPP_LINECTRL2_STP2(v)            (((v) << 3) & 0x8)
-#define BP_UARTAPP_LINECTRL2_EPS                2
-#define BM_UARTAPP_LINECTRL2_EPS                0x4
-#define BF_UARTAPP_LINECTRL2_EPS(v)             (((v) << 2) & 0x4)
-#define BP_UARTAPP_LINECTRL2_PEN                1
-#define BM_UARTAPP_LINECTRL2_PEN                0x2
-#define BF_UARTAPP_LINECTRL2_PEN(v)             (((v) << 1) & 0x2)
-
-/**
- * Register: HW_UARTAPP_INTR
- * Address: 0x50
- * SCT: yes
-*/
-#define HW_UARTAPP_INTR(d)          (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x50 + 0x0))
-#define HW_UARTAPP_INTR_SET(d)      (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x50 + 0x4))
-#define HW_UARTAPP_INTR_CLR(d)      (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x50 + 0x8))
-#define HW_UARTAPP_INTR_TOG(d)      (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x50 + 0xc))
-#define BP_UARTAPP_INTR_OEIEN       26
-#define BM_UARTAPP_INTR_OEIEN       0x4000000
-#define BF_UARTAPP_INTR_OEIEN(v)    (((v) << 26) & 0x4000000)
-#define BP_UARTAPP_INTR_BEIEN       25
-#define BM_UARTAPP_INTR_BEIEN       0x2000000
-#define BF_UARTAPP_INTR_BEIEN(v)    (((v) << 25) & 0x2000000)
-#define BP_UARTAPP_INTR_PEIEN       24
-#define BM_UARTAPP_INTR_PEIEN       0x1000000
-#define BF_UARTAPP_INTR_PEIEN(v)    (((v) << 24) & 0x1000000)
-#define BP_UARTAPP_INTR_FEIEN       23
-#define BM_UARTAPP_INTR_FEIEN       0x800000
-#define BF_UARTAPP_INTR_FEIEN(v)    (((v) << 23) & 0x800000)
-#define BP_UARTAPP_INTR_RTIEN       22
-#define BM_UARTAPP_INTR_RTIEN       0x400000
-#define BF_UARTAPP_INTR_RTIEN(v)    (((v) << 22) & 0x400000)
-#define BP_UARTAPP_INTR_TXIEN       21
-#define BM_UARTAPP_INTR_TXIEN       0x200000
-#define BF_UARTAPP_INTR_TXIEN(v)    (((v) << 21) & 0x200000)
-#define BP_UARTAPP_INTR_RXIEN       20
-#define BM_UARTAPP_INTR_RXIEN       0x100000
-#define BF_UARTAPP_INTR_RXIEN(v)    (((v) << 20) & 0x100000)
-#define BP_UARTAPP_INTR_DSRMIEN     19
-#define BM_UARTAPP_INTR_DSRMIEN     0x80000
-#define BF_UARTAPP_INTR_DSRMIEN(v)  (((v) << 19) & 0x80000)
-#define BP_UARTAPP_INTR_DCDMIEN     18
-#define BM_UARTAPP_INTR_DCDMIEN     0x40000
-#define BF_UARTAPP_INTR_DCDMIEN(v)  (((v) << 18) & 0x40000)
-#define BP_UARTAPP_INTR_CTSMIEN     17
-#define BM_UARTAPP_INTR_CTSMIEN     0x20000
-#define BF_UARTAPP_INTR_CTSMIEN(v)  (((v) << 17) & 0x20000)
-#define BP_UARTAPP_INTR_RIMIEN      16
-#define BM_UARTAPP_INTR_RIMIEN      0x10000
-#define BF_UARTAPP_INTR_RIMIEN(v)   (((v) << 16) & 0x10000)
-#define BP_UARTAPP_INTR_OEIS        10
-#define BM_UARTAPP_INTR_OEIS        0x400
-#define BF_UARTAPP_INTR_OEIS(v)     (((v) << 10) & 0x400)
-#define BP_UARTAPP_INTR_BEIS        9
-#define BM_UARTAPP_INTR_BEIS        0x200
-#define BF_UARTAPP_INTR_BEIS(v)     (((v) << 9) & 0x200)
-#define BP_UARTAPP_INTR_PEIS        8
-#define BM_UARTAPP_INTR_PEIS        0x100
-#define BF_UARTAPP_INTR_PEIS(v)     (((v) << 8) & 0x100)
-#define BP_UARTAPP_INTR_FEIS        7
-#define BM_UARTAPP_INTR_FEIS        0x80
-#define BF_UARTAPP_INTR_FEIS(v)     (((v) << 7) & 0x80)
-#define BP_UARTAPP_INTR_RTIS        6
-#define BM_UARTAPP_INTR_RTIS        0x40
-#define BF_UARTAPP_INTR_RTIS(v)     (((v) << 6) & 0x40)
-#define BP_UARTAPP_INTR_TXIS        5
-#define BM_UARTAPP_INTR_TXIS        0x20
-#define BF_UARTAPP_INTR_TXIS(v)     (((v) << 5) & 0x20)
-#define BP_UARTAPP_INTR_RXIS        4
-#define BM_UARTAPP_INTR_RXIS        0x10
-#define BF_UARTAPP_INTR_RXIS(v)     (((v) << 4) & 0x10)
-#define BP_UARTAPP_INTR_DSRMIS      3
-#define BM_UARTAPP_INTR_DSRMIS      0x8
-#define BF_UARTAPP_INTR_DSRMIS(v)   (((v) << 3) & 0x8)
-#define BP_UARTAPP_INTR_DCDMIS      2
-#define BM_UARTAPP_INTR_DCDMIS      0x4
-#define BF_UARTAPP_INTR_DCDMIS(v)   (((v) << 2) & 0x4)
-#define BP_UARTAPP_INTR_CTSMIS      1
-#define BM_UARTAPP_INTR_CTSMIS      0x2
-#define BF_UARTAPP_INTR_CTSMIS(v)   (((v) << 1) & 0x2)
-#define BP_UARTAPP_INTR_RIMIS       0
-#define BM_UARTAPP_INTR_RIMIS       0x1
-#define BF_UARTAPP_INTR_RIMIS(v)    (((v) << 0) & 0x1)
-
-/**
- * Register: HW_UARTAPP_DATA
- * Address: 0x60
- * SCT: no
-*/
-#define HW_UARTAPP_DATA(d)      (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x60))
-#define BP_UARTAPP_DATA_DATA    0
-#define BM_UARTAPP_DATA_DATA    0xffffffff
-#define BF_UARTAPP_DATA_DATA(v) (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_UARTAPP_STAT
- * Address: 0x70
- * SCT: no
-*/
-#define HW_UARTAPP_STAT(d)                      (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x70))
-#define BP_UARTAPP_STAT_PRESENT                 31
-#define BM_UARTAPP_STAT_PRESENT                 0x80000000
-#define BV_UARTAPP_STAT_PRESENT__UNAVAILABLE    0x0
-#define BV_UARTAPP_STAT_PRESENT__AVAILABLE      0x1
-#define BF_UARTAPP_STAT_PRESENT(v)              (((v) << 31) & 0x80000000)
-#define BF_UARTAPP_STAT_PRESENT_V(v)            ((BV_UARTAPP_STAT_PRESENT__##v << 31) & 0x80000000)
-#define BP_UARTAPP_STAT_HISPEED                 30
-#define BM_UARTAPP_STAT_HISPEED                 0x40000000
-#define BV_UARTAPP_STAT_HISPEED__UNAVAILABLE    0x0
-#define BV_UARTAPP_STAT_HISPEED__AVAILABLE      0x1
-#define BF_UARTAPP_STAT_HISPEED(v)              (((v) << 30) & 0x40000000)
-#define BF_UARTAPP_STAT_HISPEED_V(v)            ((BV_UARTAPP_STAT_HISPEED__##v << 30) & 0x40000000)
-#define BP_UARTAPP_STAT_BUSY                    29
-#define BM_UARTAPP_STAT_BUSY                    0x20000000
-#define BF_UARTAPP_STAT_BUSY(v)                 (((v) << 29) & 0x20000000)
-#define BP_UARTAPP_STAT_CTS                     28
-#define BM_UARTAPP_STAT_CTS                     0x10000000
-#define BF_UARTAPP_STAT_CTS(v)                  (((v) << 28) & 0x10000000)
-#define BP_UARTAPP_STAT_TXFE                    27
-#define BM_UARTAPP_STAT_TXFE                    0x8000000
-#define BF_UARTAPP_STAT_TXFE(v)                 (((v) << 27) & 0x8000000)
-#define BP_UARTAPP_STAT_RXFF                    26
-#define BM_UARTAPP_STAT_RXFF                    0x4000000
-#define BF_UARTAPP_STAT_RXFF(v)                 (((v) << 26) & 0x4000000)
-#define BP_UARTAPP_STAT_TXFF                    25
-#define BM_UARTAPP_STAT_TXFF                    0x2000000
-#define BF_UARTAPP_STAT_TXFF(v)                 (((v) << 25) & 0x2000000)
-#define BP_UARTAPP_STAT_RXFE                    24
-#define BM_UARTAPP_STAT_RXFE                    0x1000000
-#define BF_UARTAPP_STAT_RXFE(v)                 (((v) << 24) & 0x1000000)
-#define BP_UARTAPP_STAT_RXBYTE_INVALID          20
-#define BM_UARTAPP_STAT_RXBYTE_INVALID          0xf00000
-#define BF_UARTAPP_STAT_RXBYTE_INVALID(v)       (((v) << 20) & 0xf00000)
-#define BP_UARTAPP_STAT_OERR                    19
-#define BM_UARTAPP_STAT_OERR                    0x80000
-#define BF_UARTAPP_STAT_OERR(v)                 (((v) << 19) & 0x80000)
-#define BP_UARTAPP_STAT_BERR                    18
-#define BM_UARTAPP_STAT_BERR                    0x40000
-#define BF_UARTAPP_STAT_BERR(v)                 (((v) << 18) & 0x40000)
-#define BP_UARTAPP_STAT_PERR                    17
-#define BM_UARTAPP_STAT_PERR                    0x20000
-#define BF_UARTAPP_STAT_PERR(v)                 (((v) << 17) & 0x20000)
-#define BP_UARTAPP_STAT_FERR                    16
-#define BM_UARTAPP_STAT_FERR                    0x10000
-#define BF_UARTAPP_STAT_FERR(v)                 (((v) << 16) & 0x10000)
-#define BP_UARTAPP_STAT_RXCOUNT                 0
-#define BM_UARTAPP_STAT_RXCOUNT                 0xffff
-#define BF_UARTAPP_STAT_RXCOUNT(v)              (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_UARTAPP_DEBUG
- * Address: 0x80
- * SCT: no
-*/
-#define HW_UARTAPP_DEBUG(d)             (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x80))
-#define BP_UARTAPP_DEBUG_TXDMARUN       5
-#define BM_UARTAPP_DEBUG_TXDMARUN       0x20
-#define BF_UARTAPP_DEBUG_TXDMARUN(v)    (((v) << 5) & 0x20)
-#define BP_UARTAPP_DEBUG_RXDMARUN       4
-#define BM_UARTAPP_DEBUG_RXDMARUN       0x10
-#define BF_UARTAPP_DEBUG_RXDMARUN(v)    (((v) << 4) & 0x10)
-#define BP_UARTAPP_DEBUG_TXCMDEND       3
-#define BM_UARTAPP_DEBUG_TXCMDEND       0x8
-#define BF_UARTAPP_DEBUG_TXCMDEND(v)    (((v) << 3) & 0x8)
-#define BP_UARTAPP_DEBUG_RXCMDEND       2
-#define BM_UARTAPP_DEBUG_RXCMDEND       0x4
-#define BF_UARTAPP_DEBUG_RXCMDEND(v)    (((v) << 2) & 0x4)
-#define BP_UARTAPP_DEBUG_TXDMARQ        1
-#define BM_UARTAPP_DEBUG_TXDMARQ        0x2
-#define BF_UARTAPP_DEBUG_TXDMARQ(v)     (((v) << 1) & 0x2)
-#define BP_UARTAPP_DEBUG_RXDMARQ        0
-#define BM_UARTAPP_DEBUG_RXDMARQ        0x1
-#define BF_UARTAPP_DEBUG_RXDMARQ(v)     (((v) << 0) & 0x1)
-
-/**
- * Register: HW_UARTAPP_VERSION
- * Address: 0x90
- * SCT: no
-*/
-#define HW_UARTAPP_VERSION(d)       (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x90))
-#define BP_UARTAPP_VERSION_MAJOR    24
-#define BM_UARTAPP_VERSION_MAJOR    0xff000000
-#define BF_UARTAPP_VERSION_MAJOR(v) (((v) << 24) & 0xff000000)
-#define BP_UARTAPP_VERSION_MINOR    16
-#define BM_UARTAPP_VERSION_MINOR    0xff0000
-#define BF_UARTAPP_VERSION_MINOR(v) (((v) << 16) & 0xff0000)
-#define BP_UARTAPP_VERSION_STEP     0
-#define BM_UARTAPP_VERSION_STEP     0xffff
-#define BF_UARTAPP_VERSION_STEP(v)  (((v) << 0) & 0xffff)
-
-#endif /* __HEADERGEN__STMP3700__UARTAPP__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-uartdbg.h b/firmware/target/arm/imx233/regs/stmp3700/regs-uartdbg.h
deleted file mode 100644
index 070ea4b8e3..0000000000
--- a/firmware/target/arm/imx233/regs/stmp3700/regs-uartdbg.h
+++ /dev/null
@@ -1,491 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3700:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__STMP3700__UARTDBG__H__
-#define __HEADERGEN__STMP3700__UARTDBG__H__
-
-#define REGS_UARTDBG_BASE (0x80070000)
-
-#define REGS_UARTDBG_VERSION "3.2.0"
-
-/**
- * Register: HW_UARTDBG_DR
- * Address: 0
- * SCT: no
-*/
-#define HW_UARTDBG_DR                   (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x0))
-#define BP_UARTDBG_DR_UNAVAILABLE       16
-#define BM_UARTDBG_DR_UNAVAILABLE       0xffff0000
-#define BF_UARTDBG_DR_UNAVAILABLE(v)    (((v) << 16) & 0xffff0000)
-#define BP_UARTDBG_DR_RESERVED          12
-#define BM_UARTDBG_DR_RESERVED          0xf000
-#define BF_UARTDBG_DR_RESERVED(v)       (((v) << 12) & 0xf000)
-#define BP_UARTDBG_DR_OE                11
-#define BM_UARTDBG_DR_OE                0x800
-#define BF_UARTDBG_DR_OE(v)             (((v) << 11) & 0x800)
-#define BP_UARTDBG_DR_BE                10
-#define BM_UARTDBG_DR_BE                0x400
-#define BF_UARTDBG_DR_BE(v)             (((v) << 10) & 0x400)
-#define BP_UARTDBG_DR_PE                9
-#define BM_UARTDBG_DR_PE                0x200
-#define BF_UARTDBG_DR_PE(v)             (((v) << 9) & 0x200)
-#define BP_UARTDBG_DR_FE                8
-#define BM_UARTDBG_DR_FE                0x100
-#define BF_UARTDBG_DR_FE(v)             (((v) << 8) & 0x100)
-#define BP_UARTDBG_DR_DATA              0
-#define BM_UARTDBG_DR_DATA              0xff
-#define BF_UARTDBG_DR_DATA(v)           (((v) << 0) & 0xff)
-
-/**
- * Register: HW_UARTDBG_RSR_ECR
- * Address: 0x4
- * SCT: no
-*/
-#define HW_UARTDBG_RSR_ECR                  (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x4))
-#define BP_UARTDBG_RSR_ECR_UNAVAILABLE      8
-#define BM_UARTDBG_RSR_ECR_UNAVAILABLE      0xffffff00
-#define BF_UARTDBG_RSR_ECR_UNAVAILABLE(v)   (((v) << 8) & 0xffffff00)
-#define BP_UARTDBG_RSR_ECR_EC               4
-#define BM_UARTDBG_RSR_ECR_EC               0xf0
-#define BF_UARTDBG_RSR_ECR_EC(v)            (((v) << 4) & 0xf0)
-#define BP_UARTDBG_RSR_ECR_OE               3
-#define BM_UARTDBG_RSR_ECR_OE               0x8
-#define BF_UARTDBG_RSR_ECR_OE(v)            (((v) << 3) & 0x8)
-#define BP_UARTDBG_RSR_ECR_BE               2
-#define BM_UARTDBG_RSR_ECR_BE               0x4
-#define BF_UARTDBG_RSR_ECR_BE(v)            (((v) << 2) & 0x4)
-#define BP_UARTDBG_RSR_ECR_PE               1
-#define BM_UARTDBG_RSR_ECR_PE               0x2
-#define BF_UARTDBG_RSR_ECR_PE(v)            (((v) << 1) & 0x2)
-#define BP_UARTDBG_RSR_ECR_FE               0
-#define BM_UARTDBG_RSR_ECR_FE               0x1
-#define BF_UARTDBG_RSR_ECR_FE(v)            (((v) << 0) & 0x1)
-
-/**
- * Register: HW_UARTDBG_FR
- * Address: 0x18
- * SCT: no
-*/
-#define HW_UARTDBG_FR                   (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x18))
-#define BP_UARTDBG_FR_UNAVAILABLE       16
-#define BM_UARTDBG_FR_UNAVAILABLE       0xffff0000
-#define BF_UARTDBG_FR_UNAVAILABLE(v)    (((v) << 16) & 0xffff0000)
-#define BP_UARTDBG_FR_RESERVED          9
-#define BM_UARTDBG_FR_RESERVED          0xfe00
-#define BF_UARTDBG_FR_RESERVED(v)       (((v) << 9) & 0xfe00)
-#define BP_UARTDBG_FR_RI                8
-#define BM_UARTDBG_FR_RI                0x100
-#define BF_UARTDBG_FR_RI(v)             (((v) << 8) & 0x100)
-#define BP_UARTDBG_FR_TXFE              7
-#define BM_UARTDBG_FR_TXFE              0x80
-#define BF_UARTDBG_FR_TXFE(v)           (((v) << 7) & 0x80)
-#define BP_UARTDBG_FR_RXFF              6
-#define BM_UARTDBG_FR_RXFF              0x40
-#define BF_UARTDBG_FR_RXFF(v)           (((v) << 6) & 0x40)
-#define BP_UARTDBG_FR_TXFF              5
-#define BM_UARTDBG_FR_TXFF              0x20
-#define BF_UARTDBG_FR_TXFF(v)           (((v) << 5) & 0x20)
-#define BP_UARTDBG_FR_RXFE              4
-#define BM_UARTDBG_FR_RXFE              0x10
-#define BF_UARTDBG_FR_RXFE(v)           (((v) << 4) & 0x10)
-#define BP_UARTDBG_FR_BUSY              3
-#define BM_UARTDBG_FR_BUSY              0x8
-#define BF_UARTDBG_FR_BUSY(v)           (((v) << 3) & 0x8)
-#define BP_UARTDBG_FR_DCD               2
-#define BM_UARTDBG_FR_DCD               0x4
-#define BF_UARTDBG_FR_DCD(v)            (((v) << 2) & 0x4)
-#define BP_UARTDBG_FR_DSR               1
-#define BM_UARTDBG_FR_DSR               0x2
-#define BF_UARTDBG_FR_DSR(v)            (((v) << 1) & 0x2)
-#define BP_UARTDBG_FR_CTS               0
-#define BM_UARTDBG_FR_CTS               0x1
-#define BF_UARTDBG_FR_CTS(v)            (((v) << 0) & 0x1)
-
-/**
- * Register: HW_UARTDBG_ILPR
- * Address: 0x20
- * SCT: no
-*/
-#define HW_UARTDBG_ILPR                 (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x20))
-#define BP_UARTDBG_ILPR_UNAVAILABLE     8
-#define BM_UARTDBG_ILPR_UNAVAILABLE     0xffffff00
-#define BF_UARTDBG_ILPR_UNAVAILABLE(v)  (((v) << 8) & 0xffffff00)
-#define BP_UARTDBG_ILPR_ILPDVSR         0
-#define BM_UARTDBG_ILPR_ILPDVSR         0xff
-#define BF_UARTDBG_ILPR_ILPDVSR(v)      (((v) << 0) & 0xff)
-
-/**
- * Register: HW_UARTDBG_IBRD
- * Address: 0x24
- * SCT: no
-*/
-#define HW_UARTDBG_IBRD                 (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x24))
-#define BP_UARTDBG_IBRD_UNAVAILABLE     16
-#define BM_UARTDBG_IBRD_UNAVAILABLE     0xffff0000
-#define BF_UARTDBG_IBRD_UNAVAILABLE(v)  (((v) << 16) & 0xffff0000)
-#define BP_UARTDBG_IBRD_BAUD_DIVINT     0
-#define BM_UARTDBG_IBRD_BAUD_DIVINT     0xffff
-#define BF_UARTDBG_IBRD_BAUD_DIVINT(v)  (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_UARTDBG_FBRD
- * Address: 0x28
- * SCT: no
-*/
-#define HW_UARTDBG_FBRD                 (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x28))
-#define BP_UARTDBG_FBRD_UNAVAILABLE     8
-#define BM_UARTDBG_FBRD_UNAVAILABLE     0xffffff00
-#define BF_UARTDBG_FBRD_UNAVAILABLE(v)  (((v) << 8) & 0xffffff00)
-#define BP_UARTDBG_FBRD_RESERVED        6
-#define BM_UARTDBG_FBRD_RESERVED        0xc0
-#define BF_UARTDBG_FBRD_RESERVED(v)     (((v) << 6) & 0xc0)
-#define BP_UARTDBG_FBRD_BAUD_DIVFRAC    0
-#define BM_UARTDBG_FBRD_BAUD_DIVFRAC    0x3f
-#define BF_UARTDBG_FBRD_BAUD_DIVFRAC(v) (((v) << 0) & 0x3f)
-
-/**
- * Register: HW_UARTDBG_LCR_H
- * Address: 0x2c
- * SCT: no
-*/
-#define HW_UARTDBG_LCR_H                (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x2c))
-#define BP_UARTDBG_LCR_H_UNAVAILABLE    16
-#define BM_UARTDBG_LCR_H_UNAVAILABLE    0xffff0000
-#define BF_UARTDBG_LCR_H_UNAVAILABLE(v) (((v) << 16) & 0xffff0000)
-#define BP_UARTDBG_LCR_H_RESERVED       8
-#define BM_UARTDBG_LCR_H_RESERVED       0xff00
-#define BF_UARTDBG_LCR_H_RESERVED(v)    (((v) << 8) & 0xff00)
-#define BP_UARTDBG_LCR_H_SPS            7
-#define BM_UARTDBG_LCR_H_SPS            0x80
-#define BF_UARTDBG_LCR_H_SPS(v)         (((v) << 7) & 0x80)
-#define BP_UARTDBG_LCR_H_WLEN           5
-#define BM_UARTDBG_LCR_H_WLEN           0x60
-#define BF_UARTDBG_LCR_H_WLEN(v)        (((v) << 5) & 0x60)
-#define BP_UARTDBG_LCR_H_FEN            4
-#define BM_UARTDBG_LCR_H_FEN            0x10
-#define BF_UARTDBG_LCR_H_FEN(v)         (((v) << 4) & 0x10)
-#define BP_UARTDBG_LCR_H_STP2           3
-#define BM_UARTDBG_LCR_H_STP2           0x8
-#define BF_UARTDBG_LCR_H_STP2(v)        (((v) << 3) & 0x8)
-#define BP_UARTDBG_LCR_H_EPS            2
-#define BM_UARTDBG_LCR_H_EPS            0x4
-#define BF_UARTDBG_LCR_H_EPS(v)         (((v) << 2) & 0x4)
-#define BP_UARTDBG_LCR_H_PEN            1
-#define BM_UARTDBG_LCR_H_PEN            0x2
-#define BF_UARTDBG_LCR_H_PEN(v)         (((v) << 1) & 0x2)
-#define BP_UARTDBG_LCR_H_BRK            0
-#define BM_UARTDBG_LCR_H_BRK            0x1
-#define BF_UARTDBG_LCR_H_BRK(v)         (((v) << 0) & 0x1)
-
-/**
- * Register: HW_UARTDBG_CR
- * Address: 0x30
- * SCT: no
-*/
-#define HW_UARTDBG_CR                   (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x30))
-#define BP_UARTDBG_CR_UNAVAILABLE       16
-#define BM_UARTDBG_CR_UNAVAILABLE       0xffff0000
-#define BF_UARTDBG_CR_UNAVAILABLE(v)    (((v) << 16) & 0xffff0000)
-#define BP_UARTDBG_CR_CTSEN             15
-#define BM_UARTDBG_CR_CTSEN             0x8000
-#define BF_UARTDBG_CR_CTSEN(v)          (((v) << 15) & 0x8000)
-#define BP_UARTDBG_CR_RTSEN             14
-#define BM_UARTDBG_CR_RTSEN             0x4000
-#define BF_UARTDBG_CR_RTSEN(v)          (((v) << 14) & 0x4000)
-#define BP_UARTDBG_CR_OUT2              13
-#define BM_UARTDBG_CR_OUT2              0x2000
-#define BF_UARTDBG_CR_OUT2(v)           (((v) << 13) & 0x2000)
-#define BP_UARTDBG_CR_OUT1              12
-#define BM_UARTDBG_CR_OUT1              0x1000
-#define BF_UARTDBG_CR_OUT1(v)           (((v) << 12) & 0x1000)
-#define BP_UARTDBG_CR_RTS               11
-#define BM_UARTDBG_CR_RTS               0x800
-#define BF_UARTDBG_CR_RTS(v)            (((v) << 11) & 0x800)
-#define BP_UARTDBG_CR_DTR               10
-#define BM_UARTDBG_CR_DTR               0x400
-#define BF_UARTDBG_CR_DTR(v)            (((v) << 10) & 0x400)
-#define BP_UARTDBG_CR_RXE               9
-#define BM_UARTDBG_CR_RXE               0x200
-#define BF_UARTDBG_CR_RXE(v)            (((v) << 9) & 0x200)
-#define BP_UARTDBG_CR_TXE               8
-#define BM_UARTDBG_CR_TXE               0x100
-#define BF_UARTDBG_CR_TXE(v)            (((v) << 8) & 0x100)
-#define BP_UARTDBG_CR_LBE               7
-#define BM_UARTDBG_CR_LBE               0x80
-#define BF_UARTDBG_CR_LBE(v)            (((v) << 7) & 0x80)
-#define BP_UARTDBG_CR_RESERVED          3
-#define BM_UARTDBG_CR_RESERVED          0x78
-#define BF_UARTDBG_CR_RESERVED(v)       (((v) << 3) & 0x78)
-#define BP_UARTDBG_CR_SIRLP             2
-#define BM_UARTDBG_CR_SIRLP             0x4
-#define BF_UARTDBG_CR_SIRLP(v)          (((v) << 2) & 0x4)
-#define BP_UARTDBG_CR_SIREN             1
-#define BM_UARTDBG_CR_SIREN             0x2
-#define BF_UARTDBG_CR_SIREN(v)          (((v) << 1) & 0x2)
-#define BP_UARTDBG_CR_UARTEN            0
-#define BM_UARTDBG_CR_UARTEN            0x1
-#define BF_UARTDBG_CR_UARTEN(v)         (((v) << 0) & 0x1)
-
-/**
- * Register: HW_UARTDBG_IFLS
- * Address: 0x34
- * SCT: no
-*/
-#define HW_UARTDBG_IFLS                             (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x34))
-#define BP_UARTDBG_IFLS_UNAVAILABLE                 16
-#define BM_UARTDBG_IFLS_UNAVAILABLE                 0xffff0000
-#define BF_UARTDBG_IFLS_UNAVAILABLE(v)              (((v) << 16) & 0xffff0000)
-#define BP_UARTDBG_IFLS_RESERVED                    6
-#define BM_UARTDBG_IFLS_RESERVED                    0xffc0
-#define BF_UARTDBG_IFLS_RESERVED(v)                 (((v) << 6) & 0xffc0)
-#define BP_UARTDBG_IFLS_RXIFLSEL                    3
-#define BM_UARTDBG_IFLS_RXIFLSEL                    0x38
-#define BV_UARTDBG_IFLS_RXIFLSEL__NOT_EMPTY         0x0
-#define BV_UARTDBG_IFLS_RXIFLSEL__ONE_QUARTER       0x1
-#define BV_UARTDBG_IFLS_RXIFLSEL__ONE_HALF          0x2
-#define BV_UARTDBG_IFLS_RXIFLSEL__THREE_QUARTERS    0x3
-#define BV_UARTDBG_IFLS_RXIFLSEL__SEVEN_EIGHTHS     0x4
-#define BV_UARTDBG_IFLS_RXIFLSEL__INVALID5          0x5
-#define BV_UARTDBG_IFLS_RXIFLSEL__INVALID6          0x6
-#define BV_UARTDBG_IFLS_RXIFLSEL__INVALID7          0x7
-#define BF_UARTDBG_IFLS_RXIFLSEL(v)                 (((v) << 3) & 0x38)
-#define BF_UARTDBG_IFLS_RXIFLSEL_V(v)               ((BV_UARTDBG_IFLS_RXIFLSEL__##v << 3) & 0x38)
-#define BP_UARTDBG_IFLS_TXIFLSEL                    0
-#define BM_UARTDBG_IFLS_TXIFLSEL                    0x7
-#define BV_UARTDBG_IFLS_TXIFLSEL__EMPTY             0x0
-#define BV_UARTDBG_IFLS_TXIFLSEL__ONE_QUARTER       0x1
-#define BV_UARTDBG_IFLS_TXIFLSEL__ONE_HALF          0x2
-#define BV_UARTDBG_IFLS_TXIFLSEL__THREE_QUARTERS    0x3
-#define BV_UARTDBG_IFLS_TXIFLSEL__SEVEN_EIGHTHS     0x4
-#define BV_UARTDBG_IFLS_TXIFLSEL__INVALID5          0x5
-#define BV_UARTDBG_IFLS_TXIFLSEL__INVALID6          0x6
-#define BV_UARTDBG_IFLS_TXIFLSEL__INVALID7          0x7
-#define BF_UARTDBG_IFLS_TXIFLSEL(v)                 (((v) << 0) & 0x7)
-#define BF_UARTDBG_IFLS_TXIFLSEL_V(v)               ((BV_UARTDBG_IFLS_TXIFLSEL__##v << 0) & 0x7)
-
-/**
- * Register: HW_UARTDBG_IMSC
- * Address: 0x38
- * SCT: no
-*/
-#define HW_UARTDBG_IMSC                 (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x38))
-#define BP_UARTDBG_IMSC_UNAVAILABLE     16
-#define BM_UARTDBG_IMSC_UNAVAILABLE     0xffff0000
-#define BF_UARTDBG_IMSC_UNAVAILABLE(v)  (((v) << 16) & 0xffff0000)
-#define BP_UARTDBG_IMSC_RESERVED        11
-#define BM_UARTDBG_IMSC_RESERVED        0xf800
-#define BF_UARTDBG_IMSC_RESERVED(v)     (((v) << 11) & 0xf800)
-#define BP_UARTDBG_IMSC_OEIM            10
-#define BM_UARTDBG_IMSC_OEIM            0x400
-#define BF_UARTDBG_IMSC_OEIM(v)         (((v) << 10) & 0x400)
-#define BP_UARTDBG_IMSC_BEIM            9
-#define BM_UARTDBG_IMSC_BEIM            0x200
-#define BF_UARTDBG_IMSC_BEIM(v)         (((v) << 9) & 0x200)
-#define BP_UARTDBG_IMSC_PEIM            8
-#define BM_UARTDBG_IMSC_PEIM            0x100
-#define BF_UARTDBG_IMSC_PEIM(v)         (((v) << 8) & 0x100)
-#define BP_UARTDBG_IMSC_FEIM            7
-#define BM_UARTDBG_IMSC_FEIM            0x80
-#define BF_UARTDBG_IMSC_FEIM(v)         (((v) << 7) & 0x80)
-#define BP_UARTDBG_IMSC_RTIM            6
-#define BM_UARTDBG_IMSC_RTIM            0x40
-#define BF_UARTDBG_IMSC_RTIM(v)         (((v) << 6) & 0x40)
-#define BP_UARTDBG_IMSC_TXIM            5
-#define BM_UARTDBG_IMSC_TXIM            0x20
-#define BF_UARTDBG_IMSC_TXIM(v)         (((v) << 5) & 0x20)
-#define BP_UARTDBG_IMSC_RXIM            4
-#define BM_UARTDBG_IMSC_RXIM            0x10
-#define BF_UARTDBG_IMSC_RXIM(v)         (((v) << 4) & 0x10)
-#define BP_UARTDBG_IMSC_DSRMIM          3
-#define BM_UARTDBG_IMSC_DSRMIM          0x8
-#define BF_UARTDBG_IMSC_DSRMIM(v)       (((v) << 3) & 0x8)
-#define BP_UARTDBG_IMSC_DCDMIM          2
-#define BM_UARTDBG_IMSC_DCDMIM          0x4
-#define BF_UARTDBG_IMSC_DCDMIM(v)       (((v) << 2) & 0x4)
-#define BP_UARTDBG_IMSC_CTSMIM          1
-#define BM_UARTDBG_IMSC_CTSMIM          0x2
-#define BF_UARTDBG_IMSC_CTSMIM(v)       (((v) << 1) & 0x2)
-#define BP_UARTDBG_IMSC_RIMIM           0
-#define BM_UARTDBG_IMSC_RIMIM           0x1
-#define BF_UARTDBG_IMSC_RIMIM(v)        (((v) << 0) & 0x1)
-
-/**
- * Register: HW_UARTDBG_RIS
- * Address: 0x3c
- * SCT: no
-*/
-#define HW_UARTDBG_RIS                  (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x3c))
-#define BP_UARTDBG_RIS_UNAVAILABLE      16
-#define BM_UARTDBG_RIS_UNAVAILABLE      0xffff0000
-#define BF_UARTDBG_RIS_UNAVAILABLE(v)   (((v) << 16) & 0xffff0000)
-#define BP_UARTDBG_RIS_RESERVED         11
-#define BM_UARTDBG_RIS_RESERVED         0xf800
-#define BF_UARTDBG_RIS_RESERVED(v)      (((v) << 11) & 0xf800)
-#define BP_UARTDBG_RIS_OERIS            10
-#define BM_UARTDBG_RIS_OERIS            0x400
-#define BF_UARTDBG_RIS_OERIS(v)         (((v) << 10) & 0x400)
-#define BP_UARTDBG_RIS_BERIS            9
-#define BM_UARTDBG_RIS_BERIS            0x200
-#define BF_UARTDBG_RIS_BERIS(v)         (((v) << 9) & 0x200)
-#define BP_UARTDBG_RIS_PERIS            8
-#define BM_UARTDBG_RIS_PERIS            0x100
-#define BF_UARTDBG_RIS_PERIS(v)         (((v) << 8) & 0x100)
-#define BP_UARTDBG_RIS_FERIS            7
-#define BM_UARTDBG_RIS_FERIS            0x80
-#define BF_UARTDBG_RIS_FERIS(v)         (((v) << 7) & 0x80)
-#define BP_UARTDBG_RIS_RTRIS            6
-#define BM_UARTDBG_RIS_RTRIS            0x40
-#define BF_UARTDBG_RIS_RTRIS(v)         (((v) << 6) & 0x40)
-#define BP_UARTDBG_RIS_TXRIS            5
-#define BM_UARTDBG_RIS_TXRIS            0x20
-#define BF_UARTDBG_RIS_TXRIS(v)         (((v) << 5) & 0x20)
-#define BP_UARTDBG_RIS_RXRIS            4
-#define BM_UARTDBG_RIS_RXRIS            0x10
-#define BF_UARTDBG_RIS_RXRIS(v)         (((v) << 4) & 0x10)
-#define BP_UARTDBG_RIS_DSRRMIS          3
-#define BM_UARTDBG_RIS_DSRRMIS          0x8
-#define BF_UARTDBG_RIS_DSRRMIS(v)       (((v) << 3) & 0x8)
-#define BP_UARTDBG_RIS_DCDRMIS          2
-#define BM_UARTDBG_RIS_DCDRMIS          0x4
-#define BF_UARTDBG_RIS_DCDRMIS(v)       (((v) << 2) & 0x4)
-#define BP_UARTDBG_RIS_CTSRMIS          1
-#define BM_UARTDBG_RIS_CTSRMIS          0x2
-#define BF_UARTDBG_RIS_CTSRMIS(v)       (((v) << 1) & 0x2)
-#define BP_UARTDBG_RIS_RIRMIS           0
-#define BM_UARTDBG_RIS_RIRMIS           0x1
-#define BF_UARTDBG_RIS_RIRMIS(v)        (((v) << 0) & 0x1)
-
-/**
- * Register: HW_UARTDBG_MIS
- * Address: 0x40
- * SCT: no
-*/
-#define HW_UARTDBG_MIS                  (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x40))
-#define BP_UARTDBG_MIS_UNAVAILABLE      16
-#define BM_UARTDBG_MIS_UNAVAILABLE      0xffff0000
-#define BF_UARTDBG_MIS_UNAVAILABLE(v)   (((v) << 16) & 0xffff0000)
-#define BP_UARTDBG_MIS_RESERVED         11
-#define BM_UARTDBG_MIS_RESERVED         0xf800
-#define BF_UARTDBG_MIS_RESERVED(v)      (((v) << 11) & 0xf800)
-#define BP_UARTDBG_MIS_OEMIS            10
-#define BM_UARTDBG_MIS_OEMIS            0x400
-#define BF_UARTDBG_MIS_OEMIS(v)         (((v) << 10) & 0x400)
-#define BP_UARTDBG_MIS_BEMIS            9
-#define BM_UARTDBG_MIS_BEMIS            0x200
-#define BF_UARTDBG_MIS_BEMIS(v)         (((v) << 9) & 0x200)
-#define BP_UARTDBG_MIS_PEMIS            8
-#define BM_UARTDBG_MIS_PEMIS            0x100
-#define BF_UARTDBG_MIS_PEMIS(v)         (((v) << 8) & 0x100)
-#define BP_UARTDBG_MIS_FEMIS            7
-#define BM_UARTDBG_MIS_FEMIS            0x80
-#define BF_UARTDBG_MIS_FEMIS(v)         (((v) << 7) & 0x80)
-#define BP_UARTDBG_MIS_RTMIS            6
-#define BM_UARTDBG_MIS_RTMIS            0x40
-#define BF_UARTDBG_MIS_RTMIS(v)         (((v) << 6) & 0x40)
-#define BP_UARTDBG_MIS_TXMIS            5
-#define BM_UARTDBG_MIS_TXMIS            0x20
-#define BF_UARTDBG_MIS_TXMIS(v)         (((v) << 5) & 0x20)
-#define BP_UARTDBG_MIS_RXMIS            4
-#define BM_UARTDBG_MIS_RXMIS            0x10
-#define BF_UARTDBG_MIS_RXMIS(v)         (((v) << 4) & 0x10)
-#define BP_UARTDBG_MIS_DSRMMIS          3
-#define BM_UARTDBG_MIS_DSRMMIS          0x8
-#define BF_UARTDBG_MIS_DSRMMIS(v)       (((v) << 3) & 0x8)
-#define BP_UARTDBG_MIS_DCDMMIS          2
-#define BM_UARTDBG_MIS_DCDMMIS          0x4
-#define BF_UARTDBG_MIS_DCDMMIS(v)       (((v) << 2) & 0x4)
-#define BP_UARTDBG_MIS_CTSMMIS          1
-#define BM_UARTDBG_MIS_CTSMMIS          0x2
-#define BF_UARTDBG_MIS_CTSMMIS(v)       (((v) << 1) & 0x2)
-#define BP_UARTDBG_MIS_RIMMIS           0
-#define BM_UARTDBG_MIS_RIMMIS           0x1
-#define BF_UARTDBG_MIS_RIMMIS(v)        (((v) << 0) & 0x1)
-
-/**
- * Register: HW_UARTDBG_ICR
- * Address: 0x44
- * SCT: no
-*/
-#define HW_UARTDBG_ICR                  (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x44))
-#define BP_UARTDBG_ICR_UNAVAILABLE      16
-#define BM_UARTDBG_ICR_UNAVAILABLE      0xffff0000
-#define BF_UARTDBG_ICR_UNAVAILABLE(v)   (((v) << 16) & 0xffff0000)
-#define BP_UARTDBG_ICR_RESERVED         11
-#define BM_UARTDBG_ICR_RESERVED         0xf800
-#define BF_UARTDBG_ICR_RESERVED(v)      (((v) << 11) & 0xf800)
-#define BP_UARTDBG_ICR_OEIC             10
-#define BM_UARTDBG_ICR_OEIC             0x400
-#define BF_UARTDBG_ICR_OEIC(v)          (((v) << 10) & 0x400)
-#define BP_UARTDBG_ICR_BEIC             9
-#define BM_UARTDBG_ICR_BEIC             0x200
-#define BF_UARTDBG_ICR_BEIC(v)          (((v) << 9) & 0x200)
-#define BP_UARTDBG_ICR_PEIC             8
-#define BM_UARTDBG_ICR_PEIC             0x100
-#define BF_UARTDBG_ICR_PEIC(v)          (((v) << 8) & 0x100)
-#define BP_UARTDBG_ICR_FEIC             7
-#define BM_UARTDBG_ICR_FEIC             0x80
-#define BF_UARTDBG_ICR_FEIC(v)          (((v) << 7) & 0x80)
-#define BP_UARTDBG_ICR_RTIC             6
-#define BM_UARTDBG_ICR_RTIC             0x40
-#define BF_UARTDBG_ICR_RTIC(v)          (((v) << 6) & 0x40)
-#define BP_UARTDBG_ICR_TXIC             5
-#define BM_UARTDBG_ICR_TXIC             0x20
-#define BF_UARTDBG_ICR_TXIC(v)          (((v) << 5) & 0x20)
-#define BP_UARTDBG_ICR_RXIC             4
-#define BM_UARTDBG_ICR_RXIC             0x10
-#define BF_UARTDBG_ICR_RXIC(v)          (((v) << 4) & 0x10)
-#define BP_UARTDBG_ICR_DSRMIC           3
-#define BM_UARTDBG_ICR_DSRMIC           0x8
-#define BF_UARTDBG_ICR_DSRMIC(v)        (((v) << 3) & 0x8)
-#define BP_UARTDBG_ICR_DCDMIC           2
-#define BM_UARTDBG_ICR_DCDMIC           0x4
-#define BF_UARTDBG_ICR_DCDMIC(v)        (((v) << 2) & 0x4)
-#define BP_UARTDBG_ICR_CTSMIC           1
-#define BM_UARTDBG_ICR_CTSMIC           0x2
-#define BF_UARTDBG_ICR_CTSMIC(v)        (((v) << 1) & 0x2)
-#define BP_UARTDBG_ICR_RIMIC            0
-#define BM_UARTDBG_ICR_RIMIC            0x1
-#define BF_UARTDBG_ICR_RIMIC(v)         (((v) << 0) & 0x1)
-
-/**
- * Register: HW_UARTDBG_DMACR
- * Address: 0x48
- * SCT: no
-*/
-#define HW_UARTDBG_DMACR                (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x48))
-#define BP_UARTDBG_DMACR_UNAVAILABLE    16
-#define BM_UARTDBG_DMACR_UNAVAILABLE    0xffff0000
-#define BF_UARTDBG_DMACR_UNAVAILABLE(v) (((v) << 16) & 0xffff0000)
-#define BP_UARTDBG_DMACR_RESERVED       3
-#define BM_UARTDBG_DMACR_RESERVED       0xfff8
-#define BF_UARTDBG_DMACR_RESERVED(v)    (((v) << 3) & 0xfff8)
-#define BP_UARTDBG_DMACR_DMAONERR       2
-#define BM_UARTDBG_DMACR_DMAONERR       0x4
-#define BF_UARTDBG_DMACR_DMAONERR(v)    (((v) << 2) & 0x4)
-#define BP_UARTDBG_DMACR_TXDMAE         1
-#define BM_UARTDBG_DMACR_TXDMAE         0x2
-#define BF_UARTDBG_DMACR_TXDMAE(v)      (((v) << 1) & 0x2)
-#define BP_UARTDBG_DMACR_RXDMAE         0
-#define BM_UARTDBG_DMACR_RXDMAE         0x1
-#define BF_UARTDBG_DMACR_RXDMAE(v)      (((v) << 0) & 0x1)
-
-#endif /* __HEADERGEN__STMP3700__UARTDBG__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-usbctrl.h b/firmware/target/arm/imx233/regs/stmp3700/regs-usbctrl.h
deleted file mode 100644
index d6c9f3ebd1..0000000000
--- a/firmware/target/arm/imx233/regs/stmp3700/regs-usbctrl.h
+++ /dev/null
@@ -1,877 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3700:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__STMP3700__USBCTRL__H__
-#define __HEADERGEN__STMP3700__USBCTRL__H__
-
-#define REGS_USBCTRL_BASE (0x80080000)
-
-#define REGS_USBCTRL_VERSION "3.2.0"
-
-/**
- * Register: HW_USBCTRL_ID
- * Address: 0
- * SCT: no
-*/
-#define HW_USBCTRL_ID           (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x0))
-#define BP_USBCTRL_ID_REV       16
-#define BM_USBCTRL_ID_REV       0xff0000
-#define BF_USBCTRL_ID_REV(v)    (((v) << 16) & 0xff0000)
-#define BP_USBCTRL_ID_ID_N      8
-#define BM_USBCTRL_ID_ID_N      0xff00
-#define BF_USBCTRL_ID_ID_N(v)   (((v) << 8) & 0xff00)
-#define BP_USBCTRL_ID_ID        0
-#define BM_USBCTRL_ID_ID        0xff
-#define BF_USBCTRL_ID_ID(v)     (((v) << 0) & 0xff)
-
-/**
- * Register: HW_USBCTRL_GENERAL
- * Address: 0x4
- * SCT: no
-*/
-#define HW_USBCTRL_GENERAL          (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x4))
-#define BP_USBCTRL_GENERAL_SM       9
-#define BM_USBCTRL_GENERAL_SM       0x200
-#define BF_USBCTRL_GENERAL_SM(v)    (((v) << 9) & 0x200)
-#define BP_USBCTRL_GENERAL_PHYM     6
-#define BM_USBCTRL_GENERAL_PHYM     0x1c0
-#define BF_USBCTRL_GENERAL_PHYM(v)  (((v) << 6) & 0x1c0)
-#define BP_USBCTRL_GENERAL_PHYW     4
-#define BM_USBCTRL_GENERAL_PHYW     0x30
-#define BF_USBCTRL_GENERAL_PHYW(v)  (((v) << 4) & 0x30)
-#define BP_USBCTRL_GENERAL_BWT      3
-#define BM_USBCTRL_GENERAL_BWT      0x8
-#define BF_USBCTRL_GENERAL_BWT(v)   (((v) << 3) & 0x8)
-#define BP_USBCTRL_GENERAL_CLKC     1
-#define BM_USBCTRL_GENERAL_CLKC     0x6
-#define BF_USBCTRL_GENERAL_CLKC(v)  (((v) << 1) & 0x6)
-#define BP_USBCTRL_GENERAL_RT       0
-#define BM_USBCTRL_GENERAL_RT       0x1
-#define BF_USBCTRL_GENERAL_RT(v)    (((v) << 0) & 0x1)
-
-/**
- * Register: HW_USBCTRL_HOST
- * Address: 0x8
- * SCT: no
-*/
-#define HW_USBCTRL_HOST             (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x8))
-#define BP_USBCTRL_HOST_TTPER       24
-#define BM_USBCTRL_HOST_TTPER       0xff000000
-#define BF_USBCTRL_HOST_TTPER(v)    (((v) << 24) & 0xff000000)
-#define BP_USBCTRL_HOST_TTASY       16
-#define BM_USBCTRL_HOST_TTASY       0xff0000
-#define BF_USBCTRL_HOST_TTASY(v)    (((v) << 16) & 0xff0000)
-#define BP_USBCTRL_HOST_NPORT       1
-#define BM_USBCTRL_HOST_NPORT       0xe
-#define BF_USBCTRL_HOST_NPORT(v)    (((v) << 1) & 0xe)
-#define BP_USBCTRL_HOST_HC          0
-#define BM_USBCTRL_HOST_HC          0x1
-#define BF_USBCTRL_HOST_HC(v)       (((v) << 0) & 0x1)
-
-/**
- * Register: HW_USBCTRL_DEVICE
- * Address: 0xc
- * SCT: no
-*/
-#define HW_USBCTRL_DEVICE           (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0xc))
-#define BP_USBCTRL_DEVICE_DEVEP     1
-#define BM_USBCTRL_DEVICE_DEVEP     0x3e
-#define BF_USBCTRL_DEVICE_DEVEP(v)  (((v) << 1) & 0x3e)
-#define BP_USBCTRL_DEVICE_DC        0
-#define BM_USBCTRL_DEVICE_DC        0x1
-#define BF_USBCTRL_DEVICE_DC(v)     (((v) << 0) & 0x1)
-
-/**
- * Register: HW_USBCTRL_TXBUF
- * Address: 0x10
- * SCT: no
-*/
-#define HW_USBCTRL_TXBUF                (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x10))
-#define BP_USBCTRL_TXBUF_TXLCR          31
-#define BM_USBCTRL_TXBUF_TXLCR          0x80000000
-#define BF_USBCTRL_TXBUF_TXLCR(v)       (((v) << 31) & 0x80000000)
-#define BP_USBCTRL_TXBUF_TXCHANADD      16
-#define BM_USBCTRL_TXBUF_TXCHANADD      0xff0000
-#define BF_USBCTRL_TXBUF_TXCHANADD(v)   (((v) << 16) & 0xff0000)
-#define BP_USBCTRL_TXBUF_TXADD          8
-#define BM_USBCTRL_TXBUF_TXADD          0xff00
-#define BF_USBCTRL_TXBUF_TXADD(v)       (((v) << 8) & 0xff00)
-#define BP_USBCTRL_TXBUF_TXBURST        0
-#define BM_USBCTRL_TXBUF_TXBURST        0xff
-#define BF_USBCTRL_TXBUF_TXBURST(v)     (((v) << 0) & 0xff)
-
-/**
- * Register: HW_USBCTRL_RXBUF
- * Address: 0x14
- * SCT: no
-*/
-#define HW_USBCTRL_RXBUF            (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x14))
-#define BP_USBCTRL_RXBUF_RXADD      8
-#define BM_USBCTRL_RXBUF_RXADD      0xff00
-#define BF_USBCTRL_RXBUF_RXADD(v)   (((v) << 8) & 0xff00)
-#define BP_USBCTRL_RXBUF_RXBURST    0
-#define BM_USBCTRL_RXBUF_RXBURST    0xff
-#define BF_USBCTRL_RXBUF_RXBURST(v) (((v) << 0) & 0xff)
-
-/**
- * Register: HW_USBCTRL_TTTXBUF
- * Address: 0x18
- * SCT: no
-*/
-#define HW_USBCTRL_TTTXBUF              (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x18))
-#define BP_USBCTRL_TTTXBUF_TTTXBUF      0
-#define BM_USBCTRL_TTTXBUF_TTTXBUF      0xffffffff
-#define BF_USBCTRL_TTTXBUF_TTTXBUF(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_USBCTRL_TTRXBUF
- * Address: 0x1c
- * SCT: no
-*/
-#define HW_USBCTRL_TTRXBUF              (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x1c))
-#define BP_USBCTRL_TTRXBUF_TTRXBUF      0
-#define BM_USBCTRL_TTRXBUF_TTRXBUF      0xffffffff
-#define BF_USBCTRL_TTRXBUF_TTRXBUF(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_USBCTRL_CAPLENGTH
- * Address: 0x100
- * SCT: no
-*/
-#define HW_USBCTRL_CAPLENGTH            (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x100))
-#define BP_USBCTRL_CAPLENGTH_HCIVER     16
-#define BM_USBCTRL_CAPLENGTH_HCIVER     0xffff0000
-#define BF_USBCTRL_CAPLENGTH_HCIVER(v)  (((v) << 16) & 0xffff0000)
-#define BP_USBCTRL_CAPLENGTH_LENGTH     0
-#define BM_USBCTRL_CAPLENGTH_LENGTH     0xff
-#define BF_USBCTRL_CAPLENGTH_LENGTH(v)  (((v) << 0) & 0xff)
-
-/**
- * Register: HW_USBCTRL_HCSPARAMS
- * Address: 0x104
- * SCT: no
-*/
-#define HW_USBCTRL_HCSPARAMS            (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x104))
-#define BP_USBCTRL_HCSPARAMS_NPORTS     0
-#define BM_USBCTRL_HCSPARAMS_NPORTS     0xf
-#define BF_USBCTRL_HCSPARAMS_NPORTS(v)  (((v) << 0) & 0xf)
-#define BP_USBCTRL_HCSPARAMS_PPC        4
-#define BM_USBCTRL_HCSPARAMS_PPC        0x10
-#define BF_USBCTRL_HCSPARAMS_PPC(v)     (((v) << 4) & 0x10)
-#define BP_USBCTRL_HCSPARAMS_NPCC       8
-#define BM_USBCTRL_HCSPARAMS_NPCC       0xf00
-#define BF_USBCTRL_HCSPARAMS_NPCC(v)    (((v) << 8) & 0xf00)
-#define BP_USBCTRL_HCSPARAMS_NCC        12
-#define BM_USBCTRL_HCSPARAMS_NCC        0xf000
-#define BF_USBCTRL_HCSPARAMS_NCC(v)     (((v) << 12) & 0xf000)
-#define BP_USBCTRL_HCSPARAMS_PI         16
-#define BM_USBCTRL_HCSPARAMS_PI         0x10000
-#define BF_USBCTRL_HCSPARAMS_PI(v)      (((v) << 16) & 0x10000)
-#define BP_USBCTRL_HCSPARAMS_NPTT       20
-#define BM_USBCTRL_HCSPARAMS_NPTT       0xf00000
-#define BF_USBCTRL_HCSPARAMS_NPTT(v)    (((v) << 20) & 0xf00000)
-#define BP_USBCTRL_HCSPARAMS_NTT        24
-#define BM_USBCTRL_HCSPARAMS_NTT        0xf000000
-#define BF_USBCTRL_HCSPARAMS_NTT(v)     (((v) << 24) & 0xf000000)
-
-/**
- * Register: HW_USBCTRL_HCCPARAMS
- * Address: 0x108
- * SCT: no
-*/
-#define HW_USBCTRL_HCCPARAMS                        (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x108))
-#define BP_USBCTRL_HCCPARAMS_ADDR64BITCAP           0
-#define BM_USBCTRL_HCCPARAMS_ADDR64BITCAP           0x1
-#define BF_USBCTRL_HCCPARAMS_ADDR64BITCAP(v)        (((v) << 0) & 0x1)
-#define BP_USBCTRL_HCCPARAMS_PGM_FRM_LIST_FLAG      1
-#define BM_USBCTRL_HCCPARAMS_PGM_FRM_LIST_FLAG      0x2
-#define BF_USBCTRL_HCCPARAMS_PGM_FRM_LIST_FLAG(v)   (((v) << 1) & 0x2)
-#define BP_USBCTRL_HCCPARAMS_ASYNC_PARK_CAP         2
-#define BM_USBCTRL_HCCPARAMS_ASYNC_PARK_CAP         0x4
-#define BF_USBCTRL_HCCPARAMS_ASYNC_PARK_CAP(v)      (((v) << 2) & 0x4)
-#define BP_USBCTRL_HCCPARAMS_ISO_SCH_THRESHOLD      8
-#define BM_USBCTRL_HCCPARAMS_ISO_SCH_THRESHOLD      0xff00
-#define BF_USBCTRL_HCCPARAMS_ISO_SCH_THRESHOLD(v)   (((v) << 8) & 0xff00)
-
-/**
- * Register: HW_USBCTRL_DCIVERSION
- * Address: 0x120
- * SCT: no
-*/
-#define HW_USBCTRL_DCIVERSION           (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x120))
-#define BP_USBCTRL_DCIVERSION_DCIVER    0
-#define BM_USBCTRL_DCIVERSION_DCIVER    0xffff
-#define BF_USBCTRL_DCIVERSION_DCIVER(v) (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_USBCTRL_DCCPARAMS
- * Address: 0x124
- * SCT: no
-*/
-#define HW_USBCTRL_DCCPARAMS        (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x124))
-#define BP_USBCTRL_DCCPARAMS_HC     8
-#define BM_USBCTRL_DCCPARAMS_HC     0x100
-#define BF_USBCTRL_DCCPARAMS_HC(v)  (((v) << 8) & 0x100)
-#define BP_USBCTRL_DCCPARAMS_DC     7
-#define BM_USBCTRL_DCCPARAMS_DC     0x80
-#define BF_USBCTRL_DCCPARAMS_DC(v)  (((v) << 7) & 0x80)
-#define BP_USBCTRL_DCCPARAMS_DEN    0
-#define BM_USBCTRL_DCCPARAMS_DEN    0x1f
-#define BF_USBCTRL_DCCPARAMS_DEN(v) (((v) << 0) & 0x1f)
-
-/**
- * Register: HW_USBCTRL_USBCMD
- * Address: 0x140
- * SCT: no
-*/
-#define HW_USBCTRL_USBCMD           (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x140))
-#define BP_USBCTRL_USBCMD_RS        0
-#define BM_USBCTRL_USBCMD_RS        0x1
-#define BF_USBCTRL_USBCMD_RS(v)     (((v) << 0) & 0x1)
-#define BP_USBCTRL_USBCMD_RST       1
-#define BM_USBCTRL_USBCMD_RST       0x2
-#define BF_USBCTRL_USBCMD_RST(v)    (((v) << 1) & 0x2)
-#define BP_USBCTRL_USBCMD_FS0       2
-#define BM_USBCTRL_USBCMD_FS0       0x4
-#define BF_USBCTRL_USBCMD_FS0(v)    (((v) << 2) & 0x4)
-#define BP_USBCTRL_USBCMD_FS1       3
-#define BM_USBCTRL_USBCMD_FS1       0x8
-#define BF_USBCTRL_USBCMD_FS1(v)    (((v) << 3) & 0x8)
-#define BP_USBCTRL_USBCMD_PSE       4
-#define BM_USBCTRL_USBCMD_PSE       0x10
-#define BF_USBCTRL_USBCMD_PSE(v)    (((v) << 4) & 0x10)
-#define BP_USBCTRL_USBCMD_ASE       5
-#define BM_USBCTRL_USBCMD_ASE       0x20
-#define BF_USBCTRL_USBCMD_ASE(v)    (((v) << 5) & 0x20)
-#define BP_USBCTRL_USBCMD_IAA       6
-#define BM_USBCTRL_USBCMD_IAA       0x40
-#define BF_USBCTRL_USBCMD_IAA(v)    (((v) << 6) & 0x40)
-#define BP_USBCTRL_USBCMD_LR        7
-#define BM_USBCTRL_USBCMD_LR        0x80
-#define BF_USBCTRL_USBCMD_LR(v)     (((v) << 7) & 0x80)
-#define BP_USBCTRL_USBCMD_ASP0      8
-#define BM_USBCTRL_USBCMD_ASP0      0x100
-#define BF_USBCTRL_USBCMD_ASP0(v)   (((v) << 8) & 0x100)
-#define BP_USBCTRL_USBCMD_ASP1      9
-#define BM_USBCTRL_USBCMD_ASP1      0x200
-#define BF_USBCTRL_USBCMD_ASP1(v)   (((v) << 9) & 0x200)
-#define BP_USBCTRL_USBCMD_ASPE      11
-#define BM_USBCTRL_USBCMD_ASPE      0x800
-#define BF_USBCTRL_USBCMD_ASPE(v)   (((v) << 11) & 0x800)
-#define BP_USBCTRL_USBCMD_FS2       15
-#define BM_USBCTRL_USBCMD_FS2       0x8000
-#define BF_USBCTRL_USBCMD_FS2(v)    (((v) << 15) & 0x8000)
-#define BP_USBCTRL_USBCMD_ITC       16
-#define BM_USBCTRL_USBCMD_ITC       0xff0000
-#define BF_USBCTRL_USBCMD_ITC(v)    (((v) << 16) & 0xff0000)
-
-/**
- * Register: HW_USBCTRL_USBSTS
- * Address: 0x144
- * SCT: no
-*/
-#define HW_USBCTRL_USBSTS           (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x144))
-#define BP_USBCTRL_USBSTS_UI        0
-#define BM_USBCTRL_USBSTS_UI        0x1
-#define BF_USBCTRL_USBSTS_UI(v)     (((v) << 0) & 0x1)
-#define BP_USBCTRL_USBSTS_UEI       1
-#define BM_USBCTRL_USBSTS_UEI       0x2
-#define BF_USBCTRL_USBSTS_UEI(v)    (((v) << 1) & 0x2)
-#define BP_USBCTRL_USBSTS_PCI       2
-#define BM_USBCTRL_USBSTS_PCI       0x4
-#define BF_USBCTRL_USBSTS_PCI(v)    (((v) << 2) & 0x4)
-#define BP_USBCTRL_USBSTS_FRI       3
-#define BM_USBCTRL_USBSTS_FRI       0x8
-#define BF_USBCTRL_USBSTS_FRI(v)    (((v) << 3) & 0x8)
-#define BP_USBCTRL_USBSTS_SEI       4
-#define BM_USBCTRL_USBSTS_SEI       0x10
-#define BF_USBCTRL_USBSTS_SEI(v)    (((v) << 4) & 0x10)
-#define BP_USBCTRL_USBSTS_AAI       5
-#define BM_USBCTRL_USBSTS_AAI       0x20
-#define BF_USBCTRL_USBSTS_AAI(v)    (((v) << 5) & 0x20)
-#define BP_USBCTRL_USBSTS_URI       6
-#define BM_USBCTRL_USBSTS_URI       0x40
-#define BF_USBCTRL_USBSTS_URI(v)    (((v) << 6) & 0x40)
-#define BP_USBCTRL_USBSTS_SRI       7
-#define BM_USBCTRL_USBSTS_SRI       0x80
-#define BF_USBCTRL_USBSTS_SRI(v)    (((v) << 7) & 0x80)
-#define BP_USBCTRL_USBSTS_SLI       8
-#define BM_USBCTRL_USBSTS_SLI       0x100
-#define BF_USBCTRL_USBSTS_SLI(v)    (((v) << 8) & 0x100)
-#define BP_USBCTRL_USBSTS_ULPII     10
-#define BM_USBCTRL_USBSTS_ULPII     0x400
-#define BF_USBCTRL_USBSTS_ULPII(v)  (((v) << 10) & 0x400)
-#define BP_USBCTRL_USBSTS_HCH       12
-#define BM_USBCTRL_USBSTS_HCH       0x1000
-#define BF_USBCTRL_USBSTS_HCH(v)    (((v) << 12) & 0x1000)
-#define BP_USBCTRL_USBSTS_RCL       13
-#define BM_USBCTRL_USBSTS_RCL       0x2000
-#define BF_USBCTRL_USBSTS_RCL(v)    (((v) << 13) & 0x2000)
-#define BP_USBCTRL_USBSTS_PS        14
-#define BM_USBCTRL_USBSTS_PS        0x4000
-#define BF_USBCTRL_USBSTS_PS(v)     (((v) << 14) & 0x4000)
-#define BP_USBCTRL_USBSTS_AS        15
-#define BM_USBCTRL_USBSTS_AS        0x8000
-#define BF_USBCTRL_USBSTS_AS(v)     (((v) << 15) & 0x8000)
-#define BP_USBCTRL_USBSTS_NAKI      16
-#define BM_USBCTRL_USBSTS_NAKI      0x10000
-#define BF_USBCTRL_USBSTS_NAKI(v)   (((v) << 16) & 0x10000)
-
-/**
- * Register: HW_USBCTRL_USBINTR
- * Address: 0x148
- * SCT: no
-*/
-#define HW_USBCTRL_USBINTR          (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x148))
-#define BP_USBCTRL_USBINTR_UE       0
-#define BM_USBCTRL_USBINTR_UE       0x1
-#define BF_USBCTRL_USBINTR_UE(v)    (((v) << 0) & 0x1)
-#define BP_USBCTRL_USBINTR_UEE      1
-#define BM_USBCTRL_USBINTR_UEE      0x2
-#define BF_USBCTRL_USBINTR_UEE(v)   (((v) << 1) & 0x2)
-#define BP_USBCTRL_USBINTR_PCE      2
-#define BM_USBCTRL_USBINTR_PCE      0x4
-#define BF_USBCTRL_USBINTR_PCE(v)   (((v) << 2) & 0x4)
-#define BP_USBCTRL_USBINTR_FRE      3
-#define BM_USBCTRL_USBINTR_FRE      0x8
-#define BF_USBCTRL_USBINTR_FRE(v)   (((v) << 3) & 0x8)
-#define BP_USBCTRL_USBINTR_SEE      4
-#define BM_USBCTRL_USBINTR_SEE      0x10
-#define BF_USBCTRL_USBINTR_SEE(v)   (((v) << 4) & 0x10)
-#define BP_USBCTRL_USBINTR_AAE      5
-#define BM_USBCTRL_USBINTR_AAE      0x20
-#define BF_USBCTRL_USBINTR_AAE(v)   (((v) << 5) & 0x20)
-#define BP_USBCTRL_USBINTR_URE      6
-#define BM_USBCTRL_USBINTR_URE      0x40
-#define BF_USBCTRL_USBINTR_URE(v)   (((v) << 6) & 0x40)
-#define BP_USBCTRL_USBINTR_SRE      7
-#define BM_USBCTRL_USBINTR_SRE      0x80
-#define BF_USBCTRL_USBINTR_SRE(v)   (((v) << 7) & 0x80)
-#define BP_USBCTRL_USBINTR_SLE      8
-#define BM_USBCTRL_USBINTR_SLE      0x100
-#define BF_USBCTRL_USBINTR_SLE(v)   (((v) << 8) & 0x100)
-#define BP_USBCTRL_USBINTR_ULPIE    10
-#define BM_USBCTRL_USBINTR_ULPIE    0x400
-#define BF_USBCTRL_USBINTR_ULPIE(v) (((v) << 10) & 0x400)
-#define BP_USBCTRL_USBINTR_NAKE     16
-#define BM_USBCTRL_USBINTR_NAKE     0x10000
-#define BF_USBCTRL_USBINTR_NAKE(v)  (((v) << 16) & 0x10000)
-
-/**
- * Register: HW_USBCTRL_FRINDEX
- * Address: 0x14c
- * SCT: no
-*/
-#define HW_USBCTRL_FRINDEX              (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x14c))
-#define BP_USBCTRL_FRINDEX_LISTINDEX    3
-#define BM_USBCTRL_FRINDEX_LISTINDEX    0x3ff8
-#define BF_USBCTRL_FRINDEX_LISTINDEX(v) (((v) << 3) & 0x3ff8)
-#define BP_USBCTRL_FRINDEX_UINDEX       0
-#define BM_USBCTRL_FRINDEX_UINDEX       0x7
-#define BF_USBCTRL_FRINDEX_UINDEX(v)    (((v) << 0) & 0x7)
-
-/**
- * Register: HW_USBCTRL_CTRLDSSEGMENT
- * Address: 0x150
- * SCT: no
-*/
-#define HW_USBCTRL_CTRLDSSEGMENT            (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x150))
-#define BP_USBCTRL_CTRLDSSEGMENT_EMPTY      0
-#define BM_USBCTRL_CTRLDSSEGMENT_EMPTY      0xffffffff
-#define BF_USBCTRL_CTRLDSSEGMENT_EMPTY(v)   (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_USBCTRL_PERIODICLISTBASE
- * Address: 0x154
- * SCT: no
-*/
-#define HW_USBCTRL_PERIODICLISTBASE             (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x154))
-#define BP_USBCTRL_PERIODICLISTBASE_BASEADDR    12
-#define BM_USBCTRL_PERIODICLISTBASE_BASEADDR    0xfffff000
-#define BF_USBCTRL_PERIODICLISTBASE_BASEADDR(v) (((v) << 12) & 0xfffff000)
-
-/**
- * Register: HW_USBCTRL_ASYNCLISTADDR
- * Address: 0x158
- * SCT: no
-*/
-#define HW_USBCTRL_ASYNCLISTADDR            (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x158))
-#define BP_USBCTRL_ASYNCLISTADDR_ASYBASE    5
-#define BM_USBCTRL_ASYNCLISTADDR_ASYBASE    0xffffffe0
-#define BF_USBCTRL_ASYNCLISTADDR_ASYBASE(v) (((v) << 5) & 0xffffffe0)
-
-/**
- * Register: HW_USBCTRL_TTCTRL
- * Address: 0x15c
- * SCT: no
-*/
-#define HW_USBCTRL_TTCTRL           (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x15c))
-#define BP_USBCTRL_TTCTRL_TTHA      24
-#define BM_USBCTRL_TTCTRL_TTHA      0x7f000000
-#define BF_USBCTRL_TTCTRL_TTHA(v)   (((v) << 24) & 0x7f000000)
-
-/**
- * Register: HW_USBCTRL_BURSTSIZE
- * Address: 0x160
- * SCT: no
-*/
-#define HW_USBCTRL_BURSTSIZE        (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x160))
-#define BP_USBCTRL_BURSTSIZE_TX     8
-#define BM_USBCTRL_BURSTSIZE_TX     0xff00
-#define BF_USBCTRL_BURSTSIZE_TX(v)  (((v) << 8) & 0xff00)
-#define BP_USBCTRL_BURSTSIZE_RX     0
-#define BM_USBCTRL_BURSTSIZE_RX     0xff
-#define BF_USBCTRL_BURSTSIZE_RX(v)  (((v) << 0) & 0xff)
-
-/**
- * Register: HW_USBCTRL_TXFILLTUNING
- * Address: 0x164
- * SCT: no
-*/
-#define HW_USBCTRL_TXFILLTUNING                 (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x164))
-#define BP_USBCTRL_TXFILLTUNING_TXFIFOTHRES     16
-#define BM_USBCTRL_TXFILLTUNING_TXFIFOTHRES     0x3f0000
-#define BF_USBCTRL_TXFILLTUNING_TXFIFOTHRES(v)  (((v) << 16) & 0x3f0000)
-#define BP_USBCTRL_TXFILLTUNING_TXSCHEALTH      8
-#define BM_USBCTRL_TXFILLTUNING_TXSCHEALTH      0x1f00
-#define BF_USBCTRL_TXFILLTUNING_TXSCHEALTH(v)   (((v) << 8) & 0x1f00)
-#define BP_USBCTRL_TXFILLTUNING_TXSCHOH         0
-#define BM_USBCTRL_TXFILLTUNING_TXSCHOH         0xff
-#define BF_USBCTRL_TXFILLTUNING_TXSCHOH(v)      (((v) << 0) & 0xff)
-
-/**
- * Register: HW_USBCTRL_TXTTFILLTUNING
- * Address: 0x168
- * SCT: no
-*/
-#define HW_USBCTRL_TXTTFILLTUNING           (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x168))
-#define BP_USBCTRL_TXTTFILLTUNING_EMPTY     0
-#define BM_USBCTRL_TXTTFILLTUNING_EMPTY     0xffffffff
-#define BF_USBCTRL_TXTTFILLTUNING_EMPTY(v)  (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_USBCTRL_ULPI
- * Address: 0x170
- * SCT: no
-*/
-#define HW_USBCTRL_ULPI             (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x170))
-#define BP_USBCTRL_ULPI_WAKEUP      31
-#define BM_USBCTRL_ULPI_WAKEUP      0x80000000
-#define BF_USBCTRL_ULPI_WAKEUP(v)   (((v) << 31) & 0x80000000)
-#define BP_USBCTRL_ULPI_RUN         30
-#define BM_USBCTRL_ULPI_RUN         0x40000000
-#define BF_USBCTRL_ULPI_RUN(v)      (((v) << 30) & 0x40000000)
-#define BP_USBCTRL_ULPI_RDWR        29
-#define BM_USBCTRL_ULPI_RDWR        0x20000000
-#define BF_USBCTRL_ULPI_RDWR(v)     (((v) << 29) & 0x20000000)
-#define BP_USBCTRL_ULPI_ERROR       28
-#define BM_USBCTRL_ULPI_ERROR       0x10000000
-#define BF_USBCTRL_ULPI_ERROR(v)    (((v) << 28) & 0x10000000)
-#define BP_USBCTRL_ULPI_SYNC        27
-#define BM_USBCTRL_ULPI_SYNC        0x8000000
-#define BF_USBCTRL_ULPI_SYNC(v)     (((v) << 27) & 0x8000000)
-#define BP_USBCTRL_ULPI_PORT        24
-#define BM_USBCTRL_ULPI_PORT        0x7000000
-#define BF_USBCTRL_ULPI_PORT(v)     (((v) << 24) & 0x7000000)
-#define BP_USBCTRL_ULPI_ADDR        16
-#define BM_USBCTRL_ULPI_ADDR        0xff0000
-#define BF_USBCTRL_ULPI_ADDR(v)     (((v) << 16) & 0xff0000)
-#define BP_USBCTRL_ULPI_DATARD      8
-#define BM_USBCTRL_ULPI_DATARD      0xff00
-#define BF_USBCTRL_ULPI_DATARD(v)   (((v) << 8) & 0xff00)
-#define BP_USBCTRL_ULPI_DATAWR      0
-#define BM_USBCTRL_ULPI_DATAWR      0xff
-#define BF_USBCTRL_ULPI_DATAWR(v)   (((v) << 0) & 0xff)
-
-/**
- * Register: HW_USBCTRL_VFRAME
- * Address: 0x174
- * SCT: no
-*/
-#define HW_USBCTRL_VFRAME           (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x174))
-#define BP_USBCTRL_VFRAME_EMPTY     0
-#define BM_USBCTRL_VFRAME_EMPTY     0xffffffff
-#define BF_USBCTRL_VFRAME_EMPTY(v)  (((v) << 0) & 0xffffffff)
-
-/**
- * Register: HW_USBCTRL_EPNAK
- * Address: 0x178
- * SCT: no
-*/
-#define HW_USBCTRL_EPNAK            (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x178))
-#define BP_USBCTRL_EPNAK_EPTN       16
-#define BM_USBCTRL_EPNAK_EPTN       0xffff0000
-#define BF_USBCTRL_EPNAK_EPTN(v)    (((v) << 16) & 0xffff0000)
-#define BP_USBCTRL_EPNAK_EPRN       0
-#define BM_USBCTRL_EPNAK_EPRN       0xffff
-#define BF_USBCTRL_EPNAK_EPRN(v)    (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_USBCTRL_EPNAKEN
- * Address: 0x17c
- * SCT: no
-*/
-#define HW_USBCTRL_EPNAKEN          (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x17c))
-#define BP_USBCTRL_EPNAKEN_EPTNE    16
-#define BM_USBCTRL_EPNAKEN_EPTNE    0xffff0000
-#define BF_USBCTRL_EPNAKEN_EPTNE(v) (((v) << 16) & 0xffff0000)
-#define BP_USBCTRL_EPNAKEN_EPRNE    0
-#define BM_USBCTRL_EPNAKEN_EPRNE    0xffff
-#define BF_USBCTRL_EPNAKEN_EPRNE(v) (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_USBCTRL_CONFIGFLAG
- * Address: 0x180
- * SCT: no
-*/
-#define HW_USBCTRL_CONFIGFLAG           (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x180))
-#define BP_USBCTRL_CONFIGFLAG_FLAG      0
-#define BM_USBCTRL_CONFIGFLAG_FLAG      0x1
-#define BF_USBCTRL_CONFIGFLAG_FLAG(v)   (((v) << 0) & 0x1)
-
-/**
- * Register: HW_USBCTRL_PORTSC1
- * Address: 0x184
- * SCT: no
-*/
-#define HW_USBCTRL_PORTSC1                      (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x184))
-#define BP_USBCTRL_PORTSC1_PTS                  30
-#define BM_USBCTRL_PORTSC1_PTS                  0xc0000000
-#define BV_USBCTRL_PORTSC1_PTS__UTMI            0x0
-#define BV_USBCTRL_PORTSC1_PTS__PHIL            0x1
-#define BV_USBCTRL_PORTSC1_PTS__ULPI            0x2
-#define BV_USBCTRL_PORTSC1_PTS__SERIAL          0x3
-#define BF_USBCTRL_PORTSC1_PTS(v)               (((v) << 30) & 0xc0000000)
-#define BF_USBCTRL_PORTSC1_PTS_V(v)             ((BV_USBCTRL_PORTSC1_PTS__##v << 30) & 0xc0000000)
-#define BP_USBCTRL_PORTSC1_STS                  29
-#define BM_USBCTRL_PORTSC1_STS                  0x20000000
-#define BF_USBCTRL_PORTSC1_STS(v)               (((v) << 29) & 0x20000000)
-#define BP_USBCTRL_PORTSC1_PTW                  28
-#define BM_USBCTRL_PORTSC1_PTW                  0x10000000
-#define BF_USBCTRL_PORTSC1_PTW(v)               (((v) << 28) & 0x10000000)
-#define BP_USBCTRL_PORTSC1_PSPD                 26
-#define BM_USBCTRL_PORTSC1_PSPD                 0xc000000
-#define BV_USBCTRL_PORTSC1_PSPD__FULL           0x0
-#define BV_USBCTRL_PORTSC1_PSPD__LO             0x1
-#define BV_USBCTRL_PORTSC1_PSPD__HI             0x2
-#define BF_USBCTRL_PORTSC1_PSPD(v)              (((v) << 26) & 0xc000000)
-#define BF_USBCTRL_PORTSC1_PSPD_V(v)            ((BV_USBCTRL_PORTSC1_PSPD__##v << 26) & 0xc000000)
-#define BP_USBCTRL_PORTSC1_PFSC                 24
-#define BM_USBCTRL_PORTSC1_PFSC                 0x1000000
-#define BF_USBCTRL_PORTSC1_PFSC(v)              (((v) << 24) & 0x1000000)
-#define BP_USBCTRL_PORTSC1_PHCD                 23
-#define BM_USBCTRL_PORTSC1_PHCD                 0x800000
-#define BF_USBCTRL_PORTSC1_PHCD(v)              (((v) << 23) & 0x800000)
-#define BP_USBCTRL_PORTSC1_WKOC                 22
-#define BM_USBCTRL_PORTSC1_WKOC                 0x400000
-#define BF_USBCTRL_PORTSC1_WKOC(v)              (((v) << 22) & 0x400000)
-#define BP_USBCTRL_PORTSC1_WKDS                 21
-#define BM_USBCTRL_PORTSC1_WKDS                 0x200000
-#define BF_USBCTRL_PORTSC1_WKDS(v)              (((v) << 21) & 0x200000)
-#define BP_USBCTRL_PORTSC1_WKCN                 20
-#define BM_USBCTRL_PORTSC1_WKCN                 0x100000
-#define BF_USBCTRL_PORTSC1_WKCN(v)              (((v) << 20) & 0x100000)
-#define BP_USBCTRL_PORTSC1_PTC                  16
-#define BM_USBCTRL_PORTSC1_PTC                  0xf0000
-#define BV_USBCTRL_PORTSC1_PTC__DISABLE         0x0
-#define BV_USBCTRL_PORTSC1_PTC__J               0x1
-#define BV_USBCTRL_PORTSC1_PTC__K               0x2
-#define BV_USBCTRL_PORTSC1_PTC__SE0orNAK        0x3
-#define BV_USBCTRL_PORTSC1_PTC__Packet          0x4
-#define BV_USBCTRL_PORTSC1_PTC__ForceEnableHS   0x5
-#define BV_USBCTRL_PORTSC1_PTC__ForceEnableFS   0x6
-#define BV_USBCTRL_PORTSC1_PTC__ForceEnableLS   0x7
-#define BF_USBCTRL_PORTSC1_PTC(v)               (((v) << 16) & 0xf0000)
-#define BF_USBCTRL_PORTSC1_PTC_V(v)             ((BV_USBCTRL_PORTSC1_PTC__##v << 16) & 0xf0000)
-#define BP_USBCTRL_PORTSC1_PIC                  14
-#define BM_USBCTRL_PORTSC1_PIC                  0xc000
-#define BV_USBCTRL_PORTSC1_PIC__OFF             0x0
-#define BV_USBCTRL_PORTSC1_PIC__AMBER           0x1
-#define BV_USBCTRL_PORTSC1_PIC__GREEN           0x2
-#define BV_USBCTRL_PORTSC1_PIC__UNDEF           0x3
-#define BF_USBCTRL_PORTSC1_PIC(v)               (((v) << 14) & 0xc000)
-#define BF_USBCTRL_PORTSC1_PIC_V(v)             ((BV_USBCTRL_PORTSC1_PIC__##v << 14) & 0xc000)
-#define BP_USBCTRL_PORTSC1_PO                   13
-#define BM_USBCTRL_PORTSC1_PO                   0x2000
-#define BF_USBCTRL_PORTSC1_PO(v)                (((v) << 13) & 0x2000)
-#define BP_USBCTRL_PORTSC1_PP                   12
-#define BM_USBCTRL_PORTSC1_PP                   0x1000
-#define BF_USBCTRL_PORTSC1_PP(v)                (((v) << 12) & 0x1000)
-#define BP_USBCTRL_PORTSC1_LS                   10
-#define BM_USBCTRL_PORTSC1_LS                   0xc00
-#define BV_USBCTRL_PORTSC1_LS__SE0              0x0
-#define BV_USBCTRL_PORTSC1_LS__K                0x1
-#define BV_USBCTRL_PORTSC1_LS__J                0x2
-#define BF_USBCTRL_PORTSC1_LS(v)                (((v) << 10) & 0xc00)
-#define BF_USBCTRL_PORTSC1_LS_V(v)              ((BV_USBCTRL_PORTSC1_LS__##v << 10) & 0xc00)
-#define BP_USBCTRL_PORTSC1_HSP                  9
-#define BM_USBCTRL_PORTSC1_HSP                  0x200
-#define BF_USBCTRL_PORTSC1_HSP(v)               (((v) << 9) & 0x200)
-#define BP_USBCTRL_PORTSC1_PR                   8
-#define BM_USBCTRL_PORTSC1_PR                   0x100
-#define BF_USBCTRL_PORTSC1_PR(v)                (((v) << 8) & 0x100)
-#define BP_USBCTRL_PORTSC1_SUSP                 7
-#define BM_USBCTRL_PORTSC1_SUSP                 0x80
-#define BF_USBCTRL_PORTSC1_SUSP(v)              (((v) << 7) & 0x80)
-#define BP_USBCTRL_PORTSC1_FPR                  6
-#define BM_USBCTRL_PORTSC1_FPR                  0x40
-#define BF_USBCTRL_PORTSC1_FPR(v)               (((v) << 6) & 0x40)
-#define BP_USBCTRL_PORTSC1_OCC                  5
-#define BM_USBCTRL_PORTSC1_OCC                  0x20
-#define BF_USBCTRL_PORTSC1_OCC(v)               (((v) << 5) & 0x20)
-#define BP_USBCTRL_PORTSC1_OCA                  4
-#define BM_USBCTRL_PORTSC1_OCA                  0x10
-#define BF_USBCTRL_PORTSC1_OCA(v)               (((v) << 4) & 0x10)
-#define BP_USBCTRL_PORTSC1_PEC                  3
-#define BM_USBCTRL_PORTSC1_PEC                  0x8
-#define BF_USBCTRL_PORTSC1_PEC(v)               (((v) << 3) & 0x8)
-#define BP_USBCTRL_PORTSC1_PE                   2
-#define BM_USBCTRL_PORTSC1_PE                   0x4
-#define BF_USBCTRL_PORTSC1_PE(v)                (((v) << 2) & 0x4)
-#define BP_USBCTRL_PORTSC1_CSC                  1
-#define BM_USBCTRL_PORTSC1_CSC                  0x2
-#define BF_USBCTRL_PORTSC1_CSC(v)               (((v) << 1) & 0x2)
-#define BP_USBCTRL_PORTSC1_CCS                  0
-#define BM_USBCTRL_PORTSC1_CCS                  0x1
-#define BF_USBCTRL_PORTSC1_CCS(v)               (((v) << 0) & 0x1)
-
-/**
- * Register: HW_USBCTRL_OTGSC
- * Address: 0x1a4
- * SCT: no
-*/
-#define HW_USBCTRL_OTGSC            (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x1a4))
-#define BP_USBCTRL_OTGSC_DPIE       30
-#define BM_USBCTRL_OTGSC_DPIE       0x40000000
-#define BF_USBCTRL_OTGSC_DPIE(v)    (((v) << 30) & 0x40000000)
-#define BP_USBCTRL_OTGSC_ONEMSE     29
-#define BM_USBCTRL_OTGSC_ONEMSE     0x20000000
-#define BF_USBCTRL_OTGSC_ONEMSE(v)  (((v) << 29) & 0x20000000)
-#define BP_USBCTRL_OTGSC_BSEIE      28
-#define BM_USBCTRL_OTGSC_BSEIE      0x10000000
-#define BF_USBCTRL_OTGSC_BSEIE(v)   (((v) << 28) & 0x10000000)
-#define BP_USBCTRL_OTGSC_BSVIE      27
-#define BM_USBCTRL_OTGSC_BSVIE      0x8000000
-#define BF_USBCTRL_OTGSC_BSVIE(v)   (((v) << 27) & 0x8000000)
-#define BP_USBCTRL_OTGSC_ASVIE      26
-#define BM_USBCTRL_OTGSC_ASVIE      0x4000000
-#define BF_USBCTRL_OTGSC_ASVIE(v)   (((v) << 26) & 0x4000000)
-#define BP_USBCTRL_OTGSC_AVVIE      25
-#define BM_USBCTRL_OTGSC_AVVIE      0x2000000
-#define BF_USBCTRL_OTGSC_AVVIE(v)   (((v) << 25) & 0x2000000)
-#define BP_USBCTRL_OTGSC_IDIE       24
-#define BM_USBCTRL_OTGSC_IDIE       0x1000000
-#define BF_USBCTRL_OTGSC_IDIE(v)    (((v) << 24) & 0x1000000)
-#define BP_USBCTRL_OTGSC_DPIS       22
-#define BM_USBCTRL_OTGSC_DPIS       0x400000
-#define BF_USBCTRL_OTGSC_DPIS(v)    (((v) << 22) & 0x400000)
-#define BP_USBCTRL_OTGSC_ONEMSS     21
-#define BM_USBCTRL_OTGSC_ONEMSS     0x200000
-#define BF_USBCTRL_OTGSC_ONEMSS(v)  (((v) << 21) & 0x200000)
-#define BP_USBCTRL_OTGSC_BSEIS      20
-#define BM_USBCTRL_OTGSC_BSEIS      0x100000
-#define BF_USBCTRL_OTGSC_BSEIS(v)   (((v) << 20) & 0x100000)
-#define BP_USBCTRL_OTGSC_BSVIS      19
-#define BM_USBCTRL_OTGSC_BSVIS      0x80000
-#define BF_USBCTRL_OTGSC_BSVIS(v)   (((v) << 19) & 0x80000)
-#define BP_USBCTRL_OTGSC_ASVIS      18
-#define BM_USBCTRL_OTGSC_ASVIS      0x40000
-#define BF_USBCTRL_OTGSC_ASVIS(v)   (((v) << 18) & 0x40000)
-#define BP_USBCTRL_OTGSC_AVVIS      17
-#define BM_USBCTRL_OTGSC_AVVIS      0x20000
-#define BF_USBCTRL_OTGSC_AVVIS(v)   (((v) << 17) & 0x20000)
-#define BP_USBCTRL_OTGSC_IDIS       16
-#define BM_USBCTRL_OTGSC_IDIS       0x10000
-#define BF_USBCTRL_OTGSC_IDIS(v)    (((v) << 16) & 0x10000)
-#define BP_USBCTRL_OTGSC_DPS        14
-#define BM_USBCTRL_OTGSC_DPS        0x4000
-#define BF_USBCTRL_OTGSC_DPS(v)     (((v) << 14) & 0x4000)
-#define BP_USBCTRL_OTGSC_ONEMST     13
-#define BM_USBCTRL_OTGSC_ONEMST     0x2000
-#define BF_USBCTRL_OTGSC_ONEMST(v)  (((v) << 13) & 0x2000)
-#define BP_USBCTRL_OTGSC_BSE        12
-#define BM_USBCTRL_OTGSC_BSE        0x1000
-#define BF_USBCTRL_OTGSC_BSE(v)     (((v) << 12) & 0x1000)
-#define BP_USBCTRL_OTGSC_BSV        11
-#define BM_USBCTRL_OTGSC_BSV        0x800
-#define BF_USBCTRL_OTGSC_BSV(v)     (((v) << 11) & 0x800)
-#define BP_USBCTRL_OTGSC_ASV        10
-#define BM_USBCTRL_OTGSC_ASV        0x400
-#define BF_USBCTRL_OTGSC_ASV(v)     (((v) << 10) & 0x400)
-#define BP_USBCTRL_OTGSC_AVV        9
-#define BM_USBCTRL_OTGSC_AVV        0x200
-#define BF_USBCTRL_OTGSC_AVV(v)     (((v) << 9) & 0x200)
-#define BP_USBCTRL_OTGSC_ID         8
-#define BM_USBCTRL_OTGSC_ID         0x100
-#define BF_USBCTRL_OTGSC_ID(v)      (((v) << 8) & 0x100)
-#define BP_USBCTRL_OTGSC_HABA       7
-#define BM_USBCTRL_OTGSC_HABA       0x80
-#define BF_USBCTRL_OTGSC_HABA(v)    (((v) << 7) & 0x80)
-#define BP_USBCTRL_OTGSC_HADP       6
-#define BM_USBCTRL_OTGSC_HADP       0x40
-#define BF_USBCTRL_OTGSC_HADP(v)    (((v) << 6) & 0x40)
-#define BP_USBCTRL_OTGSC_IDPU       5
-#define BM_USBCTRL_OTGSC_IDPU       0x20
-#define BF_USBCTRL_OTGSC_IDPU(v)    (((v) << 5) & 0x20)
-#define BP_USBCTRL_OTGSC_DP         4
-#define BM_USBCTRL_OTGSC_DP         0x10
-#define BF_USBCTRL_OTGSC_DP(v)      (((v) << 4) & 0x10)
-#define BP_USBCTRL_OTGSC_OT         3
-#define BM_USBCTRL_OTGSC_OT         0x8
-#define BF_USBCTRL_OTGSC_OT(v)      (((v) << 3) & 0x8)
-#define BP_USBCTRL_OTGSC_HAAR       2
-#define BM_USBCTRL_OTGSC_HAAR       0x4
-#define BF_USBCTRL_OTGSC_HAAR(v)    (((v) << 2) & 0x4)
-#define BP_USBCTRL_OTGSC_VC         1
-#define BM_USBCTRL_OTGSC_VC         0x2
-#define BF_USBCTRL_OTGSC_VC(v)      (((v) << 1) & 0x2)
-#define BP_USBCTRL_OTGSC_VD         0
-#define BM_USBCTRL_OTGSC_VD         0x1
-#define BF_USBCTRL_OTGSC_VD(v)      (((v) << 0) & 0x1)
-
-/**
- * Register: HW_USBCTRL_USBMODE
- * Address: 0x1a8
- * SCT: no
-*/
-#define HW_USBCTRL_USBMODE              (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x1a8))
-#define BP_USBCTRL_USBMODE_SDIS         4
-#define BM_USBCTRL_USBMODE_SDIS         0x10
-#define BF_USBCTRL_USBMODE_SDIS(v)      (((v) << 4) & 0x10)
-#define BP_USBCTRL_USBMODE_SLOM         3
-#define BM_USBCTRL_USBMODE_SLOM         0x8
-#define BF_USBCTRL_USBMODE_SLOM(v)      (((v) << 3) & 0x8)
-#define BP_USBCTRL_USBMODE_ES           2
-#define BM_USBCTRL_USBMODE_ES           0x4
-#define BF_USBCTRL_USBMODE_ES(v)        (((v) << 2) & 0x4)
-#define BP_USBCTRL_USBMODE_CM           0
-#define BM_USBCTRL_USBMODE_CM           0x3
-#define BV_USBCTRL_USBMODE_CM__IDLE     0x0
-#define BV_USBCTRL_USBMODE_CM__DEVICE   0x2
-#define BV_USBCTRL_USBMODE_CM__HOST     0x3
-#define BF_USBCTRL_USBMODE_CM(v)        (((v) << 0) & 0x3)
-#define BF_USBCTRL_USBMODE_CM_V(v)      ((BV_USBCTRL_USBMODE_CM__##v << 0) & 0x3)
-
-/**
- * Register: HW_USBCTRL_ENDPTSETUPSTAT
- * Address: 0x1ac
- * SCT: no
-*/
-#define HW_USBCTRL_ENDPTSETUPSTAT           (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x1ac))
-#define BP_USBCTRL_ENDPTSETUPSTAT_STS       0
-#define BM_USBCTRL_ENDPTSETUPSTAT_STS       0xffff
-#define BF_USBCTRL_ENDPTSETUPSTAT_STS(v)    (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_USBCTRL_ENDPTPRIME
- * Address: 0x1b0
- * SCT: no
-*/
-#define HW_USBCTRL_ENDPTPRIME           (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x1b0))
-#define BP_USBCTRL_ENDPTPRIME_PETB      16
-#define BM_USBCTRL_ENDPTPRIME_PETB      0xffff0000
-#define BF_USBCTRL_ENDPTPRIME_PETB(v)   (((v) << 16) & 0xffff0000)
-#define BP_USBCTRL_ENDPTPRIME_PERB      0
-#define BM_USBCTRL_ENDPTPRIME_PERB      0xffff
-#define BF_USBCTRL_ENDPTPRIME_PERB(v)   (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_USBCTRL_ENDPTFLUSH
- * Address: 0x1b4
- * SCT: no
-*/
-#define HW_USBCTRL_ENDPTFLUSH           (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x1b4))
-#define BP_USBCTRL_ENDPTFLUSH_FETB      16
-#define BM_USBCTRL_ENDPTFLUSH_FETB      0xffff0000
-#define BF_USBCTRL_ENDPTFLUSH_FETB(v)   (((v) << 16) & 0xffff0000)
-#define BP_USBCTRL_ENDPTFLUSH_FERB      0
-#define BM_USBCTRL_ENDPTFLUSH_FERB      0xffff
-#define BF_USBCTRL_ENDPTFLUSH_FERB(v)   (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_USBCTRL_ENDPTSTATUS
- * Address: 0x1b8
- * SCT: no
-*/
-#define HW_USBCTRL_ENDPTSTATUS          (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x1b8))
-#define BP_USBCTRL_ENDPTSTATUS_ETBR     16
-#define BM_USBCTRL_ENDPTSTATUS_ETBR     0xffff0000
-#define BF_USBCTRL_ENDPTSTATUS_ETBR(v)  (((v) << 16) & 0xffff0000)
-#define BP_USBCTRL_ENDPTSTATUS_ERBR     0
-#define BM_USBCTRL_ENDPTSTATUS_ERBR     0xffff
-#define BF_USBCTRL_ENDPTSTATUS_ERBR(v)  (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_USBCTRL_ENDPTCOMPLETE
- * Address: 0x1bc
- * SCT: no
-*/
-#define HW_USBCTRL_ENDPTCOMPLETE            (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x1bc))
-#define BP_USBCTRL_ENDPTCOMPLETE_ETCE       16
-#define BM_USBCTRL_ENDPTCOMPLETE_ETCE       0xffff0000
-#define BF_USBCTRL_ENDPTCOMPLETE_ETCE(v)    (((v) << 16) & 0xffff0000)
-#define BP_USBCTRL_ENDPTCOMPLETE_ERCE       0
-#define BM_USBCTRL_ENDPTCOMPLETE_ERCE       0xffff
-#define BF_USBCTRL_ENDPTCOMPLETE_ERCE(v)    (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_USBCTRL_ENDPTCTRLn
- * Address: 0x1c0+n*0x4
- * SCT: no
-*/
-#define HW_USBCTRL_ENDPTCTRLn(n)                (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x1c0+(n)*0x4))
-#define BP_USBCTRL_ENDPTCTRLn_TXE               23
-#define BM_USBCTRL_ENDPTCTRLn_TXE               0x800000
-#define BF_USBCTRL_ENDPTCTRLn_TXE(v)            (((v) << 23) & 0x800000)
-#define BP_USBCTRL_ENDPTCTRLn_TXR               22
-#define BM_USBCTRL_ENDPTCTRLn_TXR               0x400000
-#define BF_USBCTRL_ENDPTCTRLn_TXR(v)            (((v) << 22) & 0x400000)
-#define BP_USBCTRL_ENDPTCTRLn_TXI               21
-#define BM_USBCTRL_ENDPTCTRLn_TXI               0x200000
-#define BF_USBCTRL_ENDPTCTRLn_TXI(v)            (((v) << 21) & 0x200000)
-#define BP_USBCTRL_ENDPTCTRLn_TXT               18
-#define BM_USBCTRL_ENDPTCTRLn_TXT               0xc0000
-#define BV_USBCTRL_ENDPTCTRLn_TXT__ISOCHRONOUS  0x1
-#define BV_USBCTRL_ENDPTCTRLn_TXT__BULK         0x2
-#define BV_USBCTRL_ENDPTCTRLn_TXT__INT          0x3
-#define BF_USBCTRL_ENDPTCTRLn_TXT(v)            (((v) << 18) & 0xc0000)
-#define BF_USBCTRL_ENDPTCTRLn_TXT_V(v)          ((BV_USBCTRL_ENDPTCTRLn_TXT__##v << 18) & 0xc0000)
-#define BP_USBCTRL_ENDPTCTRLn_TXS               16
-#define BM_USBCTRL_ENDPTCTRLn_TXS               0x10000
-#define BF_USBCTRL_ENDPTCTRLn_TXS(v)            (((v) << 16) & 0x10000)
-#define BP_USBCTRL_ENDPTCTRLn_RXE               7
-#define BM_USBCTRL_ENDPTCTRLn_RXE               0x80
-#define BF_USBCTRL_ENDPTCTRLn_RXE(v)            (((v) << 7) & 0x80)
-#define BP_USBCTRL_ENDPTCTRLn_RXR               6
-#define BM_USBCTRL_ENDPTCTRLn_RXR               0x40
-#define BF_USBCTRL_ENDPTCTRLn_RXR(v)            (((v) << 6) & 0x40)
-#define BP_USBCTRL_ENDPTCTRLn_RXI               5
-#define BM_USBCTRL_ENDPTCTRLn_RXI               0x20
-#define BF_USBCTRL_ENDPTCTRLn_RXI(v)            (((v) << 5) & 0x20)
-#define BP_USBCTRL_ENDPTCTRLn_RXT               2
-#define BM_USBCTRL_ENDPTCTRLn_RXT               0xc
-#define BF_USBCTRL_ENDPTCTRLn_RXT(v)            (((v) << 2) & 0xc)
-#define BP_USBCTRL_ENDPTCTRLn_RXS               0
-#define BM_USBCTRL_ENDPTCTRLn_RXS               0x1
-#define BF_USBCTRL_ENDPTCTRLn_RXS(v)            (((v) << 0) & 0x1)
-
-#endif /* __HEADERGEN__STMP3700__USBCTRL__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-usbphy.h b/firmware/target/arm/imx233/regs/stmp3700/regs-usbphy.h
deleted file mode 100644
index af183fc6c9..0000000000
--- a/firmware/target/arm/imx233/regs/stmp3700/regs-usbphy.h
+++ /dev/null
@@ -1,300 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: stmp3700:3.2.0
- *
- * Copyright (C) 2013 by Amaury Pouly
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#ifndef __HEADERGEN__STMP3700__USBPHY__H__
-#define __HEADERGEN__STMP3700__USBPHY__H__
-
-#define REGS_USBPHY_BASE (0x8007c000)
-
-#define REGS_USBPHY_VERSION "3.2.0"
-
-/**
- * Register: HW_USBPHY_PWD
- * Address: 0
- * SCT: yes
-*/
-#define HW_USBPHY_PWD               (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x0 + 0x0))
-#define HW_USBPHY_PWD_SET           (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x0 + 0x4))
-#define HW_USBPHY_PWD_CLR           (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x0 + 0x8))
-#define HW_USBPHY_PWD_TOG           (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x0 + 0xc))
-#define BP_USBPHY_PWD_RXPWDRX       20
-#define BM_USBPHY_PWD_RXPWDRX       0x100000
-#define BF_USBPHY_PWD_RXPWDRX(v)    (((v) << 20) & 0x100000)
-#define BP_USBPHY_PWD_RXPWDDIFF     19
-#define BM_USBPHY_PWD_RXPWDDIFF     0x80000
-#define BF_USBPHY_PWD_RXPWDDIFF(v)  (((v) << 19) & 0x80000)
-#define BP_USBPHY_PWD_RXPWD1PT1     18
-#define BM_USBPHY_PWD_RXPWD1PT1     0x40000
-#define BF_USBPHY_PWD_RXPWD1PT1(v)  (((v) << 18) & 0x40000)
-#define BP_USBPHY_PWD_RXPWDENV      17
-#define BM_USBPHY_PWD_RXPWDENV      0x20000
-#define BF_USBPHY_PWD_RXPWDENV(v)   (((v) << 17) & 0x20000)
-#define BP_USBPHY_PWD_TXPWDCOMP     14
-#define BM_USBPHY_PWD_TXPWDCOMP     0x4000
-#define BF_USBPHY_PWD_TXPWDCOMP(v)  (((v) << 14) & 0x4000)
-#define BP_USBPHY_PWD_TXPWDVBG      13
-#define BM_USBPHY_PWD_TXPWDVBG      0x2000
-#define BF_USBPHY_PWD_TXPWDVBG(v)   (((v) << 13) & 0x2000)
-#define BP_USBPHY_PWD_TXPWDV2I      12
-#define BM_USBPHY_PWD_TXPWDV2I      0x1000
-#define BF_USBPHY_PWD_TXPWDV2I(v)   (((v) << 12) & 0x1000)
-#define BP_USBPHY_PWD_TXPWDIBIAS    11
-#define BM_USBPHY_PWD_TXPWDIBIAS    0x800
-#define BF_USBPHY_PWD_TXPWDIBIAS(v) (((v) << 11) & 0x800)
-#define BP_USBPHY_PWD_TXPWDFS       10
-#define BM_USBPHY_PWD_TXPWDFS       0x400
-#define BF_USBPHY_PWD_TXPWDFS(v)    (((v) << 10) & 0x400)
-
-/**
- * Register: HW_USBPHY_TX
- * Address: 0x10
- * SCT: yes
-*/
-#define HW_USBPHY_TX                            (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x10 + 0x0))
-#define HW_USBPHY_TX_SET                        (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x10 + 0x4))
-#define HW_USBPHY_TX_CLR                        (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x10 + 0x8))
-#define HW_USBPHY_TX_TOG                        (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x10 + 0xc))
-#define BP_USBPHY_TX_USBPHY_TX_EDGECTRL         26
-#define BM_USBPHY_TX_USBPHY_TX_EDGECTRL         0x1c000000
-#define BF_USBPHY_TX_USBPHY_TX_EDGECTRL(v)      (((v) << 26) & 0x1c000000)
-#define BP_USBPHY_TX_USBPHY_TX_SYNC_INVERT      25
-#define BM_USBPHY_TX_USBPHY_TX_SYNC_INVERT      0x2000000
-#define BF_USBPHY_TX_USBPHY_TX_SYNC_INVERT(v)   (((v) << 25) & 0x2000000)
-#define BP_USBPHY_TX_USBPHY_TX_SYNC_MUX         24
-#define BM_USBPHY_TX_USBPHY_TX_SYNC_MUX         0x1000000
-#define BF_USBPHY_TX_USBPHY_TX_SYNC_MUX(v)      (((v) << 24) & 0x1000000)
-#define BP_USBPHY_TX_TXCMPOUT_STATUS            23
-#define BM_USBPHY_TX_TXCMPOUT_STATUS            0x800000
-#define BF_USBPHY_TX_TXCMPOUT_STATUS(v)         (((v) << 23) & 0x800000)
-#define BP_USBPHY_TX_TXENCAL45DP                21
-#define BM_USBPHY_TX_TXENCAL45DP                0x200000
-#define BF_USBPHY_TX_TXENCAL45DP(v)             (((v) << 21) & 0x200000)
-#define BP_USBPHY_TX_TXCAL45DP                  16
-#define BM_USBPHY_TX_TXCAL45DP                  0xf0000
-#define BF_USBPHY_TX_TXCAL45DP(v)               (((v) << 16) & 0xf0000)
-#define BP_USBPHY_TX_TXENCAL45DN                13
-#define BM_USBPHY_TX_TXENCAL45DN                0x2000
-#define BF_USBPHY_TX_TXENCAL45DN(v)             (((v) << 13) & 0x2000)
-#define BP_USBPHY_TX_TXCAL45DN                  8
-#define BM_USBPHY_TX_TXCAL45DN                  0xf00
-#define BF_USBPHY_TX_TXCAL45DN(v)               (((v) << 8) & 0xf00)
-#define BP_USBPHY_TX_TXCALIBRATE                7
-#define BM_USBPHY_TX_TXCALIBRATE                0x80
-#define BF_USBPHY_TX_TXCALIBRATE(v)             (((v) << 7) & 0x80)
-#define BP_USBPHY_TX_D_CAL                      0
-#define BM_USBPHY_TX_D_CAL                      0xf
-#define BF_USBPHY_TX_D_CAL(v)                   (((v) << 0) & 0xf)
-
-/**
- * Register: HW_USBPHY_RX
- * Address: 0x20
- * SCT: yes
-*/
-#define HW_USBPHY_RX                (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x20 + 0x0))
-#define HW_USBPHY_RX_SET            (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x20 + 0x4))
-#define HW_USBPHY_RX_CLR            (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x20 + 0x8))
-#define HW_USBPHY_RX_TOG            (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x20 + 0xc))
-#define BP_USBPHY_RX_RXDBYPASS      22
-#define BM_USBPHY_RX_RXDBYPASS      0x400000
-#define BF_USBPHY_RX_RXDBYPASS(v)   (((v) << 22) & 0x400000)
-#define BP_USBPHY_RX_DISCONADJ      4
-#define BM_USBPHY_RX_DISCONADJ      0x30
-#define BF_USBPHY_RX_DISCONADJ(v)   (((v) << 4) & 0x30)
-#define BP_USBPHY_RX_ENVADJ         0
-#define BM_USBPHY_RX_ENVADJ         0x3
-#define BF_USBPHY_RX_ENVADJ(v)      (((v) << 0) & 0x3)
-
-/**
- * Register: HW_USBPHY_CTRL
- * Address: 0x30
- * SCT: yes
-*/
-#define HW_USBPHY_CTRL                          (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x30 + 0x0))
-#define HW_USBPHY_CTRL_SET                      (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x30 + 0x4))
-#define HW_USBPHY_CTRL_CLR                      (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x30 + 0x8))
-#define HW_USBPHY_CTRL_TOG                      (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x30 + 0xc))
-#define BP_USBPHY_CTRL_SFTRST                   31
-#define BM_USBPHY_CTRL_SFTRST                   0x80000000
-#define BF_USBPHY_CTRL_SFTRST(v)                (((v) << 31) & 0x80000000)
-#define BP_USBPHY_CTRL_CLKGATE                  30
-#define BM_USBPHY_CTRL_CLKGATE                  0x40000000
-#define BF_USBPHY_CTRL_CLKGATE(v)               (((v) << 30) & 0x40000000)
-#define BP_USBPHY_CTRL_UTMI_SUSPENDM            29
-#define BM_USBPHY_CTRL_UTMI_SUSPENDM            0x20000000
-#define BF_USBPHY_CTRL_UTMI_SUSPENDM(v)         (((v) << 29) & 0x20000000)
-#define BP_USBPHY_CTRL_HOST_FORCE_LS_SE0        28
-#define BM_USBPHY_CTRL_HOST_FORCE_LS_SE0        0x10000000
-#define BF_USBPHY_CTRL_HOST_FORCE_LS_SE0(v)     (((v) << 28) & 0x10000000)
-#define BP_USBPHY_CTRL_DATA_ON_LRADC            13
-#define BM_USBPHY_CTRL_DATA_ON_LRADC            0x2000
-#define BF_USBPHY_CTRL_DATA_ON_LRADC(v)         (((v) << 13) & 0x2000)
-#define BP_USBPHY_CTRL_DEVPLUGIN_IRQ            12
-#define BM_USBPHY_CTRL_DEVPLUGIN_IRQ            0x1000
-#define BF_USBPHY_CTRL_DEVPLUGIN_IRQ(v)         (((v) << 12) & 0x1000)
-#define BP_USBPHY_CTRL_ENIRQDEVPLUGIN           11
-#define BM_USBPHY_CTRL_ENIRQDEVPLUGIN           0x800
-#define BF_USBPHY_CTRL_ENIRQDEVPLUGIN(v)        (((v) << 11) & 0x800)
-#define BP_USBPHY_CTRL_RESUME_IRQ               10
-#define BM_USBPHY_CTRL_RESUME_IRQ               0x400
-#define BF_USBPHY_CTRL_RESUME_IRQ(v)            (((v) << 10) & 0x400)
-#define BP_USBPHY_CTRL_ENIRQRESUMEDETECT        9
-#define BM_USBPHY_CTRL_ENIRQRESUMEDETECT        0x200
-#define BF_USBPHY_CTRL_ENIRQRESUMEDETECT(v)     (((v) << 9) & 0x200)
-#define BP_USBPHY_CTRL_ENOTGIDDETECT            7
-#define BM_USBPHY_CTRL_ENOTGIDDETECT            0x80
-#define BF_USBPHY_CTRL_ENOTGIDDETECT(v)         (((v) << 7) & 0x80)
-#define BP_USBPHY_CTRL_DEVPLUGIN_POLARITY       5
-#define BM_USBPHY_CTRL_DEVPLUGIN_POLARITY       0x20
-#define BF_USBPHY_CTRL_DEVPLUGIN_POLARITY(v)    (((v) << 5) & 0x20)
-#define BP_USBPHY_CTRL_ENDEVPLUGINDETECT        4
-#define BM_USBPHY_CTRL_ENDEVPLUGINDETECT        0x10
-#define BF_USBPHY_CTRL_ENDEVPLUGINDETECT(v)     (((v) << 4) & 0x10)
-#define BP_USBPHY_CTRL_HOSTDISCONDETECT_IRQ     3
-#define BM_USBPHY_CTRL_HOSTDISCONDETECT_IRQ     0x8
-#define BF_USBPHY_CTRL_HOSTDISCONDETECT_IRQ(v)  (((v) << 3) & 0x8)
-#define BP_USBPHY_CTRL_ENIRQHOSTDISCON          2
-#define BM_USBPHY_CTRL_ENIRQHOSTDISCON          0x4
-#define BF_USBPHY_CTRL_ENIRQHOSTDISCON(v)       (((v) << 2) & 0x4)
-#define BP_USBPHY_CTRL_ENHOSTDISCONDETECT       1
-#define BM_USBPHY_CTRL_ENHOSTDISCONDETECT       0x2
-#define BF_USBPHY_CTRL_ENHOSTDISCONDETECT(v)    (((v) << 1) & 0x2)
-#define BP_USBPHY_CTRL_ENHSPRECHARGEXMIT        0
-#define BM_USBPHY_CTRL_ENHSPRECHARGEXMIT        0x1
-#define BF_USBPHY_CTRL_ENHSPRECHARGEXMIT(v)     (((v) << 0) & 0x1)
-
-/**
- * Register: HW_USBPHY_STATUS
- * Address: 0x40
- * SCT: no
-*/
-#define HW_USBPHY_STATUS                            (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x40))
-#define BP_USBPHY_STATUS_RESUME_STATUS              10
-#define BM_USBPHY_STATUS_RESUME_STATUS              0x400
-#define BF_USBPHY_STATUS_RESUME_STATUS(v)           (((v) << 10) & 0x400)
-#define BP_USBPHY_STATUS_OTGID_STATUS               8
-#define BM_USBPHY_STATUS_OTGID_STATUS               0x100
-#define BF_USBPHY_STATUS_OTGID_STATUS(v)            (((v) << 8) & 0x100)
-#define BP_USBPHY_STATUS_DEVPLUGIN_STATUS           6
-#define BM_USBPHY_STATUS_DEVPLUGIN_STATUS           0x40
-#define BF_USBPHY_STATUS_DEVPLUGIN_STATUS(v)        (((v) << 6) & 0x40)
-#define BP_USBPHY_STATUS_HOSTDISCONDETECT_STATUS    3
-#define BM_USBPHY_STATUS_HOSTDISCONDETECT_STATUS    0x8
-#define BF_USBPHY_STATUS_HOSTDISCONDETECT_STATUS(v) (((v) << 3) & 0x8)
-
-/**
- * Register: HW_USBPHY_DEBUG
- * Address: 0x50
- * SCT: yes
-*/
-#define HW_USBPHY_DEBUG                         (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x50 + 0x0))
-#define HW_USBPHY_DEBUG_SET                     (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x50 + 0x4))
-#define HW_USBPHY_DEBUG_CLR                     (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x50 + 0x8))
-#define HW_USBPHY_DEBUG_TOG                     (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x50 + 0xc))
-#define BP_USBPHY_DEBUG_CLKGATE                 30
-#define BM_USBPHY_DEBUG_CLKGATE                 0x40000000
-#define BF_USBPHY_DEBUG_CLKGATE(v)              (((v) << 30) & 0x40000000)
-#define BP_USBPHY_DEBUG_HOST_RESUME_DEBUG       29
-#define BM_USBPHY_DEBUG_HOST_RESUME_DEBUG       0x20000000
-#define BF_USBPHY_DEBUG_HOST_RESUME_DEBUG(v)    (((v) << 29) & 0x20000000)
-#define BP_USBPHY_DEBUG_SQUELCHRESETLENGTH      25
-#define BM_USBPHY_DEBUG_SQUELCHRESETLENGTH      0x1e000000
-#define BF_USBPHY_DEBUG_SQUELCHRESETLENGTH(v)   (((v) << 25) & 0x1e000000)
-#define BP_USBPHY_DEBUG_ENSQUELCHRESET          24
-#define BM_USBPHY_DEBUG_ENSQUELCHRESET          0x1000000
-#define BF_USBPHY_DEBUG_ENSQUELCHRESET(v)       (((v) << 24) & 0x1000000)
-#define BP_USBPHY_DEBUG_SQUELCHRESETCOUNT       16
-#define BM_USBPHY_DEBUG_SQUELCHRESETCOUNT       0x1f0000
-#define BF_USBPHY_DEBUG_SQUELCHRESETCOUNT(v)    (((v) << 16) & 0x1f0000)
-#define BP_USBPHY_DEBUG_ENTX2RXCOUNT            12
-#define BM_USBPHY_DEBUG_ENTX2RXCOUNT            0x1000
-#define BF_USBPHY_DEBUG_ENTX2RXCOUNT(v)         (((v) << 12) & 0x1000)
-#define BP_USBPHY_DEBUG_TX2RXCOUNT              8
-#define BM_USBPHY_DEBUG_TX2RXCOUNT              0xf00
-#define BF_USBPHY_DEBUG_TX2RXCOUNT(v)           (((v) << 8) & 0xf00)
-#define BP_USBPHY_DEBUG_ENHSTPULLDOWN           4
-#define BM_USBPHY_DEBUG_ENHSTPULLDOWN           0x30
-#define BF_USBPHY_DEBUG_ENHSTPULLDOWN(v)        (((v) << 4) & 0x30)
-#define BP_USBPHY_DEBUG_HSTPULLDOWN             2
-#define BM_USBPHY_DEBUG_HSTPULLDOWN             0xc
-#define BF_USBPHY_DEBUG_HSTPULLDOWN(v)          (((v) << 2) & 0xc)
-#define BP_USBPHY_DEBUG_DEBUG_INTERFACE_HOLD    1
-#define BM_USBPHY_DEBUG_DEBUG_INTERFACE_HOLD    0x2
-#define BF_USBPHY_DEBUG_DEBUG_INTERFACE_HOLD(v) (((v) << 1) & 0x2)
-#define BP_USBPHY_DEBUG_OTGIDPIOLOCK            0
-#define BM_USBPHY_DEBUG_OTGIDPIOLOCK            0x1
-#define BF_USBPHY_DEBUG_OTGIDPIOLOCK(v)         (((v) << 0) & 0x1)
-
-/**
- * Register: HW_USBPHY_DEBUG0_STATUS
- * Address: 0x60
- * SCT: no
-*/
-#define HW_USBPHY_DEBUG0_STATUS                             (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x60))
-#define BP_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT               26
-#define BM_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT               0xfc000000
-#define BF_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT(v)            (((v) << 26) & 0xfc000000)
-#define BP_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT     16
-#define BM_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT     0x3ff0000
-#define BF_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT(v)  (((v) << 16) & 0x3ff0000)
-#define BP_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT        0
-#define BM_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT        0xffff
-#define BF_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT(v)     (((v) << 0) & 0xffff)
-
-/**
- * Register: HW_USBPHY_DEBUG1
- * Address: 0x70
- * SCT: yes
-*/
-#define HW_USBPHY_DEBUG1                (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x70 + 0x0))
-#define HW_USBPHY_DEBUG1_SET            (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x70 + 0x4))
-#define HW_USBPHY_DEBUG1_CLR            (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x70 + 0x8))
-#define HW_USBPHY_DEBUG1_TOG            (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x70 + 0xc))
-#define BP_USBPHY_DEBUG1_ENTAILADJVD    13
-#define BM_USBPHY_DEBUG1_ENTAILADJVD    0x6000
-#define BF_USBPHY_DEBUG1_ENTAILADJVD(v) (((v) << 13) & 0x6000)
-#define BP_USBPHY_DEBUG1_ENTX2TX        12
-#define BM_USBPHY_DEBUG1_ENTX2TX        0x1000
-#define BF_USBPHY_DEBUG1_ENTX2TX(v)     (((v) << 12) & 0x1000)
-#define BP_USBPHY_DEBUG1_PLL_IS_240     8
-#define BM_USBPHY_DEBUG1_PLL_IS_240     0x100
-#define BF_USBPHY_DEBUG1_PLL_IS_240(v)  (((v) << 8) & 0x100)
-#define BP_USBPHY_DEBUG1_DBG_ADDRESS    0
-#define BM_USBPHY_DEBUG1_DBG_ADDRESS    0xf
-#define BF_USBPHY_DEBUG1_DBG_ADDRESS(v) (((v) << 0) & 0xf)
-
-/**
- * Register: HW_USBPHY_VERSION
- * Address: 0x80
- * SCT: no
-*/
-#define HW_USBPHY_VERSION           (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x80))
-#define BP_USBPHY_VERSION_MAJOR     24
-#define BM_USBPHY_VERSION_MAJOR     0xff000000
-#define BF_USBPHY_VERSION_MAJOR(v)  (((v) << 24) & 0xff000000)
-#define BP_USBPHY_VERSION_MINOR     16
-#define BM_USBPHY_VERSION_MINOR     0xff0000
-#define BF_USBPHY_VERSION_MINOR(v)  (((v) << 16) & 0xff0000)
-#define BP_USBPHY_VERSION_STEP      0
-#define BM_USBPHY_VERSION_STEP      0xffff
-#define BF_USBPHY_VERSION_STEP(v)   (((v) << 0) & 0xffff)
-
-#endif /* __HEADERGEN__STMP3700__USBPHY__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3700/rtc.h b/firmware/target/arm/imx233/regs/stmp3700/rtc.h
new file mode 100644
index 0000000000..8877ff5d13
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3700/rtc.h
@@ -0,0 +1,570 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * stmp3700 version: 2.4.0
+ * stmp3700 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_STMP3700_RTC_H__
+#define __HEADERGEN_STMP3700_RTC_H__
+
+#define HW_RTC_CTRL                             HW(RTC_CTRL)
+#define HWA_RTC_CTRL                            (0x8005c000 + 0x0)
+#define HWT_RTC_CTRL                            HWIO_32_RW
+#define HWN_RTC_CTRL                            RTC_CTRL
+#define HWI_RTC_CTRL                            
+#define HW_RTC_CTRL_SET                         HW(RTC_CTRL_SET)
+#define HWA_RTC_CTRL_SET                        (HWA_RTC_CTRL + 0x4)
+#define HWT_RTC_CTRL_SET                        HWIO_32_WO
+#define HWN_RTC_CTRL_SET                        RTC_CTRL
+#define HWI_RTC_CTRL_SET                        
+#define HW_RTC_CTRL_CLR                         HW(RTC_CTRL_CLR)
+#define HWA_RTC_CTRL_CLR                        (HWA_RTC_CTRL + 0x8)
+#define HWT_RTC_CTRL_CLR                        HWIO_32_WO
+#define HWN_RTC_CTRL_CLR                        RTC_CTRL
+#define HWI_RTC_CTRL_CLR                        
+#define HW_RTC_CTRL_TOG                         HW(RTC_CTRL_TOG)
+#define HWA_RTC_CTRL_TOG                        (HWA_RTC_CTRL + 0xc)
+#define HWT_RTC_CTRL_TOG                        HWIO_32_WO
+#define HWN_RTC_CTRL_TOG                        RTC_CTRL
+#define HWI_RTC_CTRL_TOG                        
+#define BP_RTC_CTRL_SFTRST                      31
+#define BM_RTC_CTRL_SFTRST                      0x80000000
+#define BF_RTC_CTRL_SFTRST(v)                   (((v) & 0x1) << 31)
+#define BFM_RTC_CTRL_SFTRST(v)                  BM_RTC_CTRL_SFTRST
+#define BF_RTC_CTRL_SFTRST_V(e)                 BF_RTC_CTRL_SFTRST(BV_RTC_CTRL_SFTRST__##e)
+#define BFM_RTC_CTRL_SFTRST_V(v)                BM_RTC_CTRL_SFTRST
+#define BP_RTC_CTRL_CLKGATE                     30
+#define BM_RTC_CTRL_CLKGATE                     0x40000000
+#define BF_RTC_CTRL_CLKGATE(v)                  (((v) & 0x1) << 30)
+#define BFM_RTC_CTRL_CLKGATE(v)                 BM_RTC_CTRL_CLKGATE
+#define BF_RTC_CTRL_CLKGATE_V(e)                BF_RTC_CTRL_CLKGATE(BV_RTC_CTRL_CLKGATE__##e)
+#define BFM_RTC_CTRL_CLKGATE_V(v)               BM_RTC_CTRL_CLKGATE
+#define BP_RTC_CTRL_SUPPRESS_COPY2ANALOG        6
+#define BM_RTC_CTRL_SUPPRESS_COPY2ANALOG        0x40
+#define BF_RTC_CTRL_SUPPRESS_COPY2ANALOG(v)     (((v) & 0x1) << 6)
+#define BFM_RTC_CTRL_SUPPRESS_COPY2ANALOG(v)    BM_RTC_CTRL_SUPPRESS_COPY2ANALOG
+#define BF_RTC_CTRL_SUPPRESS_COPY2ANALOG_V(e)   BF_RTC_CTRL_SUPPRESS_COPY2ANALOG(BV_RTC_CTRL_SUPPRESS_COPY2ANALOG__##e)
+#define BFM_RTC_CTRL_SUPPRESS_COPY2ANALOG_V(v)  BM_RTC_CTRL_SUPPRESS_COPY2ANALOG
+#define BP_RTC_CTRL_FORCE_UPDATE                5
+#define BM_RTC_CTRL_FORCE_UPDATE                0x20
+#define BF_RTC_CTRL_FORCE_UPDATE(v)             (((v) & 0x1) << 5)
+#define BFM_RTC_CTRL_FORCE_UPDATE(v)            BM_RTC_CTRL_FORCE_UPDATE
+#define BF_RTC_CTRL_FORCE_UPDATE_V(e)           BF_RTC_CTRL_FORCE_UPDATE(BV_RTC_CTRL_FORCE_UPDATE__##e)
+#define BFM_RTC_CTRL_FORCE_UPDATE_V(v)          BM_RTC_CTRL_FORCE_UPDATE
+#define BP_RTC_CTRL_WATCHDOGEN                  4
+#define BM_RTC_CTRL_WATCHDOGEN                  0x10
+#define BF_RTC_CTRL_WATCHDOGEN(v)               (((v) & 0x1) << 4)
+#define BFM_RTC_CTRL_WATCHDOGEN(v)              BM_RTC_CTRL_WATCHDOGEN
+#define BF_RTC_CTRL_WATCHDOGEN_V(e)             BF_RTC_CTRL_WATCHDOGEN(BV_RTC_CTRL_WATCHDOGEN__##e)
+#define BFM_RTC_CTRL_WATCHDOGEN_V(v)            BM_RTC_CTRL_WATCHDOGEN
+#define BP_RTC_CTRL_ONEMSEC_IRQ                 3
+#define BM_RTC_CTRL_ONEMSEC_IRQ                 0x8
+#define BF_RTC_CTRL_ONEMSEC_IRQ(v)              (((v) & 0x1) << 3)
+#define BFM_RTC_CTRL_ONEMSEC_IRQ(v)             BM_RTC_CTRL_ONEMSEC_IRQ
+#define BF_RTC_CTRL_ONEMSEC_IRQ_V(e)            BF_RTC_CTRL_ONEMSEC_IRQ(BV_RTC_CTRL_ONEMSEC_IRQ__##e)
+#define BFM_RTC_CTRL_ONEMSEC_IRQ_V(v)           BM_RTC_CTRL_ONEMSEC_IRQ
+#define BP_RTC_CTRL_ALARM_IRQ                   2
+#define BM_RTC_CTRL_ALARM_IRQ                   0x4
+#define BF_RTC_CTRL_ALARM_IRQ(v)                (((v) & 0x1) << 2)
+#define BFM_RTC_CTRL_ALARM_IRQ(v)               BM_RTC_CTRL_ALARM_IRQ
+#define BF_RTC_CTRL_ALARM_IRQ_V(e)              BF_RTC_CTRL_ALARM_IRQ(BV_RTC_CTRL_ALARM_IRQ__##e)
+#define BFM_RTC_CTRL_ALARM_IRQ_V(v)             BM_RTC_CTRL_ALARM_IRQ
+#define BP_RTC_CTRL_ONEMSEC_IRQ_EN              1
+#define BM_RTC_CTRL_ONEMSEC_IRQ_EN              0x2
+#define BF_RTC_CTRL_ONEMSEC_IRQ_EN(v)           (((v) & 0x1) << 1)
+#define BFM_RTC_CTRL_ONEMSEC_IRQ_EN(v)          BM_RTC_CTRL_ONEMSEC_IRQ_EN
+#define BF_RTC_CTRL_ONEMSEC_IRQ_EN_V(e)         BF_RTC_CTRL_ONEMSEC_IRQ_EN(BV_RTC_CTRL_ONEMSEC_IRQ_EN__##e)
+#define BFM_RTC_CTRL_ONEMSEC_IRQ_EN_V(v)        BM_RTC_CTRL_ONEMSEC_IRQ_EN
+#define BP_RTC_CTRL_ALARM_IRQ_EN                0
+#define BM_RTC_CTRL_ALARM_IRQ_EN                0x1
+#define BF_RTC_CTRL_ALARM_IRQ_EN(v)             (((v) & 0x1) << 0)
+#define BFM_RTC_CTRL_ALARM_IRQ_EN(v)            BM_RTC_CTRL_ALARM_IRQ_EN
+#define BF_RTC_CTRL_ALARM_IRQ_EN_V(e)           BF_RTC_CTRL_ALARM_IRQ_EN(BV_RTC_CTRL_ALARM_IRQ_EN__##e)
+#define BFM_RTC_CTRL_ALARM_IRQ_EN_V(v)          BM_RTC_CTRL_ALARM_IRQ_EN
+
+#define HW_RTC_STAT                         HW(RTC_STAT)
+#define HWA_RTC_STAT                        (0x8005c000 + 0x10)
+#define HWT_RTC_STAT                        HWIO_32_RW
+#define HWN_RTC_STAT                        RTC_STAT
+#define HWI_RTC_STAT                        
+#define BP_RTC_STAT_RTC_PRESENT             31
+#define BM_RTC_STAT_RTC_PRESENT             0x80000000
+#define BF_RTC_STAT_RTC_PRESENT(v)          (((v) & 0x1) << 31)
+#define BFM_RTC_STAT_RTC_PRESENT(v)         BM_RTC_STAT_RTC_PRESENT
+#define BF_RTC_STAT_RTC_PRESENT_V(e)        BF_RTC_STAT_RTC_PRESENT(BV_RTC_STAT_RTC_PRESENT__##e)
+#define BFM_RTC_STAT_RTC_PRESENT_V(v)       BM_RTC_STAT_RTC_PRESENT
+#define BP_RTC_STAT_ALARM_PRESENT           30
+#define BM_RTC_STAT_ALARM_PRESENT           0x40000000
+#define BF_RTC_STAT_ALARM_PRESENT(v)        (((v) & 0x1) << 30)
+#define BFM_RTC_STAT_ALARM_PRESENT(v)       BM_RTC_STAT_ALARM_PRESENT
+#define BF_RTC_STAT_ALARM_PRESENT_V(e)      BF_RTC_STAT_ALARM_PRESENT(BV_RTC_STAT_ALARM_PRESENT__##e)
+#define BFM_RTC_STAT_ALARM_PRESENT_V(v)     BM_RTC_STAT_ALARM_PRESENT
+#define BP_RTC_STAT_WATCHDOG_PRESENT        29
+#define BM_RTC_STAT_WATCHDOG_PRESENT        0x20000000
+#define BF_RTC_STAT_WATCHDOG_PRESENT(v)     (((v) & 0x1) << 29)
+#define BFM_RTC_STAT_WATCHDOG_PRESENT(v)    BM_RTC_STAT_WATCHDOG_PRESENT
+#define BF_RTC_STAT_WATCHDOG_PRESENT_V(e)   BF_RTC_STAT_WATCHDOG_PRESENT(BV_RTC_STAT_WATCHDOG_PRESENT__##e)
+#define BFM_RTC_STAT_WATCHDOG_PRESENT_V(v)  BM_RTC_STAT_WATCHDOG_PRESENT
+#define BP_RTC_STAT_XTAL32000_PRESENT       28
+#define BM_RTC_STAT_XTAL32000_PRESENT       0x10000000
+#define BF_RTC_STAT_XTAL32000_PRESENT(v)    (((v) & 0x1) << 28)
+#define BFM_RTC_STAT_XTAL32000_PRESENT(v)   BM_RTC_STAT_XTAL32000_PRESENT
+#define BF_RTC_STAT_XTAL32000_PRESENT_V(e)  BF_RTC_STAT_XTAL32000_PRESENT(BV_RTC_STAT_XTAL32000_PRESENT__##e)
+#define BFM_RTC_STAT_XTAL32000_PRESENT_V(v) BM_RTC_STAT_XTAL32000_PRESENT
+#define BP_RTC_STAT_XTAL32768_PRESENT       27
+#define BM_RTC_STAT_XTAL32768_PRESENT       0x8000000
+#define BF_RTC_STAT_XTAL32768_PRESENT(v)    (((v) & 0x1) << 27)
+#define BFM_RTC_STAT_XTAL32768_PRESENT(v)   BM_RTC_STAT_XTAL32768_PRESENT
+#define BF_RTC_STAT_XTAL32768_PRESENT_V(e)  BF_RTC_STAT_XTAL32768_PRESENT(BV_RTC_STAT_XTAL32768_PRESENT__##e)
+#define BFM_RTC_STAT_XTAL32768_PRESENT_V(v) BM_RTC_STAT_XTAL32768_PRESENT
+#define BP_RTC_STAT_STALE_REGS              16
+#define BM_RTC_STAT_STALE_REGS              0xff0000
+#define BF_RTC_STAT_STALE_REGS(v)           (((v) & 0xff) << 16)
+#define BFM_RTC_STAT_STALE_REGS(v)          BM_RTC_STAT_STALE_REGS
+#define BF_RTC_STAT_STALE_REGS_V(e)         BF_RTC_STAT_STALE_REGS(BV_RTC_STAT_STALE_REGS__##e)
+#define BFM_RTC_STAT_STALE_REGS_V(v)        BM_RTC_STAT_STALE_REGS
+#define BP_RTC_STAT_NEW_REGS                8
+#define BM_RTC_STAT_NEW_REGS                0xff00
+#define BF_RTC_STAT_NEW_REGS(v)             (((v) & 0xff) << 8)
+#define BFM_RTC_STAT_NEW_REGS(v)            BM_RTC_STAT_NEW_REGS
+#define BF_RTC_STAT_NEW_REGS_V(e)           BF_RTC_STAT_NEW_REGS(BV_RTC_STAT_NEW_REGS__##e)
+#define BFM_RTC_STAT_NEW_REGS_V(v)          BM_RTC_STAT_NEW_REGS
+
+#define HW_RTC_MILLISECONDS             HW(RTC_MILLISECONDS)
+#define HWA_RTC_MILLISECONDS            (0x8005c000 + 0x20)
+#define HWT_RTC_MILLISECONDS            HWIO_32_RW
+#define HWN_RTC_MILLISECONDS            RTC_MILLISECONDS
+#define HWI_RTC_MILLISECONDS            
+#define HW_RTC_MILLISECONDS_SET         HW(RTC_MILLISECONDS_SET)
+#define HWA_RTC_MILLISECONDS_SET        (HWA_RTC_MILLISECONDS + 0x4)
+#define HWT_RTC_MILLISECONDS_SET        HWIO_32_WO
+#define HWN_RTC_MILLISECONDS_SET        RTC_MILLISECONDS
+#define HWI_RTC_MILLISECONDS_SET        
+#define HW_RTC_MILLISECONDS_CLR         HW(RTC_MILLISECONDS_CLR)
+#define HWA_RTC_MILLISECONDS_CLR        (HWA_RTC_MILLISECONDS + 0x8)
+#define HWT_RTC_MILLISECONDS_CLR        HWIO_32_WO
+#define HWN_RTC_MILLISECONDS_CLR        RTC_MILLISECONDS
+#define HWI_RTC_MILLISECONDS_CLR        
+#define HW_RTC_MILLISECONDS_TOG         HW(RTC_MILLISECONDS_TOG)
+#define HWA_RTC_MILLISECONDS_TOG        (HWA_RTC_MILLISECONDS + 0xc)
+#define HWT_RTC_MILLISECONDS_TOG        HWIO_32_WO
+#define HWN_RTC_MILLISECONDS_TOG        RTC_MILLISECONDS
+#define HWI_RTC_MILLISECONDS_TOG        
+#define BP_RTC_MILLISECONDS_COUNT       0
+#define BM_RTC_MILLISECONDS_COUNT       0xffffffff
+#define BF_RTC_MILLISECONDS_COUNT(v)    (((v) & 0xffffffff) << 0)
+#define BFM_RTC_MILLISECONDS_COUNT(v)   BM_RTC_MILLISECONDS_COUNT
+#define BF_RTC_MILLISECONDS_COUNT_V(e)  BF_RTC_MILLISECONDS_COUNT(BV_RTC_MILLISECONDS_COUNT__##e)
+#define BFM_RTC_MILLISECONDS_COUNT_V(v) BM_RTC_MILLISECONDS_COUNT
+
+#define HW_RTC_SECONDS              HW(RTC_SECONDS)
+#define HWA_RTC_SECONDS             (0x8005c000 + 0x30)
+#define HWT_RTC_SECONDS             HWIO_32_RW
+#define HWN_RTC_SECONDS             RTC_SECONDS
+#define HWI_RTC_SECONDS             
+#define HW_RTC_SECONDS_SET          HW(RTC_SECONDS_SET)
+#define HWA_RTC_SECONDS_SET         (HWA_RTC_SECONDS + 0x4)
+#define HWT_RTC_SECONDS_SET         HWIO_32_WO
+#define HWN_RTC_SECONDS_SET         RTC_SECONDS
+#define HWI_RTC_SECONDS_SET         
+#define HW_RTC_SECONDS_CLR          HW(RTC_SECONDS_CLR)
+#define HWA_RTC_SECONDS_CLR         (HWA_RTC_SECONDS + 0x8)
+#define HWT_RTC_SECONDS_CLR         HWIO_32_WO
+#define HWN_RTC_SECONDS_CLR         RTC_SECONDS
+#define HWI_RTC_SECONDS_CLR         
+#define HW_RTC_SECONDS_TOG          HW(RTC_SECONDS_TOG)
+#define HWA_RTC_SECONDS_TOG         (HWA_RTC_SECONDS + 0xc)
+#define HWT_RTC_SECONDS_TOG         HWIO_32_WO
+#define HWN_RTC_SECONDS_TOG         RTC_SECONDS
+#define HWI_RTC_SECONDS_TOG         
+#define BP_RTC_SECONDS_COUNT        0
+#define BM_RTC_SECONDS_COUNT        0xffffffff
+#define BF_RTC_SECONDS_COUNT(v)     (((v) & 0xffffffff) << 0)
+#define BFM_RTC_SECONDS_COUNT(v)    BM_RTC_SECONDS_COUNT
+#define BF_RTC_SECONDS_COUNT_V(e)   BF_RTC_SECONDS_COUNT(BV_RTC_SECONDS_COUNT__##e)
+#define BFM_RTC_SECONDS_COUNT_V(v)  BM_RTC_SECONDS_COUNT
+
+#define HW_RTC_ALARM                HW(RTC_ALARM)
+#define HWA_RTC_ALARM               (0x8005c000 + 0x40)
+#define HWT_RTC_ALARM               HWIO_32_RW
+#define HWN_RTC_ALARM               RTC_ALARM
+#define HWI_RTC_ALARM               
+#define HW_RTC_ALARM_SET            HW(RTC_ALARM_SET)
+#define HWA_RTC_ALARM_SET           (HWA_RTC_ALARM + 0x4)
+#define HWT_RTC_ALARM_SET           HWIO_32_WO
+#define HWN_RTC_ALARM_SET           RTC_ALARM
+#define HWI_RTC_ALARM_SET           
+#define HW_RTC_ALARM_CLR            HW(RTC_ALARM_CLR)
+#define HWA_RTC_ALARM_CLR           (HWA_RTC_ALARM + 0x8)
+#define HWT_RTC_ALARM_CLR           HWIO_32_WO
+#define HWN_RTC_ALARM_CLR           RTC_ALARM
+#define HWI_RTC_ALARM_CLR           
+#define HW_RTC_ALARM_TOG            HW(RTC_ALARM_TOG)
+#define HWA_RTC_ALARM_TOG           (HWA_RTC_ALARM + 0xc)
+#define HWT_RTC_ALARM_TOG           HWIO_32_WO
+#define HWN_RTC_ALARM_TOG           RTC_ALARM
+#define HWI_RTC_ALARM_TOG           
+#define BP_RTC_ALARM_VALUE          0
+#define BM_RTC_ALARM_VALUE          0xffffffff
+#define BF_RTC_ALARM_VALUE(v)       (((v) & 0xffffffff) << 0)
+#define BFM_RTC_ALARM_VALUE(v)      BM_RTC_ALARM_VALUE
+#define BF_RTC_ALARM_VALUE_V(e)     BF_RTC_ALARM_VALUE(BV_RTC_ALARM_VALUE__##e)
+#define BFM_RTC_ALARM_VALUE_V(v)    BM_RTC_ALARM_VALUE
+
+#define HW_RTC_WATCHDOG             HW(RTC_WATCHDOG)
+#define HWA_RTC_WATCHDOG            (0x8005c000 + 0x50)
+#define HWT_RTC_WATCHDOG            HWIO_32_RW
+#define HWN_RTC_WATCHDOG            RTC_WATCHDOG
+#define HWI_RTC_WATCHDOG            
+#define HW_RTC_WATCHDOG_SET         HW(RTC_WATCHDOG_SET)
+#define HWA_RTC_WATCHDOG_SET        (HWA_RTC_WATCHDOG + 0x4)
+#define HWT_RTC_WATCHDOG_SET        HWIO_32_WO
+#define HWN_RTC_WATCHDOG_SET        RTC_WATCHDOG
+#define HWI_RTC_WATCHDOG_SET        
+#define HW_RTC_WATCHDOG_CLR         HW(RTC_WATCHDOG_CLR)
+#define HWA_RTC_WATCHDOG_CLR        (HWA_RTC_WATCHDOG + 0x8)
+#define HWT_RTC_WATCHDOG_CLR        HWIO_32_WO
+#define HWN_RTC_WATCHDOG_CLR        RTC_WATCHDOG
+#define HWI_RTC_WATCHDOG_CLR        
+#define HW_RTC_WATCHDOG_TOG         HW(RTC_WATCHDOG_TOG)
+#define HWA_RTC_WATCHDOG_TOG        (HWA_RTC_WATCHDOG + 0xc)
+#define HWT_RTC_WATCHDOG_TOG        HWIO_32_WO
+#define HWN_RTC_WATCHDOG_TOG        RTC_WATCHDOG
+#define HWI_RTC_WATCHDOG_TOG        
+#define BP_RTC_WATCHDOG_COUNT       0
+#define BM_RTC_WATCHDOG_COUNT       0xffffffff
+#define BF_RTC_WATCHDOG_COUNT(v)    (((v) & 0xffffffff) << 0)
+#define BFM_RTC_WATCHDOG_COUNT(v)   BM_RTC_WATCHDOG_COUNT
+#define BF_RTC_WATCHDOG_COUNT_V(e)  BF_RTC_WATCHDOG_COUNT(BV_RTC_WATCHDOG_COUNT__##e)
+#define BFM_RTC_WATCHDOG_COUNT_V(v) BM_RTC_WATCHDOG_COUNT
+
+#define HW_RTC_PERSISTENT0                          HW(RTC_PERSISTENT0)
+#define HWA_RTC_PERSISTENT0                         (0x8005c000 + 0x60)
+#define HWT_RTC_PERSISTENT0                         HWIO_32_RW
+#define HWN_RTC_PERSISTENT0                         RTC_PERSISTENT0
+#define HWI_RTC_PERSISTENT0                         
+#define HW_RTC_PERSISTENT0_SET                      HW(RTC_PERSISTENT0_SET)
+#define HWA_RTC_PERSISTENT0_SET                     (HWA_RTC_PERSISTENT0 + 0x4)
+#define HWT_RTC_PERSISTENT0_SET                     HWIO_32_WO
+#define HWN_RTC_PERSISTENT0_SET                     RTC_PERSISTENT0
+#define HWI_RTC_PERSISTENT0_SET                     
+#define HW_RTC_PERSISTENT0_CLR                      HW(RTC_PERSISTENT0_CLR)
+#define HWA_RTC_PERSISTENT0_CLR                     (HWA_RTC_PERSISTENT0 + 0x8)
+#define HWT_RTC_PERSISTENT0_CLR                     HWIO_32_WO
+#define HWN_RTC_PERSISTENT0_CLR                     RTC_PERSISTENT0
+#define HWI_RTC_PERSISTENT0_CLR                     
+#define HW_RTC_PERSISTENT0_TOG                      HW(RTC_PERSISTENT0_TOG)
+#define HWA_RTC_PERSISTENT0_TOG                     (HWA_RTC_PERSISTENT0 + 0xc)
+#define HWT_RTC_PERSISTENT0_TOG                     HWIO_32_WO
+#define HWN_RTC_PERSISTENT0_TOG                     RTC_PERSISTENT0
+#define HWI_RTC_PERSISTENT0_TOG                     
+#define BP_RTC_PERSISTENT0_SPARE_ANALOG             18
+#define BM_RTC_PERSISTENT0_SPARE_ANALOG             0xfffc0000
+#define BF_RTC_PERSISTENT0_SPARE_ANALOG(v)          (((v) & 0x3fff) << 18)
+#define BFM_RTC_PERSISTENT0_SPARE_ANALOG(v)         BM_RTC_PERSISTENT0_SPARE_ANALOG
+#define BF_RTC_PERSISTENT0_SPARE_ANALOG_V(e)        BF_RTC_PERSISTENT0_SPARE_ANALOG(BV_RTC_PERSISTENT0_SPARE_ANALOG__##e)
+#define BFM_RTC_PERSISTENT0_SPARE_ANALOG_V(v)       BM_RTC_PERSISTENT0_SPARE_ANALOG
+#define BP_RTC_PERSISTENT0_AUTO_RESTART             17
+#define BM_RTC_PERSISTENT0_AUTO_RESTART             0x20000
+#define BF_RTC_PERSISTENT0_AUTO_RESTART(v)          (((v) & 0x1) << 17)
+#define BFM_RTC_PERSISTENT0_AUTO_RESTART(v)         BM_RTC_PERSISTENT0_AUTO_RESTART
+#define BF_RTC_PERSISTENT0_AUTO_RESTART_V(e)        BF_RTC_PERSISTENT0_AUTO_RESTART(BV_RTC_PERSISTENT0_AUTO_RESTART__##e)
+#define BFM_RTC_PERSISTENT0_AUTO_RESTART_V(v)       BM_RTC_PERSISTENT0_AUTO_RESTART
+#define BP_RTC_PERSISTENT0_DISABLE_PSWITCH          16
+#define BM_RTC_PERSISTENT0_DISABLE_PSWITCH          0x10000
+#define BF_RTC_PERSISTENT0_DISABLE_PSWITCH(v)       (((v) & 0x1) << 16)
+#define BFM_RTC_PERSISTENT0_DISABLE_PSWITCH(v)      BM_RTC_PERSISTENT0_DISABLE_PSWITCH
+#define BF_RTC_PERSISTENT0_DISABLE_PSWITCH_V(e)     BF_RTC_PERSISTENT0_DISABLE_PSWITCH(BV_RTC_PERSISTENT0_DISABLE_PSWITCH__##e)
+#define BFM_RTC_PERSISTENT0_DISABLE_PSWITCH_V(v)    BM_RTC_PERSISTENT0_DISABLE_PSWITCH
+#define BP_RTC_PERSISTENT0_LOWERBIAS                14
+#define BM_RTC_PERSISTENT0_LOWERBIAS                0xc000
+#define BF_RTC_PERSISTENT0_LOWERBIAS(v)             (((v) & 0x3) << 14)
+#define BFM_RTC_PERSISTENT0_LOWERBIAS(v)            BM_RTC_PERSISTENT0_LOWERBIAS
+#define BF_RTC_PERSISTENT0_LOWERBIAS_V(e)           BF_RTC_PERSISTENT0_LOWERBIAS(BV_RTC_PERSISTENT0_LOWERBIAS__##e)
+#define BFM_RTC_PERSISTENT0_LOWERBIAS_V(v)          BM_RTC_PERSISTENT0_LOWERBIAS
+#define BP_RTC_PERSISTENT0_DISABLE_XTALOK           13
+#define BM_RTC_PERSISTENT0_DISABLE_XTALOK           0x2000
+#define BF_RTC_PERSISTENT0_DISABLE_XTALOK(v)        (((v) & 0x1) << 13)
+#define BFM_RTC_PERSISTENT0_DISABLE_XTALOK(v)       BM_RTC_PERSISTENT0_DISABLE_XTALOK
+#define BF_RTC_PERSISTENT0_DISABLE_XTALOK_V(e)      BF_RTC_PERSISTENT0_DISABLE_XTALOK(BV_RTC_PERSISTENT0_DISABLE_XTALOK__##e)
+#define BFM_RTC_PERSISTENT0_DISABLE_XTALOK_V(v)     BM_RTC_PERSISTENT0_DISABLE_XTALOK
+#define BP_RTC_PERSISTENT0_MSEC_RES                 8
+#define BM_RTC_PERSISTENT0_MSEC_RES                 0x1f00
+#define BF_RTC_PERSISTENT0_MSEC_RES(v)              (((v) & 0x1f) << 8)
+#define BFM_RTC_PERSISTENT0_MSEC_RES(v)             BM_RTC_PERSISTENT0_MSEC_RES
+#define BF_RTC_PERSISTENT0_MSEC_RES_V(e)            BF_RTC_PERSISTENT0_MSEC_RES(BV_RTC_PERSISTENT0_MSEC_RES__##e)
+#define BFM_RTC_PERSISTENT0_MSEC_RES_V(v)           BM_RTC_PERSISTENT0_MSEC_RES
+#define BP_RTC_PERSISTENT0_ALARM_WAKE               7
+#define BM_RTC_PERSISTENT0_ALARM_WAKE               0x80
+#define BF_RTC_PERSISTENT0_ALARM_WAKE(v)            (((v) & 0x1) << 7)
+#define BFM_RTC_PERSISTENT0_ALARM_WAKE(v)           BM_RTC_PERSISTENT0_ALARM_WAKE
+#define BF_RTC_PERSISTENT0_ALARM_WAKE_V(e)          BF_RTC_PERSISTENT0_ALARM_WAKE(BV_RTC_PERSISTENT0_ALARM_WAKE__##e)
+#define BFM_RTC_PERSISTENT0_ALARM_WAKE_V(v)         BM_RTC_PERSISTENT0_ALARM_WAKE
+#define BP_RTC_PERSISTENT0_XTAL32_FREQ              6
+#define BM_RTC_PERSISTENT0_XTAL32_FREQ              0x40
+#define BF_RTC_PERSISTENT0_XTAL32_FREQ(v)           (((v) & 0x1) << 6)
+#define BFM_RTC_PERSISTENT0_XTAL32_FREQ(v)          BM_RTC_PERSISTENT0_XTAL32_FREQ
+#define BF_RTC_PERSISTENT0_XTAL32_FREQ_V(e)         BF_RTC_PERSISTENT0_XTAL32_FREQ(BV_RTC_PERSISTENT0_XTAL32_FREQ__##e)
+#define BFM_RTC_PERSISTENT0_XTAL32_FREQ_V(v)        BM_RTC_PERSISTENT0_XTAL32_FREQ
+#define BP_RTC_PERSISTENT0_XTAL32KHZ_PWRUP          5
+#define BM_RTC_PERSISTENT0_XTAL32KHZ_PWRUP          0x20
+#define BF_RTC_PERSISTENT0_XTAL32KHZ_PWRUP(v)       (((v) & 0x1) << 5)
+#define BFM_RTC_PERSISTENT0_XTAL32KHZ_PWRUP(v)      BM_RTC_PERSISTENT0_XTAL32KHZ_PWRUP
+#define BF_RTC_PERSISTENT0_XTAL32KHZ_PWRUP_V(e)     BF_RTC_PERSISTENT0_XTAL32KHZ_PWRUP(BV_RTC_PERSISTENT0_XTAL32KHZ_PWRUP__##e)
+#define BFM_RTC_PERSISTENT0_XTAL32KHZ_PWRUP_V(v)    BM_RTC_PERSISTENT0_XTAL32KHZ_PWRUP
+#define BP_RTC_PERSISTENT0_XTAL24MHZ_PWRUP          4
+#define BM_RTC_PERSISTENT0_XTAL24MHZ_PWRUP          0x10
+#define BF_RTC_PERSISTENT0_XTAL24MHZ_PWRUP(v)       (((v) & 0x1) << 4)
+#define BFM_RTC_PERSISTENT0_XTAL24MHZ_PWRUP(v)      BM_RTC_PERSISTENT0_XTAL24MHZ_PWRUP
+#define BF_RTC_PERSISTENT0_XTAL24MHZ_PWRUP_V(e)     BF_RTC_PERSISTENT0_XTAL24MHZ_PWRUP(BV_RTC_PERSISTENT0_XTAL24MHZ_PWRUP__##e)
+#define BFM_RTC_PERSISTENT0_XTAL24MHZ_PWRUP_V(v)    BM_RTC_PERSISTENT0_XTAL24MHZ_PWRUP
+#define BP_RTC_PERSISTENT0_LCK_SECS                 3
+#define BM_RTC_PERSISTENT0_LCK_SECS                 0x8
+#define BF_RTC_PERSISTENT0_LCK_SECS(v)              (((v) & 0x1) << 3)
+#define BFM_RTC_PERSISTENT0_LCK_SECS(v)             BM_RTC_PERSISTENT0_LCK_SECS
+#define BF_RTC_PERSISTENT0_LCK_SECS_V(e)            BF_RTC_PERSISTENT0_LCK_SECS(BV_RTC_PERSISTENT0_LCK_SECS__##e)
+#define BFM_RTC_PERSISTENT0_LCK_SECS_V(v)           BM_RTC_PERSISTENT0_LCK_SECS
+#define BP_RTC_PERSISTENT0_ALARM_EN                 2
+#define BM_RTC_PERSISTENT0_ALARM_EN                 0x4
+#define BF_RTC_PERSISTENT0_ALARM_EN(v)              (((v) & 0x1) << 2)
+#define BFM_RTC_PERSISTENT0_ALARM_EN(v)             BM_RTC_PERSISTENT0_ALARM_EN
+#define BF_RTC_PERSISTENT0_ALARM_EN_V(e)            BF_RTC_PERSISTENT0_ALARM_EN(BV_RTC_PERSISTENT0_ALARM_EN__##e)
+#define BFM_RTC_PERSISTENT0_ALARM_EN_V(v)           BM_RTC_PERSISTENT0_ALARM_EN
+#define BP_RTC_PERSISTENT0_ALARM_WAKE_EN            1
+#define BM_RTC_PERSISTENT0_ALARM_WAKE_EN            0x2
+#define BF_RTC_PERSISTENT0_ALARM_WAKE_EN(v)         (((v) & 0x1) << 1)
+#define BFM_RTC_PERSISTENT0_ALARM_WAKE_EN(v)        BM_RTC_PERSISTENT0_ALARM_WAKE_EN
+#define BF_RTC_PERSISTENT0_ALARM_WAKE_EN_V(e)       BF_RTC_PERSISTENT0_ALARM_WAKE_EN(BV_RTC_PERSISTENT0_ALARM_WAKE_EN__##e)
+#define BFM_RTC_PERSISTENT0_ALARM_WAKE_EN_V(v)      BM_RTC_PERSISTENT0_ALARM_WAKE_EN
+#define BP_RTC_PERSISTENT0_CLOCKSOURCE              0
+#define BM_RTC_PERSISTENT0_CLOCKSOURCE              0x1
+#define BF_RTC_PERSISTENT0_CLOCKSOURCE(v)           (((v) & 0x1) << 0)
+#define BFM_RTC_PERSISTENT0_CLOCKSOURCE(v)          BM_RTC_PERSISTENT0_CLOCKSOURCE
+#define BF_RTC_PERSISTENT0_CLOCKSOURCE_V(e)         BF_RTC_PERSISTENT0_CLOCKSOURCE(BV_RTC_PERSISTENT0_CLOCKSOURCE__##e)
+#define BFM_RTC_PERSISTENT0_CLOCKSOURCE_V(v)        BM_RTC_PERSISTENT0_CLOCKSOURCE
+
+#define HW_RTC_PERSISTENT1                                  HW(RTC_PERSISTENT1)
+#define HWA_RTC_PERSISTENT1                                 (0x8005c000 + 0x70)
+#define HWT_RTC_PERSISTENT1                                 HWIO_32_RW
+#define HWN_RTC_PERSISTENT1                                 RTC_PERSISTENT1
+#define HWI_RTC_PERSISTENT1                                 
+#define HW_RTC_PERSISTENT1_SET                              HW(RTC_PERSISTENT1_SET)
+#define HWA_RTC_PERSISTENT1_SET                             (HWA_RTC_PERSISTENT1 + 0x4)
+#define HWT_RTC_PERSISTENT1_SET                             HWIO_32_WO
+#define HWN_RTC_PERSISTENT1_SET                             RTC_PERSISTENT1
+#define HWI_RTC_PERSISTENT1_SET                             
+#define HW_RTC_PERSISTENT1_CLR                              HW(RTC_PERSISTENT1_CLR)
+#define HWA_RTC_PERSISTENT1_CLR                             (HWA_RTC_PERSISTENT1 + 0x8)
+#define HWT_RTC_PERSISTENT1_CLR                             HWIO_32_WO
+#define HWN_RTC_PERSISTENT1_CLR                             RTC_PERSISTENT1
+#define HWI_RTC_PERSISTENT1_CLR                             
+#define HW_RTC_PERSISTENT1_TOG                              HW(RTC_PERSISTENT1_TOG)
+#define HWA_RTC_PERSISTENT1_TOG                             (HWA_RTC_PERSISTENT1 + 0xc)
+#define HWT_RTC_PERSISTENT1_TOG                             HWIO_32_WO
+#define HWN_RTC_PERSISTENT1_TOG                             RTC_PERSISTENT1
+#define HWI_RTC_PERSISTENT1_TOG                             
+#define BP_RTC_PERSISTENT1_GENERAL                          0
+#define BM_RTC_PERSISTENT1_GENERAL                          0xffffffff
+#define BV_RTC_PERSISTENT1_GENERAL__SPARE3                  0x4000
+#define BV_RTC_PERSISTENT1_GENERAL__SDRAM_BOOT              0x2000
+#define BV_RTC_PERSISTENT1_GENERAL__ENUMERATE_500MA_TWICE   0x1000
+#define BV_RTC_PERSISTENT1_GENERAL__USB_BOOT_PLAYER_MODE    0x800
+#define BV_RTC_PERSISTENT1_GENERAL__SKIP_CHECKDISK          0x400
+#define BV_RTC_PERSISTENT1_GENERAL__USB_LOW_POWER_MODE      0x200
+#define BV_RTC_PERSISTENT1_GENERAL__OTG_HNP_BIT             0x100
+#define BV_RTC_PERSISTENT1_GENERAL__OTG_ATL_ROLE_BIT        0x80
+#define BV_RTC_PERSISTENT1_GENERAL__SDRAM_CS_HI             0x40
+#define BV_RTC_PERSISTENT1_GENERAL__SDRAM_CS_LO             0x20
+#define BV_RTC_PERSISTENT1_GENERAL__SDRAM_NDX_3             0x10
+#define BV_RTC_PERSISTENT1_GENERAL__SDRAM_NDX_2             0x8
+#define BV_RTC_PERSISTENT1_GENERAL__SDRAM_NDX_1             0x4
+#define BV_RTC_PERSISTENT1_GENERAL__SDRAM_NDX_0             0x2
+#define BV_RTC_PERSISTENT1_GENERAL__ETM_ENABLE              0x1
+#define BF_RTC_PERSISTENT1_GENERAL(v)                       (((v) & 0xffffffff) << 0)
+#define BFM_RTC_PERSISTENT1_GENERAL(v)                      BM_RTC_PERSISTENT1_GENERAL
+#define BF_RTC_PERSISTENT1_GENERAL_V(e)                     BF_RTC_PERSISTENT1_GENERAL(BV_RTC_PERSISTENT1_GENERAL__##e)
+#define BFM_RTC_PERSISTENT1_GENERAL_V(v)                    BM_RTC_PERSISTENT1_GENERAL
+
+#define HW_RTC_PERSISTENT2                  HW(RTC_PERSISTENT2)
+#define HWA_RTC_PERSISTENT2                 (0x8005c000 + 0x80)
+#define HWT_RTC_PERSISTENT2                 HWIO_32_RW
+#define HWN_RTC_PERSISTENT2                 RTC_PERSISTENT2
+#define HWI_RTC_PERSISTENT2                 
+#define HW_RTC_PERSISTENT2_SET              HW(RTC_PERSISTENT2_SET)
+#define HWA_RTC_PERSISTENT2_SET             (HWA_RTC_PERSISTENT2 + 0x4)
+#define HWT_RTC_PERSISTENT2_SET             HWIO_32_WO
+#define HWN_RTC_PERSISTENT2_SET             RTC_PERSISTENT2
+#define HWI_RTC_PERSISTENT2_SET             
+#define HW_RTC_PERSISTENT2_CLR              HW(RTC_PERSISTENT2_CLR)
+#define HWA_RTC_PERSISTENT2_CLR             (HWA_RTC_PERSISTENT2 + 0x8)
+#define HWT_RTC_PERSISTENT2_CLR             HWIO_32_WO
+#define HWN_RTC_PERSISTENT2_CLR             RTC_PERSISTENT2
+#define HWI_RTC_PERSISTENT2_CLR             
+#define HW_RTC_PERSISTENT2_TOG              HW(RTC_PERSISTENT2_TOG)
+#define HWA_RTC_PERSISTENT2_TOG             (HWA_RTC_PERSISTENT2 + 0xc)
+#define HWT_RTC_PERSISTENT2_TOG             HWIO_32_WO
+#define HWN_RTC_PERSISTENT2_TOG             RTC_PERSISTENT2
+#define HWI_RTC_PERSISTENT2_TOG             
+#define BP_RTC_PERSISTENT2_GENERAL          0
+#define BM_RTC_PERSISTENT2_GENERAL          0xffffffff
+#define BF_RTC_PERSISTENT2_GENERAL(v)       (((v) & 0xffffffff) << 0)
+#define BFM_RTC_PERSISTENT2_GENERAL(v)      BM_RTC_PERSISTENT2_GENERAL
+#define BF_RTC_PERSISTENT2_GENERAL_V(e)     BF_RTC_PERSISTENT2_GENERAL(BV_RTC_PERSISTENT2_GENERAL__##e)
+#define BFM_RTC_PERSISTENT2_GENERAL_V(v)    BM_RTC_PERSISTENT2_GENERAL
+
+#define HW_RTC_PERSISTENT3                  HW(RTC_PERSISTENT3)
+#define HWA_RTC_PERSISTENT3                 (0x8005c000 + 0x90)
+#define HWT_RTC_PERSISTENT3                 HWIO_32_RW
+#define HWN_RTC_PERSISTENT3                 RTC_PERSISTENT3
+#define HWI_RTC_PERSISTENT3                 
+#define HW_RTC_PERSISTENT3_SET              HW(RTC_PERSISTENT3_SET)
+#define HWA_RTC_PERSISTENT3_SET             (HWA_RTC_PERSISTENT3 + 0x4)
+#define HWT_RTC_PERSISTENT3_SET             HWIO_32_WO
+#define HWN_RTC_PERSISTENT3_SET             RTC_PERSISTENT3
+#define HWI_RTC_PERSISTENT3_SET             
+#define HW_RTC_PERSISTENT3_CLR              HW(RTC_PERSISTENT3_CLR)
+#define HWA_RTC_PERSISTENT3_CLR             (HWA_RTC_PERSISTENT3 + 0x8)
+#define HWT_RTC_PERSISTENT3_CLR             HWIO_32_WO
+#define HWN_RTC_PERSISTENT3_CLR             RTC_PERSISTENT3
+#define HWI_RTC_PERSISTENT3_CLR             
+#define HW_RTC_PERSISTENT3_TOG              HW(RTC_PERSISTENT3_TOG)
+#define HWA_RTC_PERSISTENT3_TOG             (HWA_RTC_PERSISTENT3 + 0xc)
+#define HWT_RTC_PERSISTENT3_TOG             HWIO_32_WO
+#define HWN_RTC_PERSISTENT3_TOG             RTC_PERSISTENT3
+#define HWI_RTC_PERSISTENT3_TOG             
+#define BP_RTC_PERSISTENT3_GENERAL          0
+#define BM_RTC_PERSISTENT3_GENERAL          0xffffffff
+#define BF_RTC_PERSISTENT3_GENERAL(v)       (((v) & 0xffffffff) << 0)
+#define BFM_RTC_PERSISTENT3_GENERAL(v)      BM_RTC_PERSISTENT3_GENERAL
+#define BF_RTC_PERSISTENT3_GENERAL_V(e)     BF_RTC_PERSISTENT3_GENERAL(BV_RTC_PERSISTENT3_GENERAL__##e)
+#define BFM_RTC_PERSISTENT3_GENERAL_V(v)    BM_RTC_PERSISTENT3_GENERAL
+
+#define HW_RTC_PERSISTENT4                  HW(RTC_PERSISTENT4)
+#define HWA_RTC_PERSISTENT4                 (0x8005c000 + 0xa0)
+#define HWT_RTC_PERSISTENT4                 HWIO_32_RW
+#define HWN_RTC_PERSISTENT4                 RTC_PERSISTENT4
+#define HWI_RTC_PERSISTENT4                 
+#define HW_RTC_PERSISTENT4_SET              HW(RTC_PERSISTENT4_SET)
+#define HWA_RTC_PERSISTENT4_SET             (HWA_RTC_PERSISTENT4 + 0x4)
+#define HWT_RTC_PERSISTENT4_SET             HWIO_32_WO
+#define HWN_RTC_PERSISTENT4_SET             RTC_PERSISTENT4
+#define HWI_RTC_PERSISTENT4_SET             
+#define HW_RTC_PERSISTENT4_CLR              HW(RTC_PERSISTENT4_CLR)
+#define HWA_RTC_PERSISTENT4_CLR             (HWA_RTC_PERSISTENT4 + 0x8)
+#define HWT_RTC_PERSISTENT4_CLR             HWIO_32_WO
+#define HWN_RTC_PERSISTENT4_CLR             RTC_PERSISTENT4
+#define HWI_RTC_PERSISTENT4_CLR             
+#define HW_RTC_PERSISTENT4_TOG              HW(RTC_PERSISTENT4_TOG)
+#define HWA_RTC_PERSISTENT4_TOG             (HWA_RTC_PERSISTENT4 + 0xc)
+#define HWT_RTC_PERSISTENT4_TOG             HWIO_32_WO
+#define HWN_RTC_PERSISTENT4_TOG             RTC_PERSISTENT4
+#define HWI_RTC_PERSISTENT4_TOG             
+#define BP_RTC_PERSISTENT4_GENERAL          0
+#define BM_RTC_PERSISTENT4_GENERAL          0xffffffff
+#define BF_RTC_PERSISTENT4_GENERAL(v)       (((v) & 0xffffffff) << 0)
+#define BFM_RTC_PERSISTENT4_GENERAL(v)      BM_RTC_PERSISTENT4_GENERAL
+#define BF_RTC_PERSISTENT4_GENERAL_V(e)     BF_RTC_PERSISTENT4_GENERAL(BV_RTC_PERSISTENT4_GENERAL__##e)
+#define BFM_RTC_PERSISTENT4_GENERAL_V(v)    BM_RTC_PERSISTENT4_GENERAL
+
+#define HW_RTC_PERSISTENT5                  HW(RTC_PERSISTENT5)
+#define HWA_RTC_PERSISTENT5                 (0x8005c000 + 0xb0)
+#define HWT_RTC_PERSISTENT5                 HWIO_32_RW
+#define HWN_RTC_PERSISTENT5                 RTC_PERSISTENT5
+#define HWI_RTC_PERSISTENT5                 
+#define HW_RTC_PERSISTENT5_SET              HW(RTC_PERSISTENT5_SET)
+#define HWA_RTC_PERSISTENT5_SET             (HWA_RTC_PERSISTENT5 + 0x4)
+#define HWT_RTC_PERSISTENT5_SET             HWIO_32_WO
+#define HWN_RTC_PERSISTENT5_SET             RTC_PERSISTENT5
+#define HWI_RTC_PERSISTENT5_SET             
+#define HW_RTC_PERSISTENT5_CLR              HW(RTC_PERSISTENT5_CLR)
+#define HWA_RTC_PERSISTENT5_CLR             (HWA_RTC_PERSISTENT5 + 0x8)
+#define HWT_RTC_PERSISTENT5_CLR             HWIO_32_WO
+#define HWN_RTC_PERSISTENT5_CLR             RTC_PERSISTENT5
+#define HWI_RTC_PERSISTENT5_CLR             
+#define HW_RTC_PERSISTENT5_TOG              HW(RTC_PERSISTENT5_TOG)
+#define HWA_RTC_PERSISTENT5_TOG             (HWA_RTC_PERSISTENT5 + 0xc)
+#define HWT_RTC_PERSISTENT5_TOG             HWIO_32_WO
+#define HWN_RTC_PERSISTENT5_TOG             RTC_PERSISTENT5
+#define HWI_RTC_PERSISTENT5_TOG             
+#define BP_RTC_PERSISTENT5_GENERAL          0
+#define BM_RTC_PERSISTENT5_GENERAL          0xffffffff
+#define BF_RTC_PERSISTENT5_GENERAL(v)       (((v) & 0xffffffff) << 0)
+#define BFM_RTC_PERSISTENT5_GENERAL(v)      BM_RTC_PERSISTENT5_GENERAL
+#define BF_RTC_PERSISTENT5_GENERAL_V(e)     BF_RTC_PERSISTENT5_GENERAL(BV_RTC_PERSISTENT5_GENERAL__##e)
+#define BFM_RTC_PERSISTENT5_GENERAL_V(v)    BM_RTC_PERSISTENT5_GENERAL
+
+#define HW_RTC_DEBUG                            HW(RTC_DEBUG)
+#define HWA_RTC_DEBUG                           (0x8005c000 + 0xc0)
+#define HWT_RTC_DEBUG                           HWIO_32_RW
+#define HWN_RTC_DEBUG                           RTC_DEBUG
+#define HWI_RTC_DEBUG                           
+#define HW_RTC_DEBUG_SET                        HW(RTC_DEBUG_SET)
+#define HWA_RTC_DEBUG_SET                       (HWA_RTC_DEBUG + 0x4)
+#define HWT_RTC_DEBUG_SET                       HWIO_32_WO
+#define HWN_RTC_DEBUG_SET                       RTC_DEBUG
+#define HWI_RTC_DEBUG_SET                       
+#define HW_RTC_DEBUG_CLR                        HW(RTC_DEBUG_CLR)
+#define HWA_RTC_DEBUG_CLR                       (HWA_RTC_DEBUG + 0x8)
+#define HWT_RTC_DEBUG_CLR                       HWIO_32_WO
+#define HWN_RTC_DEBUG_CLR                       RTC_DEBUG
+#define HWI_RTC_DEBUG_CLR                       
+#define HW_RTC_DEBUG_TOG                        HW(RTC_DEBUG_TOG)
+#define HWA_RTC_DEBUG_TOG                       (HWA_RTC_DEBUG + 0xc)
+#define HWT_RTC_DEBUG_TOG                       HWIO_32_WO
+#define HWN_RTC_DEBUG_TOG                       RTC_DEBUG
+#define HWI_RTC_DEBUG_TOG                       
+#define BP_RTC_DEBUG_WATCHDOG_RESET_MASK        1
+#define BM_RTC_DEBUG_WATCHDOG_RESET_MASK        0x2
+#define BF_RTC_DEBUG_WATCHDOG_RESET_MASK(v)     (((v) & 0x1) << 1)
+#define BFM_RTC_DEBUG_WATCHDOG_RESET_MASK(v)    BM_RTC_DEBUG_WATCHDOG_RESET_MASK
+#define BF_RTC_DEBUG_WATCHDOG_RESET_MASK_V(e)   BF_RTC_DEBUG_WATCHDOG_RESET_MASK(BV_RTC_DEBUG_WATCHDOG_RESET_MASK__##e)
+#define BFM_RTC_DEBUG_WATCHDOG_RESET_MASK_V(v)  BM_RTC_DEBUG_WATCHDOG_RESET_MASK
+#define BP_RTC_DEBUG_WATCHDOG_RESET             0
+#define BM_RTC_DEBUG_WATCHDOG_RESET             0x1
+#define BF_RTC_DEBUG_WATCHDOG_RESET(v)          (((v) & 0x1) << 0)
+#define BFM_RTC_DEBUG_WATCHDOG_RESET(v)         BM_RTC_DEBUG_WATCHDOG_RESET
+#define BF_RTC_DEBUG_WATCHDOG_RESET_V(e)        BF_RTC_DEBUG_WATCHDOG_RESET(BV_RTC_DEBUG_WATCHDOG_RESET__##e)
+#define BFM_RTC_DEBUG_WATCHDOG_RESET_V(v)       BM_RTC_DEBUG_WATCHDOG_RESET
+
+#define HW_RTC_VERSION              HW(RTC_VERSION)
+#define HWA_RTC_VERSION             (0x8005c000 + 0xd0)
+#define HWT_RTC_VERSION             HWIO_32_RW
+#define HWN_RTC_VERSION             RTC_VERSION
+#define HWI_RTC_VERSION             
+#define BP_RTC_VERSION_MAJOR        24
+#define BM_RTC_VERSION_MAJOR        0xff000000
+#define BF_RTC_VERSION_MAJOR(v)     (((v) & 0xff) << 24)
+#define BFM_RTC_VERSION_MAJOR(v)    BM_RTC_VERSION_MAJOR
+#define BF_RTC_VERSION_MAJOR_V(e)   BF_RTC_VERSION_MAJOR(BV_RTC_VERSION_MAJOR__##e)
+#define BFM_RTC_VERSION_MAJOR_V(v)  BM_RTC_VERSION_MAJOR
+#define BP_RTC_VERSION_MINOR        16
+#define BM_RTC_VERSION_MINOR        0xff0000
+#define BF_RTC_VERSION_MINOR(v)     (((v) & 0xff) << 16)
+#define BFM_RTC_VERSION_MINOR(v)    BM_RTC_VERSION_MINOR
+#define BF_RTC_VERSION_MINOR_V(e)   BF_RTC_VERSION_MINOR(BV_RTC_VERSION_MINOR__##e)
+#define BFM_RTC_VERSION_MINOR_V(v)  BM_RTC_VERSION_MINOR
+#define BP_RTC_VERSION_STEP         0
+#define BM_RTC_VERSION_STEP         0xffff
+#define BF_RTC_VERSION_STEP(v)      (((v) & 0xffff) << 0)
+#define BFM_RTC_VERSION_STEP(v)     BM_RTC_VERSION_STEP
+#define BF_RTC_VERSION_STEP_V(e)    BF_RTC_VERSION_STEP(BV_RTC_VERSION_STEP__##e)
+#define BFM_RTC_VERSION_STEP_V(v)   BM_RTC_VERSION_STEP
+
+#endif /* __HEADERGEN_STMP3700_RTC_H__*/
diff --git a/firmware/target/arm/imx233/regs/stmp3700/saif.h b/firmware/target/arm/imx233/regs/stmp3700/saif.h
new file mode 100644
index 0000000000..cc7a256384
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3700/saif.h
@@ -0,0 +1,270 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * stmp3700 version: 2.4.0
+ * stmp3700 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_STMP3700_SAIF_H__
+#define __HEADERGEN_STMP3700_SAIF_H__
+
+#define HW_SAIF_CTRL(_n1)                       HW(SAIF_CTRL(_n1))
+#define HWA_SAIF_CTRL(_n1)                      (((_n1) == 1 ? 0x80042000 : 0x80046000) + 0x0)
+#define HWT_SAIF_CTRL(_n1)                      HWIO_32_RW
+#define HWN_SAIF_CTRL(_n1)                      SAIF_CTRL
+#define HWI_SAIF_CTRL(_n1)                      (_n1)
+#define HW_SAIF_CTRL_SET(_n1)                   HW(SAIF_CTRL_SET(_n1))
+#define HWA_SAIF_CTRL_SET(_n1)                  (HWA_SAIF_CTRL(_n1) + 0x4)
+#define HWT_SAIF_CTRL_SET(_n1)                  HWIO_32_WO
+#define HWN_SAIF_CTRL_SET(_n1)                  SAIF_CTRL
+#define HWI_SAIF_CTRL_SET(_n1)                  (_n1)
+#define HW_SAIF_CTRL_CLR(_n1)                   HW(SAIF_CTRL_CLR(_n1))
+#define HWA_SAIF_CTRL_CLR(_n1)                  (HWA_SAIF_CTRL(_n1) + 0x8)
+#define HWT_SAIF_CTRL_CLR(_n1)                  HWIO_32_WO
+#define HWN_SAIF_CTRL_CLR(_n1)                  SAIF_CTRL
+#define HWI_SAIF_CTRL_CLR(_n1)                  (_n1)
+#define HW_SAIF_CTRL_TOG(_n1)                   HW(SAIF_CTRL_TOG(_n1))
+#define HWA_SAIF_CTRL_TOG(_n1)                  (HWA_SAIF_CTRL(_n1) + 0xc)
+#define HWT_SAIF_CTRL_TOG(_n1)                  HWIO_32_WO
+#define HWN_SAIF_CTRL_TOG(_n1)                  SAIF_CTRL
+#define HWI_SAIF_CTRL_TOG(_n1)                  (_n1)
+#define BP_SAIF_CTRL_SFTRST                     31
+#define BM_SAIF_CTRL_SFTRST                     0x80000000
+#define BF_SAIF_CTRL_SFTRST(v)                  (((v) & 0x1) << 31)
+#define BFM_SAIF_CTRL_SFTRST(v)                 BM_SAIF_CTRL_SFTRST
+#define BF_SAIF_CTRL_SFTRST_V(e)                BF_SAIF_CTRL_SFTRST(BV_SAIF_CTRL_SFTRST__##e)
+#define BFM_SAIF_CTRL_SFTRST_V(v)               BM_SAIF_CTRL_SFTRST
+#define BP_SAIF_CTRL_CLKGATE                    30
+#define BM_SAIF_CTRL_CLKGATE                    0x40000000
+#define BF_SAIF_CTRL_CLKGATE(v)                 (((v) & 0x1) << 30)
+#define BFM_SAIF_CTRL_CLKGATE(v)                BM_SAIF_CTRL_CLKGATE
+#define BF_SAIF_CTRL_CLKGATE_V(e)               BF_SAIF_CTRL_CLKGATE(BV_SAIF_CTRL_CLKGATE__##e)
+#define BFM_SAIF_CTRL_CLKGATE_V(v)              BM_SAIF_CTRL_CLKGATE
+#define BP_SAIF_CTRL_BITCLK_MULT_RATE           27
+#define BM_SAIF_CTRL_BITCLK_MULT_RATE           0x38000000
+#define BF_SAIF_CTRL_BITCLK_MULT_RATE(v)        (((v) & 0x7) << 27)
+#define BFM_SAIF_CTRL_BITCLK_MULT_RATE(v)       BM_SAIF_CTRL_BITCLK_MULT_RATE
+#define BF_SAIF_CTRL_BITCLK_MULT_RATE_V(e)      BF_SAIF_CTRL_BITCLK_MULT_RATE(BV_SAIF_CTRL_BITCLK_MULT_RATE__##e)
+#define BFM_SAIF_CTRL_BITCLK_MULT_RATE_V(v)     BM_SAIF_CTRL_BITCLK_MULT_RATE
+#define BP_SAIF_CTRL_BITCLK_BASE_RATE           26
+#define BM_SAIF_CTRL_BITCLK_BASE_RATE           0x4000000
+#define BF_SAIF_CTRL_BITCLK_BASE_RATE(v)        (((v) & 0x1) << 26)
+#define BFM_SAIF_CTRL_BITCLK_BASE_RATE(v)       BM_SAIF_CTRL_BITCLK_BASE_RATE
+#define BF_SAIF_CTRL_BITCLK_BASE_RATE_V(e)      BF_SAIF_CTRL_BITCLK_BASE_RATE(BV_SAIF_CTRL_BITCLK_BASE_RATE__##e)
+#define BFM_SAIF_CTRL_BITCLK_BASE_RATE_V(v)     BM_SAIF_CTRL_BITCLK_BASE_RATE
+#define BP_SAIF_CTRL_FIFO_ERROR_IRQ_EN          25
+#define BM_SAIF_CTRL_FIFO_ERROR_IRQ_EN          0x2000000
+#define BF_SAIF_CTRL_FIFO_ERROR_IRQ_EN(v)       (((v) & 0x1) << 25)
+#define BFM_SAIF_CTRL_FIFO_ERROR_IRQ_EN(v)      BM_SAIF_CTRL_FIFO_ERROR_IRQ_EN
+#define BF_SAIF_CTRL_FIFO_ERROR_IRQ_EN_V(e)     BF_SAIF_CTRL_FIFO_ERROR_IRQ_EN(BV_SAIF_CTRL_FIFO_ERROR_IRQ_EN__##e)
+#define BFM_SAIF_CTRL_FIFO_ERROR_IRQ_EN_V(v)    BM_SAIF_CTRL_FIFO_ERROR_IRQ_EN
+#define BP_SAIF_CTRL_FIFO_SERVICE_IRQ_EN        24
+#define BM_SAIF_CTRL_FIFO_SERVICE_IRQ_EN        0x1000000
+#define BF_SAIF_CTRL_FIFO_SERVICE_IRQ_EN(v)     (((v) & 0x1) << 24)
+#define BFM_SAIF_CTRL_FIFO_SERVICE_IRQ_EN(v)    BM_SAIF_CTRL_FIFO_SERVICE_IRQ_EN
+#define BF_SAIF_CTRL_FIFO_SERVICE_IRQ_EN_V(e)   BF_SAIF_CTRL_FIFO_SERVICE_IRQ_EN(BV_SAIF_CTRL_FIFO_SERVICE_IRQ_EN__##e)
+#define BFM_SAIF_CTRL_FIFO_SERVICE_IRQ_EN_V(v)  BM_SAIF_CTRL_FIFO_SERVICE_IRQ_EN
+#define BP_SAIF_CTRL_DMAWAIT_COUNT              16
+#define BM_SAIF_CTRL_DMAWAIT_COUNT              0x1f0000
+#define BF_SAIF_CTRL_DMAWAIT_COUNT(v)           (((v) & 0x1f) << 16)
+#define BFM_SAIF_CTRL_DMAWAIT_COUNT(v)          BM_SAIF_CTRL_DMAWAIT_COUNT
+#define BF_SAIF_CTRL_DMAWAIT_COUNT_V(e)         BF_SAIF_CTRL_DMAWAIT_COUNT(BV_SAIF_CTRL_DMAWAIT_COUNT__##e)
+#define BFM_SAIF_CTRL_DMAWAIT_COUNT_V(v)        BM_SAIF_CTRL_DMAWAIT_COUNT
+#define BP_SAIF_CTRL_CHANNEL_NUM_SELECT         14
+#define BM_SAIF_CTRL_CHANNEL_NUM_SELECT         0xc000
+#define BF_SAIF_CTRL_CHANNEL_NUM_SELECT(v)      (((v) & 0x3) << 14)
+#define BFM_SAIF_CTRL_CHANNEL_NUM_SELECT(v)     BM_SAIF_CTRL_CHANNEL_NUM_SELECT
+#define BF_SAIF_CTRL_CHANNEL_NUM_SELECT_V(e)    BF_SAIF_CTRL_CHANNEL_NUM_SELECT(BV_SAIF_CTRL_CHANNEL_NUM_SELECT__##e)
+#define BFM_SAIF_CTRL_CHANNEL_NUM_SELECT_V(v)   BM_SAIF_CTRL_CHANNEL_NUM_SELECT
+#define BP_SAIF_CTRL_BIT_ORDER                  12
+#define BM_SAIF_CTRL_BIT_ORDER                  0x1000
+#define BF_SAIF_CTRL_BIT_ORDER(v)               (((v) & 0x1) << 12)
+#define BFM_SAIF_CTRL_BIT_ORDER(v)              BM_SAIF_CTRL_BIT_ORDER
+#define BF_SAIF_CTRL_BIT_ORDER_V(e)             BF_SAIF_CTRL_BIT_ORDER(BV_SAIF_CTRL_BIT_ORDER__##e)
+#define BFM_SAIF_CTRL_BIT_ORDER_V(v)            BM_SAIF_CTRL_BIT_ORDER
+#define BP_SAIF_CTRL_DELAY                      11
+#define BM_SAIF_CTRL_DELAY                      0x800
+#define BF_SAIF_CTRL_DELAY(v)                   (((v) & 0x1) << 11)
+#define BFM_SAIF_CTRL_DELAY(v)                  BM_SAIF_CTRL_DELAY
+#define BF_SAIF_CTRL_DELAY_V(e)                 BF_SAIF_CTRL_DELAY(BV_SAIF_CTRL_DELAY__##e)
+#define BFM_SAIF_CTRL_DELAY_V(v)                BM_SAIF_CTRL_DELAY
+#define BP_SAIF_CTRL_JUSTIFY                    10
+#define BM_SAIF_CTRL_JUSTIFY                    0x400
+#define BF_SAIF_CTRL_JUSTIFY(v)                 (((v) & 0x1) << 10)
+#define BFM_SAIF_CTRL_JUSTIFY(v)                BM_SAIF_CTRL_JUSTIFY
+#define BF_SAIF_CTRL_JUSTIFY_V(e)               BF_SAIF_CTRL_JUSTIFY(BV_SAIF_CTRL_JUSTIFY__##e)
+#define BFM_SAIF_CTRL_JUSTIFY_V(v)              BM_SAIF_CTRL_JUSTIFY
+#define BP_SAIF_CTRL_LRCLK_POLARITY             9
+#define BM_SAIF_CTRL_LRCLK_POLARITY             0x200
+#define BF_SAIF_CTRL_LRCLK_POLARITY(v)          (((v) & 0x1) << 9)
+#define BFM_SAIF_CTRL_LRCLK_POLARITY(v)         BM_SAIF_CTRL_LRCLK_POLARITY
+#define BF_SAIF_CTRL_LRCLK_POLARITY_V(e)        BF_SAIF_CTRL_LRCLK_POLARITY(BV_SAIF_CTRL_LRCLK_POLARITY__##e)
+#define BFM_SAIF_CTRL_LRCLK_POLARITY_V(v)       BM_SAIF_CTRL_LRCLK_POLARITY
+#define BP_SAIF_CTRL_BITCLK_EDGE                8
+#define BM_SAIF_CTRL_BITCLK_EDGE                0x100
+#define BF_SAIF_CTRL_BITCLK_EDGE(v)             (((v) & 0x1) << 8)
+#define BFM_SAIF_CTRL_BITCLK_EDGE(v)            BM_SAIF_CTRL_BITCLK_EDGE
+#define BF_SAIF_CTRL_BITCLK_EDGE_V(e)           BF_SAIF_CTRL_BITCLK_EDGE(BV_SAIF_CTRL_BITCLK_EDGE__##e)
+#define BFM_SAIF_CTRL_BITCLK_EDGE_V(v)          BM_SAIF_CTRL_BITCLK_EDGE
+#define BP_SAIF_CTRL_WORD_LENGTH                4
+#define BM_SAIF_CTRL_WORD_LENGTH                0xf0
+#define BF_SAIF_CTRL_WORD_LENGTH(v)             (((v) & 0xf) << 4)
+#define BFM_SAIF_CTRL_WORD_LENGTH(v)            BM_SAIF_CTRL_WORD_LENGTH
+#define BF_SAIF_CTRL_WORD_LENGTH_V(e)           BF_SAIF_CTRL_WORD_LENGTH(BV_SAIF_CTRL_WORD_LENGTH__##e)
+#define BFM_SAIF_CTRL_WORD_LENGTH_V(v)          BM_SAIF_CTRL_WORD_LENGTH
+#define BP_SAIF_CTRL_BITCLK_48XFS_ENABLE        3
+#define BM_SAIF_CTRL_BITCLK_48XFS_ENABLE        0x8
+#define BF_SAIF_CTRL_BITCLK_48XFS_ENABLE(v)     (((v) & 0x1) << 3)
+#define BFM_SAIF_CTRL_BITCLK_48XFS_ENABLE(v)    BM_SAIF_CTRL_BITCLK_48XFS_ENABLE
+#define BF_SAIF_CTRL_BITCLK_48XFS_ENABLE_V(e)   BF_SAIF_CTRL_BITCLK_48XFS_ENABLE(BV_SAIF_CTRL_BITCLK_48XFS_ENABLE__##e)
+#define BFM_SAIF_CTRL_BITCLK_48XFS_ENABLE_V(v)  BM_SAIF_CTRL_BITCLK_48XFS_ENABLE
+#define BP_SAIF_CTRL_SLAVE_MODE                 2
+#define BM_SAIF_CTRL_SLAVE_MODE                 0x4
+#define BF_SAIF_CTRL_SLAVE_MODE(v)              (((v) & 0x1) << 2)
+#define BFM_SAIF_CTRL_SLAVE_MODE(v)             BM_SAIF_CTRL_SLAVE_MODE
+#define BF_SAIF_CTRL_SLAVE_MODE_V(e)            BF_SAIF_CTRL_SLAVE_MODE(BV_SAIF_CTRL_SLAVE_MODE__##e)
+#define BFM_SAIF_CTRL_SLAVE_MODE_V(v)           BM_SAIF_CTRL_SLAVE_MODE
+#define BP_SAIF_CTRL_READ_MODE                  1
+#define BM_SAIF_CTRL_READ_MODE                  0x2
+#define BF_SAIF_CTRL_READ_MODE(v)               (((v) & 0x1) << 1)
+#define BFM_SAIF_CTRL_READ_MODE(v)              BM_SAIF_CTRL_READ_MODE
+#define BF_SAIF_CTRL_READ_MODE_V(e)             BF_SAIF_CTRL_READ_MODE(BV_SAIF_CTRL_READ_MODE__##e)
+#define BFM_SAIF_CTRL_READ_MODE_V(v)            BM_SAIF_CTRL_READ_MODE
+#define BP_SAIF_CTRL_RUN                        0
+#define BM_SAIF_CTRL_RUN                        0x1
+#define BF_SAIF_CTRL_RUN(v)                     (((v) & 0x1) << 0)
+#define BFM_SAIF_CTRL_RUN(v)                    BM_SAIF_CTRL_RUN
+#define BF_SAIF_CTRL_RUN_V(e)                   BF_SAIF_CTRL_RUN(BV_SAIF_CTRL_RUN__##e)
+#define BFM_SAIF_CTRL_RUN_V(v)                  BM_SAIF_CTRL_RUN
+
+#define HW_SAIF_STAT(_n1)                       HW(SAIF_STAT(_n1))
+#define HWA_SAIF_STAT(_n1)                      (((_n1) == 1 ? 0x80042000 : 0x80046000) + 0x10)
+#define HWT_SAIF_STAT(_n1)                      HWIO_32_RW
+#define HWN_SAIF_STAT(_n1)                      SAIF_STAT
+#define HWI_SAIF_STAT(_n1)                      (_n1)
+#define HW_SAIF_STAT_SET(_n1)                   HW(SAIF_STAT_SET(_n1))
+#define HWA_SAIF_STAT_SET(_n1)                  (HWA_SAIF_STAT(_n1) + 0x4)
+#define HWT_SAIF_STAT_SET(_n1)                  HWIO_32_WO
+#define HWN_SAIF_STAT_SET(_n1)                  SAIF_STAT
+#define HWI_SAIF_STAT_SET(_n1)                  (_n1)
+#define HW_SAIF_STAT_CLR(_n1)                   HW(SAIF_STAT_CLR(_n1))
+#define HWA_SAIF_STAT_CLR(_n1)                  (HWA_SAIF_STAT(_n1) + 0x8)
+#define HWT_SAIF_STAT_CLR(_n1)                  HWIO_32_WO
+#define HWN_SAIF_STAT_CLR(_n1)                  SAIF_STAT
+#define HWI_SAIF_STAT_CLR(_n1)                  (_n1)
+#define HW_SAIF_STAT_TOG(_n1)                   HW(SAIF_STAT_TOG(_n1))
+#define HWA_SAIF_STAT_TOG(_n1)                  (HWA_SAIF_STAT(_n1) + 0xc)
+#define HWT_SAIF_STAT_TOG(_n1)                  HWIO_32_WO
+#define HWN_SAIF_STAT_TOG(_n1)                  SAIF_STAT
+#define HWI_SAIF_STAT_TOG(_n1)                  (_n1)
+#define BP_SAIF_STAT_PRESENT                    31
+#define BM_SAIF_STAT_PRESENT                    0x80000000
+#define BF_SAIF_STAT_PRESENT(v)                 (((v) & 0x1) << 31)
+#define BFM_SAIF_STAT_PRESENT(v)                BM_SAIF_STAT_PRESENT
+#define BF_SAIF_STAT_PRESENT_V(e)               BF_SAIF_STAT_PRESENT(BV_SAIF_STAT_PRESENT__##e)
+#define BFM_SAIF_STAT_PRESENT_V(v)              BM_SAIF_STAT_PRESENT
+#define BP_SAIF_STAT_DMA_PREQ                   16
+#define BM_SAIF_STAT_DMA_PREQ                   0x10000
+#define BF_SAIF_STAT_DMA_PREQ(v)                (((v) & 0x1) << 16)
+#define BFM_SAIF_STAT_DMA_PREQ(v)               BM_SAIF_STAT_DMA_PREQ
+#define BF_SAIF_STAT_DMA_PREQ_V(e)              BF_SAIF_STAT_DMA_PREQ(BV_SAIF_STAT_DMA_PREQ__##e)
+#define BFM_SAIF_STAT_DMA_PREQ_V(v)             BM_SAIF_STAT_DMA_PREQ
+#define BP_SAIF_STAT_FIFO_UNDERFLOW_IRQ         6
+#define BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ         0x40
+#define BF_SAIF_STAT_FIFO_UNDERFLOW_IRQ(v)      (((v) & 0x1) << 6)
+#define BFM_SAIF_STAT_FIFO_UNDERFLOW_IRQ(v)     BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ
+#define BF_SAIF_STAT_FIFO_UNDERFLOW_IRQ_V(e)    BF_SAIF_STAT_FIFO_UNDERFLOW_IRQ(BV_SAIF_STAT_FIFO_UNDERFLOW_IRQ__##e)
+#define BFM_SAIF_STAT_FIFO_UNDERFLOW_IRQ_V(v)   BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ
+#define BP_SAIF_STAT_FIFO_OVERFLOW_IRQ          5
+#define BM_SAIF_STAT_FIFO_OVERFLOW_IRQ          0x20
+#define BF_SAIF_STAT_FIFO_OVERFLOW_IRQ(v)       (((v) & 0x1) << 5)
+#define BFM_SAIF_STAT_FIFO_OVERFLOW_IRQ(v)      BM_SAIF_STAT_FIFO_OVERFLOW_IRQ
+#define BF_SAIF_STAT_FIFO_OVERFLOW_IRQ_V(e)     BF_SAIF_STAT_FIFO_OVERFLOW_IRQ(BV_SAIF_STAT_FIFO_OVERFLOW_IRQ__##e)
+#define BFM_SAIF_STAT_FIFO_OVERFLOW_IRQ_V(v)    BM_SAIF_STAT_FIFO_OVERFLOW_IRQ
+#define BP_SAIF_STAT_FIFO_SERVICE_IRQ           4
+#define BM_SAIF_STAT_FIFO_SERVICE_IRQ           0x10
+#define BF_SAIF_STAT_FIFO_SERVICE_IRQ(v)        (((v) & 0x1) << 4)
+#define BFM_SAIF_STAT_FIFO_SERVICE_IRQ(v)       BM_SAIF_STAT_FIFO_SERVICE_IRQ
+#define BF_SAIF_STAT_FIFO_SERVICE_IRQ_V(e)      BF_SAIF_STAT_FIFO_SERVICE_IRQ(BV_SAIF_STAT_FIFO_SERVICE_IRQ__##e)
+#define BFM_SAIF_STAT_FIFO_SERVICE_IRQ_V(v)     BM_SAIF_STAT_FIFO_SERVICE_IRQ
+#define BP_SAIF_STAT_BUSY                       0
+#define BM_SAIF_STAT_BUSY                       0x1
+#define BF_SAIF_STAT_BUSY(v)                    (((v) & 0x1) << 0)
+#define BFM_SAIF_STAT_BUSY(v)                   BM_SAIF_STAT_BUSY
+#define BF_SAIF_STAT_BUSY_V(e)                  BF_SAIF_STAT_BUSY(BV_SAIF_STAT_BUSY__##e)
+#define BFM_SAIF_STAT_BUSY_V(v)                 BM_SAIF_STAT_BUSY
+
+#define HW_SAIF_DATA(_n1)               HW(SAIF_DATA(_n1))
+#define HWA_SAIF_DATA(_n1)              (((_n1) == 1 ? 0x80042000 : 0x80046000) + 0x20)
+#define HWT_SAIF_DATA(_n1)              HWIO_32_RW
+#define HWN_SAIF_DATA(_n1)              SAIF_DATA
+#define HWI_SAIF_DATA(_n1)              (_n1)
+#define HW_SAIF_DATA_SET(_n1)           HW(SAIF_DATA_SET(_n1))
+#define HWA_SAIF_DATA_SET(_n1)          (HWA_SAIF_DATA(_n1) + 0x4)
+#define HWT_SAIF_DATA_SET(_n1)          HWIO_32_WO
+#define HWN_SAIF_DATA_SET(_n1)          SAIF_DATA
+#define HWI_SAIF_DATA_SET(_n1)          (_n1)
+#define HW_SAIF_DATA_CLR(_n1)           HW(SAIF_DATA_CLR(_n1))
+#define HWA_SAIF_DATA_CLR(_n1)          (HWA_SAIF_DATA(_n1) + 0x8)
+#define HWT_SAIF_DATA_CLR(_n1)          HWIO_32_WO
+#define HWN_SAIF_DATA_CLR(_n1)          SAIF_DATA
+#define HWI_SAIF_DATA_CLR(_n1)          (_n1)
+#define HW_SAIF_DATA_TOG(_n1)           HW(SAIF_DATA_TOG(_n1))
+#define HWA_SAIF_DATA_TOG(_n1)          (HWA_SAIF_DATA(_n1) + 0xc)
+#define HWT_SAIF_DATA_TOG(_n1)          HWIO_32_WO
+#define HWN_SAIF_DATA_TOG(_n1)          SAIF_DATA
+#define HWI_SAIF_DATA_TOG(_n1)          (_n1)
+#define BP_SAIF_DATA_PCM_RIGHT          16
+#define BM_SAIF_DATA_PCM_RIGHT          0xffff0000
+#define BF_SAIF_DATA_PCM_RIGHT(v)       (((v) & 0xffff) << 16)
+#define BFM_SAIF_DATA_PCM_RIGHT(v)      BM_SAIF_DATA_PCM_RIGHT
+#define BF_SAIF_DATA_PCM_RIGHT_V(e)     BF_SAIF_DATA_PCM_RIGHT(BV_SAIF_DATA_PCM_RIGHT__##e)
+#define BFM_SAIF_DATA_PCM_RIGHT_V(v)    BM_SAIF_DATA_PCM_RIGHT
+#define BP_SAIF_DATA_PCM_LEFT           0
+#define BM_SAIF_DATA_PCM_LEFT           0xffff
+#define BF_SAIF_DATA_PCM_LEFT(v)        (((v) & 0xffff) << 0)
+#define BFM_SAIF_DATA_PCM_LEFT(v)       BM_SAIF_DATA_PCM_LEFT
+#define BF_SAIF_DATA_PCM_LEFT_V(e)      BF_SAIF_DATA_PCM_LEFT(BV_SAIF_DATA_PCM_LEFT__##e)
+#define BFM_SAIF_DATA_PCM_LEFT_V(v)     BM_SAIF_DATA_PCM_LEFT
+
+#define HW_SAIF_VERSION(_n1)        HW(SAIF_VERSION(_n1))
+#define HWA_SAIF_VERSION(_n1)       (((_n1) == 1 ? 0x80042000 : 0x80046000) + 0x30)
+#define HWT_SAIF_VERSION(_n1)       HWIO_32_RW
+#define HWN_SAIF_VERSION(_n1)       SAIF_VERSION
+#define HWI_SAIF_VERSION(_n1)       (_n1)
+#define BP_SAIF_VERSION_MAJOR       24
+#define BM_SAIF_VERSION_MAJOR       0xff000000
+#define BF_SAIF_VERSION_MAJOR(v)    (((v) & 0xff) << 24)
+#define BFM_SAIF_VERSION_MAJOR(v)   BM_SAIF_VERSION_MAJOR
+#define BF_SAIF_VERSION_MAJOR_V(e)  BF_SAIF_VERSION_MAJOR(BV_SAIF_VERSION_MAJOR__##e)
+#define BFM_SAIF_VERSION_MAJOR_V(v) BM_SAIF_VERSION_MAJOR
+#define BP_SAIF_VERSION_MINOR       16
+#define BM_SAIF_VERSION_MINOR       0xff0000
+#define BF_SAIF_VERSION_MINOR(v)    (((v) & 0xff) << 16)
+#define BFM_SAIF_VERSION_MINOR(v)   BM_SAIF_VERSION_MINOR
+#define BF_SAIF_VERSION_MINOR_V(e)  BF_SAIF_VERSION_MINOR(BV_SAIF_VERSION_MINOR__##e)
+#define BFM_SAIF_VERSION_MINOR_V(v) BM_SAIF_VERSION_MINOR
+#define BP_SAIF_VERSION_STEP        0
+#define BM_SAIF_VERSION_STEP        0xffff
+#define BF_SAIF_VERSION_STEP(v)     (((v) & 0xffff) << 0)
+#define BFM_SAIF_VERSION_STEP(v)    BM_SAIF_VERSION_STEP
+#define BF_SAIF_VERSION_STEP_V(e)   BF_SAIF_VERSION_STEP(BV_SAIF_VERSION_STEP__##e)
+#define BFM_SAIF_VERSION_STEP_V(v)  BM_SAIF_VERSION_STEP
+
+#endif /* __HEADERGEN_STMP3700_SAIF_H__*/
diff --git a/firmware/target/arm/imx233/regs/stmp3700/spdif.h b/firmware/target/arm/imx233/regs/stmp3700/spdif.h
new file mode 100644
index 0000000000..53da6347b1
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3700/spdif.h
@@ -0,0 +1,309 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * stmp3700 version: 2.4.0
+ * stmp3700 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_STMP3700_SPDIF_H__
+#define __HEADERGEN_STMP3700_SPDIF_H__
+
+#define HW_SPDIF_CTRL                           HW(SPDIF_CTRL)
+#define HWA_SPDIF_CTRL                          (0x80054000 + 0x0)
+#define HWT_SPDIF_CTRL                          HWIO_32_RW
+#define HWN_SPDIF_CTRL                          SPDIF_CTRL
+#define HWI_SPDIF_CTRL                          
+#define HW_SPDIF_CTRL_SET                       HW(SPDIF_CTRL_SET)
+#define HWA_SPDIF_CTRL_SET                      (HWA_SPDIF_CTRL + 0x4)
+#define HWT_SPDIF_CTRL_SET                      HWIO_32_WO
+#define HWN_SPDIF_CTRL_SET                      SPDIF_CTRL
+#define HWI_SPDIF_CTRL_SET                      
+#define HW_SPDIF_CTRL_CLR                       HW(SPDIF_CTRL_CLR)
+#define HWA_SPDIF_CTRL_CLR                      (HWA_SPDIF_CTRL + 0x8)
+#define HWT_SPDIF_CTRL_CLR                      HWIO_32_WO
+#define HWN_SPDIF_CTRL_CLR                      SPDIF_CTRL
+#define HWI_SPDIF_CTRL_CLR                      
+#define HW_SPDIF_CTRL_TOG                       HW(SPDIF_CTRL_TOG)
+#define HWA_SPDIF_CTRL_TOG                      (HWA_SPDIF_CTRL + 0xc)
+#define HWT_SPDIF_CTRL_TOG                      HWIO_32_WO
+#define HWN_SPDIF_CTRL_TOG                      SPDIF_CTRL
+#define HWI_SPDIF_CTRL_TOG                      
+#define BP_SPDIF_CTRL_SFTRST                    31
+#define BM_SPDIF_CTRL_SFTRST                    0x80000000
+#define BF_SPDIF_CTRL_SFTRST(v)                 (((v) & 0x1) << 31)
+#define BFM_SPDIF_CTRL_SFTRST(v)                BM_SPDIF_CTRL_SFTRST
+#define BF_SPDIF_CTRL_SFTRST_V(e)               BF_SPDIF_CTRL_SFTRST(BV_SPDIF_CTRL_SFTRST__##e)
+#define BFM_SPDIF_CTRL_SFTRST_V(v)              BM_SPDIF_CTRL_SFTRST
+#define BP_SPDIF_CTRL_CLKGATE                   30
+#define BM_SPDIF_CTRL_CLKGATE                   0x40000000
+#define BF_SPDIF_CTRL_CLKGATE(v)                (((v) & 0x1) << 30)
+#define BFM_SPDIF_CTRL_CLKGATE(v)               BM_SPDIF_CTRL_CLKGATE
+#define BF_SPDIF_CTRL_CLKGATE_V(e)              BF_SPDIF_CTRL_CLKGATE(BV_SPDIF_CTRL_CLKGATE__##e)
+#define BFM_SPDIF_CTRL_CLKGATE_V(v)             BM_SPDIF_CTRL_CLKGATE
+#define BP_SPDIF_CTRL_DMAWAIT_COUNT             16
+#define BM_SPDIF_CTRL_DMAWAIT_COUNT             0x1f0000
+#define BF_SPDIF_CTRL_DMAWAIT_COUNT(v)          (((v) & 0x1f) << 16)
+#define BFM_SPDIF_CTRL_DMAWAIT_COUNT(v)         BM_SPDIF_CTRL_DMAWAIT_COUNT
+#define BF_SPDIF_CTRL_DMAWAIT_COUNT_V(e)        BF_SPDIF_CTRL_DMAWAIT_COUNT(BV_SPDIF_CTRL_DMAWAIT_COUNT__##e)
+#define BFM_SPDIF_CTRL_DMAWAIT_COUNT_V(v)       BM_SPDIF_CTRL_DMAWAIT_COUNT
+#define BP_SPDIF_CTRL_WAIT_END_XFER             5
+#define BM_SPDIF_CTRL_WAIT_END_XFER             0x20
+#define BF_SPDIF_CTRL_WAIT_END_XFER(v)          (((v) & 0x1) << 5)
+#define BFM_SPDIF_CTRL_WAIT_END_XFER(v)         BM_SPDIF_CTRL_WAIT_END_XFER
+#define BF_SPDIF_CTRL_WAIT_END_XFER_V(e)        BF_SPDIF_CTRL_WAIT_END_XFER(BV_SPDIF_CTRL_WAIT_END_XFER__##e)
+#define BFM_SPDIF_CTRL_WAIT_END_XFER_V(v)       BM_SPDIF_CTRL_WAIT_END_XFER
+#define BP_SPDIF_CTRL_WORD_LENGTH               4
+#define BM_SPDIF_CTRL_WORD_LENGTH               0x10
+#define BF_SPDIF_CTRL_WORD_LENGTH(v)            (((v) & 0x1) << 4)
+#define BFM_SPDIF_CTRL_WORD_LENGTH(v)           BM_SPDIF_CTRL_WORD_LENGTH
+#define BF_SPDIF_CTRL_WORD_LENGTH_V(e)          BF_SPDIF_CTRL_WORD_LENGTH(BV_SPDIF_CTRL_WORD_LENGTH__##e)
+#define BFM_SPDIF_CTRL_WORD_LENGTH_V(v)         BM_SPDIF_CTRL_WORD_LENGTH
+#define BP_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ        3
+#define BM_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ        0x8
+#define BF_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ(v)     (((v) & 0x1) << 3)
+#define BFM_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ(v)    BM_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ
+#define BF_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ_V(e)   BF_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ(BV_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ__##e)
+#define BFM_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ_V(v)  BM_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ
+#define BP_SPDIF_CTRL_FIFO_OVERFLOW_IRQ         2
+#define BM_SPDIF_CTRL_FIFO_OVERFLOW_IRQ         0x4
+#define BF_SPDIF_CTRL_FIFO_OVERFLOW_IRQ(v)      (((v) & 0x1) << 2)
+#define BFM_SPDIF_CTRL_FIFO_OVERFLOW_IRQ(v)     BM_SPDIF_CTRL_FIFO_OVERFLOW_IRQ
+#define BF_SPDIF_CTRL_FIFO_OVERFLOW_IRQ_V(e)    BF_SPDIF_CTRL_FIFO_OVERFLOW_IRQ(BV_SPDIF_CTRL_FIFO_OVERFLOW_IRQ__##e)
+#define BFM_SPDIF_CTRL_FIFO_OVERFLOW_IRQ_V(v)   BM_SPDIF_CTRL_FIFO_OVERFLOW_IRQ
+#define BP_SPDIF_CTRL_FIFO_ERROR_IRQ_EN         1
+#define BM_SPDIF_CTRL_FIFO_ERROR_IRQ_EN         0x2
+#define BF_SPDIF_CTRL_FIFO_ERROR_IRQ_EN(v)      (((v) & 0x1) << 1)
+#define BFM_SPDIF_CTRL_FIFO_ERROR_IRQ_EN(v)     BM_SPDIF_CTRL_FIFO_ERROR_IRQ_EN
+#define BF_SPDIF_CTRL_FIFO_ERROR_IRQ_EN_V(e)    BF_SPDIF_CTRL_FIFO_ERROR_IRQ_EN(BV_SPDIF_CTRL_FIFO_ERROR_IRQ_EN__##e)
+#define BFM_SPDIF_CTRL_FIFO_ERROR_IRQ_EN_V(v)   BM_SPDIF_CTRL_FIFO_ERROR_IRQ_EN
+#define BP_SPDIF_CTRL_RUN                       0
+#define BM_SPDIF_CTRL_RUN                       0x1
+#define BF_SPDIF_CTRL_RUN(v)                    (((v) & 0x1) << 0)
+#define BFM_SPDIF_CTRL_RUN(v)                   BM_SPDIF_CTRL_RUN
+#define BF_SPDIF_CTRL_RUN_V(e)                  BF_SPDIF_CTRL_RUN(BV_SPDIF_CTRL_RUN__##e)
+#define BFM_SPDIF_CTRL_RUN_V(v)                 BM_SPDIF_CTRL_RUN
+
+#define HW_SPDIF_STAT                   HW(SPDIF_STAT)
+#define HWA_SPDIF_STAT                  (0x80054000 + 0x10)
+#define HWT_SPDIF_STAT                  HWIO_32_RW
+#define HWN_SPDIF_STAT                  SPDIF_STAT
+#define HWI_SPDIF_STAT                  
+#define BP_SPDIF_STAT_PRESENT           31
+#define BM_SPDIF_STAT_PRESENT           0x80000000
+#define BF_SPDIF_STAT_PRESENT(v)        (((v) & 0x1) << 31)
+#define BFM_SPDIF_STAT_PRESENT(v)       BM_SPDIF_STAT_PRESENT
+#define BF_SPDIF_STAT_PRESENT_V(e)      BF_SPDIF_STAT_PRESENT(BV_SPDIF_STAT_PRESENT__##e)
+#define BFM_SPDIF_STAT_PRESENT_V(v)     BM_SPDIF_STAT_PRESENT
+#define BP_SPDIF_STAT_END_XFER          0
+#define BM_SPDIF_STAT_END_XFER          0x1
+#define BF_SPDIF_STAT_END_XFER(v)       (((v) & 0x1) << 0)
+#define BFM_SPDIF_STAT_END_XFER(v)      BM_SPDIF_STAT_END_XFER
+#define BF_SPDIF_STAT_END_XFER_V(e)     BF_SPDIF_STAT_END_XFER(BV_SPDIF_STAT_END_XFER__##e)
+#define BFM_SPDIF_STAT_END_XFER_V(v)    BM_SPDIF_STAT_END_XFER
+
+#define HW_SPDIF_FRAMECTRL                  HW(SPDIF_FRAMECTRL)
+#define HWA_SPDIF_FRAMECTRL                 (0x80054000 + 0x20)
+#define HWT_SPDIF_FRAMECTRL                 HWIO_32_RW
+#define HWN_SPDIF_FRAMECTRL                 SPDIF_FRAMECTRL
+#define HWI_SPDIF_FRAMECTRL                 
+#define HW_SPDIF_FRAMECTRL_SET              HW(SPDIF_FRAMECTRL_SET)
+#define HWA_SPDIF_FRAMECTRL_SET             (HWA_SPDIF_FRAMECTRL + 0x4)
+#define HWT_SPDIF_FRAMECTRL_SET             HWIO_32_WO
+#define HWN_SPDIF_FRAMECTRL_SET             SPDIF_FRAMECTRL
+#define HWI_SPDIF_FRAMECTRL_SET             
+#define HW_SPDIF_FRAMECTRL_CLR              HW(SPDIF_FRAMECTRL_CLR)
+#define HWA_SPDIF_FRAMECTRL_CLR             (HWA_SPDIF_FRAMECTRL + 0x8)
+#define HWT_SPDIF_FRAMECTRL_CLR             HWIO_32_WO
+#define HWN_SPDIF_FRAMECTRL_CLR             SPDIF_FRAMECTRL
+#define HWI_SPDIF_FRAMECTRL_CLR             
+#define HW_SPDIF_FRAMECTRL_TOG              HW(SPDIF_FRAMECTRL_TOG)
+#define HWA_SPDIF_FRAMECTRL_TOG             (HWA_SPDIF_FRAMECTRL + 0xc)
+#define HWT_SPDIF_FRAMECTRL_TOG             HWIO_32_WO
+#define HWN_SPDIF_FRAMECTRL_TOG             SPDIF_FRAMECTRL
+#define HWI_SPDIF_FRAMECTRL_TOG             
+#define BP_SPDIF_FRAMECTRL_V_CONFIG         17
+#define BM_SPDIF_FRAMECTRL_V_CONFIG         0x20000
+#define BF_SPDIF_FRAMECTRL_V_CONFIG(v)      (((v) & 0x1) << 17)
+#define BFM_SPDIF_FRAMECTRL_V_CONFIG(v)     BM_SPDIF_FRAMECTRL_V_CONFIG
+#define BF_SPDIF_FRAMECTRL_V_CONFIG_V(e)    BF_SPDIF_FRAMECTRL_V_CONFIG(BV_SPDIF_FRAMECTRL_V_CONFIG__##e)
+#define BFM_SPDIF_FRAMECTRL_V_CONFIG_V(v)   BM_SPDIF_FRAMECTRL_V_CONFIG
+#define BP_SPDIF_FRAMECTRL_AUTO_MUTE        16
+#define BM_SPDIF_FRAMECTRL_AUTO_MUTE        0x10000
+#define BF_SPDIF_FRAMECTRL_AUTO_MUTE(v)     (((v) & 0x1) << 16)
+#define BFM_SPDIF_FRAMECTRL_AUTO_MUTE(v)    BM_SPDIF_FRAMECTRL_AUTO_MUTE
+#define BF_SPDIF_FRAMECTRL_AUTO_MUTE_V(e)   BF_SPDIF_FRAMECTRL_AUTO_MUTE(BV_SPDIF_FRAMECTRL_AUTO_MUTE__##e)
+#define BFM_SPDIF_FRAMECTRL_AUTO_MUTE_V(v)  BM_SPDIF_FRAMECTRL_AUTO_MUTE
+#define BP_SPDIF_FRAMECTRL_USER_DATA        14
+#define BM_SPDIF_FRAMECTRL_USER_DATA        0x4000
+#define BF_SPDIF_FRAMECTRL_USER_DATA(v)     (((v) & 0x1) << 14)
+#define BFM_SPDIF_FRAMECTRL_USER_DATA(v)    BM_SPDIF_FRAMECTRL_USER_DATA
+#define BF_SPDIF_FRAMECTRL_USER_DATA_V(e)   BF_SPDIF_FRAMECTRL_USER_DATA(BV_SPDIF_FRAMECTRL_USER_DATA__##e)
+#define BFM_SPDIF_FRAMECTRL_USER_DATA_V(v)  BM_SPDIF_FRAMECTRL_USER_DATA
+#define BP_SPDIF_FRAMECTRL_V                13
+#define BM_SPDIF_FRAMECTRL_V                0x2000
+#define BF_SPDIF_FRAMECTRL_V(v)             (((v) & 0x1) << 13)
+#define BFM_SPDIF_FRAMECTRL_V(v)            BM_SPDIF_FRAMECTRL_V
+#define BF_SPDIF_FRAMECTRL_V_V(e)           BF_SPDIF_FRAMECTRL_V(BV_SPDIF_FRAMECTRL_V__##e)
+#define BFM_SPDIF_FRAMECTRL_V_V(v)          BM_SPDIF_FRAMECTRL_V
+#define BP_SPDIF_FRAMECTRL_L                12
+#define BM_SPDIF_FRAMECTRL_L                0x1000
+#define BF_SPDIF_FRAMECTRL_L(v)             (((v) & 0x1) << 12)
+#define BFM_SPDIF_FRAMECTRL_L(v)            BM_SPDIF_FRAMECTRL_L
+#define BF_SPDIF_FRAMECTRL_L_V(e)           BF_SPDIF_FRAMECTRL_L(BV_SPDIF_FRAMECTRL_L__##e)
+#define BFM_SPDIF_FRAMECTRL_L_V(v)          BM_SPDIF_FRAMECTRL_L
+#define BP_SPDIF_FRAMECTRL_CC               4
+#define BM_SPDIF_FRAMECTRL_CC               0x7f0
+#define BF_SPDIF_FRAMECTRL_CC(v)            (((v) & 0x7f) << 4)
+#define BFM_SPDIF_FRAMECTRL_CC(v)           BM_SPDIF_FRAMECTRL_CC
+#define BF_SPDIF_FRAMECTRL_CC_V(e)          BF_SPDIF_FRAMECTRL_CC(BV_SPDIF_FRAMECTRL_CC__##e)
+#define BFM_SPDIF_FRAMECTRL_CC_V(v)         BM_SPDIF_FRAMECTRL_CC
+#define BP_SPDIF_FRAMECTRL_PRE              3
+#define BM_SPDIF_FRAMECTRL_PRE              0x8
+#define BF_SPDIF_FRAMECTRL_PRE(v)           (((v) & 0x1) << 3)
+#define BFM_SPDIF_FRAMECTRL_PRE(v)          BM_SPDIF_FRAMECTRL_PRE
+#define BF_SPDIF_FRAMECTRL_PRE_V(e)         BF_SPDIF_FRAMECTRL_PRE(BV_SPDIF_FRAMECTRL_PRE__##e)
+#define BFM_SPDIF_FRAMECTRL_PRE_V(v)        BM_SPDIF_FRAMECTRL_PRE
+#define BP_SPDIF_FRAMECTRL_COPY             2
+#define BM_SPDIF_FRAMECTRL_COPY             0x4
+#define BF_SPDIF_FRAMECTRL_COPY(v)          (((v) & 0x1) << 2)
+#define BFM_SPDIF_FRAMECTRL_COPY(v)         BM_SPDIF_FRAMECTRL_COPY
+#define BF_SPDIF_FRAMECTRL_COPY_V(e)        BF_SPDIF_FRAMECTRL_COPY(BV_SPDIF_FRAMECTRL_COPY__##e)
+#define BFM_SPDIF_FRAMECTRL_COPY_V(v)       BM_SPDIF_FRAMECTRL_COPY
+#define BP_SPDIF_FRAMECTRL_AUDIO            1
+#define BM_SPDIF_FRAMECTRL_AUDIO            0x2
+#define BF_SPDIF_FRAMECTRL_AUDIO(v)         (((v) & 0x1) << 1)
+#define BFM_SPDIF_FRAMECTRL_AUDIO(v)        BM_SPDIF_FRAMECTRL_AUDIO
+#define BF_SPDIF_FRAMECTRL_AUDIO_V(e)       BF_SPDIF_FRAMECTRL_AUDIO(BV_SPDIF_FRAMECTRL_AUDIO__##e)
+#define BFM_SPDIF_FRAMECTRL_AUDIO_V(v)      BM_SPDIF_FRAMECTRL_AUDIO
+#define BP_SPDIF_FRAMECTRL_PRO              0
+#define BM_SPDIF_FRAMECTRL_PRO              0x1
+#define BF_SPDIF_FRAMECTRL_PRO(v)           (((v) & 0x1) << 0)
+#define BFM_SPDIF_FRAMECTRL_PRO(v)          BM_SPDIF_FRAMECTRL_PRO
+#define BF_SPDIF_FRAMECTRL_PRO_V(e)         BF_SPDIF_FRAMECTRL_PRO(BV_SPDIF_FRAMECTRL_PRO__##e)
+#define BFM_SPDIF_FRAMECTRL_PRO_V(v)        BM_SPDIF_FRAMECTRL_PRO
+
+#define HW_SPDIF_SRR                HW(SPDIF_SRR)
+#define HWA_SPDIF_SRR               (0x80054000 + 0x30)
+#define HWT_SPDIF_SRR               HWIO_32_RW
+#define HWN_SPDIF_SRR               SPDIF_SRR
+#define HWI_SPDIF_SRR               
+#define HW_SPDIF_SRR_SET            HW(SPDIF_SRR_SET)
+#define HWA_SPDIF_SRR_SET           (HWA_SPDIF_SRR + 0x4)
+#define HWT_SPDIF_SRR_SET           HWIO_32_WO
+#define HWN_SPDIF_SRR_SET           SPDIF_SRR
+#define HWI_SPDIF_SRR_SET           
+#define HW_SPDIF_SRR_CLR            HW(SPDIF_SRR_CLR)
+#define HWA_SPDIF_SRR_CLR           (HWA_SPDIF_SRR + 0x8)
+#define HWT_SPDIF_SRR_CLR           HWIO_32_WO
+#define HWN_SPDIF_SRR_CLR           SPDIF_SRR
+#define HWI_SPDIF_SRR_CLR           
+#define HW_SPDIF_SRR_TOG            HW(SPDIF_SRR_TOG)
+#define HWA_SPDIF_SRR_TOG           (HWA_SPDIF_SRR + 0xc)
+#define HWT_SPDIF_SRR_TOG           HWIO_32_WO
+#define HWN_SPDIF_SRR_TOG           SPDIF_SRR
+#define HWI_SPDIF_SRR_TOG           
+#define BP_SPDIF_SRR_BASEMULT       28
+#define BM_SPDIF_SRR_BASEMULT       0x70000000
+#define BF_SPDIF_SRR_BASEMULT(v)    (((v) & 0x7) << 28)
+#define BFM_SPDIF_SRR_BASEMULT(v)   BM_SPDIF_SRR_BASEMULT
+#define BF_SPDIF_SRR_BASEMULT_V(e)  BF_SPDIF_SRR_BASEMULT(BV_SPDIF_SRR_BASEMULT__##e)
+#define BFM_SPDIF_SRR_BASEMULT_V(v) BM_SPDIF_SRR_BASEMULT
+#define BP_SPDIF_SRR_RATE           0
+#define BM_SPDIF_SRR_RATE           0xfffff
+#define BF_SPDIF_SRR_RATE(v)        (((v) & 0xfffff) << 0)
+#define BFM_SPDIF_SRR_RATE(v)       BM_SPDIF_SRR_RATE
+#define BF_SPDIF_SRR_RATE_V(e)      BF_SPDIF_SRR_RATE(BV_SPDIF_SRR_RATE__##e)
+#define BFM_SPDIF_SRR_RATE_V(v)     BM_SPDIF_SRR_RATE
+
+#define HW_SPDIF_DEBUG                      HW(SPDIF_DEBUG)
+#define HWA_SPDIF_DEBUG                     (0x80054000 + 0x40)
+#define HWT_SPDIF_DEBUG                     HWIO_32_RW
+#define HWN_SPDIF_DEBUG                     SPDIF_DEBUG
+#define HWI_SPDIF_DEBUG                     
+#define BP_SPDIF_DEBUG_DMA_PREQ             1
+#define BM_SPDIF_DEBUG_DMA_PREQ             0x2
+#define BF_SPDIF_DEBUG_DMA_PREQ(v)          (((v) & 0x1) << 1)
+#define BFM_SPDIF_DEBUG_DMA_PREQ(v)         BM_SPDIF_DEBUG_DMA_PREQ
+#define BF_SPDIF_DEBUG_DMA_PREQ_V(e)        BF_SPDIF_DEBUG_DMA_PREQ(BV_SPDIF_DEBUG_DMA_PREQ__##e)
+#define BFM_SPDIF_DEBUG_DMA_PREQ_V(v)       BM_SPDIF_DEBUG_DMA_PREQ
+#define BP_SPDIF_DEBUG_FIFO_STATUS          0
+#define BM_SPDIF_DEBUG_FIFO_STATUS          0x1
+#define BF_SPDIF_DEBUG_FIFO_STATUS(v)       (((v) & 0x1) << 0)
+#define BFM_SPDIF_DEBUG_FIFO_STATUS(v)      BM_SPDIF_DEBUG_FIFO_STATUS
+#define BF_SPDIF_DEBUG_FIFO_STATUS_V(e)     BF_SPDIF_DEBUG_FIFO_STATUS(BV_SPDIF_DEBUG_FIFO_STATUS__##e)
+#define BFM_SPDIF_DEBUG_FIFO_STATUS_V(v)    BM_SPDIF_DEBUG_FIFO_STATUS
+
+#define HW_SPDIF_DATA               HW(SPDIF_DATA)
+#define HWA_SPDIF_DATA              (0x80054000 + 0x50)
+#define HWT_SPDIF_DATA              HWIO_32_RW
+#define HWN_SPDIF_DATA              SPDIF_DATA
+#define HWI_SPDIF_DATA              
+#define HW_SPDIF_DATA_SET           HW(SPDIF_DATA_SET)
+#define HWA_SPDIF_DATA_SET          (HWA_SPDIF_DATA + 0x4)
+#define HWT_SPDIF_DATA_SET          HWIO_32_WO
+#define HWN_SPDIF_DATA_SET          SPDIF_DATA
+#define HWI_SPDIF_DATA_SET          
+#define HW_SPDIF_DATA_CLR           HW(SPDIF_DATA_CLR)
+#define HWA_SPDIF_DATA_CLR          (HWA_SPDIF_DATA + 0x8)
+#define HWT_SPDIF_DATA_CLR          HWIO_32_WO
+#define HWN_SPDIF_DATA_CLR          SPDIF_DATA
+#define HWI_SPDIF_DATA_CLR          
+#define HW_SPDIF_DATA_TOG           HW(SPDIF_DATA_TOG)
+#define HWA_SPDIF_DATA_TOG          (HWA_SPDIF_DATA + 0xc)
+#define HWT_SPDIF_DATA_TOG          HWIO_32_WO
+#define HWN_SPDIF_DATA_TOG          SPDIF_DATA
+#define HWI_SPDIF_DATA_TOG          
+#define BP_SPDIF_DATA_HIGH          16
+#define BM_SPDIF_DATA_HIGH          0xffff0000
+#define BF_SPDIF_DATA_HIGH(v)       (((v) & 0xffff) << 16)
+#define BFM_SPDIF_DATA_HIGH(v)      BM_SPDIF_DATA_HIGH
+#define BF_SPDIF_DATA_HIGH_V(e)     BF_SPDIF_DATA_HIGH(BV_SPDIF_DATA_HIGH__##e)
+#define BFM_SPDIF_DATA_HIGH_V(v)    BM_SPDIF_DATA_HIGH
+#define BP_SPDIF_DATA_LOW           0
+#define BM_SPDIF_DATA_LOW           0xffff
+#define BF_SPDIF_DATA_LOW(v)        (((v) & 0xffff) << 0)
+#define BFM_SPDIF_DATA_LOW(v)       BM_SPDIF_DATA_LOW
+#define BF_SPDIF_DATA_LOW_V(e)      BF_SPDIF_DATA_LOW(BV_SPDIF_DATA_LOW__##e)
+#define BFM_SPDIF_DATA_LOW_V(v)     BM_SPDIF_DATA_LOW
+
+#define HW_SPDIF_VERSION                HW(SPDIF_VERSION)
+#define HWA_SPDIF_VERSION               (0x80054000 + 0x60)
+#define HWT_SPDIF_VERSION               HWIO_32_RW
+#define HWN_SPDIF_VERSION               SPDIF_VERSION
+#define HWI_SPDIF_VERSION               
+#define BP_SPDIF_VERSION_MAJOR          24
+#define BM_SPDIF_VERSION_MAJOR          0xff000000
+#define BF_SPDIF_VERSION_MAJOR(v)       (((v) & 0xff) << 24)
+#define BFM_SPDIF_VERSION_MAJOR(v)      BM_SPDIF_VERSION_MAJOR
+#define BF_SPDIF_VERSION_MAJOR_V(e)     BF_SPDIF_VERSION_MAJOR(BV_SPDIF_VERSION_MAJOR__##e)
+#define BFM_SPDIF_VERSION_MAJOR_V(v)    BM_SPDIF_VERSION_MAJOR
+#define BP_SPDIF_VERSION_MINOR          16
+#define BM_SPDIF_VERSION_MINOR          0xff0000
+#define BF_SPDIF_VERSION_MINOR(v)       (((v) & 0xff) << 16)
+#define BFM_SPDIF_VERSION_MINOR(v)      BM_SPDIF_VERSION_MINOR
+#define BF_SPDIF_VERSION_MINOR_V(e)     BF_SPDIF_VERSION_MINOR(BV_SPDIF_VERSION_MINOR__##e)
+#define BFM_SPDIF_VERSION_MINOR_V(v)    BM_SPDIF_VERSION_MINOR
+#define BP_SPDIF_VERSION_STEP           0
+#define BM_SPDIF_VERSION_STEP           0xffff
+#define BF_SPDIF_VERSION_STEP(v)        (((v) & 0xffff) << 0)
+#define BFM_SPDIF_VERSION_STEP(v)       BM_SPDIF_VERSION_STEP
+#define BF_SPDIF_VERSION_STEP_V(e)      BF_SPDIF_VERSION_STEP(BV_SPDIF_VERSION_STEP__##e)
+#define BFM_SPDIF_VERSION_STEP_V(v)     BM_SPDIF_VERSION_STEP
+
+#endif /* __HEADERGEN_STMP3700_SPDIF_H__*/
diff --git a/firmware/target/arm/imx233/regs/stmp3700/ssp.h b/firmware/target/arm/imx233/regs/stmp3700/ssp.h
new file mode 100644
index 0000000000..c660dfa089
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3700/ssp.h
@@ -0,0 +1,849 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * stmp3700 version: 2.4.0
+ * stmp3700 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_STMP3700_SSP_H__
+#define __HEADERGEN_STMP3700_SSP_H__
+
+#define HW_SSP_CTRL0(_n1)                   HW(SSP_CTRL0(_n1))
+#define HWA_SSP_CTRL0(_n1)                  (((_n1) == 1 ? 0x80010000 : 0x80034000) + 0x0)
+#define HWT_SSP_CTRL0(_n1)                  HWIO_32_RW
+#define HWN_SSP_CTRL0(_n1)                  SSP_CTRL0
+#define HWI_SSP_CTRL0(_n1)                  (_n1)
+#define HW_SSP_CTRL0_SET(_n1)               HW(SSP_CTRL0_SET(_n1))
+#define HWA_SSP_CTRL0_SET(_n1)              (HWA_SSP_CTRL0(_n1) + 0x4)
+#define HWT_SSP_CTRL0_SET(_n1)              HWIO_32_WO
+#define HWN_SSP_CTRL0_SET(_n1)              SSP_CTRL0
+#define HWI_SSP_CTRL0_SET(_n1)              (_n1)
+#define HW_SSP_CTRL0_CLR(_n1)               HW(SSP_CTRL0_CLR(_n1))
+#define HWA_SSP_CTRL0_CLR(_n1)              (HWA_SSP_CTRL0(_n1) + 0x8)
+#define HWT_SSP_CTRL0_CLR(_n1)              HWIO_32_WO
+#define HWN_SSP_CTRL0_CLR(_n1)              SSP_CTRL0
+#define HWI_SSP_CTRL0_CLR(_n1)              (_n1)
+#define HW_SSP_CTRL0_TOG(_n1)               HW(SSP_CTRL0_TOG(_n1))
+#define HWA_SSP_CTRL0_TOG(_n1)              (HWA_SSP_CTRL0(_n1) + 0xc)
+#define HWT_SSP_CTRL0_TOG(_n1)              HWIO_32_WO
+#define HWN_SSP_CTRL0_TOG(_n1)              SSP_CTRL0
+#define HWI_SSP_CTRL0_TOG(_n1)              (_n1)
+#define BP_SSP_CTRL0_SFTRST                 31
+#define BM_SSP_CTRL0_SFTRST                 0x80000000
+#define BF_SSP_CTRL0_SFTRST(v)              (((v) & 0x1) << 31)
+#define BFM_SSP_CTRL0_SFTRST(v)             BM_SSP_CTRL0_SFTRST
+#define BF_SSP_CTRL0_SFTRST_V(e)            BF_SSP_CTRL0_SFTRST(BV_SSP_CTRL0_SFTRST__##e)
+#define BFM_SSP_CTRL0_SFTRST_V(v)           BM_SSP_CTRL0_SFTRST
+#define BP_SSP_CTRL0_CLKGATE                30
+#define BM_SSP_CTRL0_CLKGATE                0x40000000
+#define BF_SSP_CTRL0_CLKGATE(v)             (((v) & 0x1) << 30)
+#define BFM_SSP_CTRL0_CLKGATE(v)            BM_SSP_CTRL0_CLKGATE
+#define BF_SSP_CTRL0_CLKGATE_V(e)           BF_SSP_CTRL0_CLKGATE(BV_SSP_CTRL0_CLKGATE__##e)
+#define BFM_SSP_CTRL0_CLKGATE_V(v)          BM_SSP_CTRL0_CLKGATE
+#define BP_SSP_CTRL0_RUN                    29
+#define BM_SSP_CTRL0_RUN                    0x20000000
+#define BF_SSP_CTRL0_RUN(v)                 (((v) & 0x1) << 29)
+#define BFM_SSP_CTRL0_RUN(v)                BM_SSP_CTRL0_RUN
+#define BF_SSP_CTRL0_RUN_V(e)               BF_SSP_CTRL0_RUN(BV_SSP_CTRL0_RUN__##e)
+#define BFM_SSP_CTRL0_RUN_V(v)              BM_SSP_CTRL0_RUN
+#define BP_SSP_CTRL0_SDIO_IRQ_CHECK         28
+#define BM_SSP_CTRL0_SDIO_IRQ_CHECK         0x10000000
+#define BF_SSP_CTRL0_SDIO_IRQ_CHECK(v)      (((v) & 0x1) << 28)
+#define BFM_SSP_CTRL0_SDIO_IRQ_CHECK(v)     BM_SSP_CTRL0_SDIO_IRQ_CHECK
+#define BF_SSP_CTRL0_SDIO_IRQ_CHECK_V(e)    BF_SSP_CTRL0_SDIO_IRQ_CHECK(BV_SSP_CTRL0_SDIO_IRQ_CHECK__##e)
+#define BFM_SSP_CTRL0_SDIO_IRQ_CHECK_V(v)   BM_SSP_CTRL0_SDIO_IRQ_CHECK
+#define BP_SSP_CTRL0_LOCK_CS                27
+#define BM_SSP_CTRL0_LOCK_CS                0x8000000
+#define BF_SSP_CTRL0_LOCK_CS(v)             (((v) & 0x1) << 27)
+#define BFM_SSP_CTRL0_LOCK_CS(v)            BM_SSP_CTRL0_LOCK_CS
+#define BF_SSP_CTRL0_LOCK_CS_V(e)           BF_SSP_CTRL0_LOCK_CS(BV_SSP_CTRL0_LOCK_CS__##e)
+#define BFM_SSP_CTRL0_LOCK_CS_V(v)          BM_SSP_CTRL0_LOCK_CS
+#define BP_SSP_CTRL0_IGNORE_CRC             26
+#define BM_SSP_CTRL0_IGNORE_CRC             0x4000000
+#define BF_SSP_CTRL0_IGNORE_CRC(v)          (((v) & 0x1) << 26)
+#define BFM_SSP_CTRL0_IGNORE_CRC(v)         BM_SSP_CTRL0_IGNORE_CRC
+#define BF_SSP_CTRL0_IGNORE_CRC_V(e)        BF_SSP_CTRL0_IGNORE_CRC(BV_SSP_CTRL0_IGNORE_CRC__##e)
+#define BFM_SSP_CTRL0_IGNORE_CRC_V(v)       BM_SSP_CTRL0_IGNORE_CRC
+#define BP_SSP_CTRL0_READ                   25
+#define BM_SSP_CTRL0_READ                   0x2000000
+#define BF_SSP_CTRL0_READ(v)                (((v) & 0x1) << 25)
+#define BFM_SSP_CTRL0_READ(v)               BM_SSP_CTRL0_READ
+#define BF_SSP_CTRL0_READ_V(e)              BF_SSP_CTRL0_READ(BV_SSP_CTRL0_READ__##e)
+#define BFM_SSP_CTRL0_READ_V(v)             BM_SSP_CTRL0_READ
+#define BP_SSP_CTRL0_DATA_XFER              24
+#define BM_SSP_CTRL0_DATA_XFER              0x1000000
+#define BF_SSP_CTRL0_DATA_XFER(v)           (((v) & 0x1) << 24)
+#define BFM_SSP_CTRL0_DATA_XFER(v)          BM_SSP_CTRL0_DATA_XFER
+#define BF_SSP_CTRL0_DATA_XFER_V(e)         BF_SSP_CTRL0_DATA_XFER(BV_SSP_CTRL0_DATA_XFER__##e)
+#define BFM_SSP_CTRL0_DATA_XFER_V(v)        BM_SSP_CTRL0_DATA_XFER
+#define BP_SSP_CTRL0_BUS_WIDTH              22
+#define BM_SSP_CTRL0_BUS_WIDTH              0xc00000
+#define BV_SSP_CTRL0_BUS_WIDTH__ONE_BIT     0x0
+#define BV_SSP_CTRL0_BUS_WIDTH__FOUR_BIT    0x1
+#define BV_SSP_CTRL0_BUS_WIDTH__EIGHT_BIT   0x2
+#define BF_SSP_CTRL0_BUS_WIDTH(v)           (((v) & 0x3) << 22)
+#define BFM_SSP_CTRL0_BUS_WIDTH(v)          BM_SSP_CTRL0_BUS_WIDTH
+#define BF_SSP_CTRL0_BUS_WIDTH_V(e)         BF_SSP_CTRL0_BUS_WIDTH(BV_SSP_CTRL0_BUS_WIDTH__##e)
+#define BFM_SSP_CTRL0_BUS_WIDTH_V(v)        BM_SSP_CTRL0_BUS_WIDTH
+#define BP_SSP_CTRL0_WAIT_FOR_IRQ           21
+#define BM_SSP_CTRL0_WAIT_FOR_IRQ           0x200000
+#define BF_SSP_CTRL0_WAIT_FOR_IRQ(v)        (((v) & 0x1) << 21)
+#define BFM_SSP_CTRL0_WAIT_FOR_IRQ(v)       BM_SSP_CTRL0_WAIT_FOR_IRQ
+#define BF_SSP_CTRL0_WAIT_FOR_IRQ_V(e)      BF_SSP_CTRL0_WAIT_FOR_IRQ(BV_SSP_CTRL0_WAIT_FOR_IRQ__##e)
+#define BFM_SSP_CTRL0_WAIT_FOR_IRQ_V(v)     BM_SSP_CTRL0_WAIT_FOR_IRQ
+#define BP_SSP_CTRL0_WAIT_FOR_CMD           20
+#define BM_SSP_CTRL0_WAIT_FOR_CMD           0x100000
+#define BF_SSP_CTRL0_WAIT_FOR_CMD(v)        (((v) & 0x1) << 20)
+#define BFM_SSP_CTRL0_WAIT_FOR_CMD(v)       BM_SSP_CTRL0_WAIT_FOR_CMD
+#define BF_SSP_CTRL0_WAIT_FOR_CMD_V(e)      BF_SSP_CTRL0_WAIT_FOR_CMD(BV_SSP_CTRL0_WAIT_FOR_CMD__##e)
+#define BFM_SSP_CTRL0_WAIT_FOR_CMD_V(v)     BM_SSP_CTRL0_WAIT_FOR_CMD
+#define BP_SSP_CTRL0_LONG_RESP              19
+#define BM_SSP_CTRL0_LONG_RESP              0x80000
+#define BF_SSP_CTRL0_LONG_RESP(v)           (((v) & 0x1) << 19)
+#define BFM_SSP_CTRL0_LONG_RESP(v)          BM_SSP_CTRL0_LONG_RESP
+#define BF_SSP_CTRL0_LONG_RESP_V(e)         BF_SSP_CTRL0_LONG_RESP(BV_SSP_CTRL0_LONG_RESP__##e)
+#define BFM_SSP_CTRL0_LONG_RESP_V(v)        BM_SSP_CTRL0_LONG_RESP
+#define BP_SSP_CTRL0_CHECK_RESP             18
+#define BM_SSP_CTRL0_CHECK_RESP             0x40000
+#define BF_SSP_CTRL0_CHECK_RESP(v)          (((v) & 0x1) << 18)
+#define BFM_SSP_CTRL0_CHECK_RESP(v)         BM_SSP_CTRL0_CHECK_RESP
+#define BF_SSP_CTRL0_CHECK_RESP_V(e)        BF_SSP_CTRL0_CHECK_RESP(BV_SSP_CTRL0_CHECK_RESP__##e)
+#define BFM_SSP_CTRL0_CHECK_RESP_V(v)       BM_SSP_CTRL0_CHECK_RESP
+#define BP_SSP_CTRL0_GET_RESP               17
+#define BM_SSP_CTRL0_GET_RESP               0x20000
+#define BF_SSP_CTRL0_GET_RESP(v)            (((v) & 0x1) << 17)
+#define BFM_SSP_CTRL0_GET_RESP(v)           BM_SSP_CTRL0_GET_RESP
+#define BF_SSP_CTRL0_GET_RESP_V(e)          BF_SSP_CTRL0_GET_RESP(BV_SSP_CTRL0_GET_RESP__##e)
+#define BFM_SSP_CTRL0_GET_RESP_V(v)         BM_SSP_CTRL0_GET_RESP
+#define BP_SSP_CTRL0_ENABLE                 16
+#define BM_SSP_CTRL0_ENABLE                 0x10000
+#define BF_SSP_CTRL0_ENABLE(v)              (((v) & 0x1) << 16)
+#define BFM_SSP_CTRL0_ENABLE(v)             BM_SSP_CTRL0_ENABLE
+#define BF_SSP_CTRL0_ENABLE_V(e)            BF_SSP_CTRL0_ENABLE(BV_SSP_CTRL0_ENABLE__##e)
+#define BFM_SSP_CTRL0_ENABLE_V(v)           BM_SSP_CTRL0_ENABLE
+#define BP_SSP_CTRL0_XFER_COUNT             0
+#define BM_SSP_CTRL0_XFER_COUNT             0xffff
+#define BF_SSP_CTRL0_XFER_COUNT(v)          (((v) & 0xffff) << 0)
+#define BFM_SSP_CTRL0_XFER_COUNT(v)         BM_SSP_CTRL0_XFER_COUNT
+#define BF_SSP_CTRL0_XFER_COUNT_V(e)        BF_SSP_CTRL0_XFER_COUNT(BV_SSP_CTRL0_XFER_COUNT__##e)
+#define BFM_SSP_CTRL0_XFER_COUNT_V(v)       BM_SSP_CTRL0_XFER_COUNT
+
+#define HW_SSP_CMD0(_n1)                            HW(SSP_CMD0(_n1))
+#define HWA_SSP_CMD0(_n1)                           (((_n1) == 1 ? 0x80010000 : 0x80034000) + 0x10)
+#define HWT_SSP_CMD0(_n1)                           HWIO_32_RW
+#define HWN_SSP_CMD0(_n1)                           SSP_CMD0
+#define HWI_SSP_CMD0(_n1)                           (_n1)
+#define HW_SSP_CMD0_SET(_n1)                        HW(SSP_CMD0_SET(_n1))
+#define HWA_SSP_CMD0_SET(_n1)                       (HWA_SSP_CMD0(_n1) + 0x4)
+#define HWT_SSP_CMD0_SET(_n1)                       HWIO_32_WO
+#define HWN_SSP_CMD0_SET(_n1)                       SSP_CMD0
+#define HWI_SSP_CMD0_SET(_n1)                       (_n1)
+#define HW_SSP_CMD0_CLR(_n1)                        HW(SSP_CMD0_CLR(_n1))
+#define HWA_SSP_CMD0_CLR(_n1)                       (HWA_SSP_CMD0(_n1) + 0x8)
+#define HWT_SSP_CMD0_CLR(_n1)                       HWIO_32_WO
+#define HWN_SSP_CMD0_CLR(_n1)                       SSP_CMD0
+#define HWI_SSP_CMD0_CLR(_n1)                       (_n1)
+#define HW_SSP_CMD0_TOG(_n1)                        HW(SSP_CMD0_TOG(_n1))
+#define HWA_SSP_CMD0_TOG(_n1)                       (HWA_SSP_CMD0(_n1) + 0xc)
+#define HWT_SSP_CMD0_TOG(_n1)                       HWIO_32_WO
+#define HWN_SSP_CMD0_TOG(_n1)                       SSP_CMD0
+#define HWI_SSP_CMD0_TOG(_n1)                       (_n1)
+#define BP_SSP_CMD0_APPEND_8CYC                     20
+#define BM_SSP_CMD0_APPEND_8CYC                     0x100000
+#define BF_SSP_CMD0_APPEND_8CYC(v)                  (((v) & 0x1) << 20)
+#define BFM_SSP_CMD0_APPEND_8CYC(v)                 BM_SSP_CMD0_APPEND_8CYC
+#define BF_SSP_CMD0_APPEND_8CYC_V(e)                BF_SSP_CMD0_APPEND_8CYC(BV_SSP_CMD0_APPEND_8CYC__##e)
+#define BFM_SSP_CMD0_APPEND_8CYC_V(v)               BM_SSP_CMD0_APPEND_8CYC
+#define BP_SSP_CMD0_BLOCK_SIZE                      16
+#define BM_SSP_CMD0_BLOCK_SIZE                      0xf0000
+#define BF_SSP_CMD0_BLOCK_SIZE(v)                   (((v) & 0xf) << 16)
+#define BFM_SSP_CMD0_BLOCK_SIZE(v)                  BM_SSP_CMD0_BLOCK_SIZE
+#define BF_SSP_CMD0_BLOCK_SIZE_V(e)                 BF_SSP_CMD0_BLOCK_SIZE(BV_SSP_CMD0_BLOCK_SIZE__##e)
+#define BFM_SSP_CMD0_BLOCK_SIZE_V(v)                BM_SSP_CMD0_BLOCK_SIZE
+#define BP_SSP_CMD0_BLOCK_COUNT                     8
+#define BM_SSP_CMD0_BLOCK_COUNT                     0xff00
+#define BF_SSP_CMD0_BLOCK_COUNT(v)                  (((v) & 0xff) << 8)
+#define BFM_SSP_CMD0_BLOCK_COUNT(v)                 BM_SSP_CMD0_BLOCK_COUNT
+#define BF_SSP_CMD0_BLOCK_COUNT_V(e)                BF_SSP_CMD0_BLOCK_COUNT(BV_SSP_CMD0_BLOCK_COUNT__##e)
+#define BFM_SSP_CMD0_BLOCK_COUNT_V(v)               BM_SSP_CMD0_BLOCK_COUNT
+#define BP_SSP_CMD0_CMD                             0
+#define BM_SSP_CMD0_CMD                             0xff
+#define BV_SSP_CMD0_CMD__MMC_GO_IDLE_STATE          0x0
+#define BV_SSP_CMD0_CMD__MMC_SEND_OP_COND           0x1
+#define BV_SSP_CMD0_CMD__MMC_ALL_SEND_CID           0x2
+#define BV_SSP_CMD0_CMD__MMC_SET_RELATIVE_ADDR      0x3
+#define BV_SSP_CMD0_CMD__MMC_SET_DSR                0x4
+#define BV_SSP_CMD0_CMD__MMC_RESERVED_5             0x5
+#define BV_SSP_CMD0_CMD__MMC_SWITCH                 0x6
+#define BV_SSP_CMD0_CMD__MMC_SELECT_DESELECT_CARD   0x7
+#define BV_SSP_CMD0_CMD__MMC_SEND_EXT_CSD           0x8
+#define BV_SSP_CMD0_CMD__MMC_SEND_CSD               0x9
+#define BV_SSP_CMD0_CMD__MMC_SEND_CID               0xa
+#define BV_SSP_CMD0_CMD__MMC_READ_DAT_UNTIL_STOP    0xb
+#define BV_SSP_CMD0_CMD__MMC_STOP_TRANSMISSION      0xc
+#define BV_SSP_CMD0_CMD__MMC_SEND_STATUS            0xd
+#define BV_SSP_CMD0_CMD__MMC_BUSTEST_R              0xe
+#define BV_SSP_CMD0_CMD__MMC_GO_INACTIVE_STATE      0xf
+#define BV_SSP_CMD0_CMD__MMC_SET_BLOCKLEN           0x10
+#define BV_SSP_CMD0_CMD__MMC_READ_SINGLE_BLOCK      0x11
+#define BV_SSP_CMD0_CMD__MMC_READ_MULTIPLE_BLOCK    0x12
+#define BV_SSP_CMD0_CMD__MMC_BUSTEST_W              0x13
+#define BV_SSP_CMD0_CMD__MMC_WRITE_DAT_UNTIL_STOP   0x14
+#define BV_SSP_CMD0_CMD__MMC_SET_BLOCK_COUNT        0x17
+#define BV_SSP_CMD0_CMD__MMC_WRITE_BLOCK            0x18
+#define BV_SSP_CMD0_CMD__MMC_WRITE_MULTIPLE_BLOCK   0x19
+#define BV_SSP_CMD0_CMD__MMC_PROGRAM_CID            0x1a
+#define BV_SSP_CMD0_CMD__MMC_PROGRAM_CSD            0x1b
+#define BV_SSP_CMD0_CMD__MMC_SET_WRITE_PROT         0x1c
+#define BV_SSP_CMD0_CMD__MMC_CLR_WRITE_PROT         0x1d
+#define BV_SSP_CMD0_CMD__MMC_SEND_WRITE_PROT        0x1e
+#define BV_SSP_CMD0_CMD__MMC_ERASE_GROUP_START      0x23
+#define BV_SSP_CMD0_CMD__MMC_ERASE_GROUP_END        0x24
+#define BV_SSP_CMD0_CMD__MMC_ERASE                  0x26
+#define BV_SSP_CMD0_CMD__MMC_FAST_IO                0x27
+#define BV_SSP_CMD0_CMD__MMC_GO_IRQ_STATE           0x28
+#define BV_SSP_CMD0_CMD__MMC_LOCK_UNLOCK            0x2a
+#define BV_SSP_CMD0_CMD__MMC_APP_CMD                0x37
+#define BV_SSP_CMD0_CMD__MMC_GEN_CMD                0x38
+#define BV_SSP_CMD0_CMD__SD_GO_IDLE_STATE           0x0
+#define BV_SSP_CMD0_CMD__SD_ALL_SEND_CID            0x2
+#define BV_SSP_CMD0_CMD__SD_SEND_RELATIVE_ADDR      0x3
+#define BV_SSP_CMD0_CMD__SD_SET_DSR                 0x4
+#define BV_SSP_CMD0_CMD__SD_IO_SEND_OP_COND         0x5
+#define BV_SSP_CMD0_CMD__SD_SELECT_DESELECT_CARD    0x7
+#define BV_SSP_CMD0_CMD__SD_SEND_CSD                0x9
+#define BV_SSP_CMD0_CMD__SD_SEND_CID                0xa
+#define BV_SSP_CMD0_CMD__SD_STOP_TRANSMISSION       0xc
+#define BV_SSP_CMD0_CMD__SD_SEND_STATUS             0xd
+#define BV_SSP_CMD0_CMD__SD_GO_INACTIVE_STATE       0xf
+#define BV_SSP_CMD0_CMD__SD_SET_BLOCKLEN            0x10
+#define BV_SSP_CMD0_CMD__SD_READ_SINGLE_BLOCK       0x11
+#define BV_SSP_CMD0_CMD__SD_READ_MULTIPLE_BLOCK     0x12
+#define BV_SSP_CMD0_CMD__SD_WRITE_BLOCK             0x18
+#define BV_SSP_CMD0_CMD__SD_WRITE_MULTIPLE_BLOCK    0x19
+#define BV_SSP_CMD0_CMD__SD_PROGRAM_CSD             0x1b
+#define BV_SSP_CMD0_CMD__SD_SET_WRITE_PROT          0x1c
+#define BV_SSP_CMD0_CMD__SD_CLR_WRITE_PROT          0x1d
+#define BV_SSP_CMD0_CMD__SD_SEND_WRITE_PROT         0x1e
+#define BV_SSP_CMD0_CMD__SD_ERASE_WR_BLK_START      0x20
+#define BV_SSP_CMD0_CMD__SD_ERASE_WR_BLK_END        0x21
+#define BV_SSP_CMD0_CMD__SD_ERASE_GROUP_START       0x23
+#define BV_SSP_CMD0_CMD__SD_ERASE_GROUP_END         0x24
+#define BV_SSP_CMD0_CMD__SD_ERASE                   0x26
+#define BV_SSP_CMD0_CMD__SD_LOCK_UNLOCK             0x2a
+#define BV_SSP_CMD0_CMD__SD_IO_RW_DIRECT            0x34
+#define BV_SSP_CMD0_CMD__SD_IO_RW_EXTENDED          0x35
+#define BV_SSP_CMD0_CMD__SD_APP_CMD                 0x37
+#define BV_SSP_CMD0_CMD__SD_GEN_CMD                 0x38
+#define BF_SSP_CMD0_CMD(v)                          (((v) & 0xff) << 0)
+#define BFM_SSP_CMD0_CMD(v)                         BM_SSP_CMD0_CMD
+#define BF_SSP_CMD0_CMD_V(e)                        BF_SSP_CMD0_CMD(BV_SSP_CMD0_CMD__##e)
+#define BFM_SSP_CMD0_CMD_V(v)                       BM_SSP_CMD0_CMD
+
+#define HW_SSP_CMD1(_n1)            HW(SSP_CMD1(_n1))
+#define HWA_SSP_CMD1(_n1)           (((_n1) == 1 ? 0x80010000 : 0x80034000) + 0x20)
+#define HWT_SSP_CMD1(_n1)           HWIO_32_RW
+#define HWN_SSP_CMD1(_n1)           SSP_CMD1
+#define HWI_SSP_CMD1(_n1)           (_n1)
+#define BP_SSP_CMD1_CMD_ARG         0
+#define BM_SSP_CMD1_CMD_ARG         0xffffffff
+#define BF_SSP_CMD1_CMD_ARG(v)      (((v) & 0xffffffff) << 0)
+#define BFM_SSP_CMD1_CMD_ARG(v)     BM_SSP_CMD1_CMD_ARG
+#define BF_SSP_CMD1_CMD_ARG_V(e)    BF_SSP_CMD1_CMD_ARG(BV_SSP_CMD1_CMD_ARG__##e)
+#define BFM_SSP_CMD1_CMD_ARG_V(v)   BM_SSP_CMD1_CMD_ARG
+
+#define HW_SSP_COMPREF(_n1)             HW(SSP_COMPREF(_n1))
+#define HWA_SSP_COMPREF(_n1)            (((_n1) == 1 ? 0x80010000 : 0x80034000) + 0x30)
+#define HWT_SSP_COMPREF(_n1)            HWIO_32_RW
+#define HWN_SSP_COMPREF(_n1)            SSP_COMPREF
+#define HWI_SSP_COMPREF(_n1)            (_n1)
+#define BP_SSP_COMPREF_REFERENCE        0
+#define BM_SSP_COMPREF_REFERENCE        0xffffffff
+#define BF_SSP_COMPREF_REFERENCE(v)     (((v) & 0xffffffff) << 0)
+#define BFM_SSP_COMPREF_REFERENCE(v)    BM_SSP_COMPREF_REFERENCE
+#define BF_SSP_COMPREF_REFERENCE_V(e)   BF_SSP_COMPREF_REFERENCE(BV_SSP_COMPREF_REFERENCE__##e)
+#define BFM_SSP_COMPREF_REFERENCE_V(v)  BM_SSP_COMPREF_REFERENCE
+
+#define HW_SSP_COMPMASK(_n1)        HW(SSP_COMPMASK(_n1))
+#define HWA_SSP_COMPMASK(_n1)       (((_n1) == 1 ? 0x80010000 : 0x80034000) + 0x40)
+#define HWT_SSP_COMPMASK(_n1)       HWIO_32_RW
+#define HWN_SSP_COMPMASK(_n1)       SSP_COMPMASK
+#define HWI_SSP_COMPMASK(_n1)       (_n1)
+#define BP_SSP_COMPMASK_MASK        0
+#define BM_SSP_COMPMASK_MASK        0xffffffff
+#define BF_SSP_COMPMASK_MASK(v)     (((v) & 0xffffffff) << 0)
+#define BFM_SSP_COMPMASK_MASK(v)    BM_SSP_COMPMASK_MASK
+#define BF_SSP_COMPMASK_MASK_V(e)   BF_SSP_COMPMASK_MASK(BV_SSP_COMPMASK_MASK__##e)
+#define BFM_SSP_COMPMASK_MASK_V(v)  BM_SSP_COMPMASK_MASK
+
+#define HW_SSP_TIMING(_n1)                  HW(SSP_TIMING(_n1))
+#define HWA_SSP_TIMING(_n1)                 (((_n1) == 1 ? 0x80010000 : 0x80034000) + 0x50)
+#define HWT_SSP_TIMING(_n1)                 HWIO_32_RW
+#define HWN_SSP_TIMING(_n1)                 SSP_TIMING
+#define HWI_SSP_TIMING(_n1)                 (_n1)
+#define BP_SSP_TIMING_TIMEOUT               16
+#define BM_SSP_TIMING_TIMEOUT               0xffff0000
+#define BF_SSP_TIMING_TIMEOUT(v)            (((v) & 0xffff) << 16)
+#define BFM_SSP_TIMING_TIMEOUT(v)           BM_SSP_TIMING_TIMEOUT
+#define BF_SSP_TIMING_TIMEOUT_V(e)          BF_SSP_TIMING_TIMEOUT(BV_SSP_TIMING_TIMEOUT__##e)
+#define BFM_SSP_TIMING_TIMEOUT_V(v)         BM_SSP_TIMING_TIMEOUT
+#define BP_SSP_TIMING_CLOCK_DIVIDE          8
+#define BM_SSP_TIMING_CLOCK_DIVIDE          0xff00
+#define BF_SSP_TIMING_CLOCK_DIVIDE(v)       (((v) & 0xff) << 8)
+#define BFM_SSP_TIMING_CLOCK_DIVIDE(v)      BM_SSP_TIMING_CLOCK_DIVIDE
+#define BF_SSP_TIMING_CLOCK_DIVIDE_V(e)     BF_SSP_TIMING_CLOCK_DIVIDE(BV_SSP_TIMING_CLOCK_DIVIDE__##e)
+#define BFM_SSP_TIMING_CLOCK_DIVIDE_V(v)    BM_SSP_TIMING_CLOCK_DIVIDE
+#define BP_SSP_TIMING_CLOCK_RATE            0
+#define BM_SSP_TIMING_CLOCK_RATE            0xff
+#define BF_SSP_TIMING_CLOCK_RATE(v)         (((v) & 0xff) << 0)
+#define BFM_SSP_TIMING_CLOCK_RATE(v)        BM_SSP_TIMING_CLOCK_RATE
+#define BF_SSP_TIMING_CLOCK_RATE_V(e)       BF_SSP_TIMING_CLOCK_RATE(BV_SSP_TIMING_CLOCK_RATE__##e)
+#define BFM_SSP_TIMING_CLOCK_RATE_V(v)      BM_SSP_TIMING_CLOCK_RATE
+
+#define HW_SSP_CTRL1(_n1)                       HW(SSP_CTRL1(_n1))
+#define HWA_SSP_CTRL1(_n1)                      (((_n1) == 1 ? 0x80010000 : 0x80034000) + 0x60)
+#define HWT_SSP_CTRL1(_n1)                      HWIO_32_RW
+#define HWN_SSP_CTRL1(_n1)                      SSP_CTRL1
+#define HWI_SSP_CTRL1(_n1)                      (_n1)
+#define HW_SSP_CTRL1_SET(_n1)                   HW(SSP_CTRL1_SET(_n1))
+#define HWA_SSP_CTRL1_SET(_n1)                  (HWA_SSP_CTRL1(_n1) + 0x4)
+#define HWT_SSP_CTRL1_SET(_n1)                  HWIO_32_WO
+#define HWN_SSP_CTRL1_SET(_n1)                  SSP_CTRL1
+#define HWI_SSP_CTRL1_SET(_n1)                  (_n1)
+#define HW_SSP_CTRL1_CLR(_n1)                   HW(SSP_CTRL1_CLR(_n1))
+#define HWA_SSP_CTRL1_CLR(_n1)                  (HWA_SSP_CTRL1(_n1) + 0x8)
+#define HWT_SSP_CTRL1_CLR(_n1)                  HWIO_32_WO
+#define HWN_SSP_CTRL1_CLR(_n1)                  SSP_CTRL1
+#define HWI_SSP_CTRL1_CLR(_n1)                  (_n1)
+#define HW_SSP_CTRL1_TOG(_n1)                   HW(SSP_CTRL1_TOG(_n1))
+#define HWA_SSP_CTRL1_TOG(_n1)                  (HWA_SSP_CTRL1(_n1) + 0xc)
+#define HWT_SSP_CTRL1_TOG(_n1)                  HWIO_32_WO
+#define HWN_SSP_CTRL1_TOG(_n1)                  SSP_CTRL1
+#define HWI_SSP_CTRL1_TOG(_n1)                  (_n1)
+#define BP_SSP_CTRL1_SDIO_IRQ                   31
+#define BM_SSP_CTRL1_SDIO_IRQ                   0x80000000
+#define BF_SSP_CTRL1_SDIO_IRQ(v)                (((v) & 0x1) << 31)
+#define BFM_SSP_CTRL1_SDIO_IRQ(v)               BM_SSP_CTRL1_SDIO_IRQ
+#define BF_SSP_CTRL1_SDIO_IRQ_V(e)              BF_SSP_CTRL1_SDIO_IRQ(BV_SSP_CTRL1_SDIO_IRQ__##e)
+#define BFM_SSP_CTRL1_SDIO_IRQ_V(v)             BM_SSP_CTRL1_SDIO_IRQ
+#define BP_SSP_CTRL1_SDIO_IRQ_EN                30
+#define BM_SSP_CTRL1_SDIO_IRQ_EN                0x40000000
+#define BF_SSP_CTRL1_SDIO_IRQ_EN(v)             (((v) & 0x1) << 30)
+#define BFM_SSP_CTRL1_SDIO_IRQ_EN(v)            BM_SSP_CTRL1_SDIO_IRQ_EN
+#define BF_SSP_CTRL1_SDIO_IRQ_EN_V(e)           BF_SSP_CTRL1_SDIO_IRQ_EN(BV_SSP_CTRL1_SDIO_IRQ_EN__##e)
+#define BFM_SSP_CTRL1_SDIO_IRQ_EN_V(v)          BM_SSP_CTRL1_SDIO_IRQ_EN
+#define BP_SSP_CTRL1_RESP_ERR_IRQ               29
+#define BM_SSP_CTRL1_RESP_ERR_IRQ               0x20000000
+#define BF_SSP_CTRL1_RESP_ERR_IRQ(v)            (((v) & 0x1) << 29)
+#define BFM_SSP_CTRL1_RESP_ERR_IRQ(v)           BM_SSP_CTRL1_RESP_ERR_IRQ
+#define BF_SSP_CTRL1_RESP_ERR_IRQ_V(e)          BF_SSP_CTRL1_RESP_ERR_IRQ(BV_SSP_CTRL1_RESP_ERR_IRQ__##e)
+#define BFM_SSP_CTRL1_RESP_ERR_IRQ_V(v)         BM_SSP_CTRL1_RESP_ERR_IRQ
+#define BP_SSP_CTRL1_RESP_ERR_IRQ_EN            28
+#define BM_SSP_CTRL1_RESP_ERR_IRQ_EN            0x10000000
+#define BF_SSP_CTRL1_RESP_ERR_IRQ_EN(v)         (((v) & 0x1) << 28)
+#define BFM_SSP_CTRL1_RESP_ERR_IRQ_EN(v)        BM_SSP_CTRL1_RESP_ERR_IRQ_EN
+#define BF_SSP_CTRL1_RESP_ERR_IRQ_EN_V(e)       BF_SSP_CTRL1_RESP_ERR_IRQ_EN(BV_SSP_CTRL1_RESP_ERR_IRQ_EN__##e)
+#define BFM_SSP_CTRL1_RESP_ERR_IRQ_EN_V(v)      BM_SSP_CTRL1_RESP_ERR_IRQ_EN
+#define BP_SSP_CTRL1_RESP_TIMEOUT_IRQ           27
+#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ           0x8000000
+#define BF_SSP_CTRL1_RESP_TIMEOUT_IRQ(v)        (((v) & 0x1) << 27)
+#define BFM_SSP_CTRL1_RESP_TIMEOUT_IRQ(v)       BM_SSP_CTRL1_RESP_TIMEOUT_IRQ
+#define BF_SSP_CTRL1_RESP_TIMEOUT_IRQ_V(e)      BF_SSP_CTRL1_RESP_TIMEOUT_IRQ(BV_SSP_CTRL1_RESP_TIMEOUT_IRQ__##e)
+#define BFM_SSP_CTRL1_RESP_TIMEOUT_IRQ_V(v)     BM_SSP_CTRL1_RESP_TIMEOUT_IRQ
+#define BP_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN        26
+#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN        0x4000000
+#define BF_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN(v)     (((v) & 0x1) << 26)
+#define BFM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN(v)    BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN
+#define BF_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN_V(e)   BF_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN(BV_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN__##e)
+#define BFM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN_V(v)  BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN
+#define BP_SSP_CTRL1_DATA_TIMEOUT_IRQ           25
+#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ           0x2000000
+#define BF_SSP_CTRL1_DATA_TIMEOUT_IRQ(v)        (((v) & 0x1) << 25)
+#define BFM_SSP_CTRL1_DATA_TIMEOUT_IRQ(v)       BM_SSP_CTRL1_DATA_TIMEOUT_IRQ
+#define BF_SSP_CTRL1_DATA_TIMEOUT_IRQ_V(e)      BF_SSP_CTRL1_DATA_TIMEOUT_IRQ(BV_SSP_CTRL1_DATA_TIMEOUT_IRQ__##e)
+#define BFM_SSP_CTRL1_DATA_TIMEOUT_IRQ_V(v)     BM_SSP_CTRL1_DATA_TIMEOUT_IRQ
+#define BP_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN        24
+#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN        0x1000000
+#define BF_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN(v)     (((v) & 0x1) << 24)
+#define BFM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN(v)    BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN
+#define BF_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN_V(e)   BF_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN(BV_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN__##e)
+#define BFM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN_V(v)  BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN
+#define BP_SSP_CTRL1_DATA_CRC_IRQ               23
+#define BM_SSP_CTRL1_DATA_CRC_IRQ               0x800000
+#define BF_SSP_CTRL1_DATA_CRC_IRQ(v)            (((v) & 0x1) << 23)
+#define BFM_SSP_CTRL1_DATA_CRC_IRQ(v)           BM_SSP_CTRL1_DATA_CRC_IRQ
+#define BF_SSP_CTRL1_DATA_CRC_IRQ_V(e)          BF_SSP_CTRL1_DATA_CRC_IRQ(BV_SSP_CTRL1_DATA_CRC_IRQ__##e)
+#define BFM_SSP_CTRL1_DATA_CRC_IRQ_V(v)         BM_SSP_CTRL1_DATA_CRC_IRQ
+#define BP_SSP_CTRL1_DATA_CRC_IRQ_EN            22
+#define BM_SSP_CTRL1_DATA_CRC_IRQ_EN            0x400000
+#define BF_SSP_CTRL1_DATA_CRC_IRQ_EN(v)         (((v) & 0x1) << 22)
+#define BFM_SSP_CTRL1_DATA_CRC_IRQ_EN(v)        BM_SSP_CTRL1_DATA_CRC_IRQ_EN
+#define BF_SSP_CTRL1_DATA_CRC_IRQ_EN_V(e)       BF_SSP_CTRL1_DATA_CRC_IRQ_EN(BV_SSP_CTRL1_DATA_CRC_IRQ_EN__##e)
+#define BFM_SSP_CTRL1_DATA_CRC_IRQ_EN_V(v)      BM_SSP_CTRL1_DATA_CRC_IRQ_EN
+#define BP_SSP_CTRL1_FIFO_UNDERRUN_IRQ          21
+#define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ          0x200000
+#define BF_SSP_CTRL1_FIFO_UNDERRUN_IRQ(v)       (((v) & 0x1) << 21)
+#define BFM_SSP_CTRL1_FIFO_UNDERRUN_IRQ(v)      BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ
+#define BF_SSP_CTRL1_FIFO_UNDERRUN_IRQ_V(e)     BF_SSP_CTRL1_FIFO_UNDERRUN_IRQ(BV_SSP_CTRL1_FIFO_UNDERRUN_IRQ__##e)
+#define BFM_SSP_CTRL1_FIFO_UNDERRUN_IRQ_V(v)    BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ
+#define BP_SSP_CTRL1_FIFO_UNDERRUN_EN           20
+#define BM_SSP_CTRL1_FIFO_UNDERRUN_EN           0x100000
+#define BF_SSP_CTRL1_FIFO_UNDERRUN_EN(v)        (((v) & 0x1) << 20)
+#define BFM_SSP_CTRL1_FIFO_UNDERRUN_EN(v)       BM_SSP_CTRL1_FIFO_UNDERRUN_EN
+#define BF_SSP_CTRL1_FIFO_UNDERRUN_EN_V(e)      BF_SSP_CTRL1_FIFO_UNDERRUN_EN(BV_SSP_CTRL1_FIFO_UNDERRUN_EN__##e)
+#define BFM_SSP_CTRL1_FIFO_UNDERRUN_EN_V(v)     BM_SSP_CTRL1_FIFO_UNDERRUN_EN
+#define BP_SSP_CTRL1_CEATA_CCS_ERR_IRQ          19
+#define BM_SSP_CTRL1_CEATA_CCS_ERR_IRQ          0x80000
+#define BF_SSP_CTRL1_CEATA_CCS_ERR_IRQ(v)       (((v) & 0x1) << 19)
+#define BFM_SSP_CTRL1_CEATA_CCS_ERR_IRQ(v)      BM_SSP_CTRL1_CEATA_CCS_ERR_IRQ
+#define BF_SSP_CTRL1_CEATA_CCS_ERR_IRQ_V(e)     BF_SSP_CTRL1_CEATA_CCS_ERR_IRQ(BV_SSP_CTRL1_CEATA_CCS_ERR_IRQ__##e)
+#define BFM_SSP_CTRL1_CEATA_CCS_ERR_IRQ_V(v)    BM_SSP_CTRL1_CEATA_CCS_ERR_IRQ
+#define BP_SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN       18
+#define BM_SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN       0x40000
+#define BF_SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN(v)    (((v) & 0x1) << 18)
+#define BFM_SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN(v)   BM_SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN
+#define BF_SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN_V(e)  BF_SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN(BV_SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN__##e)
+#define BFM_SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN_V(v) BM_SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN
+#define BP_SSP_CTRL1_RECV_TIMEOUT_IRQ           17
+#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ           0x20000
+#define BF_SSP_CTRL1_RECV_TIMEOUT_IRQ(v)        (((v) & 0x1) << 17)
+#define BFM_SSP_CTRL1_RECV_TIMEOUT_IRQ(v)       BM_SSP_CTRL1_RECV_TIMEOUT_IRQ
+#define BF_SSP_CTRL1_RECV_TIMEOUT_IRQ_V(e)      BF_SSP_CTRL1_RECV_TIMEOUT_IRQ(BV_SSP_CTRL1_RECV_TIMEOUT_IRQ__##e)
+#define BFM_SSP_CTRL1_RECV_TIMEOUT_IRQ_V(v)     BM_SSP_CTRL1_RECV_TIMEOUT_IRQ
+#define BP_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN        16
+#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN        0x10000
+#define BF_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN(v)     (((v) & 0x1) << 16)
+#define BFM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN(v)    BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN
+#define BF_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN_V(e)   BF_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN(BV_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN__##e)
+#define BFM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN_V(v)  BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN
+#define BP_SSP_CTRL1_FIFO_OVERRUN_IRQ           15
+#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ           0x8000
+#define BF_SSP_CTRL1_FIFO_OVERRUN_IRQ(v)        (((v) & 0x1) << 15)
+#define BFM_SSP_CTRL1_FIFO_OVERRUN_IRQ(v)       BM_SSP_CTRL1_FIFO_OVERRUN_IRQ
+#define BF_SSP_CTRL1_FIFO_OVERRUN_IRQ_V(e)      BF_SSP_CTRL1_FIFO_OVERRUN_IRQ(BV_SSP_CTRL1_FIFO_OVERRUN_IRQ__##e)
+#define BFM_SSP_CTRL1_FIFO_OVERRUN_IRQ_V(v)     BM_SSP_CTRL1_FIFO_OVERRUN_IRQ
+#define BP_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN        14
+#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN        0x4000
+#define BF_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN(v)     (((v) & 0x1) << 14)
+#define BFM_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN(v)    BM_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN
+#define BF_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN_V(e)   BF_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN(BV_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN__##e)
+#define BFM_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN_V(v)  BM_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN
+#define BP_SSP_CTRL1_DMA_ENABLE                 13
+#define BM_SSP_CTRL1_DMA_ENABLE                 0x2000
+#define BF_SSP_CTRL1_DMA_ENABLE(v)              (((v) & 0x1) << 13)
+#define BFM_SSP_CTRL1_DMA_ENABLE(v)             BM_SSP_CTRL1_DMA_ENABLE
+#define BF_SSP_CTRL1_DMA_ENABLE_V(e)            BF_SSP_CTRL1_DMA_ENABLE(BV_SSP_CTRL1_DMA_ENABLE__##e)
+#define BFM_SSP_CTRL1_DMA_ENABLE_V(v)           BM_SSP_CTRL1_DMA_ENABLE
+#define BP_SSP_CTRL1_CEATA_CCS_ERR_EN           12
+#define BM_SSP_CTRL1_CEATA_CCS_ERR_EN           0x1000
+#define BF_SSP_CTRL1_CEATA_CCS_ERR_EN(v)        (((v) & 0x1) << 12)
+#define BFM_SSP_CTRL1_CEATA_CCS_ERR_EN(v)       BM_SSP_CTRL1_CEATA_CCS_ERR_EN
+#define BF_SSP_CTRL1_CEATA_CCS_ERR_EN_V(e)      BF_SSP_CTRL1_CEATA_CCS_ERR_EN(BV_SSP_CTRL1_CEATA_CCS_ERR_EN__##e)
+#define BFM_SSP_CTRL1_CEATA_CCS_ERR_EN_V(v)     BM_SSP_CTRL1_CEATA_CCS_ERR_EN
+#define BP_SSP_CTRL1_SLAVE_OUT_DISABLE          11
+#define BM_SSP_CTRL1_SLAVE_OUT_DISABLE          0x800
+#define BF_SSP_CTRL1_SLAVE_OUT_DISABLE(v)       (((v) & 0x1) << 11)
+#define BFM_SSP_CTRL1_SLAVE_OUT_DISABLE(v)      BM_SSP_CTRL1_SLAVE_OUT_DISABLE
+#define BF_SSP_CTRL1_SLAVE_OUT_DISABLE_V(e)     BF_SSP_CTRL1_SLAVE_OUT_DISABLE(BV_SSP_CTRL1_SLAVE_OUT_DISABLE__##e)
+#define BFM_SSP_CTRL1_SLAVE_OUT_DISABLE_V(v)    BM_SSP_CTRL1_SLAVE_OUT_DISABLE
+#define BP_SSP_CTRL1_PHASE                      10
+#define BM_SSP_CTRL1_PHASE                      0x400
+#define BF_SSP_CTRL1_PHASE(v)                   (((v) & 0x1) << 10)
+#define BFM_SSP_CTRL1_PHASE(v)                  BM_SSP_CTRL1_PHASE
+#define BF_SSP_CTRL1_PHASE_V(e)                 BF_SSP_CTRL1_PHASE(BV_SSP_CTRL1_PHASE__##e)
+#define BFM_SSP_CTRL1_PHASE_V(v)                BM_SSP_CTRL1_PHASE
+#define BP_SSP_CTRL1_POLARITY                   9
+#define BM_SSP_CTRL1_POLARITY                   0x200
+#define BF_SSP_CTRL1_POLARITY(v)                (((v) & 0x1) << 9)
+#define BFM_SSP_CTRL1_POLARITY(v)               BM_SSP_CTRL1_POLARITY
+#define BF_SSP_CTRL1_POLARITY_V(e)              BF_SSP_CTRL1_POLARITY(BV_SSP_CTRL1_POLARITY__##e)
+#define BFM_SSP_CTRL1_POLARITY_V(v)             BM_SSP_CTRL1_POLARITY
+#define BP_SSP_CTRL1_SLAVE_MODE                 8
+#define BM_SSP_CTRL1_SLAVE_MODE                 0x100
+#define BF_SSP_CTRL1_SLAVE_MODE(v)              (((v) & 0x1) << 8)
+#define BFM_SSP_CTRL1_SLAVE_MODE(v)             BM_SSP_CTRL1_SLAVE_MODE
+#define BF_SSP_CTRL1_SLAVE_MODE_V(e)            BF_SSP_CTRL1_SLAVE_MODE(BV_SSP_CTRL1_SLAVE_MODE__##e)
+#define BFM_SSP_CTRL1_SLAVE_MODE_V(v)           BM_SSP_CTRL1_SLAVE_MODE
+#define BP_SSP_CTRL1_WORD_LENGTH                4
+#define BM_SSP_CTRL1_WORD_LENGTH                0xf0
+#define BV_SSP_CTRL1_WORD_LENGTH__RESERVED0     0x0
+#define BV_SSP_CTRL1_WORD_LENGTH__RESERVED1     0x1
+#define BV_SSP_CTRL1_WORD_LENGTH__RESERVED2     0x2
+#define BV_SSP_CTRL1_WORD_LENGTH__FOUR_BITS     0x3
+#define BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS    0x7
+#define BV_SSP_CTRL1_WORD_LENGTH__SIXTEEN_BITS  0xf
+#define BF_SSP_CTRL1_WORD_LENGTH(v)             (((v) & 0xf) << 4)
+#define BFM_SSP_CTRL1_WORD_LENGTH(v)            BM_SSP_CTRL1_WORD_LENGTH
+#define BF_SSP_CTRL1_WORD_LENGTH_V(e)           BF_SSP_CTRL1_WORD_LENGTH(BV_SSP_CTRL1_WORD_LENGTH__##e)
+#define BFM_SSP_CTRL1_WORD_LENGTH_V(v)          BM_SSP_CTRL1_WORD_LENGTH
+#define BP_SSP_CTRL1_SSP_MODE                   0
+#define BM_SSP_CTRL1_SSP_MODE                   0xf
+#define BV_SSP_CTRL1_SSP_MODE__SPI              0x0
+#define BV_SSP_CTRL1_SSP_MODE__SSI              0x1
+#define BV_SSP_CTRL1_SSP_MODE__SD_MMC           0x3
+#define BV_SSP_CTRL1_SSP_MODE__MS               0x4
+#define BV_SSP_CTRL1_SSP_MODE__CE_ATA           0x7
+#define BF_SSP_CTRL1_SSP_MODE(v)                (((v) & 0xf) << 0)
+#define BFM_SSP_CTRL1_SSP_MODE(v)               BM_SSP_CTRL1_SSP_MODE
+#define BF_SSP_CTRL1_SSP_MODE_V(e)              BF_SSP_CTRL1_SSP_MODE(BV_SSP_CTRL1_SSP_MODE__##e)
+#define BFM_SSP_CTRL1_SSP_MODE_V(v)             BM_SSP_CTRL1_SSP_MODE
+
+#define HW_SSP_DATA(_n1)        HW(SSP_DATA(_n1))
+#define HWA_SSP_DATA(_n1)       (((_n1) == 1 ? 0x80010000 : 0x80034000) + 0x70)
+#define HWT_SSP_DATA(_n1)       HWIO_32_RW
+#define HWN_SSP_DATA(_n1)       SSP_DATA
+#define HWI_SSP_DATA(_n1)       (_n1)
+#define BP_SSP_DATA_DATA        0
+#define BM_SSP_DATA_DATA        0xffffffff
+#define BF_SSP_DATA_DATA(v)     (((v) & 0xffffffff) << 0)
+#define BFM_SSP_DATA_DATA(v)    BM_SSP_DATA_DATA
+#define BF_SSP_DATA_DATA_V(e)   BF_SSP_DATA_DATA(BV_SSP_DATA_DATA__##e)
+#define BFM_SSP_DATA_DATA_V(v)  BM_SSP_DATA_DATA
+
+#define HW_SSP_SDRESP0(_n1)         HW(SSP_SDRESP0(_n1))
+#define HWA_SSP_SDRESP0(_n1)        (((_n1) == 1 ? 0x80010000 : 0x80034000) + 0x80)
+#define HWT_SSP_SDRESP0(_n1)        HWIO_32_RW
+#define HWN_SSP_SDRESP0(_n1)        SSP_SDRESP0
+#define HWI_SSP_SDRESP0(_n1)        (_n1)
+#define BP_SSP_SDRESP0_RESP0        0
+#define BM_SSP_SDRESP0_RESP0        0xffffffff
+#define BF_SSP_SDRESP0_RESP0(v)     (((v) & 0xffffffff) << 0)
+#define BFM_SSP_SDRESP0_RESP0(v)    BM_SSP_SDRESP0_RESP0
+#define BF_SSP_SDRESP0_RESP0_V(e)   BF_SSP_SDRESP0_RESP0(BV_SSP_SDRESP0_RESP0__##e)
+#define BFM_SSP_SDRESP0_RESP0_V(v)  BM_SSP_SDRESP0_RESP0
+
+#define HW_SSP_SDRESP1(_n1)         HW(SSP_SDRESP1(_n1))
+#define HWA_SSP_SDRESP1(_n1)        (((_n1) == 1 ? 0x80010000 : 0x80034000) + 0x90)
+#define HWT_SSP_SDRESP1(_n1)        HWIO_32_RW
+#define HWN_SSP_SDRESP1(_n1)        SSP_SDRESP1
+#define HWI_SSP_SDRESP1(_n1)        (_n1)
+#define BP_SSP_SDRESP1_RESP1        0
+#define BM_SSP_SDRESP1_RESP1        0xffffffff
+#define BF_SSP_SDRESP1_RESP1(v)     (((v) & 0xffffffff) << 0)
+#define BFM_SSP_SDRESP1_RESP1(v)    BM_SSP_SDRESP1_RESP1
+#define BF_SSP_SDRESP1_RESP1_V(e)   BF_SSP_SDRESP1_RESP1(BV_SSP_SDRESP1_RESP1__##e)
+#define BFM_SSP_SDRESP1_RESP1_V(v)  BM_SSP_SDRESP1_RESP1
+
+#define HW_SSP_SDRESP2(_n1)         HW(SSP_SDRESP2(_n1))
+#define HWA_SSP_SDRESP2(_n1)        (((_n1) == 1 ? 0x80010000 : 0x80034000) + 0xa0)
+#define HWT_SSP_SDRESP2(_n1)        HWIO_32_RW
+#define HWN_SSP_SDRESP2(_n1)        SSP_SDRESP2
+#define HWI_SSP_SDRESP2(_n1)        (_n1)
+#define BP_SSP_SDRESP2_RESP2        0
+#define BM_SSP_SDRESP2_RESP2        0xffffffff
+#define BF_SSP_SDRESP2_RESP2(v)     (((v) & 0xffffffff) << 0)
+#define BFM_SSP_SDRESP2_RESP2(v)    BM_SSP_SDRESP2_RESP2
+#define BF_SSP_SDRESP2_RESP2_V(e)   BF_SSP_SDRESP2_RESP2(BV_SSP_SDRESP2_RESP2__##e)
+#define BFM_SSP_SDRESP2_RESP2_V(v)  BM_SSP_SDRESP2_RESP2
+
+#define HW_SSP_SDRESP3(_n1)         HW(SSP_SDRESP3(_n1))
+#define HWA_SSP_SDRESP3(_n1)        (((_n1) == 1 ? 0x80010000 : 0x80034000) + 0xb0)
+#define HWT_SSP_SDRESP3(_n1)        HWIO_32_RW
+#define HWN_SSP_SDRESP3(_n1)        SSP_SDRESP3
+#define HWI_SSP_SDRESP3(_n1)        (_n1)
+#define BP_SSP_SDRESP3_RESP3        0
+#define BM_SSP_SDRESP3_RESP3        0xffffffff
+#define BF_SSP_SDRESP3_RESP3(v)     (((v) & 0xffffffff) << 0)
+#define BFM_SSP_SDRESP3_RESP3(v)    BM_SSP_SDRESP3_RESP3
+#define BF_SSP_SDRESP3_RESP3_V(e)   BF_SSP_SDRESP3_RESP3(BV_SSP_SDRESP3_RESP3__##e)
+#define BFM_SSP_SDRESP3_RESP3_V(v)  BM_SSP_SDRESP3_RESP3
+
+#define HW_SSP_STATUS(_n1)                      HW(SSP_STATUS(_n1))
+#define HWA_SSP_STATUS(_n1)                     (((_n1) == 1 ? 0x80010000 : 0x80034000) + 0xc0)
+#define HWT_SSP_STATUS(_n1)                     HWIO_32_RW
+#define HWN_SSP_STATUS(_n1)                     SSP_STATUS
+#define HWI_SSP_STATUS(_n1)                     (_n1)
+#define BP_SSP_STATUS_PRESENT                   31
+#define BM_SSP_STATUS_PRESENT                   0x80000000
+#define BF_SSP_STATUS_PRESENT(v)                (((v) & 0x1) << 31)
+#define BFM_SSP_STATUS_PRESENT(v)               BM_SSP_STATUS_PRESENT
+#define BF_SSP_STATUS_PRESENT_V(e)              BF_SSP_STATUS_PRESENT(BV_SSP_STATUS_PRESENT__##e)
+#define BFM_SSP_STATUS_PRESENT_V(v)             BM_SSP_STATUS_PRESENT
+#define BP_SSP_STATUS_MS_PRESENT                30
+#define BM_SSP_STATUS_MS_PRESENT                0x40000000
+#define BF_SSP_STATUS_MS_PRESENT(v)             (((v) & 0x1) << 30)
+#define BFM_SSP_STATUS_MS_PRESENT(v)            BM_SSP_STATUS_MS_PRESENT
+#define BF_SSP_STATUS_MS_PRESENT_V(e)           BF_SSP_STATUS_MS_PRESENT(BV_SSP_STATUS_MS_PRESENT__##e)
+#define BFM_SSP_STATUS_MS_PRESENT_V(v)          BM_SSP_STATUS_MS_PRESENT
+#define BP_SSP_STATUS_SD_PRESENT                29
+#define BM_SSP_STATUS_SD_PRESENT                0x20000000
+#define BF_SSP_STATUS_SD_PRESENT(v)             (((v) & 0x1) << 29)
+#define BFM_SSP_STATUS_SD_PRESENT(v)            BM_SSP_STATUS_SD_PRESENT
+#define BF_SSP_STATUS_SD_PRESENT_V(e)           BF_SSP_STATUS_SD_PRESENT(BV_SSP_STATUS_SD_PRESENT__##e)
+#define BFM_SSP_STATUS_SD_PRESENT_V(v)          BM_SSP_STATUS_SD_PRESENT
+#define BP_SSP_STATUS_CARD_DETECT               28
+#define BM_SSP_STATUS_CARD_DETECT               0x10000000
+#define BF_SSP_STATUS_CARD_DETECT(v)            (((v) & 0x1) << 28)
+#define BFM_SSP_STATUS_CARD_DETECT(v)           BM_SSP_STATUS_CARD_DETECT
+#define BF_SSP_STATUS_CARD_DETECT_V(e)          BF_SSP_STATUS_CARD_DETECT(BV_SSP_STATUS_CARD_DETECT__##e)
+#define BFM_SSP_STATUS_CARD_DETECT_V(v)         BM_SSP_STATUS_CARD_DETECT
+#define BP_SSP_STATUS_DMASENSE                  21
+#define BM_SSP_STATUS_DMASENSE                  0x200000
+#define BF_SSP_STATUS_DMASENSE(v)               (((v) & 0x1) << 21)
+#define BFM_SSP_STATUS_DMASENSE(v)              BM_SSP_STATUS_DMASENSE
+#define BF_SSP_STATUS_DMASENSE_V(e)             BF_SSP_STATUS_DMASENSE(BV_SSP_STATUS_DMASENSE__##e)
+#define BFM_SSP_STATUS_DMASENSE_V(v)            BM_SSP_STATUS_DMASENSE
+#define BP_SSP_STATUS_DMATERM                   20
+#define BM_SSP_STATUS_DMATERM                   0x100000
+#define BF_SSP_STATUS_DMATERM(v)                (((v) & 0x1) << 20)
+#define BFM_SSP_STATUS_DMATERM(v)               BM_SSP_STATUS_DMATERM
+#define BF_SSP_STATUS_DMATERM_V(e)              BF_SSP_STATUS_DMATERM(BV_SSP_STATUS_DMATERM__##e)
+#define BFM_SSP_STATUS_DMATERM_V(v)             BM_SSP_STATUS_DMATERM
+#define BP_SSP_STATUS_DMAREQ                    19
+#define BM_SSP_STATUS_DMAREQ                    0x80000
+#define BF_SSP_STATUS_DMAREQ(v)                 (((v) & 0x1) << 19)
+#define BFM_SSP_STATUS_DMAREQ(v)                BM_SSP_STATUS_DMAREQ
+#define BF_SSP_STATUS_DMAREQ_V(e)               BF_SSP_STATUS_DMAREQ(BV_SSP_STATUS_DMAREQ__##e)
+#define BFM_SSP_STATUS_DMAREQ_V(v)              BM_SSP_STATUS_DMAREQ
+#define BP_SSP_STATUS_DMAEND                    18
+#define BM_SSP_STATUS_DMAEND                    0x40000
+#define BF_SSP_STATUS_DMAEND(v)                 (((v) & 0x1) << 18)
+#define BFM_SSP_STATUS_DMAEND(v)                BM_SSP_STATUS_DMAEND
+#define BF_SSP_STATUS_DMAEND_V(e)               BF_SSP_STATUS_DMAEND(BV_SSP_STATUS_DMAEND__##e)
+#define BFM_SSP_STATUS_DMAEND_V(v)              BM_SSP_STATUS_DMAEND
+#define BP_SSP_STATUS_SDIO_IRQ                  17
+#define BM_SSP_STATUS_SDIO_IRQ                  0x20000
+#define BF_SSP_STATUS_SDIO_IRQ(v)               (((v) & 0x1) << 17)
+#define BFM_SSP_STATUS_SDIO_IRQ(v)              BM_SSP_STATUS_SDIO_IRQ
+#define BF_SSP_STATUS_SDIO_IRQ_V(e)             BF_SSP_STATUS_SDIO_IRQ(BV_SSP_STATUS_SDIO_IRQ__##e)
+#define BFM_SSP_STATUS_SDIO_IRQ_V(v)            BM_SSP_STATUS_SDIO_IRQ
+#define BP_SSP_STATUS_RESP_CRC_ERR              16
+#define BM_SSP_STATUS_RESP_CRC_ERR              0x10000
+#define BF_SSP_STATUS_RESP_CRC_ERR(v)           (((v) & 0x1) << 16)
+#define BFM_SSP_STATUS_RESP_CRC_ERR(v)          BM_SSP_STATUS_RESP_CRC_ERR
+#define BF_SSP_STATUS_RESP_CRC_ERR_V(e)         BF_SSP_STATUS_RESP_CRC_ERR(BV_SSP_STATUS_RESP_CRC_ERR__##e)
+#define BFM_SSP_STATUS_RESP_CRC_ERR_V(v)        BM_SSP_STATUS_RESP_CRC_ERR
+#define BP_SSP_STATUS_RESP_ERR                  15
+#define BM_SSP_STATUS_RESP_ERR                  0x8000
+#define BF_SSP_STATUS_RESP_ERR(v)               (((v) & 0x1) << 15)
+#define BFM_SSP_STATUS_RESP_ERR(v)              BM_SSP_STATUS_RESP_ERR
+#define BF_SSP_STATUS_RESP_ERR_V(e)             BF_SSP_STATUS_RESP_ERR(BV_SSP_STATUS_RESP_ERR__##e)
+#define BFM_SSP_STATUS_RESP_ERR_V(v)            BM_SSP_STATUS_RESP_ERR
+#define BP_SSP_STATUS_RESP_TIMEOUT              14
+#define BM_SSP_STATUS_RESP_TIMEOUT              0x4000
+#define BF_SSP_STATUS_RESP_TIMEOUT(v)           (((v) & 0x1) << 14)
+#define BFM_SSP_STATUS_RESP_TIMEOUT(v)          BM_SSP_STATUS_RESP_TIMEOUT
+#define BF_SSP_STATUS_RESP_TIMEOUT_V(e)         BF_SSP_STATUS_RESP_TIMEOUT(BV_SSP_STATUS_RESP_TIMEOUT__##e)
+#define BFM_SSP_STATUS_RESP_TIMEOUT_V(v)        BM_SSP_STATUS_RESP_TIMEOUT
+#define BP_SSP_STATUS_DATA_CRC_ERR              13
+#define BM_SSP_STATUS_DATA_CRC_ERR              0x2000
+#define BF_SSP_STATUS_DATA_CRC_ERR(v)           (((v) & 0x1) << 13)
+#define BFM_SSP_STATUS_DATA_CRC_ERR(v)          BM_SSP_STATUS_DATA_CRC_ERR
+#define BF_SSP_STATUS_DATA_CRC_ERR_V(e)         BF_SSP_STATUS_DATA_CRC_ERR(BV_SSP_STATUS_DATA_CRC_ERR__##e)
+#define BFM_SSP_STATUS_DATA_CRC_ERR_V(v)        BM_SSP_STATUS_DATA_CRC_ERR
+#define BP_SSP_STATUS_TIMEOUT                   12
+#define BM_SSP_STATUS_TIMEOUT                   0x1000
+#define BF_SSP_STATUS_TIMEOUT(v)                (((v) & 0x1) << 12)
+#define BFM_SSP_STATUS_TIMEOUT(v)               BM_SSP_STATUS_TIMEOUT
+#define BF_SSP_STATUS_TIMEOUT_V(e)              BF_SSP_STATUS_TIMEOUT(BV_SSP_STATUS_TIMEOUT__##e)
+#define BFM_SSP_STATUS_TIMEOUT_V(v)             BM_SSP_STATUS_TIMEOUT
+#define BP_SSP_STATUS_RECV_TIMEOUT_STAT         11
+#define BM_SSP_STATUS_RECV_TIMEOUT_STAT         0x800
+#define BF_SSP_STATUS_RECV_TIMEOUT_STAT(v)      (((v) & 0x1) << 11)
+#define BFM_SSP_STATUS_RECV_TIMEOUT_STAT(v)     BM_SSP_STATUS_RECV_TIMEOUT_STAT
+#define BF_SSP_STATUS_RECV_TIMEOUT_STAT_V(e)    BF_SSP_STATUS_RECV_TIMEOUT_STAT(BV_SSP_STATUS_RECV_TIMEOUT_STAT__##e)
+#define BFM_SSP_STATUS_RECV_TIMEOUT_STAT_V(v)   BM_SSP_STATUS_RECV_TIMEOUT_STAT
+#define BP_SSP_STATUS_CEATA_CCS_ERR             10
+#define BM_SSP_STATUS_CEATA_CCS_ERR             0x400
+#define BF_SSP_STATUS_CEATA_CCS_ERR(v)          (((v) & 0x1) << 10)
+#define BFM_SSP_STATUS_CEATA_CCS_ERR(v)         BM_SSP_STATUS_CEATA_CCS_ERR
+#define BF_SSP_STATUS_CEATA_CCS_ERR_V(e)        BF_SSP_STATUS_CEATA_CCS_ERR(BV_SSP_STATUS_CEATA_CCS_ERR__##e)
+#define BFM_SSP_STATUS_CEATA_CCS_ERR_V(v)       BM_SSP_STATUS_CEATA_CCS_ERR
+#define BP_SSP_STATUS_FIFO_OVRFLW               9
+#define BM_SSP_STATUS_FIFO_OVRFLW               0x200
+#define BF_SSP_STATUS_FIFO_OVRFLW(v)            (((v) & 0x1) << 9)
+#define BFM_SSP_STATUS_FIFO_OVRFLW(v)           BM_SSP_STATUS_FIFO_OVRFLW
+#define BF_SSP_STATUS_FIFO_OVRFLW_V(e)          BF_SSP_STATUS_FIFO_OVRFLW(BV_SSP_STATUS_FIFO_OVRFLW__##e)
+#define BFM_SSP_STATUS_FIFO_OVRFLW_V(v)         BM_SSP_STATUS_FIFO_OVRFLW
+#define BP_SSP_STATUS_FIFO_FULL                 8
+#define BM_SSP_STATUS_FIFO_FULL                 0x100
+#define BF_SSP_STATUS_FIFO_FULL(v)              (((v) & 0x1) << 8)
+#define BFM_SSP_STATUS_FIFO_FULL(v)             BM_SSP_STATUS_FIFO_FULL
+#define BF_SSP_STATUS_FIFO_FULL_V(e)            BF_SSP_STATUS_FIFO_FULL(BV_SSP_STATUS_FIFO_FULL__##e)
+#define BFM_SSP_STATUS_FIFO_FULL_V(v)           BM_SSP_STATUS_FIFO_FULL
+#define BP_SSP_STATUS_FIFO_EMPTY                5
+#define BM_SSP_STATUS_FIFO_EMPTY                0x20
+#define BF_SSP_STATUS_FIFO_EMPTY(v)             (((v) & 0x1) << 5)
+#define BFM_SSP_STATUS_FIFO_EMPTY(v)            BM_SSP_STATUS_FIFO_EMPTY
+#define BF_SSP_STATUS_FIFO_EMPTY_V(e)           BF_SSP_STATUS_FIFO_EMPTY(BV_SSP_STATUS_FIFO_EMPTY__##e)
+#define BFM_SSP_STATUS_FIFO_EMPTY_V(v)          BM_SSP_STATUS_FIFO_EMPTY
+#define BP_SSP_STATUS_FIFO_UNDRFLW              4
+#define BM_SSP_STATUS_FIFO_UNDRFLW              0x10
+#define BF_SSP_STATUS_FIFO_UNDRFLW(v)           (((v) & 0x1) << 4)
+#define BFM_SSP_STATUS_FIFO_UNDRFLW(v)          BM_SSP_STATUS_FIFO_UNDRFLW
+#define BF_SSP_STATUS_FIFO_UNDRFLW_V(e)         BF_SSP_STATUS_FIFO_UNDRFLW(BV_SSP_STATUS_FIFO_UNDRFLW__##e)
+#define BFM_SSP_STATUS_FIFO_UNDRFLW_V(v)        BM_SSP_STATUS_FIFO_UNDRFLW
+#define BP_SSP_STATUS_CMD_BUSY                  3
+#define BM_SSP_STATUS_CMD_BUSY                  0x8
+#define BF_SSP_STATUS_CMD_BUSY(v)               (((v) & 0x1) << 3)
+#define BFM_SSP_STATUS_CMD_BUSY(v)              BM_SSP_STATUS_CMD_BUSY
+#define BF_SSP_STATUS_CMD_BUSY_V(e)             BF_SSP_STATUS_CMD_BUSY(BV_SSP_STATUS_CMD_BUSY__##e)
+#define BFM_SSP_STATUS_CMD_BUSY_V(v)            BM_SSP_STATUS_CMD_BUSY
+#define BP_SSP_STATUS_DATA_BUSY                 2
+#define BM_SSP_STATUS_DATA_BUSY                 0x4
+#define BF_SSP_STATUS_DATA_BUSY(v)              (((v) & 0x1) << 2)
+#define BFM_SSP_STATUS_DATA_BUSY(v)             BM_SSP_STATUS_DATA_BUSY
+#define BF_SSP_STATUS_DATA_BUSY_V(e)            BF_SSP_STATUS_DATA_BUSY(BV_SSP_STATUS_DATA_BUSY__##e)
+#define BFM_SSP_STATUS_DATA_BUSY_V(v)           BM_SSP_STATUS_DATA_BUSY
+#define BP_SSP_STATUS_BUSY                      0
+#define BM_SSP_STATUS_BUSY                      0x1
+#define BF_SSP_STATUS_BUSY(v)                   (((v) & 0x1) << 0)
+#define BFM_SSP_STATUS_BUSY(v)                  BM_SSP_STATUS_BUSY
+#define BF_SSP_STATUS_BUSY_V(e)                 BF_SSP_STATUS_BUSY(BV_SSP_STATUS_BUSY__##e)
+#define BFM_SSP_STATUS_BUSY_V(v)                BM_SSP_STATUS_BUSY
+
+#define HW_SSP_DEBUG(_n1)                   HW(SSP_DEBUG(_n1))
+#define HWA_SSP_DEBUG(_n1)                  (((_n1) == 1 ? 0x80010000 : 0x80034000) + 0x100)
+#define HWT_SSP_DEBUG(_n1)                  HWIO_32_RW
+#define HWN_SSP_DEBUG(_n1)                  SSP_DEBUG
+#define HWI_SSP_DEBUG(_n1)                  (_n1)
+#define BP_SSP_DEBUG_DATACRC_ERR            28
+#define BM_SSP_DEBUG_DATACRC_ERR            0xf0000000
+#define BF_SSP_DEBUG_DATACRC_ERR(v)         (((v) & 0xf) << 28)
+#define BFM_SSP_DEBUG_DATACRC_ERR(v)        BM_SSP_DEBUG_DATACRC_ERR
+#define BF_SSP_DEBUG_DATACRC_ERR_V(e)       BF_SSP_DEBUG_DATACRC_ERR(BV_SSP_DEBUG_DATACRC_ERR__##e)
+#define BFM_SSP_DEBUG_DATACRC_ERR_V(v)      BM_SSP_DEBUG_DATACRC_ERR
+#define BP_SSP_DEBUG_DATA_STALL             27
+#define BM_SSP_DEBUG_DATA_STALL             0x8000000
+#define BF_SSP_DEBUG_DATA_STALL(v)          (((v) & 0x1) << 27)
+#define BFM_SSP_DEBUG_DATA_STALL(v)         BM_SSP_DEBUG_DATA_STALL
+#define BF_SSP_DEBUG_DATA_STALL_V(e)        BF_SSP_DEBUG_DATA_STALL(BV_SSP_DEBUG_DATA_STALL__##e)
+#define BFM_SSP_DEBUG_DATA_STALL_V(v)       BM_SSP_DEBUG_DATA_STALL
+#define BP_SSP_DEBUG_DAT_SM                 24
+#define BM_SSP_DEBUG_DAT_SM                 0x7000000
+#define BV_SSP_DEBUG_DAT_SM__DSM_IDLE       0x0
+#define BV_SSP_DEBUG_DAT_SM__DSM_WORD       0x2
+#define BV_SSP_DEBUG_DAT_SM__DSM_CRC1       0x3
+#define BV_SSP_DEBUG_DAT_SM__DSM_CRC2       0x4
+#define BV_SSP_DEBUG_DAT_SM__DSM_END        0x5
+#define BF_SSP_DEBUG_DAT_SM(v)              (((v) & 0x7) << 24)
+#define BFM_SSP_DEBUG_DAT_SM(v)             BM_SSP_DEBUG_DAT_SM
+#define BF_SSP_DEBUG_DAT_SM_V(e)            BF_SSP_DEBUG_DAT_SM(BV_SSP_DEBUG_DAT_SM__##e)
+#define BFM_SSP_DEBUG_DAT_SM_V(v)           BM_SSP_DEBUG_DAT_SM
+#define BP_SSP_DEBUG_MSTK_SM                20
+#define BM_SSP_DEBUG_MSTK_SM                0xf00000
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_IDLE     0x0
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_CKON     0x1
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS1      0x2
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_TPC      0x3
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS2      0x4
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_HDSHK    0x5
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS3      0x6
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_RW       0x7
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_CRC1     0x8
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_CRC2     0x9
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS0      0xa
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_END1     0xb
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_END2W    0xc
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_END2R    0xd
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_DONE     0xe
+#define BF_SSP_DEBUG_MSTK_SM(v)             (((v) & 0xf) << 20)
+#define BFM_SSP_DEBUG_MSTK_SM(v)            BM_SSP_DEBUG_MSTK_SM
+#define BF_SSP_DEBUG_MSTK_SM_V(e)           BF_SSP_DEBUG_MSTK_SM(BV_SSP_DEBUG_MSTK_SM__##e)
+#define BFM_SSP_DEBUG_MSTK_SM_V(v)          BM_SSP_DEBUG_MSTK_SM
+#define BP_SSP_DEBUG_CMD_OE                 19
+#define BM_SSP_DEBUG_CMD_OE                 0x80000
+#define BF_SSP_DEBUG_CMD_OE(v)              (((v) & 0x1) << 19)
+#define BFM_SSP_DEBUG_CMD_OE(v)             BM_SSP_DEBUG_CMD_OE
+#define BF_SSP_DEBUG_CMD_OE_V(e)            BF_SSP_DEBUG_CMD_OE(BV_SSP_DEBUG_CMD_OE__##e)
+#define BFM_SSP_DEBUG_CMD_OE_V(v)           BM_SSP_DEBUG_CMD_OE
+#define BP_SSP_DEBUG_DMA_SM                 16
+#define BM_SSP_DEBUG_DMA_SM                 0x70000
+#define BV_SSP_DEBUG_DMA_SM__DMA_IDLE       0x0
+#define BV_SSP_DEBUG_DMA_SM__DMA_DMAREQ     0x1
+#define BV_SSP_DEBUG_DMA_SM__DMA_DMAACK     0x2
+#define BV_SSP_DEBUG_DMA_SM__DMA_STALL      0x3
+#define BV_SSP_DEBUG_DMA_SM__DMA_BUSY       0x4
+#define BV_SSP_DEBUG_DMA_SM__DMA_DONE       0x5
+#define BV_SSP_DEBUG_DMA_SM__DMA_COUNT      0x6
+#define BF_SSP_DEBUG_DMA_SM(v)              (((v) & 0x7) << 16)
+#define BFM_SSP_DEBUG_DMA_SM(v)             BM_SSP_DEBUG_DMA_SM
+#define BF_SSP_DEBUG_DMA_SM_V(e)            BF_SSP_DEBUG_DMA_SM(BV_SSP_DEBUG_DMA_SM__##e)
+#define BFM_SSP_DEBUG_DMA_SM_V(v)           BM_SSP_DEBUG_DMA_SM
+#define BP_SSP_DEBUG_MMC_SM                 12
+#define BM_SSP_DEBUG_MMC_SM                 0xf000
+#define BV_SSP_DEBUG_MMC_SM__MMC_IDLE       0x0
+#define BV_SSP_DEBUG_MMC_SM__MMC_CMD        0x1
+#define BV_SSP_DEBUG_MMC_SM__MMC_TRC        0x2
+#define BV_SSP_DEBUG_MMC_SM__MMC_RESP       0x3
+#define BV_SSP_DEBUG_MMC_SM__MMC_RPRX       0x4
+#define BV_SSP_DEBUG_MMC_SM__MMC_TX         0x5
+#define BV_SSP_DEBUG_MMC_SM__MMC_CTOK       0x6
+#define BV_SSP_DEBUG_MMC_SM__MMC_RX         0x7
+#define BV_SSP_DEBUG_MMC_SM__MMC_CCS        0x8
+#define BV_SSP_DEBUG_MMC_SM__MMC_PUP        0x9
+#define BV_SSP_DEBUG_MMC_SM__MMC_WAIT       0xa
+#define BF_SSP_DEBUG_MMC_SM(v)              (((v) & 0xf) << 12)
+#define BFM_SSP_DEBUG_MMC_SM(v)             BM_SSP_DEBUG_MMC_SM
+#define BF_SSP_DEBUG_MMC_SM_V(e)            BF_SSP_DEBUG_MMC_SM(BV_SSP_DEBUG_MMC_SM__##e)
+#define BFM_SSP_DEBUG_MMC_SM_V(v)           BM_SSP_DEBUG_MMC_SM
+#define BP_SSP_DEBUG_CMD_SM                 10
+#define BM_SSP_DEBUG_CMD_SM                 0xc00
+#define BV_SSP_DEBUG_CMD_SM__CSM_IDLE       0x0
+#define BV_SSP_DEBUG_CMD_SM__CSM_INDEX      0x1
+#define BV_SSP_DEBUG_CMD_SM__CSM_ARG        0x2
+#define BV_SSP_DEBUG_CMD_SM__CSM_CRC        0x3
+#define BF_SSP_DEBUG_CMD_SM(v)              (((v) & 0x3) << 10)
+#define BFM_SSP_DEBUG_CMD_SM(v)             BM_SSP_DEBUG_CMD_SM
+#define BF_SSP_DEBUG_CMD_SM_V(e)            BF_SSP_DEBUG_CMD_SM(BV_SSP_DEBUG_CMD_SM__##e)
+#define BFM_SSP_DEBUG_CMD_SM_V(v)           BM_SSP_DEBUG_CMD_SM
+#define BP_SSP_DEBUG_SSP_CMD                9
+#define BM_SSP_DEBUG_SSP_CMD                0x200
+#define BF_SSP_DEBUG_SSP_CMD(v)             (((v) & 0x1) << 9)
+#define BFM_SSP_DEBUG_SSP_CMD(v)            BM_SSP_DEBUG_SSP_CMD
+#define BF_SSP_DEBUG_SSP_CMD_V(e)           BF_SSP_DEBUG_SSP_CMD(BV_SSP_DEBUG_SSP_CMD__##e)
+#define BFM_SSP_DEBUG_SSP_CMD_V(v)          BM_SSP_DEBUG_SSP_CMD
+#define BP_SSP_DEBUG_SSP_RESP               8
+#define BM_SSP_DEBUG_SSP_RESP               0x100
+#define BF_SSP_DEBUG_SSP_RESP(v)            (((v) & 0x1) << 8)
+#define BFM_SSP_DEBUG_SSP_RESP(v)           BM_SSP_DEBUG_SSP_RESP
+#define BF_SSP_DEBUG_SSP_RESP_V(e)          BF_SSP_DEBUG_SSP_RESP(BV_SSP_DEBUG_SSP_RESP__##e)
+#define BFM_SSP_DEBUG_SSP_RESP_V(v)         BM_SSP_DEBUG_SSP_RESP
+#define BP_SSP_DEBUG_SSP_RXD                0
+#define BM_SSP_DEBUG_SSP_RXD                0xff
+#define BF_SSP_DEBUG_SSP_RXD(v)             (((v) & 0xff) << 0)
+#define BFM_SSP_DEBUG_SSP_RXD(v)            BM_SSP_DEBUG_SSP_RXD
+#define BF_SSP_DEBUG_SSP_RXD_V(e)           BF_SSP_DEBUG_SSP_RXD(BV_SSP_DEBUG_SSP_RXD__##e)
+#define BFM_SSP_DEBUG_SSP_RXD_V(v)          BM_SSP_DEBUG_SSP_RXD
+
+#define HW_SSP_VERSION(_n1)         HW(SSP_VERSION(_n1))
+#define HWA_SSP_VERSION(_n1)        (((_n1) == 1 ? 0x80010000 : 0x80034000) + 0x110)
+#define HWT_SSP_VERSION(_n1)        HWIO_32_RW
+#define HWN_SSP_VERSION(_n1)        SSP_VERSION
+#define HWI_SSP_VERSION(_n1)        (_n1)
+#define BP_SSP_VERSION_MAJOR        24
+#define BM_SSP_VERSION_MAJOR        0xff000000
+#define BF_SSP_VERSION_MAJOR(v)     (((v) & 0xff) << 24)
+#define BFM_SSP_VERSION_MAJOR(v)    BM_SSP_VERSION_MAJOR
+#define BF_SSP_VERSION_MAJOR_V(e)   BF_SSP_VERSION_MAJOR(BV_SSP_VERSION_MAJOR__##e)
+#define BFM_SSP_VERSION_MAJOR_V(v)  BM_SSP_VERSION_MAJOR
+#define BP_SSP_VERSION_MINOR        16
+#define BM_SSP_VERSION_MINOR        0xff0000
+#define BF_SSP_VERSION_MINOR(v)     (((v) & 0xff) << 16)
+#define BFM_SSP_VERSION_MINOR(v)    BM_SSP_VERSION_MINOR
+#define BF_SSP_VERSION_MINOR_V(e)   BF_SSP_VERSION_MINOR(BV_SSP_VERSION_MINOR__##e)
+#define BFM_SSP_VERSION_MINOR_V(v)  BM_SSP_VERSION_MINOR
+#define BP_SSP_VERSION_STEP         0
+#define BM_SSP_VERSION_STEP         0xffff
+#define BF_SSP_VERSION_STEP(v)      (((v) & 0xffff) << 0)
+#define BFM_SSP_VERSION_STEP(v)     BM_SSP_VERSION_STEP
+#define BF_SSP_VERSION_STEP_V(e)    BF_SSP_VERSION_STEP(BV_SSP_VERSION_STEP__##e)
+#define BFM_SSP_VERSION_STEP_V(v)   BM_SSP_VERSION_STEP
+
+#endif /* __HEADERGEN_STMP3700_SSP_H__*/
diff --git a/firmware/target/arm/imx233/regs/stmp3700/timrot.h b/firmware/target/arm/imx233/regs/stmp3700/timrot.h
new file mode 100644
index 0000000000..ac57aa0622
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3700/timrot.h
@@ -0,0 +1,421 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * stmp3700 version: 2.4.0
+ * stmp3700 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_STMP3700_TIMROT_H__
+#define __HEADERGEN_STMP3700_TIMROT_H__
+
+#define HW_TIMROT_ROTCTRL                       HW(TIMROT_ROTCTRL)
+#define HWA_TIMROT_ROTCTRL                      (0x80068000 + 0x0)
+#define HWT_TIMROT_ROTCTRL                      HWIO_32_RW
+#define HWN_TIMROT_ROTCTRL                      TIMROT_ROTCTRL
+#define HWI_TIMROT_ROTCTRL                      
+#define HW_TIMROT_ROTCTRL_SET                   HW(TIMROT_ROTCTRL_SET)
+#define HWA_TIMROT_ROTCTRL_SET                  (HWA_TIMROT_ROTCTRL + 0x4)
+#define HWT_TIMROT_ROTCTRL_SET                  HWIO_32_WO
+#define HWN_TIMROT_ROTCTRL_SET                  TIMROT_ROTCTRL
+#define HWI_TIMROT_ROTCTRL_SET                  
+#define HW_TIMROT_ROTCTRL_CLR                   HW(TIMROT_ROTCTRL_CLR)
+#define HWA_TIMROT_ROTCTRL_CLR                  (HWA_TIMROT_ROTCTRL + 0x8)
+#define HWT_TIMROT_ROTCTRL_CLR                  HWIO_32_WO
+#define HWN_TIMROT_ROTCTRL_CLR                  TIMROT_ROTCTRL
+#define HWI_TIMROT_ROTCTRL_CLR                  
+#define HW_TIMROT_ROTCTRL_TOG                   HW(TIMROT_ROTCTRL_TOG)
+#define HWA_TIMROT_ROTCTRL_TOG                  (HWA_TIMROT_ROTCTRL + 0xc)
+#define HWT_TIMROT_ROTCTRL_TOG                  HWIO_32_WO
+#define HWN_TIMROT_ROTCTRL_TOG                  TIMROT_ROTCTRL
+#define HWI_TIMROT_ROTCTRL_TOG                  
+#define BP_TIMROT_ROTCTRL_SFTRST                31
+#define BM_TIMROT_ROTCTRL_SFTRST                0x80000000
+#define BF_TIMROT_ROTCTRL_SFTRST(v)             (((v) & 0x1) << 31)
+#define BFM_TIMROT_ROTCTRL_SFTRST(v)            BM_TIMROT_ROTCTRL_SFTRST
+#define BF_TIMROT_ROTCTRL_SFTRST_V(e)           BF_TIMROT_ROTCTRL_SFTRST(BV_TIMROT_ROTCTRL_SFTRST__##e)
+#define BFM_TIMROT_ROTCTRL_SFTRST_V(v)          BM_TIMROT_ROTCTRL_SFTRST
+#define BP_TIMROT_ROTCTRL_CLKGATE               30
+#define BM_TIMROT_ROTCTRL_CLKGATE               0x40000000
+#define BF_TIMROT_ROTCTRL_CLKGATE(v)            (((v) & 0x1) << 30)
+#define BFM_TIMROT_ROTCTRL_CLKGATE(v)           BM_TIMROT_ROTCTRL_CLKGATE
+#define BF_TIMROT_ROTCTRL_CLKGATE_V(e)          BF_TIMROT_ROTCTRL_CLKGATE(BV_TIMROT_ROTCTRL_CLKGATE__##e)
+#define BFM_TIMROT_ROTCTRL_CLKGATE_V(v)         BM_TIMROT_ROTCTRL_CLKGATE
+#define BP_TIMROT_ROTCTRL_ROTARY_PRESENT        29
+#define BM_TIMROT_ROTCTRL_ROTARY_PRESENT        0x20000000
+#define BF_TIMROT_ROTCTRL_ROTARY_PRESENT(v)     (((v) & 0x1) << 29)
+#define BFM_TIMROT_ROTCTRL_ROTARY_PRESENT(v)    BM_TIMROT_ROTCTRL_ROTARY_PRESENT
+#define BF_TIMROT_ROTCTRL_ROTARY_PRESENT_V(e)   BF_TIMROT_ROTCTRL_ROTARY_PRESENT(BV_TIMROT_ROTCTRL_ROTARY_PRESENT__##e)
+#define BFM_TIMROT_ROTCTRL_ROTARY_PRESENT_V(v)  BM_TIMROT_ROTCTRL_ROTARY_PRESENT
+#define BP_TIMROT_ROTCTRL_TIM3_PRESENT          28
+#define BM_TIMROT_ROTCTRL_TIM3_PRESENT          0x10000000
+#define BF_TIMROT_ROTCTRL_TIM3_PRESENT(v)       (((v) & 0x1) << 28)
+#define BFM_TIMROT_ROTCTRL_TIM3_PRESENT(v)      BM_TIMROT_ROTCTRL_TIM3_PRESENT
+#define BF_TIMROT_ROTCTRL_TIM3_PRESENT_V(e)     BF_TIMROT_ROTCTRL_TIM3_PRESENT(BV_TIMROT_ROTCTRL_TIM3_PRESENT__##e)
+#define BFM_TIMROT_ROTCTRL_TIM3_PRESENT_V(v)    BM_TIMROT_ROTCTRL_TIM3_PRESENT
+#define BP_TIMROT_ROTCTRL_TIM2_PRESENT          27
+#define BM_TIMROT_ROTCTRL_TIM2_PRESENT          0x8000000
+#define BF_TIMROT_ROTCTRL_TIM2_PRESENT(v)       (((v) & 0x1) << 27)
+#define BFM_TIMROT_ROTCTRL_TIM2_PRESENT(v)      BM_TIMROT_ROTCTRL_TIM2_PRESENT
+#define BF_TIMROT_ROTCTRL_TIM2_PRESENT_V(e)     BF_TIMROT_ROTCTRL_TIM2_PRESENT(BV_TIMROT_ROTCTRL_TIM2_PRESENT__##e)
+#define BFM_TIMROT_ROTCTRL_TIM2_PRESENT_V(v)    BM_TIMROT_ROTCTRL_TIM2_PRESENT
+#define BP_TIMROT_ROTCTRL_TIM1_PRESENT          26
+#define BM_TIMROT_ROTCTRL_TIM1_PRESENT          0x4000000
+#define BF_TIMROT_ROTCTRL_TIM1_PRESENT(v)       (((v) & 0x1) << 26)
+#define BFM_TIMROT_ROTCTRL_TIM1_PRESENT(v)      BM_TIMROT_ROTCTRL_TIM1_PRESENT
+#define BF_TIMROT_ROTCTRL_TIM1_PRESENT_V(e)     BF_TIMROT_ROTCTRL_TIM1_PRESENT(BV_TIMROT_ROTCTRL_TIM1_PRESENT__##e)
+#define BFM_TIMROT_ROTCTRL_TIM1_PRESENT_V(v)    BM_TIMROT_ROTCTRL_TIM1_PRESENT
+#define BP_TIMROT_ROTCTRL_TIM0_PRESENT          25
+#define BM_TIMROT_ROTCTRL_TIM0_PRESENT          0x2000000
+#define BF_TIMROT_ROTCTRL_TIM0_PRESENT(v)       (((v) & 0x1) << 25)
+#define BFM_TIMROT_ROTCTRL_TIM0_PRESENT(v)      BM_TIMROT_ROTCTRL_TIM0_PRESENT
+#define BF_TIMROT_ROTCTRL_TIM0_PRESENT_V(e)     BF_TIMROT_ROTCTRL_TIM0_PRESENT(BV_TIMROT_ROTCTRL_TIM0_PRESENT__##e)
+#define BFM_TIMROT_ROTCTRL_TIM0_PRESENT_V(v)    BM_TIMROT_ROTCTRL_TIM0_PRESENT
+#define BP_TIMROT_ROTCTRL_STATE                 22
+#define BM_TIMROT_ROTCTRL_STATE                 0x1c00000
+#define BF_TIMROT_ROTCTRL_STATE(v)              (((v) & 0x7) << 22)
+#define BFM_TIMROT_ROTCTRL_STATE(v)             BM_TIMROT_ROTCTRL_STATE
+#define BF_TIMROT_ROTCTRL_STATE_V(e)            BF_TIMROT_ROTCTRL_STATE(BV_TIMROT_ROTCTRL_STATE__##e)
+#define BFM_TIMROT_ROTCTRL_STATE_V(v)           BM_TIMROT_ROTCTRL_STATE
+#define BP_TIMROT_ROTCTRL_DIVIDER               16
+#define BM_TIMROT_ROTCTRL_DIVIDER               0x3f0000
+#define BF_TIMROT_ROTCTRL_DIVIDER(v)            (((v) & 0x3f) << 16)
+#define BFM_TIMROT_ROTCTRL_DIVIDER(v)           BM_TIMROT_ROTCTRL_DIVIDER
+#define BF_TIMROT_ROTCTRL_DIVIDER_V(e)          BF_TIMROT_ROTCTRL_DIVIDER(BV_TIMROT_ROTCTRL_DIVIDER__##e)
+#define BFM_TIMROT_ROTCTRL_DIVIDER_V(v)         BM_TIMROT_ROTCTRL_DIVIDER
+#define BP_TIMROT_ROTCTRL_RELATIVE              12
+#define BM_TIMROT_ROTCTRL_RELATIVE              0x1000
+#define BF_TIMROT_ROTCTRL_RELATIVE(v)           (((v) & 0x1) << 12)
+#define BFM_TIMROT_ROTCTRL_RELATIVE(v)          BM_TIMROT_ROTCTRL_RELATIVE
+#define BF_TIMROT_ROTCTRL_RELATIVE_V(e)         BF_TIMROT_ROTCTRL_RELATIVE(BV_TIMROT_ROTCTRL_RELATIVE__##e)
+#define BFM_TIMROT_ROTCTRL_RELATIVE_V(v)        BM_TIMROT_ROTCTRL_RELATIVE
+#define BP_TIMROT_ROTCTRL_OVERSAMPLE            10
+#define BM_TIMROT_ROTCTRL_OVERSAMPLE            0xc00
+#define BV_TIMROT_ROTCTRL_OVERSAMPLE__8X        0x0
+#define BV_TIMROT_ROTCTRL_OVERSAMPLE__4X        0x1
+#define BV_TIMROT_ROTCTRL_OVERSAMPLE__2X        0x2
+#define BV_TIMROT_ROTCTRL_OVERSAMPLE__1X        0x3
+#define BF_TIMROT_ROTCTRL_OVERSAMPLE(v)         (((v) & 0x3) << 10)
+#define BFM_TIMROT_ROTCTRL_OVERSAMPLE(v)        BM_TIMROT_ROTCTRL_OVERSAMPLE
+#define BF_TIMROT_ROTCTRL_OVERSAMPLE_V(e)       BF_TIMROT_ROTCTRL_OVERSAMPLE(BV_TIMROT_ROTCTRL_OVERSAMPLE__##e)
+#define BFM_TIMROT_ROTCTRL_OVERSAMPLE_V(v)      BM_TIMROT_ROTCTRL_OVERSAMPLE
+#define BP_TIMROT_ROTCTRL_POLARITY_B            9
+#define BM_TIMROT_ROTCTRL_POLARITY_B            0x200
+#define BF_TIMROT_ROTCTRL_POLARITY_B(v)         (((v) & 0x1) << 9)
+#define BFM_TIMROT_ROTCTRL_POLARITY_B(v)        BM_TIMROT_ROTCTRL_POLARITY_B
+#define BF_TIMROT_ROTCTRL_POLARITY_B_V(e)       BF_TIMROT_ROTCTRL_POLARITY_B(BV_TIMROT_ROTCTRL_POLARITY_B__##e)
+#define BFM_TIMROT_ROTCTRL_POLARITY_B_V(v)      BM_TIMROT_ROTCTRL_POLARITY_B
+#define BP_TIMROT_ROTCTRL_POLARITY_A            8
+#define BM_TIMROT_ROTCTRL_POLARITY_A            0x100
+#define BF_TIMROT_ROTCTRL_POLARITY_A(v)         (((v) & 0x1) << 8)
+#define BFM_TIMROT_ROTCTRL_POLARITY_A(v)        BM_TIMROT_ROTCTRL_POLARITY_A
+#define BF_TIMROT_ROTCTRL_POLARITY_A_V(e)       BF_TIMROT_ROTCTRL_POLARITY_A(BV_TIMROT_ROTCTRL_POLARITY_A__##e)
+#define BFM_TIMROT_ROTCTRL_POLARITY_A_V(v)      BM_TIMROT_ROTCTRL_POLARITY_A
+#define BP_TIMROT_ROTCTRL_SELECT_B              4
+#define BM_TIMROT_ROTCTRL_SELECT_B              0x70
+#define BV_TIMROT_ROTCTRL_SELECT_B__NEVER_TICK  0x0
+#define BV_TIMROT_ROTCTRL_SELECT_B__PWM0        0x1
+#define BV_TIMROT_ROTCTRL_SELECT_B__PWM1        0x2
+#define BV_TIMROT_ROTCTRL_SELECT_B__PWM2        0x3
+#define BV_TIMROT_ROTCTRL_SELECT_B__PWM3        0x4
+#define BV_TIMROT_ROTCTRL_SELECT_B__PWM4        0x5
+#define BV_TIMROT_ROTCTRL_SELECT_B__ROTARYA     0x6
+#define BV_TIMROT_ROTCTRL_SELECT_B__ROTARYB     0x7
+#define BF_TIMROT_ROTCTRL_SELECT_B(v)           (((v) & 0x7) << 4)
+#define BFM_TIMROT_ROTCTRL_SELECT_B(v)          BM_TIMROT_ROTCTRL_SELECT_B
+#define BF_TIMROT_ROTCTRL_SELECT_B_V(e)         BF_TIMROT_ROTCTRL_SELECT_B(BV_TIMROT_ROTCTRL_SELECT_B__##e)
+#define BFM_TIMROT_ROTCTRL_SELECT_B_V(v)        BM_TIMROT_ROTCTRL_SELECT_B
+#define BP_TIMROT_ROTCTRL_SELECT_A              0
+#define BM_TIMROT_ROTCTRL_SELECT_A              0x7
+#define BV_TIMROT_ROTCTRL_SELECT_A__NEVER_TICK  0x0
+#define BV_TIMROT_ROTCTRL_SELECT_A__PWM0        0x1
+#define BV_TIMROT_ROTCTRL_SELECT_A__PWM1        0x2
+#define BV_TIMROT_ROTCTRL_SELECT_A__PWM2        0x3
+#define BV_TIMROT_ROTCTRL_SELECT_A__PWM3        0x4
+#define BV_TIMROT_ROTCTRL_SELECT_A__PWM4        0x5
+#define BV_TIMROT_ROTCTRL_SELECT_A__ROTARYA     0x6
+#define BV_TIMROT_ROTCTRL_SELECT_A__ROTARYB     0x7
+#define BF_TIMROT_ROTCTRL_SELECT_A(v)           (((v) & 0x7) << 0)
+#define BFM_TIMROT_ROTCTRL_SELECT_A(v)          BM_TIMROT_ROTCTRL_SELECT_A
+#define BF_TIMROT_ROTCTRL_SELECT_A_V(e)         BF_TIMROT_ROTCTRL_SELECT_A(BV_TIMROT_ROTCTRL_SELECT_A__##e)
+#define BFM_TIMROT_ROTCTRL_SELECT_A_V(v)        BM_TIMROT_ROTCTRL_SELECT_A
+
+#define HW_TIMROT_ROTCOUNT              HW(TIMROT_ROTCOUNT)
+#define HWA_TIMROT_ROTCOUNT             (0x80068000 + 0x10)
+#define HWT_TIMROT_ROTCOUNT             HWIO_32_RW
+#define HWN_TIMROT_ROTCOUNT             TIMROT_ROTCOUNT
+#define HWI_TIMROT_ROTCOUNT             
+#define BP_TIMROT_ROTCOUNT_UPDOWN       0
+#define BM_TIMROT_ROTCOUNT_UPDOWN       0xffff
+#define BF_TIMROT_ROTCOUNT_UPDOWN(v)    (((v) & 0xffff) << 0)
+#define BFM_TIMROT_ROTCOUNT_UPDOWN(v)   BM_TIMROT_ROTCOUNT_UPDOWN
+#define BF_TIMROT_ROTCOUNT_UPDOWN_V(e)  BF_TIMROT_ROTCOUNT_UPDOWN(BV_TIMROT_ROTCOUNT_UPDOWN__##e)
+#define BFM_TIMROT_ROTCOUNT_UPDOWN_V(v) BM_TIMROT_ROTCOUNT_UPDOWN
+
+#define HW_TIMROT_TIMCTRLn(_n1)                 HW(TIMROT_TIMCTRLn(_n1))
+#define HWA_TIMROT_TIMCTRLn(_n1)                (0x80068000 + 0x20 + (_n1) * 0x20)
+#define HWT_TIMROT_TIMCTRLn(_n1)                HWIO_32_RW
+#define HWN_TIMROT_TIMCTRLn(_n1)                TIMROT_TIMCTRLn
+#define HWI_TIMROT_TIMCTRLn(_n1)                (_n1)
+#define HW_TIMROT_TIMCTRLn_SET(_n1)             HW(TIMROT_TIMCTRLn_SET(_n1))
+#define HWA_TIMROT_TIMCTRLn_SET(_n1)            (HWA_TIMROT_TIMCTRLn(_n1) + 0x4)
+#define HWT_TIMROT_TIMCTRLn_SET(_n1)            HWIO_32_WO
+#define HWN_TIMROT_TIMCTRLn_SET(_n1)            TIMROT_TIMCTRLn
+#define HWI_TIMROT_TIMCTRLn_SET(_n1)            (_n1)
+#define HW_TIMROT_TIMCTRLn_CLR(_n1)             HW(TIMROT_TIMCTRLn_CLR(_n1))
+#define HWA_TIMROT_TIMCTRLn_CLR(_n1)            (HWA_TIMROT_TIMCTRLn(_n1) + 0x8)
+#define HWT_TIMROT_TIMCTRLn_CLR(_n1)            HWIO_32_WO
+#define HWN_TIMROT_TIMCTRLn_CLR(_n1)            TIMROT_TIMCTRLn
+#define HWI_TIMROT_TIMCTRLn_CLR(_n1)            (_n1)
+#define HW_TIMROT_TIMCTRLn_TOG(_n1)             HW(TIMROT_TIMCTRLn_TOG(_n1))
+#define HWA_TIMROT_TIMCTRLn_TOG(_n1)            (HWA_TIMROT_TIMCTRLn(_n1) + 0xc)
+#define HWT_TIMROT_TIMCTRLn_TOG(_n1)            HWIO_32_WO
+#define HWN_TIMROT_TIMCTRLn_TOG(_n1)            TIMROT_TIMCTRLn
+#define HWI_TIMROT_TIMCTRLn_TOG(_n1)            (_n1)
+#define BP_TIMROT_TIMCTRLn_IRQ                  15
+#define BM_TIMROT_TIMCTRLn_IRQ                  0x8000
+#define BF_TIMROT_TIMCTRLn_IRQ(v)               (((v) & 0x1) << 15)
+#define BFM_TIMROT_TIMCTRLn_IRQ(v)              BM_TIMROT_TIMCTRLn_IRQ
+#define BF_TIMROT_TIMCTRLn_IRQ_V(e)             BF_TIMROT_TIMCTRLn_IRQ(BV_TIMROT_TIMCTRLn_IRQ__##e)
+#define BFM_TIMROT_TIMCTRLn_IRQ_V(v)            BM_TIMROT_TIMCTRLn_IRQ
+#define BP_TIMROT_TIMCTRLn_IRQ_EN               14
+#define BM_TIMROT_TIMCTRLn_IRQ_EN               0x4000
+#define BF_TIMROT_TIMCTRLn_IRQ_EN(v)            (((v) & 0x1) << 14)
+#define BFM_TIMROT_TIMCTRLn_IRQ_EN(v)           BM_TIMROT_TIMCTRLn_IRQ_EN
+#define BF_TIMROT_TIMCTRLn_IRQ_EN_V(e)          BF_TIMROT_TIMCTRLn_IRQ_EN(BV_TIMROT_TIMCTRLn_IRQ_EN__##e)
+#define BFM_TIMROT_TIMCTRLn_IRQ_EN_V(v)         BM_TIMROT_TIMCTRLn_IRQ_EN
+#define BP_TIMROT_TIMCTRLn_POLARITY             8
+#define BM_TIMROT_TIMCTRLn_POLARITY             0x100
+#define BF_TIMROT_TIMCTRLn_POLARITY(v)          (((v) & 0x1) << 8)
+#define BFM_TIMROT_TIMCTRLn_POLARITY(v)         BM_TIMROT_TIMCTRLn_POLARITY
+#define BF_TIMROT_TIMCTRLn_POLARITY_V(e)        BF_TIMROT_TIMCTRLn_POLARITY(BV_TIMROT_TIMCTRLn_POLARITY__##e)
+#define BFM_TIMROT_TIMCTRLn_POLARITY_V(v)       BM_TIMROT_TIMCTRLn_POLARITY
+#define BP_TIMROT_TIMCTRLn_UPDATE               7
+#define BM_TIMROT_TIMCTRLn_UPDATE               0x80
+#define BF_TIMROT_TIMCTRLn_UPDATE(v)            (((v) & 0x1) << 7)
+#define BFM_TIMROT_TIMCTRLn_UPDATE(v)           BM_TIMROT_TIMCTRLn_UPDATE
+#define BF_TIMROT_TIMCTRLn_UPDATE_V(e)          BF_TIMROT_TIMCTRLn_UPDATE(BV_TIMROT_TIMCTRLn_UPDATE__##e)
+#define BFM_TIMROT_TIMCTRLn_UPDATE_V(v)         BM_TIMROT_TIMCTRLn_UPDATE
+#define BP_TIMROT_TIMCTRLn_RELOAD               6
+#define BM_TIMROT_TIMCTRLn_RELOAD               0x40
+#define BF_TIMROT_TIMCTRLn_RELOAD(v)            (((v) & 0x1) << 6)
+#define BFM_TIMROT_TIMCTRLn_RELOAD(v)           BM_TIMROT_TIMCTRLn_RELOAD
+#define BF_TIMROT_TIMCTRLn_RELOAD_V(e)          BF_TIMROT_TIMCTRLn_RELOAD(BV_TIMROT_TIMCTRLn_RELOAD__##e)
+#define BFM_TIMROT_TIMCTRLn_RELOAD_V(v)         BM_TIMROT_TIMCTRLn_RELOAD
+#define BP_TIMROT_TIMCTRLn_PRESCALE             4
+#define BM_TIMROT_TIMCTRLn_PRESCALE             0x30
+#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_1   0x0
+#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_2   0x1
+#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_4   0x2
+#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_8   0x3
+#define BF_TIMROT_TIMCTRLn_PRESCALE(v)          (((v) & 0x3) << 4)
+#define BFM_TIMROT_TIMCTRLn_PRESCALE(v)         BM_TIMROT_TIMCTRLn_PRESCALE
+#define BF_TIMROT_TIMCTRLn_PRESCALE_V(e)        BF_TIMROT_TIMCTRLn_PRESCALE(BV_TIMROT_TIMCTRLn_PRESCALE__##e)
+#define BFM_TIMROT_TIMCTRLn_PRESCALE_V(v)       BM_TIMROT_TIMCTRLn_PRESCALE
+#define BP_TIMROT_TIMCTRLn_SELECT               0
+#define BM_TIMROT_TIMCTRLn_SELECT               0xf
+#define BV_TIMROT_TIMCTRLn_SELECT__NEVER_TICK   0x0
+#define BV_TIMROT_TIMCTRLn_SELECT__PWM0         0x1
+#define BV_TIMROT_TIMCTRLn_SELECT__PWM1         0x2
+#define BV_TIMROT_TIMCTRLn_SELECT__PWM2         0x3
+#define BV_TIMROT_TIMCTRLn_SELECT__PWM3         0x4
+#define BV_TIMROT_TIMCTRLn_SELECT__PWM4         0x5
+#define BV_TIMROT_TIMCTRLn_SELECT__ROTARYA      0x6
+#define BV_TIMROT_TIMCTRLn_SELECT__ROTARYB      0x7
+#define BV_TIMROT_TIMCTRLn_SELECT__32KHZ_XTAL   0x8
+#define BV_TIMROT_TIMCTRLn_SELECT__8KHZ_XTAL    0x9
+#define BV_TIMROT_TIMCTRLn_SELECT__4KHZ_XTAL    0xa
+#define BV_TIMROT_TIMCTRLn_SELECT__1KHZ_XTAL    0xb
+#define BV_TIMROT_TIMCTRLn_SELECT__TICK_ALWAYS  0xc
+#define BF_TIMROT_TIMCTRLn_SELECT(v)            (((v) & 0xf) << 0)
+#define BFM_TIMROT_TIMCTRLn_SELECT(v)           BM_TIMROT_TIMCTRLn_SELECT
+#define BF_TIMROT_TIMCTRLn_SELECT_V(e)          BF_TIMROT_TIMCTRLn_SELECT(BV_TIMROT_TIMCTRLn_SELECT__##e)
+#define BFM_TIMROT_TIMCTRLn_SELECT_V(v)         BM_TIMROT_TIMCTRLn_SELECT
+
+#define HW_TIMROT_TIMCOUNTn(_n1)                HW(TIMROT_TIMCOUNTn(_n1))
+#define HWA_TIMROT_TIMCOUNTn(_n1)               (0x80068000 + 0x30 + (_n1) * 0x20)
+#define HWT_TIMROT_TIMCOUNTn(_n1)               HWIO_32_RW
+#define HWN_TIMROT_TIMCOUNTn(_n1)               TIMROT_TIMCOUNTn
+#define HWI_TIMROT_TIMCOUNTn(_n1)               (_n1)
+#define BP_TIMROT_TIMCOUNTn_RUNNING_COUNT       16
+#define BM_TIMROT_TIMCOUNTn_RUNNING_COUNT       0xffff0000
+#define BF_TIMROT_TIMCOUNTn_RUNNING_COUNT(v)    (((v) & 0xffff) << 16)
+#define BFM_TIMROT_TIMCOUNTn_RUNNING_COUNT(v)   BM_TIMROT_TIMCOUNTn_RUNNING_COUNT
+#define BF_TIMROT_TIMCOUNTn_RUNNING_COUNT_V(e)  BF_TIMROT_TIMCOUNTn_RUNNING_COUNT(BV_TIMROT_TIMCOUNTn_RUNNING_COUNT__##e)
+#define BFM_TIMROT_TIMCOUNTn_RUNNING_COUNT_V(v) BM_TIMROT_TIMCOUNTn_RUNNING_COUNT
+#define BP_TIMROT_TIMCOUNTn_FIXED_COUNT         0
+#define BM_TIMROT_TIMCOUNTn_FIXED_COUNT         0xffff
+#define BF_TIMROT_TIMCOUNTn_FIXED_COUNT(v)      (((v) & 0xffff) << 0)
+#define BFM_TIMROT_TIMCOUNTn_FIXED_COUNT(v)     BM_TIMROT_TIMCOUNTn_FIXED_COUNT
+#define BF_TIMROT_TIMCOUNTn_FIXED_COUNT_V(e)    BF_TIMROT_TIMCOUNTn_FIXED_COUNT(BV_TIMROT_TIMCOUNTn_FIXED_COUNT__##e)
+#define BFM_TIMROT_TIMCOUNTn_FIXED_COUNT_V(v)   BM_TIMROT_TIMCOUNTn_FIXED_COUNT
+
+#define HW_TIMROT_TIMCTRL3                          HW(TIMROT_TIMCTRL3)
+#define HWA_TIMROT_TIMCTRL3                         (0x80068000 + 0x80)
+#define HWT_TIMROT_TIMCTRL3                         HWIO_32_RW
+#define HWN_TIMROT_TIMCTRL3                         TIMROT_TIMCTRL3
+#define HWI_TIMROT_TIMCTRL3                         
+#define HW_TIMROT_TIMCTRL3_SET                      HW(TIMROT_TIMCTRL3_SET)
+#define HWA_TIMROT_TIMCTRL3_SET                     (HWA_TIMROT_TIMCTRL3 + 0x4)
+#define HWT_TIMROT_TIMCTRL3_SET                     HWIO_32_WO
+#define HWN_TIMROT_TIMCTRL3_SET                     TIMROT_TIMCTRL3
+#define HWI_TIMROT_TIMCTRL3_SET                     
+#define HW_TIMROT_TIMCTRL3_CLR                      HW(TIMROT_TIMCTRL3_CLR)
+#define HWA_TIMROT_TIMCTRL3_CLR                     (HWA_TIMROT_TIMCTRL3 + 0x8)
+#define HWT_TIMROT_TIMCTRL3_CLR                     HWIO_32_WO
+#define HWN_TIMROT_TIMCTRL3_CLR                     TIMROT_TIMCTRL3
+#define HWI_TIMROT_TIMCTRL3_CLR                     
+#define HW_TIMROT_TIMCTRL3_TOG                      HW(TIMROT_TIMCTRL3_TOG)
+#define HWA_TIMROT_TIMCTRL3_TOG                     (HWA_TIMROT_TIMCTRL3 + 0xc)
+#define HWT_TIMROT_TIMCTRL3_TOG                     HWIO_32_WO
+#define HWN_TIMROT_TIMCTRL3_TOG                     TIMROT_TIMCTRL3
+#define HWI_TIMROT_TIMCTRL3_TOG                     
+#define BP_TIMROT_TIMCTRL3_TEST_SIGNAL              16
+#define BM_TIMROT_TIMCTRL3_TEST_SIGNAL              0xf0000
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__NEVER_TICK  0x0
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM0        0x1
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM1        0x2
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM2        0x3
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM3        0x4
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM4        0x5
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__ROTARYA     0x6
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__ROTARYB     0x7
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__32KHZ_XTAL  0x8
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__8KHZ_XTAL   0x9
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__4KHZ_XTAL   0xa
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__1KHZ_XTAL   0xb
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__TICK_ALWAYS 0xc
+#define BF_TIMROT_TIMCTRL3_TEST_SIGNAL(v)           (((v) & 0xf) << 16)
+#define BFM_TIMROT_TIMCTRL3_TEST_SIGNAL(v)          BM_TIMROT_TIMCTRL3_TEST_SIGNAL
+#define BF_TIMROT_TIMCTRL3_TEST_SIGNAL_V(e)         BF_TIMROT_TIMCTRL3_TEST_SIGNAL(BV_TIMROT_TIMCTRL3_TEST_SIGNAL__##e)
+#define BFM_TIMROT_TIMCTRL3_TEST_SIGNAL_V(v)        BM_TIMROT_TIMCTRL3_TEST_SIGNAL
+#define BP_TIMROT_TIMCTRL3_IRQ                      15
+#define BM_TIMROT_TIMCTRL3_IRQ                      0x8000
+#define BF_TIMROT_TIMCTRL3_IRQ(v)                   (((v) & 0x1) << 15)
+#define BFM_TIMROT_TIMCTRL3_IRQ(v)                  BM_TIMROT_TIMCTRL3_IRQ
+#define BF_TIMROT_TIMCTRL3_IRQ_V(e)                 BF_TIMROT_TIMCTRL3_IRQ(BV_TIMROT_TIMCTRL3_IRQ__##e)
+#define BFM_TIMROT_TIMCTRL3_IRQ_V(v)                BM_TIMROT_TIMCTRL3_IRQ
+#define BP_TIMROT_TIMCTRL3_IRQ_EN                   14
+#define BM_TIMROT_TIMCTRL3_IRQ_EN                   0x4000
+#define BF_TIMROT_TIMCTRL3_IRQ_EN(v)                (((v) & 0x1) << 14)
+#define BFM_TIMROT_TIMCTRL3_IRQ_EN(v)               BM_TIMROT_TIMCTRL3_IRQ_EN
+#define BF_TIMROT_TIMCTRL3_IRQ_EN_V(e)              BF_TIMROT_TIMCTRL3_IRQ_EN(BV_TIMROT_TIMCTRL3_IRQ_EN__##e)
+#define BFM_TIMROT_TIMCTRL3_IRQ_EN_V(v)             BM_TIMROT_TIMCTRL3_IRQ_EN
+#define BP_TIMROT_TIMCTRL3_DUTY_VALID               10
+#define BM_TIMROT_TIMCTRL3_DUTY_VALID               0x400
+#define BF_TIMROT_TIMCTRL3_DUTY_VALID(v)            (((v) & 0x1) << 10)
+#define BFM_TIMROT_TIMCTRL3_DUTY_VALID(v)           BM_TIMROT_TIMCTRL3_DUTY_VALID
+#define BF_TIMROT_TIMCTRL3_DUTY_VALID_V(e)          BF_TIMROT_TIMCTRL3_DUTY_VALID(BV_TIMROT_TIMCTRL3_DUTY_VALID__##e)
+#define BFM_TIMROT_TIMCTRL3_DUTY_VALID_V(v)         BM_TIMROT_TIMCTRL3_DUTY_VALID
+#define BP_TIMROT_TIMCTRL3_DUTY_CYCLE               9
+#define BM_TIMROT_TIMCTRL3_DUTY_CYCLE               0x200
+#define BF_TIMROT_TIMCTRL3_DUTY_CYCLE(v)            (((v) & 0x1) << 9)
+#define BFM_TIMROT_TIMCTRL3_DUTY_CYCLE(v)           BM_TIMROT_TIMCTRL3_DUTY_CYCLE
+#define BF_TIMROT_TIMCTRL3_DUTY_CYCLE_V(e)          BF_TIMROT_TIMCTRL3_DUTY_CYCLE(BV_TIMROT_TIMCTRL3_DUTY_CYCLE__##e)
+#define BFM_TIMROT_TIMCTRL3_DUTY_CYCLE_V(v)         BM_TIMROT_TIMCTRL3_DUTY_CYCLE
+#define BP_TIMROT_TIMCTRL3_POLARITY                 8
+#define BM_TIMROT_TIMCTRL3_POLARITY                 0x100
+#define BF_TIMROT_TIMCTRL3_POLARITY(v)              (((v) & 0x1) << 8)
+#define BFM_TIMROT_TIMCTRL3_POLARITY(v)             BM_TIMROT_TIMCTRL3_POLARITY
+#define BF_TIMROT_TIMCTRL3_POLARITY_V(e)            BF_TIMROT_TIMCTRL3_POLARITY(BV_TIMROT_TIMCTRL3_POLARITY__##e)
+#define BFM_TIMROT_TIMCTRL3_POLARITY_V(v)           BM_TIMROT_TIMCTRL3_POLARITY
+#define BP_TIMROT_TIMCTRL3_UPDATE                   7
+#define BM_TIMROT_TIMCTRL3_UPDATE                   0x80
+#define BF_TIMROT_TIMCTRL3_UPDATE(v)                (((v) & 0x1) << 7)
+#define BFM_TIMROT_TIMCTRL3_UPDATE(v)               BM_TIMROT_TIMCTRL3_UPDATE
+#define BF_TIMROT_TIMCTRL3_UPDATE_V(e)              BF_TIMROT_TIMCTRL3_UPDATE(BV_TIMROT_TIMCTRL3_UPDATE__##e)
+#define BFM_TIMROT_TIMCTRL3_UPDATE_V(v)             BM_TIMROT_TIMCTRL3_UPDATE
+#define BP_TIMROT_TIMCTRL3_RELOAD                   6
+#define BM_TIMROT_TIMCTRL3_RELOAD                   0x40
+#define BF_TIMROT_TIMCTRL3_RELOAD(v)                (((v) & 0x1) << 6)
+#define BFM_TIMROT_TIMCTRL3_RELOAD(v)               BM_TIMROT_TIMCTRL3_RELOAD
+#define BF_TIMROT_TIMCTRL3_RELOAD_V(e)              BF_TIMROT_TIMCTRL3_RELOAD(BV_TIMROT_TIMCTRL3_RELOAD__##e)
+#define BFM_TIMROT_TIMCTRL3_RELOAD_V(v)             BM_TIMROT_TIMCTRL3_RELOAD
+#define BP_TIMROT_TIMCTRL3_PRESCALE                 4
+#define BM_TIMROT_TIMCTRL3_PRESCALE                 0x30
+#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_1       0x0
+#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_2       0x1
+#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_4       0x2
+#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_8       0x3
+#define BF_TIMROT_TIMCTRL3_PRESCALE(v)              (((v) & 0x3) << 4)
+#define BFM_TIMROT_TIMCTRL3_PRESCALE(v)             BM_TIMROT_TIMCTRL3_PRESCALE
+#define BF_TIMROT_TIMCTRL3_PRESCALE_V(e)            BF_TIMROT_TIMCTRL3_PRESCALE(BV_TIMROT_TIMCTRL3_PRESCALE__##e)
+#define BFM_TIMROT_TIMCTRL3_PRESCALE_V(v)           BM_TIMROT_TIMCTRL3_PRESCALE
+#define BP_TIMROT_TIMCTRL3_SELECT                   0
+#define BM_TIMROT_TIMCTRL3_SELECT                   0xf
+#define BV_TIMROT_TIMCTRL3_SELECT__NEVER_TICK       0x0
+#define BV_TIMROT_TIMCTRL3_SELECT__PWM0             0x1
+#define BV_TIMROT_TIMCTRL3_SELECT__PWM1             0x2
+#define BV_TIMROT_TIMCTRL3_SELECT__PWM2             0x3
+#define BV_TIMROT_TIMCTRL3_SELECT__PWM3             0x4
+#define BV_TIMROT_TIMCTRL3_SELECT__PWM4             0x5
+#define BV_TIMROT_TIMCTRL3_SELECT__ROTARYA          0x6
+#define BV_TIMROT_TIMCTRL3_SELECT__ROTARYB          0x7
+#define BV_TIMROT_TIMCTRL3_SELECT__32KHZ_XTAL       0x8
+#define BV_TIMROT_TIMCTRL3_SELECT__8KHZ_XTAL        0x9
+#define BV_TIMROT_TIMCTRL3_SELECT__4KHZ_XTAL        0xa
+#define BV_TIMROT_TIMCTRL3_SELECT__1KHZ_XTAL        0xb
+#define BV_TIMROT_TIMCTRL3_SELECT__TICK_ALWAYS      0xc
+#define BF_TIMROT_TIMCTRL3_SELECT(v)                (((v) & 0xf) << 0)
+#define BFM_TIMROT_TIMCTRL3_SELECT(v)               BM_TIMROT_TIMCTRL3_SELECT
+#define BF_TIMROT_TIMCTRL3_SELECT_V(e)              BF_TIMROT_TIMCTRL3_SELECT(BV_TIMROT_TIMCTRL3_SELECT__##e)
+#define BFM_TIMROT_TIMCTRL3_SELECT_V(v)             BM_TIMROT_TIMCTRL3_SELECT
+
+#define HW_TIMROT_TIMCOUNT3                         HW(TIMROT_TIMCOUNT3)
+#define HWA_TIMROT_TIMCOUNT3                        (0x80068000 + 0x90)
+#define HWT_TIMROT_TIMCOUNT3                        HWIO_32_RW
+#define HWN_TIMROT_TIMCOUNT3                        TIMROT_TIMCOUNT3
+#define HWI_TIMROT_TIMCOUNT3                        
+#define BP_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT       16
+#define BM_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT       0xffff0000
+#define BF_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT(v)    (((v) & 0xffff) << 16)
+#define BFM_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT(v)   BM_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT
+#define BF_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT_V(e)  BF_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT(BV_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT__##e)
+#define BFM_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT_V(v) BM_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT
+#define BP_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT        0
+#define BM_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT        0xffff
+#define BF_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT(v)     (((v) & 0xffff) << 0)
+#define BFM_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT(v)    BM_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT
+#define BF_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT_V(e)   BF_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT(BV_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT__##e)
+#define BFM_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT_V(v)  BM_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT
+
+#define HW_TIMROT_VERSION               HW(TIMROT_VERSION)
+#define HWA_TIMROT_VERSION              (0x80068000 + 0xa0)
+#define HWT_TIMROT_VERSION              HWIO_32_RW
+#define HWN_TIMROT_VERSION              TIMROT_VERSION
+#define HWI_TIMROT_VERSION              
+#define BP_TIMROT_VERSION_MAJOR         24
+#define BM_TIMROT_VERSION_MAJOR         0xff000000
+#define BF_TIMROT_VERSION_MAJOR(v)      (((v) & 0xff) << 24)
+#define BFM_TIMROT_VERSION_MAJOR(v)     BM_TIMROT_VERSION_MAJOR
+#define BF_TIMROT_VERSION_MAJOR_V(e)    BF_TIMROT_VERSION_MAJOR(BV_TIMROT_VERSION_MAJOR__##e)
+#define BFM_TIMROT_VERSION_MAJOR_V(v)   BM_TIMROT_VERSION_MAJOR
+#define BP_TIMROT_VERSION_MINOR         16
+#define BM_TIMROT_VERSION_MINOR         0xff0000
+#define BF_TIMROT_VERSION_MINOR(v)      (((v) & 0xff) << 16)
+#define BFM_TIMROT_VERSION_MINOR(v)     BM_TIMROT_VERSION_MINOR
+#define BF_TIMROT_VERSION_MINOR_V(e)    BF_TIMROT_VERSION_MINOR(BV_TIMROT_VERSION_MINOR__##e)
+#define BFM_TIMROT_VERSION_MINOR_V(v)   BM_TIMROT_VERSION_MINOR
+#define BP_TIMROT_VERSION_STEP          0
+#define BM_TIMROT_VERSION_STEP          0xffff
+#define BF_TIMROT_VERSION_STEP(v)       (((v) & 0xffff) << 0)
+#define BFM_TIMROT_VERSION_STEP(v)      BM_TIMROT_VERSION_STEP
+#define BF_TIMROT_VERSION_STEP_V(e)     BF_TIMROT_VERSION_STEP(BV_TIMROT_VERSION_STEP__##e)
+#define BFM_TIMROT_VERSION_STEP_V(v)    BM_TIMROT_VERSION_STEP
+
+#endif /* __HEADERGEN_STMP3700_TIMROT_H__*/
diff --git a/firmware/target/arm/imx233/regs/stmp3700/uartapp.h b/firmware/target/arm/imx233/regs/stmp3700/uartapp.h
new file mode 100644
index 0000000000..e961878f4f
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3700/uartapp.h
@@ -0,0 +1,767 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * stmp3700 version: 2.4.0
+ * stmp3700 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_STMP3700_UARTAPP_H__
+#define __HEADERGEN_STMP3700_UARTAPP_H__
+
+#define HW_UARTAPP_CTRL0(_n1)               HW(UARTAPP_CTRL0(_n1))
+#define HWA_UARTAPP_CTRL0(_n1)              (((_n1) == 1 ? 0x8006c000 : 0x8006e000) + 0x0)
+#define HWT_UARTAPP_CTRL0(_n1)              HWIO_32_RW
+#define HWN_UARTAPP_CTRL0(_n1)              UARTAPP_CTRL0
+#define HWI_UARTAPP_CTRL0(_n1)              (_n1)
+#define HW_UARTAPP_CTRL0_SET(_n1)           HW(UARTAPP_CTRL0_SET(_n1))
+#define HWA_UARTAPP_CTRL0_SET(_n1)          (HWA_UARTAPP_CTRL0(_n1) + 0x4)
+#define HWT_UARTAPP_CTRL0_SET(_n1)          HWIO_32_WO
+#define HWN_UARTAPP_CTRL0_SET(_n1)          UARTAPP_CTRL0
+#define HWI_UARTAPP_CTRL0_SET(_n1)          (_n1)
+#define HW_UARTAPP_CTRL0_CLR(_n1)           HW(UARTAPP_CTRL0_CLR(_n1))
+#define HWA_UARTAPP_CTRL0_CLR(_n1)          (HWA_UARTAPP_CTRL0(_n1) + 0x8)
+#define HWT_UARTAPP_CTRL0_CLR(_n1)          HWIO_32_WO
+#define HWN_UARTAPP_CTRL0_CLR(_n1)          UARTAPP_CTRL0
+#define HWI_UARTAPP_CTRL0_CLR(_n1)          (_n1)
+#define HW_UARTAPP_CTRL0_TOG(_n1)           HW(UARTAPP_CTRL0_TOG(_n1))
+#define HWA_UARTAPP_CTRL0_TOG(_n1)          (HWA_UARTAPP_CTRL0(_n1) + 0xc)
+#define HWT_UARTAPP_CTRL0_TOG(_n1)          HWIO_32_WO
+#define HWN_UARTAPP_CTRL0_TOG(_n1)          UARTAPP_CTRL0
+#define HWI_UARTAPP_CTRL0_TOG(_n1)          (_n1)
+#define BP_UARTAPP_CTRL0_SFTRST             31
+#define BM_UARTAPP_CTRL0_SFTRST             0x80000000
+#define BF_UARTAPP_CTRL0_SFTRST(v)          (((v) & 0x1) << 31)
+#define BFM_UARTAPP_CTRL0_SFTRST(v)         BM_UARTAPP_CTRL0_SFTRST
+#define BF_UARTAPP_CTRL0_SFTRST_V(e)        BF_UARTAPP_CTRL0_SFTRST(BV_UARTAPP_CTRL0_SFTRST__##e)
+#define BFM_UARTAPP_CTRL0_SFTRST_V(v)       BM_UARTAPP_CTRL0_SFTRST
+#define BP_UARTAPP_CTRL0_CLKGATE            30
+#define BM_UARTAPP_CTRL0_CLKGATE            0x40000000
+#define BF_UARTAPP_CTRL0_CLKGATE(v)         (((v) & 0x1) << 30)
+#define BFM_UARTAPP_CTRL0_CLKGATE(v)        BM_UARTAPP_CTRL0_CLKGATE
+#define BF_UARTAPP_CTRL0_CLKGATE_V(e)       BF_UARTAPP_CTRL0_CLKGATE(BV_UARTAPP_CTRL0_CLKGATE__##e)
+#define BFM_UARTAPP_CTRL0_CLKGATE_V(v)      BM_UARTAPP_CTRL0_CLKGATE
+#define BP_UARTAPP_CTRL0_RUN                29
+#define BM_UARTAPP_CTRL0_RUN                0x20000000
+#define BF_UARTAPP_CTRL0_RUN(v)             (((v) & 0x1) << 29)
+#define BFM_UARTAPP_CTRL0_RUN(v)            BM_UARTAPP_CTRL0_RUN
+#define BF_UARTAPP_CTRL0_RUN_V(e)           BF_UARTAPP_CTRL0_RUN(BV_UARTAPP_CTRL0_RUN__##e)
+#define BFM_UARTAPP_CTRL0_RUN_V(v)          BM_UARTAPP_CTRL0_RUN
+#define BP_UARTAPP_CTRL0_RX_SOURCE          28
+#define BM_UARTAPP_CTRL0_RX_SOURCE          0x10000000
+#define BF_UARTAPP_CTRL0_RX_SOURCE(v)       (((v) & 0x1) << 28)
+#define BFM_UARTAPP_CTRL0_RX_SOURCE(v)      BM_UARTAPP_CTRL0_RX_SOURCE
+#define BF_UARTAPP_CTRL0_RX_SOURCE_V(e)     BF_UARTAPP_CTRL0_RX_SOURCE(BV_UARTAPP_CTRL0_RX_SOURCE__##e)
+#define BFM_UARTAPP_CTRL0_RX_SOURCE_V(v)    BM_UARTAPP_CTRL0_RX_SOURCE
+#define BP_UARTAPP_CTRL0_RXTO_ENABLE        27
+#define BM_UARTAPP_CTRL0_RXTO_ENABLE        0x8000000
+#define BF_UARTAPP_CTRL0_RXTO_ENABLE(v)     (((v) & 0x1) << 27)
+#define BFM_UARTAPP_CTRL0_RXTO_ENABLE(v)    BM_UARTAPP_CTRL0_RXTO_ENABLE
+#define BF_UARTAPP_CTRL0_RXTO_ENABLE_V(e)   BF_UARTAPP_CTRL0_RXTO_ENABLE(BV_UARTAPP_CTRL0_RXTO_ENABLE__##e)
+#define BFM_UARTAPP_CTRL0_RXTO_ENABLE_V(v)  BM_UARTAPP_CTRL0_RXTO_ENABLE
+#define BP_UARTAPP_CTRL0_RXTIMEOUT          16
+#define BM_UARTAPP_CTRL0_RXTIMEOUT          0x7ff0000
+#define BF_UARTAPP_CTRL0_RXTIMEOUT(v)       (((v) & 0x7ff) << 16)
+#define BFM_UARTAPP_CTRL0_RXTIMEOUT(v)      BM_UARTAPP_CTRL0_RXTIMEOUT
+#define BF_UARTAPP_CTRL0_RXTIMEOUT_V(e)     BF_UARTAPP_CTRL0_RXTIMEOUT(BV_UARTAPP_CTRL0_RXTIMEOUT__##e)
+#define BFM_UARTAPP_CTRL0_RXTIMEOUT_V(v)    BM_UARTAPP_CTRL0_RXTIMEOUT
+#define BP_UARTAPP_CTRL0_XFER_COUNT         0
+#define BM_UARTAPP_CTRL0_XFER_COUNT         0xffff
+#define BF_UARTAPP_CTRL0_XFER_COUNT(v)      (((v) & 0xffff) << 0)
+#define BFM_UARTAPP_CTRL0_XFER_COUNT(v)     BM_UARTAPP_CTRL0_XFER_COUNT
+#define BF_UARTAPP_CTRL0_XFER_COUNT_V(e)    BF_UARTAPP_CTRL0_XFER_COUNT(BV_UARTAPP_CTRL0_XFER_COUNT__##e)
+#define BFM_UARTAPP_CTRL0_XFER_COUNT_V(v)   BM_UARTAPP_CTRL0_XFER_COUNT
+
+#define HW_UARTAPP_CTRL1(_n1)               HW(UARTAPP_CTRL1(_n1))
+#define HWA_UARTAPP_CTRL1(_n1)              (((_n1) == 1 ? 0x8006c000 : 0x8006e000) + 0x10)
+#define HWT_UARTAPP_CTRL1(_n1)              HWIO_32_RW
+#define HWN_UARTAPP_CTRL1(_n1)              UARTAPP_CTRL1
+#define HWI_UARTAPP_CTRL1(_n1)              (_n1)
+#define HW_UARTAPP_CTRL1_SET(_n1)           HW(UARTAPP_CTRL1_SET(_n1))
+#define HWA_UARTAPP_CTRL1_SET(_n1)          (HWA_UARTAPP_CTRL1(_n1) + 0x4)
+#define HWT_UARTAPP_CTRL1_SET(_n1)          HWIO_32_WO
+#define HWN_UARTAPP_CTRL1_SET(_n1)          UARTAPP_CTRL1
+#define HWI_UARTAPP_CTRL1_SET(_n1)          (_n1)
+#define HW_UARTAPP_CTRL1_CLR(_n1)           HW(UARTAPP_CTRL1_CLR(_n1))
+#define HWA_UARTAPP_CTRL1_CLR(_n1)          (HWA_UARTAPP_CTRL1(_n1) + 0x8)
+#define HWT_UARTAPP_CTRL1_CLR(_n1)          HWIO_32_WO
+#define HWN_UARTAPP_CTRL1_CLR(_n1)          UARTAPP_CTRL1
+#define HWI_UARTAPP_CTRL1_CLR(_n1)          (_n1)
+#define HW_UARTAPP_CTRL1_TOG(_n1)           HW(UARTAPP_CTRL1_TOG(_n1))
+#define HWA_UARTAPP_CTRL1_TOG(_n1)          (HWA_UARTAPP_CTRL1(_n1) + 0xc)
+#define HWT_UARTAPP_CTRL1_TOG(_n1)          HWIO_32_WO
+#define HWN_UARTAPP_CTRL1_TOG(_n1)          UARTAPP_CTRL1
+#define HWI_UARTAPP_CTRL1_TOG(_n1)          (_n1)
+#define BP_UARTAPP_CTRL1_RUN                28
+#define BM_UARTAPP_CTRL1_RUN                0x10000000
+#define BF_UARTAPP_CTRL1_RUN(v)             (((v) & 0x1) << 28)
+#define BFM_UARTAPP_CTRL1_RUN(v)            BM_UARTAPP_CTRL1_RUN
+#define BF_UARTAPP_CTRL1_RUN_V(e)           BF_UARTAPP_CTRL1_RUN(BV_UARTAPP_CTRL1_RUN__##e)
+#define BFM_UARTAPP_CTRL1_RUN_V(v)          BM_UARTAPP_CTRL1_RUN
+#define BP_UARTAPP_CTRL1_XFER_COUNT         0
+#define BM_UARTAPP_CTRL1_XFER_COUNT         0xffff
+#define BF_UARTAPP_CTRL1_XFER_COUNT(v)      (((v) & 0xffff) << 0)
+#define BFM_UARTAPP_CTRL1_XFER_COUNT(v)     BM_UARTAPP_CTRL1_XFER_COUNT
+#define BF_UARTAPP_CTRL1_XFER_COUNT_V(e)    BF_UARTAPP_CTRL1_XFER_COUNT(BV_UARTAPP_CTRL1_XFER_COUNT__##e)
+#define BFM_UARTAPP_CTRL1_XFER_COUNT_V(v)   BM_UARTAPP_CTRL1_XFER_COUNT
+
+#define HW_UARTAPP_CTRL2(_n1)                       HW(UARTAPP_CTRL2(_n1))
+#define HWA_UARTAPP_CTRL2(_n1)                      (((_n1) == 1 ? 0x8006c000 : 0x8006e000) + 0x20)
+#define HWT_UARTAPP_CTRL2(_n1)                      HWIO_32_RW
+#define HWN_UARTAPP_CTRL2(_n1)                      UARTAPP_CTRL2
+#define HWI_UARTAPP_CTRL2(_n1)                      (_n1)
+#define HW_UARTAPP_CTRL2_SET(_n1)                   HW(UARTAPP_CTRL2_SET(_n1))
+#define HWA_UARTAPP_CTRL2_SET(_n1)                  (HWA_UARTAPP_CTRL2(_n1) + 0x4)
+#define HWT_UARTAPP_CTRL2_SET(_n1)                  HWIO_32_WO
+#define HWN_UARTAPP_CTRL2_SET(_n1)                  UARTAPP_CTRL2
+#define HWI_UARTAPP_CTRL2_SET(_n1)                  (_n1)
+#define HW_UARTAPP_CTRL2_CLR(_n1)                   HW(UARTAPP_CTRL2_CLR(_n1))
+#define HWA_UARTAPP_CTRL2_CLR(_n1)                  (HWA_UARTAPP_CTRL2(_n1) + 0x8)
+#define HWT_UARTAPP_CTRL2_CLR(_n1)                  HWIO_32_WO
+#define HWN_UARTAPP_CTRL2_CLR(_n1)                  UARTAPP_CTRL2
+#define HWI_UARTAPP_CTRL2_CLR(_n1)                  (_n1)
+#define HW_UARTAPP_CTRL2_TOG(_n1)                   HW(UARTAPP_CTRL2_TOG(_n1))
+#define HWA_UARTAPP_CTRL2_TOG(_n1)                  (HWA_UARTAPP_CTRL2(_n1) + 0xc)
+#define HWT_UARTAPP_CTRL2_TOG(_n1)                  HWIO_32_WO
+#define HWN_UARTAPP_CTRL2_TOG(_n1)                  UARTAPP_CTRL2
+#define HWI_UARTAPP_CTRL2_TOG(_n1)                  (_n1)
+#define BP_UARTAPP_CTRL2_INVERT_RTS                 31
+#define BM_UARTAPP_CTRL2_INVERT_RTS                 0x80000000
+#define BF_UARTAPP_CTRL2_INVERT_RTS(v)              (((v) & 0x1) << 31)
+#define BFM_UARTAPP_CTRL2_INVERT_RTS(v)             BM_UARTAPP_CTRL2_INVERT_RTS
+#define BF_UARTAPP_CTRL2_INVERT_RTS_V(e)            BF_UARTAPP_CTRL2_INVERT_RTS(BV_UARTAPP_CTRL2_INVERT_RTS__##e)
+#define BFM_UARTAPP_CTRL2_INVERT_RTS_V(v)           BM_UARTAPP_CTRL2_INVERT_RTS
+#define BP_UARTAPP_CTRL2_INVERT_CTS                 30
+#define BM_UARTAPP_CTRL2_INVERT_CTS                 0x40000000
+#define BF_UARTAPP_CTRL2_INVERT_CTS(v)              (((v) & 0x1) << 30)
+#define BFM_UARTAPP_CTRL2_INVERT_CTS(v)             BM_UARTAPP_CTRL2_INVERT_CTS
+#define BF_UARTAPP_CTRL2_INVERT_CTS_V(e)            BF_UARTAPP_CTRL2_INVERT_CTS(BV_UARTAPP_CTRL2_INVERT_CTS__##e)
+#define BFM_UARTAPP_CTRL2_INVERT_CTS_V(v)           BM_UARTAPP_CTRL2_INVERT_CTS
+#define BP_UARTAPP_CTRL2_INVERT_TX                  29
+#define BM_UARTAPP_CTRL2_INVERT_TX                  0x20000000
+#define BF_UARTAPP_CTRL2_INVERT_TX(v)               (((v) & 0x1) << 29)
+#define BFM_UARTAPP_CTRL2_INVERT_TX(v)              BM_UARTAPP_CTRL2_INVERT_TX
+#define BF_UARTAPP_CTRL2_INVERT_TX_V(e)             BF_UARTAPP_CTRL2_INVERT_TX(BV_UARTAPP_CTRL2_INVERT_TX__##e)
+#define BFM_UARTAPP_CTRL2_INVERT_TX_V(v)            BM_UARTAPP_CTRL2_INVERT_TX
+#define BP_UARTAPP_CTRL2_INVERT_RX                  28
+#define BM_UARTAPP_CTRL2_INVERT_RX                  0x10000000
+#define BF_UARTAPP_CTRL2_INVERT_RX(v)               (((v) & 0x1) << 28)
+#define BFM_UARTAPP_CTRL2_INVERT_RX(v)              BM_UARTAPP_CTRL2_INVERT_RX
+#define BF_UARTAPP_CTRL2_INVERT_RX_V(e)             BF_UARTAPP_CTRL2_INVERT_RX(BV_UARTAPP_CTRL2_INVERT_RX__##e)
+#define BFM_UARTAPP_CTRL2_INVERT_RX_V(v)            BM_UARTAPP_CTRL2_INVERT_RX
+#define BP_UARTAPP_CTRL2_RTS_SEMAPHORE              27
+#define BM_UARTAPP_CTRL2_RTS_SEMAPHORE              0x8000000
+#define BF_UARTAPP_CTRL2_RTS_SEMAPHORE(v)           (((v) & 0x1) << 27)
+#define BFM_UARTAPP_CTRL2_RTS_SEMAPHORE(v)          BM_UARTAPP_CTRL2_RTS_SEMAPHORE
+#define BF_UARTAPP_CTRL2_RTS_SEMAPHORE_V(e)         BF_UARTAPP_CTRL2_RTS_SEMAPHORE(BV_UARTAPP_CTRL2_RTS_SEMAPHORE__##e)
+#define BFM_UARTAPP_CTRL2_RTS_SEMAPHORE_V(v)        BM_UARTAPP_CTRL2_RTS_SEMAPHORE
+#define BP_UARTAPP_CTRL2_DMAONERR                   26
+#define BM_UARTAPP_CTRL2_DMAONERR                   0x4000000
+#define BF_UARTAPP_CTRL2_DMAONERR(v)                (((v) & 0x1) << 26)
+#define BFM_UARTAPP_CTRL2_DMAONERR(v)               BM_UARTAPP_CTRL2_DMAONERR
+#define BF_UARTAPP_CTRL2_DMAONERR_V(e)              BF_UARTAPP_CTRL2_DMAONERR(BV_UARTAPP_CTRL2_DMAONERR__##e)
+#define BFM_UARTAPP_CTRL2_DMAONERR_V(v)             BM_UARTAPP_CTRL2_DMAONERR
+#define BP_UARTAPP_CTRL2_TXDMAE                     25
+#define BM_UARTAPP_CTRL2_TXDMAE                     0x2000000
+#define BF_UARTAPP_CTRL2_TXDMAE(v)                  (((v) & 0x1) << 25)
+#define BFM_UARTAPP_CTRL2_TXDMAE(v)                 BM_UARTAPP_CTRL2_TXDMAE
+#define BF_UARTAPP_CTRL2_TXDMAE_V(e)                BF_UARTAPP_CTRL2_TXDMAE(BV_UARTAPP_CTRL2_TXDMAE__##e)
+#define BFM_UARTAPP_CTRL2_TXDMAE_V(v)               BM_UARTAPP_CTRL2_TXDMAE
+#define BP_UARTAPP_CTRL2_RXDMAE                     24
+#define BM_UARTAPP_CTRL2_RXDMAE                     0x1000000
+#define BF_UARTAPP_CTRL2_RXDMAE(v)                  (((v) & 0x1) << 24)
+#define BFM_UARTAPP_CTRL2_RXDMAE(v)                 BM_UARTAPP_CTRL2_RXDMAE
+#define BF_UARTAPP_CTRL2_RXDMAE_V(e)                BF_UARTAPP_CTRL2_RXDMAE(BV_UARTAPP_CTRL2_RXDMAE__##e)
+#define BFM_UARTAPP_CTRL2_RXDMAE_V(v)               BM_UARTAPP_CTRL2_RXDMAE
+#define BP_UARTAPP_CTRL2_RXIFLSEL                   20
+#define BM_UARTAPP_CTRL2_RXIFLSEL                   0x700000
+#define BV_UARTAPP_CTRL2_RXIFLSEL__NOT_EMPTY        0x0
+#define BV_UARTAPP_CTRL2_RXIFLSEL__ONE_QUARTER      0x1
+#define BV_UARTAPP_CTRL2_RXIFLSEL__ONE_HALF         0x2
+#define BV_UARTAPP_CTRL2_RXIFLSEL__THREE_QUARTERS   0x3
+#define BV_UARTAPP_CTRL2_RXIFLSEL__SEVEN_EIGHTHS    0x4
+#define BV_UARTAPP_CTRL2_RXIFLSEL__INVALID5         0x5
+#define BV_UARTAPP_CTRL2_RXIFLSEL__INVALID6         0x6
+#define BV_UARTAPP_CTRL2_RXIFLSEL__INVALID7         0x7
+#define BF_UARTAPP_CTRL2_RXIFLSEL(v)                (((v) & 0x7) << 20)
+#define BFM_UARTAPP_CTRL2_RXIFLSEL(v)               BM_UARTAPP_CTRL2_RXIFLSEL
+#define BF_UARTAPP_CTRL2_RXIFLSEL_V(e)              BF_UARTAPP_CTRL2_RXIFLSEL(BV_UARTAPP_CTRL2_RXIFLSEL__##e)
+#define BFM_UARTAPP_CTRL2_RXIFLSEL_V(v)             BM_UARTAPP_CTRL2_RXIFLSEL
+#define BP_UARTAPP_CTRL2_TXIFLSEL                   16
+#define BM_UARTAPP_CTRL2_TXIFLSEL                   0x70000
+#define BV_UARTAPP_CTRL2_TXIFLSEL__EMPTY            0x0
+#define BV_UARTAPP_CTRL2_TXIFLSEL__ONE_QUARTER      0x1
+#define BV_UARTAPP_CTRL2_TXIFLSEL__ONE_HALF         0x2
+#define BV_UARTAPP_CTRL2_TXIFLSEL__THREE_QUARTERS   0x3
+#define BV_UARTAPP_CTRL2_TXIFLSEL__SEVEN_EIGHTHS    0x4
+#define BV_UARTAPP_CTRL2_TXIFLSEL__INVALID5         0x5
+#define BV_UARTAPP_CTRL2_TXIFLSEL__INVALID6         0x6
+#define BV_UARTAPP_CTRL2_TXIFLSEL__INVALID7         0x7
+#define BF_UARTAPP_CTRL2_TXIFLSEL(v)                (((v) & 0x7) << 16)
+#define BFM_UARTAPP_CTRL2_TXIFLSEL(v)               BM_UARTAPP_CTRL2_TXIFLSEL
+#define BF_UARTAPP_CTRL2_TXIFLSEL_V(e)              BF_UARTAPP_CTRL2_TXIFLSEL(BV_UARTAPP_CTRL2_TXIFLSEL__##e)
+#define BFM_UARTAPP_CTRL2_TXIFLSEL_V(v)             BM_UARTAPP_CTRL2_TXIFLSEL
+#define BP_UARTAPP_CTRL2_CTSEN                      15
+#define BM_UARTAPP_CTRL2_CTSEN                      0x8000
+#define BF_UARTAPP_CTRL2_CTSEN(v)                   (((v) & 0x1) << 15)
+#define BFM_UARTAPP_CTRL2_CTSEN(v)                  BM_UARTAPP_CTRL2_CTSEN
+#define BF_UARTAPP_CTRL2_CTSEN_V(e)                 BF_UARTAPP_CTRL2_CTSEN(BV_UARTAPP_CTRL2_CTSEN__##e)
+#define BFM_UARTAPP_CTRL2_CTSEN_V(v)                BM_UARTAPP_CTRL2_CTSEN
+#define BP_UARTAPP_CTRL2_RTSEN                      14
+#define BM_UARTAPP_CTRL2_RTSEN                      0x4000
+#define BF_UARTAPP_CTRL2_RTSEN(v)                   (((v) & 0x1) << 14)
+#define BFM_UARTAPP_CTRL2_RTSEN(v)                  BM_UARTAPP_CTRL2_RTSEN
+#define BF_UARTAPP_CTRL2_RTSEN_V(e)                 BF_UARTAPP_CTRL2_RTSEN(BV_UARTAPP_CTRL2_RTSEN__##e)
+#define BFM_UARTAPP_CTRL2_RTSEN_V(v)                BM_UARTAPP_CTRL2_RTSEN
+#define BP_UARTAPP_CTRL2_OUT2                       13
+#define BM_UARTAPP_CTRL2_OUT2                       0x2000
+#define BF_UARTAPP_CTRL2_OUT2(v)                    (((v) & 0x1) << 13)
+#define BFM_UARTAPP_CTRL2_OUT2(v)                   BM_UARTAPP_CTRL2_OUT2
+#define BF_UARTAPP_CTRL2_OUT2_V(e)                  BF_UARTAPP_CTRL2_OUT2(BV_UARTAPP_CTRL2_OUT2__##e)
+#define BFM_UARTAPP_CTRL2_OUT2_V(v)                 BM_UARTAPP_CTRL2_OUT2
+#define BP_UARTAPP_CTRL2_OUT1                       12
+#define BM_UARTAPP_CTRL2_OUT1                       0x1000
+#define BF_UARTAPP_CTRL2_OUT1(v)                    (((v) & 0x1) << 12)
+#define BFM_UARTAPP_CTRL2_OUT1(v)                   BM_UARTAPP_CTRL2_OUT1
+#define BF_UARTAPP_CTRL2_OUT1_V(e)                  BF_UARTAPP_CTRL2_OUT1(BV_UARTAPP_CTRL2_OUT1__##e)
+#define BFM_UARTAPP_CTRL2_OUT1_V(v)                 BM_UARTAPP_CTRL2_OUT1
+#define BP_UARTAPP_CTRL2_RTS                        11
+#define BM_UARTAPP_CTRL2_RTS                        0x800
+#define BF_UARTAPP_CTRL2_RTS(v)                     (((v) & 0x1) << 11)
+#define BFM_UARTAPP_CTRL2_RTS(v)                    BM_UARTAPP_CTRL2_RTS
+#define BF_UARTAPP_CTRL2_RTS_V(e)                   BF_UARTAPP_CTRL2_RTS(BV_UARTAPP_CTRL2_RTS__##e)
+#define BFM_UARTAPP_CTRL2_RTS_V(v)                  BM_UARTAPP_CTRL2_RTS
+#define BP_UARTAPP_CTRL2_DTR                        10
+#define BM_UARTAPP_CTRL2_DTR                        0x400
+#define BF_UARTAPP_CTRL2_DTR(v)                     (((v) & 0x1) << 10)
+#define BFM_UARTAPP_CTRL2_DTR(v)                    BM_UARTAPP_CTRL2_DTR
+#define BF_UARTAPP_CTRL2_DTR_V(e)                   BF_UARTAPP_CTRL2_DTR(BV_UARTAPP_CTRL2_DTR__##e)
+#define BFM_UARTAPP_CTRL2_DTR_V(v)                  BM_UARTAPP_CTRL2_DTR
+#define BP_UARTAPP_CTRL2_RXE                        9
+#define BM_UARTAPP_CTRL2_RXE                        0x200
+#define BF_UARTAPP_CTRL2_RXE(v)                     (((v) & 0x1) << 9)
+#define BFM_UARTAPP_CTRL2_RXE(v)                    BM_UARTAPP_CTRL2_RXE
+#define BF_UARTAPP_CTRL2_RXE_V(e)                   BF_UARTAPP_CTRL2_RXE(BV_UARTAPP_CTRL2_RXE__##e)
+#define BFM_UARTAPP_CTRL2_RXE_V(v)                  BM_UARTAPP_CTRL2_RXE
+#define BP_UARTAPP_CTRL2_TXE                        8
+#define BM_UARTAPP_CTRL2_TXE                        0x100
+#define BF_UARTAPP_CTRL2_TXE(v)                     (((v) & 0x1) << 8)
+#define BFM_UARTAPP_CTRL2_TXE(v)                    BM_UARTAPP_CTRL2_TXE
+#define BF_UARTAPP_CTRL2_TXE_V(e)                   BF_UARTAPP_CTRL2_TXE(BV_UARTAPP_CTRL2_TXE__##e)
+#define BFM_UARTAPP_CTRL2_TXE_V(v)                  BM_UARTAPP_CTRL2_TXE
+#define BP_UARTAPP_CTRL2_LBE                        7
+#define BM_UARTAPP_CTRL2_LBE                        0x80
+#define BF_UARTAPP_CTRL2_LBE(v)                     (((v) & 0x1) << 7)
+#define BFM_UARTAPP_CTRL2_LBE(v)                    BM_UARTAPP_CTRL2_LBE
+#define BF_UARTAPP_CTRL2_LBE_V(e)                   BF_UARTAPP_CTRL2_LBE(BV_UARTAPP_CTRL2_LBE__##e)
+#define BFM_UARTAPP_CTRL2_LBE_V(v)                  BM_UARTAPP_CTRL2_LBE
+#define BP_UARTAPP_CTRL2_USE_LCR2                   6
+#define BM_UARTAPP_CTRL2_USE_LCR2                   0x40
+#define BF_UARTAPP_CTRL2_USE_LCR2(v)                (((v) & 0x1) << 6)
+#define BFM_UARTAPP_CTRL2_USE_LCR2(v)               BM_UARTAPP_CTRL2_USE_LCR2
+#define BF_UARTAPP_CTRL2_USE_LCR2_V(e)              BF_UARTAPP_CTRL2_USE_LCR2(BV_UARTAPP_CTRL2_USE_LCR2__##e)
+#define BFM_UARTAPP_CTRL2_USE_LCR2_V(v)             BM_UARTAPP_CTRL2_USE_LCR2
+#define BP_UARTAPP_CTRL2_SIRLP                      2
+#define BM_UARTAPP_CTRL2_SIRLP                      0x4
+#define BF_UARTAPP_CTRL2_SIRLP(v)                   (((v) & 0x1) << 2)
+#define BFM_UARTAPP_CTRL2_SIRLP(v)                  BM_UARTAPP_CTRL2_SIRLP
+#define BF_UARTAPP_CTRL2_SIRLP_V(e)                 BF_UARTAPP_CTRL2_SIRLP(BV_UARTAPP_CTRL2_SIRLP__##e)
+#define BFM_UARTAPP_CTRL2_SIRLP_V(v)                BM_UARTAPP_CTRL2_SIRLP
+#define BP_UARTAPP_CTRL2_SIREN                      1
+#define BM_UARTAPP_CTRL2_SIREN                      0x2
+#define BF_UARTAPP_CTRL2_SIREN(v)                   (((v) & 0x1) << 1)
+#define BFM_UARTAPP_CTRL2_SIREN(v)                  BM_UARTAPP_CTRL2_SIREN
+#define BF_UARTAPP_CTRL2_SIREN_V(e)                 BF_UARTAPP_CTRL2_SIREN(BV_UARTAPP_CTRL2_SIREN__##e)
+#define BFM_UARTAPP_CTRL2_SIREN_V(v)                BM_UARTAPP_CTRL2_SIREN
+#define BP_UARTAPP_CTRL2_UARTEN                     0
+#define BM_UARTAPP_CTRL2_UARTEN                     0x1
+#define BF_UARTAPP_CTRL2_UARTEN(v)                  (((v) & 0x1) << 0)
+#define BFM_UARTAPP_CTRL2_UARTEN(v)                 BM_UARTAPP_CTRL2_UARTEN
+#define BF_UARTAPP_CTRL2_UARTEN_V(e)                BF_UARTAPP_CTRL2_UARTEN(BV_UARTAPP_CTRL2_UARTEN__##e)
+#define BFM_UARTAPP_CTRL2_UARTEN_V(v)               BM_UARTAPP_CTRL2_UARTEN
+
+#define HW_UARTAPP_LINECTRL(_n1)                HW(UARTAPP_LINECTRL(_n1))
+#define HWA_UARTAPP_LINECTRL(_n1)               (((_n1) == 1 ? 0x8006c000 : 0x8006e000) + 0x30)
+#define HWT_UARTAPP_LINECTRL(_n1)               HWIO_32_RW
+#define HWN_UARTAPP_LINECTRL(_n1)               UARTAPP_LINECTRL
+#define HWI_UARTAPP_LINECTRL(_n1)               (_n1)
+#define HW_UARTAPP_LINECTRL_SET(_n1)            HW(UARTAPP_LINECTRL_SET(_n1))
+#define HWA_UARTAPP_LINECTRL_SET(_n1)           (HWA_UARTAPP_LINECTRL(_n1) + 0x4)
+#define HWT_UARTAPP_LINECTRL_SET(_n1)           HWIO_32_WO
+#define HWN_UARTAPP_LINECTRL_SET(_n1)           UARTAPP_LINECTRL
+#define HWI_UARTAPP_LINECTRL_SET(_n1)           (_n1)
+#define HW_UARTAPP_LINECTRL_CLR(_n1)            HW(UARTAPP_LINECTRL_CLR(_n1))
+#define HWA_UARTAPP_LINECTRL_CLR(_n1)           (HWA_UARTAPP_LINECTRL(_n1) + 0x8)
+#define HWT_UARTAPP_LINECTRL_CLR(_n1)           HWIO_32_WO
+#define HWN_UARTAPP_LINECTRL_CLR(_n1)           UARTAPP_LINECTRL
+#define HWI_UARTAPP_LINECTRL_CLR(_n1)           (_n1)
+#define HW_UARTAPP_LINECTRL_TOG(_n1)            HW(UARTAPP_LINECTRL_TOG(_n1))
+#define HWA_UARTAPP_LINECTRL_TOG(_n1)           (HWA_UARTAPP_LINECTRL(_n1) + 0xc)
+#define HWT_UARTAPP_LINECTRL_TOG(_n1)           HWIO_32_WO
+#define HWN_UARTAPP_LINECTRL_TOG(_n1)           UARTAPP_LINECTRL
+#define HWI_UARTAPP_LINECTRL_TOG(_n1)           (_n1)
+#define BP_UARTAPP_LINECTRL_BAUD_DIVINT         16
+#define BM_UARTAPP_LINECTRL_BAUD_DIVINT         0xffff0000
+#define BF_UARTAPP_LINECTRL_BAUD_DIVINT(v)      (((v) & 0xffff) << 16)
+#define BFM_UARTAPP_LINECTRL_BAUD_DIVINT(v)     BM_UARTAPP_LINECTRL_BAUD_DIVINT
+#define BF_UARTAPP_LINECTRL_BAUD_DIVINT_V(e)    BF_UARTAPP_LINECTRL_BAUD_DIVINT(BV_UARTAPP_LINECTRL_BAUD_DIVINT__##e)
+#define BFM_UARTAPP_LINECTRL_BAUD_DIVINT_V(v)   BM_UARTAPP_LINECTRL_BAUD_DIVINT
+#define BP_UARTAPP_LINECTRL_BAUD_DIVFRAC        8
+#define BM_UARTAPP_LINECTRL_BAUD_DIVFRAC        0x3f00
+#define BF_UARTAPP_LINECTRL_BAUD_DIVFRAC(v)     (((v) & 0x3f) << 8)
+#define BFM_UARTAPP_LINECTRL_BAUD_DIVFRAC(v)    BM_UARTAPP_LINECTRL_BAUD_DIVFRAC
+#define BF_UARTAPP_LINECTRL_BAUD_DIVFRAC_V(e)   BF_UARTAPP_LINECTRL_BAUD_DIVFRAC(BV_UARTAPP_LINECTRL_BAUD_DIVFRAC__##e)
+#define BFM_UARTAPP_LINECTRL_BAUD_DIVFRAC_V(v)  BM_UARTAPP_LINECTRL_BAUD_DIVFRAC
+#define BP_UARTAPP_LINECTRL_SPS                 7
+#define BM_UARTAPP_LINECTRL_SPS                 0x80
+#define BF_UARTAPP_LINECTRL_SPS(v)              (((v) & 0x1) << 7)
+#define BFM_UARTAPP_LINECTRL_SPS(v)             BM_UARTAPP_LINECTRL_SPS
+#define BF_UARTAPP_LINECTRL_SPS_V(e)            BF_UARTAPP_LINECTRL_SPS(BV_UARTAPP_LINECTRL_SPS__##e)
+#define BFM_UARTAPP_LINECTRL_SPS_V(v)           BM_UARTAPP_LINECTRL_SPS
+#define BP_UARTAPP_LINECTRL_WLEN                5
+#define BM_UARTAPP_LINECTRL_WLEN                0x60
+#define BF_UARTAPP_LINECTRL_WLEN(v)             (((v) & 0x3) << 5)
+#define BFM_UARTAPP_LINECTRL_WLEN(v)            BM_UARTAPP_LINECTRL_WLEN
+#define BF_UARTAPP_LINECTRL_WLEN_V(e)           BF_UARTAPP_LINECTRL_WLEN(BV_UARTAPP_LINECTRL_WLEN__##e)
+#define BFM_UARTAPP_LINECTRL_WLEN_V(v)          BM_UARTAPP_LINECTRL_WLEN
+#define BP_UARTAPP_LINECTRL_FEN                 4
+#define BM_UARTAPP_LINECTRL_FEN                 0x10
+#define BF_UARTAPP_LINECTRL_FEN(v)              (((v) & 0x1) << 4)
+#define BFM_UARTAPP_LINECTRL_FEN(v)             BM_UARTAPP_LINECTRL_FEN
+#define BF_UARTAPP_LINECTRL_FEN_V(e)            BF_UARTAPP_LINECTRL_FEN(BV_UARTAPP_LINECTRL_FEN__##e)
+#define BFM_UARTAPP_LINECTRL_FEN_V(v)           BM_UARTAPP_LINECTRL_FEN
+#define BP_UARTAPP_LINECTRL_STP2                3
+#define BM_UARTAPP_LINECTRL_STP2                0x8
+#define BF_UARTAPP_LINECTRL_STP2(v)             (((v) & 0x1) << 3)
+#define BFM_UARTAPP_LINECTRL_STP2(v)            BM_UARTAPP_LINECTRL_STP2
+#define BF_UARTAPP_LINECTRL_STP2_V(e)           BF_UARTAPP_LINECTRL_STP2(BV_UARTAPP_LINECTRL_STP2__##e)
+#define BFM_UARTAPP_LINECTRL_STP2_V(v)          BM_UARTAPP_LINECTRL_STP2
+#define BP_UARTAPP_LINECTRL_EPS                 2
+#define BM_UARTAPP_LINECTRL_EPS                 0x4
+#define BF_UARTAPP_LINECTRL_EPS(v)              (((v) & 0x1) << 2)
+#define BFM_UARTAPP_LINECTRL_EPS(v)             BM_UARTAPP_LINECTRL_EPS
+#define BF_UARTAPP_LINECTRL_EPS_V(e)            BF_UARTAPP_LINECTRL_EPS(BV_UARTAPP_LINECTRL_EPS__##e)
+#define BFM_UARTAPP_LINECTRL_EPS_V(v)           BM_UARTAPP_LINECTRL_EPS
+#define BP_UARTAPP_LINECTRL_PEN                 1
+#define BM_UARTAPP_LINECTRL_PEN                 0x2
+#define BF_UARTAPP_LINECTRL_PEN(v)              (((v) & 0x1) << 1)
+#define BFM_UARTAPP_LINECTRL_PEN(v)             BM_UARTAPP_LINECTRL_PEN
+#define BF_UARTAPP_LINECTRL_PEN_V(e)            BF_UARTAPP_LINECTRL_PEN(BV_UARTAPP_LINECTRL_PEN__##e)
+#define BFM_UARTAPP_LINECTRL_PEN_V(v)           BM_UARTAPP_LINECTRL_PEN
+#define BP_UARTAPP_LINECTRL_BRK                 0
+#define BM_UARTAPP_LINECTRL_BRK                 0x1
+#define BF_UARTAPP_LINECTRL_BRK(v)              (((v) & 0x1) << 0)
+#define BFM_UARTAPP_LINECTRL_BRK(v)             BM_UARTAPP_LINECTRL_BRK
+#define BF_UARTAPP_LINECTRL_BRK_V(e)            BF_UARTAPP_LINECTRL_BRK(BV_UARTAPP_LINECTRL_BRK__##e)
+#define BFM_UARTAPP_LINECTRL_BRK_V(v)           BM_UARTAPP_LINECTRL_BRK
+
+#define HW_UARTAPP_LINECTRL2(_n1)               HW(UARTAPP_LINECTRL2(_n1))
+#define HWA_UARTAPP_LINECTRL2(_n1)              (((_n1) == 1 ? 0x8006c000 : 0x8006e000) + 0x40)
+#define HWT_UARTAPP_LINECTRL2(_n1)              HWIO_32_RW
+#define HWN_UARTAPP_LINECTRL2(_n1)              UARTAPP_LINECTRL2
+#define HWI_UARTAPP_LINECTRL2(_n1)              (_n1)
+#define HW_UARTAPP_LINECTRL2_SET(_n1)           HW(UARTAPP_LINECTRL2_SET(_n1))
+#define HWA_UARTAPP_LINECTRL2_SET(_n1)          (HWA_UARTAPP_LINECTRL2(_n1) + 0x4)
+#define HWT_UARTAPP_LINECTRL2_SET(_n1)          HWIO_32_WO
+#define HWN_UARTAPP_LINECTRL2_SET(_n1)          UARTAPP_LINECTRL2
+#define HWI_UARTAPP_LINECTRL2_SET(_n1)          (_n1)
+#define HW_UARTAPP_LINECTRL2_CLR(_n1)           HW(UARTAPP_LINECTRL2_CLR(_n1))
+#define HWA_UARTAPP_LINECTRL2_CLR(_n1)          (HWA_UARTAPP_LINECTRL2(_n1) + 0x8)
+#define HWT_UARTAPP_LINECTRL2_CLR(_n1)          HWIO_32_WO
+#define HWN_UARTAPP_LINECTRL2_CLR(_n1)          UARTAPP_LINECTRL2
+#define HWI_UARTAPP_LINECTRL2_CLR(_n1)          (_n1)
+#define HW_UARTAPP_LINECTRL2_TOG(_n1)           HW(UARTAPP_LINECTRL2_TOG(_n1))
+#define HWA_UARTAPP_LINECTRL2_TOG(_n1)          (HWA_UARTAPP_LINECTRL2(_n1) + 0xc)
+#define HWT_UARTAPP_LINECTRL2_TOG(_n1)          HWIO_32_WO
+#define HWN_UARTAPP_LINECTRL2_TOG(_n1)          UARTAPP_LINECTRL2
+#define HWI_UARTAPP_LINECTRL2_TOG(_n1)          (_n1)
+#define BP_UARTAPP_LINECTRL2_BAUD_DIVINT        16
+#define BM_UARTAPP_LINECTRL2_BAUD_DIVINT        0xffff0000
+#define BF_UARTAPP_LINECTRL2_BAUD_DIVINT(v)     (((v) & 0xffff) << 16)
+#define BFM_UARTAPP_LINECTRL2_BAUD_DIVINT(v)    BM_UARTAPP_LINECTRL2_BAUD_DIVINT
+#define BF_UARTAPP_LINECTRL2_BAUD_DIVINT_V(e)   BF_UARTAPP_LINECTRL2_BAUD_DIVINT(BV_UARTAPP_LINECTRL2_BAUD_DIVINT__##e)
+#define BFM_UARTAPP_LINECTRL2_BAUD_DIVINT_V(v)  BM_UARTAPP_LINECTRL2_BAUD_DIVINT
+#define BP_UARTAPP_LINECTRL2_BAUD_DIVFRAC       8
+#define BM_UARTAPP_LINECTRL2_BAUD_DIVFRAC       0x3f00
+#define BF_UARTAPP_LINECTRL2_BAUD_DIVFRAC(v)    (((v) & 0x3f) << 8)
+#define BFM_UARTAPP_LINECTRL2_BAUD_DIVFRAC(v)   BM_UARTAPP_LINECTRL2_BAUD_DIVFRAC
+#define BF_UARTAPP_LINECTRL2_BAUD_DIVFRAC_V(e)  BF_UARTAPP_LINECTRL2_BAUD_DIVFRAC(BV_UARTAPP_LINECTRL2_BAUD_DIVFRAC__##e)
+#define BFM_UARTAPP_LINECTRL2_BAUD_DIVFRAC_V(v) BM_UARTAPP_LINECTRL2_BAUD_DIVFRAC
+#define BP_UARTAPP_LINECTRL2_SPS                7
+#define BM_UARTAPP_LINECTRL2_SPS                0x80
+#define BF_UARTAPP_LINECTRL2_SPS(v)             (((v) & 0x1) << 7)
+#define BFM_UARTAPP_LINECTRL2_SPS(v)            BM_UARTAPP_LINECTRL2_SPS
+#define BF_UARTAPP_LINECTRL2_SPS_V(e)           BF_UARTAPP_LINECTRL2_SPS(BV_UARTAPP_LINECTRL2_SPS__##e)
+#define BFM_UARTAPP_LINECTRL2_SPS_V(v)          BM_UARTAPP_LINECTRL2_SPS
+#define BP_UARTAPP_LINECTRL2_WLEN               5
+#define BM_UARTAPP_LINECTRL2_WLEN               0x60
+#define BF_UARTAPP_LINECTRL2_WLEN(v)            (((v) & 0x3) << 5)
+#define BFM_UARTAPP_LINECTRL2_WLEN(v)           BM_UARTAPP_LINECTRL2_WLEN
+#define BF_UARTAPP_LINECTRL2_WLEN_V(e)          BF_UARTAPP_LINECTRL2_WLEN(BV_UARTAPP_LINECTRL2_WLEN__##e)
+#define BFM_UARTAPP_LINECTRL2_WLEN_V(v)         BM_UARTAPP_LINECTRL2_WLEN
+#define BP_UARTAPP_LINECTRL2_FEN                4
+#define BM_UARTAPP_LINECTRL2_FEN                0x10
+#define BF_UARTAPP_LINECTRL2_FEN(v)             (((v) & 0x1) << 4)
+#define BFM_UARTAPP_LINECTRL2_FEN(v)            BM_UARTAPP_LINECTRL2_FEN
+#define BF_UARTAPP_LINECTRL2_FEN_V(e)           BF_UARTAPP_LINECTRL2_FEN(BV_UARTAPP_LINECTRL2_FEN__##e)
+#define BFM_UARTAPP_LINECTRL2_FEN_V(v)          BM_UARTAPP_LINECTRL2_FEN
+#define BP_UARTAPP_LINECTRL2_STP2               3
+#define BM_UARTAPP_LINECTRL2_STP2               0x8
+#define BF_UARTAPP_LINECTRL2_STP2(v)            (((v) & 0x1) << 3)
+#define BFM_UARTAPP_LINECTRL2_STP2(v)           BM_UARTAPP_LINECTRL2_STP2
+#define BF_UARTAPP_LINECTRL2_STP2_V(e)          BF_UARTAPP_LINECTRL2_STP2(BV_UARTAPP_LINECTRL2_STP2__##e)
+#define BFM_UARTAPP_LINECTRL2_STP2_V(v)         BM_UARTAPP_LINECTRL2_STP2
+#define BP_UARTAPP_LINECTRL2_EPS                2
+#define BM_UARTAPP_LINECTRL2_EPS                0x4
+#define BF_UARTAPP_LINECTRL2_EPS(v)             (((v) & 0x1) << 2)
+#define BFM_UARTAPP_LINECTRL2_EPS(v)            BM_UARTAPP_LINECTRL2_EPS
+#define BF_UARTAPP_LINECTRL2_EPS_V(e)           BF_UARTAPP_LINECTRL2_EPS(BV_UARTAPP_LINECTRL2_EPS__##e)
+#define BFM_UARTAPP_LINECTRL2_EPS_V(v)          BM_UARTAPP_LINECTRL2_EPS
+#define BP_UARTAPP_LINECTRL2_PEN                1
+#define BM_UARTAPP_LINECTRL2_PEN                0x2
+#define BF_UARTAPP_LINECTRL2_PEN(v)             (((v) & 0x1) << 1)
+#define BFM_UARTAPP_LINECTRL2_PEN(v)            BM_UARTAPP_LINECTRL2_PEN
+#define BF_UARTAPP_LINECTRL2_PEN_V(e)           BF_UARTAPP_LINECTRL2_PEN(BV_UARTAPP_LINECTRL2_PEN__##e)
+#define BFM_UARTAPP_LINECTRL2_PEN_V(v)          BM_UARTAPP_LINECTRL2_PEN
+
+#define HW_UARTAPP_INTR(_n1)            HW(UARTAPP_INTR(_n1))
+#define HWA_UARTAPP_INTR(_n1)           (((_n1) == 1 ? 0x8006c000 : 0x8006e000) + 0x50)
+#define HWT_UARTAPP_INTR(_n1)           HWIO_32_RW
+#define HWN_UARTAPP_INTR(_n1)           UARTAPP_INTR
+#define HWI_UARTAPP_INTR(_n1)           (_n1)
+#define HW_UARTAPP_INTR_SET(_n1)        HW(UARTAPP_INTR_SET(_n1))
+#define HWA_UARTAPP_INTR_SET(_n1)       (HWA_UARTAPP_INTR(_n1) + 0x4)
+#define HWT_UARTAPP_INTR_SET(_n1)       HWIO_32_WO
+#define HWN_UARTAPP_INTR_SET(_n1)       UARTAPP_INTR
+#define HWI_UARTAPP_INTR_SET(_n1)       (_n1)
+#define HW_UARTAPP_INTR_CLR(_n1)        HW(UARTAPP_INTR_CLR(_n1))
+#define HWA_UARTAPP_INTR_CLR(_n1)       (HWA_UARTAPP_INTR(_n1) + 0x8)
+#define HWT_UARTAPP_INTR_CLR(_n1)       HWIO_32_WO
+#define HWN_UARTAPP_INTR_CLR(_n1)       UARTAPP_INTR
+#define HWI_UARTAPP_INTR_CLR(_n1)       (_n1)
+#define HW_UARTAPP_INTR_TOG(_n1)        HW(UARTAPP_INTR_TOG(_n1))
+#define HWA_UARTAPP_INTR_TOG(_n1)       (HWA_UARTAPP_INTR(_n1) + 0xc)
+#define HWT_UARTAPP_INTR_TOG(_n1)       HWIO_32_WO
+#define HWN_UARTAPP_INTR_TOG(_n1)       UARTAPP_INTR
+#define HWI_UARTAPP_INTR_TOG(_n1)       (_n1)
+#define BP_UARTAPP_INTR_OEIEN           26
+#define BM_UARTAPP_INTR_OEIEN           0x4000000
+#define BF_UARTAPP_INTR_OEIEN(v)        (((v) & 0x1) << 26)
+#define BFM_UARTAPP_INTR_OEIEN(v)       BM_UARTAPP_INTR_OEIEN
+#define BF_UARTAPP_INTR_OEIEN_V(e)      BF_UARTAPP_INTR_OEIEN(BV_UARTAPP_INTR_OEIEN__##e)
+#define BFM_UARTAPP_INTR_OEIEN_V(v)     BM_UARTAPP_INTR_OEIEN
+#define BP_UARTAPP_INTR_BEIEN           25
+#define BM_UARTAPP_INTR_BEIEN           0x2000000
+#define BF_UARTAPP_INTR_BEIEN(v)        (((v) & 0x1) << 25)
+#define BFM_UARTAPP_INTR_BEIEN(v)       BM_UARTAPP_INTR_BEIEN
+#define BF_UARTAPP_INTR_BEIEN_V(e)      BF_UARTAPP_INTR_BEIEN(BV_UARTAPP_INTR_BEIEN__##e)
+#define BFM_UARTAPP_INTR_BEIEN_V(v)     BM_UARTAPP_INTR_BEIEN
+#define BP_UARTAPP_INTR_PEIEN           24
+#define BM_UARTAPP_INTR_PEIEN           0x1000000
+#define BF_UARTAPP_INTR_PEIEN(v)        (((v) & 0x1) << 24)
+#define BFM_UARTAPP_INTR_PEIEN(v)       BM_UARTAPP_INTR_PEIEN
+#define BF_UARTAPP_INTR_PEIEN_V(e)      BF_UARTAPP_INTR_PEIEN(BV_UARTAPP_INTR_PEIEN__##e)
+#define BFM_UARTAPP_INTR_PEIEN_V(v)     BM_UARTAPP_INTR_PEIEN
+#define BP_UARTAPP_INTR_FEIEN           23
+#define BM_UARTAPP_INTR_FEIEN           0x800000
+#define BF_UARTAPP_INTR_FEIEN(v)        (((v) & 0x1) << 23)
+#define BFM_UARTAPP_INTR_FEIEN(v)       BM_UARTAPP_INTR_FEIEN
+#define BF_UARTAPP_INTR_FEIEN_V(e)      BF_UARTAPP_INTR_FEIEN(BV_UARTAPP_INTR_FEIEN__##e)
+#define BFM_UARTAPP_INTR_FEIEN_V(v)     BM_UARTAPP_INTR_FEIEN
+#define BP_UARTAPP_INTR_RTIEN           22
+#define BM_UARTAPP_INTR_RTIEN           0x400000
+#define BF_UARTAPP_INTR_RTIEN(v)        (((v) & 0x1) << 22)
+#define BFM_UARTAPP_INTR_RTIEN(v)       BM_UARTAPP_INTR_RTIEN
+#define BF_UARTAPP_INTR_RTIEN_V(e)      BF_UARTAPP_INTR_RTIEN(BV_UARTAPP_INTR_RTIEN__##e)
+#define BFM_UARTAPP_INTR_RTIEN_V(v)     BM_UARTAPP_INTR_RTIEN
+#define BP_UARTAPP_INTR_TXIEN           21
+#define BM_UARTAPP_INTR_TXIEN           0x200000
+#define BF_UARTAPP_INTR_TXIEN(v)        (((v) & 0x1) << 21)
+#define BFM_UARTAPP_INTR_TXIEN(v)       BM_UARTAPP_INTR_TXIEN
+#define BF_UARTAPP_INTR_TXIEN_V(e)      BF_UARTAPP_INTR_TXIEN(BV_UARTAPP_INTR_TXIEN__##e)
+#define BFM_UARTAPP_INTR_TXIEN_V(v)     BM_UARTAPP_INTR_TXIEN
+#define BP_UARTAPP_INTR_RXIEN           20
+#define BM_UARTAPP_INTR_RXIEN           0x100000
+#define BF_UARTAPP_INTR_RXIEN(v)        (((v) & 0x1) << 20)
+#define BFM_UARTAPP_INTR_RXIEN(v)       BM_UARTAPP_INTR_RXIEN
+#define BF_UARTAPP_INTR_RXIEN_V(e)      BF_UARTAPP_INTR_RXIEN(BV_UARTAPP_INTR_RXIEN__##e)
+#define BFM_UARTAPP_INTR_RXIEN_V(v)     BM_UARTAPP_INTR_RXIEN
+#define BP_UARTAPP_INTR_DSRMIEN         19
+#define BM_UARTAPP_INTR_DSRMIEN         0x80000
+#define BF_UARTAPP_INTR_DSRMIEN(v)      (((v) & 0x1) << 19)
+#define BFM_UARTAPP_INTR_DSRMIEN(v)     BM_UARTAPP_INTR_DSRMIEN
+#define BF_UARTAPP_INTR_DSRMIEN_V(e)    BF_UARTAPP_INTR_DSRMIEN(BV_UARTAPP_INTR_DSRMIEN__##e)
+#define BFM_UARTAPP_INTR_DSRMIEN_V(v)   BM_UARTAPP_INTR_DSRMIEN
+#define BP_UARTAPP_INTR_DCDMIEN         18
+#define BM_UARTAPP_INTR_DCDMIEN         0x40000
+#define BF_UARTAPP_INTR_DCDMIEN(v)      (((v) & 0x1) << 18)
+#define BFM_UARTAPP_INTR_DCDMIEN(v)     BM_UARTAPP_INTR_DCDMIEN
+#define BF_UARTAPP_INTR_DCDMIEN_V(e)    BF_UARTAPP_INTR_DCDMIEN(BV_UARTAPP_INTR_DCDMIEN__##e)
+#define BFM_UARTAPP_INTR_DCDMIEN_V(v)   BM_UARTAPP_INTR_DCDMIEN
+#define BP_UARTAPP_INTR_CTSMIEN         17
+#define BM_UARTAPP_INTR_CTSMIEN         0x20000
+#define BF_UARTAPP_INTR_CTSMIEN(v)      (((v) & 0x1) << 17)
+#define BFM_UARTAPP_INTR_CTSMIEN(v)     BM_UARTAPP_INTR_CTSMIEN
+#define BF_UARTAPP_INTR_CTSMIEN_V(e)    BF_UARTAPP_INTR_CTSMIEN(BV_UARTAPP_INTR_CTSMIEN__##e)
+#define BFM_UARTAPP_INTR_CTSMIEN_V(v)   BM_UARTAPP_INTR_CTSMIEN
+#define BP_UARTAPP_INTR_RIMIEN          16
+#define BM_UARTAPP_INTR_RIMIEN          0x10000
+#define BF_UARTAPP_INTR_RIMIEN(v)       (((v) & 0x1) << 16)
+#define BFM_UARTAPP_INTR_RIMIEN(v)      BM_UARTAPP_INTR_RIMIEN
+#define BF_UARTAPP_INTR_RIMIEN_V(e)     BF_UARTAPP_INTR_RIMIEN(BV_UARTAPP_INTR_RIMIEN__##e)
+#define BFM_UARTAPP_INTR_RIMIEN_V(v)    BM_UARTAPP_INTR_RIMIEN
+#define BP_UARTAPP_INTR_OEIS            10
+#define BM_UARTAPP_INTR_OEIS            0x400
+#define BF_UARTAPP_INTR_OEIS(v)         (((v) & 0x1) << 10)
+#define BFM_UARTAPP_INTR_OEIS(v)        BM_UARTAPP_INTR_OEIS
+#define BF_UARTAPP_INTR_OEIS_V(e)       BF_UARTAPP_INTR_OEIS(BV_UARTAPP_INTR_OEIS__##e)
+#define BFM_UARTAPP_INTR_OEIS_V(v)      BM_UARTAPP_INTR_OEIS
+#define BP_UARTAPP_INTR_BEIS            9
+#define BM_UARTAPP_INTR_BEIS            0x200
+#define BF_UARTAPP_INTR_BEIS(v)         (((v) & 0x1) << 9)
+#define BFM_UARTAPP_INTR_BEIS(v)        BM_UARTAPP_INTR_BEIS
+#define BF_UARTAPP_INTR_BEIS_V(e)       BF_UARTAPP_INTR_BEIS(BV_UARTAPP_INTR_BEIS__##e)
+#define BFM_UARTAPP_INTR_BEIS_V(v)      BM_UARTAPP_INTR_BEIS
+#define BP_UARTAPP_INTR_PEIS            8
+#define BM_UARTAPP_INTR_PEIS            0x100
+#define BF_UARTAPP_INTR_PEIS(v)         (((v) & 0x1) << 8)
+#define BFM_UARTAPP_INTR_PEIS(v)        BM_UARTAPP_INTR_PEIS
+#define BF_UARTAPP_INTR_PEIS_V(e)       BF_UARTAPP_INTR_PEIS(BV_UARTAPP_INTR_PEIS__##e)
+#define BFM_UARTAPP_INTR_PEIS_V(v)      BM_UARTAPP_INTR_PEIS
+#define BP_UARTAPP_INTR_FEIS            7
+#define BM_UARTAPP_INTR_FEIS            0x80
+#define BF_UARTAPP_INTR_FEIS(v)         (((v) & 0x1) << 7)
+#define BFM_UARTAPP_INTR_FEIS(v)        BM_UARTAPP_INTR_FEIS
+#define BF_UARTAPP_INTR_FEIS_V(e)       BF_UARTAPP_INTR_FEIS(BV_UARTAPP_INTR_FEIS__##e)
+#define BFM_UARTAPP_INTR_FEIS_V(v)      BM_UARTAPP_INTR_FEIS
+#define BP_UARTAPP_INTR_RTIS            6
+#define BM_UARTAPP_INTR_RTIS            0x40
+#define BF_UARTAPP_INTR_RTIS(v)         (((v) & 0x1) << 6)
+#define BFM_UARTAPP_INTR_RTIS(v)        BM_UARTAPP_INTR_RTIS
+#define BF_UARTAPP_INTR_RTIS_V(e)       BF_UARTAPP_INTR_RTIS(BV_UARTAPP_INTR_RTIS__##e)
+#define BFM_UARTAPP_INTR_RTIS_V(v)      BM_UARTAPP_INTR_RTIS
+#define BP_UARTAPP_INTR_TXIS            5
+#define BM_UARTAPP_INTR_TXIS            0x20
+#define BF_UARTAPP_INTR_TXIS(v)         (((v) & 0x1) << 5)
+#define BFM_UARTAPP_INTR_TXIS(v)        BM_UARTAPP_INTR_TXIS
+#define BF_UARTAPP_INTR_TXIS_V(e)       BF_UARTAPP_INTR_TXIS(BV_UARTAPP_INTR_TXIS__##e)
+#define BFM_UARTAPP_INTR_TXIS_V(v)      BM_UARTAPP_INTR_TXIS
+#define BP_UARTAPP_INTR_RXIS            4
+#define BM_UARTAPP_INTR_RXIS            0x10
+#define BF_UARTAPP_INTR_RXIS(v)         (((v) & 0x1) << 4)
+#define BFM_UARTAPP_INTR_RXIS(v)        BM_UARTAPP_INTR_RXIS
+#define BF_UARTAPP_INTR_RXIS_V(e)       BF_UARTAPP_INTR_RXIS(BV_UARTAPP_INTR_RXIS__##e)
+#define BFM_UARTAPP_INTR_RXIS_V(v)      BM_UARTAPP_INTR_RXIS
+#define BP_UARTAPP_INTR_DSRMIS          3
+#define BM_UARTAPP_INTR_DSRMIS          0x8
+#define BF_UARTAPP_INTR_DSRMIS(v)       (((v) & 0x1) << 3)
+#define BFM_UARTAPP_INTR_DSRMIS(v)      BM_UARTAPP_INTR_DSRMIS
+#define BF_UARTAPP_INTR_DSRMIS_V(e)     BF_UARTAPP_INTR_DSRMIS(BV_UARTAPP_INTR_DSRMIS__##e)
+#define BFM_UARTAPP_INTR_DSRMIS_V(v)    BM_UARTAPP_INTR_DSRMIS
+#define BP_UARTAPP_INTR_DCDMIS          2
+#define BM_UARTAPP_INTR_DCDMIS          0x4
+#define BF_UARTAPP_INTR_DCDMIS(v)       (((v) & 0x1) << 2)
+#define BFM_UARTAPP_INTR_DCDMIS(v)      BM_UARTAPP_INTR_DCDMIS
+#define BF_UARTAPP_INTR_DCDMIS_V(e)     BF_UARTAPP_INTR_DCDMIS(BV_UARTAPP_INTR_DCDMIS__##e)
+#define BFM_UARTAPP_INTR_DCDMIS_V(v)    BM_UARTAPP_INTR_DCDMIS
+#define BP_UARTAPP_INTR_CTSMIS          1
+#define BM_UARTAPP_INTR_CTSMIS          0x2
+#define BF_UARTAPP_INTR_CTSMIS(v)       (((v) & 0x1) << 1)
+#define BFM_UARTAPP_INTR_CTSMIS(v)      BM_UARTAPP_INTR_CTSMIS
+#define BF_UARTAPP_INTR_CTSMIS_V(e)     BF_UARTAPP_INTR_CTSMIS(BV_UARTAPP_INTR_CTSMIS__##e)
+#define BFM_UARTAPP_INTR_CTSMIS_V(v)    BM_UARTAPP_INTR_CTSMIS
+#define BP_UARTAPP_INTR_RIMIS           0
+#define BM_UARTAPP_INTR_RIMIS           0x1
+#define BF_UARTAPP_INTR_RIMIS(v)        (((v) & 0x1) << 0)
+#define BFM_UARTAPP_INTR_RIMIS(v)       BM_UARTAPP_INTR_RIMIS
+#define BF_UARTAPP_INTR_RIMIS_V(e)      BF_UARTAPP_INTR_RIMIS(BV_UARTAPP_INTR_RIMIS__##e)
+#define BFM_UARTAPP_INTR_RIMIS_V(v)     BM_UARTAPP_INTR_RIMIS
+
+#define HW_UARTAPP_DATA(_n1)        HW(UARTAPP_DATA(_n1))
+#define HWA_UARTAPP_DATA(_n1)       (((_n1) == 1 ? 0x8006c000 : 0x8006e000) + 0x60)
+#define HWT_UARTAPP_DATA(_n1)       HWIO_32_RW
+#define HWN_UARTAPP_DATA(_n1)       UARTAPP_DATA
+#define HWI_UARTAPP_DATA(_n1)       (_n1)
+#define BP_UARTAPP_DATA_DATA        0
+#define BM_UARTAPP_DATA_DATA        0xffffffff
+#define BF_UARTAPP_DATA_DATA(v)     (((v) & 0xffffffff) << 0)
+#define BFM_UARTAPP_DATA_DATA(v)    BM_UARTAPP_DATA_DATA
+#define BF_UARTAPP_DATA_DATA_V(e)   BF_UARTAPP_DATA_DATA(BV_UARTAPP_DATA_DATA__##e)
+#define BFM_UARTAPP_DATA_DATA_V(v)  BM_UARTAPP_DATA_DATA
+
+#define HW_UARTAPP_STAT(_n1)                    HW(UARTAPP_STAT(_n1))
+#define HWA_UARTAPP_STAT(_n1)                   (((_n1) == 1 ? 0x8006c000 : 0x8006e000) + 0x70)
+#define HWT_UARTAPP_STAT(_n1)                   HWIO_32_RW
+#define HWN_UARTAPP_STAT(_n1)                   UARTAPP_STAT
+#define HWI_UARTAPP_STAT(_n1)                   (_n1)
+#define BP_UARTAPP_STAT_PRESENT                 31
+#define BM_UARTAPP_STAT_PRESENT                 0x80000000
+#define BV_UARTAPP_STAT_PRESENT__UNAVAILABLE    0x0
+#define BV_UARTAPP_STAT_PRESENT__AVAILABLE      0x1
+#define BF_UARTAPP_STAT_PRESENT(v)              (((v) & 0x1) << 31)
+#define BFM_UARTAPP_STAT_PRESENT(v)             BM_UARTAPP_STAT_PRESENT
+#define BF_UARTAPP_STAT_PRESENT_V(e)            BF_UARTAPP_STAT_PRESENT(BV_UARTAPP_STAT_PRESENT__##e)
+#define BFM_UARTAPP_STAT_PRESENT_V(v)           BM_UARTAPP_STAT_PRESENT
+#define BP_UARTAPP_STAT_HISPEED                 30
+#define BM_UARTAPP_STAT_HISPEED                 0x40000000
+#define BV_UARTAPP_STAT_HISPEED__UNAVAILABLE    0x0
+#define BV_UARTAPP_STAT_HISPEED__AVAILABLE      0x1
+#define BF_UARTAPP_STAT_HISPEED(v)              (((v) & 0x1) << 30)
+#define BFM_UARTAPP_STAT_HISPEED(v)             BM_UARTAPP_STAT_HISPEED
+#define BF_UARTAPP_STAT_HISPEED_V(e)            BF_UARTAPP_STAT_HISPEED(BV_UARTAPP_STAT_HISPEED__##e)
+#define BFM_UARTAPP_STAT_HISPEED_V(v)           BM_UARTAPP_STAT_HISPEED
+#define BP_UARTAPP_STAT_BUSY                    29
+#define BM_UARTAPP_STAT_BUSY                    0x20000000
+#define BF_UARTAPP_STAT_BUSY(v)                 (((v) & 0x1) << 29)
+#define BFM_UARTAPP_STAT_BUSY(v)                BM_UARTAPP_STAT_BUSY
+#define BF_UARTAPP_STAT_BUSY_V(e)               BF_UARTAPP_STAT_BUSY(BV_UARTAPP_STAT_BUSY__##e)
+#define BFM_UARTAPP_STAT_BUSY_V(v)              BM_UARTAPP_STAT_BUSY
+#define BP_UARTAPP_STAT_CTS                     28
+#define BM_UARTAPP_STAT_CTS                     0x10000000
+#define BF_UARTAPP_STAT_CTS(v)                  (((v) & 0x1) << 28)
+#define BFM_UARTAPP_STAT_CTS(v)                 BM_UARTAPP_STAT_CTS
+#define BF_UARTAPP_STAT_CTS_V(e)                BF_UARTAPP_STAT_CTS(BV_UARTAPP_STAT_CTS__##e)
+#define BFM_UARTAPP_STAT_CTS_V(v)               BM_UARTAPP_STAT_CTS
+#define BP_UARTAPP_STAT_TXFE                    27
+#define BM_UARTAPP_STAT_TXFE                    0x8000000
+#define BF_UARTAPP_STAT_TXFE(v)                 (((v) & 0x1) << 27)
+#define BFM_UARTAPP_STAT_TXFE(v)                BM_UARTAPP_STAT_TXFE
+#define BF_UARTAPP_STAT_TXFE_V(e)               BF_UARTAPP_STAT_TXFE(BV_UARTAPP_STAT_TXFE__##e)
+#define BFM_UARTAPP_STAT_TXFE_V(v)              BM_UARTAPP_STAT_TXFE
+#define BP_UARTAPP_STAT_RXFF                    26
+#define BM_UARTAPP_STAT_RXFF                    0x4000000
+#define BF_UARTAPP_STAT_RXFF(v)                 (((v) & 0x1) << 26)
+#define BFM_UARTAPP_STAT_RXFF(v)                BM_UARTAPP_STAT_RXFF
+#define BF_UARTAPP_STAT_RXFF_V(e)               BF_UARTAPP_STAT_RXFF(BV_UARTAPP_STAT_RXFF__##e)
+#define BFM_UARTAPP_STAT_RXFF_V(v)              BM_UARTAPP_STAT_RXFF
+#define BP_UARTAPP_STAT_TXFF                    25
+#define BM_UARTAPP_STAT_TXFF                    0x2000000
+#define BF_UARTAPP_STAT_TXFF(v)                 (((v) & 0x1) << 25)
+#define BFM_UARTAPP_STAT_TXFF(v)                BM_UARTAPP_STAT_TXFF
+#define BF_UARTAPP_STAT_TXFF_V(e)               BF_UARTAPP_STAT_TXFF(BV_UARTAPP_STAT_TXFF__##e)
+#define BFM_UARTAPP_STAT_TXFF_V(v)              BM_UARTAPP_STAT_TXFF
+#define BP_UARTAPP_STAT_RXFE                    24
+#define BM_UARTAPP_STAT_RXFE                    0x1000000
+#define BF_UARTAPP_STAT_RXFE(v)                 (((v) & 0x1) << 24)
+#define BFM_UARTAPP_STAT_RXFE(v)                BM_UARTAPP_STAT_RXFE
+#define BF_UARTAPP_STAT_RXFE_V(e)               BF_UARTAPP_STAT_RXFE(BV_UARTAPP_STAT_RXFE__##e)
+#define BFM_UARTAPP_STAT_RXFE_V(v)              BM_UARTAPP_STAT_RXFE
+#define BP_UARTAPP_STAT_RXBYTE_INVALID          20
+#define BM_UARTAPP_STAT_RXBYTE_INVALID          0xf00000
+#define BF_UARTAPP_STAT_RXBYTE_INVALID(v)       (((v) & 0xf) << 20)
+#define BFM_UARTAPP_STAT_RXBYTE_INVALID(v)      BM_UARTAPP_STAT_RXBYTE_INVALID
+#define BF_UARTAPP_STAT_RXBYTE_INVALID_V(e)     BF_UARTAPP_STAT_RXBYTE_INVALID(BV_UARTAPP_STAT_RXBYTE_INVALID__##e)
+#define BFM_UARTAPP_STAT_RXBYTE_INVALID_V(v)    BM_UARTAPP_STAT_RXBYTE_INVALID
+#define BP_UARTAPP_STAT_OERR                    19
+#define BM_UARTAPP_STAT_OERR                    0x80000
+#define BF_UARTAPP_STAT_OERR(v)                 (((v) & 0x1) << 19)
+#define BFM_UARTAPP_STAT_OERR(v)                BM_UARTAPP_STAT_OERR
+#define BF_UARTAPP_STAT_OERR_V(e)               BF_UARTAPP_STAT_OERR(BV_UARTAPP_STAT_OERR__##e)
+#define BFM_UARTAPP_STAT_OERR_V(v)              BM_UARTAPP_STAT_OERR
+#define BP_UARTAPP_STAT_BERR                    18
+#define BM_UARTAPP_STAT_BERR                    0x40000
+#define BF_UARTAPP_STAT_BERR(v)                 (((v) & 0x1) << 18)
+#define BFM_UARTAPP_STAT_BERR(v)                BM_UARTAPP_STAT_BERR
+#define BF_UARTAPP_STAT_BERR_V(e)               BF_UARTAPP_STAT_BERR(BV_UARTAPP_STAT_BERR__##e)
+#define BFM_UARTAPP_STAT_BERR_V(v)              BM_UARTAPP_STAT_BERR
+#define BP_UARTAPP_STAT_PERR                    17
+#define BM_UARTAPP_STAT_PERR                    0x20000
+#define BF_UARTAPP_STAT_PERR(v)                 (((v) & 0x1) << 17)
+#define BFM_UARTAPP_STAT_PERR(v)                BM_UARTAPP_STAT_PERR
+#define BF_UARTAPP_STAT_PERR_V(e)               BF_UARTAPP_STAT_PERR(BV_UARTAPP_STAT_PERR__##e)
+#define BFM_UARTAPP_STAT_PERR_V(v)              BM_UARTAPP_STAT_PERR
+#define BP_UARTAPP_STAT_FERR                    16
+#define BM_UARTAPP_STAT_FERR                    0x10000
+#define BF_UARTAPP_STAT_FERR(v)                 (((v) & 0x1) << 16)
+#define BFM_UARTAPP_STAT_FERR(v)                BM_UARTAPP_STAT_FERR
+#define BF_UARTAPP_STAT_FERR_V(e)               BF_UARTAPP_STAT_FERR(BV_UARTAPP_STAT_FERR__##e)
+#define BFM_UARTAPP_STAT_FERR_V(v)              BM_UARTAPP_STAT_FERR
+#define BP_UARTAPP_STAT_RXCOUNT                 0
+#define BM_UARTAPP_STAT_RXCOUNT                 0xffff
+#define BF_UARTAPP_STAT_RXCOUNT(v)              (((v) & 0xffff) << 0)
+#define BFM_UARTAPP_STAT_RXCOUNT(v)             BM_UARTAPP_STAT_RXCOUNT
+#define BF_UARTAPP_STAT_RXCOUNT_V(e)            BF_UARTAPP_STAT_RXCOUNT(BV_UARTAPP_STAT_RXCOUNT__##e)
+#define BFM_UARTAPP_STAT_RXCOUNT_V(v)           BM_UARTAPP_STAT_RXCOUNT
+
+#define HW_UARTAPP_DEBUG(_n1)           HW(UARTAPP_DEBUG(_n1))
+#define HWA_UARTAPP_DEBUG(_n1)          (((_n1) == 1 ? 0x8006c000 : 0x8006e000) + 0x80)
+#define HWT_UARTAPP_DEBUG(_n1)          HWIO_32_RW
+#define HWN_UARTAPP_DEBUG(_n1)          UARTAPP_DEBUG
+#define HWI_UARTAPP_DEBUG(_n1)          (_n1)
+#define BP_UARTAPP_DEBUG_TXDMARUN       5
+#define BM_UARTAPP_DEBUG_TXDMARUN       0x20
+#define BF_UARTAPP_DEBUG_TXDMARUN(v)    (((v) & 0x1) << 5)
+#define BFM_UARTAPP_DEBUG_TXDMARUN(v)   BM_UARTAPP_DEBUG_TXDMARUN
+#define BF_UARTAPP_DEBUG_TXDMARUN_V(e)  BF_UARTAPP_DEBUG_TXDMARUN(BV_UARTAPP_DEBUG_TXDMARUN__##e)
+#define BFM_UARTAPP_DEBUG_TXDMARUN_V(v) BM_UARTAPP_DEBUG_TXDMARUN
+#define BP_UARTAPP_DEBUG_RXDMARUN       4
+#define BM_UARTAPP_DEBUG_RXDMARUN       0x10
+#define BF_UARTAPP_DEBUG_RXDMARUN(v)    (((v) & 0x1) << 4)
+#define BFM_UARTAPP_DEBUG_RXDMARUN(v)   BM_UARTAPP_DEBUG_RXDMARUN
+#define BF_UARTAPP_DEBUG_RXDMARUN_V(e)  BF_UARTAPP_DEBUG_RXDMARUN(BV_UARTAPP_DEBUG_RXDMARUN__##e)
+#define BFM_UARTAPP_DEBUG_RXDMARUN_V(v) BM_UARTAPP_DEBUG_RXDMARUN
+#define BP_UARTAPP_DEBUG_TXCMDEND       3
+#define BM_UARTAPP_DEBUG_TXCMDEND       0x8
+#define BF_UARTAPP_DEBUG_TXCMDEND(v)    (((v) & 0x1) << 3)
+#define BFM_UARTAPP_DEBUG_TXCMDEND(v)   BM_UARTAPP_DEBUG_TXCMDEND
+#define BF_UARTAPP_DEBUG_TXCMDEND_V(e)  BF_UARTAPP_DEBUG_TXCMDEND(BV_UARTAPP_DEBUG_TXCMDEND__##e)
+#define BFM_UARTAPP_DEBUG_TXCMDEND_V(v) BM_UARTAPP_DEBUG_TXCMDEND
+#define BP_UARTAPP_DEBUG_RXCMDEND       2
+#define BM_UARTAPP_DEBUG_RXCMDEND       0x4
+#define BF_UARTAPP_DEBUG_RXCMDEND(v)    (((v) & 0x1) << 2)
+#define BFM_UARTAPP_DEBUG_RXCMDEND(v)   BM_UARTAPP_DEBUG_RXCMDEND
+#define BF_UARTAPP_DEBUG_RXCMDEND_V(e)  BF_UARTAPP_DEBUG_RXCMDEND(BV_UARTAPP_DEBUG_RXCMDEND__##e)
+#define BFM_UARTAPP_DEBUG_RXCMDEND_V(v) BM_UARTAPP_DEBUG_RXCMDEND
+#define BP_UARTAPP_DEBUG_TXDMARQ        1
+#define BM_UARTAPP_DEBUG_TXDMARQ        0x2
+#define BF_UARTAPP_DEBUG_TXDMARQ(v)     (((v) & 0x1) << 1)
+#define BFM_UARTAPP_DEBUG_TXDMARQ(v)    BM_UARTAPP_DEBUG_TXDMARQ
+#define BF_UARTAPP_DEBUG_TXDMARQ_V(e)   BF_UARTAPP_DEBUG_TXDMARQ(BV_UARTAPP_DEBUG_TXDMARQ__##e)
+#define BFM_UARTAPP_DEBUG_TXDMARQ_V(v)  BM_UARTAPP_DEBUG_TXDMARQ
+#define BP_UARTAPP_DEBUG_RXDMARQ        0
+#define BM_UARTAPP_DEBUG_RXDMARQ        0x1
+#define BF_UARTAPP_DEBUG_RXDMARQ(v)     (((v) & 0x1) << 0)
+#define BFM_UARTAPP_DEBUG_RXDMARQ(v)    BM_UARTAPP_DEBUG_RXDMARQ
+#define BF_UARTAPP_DEBUG_RXDMARQ_V(e)   BF_UARTAPP_DEBUG_RXDMARQ(BV_UARTAPP_DEBUG_RXDMARQ__##e)
+#define BFM_UARTAPP_DEBUG_RXDMARQ_V(v)  BM_UARTAPP_DEBUG_RXDMARQ
+
+#define HW_UARTAPP_VERSION(_n1)         HW(UARTAPP_VERSION(_n1))
+#define HWA_UARTAPP_VERSION(_n1)        (((_n1) == 1 ? 0x8006c000 : 0x8006e000) + 0x90)
+#define HWT_UARTAPP_VERSION(_n1)        HWIO_32_RW
+#define HWN_UARTAPP_VERSION(_n1)        UARTAPP_VERSION
+#define HWI_UARTAPP_VERSION(_n1)        (_n1)
+#define BP_UARTAPP_VERSION_MAJOR        24
+#define BM_UARTAPP_VERSION_MAJOR        0xff000000
+#define BF_UARTAPP_VERSION_MAJOR(v)     (((v) & 0xff) << 24)
+#define BFM_UARTAPP_VERSION_MAJOR(v)    BM_UARTAPP_VERSION_MAJOR
+#define BF_UARTAPP_VERSION_MAJOR_V(e)   BF_UARTAPP_VERSION_MAJOR(BV_UARTAPP_VERSION_MAJOR__##e)
+#define BFM_UARTAPP_VERSION_MAJOR_V(v)  BM_UARTAPP_VERSION_MAJOR
+#define BP_UARTAPP_VERSION_MINOR        16
+#define BM_UARTAPP_VERSION_MINOR        0xff0000
+#define BF_UARTAPP_VERSION_MINOR(v)     (((v) & 0xff) << 16)
+#define BFM_UARTAPP_VERSION_MINOR(v)    BM_UARTAPP_VERSION_MINOR
+#define BF_UARTAPP_VERSION_MINOR_V(e)   BF_UARTAPP_VERSION_MINOR(BV_UARTAPP_VERSION_MINOR__##e)
+#define BFM_UARTAPP_VERSION_MINOR_V(v)  BM_UARTAPP_VERSION_MINOR
+#define BP_UARTAPP_VERSION_STEP         0
+#define BM_UARTAPP_VERSION_STEP         0xffff
+#define BF_UARTAPP_VERSION_STEP(v)      (((v) & 0xffff) << 0)
+#define BFM_UARTAPP_VERSION_STEP(v)     BM_UARTAPP_VERSION_STEP
+#define BF_UARTAPP_VERSION_STEP_V(e)    BF_UARTAPP_VERSION_STEP(BV_UARTAPP_VERSION_STEP__##e)
+#define BFM_UARTAPP_VERSION_STEP_V(v)   BM_UARTAPP_VERSION_STEP
+
+#endif /* __HEADERGEN_STMP3700_UARTAPP_H__*/
diff --git a/firmware/target/arm/imx233/regs/stmp3700/uartdbg.h b/firmware/target/arm/imx233/regs/stmp3700/uartdbg.h
new file mode 100644
index 0000000000..112af24025
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3700/uartdbg.h
@@ -0,0 +1,817 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * stmp3700 version: 2.4.0
+ * stmp3700 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_STMP3700_UARTDBG_H__
+#define __HEADERGEN_STMP3700_UARTDBG_H__
+
+#define HW_UARTDBG_DR                   HW(UARTDBG_DR)
+#define HWA_UARTDBG_DR                  (0x80070000 + 0x0)
+#define HWT_UARTDBG_DR                  HWIO_32_RW
+#define HWN_UARTDBG_DR                  UARTDBG_DR
+#define HWI_UARTDBG_DR                  
+#define BP_UARTDBG_DR_UNAVAILABLE       16
+#define BM_UARTDBG_DR_UNAVAILABLE       0xffff0000
+#define BF_UARTDBG_DR_UNAVAILABLE(v)    (((v) & 0xffff) << 16)
+#define BFM_UARTDBG_DR_UNAVAILABLE(v)   BM_UARTDBG_DR_UNAVAILABLE
+#define BF_UARTDBG_DR_UNAVAILABLE_V(e)  BF_UARTDBG_DR_UNAVAILABLE(BV_UARTDBG_DR_UNAVAILABLE__##e)
+#define BFM_UARTDBG_DR_UNAVAILABLE_V(v) BM_UARTDBG_DR_UNAVAILABLE
+#define BP_UARTDBG_DR_RESERVED          12
+#define BM_UARTDBG_DR_RESERVED          0xf000
+#define BF_UARTDBG_DR_RESERVED(v)       (((v) & 0xf) << 12)
+#define BFM_UARTDBG_DR_RESERVED(v)      BM_UARTDBG_DR_RESERVED
+#define BF_UARTDBG_DR_RESERVED_V(e)     BF_UARTDBG_DR_RESERVED(BV_UARTDBG_DR_RESERVED__##e)
+#define BFM_UARTDBG_DR_RESERVED_V(v)    BM_UARTDBG_DR_RESERVED
+#define BP_UARTDBG_DR_OE                11
+#define BM_UARTDBG_DR_OE                0x800
+#define BF_UARTDBG_DR_OE(v)             (((v) & 0x1) << 11)
+#define BFM_UARTDBG_DR_OE(v)            BM_UARTDBG_DR_OE
+#define BF_UARTDBG_DR_OE_V(e)           BF_UARTDBG_DR_OE(BV_UARTDBG_DR_OE__##e)
+#define BFM_UARTDBG_DR_OE_V(v)          BM_UARTDBG_DR_OE
+#define BP_UARTDBG_DR_BE                10
+#define BM_UARTDBG_DR_BE                0x400
+#define BF_UARTDBG_DR_BE(v)             (((v) & 0x1) << 10)
+#define BFM_UARTDBG_DR_BE(v)            BM_UARTDBG_DR_BE
+#define BF_UARTDBG_DR_BE_V(e)           BF_UARTDBG_DR_BE(BV_UARTDBG_DR_BE__##e)
+#define BFM_UARTDBG_DR_BE_V(v)          BM_UARTDBG_DR_BE
+#define BP_UARTDBG_DR_PE                9
+#define BM_UARTDBG_DR_PE                0x200
+#define BF_UARTDBG_DR_PE(v)             (((v) & 0x1) << 9)
+#define BFM_UARTDBG_DR_PE(v)            BM_UARTDBG_DR_PE
+#define BF_UARTDBG_DR_PE_V(e)           BF_UARTDBG_DR_PE(BV_UARTDBG_DR_PE__##e)
+#define BFM_UARTDBG_DR_PE_V(v)          BM_UARTDBG_DR_PE
+#define BP_UARTDBG_DR_FE                8
+#define BM_UARTDBG_DR_FE                0x100
+#define BF_UARTDBG_DR_FE(v)             (((v) & 0x1) << 8)
+#define BFM_UARTDBG_DR_FE(v)            BM_UARTDBG_DR_FE
+#define BF_UARTDBG_DR_FE_V(e)           BF_UARTDBG_DR_FE(BV_UARTDBG_DR_FE__##e)
+#define BFM_UARTDBG_DR_FE_V(v)          BM_UARTDBG_DR_FE
+#define BP_UARTDBG_DR_DATA              0
+#define BM_UARTDBG_DR_DATA              0xff
+#define BF_UARTDBG_DR_DATA(v)           (((v) & 0xff) << 0)
+#define BFM_UARTDBG_DR_DATA(v)          BM_UARTDBG_DR_DATA
+#define BF_UARTDBG_DR_DATA_V(e)         BF_UARTDBG_DR_DATA(BV_UARTDBG_DR_DATA__##e)
+#define BFM_UARTDBG_DR_DATA_V(v)        BM_UARTDBG_DR_DATA
+
+#define HW_UARTDBG_RSR_ECR                      HW(UARTDBG_RSR_ECR)
+#define HWA_UARTDBG_RSR_ECR                     (0x80070000 + 0x4)
+#define HWT_UARTDBG_RSR_ECR                     HWIO_32_RW
+#define HWN_UARTDBG_RSR_ECR                     UARTDBG_RSR_ECR
+#define HWI_UARTDBG_RSR_ECR                     
+#define BP_UARTDBG_RSR_ECR_UNAVAILABLE          8
+#define BM_UARTDBG_RSR_ECR_UNAVAILABLE          0xffffff00
+#define BF_UARTDBG_RSR_ECR_UNAVAILABLE(v)       (((v) & 0xffffff) << 8)
+#define BFM_UARTDBG_RSR_ECR_UNAVAILABLE(v)      BM_UARTDBG_RSR_ECR_UNAVAILABLE
+#define BF_UARTDBG_RSR_ECR_UNAVAILABLE_V(e)     BF_UARTDBG_RSR_ECR_UNAVAILABLE(BV_UARTDBG_RSR_ECR_UNAVAILABLE__##e)
+#define BFM_UARTDBG_RSR_ECR_UNAVAILABLE_V(v)    BM_UARTDBG_RSR_ECR_UNAVAILABLE
+#define BP_UARTDBG_RSR_ECR_EC                   4
+#define BM_UARTDBG_RSR_ECR_EC                   0xf0
+#define BF_UARTDBG_RSR_ECR_EC(v)                (((v) & 0xf) << 4)
+#define BFM_UARTDBG_RSR_ECR_EC(v)               BM_UARTDBG_RSR_ECR_EC
+#define BF_UARTDBG_RSR_ECR_EC_V(e)              BF_UARTDBG_RSR_ECR_EC(BV_UARTDBG_RSR_ECR_EC__##e)
+#define BFM_UARTDBG_RSR_ECR_EC_V(v)             BM_UARTDBG_RSR_ECR_EC
+#define BP_UARTDBG_RSR_ECR_OE                   3
+#define BM_UARTDBG_RSR_ECR_OE                   0x8
+#define BF_UARTDBG_RSR_ECR_OE(v)                (((v) & 0x1) << 3)
+#define BFM_UARTDBG_RSR_ECR_OE(v)               BM_UARTDBG_RSR_ECR_OE
+#define BF_UARTDBG_RSR_ECR_OE_V(e)              BF_UARTDBG_RSR_ECR_OE(BV_UARTDBG_RSR_ECR_OE__##e)
+#define BFM_UARTDBG_RSR_ECR_OE_V(v)             BM_UARTDBG_RSR_ECR_OE
+#define BP_UARTDBG_RSR_ECR_BE                   2
+#define BM_UARTDBG_RSR_ECR_BE                   0x4
+#define BF_UARTDBG_RSR_ECR_BE(v)                (((v) & 0x1) << 2)
+#define BFM_UARTDBG_RSR_ECR_BE(v)               BM_UARTDBG_RSR_ECR_BE
+#define BF_UARTDBG_RSR_ECR_BE_V(e)              BF_UARTDBG_RSR_ECR_BE(BV_UARTDBG_RSR_ECR_BE__##e)
+#define BFM_UARTDBG_RSR_ECR_BE_V(v)             BM_UARTDBG_RSR_ECR_BE
+#define BP_UARTDBG_RSR_ECR_PE                   1
+#define BM_UARTDBG_RSR_ECR_PE                   0x2
+#define BF_UARTDBG_RSR_ECR_PE(v)                (((v) & 0x1) << 1)
+#define BFM_UARTDBG_RSR_ECR_PE(v)               BM_UARTDBG_RSR_ECR_PE
+#define BF_UARTDBG_RSR_ECR_PE_V(e)              BF_UARTDBG_RSR_ECR_PE(BV_UARTDBG_RSR_ECR_PE__##e)
+#define BFM_UARTDBG_RSR_ECR_PE_V(v)             BM_UARTDBG_RSR_ECR_PE
+#define BP_UARTDBG_RSR_ECR_FE                   0
+#define BM_UARTDBG_RSR_ECR_FE                   0x1
+#define BF_UARTDBG_RSR_ECR_FE(v)                (((v) & 0x1) << 0)
+#define BFM_UARTDBG_RSR_ECR_FE(v)               BM_UARTDBG_RSR_ECR_FE
+#define BF_UARTDBG_RSR_ECR_FE_V(e)              BF_UARTDBG_RSR_ECR_FE(BV_UARTDBG_RSR_ECR_FE__##e)
+#define BFM_UARTDBG_RSR_ECR_FE_V(v)             BM_UARTDBG_RSR_ECR_FE
+
+#define HW_UARTDBG_FR                   HW(UARTDBG_FR)
+#define HWA_UARTDBG_FR                  (0x80070000 + 0x18)
+#define HWT_UARTDBG_FR                  HWIO_32_RW
+#define HWN_UARTDBG_FR                  UARTDBG_FR
+#define HWI_UARTDBG_FR                  
+#define BP_UARTDBG_FR_UNAVAILABLE       16
+#define BM_UARTDBG_FR_UNAVAILABLE       0xffff0000
+#define BF_UARTDBG_FR_UNAVAILABLE(v)    (((v) & 0xffff) << 16)
+#define BFM_UARTDBG_FR_UNAVAILABLE(v)   BM_UARTDBG_FR_UNAVAILABLE
+#define BF_UARTDBG_FR_UNAVAILABLE_V(e)  BF_UARTDBG_FR_UNAVAILABLE(BV_UARTDBG_FR_UNAVAILABLE__##e)
+#define BFM_UARTDBG_FR_UNAVAILABLE_V(v) BM_UARTDBG_FR_UNAVAILABLE
+#define BP_UARTDBG_FR_RESERVED          9
+#define BM_UARTDBG_FR_RESERVED          0xfe00
+#define BF_UARTDBG_FR_RESERVED(v)       (((v) & 0x7f) << 9)
+#define BFM_UARTDBG_FR_RESERVED(v)      BM_UARTDBG_FR_RESERVED
+#define BF_UARTDBG_FR_RESERVED_V(e)     BF_UARTDBG_FR_RESERVED(BV_UARTDBG_FR_RESERVED__##e)
+#define BFM_UARTDBG_FR_RESERVED_V(v)    BM_UARTDBG_FR_RESERVED
+#define BP_UARTDBG_FR_RI                8
+#define BM_UARTDBG_FR_RI                0x100
+#define BF_UARTDBG_FR_RI(v)             (((v) & 0x1) << 8)
+#define BFM_UARTDBG_FR_RI(v)            BM_UARTDBG_FR_RI
+#define BF_UARTDBG_FR_RI_V(e)           BF_UARTDBG_FR_RI(BV_UARTDBG_FR_RI__##e)
+#define BFM_UARTDBG_FR_RI_V(v)          BM_UARTDBG_FR_RI
+#define BP_UARTDBG_FR_TXFE              7
+#define BM_UARTDBG_FR_TXFE              0x80
+#define BF_UARTDBG_FR_TXFE(v)           (((v) & 0x1) << 7)
+#define BFM_UARTDBG_FR_TXFE(v)          BM_UARTDBG_FR_TXFE
+#define BF_UARTDBG_FR_TXFE_V(e)         BF_UARTDBG_FR_TXFE(BV_UARTDBG_FR_TXFE__##e)
+#define BFM_UARTDBG_FR_TXFE_V(v)        BM_UARTDBG_FR_TXFE
+#define BP_UARTDBG_FR_RXFF              6
+#define BM_UARTDBG_FR_RXFF              0x40
+#define BF_UARTDBG_FR_RXFF(v)           (((v) & 0x1) << 6)
+#define BFM_UARTDBG_FR_RXFF(v)          BM_UARTDBG_FR_RXFF
+#define BF_UARTDBG_FR_RXFF_V(e)         BF_UARTDBG_FR_RXFF(BV_UARTDBG_FR_RXFF__##e)
+#define BFM_UARTDBG_FR_RXFF_V(v)        BM_UARTDBG_FR_RXFF
+#define BP_UARTDBG_FR_TXFF              5
+#define BM_UARTDBG_FR_TXFF              0x20
+#define BF_UARTDBG_FR_TXFF(v)           (((v) & 0x1) << 5)
+#define BFM_UARTDBG_FR_TXFF(v)          BM_UARTDBG_FR_TXFF
+#define BF_UARTDBG_FR_TXFF_V(e)         BF_UARTDBG_FR_TXFF(BV_UARTDBG_FR_TXFF__##e)
+#define BFM_UARTDBG_FR_TXFF_V(v)        BM_UARTDBG_FR_TXFF
+#define BP_UARTDBG_FR_RXFE              4
+#define BM_UARTDBG_FR_RXFE              0x10
+#define BF_UARTDBG_FR_RXFE(v)           (((v) & 0x1) << 4)
+#define BFM_UARTDBG_FR_RXFE(v)          BM_UARTDBG_FR_RXFE
+#define BF_UARTDBG_FR_RXFE_V(e)         BF_UARTDBG_FR_RXFE(BV_UARTDBG_FR_RXFE__##e)
+#define BFM_UARTDBG_FR_RXFE_V(v)        BM_UARTDBG_FR_RXFE
+#define BP_UARTDBG_FR_BUSY              3
+#define BM_UARTDBG_FR_BUSY              0x8
+#define BF_UARTDBG_FR_BUSY(v)           (((v) & 0x1) << 3)
+#define BFM_UARTDBG_FR_BUSY(v)          BM_UARTDBG_FR_BUSY
+#define BF_UARTDBG_FR_BUSY_V(e)         BF_UARTDBG_FR_BUSY(BV_UARTDBG_FR_BUSY__##e)
+#define BFM_UARTDBG_FR_BUSY_V(v)        BM_UARTDBG_FR_BUSY
+#define BP_UARTDBG_FR_DCD               2
+#define BM_UARTDBG_FR_DCD               0x4
+#define BF_UARTDBG_FR_DCD(v)            (((v) & 0x1) << 2)
+#define BFM_UARTDBG_FR_DCD(v)           BM_UARTDBG_FR_DCD
+#define BF_UARTDBG_FR_DCD_V(e)          BF_UARTDBG_FR_DCD(BV_UARTDBG_FR_DCD__##e)
+#define BFM_UARTDBG_FR_DCD_V(v)         BM_UARTDBG_FR_DCD
+#define BP_UARTDBG_FR_DSR               1
+#define BM_UARTDBG_FR_DSR               0x2
+#define BF_UARTDBG_FR_DSR(v)            (((v) & 0x1) << 1)
+#define BFM_UARTDBG_FR_DSR(v)           BM_UARTDBG_FR_DSR
+#define BF_UARTDBG_FR_DSR_V(e)          BF_UARTDBG_FR_DSR(BV_UARTDBG_FR_DSR__##e)
+#define BFM_UARTDBG_FR_DSR_V(v)         BM_UARTDBG_FR_DSR
+#define BP_UARTDBG_FR_CTS               0
+#define BM_UARTDBG_FR_CTS               0x1
+#define BF_UARTDBG_FR_CTS(v)            (((v) & 0x1) << 0)
+#define BFM_UARTDBG_FR_CTS(v)           BM_UARTDBG_FR_CTS
+#define BF_UARTDBG_FR_CTS_V(e)          BF_UARTDBG_FR_CTS(BV_UARTDBG_FR_CTS__##e)
+#define BFM_UARTDBG_FR_CTS_V(v)         BM_UARTDBG_FR_CTS
+
+#define HW_UARTDBG_ILPR                     HW(UARTDBG_ILPR)
+#define HWA_UARTDBG_ILPR                    (0x80070000 + 0x20)
+#define HWT_UARTDBG_ILPR                    HWIO_32_RW
+#define HWN_UARTDBG_ILPR                    UARTDBG_ILPR
+#define HWI_UARTDBG_ILPR                    
+#define BP_UARTDBG_ILPR_UNAVAILABLE         8
+#define BM_UARTDBG_ILPR_UNAVAILABLE         0xffffff00
+#define BF_UARTDBG_ILPR_UNAVAILABLE(v)      (((v) & 0xffffff) << 8)
+#define BFM_UARTDBG_ILPR_UNAVAILABLE(v)     BM_UARTDBG_ILPR_UNAVAILABLE
+#define BF_UARTDBG_ILPR_UNAVAILABLE_V(e)    BF_UARTDBG_ILPR_UNAVAILABLE(BV_UARTDBG_ILPR_UNAVAILABLE__##e)
+#define BFM_UARTDBG_ILPR_UNAVAILABLE_V(v)   BM_UARTDBG_ILPR_UNAVAILABLE
+#define BP_UARTDBG_ILPR_ILPDVSR             0
+#define BM_UARTDBG_ILPR_ILPDVSR             0xff
+#define BF_UARTDBG_ILPR_ILPDVSR(v)          (((v) & 0xff) << 0)
+#define BFM_UARTDBG_ILPR_ILPDVSR(v)         BM_UARTDBG_ILPR_ILPDVSR
+#define BF_UARTDBG_ILPR_ILPDVSR_V(e)        BF_UARTDBG_ILPR_ILPDVSR(BV_UARTDBG_ILPR_ILPDVSR__##e)
+#define BFM_UARTDBG_ILPR_ILPDVSR_V(v)       BM_UARTDBG_ILPR_ILPDVSR
+
+#define HW_UARTDBG_IBRD                     HW(UARTDBG_IBRD)
+#define HWA_UARTDBG_IBRD                    (0x80070000 + 0x24)
+#define HWT_UARTDBG_IBRD                    HWIO_32_RW
+#define HWN_UARTDBG_IBRD                    UARTDBG_IBRD
+#define HWI_UARTDBG_IBRD                    
+#define BP_UARTDBG_IBRD_UNAVAILABLE         16
+#define BM_UARTDBG_IBRD_UNAVAILABLE         0xffff0000
+#define BF_UARTDBG_IBRD_UNAVAILABLE(v)      (((v) & 0xffff) << 16)
+#define BFM_UARTDBG_IBRD_UNAVAILABLE(v)     BM_UARTDBG_IBRD_UNAVAILABLE
+#define BF_UARTDBG_IBRD_UNAVAILABLE_V(e)    BF_UARTDBG_IBRD_UNAVAILABLE(BV_UARTDBG_IBRD_UNAVAILABLE__##e)
+#define BFM_UARTDBG_IBRD_UNAVAILABLE_V(v)   BM_UARTDBG_IBRD_UNAVAILABLE
+#define BP_UARTDBG_IBRD_BAUD_DIVINT         0
+#define BM_UARTDBG_IBRD_BAUD_DIVINT         0xffff
+#define BF_UARTDBG_IBRD_BAUD_DIVINT(v)      (((v) & 0xffff) << 0)
+#define BFM_UARTDBG_IBRD_BAUD_DIVINT(v)     BM_UARTDBG_IBRD_BAUD_DIVINT
+#define BF_UARTDBG_IBRD_BAUD_DIVINT_V(e)    BF_UARTDBG_IBRD_BAUD_DIVINT(BV_UARTDBG_IBRD_BAUD_DIVINT__##e)
+#define BFM_UARTDBG_IBRD_BAUD_DIVINT_V(v)   BM_UARTDBG_IBRD_BAUD_DIVINT
+
+#define HW_UARTDBG_FBRD                     HW(UARTDBG_FBRD)
+#define HWA_UARTDBG_FBRD                    (0x80070000 + 0x28)
+#define HWT_UARTDBG_FBRD                    HWIO_32_RW
+#define HWN_UARTDBG_FBRD                    UARTDBG_FBRD
+#define HWI_UARTDBG_FBRD                    
+#define BP_UARTDBG_FBRD_UNAVAILABLE         8
+#define BM_UARTDBG_FBRD_UNAVAILABLE         0xffffff00
+#define BF_UARTDBG_FBRD_UNAVAILABLE(v)      (((v) & 0xffffff) << 8)
+#define BFM_UARTDBG_FBRD_UNAVAILABLE(v)     BM_UARTDBG_FBRD_UNAVAILABLE
+#define BF_UARTDBG_FBRD_UNAVAILABLE_V(e)    BF_UARTDBG_FBRD_UNAVAILABLE(BV_UARTDBG_FBRD_UNAVAILABLE__##e)
+#define BFM_UARTDBG_FBRD_UNAVAILABLE_V(v)   BM_UARTDBG_FBRD_UNAVAILABLE
+#define BP_UARTDBG_FBRD_RESERVED            6
+#define BM_UARTDBG_FBRD_RESERVED            0xc0
+#define BF_UARTDBG_FBRD_RESERVED(v)         (((v) & 0x3) << 6)
+#define BFM_UARTDBG_FBRD_RESERVED(v)        BM_UARTDBG_FBRD_RESERVED
+#define BF_UARTDBG_FBRD_RESERVED_V(e)       BF_UARTDBG_FBRD_RESERVED(BV_UARTDBG_FBRD_RESERVED__##e)
+#define BFM_UARTDBG_FBRD_RESERVED_V(v)      BM_UARTDBG_FBRD_RESERVED
+#define BP_UARTDBG_FBRD_BAUD_DIVFRAC        0
+#define BM_UARTDBG_FBRD_BAUD_DIVFRAC        0x3f
+#define BF_UARTDBG_FBRD_BAUD_DIVFRAC(v)     (((v) & 0x3f) << 0)
+#define BFM_UARTDBG_FBRD_BAUD_DIVFRAC(v)    BM_UARTDBG_FBRD_BAUD_DIVFRAC
+#define BF_UARTDBG_FBRD_BAUD_DIVFRAC_V(e)   BF_UARTDBG_FBRD_BAUD_DIVFRAC(BV_UARTDBG_FBRD_BAUD_DIVFRAC__##e)
+#define BFM_UARTDBG_FBRD_BAUD_DIVFRAC_V(v)  BM_UARTDBG_FBRD_BAUD_DIVFRAC
+
+#define HW_UARTDBG_LCR_H                    HW(UARTDBG_LCR_H)
+#define HWA_UARTDBG_LCR_H                   (0x80070000 + 0x2c)
+#define HWT_UARTDBG_LCR_H                   HWIO_32_RW
+#define HWN_UARTDBG_LCR_H                   UARTDBG_LCR_H
+#define HWI_UARTDBG_LCR_H                   
+#define BP_UARTDBG_LCR_H_UNAVAILABLE        16
+#define BM_UARTDBG_LCR_H_UNAVAILABLE        0xffff0000
+#define BF_UARTDBG_LCR_H_UNAVAILABLE(v)     (((v) & 0xffff) << 16)
+#define BFM_UARTDBG_LCR_H_UNAVAILABLE(v)    BM_UARTDBG_LCR_H_UNAVAILABLE
+#define BF_UARTDBG_LCR_H_UNAVAILABLE_V(e)   BF_UARTDBG_LCR_H_UNAVAILABLE(BV_UARTDBG_LCR_H_UNAVAILABLE__##e)
+#define BFM_UARTDBG_LCR_H_UNAVAILABLE_V(v)  BM_UARTDBG_LCR_H_UNAVAILABLE
+#define BP_UARTDBG_LCR_H_RESERVED           8
+#define BM_UARTDBG_LCR_H_RESERVED           0xff00
+#define BF_UARTDBG_LCR_H_RESERVED(v)        (((v) & 0xff) << 8)
+#define BFM_UARTDBG_LCR_H_RESERVED(v)       BM_UARTDBG_LCR_H_RESERVED
+#define BF_UARTDBG_LCR_H_RESERVED_V(e)      BF_UARTDBG_LCR_H_RESERVED(BV_UARTDBG_LCR_H_RESERVED__##e)
+#define BFM_UARTDBG_LCR_H_RESERVED_V(v)     BM_UARTDBG_LCR_H_RESERVED
+#define BP_UARTDBG_LCR_H_SPS                7
+#define BM_UARTDBG_LCR_H_SPS                0x80
+#define BF_UARTDBG_LCR_H_SPS(v)             (((v) & 0x1) << 7)
+#define BFM_UARTDBG_LCR_H_SPS(v)            BM_UARTDBG_LCR_H_SPS
+#define BF_UARTDBG_LCR_H_SPS_V(e)           BF_UARTDBG_LCR_H_SPS(BV_UARTDBG_LCR_H_SPS__##e)
+#define BFM_UARTDBG_LCR_H_SPS_V(v)          BM_UARTDBG_LCR_H_SPS
+#define BP_UARTDBG_LCR_H_WLEN               5
+#define BM_UARTDBG_LCR_H_WLEN               0x60
+#define BF_UARTDBG_LCR_H_WLEN(v)            (((v) & 0x3) << 5)
+#define BFM_UARTDBG_LCR_H_WLEN(v)           BM_UARTDBG_LCR_H_WLEN
+#define BF_UARTDBG_LCR_H_WLEN_V(e)          BF_UARTDBG_LCR_H_WLEN(BV_UARTDBG_LCR_H_WLEN__##e)
+#define BFM_UARTDBG_LCR_H_WLEN_V(v)         BM_UARTDBG_LCR_H_WLEN
+#define BP_UARTDBG_LCR_H_FEN                4
+#define BM_UARTDBG_LCR_H_FEN                0x10
+#define BF_UARTDBG_LCR_H_FEN(v)             (((v) & 0x1) << 4)
+#define BFM_UARTDBG_LCR_H_FEN(v)            BM_UARTDBG_LCR_H_FEN
+#define BF_UARTDBG_LCR_H_FEN_V(e)           BF_UARTDBG_LCR_H_FEN(BV_UARTDBG_LCR_H_FEN__##e)
+#define BFM_UARTDBG_LCR_H_FEN_V(v)          BM_UARTDBG_LCR_H_FEN
+#define BP_UARTDBG_LCR_H_STP2               3
+#define BM_UARTDBG_LCR_H_STP2               0x8
+#define BF_UARTDBG_LCR_H_STP2(v)            (((v) & 0x1) << 3)
+#define BFM_UARTDBG_LCR_H_STP2(v)           BM_UARTDBG_LCR_H_STP2
+#define BF_UARTDBG_LCR_H_STP2_V(e)          BF_UARTDBG_LCR_H_STP2(BV_UARTDBG_LCR_H_STP2__##e)
+#define BFM_UARTDBG_LCR_H_STP2_V(v)         BM_UARTDBG_LCR_H_STP2
+#define BP_UARTDBG_LCR_H_EPS                2
+#define BM_UARTDBG_LCR_H_EPS                0x4
+#define BF_UARTDBG_LCR_H_EPS(v)             (((v) & 0x1) << 2)
+#define BFM_UARTDBG_LCR_H_EPS(v)            BM_UARTDBG_LCR_H_EPS
+#define BF_UARTDBG_LCR_H_EPS_V(e)           BF_UARTDBG_LCR_H_EPS(BV_UARTDBG_LCR_H_EPS__##e)
+#define BFM_UARTDBG_LCR_H_EPS_V(v)          BM_UARTDBG_LCR_H_EPS
+#define BP_UARTDBG_LCR_H_PEN                1
+#define BM_UARTDBG_LCR_H_PEN                0x2
+#define BF_UARTDBG_LCR_H_PEN(v)             (((v) & 0x1) << 1)
+#define BFM_UARTDBG_LCR_H_PEN(v)            BM_UARTDBG_LCR_H_PEN
+#define BF_UARTDBG_LCR_H_PEN_V(e)           BF_UARTDBG_LCR_H_PEN(BV_UARTDBG_LCR_H_PEN__##e)
+#define BFM_UARTDBG_LCR_H_PEN_V(v)          BM_UARTDBG_LCR_H_PEN
+#define BP_UARTDBG_LCR_H_BRK                0
+#define BM_UARTDBG_LCR_H_BRK                0x1
+#define BF_UARTDBG_LCR_H_BRK(v)             (((v) & 0x1) << 0)
+#define BFM_UARTDBG_LCR_H_BRK(v)            BM_UARTDBG_LCR_H_BRK
+#define BF_UARTDBG_LCR_H_BRK_V(e)           BF_UARTDBG_LCR_H_BRK(BV_UARTDBG_LCR_H_BRK__##e)
+#define BFM_UARTDBG_LCR_H_BRK_V(v)          BM_UARTDBG_LCR_H_BRK
+
+#define HW_UARTDBG_CR                   HW(UARTDBG_CR)
+#define HWA_UARTDBG_CR                  (0x80070000 + 0x30)
+#define HWT_UARTDBG_CR                  HWIO_32_RW
+#define HWN_UARTDBG_CR                  UARTDBG_CR
+#define HWI_UARTDBG_CR                  
+#define BP_UARTDBG_CR_UNAVAILABLE       16
+#define BM_UARTDBG_CR_UNAVAILABLE       0xffff0000
+#define BF_UARTDBG_CR_UNAVAILABLE(v)    (((v) & 0xffff) << 16)
+#define BFM_UARTDBG_CR_UNAVAILABLE(v)   BM_UARTDBG_CR_UNAVAILABLE
+#define BF_UARTDBG_CR_UNAVAILABLE_V(e)  BF_UARTDBG_CR_UNAVAILABLE(BV_UARTDBG_CR_UNAVAILABLE__##e)
+#define BFM_UARTDBG_CR_UNAVAILABLE_V(v) BM_UARTDBG_CR_UNAVAILABLE
+#define BP_UARTDBG_CR_CTSEN             15
+#define BM_UARTDBG_CR_CTSEN             0x8000
+#define BF_UARTDBG_CR_CTSEN(v)          (((v) & 0x1) << 15)
+#define BFM_UARTDBG_CR_CTSEN(v)         BM_UARTDBG_CR_CTSEN
+#define BF_UARTDBG_CR_CTSEN_V(e)        BF_UARTDBG_CR_CTSEN(BV_UARTDBG_CR_CTSEN__##e)
+#define BFM_UARTDBG_CR_CTSEN_V(v)       BM_UARTDBG_CR_CTSEN
+#define BP_UARTDBG_CR_RTSEN             14
+#define BM_UARTDBG_CR_RTSEN             0x4000
+#define BF_UARTDBG_CR_RTSEN(v)          (((v) & 0x1) << 14)
+#define BFM_UARTDBG_CR_RTSEN(v)         BM_UARTDBG_CR_RTSEN
+#define BF_UARTDBG_CR_RTSEN_V(e)        BF_UARTDBG_CR_RTSEN(BV_UARTDBG_CR_RTSEN__##e)
+#define BFM_UARTDBG_CR_RTSEN_V(v)       BM_UARTDBG_CR_RTSEN
+#define BP_UARTDBG_CR_OUT2              13
+#define BM_UARTDBG_CR_OUT2              0x2000
+#define BF_UARTDBG_CR_OUT2(v)           (((v) & 0x1) << 13)
+#define BFM_UARTDBG_CR_OUT2(v)          BM_UARTDBG_CR_OUT2
+#define BF_UARTDBG_CR_OUT2_V(e)         BF_UARTDBG_CR_OUT2(BV_UARTDBG_CR_OUT2__##e)
+#define BFM_UARTDBG_CR_OUT2_V(v)        BM_UARTDBG_CR_OUT2
+#define BP_UARTDBG_CR_OUT1              12
+#define BM_UARTDBG_CR_OUT1              0x1000
+#define BF_UARTDBG_CR_OUT1(v)           (((v) & 0x1) << 12)
+#define BFM_UARTDBG_CR_OUT1(v)          BM_UARTDBG_CR_OUT1
+#define BF_UARTDBG_CR_OUT1_V(e)         BF_UARTDBG_CR_OUT1(BV_UARTDBG_CR_OUT1__##e)
+#define BFM_UARTDBG_CR_OUT1_V(v)        BM_UARTDBG_CR_OUT1
+#define BP_UARTDBG_CR_RTS               11
+#define BM_UARTDBG_CR_RTS               0x800
+#define BF_UARTDBG_CR_RTS(v)            (((v) & 0x1) << 11)
+#define BFM_UARTDBG_CR_RTS(v)           BM_UARTDBG_CR_RTS
+#define BF_UARTDBG_CR_RTS_V(e)          BF_UARTDBG_CR_RTS(BV_UARTDBG_CR_RTS__##e)
+#define BFM_UARTDBG_CR_RTS_V(v)         BM_UARTDBG_CR_RTS
+#define BP_UARTDBG_CR_DTR               10
+#define BM_UARTDBG_CR_DTR               0x400
+#define BF_UARTDBG_CR_DTR(v)            (((v) & 0x1) << 10)
+#define BFM_UARTDBG_CR_DTR(v)           BM_UARTDBG_CR_DTR
+#define BF_UARTDBG_CR_DTR_V(e)          BF_UARTDBG_CR_DTR(BV_UARTDBG_CR_DTR__##e)
+#define BFM_UARTDBG_CR_DTR_V(v)         BM_UARTDBG_CR_DTR
+#define BP_UARTDBG_CR_RXE               9
+#define BM_UARTDBG_CR_RXE               0x200
+#define BF_UARTDBG_CR_RXE(v)            (((v) & 0x1) << 9)
+#define BFM_UARTDBG_CR_RXE(v)           BM_UARTDBG_CR_RXE
+#define BF_UARTDBG_CR_RXE_V(e)          BF_UARTDBG_CR_RXE(BV_UARTDBG_CR_RXE__##e)
+#define BFM_UARTDBG_CR_RXE_V(v)         BM_UARTDBG_CR_RXE
+#define BP_UARTDBG_CR_TXE               8
+#define BM_UARTDBG_CR_TXE               0x100
+#define BF_UARTDBG_CR_TXE(v)            (((v) & 0x1) << 8)
+#define BFM_UARTDBG_CR_TXE(v)           BM_UARTDBG_CR_TXE
+#define BF_UARTDBG_CR_TXE_V(e)          BF_UARTDBG_CR_TXE(BV_UARTDBG_CR_TXE__##e)
+#define BFM_UARTDBG_CR_TXE_V(v)         BM_UARTDBG_CR_TXE
+#define BP_UARTDBG_CR_LBE               7
+#define BM_UARTDBG_CR_LBE               0x80
+#define BF_UARTDBG_CR_LBE(v)            (((v) & 0x1) << 7)
+#define BFM_UARTDBG_CR_LBE(v)           BM_UARTDBG_CR_LBE
+#define BF_UARTDBG_CR_LBE_V(e)          BF_UARTDBG_CR_LBE(BV_UARTDBG_CR_LBE__##e)
+#define BFM_UARTDBG_CR_LBE_V(v)         BM_UARTDBG_CR_LBE
+#define BP_UARTDBG_CR_RESERVED          3
+#define BM_UARTDBG_CR_RESERVED          0x78
+#define BF_UARTDBG_CR_RESERVED(v)       (((v) & 0xf) << 3)
+#define BFM_UARTDBG_CR_RESERVED(v)      BM_UARTDBG_CR_RESERVED
+#define BF_UARTDBG_CR_RESERVED_V(e)     BF_UARTDBG_CR_RESERVED(BV_UARTDBG_CR_RESERVED__##e)
+#define BFM_UARTDBG_CR_RESERVED_V(v)    BM_UARTDBG_CR_RESERVED
+#define BP_UARTDBG_CR_SIRLP             2
+#define BM_UARTDBG_CR_SIRLP             0x4
+#define BF_UARTDBG_CR_SIRLP(v)          (((v) & 0x1) << 2)
+#define BFM_UARTDBG_CR_SIRLP(v)         BM_UARTDBG_CR_SIRLP
+#define BF_UARTDBG_CR_SIRLP_V(e)        BF_UARTDBG_CR_SIRLP(BV_UARTDBG_CR_SIRLP__##e)
+#define BFM_UARTDBG_CR_SIRLP_V(v)       BM_UARTDBG_CR_SIRLP
+#define BP_UARTDBG_CR_SIREN             1
+#define BM_UARTDBG_CR_SIREN             0x2
+#define BF_UARTDBG_CR_SIREN(v)          (((v) & 0x1) << 1)
+#define BFM_UARTDBG_CR_SIREN(v)         BM_UARTDBG_CR_SIREN
+#define BF_UARTDBG_CR_SIREN_V(e)        BF_UARTDBG_CR_SIREN(BV_UARTDBG_CR_SIREN__##e)
+#define BFM_UARTDBG_CR_SIREN_V(v)       BM_UARTDBG_CR_SIREN
+#define BP_UARTDBG_CR_UARTEN            0
+#define BM_UARTDBG_CR_UARTEN            0x1
+#define BF_UARTDBG_CR_UARTEN(v)         (((v) & 0x1) << 0)
+#define BFM_UARTDBG_CR_UARTEN(v)        BM_UARTDBG_CR_UARTEN
+#define BF_UARTDBG_CR_UARTEN_V(e)       BF_UARTDBG_CR_UARTEN(BV_UARTDBG_CR_UARTEN__##e)
+#define BFM_UARTDBG_CR_UARTEN_V(v)      BM_UARTDBG_CR_UARTEN
+
+#define HW_UARTDBG_IFLS                             HW(UARTDBG_IFLS)
+#define HWA_UARTDBG_IFLS                            (0x80070000 + 0x34)
+#define HWT_UARTDBG_IFLS                            HWIO_32_RW
+#define HWN_UARTDBG_IFLS                            UARTDBG_IFLS
+#define HWI_UARTDBG_IFLS                            
+#define BP_UARTDBG_IFLS_UNAVAILABLE                 16
+#define BM_UARTDBG_IFLS_UNAVAILABLE                 0xffff0000
+#define BF_UARTDBG_IFLS_UNAVAILABLE(v)              (((v) & 0xffff) << 16)
+#define BFM_UARTDBG_IFLS_UNAVAILABLE(v)             BM_UARTDBG_IFLS_UNAVAILABLE
+#define BF_UARTDBG_IFLS_UNAVAILABLE_V(e)            BF_UARTDBG_IFLS_UNAVAILABLE(BV_UARTDBG_IFLS_UNAVAILABLE__##e)
+#define BFM_UARTDBG_IFLS_UNAVAILABLE_V(v)           BM_UARTDBG_IFLS_UNAVAILABLE
+#define BP_UARTDBG_IFLS_RESERVED                    6
+#define BM_UARTDBG_IFLS_RESERVED                    0xffc0
+#define BF_UARTDBG_IFLS_RESERVED(v)                 (((v) & 0x3ff) << 6)
+#define BFM_UARTDBG_IFLS_RESERVED(v)                BM_UARTDBG_IFLS_RESERVED
+#define BF_UARTDBG_IFLS_RESERVED_V(e)               BF_UARTDBG_IFLS_RESERVED(BV_UARTDBG_IFLS_RESERVED__##e)
+#define BFM_UARTDBG_IFLS_RESERVED_V(v)              BM_UARTDBG_IFLS_RESERVED
+#define BP_UARTDBG_IFLS_RXIFLSEL                    3
+#define BM_UARTDBG_IFLS_RXIFLSEL                    0x38
+#define BV_UARTDBG_IFLS_RXIFLSEL__NOT_EMPTY         0x0
+#define BV_UARTDBG_IFLS_RXIFLSEL__ONE_QUARTER       0x1
+#define BV_UARTDBG_IFLS_RXIFLSEL__ONE_HALF          0x2
+#define BV_UARTDBG_IFLS_RXIFLSEL__THREE_QUARTERS    0x3
+#define BV_UARTDBG_IFLS_RXIFLSEL__SEVEN_EIGHTHS     0x4
+#define BV_UARTDBG_IFLS_RXIFLSEL__INVALID5          0x5
+#define BV_UARTDBG_IFLS_RXIFLSEL__INVALID6          0x6
+#define BV_UARTDBG_IFLS_RXIFLSEL__INVALID7          0x7
+#define BF_UARTDBG_IFLS_RXIFLSEL(v)                 (((v) & 0x7) << 3)
+#define BFM_UARTDBG_IFLS_RXIFLSEL(v)                BM_UARTDBG_IFLS_RXIFLSEL
+#define BF_UARTDBG_IFLS_RXIFLSEL_V(e)               BF_UARTDBG_IFLS_RXIFLSEL(BV_UARTDBG_IFLS_RXIFLSEL__##e)
+#define BFM_UARTDBG_IFLS_RXIFLSEL_V(v)              BM_UARTDBG_IFLS_RXIFLSEL
+#define BP_UARTDBG_IFLS_TXIFLSEL                    0
+#define BM_UARTDBG_IFLS_TXIFLSEL                    0x7
+#define BV_UARTDBG_IFLS_TXIFLSEL__EMPTY             0x0
+#define BV_UARTDBG_IFLS_TXIFLSEL__ONE_QUARTER       0x1
+#define BV_UARTDBG_IFLS_TXIFLSEL__ONE_HALF          0x2
+#define BV_UARTDBG_IFLS_TXIFLSEL__THREE_QUARTERS    0x3
+#define BV_UARTDBG_IFLS_TXIFLSEL__SEVEN_EIGHTHS     0x4
+#define BV_UARTDBG_IFLS_TXIFLSEL__INVALID5          0x5
+#define BV_UARTDBG_IFLS_TXIFLSEL__INVALID6          0x6
+#define BV_UARTDBG_IFLS_TXIFLSEL__INVALID7          0x7
+#define BF_UARTDBG_IFLS_TXIFLSEL(v)                 (((v) & 0x7) << 0)
+#define BFM_UARTDBG_IFLS_TXIFLSEL(v)                BM_UARTDBG_IFLS_TXIFLSEL
+#define BF_UARTDBG_IFLS_TXIFLSEL_V(e)               BF_UARTDBG_IFLS_TXIFLSEL(BV_UARTDBG_IFLS_TXIFLSEL__##e)
+#define BFM_UARTDBG_IFLS_TXIFLSEL_V(v)              BM_UARTDBG_IFLS_TXIFLSEL
+
+#define HW_UARTDBG_IMSC                     HW(UARTDBG_IMSC)
+#define HWA_UARTDBG_IMSC                    (0x80070000 + 0x38)
+#define HWT_UARTDBG_IMSC                    HWIO_32_RW
+#define HWN_UARTDBG_IMSC                    UARTDBG_IMSC
+#define HWI_UARTDBG_IMSC                    
+#define BP_UARTDBG_IMSC_UNAVAILABLE         16
+#define BM_UARTDBG_IMSC_UNAVAILABLE         0xffff0000
+#define BF_UARTDBG_IMSC_UNAVAILABLE(v)      (((v) & 0xffff) << 16)
+#define BFM_UARTDBG_IMSC_UNAVAILABLE(v)     BM_UARTDBG_IMSC_UNAVAILABLE
+#define BF_UARTDBG_IMSC_UNAVAILABLE_V(e)    BF_UARTDBG_IMSC_UNAVAILABLE(BV_UARTDBG_IMSC_UNAVAILABLE__##e)
+#define BFM_UARTDBG_IMSC_UNAVAILABLE_V(v)   BM_UARTDBG_IMSC_UNAVAILABLE
+#define BP_UARTDBG_IMSC_RESERVED            11
+#define BM_UARTDBG_IMSC_RESERVED            0xf800
+#define BF_UARTDBG_IMSC_RESERVED(v)         (((v) & 0x1f) << 11)
+#define BFM_UARTDBG_IMSC_RESERVED(v)        BM_UARTDBG_IMSC_RESERVED
+#define BF_UARTDBG_IMSC_RESERVED_V(e)       BF_UARTDBG_IMSC_RESERVED(BV_UARTDBG_IMSC_RESERVED__##e)
+#define BFM_UARTDBG_IMSC_RESERVED_V(v)      BM_UARTDBG_IMSC_RESERVED
+#define BP_UARTDBG_IMSC_OEIM                10
+#define BM_UARTDBG_IMSC_OEIM                0x400
+#define BF_UARTDBG_IMSC_OEIM(v)             (((v) & 0x1) << 10)
+#define BFM_UARTDBG_IMSC_OEIM(v)            BM_UARTDBG_IMSC_OEIM
+#define BF_UARTDBG_IMSC_OEIM_V(e)           BF_UARTDBG_IMSC_OEIM(BV_UARTDBG_IMSC_OEIM__##e)
+#define BFM_UARTDBG_IMSC_OEIM_V(v)          BM_UARTDBG_IMSC_OEIM
+#define BP_UARTDBG_IMSC_BEIM                9
+#define BM_UARTDBG_IMSC_BEIM                0x200
+#define BF_UARTDBG_IMSC_BEIM(v)             (((v) & 0x1) << 9)
+#define BFM_UARTDBG_IMSC_BEIM(v)            BM_UARTDBG_IMSC_BEIM
+#define BF_UARTDBG_IMSC_BEIM_V(e)           BF_UARTDBG_IMSC_BEIM(BV_UARTDBG_IMSC_BEIM__##e)
+#define BFM_UARTDBG_IMSC_BEIM_V(v)          BM_UARTDBG_IMSC_BEIM
+#define BP_UARTDBG_IMSC_PEIM                8
+#define BM_UARTDBG_IMSC_PEIM                0x100
+#define BF_UARTDBG_IMSC_PEIM(v)             (((v) & 0x1) << 8)
+#define BFM_UARTDBG_IMSC_PEIM(v)            BM_UARTDBG_IMSC_PEIM
+#define BF_UARTDBG_IMSC_PEIM_V(e)           BF_UARTDBG_IMSC_PEIM(BV_UARTDBG_IMSC_PEIM__##e)
+#define BFM_UARTDBG_IMSC_PEIM_V(v)          BM_UARTDBG_IMSC_PEIM
+#define BP_UARTDBG_IMSC_FEIM                7
+#define BM_UARTDBG_IMSC_FEIM                0x80
+#define BF_UARTDBG_IMSC_FEIM(v)             (((v) & 0x1) << 7)
+#define BFM_UARTDBG_IMSC_FEIM(v)            BM_UARTDBG_IMSC_FEIM
+#define BF_UARTDBG_IMSC_FEIM_V(e)           BF_UARTDBG_IMSC_FEIM(BV_UARTDBG_IMSC_FEIM__##e)
+#define BFM_UARTDBG_IMSC_FEIM_V(v)          BM_UARTDBG_IMSC_FEIM
+#define BP_UARTDBG_IMSC_RTIM                6
+#define BM_UARTDBG_IMSC_RTIM                0x40
+#define BF_UARTDBG_IMSC_RTIM(v)             (((v) & 0x1) << 6)
+#define BFM_UARTDBG_IMSC_RTIM(v)            BM_UARTDBG_IMSC_RTIM
+#define BF_UARTDBG_IMSC_RTIM_V(e)           BF_UARTDBG_IMSC_RTIM(BV_UARTDBG_IMSC_RTIM__##e)
+#define BFM_UARTDBG_IMSC_RTIM_V(v)          BM_UARTDBG_IMSC_RTIM
+#define BP_UARTDBG_IMSC_TXIM                5
+#define BM_UARTDBG_IMSC_TXIM                0x20
+#define BF_UARTDBG_IMSC_TXIM(v)             (((v) & 0x1) << 5)
+#define BFM_UARTDBG_IMSC_TXIM(v)            BM_UARTDBG_IMSC_TXIM
+#define BF_UARTDBG_IMSC_TXIM_V(e)           BF_UARTDBG_IMSC_TXIM(BV_UARTDBG_IMSC_TXIM__##e)
+#define BFM_UARTDBG_IMSC_TXIM_V(v)          BM_UARTDBG_IMSC_TXIM
+#define BP_UARTDBG_IMSC_RXIM                4
+#define BM_UARTDBG_IMSC_RXIM                0x10
+#define BF_UARTDBG_IMSC_RXIM(v)             (((v) & 0x1) << 4)
+#define BFM_UARTDBG_IMSC_RXIM(v)            BM_UARTDBG_IMSC_RXIM
+#define BF_UARTDBG_IMSC_RXIM_V(e)           BF_UARTDBG_IMSC_RXIM(BV_UARTDBG_IMSC_RXIM__##e)
+#define BFM_UARTDBG_IMSC_RXIM_V(v)          BM_UARTDBG_IMSC_RXIM
+#define BP_UARTDBG_IMSC_DSRMIM              3
+#define BM_UARTDBG_IMSC_DSRMIM              0x8
+#define BF_UARTDBG_IMSC_DSRMIM(v)           (((v) & 0x1) << 3)
+#define BFM_UARTDBG_IMSC_DSRMIM(v)          BM_UARTDBG_IMSC_DSRMIM
+#define BF_UARTDBG_IMSC_DSRMIM_V(e)         BF_UARTDBG_IMSC_DSRMIM(BV_UARTDBG_IMSC_DSRMIM__##e)
+#define BFM_UARTDBG_IMSC_DSRMIM_V(v)        BM_UARTDBG_IMSC_DSRMIM
+#define BP_UARTDBG_IMSC_DCDMIM              2
+#define BM_UARTDBG_IMSC_DCDMIM              0x4
+#define BF_UARTDBG_IMSC_DCDMIM(v)           (((v) & 0x1) << 2)
+#define BFM_UARTDBG_IMSC_DCDMIM(v)          BM_UARTDBG_IMSC_DCDMIM
+#define BF_UARTDBG_IMSC_DCDMIM_V(e)         BF_UARTDBG_IMSC_DCDMIM(BV_UARTDBG_IMSC_DCDMIM__##e)
+#define BFM_UARTDBG_IMSC_DCDMIM_V(v)        BM_UARTDBG_IMSC_DCDMIM
+#define BP_UARTDBG_IMSC_CTSMIM              1
+#define BM_UARTDBG_IMSC_CTSMIM              0x2
+#define BF_UARTDBG_IMSC_CTSMIM(v)           (((v) & 0x1) << 1)
+#define BFM_UARTDBG_IMSC_CTSMIM(v)          BM_UARTDBG_IMSC_CTSMIM
+#define BF_UARTDBG_IMSC_CTSMIM_V(e)         BF_UARTDBG_IMSC_CTSMIM(BV_UARTDBG_IMSC_CTSMIM__##e)
+#define BFM_UARTDBG_IMSC_CTSMIM_V(v)        BM_UARTDBG_IMSC_CTSMIM
+#define BP_UARTDBG_IMSC_RIMIM               0
+#define BM_UARTDBG_IMSC_RIMIM               0x1
+#define BF_UARTDBG_IMSC_RIMIM(v)            (((v) & 0x1) << 0)
+#define BFM_UARTDBG_IMSC_RIMIM(v)           BM_UARTDBG_IMSC_RIMIM
+#define BF_UARTDBG_IMSC_RIMIM_V(e)          BF_UARTDBG_IMSC_RIMIM(BV_UARTDBG_IMSC_RIMIM__##e)
+#define BFM_UARTDBG_IMSC_RIMIM_V(v)         BM_UARTDBG_IMSC_RIMIM
+
+#define HW_UARTDBG_RIS                      HW(UARTDBG_RIS)
+#define HWA_UARTDBG_RIS                     (0x80070000 + 0x3c)
+#define HWT_UARTDBG_RIS                     HWIO_32_RW
+#define HWN_UARTDBG_RIS                     UARTDBG_RIS
+#define HWI_UARTDBG_RIS                     
+#define BP_UARTDBG_RIS_UNAVAILABLE          16
+#define BM_UARTDBG_RIS_UNAVAILABLE          0xffff0000
+#define BF_UARTDBG_RIS_UNAVAILABLE(v)       (((v) & 0xffff) << 16)
+#define BFM_UARTDBG_RIS_UNAVAILABLE(v)      BM_UARTDBG_RIS_UNAVAILABLE
+#define BF_UARTDBG_RIS_UNAVAILABLE_V(e)     BF_UARTDBG_RIS_UNAVAILABLE(BV_UARTDBG_RIS_UNAVAILABLE__##e)
+#define BFM_UARTDBG_RIS_UNAVAILABLE_V(v)    BM_UARTDBG_RIS_UNAVAILABLE
+#define BP_UARTDBG_RIS_RESERVED             11
+#define BM_UARTDBG_RIS_RESERVED             0xf800
+#define BF_UARTDBG_RIS_RESERVED(v)          (((v) & 0x1f) << 11)
+#define BFM_UARTDBG_RIS_RESERVED(v)         BM_UARTDBG_RIS_RESERVED
+#define BF_UARTDBG_RIS_RESERVED_V(e)        BF_UARTDBG_RIS_RESERVED(BV_UARTDBG_RIS_RESERVED__##e)
+#define BFM_UARTDBG_RIS_RESERVED_V(v)       BM_UARTDBG_RIS_RESERVED
+#define BP_UARTDBG_RIS_OERIS                10
+#define BM_UARTDBG_RIS_OERIS                0x400
+#define BF_UARTDBG_RIS_OERIS(v)             (((v) & 0x1) << 10)
+#define BFM_UARTDBG_RIS_OERIS(v)            BM_UARTDBG_RIS_OERIS
+#define BF_UARTDBG_RIS_OERIS_V(e)           BF_UARTDBG_RIS_OERIS(BV_UARTDBG_RIS_OERIS__##e)
+#define BFM_UARTDBG_RIS_OERIS_V(v)          BM_UARTDBG_RIS_OERIS
+#define BP_UARTDBG_RIS_BERIS                9
+#define BM_UARTDBG_RIS_BERIS                0x200
+#define BF_UARTDBG_RIS_BERIS(v)             (((v) & 0x1) << 9)
+#define BFM_UARTDBG_RIS_BERIS(v)            BM_UARTDBG_RIS_BERIS
+#define BF_UARTDBG_RIS_BERIS_V(e)           BF_UARTDBG_RIS_BERIS(BV_UARTDBG_RIS_BERIS__##e)
+#define BFM_UARTDBG_RIS_BERIS_V(v)          BM_UARTDBG_RIS_BERIS
+#define BP_UARTDBG_RIS_PERIS                8
+#define BM_UARTDBG_RIS_PERIS                0x100
+#define BF_UARTDBG_RIS_PERIS(v)             (((v) & 0x1) << 8)
+#define BFM_UARTDBG_RIS_PERIS(v)            BM_UARTDBG_RIS_PERIS
+#define BF_UARTDBG_RIS_PERIS_V(e)           BF_UARTDBG_RIS_PERIS(BV_UARTDBG_RIS_PERIS__##e)
+#define BFM_UARTDBG_RIS_PERIS_V(v)          BM_UARTDBG_RIS_PERIS
+#define BP_UARTDBG_RIS_FERIS                7
+#define BM_UARTDBG_RIS_FERIS                0x80
+#define BF_UARTDBG_RIS_FERIS(v)             (((v) & 0x1) << 7)
+#define BFM_UARTDBG_RIS_FERIS(v)            BM_UARTDBG_RIS_FERIS
+#define BF_UARTDBG_RIS_FERIS_V(e)           BF_UARTDBG_RIS_FERIS(BV_UARTDBG_RIS_FERIS__##e)
+#define BFM_UARTDBG_RIS_FERIS_V(v)          BM_UARTDBG_RIS_FERIS
+#define BP_UARTDBG_RIS_RTRIS                6
+#define BM_UARTDBG_RIS_RTRIS                0x40
+#define BF_UARTDBG_RIS_RTRIS(v)             (((v) & 0x1) << 6)
+#define BFM_UARTDBG_RIS_RTRIS(v)            BM_UARTDBG_RIS_RTRIS
+#define BF_UARTDBG_RIS_RTRIS_V(e)           BF_UARTDBG_RIS_RTRIS(BV_UARTDBG_RIS_RTRIS__##e)
+#define BFM_UARTDBG_RIS_RTRIS_V(v)          BM_UARTDBG_RIS_RTRIS
+#define BP_UARTDBG_RIS_TXRIS                5
+#define BM_UARTDBG_RIS_TXRIS                0x20
+#define BF_UARTDBG_RIS_TXRIS(v)             (((v) & 0x1) << 5)
+#define BFM_UARTDBG_RIS_TXRIS(v)            BM_UARTDBG_RIS_TXRIS
+#define BF_UARTDBG_RIS_TXRIS_V(e)           BF_UARTDBG_RIS_TXRIS(BV_UARTDBG_RIS_TXRIS__##e)
+#define BFM_UARTDBG_RIS_TXRIS_V(v)          BM_UARTDBG_RIS_TXRIS
+#define BP_UARTDBG_RIS_RXRIS                4
+#define BM_UARTDBG_RIS_RXRIS                0x10
+#define BF_UARTDBG_RIS_RXRIS(v)             (((v) & 0x1) << 4)
+#define BFM_UARTDBG_RIS_RXRIS(v)            BM_UARTDBG_RIS_RXRIS
+#define BF_UARTDBG_RIS_RXRIS_V(e)           BF_UARTDBG_RIS_RXRIS(BV_UARTDBG_RIS_RXRIS__##e)
+#define BFM_UARTDBG_RIS_RXRIS_V(v)          BM_UARTDBG_RIS_RXRIS
+#define BP_UARTDBG_RIS_DSRRMIS              3
+#define BM_UARTDBG_RIS_DSRRMIS              0x8
+#define BF_UARTDBG_RIS_DSRRMIS(v)           (((v) & 0x1) << 3)
+#define BFM_UARTDBG_RIS_DSRRMIS(v)          BM_UARTDBG_RIS_DSRRMIS
+#define BF_UARTDBG_RIS_DSRRMIS_V(e)         BF_UARTDBG_RIS_DSRRMIS(BV_UARTDBG_RIS_DSRRMIS__##e)
+#define BFM_UARTDBG_RIS_DSRRMIS_V(v)        BM_UARTDBG_RIS_DSRRMIS
+#define BP_UARTDBG_RIS_DCDRMIS              2
+#define BM_UARTDBG_RIS_DCDRMIS              0x4
+#define BF_UARTDBG_RIS_DCDRMIS(v)           (((v) & 0x1) << 2)
+#define BFM_UARTDBG_RIS_DCDRMIS(v)          BM_UARTDBG_RIS_DCDRMIS
+#define BF_UARTDBG_RIS_DCDRMIS_V(e)         BF_UARTDBG_RIS_DCDRMIS(BV_UARTDBG_RIS_DCDRMIS__##e)
+#define BFM_UARTDBG_RIS_DCDRMIS_V(v)        BM_UARTDBG_RIS_DCDRMIS
+#define BP_UARTDBG_RIS_CTSRMIS              1
+#define BM_UARTDBG_RIS_CTSRMIS              0x2
+#define BF_UARTDBG_RIS_CTSRMIS(v)           (((v) & 0x1) << 1)
+#define BFM_UARTDBG_RIS_CTSRMIS(v)          BM_UARTDBG_RIS_CTSRMIS
+#define BF_UARTDBG_RIS_CTSRMIS_V(e)         BF_UARTDBG_RIS_CTSRMIS(BV_UARTDBG_RIS_CTSRMIS__##e)
+#define BFM_UARTDBG_RIS_CTSRMIS_V(v)        BM_UARTDBG_RIS_CTSRMIS
+#define BP_UARTDBG_RIS_RIRMIS               0
+#define BM_UARTDBG_RIS_RIRMIS               0x1
+#define BF_UARTDBG_RIS_RIRMIS(v)            (((v) & 0x1) << 0)
+#define BFM_UARTDBG_RIS_RIRMIS(v)           BM_UARTDBG_RIS_RIRMIS
+#define BF_UARTDBG_RIS_RIRMIS_V(e)          BF_UARTDBG_RIS_RIRMIS(BV_UARTDBG_RIS_RIRMIS__##e)
+#define BFM_UARTDBG_RIS_RIRMIS_V(v)         BM_UARTDBG_RIS_RIRMIS
+
+#define HW_UARTDBG_MIS                      HW(UARTDBG_MIS)
+#define HWA_UARTDBG_MIS                     (0x80070000 + 0x40)
+#define HWT_UARTDBG_MIS                     HWIO_32_RW
+#define HWN_UARTDBG_MIS                     UARTDBG_MIS
+#define HWI_UARTDBG_MIS                     
+#define BP_UARTDBG_MIS_UNAVAILABLE          16
+#define BM_UARTDBG_MIS_UNAVAILABLE          0xffff0000
+#define BF_UARTDBG_MIS_UNAVAILABLE(v)       (((v) & 0xffff) << 16)
+#define BFM_UARTDBG_MIS_UNAVAILABLE(v)      BM_UARTDBG_MIS_UNAVAILABLE
+#define BF_UARTDBG_MIS_UNAVAILABLE_V(e)     BF_UARTDBG_MIS_UNAVAILABLE(BV_UARTDBG_MIS_UNAVAILABLE__##e)
+#define BFM_UARTDBG_MIS_UNAVAILABLE_V(v)    BM_UARTDBG_MIS_UNAVAILABLE
+#define BP_UARTDBG_MIS_RESERVED             11
+#define BM_UARTDBG_MIS_RESERVED             0xf800
+#define BF_UARTDBG_MIS_RESERVED(v)          (((v) & 0x1f) << 11)
+#define BFM_UARTDBG_MIS_RESERVED(v)         BM_UARTDBG_MIS_RESERVED
+#define BF_UARTDBG_MIS_RESERVED_V(e)        BF_UARTDBG_MIS_RESERVED(BV_UARTDBG_MIS_RESERVED__##e)
+#define BFM_UARTDBG_MIS_RESERVED_V(v)       BM_UARTDBG_MIS_RESERVED
+#define BP_UARTDBG_MIS_OEMIS                10
+#define BM_UARTDBG_MIS_OEMIS                0x400
+#define BF_UARTDBG_MIS_OEMIS(v)             (((v) & 0x1) << 10)
+#define BFM_UARTDBG_MIS_OEMIS(v)            BM_UARTDBG_MIS_OEMIS
+#define BF_UARTDBG_MIS_OEMIS_V(e)           BF_UARTDBG_MIS_OEMIS(BV_UARTDBG_MIS_OEMIS__##e)
+#define BFM_UARTDBG_MIS_OEMIS_V(v)          BM_UARTDBG_MIS_OEMIS
+#define BP_UARTDBG_MIS_BEMIS                9
+#define BM_UARTDBG_MIS_BEMIS                0x200
+#define BF_UARTDBG_MIS_BEMIS(v)             (((v) & 0x1) << 9)
+#define BFM_UARTDBG_MIS_BEMIS(v)            BM_UARTDBG_MIS_BEMIS
+#define BF_UARTDBG_MIS_BEMIS_V(e)           BF_UARTDBG_MIS_BEMIS(BV_UARTDBG_MIS_BEMIS__##e)
+#define BFM_UARTDBG_MIS_BEMIS_V(v)          BM_UARTDBG_MIS_BEMIS
+#define BP_UARTDBG_MIS_PEMIS                8
+#define BM_UARTDBG_MIS_PEMIS                0x100
+#define BF_UARTDBG_MIS_PEMIS(v)             (((v) & 0x1) << 8)
+#define BFM_UARTDBG_MIS_PEMIS(v)            BM_UARTDBG_MIS_PEMIS
+#define BF_UARTDBG_MIS_PEMIS_V(e)           BF_UARTDBG_MIS_PEMIS(BV_UARTDBG_MIS_PEMIS__##e)
+#define BFM_UARTDBG_MIS_PEMIS_V(v)          BM_UARTDBG_MIS_PEMIS
+#define BP_UARTDBG_MIS_FEMIS                7
+#define BM_UARTDBG_MIS_FEMIS                0x80
+#define BF_UARTDBG_MIS_FEMIS(v)             (((v) & 0x1) << 7)
+#define BFM_UARTDBG_MIS_FEMIS(v)            BM_UARTDBG_MIS_FEMIS
+#define BF_UARTDBG_MIS_FEMIS_V(e)           BF_UARTDBG_MIS_FEMIS(BV_UARTDBG_MIS_FEMIS__##e)
+#define BFM_UARTDBG_MIS_FEMIS_V(v)          BM_UARTDBG_MIS_FEMIS
+#define BP_UARTDBG_MIS_RTMIS                6
+#define BM_UARTDBG_MIS_RTMIS                0x40
+#define BF_UARTDBG_MIS_RTMIS(v)             (((v) & 0x1) << 6)
+#define BFM_UARTDBG_MIS_RTMIS(v)            BM_UARTDBG_MIS_RTMIS
+#define BF_UARTDBG_MIS_RTMIS_V(e)           BF_UARTDBG_MIS_RTMIS(BV_UARTDBG_MIS_RTMIS__##e)
+#define BFM_UARTDBG_MIS_RTMIS_V(v)          BM_UARTDBG_MIS_RTMIS
+#define BP_UARTDBG_MIS_TXMIS                5
+#define BM_UARTDBG_MIS_TXMIS                0x20
+#define BF_UARTDBG_MIS_TXMIS(v)             (((v) & 0x1) << 5)
+#define BFM_UARTDBG_MIS_TXMIS(v)            BM_UARTDBG_MIS_TXMIS
+#define BF_UARTDBG_MIS_TXMIS_V(e)           BF_UARTDBG_MIS_TXMIS(BV_UARTDBG_MIS_TXMIS__##e)
+#define BFM_UARTDBG_MIS_TXMIS_V(v)          BM_UARTDBG_MIS_TXMIS
+#define BP_UARTDBG_MIS_RXMIS                4
+#define BM_UARTDBG_MIS_RXMIS                0x10
+#define BF_UARTDBG_MIS_RXMIS(v)             (((v) & 0x1) << 4)
+#define BFM_UARTDBG_MIS_RXMIS(v)            BM_UARTDBG_MIS_RXMIS
+#define BF_UARTDBG_MIS_RXMIS_V(e)           BF_UARTDBG_MIS_RXMIS(BV_UARTDBG_MIS_RXMIS__##e)
+#define BFM_UARTDBG_MIS_RXMIS_V(v)          BM_UARTDBG_MIS_RXMIS
+#define BP_UARTDBG_MIS_DSRMMIS              3
+#define BM_UARTDBG_MIS_DSRMMIS              0x8
+#define BF_UARTDBG_MIS_DSRMMIS(v)           (((v) & 0x1) << 3)
+#define BFM_UARTDBG_MIS_DSRMMIS(v)          BM_UARTDBG_MIS_DSRMMIS
+#define BF_UARTDBG_MIS_DSRMMIS_V(e)         BF_UARTDBG_MIS_DSRMMIS(BV_UARTDBG_MIS_DSRMMIS__##e)
+#define BFM_UARTDBG_MIS_DSRMMIS_V(v)        BM_UARTDBG_MIS_DSRMMIS
+#define BP_UARTDBG_MIS_DCDMMIS              2
+#define BM_UARTDBG_MIS_DCDMMIS              0x4
+#define BF_UARTDBG_MIS_DCDMMIS(v)           (((v) & 0x1) << 2)
+#define BFM_UARTDBG_MIS_DCDMMIS(v)          BM_UARTDBG_MIS_DCDMMIS
+#define BF_UARTDBG_MIS_DCDMMIS_V(e)         BF_UARTDBG_MIS_DCDMMIS(BV_UARTDBG_MIS_DCDMMIS__##e)
+#define BFM_UARTDBG_MIS_DCDMMIS_V(v)        BM_UARTDBG_MIS_DCDMMIS
+#define BP_UARTDBG_MIS_CTSMMIS              1
+#define BM_UARTDBG_MIS_CTSMMIS              0x2
+#define BF_UARTDBG_MIS_CTSMMIS(v)           (((v) & 0x1) << 1)
+#define BFM_UARTDBG_MIS_CTSMMIS(v)          BM_UARTDBG_MIS_CTSMMIS
+#define BF_UARTDBG_MIS_CTSMMIS_V(e)         BF_UARTDBG_MIS_CTSMMIS(BV_UARTDBG_MIS_CTSMMIS__##e)
+#define BFM_UARTDBG_MIS_CTSMMIS_V(v)        BM_UARTDBG_MIS_CTSMMIS
+#define BP_UARTDBG_MIS_RIMMIS               0
+#define BM_UARTDBG_MIS_RIMMIS               0x1
+#define BF_UARTDBG_MIS_RIMMIS(v)            (((v) & 0x1) << 0)
+#define BFM_UARTDBG_MIS_RIMMIS(v)           BM_UARTDBG_MIS_RIMMIS
+#define BF_UARTDBG_MIS_RIMMIS_V(e)          BF_UARTDBG_MIS_RIMMIS(BV_UARTDBG_MIS_RIMMIS__##e)
+#define BFM_UARTDBG_MIS_RIMMIS_V(v)         BM_UARTDBG_MIS_RIMMIS
+
+#define HW_UARTDBG_ICR                      HW(UARTDBG_ICR)
+#define HWA_UARTDBG_ICR                     (0x80070000 + 0x44)
+#define HWT_UARTDBG_ICR                     HWIO_32_RW
+#define HWN_UARTDBG_ICR                     UARTDBG_ICR
+#define HWI_UARTDBG_ICR                     
+#define BP_UARTDBG_ICR_UNAVAILABLE          16
+#define BM_UARTDBG_ICR_UNAVAILABLE          0xffff0000
+#define BF_UARTDBG_ICR_UNAVAILABLE(v)       (((v) & 0xffff) << 16)
+#define BFM_UARTDBG_ICR_UNAVAILABLE(v)      BM_UARTDBG_ICR_UNAVAILABLE
+#define BF_UARTDBG_ICR_UNAVAILABLE_V(e)     BF_UARTDBG_ICR_UNAVAILABLE(BV_UARTDBG_ICR_UNAVAILABLE__##e)
+#define BFM_UARTDBG_ICR_UNAVAILABLE_V(v)    BM_UARTDBG_ICR_UNAVAILABLE
+#define BP_UARTDBG_ICR_RESERVED             11
+#define BM_UARTDBG_ICR_RESERVED             0xf800
+#define BF_UARTDBG_ICR_RESERVED(v)          (((v) & 0x1f) << 11)
+#define BFM_UARTDBG_ICR_RESERVED(v)         BM_UARTDBG_ICR_RESERVED
+#define BF_UARTDBG_ICR_RESERVED_V(e)        BF_UARTDBG_ICR_RESERVED(BV_UARTDBG_ICR_RESERVED__##e)
+#define BFM_UARTDBG_ICR_RESERVED_V(v)       BM_UARTDBG_ICR_RESERVED
+#define BP_UARTDBG_ICR_OEIC                 10
+#define BM_UARTDBG_ICR_OEIC                 0x400
+#define BF_UARTDBG_ICR_OEIC(v)              (((v) & 0x1) << 10)
+#define BFM_UARTDBG_ICR_OEIC(v)             BM_UARTDBG_ICR_OEIC
+#define BF_UARTDBG_ICR_OEIC_V(e)            BF_UARTDBG_ICR_OEIC(BV_UARTDBG_ICR_OEIC__##e)
+#define BFM_UARTDBG_ICR_OEIC_V(v)           BM_UARTDBG_ICR_OEIC
+#define BP_UARTDBG_ICR_BEIC                 9
+#define BM_UARTDBG_ICR_BEIC                 0x200
+#define BF_UARTDBG_ICR_BEIC(v)              (((v) & 0x1) << 9)
+#define BFM_UARTDBG_ICR_BEIC(v)             BM_UARTDBG_ICR_BEIC
+#define BF_UARTDBG_ICR_BEIC_V(e)            BF_UARTDBG_ICR_BEIC(BV_UARTDBG_ICR_BEIC__##e)
+#define BFM_UARTDBG_ICR_BEIC_V(v)           BM_UARTDBG_ICR_BEIC
+#define BP_UARTDBG_ICR_PEIC                 8
+#define BM_UARTDBG_ICR_PEIC                 0x100
+#define BF_UARTDBG_ICR_PEIC(v)              (((v) & 0x1) << 8)
+#define BFM_UARTDBG_ICR_PEIC(v)             BM_UARTDBG_ICR_PEIC
+#define BF_UARTDBG_ICR_PEIC_V(e)            BF_UARTDBG_ICR_PEIC(BV_UARTDBG_ICR_PEIC__##e)
+#define BFM_UARTDBG_ICR_PEIC_V(v)           BM_UARTDBG_ICR_PEIC
+#define BP_UARTDBG_ICR_FEIC                 7
+#define BM_UARTDBG_ICR_FEIC                 0x80
+#define BF_UARTDBG_ICR_FEIC(v)              (((v) & 0x1) << 7)
+#define BFM_UARTDBG_ICR_FEIC(v)             BM_UARTDBG_ICR_FEIC
+#define BF_UARTDBG_ICR_FEIC_V(e)            BF_UARTDBG_ICR_FEIC(BV_UARTDBG_ICR_FEIC__##e)
+#define BFM_UARTDBG_ICR_FEIC_V(v)           BM_UARTDBG_ICR_FEIC
+#define BP_UARTDBG_ICR_RTIC                 6
+#define BM_UARTDBG_ICR_RTIC                 0x40
+#define BF_UARTDBG_ICR_RTIC(v)              (((v) & 0x1) << 6)
+#define BFM_UARTDBG_ICR_RTIC(v)             BM_UARTDBG_ICR_RTIC
+#define BF_UARTDBG_ICR_RTIC_V(e)            BF_UARTDBG_ICR_RTIC(BV_UARTDBG_ICR_RTIC__##e)
+#define BFM_UARTDBG_ICR_RTIC_V(v)           BM_UARTDBG_ICR_RTIC
+#define BP_UARTDBG_ICR_TXIC                 5
+#define BM_UARTDBG_ICR_TXIC                 0x20
+#define BF_UARTDBG_ICR_TXIC(v)              (((v) & 0x1) << 5)
+#define BFM_UARTDBG_ICR_TXIC(v)             BM_UARTDBG_ICR_TXIC
+#define BF_UARTDBG_ICR_TXIC_V(e)            BF_UARTDBG_ICR_TXIC(BV_UARTDBG_ICR_TXIC__##e)
+#define BFM_UARTDBG_ICR_TXIC_V(v)           BM_UARTDBG_ICR_TXIC
+#define BP_UARTDBG_ICR_RXIC                 4
+#define BM_UARTDBG_ICR_RXIC                 0x10
+#define BF_UARTDBG_ICR_RXIC(v)              (((v) & 0x1) << 4)
+#define BFM_UARTDBG_ICR_RXIC(v)             BM_UARTDBG_ICR_RXIC
+#define BF_UARTDBG_ICR_RXIC_V(e)            BF_UARTDBG_ICR_RXIC(BV_UARTDBG_ICR_RXIC__##e)
+#define BFM_UARTDBG_ICR_RXIC_V(v)           BM_UARTDBG_ICR_RXIC
+#define BP_UARTDBG_ICR_DSRMIC               3
+#define BM_UARTDBG_ICR_DSRMIC               0x8
+#define BF_UARTDBG_ICR_DSRMIC(v)            (((v) & 0x1) << 3)
+#define BFM_UARTDBG_ICR_DSRMIC(v)           BM_UARTDBG_ICR_DSRMIC
+#define BF_UARTDBG_ICR_DSRMIC_V(e)          BF_UARTDBG_ICR_DSRMIC(BV_UARTDBG_ICR_DSRMIC__##e)
+#define BFM_UARTDBG_ICR_DSRMIC_V(v)         BM_UARTDBG_ICR_DSRMIC
+#define BP_UARTDBG_ICR_DCDMIC               2
+#define BM_UARTDBG_ICR_DCDMIC               0x4
+#define BF_UARTDBG_ICR_DCDMIC(v)            (((v) & 0x1) << 2)
+#define BFM_UARTDBG_ICR_DCDMIC(v)           BM_UARTDBG_ICR_DCDMIC
+#define BF_UARTDBG_ICR_DCDMIC_V(e)          BF_UARTDBG_ICR_DCDMIC(BV_UARTDBG_ICR_DCDMIC__##e)
+#define BFM_UARTDBG_ICR_DCDMIC_V(v)         BM_UARTDBG_ICR_DCDMIC
+#define BP_UARTDBG_ICR_CTSMIC               1
+#define BM_UARTDBG_ICR_CTSMIC               0x2
+#define BF_UARTDBG_ICR_CTSMIC(v)            (((v) & 0x1) << 1)
+#define BFM_UARTDBG_ICR_CTSMIC(v)           BM_UARTDBG_ICR_CTSMIC
+#define BF_UARTDBG_ICR_CTSMIC_V(e)          BF_UARTDBG_ICR_CTSMIC(BV_UARTDBG_ICR_CTSMIC__##e)
+#define BFM_UARTDBG_ICR_CTSMIC_V(v)         BM_UARTDBG_ICR_CTSMIC
+#define BP_UARTDBG_ICR_RIMIC                0
+#define BM_UARTDBG_ICR_RIMIC                0x1
+#define BF_UARTDBG_ICR_RIMIC(v)             (((v) & 0x1) << 0)
+#define BFM_UARTDBG_ICR_RIMIC(v)            BM_UARTDBG_ICR_RIMIC
+#define BF_UARTDBG_ICR_RIMIC_V(e)           BF_UARTDBG_ICR_RIMIC(BV_UARTDBG_ICR_RIMIC__##e)
+#define BFM_UARTDBG_ICR_RIMIC_V(v)          BM_UARTDBG_ICR_RIMIC
+
+#define HW_UARTDBG_DMACR                    HW(UARTDBG_DMACR)
+#define HWA_UARTDBG_DMACR                   (0x80070000 + 0x48)
+#define HWT_UARTDBG_DMACR                   HWIO_32_RW
+#define HWN_UARTDBG_DMACR                   UARTDBG_DMACR
+#define HWI_UARTDBG_DMACR                   
+#define BP_UARTDBG_DMACR_UNAVAILABLE        16
+#define BM_UARTDBG_DMACR_UNAVAILABLE        0xffff0000
+#define BF_UARTDBG_DMACR_UNAVAILABLE(v)     (((v) & 0xffff) << 16)
+#define BFM_UARTDBG_DMACR_UNAVAILABLE(v)    BM_UARTDBG_DMACR_UNAVAILABLE
+#define BF_UARTDBG_DMACR_UNAVAILABLE_V(e)   BF_UARTDBG_DMACR_UNAVAILABLE(BV_UARTDBG_DMACR_UNAVAILABLE__##e)
+#define BFM_UARTDBG_DMACR_UNAVAILABLE_V(v)  BM_UARTDBG_DMACR_UNAVAILABLE
+#define BP_UARTDBG_DMACR_RESERVED           3
+#define BM_UARTDBG_DMACR_RESERVED           0xfff8
+#define BF_UARTDBG_DMACR_RESERVED(v)        (((v) & 0x1fff) << 3)
+#define BFM_UARTDBG_DMACR_RESERVED(v)       BM_UARTDBG_DMACR_RESERVED
+#define BF_UARTDBG_DMACR_RESERVED_V(e)      BF_UARTDBG_DMACR_RESERVED(BV_UARTDBG_DMACR_RESERVED__##e)
+#define BFM_UARTDBG_DMACR_RESERVED_V(v)     BM_UARTDBG_DMACR_RESERVED
+#define BP_UARTDBG_DMACR_DMAONERR           2
+#define BM_UARTDBG_DMACR_DMAONERR           0x4
+#define BF_UARTDBG_DMACR_DMAONERR(v)        (((v) & 0x1) << 2)
+#define BFM_UARTDBG_DMACR_DMAONERR(v)       BM_UARTDBG_DMACR_DMAONERR
+#define BF_UARTDBG_DMACR_DMAONERR_V(e)      BF_UARTDBG_DMACR_DMAONERR(BV_UARTDBG_DMACR_DMAONERR__##e)
+#define BFM_UARTDBG_DMACR_DMAONERR_V(v)     BM_UARTDBG_DMACR_DMAONERR
+#define BP_UARTDBG_DMACR_TXDMAE             1
+#define BM_UARTDBG_DMACR_TXDMAE             0x2
+#define BF_UARTDBG_DMACR_TXDMAE(v)          (((v) & 0x1) << 1)
+#define BFM_UARTDBG_DMACR_TXDMAE(v)         BM_UARTDBG_DMACR_TXDMAE
+#define BF_UARTDBG_DMACR_TXDMAE_V(e)        BF_UARTDBG_DMACR_TXDMAE(BV_UARTDBG_DMACR_TXDMAE__##e)
+#define BFM_UARTDBG_DMACR_TXDMAE_V(v)       BM_UARTDBG_DMACR_TXDMAE
+#define BP_UARTDBG_DMACR_RXDMAE             0
+#define BM_UARTDBG_DMACR_RXDMAE             0x1
+#define BF_UARTDBG_DMACR_RXDMAE(v)          (((v) & 0x1) << 0)
+#define BFM_UARTDBG_DMACR_RXDMAE(v)         BM_UARTDBG_DMACR_RXDMAE
+#define BF_UARTDBG_DMACR_RXDMAE_V(e)        BF_UARTDBG_DMACR_RXDMAE(BV_UARTDBG_DMACR_RXDMAE__##e)
+#define BFM_UARTDBG_DMACR_RXDMAE_V(v)       BM_UARTDBG_DMACR_RXDMAE
+
+#endif /* __HEADERGEN_STMP3700_UARTDBG_H__*/
diff --git a/firmware/target/arm/imx233/regs/stmp3700/usbctrl.h b/firmware/target/arm/imx233/regs/stmp3700/usbctrl.h
new file mode 100644
index 0000000000..2470712d0a
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3700/usbctrl.h
@@ -0,0 +1,1375 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * stmp3700 version: 2.4.0
+ * stmp3700 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_STMP3700_USBCTRL_H__
+#define __HEADERGEN_STMP3700_USBCTRL_H__
+
+#define HW_USBCTRL_ID               HW(USBCTRL_ID)
+#define HWA_USBCTRL_ID              (0x80080000 + 0x0)
+#define HWT_USBCTRL_ID              HWIO_32_RW
+#define HWN_USBCTRL_ID              USBCTRL_ID
+#define HWI_USBCTRL_ID              
+#define BP_USBCTRL_ID_REV           16
+#define BM_USBCTRL_ID_REV           0xff0000
+#define BF_USBCTRL_ID_REV(v)        (((v) & 0xff) << 16)
+#define BFM_USBCTRL_ID_REV(v)       BM_USBCTRL_ID_REV
+#define BF_USBCTRL_ID_REV_V(e)      BF_USBCTRL_ID_REV(BV_USBCTRL_ID_REV__##e)
+#define BFM_USBCTRL_ID_REV_V(v)     BM_USBCTRL_ID_REV
+#define BP_USBCTRL_ID_ID_N          8
+#define BM_USBCTRL_ID_ID_N          0xff00
+#define BF_USBCTRL_ID_ID_N(v)       (((v) & 0xff) << 8)
+#define BFM_USBCTRL_ID_ID_N(v)      BM_USBCTRL_ID_ID_N
+#define BF_USBCTRL_ID_ID_N_V(e)     BF_USBCTRL_ID_ID_N(BV_USBCTRL_ID_ID_N__##e)
+#define BFM_USBCTRL_ID_ID_N_V(v)    BM_USBCTRL_ID_ID_N
+#define BP_USBCTRL_ID_ID            0
+#define BM_USBCTRL_ID_ID            0xff
+#define BF_USBCTRL_ID_ID(v)         (((v) & 0xff) << 0)
+#define BFM_USBCTRL_ID_ID(v)        BM_USBCTRL_ID_ID
+#define BF_USBCTRL_ID_ID_V(e)       BF_USBCTRL_ID_ID(BV_USBCTRL_ID_ID__##e)
+#define BFM_USBCTRL_ID_ID_V(v)      BM_USBCTRL_ID_ID
+
+#define HW_USBCTRL_GENERAL              HW(USBCTRL_GENERAL)
+#define HWA_USBCTRL_GENERAL             (0x80080000 + 0x4)
+#define HWT_USBCTRL_GENERAL             HWIO_32_RW
+#define HWN_USBCTRL_GENERAL             USBCTRL_GENERAL
+#define HWI_USBCTRL_GENERAL             
+#define BP_USBCTRL_GENERAL_SM           9
+#define BM_USBCTRL_GENERAL_SM           0x200
+#define BF_USBCTRL_GENERAL_SM(v)        (((v) & 0x1) << 9)
+#define BFM_USBCTRL_GENERAL_SM(v)       BM_USBCTRL_GENERAL_SM
+#define BF_USBCTRL_GENERAL_SM_V(e)      BF_USBCTRL_GENERAL_SM(BV_USBCTRL_GENERAL_SM__##e)
+#define BFM_USBCTRL_GENERAL_SM_V(v)     BM_USBCTRL_GENERAL_SM
+#define BP_USBCTRL_GENERAL_PHYM         6
+#define BM_USBCTRL_GENERAL_PHYM         0x1c0
+#define BF_USBCTRL_GENERAL_PHYM(v)      (((v) & 0x7) << 6)
+#define BFM_USBCTRL_GENERAL_PHYM(v)     BM_USBCTRL_GENERAL_PHYM
+#define BF_USBCTRL_GENERAL_PHYM_V(e)    BF_USBCTRL_GENERAL_PHYM(BV_USBCTRL_GENERAL_PHYM__##e)
+#define BFM_USBCTRL_GENERAL_PHYM_V(v)   BM_USBCTRL_GENERAL_PHYM
+#define BP_USBCTRL_GENERAL_PHYW         4
+#define BM_USBCTRL_GENERAL_PHYW         0x30
+#define BF_USBCTRL_GENERAL_PHYW(v)      (((v) & 0x3) << 4)
+#define BFM_USBCTRL_GENERAL_PHYW(v)     BM_USBCTRL_GENERAL_PHYW
+#define BF_USBCTRL_GENERAL_PHYW_V(e)    BF_USBCTRL_GENERAL_PHYW(BV_USBCTRL_GENERAL_PHYW__##e)
+#define BFM_USBCTRL_GENERAL_PHYW_V(v)   BM_USBCTRL_GENERAL_PHYW
+#define BP_USBCTRL_GENERAL_BWT          3
+#define BM_USBCTRL_GENERAL_BWT          0x8
+#define BF_USBCTRL_GENERAL_BWT(v)       (((v) & 0x1) << 3)
+#define BFM_USBCTRL_GENERAL_BWT(v)      BM_USBCTRL_GENERAL_BWT
+#define BF_USBCTRL_GENERAL_BWT_V(e)     BF_USBCTRL_GENERAL_BWT(BV_USBCTRL_GENERAL_BWT__##e)
+#define BFM_USBCTRL_GENERAL_BWT_V(v)    BM_USBCTRL_GENERAL_BWT
+#define BP_USBCTRL_GENERAL_CLKC         1
+#define BM_USBCTRL_GENERAL_CLKC         0x6
+#define BF_USBCTRL_GENERAL_CLKC(v)      (((v) & 0x3) << 1)
+#define BFM_USBCTRL_GENERAL_CLKC(v)     BM_USBCTRL_GENERAL_CLKC
+#define BF_USBCTRL_GENERAL_CLKC_V(e)    BF_USBCTRL_GENERAL_CLKC(BV_USBCTRL_GENERAL_CLKC__##e)
+#define BFM_USBCTRL_GENERAL_CLKC_V(v)   BM_USBCTRL_GENERAL_CLKC
+#define BP_USBCTRL_GENERAL_RT           0
+#define BM_USBCTRL_GENERAL_RT           0x1
+#define BF_USBCTRL_GENERAL_RT(v)        (((v) & 0x1) << 0)
+#define BFM_USBCTRL_GENERAL_RT(v)       BM_USBCTRL_GENERAL_RT
+#define BF_USBCTRL_GENERAL_RT_V(e)      BF_USBCTRL_GENERAL_RT(BV_USBCTRL_GENERAL_RT__##e)
+#define BFM_USBCTRL_GENERAL_RT_V(v)     BM_USBCTRL_GENERAL_RT
+
+#define HW_USBCTRL_HOST             HW(USBCTRL_HOST)
+#define HWA_USBCTRL_HOST            (0x80080000 + 0x8)
+#define HWT_USBCTRL_HOST            HWIO_32_RW
+#define HWN_USBCTRL_HOST            USBCTRL_HOST
+#define HWI_USBCTRL_HOST            
+#define BP_USBCTRL_HOST_TTPER       24
+#define BM_USBCTRL_HOST_TTPER       0xff000000
+#define BF_USBCTRL_HOST_TTPER(v)    (((v) & 0xff) << 24)
+#define BFM_USBCTRL_HOST_TTPER(v)   BM_USBCTRL_HOST_TTPER
+#define BF_USBCTRL_HOST_TTPER_V(e)  BF_USBCTRL_HOST_TTPER(BV_USBCTRL_HOST_TTPER__##e)
+#define BFM_USBCTRL_HOST_TTPER_V(v) BM_USBCTRL_HOST_TTPER
+#define BP_USBCTRL_HOST_TTASY       16
+#define BM_USBCTRL_HOST_TTASY       0xff0000
+#define BF_USBCTRL_HOST_TTASY(v)    (((v) & 0xff) << 16)
+#define BFM_USBCTRL_HOST_TTASY(v)   BM_USBCTRL_HOST_TTASY
+#define BF_USBCTRL_HOST_TTASY_V(e)  BF_USBCTRL_HOST_TTASY(BV_USBCTRL_HOST_TTASY__##e)
+#define BFM_USBCTRL_HOST_TTASY_V(v) BM_USBCTRL_HOST_TTASY
+#define BP_USBCTRL_HOST_NPORT       1
+#define BM_USBCTRL_HOST_NPORT       0xe
+#define BF_USBCTRL_HOST_NPORT(v)    (((v) & 0x7) << 1)
+#define BFM_USBCTRL_HOST_NPORT(v)   BM_USBCTRL_HOST_NPORT
+#define BF_USBCTRL_HOST_NPORT_V(e)  BF_USBCTRL_HOST_NPORT(BV_USBCTRL_HOST_NPORT__##e)
+#define BFM_USBCTRL_HOST_NPORT_V(v) BM_USBCTRL_HOST_NPORT
+#define BP_USBCTRL_HOST_HC          0
+#define BM_USBCTRL_HOST_HC          0x1
+#define BF_USBCTRL_HOST_HC(v)       (((v) & 0x1) << 0)
+#define BFM_USBCTRL_HOST_HC(v)      BM_USBCTRL_HOST_HC
+#define BF_USBCTRL_HOST_HC_V(e)     BF_USBCTRL_HOST_HC(BV_USBCTRL_HOST_HC__##e)
+#define BFM_USBCTRL_HOST_HC_V(v)    BM_USBCTRL_HOST_HC
+
+#define HW_USBCTRL_DEVICE               HW(USBCTRL_DEVICE)
+#define HWA_USBCTRL_DEVICE              (0x80080000 + 0xc)
+#define HWT_USBCTRL_DEVICE              HWIO_32_RW
+#define HWN_USBCTRL_DEVICE              USBCTRL_DEVICE
+#define HWI_USBCTRL_DEVICE              
+#define BP_USBCTRL_DEVICE_DEVEP         1
+#define BM_USBCTRL_DEVICE_DEVEP         0x3e
+#define BF_USBCTRL_DEVICE_DEVEP(v)      (((v) & 0x1f) << 1)
+#define BFM_USBCTRL_DEVICE_DEVEP(v)     BM_USBCTRL_DEVICE_DEVEP
+#define BF_USBCTRL_DEVICE_DEVEP_V(e)    BF_USBCTRL_DEVICE_DEVEP(BV_USBCTRL_DEVICE_DEVEP__##e)
+#define BFM_USBCTRL_DEVICE_DEVEP_V(v)   BM_USBCTRL_DEVICE_DEVEP
+#define BP_USBCTRL_DEVICE_DC            0
+#define BM_USBCTRL_DEVICE_DC            0x1
+#define BF_USBCTRL_DEVICE_DC(v)         (((v) & 0x1) << 0)
+#define BFM_USBCTRL_DEVICE_DC(v)        BM_USBCTRL_DEVICE_DC
+#define BF_USBCTRL_DEVICE_DC_V(e)       BF_USBCTRL_DEVICE_DC(BV_USBCTRL_DEVICE_DC__##e)
+#define BFM_USBCTRL_DEVICE_DC_V(v)      BM_USBCTRL_DEVICE_DC
+
+#define HW_USBCTRL_TXBUF                    HW(USBCTRL_TXBUF)
+#define HWA_USBCTRL_TXBUF                   (0x80080000 + 0x10)
+#define HWT_USBCTRL_TXBUF                   HWIO_32_RW
+#define HWN_USBCTRL_TXBUF                   USBCTRL_TXBUF
+#define HWI_USBCTRL_TXBUF                   
+#define BP_USBCTRL_TXBUF_TXLCR              31
+#define BM_USBCTRL_TXBUF_TXLCR              0x80000000
+#define BF_USBCTRL_TXBUF_TXLCR(v)           (((v) & 0x1) << 31)
+#define BFM_USBCTRL_TXBUF_TXLCR(v)          BM_USBCTRL_TXBUF_TXLCR
+#define BF_USBCTRL_TXBUF_TXLCR_V(e)         BF_USBCTRL_TXBUF_TXLCR(BV_USBCTRL_TXBUF_TXLCR__##e)
+#define BFM_USBCTRL_TXBUF_TXLCR_V(v)        BM_USBCTRL_TXBUF_TXLCR
+#define BP_USBCTRL_TXBUF_TXCHANADD          16
+#define BM_USBCTRL_TXBUF_TXCHANADD          0xff0000
+#define BF_USBCTRL_TXBUF_TXCHANADD(v)       (((v) & 0xff) << 16)
+#define BFM_USBCTRL_TXBUF_TXCHANADD(v)      BM_USBCTRL_TXBUF_TXCHANADD
+#define BF_USBCTRL_TXBUF_TXCHANADD_V(e)     BF_USBCTRL_TXBUF_TXCHANADD(BV_USBCTRL_TXBUF_TXCHANADD__##e)
+#define BFM_USBCTRL_TXBUF_TXCHANADD_V(v)    BM_USBCTRL_TXBUF_TXCHANADD
+#define BP_USBCTRL_TXBUF_TXADD              8
+#define BM_USBCTRL_TXBUF_TXADD              0xff00
+#define BF_USBCTRL_TXBUF_TXADD(v)           (((v) & 0xff) << 8)
+#define BFM_USBCTRL_TXBUF_TXADD(v)          BM_USBCTRL_TXBUF_TXADD
+#define BF_USBCTRL_TXBUF_TXADD_V(e)         BF_USBCTRL_TXBUF_TXADD(BV_USBCTRL_TXBUF_TXADD__##e)
+#define BFM_USBCTRL_TXBUF_TXADD_V(v)        BM_USBCTRL_TXBUF_TXADD
+#define BP_USBCTRL_TXBUF_TXBURST            0
+#define BM_USBCTRL_TXBUF_TXBURST            0xff
+#define BF_USBCTRL_TXBUF_TXBURST(v)         (((v) & 0xff) << 0)
+#define BFM_USBCTRL_TXBUF_TXBURST(v)        BM_USBCTRL_TXBUF_TXBURST
+#define BF_USBCTRL_TXBUF_TXBURST_V(e)       BF_USBCTRL_TXBUF_TXBURST(BV_USBCTRL_TXBUF_TXBURST__##e)
+#define BFM_USBCTRL_TXBUF_TXBURST_V(v)      BM_USBCTRL_TXBUF_TXBURST
+
+#define HW_USBCTRL_RXBUF                HW(USBCTRL_RXBUF)
+#define HWA_USBCTRL_RXBUF               (0x80080000 + 0x14)
+#define HWT_USBCTRL_RXBUF               HWIO_32_RW
+#define HWN_USBCTRL_RXBUF               USBCTRL_RXBUF
+#define HWI_USBCTRL_RXBUF               
+#define BP_USBCTRL_RXBUF_RXADD          8
+#define BM_USBCTRL_RXBUF_RXADD          0xff00
+#define BF_USBCTRL_RXBUF_RXADD(v)       (((v) & 0xff) << 8)
+#define BFM_USBCTRL_RXBUF_RXADD(v)      BM_USBCTRL_RXBUF_RXADD
+#define BF_USBCTRL_RXBUF_RXADD_V(e)     BF_USBCTRL_RXBUF_RXADD(BV_USBCTRL_RXBUF_RXADD__##e)
+#define BFM_USBCTRL_RXBUF_RXADD_V(v)    BM_USBCTRL_RXBUF_RXADD
+#define BP_USBCTRL_RXBUF_RXBURST        0
+#define BM_USBCTRL_RXBUF_RXBURST        0xff
+#define BF_USBCTRL_RXBUF_RXBURST(v)     (((v) & 0xff) << 0)
+#define BFM_USBCTRL_RXBUF_RXBURST(v)    BM_USBCTRL_RXBUF_RXBURST
+#define BF_USBCTRL_RXBUF_RXBURST_V(e)   BF_USBCTRL_RXBUF_RXBURST(BV_USBCTRL_RXBUF_RXBURST__##e)
+#define BFM_USBCTRL_RXBUF_RXBURST_V(v)  BM_USBCTRL_RXBUF_RXBURST
+
+#define HW_USBCTRL_TTTXBUF                  HW(USBCTRL_TTTXBUF)
+#define HWA_USBCTRL_TTTXBUF                 (0x80080000 + 0x18)
+#define HWT_USBCTRL_TTTXBUF                 HWIO_32_RW
+#define HWN_USBCTRL_TTTXBUF                 USBCTRL_TTTXBUF
+#define HWI_USBCTRL_TTTXBUF                 
+#define BP_USBCTRL_TTTXBUF_TTTXBUF          0
+#define BM_USBCTRL_TTTXBUF_TTTXBUF          0xffffffff
+#define BF_USBCTRL_TTTXBUF_TTTXBUF(v)       (((v) & 0xffffffff) << 0)
+#define BFM_USBCTRL_TTTXBUF_TTTXBUF(v)      BM_USBCTRL_TTTXBUF_TTTXBUF
+#define BF_USBCTRL_TTTXBUF_TTTXBUF_V(e)     BF_USBCTRL_TTTXBUF_TTTXBUF(BV_USBCTRL_TTTXBUF_TTTXBUF__##e)
+#define BFM_USBCTRL_TTTXBUF_TTTXBUF_V(v)    BM_USBCTRL_TTTXBUF_TTTXBUF
+
+#define HW_USBCTRL_TTRXBUF                  HW(USBCTRL_TTRXBUF)
+#define HWA_USBCTRL_TTRXBUF                 (0x80080000 + 0x1c)
+#define HWT_USBCTRL_TTRXBUF                 HWIO_32_RW
+#define HWN_USBCTRL_TTRXBUF                 USBCTRL_TTRXBUF
+#define HWI_USBCTRL_TTRXBUF                 
+#define BP_USBCTRL_TTRXBUF_TTRXBUF          0
+#define BM_USBCTRL_TTRXBUF_TTRXBUF          0xffffffff
+#define BF_USBCTRL_TTRXBUF_TTRXBUF(v)       (((v) & 0xffffffff) << 0)
+#define BFM_USBCTRL_TTRXBUF_TTRXBUF(v)      BM_USBCTRL_TTRXBUF_TTRXBUF
+#define BF_USBCTRL_TTRXBUF_TTRXBUF_V(e)     BF_USBCTRL_TTRXBUF_TTRXBUF(BV_USBCTRL_TTRXBUF_TTRXBUF__##e)
+#define BFM_USBCTRL_TTRXBUF_TTRXBUF_V(v)    BM_USBCTRL_TTRXBUF_TTRXBUF
+
+#define HW_USBCTRL_CAPLENGTH                HW(USBCTRL_CAPLENGTH)
+#define HWA_USBCTRL_CAPLENGTH               (0x80080000 + 0x100)
+#define HWT_USBCTRL_CAPLENGTH               HWIO_32_RW
+#define HWN_USBCTRL_CAPLENGTH               USBCTRL_CAPLENGTH
+#define HWI_USBCTRL_CAPLENGTH               
+#define BP_USBCTRL_CAPLENGTH_HCIVER         16
+#define BM_USBCTRL_CAPLENGTH_HCIVER         0xffff0000
+#define BF_USBCTRL_CAPLENGTH_HCIVER(v)      (((v) & 0xffff) << 16)
+#define BFM_USBCTRL_CAPLENGTH_HCIVER(v)     BM_USBCTRL_CAPLENGTH_HCIVER
+#define BF_USBCTRL_CAPLENGTH_HCIVER_V(e)    BF_USBCTRL_CAPLENGTH_HCIVER(BV_USBCTRL_CAPLENGTH_HCIVER__##e)
+#define BFM_USBCTRL_CAPLENGTH_HCIVER_V(v)   BM_USBCTRL_CAPLENGTH_HCIVER
+#define BP_USBCTRL_CAPLENGTH_LENGTH         0
+#define BM_USBCTRL_CAPLENGTH_LENGTH         0xff
+#define BF_USBCTRL_CAPLENGTH_LENGTH(v)      (((v) & 0xff) << 0)
+#define BFM_USBCTRL_CAPLENGTH_LENGTH(v)     BM_USBCTRL_CAPLENGTH_LENGTH
+#define BF_USBCTRL_CAPLENGTH_LENGTH_V(e)    BF_USBCTRL_CAPLENGTH_LENGTH(BV_USBCTRL_CAPLENGTH_LENGTH__##e)
+#define BFM_USBCTRL_CAPLENGTH_LENGTH_V(v)   BM_USBCTRL_CAPLENGTH_LENGTH
+
+#define HW_USBCTRL_HCSPARAMS                HW(USBCTRL_HCSPARAMS)
+#define HWA_USBCTRL_HCSPARAMS               (0x80080000 + 0x104)
+#define HWT_USBCTRL_HCSPARAMS               HWIO_32_RW
+#define HWN_USBCTRL_HCSPARAMS               USBCTRL_HCSPARAMS
+#define HWI_USBCTRL_HCSPARAMS               
+#define BP_USBCTRL_HCSPARAMS_NPORTS         0
+#define BM_USBCTRL_HCSPARAMS_NPORTS         0xf
+#define BF_USBCTRL_HCSPARAMS_NPORTS(v)      (((v) & 0xf) << 0)
+#define BFM_USBCTRL_HCSPARAMS_NPORTS(v)     BM_USBCTRL_HCSPARAMS_NPORTS
+#define BF_USBCTRL_HCSPARAMS_NPORTS_V(e)    BF_USBCTRL_HCSPARAMS_NPORTS(BV_USBCTRL_HCSPARAMS_NPORTS__##e)
+#define BFM_USBCTRL_HCSPARAMS_NPORTS_V(v)   BM_USBCTRL_HCSPARAMS_NPORTS
+#define BP_USBCTRL_HCSPARAMS_PPC            4
+#define BM_USBCTRL_HCSPARAMS_PPC            0x10
+#define BF_USBCTRL_HCSPARAMS_PPC(v)         (((v) & 0x1) << 4)
+#define BFM_USBCTRL_HCSPARAMS_PPC(v)        BM_USBCTRL_HCSPARAMS_PPC
+#define BF_USBCTRL_HCSPARAMS_PPC_V(e)       BF_USBCTRL_HCSPARAMS_PPC(BV_USBCTRL_HCSPARAMS_PPC__##e)
+#define BFM_USBCTRL_HCSPARAMS_PPC_V(v)      BM_USBCTRL_HCSPARAMS_PPC
+#define BP_USBCTRL_HCSPARAMS_NPCC           8
+#define BM_USBCTRL_HCSPARAMS_NPCC           0xf00
+#define BF_USBCTRL_HCSPARAMS_NPCC(v)        (((v) & 0xf) << 8)
+#define BFM_USBCTRL_HCSPARAMS_NPCC(v)       BM_USBCTRL_HCSPARAMS_NPCC
+#define BF_USBCTRL_HCSPARAMS_NPCC_V(e)      BF_USBCTRL_HCSPARAMS_NPCC(BV_USBCTRL_HCSPARAMS_NPCC__##e)
+#define BFM_USBCTRL_HCSPARAMS_NPCC_V(v)     BM_USBCTRL_HCSPARAMS_NPCC
+#define BP_USBCTRL_HCSPARAMS_NCC            12
+#define BM_USBCTRL_HCSPARAMS_NCC            0xf000
+#define BF_USBCTRL_HCSPARAMS_NCC(v)         (((v) & 0xf) << 12)
+#define BFM_USBCTRL_HCSPARAMS_NCC(v)        BM_USBCTRL_HCSPARAMS_NCC
+#define BF_USBCTRL_HCSPARAMS_NCC_V(e)       BF_USBCTRL_HCSPARAMS_NCC(BV_USBCTRL_HCSPARAMS_NCC__##e)
+#define BFM_USBCTRL_HCSPARAMS_NCC_V(v)      BM_USBCTRL_HCSPARAMS_NCC
+#define BP_USBCTRL_HCSPARAMS_PI             16
+#define BM_USBCTRL_HCSPARAMS_PI             0x10000
+#define BF_USBCTRL_HCSPARAMS_PI(v)          (((v) & 0x1) << 16)
+#define BFM_USBCTRL_HCSPARAMS_PI(v)         BM_USBCTRL_HCSPARAMS_PI
+#define BF_USBCTRL_HCSPARAMS_PI_V(e)        BF_USBCTRL_HCSPARAMS_PI(BV_USBCTRL_HCSPARAMS_PI__##e)
+#define BFM_USBCTRL_HCSPARAMS_PI_V(v)       BM_USBCTRL_HCSPARAMS_PI
+#define BP_USBCTRL_HCSPARAMS_NPTT           20
+#define BM_USBCTRL_HCSPARAMS_NPTT           0xf00000
+#define BF_USBCTRL_HCSPARAMS_NPTT(v)        (((v) & 0xf) << 20)
+#define BFM_USBCTRL_HCSPARAMS_NPTT(v)       BM_USBCTRL_HCSPARAMS_NPTT
+#define BF_USBCTRL_HCSPARAMS_NPTT_V(e)      BF_USBCTRL_HCSPARAMS_NPTT(BV_USBCTRL_HCSPARAMS_NPTT__##e)
+#define BFM_USBCTRL_HCSPARAMS_NPTT_V(v)     BM_USBCTRL_HCSPARAMS_NPTT
+#define BP_USBCTRL_HCSPARAMS_NTT            24
+#define BM_USBCTRL_HCSPARAMS_NTT            0xf000000
+#define BF_USBCTRL_HCSPARAMS_NTT(v)         (((v) & 0xf) << 24)
+#define BFM_USBCTRL_HCSPARAMS_NTT(v)        BM_USBCTRL_HCSPARAMS_NTT
+#define BF_USBCTRL_HCSPARAMS_NTT_V(e)       BF_USBCTRL_HCSPARAMS_NTT(BV_USBCTRL_HCSPARAMS_NTT__##e)
+#define BFM_USBCTRL_HCSPARAMS_NTT_V(v)      BM_USBCTRL_HCSPARAMS_NTT
+
+#define HW_USBCTRL_HCCPARAMS                            HW(USBCTRL_HCCPARAMS)
+#define HWA_USBCTRL_HCCPARAMS                           (0x80080000 + 0x108)
+#define HWT_USBCTRL_HCCPARAMS                           HWIO_32_RW
+#define HWN_USBCTRL_HCCPARAMS                           USBCTRL_HCCPARAMS
+#define HWI_USBCTRL_HCCPARAMS                           
+#define BP_USBCTRL_HCCPARAMS_ADDR64BITCAP               0
+#define BM_USBCTRL_HCCPARAMS_ADDR64BITCAP               0x1
+#define BF_USBCTRL_HCCPARAMS_ADDR64BITCAP(v)            (((v) & 0x1) << 0)
+#define BFM_USBCTRL_HCCPARAMS_ADDR64BITCAP(v)           BM_USBCTRL_HCCPARAMS_ADDR64BITCAP
+#define BF_USBCTRL_HCCPARAMS_ADDR64BITCAP_V(e)          BF_USBCTRL_HCCPARAMS_ADDR64BITCAP(BV_USBCTRL_HCCPARAMS_ADDR64BITCAP__##e)
+#define BFM_USBCTRL_HCCPARAMS_ADDR64BITCAP_V(v)         BM_USBCTRL_HCCPARAMS_ADDR64BITCAP
+#define BP_USBCTRL_HCCPARAMS_PGM_FRM_LIST_FLAG          1
+#define BM_USBCTRL_HCCPARAMS_PGM_FRM_LIST_FLAG          0x2
+#define BF_USBCTRL_HCCPARAMS_PGM_FRM_LIST_FLAG(v)       (((v) & 0x1) << 1)
+#define BFM_USBCTRL_HCCPARAMS_PGM_FRM_LIST_FLAG(v)      BM_USBCTRL_HCCPARAMS_PGM_FRM_LIST_FLAG
+#define BF_USBCTRL_HCCPARAMS_PGM_FRM_LIST_FLAG_V(e)     BF_USBCTRL_HCCPARAMS_PGM_FRM_LIST_FLAG(BV_USBCTRL_HCCPARAMS_PGM_FRM_LIST_FLAG__##e)
+#define BFM_USBCTRL_HCCPARAMS_PGM_FRM_LIST_FLAG_V(v)    BM_USBCTRL_HCCPARAMS_PGM_FRM_LIST_FLAG
+#define BP_USBCTRL_HCCPARAMS_ASYNC_PARK_CAP             2
+#define BM_USBCTRL_HCCPARAMS_ASYNC_PARK_CAP             0x4
+#define BF_USBCTRL_HCCPARAMS_ASYNC_PARK_CAP(v)          (((v) & 0x1) << 2)
+#define BFM_USBCTRL_HCCPARAMS_ASYNC_PARK_CAP(v)         BM_USBCTRL_HCCPARAMS_ASYNC_PARK_CAP
+#define BF_USBCTRL_HCCPARAMS_ASYNC_PARK_CAP_V(e)        BF_USBCTRL_HCCPARAMS_ASYNC_PARK_CAP(BV_USBCTRL_HCCPARAMS_ASYNC_PARK_CAP__##e)
+#define BFM_USBCTRL_HCCPARAMS_ASYNC_PARK_CAP_V(v)       BM_USBCTRL_HCCPARAMS_ASYNC_PARK_CAP
+#define BP_USBCTRL_HCCPARAMS_ISO_SCH_THRESHOLD          8
+#define BM_USBCTRL_HCCPARAMS_ISO_SCH_THRESHOLD          0xff00
+#define BF_USBCTRL_HCCPARAMS_ISO_SCH_THRESHOLD(v)       (((v) & 0xff) << 8)
+#define BFM_USBCTRL_HCCPARAMS_ISO_SCH_THRESHOLD(v)      BM_USBCTRL_HCCPARAMS_ISO_SCH_THRESHOLD
+#define BF_USBCTRL_HCCPARAMS_ISO_SCH_THRESHOLD_V(e)     BF_USBCTRL_HCCPARAMS_ISO_SCH_THRESHOLD(BV_USBCTRL_HCCPARAMS_ISO_SCH_THRESHOLD__##e)
+#define BFM_USBCTRL_HCCPARAMS_ISO_SCH_THRESHOLD_V(v)    BM_USBCTRL_HCCPARAMS_ISO_SCH_THRESHOLD
+
+#define HW_USBCTRL_DCIVERSION               HW(USBCTRL_DCIVERSION)
+#define HWA_USBCTRL_DCIVERSION              (0x80080000 + 0x120)
+#define HWT_USBCTRL_DCIVERSION              HWIO_32_RW
+#define HWN_USBCTRL_DCIVERSION              USBCTRL_DCIVERSION
+#define HWI_USBCTRL_DCIVERSION              
+#define BP_USBCTRL_DCIVERSION_DCIVER        0
+#define BM_USBCTRL_DCIVERSION_DCIVER        0xffff
+#define BF_USBCTRL_DCIVERSION_DCIVER(v)     (((v) & 0xffff) << 0)
+#define BFM_USBCTRL_DCIVERSION_DCIVER(v)    BM_USBCTRL_DCIVERSION_DCIVER
+#define BF_USBCTRL_DCIVERSION_DCIVER_V(e)   BF_USBCTRL_DCIVERSION_DCIVER(BV_USBCTRL_DCIVERSION_DCIVER__##e)
+#define BFM_USBCTRL_DCIVERSION_DCIVER_V(v)  BM_USBCTRL_DCIVERSION_DCIVER
+
+#define HW_USBCTRL_DCCPARAMS            HW(USBCTRL_DCCPARAMS)
+#define HWA_USBCTRL_DCCPARAMS           (0x80080000 + 0x124)
+#define HWT_USBCTRL_DCCPARAMS           HWIO_32_RW
+#define HWN_USBCTRL_DCCPARAMS           USBCTRL_DCCPARAMS
+#define HWI_USBCTRL_DCCPARAMS           
+#define BP_USBCTRL_DCCPARAMS_HC         8
+#define BM_USBCTRL_DCCPARAMS_HC         0x100
+#define BF_USBCTRL_DCCPARAMS_HC(v)      (((v) & 0x1) << 8)
+#define BFM_USBCTRL_DCCPARAMS_HC(v)     BM_USBCTRL_DCCPARAMS_HC
+#define BF_USBCTRL_DCCPARAMS_HC_V(e)    BF_USBCTRL_DCCPARAMS_HC(BV_USBCTRL_DCCPARAMS_HC__##e)
+#define BFM_USBCTRL_DCCPARAMS_HC_V(v)   BM_USBCTRL_DCCPARAMS_HC
+#define BP_USBCTRL_DCCPARAMS_DC         7
+#define BM_USBCTRL_DCCPARAMS_DC         0x80
+#define BF_USBCTRL_DCCPARAMS_DC(v)      (((v) & 0x1) << 7)
+#define BFM_USBCTRL_DCCPARAMS_DC(v)     BM_USBCTRL_DCCPARAMS_DC
+#define BF_USBCTRL_DCCPARAMS_DC_V(e)    BF_USBCTRL_DCCPARAMS_DC(BV_USBCTRL_DCCPARAMS_DC__##e)
+#define BFM_USBCTRL_DCCPARAMS_DC_V(v)   BM_USBCTRL_DCCPARAMS_DC
+#define BP_USBCTRL_DCCPARAMS_DEN        0
+#define BM_USBCTRL_DCCPARAMS_DEN        0x1f
+#define BF_USBCTRL_DCCPARAMS_DEN(v)     (((v) & 0x1f) << 0)
+#define BFM_USBCTRL_DCCPARAMS_DEN(v)    BM_USBCTRL_DCCPARAMS_DEN
+#define BF_USBCTRL_DCCPARAMS_DEN_V(e)   BF_USBCTRL_DCCPARAMS_DEN(BV_USBCTRL_DCCPARAMS_DEN__##e)
+#define BFM_USBCTRL_DCCPARAMS_DEN_V(v)  BM_USBCTRL_DCCPARAMS_DEN
+
+#define HW_USBCTRL_USBCMD               HW(USBCTRL_USBCMD)
+#define HWA_USBCTRL_USBCMD              (0x80080000 + 0x140)
+#define HWT_USBCTRL_USBCMD              HWIO_32_RW
+#define HWN_USBCTRL_USBCMD              USBCTRL_USBCMD
+#define HWI_USBCTRL_USBCMD              
+#define BP_USBCTRL_USBCMD_RS            0
+#define BM_USBCTRL_USBCMD_RS            0x1
+#define BF_USBCTRL_USBCMD_RS(v)         (((v) & 0x1) << 0)
+#define BFM_USBCTRL_USBCMD_RS(v)        BM_USBCTRL_USBCMD_RS
+#define BF_USBCTRL_USBCMD_RS_V(e)       BF_USBCTRL_USBCMD_RS(BV_USBCTRL_USBCMD_RS__##e)
+#define BFM_USBCTRL_USBCMD_RS_V(v)      BM_USBCTRL_USBCMD_RS
+#define BP_USBCTRL_USBCMD_RST           1
+#define BM_USBCTRL_USBCMD_RST           0x2
+#define BF_USBCTRL_USBCMD_RST(v)        (((v) & 0x1) << 1)
+#define BFM_USBCTRL_USBCMD_RST(v)       BM_USBCTRL_USBCMD_RST
+#define BF_USBCTRL_USBCMD_RST_V(e)      BF_USBCTRL_USBCMD_RST(BV_USBCTRL_USBCMD_RST__##e)
+#define BFM_USBCTRL_USBCMD_RST_V(v)     BM_USBCTRL_USBCMD_RST
+#define BP_USBCTRL_USBCMD_FS0           2
+#define BM_USBCTRL_USBCMD_FS0           0x4
+#define BF_USBCTRL_USBCMD_FS0(v)        (((v) & 0x1) << 2)
+#define BFM_USBCTRL_USBCMD_FS0(v)       BM_USBCTRL_USBCMD_FS0
+#define BF_USBCTRL_USBCMD_FS0_V(e)      BF_USBCTRL_USBCMD_FS0(BV_USBCTRL_USBCMD_FS0__##e)
+#define BFM_USBCTRL_USBCMD_FS0_V(v)     BM_USBCTRL_USBCMD_FS0
+#define BP_USBCTRL_USBCMD_FS1           3
+#define BM_USBCTRL_USBCMD_FS1           0x8
+#define BF_USBCTRL_USBCMD_FS1(v)        (((v) & 0x1) << 3)
+#define BFM_USBCTRL_USBCMD_FS1(v)       BM_USBCTRL_USBCMD_FS1
+#define BF_USBCTRL_USBCMD_FS1_V(e)      BF_USBCTRL_USBCMD_FS1(BV_USBCTRL_USBCMD_FS1__##e)
+#define BFM_USBCTRL_USBCMD_FS1_V(v)     BM_USBCTRL_USBCMD_FS1
+#define BP_USBCTRL_USBCMD_PSE           4
+#define BM_USBCTRL_USBCMD_PSE           0x10
+#define BF_USBCTRL_USBCMD_PSE(v)        (((v) & 0x1) << 4)
+#define BFM_USBCTRL_USBCMD_PSE(v)       BM_USBCTRL_USBCMD_PSE
+#define BF_USBCTRL_USBCMD_PSE_V(e)      BF_USBCTRL_USBCMD_PSE(BV_USBCTRL_USBCMD_PSE__##e)
+#define BFM_USBCTRL_USBCMD_PSE_V(v)     BM_USBCTRL_USBCMD_PSE
+#define BP_USBCTRL_USBCMD_ASE           5
+#define BM_USBCTRL_USBCMD_ASE           0x20
+#define BF_USBCTRL_USBCMD_ASE(v)        (((v) & 0x1) << 5)
+#define BFM_USBCTRL_USBCMD_ASE(v)       BM_USBCTRL_USBCMD_ASE
+#define BF_USBCTRL_USBCMD_ASE_V(e)      BF_USBCTRL_USBCMD_ASE(BV_USBCTRL_USBCMD_ASE__##e)
+#define BFM_USBCTRL_USBCMD_ASE_V(v)     BM_USBCTRL_USBCMD_ASE
+#define BP_USBCTRL_USBCMD_IAA           6
+#define BM_USBCTRL_USBCMD_IAA           0x40
+#define BF_USBCTRL_USBCMD_IAA(v)        (((v) & 0x1) << 6)
+#define BFM_USBCTRL_USBCMD_IAA(v)       BM_USBCTRL_USBCMD_IAA
+#define BF_USBCTRL_USBCMD_IAA_V(e)      BF_USBCTRL_USBCMD_IAA(BV_USBCTRL_USBCMD_IAA__##e)
+#define BFM_USBCTRL_USBCMD_IAA_V(v)     BM_USBCTRL_USBCMD_IAA
+#define BP_USBCTRL_USBCMD_LR            7
+#define BM_USBCTRL_USBCMD_LR            0x80
+#define BF_USBCTRL_USBCMD_LR(v)         (((v) & 0x1) << 7)
+#define BFM_USBCTRL_USBCMD_LR(v)        BM_USBCTRL_USBCMD_LR
+#define BF_USBCTRL_USBCMD_LR_V(e)       BF_USBCTRL_USBCMD_LR(BV_USBCTRL_USBCMD_LR__##e)
+#define BFM_USBCTRL_USBCMD_LR_V(v)      BM_USBCTRL_USBCMD_LR
+#define BP_USBCTRL_USBCMD_ASP0          8
+#define BM_USBCTRL_USBCMD_ASP0          0x100
+#define BF_USBCTRL_USBCMD_ASP0(v)       (((v) & 0x1) << 8)
+#define BFM_USBCTRL_USBCMD_ASP0(v)      BM_USBCTRL_USBCMD_ASP0
+#define BF_USBCTRL_USBCMD_ASP0_V(e)     BF_USBCTRL_USBCMD_ASP0(BV_USBCTRL_USBCMD_ASP0__##e)
+#define BFM_USBCTRL_USBCMD_ASP0_V(v)    BM_USBCTRL_USBCMD_ASP0
+#define BP_USBCTRL_USBCMD_ASP1          9
+#define BM_USBCTRL_USBCMD_ASP1          0x200
+#define BF_USBCTRL_USBCMD_ASP1(v)       (((v) & 0x1) << 9)
+#define BFM_USBCTRL_USBCMD_ASP1(v)      BM_USBCTRL_USBCMD_ASP1
+#define BF_USBCTRL_USBCMD_ASP1_V(e)     BF_USBCTRL_USBCMD_ASP1(BV_USBCTRL_USBCMD_ASP1__##e)
+#define BFM_USBCTRL_USBCMD_ASP1_V(v)    BM_USBCTRL_USBCMD_ASP1
+#define BP_USBCTRL_USBCMD_ASPE          11
+#define BM_USBCTRL_USBCMD_ASPE          0x800
+#define BF_USBCTRL_USBCMD_ASPE(v)       (((v) & 0x1) << 11)
+#define BFM_USBCTRL_USBCMD_ASPE(v)      BM_USBCTRL_USBCMD_ASPE
+#define BF_USBCTRL_USBCMD_ASPE_V(e)     BF_USBCTRL_USBCMD_ASPE(BV_USBCTRL_USBCMD_ASPE__##e)
+#define BFM_USBCTRL_USBCMD_ASPE_V(v)    BM_USBCTRL_USBCMD_ASPE
+#define BP_USBCTRL_USBCMD_FS2           15
+#define BM_USBCTRL_USBCMD_FS2           0x8000
+#define BF_USBCTRL_USBCMD_FS2(v)        (((v) & 0x1) << 15)
+#define BFM_USBCTRL_USBCMD_FS2(v)       BM_USBCTRL_USBCMD_FS2
+#define BF_USBCTRL_USBCMD_FS2_V(e)      BF_USBCTRL_USBCMD_FS2(BV_USBCTRL_USBCMD_FS2__##e)
+#define BFM_USBCTRL_USBCMD_FS2_V(v)     BM_USBCTRL_USBCMD_FS2
+#define BP_USBCTRL_USBCMD_ITC           16
+#define BM_USBCTRL_USBCMD_ITC           0xff0000
+#define BF_USBCTRL_USBCMD_ITC(v)        (((v) & 0xff) << 16)
+#define BFM_USBCTRL_USBCMD_ITC(v)       BM_USBCTRL_USBCMD_ITC
+#define BF_USBCTRL_USBCMD_ITC_V(e)      BF_USBCTRL_USBCMD_ITC(BV_USBCTRL_USBCMD_ITC__##e)
+#define BFM_USBCTRL_USBCMD_ITC_V(v)     BM_USBCTRL_USBCMD_ITC
+
+#define HW_USBCTRL_USBSTS               HW(USBCTRL_USBSTS)
+#define HWA_USBCTRL_USBSTS              (0x80080000 + 0x144)
+#define HWT_USBCTRL_USBSTS              HWIO_32_RW
+#define HWN_USBCTRL_USBSTS              USBCTRL_USBSTS
+#define HWI_USBCTRL_USBSTS              
+#define BP_USBCTRL_USBSTS_UI            0
+#define BM_USBCTRL_USBSTS_UI            0x1
+#define BF_USBCTRL_USBSTS_UI(v)         (((v) & 0x1) << 0)
+#define BFM_USBCTRL_USBSTS_UI(v)        BM_USBCTRL_USBSTS_UI
+#define BF_USBCTRL_USBSTS_UI_V(e)       BF_USBCTRL_USBSTS_UI(BV_USBCTRL_USBSTS_UI__##e)
+#define BFM_USBCTRL_USBSTS_UI_V(v)      BM_USBCTRL_USBSTS_UI
+#define BP_USBCTRL_USBSTS_UEI           1
+#define BM_USBCTRL_USBSTS_UEI           0x2
+#define BF_USBCTRL_USBSTS_UEI(v)        (((v) & 0x1) << 1)
+#define BFM_USBCTRL_USBSTS_UEI(v)       BM_USBCTRL_USBSTS_UEI
+#define BF_USBCTRL_USBSTS_UEI_V(e)      BF_USBCTRL_USBSTS_UEI(BV_USBCTRL_USBSTS_UEI__##e)
+#define BFM_USBCTRL_USBSTS_UEI_V(v)     BM_USBCTRL_USBSTS_UEI
+#define BP_USBCTRL_USBSTS_PCI           2
+#define BM_USBCTRL_USBSTS_PCI           0x4
+#define BF_USBCTRL_USBSTS_PCI(v)        (((v) & 0x1) << 2)
+#define BFM_USBCTRL_USBSTS_PCI(v)       BM_USBCTRL_USBSTS_PCI
+#define BF_USBCTRL_USBSTS_PCI_V(e)      BF_USBCTRL_USBSTS_PCI(BV_USBCTRL_USBSTS_PCI__##e)
+#define BFM_USBCTRL_USBSTS_PCI_V(v)     BM_USBCTRL_USBSTS_PCI
+#define BP_USBCTRL_USBSTS_FRI           3
+#define BM_USBCTRL_USBSTS_FRI           0x8
+#define BF_USBCTRL_USBSTS_FRI(v)        (((v) & 0x1) << 3)
+#define BFM_USBCTRL_USBSTS_FRI(v)       BM_USBCTRL_USBSTS_FRI
+#define BF_USBCTRL_USBSTS_FRI_V(e)      BF_USBCTRL_USBSTS_FRI(BV_USBCTRL_USBSTS_FRI__##e)
+#define BFM_USBCTRL_USBSTS_FRI_V(v)     BM_USBCTRL_USBSTS_FRI
+#define BP_USBCTRL_USBSTS_SEI           4
+#define BM_USBCTRL_USBSTS_SEI           0x10
+#define BF_USBCTRL_USBSTS_SEI(v)        (((v) & 0x1) << 4)
+#define BFM_USBCTRL_USBSTS_SEI(v)       BM_USBCTRL_USBSTS_SEI
+#define BF_USBCTRL_USBSTS_SEI_V(e)      BF_USBCTRL_USBSTS_SEI(BV_USBCTRL_USBSTS_SEI__##e)
+#define BFM_USBCTRL_USBSTS_SEI_V(v)     BM_USBCTRL_USBSTS_SEI
+#define BP_USBCTRL_USBSTS_AAI           5
+#define BM_USBCTRL_USBSTS_AAI           0x20
+#define BF_USBCTRL_USBSTS_AAI(v)        (((v) & 0x1) << 5)
+#define BFM_USBCTRL_USBSTS_AAI(v)       BM_USBCTRL_USBSTS_AAI
+#define BF_USBCTRL_USBSTS_AAI_V(e)      BF_USBCTRL_USBSTS_AAI(BV_USBCTRL_USBSTS_AAI__##e)
+#define BFM_USBCTRL_USBSTS_AAI_V(v)     BM_USBCTRL_USBSTS_AAI
+#define BP_USBCTRL_USBSTS_URI           6
+#define BM_USBCTRL_USBSTS_URI           0x40
+#define BF_USBCTRL_USBSTS_URI(v)        (((v) & 0x1) << 6)
+#define BFM_USBCTRL_USBSTS_URI(v)       BM_USBCTRL_USBSTS_URI
+#define BF_USBCTRL_USBSTS_URI_V(e)      BF_USBCTRL_USBSTS_URI(BV_USBCTRL_USBSTS_URI__##e)
+#define BFM_USBCTRL_USBSTS_URI_V(v)     BM_USBCTRL_USBSTS_URI
+#define BP_USBCTRL_USBSTS_SRI           7
+#define BM_USBCTRL_USBSTS_SRI           0x80
+#define BF_USBCTRL_USBSTS_SRI(v)        (((v) & 0x1) << 7)
+#define BFM_USBCTRL_USBSTS_SRI(v)       BM_USBCTRL_USBSTS_SRI
+#define BF_USBCTRL_USBSTS_SRI_V(e)      BF_USBCTRL_USBSTS_SRI(BV_USBCTRL_USBSTS_SRI__##e)
+#define BFM_USBCTRL_USBSTS_SRI_V(v)     BM_USBCTRL_USBSTS_SRI
+#define BP_USBCTRL_USBSTS_SLI           8
+#define BM_USBCTRL_USBSTS_SLI           0x100
+#define BF_USBCTRL_USBSTS_SLI(v)        (((v) & 0x1) << 8)
+#define BFM_USBCTRL_USBSTS_SLI(v)       BM_USBCTRL_USBSTS_SLI
+#define BF_USBCTRL_USBSTS_SLI_V(e)      BF_USBCTRL_USBSTS_SLI(BV_USBCTRL_USBSTS_SLI__##e)
+#define BFM_USBCTRL_USBSTS_SLI_V(v)     BM_USBCTRL_USBSTS_SLI
+#define BP_USBCTRL_USBSTS_ULPII         10
+#define BM_USBCTRL_USBSTS_ULPII         0x400
+#define BF_USBCTRL_USBSTS_ULPII(v)      (((v) & 0x1) << 10)
+#define BFM_USBCTRL_USBSTS_ULPII(v)     BM_USBCTRL_USBSTS_ULPII
+#define BF_USBCTRL_USBSTS_ULPII_V(e)    BF_USBCTRL_USBSTS_ULPII(BV_USBCTRL_USBSTS_ULPII__##e)
+#define BFM_USBCTRL_USBSTS_ULPII_V(v)   BM_USBCTRL_USBSTS_ULPII
+#define BP_USBCTRL_USBSTS_HCH           12
+#define BM_USBCTRL_USBSTS_HCH           0x1000
+#define BF_USBCTRL_USBSTS_HCH(v)        (((v) & 0x1) << 12)
+#define BFM_USBCTRL_USBSTS_HCH(v)       BM_USBCTRL_USBSTS_HCH
+#define BF_USBCTRL_USBSTS_HCH_V(e)      BF_USBCTRL_USBSTS_HCH(BV_USBCTRL_USBSTS_HCH__##e)
+#define BFM_USBCTRL_USBSTS_HCH_V(v)     BM_USBCTRL_USBSTS_HCH
+#define BP_USBCTRL_USBSTS_RCL           13
+#define BM_USBCTRL_USBSTS_RCL           0x2000
+#define BF_USBCTRL_USBSTS_RCL(v)        (((v) & 0x1) << 13)
+#define BFM_USBCTRL_USBSTS_RCL(v)       BM_USBCTRL_USBSTS_RCL
+#define BF_USBCTRL_USBSTS_RCL_V(e)      BF_USBCTRL_USBSTS_RCL(BV_USBCTRL_USBSTS_RCL__##e)
+#define BFM_USBCTRL_USBSTS_RCL_V(v)     BM_USBCTRL_USBSTS_RCL
+#define BP_USBCTRL_USBSTS_PS            14
+#define BM_USBCTRL_USBSTS_PS            0x4000
+#define BF_USBCTRL_USBSTS_PS(v)         (((v) & 0x1) << 14)
+#define BFM_USBCTRL_USBSTS_PS(v)        BM_USBCTRL_USBSTS_PS
+#define BF_USBCTRL_USBSTS_PS_V(e)       BF_USBCTRL_USBSTS_PS(BV_USBCTRL_USBSTS_PS__##e)
+#define BFM_USBCTRL_USBSTS_PS_V(v)      BM_USBCTRL_USBSTS_PS
+#define BP_USBCTRL_USBSTS_AS            15
+#define BM_USBCTRL_USBSTS_AS            0x8000
+#define BF_USBCTRL_USBSTS_AS(v)         (((v) & 0x1) << 15)
+#define BFM_USBCTRL_USBSTS_AS(v)        BM_USBCTRL_USBSTS_AS
+#define BF_USBCTRL_USBSTS_AS_V(e)       BF_USBCTRL_USBSTS_AS(BV_USBCTRL_USBSTS_AS__##e)
+#define BFM_USBCTRL_USBSTS_AS_V(v)      BM_USBCTRL_USBSTS_AS
+#define BP_USBCTRL_USBSTS_NAKI          16
+#define BM_USBCTRL_USBSTS_NAKI          0x10000
+#define BF_USBCTRL_USBSTS_NAKI(v)       (((v) & 0x1) << 16)
+#define BFM_USBCTRL_USBSTS_NAKI(v)      BM_USBCTRL_USBSTS_NAKI
+#define BF_USBCTRL_USBSTS_NAKI_V(e)     BF_USBCTRL_USBSTS_NAKI(BV_USBCTRL_USBSTS_NAKI__##e)
+#define BFM_USBCTRL_USBSTS_NAKI_V(v)    BM_USBCTRL_USBSTS_NAKI
+
+#define HW_USBCTRL_USBINTR              HW(USBCTRL_USBINTR)
+#define HWA_USBCTRL_USBINTR             (0x80080000 + 0x148)
+#define HWT_USBCTRL_USBINTR             HWIO_32_RW
+#define HWN_USBCTRL_USBINTR             USBCTRL_USBINTR
+#define HWI_USBCTRL_USBINTR             
+#define BP_USBCTRL_USBINTR_UE           0
+#define BM_USBCTRL_USBINTR_UE           0x1
+#define BF_USBCTRL_USBINTR_UE(v)        (((v) & 0x1) << 0)
+#define BFM_USBCTRL_USBINTR_UE(v)       BM_USBCTRL_USBINTR_UE
+#define BF_USBCTRL_USBINTR_UE_V(e)      BF_USBCTRL_USBINTR_UE(BV_USBCTRL_USBINTR_UE__##e)
+#define BFM_USBCTRL_USBINTR_UE_V(v)     BM_USBCTRL_USBINTR_UE
+#define BP_USBCTRL_USBINTR_UEE          1
+#define BM_USBCTRL_USBINTR_UEE          0x2
+#define BF_USBCTRL_USBINTR_UEE(v)       (((v) & 0x1) << 1)
+#define BFM_USBCTRL_USBINTR_UEE(v)      BM_USBCTRL_USBINTR_UEE
+#define BF_USBCTRL_USBINTR_UEE_V(e)     BF_USBCTRL_USBINTR_UEE(BV_USBCTRL_USBINTR_UEE__##e)
+#define BFM_USBCTRL_USBINTR_UEE_V(v)    BM_USBCTRL_USBINTR_UEE
+#define BP_USBCTRL_USBINTR_PCE          2
+#define BM_USBCTRL_USBINTR_PCE          0x4
+#define BF_USBCTRL_USBINTR_PCE(v)       (((v) & 0x1) << 2)
+#define BFM_USBCTRL_USBINTR_PCE(v)      BM_USBCTRL_USBINTR_PCE
+#define BF_USBCTRL_USBINTR_PCE_V(e)     BF_USBCTRL_USBINTR_PCE(BV_USBCTRL_USBINTR_PCE__##e)
+#define BFM_USBCTRL_USBINTR_PCE_V(v)    BM_USBCTRL_USBINTR_PCE
+#define BP_USBCTRL_USBINTR_FRE          3
+#define BM_USBCTRL_USBINTR_FRE          0x8
+#define BF_USBCTRL_USBINTR_FRE(v)       (((v) & 0x1) << 3)
+#define BFM_USBCTRL_USBINTR_FRE(v)      BM_USBCTRL_USBINTR_FRE
+#define BF_USBCTRL_USBINTR_FRE_V(e)     BF_USBCTRL_USBINTR_FRE(BV_USBCTRL_USBINTR_FRE__##e)
+#define BFM_USBCTRL_USBINTR_FRE_V(v)    BM_USBCTRL_USBINTR_FRE
+#define BP_USBCTRL_USBINTR_SEE          4
+#define BM_USBCTRL_USBINTR_SEE          0x10
+#define BF_USBCTRL_USBINTR_SEE(v)       (((v) & 0x1) << 4)
+#define BFM_USBCTRL_USBINTR_SEE(v)      BM_USBCTRL_USBINTR_SEE
+#define BF_USBCTRL_USBINTR_SEE_V(e)     BF_USBCTRL_USBINTR_SEE(BV_USBCTRL_USBINTR_SEE__##e)
+#define BFM_USBCTRL_USBINTR_SEE_V(v)    BM_USBCTRL_USBINTR_SEE
+#define BP_USBCTRL_USBINTR_AAE          5
+#define BM_USBCTRL_USBINTR_AAE          0x20
+#define BF_USBCTRL_USBINTR_AAE(v)       (((v) & 0x1) << 5)
+#define BFM_USBCTRL_USBINTR_AAE(v)      BM_USBCTRL_USBINTR_AAE
+#define BF_USBCTRL_USBINTR_AAE_V(e)     BF_USBCTRL_USBINTR_AAE(BV_USBCTRL_USBINTR_AAE__##e)
+#define BFM_USBCTRL_USBINTR_AAE_V(v)    BM_USBCTRL_USBINTR_AAE
+#define BP_USBCTRL_USBINTR_URE          6
+#define BM_USBCTRL_USBINTR_URE          0x40
+#define BF_USBCTRL_USBINTR_URE(v)       (((v) & 0x1) << 6)
+#define BFM_USBCTRL_USBINTR_URE(v)      BM_USBCTRL_USBINTR_URE
+#define BF_USBCTRL_USBINTR_URE_V(e)     BF_USBCTRL_USBINTR_URE(BV_USBCTRL_USBINTR_URE__##e)
+#define BFM_USBCTRL_USBINTR_URE_V(v)    BM_USBCTRL_USBINTR_URE
+#define BP_USBCTRL_USBINTR_SRE          7
+#define BM_USBCTRL_USBINTR_SRE          0x80
+#define BF_USBCTRL_USBINTR_SRE(v)       (((v) & 0x1) << 7)
+#define BFM_USBCTRL_USBINTR_SRE(v)      BM_USBCTRL_USBINTR_SRE
+#define BF_USBCTRL_USBINTR_SRE_V(e)     BF_USBCTRL_USBINTR_SRE(BV_USBCTRL_USBINTR_SRE__##e)
+#define BFM_USBCTRL_USBINTR_SRE_V(v)    BM_USBCTRL_USBINTR_SRE
+#define BP_USBCTRL_USBINTR_SLE          8
+#define BM_USBCTRL_USBINTR_SLE          0x100
+#define BF_USBCTRL_USBINTR_SLE(v)       (((v) & 0x1) << 8)
+#define BFM_USBCTRL_USBINTR_SLE(v)      BM_USBCTRL_USBINTR_SLE
+#define BF_USBCTRL_USBINTR_SLE_V(e)     BF_USBCTRL_USBINTR_SLE(BV_USBCTRL_USBINTR_SLE__##e)
+#define BFM_USBCTRL_USBINTR_SLE_V(v)    BM_USBCTRL_USBINTR_SLE
+#define BP_USBCTRL_USBINTR_ULPIE        10
+#define BM_USBCTRL_USBINTR_ULPIE        0x400
+#define BF_USBCTRL_USBINTR_ULPIE(v)     (((v) & 0x1) << 10)
+#define BFM_USBCTRL_USBINTR_ULPIE(v)    BM_USBCTRL_USBINTR_ULPIE
+#define BF_USBCTRL_USBINTR_ULPIE_V(e)   BF_USBCTRL_USBINTR_ULPIE(BV_USBCTRL_USBINTR_ULPIE__##e)
+#define BFM_USBCTRL_USBINTR_ULPIE_V(v)  BM_USBCTRL_USBINTR_ULPIE
+#define BP_USBCTRL_USBINTR_NAKE         16
+#define BM_USBCTRL_USBINTR_NAKE         0x10000
+#define BF_USBCTRL_USBINTR_NAKE(v)      (((v) & 0x1) << 16)
+#define BFM_USBCTRL_USBINTR_NAKE(v)     BM_USBCTRL_USBINTR_NAKE
+#define BF_USBCTRL_USBINTR_NAKE_V(e)    BF_USBCTRL_USBINTR_NAKE(BV_USBCTRL_USBINTR_NAKE__##e)
+#define BFM_USBCTRL_USBINTR_NAKE_V(v)   BM_USBCTRL_USBINTR_NAKE
+
+#define HW_USBCTRL_FRINDEX                  HW(USBCTRL_FRINDEX)
+#define HWA_USBCTRL_FRINDEX                 (0x80080000 + 0x14c)
+#define HWT_USBCTRL_FRINDEX                 HWIO_32_RW
+#define HWN_USBCTRL_FRINDEX                 USBCTRL_FRINDEX
+#define HWI_USBCTRL_FRINDEX                 
+#define BP_USBCTRL_FRINDEX_LISTINDEX        3
+#define BM_USBCTRL_FRINDEX_LISTINDEX        0x3ff8
+#define BF_USBCTRL_FRINDEX_LISTINDEX(v)     (((v) & 0x7ff) << 3)
+#define BFM_USBCTRL_FRINDEX_LISTINDEX(v)    BM_USBCTRL_FRINDEX_LISTINDEX
+#define BF_USBCTRL_FRINDEX_LISTINDEX_V(e)   BF_USBCTRL_FRINDEX_LISTINDEX(BV_USBCTRL_FRINDEX_LISTINDEX__##e)
+#define BFM_USBCTRL_FRINDEX_LISTINDEX_V(v)  BM_USBCTRL_FRINDEX_LISTINDEX
+#define BP_USBCTRL_FRINDEX_UINDEX           0
+#define BM_USBCTRL_FRINDEX_UINDEX           0x7
+#define BF_USBCTRL_FRINDEX_UINDEX(v)        (((v) & 0x7) << 0)
+#define BFM_USBCTRL_FRINDEX_UINDEX(v)       BM_USBCTRL_FRINDEX_UINDEX
+#define BF_USBCTRL_FRINDEX_UINDEX_V(e)      BF_USBCTRL_FRINDEX_UINDEX(BV_USBCTRL_FRINDEX_UINDEX__##e)
+#define BFM_USBCTRL_FRINDEX_UINDEX_V(v)     BM_USBCTRL_FRINDEX_UINDEX
+
+#define HW_USBCTRL_CTRLDSSEGMENT                HW(USBCTRL_CTRLDSSEGMENT)
+#define HWA_USBCTRL_CTRLDSSEGMENT               (0x80080000 + 0x150)
+#define HWT_USBCTRL_CTRLDSSEGMENT               HWIO_32_RW
+#define HWN_USBCTRL_CTRLDSSEGMENT               USBCTRL_CTRLDSSEGMENT
+#define HWI_USBCTRL_CTRLDSSEGMENT               
+#define BP_USBCTRL_CTRLDSSEGMENT_EMPTY          0
+#define BM_USBCTRL_CTRLDSSEGMENT_EMPTY          0xffffffff
+#define BF_USBCTRL_CTRLDSSEGMENT_EMPTY(v)       (((v) & 0xffffffff) << 0)
+#define BFM_USBCTRL_CTRLDSSEGMENT_EMPTY(v)      BM_USBCTRL_CTRLDSSEGMENT_EMPTY
+#define BF_USBCTRL_CTRLDSSEGMENT_EMPTY_V(e)     BF_USBCTRL_CTRLDSSEGMENT_EMPTY(BV_USBCTRL_CTRLDSSEGMENT_EMPTY__##e)
+#define BFM_USBCTRL_CTRLDSSEGMENT_EMPTY_V(v)    BM_USBCTRL_CTRLDSSEGMENT_EMPTY
+
+#define HW_USBCTRL_PERIODICLISTBASE                 HW(USBCTRL_PERIODICLISTBASE)
+#define HWA_USBCTRL_PERIODICLISTBASE                (0x80080000 + 0x154)
+#define HWT_USBCTRL_PERIODICLISTBASE                HWIO_32_RW
+#define HWN_USBCTRL_PERIODICLISTBASE                USBCTRL_PERIODICLISTBASE
+#define HWI_USBCTRL_PERIODICLISTBASE                
+#define BP_USBCTRL_PERIODICLISTBASE_BASEADDR        12
+#define BM_USBCTRL_PERIODICLISTBASE_BASEADDR        0xfffff000
+#define BF_USBCTRL_PERIODICLISTBASE_BASEADDR(v)     (((v) & 0xfffff) << 12)
+#define BFM_USBCTRL_PERIODICLISTBASE_BASEADDR(v)    BM_USBCTRL_PERIODICLISTBASE_BASEADDR
+#define BF_USBCTRL_PERIODICLISTBASE_BASEADDR_V(e)   BF_USBCTRL_PERIODICLISTBASE_BASEADDR(BV_USBCTRL_PERIODICLISTBASE_BASEADDR__##e)
+#define BFM_USBCTRL_PERIODICLISTBASE_BASEADDR_V(v)  BM_USBCTRL_PERIODICLISTBASE_BASEADDR
+
+#define HW_USBCTRL_ASYNCLISTADDR                HW(USBCTRL_ASYNCLISTADDR)
+#define HWA_USBCTRL_ASYNCLISTADDR               (0x80080000 + 0x158)
+#define HWT_USBCTRL_ASYNCLISTADDR               HWIO_32_RW
+#define HWN_USBCTRL_ASYNCLISTADDR               USBCTRL_ASYNCLISTADDR
+#define HWI_USBCTRL_ASYNCLISTADDR               
+#define BP_USBCTRL_ASYNCLISTADDR_ASYBASE        5
+#define BM_USBCTRL_ASYNCLISTADDR_ASYBASE        0xffffffe0
+#define BF_USBCTRL_ASYNCLISTADDR_ASYBASE(v)     (((v) & 0x7ffffff) << 5)
+#define BFM_USBCTRL_ASYNCLISTADDR_ASYBASE(v)    BM_USBCTRL_ASYNCLISTADDR_ASYBASE
+#define BF_USBCTRL_ASYNCLISTADDR_ASYBASE_V(e)   BF_USBCTRL_ASYNCLISTADDR_ASYBASE(BV_USBCTRL_ASYNCLISTADDR_ASYBASE__##e)
+#define BFM_USBCTRL_ASYNCLISTADDR_ASYBASE_V(v)  BM_USBCTRL_ASYNCLISTADDR_ASYBASE
+
+#define HW_USBCTRL_TTCTRL               HW(USBCTRL_TTCTRL)
+#define HWA_USBCTRL_TTCTRL              (0x80080000 + 0x15c)
+#define HWT_USBCTRL_TTCTRL              HWIO_32_RW
+#define HWN_USBCTRL_TTCTRL              USBCTRL_TTCTRL
+#define HWI_USBCTRL_TTCTRL              
+#define BP_USBCTRL_TTCTRL_TTHA          24
+#define BM_USBCTRL_TTCTRL_TTHA          0x7f000000
+#define BF_USBCTRL_TTCTRL_TTHA(v)       (((v) & 0x7f) << 24)
+#define BFM_USBCTRL_TTCTRL_TTHA(v)      BM_USBCTRL_TTCTRL_TTHA
+#define BF_USBCTRL_TTCTRL_TTHA_V(e)     BF_USBCTRL_TTCTRL_TTHA(BV_USBCTRL_TTCTRL_TTHA__##e)
+#define BFM_USBCTRL_TTCTRL_TTHA_V(v)    BM_USBCTRL_TTCTRL_TTHA
+
+#define HW_USBCTRL_BURSTSIZE            HW(USBCTRL_BURSTSIZE)
+#define HWA_USBCTRL_BURSTSIZE           (0x80080000 + 0x160)
+#define HWT_USBCTRL_BURSTSIZE           HWIO_32_RW
+#define HWN_USBCTRL_BURSTSIZE           USBCTRL_BURSTSIZE
+#define HWI_USBCTRL_BURSTSIZE           
+#define BP_USBCTRL_BURSTSIZE_TX         8
+#define BM_USBCTRL_BURSTSIZE_TX         0xff00
+#define BF_USBCTRL_BURSTSIZE_TX(v)      (((v) & 0xff) << 8)
+#define BFM_USBCTRL_BURSTSIZE_TX(v)     BM_USBCTRL_BURSTSIZE_TX
+#define BF_USBCTRL_BURSTSIZE_TX_V(e)    BF_USBCTRL_BURSTSIZE_TX(BV_USBCTRL_BURSTSIZE_TX__##e)
+#define BFM_USBCTRL_BURSTSIZE_TX_V(v)   BM_USBCTRL_BURSTSIZE_TX
+#define BP_USBCTRL_BURSTSIZE_RX         0
+#define BM_USBCTRL_BURSTSIZE_RX         0xff
+#define BF_USBCTRL_BURSTSIZE_RX(v)      (((v) & 0xff) << 0)
+#define BFM_USBCTRL_BURSTSIZE_RX(v)     BM_USBCTRL_BURSTSIZE_RX
+#define BF_USBCTRL_BURSTSIZE_RX_V(e)    BF_USBCTRL_BURSTSIZE_RX(BV_USBCTRL_BURSTSIZE_RX__##e)
+#define BFM_USBCTRL_BURSTSIZE_RX_V(v)   BM_USBCTRL_BURSTSIZE_RX
+
+#define HW_USBCTRL_TXFILLTUNING                     HW(USBCTRL_TXFILLTUNING)
+#define HWA_USBCTRL_TXFILLTUNING                    (0x80080000 + 0x164)
+#define HWT_USBCTRL_TXFILLTUNING                    HWIO_32_RW
+#define HWN_USBCTRL_TXFILLTUNING                    USBCTRL_TXFILLTUNING
+#define HWI_USBCTRL_TXFILLTUNING                    
+#define BP_USBCTRL_TXFILLTUNING_TXFIFOTHRES         16
+#define BM_USBCTRL_TXFILLTUNING_TXFIFOTHRES         0x3f0000
+#define BF_USBCTRL_TXFILLTUNING_TXFIFOTHRES(v)      (((v) & 0x3f) << 16)
+#define BFM_USBCTRL_TXFILLTUNING_TXFIFOTHRES(v)     BM_USBCTRL_TXFILLTUNING_TXFIFOTHRES
+#define BF_USBCTRL_TXFILLTUNING_TXFIFOTHRES_V(e)    BF_USBCTRL_TXFILLTUNING_TXFIFOTHRES(BV_USBCTRL_TXFILLTUNING_TXFIFOTHRES__##e)
+#define BFM_USBCTRL_TXFILLTUNING_TXFIFOTHRES_V(v)   BM_USBCTRL_TXFILLTUNING_TXFIFOTHRES
+#define BP_USBCTRL_TXFILLTUNING_TXSCHEALTH          8
+#define BM_USBCTRL_TXFILLTUNING_TXSCHEALTH          0x1f00
+#define BF_USBCTRL_TXFILLTUNING_TXSCHEALTH(v)       (((v) & 0x1f) << 8)
+#define BFM_USBCTRL_TXFILLTUNING_TXSCHEALTH(v)      BM_USBCTRL_TXFILLTUNING_TXSCHEALTH
+#define BF_USBCTRL_TXFILLTUNING_TXSCHEALTH_V(e)     BF_USBCTRL_TXFILLTUNING_TXSCHEALTH(BV_USBCTRL_TXFILLTUNING_TXSCHEALTH__##e)
+#define BFM_USBCTRL_TXFILLTUNING_TXSCHEALTH_V(v)    BM_USBCTRL_TXFILLTUNING_TXSCHEALTH
+#define BP_USBCTRL_TXFILLTUNING_TXSCHOH             0
+#define BM_USBCTRL_TXFILLTUNING_TXSCHOH             0xff
+#define BF_USBCTRL_TXFILLTUNING_TXSCHOH(v)          (((v) & 0xff) << 0)
+#define BFM_USBCTRL_TXFILLTUNING_TXSCHOH(v)         BM_USBCTRL_TXFILLTUNING_TXSCHOH
+#define BF_USBCTRL_TXFILLTUNING_TXSCHOH_V(e)        BF_USBCTRL_TXFILLTUNING_TXSCHOH(BV_USBCTRL_TXFILLTUNING_TXSCHOH__##e)
+#define BFM_USBCTRL_TXFILLTUNING_TXSCHOH_V(v)       BM_USBCTRL_TXFILLTUNING_TXSCHOH
+
+#define HW_USBCTRL_TXTTFILLTUNING               HW(USBCTRL_TXTTFILLTUNING)
+#define HWA_USBCTRL_TXTTFILLTUNING              (0x80080000 + 0x168)
+#define HWT_USBCTRL_TXTTFILLTUNING              HWIO_32_RW
+#define HWN_USBCTRL_TXTTFILLTUNING              USBCTRL_TXTTFILLTUNING
+#define HWI_USBCTRL_TXTTFILLTUNING              
+#define BP_USBCTRL_TXTTFILLTUNING_EMPTY         0
+#define BM_USBCTRL_TXTTFILLTUNING_EMPTY         0xffffffff
+#define BF_USBCTRL_TXTTFILLTUNING_EMPTY(v)      (((v) & 0xffffffff) << 0)
+#define BFM_USBCTRL_TXTTFILLTUNING_EMPTY(v)     BM_USBCTRL_TXTTFILLTUNING_EMPTY
+#define BF_USBCTRL_TXTTFILLTUNING_EMPTY_V(e)    BF_USBCTRL_TXTTFILLTUNING_EMPTY(BV_USBCTRL_TXTTFILLTUNING_EMPTY__##e)
+#define BFM_USBCTRL_TXTTFILLTUNING_EMPTY_V(v)   BM_USBCTRL_TXTTFILLTUNING_EMPTY
+
+#define HW_USBCTRL_ULPI                 HW(USBCTRL_ULPI)
+#define HWA_USBCTRL_ULPI                (0x80080000 + 0x170)
+#define HWT_USBCTRL_ULPI                HWIO_32_RW
+#define HWN_USBCTRL_ULPI                USBCTRL_ULPI
+#define HWI_USBCTRL_ULPI                
+#define BP_USBCTRL_ULPI_WAKEUP          31
+#define BM_USBCTRL_ULPI_WAKEUP          0x80000000
+#define BF_USBCTRL_ULPI_WAKEUP(v)       (((v) & 0x1) << 31)
+#define BFM_USBCTRL_ULPI_WAKEUP(v)      BM_USBCTRL_ULPI_WAKEUP
+#define BF_USBCTRL_ULPI_WAKEUP_V(e)     BF_USBCTRL_ULPI_WAKEUP(BV_USBCTRL_ULPI_WAKEUP__##e)
+#define BFM_USBCTRL_ULPI_WAKEUP_V(v)    BM_USBCTRL_ULPI_WAKEUP
+#define BP_USBCTRL_ULPI_RUN             30
+#define BM_USBCTRL_ULPI_RUN             0x40000000
+#define BF_USBCTRL_ULPI_RUN(v)          (((v) & 0x1) << 30)
+#define BFM_USBCTRL_ULPI_RUN(v)         BM_USBCTRL_ULPI_RUN
+#define BF_USBCTRL_ULPI_RUN_V(e)        BF_USBCTRL_ULPI_RUN(BV_USBCTRL_ULPI_RUN__##e)
+#define BFM_USBCTRL_ULPI_RUN_V(v)       BM_USBCTRL_ULPI_RUN
+#define BP_USBCTRL_ULPI_RDWR            29
+#define BM_USBCTRL_ULPI_RDWR            0x20000000
+#define BF_USBCTRL_ULPI_RDWR(v)         (((v) & 0x1) << 29)
+#define BFM_USBCTRL_ULPI_RDWR(v)        BM_USBCTRL_ULPI_RDWR
+#define BF_USBCTRL_ULPI_RDWR_V(e)       BF_USBCTRL_ULPI_RDWR(BV_USBCTRL_ULPI_RDWR__##e)
+#define BFM_USBCTRL_ULPI_RDWR_V(v)      BM_USBCTRL_ULPI_RDWR
+#define BP_USBCTRL_ULPI_ERROR           28
+#define BM_USBCTRL_ULPI_ERROR           0x10000000
+#define BF_USBCTRL_ULPI_ERROR(v)        (((v) & 0x1) << 28)
+#define BFM_USBCTRL_ULPI_ERROR(v)       BM_USBCTRL_ULPI_ERROR
+#define BF_USBCTRL_ULPI_ERROR_V(e)      BF_USBCTRL_ULPI_ERROR(BV_USBCTRL_ULPI_ERROR__##e)
+#define BFM_USBCTRL_ULPI_ERROR_V(v)     BM_USBCTRL_ULPI_ERROR
+#define BP_USBCTRL_ULPI_SYNC            27
+#define BM_USBCTRL_ULPI_SYNC            0x8000000
+#define BF_USBCTRL_ULPI_SYNC(v)         (((v) & 0x1) << 27)
+#define BFM_USBCTRL_ULPI_SYNC(v)        BM_USBCTRL_ULPI_SYNC
+#define BF_USBCTRL_ULPI_SYNC_V(e)       BF_USBCTRL_ULPI_SYNC(BV_USBCTRL_ULPI_SYNC__##e)
+#define BFM_USBCTRL_ULPI_SYNC_V(v)      BM_USBCTRL_ULPI_SYNC
+#define BP_USBCTRL_ULPI_PORT            24
+#define BM_USBCTRL_ULPI_PORT            0x7000000
+#define BF_USBCTRL_ULPI_PORT(v)         (((v) & 0x7) << 24)
+#define BFM_USBCTRL_ULPI_PORT(v)        BM_USBCTRL_ULPI_PORT
+#define BF_USBCTRL_ULPI_PORT_V(e)       BF_USBCTRL_ULPI_PORT(BV_USBCTRL_ULPI_PORT__##e)
+#define BFM_USBCTRL_ULPI_PORT_V(v)      BM_USBCTRL_ULPI_PORT
+#define BP_USBCTRL_ULPI_ADDR            16
+#define BM_USBCTRL_ULPI_ADDR            0xff0000
+#define BF_USBCTRL_ULPI_ADDR(v)         (((v) & 0xff) << 16)
+#define BFM_USBCTRL_ULPI_ADDR(v)        BM_USBCTRL_ULPI_ADDR
+#define BF_USBCTRL_ULPI_ADDR_V(e)       BF_USBCTRL_ULPI_ADDR(BV_USBCTRL_ULPI_ADDR__##e)
+#define BFM_USBCTRL_ULPI_ADDR_V(v)      BM_USBCTRL_ULPI_ADDR
+#define BP_USBCTRL_ULPI_DATARD          8
+#define BM_USBCTRL_ULPI_DATARD          0xff00
+#define BF_USBCTRL_ULPI_DATARD(v)       (((v) & 0xff) << 8)
+#define BFM_USBCTRL_ULPI_DATARD(v)      BM_USBCTRL_ULPI_DATARD
+#define BF_USBCTRL_ULPI_DATARD_V(e)     BF_USBCTRL_ULPI_DATARD(BV_USBCTRL_ULPI_DATARD__##e)
+#define BFM_USBCTRL_ULPI_DATARD_V(v)    BM_USBCTRL_ULPI_DATARD
+#define BP_USBCTRL_ULPI_DATAWR          0
+#define BM_USBCTRL_ULPI_DATAWR          0xff
+#define BF_USBCTRL_ULPI_DATAWR(v)       (((v) & 0xff) << 0)
+#define BFM_USBCTRL_ULPI_DATAWR(v)      BM_USBCTRL_ULPI_DATAWR
+#define BF_USBCTRL_ULPI_DATAWR_V(e)     BF_USBCTRL_ULPI_DATAWR(BV_USBCTRL_ULPI_DATAWR__##e)
+#define BFM_USBCTRL_ULPI_DATAWR_V(v)    BM_USBCTRL_ULPI_DATAWR
+
+#define HW_USBCTRL_VFRAME               HW(USBCTRL_VFRAME)
+#define HWA_USBCTRL_VFRAME              (0x80080000 + 0x174)
+#define HWT_USBCTRL_VFRAME              HWIO_32_RW
+#define HWN_USBCTRL_VFRAME              USBCTRL_VFRAME
+#define HWI_USBCTRL_VFRAME              
+#define BP_USBCTRL_VFRAME_EMPTY         0
+#define BM_USBCTRL_VFRAME_EMPTY         0xffffffff
+#define BF_USBCTRL_VFRAME_EMPTY(v)      (((v) & 0xffffffff) << 0)
+#define BFM_USBCTRL_VFRAME_EMPTY(v)     BM_USBCTRL_VFRAME_EMPTY
+#define BF_USBCTRL_VFRAME_EMPTY_V(e)    BF_USBCTRL_VFRAME_EMPTY(BV_USBCTRL_VFRAME_EMPTY__##e)
+#define BFM_USBCTRL_VFRAME_EMPTY_V(v)   BM_USBCTRL_VFRAME_EMPTY
+
+#define HW_USBCTRL_EPNAK            HW(USBCTRL_EPNAK)
+#define HWA_USBCTRL_EPNAK           (0x80080000 + 0x178)
+#define HWT_USBCTRL_EPNAK           HWIO_32_RW
+#define HWN_USBCTRL_EPNAK           USBCTRL_EPNAK
+#define HWI_USBCTRL_EPNAK           
+#define BP_USBCTRL_EPNAK_EPTN       16
+#define BM_USBCTRL_EPNAK_EPTN       0xffff0000
+#define BF_USBCTRL_EPNAK_EPTN(v)    (((v) & 0xffff) << 16)
+#define BFM_USBCTRL_EPNAK_EPTN(v)   BM_USBCTRL_EPNAK_EPTN
+#define BF_USBCTRL_EPNAK_EPTN_V(e)  BF_USBCTRL_EPNAK_EPTN(BV_USBCTRL_EPNAK_EPTN__##e)
+#define BFM_USBCTRL_EPNAK_EPTN_V(v) BM_USBCTRL_EPNAK_EPTN
+#define BP_USBCTRL_EPNAK_EPRN       0
+#define BM_USBCTRL_EPNAK_EPRN       0xffff
+#define BF_USBCTRL_EPNAK_EPRN(v)    (((v) & 0xffff) << 0)
+#define BFM_USBCTRL_EPNAK_EPRN(v)   BM_USBCTRL_EPNAK_EPRN
+#define BF_USBCTRL_EPNAK_EPRN_V(e)  BF_USBCTRL_EPNAK_EPRN(BV_USBCTRL_EPNAK_EPRN__##e)
+#define BFM_USBCTRL_EPNAK_EPRN_V(v) BM_USBCTRL_EPNAK_EPRN
+
+#define HW_USBCTRL_EPNAKEN              HW(USBCTRL_EPNAKEN)
+#define HWA_USBCTRL_EPNAKEN             (0x80080000 + 0x17c)
+#define HWT_USBCTRL_EPNAKEN             HWIO_32_RW
+#define HWN_USBCTRL_EPNAKEN             USBCTRL_EPNAKEN
+#define HWI_USBCTRL_EPNAKEN             
+#define BP_USBCTRL_EPNAKEN_EPTNE        16
+#define BM_USBCTRL_EPNAKEN_EPTNE        0xffff0000
+#define BF_USBCTRL_EPNAKEN_EPTNE(v)     (((v) & 0xffff) << 16)
+#define BFM_USBCTRL_EPNAKEN_EPTNE(v)    BM_USBCTRL_EPNAKEN_EPTNE
+#define BF_USBCTRL_EPNAKEN_EPTNE_V(e)   BF_USBCTRL_EPNAKEN_EPTNE(BV_USBCTRL_EPNAKEN_EPTNE__##e)
+#define BFM_USBCTRL_EPNAKEN_EPTNE_V(v)  BM_USBCTRL_EPNAKEN_EPTNE
+#define BP_USBCTRL_EPNAKEN_EPRNE        0
+#define BM_USBCTRL_EPNAKEN_EPRNE        0xffff
+#define BF_USBCTRL_EPNAKEN_EPRNE(v)     (((v) & 0xffff) << 0)
+#define BFM_USBCTRL_EPNAKEN_EPRNE(v)    BM_USBCTRL_EPNAKEN_EPRNE
+#define BF_USBCTRL_EPNAKEN_EPRNE_V(e)   BF_USBCTRL_EPNAKEN_EPRNE(BV_USBCTRL_EPNAKEN_EPRNE__##e)
+#define BFM_USBCTRL_EPNAKEN_EPRNE_V(v)  BM_USBCTRL_EPNAKEN_EPRNE
+
+#define HW_USBCTRL_CONFIGFLAG               HW(USBCTRL_CONFIGFLAG)
+#define HWA_USBCTRL_CONFIGFLAG              (0x80080000 + 0x180)
+#define HWT_USBCTRL_CONFIGFLAG              HWIO_32_RW
+#define HWN_USBCTRL_CONFIGFLAG              USBCTRL_CONFIGFLAG
+#define HWI_USBCTRL_CONFIGFLAG              
+#define BP_USBCTRL_CONFIGFLAG_FLAG          0
+#define BM_USBCTRL_CONFIGFLAG_FLAG          0x1
+#define BF_USBCTRL_CONFIGFLAG_FLAG(v)       (((v) & 0x1) << 0)
+#define BFM_USBCTRL_CONFIGFLAG_FLAG(v)      BM_USBCTRL_CONFIGFLAG_FLAG
+#define BF_USBCTRL_CONFIGFLAG_FLAG_V(e)     BF_USBCTRL_CONFIGFLAG_FLAG(BV_USBCTRL_CONFIGFLAG_FLAG__##e)
+#define BFM_USBCTRL_CONFIGFLAG_FLAG_V(v)    BM_USBCTRL_CONFIGFLAG_FLAG
+
+#define HW_USBCTRL_PORTSC1                      HW(USBCTRL_PORTSC1)
+#define HWA_USBCTRL_PORTSC1                     (0x80080000 + 0x184)
+#define HWT_USBCTRL_PORTSC1                     HWIO_32_RW
+#define HWN_USBCTRL_PORTSC1                     USBCTRL_PORTSC1
+#define HWI_USBCTRL_PORTSC1                     
+#define BP_USBCTRL_PORTSC1_PTS                  30
+#define BM_USBCTRL_PORTSC1_PTS                  0xc0000000
+#define BV_USBCTRL_PORTSC1_PTS__UTMI            0x0
+#define BV_USBCTRL_PORTSC1_PTS__PHIL            0x1
+#define BV_USBCTRL_PORTSC1_PTS__ULPI            0x2
+#define BV_USBCTRL_PORTSC1_PTS__SERIAL          0x3
+#define BF_USBCTRL_PORTSC1_PTS(v)               (((v) & 0x3) << 30)
+#define BFM_USBCTRL_PORTSC1_PTS(v)              BM_USBCTRL_PORTSC1_PTS
+#define BF_USBCTRL_PORTSC1_PTS_V(e)             BF_USBCTRL_PORTSC1_PTS(BV_USBCTRL_PORTSC1_PTS__##e)
+#define BFM_USBCTRL_PORTSC1_PTS_V(v)            BM_USBCTRL_PORTSC1_PTS
+#define BP_USBCTRL_PORTSC1_STS                  29
+#define BM_USBCTRL_PORTSC1_STS                  0x20000000
+#define BF_USBCTRL_PORTSC1_STS(v)               (((v) & 0x1) << 29)
+#define BFM_USBCTRL_PORTSC1_STS(v)              BM_USBCTRL_PORTSC1_STS
+#define BF_USBCTRL_PORTSC1_STS_V(e)             BF_USBCTRL_PORTSC1_STS(BV_USBCTRL_PORTSC1_STS__##e)
+#define BFM_USBCTRL_PORTSC1_STS_V(v)            BM_USBCTRL_PORTSC1_STS
+#define BP_USBCTRL_PORTSC1_PTW                  28
+#define BM_USBCTRL_PORTSC1_PTW                  0x10000000
+#define BF_USBCTRL_PORTSC1_PTW(v)               (((v) & 0x1) << 28)
+#define BFM_USBCTRL_PORTSC1_PTW(v)              BM_USBCTRL_PORTSC1_PTW
+#define BF_USBCTRL_PORTSC1_PTW_V(e)             BF_USBCTRL_PORTSC1_PTW(BV_USBCTRL_PORTSC1_PTW__##e)
+#define BFM_USBCTRL_PORTSC1_PTW_V(v)            BM_USBCTRL_PORTSC1_PTW
+#define BP_USBCTRL_PORTSC1_PSPD                 26
+#define BM_USBCTRL_PORTSC1_PSPD                 0xc000000
+#define BV_USBCTRL_PORTSC1_PSPD__FULL           0x0
+#define BV_USBCTRL_PORTSC1_PSPD__LO             0x1
+#define BV_USBCTRL_PORTSC1_PSPD__HI             0x2
+#define BF_USBCTRL_PORTSC1_PSPD(v)              (((v) & 0x3) << 26)
+#define BFM_USBCTRL_PORTSC1_PSPD(v)             BM_USBCTRL_PORTSC1_PSPD
+#define BF_USBCTRL_PORTSC1_PSPD_V(e)            BF_USBCTRL_PORTSC1_PSPD(BV_USBCTRL_PORTSC1_PSPD__##e)
+#define BFM_USBCTRL_PORTSC1_PSPD_V(v)           BM_USBCTRL_PORTSC1_PSPD
+#define BP_USBCTRL_PORTSC1_PFSC                 24
+#define BM_USBCTRL_PORTSC1_PFSC                 0x1000000
+#define BF_USBCTRL_PORTSC1_PFSC(v)              (((v) & 0x1) << 24)
+#define BFM_USBCTRL_PORTSC1_PFSC(v)             BM_USBCTRL_PORTSC1_PFSC
+#define BF_USBCTRL_PORTSC1_PFSC_V(e)            BF_USBCTRL_PORTSC1_PFSC(BV_USBCTRL_PORTSC1_PFSC__##e)
+#define BFM_USBCTRL_PORTSC1_PFSC_V(v)           BM_USBCTRL_PORTSC1_PFSC
+#define BP_USBCTRL_PORTSC1_PHCD                 23
+#define BM_USBCTRL_PORTSC1_PHCD                 0x800000
+#define BF_USBCTRL_PORTSC1_PHCD(v)              (((v) & 0x1) << 23)
+#define BFM_USBCTRL_PORTSC1_PHCD(v)             BM_USBCTRL_PORTSC1_PHCD
+#define BF_USBCTRL_PORTSC1_PHCD_V(e)            BF_USBCTRL_PORTSC1_PHCD(BV_USBCTRL_PORTSC1_PHCD__##e)
+#define BFM_USBCTRL_PORTSC1_PHCD_V(v)           BM_USBCTRL_PORTSC1_PHCD
+#define BP_USBCTRL_PORTSC1_WKOC                 22
+#define BM_USBCTRL_PORTSC1_WKOC                 0x400000
+#define BF_USBCTRL_PORTSC1_WKOC(v)              (((v) & 0x1) << 22)
+#define BFM_USBCTRL_PORTSC1_WKOC(v)             BM_USBCTRL_PORTSC1_WKOC
+#define BF_USBCTRL_PORTSC1_WKOC_V(e)            BF_USBCTRL_PORTSC1_WKOC(BV_USBCTRL_PORTSC1_WKOC__##e)
+#define BFM_USBCTRL_PORTSC1_WKOC_V(v)           BM_USBCTRL_PORTSC1_WKOC
+#define BP_USBCTRL_PORTSC1_WKDS                 21
+#define BM_USBCTRL_PORTSC1_WKDS                 0x200000
+#define BF_USBCTRL_PORTSC1_WKDS(v)              (((v) & 0x1) << 21)
+#define BFM_USBCTRL_PORTSC1_WKDS(v)             BM_USBCTRL_PORTSC1_WKDS
+#define BF_USBCTRL_PORTSC1_WKDS_V(e)            BF_USBCTRL_PORTSC1_WKDS(BV_USBCTRL_PORTSC1_WKDS__##e)
+#define BFM_USBCTRL_PORTSC1_WKDS_V(v)           BM_USBCTRL_PORTSC1_WKDS
+#define BP_USBCTRL_PORTSC1_WKCN                 20
+#define BM_USBCTRL_PORTSC1_WKCN                 0x100000
+#define BF_USBCTRL_PORTSC1_WKCN(v)              (((v) & 0x1) << 20)
+#define BFM_USBCTRL_PORTSC1_WKCN(v)             BM_USBCTRL_PORTSC1_WKCN
+#define BF_USBCTRL_PORTSC1_WKCN_V(e)            BF_USBCTRL_PORTSC1_WKCN(BV_USBCTRL_PORTSC1_WKCN__##e)
+#define BFM_USBCTRL_PORTSC1_WKCN_V(v)           BM_USBCTRL_PORTSC1_WKCN
+#define BP_USBCTRL_PORTSC1_PTC                  16
+#define BM_USBCTRL_PORTSC1_PTC                  0xf0000
+#define BV_USBCTRL_PORTSC1_PTC__DISABLE         0x0
+#define BV_USBCTRL_PORTSC1_PTC__J               0x1
+#define BV_USBCTRL_PORTSC1_PTC__K               0x2
+#define BV_USBCTRL_PORTSC1_PTC__SE0orNAK        0x3
+#define BV_USBCTRL_PORTSC1_PTC__Packet          0x4
+#define BV_USBCTRL_PORTSC1_PTC__ForceEnableHS   0x5
+#define BV_USBCTRL_PORTSC1_PTC__ForceEnableFS   0x6
+#define BV_USBCTRL_PORTSC1_PTC__ForceEnableLS   0x7
+#define BF_USBCTRL_PORTSC1_PTC(v)               (((v) & 0xf) << 16)
+#define BFM_USBCTRL_PORTSC1_PTC(v)              BM_USBCTRL_PORTSC1_PTC
+#define BF_USBCTRL_PORTSC1_PTC_V(e)             BF_USBCTRL_PORTSC1_PTC(BV_USBCTRL_PORTSC1_PTC__##e)
+#define BFM_USBCTRL_PORTSC1_PTC_V(v)            BM_USBCTRL_PORTSC1_PTC
+#define BP_USBCTRL_PORTSC1_PIC                  14
+#define BM_USBCTRL_PORTSC1_PIC                  0xc000
+#define BV_USBCTRL_PORTSC1_PIC__OFF             0x0
+#define BV_USBCTRL_PORTSC1_PIC__AMBER           0x1
+#define BV_USBCTRL_PORTSC1_PIC__GREEN           0x2
+#define BV_USBCTRL_PORTSC1_PIC__UNDEF           0x3
+#define BF_USBCTRL_PORTSC1_PIC(v)               (((v) & 0x3) << 14)
+#define BFM_USBCTRL_PORTSC1_PIC(v)              BM_USBCTRL_PORTSC1_PIC
+#define BF_USBCTRL_PORTSC1_PIC_V(e)             BF_USBCTRL_PORTSC1_PIC(BV_USBCTRL_PORTSC1_PIC__##e)
+#define BFM_USBCTRL_PORTSC1_PIC_V(v)            BM_USBCTRL_PORTSC1_PIC
+#define BP_USBCTRL_PORTSC1_PO                   13
+#define BM_USBCTRL_PORTSC1_PO                   0x2000
+#define BF_USBCTRL_PORTSC1_PO(v)                (((v) & 0x1) << 13)
+#define BFM_USBCTRL_PORTSC1_PO(v)               BM_USBCTRL_PORTSC1_PO
+#define BF_USBCTRL_PORTSC1_PO_V(e)              BF_USBCTRL_PORTSC1_PO(BV_USBCTRL_PORTSC1_PO__##e)
+#define BFM_USBCTRL_PORTSC1_PO_V(v)             BM_USBCTRL_PORTSC1_PO
+#define BP_USBCTRL_PORTSC1_PP                   12
+#define BM_USBCTRL_PORTSC1_PP                   0x1000
+#define BF_USBCTRL_PORTSC1_PP(v)                (((v) & 0x1) << 12)
+#define BFM_USBCTRL_PORTSC1_PP(v)               BM_USBCTRL_PORTSC1_PP
+#define BF_USBCTRL_PORTSC1_PP_V(e)              BF_USBCTRL_PORTSC1_PP(BV_USBCTRL_PORTSC1_PP__##e)
+#define BFM_USBCTRL_PORTSC1_PP_V(v)             BM_USBCTRL_PORTSC1_PP
+#define BP_USBCTRL_PORTSC1_LS                   10
+#define BM_USBCTRL_PORTSC1_LS                   0xc00
+#define BV_USBCTRL_PORTSC1_LS__SE0              0x0
+#define BV_USBCTRL_PORTSC1_LS__K                0x1
+#define BV_USBCTRL_PORTSC1_LS__J                0x2
+#define BF_USBCTRL_PORTSC1_LS(v)                (((v) & 0x3) << 10)
+#define BFM_USBCTRL_PORTSC1_LS(v)               BM_USBCTRL_PORTSC1_LS
+#define BF_USBCTRL_PORTSC1_LS_V(e)              BF_USBCTRL_PORTSC1_LS(BV_USBCTRL_PORTSC1_LS__##e)
+#define BFM_USBCTRL_PORTSC1_LS_V(v)             BM_USBCTRL_PORTSC1_LS
+#define BP_USBCTRL_PORTSC1_HSP                  9
+#define BM_USBCTRL_PORTSC1_HSP                  0x200
+#define BF_USBCTRL_PORTSC1_HSP(v)               (((v) & 0x1) << 9)
+#define BFM_USBCTRL_PORTSC1_HSP(v)              BM_USBCTRL_PORTSC1_HSP
+#define BF_USBCTRL_PORTSC1_HSP_V(e)             BF_USBCTRL_PORTSC1_HSP(BV_USBCTRL_PORTSC1_HSP__##e)
+#define BFM_USBCTRL_PORTSC1_HSP_V(v)            BM_USBCTRL_PORTSC1_HSP
+#define BP_USBCTRL_PORTSC1_PR                   8
+#define BM_USBCTRL_PORTSC1_PR                   0x100
+#define BF_USBCTRL_PORTSC1_PR(v)                (((v) & 0x1) << 8)
+#define BFM_USBCTRL_PORTSC1_PR(v)               BM_USBCTRL_PORTSC1_PR
+#define BF_USBCTRL_PORTSC1_PR_V(e)              BF_USBCTRL_PORTSC1_PR(BV_USBCTRL_PORTSC1_PR__##e)
+#define BFM_USBCTRL_PORTSC1_PR_V(v)             BM_USBCTRL_PORTSC1_PR
+#define BP_USBCTRL_PORTSC1_SUSP                 7
+#define BM_USBCTRL_PORTSC1_SUSP                 0x80
+#define BF_USBCTRL_PORTSC1_SUSP(v)              (((v) & 0x1) << 7)
+#define BFM_USBCTRL_PORTSC1_SUSP(v)             BM_USBCTRL_PORTSC1_SUSP
+#define BF_USBCTRL_PORTSC1_SUSP_V(e)            BF_USBCTRL_PORTSC1_SUSP(BV_USBCTRL_PORTSC1_SUSP__##e)
+#define BFM_USBCTRL_PORTSC1_SUSP_V(v)           BM_USBCTRL_PORTSC1_SUSP
+#define BP_USBCTRL_PORTSC1_FPR                  6
+#define BM_USBCTRL_PORTSC1_FPR                  0x40
+#define BF_USBCTRL_PORTSC1_FPR(v)               (((v) & 0x1) << 6)
+#define BFM_USBCTRL_PORTSC1_FPR(v)              BM_USBCTRL_PORTSC1_FPR
+#define BF_USBCTRL_PORTSC1_FPR_V(e)             BF_USBCTRL_PORTSC1_FPR(BV_USBCTRL_PORTSC1_FPR__##e)
+#define BFM_USBCTRL_PORTSC1_FPR_V(v)            BM_USBCTRL_PORTSC1_FPR
+#define BP_USBCTRL_PORTSC1_OCC                  5
+#define BM_USBCTRL_PORTSC1_OCC                  0x20
+#define BF_USBCTRL_PORTSC1_OCC(v)               (((v) & 0x1) << 5)
+#define BFM_USBCTRL_PORTSC1_OCC(v)              BM_USBCTRL_PORTSC1_OCC
+#define BF_USBCTRL_PORTSC1_OCC_V(e)             BF_USBCTRL_PORTSC1_OCC(BV_USBCTRL_PORTSC1_OCC__##e)
+#define BFM_USBCTRL_PORTSC1_OCC_V(v)            BM_USBCTRL_PORTSC1_OCC
+#define BP_USBCTRL_PORTSC1_OCA                  4
+#define BM_USBCTRL_PORTSC1_OCA                  0x10
+#define BF_USBCTRL_PORTSC1_OCA(v)               (((v) & 0x1) << 4)
+#define BFM_USBCTRL_PORTSC1_OCA(v)              BM_USBCTRL_PORTSC1_OCA
+#define BF_USBCTRL_PORTSC1_OCA_V(e)             BF_USBCTRL_PORTSC1_OCA(BV_USBCTRL_PORTSC1_OCA__##e)
+#define BFM_USBCTRL_PORTSC1_OCA_V(v)            BM_USBCTRL_PORTSC1_OCA
+#define BP_USBCTRL_PORTSC1_PEC                  3
+#define BM_USBCTRL_PORTSC1_PEC                  0x8
+#define BF_USBCTRL_PORTSC1_PEC(v)               (((v) & 0x1) << 3)
+#define BFM_USBCTRL_PORTSC1_PEC(v)              BM_USBCTRL_PORTSC1_PEC
+#define BF_USBCTRL_PORTSC1_PEC_V(e)             BF_USBCTRL_PORTSC1_PEC(BV_USBCTRL_PORTSC1_PEC__##e)
+#define BFM_USBCTRL_PORTSC1_PEC_V(v)            BM_USBCTRL_PORTSC1_PEC
+#define BP_USBCTRL_PORTSC1_PE                   2
+#define BM_USBCTRL_PORTSC1_PE                   0x4
+#define BF_USBCTRL_PORTSC1_PE(v)                (((v) & 0x1) << 2)
+#define BFM_USBCTRL_PORTSC1_PE(v)               BM_USBCTRL_PORTSC1_PE
+#define BF_USBCTRL_PORTSC1_PE_V(e)              BF_USBCTRL_PORTSC1_PE(BV_USBCTRL_PORTSC1_PE__##e)
+#define BFM_USBCTRL_PORTSC1_PE_V(v)             BM_USBCTRL_PORTSC1_PE
+#define BP_USBCTRL_PORTSC1_CSC                  1
+#define BM_USBCTRL_PORTSC1_CSC                  0x2
+#define BF_USBCTRL_PORTSC1_CSC(v)               (((v) & 0x1) << 1)
+#define BFM_USBCTRL_PORTSC1_CSC(v)              BM_USBCTRL_PORTSC1_CSC
+#define BF_USBCTRL_PORTSC1_CSC_V(e)             BF_USBCTRL_PORTSC1_CSC(BV_USBCTRL_PORTSC1_CSC__##e)
+#define BFM_USBCTRL_PORTSC1_CSC_V(v)            BM_USBCTRL_PORTSC1_CSC
+#define BP_USBCTRL_PORTSC1_CCS                  0
+#define BM_USBCTRL_PORTSC1_CCS                  0x1
+#define BF_USBCTRL_PORTSC1_CCS(v)               (((v) & 0x1) << 0)
+#define BFM_USBCTRL_PORTSC1_CCS(v)              BM_USBCTRL_PORTSC1_CCS
+#define BF_USBCTRL_PORTSC1_CCS_V(e)             BF_USBCTRL_PORTSC1_CCS(BV_USBCTRL_PORTSC1_CCS__##e)
+#define BFM_USBCTRL_PORTSC1_CCS_V(v)            BM_USBCTRL_PORTSC1_CCS
+
+#define HW_USBCTRL_OTGSC                HW(USBCTRL_OTGSC)
+#define HWA_USBCTRL_OTGSC               (0x80080000 + 0x1a4)
+#define HWT_USBCTRL_OTGSC               HWIO_32_RW
+#define HWN_USBCTRL_OTGSC               USBCTRL_OTGSC
+#define HWI_USBCTRL_OTGSC               
+#define BP_USBCTRL_OTGSC_DPIE           30
+#define BM_USBCTRL_OTGSC_DPIE           0x40000000
+#define BF_USBCTRL_OTGSC_DPIE(v)        (((v) & 0x1) << 30)
+#define BFM_USBCTRL_OTGSC_DPIE(v)       BM_USBCTRL_OTGSC_DPIE
+#define BF_USBCTRL_OTGSC_DPIE_V(e)      BF_USBCTRL_OTGSC_DPIE(BV_USBCTRL_OTGSC_DPIE__##e)
+#define BFM_USBCTRL_OTGSC_DPIE_V(v)     BM_USBCTRL_OTGSC_DPIE
+#define BP_USBCTRL_OTGSC_ONEMSE         29
+#define BM_USBCTRL_OTGSC_ONEMSE         0x20000000
+#define BF_USBCTRL_OTGSC_ONEMSE(v)      (((v) & 0x1) << 29)
+#define BFM_USBCTRL_OTGSC_ONEMSE(v)     BM_USBCTRL_OTGSC_ONEMSE
+#define BF_USBCTRL_OTGSC_ONEMSE_V(e)    BF_USBCTRL_OTGSC_ONEMSE(BV_USBCTRL_OTGSC_ONEMSE__##e)
+#define BFM_USBCTRL_OTGSC_ONEMSE_V(v)   BM_USBCTRL_OTGSC_ONEMSE
+#define BP_USBCTRL_OTGSC_BSEIE          28
+#define BM_USBCTRL_OTGSC_BSEIE          0x10000000
+#define BF_USBCTRL_OTGSC_BSEIE(v)       (((v) & 0x1) << 28)
+#define BFM_USBCTRL_OTGSC_BSEIE(v)      BM_USBCTRL_OTGSC_BSEIE
+#define BF_USBCTRL_OTGSC_BSEIE_V(e)     BF_USBCTRL_OTGSC_BSEIE(BV_USBCTRL_OTGSC_BSEIE__##e)
+#define BFM_USBCTRL_OTGSC_BSEIE_V(v)    BM_USBCTRL_OTGSC_BSEIE
+#define BP_USBCTRL_OTGSC_BSVIE          27
+#define BM_USBCTRL_OTGSC_BSVIE          0x8000000
+#define BF_USBCTRL_OTGSC_BSVIE(v)       (((v) & 0x1) << 27)
+#define BFM_USBCTRL_OTGSC_BSVIE(v)      BM_USBCTRL_OTGSC_BSVIE
+#define BF_USBCTRL_OTGSC_BSVIE_V(e)     BF_USBCTRL_OTGSC_BSVIE(BV_USBCTRL_OTGSC_BSVIE__##e)
+#define BFM_USBCTRL_OTGSC_BSVIE_V(v)    BM_USBCTRL_OTGSC_BSVIE
+#define BP_USBCTRL_OTGSC_ASVIE          26
+#define BM_USBCTRL_OTGSC_ASVIE          0x4000000
+#define BF_USBCTRL_OTGSC_ASVIE(v)       (((v) & 0x1) << 26)
+#define BFM_USBCTRL_OTGSC_ASVIE(v)      BM_USBCTRL_OTGSC_ASVIE
+#define BF_USBCTRL_OTGSC_ASVIE_V(e)     BF_USBCTRL_OTGSC_ASVIE(BV_USBCTRL_OTGSC_ASVIE__##e)
+#define BFM_USBCTRL_OTGSC_ASVIE_V(v)    BM_USBCTRL_OTGSC_ASVIE
+#define BP_USBCTRL_OTGSC_AVVIE          25
+#define BM_USBCTRL_OTGSC_AVVIE          0x2000000
+#define BF_USBCTRL_OTGSC_AVVIE(v)       (((v) & 0x1) << 25)
+#define BFM_USBCTRL_OTGSC_AVVIE(v)      BM_USBCTRL_OTGSC_AVVIE
+#define BF_USBCTRL_OTGSC_AVVIE_V(e)     BF_USBCTRL_OTGSC_AVVIE(BV_USBCTRL_OTGSC_AVVIE__##e)
+#define BFM_USBCTRL_OTGSC_AVVIE_V(v)    BM_USBCTRL_OTGSC_AVVIE
+#define BP_USBCTRL_OTGSC_IDIE           24
+#define BM_USBCTRL_OTGSC_IDIE           0x1000000
+#define BF_USBCTRL_OTGSC_IDIE(v)        (((v) & 0x1) << 24)
+#define BFM_USBCTRL_OTGSC_IDIE(v)       BM_USBCTRL_OTGSC_IDIE
+#define BF_USBCTRL_OTGSC_IDIE_V(e)      BF_USBCTRL_OTGSC_IDIE(BV_USBCTRL_OTGSC_IDIE__##e)
+#define BFM_USBCTRL_OTGSC_IDIE_V(v)     BM_USBCTRL_OTGSC_IDIE
+#define BP_USBCTRL_OTGSC_DPIS           22
+#define BM_USBCTRL_OTGSC_DPIS           0x400000
+#define BF_USBCTRL_OTGSC_DPIS(v)        (((v) & 0x1) << 22)
+#define BFM_USBCTRL_OTGSC_DPIS(v)       BM_USBCTRL_OTGSC_DPIS
+#define BF_USBCTRL_OTGSC_DPIS_V(e)      BF_USBCTRL_OTGSC_DPIS(BV_USBCTRL_OTGSC_DPIS__##e)
+#define BFM_USBCTRL_OTGSC_DPIS_V(v)     BM_USBCTRL_OTGSC_DPIS
+#define BP_USBCTRL_OTGSC_ONEMSS         21
+#define BM_USBCTRL_OTGSC_ONEMSS         0x200000
+#define BF_USBCTRL_OTGSC_ONEMSS(v)      (((v) & 0x1) << 21)
+#define BFM_USBCTRL_OTGSC_ONEMSS(v)     BM_USBCTRL_OTGSC_ONEMSS
+#define BF_USBCTRL_OTGSC_ONEMSS_V(e)    BF_USBCTRL_OTGSC_ONEMSS(BV_USBCTRL_OTGSC_ONEMSS__##e)
+#define BFM_USBCTRL_OTGSC_ONEMSS_V(v)   BM_USBCTRL_OTGSC_ONEMSS
+#define BP_USBCTRL_OTGSC_BSEIS          20
+#define BM_USBCTRL_OTGSC_BSEIS          0x100000
+#define BF_USBCTRL_OTGSC_BSEIS(v)       (((v) & 0x1) << 20)
+#define BFM_USBCTRL_OTGSC_BSEIS(v)      BM_USBCTRL_OTGSC_BSEIS
+#define BF_USBCTRL_OTGSC_BSEIS_V(e)     BF_USBCTRL_OTGSC_BSEIS(BV_USBCTRL_OTGSC_BSEIS__##e)
+#define BFM_USBCTRL_OTGSC_BSEIS_V(v)    BM_USBCTRL_OTGSC_BSEIS
+#define BP_USBCTRL_OTGSC_BSVIS          19
+#define BM_USBCTRL_OTGSC_BSVIS          0x80000
+#define BF_USBCTRL_OTGSC_BSVIS(v)       (((v) & 0x1) << 19)
+#define BFM_USBCTRL_OTGSC_BSVIS(v)      BM_USBCTRL_OTGSC_BSVIS
+#define BF_USBCTRL_OTGSC_BSVIS_V(e)     BF_USBCTRL_OTGSC_BSVIS(BV_USBCTRL_OTGSC_BSVIS__##e)
+#define BFM_USBCTRL_OTGSC_BSVIS_V(v)    BM_USBCTRL_OTGSC_BSVIS
+#define BP_USBCTRL_OTGSC_ASVIS          18
+#define BM_USBCTRL_OTGSC_ASVIS          0x40000
+#define BF_USBCTRL_OTGSC_ASVIS(v)       (((v) & 0x1) << 18)
+#define BFM_USBCTRL_OTGSC_ASVIS(v)      BM_USBCTRL_OTGSC_ASVIS
+#define BF_USBCTRL_OTGSC_ASVIS_V(e)     BF_USBCTRL_OTGSC_ASVIS(BV_USBCTRL_OTGSC_ASVIS__##e)
+#define BFM_USBCTRL_OTGSC_ASVIS_V(v)    BM_USBCTRL_OTGSC_ASVIS
+#define BP_USBCTRL_OTGSC_AVVIS          17
+#define BM_USBCTRL_OTGSC_AVVIS          0x20000
+#define BF_USBCTRL_OTGSC_AVVIS(v)       (((v) & 0x1) << 17)
+#define BFM_USBCTRL_OTGSC_AVVIS(v)      BM_USBCTRL_OTGSC_AVVIS
+#define BF_USBCTRL_OTGSC_AVVIS_V(e)     BF_USBCTRL_OTGSC_AVVIS(BV_USBCTRL_OTGSC_AVVIS__##e)
+#define BFM_USBCTRL_OTGSC_AVVIS_V(v)    BM_USBCTRL_OTGSC_AVVIS
+#define BP_USBCTRL_OTGSC_IDIS           16
+#define BM_USBCTRL_OTGSC_IDIS           0x10000
+#define BF_USBCTRL_OTGSC_IDIS(v)        (((v) & 0x1) << 16)
+#define BFM_USBCTRL_OTGSC_IDIS(v)       BM_USBCTRL_OTGSC_IDIS
+#define BF_USBCTRL_OTGSC_IDIS_V(e)      BF_USBCTRL_OTGSC_IDIS(BV_USBCTRL_OTGSC_IDIS__##e)
+#define BFM_USBCTRL_OTGSC_IDIS_V(v)     BM_USBCTRL_OTGSC_IDIS
+#define BP_USBCTRL_OTGSC_DPS            14
+#define BM_USBCTRL_OTGSC_DPS            0x4000
+#define BF_USBCTRL_OTGSC_DPS(v)         (((v) & 0x1) << 14)
+#define BFM_USBCTRL_OTGSC_DPS(v)        BM_USBCTRL_OTGSC_DPS
+#define BF_USBCTRL_OTGSC_DPS_V(e)       BF_USBCTRL_OTGSC_DPS(BV_USBCTRL_OTGSC_DPS__##e)
+#define BFM_USBCTRL_OTGSC_DPS_V(v)      BM_USBCTRL_OTGSC_DPS
+#define BP_USBCTRL_OTGSC_ONEMST         13
+#define BM_USBCTRL_OTGSC_ONEMST         0x2000
+#define BF_USBCTRL_OTGSC_ONEMST(v)      (((v) & 0x1) << 13)
+#define BFM_USBCTRL_OTGSC_ONEMST(v)     BM_USBCTRL_OTGSC_ONEMST
+#define BF_USBCTRL_OTGSC_ONEMST_V(e)    BF_USBCTRL_OTGSC_ONEMST(BV_USBCTRL_OTGSC_ONEMST__##e)
+#define BFM_USBCTRL_OTGSC_ONEMST_V(v)   BM_USBCTRL_OTGSC_ONEMST
+#define BP_USBCTRL_OTGSC_BSE            12
+#define BM_USBCTRL_OTGSC_BSE            0x1000
+#define BF_USBCTRL_OTGSC_BSE(v)         (((v) & 0x1) << 12)
+#define BFM_USBCTRL_OTGSC_BSE(v)        BM_USBCTRL_OTGSC_BSE
+#define BF_USBCTRL_OTGSC_BSE_V(e)       BF_USBCTRL_OTGSC_BSE(BV_USBCTRL_OTGSC_BSE__##e)
+#define BFM_USBCTRL_OTGSC_BSE_V(v)      BM_USBCTRL_OTGSC_BSE
+#define BP_USBCTRL_OTGSC_BSV            11
+#define BM_USBCTRL_OTGSC_BSV            0x800
+#define BF_USBCTRL_OTGSC_BSV(v)         (((v) & 0x1) << 11)
+#define BFM_USBCTRL_OTGSC_BSV(v)        BM_USBCTRL_OTGSC_BSV
+#define BF_USBCTRL_OTGSC_BSV_V(e)       BF_USBCTRL_OTGSC_BSV(BV_USBCTRL_OTGSC_BSV__##e)
+#define BFM_USBCTRL_OTGSC_BSV_V(v)      BM_USBCTRL_OTGSC_BSV
+#define BP_USBCTRL_OTGSC_ASV            10
+#define BM_USBCTRL_OTGSC_ASV            0x400
+#define BF_USBCTRL_OTGSC_ASV(v)         (((v) & 0x1) << 10)
+#define BFM_USBCTRL_OTGSC_ASV(v)        BM_USBCTRL_OTGSC_ASV
+#define BF_USBCTRL_OTGSC_ASV_V(e)       BF_USBCTRL_OTGSC_ASV(BV_USBCTRL_OTGSC_ASV__##e)
+#define BFM_USBCTRL_OTGSC_ASV_V(v)      BM_USBCTRL_OTGSC_ASV
+#define BP_USBCTRL_OTGSC_AVV            9
+#define BM_USBCTRL_OTGSC_AVV            0x200
+#define BF_USBCTRL_OTGSC_AVV(v)         (((v) & 0x1) << 9)
+#define BFM_USBCTRL_OTGSC_AVV(v)        BM_USBCTRL_OTGSC_AVV
+#define BF_USBCTRL_OTGSC_AVV_V(e)       BF_USBCTRL_OTGSC_AVV(BV_USBCTRL_OTGSC_AVV__##e)
+#define BFM_USBCTRL_OTGSC_AVV_V(v)      BM_USBCTRL_OTGSC_AVV
+#define BP_USBCTRL_OTGSC_ID             8
+#define BM_USBCTRL_OTGSC_ID             0x100
+#define BF_USBCTRL_OTGSC_ID(v)          (((v) & 0x1) << 8)
+#define BFM_USBCTRL_OTGSC_ID(v)         BM_USBCTRL_OTGSC_ID
+#define BF_USBCTRL_OTGSC_ID_V(e)        BF_USBCTRL_OTGSC_ID(BV_USBCTRL_OTGSC_ID__##e)
+#define BFM_USBCTRL_OTGSC_ID_V(v)       BM_USBCTRL_OTGSC_ID
+#define BP_USBCTRL_OTGSC_HABA           7
+#define BM_USBCTRL_OTGSC_HABA           0x80
+#define BF_USBCTRL_OTGSC_HABA(v)        (((v) & 0x1) << 7)
+#define BFM_USBCTRL_OTGSC_HABA(v)       BM_USBCTRL_OTGSC_HABA
+#define BF_USBCTRL_OTGSC_HABA_V(e)      BF_USBCTRL_OTGSC_HABA(BV_USBCTRL_OTGSC_HABA__##e)
+#define BFM_USBCTRL_OTGSC_HABA_V(v)     BM_USBCTRL_OTGSC_HABA
+#define BP_USBCTRL_OTGSC_HADP           6
+#define BM_USBCTRL_OTGSC_HADP           0x40
+#define BF_USBCTRL_OTGSC_HADP(v)        (((v) & 0x1) << 6)
+#define BFM_USBCTRL_OTGSC_HADP(v)       BM_USBCTRL_OTGSC_HADP
+#define BF_USBCTRL_OTGSC_HADP_V(e)      BF_USBCTRL_OTGSC_HADP(BV_USBCTRL_OTGSC_HADP__##e)
+#define BFM_USBCTRL_OTGSC_HADP_V(v)     BM_USBCTRL_OTGSC_HADP
+#define BP_USBCTRL_OTGSC_IDPU           5
+#define BM_USBCTRL_OTGSC_IDPU           0x20
+#define BF_USBCTRL_OTGSC_IDPU(v)        (((v) & 0x1) << 5)
+#define BFM_USBCTRL_OTGSC_IDPU(v)       BM_USBCTRL_OTGSC_IDPU
+#define BF_USBCTRL_OTGSC_IDPU_V(e)      BF_USBCTRL_OTGSC_IDPU(BV_USBCTRL_OTGSC_IDPU__##e)
+#define BFM_USBCTRL_OTGSC_IDPU_V(v)     BM_USBCTRL_OTGSC_IDPU
+#define BP_USBCTRL_OTGSC_DP             4
+#define BM_USBCTRL_OTGSC_DP             0x10
+#define BF_USBCTRL_OTGSC_DP(v)          (((v) & 0x1) << 4)
+#define BFM_USBCTRL_OTGSC_DP(v)         BM_USBCTRL_OTGSC_DP
+#define BF_USBCTRL_OTGSC_DP_V(e)        BF_USBCTRL_OTGSC_DP(BV_USBCTRL_OTGSC_DP__##e)
+#define BFM_USBCTRL_OTGSC_DP_V(v)       BM_USBCTRL_OTGSC_DP
+#define BP_USBCTRL_OTGSC_OT             3
+#define BM_USBCTRL_OTGSC_OT             0x8
+#define BF_USBCTRL_OTGSC_OT(v)          (((v) & 0x1) << 3)
+#define BFM_USBCTRL_OTGSC_OT(v)         BM_USBCTRL_OTGSC_OT
+#define BF_USBCTRL_OTGSC_OT_V(e)        BF_USBCTRL_OTGSC_OT(BV_USBCTRL_OTGSC_OT__##e)
+#define BFM_USBCTRL_OTGSC_OT_V(v)       BM_USBCTRL_OTGSC_OT
+#define BP_USBCTRL_OTGSC_HAAR           2
+#define BM_USBCTRL_OTGSC_HAAR           0x4
+#define BF_USBCTRL_OTGSC_HAAR(v)        (((v) & 0x1) << 2)
+#define BFM_USBCTRL_OTGSC_HAAR(v)       BM_USBCTRL_OTGSC_HAAR
+#define BF_USBCTRL_OTGSC_HAAR_V(e)      BF_USBCTRL_OTGSC_HAAR(BV_USBCTRL_OTGSC_HAAR__##e)
+#define BFM_USBCTRL_OTGSC_HAAR_V(v)     BM_USBCTRL_OTGSC_HAAR
+#define BP_USBCTRL_OTGSC_VC             1
+#define BM_USBCTRL_OTGSC_VC             0x2
+#define BF_USBCTRL_OTGSC_VC(v)          (((v) & 0x1) << 1)
+#define BFM_USBCTRL_OTGSC_VC(v)         BM_USBCTRL_OTGSC_VC
+#define BF_USBCTRL_OTGSC_VC_V(e)        BF_USBCTRL_OTGSC_VC(BV_USBCTRL_OTGSC_VC__##e)
+#define BFM_USBCTRL_OTGSC_VC_V(v)       BM_USBCTRL_OTGSC_VC
+#define BP_USBCTRL_OTGSC_VD             0
+#define BM_USBCTRL_OTGSC_VD             0x1
+#define BF_USBCTRL_OTGSC_VD(v)          (((v) & 0x1) << 0)
+#define BFM_USBCTRL_OTGSC_VD(v)         BM_USBCTRL_OTGSC_VD
+#define BF_USBCTRL_OTGSC_VD_V(e)        BF_USBCTRL_OTGSC_VD(BV_USBCTRL_OTGSC_VD__##e)
+#define BFM_USBCTRL_OTGSC_VD_V(v)       BM_USBCTRL_OTGSC_VD
+
+#define HW_USBCTRL_USBMODE              HW(USBCTRL_USBMODE)
+#define HWA_USBCTRL_USBMODE             (0x80080000 + 0x1a8)
+#define HWT_USBCTRL_USBMODE             HWIO_32_RW
+#define HWN_USBCTRL_USBMODE             USBCTRL_USBMODE
+#define HWI_USBCTRL_USBMODE             
+#define BP_USBCTRL_USBMODE_SDIS         4
+#define BM_USBCTRL_USBMODE_SDIS         0x10
+#define BF_USBCTRL_USBMODE_SDIS(v)      (((v) & 0x1) << 4)
+#define BFM_USBCTRL_USBMODE_SDIS(v)     BM_USBCTRL_USBMODE_SDIS
+#define BF_USBCTRL_USBMODE_SDIS_V(e)    BF_USBCTRL_USBMODE_SDIS(BV_USBCTRL_USBMODE_SDIS__##e)
+#define BFM_USBCTRL_USBMODE_SDIS_V(v)   BM_USBCTRL_USBMODE_SDIS
+#define BP_USBCTRL_USBMODE_SLOM         3
+#define BM_USBCTRL_USBMODE_SLOM         0x8
+#define BF_USBCTRL_USBMODE_SLOM(v)      (((v) & 0x1) << 3)
+#define BFM_USBCTRL_USBMODE_SLOM(v)     BM_USBCTRL_USBMODE_SLOM
+#define BF_USBCTRL_USBMODE_SLOM_V(e)    BF_USBCTRL_USBMODE_SLOM(BV_USBCTRL_USBMODE_SLOM__##e)
+#define BFM_USBCTRL_USBMODE_SLOM_V(v)   BM_USBCTRL_USBMODE_SLOM
+#define BP_USBCTRL_USBMODE_ES           2
+#define BM_USBCTRL_USBMODE_ES           0x4
+#define BF_USBCTRL_USBMODE_ES(v)        (((v) & 0x1) << 2)
+#define BFM_USBCTRL_USBMODE_ES(v)       BM_USBCTRL_USBMODE_ES
+#define BF_USBCTRL_USBMODE_ES_V(e)      BF_USBCTRL_USBMODE_ES(BV_USBCTRL_USBMODE_ES__##e)
+#define BFM_USBCTRL_USBMODE_ES_V(v)     BM_USBCTRL_USBMODE_ES
+#define BP_USBCTRL_USBMODE_CM           0
+#define BM_USBCTRL_USBMODE_CM           0x3
+#define BV_USBCTRL_USBMODE_CM__IDLE     0x0
+#define BV_USBCTRL_USBMODE_CM__DEVICE   0x2
+#define BV_USBCTRL_USBMODE_CM__HOST     0x3
+#define BF_USBCTRL_USBMODE_CM(v)        (((v) & 0x3) << 0)
+#define BFM_USBCTRL_USBMODE_CM(v)       BM_USBCTRL_USBMODE_CM
+#define BF_USBCTRL_USBMODE_CM_V(e)      BF_USBCTRL_USBMODE_CM(BV_USBCTRL_USBMODE_CM__##e)
+#define BFM_USBCTRL_USBMODE_CM_V(v)     BM_USBCTRL_USBMODE_CM
+
+#define HW_USBCTRL_ENDPTSETUPSTAT           HW(USBCTRL_ENDPTSETUPSTAT)
+#define HWA_USBCTRL_ENDPTSETUPSTAT          (0x80080000 + 0x1ac)
+#define HWT_USBCTRL_ENDPTSETUPSTAT          HWIO_32_RW
+#define HWN_USBCTRL_ENDPTSETUPSTAT          USBCTRL_ENDPTSETUPSTAT
+#define HWI_USBCTRL_ENDPTSETUPSTAT          
+#define BP_USBCTRL_ENDPTSETUPSTAT_STS       0
+#define BM_USBCTRL_ENDPTSETUPSTAT_STS       0xffff
+#define BF_USBCTRL_ENDPTSETUPSTAT_STS(v)    (((v) & 0xffff) << 0)
+#define BFM_USBCTRL_ENDPTSETUPSTAT_STS(v)   BM_USBCTRL_ENDPTSETUPSTAT_STS
+#define BF_USBCTRL_ENDPTSETUPSTAT_STS_V(e)  BF_USBCTRL_ENDPTSETUPSTAT_STS(BV_USBCTRL_ENDPTSETUPSTAT_STS__##e)
+#define BFM_USBCTRL_ENDPTSETUPSTAT_STS_V(v) BM_USBCTRL_ENDPTSETUPSTAT_STS
+
+#define HW_USBCTRL_ENDPTPRIME               HW(USBCTRL_ENDPTPRIME)
+#define HWA_USBCTRL_ENDPTPRIME              (0x80080000 + 0x1b0)
+#define HWT_USBCTRL_ENDPTPRIME              HWIO_32_RW
+#define HWN_USBCTRL_ENDPTPRIME              USBCTRL_ENDPTPRIME
+#define HWI_USBCTRL_ENDPTPRIME              
+#define BP_USBCTRL_ENDPTPRIME_PETB          16
+#define BM_USBCTRL_ENDPTPRIME_PETB          0xffff0000
+#define BF_USBCTRL_ENDPTPRIME_PETB(v)       (((v) & 0xffff) << 16)
+#define BFM_USBCTRL_ENDPTPRIME_PETB(v)      BM_USBCTRL_ENDPTPRIME_PETB
+#define BF_USBCTRL_ENDPTPRIME_PETB_V(e)     BF_USBCTRL_ENDPTPRIME_PETB(BV_USBCTRL_ENDPTPRIME_PETB__##e)
+#define BFM_USBCTRL_ENDPTPRIME_PETB_V(v)    BM_USBCTRL_ENDPTPRIME_PETB
+#define BP_USBCTRL_ENDPTPRIME_PERB          0
+#define BM_USBCTRL_ENDPTPRIME_PERB          0xffff
+#define BF_USBCTRL_ENDPTPRIME_PERB(v)       (((v) & 0xffff) << 0)
+#define BFM_USBCTRL_ENDPTPRIME_PERB(v)      BM_USBCTRL_ENDPTPRIME_PERB
+#define BF_USBCTRL_ENDPTPRIME_PERB_V(e)     BF_USBCTRL_ENDPTPRIME_PERB(BV_USBCTRL_ENDPTPRIME_PERB__##e)
+#define BFM_USBCTRL_ENDPTPRIME_PERB_V(v)    BM_USBCTRL_ENDPTPRIME_PERB
+
+#define HW_USBCTRL_ENDPTFLUSH               HW(USBCTRL_ENDPTFLUSH)
+#define HWA_USBCTRL_ENDPTFLUSH              (0x80080000 + 0x1b4)
+#define HWT_USBCTRL_ENDPTFLUSH              HWIO_32_RW
+#define HWN_USBCTRL_ENDPTFLUSH              USBCTRL_ENDPTFLUSH
+#define HWI_USBCTRL_ENDPTFLUSH              
+#define BP_USBCTRL_ENDPTFLUSH_FETB          16
+#define BM_USBCTRL_ENDPTFLUSH_FETB          0xffff0000
+#define BF_USBCTRL_ENDPTFLUSH_FETB(v)       (((v) & 0xffff) << 16)
+#define BFM_USBCTRL_ENDPTFLUSH_FETB(v)      BM_USBCTRL_ENDPTFLUSH_FETB
+#define BF_USBCTRL_ENDPTFLUSH_FETB_V(e)     BF_USBCTRL_ENDPTFLUSH_FETB(BV_USBCTRL_ENDPTFLUSH_FETB__##e)
+#define BFM_USBCTRL_ENDPTFLUSH_FETB_V(v)    BM_USBCTRL_ENDPTFLUSH_FETB
+#define BP_USBCTRL_ENDPTFLUSH_FERB          0
+#define BM_USBCTRL_ENDPTFLUSH_FERB          0xffff
+#define BF_USBCTRL_ENDPTFLUSH_FERB(v)       (((v) & 0xffff) << 0)
+#define BFM_USBCTRL_ENDPTFLUSH_FERB(v)      BM_USBCTRL_ENDPTFLUSH_FERB
+#define BF_USBCTRL_ENDPTFLUSH_FERB_V(e)     BF_USBCTRL_ENDPTFLUSH_FERB(BV_USBCTRL_ENDPTFLUSH_FERB__##e)
+#define BFM_USBCTRL_ENDPTFLUSH_FERB_V(v)    BM_USBCTRL_ENDPTFLUSH_FERB
+
+#define HW_USBCTRL_ENDPTSTATUS              HW(USBCTRL_ENDPTSTATUS)
+#define HWA_USBCTRL_ENDPTSTATUS             (0x80080000 + 0x1b8)
+#define HWT_USBCTRL_ENDPTSTATUS             HWIO_32_RW
+#define HWN_USBCTRL_ENDPTSTATUS             USBCTRL_ENDPTSTATUS
+#define HWI_USBCTRL_ENDPTSTATUS             
+#define BP_USBCTRL_ENDPTSTATUS_ETBR         16
+#define BM_USBCTRL_ENDPTSTATUS_ETBR         0xffff0000
+#define BF_USBCTRL_ENDPTSTATUS_ETBR(v)      (((v) & 0xffff) << 16)
+#define BFM_USBCTRL_ENDPTSTATUS_ETBR(v)     BM_USBCTRL_ENDPTSTATUS_ETBR
+#define BF_USBCTRL_ENDPTSTATUS_ETBR_V(e)    BF_USBCTRL_ENDPTSTATUS_ETBR(BV_USBCTRL_ENDPTSTATUS_ETBR__##e)
+#define BFM_USBCTRL_ENDPTSTATUS_ETBR_V(v)   BM_USBCTRL_ENDPTSTATUS_ETBR
+#define BP_USBCTRL_ENDPTSTATUS_ERBR         0
+#define BM_USBCTRL_ENDPTSTATUS_ERBR         0xffff
+#define BF_USBCTRL_ENDPTSTATUS_ERBR(v)      (((v) & 0xffff) << 0)
+#define BFM_USBCTRL_ENDPTSTATUS_ERBR(v)     BM_USBCTRL_ENDPTSTATUS_ERBR
+#define BF_USBCTRL_ENDPTSTATUS_ERBR_V(e)    BF_USBCTRL_ENDPTSTATUS_ERBR(BV_USBCTRL_ENDPTSTATUS_ERBR__##e)
+#define BFM_USBCTRL_ENDPTSTATUS_ERBR_V(v)   BM_USBCTRL_ENDPTSTATUS_ERBR
+
+#define HW_USBCTRL_ENDPTCOMPLETE            HW(USBCTRL_ENDPTCOMPLETE)
+#define HWA_USBCTRL_ENDPTCOMPLETE           (0x80080000 + 0x1bc)
+#define HWT_USBCTRL_ENDPTCOMPLETE           HWIO_32_RW
+#define HWN_USBCTRL_ENDPTCOMPLETE           USBCTRL_ENDPTCOMPLETE
+#define HWI_USBCTRL_ENDPTCOMPLETE           
+#define BP_USBCTRL_ENDPTCOMPLETE_ETCE       16
+#define BM_USBCTRL_ENDPTCOMPLETE_ETCE       0xffff0000
+#define BF_USBCTRL_ENDPTCOMPLETE_ETCE(v)    (((v) & 0xffff) << 16)
+#define BFM_USBCTRL_ENDPTCOMPLETE_ETCE(v)   BM_USBCTRL_ENDPTCOMPLETE_ETCE
+#define BF_USBCTRL_ENDPTCOMPLETE_ETCE_V(e)  BF_USBCTRL_ENDPTCOMPLETE_ETCE(BV_USBCTRL_ENDPTCOMPLETE_ETCE__##e)
+#define BFM_USBCTRL_ENDPTCOMPLETE_ETCE_V(v) BM_USBCTRL_ENDPTCOMPLETE_ETCE
+#define BP_USBCTRL_ENDPTCOMPLETE_ERCE       0
+#define BM_USBCTRL_ENDPTCOMPLETE_ERCE       0xffff
+#define BF_USBCTRL_ENDPTCOMPLETE_ERCE(v)    (((v) & 0xffff) << 0)
+#define BFM_USBCTRL_ENDPTCOMPLETE_ERCE(v)   BM_USBCTRL_ENDPTCOMPLETE_ERCE
+#define BF_USBCTRL_ENDPTCOMPLETE_ERCE_V(e)  BF_USBCTRL_ENDPTCOMPLETE_ERCE(BV_USBCTRL_ENDPTCOMPLETE_ERCE__##e)
+#define BFM_USBCTRL_ENDPTCOMPLETE_ERCE_V(v) BM_USBCTRL_ENDPTCOMPLETE_ERCE
+
+#define HW_USBCTRL_ENDPTCTRLn(_n1)              HW(USBCTRL_ENDPTCTRLn(_n1))
+#define HWA_USBCTRL_ENDPTCTRLn(_n1)             (0x80080000 + 0x1c0 + (_n1) * 0x4)
+#define HWT_USBCTRL_ENDPTCTRLn(_n1)             HWIO_32_RW
+#define HWN_USBCTRL_ENDPTCTRLn(_n1)             USBCTRL_ENDPTCTRLn
+#define HWI_USBCTRL_ENDPTCTRLn(_n1)             (_n1)
+#define BP_USBCTRL_ENDPTCTRLn_TXE               23
+#define BM_USBCTRL_ENDPTCTRLn_TXE               0x800000
+#define BF_USBCTRL_ENDPTCTRLn_TXE(v)            (((v) & 0x1) << 23)
+#define BFM_USBCTRL_ENDPTCTRLn_TXE(v)           BM_USBCTRL_ENDPTCTRLn_TXE
+#define BF_USBCTRL_ENDPTCTRLn_TXE_V(e)          BF_USBCTRL_ENDPTCTRLn_TXE(BV_USBCTRL_ENDPTCTRLn_TXE__##e)
+#define BFM_USBCTRL_ENDPTCTRLn_TXE_V(v)         BM_USBCTRL_ENDPTCTRLn_TXE
+#define BP_USBCTRL_ENDPTCTRLn_TXR               22
+#define BM_USBCTRL_ENDPTCTRLn_TXR               0x400000
+#define BF_USBCTRL_ENDPTCTRLn_TXR(v)            (((v) & 0x1) << 22)
+#define BFM_USBCTRL_ENDPTCTRLn_TXR(v)           BM_USBCTRL_ENDPTCTRLn_TXR
+#define BF_USBCTRL_ENDPTCTRLn_TXR_V(e)          BF_USBCTRL_ENDPTCTRLn_TXR(BV_USBCTRL_ENDPTCTRLn_TXR__##e)
+#define BFM_USBCTRL_ENDPTCTRLn_TXR_V(v)         BM_USBCTRL_ENDPTCTRLn_TXR
+#define BP_USBCTRL_ENDPTCTRLn_TXI               21
+#define BM_USBCTRL_ENDPTCTRLn_TXI               0x200000
+#define BF_USBCTRL_ENDPTCTRLn_TXI(v)            (((v) & 0x1) << 21)
+#define BFM_USBCTRL_ENDPTCTRLn_TXI(v)           BM_USBCTRL_ENDPTCTRLn_TXI
+#define BF_USBCTRL_ENDPTCTRLn_TXI_V(e)          BF_USBCTRL_ENDPTCTRLn_TXI(BV_USBCTRL_ENDPTCTRLn_TXI__##e)
+#define BFM_USBCTRL_ENDPTCTRLn_TXI_V(v)         BM_USBCTRL_ENDPTCTRLn_TXI
+#define BP_USBCTRL_ENDPTCTRLn_TXT               18
+#define BM_USBCTRL_ENDPTCTRLn_TXT               0xc0000
+#define BV_USBCTRL_ENDPTCTRLn_TXT__ISOCHRONOUS  0x1
+#define BV_USBCTRL_ENDPTCTRLn_TXT__BULK         0x2
+#define BV_USBCTRL_ENDPTCTRLn_TXT__INT          0x3
+#define BF_USBCTRL_ENDPTCTRLn_TXT(v)            (((v) & 0x3) << 18)
+#define BFM_USBCTRL_ENDPTCTRLn_TXT(v)           BM_USBCTRL_ENDPTCTRLn_TXT
+#define BF_USBCTRL_ENDPTCTRLn_TXT_V(e)          BF_USBCTRL_ENDPTCTRLn_TXT(BV_USBCTRL_ENDPTCTRLn_TXT__##e)
+#define BFM_USBCTRL_ENDPTCTRLn_TXT_V(v)         BM_USBCTRL_ENDPTCTRLn_TXT
+#define BP_USBCTRL_ENDPTCTRLn_TXS               16
+#define BM_USBCTRL_ENDPTCTRLn_TXS               0x10000
+#define BF_USBCTRL_ENDPTCTRLn_TXS(v)            (((v) & 0x1) << 16)
+#define BFM_USBCTRL_ENDPTCTRLn_TXS(v)           BM_USBCTRL_ENDPTCTRLn_TXS
+#define BF_USBCTRL_ENDPTCTRLn_TXS_V(e)          BF_USBCTRL_ENDPTCTRLn_TXS(BV_USBCTRL_ENDPTCTRLn_TXS__##e)
+#define BFM_USBCTRL_ENDPTCTRLn_TXS_V(v)         BM_USBCTRL_ENDPTCTRLn_TXS
+#define BP_USBCTRL_ENDPTCTRLn_RXE               7
+#define BM_USBCTRL_ENDPTCTRLn_RXE               0x80
+#define BF_USBCTRL_ENDPTCTRLn_RXE(v)            (((v) & 0x1) << 7)
+#define BFM_USBCTRL_ENDPTCTRLn_RXE(v)           BM_USBCTRL_ENDPTCTRLn_RXE
+#define BF_USBCTRL_ENDPTCTRLn_RXE_V(e)          BF_USBCTRL_ENDPTCTRLn_RXE(BV_USBCTRL_ENDPTCTRLn_RXE__##e)
+#define BFM_USBCTRL_ENDPTCTRLn_RXE_V(v)         BM_USBCTRL_ENDPTCTRLn_RXE
+#define BP_USBCTRL_ENDPTCTRLn_RXR               6
+#define BM_USBCTRL_ENDPTCTRLn_RXR               0x40
+#define BF_USBCTRL_ENDPTCTRLn_RXR(v)            (((v) & 0x1) << 6)
+#define BFM_USBCTRL_ENDPTCTRLn_RXR(v)           BM_USBCTRL_ENDPTCTRLn_RXR
+#define BF_USBCTRL_ENDPTCTRLn_RXR_V(e)          BF_USBCTRL_ENDPTCTRLn_RXR(BV_USBCTRL_ENDPTCTRLn_RXR__##e)
+#define BFM_USBCTRL_ENDPTCTRLn_RXR_V(v)         BM_USBCTRL_ENDPTCTRLn_RXR
+#define BP_USBCTRL_ENDPTCTRLn_RXI               5
+#define BM_USBCTRL_ENDPTCTRLn_RXI               0x20
+#define BF_USBCTRL_ENDPTCTRLn_RXI(v)            (((v) & 0x1) << 5)
+#define BFM_USBCTRL_ENDPTCTRLn_RXI(v)           BM_USBCTRL_ENDPTCTRLn_RXI
+#define BF_USBCTRL_ENDPTCTRLn_RXI_V(e)          BF_USBCTRL_ENDPTCTRLn_RXI(BV_USBCTRL_ENDPTCTRLn_RXI__##e)
+#define BFM_USBCTRL_ENDPTCTRLn_RXI_V(v)         BM_USBCTRL_ENDPTCTRLn_RXI
+#define BP_USBCTRL_ENDPTCTRLn_RXT               2
+#define BM_USBCTRL_ENDPTCTRLn_RXT               0xc
+#define BF_USBCTRL_ENDPTCTRLn_RXT(v)            (((v) & 0x3) << 2)
+#define BFM_USBCTRL_ENDPTCTRLn_RXT(v)           BM_USBCTRL_ENDPTCTRLn_RXT
+#define BF_USBCTRL_ENDPTCTRLn_RXT_V(e)          BF_USBCTRL_ENDPTCTRLn_RXT(BV_USBCTRL_ENDPTCTRLn_RXT__##e)
+#define BFM_USBCTRL_ENDPTCTRLn_RXT_V(v)         BM_USBCTRL_ENDPTCTRLn_RXT
+#define BP_USBCTRL_ENDPTCTRLn_RXS               0
+#define BM_USBCTRL_ENDPTCTRLn_RXS               0x1
+#define BF_USBCTRL_ENDPTCTRLn_RXS(v)            (((v) & 0x1) << 0)
+#define BFM_USBCTRL_ENDPTCTRLn_RXS(v)           BM_USBCTRL_ENDPTCTRLn_RXS
+#define BF_USBCTRL_ENDPTCTRLn_RXS_V(e)          BF_USBCTRL_ENDPTCTRLn_RXS(BV_USBCTRL_ENDPTCTRLn_RXS__##e)
+#define BFM_USBCTRL_ENDPTCTRLn_RXS_V(v)         BM_USBCTRL_ENDPTCTRLn_RXS
+
+#endif /* __HEADERGEN_STMP3700_USBCTRL_H__*/
diff --git a/firmware/target/arm/imx233/regs/stmp3700/usbphy.h b/firmware/target/arm/imx233/regs/stmp3700/usbphy.h
new file mode 100644
index 0000000000..6e2fa5bb3f
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3700/usbphy.h
@@ -0,0 +1,549 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * stmp3700 version: 2.4.0
+ * stmp3700 authors: Amaury Pouly
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_STMP3700_USBPHY_H__
+#define __HEADERGEN_STMP3700_USBPHY_H__
+
+#define HW_USBPHY_PWD                   HW(USBPHY_PWD)
+#define HWA_USBPHY_PWD                  (0x8007c000 + 0x0)
+#define HWT_USBPHY_PWD                  HWIO_32_RW
+#define HWN_USBPHY_PWD                  USBPHY_PWD
+#define HWI_USBPHY_PWD                  
+#define HW_USBPHY_PWD_SET               HW(USBPHY_PWD_SET)
+#define HWA_USBPHY_PWD_SET              (HWA_USBPHY_PWD + 0x4)
+#define HWT_USBPHY_PWD_SET              HWIO_32_WO
+#define HWN_USBPHY_PWD_SET              USBPHY_PWD
+#define HWI_USBPHY_PWD_SET              
+#define HW_USBPHY_PWD_CLR               HW(USBPHY_PWD_CLR)
+#define HWA_USBPHY_PWD_CLR              (HWA_USBPHY_PWD + 0x8)
+#define HWT_USBPHY_PWD_CLR              HWIO_32_WO
+#define HWN_USBPHY_PWD_CLR              USBPHY_PWD
+#define HWI_USBPHY_PWD_CLR              
+#define HW_USBPHY_PWD_TOG               HW(USBPHY_PWD_TOG)
+#define HWA_USBPHY_PWD_TOG              (HWA_USBPHY_PWD + 0xc)
+#define HWT_USBPHY_PWD_TOG              HWIO_32_WO
+#define HWN_USBPHY_PWD_TOG              USBPHY_PWD
+#define HWI_USBPHY_PWD_TOG              
+#define BP_USBPHY_PWD_RXPWDRX           20
+#define BM_USBPHY_PWD_RXPWDRX           0x100000
+#define BF_USBPHY_PWD_RXPWDRX(v)        (((v) & 0x1) << 20)
+#define BFM_USBPHY_PWD_RXPWDRX(v)       BM_USBPHY_PWD_RXPWDRX
+#define BF_USBPHY_PWD_RXPWDRX_V(e)      BF_USBPHY_PWD_RXPWDRX(BV_USBPHY_PWD_RXPWDRX__##e)
+#define BFM_USBPHY_PWD_RXPWDRX_V(v)     BM_USBPHY_PWD_RXPWDRX
+#define BP_USBPHY_PWD_RXPWDDIFF         19
+#define BM_USBPHY_PWD_RXPWDDIFF         0x80000
+#define BF_USBPHY_PWD_RXPWDDIFF(v)      (((v) & 0x1) << 19)
+#define BFM_USBPHY_PWD_RXPWDDIFF(v)     BM_USBPHY_PWD_RXPWDDIFF
+#define BF_USBPHY_PWD_RXPWDDIFF_V(e)    BF_USBPHY_PWD_RXPWDDIFF(BV_USBPHY_PWD_RXPWDDIFF__##e)
+#define BFM_USBPHY_PWD_RXPWDDIFF_V(v)   BM_USBPHY_PWD_RXPWDDIFF
+#define BP_USBPHY_PWD_RXPWD1PT1         18
+#define BM_USBPHY_PWD_RXPWD1PT1         0x40000
+#define BF_USBPHY_PWD_RXPWD1PT1(v)      (((v) & 0x1) << 18)
+#define BFM_USBPHY_PWD_RXPWD1PT1(v)     BM_USBPHY_PWD_RXPWD1PT1
+#define BF_USBPHY_PWD_RXPWD1PT1_V(e)    BF_USBPHY_PWD_RXPWD1PT1(BV_USBPHY_PWD_RXPWD1PT1__##e)
+#define BFM_USBPHY_PWD_RXPWD1PT1_V(v)   BM_USBPHY_PWD_RXPWD1PT1
+#define BP_USBPHY_PWD_RXPWDENV          17
+#define BM_USBPHY_PWD_RXPWDENV          0x20000
+#define BF_USBPHY_PWD_RXPWDENV(v)       (((v) & 0x1) << 17)
+#define BFM_USBPHY_PWD_RXPWDENV(v)      BM_USBPHY_PWD_RXPWDENV
+#define BF_USBPHY_PWD_RXPWDENV_V(e)     BF_USBPHY_PWD_RXPWDENV(BV_USBPHY_PWD_RXPWDENV__##e)
+#define BFM_USBPHY_PWD_RXPWDENV_V(v)    BM_USBPHY_PWD_RXPWDENV
+#define BP_USBPHY_PWD_TXPWDCOMP         14
+#define BM_USBPHY_PWD_TXPWDCOMP         0x4000
+#define BF_USBPHY_PWD_TXPWDCOMP(v)      (((v) & 0x1) << 14)
+#define BFM_USBPHY_PWD_TXPWDCOMP(v)     BM_USBPHY_PWD_TXPWDCOMP
+#define BF_USBPHY_PWD_TXPWDCOMP_V(e)    BF_USBPHY_PWD_TXPWDCOMP(BV_USBPHY_PWD_TXPWDCOMP__##e)
+#define BFM_USBPHY_PWD_TXPWDCOMP_V(v)   BM_USBPHY_PWD_TXPWDCOMP
+#define BP_USBPHY_PWD_TXPWDVBG          13
+#define BM_USBPHY_PWD_TXPWDVBG          0x2000
+#define BF_USBPHY_PWD_TXPWDVBG(v)       (((v) & 0x1) << 13)
+#define BFM_USBPHY_PWD_TXPWDVBG(v)      BM_USBPHY_PWD_TXPWDVBG
+#define BF_USBPHY_PWD_TXPWDVBG_V(e)     BF_USBPHY_PWD_TXPWDVBG(BV_USBPHY_PWD_TXPWDVBG__##e)
+#define BFM_USBPHY_PWD_TXPWDVBG_V(v)    BM_USBPHY_PWD_TXPWDVBG
+#define BP_USBPHY_PWD_TXPWDV2I          12
+#define BM_USBPHY_PWD_TXPWDV2I          0x1000
+#define BF_USBPHY_PWD_TXPWDV2I(v)       (((v) & 0x1) << 12)
+#define BFM_USBPHY_PWD_TXPWDV2I(v)      BM_USBPHY_PWD_TXPWDV2I
+#define BF_USBPHY_PWD_TXPWDV2I_V(e)     BF_USBPHY_PWD_TXPWDV2I(BV_USBPHY_PWD_TXPWDV2I__##e)
+#define BFM_USBPHY_PWD_TXPWDV2I_V(v)    BM_USBPHY_PWD_TXPWDV2I
+#define BP_USBPHY_PWD_TXPWDIBIAS        11
+#define BM_USBPHY_PWD_TXPWDIBIAS        0x800
+#define BF_USBPHY_PWD_TXPWDIBIAS(v)     (((v) & 0x1) << 11)
+#define BFM_USBPHY_PWD_TXPWDIBIAS(v)    BM_USBPHY_PWD_TXPWDIBIAS
+#define BF_USBPHY_PWD_TXPWDIBIAS_V(e)   BF_USBPHY_PWD_TXPWDIBIAS(BV_USBPHY_PWD_TXPWDIBIAS__##e)
+#define BFM_USBPHY_PWD_TXPWDIBIAS_V(v)  BM_USBPHY_PWD_TXPWDIBIAS
+#define BP_USBPHY_PWD_TXPWDFS           10
+#define BM_USBPHY_PWD_TXPWDFS           0x400
+#define BF_USBPHY_PWD_TXPWDFS(v)        (((v) & 0x1) << 10)
+#define BFM_USBPHY_PWD_TXPWDFS(v)       BM_USBPHY_PWD_TXPWDFS
+#define BF_USBPHY_PWD_TXPWDFS_V(e)      BF_USBPHY_PWD_TXPWDFS(BV_USBPHY_PWD_TXPWDFS__##e)
+#define BFM_USBPHY_PWD_TXPWDFS_V(v)     BM_USBPHY_PWD_TXPWDFS
+
+#define HW_USBPHY_TX                                HW(USBPHY_TX)
+#define HWA_USBPHY_TX                               (0x8007c000 + 0x10)
+#define HWT_USBPHY_TX                               HWIO_32_RW
+#define HWN_USBPHY_TX                               USBPHY_TX
+#define HWI_USBPHY_TX                               
+#define HW_USBPHY_TX_SET                            HW(USBPHY_TX_SET)
+#define HWA_USBPHY_TX_SET                           (HWA_USBPHY_TX + 0x4)
+#define HWT_USBPHY_TX_SET                           HWIO_32_WO
+#define HWN_USBPHY_TX_SET                           USBPHY_TX
+#define HWI_USBPHY_TX_SET                           
+#define HW_USBPHY_TX_CLR                            HW(USBPHY_TX_CLR)
+#define HWA_USBPHY_TX_CLR                           (HWA_USBPHY_TX + 0x8)
+#define HWT_USBPHY_TX_CLR                           HWIO_32_WO
+#define HWN_USBPHY_TX_CLR                           USBPHY_TX
+#define HWI_USBPHY_TX_CLR                           
+#define HW_USBPHY_TX_TOG                            HW(USBPHY_TX_TOG)
+#define HWA_USBPHY_TX_TOG                           (HWA_USBPHY_TX + 0xc)
+#define HWT_USBPHY_TX_TOG                           HWIO_32_WO
+#define HWN_USBPHY_TX_TOG                           USBPHY_TX
+#define HWI_USBPHY_TX_TOG                           
+#define BP_USBPHY_TX_USBPHY_TX_EDGECTRL             26
+#define BM_USBPHY_TX_USBPHY_TX_EDGECTRL             0x1c000000
+#define BF_USBPHY_TX_USBPHY_TX_EDGECTRL(v)          (((v) & 0x7) << 26)
+#define BFM_USBPHY_TX_USBPHY_TX_EDGECTRL(v)         BM_USBPHY_TX_USBPHY_TX_EDGECTRL
+#define BF_USBPHY_TX_USBPHY_TX_EDGECTRL_V(e)        BF_USBPHY_TX_USBPHY_TX_EDGECTRL(BV_USBPHY_TX_USBPHY_TX_EDGECTRL__##e)
+#define BFM_USBPHY_TX_USBPHY_TX_EDGECTRL_V(v)       BM_USBPHY_TX_USBPHY_TX_EDGECTRL
+#define BP_USBPHY_TX_USBPHY_TX_SYNC_INVERT          25
+#define BM_USBPHY_TX_USBPHY_TX_SYNC_INVERT          0x2000000
+#define BF_USBPHY_TX_USBPHY_TX_SYNC_INVERT(v)       (((v) & 0x1) << 25)
+#define BFM_USBPHY_TX_USBPHY_TX_SYNC_INVERT(v)      BM_USBPHY_TX_USBPHY_TX_SYNC_INVERT
+#define BF_USBPHY_TX_USBPHY_TX_SYNC_INVERT_V(e)     BF_USBPHY_TX_USBPHY_TX_SYNC_INVERT(BV_USBPHY_TX_USBPHY_TX_SYNC_INVERT__##e)
+#define BFM_USBPHY_TX_USBPHY_TX_SYNC_INVERT_V(v)    BM_USBPHY_TX_USBPHY_TX_SYNC_INVERT
+#define BP_USBPHY_TX_USBPHY_TX_SYNC_MUX             24
+#define BM_USBPHY_TX_USBPHY_TX_SYNC_MUX             0x1000000
+#define BF_USBPHY_TX_USBPHY_TX_SYNC_MUX(v)          (((v) & 0x1) << 24)
+#define BFM_USBPHY_TX_USBPHY_TX_SYNC_MUX(v)         BM_USBPHY_TX_USBPHY_TX_SYNC_MUX
+#define BF_USBPHY_TX_USBPHY_TX_SYNC_MUX_V(e)        BF_USBPHY_TX_USBPHY_TX_SYNC_MUX(BV_USBPHY_TX_USBPHY_TX_SYNC_MUX__##e)
+#define BFM_USBPHY_TX_USBPHY_TX_SYNC_MUX_V(v)       BM_USBPHY_TX_USBPHY_TX_SYNC_MUX
+#define BP_USBPHY_TX_TXCMPOUT_STATUS                23
+#define BM_USBPHY_TX_TXCMPOUT_STATUS                0x800000
+#define BF_USBPHY_TX_TXCMPOUT_STATUS(v)             (((v) & 0x1) << 23)
+#define BFM_USBPHY_TX_TXCMPOUT_STATUS(v)            BM_USBPHY_TX_TXCMPOUT_STATUS
+#define BF_USBPHY_TX_TXCMPOUT_STATUS_V(e)           BF_USBPHY_TX_TXCMPOUT_STATUS(BV_USBPHY_TX_TXCMPOUT_STATUS__##e)
+#define BFM_USBPHY_TX_TXCMPOUT_STATUS_V(v)          BM_USBPHY_TX_TXCMPOUT_STATUS
+#define BP_USBPHY_TX_TXENCAL45DP                    21
+#define BM_USBPHY_TX_TXENCAL45DP                    0x200000
+#define BF_USBPHY_TX_TXENCAL45DP(v)                 (((v) & 0x1) << 21)
+#define BFM_USBPHY_TX_TXENCAL45DP(v)                BM_USBPHY_TX_TXENCAL45DP
+#define BF_USBPHY_TX_TXENCAL45DP_V(e)               BF_USBPHY_TX_TXENCAL45DP(BV_USBPHY_TX_TXENCAL45DP__##e)
+#define BFM_USBPHY_TX_TXENCAL45DP_V(v)              BM_USBPHY_TX_TXENCAL45DP
+#define BP_USBPHY_TX_TXCAL45DP                      16
+#define BM_USBPHY_TX_TXCAL45DP                      0xf0000
+#define BF_USBPHY_TX_TXCAL45DP(v)                   (((v) & 0xf) << 16)
+#define BFM_USBPHY_TX_TXCAL45DP(v)                  BM_USBPHY_TX_TXCAL45DP
+#define BF_USBPHY_TX_TXCAL45DP_V(e)                 BF_USBPHY_TX_TXCAL45DP(BV_USBPHY_TX_TXCAL45DP__##e)
+#define BFM_USBPHY_TX_TXCAL45DP_V(v)                BM_USBPHY_TX_TXCAL45DP
+#define BP_USBPHY_TX_TXENCAL45DN                    13
+#define BM_USBPHY_TX_TXENCAL45DN                    0x2000
+#define BF_USBPHY_TX_TXENCAL45DN(v)                 (((v) & 0x1) << 13)
+#define BFM_USBPHY_TX_TXENCAL45DN(v)                BM_USBPHY_TX_TXENCAL45DN
+#define BF_USBPHY_TX_TXENCAL45DN_V(e)               BF_USBPHY_TX_TXENCAL45DN(BV_USBPHY_TX_TXENCAL45DN__##e)
+#define BFM_USBPHY_TX_TXENCAL45DN_V(v)              BM_USBPHY_TX_TXENCAL45DN
+#define BP_USBPHY_TX_TXCAL45DN                      8
+#define BM_USBPHY_TX_TXCAL45DN                      0xf00
+#define BF_USBPHY_TX_TXCAL45DN(v)                   (((v) & 0xf) << 8)
+#define BFM_USBPHY_TX_TXCAL45DN(v)                  BM_USBPHY_TX_TXCAL45DN
+#define BF_USBPHY_TX_TXCAL45DN_V(e)                 BF_USBPHY_TX_TXCAL45DN(BV_USBPHY_TX_TXCAL45DN__##e)
+#define BFM_USBPHY_TX_TXCAL45DN_V(v)                BM_USBPHY_TX_TXCAL45DN
+#define BP_USBPHY_TX_TXCALIBRATE                    7
+#define BM_USBPHY_TX_TXCALIBRATE                    0x80
+#define BF_USBPHY_TX_TXCALIBRATE(v)                 (((v) & 0x1) << 7)
+#define BFM_USBPHY_TX_TXCALIBRATE(v)                BM_USBPHY_TX_TXCALIBRATE
+#define BF_USBPHY_TX_TXCALIBRATE_V(e)               BF_USBPHY_TX_TXCALIBRATE(BV_USBPHY_TX_TXCALIBRATE__##e)
+#define BFM_USBPHY_TX_TXCALIBRATE_V(v)              BM_USBPHY_TX_TXCALIBRATE
+#define BP_USBPHY_TX_D_CAL                          0
+#define BM_USBPHY_TX_D_CAL                          0xf
+#define BF_USBPHY_TX_D_CAL(v)                       (((v) & 0xf) << 0)
+#define BFM_USBPHY_TX_D_CAL(v)                      BM_USBPHY_TX_D_CAL
+#define BF_USBPHY_TX_D_CAL_V(e)                     BF_USBPHY_TX_D_CAL(BV_USBPHY_TX_D_CAL__##e)
+#define BFM_USBPHY_TX_D_CAL_V(v)                    BM_USBPHY_TX_D_CAL
+
+#define HW_USBPHY_RX                    HW(USBPHY_RX)
+#define HWA_USBPHY_RX                   (0x8007c000 + 0x20)
+#define HWT_USBPHY_RX                   HWIO_32_RW
+#define HWN_USBPHY_RX                   USBPHY_RX
+#define HWI_USBPHY_RX                   
+#define HW_USBPHY_RX_SET                HW(USBPHY_RX_SET)
+#define HWA_USBPHY_RX_SET               (HWA_USBPHY_RX + 0x4)
+#define HWT_USBPHY_RX_SET               HWIO_32_WO
+#define HWN_USBPHY_RX_SET               USBPHY_RX
+#define HWI_USBPHY_RX_SET               
+#define HW_USBPHY_RX_CLR                HW(USBPHY_RX_CLR)
+#define HWA_USBPHY_RX_CLR               (HWA_USBPHY_RX + 0x8)
+#define HWT_USBPHY_RX_CLR               HWIO_32_WO
+#define HWN_USBPHY_RX_CLR               USBPHY_RX
+#define HWI_USBPHY_RX_CLR               
+#define HW_USBPHY_RX_TOG                HW(USBPHY_RX_TOG)
+#define HWA_USBPHY_RX_TOG               (HWA_USBPHY_RX + 0xc)
+#define HWT_USBPHY_RX_TOG               HWIO_32_WO
+#define HWN_USBPHY_RX_TOG               USBPHY_RX
+#define HWI_USBPHY_RX_TOG               
+#define BP_USBPHY_RX_RXDBYPASS          22
+#define BM_USBPHY_RX_RXDBYPASS          0x400000
+#define BF_USBPHY_RX_RXDBYPASS(v)       (((v) & 0x1) << 22)
+#define BFM_USBPHY_RX_RXDBYPASS(v)      BM_USBPHY_RX_RXDBYPASS
+#define BF_USBPHY_RX_RXDBYPASS_V(e)     BF_USBPHY_RX_RXDBYPASS(BV_USBPHY_RX_RXDBYPASS__##e)
+#define BFM_USBPHY_RX_RXDBYPASS_V(v)    BM_USBPHY_RX_RXDBYPASS
+#define BP_USBPHY_RX_DISCONADJ          4
+#define BM_USBPHY_RX_DISCONADJ          0x30
+#define BF_USBPHY_RX_DISCONADJ(v)       (((v) & 0x3) << 4)
+#define BFM_USBPHY_RX_DISCONADJ(v)      BM_USBPHY_RX_DISCONADJ
+#define BF_USBPHY_RX_DISCONADJ_V(e)     BF_USBPHY_RX_DISCONADJ(BV_USBPHY_RX_DISCONADJ__##e)
+#define BFM_USBPHY_RX_DISCONADJ_V(v)    BM_USBPHY_RX_DISCONADJ
+#define BP_USBPHY_RX_ENVADJ             0
+#define BM_USBPHY_RX_ENVADJ             0x3
+#define BF_USBPHY_RX_ENVADJ(v)          (((v) & 0x3) << 0)
+#define BFM_USBPHY_RX_ENVADJ(v)         BM_USBPHY_RX_ENVADJ
+#define BF_USBPHY_RX_ENVADJ_V(e)        BF_USBPHY_RX_ENVADJ(BV_USBPHY_RX_ENVADJ__##e)
+#define BFM_USBPHY_RX_ENVADJ_V(v)       BM_USBPHY_RX_ENVADJ
+
+#define HW_USBPHY_CTRL                              HW(USBPHY_CTRL)
+#define HWA_USBPHY_CTRL                             (0x8007c000 + 0x30)
+#define HWT_USBPHY_CTRL                             HWIO_32_RW
+#define HWN_USBPHY_CTRL                             USBPHY_CTRL
+#define HWI_USBPHY_CTRL                             
+#define HW_USBPHY_CTRL_SET                          HW(USBPHY_CTRL_SET)
+#define HWA_USBPHY_CTRL_SET                         (HWA_USBPHY_CTRL + 0x4)
+#define HWT_USBPHY_CTRL_SET                         HWIO_32_WO
+#define HWN_USBPHY_CTRL_SET                         USBPHY_CTRL
+#define HWI_USBPHY_CTRL_SET                         
+#define HW_USBPHY_CTRL_CLR                          HW(USBPHY_CTRL_CLR)
+#define HWA_USBPHY_CTRL_CLR                         (HWA_USBPHY_CTRL + 0x8)
+#define HWT_USBPHY_CTRL_CLR                         HWIO_32_WO
+#define HWN_USBPHY_CTRL_CLR                         USBPHY_CTRL
+#define HWI_USBPHY_CTRL_CLR                         
+#define HW_USBPHY_CTRL_TOG                          HW(USBPHY_CTRL_TOG)
+#define HWA_USBPHY_CTRL_TOG                         (HWA_USBPHY_CTRL + 0xc)
+#define HWT_USBPHY_CTRL_TOG                         HWIO_32_WO
+#define HWN_USBPHY_CTRL_TOG                         USBPHY_CTRL
+#define HWI_USBPHY_CTRL_TOG                         
+#define BP_USBPHY_CTRL_SFTRST                       31
+#define BM_USBPHY_CTRL_SFTRST                       0x80000000
+#define BF_USBPHY_CTRL_SFTRST(v)                    (((v) & 0x1) << 31)
+#define BFM_USBPHY_CTRL_SFTRST(v)                   BM_USBPHY_CTRL_SFTRST
+#define BF_USBPHY_CTRL_SFTRST_V(e)                  BF_USBPHY_CTRL_SFTRST(BV_USBPHY_CTRL_SFTRST__##e)
+#define BFM_USBPHY_CTRL_SFTRST_V(v)                 BM_USBPHY_CTRL_SFTRST
+#define BP_USBPHY_CTRL_CLKGATE                      30
+#define BM_USBPHY_CTRL_CLKGATE                      0x40000000
+#define BF_USBPHY_CTRL_CLKGATE(v)                   (((v) & 0x1) << 30)
+#define BFM_USBPHY_CTRL_CLKGATE(v)                  BM_USBPHY_CTRL_CLKGATE
+#define BF_USBPHY_CTRL_CLKGATE_V(e)                 BF_USBPHY_CTRL_CLKGATE(BV_USBPHY_CTRL_CLKGATE__##e)
+#define BFM_USBPHY_CTRL_CLKGATE_V(v)                BM_USBPHY_CTRL_CLKGATE
+#define BP_USBPHY_CTRL_UTMI_SUSPENDM                29
+#define BM_USBPHY_CTRL_UTMI_SUSPENDM                0x20000000
+#define BF_USBPHY_CTRL_UTMI_SUSPENDM(v)             (((v) & 0x1) << 29)
+#define BFM_USBPHY_CTRL_UTMI_SUSPENDM(v)            BM_USBPHY_CTRL_UTMI_SUSPENDM
+#define BF_USBPHY_CTRL_UTMI_SUSPENDM_V(e)           BF_USBPHY_CTRL_UTMI_SUSPENDM(BV_USBPHY_CTRL_UTMI_SUSPENDM__##e)
+#define BFM_USBPHY_CTRL_UTMI_SUSPENDM_V(v)          BM_USBPHY_CTRL_UTMI_SUSPENDM
+#define BP_USBPHY_CTRL_HOST_FORCE_LS_SE0            28
+#define BM_USBPHY_CTRL_HOST_FORCE_LS_SE0            0x10000000
+#define BF_USBPHY_CTRL_HOST_FORCE_LS_SE0(v)         (((v) & 0x1) << 28)
+#define BFM_USBPHY_CTRL_HOST_FORCE_LS_SE0(v)        BM_USBPHY_CTRL_HOST_FORCE_LS_SE0
+#define BF_USBPHY_CTRL_HOST_FORCE_LS_SE0_V(e)       BF_USBPHY_CTRL_HOST_FORCE_LS_SE0(BV_USBPHY_CTRL_HOST_FORCE_LS_SE0__##e)
+#define BFM_USBPHY_CTRL_HOST_FORCE_LS_SE0_V(v)      BM_USBPHY_CTRL_HOST_FORCE_LS_SE0
+#define BP_USBPHY_CTRL_DATA_ON_LRADC                13
+#define BM_USBPHY_CTRL_DATA_ON_LRADC                0x2000
+#define BF_USBPHY_CTRL_DATA_ON_LRADC(v)             (((v) & 0x1) << 13)
+#define BFM_USBPHY_CTRL_DATA_ON_LRADC(v)            BM_USBPHY_CTRL_DATA_ON_LRADC
+#define BF_USBPHY_CTRL_DATA_ON_LRADC_V(e)           BF_USBPHY_CTRL_DATA_ON_LRADC(BV_USBPHY_CTRL_DATA_ON_LRADC__##e)
+#define BFM_USBPHY_CTRL_DATA_ON_LRADC_V(v)          BM_USBPHY_CTRL_DATA_ON_LRADC
+#define BP_USBPHY_CTRL_DEVPLUGIN_IRQ                12
+#define BM_USBPHY_CTRL_DEVPLUGIN_IRQ                0x1000
+#define BF_USBPHY_CTRL_DEVPLUGIN_IRQ(v)             (((v) & 0x1) << 12)
+#define BFM_USBPHY_CTRL_DEVPLUGIN_IRQ(v)            BM_USBPHY_CTRL_DEVPLUGIN_IRQ
+#define BF_USBPHY_CTRL_DEVPLUGIN_IRQ_V(e)           BF_USBPHY_CTRL_DEVPLUGIN_IRQ(BV_USBPHY_CTRL_DEVPLUGIN_IRQ__##e)
+#define BFM_USBPHY_CTRL_DEVPLUGIN_IRQ_V(v)          BM_USBPHY_CTRL_DEVPLUGIN_IRQ
+#define BP_USBPHY_CTRL_ENIRQDEVPLUGIN               11
+#define BM_USBPHY_CTRL_ENIRQDEVPLUGIN               0x800
+#define BF_USBPHY_CTRL_ENIRQDEVPLUGIN(v)            (((v) & 0x1) << 11)
+#define BFM_USBPHY_CTRL_ENIRQDEVPLUGIN(v)           BM_USBPHY_CTRL_ENIRQDEVPLUGIN
+#define BF_USBPHY_CTRL_ENIRQDEVPLUGIN_V(e)          BF_USBPHY_CTRL_ENIRQDEVPLUGIN(BV_USBPHY_CTRL_ENIRQDEVPLUGIN__##e)
+#define BFM_USBPHY_CTRL_ENIRQDEVPLUGIN_V(v)         BM_USBPHY_CTRL_ENIRQDEVPLUGIN
+#define BP_USBPHY_CTRL_RESUME_IRQ                   10
+#define BM_USBPHY_CTRL_RESUME_IRQ                   0x400
+#define BF_USBPHY_CTRL_RESUME_IRQ(v)                (((v) & 0x1) << 10)
+#define BFM_USBPHY_CTRL_RESUME_IRQ(v)               BM_USBPHY_CTRL_RESUME_IRQ
+#define BF_USBPHY_CTRL_RESUME_IRQ_V(e)              BF_USBPHY_CTRL_RESUME_IRQ(BV_USBPHY_CTRL_RESUME_IRQ__##e)
+#define BFM_USBPHY_CTRL_RESUME_IRQ_V(v)             BM_USBPHY_CTRL_RESUME_IRQ
+#define BP_USBPHY_CTRL_ENIRQRESUMEDETECT            9
+#define BM_USBPHY_CTRL_ENIRQRESUMEDETECT            0x200
+#define BF_USBPHY_CTRL_ENIRQRESUMEDETECT(v)         (((v) & 0x1) << 9)
+#define BFM_USBPHY_CTRL_ENIRQRESUMEDETECT(v)        BM_USBPHY_CTRL_ENIRQRESUMEDETECT
+#define BF_USBPHY_CTRL_ENIRQRESUMEDETECT_V(e)       BF_USBPHY_CTRL_ENIRQRESUMEDETECT(BV_USBPHY_CTRL_ENIRQRESUMEDETECT__##e)
+#define BFM_USBPHY_CTRL_ENIRQRESUMEDETECT_V(v)      BM_USBPHY_CTRL_ENIRQRESUMEDETECT
+#define BP_USBPHY_CTRL_ENOTGIDDETECT                7
+#define BM_USBPHY_CTRL_ENOTGIDDETECT                0x80
+#define BF_USBPHY_CTRL_ENOTGIDDETECT(v)             (((v) & 0x1) << 7)
+#define BFM_USBPHY_CTRL_ENOTGIDDETECT(v)            BM_USBPHY_CTRL_ENOTGIDDETECT
+#define BF_USBPHY_CTRL_ENOTGIDDETECT_V(e)           BF_USBPHY_CTRL_ENOTGIDDETECT(BV_USBPHY_CTRL_ENOTGIDDETECT__##e)
+#define BFM_USBPHY_CTRL_ENOTGIDDETECT_V(v)          BM_USBPHY_CTRL_ENOTGIDDETECT
+#define BP_USBPHY_CTRL_DEVPLUGIN_POLARITY           5
+#define BM_USBPHY_CTRL_DEVPLUGIN_POLARITY           0x20
+#define BF_USBPHY_CTRL_DEVPLUGIN_POLARITY(v)        (((v) & 0x1) << 5)
+#define BFM_USBPHY_CTRL_DEVPLUGIN_POLARITY(v)       BM_USBPHY_CTRL_DEVPLUGIN_POLARITY
+#define BF_USBPHY_CTRL_DEVPLUGIN_POLARITY_V(e)      BF_USBPHY_CTRL_DEVPLUGIN_POLARITY(BV_USBPHY_CTRL_DEVPLUGIN_POLARITY__##e)
+#define BFM_USBPHY_CTRL_DEVPLUGIN_POLARITY_V(v)     BM_USBPHY_CTRL_DEVPLUGIN_POLARITY
+#define BP_USBPHY_CTRL_ENDEVPLUGINDETECT            4
+#define BM_USBPHY_CTRL_ENDEVPLUGINDETECT            0x10
+#define BF_USBPHY_CTRL_ENDEVPLUGINDETECT(v)         (((v) & 0x1) << 4)
+#define BFM_USBPHY_CTRL_ENDEVPLUGINDETECT(v)        BM_USBPHY_CTRL_ENDEVPLUGINDETECT
+#define BF_USBPHY_CTRL_ENDEVPLUGINDETECT_V(e)       BF_USBPHY_CTRL_ENDEVPLUGINDETECT(BV_USBPHY_CTRL_ENDEVPLUGINDETECT__##e)
+#define BFM_USBPHY_CTRL_ENDEVPLUGINDETECT_V(v)      BM_USBPHY_CTRL_ENDEVPLUGINDETECT
+#define BP_USBPHY_CTRL_HOSTDISCONDETECT_IRQ         3
+#define BM_USBPHY_CTRL_HOSTDISCONDETECT_IRQ         0x8
+#define BF_USBPHY_CTRL_HOSTDISCONDETECT_IRQ(v)      (((v) & 0x1) << 3)
+#define BFM_USBPHY_CTRL_HOSTDISCONDETECT_IRQ(v)     BM_USBPHY_CTRL_HOSTDISCONDETECT_IRQ
+#define BF_USBPHY_CTRL_HOSTDISCONDETECT_IRQ_V(e)    BF_USBPHY_CTRL_HOSTDISCONDETECT_IRQ(BV_USBPHY_CTRL_HOSTDISCONDETECT_IRQ__##e)
+#define BFM_USBPHY_CTRL_HOSTDISCONDETECT_IRQ_V(v)   BM_USBPHY_CTRL_HOSTDISCONDETECT_IRQ
+#define BP_USBPHY_CTRL_ENIRQHOSTDISCON              2
+#define BM_USBPHY_CTRL_ENIRQHOSTDISCON              0x4
+#define BF_USBPHY_CTRL_ENIRQHOSTDISCON(v)           (((v) & 0x1) << 2)
+#define BFM_USBPHY_CTRL_ENIRQHOSTDISCON(v)          BM_USBPHY_CTRL_ENIRQHOSTDISCON
+#define BF_USBPHY_CTRL_ENIRQHOSTDISCON_V(e)         BF_USBPHY_CTRL_ENIRQHOSTDISCON(BV_USBPHY_CTRL_ENIRQHOSTDISCON__##e)
+#define BFM_USBPHY_CTRL_ENIRQHOSTDISCON_V(v)        BM_USBPHY_CTRL_ENIRQHOSTDISCON
+#define BP_USBPHY_CTRL_ENHOSTDISCONDETECT           1
+#define BM_USBPHY_CTRL_ENHOSTDISCONDETECT           0x2
+#define BF_USBPHY_CTRL_ENHOSTDISCONDETECT(v)        (((v) & 0x1) << 1)
+#define BFM_USBPHY_CTRL_ENHOSTDISCONDETECT(v)       BM_USBPHY_CTRL_ENHOSTDISCONDETECT
+#define BF_USBPHY_CTRL_ENHOSTDISCONDETECT_V(e)      BF_USBPHY_CTRL_ENHOSTDISCONDETECT(BV_USBPHY_CTRL_ENHOSTDISCONDETECT__##e)
+#define BFM_USBPHY_CTRL_ENHOSTDISCONDETECT_V(v)     BM_USBPHY_CTRL_ENHOSTDISCONDETECT
+#define BP_USBPHY_CTRL_ENHSPRECHARGEXMIT            0
+#define BM_USBPHY_CTRL_ENHSPRECHARGEXMIT            0x1
+#define BF_USBPHY_CTRL_ENHSPRECHARGEXMIT(v)         (((v) & 0x1) << 0)
+#define BFM_USBPHY_CTRL_ENHSPRECHARGEXMIT(v)        BM_USBPHY_CTRL_ENHSPRECHARGEXMIT
+#define BF_USBPHY_CTRL_ENHSPRECHARGEXMIT_V(e)       BF_USBPHY_CTRL_ENHSPRECHARGEXMIT(BV_USBPHY_CTRL_ENHSPRECHARGEXMIT__##e)
+#define BFM_USBPHY_CTRL_ENHSPRECHARGEXMIT_V(v)      BM_USBPHY_CTRL_ENHSPRECHARGEXMIT
+
+#define HW_USBPHY_STATUS                                HW(USBPHY_STATUS)
+#define HWA_USBPHY_STATUS                               (0x8007c000 + 0x40)
+#define HWT_USBPHY_STATUS                               HWIO_32_RW
+#define HWN_USBPHY_STATUS                               USBPHY_STATUS
+#define HWI_USBPHY_STATUS                               
+#define BP_USBPHY_STATUS_RESUME_STATUS                  10
+#define BM_USBPHY_STATUS_RESUME_STATUS                  0x400
+#define BF_USBPHY_STATUS_RESUME_STATUS(v)               (((v) & 0x1) << 10)
+#define BFM_USBPHY_STATUS_RESUME_STATUS(v)              BM_USBPHY_STATUS_RESUME_STATUS
+#define BF_USBPHY_STATUS_RESUME_STATUS_V(e)             BF_USBPHY_STATUS_RESUME_STATUS(BV_USBPHY_STATUS_RESUME_STATUS__##e)
+#define BFM_USBPHY_STATUS_RESUME_STATUS_V(v)            BM_USBPHY_STATUS_RESUME_STATUS
+#define BP_USBPHY_STATUS_OTGID_STATUS                   8
+#define BM_USBPHY_STATUS_OTGID_STATUS                   0x100
+#define BF_USBPHY_STATUS_OTGID_STATUS(v)                (((v) & 0x1) << 8)
+#define BFM_USBPHY_STATUS_OTGID_STATUS(v)               BM_USBPHY_STATUS_OTGID_STATUS
+#define BF_USBPHY_STATUS_OTGID_STATUS_V(e)              BF_USBPHY_STATUS_OTGID_STATUS(BV_USBPHY_STATUS_OTGID_STATUS__##e)
+#define BFM_USBPHY_STATUS_OTGID_STATUS_V(v)             BM_USBPHY_STATUS_OTGID_STATUS
+#define BP_USBPHY_STATUS_DEVPLUGIN_STATUS               6
+#define BM_USBPHY_STATUS_DEVPLUGIN_STATUS               0x40
+#define BF_USBPHY_STATUS_DEVPLUGIN_STATUS(v)            (((v) & 0x1) << 6)
+#define BFM_USBPHY_STATUS_DEVPLUGIN_STATUS(v)           BM_USBPHY_STATUS_DEVPLUGIN_STATUS
+#define BF_USBPHY_STATUS_DEVPLUGIN_STATUS_V(e)          BF_USBPHY_STATUS_DEVPLUGIN_STATUS(BV_USBPHY_STATUS_DEVPLUGIN_STATUS__##e)
+#define BFM_USBPHY_STATUS_DEVPLUGIN_STATUS_V(v)         BM_USBPHY_STATUS_DEVPLUGIN_STATUS
+#define BP_USBPHY_STATUS_HOSTDISCONDETECT_STATUS        3
+#define BM_USBPHY_STATUS_HOSTDISCONDETECT_STATUS        0x8
+#define BF_USBPHY_STATUS_HOSTDISCONDETECT_STATUS(v)     (((v) & 0x1) << 3)
+#define BFM_USBPHY_STATUS_HOSTDISCONDETECT_STATUS(v)    BM_USBPHY_STATUS_HOSTDISCONDETECT_STATUS
+#define BF_USBPHY_STATUS_HOSTDISCONDETECT_STATUS_V(e)   BF_USBPHY_STATUS_HOSTDISCONDETECT_STATUS(BV_USBPHY_STATUS_HOSTDISCONDETECT_STATUS__##e)
+#define BFM_USBPHY_STATUS_HOSTDISCONDETECT_STATUS_V(v)  BM_USBPHY_STATUS_HOSTDISCONDETECT_STATUS
+
+#define HW_USBPHY_DEBUG                             HW(USBPHY_DEBUG)
+#define HWA_USBPHY_DEBUG                            (0x8007c000 + 0x50)
+#define HWT_USBPHY_DEBUG                            HWIO_32_RW
+#define HWN_USBPHY_DEBUG                            USBPHY_DEBUG
+#define HWI_USBPHY_DEBUG                            
+#define HW_USBPHY_DEBUG_SET                         HW(USBPHY_DEBUG_SET)
+#define HWA_USBPHY_DEBUG_SET                        (HWA_USBPHY_DEBUG + 0x4)
+#define HWT_USBPHY_DEBUG_SET                        HWIO_32_WO
+#define HWN_USBPHY_DEBUG_SET                        USBPHY_DEBUG
+#define HWI_USBPHY_DEBUG_SET                        
+#define HW_USBPHY_DEBUG_CLR                         HW(USBPHY_DEBUG_CLR)
+#define HWA_USBPHY_DEBUG_CLR                        (HWA_USBPHY_DEBUG + 0x8)
+#define HWT_USBPHY_DEBUG_CLR                        HWIO_32_WO
+#define HWN_USBPHY_DEBUG_CLR                        USBPHY_DEBUG
+#define HWI_USBPHY_DEBUG_CLR                        
+#define HW_USBPHY_DEBUG_TOG                         HW(USBPHY_DEBUG_TOG)
+#define HWA_USBPHY_DEBUG_TOG                        (HWA_USBPHY_DEBUG + 0xc)
+#define HWT_USBPHY_DEBUG_TOG                        HWIO_32_WO
+#define HWN_USBPHY_DEBUG_TOG                        USBPHY_DEBUG
+#define HWI_USBPHY_DEBUG_TOG                        
+#define BP_USBPHY_DEBUG_CLKGATE                     30
+#define BM_USBPHY_DEBUG_CLKGATE                     0x40000000
+#define BF_USBPHY_DEBUG_CLKGATE(v)                  (((v) & 0x1) << 30)
+#define BFM_USBPHY_DEBUG_CLKGATE(v)                 BM_USBPHY_DEBUG_CLKGATE
+#define BF_USBPHY_DEBUG_CLKGATE_V(e)                BF_USBPHY_DEBUG_CLKGATE(BV_USBPHY_DEBUG_CLKGATE__##e)
+#define BFM_USBPHY_DEBUG_CLKGATE_V(v)               BM_USBPHY_DEBUG_CLKGATE
+#define BP_USBPHY_DEBUG_HOST_RESUME_DEBUG           29
+#define BM_USBPHY_DEBUG_HOST_RESUME_DEBUG           0x20000000
+#define BF_USBPHY_DEBUG_HOST_RESUME_DEBUG(v)        (((v) & 0x1) << 29)
+#define BFM_USBPHY_DEBUG_HOST_RESUME_DEBUG(v)       BM_USBPHY_DEBUG_HOST_RESUME_DEBUG
+#define BF_USBPHY_DEBUG_HOST_RESUME_DEBUG_V(e)      BF_USBPHY_DEBUG_HOST_RESUME_DEBUG(BV_USBPHY_DEBUG_HOST_RESUME_DEBUG__##e)
+#define BFM_USBPHY_DEBUG_HOST_RESUME_DEBUG_V(v)     BM_USBPHY_DEBUG_HOST_RESUME_DEBUG
+#define BP_USBPHY_DEBUG_SQUELCHRESETLENGTH          25
+#define BM_USBPHY_DEBUG_SQUELCHRESETLENGTH          0x1e000000
+#define BF_USBPHY_DEBUG_SQUELCHRESETLENGTH(v)       (((v) & 0xf) << 25)
+#define BFM_USBPHY_DEBUG_SQUELCHRESETLENGTH(v)      BM_USBPHY_DEBUG_SQUELCHRESETLENGTH
+#define BF_USBPHY_DEBUG_SQUELCHRESETLENGTH_V(e)     BF_USBPHY_DEBUG_SQUELCHRESETLENGTH(BV_USBPHY_DEBUG_SQUELCHRESETLENGTH__##e)
+#define BFM_USBPHY_DEBUG_SQUELCHRESETLENGTH_V(v)    BM_USBPHY_DEBUG_SQUELCHRESETLENGTH
+#define BP_USBPHY_DEBUG_ENSQUELCHRESET              24
+#define BM_USBPHY_DEBUG_ENSQUELCHRESET              0x1000000
+#define BF_USBPHY_DEBUG_ENSQUELCHRESET(v)           (((v) & 0x1) << 24)
+#define BFM_USBPHY_DEBUG_ENSQUELCHRESET(v)          BM_USBPHY_DEBUG_ENSQUELCHRESET
+#define BF_USBPHY_DEBUG_ENSQUELCHRESET_V(e)         BF_USBPHY_DEBUG_ENSQUELCHRESET(BV_USBPHY_DEBUG_ENSQUELCHRESET__##e)
+#define BFM_USBPHY_DEBUG_ENSQUELCHRESET_V(v)        BM_USBPHY_DEBUG_ENSQUELCHRESET
+#define BP_USBPHY_DEBUG_SQUELCHRESETCOUNT           16
+#define BM_USBPHY_DEBUG_SQUELCHRESETCOUNT           0x1f0000
+#define BF_USBPHY_DEBUG_SQUELCHRESETCOUNT(v)        (((v) & 0x1f) << 16)
+#define BFM_USBPHY_DEBUG_SQUELCHRESETCOUNT(v)       BM_USBPHY_DEBUG_SQUELCHRESETCOUNT
+#define BF_USBPHY_DEBUG_SQUELCHRESETCOUNT_V(e)      BF_USBPHY_DEBUG_SQUELCHRESETCOUNT(BV_USBPHY_DEBUG_SQUELCHRESETCOUNT__##e)
+#define BFM_USBPHY_DEBUG_SQUELCHRESETCOUNT_V(v)     BM_USBPHY_DEBUG_SQUELCHRESETCOUNT
+#define BP_USBPHY_DEBUG_ENTX2RXCOUNT                12
+#define BM_USBPHY_DEBUG_ENTX2RXCOUNT                0x1000
+#define BF_USBPHY_DEBUG_ENTX2RXCOUNT(v)             (((v) & 0x1) << 12)
+#define BFM_USBPHY_DEBUG_ENTX2RXCOUNT(v)            BM_USBPHY_DEBUG_ENTX2RXCOUNT
+#define BF_USBPHY_DEBUG_ENTX2RXCOUNT_V(e)           BF_USBPHY_DEBUG_ENTX2RXCOUNT(BV_USBPHY_DEBUG_ENTX2RXCOUNT__##e)
+#define BFM_USBPHY_DEBUG_ENTX2RXCOUNT_V(v)          BM_USBPHY_DEBUG_ENTX2RXCOUNT
+#define BP_USBPHY_DEBUG_TX2RXCOUNT                  8
+#define BM_USBPHY_DEBUG_TX2RXCOUNT                  0xf00
+#define BF_USBPHY_DEBUG_TX2RXCOUNT(v)               (((v) & 0xf) << 8)
+#define BFM_USBPHY_DEBUG_TX2RXCOUNT(v)              BM_USBPHY_DEBUG_TX2RXCOUNT
+#define BF_USBPHY_DEBUG_TX2RXCOUNT_V(e)             BF_USBPHY_DEBUG_TX2RXCOUNT(BV_USBPHY_DEBUG_TX2RXCOUNT__##e)
+#define BFM_USBPHY_DEBUG_TX2RXCOUNT_V(v)            BM_USBPHY_DEBUG_TX2RXCOUNT
+#define BP_USBPHY_DEBUG_ENHSTPULLDOWN               4
+#define BM_USBPHY_DEBUG_ENHSTPULLDOWN               0x30
+#define BF_USBPHY_DEBUG_ENHSTPULLDOWN(v)            (((v) & 0x3) << 4)
+#define BFM_USBPHY_DEBUG_ENHSTPULLDOWN(v)           BM_USBPHY_DEBUG_ENHSTPULLDOWN
+#define BF_USBPHY_DEBUG_ENHSTPULLDOWN_V(e)          BF_USBPHY_DEBUG_ENHSTPULLDOWN(BV_USBPHY_DEBUG_ENHSTPULLDOWN__##e)
+#define BFM_USBPHY_DEBUG_ENHSTPULLDOWN_V(v)         BM_USBPHY_DEBUG_ENHSTPULLDOWN
+#define BP_USBPHY_DEBUG_HSTPULLDOWN                 2
+#define BM_USBPHY_DEBUG_HSTPULLDOWN                 0xc
+#define BF_USBPHY_DEBUG_HSTPULLDOWN(v)              (((v) & 0x3) << 2)
+#define BFM_USBPHY_DEBUG_HSTPULLDOWN(v)             BM_USBPHY_DEBUG_HSTPULLDOWN
+#define BF_USBPHY_DEBUG_HSTPULLDOWN_V(e)            BF_USBPHY_DEBUG_HSTPULLDOWN(BV_USBPHY_DEBUG_HSTPULLDOWN__##e)
+#define BFM_USBPHY_DEBUG_HSTPULLDOWN_V(v)           BM_USBPHY_DEBUG_HSTPULLDOWN
+#define BP_USBPHY_DEBUG_DEBUG_INTERFACE_HOLD        1
+#define BM_USBPHY_DEBUG_DEBUG_INTERFACE_HOLD        0x2
+#define BF_USBPHY_DEBUG_DEBUG_INTERFACE_HOLD(v)     (((v) & 0x1) << 1)
+#define BFM_USBPHY_DEBUG_DEBUG_INTERFACE_HOLD(v)    BM_USBPHY_DEBUG_DEBUG_INTERFACE_HOLD
+#define BF_USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_V(e)   BF_USBPHY_DEBUG_DEBUG_INTERFACE_HOLD(BV_USBPHY_DEBUG_DEBUG_INTERFACE_HOLD__##e)
+#define BFM_USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_V(v)  BM_USBPHY_DEBUG_DEBUG_INTERFACE_HOLD
+#define BP_USBPHY_DEBUG_OTGIDPIOLOCK                0
+#define BM_USBPHY_DEBUG_OTGIDPIOLOCK                0x1
+#define BF_USBPHY_DEBUG_OTGIDPIOLOCK(v)             (((v) & 0x1) << 0)
+#define BFM_USBPHY_DEBUG_OTGIDPIOLOCK(v)            BM_USBPHY_DEBUG_OTGIDPIOLOCK
+#define BF_USBPHY_DEBUG_OTGIDPIOLOCK_V(e)           BF_USBPHY_DEBUG_OTGIDPIOLOCK(BV_USBPHY_DEBUG_OTGIDPIOLOCK__##e)
+#define BFM_USBPHY_DEBUG_OTGIDPIOLOCK_V(v)          BM_USBPHY_DEBUG_OTGIDPIOLOCK
+
+#define HW_USBPHY_DEBUG0_STATUS                                 HW(USBPHY_DEBUG0_STATUS)
+#define HWA_USBPHY_DEBUG0_STATUS                                (0x8007c000 + 0x60)
+#define HWT_USBPHY_DEBUG0_STATUS                                HWIO_32_RW
+#define HWN_USBPHY_DEBUG0_STATUS                                USBPHY_DEBUG0_STATUS
+#define HWI_USBPHY_DEBUG0_STATUS                                
+#define BP_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT                   26
+#define BM_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT                   0xfc000000
+#define BF_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT(v)                (((v) & 0x3f) << 26)
+#define BFM_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT(v)               BM_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT
+#define BF_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_V(e)              BF_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT(BV_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT__##e)
+#define BFM_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_V(v)             BM_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT
+#define BP_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT         16
+#define BM_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT         0x3ff0000
+#define BF_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT(v)      (((v) & 0x3ff) << 16)
+#define BFM_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT(v)     BM_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT
+#define BF_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_V(e)    BF_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT(BV_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT__##e)
+#define BFM_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_V(v)   BM_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT
+#define BP_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT            0
+#define BM_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT            0xffff
+#define BF_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT(v)         (((v) & 0xffff) << 0)
+#define BFM_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT(v)        BM_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT
+#define BF_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_V(e)       BF_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT(BV_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT__##e)
+#define BFM_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_V(v)      BM_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT
+
+#define HW_USBPHY_DEBUG1                    HW(USBPHY_DEBUG1)
+#define HWA_USBPHY_DEBUG1                   (0x8007c000 + 0x70)
+#define HWT_USBPHY_DEBUG1                   HWIO_32_RW
+#define HWN_USBPHY_DEBUG1                   USBPHY_DEBUG1
+#define HWI_USBPHY_DEBUG1                   
+#define HW_USBPHY_DEBUG1_SET                HW(USBPHY_DEBUG1_SET)
+#define HWA_USBPHY_DEBUG1_SET               (HWA_USBPHY_DEBUG1 + 0x4)
+#define HWT_USBPHY_DEBUG1_SET               HWIO_32_WO
+#define HWN_USBPHY_DEBUG1_SET               USBPHY_DEBUG1
+#define HWI_USBPHY_DEBUG1_SET               
+#define HW_USBPHY_DEBUG1_CLR                HW(USBPHY_DEBUG1_CLR)
+#define HWA_USBPHY_DEBUG1_CLR               (HWA_USBPHY_DEBUG1 + 0x8)
+#define HWT_USBPHY_DEBUG1_CLR               HWIO_32_WO
+#define HWN_USBPHY_DEBUG1_CLR               USBPHY_DEBUG1
+#define HWI_USBPHY_DEBUG1_CLR               
+#define HW_USBPHY_DEBUG1_TOG                HW(USBPHY_DEBUG1_TOG)
+#define HWA_USBPHY_DEBUG1_TOG               (HWA_USBPHY_DEBUG1 + 0xc)
+#define HWT_USBPHY_DEBUG1_TOG               HWIO_32_WO
+#define HWN_USBPHY_DEBUG1_TOG               USBPHY_DEBUG1
+#define HWI_USBPHY_DEBUG1_TOG               
+#define BP_USBPHY_DEBUG1_ENTAILADJVD        13
+#define BM_USBPHY_DEBUG1_ENTAILADJVD        0x6000
+#define BF_USBPHY_DEBUG1_ENTAILADJVD(v)     (((v) & 0x3) << 13)
+#define BFM_USBPHY_DEBUG1_ENTAILADJVD(v)    BM_USBPHY_DEBUG1_ENTAILADJVD
+#define BF_USBPHY_DEBUG1_ENTAILADJVD_V(e)   BF_USBPHY_DEBUG1_ENTAILADJVD(BV_USBPHY_DEBUG1_ENTAILADJVD__##e)
+#define BFM_USBPHY_DEBUG1_ENTAILADJVD_V(v)  BM_USBPHY_DEBUG1_ENTAILADJVD
+#define BP_USBPHY_DEBUG1_ENTX2TX            12
+#define BM_USBPHY_DEBUG1_ENTX2TX            0x1000
+#define BF_USBPHY_DEBUG1_ENTX2TX(v)         (((v) & 0x1) << 12)
+#define BFM_USBPHY_DEBUG1_ENTX2TX(v)        BM_USBPHY_DEBUG1_ENTX2TX
+#define BF_USBPHY_DEBUG1_ENTX2TX_V(e)       BF_USBPHY_DEBUG1_ENTX2TX(BV_USBPHY_DEBUG1_ENTX2TX__##e)
+#define BFM_USBPHY_DEBUG1_ENTX2TX_V(v)      BM_USBPHY_DEBUG1_ENTX2TX
+#define BP_USBPHY_DEBUG1_PLL_IS_240         8
+#define BM_USBPHY_DEBUG1_PLL_IS_240         0x100
+#define BF_USBPHY_DEBUG1_PLL_IS_240(v)      (((v) & 0x1) << 8)
+#define BFM_USBPHY_DEBUG1_PLL_IS_240(v)     BM_USBPHY_DEBUG1_PLL_IS_240
+#define BF_USBPHY_DEBUG1_PLL_IS_240_V(e)    BF_USBPHY_DEBUG1_PLL_IS_240(BV_USBPHY_DEBUG1_PLL_IS_240__##e)
+#define BFM_USBPHY_DEBUG1_PLL_IS_240_V(v)   BM_USBPHY_DEBUG1_PLL_IS_240
+#define BP_USBPHY_DEBUG1_DBG_ADDRESS        0
+#define BM_USBPHY_DEBUG1_DBG_ADDRESS        0xf
+#define BF_USBPHY_DEBUG1_DBG_ADDRESS(v)     (((v) & 0xf) << 0)
+#define BFM_USBPHY_DEBUG1_DBG_ADDRESS(v)    BM_USBPHY_DEBUG1_DBG_ADDRESS
+#define BF_USBPHY_DEBUG1_DBG_ADDRESS_V(e)   BF_USBPHY_DEBUG1_DBG_ADDRESS(BV_USBPHY_DEBUG1_DBG_ADDRESS__##e)
+#define BFM_USBPHY_DEBUG1_DBG_ADDRESS_V(v)  BM_USBPHY_DEBUG1_DBG_ADDRESS
+
+#define HW_USBPHY_VERSION               HW(USBPHY_VERSION)
+#define HWA_USBPHY_VERSION              (0x8007c000 + 0x80)
+#define HWT_USBPHY_VERSION              HWIO_32_RW
+#define HWN_USBPHY_VERSION              USBPHY_VERSION
+#define HWI_USBPHY_VERSION              
+#define BP_USBPHY_VERSION_MAJOR         24
+#define BM_USBPHY_VERSION_MAJOR         0xff000000
+#define BF_USBPHY_VERSION_MAJOR(v)      (((v) & 0xff) << 24)
+#define BFM_USBPHY_VERSION_MAJOR(v)     BM_USBPHY_VERSION_MAJOR
+#define BF_USBPHY_VERSION_MAJOR_V(e)    BF_USBPHY_VERSION_MAJOR(BV_USBPHY_VERSION_MAJOR__##e)
+#define BFM_USBPHY_VERSION_MAJOR_V(v)   BM_USBPHY_VERSION_MAJOR
+#define BP_USBPHY_VERSION_MINOR         16
+#define BM_USBPHY_VERSION_MINOR         0xff0000
+#define BF_USBPHY_VERSION_MINOR(v)      (((v) & 0xff) << 16)
+#define BFM_USBPHY_VERSION_MINOR(v)     BM_USBPHY_VERSION_MINOR
+#define BF_USBPHY_VERSION_MINOR_V(e)    BF_USBPHY_VERSION_MINOR(BV_USBPHY_VERSION_MINOR__##e)
+#define BFM_USBPHY_VERSION_MINOR_V(v)   BM_USBPHY_VERSION_MINOR
+#define BP_USBPHY_VERSION_STEP          0
+#define BM_USBPHY_VERSION_STEP          0xffff
+#define BF_USBPHY_VERSION_STEP(v)       (((v) & 0xffff) << 0)
+#define BFM_USBPHY_VERSION_STEP(v)      BM_USBPHY_VERSION_STEP
+#define BF_USBPHY_VERSION_STEP_V(e)     BF_USBPHY_VERSION_STEP(BV_USBPHY_VERSION_STEP__##e)
+#define BFM_USBPHY_VERSION_STEP_V(v)    BM_USBPHY_VERSION_STEP
+
+#endif /* __HEADERGEN_STMP3700_USBPHY_H__*/
diff --git a/firmware/target/arm/imx233/regs/regs-sydma.h b/firmware/target/arm/imx233/regs/sydma.h
index a53a0b26d2..f1a27cbea9 100644
--- a/firmware/target/arm/imx233/regs/regs-sydma.h
+++ b/firmware/target/arm/imx233/regs/sydma.h
@@ -6,10 +6,9 @@
  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
  *                     \/            \/     \/    \/            \/
  * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: imx233:3.2.0
+ * headergen version: 3.0.0
  *
- * Copyright (C) 2013 by Amaury Pouly
+ * Copyright (C) 2015 by the authors
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
@@ -20,14 +19,15 @@
  * KIND, either express or implied.
  *
  ****************************************************************************/
-#ifndef __SELECT__SYDMA__H__
-#define __SELECT__SYDMA__H__
-#include "regs-macro.h"
+#ifndef __HEADERGEN_SYDMA_H__
+#define __HEADERGEN_SYDMA_H__
 
-#define IMX233_INCLUDE "imx233/regs-sydma.h"
+#include "macro.h"
 
-#include "regs-select.h"
+#define IMX233_INCLUDE  "imx233/sydma.h"
+
+#include "select.h"
 
 #undef IMX233_INCLUDE
 
-#endif /* __SELECT__SYDMA__H__ */
+#endif /* __HEADERGEN_SYDMA_H__*/
diff --git a/firmware/target/arm/imx233/regs/timrot.h b/firmware/target/arm/imx233/regs/timrot.h
new file mode 100644
index 0000000000..8a64360fe9
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/timrot.h
@@ -0,0 +1,37 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_TIMROT_H__
+#define __HEADERGEN_TIMROT_H__
+
+#include "macro.h"
+
+#define STMP3600_INCLUDE    "stmp3600/timrot.h"
+#define STMP3700_INCLUDE    "stmp3700/timrot.h"
+#define IMX233_INCLUDE      "imx233/timrot.h"
+
+#include "select.h"
+
+#undef STMP3600_INCLUDE
+#undef STMP3700_INCLUDE
+#undef IMX233_INCLUDE
+
+#endif /* __HEADERGEN_TIMROT_H__*/
diff --git a/firmware/target/arm/imx233/regs/regs-tvenc.h b/firmware/target/arm/imx233/regs/tvenc.h
index 59dae20b64..995d14ee9a 100644
--- a/firmware/target/arm/imx233/regs/regs-tvenc.h
+++ b/firmware/target/arm/imx233/regs/tvenc.h
@@ -6,10 +6,9 @@
  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
  *                     \/            \/     \/    \/            \/
  * This file was automatically generated by headergen, DO NOT EDIT it.
- * headergen version: 2.1.8
- * XML versions: imx233:3.2.0
+ * headergen version: 3.0.0
  *
- * Copyright (C) 2013 by Amaury Pouly
+ * Copyright (C) 2015 by the authors
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
@@ -20,14 +19,15 @@
  * KIND, either express or implied.
  *
  ****************************************************************************/
-#ifndef __SELECT__TVENC__H__
-#define __SELECT__TVENC__H__
-#include "regs-macro.h"
+#ifndef __HEADERGEN_TVENC_H__
+#define __HEADERGEN_TVENC_H__
 
-#define IMX233_INCLUDE "imx233/regs-tvenc.h"
+#include "macro.h"
 
-#include "regs-select.h"
+#define IMX233_INCLUDE  "imx233/tvenc.h"
+
+#include "select.h"
 
 #undef IMX233_INCLUDE
 
-#endif /* __SELECT__TVENC__H__ */
+#endif /* __HEADERGEN_TVENC_H__*/
diff --git a/firmware/target/arm/imx233/regs/uartapp.h b/firmware/target/arm/imx233/regs/uartapp.h
new file mode 100644
index 0000000000..dbadbc5927
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/uartapp.h
@@ -0,0 +1,37 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_UARTAPP_H__
+#define __HEADERGEN_UARTAPP_H__
+
+#include "macro.h"
+
+#define STMP3600_INCLUDE    "stmp3600/uartapp.h"
+#define STMP3700_INCLUDE    "stmp3700/uartapp.h"
+#define IMX233_INCLUDE      "imx233/uartapp.h"
+
+#include "select.h"
+
+#undef STMP3600_INCLUDE
+#undef STMP3700_INCLUDE
+#undef IMX233_INCLUDE
+
+#endif /* __HEADERGEN_UARTAPP_H__*/
diff --git a/firmware/target/arm/imx233/regs/uartdbg.h b/firmware/target/arm/imx233/regs/uartdbg.h
new file mode 100644
index 0000000000..2da3001fa7
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/uartdbg.h
@@ -0,0 +1,37 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_UARTDBG_H__
+#define __HEADERGEN_UARTDBG_H__
+
+#include "macro.h"
+
+#define STMP3600_INCLUDE    "stmp3600/uartdbg.h"
+#define STMP3700_INCLUDE    "stmp3700/uartdbg.h"
+#define IMX233_INCLUDE      "imx233/uartdbg.h"
+
+#include "select.h"
+
+#undef STMP3600_INCLUDE
+#undef STMP3700_INCLUDE
+#undef IMX233_INCLUDE
+
+#endif /* __HEADERGEN_UARTDBG_H__*/
diff --git a/firmware/target/arm/imx233/regs/usbctrl.h b/firmware/target/arm/imx233/regs/usbctrl.h
new file mode 100644
index 0000000000..564aad0384
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/usbctrl.h
@@ -0,0 +1,35 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_USBCTRL_H__
+#define __HEADERGEN_USBCTRL_H__
+
+#include "macro.h"
+
+#define STMP3700_INCLUDE    "stmp3700/usbctrl.h"
+#define IMX233_INCLUDE      "imx233/usbctrl.h"
+
+#include "select.h"
+
+#undef STMP3700_INCLUDE
+#undef IMX233_INCLUDE
+
+#endif /* __HEADERGEN_USBCTRL_H__*/
diff --git a/firmware/target/arm/imx233/regs/usbphy.h b/firmware/target/arm/imx233/regs/usbphy.h
new file mode 100644
index 0000000000..89fe167ec0
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/usbphy.h
@@ -0,0 +1,37 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_USBPHY_H__
+#define __HEADERGEN_USBPHY_H__
+
+#include "macro.h"
+
+#define STMP3600_INCLUDE    "stmp3600/usbphy.h"
+#define STMP3700_INCLUDE    "stmp3700/usbphy.h"
+#define IMX233_INCLUDE      "imx233/usbphy.h"
+
+#include "select.h"
+
+#undef STMP3600_INCLUDE
+#undef STMP3700_INCLUDE
+#undef IMX233_INCLUDE
+
+#endif /* __HEADERGEN_USBPHY_H__*/
diff --git a/firmware/target/arm/imx233/rtc-imx233.h b/firmware/target/arm/imx233/rtc-imx233.h
index 35304df080..77e4081507 100644
--- a/firmware/target/arm/imx233/rtc-imx233.h
+++ b/firmware/target/arm/imx233/rtc-imx233.h
@@ -25,7 +25,7 @@
 #include "system.h"
 #include "cpu.h"
 
-#include "regs/regs-rtc.h"
+#include "regs/rtc.h"
 
 #define HW_RTC_PERSISTENTn(n)   *(&HW_RTC_PERSISTENT0 + 4 * (n))
 
diff --git a/firmware/target/arm/imx233/samsung-ypz5/button-ypz5.c b/firmware/target/arm/imx233/samsung-ypz5/button-ypz5.c
index cee82e2e9f..c2e53117e5 100644
--- a/firmware/target/arm/imx233/samsung-ypz5/button-ypz5.c
+++ b/firmware/target/arm/imx233/samsung-ypz5/button-ypz5.c
@@ -21,6 +21,7 @@
 #include "system.h"
 #include "lcd.h"
 #include "string.h"
+#include "kernel.h"
 #include "pinctrl-imx233.h"
 #include "power-imx233.h"
 #include "button-lradc-imx233.h"
diff --git a/firmware/target/arm/imx233/samsung-ypz5/lcd-ypz5.c b/firmware/target/arm/imx233/samsung-ypz5/lcd-ypz5.c
index 4f7d9b88b5..99fe0b2aef 100644
--- a/firmware/target/arm/imx233/samsung-ypz5/lcd-ypz5.c
+++ b/firmware/target/arm/imx233/samsung-ypz5/lcd-ypz5.c
@@ -34,8 +34,9 @@
 #include "action.h"
 #endif
 #include "dma-imx233.h"
+#include "kernel.h"
 
-#include "regs/regs-lcdif.h"
+#include "regs/lcdif.h"
 
 /**
  * NOTE
@@ -208,7 +209,7 @@ static void setup_parameters(void)
     imx233_lcdif_set_word_length(16);
     imx233_lcdif_set_data_swizzle(false);
     imx233_lcdif_set_timings(2, 1, 1, 1);
-    BF_WR_V(LCDIF_CTRL, MODE86, 8080_MODE);
+    BF_WR(LCDIF_CTRL, MODE86_V(8080_MODE));
 
     imx233_lcdif_reset_lcd(true);
     udelay(50);
@@ -243,9 +244,9 @@ void lcd_update(void)
     /* We can safely do the transfer in a single shot, since 160 * 128 * 2 < 65k,
      * the maximum transfer size!
      */
-    lcdif_dma.dma.cmd |= BF_OR3(APB_CHx_CMD, CMDWORDS(1), XFER_COUNT(size), COMMAND(2));
+    lcdif_dma.dma.cmd |= BF_OR(APB_CHx_CMD, CMDWORDS(1), XFER_COUNT(size), COMMAND(2));
     lcdif_dma.ctrl0 = HW_LCDIF_CTRL & ~BM_LCDIF_CTRL_COUNT;
-    lcdif_dma.ctrl0 |= BF_OR2(LCDIF_CTRL, COUNT(size/2), DATA_SELECT(1));
+    lcdif_dma.ctrl0 |= BF_OR(LCDIF_CTRL, COUNT(size/2), DATA_SELECT(1));
     lcdif_dma.dma.buffer = FBADDR(0,0);
     lcdif_dma.dma.cmd |= BM_APB_CHx_CMD_SEMAPHORE;
 
diff --git a/firmware/target/arm/imx233/sdmmc-imx233.c b/firmware/target/arm/imx233/sdmmc-imx233.c
index 2c26eb42da..4296720810 100644
--- a/firmware/target/arm/imx233/sdmmc-imx233.c
+++ b/firmware/target/arm/imx233/sdmmc-imx233.c
@@ -35,6 +35,8 @@
 #include "ata_idle_notify.h"
 #include "led.h"
 
+#include "regs/ssp.h"
+
 /** NOTE For convenience, this drivers relies on the many similar commands
  * between SD and MMC. The following assumptions are made:
  * - SD_SEND_STATUS = MMC_SEND_STATUS
diff --git a/firmware/target/arm/imx233/ssp-imx233.c b/firmware/target/arm/imx233/ssp-imx233.c
index 686436af74..c11d09ce5b 100644
--- a/firmware/target/arm/imx233/ssp-imx233.c
+++ b/firmware/target/arm/imx233/ssp-imx233.c
@@ -25,6 +25,43 @@
 #include "pinctrl-imx233.h"
 #include "dma-imx233.h"
 
+#include "regs/ssp.h"
+
+#if IMX233_SUBTARGET < 3700
+#define IMX233_NR_SSP  1
+#else
+#define IMX233_NR_SSP  2
+#endif
+
+/* ssp can value 1 or 2 */
+#if IMX233_NR_SSP >= 2
+#define __SSP_SELECT(ssp, ssp1, ssp2) ((ssp) == 1 ? (ssp1) : (ssp2))
+#else
+#define __SSP_SELECT(ssp, ssp1, ssp2) (ssp1)
+#endif
+
+#define INT_SRC_SSP_DMA(ssp)    __SSP_SELECT(ssp, INT_SRC_SSP1_DMA, INT_SRC_SSP2_DMA)
+#define INT_SRC_SSP_ERROR(ssp)  __SSP_SELECT(ssp, INT_SRC_SSP1_ERROR, INT_SRC_SSP2_ERROR)
+
+#if IMX233_SUBTARGET < 3700
+#define ALL_IRQ \
+    SDIO_IRQ, RESP_ERR_IRQ, RESP_TIMEOUT_IRQ, DATA_TIMEOUT_IRQ, \
+        DATA_CRC_IRQ, RECV_TIMEOUT_IRQ, RECV_OVRFLW_IRQ
+#define ALL_IRQ_EN \
+    SDIO_IRQ_EN, RESP_ERR_IRQ_EN, RESP_TIMEOUT_IRQ_EN, DATA_TIMEOUT_IRQ_EN, \
+        DATA_CRC_IRQ_EN, RECV_TIMEOUT_IRQ_EN, RECV_OVRFLW_IRQ_EN
+#else
+#define ALL_IRQ \
+    SDIO_IRQ, RESP_ERR_IRQ, RESP_TIMEOUT_IRQ, DATA_TIMEOUT_IRQ, \
+        DATA_CRC_IRQ, FIFO_UNDERRUN_IRQ, RECV_TIMEOUT_IRQ, FIFO_OVERRUN_IRQ
+#define ALL_IRQ_EN \
+    SDIO_IRQ_EN, RESP_ERR_IRQ_EN, RESP_TIMEOUT_IRQ_EN, DATA_TIMEOUT_IRQ_EN, \
+        DATA_CRC_IRQ_EN, FIFO_UNDERRUN_EN, RECV_TIMEOUT_IRQ_EN, FIFO_OVERRUN_IRQ_EN
+#endif
+
+#define TIMEOUT_IRQ \
+    RESP_TIMEOUT_IRQ, DATA_TIMEOUT_IRQ, RECV_TIMEOUT_IRQ
+
 /* for debug purpose */
 #if 0
 #define ASSERT_SSP(ssp) if(ssp < 1 || ssp > 2) panicf("ssp=%d in %s", ssp, __func__);
@@ -37,15 +74,13 @@
 #define SSP_SETn(reg, n, field) BF_SET(reg, field)
 #define SSP_CLRn(reg, n, field) BF_CLR(reg, field)
 #define SSP_RDn(reg, n, field) BF_RD(reg, field)
-#define SSP_WRn(reg, n, field, val) BF_WR(reg, field, val)
-#define SSP_WRn_V(reg, n, field, val) BF_WR_V(reg, field, val)
+#define SSP_WRn(reg, n, field, val) BF_WR(reg, field(val))
 #define SSP_REGn(reg, n) HW_##reg
 #else
-#define SSP_SETn(reg, n, field) BF_SETn(reg, n, field)
-#define SSP_CLRn(reg, n, field) BF_CLRn(reg, n, field)
-#define SSP_RDn(reg, n, field) BF_RDn(reg, n, field)
-#define SSP_WRn(reg, n, field, val) BF_WRn(reg, n, field, val)
-#define SSP_WRn_V(reg, n, field, val) BF_WRn_V(reg, n, field, val)
+#define SSP_SETn(reg, n, field) BF_SET(reg(n), field)
+#define SSP_CLRn(reg, n, field) BF_CLR(reg(n), field)
+#define SSP_RDn(reg, n, field) BF_RD(reg(n), field)
+#define SSP_WRn(reg, n, field, val) BF_WR(reg(n), field(val))
 #define SSP_REGn(reg, n) HW_##reg(n)
 #endif
 
@@ -176,7 +211,7 @@ void imx233_ssp_set_timings(int ssp, int divide, int rate, int timeout)
     ASSERT_SSP(ssp)
     if(divide == 0 || (divide % 2) == 1)
         panicf("SSP timing divide must be event");
-    SSP_REGn(SSP_TIMING, ssp) = BF_OR3(SSP_TIMING, CLOCK_DIVIDE(divide),
+    SSP_REGn(SSP_TIMING, ssp) = BF_OR(SSP_TIMING, CLOCK_DIVIDE(divide),
         CLOCK_RATE(rate), TIMEOUT(timeout));
 }
 
@@ -262,7 +297,7 @@ void imx233_ssp_set_mode(int ssp, unsigned mode)
     switch(mode)
     {
         case BV_SSP_CTRL1_SSP_MODE__SD_MMC:
-            SSP_WRn_V(SSP_CTRL1, ssp, WORD_LENGTH, EIGHT_BITS);
+            SSP_WRn(SSP_CTRL1, ssp, WORD_LENGTH_V, EIGHT_BITS);
             SSP_SETn(SSP_CTRL1, ssp, POLARITY);
             SSP_SETn(SSP_CTRL1, ssp, DMA_ENABLE);
             break;
@@ -311,14 +346,14 @@ enum imx233_ssp_error_t imx233_ssp_sd_mmc_transfer(int ssp, uint8_t cmd,
     unsigned xfer_size = block_count * (1 << ssp_log_block_size[ssp - 1]);
 
 #if IMX233_SUBTARGET < 3700
-    ssp_dma_cmd[ssp - 1].cmd0 = BF_OR1(SSP_CMD0, CMD(cmd));
+    ssp_dma_cmd[ssp - 1].cmd0 = BF_OR(SSP_CMD0, CMD(cmd));
 #else
-    ssp_dma_cmd[ssp - 1].cmd0 = BF_OR4(SSP_CMD0, CMD(cmd), APPEND_8CYC(1),
+    ssp_dma_cmd[ssp - 1].cmd0 = BF_OR(SSP_CMD0, CMD(cmd), APPEND_8CYC(1),
         BLOCK_SIZE(ssp_log_block_size[ssp - 1]), BLOCK_COUNT(block_count - 1));
 #endif
     ssp_dma_cmd[ssp - 1].cmd1 = cmd_arg;
     /* setup all flags and run */
-    ssp_dma_cmd[ssp - 1].ctrl0 = BF_OR9(SSP_CTRL0, XFER_COUNT(xfer_size),
+    ssp_dma_cmd[ssp - 1].ctrl0 = BF_OR(SSP_CTRL0, XFER_COUNT(xfer_size),
         ENABLE(1), IGNORE_CRC(buffer == NULL), WAIT_FOR_IRQ(wait4irq),
         GET_RESP(resp != SSP_NO_RESP), LONG_RESP(resp == SSP_LONG_RESP),
         BUS_WIDTH(ssp_bus_width[ssp - 1]), DATA_XFER(buffer != NULL),
@@ -326,7 +361,7 @@ enum imx233_ssp_error_t imx233_ssp_sd_mmc_transfer(int ssp, uint8_t cmd,
     /* setup the dma parameters */
     ssp_dma_cmd[ssp - 1].dma.buffer = buffer;
     ssp_dma_cmd[ssp - 1].dma.next = NULL;
-    ssp_dma_cmd[ssp - 1].dma.cmd = BF_OR6(APB_CHx_CMD,
+    ssp_dma_cmd[ssp - 1].dma.cmd = BF_OR(APB_CHx_CMD,
         COMMAND(buffer == NULL ? BV_APB_CHx_CMD_COMMAND__NO_XFER :
         read ? BV_APB_CHx_CMD_COMMAND__WRITE : BV_APB_CHx_CMD_COMMAND__READ),
         IRQONCMPLT(1), SEMAPHORE(1), WAIT4ENDCMD(1), CMDWORDS(3), XFER_COUNT(xfer_size));
@@ -343,9 +378,9 @@ enum imx233_ssp_error_t imx233_ssp_sd_mmc_transfer(int ssp, uint8_t cmd,
         imx233_dma_reset_channel(APB_SSP(ssp));
         ret = SSP_TIMEOUT;
     }
-    else if((SSP_REGn(SSP_CTRL1, ssp) & BM_SSP_CTRL1_ALL_IRQ) == 0)
+    else if((SSP_REGn(SSP_CTRL1, ssp) & BM_OR(SSP_CTRL1, ALL_IRQ)) == 0)
         ret =  SSP_SUCCESS;
-    else if((SSP_REGn(SSP_CTRL1, ssp) & BM_SSP_CTRL1_TIMEOUT_IRQ))
+    else if((SSP_REGn(SSP_CTRL1, ssp) & BM_OR(SSP_CTRL1, TIMEOUT_IRQ)))
         ret = SSP_TIMEOUT;
     else
         ret = SSP_ERROR;
diff --git a/firmware/target/arm/imx233/ssp-imx233.h b/firmware/target/arm/imx233/ssp-imx233.h
index 42c8d1fe7b..5686dcd477 100644
--- a/firmware/target/arm/imx233/ssp-imx233.h
+++ b/firmware/target/arm/imx233/ssp-imx233.h
@@ -27,44 +27,6 @@
 #include "pinctrl-imx233.h"
 #include "dma-imx233.h"
 
-#include "regs/regs-ssp.h"
-
-#if IMX233_SUBTARGET < 3700
-#define IMX233_NR_SSP  1
-#else
-#define IMX233_NR_SSP  2
-#endif
-
-/* ssp can value 1 or 2 */
-#if IMX233_NR_SSP >= 2
-#define __SSP_SELECT(ssp, ssp1, ssp2) ((ssp) == 1 ? (ssp1) : (ssp2))
-#else
-#define __SSP_SELECT(ssp, ssp1, ssp2) (ssp1)
-#endif
-
-#define INT_SRC_SSP_DMA(ssp)    __SSP_SELECT(ssp, INT_SRC_SSP1_DMA, INT_SRC_SSP2_DMA)
-#define INT_SRC_SSP_ERROR(ssp)  __SSP_SELECT(ssp, INT_SRC_SSP1_ERROR, INT_SRC_SSP2_ERROR)
-
-#define BP_SSP_CTRL1_ALL_IRQ    0
-#if IMX233_SUBTARGET < 3700
-#define BM_SSP_CTRL1_ALL_IRQ \
-    BM_OR7(SSP_CTRL1, SDIO_IRQ, RESP_ERR_IRQ, RESP_TIMEOUT_IRQ, DATA_TIMEOUT_IRQ, \
-        DATA_CRC_IRQ, RECV_TIMEOUT_IRQ, RECV_OVRFLW_IRQ)
-#define BM_SSP_CTRL1_ALL_IRQ_EN \
-    BM_OR7(SSP_CTRL1, SDIO_IRQ_EN, RESP_ERR_IRQ_EN, RESP_TIMEOUT_IRQ_EN, DATA_TIMEOUT_IRQ_EN, \
-        DATA_CRC_IRQ_EN, RECV_TIMEOUT_IRQ_EN, RECV_OVRFLW_IRQ_EN)
-#else
-#define BM_SSP_CTRL1_ALL_IRQ \
-    BM_OR8(SSP_CTRL1, SDIO_IRQ, RESP_ERR_IRQ, RESP_TIMEOUT_IRQ, DATA_TIMEOUT_IRQ, \
-        DATA_CRC_IRQ, FIFO_UNDERRUN_IRQ, RECV_TIMEOUT_IRQ, FIFO_OVERRUN_IRQ)
-#define BM_SSP_CTRL1_ALL_IRQ_EN \
-    BM_OR8(SSP_CTRL1, SDIO_IRQ_EN, RESP_ERR_IRQ_EN, RESP_TIMEOUT_IRQ_EN, DATA_TIMEOUT_IRQ_EN, \
-        DATA_CRC_IRQ_EN, FIFO_UNDERRUN_EN, RECV_TIMEOUT_IRQ_EN, FIFO_OVERRUN_IRQ_EN)
-#endif
-
-#define BM_SSP_CTRL1_TIMEOUT_IRQ \
-    BM_OR3(SSP_CTRL1, RESP_TIMEOUT_IRQ, DATA_TIMEOUT_IRQ, RECV_TIMEOUT_IRQ)
-
 #define IMX233_MAX_SSP_XFER_SIZE            IMX233_MAX_SINGLE_DMA_XFER_SIZE
 
 enum imx233_ssp_error_t
diff --git a/firmware/target/arm/imx233/system-imx233.c b/firmware/target/arm/imx233/system-imx233.c
index 38865c47a3..666b9fedf4 100644
--- a/firmware/target/arm/imx233/system-imx233.c
+++ b/firmware/target/arm/imx233/system-imx233.c
@@ -45,6 +45,10 @@
 #include "fmradio_i2c.h"
 #include "powermgmt-imx233.h"
 
+#include "regs/digctl.h"
+#include "regs/usbphy.h"
+#include "regs/timrot.h"
+
 #define WATCHDOG_HW_DELAY   (10 * HZ)
 #define WATCHDOG_SW_DELAY   (5 * HZ)
 
@@ -99,7 +103,7 @@ void imx233_chip_reset(void)
 #if IMX233_SUBTARGET >= 3700
     HW_CLKCTRL_RESET = BM_CLKCTRL_RESET_CHIP;
 #else
-    HW_POWER_RESET = BF_OR2(POWER_RESET, UNLOCK_V(KEY), RST_DIG(1));
+    BF_WR_ALL(POWER_RESET, UNLOCK_V(KEY), RST_DIG(1));
 #endif
 }
 
@@ -243,10 +247,10 @@ void udelay(unsigned us)
 void imx233_digctl_set_arm_cache_timings(unsigned timings)
 {
 #if IMX233_SUBTARGET >= 3780
-    HW_DIGCTL_ARMCACHE = BF_OR5(DIGCTL_ARMCACHE, ITAG_SS(timings),
+    BF_WR_ALL(DIGCTL_ARMCACHE, ITAG_SS(timings),
         DTAG_SS(timings), CACHE_SS(timings), DRTY_SS(timings), VALID_SS(timings));
 #else
-    HW_DIGCTL_ARMCACHE = BF_OR3(DIGCTL_ARMCACHE, ITAG_SS(timings),
+    BF_WR_ALL(DIGCTL_ARMCACHE, ITAG_SS(timings),
         DTAG_SS(timings), CACHE_SS(timings));
 #endif
 }
diff --git a/firmware/target/arm/imx233/system-target.h b/firmware/target/arm/imx233/system-target.h
index 314ea9b773..18c0b249d9 100644
--- a/firmware/target/arm/imx233/system-target.h
+++ b/firmware/target/arm/imx233/system-target.h
@@ -28,9 +28,6 @@
 #include "icoll-imx233.h"
 #include "clock-target.h" /* CPUFREQ_* are defined here */
 
-#include "regs/regs-digctl.h"
-#include "regs/regs-usbphy.h"
-
 /**
  * Absolute maximum CPU speed: 454.74 MHz (STMP3780), 320.00 MHz (STMP3700)
  * Intermediate CPU speeds: 261.82 MHz, 64 MHz
diff --git a/firmware/target/arm/imx233/timer-imx233.c b/firmware/target/arm/imx233/timer-imx233.c
index f06c19fb76..bcadc82f2c 100644
--- a/firmware/target/arm/imx233/timer-imx233.c
+++ b/firmware/target/arm/imx233/timer-imx233.c
@@ -22,6 +22,8 @@
 #include "timrot-imx233.h"
 #include "timer.h"
 
+#include "regs/timrot.h"
+
 static long timer_cycles = 0;
 
 static void timer_fn(void)
@@ -33,7 +35,7 @@ static void timer_fn(void)
 bool timer_set(long cycles, bool start)
 {
     timer_stop();
-    
+
     if(start && pfn_unregister)
     {
         pfn_unregister();
diff --git a/firmware/target/arm/imx233/timrot-imx233.c b/firmware/target/arm/imx233/timrot-imx233.c
index 22f9853051..7c5e60c30e 100644
--- a/firmware/target/arm/imx233/timrot-imx233.c
+++ b/firmware/target/arm/imx233/timrot-imx233.c
@@ -22,6 +22,8 @@
 #include "clkctrl-imx233.h"
 #include "string.h"
 
+#include "regs/timrot.h"
+
 static imx233_timer_fn_t timer_fns[4];
 
 #define define_timer_irq(nr) \
@@ -29,7 +31,7 @@ void INT_TIMER##nr(void) \
 { \
     if(timer_fns[nr]) \
         timer_fns[nr](); \
-    BF_CLRn(TIMROT_TIMCTRLn, nr, IRQ); \
+    BF_CLR(TIMROT_TIMCTRLn(nr), IRQ); \
 }
 
 define_timer_irq(0)
@@ -46,15 +48,13 @@ void imx233_timrot_setup(unsigned timer_nr, bool reload, unsigned count,
     timer_fns[timer_nr] = fn;
 
     /* make sure we start from stop state */
-    HW_TIMROT_TIMCTRLn(timer_nr) = BF_OR2(TIMROT_TIMCTRLn,
-        SELECT(BV_TIMROT_TIMCTRLn_SELECT__NEVER_TICK), UPDATE(1));
+    BF_WR_ALL(TIMROT_TIMCTRLn(timer_nr), SELECT_V(NEVER_TICK), UPDATE(1));
     /* write count and take effect immediately with UPDATE
      * manual says count-1 for reload timers */
     HW_TIMROT_TIMCOUNTn(timer_nr) = reload ? count - 1 : count;
     /* start timer */
-    HW_TIMROT_TIMCTRLn(timer_nr) = BF_OR6(TIMROT_TIMCTRLn, SELECT(src),
-        PRESCALE(prescale), POLARITY(polarity), RELOAD(reload), IRQ(irq),
-        IRQ_EN(irq));
+    BF_WR_ALL(TIMROT_TIMCTRLn(timer_nr), SELECT(src), PRESCALE(prescale),
+        POLARITY(polarity), RELOAD(reload), IRQ(irq), IRQ_EN(irq));
     imx233_icoll_enable_interrupt(INT_SRC_TIMER(timer_nr), irq);
 
     restore_interrupt(oldstatus);
@@ -69,12 +69,12 @@ struct imx233_timrot_info_t imx233_timrot_get_info(unsigned timer_nr)
 {
     struct imx233_timrot_info_t info;
     memset(&info, 0, sizeof(info));
-    info.src = BF_RDn(TIMROT_TIMCTRLn, timer_nr, SELECT);
-    info.prescale = BF_RDn(TIMROT_TIMCTRLn, timer_nr, PRESCALE);
-    info.reload = BF_RDn(TIMROT_TIMCTRLn, timer_nr, RELOAD);
-    info.polarity = BF_RDn(TIMROT_TIMCTRLn, timer_nr, POLARITY);
-    info.fixed_count = BF_RDn(TIMROT_TIMCOUNTn, timer_nr, FIXED_COUNT);
-    info.run_count = BF_RDn(TIMROT_TIMCOUNTn, timer_nr, RUNNING_COUNT);
+    info.src = BF_RD(TIMROT_TIMCTRLn(timer_nr), SELECT);
+    info.prescale = BF_RD(TIMROT_TIMCTRLn(timer_nr), PRESCALE);
+    info.reload = BF_RD(TIMROT_TIMCTRLn(timer_nr), RELOAD);
+    info.polarity = BF_RD(TIMROT_TIMCTRLn(timer_nr), POLARITY);
+    info.fixed_count = BF_RD(TIMROT_TIMCOUNTn(timer_nr), FIXED_COUNT);
+    info.run_count = BF_RD(TIMROT_TIMCOUNTn(timer_nr), RUNNING_COUNT);
     return info;
 }
 
diff --git a/firmware/target/arm/imx233/timrot-imx233.h b/firmware/target/arm/imx233/timrot-imx233.h
index e33de39390..778cd1add9 100644
--- a/firmware/target/arm/imx233/timrot-imx233.h
+++ b/firmware/target/arm/imx233/timrot-imx233.h
@@ -25,8 +25,6 @@
 #include "cpu.h"
 #include "icoll-imx233.h"
 
-#include "regs/regs-timrot.h"
-
 /* list of timers */
 enum
 {
diff --git a/firmware/target/arm/imx233/uartdbg-imx233.c b/firmware/target/arm/imx233/uartdbg-imx233.c
index 077b405f49..e1cf533d3e 100644
--- a/firmware/target/arm/imx233/uartdbg-imx233.c
+++ b/firmware/target/arm/imx233/uartdbg-imx233.c
@@ -22,6 +22,8 @@
 #include "pinctrl-imx233.h"
 #include "clkctrl-imx233.h"
 
+#include "regs/uartdbg.h"
+
 void imx233_uartdbg_init(unsigned long baud)
 {
     /* Enable UART clock */
@@ -35,20 +37,20 @@ void imx233_uartdbg_init(unsigned long baud)
     HW_UARTDBG_FBRD = baud & 0xFFFF;
 
     /* Set port options (actually needed to set baud rate), 8 bit char, enable FIFO buffer */
-    BF_WR(UARTDBG_LCR_H, WLEN, 3);
-    BF_WR(UARTDBG_LCR_H, FEN, 1);
+    BF_WR(UARTDBG_LCR_H, WLEN(3));
+    BF_WR(UARTDBG_LCR_H, FEN(1));
 
     /* Finally enable UART device, TX enable, RX enable, device enable */
-    BF_WR(UARTDBG_CR, TXE, 1);
-    BF_WR(UARTDBG_CR, RXE, 1);
-    BF_WR(UARTDBG_CR, UARTEN, 1);
+    BF_WR(UARTDBG_CR, TXE(1));
+    BF_WR(UARTDBG_CR, RXE(1));
+    BF_WR(UARTDBG_CR, UARTEN(1));
 }
 
 void imx233_uartdbg_send(unsigned char data)
 {
     /* Wait to transmit if TX FIFO buffer is full*/
     while (BF_RD(UARTDBG_FR, TXFF));
-    BF_WR(UARTDBG_DR, DATA, data);
+    BF_WR(UARTDBG_DR, DATA(data));
 }
 
 void uart_tx(const char* data)
diff --git a/firmware/target/arm/imx233/uartdbg-imx233.h b/firmware/target/arm/imx233/uartdbg-imx233.h
index 3ee5175a21..91993b2bf3 100644
--- a/firmware/target/arm/imx233/uartdbg-imx233.h
+++ b/firmware/target/arm/imx233/uartdbg-imx233.h
@@ -19,7 +19,6 @@
  *
  ****************************************************************************/
 #include "system.h"
-#include "regs/regs-uartdbg.h"
 
 /* This values below are valid with a XCLK of 24MHz */
 #define BAUD_9600               (uint32_t)(156 << 16 | 16)