Ingenic Jz4740: add basic frequency switching

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@21625 a1c6a512-1295-4272-9138-f99709370657

3 files changed, 25 insertions, 6 deletions

diff --git a/firmware/export/config-ondavx747.h b/firmware/export/config-ondavx747.h
index 9506b6887f..22108fff49 100644
--- a/firmware/export/config-ondavx747.h
+++ b/firmware/export/config-ondavx747.h
@@ -187,9 +187,7 @@
 #define FIRMWARE_OFFSET_FILE_DATA 8
 
 /* Define this if you have adjustable CPU frequency */
-/* #define HAVE_ADJUSTABLE_CPU_FREQ */
-#define CPUFREQ_NORMAL 336000000    /* CPU clock: 336 MHz */
-#define CPUFREQ_MAX 336000000       /* CPU clock: 336 MHz */
+#define HAVE_ADJUSTABLE_CPU_FREQ
 
 #ifdef ONDA_VX747P
 #define BOOTFILE_EXT "vx747p"
diff --git a/firmware/export/jz4740.h b/firmware/export/jz4740.h
index a29266ab90..820b43f880 100644
--- a/firmware/export/jz4740.h
+++ b/firmware/export/jz4740.h
@@ -5212,4 +5212,8 @@ struct Ration2m
 /* Timer frequency */
 #define TIMER_FREQ (CFG_EXTAL) /* For full precision! */
 
+#define CPUFREQ_NORMAL  112000000   /* CPU clock: 112 MHz */
+#define CPUFREQ_DEFAULT 112000000   /* CPU clock: 112 MHz */
+#define CPUFREQ_MAX     336000000   /* CPU clock: 336 MHz */
+
 #endif /* __JZ4740_H__ */
diff --git a/firmware/target/mips/ingenic_jz47xx/system-jz4740.c b/firmware/target/mips/ingenic_jz47xx/system-jz4740.c
index c0a9bf19aa..978675825c 100644
--- a/firmware/target/mips/ingenic_jz47xx/system-jz4740.c
+++ b/firmware/target/mips/ingenic_jz47xx/system-jz4740.c
@@ -541,10 +541,11 @@ void system_reboot(void)
 void system_exception_wait(void)
 {
     /* check for power button without including any .h file */
-    while (1)
+    while(1)
     {
-        if( ~REG_GPIO_PXPIN(3) & (1 << 29) )
-            break;
+        if( (~REG_GPIO_PXPIN(3)) & (1 << 29) )
+            return;
+        asm volatile("nop");
     }
 }
 
@@ -574,3 +575,19 @@ int system_memory_guard(int newmode)
     (void)newmode;
     return 0;
 }
+
+#ifdef HAVE_ADJUSTABLE_CPU_FREQ
+void set_cpu_frequency(long frequency)
+{
+    unsigned long cfcr = REG_CPM_CPCCR;
+    cfcr &= ~CPM_CPCCR_CDIV_MASK;
+
+    if(frequency == CPUFREQ_NORMAL)
+        cfcr |= (0 << CPM_CPCCR_CDIV_BIT);
+    else
+        cfcr |= (2 << CPM_CPCCR_CDIV_BIT);
+
+    REG_CPM_CPCCR = cfcr;
+    cpu_frequency = frequency;
+}
+#endif