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author | Linus Nielsen Feltzing <linus@haxx.se> | 2005-08-11 19:00:55 +0000 |
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committer | Linus Nielsen Feltzing <linus@haxx.se> | 2005-08-11 19:00:55 +0000 |
commit | dc4a6b828ea9a36e839747249dfdb085ced7af07 (patch) | |
tree | b76a98aebe545a819f9d4fe9cdb0164ec51441bc | |
parent | 5a8eac1a5a7daa1f90af82e6d687e6c559a0d3e1 (diff) | |
download | rockbox-dc4a6b828ea9a36e839747249dfdb085ced7af07.tar.gz rockbox-dc4a6b828ea9a36e839747249dfdb085ced7af07.zip |
iriver: Moved the I2C prescaler setting to i2c_init(), and removed it from set_cpu_frequency(). The Coldfire I2C controller can't handle on-the-fly prescaler changes. Also removed the unnecessary slave address setting in i2c_init.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@7304 a1c6a512-1295-4272-9138-f99709370657
-rw-r--r-- | firmware/drivers/i2c-coldfire.c | 6 | ||||
-rw-r--r-- | firmware/system.c | 9 |
2 files changed, 4 insertions, 11 deletions
diff --git a/firmware/drivers/i2c-coldfire.c b/firmware/drivers/i2c-coldfire.c index 5b4f4a1830..788385101a 100644 --- a/firmware/drivers/i2c-coldfire.c +++ b/firmware/drivers/i2c-coldfire.c | |||
@@ -37,15 +37,17 @@ static volatile unsigned char *i2c_get_addr(int device); | |||
37 | 37 | ||
38 | void i2c_init(void) | 38 | void i2c_init(void) |
39 | { | 39 | { |
40 | /* I2C Clock divisor = 576 => 119.952 MHz / 2 / 576 = 104.125 kHz */ | ||
41 | MFDR = 0x14; | ||
42 | MFDR2 = 0x14; | ||
43 | |||
40 | #if (CONFIG_KEYPAD == IRIVER_H100_PAD) || (CONFIG_KEYPAD == IRIVER_H300_PAD) | 44 | #if (CONFIG_KEYPAD == IRIVER_H100_PAD) || (CONFIG_KEYPAD == IRIVER_H300_PAD) |
41 | /* Audio Codec */ | 45 | /* Audio Codec */ |
42 | MADR = 0x6c; /* iRiver firmware uses this addr */ | ||
43 | MBDR = 0; /* iRiver firmware does this */ | 46 | MBDR = 0; /* iRiver firmware does this */ |
44 | MBCR = IEN; /* Enable interface */ | 47 | MBCR = IEN; /* Enable interface */ |
45 | 48 | ||
46 | #if 0 | 49 | #if 0 |
47 | /* FM Tuner */ | 50 | /* FM Tuner */ |
48 | MADR2 = 0x6c; | ||
49 | MBDR2 = 0; | 51 | MBDR2 = 0; |
50 | MBCR2 = IEN; | 52 | MBCR2 = IEN; |
51 | #endif | 53 | #endif |
diff --git a/firmware/system.c b/firmware/system.c index 13d424d02b..dd356bab1f 100644 --- a/firmware/system.c +++ b/firmware/system.c | |||
@@ -529,9 +529,6 @@ void set_cpu_frequency(long frequency) | |||
529 | tick_start(1000/HZ); | 529 | tick_start(1000/HZ); |
530 | IDECONFIG1 = 0x106000 | (5 << 10); /* BUFEN2 enable + CS2Pre/CS2Post */ | 530 | IDECONFIG1 = 0x106000 | (5 << 10); /* BUFEN2 enable + CS2Pre/CS2Post */ |
531 | IDECONFIG2 = 0x40000 | (1 << 8); /* TA enable + CS2wait */ | 531 | IDECONFIG2 = 0x40000 | (1 << 8); /* TA enable + CS2wait */ |
532 | /* I2C Clock divisor = 576 => 119.952 MHz / 2 / 576 = 104.125 kHz */ | ||
533 | MFDR = 0x14; | ||
534 | MFDR2 = 0x14; | ||
535 | break; | 532 | break; |
536 | 533 | ||
537 | case CPUFREQ_NORMAL: | 534 | case CPUFREQ_NORMAL: |
@@ -548,9 +545,6 @@ void set_cpu_frequency(long frequency) | |||
548 | tick_start(1000/HZ); | 545 | tick_start(1000/HZ); |
549 | IDECONFIG1 = 0x106000 | (5 << 10); /* BUFEN2 enable + CS2Pre/CS2Post */ | 546 | IDECONFIG1 = 0x106000 | (5 << 10); /* BUFEN2 enable + CS2Pre/CS2Post */ |
550 | IDECONFIG2 = 0x40000 | (0 << 8); /* TA enable + CS2wait */ | 547 | IDECONFIG2 = 0x40000 | (0 << 8); /* TA enable + CS2wait */ |
551 | /* I2C Clock divisor = 240 => 47.9808 MHz / 2 / 240 = 99.96 kHz */ | ||
552 | MFDR = 0x0f; | ||
553 | MFDR2 = 0x0f; | ||
554 | break; | 548 | break; |
555 | default: | 549 | default: |
556 | DCR = (DCR & ~0x01ff) | 1; /* Refresh timer for bypass | 550 | DCR = (DCR & ~0x01ff) | 1; /* Refresh timer for bypass |
@@ -562,9 +556,6 @@ void set_cpu_frequency(long frequency) | |||
562 | tick_start(1000/HZ); | 556 | tick_start(1000/HZ); |
563 | IDECONFIG1 = 0x106000 | (1 << 10); /* BUFEN2 enable + CS2Pre/CS2Post */ | 557 | IDECONFIG1 = 0x106000 | (1 << 10); /* BUFEN2 enable + CS2Pre/CS2Post */ |
564 | IDECONFIG2 = 0x40000 | (0 << 8); /* TA enable + CS2wait */ | 558 | IDECONFIG2 = 0x40000 | (0 << 8); /* TA enable + CS2wait */ |
565 | /* I2C Clock divisor = 56 => 11.2896 MHz / 56 = 100.8 kHz */ | ||
566 | MFDR = 0x06; | ||
567 | MFDR2 = 0x06; | ||
568 | break; | 559 | break; |
569 | } | 560 | } |
570 | } | 561 | } |