summaryrefslogtreecommitdiff
path: root/firmware/system.c
diff options
context:
space:
mode:
Diffstat (limited to 'firmware/system.c')
-rw-r--r--firmware/system.c9
1 files changed, 0 insertions, 9 deletions
diff --git a/firmware/system.c b/firmware/system.c
index 13d424d02b..dd356bab1f 100644
--- a/firmware/system.c
+++ b/firmware/system.c
@@ -529,9 +529,6 @@ void set_cpu_frequency(long frequency)
529 tick_start(1000/HZ); 529 tick_start(1000/HZ);
530 IDECONFIG1 = 0x106000 | (5 << 10); /* BUFEN2 enable + CS2Pre/CS2Post */ 530 IDECONFIG1 = 0x106000 | (5 << 10); /* BUFEN2 enable + CS2Pre/CS2Post */
531 IDECONFIG2 = 0x40000 | (1 << 8); /* TA enable + CS2wait */ 531 IDECONFIG2 = 0x40000 | (1 << 8); /* TA enable + CS2wait */
532 /* I2C Clock divisor = 576 => 119.952 MHz / 2 / 576 = 104.125 kHz */
533 MFDR = 0x14;
534 MFDR2 = 0x14;
535 break; 532 break;
536 533
537 case CPUFREQ_NORMAL: 534 case CPUFREQ_NORMAL:
@@ -548,9 +545,6 @@ void set_cpu_frequency(long frequency)
548 tick_start(1000/HZ); 545 tick_start(1000/HZ);
549 IDECONFIG1 = 0x106000 | (5 << 10); /* BUFEN2 enable + CS2Pre/CS2Post */ 546 IDECONFIG1 = 0x106000 | (5 << 10); /* BUFEN2 enable + CS2Pre/CS2Post */
550 IDECONFIG2 = 0x40000 | (0 << 8); /* TA enable + CS2wait */ 547 IDECONFIG2 = 0x40000 | (0 << 8); /* TA enable + CS2wait */
551 /* I2C Clock divisor = 240 => 47.9808 MHz / 2 / 240 = 99.96 kHz */
552 MFDR = 0x0f;
553 MFDR2 = 0x0f;
554 break; 548 break;
555 default: 549 default:
556 DCR = (DCR & ~0x01ff) | 1; /* Refresh timer for bypass 550 DCR = (DCR & ~0x01ff) | 1; /* Refresh timer for bypass
@@ -562,9 +556,6 @@ void set_cpu_frequency(long frequency)
562 tick_start(1000/HZ); 556 tick_start(1000/HZ);
563 IDECONFIG1 = 0x106000 | (1 << 10); /* BUFEN2 enable + CS2Pre/CS2Post */ 557 IDECONFIG1 = 0x106000 | (1 << 10); /* BUFEN2 enable + CS2Pre/CS2Post */
564 IDECONFIG2 = 0x40000 | (0 << 8); /* TA enable + CS2wait */ 558 IDECONFIG2 = 0x40000 | (0 << 8); /* TA enable + CS2wait */
565 /* I2C Clock divisor = 56 => 11.2896 MHz / 56 = 100.8 kHz */
566 MFDR = 0x06;
567 MFDR2 = 0x06;
568 break; 559 break;
569 } 560 }
570} 561}