Remove the TIMER_* macros and declare target-specific functions in timer.h

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@21559 a1c6a512-1295-4272-9138-f99709370657

26 files changed, 44 insertions, 208 deletions

diff --git a/firmware/export/timer.h b/firmware/export/timer.h
index 7b56330e18..230c0ae4dc 100644
--- a/firmware/export/timer.h
+++ b/firmware/export/timer.h
@@ -40,6 +40,7 @@
  #warning "TIMER_FREQ not defined"
  #define TIMER_FREQ CPU_FREQ
 #endif
+
 bool timer_register(int reg_prio, void (*unregister_callback)(void),
                     long cycles, void (*timer_callback)(void)
                     IF_COP(,int core));
@@ -49,6 +50,11 @@ void timers_adjust_prescale(int multiplier, bool enable_irq);
 #endif
 void timer_unregister(void);
 
+/* target-specific interface */
+bool timer_set(long cycles, bool start);
+bool timer_start(IF_COP_VOID(int core));
+void timer_stop(void);
+
 /* For target-specific interface use */
 extern void (*pfn_timer)(void);
 extern void (*pfn_unregister)(void);
diff --git a/firmware/target/arm/as3525/timer-as3525.c b/firmware/target/arm/as3525/timer-as3525.c
index 50f0e73158..673e3b8f47 100644
--- a/firmware/target/arm/as3525/timer-as3525.c
+++ b/firmware/target/arm/as3525/timer-as3525.c
@@ -31,7 +31,7 @@ void INT_TIMER1(void)
     TIMER1_INTCLR = 0; /* clear interrupt */
 }
 
-bool __timer_set(long cycles, bool start)
+bool timer_set(long cycles, bool start)
 {
     if (start)
     {
@@ -53,14 +53,14 @@ bool __timer_set(long cycles, bool start)
     return true;
 }
 
-bool __timer_start(void)
+bool timer_start(void)
 {
     CGU_PERI |= CGU_TIMER1_CLOCK_ENABLE;    /* enable peripheral */
     VIC_INT_ENABLE |= INTERRUPT_TIMER1;
     return true;
 }
 
-void __timer_stop(void)
+void timer_stop(void)
 {
     TIMER1_CONTROL &= 0x10; /* disable timer 1 (don't modify bit 4) */
     VIC_INT_EN_CLEAR = INTERRUPT_TIMER1;  /* disable interrupt */
diff --git a/firmware/target/arm/as3525/timer-target.h b/firmware/target/arm/as3525/timer-target.h
index b1bdfed78f..f6b4fae370 100644
--- a/firmware/target/arm/as3525/timer-target.h
+++ b/firmware/target/arm/as3525/timer-target.h
@@ -21,19 +21,6 @@
 #ifndef TIMER_TARGET_H
 #define TIMER_TARGET_H
 
-bool __timer_set(long cycles, bool set);
-bool __timer_start(void);
-void __timer_stop(void);
-
 #define TIMER_FREQ (24000000 / 16)
 
-#define __TIMER_SET(cycles, set) \
-    __timer_set(cycles, set)
-
-#define __TIMER_START() \
-    __timer_start()
-
-#define __TIMER_STOP(...) \
-    __timer_stop()
-
 #endif /* TIMER_TARGET_H */
diff --git a/firmware/target/arm/at91sam/lyre_proto1/timer-lyre_proto1.c b/firmware/target/arm/at91sam/lyre_proto1/timer-lyre_proto1.c
index ef5c91169d..1b620e9c4f 100644
--- a/firmware/target/arm/at91sam/lyre_proto1/timer-lyre_proto1.c
+++ b/firmware/target/arm/at91sam/lyre_proto1/timer-lyre_proto1.c
@@ -48,7 +48,7 @@ void pitc_handler(void)
     }
 }
 
-bool __timer_set(long cycles, bool start)
+bool timer_set(long cycles, bool start)
 {
     if (cycles < 1000) /* Max value on PITC?? */
     {
@@ -67,7 +67,7 @@ bool __timer_set(long cycles, bool start)
     return false;
 }
 
-bool __timer_start(void)
+bool timer_start(void)
 {
     bool retval = true;
     volatile unsigned long pimr = 0;
@@ -101,7 +101,7 @@ bool __timer_start(void)
     return retval;
 }
 
-void __timer_stop(void)
+void timer_stop(void)
 {
     volatile unsigned long pimr = 0;
 
diff --git a/firmware/target/arm/at91sam/lyre_proto1/timer-target.h b/firmware/target/arm/at91sam/lyre_proto1/timer-target.h
index b8298d3d77..d0773130bf 100644
--- a/firmware/target/arm/at91sam/lyre_proto1/timer-target.h
+++ b/firmware/target/arm/at91sam/lyre_proto1/timer-target.h
@@ -25,17 +25,4 @@
 /* timer is based on PCLK and minimum division is 2 */
 #define TIMER_FREQ (49156800/2)
 
-bool __timer_set(long cycles, bool set);
-bool __timer_start(void);
-void __timer_stop(void);
-
-#define __TIMER_SET(cycles, set) \
-    __timer_set(cycles, set)
-
-#define __TIMER_START() \
-    __timer_start()
-
-#define __TIMER_STOP(...) \
-    __timer_stop()
-
 #endif /* TIMER_TARGET_H */
diff --git a/firmware/target/arm/imx31/gigabeat-s/timer-imx31.c b/firmware/target/arm/imx31/gigabeat-s/timer-imx31.c
index 5e53e4a55e..f3f78a1ee1 100644
--- a/firmware/target/arm/imx31/gigabeat-s/timer-imx31.c
+++ b/firmware/target/arm/imx31/gigabeat-s/timer-imx31.c
@@ -52,7 +52,7 @@ static void stop_timer(bool clock_off)
     }
 }
 
-bool _timer_set(long cycles, bool start)
+bool timer_set(long cycles, bool start)
 {
     /* Maximum cycle count expressible in the cycles parameter is 2^31-1
      * and the modulus counter is capable of 2^32-1 and as a result there is
@@ -86,7 +86,7 @@ bool _timer_set(long cycles, bool start)
     return true;
 }
 
-bool _timer_start(void)
+bool timer_start(void)
 {
     int oldstatus = disable_interrupt_save(IRQ_FIQ_STATUS);
 
@@ -104,7 +104,7 @@ bool _timer_start(void)
     return true;
 }
 
-void _timer_stop(void)
+void timer_stop(void)
 {
     int oldstatus = disable_interrupt_save(IRQ_FIQ_STATUS);
     /* Halt timer if running - stop module clock */
diff --git a/firmware/target/arm/imx31/gigabeat-s/timer-target.h b/firmware/target/arm/imx31/gigabeat-s/timer-target.h
index f019a45519..9d5520aa6d 100644
--- a/firmware/target/arm/imx31/gigabeat-s/timer-target.h
+++ b/firmware/target/arm/imx31/gigabeat-s/timer-target.h
@@ -24,17 +24,4 @@
 /* timer is based on ipg_clk */
 #define TIMER_FREQ (66000000)
 
-bool _timer_set(long cycles, bool set);
-bool _timer_start(void);
-void _timer_stop(void);
-
-#define __TIMER_SET(cycles, set) \
-    _timer_set(cycles, set)
-
-#define __TIMER_START() \
-    _timer_start()
-
-#define __TIMER_STOP(...) \
-    _timer_stop()
-
 #endif /* TIMER_TARGET_H */
diff --git a/firmware/target/arm/pnx0101/timer-pnx0101.c b/firmware/target/arm/pnx0101/timer-pnx0101.c
index 6e685aa20f..d54cfe84d5 100644
--- a/firmware/target/arm/pnx0101/timer-pnx0101.c
+++ b/firmware/target/arm/pnx0101/timer-pnx0101.c
@@ -43,7 +43,7 @@ void TIMER1_ISR(void)
     TIMER1.clr = 1; /* clear the interrupt */
 }
 
-bool __timer_set(long cycles, bool start)
+bool timer_set(long cycles, bool start)
 {
     if (start)
     {
@@ -68,14 +68,14 @@ bool __timer_set(long cycles, bool start)
     return true;
 }
 
-bool __timer_start(void)
+bool timer_start(void)
 {
     irq_set_int_handler(IRQ_TIMER1, TIMER1_ISR);
     irq_enable_int(IRQ_TIMER1);
     return true;
 }
 
-void __timer_stop(void)
+void timer_stop(void)
 {
     TIMER1.ctrl &= ~0x80;  /* disable timer 1 */
     irq_disable_int(IRQ_TIMER1);
diff --git a/firmware/target/arm/pnx0101/timer-target.h b/firmware/target/arm/pnx0101/timer-target.h
index 853da07838..3bfdb8986d 100644
--- a/firmware/target/arm/pnx0101/timer-target.h
+++ b/firmware/target/arm/pnx0101/timer-target.h
@@ -21,19 +21,6 @@
 #ifndef TIMER_TARGET_H
 #define TIMER_TARGET_H
 
-bool __timer_set(long cycles, bool start);
-bool __timer_start(void);
-void __timer_stop(void);
-
 #define TIMER_FREQ 3000000
 
-#define __TIMER_SET(cycles, set) \
-    __timer_set(cycles, set)
-
-#define __TIMER_START() \
-    __timer_start()
-
-#define __TIMER_STOP(...) \
-    __timer_stop()
-
 #endif /* TIMER_TARGET_H */
diff --git a/firmware/target/arm/s3c2440/gigabeat-fx/timer-meg-fx.c b/firmware/target/arm/s3c2440/gigabeat-fx/timer-meg-fx.c
index 884b0803a2..4565f79751 100644
--- a/firmware/target/arm/s3c2440/gigabeat-fx/timer-meg-fx.c
+++ b/firmware/target/arm/s3c2440/gigabeat-fx/timer-meg-fx.c
@@ -48,7 +48,7 @@ static void stop_timer(void)
     INTPND = TIMER0_MASK;
 }
 
-bool __timer_set(long cycles, bool start)
+bool timer_set(long cycles, bool start)
 {
     bool retval = false;
 
@@ -87,7 +87,7 @@ bool __timer_set(long cycles, bool start)
     return retval;
 }
 
-bool __timer_start(void)
+bool timer_start(void)
 {
     bool retval = true;
 
@@ -122,7 +122,7 @@ bool __timer_start(void)
     return retval;
 }
 
-void __timer_stop(void)
+void timer_stop(void)
 {
     int oldstatus = disable_interrupt_save(IRQ_FIQ_STATUS);
     stop_timer();
diff --git a/firmware/target/arm/s3c2440/gigabeat-fx/timer-target.h b/firmware/target/arm/s3c2440/gigabeat-fx/timer-target.h
index 700833486d..215477a806 100644
--- a/firmware/target/arm/s3c2440/gigabeat-fx/timer-target.h
+++ b/firmware/target/arm/s3c2440/gigabeat-fx/timer-target.h
@@ -25,17 +25,4 @@
 #define TIMER_FREQ (49156800/2)
 #define TIMER234_PRESCALE 21
 
-bool __timer_set(long cycles, bool set);
-bool __timer_start(void);
-void __timer_stop(void);
-
-#define __TIMER_SET(cycles, set) \
-    __timer_set(cycles, set)
-
-#define __TIMER_START() \
-    __timer_start()
-
-#define __TIMER_STOP(...) \
-    __timer_stop()
-
 #endif /* TIMER_TARGET_H */
diff --git a/firmware/target/arm/tcc77x/timer-target.h b/firmware/target/arm/tcc77x/timer-target.h
index ace31ac886..a4d869067a 100644
--- a/firmware/target/arm/tcc77x/timer-target.h
+++ b/firmware/target/arm/tcc77x/timer-target.h
@@ -24,17 +24,4 @@
 /* timers are based on XIN (12Mhz) */
 #define TIMER_FREQ (12000000)
 
-bool __timer_set(long cycles, bool set);
-bool __timer_start(void);
-void __timer_stop(void);
-
-#define __TIMER_SET(cycles, set) \
-    __timer_set(cycles, set)
-
-#define __TIMER_START() \
-    __timer_start()
-
-#define __TIMER_STOP(...) \
-    __timer_stop()
-
 #endif /* TIMER_TARGET_H */
diff --git a/firmware/target/arm/tcc77x/timer-tcc77x.c b/firmware/target/arm/tcc77x/timer-tcc77x.c
index ddf44454c2..6e8764d9ce 100644
--- a/firmware/target/arm/tcc77x/timer-tcc77x.c
+++ b/firmware/target/arm/tcc77x/timer-tcc77x.c
@@ -28,7 +28,7 @@
 /* Use the TC32 counter [sourced by Xin:12Mhz] for this timer, as it's the
    only one that allows a 32-bit counter (Timer0-5 are 16/20 bit only). */
 
-bool __timer_set(long cycles, bool start)
+bool timer_set(long cycles, bool start)
 {
     #warning function not implemented
     
@@ -37,14 +37,14 @@ bool __timer_set(long cycles, bool start)
     return false;
 }
 
-bool __timer_start(void)
+bool timer_start(void)
 {
     #warning function not implemented
     
     return false;
 }
 
-void __timer_stop(void)
+void timer_stop(void)
 {
     #warning function not implemented
 }
diff --git a/firmware/target/arm/tcc780x/timer-target.h b/firmware/target/arm/tcc780x/timer-target.h
index d6a8c4b0aa..91a623a713 100644
--- a/firmware/target/arm/tcc780x/timer-target.h
+++ b/firmware/target/arm/tcc780x/timer-target.h
@@ -24,17 +24,4 @@
 /* Timer is based on PCK_TCT (set to 2Mhz in system.c) */
 #define TIMER_FREQ (2000000)
 
-bool __timer_set(long cycles, bool set);
-bool __timer_start(void);
-void __timer_stop(void);
-
-#define __TIMER_SET(cycles, set) \
-    __timer_set(cycles, set)
-
-#define __TIMER_START() \
-    __timer_start()
-
-#define __TIMER_STOP(...) \
-    __timer_stop()
-
 #endif /* TIMER_TARGET_H */
diff --git a/firmware/target/arm/tcc780x/timer-tcc780x.c b/firmware/target/arm/tcc780x/timer-tcc780x.c
index ddd3b1d694..74502ae369 100644
--- a/firmware/target/arm/tcc780x/timer-tcc780x.c
+++ b/firmware/target/arm/tcc780x/timer-tcc780x.c
@@ -27,7 +27,7 @@
 
 static const int prescale_shifts[] = {1, 2, 3, 4, 5, 10, 12};
 
-bool __timer_set(long cycles, bool start)
+bool timer_set(long cycles, bool start)
 {
     bool found = false;
  
@@ -62,7 +62,7 @@ bool __timer_set(long cycles, bool start)
     return true;
 }
 
-bool __timer_start(void)
+bool timer_start(void)
 {
     int oldstatus = disable_interrupt_save(IRQ_STATUS);
     
@@ -73,7 +73,7 @@ bool __timer_start(void)
     return true;
 }
 
-void __timer_stop(void)
+void timer_stop(void)
 {
     int oldstatus = disable_interrupt_save(IRQ_STATUS);
     
diff --git a/firmware/target/arm/timer-pp.c b/firmware/target/arm/timer-pp.c
index 01c691f79e..a8879b1824 100644
--- a/firmware/target/arm/timer-pp.c
+++ b/firmware/target/arm/timer-pp.c
@@ -44,7 +44,7 @@ void TIMER2(void)
     }
 }
 
-bool __timer_set(long cycles, bool start)
+bool timer_set(long cycles, bool start)
 {
     if (cycles > 0x20000000 || cycles < 2)
         return false;
@@ -67,7 +67,7 @@ bool __timer_set(long cycles, bool start)
     return true;
 }
 
-bool __timer_start(IF_COP_VOID(int core))
+bool timer_start(IF_COP_VOID(int core))
 {
     /* unmask interrupt source */
 #if NUM_CORES > 1
@@ -79,7 +79,7 @@ bool __timer_start(IF_COP_VOID(int core))
     return true;
 }
 
-void __timer_stop(void)
+void timer_stop(void)
 {
     TIMER2_CFG = 0;         /* stop timer 2 */
     CPU_INT_DIS = TIMER2_MASK;
diff --git a/firmware/target/arm/timer-target.h b/firmware/target/arm/timer-target.h
index 7b7fdabdce..65867ab64b 100644
--- a/firmware/target/arm/timer-target.h
+++ b/firmware/target/arm/timer-target.h
@@ -28,25 +28,7 @@
 #error "PP specific header"
 #endif
 
-bool __timer_set(long cycles, bool start);
-bool __timer_start(IF_COP_VOID(int core));
-void __timer_stop(void);
-
 /* Portalplayer chips use a microsecond timer. */
 #define TIMER_FREQ 1000000
 
-#define __TIMER_SET(cycles, set) \
-    __timer_set(cycles, set)
-
-#if NUM_CORES > 1
-#define __TIMER_START(core) \
-    __timer_start(core)
-#else
-#define __TIMER_START() \
-    __timer_start()
-#endif
-
-#define __TIMER_STOP(...) \
-    __timer_stop()
-
 #endif /* TIMER_TARGET_H */
diff --git a/firmware/target/arm/tms320dm320/timer-dm320.c b/firmware/target/arm/tms320dm320/timer-dm320.c
index 9357ffa9de..ef1fac04eb 100644
--- a/firmware/target/arm/tms320dm320/timer-dm320.c
+++ b/firmware/target/arm/tms320dm320/timer-dm320.c
@@ -34,7 +34,7 @@ void TIMER0(void)
         pfn_timer();
 }
 
-bool __timer_set(long cycles, bool start)
+bool timer_set(long cycles, bool start)
 {
     int oldlevel;
     unsigned int divider=cycles, prescaler=0;
@@ -82,7 +82,7 @@ static void stop_timer(void)
     IO_CLK_MOD2 &= ~CLK_MOD2_TMR0; //disable TIMER0 clock
 }
 
-bool __timer_start(void)
+bool timer_start(void)
 {
     int oldstatus = disable_interrupt_save(IRQ_FIQ_STATUS);
     
@@ -100,7 +100,7 @@ bool __timer_start(void)
     return true;
 }
 
-void __timer_stop(void)
+void timer_stop(void)
 {
     int oldstatus = disable_interrupt_save(IRQ_FIQ_STATUS);
     stop_timer();
diff --git a/firmware/target/arm/tms320dm320/timer-target.h b/firmware/target/arm/tms320dm320/timer-target.h
index 9f3ffdf712..c1cf9796de 100644
--- a/firmware/target/arm/tms320dm320/timer-target.h
+++ b/firmware/target/arm/tms320dm320/timer-target.h
@@ -24,17 +24,4 @@
 /* timer is based on PCLK and minimum division is 2 */
 #define TIMER_FREQ (27000000)
 
-bool __timer_set(long cycles, bool set);
-bool __timer_start(void);
-void __timer_stop(void);
-
-#define __TIMER_SET(cycles, set) \
-    __timer_set(cycles, set)
-
-#define __TIMER_START() \
-    __timer_start()
-
-#define __TIMER_STOP(...) \
-    __timer_stop()
-
 #endif /* TIMER_TARGET_H */
diff --git a/firmware/target/coldfire/timer-coldfire.c b/firmware/target/coldfire/timer-coldfire.c
index ef9fd9ea7a..0916ebedf7 100644
--- a/firmware/target/coldfire/timer-coldfire.c
+++ b/firmware/target/coldfire/timer-coldfire.c
@@ -37,7 +37,7 @@ void TIMER1(void)
     TER1 = 0xff; /* clear all events */
 }
 
-bool __timer_set(long cycles, bool start)
+bool timer_set(long cycles, bool start)
 {
     int phi = 0; /* bits for the prescaler */
     int prescale = 1;
@@ -87,7 +87,7 @@ bool __timer_set(long cycles, bool start)
     return true;
 }
 
-bool __timer_start(void)
+bool timer_start(void)
 {
     ICR2 = 0x90;       /* interrupt on level 4.0 */
     and_l(~(1<<10), &IMR);
@@ -95,7 +95,7 @@ bool __timer_start(void)
     return true;
 }
 
-void __timer_stop(void)
+void timer_stop(void)
 {
     TMR1 = 0;               /* disable timer 1 */
     or_l((1<<10), &IMR);    /* disable interrupt */
diff --git a/firmware/target/coldfire/timer-target.h b/firmware/target/coldfire/timer-target.h
index 29488887e8..3aff57de9e 100644
--- a/firmware/target/coldfire/timer-target.h
+++ b/firmware/target/coldfire/timer-target.h
@@ -21,20 +21,7 @@
 #ifndef TIMER_TARGET_H
 #define TIMER_TARGET_H
 
-bool __timer_set(long cycles, bool start);
-bool __timer_start(void);
-void __timer_stop(void);
-
 /* timer is based on busclk == cpuclk/2 */
 #define TIMER_FREQ (CPU_FREQ/2)
 
-#define __TIMER_SET(cycles, set) \
-    __timer_set(cycles, set)
-
-#define __TIMER_START() \
-    __timer_start()
-
-#define __TIMER_STOP(...) \
-    __timer_stop()
-
 #endif /* TIMER_TARGET_H */
diff --git a/firmware/target/mips/ingenic_jz47xx/timer-jz4740.c b/firmware/target/mips/ingenic_jz47xx/timer-jz4740.c
index 8258f7b2be..c174ca6eb1 100644
--- a/firmware/target/mips/ingenic_jz47xx/timer-jz4740.c
+++ b/firmware/target/mips/ingenic_jz47xx/timer-jz4740.c
@@ -33,7 +33,7 @@ void TCU1(void)
         pfn_timer();
 }
 
-bool __timer_set(long cycles, bool start)
+bool timer_set(long cycles, bool start)
 {
     unsigned int divider = cycles, prescaler_bit = 0, prescaler = 1, old_irq;
 
@@ -79,14 +79,14 @@ bool __timer_set(long cycles, bool start)
     return true;
 }
 
-bool __timer_start(void)
+bool timer_start(void)
 {
     __tcu_start_counter(1);
 
     return true;
 }
 
-void __timer_stop(void)
+void timer_stop(void)
 {
     unsigned int old_irq = disable_irq_save();
     __tcu_stop_counter(1);
diff --git a/firmware/target/mips/ingenic_jz47xx/timer-target.h b/firmware/target/mips/ingenic_jz47xx/timer-target.h
index 2e072440ab..a305afaf8b 100644
--- a/firmware/target/mips/ingenic_jz47xx/timer-target.h
+++ b/firmware/target/mips/ingenic_jz47xx/timer-target.h
@@ -26,17 +26,4 @@
 
 #define TIMER_FREQ (CFG_EXTAL) /* For full precision! */
 
-bool __timer_set(long cycles, bool set);
-bool __timer_start(void);
-void __timer_stop(void);
-
-#define __TIMER_SET(cycles, set) \
-    __timer_set(cycles, set)
-
-#define __TIMER_START() \
-    __timer_start()
-
-#define __TIMER_STOP(...) \
-    __timer_stop()
-
 #endif /* __TIMER_H_ */
diff --git a/firmware/target/sh/archos/timer-archos.c b/firmware/target/sh/archos/timer-archos.c
index c61318f721..07d63ed3a8 100644
--- a/firmware/target/sh/archos/timer-archos.c
+++ b/firmware/target/sh/archos/timer-archos.c
@@ -32,7 +32,7 @@ void IMIA4(void)
     and_b(~0x01, &TSR4); /* clear the interrupt */
 }
 
-bool __timer_set(long cycles, bool start)
+bool timer_set(long cycles, bool start)
 {
     int phi = 0; /* bits for the prescaler */
     int prescale = 1;
@@ -71,14 +71,14 @@ bool __timer_set(long cycles, bool start)
     return true;
 }
 
-bool __timer_start(void)
+bool timer_start(void)
 {
     IPRD = (IPRD & 0xFF0F) | 1 << 4;  /* interrupt priority */
     or_b(0x10, &TSTR); /* start timer 4 */
     return true;
 }
 
-void __timer_stop(void)
+void timer_stop(void)
 {
     and_b(~0x10, &TSTR);    /* stop the timer 4 */
     IPRD = (IPRD & 0xFF0F); /* disable interrupt */
diff --git a/firmware/target/sh/archos/timer-target.h b/firmware/target/sh/archos/timer-target.h
index 89dfe57eb3..6cdd442917 100644
--- a/firmware/target/sh/archos/timer-target.h
+++ b/firmware/target/sh/archos/timer-target.h
@@ -23,19 +23,6 @@
 
 #include "config.h"
 
-bool __timer_set(long cycles, bool start);
-bool __timer_start(void);
-void __timer_stop(void);
-
 #define TIMER_FREQ CPU_FREQ
 
-#define __TIMER_SET(cycles, set) \
-    __timer_set(cycles, set)
-
-#define __TIMER_START() \
-    __timer_start()
-
-#define __TIMER_STOP(...) \
-    __timer_stop()
-
 #endif /* TIMER_TARGET_H */
diff --git a/firmware/timer.c b/firmware/timer.c
index 077176b96f..a923290a94 100644
--- a/firmware/timer.c
+++ b/firmware/timer.c
@@ -30,11 +30,6 @@ static int timer_prio = -1;
 void SHAREDBSS_ATTR (*pfn_timer)(void) = NULL;      /* timer callback */
 void SHAREDBSS_ATTR (*pfn_unregister)(void) = NULL; /* unregister callback */
 
-static bool timer_set(long cycles, bool start)
-{
-    return __TIMER_SET(cycles, start);
-}
-
 /* Register a user timer, called every <cycles> TIMER_FREQ cycles */
 bool timer_register(int reg_prio, void (*unregister_callback)(void),
                     long cycles, void (*timer_callback)(void)
@@ -50,11 +45,7 @@ bool timer_register(int reg_prio, void (*unregister_callback)(void),
     pfn_unregister = unregister_callback;
     timer_prio = reg_prio;
 
-#if NUM_CORES > 1
-    return __TIMER_START(core);
-#else
-    return __TIMER_START();
-#endif
+    return timer_start(IF_COP(core));
 }
 
 bool timer_set_period(long cycles)
@@ -64,7 +55,7 @@ bool timer_set_period(long cycles)
 
 void timer_unregister(void)
 {
-    __TIMER_STOP();
+    timer_stop();
 
     pfn_timer = NULL;
     pfn_unregister = NULL;