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author | Catalin Patulea <cat@vv.carleton.ca> | 2007-09-21 09:06:02 +0000 |
---|---|---|
committer | Catalin Patulea <cat@vv.carleton.ca> | 2007-09-21 09:06:02 +0000 |
commit | c3126e0f3c8c5c91b77d4a0383ae6dc26cdd9ebe (patch) | |
tree | 0b00e9e61bd56595fc88d27f0a404ac83bb8248a | |
parent | 2a6125946d146c0281af57814ad2121481eb5f84 (diff) | |
download | rockbox-c3126e0f3c8c5c91b77d4a0383ae6dc26cdd9ebe.tar.gz rockbox-c3126e0f3c8c5c91b77d4a0383ae6dc26cdd9ebe.zip |
m:robe 500i port: Add primitives for the SPI bus and start moving toward new-style register definitions.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@14798 a1c6a512-1295-4272-9138-f99709370657
-rwxr-xr-x | bootloader/mrobe500.c | 25 | ||||
-rw-r--r-- | firmware/SOURCES | 1 | ||||
-rw-r--r-- | firmware/export/dm320.h | 79 | ||||
-rw-r--r-- | firmware/target/arm/olympus/mrobe-500/spi-mr500.c | 77 | ||||
-rw-r--r-- | firmware/target/arm/olympus/mrobe-500/spi-target.h | 29 | ||||
-rw-r--r-- | firmware/target/arm/system-target.h | 4 |
6 files changed, 165 insertions, 50 deletions
diff --git a/bootloader/mrobe500.c b/bootloader/mrobe500.c index d0b9c2b717..3b2ede685a 100755 --- a/bootloader/mrobe500.c +++ b/bootloader/mrobe500.c | |||
@@ -38,6 +38,7 @@ | |||
38 | #include "common.h" | 38 | #include "common.h" |
39 | #include "rbunicode.h" | 39 | #include "rbunicode.h" |
40 | #include "usb.h" | 40 | #include "usb.h" |
41 | #include "spi-target.h" | ||
41 | 42 | ||
42 | void main(void) | 43 | void main(void) |
43 | { | 44 | { |
@@ -55,7 +56,7 @@ void main(void) | |||
55 | uartSetup(); | 56 | uartSetup(); |
56 | lcd_init(); | 57 | lcd_init(); |
57 | font_init(); | 58 | font_init(); |
58 | // dm320_spi_init(); | 59 | dm320_spi_init(); |
59 | 60 | ||
60 | lcd_setfont(FONT_SYSFIXED); | 61 | lcd_setfont(FONT_SYSFIXED); |
61 | 62 | ||
@@ -97,12 +98,8 @@ void main(void) | |||
97 | #endif | 98 | #endif |
98 | 99 | ||
99 | printf("ATA"); | 100 | printf("ATA"); |
100 | int count = 0, i = 0, c = 0; | ||
101 | char data[64]; | ||
102 | unsigned short out[] = {0x8000}; | ||
103 | unsigned short in[2]; | ||
104 | outw(inw(IO_GIO_DIR1)&~(1<<10), IO_GIO_DIR1); // set GIO26 to output | ||
105 | 101 | ||
102 | outw(inw(IO_GIO_DIR1)&~(1<<10), IO_GIO_DIR1); // set GIO26 to output | ||
106 | while(true) | 103 | while(true) |
107 | { | 104 | { |
108 | if (button_read_device() == BUTTON_POWER) | 105 | if (button_read_device() == BUTTON_POWER) |
@@ -110,9 +107,19 @@ void main(void) | |||
110 | printf("reset"); | 107 | printf("reset"); |
111 | outw(1<<10, IO_GIO_BITSET1); | 108 | outw(1<<10, IO_GIO_BITSET1); |
112 | } | 109 | } |
113 | // dm320_spi_block_transfer(0, out, 16, 16, in, 0); | 110 | |
114 | // printf("%x", in[0]); | 111 | // Read X, Y, Z1, Z2 touchscreen coordinates. |
115 | 112 | int page = 0, address = 0; | |
113 | unsigned short command = 0x8000|(page << 11)|(address << 5); | ||
114 | unsigned char out[] = {command >> 8, command & 0xff}; | ||
115 | unsigned char in[8]; | ||
116 | dm320_spi_block_transfer(out, sizeof(out), in, sizeof(in)); | ||
117 | |||
118 | printf("%02x%02x %02x%02x %02x%02x %02x%02x\n", | ||
119 | in[0], in[1], | ||
120 | in[2], in[3], | ||
121 | in[4], in[5], | ||
122 | in[6], in[7]); | ||
116 | } | 123 | } |
117 | #if 0 | 124 | #if 0 |
118 | rc = ata_init(); | 125 | rc = ata_init(); |
diff --git a/firmware/SOURCES b/firmware/SOURCES index e62d9331a5..3a606e5bfd 100644 --- a/firmware/SOURCES +++ b/firmware/SOURCES | |||
@@ -601,6 +601,7 @@ target/arm/olympus/mrobe-500/system-mr500.c | |||
601 | target/arm/olympus/mrobe-500/timer-mr500.c | 601 | target/arm/olympus/mrobe-500/timer-mr500.c |
602 | target/arm/olympus/mrobe-500/usb-mr500.c | 602 | target/arm/olympus/mrobe-500/usb-mr500.c |
603 | target/arm/olympus/mrobe-500/uart-mr500.c | 603 | target/arm/olympus/mrobe-500/uart-mr500.c |
604 | target/arm/olympus/mrobe-500/spi-mr500.c | ||
604 | #ifndef BOOTLOADER | 605 | #ifndef BOOTLOADER |
605 | 606 | ||
606 | #endif | 607 | #endif |
diff --git a/firmware/export/dm320.h b/firmware/export/dm320.h index 5e164cff57..f072e8975f 100644 --- a/firmware/export/dm320.h +++ b/firmware/export/dm320.h | |||
@@ -27,6 +27,7 @@ | |||
27 | #define FRAME ((short *) (0x4470000)) | 27 | #define FRAME ((short *) (0x4470000)) |
28 | 28 | ||
29 | #define PHY_IO_BASE 0x00030000 | 29 | #define PHY_IO_BASE 0x00030000 |
30 | #define DM320_REG(addr) (*(volatile unsigned short *)(PHY_IO_BASE + (addr))) | ||
30 | 31 | ||
31 | /* Timer 0-3 */ | 32 | /* Timer 0-3 */ |
32 | #define IO_TIMER0_TMMD 0x0000 | 33 | #define IO_TIMER0_TMMD 0x0000 |
@@ -58,20 +59,20 @@ | |||
58 | #define IO_TIMER3_TMCNT 0x018A | 59 | #define IO_TIMER3_TMCNT 0x018A |
59 | 60 | ||
60 | /* Serial 0/1 */ | 61 | /* Serial 0/1 */ |
61 | #define IO_SERIAL0_TX_DATA 0x0200 | 62 | #define IO_SERIAL0_TX_DATA DM320_REG(0x0200) |
62 | #define IO_SERIAL0_RX_DATA 0x0202 | 63 | #define IO_SERIAL0_RX_DATA DM320_REG(0x0202) |
63 | #define IO_SERIAL0_TX_ENABLE 0x0204 | 64 | #define IO_SERIAL0_TX_ENABLE DM320_REG(0x0204) |
64 | #define IO_SERIAL0_MODE 0x0206 | 65 | #define IO_SERIAL0_MODE DM320_REG(0x0206) |
65 | #define IO_SERIAL0_DMA_TRIGGER 0x0208 | 66 | #define IO_SERIAL0_DMA_TRIGGER DM320_REG(0x0208) |
66 | #define IO_SERIAL0_DMA_MODE 0x020A | 67 | #define IO_SERIAL0_DMA_MODE DM320_REG(0x020A) |
67 | #define IO_SERIAL0_DMA_SDRAM_LOW 0x020C | 68 | #define IO_SERIAL0_DMA_SDRAM_LOW DM320_REG(0x020C) |
68 | #define IO_SERIAL0_DMA_SDRAM_HI 0x020E | 69 | #define IO_SERIAL0_DMA_SDRAM_HI DM320_REG(0x020E) |
69 | #define IO_SERIAL0_DMA_STATUS 0x0210 | 70 | #define IO_SERIAL0_DMA_STATUS DM320_REG(0x0210) |
70 | 71 | ||
71 | #define IO_SERIAL1_TX_DATA 0x0280 | 72 | #define IO_SERIAL1_TX_DATA DM320_REG(0x0280) |
72 | #define IO_SERIAL1_RX_DATA 0x0282 | 73 | #define IO_SERIAL1_RX_DATA DM320_REG(0x0282) |
73 | #define IO_SERIAL1_TX_ENABLE 0x0284 | 74 | #define IO_SERIAL1_TX_ENABLE DM320_REG(0x0284) |
74 | #define IO_SERIAL1_MODE 0x0286 | 75 | #define IO_SERIAL1_MODE DM320_REG(0x0286) |
75 | 76 | ||
76 | /* UART 0/1 */ | 77 | /* UART 0/1 */ |
77 | #define IO_UART0_DTRR 0x0300 | 78 | #define IO_UART0_DTRR 0x0300 |
@@ -383,31 +384,31 @@ | |||
383 | #define IO_VID_ENC_ATR0 0x0854 | 384 | #define IO_VID_ENC_ATR0 0x0854 |
384 | 385 | ||
385 | /* Clock Controller */ | 386 | /* Clock Controller */ |
386 | #define IO_CLK_PLLA 0x0880 | 387 | #define IO_CLK_PLLA DM320_REG(0x0880) |
387 | #define IO_CLK_PLLB 0x0882 | 388 | #define IO_CLK_PLLB DM320_REG(0x0882) |
388 | #define IO_CLK_SEL0 0x0884 | 389 | #define IO_CLK_SEL0 DM320_REG(0x0884) |
389 | #define IO_CLK_SEL1 0x0886 | 390 | #define IO_CLK_SEL1 DM320_REG(0x0886) |
390 | #define IO_CLK_SEL2 0x0888 | 391 | #define IO_CLK_SEL2 DM320_REG(0x0888) |
391 | #define IO_CLK_DIV0 0x088A | 392 | #define IO_CLK_DIV0 DM320_REG(0x088A) |
392 | #define IO_CLK_DIV1 0x088C | 393 | #define IO_CLK_DIV1 DM320_REG(0x088C) |
393 | #define IO_CLK_DIV2 0x088E | 394 | #define IO_CLK_DIV2 DM320_REG(0x088E) |
394 | #define IO_CLK_DIV3 0x0890 | 395 | #define IO_CLK_DIV3 DM320_REG(0x0890) |
395 | #define IO_CLK_DIV4 0x0892 | 396 | #define IO_CLK_DIV4 DM320_REG(0x0892) |
396 | #define IO_CLK_BYP 0x0894 | 397 | #define IO_CLK_BYP DM320_REG(0x0894) |
397 | #define IO_CLK_INV 0x0896 | 398 | #define IO_CLK_INV DM320_REG(0x0896) |
398 | #define IO_CLK_MOD0 0x0898 | 399 | #define IO_CLK_MOD0 DM320_REG(0x0898) |
399 | #define IO_CLK_MOD1 0x089A | 400 | #define IO_CLK_MOD1 DM320_REG(0x089A) |
400 | #define IO_CLK_MOD2 0x089C | 401 | #define IO_CLK_MOD2 DM320_REG(0x089C) |
401 | #define IO_CLK_LPCTL0 0x089E | 402 | #define IO_CLK_LPCTL0 DM320_REG(0x089E) |
402 | #define IO_CLK_LPCTL1 0x08A0 | 403 | #define IO_CLK_LPCTL1 DM320_REG(0x08A0) |
403 | #define IO_CLK_OSEL 0x08A2 | 404 | #define IO_CLK_OSEL DM320_REG(0x08A2) |
404 | #define IO_CLK_00DIV 0x08A4 | 405 | #define IO_CLK_00DIV DM320_REG(0x08A4) |
405 | #define IO_CLK_O1DIV 0x08A6 | 406 | #define IO_CLK_O1DIV DM320_REG(0x08A6) |
406 | #define IO_CLK_02DIV 0x08A8 | 407 | #define IO_CLK_02DIV DM320_REG(0x08A8) |
407 | #define IO_CLK_PWM0C 0x08AA | 408 | #define IO_CLK_PWM0C DM320_REG(0x08AA) |
408 | #define IO_CLK_PWM0H 0x08AC | 409 | #define IO_CLK_PWM0H DM320_REG(0x08AC) |
409 | #define IO_CLK_PWM1C 0x08AE | 410 | #define IO_CLK_PWM1C DM320_REG(0x08AE) |
410 | #define IO_CLK_PWM1H 0x08B0 | 411 | #define IO_CLK_PWM1H DM320_REG(0x08B0) |
411 | 412 | ||
412 | /* Bus Controller */ | 413 | /* Bus Controller */ |
413 | #define IO_BUSC_ECR 0x0900 | 414 | #define IO_BUSC_ECR 0x0900 |
diff --git a/firmware/target/arm/olympus/mrobe-500/spi-mr500.c b/firmware/target/arm/olympus/mrobe-500/spi-mr500.c new file mode 100644 index 0000000000..6c0d4b5990 --- /dev/null +++ b/firmware/target/arm/olympus/mrobe-500/spi-mr500.c | |||
@@ -0,0 +1,77 @@ | |||
1 | /* | ||
2 | * SPI interface driver for the DM320 SoC | ||
3 | * | ||
4 | * Copyright (C) 2007 shirour <mrobefan@gmail.com> | ||
5 | * Copyright (C) 2007 Catalin Patulea <cat@vv.carleton.ca> | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify it | ||
8 | * under the terms of the GNU General Public License as published by the | ||
9 | * Free Software Foundation; either version 2 of the License, or (at your | ||
10 | * option) any later version. | ||
11 | * | ||
12 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
13 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
14 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
15 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
16 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
17 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
18 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
19 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
20 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
21 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
22 | * | ||
23 | * You should have received a copy of the GNU General Public License along | ||
24 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
25 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
26 | */ | ||
27 | |||
28 | #include "system.h" | ||
29 | |||
30 | #define GIO_TS_ENABLE (1<<2) | ||
31 | #define clr_gio_enable() outw(GIO_TS_ENABLE, IO_GIO_BITSET1) | ||
32 | #define set_gio_enable() outw(GIO_TS_ENABLE, IO_GIO_BITCLR1) | ||
33 | |||
34 | int dm320_spi_block_transfer(const uint8_t *tx_bytes, unsigned int tx_size, | ||
35 | uint8_t *rx_bytes, unsigned int rx_size) | ||
36 | { | ||
37 | /* Activate the slave select pin */ | ||
38 | set_gio_enable(); | ||
39 | |||
40 | while (tx_size--) | ||
41 | { | ||
42 | /* Send one byte */ | ||
43 | IO_SERIAL0_TX_DATA = *tx_bytes++; | ||
44 | |||
45 | /* Wait until transfer finished */ | ||
46 | while (IO_SERIAL0_RX_DATA & 0x100); | ||
47 | } | ||
48 | |||
49 | while (rx_size--) | ||
50 | { | ||
51 | /* Make the clock tick */ | ||
52 | IO_SERIAL0_TX_DATA = 0; | ||
53 | |||
54 | /* Wait until transfer finished */ | ||
55 | unsigned short data; | ||
56 | while ((data = IO_SERIAL0_RX_DATA) & 0x100); | ||
57 | |||
58 | *rx_bytes++ = data & 0xff; | ||
59 | } | ||
60 | |||
61 | clr_gio_enable(); | ||
62 | |||
63 | return 0; | ||
64 | } | ||
65 | |||
66 | void dm320_spi_init(void) | ||
67 | { | ||
68 | /* Set SCLK idle level = 0 */ | ||
69 | IO_SERIAL0_MODE |= (1<<10); | ||
70 | |||
71 | /* Enable TX */ | ||
72 | IO_SERIAL0_TX_ENABLE = 0x0001; | ||
73 | |||
74 | /* Set GIO 18 to output for touch screen slave enable */ | ||
75 | outw(inw(IO_GIO_DIR1)&~GIO_TS_ENABLE, IO_GIO_DIR1); | ||
76 | clr_gio_enable(); | ||
77 | } | ||
diff --git a/firmware/target/arm/olympus/mrobe-500/spi-target.h b/firmware/target/arm/olympus/mrobe-500/spi-target.h new file mode 100644 index 0000000000..ebaacb45a0 --- /dev/null +++ b/firmware/target/arm/olympus/mrobe-500/spi-target.h | |||
@@ -0,0 +1,29 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id: $ | ||
9 | * | ||
10 | * Copyright (C) 2007 by Catalin Patulea | ||
11 | * | ||
12 | * All files in this archive are subject to the GNU General Public License. | ||
13 | * See the file COPYING in the source tree root for full license agreement. | ||
14 | * | ||
15 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
16 | * KIND, either express or implied. | ||
17 | * | ||
18 | ****************************************************************************/ | ||
19 | |||
20 | #ifndef SPI_TARGET_H | ||
21 | #define SPI_TARGET_H | ||
22 | |||
23 | #include <inttypes.h> | ||
24 | |||
25 | void dm320_spi_init(void); | ||
26 | int dm320_spi_block_transfer(const uint8_t *tx_bytes, unsigned int tx_size, | ||
27 | uint8_t *rx_bytes, unsigned int rx_size); | ||
28 | |||
29 | #endif | ||
diff --git a/firmware/target/arm/system-target.h b/firmware/target/arm/system-target.h index 4e7228415d..fa63c8fb2c 100644 --- a/firmware/target/arm/system-target.h +++ b/firmware/target/arm/system-target.h | |||
@@ -93,8 +93,8 @@ static inline void flush_icache(void) | |||
93 | #endif /* CONFIG_CPU */ | 93 | #endif /* CONFIG_CPU */ |
94 | #else /* CPU_CONFIG == DM320 */ | 94 | #else /* CPU_CONFIG == DM320 */ |
95 | 95 | ||
96 | #define inw(p) (*((unsigned short*)(p + PHY_IO_BASE))) | 96 | #define inw(p) (*((volatile unsigned short*)((p) + PHY_IO_BASE))) |
97 | #define outw(v,p) (*((unsigned short*)(p + PHY_IO_BASE)) = v) | 97 | #define outw(v,p) (*((volatile unsigned short*)((p) + PHY_IO_BASE)) = (v)) |
98 | 98 | ||
99 | #endif | 99 | #endif |
100 | 100 | ||